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Modeling and Optimal Design of Nanoscale Double-Gate CMOS Devices and Technology

Permanent Link: http://ufdc.ufl.edu/UFE0024218/00001

Material Information

Title: Modeling and Optimal Design of Nanoscale Double-Gate CMOS Devices and Technology
Physical Description: 1 online resource (155 p.)
Language: english
Creator: Agrawal, Shishir
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: capacitance, design, doping, doublegate, drain, fdsoi, finfet, fringe, highk, itfet, mobility, mosfet, source, underlap, utb
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation seeks to model underlying physical effects, and gain insights into the optimal design of nanoscale Double-Gate (DG) MOSFETs, particularly the quasi-planar FinFET structure. Our work includes design of a novel FinFET-based device structure (scalable ITFET), evaluation of the suitability of high-k gate dielectrics for nanoscale FinFETs, a model for parasitic fringe capacitance in DG FinFETs, and insights on optimal source/drain (S/D) process design and carrier mobility in short-channel FinFETs. The ITFET is a recently proposed hybrid device which consists of a FinFET and planar FD/SOI MOSFET combined into a single device with a common gate. The advantage of the ITFET is that it enhances the on-state current per pitch by ~100%; its disadvantage is poor scalability. We propose a novel ITFET design which is scalable to near the end of the ITRS roadmap while still giving reasonable enhancement in on-state current (~20-35%). We perform a realistic assessment of the performance and scalability advantage of high-k dielectrics in FinFET-CMOS technology. Our results indicate that a high-k dielectric actually undermines circuit performance while giving little improvement in scalability. We conclude that high-k dielectrics are not suitable for nanoscale FinFETs. We present a physical model for fringe capacitance (Cf) in DG MOSFETs with non-abrupt S/D junctions. We model Cf in terms of the device structure and short-channel effects (SCEs). The model is implemented in our physical/process-based model, UFDG, and will enable quasi-predictive device/circuit simulations. In undoped UTB FinFETs, the lateral S/D doping profile, NSD(y), defines the tradeoff between SCEs and parasitic resistance, RS/D, via gate-source/drain underlap. We demonstrate a reverse-engineering methodology to extract NSD(y) from FinFET CGS-VGS and IDS-VGS data. The extracted NSD(y) is then used to redesign the S/D process to effect a better tradeoff between SCEs and RS/D. Finally, we discuss the degradation of mobility in short-channel FinFETs possibly due to S/D defects/dopants. We explore possible causes of the effect and make device processing suggestions to help mitigate the effect.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Shishir Agrawal.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Fossum, Jerry G.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2009-11-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0024218:00001

Permanent Link: http://ufdc.ufl.edu/UFE0024218/00001

Material Information

Title: Modeling and Optimal Design of Nanoscale Double-Gate CMOS Devices and Technology
Physical Description: 1 online resource (155 p.)
Language: english
Creator: Agrawal, Shishir
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: capacitance, design, doping, doublegate, drain, fdsoi, finfet, fringe, highk, itfet, mobility, mosfet, source, underlap, utb
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation seeks to model underlying physical effects, and gain insights into the optimal design of nanoscale Double-Gate (DG) MOSFETs, particularly the quasi-planar FinFET structure. Our work includes design of a novel FinFET-based device structure (scalable ITFET), evaluation of the suitability of high-k gate dielectrics for nanoscale FinFETs, a model for parasitic fringe capacitance in DG FinFETs, and insights on optimal source/drain (S/D) process design and carrier mobility in short-channel FinFETs. The ITFET is a recently proposed hybrid device which consists of a FinFET and planar FD/SOI MOSFET combined into a single device with a common gate. The advantage of the ITFET is that it enhances the on-state current per pitch by ~100%; its disadvantage is poor scalability. We propose a novel ITFET design which is scalable to near the end of the ITRS roadmap while still giving reasonable enhancement in on-state current (~20-35%). We perform a realistic assessment of the performance and scalability advantage of high-k dielectrics in FinFET-CMOS technology. Our results indicate that a high-k dielectric actually undermines circuit performance while giving little improvement in scalability. We conclude that high-k dielectrics are not suitable for nanoscale FinFETs. We present a physical model for fringe capacitance (Cf) in DG MOSFETs with non-abrupt S/D junctions. We model Cf in terms of the device structure and short-channel effects (SCEs). The model is implemented in our physical/process-based model, UFDG, and will enable quasi-predictive device/circuit simulations. In undoped UTB FinFETs, the lateral S/D doping profile, NSD(y), defines the tradeoff between SCEs and parasitic resistance, RS/D, via gate-source/drain underlap. We demonstrate a reverse-engineering methodology to extract NSD(y) from FinFET CGS-VGS and IDS-VGS data. The extracted NSD(y) is then used to redesign the S/D process to effect a better tradeoff between SCEs and RS/D. Finally, we discuss the degradation of mobility in short-channel FinFETs possibly due to S/D defects/dopants. We explore possible causes of the effect and make device processing suggestions to help mitigate the effect.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Shishir Agrawal.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Fossum, Jerry G.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2009-11-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0024218:00001


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1 MODELINGANDOPTIMALDESIGNOFNANOSCALEDOUBLE-GATECMOSDEVICES AND TECHNOLOGY By SHISHIR AGRAWAL A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2009

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2 2009 Shishir Agrawal

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3 To my parents and sister whose unyielding support and sacrice made this dissertation possible

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4 ACKNOWLEDGEMENTS I would like to express a deep sense of gratitude to my advisor, Dr. Jerry Fossum, for his excellent guidance and support throughout the course of this work. His knowledge, experience, and enthusiasm for the area of semiconductor devices has been invaluable in making this work a reality. I would like to thank Dr. Scott Thompson, Dr. Jing Guo, and Dr. Selman Hersheld for agreeing to be on my committee as well as for helpful discussions during my research work. I wouldliketoacknowledgeFreescaleSemiconductorandSematechInc.forprovidinguswiththe FinFET data used in this work. I especially thank Leo Mathew at Freescale and Casey Smith at Sematech for patiently answering our questions and offering invaluable suggestions about the data. I have been fortunate to have the company of my colleagues, Siddharth Chouksey, Zhichao Lu,ZhenmingZhou,DabrajSarkar,WeiminZhang,MurshedChowdhury,andSueng-HwanKim. Ithankallofthemforhelpwithtechnicalissuesaswellasfortheirgoodcompanionshipthrough theseyears.Thisworkwouldnothavebeenpossiblewithouttheunyieldingsupportandsacrice ofmyparentsandsister.Iamdeeplyindebtedtothemforthecondencetheyplacedinmeduring difcult times of my life. This work is dedicated to them. Last, but not the least, thanks go out to my wife, Shweta, for adding so much happiness and cheer to my years in graduate school.

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5 TABLE OF CONTENTS page ACKNOWLEDGEMENTS............................................................................................................4 LIST OF TABLES................................................................................................................ ..........8 LIST OF FIGURES............................................................................................................... .......10 LIST OF ABBREVIATIONS.......................................................................................................14 ABSTRACT...................................................................................................................... ............15 CHAPTER 1 INTRODUCTION............................................................................................................. 1 7 2 A NOVEL ITFET DESIGN FOR ENHANCED SCALABILITY.................................... 21 2-1 Introduction............................................................................................................... ..21 2-2 Conventional ITFET Design........................................................................................22 2-3 Scaled ITFET Design..................................................................................................23 2-4 Scalability................................................................................................................ ....24 2-5 Design Considerations.................................................................................................25 2-6 Summary.................................................................................................................... ..26 3ONTHESUITABILITYOFAHIGH-KGATEDIELECTRICINNANOSCALEFINFET CMOS TECHNOLOGY.......................................................................................................39 3-1 Introduction............................................................................................................... ..39 3-2 Device Design.............................................................................................................. 40 3-3 Simulation Setup.........................................................................................................42 3-4 Performance Projections..............................................................................................44 3-5 Scalability................................................................................................................ ....46 3-6 Summary and Discussion............................................................................................47 4 A PHYSICAL MODEL FOR FRINGE CAPACITANCE IN DOUBLE-GATE MOSFETS WITH NON-ABRUPT SOURCE/DRAIN JUNCTIONS....................................................56 4-1 Introduction............................................................................................................... ..56 4-2 Characterization of Cif................................................................................................57 4-3 Characterization of Lu and Cof...................................................................................60 4-4 Verication and Discussion.........................................................................................61 4-5 Model Implementation in UFDG (Ver. 3.8)................................................................62 4-6 Signicance of Cf for Optimal DG CMOS Design.....................................................63 4-7 Summary and Discussion............................................................................................65

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6 5 A REVERSE-ENGINEERING METHODOLOGY TO EXTRACT THE SOURCE/ DRAIN DOPING PROFILE OF NANOSCALE FINFETS FOR OPTIMAL SOURCE/ DRAIN PROCESS DESIGN................................................................................................75 5-1 Introduction............................................................................................................... .....75 5-2 Description of Reverse-Engineering Methodology........................................................76 5-3 Calibration of UFDG to C-V Characteristics (Step 1)...................................................77 5-4 Calibration of UFDG to I-V Characteristics (Step 1).....................................................78 5-5 Determination of SDE Doping Prole (Step 2)..............................................................80 5-6 Carrier Mobility Degradation in Short-Channel FinFETs..............................................81 5-7 Device Redesign for Better Ion/Ioff Tradeoff.................................................................81 5-8 Summary.................................................................................................................... .....84 6 PHYSICAL INSIGHTS ON CARRIER MOBILITIES IN SHORT-CHANNEL FINFETS.............................................................................................................. ..............108 6-1 Introduction............................................................................................................... ...108 6-2 Signicance of High Mobility for FinFET CMOS Technology...................................109 6-3 Literature Survey.......................................................................................................... 109 6-4 UFDG Calibration of Longand Short-Channel FinFETs...........................................110 6-5 Possible Explanations of the Mobility Degradation.....................................................112 6-6 Comparison of a Pragmatic FinFET Technology to Bulk Technology.....................114 6-7 Summary.................................................................................................................... ...117 7 SUMMARY AND FUTURE WORK............................................................................... 124 7-1 Summary.................................................................................................................... ...124 7-2 Future Work................................................................................................................ ..126 APPENDIX A USING TAURUS AND UFDG FOR UTB DEVICE SIMULATION...............................129 A-1 Introduction............................................................................................................... ...129 A-2 A Brief Description of Taurus and UFDG Mobility Models.......................................130 A-3 Calibration of Weak-Inversion I-V Characteristics.....................................................131 A-4 Calibration of Strong-Inversion I-V Characteristics....................................................132 A-5 Additional Note...........................................................................................................1 34 B UFDG CODE REVISIONS FOR HIGH-K DEVICE SIMULATION..............................143 B-1 Introduction............................................................................................................... .. 143 B-2 Code Revision to Account for Gate Dielectric Material..............................................143 B-3 Code Revisions for Fringe Capacitance Model...........................................................144

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7 LIST OF REFERENCES............................................................................................................ 150 BIOGRAPHICAL SKETCH......................................................................................................155

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8 LIST OF TABLES T able page 2-1Structure of conventional ITFET structure at 45nm node.................................................27 2-2Characteristics of conventional ITFET structure at 45nm node........................................27 2-3Structure of scalable ITFET structure at 45nm node.........................................................28 2-4Characteristics of scalable ITFET structure at 45nm node................................................28 2-5Structure of scalable ITFET structure at 22nm node.........................................................29 2-6Characteristics of scalable ITFET structure at 22nm node................................................29 3-1Taurus-predicted weak-inversion characteristics of pragmatic device for different values of n thickness........................................................................................................4 9 3-2Physical parameters of pragmatic and high-k device.........................................................49 3-3UFDG/Spice3-predicted propagation delays of unloaded CMOS ROs comprising pragmatic and high-k device..............................................................................................50 4-1Physical parameters of device structures used to verify fringe capacitance model...........66 4-2Effective extension length of device structures used to verify fringe capacitance model.......................................................................................................................... ........66 4-3UFDG/Spice3-predicted propagation delays of unloaded CMOS ROs comprising Device III with different spacer materials.........................................................................66 5-1Approximate device and process information available for Sematech FinFETs...............85 5-2Structural and physical parameters of Sematech FinFETs after calibration to UFDG........................................................................................................................... ......86 5-3Source/drain doping prole for Sematech n-channel FinFETs estimated using reverse-engineering methodology......................................................................................86 6-1Summary of mobility parameters of n-channel FinFETs calibrated to UFDG................118 6-2Summary of mobility parameters of p-channel FinFETs calibrated to UFDG................118 6-3Extracted mobility due to undetermined defects ( mN) for Lg=32nm as a function of temperature and inversion charge density........................................................................119

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9 6-4Possible causes and solutions to the problem of carrier mobility degradation in short-Lg FinFETs.............................................................................................................119 A-1A summary of the mobility models to be used for calibration between Taurus and UFDG........................................................................................................................... ....135

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10 LIST OF FIGURES Figure page 2-1Cross-sectional diagram of ITFET structure......................................................................30 2-2Taurus-predicted weak-inversion constituent currents of conventional ITFET.................31 2-3Taurus-predicted strong-inversion constituent currents of conventional ITFET...............32 2-4Taurus-predicted weak-inversion constituent currents of scalable ITFET with Lg = 18nm, SOI width, tSi = 10nm....................................................................................33 2-5Taurus-predicted weak-inversion constituent currents of scalable ITFET with Lg= 18nm, SOI width, tSi= 11nm.....................................................................................34 2-6Taurus-predicted weak-inversion constituent currents of scalable ITFET with Lg = 18nm, SOI width, tSi = 12nm....................................................................................35 2-7Taurus-predicted strong-inversion constituent currents of scalable ITFET with Lg= 18nm, SOI width, tSi= 10nm.....................................................................................36 2-8Taurus-predicted weak-inversion constituent currents of scalable ITFET with Lg = 9nm......................................................................................................................... ...37 2-9Taurus-predicted strong-inversion constituent currents of scalable ITFET with Lg = 9nm......................................................................................................................... ...38 3-1Taurus-predicted weak-inversion IDS-VGS characteristics of n-channel Lg= 18nm pragmatic and high-k device..............................................................................................51 3-2UFDG-predicted IDS-VGS characteristics of n-channel Lg= 18nm pragmatic and high-k device with all physical models on........................................................................52 3-3UFDG-predicted CG-VGS characteristics of pragmatic and high-k device with QM model on and off.............................................................................................................. .53 3-4UFDG-predicted IDS-VGS characteristics of n-channel Lg= 18nm pragmatic and high-k device with QM model off, RS/D= 0.....................................................................54 3-5UFDG-predicted ISD-VGS characteristics of p-channel Lg= 18nm pragmatic and high-k device with all physical models on........................................................................55 4-1Diagram of actual and simplied DG MOSFET structure................................................67 4-2Diagram of device structure portraying inner and outer fringing elds............................68

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11 4-3Taurus and model-predicted weak-inversion fringe capacitance vs. spacer permittivity.................................................................................................................. ......69 4-4Taurus and model-predicted strong-inversion fringe capacitance vs. spacer permittivity................................................................................................................... ......70 4-5Taurus and model-predicted weak-inversion fringe capacitance vs. gate height...............71 4-6Taurus and model-predicted strong-inversion fringe capacitance vs. gate height.............72 4-7Taurus and model-predicted weak-inversion fringe capacitance vs. silicon width............73 4-8UFDG-predicted CG-VGS characteristics of Device III with spacer permittivity, ksp= 1, 7.5....................................................................................................................... ...74 5-1Flowchart demonstrating reverse-engineering methodology to extract source/drain doping prole.................................................................................................................. ...87 5-2Calibration of n-channel Ninv-VGS data to UFDG.............................................................88 5-3Calibration of p-channel Ninv-VGS data to UFDG.............................................................89 5-4Calibration of UFDG to n-channel Lg= 1 m m gm/IDS 2-VGS data......................................90 5-5Calibration of UFDG to n-channel Lg = 1 m m IDS-VGS data.............................................91 5-6Channel resistance (Rch) of n-devices plotted vs. gate length, Lg.....................................92 5-7Calibration of UFDG to n-channel Lg = 75nm gm/IDS 2-VGS data....................................93 5-8Calibration of UFDG to n-channel Lg = 75nm IDS-VGS data............................................94 5-9Calibration of UFDG to n-channel Lg= 32nm IDS-VGS data (weak-inversion)................95 5-10Calibration of UFDG to n-channel Lg = 32nm gm/IDS 2-VGS data....................................96 5-11Calibration of UFDG to n-channel Lg= 32nm IDS-VGS data (strong-inversion)..............97 5-12Calibration of UFDG to p-channel Lg = 10 m m meff-Ninv data..........................................98 5-13Calibration of UFDG to p-channel Lg = 1 m m ISD-VGS data.............................................99 5-14Channel resistance (Rch) of p-devices plotted vs. gate length, Lg...................................100 5-15Calibration of UFDG to p-channel Lg= 75nm ISD-VGS data..........................................101 5-16Calibration of UFDG to p-channel Lg = 32nm (linear-scale) ISD-VGS data....................102

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12 5-17Calibration of UFDG to p-channel Lg= 32nm (log-scale) ISD-VGS data........................103 5-18Determination of NSD(y) by matching UFDGand Taurus-predicted characteristics............................................................................................................... ...104 5-19UFDG-predicted meff-Ninv for n-channel FinFETs of various Lg...................................105 5-20Taurus-predicted weak-inversion characteristics for redesigned device..........................106 5-21Extracted S/D doping prole, NSD(y), for n-channel Lg= 32nm device and projected NSD(y) for redesigned device...........................................................................................107 6-1UFDG calibration of n-channel Lg= 32nm FinFET and projection with ideal mobility parameters..................................................................................................................... ...120 6-2UFDG calibration of p-channel Lg= 32nm FinFET and projection with ideal mobility parameters..................................................................................................................... ...121 6-3UFDG-predicted meff-Ninvfor Lg= 1 m m FinFET at different temperatures....................122 6-4UFDG-predicted meff-Ninvfor Lg = 32nm FinFET at different temperatures..................123 7-1A owchart describing possible future study for FinFET source/drain design...............128 A-1A comparison of the Taurus constant mobility and velocity saturation models in weak-inversion for an abrupt junction device.................................................136 A-2Electric potential as a function of distance for abrupt junction device in weak inversion...................................................................................................................... .....137 A-3Calibration between Taurusand UFDG-predicted IDS-VGS characteristics for an abrupt junction device in weak inversion....................................................................138 A-4Electric potential as a function of distance for abrupt junction device in strong inversion...................................................................................................................... .....139 A-5Calibration between Taurusand UFDG-predicted IDS-VGS characteristics for an abrupt junction device in strong inversion.......................................................................140 A-6Calibration between Taurusand UFDG-predicted IDS-VDS characteristics for an abrupt junction device in strong inversion......................................................................141 A-7Electric potential as a function of distance for underlapped device in strong inversion...................................................................................................................... .....142 B-1Basic two-plate model of fringe capacitance...................................................................146

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13 B-2A schematic diagram of the G-S/D underlap structure along with fringe capacitance components..................................................................................................................... .147 B-3A schematic diagram of underlap structure for Cifderivation in device with SiO2dielectric..................................................................................................................... ......148 B-4A schematic diagram of underlap structure for Cif derivation in device with high-k dielectric..................................................................................................................... ......149

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14 LIST OF ABBREVIATIONS MOSFETMetal-Oxide-Semiconductor Field-Effect Transistor CMOSComplementary MOS SOISilicon-on-Insulator FDFully Depleted ITFETInverted-T FET UTBUltra-Thin Body UFDGUniversity of Florida Double-Gate SCEShort-Channel Effect DIBLDrain-Induced Barrier Lowering QMQuantum-Mechanical SDESource/Drain Extension SGSingle Gate SSubthreshold Slope

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15 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulllment of the Requirements for the Degree of Doctor of Philosophy MODELINGANDOPTIMALDESIGNOFNANOSCALEDOUBLE-GATECMOSDEVICES AND TECHNOLOGY By Shishir Agrawal May 2009 Chair: Jerry G. Fossum Major: Electrical and Computer Engineering This dissertation seeks to model underlying physical effects, and gain insights into the optimaldesignofnanoscaleDouble-Gate(DG)MOSFETs,particularlythequasi-planarFinFET structure. Our work includes design of a novel FinFET-based device structure (scalable ITFET), evaluationofthesuitabilityofhigh-kgatedielectricsfornanoscaleFinFETs,amodelforparasitic fringecapacitanceinDGFinFETs,andinsightsonoptimalsource/drain(S/D)processdesignand carrier mobility in short-channel FinFETs. The ITFET is a recently proposed hybrid device which consists of a FinFET and planar FD/SOI MOSFET combined into a single device with a common gate. The advantage of the ITFET is that it enhances the on-state current per pitch by ~100%; its disadvantage is poor scalability. We propose a novel ITFET design which is scalable to near the end of the ITRS roadmap while still giving reasonable enhancement in on-state current, Ion (~20-35%). We perform a realistic assessment of the performance and scalability advantage of high-k dielectrics in FinFET-CMOS technology. Our results indicate that a high-k dielectric actually undermines circuit performance while giving limited improvement in scalability. We conclude that high-k gate dielectrics are not suitable for nanoscale FinFETs.

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16 Wepresentaphysicalmodelforfringecapacitance(Cf)inDGMOSFETswithnon-abrupt S/D junctions. We model Cf in terms of the device structure and short-channel effects (SCEs). Themodelisimplementedinourphysical/processbasedcompactmodel,UFDG,andwillenable quasi-predictive device/circuit simulations. In undoped UTB FinFETs, the lateral S/D doping prole, NSD(y), denes the tradeoff between SCEs and parasitic resistance, RS/D, via gate-source/drain underlap. We demonstrate a reverse-engineeringmethodologytoextractNSD(y)fromFinFETCG-VGSandIDS-VGSdata.The extractedNSD(y)isthenusedtoredesigntheS/DprocesstoeffectabettertradeoffbetweenSCEs and RS/D. Finally, we discuss the degradation of mobility in short-channel FinFETs possibly due to S/Ddefects/dopants.Weexplorepossiblecausesofthephenomenonandmakedeviceprocessing suggestions to help mitigate the effect.

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17 CHAPTER 1 INTRODUCTION The Double-Gate (DG) MOSFET is considered one of the most promising technological options to replace conventional (i.e, bulk-Si and PD/SOI) technologies [1]. The primary advantage of the DG MOSFET is excellent control of short-channel effects (SCEs) [2], which makesitpotentiallyscalabletotheendoftheSIAITRSroadmap[1].Also,sincethebodyofthe DG MOSFET can be left undoped, random variation in threshold voltage and other device characteristics due to process variations can be greatly reduced [3]. The undoped body also implies high carrier mobility without the need for mobility enhancement techniques [4]. The researchdescribedhereinseekstomodelphysicaleffectsandgaininsightsintotheoptimaldesign of DG MOSFETs. In recent years, FinFET technology has been considered to be most feasible for the implementation of the DG MOSFET [5][6]. Since it is a quasi-planar technology, it is most compatiblewithtodaysstandardprocessingtechniques.OneoftherecentinnovationsinFinFET technology is the ITFET structure [7][8]. The ITFET structure consists of a planar FD/SOI MOSFETfabricatedonthethickinsulatingBOXaroundtheFinFET.TheFD/SOIMOSFETand the FinFET have a common gate, effectively forming a hybrid device. The advantage of this device is enhanced drive current per pitch (~100%), as well as to allow an analog device width as opposed to the FinFET digital width. The disadvantage of the ITFET is reduced scalability sincetheSCEsaregovernedbythesingle-gateFD/SOIMOSFET.Thus,whilethisconventional ITFET will be useful in applications where high current drive is required, like I/O and interconnect drivers, it will not be useful in extremely scaled CMOS circuits. In Chapter 2, we discuss a novel method of enhancing the scalability of the ITFET structure, while still ensuring reasonable improvement in drive current (~20-35%). We use the Taurus device simulator [9] to

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18 project the scalability and on-state current of the novel structure. Appendix A discusses the physical models used in the simulations. This scalable ITFET can be used in scaled CMOS circuits which require device ratioing, like SRAM cells. We stress, however, that the abovediscussed ITFET structures may not be appropriate for applications where considerations of device scalability and gate capacitance optimization (in addition to on-state current) are important. For these applications, the ITFET can be manufactured with the SOI ungated, thus renderingtheelectricalcharacteristicsofthedevicethesameastheFinFET.TheSOIontheBOX lends greater mechanical stability to the n, making it possible to fabricate thinner, taller ns. Since the FinFET is a novel device structure, optimal device design decisions may be different, often counterintuitive, from what we expect in conventional technology. In Chapter 3, we examine the impact of high-k gate dielectrics on the device and circuit performances of FinFET CMOS technology via physics-based device/circuit simulations. DG FinFETs are designed with high-k at the HP-45nm node of the 2005 SIA ITRS [1] (gate length, Lg = 18nm), and are compared with a pragmatic design in which the traditional SiO2/SiON gate dielectric is retained,andkeptrelativelythicktoavoidexcessivegatetunnelingcurrent.Wedesignthedevices using the Taurus device simulator [9] and use the simulation results to calibrate our physical/ process-based compact model, UFDG [10], which we use for quasi-predictive performance projections.Tosimulatedeviceswithhigh-kgatedielectricusingUFDG,wemakesomechanges in the model which are discussed in Appendix B. Whereas it is presumed that a high-k dielectric will signicantly enhance FinFET-CMOS scalability and performance, we show that there are heretofore unacknowledged compromising effects associated with it that undermine this enhancement. In fact, our results show that a high-k gate dielectric actually undermines speed performancewhilegivinglittleimprovementinscalabilityrelativetothepragmaticdesign,while the latter can be scaled, with good performance, to the end of the ITRS. We conclude that a high-

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19 k dielectric is not worthwhile given the reduced circuit performance and the technological challengesofintegratingahigh-kdielectricintotheprocessow.Webelieve,basedonourstudy, that the pragmatic approach to nanoscale DG CMOS should be taken, with good performance expected, to the end of the roadmap. NanoscaleDGMOSFETsaretypicallydesignedwithgate-source/drain(G-S/D)underlap to effect a good tradeoff between SCEs, parasitic S/D resistance (RS/D), and fringe capacitance (Cf). Underlapped DG MOSFETs are typically undoped; thus S/D dopants diffuse into the extensionsduringtheS/Dannealprocesscausinganon-abruptS/Dlateraldopingprole,NSD(y). InChapter4,wepresent,forthersttime,aphysicalmodelofCfforunderlappedDGMOSFETs with (realistic) non-abrupt NSD(y). Cf consists of two components; the inner fringe capacitance, Cif,andtheouterfringecapacitance,Cof.WerelateCifandCoftothedeviceSCEsasgovernedby the effective G-S/D underlap, LeSD. The model is veried by numerical simulations of DG MOSFETswithvaryingdeviceparametersincludingthespacerdielectricconstant.Ourmodelfor Cfisimplementedinourphysical/process-basedcompactmodel,UFDG[10].Sincethemodelis quasi-predictive, it will be useful in trading off RS/D and LeSD for optimal speed performance. InChapter5,wediscusstheproblemofS/DprocessdesignfornanoscaleFinFETswith G-S/D underlap. G-S/D underlap implies an increase in the weak-inversion effective channel length, Leff(weak) = Lg+2LeSD, while not signicantly affecting the effective channel length in strong inversion, Leff(strong)@ Lg[11]. LeSD is determined primarily by the spacer extension length, Lext, and NSD(y). An increase in LeSD implies better SCEs and also lower Cf. However, it alsoimpliesincreasedRS/D,whichresultsinreducedon-statecurrent(Ion).Thus,theS/Dprocess implies a tradeoff between SCEs and RS/D. It has also been shown [12] that it may be possible to engineer the threhold voltage,Vt, of a device by allowing controlled densities of S/D dopants to diffuseintothechannel.Tobetterunderstandtheabovedesigntradeoffs,weseektorelatetheS/D

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20 process to NSD(y). We therefore design and demonstrate a reverse-engineering methodology to extract NSD(y) from fabricated FinFET CG-VGS and IDS-VGS data. We also show how the extractedNSD(y)canbeusedtoredesigntheS/DprocesstoeffectabettertradeoffbetweenSCEs and Ion. InChapter6,wediscusstheproblemofcarriermobilitydegradationinshort-LgFinFETs, whichmayberelatedtotheS/Dprocessing.Inourwork,wehaveobservedasevere,unexplained degradation of carrier mobility in Lg<~100nm FinFETs. This effect has been reported in the literature as well [13][14][15][16]. Several possible causes for this degradation have been proposed, from Coulomb/remote Coulomb scattering due to S/D dopants to scattering due to neutral defects. We try and gain more insight into this phenomenon with a thorough literature reviewaswellasmobilitymeasurementsinshort-andlong-LgFinFETs.Basedontheseinsights, we make device processing suggestions which may lead to an improvement in mobility for short Lg FinFETs. In Chapter 7, we summarize our work and also discuss needed future work in the area of optimal FinFET design.

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21 CHAPTER 2 A NOVEL ITFET DESIGN FOR ENHANCED SCALABILITY 2-1 Introduction In FinFET technology, the vertical silicon n is very thin, and it is possible to fabricate only one n per lithographic pitch (P). Thus, there is wasted area on the thick BOX between twons.TheITFET[7][8]isarecentlyproposedhybriddevicewhichconsistsofaDouble-Gate (DG) FinFET and a single-gate (SG) planar FD/SOI MOSFET (FDFET), with all the gates common.TheideabehindtheITFET(Inverted-TFET)istointegratetheplanarFDFETwiththe FinFET to enhance the attained drive current per pitch, as well as to allow an analog device width,asopposedtotheFinFETdigitalwidth.Further,wehavediscovered[8]thattheSOIon the BOX lends mechanical stability to the n, which makes it possible to fabricate taller, thinner ns, yielding even more current per pitch. Fig. 2-1 shows a cross-sectional illustration of the ITFET structure. The sole disadvantage of the ITFET is that short-channel effects (SCEs) are governedbytheSGFDFET[17],andthelimitedSOI-UTB(ultra-thinbody)thicknessthuslimits the device scalability [7]. In this chapter, we rst examine the design and performance of a conventional ITFET at the 45nm node of the SIA ITRS [1], with a midgap metal gate on both constituent devices. We then propose a novel design to improve the scalability of the ITFET. The idea is to use different gate materials on the constituent devices, employing, in a doable technology, a higher work function for the FDFET to increase its threshold voltage (VtFD). Such design alleviates the inuenceofFDFETSCEsontheoff-statecurrent(Ioff)oftheITFET.Wedemonstratethedesign via numerical device simulations, showing that the optimal ITFET is scalable to near the end of the SIA ITRS [1] where it still yields signicant enhancement of on-state current (Ion).

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22 2-2 Conventional ITFET Design WedesignaconventionalITFET(i.e.,onewiththesamegateonbothnandFDFET)for the 45nm technology node [1] with gate length Lg = 18nm. We assume the novel processing discussed in [7] whereby the n gate extends down to the BOX to prevent prodigious leakage currentinthenbase(Fig.2-1).ThisextensionofthengatetotheBOXisrelativelythin,butit reduces the width of the planar FDFET by twice the n-base gate thickness (tgb), and yields an ITFET that essentially comprises the two constituent devices in parallel. We thus model this ITFET, per pitch, using the 2-D simulator Taurus [9], by simulating each constituent device, per unit width, and summing their predicted current-voltage characteristics multiplied by the respective widths; the n height (hSi) for the FinFET and (P wSi 2tgb) for the FDFET, where wSi is the n-UTB width. We design a near optimal Lg= 18nm FinFET which includes gate-source/drain (G-S/D) underlap [11] with an undoped UTB and midgap gate. The S/D extension length is Lext= 18 nm, andthelateraldopingstraggleintheextensionis sL=9.6 nm,givinganeffectiveunderlap(LeSD) of about 3.5nm. We choose wSi= 12nm and gate oxide thickness tox = 1.2nm for adequate SCE control(DIBL=100mV/VandS=78mV/dec).WeassumeanaspectratioofRf=hSi/wSi=4, which means hSi= 48nm. The series resistance (RS/D) for both the n and FDFET is assumed to be 80 W m m. At the assumed technology node, P = 90nm [1], and if we assume tgb = 3nm, the FDFET width is 72nm.We note that the ITFET fabrication process results in the FDFET gate length being about 20-30% longer than the gate length of the FinFET. This is due to the limited depthoffocusofthelithographictool.WethereforeassumeinournominaldesignthatLg@ 22nm for the FDFET. The underlap associated with the FDFET is the same as that of the FinFET. To determine the needed SOI width, tSi, we use the insight that for a well tempered FDFET, tSi@ Leff(weak)/5 [17], where Leff(weak)is the effective channel length in weak inversion. With

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23 Leff(weak) = Lg+ LeS+ LeD@ 29 nm, using Taurus to simulate different values of SOI width, we arriveattSi=6nm.ThedesignissummarizedinTable2-1withperformancepredictionsinTable 2-2.NoQMeffectsareturnedoninTaurusandaconstantelectronmobility( mn=300cm2/V-s)is used.Thecarriervelocitysaturationeffectisturnedoffforweak-inversionprojectionsandturned on for strong-inversion projections (Appendix A). Fig. 2-2 shows Taurus-predicted ITFET constituent currents in weak inversion while Fig. 2-3 portrays constituent currents in strong inversion.Wenotethattheenhancementindrivecurrentis~110%ascomparedtoaconventional FinFET. We also note that the IDS-VGS characteristic is smooth without any hump as may be expected from the hybrid device. We believe that the reason.for this is that both devices have pretty much the same threshold voltage. We note, however, that this device is not very scalable since the SCEs are controlled by the single gate FDFET. This is discussed in more detail in Sec. 2-4. 2-3 Scaled ITFET Design For improved n-channel ITFET scalability with undoped UTB, we propose to use a midgap metal gate on the FinFET and a p+-polysilicon gate on the FDFET. We note that this design is doable because the FinFET is gated using a thin layer of midgap metal and then capped off with polysilicon [18], which can be n-type or p-type. Therefore, it is possible to deposit p+poly on the entire device, thus dening a high work function gate on the FDFET. The high threshold voltage of the FDFET (VtFD) lets us get away with poor SCEs without impacting the Ioff. This implies more device scalability. The disadvantage of this design is that the high VtFDyields a smaller enhancement in current drive compared to that of the ITFET with a common metal gate, as described in Sec. 2-2. Via simulation, we rst design and check a so-designed ITFET at the 45nm node (i.e., Lg=18nmfortheFinFET)oftheSIAroadmap[1].Thedevicedesignassumedisthesameasforthe

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24 conventional ITFET described in Sec. 2-2 (Table 2-3) with the exception of tSi As discussed above, we can afford a much thicker tSi because of the high VtFD. We let tSi vary (10, 11, and 12nm), and simulate the designed ITFET. Taurus-predicted weak-inversion IDS-VGScharacteristics are shown in Fig 2-4 to 2-6. We observe that for tSi= 10 or 11nm, Ioff of the FinFET dominates the total Ioff of the ITFET, despite the poor subthreshold characteristics of the FDFET. However, for tSi= 12nm, Ioff of the FDFET dominates, and the ITFET shows worse subthreshold characteristics. To allow for process variations, a reasonable design should then be tSi=10-11nm. Fig. 2-7 depicts the constituent strong-inversion IDS-VGS characteristics of the scalable ITFET with tSi = 10nm and specic performance parameters are given in Table 2-4. We observe from Fig. 2-7 that the enhancement in Ion over the FinFET is predicted to be ~23%. We note that in the device-on condition (VGS = VDS = 1.0V), the constituent FDFET is biased near moderate inversion because of the high VtFD, which explains the relatively low Ion enhancement. We note again, the absence of a hump in the IDS-VGS characteristics. We believe this can be explained by the poor subthreshold slope of the constituent FDFET, which causes the FDFET componentofthecurrenttoincreaseslowerthantheFinFETcomponent.Thisbiasconditionalso implies that small uncertainties in the device structure and/or underlying physics could translate to large errors in the results. For example, an error in the quantization modeling could mean a large uncertainty in the Ion enhancement. 2-4 Scalability The scalability of both the conventional and novel ITFET designs will be ultimately limited by how thin tSi can be made, as noted in [7]. It has been shown [19] that for tSi < 4nm, VtFD increases dramatically with decreasing tSi because of the energy quantization due to the structural connement of carriers in the thin body. We therefore base our scalability estimate on the fact that it is not possible to realistically design devices with tSi < @ 5nm. It is evident that our

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25 conventional ITFET (with tSi= 6nm for Lg= 18nm) cannot be scaled far beyond this node. The advantageofthisdevice,however,isthattheimprovementincurrentdriveis @ 110%perpitchand itwillbepossibletotailorthewidthoftheFDFETinananalogfashionforoptimizedlayoutarea. For the novel ITFET design, scalability will be limited to the gate length at which Ioff(FDFET)
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26 CMOS circuitry where additional current or modest device ratioing is desirable. A possible application might be pull-down transistors in SRAM cells. A third possible design is an ITFET structure with the FDFET ungated. As discussed earlier, the SOI on the BOX lends mechanical stability to the n and makes it possible to fabricate taller, thinner ns. Thus, even with the SOI ungated, we can achieve improved current per pitch as compared to a conventional FinFET structurewithlowerRf.Thiscouldbethedesignmostusefulforthedesignoflogicdeviceswhere the optimization of gate capacitance with on-state current is crucial. 2-6 Summary Using numerical device simulations, we have examined different ITFET designs, their scalability and possible applications. We found that the conventional ITFET gives a huge (~110%) enhancement in on-state current as compared to the FinFET but has limited scalability. We then showed that a novel ITFET, designed with a p+-poly gate on the constituent planar SG FD/SOIMOSFETandamidgapgateontheDGFinFET,canpossiblybescaledtoneartheendof the SIA roadmap [1], still yielding signicant enhancement of current drive over that of the FinFET.WedemonstratedvianumericalsimulationsthataviableITFETcanbedesigneduptothe 22nmnode(Lg=9nm)with~20-35%enhancementinon-statecurrent.AthirdITFETstructureis one in which the constituent FDFET is left ungated, so that the electrical characteristics of the device are the same as the FinFET. The added mechanical stability provided to the ITFET n by the SOI covering the pitch area is a huge advantage over the conventional FinFET, making it possible to fabricate thinner, taller ns, and thus attain more current per pitch. .

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27 Table 2-1. Summary of the conventional ITFET structure at the 45nm node. The constituent devices are depicted. FinFETFDFET wSi= 12nmtSi= 6nm FG= 4.71V (midgap metal) FG= 4.71V (midgap metal) hSi= 48nmW = 72nm RS/D= 80 W-m mRS/D= 80 W-m m LgFF= 18nmLgFD= 22nm Lext= 18nmLext= 18nm sL= 9.6nm sL= 9.6nm Table2-2.Taurus-predictedcharacteristicsfortheconventionalITFET(designinTable2-1)atthe 45nm node DIBL (mV/V)S (mV/dec)Ion (A per pitch)Ioff (A per pitch)Ion enhancement (%) 110781.21 10-44 10-9109

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28 Table 2-3. Summary of the scalable ITFET structure at the 45nm node. The constituent devices are depicted. FinFETFDFET wSi= 12nmtSi= 10nm FG= 4.71V (midgap metal) FG= 5.26V (heavily doped p+ poly) hSi= 48nmW = 72nm RS/D= 80 W-m mRS/D= 80 W-m m LgFF= 18nmLgFD= 22nm tox = 1.2nmtox = 1.2nm Lext= 18nmLext= 18nm sL= 9.6nm sL= 9.6nm Table 2-4. Taurus-predicted characteristics for the scalable ITFET (design in Table 2-3) at the 45nm node DIBL (mV/V)S (mV/dec)Ion (A per pitch)Ioff (A per pitch)Ion enhancement (%) 100787.1 10-52 10-923

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29 Table 2-5. Summary of the scalable ITFET structure at its scaling limit (22nm node). The constituent devices are depicted. FinFETFDFET wSi= 5nmtSi= 5nm FG= 4.71V (midgap metal) FG= 5.26V (heavily doped p+ poly) hSi= 20nmW =33nm RS/D=80 W-m mRS/D=80 W-m m LgFF= 9nmLgFD= 11nm tox=1.2nmtox=1.2nm Lext= 9nmLext= 9nm sL= 5nm sL= 5nm Table 2-6. Taurus-predicted characteristics of a scalable ITFET (design in Table 2-5) at the 22nm node DIBL (mV/V)S (mV/dec)Ion (A per pitch)Ioff (A per pitch)Ion enhancement (%) 100783.07 10-51 10-936

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30 Figure 2-1. Cross-section of the ITFET structure, which shows the single gate FD/SOI MOSFET sandwiched between two double-gated ns, with all gates common. DG FinFET SG SOI MOSFET hSi wSi P (pitch) BOXSOI tSi Gate SiO2 Si Substrate x z structure tgb

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31 Figure 2-2. Taurus-predicted weak-inversion constituent currents of conventional ITFET with Lg= 18nm (Table 2-1 design). No QM effects are turned on, and a constant electron mobility ( mn= 300cm2/V-s) without velocity saturation is used. VGS (V)IDS (A per pitch)VDS=1V -0.2-0.10.00.10.20.30.40.50.60.70.80.9 10-1310-1210-1110-1010-910-810-710-610-510-410-310-2 FinFET FDFET ITFET

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32 0.00.10.20.30.40.50.60.70.80.91.0 0.00000 0.00005 0.00010 FinFET FDFET ITFET Figure2-3.Taurus-predictedstrong-inversionconstituentcurrentsofconventionalITFETwithLg= 18nm (Table 2-1 design).No QM effects are turned on, and a constant electron mobility ( mn= 300cm2/V-s) with velocity saturation is used.IDS (A per pitch)VGS (V) VDS=1V

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33 Figure 2-4. Taurus-predicted weak-inversion constituent currents of scalable ITFET with Lg = 18nm, tSi= 10nm (Table 2-3 design).No QM effects are turned on, and a constant electron mobility ( mn= 300cm2/V-s) without velocity saturation is used. VGS (V)IDS (A per pitch)VDS=1V -0.2-0.10.00.10.20.30.40.50.60.70.80.9 10-1210-1110-1010-910-810-710-610-510-410-310-2 FinFET FDFET ITFET

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34 Figure 2-5. Taurus-predicted weak-inversion constituent currents of scalable ITFET with Lg= 18nm, tSi= 11nm (Table 2-3 design).No QM effects are turned on, and a constant electron mobility ( mn= 300cm2/V-s) without velocity saturation is used. VGS (V)IDS (A per pitch)VDS=1V -0.2-0.10.00.10.20.30.40.50.60.70.80.9 10-1210-1110-1010-910-810-710-610-510-410-310-2 FinFET FDFET ITFET

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35 Figure 2-6. Taurus-predicted weak-inversion constituent currents of scalable ITFET with Lg = 18nm, tSi= 12nm (Table 2-3 design).No QM effects are turned on, and a constant electron mobility ( mn= 300cm2/V-s) without velocity saturation is used. VGS (V)IDS (A per pitch)VDS=1V -0.2-0.10.00.10.20.30.40.50.60.70.80.9 10-1210-1110-1010-910-810-710-610-510-410-310-2 FinFET FDFET ITFET

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36 0.00.10.20.30.40.50.60.70.80.91.0 0.00000 0.00002 0.00004 0.00006 0.00008 FinFET FDFET (tSi=10nm) ITFET Figure 2-7. Taurus-predicted strong-inversion constituent currents of scalable ITFET with Lg = 18nm, tSi= 10nm (Table 2-3 design).No QM effects are turned on, and a constant electron mobility ( mn= 300cm2/V-s) with velocity saturation is used. VGS (V)IDS (A per pitch)VDS=1V

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37 Figure 2-8. Taurus-predicted weak-inversion constituent currents of scalable ITFET with Lg= 9nm (Table 2-5 design).No QM effects are turned on, and a constant electron mobility ( mn= 300cm2/V-s) without velocity saturation is used. VGS (V)IDS (A per pitch)VDS=1V -0.2-0.10.00.10.20.30.40.50.60.70.80.9 10-1210-1110-1010-910-810-710-610-510-410-3 FinFET (W=20nm) FDFET (W=33nm) ITFET

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38 Figure 2-9. Taurus-predicted strong-inversion constituent currents of scalable ITFET with Lg= 9nm (Table 2-5 design).No QM effects are turned on, and a constant electron mobility ( mn= 300cm2/V-s) with velocity saturation is used. 0.00.10.20.30.40.50.60.70.80.91.0 0.000000 0.000010 0.000020 0.000030 0.000040 FinFET FDFET ITFET VGS (V)IDS (A per pitch)VDS=1V

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39 CHAPTER 3 ON THE SUITABILITY OF A HIGH-K GATE DIELECTRIC IN NANOSCALE FINFET CMOS TECHNOLOGY 3-1 Introduction In the nanoscale Double-Gate (DG) FinFET, control of short-channel effects (SCEs) is effected by the two, coupled gates on either side of a thin Si n. As the gate length (Lg) is scaled down,then-body(tSi)canbethinnedfurthertomaintaintheSCEcontrol, withouthavingtothin the gate dielectric (EOT, or tox) [2]. Such scaling is possible for the DG FinFET because of its zero body capacitance, which implies ideal subthreshold slope in the absence of SCEs, independent of tox. Further, bulk-inversion [20] in the undoped n-body tends to render the gate capacitance (and hence inversion-charge density and on-state current) less dependent on a nonscaled tox. This pragmatic DG-FinFET CMOS design [2] could eliminate the need to replace the traditional SiON gate dielectric with a thicker high-k material [21][22] to avoid excessive gate tunneling current in the scaled device. However, a high-k gate dielectric could offer additional advantages, and the widespread notion is that it can signicantly enhance CMOS performance as well as scalability, including DG-FinFET CMOS [23]. The possible high-k advantages include thinnereffectiveoxidethickness(EOT),whichimplieshighergatecapacitance(CG)andon-state current (Ion), as well as improved scalability. Also, the larger physical thickness (thk) of the highk dielectric reduces the parasitic gate-source/drain (G-S/D) outer-fringe capacitance [24][25]. However, there are disadvantages as well. The larger thk results in the eld-induced barrier lowering(FIBL)effect,whichsignicantlydegradesSCEcontrol[25][26].Thechannelmobility tends to be signicantly degraded [27] due to both the poor quality of the Si-high-k dielectric interfaceand,fundamentally,thelong-rangescatteringfromopticalphononsinherentlypresentin high-k insulators [28]. Further, the integration of a high-k dielectric into the CMOS process presents formidable technological challenges [21][22].

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40 Manoj and Rao [25] did a numerical simulation-based study of the impact of high-k dielectrics on nanoscale FinFET design and performance. They compared Lg = 32nm devices having different gate dielectric constants (k). They maintained the same off-state current (Ioff) in each device by reducing tSiwith increasing k to suppress FIBL. They did CMOS ring-oscillator simulations, giving good insights, and reported a modest performance enhancement for optimum k ~ 20, relative to counterpart CMOS with SiO2 gate dielectric. However, their optimal high-k device needed tSi= 6nm, as opposed to tSi= 11nm for their SiO2 device. Using such an ultra-thin Si n is not realistic at an Lg = 32nm technology node. Also, the design would notbescalable,irrespectiveofthetechnology,sincetSicannotbethinnedmuchbelow @ 5nmdue to the fundamental quantization effect on threshold voltage [19]. In this chapter, we do a more realistic assessment of high-k nanoscale DG FinFETs, comparing their projected CMOS performance with that of pragmatic DG-FinFET CMOS with SiO2(orSiON)gatedielectric.Weuseourprocess/physics-based(predictive)compactmodelfor DG MOSFETs (UFDG [10]) in Spice3, supported by a numerical device simulator (Taurus [9]). We rst design the devices at the HP-45nm technology node dened by the 2005 SIA ITRS [1], with Lg = 18nm, and project performances, noting heretofore unacknowledged compromising effects associated with the high-k dielectric in addition to those mentioned above. We then compare the scalability of the two technologies. 3-2 Device Design We rst design two Lg = 18nm DG FinFET structures using Taurus. Device I uses a relatively thick, pragmatic SiO2 gate dielectric and Device II uses a high-k gate dielectric. For Device I, we let tox = 1.2nm, thick enough to avoid excessive gate tunneling current (<100A/cm2[29]) in the HP device as specied in the ITRS [1]. To optimize the design, we incorporate a G-S/ D underlap [11] via the S/D-extension lateral doping-density prole, assumed to be gaussian:

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41 NSD(y) = NSD0exp(-y2/ sL 2). The peak doping density at the edge of the S/D contact region is assumed to be NSD0 = 1 20cm-3. For an assumed S/D extension length (Lext) of 18nm, a reasonable doping straggle sL = 9.6nm yields, according to Taurus and UFDG simulations [11], aneffectiveunderlapLeSD=3.5nm,ora(weak-inversion)effectivechannellengthLeff(weak)=Lg+ 2(3.5)nm = 25nm. We consider this NSD(y) to be near-optimal, as well as reasonable, as explained in the following section. The gate work function is assumed to be midgap (e.g., TiN [18]), with the FinFET body/channel left undoped. We specify tSi so as to obtain acceptable SCE performance,DIBL @ 100mV/VandS<90mV.Table3-1showsTaurus-predictedSCEsatroom temperature, and Ioff for (n-channel) Device I with different tSi.No QM effects are turned on in Taurusandaconstantelectronmobility( mn=300cm2/V-s)isused.Thecarriervelocity-saturation effect is turned off (Appendix A).We choose tSi = 12nm to meet the SCE specications, getting Ioff=49nA/ m m(pernheight).Westress,however,thatIoffcanbefurtherloweredbythinningtSislightly, as shown in the table; and sensitivity to typical tSi variations is acceptable [30]. The parasitic S/D series resistance, RS/D, has two main components: the extension resistance Rext and the contact resistance Rcon. We estimate Rextby numerical evaluation of ,(3-1) wherethecarriermobility m dependsonNSDviatheclassicalAroramobilitymodel[31].Forthe nFinFET, Rext is estimated to be 46 W m m. Since the ITRS at 45nm targets RS/D = 125 W-m m [1], we then assume a reasonable Rcon = 79 W m m. For the pFinFET, Eq. 3-1 yields Rext= 77 W m m. Then,againassumingRcon=79 W m m,weletRS/D=156 W m m.ThepragmaticDeviceIdesignis summarized in Table 3-2. R ext 1 qN SD y ()m N SD () t si ------------------------------------------------------yd0 L ext=

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42 Device II, with a high-k dielectric, has almost the same structure as Device I. We assume an EOT of 0.7nm, in accordance with the HP-45nm node of the ITRS [1]. The gate dielectric constant is assumed to be k = 25, corresponding approximately to HfO2 [21], and hence thk = 4.5nm. With the thin EOT, the n thickness can be relaxed to tSi= 13.2nm for the same (Tauruspredicted)IoffasDeviceI;wedothistomakeafaircomparisonofthetwoFinFETdesigns.With thethickertSi,Eq.3-1yieldsslightlylowerRext=42 W m m/70 W m mforthen/p-channelDeviceII, and so RS/D = 121 W m m/149 W m m. The high-k Device II structure is summarized in Table 3-2 also.Taurus-predictedIDS-VGScurvesofthen-channelversionsofDevicesIandIIareplottedin Fig. 3-1 for low and high VDS. Note the identical Ioff = 49nA/ m m for both devices, with Ion (for VDD = 1.0V) of Device II being only slightly higher than that of Device I. We note that these predictionsareequivocalduetoinadequatephysicalmodelinginTaurus,whichwediscussinthe next section. 3-3 Simulation Setup WeuseTaurustosimulatethebasicFinFETstructures(Table3-2),andthenusetheresults to calibrate our process/physics-based compact model, UFDG [10], which we use in Spice3 for CMOS performance projections. We are careful to avoid errors that may arise due to different physical models in Taurus and UFDG. So, we rst turn-off the quantization models, and use a constantcarriermobilityinbothTaurusandUFDG(AppendixA)toachieveagoodcalibrationin the weak-inversion region. This is necessary because the transport and quantization modeling in Taurus is, we believe, not well-suited to ultra-thin-body (UTB) devices. The calibration involves matching Taurus-predicted subthreshold characteristics by tuning in UFDG the effective G-S/D underlap (LeSD) [11]. It also involves matching Taurus-predicted weak-inversion CG-VGScharacteristics by tuning two UFDG parameters related to the parasitic G-S/D fringe capacitance (FIF=0.8,QIF=5)[24].CorrespondingtotheNSD(y)assumed,wegetfromtheUFDGcalibration

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43 LeSD = 3.5nm, as noted previously. This value of underlap has been shown to give near-optimal ring-oscillator (RO) intrinsic propagation delay for 18nm DG-FinFET CMOS [24]. Since UFDG assumes that the gate dielectric is SiO2, we made changes in the model to account for the high-k dielectric in Device II. They include modifying the dielectric constant of the gate dielectric and changes to the parasitic capacitance model (Appendix B). In addition, since UFDG does not accountfortheFIBLeffect[26],weuseasmallincreaseintheUFDGtSi(from13.2nmto14nm) to match the Taurus-predicted subthreshold characteristics for Device II. This tuning of tSi does not affect the predicted strong-inversion characteristics of the high-k device. We then use UFDG, with its physical transport and quantization modeling, to perform quasi-predictive simulations of the DG-FinFET CMOS devices and ROs. UFDG includes QMbased models for UTB effective carrier mobility ( meff) [32], quantization-dened thresholdvoltage shift ( D Vt) [19] and inversion-layer capacitance (Cinv) [33], carrier-velocity overshoot [34], and ballistic-limit current [4]. Typical values for the two meff parameters, derived from the modelverication[32],areused.Forelectronsinthen-channelDeviceIwith{110}nsurfaces, these parameters (UO = 1100cm2/V-s, Q = 0.8) yield mn(eff) = 298cm2/V-s in the on-condition (VDD = 1.0V); and for holes (UO = 190cm2/V-s, Q = 1), they yield mp(eff)=118cm2/V-s. These mobilities are consistent with measured ones in actual undoped DG FinFETs [4]. For Device II, we neglect for now any mobility degradation due to the high-k dielectric [27][28]. For convenience in the discussion of the performance projections in the next section, we collectively refer to meff[32], D Vt[19], and Cinv[33] as the QM model in UFDG. When the QM model is turned off, the quantization effects on Vtand Cinvare not modeled, and meffis replaced by a mobility ( mn= 298cm2/V-s, mp= 118cm2/V-s) with no dependence on tSi nor transverse electric eld (Ex). However, dependence on the longitudinal electric eld (Ey) through the velocitysaturation/overshoot/ballistic-limit effects [34][4] is retained.

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44 3-4 Performance Projections The IDS-VGS characteristics predicted by UFDG for the n-channel Devices I and II are shown in Fig. 3-2. We note that the predicted enhancement in Ion in the high-k Device II, relative to the pragmatic Device I, is only 10%, which is not inconsistent with the Taurus predictions in Fig. 3-1. This seems surprisingly low since EOT is 58% (0.7/1.2) thinner than tox of Device I, makingtheequivalentoxidecapacitance72%higher.Examiningourpredictions,wendthatthe reason is two-fold. First, Ex in Device II is higher, at VGS = 1.0V, because of the thinner EOT. This leads to additional CG, or Cinv, reduction due to quantization [33] [35] (i.e., the electrical connement of the inversion electrons) and hence a compromising of Ion. Fig. 3-3 shows the UFDG-predicted low-VDS intrinsic (without the parasitic G-S/D fringe capacitance) CG-VGScurves for Devices I and II, with the QM model turned on and off. In the on-condition, CGfor Device II is 71% higher than that for Device I when the QM model is turned off. However, when the QM model is turned on, CGis only 40% higher. The undermining quantization effect is, therefore, exacerbated in Device II. Second, RS/D in Device II is more detrimental. Due to the ohmicdropacrossRS,theeffectivegatebias(VGS(eff)=VGS-IonRS)intheon-conditionislower inDeviceIIbecauseofthehigherIon.TheenhancementinIonisthuscompromisedfurther.These two effects are reected well by comparing Fig. 3-2 with Fig. 3-4, where we show predicted IDSVGScharacteristicsofDevicesIandIIwiththeQMmodelturnedoffandRS/D=0.Noteherethat the predicted Ion enhancement ( @ 60%) is much higher than that in Fig. 3-2, and more in accord withtheEOT/toxratio.Theenhancementisstilllessthanthenoted72%becauseofthesignicant bulk(strong)inversion[20]inundopedDGMOSFETs,whichimpliesthattheintrinsicCGisless than the gate oxide capacitance even when QM effects are not taken into account. TheUFDG-predictedIDS-VGScharacteristicsforthep-channelDevicesIandIIareshown in Fig. 3-5. We note here that there is almost no improvement in Ion afforded by the high-k

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45 dielectric. We believe the additional compromising of the high-k enhancement in the p-channel Device II is related to the Exdependence of hole mobility. In the nFinFET, because of the high electronmobility(Table3-2),Ionis(ballistic-)limitedbytheinjectionvelocity(vinj)atthesource [4]:Ion/W=QiSvinj,whereQiSistheinversionchargedensityatthesourcewhichisenhancedby the high-k dielectric. However, in the pFinFET, the hole mobility is much lower (Table 3-2), and vinjdoesnotlimitIon.ThismeansthatIonismoredependenton mp(eff),whichisdegraded(~10%) moreinDeviceIIthaninDeviceIbecauseofthehigherEx.Thehigh-kenhancementinIonisthus further compromised in the pFinFET. Since the increase in CG yielded by the high-k dielectric (Fig. 3-3) is more than the increase in Ion (Fig. 3-2), the CV/I speed metric of Device II is actually degraded relative to pragmatic Device I. Whereas CV/I is not necessarily a reliable metric for undoped DG FinFETs [37], its implication here is borne out by results of UFDG/Spice3 unloaded CMOS-RO simulations. We consider three cases (all with equal nFinFET and pFinFET heights (i.e., device widths)becauseofthecomparablecurrentsinFigs.3-2and3-5).CaseIistherealisticcase,with the devices in Table 3-2 simulated with the QM model on and with the noted RS/D. The simulationsforthiscasepredict,asrevealedinTable3-3,thattheROwithDeviceIIactuallyhas a 6% longer propagation delay ( tpd) compared to the RO with Device I. We note also that since Ion of Device II is not signicantly improved relative to Device I, this negative relative speedprojectionresultwillnotimprovemuchwithreasonableloadcapacitance.CaseIIisanidealcase, with the QM model turned off and RS/D= 0 (as in Fig. 3-4). The simulation results for this case, also given in Table 3-3, show tpd of the Device II RO to be 19% shorter than that of the Device I RO. And, the much higher Ion of Device II for this case (Fig. 3-4) implies even better high-k performanceenhancementwithloadcapacitance.So,ideally,thehigh-kgatedielectricyieldsthe anticipated enhancement, but, realistically, this enhancement is more than negated by the QM

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46 effectsandtheniteRS/D.Togainmoreinsightonthesecompromisingeffects,weconsiderCase IIIinwhichtheQMmodelisturnedon,butwithRS/D=0.Thesimulationresultsforthiscase,in Table3-3,showthat tpdisvirtuallythesamefortheROswithDevicesIandII.Thus,considering all cases, we nd that the QM and RS/D effects both contribute signicantly to the compromising of the anticipated performance advantage afforded by the high-k dielectric. We stress that we neglectedanymobilitydegradation[27][28]duetothehigh-kdielectricinDeviceII.Wenotethat this degradation cannot be completely suppressed, even in an ideal technology, because of the fundamental long-range scattering from the optical phonons present in high-k insulators [28]. Thus, the performance of the high-k FinFETs relative to the pragmatic ones will be even worse than what we are projecting. 3-5 Scalability While speed performance is an important consideration, the primary benet of a high-k gate dielectric is generally presumed to be enhanced CMOS scalability enabled by thin EOT without excessive gate tunneling current. As we noted in Sec. 3-2, we were able to relax tSi from 12nm to 13.2nm for the same Ioff in the high-k Device II. If we assume that a minimum tSicorrelateswithaparticulartechnologynode,thenthisrelaxationoftSiaffordedbythehighk(i.e., by thinner EOT) translates to some improvement in device scalability. To quantify the improvement, and describe the actual impact of high k on scalability, we thinned tSi in Device II back to 12nm (as for Device I), and then shortened Lg (keeping the same G-S/D underlap) to match, via Taurus simulations, the SCEs of the original Device II. We found that Lg can be shortened to 16.5nm (from the original 18nm) for the same Ioff and similar SCEs. Thus, we get only about an 8% Lg-scaling boost, relative to the pragmatic Device I, from the high-k gate dielectric. The limited enhancement in scalability can be attributed to the FIBL effect [25][26], which undermines the SCE control afforded by the thin EOT and hence limits the allowed

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47 increase in tSi, or shortening of Lg, for the same Ioff. This modest scaling benet is really not worthwhile when we consider the reduced performance, as characterized in Sec. 3-4, as well as theformidabletechnologicalchallengesofintegratingahigh-kdielectricintotheprocessow.In fact,additionalsimulationsshowthatthesameSCEcontrolcanbeachievedwithDeviceIscaled to 16.5nm by merely thinning tSi from 12nm to 10.8nm. Such scaling, with the better Device I performance, seems to be the logical, pragmatic choice. 3-6 Summary and Discussion Via physics-based device/circuit simulations, we have studied the impact of a high-k gate dielectric on the performance and scalability of nanoscale DG-FinFET CMOS. We designed a high-k FinFET (Device II), and compared it with a pragmatic FinFET (Device I) having thicker (> EOT), conventional SiO2 gate dielectric at the HP-45nm node (Lg = 18nm) of the 2005 SIA ITRS.Wefoundthatthehigh-kdielectricactuallydegradesCMOS-speedperformanceduetotwo heretofore unacknowledged compromising effects of the high k. One is additional CG reduction due to quantization because of higher transverse electric eld resulting from thinner EOT; the IonenhancementexpectedforthethinnerEOTisthuscompromised.Thesecondisadditionallossof effective gate bias due to RSbecause of the higher Ion; the enhancement in Ion is thus compromised more. Further, in the pFinFET, hole mobility is degraded due to the higher transverse eld, compromising Ion even more. We stress that we have not considered any degradation in channel mobility resulting from the integration of the high-k dielectric [27][28], which will cause further loss of performance relative to the pragmatic DG FinFET. Further, highk dielectrics also suffer from reliability issues which make their integration into the process ow very challenging [36]. OurstudyfocusedontheHP-45nmnode.However,ourconclusionsareapplicabletoLOP and LSTP applications [1] as well, for which thicker SiON for Device I [2] can be used to

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48 adequately suppress gate current [29], with the n thickness scaled to meet the ITRS Ioffrequirement. Further, the conclusions remain valid for scaling DG-FinFET CMOS to the end of the ITRS, which is enabled by well-designed G-S/D underlap [11][30] in the pragmatic device [2]. Our simulation-based study did imply a small improvement in the scalability of DGFinFET CMOS due to the thinner EOT. However, given the reduced performance and the technologicalchallengesofintegratingahigh-kdielectricintotheprocessow[36],weconclude that it is not worthwhile. We believe, also based on our study, that the pragmatic approach to nanoscale FinFET CMOS should be taken, with good performance expected to the end of the ITRS.

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49 Table 3-1. Taurus-predicted weak-inversion characteristics of the pragmatic 18nm DG nFinFET (Device I) at room temperature for different values of Si-n thickness. The off-state current is given per Si-n height.No QM effects are turned on in Taurus and a constant electron mobility ( mn= 300cm2/V-s) is used. The carrier velocity saturation effect is turned off (Appendix A). tSi (nm)DIBL (mV/V)S (mV)Ioff (nA/ m m) at VDS=1.0V 1078744 11897614 121007849 1312283160 Table 3-2. Physical parameters for the pragmatic Device I and the high-k Device II. The parameters are the same for the nFinFET and pFinFET unless noted otherwise. ParameterDevice IDevice II Gate length (Lg)18nm18nm Fin thickness (tSi)12nm13.2nm Effective gate oxide thickness (EOT)1.2nm0.7nm Gate dielectric constant (k)3.925 Gate work functionmidgapmidgap S/D-extension length (Lext)18nm18nm S/D-extension doping straggle ( sL)9.6nm9.6nm S/D contact resistance (Rcon)79 W-m m79 W-m m S/D-extension resistance (Rext) for nFinFET46 W-m m42 W-m m S/D-extension resistance (Rext) for pFinFET77 W-m m70 W-m m S/D resistance (RS/D=Rext+Rcon) for nFinFET125 W-m m121 W-m m S/D resistance (RS/D=Rext+Rcon) for pFinFET156 W-m m149 W-m m Effective electron mobility in on-condition ( mneff) for nFinFET 298cm2/V-s260cm2/V-s Effective hole mobility in on-condition ( mpeff) for pFinFET 118cm2/V-s107cm2/V-s

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50 Table 3-3. UFDG/Spice3-predicted propagation delays of unloaded CMOS ring oscillators comprising pragmatic-Device I and high-k-Device II 18nm DG FinFETs, for three cases as noted. CaseDevice I tpd (ps)Device II tpd (ps)High-k tpdbenet (%) I. Realistic: QM model on, actual RS/D (Table 3-2) 1.942.06-6 II. Ideal: QM model off, RS/D= 0 0.730.59+19 III. Quasi-Ideal: QM model on, RS/D = 0 1.081.07+1

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51IDS (A/ m m)VGS (V)VDS=100mV VDS=1.0V 0.00.10.20.30.40.50.60.70.80.91.0 10-910-810-710-610-510-410-310-2 Device I Device IIFigure 3-1.Taurus-predicted IDS-VGS characteristics (per fin height) of n-channel 18nm DG FinFETs:pragmaticDeviceIandhigh-kDeviceII.NoQMeffectsareturnedon,and a constant electron mobility ( mn= 300cm2/V-s) without velocity saturation is used

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52 VGS (V)IDS (mA/ m m) 0.00.10.20.30.40.50.60.70.80.91.0 0.0 0.5 1.0 1.5 2.0 Device I Device II Figure 3-2.UFDG-predicted IDS-VGS characteristics (per fin height) of n-channel pragmatic Device I and high-k Device II. The QM model is turned on and RS/D = 125 W-m m/ 121 W-m m for Device I/II. VDS=0.1V VDS=1V

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53 VGS (V)CG (fF/ m m) 0.00.10.20.30.40.50.60.70.80.91.0 0.0 0.5 1.0 1.5 2.0 Device I w/ QM model off Device II w/ QM model off Device I w/ QM model on Device II w/ QM model on Figure 3-3. UFDG-predicted low-VDS intrinsic CGS-VGS characteristics (per n height) of nchannel pragmatic Device I and high-k Device II, with the QM model turned on and off.

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54 VGS (V)IDS (mA/ m m) 0.00.10.20.30.40.50.60.70.80.91.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Device I with QM model off, RS/D=0 Device II with QM model off, RS/D=0 VDS=0.1V VDS=1.0VFigure 3-4. UFDG-predicted IDS-VGS characteristics (per n height) of n-channel pragmatic Device I and high-k Device II. The QM model is turned off and RS/D= 0.

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55 VGS (V)ISD (mA/ m m) -1.0-0.9-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.10.0 0.0 0.5 1.0 1.5 Device I Device IIVSD=1.0V VSD=0.1VFigure 3-5.UFDG-predicted ISD-VGS characteristics (per fin height) of p-channel pragmatic Device I and high-k Device II. The QM model is turned on and RS/D = 156 W-m m/ 149 W-m m for Device I/II.

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56 CHAPTER 4 APHYSICALMODELFORFRINGECAPACITANCEINDOUBLE-GATEMOSFETSWITH NON-ABRUPT SOURCE/DRAIN JUNCTIONS 4-1 Introduction Double-Gate(DG)MOSFETstypicallyhaveundopedbodies;theyarethereforedesigned with reasonably long extensions (Lext) to prevent substantial density of source/drain (S/D) dopants in the channel. S/D dopants diffuse into the extension during the S/D implant/anneal process thereby dening the S/D lateral doping prole, NSD(y). NSD(y) can be reasonably assumedtobegaussian;NSD(y)=NSD0exp(-(y-Lext)2/ sL 2),wherey=0ischosentobetheedgeof the gate (Fig. 4-1A). Due to the relatively light doping density near the gate edges, the gate can modulate portions of the S/D extension via the inner and outer fringing elds (Fig. 4-2). This encroachment of the gate eld effect into the S/D extension causes a lengthening of the effective channellengthinweakinversion,Leff(weak),whichdenesshort-channeleffects(SCEs)[11].The SCEsofanunderlappeddevice(Fig.4-1A)withgatelength,Lg,canbecharacterizedintermsof a simplied device structure of gate length, Leff(weak)= Lg+2LeSD (Fig. 4-1B). LeSD is governed by NSD(y) and the spacer dielectric constant, ksp. LeSD is not modeled directly; it is dened and derivedbymatchingtheSCEsoftheactualdeviceinFig.4-1Atothosedenedbythesimplied device structure in Fig. 4-1B. Shorter sL implies fewer dopants in the S/D extension, which causes the inner fringing eld to penetrate further into the extension thereby lengthening LeSD. Similarly, increasing ksp causes stronger coupling between the gate and S/D extension causing a lengthening of LeSD. In strong inversion, the inversion charge in the body screens out the inner fringing eld via the short Debye length, LD (1/n)0.5, where n is the inversion charge density. Thus, the effective channel length in strong inversion (which denes on-state current) is Leff(strong) @ Lg.

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57 The G-S/D parasitic fringe capacitance, Cf, of nanoscale DG MOSFETs is a signicant CMOS speed limiter [24]. Cf consists of two components: the inner fringe capacitance, Cif, and theouterfringecapacitance,CofasreectedinFig.4-2.IthasbeenrelatedtoLeSDviamodeling thatassumesabruptS/Djunctions[24].SuchCfmodelingprovidesgoodqualitativeinsight,butis inaccurate because it approximates NSD(y) as an abrupt junction at y=LeSD in weak inversion. TheinaccuracyisduetothefactthatLeSDistheeffective gated extensionwhichdenesSCEsin the simplied structure (Fig. 4-1B). Thus, LeSD is different from the length that relates to the depletion of the S/D extension, y=Lu, in the actual structure (Fig. 4-1A), which denes Cf [24]. AccuratemodelsforCofintermsofLuarepresentedin[38]and[39],buttheydonotprovideany insight on how Lu is dened in a realistic device structure with nite sL. In this chapter, we characterize Cif and Lu in terms of LeSD and the device structure. Then, we characterize Cof in termsofLuusingthemodelingin[38].Theresultisthenacompleteaccountingfortheeffectsof thecrucialG-S/DunderlapinnanoscaleDGMOSFETs.WepresentmodelsforCifandLuinSec. 4-2 and 4-3 respectively. In Sec. 4-4, we verify our modeling by comparing predictions with numerical simulation results for varying device parameters, UTB thickness (tSi), gate oxide thickness (tox), gate height (tg), and ksp. In Sec. 4-5, we implement the model for Cf in our physical, process-based model, UFDG. In Sec. 4-6, we perform ring oscillator (RO) simulations using UFDG/Spice3 to study the signicance of ksp in dening CMOS circuit speed. 4-2 Characterization of CifFig. 4-1A depicts the actual DG MOSFET device structure.The spacer width defines the S/D extension length, Lext. Lateral S/D dopant diffusion defines a gaussian S/D profile, NSD(y), intheextensionregion.Theoriginoftheco-ordinatesystemistakentobeattheedgeofthegateoxide as shown. We assume VDS = 0 to simplify the analysis, since numerical simulation results showthatCfisonlyweaklydependentonVDS.OurCfmodelingappliestothedrainaswellasto

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58 thesource.Chargeintheextensionregion,whichgoestozero(neutrality)forincreasingy,canbe related to Cif and Cofas follows: (4-1) where FGS is the workfunction difference between the gate and S/D extension, and n(x,y) is the electron density in the extension. Further, we can write Poissons equation in the extension as: .(4-2) Wemakeareasonableassumption,basedonnumericalsimulations,thatdEx/dxisconstantinxat giveny;dEx/dx @ -Esx(y)/(tSi/2)whereEsxistheelectriceldattheextension-spacerinterfacein the x-direction. Now, we integrate Eq. 4-2 along x and y directions to get: .(4-3) WemakethereasonableassumptionthatCofisassociatedonlywiththex-componentofthe electric eld, Esx, (Fig. 4-2) which implies: .(4-4) Combining Eq. 4-1, 4-3, and 4-4 we get: .(4-5) With Ey(x, )=0 and letting we differentiate Eq. 4-5 to get V GS F GS () C if C of + () qN SD y () nxy () [] xdydx 0 = t Si 2 y 0 = = dE x dx --------dE y dy --------+ q e si -----N SD y () nxy () = dE y dy ---------x 0 = t Si 2 xdydy 0 = q e si -----N SD y () nxy () [] xdydx 0 = t Si 2 y 0 = E sx y () ydy 0 = + = e si E sx y () ydy 0 = C of V GS F GS () = E y x () E y x 0 () () xdx 0 = t Si 2 C if e si ----------V GS F GS () =E y xy () xdx 0 = t Si 2 E Y y () t Si 2 -----=

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59 a simple but physical expression for Cif: .(4-6) To characterize Cif in weak inversion (Cifw), we recognize that if the SCEs of the actual device (Fig. 4-1A) are comparable to the simplied device structure (Fig. 4-1B), the potential distributions within Lg of the two structures should also be comparable. We therefore use the 2D PoissonsolutioninweakinversionofthesimpliedstructuretoapproximatethederivativeinEq. 4-6. Recognizing that y = 0 in the actual device structure maps to y=LeSD in the simplied structure and using Yehs analysis for the latter [40], we get: (4-7) where From Eq. 4-6 and Eq. 4-7, we now have .(4-8) Eq. 4-8 is a compact relation for Cifw in terms of the device structural parameters and LeSD. It physically relates Cifw to the G-S/D underlap that governs the SCEs. In strong inversion, Ey gets screened out by free carriers in the body. This implies that the LHS of Eq. 4-6 is approximately zero, and thus Cif in strong inversion goes to Cifs= 0. dE Y y 0 = () dV GS ----------------------------2 C if e si t Si -------------= dE Y y 0 = () dV GS ----------------------------dE y t Si 2 L eSD () simplified () dV GS -----------------------------------------------------------------------------L eSD l () exp l -------------------------------------= l t Si 2 -----0.51 4 e si t ox e ox t Si -----------------+ = C ifw e si t Si L eSD l () exp 2 l ----------------------------------------------------=

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60 4-3 Characterization of Lu and CofTo characterize Cof, we rst characterize Lu, which is the depleted length of the S/D extension region; beyond Lu, towards the S/D, there is signicant free-carrier density, and so Ludenes Cof [38]. To characterize Lu, we assume the simplied picture of the inner and outer fringing eld illustrated in Fig. 4-2. We assume that the electric eld in 0Lu,whichdenesCof,isx-directional (as was assumed to get Eq. 4-4). In effect, we assume that the depletion charge in 0
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61 (via Eq. 4-11 and Eq. 4-12) is relatively weak. We therefore choose a nominal value of VGS for the purpose of evaluating Lu. For an undoped DG MOSFET with midgap gates, we choose VGS=0. Thus, noting that FGSybi for undoped bodies, we get from Eq. 4-11: .(4-13) Eq. 4-13 with the modeling in [38] analytically gives Cofw in terms of LeSD and the device structure. In strong-inversion, Cifs=0; thus Eq. 4-9 implies that Lu=0. Then, [38] denes Cofs. 4-4 Verication and Discussion To evaluate our model, we use Taurus [9] to do 2-D simulations of DG MOSFETs with differentstructures,andcompareCfpredictedbyTaurustoourmodel-predictedCf=Cif+Cof.The device structures assumed are summarized in Table 4-1. The S/D doping prole is assumed to be gaussian, NSD(y) = NSD0exp(-(y-Lext)2/ sL 2) in Fig. 4-1A; NSD0 is the peak S/D doping density and sL is the lateral doping straggle. To evaluate LeSD, we tune the Taurus-predicted SCEs of a givendevicetoourphysical/process-basedmodel,UFDG[10].UFDGmodelstheweak-inversion region of a device via an analytical solution [40] for the 2D poisson equation in the UTB of the simplied device structure in Fig. 4-1B. Table 4-2 gives LeSD evaluated for all four device structures in Table 4-1 with different ksp. Increasing Lext or reducing sL implies fewer dopants nearthegateedge.Fewerdopantsnearthegateedgeimpliesfewerfreecarriers,duetowhichthe inner fringing eld can penetrate deeper into the extension region thereby increasing LeSD. Also, as ksp increases, LeSD increases, indicating better control of the potential in a portion of the extension through the spacer. Fig. 4-3 shows Taurusand model-predicted Cf in weak inversion, Cfw vs. ksp for all four devicestructures.Weobservethatthereisgoodagreementbetweenthenumericalresultsandthe model.WealsondthatforincreasingkspandalsoforincreasingLeSD,themodelbecomesless L u e si t si C ifw ------------1 Y 0 () Y bi ------------ =

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62 accurate. We believe this is because our assumption (Fig. 4-2) that Cif and Cof are dened exclusivelybyEy(Eq.4-9)andEx(Eq.4-4),respectively,tendstobreakdown.Forincreasingkspand LeSD, the outer fringing eld tends to have a signicant Ey-component which contributes to Lu. Since Eq. 4-9 does not take this into account, it tends to underpredict Cofw. However, for reasonable DG MOSFET design where ksp= 1-7.5 and LeSD= 1-4nm, the model predictions are quite good (<~10% error). Fig. 4-4 displays Taurusand model-predicted Cf in strong inversion, Cfs vs. ksp for Device III. We observe that the model is reasonable and predicts Cfs with <~15% error. Further, we evaluate the model for different values of the device structural parameters, tg, and tSi. Fig. 4-5 and 4-6 display Cfw and Cfs respectively vs. tg for Device III; Fig. 4-7 displays Cfwvs.tSiforDeviceIII.Onthewhole,weobservethatthemodelpredictsthetrendswithrespect to the device structure reasonably well with errors <~15%. 4-5 Model Implementation in UFDG (Ver. 3.8) We implement our analytical model for Cf in our physical/process-based model, UFDG [10]. UFDG is a compact Poisson-Schrodinger solver for undoped UTB devices with regional analysesfortheweak-[40]andstrong-inversion[41]regionslinkedbya2-Dcubicsplineforthe moderate-inversion region. G-S/D underlap is modeled via different effective channel lengths for the weak-inversion (Leff(weak) = Lg+LeS+LeD) [11] and strong-inversion (Leff(strong)= Lg) [41] solutions. UFDG physically accounts for QM-based effects: increase in threshold voltage due to structural connement [19] and inversion-layer capacitance [33]. UFDG also models transport phenomena via a QM-based carrier mobility model [32], carrier temperature-dependent velocity overshoot [34], and ballistic-limited current [4]. The above modeling makes UFDG quasipredictive and hence useful for performance projections and design of nanoscale DG CMOS technology.

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63 The model implementation is done as follows. A ag (CFF) is used to turn the fringe capacitance model on (CFF = 1,2) and off (CFF = 0). When CFF = 1, the current model for Cf[24] is retained and when CFF = 2, the above-described model is used. The above-described model is for symmetrical Double-Gate (SDG) devices and should only be used as such. It can be extended for aysmmetrical Double-Gate (ADG) and FD/SOI devices in the future. The implementationisfacilitatedbytheregionalanalysesmentionedabove,withthemodelforCfw= Cifw+Cofw implemented in the weak-inversion solution and for Cfs = Cifs+Cofs implemented in the strong-inversion solution. The terminal charges dened by Cfw and Cfs are added to the intrinsic gate and source/drain charges in the weakand strong-inversion solutions respectively. The 2-D spline interpolates the terminal charges in the moderate-inversion region. Currently, UFDG(ver.3.7)implicitlyassumesthatthespacerdielectricisSiO2(ksp=3.9).Togeneralizethe model, we add a parameter for the spacer permittivity (KSP). KSP is used to dene Cofw and Cofs.Intheweak-inversionsolution,CifwiscomputedusingEq.4-8andLuiscomputedusingEq. 4-13.Equations(5),(7)and(12)in[38]deneCofwintermsofLu,tg,tox,ksp,andtheS/Dwidth, LSD. Since Cofw is a very weak function of LSD, we hard-code the value of LSD= 50nm. In the strong-inversion model for Cf, Cifs is assumed to be zero consistent with the insight in Sec. 4-2. CofsisdenedintermsofLu=0,tg,tox,ksp,andLSD=50nmusingEqs.(5),(7),and(12)in[38]. Fig. 4-8 displays UFDG-predicted CG-VGS characteristics at low and high VDS for Device III (Table4-3)withksp=1andksp=7.5.WenotethesignicanceofCfindeningCG(VGS)which underscores the need to reduce Cf for optimal CMOS speed performance. 4-6 Signicance of Cf for Optimal DG CMOS Design It has been shown [24] that Cf is a signicant speed limiter in nanoscale DG CMOS technology.Cfcanbereducedbyusingalow-kdielectricspacer,preferablyanair-spacer[42].To study the signicance of spacer material on optimal speed performance of nanoscale FinFET

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64 CMOS, we use UFDG to perform quasi-predictive ring oscillator (RO) simulations of Device III with different ksp. We assume realistic mobility parameters in UFDG (UO = 1100cm2/V-s, Q = 0.8 for nFinFET; UO = 190cm2/V-s, Q = 1 for pFinFET) which correspond to actual measured mobilities in undoped UTB FinFETs [32]. These parameters imply electron mobility, mN(eff) = 298cm2/V-s and hole mobility, mP(eff)= 118cm2/V-s in the on-condition (VDD=1V). While increasing ksp leads to increased Cf, it also leads to reduced RS/D via modulation of the carrier density in the S/D extension region by the gate-eld through the spacer. Taurus simulations of Device III with different ksp show that Ion increases by 7% and 12% when ksp is increased from ksp=1to3.9and7.5respectively.ToaccountforthiseffectinourROsimulations,wetuneRS/Din UFDG to reect the increased Ion for higher ksp. We assume RS/D = 125 W-m m [1] for ksp= 1. For the same percentage change in Ion with increasing ksp, we set RS/D = 105 W-m m for ksp= 3.9 andRS/D=90 W-m mforksp=7.5.WealsoassumeequalnFinFETandpFinFETwidthssincethe UFDG-predictedIonforbothdevicesiscomparable.Table4-3,whichdisplaystheperstagedelay tpdvs.ksp,showsthesignicanceofreducingksptoimprovecircuitperformance.Wenotethattpdreducesby~25%whenthespacermaterialischangedfromSi3N4toSiO2andby~40%whenitis changedtoair(ksp=1).WestressthatCfdoesnotscalewithLg;theimportanceofCfindening circuit speed would increase with scaling Lg. Also, the gate to S/D contact capacitance [43] has not been considered in our discussion; this would increase with reducing gate pitch and become increasingly important in dening circuit speed. Cf can also be reduced by increasing LeSD via appropriate NSD(y) design as is evident from the device designs in Table 4-1 (which also implies reduced SCEs). However, such design also increases the RS/D [11], implying lower Ion and thereby dening a design tradeoff. NSD(y) needs to be carefully engineered to effect an optimal trade-off between SCEs, Cf, and Ion. We examine this problem in Chapter 5 where we develop and demonstrate a reverse-engineering

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65 methodologytorelateNSD(y)totheS/Dprocess.BasedontheextractedNSD(y),theS/Dprocess can be redesigned to effect a better device design trade-off. 4-7 Summary and Discussion Wehavepresented,forthersttime,aphysicalmodelforparasiticfringecapacitance(Cf)inDGMOSFETswith(realistic)non-abruptsource/drainjunctions.Weevaluatedourmodelfor different device structures and found good agreement with numerical simulation results. The modelisimplementedinourphysical/process-basedmodel,UFDG.Weperformedring-oscillator simulations using UFDG in Spice3 to demonstrate the signicance of Cf in dening CMOS circuit speed. Our model will be helpful in DG MOSFET design to trade-off SCEs, on-state current and parasitic capacitance for optimal CMOS performance.

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66 Table 4-1. Physical parameters for the Device Structures I-IV ParameterDevice IDevice IIDevice IIIDevice IV Gate length (Lg) (nm)18181818 Fin thickness(tSi) (nm)10101010 Effective gate oxide thickness (EOT) (nm) 1.21.21.21.2 Gate height (tg) (nm)15151515 Gate work functionmidgapmidgapmidgapmidgap S/D peak doping density (NSD0)(cm-3) 1 10201 10201 10201 1020S/D-extension length (Lext)(nm)12121818 S/D-extension doping straggle ( sL) (nm) 87.079.67.77 Table4-2.Effectivegatedextensionlength,LeSDobtainedforDevicesI-IVfordifferentvaluesof spacer permittivity, ksp, and material. LeSD was obtained by calibrating the SCEs of a given device structure to UFDG. ksp (material)LeSD (nm) Device I LeSD (nm) Device II LeSD (nm) Device III LeSD (nm) Device IV 01.102.002.804.00 1 (Air)1.202.203.104.50 3.9 (SiO2)1.652.503.505.00 7.5 (Si3N4)2.203.004.305.60 Table 4-3. UFDG/Spice3-predicted propagation delays of unloaded CMOS ROs comprising of Device III with different spacer materials ksp (material)tpd (ps) 1 (Air)1.67 3.9 (SiO2)2.22 7.5 (Si3N4)2.78

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67LgLeSDLeSDA Figure4-1.TheactualDGMOSFETdevicestructureisportrayedinA.Thespacerwidthdenes the S/D extension length, Lext. S/D dopant diffusion denes a gaussian S/D prole, NSD(y),intheextensionregion.Bportraysthesimpliedstructurewitheffectivegate length,Leff(weak)=Lg+2LeSDusedtocharacterizetheSCEsoftheactualdevice.Note that different y coordinates are used for the actual and simplied structures. LgLextB tsitoxtgtsitoxSpacer Dopants diffused from source Dopants diffused from drain X Y Heavily Doped Source Heavily Doped Drain Gate Gate Heavily Doped Source Heavily Doped Drain Gate Gate Undoped UTB X Y

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68 tsitoxtgGateSi UTB Cif tgGate Lu Cof Source/DrainFigure 4-2. This gure portrays the fringing elds that underlie Cf. It is assumed that the inner fringing eld is predominantly y-directional while the outer fringing eld is xdirectional. The depleted length in the y-direction, Lu, is dened by Cif. Cof is then dened by Lu and the device structure, as shown. X Y

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69 kspCfw (10-16 F/ m m)Figure 4-3. Taurusand model-predicted weak-inversion fringe capacitance, Cfw v/s spacer permittivity, ksp for Device I-IV. 0.01.03.97.5 0.0 0.0 2.0 4.0 6.0 8.0 10.0 Device I (Taurus) Device I (Model) Device II (Taurus) Device II (Model) Device III (Taurus) Device III (Model) Device IV (Taurus) Device IV (Model)

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70 kspCfs (10-16 F/ m m) 0.01.03.97.5 0.0 0.0 2.0 4.0 6.0 8.0 Cfs(Taurus) Cfs(Model) Figure 4-4. Taurusand model-predicted strong-inversion fringe capacitance, Cfs v/s spacer permittivity, ksp, for Device III.

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71 0.05.010.015.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Cfw(Taurus) ksp=1 Cfw(Model) ksp=1 Cfw(Taurus) ksp=3.9 Cfw(Model) ksp=3.9 Figure 4-5. Taurusand model-predicted weak-inversion fringe capacitance, Cfw v/s gate height, tg for Device III with ksp= 1,3.9. tg(nm)Cfw (10-16 F/ m m)

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72 2.05.010.015.0 0.0 1.0 2.0 3.0 4.0 Cfs(Taurus) ksp=1 Cfs(Model) ksp=1 Cfs(Taurus) ksp=3.9 Cfs(Model) ksp=3.9 Figure 4-6. Taurusand model-predicted strong-inversion fringe capacitance, Cfs v/s gate height, tg for Device III with ksp= 1,3.9. tg(nm)Cfs (10-16 F/ m m)

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73 7.08.09.010.011.012.013.0 2.0 3.0 4.0 5.0 Cfw(Taurus) ksp=1 Cfw(Model) ksp=1 Cfw(Taurus) ksp=3.9 Cfw (Model) ksp=3.9 Figure4-7.Taurus-andmodel-predictedweak-inversionfringecapacitance,Cfwv/ssiliconwidth, tsi for Device III with ksp= 1,3.9. tsi(nm)Cfw (10-16 F/ m m)

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74 0.00.51.01.52.0 0.0 0.5 1.0 1.5 2.0 ksp=1 ksp=7.5 Figure 4-8. UFDG-predicted CG-VGS characteristics for n-channel Device III with spacer permittivity, ksp= 1, 7.5 for VDS= 0,1V.CG (10-15 F/ m m)VGS(V)VDS=1V VDS=0V VDS=1V VDS=0V

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75 CHAPTER 5 A REVERSE-ENGINEERING METHODOLOGY TO EXTRACT THE SOURCE/DRAIN DOPINGPROFILEOFNANOSCALEFINFETSFOROPTIMALSOURCE/DRAINPROCESS DESIGN 5-1 Introduction Unlike conventional bulk-CMOS devices, UTB FinFETs are typically undoped; shortchannel-effect (SCE) control is achieved by means of two gates on either side of a thin n. The undoped nature of the body implies high carrier mobility [4] and also avoids random dopant effects [3]. To prevent source/drain (S/D) dopants from intruding into the channel region during the annealing process, the device needs to be designed with reasonably long S/D extensions. As discussedinChapter4,indeviceswithgate-source/drain(G-S/D)underlaps,theeffectivechannel lengthinweakinversion,Leff(weak),islongerthanthephysicalgatelength,Lg,whiletheeffective channel length in strong inversion, Leff(strong)@ Lg. Increase in Leff(weak) is desirable because it improves SCE performance, implying lower Ioff. It also implies reduced parasitic G-S/D fringe capacitances, Cif and Cof, as modeled in Chapter 4. Leff(weak)is a function of the S/D extension length,Lext,andtheS/Ddopingstraggle, sL[11].IncreasingLextand/ordecreasing sLincreases Leff(weak). However, it also increases the parasitic S/D resistance, RS/D, implying lower on-state current (Ion) [11]. Further, dopant atoms, or ions, in the channel region of the n-channel device can cause a reduction in the threshold voltage (Vt) [12]. It has been shown [12] that it may be plausible to tailor Vt by allowing controlled densities of S/D dopants into the channel region. Clearly, the doping straggle needs to be carefully controlled to trade-off the SCEs with Ion. Tobetterunderstandtheabovedesigntradeoffs,weseektorelatetheS/DprocesstotheS/ D doping prole in the extensions and channel region. We therefore propose a reverseengineeringmethodologytoextracttheS/Dlateraldopingprole,NSD(y),fromFinFETCG-VGSand IDS-VGS data. The extracted NSD(y), for specic processes, can be used to redesign the S/D

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76 process to effect a better tradeoff between SCEs and Ion. In Sec. 5-2, we briey describe our methodology, and in subsequent sections, we demonstrate it using FinFET data from Sematech. 5-2 Description of Reverse-Engineering Methodology Our methodology consists of two steps. The rst step consists of calibrating our physical/ process-based compact model, UFDG [10], to FinFET CG-VGS and IDS-VGS data. UFDG is a quasi-predictive model which models FinFET characteristics using a small number of processdependent parameters. UFDG has physical, QM-based models for carrier mobility ( meff) [32], quantum-mechanical Vt shift [19], inversion-layer capacitance [33], velocity overshoot [34], and ballistic-limit current [4]. We turn on all these physical models for this step (QMX = QMD = 1, VO = 1, BLIM = 1). UFDG calibration helps dene the device structure and extract crucial parameters like meff and RS/D. The simple algorithm to do so is dened as follows. Step 1: Calibration of UFDG to Device Data 1.WeusetheCG-VGScharacteristicsofalong-Lgdevicetotunethenheight,hSi,effectivegate oxide thickness, EOT, and gate work function, FM. 2. We match the weak-inversion IDS-VGS characteristics by tuning the G-S/D underlap in weak inversion, LeSD [11]. The effective channel length in weak inversion is Leff(weak)=Lg+2LeSD. 3.Wenowtunethe meffparameters,UOand Q .UOisthelow-field,thick-Simobility,and Q isa tuning parameter for surface-roughness scattering.To tune UO and Q, we match the gm/IDS 2VGS curves of data with UFDG. This characteristic is virtually independent of the parasitic RS/D. 4. We tune RS/D by matching the strong-inversion low-VDS current and the linear IDS-VDScharacteristics. 5.Wethenmatchthestrong-inversion,high-VDScurrentbycalibratingthedrain-inducedcharge enhancement (DICE) [44] and velocity overshoot (VO) [34] parameters.

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77 Step 2: Matching UFDG and Taurus to Get NSD(y) UFDG does not characterize devices in terms of NSD(y); rather it uses an effective underlap, LeSD, as discussed above. (Sec. 4-1 has a more detailed discussion.) Thus, in step 2 of our methodology, we use the Taurus device simulator [9] to simulate the rened device structure, and tune NSD(y) to match the UFDG-predicted weak-inversion characteristics. We are careful to avoid errors associated with Taurus inadequate modeling of quantization and transport phenomena for ultra-thin-body (UTB) devices. Thus, we turn off QM and transport models in UFDG (QMX=QMD=0, VO=BLIM=0) and use a constant, VGS-independent meff model (tune UO to get certain meff, Q = 0). We also use a constant mobility model in Taurus and turn velocitysaturationofftoavoidmobilitymodel-relatederrorsinweak-inversion(AppendixA).Weassume that NSD(y) is gaussian, NSD(y) = NSD0exp(-y2/ sL 2). The gaussian roll-off is assumed to start at the edge of the spacer, and NSD0 is assumed from the process information. We tune sL so as to match the UFDG-predicted weak-inversion IDS-VGS characteristics. Fig. 5-1 summarizes the methodology used for the NSD(y) extraction. Starting in the next section, we demonstrate the above methodology using FinFET data from Sematech. The data consists of CG-VGScharacteristics of a Lg = 10 m m device and IDS-VGS characteristics for four different gate lengths (Lg= 10 m m, 1 m m, 75nm, 32nm). 5-3 Calibration of UFDG to C-V Characteristics (Step 1) Inthissection,weusetheCG-VGScharacteristicsofaLg=10 m mdevice,withnumberof ns, Nf= 200, to rene the device structural parameters: hSi, EOT, and FM. The preliminary process information provided to us is given in Table 4-1. Thus, we calculate the inversion charge density,

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78 (5-1) andmatchittoUFDG-predictedNinv-VGSdata.Figs.5-2and5-3showthematchfornMOSand pMOS respectively. Interestingly, we find that usinghSi = 40nm (as given), leads to needed tuning of FM= 4.3V for nMOS and FM= 4.8V for pMOS to match the charge level. This is not physical because the gate metal (TiN) used for both devices is the same and is known to be near midgap. Also, it is not possible to match the slope of the Ninv-VGS data by tuning EOT ~ 1.21.4nm(asgiven).Thus,wetunehSi=60nmandEOT=1.2nmsoastoadequatelymatchtheslope ofthegraph(alsoinFigs.5-2and5-3)aswellasobtainareasonable FM(4.5VfornMOS,4.55V for pMOS). We renormalize all the IDS-VGS data, which was given to us per unit device width (=Nf hSi as noted) to reect the calibrated value of hSi. 5-4 Calibration of UFDG to I-V Characteristics (Step 1) We now calibrate UFDG to the Lg = 1 m mIDS-VGS data. We tune the weak-inversion characteristics by tuning FM. We then tune the UFDG [10] mobility parameters, UO = 900cm2/ V-s and Q = 0.32, by matching the gm/IDS 2-VGS characteristics, shown in Fig. 5-4 for n-channel Lg = 1 m m.Fig. 5-5 shows the measured and UFDG-predicted IDS-VGS characteristics of the nchannel Lg=1 m m device. The high-VDS current does not match because UFDG, which is primarily aimed at nanoscale devices, does not model the effect of meff increasing towards the drain end of the channel in long-Lg devices due to decreasing transverse electric eld. The short-Lg devices display a degradation in meff as compared to the long Lg = 1 m m device. This is evident from the channel resistance, Rch, versus Lg plot (Fig. 5-6). This effect has been observed in earlier work [13][14][15][16], and we will discuss it in Sec. 5-6, and in greater N inv V GS () C G V GSd0 V GSqh Si N f L g---------------------------------------=

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79 detail in Chapter 6. For Lg = 75nm, we obtain UO = 350cm2/V-s and Q = 0.2, by matching the gm/IDS 2-VGS graph as illustrated in Fig. 5-7. Having determined the meff parameters, we match (very well) the linear-region current by tuning RS/D= 100 W-m m, as shown in Fig. 5-8. For high VDS,thereissignicantdiscrepancybetweenthemeasuredandpredictedcurrentinthehigh-VGSregion.Weattributethistoself-heatingofthedevice,whichreducesmobilityandcurrent.TheLg= 32nm device shows signicant, but not excessive, short-channel effects (see Fig. 5-9). We therefore tune short-channel effects (SCEs) using effective underlap, LeSD= 9.25nm, so that the effective channel length in weak inversion is Leff(weak)= Lg+2LeSD; in strong inversion, Leff(strong)=Lg.Thegm/IDS 2calibration,showninFig.5-10,givesUO=110cm2/V-sand Q =0.2, and the linear IDS-VGS calibration, shown in Fig. 5-11, gives RS/D= 120 W-m m. Again the measured and UFDG-predicted characteristics match well, except for the self-heating effect. For the p-channel Lg=1 m m device, the meff parameters obtained from the gm/IDS 2-VGScalibration do not provide a good IDS-VGSmatch. We think this is because RS/D is high and is a functionofVGSinthep-channeldevices,implyingthatgm/IDS 2-VGSisnotindependentofRS/D. Thus, we instead used a split-CV measurement on the Lg=10 m m device to calibrate the meffparameters, UO = 205cm2/V-s, Q = 0.2 (Fig. 5-12). The corresponding IDS-VGS match is shown in Fig. 5-13. The Rch vs. Lg plot (Fig. 5-14) suggests little or no meff degradation for Lg = 75nm, but huge degradation for Lg = 32nm. Thus, we use UO = 205cm2/V-s and Q = 0.2 for calibration totheLg=75nmdevice,andtuneRS/D=250 W-m mtomatchthelinear-regioncurrent,asshown in Fig. 5-15. We see discrepancy between the measured and predicted linear-region characteristics,whichconrmsourinsightthatRS/DisvaryingwithVGS.ForincreasingVGS,the gate induces free carriers in the extension via the outer fringing eld through the spacer, thereby reducing the extension resistance and therefore, RS/D. This effect can be signicant in devices withlongG-S/Dunderlapsincethelightlydopedextensionimpliesthatgate-inducedfreecarriers

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80 would contribute signicantly to the extension resistance. We are unable to tune the meffparameters for Lg= 32nm since, as discussed above, gm/IDS 2-VGS is not independent of RS/D. However,ifweletRS/D=250 W-m m(ascertainedfromLg=75nm),wecantuneUO=90cm2/V-s to approximately match the strong-inversion characteristics, as shown in Fig. 5-16. We note a signicant self-heating related discrepancy between the Lg = 32nm data and the model at high VGS, VDS = 1V. The discrepancy is less pronounced than in n-channel devices due to the lower IDS in p-channel devices. Also, the weak-inversion calibration, illustrated in Fig. 5-17, yields an underlap of LeSD= 8.0nm. 5-5 Determination of SDE Doping Prole (Step 2) We now seek to estimate NSD(y) of the n-channel FinFETs. To estimate NSD(y), we match the short-channel effects of the Lg= 32nm device with a Taurus-simulated device of the refinedstructure(Table5-2).WeusetheUFDGmodelcardobtainedfromcalibrationoftheLg= 32nm device, turn the QM and transport models off and use a constant, VGS-independent meff = 107cm2/V-s (corresponding to UO = 110cm2/V-s). We use a constant mobility model with velocity saturation and QM models off in Taurus as well (Appendix A). We assume a gaussian dopingprofileandestimatethatNSD0~1 20cm-3.Wethentune sL=20nminTaurustomatch (very well) the UFDG-predicted SCEs, as indicated in Fig. 5-18. Since we recognize that our estimate of NSD0 is subject to error, we repeat this procedure for several values of NSD0 near the nominal value. Table 5-3 indicates the different combinations of NSD0 and sL which would give the predicted SCEs. We find that for reasonable perturbations about NSD0~1 20cm-3, sLvaries by ~+/-10%. We repeat the above procedure for the p-channel devices and obtain sL = 22nm corresponding to NSD0= 1 20cm-3.

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81 5-6 Carrier Mobility Degradation in Short-Channel FinFETs Fig. 5-19 shows the UFDG-predicted meff-Ninv for devices of all three gate lengths. We note that there is some degradation in meff for Lg= 75nm and huge degradation for Lg= 32nm. One possible explanation for this effect is that it may be caused by Coulomb scattering; either dopants in the channel, or long-range Coulomb scattering from the S/D. However, Fig. 5-19 shows that the degradation is almost independent of the inversion charge density, Ninv. This is inconsistent with the Coulomb scattering explanation because Coulomb scattering tends to get screenedoutathighNinv.Also,thedopingproleextractedinSec.5-5impliesaverylowdopant density, ~5 1017 cm-3 at the edge of the channel. This dopant density would not explain the strong meffdegradationviaCoulombscattering.Recentworks[13][14]attributethisshort-Lgmeffdegradation to neutral defects associated with the S/D, but there is no insight on what may be the nature of these defects; [13] also suggests that meff improves with an increase in annealing temperature. We will discuss this effect in more detail in Chapter 6, and offer suggestions to diagnose and possibly mitigate the meff degradation. For now, we note that meff is probably dependent on the S/D process, and a more comprehensive study should examine the effects of different S/D processes on meff. 5-7Device Redesign for Better Ion/Ioff Tradeoff UsingourUFDG-datacalibrationsandobservations,weattaingoodinsightsintoFinFET design. We observed in Section 5-4 that LeSD= 9.25nm/8.0nm for the n/p-channel devices. This implies excellent SCEs as demonstrated in Figs. 5-9 and 5-17. However, it also leads to large RS/D=120/250 W-m mforthen/p-channeldevices.Forhigh-performance(HP)design,thedevice can be redesigned to effect a better tradeoff between Ion and SCEs [11]. This can be achieved by using a shorter spacer (Lext @ 50nm for the actual FinFETs) and/or increasing the annealing time/ temperature to allow more dopants in the S/D extension (SDE), and perhaps a controlled number

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82 of dopants in the channel. A higher doping density in the SDE would reduce Leff(weak), thereby degrading SCEs in weak inversion. However, in strong inversion, Leff(strong)@ Lg and a higher doping density in the SDE would imply higher carrier density, thereby reducing RS/D. Also, S/D dopants in the channel would imply a reduction in the strong-inversion Vt, causing more Ionenhancement [12]. To prevent reduction in the weak-inversion Vt and avoid random dopant uctuations, we must ensure that the doping density in the center of the channel < @ 5 1017 cm-3[12]. BasedonourestimatedNSD(y),NSD0=1 1020cm-3and sL=20nmforthenFinFET,we use Taurus to estimate the spacer width, Lext, that would give reasonable SCEs (DIBL < 100mV/ V and S < 80mV) and Ioff< @ 100nA/ m m. We project that reducing the spacer width to Lext = 40nmwouldyieldreasonableSCEs(DIBL=85mV/V ,S=73mV)andgiveIoff@ 100nA/ m m.The reason for the relatively high Ioff is that the gate work function is ~100mV below midgap ( FM = 4.5V).TheresultinghigherdopingdensityintheextensionwouldsignicantlyreduceRS/D.Fig. 5-20 demonstrates Taurus-predicted weak-inversion IDS-VGS characteristics for the redesigned device (Lext= 40nm). We calibrate the weak-inversion characteristics of the redesigned device to UFDG to obtain LeSD= 4.5nm (instead of LeSD= 9.25nm for the actual device), which implies Leff(weak) = Lg+2LeSD = 41nm. The value of Leff(weak) is consistent with the thumb rule that for reasonable SCEs, tSi/Leff(weak)@ 0.5. We note from Fig. 5-20 that Ioff increases by almost two ordersofmagnitude(from @ 2nA/ m mto @ 100nA/ m m)intheredesigneddeviceascomparedtothe nominal device. Fig. 5-21 portrays our estimated NSD(y) for the actual device and also the projected NSD(y) for the redesigned device (Lext= 40nm). The projected doping density in the center of the channel for the redesigned device is @ 8 1016 cm-3; this should avoid excessive random dopant uctuations [12].

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83 Since the redesigned device has more dopants in the extension region, the extension resistance(Rext)willbereducedresultinginlowerRS/D.Itisdifculttoestimatethereductionin RS/DintheredesigneddevicesincethatwoulddependontherelativecontributionsofRextandthe other RS/D components, primarily the contact resistance, Rcon. To quantify the Ion/Ioff tradeoff, deviceswithdifferentLextshouldbefabricatedaspartofamorecomprehensivestudy.Weoutline such a study in Sec. 7-2 that would provide a clearer picture into the S/D design tradeoffs for optimal FinFET design. To get a sense of the typical Ion/Ioff tradeoff at Lg = 32nm, we consider the Lg = 30nm bulk device in [45]. Fig. 3 in [45] shows that an increase in Ioff from ~1nA/ m m to 100nA/ m m leads to ~30% increase in Ion (from ~1.2mA/ m m to 1.55mA/ m m). We recognize that the comparison between a bulk device and a FinFET is not exact, but the above illustration does imply a crude estimate of the improvement in Ion corresponding to the increased Ioff. S/Ddopantsinthechannelcancauseareductioninthestrong-inversionthresholdvoltage (Vts) and therefore enhanced Ion. The reduction in Vts ( D Vts) can be estimated [12] using the average doping density in the channel (5-2) where .(5-3) Fortheredesigneddevice(Lext=40nm),weuseEq.5-2andEq.5-3toestimateanegligible D Vts@ -30mV.Thenegligible D VtscanbeattributedtothelongLeSD=4.5nmneededtocontrolSCEs; forHPdevices,ashorterLeSD@ 1-2nmmaybedesirable.Forawell-tempereddevicewithshorter LeSD, tSi should be scaled down for better SCE control. For example, if the device is designed withLeSD=2nm,Leff(weak)=Lg+2LeSD=36nmwhichwouldimplytSi~0.5Leff(weak)=18nm.A D V ts @ qN SD t Si 2 C ox ---------------------- N SD 1 L g -----N SD y () y d 0 L g@

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84 shorterLeSDwouldallowshorterLextwhichwillimplyhigher D VtsandgreaterreductioninRS/Dleading to more enhancement in Ion. The meff-degradation effect has important consequences for the design of short-LgFinFETs. The severe degradation in meff undermines an important benet of FinFET scaling and raises questions about the viability of nanoscale FinFET technology, especially for HP logic applications. Reducing Lext in order to improve Ion as suggested above would increase the proximity of the channel to the S/D, potentially causing even worse meff degradation. This might thenimplyatradeoffbetween meffandRS/D.Weanalyzethe meffdegradationeffectinmoredetail in Chapter 6 and offer suggestions in Sec. 6-5 to diagnose and possibly mitigate it. 5-8 Summary In this Chapter, we developed a reverse-engineering methodology to extract the source/ drain doping prole from the I-V and C-V characteristics of nanoscale FinFETs. We demonstratedthemethodologyusingFinFETdatafromSematech.Basedontheextracteddoping prole, we provided insights on device redesign for better Ion/Ioff tradeoff. The reverseengineeringmethodologydiscussedinthischaptercanbeusedinamorecomprehensivestudyof optimalS/DprocessdesignfornanoscaleFinFETs.Wealsonotedtheunexplaineddegradationof carrier mobility in short-Lg FinFETs (Fig. 5-19) which is possibly related to S/D processing. We discuss the signicance and possible causes of this effect in Chapter 6 and propose solutions to possibly mitigate it.

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85 Table 5-1. Approximate device and process information available for Sematech nand p-channel FinFETs Device Physical Parameter NameDevice Physical Parameter Value Physical gate length, Lg~1 m m, ~75nm, ~32nm Fin width, wSi~20nm Effective oxide thickness, EOT~1.2-1.4nm High-k dielectric, K~15 Fin height, hSi~40nm Gate work function, FMnear midgap Channel dopingUndoped Surface orientation{110} Spacer width, Lext~50nm Spacer materialSi3N4Peak S/D doping density, NSD0~1 20cm-3Source/drain implant dose (As/B)3 15cm-2Source/drain implant energy35 keV/4 keV for As/B at 0o tilt Source/drain anneal1070oC spike anneal (4 sec for nMOS, 1 sec for pMOS)

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86 Table 5-2. Device structural and physical parameters obtained after calibration of CG-VGS and IDS-VGS data to UFDG Device Physical Parameter NameDevice Physical Parameter Value Physical gate length, Lg1 m m75nm32nm UFDG mobility parameters (n-channel)UO = 900 Q = 0.32 UO = 350 Q = 0.2 UO = 110 Q = 0.2 UFDG mobility parameters (p-channel)UO = 205 Q = 0.2 UO = 205 Q = 0.2 UO ~ 90 Q ~ 0.2 S/D resistance (RS/D) (n-channel) ( W-m m)100120 S/D resistance (RS/D) (p-channel) ( W-m m)250~250 Fin width, wSi (nm)202020 Effective oxide thickness, EOT (nm)1.21.21.2 Fin height, hSi (nm)606060 Gate work function, FM4.54.54.5 Channel dopingUndopedUndopedUndoped Spacer width, Lext (nm)~50~50~50 Spacer materialSi3N4Si3N4Si3N4Peak S/D doping density, NSD0 (cm-3)~1 20~1 20~1 20Table 5-3. This table portrays the estimated doping proles, NSD(y), which would match the SCEsofthen-channelLg=32nmdevice.NSD0isthepeakdopingdensityand sListhe doping straggle. Peak Doping density, NSD0Doping straggle sL (nm) 8 1921 1 2020 2 2018

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87 Calibrate CG-VGS and IDS-VGS data to UFDG with all physical models turned on (QMX=QMD=1, VO=1, BLIM=1). 1.Renebasicdevicestructure(hSi, FM,EOT,Lg) 2. Extract important physical parameters ( meff, RS/D, LeSD) 1. Turn quantization and transport models off in UFDG (QMX=QMD=VO=BLIM=0) and Taurus. Use constant mobility model in both. 2.SimulatereneddevicestructureinTaurus;tune NSD(y) to match UFDG predicted weak-inversion characteristics. Start End Figure5-1.Theaboveowchartdemonstratesthereverse-engineeringmethodologytoextractthe source/drain doping prole, NSD(y), from FinFET CG-VGS and IDS-VGScharacteristics.

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88 Figure5-2.CalibrationofUFDGton-channel(Lg=10 m m)Ninv-VGSdatafortwodifferentvalues of hSi. Here, Ninv was calculated using CG-VGS data and Eq. 5-1. 0.00.51.01.5 0.0e+00 5.0e+12 1.0e+13 1.5e+13 2.0e+13 nMOS data w/ hSi=40nm UFDG:FM=4.3V, EOT=1.2nmnMOS data w/ hSi=60nm UFDG:FM=4.5V, EOT=1.2nm VGS (V)Ninv (cm-2)

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89 Figure5-3.CalibrationofUFDGtop-channel(Lg=10 m m)Ninv-VGSdatafortwodifferentvalues of hSi. Here, Ninv was calculated using CG-VGS data and Eq. 5-1. -1.5-1.0-0.50.0 0.0e+00 1.0e+13 2.0e+13 3.0e+13 pMOS data w/ hSi=40nm UFDG: FM=4.8, EOT=1.2nm pMOS data w/ hSi=60nm UFDG: FM=4.55, EOT=1.2nm Ninv (cm-2)VGS (V)

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90 0.70.80.91.01.11.21.31.41.5 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 Lg=1 m mdata UFDG UO=900Q=0.32 Figure 5-4. Measured and UFDG-predicted low VDS, gm/IDS 2 vs. VGS used to tune the UFDG mobility parameters: UO = 900cm2/V-s, Q = 0.32 for the Lg= 1 m m nFinFET.VGS (V)gm/IDS 2 (106m m/W)VDS=0.05V

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91 0.00.51.01.5 0.00000 0.00010 0.00020 0.00030 0.00040 0.00050 Lg=1 m mdata UFDG Figure 5-5. Lg = 1 m m nFinFET IDS-VGS data, with corresponding UFDG calibration results. The meffparametersextracted,viagm/IDS 2-VGSinFig.5-4(UO=900cm2/V-s, Q =0.32) were used in the calibration.VGS (V)IDS (A/ m m)VDS=1V VDS=0.05V

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92 Figure 5-6. Channel resistance of n-devices, Rch (VGS= 1V, VDS = 0.05V) plotted v/s Lg. The inset shows the increase in Rch for Lg = 32nm compared to Lg = 75nm. 0.02000.04000.06000.08000.010000.0 0.0 10000.0 20000.0 30000.0 0100200 300 400 500 600 Lg (nm)Rch ( W m m)

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93 0.70.80.91.01.11.21.31.41.5 0.00 0.01 0.02 0.03 Lg=75nm data UO=350Q=0.2 Figure 5-7. Measured and UFDG-predicted low-VDS gm/IDS 2 vs. VGS used to tune the UFDG mobility parameters: UO = 350cm2/V-s, Q = 0.2 for the Lg= 75nm nFinFET.VGS (V)gm/IDS 2 (106m m/W)VDS=0.05V

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94 0.00.20.40.60.81.01.21.4 0.0000 0.0005 0.0010 0.0015 0.0020 Lg=75nm data UFDG Figure5-8.Lg=75nmnFinFETIDS-VGSdata,withcorrespondingUFDGcalibrationresults.The meff parameters extracted, via gm/IDS 2 -VGS in Fig. 5-7 (UO = 350cm2/V-s, Q = 0.2) and RS/D = 100 W-m m were used in the calibration.VGS (V)IDS (A/ m m)VDS=0.05V VDS=1V

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95 -0.50.00.51.01.5 10-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-310-2 Lg=32nm data UFDG Figure 5-9. Lg= 32nm nFinFET IDS-VGS data (on a log scale), with corresponding UFDG calibration results. The effective extension length, LeSD is tuned to be 9.25nm, implying Leff(weak)= Lg+2LeSD= 50.5nm.VGS (V)IDS (A/ m m)VDS=0.05V VDS=1V

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96 0.70.80.91.01.11.21.31.41.5 0.000 0.002 0.004 0.006 0.008 0.010 0.012 0.014 0.016 0.018 0.020 Lg=32nm data UO=110 Q =0.2 Figure 5-10. Measured and UFDG-predicted low-VDS gm/IDS 2 vs. VGS used to tune the UFDG mobility parameters: UO = 110cm2/V-s, Q = 0.2 for the Lg = 32nm nFinFET.VGS (V)gm/IDS 2 (106m m/W)VDS=0.05V

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97 Figure 5-11. Lg = 32nm n-FinFET IDS-VGS data with corresponding UFDG calibration results. The meffparametersextracted,viagm/IDS 2-VGSinFig.5-10(UO=110cm2/V-s, Q = 0.2) and RS/D= 120 W-m m were used in the calibration. 0.00.51.01.5 0.0000 0.0005 0.0010 0.0015 0.0020 Lg=32nm data UFDG VGS (V)IDS (A/ m m)VDS=0.05V VDS=1V

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98 5.0e+121.0e+131.5e+132.0e+13 0.0 50.0 100.0 150.0 200.0 Lg=10 m m meff data UFDG U0=205 Q =0.2 Ninv (cm-2)meff (cm2/ Vs)Figure 5-12. meff-Ninv for p-channel Lg = 10 m m device extracted using split-CV method. UFDG meff parameters (UO = 205 cm2/Vs, Q = 0.2) are tuned to match data.

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99 -1.5-1.4-1.3-1.2-1.1-1.0-0.9-0.8-0.7-0.6-0.5 0.00000 0.00005 0.00010 0.00015 0.00020 0.00025 Lg=1 m m data UFDG VGS (V)ISD (A/ m m)VDS=-0.05V VDS=-1V Figure 5-13. Lg = 1 m m p-FinFET ISD-VGS data, with corresponding UFDG calibration results. The meffparametersextractedviasplit-CVinFig.5-12(UO=205cm2/V-s, Q =0.2) were used in the calibration.

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100 0.02000.04000.06000.08000.010000.0 0 10000 20000 30000 40000 50000 020406080100 0 1000 2000 Figure 5-14. Channel resistance of p-channel devices, Rch (VGS= -1V, VDS = -0.05V) plotted versusgatelength,Lg.TheinsetshowstheincreaseinRchforLg=32nmcompared to Lg = 75nm.Rch ( W m m)Lg (nm)

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101 -1.5-1.0-0.50.0 0.0000 0.0005 0.0010 0.0015 Lg=75nm data UFDG Figure 5-15. Lg= 75nm pFinFET IDS-VGS data, with corresponding UFDG calibration results. The meff parameters extracted for Lg= 1 m m (UO = 205cm2/V-s, Q = 0.2) and RS= RD = 250 W-m m were used in the calibration.VGS (V)ISD (A/ m m)VDS=-0.05V VDS=-1V

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102 -1.5-1.0-0.50.0 0.0000 0.0005 0.0010 0.0015 Lg=32nm data UFDG Figure5-16.p-channelLg=32nmnFinFETIDS-VGSdata,withcorrespondingUFDGcalibration results. The meff parameters (UO = 90cm2/V-s, Q = 0.2) and RS/D= 250 W-m m were used in the calibration.ISD (A/ m m)VGS (V)VDS=-1V VDS=-0.05V

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103 Figure 5-17. Lg= 32nm p-FinFET IDS-VGS data (on a log scale), with corresponding UFDG calibrationresults.Theeffectiveextensionlength,LeSDistunedtobe8nm,implying Leff(weak)= Lg+2LeSD= 48nm.ISD (A/ m m)VGS (V)VDS=-1V VDS=-0.05V -1.5-1.0-0.50.00.5 10-1810-1710-1610-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-310-2 Lg=32nm data UFDG

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104 Figure5-18.Thisgureportraystheweak-inversionmatchbetweenUFDGandTaurus-predicted characteristics to estimate the S/D doping prole, NSD(y). For NSD0= 1 20 cm-3, sL= 20nm. Both Taurus and UFDG use a constant mobility model with meff= 107 cm2/V-s.VGS (V)IDS (A/ m m) -0.2-0.10.00.10.20.30.40.50.60.70.80.9 10-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-310-2 UFDG Taurus sL=20nm

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105 Figure 5-19. UFDG predicted meff-Ninv data for nFinFETs of various Lg. We observe a strong degradation of meff with reducing Lg. Further the degradation seems almost independent of Ninv. 5 10121 10131.5 10132 1013 0 100 200 300 400 Lg=1 m m Lg=75nm Lg=32nmNinv (cm-2)meff (cm2/ Vs)

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106 Figure5-20.ThisgureportraystheTaurus-projectedweak-inversionIDS-VGScharacteristics(on log scale) for the redesigned n-channel device. For reference, the IDS-VGScharacteristics of the actual n-channel device are also shown.VGS (V)IDS (A/ m m) -0.3-0.2-0.10.00.10.20.30.40.5 10-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-3 Redesigned device VDS=0.05V Redesigned device VDS=1V Actual device VDS=0.05V Actual Device VDS=1V

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107 Figure5-21.ThisgureportraystheextractedNSD(y)v/sdistancefromthecenterofthechannel (in channel direction). It also portrays the projected NSD(y) for an improved device design with Lext= 40nm. y = 0 corresponds to the center of the channel, so NSD(y) rolls off at y = Lg/2+Lext. For Lext= 50nm, this corresponds to y = 66nm while for Lext = 40nm, the corresponding point is y = 56nm.y ( n m)NSD (cm-3) -70-60-50-40-30-20-10010203040506070 1015101610171018101910201021 extracted NSD(y) NSD(y) w/ Lext=40nm Lg

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108 CHAPTER 6 PHYSICAL INSIGHTS ON CARRIER MOBILITIES IN SHORT-CHANNEL FINFETS 6-1 Introduction Scaling the conventional bulk device implies the need to reduce depletion width with reducing gate length (Lg) via increased channel doping [35]. The increased channel doping implies degraded effective carrier mobility, meff, due to higher impurity scattering as well as higher surface roughness scattering due to increased transverse electric eld, Ex [35]. In the FinFETdevicestructure,thebodycanbeleftundopedsinceshort-channel-effect(SCE)controlis obtained via two coupled gates on either side of a thin n. Thus, SCE control for scaled Lg is maintained by scaling down the n width, tSi, not by increased channel doping. Since the stronginversion meff is not a strong function of tSi [32], meff in strong inversion should not reduce with scaling Lg. While high meff, about three-times that of conventional bulk devices, has been widely reportedforlongLg(~1 m m)devices[4][13][14][15],wehaveobservedstrongdegradationin mefffor Lg< ~100nm (Fig. 5-19); further, such degradation has also been noted in the literature [13][14][15]. In fact, for Lg< ~100nm, reported meff is comparable to that of bulk devices at the same Lg[13]. This trend is worrisome because it undermines an important benet of FinFET technology and also raises questions about the potential benets of FinFET scalability. Various explanations have been advanced to explain this effect. They include Coulomb scattering due to source/drain (S/D) dopants/defects [16] and also neutral defects related to S/D processing [13][14]. In this chapter, we study the signicance, and possible causes of the mobility degradation for undoped short-Lg FinFETs. In Sec. 6-2, we use the Lg= 32nm device data from Sematech (Table 5-1) and our physical/process-based model, UFDG [10], to discuss the signicance of attaining high mobility in short-Lg FinFETs. In Sec. 6-3, we perform a literature survey focused

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109 on various papers that deal with the mobility-degradation issue. In Sec. 6-4, we discuss our insightsbasedonUFDGcalibrationoflong-andshort-LgFinFETdataatdifferenttemperatures. In Sec. 6-5, we use the insights gained to discuss possible causes of this effect and suggest ways ofaddressingit.Assumingthatthemobility-degradationissuecanberesolved,wethenperforma comparison (Sec. 6-6) between a pragmatic Lg=32nm FinFET technology with state-of-the-art bulk-MOSFET technology. Based on the comparison, we discuss technological requirements for FinFET-CMOS to eventually replace bulk-CMOS. 6-2 Signicance of High Mobility for FinFET CMOS Technology WeuseourUFDGmodelcardobtainedbycalibrationofthen-channelLg=32nmdevice (Table 5-2), and substitute the mobility parameters with those obtained for the Lg= 1 m m device (Sec. 5-4). The UFDG projection using the (ideal) high mobility is shown in Fig. 6-1, along with the actual UFDG calibration. We observe that the degradation in meff accounts for ~40% degradationinIon,fromIon=1.48mA/ m mto0.9mA/ m m,inthen-channeldeviceand~30%,from Ion=0.61mA/ m mtoIon=0.43mA/ m m,inthep-channeldevice(Fig.6-2).Thisseveredegradation inIonhighlightstheimportanceofachievinghighmobilityinshort-LgFinFETs.Further,thetrend (Fig. 5-6) implies a reduction in Ion with reducing Lg; if unresolved, it would undermine an important benet of scaling. For many applications, especially high-performance (HP) logic, the degradation in mobility threatens to be a show-stopper for FinFET CMOS technology. 6-3 Literature Survey The degradation of mobility for short-Lg undoped DG MOSFETs was rst observed in [13], where the low-eld mobility, m0, of longand short-Lg FinFETs was extracted from measured data using the Y-function method [46] at different temperatures. The authors found a substantial, temperature (T)-independent degradation in m0 which got worse with reducing Lg. This led them to conclude that the mobility at short-Lg was being limited by neutral defects

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110 associatedwiththesource/drain(S/D),sinceCoulomb-limitedmobility, mco,typicallyhas~T1-1.5dependence[47].Theauthorsalsoreportedsomeimprovementinmobilitywithincreasinganneal temperature which they attributed to neutral defect healing. In [14], meff measurements were done for both the front as well as the back channel of an undoped FD/SOI MOSFET. Interestingly, the authors obtained similar results as [13] for the front channel but observed little ornodegradationin meffforthebackchannel.Bothpapers[13][14]didnotcheckthedependence of meff on Ninv; that would have solidied (or not) their insights since mco tends to increase with Ninv. In [16], meff measurements were done on undoped FD/SOI MOSFETs using the magnetoresitancemethodandtheauthorsconcludedthatthedegradationforshortLgwasactually causedbyCoulombscatteringduetoS/Ddopants/defects.Theysuggestedthattheirmethodology is more accurate than [13][14] because i) it is not limited by uncertainties in Lg, ii) is more accurate at low Ninv, and iii) T dependence of mco is higher for magnetoresistance method [48]. Fig. 6 in [16] suggests that the meff degradation at room temperature is pronounced only for low Ninv; for high Ninv, the Lg= 40nm MOSFET displays about the same meff as the Lg = 1 m m. However, mco is about 3x higher in magnetoresistance measurements as compared to split-CV measurement [48]. So, the meff degradation might well be signicant even in strong inversion. 6-4 UFDG Calibration of Longand Short-Channel FinFETs UFDG has a physical, QM-based model for meff [32] with just two parameters: UO, the thick-tSi,low-Exmobilityand Q, whichisthesurface-roughnesstuningparameter.Typicalvalues are UO = 1100cm2/V-s and Q = 0.8 for n-FinFETs and UO = 190cm2/V-s and Q = 1 for pFinFETs [32]. Table 6-1 shows a summary of the meff parameters derived from the calibration of both longand short-Lg FinFETs. Let us rst look at the three devices (Lg = 1 m m, 75nm, 32nm) from Sematech. All of these devices were manufactured using the same S/D process (Table 5-1). Fig.5-19showsthe meff-Ninvgraphforthethreedevices.FortheLg=1 m mFinFET,the meff-Ninv

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111 plot shows (as expected) high meff = 330cm2/V-s at high Ninv = 1013cm-2. The low value of Q suggests relatively clean surfaces implying low surface roughness scattering. It is also clear that for progressively shorter Lg, there is a scattering component caused by proximity of channel carrierstotheS/D.ThedegradationispronouncedatLg=32nmandseemsalmostindependentof Ninv.LetusnowlookattheotherdevicesinTable6-1and6-2withLg~60-70nm.Wenoticethat the degradation in mobility corresponds directly to the effective underlap, LeSD. Longer LeSDimplieslowerdegradationin meff.Onepossibleexplanationforthisfactcouldbe(assuggestedin [16])CoulombscatteringfromS/DdopantsinthechannelorremoteCoulombscatteringfromthe S/D. Shorter underlap implies more S/D dopants in the channel (or in close proximity to the channel).However,CoulombscatteringwouldtendtobescreenedoutathighNinv,whilethe meffdegradation is almost independent of Ninv (Fig. 5-19). WeperformlinearregionIDS-VGSmeasurementsandUFDGcalibrationsatdifferentTfor theLg=1 m m,32nmFinFETsfromSematech(Table5-2).Thecorresponding meff-Ninvgraphsare shownforLg=1 m m,32nminFigs.6-3and6-4,respectively.Forthelong-Lgdevices,wendthat meff~ meff0 (T/300)-0.8, which is close to the typical T dependence of acoustic phonon scattering. Forshort-Lgdevices,thereisamuchweakerdependenceof meffonTforallvaluesofNinv.Ifwe assume that the additional scattering component due to S/D defects/dopants is mN, then .(6-1) Table 6-3 shows the so-computed values of mN at different T and Ninv. We note a very weak dependenceonTandalmostnodependenceonNinv.Thus,ourobservationsseemtoconcurwith [13][14],whichattributethe meffdegradationtoneutraldefects,ratherthanCoulombscattering. Wedonotdrawanyconclusions,however,sincethereisnoinsightonwhatmightbethenatureof 1 m N L g 32 nm = () ---------------------------------------1 m eff L g 32 nm = () -------------------------------------------1 m eff L g 1 m m = () ----------------------------------------- =

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112 these neutral defects and how they might scatter charge carriers. Another observation from Table 6-1 and 6-2 is that mN seems approximately the same for nand p-channel FinFETs. For Sematech p-channel devices, mN = 160cm2/V-s from Eq. 6-1 ( m0= 205cm2/V-s for Lg = 1 m m, m0= 90cm2/V-s for Lg= 32nm (Table 6-2)). This corresponds closely to the values of mN for the nchanneldevices(Table6-3).Thus,the meffdegradationseemstobeindependentofcarrier/dopant type. In Sec. 6-5, we discuss possible explanations of the meff degradation and suggest next steps into further diagnosing the problem. 6-5 Possible Explanations of the Mobility Degradation Letusrstdiscussthepossibilityofneutraldefectscatteringasthecauseofthemobility degradation.Sinceallscatteringisessentiallyelectricalinnature,aneutraldefectwouldhaveto introduce electrical perturbations in the silicon lattice to effectively scatter charge carriers. One might imagine that the presence of copious numbers of vacancies/divacancies might have this effect. Since interstitials are electrically neutral, they would not be effective in scattering charge carriers.[49]suggeststhat,sincedivacanciesareimmobileatroomtemperature,high-temperature processing can cause large (T-dependent) concentrations of divacancies to get frozen when the temperature is reduced too quickly to room temperature. The suggested solution is a long, relatively low-temperature (~350-400o C) anneal which would restore the equilibrium detailed balancebetweenvacanciesanddopants.ThisseemstobeaplausibleexplanationgiventhattheS/ D anneal used in the Sematech devices (Table 5-1) and also in [13][14][15] is a >1000o C spike anneal However, [49] also suggests that the divacancy concentration, Nd, is a strong function of donordoping,ND,butaweakfunctionofacceptordoping,NA.Thismeansthatp-channeldevices shouldberelativelyimmunefromthemobilitydegradationifitiscausedbydivacancies,whichis contrary to our observations in Sec. 6-4. Also, the S/D silicidation anneal is typically a long, relatively low-T anneal which should restore the equilibrium detailed balance between dopants

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113 and vacancies. Nevertheless, we believe that this is a theory worth checking. We suggest that a futurestudyofmobilityinundopedshort-LgMOSFETsshouldchecktheeffectofa~30min,350400o C anneal following the S/D processing on device characteristics. Another possible explanation may be that ion-implantation damage, possibly amorphization at the edges of the channel, might account for the mobility degradation. This explanation could explain the observation of [14], where the front-channel carrier mobility of a FD/SOI MOSFET is degraded but the back-channel mobility is not. The problem with this explanationisthatthespacerwidthoftheSematechdevicesisLext~50nm(Table5-1),andtheS/ D implant is carried out at a 0o vertical tilt. Thus, it seems unlikely that implantation damage couldmakeittotheedgesofthechannel.Tocheckthisexplanation,wesuggestareductioninthe S/Dimplantdose.FortheSematechdevices,theimplantdosewas3 1015cm-2foranheight,hSi=60nm(Table5-1).ThisimpliesaS/Ddopantconcentrationofdose/hSi=5 1020cm-3,whichis much larger than the active dopant concentration (~1 1020cm-3). We suggest that a reduction of the total implant dose should also be accompanied by implantation at multiple energies to ensure that the S/D dopants are distributed evenly across the vertical height of the n. A third possible explanation might be that the mobility degradation is caused by the highk/TiN gate stack. It has been shown [50] that nitrogen diffusion to the Si-dielectric interface causes Si-N interface donor/acceptor-type defects, which can cause Coulomb scattering. It is possible that N-diffusion to the edges of the channel during the deposition the TiN gate might accountforSiNinterfacedefects,whichaccountforthemobilitydegradation.Thisexplanationis supportedbythefactthat,tothebestofourknowledge,thepapersreportingmobilitydegradation [14][15][16] as well as our studies here have used device with a TiN gate (gate material not mentioned in [13]). The obvious objection to this theory is that the T, Ninv dependences of mNmake Coulomb scattering an unlikely explanation. Nevertheless, this explanation can be checked

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114 out by fabricating devices with a SiO2/poly gate stack. If the TiN gate is determined to be the cause of the effect, it may be necessary either to switch to a different gate material (e.g., TaC) or tointroduceavariationintheprocesswhichpreventsN-diffusion.Thehigh-kmaterialmightalso potentiallyplayaroleinthemobilitydegradation.BasedonourinsightsinChapter3,wethinkit is best to do away with high-k materials and use the conventional, relatively thick SiO2/SiON dielectric for nanoscale FinFET technology. A slight improvement in short-Lg mobility with increasing anneal temperature has been reported in [13]. A future study should also check the effect of different anneal temperatures to study any signicant correlation with carrier mobility. The above observations are summarized in Table 6-4. While we have not been able to establish the cause of the mobility degradation, we have laid out a plan for a future study of this effect. As noted in Sec. 6-2, the mobility-degradation issue needs to be resolved for FinFET technology to be viable in high-performance (HP) logic applications. Assuming that high carrier mobilitycanberealizedinnanoscaleFinFETs,wediscusstechnologicalrequirementsinSec.6-6 for FinFET-CMOS to eventually replace bulk-CMOS. 6-6 Comparison of a Pragmatic FinFET Technology to Bulk Technology We now seek to compare a hypothetical pragmatic FinFET technology [2], one with a commonmidgapmetalgate,relativelythickSiO2/SiONgatedielectric,highmobilitywithoutany transport enhancement via strain, to a state-of-the-art HP bulk technology at Lg~ 32nm [45]. We assume that the mobility degradation issue for short-Lg can be resolved based on our insights in Sec. 6-5 and future development work. We therefore use our UFDG model card obtained from calibrationofLg=32nmdevicedatawithidealmobilityparameters(obtainedforLg=1 m m).The UFDG projected IDS-VGS characteristics of the nand p-channel devices are shown in Fig. 6-1

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115 and 6-2, respectively. Based on the comparison, we seek to understand the technological requirements for FinFET-CMOS to eventually replace planar bulk-CMOS. Since FinFET device width is along the height of the n, a fair comparison of the two technologies would entail comparison of Ion per unit lithographic pitch (P) [1]. This is discussed more in the next paragraph; we rst look at Ion per unit device width. We use the (correct) device width denition, W = hSi, for the FinFET [20] as compared to W = 2hSi typically used in the literature. The HP n-channel Lg = 30nm bulk device displays Ion= 1.55mA/ m m [45], while the pragmatic [2] Lg= 32nm Sematech FinFET with ideal mobility parameters would give Ion = 1.48mA/ m m(Fig.6-1).TheHPp-channelLg=30nmbulkdevicedisplaysIon=1.21mA/ m m[45], whilethepragmaticp-FinFETwouldgiveIon=0.61mA/ m m(Fig.6-2).Thep-channelFinFETIonis low, partly due to the high parasitic resistance, RS/D = 250 W-m m (Table 5-2). Due to the long underlap,thereisscopeforimprovementintheFinFETIonforbothp-andn-channeldevicesvia the device redesign insights in Sec. 5-7. For example, in the p-channel device, a more reasonable RS/D= 100 W-m m would give Ion = 0.82mA/ m m. Aside from higher RS/D as a result of the long underlap, the reason that FinFET Ion per unitgatewidth(2hSi)issignicantlylowerthanIonperunitwidthinbulkdevicesisthree-fold. One,thebulk-inversioneffect[20]inundopedUTBMOSFETsimpliesthatthechargecentroidis signicantly removed from the Si-dielectric interface, resulting in a lower gate capacitance than bulkdevices.Webelievethatthiseffectleadsto~15%reductioninchargeinundopeddevicesfor thesamegateoverdrive(VGS-Vt)[51].Also,themidgapgatetypicallyusedinFinFETsimpliesa relatively high threshold voltage in strong inversion, Vts ~ 0.4V, causing lower Ion. Vt can potentially be tuned by allowing controlled densities of S/D dopants into the channel [12], or by using a dual-metal gate technology. Additionally, the absence of carrier transport enhancement via strain leads to p-channel Ion per unit device width being signicantly lower in the FinFET as

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116 comparedtothebulkdevice.Thereasonforthesignicantdifferenceinp-channelIonratherthan the n-channel Ion is because strain leads to mobility enhancement ~4x for holes as compared to only ~1.7x for electrons [52]. Basedontheaboveinsights,wecanmakethefairassumptionthatanoptimized pragmatic n-channel FinFET would give somewhat better Ion per unit device width than a HP bulk device, provided the FinFET device width is dened as W = hSi. A pragmatic p-channel FinFET would give signicantly lower Ion per unit device width in comparison because of the absence of the transportenhancementviastrain[52]asinabulkdevice.Itmaybefeasibletoenhancep-FinFET Ion via strain-induced transport enhancement in the future [53]. The primary advantage of FinFET technology over a future bulk technology is the enhanced scalability due to excellent SCE control and reduced process-related variations from devicetodevice.WhilebulkdevicesarenotscalablebeyondLg<~30nm,FinFETscanbescaled to Lg<10nm [2]. Given this enhanced scalability, we reasonably assume that for HP FinFETCMOS technology to be competitive with HP bulk technology would require the total device width per pitch to be about the same as the pitch. For a nominal technology with one n per lithographic pitch, this translates to hSi = P while for a spacer lithography technology [54] with twonsperpitch,2hSi=PorhSi=P/2.Whilethechallengesforfuturebulktransistorsarenovel dielectric and channel materials and a dual metal gate technology, pragmatic FinFET devices could use the conventional SiO2/SiON gate dielectric (Chapter 2) and a midgap metal gate. The important challenges for the commercialization of FinFET-CMOS technology include optimal S/ D engineering (Chapter 5), resolution of the mobility degradation issue, and fabrication of thin, tall ns for adequate on-state current drive.

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117 6-7 Summary In this chapter, we obtained physical insights into the signicance and possible causes of carrier mobility degradation in short-channel FinFETs. We offered processing suggestions which can be used to diagnose and possibly mitigate the effect. We then compared our Lg = 32nm FinFET device, with high mobility, with a state-of-the-art bulk device, noting technological requirements for FinFET-CMOS to eventually replace conventional bulk-CMOS.

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118 Table 6-1. Summary of mobility parameters for n-channel FinFETs. The table also gives the source of the data along with relevant device characteristics. Data Sourcen-channel Lg (nm)Mobility parametersDevice characteristics Sematech1 m mUO = 900 Q = 0.32{110} surface LeSD= 9.25nm Sematech75nmUO = 350 Q = 0.2{110} surface LeSD= 9.25nm Freescale60nmUO = 200 Q = 0.2underlapped Freescale70nmUO = 125 Q = 0.4LeSD= -5 to -10nm Sematech32nmUO = 110 Q = 0.2{110} surface LeSD= 9.25nm Sematech32nmUO = 80 Q = 0.2{100} surface LeSD= 9.25nm Table 6-2. Summary of mobility parameters for p-channel FinFETs. The table also gives the source of the data along with relevant device characteristics. Data Sourcep-channel Lg (nm)Mobility parametersDevice characteristics Sematech1 m mUO = 205 Q = 0.2{110} surface LeSD= 8nm Sematech75nmUO @ 205 Q @ 0.2{110} surface LeSD= 8nm Freescale60nmUO = 140 Q = 0.2LeSD = 3nm Sematech32nmUO @ 90 Q = 0.2{110} surface LeSD= 8nm Sematech32nmUO @ 90 Q = 0.2{100} surface LeSD= 8nm

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119 Table 6-3. The extracted mobility due to undetermined degradation mechanism ( mN) for Lg= 32nm as a function of temperature (T) and inversion charge density, Ninv. T (K) mN (Ninv=6 1012 cm-2) mN (Ninv=1 1013 cm-2) mN (Ninv=1.5 1013 cm-2) 125161160164 175178182184 200194192206 225194197208 250200203208 275154157165 Table 6-4. Possible causes and solutions to the problem of mobility degradation in nanoscale FinFETs Possible causes of mobility degradationPossible Solutions High concentration of vacancies/divacancies during high temperature processing, which get frozen due to quick reduction to room temperature. A long (~30min), relatively low temperature (350-400o C) anneal to restore equilibrium detailed balance between dopants and vacancies. Ion implantation damage, e.g. amorphization, which affects the edges of the channel Reduce implant dose; implant at multiple energies to distribute S/D dopants uniformly along n height. Nitrogen diffusion to channel edges during depositionofTiNmetalgate,whichresultsin interface states that may cause Coulomb scattering. FabricatedeviceswithSiO2/polygatestackto checkexplanation.Iftrue,useadifferentgate materialorchangeprocesstopreventN-diffusion.

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120 Figure 6-1. This gure portrays UFDG calibration of IDS-VGS characteristics of the n-channel Lg=32nmdeviceinTable5-1alongwithUFDGprojectedIDS-VGScharacteristics with ideal mobility parameters (same as Lg= 1 m m)VGS (V)IDS (A/ m m) 0.00.10.20.30.40.50.60.70.80.91.0 0.0000 0.0005 0.0010 0.0015 Actual UFDG calibration UFDG projection w/ ideal mobility

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121 Figure 6-2. This gure portrays UFDG calibration of IDS-VGS characteristics of the p-channel Lg=32nmdeviceinTable5-1alongwithUFDGprojectedIDS-VGScharacteristics with ideal mobility parameters (same as Lg = 1 m m)VGS (V)IDS (A/ m m) -1.0-0.9-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.10.0 0.0000 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 Actual UFDG calibration UFDG projection w/ ideal mobility

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122 5.0e+121.0e+131.5e+13 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 1000.0 T=125K T=175K T=200K T=225K T=250K T=275K T=300K Figure 6-3. This gure portrays UFDG-predicted effective mobility, meffvs. inversion charge density, Ninv at different temperatures for n-channel Lg= 1 m m FinFET.Ninv (cm-2)meff (cm2/ V-s)

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123 5.0e+121.0e+131.5e+13 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 160.0 180.0 200.0 T=125K T=150K T=175K T=200K T=225K T=250K T=275K T=297K Figure 6-4. This gure portrays UFDG-predicted effective mobility, meffvs. inversion charge density, Ninv for n-channel Lg = 32nm FinFET.Ninv (cm-2)meff (cm2/ V-s)

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124 CHAPTER 7 SUMMARY AND FUTURE WORK 7-1 Summary This dissertation focused on physical modeling and optimal design insights for nanoscale Double-Gate CMOS devices and technology. The major contributions of the research are summarized as follows. InChapter2,weproposedanddemonstratedviadevicesimulationsanovelITFETdesign which is more scalable than a conventional ITFET. The design used a midgap metal gate on the FinFET in conjunction with a higher work function gate on the FDFET (p+ poly gate on the nITFET and vice versa). This design allows for a poorly tempered FDFET since the ITFET weak-inversion characteristics are not affected by the short-channel effects of the FDFET. The resulting device gives an improvement in on-state current of ~20-35% over the conventional FinFET.TheproposeddesignisscalabletogatelengthLg~9nm,whichisneartheendoftheSIA ITRS roadmap. In Chapter 3, we studied the impact of a high-k gate dielectric on the performance and scalabilityofnanoscaleDG-FinFETCMOS.Wedesignedahigh-kFinFET,andcompareditwith a pragmatic FinFET having thicker (> EOT), conventional SiO2 gate dielectric at the HP-45nm node (Lg = 18nm) of the 2005 SIA ITRS. We found that the high-k dielectric actually degrades CMOS-speed performance due to two heretofore unacknowledged compromising effects of the high-k. One is additional CG reduction due to quantization because of higher transverse electric eld resulting from thinner EOT; the Ion enhancement expected for the thinner EOT is thus compromised. The second is additional loss of effective gate bias due to source resistance, RSbecause of the higher Ion; the enhancement in Ion is thus compromised more. Further, in the pFinFET, hole mobility is degraded due to the higher transverse eld, compromising Ion even

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125 more. Our simulation-based study did imply a small improvement in the scalability of DGFinFET CMOS due to the thinner EOT. However, given the reduced circuit performance and the technologicalchallengesofintegratingahigh-kdielectricintotheprocessow,weconcludedthat itisnotworthwhile.Webelieve,alsobasedonourstudy,thatthepragmaticapproachtonanoscale FinFET CMOS should be taken, with good performance expected to the end of the ITRS. InChapter4,wepresented,forthersttime,amodelforparasiticfringecapacitance(Cf) in DG MOSFETs with (realistic) non-abrupt source/drain junctions. Our model is physically based and therefore quasi-predictive. We evaluated our model for different device structures and foundgoodagreementwithnumericalsimulationresults.WeimplementedthemodelforCfinour physical/process-basedmodel,UFDG.Weusedquasi-predictiveringoscillatorsimulationsusing UFDG/Spice3 to study the impact of a low-k spacer on FinFET CMOS speed performance. We found that using a SiO2 (ksp= 3.9) spacer instead of a Si3N4 (ksp= 7.5) reduced RO delay by ~25%, while using an air (ksp= 1) spacer reduced RO delay by ~40%. Cf can also be reduced by increasing the effective underlap, LeSD; however, that also increases the S/D resistance (RS/D) implying a design tradeoff. Our model for Cf will be helpful in engineering this design trade-off for optimal speed performance. In Chapter 5, we discussed the problem of S/D process design for nanoscale FinFET CMOS technology. FinFETs have undoped bodies; so, the S/D lateral doping prole, NSD(y), denes the tradeoff between LeSD (which denes SCEs and Cf) and RS/D (which denes on-state current, Ion). For optimal S/D process design, we developed and demonstrated a methodology to reverse-engineer NSD(y) from FinFET CG-VGS and IDS-VGS characteristics. Using the extracted NSD(y), we provided insights on redesigning the device so as to obtain a better tradeoff between SCEs and Ion.

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126 In Chapter 6, we studied the problem of mobility degradation for short-Lg FinFETs. We observed that in the Lg = 32nm device data obtained for Sematech, the mobility degradation is responsiblefor~40%and~30%degradationinIonforn-andp-devices,respectively.Weattained insights into this phenomenon via a thorough literature survey as well as UFDG calibration to devicedataatdifferenttemperatures.Basedontheseinsights,wediscussedpossiblecausesofthe problem, which included high divacancy concentration related to high-temperature S/D processing, ion-implantation damage at the edges of the channel, and Coulomb scattering due to interface states caused by nitrogen diffusion. We also proposed solutions to help diagnose and possiblymitigatetheeffect.WethencomparedapragmaticFinFETtechnologybasedonourLg= 32nmdevicedata(assumingidealmobility)tostate-of-the-artLg=30nmbulktechnology.Based on the comparison, we discussed technological challenges for FinFET CMOS to eventually replace bulk CMOS. 7-2 Future Work In Chapter 4, we developed a model for Cf in symmetrical DG MOSFETs. The model should be generalized to include asymmetrical DG and FD/SOI MOSFETs. In Chapter 5, we outlined a methodology to extract NSD(y) = NSD0exp(-y2/ sL 2) from deviceCG-VGSandIDS-VGSdata.AcomprehensivestudyonS/Dprocessingisrequiredtostudy the variation of device characteristics to different spacer widths (Lext) as well as different anneal conditions (anneal temperature, time and type). To study the variation of device characteristics with Lext, devices should be fabricated with different Lext but using the same S/D anneal conditions (so they have approximately the same sL). Depending on Lext, some of these devices will have underlap, others will have overlap. With the methodology in Chapter 5, the S/D doping straggle, sL can be obtained for each device. The average value of sL can be used to plot, via Taurus simulations, LeSD as a function of Lext. In the case of overlapped devices, RS/D@ Rcon,

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127 where Rcon is the contact resistance. In the case of underlapped devices, RS/D= Rcon +Rext(Lext), whereRextistheextensionresistanceasafunctionofLext.Rconcanbeobtainedfromoverlapped devices,whichcanthenbeusedtoobtainRextasafunctionofLextforunderlappeddevices.Rcon, Rext(Lext), and LeSD(Lext) can be used to calibrate UFDG and perform RO simulations to design Lext for optimal circuit performance. Fig. 7-1 summarizes the methodology which would adequately characterize the S/D process. This methodology should be repeated for different S/D anneal cycles with variations in S/D anneal temperature/time to characterize the dependence of annealconditionsonRS/DandLeSD.Itwillbeinterestingalsotoseehowthemobility, meff,varies with Lext and as a function of S/D anneal conditions. In Chapter 6, we made conjectures into the possible causes of mobility degradation in short-Lg FinFETs. We also offered processing suggestions to diagnose and possibly mitigate the effect of mobility degradation in short-Lg FinFETs. We believe that these processing suggestions should be tried in a comprehensive study of mobility in short-Lg FinFETs. To test the theory that meffdegradationisrelatedtodivacanciescausedbyhigh-temperatureprocessing,weproposethat the devices be subject to a long (~30 min), relatively low temperature (350-400o C) anneal after the S/D processing. To test the theory that the meff degradation is caused by ion-implantation damage, we propose that the S/D implant dose be reduced and the implant be carried out with different energies to ensure relatively uniform distribution of S/D dopants along the vertical height of the n. To check the possibility of scattering by interface states caused by nitrogen diffusion, we propose that devices be fabricated with SiO2/poly gate stack. If substantial improvement in meff is observed, the TiN gate should be replaced by a different material, or the process should be varied to prevent N diffusion.

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128 Figure 7-1. This owchart describes a potential future study to optimize the S/D process using devices with different spacer width, Lext. Calibration of de vices with long underlap Vt implies FMSCEs imply sLRS/D=Rcon+Rext(Lext) Calibration of de vices with o v erlap/ short underlap SCEs imply sLRS/D@ Rcon Obtained process information FMRconsL,LeSD(Lext) Rext(Lext) End Start

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129 APPENDIX AAUSING TAURUS AND UFDG FOR UTB DEVICE SIMULATION A-1 Introduction This appendix discusses how we use the Taurus device simulator [9] and our compact model,UFDG[10],inconjunctionwitheachotherforperformanceprojectionsofultra-thin-body (UTB) devices. Both UFDG and Taurus have unique strengths which are extremely useful in device modeling. Taurus has the advantage of the superior 2-D electrostatics modeling typical of device simulation programs. However, the quantization and transport models in Taurus are not well-suited to UTB devices. Also, the modeling of the carrier velocity-saturation effect in Taurus canintroduceinadvertenterrorsinI-Vprojectionsaswewillseelater(Thishasbeenxedinthe newer version of Taurus ( Sentaurus [55]) as will be discussed). On the other hand, UFDG has physical, well-calibrated models for mobility [32], velocity overshoot [34], ballistic-limit current [4], quantum-mechanical threshold shift [19], and inversion layer capacitance [33]. TotakeadvantageofthesuperiorelectrostaticsofTaurusaswellasthephysicaltransport and QM models of UFDG, we often compare I-V characteristics predicted by them. When comparingUFDG-andTaurus-predictedcharacteristics,weturnoffQM(QMX=QMD=0)and transport(VO=0,BLIM=0)modelsinUFDG.Wealsousecomparablemobilitymodelsinboth UFDG and Taurus with the same electric eld (Ex, Ey) dependence. Here, Ex refers to the transverseeldperpendiculartothecurrentdirectionandEyreferstothelongitudinaleldinthe current direction. Section A-2 briey describes the relevant Taurus and UFDG mobility models and how to relate them to each other. Section A-3 and A-4 describe how the models are used in weak and strong inversion, respectively.

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130 A-2 A Brief Description of Taurus and UFDG Mobility Models Taurus offers several low-eld mobility models which model mobility as a function of transverse eld, Ex, doping, ND and temperature T (i.e., meff(Ex, ND, T)). (Note that the low-eld hereimplieslowlongitudinaleld,Eynottransverseeld,Ex).Noneoftheseareparticularlywell suited to UTB devices. Thus, we rely on the default low-eld mobility model which assumes no Ex, ND or T dependence. The default low-eld mobility can be specied by using MUN0 ( mN0) and MUP0 ( mP0) parameters for electron and hole mobility respectively. Let us assume that we specify MUN0 = 500cm2/Vs. In addition, there are two options to specify longitudinal eld (Ey) dependence. The rst one is the constant mobility model which assumes no meff(Ey) dependence. Thus, it does not model the velocity saturation effect for high VDS. For the rest of thisappendix,werefertothismodelastheconstantmobilitymodel.Thismodelisspeciedin the Taurus model card as follows: Constant=True MUN0=500 The other high-Ey model offered by Taurus is the CaugheyThomas model which can be tuned to model the Ey dependence the same way as UFDG. This model species meff as follows: meff= mN0/[1+(vsat/ mN0Ey)b]1/b. To tune this model to UFDG, we specify betan( b ) = 1. vsat can also be set according to our convenience. The default value is vsat= 1 7cm/s. The model code is as follows. MUN0=500 HighFieldMobilityActive=True, HighFieldMobility ( HighFieldModel=CaugheyThomasModel, heatingField=EdgeField, vsatModel=constantvsatmodel,

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131 CaugheyThomasModel(betan=1), constantvsatmodel(vsatn=7e6) ) Through the rest of this appendix, this model is referred to as the velocity saturation model for convenience. As described in the following sections, we need to use both the constant mobility model and the velocity saturation model selectively to accurately tune Taurus-predicted characteristics to UFDG. The mobility model in UFDG is QM-based [32]; when the QM model is turned off (QMX=QMD=0), the mobility model reverts to the simple model specied in [41]. Both these mobility models have two parameters: UO, which is meff in a thick body (tSi-> and Ex= 0) and Q ,whichisthesurfaceroughnesstuningparameter.WhentuningUFDG-predictedcharacteristics to Taurus, we always turn the QM model off as discussed in Sec. A-1. Specifying Q = 0 removes the Ex dependence of meff. meff is then a function of UO and tSi. We then choose UO so that it givesus meff=500cm2/Vs(asspeciedinTaurusmodelcard).Weachievethisbyprintingout mefffrom the UFDG code for different values of UO. A-3 Calibration of Weak-Inversion I-V Characteristics Werstdescribecalibrationofweak-inversioncharacteristicsofanabruptjunctiondevice predicted by Taurus and UFDG. We assume a nominal DG MOSFET structure with abrupt junction, Lg = 25nm, UTB width tSi= 10nm, gate oxide thickness tox= 1.2nm and midgap gates. Since weak-inversion current is diffusion limited, meff(Ey) should not have a signicant effect on weak-inversion I-V characteristics. Hence, it is surprising that Taurus predicts very different I-V characteristics when using the constant mobility and velocity saturation models (Fig. A-1) On closer inspection, we nd that when using the velocity saturation model, Taurus predicts a 4x reduction in carrier mobility because of the junction electric eld between the source and

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132 channel.Fig.A-2showstheelectricpotentialasafunctionofpositionwit hy=0 correspondingto the center of the channel. If we consider the diffusion length to be ~5nm, Ey at the source end of thediffusionlengthis6 4V/cm.PluggingEyintotheexpressionfor meff(Ey)wecalculatea4x reduction in mobility. This is an invalid effect because the electric eld in the source to channel junction is a built-in equilibrium eld which does not heat carriers; thus it does not lead to meffreduction. We note, therefore, that calibration of UFDG with Taurus using the Taurus velocity saturation model will give erroneous results. Ideally, if the gradient of the electron quasi-Fermi potential, dFn/dx, is used (instead of Ey) to dene meff, the above-mentioned effect will be eliminated. Since Taurus does not provide the user with this option, we use the constant mobilitymodelinweakinversiontoremovethisdubiousEydependence Agoodmatchbetween UFDG and Taurus-predicted characteristics is obtained as observed in Fig. A-3. (The recent upgraded version of Taurus, Sentaurus [55], provides the user with the option of using dFn/dx to dene meff. Thus, device simulations using Sentaurus should use the velocity saturation model with meff dened by dFn/dx instead of Ey). With the constant mobility model turned on, Taurus is very useful in predicting weakinversionI-Vcharacteristicsfordeviceswithanon-abruptsource/drain(S/D)dopingprole.This is due to the superior electrostatics modeling which is typical of device simulation tools. UFDG doesnotmodeldevicecharacteristicsintermsoftheirS/Ddopingprole;insteaditusesatunable effective underlap, LeS/LeD. To tune UFDG to Taurus-predicted I-V characteristics of devices withnon-abruptS/Djunctions,wetunethemobilitymodelsasdiscussedaboveandadditionally tune LeS/LeD. A-4 Calibration of Strong-Inversion I-V Characteristics As discussed above, since QM effects like inversion-layer capacitance [33] and transport effectslike meff[32],velocityovershoot[34]andballistic-limitedcurrent[4]arenotwellmodeled

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133 in Taurus, it is not possible to obtain realistic I-V projections in strong inversion. Typically, we use UFDG with all physical models turned on for quasi-predictive I-V projections in stronginversion. However, we still use Taurus to predict relative currents for different device structures which cannot be reliably modeled using UFDG (Chapter 2). The velocity saturation mobility modelisusedinspiteofsomeerrorintroducedduetotheinvalid meffdegradationeffectdiscussed above. We note that this error is reduced in strong inversion for abrupt S/D junctions because the potentialbarrierbetweentheS/Dandthechannelisgreatlyreduced(Fig.A-4).Figs.A-5andA-6 show the match between Taurus and UFDG-predicted strong-inversion characteristics with RS/Dtunedto25 W-m minUFDG.Fordeviceswithnon-abruptS/Djunctions,thereisstillasignicant potential barrier in the S/D extension (Fig. A-7) which amounts to an invalid RS/D component. However,webelievethattrendspredictedbyTaurusfordifferentdevicestructureswiththesame S/D doping prole, NSD(y), would still be meaningful since they would have the same (dubious) RS/D.AsmentionedinSec.A-3,ifSentaurus[55]isusedfordevicesimulations,theinvalidRS/Dcomponent can be eliminated by using dFn/dx (instead of Ey) to dene meff. While predicting strong-inversion currents, we use realistic values for MUN0, MUP0 based on UFDGs mobility model predictions. For example, typical meff parameters for n-channel DG MOSFETs (UO = 1100cm2/V-s and Q = 0.8) predicts meff ~ 300cm2/Vs for an undoped DG MOSFET with midgap gates at VGS = 1V. In summary, it is possible to predict trends in strong inversion between different device structures using Taurus as long as the S/D doping prole is the same for all given structures. MUN0, MUP0 should be chosen to be realistic and the velocity saturation model should be turned on. Table A-1 summarizes our ndings.

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134 A-5 Additional Note When the doping prole is assumed to be gaussian, Taurus assumes the lateral straggle s asisgivenintheequation,NSD(y)=NSD0exp(-y2/2 s2).Medici[56],however,assumesthe s asis givenintheequation,NSD(y)=NSD0exp(-y2/ s2)(asisassumedinourwork).Thus, s( asgivenby Medici) =sqrt(2)* s (as given by Taurus).

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135 Table A-1. A summary of the mobility models to be used for Taurus predictions. Type of Characteristic Mobility Model Weak inversion IDS-VGS characteristicsUse constant mobility model, i.e. constant mobility with velocity saturation turned off Strong inversion IDS-VGS and IDS-VDScharacteristics Use velocity saturation model i.e. constant mobility with velocity saturation turned on

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136 0.00.10.20.30.40.50.60.70.80.91.0 10-1110-1010-910-810-710-610-510-410-310-210-1100 Taurus constant mobility model Taurus velocity saturation model FigureA-1.AcomparisonoftheTaurus-predictedIDS-VGScharacteristicsusingconstantmobilityandvelocitysaturationmodelsforanabruptDGMOSFET(Lg=25nm,wSi= 10nm, tox= 1.2nm, midgap gates).VGS (V)IDS (A/ m m)

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137 -12.5-7.5-2.52.57.512.5 0.00 0.10 0.20 0.30 0.40 0.50 FigureA-2.Theelectricpotentialasafunctionofdistancealongthecenterofthechannelofan abrupt junction DG MOSFET (Lg= 25nm, wSi= 10nm, tox= 1.2nm, midgap gates).ThebiasconditionsusedareVGS=0V,VDS=100mV.y=0correspondsto the center of the channel.y (nm)Potential (V)

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138 0.00.10.20.30.40.50.60.70.80.91.0 10-1010-910-810-710-610-510-410-310-210-1100 Taurus with constant mobility model UFDG Figure A-3. Calibration between Taurus and UFDG-predicted weak-inversion IDS-VGS characteristics of an abrupt junction DG MOSFET using the constant mobility model. The deviceusedhasLg=25nm,wSi=10nm,tox=1.2nm,abruptS/Djunctions,andmidgap gates.VGS (V)IDS (A/ m m)

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139 -5051015202530 0.62 0.63 0.64 0.65 0.66 0.67 0.68 0.69 0.70 0.71 Figure A-4. The electric potential as a function of distance along the center of the channel of an abrupt junction DG MOSFET (Lg= 25nm, wSi= 10nm, tox = 1.2nm, midgap gates). ThebiasconditionsusedareVGS=1V,VDS=100mV.y=0isattheedgeofthegatePotential (v)y (nm)

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140 0.00.10.20.30.40.50.60.70.80.91.0 0.0000 0.0010 0.0020 0.0030 Taurus UFDG Figure A-5. Calibration between Taurus and UFDG-predicted IDS-VGS strong-inversion characteristics of an abrupt junction DG MOSFET using the velocity saturation model. The S/D resistance is tuned to RS/D= 25 W-m m in UFDG. The device used has Lg = 25nm, wSi = 10nm, tox = 1.2nm, midgap gates.VGS (V)IDS (A/ m m)

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141 0.00.10.20.30.40.50.60.70.80.91.0 -0.0010 0.0000 0.0010 0.0020 0.0030 Taurus UFDG Figure A-6. Calibration between Taurus and UFDG-predicted IDS-VDS strong-inversion characteristics of an abrupt junction device using the velocity saturation mobility model. The S/D resistance is tuned to RS/D = 25 W-m m in UFDG. The device used has Lg = 25nm, wSi = 10nm, tox = 1.2nm, abrupt S/D junctions, and midgap gates.VGS (V)IDS (A/ m m)

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142 -20-100102030 0.55 0.60 0.65 0.70 Figure A-7. The electric potential as a function of distance along the center of the channel of a non-abrupt junction DG MOSFET (Lg= 18nm, wSi= 10nm, tox= 1.2nm, Lext= 20nm, s = 10.7nm, midgap gates). The point y = 0 is at the edge of the gate.y (nm)Potential (v)

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143 APPENDIX BB UFDG CODE REVISIONS FOR HIGH-K DEVICE SIMULATION B-1 Introduction In Chapter 3, we discussed the suitability of high-k gate dielectrics in nanoscale FinFET CMOS technology. To evaluate the performance of FinFETs with a high-k gate dielectric, we performed quasi-predictive simulations of these devices using UFDG [10]. However, UFDG implicitly assumes that the gate dielectric material is SiO2. This Appendix discusses the UFDG codechangesthatweremadetoaccountforthehigh-kdielectricmaterial.Wenotethatthesecode revisions are not permanent; they were done only for the purpose of this work. The revisions includeddeninganewconstanttoaccountforthegatedielectricmaterial(Sec.B-2)andchanges in the parasitic fringe capacitance model (Sec. B-3). B-2 Code Revision to Account for Gate Dielectric Material Asofversion3.7,UFDGassumesthatboththegatedielectricandthespacermaterialare SiO2. In the UFDG header le a constant, OXIDE_PERMITTIVITY, is dened and its value is setto3.9 e0(correspondingtoSiO2),where e0isthepermittivityofvacuum.Thisconstantisused both for the gate dielectric permittivity as well as the spacer permittivity. In our high-k device simulation,weassumethatthegatedielectrichask=25(correspondingapproximatelytohafnium dioxide) and the spacer material is SiO2(k=3.9). Thus, we set the value of OXIDE_PERMITTIVITY to 25 e0, corresponding to the high-k gate dielectric material. We also dene a new constant for the spacer permittivity. We call it SPACER_PERMITTIVITY and set the value to 3.9 e0. The new variable, SPACER_PERMITTIVITY, is used in the parasitic capacitance model of UFDG to dene the outer fringe capacitance (Cof).

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144 B-3 Code Revisions for Fringe Capacitance Model The basic fringe-capacitance model [24] in UFDG stems from that dened by two separatedconductingplatesatanangle q asshowninFig.B-1.Thecapacitanceperunitwidthof this system is given by [57] (B-1) where e isthepermittivityand q, r1andr2arethegeometricalparametersdenedinFig.B-1.The underlapstructureinweakinversionisapproximatedbyanabruptjunctionatdistanceLeSDfrom the gate edge. LeSD is dened by the lateral doping prole, NSD(y), and is a function of the source/drain extension length, Lext, and doping straggle, sL (Chapter 4). The system is shown in Fig. B-2. The model for Cif reduces the plate-plate angle from p /2 to b (Fig. B-3), to effectively account for the silicon permittivity ( eSi) being about three times that of the gate dielectric ( edi)(SiO2 in this case). .(B-2) However, when we use the high-k gate dielectric ( edi=25 e0) instead of SiO2, b > p and the constructioninFig.B-3isnotphysical.ToaccountforCif,weuseanotherconstruction,shownin Fig.B-4,wherethethicknessofthegatedielectricisscaledby a ,where a=edi/ eSi.Thisisdoneto dene an effective system consisting of only one dielectric material (silicon), while keeping the capacitance of the gate dielectric constant. From Fig. B-4, we see that, If LeSD>tdi/ a Cifis given by, .(B-3) If LeSD
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145 .(B-4) In the above expressions, tdi is the thickness of the gate dielectric and tSi is the thickness of the silicon n. fif is a tuning parameter used to account for uncertainty in LeSD and is determined by matching model predictions with numerical simulations. To tune fif for the high-k device in Chapter3,wesimulatedthehigh-kdevicestructure(Table3-2)usingTaurus[9]andtunedfif=1.3 in UFDG to match the weak-inversion fringe capacitance. C if 2 e Si p ---------t Si t di a + t di a --------------------------log =

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146 f 0r1r2r 0 q+ + + + + + + + + + + + + + + + +_ _ _ _ _ + _V FigureB-1.Basictwo-platemodelforfringecapacitance(perunitwidthinz),withthecylindrical coordinates (r and f ) used in the analysis shown.

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147 tg toxGate Oxide b ao c Si UTB Source/Drain LeSD CifCof FigureB-2.Aschematicdiagramofthegate-source/drainstructureofaDGMOSFET,indicating the G-S/D underlap (with effective length, LeSD) and the two components of the parasitic fringe capacitance.

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148 tg tox tSiSource/Drain Gate Oxide Si Oxide b LeSD b ao o ac f g de (a) Figure B-3. Schematic of the G-S/D underlap structure used in derivation of Cif for device with SiO2dielectric.Thereducedangle b isdenedafterreplacingthehigher-permittivity silicon with oxide.

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149 tg Source/Drain Gate Oxide Si LeSD b oc f g(a) tdi/ a p/2 tsiCifDielectric -> Si Figure B-4. The effective G-S/D underlap structure used in derivation of Cif for device with highk dielectric. The effective dielectric thickness is reduced to tdi/ a to account for permittivity of dielectric.

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150 LIST OF REFERENCES [1]Itr05The International Technology Roadmap for Semiconductors 2005, Austin, TX: Semiconductor Industry Association. [2]Fos04J. G. Fossum, L. Q. Wang, J.-W. Yang, S.-H. Kim, and V. P. Trivedi, Pragmatic design of nanoscale multi-gate CMOS,in IEDM Tech. Dig. Dec. 2004, pp. 613-616. [3]Tri07V. P. Trivedi, J. G. Fossum, and W. Zhang, Threshold voltage and bulk inversion effects in nonclassical CMOS devices with undoped ultra-thin bodies, Solid State Electronics Journal vol. 26, no. 8, pp. 170-178, Jan. 2007. [4]Cho07M. M. Chowdhury, V. P. Trivedi, J. G. Fossum, and L. Mathew, Carrier mobility/ transport in undoped-UTB DG FinFETs, IEEE Trans. Electron Devices vol. 54, no. 1, pp. 1125-1131, May 2007. [5]His98D.Hisamoto etal .,Afolded-channelMOSFETfordeep-sub-tenthmicronera,in IEDM Tech. Dig. Dec. 1998, pp. 1032-1034. [6]Hua99X.Huang etal .,Sub50-nmFinFET:PMOS,in IEDMTech.Dig. ,Dec.1999,pp.6770. [7]Zha06W. Zhang, J. G. Fossum, and L. Mathew,The ITFET: A novel FinFET-based hybrid device, IEEE Trans. Electron Devices vol. 53, no. 9, pp. 2335-2343, Sep. 2006. [8]Mat06aL. Mathew et al ., ITFET: Inverted T Channel FET, A novel device architecture and circuits based on the ITFET, in IEEE Int. Conf. on Integrated Circuit Design and Technology May 2006, pp. 1-4. [9] Taurus-Device User Guide Synopsys, Inc., Mountain View, CA, Sep. 2004.T[10] UFDG MOSFET MODEL Users Guide (Ver. 3.7), SOI Group, Univ. Florida, Gainesville, FL, Jul. 2007. [Online]. Available: http://www.soi.tec.u.edu. [11]Tri05aV.P.TrivediandJ.G.Fossum,NanoscaleFinFETswithgate-source/drainunderlap, IEEE Trans. Electron Devices vol. 52, no. 1, pp. 56-62, Jan. 2005. [12]Chou08 aS. Chouksey, J. G. Fossum, S. Agrawal, and L. Mathew, LP-HP nanoscale FinFETCMOS design via source/drain engineering, in IEEE Int. SOI Conf. Oct. 2008, pp. 125-126. [13]Cro06A. Cros et al ., Unexpected mobility degradation for very short devices: A new challenge for CMOS scaling, in IEDM Tech. Dig ., Dec. 2006, pp. 1-4. [14]Ngu08Nguyen et al ., Direct comparison of Si/high-k and Si/SiO2 channels in advanced FD SOI MOSFETs, in IEEE Int. SOI Conf. Oct. 2008, pp. 25-26. [15]Ram06Ramos etal .,EffectivemobilityextractionbasedonasplitRFC-Vmethodforshortchannel FinFETs, in IEEE Solid-State Device Research Conf. Sep. 2006, pp. 363366.

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152 [29]Cha04V. S. Chang et al ., Optimization and scaling limit forecast of nitrided gate oxide using an equivalent nitride/oxide (N/O) stack model, in Proc. IEEE Int. Conf. Integrated Circuit Design Technology Mar. 2004, pp. 363-366. [30]Kim07S. -H. Kim and J. G. Fossum, Design optimization and performance projections of Double-GateFinFETsWithgate-source/drainunderlapforSRAMapplication, IEEE Trans. Electron Devices vol. 54, no. 8, pp. 1934-1942, Aug. 2007. [31]Aro82N.D.Arora,J.R.Hauser,andD.J.Roulston,Electronandholemobilitiesinsilicon as a function of concentration and temperature, IEEE Trans. Electron Devices vol. 29, no. 2, pp. 292-295, Feb. 1982. [32]Tri04V. P. Trivedi, J.G. Fossum, and F. Gamiz, A compact QM-based mobility model for nanoscale ultra-thin-body CMOS devices, in IEDM Tech. Dig. Dec. 2004, pp. 763766. [33]Ge02L.GeandJ.G.Fossum,Analyticalmodelingofquantizationandvolumeinversionin thin Si-lm DG MOSFETs, IEEE Trans. Electron Devices vol. 49, no. 2, pp. 287294, Feb. 2002. [34]Ge01L.Ge,J.G.FossumandB.Liu,Physicalcompactmodelingandanalysisofvelocity overshoot in extremely scaled CMOS devices and circuits, IEEE Trans. Electron Devices vol. 48, no. 9, pp. 2074-2080, Sep. 2001. [35]Tau98Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices Cambridge: Cambridge University Press, 1998, pp. 132-133. [36]Rib05G. Ribes et al ., Review on high-K dielectrics reliability issues, IEEE Trans. Device and Materials Reliability vol. 5, no. 1, pp. 5-19, Mar. 2005. [37]Kim05 bS.-H. Kim and J. G. Fossum, Nanoscale CMOS: Potential nonclassical technologies versus a hypothetical bulk-silicon technology, Solid-State Electronics Journal vol. 49, no. 4, pp. 595-605, Apr. 2005. [38]Roy06A. S. Roy, C. C. Enz, and J. M. Sallese, Compact modeling of gate sidewall capacitance of DG-MOSFET, IEEE Trans. Electron Devices vol. 53, no. 10, pp. 26552657, Oct. 2006. [39]Ban05A. Bansal, B. C. Paul, and K. Roy, Modeling and optimization of fringe capacitance ofnanoscaleDGMOSdevices, IEEETrans.ElectronDevices ,vol.52,no.9,pp.256262, Feb. 2005. [40]Yeh95P. C. Yeh and J. G. Fossum, Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology, IEEE Trans. Electron Devices vol. 42, no. 9, pp. 1605-1613, Sep. 1995. [41]Men01Meng-Hsueh Chiang, Process-based compact modeling and analysis of silicon-oninsulator CMOS devices and circuits, including Double-Gate MOSFETs, Ph.D. Dissertation, Univ. of Florida, Gainesville, FL, 2001.

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153 [42]Yin05C. Yin, P. C. H. Chan, and M. Chan, An air spacer technology for improving shortchannel immunity of MOSFETs with raised source/drain and high-k gate dielectric, IEEE Electron Device Lett. vol. 26, no. 5, pp. 323-325, May 2005. [43]N. R. Mahopatra, M. P. Desai, S. G. Narendra, and V. Ramgopal Rao, Modeling of parasiticcapacitancesindeepsubmicrometerconventionalandhigh-kdielectricMOS transistors, IEEE Trans. Electron Devices, vol. 50, no. 4, Apr. 2003. [44]Chou08 bS. Chouksey and J. G. Fossum, DICE: A benecial short-channel effect in nanosale Double-Gate MOSFETs, IEEE Trans. Electron Devices vol. 55, no. 3, pp. 796-802, Mar. 2008. [45]S. Natarajan et al ., A 32nm logic technology featuring 2nd-generation high-k+metalgate transistors, enhanced channel strain and 0.171 m m2 SRAM cell size in a 291Mb array, in IEDM Tech. Digest Dec. 2008, pp. 941-943. [46]Ghi88G. Ghibaudo, New method for the extraction of MOSFET parameters, Electronics Letters vol. 24, no. 9, pp. 543-545, Apr. 1988. [47]Lun00M. Lundstrom, Fundamentals of Carrier Transport. Cambridge: Cambridge University Press, 2000, pp. 67-72. [48]Mez04Y.M.Meziani,J.Lusakowski,W.Knap,N.Dyakonova,andF.Teppe,Magnetoresistance characterization of nanometer Si Metal-Oxide-Semiconductor Transistors, J. Applied Physics vol. 96, no. 10, pp. 5761-5765, Nov. 2004. [49]Fos82J. G. Fossum and D. S. Lee, A physical model for the dependence of carrier lifetime on doping density in nondegenerate silicon, Solid State Electronics Journal vol. 25, no. 8, pp. 741-747, Aug. 1982. [50]Gar08X.Garros etal .,GuidelinestoimprovemobilityperformancesandBTIreliabilityof advanced high-k/metal gate stacks, in 2008Symp. VLSI Technology Jun. 2008, pp. 68-69. [51]V.P.Trivedi,PhysicsanddesignofnonclassicalnanoscaleCMOSdeviceswithultrathin bodies, Ph.D. Dissertation, Univ. of Florida, Gainesville, FL, 2005. [52]S.E.Thompson,S.Suthram,Y.Sun,G.Sun,S.Parthasarthy,M.Chu,andT.Nishida, Future of strained Si/Semiconductors in nanoscale MOSFETs, in IEDM Tech. Dig. Dec. 2006, pp. 1-4. [53]S.Suthram etal .,UnderstandingstraineffectsonDouble-GateFinFETdrive-current enhancement,hot-carrierreliabilityandring-oscillatordelayperformanceviauniaxial wafer bending experiments, in 2008Intl. Symp. VLSI Technology Systems, and Applications Apr. 2008, pp. 163-164. [54]Yang-KyuChoi,Tsu-JaeKing,andChenmingHu,NanoscaleCMOSspacerFinFET for the terabit era, IEEE Electron Device Lett ., vol. 23, no. 1, pp. 25-27, Jan. 2002. [55] Sentaurus Users Guide Synopsys, Inc., Mountain View, CA, Sep. 2007.

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155 BIOGRAPHICAL SKETCH Shishir Agrawal was born in Pune, India. He received his Bachelor of Technology degree from Banaras Hindu University, Varanasi, India in 2002, M.S. degree from Rutgers University in 2005, and Ph.D. degree from the University of Florida in 2009. In the Summer of 2008, he was a summer intern in the Compact Modeling and Characterization group at Advanced Micro Devices (AMD) in Sunnyvale, CA. His research interests are in the areas of modeling and design of non-classical CMOS devices, circuits and technology.