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CMOS Diode Circuits for Wireless Radio Frequency Applications

Permanent Link: http://ufdc.ufl.edu/UFE0024215/00001

Material Information

Title: CMOS Diode Circuits for Wireless Radio Frequency Applications
Physical Description: 1 online resource (137 p.)
Language: english
Creator: Mao, Chuying
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: cmos, diode, frequency, mos, mutiplier, receive, schottky, switch, transmit, varactor
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The continuous Complementary Metal-Oxide-Silicon (CMOS) technology scaling is the driving force for lower cost, lower power, and higher data rate consumer electronics. However, with today?s nano-scale transistors, addressing the applications at the upper millimeter-wave and terahertz region are still challenging. In addition, the power performance is greatly limited by the ever decreasing breakdown voltage. This dissertation presents and demonstrates the concepts of using diodes built in CMOS without any process modifications to increase the circuit operating frequency and power handling capability beyond that limited by the transistors. Shallow trench isolated (STI) Schottky barrier diodes (SBD?s) fabricated in CMOS with cut-off frequency (fco) well over 1 THz have been previously demonstrated. By eliminating the n-well region below a Schottky contact surrounded by an STI ring, a polysilicon gate separated (PGS) SBD achieves higher fco and scales better with technology compared with a STI SBD. The measured fco of PGS SBD is improved from the previously reported value of 1.5 to ~2 THz by using an optimum layout in the UMC 130-nm logic CMOS process. A low leakage PGS SBD having a p+-n guard ring with fco of 1.5 THz is reported for the first time. Besides these, the measured reverse breakdown voltages of p-n diodes and SBD?s in the 130-nm logic CMOS process are higher than 11 V, which is ~3-4X that of MOS transistors. Therefore, it is possible to use these diodes to open up millimeter-wave and even terahertz region for low cost high volume applications. The utility of SBD?s for implementing millimeter-wave circuits is demonstrated by characterizing a varistor-mode and a varactor-mode frequency doubler fabricated in the 130-nm logic CMOS process. The varistor mode and varactor mode frequency doublers exhibit 14-dB conversion loss (CL) at 132-GHz and 10-dB CL at 125-GHz output frequency, respectively. These performances are comparable to that of the doubler fabricated in the SiGe BiCMOS process. With the CMOS Schottky barrier diodes, it should be possible to implement frequency doublers operating above 200 GHz. Using a shunt p-n diode and shunt NMOS transistors in the 130-nm CMOS technology, a single-pole-double-throw transmit/receive (T/R) switch operating at 57~66 GHz frequency band has been successfully demonstrated. The switch exhibits insertion loss of ~2 and 3 dB for TX and RX mode at 60 GHz, respectively. Measured input 1-dB compression point is limited by the measurement setup and higher than 18 dBm. Isolation is ~20 dB at 60 GHz. This suggests that it is possible to use a p-n diode in foundry CMOS like a PIN diode in millimeter-wave switches to improve their power handling capability with small impact to insertion loss. Lastly, the use of MOS varactor diodes in frequency multiplication for generating 62-GHz LO signal for a 77-GHz radar system is suggested through a simulation study. By differently biasing several shunt MOS varactors, the control voltage range over which the capacitance changes from Cmin to Cmax can be extended, which improves power handling capability compared to a single MOS varactor. In simulations, the doubler with a power amplifier can generate higher than 0-dBm output at 62 GHz.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Chuying Mao.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: O, Kenneth K.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2011-05-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0024215:00001

Permanent Link: http://ufdc.ufl.edu/UFE0024215/00001

Material Information

Title: CMOS Diode Circuits for Wireless Radio Frequency Applications
Physical Description: 1 online resource (137 p.)
Language: english
Creator: Mao, Chuying
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: cmos, diode, frequency, mos, mutiplier, receive, schottky, switch, transmit, varactor
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The continuous Complementary Metal-Oxide-Silicon (CMOS) technology scaling is the driving force for lower cost, lower power, and higher data rate consumer electronics. However, with today?s nano-scale transistors, addressing the applications at the upper millimeter-wave and terahertz region are still challenging. In addition, the power performance is greatly limited by the ever decreasing breakdown voltage. This dissertation presents and demonstrates the concepts of using diodes built in CMOS without any process modifications to increase the circuit operating frequency and power handling capability beyond that limited by the transistors. Shallow trench isolated (STI) Schottky barrier diodes (SBD?s) fabricated in CMOS with cut-off frequency (fco) well over 1 THz have been previously demonstrated. By eliminating the n-well region below a Schottky contact surrounded by an STI ring, a polysilicon gate separated (PGS) SBD achieves higher fco and scales better with technology compared with a STI SBD. The measured fco of PGS SBD is improved from the previously reported value of 1.5 to ~2 THz by using an optimum layout in the UMC 130-nm logic CMOS process. A low leakage PGS SBD having a p+-n guard ring with fco of 1.5 THz is reported for the first time. Besides these, the measured reverse breakdown voltages of p-n diodes and SBD?s in the 130-nm logic CMOS process are higher than 11 V, which is ~3-4X that of MOS transistors. Therefore, it is possible to use these diodes to open up millimeter-wave and even terahertz region for low cost high volume applications. The utility of SBD?s for implementing millimeter-wave circuits is demonstrated by characterizing a varistor-mode and a varactor-mode frequency doubler fabricated in the 130-nm logic CMOS process. The varistor mode and varactor mode frequency doublers exhibit 14-dB conversion loss (CL) at 132-GHz and 10-dB CL at 125-GHz output frequency, respectively. These performances are comparable to that of the doubler fabricated in the SiGe BiCMOS process. With the CMOS Schottky barrier diodes, it should be possible to implement frequency doublers operating above 200 GHz. Using a shunt p-n diode and shunt NMOS transistors in the 130-nm CMOS technology, a single-pole-double-throw transmit/receive (T/R) switch operating at 57~66 GHz frequency band has been successfully demonstrated. The switch exhibits insertion loss of ~2 and 3 dB for TX and RX mode at 60 GHz, respectively. Measured input 1-dB compression point is limited by the measurement setup and higher than 18 dBm. Isolation is ~20 dB at 60 GHz. This suggests that it is possible to use a p-n diode in foundry CMOS like a PIN diode in millimeter-wave switches to improve their power handling capability with small impact to insertion loss. Lastly, the use of MOS varactor diodes in frequency multiplication for generating 62-GHz LO signal for a 77-GHz radar system is suggested through a simulation study. By differently biasing several shunt MOS varactors, the control voltage range over which the capacitance changes from Cmin to Cmax can be extended, which improves power handling capability compared to a single MOS varactor. In simulations, the doubler with a power amplifier can generate higher than 0-dBm output at 62 GHz.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Chuying Mao.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: O, Kenneth K.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2011-05-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0024215:00001


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1 CMOS DIODE CIRCUITS FOR WIRELE SS RADIO FREQUENCY APPICATIONS By CHUYING MAO A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2009

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2 2009 Chuying Mao

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3 To my parents

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4 ACKNOWLEDGMENTS I would lik e to begin by expressing my deep gratitude and appreciation to my advisor, Professor Kenneth K. O, for his constant support, inspiration and encouragement. He gave me the opportunity to be part of the SIMICs group and guided me through the darkest phase to the successful conclusion of this research work. What I have learned here will benefit me for the rest of my life. I also deeply appreciate Professor William Eisenstadt, Professor Huikai Xie and Professor Oscar D. Crisalle for their interest in this work and their time commitment for serving in the committee. I would like to thank my co lleagues, Chakravartula Shas hank Nallani, Hsinta Wu, Ning Zhang, Dongha Shim and Ruonan Han for their pric eless friendship and suggestions. I am also grateful to the great guidance and inspirations of the former group members, Zhenbiao Li, Xiaoling Guo, Ran Li, Haifeng Xu, Yanping Ding, Changhua Cao, Yu Su, Chikuang Yu, Jau-Jr Lin, Dong-Jun Yang, Kwangchun Jung, Swaminatha n Sankaran and Enyoung Seok. I would also recognize other group members, Choongyul Cha, Myoung Hwang, Seon-Ho Hwang, Zhe Wang, Wuttichai Lerdsitsomboon, Kyujin Oh, Minsoon Hwang, Tie Sun, Gayathri Devi Sridharan, Teyu Kao, Chiehlin Wu, Yanghun Yun and Gyungseon Seol. I would like to thank the Semiconductor Resear ch Corporation (SRC) for sponsoring part of this work and UMC for the chip fabrication. Finally, I am grateful to my parents, my husband, my sister and her family for their unconditional love, support a nd encouragement which guided me through the challenging periods.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................4LIST OF TABLES................................................................................................................. ..........8LIST OF FIGURES.........................................................................................................................9ABSTRACT...................................................................................................................................13 CHAP TER 1 INTRODUCTION..................................................................................................................151.1 CMOS Device Comparison for Transceiver Building Block Applications.................. 161.1.1 P-n Junction Diode............................................................................................161.1.2 Schottky Barrier Diode.....................................................................................181.1.3 MOSFET........................................................................................................... 201.2 Challenges of CMOS Base d Diode Circuit Design......................................................211.3 Overview of Dissertation..............................................................................................212 CMOS DIODE DESIGN AND CHARACTERIZATION..................................................... 242.1 Introduction............................................................................................................... ....242.2 CMOS Diode Structure................................................................................................. 252.2.1 P-n Junction Diode Structure............................................................................252.2.2 Schottky Barrier Diode Structure...................................................................... 252.3 Design Optimization of CMOS Schottky Barrier Diodes............................................. 292.3.1 Dimension Optimization of Shallow Trench Isolated (STI) Schottky Barrier Diodes...................................................................................................292.3.2 Polysilicon Gate Separated (PGS) Schottky Barrier Diodes............................ 312.3.3 Schottky Barrier Di ode with Guard Ring.......................................................... 322.4 Measurement Results and Discussion........................................................................... 332.4.1 Measurement Setup...........................................................................................332.4.2 Diode Parameter Extraction Method.................................................................342.4.2.1 DC parameter extraction..................................................................... 342.4.2.2 AC parameter extraction..................................................................... 362.4.3 DC Measurement Results.................................................................................. 372.4.4 AC Measurement Results.................................................................................. 402.5 Conclusions................................................................................................................ ...443 SCHOTTKY BARRIER DIODE BASED FR EQUENCY MULTIPLIERS IN CM OS........ 463.1 Introduction............................................................................................................... ....463.2 Overview of Diode Frequency Multiplier Theory........................................................ 483.2.1 Operating Principle........................................................................................... 49

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6 3.2.2 Parameters for Frequency Multipliers............................................................... 493.2.3 Theoretical Conversion Limitations of Diode Frequency Multipliers.............. 503.3 Transmission Line Designs in CMOS.......................................................................... 513.4 Design of 130-GHz Varistor Mode Frequency Multiplier............................................ 543.4.1 Multiplier Topology.......................................................................................... 543.4.2 Schottky Barrier Diode Design......................................................................... 563.4.3 Transmission Line Design................................................................................ 573.4.4 Circuit Bias and Diode Sizing........................................................................... 583.4.5 Measurement Results........................................................................................ 593.5 Design of 125-GHz Varactor Mode Frequency Multiplier........................................... 643.5.1 Design Optimization......................................................................................... 643.5.2 Circuit Design and Simultion............................................................................ 673.5.3 Measurement Results........................................................................................ 683.6 Conclusions................................................................................................................ ...724 P-N DIODE BASED TR ANSMIT/RECEIVE SW ITCH IN CMOS..................................... 744.1 Introduction............................................................................................................... ....744.1.1 T/R Switch Parameters...................................................................................... 744.1.2 CMOS T/R Switch Design Challenges............................................................. 764.1.2.1 Low frequency T/R switch design challenges....................................774.1.2.2 Millimeter-wave T/R switch design challenges................................. 784.1.3 P-n Junction Diode T/R Switch Design Challenges.........................................804.2 Design of 60-GHz P-n Diode/MOS Transistor T/R Switch in CMOS......................... 814.2.1 Design Specifications and Switch Topology....................................................814.2.2 Circuit Design................................................................................................... 824.2.2.1 Diode biasing circuit design...............................................................824.2.2.2 Quarter-wave transformer................................................................... 864.2.2.3 Method of improving isolation...........................................................874.2.2.4 Passive components design................................................................. 914.2.2.5 Schematic of 60-GHz p-n diode /MOS transistor T/R switch............. 924.2.3 Measurement Results and Analysis.................................................................. 944.3 Conclusions................................................................................................................ .1015 LOCAL OSCILLATOR SIGNAL GENERATI ON FOR 77GHZ RADAR SYSTEM USING MOS VARACTOR FR EQUENCY DOUBLER.....................................................1035.1 Introduction............................................................................................................... ..1035.2 MOS Varactor Diode..................................................................................................1045.3 Design of 62-GHz LO Signal Generation Circuit.......................................................1085.3.1 Design Specifications and Figures of Merit....................................................1085.3.2 Method of Improving MOS Varactor Power Handling Capability................. 1095.3.3 Design of 62-GHz Frequency Doubler...........................................................1105.3.4 Design of 31-GHz Driver Amplifier (Power Amplifier)................................ 1145.3.5 LO Signal Generation Circuit Si mulation Results and Discussions............... 1175.4 Conclusions................................................................................................................ .122

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7 6 SUMMARY AND SUGGESTED FUTURE WORK.......................................................... 1246.1 Summary.................................................................................................................... .1246.2 Future Work................................................................................................................ 1256.2.1 Optimization and Characterizati on of Schottky Barrier Diodes.....................1256.2.2 Performance Improvement of 60-GHz T/R Switch........................................ 1266.2.3 Implementation and Characterizatio n of 62-GHz LO Signal Generation Circuit..............................................................................................................126LIST OF REFERENCES.............................................................................................................127BIOGRAPHICAL SKETCH.......................................................................................................137

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8 LIST OF TABLES Table page 2-1 DC parameters for diodes with a gua rd ring in the UMC 130-nm logic CMOS process................................................................................................................................38 2-2 DC parameters for PGS SBD and PGS SBD with a guard ring in the UMC 130-nm logic CMOS process. ......................................................................................................... 39 3-1 A 30 0.32 m 0.32 m STI SBD measur e ment results in the UMC 130-nm logic CMOS process...................................................................................................................57 3-2 A 38 0.64 m 0.64 m STI SBD measur e ment results in the UMC 130-nm logic CMOS process...................................................................................................................66 3-3 CMOS frequency multiplier perf orm ance summary and comparison............................... 73 4-1 Reported transistor based CM OS T/ R switches with highest IP1dB below 15 GHz..........77 4-2 Comparison of breakdown voltage for p-n diodes and MOS transistors in the UMC 130-nm logic CMOS process............................................................................................. 78 4-3 Performance comparison for reported millimeter-wave CMOS transistor T/R switches. ...................................................................................................................... .......80 4-4 Design specifications of 60-GHz p-n junction diode T/R switch. .....................................81 4-7 Performance summary for 60-GHz p-n diode /MO S transistor T/R switch in the UMC 130-nm logic CMOS process........................................................................................... 101 5-1 Comparison between thin and thic k gate oxide MOS varactors with L =0.36 m in the UMC 130-nm logic CMOS process.................................................................................106 5-2 Design specifications of 62-GHz LO signal generation circuit. ...................................... 108 5-3 Comparisons of recent published powe r am plifiers at 20~30 GHz in CMOS................ 114 5-4 Performance summary of the 62-GHz LO signal generation circuit. .............................. 122

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9 LIST OF FIGURES Figure page 1-1 TDD transceiver architecture............................................................................................. 16 1-2 Measured I-V curve comparison for a 16 cells of 0.32 m 0.32 m Schottky barrier diode and a p-n junction diod e in the UMC 130-nm CMOS technology.............. 18 1-3 Cut-off frequency improvement with time........................................................................ 21 2-1 An n-well SBD in 130-nm CMOS.....................................................................................26 2-2 Small signal equivalent circuit for an n-well SBD. ...........................................................26 2-3 Single SBD cell layout..................................................................................................... ..29 2-4 N-well parasitics versus n-well area a nd perim eter of STI SBDs in the UMC 130nm logic CMOS process.................................................................................................... 30 2-5 Polysilicon gate separated (P GS) SBD cross section and layout. ...................................... 31 2-6 Cross section of an n-well SBD with a p+-n guard ring..................................................... 32 2-7 Schottky diode DC parameter extraction method.............................................................. 35 2-8 Test structure models...................................................................................................... ...37 2-9 Current densities versus diode bias volta ge for the STI SBDs with different guard ring sizes in the UMC 130-nm logic CMOS process. Results for diodes with no guard ring and p-n diodes are also shown.......................................................................... 37 2-10 Current density comparison for PGS SBD, PGS SBD with lguard = 0.18 m, STI SBD and STI SBD with lguard = 0.12 m in the UMC 130-nm logic CMOS process................ 39 2-11 Rs and Cjo versus frequency for a 16 0.4 m 0.4 m PGS SBD without a guard ring fabricated in the UMC 130-nm logic CMOS process................................................ 40 2-12 Rs and Cjo versus frequency for a 16 0.42 m 0.42 m PGS SBD with a guard ring width lguard = 0.18 m fabricated in the UMC 130-nm logic CMOS process............ 40 2-13 Zero-bias cut-off frequency fco and grading coefficient mj versus ls for STI SBDs with and without a guard ring in the UMC 130-nm logic CMOS process........................ 41 2-14 Unit cell zero-bias junction capacitance and unit cell series resistance versus ls for STI SBDs with and without a guard ring in the UMC 130-nm logic CMOS process...... 42 2-15 Zero-bias cut-off frequency fco and grading coefficient mj versus ls for p-n diodes in the UMC 130-nm logic CMOS process............................................................................. 43

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10 2-16 Unit cell zero-bias junction capacitance and unit cell series resistance versus ls for pn diodes in the UMC 130-nm logic CMOS process..........................................................44 3-1 Transmission lines in CMOS............................................................................................. 52 3-2 U-shaped GCPW cross section in the 130-nm logic CMOS process................................ 52 3-3 Simulated Zo, loss and normalized d( Zo)/d( Loss ) versus signal conductor width, w for U-shaped GCPW in the 130-nm logic CMOS process...................................................... 53 3-4 Frequency doubler schematic............................................................................................55 3-5 HFSS simulated loss versus frequency for 50 and 72U-shaped GCP Ws in the UMC 130-nm logic CMOS process...................................................................................58 3-6 Varistor mode diode frequency multipli er die ph otograph in the UMC 130-nm logic CMOS process...................................................................................................................59 3-7 Measured and simulated S-parameters of the varistor mode frequency multiplier at Ibias= 500 A for each diode.............................................................................................. 60 3-8 Power measurement setup for vari stor m ode frequency multiplier................................... 62 3-9 Agilent 75~110-GHz harmonic mixer lo ss calibration and extrapolation. ........................63 3-10 Conversion loss and Pout versus output frequency at Ibias=500 A for the varistor mode frequency multiplier................................................................................................. 63 3-11 Conversion loss and Pout versus input power for 132-GHz output at Ibias=500 A for the varistor mode frequency doubler................................................................................. 64 3-12 Measurement results of mj and fco for STI SBDs with varying unit cell area in the UMC 130-nm logic CMOS process. Calc ulated theoretical efficiency and fcd are also shown.................................................................................................................................65 3-13 Simulated voltage across diode ve rsus num ber of unit diode cells................................... 68 3-14 Die photograph for varactor mode fre quency doubler in the U MC 130-nm logic CMOS process...................................................................................................................69 3-15 Measured and simulated S-parameters at Vbias= -1.5 V for the varactor mode frequency doubler..............................................................................................................70 3-16 Conversion loss and Pout versus output frequency at Vbias = -1.5 V for the varactor mode frequency doubler.................................................................................................... 71 3-17 Conversion loss and Pout versus input power for 125-GHz output at Vbias= -2 V for the varactor mode frequency doubler................................................................................ 71

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11 3-18 Conversion loss versus bias for 125-GHz out put at varying input power levels for the varactor m ode frequency doubler...................................................................................... 72 4-1 Simplified TDD transceiver architecture........................................................................... 74 4-2 MOS transistor small-signal model................................................................................... 79 4-3 Simplified schematic of a 60-GHz pn diode/MO S transistor T/R switch........................ 81 4-4 Clamping characteristics of diode...................................................................................... 83 4-5 A diode self-biasing circuit............................................................................................... .84 4-6 Equivalent circuit for the diode bias chain when TX is transmitting................................ 85 4-7 Voltage waveforms at input, node B and N when input sign al has amplitude of 3 V....... 86 4-8 Quarter-wave transformer lump ed elem ent equivalent network....................................... 86 4-9 Equivalent -network form ed by Lx and MN2 as well as MN3............................................87 4-10 Effects of Lx on TX and RX isolation in TX mode............................................................ 88 4-11 Effects of Lx on RX-ANT insertion loss in RX mode........................................................ 88 4-12 Effects of Lx on TX-ANT insertion loss in TX mode........................................................89 4-13 Effects of Lx on TX and RX isolation in RX mode........................................................... 90 4-14 Line inductor configurations with A) side view and B) top view. ..................................... 91 4-15 Line inductor HFSS simulation results..............................................................................92 4-16 A 60-GHz p-n diode/MOS tran sistor T/R switch schem atic.............................................93 4-17 Die photograph for a 60-GHz p-n diode/MOS transistor T/R switch in the UMC 130nm logic CMOS process.................................................................................................... 94 4-18 Measurement results in TX mode...................................................................................... 95 4-19 Measurement results in RX mode...................................................................................... 96 4-20 Measured and simulated output power vers us input power in TX m ode at 60 GHz......... 96 4-21 Simulation results for the switching speed of the 60-GHz p-n di ode/MOS trans istor switch when TX is transmitting 0-dBm power..................................................................97 4-22 Switching time versus input power of the switch in TX mode.......................................... 98

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12 4-23 Equivalent circuits of the diode bias chain. .......................................................................99 5-1 A 77-GHz heterodyne receiver prototype........................................................................ 104 5-2 Layout and a cross sec tion for a MOS varactor. ..............................................................105 5-3 Equivalent circuit for a MOS varactor. ............................................................................ 105 5-4 Thick gate oxide MOS varactor model fitting using a Verilog-A code in Cadence. ....... 107 5-5 Proposed distributed biasing schem e for the MOS varactor............................................110 5-6 Schematic of a standalone 62-GHz frequency doubler.................................................... 111 5-7 Small signal S-parameter simulation re sults for the 62-GHz frequency doubler. ........... 112 5-8 Large signal S-parameter simulation re sults for the 62-GHz frequency doubler. ........... 112 5-9 Simulated conversion loss (CL) versus input power for the 62-GHz frequency doubler. ............................................................................................................................113 5-10 Simulated output spectrum of the 62-GHz frequency doubler at Pin=10 dBm................ 113 5-11 A mode-locking PA......................................................................................................... 115 5-12 Schematic of a mode-locki ng Class-E power amplifier. ................................................. 116 5-13 Simulated small signal S-parameters for the 62-GHz LO signal generation circuit........ 118 5-14 Simulated large signal S-parameters for the 62-G Hz LO signal generation circuit........ 118 5-15 Simulated output power at fundam ental frequency (Pf0) and second harmonic (P2f0) versus input power for the 62-GHz LO signa l generation circuit. PA output power is also shown........................................................................................................................119 5-16 Simulated output spectrum for the 62GHz LO s ignal generation circuit when Pin=10 dBm.............................................................................................................................119 5-17 Simulated efficiency versus input power for the 62-GHz LO signal generation circuit. ....................................................................................................................... .......120 5-18 Simulated output transient wave form at output with -10-dB m input power for the 62-GHz LO signal generation circuit............................................................................... 121 5-19 Simulated transient waveform across a MO S varactor with 0.1-V n-well bias with input power of -10 dBm ................................................................................................... 121

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13 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy CMOS DIODE CIRCUITS FOR WIRELE SS RADIO FREQUENCY APPICATIONS By Chuying Mao May 2009 Chair: Kenneth K. O Major: Electrical and Computer Engineering The continuous Complementary Metal-OxideSilicon (CMOS) technolo gy scaling is the driving force for lower cost, lower power, and hi gher data rate consumer electronics. However, with todays nano-scale transistors, addressing th e applications at the upper millimeter-wave and terahertz region are still challengi ng. In addition, the power performance is greatly limited by the ever decreasing breakdown voltage. This dissertation presents and demonstrates the concepts of using diodes built in CMOS without any process m odifications to increase the circuit operating frequency and power handling capability beyond that limited by the transistors. Shallow trench isolated (ST I) Schottky barrier diodes (SBDs) fabricated in CMOS with cut-off frequency ( fco) well over 1 THz have been previously demonstrated. By eliminating the nwell region below a Schottky contact surrounded by an STI ring, a polysilicon gate separated (PGS) SBD achieves higher fco and scales better with technol ogy compared with a STI SBD. The measured fco of PGS SBD is improved from the previously reported value of 1.5 to ~2 THz by using an optimum layout in the UMC 130-nm logic CMOS process. A low leakage PGS SBD having a p+-n guard ring with fco of 1.5 THz is reported for the first time. Besides these, the measured reverse breakdown voltages of p-n diodes and SBDs in the 130-nm logic CMOS

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14 process are higher than 11 V, which is ~3-4X that of MOS transistors. Therefore, it is possible to use these diodes to open up millimeter-wave and even terahertz region for low cost high volume applications. The utility of SBDs for implementing millim eter-wave circuits is demonstrated by characterizing a varistor-mode and a varactor-m ode frequency doubler fabr icated in the 130-nm logic CMOS process. The varistor mode and va ractor mode frequency doublers exhibit 14-dB conversion loss (CL) at 132-GHz and 10-dB CL at 125-GHz out put frequency, respectively. These performances are comparable to that of the doubler fabricated in the SiGe BiCMOS process. With the CMOS Schottky barrier diodes, it should be possible to implement frequency doublers operating above 200 GHz. Using a shunt p-n diode and shunt NMOS tran sistors in the 130-nm CMOS technology, a single-pole-double-throw transmit/receive (T/R) switch operating at 57~66 GHz frequency band has been successfully demonstrat ed. The switch exhibits insertion loss of ~2 and 3 dB for TX and RX mode at 60 GHz, respectively. Measured input 1-dB compression poi nt is limited by the measurement setup and higher than 18 dBm. Isolation is ~20 dB at 60 GHz. This suggests that it is possible to use a p-n diode in foundry CMOS like a PIN diode in millimeter-wave switches to improve their power handling capability wi th small impact to insertion loss. Lastly, the use of MOS varactor diodes in frequency multiplication for generating 62-GHz LO signal for a 77-GHz radar system is suggest ed through a simulation study. By differently biasing several shunt MOS varactors, the cont rol voltage range over which the capacitance changes from Cmin to Cmax can be extended, which improves power handling capability compared to a single MOS varactor. In si mulations, the doubler with a power amplifier can generate higher than 0-dBm output at 62 GHz.

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15 CHAPTER 1 INTRODUCTION The ever increasing demand for portable hi gh data rate com munications has driven research to produce transceivers at lower co st, smaller size and higher operating frequencies [1] Successful applications of Co mplementary Metal-Oxide-Semic onductor (CMOS) field-effect trans istors in the digital market [2] makes the fabrication cost mu ch lower than its bipolar and GaAs counterparts. Furthermore, as the device continues to be scaled, power consumption of CMOS circuits is lowered and their intrinsic speed is increased [3] This has m ade CMOS the dominant technology for modern radio fre quency (RF) communication applications. A simple CMOS Time Division Duplex (TDD) transceiver architecture is shown in Figure 1-1. It is composed of linear functions performed by blocks [3] such as a low noise amplifier (LNA), f ilter, T/R switch, etc. There are also signal-processing functions that can only be implemented by nonlinear elements [4] Examples include the generation of DC voltages from AC signal, as in a rectifier, and frequency conversion blocks like mixers and frequency multipliers/dividers. Power amplifiers (PAs) can either be linear or nonlinear. Tremendous works have been done to explor e the use of metal-oxide field-effect transistors (MOSFETs) to build these RF tran sceiver blocks. CMOS transceivers operating at 100 GHz and higher seem possible [5] [10] The maximum transit frequency ( ft) and maximum frequency of oscillation ( fmax) for MOSFETs may reach up to ~500 GHz by the year 2014 [11] Even with s uch transistors, addressing applica tions at upper millimeter-wave and terahertz region will be challenging if not impossible. Also th e lower breakdown voltage resulting from device scaling limits power performan ce of MOSFETs. Instead of s earching for new materials or devices for alternatives [12] [13] this resea rch investigated the possibility of using diodes built in CMOS to mitigate the problems.

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16 Figure 1-1. TDD transceiver architecture [2] Diodes are the sim plest and most fundamental devices in CMOS. The nonlinear I-V characteristic [4] is suitable for RF switch applications such as m ixer and T/R switch design. Besides this, a diode can also be used as a vol tage-controlled nonlinear ca pacitor, which is so called varicap [14] This can be us ed for harmonic generation in frequency multipliers. This chapter starts out from a comparis on of diodes and MOSFETs in a CMOS technology, the possibility of usi ng CMOS based diodes for buildi ng RF transceiver blocks is then discussed, and finally the overview of the dissertation is presented in the end. 1.1 CMOS Device Comparison for Trans ceiver Buildin g Block Applications 1.1.1 P-n Junction Diode P-n junction diodes are the sim plest nonlin ear devices in CMOS technology which are formed whenever p-type and n-type se miconductors (silicon) are in contact [15] A space-charge region called depletion region form s when elect rons diffuse from an n-type region into a ptype region. The charge variation with the applied bias in the depletion region gives rise to depletion capacitance. In addition, under a forw ard bias condition, additional charges exist to LNA ANT Image reject filter RF mixer Preselect filter PA Buffer Mixer Frequency Multiplier /Divider VCO Frequency synthesizer Base band Base band T/R switch TX RX

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17 maintain charge neutrality in the presence of excess minority carriers [16] This leads to diffusion capacitance. The diffusion capacitance like the current increa ses exponentially with the diode forward bias voltage [17] )exp(T bias T ST T D TdV V V I V I C (1-1) where, T is diode transit time, IS is the diode reverse saturation current and VT is the thermal voltage (26 mV at room temper ature). Due to this rapid incr ease of diffusion capacitance with forward bias voltage, p-n junction diodes in forward bias are not good for switching operation beyond several hundred megahertz. However, p-n junctions have some advantages. First is the lower capacitance at zero bias, where the depletion capacitance Cj dominates. Cj can be expressed as [18] jm bi R jo jV V C C )1( (1-2) bi Dor joV Nq AC 2 (1-3) where, VR is the applied reverse-bias voltage, mj is the junction grading coefficient, A is the cross-sectional area of the junction, r is the relative permittivity of silicon (= 11.8), o is the vacuum permittivity (= 8.85 10-14 F/cm), ND is the n-type doping co ncentration in silicon assuming p-type doping concentration is much bigger, and Vbi is the built-in potential. Since the built-in potential of p-n junction is around 0.7 V which is higher than that of metal semiconductor junction (around 0.4 V or less), p-n junction diode possesses smaller zero-bias junction capacitance as compared to that of Schottky diodes when the anode areas are the same.

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18 Secondly due to the high injection under large forward bias such that the injected minority carrier density is comparable with the majority concentration [19] the small s ignal resistance decreases much slower for Schott ky diode with increased bias vo ltage as shown in Figure 1-2. Besides these, p-n junction di odes have much higher breakdown voltage than MOSFETs [19] Therefore p-n junction diode is a very prom ising candidate to enhance the power handling capability of T/R switches. Chapter 4 will discuss the design details of a p-n junction diode based 60-GHz T/R switch. Figure 1-2. Measured I-V curve comparison for a 16 cells of 0.32 m 0.32 m Schottky barrier diode and a p-n junction diod e in the UMC 130-nm CMOS technology. 1.1.2 Schottky Barrier Diode Unlike p-n junction diodes, a Sc hottky barrier diode is a majo rity carrier device because the current conduction is almost entirely due to the thermal em ission of electrons (majority carriers). Thus it does not have th e charge storage effect of a fo rward biased p-n junction diode. This enables higher frequency operation of a forw ard biased Schottky barr ier diode in frequency multipliers, mixers and etc. 40 30 20 10 0 0 0.5 1.0 1.5 Schottky diode p-n junction diode Vbias (V) I (mA)

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19 In mixers, a Schottky barrier diode acts as a variable resistance or as a switch [20] The increm ental small signal conductance of the junction can be expressed as )( 1 ]}1)[exp({)()( VI nV nV V I dV d VI dV d Vgt t S (1-4) where n is the ideality of diode. The junction con ductance is proportional to the large signal junction current. Diode mixers are passive mixers which have conversion loss and require high LO power. But it has broader bandwidth as compared to MOSFET based active mixers [20] The zero-bias cut-off frequency fco is a figure of merit for mixe r diodes, which is defined as jos coCR f2 1 (1-5) where, Cjo is the zero-bias junction capacitance and Rs is the series resistance. Higher the fco, lower the conversion loss of diode mixer [20] For f requency multiplication, a Schottky diode is usually used as a varactor to achieve reactive harmonic generation [21] At high frequencies, the im por tance of minimizing parasitic series resistance and maximizing junction capacitance variation become progressively challenging. Besides the zero-bias cut-off fre quency defined in Equation (1-5), the most important figure of merit for a varactor diode is the dynamic cut-off frequency fcd: s s cdR SS CCR f 2 ) 11 ( 2 1min max max min (1-6) where, S is the elastance, or inverse of capacitance. Smin is the minimum elastance, which occurs as the junction voltage appro aches the built-in potential Vbi. Smax is the inverse of the junction capacitance at breakdown voltage. It is possible to create diodes w ith very high zero-bias cut-off frequency but poor nonlinearity due to low fcd, which makes the diode inefficient for harmonic generation. Hence, the Schottky diode characteri stics have been optimized and the details are

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20 presented in Chapters 2 and 3. Based on this, a 125-GHz frequency doubler was realized and the design considerations as well as measurements are discussed in Chapter 3. 1.1.3 MOSFET For T/R switch and passive mixer applications when a MOSFET is turned on, it is biased in triode region and acts as a linear resistor. The small signal resistance is ))(( 1tGS ox dsVV L W C r (1-7) where, is the carrier mobility, Cox is the gate capaci tance per unit area, W is the width and L is the gate length. When a MOSFET is off, the sour ce (S)/drain (D) junction capacitances as well as all the parasitic capacitances between the source and drain terminal cont ribute to the off-state capacitance. Compared to diode based switches, a MOSFET switch has the advantages of lower power consumption and a simpler bias network. Yet as discussed in section 1.1.1, the most challenging part for designing MOSFET based switch is achieving high power handling capability up to 1 W required for several wireless communication standards. When used for harmonic generation, MOSFET frequency multipliers exhibit higher conversion gain than passive diode frequency multipliers, especially at low to moderate frequencies. However, at millimeter-wave and higher frequencies, Schottky diode multipliers have better performance due to the significantly higher zero-bia s cut-off frequency. This is clearly shown in Figure 1-3 [11] [22] At present, the m aximum measured zero-bias cut-off frequency of silicon Schottky barrier diode in the 130-nm CMOS technology is about 1.5 THz, which is ~7X of that for 130-nm MOSFETs. As the technology is scaled with time, Schottky barrier diodes are expected to continue outperforming MOSFETs.

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21 Figure 1-3. Cut-off freque ncy improvement with time. 1.2 Challenges of CMOS Based Diode Circuit Design The first of all is the correct modeling of diodes. Since the diode parameters are not provided by foundries, test stru ctures must be implemented and measured. The de-embedding method affects the accuracy of diode model. Ca reful measurements are required to minimize measurement errors as the diode cut-off freque ncy and quality factor increases. Secondly, the diode structures must be optimized for specific a pplications such as switch, frequency multiplier, mixer and etc. Finally, a proper di ode bias scheme is essential for integrated circuit applications. Unlike MOSFETs operating in the li near region, when a diode is turned on, there is significant current flowing through the junc tion and the power consumption is non-negligible. Besides, a bias circuitry should provide high impedance to a diode when it is off. Limiting the static power consumption and presenting sufficient isolation to the diode are challenges for diode based circuit design. 1.3 Overview of Dissertation This work focuses on the design issues of CMOS based diode circuitries covering from millimeter-wave frequency multipliers to T/R switc hes. The successful realization and evaluation CMOS peak ft CMOS peak fmax Schottky diode fco (measured)1.5 1.0 0.5 0.0 2005 201020152020 Y earFrequency (THz)

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22 of these blocks provide the support for the as sertion that CMOS based diodes are necessary components for high frequency applications. The design and characterization of Schottky barrier diodes and pn junction diodes are presented in Chapter 2. Different Schottky barrier diode stru ctures are compared. The DC characteristic comparisons among Schottky barri er diodes and p-n junc tion diodes, Schottky barrier diodes and Schottky barrier diodes with gu ard ring are presented. Th e scaling of zero-bias cut-off frequency and junction grad ing coefficient with unit Schottky anode area is also studied. Based on the measurements of diodes, a 130-GH z varasitor-mode diode frequency doubler using a Schottky barrier diode with high fco is demonstrated in 130-nm CMOS. It achieves 14-dB conversion loss and -11-dBm out put power at 132 GHz. To in crease conversion efficiency further, an optimized diode structure is utili zed to demonstrate a 125-GHz varactor-mode diode frequency doubler in 130-nm CMOS. It exhibits 10-dB conve rsion loss and -1.5-dBm output power at 125 GHz. Design considerations and simulation results are discussed in Chapter 3. By exploiting the high breakdown voltages and cut-off frequency of p-n junction diodes, a 60-GHz hybrid p-n diode/MOS tran sistors T/R switch is experi mentally demonstrated. The switch exhibits ~2and 3-dB insertion loss at 60 GHz in TX and RX mode, respectively. The measured input referred 1-dB compression point limited by the meas urement setup is higher than 18 dBm. The isolation is ~20 dB at 60 GHz in TX mode. The diode bias ing circuit and method of improving the isolation are presented in Chapter 4. In Chapter 5, a distributed bias technique to increase the power handling capability of conventional MOS varactor diodes is investigat ed through simulation. The detailed bias method and MOS varactor modeling are discussed. The design of a 62-GHz fre quency doubler using the distributed biased MOS varactor diodes is presented. By combining with a 31-GHz power

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23 amplifier, the doubler is able to generate a 1dBm 62-GHz output signal in simulation which can be used as the LO signal for a 77-GHz radar system. Finally, the dissertation is summ arized and possible future works are suggested in Chapter 6.

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24 CHAPTER 2 CMOS DIODE DESIGN AND CHARACTERIZATION 2.1 Introduction Schottky diodes and p-n juncti on diodes are the simplest nonlinear devices in a CMOS technology. Although transistors are favored due to the inherent is olation between the input and output ports [23] diodes have found their p laces in Elect rostatic-Discharge (ESD) protection [24] frequency conversion and m ixing [25] RF signal rectificati on and photo-detection [26] [27] Schottky Barrier Diodes (SBDs), being the m ajority carrier devices, are well known for their high frequency operation capability. There have been extensive researches on their applications in high speed co mmunication and radar technology [28] Silicon Schottk y barrier diode development has received less attention than its III-V compound p eers, due to the low mobility of silicon and a lower bandgap resulting in higher leakage current [29] Yet as driven by the high lev el of integration and lower fabricatio n cost, silicon Schottky barrier diodes fabricated in mainstream silicon technology ar e starting to receive more atte ntion. Schottky diodes with zero-bias cut-off frequencies up to 1 THz have been demonstrat ed on high-resistivity silicon substrates by growing a thin Molecular B eam Epitaxial (MBE) layer on top of an n+ layer [28] [30] [31] Schottky con tacts in CMOS have been real ized by directly contacting an n-well with Aluminum metallization [32] Schottky barriers have also been im plemented by blocking n+/p+ implantation in selected diffusion regions in CMOS [33] [34] Using the sam e approach, CoSi2n-Si and CoSi2-p-Si Schottky diodes with extrapolated zero-bias cut-off frequencies of ~1.5 and 1.2 THz have been reported [35] SBD diodes with cut-off frequency of 1.1 THz with low leakage have also been realized in a 130-nm SiGe BiCMOS technology [36]

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25 This chapter will discuss the layout and design of CMOS SBDs as well as p-n junction diodes. Optimizations of CMOS SBDs in combin ation with a p-n junctio n guard ring to reduce reverse leakage current, and w ith polysilicion gate to increase zero-bias cut-off frequency are also discussed. DC and AC performances are ch aracterized and presented at the end of this chapter. No additional masks or other process m odifications are needed to fabricate SBDs and p-n junction diodes in CMOS. These low cost and high volume production diodes are not only useful for Very Large Scale Integration (VLSI) ci rcuit applications, but also for millimeter wave and even THz region applications. 2.2 CMOS Diode Structure For integrated circuit applications, p-n junc tion diodes and SBDs have the same physical dimensions. Both diodes have a square shape anod e. Special attention has paid to optimize their high frequency performance. 2.2.1 P-n Junction Diode Structure P-n junction diodes have two kinds of vari ants in CMOS process, which are an n+-p diode and a p+-n diode in n-well. An n+-p diode is composed of a heavily doped n-type region and the p-type substrate [37] and vice versa for a p+-n diode. Because in CMOS, substrate is usually ptype doped and is always grounded, for an n+-p diode, the bias can only be applied to the n+ terminal. Therefore p+-n diodes in n-well are designed and utilized as described in Chapter 4. For the same reason, there is greater flexib ility for how SBDs in n-well are used. 2.2.2 Schottky Barrier Diode Structure In modern CMOS technology, metallizing the source/drain junctions with silicide can reduce contact resistance and lateral spread ing resistance due to the shallow junction [38] A cross-sectio n view with current flowing path (dashed arrows) and layout of an n-well SBD in 130-nm CMOS are shown in Figure 2-1 [22] The Schottky anode is formed by directly

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26 contacting an n-type semi conductor region with CoSi2 using copper metallization, while the cathode connection is realized by an oh mic contact between heavily doped n+ regions and silicide. Figure 2-1. An n-well SBD in 130-nm CMOS. A) Cross section and B) layout. Figure 2-2. Small signal equivale nt circuit for an n-well SBD. Figure 2-2 also shows the small sign al equivalent model for an SBD [22] The paras itic components in this SBD struct ures are series resistance Rs, side-wall capacitance Cp, n-well to pCpRsCj (V) gj (V) Cnw Rnw Cp: Sidewall parasitic capacitance Rs: Series resistance Cj (V ): Junction capacitance gj (V ): Junction conductance Cnw: n-well to p-substrate diode capacitance Rnw: n-well to p-substrate diode parasitic series resistance p -substrate Schottky terminal Cathode n-terminal n+ implant Metal n-well l2 l1 ls A B Schottky Contact/via n+ diffusion

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27 substrate reverse junction diodes series resistance Rnw and depletion capacitance Cnw. These degrade SBD performance by increasing loss as well as lowering its switching speed. Rs includes all resistances between the edge of depletion region and the ohmic contact metallization. It is consisted of two components: the resistance of the undepleted region and the ohmic contact resistance [39] Studies in [22] show the contributors of Rs in Figure 2-1 A) as c sRRRRR 321 (2-1) c s nsa s STIsh nwellsh sR ll l R l l R R R 1 2 122 4 29 (2-2) where, Rsh-nwell is the n-well sheet resistance, Rsh-STI is the n-well sheet resistance under the shallow trench isolation (STI), Rsa-n+ is the salicided n+ sheet resistance, Rc is the resistance associated with contacts and vias. ls is the length of square shape Schottky anode, l1 is the STI width and l2 is the separation between th e edge of STI and n-well metal contact. Series resistance can be reduced by lowering the separation ( l1+ l2) between Schottky contact and n+ diffusion region contact. Adding multiple cont acts on the diffusion region can reduce Rs further. But this increases the n-well size which results in bigger Cnw and lower n-well node impedance hence shorting signal to ground at high frequencies when the diode is series connected. The junction capacitance of SBD has similar e xpression as the depletion capacitance of p-n junction diodes. The difference is that SBD does not have di ffusion capacitance under forward bias condition since there is no minority-charge storage effect [15] pjTCCC (2-3) jm bi jo jVV C C )/1( (2-4)

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28 bi SiD sjoV qN lC 22 (2-5) where, Cjo is the zero bias junction capacitance, q is the charge on an electron, ND is the n-well doping density, Si is the permittivity of silicon, Vbi is the built-in potential, Cp is the metal-tometal sidewall parasitic capacitance and mj is the junction grading coefficient. The junction coefficient characterizes the nonlinearity in a CV curve of diode, which also affects the dynamic cut-off frequency in Equation (1-6) for frequency multipliers. mj is lowered by the parasitic capacitance Cp in Figure 2-2. This capacitance which is almost independent of bias decreases the sensitivity of total capacitance to diode bias voltage. To reduce Cp, the metal connections to Schottky and n+ diffusion must be spaced wide apart. As discussed in Chapter 1, a figure of merit of mixer diode is zerobias cut-off frequency jos coCR f2 1 (2-6) To increase fco, the product of Rs and Cjo needs to be reduced. Equations (2-2) and (2-5) indicate that Rs is roughly proportional to 1/ ls and Cjo is proportional to ls 2 [22] Thus fco increases as ls decreases, which means maximum fco is determined by the minimum allowable length of ls set by specific technology. However, from the current flowing path in Figure 2-1, another important factor affecting fco not considered in the previous equati ons is the thickness of the STI layer. According to High Frequency Structural Simulato r (HFSS) simulation, the series resistance is dominated by the resistance of the region surrounded by STI, which contributes to R1 shown in Figure 2-1 A). Thus Equation (2 -2) should be modified to c s nsa s STIsh s JSTI nwellsh nwellsh sR ll l R l l R l xd R R R 1 2 1 222 4 29 (2-7)

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29 where, dSTI is the STI thickness and xJ is the n-well depth. The increase of fco by scaling down of technology node from study in [22] needs to be modified. To achieve impressive fco, the nonlinearity of C-V characteristics for SBDs was sacrificed. The effect of Cp on total diode capacitance increases as ls decreases, and this desensitizes the capacitance to the diode voltage variation, which results in low mj. Therefore for varactor operation of SBDs discussed in Ch apter 3, a diode with larger ls is chosen to obtain a better combination of fco and mj. 2.3 Design Optimization of CMOS Schottky Barrier Diodes 2.3.1 Dimension Optimization of Shallow Trench Isolated (STI) Schottky Barrier Diodes The analysis in 2.2.2 shows that the zero-bias cut-off frequency of SBD is limited by series resistance Rs and side-wall para sitic capacitance Cp for a fixed Schottky anode area. Figure 2-3. Single SBD cell la yout. A) Top view and B) typi cal interconnection scheme [22] The controlling variables for Rs include l1, ls, and l2 in Equation (2-2), as well as l3, the separation between parallel SB D unit cells in Figure 2-3 [22] Since the n -well sheet resistance B A

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30 under the shallow trench isolation Rsh-STI is much higher than the salicided n+ sheet resistance Rsan+, Rs monotonically increases with l1. Thus, l1 is set to the minimum length allowed by the design rule. Rs is also lowered by decreasing l2, but this will increase the side-wall capacitance since Schottky anode metal trace is getting closer to the n-well contact metal. Five diode test structures with different combinations of l2 and l3 are fabricated in the UMC 130-nm CMOS process and the AC measurement results are compared [22] All thes e diodes keep the same Schottky anode area of ~1.64 m2 (16 cell of 0. 32 m 0.32 m). Measurements indicate the optimum l2 is between 0.7 ~ 1.1 m, and l3 should be greater than 0.6 m [22] to increase fco. Figure 2-4. N-well parasitics versus n-well area and perimeter of STI SBDs in the UMC 130nm logic CMOS process. A) N-well capacitance and B) n-well resistance. The effects of l2 and l3 on diode n-well parasitics are analyzed by fitting the measurement data in Figure 2-4 using linear regression. The independent variables contro lling n-well parasitics are n-well perimeter and area which are related to l2 and l3. The results are shown as Equations (2-8) and (2-9), where the units of Areanw and Perimeternw are m2 and m, respectively. nw nw nwPerimeter Area C 6.01.02.4 (2-8) nw nw nwPerimeter Area R 5.06.02.156 (2-9) A Cnw (fF) 60 40 20 40 60 80 100 120140 A rea (m 2 ) 30 40 50 60 Perimeter (m) Cnw vs Area Cnw vs Perimeter 40 60 80 100 120 140 A rea (m 2 ) 30 40 50 60 Perimeter (m) 100 80 60 40Rnw ( ) Cnw vs Area Cnw vs Perimeter B

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31 N-well parasitic capacitance is mostly depende nt on n-well perimeter in Equation (2-8). This indicates the n-well to p-type substrate side-wall capacitance dominates and is probably due to the fast drop of doping concentration from the surface to the junction depth of n-well. Equation (2-9) shows that n-well series resistan ce is almost equally dependent on the well area and perimeter. Hence to decrease n-well parasiti cs, a well shape with bigger area to perimeter ratio is desired, which means n-well needs to be more like a circle or a square. 2.3.2 Polysilicon Gate Separated (PGS) Schottky Barrier Diodes Figure 2-5. Polysilicon gate separated (PGS) SBD cross section and layout. As discussed, the dominant part in series resistance Rs shown in Figure 2-1 is R1, which is the resistance of the region surrounded by STI. To further decrease Rs besides optimizing SBDs layout, a new diode configuration that reduces or eliminates this region is necessary. Such a structure is a polysilicon gate sepa rated (PGS) SBD shown in Figure 2-5 [22] This new topology reduces s eries resistan ce by not only decreasing R1 but also R2. l1 changes from 0.22 m for the conventional SBD to the minimum gate length of ~0.12 m for the PGS SBD in 130-nm CMOS. Furthermore, the region under the STI which sets R2 is replaced by the lower sheet resistance ls l 2 Poly ring l1= 0.12 um n+ diffusion n+ implant n-terminal Schottky terminal CoSi2-Si Schottky Contact ILD ILD ILD ILD STI STI Polysilicon seperator l1 l1 ls l2 l2

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32 region under the gate oxide. The current flow pa th (dashed arrows) in Figure 2-5 clearly demonstrates the series resistance reduction mech anism. A drawback of PGS SBD is a larger anode area required by the polysilicon to source/drain contact spacing than that for the diffusion overlap of a contact. Another disadvantage is higher reverse leakage current than that of conventional SBD. 2.3.3 Schottky Barrier Diode with Guard Ring Figure 2-6. Cross section of an n-well SBD with a p+-n guard ring. Schottky barrier diode is renowned for its low barrier height which makes it well suited for low-power applications. However, this and the sharp electrode edge effect [40] increase reverse leakage current. To improve its reverse bias performance, Schott ky diodes with a guard ring have been introduced [41] For the PGS SBD in the 130-nm CMOS process, a guard ring is even more critical since it has higher leakage current than STI SBD. Figure 2-6 shows the cross section and layout of an n-well SBD with p+ diffused guard ring [22] This diode is a hybrid of Schottky barrier diode and p-n junction diode. The anode of p-n junction diode formed between p+ guard n-terminal Schottky terminal CoSi2-Si Schottky Contact Rc Rc Rc Cp Cp ILD ILD ILD ILD STI STI STI STI R3 R3 R2 R2 R1 Cjo n+ n+ p+ p+ lguard lguard

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33 ring and n-well is effectively s horted with Schottky anode by CoSi2. The Schottky barrier, formed in the interior of the ring, is electricall y contacting the p-n junction so that the sharp edge effect around the periphery of th e metal is reduced, thus the reverse leakage current is lowered. The composite characteristic is dominated by the p-n junction at high forward voltages when there are appreciable minority carrier charges injected by the p-n junction [42] This will lim it the high-speed switching operation at high-current levels. At low fo rward bias, I-V characteristic is essentially that of an SBD and the switchi ng speed is not limited by the minority charge storage effect. The diode junction capacita nce is increased due to the guard ring. 2.4 Measurement Results and Discussion 2.4.1 Measurement Setup To improve the measurement accuracy, severa l unit cells of square type diodes are connected in parallel. For circuit applications which will be discussed in subsequent chapters, diodes are all configured like this to reduce the effective series resistance. The key point that determines the number of parallel cells in test structures is making the total Rs to be sufficiently larger than the contact resistance (1~2 ) of the high frequency probe [22] Also, the total d iode capacitance should not be significantly smalle r than the bond pad parasitic capacitance. For the structures fabricated in the UM C 130-nm CMOS, one port measurement using small bond pads (50 m 54 m) is utilized due to the simplicity, small area and low parasitic capacitance. The signal pad uses a small bond pa d where the top metal layer (metal 8) is connected to signal and is supported by a stack of metal 6, metal 4, as well as metal 2 to satisfy the mechanical strength requirement [22] Besides, a poly ground shield is utilized to reduce the loss through substrate. T he measured bond pad ca pacitance is around 26 fF in the 130-nm CMOS which is about a half of that for the conve ntional bond pad (76 m 64 m) capacitance (~ 48

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34 fF) in the same process. The ground pad also uses this small bond pad but the ground connection of metal 1 is shunted all the way up to metal 8 through vias. Diode I-V characteristics are measured using an HP 4155A semiconductor parametric analyzer. DC parameters like reverse saturation current Is, ideality factor n and barrier height B can be extracted from I-V curves. S-parameters of dedicated one-port open and short structures together with the above diode test structures are measured from 15 to 20 GHz using an HP 8510C network analyzer and GGB 40A G-S/S-G probe s. AC parameters like zero-bias junction capacitance Cjo, series resistance Rs and junction grading coeffi cient mj are extracted. The detailed procedures are discussed next. 2.4.2 Diode Parameter Extraction Method 2.4.2.1 DC parameter extraction The current in Schottky barrier diodes is mos tly due to the thermionic emission of majority carriers [37] at low bias voltage, ]1)[exp( nkT qV IIs (2-10) )exp(2kT q TAAIB effs (2-11) where, Is is the reverse saturation current, n is the ideality factor (=1 for pure thermionic emission), Aeff is the effective anode area of diode, A** is the effective Richardson constant and B is the barrier height. Most of Schottky barri er diode deviates from this ideal thermionic emission behavior, thus ideality factor of Schottky barrier diode is usually greater than 1. Although the current transport mech anism of p-n junction diodes is different, which is due to drift, diffusion and thermal recombination-genera tion of minority carriers, it has similar I-V

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35 characteristics as shown in Equation (2 -10). However, a p-n diode has smaller Is than a Schottky barrier diode due to a higher barrier height. The effect of Schottky barrier diode series resistance can be included and expressed as ] )( exp[ nk T IRVq IIs s (2-12) At sufficient large forward bias, th e ratio of minority-carrier current to total current increases in Schottky barrier diode, Equations (2-10) and (2-12) need to be modified [37] Under the forward bias condition, for V > 3kT/q but current density is sm all enough that effect of Rs is negligible, the forward bias current is [37] )exp( nkT qV IIs (2-13) Figure 2-7. Schottky diode DC parameter extraction method. The ideality factor can be calculated from th e slope of ln(I)-V curve which is equal to q/nkT. Is is the diode current when bias voltage is zero. Figure 2-7 shows a typical Schottky diode I-V curve with the extrapolated Is value. The barrier height can be obtained from the equation Is 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 0 0.1 0.2 0.3 V bias ( V ) I (A) Slope~60mV/decade

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36 ) / ln(2 effs BAI TA q kT (2-14) The effective Richardson constant A** is 112 A/cm2K2 for electrons and 32 A/cm2K2 for holes in silicon [43] 2.4.2.2 AC parameter extraction One-port measurement is utilized to extr act diode junction capacitance and series resistance. Dedicated open and short structur es are used to de-embed bond pad parasitic capacitance and probe contact resi stance, respectively. Figure 2-8 shows the configurations of the measured structures [44] The diode is simply modeled as junction capacitance Cj in series with parasitic resistance Rs. The extraction of diode parameters is as follo ws. First, probe contac t resistance is obtained from measurement of a short test structure. Th en this contact resist ance is subtracted from impedance of both open test structure and diode test structure. After this, the remaining admittance of open test structure is deducted from the remaining admittance of diode test structures. This procedure can be expr essed by Equations (2-15) to (2-20). short diode dZZZ (2-15) short open oZZZ (2-16) d dZY/1 (2-17) o oZY/1 (2-18) ))/(1(2 1od jYYimagf C (2-19) ) 1 (od sYY realR (2-20)

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37 Figure 2-8. Test structure models. A) Open test structure and B) di ode test structure. 2.4.3 DC Measurement Results Figure 2-9. Current densities ve rsus diode bias voltage for the STI SBDs with different guard ring sizes in the UMC 130-nm logic CMOS pr ocess. Results for diodes with no guard ring and p-n diodes are also shown. To compare the effect of p+ guard ring on the reverse leakage current of n-well STI SBDs, different sizes of guard ring (lguard = 0.12 um, 0.16 um and 0.2 um in Figure 2-7 B)) structures are constructed in the UMC 130-nm logic CMOS pr ocess. All the test structures have center Schottky area of 16 0.32 m 0.32 m. A p-n j unction diode with the same anode area is also fabricated and measured. Fi gure 2-9 shows the results. No guard STI SBD STI SBD with lguard=0.12 m STI SBD with lguard=0.16 m STI SBD with lguard=0.20 m p-n diode 1E+03 1E+00 1E-03 1E-06 1E-09 1E-12 1E-15 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 Vbias (V) Current density (A/m2) Contact resistance Open pad parasitics Contact resistance Open pad parasitics Device Under Test ( DUT ) A B

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38 By adding a p+ guard ring, the reverse leakage current of STI SBD has been reduced by a factor of 105 at -3 V, and 103 at -1 V, but the Schottky diodes with a guard ring st ill have greater than 300X of the reverse leakage current of p-n diode. The reverse l eakage current of the structure with lguard = 0.12 m is ~ 3X that of the structure with lguard = 0.16 m, and 7X that of the structure with lguard = 0.20 m. The forward conduction curre nt also drops of about 100 times for the diodes with a guard ring when the bias voltage is smaller than 0.8 V. This is due to the shrinking of effective Schottky ar ea by the lateral diffusion as we ll as changes of the barrier height. When the bias voltage exceeds around 0.8 V, p+-guard ring-n junction is turned on. The current increases rapidly with voltage. The diode with lguard = 0.20 m shows smallest current variation over the 10 measured samples. For better repeatability and to limit the increase of the diode junction capacitance, lguard = 0.18 m is chosen in future design. Table 2-1 lists the DC parameters for these diodes. The diodes with a guard ring have an ideality factor close to 1. Table 2-1. DC parameters for diodes with a guard ring in the UMC 130nm logic CMOS process Diode Ideality factor n Reverse saturation current Is (A) Barrier height B (V) No guard STI SBD 1.08 8.0e-09 0.44 STI SBD with lguard=0.12 m 1.02 4.2e-11 STI SBD with lguard=0.16 m 1.02 1.4e-11 STI SBD with lguard=0.20 m 1.02 7.0e-12 p-n diode 1.02 4.0e-17 Current densities of PGS SBD, PGS SBD with a p+-n guard ring width lguard = 0.18 m, STI SBD as well as STI SBD with a guard ring width lguard = 0.12 m fabricated in the UMC 130-nm logic CMOS process are compared in Figure 2-10. The reverse leakage current density of PGS SBD is ~ 20X that of STI SBD at -3 V and ~ 7X at -1 V. By adding a p+ guard ring, the reverse leakage current of PGS SBD is reduced by ~ 5 orders of magnitude at -3 V. The forward conduction current drops 15X for the PGS SBD with a guard ring as compared to the one

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39 without a guard ring. The PGS SB D with a guard ring has ~ 100X more leakage current than the STI SBD with a guard ring at -3 V. Figure 2-10. Current density comp arison for PGS SBD, PGS SBD with lguard = 0.18 m, STI SBD and STI SBD with lguard = 0.12 m in the UMC 130-nm logic CMOS process. Table 2-2. DC parameters for PGS SBD and PGS SBD with a guard ring in the UMC 130-nm logic CMOS process Diode Ideality factor n Reverse saturation current Is (A) Barrier height B (V) PGS SBD 1.35 1.0e-08 0.37 PGS SBD with lguard = 0.18 m 1.09 3.0e-10 STI SBD 1.08 8.0e-09 0.44 STI SBD with lguard = 0.12 m 1.02 4.2e-11 Table 2-2 lists the extracted DC parameters for PGS SBDs and PGS SBDs with a guard ring. The ideality factor of PGS SBDs is higher than that of STI SBDs, which is 1.35 compared with 1.08 for STI SBDs. This indicates th e presence of additional surface imperfections [26] for the PGS SBDs which cause the I-V curve deviate from the ideal thermionic emission behavior. Although a PGS SBD has higher leakage, adding a guard ring can effectively limit the leakage current level and also suppr ess the non-ideal behavior. PGS SBD PGS SBD with lguard = 0.18m STI SBD STI SBD with lguard = 0.12 m 1E+00 1E-02 1E-04 1E-06 1E-08 1E-10 1E-12 1E-14 -3 -2 -1 0 1 Vbias (V) Current density (A/m2)

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40 2.4.4 AC Measurement Results Figure 2-11. Rs and Cjo versus frequency for a 16 0.4 m 0.4 m PGS SBD without a guard ring fabricated in the UMC 130-nm logic CMOS process. Figure 2-12. Rs and Cjo versus frequency for a 16 0.42 m 0.42 m PGS SBD with a guard ring width lguard = 0.18 m fabricated in the UMC 130-nm logic CMOS process. Based on the discussions of section 2.3, 16 0.4 m 0.4 m PGS SBDs with optimized dimension where l2 = 1 m and l3 = 1 m are fabricated in the UMC 130-nm logic CMOS process. Figure 2-11 shows the measured Cjo and Rs over the frequency. The junction capacitance Rs Cjo 15 16 17 18 19 20 Frequency (GHz) 10 5 R s ( ) 30 20 0 10 0 Cjo (fF) Rs Cjo Rs ( ) 20 15 10 5 0 15 16 17 18 19 20 Frequency (GHz)10 5 Cjo (fF)

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41 stays relatively constant over the measured freq uency range, while series resistance has bigger variation around a mean value. Due to the high Q of diode, the impact of contact variation on the series resistance of diode is more serious, thus it is harder to get accurate measurements of Rs. The average values of Cjo and Rs over frequency in Figure 2-11 are ~10 fF and ~8 respectively. The calculated zero-bias cut-off fre quency in Equation (2-6) varies from 1.8 to 2.6 THz for multiple measurements of different samples. Figure 2-13. Zero-bias cut-off frequency fco and grading coefficient mj versus ls for STI SBDs with and without a guard ring in th e UMC 130-nm logic CMOS process. Figure 2-12 shows the measured Cjo and Rs for a 16 0.42 m 0.42 m PGS SBD with l2 = 1 m, l3 = 1.2 m and a guard ring width lguard = 0.18 m. The average values of Cjo and Rs over frequency are 26 fF and ~4 respectively. The calculated fco varies from 1.3 to 1.6 THz for multiple measurements of different samples. The measured Cjo is ~ 2.5X that of a PGS SBD without a guard ring, which is due to the increased effective anode area by ~ 3.5X (= 0.782 m2/0.422 m2). The difference of built-i n potentials between that of Schottky junction area and p+ guard ring area causes the capacitance not to s cale with the effective Schottky anode area. The series resistance is smaller than the one without a guard ring which may result from the lateral diffusion of the p+ guard ring into the undoped region unde r the polysilicon gate separated region. f co ( THz ) 1.2 0.9 0.6 0.3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ls (m) Diodes w/ a guard ring Diodes w/o a guard ring 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ls (m) m j 0.6 0.4 0.2 0 Diodes w/ a guard ring Diodes w/o a guard ring

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42 Figure 2-14. Unit cell zero-bia s junction capacitance and unit ce ll series resistance versus ls for STI SBDs with and without a guard ring in the UMC 130-nm logic CMOS process. The relationship between grading coefficient mj as well as zero-bias cut-off frequency fco and diode anode size is important for diode multipliers design. 16 0.32 m 0.32 m, 16 0.45 m 0.45 m, 8 0.64 m 0.64 m and 2 1.28 m 1.28 m STI SBDs without a guard ring as well as STI SBDs with a guard ring width lguard = 0.18 m and the same center Schottky areas are fabricated in the UMC 130-nm logic CMOS pr ocess. All the diodes have l2 = 2 m, l3 = 0.6 m. Due to use of suboptimal dimensions, these diodes exhibit poorer Q and lower zero-bias cut-off frequency. Fi gure 2-13 shows the scaling of mj and fco with Schottky anode unit cell side length ls in Figure 2-1. Figure 2-14 shows the scaling of unit cell Cjo and Rs with ls. As ls increases, zero-bias cut-o ff frequency decreases while mj goes up. For bigger harmonic generation, fco and mj need to be traded off. This will be discussed in more detail in Chapter 3. The unit cell zero-bias junction capacitance monotonically increases with ls. This is as expected from the discussion in section 2. 2. Yet, the scaling of unit cell Rs with ls is not monotonic, which implies that besides the resistance under STI (R2 in Equation (2-2)), th ere are other factors influencing Rs. When ls < 1.28 m, the diodes with a guard ring show higher zero-bias cut-off frequency than the ones without a guard ring. Th is is probably due to the relatively bigger reduction of Rs by larger diffusion area and junction depth of the guard ring than the increase of Diodes w/ a guard ring Diodes w/o a guard ring 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ls (m) Unit cell C j o ( fF ) 6 4 2 0 Unit cell R s ( ) 700 500 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ls (m) 300 100 Diodes w/ a guard ring Diodes w/o a guard ring

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43 Cjo. The diodes with a guard ring present smaller mj than those without. This is due to the decreased voltage modulation on capacitance for the p+-n guard ring. The expansion and shrinking during p+ implant mask generation causes the diode with a guard ri ng having the center Schottky area of 16 0.32 m 0.32 m to be fabricated as p-n diodes. Figure 2-15. Zero-bias cut-off frequency fco and grading coefficient mj versus ls for p-n diodes in the UMC 130-nm logic CMOS process For comparison, the relationship between grading coefficient mj as well as zero-bias cut-off frequency fco of reverse biased p-n junction diodes is also studied. 16 0.32 m 0.32 m, 16 0.45 m 0.45 m, 8 0.64 m 0.64 m and 2 1.28 m 1.28 m p-n junction diodes are fabricated in the UMC 130-nm logic CMOS process. All the diodes have l2 = 1 m, l3 = 0.6 m. Figures 2-15 shows the scaling of mj and fco with anode unit cell side length ls. The mj is very low which is below 0.15 even when the diode unit si ze increases up to 1.28 m 1.28 m which is determined by the doping profile of the p-n junc tion in CMOS. This makes the reverse biased pn diodes not suitable for frequency multiplier applications. However, the fco of these diodes are very high and they can be used as high Q capaci tors in the design. Figure 2-16 shows the unit cell capacitance and resistance of the p-n diodes. The un it cell capacitance is smaller than 2 1.5 1 0.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ls (m) fco (THz) 0 0.05 0.1 0.15 mj fco mj

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44 Schottky barrier diodes in Figure 214 which is probably due to the higher built-in potential. The unit cell series resistance is smaller than the ones in Figure 2-14 B) due to the use of optimized layout. Figure 2-16. Unit cell zero-bia s junction capacitance and unit ce ll series resistance versus ls for p-n diodes in the UMC 130-nm logic CMOS process. 2.5 Conclusions A polysilicon gate separated (PGS) SBD with zero-bias cut-off fre quency of ~ 2 THz has been realized in the UMC 130-nm logic CMOS pro cess. By replacing the STI with a polysilicon gate, the total series resistance of diode is redu ced by a factor of 2. Co mpared to an STI SBD, PGS SBDs have ~ 20X higher reverse leakage current at -3 V. A guard ri ng is essential to limit the reverse leakage current for PGS SBDs. A dding a guard ring to PGS SBDs reduces the leakage current by around five orde rs of magnitude at -3 V. This in addition, increases the junction capacitance, while decreasing the series resistance. Because of this, the drop of zerobias cut-off frequency is not as much as predicted in [22] With about 3X bigger Schottky anode area, PGS SBDs with a guard ring still have ~ 1.5 THz zero-bias cut-off frequency in the UMC 130-nm logic CMOS process. The high zero-bias cut-off frequency implies their uses in 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ls (m) 0 0.5 1 1.5 2 2.5 3 100 120 140 160 180 200 Unit cell Cjo (fF) Unit cell Rs ( )

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45 millimeter-wave and infrared circuits [8]. With optimized layout, a bigger STI SBD will achieve a better combination of zero-bias cut-off freque ncy and junction grading coefficient, which can be utilized for building a better millimeter-wave or even THz signal source. The zero-bias junction capacitance of p-n junction is smaller than that of SBD due to the higher built-in potential. This together with high breakdown voltage could make p-n diodes suitable for T/R switch applications to achieve low insertion loss as well as high power handling capability.

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46 CHAPTER 3 SCHOTTKY BARRIER DIODE B ASED FREQUENCY MULTIPLIERS IN CMOS 3.1 Introduction Terahertz frequencies, defined as spanning from 100 GHz though 10 THz [29] [45] have been gain ing extensive attenti on in recent years. This freque ncy band includes high MillimeterWave (wavelength from 1 mm to 10 mm) and Submillimeter-Wave (wavelength from 0.1 mm to 1 mm) range. Operation in this frequency re gion has many advantages for scientific and technological applications such as de tection of chemical and bio agents [46] [48] imaging of concealed weapons [49] and contraband [50] diagnosing tum or and plasma [51] observation of the atm osphere and deep-space sounding [39] as well as short range radar [52] and high data rate communications. Despite these, it has often been described as the most scientifically useful yet the least explored region of spectrum [29] One of the reasons is the lack of sign al s ources at this unique spectral region which spans the transition from conventional electronics to quantum optics. At frequencies below 100 GHz, transistor based sources and Gunn oscillators are widely used, while for frequencies above 10 THz, solid-state lasers and light-emitting diodes are employed. However, in between, neither of these technologies is particularly well suited [29] Harmonic multiplications are the key and most common approach to handle this technology gap, wh ich utilize nonlinear devices to translate the low frequency electronic signa ls into the terahertz band [29] Among all the available nonlinear devices, Schottky barrier diodes are the most wide ly used. This is because of their inherent simplicity and fast switching speed resulting from th e absence of minority carrier storage effects. Terahertz signal sources have long been realized using frequency multipliers based on IIIV Schottky barrier diodes due to their high mobility and large bandgap [29] Early m ultipliers utilized a honeycomb anode chip with a whis ker contact across a waveguide mount. The best

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47 performance has been demonstrated by Faber wi th 35% efficiency at 98 GHz output for 5 mW input [53] and Erickson with peak efficiency of 35% with 35 mW input at 79 GHz output [54] Rizzi et al. achieved peak e fficiency of 25% and peak out put power of 55 mW at 174 GHz output using a balanced com bin ation of two planar diode [55] pairs in a crossed-waveguide mount [56] More re cently, the bulky waveguide-based frequency multipliers were replaced by planar monolithic microwave integrated circuit (MMIC) multipliers for compact size and low cost. However, planar circuits have higher loss and lower Q compared to the waveguide ones. It is also more difficult to include tuning elemen ts. Even with these limitations, useful MMIC multipliers have been reported. Chen et al. successfully demonstrated a diode-based MMIC multiplier with 65 mW output power and efficien cy of 25% at 94 GHz using microstrip lines [57] A 320 GHz m icrostip based fre quency doubler has also been re alized by Bruston with 2.8% efficiency [58] Based on finite ground coplanar (FGC) lines, Brauchler et al. achieved output power of 93 mW at 80 GHz [59] Papapolym erou et al. achieve d 115 mW output power at 74 GHz with four diodes [60] and Lee et al. dem onstrated peak efficiency of 36% for 20 dBm input at 76 GHz output [61] Although III-V Schottky barrier d iode base d frequency multipliers have excellent performance at THz frequencies, their bulky si ze and high cost are two major problems that hinder the widespread of THz tec hnology. This calls for higher integration and an inexpensive solution, which necessitates th e examination for possible use of CMOS technology. CMOS SBDs with zero-bias cut-off frequency up to THz presented in Chapter 2 possess comparable performance as their III-V peers. Besides this the recent advances in CMOS have made implementation of voltage controlled oscillators [5] [6], [7], [62] [63] as well as a Schottky diode detector [8] operating above 100 GHz possible. In f act, with the scali ng, it appears that

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48 terahertz CMOS circuits will be possible [10] [64] This will potentially allow implementation of highly integrated THz imaging and spectrosco py systems for scientific, medical, military and commercial applications [29] that may cost 100s of dollars instead of 100s of thousands. To date, no multipliers operating at 100 GHz and highe r have been demonstrated in CMOS. The only one demonstrated in main stream silic on technology is the Scho ttky diode frequency doubler with conversion loss (CL) of ~14 dB at 110 GHz output frequency implemented in a 130-nm SiGe BiCMOS technology [65] [66] This chapter presents the design, analyses and m easurement results of the first mm-wave varistor and varactor mode Sc hottky diode frequency doublers fabricated in CMOS. The varistor mode frequency doubler exhibits 14-dB conversion loss and -11-dBm output power at 132 GHz, while the varactor mode freque ncy doubler exhibits 10-dB conversion loss and -1.5-dBm output power at 125 GHz. Both doublers can generate signals up to 140 GHz. These provide additional support for the assertion that CMOS technology in n ear future will not only bridge the terahertz gap, but open up the THz region for lo w cost high volume applications. 3.2 Overview of Diode Frequency Multiplier Theory Frequency multiplication in electron devices takes place due to their nonlinearities [67] For m illimeteror submillimeter-wave harmonic generation, the nonlinear devices should be fast enough to follow the rapid signal changes. Two kinds of characteristics are available to generate harmonics: nonlinear current-volta ge characteristics (nonlinear resistor) and non linear chargevoltage charactersitics (nonlinear capacitor). Correspondingly, frequency multipliers using a nonlinear resistor to generate harmonics are ca lled in varistor mode, while those using a nonlinear capacitor are in va ractor mode. Quite often, these two modes co-exist.

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49 3.2.1 Operating Principle [39] The nonlinear current-voltage and charge-volta ge characteristics can be expanded into power series about the operati ng point of DC bias voltage VB: 3 3 2 210)(vavavaavVIB (3-1) 3 3 2 210)(vbvbvbbvVQB (3-2) With input signal v = V0cos( 0t), )3cos()2cos()cos( )(0 30 20 10tItItIItI (3-3) )3cos()2cos()cos( )(0 30 20 10tQtQtQQtQ (3-4) Thus, using nonlinear devices and filters, a frequ ency multiplier is able to select a desired input harmonic in Equation (3-3) or (3-4). In general, input and output matching networks are necessary for improving selectivity and efficiency as well as ach ieving maximum power transfer. 3.2.2 Parameters for Frequency Multipliers [39] Conversion Loss and Maximum Input/Output Signal Power Diode frequency multipliers use passive devices and are inherently lossy. Matching networks also dissipate energy. Conversion loss is defined as the ratio of the available power 0P to the output harmonic power Pn delivered to the load. It is usually expressed in decibels. )log(10][0n nP P dBL (3-5) Conversion efficiency n is the ratio between Pn and0P, and is equal to the inverse of Ln. Conversion loss depends on input/output frequenc y as well as the input signal level. The maximum input signal power is limited by the power handling capability of the nonlinear devices and matching, while the maximum output power depends on the conversion loss as well as the maximum input signal power.

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50 Source and Load Impedance To achieve the maximum conversion efficien cy, optimum source and load impedances should be presented to the diode. This is quant ified by the larg e signal reflection coefficients S11/S22, which depend on the input signal level. Bandwidth Bandwidth is usually defined as the ou tput/input frequency range over which the conversion loss is sufficient for a particular appl ications. As will be discussed next, varistor multipliers are naturally broadband, while varact or multipliers usually show tuned frequency response with a narrower bandwidth. Besides the above figures of merit, harmonic contents and noise conversion properties are also important for frequency multipliers. The detailed discussion can be found in [39] In this chapte r, conversion loss, maximum output power, input matching and bandwidth will be used to characterize and compare the diode frequency multiplier designs. 3.2.3 Theoretical Conversion Limitation s of Diode Frequency Multipliers In the case of varistor mode frequency multiplier with positive nonlinear resistance [39] 20nL P Pn n (3-6) where n is the order of output harmonics. This funda mental limitation results from the real power consumption in the voltage dependent variable re sistance of diode. Since the idealized varistor multiplier does not store reactive energy, input and output tuning is not necessary, which makes it broadband [39] W hile for a varactor mode frequency multiplier, ideally, there is no energy dissipation in the nonlinear cap acitor, thus Ln = 0 dB. In reality, devices and circuits are lossy, so the

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51 conversion loss is greater than 0 dB. To increa se conversion efficiency high quality input and output matching is necessary. This however decreases bandwidth. 3.3 Transmission Line Designs in CMOS Transmission lines (TLs) are important for millimeter-wave (mm-wave) frequency multiplier designs. At mm-wave frequencies, th e reactive elements needed for matching and filtering networks become increasingly small, requiring inductance values on the order of pH [68] Transm ission lines are inherently scalable in length and are capable of realizing precise small reactance. Also the well defined ground return path greatly reduces magnetic and electric field coupling to adjacent structures, which are significant at mm-wa ve frequencies. The most commonly used transmission lines in CMOS are microstrip (MS) and coplanar waveguide (CPW) (Figure 3-1 A) and B)). An MS is usually formed by a top conductor over dielectric, silicon substrate and ground plane. A CPW consists of a cente r conductor and adjacent grounds in the same plane [69] The main loss mechanisms of CMOS transmission lines include conductor loss of the meta llization, dielectric loss and substrate loss [70] Due to the thin interlevel dielectric layer of a few microns, there is large capacitance betw een signal line and ground for an MS. Thus to achieve Zo = 50 the signal path needs to be narrow (9 m for a 6-m thick dielectric layer) resulting high conductor loss. An MS with Zo > 100 is almost impossible due to the narrow signal strips (< 1 m). While a CPW has the inherent a dvantage that it allows a wi der signal path to be used, because the physical gap between si gnal and ground which determines Zo is not set by the dielectric thickness [71] Thus a CPW has relatively lower loss and it can achieve broader Zo range than an MS. Also its balanced topol ogy makes ground-signal-groun d probing at mm-wave frequencies straightforward. Ho wever, the ground of CPW does not shield the energy leakage through the underlying lossy silicon substrate. If the gap is smaller than the dielectric thickness

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52 not to confine the electromagnetic field, there is significant loss of energy to the substrate [71] w hich is the major loss mechanism. This is demons trated by the electrical field penetrating into the substrate in Figure 3-1 B). Figure 3-1. Transmission lines in CMOS. A) MS, B) CPW, C) GCPW and D) U-shaped GCPW with electric field lines (arrows). Figure 3-2. U-shaped GCPW cross sec tion in the 130-nm logic CMOS process. To reduce the loss in the substrate for a CPW, a bottom metal ground shield used in an MS is introduced to form a grounded CPW (GCPW) [72] The return cu rrent mainly flows in the bottom thin ground shield instead of the thick co planar ground lines. Thus the conductor loss is higher at low frequencies and the distributed inductance is lower than that of a CPW. However, Signal GND GND M8 ws 5.5 m M2 M2 M1 Dielectric Layer s A B C D Signal Metal Dielectric Substrate Substrate Signal GND GND Signal GND GND Signal GND GND Substrate Substrate

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53 the lower loss at high frequencies still makes a GC PW a better choice for mm-wave applications [73] Figure 3-3. Sim ulated Zo, loss and normalized d(Zo)/d(Loss) versus signal conductor width, w for U-shaped GCPW in the 130-nm logic CMOS process. Several modified GCPW structures includi ng semi-circular stacked GCPW (S-GCPW), Vshaped stacked GCPW and regular GCPW are discussed in [73] The loss of transm ission lines can be reduced by altering the electric field under th e signal line. A semi-cir cular return path in an S-CPW has lower loss due to the more unifo rmedly distributed magnetic field beneath the signal conductor. Based on these, a modified GCPW structure is used to construct all the matching and filter networks for this work on frequency doublers. For easy layout and implementation, a U-shaped return path as show n in Figure 3-1 D) is us ed for doubler design in CMOS. Figure 3-2 shows the detailed cross s ection of U-shaped GC PW. The signal and two ground conductors are formed with the top meta l layer, and the ground conductors are connected to the ground plane formed by metal 1 and 2 layers through vias [74] Zo Loss Normalized d(Zo)/d(Loss) Z o ( ) 90 80 70 60 1.6 1.4 1.2 1.0 0.8 Loss (dB/mm) 2 3 4 5 6 w (m)

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54 Transmission lines with 50 ~ 100 characteristic impedance are necessary for input/output matching and filtering in frequency doubler design. For proper optimization, the effects of varying the ratios between ground and signal c onductor spacing (s), and signal conductor width (w) were simulated in the 3-D E-M si mulator, High Frequency Structural Simulator (HFSS). The total width of GCPW was set at 40 m in simulations to keep the chip area the same. The total thickness of dielectric la yer between the signal line and ground plane is around 5 m [74] Figure 3-3 presents the dependence of characteristic impedance and loss on the signal conductor width (w). The normalized d(Zo)/d(Loss) values are also shown. 3.4 Design of 130-GHz Varistor Mode Frequency Multiplier Although varistor mode doublers have lower th eoretical efficiency, they have larger bandwidths than their varactor mode peers. In addition, they could use smaller unit cell diodes with higher zero-bias cut-off frequency (fco) and lower junction grading coefficient (mj) for higher maximum frequency operation [75] This section w ill present the design details of varistor mode frequency multiplier built in the UM C 130-nm logic CMOS process with 14-dB conversion loss, -11-dBm output power at 132 GHz. 3.4.1 Multiplier Topology According to the way diodes are configured in a circuit, diode frequency multipliers can be divided into series and shunt type. Depending on the number of diodes used, diode frequency multipliers are further classified as single-diode and multiple-diode configurations. Single-diode frequency multipliers are easy to analyze but have limited power handling capability and sometimes inconvenient impedances. At present, single-diode frequency multipliers are mostly used as power sources at upper millimeterand submillimeter-wave frequencies where multidiode circuits are difficult to realize. Multiple -diode frequency multipliers with several diodes connected either in series or shunt improve th e power or current handling capability and provide

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55 the flexibility of varying the impedance level for improved performance. Frequency multipliers with anti-parallel or anti-series diode pairs have inherent filteri ng capability to suppress even or odd harmonics. Thus they are suitable for designi ng frequency triplers or doublers with relatively lower loss due to the simplification of filter design [39] Bridge frequency multipliers like fullwave rectifiers, can be used to obtai n even-order frequency multiplications [39] Figure 3-4. Frequenc y doubler schem atic. A choice of a frequency doubler topology depends on the de sign specifications including the maximum input handling power, input/output fr equency, etc. But more importantly, it is determined by the diode. Compared to the Schottky diodes in SiGe BiCMOS technology [36] [65] [66] due to the un availability of an n+ buried layer, the Schottky diode in CMOS is made to have a smaller unit diode cell area (0.32 0.32 ~ 0.64 0.64 m2) as compared to 1 m2 in [65] [66] and larger n+ cathode contact areas to lower the series resistance [35] These sign ificantly increase the cathode (n-well) to substrate capacitance (40 fF for a diode with 1.64-m2 anode area and 5.8-fF Schottky junction capacitance) This in combination with non-negligible substrate resistance makes use of a series topology for frequency multiplication in [65] [66] difficult in CMOS. To overcom e this, a balanced topology with two shunt diodes with grounded Input signal at fo Zo=50 Zo=50 Zo=50 Zo=50 Zo=50 Zo=50 Zo=50 Zo=50 Zo=72 Zo=72 Output signal at 2 fo Input matching stub Output matching stub L1L2Lin= /4 @ 2 fo Lin= /4 @ 2 fo Lout= /4 @ fo Lout= /4 @ fo Ydi YdoA B C

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56 cathodes [59] [61] [76] in Figure 3-4 which can increase output power is u tilized for the CMOS implementation [75] The m atching and filtering networks are formed with 50 and 72transmission lines. The 50transmission lines are used to ma tch input and output impedance to 50 while the 72transmission lines connected to the Schottky diode pair and 50transmission line provide inductive impedance to cancel out the average diode capacitance. Quarter wave open stubs at input and output are used to attenuate the s econd order harmonic and fundamental signals, respectively. Besides these, to minimize conve rsion loss, unnecessary losses of input signal power in the output networks should be avoided and the same for the output signal power [39] This can be accom plished by making 0)](Re[odofY and 0 )]2(Re[ odifY (3-7) where Ydo and Ydi are the conductance seen at node A in Figure 3-4 toward the load and source, respectively. Since the impeda nce for the second order harmonics at node B should be approximately zero, the length of L1 should be a quarter wave at the second harmonic frequency (2fo). Similarly, the length of L2 should be close to a quarter wa ve at the fundamental frequency (fo). The length of high impedance TL must be se t in such a way to maximize the fundamental power delivered to the diodes. The bond pad parasitics are tu ned out by the input and output matching stubs, respectively. DC bias is applie d to the input of the circuit through a 1.2-k onchip polysilicon resistor [74] 3.4.2 Schottky Barrier Diode Design The heart of every frequency multiplier ope rating higher than 100 GHz is a Schottky diode. The performance of diode determines the intrinsic efficiency (c onversion loss), and the maximum output power the multiplier can achieve [57] A theoretical analysis relates the

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57 multiplier maximum conversion efficiency to the diode zero-bias cut-off frequency (fco) and fco >> fn is required for high c onversion efficiency, where fn is the desired output harmonic frequency [39] Thus for this first CMOS diode frequency multiplier design, use of a STI SBD with high zero-bias cut-off fr equency is investigated. Table 3-1. A 30 0.32 m 0.32 m STI SBD measurement results in the UMC 130-nm logic CMOS process Series resistance Rs ( ) Zero-bias junction capacitance Cjo (fF) Grading coefficient mj Zero-bias cut-off frequency fco (THz) Saturation current Is (nA) Ideality factor n 14 15 0.2 0.8 4.3 1.08 From the discussion in section 2.2.2, for STI SBDs fabricated in CMOS, the zero-bias junction capacitance Cjo is approximately pr oportional to the devi ce cross section area As, while Rs is roughly proportional to As -0.5. These indicate that decreasing As will increase fco [35] Therefore, a diode with ls = 0.32 m, which is the minimum allowable length in the 130-nm CMOS, is used for this doubler design. Ho wever, this small unit size diode has low mj due to the effects of para sitic capacitance Cp in Figure 2-2 on the total diode capacitance. To mitigate this, the separation of Schottky a node and n-well contact metals, l2 in Figure 2-1 is set to 2 m. Besides this, the top metal layer (metal 8) is us ed to connect the anodes of unit diode cells, while the n-well contact is formed by shunting the two lowest metal layers to lower the parasitic capacitances. However, a larger l2 causes the diode series resistan ce to increase. Table 3-1 lists the measurement results for a 30 0.32 m 0.32 m STI SBD. The diode exhibits fco of ~0.8 THz and mj of ~0.2 [75] 3.4.3 Transmission Line Design To match 50input and output, a 50U-shaped GCPW was utilized. For the transmission lines connecting to the diode pair, higher characteri stic impedance is desired. A higher Zo line is more inductive at given length so that a shorter transmission lines with lower

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58 total loss can be used to tune out the capacitance of th e diodes. This increases the voltage swing seen by the diode which typically increases the conversion efficien cy both for varistor mode and varactor mode operation. However, if the total width of GCPW (2s + w) is fixed to keep the area constant, a high Zo transmission line has higher loss due to the narrower signal conductor required [70] Figure 3-5. HFSS si mulated loss versus frequency for 50 and 72U-shaped GCPWs in the UMC 130-nm logic CMOS process. From Figure 3-3, since the fr equency doubler using the U-shap ed GCPW with w = 4 m/s = 18 m (Zo = 72 ) has the minimum loss, this structure was chosen for the high characteristic impedance line connecting to the diode pairs. The simulated loss versus frequency plots for the 50 and 72U-shaped GCPWs are shown in Figure 3-5. Compared to the microstrips used in the BiCMOS technology [65] [66] [77] the loss is approxim ately 0.2 dB lower at 70 GHz for the 50transmission line despite the use of th inner metal layers in the foundry CMOS [74] 3.4.4 Circuit Bias and Diode Sizing Using the diode models extracted from meas urements and transmission line models from HFSS simulations, harmonic balance and S-parameter simulations were performed in Agilent Loss (dB/mm) 2.5 2.0 1.5 1.0 0.5 0 50 100 150 200 Frequency (GHz) Zo = 72 Zo = 50

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59 Advanced Design System (ADS) to determine the optimum diode size and transmission line lengths as well as the proper DC bias for the diode [74] Input power level and mj determine the bias point a nd diode size for the maximum efficiency. Since at the time of design, the maximum power from V-Band sources (Gunn oscillator) available in the rese arch group is less than 5 dBm in cluding the loss of cables, 5-dBm input power is chosen for simulation to optim ize conversion efficiency. This power level together with the low mj results the multiplier to exhibit higher efficiency in the varistor mode. Forward biasing the diode improves the conversion effi ciency from less than 1% at -0.6 V bias to 2% at 500 A forward bias for each diode pum ped by 5-dBm input signal at 70 GHz. The optimum diode size is a 5 by 6 array of 0.32 0.32 m2 diode unit cells with 14series resistance and 15-fF zero-bias Schottky junction capacitance [75] 3.4.5 Measurement Results Figure 3-6. Varistor mode di ode frequency multiplier die phot ograph in the UMC 130-nm logic CMOS process. A photograph of the fabricated chip and the di ode array are shown in Figure 3-6. The total die area is ~1.05 mm 1.03 mm. The active ar ea including those of the diode and main

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60 transmission lines is ~ 0.25 mm2. Most of the area is occupied by the ground plane formed by shunting metal 1 up to metal 8 layers. Figure 3-7. Measured and simulated S-parameters of the varistor mode frequency multiplier at Ibias= 500 A for each diode. The S-parameters of doubler were measured using an Agile nt E8361A network analyzer. A pair of GGB 110H-GSG-150P probes was used to measure the doubler from 40 to 100 GHz. Measurements above 110 GHz are not available because the maximum operating frequency of network analyzer is limited to 110 GHz. Figur e 3-7 shows the simulated and measured |S11| and |S22| |S11| |S21| S-parameters (dB) 0 -5 -10 -15 -20 40 60 80 100 Frequency (GHz) Measurement Simulation S-parameters (dB) 40 60 80 100 Frequency (GHz) Measurement Simulation 0 -20 -40 -60

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61 |S22| at Ibias = 500 A for each diode. The measured a nd simulated behaviors agree well. Input matching |S11| is below -10 dB between 62 and 70 GHz, wh ile the isolation of fundamental signal at the output 1/|S21| is greater than 14 dB from 62 to 70 GHz. A power measurement set up shown in Figure 38 was constructed to measure the output harmonics of the doubler. The input signal from th e Agilent E8361 network analyzer is amplified by two Terabeam HHPAW-071 V-band power amplif iers and then fed to the doubler through a GGB 67A-GS-150P probe. Meanwhile, a GGB 120-GHz ground-signal wa veguide probe was used to connect the output to an Agilent E 4448A spectrum analyzer through an Agilent 75~110GHz harmonic mixer. The gain of input chain including cables and power amplifiers as well as input probe has been calibrated from 55 to 67 GHz for varying power levels using an OML M15HWD 50~75-GHz harmonic mixer and an HP 8563E spectrum analyzer. Due to the linearity and saturation power limitation of the power amplifier and OML mixer, the maximum calibrated power that can be provided to the frequency doubler is 8.5 dBm at frequencies between 55 and 67 GHz [74] The frequency response of Ag ilent 75~110-GHz harm onic mixe r has been characterized with an ELVA-1 75~110-GHz power meter from 75 to 110 GHz. The loss of mixer from 110 to 125 GHz was linearly extrapolat ed from the measured data. The calibrated as well as extrapolated loss is shown in Figure 3-9. The standard de viation of harmonic mixer loss measurements over multiple calibrations is less th an 1.2 dB at each frequency point. At 132 GHz the estimated loss is ~5 dB higher than that at 110 GHz. In reality, the loss will be even higher due to propagation of multiple modes in the waveguide of harmonic mixer above 110 GHz [78] The output probe loss was assum ed to be the same as that at 110 GHz (~1.6 dB from the data

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62 sheet). Once again, the actual loss is expected to be higher. Thus, the de-embedded power and conversion gain are lower than the actual [75] Figure 3-8. Pow er measurement setup fo r varistor mode frequency multiplier. The diodes are biased using an exte rnal power supply through the 1.2-k on-chip nonsilicide polysilicon resistor. The optimum bi as for each diode is around 500 A, corresponding to 0.4-V forward bias (close to diode turnon voltage) for 2-dBm input pump power at 132 GHz output frequency. Figure 3-8 al so shows the measured output spectrum at 132 GHz over 1 MHz span. The spectrum is well defined, as well as showing the skirt associated with the phase locked input signal. Using the frequency extension module of network analyzer, the frequency of input signal was swept up to 75 GHz at input power le vel of ~ 8 dBm. Outputs at frequencies up to 140 GHz have been observed. Figure 3-10 shows the conversi on loss (CL) and output power versus the output frequency at three different i nput power levels. The maximum output power and minimum CL occur around 130 to 132 GHz. These sugges t that the output is matche d at ~130 GHz. The ringing in the CL plots is most likely due to the variation of PA match (Fi gure 3-8) with frequency. The 3-

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63 dB bandwidth is ~6 GHz from 128 to 134 GHz. Th e measured CL and output power versus input power at 66 GHz input/132 GHz output are shown in Figure 3-11. The minimum CL of 14 dB occurs at input power of 2 dBm, corresponding to 4% efficiency. The maximum output power is ~ -11 dBm at 132 GHz. The simulation and measurement results match reasonably. The increase of CL at higher power is due to the increase of diode curren t dependent series resistance [79] Figure 3-9. Agilent 75~ 110-GHz harmonic mixer loss calibr ation and extrapolation. Figure 3-10. Conversion loss and Pout versus output frequency at Ibias=500 A for the varistor mode frequency multiplier. Pin= -7 dBm Pin= -2 dBm Pin= 3 dBm CL Pout 3-dB BW CL (dB) 30 20 10 0 120 125 130 135 Output frequency (GHz) 40 20 0 -20 -40 Pout (dBm) 55 50 45 40 35 75 95 115 135 Measurement Extrapolation Frequency (GHz) Multiple measurements variation max = 1.2 dB W-band harmonic mixer loss (dB)

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64 Figure 3-11. Conversion loss and Pout versus input power for 132-GHz output at Ibias=500 A for the varistor mode frequency doubler. 3.5 Design of 125-GHz Varactor Mode Frequency Multiplier In the previous section, the first mm-wave varistor mode di ode frequency doubler fabricated in 130-nm CMOS exhi bits comparable conversion loss (~14 dB) at 132 GHz as that at 110 GHz for the doubler fabricated in a 130-nm SiGe BiCMOS process. The maximum output power (-11 dBm) is ~10 dB lower than that in [65] and [66] Therefore, the doubler was further optim ized. This section discusses the details of optimization effort, which result a varactor mode diode frequency multiplier in the 130-nm CMOS with -10-dB minimum CL and -1.5-dBm maximum output power at 125 GHz. 3.5.1 Design Optimization From the analysis in 3.2.3, the operation mode of diode in frequency multipliers is a critical factor determining the intrin sic efficiency. The theoretical CL is n2 (n is the output harmonic order) for varistor mode frequency multipliers, while 0 dB for varactor mode ones. Consequently, varactor m ode operation is chosen for this improved design. CL Pout CL (dB) Pout (dBm) 40 30 20 10 -15 -5 0 10 -50 -40 -30 -20 -10 0 Pin (dBm) Measurement Simulation

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65 Figure 3-12. Measurement results of mj and fco for STI SBDs with vary ing unit cell area in the UMC 130-nm logic CMOS process. Calc ulated theoretical efficiency and fcd are also shown. In this mode, a diode is reverse biased and the voltage modulation on Schottky junction capacitance causes reactive multiplication [21] The junction grading coefficient, mj is a dominant factor determining the varact or mode conversion efficiency. Higher mj is desired to reduce conversion loss. For Schottk y diodes fabricated in CMOS, mj is degraded by the parasitic capacitance Cp in Figure 2-2 between the Schottky contac t metal lines and n-well as well as its contact metals. This capacitance which is almost independent of bias decreases the sensitivity of total capacitance to diode bias voltage. Since a diode with a larger unit cell area requires less interconnects at given capacitance, such a diode has higher mj. Figure 3-12 shows the measured mj for multiple square STI SBD test structures with different unit area, which is consistent with the above discussion [74] All the diode structures have l2 = 2 m and l3 = 0.6 m. Besides mj, zero-bias cut-off frequency fco is another factor which affects the conversion efficiency. To achieve low conversion loss, fco >> fn is desired [39] The analysis in section 2.2.2 theoretical efficiency f co mj mj and theoretical efficiency 0.6 0.4 0.2 0 0.1 1 10 0 1.0 2.0 3.0 fc (THz) Diode unit cell Schottky area (m2) f c d

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66 shows that decreasing diode unit cell area As will increase the fco. Yet the impact of Cp increases and this degrades mj. Therefore, mj and fco must be properly traded off. Table 3-2. A 38 0.64 m 0.64 m STI SBD measurement results in the UMC 130-nm logic CMOS process Series resistance Rs ( ) Zero-bias junction capacitance Cjo (fF) Grading coefficient mj Zero-bias cut-off frequency fco (THz) Saturation current Is (nA) Ideality factor n 4.7 50 0.49 0.7 4.75 1.03 According to [80] for a fully-driven diode operating in the varactor m ode (the voltage swing across a diode is from the breakdown to turn-on voltage), the maximum conversion efficiency of the diode is c j c jmB mB )(1 )(1 (3-8) where, c is the cutoff frequency at br eakdown voltage of the diode, is the fundamental frequency. B(mj) is a monotonically decreasing function of mj for its value less than 0.6, which is the case for the integrated Schottky diode structur e. The calculated theoretical efficiency based on (3-8) and dynamic cut-off frequency fcd are also shown in Figure 3-12. Since the diode with unit cell area As of 0.64 m 0.64 m has highe st theoretical efficiency and fcd, a diode with this unit cell area was chosen for this design with optimized dimension of l2 = 1 m and l3 = 0.6 m. Similar to the diode design for varistor mode ope ration, to reduce the parasitic capacitance, the top metal layer (metal 8) is used to connect the anodes of unit diode ce lls, while the n-well contact is formed by shunting the two lowest metal layers. Table 3-2 lists the measured parameters for a 38 0.64 m 0.64 m diode in the UMC 130-nm logic CMOS process.

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67 3.5.2 Circuit Design and Simultion This varactor mode frequency multiplier uses the same topology and transmission lines as the varistor pair in section 3.4. Once again, using the diode models extracted from measurements and transmission line model from HFSS simu lations, harmonic balance and S-parameter simulations were performed in ADS to determine the optimum di ode size and transmission line lengths as well as the proper DC bias for the diode. For the optimized diode structure in this de sign with a unit cell area of 0.64 m 0.64 m and mj = 0.49, the optimum bias for Pin = 10 dBm and fin = 70 GHz is -1 V, and the simulated maximum efficiency is 5.7%. The voltage across the diode varies from 0 V to -3.9 V and the diode is in varactor mode. The efficiency impr oves from around 2% at ze ro diode bias to around 5.7% at -1 V for Pin = 10 dBm. When the reverse bias is more positive than the optimum, the efficiency is limited by the clamping action of fo rward biased junction while the efficiency is lowered by decreased voltage dependence of capacita nce when the reverse bias is more negative than the optimum [74] The optim um diode size depe nds on the input power level [80] For a fully pum ped diode with the voltage swinging from the breakdown voltage to turn on voltage, 2 min)()(biBV inj avgVCmAP (3-9) where Pavg is the average converted power from the fundamental signal to the second harmonic. Ideally, Pavg is equal to input power assumi ng no loss and optimum matching. A(mj) is a function of grading coefficient mj, in is fundamental frequency in radian, Cmin is the minimum capacitance at the breakdown voltage, and VBV is the breakdown voltage. If a diode size is too small, the maximum output power is limited. If a diode size is too big, the voltage swing across the diode decreases due to the impedance drop, wh ich eventually leads to reduced modulation of

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68 junction capacitance and lower efficiency. The si mulated optimum size of each diode for input power of 10 dBm is 38 0.64 0.64 m2, which has the maximum simulated voltage swing across diode in Figure 3-13. The measured Cjo and Rs are 50 fF and 4.7 respectively [74] Figure 3-13. Sim ulated voltage across di ode versus number of unit diode cells. To make the layout more compact, the open st ubs at the output are folded. The folded structure has been simulated in HFSS. The folding increases conversion lo ss of the circuit at 125 GHz output by only 0.2 dB for 10-dBm input power level. 3.5.3 Measurement Results The varactor mode frequency doubler was once again fabricated in the UMC 130-nm logic CMOS technology without any process modifications Figure 3-14 shows the fabricated chip and the diode array. The total die area is ~1.1 mm 0.7 mm. The active ar ea including those of the diode and main transmission lines is ~ 0.21 mm2. Most of the area is occupied by the ground plane formed by shunting metal 1 up to metal 8 layers. Figure 3-15 shows the simu lated and measured |S11| and |S22| at -1.5 V bias for the diode. The measured and simulated behaviors agree well. Input matching |S11| is below -10 dB between 0.5 -0.5 -1.5 -2.5 -3.5 250 255 260 265 270 Time (ps) V oltage across diode (V) N=38 N=46 N=30

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69 61 and 66 GHz, while the isolation of f undamental signal at the output 1/|S21| is greater than 12 dB from 61 to 66 GHz. Figure 3-14. Die photograph for varactor mode frequency doubler in the UMC 130-nm logic CMOS process. The power measurement setup was constructed in the same way as that for varistor mode frequency multiplier in Figure 3-8. The only differen ce is that an HP 8563E spectrum analyzer is used instead of the Agilent E4448A spectrum an alyzer. The loss of the system including the cable and harmonic mixer losses ar e all calibrated using the method discussed in section 3.4.5 for the varistor mode frequency doubler. Based on the measurement and extrapolation in Figure 312, the estimated loss of Agilent 75~110 GHz ha rmonic mixer at 125 GHz is ~4 dB higher than that at 110 GHz. Similarly, due to the multiple mode propagation and conservative estimation of probe loss, the de-embedded power a nd conversion gain are under estimated [74] The diodes are biased again using an external power supply through the 1.2-k on-chip non-silicide polysilicon resisto r. The optimum bias voltage for each diode is around -2 V for 8.5dBm pump power at 125-GHz output frequency. The DC bias current in each diode is 3 A. Figure 3-16 shows the CL and output power vers us the output frequency for three different input power levels. The maximum output pow er and minimum CL occur around 125 GHz. The

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70 measured CL and output power versus input po wer at 125 GHz output are shown in Figure 3-17. Once again the measured and simulated behaviors agree reasonably. The difference between simulation and measurement might due to the er rors in diode modeling and frequency tuning. The minimum CL of about 10 dB occurs at i nput power of 8.5 dBm, corresponding to ~10 % efficiency. The maximum output power is ~ -1.5 dBm at 125 GHz. There is no saturation of CL up to input power of 8.5 dBm suggesting that th e doubler should be able to provide even higher output power if an input signal source with higher calibrated power is used. Figure 3-15. Measured and simulated S-parameters at Vbias= -1.5 V for the varactor mode frequency doubler. S-parameters (dB) 0 -5 -10 -15 -20 -25 Measurement Simulation |S22| |S11| 40 50 60708090100110 Frequency (GHz)40 50 60708090100110 Frequency (GHz)S-parameters (dB) 0 -20 -40 -60 |S21| Measurement Simulation

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71 Figure 3-16. Conversion loss and Pout versus output frequency at Vbias = -1.5 V for the varactor mode frequency doubler. Figure 3-17. Conversion loss and Pout versus input power for 125-GHz output at Vbias= -2 V for the varactor mode frequency doubler. Figure 3-18 shows the bias dependence of th e conversion loss for 125-GHz output signal. Vbias is the bias voltage applied at the DC pad. Th is is essentially the DC voltage across the diode when it is reverse biased. As discussed, with th e increasing input power le vel, the optimum bias CL (dB) 35 25 15 5 Measurement Simulation -10 -5 0 5 10 15 -50 -30 -10 10 Pout (dBm) Pin (dBm) CL Pout Pin= 5 dBm Pin= 0 dBm Pin=-5 dBm CL Pout CL (dB) 40 30 20 10 0 -10 110 115 120 125 Pout (dBm) -50 -30 -10 10 30 50 Output frequency (GHz)

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72 point of the conversion loss shifts more negative to delay the onset of the compression resulting from the forward conduction of the diode [74] Figure 3-18. Conversion loss versus bias for 125GHz output at varying input power levels for the varactor mode frequency doubler. 3.6 Conclusions The feasibility of utilizing Schottky barrier diodes fabricated in foundry CMOS for mmwave applications has been demonstrated by impl ementing a varistor mode and a varactor mode frequency multiplier. The varistor mode and varactor mode frequency doubler exhibits 14-dB CL at 132-GHz and 10-dB CL at 125-GHz output frequency, respectively. These performances are comparable to that of the doubler fabricated in the SiGe BiCMOS proces s. Table 3-3 summarizes the performance of the CMOS frequency doublers. The -1.5-dBm output of varactor mode frequency doubler is the highest power generated by a circuit fabricated in CMOS above 100 GHz [7]. Using the CMOS Schottky barrier diodes, it should be possible to implement frequency doublers operating above 200 GHz. Eventually, it ma y be possible to generate signals at 1 THz and higher with Schottky barrier diodes in CMOS. CLmin CLmin CLmin CLmin CL (dB) 30 25 20 15 10 -2 -1 0 1 2 Vbias (V) Pin=-5 dBm Pin=0 dBm Pin=5 dBm Pin=8.5 dBm

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73 Table 3-3. CMOS frequency multipli er performance summary and comparison Frequency doubler in [61] Frequ ency doubler in [66] Varistor mo de frequency doubler Varactor mode frequency doubler Topology Shunt type Series type Shunt type Shunt type Nonlinear device Schottky barrier diode Schottky barrier diode Schottky barrier diode Schottky barrier diode Diode fco ~0.6 THz ~1.1 THz ~0.8 THz ~0.7 THz Diode size 66 m2 for each diode 4 m2 30 0.32 0.32 m2 for each diode 38 0.64 0.64 m2 for each diode |S11| <-10 dB N/A 50 ~ 55 GHz 62 ~ 70 GHz 61 ~ 66 GHz fout 70 ~ 76 GHz 95 ~ 110 GHz 120 ~ 134 GHz 120 ~ 125 GHz Bias voltage Negative bias 0 V 0.4 V -2 V Minimum conversion loss 4.4 dB @ fout = 76 GHz ~ 11 dB @ fout = 100 GHz; 14 dB @ fout = 110 GHz 14 dB @ fout = 132 GHz 10 dB @ fout = 125 GHz Maximum output power 15.6 dBm @ fout = 76 GHz, Pin = 20 dBm 2.5 dBm @ fout = 100 GHz, Pin = 16 dBm -11 dBm @ fout = 132 GHz, Pin = 6 dBm -1.5 dBm @ fout = 125 GHz, Pin = 8.5 dBm Technology GaAs 0.13-m SiGe BiCM OS 0.13-m CMOS 0.13-m CMOS

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74 CHAPTER 4 P-N DIODE BASED TRANSMIT/RECEIVE SWITCH IN CMOS 4.1 Introduction A Transmit/Receive (T/R) switch is the first bui lding block in a Time Division Duplexing (TDD) system, where users are allowed only to either transmit or receive at a given time interval [81] Unlike m ixers, which switches si gnals rapidly at radi o-frequency, a T/R switch is left in one state, on or off, for long intervals, ~1 ms, before it is switched to the other state [82] And because the cut-off frequency requ irement of de vice is low, integrated p-n junction diodes, Schottky barrier diodes, MOS tran sistors as well as discrete PIN diodes and III-V MESFETs are all suitable for T/R switch applications. In this ch apter, the potential of using CMOS p-n junction diodes in T/R switches for performance improvement is presented. 4.1.1 T/R Switch Parameters Figure 4-1. Simplified TDD transceiver architecture. A simplified TDD transceiver architecture is shown in Figure 4-1. A low noise amplifier (LNA) at receiver (RX) side and a power amplifier (PA) at transmitter (TX) side connect to an antenna (ANT) through a singlepole-double-throw (SPDT) T/R sw itch. In transmit mode, high power from a PA is sent out to an ANT. The sw itch should be able to ha ndle this large power PA LNA T/R switch ANT TX RX Port 3 Port 1 Port 2

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75 without excessive distortion and loss. Besides, good isolation betw een TX and RX is required to limit the leakage of power from PA to LNA, which may stress the LNA by the high voltage in transmit mode. During receive mode, the ANT pick s up very weak signals and delivers to the LNA. The loss of switch increases noise figure of a receiver by the same amount. Thus, the T/R switch should have low loss to reduce its impact on receiver sensitivity [83] Figures of merit of T/R switches include insert io n loss, isolation, return loss and linearity. Their definitions are as follows. All three ports defined in Figure 4-1 are assumed to have the same characteristic impedance of Zo. INSERTION LOSS (IL) characterizes how much signal pow er is dissipated by the switch when the switch is on. IL(dB)=-20log(|S31|) for transmit mode and IL(dB)=-20log(|S23|) for receive mode. These are affected by th e mismatch or return loss as well. ISOLATION (IS) represents how much signal power is attenuated through the switch when the switch is off. The expression for isolati on is the same as that of insertion loss. RETURN LOSS (RL) measures how much power is reflec ted back from a specified port. It describes the degree of mismatch. RL(dB)=-20log(|Sxx|) where x=1~3. LINEARITY or POWER HANDLING CAPABILITY of the switch is us ually represented by 1-dB compression point ( P1dB) and third-order intercept point ( IP3) at output or IP1dB and IIP3 at input. IP1dB is defined as the input sign al power that causes the sma ll-signal gain to drop by 1 dB [2] and the corresponding output power is defined as P1dB. IP3 and IIP3 are defined as the output and input power level at which th e linearly extrapolated output power of desi red signal and that of the third order inte rmodulation component intersect. The linearity requirement of transmitter is much higher than that for a receiver.

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76 A high quality T/R switch exhibits low insertion loss, high isolation and high P1dB, which requires the switching devices to have low on-resistance ( Ron) and off-capacitance ( Coff) product as well as high breakdown voltage. 4.1.2 CMOS T/R Switch Design Challenges Traditionally, T/R switches are implemented using GaAs MESFETs and PIN diodes. This hinders their integration with other transceiver building blocks be sides their higher fabrication cost. Meanwhile, CMOS technology has demonstrated its potential to integr ate all the digital and analog circuits into one single ch ip, which leads to lower manufacturing cost especially for high volume products. These have been the motivations to implement a fully in tegrated T/R switch in a bulk CMOS technology. There are two major obstacles to make a high quality transistor based CMOS T/R switch. First is the relatively large channel resistance [84] [85] Compared to GaAs devices, CMOS MOSFETs have higher cha nne l sheet resistance ( ch) due to the lower electron mobility. The channel resistance Rch = ch L/W where W and L are the channel width and length respectively, determines the insertion loss of CMOS T/R switch. Lower the channel resistance, lower is the insertion loss. To reduce Rch, big W/L ratio is required. However, W can not be increased arbitrarily due to the increased parasitic capacitances resulting from the enlarged source/drain area. This will lead to signal le akage to the lossy substrate, wh ich is the second challenge for CMOS T/R switch design [84] [86] This degrades the insertion loss whe n the switch is on and hurt the isolation when the switch is off. Theref ore a minimum gate length which is determined by the technology is usually utilized to limit the transistor width. As the technology is scaled, insertion loss of CMOS switches is reduced resulting both from lower channel resistance a nd smaller parasitic capacitance [87] However, the technology scaling inevitably reduces the transistor br eakdow n voltage which makes it challenging to

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77 achieve the necessary power handling performance. Besides this, an additional reliability issue has to be considered due the presence of an ultra-thin gate oxide layer [84] [85] [88] 4.1.2.1 Low frequency T/R swit ch design challenges Table 4-1. Reported CMOS transi stor T/R switches with highest IP1dB below 15 GHz IL (dB) IS (dB) Freq. (GHz) TX RX TX RX TX IP1dB (dBm) Technique, Chip area, Control voltage Technology Ref. 0.9 0.5 1.0 37 29 31.3 Floating body, stacking SDR* transistor, feed-forward capacitor, 0.11 mm2, 2~6 V 0.13-m triple well CMOS [89] 2.4 1.5 1.6 32 17 28.5 LC-tuned substrate, 0.56 mm2, 0~1.8 V 0.18-m CMOS [90] 5~ 6 0.9 0.8 27 17 31.8 Body isolation with p implant block, 0.2 mm2, 5 V 90-nm CMOS [86] 15 1.7 1.7 32 32 30.0 Floating well, differential switch, 0.18 mm2, 0~2 V 0.13-m triple well CMOS [91] SDR*: Sub-Design-Rule transistor [89] For a transistor based CMOS T/R switch ope rating below 15 GHz, the insertion loss and isolation can be improved by minimizing the subs trate resistance and DC biasing the S/D nodes [84] [92] However achieving IP1dB higher than 1 W, which is needed for several wireless communication standards, has been a very diffi cult challenge. The techniques to improve linearity include DC biasing S/D nodes [84] [92] impedance transformation [87] [93] as well as floating body. The concept of floating body in CMOS was first introduced in [92] by using a m inimum number of body contacts for transistor s. Then depletion-layer-extended transistors (DETs) have been introduced in [94] [95] to increase sub strate resistance with the help of extra fabrication masks. An LC-tuned subs trate bias is first reported in [90] where the bulk connection of NMOS transisto rs is made floating at resonant frequency. St acked transistor techniques are employed in addition to the body floating met hod to further improve the power handling capability [89] [95] Table 4-1 lists the m aximum reported IP1dB for transistor based CMOS T/R switches operating below 15 GHz Most of the switches employ a series-shunt topology.

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78 Although the maximum output power has reached up to ~31 dBm, the bottleneck of power handling capability of transistor based T/R switch is still the voltage lim itations for reliable operation. Compared to transistors, p-n j unction diodes in CMOS have higher breakdown voltage, which is greater than 1.3X of 3.3-V thic k gate oxide transistor breakdown voltage in the UMC 130-nm logic CMOS process as shown in Table 4-2. Therefor e, it is possible to use p-n junction diodes to improve the power handling capability of low frequency T/R switches. Table 4-2. Comparison of br eakdown voltage for p-n diodes a nd MOS transistors in the UMC 130-nm logic CMOS process Device p-n junction diode in p-sub p-n junction diode in n-well 1.2-V nMOS 1.2-V pMOS 3.3-V nMOS 3.3-V pMOS Breakdown voltage (V) 10.7 14.5 2.7 3 8.1 6.5 Pmax* (dBm) 30.6 33.2 18.6 19.5 28.2 26.3 Pmax*: The maximum delivered power for a 50load. 4.1.2.2 Millimeter-wave T/R switch design challenges Unlike the other RFIC circuits whose operating frequency has been pushed up to 60 GHz, CMOS transistor T/R switches for higher frequency operations are explored only to a limited extent due to the high inse rtion loss and low isolation [91] At millimeter-wave frequencies, the best transistor based CMOS T/R switch has ~3-d B insertion loss, greater than 27-dB isolation and 15-dBm IP1dB from 50 to 94 GHz [96] Compared to this III-V T/R switches have better performance with less than 2-dB insertion loss, hi gher than 30-dB isolation [97] as well as 20 dBm IP1dB [98] The insertion loss of comm on series-shunt topology at lower frequencies is degraded due to the big parasiti c capacitance of shunt-arm at hi gh frequency. While the lack of shunt arm results poorer isolation [91] At the m illimeter-wave frequency range, it is challenging to achieve isolation higher than 20 dB due to the signifi cantly reduced impedances of parasitic capacitances Cjd and Cjs as well as Cds between source and drain in Figure 4-2. This necessitates a trade-off between insertion loss and isolation during sizing of the transistors [99] Besides, passive com ponents like inductors

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79 and transmission lines for matching networks have low Q in standard CMOS technologies. These pose challenges for millimeter-wave T/R switch design. Figure 4-2. MOS transist or small-signal model. As mentioned, shunt elements are commonly place at TX and RX branches to achieve sufficient isolation. However, this increases in sertion loss. To overcome this, the technique of merging the shunt transistors into matching networ k to reduce their impact on insertion loss is developed [99] ; traveling-wave (distributed switch) concept is also utilized to periodically load a transmission line or an inductor with the pa rasitic capacitance from shunt transistors [96] ,[100] Table 4-3 lis ts the performance of millimeter-wave CMOS transistor T/R switches up to the present. The power handling capability and inse rtion loss are inferior to those of III-V T/R switches. To improve linearity, p-n diodes with hi gher breakdown voltages can be used. The measured breakdown voltage of pn diodes is higher than 11 V wh ich is ~2-3X higher than that of a 1.2-V MOS transistor in the 130-nm CM OS technology. Besides, a p-n diode has less parasitic capacitance to lossy substrate than a MO S transistor, using it as a shunt element should reduce insertion loss degradation. In simulation, p-n diodes with equivale nt on-resistance as an Rg ( ~k ) Rsub D S Vg G Rsub Rch Cjd Cjs Cds D S RF Floating

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80 NMOS transistor have ~3X lower parasitic capacit ances. Using a similar optimized layout as that of high Q Schottky barrier diode the p-n diodes achieved a cutoff frequency of ~1.8 THz. Because of these, it should be possible to use p-n diodes to improve millimeter-wave switch insertion loss and power handling capability. Table 4-3. Performance comparison for repor ted millimeter-wave CMOS transistor T/R switches Freq. (GHz) IL (dB) IS (dB) IP1dB (dBm) Technique, Chip area Technology Ref. 0~50 <6 ANTTX/RX >38 19.6 @ 40 GHz Body floating, stacking transistors, distributed switch, 0.25 mm2 0.18-m triple well CMOS [100] 50~94 <3.3 ANT-TX/RX >27 15 Body floating, traveling wave switch (distributed switch), 0.24 mm2 90-nm triple well CMOS [96] 57~ 66 4.5~5.8 TX-RX 24~26 4.1 2 shunt transistors at each branch, 0.21 mm2 w/o pads 0.13-m triple well CMOS [99] 57~ 66 3.5~4.9 TX-RX >30 7.2 2 shunt transistors at each branch, 0.13 mm2 w/o pads 0.13-m triple well CMOS [101] 4.1.3 P-n Junction Diode T/R Switch Design Challenges Although p-n junction diodes have higher breakd own voltage to handle large power, their static power consumption due to the bias curren t remains as a drawback. To turn a diode on, it needs to be biased at several mAs to ensure low AC resistance for low insertion loss in series topology or high isolation in s hunt topology. Reducing this sta tic power consumption is a challenge. Besides this, the current must be supplied through a choke or a biasing circuit which minimize the power consumption when a diode is on while providing high impedance when the diode is off. A high impedance choke design is challenging in CMOS due to the significant parasitic capacitance resulting from thin dielectric layers that lowers the impedance. These issues will be discussed in the following sections.

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81 4.2 Design of 60-GHz P-n Diode/MOS Transistor T/R Switch in CMOS 4.2.1 Design Specifications and Switch Topology Table 4-4 lists the design specifications for the 60-GHz T/R switch. Table 4-4. Design specifications of 60-GHz p-n junction diode T/R switch Specification parameter Target value Operating frequency (GHz) 60 Insertion Loss (dB) < 3 Return Loss (dB) > 10 Isolation (dB) RX-ANT > 20 (TX mode) TX-RX > 20 (TX mode) TX-ANT as high as possible (RX mode) Input linearity IP1dB (dBm) > 20 (TX mode) As high as possible (RX mode) Control voltage (V) 0 < Vctrl < VDD DC power consumption As small as possible Figure 4-3. Simplified schematic of a 60GHz p-n diode/MOS tran sistor T/R switch. The switch topology is determined by the avai lable devices and required power handling capability. As discussed in Chapter 2, since a p+-n diode in an n-well can be biased at both nodes, this type of p-n junction diode is util ized for the T/R switch design. The breakdown voltage of diode is higher than 11 V. However, similar to the Schottky diode built in an n-well discussed in Chapter 3, the n-well to substrate capacitance is non-negligib le due to the large nwell size needed to lower the seri es resistance. Hence, a shunt topology is chosen to overcome this limitation. TX Matching Network Quarter-wave Transformer Quarter-wave Transformer RX Matching Network TX ANT RX

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82 Due to the different power handling capability requirement of transmitter and receiver, different switching devices can be utilized. A p-n junction diode is connected in the TX branch to handle higher than 20-dBm input power, wh ile a low breakdown voltage MOSFET biased in the triode region is employed in the RX branch to reduce the total power consumption. Figure 43 shows the simplified schematic for the 60-GHz p-n diode/MOS transistor T/R switch. A quarter-wave transformer is employed at TX and RX to block signals from going into the branch that is turned off, and matches the ANT por t impedance to TX/RX port impedance. Matching networks are used to match the impedance at TX and RX port. 4.2.2 Circuit Design 4.2.2.1 Diode biasing circuit design As discussed in section 4.1, a proper diode biasing circuit should provide high impedance to the diode when it is off while consuming low power when it is on. Possible choices for the biasing element are a diode, an inductor or a hi gh value resistor. Owing to the diode ideal I-V characteristics, the impedance looki ng into the cathode (n-well node for p+-n diode in n-well) of diode is very high. Yet in reality, there are non-neg ligible parasitics to lossy substrate at cathode when the biasing diode size is increased to ensure relatively low impedance of D1 at certain turnon current under fixed supply vol tage. Biasing through a high-Q inductor has the advantage of lower power consumption compared to the previo us method. Nevertheless, in advanced CMOS process, thin dielectric and metal layers make the design of high-Q inductor challenging. Besides this, the inductor-bias method occupies more area than the diode or resist or-bias scheme and an inductor has appreciable parasitics to substrate like the diode. The imperfection of ground plane in the inductor-bias scheme is also more significant than the di odeor resistor-bias schemes due to the necessary ground slots for avoiding eddy current.

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83 Besides these, the diode can also be biased through a hi gh value resistor. Although the power consumption is relatively high, the parasi tics introduced by resist or are the lowest among all three bias schemes. A nonsilic ide polysilicon resistor can be ut ilized to make the occupied chip area and thus the parasitic capacitance the minimum. The parasitic capacitance at each terminal of a 1-k nonsilicide polysilicon resi stor with dimension of 3 m m is less than 2 fF, which is about half of that for a 45 m 45 m 210-pH spiral inductor using top 2 metal layers without poly ground shield and ~20X lower than the n-we ll parasitic capacitance for a 16.32 m.32 m p-n diode. Therefore, a resist or-bias scheme is chosen in this design. Figure 4-4. Clamping ch aracteristics of diode. Another concern for the biasing circuit is the diode clamping when it is turned on. When the voltage across a diode exceeds the turn-on vo ltage, the positive voltage waveform will be clamped at its turn-on voltage VD0 (0.7~1.0 V for a p-n diode) li ke that in a limiter circuit [4] This lim its the power handling capability of a switc hing diode which is illustrated in Figure 4-4. Thus, a diode biasing circuit should also be ab le to adjust the diode bias according to the magnitude of the input signal so that the voltage across the di ode can swing from the turn-on Vin + Vout + VinVout Vint Vout t Von (0.7~1.0 V) R D1 0 0 0

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84 voltage to certain negative volta ge without breakdown. This can only be achieved when the two terminals of diode are made to have high impedance at DC. Figure 4-5. A diode self-biasing circuit. Based on these, a diode self-b iasing circuit shown in Figur e 4-5 has been developed. C1 is provided by external bias te e and is much bigger than C2 (on-chip metal capacitor) in this design. Rbias is ~1 k to provide high impedance for the diode for avoiding power leakage when diode bias chain is off. When a large signal passe s through the TX branch, PMOS transistor MP1 and NMOS transistor MN1 are biased in cut-off region by setting the control voltage Vg1=VDD and Vg2=0 V. Therefore, the diode bias chain in TX mode can be simplified to Figure 4-6, where the input is a sinusoidal signal with zero DC level and amplitude of VA from TX port in Figure 4-5. In one period, D1 conducts a brief interval of t near peak of Vin and Cn is charged with time constant of Rn( Cn+C1). As the input drops, diode D1 turns off and node N is discharged through Rn with time constant of RnCn for the rest of the period. Since the charging time ( t) is much shorter than the discharging time (~T, period of the signal) or ch arging time constant is much B N P R1 R2 MP1MN1C1 C2 VDD Rp Cp Rn Cn Biasing element D1 Vg1Vg2TX ANT Rbias Lbias D0

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85 longer than discharging time cons tant, the voltage at node N stays close to a low DC value of 0 V. Figure 4-6. Equivalent circ uit for the diode bias chain when TX is transmitting. Therefore, the diode bias chain is eq uivalent to a DC restorer circuit [4] formed by D1 and C1. C1 is charged to VC (=VA-VD0) as input signal increases from 0 to VA in its positive cycle. Then, input signal decreases, di ode turns off since the voltage drop across it is less than VD0 and C1 retains its voltage. Because Vin=VC+Vout according to their polarity in Figure 4-6, output signal at node B follows the input signal with a DC shift of VC, i.e., VD0-VA. Hence, a DC voltage equal to VD0-VA appears at node B. This is equivalent to bias the diode adaptively according to the input signal level. The voltage across the diode D1 is the difference voltage between nodes B and N, which swings approximately from -2VA+VD0 to the diode turn-on voltage if the diode does not brea kdown during the negative cycle. If input signal is not large enough to turn on the diode, D1 will be biased at 0 V and signal across it will not be clamped either. Figure 4-7 shows the transient waveform at input, node B and N wh en input signal has amplitude of 3 V. Rp and Rn (~1 k ) are used to increase the isolation between TX and RX branch so that the transistor in RX branch wont see excessive voltage. By-pass capacitors Cp and Cn (2 pF) provide RF ground at node P/N so that only off-capacitance of D1 and parasitics of Rbias are seen at node B CDC D1 Vin V A Rn Cn N + +-Vout +

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86 B. AC coupling capacitors C1 and C2 are necessary to block the diode DC bias to the rest of the circuit. Figure 4-7. Voltage waveforms at input, node B and N when input signal has amplitude of 3 V. When Vg1=0 V and Vg2=VDD, all the devices in the bias circuit are turned on and there is ~2 mA current flowing through diode D1 as well as Mp1 and Mn1. The total on-resistance of Mn1 is set to ~1 to minimize its effect on switch perfor mance. To accommodate 2-mA current and handle greater than 20-dBm power (.2 V signal swing for a 50system), VDD should be higher than 2 V and thick gate oxi de transistors are used for MP1 and MN1. 4.2.2.2 Quarter-wave transformer Figure 4-8. Quarter-wave transformer lumped element equivalent network. )2/(oofZL (H) )2/(1ooZfC (F) L C C 112.1 112.11 112.12 112.13 112.14 112.15 -6 -4 -2 0 2 4 Time (ns)Voltage (V)Vin Node N Node B

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87 At 60 GHz, a quarter-wave in silicon dioxide is ~620 m, which is too long, thus a transformer constructed with a transmission line will occupy a lot of area, and a lumped transformer using inductors and capacito rs shown in Figure 4-8 is used. 4.2.2.3 Method of improving isolation As discussed in section 4.1.2.2, achieving sufficient isolation at the millimeter-wave frequency range is very challeng ing. A common way to increase isolation is to put several shunt arms in the TX/RX branch [96] [99] [101] In integra ted transceivers, a transmitter may need to deliver power as big as 30 dBm of higher in cellular and wireless LAN applications, while a receiver usually will only pick up weak signals fr om an antenna. Therefore, the isolation between TX/ANT and RX in a T/R switch when TX is tr ansmitting (TX mode) is critical to ensure reliable operation. On the other hand, the isolat ion requirement for TX/ANT and RX when RX is receiving (RX mode) is relaxed. Ye t it should still be su fficiently high so that the insertion loss of RX chain is not significantly degraded. Based on these, two identical 1.2-V NMOS transistors MN2 and MN3 as well as inductor Lx are used to form a -network with low pass characteristics in RX branch for isolation improvement in this design [102] Figure 4-9. Equivalent -network form ed by Lx and MN2 as well as MN3. Lx Ctran Ctran Rtran Rtran Zx ZRX =50 Low pass -network /4 Z0=50 Vin Vout ANT RX

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88 Figure 4-10. Effects of Lx on TX and RX isolation in TX mode. Figure 4-11. Effects of Lx on RX-ANT insertion loss in RX mode. The equivalent circuit of this -network is shown in Figure 4-9, where Ctran and Rtran are equivalent capacitance a nd series resistance of MN2 and MN3, ZRX is the RX port load impedance (50 ). When TX is connected to ANT, MN2 and MN3 are biased in linear region with low 50 55 60 65 70 -3.5 -3.3 -3.1 -2.9 -2.7 -2.6 Frequency (GHz)RX-ANT Insertion Loss (dB) Lx=40 pH Lx=60 pH Lx=80 pH Lx=100 pH 10 20 30 40 50 60 70 -55 -45 -35 -25 -15 Frequency (GHz)TX-RX Isolation (dB) Lx=40 pH Lx=60 pH Lx=80 pH Lx=100 pH

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89 parasitic resistance of Rtran-on and big parasitic capacitance of Ctran-on. If Rtran-on is negligible, the transfer function of this ne twork can be expressed as 22 2)/(1 1 1 )( )( )(c ontranx ontranx in outs CL CLssV sV sH (4-1) ontranx cCL /1 (4-2) where, c is the cut-off frequency in radian. These are the characteristics of a second-order low pass filter [4]. Figure 4-12. Effects of Lx on TX-ANT insertion loss in TX mode. To achieve acceptable RX mode insertion loss, the sizes of MN2 and MN3 need to be relatively small. They are less than 30 m in th is design. In simulations, the parasitic capacitance Ctran-on associated with such a transistor in TX mode will be smaller than 0.5 pF. If Lx is less than 100 pH limited by the chip area, the cut-off frequency for this low pass filter will be greater than 22.5 GHz. Further away the operating frequency from c, bigger the attenuation of the filter and higher the isolation of the sw itch will be. Therefore, it is possible to use a big Lx for isolation improvement if the sizes of MN2 and MN3 are fixed. This is illustrated in Figure 4-10 when W/L 40 45 50 55 60 65 70 -4 -3.5 -3 -2.5 -2 Frequency (GHz)TX-ANT Insertion loss (dB) Lx=40 pH Lx=60 pH Lx=80 pH Lx=100 pH

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90 ratio for MN2 and MN3 is 24 m/0.12 m. On the other hand, closer the operating frequency to c (when c is higher than the operating frequency), larger the transmission of the filter is. This is the case in RX mode where th e parasitic capacitance of MN2/MN3 Ctran-off < 50 fF and c > 70 GHz for Lx < 100 pH. Figure 4-11 shows that RX-ANT insertion loss drops as Lx increases. In the meantime, TX to ANT insertion loss will become worse as Lx increases. When TX is transmitting, the low pass filter in Figure 4-9 is equivalent to a quarte r-wave transformer with characteristic impedance of ZLP = ontranxCL/ (Figure 4-8). Therefore the impedance at ANT port looking into RX branch is Zx = 50(Z0/ZLP)2. Bigger the Lx, higher the ZLP and lower the Zx are. These cause more power leakage to RX branch from TX port and degrade TX to ANT insertion loss. Figure 4-12 shows this effect. Ho wever, this degradation is much less than the improvement of isolation compared with that in Figure 4-10. Figure 4-13. Effects of Lx on TX and RX isolation in RX mode. Similarly, the impedance at ANT port looking into RX branch decreases as Lx increases in RX mode. The ratio between the power leakages to RX branch and total power transmitted by 50 55 60 65 70 -21 -20 -19 -18 -17 -16 Frequency (GHz)TX-RX Isolation (dB) Lx=40 pH Lx=60 pH Lx=80 pH Lx=100 pH

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91 TX equals to 50/(50+Zx) assuming the ANT port impedance is 50 Therefore, this power ratio becomes bigger as Lx increases, which means isolation be tween TX and RX degrades in RX mode. This is shown in Figure 4-13, alt hough the degradation is not significant. To balance the insertion loss in the TX and RX modes and to increase the isolation in TX mode as much as possible, Lx is chosen to be ~70 pH in this design. 4.2.2.4 Passive components design Figure 4-14. Line inductor configurations with A) side view and B) top view. The design of passive components especially the inductors for matching networks is critical for improving switch performance. A lthough transmission lines are commonly employed at this frequency, it is still not practical to use them to build large inductors due to their lower distributed inductance and higher loss in CMOS technology. In th is design, inductors with a value of 50~200 pH are needed. Thus, high-Q line inductors are designed The other advantage of using line inductors is that the interconnections can be included as part of inductor design thus the chip area can be minimized. To reduce the pa rasitic capacitance to substrate, the top metal layers are used. To reduce the conductor loss, mu ltiple metal layers (two copper layers metal 7 and metal 8 as well as an aluminum pad layer) ar e shunted together. The total metal thickness of inductor is ~2.8 m. Figure 4-14 shows the conf iguration of the line i nductors. An irregular Aluminum Metal 8 Metal 7 A B 5 m 4.7 m 3 m

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92 shaped metal 8 layer pattern is used to satisf y the design rules of minimum pad via width while minimizing the parasitic capacitance to substr ate. There is no ground shield under the line inductor to further reduce the pa rasitic capacitance. The HFSS simulation results for a 200-m line inductor are shown in Figure 4-15. Qeff is defined as Im( Yxx)/Re( Yxx), where x=1, 2, is the port number. Qeff of ~27 is achieved at 60 GHz with inductance of ~170 pH. Figure 4-15. Line inductor HFSS simulation results. All the resistors are implemented using a non-si licide polysilicon layer to reduce chip area. The advantage of non-silicide poly resistor is its lower parasitic capacitance to substrate due to a smaller area needed compared to a silicided pol ysilicon resistor. The nonsilicide polysilicon resistor has ~30X higher resist ance for a given area. All capacitors are metal-insulator-metal capacitors for high voltage operation. 4.2.2.5 Schematic of 60-GHz p-n diod e/MOS transistor T/R switch Figure 4-16 shows the complete schematic of 60-GHz p-n diode T/R switch. A p-n diode D1 is employed in the TX branch to handle greate r than 20-dBm input power This is similar to that in PIN diode switches [103] Shunt transisto rs MN2 and MN3 (1.2-V type) are used in the RX 150 160 170 180 190 200 5055606570 Frequency (GHz)L (pH)0 10 20 30Q Q L

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93 branch to make DC power consumption zero in TX mode with the aid of by-pass capacitor Cby. When the TX branch is connected to the antenna (TX mode), MN2 and MN3 are biased in the linear region with low impedance. This impe dance is transformed high using essentially a quarter-wave transformer formed by Lr and parasitic capacitances at node Y and ANT port. This lowers the power leakage into the RX branch and TX branch insertion loss. Because of this, the shunt transistors do not see hi gh voltages and it is permissi ble to use low voltage MOS transistors. Figure 4-16. A 60-GHz pn diode/MOS transistor T/R switch schematic. In the RX mode, the p-n diode is on. Similar to the previous case, Lt and C1 as well as the parasitic capacitances at node X and ANT port quarter-wave transform the on-impedance of diode to high impedance. The drain voltage of MN2 and MN3 is also set high to lower the total off-state capacitance. To reduce insertion loss even more, the body-floating technique using a limited number of substrate contacts [92] is utilized. The TX and RX pad parasitics are tuned out R1 VDD_TX (2 V) Rp Cp Ltx Lt D1 (300.32.32m2) R2 MN1 Cn Rn R3 R4 Lr Lx C1 TX ANT Rbias (1 k ) MP1 MN2 Vg1 Vg1 X (24m/0.12m) Vg1 Vg1 VDD_TX (2 V) RX Lrx MN3 R5 Cby Vg2Vg2 (24m/0.12m) CDC CDC Y Vg2 VDD_RX (1.2 V) Vg2

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94 using Ltx and Lrx. Series coupling capacitors CDCs (2 pF) not presently integrated (bias tee) are needed at the TX and RX nodes to DC isolate the switch biases [104] C1 is utilized for isolating the biases of TX and RX branches. A wide transistor (3300 m/0.34 m) is used for MN1 to minimize the on-impedance of diode biasing chain for lower insertion loss and higher isolation in RX mode. D1 is made of 30 cells of a 0.32 m.32 m p+n diode in n-well with ~16-fF off-state capacitance, ~5parasitic resistance. MN2 and MN3 have a size of 24 m/0.12 m a nd an on impedance of ~19 as well as a 24-fF off-state capacitance at their drain node. To reduce gate resistance, double ga te contacts are used. Also metal 1 to metal 3 stacks are employed for source/drain connections to reduce parasitic resistance without adding excessive source drain parasitic capacitan ce. The simulated power handling capability limited by reliability is higher than 21 dBm to ensure the voltage drops across the 4 terminals are less than 4 V and 1.5 V for 3.3-V a nd 1.2-V transistors, respectively. 4.2.3 Measurement Results and Analysis Figure 4-17. Die photograph for a 60-GHz p-n di ode/MOS transistor T/R switch in the UMC 130-nm logic CMOS process. TX ANT RX C1 Lt RbiasD1 MN2Lr Ltx Lrx Vg1 VDD_RXVDD_TXGND GND GND GND GND GND Vg2 MN3

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95 This 60-GHz p-n diode/MOS transistor T/R switch was bui lt in the UMC 130-nm logic CMOS process. Figure 4-17 shows the chip die photograph. The die ar ea is ~0.5 0.6 mm2 including bond pads. A. Small signal performance The S-parameters were measured using an Agilent E8361A network analyzer. A pair of GGB 110H-GSG-150P probes was used to measur e the switch from 20 to 100 GHz on wafer. Figures 4-18 and 4-19 show the measured results for TX and RX modes, respectively. In TX mode, Vg1 = 0 V, Vg2 = 1.2 V and VDD = 2 V. DC power consumption is ~0 mW. The TX port return loss (TX_RL) is below -10 dB from 30 to 57 GHz and ANT port is matched from 37 to 84 GHz. The TX-ANT insertion loss (TX-ANT_IL) is ~2.1 dB around 60 GHz. The isolation between TX and RX is 19.5 dB at 60 GHz. Figure 4-18. Measuremen t results in TX mode. In RX mode, Vg1 = 3.3 V, Vg2 = 0 V and VDD = 2 V. The diode draws ~2.5 mA current. The switch power consumption is 5 mW. The RX port is tuned from 62 to 95 GHz and the ANT port is matched from 53 to 88 GHz. The RX-ANT insertion loss (RX-ANT_IL) is ~3.1 dB at 60 20 40 60 80 100 -25 -20 -15 -10 -5 0 Frequency (GHz)S-parameters (dB)TX-ANT_IL TX_RL ANT_RL TX-RX_IS

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96 GHz. The isolation between TX and RX is ~12 dB at 60 GHz. This is low but acceptable since the received power is low [104] Figure 4-19. Measurem en t results in RX mode. B. Power handling capability Figure 4-20. Measured and simu lated output power versus input power in TX mode at 60 GHz. -10 0 10 20 30-10 0 10 20 30Pin (dBm)Pout (dBm)-10 -8 -6 -4 -2 0IL (dB) Measurement Simimulation Pin=21dBm when |Vgd|=1.5 V for MN2, |Vgd|= 3.9 V for MP1 IP1dB=29.3 dBm 20 40 60 80 100 -25 -20 -15 -10 -5 0 Frequency (GHz)S-parameters (dB)RX-ANT_IL RX_RL ANT_RL TX-RX_IS

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97 The power handling capability in TX mode was characterized using an Agilent E8257D 0.25~67-GHz signal generator, an OML V-band harmonic mixer and an Agilent E4448A spectrum analyzer at 60 GHz. This setup allows application of 9 dBm at the input. Figure 4-20 shows the measured results. Th e data points at 10-, 13.8-, 14. 2and 18-dBm input were taken using a Terabeam Gunn oscillator with 22-dBm output power. The switch hasnt reached its IP1dB up to 18-dBm input power. C. Switching speed Figure 4-21. Simulation results for the switching speed of the 60-GHz p-n diode/MOS transistor switch when TX is transmitting 0-dBm power. The switching speed is charac terized by the rise time, trise, and fall time, tfall [99] The rise and fall tim e are defined as the time between 10% and 90% points of the transition waveforms [105] A transient s imulation in Cadence is used to evaluate the switching speed of the switch. In this simulation, control voltages Vg1 and Vg2 in Figure 4-16 are set as 5-MHz 50% duty cycle pulses with a high level of 3.3 V and 1.2 V, respec tively, and low level of 0 V for both. The input 150 250350450 Time(ns) 300 100 0 -100 -300 V out ( m V ) tfall=1.7 ns trise=3.3 ns 550 200 -200

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98 signal is a 60-GHz sinusoid waveform at 0-dBm power level comi ng from TX port. DC blocking capacitor CDC is 1 pF. The rise and fall time are meas ured from ANT port output waveform to be ~3.3 and 1.7 ns, respectively. Figure 4-21 shows the simulated waveform. This is faster than commercial GaAs PIN diode switches which usually have switching speed of tens or even couple hundreds of nanoseconds [106] [107] The variations of trise and tfall versus the input power are shown in Figure 4-22. When the input power is gr eater than -10 dBm, sw itching speed reduces as input power increases. However, the switching ti me also gets longer as input power reduces when the input power is lower than -10 dBm. Figure 4-22. Switching time versus i nput power of the switch in TX mode. The switching of transistors MN2 and MN3 by Vg2 in Figure 4-16 is relatively fast due to the small transistor size of 24 m/0.12 m with ga te capacitance of ~16 fF for both. The time constant for the network R3-MN2 or R4-MN3 in Figure 4-16 is less than 0.1 ns. For the input power greater than -10 dBm, the switching speed of diode bias chain is expected to dominate the speed performance of the switch. When the input power is below -10 dBm, di ode bias chain can be switched faster which will be discussed later and the switching behavior of R3-MN2 as well as R4-20 -10 0 10 20 25 0 2 4 6 8 10 12 Pin (dBm)Switching time (ns) trise tfall

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99 MN3 networks slows down the enti re switch. This is illustrated by the comparison of the solid and dashed curves shown in Figure 4-22, where the dashed curves are the switching time when Vg2 is set at a constant value of 1.2 V and the solid curves are the ones when Vg2 is a 5-MHz pulse. Figure 4-23. Equivalent circuits of the diode bias chain when A) Vg1 is low, B) Vg1 is high and C) the waveform of Vg1. Figure 4-23 shows the simplified equivalent circuits when Vg1 is low and high, where RMP1 and RMN1 are the on impedance of the MP1 and MN1. The inductors Ltx and Lt are omitted for simplification. The arrows show the char ge moving direction. Right before time t0, there are ~0.7 D1 Rn Cn From TX To ANT N From ANT Rn N To TX RMP1A B CDC Rbias Rbias B B CDC Rp Cp P Cn Rp Cp P 3.3 V 0 V t1 t0 t2 C RMP1 VDD D1 MP1 MN1 Path I Path II

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100 V DC voltage at node B and ~VDD at node P. At time t0, Vg1 changes rapidly from 3.3 V to 0 V, transistors MN1 and MP1 are turned off, node B is discharged from ~0.7 V to ~VD0-VA by the input signal through the capacitor CDC (1 pF) via paths I and II in Figure 4-23 A) as discussed in section 4.2.2.1, where VD0 is the diode turn on voltage and VA is the magnitude of input signal. Therefore, the time constants of networks RbiasCDCRpCpRnCn, R1-MP1 and R2-MN1 in Figure 4-16 determine the rise time trise of the switch. At time t1, Vg1 changes from 0 V to 3.3 V, MP1 and MN1 are turned on with low impedance, node B is charged again up to 0.7 V. Since the RMP1 (~14 ) is much lower than Rp (1 k ), node P can be charged very fast to ~VDD. Then node B is charged to ~0.7 V through Rbias and CDC. Therefore, the charging time or tfall is mostly determined by the time constants of networks RbiasCDC, R1-MP1 and R2-MN1 in Figure 4-16. Due to the smaller time constant in discharging of node B, tfall is shorter than trise. Also slower switching time is exp ected as the input power increases from the above analysis because node B is charged and discharged from VD0-VA to VD0 back and forth. The switching speed can be improved by decreasing Rbias, Rp, R1, R2, CDC, Cp and sizes of MP1 and MN1. Changing Rbias from 1 k to 500 can reduce switching time by 10%. Yet this will degrade insertion loss in TX mode of ~0.3 dB. Reducing CDC from 5 to 1 pF can make the switching time ~15% lower without significant degradation of in sertion loss. Further reduction of CDC will hurt insertion loss as well. Reducing the time constant of R1-MP1 and R2-MN1 networks by 20X can reduce sw itching time by 12%. However, R1/ R2 can not be too low otherwise the gate node of MP1/MN1 will not be an open to RF input, which will increase insertion loss. Besides, reducing the size of MP1/MN1 too much will lower the diode on-current and increase the Rdiode in Figure 4-23 B), which will degrade insertion loss and isolation in RX

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101 mode. Reducing the time constant of RpCp network by making Rp lower will hurt insertion loss and by reducing Cp will make AC grounding at node P worse. D. Performance summary Table 4-4 summarizes the switch performance a nd also compares to those of recently published millimeter-wave switches. This 60GHz hybrid p-n diode/MOS transistor switch fabricated in the UMC 130-nm logic CMOS proce ss exhibits competitive insertion loss as the MOS T/R switch in 90-nm triple well CMOS with the lowest insertion loss and have better power handling capability [104] IP1dB is greater than 18 dBm. Due to unavailability of a high power signal source, the simulated power handli ng limit of 21 dBm set by the oxide reliability (Figure 4-17) has not been experimentally veri fied. The performance of switch has met the specifications listed in Table 4-4. Table 4-7. Performance summary for 60-GHz p-n diode/MOS tran sistor T/R switch in the UMC 130-nm logic CMOS process Freq. (GHz) IL (dB) IS (dB) TX IP1dB (dBm) Switching speed (ns) Switching devices Size (mm2) Technology Ref. 50~94 2.7 (77GHz) ANT-T(R)X 29 (77GHz) 15 (77GHz) N/A MOSFET 0.6.4 90-nm triple well CMOS [96] 57~66 5.0 (60GHz) TX-RX 24 (60GHz) 4.1 (60GHz) 0.40 (trise) 0.36 (tfall) MOSFET 0.7.3 w/o pad 0.13-m RF CMOS [99] 57~ 66 4.0 (60GHz) TX-RX 30 (60GHz) 7.2 (60GHz) 0.40 (trise) 0.36 (tfall) MOSFET 0.5.3 w/o pad 0.13-m RF CMOS [101] 57~ 66 2.1 (TX, 60GHz) 3.1 (RX, 60GHz) TX-RX 20 (TX, 60GHz) 12 (RX, 60GHz) >18 (60GHz) 3.3 (trise) 1.7 (tfall) (Pin=0 dBm) p-n diode /MOSFET 0.5.6 0.13-m logic CMOS This work 60~90 <2.5 >25 >23 (78GHz) 2000 (trise) 6000 (tfall) Silicon PIN diode 3.3.7 SIMMWIC [98] 4.3 Conclusions A 60-GHz hybrid p-n diode/MOS transistor T/R switch was successfully designed using the UMC 130-nm logic CMOS process. The switch achieves ~2 and 3 dB insertion loss in TX and RX mode at 60 GHz, respectively. Measured input 1-dB compression poi nt is limited by the measurement setup and higher than 18 dBm, and isolation is ~20 dB at 60 GHz in TX mode. By

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102 using a higher breakdown voltage p-n diode, th is hybrid switch achieves the highest power handling capability in CMOS millim eter-wave switches reported up to date. This work suggests that it is possible to use a p-n di ode in foundry CMOS like a PIN diode [98] in millimeter-wave switches to improve their power handling capab ility with small impact to insertion loss [104]

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103 CHAPTER 5 LOCAL OSCILLATOR SIGNAL GENERATION FOR 77GHZ RADAR SYSTEM USING MOS VARACTOR FREQUENCY DOUBLER 5.1 Introduction Long-Range Radars (LRR) at 76-77 GHz are be ing used for automatic cruise control (ACC) or collision warning [108] Traditionally, these rad ar systems are built from III-V discrete components with high cost and bulky size, whic h make them only suitable in high-end cars [109] The advance of CMOS technology today has demonstrated a peak transistor transit frequency fT higher than 300 GHz [110] [111] which m akes it possible to implement these radar systems with much lower cost and compact size [112] One of the critical parts for integrated CMOS radar transceiver desi gn is the generation of local oscillator (LO) signal. The LO signal us ually needs about 300 mV-pk swing to drive a millimeter-wave active mixer with adequate spectral purity [112] Howe ver, this becomes more challenging as the operating frequency is increased. At millimeter-wave frequencies, the phase noise of a voltage controlled os cillator (VCO) is degraded by the tank quality factor, layout parasitics and power consumption constraints [112] For example, a 30-GHz VCO with phase noise of -110 dBc/Hz at 1-MH z offset is read ily achievable [113] whereas the phase noise of a 60-GHz VCO is higher than ~100 dBc/Hz at 1-MHz offset [114] [116] This is ~4 d B more than the theoretical degradation of 6 dB ( 20log(N) where N is the multiplication factor [117] ). Besides, MOS varactors used for VCO frequency tuning has low Q (3~5) and lower selfresonant f requency, which limit the t unability of the millimeter-wave VCO [118] Finally, the design of a millimeter-wave frequency divider whic h is driven by an LO in a phase-locked loop (PLL) becomes more difficult [112] An alternative m ethod is to use a frequency mu ltiplier following a PLL stage to provide the desired LO signal [112] The idea is s imilar to that in Chapter 3 where signal from a lower

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104 frequency source is up-converted by the fr equency multipliers to the millimeter-wave frequencies. This increases the flexibility for system design, allowing use of a technology with superior noise performance for realizing a lowe r noise oscillator at lo wer frequencies with improved VCO tunability. Figure 5-1. A 77-GHz hete rodyne receiver prototype. Based on this, a frequency generation plan is proposed and shown in Figure 5-1. This is a dual-conversion heterodyne system with LO signa ls at 4/5 (61.6 GHz) and 1/5 (15.4 GHz) of 77GHz frequency of the input signal. The 15.4-GHz LO signal can be obtained by dividing a 30.8GHz VCO signal. While the 61.6-GHz LO signal can be realized by incorporating a driver amplifier at 30.8 GHz and a frequency doubler following the VCO. No buffer amplifier is used following the frequency doubler to reduce total DC power consumption. In this chapter, the nonlinear device a MO S varactor diode for frequency multiplication is first introduced, and then the design detail s of driver amplifier and frequency doubler are presented. The performance of complete LO signal generation circuit will be given in the end. 5.2 MOS Varactor Diode Voltage-dependent capacitors are called varactors or varicap [3] They are widely used in VCOs for frequency tuning. Besides this, th eir nonlinear C-V character istics are also useful for frequency multiplication as discussed in Chapter 1. LNA Filter Filter VCO (30.8 GHz) Driver X2 /2 90 Base band Targeted design fo (77 GHz) 4fo/5 (61.6 GHz) fo/5 fo/5

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105 In CMOS, reversed-biased p+-n-well diodes and MOS capacitors in accumulation/depletion modes can be used as a varactor [83] The tuning range of a p+-n diode is limited especially when the supply voltage is li mited and the capacitance changes rapidly when the diode starts to be forward-biased. This is accompanied by increased loss due to the conduction current. As the supply vo ltage is scaled down, MOS va ractors exhibit higher Q and wider tuning capability than p-n diodes [119] [120] Therefore, MOS varactors are cho sen as the nonlinear device for frequency multiplication in this design. Figure 5-2. Layout and a cro ss section for a MOS varactor [83] Figure 5-3. Equivalent ci rcu it for a MOS varactor [83] A cross section and a layout of a MO S varactor are shown in Figure 5-2 [83] [121] The corresponding equivalent circuit is also shown in Figure 5-3 [83] where the parasitic inductance Gate terminal Ls Rmetal Rpoly Rwell Cp Cvar n-well terminal contact Gate terminal A A metal W L diffusion STI STI n+ n+ poly Metal 2 n-well p-substrate contact Via1 Metal 1 Metal 1 n-well terminal

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106 of interconnects is modeled by Ls; parasitic resistances incl uding metal, poly and n-well resistances are represented by Rmetal, Rpoly and Rwell; Cp is the parasitic capacitance between gate and n-well terminal and Cvar is the varactor intrinsic capacita nce. The top and bottom plates of MOS varactor are formed by silicided polysilicon and n-well, and are separated by a gate oxide (SiO2) layer with thickness of about several nanometers [122] Due to this thin dielectric layer, the varactor has a high intrinsic capacitance-to-area ratio, especially if it is biased in the accumulation region [122] Table 5-1. Com parison between thin a nd thick gate oxide MOS varactors with L =0.36 m in the UMC 130-nm logic CMOS process MOS varactor Quality factor in accumulation mode Qaccu [1] Capacitance tuning ration [2] Maximum voltage[3] across varactor (V) Thin oxide 16 3.0 1.5 Thick oxide 48 1.9 4.0 [1]: Qaccu=1/( RsCmax), measured at 24 GHz [83] [2]: =Cmax/ Cmin [83] [ 3]: This voltage is limited by reliability of the gate oxide. The nonlinear C-V characteristic of MOS varact or is due to the changes of its operation mode among accumulation, depletion and inversion [19] When the gate to n-well voltage is great than zero, electron s are a ttracted to the polysilicon gate and accumulated at the silicon surface. The capacitance of MOS varactor reaches its maximum value and equals to the gate oxide capacitance. If the voltage polarity is re versed, electrons are repelled away from the surface, which is referred to as the depletion co ndition. The total capacitance of MOS varactor decreases due to the series combination of gate oxide capacitance and depletion capacitance. As the negative gate voltage exceeds the threshold voltage, an invers ion layer is formed at the silicon surface. The capacitance of MOS varactor increases again to the gate oxide capacitance. However, this can only be observed at low freque ncies (several kHz). At higher frequencies, the

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107 inversion charge cannot respond fa st enough to the applied signal and the capacitance remains at its minimum value. Figure 5-4. Thick gate oxide MOS varactor mode l fitting using a Verilog-A code in Cadence. The study in [83] demonstrated that varactors with a thicker gate-oxide layer have higher Q which is defined as 1/( RsC) Besides, the voltage limitation is also higher than that of thin gateoxide MOS varactor which enables higher pow er handling. However the tuning range ( Cmax/ Cmin) is narrower due to the bigger effect of Cp on the lowered Cvar. Table 5-1 summarizes the comparison between the thick and thin gate oxide MOS varactors with L =0.36 m fabricated in the UMC 130-nm logic CMOS process. For millimeter-wave LO signal generation in this design, high Q as well as high power handling capability is desired and thus a thick gate oxide MOS varactor is chosen. A Verilog-A code using a hyperbolic tangent function is utilized to model the MOS varactor in Cadence. Figure 5-4 shows the simula tion results using the Verilog-A code as well as the measurement results of the MOS varactor. The simulation fits well with the measurements. 40 35 30 25 20 -4 -2 0 2 4 Gate voltage (V) Capacitance (fF) Verilog-A code: C1=(Cmax-Cmin)/2; C0=(Cmax+Cmin)/2; V0=-0.2; V1=0.6; Q(V)=C0*V+C1*V1*ln(cosh((V-V0)/V1))) Cmax maximum capacitance Cmin minimum capacitance

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108 5.3 Design of 62-GHz LO Sign al Generation Circuit 5.3.1 Design Specifications and Figures of Merit Table 5-2 lists the design specifications for the 62-GHz LO signal ge neration circuit. The figures of merit include conversion gain (or loss), output powe r, efficiency, and added phase noise. Table 5-2. Design specifications of 62-GHz LO signal generation circuit Specification parameters Target value Input center frequency f0 (GHz) 30.8 Output center frequency fn (GHz) 61.6 Return loss RL (dB) >10 Input power Pin (dBm) <-5 Minimum conversion gain CGmin (dB) >5 Maximum output power Pout (dBm) >0 Efficiency >5% Added phase noise As small as possible Conversion gain ( CG) is the ratio between the desire d output harmonic power and the available source power. Conversion loss ( CL ) is the inverse of CG. This is same as that defined in Chapter 3. Usually, multipliers using active devices will exhibit gain, while those using passive devices will only have loss if no ampl ifier stages are included. The maximum input signal power is limited by the power handling capability of nonlinear devices and impedance matching, while the maximum output power depe nds on the conversion loss as well as the maximum input signal power. Therefore, a devi ce which has high power handling capability is desired to increas e output power. Efficiency ( ), different from the conversion efficien cy in Chapter 3, is now defined as )(0DC nPP P (5-1) where Pn is the desired output harmonic power, P 0 is the input fundamental power, and PDC is the DC power consumption.

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109 Added phase noise ( APN ) is defined as )log(20 N APNout (5-2) where out is the phase noise of output harmonics, and N is the order of output harmonics. A frequency multiplier is naturally a phase multiplier. It multiplies the input frequency as well as the phase deviations and this causes a th eoretical phase noise degradation given by 20log(N) [123] 5.3.2 Method of Improving MOS Varactor Power Handling Capability As discussed in section 3.2.1, for a varactor mode frequency multiplier, it is desirable to increase the voltage swing across varactor to improve conversion efficiency. The measured thick gate oxide MOS varactor C-V curve in Figure 5-4 shows a steep transition from Cmin to Cmax with a narrow active control voltage range from about -0.8 to 0.4 V. This translates to ~5.6-dBm input power handling capability in a 50system with proper bias and it is too low to achieve high conversion efficiency. To solve this, a distributed bias scheme shown in Figure 5-5 is proposed to differently bias several varactors c onnected in parallel [124] The steep portions of each MOS varactor are shifted and the effective C-V curve of the entire structure has sm aller slope but wider voltage control range. In this design, four thick gate oxide MOS varact ors with unit size of 0.36 m ( L ) 16.2 m (W ) are connected in parallel and the n-well node of each is biased through a 5-k nonsilicide polysilicon resist or at 0.1, 0.2, 0.3 and 0.4 V. Biasing the n-well node instead of the polysilicon gate terminal avoids the use of DC blocking capacitors between each varactor, which reduces chip area and eliminates the associated parasitic effects. The active control voltage corresponding to the nonlinear C-V curve region increases ~4X and power handling capability improves ~10 dB from 5.6 to 16 dBm.

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110 Figure 5-5. Proposed distributed bi asing scheme for the MOS varactor. 5.3.3 Design of 62-GHz Frequency Doubler Figure 5-6 shows a standalone 62-GHz freque ncy doubler schematic where the input and output are terminated by 50 This 62-GHz frequency doubler ut ilizes the similar topology as that of the 125-GHz frequency doubler in Chap ter 3 where two 4.36 m.2 m thick-gateoxide MOS varactors are placed in parallel to increase output power. Each MOS varactor is then formed by 4 small varactors shunted and bi ased at different n-well voltages. 5-k polysilicon resistors are used for biasing. Bypass capacitors (5 pF) are need ed at the n-well node of each varactor to provide AC ground. Vbias1 to Vbias4 (0.1 to 0.4 V with 0.1 V step) set the bias voltages for the varactors. DC blocking capacitors CDC1 is necessary to isolate th e varactor bias and can be part of the preceding driver stage. To reduce chip area, line inductors discussed in Chapter 4 and Gate voltage Gate voltage Capacitance Total Capacitance Vbias4 Vbias3Vbias2 Vbias1 Cmin Cma x 4Cmin 4Cma x

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111 metal capacitors are used for the matching network. L2 tunes out the average varactor capacitance and matches the impedances of the two varactor banks to the 50input impedance at f0 to ensure that the maximum fundamental power is delivered to the varactor. The traps at fundamental and second harmonic frequencies at the input and output are replaced by a low pass filter formed by L1, C1 and C2 at input and a notch filter formed by L3 and C3 at output, respectively. The low pass filter at input can filter out the second harmonic and thus minimize conversion loss by reducing its power consumption at input network [39] The notch filter at output is used for the sim ilar reason to provide large suppression for the fundamental signal at output network. Figure 5-6. Schematic of a sta ndalone 62-GHz frequency doubler. The input pad parasitic capacitance as well as parasitic capacitance of L1 can be absorbed into C1 at input node. Parasitics of L1, L2, L3 and C3 can also be absorbed into C2 at node A. Input and output matching are rea lized by the filters. CDC1 f0 L1 C1 C2L 2 L 2 L 3 C3 CDC2 Varactor bank w/ bias Varactor bank w/ bias Lowpass filte r Notch filter at f 0 Varactor bank w/ bias Vbias1Cby1 Rbias1 Cvar1 Vbias2 Cby2 Rbias2 Cvar2 Vbias3Cby3 Rbias3 Cvar3 Vbias4Cby4Rbias4 Cvar4 2f0A

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112 Figure 5-7. Small signal S-parameter simula tion results for the 62-GHz frequency doubler. Figure 5-8. Large signal S-parameter simula tion results for the 62-GHz frequency doubler. To account for the mismatch between simulation and measurement, the designs are tuned at 34 and 68 GHz for input and output frequencie s, respectively. Figures 5-7 and 5-8 show the small and large signal S-parameter simulation re sults. Input and output are well matched at 34 and 68 GHz, respectively. The notch filter at output presents a dip in the |S21| plot at 34 GHz in Figure 5-7 which ensures sufficient rejecti on of fundamental signa l at output. The |S11| at 34 GHz -15 -20 -25 -30 0 5 10 15 S-parameters (dB) Pin (dBm) |S11| at 34 GHz |S22| at 68 GHz |S21| at 34 GHz 0 -5 -10 -15 -20 20 30 40 50 60 70 80 -40 -30 -20 -10 0 Frequency (GHz) S-parameters (dB) S-parameters (dB) |S11| |S22| |S21|

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113 and |S22| at 68 GHz remain below -10 dB up to 15 dBm input. At output, the suppression of fundamental signal (|S21| at 34 GHz) is greater than 25 dB up to 15 dBm input. Figure 5-9. Simulated convers ion loss (CL) versus input po wer for the 62-GHz frequency doubler. Figure 5-10. Simulated output spectrum of the 62-GHz frequency doubler at Pin=10 dBm. Figure 5-9 shows that CL decr eases as the input power incr eases and no sign of saturation is observed up to 15-dBm input power. The output power will be greater than 0 dBm if input power is higher than 10 dBm. The conversion ef ficiency at 10-dBm input is 11.4%. An output 16 14 12 10 8 0 5 10 15 Pin (dBm) CL (dB) 30 50 70 90 110 -30 -20 -10 0 Frequency (GHz)Power (dBm)1.2 dBm at 68 GHz -16.1 dBm at 34 GHz -25.2 dBm at 102 GHz

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114 spectrum at input power of 10 dB m is also shown in Figure 510. At output port, the second harmonic power at 68 GHz (2 f0) is 1.2 dBm, which is about 17 and 26 dB higher than that of fundamental signal and thir d harmonic, respectively. 5.3.4 Design of 31-GHz Driver Amplifier (Power Amplifier) Based on the simulations for a standalone 62-GHz frequency doubler, a driver amplifier at fundamental frequency (30.8 GHz) with output power greater than 10-dBm is required to generate an LO signal with power greater than 0 dBm. Another concern for this driver is that it should have high power efficiency The overall system efficiency is determined by the power hungry driver amplifier. The comparisons of r ecent published power amplifier (PA) at 20 ~30 GHz in Table 5-3 show that the Cl ass-E power amplifier designed in [125] using a m ode-locking technique has the highest efficien cy. Therefore this pow er amplifier topology is chosen for this design. Table 5-3. Comparisons of recent publishe d power amplifiers at 20~30 GHz in CMOS Freq. (GHz) Gain (dB) IDC (mA), Vsupply (V) Pout (dBm) PAE* (%) Topology Area (mm2) Tech. Ref. 24 7 100 mA, 2.8 V 14 6.5 Cascode, 2 stages, Class AB 0.7.8 0.18 m CMOS [126] 20 26 35 mA, 1.5 V 10.2 20.5 Common source, 4 stages, modelocking, Class E 0.9.9 0.13 m CMOS [125] 27 14.5 94 mA, 1.8 V 14 13.2 Common source, 3 stage 0.7.2 0.18 m CMOS [127] 22 16.3 /, 3.6 V 16.8 10.7 Cascode, 3 stage, Class AB 0.7.5 0.18 m CMOS [128] 24 18.8 /, 3.6 V 19.1 15.6 Cascode, 2 stage 0.6.6 0.18 m CMOS [129] *: PAEpower added efficiency, PAE=(Pout-Pin)/PDC. The mode locking is defined as a condition in which an otherwise self-oscillating circuit is coupled and forced to run at the same frequency as an input signa l, which results in a significant reduction of the required input power [130] By combining this with a high efficiency switch

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115 mode Class-E load network, a Class-E mode-l ocking PA has superior power efficiency among all other classic PAs. Figure 5-11. A mode-locking PA. A) Schematic of switching stage [125] B) equivalent circuit between input and drain node of M1 [125] and C) general feedback system between input and drain node of M1. Figure 5-11 A) shows a schematic of the PA, which consists of a conventional Class-E load network formed by L1, L2, C1 as well as C2, and an oscillator formed by inductor Lg together with capacitors Cgd and Cgs [131] CDC is used to isolate bias from the driver stage and Cby is employed to provide AC ground at the bias node. An equivalent ci rcuit and a general feedback diagram between the gate and drain nodes of transistor M1 are also shown in Figure 5-11 B) and C). Zd is the load network impedance. H(s) is th e feedforward transfer function which presents about 180 degree phase shift. G(s) is the feedba ck network transfer f unction. When operating frequency is lower than th e resonant frequency of LgCgs network, the impedance at gate node is inductive with equiva lent inductance of Leq and series resistance of Req. And G(s) can be expressed as [125] Vin CDC Cby Vbias Lg Cgd L1 L 2 C1C 2 RloadVd Class-E load network Oscillato r Vin+ Lg Rg CgsCgd gmVin + VinVdH(s) G(s) A B C M1 + VdZd

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116 gd eqeq eqeq gd gs gg gs gg d insC RsL RsL sCsC RsL sC RsL sV sV sG 1 11 ||)( 1 ||)( )( )( )( 1 12 2 2 2 gdeq gdeq gdeq gdeq gdeq gdeq gdeq gdeqCjRCL CjRCL js sCRsCL sCRsCL (5-3). To satisfy the Barkhausens oscillation criteria [3] and thus to enhance the am plifier power efficiency, G(s) should have another 180 degree phase shift in addition to the 180 degree phase shift from H(s). This can be satisfied when Leq>>Req and <1/ gdeqCL, which means the gate node network should have high inductive Q and the operating frequency should be well below the resonant frequency of Leq-Cgd network [125] The difference between the input frequency and oscillation frequency or locking range can only be determ ined by simulations and experiments [130] Figure 5-12. Schem atic of a mode -locking Class-E power amplifier [125] Vin Lg1 Rg1 Vbias1 M1Cby1 M2Ld1 Cc1 Cby2 Ld2Rg2 Vbias2 Cc2M3M4Rg3M5Ld3L1 Cc3Lg Cby3Vbias3 Vbias4 M6L2 C1 C2 To doubler VDD_driver VDD_PA1 VDD_PA2

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117 However, the PA is inherently unstable. To isolate the input from the unstable switching stages, a 2-stage cascode predriver amplifier is included. They will also provide sufficient gain and good matching for the input [125] A common source amplifier stag e is inserted between the two cascode predriver amplifier and final switc hing stage to accommodate large voltage swing which will be otherwise limited by the voltage headroom of the cascode amplifier [125] A schem atic of the PA is shown in Figure 5-12. Potentially, gate bias resistor Rg3 could be replaced by another high Q inductor with a bypass capacitor like the way Lg and Cby3 are connected. This will reduce the input power requirement even more and further boost the efficiency. However, this will make the PA more unstable and thus only one inductor biased stage is used in this design. The transistors used in this de sign have the same size as that in [125] The W /L ratio is 14 m/0.12 m for M1/M2, 24 m/0.12 m for M3/M4, 40 m/0.12 m for M5 and 100 m/0.12 m for M6. The pad parasitics are included as part of the matching network. High Q spiral inductors and metal cap acitors are used. The gate bias resistors Rg1~Rg3 are 5-k polysilicon resistors. The voltage supply of predriver stages and each switching stages are separated to make the PA more stable by suppressing th e signal coupling through a common VDD. 5.3.5 LO Signal Generation Circuit Si mulation Results and Discussions Combining the 62-GHz standalone frequency dou bler in Figure 5-6 and the 31-GHz PA in Figure 5-12, a 62-GHz LO signal generation circu it is implemented. The component values are adjusted to achieve the highest output power and efficiency. A bond pad is included between the PA and doubler to add the measurement flexibility for individually characterizing both circuits. The supply voltage for the 2-stage predriver amp lifiers and switching stag es are set to 1.45 V. The gates of M1 and M3 are biased at 0.6 V, while the gates of M5 and M6 are biased at 0.45 V in Figure 5-12. The current flowing through M1/M2, M3/M4, M5 and M6 are ~2, 3, 5 and 30 mA at -

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118 10-dBm input, respectively. There is no DC power consumption in the 62-GHz varactor frequency doubler. Figure 5-13. Simulated small signal S-parameters for the 62-GHz LO signal generation circuit. Figure 5-14. Simulated large sign al S-parameters for the 62-GHz LO signal generation circuit. Figure 5-13 shows the simulated small signal S-pa rameters for the entire circuit. The input and output are again well matched to 34 and 68 GHz, respectively. The variation of input and output matching with the input power is also sh own in Figure 5-14. The input matching is below 20 40 60 80 -20 -15 -10 -5 0 Frequency (GHz)S-parameters (dB)|S11| |S22| 34 GHz 68 GHz -20 -16 -12 -8 -20 -16 -12 -8 Pin (dBm)S-parameters (dB)|S11| at 34 GHz |S22| at 68 GHz

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119 -10 dB up to -11-dBm input power The output matching remains relatively constant for the input power ranging from -20 dBm to -9 dBm. Figure 5-15. Simulated output pow er at fundamental frequency (Pf0) and second harmonic (P2f0) versus input power for the 62-GHz LO signa l generation circuit. PA output power is also shown. Figure 5-16. Simulated output spectrum for th e 62-GHz LO signal generation circuit when Pin=10 dBm. 30 50 70 90 110 -30 -20 -10 0 10 Frequency (GHz)Power (dBm)1.4 dBm at 68 GHz -15.9 dBm at 34 GHz -25.7 dBm at 102 GHz -20 -15 -10 -5 -25 -15 -5 5 15 Pin (dBm)Power (dBm)PA output power P2f0 at output Pf0 at output

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120 The output power at fundamental frequency and second harmonic versus input power are shown in Figure 5-15. The PA output power is also given. When the input power is higher than 12 dBm, the PA can provide higher than 10-dBm output and the LO signal generation circuit can have second harmonic power (P2f0) greater than 0 dBm. The fundamental signal power remains below -15 dBm up to -5-dBm input power. Figur e 5-16 shows the output spectrum when the input power is -10 dBm. The output power level of the 62-GHz LO signal generation circuit at 10-dBm input is almost the same as the st andalone 62-GHz frequenc y doubler under -10-dBm pump power shown in Figure 5-10. Figure 5-17. Simulated efficiency versus i nput power for the 62-GHz LO signal generation circuit. The efficiency versus input power plot is shown in Figure 5-17. The maximum efficiency is 2.5% when the input power is -6 dBm. At -10-dBm input, the efficiency is 2.1%. The transient waveforms at input and output are shown in Figure 5-18 where the second harmonic signal at output can be easily observed. The maximum voltage swing across those MOS varactors is less than 2 V under -10-dBm pump power depending on their biases, which -20 -15 -10 -5 0.5 1 1.5 2 2.5 3 Pin (dBm)Efficiency (%)

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121 is well below the reliability voltage limitation of 4 V. Figure 5-19 shows the transient waveform for the MOS varactor wi th n-well node biased at -0.1 V. Figure 5-18. Simulated output transient wave fo rm at output with -10-dBm input power for the 62-GHz LO signal generation circuit. Figure 5-19. Simulated transient waveform acros s a MOS varactor with 0.1-V n-well bias with input power of -10 dBm. 12 12.05 12.1 12.15 12.2 -2 -1 0 1 2 Time (ns)Voltage (V) 0.4 0.2 0 -0.2 -0.4 10 10.01 10.02 10.03 10.04 10.05 Time (ns) V out (V) Vin (V) -0.1 -0.05 0 0.05 0.1 Vout Vin

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122 Table 5-4 summarizes the simulated performan ce of 62-GHz LO signal generation circuit. The comparisons with other recently publishe d CMOS frequency doublers at around 60 GHz are also included. The LO generation circuit in this work has the highest conversion gain with modest DC power consumption. Due to this high conversion gain, the input requirement is much lower than others. However, the suppression of fundamental signal at out put is relatively low which degrades the LO phase noise performance. A higher order notch filter for the doubler or another filter block should be included to impr ove this. Besides, the overall efficiency is not high. This is probably due to the low PAE of ~1 8% for the 31-GHz driver amplifier and high conversion loss of 9.5 dB for the 62-GHz frequency doubler. While other doublers in [132] [134] use active doublers which can provide certain amplification instead of adding loss w ithout consuming excessive power. The performance of th e LO signal generation circuit has met the design specifications listed in Table 5-2. Table 5-4. Performance summary of th e 62-GHz LO signal generation circuit fout (GHz) Pout (dBm) Suppr. (dB) CG (dB) PDC (mW) Eff. (%) Topology Tech. Ref. 58 1.2 35 7.2 26.4 4.9 DA[1]+X2[2]+BA[3], Pin=-6 dBm 0.13m CMOS [132] 60 -10.3 25 -15.3 4 1.3 X2, Pin=5 dBm 90nm CMOS [133 ] 54.2 -4.5 49.2 -0.5 9 3.8 X2+BA, Pin=-4 dBm 0.13m CMOS [134] 61.6 1.4 17 11.4 58 2.1 DA+X2, Pin=-10 dBm 0.13m CMOS This work [1]: DAdriver amplifier. [2]: X2frequency doubler. [3]: BAbuffer amplifier. 5.4 Conclusions The applicability of high Q thick gate oxide MOS varactor diodes fabricated in a foundry CMOS technology for millimeter-wave circuit desi gn has been demonstrated in simulation by implementing a 62-GHz frequency doubler. The control voltage range and power handling capability of the MOS varactor are increased with a distributed bias scheme where several shunt

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123 MOS varactors are biased for varying voltages at the n-well node. Combining with a high efficiency mode-locking 31-GHz power amplifier, the doubler is able to generate a 1.4-dBm 62GHz output signal which can be used for the LO signal in a 77-GHz radar receiver. The signal generation circuit has good input and output ma tching at the fundamental and second harmonic frequencies. The DC power consumption is 58 mW and the power efficiency is 2%.

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124 CHAPTER 6 SUMMARY AND SUGGESTED FUTURE WORK 6.1 Summary The insufficient high frequency performance of the MOSFETs in the advanced CMOS technology limits their applications in the upper millimeter-wave and even terahertz region. Besides this, the lower breakdown voltage resu lting from device scaling limits the power performance of MOSFETs. To mitigate the problem, this research explor ed the possibility of using other devices and techniques without modifying the existing foundry process. Schottky barrier diodes and p-n diodes fabricated in standard CM OS technologies are shown to be useful for these purposes. A distributed biasing scheme for accumulation mode MOS varactor diodes is also proposed to enhance the power handling capability. In this work, Schottky barrier diodes (SBDs) with and without guard rings fabricated in a 130-nm foundry CMOS technology have measured cut-off frequency of ~2 THz and ~1.5 THz, respectively. These are the highest cut-off frequency reported in CMOS up to the present and ~57X of that for MOSFETs in the mo st advanced CMOS technology today [110] [111] The diodes can b e used to implement upper millimete r-wave and even terahert z circuits. This will provide a low cost and high integration solution for implementing terahertz systems. The trade-off between the cut-off frequency and C-V nonlinearity of Schottky barrier diodes has been studied and used for the successful demonstration of a 132-GHz varistor mode and a 125-GHz varactor mode frequency doubler in the 130-n m logic CMOS process. The doublers exhibit 14and 10-dB conversion loss at 132and 125-GHz output, respectively. P-n diodes with equivalent on-resistance as an NMOS transistor have ~3X lower parasitic capacitances and ~2-3X higher breakdown voltage in the 130 -nm CMOS technology. Using a

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125 similar optimized layout as that of high Q Schot tky barrier diode, a cut-off frequency of ~1.8 THz has been achieved for the diode [104] The usefulness of this high quality diode has been dem onstrated by implementing a 60-GHz hybrid p-n diode/MOS transistor transmit/receive (T/R) switch. The switch exhibits insertion loss of ~2 and 3 dB in transmit and receive mode at 60 GHz, respectively. The measured input 1-dB compression point which is limited by the measurement setup is higher than 18 dBm. Th e isolation between the transmitter and receiver ports is ~20 dB in transmit mode at 60 GHz. This T/R switch exhibits the highest power handling capability among millimeter-w ave switches fabricated in CMOS with low insertion loss. It shall be possible to use this diode for T/R switc h designs for operation at 100 GHz and higher. A distributed biasing scheme is also invest igated in simulation to improve the power handling capability of the conventional MOS varact or diodes. By differently biasing the n-well nodes of several shunted thick gate oxide MOS va ractors, the voltage ra nge over which varactor capacitance varies and thus power handling capability are increas ed. Using this technique, a 1dBm 62-GHz signal is generated in simulation. This signal can be used as the LO signal of 77GHz heterodyne radar. 6.2 Future Work 6.2.1 Optimization and Characterization of Sch ottky Barrier Diodes The techniques of optimizing the SBD performance have been demonstrated in a 130-nm CMOS technology. The validity of this needs to be verified by characterizing optimized structures in other more advanced CMOS t echnologies. The factors limiting SBDs performance in each technology should be understood.

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126 6.2.2 Performance Improvement of 60-GHz T/R Switch The switching speed of the 60-GHz T/R switch is on the order of several nanoseconds, which is much slower than the one in [99] A 60-GHz T/R switch with f aster switching speed should be implemented in the future. The sizes of diode D1 and MOSFET MN2 as well as MN3 in Figure 4-16 should be adjusted to balance th e insertion loss for TX and RX branch. The possibility of using the high breakdown voltage diode for handling even larger power at 30-dBm or higher should be investigated. 6.2.3 Implementation and Characterization of 62-GHz LO Signal Generation Circuit The 62-GHz LO signal generation circuit design needs to be verified by fabricating the circuit in the 130-nm logic CMOS process. The performance of circuit using distributed and fixed biasing schemes should be compared to u nderstand the validity of distributed bias for power handling capability improvement.

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137 BIOGRAPHICAL SKETCH Chuying Mao was born in W uhan, Hubei, China in 1979. She received the Bachelor of Science and Master of Science in instrumentation engineering from Shanghai Jiaotong University, Shanghai, China, in 2001 and 2003, resp ectively. In 2005, she rece ived the Master of Engineering in electrical and computer engineeri ng from the University of FloridaGainesville. She received her Ph.D. from the same depa rtment in 2009 and has been with the Silicon Microwave Integrated Circuits and Systems (SIMICs) Research Group since 2004. Her current research interests include millimeter-wave and THz circuit designs in CMOS.