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Digital Aided Synchronization and Mixed Signal Modeling of High Frequency DC-DC Converters

Permanent Link: http://ufdc.ufl.edu/UFE0024174/00001

Material Information

Title: Digital Aided Synchronization and Mixed Signal Modeling of High Frequency DC-DC Converters
Physical Description: 1 online resource (64 p.)
Language: english
Creator: Bhatia, Deepak
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: converter, dc, dpll, synchronization
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, M.S.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: As technology progresses and device dimensions shrink, analog design becomes increasingly difficult because of smaller supply voltages, higher leakage, and difficulty in the matching of device parameters. Fully scalable analog solutions are difficult to achieve and redesign is often needed for each technology node. Most digital circuits, however, remain portable. Digital designs are less susceptible to both internal and external sources of noise. All of the aforementioned trends are driving the industry to create digital implementations of traditional analog circuit blocks. Motivated in-part by the scalability of digital design, we propose a digitally aided synchronization scheme for high frequency dc-dc converters. High frequency dc-dc converters are gaining interest for localized power delivery solutions where fast transient response and localized voltage control is critical. In this thesis, we propose a digital phase locked loop (DPLL) based frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed technique achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or output voltage conversion range. The DPLL is programmable over a wide range of parameters and can be locked to a reference clock to ensure the converter switching frequency falls outside power supply resonance bands. The entire DPLL, except the delay line, is synthesizable. In addition, a behavioral model which describes the dc-dc converter as a voltage controlled oscillator is proposed and the analysis of the entire design as a Charge Pump PLL (CPPLL) is presented. The DPLL synchronized converter works over a frequency range of 90-240MHz and was implemented in a 130nm digital CMOS process. A simulation approach for mixed signal designs is described. This methodology helps in reducing interface problems for large designs and also decreases simulation time. In addition, aspects of digital synthesis flow are described. A mixed signal simulation of a DPLL synchronized buck converter is presented as an example to show how SpectreVerilog can be used to validate the analog-digital interface and verify proper functionality of the design.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Deepak Bhatia.
Thesis: Thesis (M.S.)--University of Florida, 2009.
Local: Adviser: Bashirullah, Rizwan.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2009-11-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0024174:00001

Permanent Link: http://ufdc.ufl.edu/UFE0024174/00001

Material Information

Title: Digital Aided Synchronization and Mixed Signal Modeling of High Frequency DC-DC Converters
Physical Description: 1 online resource (64 p.)
Language: english
Creator: Bhatia, Deepak
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: converter, dc, dpll, synchronization
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, M.S.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: As technology progresses and device dimensions shrink, analog design becomes increasingly difficult because of smaller supply voltages, higher leakage, and difficulty in the matching of device parameters. Fully scalable analog solutions are difficult to achieve and redesign is often needed for each technology node. Most digital circuits, however, remain portable. Digital designs are less susceptible to both internal and external sources of noise. All of the aforementioned trends are driving the industry to create digital implementations of traditional analog circuit blocks. Motivated in-part by the scalability of digital design, we propose a digitally aided synchronization scheme for high frequency dc-dc converters. High frequency dc-dc converters are gaining interest for localized power delivery solutions where fast transient response and localized voltage control is critical. In this thesis, we propose a digital phase locked loop (DPLL) based frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed technique achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or output voltage conversion range. The DPLL is programmable over a wide range of parameters and can be locked to a reference clock to ensure the converter switching frequency falls outside power supply resonance bands. The entire DPLL, except the delay line, is synthesizable. In addition, a behavioral model which describes the dc-dc converter as a voltage controlled oscillator is proposed and the analysis of the entire design as a Charge Pump PLL (CPPLL) is presented. The DPLL synchronized converter works over a frequency range of 90-240MHz and was implemented in a 130nm digital CMOS process. A simulation approach for mixed signal designs is described. This methodology helps in reducing interface problems for large designs and also decreases simulation time. In addition, aspects of digital synthesis flow are described. A mixed signal simulation of a DPLL synchronized buck converter is presented as an example to show how SpectreVerilog can be used to validate the analog-digital interface and verify proper functionality of the design.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Deepak Bhatia.
Thesis: Thesis (M.S.)--University of Florida, 2009.
Local: Adviser: Bashirullah, Rizwan.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2009-11-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0024174:00001


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1 DIGITAL AIDED SYNCHRONIZATION AND MIXED SIGNAL MODELING OF HIGH FREQUENCY DC DC CONVERTERS By DEEPAK BHATIA A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQU IREMENTS FOR THE DEGREE OF MASTER OF SCIENCE UNIVERSITY OF FLORIDA 2009

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2 2009 Deepak Bhatia

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3 To my Mom and Dad

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4 ACKNOWLEDGMENTS First of all I would like to thank my academic advisor Dr. Rizwan Bashi rullah for his v aluable guidance over the last two years. I would also like to thank Dr Robert Fox and Dr William Eise nstadt for their advice and their willingness to be on my thesis committee. S pecial thanks go to Chung Ching Peng for teachi ng me everything about Digital Synthesis Design flow and f or all the support and help. S pecial thanks go to Jikai Chen, Hang Yu, Pawan Sabharwal and C.M.Tang for useful designrelated discussions. I also thank Yan Hu, Pengfei Li, X iao Zhiming and Xue Lin for always being open to answer any question at any time, day or night. Considering classes at the U niversity of Florida (UF), I thank Dr. Rizwan Bashirullah for hi s excellent Advanced VLSI class; Dr Fox for his Bipolar and MOS design clas s es especially the simple design related app roach and second order analysis; and Dr Kenneth O for his excellent Microwave IC design class. S pecial thanks go to C.M Tang for the baske tball training and Chris for the small b ut great guitar lessons. I will miss playing basketbal l with all the guys : the Chris shot and ChungChings accurate baskets S pecial thanks go to Pawan Sabharwal, Abhishek Verma and Haswath for all their help and support day in and day out. I will never forget the late night discussions we had. I thank Geo ff for always supporting me in discussio ns and arguments with Chris. S pecial thanks go to Yan Hu for being so sweet and supportive. S pecial thanks go to Quizhong Wu for helping me with my thesis by taking most of the burden of the VLSI class Finally, I th ank my mom, dad and brother for all their love and support I love them all.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................................... 4 LIST OF TABLES ................................................................................................................................ 7 LIST OF FIGURES .............................................................................................................................. 8 ABSTRACT ........................................................................................................................................ 10 CHAPTER 1 INTRODUCTION ....................................................................................................................... 12 1.1 Overview ............................................................................................................................... 12 1.2 Motivation ............................................................................................................................. 13 1.3 Study Overview ..................................................................................................................... 14 2 LITERATURE REVIEW ........................................................................................................... 15 2.1 Basic Phase Locked Loop (PLL) ......................................................................................... 15 2.2 Charge Pump Phase Locked Loop ....................................................................................... 15 2.2.1 Loop Analysis ............................................................................................................. 17 2.2.2 Phase Noise and Jitter ................................................................................................ 20 2.3 Digita l Phase Locked Loop .................................................................................................. 21 2.3.1 Linear Digital Phase Locked Loop............................................................................ 21 2.3.2 Bang Bang Digital Phase Locked Loop .................................................................... 23 2.3.3 Loop Analysis of a Linear DPLL .............................................................................. 24 2.3.4 Linear PLL Design Using Charge Pump PLL .......................................................... 25 3 SYNCHRONIZING SCHEME FOR BUCK CONVERTER .................................................. 27 3.1 Basic Buck Converter ........................................................................................................... 27 3.2 Synchronization Scheme for DC DC Buck Conver ter Using DPLL ................................ 29 3.2.1 Architecture of DC DC Buck Converter with DPLL .............................................. 29 3.2.2 Digital Phase Locked Loop (DPLL) ......................................................................... 31 3.2.2.1 Phase frequency detector ................................................................................. 32 3.2.2.2 Digital loop filter ............................................................................................. 33 3.2.2.3 F irst order sigma delta ..................................................................................... 34 3.2.2.4 Digitally controlled delay line ........................................................................ 35 3.3 Modeling of DC DC Buck Converter and Analysis as a CPLL ........................................ 36 3.3.1 Modeling DC DC Converter as a VCO .................................................................... 36 3.3.2 Analysis of a PLL Synchronized DC DC Converter as a Charge Pump PLL ....... 38 3.3.3 Transient Response for Phase and Frequency Step .................................................. 40 3.3.3.1 Phase step ......................................................................................................... 41 3.3.3.2 Frequency step ................................................................................................. 45

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6 3.4 Experimental Results ............................................................................................................ 48 3.4.1 Frequency Synchronization Test ............................................................................... 49 3.4.2 Jitter Measurement ..................................................................................................... 49 4 MIXED SIGNAL SIMULATION ENVIRONMENT .............................................................. 51 4.1 Mixed Signal D esign Flow ................................................................................................... 51 4.2 Mixed Signal Simulation Environment ............................................................................... 53 4.3 Digital Modeling and Synthesis Flow ................................................................................. 55 4.4 Mixed Signal Simulation of DPLL Synchronized Buck Converter .................................. 56 4.4.1 Response of DPLL to Change in Proportional Path Gain ....................................... 56 4.4.2 Response of DPLL to a Frequency and Phase Step ................................................. 57 4.4.3 Response of DPLL to a Load Step ............................................................................ 58 5 CONCLUSIONS ......................................................................................................................... 60 LIST OF REFERENCES ................................................................................................................... 62 BIOGRAPHICAL SKETCH ............................................................................................................. 64

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7 LIST OF TABLES Table page 2 1 The values of PK and IK using bilinear and impulse invariant transform ......................... 26 4 1 Simulators in cadence for different models .......................................................................... 53

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8 LIST OF FIGURES Figure page 2 1 Block diagram of a PLL ......................................................................................................... 15 2 2 Block diagram of a CPLL ...................................................................................................... 16 2 3 Open loop transfer function ................................................................................................... 18 2 4 Step response of a CPPLL ..................................................................................................... 19 2 5 Transfer function of jitter ....................................................................................................... 20 2 6 Effect of PLL on output frequency spectrum ....................................................................... 21 2 7 Block diagram of a linear TDC based DPLL ....................................................................... 22 2 8 Block diagram of a bang bang DPLL ................................................................................... 23 2 9 Linear discrete time model of a DPLL ................................................................................. 24 2 10 An s -domain model ................................................................................................................ 26 3 1 Basic buck converter topology .............................................................................................. 27 3 2 Hysteretic loo p based dc dc converter ................................................................................. 29 3 3 Digital phase locked loop synchronized hysteretic controlled buck converter .................. 30 3 4 Digital phase locked loop ...................................................................................................... 32 3 5 Phase frequency detector ....................................................................................................... 33 3 6 Proportional integral filter ..................................................................................................... 34 3 7 First order sigma delta ........................................................................................................... 34 3 8 Coarse tuning stage ................................................................................................................ 35 3 9 Fine dela y stage ...................................................................................................................... 36 3 10 An s -domain model of the CPPLL with dc dc converter as a VCO ................................... 38 3 11 Bode plot of the open loop transfer function for different damping factor. ....................... 39 3 12 Bode plot of the closed loop transfer function for different damping factor ...................... 40 3 13 Tran sient response to a phase step for different damping factors ....................................... 41

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9 3 14 Transient response to a phase step ( 53 0 ) ..................................................................... 43 3 15 Transient response to a phase step ( 59 .2 ). .................................................................... 44 3 16 Transient response to a frequency step for different damping factor ................................. 45 3 17 Transient response to a frequency step ( 53 .0 ) .............................................................. 46 3 18 Transient response to a frequency step ( 59 .2 ) .............................................................. 47 3 19 Die of dc -dc with DPLL ........................................................................................................ 48 3 20 Converter switching frequency vs output voltage ................................................................ 49 3 21 Jitter histogram ....................................................................................................................... 50 4 1 High level simulation flow .................................................................................................... 52 4 2 Analog, digital blocks in mixed signal simulation environment ......................................... 54 4 3 Hierarchical editor window ................................................................................................... 54 4 4 Digital synthesis flow ............................................................................................................ 55 4 5 Control voltage vs time for different values of Kp .............................................................. 57 4 6 Control voltage vs time .......................................................................................................... 58 4 7 Control voltage vs time for a load step. ................................................................................ 59

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10 Abstract of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Master of Science DIGITAL AIDED SYNCHRONIZATION A ND MIXED SIGNAL MODELING OF HIGH FREQUENCY DC DC CONVERTERS By Deepak Bhatia May 2009 Chair: Rizwan Bashirullah Major: Electrical and Computer Engineering As technology progresses and device dimensions shrink, analog design becomes increasingly difficu lt because of smaller supply voltages, higher leakage, and difficulty in the matching of device parameters Fully scalable an alog solutions are difficult to achieve and redesign is often needed for each technology node Most digital circuits, however, rem ain portable D ig ital designs are less susceptible to both internal and external sources of noise All of the aforementioned trends are driving the industry to create digital implementations of traditional analog circuit blocks. Motivated in part by the scalability of digital design, we propose a digitally aided synchronization scheme for high frequency dc -dc converter s High frequency dc -dc converters are gaining interest for localized power delivery solutions where fast transient response and localized voltage control is critical. In this thesis, we propose a digital phase locked loop (DPLL) based frequency locking technique for high frequency hyste r etic controlled dc -dc buck converters The proposed technique achieves constant operating frequency over a wide output vol t age range, eliminating the dependence of switching frequency on duty cycle or output voltage conversion range. The DPLL is programmable over a wide range of parameters and can be locked to a reference clock to ensure the converter switchi ng frequency falls outside power

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11 supply resonance bands. The entire DPLL, except the delay line is synthesizable. In addition, a behavioral model which desc ribes the dc -dc converter as a v oltage controlled oscillator is proposed and the analysis of the entire design as a Charge Pump PLL (CP P LL) is presented. The DPLL synchronized converter works over a frequency range of 90 240MHz and was impl e mented in a 130nm digital CMOS process. A simulation approach for mixed signal designs is described. This methodol ogy helps in reducing interface problems for large designs and also decreases simul ation time. In addition, aspects of digital s ynthes is flow are described. A mixed signal sim ulation of a DPLL synchronized buck converter is presented as an exampl e to show how Spectre Verilog can be used to validate the analog -d igital interface and verify proper functionality of the design.

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12 CHAPTER 1 INTRODUCTION 1.1 Overview Phase Locked Loop (PL L) is a common building block in a variety of applications such as transceiver s, microprocessors, and memories. In transceivers, PLL s are used as frequency synthesizers an d for Clock and Data recovery (CDR). In microprocessors PLL s are used for clock generation, and also for skew reduction. All these applications have led to a lot o f focus being giv en to the design of PLLs We investigated the use of D igital Phase Locked Lock (DPLL) circuits in high frequency dc -dc co nverter applications We focus ed on d igital implementation because of the advantages listed below. Digital systems are m ore immune to noisy environment s when compared to a nalog systems. D evice scaling leads to more gate leakage, issues with matching of devices and other related problems; all of which effect a nalog circuit s more than digital circuits. Thus, analog d esign s must be re -designed each time there is a change in technology This process leads to a slow design cycle for analog products which affects the time to market, the ability to compete in the industry, and the projected profi t On the other hand, digital bl ocks are portable to newer technologies which results in a smaller design cycle. All of these considerations have lead to a growing demand for the development of digital equivalents of a nalog circuits. Although the trend is to digitize as many components i n the system as possible, complete digitization of the all the components in many system s is difficult. Traditionally most mixed signal designs have a large digital block and a small analog block To design and test these designs is not a trivial task. C are has to be ta ken while interfacing the analog and digital components In addition simulations must be performed to check for func tionality under all conditions; these generally take a large a mount of time and resources. A mixed signal simulation

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13 approa ch is presented. This method was developed to decrease failures due to interface problems between blocks and to reduce simulation time for large circuits 1.2 Motivation H igh performance processors require the insertion of near load dc -dc converter s with f ast load response and small output voltage ripple to meet peak and transient current demands with tighter supply voltage tolerances To achieve this goal, high frequency dc -dc converters have been proposed [1 ]. Classically, either a pulse width modulation (PWM) or hysteretic con troller based control scheme have been used to regulate the output voltage of the converter. Unlike the PWM loops, hysteretic controller s exhibit a near immediate load response and are inherently stable. However, i n the hysteretic co ntroller the free running switching frequency changes with conversion voltage. If left unchecked, the freerunning oscillations may fall in unde sired power supply resonance bands created by parasitic package inductance interconnects and on -d ie decoupling c apacitances. Operation at these frequencies can potentially generate large voltage excursions in the sup ply network due to high impedance peaks formed by the multi -resonant networks, compromising overall system op e ration and device reliability [ 2 ]. Therefo re, ideally it is desirable to synchronize the converter to an on -chip clock generated from within the proce s sor to mitigate noise injection in undesirable frequency bands. We proposed a Digital Phase lock loop ( D PL L) based synchronization scheme to solve this problem D igital implementation of the PLL is preferred due to the advantages provided. First, as stated earlier, digital circuits are less prone to noise than their analog counterparts and are portable. Sec ond, digital circuits dont require the use of resistor s and capacitors ; these components are absent f r om standard CMOS logic libraries Finally, the area and power c onsumption of a digital version is lower T he design described in the thesis has both analog and

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14 d igital blocks. To ensure proper ope ration and avoid interface error s a mixed signal simulation environment using SpectreVerilog is also presented in the thesis 1.3 Study Overview The focus of th is thesis is to present the design of a DPLL ci rcuit Also, a simulation scheme for mixed signal designs is presented. A literature review of DPLL designs is presented in c hapter 2 Chapter 3 describes the design of the DPLL used for synchronizing a b uck converter to an onchip clock used to mitigate noise injection in undesirable frequ ency bands Th e modeling of the dc -dc converter as a voltage controlled oscillator ( VCO ) and the analysis of the entire system as a charge pump PLL (C P P LL ) is proposed. A description of the mixed signal desi gn environment and simulation flow is presented in c hapter 4 T he simulators used at each level of the design cycle are presented. Finally the conclu sions are presented in chapter 5

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15 CHAPTER 2 LITERATURE REVIEW 2.1 Basic Phase Locked Loop ( PLL ) A Phase Locked Loop (PLL) is a feedback circuit which synchronizes an ex ternal signal with refer ence to both frequency and phase [ 3 ]. A wide variety of PLL implementations have been proposed over the years but the b asic building blocks remain unchanged. Figure 2 1 shows a simple block diagram of a PLL. It consists of three m ain components : a p hase detector, a low pass filter and an oscillator. The phase detector compares the phase s of the reference and output signals, refF and divF respectively, to produce an error signal. The loop filter utilizes the error to generate a control signal that adjusts the oscillation frequency The oscillator frequency is increas ed or decreased until the phase difference between the reference and the output is made as low as possible (ideally zero). The PLL c an also be used as a frequency multiplier if it has a divider i n the feedback path ( Figure 2 1 ). In this case, the output frequency is N times the frequency of the reference ( ref outF N F ), where N is the divide ratio N / 1 refF PD/PFD Loop Filter Oscillator outF divF Fig ure 2 1 Block diagra m of a PLL 2.2 Charge Pump Phase Locked Loop Figure 2 2 shows the block diagram of a Charge pump PLL. The b asic components of the CP PLL [ 4 ] are a phase frequency d etector (PFD), charge pump, loop filter and a voltage controlled oscillator (VCO) The CPP LL operated by comparing the phase of the reference

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16 signal refF and the output signal divF using a PFD. The comparison produce s two signals UP and DOWN, whose duration s determine the on time s for the switches S1 and S2 of the charge pump. W hen the CP P LL is first turned on, the difference in frequencies of refF and divF is large. In response, the PFD initially acts like a frequency detector and brings refF and divF closer ; after this start up time the PFD acts as a phase detector. The charge pump is connected to a low pass RC filter supplying or removing charge, depending upon which of the two switc hes S1 and S2 is on. The l oop filter attenu ates the high frequency components and provides a steady dc value to the VCO at lock. The resistor in the loop filter is crucial as it determines the stability of the loop by sett ing the position of the feed -forward zero. The dc voltage at the out put of the loop filter controls the frequency of the VCO. As the VCO frequency increases, the CP PLL is able to accumulate phase faster, graduall y decreasing the phase error in order to attain lock. N / 1 refF PFD VCO outF divF S2 S1 R C DOWN UP Figure 2 2 Block diagram of a C PL L

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17 2.2.1 Loop Analysis The sta bility of the C P PLL can be understood by analyzing the open loop and closed loop transfer function s Because the loop filter integrates the charge representing the phase error and the VCO integrates the output frequency, the CPPLL response has a second ord er response. The open loop transfer function is given by Equation 2 1 [4 ]. N s K Cs R I s svco p open in out1 1 2 ) ( ) ( (2 1) w here Ip is the charge pump current, R is the resistance and C is the capacitance of the capacitor in the loop filter, Kvco is the gain of the VCO, and N is the divide ratio. The closed loop transfer function for the CPPLL is given by Equation 2 2 [4 ]. N K C I Rs N K I s RCs CN K I s s s Hvco p vco p vco p closed in out 2 2 1 2 ) ( ) ( ) (2 (2 2 ) The feed -forward zero, natural frequency damping factor, and loop gain are given by RC sz1 (2 3 ) CN KIvco p n 2 (2 4 ) N CK I Rvco p 2 2 (2 5 ) CN K I Kvco p loop2 (2 6) Using Equations 2 3, 24, 2 5, 2 6 the Equations 2 1 and 22 become 2) 1 ( ) ( ) ( ss s K s sz loop open in out (2 7)

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18 2 2 22 2 ) (n n n ns s s s H (2 8) The damping factor is a very good indicator of the stability of the system. The damping factor for a CP PLL depends on vco pK I and on R where pI is the charge pump current so urce current and vcoK is the gain of the VCO The effect of increasing the resistance on the stability of the system can be explained using Figure 2 3. Increasing R w ill increase the damping factor and move the feed -forward zero towards the origin (Figure 2 3B). As the zero moves towards the origin, the phase margin increases from 73 degrees to 89 degrees making the system more stable. Similarly, increasing pI and vcoK also incr eases the damping factor and improves stability. Thus, the higher the damping factor, the better the stability of the system. In the CPPLL there will be a third pole introduced due to parasitic capacitance at the VCO which will degrade the -50 0 50 100 150 200 Magnitude (dB) 104 105 106 107 108 109 -180 -135 -90 Phase (deg) Frequency (rad/sec) =0.31539 =1.577 =2.8385 Figure 2 3 Open loop transfer function. A) Bode plot. B) Pole zero plot. PM=89deg PM=73deg A

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19 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 x 106 -1 -0.5 0 0.5 1 Real AxisImaginary Axis =0.31539 =1.577 =2.8385 Figure 2 3 Continued phase margin. For good stability, the frequency of the zero should be at least an order of magnitude lower than the pole frequency. The damping factor also affects t he response of the PLL to a phase step (Figure 2 4). The higher the damping factor, the more quickly the system settles. 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 x 10-6 0 0.5 1 1.5 Time (sec)Amplitude =0.31539 =1.577 =2.8385 Figure 2 4 Step r esponse of a CP P LL B

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20 2.2.2 Phase Noise and Jitter Phase n oise and j itter are two important parameters in PLL design. The PLL has two main sources of jitter, reference in put jitter and VCO jitter [4 ]. The jitter can either be slow or fast. A PLL acts as a low pass filter ( Figure 2 5A ). I f we have slow jitter at the reference it will pass directly to the output Fast jitt er will be attenuated by the LPF and will have less effect at the output. The second jitter comes from the VCO itself. The VCO jitter transfer function is h igh pass in nature ( Figure 2 5B ). The high pass nature of the transfer function prevents the slow VC O jitter to pass to the output. However, the fast jitter component would pass directly to the output Thus, when a clean reference clock is available, a wide bandwidth PLL is desirable as it helps reject VCO noise. Change in in out BW in Change in in vco vco Figure 2 5 Transfer function of jitter A) From i nput B) From VCO. Figure 2 6 shows the power spectral density (PSD) of the VCO in a free running (un locked) state and a phase locked state. The free running PSD is shown by the dotted line and the locked state PSD is given by t he solid line. When locked the PLL will act as a high pass f ilter to the VCO phase noise, such that noise that is close to the free running frequency, ffr is attenuated but the high frequency noise remain s (Figure 2 6). The area under the PSD curve is an indica tor of the amount of phase noise [5]. The b andwidth of the PLL is also determined from the PSD. A B

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21 frequency PSD frf BW BW Free running Locked state Figure 2 6 Effect of PLL on output frequency spectrum 2.3 Digital Phase Locked Loop DPLL architectures can be broadly classified into two categories : Linear Dig ital Phase Locked Loop (L -DPLL), Bang Bang Digital Phase Locked Loop (BB DPLL). A brief overview of these two architectures is presented in the following sections. 2.3.1 Linear Digital Phase Locked Loop Figure 2 7 shows t he block diagram of a l inear DP LL It consists of a time to digital converter (TDC), a digital loop filter, a digitally controlled oscillator (DCO) and an optional divider. The TDC compares the reference signal with the feedback signal and prod uces a digital equivalent of an error signal. A TDC has a delay line with registers which sample the amount of phase error and generate the error word. Resolution of the delay line is a very important parameter in the TDC design The TDC which has several common architectures, is also referred to as a phase to d igital converter [6, 7 ]. The o utput from the TDC is passed to a digital loop filter that filters the information and gives the final control word to the digitally controlled oscillator (DCO). The DCO changes the output frequency depending u pon the control word. The

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22 output divF is fed back to the input and compared to refF The lock time of a TDC based DPLL is small. However, design of th is type of PLL s is a bit complex as the resolution of the delay cell s in the TDC has to be very high and calibration of the delay line has to be done to make it tolerant to pr ocess and ambient conditions [8]. The DPLL is linear because each value of phase error has a corresponding unique control word; there is a one to one mapping. The smallest error that this type of DPLL can detect will depend upon the resolution of the delay line which, in turn, constitutes its static phase error [9 ]. N / 1 refF TDC Digital Loop Filter DCO outF divF Figure 2 7 Block diagram of a l inear TDC based DPLL Chung et al [10], Watanabe et a l [11 ], and Dunning et al [12 ], presented several a rch itectures of fast locking DPLL designs, each based on standard cell s These designs are either fully or partly synthesizable which make s them extremely portable. In partly synthesized designs the DCO is generally custom made. The all -digital PLL (ADPLL) [ 10] u tilizes a fr equency tracking algorithm that uses adaptive step size s to a chieve fast lock times. It also presents a new fine delay cell design. A fast locking DPLL with a fixed 50 cycle lock time [12 ] works in four modes : frequency acquisition, phase acquisition, frequency maintenance and phase maintenance It use s frequency comparators and a gain mechanism to attain a fast lock time. Another fast locking PLL with 7 cycle lock time [11], has a TDC which acts as a phase and frequency detector and uses a common ring delay line for the TDC a nd DCO. This design allows

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23 for the matching of the resolution of both circuits i rrespective of voltage and temperature variations. 2.3.2 Bang Bang Digital Phase L ocked Loop Figure 2 8 shows the block diagram of a b ang bang PLL. A b ang b ang DPLL uses a phase detector (PD) or a phase frequency detector (PFD) to compare the phase of the reference refF and the feedback signal divF and provides an early/late (e/l) signal based on the comparison. This si gnal is then passed to a digital loop filter that produces a control word The control word adjusts the DCO to tune the frequency This design is non linear as the output of the P D/PFD is either or irrespective of the amount of phase error In addition the l ock time is long as the filter accumulates phase error over many clock cycles before updating the control word. However design of BB DPLL is less complex as it does n ot involve making a high resolution delay line N / 1 refF PD/PFD Digital Loop Filter DCO outF l e / divF Figure 2 8 Block diagram of a bang bang DPLL The wide range a ll d igital b ang b ang PLL design [13 ] is a low jitter implementation with a ring oscillator based DCO design. It operates over a wide voltage ra nge and uses a 3rd order MASH sigma delta modulator to improve the resolution. In PLL designs the most crucial part is the oscillator design. A few of the commonly used architectures are discussed here. A VCO used in conjunction with a D/A converter can b e used as an oscillator [1 4 ]. Though the design is

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24 simple it is not portable because of its analog nature. Also, the fact that D/A converter s occupy an extremely large area is an additional drawback A n LC tank with a varactor bank designed to control the oscillation frequency is another option [1 5 ]. A digital control is used to control the varactor bank. This design has very good resol ution and low spurious tones, thus it is advantageous for RF applications. A ring oscillator based DCO with multiple tri -s tates in parallel can also be implemented [13]. Th is DCO is made f rom standard library cells, m aking it very porta ble. In addition, Chen et al [16] and Sheng el al [17] present some other commonly used DCO architectures 2.3.3 Loop Analysis of a Linear D PLL Figure 2 9 shows a linear discrete time model of a DPLL [18]. The loop filter transfer function is given by Equation 2 5 11 ) ( z K K z FI P (2 5) KPKI refF 1 z 1 z Kdco N / 1 outF Loop Filter Figure 2 9 Linear discrete time m odel of a DPLL where PK is the proportional path gain and IK is the integral path gain. The transfer function of the DCO is given by

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25 1 ) ( z K z Fdco DCO (2 6) where dcoK is the DCO gain. The closed loop transfer function for the DPLL is N K K z N K K K z K KK z K K K z HI dco I P dco I P P I P dco1 ) (2 ) ( ) (2 (2 7) A root locus analysis of the closed loop trans fer function [18 ] indicates that PK controls the damping factor of the DPLL and has less impact on the closed loop bandwi dth. The analysis also shows tha t IK affects both the bandwidth and damping factor. High value s of IK make the system oscillatory and high values of PK make it stable. This indicates that the ratio, I PK K shou ld be high for stable operation. 2.3.4 Linear PLL D esign U sing Charge Pump PLL A design procedure exists for deriving parameters for a DPLL based on an analog CPPLL [19]. Figure 2 10A and B show the s -domain model for C P PLL and DPLL respectively. Based on the s domain model, the two systems become equivalent if TDC ref CPT I (2 8) dco vcoK K (2 9) ) ( ) ( s H s Z (2 10) Based on E quation 2 10, a digital equivalent of an analog RC filter is to be designed. A digital loop filter with a proportional path gain, PK and integral path gain IK represents an appropriate digital equivalent of the analog RC model [19]. Bilinear or i mpulse invariant transform s are u sed to transform the analog filters to their digital counterparts The bilinear transform preserves the frequency response and stability of the system and the impulse invariant

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26 ) ( s Z 2 / Icp s Kvco/ N / 1 refF outF ) ( s H 2 /refT s Kdco/ N / 1 refF outF TDC / 1 divF divF Figure 2 10. An s -domain model A) CPLL B) DPLL transform preserves the shape of the impulse response during s domain to z -domain transformation. Table 2 1 lists the values of PK and IK given by each of the transforms. Table 2 1 The value s of PK and IK using bilinear and i mpulse i nvariant transform Bilinear Transform Impulse Invariant Transform PK C T Rs2 R IK C Ts C Ts Based on the equivalence provided by a Bilinear model, a relation between PK and IK is given by Equation 2 11 2 1 s I PT RC K K (2 11) Though PK and IK individually a ffect the stability, its the ratio KP/KI that actually determines when the system is stable. Higher the value of KP/KI more stable the system is same [18]. B A

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27 CHAPTER 3 SYNCHRONIZING SCHEME FOR BUCK CONVERTE R 3.1 Basic Buck Converter A b uck converter prod uces an output whose voltage is less than the input. Figure 3.1 shows the basic topology of the buck converter. The converter can be divided into three basic components : bridge, f ilte r, and control loop with associated sensor The bridge output is a switch ing signal ( XV ) with a duty cycle D. The switching signal is given to the filter which then produces a dc signal ( outV ) whose average value is proportional to the duty cycle (D) of the switching signal. A sense circu it monitors the output signal ( outV ) and controls the duty cycle through the control loop. Vin L S1S2C R Vout+ Bridge Filter Vx Control Loop Sense Figure 3 1. Basic buck converter topology Two of the most commonly used control loops are the pulse width modulation (PWM) loop and the hyst eretic loop. The PWM loop has a response time of about 10 cycles whereas the hysteretic controlled l oop can achieve a faster response of 2 3 cycles and is inherently st able [1]. s f

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28 The hysteretic loop was chosen as a control loop in our design due to its sta bility and speed The h ysteretic controlled dc -dc switch -mo de converter is suitable for high frequency operation; enabling reduction in capacitor and inductor sizes by several orders of magnitude. The reduction in passive component size can potentially lea d to ful ly integrated ne ar load power delivery solution s for high performance systems such as multi -core processing platforms. The fast response time is particularly beneficial f or high performance m i croprocessors requiring fast entry and exit strategies f rom multiple supply domains. One of the drawbacks of the hysteretic control loop is the dependence of its switching frequency on conversion ratio or duty cycle (D) The switching frequency ( fs) can be written as Equation 3 1. f S sD D f ) 1 ( 2 (3 1) where D is the duty cycle, is the sensing delay and is the fixed delay of the loop. Thus, the converter exhibits a parabolic de pendence of switch ing frequency on duty cycle as seen from Equation 3.1 [20]. As the free running switching f re quency change s with conversion voltage it may cause the frequency to fall in unde sired power supply resonance bands created by parasitic package inductance interconnects and on-die decoupling capacitances. Thus, fixing the switching frequency to a known reference frequency is desired. Fig 3 2A shows t he basic topology of the hys teretic loop It consists of a hysteretic controller bridge network, low pass LC filter and a sense network. The hysteretic controller consists of a hysteretic comparator which produces a switching signal whose duty cycle depends on the feedback signal provided by the sense network. Fig 3 2B shows the modified controller. In order to control the switching frequency, a delay line is inserted in the loop which compensates for chang e in duty cycle by changing the delay of the loop The delay line is s f

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29 controlled by a PLL based loop which locks the switching frequency to the reference ( FREF). A digital phase lock loop ( D P L L) is used in our design for synchronization of the hysteretic sw itch mode buck dc -dc co n verters The DPLL has parameters which are programmable which helps in adjusting the stability of the loop. L IN Sense Hysteretic Controller VREFVFB Bridge Filter C R Hysteretic Controller VREFVFB L IN Sense Bridge Filter C R Delay line PD Loop filter 1/N FREF Figure 3 2. Hysteretic loop based dc -dc converter. A) Basic topology. B) Modified topology. 3.2 Synchronization Sc heme for DC -DC Buck Converter U sing DPLL 3.2 .1 Architecture of DC -DC Buck C onverter with DPLL Figure 3 3 shows t he proposed DPLL synchronized hysteretic controlled dc -dc buck converter There are two feedback loops in the design: a loop from the voltage re ference ( REFV ) B A

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30 to the dc output ( OUTV ) and a phase feedback loop which synchronizes the hysteretic converter output (HYS ) to the off -chip clock reference (REF ) The voltage feedback loop has a bridge followed by a n LC low pas s filter. A high pass F FC R circuit senses the output and controls the duty cycle of the switching signal through a hysteretic comparator. The control loop of the dc dc converter can be viewed as a freerunning oscil lator with swit ching frequency s The oscillation frequency is given in Equation 3 2 [21 ]. s = f RCD D ) 1 ( 2 (3 2 ) The oscillation frequency depends on the duty cycle (D), the time constant ( RC ) and the overall loop delay ( f ). Because D sets the conversion range, and RC affects both the load response ( via the high pass feedback network RFCF) and the ripple voltage ( via the hysteretic window VH ), it is desirable to synchronize the oscillating frequency by changing the loop delay. A1 + VFB VREFRH0 RD CFRF L VIN VX VSENSE ILOADCDIEVOUT 8 REF 1/N early /late SERIAL INTERFACE DIGITALLY CONTROLLED DELAY LINE DATA R 2R Ladder RH2RH1 1/M PD DIGITAL LOOP FILTER Hysteretic Comparator A1 + VFB VREFRH0 RD CFRF VIN VX VSENSE ILOADCDIEVOUT ILOADCDIEVOUT 1/N early /late SERIAL INTERFACEDigital Controlled Delay Line CLK R 2R Ladder RH2RH1 1/M PFD Digital Loop Filter 1 DPLL Fig ure 3 3 Digital phase locked loop s ynchronized hysteretic controlled buck converter HYS

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31 In order to digitally adjust the control loop delay, which sets the oscillating frequency, a digitally controlled delay line (DCDL) is inserted in the controller feedback path (Figure 3 3 ). The frequency at the output of the hysteretic comparator is divided down and compared a gainst an external reference clock ( REF ) using a bang -bang phase and frequency detector (PFD). The resulting early/late informa tion is filtered using a propor tional -integral digital loop filter. The output bits of the loop filter are fed to a first order s igma delta modulator and a decoder which in turn control the DCDL. The sigma -delta modulator enhance s the delay resolution of the DCDL. A serial interface is used to program DPLL parameters such as the prop ortional and integral gains and the divide ratio The dc -dc converter low/high side buffer sizes, and the feedback network values, specifically RF of RFCF time constant, are also programmable. 3.2 2 Digital Phase Locked Loop (DPLL) Figure 3 4 shows a block diagram of the DPLL. The bang-bang PFD compares the arrival times of the reference clock (REF) and the divided down output of the hysteretic controller. The PFD generates the early/late signals for the digital loop filter The loop filter has controllable gains on the integral and proportional paths. T hese gains are controlled th rough t he serial interface. The ratio of the gains is the key to stabilizing the loop. A sele c tor (SEL) at the output of the loop filter selects 11 bits out of the 19 bits available (i.e. [10:0], [11:1], ). Out of these 11 bits 3 bits are used by the sigma delta to generate a bit -stream that co n trols one of the fine delay cells in the DCDL. The 8 remaining bits at the output of the selector along with the sigma delta output form a 9 -bit control word (A <8:0> ). A <0> represents the bit -stream of the first order sigma -delta. Two 3 to 8 decoders are used to control the coarse d e lay line The first 6 MSB s of the control word (A<8:3>) are given to the two 3 to 8 decoders and the three LSB s of the control word control the fine delay cells. Programmable dividers generate the nece s sary clocks for the PFD, sigma -delta, digital loop filter and the selector (SEL). The sigma delta is

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32 clocked at a progra m mable divide -by-M ratio, whereas the loop filter and PFD operate at a divide -byNxM rati o locked to the reference clock frequency. With the exce p tion of the PFD and DCDL, automatic synthesis and place and route tools were employed to implement the DPLL. From Hysteretic Comparator 421REF PFDBit SelectDCDL19 3BIT_SEL DIV_SEL 1/N To Drivers 1/M Decoder Loop Filter 11 8 Fig ure 3 4 Digital phase locked l oop 3.2 .2.1 Phase frequency detector A phase detector is a circuit that delivers an output signal that is proportional to the phase difference between the reference and the feedback signal. Th ere are many phase detectors that can be used depending upon the application. Simple phase detectors, such as XOR gat e and J -K flip flop can track phase error over only a small range. Also, when the system starts and is initially out of lock ( the frequency difference between the reference signal and the feedback is large) the se phase detectors can only operate over a li mited range of frequencies thus their ability to lock is limited. A Phase Frequency Detector (PFD) Figure 3 5 is less susceptible to the problems mentioned above. If the REF signal is leading the FBK signal at the rising edge of the REF signal, U (the u p indicator) becomes 1. When the FBK signal ris es D (the down indicator) becomes 1 and the following flip flop samples the U signal to make the e/l signal 1. Now that bot h U and D are 1, the NAND will reset the flip -flop s making U and D 0 If th e

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33 REF signal is lagging the feedback signal FBK at the rising edge of FBK D=1 and the following flip flop will sample U=0 making e/l =0. Now the REF signal will rise making the NAND gate reset the two flip flops and correspondingly, making U and D 0 D uring the acquisition phase, the e/l signal remains as a or W hen lock ed, e/l constantly switches between 1 and 0 For proper operation, t he U and D signals should be wide enough to drive the D flip flop. D Q R D Q R D Q R e/l REF FBK U D Fig ure 3 5 Phase frequency d et ector 3.2 .2.2 Digital loop filter A proportional integral (PI) filter ( Figure 3 6 ) is used in the design. The integral path of the filter is an accumulator with adjustable gain, and the proportional path is a feed -forward path with adjustable gains. A 19 -b it accumulator is used in the design. A 2 bit integral gain and a 3 bit proportional gain control are pro vided to set the stability of the loop. The PI filter can be thought of as a simple first order RC low pass filter, analogous to that of a c harge p ump PLL. The resistor in the c harge p ump PLL adds a zero which stabilizes the system. Similarly the p roportional part in the PI filter adds a feed -forward zero which stabilizes the DPLL loop. Varying these gain s allows the designer to control the position of the zero and provides greater control over the loop stability. Keeping the proportional path gain (KP) higher than the integral

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34 path gain (KI) increases the damping factor of the system and increases the stability of the system [18]. A KP/KI ratio of 3 or higher is used in the design to stabilize the loop. The output of the loop filter is given to a bit selector circuit which selec ts 11 bits out of the 19 coming from the loop filter. The 3 LSB s of the selected 11 bits are passed to the sigma delta modulator an d the remaining 8 bits are sent to the delay line to control the coarse and fine cells. 19 311 Z1 KPKI 2 e/l Filter_Out Fig ure 3 6 Proportional integral f ilter 3.2 .2.3 First o rder sigma d elta A first o rder s igma d elta ( Figure 3 7 ) is used in the design to increase the resolution of the DPLL. The sigma d elta works at a higher frequency and is clocked by a frequency divider whose 3 3COUT D Q D Q bit Fig ure 3 7 First o rder sigma d elta

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35 division factor is eight times lower than that of the dividers used to clock the loop filter. The modulator takes i n 3 bits from the filter and over -samples these bits by a factor of eight, generating a bit -stream which is sent to the DCO. This bit -stream is eight times faster than the normal control word and switches a tri -state in the fine delay line. This effectivel y increases the resolution of the delay line and pushes the phase noise to higher frequencies. The DPLL closed loop response resembles a low pass filter, thus, the high frequency noise is rejected. 3.2 .2.4 Digitally controlled delay line A digital ly -controlled delay line is employed to supply variable delay to the control loop. The delay line is divided into two tuning stages: a coarse tuning stage and a fine tuning stage. The coarse tuning delay chain ( Figure 3 8 ) is made up of 63 delay buffers each of wh ich has a fixed delay of about 40ps. The 6 3 delay cells are divided into eight groups with the first group having seven delay cells and each of the others having eight A two stage tri -state approach is used to control the amount of added delay. To next row To row mux C<0> C<1> C<2> C<3> C<4> C<5> C<6> C<7> From previous row 3:8 A<5:3> To fine line IN R<0> R<4> R<1> R<2> R<3> R<6> R<5> R<7> 3:8 A<8:6> Fig ure 3 8 Coarse t uning s tage

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36 Two decoders generate the required delay from the coarse delay line depending upon the 6 MSBs (A<8:3>) of the control word. A<5:3> selects the number of delay cells from each group and A<6:8> selects the numb er of groups. For exam ple, if A<8:3>=[101011 ], three delay cells from each group are selected and five groups in total are selected; so thirty -four (7 + (3*8) + 3) delay cells contribute to the delay. The output fro m the coarse delay line is passed to the fine delay stage. The fine tuning stage ( Figure 3 9 ) consists of an inverter with three tri -states (1X, 1X, 2X) in parallel. The fine delay stage covers the delay of one coarse delay stage. The tri -state increases the loading on the output when switched OFF increasing the dela y. The bit -stream from the sigma -delta (A<0>) controls the first tri -state with strength 1X. The remaining 2 LSBs (A<1>, A<2>) control the other tri -states with 1X and 2X strength, respectively. 2X 1X 1X 1X From Coarse Delay Line To DriversA<2:0> I/P EN O/P Fig ure 3 9 Fine delay s tage 3. 3 Modeling of DC -DC Buck Co nverter and Analysis as a C PLL 3.3 1 Modeling DC -DC Converter as a VCO The dc dc buck converter is synchronized using a D PLL with a variable delay line. The switching frequency of the dc -dc converter is given by Equation 3 2 Adding a delay line

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37 introduces an extra delay term in the denominator of Equation 3 2 which changes the switching frequency. The switching frequency is now represented by Equation 3 3 s = f RCD D ) 1 ( 2 (3 3 ) Assuming t he converter is in stea dy state operation, the duty cycle D, remains approximately constant and so do the filter and fixed delay values RC and f respectively. Th e only varying term is Under th ese conditions the switching frequency equation is Equation 3 4. s = 11 ) 1 ( 2 F FD D (3 4 ) f RC F (3 5 ) Assuming 1 F since the amount of delay that is added by the delay line ( ) is small compared to the total delay F a Taylor series expansion yields s = 2) 1 ( 2 ) 1 ( 2F FD D D D (3 6 ) Let F FRD D ) 1 ( 2 and cont DLV K where DLK and contV is the gain of the delay line and control voltage respectively 2) 1 ( 2F cont DL FR sV K D D (3 7 ) The excess phase at the output of the dc -dc converter modeled as a VCO and is given by dt V K D D tcont F DL out 2) 1 ( 2 ) ( (3 8 ) The input/output transfer function of the dc dc modeled VCO is given by s K s V svco cont out ) ( ) ( where 2) 1 ( 2F DL vcoK D D K (3 9 )

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38 3.3 2 Analysis of a PLL S ynchronized D C -DC C onverter as a Charge Pump PL L In the previous section the dc -dc converter was modeled as a VCO. Now the overall design can be analyzed as a charge pump PLL A charge pump PLL is chosen for analysis as the RC filter can be easily transformed to a digital (PI) loop filter using the impulse invariant or b iline ar transform [19]. An s -domain model of the charge pump PLL with the dc dc rep resented as the VCO (Figure 3 9) has an open loop transfer functi on given by Equation 3 10 [4]. N s K Cs R I s svco p open in out1 1 2 ) ( ) ( (3 10) sC R 1 2 / Ip s Kvco/ N / 1 refF DCDC e Figure 3 10. An s -domain model of the C PP LL with dc dc converter as a VCO The closed loop transfer function [4 ] for the block diagram is given by N K C I Rs N K I s RCs CN K I s s s Hvco p vco p vco p closed in out 2 2 1 2 ) ( ) ( ) (2 (3 11) The zero, damping factor and natural frequency of oscillation are given by Equations 3 12, 3 13, and 3 14, respectivel y. RC sz1 (3 12) CN K Ivco p n 2 (3 13)

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39 N CK I Rvco p 2 2 (3 14) The closed loop transfer function is given by Equation 3 15. 2 2 22 2 ) (n n n ns s s s H (3 15) From Equation 3 14, it is eviden t that the damping factor of the system can be altered by changing the resistance, capacitance, charge pump current or VCO gain. Figure 3 11 and 3 12 show the bode plot s for the open and closed loop transfer function of the system for different damping fac tor s In the present MATLAB model, t he damping factor is changed by adjusting the resistance of the loop filter I ncreasing the damping factor moves the position of the zero towards the origin (Figure 3 11), which causes the phase margin of the system to i ncrease. In this -100 -50 0 50 100 150 Magnitude (dB) 105 106 107 108 109 1010 -180 -135 -90 Phase (deg) Frequency (rad/sec) =0.099257 =0.29777 =0.49629 =0.6948 =0.89332 =1.0918 =1.2903 Figure 3 11. Bode plot of the open loop transfer function for different damping factor.

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40 simulation, the phase margin changes from 11 degrees for 09 0 to 82 degrees for 29 1 effectively resulting in higher proportional path gain for a Digital PLL (as seen from the transformation equations in [19 ]). The magnitude response of the closed loop transfer function vs. different damping factor s (Figure 3 12) shows peaking at low damping factor values As the damping factor increases the overshoot decreases phase response smoothens and the closed loop bandwidth increases -80 -60 -40 -20 0 20 Magnitude (dB) 106 107 108 109 1010 -180 -135 -90 -45 0 Phase (deg) Frequency (rad/sec) =0.099257 =0.29777 =0.49629 =0.6948 =0.89332 =1.0918 =1.2903 Figure 3 1 2 Bode plot of the closed loop transfer function for different damping factor 3.3 3 Transient Response for Phase and Frequenc y Step The transfer function of the PLL gives a relationship between output phase ( out ) and input phase ( in ). The error transfer function provides another useful relationship that is used to

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41 analyze the transient r esponse of the system for a frequency or phase step. T he phase error ( e ) is the difference between input phase ( in ) and the output phase ( out ). out in e (3 16) in out in e 1 (3 17) So t he error transfer function represented by eHis given by Equation 3 18 2 2 22 ) ( 1 ) (n n es s s s H s H (3 18) 3.3 .3.1 Phase s tep When a phase step ( ) is applied to the system, the error transfer function [3 ] is expressed in Equation 3 19. 2 2 22 ) (n n es s s s s H (3 19) The inverse transfer function of Equation 3 19 gives the phase error (Figure 3 13). The phase 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10-6 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Time (sec) =0.18338 =0.52722 =0.87105 =1.2149 =1.5587 =1.9026 =2.2464 =2.5902 ) ( t e Figure 3 13. Transient response to a phase step for differ ent damping factors

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42 error is normalized to the phase step. Figure 3 13 shows that at t=0, when the phase step is applied, the phase error is maximum, and with time the phase error is reduced, eventually approaching zero. It is also observed that as the dam ping factor increases, the system settles down faster because of a larger phase margin (Figure 3 11). In the VCO model of the buck converter, the gain of the VCO depends on the d uty c ycle (D), and time constants rc and f All of these parameters are associated with the b uck converter. A n analysis of how these parameters affect the stabilit y of the system for a phase s tep is presented in Figures 3 14 and 3 15. Figure 3 14 shows the error response for low value of d amping factor and Figure 3 15 shows the error response for high value of damping factor. The low and high values are set by adjusting the position of the zero. Figure 314 shows the error response of the PLL to a phase step for different values of VCO gain (Kvco) due to changes in D, rc and f As observed, the duty cycle has the most dominant effect on the phase error response. The error response of the loop settles down the fastest for D=0.5. Any value other than D =0.5 will decrease the VCO gain (Kvco) and the damping factor (and thus the stability ) of the loop However, if the loop filter parameters are already set so that the loop is under -damped, even with the optimal value of D=0.5, the system will remain under damped. Figures 3 14B and C show that t he effect s of rc and f are minimal in terms of the loop stability. A decrease in both of these values will increase the gain of VCO, and hence the stability, but only by a cur sory amount. A similar set of behaviors is observed when the damping factor is large (Figure 3 15). The duty cycle has the most effect on the error transient response and rc f have minimal effect on the error transi ent response of the loop. The trend is identical to the low damping factor case but the loop settles much faster.

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43 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10-6 -0.5 0 0.5 1 Time (sec) D=0.2 D=0.3 D=0.4 D=0.5 D=0.6 D=0.7 D=0.8 ) ( t e 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10-6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Time (sec) Trc=8600e-12 Trc=8400e-12 Trc=8200e-12 Trc=8000e-12 Trc=7800e-12 Trc=7600e-12 ) ( t e 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10-6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Time (sec) Tf=50e-12 Tf=150e-12 Tf=250e-12 Tf=350e-12 ) ( t e Figure 3 14. Transient response to a phase step ( 53 0 ). A) Duty cycle B) RC C) C B A

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44 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 x 10-7 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 Time (sec) D=0.2 D=0.3 D=0.4 D=0.5 D=0.6 D=0.7 D=0.8 ) ( t e 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 x 10-7 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 Time (sec) Trc=8600e-12 Trc=8400e-12 Trc=8200e-12 Trc=8000e-12 Trc=7800e-12 Trc=7600e-12 ) ( t e 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 x 10-7 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 Time (sec) Tf=50e-12 Tf=150e-12 Tf=250e-12 Tf=350e-12 ) ( t e Figure 3 15. Transient response to a phase step ( 59 2 ). A) Duty cycle B) RC C) C B A

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45 3.3 .3.2 Frequency s tep When a frequency step ) (t u is applied to the PLL, the phase change ) ( tc is obtained by integrating the frequency step at the reference input. t tc ) ( (3 20) 2) ( s sc (3 21) A frequency step at the referenc e input is equivale ntly a ramp in terms of the phase. Thus, the error transfer function for the frequency step [3 ] is given by Equation 3 -22. 2 2 2 22 ) (n n es s s s s H (3 22) Applying the inverse transform the phase er ror curves are obtained ( Fig ure 3 16). All of the curves start from zero as the initial phas e error is zero (phase error ramp). A s the phase error increases the loop responds and eventually re duces the error to zero. As observed ( Figure 3 16), no peaking exists and the loop settles fastest when the syst em is over damped. 0 0.5 1 1.5 2 2.5 x 10-6 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 Time (sec) =0.18338 =0.52722 =0.87105 =1.2149 =1.5587 =1.9026 =2.2464 =2.5902 nt e ) ( Figure 3 16. Transient response to a frequency step for different damping factor

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46 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10-6 -0.2 0 0.2 0.4 0.6 Time (sec) D=0.2 D=0.3 D=0.4 D=0.5 D=0.6 D=0.7 D=0.8 nt e ) ( 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10-6 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 Time (sec) Trc=8600e-12 Trc=8400e-12 Trc=8200e-12 Trc=8000e-12 Trc=7800e-12 Trc=7600e-12 nt e ) ( 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10-6 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 Time (sec) Tf=50e-12 Tf=150e-12 Tf=250e-12 Tf=350e-12 nt e ) ( Figure 3 17. Transient response to a frequency step ( 53 0 ). A) Duty cycle B) RC C) C B A

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47 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10-6 0 0.05 0.1 0.15 0.2 0.25 Time (sec) D=0.2 D=0.3 D=0.4 D=0.5 D=0.6 D=0.7 D=0.8 nt e ) ( 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10-6 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 Time (sec) Trc=8600e-12 Trc=8400e-12 Trc=8200e-12 Trc=8000e-12 Trc=7800e-12 Trc=7600e-12 nt e ) ( 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10-6 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 Time (sec) Tf=50e-12 Tf=150e-12 Tf=250e-12 Tf=350e-12 nt e ) ( Figure 3 18. Transient response to a frequency step ( 59 2 ). A) Duty cycle. B) RC C) C B A

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48 Figures 3 17 and 3 18 show how the VCO parameters such as the duty cycle (D), rc and f respond to a frequency step. The curves in Figure 3 17 corresponds to the under -damped case and Figure 3 18 corresponds to the over -damped case. As with the phase step, the effect of duty cycle is dominant on the response for a frequency step. The loop settles down fastest to a frequency step when D=0.5. Any value other than D=0.5 will decrease the VCO gain (Kvco), decrease the damping factor, and result in slower settling time. The effect of rc and f on the settling time of the loop resembles the phase step. The decrease in both these values increases the gain of VCO and improves the stability. Thus, we can conclude that for a buck converter acting as a VCO, the buck converter p arameters of VCO gain do not affect the settling time as much as the position of the zero as set by the loop filter parameters. 3. 4 Experimental Results A single integrated buck dc -dc converter with hysteretic control loop and DPLL based synchronizat ion was fabricated in a standard 130nm digital CMOS process. Fig ure 3 19 shows t he die phot o The DPLL without the DCDL mea s ures 3 20m by 200m. The converter is operational from 90MHz to 300MHz and occupies approximately 0.34mm2, which includes the DCDL and a 0.7nF input decoupling capacitor. Figure 3 19. Die of dc -dc with DPLL

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49 3.4 1 Frequency Synchronization Test In order to evaluate the performance of the DPLL synchron i zation scheme, the converter output voltage was varied and the output frequency was measured (Fig ure 3 -20). When the DPLL is disabled, the free running switching fr e quency exhibits a parabolic dependence on output voltage for a fixed input voltage (VIN) of 1.2V. To test the DPLL, we set the divide ratio to 128 and var ied the reference f requency from approximately 703 KHz to 1.875MHz in 30MHz/128 increments. The corresponding measurements show that the output switching frequency is locked to the input reference over a wide switching frequency range of 90MHz to 240MHz. The output voltage range over which the DPLL locks is bounded by the free -running switching frequency of the converter. Thus the output voltage range decreases as the fr e quency is increased. 0 50 100 150 200 250 300 350 0.2 0.4 0.6 0.8 1 1.2 Output voltage (V)Frequency (MHz) without PLL 1.875MHz 1.64MHz 1.40MHz 1.17MHz 938KHz 703KHz Figure 3 20. Converter switching frequency vs output voltage 3.4 2 Jitter Measurement The jitter histogram of the divided down clock (VDIV) and the multiplied clock or bridge output signal (VX) are shown in Figure s 3 2 1 A and B r e spectively. The RMS and peak -to -peak jitter s of the bridge output are 42.5ps and 244ps, respectively. The jitter of the bridge output is

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50 worse because of the fact that the noise introduced by the drivers and the bridge is outside the feedback l oop. Figure 3 21. Jitter histogram A) D ivided c lock B) DC DC b ridge output B A

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51 CHAPTER 4 MIXED SIGNAL SIMULAT ION ENVIRONMENT 4 .1 Mixed Signal Design Flow Over the past few decades, designs have grown very large and complex. Many designs incorporate both analog and digital circuitry. Analog and digital circuits are designed at different levels of abstraction. Digital designs can be implemented at transistor level or higher level s of abstraction and later synthesized to gate level models. Analog circuits, for ages, have been designed at transistor level. As designs grow larger, checking for func tionality of a system at the transistor level becomes very difficult due to the higher probability of functional failures and interface problems because of a lack of complete testability A methodology to check for interface and functionality errors using Cadence mixed signal design tools is presented in this section. Figure 4 1 shows a high level design flow for mixed signal designs. There are three phases in the design flow. In the first phase, digital and analog model s of the designs are made separately The digital section of the design is modeled using V erilog or VHDL and the same model can be later synthesized to a gate level net -list and final layout. Analog blocks can also be modeled using V erilog -A, but this model cannot be synthesized. In the init ial phase, the behavioral model of the analog and digital blocks can be used to decide on the architecture, check for functionality, and decide upon interface connections In the next phase, the V erilog -A model of the analog portion is replaced with a tran sistor level schematic and the entire model is simulated again. The results obtained from this simulation should be similar to those obtained from the initial behavioral model simulation. This simulation is slower than the initial phase simulation but is f aster than the transistor level simulation of the entire design. After this, a final transistor level simulation is conducted to verify the actual functionality. This phase is very time

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52 consuming a nd the simulations can take hours. The second step of the d esign phase, though slower than a behavioral model simulation, provides a reasonable tradeoff between accuracy and simulation time. It is a much better indicator of the functionality when compared to the initial behavioral model but still maintains a reas onably short simulation time because the V erilog model is still u sed for the digital portion. For this digital component, the actual synthesizable code has a high probability of matching final transis tor level performance within an appropriate amount of er ror. Specification Behavioral Level Simulation Analog Veriloga Digital Verilog Architecture, Functional and Interface Verification Simulator : SpectreVerilog Mixed Mode Simulation Analog Transistors Digital Verilog Functional and Interface Verification Simulator : SpectreVerilog Transistor Level Simulation Analog Transistors Digital Transistors Functional and Interface Verification Simulator : Spectre Tape Out Figure 4 1. High level simulation flow Cadence provides a number of simulators to carry out the simulations at each phase of the design. Table 4 1 show s the different simulators used in each phase The d igital model is coded in V erilog and its fun ctionality is checked by making test fixtures and simulating it using V erilog -XL. Analog models are coded in V erilog -A and simulated in SpectreS to check for functionality. Next, the mixed signal model with a V erilog digital block and a V erilog -A analog

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53 bl ock is made and simulated in SpectreVerilog to verify functionality and interface the entire design. The same SpectreVerilog setup is used later in the design flow, when the analog block is replaced by transistor level schematic, to verify functionality. T his replacement of models is done through the hierarchical editor, in which you can specify what model is to be used for a particular block. Table 4 1 Simulator s in c adence for different m odels Language/Model Simulator Verilog (Digital Model) Verilog XL Verilog A (Analog Model) SpectreS Gate Level or Transistor Level Model Spectre Mixed Signal Model ( Verilog, Verilog A, Transistor) SpectreVerilog, Hierarchical Editor 4 .2 Mixed Signal Simulation Environment Mixed signal simulations are performed when analog and digital blocks are to be simulated together. The analog block is either a V erilog -A model or a transistor level model. The digital block is a V erilog view. After each block is individually tested, their symbols are made and a new schematic with analog and digital blocks is created (Figure 4 2). After all the desired inputs are set in the mixed signal view, the hierarchical editor is invoked (Figure 4 3). The hierarchical editor shows the level of abstraction of each block found in the schematic. Functional views represent a Verilog coded digital block. Schematic and Spectre views represent analog blocks and input sources respectively. The designer can choose which view to use for a particular block by changing a setting in the view to use colum n. Once the schematic and the hierarchical editor are set, the design partitions are checked to verify whether the analog and digital blocks have been interpreted correctly. Figure 4 2 shows color coded partitions. In addition, the tool automatically intr oduces A/D and D/A converters at the analog/digital interface. The interface parameters are set by the designer before the simulation setup is complete. Once this is complete, the simulation is run using SpectreVerilog.

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54 Digital Block Analog Block A/D and D/A Interface Figure 4 2. Analog, digital blocks in mixed signal simulation environment Digital View View to Use Sources Analog View Figure 4 3. Hierarchical editor window

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55 4 .3 Digital Modeling and Synthesis Flow During the mixed signal simulation flow, developing a digital model that is synthesizable is very important. The digital model ca n eith er be written in VHDL or V erilog. After the digital model has been coded and tested, both individually and with the analog block, the model has to be synthesized. Figure 4 4 shows the various steps in the digital synthesis flow. Specification Analog/Digital partition Analog DesignDigital AnalogRTL Coding & Simulation Logic Synthesis Physical Implementation RC Extraction Delay Calculation Pre Layout Simulation Post Layout Simulation Test Bench DRC/LVS Tape Out Standard Cell Design Library Characterization Abstract Generation Figure 4 4. Digital synth esis flow To carry out synthesis, a characterized standard cell library with timing, area, and power information (Signal Storm) is needed. This information is used by the synthesis tool (Design Compiler) to convert the VHDL/ V erilog code to a gate level net list. The generated gate level net list is tested for functionality before going for physical implementation. The physical implementation is carried out using a place and route tool (Encounter). In addition to the timing,

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56 area, and power information, the place and route (P&R) tool requires the metal and via information of each cell. This information is provided by a Library Exchange Format (LEF) file generated by a tool named A bstract G enerator. After P&R is complete, the layout of the design is generated. To check for functionality after P&R, RC extraction of the layout is done and the net list is subjected to the same set of simulations as performed before P&R with a back annotated timing file. After verifying the functionality, DRC and LVS are performed and the chip is taped out. 4 .4 Mixed Signal Simulation of DPLL S ynchronized Buck Converter Mixed signal simulations are performed on the DPLL synchronized dc -dc buck converter. In this simulation of the DPLL, except the delay line, all the components are replaced by the Verilog code and the Analog block is used at the schematic level. Simulations are carried out to analyze the behavior of the DPLL when the proportional path gain is changed and when frequency and phase steps are applied to the design. 4 .4.1 Respo nse of DPLL to Change in Proportional Path Gain In the DPLL, the stability of the loop is determined by the damping factor, which in turn depends on the proportional path gain (Kp). A simulation with different Kp values is carried out to analyze this behavior of the DPLL. Figure 45 shows how the control word settles with a change in proportional path gain (Kp). In the simulation setup, the reference frequency is 12.5 MHz with a division factor of 16. Two simulations with different proportional path gains are carried out. As th e proportional path gain effect the position of the zero in the system, it also affects the stability and the s ettling behavior of the DPLL. Figure 4 5 shows that for higher values of Kp, the damping factor becomes larger and th e system settles faster but the ripple in the control word is higher.

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57 M=2,N=8 K1=0.5,K2=3 M=2,N=8 K1=0.5,K2=7 0 50 100 150 200 250 300 350 400 30 40 50 60 Reference periodsControl Word 0 50 100 150 200 250 300 350 400 30 40 50 60 Control Word M=2,N=8 KI=0.5,KP=3 M=2,N=8 KI=0.5,KP=7 Figure 4 5. Control voltage vs t ime for different values of Kp 4 .4.2 Response of DPLL to a Frequency and Phase Step Figure 4 6A shows the response of the DPLL to a frequency step a t the reference. In the simulation setup, an initial reference frequency of 40 MHz was set and then decreased to 33.33MHz. The division factor is set to 4. The integral path gain was set to 0.5 and the proportional path gain was set to 3. Figure 4 6A shows that the loop first locks to 40 MHz setting the switching frequency to 160 MHz Later the loop locks to 33.33MHz setting the switching frequency to 134MHz. When a frequency step is applied, the control word changes and finally settles to a new value. A similar setup is used for the phase step except that the reference frequency is maintained at 40MHz and a phase s hift of 108 degrees is provided. Figure 4 6B shows how the control word settles when the phase step is applied. Figure 4 6B shows that

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58 when the phase step is applied the loop responds and the control word changes before settling back to its initial value. Frequency step Lock LockDigital Control WordReference Period 0 100 200 400 300 500 60 40 50 30 Phase step Lock Lock Reference PeriodDigital Control Word0 200 100 300 500 400 600 60 55 50 40 45 Figure 4 6. Control voltage vs time. A) Frequency step. B) Phase step. 4 .4.3 Response of DPLL to a Load Step Figure 4 7 shows the r esponse of the DPLL to a load step at the output of the dc dc converter. In the simulation setup, a reference frequency of 45 MHz is set. The division factor is B A

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59 set to 4. The integral path gain was set to 0.5 and the proportional path gain was set to 3. Af ter the system is a current load step of 80 mA is applied at the output. A load step at the output results in a change of duty cycle With the change in duty cycle the switching frequency of the converter will change The delay line in the DPLL compensate s for the change in the duty cycle and again locks the system back to the reference. From the response we can conclude that a load step at the output is similar to a frequency step at the reference under steady state conditions. 0 100 200 300 400 500 40 45 50 55 60 Reference periodsDigital control word Load step Lock Lock Figure 4 7 Control voltage vs time for a load step.

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60 CHAPTER 5 CONCLUSIONS Advances in technology have resulted in smaller devices with faster operation, less area usage and low power dissipation. Unfortunately, smaller device sizes also lead to more gate leakage, issue s with the matching of devices and other related problems. A ll of these non idealities a ffe ct analog circuit performance more than digital circuits. Further more, as technologies scale, device parameters change, this leads to changes in the design of analo g circuits. Thus, new designs must be made each time there is a change in technology ; this leads to a long design cycle, which in turn delay s the release of a product and limits profitability On the other hand, d igital blocks can be easily ported to newe r technologies resulting in smaller cycle times. A shift to digital design seems to be inevitable. This thesis presented an emphasis on d igital implementations of PLL s for dc -dc converter applications. A DPLL based freque ncy locking technique for high fre quency hyste retic controlled dc -dc buck con verters is presented in c hapter 3 The DPLL locks the converter operating frequency to a clock reference eliminating the dependence of switching frequency on output conversion voltage. In addition, an analysis of how the dc dc converter can be modeled as a VCO is presented. The proposed DPLL converter operates over a wide frequency range of 90240MHz and achieves a conversion range of 33% to 80%, or 0.4V to 0.96V. Using a single 8.2nH inductor and a 20nF external decoupling capacitance, the converter achieves a load response of 40ns to a 120mA step and ripple voltage less than 25mV. The dc dc converter was implemented in 130nm 1.2V digital CMOS process and achieves a peak efficiency of 80% at 180MHz for load cur re nt of 200mA. A mixed signal design and simulation approach was discussed in chapter 4 A mixed signal design flow started by modeling the a nalog and d igital blocks and concluded with a final

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61 verification. Various simulators were used for simulation at each stage of the design process and document ed. The dc -dc converter with DPLL was used as an example to explain how the mixed signal simulator can be used. This approach is very useful as it helps in detecting interface errors which are one major reason for failures in large designs. Thus, to make large designs successful modeling circuits and fixing the interfac e in the earliest design phases is essential .

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62 LIST OF REFERENCES [1] P. Hazucha G. Schrom, J. Hahn, B.A. Bloechel, G. Dermer, S. Narendra, D. Gardner, T. Karnik, V. De S. Borkar A 233-MHz 80%87% efficient four -phase DC -DC converter utilizing air -core inductors on package, IEEE J. Solid -State Circuits vol. 40, no. 4, pp 838 845, Apr. 2005. [2] J. Xu, On -die Supply Resonance Suppression Us ing Ban d Limited Active Damping, IEEE Int. Solid -State Circuits Conf. Dig. Tech. Paper s Feb. 2007, pp 286287,603. [3 ] R. E. Best, Phase Locked Loops: Design, Simulation and Applications 5th ed New York NY: McGraw Hill 2003. [4 ] B. Razavi, Design o f Analog CMOS Integrated Circuits New York NY : McGraw Hill 2002. [5 ] A. Hajimiri and T.H. Lee, A General Theory of Phase Noise in Electrical Oscillators, IEEE J. Solid -State Circuits vol. 33, no. 2, pp 179194, Feb 1998. [6 ] R. B. Staszewski, S. Ve mulapalli, P. Vallur, J. Wallberg, P. T. Balsara Time to -digital converter for RF frequency synthesis in 90 nm CM OS," IEEE Symposium on Radio Freque ncy Integrated Circuit (RFIC ). Dig. Tech. Papers Jun. 2005, pp 473476. [7 ] P. Dudek, S. Szczepanski, and J. Hatfield, A high resolution CMOS time to -digital converter utilizing a Vernier delay line," IEEE J. Solid -State Circuits vol. 35, no. 2 pp 240 247, Feb 2000. [8] E. Raisanen -Ruotsalainen, T. Rahkonen, J. Kostamovaara, A low power CMOS time to digital converter, IEEE J. Solid -State Circuits vol. 30, no. 9, pp. 984 990, Sept. 1995. [9] S. Cha, C. Jeong, C. Yoo, A phase locked loop with embedded analog -to -digital converter for digital control, Electronics and Telecommunications Research Institute Journal, vol. 29, no. 4, pp. 463469, Aug. 2007. [10] C. Chung, C Lee An All Digital Phase Locked Loop for High Speed Clock Generatio n, IEEE J. Solid -State Circuits vol. 38, no. 2 pp 347 351 Feb. 2003. [11] T Watanabe, S Yamauchi, An All Digi tal PLL for Frequency Multiplication by 4 to 1 022 With Seven Cycle Lock Time, IEEE J. Solid -State Circuits vol. 38, no. 2, pp 198 204, Feb 2003. [1 2 ] J Dunning, G Garcia, J Lundberg, E Nuckolls, An All -Digital Phase -Locked Loop with 50 Cycle Loc k Time Suitable for High -Performance Microprocessors, IEEE J. Solid -State Circuits vol. 30, no. 4, pp 412 422 Apr. 1995. [1 3 ] J A Tierno, A V. Rylyakov, D J. Friedman A Wide Power Supply Range, Wide Tuning Range, All Static CM OS All Digital PLL in 65nm SOI, IEEE J. Solid -State Circuits vol. 4 3 no. 1 pp 42 51, Jan. 2008.

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63 [1 4 ] V Kratyuk, P Hanumolu, K. Ok, K Mayaram, A digital PLL with a stochastic time to digital converter, IEEE Symposium on VLSI circuits Dig. Tech. Papers Ju n 2006, pp. 3132. [1 5 ] R. B. Staszewski, D Leipold, K Muhammad, P T. Balsara, Digitally Controlled Oscillator (DCO) Based Architecture for RF Frequency Synthesis in a Deep Submicrometer CMOS Process IEEE Transactions on Circuits and Systems II, vol 50, no. 11, pp 815828, Nov 2003. [1 6 ] P Chen, C Chung, C Lee, A Portable Digitally Controlled Oscillator Using Novel Varactors, IEEE Transactions on Circuits and Systems II vol 52, no 5, pp 233237, May 2005. [1 7 ] D Sheng, C Chung, C Lee An Ultra Low Power and Portable Digitally Controlled Oscillator for SOC Applications IEEE Transactions on Circuits and Systems -II, vol. 54, no. 11, pp 954 958, Nov. 2007. [1 8 ] A M. Fahim A Compact, Low Power Low Jitter Digital PLL, IEEE European Solid State Circuits Conf. (ESSCIRC ), Sep. 2003, pp 101104. [1 9 ] V Kratyuk, P Hanumolu, U K. Moon, K Mayaram, A Design Procedure for ALL Digital Phase -locked Loops Based on a Charge -Pump Phase Locked Loop Analogy IEEE Transactions On Circuits And Systems-II, vol. 54, no. 3, pp. 247251, Mar. 2007. [20] P. Li, R. Bashirullah, P. Hazucha, T. Karnik A delay locked loop synchronization scheme for high frequency multiphase hysteretic dc -dc converter IEEE Symposium on VLSI circuits. Dig. Tech. Paper s Ju n. 2007, pp. 26 27. [21] T. Nabeshima T. Sato, S. Yoshida, S. Chiba, K. Onda, Analysis and design considerations of a buck converter wit h a hysteretic PWM controller, IEEE P ower Electronics Specialists Conf. Jun 2004, pp 17111716. [2 2 ] D H. W olaver, Ph ase Locked Loop Circuit Design, Upper Saddle River, NJ: Prentice Hall, 1991. [2 3 ] T Olsson, P Nilsson A Digitally Controlled PLL for SOC Applications IEEE J. Solid -State Circuits vol. 39, no. 5 pp 751 760, May. 2004. [2 4 ] C. T. Wu, W W ang, I C. Wey, A Y. Wu A Scalable DCO De sign for Portable ADPLL Design, IEEE Symposium on Circuits and Systems (ISCAS) May. 2005, pp 5449 5452. [2 5 ] A. Prodic, D. Maksimovic Mixed -signal simulation of digitally controlled switching converters IEEE Workshop on Computers in Power Electronics Jun. 2002, pp. 100 105.

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64 BIOGRAPHICAL SKETCH Deepak Bhatia was born in Hyderabad, India in 1985. He received his B.S.E.E from Padma sri Dr. B.V. Raju Institute of T echnology, Hyderabad, India in 2006; and an M.S.E.E from the University of Florida, Gainesville, Florida in 2008. He was a member of the Integrated Circuit Research lab (ICR) from May 2007 to December 2008 where his focus of research was Digital Phase Locked Loop (DPLL) and Delay Locked Loop design (DDLL) His research interests inc lude low power digital design, phase l ocke d loop design, and delay l o cked l oop design.