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Impact of Mechanical Stress on Silicon and Germanium Metal-Oxide-Semiconductor Devices

Permanent Link: http://ufdc.ufl.edu/UFE0022864/00001

Material Information

Title: Impact of Mechanical Stress on Silicon and Germanium Metal-Oxide-Semiconductor Devices Channel Mobility, Gate Tunneling Currents, Threshold Voltage, and Gate Stack
Physical Description: 1 online resource (106 p.)
Language: english
Creator: Choi, Youn
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2008

Subjects

Subjects / Keywords: germanium, hfsion, leakage, mobility, mos, reliability, silicon, strain, threshold, uniaxial
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation explores impact of uniaxial mechanical stress on metal-oxidesemiconductor devices in terms of channel mobility, gate direct tunneling current, trap-assisted gate tunneling current, threshold voltage, high-k gate dielectric, and metal gate using four point wafer bending setup. Beyond 90 nm technology node, strained Si technology has been a mainstream in VLSI manufacturing technology. Therefore, it is important to properly understand strain effects on not only channel mobility, but also other electrical parameters, such as gate leakage, gate stack, and reliability of MOS devices. Process-induced uniaxial stress has been compared with substrate-induced biaxial tensile stress and its advantages on Si p-MOSFETs have been pointed out. It is shown that the net band splitting from strain and confinement is additive for uniaxial compressive stress but subtractive for biaxial tensile stress. This results in larger hole mobility enhancement under uniaxial compressive stress. Impact of uniaxial mechanical stress on gate direct tunneling current in Si and Ge MOS devices are investigated. Due to different conduction edge of Si and Ge, opposing uniaxial mechanical stress dependence has been observed in gate direct tunneling currents of Si and Ge n-MOSFETs. Based on gate bias-dependent gate direct tunneling current under mechanical stress,Ge conduction band deformation potentials have been extracted and well matched with theoretical calculations. We also measure gate direct tunneling current of Si and Ge p-MOSFETs under mechanical stress using carrier separation technique in order to investigate strain effects on subband structure in p-type inversion layer of Si and Ge. Due to larger strain-induced valence band edge splitting in Ge, the relative change in gate tunneling current in Ge is 3 time larger than that in Si under uniaxial tensile stress. Strain effects on trap-assisted gate tunneling mechanism, including trap-assisted tunneling and Poole-Frenkel emission, are also investigated from both SiO2 and nitrided hafnium silicate (HfSiON) gate dielectric Si MOS capacitors. A decrease in electron and/or hole trap activation energy results in an increase in trap-assisted gate tunneling current with both 110 tensile and compressive stresses. The dielectric constant of HfSiON also increases with mechanical stress, resulting from strain-induced N p band splitting, which reduces band gap of HfSiON.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Youn Choi.
Thesis: Thesis (Ph.D.)--University of Florida, 2008.
Local: Adviser: Thompson, Scott.
Local: Co-adviser: Nishida, Toshikazu.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2009-06-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2008
System ID: UFE0022864:00001

Permanent Link: http://ufdc.ufl.edu/UFE0022864/00001

Material Information

Title: Impact of Mechanical Stress on Silicon and Germanium Metal-Oxide-Semiconductor Devices Channel Mobility, Gate Tunneling Currents, Threshold Voltage, and Gate Stack
Physical Description: 1 online resource (106 p.)
Language: english
Creator: Choi, Youn
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2008

Subjects

Subjects / Keywords: germanium, hfsion, leakage, mobility, mos, reliability, silicon, strain, threshold, uniaxial
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation explores impact of uniaxial mechanical stress on metal-oxidesemiconductor devices in terms of channel mobility, gate direct tunneling current, trap-assisted gate tunneling current, threshold voltage, high-k gate dielectric, and metal gate using four point wafer bending setup. Beyond 90 nm technology node, strained Si technology has been a mainstream in VLSI manufacturing technology. Therefore, it is important to properly understand strain effects on not only channel mobility, but also other electrical parameters, such as gate leakage, gate stack, and reliability of MOS devices. Process-induced uniaxial stress has been compared with substrate-induced biaxial tensile stress and its advantages on Si p-MOSFETs have been pointed out. It is shown that the net band splitting from strain and confinement is additive for uniaxial compressive stress but subtractive for biaxial tensile stress. This results in larger hole mobility enhancement under uniaxial compressive stress. Impact of uniaxial mechanical stress on gate direct tunneling current in Si and Ge MOS devices are investigated. Due to different conduction edge of Si and Ge, opposing uniaxial mechanical stress dependence has been observed in gate direct tunneling currents of Si and Ge n-MOSFETs. Based on gate bias-dependent gate direct tunneling current under mechanical stress,Ge conduction band deformation potentials have been extracted and well matched with theoretical calculations. We also measure gate direct tunneling current of Si and Ge p-MOSFETs under mechanical stress using carrier separation technique in order to investigate strain effects on subband structure in p-type inversion layer of Si and Ge. Due to larger strain-induced valence band edge splitting in Ge, the relative change in gate tunneling current in Ge is 3 time larger than that in Si under uniaxial tensile stress. Strain effects on trap-assisted gate tunneling mechanism, including trap-assisted tunneling and Poole-Frenkel emission, are also investigated from both SiO2 and nitrided hafnium silicate (HfSiON) gate dielectric Si MOS capacitors. A decrease in electron and/or hole trap activation energy results in an increase in trap-assisted gate tunneling current with both 110 tensile and compressive stresses. The dielectric constant of HfSiON also increases with mechanical stress, resulting from strain-induced N p band splitting, which reduces band gap of HfSiON.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Youn Choi.
Thesis: Thesis (Ph.D.)--University of Florida, 2008.
Local: Adviser: Thompson, Scott.
Local: Co-adviser: Nishida, Toshikazu.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2009-06-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2008
System ID: UFE0022864:00001


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1 IMPACT OF MECHANICAL STRESS ON SILICON AND GERMANIUM METAL-OXIDESEMICONDUCTOR DEVICES: CHANNEL MO BILITY, GATE TUNNELING CURRENTS, THRESHOLD VOLTAGE, AND GATE STACK By YOUN SUNG CHOI A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2008

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2 2008 Youn Sung Choi

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3 To my parents in Korea and family, Luke and Jin-Hwa

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4 ACKNOWLEDGMENTS First and foremost I would lik e to thank my advisor, Dr. Scott E. Thompson, for his constant encouragement and expert guidance ove r the past four years. I have learned many things, including how to solve critical problem s from a simple model and logical thinking, from him. I also would like to convey my special thanks to my co-advisor, Dr. Toshikazu Nishida. His consistent advice and technical writing skill have been very valuable in the course of my research. I also would like to express my gr atitude to my committee members (Dr. Arnost Neugroschel, Dr. Jing Guo, and Dr. Franky So) for th eir interest and suggestions on my research. My colleagues in our lab have contributed sign ificantly to my Ph.D. research work through interactive discussions. I would like to thank Dr. Ji-song Lim for his priceless help to publish my first publication, which has been a booster for my research works. Dr. Toshinori Numata, a visiting scholar from Toshiba, also gave me a lo t of insightful ideas and reviewed a couple of my publications. Hyunwoo Park, Uma A ghoram, Min Chu and Andrew Koehler have been with me during my Ph. D. study and given me valuable id eas. I also would like to thank previous group members, Dr. Sagar Suthram and Dr. Guangyu Son, and current members, Dr. Yongke Son, Tony Acosta, Ukjin Roh, Xiaodong Yang, Srivatsan Parthasarathy, Mehmet Baykan and others for their helps. I dedicate this dissertation to my parents and family. I especially thank my father, mother, and younger brother in Korea for th eir endless support and love, whic h have made me what I am now. I also owe my deepest thanks to my wife Jin-Hwa Lee, who has stood by and encouraged me, and my son, Luke Jun-Young C hoi, who has grown up healthily.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................4 LIST OF TABLES................................................................................................................. ..........7 LIST OF FIGURES................................................................................................................ .........8 ABSTRACT....................................................................................................................... ............11 CHAPTER 1 INTRODUCTION..................................................................................................................13 Overview of Strained CMOS Technology.............................................................................13 How to Apply Strain to MOSFETs........................................................................................15 Brief Description of Study..................................................................................................... .19 2 UNIAXIAL-STRESS-INDU CED CHANNEL MOBILI TY ENHANCEMENT..................21 Physics........................................................................................................................ ............21 Strain Enhanced Hole Mobility..............................................................................................26 3 STRAIN EFFECTS ON GATE LEAKAGE CURRENTS OF GERMANIUM (Ge) MOS DEVICES.................................................................................................................... ..32 N-Type Metal-Oxide-Semiconducto r Field Effect Transistors..............................................32 Ge Conduction Band Edge Shift and Splitting................................................................32 Theoretical Model...........................................................................................................34 Experimental Set-Up and Results....................................................................................36 Extraction of Conduction Band Deformation Potentials.................................................40 Summary........................................................................................................................ ..42 P-Type Metal-Oxide-Semiconducto r Field Effect Transistors...............................................43 Experimental Set-Up.......................................................................................................43 Stress Altered Hole Tunneling Currents of Ge and Si p-MOSFETs...............................44 Stress Altered Electron Tunneli ng Currents From Metal Gate.......................................51 Summary........................................................................................................................ ..55 4 IMPACT OF MECHANICAL STRESS ON DIRECT AND TRAP-ASSISTED GATE LEAKAGE CURRENTS IN PTYPE MOS CAPACITORS................................................56 Introduction................................................................................................................... ..........56 Experimental Set-Up............................................................................................................ ..56 Results and Discussions........................................................................................................ ..57 Conclusions.................................................................................................................... .........59

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6 5 STRAIN INDUCED CHANGES IN GATE LEAKAGE CURRENT AND DIELECTRIC CONSTANT OF NITRIDED HF-SILICATE DIELECTRIC SILICON MOS CAPACITORS..............................................................................................................62 Introduction................................................................................................................... ..........62 Experimental Procedures........................................................................................................62 Results and Discussions........................................................................................................ ..63 Conclusions.................................................................................................................... .........67 6 IMPACT OF DIFFERENT GATE STACKS AND CHANNEL MATERIALS ON THRESHOLD VOLTAGE SHIFTS IN PTYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS UNDER MECHANICAL STRESS................................69 Introduction................................................................................................................... ..........69 Threshold Voltage Shift Models.............................................................................................69 Results And Discussion......................................................................................................... .71 Conclusion..................................................................................................................... .........72 7 RELIABILITY OF NITRIDED HAF NIUM SILICATE GATE DIELECTRICS UNDER [110] UNIAXIAL MECHANICA L STRESS: TIME DEPENDENT DIELECTRIC BREAKDOWN..............................................................................................77 Introduction................................................................................................................... ..........77 Experimental Setup............................................................................................................. ....78 Experimental Results........................................................................................................... ...79 Discussion..................................................................................................................... ..........82 Conclusion..................................................................................................................... .........86 8 SUMMARY AND RECOMMENDATIO NS FOR FUTURE WORK..................................88 Summary........................................................................................................................ .........88 Recommendations for Future work........................................................................................89 LIST OF REFERENCES............................................................................................................. ..91 BIOGRAPHICAL SKETCH.......................................................................................................106

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7 LIST OF TABLES Table page 3-1. Dilation (d) and shear (u) deformation potentials extr acted from gate tunneling current of Ge MOS device under tens ile stress along [100] and [110]..............................42 6-1. Deformation potential constant s used in this study [17] and CE andgE of Si and Ge, calculated at 300 MPa of uniaxial tension and compression along [110] direction...................................................................................................................... .......73 6-2. Model-predicted, with m=1.3, contributi ons of band edge shifts, DOS change, and M terms. ( M is estimated from [102])................................................................74 7-1. Measured and estimated reliability issues of thick (> 7 nm) high k Si MOSFET as a function of uniaxial mechanical stress...............................................................................87

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8 LIST OF FIGURES Figure page 1-1. Process architecture for strained Si....................................................................................17 1-2. Uniaxial four point wafe r bending jig: two pairs of cyli ndrical rods are used and a sample is inserted between the pairs..................................................................................18 1-3. Uniaxial wafer bending jig. The displacement (d) is defined as d=di-df..........................18 2-1. Hole constant energy band surfaces fo r the top band obtained from 6 band k p calculations for common t ypes of 1GPa stresses..............................................................23 2-2. Summary of key valence band parameters for top and second band for bulk Si under 500MPa stress.................................................................................................................. ..25 2-3. Conduction valley energy level splitti ng under 500MPa of longitudinal uniaxial tensile stress: bulk and MOSFET inversion layer (1MV/cm). ........................................26 2-4. Valence energy band splitting calculated using 3 different models versus inversion charge density for longitudinal compre ssion and biaxial tension stress. .........................28 2-5. Calculated and experimental data for longitudinal compressive and biaxial tensile stress enhanced mobility vs. stress (Biaxial stress= X+ Y)............................................31 3-1. Conduction-band constant energy ellipsoids are centered at the L point, and the major axis of eight half ellipsoids are along or [111] direction.....................................33 3-2. Schematic band diagrams for direct elect ron tunneling from inversion layer in Ge MOS device..................................................................................................................... ..34 3-3. The [100] tensile stress-altered gate tunneling current for Ge MOS device under different gate biases.......................................................................................................... .38 3-4. The [110] tensile stress-altered gate tunneling current of Ge MOS device under different gate biases.......................................................................................................... .39 3-5. The [110] tensile stress-altered electron ga te tunneling current of Ge and Si devices at inversion charge of 1013/cm2, where 1.2 V and 0.6 V gate biases are applied for Si and Ge MOS devices, respectively[68].............................................................................39 3-6. Schematic band diagrams for [110] tensil e stress effects on elect ron gate tunneling in Si and Ge devices.............................................................................................................. .40 3-7. Change in slopes ( d I I dG G/ )] 0 ( / ) ( [) versus gate voltage with 95% confidence error bars for tensile stress along [100]..............................................................................41

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9 3-8. Change in slopes ( d I I dG G/ )] 0 ( / ) ( [) versus gate voltage with 95% confidence error bars for tensile stress along [110]..............................................................................42 3-9. Carrier separation measurement of p-MO SFET and 4-point wafer bending. The gate tunneling current (IG) can be separated into electrons (IG,electron)and holes (IG,hole) tunneling from gate and substrate, respectively[75]..........................................................44 3-10. Carrier separation measurement of a) Source/drain (IS/D) and substrate tunneling current (ISUB) as a function of gate voltage (VG) for Ge p-MOSFET. b) IS/D and ISUB as a function of VG for Si p-MOSFET...............................................................................47 3-11. Relative change in IS/D of Si and Ge p-MOSFET as a function of stress. Symbols and lines are measured data and modeling, respectively..........................................................48 3-12. Schematic band diagram for the hole ga te tunneling current in a p-MOSFET on a (100) wafer.................................................................................................................... .....48 3-13. Valence band edge splitting of Ge and Si under tensile stress along [110].......................49 3-14. Charge density versus applied stress for the top (E1), bottom (E2), and third subbands (E3) at an inversion charge density of 3.5x1013/cm2 for a) Ge and b) Si, respectively................................................................................................................... .....50 3-15. Relative change in ISUB of Ge p-MOSFET as a function of stress at gate bias of 2.8V........................................................................................................................... .........53 3-16. The VFB shift under uniaxial stress....................................................................................53 3-17. Work-function shifts of TaN, bulk Al a nd bulk Cu as a function of stress[87]. Workfunctions of three different metal increase/ decrease with compressive/tensile stress. Line is the linear fit of extracted data................................................................................54 3-18. Relative changes in gate tunneling current of MOS capac itor with TaN gate as a function of stress. Symbols and lines are m easured data and modeling, respectively.......54 4-1. Relative change of gate leakage currents in MOS devices before constant voltage stress (CVS) and after CVS as a function of applied mechanical stress along [110] direction...................................................................................................................... .......60 4-2. Schematic band diagrams for direct and trap-assisted gate tunneling mechanisms. Key parameters for mechanical stress-alter ed electron gate tunneling currents before and after CVS are summarized in table.............................................................................61 4-3. Schematic of SiO2/(100) Si interface structure including Pb0 and Pb1 centers, showing mechanical stress-induced cha nges in dangling bond angles ( ) and interface trap activation energy (T)........................................................................................................61

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10 5-1. The C-V characteristics at 1MHz of the MOS de vice with Pt and Al gate on nitrided Hf-silicate film. The inset shows current density-voltage (J-V) measurements of both devices........................................................................................................................ ........64 5-2. Poole-Frenkel (ln(J/E) vs E1/2) plot of Pt and Al gate on nitrided Hf-silicate film at 25 oC. Inset in figure shows a schematic band diagram for MOS capacitors with HfSiON dielectric and interlayer and meta l gates (Pt and Al) under negative gate bias........................................................................................................................... ..........64 5-3. Changes in gate leakage current of Si MOS capacitors with HfSiON dielectric as a function of applied stress...................................................................................................66 5-4. Changes in dielectric constant of HfSiON, HfSiOx and HfO2, measured from C-V and PF slope change...........................................................................................................67 6-1. Plots of uniaxial stressed Vth shifts of p-MOSFETs with different gate stacks (poly Si/SiO2 vs TiN/HfO2) and different channels (Ge vs Si). Symbols and lines are experimental data and calcul ated models, respectively.....................................................75 6-2. Plots of Vth shifts of Ge and Si p-MOSFETs with the mobility correction as a function of stress. Symbols and lines are experimental data an d calculated models, respectively. The inset shows the relative changes in mobility of Ge and Si pMOSFETs with TiN/HfO2 gate stack as a function of stress.............................................76 7-1. Current-time curve for 7 nm HfSiON dielectric Si MOS device during CVS..................78 7-2. The tBD distributions and area scaled tBD distributions for different size samples under VG = -5.2 V..............................................................................................................80 7-3. Uniaxial tensile stress effect on tBD distributions a nd area scaled tBD distributions under VG = -5.2 V..............................................................................................................81 7-4. Uniaxial compressive stress effect on tBD distributions and area scaled tBD distributions under VG = -7 V............................................................................................81 7-5. The QBD distributions for samples with two di fferent HfSiON dielectrics thickness (7 and 8 nm) under tensile mechanical stress.........................................................................82 7-6. Interface trap generation under mechanical stress.............................................................85 7-7. Schematic band diagram for key strain-rela ted parameters for reliability issues..............85

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11 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy IMPACT OF MECHANICAL STRESS ON SILICON AND GERMANIUM METAL-OXIDESEMICONDUCTOR DEVICES: CHANNEL MO BILITY, GATE TUNNELING CURRENTS, THRESHOLD VOLTAGE, AND GATE STACK By Youn Sung Choi December 2008 Chair: Scott E. Thompson Cochair: Toshikazu Nishida Major: Electrical and Computer Engineering Our study explores the impact of uniaxial m echanical stress on metal-oxide-semiconductor devices in terms of channel mobility, gate direct tunneling current, trap-assisted gate tunneling current, threshold voltage, high-k gate dielectric, and metal gate using four point wafer bending setup. Beyond 90 nm technology node, strained Si technology has been a mainstream in VLSI manufacturing technology. Theref ore, it is important to prope rly understand strain effects on channel mobility and also other electrical para meters, such as gate l eakage, gate stack, and reliability of MOS devices. Process-induced uniaxial stress has been compar ed with substrate-induced biaxial tensile stress and its advantages on Si p-MOSFETs have been pointed out. The net band splitting from strain and confinement is additive for uniaxia l compressive stress but subtractive for biaxial tensile stress. This results in larger hole mob ility enhancement under uniaxial compressive stress. Impact of uniaxial mechanical stress on gate direct tunneli ng current in Si and Ge MOS devices are investigated. Because of the di fferent conduction edges of Si and Ge, opposing uniaxial mechanical stress dependen ce has been observed in gate di rect tunneling currents of Si and Ge n-MOSFETs. Based on gate bias-depen dent gate direct tunneling current under

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12 mechanical stress, Ge conduction band deformati on potentials have been extracted and agree well with theoretical calc ulations. We also measure gate dire ct tunneling current of Si and Ge pMOSFETs under mechanical stress using carrier separation techni que in order to investigate strain effects on subband structure in p-type inversion layer of Si and Ge. Due to larger straininduced valence band edge splitting in Ge, the relative change in gate tunneling current in Ge is 3 times larger than that in Si under uniaxial tensile stress. Strain effects on trap-assisted gate tunneling mechanism, including trap-assisted tunneling and Poole-Frenkel emission, are also investigated from both SiO2 and nitrided hafnium silicate (HfSiON) gate dielectr ic Si MOS capacitors. A decrease in electron and/or hole trap activation energy results in an in crease in trap-assisted gate tunneling current with both [110] tensile and compressive stresses The dielectric constant of HfSiON also increases with mechanical stress, result ing from strain-induced N p band splitting, which reduces the band gap of HfSiON.

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13 CHAPTER 1 INTRODUCTION 1.1 Overview of Strained CMOS Technology Strain effects on semiconductors such as si licon (Si) and germanium (Ge) have been extensively studied to maintain historical performance improvement. Bardeen and Shockley introduced a deformation potential theory, explaining that the el ectronor hole-phonon interaction causes a static displacement of the at oms, thus resulting in the conduction or valence band energy shifts[1]. Herring et al. and Pikus et al. quantified the c onduction and valence band energy shift as a function of st rain, respectively, based on deformation potential constants, which are important parameters in strained CMOS technology[2, 3]. The origin of strained-Si to improve CMOS de vices can be traced to thin Si layer grown on relaxed SiGe substrates in 1980s[4, 5]. The thin Si layer takes the larger lattice constant of the SiGe and creates biaxial tensile stress. Wafer-b ased substrate strain was experimentally and theoretically studied by a large number of resear chers for two decades[6]. In the 1990s, two other strained-Si activities started based on process-in duced strain. First, hi gh-stress capping layers deposited on MOSFETs were investigated as a technique to introduce st ress into a channel.[7] Second, Gannavaram et al [8] proposed SiGe in the source and drain area for higher boron activation and reduced external resistance. It wa s this embedded SiGe literature that prompted Intel [9] to evaluate the technology, which resulte d in larger than expected device performance enhancement, which, after considerable intern al debate, was later at tributed to uniaxial compressive channel stress[10]. Still, neither biax ial nor uniaxial stress was immediately adopted in CMOS logic technologies for several reasons Biaxial stress suffe rs from defects and performance loss at high vertical electric fields[11]. Process-i nduced stress requires different stress types (tensile and comp ressive for nand p-channel, respectively) to simultaneously

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14 improve both nand p-channel devices. However, inside Intel and in the industry, strain was becoming recognized as offering the best poten tial to enhance perf ormance in sub-100-nm process technologies (si gnificantly larger performance gain than highgates, fully depleted silicon-on-insulator (SOI), or multi-gate devices). The only debate was on the best path to take (biaxial substrate versus uniax ial-process-induced stress)[12]. Careful analysis of the 1990s biaxial and uniaxial st rained-Si experimental data suggested that the industry adopt process-i nduced uniaxial strain. The key obser vations are as follows. First, uniaxial (versus biaxial) stress provides significantly larger hole mobility enhancement at both low strain and high vertical elect ric field due to differences in the warping of the valence band under strain[13]. Large mobility enhancement at lo w strain is important since yield loss via dislocations occurs at high st rain. Second, uniaxial (as compared to biaxial) stress enhanced mobility provides larger drive current improvement for nanoscale short-channel devices. This results since the uniaxial stress-enhanced electron and hole mobility arises mostly from reduced conductivity effective mass (versus reduced scatte ring for biaxial stress), since uniaxial shear stress provides significant valence and some c onduction band warping. La stly, process-induced uniaxial stress causes approximately five times smaller n-channel threshold voltage shift. Since any threshold voltage shift needs to be retarg eted by adjusting channel doping (for industry standard poly-Si gate devices on bulk or partia lly depleted SOI), the larger threshold voltage shift for wafer substrate-induced biaxial tensil e stress causes approximate ly half of the stressenhanced electron mobility to be lost[14]. Rare ly is the stress-induced threshold voltage shift taken into account in the biaxia l tensile-stress mobility data. On the other hand, Ge and strained Ge are currently being investigated as a potential replacement to strained Si[15, 16]. To characte rize strained Ge, accurate deformation potential

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15 constants (d and u) are required to model the strain induc ed energy level shif ts and splitting. Recently, strain altered gate leakage current has been proposed as an accurate method to extract conduction band deformation potential constants and has been applied to Si with the results matching theoretical expectati ons[17, 18]. For Si p-MOSFETs, uni axial tensile stress increases while compressive stress decreases the gate tunneling current[19, 20]. An opposite dependence exists in Si n-MOSFETs[18, 21]. These results can be understood from the strain-altered out-ofplane effective mass, energy spli tting, and carrier repopulation in Si inversion layer[20], which can be used to understand impact of strain on gate tunneling currents of Ge n& p-MOSFETs. Since Ge MOSFETs are usually incorporated w ith high k dielectric a nd metal gate, strain effects on metal/high-k dielectric gate stack, such as strain altered metal gate work function and high-k dielectric constant, can ch ange the electrical parameters, such as the threshold voltage, gate leakage current, gate capacitance and so on. Unlike SiO2 technology, high-k dielectric technology suffers from trap-related problems (i.e. bulk and interface traps) which may result in a degradation of the benefit from strain technology. Even in SiO2 devices, especially in nonvolatile memory (NVM) application, stressinduced leakage current (SILC) has become a ma jor concern for the reliability of the tunneling dielectric, resulting from the ge nerated interface trap due to the repeated high-field stress (Fowler-Nordheim stress)[22, 23]. Th erefore, it is important to understand impact of mechanical stress on trap-assisted gate leakage and dielectric breakdown. 1.2 How to Apply Strain to MOSFETs This section describes two techniques used in commercial 90 and 65 nm logic technologies to introduce uniaxial stress into the Si channel. The techniques in production include high stress

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16 tensile and compressive SiN ca pping layers and selective ep itaxial SiGe deposited in recessed/raised source and drains. The cost to implement process stressors is lo w at less than approxima tely 2-3% due to the comparatively few new process steps. Several process flows exist to introduce the epitaxial SiGe into a MOSFET[24-26]. The first co nsists of the steps shown in Fig. 1-1(a). The source/drains are etched creating a silicon recess. Next, SiGe (for p-channel) or SiC for n-channel is epitaxially grown in the source and drain. First generati on embedded SiGe used ~17% Ge to create ~500MPa of channel stress. Future generations bring the SiGe closer to the channel and will likely increase the Ge concentration[25, 27]. Locati ng the SiGe closer to the channel will require reduced midsection thermal cycles to prevent an y boron or Ge out-diffusi on from the SiGe into the channel. To date a maximum of ~900MPa of stress has been created with embedded SiGe and impressive current improvements from 60-90% have been demonstrated on short devices (~35 nm)[25, 27]. Instead of embedded SiGe, dual stress liners (t ensile and compressive capping layers) [28] are also being widely adopted[29, 30]. The advantag es of a dual stress liner flow over epitaxial SiGe are reduced process complexity and integr ation issues. Recent progress in increasing stress of SiN films to ~3.0GPa for compressive and ~2.0 GPa tensile [31] increases the attractiveness of this option. The capping films are introduced either as a sacrificial layer before source and drain anneal [28, 31, 32] or as a perman ent layer post salicide (Fig. 1-1(b) ). With 2-3GPa stress in the SiN, comparable performance to the first gene ration SiGe has been demonstrated. The process flow consists of a uniform deposition of a high tensile SiN liner post silicidation over the entire wafer followed by patterning and etching the film off p-channel transistors. Generally a thin etch stop layer is used under the liner to prevent any damage to the silicide. With highly selective

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17 etches, the etch stop layer can be < 50A which only slightly degrades the stress transfer into the channel. Next, a highly compressi ve SiN layer is deposited and this film is patterned and etched from n-channel regions. Figure 1-1. Process architecture for strained Si (a) p-channel MOSFET process flow for the representative stacked gate transistor and TEM cross sectional view (source: Chipworks) and (b) dual stress liner with tensile and compressi ve silicon nitride capping layers. In this work, instead of process-induced st ress described above, f our point wafer bending technique has been used to appl y strain to MOS devices. Figure 1-2 and 1-3 show the fixture to simulate uniaxially strained MOSFETs as shown in figure 1-1.

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18 Figure 1-2. Uniaxial four point wafer bending jig: two pairs of cy lindrical rods are used and a sample is inserted between the pairs. Figure 1-3. Uniaxial wafer bending jig. Th e displacement (d) is defined as d=di-df. (a) an unstressed sample (b) a stressed sample.

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19 Such a bending structure has been well studied and a relation between the applied force and stress under uniform stress is given by [33] 3 2 2 2 a L a d t Y Y (1-1) Here, and are the stress and strain values at the center of the sample respectively, Y is Youngs modulus of Si along the stress direction, 2 D L a and the deflection d is the vertical displacement between the uppe r and lower plates of the uniaxial ji g when we apply stress. In Fig. 1.3, d is defined as d = di df, and actually measured by the change in micrometer graduations. The stress calibration of this setup has been don e with both strain gauge and optical curvature measurements. 1.3 Brief Description of Study The main purpose of our study is to understand the strain effects on Si and Ge MOSFET operations: channel mobility, gate tunneling cu rrents (direct and trap-assisted tunneling mechanisms), threshold voltage, high k dielectric constant, and reliabilit y related to dielectric breakdown. The brief explanation of stra in-induced mobility enhancement of Si MOSFETs is given and the physics behind some strained-S i experimental data is explored. The strain effects on direct ga te tunneling currents of Si and Ge MOSFETs are compared and explained. Based on experimental observati ons, qualitative analyses are made for both nand pMOSFETs. Next, deformation potential constants of Ge conduc tion band edge are extracted from the measured gate tunn eling current under mechanical stress.

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20 The impact of mechanical stress on gate l eakage current based on trap-assisted conduction mechanism for Si MOS capacitors is discussed us ing constant voltage stressing and compared with strain-altered dir ect tunneling current. Strain induced changes in gate leakage curren t and dielectric constant of nitirided Hfsilicate dielectric (HfSiON) Si MOS capacitors are explored with qual itative explanations. Strain-induced threshold voltage shift models of different channel materials (Si and Ge) and gate stacks (Poly Si/SiO2 and TiN/HfO2) are discussed with theoretical modeling. Each component of model is analyzed thoroughly in conjunction with its underlying physical mechanism. Impact of mechanical stress on time depende nt dielectric breakdown of HfSiON is also investigated using controlled external app lied mechanical stress and its mechanism is experimentally clarified.

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21 CHAPTER 2 UNIAXIAL-STRESS-INDUCED CHAN NEL MOBILITY ENHANCEMENT 2.1 Physics When deciding on a strained-Si process flow it is first necessary to comprehend the potential magnitude for electron versus hole mo bility enhancement and whether the mobility enhancement results from reduced conductivity effective mass or scattering. Sin ce the valenceband dispersion relationship for semiconductors depends on nearest neighbor atomic spacing, certain stress (in particular sh ear stress) warps the valence bands (although less so for conduction band but some warping for shear stress)[34]. The warping of the valence band provides dramatic changes to the constant-energy surfaces in k space and can lead to large hole mobility enhancement via reduced conductivity mass in the channel direction. Mob ility enhancement via reduced mass (as opposed to reduced scattering) is a key in nanoscale MOSFETs and often not appreciated. Only mobility enhancement from reduced mass (unlike reduced scattering) is maintained at the very short 15-nm channel lengt hs (35-nm gate length) devices currently in production[35, 36]. A strained-Si flow, which is scalable for multiple technology nodes, thus, needs to focus on reducing the hole conductivity mass with the goal of improving the n/p ratio from 2 to 1. Therefore, in this section, we will focus on strain-enhanced hole mobility from reduced conductivity mass. As a star ting point, it is helpful to visual ize the effect of strain on the valence-band constant-energy surfaces in k space for bulk Si. Fig. 2-1 shows the surfaces obtained using six band k p and band parameters in [37]. The st rain-altered surfaces for the top two bands are shown at 1 GPa for the common st resses of interest: l ongitudinal compression on (001)[24, 25, 38, 39] and (110) hybrid wafer orientat ion [39] and biaxial tens ile stress. [40] Note from the constant-energy surfaces in Fig. 2-1, the heavy and light hole bands lose their meaning and we label the bands (first, second, etc.) in th is work. Some important differences in the band

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22 structure under the various stresses at 500 MPa are summarized in Fig. 2-2 for the in-plane and out-of-plane conductivity effective masses and density of states at the band edge. We will refer to Fig. 2-2 in the next section du ring analysis of experimental data. Before covering strain-altered hole mobility calculations, we will briefly cover a qualitative model for strain-enhanced electron mobility since the concepts are similar for electrons and holes. The important concepts to understand are strain-induced energy-level splitting, inversion-layer quantum confinement en ergy-level shifts, average mass change due to repopulation and band warping, two-dimensional (2-D ) density of states, and interband scattering changes due to band splitting. All of these will be discussed in the following sections. A simple qualitative model is now presented to gain insight and to understand the more complex mathematics used elsewhere [11] and later in this work. The electron mobility in bulk strained-Si along <110> direction is determined by occupation and scattering in the 2 and 4 valleys and can be expressed as 24 2424 **/()eff tlnn qnn mm (2-1) where q n and m are the electron charge, concentration, relaxation time, and conductivity mass in the MOSFET channel direction, respectively. Strain improves the mobility by increasing the electron concentration in the 2 valley. The repopulation improves the average in-plane conductivity mass (unstressed: mt = 0 19 m0 versus ml = 0 98 m0) and some further improvement is possible for stresses that warp the conduction valleys and lower mt[34]. Reduced intervalley scattering by the strain-i nduced splitting between 2 and 4 plays some role (enhances long channel mobility) when the splitting becomes comparable or larger than the optical phonon energy. In addition to a low in-plane mass, a high out-of-plane mass for the 2 valley electron is

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23 equally important since carrier motion perpendicular to the SiO2 interface (taken as the z direction in this paper) is quan tized. This quantization in addition to strain alters the position of the energy levels. The quantization leads to ba nds becoming subbands since only discrete wave vectors kz are allowed. Including quantization, the tota l inversion-layer electron energy is given by discrete values of energy ( En) added to the electron energy in the x and ydirections (in the plane of the MOSFET)[41]. Figure 2-1. Hole constant energy band surfaces for the top band obtained from 6 band k p calculations for common types of 1GPa stresses (a) unstressed, (b) biaxial tension, (c) longitudinal compression on (001) wafe r, (d) longitudinal compression on (110) wafer. (Note significant differences in st ress induced band warping altering the effective mass).

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24 y y x x nm k m k 2 22 2 (2-2) Each step in energy is called a subband with En the energy of the bottom of the subband. As an example, self-consistent solution of Schrdinger and Poisson equation for 500 MPa of uniaxial tensile stress and an inve rsion-layer vertical field of 1 MV/cm gives the energy levels, as shown in Fig. 2-3. Since the subband separation is greater than kT nearly all the electrons in most cases occupy the bottom two subbands [ground state n = 0 typically called Eo (from 2) and Eo_ (from 4)]. The ground state energy is significantly lower for the 2 valleys because of the higher quantization mass ( 2 : mz = 0 98 m0 versus 4 : mz = 0 19 m0) which leads to increased splitting between the bottom two subbands and c onfinement and strain splitting being additive (for the common biaxial and un iaxial tensile stress). Note, the strong confinement in an MOSFET shifts the energy levels more than the moderate 500-MPa stress typically used in present-day production logic tec hnologies. Thus, a high out-of-plan e mass in the bottom subband (top subband for holes) is an important requir ement for the strain altered band structure. Lastly, in addition to a low in-plane and hi gh out-of-plane effective mass, a high in-plane mass perpendicular to the channel direction is al so important. The density of states per unit area for the quantized system is y x o y xdk dk m m m ) / ( ) 2 /( 22, which results in the density-of-states mass approximated by y x D DOSm m m 2. Though strain does not signif icantly alter the electron subband density of states, as discussed next, a highD DOSm2 will be shown to be important for maintaining a hole concentration in the top subband.

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25 Figure 2-2. Summary of key vale nce band parameters for top a nd second band for bulk Si under 500MPa stress. The conductivity and density of states effective mass is listed at Gamma point. Uniaxial compression is lo ngitudinal along <110> channel direction. (Note significant differences for in-plane, out-of-plane and density of states masses). Similar to strained enhanced electron mob ility, hole mobility in an inversion layer can qualitatively be described as resulting from occupation and scattering in the top two bands ) /(2 110 2 2 2 110 nd top nd nd nd top top top effp p m p m p q (2-3) However, hole transport is more complicated since strain significantly warps the valence band (as seen in Fig. 2-1) altering both the in and out-of-plane mass and D DOSm2. Further, the mass changes with stress and is not constant in k sp ace. As follows from the previous discussion on strain enhanced electron transport, an advantageo us strain for holes need s to warp the valence band to create both a low in-pla ne and high out-of-plane mass and if possible a large mass in the plane of the MOSFET perpendicular to th e channel direction (creates a large D DOSm2 ). Band calculations and measurements to be discussed next show uniaxial stress warps the valence band

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26 creating most of these features. The strain al tered band structure is ca lculated using 6 band k p, including quantum confinement via a self-consistent soluti on of Schrdinger and Poisson equation[41, 42]. The mobili ty is calculated by a linearization of the Boltzman transport equation. The numerics confirm that the simple qualitative model captures much of the essential physics for understanding the physical mechan isms for mobility enhancement. Figure 2-3. Conduction valley energy level spli tting under 500MPa of longitudinal uniaxial tensile stress: bulk and MO SFET inversion layer (1MV/cm). Note, energy level splitting from inversion layer confinement is larger than strained. 2.2 Strain Enhanced Hole Mobility In a MOSFET, the 2-D surface confinement in the inversion layer also shifts the valence bands and the conduction valleys[11, 43]. Whethe r the confinement-induced shift adds to or reduces (cancels) the strain-induced splitting si mply depends on the magnitude of the out-ofplane masses (valence-band splitting is more co mplicated but this simple model captures the essential physics). Bands or valleys with a light out of plane mass will shift more in energy

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27 relative to bands with a heavy mass (similar to the increasing ground state energy of a quantum well as the particle mass decreases). Hence, when the top most occupied band (or valley) has a lower out-of plane mass compared to the next occupi ed band, the splitting is reduced or lost with surface confinement. Fig. 2-4 pictorially show s the valence-band energy-level shift with confinement for both uniaxial and biaxial stress. Etop represents the top ba nd with large out-ofplane mass for uniaxial stress a nd small for biaxial stress (rel ative to the second band with masses given in Fig. 2-2). Hence, the top band will ha ve a small shift in energy due to confinement for uniaxial stress but large shift for biaxial stress. Esecond represents the second band. As seen in Fig. 2-4, the stress-induced band splitting ( Etop Ebottom) increases for uniaxial stress but decreases for biaxial tensile stress. Thus, although strain favors o ccupation of the top band for both types of stresses, confinement fa vors occupation of the top band for uniaxial compressive stress and the second band for biaxia l tensile stress. The ne t band splitting from strain and confinement is additive for uniaxia l compressive stress but subtractive for biaxial tensile stress. The competing effects of strain and surface confinement on the band splitting is the reason for the loss in mobility enhancement in biaxially strained-silicon p-MOSFETs at high electric fields. The undesirable li ght out of-plane mass created by bi axial tensile stress occurs in other material systems, such as Ge and III-V ma terials, and presents a fundamental problem in using this type of strain in inversion layer MOSFETs (dominant device type due to superior scaling properties). To date, unlike biaxial stress [6], limited data exist for the maximum mobility possible for uniaxial stress. We used a set of scattering parameters that fit the experimental data for hole mobility enhancement under biaxia l tensile stress[11]. The calc ulations include acoustic and optical phonon and surface roughness scattering. This set of scattering parameters shows that the

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28 dominant mechanism responsible fo r biaxial tensile-stress mobility enhancement (at large stress) is reduced optical phonon scattering. Acoustic ph onon scattering is only slightly altered due to the changes in the density of st ates. Surface roughness scattering is slightly changed by stress but uncertainty exists in the literatur e[11, 44, 45] and more work is needed especially for the (110) substrate. The calculations for biaxial stress are consistent with the previous work [11], although in this work, Schrdingers and Poissons equation s are solved self-consistently. The model fit to the biaxial tensile-stress experiment al data is shown in Fig. 2-5. Figure 2-4. Valence energy band splitting calculat ed using 3 different mo dels versus inversion charge density for longitudinal compression and biaxial tension stress. Note all models show the net band splitting from strain and confinement is additive for uniaxial compressive stress but subtractive for biaxial tensile stress. Using the same scattering parameters, mobility enhancement for uniaxial stress on (001) and (110) wafers is calculated, as shown in Fig. 2-5, and compared to uniaxial stress data from from three references[6, 24, 46]. The mobility calc ulations use the full sixband subband structure

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29 and KuboGreenwood linearization of the Boltzmann equation[16] Where data exist (0 to 600 MPa for uniaxial stress), the model shows good agreement. The maximum predicted Si inversion-layer hole mobility enhancement is estimated to be 4 times higher for uniaxial stress on (100) wafer and 2 times higher for biaxial stress on (100 ) wafer and for uniaxial stress on a (110) wafer. The larger maximum mobility enha ncement on a (001) wafer results from the high density of states in the top band, as discussed previously but sc attering differences also play a role. Scattering differences for various substrate or ientations and stresses should be expected as captured in analytical scattering expressions. First for acoustic phonon in th e two dimensional inversion layer, the scattering time ac is expressed as [11, 44, 45, 47] ) ( 12 2 3 2 2 D DOS l B D DOS mn ac acm u T k m b D (2-4) where eV Dac1 3 [48] is the acoustic deformation poten tial constant of the valence band, D DOSm2 is the density-of-state effective mass, is the density, and lu is the longitudinal sound velocity. The constant z z dz bn k w m k mn 0 is the form factor which defines the transition from initial state m to final state n, and mmb 2 represents the effective we ll width for the m-th subband. Since the acoustic phonon energy is very small compared to the subband splitting, the acoustic phonon scattering mainly occurs via intraband sc attering. Thus, stress-induced band splitting only weakly affects the acousti c phonon scattering time[13, 49]. As seen from Eq. 2-4, an increased density-of-states will decrease the acoustic phonon scattering time which is proportional to D DOSm2. For uniaxial stress on a (100) wafer with a high density of states in the top

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30 band, this slight negative effect on mobility (at least for uniaxial stress on (001) wafer) is offset by the high hole density in the t op band having a light conductivity ma ss in the channel direction. Also, a large out-of-plane mass increases the acoustic phonon scat tering time (decreases scattering rate) since it decreases the effective we ll width (important for the high initial mobility on (110) wafer). Second, the optical phonon scattering time op is [13, 45, 47, 49] ] 1 1 1 1 1 [ 2 12 0 2 2 f E k f N f E k f N D b mB p B q op mn D DOS op (2-5) where E is the band splitting energy, cm eV Dop/ 10 5 108 [50] is the optical deformation potential constant of the valence band, f is Fermi-Dirac distribu tion function at energy K 735 is the Debye temperature and meV kB630 is the optical phonon energy[47], and 1 1 01 / exp 1 / exp T T k NB qis the number of phonons from Bose-Einstein statistics. Hole intervalley scattering is not significantly reduced for stress < 1GPa since the band splitting is less than the optical phonon energy (60meV). Band splitting greater than 60meV (stress > 1GPa) is necessary to apprecia bly suppress intervalley phonon scattering. Also, the correlation between the topmost two subbands, mnb under uniaxial stress is smaller due to the higher band splitting (strain and confinement being addi tive) and, therefore, the scattering rate is less than that for biaxially stressed devices. Furthermore with the high out-of-plane mass causing larger subband splitting, th e interband optical phonon scattering rate is less on (110) vs. (001) devices. Third, the surface roughness scattering relaxation time sr [11, 45] can be expressed as d q S m E qD DOS eff sr 2 0 3 2 2 2cos 1 2 1 (2-6)

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31 whereeffEis the transverse effective electric field in the inversion layer and 3 2 2 2 22 / 1 L q L q S is the power spectrum of th e roughness at the interface. L is the correlation length (nm L 6 2 ) and is the average step height (nm 4 0 ). Differences in sr for various stresses and substrates result from changes in the density-of-states a nd location of the inversion layer charge from the SiO2 interface. There is also a fair amount of uncertainly in surf ace roughness scattering particularly on a (110) wafer since the commonl y used universal mobility vs. effective oxide fieldeffEapplies only to the (100) substrate[51, 52] However, one can conclude since the effective well width depends heavily on the out-of-plane effective mass for each subband, the top subband for a (110) devices having a very large ou t-of-plane effective ma ss (see Fig. 2-2), will lead to carriers significantly closer to the interface and gr eater surface roughness scattering. Figure 2-5. Calculated and expe rimental data for longitudinal compressive and biaxial tensile stress enhanced mobility vs. stress (Biaxial stress= X+ Y). Note, the maximum predicted Si inversion layer hole mobility enhancement is estimated to be ~4 times higher for uniaxial stress on (100) wafer and ~2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a (110) wafer.

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32 CHAPTER 3 STRAIN EFFECTS ON GATE LEAKAGE CU RRENTS OF GERMANIUM (Ge) MOS DEVICES 3.1 N-Type Metal-Oxide-Semiconduc tor Field Effect Transistors 3.1.1 Ge Conduction Band Edge Shift and Splitting Strain-induced energy shift a nd splitting alters the gate tunneling current. The Ge conduction band minima are located at the equivalent gamma (L) points[53]. Fig. 3-1 shows the conduction band constant energy ellipsoids around the L point Since the centers of the diagonally opposite half ellipsoi ds are one wave vector apart, the 8 half ellipsoids can be combined into four equivalent full ellipsoids( ] 11 1 [ ], 1 1 1 [ ], 1 11 [ ], 111 [).[54] Due to the major axis along the or [111] direction, uniaxial stress along [100] shifts but does not split the 4 ellipsoids, while splitting occurs for stress along [ 110], as shown in Fig. 3-2(b) and (c)[55]. Fig. 3-2(a) shows a schematic drawing of the direct tunneling process from the sub-bands (E) in the inversion layer for uniaxial tensile stress. The strain-induced shif t of the conduction band edge is given by [2, 56] ) ( )) ( ( ) ( k k Tr Eij u ij d i C (3-1) whered and u are the dilation and shear deformation potential constants of the conduction band, respectively, and i denotes the various valleys. Tr( ij) is the trace of the strain tensor (ij )[57, 58] and kand are a unit vector in reciprocal space and applied stress, respectively. In Fig. 3-2(b), stress along [100] causes a hydrostatic conduction band edge shift (Hydro E ) resulting in an altered HfO2/Ge conduction band offset. Th e hydrostatic strain-induced conduction band edge shift can be expressed in te rms of the deformation potentials [53] and is given by

PAGE 33

33 ) ( ) 3 1 ( ) ( ) (ij u d ij Hydro HydroTr Tr E (3-2) where Hydro is the hydrostatic deformation potential constant. Unlike stre ss along [100], stress along [110] leads to band splitti ng between the (110) plane and ) 10 1 (plane ellipsoids. The band splitting of each conduction ba nd edge is given by [55] 110 44 ) 110 (6 1 ) ( u ShearS E (3-3) 110 44 ) 10 1 (6 1 ) ( u ShearS E (3-4) where <110> is the uniaxial stress along [110] direc tion (positive for tensile stress) and S44 is the elastic compliance constant. A schematic drawing of the [110] stress effect on E is shown in Fig. 3-2(c). Figure 3-1. Conduction-band constant energy ellipsoids are centered at the L point, and the major axis of eight half ellipsoids are along or [111] direction. Out-of-plane effective mass and Eeff are defined along [001] direction.[54, 59] Note half of ellipsoids belong to (110) plane while the rest of ellipsoids belong to ) 10 1 (plane.

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34 Figure 3-2. Schematic band diagra ms for direct electron tunneli ng from inversion layer in Ge MOS device. (a) Conduction band offset between HfO2 and Ge is from reference.[59] (b) Stress along [100] raises energy level resulting from hydrostatic strain-induced energy level shift ( EHydro). (c) Stress along [110] cause s shear strain-induced energy level splitting (ShearE ) between (110) plane valley [) 110 ( ] and ) 10 1 ( ) 110 ( energy level is raised while ) 10 1 ( energy level is lowered. Note EHydro is additive forShearE) 110 ( 3.1.2 Theoretical Model From the change in the stress altered tunneli ng current, the Ge deformation potential can be extracted[18]. The electron di rect tunneling current density (IG) can be expressed in terms of the electron charge density (in) and lifetime (i ) of each energy sub-band in the quantization layer, which are functions of stress, i i i Gn q I ) ( ) ( ) ( (3-5)

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35 where the subscript i denotes each sub-band belonging to the valley of Ge. Above the threshold voltage, most electrons occupy each ground state for the) 110 ( and) 10 1 ( valleys. The relative change of gate tunne ling current due to the applied st ress can be expressed as [18, 60] ) 0 ( ) ( ) 0 ( ) 0 ( ) ( ) 0 ( ) 0 ( ) ( ) 0 ( ) 0 ( ) () 110 ( ) 110 ( ) 10 1 ( ) 10 1 ( ) 110 ( ) 110 ( C B n n A I IG G (3-6) where ) 0 ( / ) 0 ( ) 0 ( / ) 0 ( ) 0 ( / ) 0 ( 1 ) 0 () 110 ( ) 10 1 ( ) 110 ( ) 10 1 ( ) 110 ( ) 10 1 ( n n A ) 0 ( / ) 0 ( ) 0 ( / ) 0 ( ) 0 ( / ) 0 ( ) 0 () 110 ( ) 10 1 ( ) 110 ( ) 10 1 ( ) 110 ( ) 10 1 ( n n n n B ) 0 ( / ) 0 ( ) 0 ( / ) 0 ( ) 0 ( / ) 0 ( ) 0 () 10 1 ( ) 110 ( ) 10 1 ( ) 110 ( ) 10 1 ( ) 110 ( n n n n C The charge density of electrons in the sub-bands is calculated from the self-consistent solution of the Schrdinger and Poisson equa tions[61]. The effective mass a pproximation is used for Ge[54, 62]. For a (100) surface oriented Ge devi ce, the out-of-plane effective mass (*nm ) can be defined as) 2 /( 3t l t lm m m m where lm andtm are the longitudinal and transverse effective masses of the valley, respectively (064 1 m ml and 008 0 m mt )[54]. Once the basic Hamiltonian has been identified, the electron charge density is calculated by summing the contributions of each sub-band in the valley. The electron charge density of each sub-band can be described by [63] )) exp( 1 ln( ) (* 2kT E E gm kT ni F d i (3-7)

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36 where k is the Boltzmann constant, T is room temperature, 300K, EF is the Fermi energy, dm is the density of state electron effective mass in the valley (* dm =0.30m) [59], and Ei and g are the energy level of the ith sub-band and the degeneracy of the valley, respectively. Based on the finite difference method [61], the self consiste nt solution provides the charge density and the corresponding sub-band energy levels. The tunne ling lifetime of the elec tron in each sub-band is approximated by [64] dx x E E m E TC i n i i)] ( /[ 2 ) ( 1* (3-8) where EC(x) is the edge of the conduction band of Ge and T(Ei) is the transmission probability calculated with a modified WKB approximation[63, 64]. An E(k) dispersion proposed by Franz, which is consistent with two ba nds separated by an energy gap (2HfO gE=5.8eV), is used for the Ek dependence of HfO2 [65, 66] and an oxide effective mass, OXm =0.180m is used for this calculation[59]. The validity of the WKB approximation for highk dielectrics has been shown elsewhere[62]. 3.1.3 Experimental Set-Up and Results Four-point bending is used to apply uniaxial stress along the [ 100] and [110] directions on (100) surface oriented Ge MOS samples.[13] Th e Ge MOS devices consist of TiN metal gate on top of 3.0 nm HfO2 gate dielectric on p-well substrate. Large area 10-4 cm2 Ge MOS devices are used to eliminate the fringe l eakage components. The electron ga te tunneling current from the Ge substrate to gate is measured under inversion with positive gate bias and substrate grounded using a Keithley 4200 DC characterization system.

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37 Fig. 3-3 shows the [100] stress -altered electron gate tunneling current for different gate biases. The tunneling currents in crease with applied tensile stre ss. Unlike Si, stress along [100] does not result in any change in the aver age conductivity effective mass via electron repopulationthe inset shows the tunn eling barrier height reduced byHydroE Fig. 3-4 plots the change in the electron gate tunneling current for mechanical stress along [110]. The change in the tunneling current for stress along [110] is slightly smaller than for stress along [100]. It is instructive to compare [110] tensile st ress altered tunneling currents for (100) surface oriented Si and Ge n-MOS devices which is show n in Fig. 3-5. The trend for Si MOS devices can be found in several recent publications al l showing similar results[19, 67]. An opposite stress dependence is observed with an increase in tunneling current for Ge and a decrease for Si. The key difference in the gate tunneling mechan ism between Si and Ge devices is due to the position of conduction band minimum (X for Si and L for Ge)[54]. To understand the difference, strain effects on the conduction sub-band structure of Si and Ge are illustrated in Fig. 36. For Si, due to different out -of-plane effective masses of 2 valley (0.92m0) and4 valley (0.19m0), electron repopulation between these two valleys plays an important role in strain-altered gate leakage cu rrent[18]. The decrease in the gate tunneling current of Si results fr om repopulation into the 2 sub-band with a larger out-of-plane effective mass. In addition, the 2 sub-band shift leads to an increase d barrier height. In Ge, the out-ofplane effective masses of the 8-fold degenerate valleys are the same (0.12m0)[54]. Since) 110 ( and) 10 1 ( have the same out-of-plane effectiv e mass and barrier height (without the applied stress), ) 0 () 10 1 ( is identical to) 0 () 110 ( resulting in A(0) in (6) equal to zero. The

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38 degeneracy of) 110 ( and) 10 1 (also results in ) 0 () 10 1 (n= ) 0 () 110 ( nand B(0) = C(0) in (3-6). Thus for Ge,) 0 ( / ) ( (second and third terms in (3-6)) is the dominant effect which is altered via strain by changes in the HfO2 to Ge barrier height, as s hown in Fig. 3-2(c). At lower gate bias, the relative change of as a function of stress is larger based on (3-8). Therefore, the relative change of stress altered gate leakage current at lower gate bias is larger than at higher gate bias, consistent with the experimental data in Fig. 3-3 and 3-4. Also, we observe, in Fig. 3-5, the increase of the gate leakage current in Ge device is approximately 3 times smaller than the decrease in the Si device. Figure 3-3. The [100] tensile stress-altered ga te tunneling current fo r Ge MOS device under different gate biases. Current is increased due to reduced barrier height resulting from EHydro. The inset represents schematic band di agram of sub-band in inversion with no stress and tensile stress along [100].

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39 Figure 3-4. [110] tensile stress -altered gate t unneling current of Ge MOS device under different gate biases. Current is increased due to reduced barrier height of electrons in ) 110 ( energy level. The inset shows schema tic band diagram with strain-induced sub-band splitting between ) 110 ( and ) 10 1 ( sub-bands. Figure 3-5. The [110] tensile stre ss-altered electron gate tunneling current of Ge and Si devices at inversion charge of 1013/cm2, where 1.2 V and 0.6 V gate biases are applied for Si and Ge MOS devices, respectively.[68] Si data are from reference [19] (measured from n-MOSFETs with N+ poly gate and SiO2 dielectric). Note that strain-altered current is increased in Ge while decreased in Si due to the different position of conduction band minimum (X for Si and L for Ge).[54]

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40 Figure 3-6. Schematic band diagrams for [110] te nsile stress effects on el ectron gate tunneling in (a) Si and (b) Ge devices, respectively. A decrease in t unneling current for Si device is induced by 1) barrier height enhancement of mostly populated 2 and 2) electron repopulation into 2 sub-bands, which has higher out-of-plane effective mass(0.92m0), while only barrier height lowering of (110) contributes to an increase of tunneling current of Ge MOS device. 3.1.4 Extraction of Conduction Band Deformation Potentials In this section, the conduction band deformation potential s of Ge are extracted from the strain-altered gate tunneling current. Since stre ss along [100] only causes aHydro E shift and no shear band splitting on the valley structure, Hydro E can be determined from the data in Fig. 33. To extractHydroand capture the change in the tunneling current under the applied stress in the full range of gate voltages, Fig. 3-7 s hows the change of slope in Fig. 3-3 or d I I dG G/ )] 0 ( / ) ( [ versus applied gate bias. Hydro is used to fit the experimentally measured data[2, 53]. To illustrate the goodness of the model fit, maximum deviation curves are plotted in which Hydro ranges from 1.2 to 1.5 eV. The model fits well with the data ove r the range of gate

PAGE 41

41 bias from 0.5V to 1.1V. The same procedure is employed for stress along [110] to determine the two deformation potentials of d and u. The slope of Fig. 3-4 was extracted and compared with fitting models over the entire gate bias range (0.5~1.1 V) in Fig. 3-8. The obtained values of deformation potential constants (d and u) are compared with hydrosta tic deformation potential constants (Hydro) from stress along [100], based on u d Hydro 3 1 [53]. The best fitting values of d and u in Fig. 3-8 are in good agreement with Hydro in Fig. 3-7. The obtained deformation potentials (3 0 3 4 dandeVu5 0 5 16 ) listed in Table 3-1 are close to the theoretical values by Fischetti et al. (43 4 dand eVu8 16 )[17]. Figure 3-7. Change in slopes ( d I I dG G/ )] 0 ( / ) ( [) versus gate voltage with 95% confidence error bars for tensile stre ss along [100]. Best fits ( and ) for the entire data set occur for Hydro = 1.3 and 1.4 eV. Maximum deviations ( and ) from the data occur for Hydro = 1.2 and 1.5 eV.

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42 Figure 3-8. Change in slopes ( d I I dG G/ )] 0 ( / ) ( [) versus gate voltage with 95% confidence error bars for tensile stre ss along [110]. Best fits (, ) for the entire data set occur for d= -4.2 to -4.4 and u=16.5 to 16.8 eV. Maximum deviations ( and ) from the data set occur for d= -4.1 and -4.5 and u=17.0 and 16.0 eV, respectively. Table 3-1. Dilation (d) and shear (u) deformation potentials extracted from gate tunneling current of Ge MOS device under tensile st ress along [100] and [110]. Comparison is made with previous theoreti cal and experimental result s.[17, 53, 55, 69, 70] All quantities are in eV. 3.1.5 Summary In summary, measurement of the electron gate leakage currents under two different mechanical stress conditions provides a method to extract the Ge conduction band deformation potentials. For uniaxial tensile stress al ong [110] and [100], the change in gate leakage current for Ge is measured to be 3 times smaller than that of Si n-MOS device and opposite in sign. This reverse behavior occurs because tensile st ress for Si causes electron repopulation into 2

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43 increasing the out-of-plane effective mass while in Ge, a reduced tunneling barrier is the dominant mechanism, resulting from the hydros tatic shift of the conduction band edge. Although the hydrostatic shift of Si is larger than that of Ge, its c ontribution to the st rain-altered gate leakage current change in Si is not as critical as in Ge due to the primary role of electron repopulation via shear strain-i nduced band splitting in Si. 3.2 P-type metal-oxide-semiconduc tor field effect transistors 3.2.1 Experimental Set-Up Three different kinds of sample s are used in this work: (1) Ge <110> channel/(100) surface p-MOSFETs with TiN metal gate and 3.0 nm HfO2/interlayer (IL) stacked dielectric fabricated on n-type Ge substrate, (2) Si <110> channel/(100) surface p-MO SFETs with p+ poly-Si gate and 1.3 nm SiO2 fabricated on n-well, and (3) Si MOS cap acitors with TaN gate and 2.5 nm SiO2 fabricated on p-type Si substrate. Conventional carrier separation method is used to measure the elec tron and hole tunneling currents for the Ge and Si p-MO SFETs[71-73]. Fig. 3-9 is a sche matic illustration of carrier separation and 4-point wafer bending. The electron (from the gate) and hole (from the substrate) tunneling currents are measured with source and drain physically tied to ground and the gate negatively biased. Mechanical uniax ial stress is applied longitudinal to the <110> channels of Ge and Si MOSFETs. The hole and electron tunnelin g currents are measured using a Keithley 4200 dc characterization system. Devices with differe nt areas are measured and the current density exhibits no area dependence, which indicates a neg ligible edge tunneling effect[74]. To measure the magnitude of metal gate work-f unction shift under mechanical stress, Si MOS capacitors have been used for C-V measurements with HP 4294 to measure flat band voltage shift (VFB).

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44 Figure 3-9. Carrier sepa ration measurement of p-MOSFET and 4-point wafer bending. The gate tunneling current (IG) can be separated into electrons (IG,electron)and holes (IG,hole) tunneling from gate and substrate, respectively.[75] 3.2.2 Stress Altered Hole Tunneling Cu rrents of Ge and Si p-MOSFETs Fig. 3-10(a) shows the carrier separation for Ge and Fig. 3-10(b) for Si p-MOSFETs. For both type of devices, the gate current, IG, is nearly identical with the source/drain current, IS/D, showing hole tunneling current from inversion layer is the domina nt mechanism consistent with previous studies[64, 76, 77]. In Ge device, IS/D is lower and the portion of ISUB in IG is larger than that in the Si device due to 1) HfO2 dielectric with larger equiva lent oxide thickness and 2) TiN metal electrode with free electrons[73, 77]. Fig. 3-11 shows the relative hole gate tunneli ng current change in Ge and Si p-MOSFET as a function of applied external m echanical stress. Theoretical ca lculation for the stress altered hole tunneling current, based on the self-consistent solution to the Poisson and Schrdingers equation for Si and Ge, are also shown in Fig. 3-11[20]. A si x band kp approximation is used for the calculation of charge density and out-o f-plane effective mass[42]. The hole tunneling probability, based on a WKB approximation,[64, 65] is used to fit the experimental data. The

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45 dominant tunneling mechanism for high-k dielectric can be either trap-a ssisted tunneling (PooleFrenkel (PF) emission) or classical tunneli ng (direct or FN tunne ling), depending on the thickness of dielectric and the quality of the hi gh-k/substrate interface and bulk dielectric[62, 67, 78]. In our samples, we determine the dominant mechanism for gate tunn eling current to be classical tunneling (direct or FN tunneling), base d on two reasons: 1) PF plot is not linear (not shown)[79] and 2) hole tunneling oc curs through thin hi gher band gap interlay er (PF emission is dominant for the device with thick dielectric)[ 67]. The strain altered hole tunneling current for both Ge and Si p-MOSFETs increase with stress and the relative change in Ge is approximately 4 times larger than that in Si. The measured data can be understood from stra in altered out-of-plane effective mass and hole repopulation between th e top two sub-bands (E1 and E2)[80]. Fig. 3-12 shows a schematic drawing of the hole tunneling process from E1 and E2 and the strain induced sub-band energy shift. For both Ge and Si, the strain alte red out-of-plane hole effective masses of E1 and E2 are observed to be fairly constant at the point for stress < ~200 MPa a nd listed in Fig. 3-12(c)[13]. The band splitting at low stress and moderate to high gate bias is set by confinement and with E1 having larger strain altered out-of-plane e ffective mass becomes the top band[80]. Applied tensile stress causes the E1 to E2 band splitting to decrease re sulting in hole repopulation from E1 to E2, as shown in Fig. 3-12(b)[19, 20]. Fo r tensile stress, the hole tunneling current enhancements of both Ge and Si devices result from hole repopulation into E2, which has a smaller tunneling barrier height (1 2 B B ) and out-of-plane effective mass (z E z Em m1 2). Compared to Si, the larger increase in strain altered hole tunneling current of Ge can be explained by larger 1) stress i nduced valence band edge splitting and 2) change in hole tunneling attempt frequency.

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46 The hole repopulation can be quantified fr om the valence band edge splitting ( Ev) as a function of stress[81]. Fig. 3-13 shows the valence band edge splitting in Ge and Si under no confinement, based on EV as follows: [55] ] 110 [ 2 / 1 2 44 2 12 11 2 V) 3 2 ( 3 ) ( 2 1 E S d S S b (3-9) where [110] is the applied longitudinal stress, Sij is the elastic compliance constants and b and d are deformation potentials of valen ce band from Ref. [17]. Note that Ev of Ge is 1.5 times larger than that of Si, caus ing more hole repopulation in Ge. Fig. 3-14 plots the hole charge de nsity in the top three sub-bands (E1, E2, and E3) as a function of stress for a) Ge and b) Si, respectively. Note in this calculation, since the total charge density is approximately constant with applied stress, we use N1+ N2+ N3 = 0, where Ni is hole charge density of each sub-band[20]. Since the 2D density of states of both Si and Ge do not change significantly at low stress (<200MPa)[82], hole repopulation from E1 to E2 mainly results from valence band edge splitting as seen in Fig. 3-13, leading to the larger increase in the hole tunneling of Ge, relative to Si. The inversion-layer hole attempt frequency on gate dielectric barrier is also different for E1 and E2[19]. Due to the larger mass ratio of Ge (E1/E2=0.12/0.05), compared to that of Si (0.26/0.21), the relative change of stress altered hole t unneling attempt frequency in Ge is larger, resulting in a larger increase in hole t unneling current for Ge.

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47 Figure 3-10. Carrier separation m easurement of a) Source/drain (IS/D) and substrate tunneling current (ISUB) as a function of gate voltage (VG) for Ge p-MOSFET. b) IS/D and ISUB as a function of VG for Si p-MOSFET.

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48 Figure 3-11. Relative change in IS/D of Si and Ge p-MOSFET as a function of stress. Symbols and lines are measured data and modeli ng, respectively. The magnitude of hole tunneling current change in Ge is approximately 4 times larger than that in Si. Figure 3-12. Schematic band diagram for the hol e gate tunneling current in a p-MOSFET on a (100) wafer. a) each subband has diffe rent tunneling barrier height. b) E1 and E2 subbands shift under stress results in hole repopulation into E2 sub-band, which has lower tunneling barrier height and smaller out-of-plane effectiv e mass. c) Strain altered outof-plane effective mass for each sub-band is listed in table.

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49 Figure 3-13. Valence band edge splitting of Ge and Si under tensile stress along [110] (not including confinement). Ge has larger valence band edge splitting than Si.

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50 Figure 3-14. Charge density versus applied stress for the top (E1), bottom (E2), and third subbands (E3) at an inversion charge density of 3.5x1013/cm2 for a) Ge and b) Si, respectively. Strain altered out-of-plane effective mass of each sub-band is denoted (e.g., 0.12 m0). Note, due to larger valence band edge splitting of Ge, hole repopulation in Ge is more than in Si.

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51 3.2.3 Stress Altered Electron Tunne ling Currents From Metal Gate The carrier separation techni que also allows the electr on tunneling current via ISUB to be measured which is altered by strain due to a shif t in the band offset between the gate electrode and dielectric [83]. Fig. 3-15 shows th e relative change of ISUB as a function of stress for the Ge channel MOSFET. Due to the decreased TiN gate work-function with stress, ISUB increases, showing that the work-function of metal gate decreases under tensile stress. To quantify the metal work-function shift, VFB, where OX OX MS FBC Q V is measured using capacitance-voltage measurement. Since the permittivity of SiO2, the fixed oxide charge and the interface trapped charge does not change appreciably with app lied stress [84] and the Fermi energy level of the silicon substrate only cha nges up to ~1mV at 200 MP a [85, 86], the metal work-function shift (M ) can be approximated from VFB. Fig. 3-16 shows the C-V characteristics of MOS capacitor with TaN gate and VFB is measured to increases/decreases with compressive/tensile stress. Fig. 3-17 plotsM of the TaN gate as a function of st ress, obtained from Fig. 3-16(b) and compared to the work-function shif ts of bulk metals[87, 88]. The stress altered work-function in TaN gate follows a similar trend as that in bulk metal of Al and Cu. The TaN work-function increases/decreases by approximately 4 mV at compressive/tensile stress of 200 MPa. The relative change in the stre ss altered electron ga te tunneling current from the TaN gate to substrate is measured and plotted in Fig. 3-18[89]. The data is extracted at the gate bias of -1.7 V. The gate tunneling curre nt increases/decreases w ith tensile/compressive stress. An analytical equation based on the electron direct tunneling model is employed to fit experimental data [90, 91].

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52 ] 2 )) ( 2 ( ) ( ) 2 ( 2 exp[ 42 2 / 1 2 / 3 2 / 1 2 2qEd m d m m m d q Jb b (3-10) where d V V ES FB G 2 2 2 2 2 2) ( ) / ( /FB G OX Si A FB G OX Si A FB G SV V d qN V V d qN V V wheredis the oxide th ickness and ) 5 0 (*m m [92] and E is the effective electron mass and the electric field in the SiO2 layer, respectively. Also,m, S and ) ( b is the electron mass in the free space, the substrate bend bending and th e effective barrier height as a function of applied stress, respectively. We used the effective oxide thickness, ) 08 0 (*nm d d instead of the physical thickness due to the su rface roughness or the uncer tainty of electrical measurement for the determination of the oxide thickness[90]. For modeling, ) ( bis estimated with the linear fit of M in Fig.3-17. Our calculation show s good agreement with measured data in Fig. 3-18. The relative change in el ectron tunneling current in creases/decreases up to 1.0% under 200 MPa of tensile/compressive stress, resulting from the decreased/increased metal gate work-function by 4meV.

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53 Figure 3-15. Relative change in ISUB of Ge p-MOSFET as a function of stress at gate bias of 2.8V. Due to decreased work-function of Ti N gate, electron gate tunneling current from TiN gate increases up to ~4% with 100MPa of stress. The inset shows the decreased tunneling barrier he ight via strain by the decreased work-function of TiN gate. Figure 3-16. The VFB shift under uniaxial stress. (a) C-V cu rve of MOS capacitor, measured at 100KHz. VFB is extracted from CFB.[93] (b) VFB shift as a function of tensile and compressive stress. VFB decreases /increases with tension/compression.

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54 Figure 3-17. Work-function shifts of TaN, bulk Al and bulk Cu as a function of stress[87]. Work-functions of three different metal in crease/decrease with compressive/tensile stress. Line is the linear fit of extracted data. Figure 3-18. Relative changes in gate tunneling current of MOS capacitor with TaN gate as a function of stress. Symbols and lines are m easured data and modeling, respectively.

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55 3.2.4 Summary Due to larger 1) stress induced valence band edge splitting a nd 2) change in hole tunneling attempt frequency in inversion-layer of Ge under uniaxial tensile stress, the change in stress altered hole gate tunneling current in Ge is ~4 times larger than that in Si. The work-function of the metal gate is measured to change with st rain and decrease/increase ~20meV for each 1 GPa of uniaxial tensile/compressive stress.

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56 CHAPTER 4 IMPACT OF MECHANICAL STRESS ON DIRECT AND TRAP-ASSISTED GATE LEAKAGE CURRENTS IN PTYPE MOS CAPACITORS 4.1 Introduction State-of-the-art logic devices requires uniaxial stress to enhan ce transistor performance[80, 94]. Uniaxial stress is also being used in nonvol atile memory (NVM) to improve the retention time[95-97]. In NVM, trap-assisted gate tunneling current can be a dominate factor in the retention time[98] and the reliabi lity of the tunneling dielectric [22, 23]. The high electric field during programming (Fowler-Nordheim tunneling) generates electron traps in the SiO2 dielectric or at the SiO2/Si interface, resulting in trap -assisted gate tunneling[98]. It has been reported that mechan ical stress affects trap gene ration in MOS devices [99, 100], but less attention has been paid to mechani cal stress-altered trap-assisted gate tunneling current[67]. In this work, we report for the first time, the effects of uniaxial stress on trapassisted gate tunneling current using controlled applied mechanic al stress and constant voltage stress (CVS). 4.2 Experimental Set-Up Samples used in this work consist of MOS capacitors with TaN metal gate on top of 2.5 nm SiO2 dielectric fabricated on p-type (100) Si surface substrate. Large area 105 m2 devices are used to eliminate the fringe leakage components. The electric damage is created by -4.0 V of gate voltage for 50 seconds[101]. By monitoring the gate leakage cu rrent as a function of time at the fixed gate voltage, the CVS condition is adopte d, where applied gate vo ltage generates traps, but does not cause dielectric breakdown. Due to the generated traps du ring CVS, trap-assisted tunneling becomes a dominant gate leakage mechanism, resulting in an increase in gate leakage current after CVS, compared to one before CVS[ 23]. Next, uniaxial 4-poin t external mechanical stress is apply along [110] dir ection while changes in the gate to substrate electron tunneling

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57 current (negative gate bias) and electron gate tunne ling from substrate to ga te (positive gate bias) are measured[13]. The maximum gate voltage used during the gate leakage measurement (VG = 1.7 V) is limited below the magnitude of the gate voltage in CVS condition (VG = -4 V) to ensure minimal gate oxide damage during this measurement. 4.3 Results and Discussions To understand the effects of uniaxial mechanical stress on gate leakag e current in samples before and after CVS, both ga te and substrate in jections are measur ed under tensile and compressive stresses. Figure 4-1 shows the rela tive change of gate leakage current in samples before (Fig. 4-1(a)) and after CV S (Fig. 4-1(b)) as a function of mechanical stress. The relative changes for gate and substrate injections are extr acted at the gate voltage of -1.7 V and 0.8 V, respectively[89]. In samples before CVS wh ere direct electron t unneling is a dominant mechanism, gate and substrate injections show an opposing dependence on mechanical stress, as shown in Fig. 4-1(a). Under tensile (compressive ) stress, gate injectio n increases (decreases) while substrate injection decreases (increases). For sample after CVS where the dominant leakage current is trap-assisted tunneling current both gate and substrate injection is increased under tensile and compressive stress es, as shown in Fig. 4-1(b). Fi g. 4-1(b) also shows a larger slope for the change in gate a nd substrate injections under compre ssive stress as compared to tensile stress. The effects of mechanical stress on direct a nd trap-assisted gate leakage currents can be understood with Fig. 4.2. Fig. 4. 2(a) illustrates the impact of m echanical stress on direct gate tunneling for gate and substrate in jections. Under gate injection, applied tensile (compressive) stress decreases (increases) the tunneling barrier height of electrons from gate to substrate via TaN gate work function shift, resulting in an in crease (decrease) in ga te leakage current[102].

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58 Under substrate injection, mechanical stress-induced electr on repopulation between 2 and 4 sub-bands in the n-type inversion layer cha nges the out-of-plane effective mass and tunneling barrier height of electrons in sub-bands as previously reported [18, 19, 21, 103]. During CVS for thin SiO2 (< 2.5 nm), energetic electrons injected from gate to the Si substrate breaking dangling bonds in the [111] di rection, normally passivated by hydrogen at Pb0 and Pb1 centers at near the SiO2/(100)Si interface [99]. These a dditional defects increase trap assisted tunneling currents [98, 101]. For trap-assisted gate tunneli ng, the detrapping of the SiO2 electron plays a primary role in gate leakage current [104]. The trap activation energy,T where TRAP OX C TE E determines the detrapping processes as illu strated in Fig. 4-2(b). Here, OX CEand TRAPEare the conduction band edge of SiO2 and trap energy level, respectively, and T is a function of applied mechanical stress ( ) [105]. Uniaxial mechanical stress along [110] direction alters th e structure of Pb0 and Pb1 centers, as illustrated in Fig. 4-3 [99, 106-108]. This aff ects the stability of inte rface traps, resulting in a change in T [108]. In Pb0 center, compressive stress along [110] decreases bond angle 1 and increases the other bond angle 2, due to 1) (100) Si substrate surface structure and 2) dangling bond along [111] direction [99, 106]. For tensile stress along [110], it sh ould have the opposite effect as that for compressive stress. The decrease, ( ) <0, means an increase in repulsive force between the dangling bond and at least one of the three back bonds, resulting in the less stable dangling bond, as described in Fig. 4-3(a) and table [106]. For Pb1 center, the dangling bond with unstrained ( = 45) is known to have minimum en ergy and either positive or negative ( ) makes the dangling bond less stable, as sh own in Fig. 4-3(b) [109]. Therefore, both compressive and tensile stre sses along [110] cause a decrease in the trap activation energy

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59 at Pb0 and Pb1 centers,0 ) ( T[67, 99, 110], resulting in an increase in trap-assisted gate leakage current for both gate and substrate injections, as shown in Fig. 4-1(b). It is reported that a change in SiO2/(100) Si interface trap activ ation energy under compressive stress is larger than one under tensile stress [105, 111, 112], matching with ou r results that the relative change of trap-assisted gate leakage current under compressi ve stress is larger than under tensile stress (observed for both gate and substrat e injections in Fig. 4-1(b)). 4.4 Conclusions Different dependences of gate leakage currents on uniaxial mechanical stress are observed from direct and trap-assisted ga te tunneling currents. The CVS t echnique is used to generate traps at SiO2/(100) Si interface and monito r interface trap-assisted gate leakage current in MOS capacitor with 2.5 nm thin SiO2. Both mechanical tensile and co mpressive stresses along [110] increase trap-assisted gate leakage current vi a the lowering of trap activation energy of Pb0 and Pb1 centers, showing that uniaxial stress along [110] may not be appl icable to improve the gate leakage of logic devices and the retention time of NVM devices when trap -assisted tunneling is a dominant mechanism in gate leakage current.

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60 Figure 4-1. Relative change of gate leakage curre nts in MOS devices (a) be fore constant voltage stress (CVS) and (b) after CVS as a functi on of applied mechanic al stress along [110] direction, respectively.

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61 Figure 4-2. Schematic band diagrams for a) direct and b) trap-a ssisted gate tunneling mechanisms. Key parameters for mechanic al stress-altered el ectron gate tunneling currents before and after CVS are summarized in table. Figure 4-3. Schematic of SiO2/(100) Si interface st ructure including Pb0 and Pb1 centers, showing mechanical stress-induced cha nges in dangling bond angles ( ) and interface trap activation energy (T). 1999 A. Toda et al. 2005

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62 CHAPTER 5 STRAIN INDUCED CHANGES IN GATE LEAKAGE CURRENT AND DIELECTRIC CONSTANT OF NITRIDED HF-SILICATE DI ELECTRIC SILICON MOS CAPACITORS 5.1 Introduction Hafnium silicate has been extensively studied as a gate dielectric material in advanced metal oxide semiconductor field effect transistors (MOSFETs) due to a high crystallization temperature, thermodynamic stability with Si, high permittivity and relatively large band gap (5.68 eV) [113-116]. Nitrogen incorporated Hf-s ilicate (HfSiON) has r eceived attention since HfSiON minimizes interf acial layer formation and reduces bo ron diffusion from the poly-Si gate into the channel [117, 1 18]. Also, recent reports have explaine d additional advantages of nitrided Hf-silicate such as increased dielectric constant and improved reliability [119, 120]. Strained silicon technology has been adopt ed in high-k gate st ack MOSFETs, showing strain can improve mobility similarly for Hf-silicate MOSFETs compared to SiO2 MOSFETs [82]. However, to date, there is no systematic and quantitative result on the strain altered dielectric constant and gate leakage current of HfSiON dielectric film. In this work, we report on the effect of mechanically applied uniaxial st ress on the gate leakage current and dielectric constant of Si MOS capacitors with HfSiON gate dielectric. 5.2 Experimental Procedures The HfSiOx films are deposited directly on p-type (100) pre-cleaned (1% HF solution and DI water rinse) 8 inch Si substrates with a resistivity of 3-25 cm using atomic layer deposition (ALD) at 300oC. The oxidizing agents for TEMAH and Si are O3 and H2O, respectively. HfSiOx film deposition is followed by nitrogen incorp oration by rapid thermal anneal (RTA) at 650 oC in NH3 ambient for 60 s. MOS capacitors with Pt and Al gate electrode were fabricated using RF magnetron sputtering. All of the metals were deposited by Ar plasma assisted RF sputtering at a pressure of 15 mTorr and 150W RF (13.56 MHz) power. For all MOS devices, post metallization

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63 annealing (PMA) was carried ou t in a tube furnace at 400oC in forming gas (10% H2 / 90% N2) ambient for 30 min. Capacitance-voltage (C-V) and current-voltage (J-V) measurements were measured with Agilent E4980A and Keithley 4200, respectively, using external mechanical uniaxial stress along the [110] direction [13]. To extract the frequency-independent device capacitance value and eliminate th e effect of both series and s hunt parasitic resistances, a twofrequency method is adopted [ 121]. The flat band voltage (VFB) is extracted from the C-V measurements [122]. To reduce th e electrical instability from Hf SiON charging [123], a constant gate voltage (-1V) was applied for 160 s befo re J-V measurement. This reduces the J-V instability to less than 0.2% variation. 5.3 Results and Discussions Figure 5-1 shows the C-V (a) and J-V (b) characteristics of Hf-silicate dielectric MOS capacitors. In order to verify the gate tunnel ing conduction mechanism, aluminum (Al) and platinum (Pt) electrodes are used due to their large bulk work function difference (Al 4.1 and Pt 5.8 eV) [124]. The accumulation capacitanc e values are almost identical (~1.2 10-6 F/cm2) resulting in an equivalent oxide thickness of 2.7 nm regardless of the gate electrodes[125]. The nearly identical accumulation ca pacitance and parallel shift of C-V curves for Pt and Al gate electrodes indicates that, regardless of gate ma terial, a sharp interface and minimal interaction between the metal gate and dielectric film are maintained. Due to the difference in the work function of Pt and Al, a difference in VFB and larger leakage current under negative gate bias is observed for the Pt devices. The larger leakage current in Pt devices can be explained by the following: (1) the dominant leakag e current mechanism is hole tunneling from the substrate to gate as opposed to electron tunneling from gate to substrate[126], and 2) a higher built-in oxide field of the Pt device results from a larger work function as illustrated in the inset of Fig. 5-2.

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64 Figure 5-1. The C-V characteristics at 1MHz of the MOS de vice with Pt and Al gate on nitrided Hf-silicate film (a). The inset shows current density-voltage (J-V) measurements of both devices (b). Figure 5-2. Pool e-Frenkel (ln(J/E) vs E1/2) plot of Pt and Al gate on nitrided Hf-silicate film at 25 oC. Inset in figure shows a schematic ba nd diagram for MOS capacitors with HfSiON dielectric and interlayer and metal gate s (Pt and Al) under negative gate bias.

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65 Fig. 5-2 shows the Poole-Frenkel (PF) plot for both metal electrodes with HfSiON gate dielectric. The slope of PF pl ot can be expressed as 0) ( ) / ln( ) ( rq kT q E E J Slope (5-1) where k, T, ) ( rand 0 are the Boltzmann constant, temper ature, high frequency dielectric constant of the insulator under external stress, and vacuum permittivity, respectively. The high frequency dielectric constant without external stress extrac ted from the slope of the PF plot is 4.9. The refractive index, n, given by the square root of the high frequency dielectric constant,[127, 128] is found to be 2.23, showing that the extracted dielectric constant is within the range of refractive indices reported for HfSiON films (1.8~2.4)[129]. The normalized change in strain-altered gate leakage currents for Al and Pt HfSiON MOS capacitor are shown in Fig. 5-3. Regardle ss of electrodes, an increase in normalized leakage current is observed for both tensil e and compressive stresses. Recently, Choi et al suggested that a decrease in trap activation energy results in an increase in trap-assisted gate leakage current under mech anical stress[130]. Based on a decreas e in hole trap activation energy under mechanical stress [131] and a dominant hole tunneling gate leakage mechanism under negative gate bias in high-k dielectric[132], an increase in PF emission-based gate leakage may result from a decrease in hole trap activation energy in high-k dielectric under both tensile and compressive stresses. The measured normalized change in the stra in altered dielectric constant of HfSiON, HfSiOx, and HfO2 are shown in Fig. 5-4. Unlike HfO2 and HfSiOx, the dielectric constant of HfSiON is observed to increase with both tensil e and compressive stresses, as determined using two separate techniques, C-V curve and slope extraction from th e PF plot shown in Fig. 5-2.

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66 We propose that the incorporated nitrogen in Hf-silicate film may be the origin of the strain-induced dielectric c onstant change. The nitrogen incorporation creates a N p band above the valence band edge of HfSiO[119]. The N p band splitting by applied mechanical stress may lead to band gap narrowing of HfSiON, incr easing the electronic transition from the N p band to the conduction band[133, 134]. This band gap narro wing should increase the HfSiON dielectric constant[119]. Figure 5-3. Changes in gate leak age current of Si MOS capacitors with HfSiON dielectric as a function of applied stress.

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67 Figure 5-4. Changes in dielectr ic constant of HfSiON, HfSiOx and HfO2, measured from C-V and PF slope change. To date, there have been no reports on strain altering the dielectric constant of SiON which is commonly used for gate dielectrics in advance logic technologie s. One explanation is that for SiON, nitrogen incorporation into SiO2 primarily occurs at the SiO2/Si interface. XPS measurement results show no obs erved band gap narrowing of SiO2 due to N p band formation near valence band edge of SiO2[135]. Thus, the dielectric consta nt of SiON is not expected to change significantly for mechanical stre ss range (<100 MPa) used in this work. 5.4 Conclusions The impact of four point wafer bending uniaxia l stress on gate leakage and gate dielectric constant of Si MOS capacitor with HfSiON has been studied. A measur ed increase in strainaltered gate leakage is attribut ed to a decrease in hole trap activation energy in HfSiON. An increase in HfSiON dielectric constant is also observed under both tensile and compressive

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68 stresses. Thus, in additional to strain enhanced channel mobility, strained HfSiON may provide a slight additional improvement via an increase in oxide capacitance.

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69 CHAPTER 6 IMPACT OF DIFFERENT GATE STACKS AND CHANNEL MATERIALS ON THRESHOLD VOLTAGE SHIFTS IN P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS UNDER MECHANICAL STRESS 6.1 Introduction Uniaxial strained-Si has been adopted to increase performance in sub-90nm production technologies[24, 31, 80]. Strain -induced threshold voltage, Vth, shift can be a critical issue[136]. However, little attention has been given to Vth shift in uniaxial t echnology[137]. Vth shift in Si pMOSFETs is generally regarded as insignifi cant without any quantit ative explanation[138]. Because scaling has reached fundamental materi al limits for gate stacks and channels, we can now scale with new materials an d/or device architectures. TiN/HfO2 gate stack and strainedGe have been expected to be substitutes for poly Si/SiO2 gate stack and strained-Si because of their smaller gate leakage and higher channel mobility, respectively[139, 140]. Therefore the investigation of strain-altered Vth shift of these devices is time ly and worthy. In this work, uniaxial strain-induced Vth shifts of both Ge and Si p-MOSFETs with TiN/HfO2 gate stacks are explained and compared to poly Si gate stacks. The contribution of st rain-induced mobility change to measured Vth shifts is also considered. 6.2 Threshold Voltage Shift Models The Vth shift for a Si p-MOSFET with a poly Si gate under mechanical stress can be derived from [136, 137]; ) ) ( ) 0 ( ln( ) ) ( ) 0 ( ln( ) 1 ( ) ( ) ( dp dp C C g thm m q kT m N N q kT m E m V (6-1) where) ( gE m, CNanddpmare the change in the band gap wi th stress, the body-coefficient, the effective densities of states (DOS) in the 3-D conduction band and the 2-D hole DOS

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70 effective mass in the predominant sub-band, respec tively. The same derivation can be used for Si and Ge p-MOSFETs with TiN gate, as shown in (6-2) ) ) ( ) 0 ( ln( ) ) ( ) 0 ( ln( ) 1 ( ) ( ) ( ) ( ) ( dp dp C C g C M thm m q kT m N N q kT m E m E V (6-2) where) ( Mand) ( CE are the changes in the gate work -function [102] and channel electron affinity and CE andgEcontribute to the Vth, but with different signs. Here, M is positive/negative under compression/tension[87, 102, 141]. Note that, in (6-2), a TiN gate device has bothCEandgE, while, in (1), a pol y Si gate device has gE only. This is because both the Si channel and the poly Si gate are be ing strained in poly Si gate device[137]. Deformation potential theory is used to express CE andgE as a function of stress. Strain induces the hydrostatic shift a nd shear band splitting of conduc tion band edges, which can be expressed as; [53, 55, 84] ii u ij d i CTr E ) ( (6-3) wheredanduare dilation and shear deformation potential constants, Tr( ij) is the trace of the strain tensor (ij ) and i denotes the various valleys (X for Si and L for Ge). For Si and Ge ,CEandgE are calculated and listed in Table 6-1[17, 55]. Strain-induced changes in DOS -related terms also shift Vth (last two terms in (6-1) and (62)). The change in the effective DOS in the 3-D conduction band is given by2 / 3 2 / 3 *) ( / ) 0 ( ) ( / ) 0 ( C C C Cm m N N.[142] In both Si and Ge, CN-related term is negative, irrespective of the type of stress, because stress along [110] causes ) 0 ( ) (* *C Cm m via band splitting [137]. For low stress and moderate to hi gh gate bias, the predominant sub-band in the hole inversion-layer can be de termined by gate bias since the energy level splitting from

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71 confinement is dominant[80]. Theref ore, applied stress alters ) ( dpm only via valence band warping, resulting in ) ( dpmto increase/decrease with compression/tension[13, 80]. Therefore,dpm-related term is positive/negative with compression/tension. The contribution of CNanddpm-related terms are significant under tension because both of terms are negative, while under compression, the two terms are opposite in sign. Both (6-1) and (6-2) were derived based on equal inversion charge at the threshold condition [136]. To relate these expressions to the measured Vth shift [143], the correction term is needed to account for the change in mob ility in the strained channel and given; ) ) 0 ( ) ( ln( ) ( q kT m Vth (6-4) 6.3 Results And Discussion Strain-induced Vth shifts are calculated and compared with wafer bending data. Fig. 6-1(a) plots Vth shifts of Si p-MOSFETs w ith poly Si and TiN gates, re spectively. Under compression, the Vth shift in TiN gate devices is ~2/3 times of th at in poly Si gate devices, while it is larger than that in poly Si gate de vices under tension. This mainly results from subtractive CE in TiN gate devices, as explained in Sec. 6.2. It is also found that, for poly Si gate devices, the Vth shift under compression is larger than tension, becau se there is larger band gap narrowing from compression and smaller contribution of DOS -related terms[84]. Fig. 6-1(b) plots Vth shifts of Ge and Si p-MOSFETs with TiN gate. Based on the calculation using (6-2), larger Vth shifts for Ge are expected under compression because, relative to Si p-MOSFET, the Ge channel has larger band edge shift terms () ( ) ( g CE m E ). Next, the mobility correction term is c onsidered. Uniaxial stress along [110] causes channel mobility to change significantly rela tive to biaxial strain[ 80]. The contribution of

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72 mobility change to the Vth shift, which has been regarded as insignificant in biaxial strain, may be critical in uni axial strain [136]. Fig. 6-2 plots the strain-induced Vth shift of Ge and Si pMOSFETs with TiN gates with the mobility correction. The inset s hows that the relative change in mobility of Si is slightly larger than that of Ge, which is extracted from measured drain current change [82, 93]. Based on mobility change, we calculate the contribution of mobility change terms, listed in Table 6-2, where model-predicte d contributions of bandedge shift, DOS-related terms, and M are also indicated. As expected, the cont ribution of mobility change to measured Vth shifts is significant and even dominant for Si devices. Note that after the correction, the Vth shift of Ge is slightly larger than th at of Si, resulting in insignificant Vth shifts of both Ge and Si p-MOSFETs with TiN/HfO2 gate stacks. 6.4 Conclusion Both Ge and Si p-MOSFETs with TiN ga tes are observed to have insignificant Vt variation under uniaxial stress. The simple Vth shift model including the mobility correction shows good agreements with the measured data from di fferent types of p-MOSF ETs, demonstrating its universality [144].

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73Table 6-1. Deformation potential cons tants used in this study [17] and CE andgE of Si and Ge, calculated at 300 MPa of uniaxial tension and compression along [110] direction. DEFORMATION POTENTIAL CONSTANTS [EV] STRESS TYPE EC [mV] @300MPA EG [mV] @300MPA TENSION -5.14 -3.48 Si d=1.0,u =9.6 B=-2.33, D=-4.75 au d 3=0.29 COMPRESSION -8.99 -10.6 TENSION -5.52 -1.33 Ge d=-4.3,u =16.5 b=-2.16, d=-6.06 au d 3=-0.83 COMPRESSION -8.68 -13.9

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74Table 6-2. Model-predicted, with m=1.3, c ontributions of band edge shifts, DOS change, and M terms. ( M is estimated from [102]) THEORETICAL VALUE EXPERIMENTAL VALUE VTH FROM BAND EDGE SHIFT VTH FROM DOSRELATED TERMS VTH FROM VTH FROM M STRESS TYPE [mV] @ 100MPA TENSION -0.21 -1.46 -2.45 -1.5 Si COMPRESS ION 1.32 0.13 1.97 1.5 TENSION -1.50 -1.15 -1.79 -1.5 Ge COMPRESS ION 2.12 0.43 1.81 1.5

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75 Figure 6-1. Plots of uniaxial stressed Vth shifts of p-MOSFETs with (a) different gate stacks (poly Si/SiO2 vs TiN/HfO2) and (b) different channels (G e vs Si). Symbols and lines are experimental data and calculated models, respectively. Note here that 0 thVwould mean that the magnitude of Vth (which is negative) is increased by stress. W. Zhao 2004 S. Suthram 2008

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76 Figure 6-2. Plots of Vth shifts of Ge and Si p-MOSFETs with the mobility correction as a function of stress. Symbols and lines are experimental data an d calculated models, respectively. The inset shows the relative changes in mobility of Ge and Si pMOSFETs with TiN/HfO2 gate stack as a function of stress.

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77 CHAPTER 7 RELIABILITY OF NITRIDED HAFNIUM SILICATE GATE DIELECTRICS UNDER [110] UNIAXIAL MECHANICAL ST RESS: TIME DEPENDENT DIELECTRIC BREAKDOWN 7.1 Introduction State-of-the-art CMOS devices requires uniaxial stress to enhance the performance of transistor with high k gate stack[145]. Among th e candidates for high-k dielectrics, nitrided hafnium silicate (HfSiON) is a promising material due to high crystallization temperature and thermodynamic stability with Si[146]. The reliab ility of HfSiON Si MOS device, such as time dependent dielectric breakdown (TDDB), bias temperature instabilit y (BTI) and threshold voltage (VTH) instability, and hot carrier in jection (HCI) also has been extensively studied to help improve device lifetime[147]. It has been reported that applied mechanic al stress changes TDDB and negative bias temperature instability (NBTI) in SiO2 dielectric Si MOS device[ 100, 148-150] but less attention has been focused on impact of applied mechan ical stress on TDDB and NBTI in HfSiON[111, 151]. Furthermore, most of these works have us ed process-induced strain, such as a nitride stressor, which can contain hydroge n and water and introduce ambiguity into the strain effect on device reliability[100, 152-154]. In this work, we report on the effects of both uniaxial tensile and compressive stresses on TDDB in HfSiON Si MOS devices using controlled applie d external mechanical stress. From the mechanical stress dependence and thickness inde pendence, possible degradation mechanisms are identified. Mechanical stress-induced BTI, HCI, and VTH instability of high k MOSFETs are also briefly discussed.

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78 7.2 Experimental Setup Samples used in this work consist of MOS cap acitors with aluminum metal gate on top of 7 and 8 nm HfSiON dielectrics fa bricated on p-type (100) Si substrate[155]. Samples with gate area of 0.000857, 0.0016, 0.0026, and 0.0052 cm2 are used. Constant negative gate voltage stressing is performed with a gate leakage cu rrent compliance limit of 10 pA using a Keithley 4200 DC characterization system. We define the time to breakdown (tBD) as the first sudden increase in the gate leakage current (soft br eakdown), as shown in Figure 7-1[147, 156-158]. The steep increase in the gate leak age current upon onset of breakdow n allows measurement of the breakdown event at a well-defined electric field. A custom built four point wafer bending setup is used to apply external mechanical stress along the [110] direction du ring constant voltage stressing (CVS)[13]. The impact of mech anical stress on th e distribution of tBD and charge to breakdown (QBD) is monitored in the HfSiON MOS capacitor samples. Figure 7-1. Current-time curve for 7 nm Hf SiON dielectric Si MOS device during CVS

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79 7.3 Experimental Results In this section, experimental data on the distributions of tBD and QBD in HfSiON Si MOS capacitors under both mechanical tensile and comp ressive stress is report ed. Figure 7-2(a) shows tBD Weibull plots with different area samples with 7 nm thick HfSiON dielectrics, where an areadependent tBD distribution is observed [159]. When the results are scaled by area as in Figure 2(b), the scaled tBD Weibull curves coincide which indica tes an intrinsic breakdown mechanism. The area scaled tBD is computed based on the following equation. i jA A i jt F t F/)) ( 1 ( 1 ) ( (7-1) wherejFand iFare the probability of failure at area jAandiA[111, 160]. The Weibull slope () is 1.2, which is close to the published value[156]. To understand the impact of uniaxial mechanical stress on tBD in samples, CVS is performed with VG = -5.2 and -7 V under tensile and compressive stresses, respectively. Fig.7-3 and 7-4 show impact of mechanical stress on tBD Weibull plots. Applied tensile stress reduces time to breakdown at 50% (tBD,50%) from 44 to 15 sec and from 1.4 to 1.1, respectively, as shown in Fig. 7-3(a) and (b). In addition, compressive stress, in Fi g. 7-4(a) and (b), also reduces tBD,50% from 24 to 7.3 sec and from 0.81 to 0.74, respectively. In summary, both applied tensile and compressive stresses degrade tBD of HfSiON dielectric, consistent with the previously reported data from process-induced strain and SiO2 dielectrics[111, 148, 161]. Mechanical stress dependence on tBD can be investigated by (1) monitoring the relative change in gate injection current of HfSiON Si MOS device as a function of applied mechanical stress[149] and (2) mechanical stress-induced increase in HfSiON/Si interface trap generation during CVS[111]. In our previous work[155], we al ready observed an incr ease in gate injection current, based on Poole-Frenkel emission, under bot h tensile and compressi ve stresses, matching

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80 with our mechanical stress dependence on tBD in this work. Hence, it is consistent with the observation that an increase in gate inj ection current results in a decrease of tBD.[149]. It has been reported that, for gate stack w ith high-k dielectric thicker than 7~8 nm, QBD for gate injection is equivalent with those for SiO2 with a thickness identical to the interfacial layer [158]. In Fig. 7-5, QBD for 8 nm thick HfSiON is measured and compared to QBD in samples with 7 nm thick HfSiON in order to confirm this interfacial layer breakdown mechanism. Since interface quality is independent of the thickness of HfSiON [162], it shows almost similar QBD distributions under 84 MPa of tensile and no me chanical stresses. Therefore, impact of mechanical stress on tBD in HfSiON Si MOS device can be explained by mechanical stressaltered trap generation in Si-rich HfSiON interlay er (IL) or at IL / (100) Si interface during CVS [111]. Both tensile and compressive mechanical stresses facilitate tr ap generation at IL / (100) Si interface or Si-O bond breaking in IL [99, 100, 105, 109, 111]. Figure7-2. The tBD distributions and area scaled tBD distributions for diffe rent size samples under VG = -5.2 V.

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81 Figure 7-3. Uniaxial tens ile stress effect a) on tBD distributions and b) on area scaled tBD distributions under VG = -5.2 V. Figure 7-4. Uniaxial compre ssive stress effect a) on tBD distributions and b) on area scaled tBD distributions under VG = -7 V.

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82 Figure 7-5. The QBD distributions for samples with two di fferent HfSiON dielec trics thickness (7 and 8 nm) under tensile mechanical stress 7.4 Discussion In this section, physical insight into impact of mechanical st ress on reliability issues, such as BTI, HCI, thermal stress-induced subthreshold leakage and VTH instability, will be provided based on how applied mechanical stress affects high k/Si interface trap generation and trap activation energy in high k dielectric. In previous section, impact of mechanical stress on TDDB of 7 nm thick HfSiON Si MOS device with negative gate voltage stressing was discussed. If TDDB occurs in thin (< 3 nm) high k or with positive gate voltage stressing, it do es not involved significant interface trap generation and may be dependent on high k la yer not Si rich interlayer[158] This can result in improved TDDB with mechanical stress if mechanical st ress reduces gate tunneling current[149]. Since a dominant gate tunneling mechanism in thick (> 3 nm) high k MOS device is Poole-Frenkel emission[158] and mechanical stress increases Poole-Frenkel emission or trap-assisted gate

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83 tunneling[130, 155], TDDB under mechanical stress may be improved only in thin (< 3 nm) high k, where mechanical stress can decrease direct gate tunneli ng current[102]. It is widely proposed that NB TI also results from the gene ration of trap via Si-H bond breaking at high k/Si interface[ 158, 163-165]. Fig. 7-6(a) shows high resolution TEM image of HfSiON Si MOS capacitor, which contains SiO2-like Si rich interlayer. Since mechanical stress makes Si-H bond less stable, as illustrated in Fi g. 7-6(b) and (c)[109], both [110] tensile and compressive mechanical stresses may degrad e NBTI in high k Si MOSFETs [100, 166]. As discussed above, positive bias temperat ure instability (PBTI) may not generate interface trap but involve charge trapping in high k bulk or hi gh k/Si interface [158, 165]. This may result in improved PBTI via mechanical st ress-induced increase in charge detrapping in thick (> 7 nm) HfO2 Si MOSFET [131]. An insignificant pr ocess-induced stress dependence of PBTI in thin (3 nm) high k Si MOSFET has been already reported, resulting from negligible charge trapping in thin hi gh k layer [151, 167]. Thermal stress-induced sub-threshold leakage, which can degrade th e retention time of dynamic random access memory (DRAM) [168], also results from Si-H bond breaking at high k/Si interface [168, 169]. Therefor e, both [110] tensile and compressi ve stresses likely increase thermal stress-induced sub-threshold leakage in high k Si MOSFETs via strain-enhanced hydrogen depassivation at hi gh k/Si interface [109]. It has been reported that HCI and VTH instability likely result from a trapping of charges in the pre-existing traps in high k/Si interface and/or high k dielectric without creation of additional traps [105, 107, 108, 158, 170]. Due to its t echnological importance, impact of external mechanical stress on HCI has been aggressive ly studied, showing opposite trends[105, 107, 108, 170, 171]. Two strain-related models can explain this discrepancy: (1) a decrease in charge

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84 trapping in relative thick gate dielectric via strain-altered tr ap activation energy[105, 107, 108] and (2) strain-induced Si band gap narrowing and an increase in impact ionization at drain edge[170, 171]. For both uniaxial te nsile and compressive stresses, a decrease in a trapping of injected hot carriers in high k lik ely results in an improved HCI, [130, 131] while an increase in impact ionization may multiply a number of hot carriers, leading to an degradation of HCI [84]. In high k integration, VTH instability has been one of ch allenges[158]. As explained above, applied mechanical stress reduces electron or /and hole trap activation energy in high k/Si interface and/or high k dielectric[ 130, 131]. This results in (1) an increase in trap-assisted gate tunneling (or Poole-Frenkel emissi on) and (2) a decrease in char ge trapping in high k[130, 131]. Therefore, VTH instability can be improved at the expe nse of an increased trap-assisted gate tunneling leakage under both uniaxia l tensile and compressive st resses. Due to substantial reduction of gate leakage in high k device,[165] this trade-off will be beneficial for device performance. Table 7-1 and Fig. 7-7 summarize impact of uniax ial mechanical stress on reliability issues with thick (~ 7 nm) high k Si MOSFETs as discusse d above. Most of reliability issues in strained Si technology may be evaluated with impact of mechanical stress on tr ap activation energy in high k and on high k/Si in terface trap generation.

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85 Figure 7-6. Interface trap generation under mechan ical stress. a) High resolution TEM image of HfSiON Si MOS capacitor. The gate dielectric is composed of Hf rich HfSiON and Si rich interlayer. b) Schematic of Si rich interlayer/ (100) Si interface including Si-H bonding. c) The calculated energies corre sponding to the hydrogen position [109]. Here, ESi-H is Si-H bonding energy and is applied uniaxial stress. Figure 7-7. Schematic band diagram for key strain-re lated parameters for reliability issues.Here, EA,H and EA,E is hole and electron trap activation energy, is applied uniaxial stress, Qot, IG, and Nit is trapped charge density, gate leakage, and the number of interface trap, respectively. 1999

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86 7.5 Conclusion Uniaxial mechanical stress may not be bene ficial for > 7nm thic k HfSiON Si MOS device from the view point of reliability issues, su ch as TDDB, BTI and th ermal stress-induced subthreshold leakage[172]. Applied tensile and comp ressive stresses degrade TDDB in HfSiON Si MOS device, which results from mechanical stre ss-induced increase in (1) trap generation in HfSiON/Si interface during negativ e gate voltage stressing and/ or (2) trap-assisted gate tunneling. For state-of-the-art strained-Si tec hniques, where up to 1.5 GPa of stress can be achieved in channel area, process-induced mechani cal stress in HfSiON/Si interface is inevitable. Therefore, interface engineering, which can impr ove the quality of HfSi ON/Si interface, may be required to improve TDDB, NBTI, and thermal stre ss-induced sub-threshold leakage of HfSiON Si MOSFETs together with stra in engineering[152]. Uniaxial strain engineering shows the potential to decrease HCI and VTH instability in high k MOSFETs via a decrease in charge trapping.

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87 Table 7-1. Measured and estimated reliability is sues of thick (> 7 nm) high k Si MOSFET as a function of uniaxial mechanical stress. KEY MECHANISM KEY STRAINRELATED PARAMETER TENSION COMPRESSIO N REF. VG < 0 POOLEFRENKEL EMISSION & INTERFACE TRAP GENERATION TRAP ACTIVATION ENERGY & SI-H BOND DEPASSIVATION DEGRADED DEGRADED THIS WORK TDDB VG > 0 POOLEFRENKEL EMISSION TRAP ACTIVATION ENERGY DEGRADED DEGRADED [155] VG < 0 INTERFACE TRAP GENERATION SI-H BOND DEPASSIVATION DEGRADED DEGRADED [100, 151, 166] BTI (VTH SHIFT) VG > 0 CHARGE TRAPPING TRAP ACTIVATION ENERGY IMPROVED IMPROVED [131] THERMAL STRESS INDUCED SUBTHRESHOLD LEAKAGE INTERFACE TRAP GENERATION SI-H BOND DEPASSIVATION DEGRADED DEGRADED IMPACT IONIZATION DEGRADED DEGRADED [170, 171] HCI CHARGE TRAPPING TRAP ACTIVATION ENERGY IMPROVED IMPROVED [105, 107, 108] VTH INSTABILITY CHARGE TRAPPING TRAP ACTIVATION ENERGY IMPROVED IMPROVED [131]

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88 CHAPTER 8 SUMMARY AND RECOMMENDATIONS FOR FUTURE WORK 8.1 Summary This study mainly focuses on externally applie d mechanical uniaxial stress effects on Si & Ge MOSFETs in terms of channe l mobility, gate tunneling leakage, and gate stack, such as high k dielectric and metal gate. The physics and advantages of uniaxial process induced stress are understood. Calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all nece ssary for large hole and electron mobility enhancement. It is explained that, for nMOSFETs under uniaxial tensile st ress along [110] and [100], the change in direct gate tunneling current for Ge is measured to be 3 times smaller than that for Si and opposite in sign. This reverse behavior occu rs because tensile stre ss for Si causes electron repopulation into 2 increasing the out-of-plane effectiv e mass while, in Ge, a reduced tunneling barrier is the dominant mechanism, resulting from the hydrostatic shift of the conduction band edge. This is followed by the study about the direct gate tunneling current of Ge and Si pMOSFETs. Due to larger 1) stress induced valen ce band edge splitting and 2) change in hole tunneling attempt frequency in inversion-layer of Ge under uniaxial tensile stress, the change in stress altered hole direct gate tunn eling current in Ge is ~4 times larger than that in Si. The workfunction of the metal gate is measured to cha nge with mechanical stre ss and decrease/increase ~20meV for each 1 GPa of uniaxia l tensile/compressive stress. Impacts of mechanical stress on direct and tr ap-assisted gate tunneling leakage current are also observed. The applied mechanical stress in creases trap-assisted t unneling current via the

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89 lowering of trap activation ener gy showing uniaxial stress may not be applicable to reduce gate leakage current when trap-assisted tunneling conduction is dominant. The roles of HfSiON dielectri c in strained Si technology are explored. Unlike HfSiOx and HfO2, HfSiON shows strain altered in creased dielectric constant, which allows scaling to achieve an increased gate capacitance. Both Ge and Si p-MOSFETs with TiN gate are observed to have insignificant Vt variation under uniaxial stress. The simple Vth shift model including the mobility correction shows good agreements with the measured data from di fferent types of p-MOSFETs (poly Si/SiO2 vs TiN/HfO2 gate stacks and Si & Ge channels). Finally, impact of mechanical uniaxial st ress on time dependent dielectric breakdown of HfSiON dielectric is studied. U nder constant voltage stressing w ith negative gate bias, applied mechanical stress causes HfSiON/S i interface to become less stable This results in more trap generation at interface and leads to a decr ease in time to dielectric breakdown. 8.2 Recommendations for Future work The demand for novel material and structur e becomes increasing in the CMOS regime. With strain engineering becoming a mainstream in VLSI technology, there will be much interest in studying its effects in channel mobility of novel devices, such as FINFET with Ge or III-V channel. While aggressive researches have been done on how strain improve channel mobility of planar novel channel devices, such as Ge and III-V less attention has been paid to strain effect on reliability of these devices. As a part of future work, it is interesting to continue the work on impact of mechanical stress on reliability of novel channel devices, such as time dependent dielectric breakdown, hot carri er injection, bias temperat ure instability and so on.

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90 The aggressive scaling of VLSI technology will push the channel length to ballistic transport regime and the importance of su rface roughness scattering limited mobility gets significant. Therefore, it is interesting to study strain effects on physical surface roughness or/and surface roughness scattering in order to fully understand mobility enhancement mechanism in very short ch annel length devices.

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106 BIOGRAPHICAL SKETCH Younsung Choi received the B.S. degree in mate rial science and engine ering, and the M.S. degree in physics from Yonsei University, Seoul Korea, in 1998 and 2002, respectively. He is currently working toward the Ph.D. degree in electr ical engineering at the University of Florida, Gainesville and has been with Dr. Thompson since 2004. He was with the Semiconductor Research a nd Development Center, Samsung Electronics, Korea, as a process engineer from 2002 to 2004. During that period, he was involved in the dry etch process development of memory device. His current research involves electrical characterizations and theoretical modeli ng of strained-Si and Ge MOS devices.