<%BANNER%>

Broadband Balun and Embedded Phase Noise Measurement System Design for RF IC Testing

Permanent Link: http://ufdc.ufl.edu/UFE0022762/00001

Material Information

Title: Broadband Balun and Embedded Phase Noise Measurement System Design for RF IC Testing
Physical Description: 1 online resource (217 p.)
Language: english
Creator: Kim, Jae
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: balun, bist, fm, marchand, phase, rf, test
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This research mainly focuses on test cost reduction for RF ICs. First, differential circuit measurements with a two port network instrument are discussed. Many companies and academic researchers use a four port instrument to measure their differential RF chips. This is the simple and accurate method, however, the test instruments are very expensive compared to a two port instrument, especially for high frequency ( > 20GHz) system. Alternative method is using balun to convert the differential signal into a single-ended signal, and then measures it with a two port instrument. This method can save the cost of the expensive instruments but need at least 6 different test setups. The time is another test part of test cost. By integrating the balun in a RF differential probe, the measurement can be simplified with a two port instrument. Second, for building a balun integrated probe, a new analysis is introduced for the Marchand balun. The new method takes the termination impedance variation into account. Third, a new closed form equation based on conformal mapping method for extracting the broadside coupled transmission line, is introduced and verified with FEM method. Fourth, a balun integrated probe is designed, fabricated, and measured in Cascade probe technology. Finally, the embedded test system or Built-in Self Test (BIST) for the phase noise is discussed. Testing and verification of the RF and microwave components are major parts of the total test cost. Over the years, various methods have been studied for reducing the test cost. A new method is an on-wafer phase noise measurement which is a very economical method while keeping a high level accuracy. Through the noise and system analysis, the proposed system specifications are determined and implemented in IBM8HP technology. Measurement indicates better performance than the commercial external systems up to 1.5GHz.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Jae Kim.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Eisenstadt, William R.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2009-11-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0022762:00001

Permanent Link: http://ufdc.ufl.edu/UFE0022762/00001

Material Information

Title: Broadband Balun and Embedded Phase Noise Measurement System Design for RF IC Testing
Physical Description: 1 online resource (217 p.)
Language: english
Creator: Kim, Jae
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: balun, bist, fm, marchand, phase, rf, test
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This research mainly focuses on test cost reduction for RF ICs. First, differential circuit measurements with a two port network instrument are discussed. Many companies and academic researchers use a four port instrument to measure their differential RF chips. This is the simple and accurate method, however, the test instruments are very expensive compared to a two port instrument, especially for high frequency ( > 20GHz) system. Alternative method is using balun to convert the differential signal into a single-ended signal, and then measures it with a two port instrument. This method can save the cost of the expensive instruments but need at least 6 different test setups. The time is another test part of test cost. By integrating the balun in a RF differential probe, the measurement can be simplified with a two port instrument. Second, for building a balun integrated probe, a new analysis is introduced for the Marchand balun. The new method takes the termination impedance variation into account. Third, a new closed form equation based on conformal mapping method for extracting the broadside coupled transmission line, is introduced and verified with FEM method. Fourth, a balun integrated probe is designed, fabricated, and measured in Cascade probe technology. Finally, the embedded test system or Built-in Self Test (BIST) for the phase noise is discussed. Testing and verification of the RF and microwave components are major parts of the total test cost. Over the years, various methods have been studied for reducing the test cost. A new method is an on-wafer phase noise measurement which is a very economical method while keeping a high level accuracy. Through the noise and system analysis, the proposed system specifications are determined and implemented in IBM8HP technology. Measurement indicates better performance than the commercial external systems up to 1.5GHz.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Jae Kim.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Eisenstadt, William R.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2009-11-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0022762:00001


This item has the following downloads:


Full Text

PAGE 1

1 BROADBAND BALUN AND PHASE NOIS E MEASUREMENT SYSTEM DESIGN FOR RFIC TESTING By JAE SHIN KIM A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2009

PAGE 2

2 2009 Jae Shin Kim

PAGE 3

3 To my Wife, Youn Pil Jeong

PAGE 4

4 ACKNOWLEDGMENTS I would like to thank Prof. Eisenstadt for hi s guidance and encouragem ent. Without him, I could not have completed my Ph.D dissertation. Wh en I was in deep trouble, he gave me the chance not to give up on my dream. I cannot compare his support a nd encouragement to anything that I have ever rece ived from anyone. He commands true respect from me both professionally and personally as he does from many of his previous and current students. I cannot thank him enough. Also, I would like to thank Prof. O, Prof. Ba shirulla and Prof. Benson of my committee for their help and advice. My research group members, Moisha Groger, Jeaseok Kim, Said Lami, Sarhi Harb, and Devin deserve my thanks. My parent-in-laws, Moobak Jeong and Young-Ae Lee should receive my thanks for their support and advice, which have encouraged me to complete my Ph.D dissertation. Their encouragement gave me the reason that I should continue to pursue my degree, and I am truly grateful for their endless support. Last, but not the least, my lovely wife, Younpil Jeong, should have all the credit for completing my dissertation. She has always been the source of my motivation to continue my research. She was there for me in times of diffi culty, and her resilience has always put me back to research during the ups and dow ns of my Ph.D years. Without her love and devotion, I could not have reached this point in my life.

PAGE 5

5 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................4LIST OF TABLES................................................................................................................. ..........8LIST OF FIGURES.........................................................................................................................9ABSTRACT...................................................................................................................................171 INTRODUCTION..................................................................................................................191.1. Introduction to RFIC Test................................................................................................ 191.2. The Test Cost Reduction Method....................................................................................211.3. Challenges and Approach in wafer-level RF Test........................................................... 221.4. Study Overview............................................................................................................ ...242 BACKGROUND TO THIS WORK....................................................................................... 252.1. Introduction to Diff erential Circuit..................................................................................252.2. Differential Circuit Measurement.................................................................................... 262.3. Baluns..............................................................................................................................272.4. Introduction to Embedded Testing.................................................................................. 293 MARCHAND BALUN ANALYSIS..................................................................................... 333.1. Introduction to Marchand Baluns.................................................................................... 333.2. Basic Operation of Marchand Baluns.............................................................................. 333.3. New Analysis Method for Planar Marchand Baluns....................................................... 353.4. Numerical Results of New Analysis for Plan ar Marchand Baluns..................................423.5. Verification of New Analysis for Planar Marchand Baluns............................................ 463.6. Conclusion.......................................................................................................................484 MARCHAND BALUN INTEGRATION USING BROADSIDE COUPLE D COPLANAR STRIPLINES.................................................................................................... 504.1. Broadside Coupled Coplanar Striplines (CPS)................................................................ 514.1.1. Introduction to Coplanar stripline (CPS)............................................................... 514.1.2. Broadside Coupled Asymmetric Coplanar Striplines (CPS)................................. 534.2. Analysis of Broadside Coupled Coplanar Striplines (CPS)............................................ 544.2.1 Even Mode..............................................................................................................554.2.2 Odd Mode...............................................................................................................554.3. Numerical Results of Broadside C oupled Coplanar Striplines (CPS)............................. 574.4. Marchan Balun Implementation...................................................................................... 604.4.1 The Design Verification using HFSS..................................................................... 614.4.2. Layout....................................................................................................................63

PAGE 6

6 4.5. Marchan Balun Measurement.......................................................................................... 654.6. Conclustion............................................................................................................... .......685 MARCHAND BALUN INTEGRATION USING BROADSIDE COUPLE D COPLANAR WAVEGUIDE................................................................................................. 705.1. Broadside Coupled Copl anar Waveguide (CPW)........................................................... 705.1.1. Introduction to Coplanar Waveguide (CPW)........................................................705.1.2. Broadside Coupled Coplanar Waveguide (CPW) with finite ground plane.......... 715.2. Analysis of Broadside Coupled Coplanar Waveguide (CPW)........................................ 725.2.1 Even Mode..............................................................................................................725.2.2 Odd Mode...............................................................................................................735.3. Numerical Results of Broadside C oupled Coplanar Waveguide (CPW)........................745.4. Marchan Balun Implementation...................................................................................... 785.4.1 The Design Verification using HFSS..................................................................... 795.4.2. Layout....................................................................................................................805.5. Measured Results.......................................................................................................... ...825.6. Conclustion............................................................................................................... .......846 EMBEDDED PHASE NOISE MEASUREMENT SYSTEM............................................... 856.1. Introduction to Phase Noise............................................................................................. 856.2. Phase Noise Modeling of an Oscillator...........................................................................906.2.1. Basics of Oscillators.............................................................................................. 906.2.2. Leesons Phase Noise Model................................................................................. 926.3. Phase Noise Measurement Methods................................................................................ 956.3.1. Direct Measurement.............................................................................................. 956.3.2. PLL-based Measurement (T wo oscillator method)........................................ 976.3.3. FM Discriminator (delay-line base d) Measurement (One oscillator method)...............................................................................................................1016.4. Embedded Phase Noise Measurement System.............................................................. 1056.4.1. FM discriminator system noise analysis.............................................................. 1056.4.2. Proposed Embedded Phase Noise Measurement System.................................... 1086.5. System Level verification of the Em bedded Phase Noise Measurement System......... 1096.6. Conclusion.....................................................................................................................1147 EMBEDDED PHASE NOISE MEASUREM ENT SYSTEM IMPLEMENTATION ......... 1167.1. System Considerations................................................................................................... 1167.2. System Implementation................................................................................................. 1177.2.1. Active Balun........................................................................................................1177.2.2. Active Delay Line................................................................................................1237.2.3. Active Phase Shifter (Based on Variable Delay Cell)......................................... 1307.2.4. Double Balanced Mixe r (Phase Detector)........................................................... 1377.2.4.1. Passive Ring Mixer (Input Structure)........................................................ 1377.2.4.2. Active RC Filter (Output Structure).......................................................... 1407.2.4.3. Double Balanced Mixer Result.................................................................147

PAGE 7

7 7.2.5. Phase Shifter Auto-adjustment............................................................................ 1527.3. Conclusion.....................................................................................................................1538 EMBEDDED PHASE NOISE MEAS UREMENT SYSTEM RESULTS ........................... 1548.1. Measurement Setup....................................................................................................... 1548.2. System Linearity and Calibra tion Constants Measurements......................................... 1568.3. System Sensitivity Measurement................................................................................... 1638.4. Phase Noise Measurement............................................................................................. 1658.5. Conclusion.....................................................................................................................1759 SUMMARY AND CONCLUSION..................................................................................... 1769.1. Summary........................................................................................................................1769.2. Conclusion.....................................................................................................................178A EXTRACTION OF BROADSIDE C OUP LED COPLANAR STRIPLINES CHARACTERISTIC PARAMETERS WITH FINITE GROUND PLANE........................ 180A.1. Analysis of Broadside Coupled Coplanar Striplines (CPS) with finite ground plane.. 180A.2. Even Mode....................................................................................................................181A.3. Odd Mode.....................................................................................................................184B E XTRACTION OF BROADSIDE COUPLED COPLANAR WAVEGUIDE CHARACT ERISTIC PARAMETERS WITH FINITE GROUND PLANE........................ 189B.1. Broadside Coupled Coplanar Wavegui de (CPW) with finite ground plane................. 189B.2. Even Mode....................................................................................................................190B.3. Odd Mode.....................................................................................................................193C SYSTEM MISMATCH RESPONSE................................................................................... 198C.1. Signal Distortion due to Delay Line and Phase Shifter................................................ 198C.2. System Mismatch Response.......................................................................................... 202D SYSTEM LIMITATION......................................................................................................206D.1. The Discriminator Transfer Response.......................................................................... 206LIST OF REFERENCES.............................................................................................................209BIOGRAPHICAL SKETCH.......................................................................................................217

PAGE 8

8 LIST OF TABLES Table page 4-1 Numerical and simulated coupling coefficients ................................................................. 604-2 Design parameter of the fabr icated balun probe membrane.............................................. 655-1 Numerical and simulated coupling coefficients................................................................. 775-2 Design parameter of the fabr icated balun probe membrane.............................................. 816-1 Error contribution to the measurement............................................................................1007-1 Baluns Performance Summary........................................................................................ 1227-2 Performance summary..................................................................................................... 1387-3 Performance summary..................................................................................................... 1468-1 Calibration Constant Evaluation...................................................................................... 162

PAGE 9

9 LIST OF FIGURES Figure page 1-1 Silicon and Test Capi tal per Trans istor.............................................................................. 201-2 ATE cost increase with additiona l mixed signal and RF features..................................... 201-3 Evolution from A) conventiona l test with high-cost ATE B) test with balun probe C) embedded test with low-cost ATE..................................................................................... 232-1 Differential system test methods with A) conventional 4-port measurement B) 2-port measurement using baluns................................................................................................. 272-2 Conventional balun implementation A) Balanced two wire transmission line, I1 = I2 B) Unbalanced coaxial cable transmission line.................................................. 282-3 Marchand compensated balun A) Coaxial cross section B) Equivalent transmission line model..................................................................................................................... ......292-4 Low cost test of an integrated transc eiver through on-chip te st circuitry [2.9]................. 313-1 Marchand Compensated Balun A) Coaxial cross section B) equi valent transmissionline model..................................................................................................................... ......343-2 Simplified equivalent circuit of a fourth-order Marchand balun.......................................353-3 Block diagram of a symmetrical Marcha nd balun with two identical couplers................373-4 Single section coupled line coupler geometry and port designations................................ 373-5 Insertion loss (S21, S31) of the planar Marchand Balun as a function of coupler electrical length ( ) depending on the coupling factor (C)................................................ 423-6 Insertion loss (S21, S31) of the planar Marchand Balun as a function of coupler electrical length ( ) depending on the coupling factor (C)................................................ 433-7 Responses of the planar Marchand Balun as a function of coupler electrical length ( ) at A) 1:1 impedance transforming ratio (Z0=ZL C=-4.78dB) B) 1:2 impedance transforming ratio (Z0=2ZL C=-7dB) C) 1:3 impeda nce transforming ratio (Z0=3ZL C=-8.45dB) D) 1:4 impedance transforming ratio (Z0=4ZL C=-9.54dB) with the optimized coupling factor (C)............................................................................................ 443-8 Responses of the planar Marchand Balun as a function of coupler electrical length ( ) at A) 1:1 impedance transforming ratio (Z0=ZL C=-2.46dB) B) 1:2 impedance transforming ratio (Z0=2ZL C=-4dB) B) 1:3 impedance transforming ratio (Z0=3ZL C=-5.2dB) D) 1:4 impedance transforming ratio (Z0=4ZL C=-6.08dB) with the optimized coupling factor (C)............................................................................................ 45

PAGE 10

10 3-9 ADS verification A) The schematic diag ram for the conventional planar Marchand Balun B) The vertical view of the broadside coupled stripline structure.......................... 473-10 Numerical results verifica tions A) Numerical results and B) Simulated result with 7dB of the coupling factor when the im pedance transforming ratio is 1:2........................483-11 Numerical results verifica tions A) Numerical results and B) Simulated result with 4.78dB of the coupling factor when the impedance transforming ratio is 1:1................... 484-1 RF/microwave dual probe structure A) th e overall structure B) cross-sectional view of the probe membrane C) top view of the probe membrane............................................ 504-2 Coplanar strips transmission line structure [4.4]............................................................... 524-3 Broadside coupled coplanar stripline (CPS) cr oss-section with finite ground plane.........544-4 Even and odd mode characteristic impeda nce variation depend ing on slot width ( b a) as a function of signal line width ( a) while the ground plane width ( c b ) is 50 um. ............................................................................................................................................584-5 Even and odd mode characteristic impe dance variation depending on GND width ( c b) as a function of signal line width ( a) while slot width ( b a ) is 30 um.........................584-6 Coupling coefficient depending on slot width ( b a ) as a function of signal line width ( a) when GND widths ( b a ) are 50 um and .......................................................594-7 100GHz Marchand balun structure....................................................................................624-8 Simulation results of Marc hand balun integrated probe.................................................... 634-9 Actual layout of Marchand balun integrated probes using broadside coupled CPS..........644-10 Die photo of Marchand balun integrated probes using broadside coupled CPS................644-11 Measuring balun integrated probes usi ng a dual-through connected to a dual-probe....... 654-12 Measurement procedure with two port network analyzer.................................................. 664-13 Measured results of Marc hand balun integrated probe...................................................... 674-14 Comparison between the measured a nd simulated results of Marchand balun integrated probe A) Inserti on loss B) Phase Difference....................................................674-15 Flow chart of the Marchand balun design methods........................................................... 695-1 Coplanar strips transmission line structure [5.2]............................................................... 705-2 Cross-section of a broadside coupled copl anar waveguide with finite ground plane........ 72

PAGE 11

11 5-3 Calculated even and odd mode characterist ic im pedance with the slot width variation as a function of signal line width wh ile the ground plane is fixed at 50 um ......................755-4 Calculated even and odd mode characteri stic impedance as a function of signal line width ( a) with 20mm finite slot width...............................................................................765-5 Calculated coupling factor with slot width variation as a function of signal line width for the cases of 100 um finite ground plane a nd infinite ground....................................... 775-6 Marchand balun integrated probe struct ure using finite ground broadside coupled lines.......................................................................................................................... ..........795-7 Marchand balun structure using fi nite ground broadside coupled lines............................ 805-8 Actual layout of Marchand balun integrated probe using broadside coupled CPW..........815-9 Measured results of Marchand balun integrated probe...................................................... 825-10 Comparison between the measured a nd simulated results of Marchand balun integrated probe A) Inserti on loss B) Phase Difference....................................................836-1 RF sideband spectrum from sp ectrum analyzer with deriving L(fm)................................ 866-2 L(fm) which is described logarithmically as a function of offset frequency...................... 886-3 Conventional Oscill ator Block Diagram............................................................................906-4 Parallel Resonance Circuit................................................................................................. 916-5 Normalized bandwidth of a resonator................................................................................ 926-6 Phase noise: Leeson versus equation (6.26) [6.6].............................................................956-7 SSB phase noise with direct measurement method........................................................... 966-8 Basic diagram of PLL-based phase noise measurement system........................................ 976-9 Conventional double-balanced mixer characteristic.......................................................... 986-10 Mixer operation........................................................................................................... .......986-11 Basic delay line freque ncy discriminator method............................................................ 1026-12 Discriminator implementa tion using time delay [6.9]..................................................... 1036-13 Linearized noise model of a delay line frequency discriminator method in case that the delay line and phase shifter share the same signal path............................................. 105

PAGE 12

12 6-14 Linearized noise model of the delay line frequency discrim inator method in case that the delay line and phase shifter use different signal paths...............................................1066-15 Block diagram of the embedded phase noise measurement system................................ 1086-16 System level verification of the propos ed phase noise measurement system in Agilent ADS.....................................................................................................................1106-17 System simulation results of the pro posed phase noise measurement system in Agilent ADS: A) input power spectrum B) de lay line and phase sh ifter output C) the system noise output D) the phase noise result................................................................. 1126-18 Calibration process A) Calibration te st set-up B) Calibra tion equations and calibration results............................................................................................................ .1137-1 The on-chip phase noise meas urement system block diagram........................................ 1167-2 Single NMOS balun schematic........................................................................................ 1187-3 Cascaded common source-common gate balun schematic..............................................1197-4 Amplitude response of the active balun........................................................................... 1217-5 Amplitude difference of the active balun, (S21-S31)......................................................... 1217-6 Phase difference of the active balun................................................................................ 1227-7 Cascaded of finite gain amplifiers................................................................................... 1247-8 Cascaded gain stage time response with excessive gain.................................................. 1257-9 Delay line cell schematic................................................................................................. 1267-10 Transient response of the proposed differential inverting amplifier................................ 1277-11 Transient simulation results of the pr oposed differential inverting amplifier................. 1287-12 AC response of the proposed differential inverting amplifier......................................... 1287-13 Transient response of the proposed delay line................................................................. 1297-14 Delay time variation dependence on the operation frequency of operation.................... 1307-15 Basic cell of the proposed phase shifter........................................................................... 1327-16 Simplified schematic of the self-biased re plica-feedback current source bias for the differential variable de lay cell stage [7.9]........................................................................ 133

PAGE 13

13 7-17 Schematic of the self-biased replica-feedb ack cu rrent source bias for the differential variable delay cel l stage [7.9].......................................................................................... 1347-18 Transient simulation results for the proposed 6-stage variable delay cell depending on the PMOS load bias.................................................................................................... 1367-19 Simplified schematic of the passive ring mixer (bias not shown)................................... 1377-20 Phase detector topology (bias not shown)....................................................................... 1397-21 Operational amplifier schematic (bias not shown).......................................................... 1417-22 AC modeling of Operational amplifier............................................................................ 1427-23 Amplifier A) gain and B) phase acco mplished with the proposed compensation and the conventional RC compensation network................................................................... 1457-24 Double Balanced Mixer output spectrum........................................................................ 1477-25 Double Balanced Mixer Out put as a phase detector........................................................ 1487-26 Die photo of the Double Balanced Mi xer with active RC filter and buffer.....................1497-27 Test setup for the phase detector...................................................................................... 1507-28 Simulated and measured phase detect or output for different phase input....................... 1507-29 Measured conversion gain fo r different input frequencies.............................................. 1517-30 Measured conversion gain for different LO power.......................................................... 1517-31 Auto-phase adjustment unit............................................................................................. 1528-1 Layout of the proposed system (1 mm 1.5 mm)..............................................................1558-2 Test setup of the embedded phase noise measurement system........................................ 1568-3 Linearity test procedure and calibra tion method for the embedded phase noise measurement system........................................................................................................ 1588-4 Example of the linearity test for, A) An input test signal (FM dev=200 kHz, FM rate =1 MHz) B) The resultant output signal at 1 MHz..........................................................1598-5 Linearity measurement as a function of FM deviation while the modulation index is less than 0.2 radian...........................................................................................................1618-6 Sensitivity A) small output test signal (F M dev=2 Hz, FM rate =1 MHz) B) System sensitivity.........................................................................................................................164

PAGE 14

14 8-7 System output noise and system sensitivity..................................................................... 1658-8 Phase noise measurement procedure A) input test signal B) system output.................... 1668-9 Phase noise measurement for 1GHz 0dB m input generated by Agilent E8542A...........1688-10 Phase noise measurement for 0.5GHz 0dBm input generated by an Agilent E8542A.... 1698-11 Phase noise measurement for 1GHz 0dB m input generated by Agilent E4421B............ 1708-12 Phase noise measurement for 0.5GHz 0dB m input generated by Agilent E4421B.........1718-13 Phase noise measurement for 1GHz 0dBm input generated by the commercial external VCO (mini-circ uits ZX95-1700W-S)................................................................ 1728-14 Phase noise measurement for 0.8GHz 0dBm input generated by the commercial external VCO (mini-circ uits ZX95-1700W-S)................................................................ 1738-15 Phase noise measurement for 0.6GHz 0dBm input generated by the commercial external VCO (mini-circ uits ZX95-1700W-S)................................................................ 1738-16 Compensated phase noise measurement for 0.6GHz 0dBm input generated by the commercial external VCO (min i-circuits ZX95-1700W-S)............................................ 174A-1 Broadside coupled coplanar stripline (CPS) cr oss-section with finite ground plane.......180A-2 Field distribution under A) even mode excitation. B) odd mode excitation.................... 181A-3 Detailed conformal mapping proced ure for the even mode excitation............................ 182A-4 Detailed conformal mapping proced ure for the odd mode excitation............................. 184A-5 Conformal mapping procedure for the inte rmediate dielectric region in odd mode excitation..................................................................................................................... .....185B-1 Cross-section of broadside coupled copl anar waveguide with finite ground plane......... 189B-2 Field distribution of the broadside coupled CPW under A) an even mode excitation and B) an odd mode excitation with a bottom and top ground plane.............................. 190B-3 Field distribution of the finite ground broadside coupled CPW under an even mode excitation..................................................................................................................... .....191B-4 Detailed conformal mapping proced ure for the even mode excitation............................ 191B-5 Field distribution of the CPW with finite ground plane under an odd mode excitation.. 193B-6 Detailed conformal mapping proced ure for the odd mode excitation............................. 194

PAGE 15

15 B-7 Conformal mapping procedure for the lowe r dielectric region in odd m ode excitation. ..........................................................................................................................................195C-1 System simulation block diagram.................................................................................... 198C-2 Delay line circuit points for the simulation input and output.......................................... 199C-3 Spectrum of A) the input B) the delay line output........................................................... 200C-4 Analog delay line output as a f unction of input power at 1GHz.....................................201C-5 Variable phase shifter A) input spectrum and B) output spectrum.................................. 202C-6 Output spectrum A) mi smatched (input mismatch 10O) on a linear scale B) mismatched in log scale................................................................................................... 203C-7 Output spectrum A) matched in li near scale B) matched in log scale............................. 204C-8 System responses depending on the mismatch in linear scale......................................... 205C-9 System responses depending on the mismatch in log scale............................................. 205D-1 Nulls in sensitivity of delay line discriminator [D.1]...................................................... 207

PAGE 16

16 LIST OF ABBREVIATIONS FGBC-CPW: Finite Ground Broadsid e Coupled Coplanar Waveguide FGBC-CPS: Finite Ground Broads ide Coupled Coplanar Strips CPW: Coplanar Waveguide CPS: Coplanar Stripline DUT: Device Under Test FM: Frequency Modulation LO: Local Oscillator ADS: Advanced Design System RF: Radio Frequency HFSS: High Frequency Structural Simulation PLL: Phase-Locked Loop

PAGE 17

17 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy BROADBAND BALUN AND PHASE NOISE MEASUREMENT SYSTEM DESIGN FOR RFIC TESTING By Jae Shin Kim May 2009 Chair: William R. Eisenstadt Major: Electrical and Computer Engineering This research mainly focuses on test cost redu ction for RF ICs. First, differential circuit measurements with a two port network instrument are discussed. Many companies and academic researchers use a four port instrument to measure their differential RF chips. This is the simple and accurate method, however, the test instrument s are very expensive compared to a two port instrument, especially for high frequency (>20GHz ) system. Alternative method is using balun to convert the differential signal in to a single-ended signa l, and then measures it with a two port instrument. This method can save the cost of the expensive instrument s but need at least 6 different test setups. The time is another test part of test cost. By integr ating the balun in a RF differential probe, the measurement can be simp lified with a two port instrument. Second, for building a balun integrated probe a new analysis is introduced for the Marchand balun. The new method takes the termination impedance varia tion into account. Third, a new closed form equation based on conformal mapping method for extracting the broadside coupled transmission line, is introduced and verified with FEM method. Fourth, a bal un integrated probe is designed, fabricated, and measured in Cascade probe te chnology. Finally, the embedded test system or Built-in Self Test (BIST) for the phase noise is discussed. Testing and verification of the RF and microwave components are major parts of the tota l test cost. Over the years, various methods

PAGE 18

18 have been studied for reducing the test co st. A new method is an on-wafer phase noise measurement which is a very economical met hod while keeping a high level accuracy. Through the noise and system analysis, the proposed system specifications are determined and implemented in IBM8HP technology. Measurem ent indicates better performance than the commercial external systems up to 1.5GHz.

PAGE 19

19 CHAPTER 1 INTRODUCTION 1.1. Introduction to RFIC Test W ireless communication devices among the semiconductor industrys most high volume products, are subject of a continually growing number of standards and applications. In todays competitive market, incorporating a comprehensive testing strategy into a wireless modules design flow is indispensable to its timely de velopment and economic success [1.1][1.2]. Modern wireless transceivers and receiv ers are highly integrated systems. Their diverse specifications and components and high frequencies of operatio n make testing them complex and expensive. Increasing the effectiveness and cost efficiency of analog and RF tests in integrated systems is a complex problem that researchers have addressed at various levels. Recent efforts include defect modeling, automated test algorithms, alternate tests for system specifications, DFT techniques [1.3] and BIST techniques [1.4 ][1.5][1.6] due to high cost Auto matic Test Equipment (ATE) for RF/microwave circuits. As shown in Figure 1-1, the test cost issue was predicted in the 97 SIA roadmap in which test capital per transistor was expected to exceed the silicon capital cost. The portion of the test cost in semiconductor manufacturing can not be i gnored because of ever-increasing complexity of tests. Although analog and RF circuitry has far fewer transistors than di gital circuitry in most modern system-on-chip (SOC), analog and RF ci rcuits require the use of complicated test procedures, increasing the test time and the cost of automatic test equipment (ATE). As a result, the test cost of modern mixe d-signal SOC can be as high as 30% of their manufacturing cost [1.7].

PAGE 20

20 Figure 1-1. Silicon and Test Capital per Transistor. A key contributor to the test cost is the cost of external ATE and its interface to the device under test (DUT). Figure 1-2 gives an idea of how basic ATE test cost increase when incorporating mixed signal and RF options to it. In order to re duce the complexity and external ATE cost and its interface to DUT, it is desirable to move some testing func tion to the test board and into the device under test (DUT) itself. Figure 1-2. ATE cost increase with additi onal mixed signal and RF features.

PAGE 21

21 In the past 30 years, wafer probing above a GHz has progressed to a mainstream very large scale integration (VLSI) topic. With the develo pment of high performance and high frequency on wafer probes and probe stations, wafer-level test and characteri zation can be performed before ICs were diced and packaged. Current RFIC te sting methodologies requi re performance-based measurement (i.e. using external instruments), a nd the complexity of appl ications increases the number of instruments in a given test system [1.8]. Extremely complex, million-dollar automated test equipment (ATE) systems that integrate a ll of the functions and provide a much higher throughput capability than typica l rack-and-stack equipment have now become readily available from numerous vendors. This trend of incr easing instrument numbers, complexity and performance is expected to continue. 1.2. The Test Cost Reduction Method Conventional test m ethods use external testers to generate test stimulus and the DUT response is directly measured from the stimulus High-bandwidth data transfer is done at the operational speed of the DUT. The measurement re sults include the transmission properties of the interconnection, such as wires, connectors, probe cards path. Extra effort and cost to decouple the response of the inte rconnection from the actual response of the DUT are needed to ensure accurate measurement results. Figure 1-3 A) shows a conventional test setup to measure a DUT. The measurement instruments have high cost and the interfaces betw een the instrument and DUT have high cost as well. Figure 1-3 B) presents one of methods fo r reducing the test cost [1.9]. This method is proposed to measure the differential circuitry which generates differential signals. By combining and converting the differential signal into a single-ended signal, the number of high-cost interfaces can be reduced and the differential instruments for RF test can be replaced with a cheap instruments such as 2-port network anal yzer. Usually, a 4-port instrument like a 4-port

PAGE 22

22 network analyzer is much more expensive th an a 2-port instrument like a 2-port network analyzer. Figure 1-3 C) shows that the integration of embedded test circuitry into a DUT, results in a new on-chip and off-chip distribution of test resources compared to conventional test resource partitioning. Embedded test integrates the capability of the high-speed and the highbandwidth portion of the external ATE circuits directly into the DUTs. With these embedded circuits, high-speed test stimulus and response signature generation functi ons can be customized as required per test application type, and onchip test data compression reduces ATE data requirements. 1.3. Challenges and Approach in wafer-level RF Test Much research has been perform ed in the effo rt to reduce test cost, but, many challenges still exist. For the balun integrated probe for di fferential circuit measurement as shown in Figure 1-3 B), the availability of balun integrated probe s is very limited due to the lack of frequency range. Prior to this work, the available ba lun integrated probes only covered the 10GHz operational range in external boa rd-level implementations [1.9] or with coaxial baluns [1.10]. Since a high frequency (> 20GHz) instrument co sts much higher than that of the instrument (<20GHz), the high frequency balun over 20GHz n eeds to be developed to provide test cost reduction. Embedded test can improve test coverage at internal nodes in a complex system-on-a-chip (SOC) and reduce the use of high-cost equipments as well. Up to date, many RF building blocks such as the low noise amplifier (LNA) [1.11][1.12] and the power amplifier (PA) [1.13], can be measured using embedded test circuitry. Howe ver, the embedded characterization of VCO or PLL blocks has not been researched as much as the amplifier gain blocks are. Particularly, the embedded phase noise characterization of a VCO is incomplete compared with the other RF building blocks.

PAGE 23

23 A B C Figure 1-3. Evolution from A) conventional test with high-cost ATE B) test with balun probe C) embedded test with low-cost ATE

PAGE 24

24 1.4. Study Overview This thes is focuses on reducing the overall cost for testing RFICs. Th e test cost reduction approach in this work mainly consists of tw o methods. The first approach is to reduce the number of the high cost interfaces to the DUT by designing balun integrated RF/microwave probes. Chapter 2 briefly introduces the concept of differential signal and the differential circuit measurement using a conventional 2-port VNA, and not using an expensive 4-port VNA. Chapter 3 introduces a new Marchand balun analys is for finding the design parameters. Chapter 4 and 5 explains design methods for balun integrated RF/microwave probes. The second approach is to build the embedded test circuitry ne xt to an RF circuit fo r converting the high cost test signal into the low cost test signal. Chapte r 2 introduces Built-In-Self-Test (BIST) and past work done by other researchers. Chapter 6 shows the theoretical background for an embedded phase noise measurement system. Chapter 7 s hows the circuit implementation and Chapter 8 shows measurement results for embedded phase noise measurement system.

PAGE 25

25 CHAPTER 2 BACKGROUND TO THIS WORK 2.1. Introduction to Differential Circuit The use of differential circuit topologies is becom ing increasingly common in a wide range of microwave/RF applications. Differential circuits have exce llent immunity to many noise sources that are generated from power supplies, adjacent circuitry and other external sources that are electrically or electromagne tically coupled [2.1]. Generally, the nature of signal propagation is taught in terms of single-en ded modes. The single-ended mode is distinguished from two other types of signal propaga tion, differential mode and co mmon mode. Differential mode signals propagate through a pair of traces. One trace carries the signal as we normally understand it, the other carries a signal that is exactly equal and opposite ideally. Differential and singleended modes are not quite as different as they may initially appear. All signals have a return, typically the zero-voltage, or ground. Each side of a differential signal would return through the ground circuit, except that since each signal is exactly equal and opposite the returns simply cancel. Therefore, there is no ground path cancel Common-mode refers to signals that occur on both traces of a differential signal pair or on both the single-ended trace and ground. Common mode signals are most often generated by spurious conditions within a circ uit or coupled into a circuits from adjacent or outside sources. Common-mode signals are almost always undesirable and many of current circuit and board design rule s are created to preven t them from occurring [2.2][2.3]. Single-ended signals are compared to some kind of reference level such as the positive or ground voltage, device threshol d voltage, or another signal some where on the circuit. On the other hand, a differential signal is re ferenced only to its port pair. Th at is, a logical state occurs if

PAGE 26

26 the voltage on one trace is sufficiently higher th an on the other trace. Differential signals have several advantages compared to single-ended signals. Timing is much more precisely defined because it is easier to control the crossover point on a signal pair than it is to control an absolu te voltage relative to some other reference. If the traces are not equal length (the signals arri ve at different times at the ends), commonmode noise might result which cau se signal timing and EMI issues. Differential circuits can normally operate at higher speeds than comparable single-ended circuits since they referen ce no other signals than themselves. The timing of signal crossover can be more tightly controlled, and the voltage cab be greatly reduced. The result net signal is twice as large compared to ambient noise since differential circuits react to the difference between the signals on tw o traces. Therefore, di fferential signals, all other things equal, have greater si gnal to noise ratios and performance. 2.2. Differential Circuit Measurement For efficient m easurement of a differential circuit without engineering overhead [2.3], a new method was proposed [2.2]. This method uses baluns in order to measure the differential circuit, by which measurement steps greatly are reduced and the measurement setup time also is saved. Figure 2-1 shows the basic concepts of th is method. In general, a 4-port equipments is always more expensive than 2-port counterparts. If one measures a differential circuit with 2-port equipment, one must measure it through 6 independe nt steps. All the steps need different test setup [2.2]. In particular, if onchip measurement is required for the device-under-test (DUT), the test setup becomes more complicated. Howeve r, the number of measurement steps can be reduced by using baluns. Previous research de veloped a relatively low frequency RF probe embedded probe, which uses separate baluns to connect the DUT ports and coaxial cable for equipment connection [2.2]. In this work, baluns are integrated on a microwave probe structure directly. By integrating the balun on this thin film structure, the balun can operate at very high frequency. Until the operation frequency reaches the cutoff frequency of the transmission line

PAGE 27

27 structure, the balun can opera te. Through designing, implemen ting and measuring the balun integrated probe, test cost can be reduced compared to using a 4-port ne twork network analyzer. A B Figure 2-1. Differential system test methods with A) conventi onal 4-port measurement B) 2-port measurement using baluns. 2.3. Baluns A balun is a device which converts a balanced impedance (differential signal) to unbalanced impedance (single-ended signal) and vice versa. In addition, baluns can also provide im pedance transformation, hence the name Balun Transformers. Coaxial cable, microstrip and CPW lines are examples of unbalanced transmissi on lines, while a two wire transmission line is a example of balanced transmission line as s hown in Figure 2-2. Two conductors of the same geometry having equal potential with 180 phase difference constitute a balanced line. When this condition is not sa tisfied, the transmission line is terms as unbalanced as shown in Figure 2-2 B) (i.e, I1 I2 and Ig 0) in this case Ig is finite and flows through the outer side of the grounded shield, since there is also potential voltage at the outer conductor [2.4].

PAGE 28

28 A B Figure 2-2 Conventional balun implementation A) Balanced two wire transmission line, I1 = I2 B) Unbalanced coaxial cable transmission line Baluns are required for such ci rcuits as balanced mixers, push-pull amplifiers, balanced frequency multipliers, phase shifters, balanced modulators, and dipole antenna feeds. Several different kinds of balun structures have been developed, such as th e coaxial cable baluns, lumped-element baluns, active baluns and Marcha nd-type baluns. In this work, the focus was on building a planar Marchand balun performing at 60GHz operation for high frequency differential circuit measurements. There are several types of tran smission line based balun topologies. In this section, it is shown how to choose the balun topology for integrated balun probes. The Marchand balun is one of the most commonly used components in broadband balanced circuit design. As compared with othe r balun topologies, the Marchand balun structure when implemented using couplers will have a less strict requirement for Z0e (even mode characteristic impedance) [2.4]. To obtain a ba lun with good performance, it is sufficient to have

PAGE 29

29 Z0e =3 to 5 times larger than Z0o (odd mode characteristic impeda nce) [2.5]. A wide bandwidth balun can be obtained by proper selection of the balun parameters. Figure 2-3 show s the original Marchand balun [2.5], which consists of an unbalanced, an open-circuited, and two shortcircuited and balanced transmission line secti ons and equivalent transmission line model. A B Figure 2-3. Marchand compensated balun A) Coaxial cross secti on B) Equivalent transmission line model. In this work, the Marchand balun is imple mented on a microwave/RF probe membrane thanks to its simplicity and potential for wi de bandwidth operation. A new Marchand balun analysis is proposed in order to build 1:1 to 1:4 impedance transformations with the best achievable response. Through the proposed analys is, a simple design equation is constructed depending on the specific application. Chapter 3 discusses the proposed Marchand balun analysis and Chapter 4 and 5 show an actual balun impl ementation by using broadside coupled lines on the microwave/RF probe membrane. 2.4. Introduction to Embedded Testing Traditionally, RF design and sili con m anufacturing have contributed the highest overall IC manufacturing cost component, thus the test cost s received little atte ntion. Improvements in

PAGE 30

30 manufacturing technology, and rela xed performance requirements of some application domains, lead to high-yield low-area design processes; the cost of manufacturing RF dies has reduced appreciably. However, the test cost has not redu ced at the same rate, and indeed has been an increasing percentage of the overall IC manufact uring cost. The first high-volume microwave chip tests were relatively simple, and include d the tests of switches, amplifiers, mixers, LNA/mixer combinations, etc. Wafer level tests were used to prune away catastrophically defective dies before packaging and the RF path was completely by-passed in the wafer level test. As IC complexities have incr eased, the yields are improved, the package costs become an appreciable component of the overall cost, and th e need for wafer level RF path test before packaging has arisen. Since 1999, there has been a steady increase in the number of high volume RFICs that are tested on-wafer instead of being tested at p ackage level. In addition, RFIC systems are being built with advanced packag es by which require known-good-die (KGD) which are pre-tested. With the development of hi gh-performance and high-frequency on-wafer probes and probe stations, wafer-level te st and characterization can be performed before ICs are diced and packaged. Conventional analog/RF IC tests us e ATE (automated test equipment) systems. However, the cost associated with ATE systems has significant impact on the total manufacturing test cost. The co mplexity of the test systems needs to be matched to the complexity of the ICs to be test ed and generally the cost of A TE system is proportional to the complexity of the device to be tested. Also, ATE systems are costly to operate and require a complicated test procedure development, wh ich makes the situati on even worse [2.6]. In order to overcome the problems mentioned earlier, embedded test is a potential new solution. For example, digital BIST (built-in-self-t est) circuits allow lowe r cost ATE testers to evaluate the quality of the device [2.7]. Since th e DUT tests itself using BIST, it lowers the test

PAGE 31

31 cost a lot by requiring less expensive ATE tests. Unfortunately, analog/RF BIST technology has always lagged behind digital BIST due to the re quired high accuracy of signals generated and measured on chip. Particularly, c onventional test methods use extern al testers to generate test stimuli and the DUT response is directly measur ed from the stimuli. Thus, the measurement results include all the possible parasitic e ffects such as the in terconnection coupling, transmission properties and matc hing conditions. However, the integration of embedded test circuitry into the DUTs results in a new on-chip and off-chip distribut ion of test resources compared to the conventional methods [2.8]. The embedded testing circuits communicate w ith the ATE through a low-rate digital data interface or DC voltages. Figure 2-4 illustrates an example of an RF BIST concept. From the extracted information at different intermediate st ages, catastrophic and parametric faults can be detected and located [2.9]. Figure 2-4. Low cost test of an integrated transceiver through onchip test circuitry [2.9]. A loop-back connection between the transmitter a nd receiver chains is one of the earlier strategies to test th e functionality of RF sy stems [2.10]. On-chip implementation of this technique have been demonstrated [2.11][2.12]. Th is approach does not re quire external stimuli

PAGE 32

32 and it is effective in detecting catastrophic faults in the comp lete signal path. Also, several parametric embedded tests have been proposed fo r BIST. For example, the center frequency and bandwidth of RF circuits-under-test (CUT) were extracted using a step input signal on chip [2.13]. The noise figure (NF) and th e input referred third-order in terception point (IIP3) of the DUT were estimated using machine-l earning (ML) based methods [2.14][2.15]. Phase noise or jitter performance of a PLL is one of the most critical design parameters in RF systems. While phase noise measures the in accuracy of a signal source in the frequency domain, jitter shows the clock edge uncertainty in the time domain. Several on-chip schemes that directly measure jitter in the time domain have been proposed [2.16][2.17][2.18]. These schemes are based on time interval analysis, and therefor e are limited by the purity of the reference clock and gate delay resolution of the given technology. Phase noise can be a critical parameter that characterizes the RF, analog and digital sources. Timing jitter can be measured indirectly from phase noise by integration of the noise spectrum over a specified frequency range. Generally, phase noise measurement has been limited to o ff-chip methods, using spectrum analyzers or phase noise analyzers [2.19].

PAGE 33

33 CHAPTER 3 MARCHAND BALUN ANALYSIS 3.1. Introduction to Marchand Baluns The Marchand balun m ay be one of the most popular forms of microwave balun used to generate a balanced signal. In particular, the planar coupled -line Marchand balun shows good compatibility with microwave circuits (MIC) and monolithic MICs (MMIC) [3.1]. Numerous studies about its design and anal ysis have been performed sin ce it was first introduced in 1944 [3.2]. Most designs, however, emphasize maximum po wer transfer to the balanced load within a specified passband using a quarter wave transmission line equivalent circuit. A wide bandwidth balun can be obtained by pr oper selection of th e balun parameters. Figure 3-1 (a) shows the origin al Marchand balun [3.2], which c onsists of an unbalanced, an open-circuited, and two short-circuited a nd balanced transmission line sections. 3.2. Basic Operation of Marchand Baluns The balun basically consists of an unbalance d, an open-circuited, two short-circuited, and balance transm ission line sections Each section is about a quar ter-wavelength long at the center frequency of operation. A coaxial version of a compensated Marchand balun is shown in Figure 3-1 A), while its equivalent circ uit representation is shown in Figure 3-1 B). The compensation term is used in broadband baluns where th e balanced output and reduced phase slope are maintained over a wide bandwidth. As shown in Figure 3-1 A) [3.2], this structure basically consists of two coaxial lines, each /4 long at the center frequenc y. The left-hand line has the characteristic impedance of Z1. The second conductors of these transmission line sections with housing mask another two short-circuited /4 lines that are in series with each other and shunt the balanced lines, having a characteristic impedance of ZB, at location a and b. As shown in the equivalent circuit (Figure 3-1 B)) [3.3], the stubs Zs1 and Zs2 are in series and shunt the balanced

PAGE 34

34 lines. Their characteristic impedance is made as large as possible. These impedances along with the other transmission line impedances determin e the impedance transformation and bandwidth. A B Figure 3-1. Marchand Compensated Balun A) Coaxia l cross section B) eq uivalent transmissionline model.

PAGE 35

35 Figure 3-2 shows a simplified equivalent circ uit of the Marchand balun. Because of the equal shunting effects on the balanced lines, th ese stubs provide greater bandwidth. The open circuit stub Z2 provides low impedance at the junction of the four different lines and acts like a series resonant circuit. The series resonant circ uit with a shunt resonant circuit reduces the phase variation over the designed bandwidth. The rati o of the characteristic impedances of shortcircuited stubs determines the bandwidth. The highe r the ratio is, the wider the bandwidth is. The transmission line ZB can be designed with a characteristic impedance of the balanced line or can be used as an impedance transformer between the desired impedance and the balanced-line impedance [3.2]. Figure 3-2. Simplified equivalent circu it of a fourth-order Marchand balun. 3.3. New Analysis Method for Planar Marchand Baluns Since the structure of Marchand balun is symm etrical, the four tran sm ission lines can be treated as two sections of coupled lines. Marchand balun analysis in its original paper [3.2] and similar work [3.3][3.4] is base d on the calculation of input (unbalanced port) and output (balanced port) impedance for coaxial-based coupled lines. Therefore, it is difficult to use these

PAGE 36

36 analyses for a planar type Ma rchand balun since the calculated impedance is the impedance of inner and outer conductor in co axial cable. The following references have been focused on the fabrication and synthesis, includ ing coupled line equivalent circuits models and computer-aided analysis [3.5][3.6][3.7][3 .8]. However, using these results, the designer still need to work a lot due to their complex analyses. Since K. S. Ang proposed Marchand balun analysis using scattering matrix [3.9] by assuming the symmetri c coupled lines, many researches adapted the scattering matrix based analysis and synthesized the broadband balun on standard Si technology [3.10][3.11][3.12], LTCC [3.13][3.1 4]or FR4 PCB board [3.15]. Angs analysis method can calculate the appropriate coupli ng factor and simplify the balun design. To get a design solution for a coupling factor for the desire d Marchand balun, the coupling factor C of the coupled line needs to be assumed. This conventional Marchand balun analysis [3.9] did not consider the effect of the coupled li nes electrical length ( ). This conventional analysis is optimized exactly at the center frequency. The transmission lines characteristics vary significantly depending on the transmission lines physical and electrical le ngth. Therefore, if one c onsiders the effect of the electrical length ( ) of the transmission line, the analys is will be more accurate. Also, the response depending on the coupled lines electrical length ( ) illustrates the actual response of the designed Marchand balun. The start of this new analysis procedure is the same as the conventional case [3.9]. For symmetrical baluns, the scattering matrix of the balun can be deri ved from the scattering matrix of two identical couplers. First, consider th e case where the source and load impedances are equal to Z0.

PAGE 37

37 Figure 3-3. Block diagram of a symmetrical Marchand balun w ith two identical couplers. In this case, the couplers scattering para meter includes the elect rical length of the transmission line as opposed to simpli fying it using a quarter wavelength ( /4). Figure 3-4 shows geometry and port designa tions of the coupled line. Figure 3-4. Single section coupled line c oupler geometry and port designations. When two unshielded transmission lines are cl ose together, power can be coupled between the lines due to the interacti on of the electromagnetic fields of each line. Designs usually assume coupled transmission operate in the TEM mode, which is rigorous ly valid for stripline and coaxial structures and appr oximately valid for microstirp structure. For the sake of simplicity, the input (port 1) is matched and port 3 is isolated. Equation (3.1) shows the

PAGE 38

38 couplers scattering parameter [ 3.16] with the assumption of a homogeneous case which means the even and the odd mode phase velocity are equal. 0 tan 1 tan 0 sin1cos 1 tan 1 tan 0 sin1cos 1 0 0 sin1cos 1 0 tan 1 tan sin1cos 1 0 tan 1 tan 02 2 2 2 2 2 2 2 2 2 2 2 jC jC jC C jC jC jC C jC C jC jC jC C jC jC Scoupler (3-1) Equation 3-1 simplifies into the conventional analysis of [3.9] by substituting the electrical length ( ) with a quarter wavelength ( = /4 = /2 ). The scattering parameter of the Marchand balun can then be obtained by usi ng the voltage waves relationships that are indicated in Figure 3-3, which is derive d as equation 3-2. 2 2 2 4222 2 3 3 2 4222 2 2 2 3 3 2 3 3 2 3 3 2 2441 1 1 1 1 1 1 1 1 y x y yyyx y xyxyyx y yyyx y x y xyxyyx y xyxyyx y xyxyyx y yyx Sbalun (3-2) where tan 1 tan sin 1cos 12 2 2jC jC y jC C x If the load (balanced port) terminat ion impedance is no longer equal to Z0, the baluns scattering matrix will be modified from [S]balun to [S]'balun. The relationship between the two matrices is given by equations 3-3 through 3-5. 1 1[][] []balun balun balunSASISA (3-3)

PAGE 39

39 where [I] is the identical matrix, while [ ] and [A] are in equation 3-4 and 3-5. 0 0 0 000 0 0 000 ZZ ZZ ZZ ZZL L L L (3-4) 0 0 0 0200 0 20 0 01 ZZ ZZ ZZ ZZ AL L L L (3-5) In order to simplify the final equation, the e quation 3-2 is converted to the equation 3-6. 22 2312 23 22 12 12 12 11 2 2 2 4222 2 3 3 2 4222 2 2 2 3 3 2 3 3 2 3 3 2 2441 1 1 1 1 1 1 1 1 SSS SSS SSS y x y yyyx y xyxyyx y yyyx y x y xyxyyx y xyxyyx y xyxyyx y yyx Sbalun (3-6) Finally, 333231 232221 131211SSS SSS SSS Sbalun (3-7) where 2 12 0 1111 2322 0 02L LLSZZ SS SSZZZZ

PAGE 40

40 0 0 2223 0 12 21 122 ZZZZSS ZZS SSL L L 0 0 2223 0 12 31 132 ZZZZSS ZZS SSL L L 1 2 2 1 2 123 2 22 2 0 0 22 22 0 22 22 2 23 2 0 22 22 0 22 22 2 23 2 33 22 SSZZZZSZZSS ZZSZZSS SSL L L L L 1 2 2 1 423 2 22 2 0 0 22 22 0 22 22 2 23 2 230 32 23 SSZZZZSZZSS SZZ SSL L L L These equations can be reduced to the e quations of the quarter wavelength case by replacing the electrical length ( ) with a quarter wavelength ( = /4 = /2). If the load termination impedance ( ZL) is the same as Z0, the equation 3-7 is reduced to equation 3-2. Also, in case of the electrical length of coupled line s are equal to a quarter wavelength, equation 3-7 is reduced to equation 3-8. When the load termination is equal to Z0, equation 3-8 is the same as equation 3-2. Equation 3-8 shows that the use of identical coup led sections results in balun outputs of equal amplitude and opposite phase, regardless of the coupling factor and port terminations. To achieve optimum power transfer of -3dB to each balanced port, equation 3-8 is required.

PAGE 41

41 1 2 1 1 1 2 1 2 1 2 1 12 1 2 1 2 1 2 1 1 1 2 1 12 1 2 1 12 1 2 1 12 1 2 1 1 2 10 2 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2Z Z C C Z Z C Z Z C Z Z C Z Z CC j Z Z C Z Z C Z Z C C Z Z C Z Z CC j Z Z C Z Z CC j Z Z C Z Z CC j Z Z C Z Z C SL L L L L L L L L L L L L L L L balun (3-8) 2 131, 21, balun balunSS (3-9) With the equation (3.8) and (3.9), the required coupling factor fo r optimum balun performance is as followed. 1 2 10 Z Z CL (3-10) It is interesting to note that when all the ports are terminated with the same impedance, such as 50 where the impedance transforming ratio is unity, the required coupling facto is -4.8dB which is different from the well-known result of -3dB. Based on the equation 3-7, the use of commonly assumed -3dB couplers will result in -3.52 dB of the insertion loss (S21, S31) and output isolation (S23, S32). Input and output return loss is -9.54dB at the center frequency. The proposed analysis can provide an accura te design parameter for the input and output impedance to the balun. With the known impedance, the coupling factor of the coupled line determines the optimum response of the Marchand balun.

PAGE 42

42 3.4. Numerical Results of New Analys is for Planar Marchand Baluns Equation 3-7 shows the dependence of the coupli ng factor on the insertion loss as shown in Figure 3-5 while the load (balan ced) impedance is the same as the input (unbalanced) impedance ( ZL = Z0 ) Figure 3-5. Insertion loss (S21, S31) of the planar Marchand Balun as a function of coupler electrical length ( ) depending on the coupling factor (C). As expected in previous section, the op timum response can be achieved with -4.8dB symmetric coupled lines. Tight er coupled lines can increase operation bandwidth while it degrades the response at the center frequency. Therefore, as long as a compensation method is provided, the tighter coupled lines can improve the operational bandwidth. For this work, the microwave/RF probe has a cal ibration method to make up for its uneven response. Suppose there is a desired maximum insertion loss at -4 dB in order to quantify the operational bandwidth. Figure 3-6 shows the insert ion loss of the marchand balun with different coupling coefficients and shows f1 and f2 which represent the intersection point at -4dB for deriving the normalized bandwidth (( f2f1)/ f0). If the coupling coefficient is greater than the optimized coupling coefficient which is calculat ed through equation 3-10, the insertion loss at

PAGE 43

43 the center frequency decreases. With more than -3 dB coupling coefficient, the insertion loss at center frequency is less than -4 dB. The maxi mum bandwidth balun can be designed using the equation 3-11 derived with -4 dB in sertion loss at the center frequency. ,21 ,311 2.5balunbalunSS (3-11) Balun operational bandwidth can be maximized around -2.46 dB with 1.23 times the normalized bandwidth while the normalized bandw idth of balun optimized for maximum center frequency response is 0.88. Therefore, the balun design can be divided into two styles. First is the design which has the best re sponse at center frequency. Sec ond is the design which has the widest operational bandwidth fo r broadband applications. Figure 3-6. Insertion loss (S21, S31) of the planar Marchand Balun as a function of coupler electrical length ( ) depending on the coupling factor (C). Figure 3-7 illustrates the balun responses de pending on the impedance transforming ratio (ZL/Z0) while the coupling factors are decided by equation 3-10. Figure 3-8 illustrates the responses depending on the impedance transforming ratio (ZL/Z0) while the coupling factors are

PAGE 44

44 decided by equation 3-11 for the broadband applications. S21 (=S31=S13=S12) represents the insertion loss. S11 represents reflection at unbalanced port. S22 (=S33) represents reflection at balanced port. S23 (=S32) represents the isolation between the balanced ports. It is worth noting that as the impedance transforming ratio increas es, the operational bandwidth starts to shrink while the response at the cente r frequency is optimized. Figure 3-7. Responses of the plan ar Marchand Balun as a function of coupler electrical length ( ) at A) 1:1 impedance transforming ratio (Z0=ZL C=-4.78dB) B) 1:2 impedance transforming ratio (Z0=2ZL C=-7dB) C) 1:3 impedance transforming ratio (Z0=3ZL C=-8.45dB) D) 1:4 impedance transforming ratio (Z0=4ZL C=-9.54dB) with the optimized coupling factor (C).

PAGE 45

45 Figure 3-8. Responses of the plan ar Marchand Balun as a function of coupler electrical length ( ) at A) 1:1 impedance transforming ratio (Z0=ZL C=-2.46dB) B) 1:2 impedance transforming ratio (Z0=2ZL C=-4dB) B) 1:3 impedance transforming ratio (Z0=3ZL C=-5.2dB) D) 1:4 impedance transforming ratio (Z0=4ZL C=-6.08dB) with the optimized coupling factor (C). Figure 3-7 shows a reasonable performance for all the responses. Particularly, the input reflection shows a perfect matching at th e center frequency. The isolation (S23) and the reflection (S22) for balanced ports is poor due to the inhere nt limitations of the Marchand balun. Several studies have been done to improve this poor isol ation [3.9][3.17]. All the reported compensations for the isolation need to use lumped elements such as resistors. However, this work limits the balun to a transmission line structure. Figur e 3-8 shows the achievable widest operation bandwidth with the sacrifice of input matching at the center frequency. As like the case of Figure 3-7, the operational bandwidth st arts to shrink with the increase of the impedance transforming ratio.

PAGE 46

46 3.5. Verification of New Analysis for Planar Marchand Baluns For verification, numerical results are compar ed with simulated results using Agilent ADS. Figure 3-9 shows the simulation setup and the si mulated structure. In order to find proper parameters for coupled-line structures, LINE CAL in ADS is used. The proposed analysis assumes the homogeneous media and TEM mode propa gation so that a stripline design is used. The stripline structure can support TEM mode propaga tion and can be consider ed to be built in a homogeneous media. In order to achieve tight coupling, the simulation is performed with a broadside coupled stripline. Figure 3-10 shows the results when the input impedance is 50 and the output impedances are 100 with coupling coefficient is -7 dB while Figure 3-11 shows the results when the input impedance is 50 and the output impedances are 50 with the coupling coefficient as -4.78 dB. Figure 3-10 and Figure 3-11 show the comparis on between the numerical results of the proposed analysis and the simulated results in Agilent ADS. All the re sponses of both cases show very good agreement. Through the propos ed analysis, the design procedure can be simplified by removing time-consuming trial and error when finding the optimum design parameters. With a given input and output impe dance, the design equation suggests the proper coupling level to optimize the design.

PAGE 47

47 A B Figure 3-9. ADS verification A) The schematic diagram for th e conventional planar Marchand Balun B) The vertical view of the br oadside coupled stri pline structure.

PAGE 48

48 A B Figure 3-10. Numerical results veri fications A) Numerical results and B) Simulated result with 7dB of the coupling factor when the im pedance transforming ratio is 1:2. A B Figure 3-11. Numerical results veri fications A) Numerical results and B) Simulated result with 4.78dB of the coupling factor when th e impedance transforming ratio is 1:1. 3.6. Conclusion A new analysis method for a planar Marchand ba lun is proposed with the consideration of input (unbalanced) port and out put (balanced) port terminati on impedances. The proposed method was verified with Agilent ADS and shows very good accuracy when compared to commercial RF/Microwave simulation tools. In order to achieved optimize designs, conventional methods take much longer time compared to the proposed method. The proposed

PAGE 49

49 analysis method leads the designers to find th e optimum balun design parameters for specific application. By this method, a high frequency Ma rchand baluns are designed and implemented as shown in chapter 4 and chapter 5.

PAGE 50

50 CHAPTER 4 MARCHAND BALUN INTEGRATION USI NG BROADSIDE COUPLE D COPLANAR STRIPLINES In measuring four-port differential circuits, the most convenient method is to use a fourport vector network analyzer ( VNA), which has balanced differential source and receivers [4.1]. However, due to the high cost of such test equi pment, the balun integrated probe is proposed to measure the differential ci rcuit with commonly available two-port VNA by focusing on measuring the differential mode [4.2]. Figure 4-1. RF/microwave dual probe structure A) the overall structure B) cross-sectional view of the probe membrane C) top view of the probe membrane. In a previous chapter, the new planar Ma rchand balun analysis method was proposed. By using the previous chapters analysis, the optimum design parameters can be derived to build the

PAGE 51

51 Marchand balun integrated differential probe for combining the differential signal into a single ended signal. In order to implement the ba lun on a RF/microwave probe membrane, probe membrane structure is investigated for the purpose of finding an available transmission line structure to build the optimum optimum coupling coupled line. Figure 4-1 shows one example of a RF/microwa ve probe structure. Figure 4-1 A) shows the overall microwave probe structure and Figure 4-1 B) and C) illustrate the probe membrane structure. A microwave membrane probe generally consists of three dielectric layers, two metal layers and a via. For low frequency applicati on (<40GHz), the connection from DUT to COAX uses a microstrip line structure which has 50 characteristic impedance while for higher frequency applications (<100GHz), a coplanar waveguide structure is used. For the probe membrane, there is no ground shield for the upper and lower layers due to th e fact that these are only two available metal layers. Therefore, the ava ilable coupled line structures are very limited when implementing balun probe membrane. Two possible transmission line structures ar e investigated and used for the balun implementation. This chapter deals with coplanar stripline structure and th e next chapter handles coplanar waveguide structures. The two structures do not need a ground plane on an upper or a lower signal line plane. Therefore, they are very good candidates for a two metal layer structure. 4.1. Broadside Coupled Coplanar Striplines (CPS) 4.1.1. Introduction to Copl anar stripline (CPS) The physical realization of a c oplanar strip transmission line (CPS) is illustrated in Figure 4-2. This was first studied by C. P. Wen [4.3]. It is realized by setting two conductor strips of width w1 and w2 in close proximity supporte d by a dielectric of thickness h while on the other side of the dielectric, there is no ground plane. If w1 is not equal to w2, the structure is called as an asymmetric CPS (ACPS). CPS is a full planar transmission line similar to slot lines or

PAGE 52

52 coplanar waveguide. CPSs low order propagation mode is not a real TEM mode due to the bottom and top dielectric discontinuity. The f undamental mode is quasi-TEM mode because it resembles a pure TEM mode since the longitudi nal field components are smaller than the transverse ones, which can be ignored [4.4]. The advantages of CPS are as follows: (1) both series as well as shunt mounting of devices is possible. (2) The CPS is a balanced transmission line. The main disadvantage of the CPS is th at because it lacks a ground plane, the line can support besides the fundamental CPS mode tw o other parasitic modes, namely the TE0 and TM0 dielectric slab waveguide mode s. These parasitic modes do not have a cutoff frequency. The TE0 and TM0 modes have their electric fields predom inantly parallel and perpendicular to the dielectric-air interface, respect ively. The electric field of the fundamental CPS mode is predominantly parallel to the dielectric-air interface and henc e strongly couples to the TE0 parasitic mode at discontinuities. Figure 4-2. Coplanar strips tr ansmission line structure [4.4].

PAGE 53

53 4.1.2. Broadside Coupled Asymmetric Coplanar Striplines (CPS) Uniform coupled-line circuits are used for many application including filters, couplers, and impedance matching networks. These circuits ar e usually designed by utilizing the impedance, admittance, chain and other parameters characterizing the coupled-line four-port network. These parameters may be obtained in terms of coupl ed-line impedances or admittances, and phase velocities for even and odd modes of excitation fo r the case of pure TEM lines in a homogeneous medium or quasi-TEM lines in an inhomogene ous medium. Recall that even and odd modes of excitation correspond to the cases where the voltages and the curre nts on the two lines are equal in magnitude and are in phase for the even m ode and out of phase for the odd mode [4.5]. Generally, the thin film process for the fabrication of a RF/microwave probe membrane does not support a top and bottom me tal layer which works as the sh ield (or housing) in order to protect against a field disturbance due to an external source. Therefore, the field analysis of a coupled lines structure without a shield is much complicated when compared to the case with a shield. In addition, the optimized balun design requires at least -4.8dB of coupling factor between the coupled lines. A conventional parallel coupled lines structur e can not achieve this tight coupling except with a special kind of para llel coupler such as a Lange Coupler. But the Lange coupler needs to connect two separated signal lines by wirebonding or air-bridging to increase the coupling effect. However, the broa dside coupled line structure can achieve such tight coupling and be very area-efficient compared to a parallel coupled line structure. Hence, the balun is integrated in a probe membrane structure using a broadside coupled line structure. In addition, the small area for the balun integrati on requires that the fini te ground plane effect should be considered. Generally, a ground plane, which is electrically and physically narrow, typically less than g/5 wide, where g is the signal wavelength [4.6], is considered as a finite

PAGE 54

54 ground. A finite ground can support a great circu it size reduction and can influence higher order mode propagation. Recently, finite ground plane coplanar waveguide and coplanar striplines have received strong attention due to their inherent advantages. However, these applications are limited due to the lack of analysis of these stru ctures. In the next section, broadside coupled coplanar stripline is anal yzed for the first time. 4.2. Analysis of Broadside Coupled Coplanar Striplines (CPS) Figure 4-3. Broadside coupled copl anar stripline (CPS) cross-section with finite ground plane. Figure 4-3 shows a symmetric finite ground broa dside coupled coplanar striplines crosssection with three dielectric la yers. The signal line width is a and the gap between the signal line and ground is b-a The ground width is c-a Due to the narrow ground, the field distribution will distort a lot, which makes a big difference of the ch aracteristics of both the finite and the infinite ground coupled-line structures. The dielectric constant and the he ight of the dielectric between the signal lines are r1 and h1, respectively. The dielectric c onstant of the dielectric located on the upper and the lower signal lines are r2 and h2, respectively. The detailed analysis of this cross-section is found in Appendix A. In this section, the final results are used for extracting the balun design parameters.

PAGE 55

55 4.2.1 Even Mode The final even mode capacitance is described by equation 4-1. )( )( )( )( 1 )( )(3 3 0 2 2 20 1 1 10321 e e e e r e e r eeeEkK kK kK kK kK kK CCCC (4-1) where K(k) is the complete elliptic integr al of the first kind with module k and K'(k) its complement. acb bca k h a h c h b h b h c h a k h a h c h b h b h c h a ke e e 3 2 2 2 2 2 2 2 1 1 1 1 1 1 1exp exp1 exp exp exp1 exp exp exp1 exp exp exp1 exp (4-2) The effective dielectric consta nt and the characteristic impedance are derived as the equation 4-3 and 4-4. )( )( )( )( )( )( 1 )( )( 1 13 3 1 1 2 2 2 1 1 1 e e e e e e r e e r EeffkK kK kK kK kK kK kK kK (4-3) )( )( )( )( 1203 3 1 1 0 e e e e Eeff EkK kK kK kK Z (4-4) 4.2.2 Odd Mode The final even mode capacitance is described by equation 4-5.

PAGE 56

56 )( )( )( )( 1 )( )( )( )(3 3 0 2 2 20 2_1 2_1 1_1 1_1 10321 o o o o r o o o o r oooOkK kK kK kK kK kK kK kK CCCC (4-5) where K(k) is the complete elliptic integr al of the first kind with module k and K'(k) its complement. acb bca k h a h c h b h b h c h a k H WW H WW k H W H W k h a h b h b h a ko o o o o 3 2 2 2 2 2 2 2 1 41 1 31 2_1 1 4 1 2 1_1 1 1 1 1 1exp exp1 exp exp exp1 exp 2 tanh 2 tanh1 2 tanh 2 tanh1 exp1 exp exp1 exp (4-6) W1, W2, W3, W4 and H1 can be derived as shown in equation 4-7. 2 1 exp exp exp1 exp arcsin 1 exp 1 exp arcsin )( )(32 4 1 1 1 1 1 3 1 1 1 2 1 1 1 1WW W k h c h b h c h b FW k t h b t h b FW kK kK H Wo o o o (4-7)

PAGE 57

57 where F(,k) is the incomplete elliptic integral of the first kind, written in Jacobis notation. The effective dielectric constant and the characteristic impe dance are in equation 4-8 and 4-9. )( )( )( )( )( )( )( )( 1 )( )( )( )( 1 13 3 2_1 2_1 1_1 1_1 2 2 2 2_1 2_1 1_1 1_1 1 o o o o o o o o r o o o o r OeffkK kK kK kK kK kK kK kK kK kK kK kK (4-8) )( )( )( )( )( )( 1203 3 2_1 2_1 1_1 1_1 0 o o o o o o Oeff OkK kK kK kK kK kK Z (4-9) 4.3. Numerical Results of Broadside Co upled Coplanar Striplines (CPS) The analytic expressions are verified with an aid of MA TLAB. The field distribution change will affect the charac teristic impedance and the coupl ing. Figure 4-4 illustrates the characteristic impedance variation as the slot width changes from 10 um to 50 um while the ground plane width is 50 um The thickness of the lower ( h1) and the upper ( h2) dielectrics are 10 um and 15 um As the slot width increas es, the characteristic impe dances of both even and odd mode excitations increase because the electric field is distributed over a large area. Even mode characteristic impedance increases at a great ra te than odd mode characteristic impedance since the electric field distribution under the even mode excitation concentr ates more in the slot area. Figure 4-5 shows the characteristic impedance variation as the ground width changes from 50 um to 250 um. The response is similar to that of Figure 4-4. As the ground plane width increases, the electric field converges into ground plane w ith less loss. Therefore, the characteristic impedance decreases, especially the even mode excitation because the field distribution under the even mode excitation is more concentrated over the slot. For odd mode

PAGE 58

58 excitations, the electric field c oncentrates on the lower dielectric, intensively. So the odd mode case varies less with gr ound width variation. Figure 4-4. Even and odd mode characteristic impedance varia tion depending on slot width ( b a) as a function of signal line width ( a) while the ground plane width ( c b ) is 50 um. Figure 4-5. Even and odd mode characteristic impedance variation depending on GND width ( c b) as a function of signal line width ( a) while slot width ( b a ) is 30 um.

PAGE 59

59 Through this analysis, the coupling factor can be derived using well-known the equation 410. 00 00 eo eo Z Z C Z Z (4-10) Figure 4-6 shows one of example which descri bes the coupling factor The coupling factor increases as the ground width gets narrower and slot width gets larger. As explained earlier, the even mode characteristic impedance is aff ected more than the odd mode characteristic impedance. The even mode field distribution aff ects the coupling between the signal lines. As the signal line gets wider, more electric field concen trates between the signal lines so that the coupling gets stronger. Figure 4-6. Coupling coeffici ent depending on slot width (b a) as a function of signal line width (a) when GND widths (b a) are 50 um and Table 4-1 compares the numerical results and simulated results for several cases. The simulation is performed with a 3D EM simulato r for the purpose of the verification of the proposed analysis. Through this analysis, the coupling coeffici ent for the Marchand balun is

PAGE 60

60 extracted and verified with 3D-EM simulator which uses Finite Element Method (FEM). The simulation results are based on the frequency so that the coupling coefficients are chosen by selecting the best value through all frequency re sponses. Table 4-1 compares the numerical and simulated results of broadside coupled coplanar waveguides. Si mulated results and numerical results show less than 0.2dB difference. Howeve r, the simulation takes longer time than the numerical results due to the complex mesh equa tions. The proposed equation saves the time and effort in finding the initial design parameters. Table 4-1. Numerical and si mulated coupling coefficients Signal widhth ( a ) Gap width ( b-a ) GND width (c-b ) Numerical result (dB) Simulated result (dB) 50 um -4.536 dB -4.427 dB 30 um 200 um -4.745 dB -4.782 dB 50 um -3.59 dB -3.454dB 30 um 50 um 200 um -3.805 dB -3.755 dB 50 um -3.477 dB -3.3836 dB 30 um 200 um -3.688 dB -3.548 dB 50 um -2.754 dB -2.595 dB 50 um 50 um 200 um -2.962 dB -2.797 dB 50 um -2.827 dB -2.812 dB 30 um 200 um -3.031 dB -2.943 dB 50 um -2.24 dB -2.206 dB 70 um 50 um 200 um -2.437 dB -2.382 dB 4.4. Marchan Balun Implementation The basic parameters were extracted from the analytic expression in the previous section. The characteristics of these broa dside coupled line, CPS does not affect the frequency variation as long as the coplanar line works in TEM m ode. Generally, CPS and CPW can sustain the normal operation without serious loss up to 220GHz Also, the dispersion of these CPS can be

PAGE 61

61 ignored due to the relatively th ick metal layer. Rigid calculati on shows 200nm of skin depth in 100GHz operation. But this process metal thic kness is around 5um. The broadside coupled CPSs quarter wavelength is around 500um in 60 GHz operation, which is verified through HFSS simulation. The baluns were in tegrated on a Cascade probe stru cture (GSSG with 150um pitch). This thin film process has relatively large proces s variation, especially on dielectric thickness. General application of this process is for the integration of the single or parallel coupled transmission lines with a lo wer ground plane. So, the ground of this process can not be considered as infinite ground due to the fact th at there is no shielding or housing. The basic parameters were extracted from the broads ide coupled CPS analysis. The final design verifications were performed w ith the aid of HFSS because the proposed analysis can not consider the discontinuity causing by transmission line connection to the coaxial cable. In order to check the effect of the coupling coefficient vari ation in chapter 3, the baluns were fabricated in 30, 50, 70 and 90 um coupled line widths with 50 um gap width between the signal line and the ground. 4.4.1 The Design Verification using HFSS Figure 4-7 shows the schematic diagram of th e Marchand balun integrated probe using the broadside coupled CPS with finite ground. An unbalanced port connects with coaxial cable for the connection to the test equipment while a ba lanced port touches the DUT with sharp probe tips. For an accurate measurement, calibration is essential. The final verifications were performed as closely as possible to the actual pr obe environment, which means the air encloses this structure. The air region set up as a radiation boundary in simulation.

PAGE 62

62 Figure 4-7. 100GHz Marcha nd balun structure Figure 4-8 shows the simulation results. The re sults include the unbalanced to balanced insertion losses (S31, S32) and phase difference (target value 180) to check the balun performance. The operational bandwidth ranges from 20GHz to 100GHz. The coupled line uses 3 dB coupling factor for which the signal line width (a) chosen is 50 um and the slot width (b-a) is 50 um with approximately 80 um ground plane width (c-b).

PAGE 63

63 Figure 4-8. Simulation results of Marchand balun integrated probe. 4.4.2. Layout Actual layouts of Marchand balun integrated probe using broadside coupled CPS is shown in Figure 4-9. In the actual layout, the ground plane shape varies in order to fit the design into the original GSSG (150 um pitch) probe structure. For 90um signal line design, the gap width becomes smaller. The design of 30 um of the signal line width facilitates -4.8 dB coupling factor to get the best center frequenc y performance. The designs of 50um and 70um of the signal line widths are taken into account th e process variations. These two designs show around -3 dB and 2.5 dB coupling coefficients by the previous an alysis. The connections to both DUT and COAX use 50 microstrip lines for easy assembly. Layout was performed with L-Edit. Figure 4-10 shows the die photographs of the fa bricated balun integrated probes. Four rectangular shapes of the botto m of the figure represents the DUT connection tips which usually have very small resistance (<2 ).

PAGE 64

64 Figure 4-9. Actual layout of Marchand balun integrated probes using broadside coupled CPS. Figure 4-10. Die photo of Marcha nd balun integrated probes us ing broadside coupled CPS. Table 4-2 organizes the Marc hand balun design parameters fabricated by Cascade Microtech thin film process. The measurement is performed for one desi gn due to the expensive probe combining process such as high frequency coaxial cable, probe tips connection expense etc. For one measurement, at least two prototype de signs were assembled to make sure of the measurement accuracy.

PAGE 65

65 Table 4-2 Design parameter of the fabricated balun probe membrane Signal Line Width Slot Widt h Ground WidthTransmission Line Width Tested Structure 25 um X 30 um 50 um 80 um 45 um X 25 um O 50 um 50 um 80 um 45 um O 25 um X 70 um 50 um 80 um 45 um X 25 um X 90 um 30 um 80 um 45 um X 4.5. Marchan Balun Measurement The balun integrated probes are measured usi ng a dual-through pattern that is connected to a dual-probe, as shown in Figure 4-11. The displa yed ports, port1~port3, ar e measured 2-ports at a time using a 2-port VNA, while the 3rd port is terminated in a matched load. This is followed by a post measurement process that shifts the refe rence phase plane, as shown in Figure 4-11. In this measurement, the dual through length will be considered seriously due to relatively high frequency configuration. To overcome this probl em, the measurement is adjusted by the phase difference due to dual-through on the ISS. Figure 4-11. Measuring balun inte grated probes using a dual-thr ough connected to a dual-probe.

PAGE 66

66 Figure 4-12. Measurement procedure with two port network analyzer. Figure 4-12 shows the measurement procedure w ith a two port vector network analyzer. While measuring the two ports, the other port is terminated with 50 Final scattering parameters are organized with these measurement results. Figure 4-13 shows the measurement result with a -3 dB coupling factor coupled line. The signal line width (a) chosen is 50 um and the slot width (b-a) is 50 um with approximately 80 um ground plane width (c-b). For the comparison with the simu lated results in HFSS in Figure 4-8, all the scales in Figure 4-12 are the same as thos e in Figure 4-8. The phase imbalance is less than 9 through the entire measured frequency range. Amplitude differences between the balanced ports are less than 1 dB up to 90GHz. As shown in the figure, lower amplitude imbalance indicates lower phase imbalance. The rela tive bandwidth can be calculated by simply normalizing the frequency at -4dB with the center frequency. In this case, f1, f2 and f0 are equal to 28GHz, 82GHz, and 55GHz, respectively. 21 0Relative Bandwidth=0.98 ff f (4.11) This designs coupling factor is le ss than -3 dB due to process varia tion. As analyzed in chapter 3, greater than -3 dB coupling f actor ensures greater than 1 re lative bandwidth. The measured

PAGE 67

67 results verify the previous balun analysis. The difference between the insertion losses is caused by the quasi TEM mode propagati on. The designed balun assumes a homogeneous media which can support pure TEM propagation. However, th e actual fabricated structure is not a homogeneous media so that an insertion loss difference arises. Also, at higher frequencies, another propagation mode TE0 or TM0 arises. This causes the glitch in the insertion loss response around 90GHz. Figure 4-13. Measured results of Marchand balun integrated probe. A B Figure 4-14. Comparison between the measured and simulated results of Marchand balun integrated probe A) Insertion loss B) Phase Difference

PAGE 68

68 Figure 4-14 compares the measured and simula ted results through the specified frequency range. The insertion loss responses show differences at higher frequencies. This phenomenon comes from the other propagati on mode excitations such as TE0 and TM0. The HFSS simulation is performed for low order propagation modes which only consider TEM mode propagation. However, the measured response can be compensa ted through a cal ibration procedure [4.2]. The phase response shows good agreement between the measurement and simulation. 4.6. Conclustion In this chapter, the Marchand balun integr ated probes are designed, fabricated and measured based on a proposed Marchand balun an alysis presented in chapter 3 and on the coupled line parameter analysis in Appendix A. The parameter extraction method in Appendix A suggests a closed form equation which is different from the general EM solver solution. Typically, an EM solver use Finite-Difference Time-Domain (FDTD) method or Finite Element Method (FEM) which are solving huge mesh equation to find the differentia l equation solution. However, the proposed method in Appendix A uses the closed form equation and saves simulation time dramatically while providing an accurate solution. Measured results and simulated results agree very well as sh own in this chapter. Through the proposed design method, the design accuracy a nd time will be greatly enhanced compared to a trial and error simulation method. Figure 415 summarizes the balun design method using a flow chart.

PAGE 69

69 Figure 4-15. Flow chart of th e Marchand balun design methods.

PAGE 70

70 CHAPTER 5 MARCHAND BALUN INTEGRARTION USING BROADSIDE COUPLED COPLANAR WA VEGUIDE 5.1. Broadside Coupled Coplanar Waveguide (CPW) 5.1.1. Introduction to Coplanar Waveguide (CPW) The physical realization of a c oplanar waveguide is shown in Figure 5-1. This transmission line was first studied by C. P. Wen [5.1]. CPW is a full planar transmission line since in contrast to the microstrip case, there is no bottom ground conductor. Later, coplanar waveguide with the case of a bottom ground conductor was studied. As shown in Figure 5-1, this transmission line is composed of a central conductor of width w separated from two latera l conductors by a distance s called the slot. All th e conductors of thickness t are placed on a dielectric slab of height h and dielectric and magnetic constant r and r. Figure 5-1. Coplanar strips tr ansmission line structure [5.2].

PAGE 71

71 Coplanar waveguide has a zero cut-off frequency, but its lo w order propagation mode is quasi-TEM because it is not a pure TEM mode. However, the error made in evaluating the fundamental propagation mode as a pure TEM is negligible for fr equencies up to some tens of GHz [5.3][5.4].[5.5]. After this limit, disper sion occurs and the propa gation mode gets into nearly TE0 with the magnetic field elliptically polarized along the longitudinal planes. Since the electric and magnetic field in the air is larger than in the microstrip, the effective dielectric constant of CPW generally is lower than that of microstrip. Consequently, the achievable characteristic impedance is higher than the micros tip value. A coplanar waveguide, together with microstrip, is studied to a great extent due to its quasi-TEM propagati on mode and its planar structure [5.6][5.7][5.8][5.9]. 5.1.2. Broadside Coupled Coplanar Waveguide (CPW) with finite ground plane. Many active and passive circuits can be in tegrated on relatively small IC area. The designer usually uses lumped-element counter part s of transmission line based circuits such as 3dB coupler, branch line couplers and baluns due to their compact ness. As RF circuit operation frequency goes higher, the tran smission lines area gets smaller. Therefore, many studies have done to integrate transm ission-line-based passiv e circuits on-chip. In spite of these all contributions, many passive circuits still model limitation due to the lack of a ground plane. Specially, the coplanar waveguide needs a ground plane on the same plane as the signal. For 60GHz circuits, the wavelength will be 5mm. In or der to consider the ground as infinitely wide, the ground plane width should be at least g/5 (=1mm) wide [5.10]. This consumes a huge area in the chip environment. Unless the ground plan e is considered as infinitely wide, the conventional analysis will not be matched to realit y due to the field distor tion, caused by the lack of a very wide ground plane.

PAGE 72

72 Figure 5-2. Cross-section of a br oadside coupled coplanar wavegui de with finite ground plane. Figure 5-2 describes the finite ground broadside coupled coplan ar waveguide. In order to extract the characteristic parameters for designi ng a balun, a new analytic expression for the broadside coupled CPW with finite ground plane is presented for the first time. The detailed derivation procedure and equations are in Appendix B. This method can be used for transmission line circuit modeling in a standa rd CMOS process due to its simplicity. In this section, numerical simulation results are used for designing a 90GHz Balun. 5.2. Analysis of Broadside Coupled Coplanar Waveguide (CPW) 5.2.1 Even Mode The effective dielectric consta nts and the characteristic impe dance are derived as equation 5-1 and 5-2. )( )( )( )( )( )( 1 )( )( 1 12 2 1 1 3 3 2 1 1 1 e e e e e e r e e r EeffkK kK kK kK kK kK kK kK (5-1) )( )( )( )( 602 2 1 1 0 e e e e Eeff EkK kK kK kK Z (5-2)

PAGE 73

73 2 2 2 2 2 2 2 2 2 2 3 22 22 2 1 2 1 2 1 2 1 2 1 1 12 sinh2 sinh1 2 sinh2 sinh1 2sinh 2sinh 1 1 2 sinh2 sinh1 2 sinh2 sinh1 2sinh 2sinh hc ha hc hb hb ha k ca cb b a k hc ha hc hb hb ha ke e e (5-3) where K(k) is the complete elliptic integr al of the first kind with module k and K(k') its complement. The asymptote of these equations when the ground plane width grows infinite ( c ) agrees with the infinite ground plane case [5.2]. 5.2.2 Odd Mode The effective dielectric consta nts and characteristic impeda nce are given in equation 5-4 and 5-5. )( )( )( )( )( )( )( )( 1 )( )( )( )( 1 12 2 2_1 2_1 1_1 1_1 3 3 2 2_1 2_1 1_1 1_1 1 o o o o o o o o r o o o o r OeffkK kK kK kK kK kK kK kK kK kK kK kK (5-4) )( )( )( )( )( )( 1 602 2 2_1 2_1 1_1 1_1 0 o o o o o o Oeff OkK kK kK kK kK kK Z (5-5) where

PAGE 74

74 33 22 1 31 1 41 2_1 1 4 1 2 1_12 tanh 2 tanh 1 2 tanh 2 tanh 1eo eo o okk kk H WW H WW k H W H W k (5-6) W1, W2, W3, W4 and H1 can be derived. 2 2 tanh 2 tanh arcsin 2 tanh 2 tanharcsin )( )(32 4 1 1 1 3 1 1 1 2 1 1 1 1WW W k h c h b FW k h c h b FW kK kK H Wo o o o (5-7) where F(, k) is the incomplete elliptic integral of the first kind, written in Jacobis notation. The expression derived in this section can eas ily be extended to include infinite ground broadside coupled CPW. 5.3. Numerical Results of Broadside Coupled Coplanar Waveguide (CPW) A even and odd mode characteristic impedance were calculated and compared in order to examine variations of signal line width, slot width, ground width and board dielectric constants. By extracting the even a nd odd mode characteristic impedance, the coupling factor can be easily determined. The coupling coefficient specification is essential for couplers, filters, transformers and baluns, using coupled line structures.

PAGE 75

75 The analysis was verified with the aid of Matlab. Figure 5-3 shows even and odd mode characteristic impedances with a fixed dielec tric height ( h1 = 10 um and h2 = 15 um ) on a polyimide substrate (r = 3.5). As the slot width get larg er with the fixed ground width (50 um ), the characteristic impedance gets higher since the effective dielectric constant get lower because the field distributes less extensively. Figure 5-3. Calculated even and odd mode characteristic impedance with the slot width variation as a function of signal line width wh ile the ground plane is fixed at 50 um Figure 5-4 shows the characteristic impedance variation depending on ground width change while the slot width is fixed at 10 u m with a fixed dielectric height ( h1 = 10 um and h2 = 15 um ) on polyimide substrate (r = 3.5). For an even mode ex citation, the characteristic impedance shows a bigger change than for the od d mode excitation because the electric field distributes more between the signa l lines. The odd mode characteristic impedance is less affected since the ground width variation a ffects more the horizontal field distribution than the vertical field distribution. However, the coupling factor tends to change much rapidly than the variation

PAGE 76

76 rate of the even and odd mode characteristic impedance. The odd mode characteristic impedance will change to be larger if the signal line is on an inhomogeneous media. By increasing c to infinity, the equations for the finite ground broadside coupled CPW convert into the equations of the infinite ground broads ide coupled CPW [5.10]. Figure 5-4. Calculated even a nd odd mode characteristic impeda nce as a function of signal line width ( a ) with 20mm finite slot width. Figure 5-5 describes the coupli ng factor variation depending on slot width variation for the ground widths that are 100 um and the infinite ground width case. Slot width affects the coupling factor dramatically. By simple comparison betw een the finite ground width and infinite ground, Figure 5-5 displays the importance of the finite ground width analysis.

PAGE 77

77 Figure 5-5. Calculated coupling f actor with slot width variation as a function of signal line width for the cases of 100 um finite ground plane and infinite ground. Table 5-1. Numerical and si mulated coupling coefficients Signal widhth (2 a ) Gap width ( b-a ) GND width (c-b ) Numerical result (dB) Simulated result (dB) 100 um -4.757 dB -4.627 dB 30 um -5.704 dB -5.604 dB 100 um -3.129 dB -3.0235dB 30 um 70 um -3.807 dB -3.7012 dB 100 um -3.708 dB -3.4836 dB 30 um -4.237 dB -4.1223 dB 100 um -2.442 dB -2.2295 dB 50 um 70 um -2.836 dB -2.726 dB 100 um -3.06 dB -2.8692 dB 30 um -3.418 dB -3.2188 dB 100 um -2.02 dB -1.952 dB 70 um 70 um -2.295 dB -2.182 dB

PAGE 78

78 Through this analysis, the coupling coefficien t for the Marchand balun is extracted and verified with 3D-EM simulator which uses th e Finite Element Method (FEM). The simulation results are based on the frequency so that the co upling coefficients are chosen by the best value through all the specification frequency respons es. Table 5-1 compares the numerical and simulated results of broadside coupled coplanar waveguides. Si mulated results and numerical results show less than 0.2dB difference. Howeve r, the simulation takes a lot longer time than numerical results due to the complex mesh equa tions. The proposed equation saves the time and effort for finding initial design parameters. 5.4. Marchan Balun Implementation The basic parameters were extracted from the analytic expression in a similar manner in the chapter 4. The characterist ics of these broadside coupled line CPW does not affect on the frequency variation as long as the coplanar line works in the quasi-TEM mode. Generally, CPS and CPW can sustain the normal operation wit hout serious loss up to 220GHz. Also, the dispersion of these CPS can be ignored due to a relatively thick metal layer. Rough calculation shows 200nm of skin depth in 100GHz operation. But this process metal thickness is around 5um. The broadside coupled CPWs qua rter wavelength is around 500u m in 60GHz operation, which is verified through HFSS simula tion. The baluns were integrat ed on a Cascade probe structure (GSSG with 150um pitch). This th in film process has relatively large process variation, especially in dielectric thickness. A general appli cation of this process is the integration of the single or parallel coupled transmission lines with a lower ground plane. So, the ground of this process can not be considered as infinite ground due to the fact that there is no shielding or housing. The basic design parameters were extracted from the finite ground broadside coupled CPWs analytic expression. The final design verifi cation was performed with the aid of HFSS. In order to check the effect of the coupling coeffi cient variation in chapter 3, the baluns were

PAGE 79

79 fabricated in 30, 50 and 70 um coupled line widths with a 50 um gap width between the signal line and the ground. 5.4.1 The Design Verification using HFSS Figure 5-6 shows the schematic diagram of th e Marchand balun using a broadside coupled CPW with a finite ground. An unbalanced port c onnects with coaxial cable for the connection to the test equipment while balanced ports touch th e DUT with sharp probe tips. For an accurate measurement, the calibration is essential. The final verification was performed as close as possible to the actual environment, which means that air encloses this structure. The air region is set up as a radiation boundary in simulation. Figure 5-6. Marchand balun integr ated probe structure using fi nite ground broadside coupled lines Figure 5-7 shows the simulation results. The results include the insertion loss (S21 and S31) and the phase imbalance which are the most useful parameters to check the balun performance.

PAGE 80

80 Compared to CPS cases, CPW shows better symme tric characteristic due to its symmetric ground plane at both sides. Figure 5-7. Marchand balun structure usi ng finite ground broadside coupled lines 5.4.2. Layout Layouts of the Marchand balun integrated pr obe using broadside coupled CPW are shown in Figure 5-8. In an actual layout, the ground plane shape varies in order to fit the design into the original GSSG (150 um pitch) probe structure. For a 70 um signal line design, the gap width becomes small. The design of 30 um of the signal line width facilitates a -4.8 dB coupling coupler to get the best center freq uency performance. The designs of 50 um and 70 um signal line widths result from considering the process va riations. These two designs show around 3 dB and 2.5 dB coupling effects through the previous an alysis. The connections to both DUT and COAX use 50 microstrip lines for easy assembly. Layout was performed with L-Edit.

PAGE 81

81 Figure 5-8 Actual layout of Marchand balun integrated probe using broadside coupled CPW. Table 5-2 summarizes the fabric ated design parameters. Tran smission line width variation is to verify the width of the 50 transmission line. The characte rization is performed for one design due to the expensive probe prototyping expenses such as high frequency coaxial cable, probe tips connection etc. For one, at least two prototype designs are a ssembled to provide the measurement accuracy. Table 5-2. Design parameter of th e fabricated balun probe membrane Signal Width Slot Width Transmission Line Width Tested Structure 25 um X 30 um 50 um 45 um X 25 um O 50 um 50 um 45 um O 25 um X 70 um 50 um 45 um X

PAGE 82

82 5.5. Measured Results Measurement is performed by the same method in chapter 4. The tested structure is the fabricated balun integrated probes whos e signal line width, slot width are 50 um and 50 um As shown in Figure 5-8, the integrat ed area is relatively small so that the ground width should be varied at specific location. A full wave simula tor helps to compensate this discontinuity and helps to consider the transmission line transitions. Figure 5-9. Measured results of Marchand balun integrated probe. Measured results shows rela tively good phase balance ra nging through all measured frequencies. Insertion losses (S21, S31) from unbalanced to balanced port show a little deviation up to 90GHz and show a relatively large di fference at 100GHz. Even though the balun is designed with a 60GHz center frequency, the m easured center frequency is around 55GHz. Since the CPW uses twice the ground pl ane of the CPS, the unwanted parasitic capacitance causes the frequency shift. This effect is similar to capacitive loading. If the balanced port connects to a

PAGE 83

83 capacitor such as large DUT pad, this capacitor cincreases the el ectrical length of the coupled line. So the electrical length can be considered longer than the original design in this case. The relative bandwidth can be calculated by si mply adapting the frequency at -4dB with center frequency. In this case, f1, f2 and f0 are equal to 20GHz, 90GHz, and 55GHz, respectively. 21 0Relative Bandwidth=1.273ff f (5-8) The homogeneous media which enhance the couple d line directivity a nd the tighter coupling factor cause this relatively wide bandwidth. This balun uses around a -2.5 dB coupled line to increase the bandwidth. A B Figure 5-10. Comparison between the measured and simulated results of Marchand balun integrated probe A) Insertion loss B) Phase Difference Figure 5-10 shows the comparison between the m easured results and simulated results. The measured results show wider bandwidth than th e simulated one does. Also, the measured and simulated S21 show a similar glitch around 80 GHz due to the introduction of another propagation mode than TEM mode. The copl anar waveguide shows a better symmetric characteristic around the center frequency than the coplanar stripline case. Generally, CPW

PAGE 84

84 sustains TEM propagation mode better than C PS does due to its symmetric ground plane. The phase response shows stable behavior in the interested frequency range. 5.6. Conclustion The Marchand balun integrated probes using broadside coupled coplanar waveguide are designed, fabricated and measur ed. The design parameters are determined by the proposed balun analysis in chapter 3. With the proposed pa rameter extraction method in Appendix B, it is possible to make a simple and accurate Marcha nd balun. A 3D EM simulator is employed to consider the discontinuity between the transmission lines for the final function verification. The measured results show a good agreement to the final simulation.

PAGE 85

85 CHAPTER 6 EMBEDDED PHASE NOISE MEASUREMENT SYSTEM 6.1. Introduction to Phase Noise Frequency sources include noise that appears to be a superposition of causally generated signals and random, nondeterministic noise. Thermal noise, shot noise, and noise of undetermined origin (such as f licker noise) are considered to be the random noise. The final result is time-dependent phase a nd amplitude fluctuations in the frequency source. Measurements of these fluctuations characterize the frequenc y source in terms of amplitude modulation (AM) and phase modulation (PM) noise. Frequency stability can be defined as the de gree to which an oscillating source produces the same frequency throughout a specified peri od of time. Every RF and microwave source exhibits some amount of freque ncy instability. This stability can be divided into two componentslong-term and short-term stability. It is implicit in this general definition of frequency stability that the given frequency stability decreases if anything except a perfect sine function is the signal wave shape. Long-term stability describes the frequency variations that occur over long time periods, expressed in parts per million per hour, day, month or year. Short-term frequency stability contains all elements causing fr equency changes about the nominal frequency of less than a few seconds duration [6.1]. Phase noise is the term most widely used to describe the characteristic randomness of frequency stability. The spectral pu rity refers to the ratio of si gnal power to phase-noise sideband power. Measurements of phase noise and AM noi se are performed in the frequency domain using a spectrum analyzer that provides a frequency window followi ng the detector (double

PAGE 86

86 balanced mixer). Frequency stability can also be measured in the time domain with a gated counter that provides a time window following the detector. Mathematically, an ideal si newave can be described by 0()sin2cVtVft (6-1) where V0, 2 fct and fc are nominal amplitude, linearly gr owing phase component and nominal frequency, respectively. However, a real signal is better modeled by 0()()sin2()cVtVtftt (6-2) where (t) and (t) are amplitude fluctuations and randomly fluctuation phase terms (phase noise) [6.2]. Figure 6-1. RF sideband spectrum from spectrum analyzer with deriving L(fm). This randomly fluctuating phase terms could be observed on an ideal spectrum analyzer (one which had no sideband noise of its own) as shown in Figure 6-1. There are two kinds of

PAGE 87

87 fluctuating phase terms. The deterministic term s are discrete signals appearing as distinct components in the spectral density plot. These si gnals which usually are called spurious, can be related to known phenomena in the signal source such as power line frequencies, vibration frequencies, or mixer products. The second kind of phase instability is random in nature, and is commonly considered as phase noise. The source of random sideband noise in an oscillator includes thermal noise, shot noise, and flicker noise. Many terms exist to quantify the characteristic randomness of phase noise. Essentially, all methods meas ure the frequency or phase devi ations of the source under test in either the frequency or time domain. Since freq uency and phase are related to each other, all of the terms that characterize ph ase noise are also related. One fundamental description of phase instabi lity (phase noise) is the spectral density of phase fluctuations on a per-Hertz basis. The spec tral density defines the energy distribution as a continuous function, expressed in units of phase variance per unit bandwidth. Thus S(fm) may be considered as 2 2 rms() () used to measure rmsm mf rad Sf B WH z (6-3) where BW(bandwidth) is negligible with respect to any changes in S versus the Fourier frequency or offset frequency fm. One of useful measure of noise energy is L(fm), which is then directly related to S(fm) by a simple approximation which has generally negligib le error if the modula tion sidebands are such that the total phase deviations are much less than 1 radian (pk 1 radian). () () 2m mSf fL (6-4)

PAGE 88

88 L(fm) is an indirect measurement of noise en ergy related to the RF power spectrum which is observed on a spectrum analyzer Figure 6-1 shows that the U.S. National Bureau of Standards defines L(fm) as the ratio of th e power in one phase modulati on sideband to the total signal power (at an offset fm Hertz away from the carrier). The phase modulation sideband is based on per Hertz of bandwidth spectral density and fm equals the Fourier frequency or offset frequency. power density (in one phase modulation sideband) () total signal power single sideband (SSB) phase noise to carrier ratio per Hzssb m sP f P L (6-5) Phase noise generally uses the logarithm as a spectral density of the phase modulation sidebands in the plot of the pha se-frequency domain, expressed in dB relative to the carrier per Hz (dBc/Hz) as in Figure 6-2. Figure 6-2. L(fm) which is described logarithmically as a function of offset frequency. The spectral density of frequency fluctuations ( Sf( fm)) is also used for quantifying short term frequency instability (phase noise).The spec tral density defines the energy distribution as a continuous function, expressed in units of fre quency variance per unit bandwidth. Equation 6-6 describes Sf( fm).

PAGE 89

89 2 2 rms() () used to measure rmsm fmff Hz Sf B Wf H z (6-6) where BW is negligible with respect to any changes in S versus fm. Frequency is the time rate of change of phase, so that the three common terms ( S( fm), L( fm), and Sf( fm)) have a relationship as s hown equation 6-7 and 6-8. 2() ()fm m mSf rad Sf f Hz (6-7) 2() () 2fm m mSf f fL (6-8) A frequency discriminator outputs a voltage directly proportional to Sf( fm). Sv( fm) is the power spectral density of the vo ltage fluctuations out of the detection system. For small BW, may be considered as shown in equation 6-9. 2 2 rms() () used to measure rmsm vmVf V Sf B WV H z (6-9) Because of the large magnitude variations of the phase noise on an oscillator, it is convenient to talk about phase noise in logarithmic terms. Logarithm expression of Sf( fm) is shown in equation 6-10. () ()20logper Hz 1fmdBHzfHz Sf Hz Hz (6-10) Logarithm expression of S( fm) is shown in equation 6-11. () ()20logper Hz 1mdBr rad Sf Hz rad (6-11) Logarithm expression of L( fm)is shown in equation 6-12.

PAGE 90

90 ()10logper Hznoise m carrierP dBc f HzP L (6-12) Therefore, the relationship between S( fm), L( fm), and Sf( fm) can be described as shown in equation 6-13 and 6-14. () ()()20log 1m mf m f Hz dBrdBHz SfSf HzHzHz (6-13) () 20log-3 dB 1m mf mfHz dBc dBHz fSf Hz Hz Hz L (6-14) where dBHz/Hz is dB relative to on Hz per Hz bandwidth, dBr/Hz is dB relative to one radian per Hz bandwidth, and dBc/Hz is dB rela tive to a carrier per Hz bandwidth [6.2]. 6.2. Phase Noise Modeling of an Oscillator 6.2.1. Basics of Oscillators Figure 6-3. Conventional Os cillator Block Diagram. The basic idea of an os cillator is to convert dc power to a periodic, sinusoidal RF output signal. Though all oscillators need a nonlinear description of their behavior a linear approach is sufficient for their analysis and design. Th e block diagram below includes all necessary components of an oscillator. This block diagram is composed of an amplifier with a frequency dependent gain G(j) and a frequency dependent feedback network H(j) The feedback network is the resonator circuit with quality factor Q The resonating circuit has losses due to the

PAGE 91

91 finite quality factor and can be modeled as a pa rallel RLC resonance circ uit as shown in Figure 6-4 [6.3]. Figure 6-4. Parallel Resonance Circuit. The inductor L and the capacitor C determine the resonance frequency and the resistor R represents the losses in the circuit. The resistor R determines the Q of the resonator. The impedance of the circuit looking at the input port can be described below. 111in Z jC RjL (6-15) The resonance frequency can be established wh en the imaginary part of equation 6-15 is equal to zero. This means that the maximum amount of energy is os cillating between the inductor and capacitor. The osci llation frequency is below. 1c cL C (6-16) and the resonance frequency can be de scribed as shown in equation 6-17. 1cLC (6-17) The Q is defined as the bandwidth of the resonance graph as shown in Figure 6-5. The Q for a resonator with losses described by the resistance R can be modeled as shown in equation 618.

PAGE 92

92 c cR QCR L (6-18) Figure 6-5. Normalized ba ndwidth of a resonator. The transfer function for a conventional oscillator block ca n be derived as () 1()()o inV Gj VGjHj (6-19) For an oscillator, Vo is nonzero when Vin is equal to zero, the os cillation condition can be extracted as shown in equation 6-20 and 6-21. ()()1ccGjHj (6-20) arg()()180ccGjHj (6-21) These magnitude and phase conditions have to be fulfilled to get stable oscillation at the output of the oscillator [6.4]. 6.2.2. Leesons Phase Noise Model Dating back to 1966, D. B. Leeson published a model for describing the output noise behavior of a feedback oscillator. This model is historic but still is in use for estimating the output spectral density of the phase noise of an oscillator. Assuming that the output in Figure 6-4

PAGE 93

93 is the voltage across the tank circ uit, the only source of noise is the white thermal noise of the tank conductance. It can be repres ented as a current source across the parallel resonance circuit with a mean-square spectral density of equation 6-22. 24ni kT f R (6-22) This current noise becomes voltage noise when multiplied by the effective impedance looking into the current source. By considering that the ener gy restoration element must contribute an average effective negative resistance that precisel y cancels the positive resistance of the parallel resonance circuit, the effective im pedance looking into the noise current source is the same as the impedance of a pe rfectly lossless LC network. But at resonance, this is zero. For a relatively small offset frequency from the center frequency c, the impedance of an LC resonance circuit is approximate ly described by equation 6-23. 2c c cL Zj (6-23) By using the definition of quality factor Q the impedance of an LC resonance circuit yields equation 6-24. 2c cZR Q (6-24) Then, the spectral density of the mean-square noise voltage can be obtained by multiplying the spectral density of the mean-square noise current with the squared magnitude of the impedance of an LC resonance circuit. 2 22 24 2nn cvi ZkTR ffQ (6-25)

PAGE 94

94 The power spectral density of the output noise is frequencydependent. This 1/ f2 behavior represents the two facts. The fi rst is that the voltage frequency response of an LC resonance circuit rolls off as 1/ f to either side of the center frequency. The second is the power is proportional to the square of voltage. An increase of an LC resonance circuits Q reduces the noise density with all other pa rameters constant [6.5]. Thermal noise causes fluctuations in both amplitude and phase as shown in equation 6-25. Noise energy would split equally into amplitude and phase noise without amplitude limiting that occurs in real circuits. However, amplitude lim iting mechanisms are present in all practical oscillators so that the amplitude noise will be attenua ted. In order to quantify this noise level, it is conventional to normalize the mean-square noise voltage density to the mean-square carrier voltage in decibels. This nor malization expresses the follo wing phase noise equation. 22 ()10logper Hz10log 2noise c m carrier carrierP dBc kT f HzP PQ L (6-26) However, equation 6-26 requires many simplifying assumptions so that there are some significant differences between the spectrum by equa tion 6-26 and the real oscillator spectrum. To solve this discrepancy, a modification to equation 6-26 is shown in equation 6-27. [6.5]. 32 1/2 ()10log11 2f c m carrierdBc FkT f HzPQ L (6-27) These modifications consist of a factor F to account for the increased noise in the 1/( fm)2 region, an additive factor of un ity to account for the noise floor, and a multiplicative factor to provide a 1/ fm3 behavior at sufficiently small offset fr equency. This modification is described in Figure 6-6.

PAGE 95

95 Figure 6-6. Phase noise: Leeson versus equation 6-26 [6.6]. The Leesons model is extremely important for intuitive insight. However, it should be noted that the factor F is an empirical fitting parameter and must be determined from measurement, diminishing the predictive power of the phase noise equation. Also, the 1/f corner of device noise is not precisely equal to ( fm)1/ f3 in practice. 6.3. Phase Noise Measurement Methods This chapter describes three different met hods for measuring phase noise. The purpose is to show the complexity of the measurement and derive the necessary equation to determine the single sideband phase noise. Finally, the proper method is chosen for an embedded phase noise measurement system. 6.3.1. Direct Measurement The most simple and straightforward method of phase noise measurem ent is to input the test signal into a spectrum analyzer, directly measuring the power spectral density of the oscillator. However, this method may be signi ficantly limited by the spectrum analyzers

PAGE 96

96 dynamic range, resolution, and LO phase noise. Though this direct measurement is not useful for measurements close-in to a drifting carrier, it is convenient for qualitative quick evaluation on sources with relatively high noise The measurement is valid if the following conditions are met. The first is that the spectrum analyzer SSB phase noise at the offset of interest must be lower than the noise of the Device-U nder-Test (DUT). The second conditi on is that since the spectrum analyzer will measure total noise power, the am plitude noise of the DUT must be significantly below its phase noise (Typically 10dB will suffice) [6.2] Figure 6-7 shows a typical display of an osci llator mixed down to DC. The main advantage of this method is its simple test set-up and that it can measure phase noise at high offset frequencies from the carrier. However, there are several disadvantages. One is that the spectrum analyzer can not distinguish a difference between amplitude noise and phase noise when one does not have any idea regarding the noise power in the amplitude and phase of a DUT. Finally, some correction factors have to be incorporated in order to co mpensate the phase noise power since the phase noise power is norma lized to a bandwidth of 1Hz in an ideal rectangular filter but the resolution bandwidth filter of the spectrum analyzer is non-ideal. Figure 6-7. SSB phase noise w ith direct measurement method.

PAGE 97

97 6.3.2. PLL-based Measurement (Two oscillator method) The PLL-based method is the most sensitive of all methods. Two oscillators send signals to the two RF ports of a mixer. The IF signal of a mixer passes through a low pa ss filter to keep out the sum frequency components and then sends them back in a small bandwidths signal to lock one oscillator to the othe r. The fundamental block diagram is shown in Figure 6-8. The basis of this method is the double-balanced mi xer is used as a phase detector. Figure 6-8. Basic diagra m of PLL-based phase noise measurement system Two signals at identical frequencies a nd nominally in phase quadrature (90 out of phase) are input to the phase detector (double balanced mixer). At quadr ature, the output of the phase detector is a difference frequency of 0 Hz and an average voltage output of 0 V There is a small fluctuation voltage, V For small phase deviations ( << 1 rad), this fluctuating voltage is proportional to the fluctuating pha se difference between the two signals. This phase difference represents the combined phase modulation sidebands of the two input signals. When the two input signals are identical in frequency and in phase quadrature, the output of the phase detector is a voltage directly proportiona l to the combined phase modulation sidebands of the two input signals. The frequency and amplitude offsets are then removed such that the two input signals are again at identical frequencies, and are set in phase quadrature. It is importa nt to use the mixer in

PAGE 98

98 its linear region where the voltage output is di rectly proportional to the phase difference of the input signals by a constant A as shown in equation 6-28. Figure 6-9 shows a typical mixer-phase dete ctor characteristic. The mixer produces a output voltage V ( t ) proportional to the fluctuating phase difference between the two input signals LORF. The point of maximum phase sensitivity a nd the center of the region of most linear operation occur where the phase difference between the two inputs is equals to 90 or phase quadrature. Figure 6-9. Conventional double-ba lanced mixer characteristic. In order to understand how a mixer operates as a phase detector, we need examination of a normal mixer output as shown in Figure 6-9. Figure 6-10. Mixer operation

PAGE 99

99 The output of the mixer VIF(t) is the product of the two signals. cos cos ...IF d rd r rdVtAVttAVtt (6-28) The low pass filter will remove the higher frequency components, leaving V(t) cosdrdVtAV tt (6-29) Let the peak amplitude of V(t) be defined as Vb,peak(peak voltage of the be at signal), equal to AVd, where A is the mixer efficiency. ,cosbpeakrdVtV tt (6-30) When operating the mixer as a phase detector, the input signals must be at the same frequency and 90 degrees out of phase. and 1, 1,2,3.... 2drtktk (6-31) The output of the mixer at quadrature is expressed by ,,sin for 1 radianbpeak bpeak peakVtVtVt (6-32) where V(t) is instantaneous voltage fluctuations around 0 V, and (t) is instantaneous phase fluctuations. This yields a direct linear re lationship between the voltage fluctuations at the mixer output and the phase fluctuations of the input signals. mVK (6-33) where Km=Vb,peak= mixer constant(volts/radian), which is equal to the slope of the mixer sine wave output at the zero crossings. The voltage output of the mixer as a function of frequency will be dir ectly proportional to the input phase deviations.

PAGE 100

100 ,2mb r m sVfKfVf (6-34) Then, rms( f ) measured on the spec trum analyzer is, 2 2bandwidth used to measure rms rmsrad Sf Hz (6-35) Therefore, 2 2 2 ,1 in 1 Hz measurement bandwidth 2 rms rms brmsV Sff V (6-36) The final phase noise equations is below 2 2 ,11 in 1 Hz measurement bandwidth 24 rms brmsV fSf V L (6-37) In this measurement method, the phase qua drature is the point of maximum phase sensitivity and the region of most linear operati on. Any small deviation from quadrature results in a measurement error. Table 6.1 shows the typical error table of PLL based phase noise measurement system (Agilent 11729B phase noise measurement system) [6.7],[6.8]. Table 6-1. Error contribution to the measurement Offset from quadrature Measurement Error 1 -0.001dB 3 -0.01dB 10 -0.13dB The PLL-based method has several advantages and disadvantages. A smaller spectrum analyzer dynamic range is necessary after converting the RF signal to the baseband signal.

PAGE 101

101 The internal noise of the spectrum analyzer is not the limiting factor. A low noise preamplifier is used to amplify the baseband signal to meet the range of the spectrum analyzer. The mixer operating as a phase detector is suppressing the amplitude noise due to its quadrature input condition in this setup. G ood mixers achieve an AM noise suppression from 30~40dB. The measurement result is 3dB higher for the case of two identical sources, since the DUT and reference have the same characteristic. The reference source is a high stab le oscillator that is the lim iting factor of the test setup. The only disadvantage is the need for two sources in this test setup. 6.3.3. FM Discriminator (delay-line based) Measurement (One oscillator method) It is important to first identify the two type s of noise present in a frequency source: AM noise and phase noise. Phase noise, generally co nsidered to be the dominant form of random noise, is defined as the noise generated from ra ndom fluctuations in the phase of a frequency source. AM noise is simply the noise generated from random fluctuations in the amplitude of a frequency source. Delay line discriminators are only capable of measuring phase based random noise, and are in fact insensitive to AM noise. This can be an important advantage when measuring the phase noise of sources which do have significant AM noise. Unlike the PLL based method, a frequency disc riminator method (delay line method) does not require a second reference signal phased lo cked to a DUT. This makes the frequency discriminator method extremely useful for measur ing DUTs that are difficult to phase lock. It can also be used to characterize sources with high -level, low-rate phase noise, or high close-in spurious sidebands, which can impose seri ous problems for the PLL based method.

PAGE 102

102 The delay line implementation of the fre quency discriminator converts short-term frequency fluctuations ( f ) of DUT into voltage fluctuations ( V ) that can be measured using a baseband analyzer. The conversion is two part process, first converting the frequency fluctuations into phase fluctuations and then converting the phase fluctuations to voltage fluctuations as show n in Figure 6-11. Figure 6-11. Basic delay line fr equency discriminator method The frequency fluctuation to pha se fluctuation transformation ( f ) takes place in the delay line. The nominal frequency arrives at the d ouble-balanced mixer at a particular phase. As the frequency changes slightly, the phase shif t incurred in the fixed delay time will change proportionally. The delay line converts the frequenc y change at the line i nput to a phase change at the line output when compared to the un-de layed signal arriving at the mixer in the second path. The double-balanced mixer transforms the instantaneous pha se fluctuations into voltage fluctuations ( V ). With the two input signals 90 out of phase, the voltage output is proportional to the input phase fluctuations [6.2]. In order to understand th e function of the delay line as a discriminator, let us investigate the process of differentiation implemented by a time-delay line as shown in Figure 6-12. The signal y(t) which is the input to the output, is given by equation 6-38.

PAGE 103

103 Figure 6-12. Discriminator implem entation using time delay [6.9] ()()rrytxtxt (6-38) which can be written ()()rryt xtxt (6-39) Since, by definition, 00()()() limlimrrryt x txtdxt dt (6-40) it follows that for small ()rdxt yt dt (6-41) Through the delay-line discriminator, the voltage fluctuations can then be measured by the spectrum analyzer and converted to phase noise units. The output voltage of DUT is in equation 6-42. ,cosoutDUTmVtVtt (6-42) The signals passing the delay line and phase shifter are shown in equation 6-43 and 6-44 under the assumption that the amplitude fl uctuation is negligibly small. ,_cosoutdelayline Dm d dVtAVtt (6-43) ,_cosoutphaseshifter PmVtAVtt (6-44)

PAGE 104

104 After mixing the two signals, the output is the multiplied form of the two signals. After traveling through a low pass filter the higher order term is removed. By use of a quadrature monitor, (0d-) can be adjusted to 90. Then the final form can be derived as shown equation 6-45: 2cos cos cos coscos sinsin sin sin sinoutPDmm d d dd dddd dd dVtAAAVtttt Ktt Ktttt dt KttK dt Kt 2ddKtKft (6-45) With the assumption that f is zero-mean random signal, the mean square value of Vout is below: 22 22 22 ,,22outrms drms outrmsm drmsmVtKftVfKff (6-46) The power spectral density of the frequency noise is below: 2 22 222 2 2 222 2 2 22rmsm outrmsm drmsm dm m dmm f f VfKffKf f Kff L (6-47) Finally, the power spectral density of the phase noise is described in equation 6-48. 2 2in 1 Hz measurement bandwidth 22outrmsm m mdVf f KfL (6-48) The system sensitivity is closely related to delay time as shown in equation 6-48. As the delay time increases, the sensitivity is better. In order to get a proper sensitivity, the delay line should be long enough since the delay time is inve rsely proportional to the phase noise [6.10] [6.11].

PAGE 105

105 6.4. Embedded Phase Noise Measurement System The delay-line based phase noise measurement method is implemented as the embedded phase noise measurement system on standard CMOS thanks to its simple structure compared to PLL-based system. Building a PLL for the phase noise measurement is considerably more difficult due to the considerations of locki ng range and large area system components. However, there are two possible methods to im plement a delay line technique. One is that the delay line and phase shifter use separate signal paths. Another is that the delay line and phase shifter use the same signal path. The two possi ble implementations share the same frequency discriminator transfer response as long as the syst em uses a passive delay line and a phase shifter, which do not generate additional noise for the whole system. However, if one converts the passive elements into a system with active elements, the two possible implementations show a different system noise floor. By considering the system noise analysis of the two possible frequency discriminator system implementations, the proposed embedded phase noise measurement system will be design as the superior configuration. 6.4.1. FM discriminator system noise analysis Figure 6-13. Linearized noise model of a delay li ne frequency discriminator method in case that the delay line and phase shifter share the same signal path.

PAGE 106

106 V2 n,out can be derived by independently su mming up the different noise sources. V2 n,out is located right after low pass filter. 2222222 ,,,, noutnMIXsmixerPSnDLYnPSVvVKKvv (6-49) where Vs is the amplitude of DUT generated signal. The resulting system noise floor can be described as equation (6.50). 2 system 2 222222 ,, 2 2 222 ,, 2 2222 22 1 22noutm m mmd nMIXsmixerPSnDLYnPS mmd nMIX PSnDLYnPS smixer mdVf f Kf vVKKvv Kf v Kvv VK f L (6-50) where Km=VsKmixerKPS is the overall system gain, Kmixer is the mixer gain and KPS is the phase shifter gain. Figure 6-14. Linearized noise model of the de lay line frequency discriminator method in case that the delay line and phase shif ter use different signal paths. V2 n,out can be derived by independently su mming up the different noise sources. V2 n,out is located right after low pass filter. 222222 ,,,, noutnMIXsmixernDLYnPSVvVKvv (6-51)

PAGE 107

107 where Vs is the amplitude of DUT generated signal. The resulting system noise floor can be described as equation 6-52. 2 system 2 22222 ,, 2 2 22 ,, 2 2222 22 1 22noutm m mmd nMIXsmixernDLYnPS mmd nMIX nDLYnPS smixer mdVf f Kf vVKvv Kf v vv VK f L (6-52) where Km=VsKmixer is the overall system gain, Kmixer is the mixer gain. Equation 6-52 will show lower noise floor than equation 6-50. The multiplication of the noise signal power can reduce the overall noise power compared to the sum of noise signal power with cross-correlation. Particularly, the proposed system uses an active phase shifter which contains an inherent amplification because the active phase shifter adapts a variable delay line structure based on a differential inverting amplifier. Through the simple noise analysis shown, th e FM discriminator system using different signal paths for the delay line and phase shifter is chosen due to its lower system noise floor compared to the case of using the same signal path. Also, the noise analysis implies system consid eration to reduce the system noise floor. The higher mixer gain reduces the system noise floor as shown in equation 6-52.

PAGE 108

108 6.4.2. Proposed Embedded Phase Noise Measurement System Figure 6-15. Block diagram of the embedded phase noise measurement system The embedded phase noise measurement system adapts to a delay-line based phase noise measurement system in Figure 6-15. The main differ ence is that the delay-line is replaced with a delay cell to get enough delay time and save chip area. The transmission line based delay line might be best for this application. However, the transmission line need s a considerably longer line to achieve greater than 1ns delay time with transmission line such as a coaxial cable or a coplanar waveguide. Also, this long line attenua tes the signal considerably. Also, a lumped element delay cell (i.e. LC ladder filter) also needs several hundred st ages to achieve enough delay time and can add resistive noise. Particularly, a LC ladder filter has a cutoff frequency which is relatively small compared to transmission line. Lower cutoff frequency achieves a bigger delay per stage for the LC ladder filter but the delay time per stage will still be considerably short for this application. By cons idering chip area and achievable delay time, the differential inverting amplifier is chosen for the delay cell circuit. However, the delay cell circuit

PAGE 109

109 uses active devices which are different from tran smission line or LC ladder network. Therefore, the active device noise contribu tion should be considered fo r the system operation. A phase shifter also can be designed as a lumped-element structure with variable capacitance. A lumped-element phase shifter is fixed at a narrow opera tional frequency and has very limited phase shift capability. This new system aims to achieve DC~2 GHz oscillator phase noise measurement. Thus, a wide phase shifting abil ity is a key feature so that the phase shifter also is implemented using variable delay cell. In a commercial measurement system such as an Agilent E5500, the phase quadrature is adjusted manually by watching the quadrature mon itor. Thus, this systems accuracy will be degraded due to the inconvenience of adjusti ng a perfect quadrature condition at different frequency measurements. Also, the user should watch the quadrature monitor to control it continually during the measurement. In this work, the system is able to co ntrol the phase quadrature automatically. By comparing the output dc voltage level with its re ference voltage, the adjustment unit controls the phase shifter to maintain the phase quadrature. If the mixer does not operate in phase quadrature, the output signal power is large e nough to make an adjustment at a very small phase discrepancy. The adjustment unit controls the phase shifter (w hich is a voltage contro lled inverting amplifier) depending on the comparator output. 6.5. System Level verification of the Em bedded Phase Noise Measurement System In order to verify the system functionality, a system level simulation is performed with Agilent ADS. The purpose of this effort is to verify the embedded phase noise measurement system. A DUT generates a noisy signal (white noise) at a specific frequency. A delay line (which will be implemented by the CMOS delay cells) and phase shifter generate the planned time delay (which is phase shift at both output s) and time delayed signal. The mixer works like

PAGE 110

110 analog multiplier to function as a phase detector. A final active low pass filter filters out higher order signals with specific gains. The remaini ng signal is located at DC with a noisy sideband which is similar to the baseband signal. Therefore, the simulation focuses on exploring this noise sideband. In actual circu itry, this signal is detected as voltage components in time domain. In order to see the noise sideband, a Fourier Transf orm (FFT or DFT) which consists of an Anologto-Digital Converter and a DSP module, should fo llow. In this simulati on, a spectrum analyzer block replaces these complex blocks. Figure 6-16. System level verification of the proposed phase noise measurement system in Agilent ADS. Figure 6-16 shows the simulated system bloc k. In this simulation, an auto-phase quadrature adjustment block is omitted for simplic ity. In order to check the response accuracy, a single-tone FM signal with thermal noise is gene rated in simulation to represent a noisy source. Therefore, the final output sp ectrum only contains the 1/ f2 noise region due to the absence of the flicker noise contribution. Conceptually, the device flicker noise contributes the close-in phase noise (1/ f3 region) which is at very lo w frequencies. So, in this sy stem simulation, the close-in

PAGE 111

111 noise can not be shown. Simulations are performe d from a 0.5 GHz carrier frequency to a 2 GHz carrier frequency. As expected, the final out put signals are almost same because the same random noise is added to a pure sinusoidal sour ce. Spectrum analyzer will show the output noise spectrum. The final phase noise spectrum is described by equation 6-48. The measured noise power must be scaled by several constant fact ors as well as by the square of the frequency, because the display is actually the noise frequency. As a numerical example, let B be 100 Hz (20 dBHz) and k2d is 10-5. Let the power measured over the resolution bandwidth of the spectrum analyzer at 100 kHz be 2 nW (-57 dBm). Then, the phase noise at that 100 kHz offset from the carrier is -110 dBc/Hz. Figure 6-17 describes the response of the pr oposed system. Figure 6-17 A) and B) shows the noisy source signal and th e responses after the system passes through the delay line and phase shifter. In transient simulations, the de lay line output shows the 20ns delayed signal and both spectrums shows almost same response. Fi gure 6-17 C) shows the transient and spectral response of the output signal of the proposed syst em. In time domain, there is the only noisy signal since the mixer cancels out all the signal components by adjusting the input phase quadrature. In the transient simulation, the noise is scaled up to properl y display it. As shown Figure 6-17 C), the spectrum shows the output no ise voltage which should be converted into phase noise representation through equation 6-48 called calibration. Figure 6-17 D) shows the phase noise response by equati on 6-53 which is same as equation 6-48 except in dB representation. In equation 6-53, B represents noise bandwidth which is decided by spectrum analyzers resolution bandwidth. ()20log220log310log() mvm dm f SfK fBL (6-53)

PAGE 112

112 Figure 6-17. System simulation results of the proposed phase noise measurement system in Agilent ADS: A) input power spectrum B) de lay line and phase sh ifter output C) the system noise output D) the phase noise result.

PAGE 113

113 The final spectrum after calibration process through equation 6-53, shows the expected results in Figure 6-17 D). In this simulation, the added noise power is relatively small which is around -174 dBm, then the final phase noise output shows very low system noise floor. For the calibration, the second term in right-hand side of equation 6-53 can be obtained through the system gain calculation or thr ough the calibration measur ement. The calibration is performed by inserting a single tone FM signal at input, then comparing the output signal with th e input signal. Figure 6-18 shows the calibration procedure. A known single tone FM signal is inserted in input of the system. Then, the output signal shows th e single tone output in spectral domain since the signal is canceled out through th e system. Equation 6-54 through 6-58 shows the derivation of the calibration equation in Figure 6-18 B). This calibration procedure will be applied for the proposed system test. Figure 6-18. Calibration process A) Calibration test set-up B) Calibration equations and calibration results.

PAGE 114

114 2 2 21 44 ; = the peak deviation, = the FM rate of the calibration signalcalpk ssb cal carrier mcal calpk mcalf P S P f ff (6-54) [] 2 2 2 101 210 2calSdB calrmscalpkmcalfff (6-55) 22 2 [] 2 2 10210calrms rms d SdB calrms mcalVV K f f (6-56) [][]([]20log3[])d cal cal mcalKdBPdBSdBfdB (6-57) [/] 20log()310log()mv m dm f dBcHzSfKf B L (6-58) For this example, the value of Kd is -77 dB. The system noise is higher than one in Figure 6-17 D) since the FM modulated signal generates higher noise around th e carrier signal. The system output affects on this high noise compone nts so that the system noise floor goes higher than the case in Figure 6-17 D). Interestingly, only white (thermal) noise is added to the generated signal source so that there is no close-in noise component which shows 1/ f3 slope. 6.6. Conclusion In this chapter, the phase noise definiti on and theoretical bac kground are introduced and the conventional phase noise measurement methods also are explained and compared. By the comparison of the conventional phase noise m easurement systems, the delay line based FM discriminator system is chosen for the embedded phase noise measurement system. The design considerations are investigated through the system noise and performance analysis. In order to achieve the best sensit ivity of the embedded phase noise measurement system, the noise analysis verifies that th e mixer should possess high gain and the system

PAGE 115

115 analysis shows that a longer delay line can redu ce the system noise floor which determines the phase noise measurement system sensitivity. The calibration procedure for the proposed syst em is presented in order to provide the proper test results after the system measuremen t data acquisition. The calibration procedure can save the effort to derive the system gain. By measuring the known single tone FM signal, the system gain can be easily obtained. The next chapter handles the actual system implementation based on the analysis in this chapter using IBM8HP technology.

PAGE 116

116 CHAPTER 7 EMBEDDED PHASE NOISE MEASUR EMENT SYSTEM IMPLEMENTATION 7.1. System Considerations The newly developed phase noise measuremen t system described in this chapter is Frequency Discriminator Phase Noise measurement system. The key issue is that the discrete components in a large circuit breadboard are conv erted into a small integration compatible onchip application. A circuit board -based external discriminator phase noise measurement system, typically, uses passive elements in order not to generate any additional noise in the system; This requires a large test bench and a large circuit area. For example, providing 2 ns of delay requires 40 cm of a standard 50 coaxial cable. When it comes to an on-chip system, it is impossible to implement this long transmission line in a small ch ip area and not have excessive signal losses. With the new circuits shown in this chapter, the passive components may be converted into active circuits. Also, the DUT signal distortion should be minimized throughout the whole onchip system, especially in the delay line and in the phase shifter as shown in Figure 7-1. Figure 7-1. The on-chip phase noise measurement system block diagram.

PAGE 117

117 The next sections explain the new design and the reasons why the spec ific configurations are chosen for the on-chip discriminator noise measurement system. Then, the simulation results characterizing each component are shown. 7.2. System Implementation 7.2.1. Active Balun A single-ended signal is define d as one that is measured with respect to a fixed potential, generally a ground, while a differential signal is defined as one that is measured between two nodes that have equal and opposite signal excurs ions around a fixed potential. An active balun converts a single-ended signal to a differential signal with a 180 phase difference. This is used in the discriminator in order to supply signals for differential system components including the delay line and the phase shifter. The differentia l discriminator circuits have several inherent advantages. An important advantage of the di fferential circuit operation over a single-ended circuits operation is a much higher immunity to environmental noise such as capacitive coupling noise due to adjacent signal lines and same line noise from a noisy power supply. Another useful property of differential circuits is the doubling of maximum achie vable voltage swings. Simpler biasing and higher linearity are ot her advantages of differential ci rcuits over their single-ended counterparts. Differential circuits may occupy twice as mu ch area and consumed twice as much power as their single-ended counterparts, in practice. These are the major drawbacks over single-ended circuits [7.1]. Passive on-chip baluns for RF and microw ave frequencies can consume a large area, especially, at lower frequencies. For this reason, baluns are often realized off-chip, which adds to assembly costs and may degrade the conversion gain or loss. The designer can use transmissionline baluns on-chip, but they are not economically feasible except possibly at very high

PAGE 118

118 frequency (> 60GHz) since their size is proporti onal to wavelength and on-chip thin metal lines have excessive loss when made long. For exampl e, at 60 GHz, a Marchand type balun requires two 500um long directional coupled lines as shown in Chapter 3. In this application, active baluns are emplyed because of their wide-band characteristics in a very small chip area. There are several types of the active balun topologies published [7.2] [7.3 ] [7.4] [7.5]. The simplest active balun is a NMOS transistor with resistors in the drain and source as shown in Figure 7-2 [7.2]. Figure 7-2. Single NMOS balun schematic. The amplitude of the two outputs can be made equal by adjusting, appropriately, the resistance value of the drain and source. Vout1 has a unity gain, ideally, since it is a source follower circuit as shown in equation 7-1. In reality, the gain is about 0.6~0.7. 11 1outmS in mSVgR VgR (7-1) Therefore, a design equation can be easily obtained for the resistors RD and RS, to a first order approximation, in order to achieve an equivalent Vout2 amplitude.

PAGE 119

119 211out mDout in mSinVgRV VgRV (7-2) The negative sign of equation 7-2 indicates that Vout2 space has a 180 phase shift relative to the input, whereas Vout1 has the same phase as the input. This simple structure has a severe limitation during high frequency operation due to the parasitic capacitance associated with the active device. Particularly, the gate-drain parasitic capacitance seriously degrades th e high frequency operation in term s of the Miller effect since the effects of this capacitance are effectivel y multiplied by the gain of the common-source amplifier. Figure 7-3. Cascaded common sour ce-common gate balun schematic. Other active balun topologies improve the hi gh frequency cut-off by incorporating several techniques to overcome this Miller capacitance limited high frequency oper ation. For this noise detection application, the common-source common-gate topol ogy is chosen since it has several advantages over other topologies [7.4]. First, it can achieve broadband input impedance

PAGE 120

120 matching easily through adjusting th e input active device size. The input impedance at the gate of an active device in a common source topology is typically very high due to its large capacitive component, the input reflection coefficient of a common gate devi ce can be described approximately by 1/gm. Therefore, the proper selection of device size and biasing can yield a 50 input impedance. The input impedance of the co mmon gate device is in parallel with the very high input impedance of the co mmon source device so that the resulting input impedance is approximately that of the common gate device as shown in Figure 7-3. This means that there is no input matching circuit which typically, is implemented using passive devices like transmission lines, inductors or capacitances. The input matching circuits can limit the balun bandwidth due to their Q or frequency selectiv ity. Second, there is no need to use on-chip inductors which consume a huge area to prov ide matching or feedback compensation. Resistor RB should be large enough so that it ha s a very small impact on the input impedance since it is in parallel with 1/gm1. The gate of transistor M1 is biased at Vdd to avoid additional biasing circuitry and the gate M2 is biased at a voltage level set by the drop across RB which is determined by the DC current through M1. Also, the AC bypass capacitance at both input and output ports should be large enough to enhance the low frequency performance by establishing a proper low frequency cut-off frequency. The balun was simulated in the Cadence Spect ra simulator. The amplitude response is shown in Figure 7-4 and the difference in amplitude is shown in Figure 7-5. Both responses are plotted on log scale on the x-axis. Amplitude res ponses show a reasonable amplitude difference (< 0.5 dB) ranging from 200 MHz to 8 GHz. Th e narrow range from 300 MHz to 3 GHz shows less than 0.2 dB amplitude difference. The proposed system aims to measure the phase noise

PAGE 121

121 generated a over the range 500 MHz to 2 GHz so the balun design is adequate without calibration. The balun power consumption is le ss than 6 mW with a 1.2 V power supply. Figure 7-4. Amplitude response of the active balun. Figure 7-5. Amplitude difference of the active balun, (S21-S31).

PAGE 122

122 Figure 7-6 shows the phase response. In th e range from 300MHz to 3GHz, the figure shows less than 4 error in phase difference. In particular, it shows an exact 180 phase difference at 1GHz which is ideal. Figure 7-6. Phase difference of the active balun. Table 7-1 summarizes the simulated performan ce of the active balun in this work. The active balun converts the single-ende d input signal into a differen tial signal for the subsequent analog delay line and phase shifter which ar e presented in the next sections. Table 7-1. Baluns Performance Summary This Work [7.3] [7.5] Frequency Range 200MHz ~4GHz 1. 7GHz ~5.8GHz 5.1GHz ~5.9GHz Gain Error 0.3 dB 1 dB 0.02 dB Phase Error 4 1 0.58 Power 6 mW 11.4 mW 9.17 mW

PAGE 123

123 7.2.2. Active Delay Line In a commercial phase noise measurement system, a delay line usually is implemented by a coaxial cable or transmission line which does not am plify or significantly dist ort the signal. If the delay line imposes an excessive gain or loss to the signal, the output will provide a distorted signal compared to the input signal. Also, if the signal is amplif ied through the delay line, the noise is amplified as well. A transmission line based delay line can be successful for this application. Ideally, a 0dB loss delay line is the best choice with a wide bandwidth. However, a very long line is needed to achie ve greater than a 10ns delay time with a transmission line such as a coaxial cable or a coplanar waveguide. Also, this long line attenuates the signal considerably. A lumped element delay cell (i.e. a LC ladder filter) needs several hundre d stages to achieve enough delay time. Moreover, the LC ladder filte r has a cutoff frequency which is relatively small compared to a transmission line. The lo wer cutoff frequency achieves a bigger delay per stage for the LC ladder filter but the delay time per stage is still very small for this application [7.7]. In digital applications, delay is reali zed by reducing the bandwidth of a switching stage. The subsequent switching of an unloaded stage re stores the rise time of the digital waveform [7.8]. However, this approach is not useful in analog applications that are sensitive to signal distortion. An active analog delay stage should de monstrate constant band width at a variety of delay values. After considering chip area and achievable delay time, the basic delay line, a differential inverting amplifier with a output level shifter is chosen. The delay line uses a differential inverting amplifier configurati on which introduces a limited operational bandwidth. Also, in order to achieve enough delay for an accurate phase noise measurement, the delay line consists of a 100 differential inverti ng amplifier stages in series. The following gain and bandwidth analysis depends on the number of cascaded stages, N. The cascade gain stage design analysis will introd uce a gain and bandwidth trade-off [7.6].

PAGE 124

124 Figure 7-7. Cascaded of finite gain amplifiers. In Figure 7-7, each stage has an ideal voltage amplifier with gain A0, an output resistance ROUT, and a load capacitance COUT. The overall transfer functi on is given by equation 7-3. N 01 () where 1c OUTOUT cA Hs s RC (7-3) where c is the -3-dB bandwidth of each stage. For more than 2 stages, the bandwidth of the overall circuit can be described as shown in equation 7-4 [7.6]. 30.9 21N dBccN (7-4) The foregone analysis suggests th at each stage in a differen tial inverting amplifier chain must achieve a very wide bandwidth in order not to distort the signal. Th erefore, each stage of delay line circuit is designed to achieve ar ound a 10GHz 3 dB operational bandwidth. Also, the gain of each stage is a major consideration. The ca scaded gain stages add the gain of each stage on a logarithmic scale. Theref ore, if each stage gain is A0, the total gain of N stages is NA0. For example, a 1 dB gain amplifier of 100 stages accumulates 100 dB, which is 100000 in magnitude.

PAGE 125

125 Figure 7-8 shows the impact on the signal response of a high gain amplifier which introduces signal distortion such as clipping. With excessive stage gain, the signal will experience signal distortion shown in Figure 7-8 B. When passed th rough several gain stages, the pure sinusoidal signal changes into a rectangular wave. So the am plifier stage only amplifies the linear region of the rectangular wave (dotted area) as shown in Figure 7-8 C. Phase noise can be interpreted as jitter in the time domain. So jitt er in the time domain also experiences distortion compared to the original input signal. In orde r to keep the same phase noise through the delay line, each stage gain should be about unity in order not to distort the signal and noise. The gain and bandwidth of each basic delay line circuit should be optimized to achieve a reasonable gain and operation bandwidth dependi ng on the number of stages. The delay time should be large enough to produce accurate measurement results. Figure 7-8. Cascaded gain stage time response with excessive gain.

PAGE 126

126 In this work, a differential inverting amplifier topology was chosen (differential amplifier with load resistor) because th is topology can ensure the maximu m operational bandwidth without using an inductive peaking technique. This topology can have a large gain which will degrade the delay line response. To minimize the gain of each stage, a source follower is added to the each differential amplifier stage. Figure 7-9 sh ows the proposed delay line cell topology. Figure 7-9. Delay line cell schematic. The source follower provides two key operations First, the source follower usually shows less than 0dB gain with a relativ ely wide bandwidth due to the suppressed Miller capacitance. The second, the source follower can shift down the DC operating point. Therefore, each stage input always experiences the same DC bias poi nt. By adjusting the out put DC level of the differential inverting amplifier, the stages ar e easily cascaded. Figure 7-10 shows the basic concept of this topology that adjusts the different ial inverting amplifier. The first stage of the differential inverting amplifier increases the DC level and amplifies th e signal as shown in Figure 7-10. The source follower reduces the DC bi as level and the signal amplitude. Therefore, the output signal preserves the same amplit ude and DC bias as the input signal.

PAGE 127

127 Figure 7-10. Transient response of the proposed differential inverting amplifier. Transient simulation results of the proposed delay line are shown in Figure 7-11. The first stage of the proposed delay line cell increases the DC bias level and the s econd stage sends it back to the input DC bias level. This topol ogy can minimize unwanted si gnal distortion and keep the original signal applied to the output through many cascaded st ages. The differential amplifier and source followers share a 1.2 V power supply in order to minimize the power consumption

PAGE 128

128 and prevent overloading the DUT. The simula ted DC power consumption is 60mW for 100 stages. Figure 7-11. Transient simulation results of th e proposed differential inverting amplifier. Figure 7-12. AC response of the propos ed differential inverting amplifier. The AC simulation shows the 3dB bandwidth of the proposed delay line cell. As explained by equation 7-4, the operational bandwidth shoul d be large enough to minimize unwanted signal

PAGE 129

129 distortion at high frequency. The 3dB bandwidth is set around 8GHz. Without using any feedback compensation element, the circuit achieves the widest bandwidth. The delay time and operational bandwidth have a trade-off. The delay time is inversely proportional to the operational bandwidth. Theref ore, a longer delay sacrifices the operation bandwidth which in turn introdu ces unwanted signal distortion. Fo r the phase noise measurement system, the delay time should be large enough to en sure an accurate measurement result. In this work, the goal is to provide 2.5 ns delay genera tion to measure up to a 20 MHz offset frequency. Each delay cell of the proposed inverting amplif ier can generate 26 ps delay with 8 GHz 3 dB bandwidth. Therefore, the delay line consists of 100 stages in orde r to achieve a long delay time. The transient simulation result is shown in Figur e 7-13. The delay line generates greater than 3.447 ns delay through 100 stages with minimi zed signal distortion at 1 GHz frequency. Figure 7-13. Transient response of the proposed delay line. Figure 7-14 shows the delay va riation of the delay line depending on the operational frequency. At smaller bandwidths, the delay time is increased in the same environment. Through

PAGE 130

130 all the simulations over the entire frequency ra nge, the power consumption is almost the same, around 60 mW, for 100 stages. Gain also varies depending on frequency. For an accurate comparison, the gain of delay line is controll ed through the source follower and current source of the first stage of the delay line cell. Delay time is calculated by observing th e first rising point of the delayed signal. Figure 7-14. Delay time variation dependence on the operation fre quency of operation. 7.2.3. Active Phase Shifter (Based on Variable Delay Cell) The phase shifter in a commercial phase noise measurement system is usually an external module which consists of variab le capacitors and inductors. Th is discrete module can have a large tuning range and an accurate tuning sensitivity. When it comes to on-chip applications, the choice of a phase shifter design is very limited due to the available passive elements such as varactors, capacitors and inductors. If the design goal of the phase shif ter is for a narrow band operation at a specific frequency, the design can be realized wi th these passive components. However, the phase shifter in the proposed noi se measurement system needs to operate over a

PAGE 131

131 wide frequency range. Thus, the phase shifter is designed using a variable delay line due to the variable delay lines relatively wide operational frequency range and wide tuning range. A phase shifter in the frequency domain provides the same circuit function as a vari able delay circuit in time domain. This embedded phase noise measurement system is designed for measurements from several hundred MHz up to 2 GHz. To achieve this specification, the phase shifter was implemented with the shifter element to be a variab le delay cell. In this case, the variable delay cell can control its output to produ ce a wide range of delay time to adjust the input to the mixer to be 90 out of phase. Also, the phas e shifter keeps the output signa l at the same amplitude as the input in order not to produce signal distortion. Thus, the fina l phase shifter is designed using a variable resistance dela y cell with a source follower to adjust the output DC level to the next cell input DC level and prevent si gnal distortion. In addition, th e variable delay line usually experiences a severe DC level change at the outpu t to the mixer so additional DC bias adjustment circuitry is added to produ ce a stable output DC level. Figure 7-15 shows the basic vari able delay stage of the variable delay line. The load element contains a diode-connected PMOS device in shunt with an equally sized externally biased PMOS device that produces symmetric load char acteristics [7.9]. Two PMOS device pairs create a symmetric load in order to ma ke the load resistance looking into M3 and M4 linear and dependent on the control voltage ( VP). Ideally, by the standard qua dratic model of a long channel MOS, the I-V characteristics of the symmetric lo ads are completely symm etric about the center of the voltage swing. The load swing is defined from the Vdd rail supply to the bias voltage for the M4 and M6 PMOS devices. It is importa nt to see that the effective resistance of a symmetric load is directly proportional to the small signal resistance at the ends of the swing range. This

PAGE 132

132 small signal resistance is just one over the transconductance, gm for one of the two equally sized devices when biased at Vp as shown in equation 7-5. eff effeffRdelay mC tC g (7-5) where Reff, Ceff are the effective output resistance and capa citance of the first stage of the variable delay cell, respectively [7.10]. Figure 7-15. Basic cell of th e proposed phase shifter. The PMOS bias voltage for the lo ad element must be controlled so that the load current at the point of symmetry equals one half of the di fferential pair bias current. The PMOS bias voltage can be generated simply by connecting the bias voltage to the output of a dummy load element biased by a differential pair bias current. This connection will es tablish the PMOS bias voltage as the lower DC voltage swing limit, the point where the load current equals the differential pair bias current. Alternatively, the differential pair bias current can be established for a given PMOS bias voltage using a replica-f eedback bias circuit as shown in Figure 7-16.

PAGE 133

133 The MOS realization of symmetric loads has additional advantages beyond their high dynamic supply noise rejection characteristics. B ecause the higher gain region always occurs at the center of the voltage swing, the delay cells will provide adequate ga in for generating signal delay over a broad frequency range. Furthermore, because the load resistance of symmetric loads decreases towards the ends of the voltage swing, the transient swing limits will always be well defined near the DC swing limits, resulting in reduced noise sensitivity. The IC layout for the differential delay cell will be ve ry compact because the load elements only contain two equally sized PMOS devices. Figure 7-16. Simplified schematic of the self-biase d replica-feedback current source bias for the differential variable de lay cell stage [7.9]. A simplified schematic of the current source bias circuit illustra tes the basic circuit functions. The bias circuit sets the current through the simple NM OS current source in the delay cells in order to provide the correct symmetric load swing limits. In addition, it adjusts the NMOS current source bias dynamically so that this current is held constant and highly independent of supply voltage in order to counter act the effect of the fi nite output impedance of the simple NMOS current source and achiev e high static supply noise rejection.

PAGE 134

134 Figure 7-17. Schematic of the self -biased replica-feedback current source bias for the differential variable delay cell stage [7.9]. The current source bias circuit is based using a replica of ha lf the buffer stage and a singlestage differential amplifier. The amplifier adjusts the current output of the NMOS current source so that the voltage at the output of the replicat ed load element is equa l to a control voltage, a condition required for correct symmetric load swi ng limits. The net result is that the output current of the NMOS current source is establishe d by the load element and is independent of the supply voltage. As the supply voltage changes, the drain voltage of the NMOS current source devices varies. However, the gate bias is adju sted by the amplifier to keep the output current constant, counteracting the effects of the current source finite output impedance. As shown in Figure 7-17, in order for the amplifier not to limit the delay cell supply voltage operating range, it must have low suppl y voltage requirements. For this reason, an amplifier based on a self-biased PMOS source c oupled pair is used. In order for the PMOS current source device in the amplifier to remain in saturation, the current densities of the PMOS source coupled pair devices and th e PMOS current source device must be one quarter of that in the PMOS symmetric load devices. The amplifier bias is generated from the same NMOS current

PAGE 135

135 source bias through a stage mirroring the half-delay cell replica so that amplifier supply voltage requirements are similar to those of the buffers and the amplifier bias current is highly independent of supply voltage. This replica bias stage is necessa ry because otherwise the input offset of the amplifier will vary with supply voltage, causing the output current of the NMOS current source to also change with supply voltage Because the amplifier is self biased with a potential of multiple operating points, the bias ci rcuit is made stable with the amplifier unbiased and an NMOS current source bias at the negative supply. As a result, an initialization circuit is needed to bias the amplifier at power-up to the exact operating point. This initialization circuit prevents the NMOS current source bias from completely turning o ff the bias current sources to a stable zero current op erating point [7.9]. As shown in Figure 7-17, a compensation for stable operation is required because this current source bias circuit contains a feedback lo op with two gain stages and with two significant poles. The pole at the amplifier output will domin ate with a much higher output impedance than the pole at the half-delay cell repl ica output. Therefore, to increase the phase margin of the bias circuit, the design simply limits the capacitive output load of the simple NMOS current source gates in the delay cell stages. Th e output load should be limited to about ten delay cell stages containing devices of the same size as the corres ponding devices in the bias circuit in order to prevent the output recovery time of the bias circuit from limiting the dynamic supply noise rejection of the delay cells. With no required re ference voltage, the only external bias is the control voltage ( VP). Although no device cascading is used, the resultant stat ic supply noise rejection is equivalent to that achievable by a delay cell stage and a bias circuit with cascading, without requiring an extra supply voltage. The total supply voltage requi rement of the buffer

PAGE 136

136 state and bias circuit is slightly less than a series NMOS and PMOS diode voltage drop with identical current densities. Figure 7-18. Transient simulation results for th e proposed 6-stage variable delay cell depending on the PMOS load bias. Figure 7-18 shows a transient simulation resu lts for the proposed variable delay cell. The source follower produces an output DC level th at feeds into the input DC level, which is similar to the delay line architec ture except for its symmetric load In this way, the output level of the proposed variable delay cell can preven t the signal from producin g unwanted distortion. By cascading six stages of the proposed variable delay cell, th e maximum variable delay is adjusted to 500 ps at 1 GHz. In the frequency domain, the delay module can adjust the phase quadrature up to 500 MHz. All the circuits use a 1.2 V power supply in order to minimize power consumption. The simulated DC power consumption is 12mW.

PAGE 137

137 7.2.4. Double Balanced Mixer (Phase Detector) 7.2.4.1. Passive Ring Mixer (Input Structure) Most systems which require phase information use mixers somewhere in the measurement for comparison of phase information. Theoretica lly, any mixer with a dc coupled port could be used as a phase detector. Practically, however mixers often display some very non-ideal characteristics (e.g., DC offset) when used as phase detectors. The act ual mixer chosen for a particular application will of ten depend on the degree to whic h these non-ideal characteristics can be tolerated. In this work, a double balanced passive mixer is chosen with an active RC filter following it because the system has high linear ity, no flicker noise generation and low power consumption. Normally NMOS transistors ha ve better switch perf ormance than do PMOS transistors because of the higher mobility of elec trons than holes. Therefore, NMOS transistors are chosen for the passive mixer elements. Figure 7-19. Simplified schematic of the passive ring mixer (bias not shown). The basic phase detection concept is the applic ation of two identical frequencies, constant amplitude signals to a mixer which results in a dc output which is proportional to the phase difference between the two signals. While it is true that even a single diode can be used as a

PAGE 138

138 mixer, most phase detectors involve the use of double balanced mixers. With this in mind, the theory presented in this chapter fo cuses on double balanced mixer design. Figure 7-19 is a schematic of a typical doubl e balanced, four-MOSFET mixer. The main difference between the Gilbert quad mixer and a folded ring mixer is the biasing levels. The Gilbert quad mixers are biased nominally into sa turation and have DC current while the passive ring mixers are biased near the FET threshold and have no DC current. Gilbert mixers which convert an incomi ng RF voltage into a current through a transconductor, whose linearity and noise figure set a firm bound on the overall mixer linearity and noise figure. This circuit uses voltage-controll ed current sources in VI converter circuit for a voltage-controlled resistance. The resistance of a triode-region MOSFET varies in a manner inversely proportional to the incoming RF signal. If the voltage between the mixer transistor drain and the source is maintained at a fixed value, the current flowing through the device will be a faithful replica of the RF voltage, and if the drai n-source voltage varies with the local oscillator, LO then the current will be proportional to the product of th e LO and RF signals [7.11]. Table 7-2 summarizes the simulation re sults of the passive ring mixer. Table 7-2. Performance summary Parameters This Work Reference Work [7.12] Process 0.13 um 0.13 um Conversion Gain (Gc) -4.8 dB -5.5 dB Noise Figure 4.9 dB 6.5 dB P1dB (dBm) -1.5 dBm N/A IIP3 (dBm) 7.65 dBm 10 dBm LO Power (dBm) 5 dBm 5 dBm

PAGE 139

139 Figure 7-20. Phase detector topology (bia s not shown). The use of a double balanced structure cancel s out the common-mode dc biasing signals and the nonlinear dependence of gds on Vds. The final down-conversion mi xer circuit is shown in Figure 7-20. There are two very important capacitors at tached to the virtual ground nodes of this topology. The output stage (the opamp and the f eedback resistors), wh ich convert the output current of the mixing transistors back into a voltage, should only be able to produce a lowfrequency output signal. However, in order to let the input operate for all frequencies, the virtual ground nodes of the mixer must have no high frequency signals. This is usually done with the feedback structure connected to the opamp whic h creates the virtual ground at its inputs. The transistors in the input would operate as pass-t ransistors for high-fre quency signals when the frequency capability of the opamp would not be high enough. Therefore, the capacitors C1 have been added. The C1 capacitors make sure that all the high frequency currents injected to the virtual ground nodes are filtered out and not conver ted into voltages. The opamp still generates a

PAGE 140

140 virtual ground for low frequency signals. The de sign procedure can split the design of the input and the opamp by using the structure shown in Figure 7-20. The input structure (passive ring mixer) can be optimized for high frequency operation (more than 1 GHz) while the opamp can be design ed for low-frequency operation (up to several hundreds of MHz). The dc biasing levels of the RF and LO signa l must be chosen carefully. There will be severe distortion when the pass-transistors are not kept in the triode re gion at all times. The smallest possible level that can appear at the gates must be at least a VT higher than the largest possible source level. Otherwise the transistor s will be turned off during the mixing period. Saturation of the pass-transistors will appe ar when the largest drain-source voltage Vd s becomes higher than the smallest Vgs-VT. However, saturation does not dire ctly result in distortion. The cross-coupled double balanced structure makes sure that all quadratic co mponents in the voltageto-current conversion characte ristic of the pass-transistor s are cancelled out [7.13]. 7.2.4.2. Active RC Filter (Output Structure) In order to build a reliable double balanced mixer with an active RC filter for downconversion, the active RC filter should have severa l characteristics. First, it should provide low power consumption. Second, it should have hi gh linearity. Third, it should have a wide operational bandwidth. The proposed system is targ eted to measure phase noise which usually is measured at several offset frequencies (e.g 600 kHz, 1 MHz, 3 MHz and 10 MHz) depending on the test device technology standard. Therefore, the active RC filter should possess at least a 50 MHz 3 dB bandwidth. The main design challenge lies in designing for a low voltage supply. Generally, integrated continuous-time high frequency baseband filters employ either gm -C or MOSFET-C topologies with an automatic tuning methods [7.14] [7.15]. However, the tr end towards low supply voltage

PAGE 141

141 introduces new challenges in the realization of these techniques. For gm -C filter types, it is difficult to achieve a broad dynamic range and good linearity performa nce with low power consumption, whereas CMOS implementations su ffer from reduced programmability [7.16]. The MOSFET-C approach may be better than gm -C in terms of power dissipation and noise performance, but linearity and tuning range may be poor for low supply voltages. The operational amplifiers of the filter operate on a 1.2 V supply and demonstrate a very good compromise between high-frequency performa nce and current consumption, due to the compensation technique reported in [7.17]. In part icular, a 20 times boost is achieved in terms of the dominant pole of the amplifier relative to traditional compensation practices without causing any stability problems in the pres ence of an output load. The system consists of a differential input stage, an output stage, and a common mode feedback (CMF B) circuit as shown in Figure 7-21. Figure 7-21. Operational amplifier schematic (bias not shown). In order to expand the amplif iers bandwidth without a loss of a gain, a new compensation technique is adopted, based on [7.15]. The idea is to place two cross-coupled capacitors between the input differential pair and the output buffer. These capacitors act as a negative capacitance,

PAGE 142

142 C of the input transistors, thus generating an anti-pole-splitting behavi or that augments the amplifiers gain-bandwidth product. The proposed compensation techniqu e uses the anti-polesplitting method, but in a different way than the technique in [7.16]. The compensation capacitors ( CF) are cross connected to the outputs of the first and sec ond stages of the amplifier, which is combined with the classic Miller RC co mpensation. It provides not only an anti-polesplitting behavior, but also a phase-controlling ac tion, that holds the output phase away from 180 for frequencies spanning far beyond the unity gain frequency, thus providing extra bandwidth and adequate phase margin [7.17]. Figure 7-22. AC modeling of Operational amplifier. The simplified AC equivalent model of th e amplifier with an output capacitance Cload is shown in Figure 7-22. The differential open-loop volta ge gain is described in equation (7.6). For the sake of simplicity, a third order term in the denominator is omitted si nce its contribution is marginal at the frequency range of interest comp ared to the lower order terms. The impedance of the current source transistor will be very large. By symmetry, M1 and M2, M3 and M4, M6 and M9, M7 and M10, M8 and M11 are equal.

PAGE 143

143 2 116 6166 32 16 611367 2 116 6166 2 16 6() 4 4out in mgdFFgdFFgdFmFFm FFmF mFF dsdsdsds mgdFFgdFFgdFmFFm FFmF mFV As V gsCRCCCsCCCgRCsg DsCCgREsgCCFsgggg gsCRCCCsCCCgRCsg CCgREsgCC 11 3 6 7 Fd s d s d s d sFsgggg (7.6) where 2 13661671 61 FFgdgdgdgsFgdgdFloadgdFDRCCCCCCCCCCCC (7.7) 2 1366167161 6713661 1367166 1376 gdgdgdgsFgdgdloadFgdF dsdsgdgdgdgsF FF dsdsgdgdloadFmgd FgdgdgdgsloadECCCCCCCCCCC ggCCCCC RC ggCCCCgC CCCCCC (7.8) 6713661 1367166 13671367 dsdsgdgdgdgsF dsdsgdgdloadFmgd FFdsdsdsdsFdsdsdsdsFggCCCCC ggCCCCgC RCggggCgggg (7.9) The term E and F depends on parasitic capacitances and output load capacitances. If the output load capacitance is small enough, the term E and F can be ignored. The feedback capacitors CF and CF1 should be substantially greater than the circuits parasitic capacitance. The open loop gain indicates that the poles are on the le ft-half plane as long as the coefficients of the first-order and second-order terms of the denomin ator are positive. Consequently, two relations must be valid for the circuit stability. 64F mR g (7.10) 1FFCC (7.11)

PAGE 144

144 These relationships are derived under the assumption that the terms E and F are negligible. In order to verify the zero circuit effects, in the numerator of equation 7-6, it is assumed that Cgd3 is negligible. Equation 7-6 can be approximated by equation 7-12. 22 11 66 22 61 3 6 7() 4mgdFFmFFm FmFdsdsdsdsgsCRCsgRCsg As CgRBsCsgggg (7-12) As shown in equation 7-12, the transfer respons e contains 3 zeros. One is located in the right-half plane at extremely high frequencies. Th e other two lie on the left-half plane and can be described as below. 6 6 1,2 64 2 2mF m F F F mgR g z C R C g (7-13) It is obvious that these two zeros are on the real frequency axis if RF>4/gm6. Now, when it comes to the third order coefficient, D, the third pole moves to a lower frequency as RF increases. Larger values for RF generate wider bandwidth as the two more significant poles shift to higher frequencies as shown in e quation 7-13. By selecting RF=4/gm6, the circuit create s a double zero at frequency -gm6/2CF. In practice, there might still be a sma ll imaginary part, but it has a negligible effect. Also, this analysis disregards parasitic capacitance and real circuits have these two zeros and the third pole appear at rath er lower frequencies than our an alysis suggests. One important fact is that the dependence of the zeros on CF is much stronger than that of the two dominant poles. This gives more flexibility to the posi tioning of the zeros in a frequency compensation procedure when they can be moved without sign ificantly altering the lo cation of the two poles. Practically, the value of RF can be a little greater than 4/gm6 without the sacrifice of stability in simulation.

PAGE 145

145 A B Figure 7-23. Amplifier A) gain and B) phase acc omplished with the proposed compensation and the conventional RC compensation network. This double zero features are very important. It adds positively to the phase response, thus moving the -180 intersect to a much higher freque ncy. Figure 7-22 shows the difference between the pole-splitting compensation method and the proposed compensation method. The amplifier core is identical in both cases except for th e circuit feedback elements. The proposed topology offers a 20 times increase in the freque ncy of the amplifiers dominant pole with respect to the classic RC approach for the same cu rrent dissipation. The unity gain frequency is less important for the filter application. Phase response is non-monotonic, showing a minimum of -150 below the unity gain frequency, but this is not the relevant phase to consider for stability.

PAGE 146

146 The compensation technique drastically improve d the amplifiers frequency behavior for the benefit of the filter performance. The filters linearity is improved and so is the frequency response. Simulations revealed that using the am plifier with this compensation technique in the filter, provides significant improvement in both in-band and out-of-band IIP3 performance compared to conventional approaches. More specifically, the performance gain increases as the two input tones move higher in frequency. A nother interesting advant age of this works compensation technique over conventional pole-splitti ng methods is that it mitigated the filters passband ripple. The CMFB circuitry is descri bed in Figure 7-21. Voltage, VCM is in the region of half the supply voltage (typical ly, 600 mV). The same current flows through M12 and M13 only if their VG is equal. Given the fact that VCM remains constant, then, the half sum of the voltage at the two output stages must equalize VCM for a current equilibrium in M12 and M13. Hence, the loop that closes through M12, M13, M14, M15 and M16 maintains the dc output voltage equal to VCM. This loop must have small gain to be wideband and stable. Capacitors C1 and C2 improve the loop phase margin so that common mode oscillations cannot be sustained. C1 also enhances the bandwidth of the CMFB loop in order to have sufficient CMRR at high frequencies. Table 7-3 summarizes the simulated pe rformance of operational amplifier. Table 7-3. Performance summary. Parameters Performance DC gain 45 dB Phase Margin 45 Gain Bandwidth 600 MHz Power Consumption 3.1 mW

PAGE 147

147 7.2.4.3. Double Balanced Mixer Result A mixers frequency converting action is char acterized by conversion gain or loss. The voltage conversion gain is the ratio of the RMS voltages of th e IF and RF signals. The power conversion gain is the ratio of the power delivered to the load and the available RF input power. When the mixers input impedance and load impeda nce are both equal to the source impedance, the power and voltage conversion ga ins, in decibels, are the same Note, that when the circuit load is a mixer with a high impedance f ilter, this condition is not satisfied. The mixers conversion gain and output distor tion level was simulated and the result is plotted in Figure 7-24. For the main 1 MHz IF signal, the mixer achieve s a conversion gain of 10.3 dB. Also, for a 10 MHz IF signal, the mi xer produces 8.3 dB of conversion gain. The conversion gain is calculate d based on equation 7-14. Figure 7-24. Double Balanced Mixer output spectrum As a phase detector, the mixer produces di fferent DC voltages proportional to the difference from the input phase quadrature. Figure 7-25 shows the mixer performance as a phase

PAGE 148

148 detector. As the phase difference increases, the output DC level increas es. The response of the phase detector shows a conventi onal multiplier response. For a sm all phase difference, the output dc changes rapidly while the output dc cha nges slowly for a large phase difference (>36). The simulation is performed for 500MHz, 1 GHz, and 2GHz. Depending on the operational frequency, the responses shows slight difference. output voltage Conversion Gain=20log input voltage (7-14) Figure 7-25. Double Balanced Mixer Output as a phase detector. The double-balanced mixer followed by active RC filter plays a key role in the entire system. Thus, the test circuitry for this part is implemented and measured in a separate test structure IC. The die-photo is shown in Figure 726. The test circuit aims to test the mixer function as a phase detector so that the outputs of mi xer are combined through a differential to single-ended buffer.

PAGE 149

149 Figure 7-26. Die photo of the Double Balanced Mixer with active RC filter and buffer. Figure 7-27 describes the test setup for the pha se detector functionali ty. A signal generator is used for sinusoidal signal generation. A bal un converts the single-ende d signal to differential signal and power splitter divides th e signal into two same phase si gnals. A variable phase shifter changes the phase difference and measuremen ts are performed depending on input phase difference. An Agilent infiniium 54832D is used for displaying th e output. The ge nerated signals range from 500MHz to 2GHz for the measurement. Measured data shows similar results in simulation for the entire range of measured fr equencies. Figure 7-28 shows the measured and simulated results after passing a buffer with 7dBm LO power and -7dBm RF power. Measured results show very good agreement with the simulate d results for two different frequencies. Both simulation and measurement shows the output independent to input power variations.

PAGE 150

150 Figure 7-27. Test setup fo r the phase detector. Figure 7-28. Simulated and measured phase de tector output for diffe rent phase input. Conversion gain is measured for different RF input frequencies in order to check the gain stability depending on the input frequency variation as shown in Figure 7-29. A buffer reduces the conversion gain to around 10 dB for the entire frequency range. In order to calibrate the proposed system, the mixer gain should be known as shown in equation 6-48. Conversion gain is

PAGE 151

151 measured for 1MHz IF output since the proposed system calibration is performed for a 1 MHz offset frequency. The conversion gain rangi ng from 750MHz to 2GHz shows less than 1dB difference. Figure 7-29. Measured conversion gain for different input frequencies. Figure 7-30. Measured conversion gain for different LO power.

PAGE 152

152 Figure 7-30 presents the conversion gain as a function of LO power variation for 1 MHz IF output while input RF power is -7 dBm. 7.2.5. Phase Shifter Auto-adjustment In the system, the mixer acts as an ideal phase detector by forcing the input signals to be in quadrature. Considering the mixer in a standalone operation, any deviation error from quadrature results in an output amplitude error, which is ve ry small when the deviation around quadrature is small. For example, a 1 offset from quadrature results in an amplitude error of -0.001 dB. However, the situation for the delay-line discriminator is much worse than the standalone mixer case due to the presence of the delay line before th e mixer. This problem is inherent in delay-line discriminators. A high phase shift can result when the delay time is much larger than the DUT signal period. In this case, the deviation from a quadrature condition is amplified by the delay, which results in significantly larger dc offset and amplitude detection errors. Figure 7-31. Auto-phase adjustment unit

PAGE 153

153 The proposed calibration circuit shown in Figur e 7-31 uses a comparator to measure the dc signal at the mixer output against a zero dc stat e. A charge pump and reset switch monitors the comparator output and then decides on the proper vol tage step to drive the control voltage of the VCDL. This is achieved by the ci rcuitry shown in Figure 7-31. The auto adjustment unit consists of three main components, which are DC comparator, Charge pump and Reset switch. By comparing the mixer output with a zero DC state, the charge pump achieves the proper dc level. A reset switc h works for the case of excessive dc levels. If charge pump accumulates a dc level more or less than the available control voltage (0.45~0.7V), the reset switch turns on and resets dc level in order to avoid system malfunction. The actual implementation is fairly simple because this ci rcuit only controls the dc voltage without any proper bandwidth depending on offset frequency. 7.3. Conclusion This chapter explains each building block implementation of the embedded phase noise measurement system. All the system components are implemented in standard CMOS technology in order to minimize the test system overload on the DUT system. In order to minimize unwanted distortion a nd noise generation in a test signal, the embedded system uses a differential circuitr y by converting a singleended signal into a differential signal through an active balun. The te st signal is delayed through the analog delay line which minimizes the unwanted test signal di stortion by introducing a level-shifting method to achieve 0 dB gain. The variable phase shif ter also adapts the same method to minimize unwanted test signal distortion. The double-balanced mixer suppresses the signal components of the test signal and leaves the noise component s which contain the phase noise components. By monitoring the system output level, an auto-a djustment unit cancels out the signal component automatically.

PAGE 154

154 CHAPTER 8 EMBEDDED PHASE NOISE MEASUREMENT SYSTEM RESULTS 8.1. Measurement Setup A phase noise measurement circuit is fabricated in a 0.13 um, seven metal CMOS process (IBM8HP) and occupies an active area of 1 mm 1.5 mm. The die photo for the fabricated system is shown in Figure 8-1. The power s upply is 1.2 V for all the components of the fabricated system. DUTs input is imposed at IN on left center pad and the output is extracted from OUT+ or OUT-. In this work, one of the out puts is utilized for the phase noise evaluation. The other pads on the upper and the lower side are for the DC biasing of individual building blocks. Active baluns are self-b iased by using a biasing resistor at the input port. The active delay line needs three DC biases. One is for the input DC level, VDCIN ( 0.4V). Another is for the current source biasing, VCDLY (0.5~1.2V) of th e active delay line to co ntrol the active delay line gain. Depending on the carrier frequency, the active delay line gain will vary. Thus, the current source biasing controls th e active delay line gain. The last one is for the current source biasing, VBDLY (0.35~0.6 V) of a source followe r (DC level shifter). By controlling the source follower current, the fine tuning of an active delay line gain is be possible. The phase shifter also needs biasing. VPVCDL (0.45~0.75V) controls the symmetric load impedance. In this work, it is not necessary to control VPVCDL since an auto-adjustment unit provides DC bias for the symmetric loading of the phase shifter. The magnitude of VCVCDL ( 0.5V) is similar to VBDLY in the active delay line. The passive mixer also needs a DC bias for it s input signal. The passive mixer is designed to work in the triode region. So the input signal DC levels are set to opera te the passive mixer in the triode region. VLODC ( 1V) is for DC biasing the intern al gate inputs. The active RC filter

PAGE 155

155 needs three DC biases. The, first is for the OPAMP input bias, VAMP ( 0.6V) since the OPAMP input DC range can not cover the entire DC bias range. The second is for the OPAMP CMFB reference, VCM ( 0.55V). The CMFB of OPAMP needs a reference bias to compare it with the average of OPAMP output bias. Then CMFB adjusts OPAMP output DC bias to operate correctly. VCAMP ( 0.5V) is for the output buffer bias. Figure 8-1. Layout of the proposed system (1 mm 1.5 mm) The general test setup used to characterize the embedded phase noise measurement system is illustrated in Figure 8-2. The most accurate method to evaluate the linearity and sensitivity of the phase noise measurement system is the m easurement of the response of a known carrier modulated with a single-tone FM si gnal as explained in Chapter 6.

PAGE 156

156 Figure 8-2. Test setup of the embedded phase noise measurement system. 8.2. System Linearity and Calibra tion Constants Measurements An Agilent E8254A signal generator is used to provide a 1 GHz FM-modulated signal at the DUT port for calibrating the system. To produ ce a single-tone FM signal while suppressing the power in the higher order sidebands, the modulation index () of the DUT signal is set to less than 0.2 rad by adjusting the FM deviation and th e FM rate of the Agilent signal generator. The first step in characterizing the phase noise measurement system is to validate the linear gain relation between the output voltage fluctua tions and the DUT frequency deviation (fm) [8.1]. In order to avoid a possible confusion between the terms, the single-tone FM signal is described and the terms which ar e used in system linearity an d sensitivity measurement are described in terms of physical definitions. The sinusoidal modulating signal ca n be described by equation 8-1. cos2mmmtAft (8-1)

PAGE 157

157 The instantaneous frequency of the resulting FM signal equals cos2 cos2icfmmc m f tfkAftffft (8-2) The quantity f is called the frequency deviation, re presenting the maximum departure of the instantaneous frequency of the FM signal from the carrier frequency fc. A fundamental characteristic of an FM signal is that the frequency deviation, f is proportional to the amplitude of the modulating signal and is independent of th e modulation frequency (FM rate). The phase of the FM signal is obtained as 022s i n 2t iicm mf tfdftft f (8-3) The ratio of the frequency deviation, f, to the modulation frequency, fm, is commonly called the modulation index of the FM signal and is shown in equation 8-4. m f f (8-4) Figure 8-3 shows the relationship between th e FM deviation and the FM rate. The FM deviation is proportional to the signal amplitude and the FM rate defines an offset frequency. The calibration constant is a different name for the system gain as e xplained in Figure 8-3. Figure 8-3 assumes that the measurement resolution bandwidth is 1 Hz for the simplicity of the equation. The input signal power is determined by the FM deviation for the case of a small modulation index (<0.2). Thus, a linearity test is pe rformed by checking the output powers dependance on the input signal va riation which is proportional to the FM deviation. The FM deviation represents the amplitude of the voltage of the input signal at a 50 system.

PAGE 158

158 Figure 8-3. Linearity test pr ocedure and calibration method for the embedded phase noise measurement system. The input signal power can be easily determin ed by equation 8-5 as shown in Figure 8-3. 22 m I nputPowerff (8-5) 20log20logm I nputPowerdBfdB f (8-6) For example, Figure 8-4 shows the linearity te st and the calibration procedure for a 1GHz 0dBm carrier signal. Figure 8-4 A shows the i nput signal with 200kHz FM deviation and 1MHz FM rate. The modulation index is displayed in terms of signal power so the actual input signal power needs to be converted to a more familiar fo rm. In Figure 8-4, the modulation index is 0.2 with 200kHz frequency deviation. In case of a 100kHz of FM rate 0.2 of the modulation index requires a 20kHz FM deviation. The input sign al power seems to be same for both cases. However, the actual input power is determined by the FM deviation as shown in equation 8-6. The actual input power for 20kHz FM deviation is -20 dB less than the one for 200kHz FM deviation. As FM deviation gets smaller at a fixed FM rate, the input power level decreases at a

PAGE 159

159 rate of -20dB/Decade [8.2]. The output signal power can be detected at the same FM rate (offset frequency). The input signal pow er can be estimated from eq uation 8-7 to equation 8-10. 22 222rms rmsm m f fff (8-7) 2 2 222 2pk ssb rms carrier m mf Pf Pf f (8-8) 20log20log 2 2rms calssbcarrier mf SPP f (8-9) 20log220log2 20log3rms rmsm mcal mfdBfffSf (8-10) Thus, the input power for a 200kHz FM deviat ion at 1MHz offset is 103 dB while the input power for a 20kHz FM deviation at 1MHz is 83 dB. The rough calculation of the system gain is -131 dBm (-28dBm 103dB) fo r the case of Figure 8-4. Figure 8-4. Example of the linearity test for, A) An input test signal (FM dev=200 kHz, FM rate =1 MHz) B) The resultant output signal at 1 MHz. The linearity test is performed by varying th e modulation index. The input power level has a linear relationship to the modulation index as e xplained in equation 8-5. As shown in Figure 8-

PAGE 160

160 3, both the modulation index and the fm rate for the input signal are varied with the completion of an auto adjustment process and the discrimina tor output is displayed with an Agilent E4448A spectrum analyzer. In order to measure the lowlevel output signal, the spectrum analyzers sensitivity is enhanced by the three methods. The first enhancement is by narrowing down the resolution bandwidth (RBW) of th e spectrum analyzer up to 1Hz. The second is by turning off or minimizing the input attenuator of the spectrum anal yzer. The input attenuator serves to increase the spectrum analyzers dynamic range by attenu ating the high power in put carrier. The last enhancement is through turning on the analysers internal preamplifier to increase the weak signal output signal of interest. These techniques effectively lo wer the displayed average noise level up to around -165 dBm. Thus, th e low-level signal is detected. Figure 8-5 shows the output power as a functi on of the FM deviation while the modulation index is less than 0.2 rad. Here, the FM devi ation on the X-axis represents the input power dependance on the FM deviation. Thus, the x-axis presents the input power with a 20dB/Decade increase. The displayed output shows good linearity up to a 1 MHz offset frequency since the output power shows 20 dB/Decade increase while the input power level increases 20dB/Decade as the FM deviation is proportional to input power level as shown in equation 8-6. The limitation of this measurement mainly comes from the signal generator which can only generate a 1 MHz FM rate ( fm).

PAGE 161

161 Figure 8-5. Linearity measurement as a function of FM deviation while the modulation index is less than 0.2 radian. For a phase noise measurement, the calibrati on constant should be evaluated for an accurate measurement. As shown in Figure 8-4, the calibration constant derivation procedure is similar to a linearity test. The calibration constant is calculated through eq uation 8-3 as explained in Figure 8-3. The calibration constants ( Kd) will be the same as long as the system shows linearity. [][]([]20log3[])d cal cal mcal K dBPdBSdBfdB (8-11) Table 8.1 shows the calibration constant ex tracted from the linearity test. Here Pcal, Scal and fmcal represent the output power, the power differe nce between the carrier and sideband of the input signal, and the measured offset frequency (measured FM rate), respectively. With a fixed

PAGE 162

162 FM rate, the FM deviation is changed to control the input signal level. As the input signal level gets smaller, the output power gets smaller at the same rate. Equations 8-12 and 8-13 show examples of this calculation. 6[][]([]20log3[]) 28[](20[]20log103[]) 131[] ; 1, 200d cal cal mcal mcal K dBmPdBmSdBfdB dBmdBdB dBmfMHzfkHz (8-12) 6[][]([]20log3[]) 40[](32[]20log103[]) 131[] ; 1, 50d cal cal mcal mcal K dBmPdBmSdBfdB dBmdBdB dBmfMHzfkHz (8-13) Table 8-1. Calibration Constant Evaluation. Scal [dB] Pcal [dBm] Kd [dBm] 0.2 -20 dB -28 dBm -131 0.1 -26 dB -34 dBm -131 0.05 -32 dB -40 dBm -131 0.01 -46 dB -54 dBm -131 fm rate = 1MHz 0.005 -52 dB -60 dBm -131 0.2 -20 dB -48 dBm -131 0.1 -26 dB -54 dBm -131 fm rate = 0.1MHz 0.05 -32 dB -60 dBm -131 The calibration constant can be derived through the system gain as shown in equation 8-14. The derivation of equation 8-14 is in Chapter 6. 2 22 2 2 ,2outrmsm drmsmdrmsmVfKffKff (8-14) The calibration constant is a function of the total system gain and the delay time ( d) as shown in equation 8-14. Therefore, this calibrati on constant will be calculated for each DUT in order to achieve accurate measurement results since the calibration constants will vary depending

PAGE 163

163 on the carrier power and th e carrier frequency. This is because the fabricated systems gain has limitations in the input power and the operational fr equency. As explained in chapter 7, the delay line and phase shifter have are limited in input po wer since their peak-to-peak voltage amplitudes are limited to -3dBm. Also, the delay line gain drops significantly over 1.5 GHz since the 100 cascaded stages of the delay cell reduces the operational frequency of the entire delay line. Also, the mixer shows input power limitations. With a signal input greater than 5dBm, the output shows gain compression which limits the input linear power range of the system. The mixer gain varies depending on the carrier frequency. From 500MHz to 2GHz, the mixer gain variation is less than 2dB. Thus, for up to a 1.5GHz input si gnal with less than 0dBm power, the calibration constant variation shows lit tle variation (<5dB). 8.3. System Sensitivity Measurement The phase noise system DC output represents the DUT noise output which contains phase noise information. This noise output should be converted to a phase noi se magnitude by using the measured calibration constant. The final pha se noise can be obtaine d through equation 8-15. [/] 20log()310log()mv m dm f dBcHzSfKf B L (8-15) where Sv( fm) is the output power, Kd is the calibration constant and B is the resolution bandwidth of the measured output power. The system sensitivity directly relates to th e linearity measurement in terms of noise level since low power input can not be detected at the output due to system generated noise. The sensitivity defines the minimum detectable pha se noise level without being affected by the system noise level in this work. Thus, the sensitivity of the fabricated system is calculated based on a linearity measurement. The minimum detectable signal level is set by the noise floor level. The system sensitivity at a 1 MHz offset is derived in equation 8-16 and is based on the response

PAGE 164

164 in Figure 8-6 A). Equation 8-17 shows the system sensitivity at a 100kHz offset. The minimum detectable signal level is almost same while m easuring with the same resolution bandwidth with the offset ranging from 100Hz to 1MHz. Thus, th e system sensitivity depends on the offset frequency so that the system sensitivity show s a slope of 20dB/Decade. Figure 8-5 B) shows the system sensitivity as a function of offset frequency in log scale. 62[/] 20log()310log() 140(131)20log(10)310log(10) 152 dBc/Hzmv m dm f dBcHzSfKf B L (8-16) 52[/] 20log()310log() 140(131)20log(10)310log(10) 132 dBc/Hzmv m dm f dBcHzSfKf B L (8-17) A B Figure 8-6. Sensitivity A) small output test signal (FM dev=2 Hz, FM rate =1 MHz) B) System sensitivity. Ideally, the system can detect -152 dBc/Hz at 1MHz offset frequency. This calculation did not consider any 1/f device noise since the sy stem noise floor in simulation is less than the sensitivity level up to 1MHz as shown in Figure 8-7.

PAGE 165

165 Figure 8-7. System output noise and system sensitivity. The output noise shows 1/ f noise slope of up to 1MHz and over 10 MHz the system noise floor drops 20 dB/Decade since the active RC filter followed by mixer has around a 10MHz operational bandwidth. The main noise source co mes from the down-conversion mixer as the noise analysis shows in Chapter 6. In particular, the mixer is implemented by four NMOS devices and followed by an active RC filter. This active RC filter is the main contributor of the system noise floor. However, the noise analysis of this mixer shows less than -110 dB at 100 Hz offset. The mixer noise simulation shows a lower noise floor than the system sensitivity level up to 1MHz. Therefore, the mixer device noise can be ignored in this case However, other noise sources such as coupling noise and subs trate noise can still impact the system. 8.4. Phase Noise Measurement In order to verify the system performance, the proposed system characterized two signal generators and one commercial VCO. The firs t measurement was performed with an Agilent

PAGE 166

166 E8254A signal generator. The Ag ilent E8254A is based on a PSA which shows a superior noise floor compared to other types of signal genera tors. The measured results are compared to the Agilent E4448A spectrum analyzer phase noise measurement results. The signal generator specifications generally provide the noise floor information at specific frequency so that the measured results can be compared the signal generator noise floor sp ecifications. Also, the spectrum analyzer has a noise specification. This noise specification lim its the accuracy of the spectrum analyzer measurement results. Figure 8-8. Phase noise measur ement procedure A) input te st signal B) system output.

PAGE 167

167 Figure 8-8 shows the measurement procedur e and actual output spectrum. The system output is measured by a input filte r bandwidth depending on offset frequency. In this series of measurements, the measured resolution bandwidths, RWBs of the spectrum analyzer are set to 1kHz to 10kHz (RBW=82Hz), 10kHz to 100kHz (RBW=820Hz), 100kHz to 1MHz (RBW=8.2kHz) and 1MHz to 10MHz (RBW=82kHz). The RBWs are set at the input stage of the spectrum analyzer. Since sp ectrum analyzers measure the RF signal power in a specific bandwidth, they can clearly be used to measur e phase noise. Most modern analyzers include software functions which will convert a measured signal level from its absolute value to the equivalent noise signal in a 1Hz bandwidth; th en, a phase noise measurement can be derived. The system output shows around 10 dB difference per decade caused by the spectrum analyzer resolution bandwidth.. A higher offset frequency requires 10 times bigger resolution bandwidth or measurement time can be excessive. Figure 8-8 shows the measured phase noise for 1GHz 0dBm input signal generated by E8254A. Phase noise result shows good agreement ranging from 3kHz to 1MHz. Above a 1MHz offset frequency, there is a severe roll-off because the active RC filter which is a part of active mixer has less than a 10MHz operational bandwidth since the active RC filter use a CMOS OPAMP. As shown in Figure 7-23, the gain re duction is around 20 dB per decade above 10MHz. However, the measurement shows a reduced operation bandwidth since there is several parasitic capacitance contributions from RF bonding pads and long connection lines. Up to 10 kHz, spectrum analyzer measurement results show a little change due to its limitations. The discriminator system results can not accurate m easure the phase noise results from DC up to 3 kHz since the system noise floor (sensitivity) is higher than DUTs signal noise. Thus, from DC to 3 kHz, the system shows the system noise floor instead of characterizing the DUTs phase

PAGE 168

168 noise. This is due to 1/f noise and VT mismatch of the CMOS transistors throughout the discriminator system. Figure 8-9. Phase noise measurement for 1 GHz 0dBm input generated by Agilent E8542A. Figure 8-10 shows the phase noise measurement results for characterizing an input signal of 500MHz 0dBm from an Agilent E8542A. The meas ured results show similar behavior to the characterized 1GHz carrier input. The close-in offset frequency (< 3kHz) shows a big deviation due to the discriminator systems poor sensitivit y. However, the discriminator system response ranging from 3 kHz to 1 MHz follows the DUTs phase noise response. Above 1 MHz offset, the discriminator system response shows a gain roll-off due to the active RC filter bandwidth limitations. The close-in measured phase noise of the proposed system shows lower DUT phase noise response below the system sensitivity. The system sensitivity can be determined by the

PAGE 169

169 spectrum analyzer resolution bandwidth. A smaller offset frequency allows detection of a lower power signal than at a higher offset frequency. In this work, the system sensitivity is calculated in an actual situation, not in ideal situation. Ideally, system simulations in Spectre shows less than -160 dBc/Hz at a 1MHz offset. Thus, th ere is around 5~10dB deviation in sensitivity calculation from the ideal simulation. Figure 8-10. Phase noise measurement for 0.5 GHz 0dBm input generated by an Agilent E8542A. Figure 8-9 and 8-10 use PSA type signal genera tor which has superior noise sidebands. The two measured results from the spectrum analy zer are close to the spectrum analyzer noise floor which degrades the measurement accuracy. T hus, an ESA signal generator is also used to generate a noisy input signal. The ESA signal gene rator usually has a higher noise sideband than the spectrum analyzer.

PAGE 170

170 Figure 8-11 shows the measured results from using both the discriminator system and the spectrum analyzer. The spectrum analyzer measured results shows a higher noise sideband than the spectrum analyzers noise floor. Thus, the a ccuracy of the spectrum analyzer is enhanced when compared to PSA signal generator measurement results. Figure 8-11. Phase noise measurement for 1 GHz 0dBm input generated by Agilent E4421B. Figure 8-12 shows the proposed system measur ement results follow the spectrum analyzer result up to a 1MHz offset frequency. Above a 1MHz offset, the gain is reduced severely. Figure 8-12 illustrates a 500MHz 0dBm input signal generated by an Agilent E4421B signal generator. The system and spectrum analyzer response show the same behavior as explained in Figure 8-11. The cl ose-in (<10kHz) phase noise meas urement of the discriminator system follows the system sensitivity curve sinc e the system sensitivity is higher than the measured phase noise.

PAGE 171

171 Figure 8-12. Phase noise measurement for 0. 5GHz 0dBm input generated by Agilent E4421B. For the final verification of the discriminato r system, a commercial external VCO (minicircuits ZX95-1700W-S) is measured with di fferent tuning voltages (600MHz, 800MHz, and 1GHz). The different tuning voltages show di fferent phase noise performances. So, this measurement provides a good insight into the capabilities of the onchip discriminator system. Figure 8-13 shows the 1GHz VCO phase noise measurement results. The close-in phase noise of the external VCO shows very low phase noise performance below the system sensitivity level. However, the noise peaking arises at around a 60 kHz offset frequency. The proposed system shows noise peaking at the same offset frequency. The phase noise performance over the 10kHz ~ 1MHz band shows good agreement between the proposed system and the spectrum analyzer response.

PAGE 172

172 Figure 8-13. Phase noise measurement for 1 GHz 0dBm input generated by the commercial external VCO (mini-circuits ZX95-1700W-S). Figure 8-14 and 8-15 shows the phase noise measurement results for 800MHz input and 600MHz input signals. The noise peaking happens at different offset frequencies depending on the carrier frequency. The discriminator system s hows a similar noise peaki ng at the same offset frequency as the spectrum analyzer shows. The cl ose-in phase noise in the disciminator system follows the discriminator system sensitivity leve l due to the external VCOs superior noise characteristics. For higher offset frequency (>1MHz), the phase noise shows rapid drop as explained in previous measurements.

PAGE 173

173 Figure 8-14. Phase noise measurement for 0. 8GHz 0dBm input generated by the commercial external VCO (mini-circuits ZX95-1700W-S). Figure 8-15. Phase noise measurement for 0. 6GHz 0dBm input generated by the commercial external VCO (mini-circuits ZX95-1700W-S).

PAGE 174

174 Figure 8-16 shows 600MHz VCO pha se noise measurement resu lts after compensating for the gain roll-off. The gain roll-o ff compensation is performed by adding 20 log( fm/106) on the phase noise results ranging from 1MHz to 10MHz. With proper compensation of the system response, the proposed system can measure the accurate phase noise of DUT as long as the system sensitivity is low enough. Figure 8-16. Compensated phase noise measurem ent for 0.6GHz 0dBm input generated by the commercial external VCO (mini-circuits ZX95-1700W-S). The measured results for several DUTs demonstr ate the possibility of on-chip phase noise evaluation ranging from 3kHz to 2MHz. The main lim itations of this system arise from the poor system sensitivity level for low offset frequencies and the operational bandwidth limitation of active RC filter for high offset frequency (> 1MHz). The gain roll-off at higher offset frequencies can be compensated since the gain drop ratio of OPAMP is known (-20dB/Decade). As shown in

PAGE 175

175 Figure 8-6, the system noise floor is lower th an the system sensitivity. Thus, the mixer downconversion noise and the noise ge nerated by active delay line and pha se shifter can be ignored up to 1MHz where the sensitivity and the system noi se floor intersect. In order to increase the system capability for phase noise evaluation, the whole system is optimized to lower the system noise level by designing each building block not to impose any additive noise. By considering the system noise analysis in Chapter 6, the mi xer should be optimized to minimize the noise and the active RC filter needs to be optimized in order not to generate excessive noise. An active RC filter also needs to be designed to have a wide operational bandwidth and not to limit the range of the offset frequency. 8.5. Conclusion This work demonstrates an on-chip phase noise measurement for the first time. The proposed phase noise measurement system is used to be measured various noisy sources to check the systems performance. The measurement resu lts show an accurate phase noise performance ranging from 3kHz to 1MHz. The system sensitiv ity is achieved -135dBc/Hz at 100kHz offset and -155dBc/Hz at 1MHz offset. The measuremen t limitations are mainly due to the system sensitivity at lower offset frequency and to gain roll-off at higher offset frequencies. For higher offset frequency response, the gain roll-o ff can be compensated through mathematical manipulation with the consideration of OPAMP gain roll-off in the signal path. The proposed system measurement shows the pos sibility of cost re duction by replacing the expensive phase noise test equi pments with the simple 1mm x 1.5mm chip. The system sensitivity can be enhanced by increasing the do uble-balanced mixer gain or by increasing the signal delay time in the discriminator. However, the mixer should be considered a primary source of noise generation since it aff ects close-in phase noise sensitivity.

PAGE 176

176 CHAPTER 9 SUMMARY AND CONCLUSION 9.1. Summary In this dissertation, balun integrated RF/M icrowave probes and an embedded phase noise measurement system are designed for RF ICs test ing. The balun integrated probe is analyzed first to find the optimum design parameters and is simulated with aid of Ansoft HFSS and Agilent ADS. The final design is fabricated in Cascade Microtech Thin Film Technology. The embedded phase noise measurement system is analy zed in terms of the noise and the system gain and fabricated in the IBM8HP process. A new embedded phase noise measurement system is proposed based on the previously pu blished FM discriminator method. In chapter 1 and chapter 2, the motivation and inspiration of this Ph.D work are introduced and the background of this work is explained. Chapter 3 presents a new Marchand balun analysis. The new method introduces the extraction of an optimized design that depends on the input or output termination impedance variation. A full SPICE simulati on demonstrates the new analysis. The analysis provides the optimized design equations for a balun integrated probe. Chapter 4 and 5 shows the integration of a RF/Microwave balun probe using transmission lines finite ground broadside coupled lines based on coplanar strip and co planar waveguide that create difficulty in the extraction of the structure dimensions. The structures presented make it difficult to extract the characteristic paramete rs due to the long simulation time and the large effort when one uses a commercial EM solver. In this work, new closed form equations for coplanar strip line and coplan ar waveguide are developed to extract the desired design parameters. The analyses are based on the c onformal mapping method a nd verified through a comparison with FEM based simulations. The fina l designs are simulated with Ansoft HFSS in

PAGE 177

177 order to consider the discontinuities where the tr ansmission transition occurs to the outside world. The balun integrated probes are implemented in Cascade Microtech thin film technology. The measured results are compared with the final design simulations and show good agreement. Chapter 6 introduces an embedded phase noise measurement system and explains the basic theory of phase noise and conventional pha se noise measurement methods. Through the comparison between conventional measurement me thods, a delay-line-based phase noise system is chosen for implementing an embedded system In order to optimize the performance of the embedded measurement system, the proposed system is analyzed in terms of noise and system gain. System design considerations are presente d through the analysis. Final system validity is demonstrated through a system simulation perf ormed by Agilent ADS DSP based simulations. Chapter 7 shows a system implementation in IBM8HP technology. The entire system and its components are optimized, designed and fabr icated. The active balun is implemented by common-source/common gate topology. The de sign is optimized for a 1 GHz operational frequency. The proposed delay line can achieve 0 dB gain and 3 ns delay at a 1GHz operational frequency by introducing a level shifting technique in order to prevent the signal from distorting. A phase shifter also be used in a circuit module similar to a delay line except that interface to a symmetric load to control signal quadrature and ti me delay is required. A self-biasing technique makes up for the output DC level variations. The double balanced mixer in this system works as a phase detector while it suppr esses all fundamental and harmoni c signal components and leaves only the noise response. In order to achieve a fl at noise response up to 100 MHz, an active RC filter uses a feedback capacitance to increase the operational bandwidth a nd the system stability. Chapter 8 shows the final system measurement me thod which results in a low noise floor and a high sensitivity. Appendix A and B explain the pa rameter extraction of broadside coupled CPS

PAGE 178

178 and CPW coupled line equati ons through the conformal mapping method. The closed form equation is presented and veri fied by 3-D EM simulations (H FSS). Appendix C explains the phase noise system noise floor de pending on key circuits in the sy stem causing mismatch due to process variation and mixer input mismatch. Al so, Appendix D shows the systems limitation based on the FM discriminator. The system accur acy dependence on the discriminator delay time is explained. 9.2. Conclusion RF IC test cost is becoming a major part of chip manufacturing cost thanks to recent mass production technology. In order to reduce the test cost of RF ICs, much research has been performed over the last few decades but further work is needed. This dissertation work is finding test cost reduction methods by using differential probes a nd embedded test systems. Many academic and organizations study RFICs to improve their functions. But the same effort is not put into test. Particularly, for the differential circuits, expensive test equipment is required due to the lack of alternative on-chip test. In this work, by developing the balun integrat ed probe, expensive differential measurement equipment can be replaced with the conventiona l two port equipment. A new analysis method for the Marchand balun is introduced that optimizes the balun design for the circuit applications. For example, some designs do not optimize their load terminations to 50 The proposed analysis makes it possible to design a balun as a function of the termination impedance variation. Also, in order to build a balun integrated probe, a new field analysis method is presented through the conformal mapping method. The proposed field analysis method introduces a close-form equation for a specific transmission structure. Thus, the design time to find the optimized parameters for a particular circuit application grea tly is reduced. The fabricated balun integrated

PAGE 179

179 probe through the proposed analys es achieves superior performa nce compared to conventional balun designs. An embedded phase noise measurement system based on FM discriminator methods is developed for RFIC production test. The conventional measurements using this method need a complicated and arduous test set-up and extensive test time to complete device characterization. However, the system in this dissertation can easily convert the phase noise at high frequency carrier into baseband noise. Thus the required measurement step can be reduced to a simple step which checks baseband noise at DC with a base band frequency analyzer or an ADC and DSP system. In addition, the system introduces au to-adjustment to find the optimum measurement point by controlling a variable phase shifter. Co mpared to a conventiona l external phase noise test system such as the HP E5500, the embedded test system can save test time by removing the input quadrature manual adjustment. The phase noise system is implemented in IBM8HP technology. The measured system performance shows an effective accuracy from 3kHz to 1MHz without gain compensation. The sensitivity is -155dBc at 1M Hz offset frequency.

PAGE 180

180 APPENDIX A EXTRACTION OF BROADSIDE C OUP LED COPLANAR STRIPLINES CHARACTERISTIC PARAMETERS WITH FINITE GROUND PLANE A.1. Analysis of Broadside Coupled Coplanar Striplines (CPS) with finite ground plane Figure A-1. Broadside coupled c oplanar stripline (CPS) cross-section with finite ground plane Figure A-1 shows the symmetric finite ground broadside coupled coplanar striplines cross-section with three dielectr ic layers. Signal line width is a and the gap between the signal line and ground is b-a The ground width is c-a Due to the limited ground, the field distribution will distort a lot, which makes the big difference of the characteristics of both finite and infinite ground coupled-line structures. Dielec tric constant and height of th e dielectric between the signal lines are r1 and h1, respectively. Dielectric constant of the dielectric located on upper and lower signal lines are r2 and h2, respectively. Let us call them the intermediate and upper dielectric. Analysis of this structure starts from the isolation of two different modes [A.1], which are the even mode and the odd mode as shown in Figure A-2.

PAGE 181

181 A B Figure A-2. Field dist ribution under A) even mode exci tation. B) odd mode excitation. A.2. Even Mode The field distribution is similar to the case of infinite ground plane as shown in Figure A-2 A). The total even mode capacitance per unit leng th can be obtained by the sum of the three components, Ce1, Ce2 and Ce3, representing the electric field in the intermediate region, the upper dielectric region and the air region with the pa rtial capacitance method [A .2] [A.3] [A.4][A.5].

PAGE 182

182 Figure A-3. Detailed conformal mapping pr ocedure for the even mode excitation Figure A-3 shows the detailed procedure for th e conformal mapping method. By the partial capacitance method, the total capac itance can be divided into thr ee different region capacitances such as the intermediate dielectric region capac itance, the upper dielectric region capacitance and air-filled region capacitance. Two conductor lines form the air region capacitance and the dielectric region capacitances. The transformation from Z -plane to T -plane uses equation A-1 through A-2 for the intermediate dielectric region and the upper dielectric region, respectively. 1exp h z t (A-1)

PAGE 183

183 2exp h z t (A-2) The final transformation from T -plane to W -plane is performed by Schwarz-Christoffel transformation by equation A-3. ))()()((0 c b atttttttt dt w (A-3) The final even mode capacitance is described by equation A-4. )( )( )( )( 1 )( )(3 3 0 2 2 20 1 1 10321 e e e e r e e r eeeEkK kK kK kK kK kK CCCC (A-4) where K(k) is the complete elliptic integr al of the first kind with module k and K'(k) its complement. acb bca k h a h c h b h b h c h a k h a h c h b h b h c h a ke e e 3 2 2 2 2 2 2 2 1 1 1 1 1 1 1exp exp1 exp exp exp1 exp exp exp1 exp exp exp1 exp (A-5) The effective dielectric consta nt and the characteristic impedance are derived as the equation A-6 and A-7. )( )( )( )( )( )( 1 )( )( 1 13 3 1 1 2 2 2 1 1 1 e e e e e e r e e r EeffkK kK kK kK kK kK kK kK (A-6)

PAGE 184

184 )( )( )( )( 1203 3 1 1 0 e e e e Eeff EkK kK kK kK Z (A-7) A.3. Odd Mode With the assumption of an electric wall in th e center of the coupled lines, the analytic expression for the odd mode capacitance per unit length can be derived by the sum of three components, Co1, Co2 and Co3, representing the electric field in the intermediate region, the upper dielectric region and the air region with the partial capacitance method. Co2 and Co3 are similar to the even mode excitation while Co1 has another ground plane due to an electric wall, which complicate the analysis. For the derivation of Co1, the analysis needs another step by dividing Co1 in two parallel rectangular capacitances. Figure A-4. Detailed conformal mapping procedure for the odd mode excitation

PAGE 185

185 Figure A-4 shows the detailed procedure for the odd mode excitation. The additional procedure for Co1 is performed as shown Figure A-5. The transformation from Z -plane to T plane uses equation A-8 through A-9 for the in termediate dielectric region and the upper dielectric region, respectively. 1exp h z t (A-8) 2exp h z t (A-9) Figure A-5. Conformal mapping procedure for the intermediate dielectric region in odd mode excitation. The final transformation from T -plane to W -plane for Co2 and Co3, is performed by Schwarz-Christoffel transf ormation by equation A-10.

PAGE 186

186 64; ))()()((0ori tttttttt dt wib a (A-10) After the transformation to W-plane, the rectangular capacitance of Co1 is divided into two parallel capacitances in Figure A-5 by assuming a magnetic wall for the dashed line in Figure A5 [A.6]. The transformation is performed by equation A-11 and A-12. 1 22 cosh H z t (A-11) ))()()((d c b atttttttt td w (A-12) The final even mode capacitance is described by equation A-13. )( )( )( )( 1 )( )( )( )(3 3 0 2 2 20 2_1 2_1 1_1 1_1 10321 o o o o r o o o o r oooOkK kK kK kK kK kK kK kK CCCC (A-13) where K(k) is the complete elliptic integr al of the first kind with module k and K'(k) its complement. acb bca k h a h c h b h b h c h a k H WW H WW k H W H W k h a h b h b h a ko o o o o 3 2 2 2 2 2 2 2 1 41 1 31 2_1 1 4 1 2 1_1 1 1 1 1 1exp exp1 exp exp exp1 exp 2 tanh 2 tanh1 2 tanh 2 tanh1 exp1 exp exp1 exp (A-14)

PAGE 187

187 W1, W2, W3, W4 and H1 can be derived as shown in equation A-15. 2 1 exp exp exp1 exp arcsin 1 exp 1 exp arcsin )( )(32 4 1 1 1 1 1 3 1 1 1 2 1 1 1 1WW W k h c h b h c h b FW k t h b t h b FW kK kK H Wo o o o (A-15) where F(,k) is the incomplete elliptic integral of th e first kind, written in Jacobis notation. The effective dielectric constant and the characteristic impe dance are in equation A-16 and A-17. )( )( )( )( )( )( )( )( 1 )( )( )( )( 1 13 3 2_1 2_1 1_1 1_1 2 2 2 2_1 2_1 1_1 1_1 1 o o o o o o o o r o o o o r OeffkK kK kK kK kK kK kK kK kK kK kK kK (A-16) )( )( )( )( )( )( 1203 3 2_1 2_1 1_1 1_1 0 o o o o o o Oeff OkK kK kK kK kK kK Z (A-17) Simple and accurate formulas are available for so lving the complete elli ptic integral of the firs kind [A.7]. These ar e given in equation A-17.

PAGE 188

188 15.0 112ln 5.00 112ln )( )(2 2k kk k kk kK kK (A-17) where k'= (1-k2)

PAGE 189

189 APPENDIX B EXTRACTION OF BROADSIDE COUPLED COPLANAR WAVEGUIDE CHARAC TERISTIC PARAMETERS WITH FINITE GROUND PLANE B.1. Broadside Coupled Coplanar Waveguide (CPW) with finite ground plane. A new analytic expression for the broadsid e coupled CPW with finite ground plane is proposed for the first time. This method can be us ed on the transmission line circuit modeling in the standard CMOS process due to their simplicit y. Figure B-1 shows th e cross-section of the analyzed structure. Due to thei r finite ground plane, the analysis is much complicated compared to infinite ground plane case. Figure B-1. Cross-section of br oadside coupled coplanar waveguide with finite ground plane. The field distributions of both even and odd mode are shown in Figure B-2. The finite ground plane causes the field distortion and the final characteristics will be very different from the ones of an infinite ground plane case. The analysis starts from isolating the even and odd mode excitation. The even mode excitation assume a magnetic wa ll in the center line while the odd mode excitation assume a electric wall [B.1].

PAGE 190

190 A B Figure B-2. Field distri bution of the broadside coupled CPW under A) an even mode excitation and B) an odd mode excitation with a bottom and top ground plane. B.2. Even Mode Figure B-3 shows the field dist ribution of the upper half of the finite ground broadside coupled coplanar waveguide for even mode ex citations. The bottom dashed line describes the magnetic wall while both signal lines carry the same amplitude and phase signals and are symmetrical. This assumption is always true as lo ng as the structure behaves as a coplanar line [B.1]. The half plane of Figure 4-3 will be used to derive the even mode capacitance. The total even mode capacitance per unit length can be obtained by the sum of three components, Ce1, Ce2 and Ce3, representing the electric fiel d in the lower dielectric regi on, the air region and the upper dielectric region with the pa rtial capacitance method [B.2].

PAGE 191

191 Figure B-3. Field distri bution of the finite ground broadsid e coupled CPW under an even mode excitation. Figure B-4 describes the deta iled procedure for the CPW conformal mapping. The total capacitance can be divided into three different regions; there are the lower dielectric region, the air-filled region and the upper diel ectric region. In the air regi on, two conductor lines form the air region capacitance and the dielec tric region capacitance [B.3]. Figure B-4. Detailed conformal mapping pr ocedure for the even mode excitation.

PAGE 192

192 The transformation uses equation B-1 through B-3 for the air region and the dielectric region. 1 22 sinh h z t (B-1) 2zt (B-2) 1 22 cosh h z t (B-3) The Schwarz-Christoffel transformation from T -plane to W -plane is in equation B-4. ))()()((0 cb atttttttt dt w (B-4) The final even mode capacitance is described by equation (B.5). )( )( 12 )( )( 2 )( )( 23 3 20 2 2 0 1 1 10 e e r e e e e r EkK kK kK kK kK kK C (B-5) where K(k) is the complete elliptic integr al of the first kind with module k and K(k') its complement. 2 2 2 2 2 2 2 2 2 2 3 22 22 2 1 2 1 2 1 2 1 2 1 1 12 sinh2 sinh1 2 sinh2 sinh1 2sinh 2sinh 1 1 2 sinh2 sinh1 2 sinh2 sinh1 2sinh 2sinh hc ha hc hb hb ha k ca cb b a k hc ha hc hb hb ha ke e e (B-6) The effective dielectric consta nts and the characteristic impe dance are derived as equation B-7 and B-8.

PAGE 193

193 )( )( )( )( )( )( 1 )( )( 1 12 2 1 1 3 3 2 1 1 1 e e e e e e r e e r EeffkK kK kK kK kK kK kK kK (B-7) )( )( )( )( 602 2 1 1 0e e e e Eeff EkK kK kK kK Z (B-8) The asymptote of these equation when th e ground plane width grows infinite ( c ) agrees with the infinite ground plane case [B.4]. B.3. Odd Mode The field distribution of Figur e B-5 explains the capacitance of the odd mode excitation. There is an electrical wall in the center of the coupled lines. The analytic expression for the odd mode capacitance per unit lengt h can be derived by the sum of three components, Co1, Co2 and Co3, representing the electric field in the lower dielectric region, air region and the upper dielectric region. Figure B-5. Field distri bution of the CPW with finite ground plane under an odd mode excitation. Figure B-6 shows the conformal mapping procedure for the dielec tric region. The electrical wall is a virtual ground. The mapping procedure is divided into three parts via the partial capacitance method as shown in Figure B-6. The air region capacitance and the upper dielectric region capacitance are the same as the even m ode. But the lower dielectric region capacitance is

PAGE 194

194 more complicated to analyze due to the finite ground widths. For an odd mode excitation, the lower dielectric region capacitance is n eeded to extract additional parameters. Figure B-6. Detailed conformal mapping pr ocedure for the odd mode excitation. The transformation into t-plane for the lowe r dielectric region field is performed as equation B-9. 1 22 sinh h z t (B-9) The remaining steps of the conformal mapping use the Schwarz-Christoffel transformation as shown in equation B-10.

PAGE 195

195 1 1 12 tanh 2 tanh h b h a ko (B-10) After the transformation to the w-plane, the rectangular capacitance is divided into two parallel rectangular capacitances in Figure B-7 (b) by assuming a magnetic wall for the dashed line in Figure B-7 (a) [B.5]. Figure B-7. Conformal mapping procedure for the lo wer dielectric region in odd mode excitation. Equation B-11 and B-12 perform the transformation. 1 22 cosh H z t (B-11)

PAGE 196

196 ))()()((0 c b atttttttt td w (B-12) Finally, the odd mode capacitance is derive d as shown in equation B-13 to B-15. 3 3 20 2 2 0 2_1 2_1 1_1 1_1 1012 2 2o o r o o o o o o r OkK kK kK kK kK kK kK kK C (B-13) where 33 22 1 31 1 41 2_1 1 4 1 2 1_12 tanh 2 tanh 1 2 tanh 2 tanh 1eo eo o okk kk H WW H WW k H W H W k (B-14) W1, W2, W3, W4 and H1 can be derived. 2 2 tanh 2 tanh arcsin 2 tanh 2 tanharcsin )( )(32 4 1 1 1 3 1 1 1 2 1 1 1 1WW W k h c h b FW k h c h b FW kK kK H Wo o o o (B-15) where F(, k) is the incomplete elliptic integral of the first kind, written in Jacobis notation. The effective dielectric consta nts and characteristic impeda nce are in equation B-16 and B17.

PAGE 197

197 )( )( )( )( )( )( )( )( 1 )( )( )( )( 1 12 2 2_1 2_1 1_1 1_1 3 3 2 2_1 2_1 1_1 1_1 1 o o o o o o o o r o o o o r OeffkK kK kK kK kK kK kK kK kK kK kK kK (B-16) )( )( )( )( )( )( 1 602 2 2_1 2_1 1_1 1_1 0 o o o o o o Oeff OkK kK kK kK kK kK Z (B-17) The expression derived in this section can eas ily be extended to include infinite ground broadside coupled CPW.

PAGE 198

198 APPENDIX C SYSTEM MISMATCH RESPONSE C.1. Signal Distortion due to Delay Line and Phase Shifter It is important to understand the input signal distortion after passi ng a signal through an analog delay line circuit. A transient simulation of the analog delay line in the discrimator system was performed and the simulation output was converte d to the spectral domain in order to see the degree of distortion. An analog delay line will intr oduce signal distortion, inevitably, even if the analog delay line is designed to minimize the signal distortion. Fi gure C-1 indicates the displayed simulation points in yellow in order to help understand of the system functionality. Figure C-1. System simulation block diagram. The transient simulation aims to show the input signal spect rum and output signal spectrum at different delay line ou tput points in order to establis h signal distortion levels. Figure C-2 shows the physical points in th e circuit simulation used to set and detect the input signal and output signals. A sinusoidal wavefo rm is chosen for the input signal in order to generate a clean spectrum at the input. The simulation results show the delay line output distortion level by comparing the input and output spectrums. Figure C-3 A) shows the 0 dBm input signal spectrum at 1GHz and B) shows the delay line output spectrum at the marked point in Figure C-2.

PAGE 199

199 Figure C-2. Delay line circuit points for the simulation input and output. The active delay line has a limited peak-to-peak voltage swing which restricts the maximum output power (around -3dBm). The funda mental output spectrum (-3dBm at 1GHz) in Figure C-3 B) shows the input sp ectrum with a small loss (-3dB) and includes other higher order harmonics. Compared to the fundamental signal le vel, the higher order ha rmonics are negligible since the higher order harmonics are 40 dB lower than the fundamental signal. The analog delay line is designed for minimizing unwanted signal di stortion. This simulation results shows a very low level of signal distortion over the 1GHz band of interest. Another important observation of this simulation result comes from looking at the noise level. The input signal noise level is around -70dBm for entire frequency range of simu lation. The analog delay line is designed to achieve around 0dB gain so the output signal noise level shows almost the same level of input noise up to 1.5GHz since the operational frequenc y of the analog delay line is around 1.5 GHz. Beyond 1.5GHz, the signal and noise show lower valu es since the analog dela y line gain has rolloff beyond 1.5GHz.

PAGE 200

200 A B Figure C-3 Spectrum of A) the i nput B) the delay line output For low level signals, the anal og delay line achieves around 0 dB gain for 1GHz signals by controlling delay line gain using the inverting amplifier curren t source bias. Figure C-4 shows the fundamental signal power which depends on i nput signal power at 1GHz. As in a typical amplifier, the analog delay line shows linear gain. The gain comp ression occurs at -3dBm input

PAGE 201

201 power which is the same power level as th e maximum achievable output power. For a input power higher than -3dBm, the analog delay line shows gain compression that is shown in Figure C-4. Figure C-4. Analog delay line output as a function of input power at 1GHz. Figure C-5 shows the phase sh ifter input and output power at 1GHz. The phase shifter shows a similar response to the analog delay line except the phase shifter shows a wider operational bandwidth than that of the analog delay line. The higher order harmonics show magnitudes 40 dB lower than the fundamental sign al which can be ignored. The variable phase shifter output suppresses even order harmonics so that the transient response will shows a little rectangular waveform shape. In this case, the suppres sion level is relativel y small, thus, the signal experiences only a little dist ortion. The variable phase shifter achieves a very low level of signal distortion. The phase shifter has a 1.8 GHz operational bandwidth. Thus, the signal and noise amplify up to 1.8GHz. The phase shifter is in cutoff beyond 1.8 GHz and should not be used at frequencies higher that 1.8 GHz.

PAGE 202

202 A B Figure C-5. Variable phase shifter A) input spectrum and B) output spectrum C.2. System Mismatch Response The output response of the discriminator system mainly depends on the input imbalance at the mixer input since the mixer inputs which are not in quadrature, introduce additional noise beside the DUTs phase noise. A si mulation is performed when the mixer input is in quadrature and not in quadrature. The input has the same signal applied as used in the analog delay line

PAGE 203

203 transient simulation (sinewave of 1 GHz) and phase shifter simulation is shown in Figure C-3 A). The simulation results for the mixer input signal mismatched case (10 mismatch) are displayed in Figure C-6 and for the matched case are displayed in Figure C-7. Figure C-8 shows the noise floor comparison between the matched case and mismatched case and includes the degree of the mismatch. The mismatched case shows a higher noise floor which impedes low level phase noise signal detection. Thus, the sensitivity of th e system will degrade. Equation C-1 shows the sensitivity level of this case. The resolution bandwidth for this simulation is 20MHz and the offset frequency is 20MHz. 77[/] 20log()310log() 57(131)20log(210)310log(210)148 dBc/Hzmv m dmfdBcHzSfKfB L (C-1) A B Figure C-6. Output spectrum A) mismatched (input mismatch 10O) on a linear scale B) mismatched in log scale.

PAGE 204

204 A B Figure C-7. Output spectrum A) matched in linear scale B) matched in log scale. The matching condition can be observed by ch ecking the DC power level. In this simulation case, DC level is -9dBm for a matched signal to the mixer while the mismatched case shows higher power level (-2dBm). Figure C-7 sh ows an important observation. Compared to Figure C-7 A), the signal levels such as 1GHz and higher order harmonics show almost the same signal power but with a lower noise floor. Thus the mixer input matching conditions determine the noise floor level of the system. For matched case, the system noise floor can be calculated by equation (C.2). 77[/] 20log()310log() 68(131)20log(210)310log(210)159 dBc/Hzmv m dmfdBcHzSfKfB L (C.2) The system sensitivity is -159dBc/Hz. The matched case obviously shows great sensitivity enhancement. Figure C-8 shows the system response as a func tion of the level of mismatch. If the mixer inputs are in quadrature, the system response shows the lowest noise level since the mixer cancels out the redundant terms in DUT signal. Th e matched case introduces the lowest system noise floor as shown in Figure C-8. As the mismat ch increases, the noise floor level increases to

PAGE 205

205 some extent. More than 10 of the mismatch shows almost the same noise floor level. Figure C-9 shows the system response depending on the leve l of the input mismatch in log scale. The matched case shows very low noise level fo r closed-in offset frequency (<300 MHz). Figure C-8. System responses dependi ng on the mismatch in linear scale. Figure C-9. System responses depend ing on the mismatch in log scale.

PAGE 206

206 APPENDIX D SYSTEM LIMITATION The frequency discrim inator method has an inherent limitation during measurement of very close-in phase noise and the specific offs et frequency which is determined by time delay ( d) of the delay line. In this section, the system limitations and accurate measurement methods are explained. D.1. The Discriminator Transfer Response The discriminator system response is derived in chapter 6. Equation D-1 is the typical system transfer response of the FM discriminator. 2sin sinsin 1 2 (For 1) 2 = 2out md m md md dm md d md df VKf f ff Kff ff Kf (D-1) A system sensitivity of the frequency discriminator is determined by the transfer response as shown in equation D-1. It is desirable to make both the phase detector constant K and the amount of delay d large. Then, the voltage fluctuations out of a frequency discriminator will be measurable for even small frequency fluctuations f The magnitude of the sinusoidal output term of the frequency discriminator is proportional to sin( fmd)/( fmd). This implies that the output respons e will have peaks and nulls, with the first null occurring at fm=1/ d Increasing the rate of a modula tion signal applied to the system will cause nulls to appear at frequency multiples of 1/ d

PAGE 207

207 Figure D-1. Nulls in sensitivity of delay line discriminator [D.1]. To avoid having to compensate for the sin(x)/x response, measurements are typically made at offset frequency much less than 1/ d. It is possible to measure at offset frequencies out to and beyond the null by scaling the measured results using the discriminator transfer equation. However, the sensitivity of the system gets very poor near the nulls. The transfer function shows that increasing d increases the sensitivity of the system. However, increasing d also decreases the offset frequencies that can be measured w ithout compensating for the sin(x)/x response. The Discriminators with 50ns line are usable to offs ets of 10MHz. Increasing the delay also increases the attenuation of the line. While this has no dir ect effect on the sensitiv ity provided by the delay line, it does reduce the signal into the phase detector and can result in decreased K and decreased system sensitivity. In the on-chip discriminator system, the de lay is chosen to be 3.5ns. However, the discriminator constant is larger than commercial instruments sin ce the proposed system uses an active mixer instead of using a pass ive mixer in typical systems.

PAGE 208

208 Equation D-2 exhibits the highest offset fre quency of interest for the proposed system. ,1 45 MHz 2mhigh df (D-2) ,1 285 MHz mnull df (D-3) Equation D-3 indicates the first null of the system. The highest offset frequency of interest means the maximum measurable frequenc y without compensating this null.

PAGE 209

209 LIST OF REFERENCES [1.1] S. Ozev, A. Orailoglu and C. V. Olgaar d, Multilev el Testabilit y Analysis and Solutions for Integrated Bluetooth Transceivers, IEEE Design and Test vol. 19, no. 5, pp. 82-91, Oct. 2002. [1.2] J. Ferrario, R. Wolf and S. Moss, A rchitecting Millisecond Test Solutions for Wireless Phone RFICs, Proc. International Test Conf. pp. 1325-1332, 2003. [1.3] M. Jarwala, L. Duy and M. S. He utmaker, End-to-End Test Strategy for Wireless Systems, Proc. International Test Conf., pp. 940-946, 1995. [1.4] J. S. Yoon and W. R. Eisensta dt, Embedded Loopback Test for RF ICs, IEEE Trans. Instrumentation and Measurement. vol. 54, no. 5, pp. 1715-1720, Oct. 2005. [1.5] S. Bhattacharya and A. Chatterjee, Use of Embedded sensors for Built-In-Test of RF Circuits, Proc. International Test Conf. pp. 801-809, 2004. [1.6] J. Y. Ryu and B. C. Kim, Low-Cos t Testing of 5GHz Low Noise Amplifier Using New RF BIST Circuit, Journal of Electronic Testin g: Theory and Applications., vol. 21, no. 6, pp. 571-581, Dec. 2005. [1.7] S. Director, W. Maly and A. St rojwas, VLSI Design for Manufacturing: Yield Enhancement, 1ST ed., Norwell, MA, 1990, ch. 1. [1.8] D. A. Gahagan, RF(Gigahertz) ATE production testin g on wafer: options and tradeoffs, Proc. International Test Conf. pp. 388-395, 1999. [1.9] K. Jung, Broadband Balun Embedded Measurement for Differential Circuits, Ph.D. Dissertation, Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, 2007, chapter 1-4. [1.10] Integrated Balun Probes, Data sheet, GGB Industries Inc. [2.1] R. L. Campbell, High Frequenc y Differential Passive FET Direct Conversion Mixer/Modulator, 2006 International Microwave Sym posium, IEEE Microwave Theory and Technique Society pp. 922-925, Jun. 2006. [2.2] K. Jung, Broadband Balun Embedded Measurement for Differential Circuits, Ph.D. Dissertation, Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, 2007, chapter 1-4. [2.3] D. E. Bockelman a nd W. R. Eisenstadt, Pure-mode network analyzer for on-wafer measurements of mixed-mode S-para meters of differential circuits, IEEE Transaction on Microwave Theory and Techniques vol. 45, pp. 1071-1077, Jul. 1997. [2.4] R. Mongia, I. Bahl, and P. Bharti a,RF and Microwave Coupled-Line Circuits, 1ST ed., Artech House Inc., Norwood, MA, 1999, ch. 11.

PAGE 210

210 [2.5] N. Marchand, Transmissi on-Line Conversion Transformers, Electronics vol. 17, pp. 142-146, Dec. 1944. [2.6] M. He, Embedded substrate noise measurement for mixed-signal/radio frequency/microwave integrated circuits, Ph .D. Dissertation, Depa rtment of Electrical and Computer Engineering, University of Florida, Gainesville, FL, 2006, chapter 1-2. [2.7] W. R. Eisenstadt, R. M. Fox, Y. Qizh ang and T. Zhang,On-chip microwave test circuits for production IC measurements, 64th ARFTG Microwave Measurements Conference, pp.213-219, Fall. 2004. [2.8] J. Yoon, R. M. Fox, and W. R. Ei senstadt, Integrated Bi CMOS 10GHz S-parameter Module, Bipolar/BiCMOS Circuit and Technology Meeting pp. 1-4, Oct. 2006. [2.9] A. Valdes-Garcia, W. Khalil, B. Bakka loglu, J. Silva-Martinez and E. Sachez-Sinencio, Bulit-In Self Test of RF Transceiver SoCs: from Signal Chain to RF Synthesizers, Proc. of IEEE Radio Freq. IC Symp. pp. 335-339, 2007. [2.10] M. Jarwala, L. Duy and M. S. Heut maker, End-to-End Test Strategy for Wireless Systems, Proc. International Test Conf., pp. 940-946, 1995. [2.11] J. Yoon and W. R. Eisenstadt Embedded loopabck test for RF ICs, IEEE Transaction on Instrumentation and Measurements vol. 54, pp. 1715-1720, Oct. 2005. [2.12] A. Valdes-Garcia, W. Khalil, B. Bakka loglu, J. Silva-Martinez and E. Sachez-Sinencio,, On-chip Testing Techniques for Wireless RF Transceiver, IEEE Design&Test of Computers pp. 268-277, July. 2006. [2.13] Q. Wang, Y. Tang and M. Soma, GHz RF Front-end Bandwidth Time Domain Measurement, IEEE Proc. VLSI Test Symp. pp. 223-228, 2004. [2.14] A. Halder, S. Bhattacharya and A. Ch atterjee, Automatic multi-tone alternate test generation for RF circuits using behavioral models, Proc. International Test Conf. pp. 665-673, 2003. [2.15] S. Bhattacharya, G. Srinivasan, S. Cherubal, A. Halder and A. Chatterjee, System-level testing of RF transmitter specifications using optimized periodic bitstreams, IEEE Proc. VLSI Test Symp. pp. 229-234, 2004. [2.16] M. Takamiya, H. Inohara, and M. Mi zuno,On-chip jitter-spectrum-analyzer for highspeed digital designs, IEEE ISSCC Digest Technology Papers, pp. 350-352, Feb. 2004. [2.17] M. Ishida, et al .,A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input, IEEE ISSCC Digest Technology Papers pp. 512-513, Feb. 2005. [2.18] K. Nose, M. Kajita, and M. Mizuno,A 1 ps-resolution jitter-measurement macro using interpolated jitter oversampling, IEEE ISSCC Digest Technology Papers pp. 520-521, Feb. 2006.

PAGE 211

211 [2.19] J. Ferrario, R. Wolf and S. Moss, A rchitecting Millisecond Test Solutions for Wireless Phone RFICs, Proc. International Test Conf. pp. 1151-1158, 2002. [3.1] S. A. Maas and K. W. Chang,A Broadband, Planar, Doubly Balanced Monolithic Kaband Diode Mixer, IEEE Transaction on Microwave Theory and Techniques vol. 41, no. 12, pp. 2330-2335, Dec. 1993. [3.2] N. Marchand, Transmission-Line Conversion Transformer, Electronics, vol. 17, pp. 142-146, Dec. 1944. [3.3] W. K. Roberts, A new wide-band balun, Proc. IRE, vol. 45, pp. 1628-1631, Dec. 1957. [3.4] H. G. Oltman, The Compensated Balun, IEEE Transaction on Microwave Theory and Techniques, vol. mtt-14, No. 3, pp. 112-119, Mar. 1966. [3.5] C. M. Tsai and K. C. Gupta,A Generalized Model for Coupled Lines and Its Applications to Two-Layer Planar Circuits, IEEE Transaction on Microwave Theory and Techniques, vol. 40, pp. 2190-1299, Dec. 1992. [3.6] R. Schwindt and C. Nguyen,Comput er-Aided Analysis and Design of a Planar Multilayer Marchand Balun, IEEE Transaction on Microwa ve Theory and Techniques vol. 42, pp. 1429-1434, Jul. 1994. [3.7] J-W. Lee and K. J. Webb, Analysis and Design of Low-Loss planar Microwave baluns Having Three Symmetric Coupled Lines, IEEE MTT-S Int. Microwave Symp. Dig pp. 117-120, Jun. 2002. [3.8] J. H. Clotte, Exact Design of the Marchand balun, IEEE Europian Microwave Conf. Dig. pp. 480-484, Oct. 1979. [3.9] K. S. Ang and I. D. Robertson,Ana lysis and Design of Impeda nce-Transforming Planar Marchand Baluns, IEEE Trans. Microwave Theory Tech ., vol. 49, pp. 402-406, Feb. 2001. [3.10] W-Z. Chen and W-H. Chen, Symmetric 3D passive components for RF ICs application, Radio Freq. IC Symp. Dig ., pp. 599-602, Jun. 2003. [3.11] I. C. H. Lai and M. Fujishima, Psuedo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems, Design Automation Conf. Dig., pp. 106107, Jan. 2007. [3.12] I. C. H. Lai and M. Fujishima, CMOS on-chip stacked Marchand balun for MillimeterWave applications, IEICE Electon. Express, Vol. 4, No. 2, pp. 48-53, Jan. 2007. [3.13] Y. X. Guo, Z. Y. Zhang, and L. C. Ong, LTCC Full-Ma tching Marchand Balun, IEEE Europian Microwave Conf. Dig pp. 76-78, Sep. 2006.

PAGE 212

212 [3.14] Y. X. Guo, Z. Y. Zhang, and L. C. Ong, Design of Miniaturized LTCC Baluns, IEEE MTT-S Int. Microwave Symp. Dig pp. 1567-1570, Jun. 2006. [3.15] Z-Y. Zhang, Y-X. Guo, L. C. Ong, and M. Y. W. Chia, A New Planar Marchand Balun, IEEE MTT-S Int. Microwave Symp. Dig pp. 12-17, Jun. 2005. [3.16] D. M. Pozar, Microwave Engineering, 2ND ed., John Wiley & Sons Inc., Norwood, MA, 1998, ch. 7. [3.17] M. Chongcheawchamnan, Y. Choon, K. Bandudej, A. Worapishet and I. D. Robertson,On miniaturizati on isolation network of an all-ports matched impedancetransforming Marchand Balun, IEEE Microwave and Wire less Components Letter ., vol. 13, pp. 281-283, Jul. 2003. [4.1] J. Dunsmore, New methods and nonlinea r measurements for active differential devices, IEEE MTT-S Int. Microwave Symp. Dig pp. 1655-1658, Jun. 2003. [4.2] K. Jung, L. Campbell, P. Hanaway, M. F. Andrew, C. McCuen, W. R. Eisenstadt and R. M. Fox,Marchand Balun Embedded Probe, IEEE Trans. Microwave Theory Tech ., vol. 56, pp. 1207-1214, May. 2008. [4.3] C. P. Wen,Coplanar Waveguide: a surface strip transmissi on line for nonreciprocal gyromagnetic device application, IEEE Trans. Microwave Theory Tech ., pp. 1087-1096, Dec. 1969. [4.4] F. D. Paolo,Networks and De vices using Planar Transmission Lines, 1ST ed., CRC Press Llc., Boca Raton, FL, 2000, ch. 11. [4.5] R. Mongia, I. Bahl, and P. Bharti a,RF and Microwave Coupled-Line Circuits, 1ST ed., Artech House Inc., Norwood, MA, 1999, ch. 11. [4.6] G. E. Ponchak, L. P. B. Katehi and E. M. Tentzeris,Fini te ground coplanar (FGC) waveguide: Its characteristics and advantages for use in RF and wireless communication circuits, 3rd Int. Wireless. Communications Conf. Dig. pp. 75-83, Nov. 1998. [5.1] C. P. Wen, Coplanar Waveguide : A Surface Strip Transmission Line Suitable for Nonreciprocal Gyromagnetic Device Application, IEEE Trans. Microwave Theory Tech. vol. 17, No. 12, pp. 1087-1090, 1969. [5.2] F. D. Paolo,Networks and De vices using Planar Transmission Lines, 1ST ed., CRC Press Llc., Boca Raton, FL, 2000, ch. 10. [5.3] J. W. Huang, and C. K. C. Tzuang, Mode coupling avoidance of shielded conductor backe coplanar waveguide (CBCPW) using dielectric lines copensation, IEEE MTT-S Int. Microwave Symp. Dig pp. 149-152, Jun. 1994.

PAGE 213

213 [5.4] J. Hesselbarth, and R. Vahldieck, Leak age suppression in coplanar waveguide circuits by pattened backside metallization, IEEE MTT-S Int. Microwave Symp. Dig ., Vol. 3, pp. 13-19, Jun. 1999. [5.5] R. Spickermann, and N. Dagli Expe rimental analysis of millimeter wave coplanar waveguide slow wave structures on GaAs, IEEE Trans. Microwave Theory Tech., Vol. 42, pp. 1918 1924, Oct. 1994. [5.6] V. Milanovic, M. Ozgur, D. C. DeGroo t, J. A. Jargon, M. Gaitan, and M. E. Zaghloul, Characterization of broad band transmissi on for coplanar waveguides on CMOS silicon substrates, IEEE Trans. Microwave Theory Tech., Vol. 46, pp. 632-640, May. 1998. [5.7] K. J. Herrick, T. A. Schwarz, a nd L. P. B. Katehi, Si-micromachined coplanar waveguides for use in high frequency circuits, IEEE Trans. Microwave Theory Tech. Vol. 46, pp. 762-768, Jun. 1998. [5.8] A. Dehe, H.Klingbeil, C. Weil, and H. L. Hartnagel, Membrane supported coplanar waveguides for MMIC and sensor applicaiton, IEEE Microwave and Guided Wave Letter ., vol. 8, pp. 185-187, May. 1998. [5.10] S. S. Bedair and I. Wolff, Fast a nd Accurate Analytic Formulas for Calculating the Parameters of a General Broadside-C oupled Coplanar Waveguide for (M)MIC Applicaitons, IEEE Transaction on Microwave Theory and Techniques vol. 37, pp. 843-850, May. 1989. [6.1] Algie L. Lance, Wendell D. Seal, and Frederik Labaar, Inf rared and Millimeter Waves,Vol. 11, pp. 239-289, 1984. [6.2] Product Note 11729C-2,Phase Noise Characterization of Microwave Oscillator: Frequency Discriminator, Agilent Technologies. [6.3] D. M. Pozar, Microwave Engineering, 2nd ed., John Wiley & Sons Inc., Amherst, MA, 1998, ch. 6. [6.4] U. Rohde, Digital PLL Frequency Synthesizers: Theory and Design, 1st ed., Prentice Hall Inc., Eaglewood Cliffs, NJ, 1983, ch. 7. [6.5] D. B. Leeson, A simple model of feedback oscillato r noise spectrum, IEEE Proceedings Vol. 54, Feb. 1966. [6.6] T. H. Lee, Planar Microwave Engineer ing: A practical Guide to Theory, Measurements and Circuits, 1st ed., Cambridge Univer sity Press., New York, NY, 2004, ch. 17. [6.7] Product Note 11729B-1,Phase Noise Char acterization of Microwave Oscillator: Phase Detector Method, Agilent Technologies. [6.8] D. Scherer, The Art of Phase Noise Measurement Seminar, HP RF Microw. Meas. Symp. Oct. 1984.

PAGE 214

214 [6.9] R. E. Ziemer, and W. H. Tranter, P rinciples of Communications : Systems, Modulation, and Noise, 4th ed., John Wiley&Sons Inc., New York, NY, 1995, ch. 6. [6.10] F. Labaar, New discrimi nator boosts phase noise testing, Microwaves, Vol. 21, No. 3, pp. 65-69, 1982. [6.11] A. Lance, D. S. Wendell, and F. Labaar Phase noise and AM noise measurements in the frequency domain, Infrared and Milimeter Waves, Vol. 11, pp. 239-289, 1984. [7.1] B. Razavi, Design of Analog CMOS Integr ated Circuits, Intera ntional ed., McGraw-hill International Edition., Singapore, 2001, ch. 4. [7.2] M. Goldfard, J. B. Cole, and A. Platzker, A novel MMIC biphase modulator with variable gain using enhancement-mode FETs su itable for 3V wireless applications, IEEE Proceedings of Microwave and Millimeter Wave Monolithic Circuits Symposium pp. 99102, San Diego, CA, 1994. [7.3] H. Ma, S. J. Fang, F. Lin and H. Nakamu ra, Novel Active Differential Phase Splitters in RFIC for wireless applications, IEEE Trans. Microwave Theory Tech. vol. 46, No. 12, pp. 1087-1090, Dec., 1998. [7.4] L. M. Devlin, B. J. Buck, J. C. Clifton and A. W. Dearn, A 2.4 GHz single chip transceiver, IEEE Proceedings of Microwave and Mi llimeter Wave Monolithic Circuits Symposium pp. 23-26, June. 1993. [7.5] M. A. Do, W. M. Lim, J. G. Ma and K. S. Yeo, Design of a Phase Splitter for 3rd ISM Band, IEEE ISCAS, pp. 23-26, June. 2003. [7.6] B. Razavi, Design of Integrated Circui ts for Optical Communications, Interantional ed., McGraw-hill Higher Edition., Singapore, 2003, ch. 5. [7.7] T. H. Lee, Planar Microwave Engineer ing: A Practical Guide to Theory, Measurements and Circuits, 1st ed., Cambridge Univer sity Press., New York, NY, 2004, ch. 2. [7.8] T. H. Lee and J. F. Bulzachelli, A 155-MHz Clock Recovery Delay and Phase Locked Loop, IEEE Journal of Solid-State Circuits vol. 27, no. 12, pp. 1736-1746, Dec. 1992. [7.9] J. G. Maneatis, Low-jitter proces s-independent DLL and PLL based on self-biased techniques, IEEE Journal of Solid-State Circuits vol. 31, no. 11, pp. 1723-1732, Nov. 1996. [7.10] J. G. Maneatis and M. A. Horowitz, Precise delay generation us ing coupled oscillators, IEEE Journal of Solid-State Circuits vol. 28, no. 12, pp. 1273-1282, Dec. 1993. [7.11] J. Crols and M. Steyaert, A 1.5 GHz Highly Linear CMOS Downconversion Mixer, IEEE Journal of Solid-State Circuits vol. 30, no. 7, pp. 736-742, July. 1995.

PAGE 215

215 [7.12] R. Circa, D. Pienkowski and G. Boeck, Integrated 130nm CMOS Passive Ring Mixer for 5GHz WLAN Applications, IEEE SBMO MTT-S International Conf. .pp 736-742, July. 2005. [7.13] K. Kanazawa et al, A GaAs double-bala nced dual-gate FET mixer IC for UHF receiver front-end applications, IEEE Int. Microwave Symp. Digest., pp. 60-62, 1985. [7.14] J. Silva-Martinez, J. Adut, J. M. Roch a-Perez, M. Robinson, and S. Rokhsaz, A 60-mW 200-MHz continuous-time seventh order linear phase filter with on-chip automatic tuning system, IEEE Journal of Solid-State Circuits vol. 38, no. 2, pp. 216-225, Feb. 2003. [7.15] J. Silva-Martinez, M. S. J. Steyaert, and W. Sansen, A 10.7-MHz 68 dB SNR CMOS continuous-time filter with on-chip automatic tuning, IEEE Journal of Solid-State Circuits vol. 27, no. 12, pp. 1846-1853, Dec. 1992. [7.16] M. Vadipour, Capacitive feedback technique for wideband amplifiers, IEEE Journal of Solid-State Circuits vol. 28, no. 1, pp. 90-92, Jan. 1993. [7.17] A. Vasilopoulos, G. Vitzilaios, G. Theodoratos, and Y. Pa pananos, A Low-Power Wideband Reconfigurable Integrated Active-RC Filter with 73 dB SFDR, IEEE Journal of Solid-State Circuits vol. 41, no. 9, pp. 1997-2008, Sep. 2006. [8.1] R. E. Ziemer, and W. H. Tranter, P rinciples of Communications : Systems, Modulation, and Noise, 4th ed., John Wiley&Sons Inc., New York, NY, 1995, ch. 3. [8.2] W. Khalil, B. Bakkal oglu, and S. Kiaei, A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With -75dBc Single-Tone Sensitivity at 100 kHz Offset, IEEE Journal of Solid-State Circuits vol. 42, no. 12, pp. 2758-2765, Dec. 2007. [A.1] S. S. Bedair and I. Wolff, Fast and Accurate Analytic Formulas for Calculating the Parameters of a General Broadside-C oupled Coplanar Waveguide for (M)MIC Applicaitons, IEEE Transaction on Microwave Theory and Techniques vol. 37, pp. 843-850, May. 1989. [A.2] E. Chen and S. Y. Chou,Charcterist ics of Coplanar Transm ission Lines on Multilayer Substrates: Modeling and Experiment IEEE Transaction on Microwave Theory and Techniques, vol. 45, pp. 939-945, Jun. 1997. [A.3] G. Ghione,A CAD-oriented analytic al model for the losses of general asymmetric coplanar lines in hybrid and monolithic MICs IEEE Transaction on Microwave Theory and Techniques, vol. 41, pp. 1499-1510, Sep. 1993. [A.4] G. Ghione and M. Goano,The influe nce of ground-plane width on the ohmic losses of coplanar waveguides with finite lateral ground planes, IEEE Transaction on Microwave Theory and Techniques vol. 45, pp. 1640-1642, Sep. 1997.

PAGE 216

216 [A.5] C. Veyres and V. F. Hanna, Ext ension of the application of conformal mapping techniques to coplanar lines with finite dimensions, International Journal of Electronics, vol. 48, pp. 47-56, 1980 [A.6] K-K. M. Cheng,Analysis and Synthesi s of Coplanar Coupled Lines on Substrates of Finite Thicknesses, IEEE Transaction on Microwave Theory and Techniques vol. 44, pp. 633-639, Apr. 1996. [A.7] V. K. Tripathi, Asymmetric Coupled Transmission Lines in an Inhomogeneous Medium, IEEE Trans. Microwave Theory Tech., vol. MTT-23, No. 9, pp. 734-739, Sep. 1975. [B.1] S. S. Bedair and I. Wolff, Fast and Accurate Analytic Formulas for Calculating the Parameters of a General Broadside-C oupled Coplanar Waveguide for (M)MIC Applicaitons, IEEE Transaction on Microwave Theory and Techniques vol. 37, pp. 843-850, May. 1989. [B.2] G. Ghione,A CAD-orie nted analytical model for the losses of general asymmetric coplanar lines in hybrid and monolithic MICs IEEE Transaction on Microwave Theory and Techniques, vol. 41, pp. 1499-1510, Sep. 1993. [B.3] C. Veyres and V. F. Hanna, Ext ension of the application of conformal mapping techniques to coplanar lines with finite dimensions, International Journal of Electronics, vol. 48, pp. 47-56, 1980 [B.4] W. Hilberg,From a pproximations to exact relations for characteristic impedances, IEEE Trans. Microwave Theory Tech., vol. MTT-13, pp. 29-38, 1965. [B.5] K-K. M. Cheng,Analysis and Synthesi s of Coplanar Coupled Lines on Substrates of Finite Thicknesses, IEEE Transaction on Microwave Theory and Techniques vol. 44, pp. 633-639, Apr. 1996.

PAGE 217

217 BIOGRAPHICAL SKETCH Jae Shin Kim received the B.S. degree in elect ro nic engineering from Yonsei University, Seoul, Korea in 2001 and M.S. degree in electrica l engineering from Seou l National University, Seoul, Korea in 2003 and is currently working toward the Ph. D degree at University of Florida, Gainesville, FL. He worked as a Research Assistant for ISRC from 2001 to 2002. He worked as an Analog Design Engineer for Hynix Semiconductor in 200 3. During the spring and summer of 2007, he worked for Cascade Microtech, Beaverton, OR, on the 60GHz passive circuit design. He worked on RF IC and module design as a senior en gineer for SiRF Technology from Aug 2008. Mr. Kim was the recipient of Yonsei Outsta nding scholarship in 1994 and University of Florida Alumni Fellowship from 2003 to 2006.