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PAGE 1 INVESTIGATION OF PROCESS FABRICATION FOR LOWNOISE PTYPE DIFFUSED PIEZORESISTORS By ROBERT DIEME A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2009 1 PAGE 2 2009 Robert Dim 2 PAGE 3 To my father and mother. 3 PAGE 4 ACKNOWLEDGMENTS I would like to thank my advisor, Dr. Toshikazu Nishida, for his guidance and encouragement. I also would like to express my gratitude to Dr. Ma rk Sheplak, Dr. Gijs Bosman, and Dr. Kevin Jones, for their ideas and encouragement. I would also like to thank Dr. Louis N. Cattafesta III for help with my experime nts. I also thank Brya n L. Zachary, Nicholas G. Rudawski, Jack Y. Zhang, and all Interdisciplinary Microsystems Group (IMG) students for their help and support. I thank my father, mother, brother, sisters, and friends for their prayers, support, and encouragement through my study. Special thanks go to Rev. John D. Gillespie for his advice and all the people at St. Augustine Church. Finally, I thank God for all of the grace He gives me. 4 PAGE 5 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................4 LIST OF TABLES................................................................................................................. ..........9 LIST OF FIGURES.......................................................................................................................11 ABSTRACT...................................................................................................................................17 CHAPTER 1 INTRODUCTION................................................................................................................. .19 1.1 Motivation.....................................................................................................................19 1.2 Objective an d Outline...................................................................................................20 2 BACKGROUND................................................................................................................... .22 2.1 Test Vehicle: Piezoresistor............................................................................................22 2.1.1 Computation of Piezoresistor Resistance under NonDegenerate Approximation..................................................................................................23 2.1.1.1 Resistance computation with uniform carrier concentration under nondegenerate approximation...........................................................24 2.1.1.2 Resistance computation with nonuniform carrier concentration under nondegenerate approximation.................................................24 2.2 MEMS Piezoresistive Microphone...............................................................................26 2.2.1 MEMS piezoresistive Mi crophone Voltage Output..........................................26 2.2.2 MEMS Piezoresistive Microphone Sensitivity.................................................27 2.2.3 MEMS Piezoresistive Microphone Minimum Detectable Signal.....................27 2.3 Noise and Noise Power Spectral Density......................................................................28 2.4 Noise Sources in Piezoresistor......................................................................................29 2.4.1 Electrical Thermal Noise...................................................................................29 2.4.2 Mechanical Thermal Noise...............................................................................30 2.4.3 Low Frequency Noise.......................................................................................30 2.4.3.1 Hooges model....................................................................................31 2.4.3.2 McWhorters model............................................................................32 2.4.4 Shot Noise.........................................................................................................33 2.5 Defects in Semiconductors............................................................................................34 2.5.1 Bulk Defects......................................................................................................34 2.5.2 Interface Traps..................................................................................................35 2.6 Process Dependence of 1 /f Noise..................................................................................36 2.7 Summary.......................................................................................................................38 5 PAGE 6 3 PIEZORESISTOR DESIGN..................................................................................................41 3.1 Introduction................................................................................................................... 41 3.1.1 Piezoresistor Design with Un iform Doping Concentration..............................41 3.1.2 Piezoresistor Design with Gaussian NonUniform Doping Concentration......42 3.1.3 Fabrication NonIdealities.................................................................................43 3.1.3.1 Transient enhanced diffusion (TED)..................................................43 3.1.3.2 Oxidation enhanced diffusion (OED).................................................44 3.1.3.3 Impurity segregation...........................................................................44 3.1.4 Fundamental Physics That Affect El ectrical Activation of Impurities.............45 3.2 Piezoresistor Design Parameters...................................................................................47 3.2.1 Piezoresistor Impurity Profile...........................................................................47 3.2.2 Piezoresistor Resistance....................................................................................47 3.2.3 Piezoresistor Surface Area................................................................................48 3.2.4 Piezoresistor Volume........................................................................................48 3.3 Test Structures Design..................................................................................................48 3.4 Boron Profile Simulations.............................................................................................49 3.4.1 Analytical Calculation.......................................................................................49 3.4.2 Limited Source Diffusion: Ion Implantation.....................................................49 3.4.3 Annealing After Ion implantation.....................................................................50 3.4.5 Florida Object Oriented Pr ocess Simulator (FLOOPS)....................................51 3.4.5.1 Simplest FLOOPS (Fermi model)......................................................52 3.4.5.2 More accurate FLOOPS (Pair model)................................................52 3.5 Ptype Piezoresistor Implant and Annealing Condition................................................52 3.5.1 Piezoresistor Generation 1 (PG1)......................................................................52 3.5.2 Piezoresistor Generation 2 (PG2)......................................................................54 3.5.2.1 Boron implanted piezoresistors at 20 keV with a dose 7x1014 cm2...55 3.5.2.2 Boron implanted piezoresistors at 40 keV with a dose 7x1014 cm2 through SiO2.......................................................................................56 3.5.2.3 Boron solid source diffused piezo resistors for 25 min at 950 C.........56 3.5.2.4 Boron solid source diffused piezo resistors for 25 min at 950 C followed by phosphorus solid source diffusion for 5 min at 800 C....57 3.6 Additional Test Structures.............................................................................................57 3.6.1 Ptype Capacitor................................................................................................57 3.6.2 P/N Diode..........................................................................................................58 3.6.3 Van der Pauw Structure....................................................................................59 3.6.4 Carrier Concentration Test Structures...............................................................59 3.6.4.1 Spreading resistance technique...........................................................60 3.6.4.2 Secondary ion mass spectroscopy (SIMS) technique.........................60 3.6.4.3 Capacitancevoltage technique...........................................................60 3.6.4.4 Hall measurement technique...............................................................61 3.7 Summary.......................................................................................................................62 4 EXPERIMENTAL METHOD................................................................................................78 4.1 Piezoresistor Expe rimental Methods.............................................................................78 4.1.1 Piezoresistor IV Measurement.........................................................................78 6 PAGE 7 4.1.2 Piezoresistor Noise Measurements...................................................................79 4.1.2.1 Noise measurement setup...................................................................79 4.1.2.2 Equipment setting for noise PSD measurement.................................80 4.1.2.3 Noise power spectral density extraction.............................................80 4.2 P/N Diode Experimental Method..................................................................................82 4.2.1 P/N Diode DC CurrentVoltage........................................................................82 4.2.2 P/N Diode Shot Noise Measurement................................................................82 4.2.2.1 P/N diode noise measurement setup...................................................82 4.2.2.2 Shot noise power spectral density extraction......................................83 4.3 PType Capacitor Experimental Method......................................................................83 4.4 Transmission Electron Microscopy...............................................................................85 4.5 Van Der Pauw Structure...............................................................................................86 4.5.1 Sheet Resistance................................................................................................86 4.5.2 Line Width........................................................................................................86 4.5.3 Contact Resistance............................................................................................87 4.6 Hall Effect Measurement..............................................................................................87 4.7 Summary.......................................................................................................................87 5 FABRICATION AND MEASUREMENT RESULTS..........................................................91 5.1 Implantation, SolidSource, and A nnealing of Test Structures.....................................91 5.2 Characterization of Fabri cated Test Structures.............................................................92 5.2.1 Piezoresistor Test Structures.............................................................................92 5.2.2 Ptype Capacitor Test Structure........................................................................94 5.2.3 P/N Diode Test Structure..................................................................................95 5.2.4 Van der Pauw Test Structure............................................................................95 5.2.5 Hall Effect Test Structure..................................................................................96 5.3 Investigation of Process Dependence of 1 /F Noise......................................................97 5.3.1 Noise PSD of piezoresistors R6 for B, 20 keV, 7x1014 cm2, and 7o tilt...........98 5.3.2 Noise PSD of piezoresistors R6 for B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 101 5.3.3 Noise PSD of solidsource diffused piezoresistors R9 of wafers C1 and C2.102 5.4 Hooge Parameter and 1 /F Noise Analysis and Discussion.........................................103 5.5 Shot Noise Measurements...........................................................................................104 5.6 Number of Carrier Dependence of 1 /F Noise.............................................................105 5.6.1 Fabrication and Measuremen ts of Test Structures..........................................105 5.6.1 Noise PSD Measurements...............................................................................106 5.6.2 Analysis and Discussion.................................................................................107 5.7 Summary.....................................................................................................................108 6 DEFECTS MEASUREMENTS AND ANALYSIS.............................................................134 6.2 Bulk Defects in Piezoresistors....................................................................................134 6.2.1 CrossSection Transmission El ectron Microscopy (XTEM)..........................134 6.2.2 Plan View Transmission Electron Microscopy (PTEM)................................135 6.3 Interface Trap Density.................................................................................................136 6.4 Correlation of Noise Volta ge PSD to Defects............................................................137 7 PAGE 8 6.4.1 Noise Voltage PSD of 20 keV Boron Im planted Piezoresistors and Defects.137 6.4.2 Noise Voltage PSD of 40 keV Boron Implanted Piezoresistors through 0.1 m of SiO2 and Defects..................................................................................138 6.4.3 Noise Voltage PSD of Solid Source Diffused Piezoresistors and Interface Traps 140 6.5 Summary.....................................................................................................................140 7 CONCLUSION AND FUTURE WORK.............................................................................154 APPENDIX A PIEZORESISTIVITY...........................................................................................................15 7 B MEMS PIEZORESISTIVE MICROPHONE VOLTAGE OUTPUT..................................160 C DIFFRENCE BETWEEN HOOGE AND MCWHORTER 1/F NOISE MODEL..............162 D PROCESS FLOW................................................................................................................. 165 D.1 Generation 1 Process...................................................................................................165 D.2 Generation 2 Process...................................................................................................169 LIST OF REFERENCES.............................................................................................................175 BIOGRAPHICAL SKETCH.......................................................................................................180 8 PAGE 9 LIST OF TABLES Table page 31 Wafer characteristics used to fabr icate test structures generation 1..................................63 32 Process steps for piezoresistor test structures generation 1...............................................63 33 Wafer characteristics used to fabr icate test structures generation 2..................................63 34 Process steps for piezoresistor test structures generation 2...............................................64 35 Implant and annealing conditions of test structures generation 1......................................64 36 Dimensions, surface area, and volume of piezoresistors assuming uniform doping profile.................................................................................................................................65 41 Lownoise preamplifier SRS 560 setting...........................................................................89 42 Spectrum analyzer SRS 785 setting...................................................................................89 51 Resistance of piezoresistor s of generation 2 process.......................................................110 52 The junction depths and surface concentr ations of SIMS profiles of generation 2 process..............................................................................................................................110 53 Dimensions of the pMOSC1 and pMOSC2 of generation 2 process...............................110 54 Measured oxide thicknesses with Ellipsometer and pMOSC CV of generation 2 process..............................................................................................................................111 55 Dimensions of the three P/N diodes of generation 2 process..........................................111 56 MeasuredS R and W C R of generation 2 processes....................................................111 57 Computed electrical active dose, implanted dose, Q, and fraction of active dose AAN AANQ for each generation 2 process.............................................................................112 58 Hooge parameters of each of the three piezoresistors of process 2A (B, 20 keV, 7x1014 cm2, 7o tilt and 5 min dry, 5 min we t and 10 min dry at 900 C).........................112 59 Hooge parameter using number of carrier obtained from Hall Effect measurements of generation 2 process....................................................................................................112 510 Resistance of fabricated junction isolat ed piezoresistors of generation 1 process..........113 61 Slopes of regression lines and the 95 % confidence intervals.........................................142 9 PAGE 10 62 Line length, loop area, and faulted loop area of the B 20 keV and 40 keV with inert anneal and oxidation........................................................................................................142 A1 Piezoresistive coefficients of silicon................................................................................159 A2 Transverse and longitudinal piezoresistance coefficients of silicon for <110> direction...........................................................................................................................159 10 PAGE 11 LIST OF FIGURES Figure page 21 Piezoresistor A) plan view B) crosssection......................................................................39 22 Piezoresistors configured in Wheatstone bridge................................................................39 23 Trappingdetrapping model for 1 /f noise. A) Energy band diagram of trapping and detrapping at two trap levels, B) Lorent zian spectrum of two trap levels in comparison with thermal noise..........................................................................................40 24 Category I damage adapted from Jones et al. ................................................................40 31 Piezoresistor A) top view and B) crosssection.................................................................65 32 Uniform doping concentration...........................................................................................66 33 Nonuniform doping concentr ation (Gaussian Profile).....................................................66 34 Illustration of boron profiles when seconda ry effect such segregation (A) oxidation enhance diffusion (B), transient enhanced diffusion (C) are present during processing and comparison of a Gaussian profile with and a nonideal bor on distribution (D)..........67 35 Piezoresistors with same sheet resist ance, but different number of squares and resistance............................................................................................................................67 36 Piezoresistors with same resistance, different surface area and same number of square.................................................................................................................................68 37 Simulated boron profile for piezoresistor generation 1.....................................................68 38 Piezoresistors test structures A1) Piezoresistor 7, A2) Piezoresistor 8, A3) piezoresistor 9 and B) piezo resistor crosssection.............................................................69 39 Boron 20 keV implantedsili con and anneal flow chart....................................................70 310 Boron, 20 keV, 7x1014 cm2, 7tilt implant and anneal 1 (Dt1).........................................70 311 Boron, 20 keV, 7x1014 cm2, 7tilt implant and anneal 2 (Dt2).........................................71 312 Boron, 20 keV, 7x1014 cm2, 7tilt implant and anneal 3 (Dt3).........................................71 313 Boron 40 keV implantedsili con and anneal flow chart....................................................72 314 Boron, 40 keV, 7x1014 cm2, 0tilt implant and anneal 1 (Dt1).........................................72 315 Boron, 40 keV, 7x1014 cm2, 0tilt implant and anneal 2 (Dt2).........................................73 11 PAGE 12 316 Boron, 40 keV, 7x1014 cm2, 0tilt implant and anneal 3 (Dt3).........................................73 317 Boron, 40 keV, 7x1014 cm2, 0tilt implant and anneal 4 (Dt4).........................................74 318 Boron solid source diffusion in nsilicon and anneal flow chart.......................................74 319 Analytical calculation of boron solid sour ce diffusion in nsilicon and anneal 3 (Dt3)....75 320 Boron and Phosphorus solid source diffusions in nsilicon and anneal flow chart...........75 321 Capacitor layout A) plan view and B) crosssection.........................................................76 322 P/N diode layout A) plan view and B) crosssection.........................................................76 323 Plan view of a Van der Pauw structure..............................................................................77 324 Hall Effect structure A) plan view and B) crosssection...................................................77 41 Piezoresistor noise measurement A) setup and B) small circuit noise representation.......89 42 Diode noise measurement A) setup and B) small circ uit noise repr esentation..................90 43 CapacitanceVoltage measurement setup adapter from Sah..............................................90 51 Asimplant profiles of boron with B, 20 keV, 7x1014 cm2, 7o tilt of generation 2 process..............................................................................................................................113 52 Asimplant profiles of boron with B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 of generation 2 process.........................................................................................................114 53 SIMS profiles of wafers with B, 20 keV, 7e14 cm2, 7o tilt of generation 2 process.......114 54 SIMS profiles of wafers with B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 of generation 2 process.........................................................................................................115 55 SIMS profiles of solidsource diffused wa fers C1 and C2 of generation 2 process........115 56 Piezoresistor test structur e 9 of generation 2 process......................................................116 57 CV measurement of pMOSC2 of wafer 2E of generation 2 process..............................116 58 IV characteristics of Resistor 6, Diode 1 and Diode 2 of process 1A of generation 2 process..............................................................................................................................117 59 Logarithmic scale of the forward bi as Diode 1 of generation 2 process.........................117 510 Reverse bias current of the forward bias Diode 1 of generation 2 process......................118 12 PAGE 13 511 Sheet hall coefficientSH R for the B, 20 keV, 7x1014 cm2, 7o tilt implanted piezoresistors of generation 2 process.............................................................................118 512 Sheet hall coefficientSH R for the B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 implanted piezoresistors subjected to only inert annealing of generation 2 process.......119 513 Sheet hall coefficientSH R for the B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 implanted piezoresistors subjected to iner t annealing and oxidation of generation 2 process..............................................................................................................................119 514 Sheet hall coefficientSH R for the solid source diffused piezoresistors of generation 2 process..............................................................................................................................120 515 IV characteristic of resistor 6 of wafer 2A of generation 2 process...............................120 516 Noise voltage PSD of piezoresistor R6 of wafer 2A of generation 2 process.................121 517 Noise voltage average PSD of three piezo resistors R6 of wafer 2A of generation 2 process..............................................................................................................................121 518 Noise voltage PSDs average of three piezo resistors R6 of wafer 2A, 2E, and 1A of generation 2 process.........................................................................................................122 519 PSDs and their uncertainties of three different piezoresis tors of .process 2A (B, 20 keV, 7x1014 cm2, 7o tilt and 5 min dry, 5 min wet and 10 min dry at 900 C).................122 520 The fitted lines of the three PSDs of process 2A (B, 20 keV, 7x1014 cm2, 7o tilt and 5 min dry, 5 min wet and 10 min dry at 900 C)..................................................................123 521 Noise voltage average PSDs of three pi ezoresistors R6 of wafer 2B and 5A of generation 2 process.........................................................................................................123 522 Noise voltage average PSDs of three pi ezoresistors R6 of wafer 3E and 4A of generation 2 process.........................................................................................................124 523 IV characteristic of pi ezoresistor R9 of wafer C1 of generation 2 process....................124 524 IV characteristic of pi ezoresistor R9 of wafer C2 of generation 2 process....................125 525 Noise voltage average PSDs of three pi ezoresistors R9 of wafer C1 and C2 of generation 2 process.........................................................................................................125 526 Noise voltage PSDs of C1 and C2 with N of C2 used for C1 at 1Hz of generation 2 process..............................................................................................................................126 527 Resistor geometry before and after di ffusion, A) planview and B) crosssection..........126 13 PAGE 14 528 Shot noise of resistor 6 of process 1A of generation 2 of generation 2 process..............127 529 Top views of piezoresistors test struct ures 7 A1), 8 A2) and 9 A3) and a crosssection B) of generation 1 process...................................................................................128 530 Secondary ion mass spectroscopy (SIMS) obtained from Evans Analytical Group for the fabricated piezoresistor s of generation 1 process......................................................128 531 IV characteristic of piezoresis tor R1B1W of generation 1 process................................129 532 Noise voltage PSD of R1B1 W of generation 1 process..................................................129 533 IV characteristic of piezoresis tor R3A12E of generation 1 process...............................130 534 Noise voltage PSD of R3A 12E of generation 1 process..................................................130 535 IV characteristic of junction isolated piezoresistor test structure 1 (R1B1W) of generation 1 process.........................................................................................................131 536 Shot noise of piezoresistor test structure 1(R1B1W) of generation 1 process................131 537 Noise voltage PSD of piezoresistor test structure 1 (R1B1W) a nd piezoresistor test structure 12 (R3A12E) are biased re spectively at 1.49 Vdc and 1.48 Vdc of generation 1 process.........................................................................................................132 538 Noise measurement PSDs A) of piezoresistors123, and R RR at same voltage and B) of number of carriers of piezoresistors123, and R RR at same voltage of generation 1 process..............................................................................................................................133 61 Focus ion beam (FIB) on a piezoresistor test structure....................................................142 62 The XTEM of piezoresistor implanted with B, 20 keV, 7x1014 cm2 of generation 2 process, A) 2A, B) 2E, C) 1A..........................................................................................143 63 XTEM of piezoresistor generati on 2 implanted with B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 of generation 2 process, A) 2B, B) 3E, C) 4A), D) 5A..........................143 64 The XTEM of piezoresistor A) solid s ource diffusions of B, 25 min, 950 C, B) solid source diffusions of B, 25 min, 950 C and P, 5 min, 800 C of generation 2 process......144 65 Ten PTEM pictures for process 2A of generation 2 process, implanted with B, 20 keV, 7x1014 cm2 and annealed for 5 min dry, 5 min wet and 10 min dry at 900 C........144 66 PTEM of the 20 keV implanted test structures A) 2A, B) 2E, C) 1A.............................145 67 PTEM of the 40 keV implan ted test structures A) 2B B) 3E, C) 4A, D) 5A..................145 14 PAGE 15 68 Defects densities as a func tion of anneal time of the 20 keV implanted test structures of generation 2 process....................................................................................................146 69 Regression line of the defect densit y versus annealing time for the B 20 keV...............146 610 Defects densities as a func tion of anneal time of the 40 keV implanted test structures with only inert anneal of generation 2 process................................................................147 611 Defects densities as a func tion of anneal time of the 40 keV implanted test structures with inert anneal and oxidation of generation 2 process..................................................147 612 PTEM of processes 40 keV, 7x1014 cm2, through 0.1 m of SiO2., A) 3E (10 min in N2 and 5 min dry, 5 min wet and 10 min dry oxidation at 900 C) and B) 4A (30 min in N2 and 5 min dry, 5 min wet and 10 min dry oxidation at 900 C)...............................148 613 Surface terminated defects versus the annealing time of the 20 keV implanted test structures of generation 2 process....................................................................................148 614 Surface terminated defects versus the annealing time of the 40 keV implanted test structures with only inert anne al of generation 2 process................................................149 615 Surface terminated defects versus the annealing time of the 40 keV implanted test structures with inert anneal and oxidation of generation 2 process.................................149 616 Defects count versus loop size of the 20 keV implanted test structures of generation 2 process...........................................................................................................................150 617 Defects count versus loop size of the 40 ke V implanted test structures with only inert anneal of generation 2 process.........................................................................................150 618 Defects count versus loop size of the 40 keV implanted test structures with inert anneal and oxidation of generation 2 process..................................................................151 619 Measured and ideal high frequency CV of process 2E, implanted with B, 20 keV, 7x1014 cm2 and annealed for 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C, of generation 2 process..........................................................................151 620 Energy level versus the DIT of the 20 keV implanted test structures. of generation 2 process..............................................................................................................................152 621 Energy level versus the DIT of the 40 keV implanted test structures with only inert anneal of generation 2 process.........................................................................................152 622 Energy level versus the DIT of the 40 keV im planted test structures with inert anneal and oxidation of generation 2 process.............................................................................153 623 Energy level versus the DIT of the solid source diffused test structures of generation 2 process...........................................................................................................................153 15 PAGE 16 A1 Polar plots of longitudinal A) and transv erse B) piezoresistance coefficients for ptype (100) silicon............................................................................................................. 159 16 PAGE 17 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy INVESTIGATION OF PROCESS FABRICATION FOR LOWNOISE PTYPE DIFFUSED PIEZORESISTORS By Robert Dim December 2009 Chair: Toshikazu Nishida Major: Electrical and Computer Engineering The geometry and process dependence of 1 /f noise in ptype piezoresistors was systematically investigated in this work. Pt ype piezoresistors were fa bricated with 20 keV boron implants, 40keV boron implants with impl ant oxide, and solidsource diffusion and varying isochronal 900C inert anneals on teststruc tures of different surface area and volume. The devices were characterized electrically using IV, CV, a nd power spectral density noise measurements. The defects were visualized using crosssection (XTEM) and plane view TEM (PTEM). In addition, the influence of carrier number on piezoresistors 1 /f noise was investigated. For the first time, the measured 1 /f noise in piezoresistors is systematically compared to bulk defect densities measured w ith TEM and interface trap densities from HFCV after each annealing condition of the piezoresistors. For ptype piezoresistors implanted with 20 keV boron at 7x1014 cm3 dose and isochronally annealed at 900C for varying times in inert N2 followed by a short dry/wet/dry oxidation at th e same temperature, increasing inert anneals resulted in decreasing 1/f noise as well as bulk defect dens ities measured by PTEM. A decrease of the 1 /f noise and bulk defect dens ities with increased anneali ng times was also observed on ptype piezoresistors implanted with 40 keV boron at 7x1014 cm3 dose through 0.1 m of SiO2 with only inert anneal at 900 C. However, for the ptype piezoresistors implanted with 40 keV 17 PAGE 18 boron at 7x1014 cm3 dose through 0.1 m of SiO2 with inert anneal and additional dry/wet/dry oxidation, increased 1 /f noise was observed with increased in ert anneal time (10 min versus 30 min) at 900 C although the bulk trap density decreas ed. From TEM, it appeared that the PSDs of the piezoresistors implanted with 40 keV boron at 7x1014 cm3 dose through 0.1 m of SiO2 with inert anneal and oxidation tr ack the faulted loop areas. A phosphorous counterdoped solidsource diffused ptype piezoresi stor had less noise than the borononly solidsource diffused piezoresistor which is attributed to the boron centroid furt her from the Si/SiO2 interface. 18 PAGE 19 CHAPTER 1 INTRODUCTION The trend in integrated circ uit (IC) technology is to fabr icate small size devices while focusing simultaneously on improving their performan ce, their reliability, and their affordability. In the field of integrated ci rcuits technology, microelectromechanical systems (MEMS), also known as microsystems design, allo ws the fabrication of miniature systems such as sensors and actuators. These miniature system transducers used in field such as automotive, aeronautic, environmental, and medical are typically on the mi crometer scale. A few examples of miniature systems are piezoresistive pressure sensors, microphones, accelerometers, and cantilevers. Key specifications include sensitivity, linearity, freque ncy response, selectivity, and dynamic range. The latter specification refers to the range of input signal magnitudes that can be measured. It is not surprising that the fabrication process, ma terial properties, and geometric dimension have enormous effects on the MEMS performance, in particular the noise floor or minimum detectable signal. 1.1 Motivation Noise plays an important role in the performa nce of MEMS transducers since it determines the minimum signal that can be detected. For example, in the MEMS piezoresistive microphone, the minimum detectable signal (MDS) and the si gnaltonoise ratio (S/N) can be reduced by improving the transducer sensitivity, reducing the noise, or both. The reduction of the noise generated from piezoresistors configured in a Wheatstone bridge can be achieved by understanding the physical phenomena that lead to its occurrence. For example, anecdotally, two piezoresistive microphones with the same diaphr agm geometry but different piezoresistor structure and process flow exhibited significantly different nois e characteristics. The first microphone employed dielectrically isolated 1x1018 cm3 doped piezoresistor which underwent 19 PAGE 20 DRIE and high temperature anneal while the s econd piezoresistor used a junction isolated 1x1019 cm3 doped piezoresistor with less high temperature anneal. With multiple differences, it is difficult to pinpoint the geometry trends and the annealing factor that a ffect the device noise. 1.2 Objective and Outline The objective of this work is to systematica lly investigate the dependencies of noise in piezoresistors geometry, passiva tion, and fabrication process. Such an understanding can facilitate the design of lownoise piezoresistiv e transducers such as microphones. Thus, we investigate low frequency noise through varyi ng the process fabrication (implant energy, annealing condition, and oxide thic kness) and geometry (surface a nd volume) of piezoresistors. In order to relate the noise to the physical defects in the silicon, techniques such as Transmission Electron Microscopy (TEM) are used for defect density analysis. Noise measurements on piezoresistors are analyzed, and the results are us ed to provide guidelines for the fabrication of low noise piezoresistors. The contributions of this work are first a syst ematic correlation of the noise voltage PSD to the bulk defects and surface traps of the piezoresis tors and second the effect of the number of carriers on 1 /f noise. The systematic corre lation of the noise voltage PSD to the bulk defects and surface traps is done by measuring the defects of ion implanted or solid source diffused piezoresistors at various implant s and anneals conditions, measured the noise voltage PSD of the piezoresistors after each ann ealing condition and correlated th e defects to the measured 1 /f noise. The effect of the number of carriers on 1 /f noise is studied in piezoresi stors with identical process fabrication. However some piezore sistors have same resistance and different volume while other piezoresistors have different resi stance and different volumes. In addition to the ion implanted piezoresistors, two different conditions of solid source diffused piezoresistors are used to study the effect of number of ca rriers and surface traps on the 1 /f noise. 20 PAGE 21 The dissertation is organized as follow; in chapter 2, we discuss the background of piezoresistors, piezoresistive microphone, noise source, defects in semiconductors and process dependence of 1 /f noise. In Chapter 3, the piezoresistor design of the test struct ures is presented. The experimental method is described in Chap ter 4 and is followed by the fabrication and measurement results in Chapter 5 and the defect measurement and analysis in Chapter 6. The conclusion and future work are discussed in Chapter 7. 21 PAGE 22 CHAPTER 2 BACKGROUND This chapter discusses the background for the motivation of this res earch. We start by presenting the strain sensitive resistive element (piezoresistor) that is employed for the noise investigation. An example of a piezoresistive MEMS microphone which uses piezoresistors for sensing pressureinduced diaphragm strain is briefly described. The effect of the noise on the performance of such a device is shown th rough the minimum detectable signal. The mathematical and physical foundation of noise, th e various noise sources, and potential defects that cause noise are discussed. We finally pres ent summaries of previous studies of noise in semiconductor devices. 2.1 Test Vehicle: Piezoresistor A piezoresistor is typically a ptype resistor made most commonly today via ionimplantation, which is based on the bombardmen t of foreign impurity species (boron) into a piezoresistive semiconductor material such as cr ystalline silicon. The property of a material, such as silicon, for which the resistivity changes when submitted to stress is called piezoresistivity. Piezoresistors play a critic al role in the nonenergy conserving dissipative transduction of the strain signal from the mech anical domain to the electrical domain. This ability to change resistivity know n as the piezoresistive effect, gives rise to a much larger gauge factor in semiconductors (two orders of magnitude) than in metals. The relation between the resistivity and the applied stress is descri bed by the piezoresistanc e coefficients. The resistivity of a piezoresistor is expressed as follows; 1 cm qp (21) 22 PAGE 23 In the expression above, is the electronic charge, q is the carrier mobility, and is the carrier concentration. Additional information on piezoresistivity is given in Appendix A. p2.1.1 Computation of Piezoresistor Resist ance under NonDegenerate Approximation The resistance of the piezoresistor is calcu lated in two ways: 1) for a uniform carrier concentration and 2) for a nonuniform carrier co ncentration. In both computations, we assume nondegenerate semiconductors. A semiconductor is said to be nondegenera te if the Fermi level is in the band gap at a distance of greater than3away from the conduction and valence band edges. In this case, the impurity concentra tion is low and the FermiDirac distribution is approximated by the Boltzmans approximation as shown in Equation 22,38 kT 11FFEE EE kT kTfEee (22) where is the Fermi energy, is the Boltzmans constant, and Tis the temperature in Kelvin. Under this approximation, the el ectron and hole concentrations are given in Equation 23 and Equation 24.38 FEk CFEE kT CNNe (23) FVEE kT VPNe (24) CN and are respectively the e ffective densities of states in the conduction and valence bands. and are respectively th e conduction and valence band edges. VNCEVE 23 PAGE 24 2.1.1.1 Resistance computation with uniform ca rrier concentration under nondegenerate approximation The resistance of the piezoresistor is co mputed using Equation 25 shown below, jL R XW (25) where is the resistivity as shown in Equation 21, j X is the junction depth, L the piezoresistor length and W the piezoresistor width. This computation of the resistance is not very accurate because in reality the impuritie s are not uniformly distributed in the semiconductor after the implant and subsequent anneal and thermal oxi dation used to activate the impurities and grow the oxide layers. A better approximati on of the resistance is discussed next. 2.1.1.2 Resistance computation with nonuni form carrier concentration under nondegenerate approximation The sheet resistance of the piezoresistor fo r a nonuniform profile is computed using Equation 26,1 01 jS x BR qnxNnxdx (26) where is the impurity distribution, is background dopi ng concentration and nxBN nx is the mobility as a function of the impurity profile. Given an initial fixed or limited impurity dose th at is thermally driven in at temperature, T, a first approximation of the impurity profile is given by a Gaussian di stribution as shown in Equation 27,1 224,40 x x D tQ CxteCte Dt D t (27) 24 PAGE 25 D Tis the temperature dependent impurity diffusivity, t is the drivein time, D t is the thermal budget and Q is the dose. However, a nonideal profile resu lts after fabrication due to second order process effects. Therefore, it is necessa ry to experimentally measure the final impurity profile. Experimental techniques include s econdary ion mass spectroscopy (SIMS). The concentration of the dopants is obta ined by bombarding ions such as O+ and Cs+ into the sample at a constant rate. The collisions cause the atoms in the sample to be ejected, analyzed and counted. However, SIMS gives the atomic impurity concentration, which does not always represent the electrical ly active carrier concentration. Fo r example, when a semiconductor is heavily doped or is submitted to low temperatur e, not all impurities are ionized and one speaks of impurity deionization. At high doping concentration 183 110 cm, the Fermi level lies within below the conduction band or within 3above the valence band. Since the targeted doping concentr ation is greater the 1x1018 cm3, impurity deionization must be considered in the resistance design for piezoresistors. To account for the el ectrical active carrier concentration, techniques widely used in the indu stry are spreading resistance profiling and Hall Effect. 3 kT kTA more accurate computation of the resistance is obtained when we deviate from the assumption of a nondegenerate semiconductor to a degenerate one. A semiconductor is said to be a degenerate semiconductor when the carri er concentration is significantly large and the Fermi energy is less than 3 from the valence band. In order to compute the carrier concentrations, one must use the FermiDirac distribution, i.e. the Boltzmann approximation is no longer valid. The FermiDirac integral of order 0.1VPN kT 12 is given in Equation 28,38 25 PAGE 26 12 02d F 1 e (28) where CEEkT is the normalized electron kinetic energy and FCEEkT. Using FermiDirac distribution, the electron and hole concentrations are given by Equation 29 and Equation 210,38 12FFC CEE NN kT (29) 12FVF VEE PN kT (210) 2.2 MEMS Piezoresistive Microphone The detection of acoustic pre ssureinduced strain via a co rresponding resistance change is the basic transduction mechanism of MEMS pi ezoresistive microphones. The diaphragm of a MEMS piezoresistive microphone defl ects when pressure is applie d. This deflection produces a change in the resistance of the four piezoresistors located at the diaphragm edge where stress is maximum in a Wheatstone bridge co nfiguration as shown in Figure 22. The four piezoresistors in the Wheatstone bridge are positioned such that two piezoresistors sens e the stress parallel to the current flow and the other two piezoresistor s sense the stress perpendicular to the current flow. 2.2.1 MEMS piezoresistive Microphone Voltage Output When the four piezoresistors R1, R2, R3, and R4 are equal, the Wheatstone bridge is said to be balanced. Thus at zero pressure, the output voltage, Vout, is zero. When the pressure on the diaphragm is nonzero, the diaphr agm deflects and the resistances of the four piezoresistors change in equal magnitude. However, the resistance change of 1 R and3 R have opposite signs to 26 PAGE 27 that of 2 R and4 R as indicated in Figure 22 by arrows. If 1234 R RRRR and change with equal magnitude, R the resulting piezoresistive mi crophone output voltage is given by Equation 211, out biasR VV R (211) where R is the change in resistance, R is the normalized unstrained resistance, and Vbias is the bias voltage Appendix B provides additional information on MEMS piezoresistive microphone voltage output. 2.2.2 MEMS Piezoresistive Microphone Sensitivity The sensitivity of a MEMS piezoresistive microphone is given by the ratio of the output voltage to the input pressure. The normalized sensitivity, which is the sensitivity divided by the bias voltage, is shown in Equation 212, 111out out bias biasVV R S VpVpRp (212) where Vbias is the voltage applied to the microphone, outV is the differential output voltage, and R is the resistance modulati on of the piezoresistor. 2.2.3 MEMS Piezoresistive Microphone Minimum Detectable Signal The lower limit of the dynamic range of a MEMS piezoresistive microphone is the minimum detectable signal (MDS). The expressi on of the MDS, which is the ratio of the output referred noise voltage to the sensit ivity, is given in Equation 213, PSDdf Noise MDS SensitivitySensitivity (213) 27 PAGE 28 From Equation 213, we see that the MDS can be reduced by lowering the noise or increasing the transducer sensitivity. 2.3 Noise and Noise Power Spectral Density In general, a disturbance can be described as an unwanted internal or external signal (acoustic, electrical) of a system that contaminates the signal of interest. In the electrical domain, disturbances can originate from the e nvironment or from within the device itself via current or voltage fluctuations. To reduce any contamination of the desi red signal from external disturbances such as power lin e 60 Hz ac interference, technique s such as shielding and proper wiring may be used. However, shielding or proper wiring cannot reduce the intrinsic nondeterministic random fluctuations that origin ate from the device. This intrinsic random fluctuation in voltage or current or generally effort or flow is termed noise. Since noise is a random process, analyzing it in the time domain does not give useful information regarding its average magnitude Therefore, we employ the power spect ral density function which gives the magnitude of the random signal squared over a ra nge of frequencies for noise measurements. The power spectral density function as described by Bendat and Piersol2 is given in Equation 214, 2 0, limx x f f f G f (214) where 22 01 ,lim,,T x T f fxtf Tfdt is the mean square value of a sample time record between frequencies f and f f 28 PAGE 29 2.4 Noise Sources in Piezoresistor Noise in semiconductor piezoresistors can be affected by defect density, temperature, doping concentration, and bias voltage. A semiconduc tor is in equilibrium, and its properties remain constant independent of time when it is no t subjected to a bias vol tage or any external stimuli such as light or thermal gradient. Ho wever, when bias or stimuli are applied to a semiconductor, the device is in nonequilibrium thus its properties are no longer constant. MEMS sensors are subjected to different noise mechanisms depending on whether they are at equilibrium or at nonequilibrium. Semiconductors are solidstate materials w ith conductivities lyi ng between those of insulators and conductors (1x108 and 1x104 S/cm). Semiconductor materials are very attractive and widely used in electronic devices si nce their conductivity can change with doping concentration, temperature, and light. Next we c onsider different noise mechanisms in silicon semiconductorbased MEMS piezoresistive microphones. 2.4.1 Electrical Thermal Noise Electrical thermal noise, also known as Johnson no ise, describes voltage fluctuations at the terminal of a conductor or semiconductor at equili brium. These fluctuations are caused by the random vibrations of charge carriers in equilibrium with the lattice at temperature, T Work by Nyquist3and Johnson4 led to the expression of the thermal noise power spectral density given in Equation 215, 24 thBV SkRT H z (215) where kB is the Boltzmann constant, R is the resistance, and T is the temperature in Kelvin. From Equation 215, we notice that electrical thermal noise is independent of bias voltage but depends on temperature. Elec trical thermal noise is not aff ected by bias voltage since the 29 PAGE 30 agitation of the charge carriers by thermal lattice vibrations is pres ent regardless of bias voltage. However, it is temperature dependent since mo re agitation of the carri ers occurs when the temperature is increased. In addition, Johnson noise is frequency independent because lattice vibrations are random, thus not related to any single time constant. 2.4.2 Mechanical Thermal Noise Mechanical thermal noise is the mechanical analogue of electrical thermal noise.5 By the fluctuationdissipation theorem, any dissipative mechanism that re sults in mechanical damping must be balanced by a fluctuation force to main tain macroscopic energy balance, hence thermal equilibrium. The expression of the mechani cal thermal noise is given in Equation 216, 24 mthBmN SKRT H z (216) where m R is the equivalent mechanical resistan ce of the sensor. In a MEMS microphone mechanical damping can originate from the vent channel and the diaphragm. 2.4.3 Low Frequency Noise Low frequency noise is a fre quency dependent nonequilibri um noise. When an actual piezoresistor is subjected to an external stim ulus (voltage, light), an excess noise at low frequencies is observed above the thermal noise floor. Since it is i nversely proportional to frequency, it is also known as 1/f noise. The mechanism that generates 1 /f noise is still an active area of research. Two widely discussed mechanisms of 1 /f noise are the fluctuation in the mobility ( ) described by Hooge6 and the fluctuation in th e number of carriers ( n) developed by McWhorter. 7 30 PAGE 31 2.4.3.1 Hooges model Hooge6 originally conducted experiments on noise in homogeneous samples at low frequency and observed low frequency noise with an inverse frequency dependence. He suggested that this 1 /f noise at low freque ncy is a bulk phenomenon6 and is due to fluctuations in the mobility ( ).8, 9, 10 Hooge gave an empirical formula fo r the noise power spectral density of 1/f noise in his publications6 as shown in Equation 217, 2 2 VV V S Hz Nf (217) In Equation 217, known as the Hooge parameter, is an empirical material parameter varying from 1x106 to 1x103, V is the bias voltage, N is the number of carriers, and f is the frequency. Hooges equation indi cates a square bias voltage de pendence for the low frequency noise. Thus, this noise mechanism is only pres ent when a voltage is applied. In addition, Equation 217 shows that the no ise power spectral de nsity is inversely proportional to the number of carriers, N Thus, the low frequency noise depends on the doping concentration n and volume V as shown in Equation 218 through the dependence on N NnV (218) The accurate computation of the number of carri ers is important for an accurate estimated of or conversely, for the design of the 1 /f noise given In some works, the number of carriers used to compute the Hooge para meter is extracted assuming a homogeneous semiconductor. Thus, the current density and electric field has b een assumed to be the same in the bulk of the piezoresistor. However, for our diffused piezoresistor, computing the number of carriers using Equation 218, might lead to an ov erestimate of the numbe r of carriers. To 31 PAGE 32 illustrate the importance of the number of carriers, let us use the example of two piezoresistors N1 and 2 R R and with same resistance R but a different estimate of the number of carriers, with Using Equation 2.17, although th e resistors have the same Hooge parameter12 and NN2 1 > NN the predicted 1 /f noise PSD of resistor 1 R will be less than that of the resistor 2 R To better estimate the number of carriers in an inhomogeneous semiconductor, we use Hall Effect measurement to obtain the active dose, which is multiplied by the piezoresistor aera to obtain as shown in Equation 219. N AANNA (219) where A AN is the electrical ac tive dose expressed in 2cm and A is the area of the sample. 2.4.3.2 McWhorters model McWhorter7 conducted his experiments on germanium samples and concluded that 1 /f noise is a surface effect. At the semiconductor su rfaces and interfaces, physical defects give rise to electronic traps that capture a nd emit charge. He postulated that 1 /f noise is caused by fluctuations of the number of char ge carriers due to trapping and de trapping of charge carriers at these traps. The Lorentzian generationrecomb ination spectrum resulting from the trapping and detrapping of the charge carriers at trap levels is given by Equation 220,11 212t GR GR tSfA f (220) 32 PAGE 33 where AGR is proportional to the density of the trap levels, and t is the tunneling time constant. Figure 23 describes the energy band diagram w ith two trap levels and their associated Lorentzian spectra with a corner frequency at 31 2dBf Since electrons located in trap centers far from the conduction band require more energy for generationrecombination to occur, is larger for deep trap cente rs than shallow trap centers as illustrated in Figure 23. Su mming the noise power spectral dens ities for a continuum of trap levels, we observe a 1 /f noise shape up to the cut off freque ncy where the curve rolls off as 1 /f2. The 1 /f noise observed at low frequenc ies is caused by fluctuations in the number of carriers in the conduction and valence bands due to trapping and detrapping of carriers located at multiple trap levels. The Hooge and McWhorter 1/f noise models are illustrated via the predicted resistance fluctuations in a ptype resistor in Appendix C. Both Hooges and McWhorters 1 /f noise models are actively us ed or modified to analyze and interpret low frequency noise m easurements in electronic devices.12,13, 14 However, since Hooges model describes the low frequency noi se through parameters (voltage, number of carriers, and Hooge parameter) that are easily mani pulated it is very attractive for analysis. Designers can model low 1/f noise piezoresistor by adjusting or modifying these parameters. 2.4.4 Shot Noise Schottky15 investigated noise in vacuum tubes. In a semiconductor, when charge carriers cross a potential barrier independently and randomly, fluctuati ons occur in the average current, I These fluctuations give rise to shot noise whic h is a nonequilibrium noise. In particular, shot noise is observed in a P/N junction due to the fluctuations in the average current I induced by the 33 PAGE 34 random crossing of carriers over a po tential barrier. The shot noise power spectral density is given in Equation 221, 22 IA SqI H z (221) where q is the electron charge, and I is the current. Equation 221 shows that shot noise is di rectly proportional to the average current I hence it is only present under bias conditions, a nd is frequency independent. 2.5 Defects in Semiconductors Defects have been cited to be the major cau se of low frequency noise. As described earlier, there are two well known theories6, 7 for the presence of the nonequilibrium 1 /f noise. In this section, we present mechanis ms that create different defect s in the bulk of a semiconductor that has been subjected to preamorphization, ion implantation, and diffusion. We also discuss defects at the semiconductor surface (Si/SiO2 interface) that may give rise to low frequency noise. 2.5.1 Bulk Defects Ion implantation is widely used for the intr oduction of foreign species in a semiconductor material such as silicon. Some advantages of ion implantation are the capacity to control the dopant concentration, the use of relatively low temperature, and reduced lateral distribution of the dopant. However, ion implantation has also some disadvantages. One of the disadvantages is the introduction of point defects such as interstitials and vacancie s into the crystalline lattice. Annealing is used after ion impl antation to recrystallize the silicon substrate and promote the activation of the dopant. The type of defects fo rmed after annealing have been categorized by Jones et al.16 The first category is termed Category I Damage by Jones et al.16 In this case, 34 PAGE 35 the implantation damage does not create an am orphous layer, however; a certain dose must be reached to lead to defect formation. The formed defects, located in the vi cinity of the projected rangep R are rodlike {311} defects a nd dislocation loops. The s econd category of defects, referred as Category II Damage by Jones et al.16occurs when the silicon is amorphized during ion implantation. After low annealing temper ature, {311} defects and dislocation loops are formed and are located beyond the amorphous/cryst alline interface. These defects are known are endofrange defects. The third category of defects is called Category III Damage. 16 The creation of these defects, Hairpin dislocations and microtwins, is re lated to the imperfect regrowth of the amorphous layer. The fourth category of defects, Category IV Damage,16 refers to the defects generated when a buried amorphous layer is created. During annealing of Category IV Damage, extended defects such as dislocation loops, are formed where the two amorphous/crystalline interfaces meet. The fift h category of defects, Category V Damage,16 is observed after annealing when the dopant concentra tion is larger than it s solid solubility in silicon. The defects are disloc ation loops and precipitates an d are formed around the projected range. Figure 24, adapted form a publication of Jones et al.16 illustrates the Category I Damage, which is the type of damage that ma y be present in our piezo resistors since the boron implant energies, 5, 20 keV and 40 keV (through 0.1 m of SiO2), with respective doses of 6x1014, 7x1014, and 7x1014 cm2 are not likely to amorphize the silicon. 2.5.2 Interface Traps At the Si/SiO2 interface in a semiconductor device, in terface traps can be a major issue in the performance of the device. The 1 /f noise modeled by McWhorter7 is based on the trapping and detrapping of charge carrier s at the interface traps. Res earchers have used modified McWhothers models 14, 17 in their work. For instance, Hou et al.,18 have used Fu and Sah 35 PAGE 36 model17 in their oxide trapping noise simulations The density of traps at the Si/SiO2 interface can be measured using Termans19 method which employed a high CV frequency measurement of a capacitor. In Chapter 4 we discuss the e xperimental method to co mpute the interface trap density, itD 2.6 Process Dependence of 1 /f Noise Various hypotheses on the source of the 1 /f noise, their relation to the process fabrication (defects) and geometry have been provided by authors to describe th e limiting factors. Summaries process dependence of 1/f noise, defect formation and en ergy distribution of defects in semiconductors are provided. Researchers such as Bilger et al. 20, Vandamme and Ooterhoff21 Clevers22, Harley and Kenny23,12, Yu et al. 13, 24, Davenport et al.25, Mallon et al.26, E. Cocheteau et al.27, and B. Belier et al.28 have studied the process dependence of 1 /f noise by varying parameters such as impurity species (boron, B or boron fluoride, 2 B F ), preamorphization, ion implantation (energy, dose) with or without im plant oxide, annealing condition (furnace or RTA), surface passivation (thermal oxide, PECVD oxide, nitride), materials (crystal, amorphous and poly silicon), and device dimensions Their results indicate that low 1 /f noise and low Hooge parameters can be achieved through low implan t energy, long annealing conditions, good oxide quality, and large number of carriers. To illustrate the effect of impurity we examine the works of Cocheteau et al.27 and Belier et al.28 who both implanted their samples with2 B F instead of B However, Belier et al.28 performed Gepreamorphization prior to ion implantation. Results from Cocheteau et al.27 show higher noise than they expected, thus Cocheteau et al.27 suggested that an increase in annealing time to reduce 1 /f noise. As for Belier et al.28 their devices with preamorphization have less lowfrequency noise than those without preamorphization. Belier et 36 PAGE 37 al.28 recommended the lowering of preamorphization a nd implant energies to further reduce the 1/f noise. The defect evolutions and the defect types with their locations in implanted samples with or without amorphization have been studied by researchers such as Jones et al.16, Li and Jones29, Liu et al.30, and Girginoudi and Tsiarapas.31 In addition, as discussed in Section 2.5.1, Jones et al. 16 have categorized the types of defects and their locations after ion implantation and annealing and have described fact ors such as implant species, i on implantation (energy and dose) that lead to the defects formations and locations. The defect concentrations and energy levels in samples implanted with BF2, B or FB and inert annealed or oxi dized were investigated by authors such as Yarykin and Steinman32, Boussaid et al.33, Benzohra et al 34, Kaniewski et al.35 and Girginoudi and Tsiarapas.31 Boussaid et al.33 results show energy levels caused by the boron implantation and annealing and other energy levels associated with the preamorphization. In their work, Boussaid et al.33 show that the DLTS peaks of defects associated with Gepreamorphization increases as the Ge energy increases. In add ition, samples with fluorine have higher defect concentrations than those without fluorine. The reverse bias currents of the p+n diodes fabricated by and Girginoudi and Tsiarapas31 are large but decrease as the deep level density decreases due to lower preamorphization energies and higher annealing temperatures. Low frequency noise has also been us ed by researchers such as Michelutti et al.36 to investigate the effect of environment on pressure sensors. Their measurements show that temperature influences 1 /f noise in corroded and noncorroded samples. Other scientists such as Park and Hwang37 have shown methods to fabricated shallo w junction for MOSFET devices. Park and Hwang37 implanted B and BF2. After ion implantation both pr ofiles have approximately the same junction depth but after annealing the BF2 profiles have shallowe r junction depths than 37 PAGE 38 those of B All the results presented in this section are important since they present the process dependence of 1 /f noise, defect formation and energy dist ribution of defects in semiconductors. This dissertation addresses the process dependence of 1 /f noise not only with 1/f noise magnitude as a function of annealing times but also with a systematic correlation of the 1 /f noise to the defects densities obtained with TEM and HFCV after each anneali ng condition. The effect of the number of carriers on 1 /f noise is studied first in piezoresistors with same resistance and different volume and piezoresistors with different resistances and volumes that underwent the same ion implantation and annealing conditions. S econd, the number of carriers is studied on piezoresistors with two different solid source diffusion conditions, to limit the interaction of the carriers with the interface traps, but with same annealing conditions. This allows to see if the reduction of the 1 /f noise is due to the number of carrier s or the additional solid source diffusion. 2.7 Summary There is a need to correlate the noise present in the devices to fabrication process and to the physical defects characterized by surface analytical techniques such as TEM. Therefore, an investigation of the correlati on of noise and defects in impl anted, solid source diffused and annealed piezoresistors is performed. Now that the background of the research and the contribution of this work were discussed, the piezoresistor desi gn is presented next. 38 PAGE 39 A B Figure 21. Piezoresi stor A) plan view B) crosssection. Figure 22. Piezoresistors conf igured in Wheatstone bridge. 39 PAGE 40 EC E n g r ET1 ET2 I(t)=qneAn(t) A) LogPSD (V2/Hz)f3dBLog f (Hz) f3dB 1/f gr 1 gr 2 Thermal noise B) Figure 23. Trappingde trapping model for 1 /f noise. A) Energy band diagram of trapping and detrapping at two trap levels, B) Lorent zian spectrum of two trap levels in comparison with thermal noise. Category I Damage Density Distribution (keV/cm3) crystalline Figure 24. Category I da mage adapted from Jones et al. 40 PAGE 41 CHAPTER 3 PIEZORESISTOR DESIGN In this chapter, we present the theoretical de sign of piezoresistors a nd their realization via microfabrication that are used to study the process dependence of piezoresistor noise. We start by presenting the design of a piezoresistor assuming a nondegenerate semiconductor for both uniform and nonuniform impurity concentration profiles. Afterwards, we discuss the key resistor design parameters such as resistivity, resistance, and surfacetovolume ratio. We also consider nonidealities in the fa brication process that affect th e impurity profile. We finish by presenting the design of the piezoresistor test structures. 3.1 Introduction A ptype silicon piezoresistor is typically fabricated via ionimplantation of boron into crystalline silicon. The geometry of the pi ezoresistor is defined in Figure 31 where L and W are the length and widt h of the piezoresistor, is the contact width, andCWj X is the junction depth. In the depth direction, the spatial dependence of the boron concentration affects the conductivity and the resulting resistance measured be tween the two contacts. In the next section, the simplest (ideal) case of a uniform impurity profile is first consid ered. This simplifying assumption is then relaxed to derive more accurate resistance es timates for practical fabrication processes. 3.1.1 Piezoresistor Design with Uniform Doping Concentration The ideal case of a spatially uniform impurity profile in the depth direction is considered first as illustrated in Figure 32. Furthermore, the concentration is assumed to be low enough such that the carrier concen tration is nondegenerate, and the Boltzmann approximation for carrier statistics can be employed. For ptype silicon, this means a carrier concentration less than 1x1018 cm3.38 In this case, the resistance of a uni formly doped piezoresistor is given by 41 PAGE 42 jL R XW (31) This approximation is not accurate for implanted samples because the impurity concentration is peaked at the projected range of the impurities and decreases exponentially approximately as the square of the distance from the projected range in a Gaussian profile. Thermal anneal of the implanted impurity profile in an inert ambient furt her distributes the impurities into the silicon. This Gaussian approximation of the spatial doping nonuniformity after ion implant and inert diffusion is considered next. 3.1.2 Piezoresistor Design with Gaussian NonUniform Doping Concentration The impurity concentration introduced into si licon via ion implantation and subjected to annealing varies with depth and is approximated by a Gaussian pr ofile as shown in Figure 33. For a limitedsource diffusion in an inert ambient, the Gaussian distribution of impurities in the silicon is given by1 22,x D tQ Nxte Dt (32) For a limitedsource diffusion, is constant, and the surface c oncentration decreases as the dopants are diffused into the substrate. is the temperature dependent diffusion coefficient of the impurity, and t is the drivein time. The characteristic length,QD Dt is a function of the time at elevated temperature and re presents the thermal budget needed to obtain desired parameters such as the junction depth and surface concentrat ion. The resistance of a piezoresistor assuming a Gaussian distribution is computed using SL RR W (33) 42 PAGE 43 where S R is the sheet resistance of a di ffused layer which is given by1 01 jS x AA BAAR qNxNNxdx (34) where AANxis the impurity distribution, is the background doping concentration and is the mobility as function of the impurity profile. When a Gaussian distribution is used to predict the resistance of an implanted pi ezoresistor, there is still a mismatch between the theoretical and fabricated piezoresistor resistan ce. Possible causes of this mismatch include fabrication nonidealities that affect the atomic impurity concentration profile and the fundamental semiconductor physics of impurity deionization and degenerate FermiDirac statistics. BNAANx 3.1.3 Fabrication NonIdealities During piezoresistor fabrica tion, there are secondary eff ects that cause the impurity profile to deviate from the ideal Gaussian di stribution. These seconda ry fabrication effects include transient enhanced diffusion (TED) and oxidation enhanced diffusion (OED), two mechanisms that both may result in a deeper junction depth. In a ddition, the impurity atoms redistribute during oxidati on resulting in a pile up (phosphor us) or depletion (boron) at the Si/SiO2 interface. 3.1.3.1 Transient enhanced diffusion (TED) Ideally, the impurity diffusion coefficient is only a function of temperature; however, in practice, it is affected by the con centration of neutral and charged defects. The deepening of the junction depth during annealing du e to high diffusivity of the dopant caused by implant damage is termed transient enhanced diffusion (TED). The final junction depth is affected by the 43 PAGE 44 annealing temperature used to activate the dopan t in the semiconductor when implant damage is present. The choice of the diffusion te mperature is critical for TED. Deal et al. ,1 discuss the effect of time and temperature on TED. Deal et al. ,1 use a figure from Crowder39 that shows the effect of temperature on TED. In that figure from Crowder39 there is more diffusion for the lower temperature. 3.1.3.2 Oxidation enhanced diffusion (OED) During oxidation, there is injecti on of extra interstitials into the bulk of the silicon which may cause an increase of the dopant diffusion rate resulting in a deeper junction depth. This phenomenon is termed oxidation enhanced diffusi on (OED) and is observed during the oxidation of boron implanted silicon.1 3.1.3.3 Impurity segregation When two different materials are in contact, dopant present in one ma terial segregate into the materials until equilibrium is reached.1 Dopant segregation may cause a depletion or a pileup of the dopant near the materials interface. For example, during thermal oxide growth, boron preferentially segregates into the oxide causi ng a depletion of the boron concentration in the silicon near the Si/SiO2 interface. Thus, during oxidation or annealing in an oxidizing ambient, the predicted surface concentration may decr ease due to boron segregation into the SiO2 leading to a reduction of the total boron dose in the silicon. The segregation of boron in SiO2 were studied by Fair and Tsai.40 Figure 34 shows boron profiles assu ming ideal (Gaussian) and the nonideal boron distribution that may result fr om TED, OED, and impur ity segregation. In Figure 34, the nonideal profile has a smaller su rface concentration than the ideal Gaussian profile but also has a deeper junction depth. 44 PAGE 45 3.1.4 Fundamental Physics That Affect Electrical Activation of Impurities Another parameter to consider in the piezoresistor design is the electrically active concentration of impurities which can differ from the atomic concentration. This difference is due to the fundamental physics of impurity de ionization and degenera te carrier statistics discussed in Chapter 2. In both cases, the concen tration of the neutral donor and acceptor are estimated by taking into account the o ccupation factor of the donor impurities D f and acceptor impurities A f given in Equation 3.5 and 36.38 1 1 1DFD EE kT Df e g (35) 1 1 1FAA EE kT Af e g (36) where D g and A g are the donor and acceptor site degeneracy factor, is the Fermi level, FE D E is the donor level, and A E the acceptor level. The charge neutrality equation which allows the computation of the electron and hole concentrat ion at thermal equilibrium is given in Equation 37,38 0DDDAAAqPNNNNN (37) where and are the hole and electron concentrations,PN D DN and A AN are the donor and acceptor impurity concentrations, and D N and A N are the concentrations of electrons and holes trapped respectively at the donor and acceptor sites. Thus, the quantities D DDNN and A AANN represent the concentrati on of ionized donors and the concentration of ionized 45 PAGE 46 acceptors respectively. Since we take into account impurity deionization, D N and A N are not assumed to be zero but rather are computed using the donor and acceptor occupation factors and the respective impurity concentrations from38 D DDDNfN (38) and A AAANfN (39) Using 1 D DDDDDDDDDDDNNNNfNNf, the concentration of ionized donors is given by 1 1FDDDD EE kT DNN ge (310) and the concentration of i onized acceptors is given by 1 1AFAAA EE kT ANN ge (311) The electrical active carrie r concentration is obtained by solving the general charge neutrality condition, Equation 37 to gether with the mass action laws, 12 12 FCVF CV E EE NPNNF F kT kT E 46 PAGE 47 3.2 Piezoresistor Design Parameters Four key parameters are considered in the pi ezoresistor design. These parameters are the piezoresistor impurity profile, resi stance, surface area, and volume. Associated with the impurity profile are the doping process details such as im plant energy, annealing time and ambient. The overall purpose for the variation of these four parameters is to study the process and geometry dependencies of 1 /f noise in piezoresistors. The impurity profile is used to compute the number of carriers which in turn is used in the computation of the Hooge parameterN From Equation 217, we see that as increases, the 1 /f noise decreases for a specific value of N In addition, the 1 /f noise may originate from the bulk or th e surface of the piezoresistor. Thus, by varying the surface area and the vol ume of the piezoresistor, we change the surface to volume ratio to investigate whether the car riers are more affected by the de fects in the bulk or the surface traps when the piezoresistor is in nonequilibrium. 3.2.1 Piezoresistor Impurity Profile For fixed implant and annealing conditions the junction depth and surface concentration are unchanged for piezoresistors with different dimensions in the same wafer. Then the sheet resistanceS R the ratio of the resistivity to the junction depth, will be the same for all piezoresistors. Therefore, to design piezoresistors with different resistances, one may manipulate the piezoresistor width and length. 3.2.2 Piezoresistor Resistance Piezoresistors with four differe nt resistances have been desi gned. Since the junction depth and doping profile are the same for all the piezoresistors, the four different resistances have been obtained by varying the number of squares, which is the ratio of the length to the width of the 47 PAGE 48 piezoresistor LW. Figure 35, adapted from Jaeger41 shows two piezoresistors with the same sheet resistance, but different number of squares LWand hence resistance. 3.2.3 Piezoresistor Surface Area Piezoresistors with different surface area bu t same resistance are obtained by changing while maintaining the same number of squares,LW LW. Figure 36, adapted from Jaeger,41 shows two piezoresistors with the same resistance, R same number of squares, LW, but different surface area. 3.2.4 Piezoresistor Volume The piezoresistor volume is approximately equal to the product of the total surface area and the junction depth. It will vary as the surface area or the junction depth of the piezoresistors is changed. Thus, piezoresistors with the same resistance and different volume are also obtained. If the junction depth,j X is the same, then the ratio of the su rface area to volume is constant and equal to 1j X In the next section, the photomask design is outlined. 3.3 Test Structures Design The piezoresistor photomask de sign varies the four parameters described earlier. The process flow is summarized in Appendix D. A total of four photomasks have been designed in AutoCAD for the fabrication of th e test structures. The first mask is the implant mask, the second is the contact mask, the th ird is the metal mask, and the fourth is the bond pad mask. Two generations of test structures generation 1 and generation 2, have been fabricated. The difference between the two generations is in th e order that the implan t and oxide growth are performed and also the removal of an oxide layer before implant. In addition to the piezoresistors, we have designed additional test structures which are the ptype capacitor, P/N junction diode, Van der Pauw stru ctures and Hall Effect structures. The wafers used for the 48 PAGE 49 fabrication of test structures generation 1 and generation 2 are described respectively in Table 31 and Table 33 and the process flows of test st ructures generation 1 and generation 2 are shown in Table 32 and Table 34. The difference between the wafers of generation 1 and 2 is the resistivity. 3.4 Boron Profile Simulations The boron profile simulations are used to pred ict the surface concentration and junction depth after fabrication. However, many secondary effects may occur during the fabrication; thus the simulations serve only as an estimate and not as a final profile. Th e exact boron profile is obtained through measurements such as SIMS as described above. We use analytical calculations, FLOOPS (Florida Object Oriented Process Simulator)42 Fermi model and FLOOPS Pair model to estimate the boron profiles. 3.4.1 Analytical Calculation The analytical calculation is the least accurate among all the simulations since it does not include oxidation enhanced diffusion (OED), tran sient enhanced diffusion (TED), nor leakage of boron into the oxide (boron segregation). The eq uation used for test st ructures that are boron implanted and those that are boron solid source diffused are discussed next. 3.4.2 Limited Source Diffusion: Ion Implantation In ion implantation, charged impurities are bom barded into the silicon substrate. The higher the energy used to accelerate the particles the deeper they pe netrate into the substrate after colliding with the substrate atoms causing damage. The distribution of the atoms in the silicon bulk has a Gaussian profile expressed as follows1 2 22P PxR R pCxCe (312) 49 PAGE 50 where 2p P Q C R is the surface concentration, Q is the dose, and P R is the projected range which is the average distance that the impurity ions travel into the substrate before stopping. The peak concentration occurs at the projected range. P R is the standard deviation also called vertical or normal straggle. 3.4.3 Annealing after Ion implantation After ion implantation, the wafer is heated at an elevated temperature for a designated time for several reasons. During this process called an nealing, the substrate is recrystallized, the impurities are electrically activated and the defects are removed. In the meantime, the impurities diffuse further into the substrate, and the surf ace concentration decrease s under inert annealing. There are conditions when the impurity concentr ation decreases or increases further at the surface of the substrate. This is the case duri ng an annealing in an oxidizing ambient. During oxidation, impurities such as boron segregate into the oxide while other species such as phosphorus pile up at the silicon side of the Si/SiO2 interface. This effect is not taking into account in the analytical calcula tion as shown in Equation 3131 ,2 222 222P PxR RDt PQ Cxt e RDt (313) where 0A BE kTDDe 1is the diffusion coefficient of the impurity in the substrate. The intrinsic diffusivity, and activation energy, ,of boron in silicon are respectively 0DAEsec21 cm and .1 The quantity. 35 eV D t, the product of the diffusion coefficient, and the annealing time, t is called the thermal budget. The quantityD D t is an indicator of the time and temperature needed to achieve a junction depth or surface concentration. 50 PAGE 51 3.4.4 Solid Source Diffusion During solid source diffusion, the surface concentrat ion of the impurity is kept constant. The value of the surface concentration is solid so lubility limited. There is no damage during the introduction of the impurity into the substrate; however the dose of the impurity is not well controlled. The distribution of the impurity in the si licon is approximated by a complementary error function (erfc) as shown in Equation 314 ,1 (,) 2S predepx CxtCerfc Dt (314) where 2S predepQ C Dtis the surface concentration. Often the impurities are driven deeper into the s ubstrate after predeposition. The distribution of the impurity after drivein is expressed by ,240drivein driveinx DtCxtCe (315) Since 0driveinQ C Dt and 2predep SDt QC we can rewrite Equation 315 as follows ,242predep drivein drivein driveinx Dt SDt C Cxt e Dt (316) 3.4.5 Florida Object Oriented Process Simulator (FLOOPS) FLOOPS42 is a twodimensional process simulator. To estimate the profile of a dopant after ion implantati on and annealing, FLOOPS so lves the differentials diffusion equations of the 51 PAGE 52 impurity atoms and the point defects differentials equations. The initial distribution of the point defects, vacancies and interstitials, is determined by the implantation process. Two FLOOPS diffusion models, Fermi model and pair model, ar e used to approximate the boron profiles of our processes prior to fabrication. 3.4.5.1 Simplest FLOOPS (Fermi model) The FLOOPS Fermi model is the simplest FL OOPS simulation. In the Fermi model, diffusion is described as a con centrationdependent diffusivity.59 It is more sophisticated than the analytical calculation shown above. 3.4.5.2 More accurate FLOOPS (Pair model) In this model, the diffusion of the dopant o ccurs via dopantintersti tial or dopantvacancy pairs.59 FLOOPS Pair model includes TED, impur ity segregation and OED which shows a drastic deepening of the profile when oxidation enhanced diffusion (OED) is modeled. It is more sophisticated that the an alytical calculation and the FLOOPS Fermi model. 3.5 Ptype Piezoresistor Implant and Annealing Condition The details of the implant and annealing condition for the ptype piezoresistors is discussed in the context of the resistan ce, surface area, and volume. 3.5.1 Piezoresistor Generation 1 (PG1) The junction isolated piezoresistors are designed to have various lengths and widths to obtain different surface areas. The purpose of va rying the surfacetovolume ratio is to find out whether the low frequency noise is more strongly dependent on the surface area based on McWhorters theory7 or the volumedistributed bulk defects based on Hooges theory.6 As stated earlier if the junction depth, j X is constant, then the ratio of the surface area to volume is constant and equal to 1j X This is the case for the piezoresistor design. The implant and 52 PAGE 53 anneal conditions of test stru ctures generation 1 are shown in Table 35. Figure 37 shows the simulated boron profile for piezoresistor gene ration 1. The FLOOPS model and analytical calculation show the same Rp However after annealing, the j unction depth of the FLOOPS pair model is deeper than those of the FLOOPS Fermi model and analytical calculation. The simulated junction depths are around 2.8 m, 1. 8 m and 1.7 m for the FLOOPS pair model, FLOOPS Fermi model and analytical calculation resp ectively. The surface concentrations of all simulated profiles are in the range of 6x1018 cm3. There are four groups of piezoresistors with each group having the same resistance value but different surface area and volume. The fi rst group is composed of piezoresistor test structures 1, 2 and 3 with resistance, 1 R The second group has piezoresi stor test structures 4, 5 and 6 with resistance, 2 R The third group has piezoresistor test structures 7, 8 and 9 with resistance, 3 R and the fourth group contains piezoresistor test structures 10, 11 and 12 with resistance, 4 R respectively. Figure 38 shows designed piezoresistors test structures 7, 8, and 9 and their crosssection. Piezore sistor 7 has a dogbone shape while piezoresistors 8 and 9 have serpentine shapes. The serpentine shape is used to minimize the area occupied by the piezoresistor. The piezoresistor surface area, volume and carrier number are used for the noise analysis as discussed earlier. The carrier num ber and resistance depend on the actual depth profile of the impurity c oncentration as well as on the funda mental carrier statistics and the carrier mobility. The dimensions, surface area and volume of the piezoresistors assuming uniform doping concentration are shown in Table 36, which shows groups of piezoresistors with the same LW but different surface and volume. Thus each set of piezoresistors with same resistance have carrier numbers that differ, which will affect the piezoresistors noise performance since Hooges expression of the 1 /f noise given in Equati on 217 shows that the 53 PAGE 54 noise voltage PSD is inversely propor tional to the number of carriers, Thus piezoresistors with larger should have lower 1 /f noise. Other parameters that could be used to analyze the noise voltage PSD of the piezoresistors are surfac e area and volume. The surface to volume ratio is constant since all the piezoresistors have been designed to have the sam e junction depth. In devices with the same junction dept h, most of the carriers in the piezoresistor are located at the same average distance away from the N N 2SiSiO interface. 3.5.2 Piezoresistor Generation 2 (PG2) The piezoresistors in generation 2 are fabric ated such that there is a systematic investigation of 1) th e correlation between 1 /f noise and defects and 2) the effect of Si/SiO2 interface traps on 1 /f noise. The piezoresistor have been doped with boron in three ways. The first method is by ionimplantati on through oxide into th e silicon substrate, the second is by ionimplantation directly into the silic on substrate, and the third is via solid source diffusion. After, the boron ion implantation and predeposition, the piezoresistors are then annealed in multiple ways. This different anneals allow investigation of defect evolution in the piezoresistors which are monitored with TEM and correlated to the 1 /f noise. Varying the j unction depth will allow different distances between the carriers centroid with respect to the SiO2 interface. The latter will help in verifying the eff ect of the surface traps on the 1/ f noise. There are two ways for which we can vary the anneal conditions. The first option is by fixing the te mperature and varying the annealing time and the second is by fixing the time and varying the temperature. Isothermal annealing was selected to investigate the time evoluti on of the defects. During the annealing, one should ramp up the furnace temperat ure to the proper temperature. If there are two different annealing temperatures, one for the inert annealing and one for the oxidation, two temperature ramps are required which is not time efficient and increase the thermal budget. Thus 54 PAGE 55 since all the piezoresistors will have a thin dry/ wet/ dry SiO2 passivation layer (200 ) thermally grown at 900 C for 5 min/ 5 min/ 10 min, the c hoice would be to have th e temperature fixed at 900 C for the inert anneal and vary the time to change the thermal budget, Dt where is the boron diffusivity with unit of D sec2cm and t is the annealing time. Thermally grown oxide at 900 C for 5 min/ 5 min/ 10 min is no netheless an annealing. The ques tion is if this step in itself does not remove all the defects. Our approach to this question is to en sure that the amount of defect is large enough so that a thermally grown oxide at 900 C fo r 5 min/ 5 min/ 10 min will not completely remove the defects. This can be done by high energy implant and/or large dose. Hence, for the implant directly into the sili con, we choose boron at 20keV with a dose of 7x1014 cm2 and for the implant through SiO2 we choose boron at 40keV with a dose of 7x1014 cm2. One may say that the boron dose of the 40 keV s hould be increased so that we would have the same concentration of boron in th e silicon as for the case of the 20 keV implant. The same dose was selected for a more straight forward analysis of the results. For the wafer with solidsource boron predeposition we have two conditions. In the first conditi on, boron is predeposited for 25 min at 950 C and in the second condition boron is also predeposited for 25 min at 950 C but it is followed by a phosphorus predeposition for 5 min at 800 C. The phosphorus predeposition is used to push the boron peak concentration away from the Si/SiO2 interface. This technique should allow us to investigat e the effect of the Si/SiO2 interface traps on the 1/ f noise magnitude since no bulk defect should be in troduced with so lid source diffusion. 3.5.2.1 Boron implanted piezoresis tors at 20 keV with a dose 7x1014 cm2 The flow chart of the piezoresistors impl anted with boron at 20 keV with a dose of 7x1014 cm2 at 7 degree tilt is shown in Figure 39. The boron profiles obtained with the analytical calculation and FLOOPS pair model for the implan t and all the anneal co nditions are shown in 55 PAGE 56 Figure 310, Figure 311, and Figure 312. In all figures, the asimp lant and postanneal profiles obtained with FLOOPS pair model have deeper junctions than thos e of the analytical solution. We also notice after annealing a decrease in th e peak concentration of the FLOOPS pair model while no significant change is observed for the an alytical calculation. These differences in the profiles are due to the fact that the FLOOPS pair model take into account secondary effects such as TED, OED, and impurity segreg ation as discussed in Section 3. 4.5.2. However, both models predict the same implant projected range, Rp around 0.1 m. The pr edicted junction depths after annealing are in the ranges of 0.25 m and 0.75 m for the analytical calculation and FLOOPS pair model respectively from the wafer surface. 3.5.2.2 Boron implanted piezoresis tors at 40 keV with a dose 7x1014 cm2 through SiO2 The flow chart of the piezoresistors im planted with boron at 40 keV with a dose 7x1014 cm2 at 0 degree tilt through SiO2 is shown in Figure 313. The boron profiles obtained with the analytical calculation and FLOOP S pair model for the implant a nd all the anneal conditions are shown in Figure 314, Figure 315, Figure 316, and Figure 17. Here also, as in the case of the 20 keV implant, all figures for the asimplant and postanneal profiles obtained with FLOOPS pair model have deeper junctions than those of th e analytical solutions. A decrease in the peak concentration is noticed for the FLOOPS pair model while no significant change is observed for the analytical calculation in Figure 314, Figure 315, Figure 316, and Fi gure 17. The predicted junction depths after annealing are in the ranges of 0.35 m and 0.75 m for the analytical calculation and FLOOPS pair model except for the piezoresistor with only inert anneal which has a junction depth of 0.47 m. The junction depths are measured from the wafer surface. 3.5.2.3 Boron solid source diffused pi ezoresistors for 25 min at 950 C The flow chart of the piezoresistors with boron solid source diffusion for 25 min at 950 C 56 PAGE 57 is shown in Figure 318. The boron profile obtained with the predeposition analytical calculation and the anneal condition is shown in Figure 319. The diffe rence between junction depths for the predeposition and post annealing profiles are small. The junction depths are around 0.13 m and 0.17 m for the predeposi tion and post annealing profiles respectively while the surface concentrati ons are in the range of 2x1020 cm3 and 9x1019 cm3 for the predeposition and post annealing profiles. 3.5.2.4 Boron solid source diffused piezores istors for 25 min at 950 C followed by phosphorus solid source di ffusion for 5 min at 800 C The flow chart of the piezoresistors with boron predeposition for 25 min at 950 C followed by phosphorus predeposition for 5 min at 800 C is shown in Figure 320. Next we will discuss the other test structures such as the Ptype capacitors, the P/N diode, the Van der Pauw and the Hall Effect structures. 3.6 Additional Test Structures In addition the piezoresistors, we fabricate additional test structures such as ptype capacitors, P/N diodes, Van der Pauw structures, a nd Hall effect structures. We use the ptype capacitor is to measure the oxide thickness and co mputed the interface trap densities. The P/N diode is used to measure the junction leakage cu rrent and the shot noise The sheet resistance and contact resistance are measured using the Va n de Pauw structure wh ile the electrical active carriers are measured using th e Hall Effect structure. 3.6.1 Ptype Capacitor Equipments such as Nanospec and Ellipsometer are commonly used to measure oxide thicknesses optically. The capacitancevoltage, CV, characteristic of a pt ype capacitor can also be used not only for oxide thickness measurement but also for the computation of interface trap density. Figure 321 shows the plan view and crosssection of a pt ype capacitor. The 57 PAGE 58 theoretical value of the capacitance of the pcapacitor is obtained using Equation 317 at the accumulation condition, ox oxCA t (317) where ox is the product of the permittivity of free space 0 (8.854x1012 F/m) and the dielectric constant (3.9 at 300 K) of the insulator (SiO2), is the oxide thickness, and 0koxt A is the area of the metal on top of the insulator. 3.6.2 P/N Diode P/N diodes are used to measure the junction leakage current and the associated shot noise. A top view and crosssection of a P/N diode are shown in Fi gure 322. The ideal current equation of a P/N diode is given by 01A BqV kT DIIe (318) where is the bias voltage, is the Boltzmann constant, Tis the temperature in Kelvin, and AVBk0 I is the saturation current as expressed by 22 0 Nii P NAPD D nn D IqA LNLN (319) where is the electronic charge, q A is the crosssectional area, and ND P D are respectively the electron and hole diffusion coefficients sec2cmand and NL P L are respectively the electron and hole minority carrier diffusion lengths, and is the intrinsic carrier concentration. in 58 PAGE 59 3.6.3 Van der Pauw Structure Van der Pauw structures are used to measure the sheet resistance, line width, and contact resistance. The top view of th e Van der Pauw structure layout is shown in Figure 323. From Figure 323, the sheet resistance is calculated from voltages and currents measured at contact pads A, B, C and D using 1 2ln2ABAD s CDBCVV R II (320) Equation 321 and Equation 322 are us ed to compute the line width, W, and contact resistance, C R m SR WLW R (321) FG C GEV R I (322) where D E m CFV R I L is given by the center to center spaci ng between D and E, and W is the width of the bar. In the next section, we present test structures used fo r extracting the carrier concentration. 3.6.4 Carrier Concentration Test Structures Several methods exist to compute the carrier concentration in se miconductor devices. Methods that are used to measure or estimate th e carrier concentration in semiconductor devices include spreading resistance, SI MS, capacitancevoltage profiling, and Hall Effect. Each method has advantages and disadvantages. 59 PAGE 60 3.6.4.1 Spreading resistance technique In the spreading resistance technique, the surf ace of the semiconductor is cut at an angle rendering the measurement destructive. Twopoint metal probes are used to measure the resistivities of th e layers along the depth of the bevele d area while successively comparing it against standards.1 A disadvantage of the spreading resistan ce is the tedious sample preparation and measurement analysis. 3.6.4.2 Secondary ion mass spectroscopy (SIMS) technique Secondary ion mass spectroscopy (SIMS) prov ides the dopant concentration of both uniform and nonuniform doped samples. It is also a destructive method. In this method, ion beams such as O+ and Cs+ are focused on the sample silicon substrate. These ions collide with the impurity in the substrate cau sing them to be ejected. The resulting secondary ions are analyzed and counted. In this method, one disadvan tage is that the profile consists of the foreign atom concentration. In some applications such as ours, where the sample is heavily doped, impurity deionization occurs, thus the atomic concentration does not represent the electrically active carrier concentration in which we are inte rested. Thus, SIMS may overestimate the carrier concentration which will lead to an inaccurate number of carri ers and thus an error in the estimate of the Hooge parameter However, SIMS can be useful in determining the junction depth and the profile of atoms residing in each layer such as boron in oxide due to boron segregation during oxidation. This information can be used to approximate the boron dose before and after thermal oxidation into the silicon. 3.6.4.3 Capacitancevoltage technique In the capacitancevoltage technique, de vices that exhibit a voltage dependence capacitance such as Schottky diode, P/N junction, and MOS capacitor (MOSC) are used. The doping profile can be obtained from the DC volta ge dependent space charge layer thickness in a 60 PAGE 61 MOSC since the free carriers concentration resp ond to the small signal applied at the gate. Therefore, since the free carrier concentration depends on the dopa nt profile, the profile of the impurity can be obtained over the ra nge of depletion thicknesses. The ionized impurity profile is given by43 22 1s GNx d q dVC (323) where x is the depth,0ssK is the dielectric permittivity of silicon, is the DC gate bias, and is the smallsignal depletion capacitance. So me advantages of CV profiling using a MOSC over a Schottky diode and a P/N junc tion is that the CV of a MOSC can scan distances close to the semiconductor/oxide interface. In addition, higher doping densities can be measured with MOSC CV than with Schottky diode or P/N diode which are junction breakdown voltage limited. GVC3.6.4.4 Hall measurement technique The Hall effect is a nondestr uctive measurement t echnique that can determine whether a material is p or ntype, the carrier concentrati on, and the mobility. This makes Hall effect a powerful technique. The top view of the Hall effect structure layout is shown in Figure 324. In the Hall effect measurement, a magnetic field, Bz, is applied perpendicularly to the sample, while a current, AC I is passed from contact A to contact C and a hall voltage D BV is measured between contacts D and B as shown in Figure 324. The expre ssion of the hall voltage is given by AC DBZ I VB qtp (324), 61 PAGE 62 where q is the electronic charge, t is the sample thickness, and p is the carrier density. The Hall H R coefficient is obtained using D B H Z ACtV R B I (325), and the carrier concentration p is obtained from 1 H p qR (326), Generally, in Hall effect measurement, the samp le is assumed to have a uniform doping profile. However, this is not always the case. Theref ore, for non uniformly doped samples, to obtain an accurate number of carriers for the computati on of the Hooge parameter, we measure the electrically active dose, from th e measured Hall sheet coefficient, and multiply it by the sample area. 3.7 Summary We have discussed the piezoresi stor test structur es designs of generation 1 process and generation 2 process for the st udy of the effect of the numbe r of carriers and the process dependence on 1 /f noise respectively. The de sign of additional test st ructures, such as ptype capacitors and Van der Pauw structures were disc ussed. Their purpose is to extract parameter such as oxide thickness, sheet resistance and doping concentration used in the study of the effect of the number of carriers on the 1 /f noise and in the analysis of the correlation of 1/f noise to defects. 62 PAGE 63 Table 31. Wafer characteristics used to fabricate test stru ctures generation 1. Diameter Type Orientation Resistivity Thickness 4 inch N (100) 2.05.0 cm 500550 m Table 32. Process steps for piezoresistor test structur es generation 1. Process Step 1. RCA wafer clean (nSi, 100 mm diameter., CZ (100), 25 cm, 500550 m thick) 2. Thick isolation oxide growth 3. Lithography for implant mask 4. Oxide etch 5. Photoresist strip 6. Ion implantation 7. RCA wafer clean 8. N2 anneal + dry/ wet/dry oxidation 9. Lithography for contact hole 10. Oxide etch 11. Photoresist strip 12. Front side metallization (Al, 1% Si) 13. Lithography for metal bond pad 14. Metal etch 15. Back side metallization (Al, 1% Si) 16. Photoresist strip 17. Nitride passivation depos ition step and patterning 18. Post metallization anneal (Forming gas 96%N2, 4% H2) 19. Wafer dice 20. Chip die attach and wirebond Table 33. Wafer characteristics used to fabricate test stru ctures generation 2. Diameter Type Orientation Resistivity Thickness 4 inch N (100) 0.51.0 cm 500550 m 63 PAGE 64 Table 34. Process steps for piezoresistor test structur es generation 2. Process Step 1. RCA of wafers (nSi, 4 in, CZ <100>, 0.51 cm, 525 25 m) single side polished. (UF) 2. Grow thick isolation mask dr y/wet/dry SiO2 (70/23/70 min at 1100 C) and spin resist. (UF) 3. Lithography for a) channel implant or b) channel solidsou rce predep (UF) 4. Etch dry/wet/dry oxide where channel a) impl ant or b) solidsource predep is to be performed. (UF) 5. Photoresist strip. (UF) 6. RCA clean (UF) 7. Growth thin dry/wet/dry SiO2 and lithography for channel implant with mask 2 (dark field). 8. Ion implantation 9. Photoresist strip and RCA wa fer organic clean (SC1) 10. Inert anneal in N2 and dry/wet/dry SiO2 of wafers 11. Lithography for contact holes with mask 3 (dark field). This a pplies to wafers with and without thin oxide implant masks. 12. Etch oxide for contact holes 13. Photoresist strip and front side meta llization on top waferpolished surface 14. Lithography for metal with mask 4 (clear field), metal etch a nd photo resist strip 15. Nitride passivation depo sition (PECVD) on top of waferpolished surface 16. Lithography for contact pads with mask 5 (dark field), nitride etch and back side metallization on bottom of waferunpolished surface 17. Post metallization anneal (forming gas 96% N2, 4% H2) 18. Wafer dicing 19. Packaging Table 35. Implant and a nnealing conditions of test structures generation 1. Species Energy (keV) Dose (cm3) Tilt (degree) Inert anneal in N2 Dry/Wet/Dry oxide Boron 5 6x1014 7 300 min, 1050 C 65/21/65 min, 950 C 64 PAGE 65 Table 36. Dimensions, surface area, and vol ume of piezoresistors assuming uniform doping profile. Piezoresistor L ( m) W ( m) (L/W) Surface ( m2) Volume ( m3) 1 70 13.9 5.04 973.00 2208.71 2 105 20.85 5.04 2189.25 4969.60 3 122.5 24.33 5.04 2980.43 6765.56 4 140 13.90 10.07 1946.00 4417.42 5 210 20.85 10.07 4378.50 9939.20 6 245 24.33 10.07 5960.85 13531.13 7 700 13.90 50.36 9730.00 22087.10 8 1050 20.85 50.36 21892.50 49695.98 9 1225 24.33 50.36 29804.25 67655.65 10 1400 13.90 100.72 19460.00 44174.20 11 2100 20.85 100.72 43785.00 99391.95 12 2450 24.33 100.72 59608.50 135311.30 A B Figure 31. Piezoresi stor A) top view a nd B) crosssection. 65 PAGE 66 Figure 32. Uniform doping concentration. Concentration (cm3) Figure 33. Nonuniform doping c oncentration (Gaussian Profile). 66 PAGE 67 Figure 34. Illustration of boron profiles when secondary effect such segregation (A) oxidation enhance diffusion (B), transient enhanced diffusion (C) are present during processing and comparison of a Gaussian profile with and a nonideal bor on distribution (D). Figure 35. Piezoresist ors with same sheet resistance, but different number of squares and resistance adapted from Jaeger. 67 PAGE 68 Figure 36. Piezoresistors with same resistance, different su rface area and same number of square adapted from Jaeger. Figure 37. Simulated boron profile for piezoresistor generation 1. 68 PAGE 69 A1 A2 A3 B Figure 38. Piezoresist ors test structures A1) Piezoresistor 7, A2) Piezoresistor 8, A3) piezoresistor 9 and B) piezo resistor crosssection. 69 PAGE 70 Figure 39. Boron 20 ke V implantedsilicon and anneal flow chart. Figure 310. Boron, 20 keV, 7x1014 cm2, 7tilt implant and anneal 1 (Dt1). 70 PAGE 71 Figure 311. Boron, 20 keV, 7x1014 cm2, 7tilt implant and anneal 2 (Dt2). Figure 312. Boron, 20 keV, 7x1014 cm2, 7tilt implant and anneal 3 (Dt3). 71 PAGE 72 Figure 313. Boron 40 keV implantedsilicon and anneal flow chart. Figure 314. Boron, 40 keV, 7x1014 cm2, 0tilt implant and anneal 1 (Dt1). 72 PAGE 73 Figure 315. Boron, 40 keV, 7x1014 cm2, 0tilt implant and anneal 2 (Dt2). Figure 316. Boron, 40 keV, 7x1014 cm2, 0tilt implant and anneal 3 (Dt3). 73 PAGE 74 Figure 317. Boron, 40 keV, 7x1014 cm2, 0tilt implant and anneal 4 (Dt4). Figure 318. Boron solid source diffusion in nsilicon and anneal flow chart. 74 PAGE 75 Figure 319. Analytical calcu lation of boron solid source diffu sion in nsilicon and anneal 3 (Dt3). Figure 320. Boron and Phosphorus solid source diffusions in nsi licon and anneal flow chart. 75 PAGE 76 A B Figure 321. Capacitor layout A) pl an view and B) crosssection. A B Figure 322. P/N diode layout A) plan view and B) crosssection. 76 PAGE 77 Figure 323. Plan view of a Van der Pauw structure. Figure 324. Hall Effect structure A) plan view and B) crosssection. 77 PAGE 78 CHAPTER 4 EXPERIMENTAL METHOD In this chapter, we elaborate on the experiment s that are conducted using the test structures designed in Chapter 3. We discuss the equi pments, measurement setup, and measurement analysis for each experiment to be conducted. We start with the experimental method for the characterization of the piezoresistors, which is followed by that of the ptype capacitor and the P/N diode. The goal of these experiments is to st udy the effect of the nu mber of carriers on the 1 /f noise using the piezoresistors test structures of generation 1, the process dependence of 1 /f noise and correlate the low freque ncy noise to defects using test structures of generation 2. 4.1 Piezoresistor Experimental Methods In this section, we discuss two important measurements to be conducted on piezoresistors which are the IV and the noise measurements. 4.1.1 Piezoresistor IV Measurement The IV characteristics are measured to obt ain the piezoresistor resistances and their linearity range. This linear ra nge is useful since it allows us to know the range of voltages to apply to the piezoresistor s during the noise measurements. The piezoresistor resistance is also useful since it allows us to compute the theoretica l thermal noise that will be compared with the measured value. Thus, this gives us confidence in the measurement. Th e IV characteristic of the piezoresistor is obtained with the Agilent Semiconductor Parameter Analyzer 4155C and a probe station We place probes on the piezoresistor co ntacts and then sweep voltages across the piezoresistor while simultaneously recording the corresponding currents. Afterwards, we plot the current versus the voltage and use the slope of the curve to obtain the resistance value. Since the piezoresistors are junction isolated, during the IV measurement, a voltage is applied to the ntype substrate to reverse bias the P/N junction and thus potentially avoid leakage current. Once 78 PAGE 79 we know the piezoresistor linear range and re sistance, we then proceed to the noise measurement. 4.1.2 Piezoresistor Noise Measurements There are three phases for the piezoresistor noise measurement. The first one is the noise setup, the second is the equipment settings, and the third is noise extraction. The noise measurement is used to measure the excess noi se of the piezoresistor and the P/N diode. 4.1.2.1 Noise measurement setup The equipment used for the noise measurement are three nested Faraday cages, a lownoise preamplifier (SRS 560), a dynamic signal analyzer (SRS 785), lead acid batteries, metal film resistors, double shielded coaxial cables (RG223/U), BNC connect ors, and LabView to automate the measurements. The noise measurement setup uses DC bias voltages. The combination of lead acid battery, short cable, triple shielded Faraday cage and single point ground help to reduce potent ial extrinsic in terference signals such as radio signals (AM, FM) at high frequencies and power line interference at 60 Hz and their harmonics. Figure 41 A) and B) shows the piezoresistor noise measurement set up and the small signal noise representation for the extraction of the noise of the device under test (DUT). In Figure 41, the current noise PSD associated with the bias resistorand the DUT biasR D UTR are respectively and biasiRS D UTiRS. and are the input referred current and voltage noise PSD of the low noise amplifier. Th ey are obtained respectively via open and short circuit noise measurements of the lownoise preamplifier. iAmpSvAmpSi R and G represent respectively the noise free input impedance and ga in of the preamplifier, and is the raw measured voltage noise PSD. After proper shielding, another important c onsideration for the noise measurement is the equipment settings which are discussed next. vO utS 79 PAGE 80 4.1.2.2 Equipment setting for noise PSD measurement As mentioned earlier, we use a lownoise pr eamplifier (SRS 560), a spectrum analyzer (SRS 785), and a computer with LabView to coll ect the data. Table 41 shows the lownoise amplifier settings. The amplifier input A is set to ac coupling because we are interested in the timevarying signal. The gain is set to 1000 to ensure that the output signal of the preamplifier is higher than the noise floor of the spectrum anal yzer allowing accurate noise measurement. The output of the lownoise amplifier is fed to the input A of the spectrum analyzer. Table 42 shows the spectrum analyzer settings. The coupling is set to ac since we are interested in small signal fluctuations. A Hanning window is selected for the measurement of the random signal because it provides good selectivity and reduces power spectral density leakage. A list of spans, FFT lines, and bin widths is given in Ta ble 42. The overall power sp ectral density is obtained by overlapping the measurements of the different spans. At low frequencies, the binwidth is smaller to ensure better frequency resolution and th erefore good accuracy of th e measurements. All these different equipment settings are set in LabView which automates the measurements. In addition to the proper shielding, equipment sett ings, and measurement automation, one needs to correctly extract the DUT noise PSD from the raw measured noise PSD In the next section, we show how to extract the DUT noise. 4.1.2.3 Noise power spectral density extraction The piezoresistor noise voltage PSD is extracted by noise ci rcuit analysis of the noise equivalent circuit shown in Figur e 41 B). The raw output noise voltage PSD expression is given in Equation 41. 2 2 2 2//// //bias DUTi vOut vAmp iRiAmpiRbiasDUTi ibiasDUTR SGS SSSRRR RRR (41) 80 PAGE 81 In Equation 41, the opencircuit noise PSD of the SRS 560, is negligible compared to the other noise sources. Also note thatiAmpSibi as R Rand iDU T R R, thus and //////biasDUTibiasDUTRRRRR 2 2//i ibiasDUTR RRR is reduced to one since //ibiasDUTiRRRR Therefore, 2 2//bias DUTvOut vAmpiRiRbiasDUTSGSSSRR Solving for D UTiRS, we obtain 2 2 2Hz //DUT biasvOut vAmp iR iR biasDUTS S G SS RR A (42) The noise voltage D UTvRSis obtained by multiplying D UTiRSby D UT R squared as shown below, 22 VHzDUT DUTvRiRDUTSSR (43) The bias resistor is a metal film resistor which has very little 1 /f noise, thus it does not contribute to the measured excess noise. However, since it st ill contributes thermal noise, to minimize the effect of the bias resistor th ermal noise on the measurement, we select abiasRbias R with a resistance much larger than that of the resistance of the device under test, D UT R so that the parallel combination of the two resistances equals that of the D UT R Finally, the bias voltage across D UT R is varied by fixing the large impedance, bias R and changing the battery voltage batteryV. In addition to the piezoresistor exce ss noise, we measure the P/N diode shot noise. In the next section, we will disc uss the P/N diode experimental method. 81 PAGE 82 4.2 P/N Diode Experimental Method There are two important measurements to be c onducted with the P/N diode. The first is the DC currentvoltage char acteristic, and the second is the shot noise. 4.2.1 P/N Diode DC CurrentVoltage The P/N diode currentvoltage measurement is a useful monitor of the reverse bias voltage prior to voltage breakdown and also of th e turn on voltage. For wafers with a uniform background concentration of 1x1016 cm3 and an abrupt junction, the theoretical breakdown voltage is around 60 V,38 which is sufficiently large enough for our application. However, the actual breakdown voltage needs to be verified. The setup for the IV measurement of the piezoresistor applies also for the P/N diode IV ch aracteristics. However, for the P/N diode, one probe makes contact with the pt ype region and the other with th e ntype substrate. The P/N diode shot noise is discussed ne xt. Although we have P/N diode te st structures, we measure the shot noise directly on the piezore sistor substrate isol ation junction for which we have measured the noise voltage PSD as desc ribed in Section 4.1.2.3. 4.2.2 P/N Diode Shot Noise Measurement The origin of the shot noise ha s been discussed in Chapter 2, Section 2.4.4. It has also been shown to be proportiona l to the DC current passi ng through the P/N diode. 4.2.2.1 P/N diode noise measurement setup Although we use the same shielding method for the shot noise measurement and equipment settings, the resistor bi asing network for the P/N diode shot noise is different than that of the piezoresistor. Figure 42 shows the noise measurement setup for the P/N diode noise measurement. In Figure 42, and are the noise current sources associated respectively with the bias resistors 1 biasiRS2 biasiRS3 biasiRS1bias R and 2biasR3bias R The noise associated with the diode 82 PAGE 83 resistance D R is The diode resistance iDS D R is equal to TDCnVI where is the ideality factor and is the thermal voltage nTV kTq. As in Figure 41, and are the input referred current and voltage noise of the low noise amplifier with input impedance iAmpSvAmpSi R and raw measured noise The bias resistor 1 vOutS 1biasRand the bias resistor 2 2biasR serve as the voltage divider step down of the 12 V lead acid battery bias voltage. 3bias R is used in a voltage divider of the already st epped down voltage. The vo ltage across the P/N diode D V is measured and the corresponding current D I passing through the diode D is obtained by use of the P/N diode IV curve. 4.2.2.2 Shot noise power sp ectral density extraction Figure 42 B) is used for the noise analysis. The extracted P/N diode shot noise current PSD is given by 2 2 2A Hz //Db i a svOut vAmp iR iRiAmp biasDS S G SS S RR (44) In Equation 44, bias R is and is the current thermal noise of 123//biasbiasbiasRRR biasiRSbias R 4.3 PType Capacitor Experimental Method The high frequency CV measurement (HFCV) of the ptype metaloxidesemiconductor capacitor (pMOSC) is used to measure the oxide thickness and also to estimate the density of interface traps (DIT) at the Si/SiO2 interface using the Termans method.19 The impedance analyzer 4294A is used for th e CV measurement. Figure 43 shows the setup for a CV measurement adapted from Sah.38 Not shown in Figure 43 is the ac signal in addition to the DC bias. During the CV measurement, an oscillating frequency f is applied 83 PAGE 84 through the surper imposed ac signal while the DC voltage is swept from negative to positive voltages. From the measured capacitance, the oxide thickness is computed using Equation 317 in accumulation, which for a pMOSC is at the maximum applied negative gate voltage where the majority holes accumulate at the silicon surface. The accumulation and inversion capacitances respectively, and are extracted from the HFCV and used to compute the semiconductor capacitance oxCinvC s C from 21 F cms invoxC AA CC (45) Next, the carrier concentration, is obtained by solving AAN 1 2 02sAA s SKqN C (46) where S is the surface potential expressed by 2lnAA S iN kT qn (47) In Equations 45, 46 and 47, is the electronic charge, q s K is the semiconductor dielectric constant, 0 is the permittivity of free space, k is the Boltzmann constant, Tis the temperature in Kelvin, and A is the crosssectiona l area of the MOSC. The extracted carrier concentration, and oxide thickness are then used to compute and plot the ideal high frequency CV of the pMOSC on the same figur e as the measured high frequency CV. For each capacitance value, the corresponding measured and ideal gate voltages, are recorded and AANGV 84 PAGE 85 a difference between the two is computed. The interface trap density, DIT, is then computed from the measured distortion betw een the ideal and actual HFCV curves in terms of a surface potential, idealGGGVVVS dependent GV using 21 2 oxG it SCdV Dc m qd e V (48) Next we discuss the transmission electr on microscopy (TEM), a technique used to visualize and count the def ects in the silicon. 4.4 Transmission Electron Microscopy Transmission electron microscopy (TEM) allows the visualiza tion of the defects in the bulk of the piezoresistors. In this technique, the image is form ed by electrons that pass through thinned samples, via ion milling, and hit a photographic plate. One can use crosssection TEM (XTEM) and planview TEM (PTEM) to visualize a nd analyze the defects in the sample. XTEM allows sides view of the defects thus its depth into the sample while the PTEM allows a top view of the defects therefore can be used to comput e the defect densities. PTEM is made out of samples that have about 3 mm diameter. The samples are polished using polishing jigs and aluminum power. After the sample is thinne d, it is mounted face dow n on a Teflon holder which has a hole at its center. A wax is used on the edge of the sample to secure it on the holder. A hole at the center of the sample it made by etching it from the back side with HF:HNO3 (25%:75%) solution. The edges of the sample th at are cover with wax are not etched. After etching the hole the samples are released from the holder by a pplying acetone to the wax. Region around the hole are thin en ough and are electron tr ansparent. It is in these electron transparent regions that PTEM pictures are taken. For XTEM a thin elec tron transparent section of the sample in obtained via focus ion beam (FIB). Since we have oxide on the surface of our 85 PAGE 86 samples which is not conductive, we carbon coat the samples prior to inserting them in the chamber of the Dual Beam SEMFocused Ion Be am (FEI Strata DB235) system. After, the section is cut with the FIB station and placed on a sample holder, it is inserted in JEOL TEM 200CX instrument to obtain crosssection images. Next we discu ss the Van der Pauw structure. 4.5 Van Der Pauw Structure The Van der Pauw structure is very useful si nce it allows the computation of the sheet resistance,S R of a doped semiconductor which is relate d to the surface concentration. In addition to the sheet resistance, the Van der Pauw structure allo ws the measurement of the line width, and the contact resistance,W C R of the structures. The detailed equations are summarized in Chapter 3. 4.5.1 Sheet Resistance The Agilent Semiconductor Parameter An alyzer 4155C and a probe station are used to measure the sheet resistanceS R We place probes on the four contacts A B C and D of the Van der Pauw structure, and we inject a current through two contacts while we record the corresponding voltage across the tw o other of contacts. The sheet resistance is computed using Equation 320 and can be used to compute the resi stance of a piezoresistor for a given number of squares LW. 4.5.2 Line Width For the line width measurement, we also use the Agilent Semiconductor Parameter Analyzer 4155C and a probe station. This m easurement gives insight on any lithography error that occurs during fabrication. The line width is measured us ing Equation 321 in Chapter 3, Section 3.7.5. W 86 PAGE 87 4.5.3 Contact Resistance The contact resistance, C R is measured with the same equipment used to measure the sheet resistance and the line width. Knowing C R is relevant since it allows us to verify its effect on the measurement of the piezoresistor resistance. The contact resistance C R is measured using Equation 322. The test structure used to comput e the electrical active carrier c oncentration is discussed next. 4.6 Hall Effect Measurement The Hall Effect measurement is used to compute the active dose, which is used for the computation of the number of carriers, An accurate number of carriers is necessary for a correct extraction of the Hooge parameter (Equation 217). The test structure used for the Hall Effect measurement was shown in Chapter 3, Fi gure 324. In the extraction of the carrier concentration, a uniform doping pr ofile is assumed. Schroder44 discusses two methods to measure the carrier concentra tion of non uniformly doped samples. The first method is to successively chemically etch layers of the samp le while conducting a Hall Effect measurement of each etched sample. The second method is to produce a junction at the surface of the sample to make the layer inactive using a P/N junction, a Schottky barrier, or a MOS capacitor. Another approach is to measure the Hall sheet coefficien t to extract the active impurity dose and compute the number of carriers by multiplying the active dose by the tota l surface area of the piezoresistor. QN4.7 Summary We have presented the experimental methods for the measurement of sheet and contact resistance, line width, low fr equency noise, surface and bulk defects, junction leakage current, and carrier concentration. These results of th ese measurements are used to correlate the 1 /f noise 87 PAGE 88 to the defects, relate the low frequency noise to the number of carrier s and compute the Hooge parameter. The experiments will help monitor the 1 /f noise of the piezoresistor with increasing annealing time. In the next chapter, the fabrication and measurement results are discussed. 88 PAGE 89 Table 41. Lownoise pr eamplifier SRS 560 setting. Coupling Input Bandwidth Gain Input Output AC A 0.03 Hz 300 KHz 1000 100 M 25 pF 50 Table 42. Spectrum an alyzer SRS 785 setting. Parameters Settings Coupling AC AC AC AC Input A A A A Window Hanning Hanni ng Hanning Hanning Span (Hz) 12.5 200 1600 12800 FFT Lines 800 800 800 800 Binwidth (Hz) 0.016 0.25 2 16 A biasiRSbias R DUT R D UTiRSiAmpSvAmpSi R GvOutSB Figure 41. Piezoresi stor noise measurement A) setup and B) small circuit noise representation. 89 PAGE 90 1 bias R 2 biasR3 bias R D i R GbatteryVA 1 bias R 2 biasR3 biasRi R D R G1 biasiRS 2 biasiRS 3 biasiRS iDS iAmpS vAmpS vOutSB Figure 42. Diode noise measurement A) setup and B) small circuit noise representation. Al, 1% Si SiO2Ptype VDCC Figure 43. CapacitanceVoltage m easurement setup adapter from Sah. 90 PAGE 91 CHAPTER 5 FABRICATION AND MEASUREMENT RESULTS In Chapter 3, we presented the design of the test structures and in Chapter 4 the experimental methods. In this Chapter, we show the fabricated test structures and the measurement results. We start with the fabrication results of the test structures and follow with the measurements results which include the IV ch aracteristics for the piezoresistors and diodes, the sheet resistance, the ptype capacitor, and the noise voltage PSD of the piezoresistors and the diodes. We use these measurements to compare the theoretical design results to the fabricated test structures and to monitor the effect of ann ealing time and the effect of the number of carriers on the 1 /f noise. 5.1 Implantation, SolidSource, and Annealing of Test Structures The test structures were fa bricated at Coresystems, Georgia Institute of Technology, MEMSexchange and at the UF na nofabrication clean room. The pr ocess flows are detailed in Appendix D. The ion implantation of the piezo resistors was done at Coresystems. Test structures using generation 1 processes were annealed at MEMSexchange while those of generation 2 processes were annealed at Georgia Institute of Technology. The geometry of the fabricated test structures of generation 2 is the same as those of generation 1 with exceptions in the diode and capacitor dimensions. The process va riables of ion implantation, annealing, oxide and nitride thickness were varied in generation 2. We presen t the fabrication results and measurements of all the tests structures of ge neration 2 since a combination of the results is needed to monitor the process dependence on 1 /f noise and to correlate the low frequency noise to defect densities. We present the results of piezoresistors gene ration 1 to study the effect of the number of carriers on the 1 /f noise. 91 PAGE 92 5.2 Characterization of Fa bricated Test Structures Prior to the study of the process dependence of 1 /f noise, we electrical ly characterize the fabricated generation 2 process te st structures such as piezor esistors, ptype capacitors, P/N diodes, Van der Pauw and Hall Effect structures for two reasons; fi rst, it is used to compare the measurements to the theoretically predicted resu lts. Second, the charact erization of the test structures help to extract parameters such as oxide thickness and Hall shee t coefficient, compute the interface trap density and num ber of carriers. It also pr ovides the linear range of the piezoresistor with the IV charact erization of the piezoresistor a nd the junction leakage current of the piezoresistor. 5.2.1 Piezoresistor Test Structures A comparison of the theoretical design to the fabricated piezoresistors is presented in terms of resistances, profiles, and oxide thicknesse s. The IV characteristics are used to obtain the resistances of the fabricated junction isolat ed piezoresistors of each fabrication process. Table 51 shows the measured resistances of piez oresistors 6 and 9 when the piezoresistor is biased from 10 V to 10 V. In that voltage range the IV curve is linear. Therefore, the piezoresistors can be biased up to 10 V during the noise measurement. Process 2A, which correspond to a boron implant at 20 keV with a dose of 7x1014 cm2 at 7o tilt follow by a thermal oxidation of 5 min dry, 5 min we t and 10 min dry at 900 C, has a theoretical resistance of 1559.6 for piezoresistor 6. However, the fabri cated piezoresistor 6 has a resistance around 2200 The theoretical resistance was computed usi ng the profile obtained from the FLOOPS pair model. The FLOOPS pair model profiles are compared to the SIMS profiles. Regarding SIMS accuracy, the SIMS data has a 10 % uncertain ty according to the company that did the measurements. The estimate of the atomic dopant number is affected by the inaccuracy of the 92 PAGE 93 SIMS measurement. Note that the true atomic nu mber will be larger than the true carrier number since not all dopants are el ectrically active and io nized. Instances where this does not hold must be due to inaccuracies in the measurements. Th e profile using the FLOOPS pair model predicted a junction depth of 0.72 m and a surface concentration 2x1019 cm3 at the Si/SiO2 for all the B 20 keV implant processes. From SIMS proce ss 2A, which corresponds to a boron implant at 20 keV with a dose of 7x1014 cm2 at 7o tilt followed by a thermal oxida tion of 5 min dry, 5 min wet and 10 min dry at 900 C, has a junction depth of 0.54 m and a surface concentration of 1.42 x1019 cm3. All the theoretical junction depths obta ined from FLOOPS pair model have deeper junction depths than those of the SIMS profiles except for proc ess 2B which correspond to boron implanted at 40 keV through 0.1 m of SiO2 with a dose of 7x1014 cm2 and annealed for 10 min at 900 C in N2. The asimplant SIMS boron profiles for the 20 keV and 40 keV are shown in Figure 51, and Figure 52. The respective peak concentrations for the 20 keV and 40 keV from SIMS measurements are 0.08 m and 0.15 m. Th e post annealed profiles obtained with SIMS for the 20 keV, 40 keV and solid source diffusions are shown in Figure 53, Figure 54 and Figure 55. The junction depth and surface concentration of each SIMS profile is listed in Table 52. The junction depths and surface concentrati ons are about the same. The noise floor of the SIMS is about 1x1017 cm3 while the background concentrat ion of the wafers is about 1x1016 cm3. The oxide thickness through which the 40 keV boron is implanted shown in Figure 54 is 0.089 m. The theoretical profiles for th e solid source diffused piezoresistor were obtained using the analytical calculation. The results show shallower junction depths and higher surface concentrations of the theoretical profiles than those of the measured SIMS. Also, the SIMS profiles show that the surface concentration of the phosphorous in the piezoresistors with 93 PAGE 94 phosphorous counterdoped solidsource diffusion is higher than the phosphorous surface concentration in the phosphorous without phosp horous counterdoped so lidsource diffusion. The piezoresistors with phosphorous counterdoped solidsource di ffusion have deeper junction depths. Next we discuss the fa bricated pMOSC generation 2. 5.2.2 Ptype Capacitor Test Structure The ptype capacitors are used to measure th e oxide thickness and the interface trap density (DIT). Two capacitors of different dimensions we re designed. Table 53 shows the dimensions of the two capacitors, pMOSC1 and pMOSC2. In Table 54, we show the oxide thickness measured with Ellipsometer and pMOSC capac itancevoltage (CV) m easurements for the implanted and solid source diffused resistors. Th e measured oxide values with the Ellipsometer and the pMOSC CV are within the range of the theoretical computed values which were 0.02 m for the 20 keV and solid source diffused stru ctures and 0.1 m for the 40 keV implants. Figure 57 shows the CV profile of pMOSC2 of wafer 2E. In Figure 57, the DC voltage is varied from 2 V to 6.5 V, from accumulati on to inversion. The accumulation voltage was limited to 2 V to avoid damaging the capacitor. The depletion region of the CV lies between these two voltages and that is needed to measure the density of interface traps (DIT) using Termans method.19 The theoretical value using an estimated oxide thickness 200 MOSC is 846 pF. Using the measured oxide thickness with the Ellipsometer (252.12 ), the estimated capacitance is 671 pF. From the CV measurem ent shown in Figure 57 at accumulation the measured capacitance is 560 pF and using Equati on 317 we compute an oxide thickness of 302 The uncertainty in the oxide thicknesses is estimated to be 5%. This number is based on the inaccuracies of the CV in the accumulation regi on. The latter electrical oxide thickness obtained from CV is used since the Ellipsomete r measurements were done prior to completion 94 PAGE 95 of the device while the CV is measured on the fi nished device. We discuss next the fabricated P/N test structure. 5.2.3 P/N Diode Test Structure The P/N diodes of generation 2 process have tw o sizes. Table 55 shows the dimensions of the two P/N diodes. The IV characteristics of resistor 6, diode 1 and diode 2 are shown in Figure 58. Using logarithmic s cale, the reverse bias and forwar d bias currents of diode 1 are shown in Figure 59 and Figure 510. The magnitude of the reverse bias current at 1 Vdc, 3 Vdc and 10 Vdc are respectively 3.15x109, 3.87x108, and 1.94 x107 A as shown in Figure 510 for the current at 1 Vdc. 5.2.4 Van der Pauw Test Structure The Van der Pauw structure is used to compute the sheet resistanceS R the line width W and the contact resistance C R as presented in Chapter 4. Table 56 shows the measuredS R W and C R for each of the processes. The sheet resi stance varies between 61.22 for wafer C2 to 224.87 for wafer 2A as shown on Table 56. The measuredS R agree with the measured resistances for the implanted piezoresistors. For a given piezoresistor, say R6, the solid source diffused piezoresistors show lowe r resistance than the implanted cases. This can be observed from the measured S R Referring to Equation 51, the resistance R is linearly proportional toS R SL RR W (51) where L and W are the length and width of the pi ezoresistor. So, for a given ratio LWas S R varies, the resistance, R also changes. The line width,W are about 2 m for all the processes except for the solid sour ce diffused resistors where it is 4.88 m and 2.95 m for C1 95 PAGE 96 and C2 respectively. The contact resistance C R is larger for the implanted piezoresistors and smaller for the solid source diffused ones C1 and C2. Contact resistance,C R is a function of doping concentration. As the doping concentrati on increases, the specif ic contact resistance,c decreases. The contact resistan ce can be obtained from the sp ecific contact resistance using Equation 52. c CR A (52) where A is the contact area. The specific contact re sistance of aluminum1.5 % silicon to ptype silicon with doping c oncentration of 1x1019 cm3 is 1x106 2cm .45 Therefore, the theoretical contact resistance is 0.17 However, the measured contact resistances vary between 10.52 to 39.28 An ideal theoretical cont act resistance is very difficult to predict and achieve. Although the measured contact resi stance is higher than the theoretical contact resistance, the value of the contact resistance, 39.28 is negligible compared to the resistance of the resistor channel, 2200. Therefore, the contact resistance does not affect the measured noise voltage PSD. Next we discuss the Hall Effect measurements. 5.2.5 Hall Effect Test Structure The Hall Effect measurements as described in Chapter 4 have been performed on each implant, solidsource, and annealing process. The Hall Effect measurement allows the computation of the electri cal active dopant that is needed to compute the number of carriers used in the calculation of the Hooge parameter. Figure 511, Figure 512, Figure 513, and Figure 514 show the plot of magnetic field, Z B versus the product of the magnetic field, Z B and the sheet hall coefficientSH R The positive slope indicates a ptype doping profile and gives 96 PAGE 97 the value ofSH R Knowing SH R we then can compute the active dopant c oncentration Table 57 shows the computed active dopant concentration the SIMS dose, Q, and the fraction of activated dose,AANAAN AANQ In some cases, such as pro cess 2E, the calculated electrically active dose exceeds 100 %. This discrepancy is due to errors in the SIMS and Hall effect measurements. The maximum possible percentage for the electrically active dose is 100%. 5.3 Investigation of Process Dependence of 1/F Noise In this section, we measured the noise voltage PSD of each generation 2 process and monitor the low frequency noise as a function of increased anneal time with fixed temperature. The noise measurements of piezoresistors fabricat ed with the process flow shown in Table 3.4 are presented. In generation 2 process, there ar e nine processes that ha ve been used in the fabrication of piezoresistors as shown in Chapte r 3, Section 3.7.2 in order to investigate the process dependence of 1 /f noise. The IV characteristic s and the noise voltage PSDs of piezoresistor for the implanted piezoresistors and for the solid source diffused piezoresistors are presented. The reason why is used for the solid source diffused piezoresistors is because they have a resistance that is the closest to for the implanted piezoresistors. For each process, three noise voltage PSDs were measured at the same bias voltage. The average and standard deviation of th e three noise voltage PSDs of each process was then computed. The noise voltage PSDs are pres ented as a function of the implant condition and annealing processes. The average noise voltage PSDs of the piezoresistors implanted at 20 keV, the average noise voltage PSDs of the piezoresist ors implanted at 40 keV, and the average noise voltage PSDs of the solid source diff used piezoresistors are presented. 6 R 9 R 9 R 6 R 97 PAGE 98 5.3.1 Noise PSD of Piezoresistors R6 for B, 20 keV, 7x1014 cm2, and 7o Tilt The voltage PSD is compared for 20 keV B implanted samples subjected to different annealing times at 900 C. A model is that as th e anneal time increases, th e bulk defect densities decrease. A decrease of defects should result in a reduction of the 1 /f noise PSD. In order to investigate this model hypothesis, piezoresistors are implanted at 20 keV B and annealed at 900 C with times of 20 min, 30 min and 50 min. The defect densities are monitored via the measured 1 /f noise voltage PSDs of the piezoresistors. Th e annealing conditions of the test structures implanted with 20 keV B, at 7x1014 cm2 dose, and 7o tilt are shown in Table 57. The IV characteristics are obtained by varying the volta ge from 10 V to 10 V and are shown in Figure 515 for process 2A. The three noise voltage PSDs of three piezoresistors of wafer 2A (5 min dry, 5 min wet and 10 min dry at 900 C) at same bias voltage are shown in Figure 516. The average and standard deviation of the three noise voltage PSDs are shown in Figure 517. The IV characteristics, the three noise voltage PSDs at same bias voltage of three piezoresistors R6 and the average noise voltage PSDs of wafer 2E (10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C) and wafer 1A (30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C) are also measur ed. In Figure 518, we show the average noise PSDs of wafer 2A, wafer 2E, and wafer 1A which have respec tive corner frequencies are 1900 Hz, 1530 Hz and 958 Hz. The longer the annealing condition (inert and oxidation), th e lower is the noise voltage PSDs and the smaller the corner frequency. In Figure 518, process 2A has a higher noise voltage PSD, followed by process 2E, then by process 1A. The annealing time of process 2A, 2E and 1A are 20 min, 30 min and 50 min at 900 C respectively. The uncertainty of the Hooge parameter is obtained by propagating the uncertain ties of the measured values such as the PSD, the number of carriers, the power dependence of the frequency,6 R and the bias voltage. Three 98 PAGE 99 PSDs are measured for each process. The uncer tainties in the PSDs used to estimate the uncertainty in the Hooge parameter are computed using2 '' 224xx bxx xxGf f Gf Gf (5.3) and 1effrxx dGf n (5.4) The normalized mean square uncertainty2xxGf is obtained through (5.5) 222xx bxx rxxGfGfGf where b and r are the normalized bias and random uncertainties, xxGf is the power spectral density, f is the bandwidth, and is the number of average. The Hooge parameter for each PSD is obtained using6 effdn 2vSNf V (56) The uncertainty associated with the Hooge pa rameter of each of the three PSDs is obtained using46 122 22 2 22 2 12 2 1122JX XX J r JJU UU X UX X rrr rrXXrXXrXX (5.7) 99 PAGE 100 where is an experimental resu lt which is a function of measured variablesrJi X rU ris the relative uncertainty of the result and iX iU X are the relative uncertainties for each variable. The fitted line is obtained from MatLab curve fitting tool, cftool The Hooge parameter is computed at 1 Hz. This makes the frequency f independent of the factor The value of the PSD at 1 Hz used to compute the Hooge parameter is obtained from the fitted line at 1 Hz. The Hooge parameter of each process is obtained by taking th e average of three Hooge parameters extracted as described above on three differ ent devices. The uncertainty in the Hooge parameter is then obtained by applying Equati on 54 to the average shown in Equation 55. 1233 (5.8) Figure 516, shows the PSDs wit hout the setup noise of three different piezoresistors of process 2A (B, 20 keV, 7x1014 cm2, 7o tilt and 5 min dry, 5 min we t and 10 min dry at 900 C). Figure 519, shows the uncertainties of the PSDs fo r each different piezoresistor of process 2A. The fitted lines of the three PSDs of proce ss 2A are shown in Figure 520. The Hooge parameters for each of the three piezoresistors m easured to characterize pr ocess 2A are shown in Table 58. The Hooge parameters for all the processes ar e shown in Table 59. The Hooge parameter for processes 2A, 2E and 1A are respectively 4.41x104 1.38x104, 3.42x104 1.17x104, 1.06x104 3.77x105. The noise voltage PSD shows that as the annealing time increases, the 1 /f noise PSD and the Hooge parameters decrease for the 20 keV B annealed at 900 C. The uncertainties in the extracted Hooge parameter ma ke a definitive conclusion difficult. Extensive measurements over a wider range of process conditions are recommended for future work. 100 PAGE 101 5.3.2 Noise PSD of Piezoresistors R6 for B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 The voltage PSD is compared for 40 keV B implanted samples subjected to different annealing times at 900 C. The decrease of the de fect densities are monitored via the measured 1 /f noise voltage PSD of the piezoresistors. The piezoresistors implanted at 40 keV are annealed at 900 C with times of 10 min, 30 min, 50 min and 90 min. The same measurements described in Section 5.3.1 for the IV characteristics and average noise voltage PSDs are performed for the wafers implanted at B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2. Figure 521 shows the average noise voltage PSDs of wafer 2B and wafe r 5A which were not oxidized after the inert anneals as shown in Table 58. The corner fr equency for wafer 2B is 1790 Hz and 1680 Hz for wafer 5A. The longer the anneal ing condition (inert) the lower is the noise voltage PSDs and the smaller the corner frequency. Processes 2B a nd 5A are annealed respectively for 10 min and 90 min respectively at 900 C and the noise voltage of pr ocess 2B is higher than that of process 5A. Figure 522 shows the average noise voltage PSDs of wafer 3E and wafer 4A with respective corner frequencies of 442 Hz and 2960 Hz. The annealing conditions of process 3E and 4A are shown in Table 58. In contrast to wafer 2B and wafer 5A, the wafer 4A with the longer the annealing condition (inert and oxi dation) shows higher noise and co rner frequency than wafer 3E with shorter annealing. The Hooge parameter is computed as described in Section 5.3.1 with the number carriers obtained from Hall Effect measur ement of process 2B, 3E, 4A and 5A. Table 58 shows the Hooge parameters. The Hooge parameter for pro cesses 2B, 5A, 3E, and 4A are respectively 9.67x104 4.13x104, 4.94x104 1.73x104, 8.58x105 2.84x105, 7.97x104 3.15x104. As the annealing time increases, the 1 /f noise PSDs and the Hooge parameters for processes 2B and 5A that were not oxidized decrease. However, for the oxidized processes 3E and 4A where the annealing time increases, the noise voltage PSD also increases. The 40 keV 101 PAGE 102 with oxidation gives unexpected resu lts. This could be explained by the faulted loop areas in the piezoresistors as discussed in Chapter 6. 5.3.3 Noise PSD of SolidSource Diffused Piez oresistors R9 of Wafers C1 and C2 Solid source diffusion is used to avoid dama ge created in the pi ezoresistor during ion implantation. However, interface traps at the Si/SiO2 interface are sti ll present in the piezoresistors. Hence, 1 /f noise can still originate from the in terface traps. To study the effect of the interface traps on the 1 /f noise two processes for solid sour ce diffusion were made. Process C1 was solid source diffused with B for 25 min at 950 C while process C2 was first solid source diffused with B for 25 min at 950 C and then solid source diffused with P for 5 min at 800 C. The phosphorous solid source diffusion is used to re duce the interaction of the carriers with the interface traps during device operati on. Piezoresistor test structure 9 is used for the noise measurements because it has a resistance in some cases comparable to each other and comparable to those of R6 for the implanted resistors in other cases. The IV characteristics are shown in Figure 523 and Figure 524 for proces s C1 and C2 respectively. The IV of both processes are linear from 10 V to 10 V, but those of C2 do not overlap as reflected in the observed variation of resistances as shown in Table 51. The av erage noise voltage PSDs of C1 and C2 are shown in Figure 525. The average nois e voltage PSD of wafer C2 is lower than that of wafer C1 and their respectiv e corner frequencies 112 Hz are and 418 Hz. The lower average noise voltage PSD of C2 could be due to the pho sphorus deposition after the boron diffusion. It is possible that surface traps may not play an important role in the noise magnitude of C2 since the phosphorous near the surface would push the hol es distribution away from the surface traps at the Si/SiO2 interface. The surf ace trap density is computed in the next chapter. The other possible explanation for lower noise is a larger number of carriers N To verify this assumption, we substituted the number of carriers of C2 into the Hooge expression of the 1 /f noise, Equation 102 PAGE 103 217, at 1 Hz. The noise voltage PSD resulting from that computation, pr esented in Figure 526, shows a decrease in the noise voltage PSD; however, the value of the noise voltage PSD of C1 at 1 Hz does not overlap with that of C2 at 1 Hz Although, the Hooge mode l is based on mobility fluctuations (bulk defects), it is used as a figure of merit for the solid source diffused piezoresistors which have much lo wer bulk defects and where the 1 /f noise is presumably due to carrier fluctuations (surface def ects). The Hooge parameter is co mputed obtained as described in Section 5.3.1 with the number car riers obtained from Ha ll Effect measurement of process C1 and C2. Table 58 shows the Hooge parameters. Th e Hooge parameter for process C1 and C2 are respectively 6.89x104 2.92x104, and 2.38x104 1.20x104. The noise voltage PSD shows that the process, C2, with phosphorus solid source diffusion has lower1 /f noise voltage PSD and Hooge parameters than the proc ess without phosphorous, C1. In the absence of ion implantation induced defects, the noise voltage PSD measurements indicate that the phosphorus solid source diffusion may play a role in the noise reduction by keeping the holes away from the interface traps. Next we analyze the noise voltage. 5.4 Hooge Parameter and 1/F Noise Analysis and Discussion In this section, we analyz e the measured noise voltage PSDs in terms of their Hooge parameter As mentioned earlier, the Hooge paramete r is employed as an empirical a figure of merit of the quality of the crystal. There are other models such as the McWhorter model7 which is based on the carrier fluctuation. The number of carriers, used to compute the Hooge parameter is estimated from Hall effect measurements. The uncertainty in is obtained by propagating the uncertainties of the dose and of the areaN NQ A NQA (5.9) 103 PAGE 104 After diffusion, the length and width of the resi stor differ from that of the actual mask. The largest possible increase in the width and length is2 j x where j x is the junction depth as illustrated in Figure 527. For the measured resi stors, the length and widths are 245 m and 24.3 m respectively. The junction depth m easured with SIMS is 0.5 m. Thus 2 j x is 1 m. A 3 % uncertainty in the area was used to account for late ral diffusion. The Hooge parameters of all the processes are shown in Table 58 where it is obse rved that the Hooge parameter decreases as the defect density decreases with in creased annealing time except for processes 3E and 4A. In these two processes implanted with B 40 keV and subj ected to inert anneal and oxidation, the PSDs appear to track the faulted loop area s as it is discusse d in Chapter 6. Current crowding on metal c ontacts has been studied by Murrmann and Widmann.47 Current crowding may cause localized heating a nd thus play a role in electromigration. However, the current density in the resistor durin g noise measurement is very low; for example, the current density used during th e measurement of process 2A is 22.56x10 Acm2, over three orders of magnitude lower than the typical current density th reshold for electromigration. Therefore, current crowding is not an issue in the measurements. During oxidation, boron segregates into the silicon dioxi de. Therefore, there is a re duction of the boron dose in the silicon. The implanted boron dose was 7x1014 cm2. Using the SIMS profiles after oxidation, the boron dose in the silicon varies from 4.5x1014 to 6.7x1014 cm2. This indicates that approximately 36 % to 4.3 % of the boron dose resides in the silic on dioxide. The effect of the boron inside the silicon dioxide on the measured no ise PSD needs to be studied. 5.5 Shot Noise Measurements The shot noise is measured on piezoresistors in stead of the fabricated P/N diodes to have an insight of the quality of the defects in the pi ezoresistors. The P/N diode IV characteristics of 104 PAGE 105 resistor 6, diode 1 and diode 2 of process 1A of generation 2 are shown in Figure 58. Figure 528 shows the shot noise of R6 for process 1A. Th e current used for the measurement is taken in the linear region of the IV. The shot noise m easurements of piezoresistor R6 of process 1A reveal the presence of high density bulk and surf ace defects. The shot noise magnitude given by Equation 221 is obtained in the measurement at high frequencies (> 1x104 Hz). This is an indication of significant def ects in the crystal lattice. 5.6 Number of Carrier Dependence of 1/F Noise In this section we study the ef fect of the number of carrier s on the low frequency noise. We use piezoresistor test structures 1, 6 and 12 of generation 1 process for the investigation. The process flow of generation 1 process is described in Appendix D. 5.6.1 Fabrication and Measurements of Test Structures The test structures have been fabricated at MEMSexchange, Coresy stems and at the UF nanofabrication clean room. ME MSexchange services have b een used for the annealing treatments. The ion implantations of piezoresi stors have been done at Coresystems. As discussed in Chapter 3, piezoresi stors were designed to have th e same resistance with different surface areas and volumes. In Figure 529 we show the top views and a crosssection of piezoresistors test structures 7 (R1B7N), 8 (R1B8E) and 9 (R1B9W) which have different dimensions but respective resistance values of 8217.17 8209.27 and 8419.17 Measured resistances of the fabricated junction isolated piezoresi stors are shown in Table 510. The boron profile obtained via secondary ion mass spectroscopy (SIMS) performed by Evans Analytical Group is shown in Figure 530. In Figure 530, the surface concentration is about 1x1018 cm3 and junction depth is abou t 2.27 m. The Van der Pauw structures are used to measure the sheet resistance, line width, and cont act resistance. The measured sheet resistance is 105 PAGE 106 178.70 / The line width and contact resistance using Equation 320 and Equation 321 are respectively 0.018 m and 4 5.6.1 Noise PSD Measurements In order to explore the number of carrier and surface to volume ratio dependency of 1 /f noise, we perform noise measuremen ts on piezoresistors and 1, 2, 3 and 12. Piezoresistors 1, 2, and 3 have the same resistance but different num ber of carriers while piezoresistor 12 have a different resistance and number of carrier. Table 510 shows th e piezoresistor nomenclatures and their resistances. In Table 510, the nomencl ature R1B1W means piezo resistor of row 1, from quadrant B in the wafer, piezo resistor test structur e 1 and location west in the chip. This allows us to avoid measuring the same piezoresistor multiple times. The number of carriers used to compute the Hooge parameter is extracted using the SIMS profiles since there was no space reserved for Hall Effect measurement. Although SIMS gives the atomic concentration of the dopant, it will be sufficient for our application wh ich is to see how the num ber of carriers affects the 1 /f noise. However, the number of carriers obta in from SIMS is not appropriate for the computation of the Hooge parameter. The number of carriers, is obtained by multiplying the dose, Q obtained from the SIMS profile with the piezoresistor areaN A NQA (510) The IV characteristics and noise voltage power spectral density (PSD) of three piezoresistor test structures 1 have been measur ed. Figure 531 shows th e IV characteristic of piezoresistor R1B1W at three bias voltages. The noise voltage PSDs are shown in Figure 532. The corner frequency, which is the frequency at which the 1 /f noise and the thermal noise coincide, when the piezoresistor is biased at 4.65 V dc is larger than 12.8 kHz. Figure 533 shows the IV characteristic of piezoresistor R3A 12E. The noise voltage PSD is shown in Figure 106 PAGE 107 534. The corner frequency when the piezoresistor is biased at 1.48 V dc is around 70 Hz. At the same bias voltage, piezoresistor 12 has less noise and smaller corner frequency than piezoresistor 1. To obtain insight about the de fect concentration in the pi ezoresistor bulk, shot noise measurements are performed on the junction isolated piezoresistor test structure 1. First, the IV characteristic of the P/N diode as shown in Figur e 535 is measured. The shot noise is measured for currents of 1.54x107, 3.30x107, and 4.81x107 A, which are in the linear region of the P/N diode IV characteristic. Figure 536 shows the shot noise of piezoresistor test structure 1. In Figure 536, the corner frequencyc f is 10 Hz (I = 1.54 x107) which is much lower than that of resistor 6 of process 1A. 5.6.2 Analysis and Discussion In this section, we analyze the measured noi se voltage PSDs in terms of their number of carriers and dimensions (surface ar ea and volume). In this secti on it is shown how the number of carriers affects the low noise frequency. Piezoresistor 1 has been designed to have a smaller area than piezoresistor 12. Figure 537 shows the noise voltage PSDs of piezoresi stor test structure 1 (R1B1W) and piezoresistor test structure 12 (R3A12E) biased at 1.49 Vdc and 1.48 Vdc respectively. In Figure 537, th e noise voltage PSD of piezoresi stor test structure 12 (R3A12E) is smaller than that of piezoresistor test structur e 1 (R1B1W). This may be due to the fact of a larger number of carriers for pi ezoresistor test st ructure 12 (R3A12E). Hooges empirical relation of the 1 /f noise (Equation 217) shows that the 1 /f noise is inversely proportional to the number of carriers, To further investigate the effect of the number of carriers we perform noise measurements of three piezoresistors with identical resistances. Some piezoresistors were designed to have the same resistance value and different surface area and volume. This is for N 107 PAGE 108 example the case of piezores istor test structures 1, 2 and 3. As shown in Table 31, piezoresistor test structure 3 has the larger surface area and volume followed by piezoresistor test structure 2 and piezoresistor test structure 1. In addition, these piezoresistors have the same junction depth thus different number of carriers. Th e effect of the surface at the Si/SiO2 interface cannot be used for the noise analysis since all piezoresi stors have the same surface to volume ratio. A same surface to volume ratio means that the carriers in the piezoresistors are equally affected by the surface traps. Therefore, the main parameter that affects the 1 /f noise is the number of carriers. Figure 538 A) and B) show the noise voltage PSDs of piezoresistor test structures 1, 2 and 3 biased respectively at 4.69 Vdc, 4.80 Vd c and 4.88 Vdc. In Figure 538 A), among the three piezoresistor test structures, piezoresistor test structure 3 which ha s the largest number of carriers has the lowest 1 /f noise voltage PSD. Figure 538 B) shows the noise PSD at 10 Hz for piezoresistors123, and R RR at the same bias voltage as a function of number of carriers. The noise voltage PSD decreases as th e number of carrier increases. 5.7 Summary The fabricated test structures and the measur ements based on the experimental methods of Chapter 4 have been presented. The carrier concentrations using the Hall measurement, and the sheet resistance, contact resistance and line width using the Van de r Pauw structure are measured. The CV of the pMOSC is presented and the oxide thickness computed. The IV of the piezoresistors is linear from 10 V to 10 V. It is shown th at the average noise voltage PSDs for the implanted piezoresistors decreases as the annealing time increases for the 20 keV implant and for the 40 keV process without oxidation. However, an exception of the decrease of the 1 /f noise with longer annealing is ob served for the 40 keV process, 3E and 4A, with oxidation. The process with longer annealed time, 4A, has higher noise voltage PSD magnitude than of 3E with 108 PAGE 109 shorter anneal time. The measured shot noise for the generation 2 process coincides with the theoretical shot noise at high frequencies (>1x104 Hz) which is an indication of the presence of defects in the crystal. The 1 /f noise dominates at low frequencie s. The shot noise of generation 1 process shows a corner frequency at 10 Hz. This indicates less bulk defect s in the piezoresistor of the generation 1 process. The effect of the number of carriers was st udied with resistors of different resistance and dimensi ons as well as resistors of sa me resistance and different dimensions. The noise voltage PSDs show that re sistors with larger number of carriers have less 1 /f noise. Next, the defects in the test structures are measured and the analyses of the relations of the defects to the measured noise voltage PSD of piezoresistor generation 2 are also performed. 109 PAGE 110 Table 51. Resistance of piezore sistors of generation 2 process. Implant and annealing Piezoresistor ( ) B, 20 keV, 7x1014 cm2, 7o tilt R6 5 min dry, 5 min wet and 10 min dry at 900 C (2A) 2288, 2277, 2269 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (2E) 2188, 2198, 2212 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (1A) 2153, 2173, 2149 B, 40 keV, 7x1014 cm2through 0.1 m of SiO2 R6 10 min N2 at 900 C (2B) 2010, 2019, 2009 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (3E) 2206, 2229, 2203 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (4A) 2160, 2178, 2145 90 min N2 at 900 C (5A) 1688, 1681, 1670 Solid source diffusion of B, 25 min, 950 C R9 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C1) 4337, 4367, 4387 Solid source diffusions of B, 25 min, 950 C and P, 5 min, 800 C R9 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C2) 2277, 2653, 3586 Table 52. The junction depths and surface concentrations of SIMS profiles of generation 2 process. Implant and annealing conditions Junction Depth (m) Surface concentration (cm3) B, 20 keV, 7x1014 cm2, 7o tilt 5 min dry, 5 min wet and 10 min dry at 900 C (2A) 0.54 1.42x1019 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (2E) 0.46 1.80x1019 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (1A) 0.53 1.78x1019 B, 40 keV, 7x1014 cm2through 0.1 m of SiO2 10 min N2 at 900 C (2B) 0.58 1.46x1019 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (3E) 0.47 1.69x1019 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (4A) 0.52 2.17x1019 90 min N2 at 900 C (5A) 0.59 3.45x1019 Solid source diffusion of B, 25 min, 950 C 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C1) 0.85 1.15x1019 Solid source diffusions of B, 25 min, 950 C and P, 5 min, 800 C 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C2) 0.97 1.63x1019 Table 53. Dimensions of the pMOSC1 and pMOSC2 of generation 2 process. Sructure Dimension (m) pMOSC1 400 x 400 pMOSC2 700 x 700 110 PAGE 111 Table 54. Measured oxide thicknesses with Ellipsometer and pMOSC CV of generation 2 process. Implant and annealing conditions Ellipsometer () pMOSC () B, 20 keV, 7x1014 cm2, 7o tilt 5 min dry, 5 min wet and 10 min dry at 900 C (2A) 231.75 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (2E) 252.12 301.68 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (1A) 253.32 327.35 B, 40 keV, 7x1014 cm2through 0.1 m of SiO2 10 min N2 at 900 C (2B) 1003.2 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (3E) 1131.40 1252.00 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (4A) 1079.40 1148.80 90 min N2 at 900 C (5A) 962.52 1065.70 Solid source diffusion of B, 25 min, 950 C 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C1) 276.33 313.25 Solid source diffusions of B, 25 min, 950 C and P, 5 min, 800 C 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C2) 264.19 303.93 Table 55. Dimensions of the thr ee P/N diodes of generation 2 process. Sructure Dimension (m) Resistor 6 245 x 24.33 Diode 1 371.7 x 332.9 Diode 2 571.7 x 523.9 Table 56. MeasuredS R and W C R of generation 2 processes. Annealing RS ( ) W (m) RC ( ) B, 20 keV, 7x1014 cm2, 7o tilt 5 min dry, 5 min wet and 10 min dry at 900 C (2A) 224.87 2.04 28.98 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (2E) 217.02 2.20 27.00 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (1A) 210.23 2.16 25.43 B, 40 keV, 7x1014 cm2through 0.1 m of SiO2 10 min N2 at 900 C (2B) 194.03 1.92 24.02 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (3E) 215.08 1.97 39.28 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (4A) 205.19 1.79 28.71 90 min N2 at 900 C (5A) 165.44 2.24 22.60 Solid source diffusion of B, 25 min, 950 C 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C1) 91.07 4.88 14.51 Solid source diffusions of B, 25 min, 950 C and P, 5 min, 800 C 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C2) 61.22 2.95 10.52 111 PAGE 112 Table 57. Computed electrical active dose, implanted dose, Q, and fraction of active dose AAN AANQ for each generation 2 process. Implant, solidsource and anneal condition NAA (cm2) Q (cm2) NAA / Q (%) B, 20 keV, 7x1014 cm2, 7o tilt 5 min dry, 5 min wet and 10 min dry at 900 C (2A) 5.6x1014 5.6x1013 4.7x1014 4.1x1013 85 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (2E) 4.6x1014 4.6x1013 4.9x1014 3.1x1012 108 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (1A) 5.2x1014 5.2x1013 5.2x1014 3.9x1013 101 B, 40 keV, 7x1014 cm2through 0.1 m of SiO2 10 min N2 at 900 C (2B) 4.5x1014 4.5x1013 6.4x1014 8.1x1013 142 90 min N2 at 900 C (5A) 6.7x1014 6.7x1013 6.3x1014 1.3x1012 94 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (3E) 4.6x1014 4.6x1013 5.3x1014 6.0x1013 116 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (4A) 5.6x1014 5.6x1013 4.7x1014 5.4x1013 83 Solid source diffusion of B, 25 min, 950 C 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C1) 7.3x1014 7.3x1013 7.6x1014 7.9x1012 NA Solid source diffusions of B, 25 min, 950 C and P, 5 min, 800 C 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C2) 1.1 x1015 1.1x1014 1.5x1015 1.8x1013 NA Table 58. Hooge parameters of each of the three piezoresistors of process 2A (B, 20 keV, 7x1014 cm2, 7o tilt and 5 min dry, 5 min wet and 10 min dry at 900 C). Process Hooge parameter 2A1R6 6.27x104 1.13x104 2A2R6 2.55x104 4.37x105 2A3R6 4.39x104 8.30x105 Table 59. Hooge parameter using number of carrier obtained from Hall Effect measurements of generation 2 process. Implant and Annealing B, 20 keV, 7x1014 cm2, 7o tilt 5 min dry, 5 min wet and 10 min dry at 900 C (2A) 4.41x104 1.38x104 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (2E) 3.42x104 1.17x104 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (1A) 1.06x104 3.77x105 B, 40 keV, 7x1014 cm2through 0.1 m of SiO2 10 min N2 at 900 C (2B) 9.67x104 4.13x104 90 min N2 at 900 C (5A) 4.94x104 1.73x104 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (3E) 8.58x105 2.84x105 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (4A) 7.97x104 3.15x104 Solid source diffusion of B, 25 min, 950 C 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C1R9) 6.89x104 2.92x104 Solid source diffusions of B, 25 min, 950 C and P, 5 min, 800 C 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (C2R9) 2.38x104 1.20x104 112 PAGE 113 Table 510. Resistance of fabricated junction isolated piezore sistors of generation 1 process. Piezoresistor test structure Xj ( m) L ( m) W ( m) (L/W) R ( ) 1 (R1B1W) 2.27 70 13.9 5.04 757.63 2 (R1A2N) 2.27 105 20.85 5.04 780.73 3 (R1B3S) 2.27 122.5 24.33 5.04 811.00 4 (R1A4W) 2.27 140 13.90 10.07 1524.27 5 (R1A5N) 2.27 210 20.85 10.07 1603.56 6 (R1A6W) 2.27 245 24.33 10.07 1611.01 7 (R1B7N) 2.27 700 13.90 50.36 8217.17 8 (R1B8E) 2.27 1050 20.85 50.36 8209.27 9 (R1B9E) 2.27 1225 24.33 50.36 8419.17 10 (R1B10N) 2.27 1400 13.90 100.72 15843.87 11 (R1B11N) 2.27 2100 20.85 100.72 16188.90 12 (R3A12E) 2.27 2450 24.33 100.72 16496.49 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 1017 1018 1019 1020 1021 Depth (m)Concentration (cm3) B, 20keV, 7e14cm2, 7o tilt asimplant into silicon Figure 51. Asimplant profile s of boron with B, 20 keV, 7x1014 cm2, 7o tilt of generation 2 process. 113 PAGE 114 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 1017 1018 1019 1020 1021 Depth (m)Concentration (cm3) 40keV, 7e14cm2 asimplant through 1000 A of oxide into silicon SiO2 Si Figure 52. Asimplant profile s of boron with B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 of generation 2 process. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1016 1017 1018 1019 1020 1021 Depth (m)Concentration (cm3) 2A Oxidation (5 min dry, 5 min wet and 10 min dry at 900 C) 2E Inert anneal (10 min at 900 C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) 1A Inert anneal (30 min at 900C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) B, 20 keV, 7x1014 cm2, 7o tilt SiO2 Si Figure 53. SIMS profiles of wafers with B, 20 keV, 7e14 cm2, 7o tilt of generation 2 process. 114 PAGE 115 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1016 1017 1018 1019 1020 1021 Depth (m)Concentration (cm3) 3E Inert anneal (10 min at 900 C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) 2B Inert anneal (10 min dry at 900 C) 4A Inert anneal (30 min at 900C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) SiO2 B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 Si5A Inert anneal (90 min dry at 900 C) Figure 54. SIMS profiles of wafers with B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 of generation 2 process. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1016 1017 1018 1019 1020 Depth (m)Concentration (cm3)SiO2/Si interface B in C2 C2 (Solid source diffusion B, 25 min, 950 C and P, 5 min, 800 C), Inert anneal (30 min at 900 C), Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) P in C1 B in C1 C1 (Solid source diffusion B, 25 min, 950 C), Inert anneal (30 min at 900 C), Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) P in C2 Figure 55. SIMS profiles of solidsource diffused wafers C1 a nd C2 of generation 2 process. 115 PAGE 116 Figure 56. Piezoresist or test structure 9 of generation 2 process. 2 1 0 1 2 3 4 5 6 525 530 535 540 545 550 555 560 565 Voltage (V)Capacitance (pF)B, 20keV, 7x1014 cm2, 7o tiltInert anneal (10 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) 2E Figure 57. CV measurement of pMOSC2 of wafer 2E of generation 2 process. 116 PAGE 117 0.5 0 0.5 1 0 0.2 0.4 0.6 0.8 1 1.2 Volta g e ( V ) Current (mA)B, 20 keV, 7x1014 cm2, 7o tiltDiode 1 Diode 2 Resistor 6 1A Inert anneal (30 min at 900 C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) Figure 58. IV characteristics of Resistor 6, Diode 1 and Diode 2 of process 1A of generation 2 process. 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 10 9 8 7 6 5 4 3 2 1 x 109 Volta g e ( V ) C urren t (A ) Diode 1 B, 20 keV, 7e14 cm2, 7o tilt 1A Inert anneal (30 min at 900 C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) Thermal generation in the depletion region Figure 59. Logarithmic scale of the reve rse bias Diode 1 of generation 2 process. 117 PAGE 118 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 109 108 107 106 105 104 103 Voltage (V)Current (A)B, 20 keV, 7e14 cm2, 7o tilt 1A Inert anneal (30 min at 900 C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) Diode 1 Figure 510. Forward bias current of Diode 1 of generation 2 process. 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 0.5 1 1.5 2 x 108 RSH2A = 1.30x104 1130 cm2/C 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 0.5 1 1.5 2 x 108 RSH2E = 1.26x104 80 cm2/C 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 0.5 1 1.5 2 x 108 Bz (G)Bz RSH (G*cm2/C)RSH1A = 1.19x104 890 cm2/C Figure 511. Sheet hall coefficientSH R for the B, 20 keV, 7x1014 cm2, 7o tilt implanted piezoresistors of generation 2 process. 118 PAGE 119 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 2 4 6 8 10 12 x 107 RSH2B = 9708 1234 cm2/C 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 2 4 6 8 10 12 x 107 Bz (G)Bz RH (G*cm2/C)RSH5A = 9915 21 cm2/C Figure 512. Sheet hall coefficientSH R for the B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 implanted piezoresistors subjected to only inert annealing of generation 2 process. 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 5 10 15 x 107 RSH3E = 1.16x104 1300 cm2/C 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 5 10 15 x 107 Bz (G)Bz RSH (G*cm2/C)RSH4A = 1.32x104 1530 cm2/C Figure 513. Sheet hall coefficientSH R for the B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 implanted piezoresistors subjected to iner t annealing and oxidation of generation 2 process. 119 PAGE 120 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 0 5 10 x 107 RSHC1 = 8183 86 cm2/C 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 0 5 10 x 107 Bz RSH (G*cm2/C)Bz (G) RSHC2 = 3946 45 cm2/C Figure 514. Sheet hall coefficientSH R for the solid source diffused piezoresistors of generation 2 process. 5 4 3 2 1 0 1 2 3 4 5 10 8 6 4 2 0 2 4 6 8 10 Current (mA)Voltage (V) 2A1 R6 (2288 ) 2A2 R6 (2277 ) 2A3 R6 (2269 ) Figure 515. IV characteris tic of resistor 6 of wafer 2A of generation 2 process. 120 PAGE 121 100 101 102 103 104 1016 1015 1014 1013 1012 Fre q uenc y ( Hz ) SVDUT (Vrms 2/Hz) 2A1R6 (2288 ) at 3.34 Vdc 2A2R6 (2277 ) at 3.34 Vdc 2A3R6 (2269 ) at 3.32 Vdc Thermal noise of 2A1R6 Figure 516. Noise voltage PSD of piezoresistor R6 of wafer 2A of generation 2 process. 100 101 102 103 104 1016 1015 1014 1013 1012 Fre q uenc y ( Hz ) SVDUT (Vrms 2/Hz) 2AR6 average PSD at 3.33 Vdc B, 20keV, 7x1014 cm2, 70 tilt 2A Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900) Figure 517. Noise voltage averag e PSD of three piezoresistors R6 of wafer 2A of generation 2 process. 121 PAGE 122 100 101 102 103 104 1016 1015 1014 1013 1012 Frequency (Hz)SVDUT (Vrms 2/Hz)B, 20keV, 7x1014 cm2, tilt 7o2A at 3.33 0.01 V 2E at 3.32 0.02 V 1A at 3.26 0.03 V2A Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) 2E Inert anneal (10 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) 1A Inert anneal (30 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) Figure 518. Noise voltage PSDs average of three piezoresistors R6 of wafer 2A, 2E, and 1A of generation 2 process. 100 101 102 103 104 1016 1014 1012 2A1R6 (2288 ) at 3.34 Vdc Uncertainty 2A1R6 (2288 ) at 3.34 Vdc 2A1R6 (2288 ) at 3.34 Vdc + Uncertainty 100 101 102 103 104 1016 1014 1012 SVDUT (Vrms 2/Hz)2A2R6 (2277 ) at 3.34 Vdc 2A2R6 (2277 ) at 3.34 Vdc Uncertainty 2A2R6 (2277 ) at 3.34 Vdc + Uncertainty 100 101 102 103 104 1016 1014 1012 Frequency (Hz) 2A3R6 (2269 ) at 3.32 Vdc 2A3R6 (2269 ) at 3.32 Vdc Uncertainty 2A3R6 (2269 ) at 3.32 Vdc + Uncertainty 2A1R6 2A2R6 2A3R6 Figure 519. PSDs and their uncer tainties of three different piezo resistors of .process 2A (B, 20 keV, 7x1014 cm2, 7o tilt and 5 min dry, 5 min wet and 10 min dry at 900 C). 122 PAGE 123 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 15.5 15 14.5 14 13.5 13 12.5 Log10(Frequency (Hz))Log10(SVDUT (Vrms 2/Hz))2A1R6 PSD at 3.34 Vdc 2A2R6 PSD at 3.34 Vdc 2A3R6 PSD at 3.32 Vdc Figure 520. The fitted lines of the th ree PSDs of process 2A (B, 20 keV, 7x1014 cm2, 7o tilt and 5 min dry, 5 min wet a nd 10 min dry at 900 C). 100 101 102 103 10 4 1016 1015 1014 1013 1012 Frequency (Hz)SVDUT (Vrms 2/Hz)B, 40keV, 7x1014 cm2, throught 0.1 m of SiO22B at 3.35 0.01 V 5A at 3.37 0.01 V 2B Inert anneal (10 min at 900 C) 5A Inert anneal (30 min at 900 C) Figure 521. Noise voltage aver age PSDs of three piezoresistors R6 of wafer 2B and 5A of generation 2 process. 123 PAGE 124 100 101 102 103 10 4 1016 1015 1014 1013 1012 Frequency (Hz)SVDUT (Vrms 2 /Hz)B, 40keV, 7x1014 cm2, throught 0.1 m of SiO23E at 3.34 0.07 V 4A at 3.35 0.02 V4A Inert anneal (30 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) 3E Inert anneal (10 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) Figure 522. Noise voltage aver age PSDs of three piezoresistors R6 of wafer 3E and 4A of generation 2 process. 2.5 2 1.5 1 0.5 0 0.5 1 1.5 2 2.5 10 8 6 4 2 0 2 4 6 8 10 Current (mA)Voltage (V) C11 R9 (4337 ) C12 R9 (4367 ) C13 R9 (4387 ) Figure 523. IV characteristic of piezoresistor R9 of wafer C1 of generation 2 process. 124 PAGE 125 5 4 3 2 1 0 1 2 3 4 5 10 8 6 4 2 0 2 4 6 8 10 Current (mA)Voltage (V) C21 R9 (2277 ) C22 R9 (2653 ) C23 R9 (3586 ) Figure 524. IV characteristic of piezoresistor R9 of wafer C2 of generation 2 process. 100 101 102 103 10 4 1016 1015 1014 1013 1012 Fre q uenc y ( Hz ) SVDUT (Vrms 2/Hz)C1 Solid source diffusion of B for 25 min at 900 C C2 Solid source diffusions of 1) B for 25 min at 900 C 2) P for 5 min at 800 C C1 at 3.46 0.04 V C2 at 3.41 0.09 V Inert anneal (30 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) Figure 525. Noise voltage average PSDs of three piezoresistors R9 of wafer C1 and C2 of generation 2 process. 125 PAGE 126 100 101 102 103 10 4 1016 1015 1014 1013 1012 Frequency (Hz)SVDUT (Vrms 2/Hz)C1 at 3.46 0.04 V PSD of C1 with N of C2 at 1Hz C2 at 3.41 0.09 V Figure 526. Noise voltage PSDs of C1 and C2 with N of C2 used for C1 at 1Hz of generation 2 process. L L+2Xj Xj A) B) Resistor dimension in mask Resistor dimension after diffusion xx Figure 527. Resistor geometry before and after diffusion, A) planview and B) crosssection. 126 PAGE 127 100 101 102 103 104 10 5 1025 1024 1023 1022 1021 1020 1019 Frequency (Hz)SI (A2 rms/Hz)Theoritical shot noise B, 20 keV, 7x1014 cm2, 7o tilt1A Resistor 6 Figure 528. Shot noise of resi stor 6 of process 1A of genera tion 2 of generation 2 process. A1 A2 127 PAGE 128 A3 B Figure 529. Top views of piezo resistors test structures 7 A1 ), 8 A2) and 9 A3) and a crosssection B) of generation 1 process. 1.E+15 1.E+16 1.E+17 1.E+18 1.E+19 1.E+20 0.00E+005.00E011.00E+001.50E+002.00E+002.50E+00Depth ( m)Concentration (cm3) B,5keV,6e14cm2 SIMS Figure 530. Secondary ion mass spectroscopy (S IMS) obtained from Ev ans Analytical Group for the fabricated piezoresist ors of generation 1 process. 128 PAGE 129 R1B1Wy = 757.63x 9E05 8 4 0 4 8 0.01 0.005 0 0.005 0.01 Current (A)Voltage (V) Figure 531. IV characteristic of piezor esistor R1B1W of generation 1 process. 1E17 1E16 1E15 1E14 1E13 1E12 1E11 1.E+001.E+011.E+021.E+031.E+04 Frequency (Hz)Sv (V2/Hz) Theoritical thermal noise 4.65 Vdc 3.07 Vdc 1.49 Vdc R1B1W Figure 532. Noise voltage PSD of R1B1W of generation 1 process. 129 PAGE 130 R3A12Ey = 16496.49x 0.00 8 4 0 4 8 0.0005 0.00025 0 0.00025 0.000 5 Current (A)Voltage (V) Figure 533. IV characteristic of piezores istor R3A12E of generation 1 process. 1E16 1E15 1E14 1E13 1E12 1.E+001.E+011.E+021.E+031.E+0 4 Frequency (Hz)Sv (V2/Hz) Theoritical thermal noise 4.59 Vdc 3.04 Vdc 1.48 VdcR3A12E Figure 534. Noise voltage PSD of R3A12E of generation 1 process. 130 PAGE 131 1.E14 1.E13 1.E12 1.E11 1.E10 1.E09 1.E08 1.E07 1.E06 1.E05 1.E04 1 E 03 0.00.10.20.30.40.50.60.70.80.91.0 Voltage (V)Current (A) Figure 535. IV characteristic of junction isolated piezoresistor test structure 1 (R1B1W) of generation 1 process. 1E27 1E26 1E25 1E24 1E23 1E22 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 Frequency (Hz)Si (A2/Hz) I = 4.81x107 A I = 3.30x107 A I = 1.54x107 A R1B1W Figure 536. Shot noise of pi ezoresistor test structure 1(R1 B1W) of generation 1 process. 131 PAGE 132 1E17 1E16 1E15 1E14 1E13 1E12 1E11 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 Frequency (Hz)Sv (V2/Hz) R1 (R1B1W) at 1.49 Vdc R12(R3A12E) at 1.48 Vdc Figure 537. Noise voltage PSD of piezoresistor test structure 1 (R1B1W) and piezoresistor test structure 12 (R3A12E) are biased resp ectively at 1.49 Vdc and 1.48 Vdc of generation 1 process. 1E17 1E16 1E15 1E14 1E13 1E12 1E11 1.E+001.E+011.E+021.E+031.E+04 Frequency (Hz)Sv (V2/Hz) R1 (R1B1S) at 4.69 Vdc R2 (R1A2S) at 4.80 Vdc R3(R1A3S) at 4.88 VdcA 132 PAGE 133 1E14 1E13 1E12 1.E+09 4.E+09 7.E+09 1.E+10 Number of carriersSv (V2/Hz) f = 10 Hz R1 (R1B1S) at 4.69 Vdc R2 (R1A2S) at 4.80 Vdc R3(R1A3S) at 4.88 Vdc B Figure 538. Noise measurement PSDs A) of piezoresistors123, and R RR at same voltage and B) of number of carriers of piezoresistors123, and R RR at same voltage of generation 1 process. 133 PAGE 134 CHAPTER 6 DEFECTS MEASUREMENTS AND ANALYSIS In this Chapter, further studies of the process dependence of 1 /f noise are performed by using transmission electron microscopy (TEM) to vi sualize the bulk defects in the piezoresistors and the high frequency CV of pMOSC to extr act the density of in terface traps for each fabrication process of generation 2. 6.2 Bulk Defects in Piezoresistors The experimental methods to compute the bu lk defects and interface trap densities were described in Chapter 4. The bul k defects are studied with XTEM and PTEM. In Section 4.4, XTEM and PTEM are described. The sample preparation for XTEM is done with focus ion beam, which allows a thin section of the piezoresistor to be cut from the sample as shown in Figure 61. For a PTEM sample preparation, a sa mple is thinned, then a hole a made in the sample. The PTEM are taken with the same magnification for consistency. 6.2.1 CrossSection Transmissi on Electron Microscopy (XTEM) The XTEM is used to see th e depth of the defects into the samples. The XTEM of piezoresistor implanted with B, 7x1014 cm2 at 20 keV, 40 keV and solid source diffused are shown in Figure 62, Figure 63 and Figure 64. All the implanted piezoresistors show dislocation loops while those that are solid source diffused do not show visible defects. Point defects might still be present in the solid source diffused piezoresistors but they are not visible with XTEM. It is assumed th at all the defects co nsist of dislocation loops. Some loops terminate at the surface which serves a sink for the defects as they gr ow in size during inert annealing and oxidation. The locations of the defects are in the projected range, Rp, which are 0.0658 m and 0.1283 m for 20 keV boron implant in silicon and for 40 keV boron implant in 134 PAGE 135 SiO2 respectively. Since we have found defects in our ion implanted samples, we compute their defect densities using pictures taken from plan view TEM. 6.2.2 Plan View Transmissi on Electron Microscopy (PTEM) To determine the defect densities, we use PTEM since it allows a top vi ew of the defects. We compute the overall defect densities and th e surface terminated defects only for the ion implanted test structures since the solid sour ce diffused ones did not show any visible bulk defects. According to Ostwald ripening process48 smaller defects shrink in favor of larger ones during annealing. Therefore the number of defect density decreases but the dislocation loop size increases as the anneal time increases at fix te mperature. The defect density is computed by taking ten PTEM pictures of each process, counting the defects in each process and dividing by the area. Details of ion implantations and anneal ing conditions are given in Table 57 in Chapter 5. Figure 65 shows ten PTEM pictures for pr ocess 2A and Figure 66 and Figure 67 show the PTEM of the 20 keV and 40 keV impl anted test structures respectivel y. The defect densities are computed from pictures such as those shown in Figure 66 and Figure 67 and plotted as function of anneal time. Figure 68, Fi gure 610 and Figure 611 show the defects densities as a function of anneal time for the 20 keV implanted piezor esistor, 40 keV implanted piezoresistors without oxidation and 40 keV implanted piez oresistors with oxidation respectively. For all the processes as the anneal time increases the defect dens ity decreases. The surface terminated defects increase as the anneal time increases. This is because the smaller defect s disappear in favor of the larger ones and during oxidation interstitials that are injected in the silicon participate in the enlargement of the loops.48 Figure 613, Figure 614 and Figure 615 show the surface terminated defects versus the annealing time for the 20 keV implanted piezoresistor, 40 keV implanted piezoresistors without oxi dation and 40 keV implanted piezoresistors with oxidation. 135 PAGE 136 The visualization of the growth of the defects as the annea ling time increases is done by plotting the defects density versus the defect size. The de fect size is measured from the longer axis of a loop. Figure 616, Figure 617 and Figure 618 show th e Ostwald ripening process. 48 As the annealing time increases we observe that the defects are larger in size but their densities decrease. The observed defects with TEM are not the only defect s present in the bulk of the piezoresistors. There still could be point defect s not visible to TEM that can contribute to the measured noise source. Now that the bulk defe cts through XTEM and PTEM have been studied, next the defects located at the Si/SiO2 interface are investigated. 6.3 Interface Trap Density As mentioned earlier in Chapte r 4, the high frequency CV of the pMOSC is used for the computation of the interface trap density (DIT). Figure 619 shows the measured and ideal high frequency CV of wafer 2E.49 The parallel shift of the measur ed CV curve with respect to the ideal along the voltage axis indi cates the presence of charged oxide traps known as fixed oxide charges. The presence of interface traps are re vealed by the distortion of the measured CV curve with respect to the ideal curve and are successfully meas ured using the Termans method. 19 The negative gate voltage shift on Figure 619 is due to positive oxide charge.38 The high doping concentration of the test st ructures causes a high voltage for the onset of the inversion capacitance. Going through the e xperiment method described in Ch apter 4, Section 4.3 the oxide thickness and carrier concentrati on are computed. The oxide thicknesses obtained from the CV at accumulation are listed in Table 54. The energy level versus the DIT are shown in Figure 620, Figure 621, Figure 622, and Figure 623. Values of the order of 1x1012 cm2 eV1to 1x1013 cm2 eV1 extracted from our test structures indicate poor ox ide quality for all the processes. The DIT for a good quality oxide is in the order of 1x1010 cm2 eV1. Now that the defect densities are 136 PAGE 137 computed, an attempt to correlate the measured 1 /f noise voltage PSD to th e bulk defect densities measured with PTEM and interface trap densities obtained with Termans method19 is made. 6.4 Correlation of Noise Voltage PSD to Defects Since defects are the source of low frequency noise, the 1 /f noise magnitude is monitored as a function of the bulk defect and interface trap densities. The bulk defects densities were measured using PTEM and high frequency CV were used for the computation of interface trap densities. 6.4.1 Noise Voltage PSD of 20 keV Boron Implanted Piezoresistors and Defects In the analysis, it is assumed that all the bulk defects in the piezoresistors consist of dislocation loops and that all de fects are potential traps. For annealing times of 20 min, 30 min and to 50 min the bulk defect densities d ecrease as shown in Figure 68 from 6.82x108 cm2 to 5.89x108 cm2 and to 5.16x108 cm2 respectively. The measured noise voltage PSD, Figure 518, decreases as the defect density decreases with increasing annealing time. There is a correlation between the bulk defect de nsities and the measured noise voltage PSDs. The uncertainties in the defect densities ove rlap. A Monte Carlo simulation, with 100,000 iterations using the MATLAB function randn is used to fit a line and estimate the uncertainty in the variables.46 Figure 69 shows the Monte Carlo simulation of the PTEM defect density for process 2A, process 2E, and proce ss 1A. Figure 69 is plotted in the linear scale. A linear regression was performed on the data in Figure 69. The linear regression indicates a negative slope. Table 61 shows the slope of the regressi on line and the 95 % confidence intervals for the 20 keV implant. 137 PAGE 138 Figure 69 indicates a decrease of the defect density with annealing time increase although the uncertainty is large. Further measurements over a wider annealing time is recommended as future work to obtain more conclusive data. Using the Termans method,19 the interface trap densities (DIT) are computed as shown in Figure 620. The DIT of process 2E and 1A ar e shown in Figure 620. Both wafers have large DIT. At midgap the DIT are in the order of 1x1013 and 1 x1012 eV1cm2 respectively for process 2E and 1A. Here, the process with the lower DIT has the lower noise PSD as shown in Figure 518. A correlation exits between the DIT and the 1 /f noise. The nonuniform doping profiles show surface concentrations 1.80x1019 and 1.78x1019 cm3 of process 2E and 1A are respectively. The peak concentration is not at th e surface and piezoresistors are not field devices, therefore the carriers will be affected by bulk defects located at the peak concentrations. 6.4.2 Noise Voltage PSD of 40 keV Boron Impl anted Piezoresistors through 0.1 m of SiO2 and Defects The bulk defects in the piezoresistor s implanted with boron, 40 keV, 7x1014 cm2, through 0.1 m of SiO2 are of the same type as those for the wafers implanted with boron, 20 keV, 7x1014 cm2, 7o tilt. As the annealing increases, the defect density decreases as shown in Figure 610 and Figure 611. Monte Carlo simulations, with 100,000 iterati ons using the MATLAB function randn are used to fit lines and estimate the uncer tainties in the variab les in Figure 610 and Figure 611.46 The linear regressions indicate negative slopes. Table 61 shows the slopes of the regression lines and the 95 % confidence intervals for the 40 keV implants. However, the noise voltage PSD decreases as the defect density decr eases for only the two processes with only inert anneal process 2B and process 5A, as shown in Figure 521 and Figure 610. In this case, there is a correlation between the measured defect densities and 1 /f noise. For 138 PAGE 139 the processes with oxidation, pr ocess 3E and process 4A, the noi se voltage PSDs do not decrease as the bulk defect density decreases as shown in Figure 522 and Figure 611. To explain this trend, we measure the line le ngth, the loop area, and the area of the faulted loops for process 3E (10 min in N2 and 5 min dry, 5 min wet a nd 10 min dry oxidation at 900 C) and process 4A (30 min in N2 and 5 min dry, 5 min wet and 10 min dry oxidation at 900 C). The measurements are conducted on only the readily observed loops. Figur e 612 shows PTEM of process 3E and process 4A. The line length is the total perimete r of the loops in three PTEM images. For the round loops, the perimeter is approximated by using D for the nonsurface terminated round defects, 2 D for the surface terminated round defects, and for the elongated defects. is the longest axis for a round loops, and is the length of the elongated defects. The loop area is the to tal area of the loops in three P TEM images. For the round loops, the area is approximated by using 2 lDl 22D for the nonsurface terminated round defects and 22 D 2 for the surface terminated round def ects. The elongated defects are not included in the loop area computation. The faulted loop area is the to tal area of the loops in three PTEM images for only the faulted nonsurface terminated and surface terminated round defects. The equations used for the faulted loop areas are identical to those of the loop areas discu ssed above. Table 62 shows the computed line lengths, loop areas, and faulted lo op areas of the B 20 keV and 40 keV with inert anneal and oxidization. In Tabl e 62, as the annealing time in creases from 30 min to 50 min at 900 C, the line lengths decrease for both the B 20 keV and B 40 keV. However, the loop areas and the faulted loop areas increase The PTEM show that the 1 /f noise PSDs track the bulk defect densities except for process 3E and 4A. In these samples implanted with B 40 keV with 139 PAGE 140 inert anneal and oxidation, th e PSDs appear to track the fa ulted loop areas. Extensive measurements over a wider range of process conditions are recommended for future work. Termans method19 was used to measure the interface trap densities (DIT) in the piezoresistors. The interface trap densities for the 40 keV implants are shown in Figure 621 and Figure 622. The processes with only inert anneal after the implant, 2B and 5A, have DIT of the same order as shown in Figure 621. In additi on, their junction are abou t the same, Table 52, therefore these two processes are equally affected by the interface tr aps. However, for processes 3E and 4A, with inert anneal and oxidation after the implant the interface tr ap densities are lower for the process with long er annealing as shown in Figure 622. The 1 /f noise is however larger for the device with lower DIT and lower bulk defects. The results from processes 3E and 4A suggest that bulk 1 /f noise is the dominant source for the 1 /f noise in these piezoresistors and that the PSDs appear to track the faulted loop areas. 6.4.3 Noise Voltage PSD of Solid Source Di ffused Piezoresistors and Interface Traps The interface trap densities for the solid sour ce diffused piezoresistors C1 and C2 are of same magnitude as shown in Figure 623. Howe ver the noise voltage PSD of C2 is much less than that of C1. This could be due to the fact the phosphorus diffused after the boron diffusion for process C2 reduces the intera ction of the holes with the inte rface traps. Therefore, the less the interaction of the car riers with the interface traps th e less is the 1 /f noise. 6.5 Summary XTEM, PTEM pictures and the HFCV CV m easurements were used to visualize and compute the bulk and surface defect densities in the piezoresistors. Measurement results show that as the annealing time increases, the bulk defect density decrea ses for all implanted samples. This reduction in bulk defect dens ities is correlated to the decrease of the noise voltage PSDs of the 20 keV implanted piezoresistors and of the 40 keV implanted piezoresistors with only inert 140 PAGE 141 anneal. However, a possible li nk between the defects and the noise voltage PSDs for the 40 keV implanted piezoresistors with inert anneal and oxidation is the faulted loop areas. For the solid source diffused piezoresistors, the process with phosphorous solid source diffusion in addition to the boron so lid source diffusion has lower 1 /f noise. This suggests that the phosphorous cause a reduction of the interac tion of the hole with th e surface traps. The interface traps decrease for th e 20 keV implanted piezoresistors and the 40 keV implanted piezoresistors with inert anneal and oxidation as the annealing time increases. However, the DIT is of the same magnitude for the 40 keV implan ted piezoresistors with only inert and the solid source diffused piezoresistors. The bulk defects are the dominant noise source of the piezoresistors. During devices operation the current flows in the bulk which has high defect concentrations. 141 PAGE 142 Table 61. Slopes of re gression lines and the 95 % confidence intervals. Process Slope 95 % confid ence interval in slope 20 keV 8.80x104 [3.24x105 1.48x105] 40 keV with inert only 8.07x104 [2.26x105 0.65x105] 40 keV with inert and oxidation 1.23x105 [4.43x105 1.96x105] Table 62. Line length, loop area, and faulted loop area of th e B 20 keV and 40 keV with inert anneal and oxidation. Implant and annealing Line length (cm/cm2) Loop area (cm2/cm2) Faulted loop area (cm2/cm2) B, 20 keV, 7x1014 cm2, 7o tilt 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (2E) 1.73x104 3.39x102 1.83x102 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (1A) 1.63x104 4.09x102 2.13x102 B, 40 keV, 7x1014 cm2through 0.1 m of SiO2 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (3E) 1.94x104 4.39x102 2.52x102 30 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C (4A) 1.93x104 6.64x102 4.70x102 Figure 61. Focus ion beam (FIB) on a piezoresistor test structure. 142 PAGE 143 Figure 62. The XTEM of piezoresi stor implanted with B, 20 keV, 7x1014 cm2 of generation 2 process, A) 2A, B) 2E, C) 1A. Figure 63. XTEM of piezo resistor generation 2 implanted with B, 40 keV, 7x1014 cm2 through 0.1 m of SiO2 of generation 2 process, A) 2B, B) 3E, C) 4A), D) 5A. 143 PAGE 144 Figure 64. The XTEM of piezoresistor A) solid sour ce diffusions of B, 25 min, 950 C, B) solid source diffusions of B, 25 min, 950 C and P, 5 min, 800 C of generation 2 process. Figure 65. Ten PTEM pi ctures for process 2A of generatio n 2 process, implanted with B, 20 keV, 7x1014 cm2 and annealed for 5 min dry, 5 min wet and 10 min dry at 900 C. 144 PAGE 145 Figure 66. PTEM of the 20 keV implanted test structur es A) 2A, B) 2E, C) 1A. Figure 67. PTEM of the 40 ke V implanted test structures A) 2B, B) 3E, C) 4A, D) 5A. 145 PAGE 146 103 10 4 108 109 Annealing time (sec)Defect density (cm2) B, 20keV, 7x1014 cm2, 70 tilt2a (5 min dry, 5 min wet and 10 min dry oxide at 900 C) 2e (10 min in N2 followed by 5 min dry, 5 min wet and 10 min dry oxide at 900 C) 1a (30 min in N2 followed by 5 min dry, 5 min wet and 10 min dry oxide at 900 C) 2e 1a 2a Figure 68. Defects densities as a function of anneal time of the 20 keV implanted t est structures of generation 2 process. 1000 1500 2000 2500 3000 3500 4 4.5 5 5.5 6 6.5 7 7.5 8 x 108 Anneal time ( sec ) Defect density (cm2) Fitted line Figure 69. Regression line of the defect density versus annealing time for the B 20 keV. 146 PAGE 147 102 103 104 108 109 1010 Annealing time (sec)Defect density (cm2) B, 40keV, 7x1014 cm2 throught 0.1 m of SiO22b (10 min in N2 at 900 C) 5a (90 min in N2 at 900 C) 2b 5a Figure 610. Defects densities as a function of anneal time of the 40 keV implanted test structures with only inert anneal of generation 2 process. 103 104 108 109 Annealing time (sec)Defect density (cm2) B, 40keV, 7x1014 cm2 throught 0.1 m of SiO23e (10 min in N2 followed by 5 min dry, 5 min wet and 10 min dry oxide at 900 C) 4a (30 min in N2 followed by 5 min dry, 5 min wet and 10 min dry oxide at 900 C) 3e 4a Figure 611. Defects densities as a function of anneal time of the 40 keV implanted test structures with inert anneal and oxidation of generation 2 process. 147 PAGE 148 Figure 612. PTEM of processes 40 keV, 7x1014 cm2, through 0.1 m of SiO2., A) 3E (10 min in N2 and 5 min dry, 5 min wet and 10 min dry oxidation at 900 C) and B) 4A (30 min in N2 and 5 min dry, 5 min wet a nd 10 min dry oxidation at 900 C). 103 104 107 108 109 Annealing time (sec)Surface terminated defects (cm2) B, 20keV, 7x1014 cm2, 70 tilt2a (5 min dry, 5 min wet and 10 min dry oxide at 900 C) 2e (10 min in N2 followed by 5 min dry, 5 min wet and 10 min dry oxide at 900 C) 1a (30 min in N2 followed by 5 min dry, 5 min wet and 10 min dry oxide at 900 C) 2a 2e 1a Figure 613. Surface terminated defects versus the annealing time of the 20 keV implanted test structures of generation 2 process. 148 PAGE 149 102 103 104 107 108 109 Annealing time (sec)Surface terminated defects (cm2) B, 40keV, 7x1014 cm2 throught 0.1 m of SiO22b (10 min in N2 at 900 C) 5a (90 min in N2 at 900 C) Figure 614. Surface terminated defects versus the annealing time of the 40 keV implanted test structures with only inert anneal of generation 2 process. 103 10 4 107 108 109 Annealing time (sec)Surface terminated defects (cm2) B, 40keV, 7x1014 cm2 throught 0.1 m of SiO23e (10 min in N2 followed by 5 min dry, 5 min wet and 10 min dry oxide at 900 C) 4a (30 min in N2 followed by 5 min dry, 5 min wet and 10 min dry oxide at 900 C) 3e 4a Figure 615. Surface terminated defects versus the annealing time of the 40 keV implanted test structures with inert anneal and oxidation of generation 2 process. 149 PAGE 150 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 5 10 15 x 107 B, 20keV, 7x1014 cm2, 70 tilt2A Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 5 10 15 x 107 Defect density (cm2) B, 20keV, 7x1014 cm2, 70 tilt2E Inert (10 min at 900 C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) 0 0.1 0.2 0.3 0.4 0.5 0.6 15 x 1070.7 0 5 B, 20keV, 7x1014 cm2, 70 tilt10 1A Inert (30 min at 900 C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) Defect size (m)Figure 616. Defects count versus loop size of the 20 ke V implanted test stru ctures of generation 2 process. 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.5 1 1.5 2 2.5 3 x 108 B, 40keV, 7x1014 cm2 through 0.1 m of SiO22B Inert (10 min at 900 C) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.5 1 1.5 2 2.5 3 x 108 Defect size (m)Defect density (cm2) B, 40keV, 7x1014 cm2 through 0.1 m of SiO25A Inert (90 min at 900 C) Figure 617. Defects count vers us loop size of the 40 keV implanted test st ructures with only inert anneal of ge neration 2 process. 150 PAGE 151 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 5 10 15 x 107 B, 40keV, 7x1014 cm2 through 0.1 m of SiO23E Inert (10 min at 900 C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 5 10 15 x 107 Defect size (m)Defect density (cm2) B, 40keV, 7x1014 cm2 through 0.1 m of SiO24A Inert (90 min at 900 C) Oxidation (5 min dry, 5 min wet and 10 min dry oxide at 900 C) Figure 618. Defects count versus loop size of the 40 keV implanted test structures with inert anneal and oxidation of generation 2 process. 60 40 20 0 20 40 60 530 535 540 545 550 555 560 VG (volts)Capacitance (pF) Ideal Experimental 2E Figure 619. Measured and idea l high frequency CV of process 2E, implanted with B, 20 keV, 7x1014 cm2 and annealed for 10 min N2 and 5 min dry, 5 min wet and 10 min dry oxide at 900 C, of generation 2 process. 151 PAGE 152 0.6 0.4 0.2 0 0.2 0.4 0.6 1012 1013 1014 S B (eV)DIT (eV1 cm2) B, 20keV, 7x1014 cm2, 7o tilt 2E Inert anneal (10 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) 1A Inert anneal (30 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) Figure 620. Energy level versus the DIT of the 20 keV implanted test structures. of generation 2 process. 0.6 0.4 0.2 0 0.2 0.4 0.6 1012 1013 1014 S B (eV)DIT (eV1 cm2) B, 40keV, 7x1014 cm2, through 0.1 m of SiO22B Inert anneal (10 min at 900 C) 5A Inert anneal (90 min at 900 C) Figure 621. Energy level versus the DIT of the 40 keV implanted test structures with only inert anneal of generation 2 process. 152 PAGE 153 0.6 0.4 0.2 0 0.2 0.4 0.6 1012 1013 1014 S B (eV)DIT (eV1 cm2) B, 40keV, 7x1014 cm2, through 0.1 m of SiO23E Inert anneal (10 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) 4A Inert anneal (30 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) Figure 622. Energy level versus the DIT of th e 40 keV implanted test structures with inert anneal and oxidation of generation 2 process. 0.6 0.4 0.2 0 0.2 0.4 0.6 1012 1013 1014 S B (eV)DIT (eV1 cm2)C1 Solid source diffusion 1) B, 25 min at 950 C C2 Solid source diffusions 1) B, 25 min at 950 C and 2) P, 5 min at 800 C C1 and C2 Inert anneal (30 min at 900 C) Oxidation (5 min dry, 5 min wet, 10 min dry at 900 C) Figure 623. Energy level versus the DIT of the solid source diffused test structures of generation 2 process. 153 PAGE 154 CHAPTER 7 CONCLUSION AND FUTURE WORK The noise performance of piezoresistive MEMS transducers defi ned as the minimum detectable signal depends on both the sensitivity and output referre d noise. It has been observed that identical sensors fabricated with different fa brication processes exhibit very different noise. Hence, the fabrication process can have a large effect on the intrinsic noise mechanisms, in particular the 1 /f noise which is related to electronically active defects or tr aps. The geometry and process dependence of 1 /f noise in ptype piezoresistors was systematically investigated in this work. Ptype piezoresistors were fabric ated with 20 keV and 40keV boron implants, with implant oxide for the 40keV case, and solidsour ce diffusion and varying isochronal 900C inert anneals on teststructures of different surface area and volume. The devices were characterized electrically using IV, CV, and power spectral density noise m easurements. The defects were visualized using crosssection a nd plane view TEM. In addition, the influence of carrier number on piezoresistors 1 /f noise was investigated. In genera l, the results show that lower 1/f noise can be achieved by increased carrier number and longer inert anneal time. For the first time, the measured 1 /f noise in piezoresistors is systematically co mpared to bulk defect densities measured with TEM and interface trap de nsities from HFCV after each annealing condition of the piezoresistors. For ptype piezoresistors impl anted with 20 keV boron at 7x1014 cm3 dose and isothermally annealed at 900C for varying times in inert N2 followed by a short dry/wet/dry oxidation at the same temperature, increasi ng inert anneals result ed in decreasing 1 /f noise as well as bulk defect densities measured by PTEM. DIT measured by HFCV also indicated decreasing interface trap density for the 20 keV boron samples with increasing inert anneal and constant dry/wet/dry oxidation at 900C. 154 PAGE 155 For the 40 keV implant through 0.1 m oxide, th e noise in samples th at underwent only increased inert anneal showed a correlation between lower 1 /f noise and lower bulk defect density with longer anneal time. However, 40 keV samples with inert anneal and additional dry/wet/dry oxidation showed increased 1 /f noise with increased 900C inert anneal (10 min versus 30 min) but decreased bulk trap density. In both cases, the interface traps density measured by HFCV decreased slightly or remained unchanged. Upon further inspection, it was found that for the two processes implanted with B 40 keV and s ubjected to inert anneal and oxidation, the PSDs appear to track the faulted loop areas. Additional measurements over a wider range of process c onditions are recommended. In contrast to the implanted samples, the solidsource diffused ptype resistor exhibited no bulk defects observable by TEM. A phosphorous counterdoped so lidsource diffused ptype piezoresistor had less noise than the borononly solidsource diffused piezoresistor which is attributed to the boron centroid further from the Si/SiO2 interface. In bulk piezores istors, the 1 /f noise appears to be more strongly affected by the bulk defect density than the surface trap densit y which is expected since current density profile is distributed and centered at the region of hi ghest conductivity. When the bulk defect density is low, then surface trap effects on the 1 /f noise become significant. From the noise performance of the implanted and diffused piezoresistor s, the reduction of the 1 /f noise can be achieved using boron solid source diffusion and counter phosphorous solid source diffusion. When solid source diffusion is used, defects in the silicon caused by ion implantation are avoided. Furthermore, the in teraction of carriers with the interface trap densities is limited by the presence of phosphorous at the surface of the silicon by shifting the hole centroid away from the Si/SiO2 interface. Other important parameters for better noise 155 PAGE 156 performance are good oxide quality and large carri er number. The less the interface traps the less the trapping and detrapping of carriers at the in terface. The larger the nu mber of carriers, the lower the 1 /f noise as illustrated by th e Hooge formulation of the low frequency noise which shows an inverse proportionality between the low frequency noise and the number of carriers. The distribution of the trap en ergy levels and their capture cr oss sections and the defect concentrations in the piezoresistors using d eep level transient spectroscopy and isothermal transient capacitance C(t,T) 50, 51, 52 are worth investigating. In addition to boron implant, the correlation of 1 /f noise to defects can be studied in preamorphized a nd low energy ion implanted piezoresistors with BF2 followed by rapid thermal annealing. This study would help analyze and correlate the 1 /f noise to defects in piezoresistors with shallower junctions a nd higher electrical active carrier concentrations. 156 PAGE 157 APPENDIX A PIEZORESISTIVITY Crystalline silicon has three fundamental piezoresistive coefficients (11, 12, and 44). The piezoresistance coefficient matrix of silicon is shown in Equation A1.53 11 111212 22 121112 33 121211 41 44 52 44 63 44000 000 000 1 00000 00000 00000 ) (A1) where 1=xx, 2=yy, and 3=zz are the normal stresses, and 1=yz, 2=xz, and 3=xy are the shear stresses. Smith53 provided the piezoresis tance coefficients for ntype and ptype silicon at a specific given resistivity are shown in Table A1. The piezoresistance coefficient magnitude changes with orientation. Kanda54 has provided a way to co mpute the piezoresistance coefficient for different orientations. When the a pplied stress is perpendicular or parallel to the electric field, the piezoresistance coefficient is decomposed respectively into a transverse piezoresistive, t, and a longitudinal piezoresistive coefficient, l as illustrated in Equation A2 in terms of the piezoresistance coefficients 11, 12, 44, and the direction cosines (l,m)54 (A2) 222222 12441211121212 222222 11441211111111() ( 2( )( )l tllmmnn lmlnmn Using the piezoresistive coeffi cients values of silicon (11, 12, and 44) of Table A1, one obtains the polar plots of the l ongitudinal A) and transverse B) piezoresistance coefficients for ptype (100) silicon as shown in Figure A1. 157 PAGE 158 In Figure A1, the piezoresistance coefficients are larger in the <110> direc tion. In addition, we notice that the transverse piezo resistance coefficients are appr oximately equal but have opposite sign compared to the longitudinal piezoresistance co efficient. To take advantage of the equality in magnitude and difference in sign, in the desi gn of piezoresistive micr ophone, researchers such as Saini55 orient the piezoresistors in such directions in a Wheatstone bridge configuration. Table A2 provides the transverse and longitudinal piezoresistan ce coefficients of silicon along the <110> direction on a (100) wafer for room te mperature and lowly doped silicon. In Table A2 above, for <110> ptype silicon, the l is has opposite sign but has almost the same magnitude as t. However, his is not the case for the ntype silicon where l and t have not only the same sign but also they differ in magnitudes. Th e piezoresistance coefficients are inversely proportional to the doping concentration. Equation A1 shows that as the doping concentration increases, the resistivity decrea ses, thus a decrease in the resi stance. The dependence of the piezoresistive coefficients on doping concentration and temperature using FermiDirac statistics have been studied by Kanda.54 However, at high doping con centration, Kandas theoretical prediction of the piezoresistance coefficients is di fferent from more recent studies by Harley and Kenny.12 By fitting data from Manson et al.,56 Tufte and Stetzer,57 and Kerr and Milnes,58 Harley and Kenny12 show that at high doping concentrati on one can approximate the decrease of the piezoresistance coefficient by a straight line. 158 PAGE 159 Table A1. Piezoresistive coefficients of silicon. Silicon ( cm) 11 (1011 Pa1) 12 (1011 Pa1) 44 (1011 Pa1) ptype 7.8 6.6 1.1 138.1 ntype 11.7 102.2 53.4 13.6 Figure A1. Polar plots of longitudinal A) and transverse B) pi ezoresistance coefficients for ptype (100) silicon. Table A2. Transverse and l ongitudinal piezoresistance coeffi cients of silicon for <110> direction Silicon l (1011 Pa1) t (1011 Pa1) ptype 71.8 66.3 ntype 31.2 17.6 159 PAGE 160 APPENDIX B MEMS PIEZORESISTIVE MICRO PHONE VOLTAGE OUTPUT When pressure or force is applied to the microphones membrane, it induces stress resulting in strain on the membrane. The stress and strain have an impact on the piezoresistors located at the edge of the membrane where the stress is maximum. Strain is the change per unit length of the piezoresistors and is ex pressed as shown in Equation B1. L L (B1) where L is the change in the original length and L is the original length of the resistor. The expression of the strain sensitiv ity, also known as gauge factor G0, is shown in Equation B2. 0 0 R R G (B2) where R is the chance of resistance R and is the strain. The resistance of a semiconductor resi stor is given in Equation B3. l R wt (B3) where is the resistivity, and l w and t are respectively the length width and thickness of the resistor. The expression R R is obtained by differentiating Equation B3 and dividing the resulting expression by the resistance R as illustrated in Equation B4. R lw t R lwt (B4) Using the Poissons ratio, the strain sensitivity G becomes 160 PAGE 161 12R R G (B5) In Equation B5, 12 is due to the geometry change and is due to the piezoresistive effect. For metal, the piezoresist ive effect is negligible and th erefore the gauge factor can be expressed in term of its geometrical change only as shown in Equation B6. 12 R R G (B6) Since is less than 0.5, G for metal is about two. For semiconductor, the gauge factor, G, is dominated by the piezoresistive effect and can have a magnitude in the range of 100. The expression of sensor output voltage outV given in Equation B7 describes a linear relation between the input pressure on the membrane of the microphone and the output voltage of the Wheatstone bridge configuration. 0out biasVGV (B7) Using Equation B6, we express the bridge output voltage Vout in terms of the change in resistance R the resistance R and the bias voltage Vbias. out biasR VV R (B8) Hence with application of an external bias the piezoresist ive microphone provides a linear output voltage related with resistance change. If a mechanical tran sfer function relating R to pressure is linear, then a linear acoustic transducer is achieved. 161 PAGE 162 APPENDIX C DIFFRENCE BETWEEN HOOGE AND MCWHORTER 1/F NOISE MODEL The difference between 1/f noise proposed by Hooge6 and McWhorter7 is illustrated via the resistance fluctuations in a ptype resistor. Hooge6 gives a spectral po wer density of the fluctuation in the resistance R as shown in Equation C1, 2RS R Nf (C1) where is the noise power spectral density, is a dimensionless parameter, f is the frequency, and N is the number of carriers. RSIn a linear system, Ohms Law,* VRI holds and one can extend Equation C1 to Equation C2 shown below 222V RIS SS R VINf (C2) In a ptype resistor (p>>n) with length l, width w and thickness t, the resistance R is l R wt (C3) Here the resistivity of a ptype resistor is expressed as 111ppqp where is the conductivity, q is the charge of the carrier, p is the hole mobility, and is the hole concentration. Thus, Equation C3 can be expressed in terms of mobility and hole concentration as shown in Equation C4. p pl R qwtp (C4) 162 PAGE 163 Fluctuations in R is expressed in Equation C5. 22 p p p pp p pRR Rp p ll p qwtpqwtp RR p p and p p R p R p (C5) where p is the fluctuation in mobility and p is the fluctuation in the carrier concentration. It is seen that fluctuations in R may be caused by fluctuations in p, p or both under bias conditions. The fluctuations in mobility can be explained as follows. The time interval between two successive hole collisions is called the relaxation time or mean free transit time and is denoted by This relaxation time is determined by la ttice and impurity scattering. The mobility p is related to the relaxation time as described in Equation C6. p pq m (C6) where mp is the hole effective mass, q is the charge of the carrier, and < >is the average relaxation time. Therefore, fluctuations in < > induce fluctuations in p as shown in Equation C7. p pq m (C7) 163 PAGE 164 Under applied voltage bias, carriers drift in the resulting electric field giving rise to a current I. This current is related to the mobility as shown in Equation C8 for a ptype semiconductor resistor. driftpp I qpA (C8) where is the electric field, and A is the crosssectional area of the resistor. Thus, from Equation C8, one sees that fluctuations in the current driftp I are induced by fluctuations in the mobilityp which is in turn related to fluctuations in the relaxation time as shown in Equation C7. These time dependent fluctuations give rise to 1/f noise. 164 PAGE 165 APPENDIX D PROCESS FLOW D.1 Generation 1 Process 1. Start with bulk wafer (nSi, 4 in, CZ <100>, 25 cm, 500550 m), single side polished, NB =1x1015cm3. RCA clean. 2. Grow thick isolation mask SiO2. 3. Lithography for implant mask. nSi SiO2 Resist 4. Etch oxide 5. Photo resist strip 165 PAGE 166 6. Ion implantation Table D1. Implant conditi on of process generation 1. Species B Isotope 11 Dose (ions/cm2) 6x1014 Energy (keV) 5 Tilt angle (degree) 7 Substrate temperature (C) 25 7. RCA wafer clean 8. Inert anneal and oxidation a. Inert Anneal in N2 (300 min, 1050 C) b. Grow of thermal SiO2 (dry 65 min, wet 21 min, dry 65 min at 950 C) 9. Lithography for contact hole 10. Etch oxide 166 PAGE 167 11. Photo resist strip 12. Front side metallization on top waferpolished surface 13. Lithography for metal bond pad 14. Metal etch and photo resist strip 15. Back side metallization on bo ttom of waferunpolished surface. 16. Photoresist strip 17. Nitride passivati on deposition (PECVD) and patterning 18. Post metallization anneal (forming gas 96% N2, 4% H2) 167 PAGE 168 19. Wafer dicing 20. Packaging 168 PAGE 169 D.2 Generation 2 Process 1. RCA of wafers (nSi, 4 in, CZ <100>, 0.51 cm, 525 25 m) single side polished. (UF) 2. Grow thick isolation mask dry/wet/dry SiO2 (70/23/70 min at 1100 C) and spin resist. (UF) 3. Lithography for a) channel implant or b) channel solidsou rce predep (UF) Ntype Si SiO2 Resist 4. Etch dry/wet/dry oxide where channel a) impl ant or b) solidsource predep is to be performed. (UF) Ntype Si SiO2 Resist 169 PAGE 170 5. Photoresist strip. (UF) Ntype Si SiO2 6. RCA clean (UF) 7. Growth thin dry/wet/dry SiO2 and lithography for channel implant with mask 2 (dark field). Ntype Si SiO2 Implant oxide 8. Ion implantation a) B 20keV, etch the dry oxide and leav e the resist which serves as mask during the implant. 170 PAGE 171 b) B 40keV, leave the resist which serv es as mask during the implant. c) B or P solid source diffusion 9. Photoresist strip and RCA wa fer organic clean (SC1) 10. Inert anneal in N2 and dry/wet/dry SiO2 of wafers a) B, 20 keV, 7x1014 cm2 directly into the silicon Table D.2.1 B, 20 keV, 7x1014 cm2 7 tilt implanted directly into silicon. Process Implant Anneal in N2 Dry/wet/dry Oxide 120keVDt B, 20 keV, 7x1014 cm2 7 tilt NA 5/5/10 min at 900 C 220keVDt B, 20 keV, 7x1014 cm2 7 tilt 10 min, 900 C 5/5/10 min at 900 C 320keVDt B, 20 keV, 7x1014 cm2 7 tilt 30 min, 900 C 5/5/10 min at 900 C 171 PAGE 172 b) B, 40 keV, 7x1014 cm2 through SiO2 Table D.2.2 B, 40 keV, 7x1014 cm2 implanted through oxide. Process Implant Anneal in N2 Dry/wet/dry Oxide 140keVDt B, 40 keV, 7x1014 cm2 10 min, 900 C NA 240keVDt B, 40 keV, 7x1014 cm2 10 min, 900 C 5/5/10 min at 900 C 340keVDt B, 40 keV, 7x1014 cm2 30 min, 900 C 5/5/10 min at 900 C 440keVDt B, 40 keV, 7x1014 cm2 90 min, 900 C 5/5/10 min at 900 C c) Solid source diffusion annealing Table D.2.3 Inert anneal in N2 and dry/wet/dry SiO2 of wafers for constant source diffusion. Process name Anneal in N2 Dry/wet/dry oxide (0.0205 m) C1 and C2 30 min, 900 C 5/5/10 min at 900 C 11. Lithography for contact holes with mask 3 (dark field). This appl ies to wafers with and without thin oxide implant masks. Ntype Si SiO2 Implant oxide Boron 12. Etch oxide for contact holes Ntype Si SiO2 Implant oxide Boron 172 PAGE 173 13. Photoresist strip and front side metallization on top wafe rpolished surface Ntype Si SiO2 Implant oxide Boron Metal 14. Lithography for metal with mask 4 (clear field), metal etch and photo resist strip 15. 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After fi nishing high school in 1995, he received the Associate of Arts certificate from Tallahasse e Community College in December 1998. He graduated with a bachelors degr ee in electrical engineering from the University of Florida in December 2001 and received a Master of Science in electrical engineering fr om the University of Florida in spring 2005 under the guidance of Dr. Toshikazu Nishida. He began pursuing a doctorate concentrating in the i nvestigation of noise in piezore sistors, in the summer 2005. 180 