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Receivers Using Schottky Barrier Diodes in CMOS

Permanent Link: http://ufdc.ufl.edu/UFE0022002/00001

Material Information

Title: Receivers Using Schottky Barrier Diodes in CMOS
Physical Description: 1 online resource (133 p.)
Language: english
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2008

Subjects

Subjects / Keywords: am, cdma, cmos, detector, fdma, receiver, rectifier, rf, schottky, ultrawideband
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: With the rapid expansion of the market for low-cost communication devices, Complementary Metal Oxide Semiconductor (CMOS) Integrated circuits technology has emerged as the technology of choice and is envisaged to remain as such. The ultimate goal has been to integrate all functionalities on one die thereby reducing the form factor, minimizing the cost, and simplifying use. This dissertation presents and demonstrates the concept for efficiently providing the additional utility of signal rectification and detection in CMOS that could be used for radio frequency (RF) signal demodulation and on-chip testing. Rectification of amplitude modulated (AM) signal at RF requires high-speed devices that have close to exponential transfer characteristics (current-voltage, I-V). Schottky Barrier diodes (SBDs), fabricated without any changes to the mainstream CMOS process flow provide 100% improvement in the conversion gain over MOS transistors for detection circuits. The requirement for not making modifications is critical towards reducing the chip manufacturing cost. The SBDs fabricated in a 130-nm CMOS process have close to ideal exponential I-V characteristics and have cut-off frequencies well over a THz. It may be possible to open up the market for RF as well as sub-millimeter wave applications using these diodes. Experimental study into the layout of these devices indicates that it is possible to engineer these diodes for use in detectors with over 30 GHz bandwidth while maintaining comparable cutoff frequency. Also, instead of using an oxide ring, by using a polysilicon gate layer to isolate the Schottky and well contacts, the cutoff frequency can be increased beyond 2 THz. The utility of these diodes is demonstrated by implementing a detector suitable for pulse-based ultra-wideband (UWB) applications. The detector is capable of operating in the UWB range of 3.1 ? 10.6 GHz with ~-56 dBm sensitivity for 100 Mbps data rate and 1-GHz pulse width. Using a detector based scheme eliminates the need for a PLL, mixer and its drivers thereby drastically reducing the power consumption. The power consumption is only 8.5 mW. Wireless interconnects capable of replacing opto-couplers currently used on a hybrid engine controller board are presented. The wireless interconnects provide higher data rates and the same functionality as opto-couplers while reducing the cost and footprint. However, the control board with lots of metal traces and components is expected to be a harsh environment for wireless communication. The system uses code division multiple access (CDMA) on the down link and frequency division multiple access (FDMA) on the up link. The CDMA receiver uses a SBD based detector for down-conversion at frequencies ranging from 15-20 GHz. A prototype of SBD detection based CDMA receiver is implemented in a 130-nm CMOS foundry process and used to demonstrate a wireless link in the hybrid motor controller board. The receiver reconstructs the clock from the incoming signal thereby eliminating the need for an external frequency reference. The receiver has 35-dB peak gain and operates optimally between 14-16 GHz. The sensitivity for an Eb/No of 14 dB and 400-Mbps data rate is -58 dBm and the noise figure (NF) is 20 dB. The power consumption is ~ 60 mW and the receiver occupies ~2.1 mm2 of area. Successful reception and de-modulation of an AM signal transmitted 15 cm away, using the receiver, indicates the feasibility of wireless communication within the control board.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Thesis: Thesis (Ph.D.)--University of Florida, 2008.
Local: Adviser: O, Kenneth K.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2009-05-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2008
System ID: UFE0022002:00001

Permanent Link: http://ufdc.ufl.edu/UFE0022002/00001

Material Information

Title: Receivers Using Schottky Barrier Diodes in CMOS
Physical Description: 1 online resource (133 p.)
Language: english
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2008

Subjects

Subjects / Keywords: am, cdma, cmos, detector, fdma, receiver, rectifier, rf, schottky, ultrawideband
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: With the rapid expansion of the market for low-cost communication devices, Complementary Metal Oxide Semiconductor (CMOS) Integrated circuits technology has emerged as the technology of choice and is envisaged to remain as such. The ultimate goal has been to integrate all functionalities on one die thereby reducing the form factor, minimizing the cost, and simplifying use. This dissertation presents and demonstrates the concept for efficiently providing the additional utility of signal rectification and detection in CMOS that could be used for radio frequency (RF) signal demodulation and on-chip testing. Rectification of amplitude modulated (AM) signal at RF requires high-speed devices that have close to exponential transfer characteristics (current-voltage, I-V). Schottky Barrier diodes (SBDs), fabricated without any changes to the mainstream CMOS process flow provide 100% improvement in the conversion gain over MOS transistors for detection circuits. The requirement for not making modifications is critical towards reducing the chip manufacturing cost. The SBDs fabricated in a 130-nm CMOS process have close to ideal exponential I-V characteristics and have cut-off frequencies well over a THz. It may be possible to open up the market for RF as well as sub-millimeter wave applications using these diodes. Experimental study into the layout of these devices indicates that it is possible to engineer these diodes for use in detectors with over 30 GHz bandwidth while maintaining comparable cutoff frequency. Also, instead of using an oxide ring, by using a polysilicon gate layer to isolate the Schottky and well contacts, the cutoff frequency can be increased beyond 2 THz. The utility of these diodes is demonstrated by implementing a detector suitable for pulse-based ultra-wideband (UWB) applications. The detector is capable of operating in the UWB range of 3.1 ? 10.6 GHz with ~-56 dBm sensitivity for 100 Mbps data rate and 1-GHz pulse width. Using a detector based scheme eliminates the need for a PLL, mixer and its drivers thereby drastically reducing the power consumption. The power consumption is only 8.5 mW. Wireless interconnects capable of replacing opto-couplers currently used on a hybrid engine controller board are presented. The wireless interconnects provide higher data rates and the same functionality as opto-couplers while reducing the cost and footprint. However, the control board with lots of metal traces and components is expected to be a harsh environment for wireless communication. The system uses code division multiple access (CDMA) on the down link and frequency division multiple access (FDMA) on the up link. The CDMA receiver uses a SBD based detector for down-conversion at frequencies ranging from 15-20 GHz. A prototype of SBD detection based CDMA receiver is implemented in a 130-nm CMOS foundry process and used to demonstrate a wireless link in the hybrid motor controller board. The receiver reconstructs the clock from the incoming signal thereby eliminating the need for an external frequency reference. The receiver has 35-dB peak gain and operates optimally between 14-16 GHz. The sensitivity for an Eb/No of 14 dB and 400-Mbps data rate is -58 dBm and the noise figure (NF) is 20 dB. The power consumption is ~ 60 mW and the receiver occupies ~2.1 mm2 of area. Successful reception and de-modulation of an AM signal transmitted 15 cm away, using the receiver, indicates the feasibility of wireless communication within the control board.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Thesis: Thesis (Ph.D.)--University of Florida, 2008.
Local: Adviser: O, Kenneth K.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2009-05-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2008
System ID: UFE0022002:00001


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1 RECEIVERS USING SCHOTTKY BARRIER DIODES IN CMOS By SWAMINATHAN SANKARAN A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2008

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2 2008 Swaminathan Sankaran

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3 To my Amma and Appa

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4 ACKNOWLEDGMENTS I would like to begin by thanking my Goddess and spiritual Guru for being my sources of strength and hope. I offer my success and humble prayers to them. It is my conviction that through them, I have gotten the companionship of my advisor, Professor Kenneth O, whose constant support, encouragement, guidance, and friendship have been invaluable. My admiration and respect for him are unbound for the commitme nt and passion he has exuded towards my research. I deeply appreciate the time commitment of Professors Jenshan Lin, Rizwan Bashirullah and Peng Jiang for serving in my committ ee and showing interest in this work. I am fortunate to have worked with my colleagues Yu Su, Chikuang Yu, Ning Zhang, Hsinta Wu, Kyujin Oh and Eunyoung Seok. Their frie ndship and camaraderie are priceless and I would like to thank them for thei r suggestions and advice. The l ong discussions with them that often went deep into the nights will remain etched in my mind forever. I am grateful to the guidance from former group members, Zhenbiao Li, Xiaoling Guo, Ran Li, Haifeng Xu, Yanping Ding, Changhua Cao, Jau-Jr. Lin and DongJun Yang. I would also like to recognize Wuttichai Lerdsitomboon, Gayathri Devi Sr idharan, Dongha Shim, Kwangchun Jung, Minsoon Hwang, Shashank Nallani Kiron, Chuyi ng Mao, Tie Sun and Ruonan Han. I am grateful to the support from IBM, DAR PA and Toyota during diffe rent phases of this work in the form of research grants. Special thanks go to Albert Yen at UMC Inc. and Geoff Dawe at Bitwave Semiconductor Inc. for chip fa brication. I would also like to acknowledge the support from Al Ogden for bonding the chips. Over the period of this resear ch, some wonderful friendships away from school that merit special mention were forged. I am deeply indebted to Vikas Aggarwal and Soniya

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5 Thekkevelappil for being at the ri ght place at the right time to offer support and to help maintain my tranquility during stressful periods. I am grateful to my aunt Shobhana for the i nnumerous healings, and more importantly for the help and guidance that made me what I am. I am also indebted to my sister Ramya, her husband Suresh and their lovely daughter Anusha for their warmth and affection. Finally, I would like to thank my parents whose love, prayer s and support have meant more than what can be expressed in words. It is to them that this work is dedicated. Their unconditional love, patience and encouragement have been vital to my success and progress as a human being.

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6 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................4 LIST OF TABLES................................................................................................................. ..........9 LIST OF FIGURES................................................................................................................ .......10 1 INTRODUCTION..................................................................................................................17 1.1 Rectification Using Devices in CMOS.............................................................................18 1.1.1 p-n Junction Diode.................................................................................................18 1.1.2 MOS Transistor......................................................................................................19 1.1.3 MOS SBD DC Comparison.................................................................................22 1.2 Derivation of AC Conversion Gain..................................................................................24 1.3 AM System Architecture..................................................................................................26 1.3.1 AM Transmission...................................................................................................27 1.3.2 AM Reception........................................................................................................29 1.3.3 Advantages and Disadvantages..............................................................................30 1.4 Organization of the Thesis................................................................................................31 2 DESIGN, LAYOUT A ND CHARACTERIZATION OF CMOS SBDS...............................32 2.1 Introduction............................................................................................................... ........32 2.2 SBD Device Structure.......................................................................................................33 2.2.1 Guard Rings............................................................................................................36 2.2.2 Measurement Setup................................................................................................37 2.3 Measurement Results and Discussions.............................................................................39 2.3.1 DC Characterization...............................................................................................39 2.3.2 Barrier Height Estimation.......................................................................................41 2.3.3 Noise Characterization...........................................................................................43 2.3.4 AC/RF Characterization.........................................................................................44 2.4 Conclusions................................................................................................................ .......48 3 OPTIMIZATION OF TERAHERTZ SBDs IN 130-NM CMOS TECHNOLOGY..............50 3.1 Introduction............................................................................................................... ........50 3.2 SBD Design and Layout...................................................................................................50 3.3 Measurement Results and Discussions.............................................................................53 3.3.1 Poly-SBD Characterization.................................................................................... 53 3.3.2 Tradeoff Evaluation................................................................................................55 3.4 Conclusions................................................................................................................ .......57 4 SCHOTTKY BARRIER DIODE BASE D ULTRA-WIDEBAND AMPLITUDE MODULATION (AM) D ETECTOR IN CMOS....................................................................58

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7 4.1 Introduction............................................................................................................... ........58 4.2 Overview of Ultra-Wideband Communication................................................................58 4.2.1 Necessity................................................................................................................ .58 4.2.2 UWB Signaling Principles.....................................................................................60 4.2.3 Monopulse Based UWB.........................................................................................60 4.2.4 Monopulse-based Carrier -less Transceiver............................................................62 4.3 System Architecture of AM Detector...............................................................................64 4.4 Circuit Description and Layout of AM Detector..............................................................66 4.4.1 Overview................................................................................................................66 4.4.2 Two Stage LNA Design.........................................................................................67 4.4.3 Half-wave Rectifier/Filter Design..........................................................................67 4.5 Measurement Results and Discussions of AM Detector..................................................70 4.5.1 LNA, Diode Detector and Filter Results................................................................70 4.5.2 Overall Detector.....................................................................................................73 4.6 Conclusions................................................................................................................ .......79 5 SYSTEM DESIGN OF WIRELESS INTERCONNECTS ON AN INVERTER PRINTED CIRCUIT BOARD...............................................................................................80 5.1 Introduction............................................................................................................... ........80 5.2 System Setup............................................................................................................... .....82 5.3 Concerns, Design Considerations and Tr anslation to Block Level Parameters...............88 5.3.1 Synchronization......................................................................................................88 5.3.2 Multi-path...............................................................................................................91 5.3.3 LNA and Duplexer.................................................................................................92 5.3.4 Inter-stage Amplifier (IA) and Band-Pass Filter (BPF).........................................93 5.3.5 Motor Node Analog to Di gital Converter (ADC)..................................................95 5.3.6 Other Concerns.......................................................................................................96 5.4 Simulation Results......................................................................................................... ...96 5.4.1 RX at Motor Node..................................................................................................96 5.4.2 RX at Deadtime Controller Node...........................................................................98 5.5 Conclusions................................................................................................................ .....100 6 CDMA RECEIVER FOR WIRELESS IN TERCONNECTION ON AN INVERTER PCB............................................................................................................................ ...........101 6.1 Introduction............................................................................................................... ......101 6.2 Circuit Description and Layout......................................................................................101 6.2.1 RF Section............................................................................................................103 6.2.1 SBD Rectifier.......................................................................................................105 6.2.3 Baseband Amplifier..............................................................................................107 6.2.4 Limiter..................................................................................................................110 6.3 Measurement Results and Discussions...........................................................................112 6.3.1 RF, Detector-Baseband Amplifier and Limiter....................................................112 6.3.2 Overall Receiver...................................................................................................117 6.4 Conclusions................................................................................................................ .....122

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8 7 SUMMARY AND FUTURE WORK..................................................................................124 7.1 Summary.................................................................................................................... .....124 7.2 Future Work................................................................................................................ ....124 7.2.1 SBD Evaluation....................................................................................................124 7.2.2 CDMA Receiver Chain Optimization and Characterization................................125 LIST OF REFERENCES.............................................................................................................126 BIOGRAPHICAL SKETCH.......................................................................................................133

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9 LIST OF TABLES Table page 1-1 DC gain and 3-dB frequency for varying relative magnitudes of Rs and 1/gm.................26 3-1 List of fabricated structures out of the nine possibilities...................................................52 4-1 Link margin analysis for UWB detector w ith 100 kbps data rate and 30m range. The required signal to noise ratio is ~-34 dB (SNRdB + PGdB = Eb/NodB), where Eb/NodB= 6 dB for 0.01 BER. The required signal output power level is -110 dBm. The sensitivity with the 20-dB additional gain is -93 dBm (-73 dBm from Figure 4-16(a) + 20 dB shift)................................................................................................................. ....79 5-1 Frequency plan for one side of the inverter board.............................................................83 5-2 Link margin analyses for the CDMA and FDMA links....................................................88 5-3 Summary of RF subsection specifications for CDMA and FDMA RX........................... 95 6-1 Summary of specifications, simulated and meas ured results of various blocks in the receiver....................................................................................................................... ......113

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10 LIST OF FIGURES Figure page 1-1 gm/I of a minimum geometry MOS transist or in the UMC 130-nm CMOS process as a function of bias current I.................................................................................................21 1-2 Comparison of device currents for the minimum sized NMOS and SBD in the UMC 130-nm CMOS process......................................................................................................22 1-3 gm/I plots of the minimum geometry NMOS transistor and SBD in the UMC 130-nm CMOS process...................................................................................................................23 1-4 gm as a function of device bias current (I ) for NMOS and SBD devices with varying sizes......................................................................................................................... .......24 1-5 Typical rectifier configuration with e quivalent small-signa l representation.....................25 1-6 AM system architecture.....................................................................................................27 1-7 Spectral content of an AM signal.......................................................................................28 1-8 AM rectification time and fre quency domain representations........................................29 2-1 (a) Cross-section of n/p type SBD ce ll with components contributing to Rs and Co, (b) Layout of n/p type SBD cell, and (c) Small-signal equivalent model for SBD...........33 2-2 Simulated cut-off frequency (fcutoff) versus Schottky dimension ls for SBDs in the UMC 130-nm CMOS process............................................................................................35 2-3 (a) Cross-section of an n-type SBD cell with a p+ guard ring and (b) Equivalent cell layout........................................................................................................................ ......36 2-4 (a) Layout of interleav ed metal layers and (b) Crosssection of reduced area bondpad in the UMC 130-nm CMOS process. The gr ound shield is not shown for simplicity.......38 2-5 Noise measurement setup..................................................................................................38 2-6 Current density versus voltage curves fo r diodes fabricated in the 180-nm CMOS with and without guard rings.............................................................................................39 2-7 Current density versus voltage curves for nand ptype diodes fabricated in the UMC 130-nm CMOS process............................................................................................40 2-8 Histograms for (a) current at 1-V reverse bias and (b) ideality factor ( ) over 15 ntype SBDs...................................................................................................................... ....41 2-9 Extracted zero-bias Js for SBDs of the 180-nm and 130-nm processes...........................42

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11 2-10 Measured diode noise current at bias of 100, 450, 900 and 2100 A. White noise level at bias of 450 A should be 218 dBA2/Hz.................................................................44 2-11 Measured Co and Rs for the array of 24 minimum geometry 0.45 m0.45 m diodes connected in parallel, which are fabr icated using a 180-nm CMOS process....................44 2-12 The cut-off frequency, fcutoff as a function of bias vo ltage for the array of 24 minimum geometry 0.45 m0.45 m diodes fabricated in a 180-nm CMOS process......45 2-13 Rs and Co as a function of frequency for (a) n-type and (b) p-type 130-nm SBDs............46 2-14 Average fcutoff versus bias voltage for the nand p-type diodes fabricated in the UMC 130-nm CMOS process......................................................................................................47 2-15 Scaling of fcutoff with technology........................................................................................49 3-1 Layout of SBD cell with typi cal interconnection scheme.................................................51 3-2 (a) Cross-section and (b) layout of a poly-SBD cell..........................................................52 3-3 Current density vs. bias voltage for polyand conventional SBDs...................................53 3-4 Extracted Rs and Co vs. frequency for polyand conve ntional SBDs at 0-V DC bias......54 3-5 Measured (a) diode capacitance (Co) and (b) series resistance (Rs) for the poly-SBD and structures listed in Table 3-1.......................................................................................55 3-6 Cutoff frequency (fcutoff) for the poly-SBD and structur es listed in Table 3-1..................56 3-7 Measured (a) n-well capacitance (Cwell) and (b) n-well substrate resistance (Rsub) for poly-SBD and structures in Table 3-1...............................................................................56 4-1 Time and frequency domain representati ons of a 0.5-ns monopulse. Equivalent 10dB bandwidth is greater than 4 GHz..................................................................................61 4-2 Pulse train in time and frequency domain (a) before and (b) after randomization. Spectral smoothing of the comb lines is clearly observed.................................................62 4-3 Conventional carrier-less monopulse -based transceiver for UWB....................................63 4-4 Carrier-less monopulse-based transceiver fo r UWB with an RF subsection for up and down conversion of a baseband pulse stream....................................................................64 4-5 RF transceiver with sample waveforms for operation without carrier suppression...........65 4-6 A schematic of the AM detector........................................................................................66 4-7 Simulated output power as f unction of diode bias current Input side band power, Pin is -40 dBm..................................................................................................................... .....68

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12 4-8 Input and output waveform examples................................................................................69 4-9 Simulated output power as function of the number of parallel SBDs (mSBD). Input side band power, Pin is -40 dBm........................................................................................70 4-10 Measured LNA magnitudes of S-parameters.....................................................................71 4-11 | S21| of 5th order Chebychev filter......................................................................................72 4-12 Measured magnitudes of S-parameters for the diode detector and low pass filter............72 4-13 A photo-micrograph of the detector a nd a layout of 16 SBDs in parallel.........................73 4-14 Input signal seen on (a) spectrum analyzer (b) an oscillosc ope and output signal (700 kHz, 1.4 s) seen on (c) a spectrum analyzer, and (d) an oscilloscope.....................74 4-15 Output power vs. (a) bias curre nt and (b) carrier frequency..............................................75 4-16 (a) Output power and (b) conversion gain vs. input side-band power...............................76 4-17 Noise measurement setup..................................................................................................77 4-18 Measured output noise power spectral density..................................................................78 5-1 Prototype inverter board that goes into a HEV. N1 and N2 communicate with N3-N8 and N9-N14 respectively. (Courtesy of Toyota)...............................................................81 5-2 Signaling scheme for the fo rward and reverse links..........................................................82 5-3 System block diagram of transceivers fo r the deadtime controller and motor nodes for the frequency plan in Table 5-1....................................................................................84 5-4 Coder in the deadtime controller. The data element could be either a flip-flop or a read only memory (ROM).................................................................................................85 5-5 Block diagram of baseband section of a motor node.........................................................86 5-6 (a) 8-chip signal from each channel w ithin the data period of 20-ns and (b) Comprehensive CDMA signa l in relative scale.................................................................90 5-7 Correlation of total CDMA signal with channel 3 code without and with misalignments.................................................................................................................. ..91 5-8 Correlation of total CDMA signal with channel 4 code without and with misalignments. The maximum sum is possible only for the case with no misalignment................................................................................................................... ...92 5-9 Characteristics of duplexer filters at (a ) motor nodes and (b) deadtime controller...........93

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13 5-10 Amplifier and BPF characteris tics at (a) Motor and (b) deadtime controller nodes. The characteristics are si milar except for the differe nce in frequency bands....................94 5-11 RX at motor nodes Simulation se tup and validation of operation..................................97 5-12 RX at deadtime controller node Simula tion setup and validation of operation..............99 6-1 Block diagram of CDMA receiver chain including limiter and CDR.............................102 6-2 Modified block-level schematic of CDMA receiver chain..............................................102 6-3 Circuit schematics of components in RF section.............................................................104 6-4 Simulation results for 50 RF section with 50output drivability..............................106 6-5 Circuit schematic and sample input/output waveforms of SBD half-wave rectifier.......107 6-6 Baseband amplifier (a) block di agram, and schematics of (b ) bias circuit, (c) gain, and (d) buffer blocks........................................................................................................108 6-7 Frequency response of baseband amplifier......................................................................109 6-8 Time domain response of the baseband amplifier...........................................................110 6-9 Circuit schematic of limiter.............................................................................................111 6-10 (a) Simulated time domain 240-mV peak-peak input signal to lim iter, (b) in-phase, and (c) out-of-phase signal s at the limiter output............................................................112 6-11 RF section (a) mounted on a printed circ uit board and (b) measurement setup..............113 6-12 Measured magnitudes of S-parameters and noise (NF) of RF section............................114 6-13 (a) PCB with detector-baseband amplifier stand-alone test structure mounted and bonded and (b) measurement setup..................................................................................115 6-14 Frequency response of detector-baseband amplifier and sample output power spectrum with ~-61 dBm, 200 MHz input.......................................................................116 6-15 Limiter output when input is at 200 MHz, (a) -25 dBm and (b) -35 dBm power............117 6-16 Test board used to measure the receiver chain................................................................117 6-17 Die photograph of the receiver........................................................................................118 6-18 Output power versus (a) bias current (IDIODE) and (b) carrier frequency (fcarrier).............119 6-19 Input AM signal observed on (a) an oscill oscope, (b) a spectrum analyzer, 200-MHz output seen on (c) an oscilloscope and (d) a spectrum analyzer.....................................119

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14 6-20 (a) Pout versus Pin and (b) Output noise power spectral density.......................................120 6-21 Detected baseband signal at (a) 197. 3 MHz, (b) 200 MHz, and (c) 202.3 MHz observed in a spectrum analyzer and, r ecovered clock at (d) 394.6 MHz, (e) 399.9 MHz, and (f) 404.5 MHz seen on a sampling oscilloscope.............................................121 6-22 Wireless link demonstration and setup............................................................................122

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15 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy RECEIVERS USING SCHOTTKY BARRIER DIODES IN CMOS By Swaminathan Sankaran May 2008 Chair: Kenneth K. O Major: Electrical and Computer Engineering With the rapid expansion of the market for low-cost communication devices, Complementary Metal Oxide Semiconductor (C MOS) integrated circuits technology has emerged as the technology of choice and is envisaged to remain as such. The ultimate goal has been to integrate all functiona lities on one die thereby reducing the form factor, minimizing the cost, and simplifying use. This dissertation presen ts and demonstrates the concept for efficiently providing the additional utility of signal rectification and detection in CMOS that could be used for radio frequency (RF) signal demodulation and on-chip testing. Rectification of amplitude modul ated (AM) signal at RF requ ires high-speed devices that have close to exponential transfer characteristics (cu rrent-voltage, I-V). Sc hottky Barrier diodes (SBDs), fabricated without any changes to th e mainstream CMOS process flow provide 100% improvement in the conversion ga in over MOS transistors for dete ction circuits. The requirement for not making modifications is critical toward s reducing the chip manufacturing cost. The SBDs fabricated in a 130-nm CMOS process have clos e to ideal exponential I-V characteristics and have cut-off frequencies well ove r a THz. It may be possible to open up the market for RF as well as sub-millimeter wave applications using these diodes. Experimental study into the layout of these devices indicates that it is possible to engineer these diodes fo r use in detectors with

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16 over 30 GHz bandwidth while maintaining comparab le cutoff frequency. Al so, instead of using an oxide ring, by using a polysilicon gate laye r to isolate the Schottky and well contacts, the cutoff frequency can be increased beyond 2 THz. The utility of these diodes is demonstrated by implementing a detector suitable for pulsebased ultra-wideband (UWB) applications. The de tector is capable of operating in the UWB range of 3.1 10.6 GHz with ~-56 dBm sensitivity for 100 Mbps data rate and 1-GHz pulse width. Using a detector based scheme eliminates the need for a PLL, mixer and its drivers thereby drastically reducing the power consum ption. The power consumption is only 8.5 mW. Wireless interconnects capable of replacing opto-couplers currently used on a hybrid engine controller board are pres ented. The wireless interconnects provide higher data rates and the same functionality as opto-couplers while reducing the cost and footprint. However, the control board with lots of metal traces and compon ents is expected to be a harsh environment for wireless communication. The system uses code division multiple access (CDMA) on the down link and frequency division multiple access (FDMA) on the up link. The CDMA receiver uses a SBD based detector for down-conve rsion at frequencies ranging from 15-20 GHz. A prototype of SBD detection based CDMA receiver is implem ented in a 130-nm CMOS foundry process and used to demonstrate a wirele ss link in the hybrid motor cont roller board. The receiver reconstructs the clock from the incoming signal thereby eliminating the need for an external frequency reference. The receiv er has 35-dB peak gain and ope rates optimally between 14-16 GHz. The sensitivity for an Eb/No of 14 dB and 400-Mbps data ra te is -58 dBm and the noise figure (NF) is 20 dB. The power consumption is ~ 60 mW and the receiver occupies ~2.1 mm2 of area. Successful reception and de-modulation of an AM signal transmitted 15 cm away, using the receiver, indicates the feasib ility of wireless communicatio n within the c ontrol board.

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17 CHAPTER 1 INTRODUCTION Communication, collection and generation of info rmation occupy the majority of our daily lives. The instant explosion in the market for wire less applications with the availability of costeffective means comes as no surprise. The tren d continues to be towards providing economical solutions while integrating additional functionality at the same time. In this regard, complementary metal oxide semiconductor (C MOS) technology has pr ovided an excellent platform in providing increased functionality and improved transi stor speed performance with each passing technology node [1]. Tremendous research effort s therefore have been expended towards achieving high volumes of integration by incorporating radio frequency (RF), mixed signal as well as digital functionalities on the sa me chip. Currently, it is common to find whole transmitter/receiver chains on the same die [2]-[4]. The RF part also includes Q-limited and power hungry blocks such as filters and power amplifiers respectively [5]-[10]. Another functionality which is bei ng investigated is signal rectification and detection [11]. Detection has been used for built-in self test (BIST) that involve on-chip generation of a DC level proportional to the root mean square (RMS) amplitude of an RF signal. This can be used towards estimation of various performance metric s such as the gain and IIP3/IP1dB of an LNA or a mixer [11]. The curcurrent state of the art for BIST circu its in terms of operating frequency is 20 GHz [12] (1 GHz if only the measurement results are considered [11]) in CMOS. Detection could be used for demodulating amplitude modulated (AM) signals. W ith detection being used primarily for BIST, the concept of using rectification for signal de modulation and signaling have not been widely explored at RF frequencies [13]. This work focuses on demonstra ting AM receiver circuits at RF. As will be discussed further in the chapter, depending upon the architecture used, use of detection can lower power consumption and complexity.

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18 This chapter reviews the rectification using de vices in CMOS. The crit ical parameters are identified and limitations quantified. The possibility of new structures that could offer improved performance whilst remaining within the fram ework of mainstream CMOS are discussed. 1.1 Rectification Using Devices in CMOS Typically, CMOS detection circuits use p+-n or n+-p diodes or MOS tran sistors biased in the weak-inversion or sub-threshold region [14], [15]. 1.1.1 p-n Junction Diode Conduction in a p+-n/n+-p diode is due to both majority and minority carriers, which results in a diffusion capacitance in addition to the j unction capacitance. Under reverse-bias and moderately forward-bias condi tions, the diffusion capacitance is smaller than the junction capacitance and plays an insignificant role in limiting the frequency at which these devices can be used. However, with increasi ng bias, this contribu tes in an exponential manner to the total capacitance as given in Equation (1.1) [16]. T BIAS o d dV V C C exp, (1.1) where, Cd is the diffusion capacitance at VBIAS, Cd,o is the zero-bias diffusion capacitance and VT is the thermal voltage (25 mV at room temperature). The diffusion capacitance can also be written as f m dg C (1.2) Here, gm is the diode transconductance at VBIAS and f the minority carrier transit time which is given in Equation (1.3) e sep fD W 2 (1.3)

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19 where Wsep is the spacing between the n and p contact s for a diode with short quasi-neutral region and De is the diffusion constant given by VT, with being the mobility. For a 130-nm CMOS process with minimum Wsep of 0.5 m, f is around 60 ps, which can be translated to a maximum operable frequency of around 2 GHz using a figure of merit (Equation 1.4) similar to the cut-off frequency (fT) of a transistor. f opf 2 1max, (1.4) The calculated fmax,op does not include the effects of se ries resistance nor the junction capacitance. Taking thes e into account would reduce the fre quency limit even further. This indicates that the conventiona l p-n diodes are inadequate for operation beyond 2 GHz. For this reason, BiCMOS processes that offer much reduced Wsep are often preferred over their CMOS counterparts. Using the bipolar transistors in a 7-metal layer BiCMOS process, 20-GHz RF-DC detection circuits for BIST having been demonstrated [17]. 1.1.2 MOS Transistor For a diode or device operating in the exponen tial (sub-threshold or weak inversion for MOS) region, the small signal outpu t current can be expressed using the Taylor series expansion [18] around the bias point (IO,VO) as ... 2 ) (2 2 2 O OV V OdV I d v dV dI v V I I (1.5) where, v is the small-signal input across the di ode. Higher order terms are neglected assuming v is small. For VO > 3VT, the currents of a MOS transistor in subthreshold and diode can be expressed as

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20 T O s oV V I V Iexp ) (. (1.6) Here, I(VO) is the current at bias VO and the ideality factor. VO is the voltage across the junction for a diode or VGS for a MOS transistor in subthreshold. is also a function of VO. Is is proportional to the diode area and W/L for a MOS tran sistor. Equation (1.5) can be re-written as ... ) ( ) ( ) (' O O OV i V i V I I (1.7) and ... 2 ) (' 2 m m Og v vg V I I (1.8) with gm and gm given by T O mV V I g) ( (1.9) 2 ') (T O mV V I g (1.10) For a linear circuit, the output signal is in the 1st order term i(Vo) given by vgm in Equation (1.5). For a detector circuit however, the output baseband signal is derived from the squaring operation and hence depends on the second derivative term, i(Vo) given by v2gm /2. If the detectors are intended to be us ed for signal down-conversion, i(Vo) is also directly related to the conversion gain. Figure 1-1 plots gm/I (which is equal to 1/ VT) as a function of bi as current for a MOS transistor with the minimu m drawn gate length of 0.12 m in a 130-nm CMOS process.

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21 Figure 1-1 gm/I of a minimum geometry MOS transist or in the UMC 130-nm CMOS process as a function of bias current I. In the sub-threshold region, where the current is exponentially dependent on VGS, maximum gm/I is expected. The peak value of gm/I is ~27. This is equivalent to an of ~1.5. The deviation in from the ideal value of 1 is due to the control of ch annel by the gate through the capacitive divider formed by the oxi de and depletion capacitances (COX and CDEP, respectively) in the weak-inversion regime [19]. This can be quantified as OX DEPC C 1. (1.11) The increase in degrades gm (and hence the conversion gain) to the second power. In this aspect a p-n junction diode that has close to 1 is better. However, as mentioned, the conventional diodes are limited in their frequency capabilities due to their large diffusion capacitance. This leads to explorin g and realizing a device that has similar to that of p-n junction diodes, while having re duced or zero diffusion capacitance. With this vision, the 0 5 10 15 20 25 30 1010 109 108 107 106 105 104 gm/I (V-1) Device bias current I (A)

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22 performance of a fast rectifying/detecting Sc hottky barrier diode (SBD ) engineered without modification to existing CMOS pr ocess flow is investigated. The SBDs being majority carrier devices do not have minority car rier storage, and thus ha ve no diffusion capacitance. 1.1.3 MOS SBD DC Comparison Figure 1-2 compares the current as a function of bias voltage for the minimum-sized NMOS transistor (120nm long and 360nm wide) with the smallest possi ble SBD structure that was fabricated and characterized in the UM C 130-nm CMOS. The Sc hottky area is 0.32x0.32 m2 and the detailed characteristics are presented in chapter 2. The NMOS tran sistor and SBD device have comparable forward-bias currents. However, th e increase in current with bias is steeper for the SBD compared to the NMOS. gm/I plots for both these devices are shown in Figure 1-3. The SBD exhibits a peak value of ~37 compared to 27 for the NMOS. This theore tically translates to an improvement of 100% in gm Figure 1-2 Comparison of devi ce currents for the minimum sized NMOS and SBD in the UMC 130-nm CMOS process. 1x1010 1x109 1x108 1x107 1x106 1x105 1x104 1x103 0 0.1 0.2 0.30.4 0.5 0.60.7 0.8 0.9 0 20 40 60 80 100 120 Device current log scale (A) Bias voltage (V) Device current linear scale ( A) NMOS SBD

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23 Figure 1-3 gm/I plots of the minimum geometry NM OS transistor and SBD in the UMC 130nm CMOS process. The values of gm as a function of bias current for di fferent numbers of fingers (2 and 8) of the minimum sized NMOS and SBD are plotte d in Figure 1-4. For the same number of fingers, at the peak gm for NMOS, the SBD shows an improvement that is greater than 2 in gm A drop in gm for higher bias currents is observed for bot h devices. This is due to the effects of velocity saturation in case of the MOS transi stor and high-level in jection in the SBD. Furthermore, referring back to the plots of DC current versus bias in a linear scale in Figure 1-2, the turn-on voltage for the SBD is almost 100 mV smaller compared to that of the MOS transistor in weak-inversion. This is of adde d value in systems such as power converters and rectifiers where low-power and zero-bias circuit design is of critical importance [20], [21]. 0 5 10 15 20 25 30 35 40 1010 109 108 107 106 105 104 gm/I (V-1) NMOS SBD Device bias current I (A)

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24 Figure 1-4 gm as a function of device bias current (I) for NMOS and SBD devices with varying sizes. 1.2 Derivation of AC Conversion Gain For a rectifying element biased at VO, shown in Figure 1-5, the conversion gain (CG) can be defined as the magnitude of ratio of the generated second order current (i[VO]) to the input voltage (vs). The rectifying element could be a diode or a MOS transistor appropriately biased. A typical small signal equivalent mode l is also shown in Figure 1-5. s Ov V i CG ) (' (1.12) i(VO) is dependent on the voltage across the device junction, vd, 2 '! 2 ) (m d Og v V i (1.13) 104 0 5 10 15 20 25 30 1010 109 108 107 106 105 NMOS SBD n=8 n=4 g m (mA/V2) Device bias current I (A)

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25 Figure 1-5 Typical rectifier c onfiguration with equivalent small-signal representation. vd is proportional to vs with the proportionality factor given by the impedance ratio between Rs and the device junction impedance, ) ( 1 1o m s s dC j g R v v (1.14) Using Equation (1.14) in Equa tion (1.13) and simplifying, 2 2 '1 1 2 ) (s o s m m s OR C j R g g v V i (1.15) Conversion gain (CG) is then given by 2 2 2 ') 1 ( 1 1 1 2 ) (s m s o m s m m s s OR g R C j g R g g v v V i CG (1.16) The DC gain and 3-dB freque ncy of the CG equation are 2 2 '1 2 m s m m s DCg R g g v Gain and, s m o dBR g C f 1 2 13 (1.17) RECTIFYING ELEMENT VO,IO vs i (VO) vs Rs 1/gm Covd i (VO) Rs Device series resistance Co Device junction capacitance gm Device transconductance +

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26 The following observations can be made from Equation (1.17). 1. The conversion gain is proportional to the amplitude of the input signal (vs) which indicates that gain is no longe r independent of the input as with typical linear systems. 2. Depending upon the bias conditions, for different values of gm, the DC gain as well as the 3-dB frequency could be different. Table 1-1 lists the DC gain and 3-dB frequency for different possi ble combinations of relative magnitudes of Rs and 1/gm. Under typical bias conditions, Rs is much smaller compared to 1/gm. Referring to Table 1-1, for this condition, the 3-dB frequency is independent of the device transconductance and is dependent only on the parasitic series re sistance and junction capacitance. This parameter is called as the cu toff-frequency and is ofte n used as a figure of merit to characterize the high frequency capabili ties of diodes. Incidentally, the DC gain under the same conditions is independent of th e series resistance and depends only on gm Table 1-1 DC Gain and 3-dB frequenc y for varying relative magnitudes of Rs and 1/gm. Condition DC Gain 3-dB frequency m sg R 1 2 2 '2s m m sR g g v o mC g2 m sg R 1 8' m sg v o mC g m sg R 1 2' m sg v o sC R2 1 1.3 AM System Architecture Signal rectification or detection is primarily used in AM systems wherein the information is embedded in the amplitude or signal strength. Incidentally, AM architecture was the first system topology used to demonstr ate quality audio over telephone li nes and still remains in use today [22]. The block-diagram repres entation of a simple AM syst em with example waveforms

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27 at different nodes is shown in Figure 1-6. An important featur e of AM systems is that the transmitter and receiver do not require a frequency reference. Figure 1-6 AM system architecture. 1.3.1 AM Transmission At the transmitter side, the low frequency data signal which can be either analog or digital, herein termed baseband signal, is amplitude modul ated on to a high freque ncy carrier. This can be mathematically expressed as ) ( )] ( 1 [ ) ( t c t m t Vt (1.18) Here Vt(t) is the AM signal, m(t) the low-frequency data signa l and c(t) the high frequency carrier. If c(t) is a singletone sinusoid of the form ) sin( ) ( t t cc where c cf 2 and fc is the carrier frequency, (1.19) then the AM signal can be repres ented in the frequency domain as [23] )] ( ) ( [ 2 )] ( ) ( [ ) (c c c c tM M i i V (1.20) A number of interesting observa tions can be made from the magnitude of the baseband and transmitted signal (|m(t)| and |Vt(t)|, respectively) s hown in Figure 1-7. Vt(t) PA Mixer m(t) c(t) Non-linear element RECTIFIER LNA LPF Vr(t)Vrect(t) RECEIVER TRANSMITTER

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28 Figure 1-7 Spectral content of an AM signal. First, the power efficiency of AM signal is relatively poor due to significant power of carrier (at c) which conveys no information. The maxi mum efficiency that can be achieved from these systems is around 33%. Second, obser ving the frequency cont ent, the AM signal occupies twice the bandwidth required for proper information transmission since both the positive and negative sidebands are up converted. This results in poorer spectral efficiency. This spectrally inefficient form of AM is also called as Double-side band AM (DSB-AM). The system can be made power efficient by suppressing the c ontent at the carrier frequency which leads to another form of AM called as the Doublesideband suppressed carri er AM (DSBSC-AM). DSBSC systems can have power efficiency as high as 100% since no pow er is wasted on the carrier signal. Further, the system can be made more efficient by eliminating either the positive or negative up-converted sidebands. This result s in the Single-sideband suppressed carrier AM (SSBSC-AM). The suppressed carrier systems do nece ssitate the re-introducti on of the carrier at the receiver and therefore require additional circuitry (mixer and local oscillator). It is for this reason that sometimes DSB is preferred over the more efficient forms of AM. ) (M ) ( 2 1cM ) (tV ) ( 2 1cM c c Single sideband signal will have one of the two

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29 1.3.2 AM Reception Referring back to Figure 1-6, the received AM signal is first amplified by a Low noise amplifier (LNA). Design of the LNA is particularly critical in AM systems because information is contained in the signal amplitude. The amplified signal is then rectified/detected using the rectifier which performs the cruc ial function of down-conversion. An ideal rectifier allows either positive or negative signals to pass, not both. S hown also in Figure 1-6 is the time domain snapshot of an AM signal before (Vr(t)) and after ideal rectification (Vrect(t)). In terms of the frequency content of a rectified signal, ideal rectification can also be viewed as mixing or multiplication operation between the AM signal and a square wave with 50% duty cycle operating at the carrier frequency. Multiplicati on in time-domain corresponds to convolution in frequency domain [23]. Therefore, as shown in Figure 1-8, the rectified signa l can be expressed as the convolution between the AM signal and the s quare wave in frequency domain. This results in the rectified signal having baseband inform ation at DC as well as components at higher harmonics, which is the reason w hy the signal has to be low-pass fi ltered to extract the baseband component. Figure 1-8 AM rectification time a nd frequency domain representations. . . c c c c c 2 c 2 c c

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30 The most realistic detect ors with a wide dynamic range tend to operate in the square-law mode with the rectified signa l being expressed as 2) ( ) ( t V t Vr rect where is a constant. (1.21) Vr(t) is of the form similar to Vt(t) (Equation 1.18). The differen ce in the amplit udes is accounted by Therefore, Vrect(t) can be expressed as t t m t Vc rect 2 2sin ) ( 1 ) ( (1.22) ) 2 cos 2 1 ( ) ( ) ( 2 1 22t t m t mc (1.23) If m(t) is much smaller than 1, then m2(t) term can be neglected. Taking this into account, Equation (1.23) can be rewritten as ) 2 cos 2 1 ( ) ( 2 1 2 ) ( t t m t Vc rect (1.24) Equation (1.24) shows that the rectification ope ration produces spectral components at baseband and 2fc. Representing rectification us ing a Taylor series expansi on reveals the presence of higher order harmonics in addition to that at 2fc [18]. It is therefore requ ired to low-pass filter the detected signal to ex tract the baseband signal. 1.3.3 Advantages and Disadvantages The fundamental advantage of AM/ASK system over its contemporaries is the reduction in the number of components. This also directly impacts in reducing the power consumption. DSBAM receivers do not require a synt hesizer, mixer and drivers for it s local oscillator ports which are major sources of power consumption in current architectures. This is particularly useful in implementing receiver circuits that require very low-power operation [20], [21]. The circuits

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31 must however tolerate poorer spectral and transmitter power efficiency and SNR. The degradation in spectral and transmitted power efficiencies and SNR can be improved by migrating to more sophisticated AM architectur es such as DSBSC and SSBSC albeit at the expense of additional circuitry and power consumption. Herein lies the tradeoff between the circuit complexity and improved utility of communication resources. 1.4 Organization of the Thesis This research has two major objectives. The first is realizing and characterizing Schottky barrier diode structures that promise improveme nt in AM detector performance over detectors formed using standard devices currently availabl e in mainstream CMOS processes. The second is to utilize these devices and demonstrate the functionality and lower cost in building communication receivers. The design and measurement re sults of Schottky barrier diod es fabricated in 180-nm and 130-nm CMOS are presented in chapter 2. Cutoff frequencies of ~ 400 GHz and 1.5 THz are demonstrated for the SBDs fabricated in the 180-nm and 130-nm proce sses, respectively. The measurement and de-embedding tec hniques are also brie fly described. Chapter 3 presents the tradeoffs involved in the layout of the high cuto ff frequency SBDs. Furthe r, a new SBD structure that could potentially extend th e cut-off frequency beyond 2 THz is also presented. An Ultrawideband (UWB) communication rece iver that uses these SBDs for detection over the UWB frequency range between 3.1 and 10.6 GHz is pr esented in chapter 4. System design for a CDMA based wireless communication links that may be able to re place high-cost opto-couplers on a motor controller board is discussed in chapter 5. Chapter 6 presents the design and characterization of the CDMA recei ver chain that uses SBDs for de tection. Finally, future work is suggested in chapter 7.

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32 CHAPTER 2 DESIGN, LAYOUT AND CHARACTERIZATION OF CMOS SBDS 2.1 Introduction Schottky barrier diodes (SBDs) due to their high operating frequencies and low forward voltage drops have been extens ively studied and widely used [24], [25]. The applications include RF signal rectification/detection and image sensing [26]-[28]. Silicon SBDs with near ideal I-V characteristics have been demons trated using a diffused guard ring [29], a double diffused guard ring [30] and moat-etched techniques [31]. SBDs with cut-off freque ncies up to 1 THz have been realized on high-resistivity silicon substrates by growing a thin Molecular Beam Epitaxial layer on top of an n+/p+ layer [32], [33]. Schottky contacts with a high barrier height of 0.78 eV and cutoff frequency of 600 MHz have also been impl emented by directly cont acting an n-well with Aluminum metallization [34]. Modern CMOS processes employ salicidation th at can be used to build Schottky contacts [35]. Salicidation is primarily used to improve the conductivity of poly and n+/p+ regions. The process involves deposition of a thin transition metal layer (T i until 180-nm and Co for 130-nm CMOS) over fully patterned and formed semiconduc tor devices. The wafer is heated, allowing the transition metal to react with exposed silicon in the active regions of the semiconductor device (such as the gate, s ource and drain) forming a low-resistance transition metal salicide. In a similar manner, salicidation over n/p-well regions can be used to form Schottky contacts owing to the occurrence of Fermi energy of the metal in between the valence and conduction bands of silicon. Using this method, Schottky clamped tran sistor structures with greatly reduced latch-up susceptibility while maintaining the same drive current as conventional transistors have been demonstrated by blocking n+/p+ implantation in selected salicided regions [36], [37]. Using the same approach, TiSi2-Si Schottky diodes in a 180-nm and CoSi2-Si Schottky diodes in a 130-nm

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33 CMOS technology are fabricated and their DC and AC performances are characterized and presented in this chapter. The fabrication of Schottky diodes does not involve modification of the process flow and the diodes can be fabricated alongside the NMOS and PMOS transistors thus leading to lower cost and monolithic integration. 2.2 SBD Device Structure A cross-section and a layout of n and p-type Schottky diodes are shown in Figure 2-1(a) and (b). The ohmic contacts to the n/p-wells around the Scho ttky contact form the second terminal. Shown in Figure 2-1(c) is the smallsignal representation of the Schottky diode. Figure 2-1 (a) Cross-section of n/p type SBD cell with components contributing to Rs and Co, (b) Layout of n/p type SBD cell, and (c) Sm all-signal equivalent model for SBD. n+/p+ implant Metal n/p-well l2 l1 ls (a) (b) Schottky n+/p+ diffusion Contact /via Rs Cj Rsub Cwell Cp Rd n-terminal p-substrate/ t-well Schottky terminal Rs Series resistance Cj Junction capacitance Rd Diode on resistance = kT/qIdiode Cwell Well-substrate-diode reverse bias capacitance Rsub Well-substrate-diode parasitic series resistance Cp Sidewall parasitic capacitance (c) STI STI STI STI p+/n+p+/n+ ILD ILD ILD ILD lsl1l1l2l2 R1CjoR2R3R2R3 RcRcRcCpCpn-terminal Schottky terminal Ti/CoSi2-Si Schottky Contact n/p-well p-substrate/t-well Cwell Rsub Cwell Rsub STI STI STI STI p+/n+p+/n+ ILD ILD ILD ILD lsl1l1l2l2 R1CjoR2R3R2R3 RcRcRcCpCpn-terminal Schottky terminal Ti/CoSi2-Si Schottky Contact n/p-well p-substrate/t-well Cwell Rsub Cwell Rsub STI STI STI STI p+/n+p+/n+ ILD ILD ILD ILD lsl1l1l2l2 R1CjoR2R3R2R3 RcRcRcCpCpn-terminal Schottky terminal Ti/CoSi2-Si Schottky Contact n/p-well p-substrate/t-well Cwell Rsub Cwell Rsub Cwell Rsub Cwell Rsub

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34 The quality factor (Q) for an SBD is the cutoff frequency (fcutoff) given in Equation (2.1) [25], [33] divided by the operating frequency. o s cutoffC R f 2 1 (2.1) Rs is the series resistance and Co the capacitance at zero bias. The approximate expressions of Rs and Co are given in Equations (2.3) and (2.5), resp ectively.Individua l components that contribute to Rs and Co of a square diode are in dicated in Figure 2-1(a). c sR R R R R 3 2 1 (2.2) c s n sa v s STI sh nwell sh sR l l l R R l l R R R 1 2 12 2 4 29 (2.3) p jo oC C C (2.4) p BI Si D s oC qN l C 22 (2.5) where Rsh-nwell is the n-well sheet resistance, Rsh-STI is the n-well sheet resistance under the shallow trench isolation, Rsa-n+ is the salicided n+ sheet resistance, Rc is the resistance associated with contacts and vias, Rv is the vertical component of the n-well resistance, Cjo is the zero bias junction capacitance, q is the charge on an electron, ND is the n-well doping density, Si is the permittivity of silicon, BI is the built-in potential and Cp is the metal-metal sidewall parasitic capacitance. ls, l1 and l2 are the dimensions indicated in Fi gure 2-1(b). The factor of 1/29 is derived from the base-spreading resistance model presented in [38]. R2 and R3 are obtained by counting the number of squares. The factors of and in R2 and R3 account for the four-sided and two-sided resistances in parallel, respectively.

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35 The series resistance is reduced by minimizi ng the space between the Schottky contact and n+/p+ diffusion regions. Rs is further reduced by increasing the n+/p+ diffusion width and by having multiple contacts on the diffusion regions. The metal connections to Schottky and n+/p+ diffusions are spaced wide apart (l2 = 1.2 m and 0.7 m fo r 180-nm and 130-nm CMOS processes, respectively) to reduce the sidewall pa rasitic capacitance. This is critical for achieving a high cut-off frequency as well as maintain ing reasonable junction grading coefficient (mj). Because the minimum diode area (ls 2) and metal-to-metal spacing of multi-level metal layers can be small, the impact of parasitic capacitance ca n be particularly great. The only controllable parameter in the design of these diod es is the device cross-section area As (As = ls 2), since all the other parameters such as barrier height and dopi ng are set by the process. A plot of calculated cut-off frequency using Equations (2-1) thro (2-5) versus ls is shown in Figure 2-2 for SBDs in the 130-nm CMOS. A monotonic decrease in fcutoff with ls is observed. Figure 2-2 Simulated cut-off frequency (fcutoff) versus Schottky dimension ls for SBDs in the UMC 130-nm CMOS process. 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.4 1.2 1.0 0.8 0.6 0.4 0.2 f cutoff ( THz ) Schottky dimension ls ( m) 130-nm process minimum 0.32 m

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36 This is because Co and Rs are roughly proportional to As and As -0.5. As a result, increasing As decreases the cut-off frequency. Because of this, the Schottky contact area (As) is set to the minimum contact diffusion area perm itted by the process of 0.45 0.45 m2 and 0.32 0.32 m2 for the 180-nm and 130-nm CMOS processes, respectively. Due to this small diode area, even with a large spacing, the measurements suggest that the metal-to-metal capacitance contributes considerably to the total capacitance. 2.2.1 Guard Rings Leakage current under reverse bias is signi ficantly higher for SBDs compared to n+-p/p+-n diodes due to a smaller barrier height ( BI) and hence a smaller built-in potential (VBI = q BI). The leakage is especially high at the perimeter of Sc hottky diode junctions due to high electric fields. Guard rings formed using p+ or n+ diffusions around the Schottky in n/p-well, respectively reduce this leakage. Figure 2-3(a) shows the cro ss-section of an SBD cell in an n-well with a p+ guard ring around the Schottky region. The equiva lent layout is shown in Figure 2-3(b). Figure 2-3 (a) Cross-section of an n-type SBD cell with a p+ guard ring and (b) Equivalent cell layout. n+ implant Metal n-well l g uard p+ implant (a) (b) n+ diffusion Contact/via Schottky

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37 The structures fabricated in the 180nm CMOS have the guard ring width (lguard) varied from 0.12 0.24 m. The ratio of Schottky contact area to the p+ guard ring area is fixed at ~3 to reduce the contribution of p+-n/n+-p diodes to the forward bias current. To satisfy this requirement and maximum lguard of 0.24 m, the diodes have a significantly larger area (2.5 x 2.5 m2). 2.2.2 Measurement Setup To improve the power handling capability and measurement accuracy, 24 Schottky-cells in 180nm and 16 Schottky-cells in 130-nm, CMOS are connect ed in parallel. It is important to limit the total capacitance value to make sure that Rs is sufficiently larger than the contact resistance of high frequency probes (1-2 ). The structures are configur ed for one-port measurements. Ground shielded bond pads with a reduced area a nd capacitance are used to increase the device capacitance to de-embedded capacita nce ratio once again to improve the measurement reliability [39]-[41]. The bond pads have areas of 48 48 m2 and 50 54 m2 in the 180-nm and 130-nm CMOS processes, respectively. The pads are constr ucted using the top metal layer (Metal 6) in the 180-nm process. In the 130-nm process, the pa ds have additional meta l layers (Metals 6, 4 and 2) beneath the top metal laye r (Metal 8) to partially satisfy the mechanical strength requirements of bond pads. Strips of floating metal patterns are laid with the minimum overlap between the alternate metal layers of 6, 4 and 2 to reduce the inter-metal coupling and hence the overall pad capacitance. The cr oss-section of the reduced area bond-pad in the 130-nm CMOS process is shown in Figure 2-4. Measurements indicate this structure to have a reduced capacitance of 28 fF which is 20 fF smaller compar ed to the conventional AC pad structure that is larger (76 64 m2) and has all the metal layers. A dedi cated open structure for each of the diodes is used to de-embed the parasitic capacitances [39]. A short structure is used to de-embed the probe contact resistance [39]. Finally, to characterize the noise performance of the minimum

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38 sized SBDs, 96 130-nm n-type SBD cells (0.32 0.32 m2) are shunted in parallel to ensure adequate generation of noise currents. Figure 2-4 (a) Layout of interl eaved metal layers and (b) Cr oss-section of reduced area bondpad in the UMC 130-nm CMOS process. The ground shield is not shown for simplicity. The measurement setup used to characterize the noi se performance is shown in Figure 2-5. The SBD is connected serially with a bias resistor (RBIAS) using DC probes and is biased from a voltage source (battery VBIAS). Figure 2-5 Noise measurement setup. 60 dB Model 5184 Ultra-low noise preamplifier DUT RBIASVBIASHP 3561A 1-100 kHz Dynamic signal analyze r Metal 6 stripes Slotted Metal 8 Metal 4 stripes Al metallization 54 m x 50 m 50 m x 46 m Passivation opening 10 m Metal 2 stripes Al Metal 8 via* Ground shield not shown for simplicity

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39 The generated noise is amplifie d using a ultra-low noise amplif ier with 60-dB gain (Model 5184) and observed on a signal analyzer (HP 3561A). The whole setup (e xcluding the sign al analyzer) is placed inside a metal cage to minimize th e effects of external noise. The BNC cable connecting the output of the amplifie r to the signal analyzer is also shielded using aluminum foil for the same reason [42]. 2.3 Measurement Results and Discussions 2.3.1 DC Characterization The J-V curves of the SBDs in an n-well with and without p+ guard-rings fabricated in the 180-nm CMOS is shown in Figure 2-6. Figure 2-6 Current density versus voltage curv es for diodes fabricated in the 180-nm CMOS with and without guard rings. These devices have an ideality factor ( ) of ~1.8 which is large. For the 2.5 x 2.5 m2 diode without the guard ring, the reve rse leakage current de nsity at 1-V reverse bias is ~ 440 nA/m2. The leakage current is reduced with an increase of guard-ring width. For the device with a 0.18Bias voltage (V) 1x1013 1x1011 1x109 1x10-7 1x105 1x103 1x101 -2 -1.5 -1.0 -0.5 0 0.5 1 1.5 2 No g uard 0.12 m g uard 0.18 m g uard 0.24 m g uardCurrent densit y ( A/ m2 )

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40 m wide p+ guard ring and the same diffusion area (2.32 x 2.32 m2 Schottky area), the reverse leakage current density drops down by a factor of ~100 at 1-V reve rse bias and by a factor of ~6 at 3-V reverse bias. The guard rings also redu ce the forward bias current by ~3.5X at 0.35-V forward bias due to the reduction in eff ective Schottky area. The devices with p+ guard rings show an abrupt change in current when the forward bias is larger than ~1.5 V. This is caused by the p-n junction current becoming larger than the Schottky diode current. The diodes without the p+ guard rings are leaky. This is a concern but it is a limitation that can be tolerated if the devices are used in the forward bias region with limited vo ltage swing. J-V curves for SBDs in an n and a p well, fabricated in 130-nm CM OS are shown in Figure 2-7. Figure 2-7 Current density versus voltage curves for nand ptype diodes fabricated in the UMC 130-nm CMOS process. For both of these diodes, the current increases by a decade for ~65-mV increase in forward bias which indicates an ideality factor of 1.08. The leakage cu rrent densities of n and p-type diodes at 1.0-V reverse bias vary between 2 and 60 nA/ m2, and between 26 and 330 nA/ m2, Current densit y ( A/ m2 ) Bias voltage (V) 1x1014 1x1012 1x1010 1x1008 1x1006 1x1004 1x1002 0 -2 -1.5 -1.0 -0.5 0.5 1.0 1.5 2 n-t yp e p -t yp e

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41 respectively. The actual leakag e currents for the structures va ry between 0.4 and 10 nA, and between 4.2 and 54 nA, respectively, which are not terribly high. This indicates that a guard ring for reducing the leakage current, which incr eases the capacitance and lowers the cut-off frequency, may not be needed even for the 0-V dc bias operation. Histograms of current at 1-V reverse bias and for the n-type SBDs measured over 15 samples are shown in Figure 2-8(a) and (b). The average values of the current at 1-V re verse bias and are ~1 nA and 1.08.A possible reason for this improvement over th e 180-nm SBDs is the use of CoSi2-Si junctions which have larger barrier heights compared to the TiSi2-Si junctions. The turn-on voltages and forward knee currents (IKF) are ~0.4/0.3 V and ~1/0.6 mA fo r the n and p-type Schottky diodes. Figure 2-8 Histograms for (a) current at 1-V reverse bias and (b) ideality factor ( ) over 15 ntype SBDs. The reverse breakdown voltage is ~15 V for both of the devices with an appreciable reverse leakage current of 1 A at ~ 10.5 V for the n-type and ~3 V for the p-type structures. 2.3.2 Barrier Height Estimation The barrier height is a critical parameter that infl uences all of the SBD char acteristics such as the forward bias current, turn-on voltage, leakage performance and junction capacitance. Since the 1.06 1.08 1.1 1.12 1.14 (b) (a) 0 1 2 3 4 5 6 Reverse bias current (pA)Number of samples Peak at ~ 1nA 10 1 10 2 10 3 10 4 Number of samples Ideality factor ( ) 0 1 2 3 4 5 6 Peak at 1.08

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42 current transport in a Schottky barrier contact is sometimes explained in terms of the thermionic emission-diffusion theory of carriers into vacume [25], BI can be extracted from the SBDs forward J-V plots. Figure 2-9 Extracted zero-bias Js for SBDs of the 180-nm and 130-nm processes. Based on the thermionic emission model, the cu rrent density (J) for SBD with moderately doped semiconductor and V>3kT/q is, 1x1012 1x1010 1x108 1x106 1x104 0 0.05 0.1 0.15 0.2 0.25 130-nm SBD n-type p-type Jsp = 2.5 nA/ m 2 Slope ~ 65 mV/decade Jsn = 80 pA/ m 2 Current density (A/ m2) Bias voltage (V) 1x1010 1x109 1x108 1x10-7 1x106 1x10-5 1x104 0.05 0 0.1 0.15 0.2 0.25 Js = 80 nA/ m 2 Current density (A/ m2) Bias voltage (V) Slope = 108 mV/decade 180-nm SBD (a) (b)

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43 kT qV kT q T A JBIexp exp2 *, (2.6) where J is the current density, A* is the effective Richardson constant for metal-semiconductor interface, T is the temperature, q is the charge on an electron, k is the Boltzmann constant, BI is the barrier height and is the ideality factor. The barrier height can be extracted from, s BIJ T A q kT2 *ln, (2.7) where Js is the extrapolated saturation current dens ity at 0-V bias.A plot of measured forwardbias current with extrapolated value of Js for the SBDs in an n-well on the 180-nm CMOS process is shown in Figure 2-9(a) Figure 2-9(b) plots the measur ed forward bias currents with the extrapolated current densities at 0-V bias (Jsn and Jsp) for the SBDs in an n and a p well fabricated in the 130-nm CMOS. Th e effective Richardson constants (A*) of 1.12 A/m2K2 for electrons and 0.32 A/m2K2 for holes are used to determine the barrier height [43]. The extracted value of Js is 80 nA/m2 for the SBDs in a n-well of th e 180-nm process. The extracted Js for the 130-nm SBDs in an n-well and a p-well are 80 pA/m2 and 2.5 nA/m2, respectively. At room temperature (T = 298K), the respective ba rrier heights are 0.35, 0.52 and 0.44 eV for the n-well 180-nm SBD, and nand pwell 130-nm SBDs. 2.3.3 Noise Characterization The measured noise currents of 96 n-type minimum sized (0.32 0.32 m2) SBD cells in 130nm CMOS are shown in Figure 2-10. Approximate ly 15-dB increase in low-frequency noise is observed for a 10X current increase, similar to that reported for TiN-Si diodes [44]. The 1/f corner frequency at 450 A is ~3 MHz.

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44 Figure 2-10 Measured diode noise current at bias of 100, 450, 900 and 2100 A. White noise level at bias of 450 A should be 218 dBA2/Hz. 2.3.4 AC/RF Characterization Figure 2-11 plots the series resistance (Rs) and diode capacitance (Co) of the 24-cell minimum sized diode (0.45x0.45 m2) fabricated in the 180-nm process. Figure 2-11 Measured Co and Rs for the array of 24 minimum geometry 0.45 m.45 m diodes connected in parallel, which are fa bricated using a 180 -nm CMOS process. 0 10 20 30 40 50 0 4 8 12 16 20 Junction capacitanceJunction capacitance (fF) 18 19 20 17 16 15 Series resistanceSeries resistance ( ) Frequency (GHz) 10 2 10 3 10 4 10510 6 -220 -210 -200 -190 -180 -170 -160 -150 Frequency (Hz) Noise current (dB A 2/Hz) 450 A 2.1 mA White noise level at 450 A 10 dB/decade 900 A 100 A

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45 S-parameters are measured between 15 and 20 GHz using a Vector Network Analyzer (HP-8510C) and the values of Rs and Co are extracted using th e one-port de-embedding technique in [39]. The capacitance and resistance are relatively constant over the frequency range. Using the measurement results at 20 GHz, the computed cut-off frequency using Equation (2.1) is over 400 GHz. A plot of fcutoff as a function of bias voltage is show n in Figure 2-12. A decrease in cut-off frequency with an increase of bias is observed. This is attributed to the monotonic increase in diode capacitance with bias.E quation 2-8 shows the monotonic dependence of diode junction capacitance on bias voltage (V). jm BI jo jV C C 1, (2.8) where Cj is the junction capacitance at V, Cjo is the zero-bias junction capacitance, BI is the built-in potential and mj is the junction grading coefficient. Figure 2-12 The cut-off frequency, fcutoff as a function of bias volta ge for the array of 24 minimum geometry 0.45 m0.45 m diodes fabricated in a 180-nm CMOS process. 300 400 500 600 700 -2 -1.5 -1 -0.5 0 0.5 Cut-of frequency (GHz) Bias voltage (V)

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46 The cut-off frequencies of devices with the p+ guard rings are ~60 GHz or less. This reduction is due to the larger diffusion area resulting in a la rger capacitance. Plots of Rs and Co for the n and p-type devices fabricated in 130-nm are shown in Figure 2-13(a) and (b). Figure 2-13 Rs and Co as a function of frequency for (a) n-type and (b) p-type 130-nm SBDs. 2.0 4.0 6.0 8.0 10.0 12.0 0.0 0 10 20 30 40 50 Junction capacitance Junction ca p acitance ( fF ) Series resistanceSeries resistance ( ) 181920 17 16 15 Frequency (GHz) p-type SBD 2.0 4.0 6.0 8.0 10.0 12.0 0.0 10 20 30 40 50 Junction ca p acitance ( fF ) Series resistance ( ) 181920 17 16 15 Frequency (GHz) 0 Junction capacitance Series resistance n-type SBD (a) (b)

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47 Again, Rs and Co are extracted from the measured one -port S-parameters between 15 and 20 GHz using the Agilent-8510C vector network anal yzer. The capacitances ar e relatively constant over the frequency range. The resistances, however exhibit significant variations about a mean value. This is caused by the va lues of resistances and capacita nces being simultaneously small and the de-embed capacitance being larger than the diode capacitance.The cut-off frequencies computed using Equation 2-1 range between 1 to 3 THz (~1.5 THz average) for the n-type diode, and between 1 to 1.7 THz (~1.2 THz average) fo r the p-type. The n-type diode has a higher fcutoff due to slightly lower capacitance. This is possi bly due to the higher built-in potential of n-type devices. Plots of fcutoff versus bias voltage for the 130-nm nand ptype SBDs are shown in Figure 2-14. Monotoni c decrease in fcutoff with bias voltage predicte d in Equation 2-8 is again observed. Figure 2-14 Average fcutoff versus bias voltage for the nan d p-type diodes fabricated in the UMC 130-nm CMOS process. For the devices fabricated in both of th e 180-nm and 130-nm CMOS processes, the measured resistance are in good ag reement with the simulated es timates using Equations (2.2) n-t yp e p -t yp e 1.1 1.2 1.3 1.4 1.5 1.6 1.7 -1.5 -1 -0.5 0 Bias voltage (V) Cut-off frequency (THz)

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48 thru (2.4). The diode capacitance however is almo st twice as large compared to the estimates purely based on junction cap acitance. This additional capacitance can be attributed to the metalmetal sidewall parasitic capacitance between the metal interconnects of Schottky and n+/p+ contacts. A reduction in this para sitic should yield even higher fcutoffs. To utilize these devices at frequencies greater than 100 GHz full 3-D electro-magnetic (E M) simulations are however required to comprehensively understand their behavi ors. This includes inductive and skin effects that have a huge impact on circuit performance at those frequencies. 2.4 Conclusions SBDs with cut-off frequencie s around 400 GHz and over 1 THz have been realized in 180nm and 130-nm foundry CMOS processes. No add itional masks or modifications are needed to fabricate these devices. The Schottky ba rrier contacts were formed by blocking n+ /p+ implants in diffusion areas. The high leakage current for devices in the 180-nm CMOS is a concern, but this can be tolerated by using the devices in the fo rward bias region with limited voltage swing. Guard ringed structures show more than 100X reduction of re verse leakage; however, this reduces the cut-off frequency by a factor of ~6-7. Devices in the 130-nm CMOS, however exhibit excellent reverse bias characteristics that may circumvent the need of having guard ring structures to reduce the reverse leakage current. The 130-nm devices have a 1/f corner frequency of ~3 MHz. The high breakdown voltage suggests a potential use of these devices also in high power switches. The high cut-off frequencies indicate that these devices can very well be used for millimeter and infrared applications [45]. Scaling down of technol ogy is expected to yield higher fcutoffs. The projected fcutoff as a function of technology node is shown in Figure 2-15. The measured data points on 180-nm and 130-nm are al so plotted in the same figure. At the 65-nm node, it may be possible to attain fcutoff of around 3-4 THz. Using such diodes, it will be possible

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49 to implement detectors operating at frequencies as high as half TH z along with other circuitry, all fabricated in CMOS technology. Figure 2-15 Scaling of fcutoff with technology. 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.25 0.180.130.090.065 Technology ( m) Cut-off frequency (THz) Measured data point

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50 CHAPTER 3 OPTIMIZATION OF TERAHERTZ SBDS IN 130-NM CMOS TECHNOLOGY 3.1 Introduction The small-signal equivalent circuit that captu res all the primary and parasitic components of an SBD fabricated in CMOS technology was shown in Figure 21(c). The series resistance (Rs) and diode capacitance (Co) are given by Equations (2.3) and (2.5). In addition, the model also includes the well to substrate diode reverse bias junction capacitance (Cwell) and its associated resistance Rsub. These two elements are in series be tween the n-terminal and substrate. As described in section 2.2, it is essential to minimize both Rs and Co to maximize fcutoff. Also, if these diodes are to be used in anti-parallel c onfiguration (such as fu ll-wave high-frequency detectors) or for detection of si gnals with very wide bandwidths ( over 30 GHz), it is necessary to limit Cwell. This chapter presents the measured depe ndences of series resistance, capacitance, cutoff frequency, n-well to substrate capaci tance and resistance on the diode layout. SBD structures with a comparable fcutoff as the previously reported st ructure in chapter 2 and ~5X lower n-well to substrate capacitance are presented. Furthermore, a new diode structure in which Schottky and n-well contacts are se parated by a polysilicon gate laye r instead of a shallow-trench that can increase fcutoff by 2X is also presented. 3.2 SBD Design and Layout The layout of a single SBD cell in an n-we ll and the typical manner in which they are interconnected are illustrated in Figure 3-1. To minimize Rs at given Co, the diode is formed by parallel connecting minimum ar ea Schottky contacts (0.32.32m2). This maximizes fcutoff. The width of shallow tren ch isolation (STI) l1 in Figure 3-1 is set at the minimum allowable separation between diffusion regions of 0. 22 m. This limits the contribution of R2 (resistance of n-well under the shallow trench ) in Equation (2.3) to Rs.

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51 Figure 3-1 Layout of SBD cell with typical interconnection scheme. Decreasing l2 reduces Rs, this however will increase the side-wall parasitic capacitance (Cp) and hence Co. This effect could be non-negligible especi ally when the Schottky junction capacitance (Cjo) is small (~0.2-0.5 fF). Raising l2 however increases n-well cap acitance and decreases the resistance (Cwell and Rsub) to substrate (Figure 2-1(c)). A sim ilar tradeoff is apparent with varying l3, which is the spacing am ong SBD cells (Figure 3-1). To observe the tradeoff, multiple devices with varying l2 of 1.14, 1.57 and 2 m and l3 of 0.16, 0.3 and 0.6 m are fabricated and evaluated. Out of the possible set of nine combinations between l2 and l3, five structures as indicated in Table 3-1 are fabricated. Of the four resistances, R1-Rc in Equation (2.2), R2 is the dominant contributor. The impact of R2 can be reduced by using a polysilicon gate ring (poly-SBD) instead of an STI ring for separating Schottky and n-we ll contacts. The crosssection and layout of a poly-SBD cell is shown in Figure 3-2. The effect of using the polysilicon gate ring is two fold. It reduces l1 of ~0.2 m for the conventional SBD to the minimum gate length of ~0.12 m for the poly-SBD. Furthermore, the region under the STI which sets R2 is replaced by the lower sheet resistance n+ im p lant Schottk y n+ diffusion Contact/via Metal l s l1 l 2 l3 l3 Metal 6 Metal 2

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52 region under the gate oxide. The poly-SBD occupies ~60% larger area due to the larger required polysilicon to source/drain cont act spacing than that for the diffusion overlap of a contact. Table 3-1 List of fabricated struct ures out of the nine possibilities. l2 l3 2 m 1.57 m 1.14 m 0.6 m 0.3 m 0.16 m To improve AC measurement accuracy, 16 diode cells are connected in parallel with the structures configured for one-port measurements [39], as described in chapter 2. The second terminal is grounded with the substrate to fac ilitate more robust de-embedding of the bond pad parasitics. Figure 3-2 (a) Cross-section and (b) layout of a poly-SBD cell. n+ implant Schottky n+ diffusion Contact/via Metal ls l 2 l1: 0.12 poly (a) (b)

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53 3.3 Measurement Results and Discussions 3.3.1 Poly-SBD Characterization A plot of DC current density as a function of bi as voltage for the poly-SBD is shown in Figure 33. Also shown in the same figure is a plot for a conventional SBD. The ideality factor ( ) of poly-SBD and conventional SBD is ~1.35 and ~1 .08, respectively. Additionally, the poly-SBD has more than 10X larger leakag e current density at given revers e bias voltage. This indicates that the leakage in the edges bor dering the spacers is higher than that for the edges bordering STI. The non-ideal nature and increased leakage in the poly-SBD suggest the presence of additional surface imperfections [26]. The extracted barrier he ights based on the thermionic emission model is ~0 .50 eV, respectively [24], [25]. The poly-SBD turns on at ~0.3 V and has a forward knee current (IKF) of ~0.1 mA. Figure 3-3 Current density vs. bias voltage for polyand conventional SBDs. Current density (A/m2) -2.0 -1.5 -1.0-0.50.00.5 1.0 10-16 10-14 10-12 10-10 10-8 10-6 10-4 10-2 Bias voltage (V) Conventional SBD Poly-SBD

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54 Figure 3-4 plots series resistan ce and diode capacitance of the poly-SBD and contrasts it with those for the conventional SBD structure. Figure 3-4 Extracted Rs and Co vs. frequency for polyand conventional SBDs at 0-V DC bias. Rs and Co at 0-V DC bias are extracted from oneport S-parameters meas ured between 15 and 20 GHz using an HP-8510C Vector Network An alyzer. The resistance plots exhibit variation about a mean value similar to the resu lts presented in chapter 2. Average Rs of the poly-SBD is 2.5X smaller than that of the conventional struct ure, which is expected from Equation (2.3). The extracted capacitances are essentially cons tant over the entire frequency range. Co for the polySBD is larger (7.4fF) compared to the conventi onal SBD (5.7fF) due to th e larger cell area of poly-SBD. The cut-off frequencies are computed us ing Equation (2.1) with the average values of Rs and Co. The conventional SBD structure has fcutoff of ~0.76 THz. This is lower than the previously reported fcutoff of ~1.5 THz reported in chapter 2. This is partially due to the reduced 15 16 17 18 19 20 20 40 60 0 1 2 3 4 5 6 7 8 9 0 80 Co ( fF ) Frequency (GHz) Rs ( ) Cavera g e= 5.7 fF Raverage = 37 Cavera g e= 7.4 fF Raverage = 14.5 Poly-SBD Conventional SBD

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55 overlap of n-well between consecutive SBD cells (l3) from 1.2 to 0.6 m which is done to lower n-well to substrate capacitance. A more detailed discussion of the tradeoffs will be presented in the next section. The poly-SBD has fcutoff of ~1.5 THz. This fcutoff is almost 2X of that for the conventional structure with the minimum allowable l1 and ls. 3.3.2 Tradeoff Evaluation The measured Rs and Co over 15-20 GHz for the structures in Table 3-1 are shown in Figure 3-5. The series resistance and diode capacitance are extracted from S-parameter measurements as described in the previous se ction and section 2.3.4. Rs and Co reported in Figure 3-5 are average values over the frequency range. The structures with smaller l2 and larger spacing (l3) have smaller Rs as expected from Equation (2.2). The dependence of Rs on l3 is more significant for smaller l2, which could be due to comparable Rs contributions from the resistances dependent on l2 and l3. The dependence of Rsub on l3 is also stronger for smaller l2 (Figure 3-7(b)). Figure 35(b) shows almost negligible change in Co for different structures which indicates a small contribution from the side-wall parasitics (Cp). Figure 3-5 Measured (a) diode capacitance (Co) and (b) series resistance (Rs) for the polySBD and structures li sted in Table 3-1. 0.6 0.3 0.16 l3 ( m) 0 2 4 6 8 Co (fF) poly-SBD l2 ( m) 2.0 1.57 1.14 5.6 fF 5.7 fF 5.4 fF 5.8 fF 7.4 fF (a) (b) 5.7 fF 40 Rs ( ) 1.57 1.14 0.3 0.16 0 20 50 l3 ( m) poly-SBD 33 22 38 43 15 l2 ( m) 37 0.6

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56 Figure 3-6 Cutoff frequency (fcutoff) for the poly-SBD and structur es listed in Table 3-1. The extracted value of Cp is ~0.3 and 0.7 fF for the structures with l2/l3 of 2 m/0.16 m and 1.14 m/0.6 m, respectively. As a consequence, fcutoff (Figure 3-6) is the la rgest for the device with the smallest Rs, or l2 = 1.14 m and l3 = 0.6 m (~1.3 THz) among the conventional structures. Additionally, the n-well capacitance of this struct ure is one of the lowest. (Figure 3-7). These results in combination with those fr om chapter 2 indicate an optimal l2 between 0.7-1.1 m, and l3 over 0.6 m. Figure 3-7 Measured (a) n-well capacitance (Cwell) and (b) n-well substrate resistance (Rsub) for poly-SBD and structures in Table 3-1. 2.0 1.57 1.14 0 0.4 0.8 1.2 1.6 l2 ( m) 0.6 0.3 0.16 l3 ( m) fcutoff ( THz ) poly-SBD 0.85 THz 0.65 THz 0.76 THz 0.78 THz 1.3 THz 1.5 THz (a) (b) 0 20 40 60 36 fF 40 fF 52 fF 44 fF Cwell (fF) 2.0 1.57 1.14 0.3 0.16 0.6 l3 ( m) l2 ( m) poly-SBD 54 fF 0 40 80 120 l2 ( m) poly-SBD 108 72 57 67 Rsub ( ) 2.0 1.57 1.14 0.3 0.16 0.6 l3 ( m) 55

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57 3.4 Conclusions A novel Schottky barrier diode in foundry CMOS that employs a polysi licon gate ring for separating the Schottky and n-well contact is realized. No additi onal masks or process modifications are needed to fabricate these devices. The poly-SBDs have poorer leakage and ideality compared to the conventional SBDs. Th e higher leakage can however be tolerated by using these diodes in the forward-bias region. The poly-SBDs exhibit 2X improvement in cut-off frequency over a conventional SBD structure w ith the similar layout. The tradeoff study in engineering the n-well ohmic contacts for the minimum Schottky contact area indicates the optimal structure in terms of the cut-off freque ncy, n-well to substrate parasitic capacitance and resistance has l2 around 0.7-1.1 m and inter-cell spacing (l3) over 0.6 m. This should have fcutoff comparable to the 130-nm n-type structure pr esented in chapter 2 and ~5X lower n-well to substrate capacitance. The 2X improvement in cu t-off frequency of the poly-SBD in addition to the ~80% reduction of Cwell suggests that it should be feas ible to realize SBDs with fcutoffs greater than 2 THz and use them for detection of signals with ba ndwidths greater than 30 GHz in 130-nm CMOS.

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58 CHAPTER 4 SCHOTTKY BARRIER DIODE BASE D ULTRA-WIDEBAND AMPLITUDE MODULATION (AM) DETECTOR IN CMOS 4.1 Introduction In order to demonstrate the usefulness of SBDs formed in CMOS technology, an AM detector which can de-modulate ultra-wide band (UWB ) signals in the 3.1-10.6 GHz UWB band with a bandwidth of ~1 GHz is fabricated in the UMC 130-nm logic CM OS process. The design and measured performance of the detector are pr esented in this chapte r. The input and output matching of the detector is better than -10 dB from dc to 10.3 GHz and dc-1.7 GHz, respectively, and almost covers the entire UWB frequenc y band (3.1 10.6 GHz). The measured peak conversion gain is -2.2 dB. The sensitivity over the band for amplitude modulated signals with the minimum Eb/No of 6 dB and bandwidth of 1 GHz is between -53 and -56 dBm. The power consumption is only 8.5mW. These indicate that it should be possible to use this detector to down convert a chain of monocycles implementing pul se position modulation that have been upconverted using a carrier so that the signal can be transmitted and received with relatively narrow band antennas. As mentioned in section 1.3.3, this detection technique does not require a synthesizer and drivers for a mixe r, which are major sources of power consumption in the radio frequency (RF) section of a receiver. 4.2 Overview of Ultra-Wideband Communication 4.2.1 Necessity Ultra-wide band (UWB) signaling is a short-range wireless sche me that is rapidly gaining popularity. As the name indicate s, UWB occupies a very huge signal bandwidth compared to conventional narrow-band standards such as GSM and 802.11. By definition, a radio signal that has a fractional bandwidth ( ) greater than 25% of the center-f requency or a bandwidth of 1.5 GHz is called UWB. The frac tional bandwidth is given by

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59 L H L Hf f f f 2, (4.1) where fH and fL are the upper and lower frequencies at wh ich the power spectral density is 10 dB below the peak [48]. The center frequenc y is the average of fH and fL. UWB typically implemented w ithout a carrier has been driv en by the following trends in wireless communications [49]: 1. Ever increasing demands for higher bandwidths a nd data rates at lower cost as well as lower transmitted power compared to the cu rrently available wireless standards. 2. Re-use of the currently crowded wireless spectrum, especially between 900 MHz 5.4 GHz. 3. Increase in baseband and digital signal processing capabilities at lower die area as well as cost. Owing to their inherent broadband nature, UWB technology is consis tent with the first trend. This can also be deduced from the channel-coding theorem that states N S B C 1 log2 (4.2) where C is the channel capacity in bits/sec, B is the bandwidth in Hz and S/N is the signal to noise ratio [50]. To avoid interference to the existing standa rds using the same frequency spectrum, UWB systems cannot transmit large average power. UW B power emission restrictions on intentional and unintentional radiators in unlicensed bands are outline d in FCC Part 15 rules [48]. For midfrequency and high-frequency imaging systems operating between 3.1 and 10.6 GHz, the limit on average emitted power is -41.3 dBm measured over a 1-MHz resolution bandwidth. However,

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60 the limit on peak emitted power density is significantly higher and can go up to 0 dBm measured over a maximum resolution bandwidth of 50 MHz [51]. The second trend th at targets spectral reuse is also consistent with the UWB technology. Finally, the incr ease in functionality/die area with scaling of technology node has made it possible to use complex signal processing techniques that have made implem entation of UWB systems practical. 4.2.2 UWB Signaling Principles Currently, there are two competing standards for high data rate UWB applications. The first is termed Multi-band OFDM (orthogonal frequency division multiplexing) alliance (MBOA) [52]. This standard involves division of the 7.5 GHz UWB spectrum (from 3.1 10.6 GHz) into a maximum of 5 sub-groups and a to tal of 122 sub carriers. The sub-carriers are modulated using QPSK, and are generated usi ng high-precision fast Fourier transform (FFT) techniques. Multiple sub-carriers co-exist at the same time, giving a pseudo-UWB nature. The second standard involves transmission of Gaussian -shaped pulses (also termed as monopulses) in bursts or continuous streams. The work presented in this chapter is more relevant to the second standard. 4.2.3 Monopulse Based UWB The monopulses are naturally broadband in na ture and can be represented in time and frequency domain as [53] 2exp ) ( t t t v (4.3) and 2 2exp ) ( f f j f V (4.4)

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61 where is a time constant that determines the wi dth of monocycle and the center frequency fc (fc is proportional to 1/ ). Figure 4-1 shows a monopulse with fc at ~2 GHz and -10 dB bandwidth greater than 4 GHz. The fractional bandwidth ( ) is 1.6, which makes its UWB. Figure 4-1 Time and frequency domain repres entations of a 0.5-ns monopulse. Equivalent 10-dB bandwidth is greater than 4 GHz. An important observation is that there is no signal content at zero-frequency. This is critical for carrier-less communication due to the band-pass nature of transmitting and receiving antennas. Information is enc oded in pulse amplitude, position or phase. In a position based system, the pulse-to-pulse interval is vari ed on a pulse-by-pulse basis depending upon the information and pseudo-noise code. The pseudo-noise code is not used for spreading but instead for channelization and energy smoothing in the fr equency domain. Periodi c pulse trains produce energy spikes (comb lines) at regular intervals in the frequency domain that severely limit the maximum transmitted power. Rando mizing using pseudo-noise code evens out these regular spikes. The smoothing aspect of the pseudo-noise c ode can be seen in Figure 4-2(a) and (b). The code additionally improves the jamming resistance. Amplitude 0.0 Time (ns) 0.2 0.4 0.6 0.8 0.01.02.03.0 4.05.0 Frequency (GHz) Power (dBr) -50 -40 -30 -20 -10 0 0.5 ns 10-dB BW > 4 GHz

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62 Figure 4-2 Pulse train in time and frequency do main (a) before and (b) after randomization. Spectral smoothing of the comb lines is clearly observed. 4.2.4 Monopulse-based Carrier-less Transceiver A typical pulse-position monopul se-based transceiver is shown in Figure 4-3. In the transmitter, the data and pseudo-noi se code are encoded as a variable time delay. The resulting signal is Gaussian-pulse shaped before transm ission. Upon reception, the signal is correlated with a template before processing through a 1-bi t A/D converter (S/H) to decode the transmitted data. Template generation involves suitable shap ing of the same pseudo-random code without the data. The shaping at the re ceiver can be quite different compared to the shaping at the Time (ns) Amplitude Frequency (GHz) Power (dBr) -80 -40 0 0.01.02.03.04.0 5.0 -60 -20(a)Amplitude Time (ns) Frequency (GHz) Power (dBr) -40 0 0.01.02.03.0 4.0 5.0 -20(b)

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63 transmitter depending upon the nature of the antenna. Some of the significant challenges, however are that the transceiver requires a broadband antenna as well as very wide-band matching at the interface between the radiofrequency stage and the receiving antenna. Figure 4-3 Conventional car rier-less monopulse-based transceiver for UWB. Both of these issues can be greatly allevi ated as shown in Figur e 4-4 by upconverting the generated pulse-stream before transmission and subsequently down-converting upon reception. Resorting to an AM scheme for up and down conve rsion greatly simplifies the design and has the potential advantages of a high level of integration in addition to lower power consumption. Monopulse Correlation Template Generation Pulse Train Integration Compare to Zero Data Out Receiver Data in Monopulse generation Programmable time delay Clock oscillator Transmitter Code generation & Modulation

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64 Figure 4-4 Carrier-less monopulse-b ased transceiver for UWB w ith an RF subsection for up and down conversion of a baseband pulse stream. 4.3 System Architecture of AM Detector Figure 4-5 shows a block diagram and waveform s of the RF section. The up-converted AM signal can be single or double sided with or wit hout carrier suppression. A single sided system would have improved bandwidth efficiency at the co st of additional circuitry. The receiver picks up the signal, amplifies, filters and passes the signal to a detector that outputs the transmitted base-band signal. The signal is then processe d by a conventional UWB de-modulation circuitry to convert the pulse position modulated signals into a binary bit stream [56]-[59]. The power efficiency of transmitter is low due to the consta nt presence of carrier. The transmitted side band Data in Programmable time delay Clock oscillator Transmitter Code generation & Modulation RF-Transmitter sub-section Monopulse generation RF-Receiver sub-section Template Generation Pulse Train Integration Compare to Zero Data Out Receiver Monopulse Correlation

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65 power is significantly lower than the carrier power Since the carrier power must be less than the UWB emission limit, this lowers the range. Ho wever, by confining the frequency of carrier within the unlicensed 5.15-5.35 GHz or 5.725-5.825 GHz bands, the emission restriction for carrier can be greatly relaxed. The power efficien cy and range can also be dramatically increased using AM with carrier suppression in which no signal is transmitted duri ng the interval between pulses. Figure 4-5 RF transceiver with sample wavefo rms for operation withou t carrier suppression. The transceiver in Figure 4-5 implements a double sideband (DSB) type without carrier suppression. The carrier frequency is assumed to be 5.8 GHz. As mentioned, utilizing a DSB system circumvents the need for a synthesizer, mi xer, and drivers for local oscillator ports of mixers, which are major sources of power consumption. This lowers the power consumption of

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66 receiver. Figure 4-5 also shows the waveforms at different nodes of the transmitter and receiver. The receiver base-band circuitries are not include d. A concern for the architecture shown in Figure 4-5 is its susceptibility to interference from high amplitude in-band blockers. This issue can be alleviated to a large extent by targeting the system in environments that have restricted spectrum usage such as factorie s, power plants, industrial campus es, and forests as well as printed circuit boards [60]. 4.4 Circuit Description and Layout of AM Detector 4.4.1 Overview A circuit schematic of AM detector is shown in Figure 4-6. The dete ctor can be divided into two sections. The first is a two-stage re sistive feedback low noise amplifier (LNA) for providing wide-band gain and input match to 50. Figure 4-6 A schematic of the AM detector The second section consists of a half-wave r ectifier in shunt using 16 Schottky diodes each composed of 16 0.32 m x 0.32 m sub-cells, followed by a 5th order Chebychev low-pass filter for rejecting the carrier and other high order ha rmonics. Connecting the diode in shunt eliminates the impact of parasitic n-well to substrate junc tion capacitance to the circuit operation. Since the VDIODE VDD Section 1 mN1 mN2 mP1 mP2 Rf1 Rf2 CDC CDC CBYP CBYP CC mSBD C1 C3 C5 L2 L4 Section 2 vin vout RBIAS

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67 substrate resistance of parasitic junction is bypassed, the circu it characteristics can be more accurately simulated. Furthermore, the intrin sic diode capacitance can be absorbed into C1 of the low-pass filter. This simplifies cascading the LNA and rectifier-filter combination using a coupling capacitor (Cc). Both the LNA and the filter sections are matched to 50 at their respective inputs and outputs. The input and out put connections for detector are made using signal-ground probes. The DC biases for the LNA and rectifier are provided using a 4-pin DC probe. 4.4.2 Two Stage LNA Design The two stage resistiv e feed-back amplifier [61]-[65] in Figure 4-6 bi ases by itself. The bypass capacitors are formed using MOS capacitors in n-wells [39], [66]. Besides providing wide-band gain and input match to 50, this stage improves the sensitivity of detector by reducing the impact of signal-to-noise ratio degrada tion in the rectifier and filter. This stage also helps to isolate the section wh ich handles the signals at freq uencies between 3 and 10 GHz and the one that handles signals at frequencies betw een dc and 1.7 GHz. Without this, achieving flat gain and match over the band of interest for additional tuned amplifier and filter that may precede the detector is challenging since the input impedance of low pass filter deviates significantly from 50 at frequencies above ~2.5 GHz. The channel length of transistors is 120 nm and the widths for mP1 and mN1 are 92 m, while those for mP2 and mN2 are 96 m. The feedback resistors Rf1 and Rf2 are 150 and 330 and implemented using the conventional p+ polysilicon gate layer. 4.4.3 Half-wave Rectifier/Filter Design To simplify testing, the di ode in half-wave rectifie r is biased through a 5-k polysilicon resistor thus eliminating the need for an external bias-tee. It is AC coupled to the LNA for DC

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68 isolation. In complete systems, the diodes can be biased using conventional MOS current mirror. The filter is designed using the standa rd design tables for low-pass filters [67] and is frequency scaled to have a 3-dB bandwidth of ~1.7 GHz. A Chebychev configuration is chosen because of its higher roll-off near the cut-off frequency. The number of diodes, mSBD and bias current (IDIODE) of Schottky diode in Figure 4-6 are set by maximizing the de tected signal power at the output. The simulated output power (Pout) of the detector as function of diode bias is shown in Figure 4-7. Figure 4-7 Simulated output power as function of diode bias current. Input side band power, Pin is -40 dBm. Figure 4-8 shows examples of AM wavefo rms at the input and envelope-detected waveforms at the output. The input to the circu it is an AM signal centered at 5.5 GHz having sidebands at 1 GHz away on either side for mSBD of 16. The frequency of 5.5 GHz is chosen because it is about half way between 5.15 and 5.825 GHz. The gain is maximized when the diode bias current is 0.5 mA or diode voltage is 280 mV. At lo w diode current levels, the downconverted output volta ge increases with IDIODE, since the change of diod e current due to an input voltage swing increases with IDIODE [26]. The output voltage decr eases for diode bias voltages 50 46 42 0 1 2 54 50 46 42 0 0.5 1 1.5 2 Pin = -40 dBm mSBD = 16 Pout (dBm) IDIODE (mA)

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69 larger than 280 mV due to an incr ease in the drop across the diode series resistance. As will be discussed in section 3.5, these behavior s are seen in the measurement results. Figure 4-8 Input and out put waveform examples. The simulated output power as a function of mSBD is shown in Figure 4-9. The input to circuit is again an AM signal centered at 5.5 GH z having sidebands at 1 GHz away on either side with the diode bias voltage set at the op timal value of 280mV. From Figure 4-9, mSBDs between 12 to 16 give maximum output. For low mSBDs, increasing mSBD increases IDIODE and raises the output voltage. For high mSBDs, because the diode voltage is kept constant, increasing mSBDs raises the diode current, which eventually makes the diode junction impeda nce comparable to the load (filter input) it drives. This results in a dr op of AM input signal ac ross the diode which in turn leads to the dr op in output voltage [18],[26]. The mSBD value of 16 is chosen. This results a larger capacitance contribution from the diode to the filter input s ection and therefore reduces the magnitude of additional capacitanc e needed. The coupling capacitor (Cc) value is 1 pF with parasitic capacitance of 200 fF The parasitic capacitance is also absorbed into C1 of the filter. 0.0 0.5 1.0 2.0 -10 0 10 20 -20 0.0 0.5 1.0 1.5 2.0 -1.5 0.0 1.5 3.0 -3.0 Vin (mV) Vout (mV) Time (ns) Time (ns) 1.5

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70 Figure 4-9 Simulated output pow er as function of the num ber of parallel SBDs (mSBD). Input side band power, Pin is -40 dBm. The following are the values of components used in the second section of the detector: m-SBD = 16, C1 = 700 fF, L2 = 5.36 nH, C3 = 2.65 pF, L4 = 5.36 nH, C5 = 820 fF, RBIAS = 5 k and IBIAS = 0.3 mA. The deviation of C1 from that in the filter table translates into ripples in the passband. From simulations, a deviation of 400 fF in C1 yields .4 dB ri pples in the pass band, which should be tolerable. Because of this, C1 is implemented exclusively using the parasitic capacitances. The inductors are implemented using the top metal layer (Metal 8) and off set by 45 degrees to minimize the mu tual inductive coup ling between them [68]. All the capacitors are metal-insulator-metal structures formed using metal layers 5-8. Using metalinsulator-metal capacitors lessens the possibility of capacitance varying with large signal levels especially at the output of LNA, as in MOS capacitors. 4.5 Measurement Results and Disc ussions of AM Detector 4.5.1 LNA, Diode Detector and Filter Results The measured LNA |S-parameters| are shown in Figure 4-10. The |S21| plot indicates relatively flat gain over 0.5 to 4 GHz with a 3-dB frequency of 6.8 GHz. The |S11| and |S22| mSBD 52 48 44 40 0 10 20 30 40 Pin = -40 dBm VDIODE = 280 mV IDIODE = 400 A Pout (dBm)

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71 curves in Figure 4-10 indicate reasonable matc hing almost up to 10 GHz. Reverse isolation is greater than 28 dB over the band of interest (3 10 GHz). The noise figure of LNA is 7.4 dB over the frequency range between 0.5 and 7.0 GHz. Figure 4-10 Measured LNA ma gnitudes of S-parameters. The filter frequency response is shown in Figure 4-11. The pass-band loss is ~4 dB resulting primarily from the losses in induc tors. A combination of field (FastHenry) [69] and circuit simulations indicates that the loss can be reduced to ~2 dB by in creasing the metal width of inductors from 2.7 m to ~7 m. Figure 4-12 shows that the magnitudes of input and output reflection coefficients of the diode detector and low pass filter combination are less than -10 dB up to 10 and 1.7 GHz, respectively, once ag ain indicating good matching. The amplifier consumes 8.3 mW from a 1.2-V supply. -35 -30 -25 -20 -15 -10 -5 0 2 4 6 8 10 Frequency (GHz) 0 2 4 6 8 10 |S-parameters| (dB) S-parameters (dB) |S21| |S12| lS11l |S22|

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72 Figure 4-11 |S21| of 5th order Chebychev filter. Figure 4-12 Measured magnitudes of S-parameters for the diode detector and low pass filter. A photo-micrograph of the detector circuit is shown in Figure 4-13. A layout of the 16 parallel connected SBD struct ure consisting of 16 0.32x 0.32 m2 diodes with connections for biasing is also shown in Figure 4-13. The total diode area with all th e diode n-wells merged together is 50 x 80 m2. The LNA occupies an area of 50m 70m by itself. The filter -50 10 -40 -30 -20 -10 0 0 2 4 6 8 Frequency (GHz)|S21| (dB) f3-dB ~ 1.7 GHz 0 -25 -20 -15 -10 -5 0 2 6 8 10 Frequency (GHz) 4 lS11l lS22l |S-parameters| (dB)

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73 consumes no power and occupies an area of 270m 370m. The entir e detector occupies 440m 740m. Figure 4-13 A photo-micrograph of the detect or and a layout of 16 SBDs in parallel. 4.5.2 Overall Detector The AM input and de-modulated output wavefo rms and spectra when the input power of sideband is -44 dBm (carrier power of -22 dBm) are shown in Figure 4-14. These plots demonstrate that the AM detector has recovered the envelope, and remove d the carrier and other harmonics. The output power (Pout) versus bias current (IDIODE) plot for input signal with a 5.5GHz carrier (fcarrier) amplitude modulated by a 700-kHz sine wave (fmod) at modulation depth of 20% is shown in Figure 4-15(a). The input side band power level (Pin) is -42 dBm which is ~ 22 dB below the carrier power. The output power increas es with bias current due to the increase in current change with input voltage; however, at high current levels, Pout falls possibly due to the C 3 L 4 L 2 C 5 C c SBD 740 m DC p ads for bias LN A 440 m 80 m60 m 8 SBD cells 8 SBD cells RF si g nal p ath DC bias from R BIAS Schottky Schottky n-terminaln-terminal

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74 effects of series resistance described earlier. The peak output power is achieved in the bias current range between 0.2 to 0.6 mA or di ode voltage of ~ 250 to 300 mV, which are in agreement with the simulations. Figure 4-14 Input signal seen on (a) spectrum analyzer, (b) an oscilloscope and output signal (700 kHz, 1.4 s) seen on (c) a spectru m analyzer, and (d) an oscilloscope. Figure 4-15(b) shows an output power versus the carrier frequency. Pout drops at frequencies greater than 4 GHz because of the LNA |S21| roll-off. Between 4 and 7 GHz, the gain decreases by ~ 4 dB. The gain drops at freque ncies lower than 2 GHz due to the high-pass filtering effect of coupling capacitor (Cc). Figure 4-16(a) shows an output power versus input side band power plot. The input signa l is once again a 5.5-GHz carrier (fcarrier) amplitude modulated by a 700 kHz signal (fmod) at modulation depth of 20%. At low input signal levels (sideband power less than -36 dBm), the detector operates in the square-law region. For larger inputs, the diode functions in th e linear region with a slope of 1 decade/decade. This can be observed in Figure 4-16(a) when the input side-b and level is greater than -30 dBm. For input vin (mV) -25 -50Pin (dBm) -30 -10 5.499 5.501 Frequency (GHz) -70 -50 -110 -90 5.500 25 50 0 0 4 Time (ns) 1 2 3 Pout (dBm) -45 650 750 Frequency (kHz) -65 -105 -85 700 Vout (mV) -6 -12 6 12 0 0 4 Time (ns) 1 2 3 fcarrie r = 5.5 GHz 700 kHz 700 kHz fmod = 700 kHz 1.4 s(a) (b) (c) (d)

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75 power levels greater than ~-20 dB m, the LNA starts to compress, which results in clipping of the AM signal. As a result, the amplitude informati on in the side-band is compressed which results in a drop in Pout as well as conversion gain (Figure 416(a) and (b)). The square law region (slope of 2) from the curve indicates an input dynamic range larger than 35 dB [17], [70]. Figure 4-15 Output power vs. (a) bias current and (b) carrier frequency. If higher modulation index were utilized such th at the difference betwee n the carrier and side band power is lowered, the dynamic range would be higher. Figure 4-16(b) shows the conversion gain versus input side band power. The peak conver sion gain is ~ -2.2 dB which occurs when the input power is ~ -30 dBm. -80 -70 -60 -50 -40 2 46 8 10 -80 -70 -60 -50 0 0.2 0.40.60.8 1 Pout (dBm) Pout (dBm) IDIODE (mA) fcarrie r (GHz) fcarrier = 5.5 GHz fmod = 700 kHz Pin = -42 dBm IDIODE = 300 A fmod = 700 kHz Pin = -42 dBm(a) (b)

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76 Figure 4-16 (a) Output power and (b) c onversion gain vs. input side-band power. To estimate the smallest signal the detector can successfully demodulate and hence the sensitivity, the output noise power spectral de nsity between 10 MHz and 1.8 GHz is measured. The measured noise density integrated over th e 1-ns monocycle bandwidth corresponds to the total noise in the down-converted band. To limit the bandwidth, the low pass filter in the detector should be replaced with a band pass filter. This output noise power can be referred back to the input to specify the sensitivity of the system. The measurement setup for estimating the noise performance is shown in Figure 4-17. The noise is measured using a spectrum analyzer after amplifying the noise genera ted by the detector. A 50termination at the input of the detector is used as the white noise source. -40 -30 -20 -10 0 75 65 55 45 35 25 15 -110 -90 -70 -50 -30 75 65 55 45 35 25 15 IDIODE = 300 A fmod = 700 kHz fcarrier = 5.5 GHz IDIODE = 300 A fmod = 700 kHz fcarrier = 5.5 GHz Pout (dBm) Pin (dBm)Conversion gain (dB) Pin (dBm)(a) (b)

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77 Figure 4-17 Noise measurement setup. Figure 4-18 shows the measured outp ut noise spectral density at IDIODE of 0.3 mA. A lower DC bias for the diode is preferred to reduce th e shot noise added by the diode. The integrated output noise power over the 1. 0-GHz band ( 500 MHz) cent ered around 1 GHz corresponding to the 3-dB bandwidth for a 1-ns UWB monocycle pulse is ~ -76dBm. Us ing Figure 4-15(a), the corresponding input referred noise power is ~-54dBm which is the sum of kT (dB), Noise Figure (NF), and Bandwidth (dB). For the 1-GHz bandwidth previously described, NF is ~30 dB. For a data rate of 100 Mbps (bits per second), the proc essing gain (PG) of the system for a 1-GHz wide UWB monocycle is 10 dB. An Eb/No of 6 dB (bit error rate of 10-2 for ASK) [71] would translate into a minimum required signal to noise ratio (SNRdB) of ~-4 dB (SNRdB + PGdB = Eb/NodB). This results in a required signa l output power level of -76 dB m 4 dB = -80 dBm. Referring back to the input of detector using Figure 4-16 (a), the corr esponding input power level is -56 dBm for the signal with a 5.5GHz carrier. Th is input sideband power of ~-56dBm is the sensitivity of this detector. For the signal with a 9-GHz carrier, from Figure 4-15(b), the sensitivity is ~ -53dBm. Input SG probe 50 DUT Bias Source 4-pin DC probe Output SG probe External Amplifier Spectrum Analyzer Input SG probe Input SG probe 50 50 DUT Bias Source Bias Source 4-pin DC probe 4-pin DC probe Output SG probe Output SG probe External Amplifier External Amplifier Spectrum Analyzer Spectrum Analyzer

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78 Figure 4-18 Measured output noise power spectral density. By including additional 20-dB gain in the LNA, NF of the system can be reduced from ~30 dB to ~10 dB (neglecting the noise of the additional amplification stages). With this added gain, the plot in Figure 4-16(a) would shift towards the left by 20 dB. Maintaining the same output power level of ~-80 dBm, the sensitivity would be improved to ~ -76dBm. This is approaching that needed for MBOA receivers, though this ty pe of AM detectors is not well suited for MBOA applications. Table 4-1 summarizes the link an alyses for a 5.8 GHz system that can support a data rate of 100 kbps at range of 30m. The transmitting a nd receiving antenna gains are assumed to be 0 dBi and the path loss is proportional to 1/R2, where R is the antenna separation. The required signal to noise ratio is ~-34 dB (SNRdB + PGdB = Eb/NodB). The required signal output power level is -110 dBm. The sensitivity with the 20-dB additional gain is -93 dBm (-73 dBm from Figure 4-16(a) + 20 dB shift). With transmitted ca rrier power of -6 dBm and modulation index of 100%, the transmitted side band power is -12 dBm. This is less than the maximum permissible power of -11.48 dBm as per FCC Part 15 limits The propagation loss at 5.8 GHz is 77 dB. The -158 Noise (dBm/Hz) Frequency (GHz) -162 -166 -170 0 2.0 0.5 1.0 1.5 Shaded area ~ -76 dBm IDIODE = 300 A

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79 received power is -89 dBm, which is 4 dB above sensitivity level. Including 2-dB implementation loss, the system has link margin of 2 dB. The link margin can be increased by reducing the data rate or range. Table 4-1 Link margin analysis for UWB detect or with 100 kbps data rate and 30m range. The required signal to noise ratio is ~-34 dB (SNRdB + PGdB = Eb/NodB), where Eb/NodB= 6 dB for 0.01 BER. The required signal output power level is -110 dBm. The sensitivity with the 20-dB additional gain is -93 dBm (-73 dBm from Figure 4-16(a) + 20 dB shift). Parameter Value Unit Center frequency 5.8GHz Bandwidth 1GHz Data rate 100kbps Range 30m Transmitted side band power (Pt) -12dBm Transmitter (TX) and receiver (RX) antenna gain + antenna loss (A) 0 dB Free-space path loss ( /4 R)2 (L) 77dB Received power (Pr = Pt L) -89dBm Input sensitivity (S) -93dBm Minimum Eb/No 6dB Implementation loss (I) 2dB Link margin (LM = Pr S I + A) 2dB 4.6 Conclusions Applicability of the Schottky diodes fabri cated in a foundry CMOS technology has been demonstrated by implementing an UWB AM de tector that down-converts a UWB signal upconverted to the frequencies between 3 and 10 GHz. The detector provides adequate 50input and output match over dc-10.3 GHz and dc-1.7 GHz, respectively, and consumes 8.5 mW of power. The sensitivities over the band range between -53 to -56 dBm. The Schottky diodes should allow implementation of new types of UW B receivers which do not require a synthesizer and a conventional mixer.

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80 CHAPTER 5 SYSTEM DESIGN OF WIRELESS INTERCO NNECTS ON AN INVERTER PRINTED CIRCUIT BOARD 5.1 Introduction Schottky diode detectors should be applicab le for communication systems operating at frequencies higher than 10 GHz. In order to demons trate this, use of diode detectors for wireless interconnection in the inverter board of hybr id vehicles operating between 15-20 GHz is investigated. In recent years, automobile manufacturers have successfu lly deployed hybrid electric vehicles (HEV) with radically improved fuel e fficiency and reduced emission of harmful airborne particles. The HEVs achieve this by dy namically switching between gasoline-powered and battery-operated modes depending upon the vehicle load. The batteries are charged by regenerative conversion of the ki netic energy while breaking, into electricity. This is especially beneficial with the possibility of fossil-fuel becoming scarcer in future [73]. To achieve high efficiency, design of the interface between the gasoline-powered and electrical control sections is of great importance [74]-[76]. With both high-power (>300 V) and low-power (~ 12 V or less) control circuits co-existing on the control board within a HEV, design of interface between the tw o is of particular challenge. Figure 5-1 shows the prototype of an i nverter board. Not shown in the figure is the metal casing that encloses the board. Tw o major control nodes (herein called deadtime controllers) located towards the middle of the board transmit and receive phase information from a motor on each side. Also, there are two additional nodes on either side that transmits the motor temperature to the deadtime controller. The cont rol nodes operate at low voltage and the motor sections function at voltages greater than 300 V. A key requirement is isolating the return paths for the low voltage and high voltage sections. In curren t designs, the ground is isolated by using

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81 photo couplers that separate the input from the output, thereby fl oating the two. With the use of more than 10 of these per boa rd, the cost is an issue. Figure 5-1 Prototype inverter boa rd that goes into a HEV. N1 and N2 communicate with N3N8 and N9-N14 respectively. (Courtesy of Toyota) A potential way for reducing th e cost, footprint and latency while increasing the data-rate is using wireless interconnects. By suitably c hoosing the operating freque ncy, the interconnects can also provide additional isolation from the inverter board noise. The wireless interconnects are required to operate in full duplex mode and provide the same ease of use as a photo coupler. This chapter evaluates one of the possible ways in which wireless interconnection can be incorporated for the inverter boa rd to address the issues men tioned above. A data rate of 50 Mbps/channel, latency less than 2s and a range of up to 15 cm are the design targets. Conditions and concerns relevant to the inverter board and wireless scheme are translated into N2 N1 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N1, N2 Deadtime controller nodes N3-N14 Motor nodes 15 cm 25 cm

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82 system requirements. System design and simu lation results demonstrating its operation are presented. 5.2 System Setup Out of the three widely utilized multiple access schemes, namely time (TDMA), frequency (FDMA) and code (CDMA) division multiple access, CDMA with 8 possible orthogonal channels is used for the forward link from th e deadtime controller to each of the six nodes controlling the motor phases. For a data rate of 50 Mbps, spreading by a factor of 8 results in a chip rate of 400 Mcps (Mega chip s per second). For the reverse li nk, an FDMA scheme is used. This idea is illustrated in Figure 5-2. Each of the two deadtime controllers has one CDMA transmitter (TX) and seven FDMA receiver (RX) channels while a motor has one FDMA TX and CDMA RX. TX and RX for the deadtime controller as well as the motor nodes are intended to be on the same chip. Figure 5-2 Signaling scheme for th e forward and reverse links. For a square wave, ~80% of the signal energy is located within the first 3 harmonics. As a result, the baseband bandwidth for the FDMA and CDMA links are set at three times the data and chip rates, respectively. With the RF bandw idth being twice the bandwidth at baseband for an AM system [78], RF bandwidths of 2.4 GHz for CD MA and 300 MHz for FDMA have been allocated. The frequency plan for one side of the inverter board (N1 communicating with N3-N8

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83 in Figure 5-1) is given in Table 5-1. The frequency plan is sim ilar for the other side with the CDMA and FDMA links spanning from 18-20. 4 GHz and 29-31.8 GHz respectively. Table 5-1 Frequency plan for one side of the inverter board. TX Channel Freq. Band RX Channel Freq. Band Chip Motor 1 24.2-24.6 1 15.6-18, C1 1 2 24.6-25.0 2 15.6-18, C2 2 3 25.0-25.4 3 15.6-18, C3 3 4 25.4-25.8 4 15.6-18, C4 4 5 25.8-26.2 5 15.6-18, C5 5 6 26.2-26.6 6 15.6-18, C6 6 7 26.6-27.0 7 Deadtime controller 1 15.6-18, C1 1 24.2-24.6 1 2 15.6-18, C2 2 24.6-25.0 1 3 15.6-18, C3 3 25.0-25.4 1 4 15.6-18, C4 4 25.4-25.8 1 5 15.6-18, C5 5 25.8-26.2 1 6 15.6-18, C6 6 26.2-26.6 1 7 26.6-27.0 1 In Table 5-1, C1-C6 represent six of th e eight possible orthogonal chip sequences and hence channels for the CDMA link. The moto r nodes extract their information from the transmitted comprehensive CDMA signal by correla ting with their respective codes. A chip sequence of one is indicated in th e last column for the FDMA scheme to indicate the absence of any coding. Since both TX and RX are co-located on the same chip, the separation greater than 6 GHz between the TX and RX bands is used to improve isolation. A block level representation of the transceivers at the deadtime controller and mo tor nodes with a frequency plan consistent with Table 5-1 is shown in Figure 5-3.

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84 Figure 5-3 System block diagram of transceive rs for the deadtime controller and motor nodes for the frequency plan in Table 5-1. Coder LPF Frequency Divider VCO PLL Digital Clock 4.8 GHz LOR 24 GHz LOT 12 GHz BPF Duplexer Filter 24.2 GHz LNA Duplexer Gain ~ 12 dB 2.8 GHz Bandwidth RF Amplifier Gain ~ 15 dB 15.6 GHz LPF Baseband Amp LPF LPF 400 MHz 800 MHz 2.8 GHz Baseband Amp Baseband Amp IF Amp 1.6 GHz G ~ 8 dB LOR 24 GHz TX chains RX chains Data to Deadtime controller Crystal Reference Data from Deadtime controller Chip boundary LPF VCO PLL Frequency Divider Duplexer Filter BPF LPF Envelope Detector 3-bit ADC Decoder ADC Clock Clock/Data Recovery 15.6 GHz LNA Duplexer Gain ~ 12 dB RF Amplifier Gain ~ 15 dB Baseband Amplifier 24 GHz or others Data from Motor Frequency select CDMA channel select Data to Motor TX chain RX chain Chip boundary BPF Buffer Buffer Buffer Transceiver at M otor Transceiver at deadtime controller

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85 In the transmitter of a deadtime controller, the data for the six motor nodes are encoded using the respective orthogonal codes before comb ining to form the multi-level CDMA signal. This operation is performed by the code r which is given in Figure 5-4. Figure 5-4 Coder in the deadtime controller. The data element could be either a flip-flop or a read only memory (ROM). The multi-level signal is then up-converted to a 16.8 GHz carrier that is generated by mixing single-tone 12 and 4.8 GHz signa ls from the PLL. The RX has a common broad-band RF stage that amplifies the 7 FDMA signals (6 motor and 1 temperature control node) spanning from 24.2 27 GHz. Filters having the same bandwidth and frequency range reject other out-of-band signals. The FDMA signals are next down converted to the first IF of 1.6 GHz. Signals in each of the FDMA bands are then extr acted by parallel mixing with 7 carriers ranging from 400-2800 MHz. An RX of the motor nodes receives and am plifies the 2.4-GHz wide CDMA signal centered at 16.8 GHz that is transmitted by the deadtime controller. Similar to the RX in a deadtime controller, filters centered at 16.8 GHz spanning 2.4 GHz reject spurious out of band components. The signal is next rectified, low-pass filtered and amplified to recreate the baseband multi-level CDMA signal. A 3-bit ADC conve rts the multi-level CDMA signal into its equivalent 3-bit representation. To decipher the data for each motor from the multi-level signal, XNOR 6x8 data element having 6-channel 8-chip code information Chipcombiner Clock @ 400 MHz Data <0:5> @ 50 MHz Coder

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86 the 3-bit data from the ADC is correlated with the corresponding code. The correlation operation is accomplished using a decoder. A more detailed block diagram of the baseband section of a motor node is shown in Figure 5-5. Figure 5-5 Block diagram of ba seband section of a motor node. The multi-level CDMA signal is limited to capt ure the data transitions and passed on to a clock and data recovery (CDR) ci rcuit to reconstruct the clock. This serves the dual purpose of providing the clock for the ADC and reference for the motor node TX. The TX modulates the data from the motor node on to a carrier whose center frequency is pr ogrammable between 24.4 26.8 GHz depending upon the motor node location. Such a wireless interconnection system has potential advantages: CDR 3-bit A DC Limiter Peak Detector 8-chip Walsh code generator Multi-level CDMA data from baseband amplifier Clock Recovered Clk @ 400 MHz Data Out 6b registe r Data Clock @ 50 MHz 1b 3b 3b 6b From A DC From Walsh code g enerato r Data Out 6b registe r Decoder

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87 By using FDMA for the link from the motor node to the deadtime cont roller, the near and far, and synchronization problems of CDMA signals is eliminated [79]. These problems arise in a CDMA scheme due to the signals from each of the motor nodes having inconsistent power as well as phase at the deadtime controller RX because of being located at varying distances. TX to RX isolation is improved by approximate ly 6 dB due to increased noise immunity resulting from the spreading involved in CDMA. Only one transmitter is needed at the dead time controller to support six channels thus reducing RF circuitry. Furthermore, most of th e RF section including the PLL can be shared by the seven RXs, thereby increasing circuit re-u se. The corresponding CDMA TX power amplifier however needs to be linear resulti ng in increased power consumption, At the motor node, the filtering requirement is relaxed (300 MHz ve rsus 2.4 GHz) over a system that uses FDMA for the link from the de adtime controller to the motor node. This is due to the channels being separated in codes inst ead of frequency. Also, each of the motor nodes could potentially use the same chip that has a programmable frequency and CDMA code setting for the TX and RX respectively at the motor node. The detector based CDMA receiver at the motor node does not require mixers, or PLL which drastically reduces power co nsumption. The recovered clock from the CDR can be used as the frequency reference for the FDMA transmitter in each of the motor nodes thereby eliminating the need for a separate refere nce source for each motor node. The link analyses for a single channel on the CDMA and FDMA links for a maximum distance of 15 cm is summarized in Table 5-2. Eb/No is 14.5 dB for AS K modulation with 1X10-13 BER [71]. An on-chip antenna on a 100m thick substrate with loss of 7 dB is assumed. To evaluate the poorest link margin, pr opagation loss is calculated at the highest possible frequency

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88 of 32 GHz for the system proposed. Even for th ese worst case conditions, link margins greater than 16 dB is possible for the CDMA and FDMA links. Table 5-2 Link margin analyses for the CDMA and FDMA links. CDMA FDMA Range (R) 15 cm Range (R) 15 cm TX power/Channel (Total power ~ 10 dBm) 2 dBm TX power 3 dBm Propagation Loss @ 32 GHz ( /4 R) 2 46 dB Propagation Loss @ 32 GHz ( /4 R) 2 46 dB Antenna Gain (0.25 = 3.2 mm) 7 dB Antenna Gain (0.25 = 3.2 mm) 7 dB Received power -58 dBm Received power -57 dBm Thermal Noise [kT (oK)] -173.8 dBm/Hz Thermal Noise [kT (oK)] -173.8 dBm/Hz Bandwidth (50 MHz) 77 dB Bandwidth (50 MHz) 77 dB Eb/No for BER of 1x10-13 for ASK 14.5 dB Eb/No for BER of 1x10-13 for ASK 14.5 dB RX noise figure 8 dB RX noise figure 8 dB Sensitivity -74.3 dBm Sensitivity -74.3 dBm Link margin 16.3 dB Link margin 17.3 dB 5.3 Concerns, Design Considerations and Translation to Block Level Parameters As with any wireless system, the require ments outlined in the link analyses and architectural scheme must be converted into design parameters of the blocks, which includes duplexer, low noise amplifier (LNA), inter-stage amplifier (IA) and band-pa ss filter (BPF) that are common to the RXs at both deadtime cont roller and motor nodes (although at different frequency bands) and specific blocks such as the analog to digital converter (ADC) (motor node), mixers and local oscillators (deadtime cont roller node). Further, additional features specific to the setup also ha ve to be accounted for while deriving the block parameters. 5.3.1 Synchronization Before normal operation of the RX at motor no des, two synchronization steps have to be accomplished. First, the CDR has to be locked to transitions in the incoming multi-level CDMA

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89 signal (herein called clock synchronization). Clock synchronization is imperative for proper data sampling at the ADC and providing a stable reference frequency to the motor node TX. Second, the 8-chip orthogonal code generator at each moto r node has to be aligned to the sequence at the deadtime controller CDMA transmitter for proper correlation. This data-level synchronization is not the same as clock synchroni zation and is more complex. Th e following case study would put this issue in perspective. Six orthogonal code sequences, one for each CDMA channel is shown in Equation 5.1. The sequence is transmitted as such for data in a particular channel and flipped for data With data 0 and being transmitted in channels 1, 2 and 6 and channels 3, 4 and 5 respectively, a snapshot of the signal from each ch annel within the data period of 20-ns is shown in Figure 5-6(a). The comprehensiv e CDMA signal, depicted in rela tive scale in Figure 5-6(b) is the sum of the signals from each individual channe l. While extracting the data at the motor node RX, the total CDMA signal is corr elated with the code correspondi ng to the particular channel. Figure 5-7 shows the result of correl ation for channel 3 without and with misalignments. A correlation maximum and minimum of 4 and -4 in dicate data or respectively. A correlation maximum is achieved for the cases with no misalignment, 3, 4 and 7 chip misalignments. If the RX were synchronized to a wrong chip sequence, subsequent correlations would then occur with a code that is different from the one speci fic for channel 3. This would 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 (5.1)

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90 result in data misinterpretation. For proper correlation, the starting point of chip sequences at the RX and transmitted comprehensive CDMA signal have to be aligned. Figure 5-6 (a) 8-chip signal from each channe l within the data period of 20-ns and (b) Comprehensive CDMA signal in relative scale. The multiple maximum correlations are due to the channel 3 being similar to the channels 2, 5 and 6 except for a shift. The probl em can therefore be alleviated by correlating with a code that is least similar to the other five, to initially align the chip-sequence. The respective codes can then be aligned and loaded once the alignment is achieved. Of the six codes in Equation 4.1, channel 1 and channel 4 codes are least similar to the other four. Channel 1 code is however not suitable again since it woul d result in maximum co rrelation for every other misalignment. As a result, channel 4 is the best for synchronization. Chip Number 1 2 3 4 5 6 7 8 Data period: 20 ns Chips flipped for data Relative magnitude 0 1 2 3 5 6 4 Data period: 20 ns (a) (b)

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91 Figure 5-7 Correlation of tota l CDMA signal with channel 3 code without and with misalignments. Correlation of the complete CDMA signal w ith channel 4 code without and with misalignment is shown in Figure 5-8. The maxi mum and minimum values are achieved for no misalignment and 4-chip misalignment cases, resp ectively. If the data transmitted was unknown, there would still be uncertainty in synchronization. As a result, a predetermined pilot sequence of data s or s have to be transmitted to ensure proper synchronization. If the synchronization were done serially, the maximum duration for th is synchronization is set by the worst-case misalignment of 7 chips and require seven da ta periods of 140 ns for synchronization. 5.3.2 Multi-path A concern for the use of CDMA is the effects of multi-paths that occur in closed systems such as the inverter board in Fi gure 5-1. Multi-path effects caus e small-scale fading resulting in spreading of the received signal. Time-delay m easurements for the inverter board as part of another dissertation indicate a maximum excess delay of approxi mately 1ns over a range of 15 Relative magnitude 0 1 2 3 5 6 4 Data period: 20 ns Channel 3 code Relative correlation sum -3 -2 -1 0 2 3 1 Number of chips misalignment 4 -4 0 1 2 3 4 5 6 7

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92 cm (15 cm being the maximum possible dist ance between a deadtime controller and its corresponding set of motor nodes) [80]. This value is less than the CDMA signals chip period of 2.5 ns (1/8th of the 20-ns data period co rresponding to a 50 Mbps si gnal). Extensive research and simulations have to be conducted to fully evaluate this. Figure 5-8 Correlation of tota l CDMA signal with channel 4 code without and with misalignments. The maximum sum is possible only for the case with no misalignment. 5.3.3 LNA and Duplexer For the transceivers at the deadtime controlle r and motor nodes, both TX and RX co-exist on the same chip. In a full-duplex scheme of opera tion, both TX and RX operate at the same time with both sharing the same antenna In the absence of any filteri ng, the full TX si gnal (~ 5dBm) appears at the receiver input completely saturati ng the LNA. This issue se ts the requirement for the duplexer filter and the LNA compression point. Greater than 30 dBr rejection of the TX signal at the LNA input reduces the magnitude to -25 dBm. As a consequence, an input 1-dB compression point (IP1dB) of -20 dBm for the LNA gives a 5-dB margin for the amplifier to work Relative magnitude 0 1 2 3 5 6 4 Data period: 20 ns Channel 4 code Relative correlation sum -3 -2 -1 0 2 3 1 Number of chips misalignment 4 -4 0 1 2 3 4 5 6 7

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93 without compression. The constraint on IP1dB is not strict because it is conventionally defined for in-band signals. As a consequence, the margin in the linearity specification is expected to be larger. However, in the current system both TX and RX are broad-band and the rejection at the TX frequency band for the receiver is not hi gh (~ 7 dB). Plots of the duplexer filter characteristics at the CDMA and FDMA nodes are shown in Figure 5-9. The duplexer filters have an in-band loss of 3 dB and have greater than 30 dB rejection at the respective TX band edges. Figure 5-9 Characteristics of duplexer filters at (a) motor nodes and (b) deadtime controller. 5.3.4 Inter-stage Amplifier (IA) and Band-Pass Filter (BPF) In mainstream CMOS, where the substrates are conductive (20 -cm), the high amplitude TX signals can also couple through the substrat e and interfere with the receiver operation by saturating the LNA, gain and mixing stages. Th e substrate-coupled signa ls also degrade the receiver performance by introducing additional sp ectral components. The effects are similar to that in section 5.3.3 with the difference only in the coupling mechanism. With an assumption of ~30-dB substrate-isolation between the TX and RX, the TX signal strength is ~ -25 dBm at the receiver nodes. This sets the IP1dB linearity specification of -20 dBm for the amplifier stage. Measurements are required to validate the assumption on substrate isolation. The intermediate 15 17 1921 23 2527 0 -20 -40 -60 ~ -3 dB in-band ~ -35 dBr @ 24 GHz Frequency (GHz) |S21| (dB) 0 -20 -40 -50|S21| (dB) 13151719 21 23 Frequency (GHz) 25 ~ -33 dBr @ 18 GHz ~ -3 dB in-band (a) (b)

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94 stage amplifiers in the FDMA RX at the deadti me controller node have a 5-dB higher linearity requirement to account for the larger power in the TX multi-level CD MA signal. Additional band-pass filter (BPF) stages are inserted in between the gain stages to further reduce the impact of the coupled TX signals. Figure 5-10(a) and (b) plot the gain (including the LNA) and intermediate BPF characteristics at th e motor and deadtime controller nodes. Figure 5-10 Amplifier and BPF characteristics at (a) Motor and (b) deadtime controller nodes. The characteristics are similar except fo r the difference in frequency bands. The filters and the amplifiers have a larger 3-dB bandwidth (3.5 GHz compared to 2.4 and 2.8 GHz) to account for process variations. The LNA and amplifying stages have a gain and noise figure (NF) of 15 dB and 6 dB. Since the LNA gain and NF primarily set the noise figure of the entire receiver [82], an LNA with 6-dB NF and 15 dB gain should be sufficient to satisfy 13.6 15.6 17.6 19.6 15 13 11 9 Frequency (GHz)|S21| (dB) 7 BW ~ 3.5 GHz -2 -4 -6 -8 |S21| (dB) -10 0 13.615.617.6 19.6 Frequency (GHz) BW > 4 GHz 15 13 11 9 |S21| (dB) 23 24 25 26 Frequency (GHz) 27 28 BW ~ 3.5 GHz -2 -4 -6 -8 |S21| (dB) -10 0 22 24 Frequency (GHz) 26 28 BW > 4 GHz (a) (b)LNA and gain stages Intermediate BPF stages

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95 the 8-dB NF requirement of entire receiver in Tabl e 5-1. Furthermore, the filters have an in-band loss of 3 dB. The rejection of the filters in th e respective TX bands is greater than 15 dB. The specifications of RF sections for the CDMA and FDMA receivers are recaptured in Table 5-3. In addition to the on-chip TX coupling, signals fro m adjacent nodes will also be picked up. These tend to reduce the margin in linea rity even further. To estimate the robustness of the linearity specifications, transient simulations using Adva nced Design System (ADS) an RF system design tool are conducted, and the resu lts are presented in section 5.4. Table 5-3 Summary of RF subsection specif ications for CDMA and FDMA RX. CDMA RX FDMA RX LNA and IA fc :16.8 GHz BW : 3.5 GHz Gain : 15 dB NF : 6 dB IP1dB : -20 dBm IIP3 : -10 dBm LNA and IA fc :25.6 GHz BW : 3.5 GHz Gain : 15 dB NF : 6 dB LNA IP1dB : -20 dBm IA IP1dB : -15 dBm LNA IIP3 : -10 dBm IA IIP3 : -5 dBm BPF fc :16.8 GHz BW : 3.5 GHz In-band loss : 3 dB Loss @ TX band edge of 24.4 GHz : 15 dB BPF fc :25.6 GHz BW : 3.5 GHz In-band loss : 3 dB Loss @ TX band edge of 18 GHz : 15 dB Duplexer In-band loss : 3 dB Loss @ TX band edge of 24.4 GHz : > 30 dB Duplexer In-band loss : 3 dB Loss @ TX band edge of 18 GHz : > 30 dB 5.3.5 Motor Node Analog to Digital Converter (ADC) The ADC at the motor node RX converts the multi-level CDMA signal into its equivalent binary form. Two parameters of importance while designing the ADC are the number of bits (NB) and, signal to noise and distortion ratio (S NDR). A spreading factor of 8 in the received CDMA signal at the motor node RX translates into a minimum requi rement of 3-bit resolution in the ADC. Using Equation (5.2),

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96 02 6 76 1 PSNDR ENOB (5.2) an NB of 3 bits transforms into an SNDR at the ADC output of 19.8 dB considering only the effects of quantization noise [81]. Additional effects such as aperture jitter further reduce the SNDR. The value of 19.4-dB SNDR is the maximum SNR at the ADC input that can be successfully processed without additional degradation from the ADC. For the CDMA RX link, the minimum SNR requirement is 14.5 dB per cha nnel, resulting in a 5 dB margin. A 3-bit ADC therefore should be sufficient. 5.3.6 Other Concerns The mixers at the deadtime c ontroller node can be passive or active with the gains suitably adjusted with the other stages. The local oscillator (LO) signals that cover a wide range from 400 MHz through 24 GHz can be derived from one PLL by suitable manipulation of the locked voltage controlled oscillator (VCO) and divide d signals. The design of the multiple LO signal generation is part of another dissertation work. The gain of the baseband amplifier is set at 20 dB. However, it need s to be adjusted to have adequate signal swing to feed into the ADC (motor node RX) or buffer (deadtime controller node RX). This is more critical at the motor node RX where the detection circuitry used could introduce considerable loss. 5.4 Simulation Results 5.4.1 RX at Motor Node A block diagram of the RF sub-section of th e RX at motor node with the specifications mentioned in Table 5-3 is shown in Figure 5-11. The receiver includes and envelope detector which will be implemented using a Schottky diode detector.

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97 Figure 5-11 RX at motor nodes Simula tion setup and validation of operation. A 6-level CDMA signal up converted to 16.8 GHz is applied at the input. The signal has 50 dBm power. This is the resulting power of a 10-dBm transmitted signal from the deadtime controller TX after undergoing ~ 60 dB loss. The 60 dB estimate includes the worst-case path and two-side antenna loss in Table 5-2. In addition to the in-band CDMA signal, a 7-dBm Duplexer Filter LN A IA BPF 0 A mplitude (mV) 0 Time (ns) -0.5 -1.0 -1.5 1.5 1.0 0.5 20 40 60 80 100 120 LPF BA Envelope Detector 0 Time (ns) 20 40 60 80 0 A mplitude (V) -0.5 -1.0 1.0 0.5 After 30-dB attenuation FDMA blocker @ 24.4 GHz and 7 dBm In-band CDMA signal @ 16.8 GHz and -50 dBm 0Amplitude (mV) -20 -40 -60 60 40 20 0 Time (ns) 20 40 60 80 100 120 0 A mplitude (mV) 15 10 5 0 Time (ns) 20 40 60 80 100 120 0 Time (ns) 20 40 60 80 100120 A mplitude (V) Comprehensive baseband CDMA signal at deadtime controller node TX Received CDMA signal after detection, LPF and baseband amplification LNA : Low noise amplifier IA : Intermediate amplifier BPF : Band-pass filter BA : Baseband amplifier

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98 FDMA signal in the nearest possible motor TX ba nd (24.4 GHz) is also applied. The value of 7dBm which is higher than the estimated value of 3 dBm in Table 5-2 is used to evaluate the robustness of the RF sub-system. Further, to incl ude the effects of on-chip substrate coupling, the same FDMA signal with additional loss of 30 dB is injected at various n odes indicated in Figure 5-11. The signals at the input and output of detector and base band amplifier, respectively indicate that the transmitted signal can be recovered with removal of the FDMA blocker components and without satura tion of the gain stages. 5.4.2 RX at Deadtime Controller Node Similar to that for the RX of at the motor node in Figure 5-11, input stimulus at different positions of the RF sub-section of the deadtime c ontroller RX is indicated in Figure 5-12. As mentioned, component specifications of the differe nt RF blocks are outlined in Table 5-3. An ASK signal up converted to 24.4 GHz with -53 dBm power is applie d at the input. This is the received power of a 7-dBm transmitted signal from the motor controller TX after undergoing ~ 60 dB loss. The 60 dB estimate once again includes the worst-cas e path and two-side antenna loss in Table 5-2. An out-of-band CDMA signa l with 13-dBm power, centered at 16.8 GHz and having 2.4 GHz bandwidth is applied to simula te the same chip blocker. A 13-dBm CDMA signal, 3-dB larger than the estimated value of 10 dBm for the CDMA TX signal in Table 5-2 is used to evaluate the robustness of the deadtim e controller receiver RF sub-system. Additionally, the deadtime controller receives FDMA signal from 7 nodes spr ead from 24.4 27 GHz. While down-converting signal from one node, the other si x act as in-band interferers. To account for this effect, six signals with ~ -38 dBm each and center frequency ranging from 24.8-26.8 GHz are also input to the RX. -38 dBm is the equiva lent power of a 7 dBm signal after adding 50-dB loss of propagation and two-side d antenna loss for a smallest possible distance (5 cm) between the deadtime controlle r and motor nodes.

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99 Figure 5-12 RX at deadtime controller node Simulation setup and validation of operation. LN A IA LPF Duplexer Filter IFA BPF Mixer Mixer 24 GHz 400 MHz Buffer 0 A mplitude (V) -1.0 -2.0 2.0 1.0 0 Time (ns) 20 40 60 80 100 120 0 Time (ns) 20 40 60 80 100 120 0 A mplitude (mV) -0.5 -1.0 1.0 0.5 0 A mplitude (mV) -20 -40 -60 60 40 20 0 Time (ns) 20 40 60 80 100 120 CDMA blocker @ 16.8 GHz and 13 dBm In-band FDMA signal @ 24.4 GHz and -53 dBm 6 composite In-band FDMA blockers from 24.8-26.8 GHz and -40 dBm power each After 30-dB attenuation A mplitude (mV) 200 100 0 -100 0 Time (ns) 20 40 60 80 100120 0 Time (ns) 20 40 60 80 100120 A mplitude (V) 1.2 0 0 Time (ns) 20 40 60 80 100 120Amplitude (V) 1.2 0Transmitted baseband FDMA signal from motor node operating at 24.4 GHz Received baseband signal after dual down-conversion of FDMA signal centered at 24.4 GHz LNA : Low noise amplifier IA : Intermediate amplifier IFA : IF amplifier at 1.6 GHz BPF : Band-pass filter

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100 Further, to simulate on-chip substrate coupling, the CDMA blocker signal w ith additional loss of 30 dB is injected at various points indicated in Figure 5-12. Down-converte d signal at output of low-pass filter and digital output indicate that the transmitted ba seband signal can be recovered in the presence of CDMA and FDMA blocker co mponents without satura ting the gain stages. 5.5 Conclusions The concept of using wireless interconnect s to replace existing photo-couplers on an inverter board in a HEV is propos ed in this chapter. Signal sepa ration strategies and transceiver topology are proposed. In this regard, a CDMA sc heme is used for the forward link from the central deadtime controller to the motor nodes, and FDMA for the revers e link. The issues of synchronization related to CDMA and linearity ha ve been analyzed and block-level parameters have been derived. Finally, the simulation resu lts of the transceiver are presented suggesting proper operation of the system. The proposed res earch will further focus on the implementation of the receiver at the motor node including an envelope detector.

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101 CHAPTER 6 CDMA RECEIVER FOR WIRELESS INTER CONNECTION ON AN INVERTER PCB 6.1 Introduction System design of a wireless interconnect that supports CDMA for the down link and FDMA for the up link was described in the previ ous chapter. The wireless interconnect scheme could potentially replace opto-coup lers on an inverter PCB to provi de benefits in cost, latency, speed as well as footprint. Most of the FDMA receiver chain components, both individual and integrated, have already been demonstr ated at the University of Florida [83]. The design and characterization of components for the CDMA r eceiver chain (excluding the duplexer and clock and data recovery CDR) with specifications liste d in Table 5-3 is presented in this chapter. A 130-nm CMOS process is used for circuit fabricati on. An SBD detector is used for rectification, similar to that presented in ch apter 4. Characterization of dupl exer and CDR are parts of other theses [80]1. Finally, the performance of the entire down-converter chain including the RF and analog components is presented. 6.2 Circuit Description and Layout A block diagram of the CDMA receiver chain th at is part of this thesis is redrawn in Figure 6-1. The limiter and CDR bl ocks are included. An on-chi p antenna is used for signal reception. To accommodate the differential nature of the antenna, both the duplexer and the LNA are differential. The differential LNA additionally provides resistance to common-mode substrate noise coupling. This could be benefi cial especially in the presence of the highamplitude FDMA transmitter signal coupled through the substrate. The SBD based detection is single-ended. To convert the differential signal to single-end, an active current-mirror based balun is used following the LNA. The active balun provides added gain and accommodates an 1. K. Oh, Private communications.

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102 additional 2nd order filter that improves the rejection of out of band FDMA TX signals. Further a buffer that acts as a low-impedance source is used to drive the SBD detector. Figure 6-1 Block diagram of CDMA r eceiver chain including limiter and CDR. A modified block-level schematic is shown in Figure 6-2. Figure 6-2 Modified block-level sc hematic of CDMA receiver chain. Active balun LNA with 2nd order BPF RF buffe r 2n d order LPF SBD based rectifier Multi-level CDMA signal Recovered Clock Duplexer 3r d order BPF RF amplifier with 3rd order BPF 50tapered buffer RF Section fc 16.8 GHz Bandwidth 3.5 GHz Gain >30 dB Noise Figure < 6 dB IP1dB >-45 dBm Rejection > 55 dB at 25.6 GHz RF Section Baseband amplifier section Limiter CDR Baseband amplifier Bandwidth 0-1.2 GHz Gain ~40 dB Vo-peak 100 mV LNA : Low noise amplifier IA : Intermediate amplifier BA : Baseband amplifier BPF : Band-pass filter LPF : Low-pass filter BPF LNA BPF I A LPF Limiter CDR SBD based rectifier B A Duplexer Multi-level CDMA signal Recovered Clock

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103 The receiver design is split into multiple secti ons (indicated in dotted li nes) to facilitate use of straightforward design methodol ogies. Included in Figure 6-2 are the target specifications that account for component variations and quality factor (Q). The IP1dB for the entire RF chain is derived from the IP1dB specification of each stage. The gain and filter blocks are co-designed to aid absorption of parasitics elements. The band-p ass filters (except the first filter between the LNA and active balun) are of 3rd order to achieve the required reje ction listed in Table 5-3. The additional 20-dB gain in the baseband amplifier accounts for the loss in the SBD rectification circuit and ensures ~200-mV volta ge swing at the output for -60dBm RF input. A tapered buffer stage following the baseband amplifier is used to drive the 50input of measurement instruments. 6.2.1 RF Section The circuit schematics of various blocks that constitute the RF section starting from the LNA are shown in Figure 6-3. The induc tively source-degenerated diffe rential LNA has a low input quality factor (Qin) of ~1.4 to provide a wideband match to 50 over a 3.5-GHz band centered around 16.8 GHz. The common-mode poi nt is tuned to offer high impedance at 16.8 GHz using an inductor (LCOM) thereby improving the common-mode re jection ratio (CMRR). A two-section capacitive coupled filter with 400termination is used at the output. The 400termination provides additional voltage gain, makes the filter response flat and component values reasonable for implementation. The width and length of MN1 and MN2 are 64 m and 120nm, respectively. The values of LG1, LS1 and LCOM are 1.1 nH, 0.1 and 0.4 nH. Th e tank inductor (L) and capacitor (C) values used in the 2-section filter are 1.05 nH and 70 fF respectively. The coupling capacitor between the two tanks is 25 fF.

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104 Figure 6-3 Circuit schematics of components in RF section. The differential LNA output is combined usi ng the active current-mirror balun. Again the common-mode point at the source node of the input transistors is tuned at 16.8 GHz to improve CMRR. Further, the 1/gm diode-connected low-impedance node is also tuned to improve the inband gain and make the frequency response flat. The transistor widths of both MNB and MPB are 24 m and the channel length is 120nm. The values for LCOM and LD2 are 600 pH. The second terminal of LD2 is connected to the small-signal ground using a 10 pF bypass capacitor (CBYP). The combined signal at the output of balun is filtered using a 3-sect ion capacitive coupled Chebychev filter with 3.5-GHz bandwidth and 16.8 GHz fc. The filter is designed for 400termination for the reasons mentioned earlier. Th e L and C values of the center tank are 770 pH LNA with 2nd order BPF RF buffe r 3r d order BPF From duplexer RF amplifier with 3rd order BPF Active balun vi + vi -LS LCOM1 MN1 MN2 LG1 LG1 LD1 CC1 L2 C2 C2 L2 CC1 CC CC C2 C3 L2 L3 L1 C1 C2 C3 L2 L3 CC CC MN1 MN2 LD MNB LCOM2 CBYP LD2 MNB MPB MPB To SBD detector

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105 and 67 fF. The L and C values for the tanks on e ither side are 770 pH and 100 fF, respectively. The three tanks are coupled using 30-fF capacitors (CC). A cascode amplifier follows the filter and is terminated at the output using the same 3-section filter. The widths and lengths of the common-drain and common-gate transistors of the cascode amplifier are 72 m and 120 nm respectively. Finally, the signal is buffered us ing a cascode amplifier with 60-m wide and 120nm long transistors. The buffer acts as a low-impedance voltage source (~10 ) for the following SBD rectification stage. All the transistors are biased through 400p+ polysilicon resistors. The bias resistors additi onally act as the 400terminations for the band-pass filter sections. The inductors are implemented using the top metal la yer (metal 8) and are ground shielded using a slotted p+ polysilicon layer. All the capacitors us ed are metal-metal cap acitors implemented using metal 7 and 8 layers. To test the RF section by itself, the 10buffer is replaced by a buffer that drives 50 The simulation results of the RF section with 50output driving capability are shown in Figure 64. The input and output reflecti on coefficients magnitudes (|S11| and |S22|) are less than -10 dB over 14.5-20 GHz. The peak simulated gain (|S21|) is over 40 dB with a 3-dB bandwidth of ~4 GHz and the in-band noise figure is less than 2 dB. The plot of output power versus input power indicates that IP1dB is greater than -45 dBm. 6.2.1 SBD Rectifier Figure 6-5 shows the circu it schematic of SBD half wave rectifier. A voltage source with low source impedance (10 ) is used to excite an d optimize the performance of the detector. The low-impedance source emulates the RF buffer output. The RF signal is passed through a coupling capacitor (CC) to the detector and block the injection of baseband output into the RF section. It additionally DC isolates the detector and preceding buffer stage. In the final integrated system, this coupling function is provided by the output matching capacitor of RF buffer. The SBD is biased through a 5-k polysilicon resistor (RBIAS) and is connected in shunt mode to

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106 eliminate the impact of parasitic capacitance at the n-well terminal. A 4-section Chebychev lowpass filter with 1.2 GHz cut-off and 30 termination is used to fi lter the higher order harmonic components generated during rectification. Figure 6-4 Simulation results for 50 RF section with 50output drivability. The inductor-first LPF configuration offers hi gh impedance at RF. This is important to prevent RF signal loss through the filter. The diode size and bias are de termined by using the approach presented in section 4.4.3. The optimal values for mSBD and IDIODE are 4 and 0.5 mA respectively. Each SBD has 16 X 0.32 X 0.32 m2 Schottky area. The filter component values are L1, L3 = 4.3 nH and C2, C4 = 1.5 pF. The inductors are formed on metal 8 with a polysilicon patterned ground shield at the bottom. The capacito rs are again metal-metal capacitors (metals 58) to prevent variation in capacitance value ove r large signal swing. Also shown in Figure 6-5 S-parameters (dB) -30 -20 -10 0 10 12 1416 18 202224 Fre q uenc y ( GHz ) | S11 | | S22 | Fre q uenc y ( GHz ) 1012141618 20 2224 -30 -10 10 30 50 S parame ters(dB) | S21 | Fre q uenc y ( GHz ) 10 12 14 16 18 202224 0 20 40 60 80 Noise figure (dB) NF < 2dB inband IP1dB > -45 dBm -16 -12 -8 -4 0 4 -60-50-40 -30 PIN ( dBm ) POUT (dBm)

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107 are a multi-level RF input (at 16.8 GHz) and dete cted output waveforms. The output follows the negative envelope which is consistent with the way the SBD is configured. Figure 6-5 Circuit schematic and sample input/o utput waveforms of SBD half-wave rectifier. 6.2.3 Baseband Amplifier The block-level schematic with the circuits that constitute each block of the baseband amplifier is shown in Figure 6-6. The gain bloc k comprises of three identical stages with an NMOS input transistor and a PMOS load. To se t the bias point at the output, a single diodeconnected 120-nm long and 1m wide PMOS transistor is also conn ected at the load as shown in Figure 6-6(c). The gain and bandwidth of th e individual stages are ~7 dB and 1.5 GHz, respectively. Both the NMOS input and PMOS load are biased using the bias circuit shown in Figure 6-6(b). Biasing resistors are used to isolat e the AC signal from the bias block. The three L1 L3 C2 C4 RBIAS VDIODE CC mSBD IDIODE 10source at 16.8 GHz 30load termination -40 -20 0 20 40 Time (ns) 0 5 1015 20Voltage (mV) Follows negative envelope 0 5 10 15 20 -2.5 -1.5 -0.5 0.5 1.5 Time (ns)Voltage (mV)

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108 stages are capacitively c oupled and as large as 40 M resistors are used for biasing the NMOS inputs. Figure 6-6 Baseband amplifier (a) block diagram, and schematics of (b) bias circuit, (c) gain, and (d) buffer blocks. The 40-M resistor in conjunction with CC (140 fF) has a high-pass co rner frequency of around 50 kHz which is small enough to accommodate for the low-frequency cont ent of the multi-level CDMA signal. The NMOS and PMOS gain-s tage transistors ar e 12 and 35 m wide, respectively and have the minimum gate length (120 nm). The output signal is buffered using four capacitively coupled NMOS stages with a diode-connected PMOS load. Again the NMOS inputs are biased using 40-M resistors to allow for the low-fr equency content. The four stages are designed in a tapered manner to drive a 3-pF load capacitor. Under this condition, the output impedance of the final stage is ~50 Therefore, the output can also be used to drive the 50of RBIASNCc VBIASN VOUT vIN MP MN 1 MP MN RBIASN RBIASP Cc VBIASN VBIASP vIN VOUT 3pF/ 50 Gain block Tapered buffer block BIAS CIRCUITRY From Detecto r To A DC RBIAS RBIAS MNBIAS MPBIAS IBIAS VBIASN VBIASP (a) (b) (d) (c)

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109 measurement instruments. The NMOS and PMOS tr ansistor widths for th e four tapered buffer stages are 12, 18, 54 and 81 m, respectively and have 120-nm gate length. The coupling capacitor values for each of the four stages are 140, 200, 600 and 1200 fF, respectively. The 40M resistors are implemented using the highly resistive silicide-blocked p+ polysilicon with 120-nm width and the coupling capac itors are metal-metal structur es implemented using the top two metal layers (metals 7 and 8). Figure 6-7 plots the frequency response of the baseband amplifier with the LPF from the preceding half-wave re ctifier stage. Figure 6-7 Frequency response of baseband amplifier. The gain and bandwidth are ~38 dB and 1.3 GHz respectively which are large. To prevent positive feedback and oscillations due to the fi nite impedance of bond wires at the power and ground node, every odd-connected stage has separate power and ground. Further, there are no bypass capacitors between the supply rails on chip to prevent any effects of resonance with the bond wires. Despite these efforts, a slight peaking in the frequency response is seen at ~5 GHz. 40 -40 -20 0 20 0 1 2 3456789 Frequency (GHz) f3-dB = 1.3 GHz Gain (dB) Effects of bond wire resonance

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110 The time domain response is shown in Figure 68. The output is an amplified form of the input signal and is inverted. This is due to th e odd number of stages. The output takes over 100 s to settle due to the large value of the NMOS input bias resistors. Figure 6-8 Time domain response of the baseband amplifier. 6.2.4 Limiter A circuit schematic of the limiter is shown in Figure 6-9. The limiter rails an incoming signal depending upon a threshold voltage (VTHRESH) and provides a two-level random binary data pattern to the CDR. This facilitates prope r locking of the CDR. The multi-level baseband signal is compared with VTHRESH and amplified using a differentia l pair with a tail current source and a diode-connected PMOS load. Cross-coupled PM OS transistors are used at the output of the differential pair to improve the gain. 0.1 0.3 0.5 0.7 0.8 Output 0 40 80 120 160200 Time ( s ) VOUT (mV) 0.2 0.3 0.4 0.5VOUT (mV) 2.5 2 1 0VIN (mV) 0 40 80 120 160200 Time ( s ) 2.5 2 1 0 VIN (mV) In p ut

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111 Figure 6-9 Circuit schematic of limiter. The differential output is then railed using a high-gain ra il-to-rail converter [84]. The resulting differential outputs are buffered using a 3-stage inverter. Additional capacitance is added along the 3-stage inverter paths to prope rly align the delays for the multi-level and the binary input data pattern to the CDR. Transistors MN1, MP1, MP2, MN2, MC, are 20, 4, 8, 4 and 32 m wide, respectively and 120-nm long. Transistors MP3 and MC1 are 12 and 8m wide and have a length of 240 nm The capacitors CC1, CC2 and CL are 500,100 and 200 fF, respectively. These are implemented using metal-metal capacitors built using metal 5-8 layers. The bias resistors are 1 M and are fabricated us ing silicide-blocked p+ polysilicon resistors w ith 120-nm width. The IBIAS VN MC Vo2 Vo2 + CL CL CL CL Differential, random binary data pattern to CDR MN2 MP3 VN MC1 MP3 MP3 MC1MC1 RBIAS2 CC2 CC2 VBIAS2 VBIAS2 Vo1 +Vo1 Vo2 -Vo2 +VN VTHRESH MN1 MN1 MP2 MP1 VBIAS1 VN MC RBIAS1 Vo1 + Vo1 -CC1 MP1 MP2 RBIAS1 VMULTI-LEVEL

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112 differential output of the limiter with 240-mV p eak-peak input is shown in Figure 6-10. The differential output shows complement ary rail-to-rail voltage swing. Figure 6-10 (a) Simulated time domain 240-mV p eak-peak input signal to limiter, (b) inphase, and (c) out-of-phase signals at the limiter output. 6.3 Measurement Results and Discussions To facilitate ease of measurements and tes ting, apart from the w hole receiver, breakout structures of the receiver are also fabri cated. These include the RF section with 50output matching, detector-baseband amplifie r combination and limiter structures. 6.3.1 RF, Detector-Baseband Amplifier and Limiter Summary of specifications, simulated and meas ured results are presented in Table 6-1. Detailed explanation on the difference between simu lated and measured results is given when the respective stages are discussed. 0 0.1 0.2 0.25 17.25 17.3 17.35 17.4Voltage (V) Time ( s ) 0 0.4 0.8 1.2 1.4 17.2517.317.35 17.4 Time ( s ) Voltage (V) 0 0.4 0.8 1.2 1.4 17.2517.317.35 17.4 Time ( s ) Voltage (V) (a) (b) (c)

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113 Table 6-1 Summary of specificatio ns, simulated and measured re sults of various blocks in the receiver. Stage SpecificationSimulatedMeasured RF Gain (|S21|) Bandwidth Input matching center frequency Output matching center frequency Noise figure (NF) Rejection at 25.6 GHz Detector-baseband amplifier Gain Bandwidth Vopeak-peak Limiter Sensitivity (peak-peak) ~24 dB 2.4 GHz 16.8 GHz 16.8 GHz 6 dB ~56 dBr NA 1.2 GHz NA NA ~40 dB ~4 GHz 16.8 GHz 16.8 GHz < 2dB ~ 60 dBr 38 dB 1.3 GHz 200 mV 20 mV ~15 dB ~4.5 GHz ~13 GHz ~17.6 GHz 8 dB ~35 dBr 33 dB 0.9 GHz ~200 mV <20 mV The RF section is measured on a test printe d circuit board (PCB) with DC bonded out to facilitate robust grounding and measurem ents as shown in Figure 6-11(a). Figure 6-11 RF section (a) mounted on a printe d circuit board and (b ) measurement setup. The input and output are connected using differential ground-signa l-signal-ground (GSSG) probes. Since the output is single ended, one signal-ground (S G) of the output differential port is terminated with 50 on chip. This facilitates differentia l input and pseudo differential output Off-chip balun (a) (b) DUT DUT Device under testDifferential in p ut and out p ut

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114 measurements. The measurement setup is also shown in Figure 6-11(b). Single ended signals from a network analyzer (HP8510C) are converted to differential using an off-chip balun.The measured magnitudes of S-paramete rs are shown in Figure 6-12. A peak gain of 14.5 dB and 4.5 GHz 3-dB bandwidth are observed. The input and output are tuned at 13 and 17.6 GHz respectively. The measured noise figure (NF) is around 7-dB. The measured gain is ~25 dB lower and the noise figure is higher (Table 6-1) th an the simulated results in Figure 6-4. This is mainly due to the mistuning among different stag es, as well as, the input and output (contributes to ~5 dB drop), and the low Q of the inductors implemented on just the top metal layer. A 20 dB reduction in the gain is observed in simulations when the Q drops from 20 to ~6. The RF section consumes ~33 mA from a 1.5-V supply. Figure 6-12 Measured magnitudes of S-paramete rs and noise figure (N F) of RF section. The detector-baseband breakout structure is also measured on a test PCB to improve grounding and to reduce the impact of parasitic i nductances. The measurement board is shown in -80 -60 -40 -20 0 20 10 2025 S-parameters and NF (dB) Frequency (GHz) |S22| |S11| NF |S12| |S21| 15

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115 Figure 6-13(a). 10-F bypass capacito rs are placed on the back-sid e of the board, as close as possible to the PCB DC pads to minimize add itional inductance at the power supply nodes. The SBD in the detector is biased for 50matching (corresponds to a diode current of 0.5 mA) at the input. The input and output are connected using single-ended SG probes as indicated in the measurement setup in Figure 6-13(b). The inpu t is swept over 0.01 to 3 GHz using a signal generator (E4421B) and the output is measured using a spectrum analyzer (HP8563E). Figure 6-13 (a) PCB with detect or-baseband amplifier stand-alone test structure mounted and bonded and (b) measurement setup. The frequency response of detector-baseba nd amplifier is shown in Figure 6-14. The measured gain is ~33 dB with 3-dB bandwidth of ~900 MHz. Compared to the simulation results (Figure 6-7 and Table 6-1), th e gain and bandwidth are lo wer by ~5 dB and ~300 MHz, respectively. The reduction in bandw idth can be attributed to the additional capacitive loading at the NMOS input by the large 40-M bias resistor. The resistor also causes the gain to drop by ~3 dB. The remaining 2 dB is due to the lower Q of the inductors used in the LPF. A bump in the (a) DUT Device under test (b) DUT Single-ended input and output

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116 frequency response is observed around 2 GHz. This is due to the effects of bondwire resonance which were also seen in the simulations (Figur e 6-7). Also shown in Figure 6-14 is a sample output spectrum observed on HP8563E for ~-61 dBm, 200 MHz input. The out put has a peak at 200 MHz with ~-27 dBm power which corresponds to a gain of ~ 34 dB. Additional spectral content between 600-900 MHz is also observed. Th is is due to pick-up of emissions from the television broadcasting and land mobile ba nds. The detector-baseband amplifier section consumes ~11 mW of power. The limiter is measured on wafer using SG pr obes. The input is supplied from a signal generator at 200 MHz (corresponds to 400 Mbps data) and the output is observed on a spectrum analyzer. The output spectrum for a 200-MHz, 25 dBm input is shown in Figure 6-15(a). Figure 6-14 Frequency response of detector-b aseband amplifier and sample output power spectrum with ~-61 dBm, 200 MHz input. Harmonic at 600 MHz, which is the third harmonic, indicates that the output is square-wave like. Furthermore, significant harmoni c at 400-MHz indicates that the output duty cycle is not 50%. This is not an issue since the CDR that uses th is output relies only on either the rising or the falling edges. Shown in Figure 6-15(b) is the out put signal when the input is at 200 MHz and has power of -35 dBm. Degradation in the fundamental as well as the harmonics is started to be seen. 12 03 -60 -40 -80 -20 Frequency (GHz) Peak at 200 MHz Output power (dBm) fin = 200 MHz Pin = -61 dBm 3.5 0 10 20 30 40 0 1 2 3 Filter roll-off Bond-wire resonance effects Frequency (GHz) Gain (dB)

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117 These results indicate that the limiter is sensit ive to input signals with higher than -35 dBm power. Figure 6-15 Limiter output when input is at 200 MHz, (a) -25 dBm and (b) -35 dBm power. This corresponds to less than 20 mV peak-peak input swing for a 50system which is sufficient to discern adjacent levels for a multi-le vel system with 6 levels and 30 mV step. The limiter consumes ~5 mW of powe r from a 1.2-V power supply. 6.3.2 Overall Receiver The receiver chain is mounted on a test PCB to ease DC biasing and observe the baseband and CDR outputs. The test board along with a zoomed snapshot of the bonding area is shown in Figure 6-16. Figure 6-16 Test board used to measure the receiver chain. 6 cm 12 cm SMA connectors to observe recovered clock and baseband output 800 200 400 600 100 -60 -40 -80 -20 Frequency (MHz) Output power (dBm) (a) (b)800 Frequency (MHz) 200400600 100 -50 -30 -70 -20 Output power (dBm)

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118 There is no ground plane beneath th e chip to prevent degradation of the on-chip dipole antenna performance. The 400-Mbps data and 400-MH z recovered clock are observed using SMA connections. Figure 6-17 shows the chip micro-gra ph of the receiver. The total active area is ~2.1 mm2 excluding the bond-pads. A receiver without a duplexer is characterized using 12-16 GHz input signals amplitude modulated with 200-MHz sine wave and 50% m odulation index. The m odulation frequency is selected to emulate waveforms of 400 Mbps data. A plot of Pout versus carrier frequency (fcarrier) is shown in Figure 6-18(a). The SBD bias current is ~130 A and the input sideband power is 54 dBm. Pout fluctuates by ~3 dB over 14-16 GHz and is relatively flat due to the RF input being matched around 13 GHz (Figure 6-12). Figure 6-17 Die photograph of the receiver. Figure 6-18(b) plots the output power (Pout) at 200 MHz versus diode bias current. The input signal frequency is 14.5 GHz. The sideband power (Pin) is -54 dBm. The output power is maximized at bias current of ~130 A which is lower than what is expected from simulations (0.5 mA). This is possibly due to larger impe dance at the output of RF buffer compared to simulations (10 ). At lower bias currents, the SBD junc tion impedance is larger. This aids in larger voltage transfer from the RF buffer to the detector for larger buffer output impedance. 4mm Du p lexe r RF SBD rectifier and low pass filte r 4-mm zi g za g 1.8mm Baseband amplifie r CDR Limite r Active area: ~2.1 mm 2 (Excludes bond-pads)

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119 Figure 6-18 Output power ve rsus (a) bias current (IDIODE) and (b) carrier frequency (fcarrier). The input and output signals are shown in Figures 6-19(a)-(d). Pin is -54 dBm and is centered at 14.5 GHz. Figures 6-19(c) and (d) indicate su ccessful recovery of the baseband signal. Figure 6-19 Input AM signal observed on (a) an oscilloscope, (b) a spectrum analyzer, 200MHz output seen on (c) an oscillos cope, and (d) a spectrum analyzer. 0 5 10 -6 -3 0 3 6 Vin (mV) Time (ns) -20 -10 0 10 20 0 5 10vout (mV) Time (ns) -60 -80 -40 14.3 14.5 14.7 Pin (dBm) Frequency (GHz) 200 190 210 -60 -40 -70 -20 Pout (dBm) Frequency (MHz) 5 ns ~-25dBm (d) (b) (c) (a) ~-55 dBm ~-54 dBm -80 -60 -40 12 14 16 18 Pout (dBm) Frequency (GHz) -20 -60 -40 -20 0 200 400 600 800Pout (dBm) Diode bias (A) (a) (b) fcarrier: 14.5 GHz fmod: 200 MHz Pin: -54 dBm IDIODE: 130 A fmod: 200 MHz Pin: -54 dBm

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120 Figure 6-20(a) plots Pout at 200 MHz versus Pin. The input is centered at 14.5 GHz. The square-law region marked with a slope of 2 indi cates a dynamic range at the input of over 37 dB and at the output of ~80 dB [54]. The peak conversi on gain occurs when Pin is ~-45 dBm and is ~35 dB. The RX noise is measured by terminating the RF input with 50and observing the output noise [54] (Figure 6-20 (b)). The total integrat ed output noise to 1 GHz is ~-42 dBm. From Figure 6-20(a), this corresponds to Pin of ~-64 dBm which is the receivers input noise floor. This translates to a system NF of 20 dB and ~-58 dBm receiver sensitivity for an Eb/No of 14dB (bit error rate of 1X10-13 for ASK) and 400-Mbps data rate. Figure 6-20 (a) Pout versus Pin and (b) Output noise power spectral density. Plots of the detected baseband signal in frequency domain a nd the recovered clock in timedomain when the modulating frequency (fm) is varied from 197.3 to 202.3 MHz are shown in Figures 6-21(a)-(f). The input sign al is centered at 14.5 GHz with Pin = -55 dBm. The CDR locks to the incoming signal and the recovered clock follows the m odulating signal with 10 MHz locking range. The locking range is degraded at lower power levels due to the coupling of the large-amplitude recovered clock to the baseband section. This coupling could be due to multiple Pin (dBm) Pout (dBm) -80 -60 -40 -20 0 -85 -75 -65 -55 -45 2 dec/dec slope fcarrier: 14.5 GHz fmod: 200 MHz Idiode: 130 A (a) -160 -150 -140 -130 -120 00.20.40.60.8 1.0Noise (dBm/Hz) Frequency (GHz) Idiode: 130 A -110(b)

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121 mechanisms one of which is that among the bond-wires of the baseband output, power supply and recovered clock signals. To demonstrate a wireless link within the mo tor control board, a m easurement setup shown in Figure 6-22 is used. The CDR is biased down to avoid corrupt ion of the baseband signal. A 200-MHz AM signal centered at 14.5 GHz is tran smitted from location N14 in Figure 5-1 using a 4-mm dipole antenna. A signal with ~2 dBm si deband power is converted to differential and fed to the antenna. A metallic cover is used ov er the controller board to emulate the operation environment. The cover reduces the propaga tion loss and impact of multi-path effects [85]. The signal is picked up at location N9 (Figure 5-1) using a receiver (with the antenna and duplexer). The separation between points N9 and N14 is ~15 cm, which is the maximum needed for the system. Figure 6-21 Detected baseband signal at (a ) 197.3 MHz, (b) 200 MHz, and (c) 202.3 MHz observed in a spectrum analyzer and, recovere d clock at (d) 394.6 MHz, (e) 399.9 MHz, and (f) 404.5 MHz seen on a sampling oscilloscope. 180 220 140 260 -60 -40 -70 -20 Frequency (GHz) fm = 197.3 MHz 180220 140260 -60 -40 -70 -20 Frequency (GHz) fm= 200 MHz 180 220 140 -60 -40 -70 -20 Frequency (GHz) fm = 202.3 MHz 260Output power (dBm) fclock = 404.5 MHz fclock = 399.9 MHz fclock = 394.6 MHz (a) (b) (c) (d) (e) (f)

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122 The transmitted and receive d signals are also shown in Figure 6-22. The 200-MHz received signal has ~-38 dBm power. De-embedding the receiver gain (Figure 6-20(a)) and 3-dB measured duplexer loss; the channel loss includi ng those for on-chip ante nnas is ~60 dB at ~15 GHz. Figure 6-22 Wireless link demonstration and setup. The receiver consumes ~60 mW of power and occupies ~2.1 mm2 of area (circuits + antenna). The gain is ~30 dB lower than needed. The RF stage gain can be raised by 10 dB using inductors formed with top two me tal layers shunted instead of ju st the top metal layer and by reducing the mistuning among different blocks. This should increase the detector conversion gain by 20 dB. This should also reduce NF by 10 dB. Adding another baseband amplification stage should increase the gain by another 10 dB. 6.4 Conclusions The integrated circuit implementation of the CDMA receiver at the motor node is presented in this chapter. Individual radio frequency, detector and baseband amplifier components that make up the receiver are ch aracterized and the performance of the downAgilent 8341A LO at 14.5 GHz SS Probe Receiver Agilent 8563E Spectrum Analyzer -60 20 14.3 14.5 14.7 Pin (dBm) Frequency (GHz) Mixe r Power Amplifiers Receiver mounted on board 15 cm Controller Board SS probe ~-38 dBm 15 cm Pout (dBm) Frequency (MHz) 200 180 220 -60 -100 -20 ~1.5 dBm ~2 dBm Agilent E4421B IF at 200 MHz

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123 converter chain is also evaluated. The detect or consumes ~60 mW of power and has ~-58 dBm sensitivity for an ASK system with Eb/No of 14 dB and 400-Mbps data rate. The feasibility of wireless interconnection within the hybrid engine controller boa rd is also demonstrated by demodulating an AM signal cen tered from 14-16 GHz and capabl e of supporting 400-Mbps data rate. This work also suggests the potential fo r implementing a Schottky diode based receiver for frequencies over 10 GHz, which does not need a frequency reference.

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124 CHAPTER 7 SUMMARY AND FUTURE WORK 7.1 Summary A Schottky barrier diode (SBD) with cut-of f frequency greater than 1 THz has been demonstrated in a 130-nm foundry CMOS pro cess. The implementation requires no process modification. The diodes provide higher second-order conversion gain in comparison to the MOS structures available in CMOS. The diodes can be used to implement high millimeter wave and terahertz circuits. An experimental optimiza tion study suggests that it will be possible to increase the cut-off frequency beyond 2 THz at the 130-nm technology node. The usefulness of these diodes is demonstrated by using them in an AM detector suited for pulse-based UWB applications. System level simula tions of a wireless interconnect system using both CDMA and FDMA on an inverter printed circ uit board suggest it is possible to replace the costly photo couplers currently us ed with a low cost CMOS solu tion. Demonstration of wireless interconnection within the hybrid engine contro ller board indicates th e potential of using Schottky diode detectors at even higher freque ncies which could yield significant reduction in area and power, and eliminate the need for an external crystal frequency reference. 7.2 Future Work 7.2.1 SBD Evaluation The optimization studies in chapter 3 indicate that it should be possible to increase the cutoff frequency beyond 2 THz by using a polysilicon gate layer lined with insu lators instead of a shallow-trench to separate the n-well and Sc hottky contacts. The study also indicates the possibility of reducing the n-well capacitance thereby improving the bandwidth of detectors. These need to be validated by fabricating and ch aracterizing the optimized diode structures. The work on the SBDs in this thesis mostly used a foundry 130-nm CMOS technology with some

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125 using a 180-nm process. The diode characteristics and its layout dependences are required to be evaluated at more advanced techno logy nodes such as the 90 and 45 nm. 7.2.2 CDMA Receiver Chain Optimiza tion and Characterization The performance of a Schottky diode base d receiver capable of detecting a 400-Mbps multi-level CDMA signal is evaluated in chapter 6. Currently the gain and sensitivity are lower than the required due to low gain of the RF st age. Furthermore, the frequencies are not properly tuned. The passive components used in the RF st age circuits need to be improved and the tuning among blocks must be improved. Another concer n is the coupling between the large amplitude signals in the CDR and the baseband circuits. Th is needs to be more carefully studied and methods to mitigate this must be developed. The RF and analog sections are presented in this work. The ADC and digital correlator need to be integrated with the down-converter, and their performance should be characterized on the motor controller board.

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BIOGRAPHICAL SKETCH Swaminathan Sankaran was born in Madras, Tamil Nadu, India, in 1981. He received the B. Tech degree in electronics and communicati ons engineering from P ondicherry Engineering College, Pondicherry, India, in 2002, and the M.S. degree in electrical and computer engineering from the University of Florida, Gainesville, in 2004. He receiv ed his Ph.D. degree in the same department in 2008 and has been with Silicon Microwave Integrated Circuits and Systems (SIMICS) research group since 2003. During the summer of 2006, he interned at Bitwave Semiconductor Corporation where he was involved in circuit design a nd device modeling. He has been a student member of IEEE for the past five years. His current research intere sts are in analysis and design of RFIC systems, receiver front end and high-speed analog circuits in CMOS.