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CMOS Millimeter and Submillimeter-Wave Components

Permanent Link: http://ufdc.ufl.edu/UFE0021972/00001

Material Information

Title: CMOS Millimeter and Submillimeter-Wave Components
Physical Description: 1 online resource (126 p.)
Language: english
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2008

Subjects

Subjects / Keywords: antenna, cmos, detector, oscillator, patch, push, vco
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: With continued introduction of new wireless applications, the available spectrum is becoming crowded. Because of this, interests for developing circuits and systems operating at higher frequencies have been increasing larger bandwidth and propagation properties of signals in the frequency range from 100 GHz to 3 THz have led to the recent increase in research efforts. For the communication over 30m, use of antennas are better than using transmission lines at the frequency above 60GHz. Use of on-chip antennas at high frequencies makes systems compact and lower cost, as well as potentially improve their performance. The impact of realistic metal interference structures which can significantly modify the characteristics of on-chip antennas, such as a power grid, local clock trees and data lines have been investigated using EM simulations. In the presence of a power grid, the antenna pair |S12| can be traded off for improved stability of antennas characteristics and the predictability of on-chip antenna characteristics. The radiation of a patch antenna is due to the fringing fields. The ground plane in the patch antenna decreases the coupling to near by circuits. The design of patch antenna in CMOS processes is limited by the fixed relatively low dielectric thicknesses. These limit the input resistance and efficiency. The bond wires change the radiation direction by ~13? at the distance of 50 um from a patch for 250 GHz operation and decrease the input resistance by about 4 ohm. Increasing the separation to 150 um, make the impact of bond wires negligible. A 182-GHz Schottky diode detector is demonstrated in foundry 130-nm CMOS technology. A 182-GHz AM modulator is implemented by changing the gate bias of PMOS current source of a push-push oscillator which utilizes the 2nd order harmonics. The operation is verified by the observation of 91-GHz AM signals at the fundamental using an OML harmonic mixer. The noise performance of a 250 GHz Schottky barrier diode detector with an on-chip patch antenna in 90 nm CMOS also have analyzed. To overcome the difficulties of electrical measurement techniques for submillimeter-wave circuits, optical techniques are utilized. The power and spectrum of 250-GHz and 410-GHz push-push oscillators have been measured using a bolometer (HD-3, IR Lab) and FTIR (IFS 113v, Bruker). A 250-GHz push-push oscillator with an on-chip patch antenna fabricated using a 90-nm CMOS process is demonstrated. A ring oscillator is incorporated for the generation of 250-GHz AM signals. The 125-GHz AM signal is measured using a harmonic mixer and a spectrum analyzer. The radiated second harmonic power from the patch antenna is about -32 dBm. A 410-GHz push?push oscillator with an on-chip patch antenna fabricated using low leakage transistors of a 45-nm CMOS process with 6 metal layers is demonstrated. The patch antenna size is 200 x 200 um2. The radiated second harmonic power from the patch antenna is about -49 dBm. The 410-GHz operating frequency is the highest among the transistor circuits fabricated in any technology including the III-V technologies. These suggest the possibility of CMOS THz systems.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Thesis: Thesis (Ph.D.)--University of Florida, 2008.
Local: Adviser: O, Kenneth K.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2008
System ID: UFE0021972:00001

Permanent Link: http://ufdc.ufl.edu/UFE0021972/00001

Material Information

Title: CMOS Millimeter and Submillimeter-Wave Components
Physical Description: 1 online resource (126 p.)
Language: english
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2008

Subjects

Subjects / Keywords: antenna, cmos, detector, oscillator, patch, push, vco
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: With continued introduction of new wireless applications, the available spectrum is becoming crowded. Because of this, interests for developing circuits and systems operating at higher frequencies have been increasing larger bandwidth and propagation properties of signals in the frequency range from 100 GHz to 3 THz have led to the recent increase in research efforts. For the communication over 30m, use of antennas are better than using transmission lines at the frequency above 60GHz. Use of on-chip antennas at high frequencies makes systems compact and lower cost, as well as potentially improve their performance. The impact of realistic metal interference structures which can significantly modify the characteristics of on-chip antennas, such as a power grid, local clock trees and data lines have been investigated using EM simulations. In the presence of a power grid, the antenna pair |S12| can be traded off for improved stability of antennas characteristics and the predictability of on-chip antenna characteristics. The radiation of a patch antenna is due to the fringing fields. The ground plane in the patch antenna decreases the coupling to near by circuits. The design of patch antenna in CMOS processes is limited by the fixed relatively low dielectric thicknesses. These limit the input resistance and efficiency. The bond wires change the radiation direction by ~13? at the distance of 50 um from a patch for 250 GHz operation and decrease the input resistance by about 4 ohm. Increasing the separation to 150 um, make the impact of bond wires negligible. A 182-GHz Schottky diode detector is demonstrated in foundry 130-nm CMOS technology. A 182-GHz AM modulator is implemented by changing the gate bias of PMOS current source of a push-push oscillator which utilizes the 2nd order harmonics. The operation is verified by the observation of 91-GHz AM signals at the fundamental using an OML harmonic mixer. The noise performance of a 250 GHz Schottky barrier diode detector with an on-chip patch antenna in 90 nm CMOS also have analyzed. To overcome the difficulties of electrical measurement techniques for submillimeter-wave circuits, optical techniques are utilized. The power and spectrum of 250-GHz and 410-GHz push-push oscillators have been measured using a bolometer (HD-3, IR Lab) and FTIR (IFS 113v, Bruker). A 250-GHz push-push oscillator with an on-chip patch antenna fabricated using a 90-nm CMOS process is demonstrated. A ring oscillator is incorporated for the generation of 250-GHz AM signals. The 125-GHz AM signal is measured using a harmonic mixer and a spectrum analyzer. The radiated second harmonic power from the patch antenna is about -32 dBm. A 410-GHz push?push oscillator with an on-chip patch antenna fabricated using low leakage transistors of a 45-nm CMOS process with 6 metal layers is demonstrated. The patch antenna size is 200 x 200 um2. The radiated second harmonic power from the patch antenna is about -49 dBm. The 410-GHz operating frequency is the highest among the transistor circuits fabricated in any technology including the III-V technologies. These suggest the possibility of CMOS THz systems.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Thesis: Thesis (Ph.D.)--University of Florida, 2008.
Local: Adviser: O, Kenneth K.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2008
System ID: UFE0021972:00001


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CMOS MILLIMETER AND SUBMILLIMETER-WAVE COMPONENTS


By

EUNYOUNG SEOK















A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2008


































2008 Eunyoung Seok



































To my parents









ACKNOWLEDGMENTS

I would like to begin by thanking my advisor, Professor Kenneth K. O, whose constant

encouragement and patient guidance provided a clear path for my research. I would also like to

thank Dr. Gijs Bosman and Dr. William Eisenstadt for helpful suggestions and their time

commitment in serving on my committee. Also, I am grateful to Dr. David Tanner for the FTIR

measurements. Without his invaluable guidance and encouragement, this work could not have

come to fruition.

I would like to thank the former SiMICS members Dong-Jun Yang, Seong-Mo Yim,

Zhenbiao Li, J. Branch, Ran Li, Xiaoling Guo, Jose Bohorquez, Jason Branch, Jie Chen, Seon-ho

Hwang, Changhua Cao, Yu Su, Yanping Ding, Haifeng Xu, Chikuang Yu, Aravind Sugavanam,

Jau-Jr Lin. I have been quite fortunate to have worked with my colleagues Kwangchun Jung,

Swaminathan Sankaran, Ning Zhang, Chuying Mao, Hsinta Wu, Myoung Hwang, Shashank

Nallani Kiron, Wuttichai Lerdsitomboon, Dongha Shim, Kyujin Oh, Gayathri Devi Sridharan,

Minsoon Hwang, Tie Sun and Ruonan Han. The discussions with them and their advice were

immensely helpful for this work.

Much appreciation goes to Texas Instruments (TI) for funding this work. My special

thanks go to Albert Yen at UMC Inc. for chip fabrication. Thanks also go to Dr. Chih-Ming

Hung at TI and Dr. Brian A. Floyd at IBM for helpful technical discussions. I would like to

express my sincere appreciation to the Dr. Hyun Kyu Yu, Dr. Sang-Hun Chai and Dr. Jae-Sang

Cha. I am grateful to the support from UMC, IBM and TI for research support and chip

fabrication. I would also like to acknowledge the support from Al Ogden for bonding the chips

and Daniel J. Arenas for the measurements using an FTIR.

I am deeply thankful to my parents for their constant interest and support. Their love and

encouragement are the source of my strength.









Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

CMOS MILLIMETER AND SUBMILLIMETER-WAVE COMPONENTS

By

Eunyoung Seok

May 2008

Chair: Kenneth K. O
Major: Electrical and Computer Engineering

With continued introduction of new wireless applications, the available spectrum is

becoming crowded. Because of this, interests for developing circuits and systems operating at

higher frequencies have been increasing larger bandwidth and propagation properties of signals

in the frequency range from 100 GHz to 3 THz have led to the recent increase in research efforts.

For the communication over 30m, use of antennas are better than using transmission lines

at the frequency above 60 GHz. Use of on-chip antennas at high frequencies makes systems

compact and lower cost, as well as potentially improve their performance. The impact of realistic

metal interference structures which can significantly modify the characteristics of on-chip

antennas, such as a power grid, local clock trees and data lines have been investigated using EM

simulations. In the presence of a power grid, the antenna pair IS121 can be traded off for improved

stability of antennas characteristics and the predictability of on-chip antenna characteristics.

The radiation of a patch antenna is due to the fringing fields. The ground plane in the patch

antenna decreases the coupling to near by circuits. The design of patch antenna in CMOS

processes is limited by the fixed relatively low dielectric thicknesses. These limit the input

resistance and efficiency. The bond wires change the radiation direction by -13 at the distance









of 50 |tm from a patch for 250 GHz operation and decrease the input resistance by about 4 Q.

Increasing the separation to 150 |tm, make the impact of bond wires negligible.

A 182-GHz Schottky diode detector is demonstrated in foundry 130-nm CMOS

technology. A 182-GHz AM modulator is implemented by changing the gate bias of PMOS

current source of a push-push oscillator which utilizes the 2nd order harmonics. The operation is

verified by the observation of 91-GHz AM signals at the fundamental using an OML harmonic

mixer. The noise performance of a 250 GHz Schottky barrier diode detector with an on-chip

patch antenna in 90 nm CMOS also have analyzed.

To overcome the difficulties of electrical measurement techniques for submillimeter-wave

circuits, optical techniques are utilized. The power and spectrum of 250-GHz and 410-GHz

push-push oscillators have been measured using a bolometer (HD-3, IR Lab) and FTIR (IFS

113v, Bruker). A 250-GHz push-push oscillator with an on-chip patch antenna fabricated using a

90-nm CMOS process is demonstrated. A ring oscillator is incorporated for the generation of

250-GHz AM signals. The 125-GHz AM signal is measured using a harmonic mixer and a

spectrum analyzer. The radiated second harmonic power from the patch antenna is about -32

dBm. A 410-GHz push-push oscillator with an on-chip patch antenna fabricated using low

leakage transistors of a 45-nm CMOS process with 6 metal layers is demonstrated. The patch

antenna size is 200 x 200 tmm2. The radiated second harmonic power from the patch antenna is

about -49 dBm. The 410-GHz operating frequency is the highest among the transistor circuits

fabricated in any technology including the III-V technologies. These suggest the possibility of

CMOS THz systems.









CHAPTER 1
INTRODUCTION

1.1 An Overview of Millimeter and Submillimeter-Wave Technology

As more wireless services continue to be introduced, the available spectrum becomes

crowded. Because of this, there has been a trend of developing circuits and systems operating at

higher frequencies where wider bands are available. In 2001, the Federal Communications

Commission (FCC) set aside a continuous block of 7 GHz of spectrum between 57 and 64 GHz

for wireless communications. The unlicensed 7-GHz bandwidth is wide enough to accommodate

high data rate communications such as wireless gigabit Ethernets, wireless USB's, and wireless

high definition televisions (HDTV) [1]. A 76-77 GHz frequency band is assigned for automotive

radars. Automotive radars are employed in advanced cruise control systems, which can actuate

accelerators and brakes to control the distances of other vehicles [2]. Imaging systems operating

around 94 GHz have been used for medical applications and observations of earth atmosphere

[3]. The millimeter-wave imaging systems can have higher resolution than microwave imaging

systems. The wide bandwidth of millimeter-wave makes it possible to communicate at high

speed and the short wavelength of millimeter-wave makes automotive radar and imaging systems

compact.

The potential bandwidth and propagation properties of carriers in the frequency range from

300 GHz to 3 THz have led to the recent increased investment and research in terahertz

technology. The major interest in terahertz technology is almost exclusively with the radio

astronomy [4]. The rotational energy level of important molecules in biology and astrophysics,

such as water, oxygen, chlorine and nitrogen compounds are in the terahertz range [5]. These

levels can be used to unambiguously to identify these molecules in remote environments. Radio

astronomers have identified hundreds of molecules in space and have thereby gained a great









amount of understanding of the structure and dynamics of the Universe, particularly with regard

to the formation of stars in molecular clouds [6], [7]. There are now worldwide initiatives in

terahertz technology.

The uses of terahertz in advanced imaging, and bio-agent and chemical detection [4], [6]

have been extensively studied. Its ability to penetrate objects enables the imaging systems to

detect concealed weapons. Chemists use terahertz spectroscopy to study the structure and

dynamics of a wide range of molecules. Other applications of terahertz technology include

plasma diagnostics, studies of solid-state physics, compact range radars and more recently

studies of biological macromolecules, such as DNA and proteins. In addition, terahertz radiation

is nonionizing radiation, therefore health risks are minimal. These characteristics are due to the

unique electromagnetic properties of terahertz radiation and can not be duplicated in other

regions of the spectrum [6].

A key limitation for wide scale utilization of millimeter-wave systems is the high cost of

circuits. Additionally, industrial and commercial applications of millimeter-wave require

compact and portable systems. Integration of transmitters, detectors, and on-chip antennas [8], as

well as, baseband digital signal processing (DSP) circuits in CMOS should allow single-chip

realization [8] of compact and low cost millimeter and sub-millimeter-wave systems.

The development of terahertz technologies is impeded by the lack of standards and the

inability to perform precise measurements to characterize noise, power, dielectric constants, and

scattering parameters of systems and components operating at terahertz [9]. Optical measurement

techniques and microwave measurement techniques are both required for terahertz systems.

Power can be measured using a bolometer and frequency spectrum of the circuits can be

measured using a Fourier transform infrared spectroscopy (FTIR).









Advanced CMOS technology and frequency doubling techniques are key factors for the

implementation of millimeter and sub-millimeter-wave VCO's. Figure 1-1 shows the required

fmax and fT of transistors in various technologies. The measured fmax and fT of an NMOS

transistor [63] of a 65-nm CMOS technology are plotted. The required fmax of NMOS transistor

becomes higher than SiGe technology in 2011. The required fmax based on the international

technology roadmap for semiconductors (ITRS) reaches over 1THz around 2010 and suggests

the possibility of CMOS THz systems.

The carrier transport in Schottky diodes only relies on the majority carrier conduction, in

contrast to that in p-n junction diodes where the carrier transport involves both the minority and

majority carrier. Since there are no minority carrier storage effects, these devices are potentially

capable of operation up to the frequencies approaching the reciprocal of dielectric relaxation

time of the semiconductor crystal [15]. However the series resistance and junction capacitance

typically limit the high frequency capability before reaching the limit set by the dielectric

relaxation. Schottky diodes with a cutoff frequency of greater than 1 THz have been

demonstrated in the UMC 130-nm digital CMOS process [16]. Using such diodes, it should be

possible to implement detectors operating in the high end of millimeter-wave to lower end of

sub-millimeter-wave range in CMOS.

1.3 Overview of the Dissertation

This research focuses on the design and characterization of millimeter-wave and sub-

millimeter-wave transmitters and Schottky diode detectors. The primary goal is to demonstrate

the feasibility of implementing the components including antennas. Instruments using traditional

microwave measurement techniques are not available for terahertz measurements, so a

combination of optical measurement techniques and microwave measurement methods must be

used to characterize the sub-millimeter-wave transmitters and diode detectors. This research also









seeks to investigate the feasibility of implementing circuits for future terahertz radios, sensor

networks, and imaging systems using CMOS technology.

Since on-chip antennas are necessary components, antenna structures that can be fabricated

in silicon substrates are investigated and presented in chapters 2 and 3. Chapter 2 discusses on-

chip dipole antennas. It is found that these characteristics are strongly influenced by near by

metal structures [17]. In order to enable circuits and system design with these constraints, a set of

design rules for increasing the predictability of on-chip antenna characteristics are developed and

presented. Various interference structures are discussed and their impact on on-chip antenna

characteristics are studied. The impact of on-chip metal interference structures, such as power

grids, local clock trees and data lines to on-chip antennas performance has been investigated

using Ansoft High Frequency Structure Simulator (HFSS).

Chapter 3 reviews the fundamentals of patch antennas. The key parameters of patch

antennas are discussed. There are limitations on antenna performance when the patch and dipole

antennas are implemented in a CMOS technology. A 3-D electromagnetic simulator is used to

compare with the theoretical analysis. The results clearly show the factors which limit the

performance of on-chip antenna fabricated in CMOS technology. Patch antennas also have

interference phenomenon with metal lines in near fields region. Design rules should be defined

for optimum performance while keeping the chip area acceptable. Also bond wires and packages

are need for systems. The minimum allowable distance between antenna and bond wire are

discussed.

Chapter 4 describes the design of sub-millimeter-wave detectors. The basic set of detector

parameters, tangential sensitivity, responsivity, and noise equivalent power (NEP) are reviewed.

Optimization and trade-off of detector design for better sensitivity are presented. Since sub-









millimeter-wave sources are not widely available, the amplitude modulated VCO has been

designed and described. Design and analysis of a 250 GHz Schottky barrier diode detector with

an on-chip patch antenna in 90nm CMOS also has been discussed in chapter 4.

Instruments using traditional microwave techniques are not widely available for THz

oscillator measurements. The optical measurement techniques are presented in chapter 5. The

basics of the Michelson interferometer are presented to describe the operating principle of FTIR

system. The FTIR system can specify spectrum of millimeter-wave and submillimeter-wave

oscillators. Using a bolometer and a lock-in amplifier, power of the THz oscillator can be

measured.

Chapter 6 reviews the fundamentals of VCO. The design and measurements of 250GHz

push-push VCO with an on-chip patch antenna is presented. Also a 410GHz push-push oscillator

with an on-chip patch antenna is discussed in chapter 6.

Finally, this research work is briefly summarized and possible future works are suggested

in Chapter 7.









CHAPTER 2
PREDICTABILITY IMPROVEMENT OF ON-CHIP DIPOLE ANTENNA
CHARACTERISTICS

2.1 Introduction

An on-chip antenna is expected to be a critical component for millimeter and sub-

millimeter-wave circuits and systems. A concern for on-chip antennas is how their characteristics

are modified by nearby metal structures [17]. The effects of metal structures near on-chip

antenna for intra-chip clock distribution system have been studied. A set of design rules for

antenna layout has been proposed to improve predictability of antenna characteristics to improve

predictability of antenna characteristics [18], [19]. To describe the performance of an antenna,

definitions of various parameters are fist presented. Definitions of antenna parameters are

specified. Antenna pair performance is compared with various transmission schemes using the

Friis transmission equation [23].

2.2 Antenna Fundamentals and Definitions

Key antenna parameters including directivity, gain, antenna input impedance, and antenna

efficiency are summarized in this section. More detailed discussions of these parameters can be

found in the references [20], [21].

2.2.1 Directivity

The directivity D and the gain G are the most important parameters of an antenna. The

directivity of an antenna is defined as the ratio of the radiation intensity (U, power per solid

angle) in a given direction from the antenna to the radiation intensity averaged over all

directions. The average radiation intensity is equal to the total power radiated by the antenna

divided by 4x7. If the direction is not specified, the direction of maximum radiation intensity is

implied. The directivity can be expressed as









D(O,q) =U(O, 'q) 4; U(, )(2.1)
Uo Pad

where, D is the directivity, Uis the radiation intensity, Uo is the radiation intensity of an isotropic

source, and Prad is the total radiated power. The directivity is a dimensionless ratio >1.

2.2.2 Gain

The gain of an antenna defined as the ratio of the radiation intensity, in a given direction,

to the radiation intensity that would be obtained if the power delivered to the antenna were

radiated isotropically. The radiation intensity corresponding to the isotropically radiated power is

equal to the power delivered to the antenna divide by 47r. The gain G of an antenna is an actual

or realized quantity which is less than the directivity D due to losses in the antenna.

G = 4 Radiation Intensity P(0, q) eD
G = 4- max = eD ,
Total Input Power P,

(2.2)

where et is the total antenna efficiency.

2.2.3 Antenna Input Impedance

Input impedance is defined as the impedance presented by an antenna at its terminals or the

ratio of the voltage to current at a pair of terminals.

Z = R, +R + jXA (2.3)

where, ZA is antenna impedance at the terminal, R, is the radiation resistance of antenna, RL is

the loss resistance of the antenna and XA is the antenna reactance at the terminal.









2.2.4 Antenna Efficiency

The total antenna efficiency et is used to take into account losses at the input terminals and

within the structure of the antenna. The losses of antennas may be caused by the mismatch with a

transmission line and I2R losses caused in the conductor and dielectric.

et = erected (2.4)

where, eris reflection efficiency (1- 2), ec is conduction efficiency and ed is dielectric

efficiency.

It's not easy to separate ec and ed sometimes. The conduction-dielectric efficiency ecd can

be used to describe antenna efficiency. The conduction-dielectric efficiency ecd is defined as the

ratio of the power delivered to the radiation resistance R, to the power delivered to R, + RL.


ecd R R (2.5)


2.2.5 Bandwidth

The bandwidth of an antenna is defined as the range of frequencies within which the

performance of the antenna with respect to some characteristics conforms to a specified standard.

The bandwidth can be considered to be the range of frequencies, on either side of a center

frequency (usually the resonance frequency, pattern, beamwidth, polarization, side lobe level,

gain, beam direction, radiation efficiency) are within an acceptable value of those at the center

frequency. For broadband antennas, the bandwidth is usually expressed as the ratio of the upper-

to lower frequencies of acceptable operation. For example, a 10:1 bandwidth indicates that the

upper frequency is 10 times greater than the lower. For narrow bandwidth antennas, the

bandwidth is expressed as a percentage of the frequency difference (upper minus lower) over the

center frequency of the bandwidth. For example a 5-% bandwidth indicates that the frequency









range for acceptable operation is 5 % of the center frequency. Because the characteristics (input

impedance, pattern, gain, polarization, etc) of an antenna do not necessarily vary in the same

may, there is no one bandwidth for antenna. Usually there is a distinction made between pattern

and input impedance variations. Accordingly pattern bandwidth and impedance bandwidth are

separately specified to emphasize this distinction.

2.3 Signal Transmission Using Antennas and Transmission Lines

Antennas are transducers designed to transmit or receive electromagnetic waves.

Alternatively, electromagnetic energy can be transported using transmission lines. At low

frequencies and short distances, transmission lines are practical. But at high frequencies and long

distances, use of antennas can be better because of available bandwidth. If a transmission line is

used to send signal between a transmitter and a receiver, the power loss in a transmission line is

proportional toe 2". R is the communication distance and a is the attenuation constant of a

transmission lines. If antennas are used in a line of sight configuration, the received power is

proportional to 1/R2. As the distance increases at high frequencies, the signal losses and the

costs of using transmission lines become large, and thus the use of antennas can be advantageous

over use of transmission lines [21], [22].

Figure 2-1 shows the attenuation cased by antenna pairs and transmission lines. The

attenuation constant of microstrip, coaxial cable, and waveguide are assumed to be 60, 13, and 3

dB/meter respectively. Antenna gain is 4 dBi. The Friis transmission formula [23] is used to

compare power transfer using antennas and using transmission lines at 60 GHz.

pGG (2.6)
(4rR)2

P, and Pt are received power at a receiver antenna and transmitted power from a transmitter

antenna respectively. Gt and G, are the gain of the transmitter and receiver antenna. The equation









addition, to reduce the size of on-chip antennas, a much higher global clock frequency which is

about 20 GHz is generated by the transmitter and used as the global clock. Because of this, at the

receiver side, the high frequency global clock is divided down to a lower frequency for local

clocking [28].

On-chip antennas could also be used in communication links for sensor networks, radio

frequency identifiers (RFID's), and single chip radars. On-chip antennas/inductors have also

been used as near field couplers in RFIDs [8]. In all these applications, on-chip antennas are co-

located with circuits and the associated interconnects such as power grids, clock trees, and data

lines. An on-chip antenna is also expected to be a critical component for millimeter and sub-

millimeter-wave circuits and systems. A concern for on-chip antennas is how their characteristics

are modified by nearby metal structures [17]. Because of this, the effects of metal structures near

on-chip antenna for intra-chip clock distribution system have been studied. The metal structures

significantly affect the on-chip antenna characteristics, such as gain, phase, and antenna input

impedance [17], [18]. Approaches to better guarantee the characteristics of on-chip antennas are

critical to provide predictability for the design community. The impact of power grid on the char-

acteristics of on-chip antennas has been presented. The metal structures near an on-chip antenna

in the presence of a power grid have greatly reduced impact on antenna characteristics.

Exploiting this, a set of design rules for antenna layout has been proposed to improve

predictability of antenna characteristics [18], [19].

2.5 Antenna Measurements and Simulations

The Finite Difference Time Domain Method (FDTD) and Finite Element Method (FEM)

have been used for evaluation of a power grid [29] and other interference structures for on-chip

antennas [30]. In order to validate the simulation results, a set of representative test structures

consisting of 2-mm long linear dipole antenna pairs and varying interference structures have









The width and pitch of power lines are 250 itm. Figure 2-9 shows some of the simulated

power line structures. Figure 2-10 shows the simulated results. The parallel metal lines in Figure

3-10(a) decrease IS121 by 25 dB at 24 GHz. The perpendicular structure in Figure 2-10(b)

increases IS121 by 6 dB and decreases the imaginary part of input impedance by 8 Q. The power

grid shown in Figure 2-10(c) decreases gain by 18 dB and changes input impedance from 52 to

42 Q. The structures with the parallel power lines and power grid in Figure 2-10 have similar

input impedance, because the near field interaction is dominated by the parallel lines. 20-[tm

wide data lines are placed in metal 3 layer as shown in Figure 2-10(d). The length of data lines is

2 mm, separation is 20 |tm, and distance to antenna is 1.5 mm. Compared to the simulation

results for the structures in Figures 2-9(c) and (d), the input impedance, gain, and phase of this

structure show little difference. When the polarization of the incident wave is parallel to a

densely packed wire grid, the reflection coefficient for the wire grid is close to -1. The power

grid acts like a metal plate reflecting incident waves, therefore data lines have relatively small

effects on the antenna performance.

Input impedance, and magnitude and phase of S12 for antenna pairs (5-mm separation) are

simulated at varying separations between the power grid and antenna at 24 GHz. Figure 2-11

indicates that IS121 (dB) linearly depends on Dl and D2 in Figure 2-9. The power grid has

significant effects on the characteristics of on-chip antennas. Compared to the control case, IS21

is reduced by -20 dB. This is due to the destructive interference effects of reflected waves from

the power grid. This is indeed a significant reduction. However, much of this can be recovered

by using an A1N propagating layer in conjunction with antennas on thinned substrates. It has

been shown recently that the gain can be improved by 10, 15 and 20 dB for 0.5, 1 and 2-cm

antenna pair separations [17] over the best previously reported results by thinning the substrate









Table 2-1. Simulation results of antenna pairs at 24 GHz in the presence of interference
structures shown in Figure 2-13.
Structure Real(Z11) Im (Z1) |S12|(dB) Phase()

(a) 42.6 -30 -60.4 40
(b) 41.8 -34 -60.2 43

(c) 42.8 -30 -60.5 36
(d) 40.5 -26 -60.2 27


The power grid acts like a metal plate reflecting incident waves, so data lines, the local

clock trees, and dummy fills have relatively small effects on the antenna performance. The

simulation results are listed in Table 2-1. For the wireless clock distribution system, because the

transmitted clock is frequency divided by 8, the phase variations of 1% of a period or skew for

the actual clock correspond to 28 degrees for the transmitted clock signal. One percent is one-

tenth of the typical skew/jitter tolerance and this can be used as the criterion to determine

acceptability of variations. Based on this, all the structures in Table 2-1 are acceptable. The

presence of a power grid reduces S12L, however it makes the antenna characteristics to be almost

independent of other metal structures. This allows definition of a relatively simple set of design

rules for on-chip antennas. Table 2-2 lists the design rules when followed should make on-chip

antenna characteristics more predictable.









Table 2-2. Design rules.
Wide power lines directly over antenna should be avoided in region A. Dl and
D2 are 255 tm and 275 tm.

2 Any metal structures can be placed in region B.

3 Perpendicular metal lines to antenna off by 200 [tm away are acceptable (Figure
2-12).

To run multiple perpendicular metal lines over antennas, the characteristics of
antennas must be simulated using an EM software.
Short (length < 100 utm, width < 20 utm, and space > 20 utm) discontinuous
5 metal lines are acceptable in the region A. These lines can be connected to
transistors.

6 Local clock trees can be placed over the area A and B.

7 Dummy fills (size: 10 tm x 10 utm and space > 10 utm) are acceptable in regions
A and B

2.8 Summary

The signal transmission using transmission line and antennas are compared. At millimeter

and sub-millimeter-wave frequencies, use of antennas for information transmission has

advantage over use of transmission lines. The impact of realistic metal interference structures

which can significantly modify the characteristics of on-chip antennas, such as a power grid,

local clock trees and data lines have been investigated primarily using EM simulations. In the

presence of a power grid, the antenna pair |S121 can be traded off for improved stability of

antenna characteristics. This can be exploited to define a set of design rules to improve the

predictability of on-chip antenna characteristics in the presence of other metal structures.









CHAPTER 3
PATCH ANTENNAS IN CMOS TECHNOLOGY

3.1 Advantages of On-Chip Antennas for Submillimeter-Wave System

As the operating frequency is increased, wavelengths of electromagnetic waves and

antenna sizes become smaller. Use of on-chip antennas at the upper millimeter and sub-

millimeter-wave frequencies need to occupy a small chip area and avoids the difficulty of

interconnection between on-chip components and an external antenna. The parasitic inductance

of bond wires for making the connection between on-chip components and an external antenna

impedes signal transmission as well as causing coupling between bond wires. Since bond wires

can cause unwanted resonance and radiation, they can degrade stability and cause

electromagnetic interference with other chips and systems. On-chip antennas can make systems

compact and reduce the loss and coupling problems caused by the bond wires.

On-chip antennas can be co-located with digital and analog circuits, which is a key

technology for realizing a true single chip radio [8]. For sensors, radars and imaging systems

digital signal processing is necessary. For spectroscopy, Fourier transformation is needed to

detect and increase sensitivity to molecules with multiple resonant frequencies [32]. Digital

signal processing techniques can increase the resolution of radar and imaging systems. The

precise control of physical dimensions in CMOS integrated circuits results high yield of

millimeter-wave arrays with a large number of elements, which is necessary to lower cost.

3.2 Fundamentals of Microstrip Patch Antenna

As discussed in chapter 2, the performance of dipole antennas is significantly degraded by

the conduction in the substrate. Conductivity of silicon substrates used in CMOS fabrication is

about 2 to 20 f-cm. The energy in the reactive near field around the antenna is dissipated by the

conductive silicon substrate. In addition, the characteristics of dipole antennas are significantly









affected by metal structure near the antennas. The technique to make antenna characteristics

more predictable proposed in chapter 2 degrades antennas gain. The options are limited for intra-

chip communications. For inter-chip applications, especially when the desired signal

transmission is perpendicular to the chip surface, there is a better option. The loss caused by the

conductive silicon substrate can be avoided by putting a metal plate between the antenna and

silicon substrate, although this metal plate increases capacitance and decreases radiation

efficiency. A patch antenna [21] is consistent with these. In addition, the ground plane reduces

the impact of near by metal structures on the antenna characteristics.

Microstrip antennas are popular with antenna engineers for their low profile, for the ease

with which they can be configured to specialized geometries, and low cost when produced in

large quantities [21]. Figure 3-1 shows an edge-fed microstrip antenna. At the bottom, there is a

ground plane, and a dielectric substrate separates the patch and ground plane. A rectangular

patch is fed from a microstrip transmission line. The patch length is about half wavelength. The

substrate thickness "h" is much less than a wavelength. The patch antenna belongs to the class of

resonant antennas and its resonant characteristic is responsible for the narrow bandwidth [21].

The radiation from microstrip antennas occurs from the fringing fields between the edge of the

microstrip antenna conductor and ground plane. The fringing fields act to extend the effective

length of the patch. Thus, the length of a half-wave patch is slightly less than a half wavelength

of dielectric substrate material.









electric fields that are of opposite phases. Therefore, the total fringing fields at the edges are 1800

out of phase and equal in magnitude. The peak radiation is in the +z direction. The radiation edge

can be thought as a slot. The width of a slot is often taken to equal to the substrate thickness. The

patch radiation is linearly polarized in the x-z plane, that is, parallel to the electric fields in the

slots.

The radiation pattern of a rectangular patch antenna is rather broad with the maximum

direction normal to the plane of the antenna. Pattern computation for the rectangular patch is

easily performed by first creating equivalent magnetic surface currents.

M, = 2E, x n, (3.2)

where, E, is the fringe electric field in each of the edge slot.

The factor of 2 comes from the image of the magnetic current in the electric ground plane.

The far-field components are

E, = E, cos O f(0, )(3
E = -Eo cos 0 sin f(0, 0)'

where,


sin f8W sin 0 sin q
f(0,= ) 2cos ( -sin 0cos (3.4)
-W sin 0 sin 2
2

p is the usual free-space phase constant and equal to (2;r /A). The first factor in equation

(3.4) is the pattern factor for a uniform line source of width W. The second factor is the array

factor for a two-element array along the x-axis corresponding to the edge slot [21].

Typical input impedances at the edge of a resonant rectangular patch range from 100 to

400 Q. An approximate expression for the input impedance of a resonant edge-fed patch is









Increasing the dielectric constant decreases the wavelength in the dielectric and decreases the

resonant frequency at given patch size. The changes in dielectric constants do not significantly

modify the trajectory in a smith chart and rotate the trajectory.

3.3 Microstrip Patch Antennas on CMOS Technology

Dielectric layers in a CMOS process have various thicknesses and dielectric constants.

Antenna simulations solve a structure with dimensions on the order of a comparable with

wavelength. For example a dipole antenna has a half wavelength and the surrounding air box is

about 3/4 wavelength. So, simulation structures are bigger than that for discrete devices such as

capacitors and inductors. It is not efficient in time to include all dielectrics in EM simulation.

Sometimes, it is not possible to include all the dielectric layers. An effective dielectric constant

can be used in simulations.

First, a small section of a microstrip with all the dielectric layers can be simulated and

propagation constant and characteristic impedance of the microstrip can be extracted. Second, a

small section of a microstrip using a dielectric layer with an effective dielectric constant can be

simulated. Propagation constant and characteristic impedance can be matched with the microstrip

with all the dielectric layers by adjusting the effective dielectric constant.

3.3 The Impact of Bond Wires on On-Chip Patch Antenna Performance

As discussed at chapter 2, a concern for on-chip antennas is how their characteristics are

modified by nearby metal structures. The interference study in chapter 2 shows that the metal

structures significantly affect the on-chip antenna characteristics, such as gain, phase, and

antenna input impedance and the impact on on-chip antenna performance increases with the size

of metal structures. Approaches to guarantee the characteristics of on-chip antennas are critical

for communication circuits and systems with on-chip antennas. The ground plane of the patch









To study this, the effects of bond wires near on-chip antenna have been simulated. The Ansoft

HFSS has been used for this purpose. Three bond wires are place near an on-chip patch antenna.

The bond wire length is about 1mm in Figure 3-7. The distance from the bond wires to antenna

has been changed and the antenna input impedance, resonant frequency, directivity, efficiency

and radiation pattern have been simulated. Figure 3-8 shows the input resistance of on-chip patch

antenna with varying distance to bond wires from 50 to 450 |tm with 100 |tm steps. The input

resistance maintains about 101 Q for spacing greater than 150 |tm. The input resistance becomes

97 Q at 50 |tm.

Figure 3-9 shows on-chip patch antenna directivity with varying distances to bond wires.

The directivity is about 5 down to 250 |tm. It gradually decreases and reaches 4.3 at 50 |tm. The

efficiency of patch antenna is about 32 % for all cases. Figure 3-10 shows the radiation pattern of

patch antenna with varying distances to bond wires at 4=00. Ideally, direction of peak radiation

is normal to antenna patch antenna surface (4t=0, 0 =0 ). The maximum radiation directions are

3600 (0), 3590, 356, 351, 347, 3400 at the distances of 450, 350, 250, 150, 50 |tm, respectively.

3.4 Summary

This chapter presented the basic properties of patch antenna. The radiation mechanism of

radiation on patch antenna is discussed and the simple equations for the patch antenna size and

input impedance are presented. The design of patch antenna in CMOS processes is limited by the

fixed dielectric layer thickness, which limits the input resistance and efficiency. The impact of

bond wires on on-chip patch antenna performance is presented. The bond wires change radiation

direction by -13 at the distance of 50 |tm and decrease the input resistance by 4 Q. The

minimum distance from antenna to the bond wires can be set to 150 |tm based on input resistance

changes.









CHAPTER 4
MILLIMETER-WAVE SCHOTTKY DIODE DETECTORS IN CMOS TECHNOLOGY

4.1 Introduction

The uses of millimeter and sub-millimeter-waves in radars, remote sensing, advanced

imaging, and bio-agent and chemical detection [4], [40] have been extensively studied. A key

limitation for wide scale utilization of these is the high cost of circuits. A 182-GHz Schottky

diode detector fabricated in foundry 130-nm CMOS technology is presented in this chapter. The

design of a Schottky barrier diode detector with an on-chip patch antenna in 90nm CMOS

process also discussed. Integration of those type of detectors with an on-chip antenna and

baseband electronics in CMOS should allow single-chip realization of low cost millimeter and

sub- millimeter-wave systems [33].

4.2 A Schottky Barrier Diode in CMOS Technology

Schottky barrier diodes due to their high operating frequencies and a low forward-voltage

drop have been widely used. Operation of the Schottky barrier diode depends only on the

majority carrier conduction, in contrast to p-n junction diodes which rely on both majority and

minority carriers for their operations [16]. The series resistance and junction capacitance

determines the frequency response for Schottky diodes. Schottky diodes with a cutoff frequency

greater than 1 THz have been demonstrated in the UMC 130-nm digital CMOS process [16]. The

diodes are formed by blocking n+ implant over selected diffusion regions in a n-well. The

formation of diode requires no modifications to the existing CMOS flow [16]. A cross-section of

a representative Schottky barrier diode cell is shown in Figure 4-1. A CoSi2-Si junction forms the

Schottky diode. Ohmic contacts around the Schottky contact form the second terminal. To

improvefutoff given in (4.1), both the series resistance Rs and the capacitance Co must be lowered

[16].









n-terminal p-terminal Schottky metal
S/ Barrier
Contact





STI ....t* STI STI In STI


n-well
p-substrate

Figure 4-1. A Schottky diode implemented in CMOS process.

To minimize R, at given Co, the diode is formed by parallel connecting minimum area

Schottky contacts (0.32 x 0.32 am2)

1
f cff = 1 (4.1)
fc 2 27xR x C(4.1)

Using such diodes, it should be possible to implement detectors operating in the high end

of millimeter-wave to the lower end of sub-millimeter-wave bands. To investigate this, a detector

operating -180 GHz has been implemented in the 130-nm CMOS process using a diode formed

with 16 of the 0.32 x 0.32 |tm2 cells connected in parallel. The series resistance of the Schottky

diode is about 10 Q and junction capacitance is 12 fF at zero bias.

4.3 Sensitivity Analysis of Schottky Barrier Diode

The tangential sensitivity and noise equivalent power (NEP) are used to describe detector

performance. Noise equivalent power is defined as the RF input power required to produce an

output signal-to-noise ratio of unity, for signal with a bandwidth of the square root of one hertz

[34]. The assumption of unit bandwidth is useful for examining devices operating at video

frequencies in the /f noise region. Tangential sensitivity (TSS) is the lowest signal power level









for which the detector will have a specified signal-to-noise ratio at the output. Agilent

Technologies specifies TSS at the output signal-to-noise ratio of 8 dB. The units for TSS are

dBm or milli-watts.

In this chapter, the basic operation of detectors is reviewed [34], [35]. The noise equivalent

power is derived as a function of the ideality factor (n), series resistance (Rs), and junction

capacitance (CB). The noise equivalent power and tangential sensitivity are related to each other,

and these parameters entirely depend on the ideality factor, series resistance and junction

capacitance. The derivation shows the relation. It was assumed that all of the available RF power

is absorbed by the device. The current-voltage function of a nonlinear device can be denoted by

i = f(v), (4.2)

and

v = V0 + Acoscot, (4.3)

where, V, is dc bias voltage and ac input voltage is A cos ot.

Expanding (4.2) with a power series around V, and substituting (4.3)

i = f(v) = f(V, + A coso)t) (4.4.1)


= f(Vo)+ f l(V)(Acosot)+ f(( (AcosCot)2 + (Acosot)3
2 6 (4.4.2)
+ (((AcosCot)4 + (Acosot)5 + ..
24 120


= f(Vo) + f (Vo)(A cos cot) + f(2() V A(1 + cos 2ct) +
2 2 (4.3.3)
f' '(VF) A' f (4) (V) 3 3+ 4cos 2t+cos4ot
(3cos at + cos 3mt)+ A (------ )...
6 4 24 8


i-f(V) =i- = f) + f(4) + Af(1) + f(3) cost+... (4.4.4)
4 64 8 1








The average ac power, P absorbed by the device can be found by multiplying (4.4.4) with

the input voltage, A coso t and integrating over one period. This leads to the following

expression for P

(i- I)(v -V)= (i- I)A coscot (4.5.1)

=A f) + f Acoscot+ Af(+ f3 A(+cos 2t)... (4.5.2)
4 64 1 8 _2


=[A f)+ A f(4) Acosct + Af(+ A f() Acos ot ... (4.5.3)
4 64 1 8

P= f (v_ Vo).- i dt f(1) + (4.5.4)
T 0 8

The first term in the bracket on the right-hand side of (4.4.4) is the detected current Ai, the

time average of quantity incrementally increased due to the application of ac power. The ratio of

Ai to P is called the current responsivity and can be written as.

A L (2) + f(4)
Ai 4 64
= P =2 (4.6.1)
PA A1
P A f (1) + f(3)
2 8

SA2 f(4)
1+
1 f(2) 16 f(2)
(4.6.2)
2 f + A2 f(3)
8 f(1)


=/0 1+82 (4.6.3)
1+A2



1 f(2) A2 f(4) A2 f(3)
where, /0 2 f(1) 8 f,
162ffl 1 8 fU1)








The part of power absorbed in the device is dissipated in the parasitic series resistance Rs.

A simple analysis of the equivalent circuit in Figure 4-2 yields the following relation for the ratio

of the power absorbed in RB (PB) to the total RF power, P

P=V2 (,+Rsw2CB2R,2Rs) (4.11)
2 (RB + RS) +( CBRBRS)2

V2 RB
P (4.12)
2 (RB +RS)2 +(oCBRBRS)2

PB= RB 1 (4.13)
P R, +Rs + 2CB2R 2Rs RS r (f/f 1
RB R,


1+ Rs
where, f, =
2C, (RsR,)l/2

The ratio of Ai andPB is

Ai q 1 q (4.14)
PB 2nkT 8 nkT(lo +Is)

and

Ai q 1
='8 =, (4.15)
P 2nkT[+ Rs][i (fIf2]


where, fP is the low-level current responsivity for the device.

In order to calculate the sensitivity of Schottky diode, the noise properties of device must

be known. Schottky diodes exhibit 1/f noise, in addition to white noise. The noise of Schottky

diodes can be characterized in terms of noise temperature ratio t.

The incremental detected current corresponding to a given input power P is simply










Tangential sensitivity (TSS) is the lowest signal power level for which the detector will

have a specified signal-to-noise ratio at the output. TSS can be expressed in (4.20), where B is the

bandwidth of signal.

TSS, = ENP + 8 + 5 log B (dBm) (4.20)


N4


0Z
LU
Z~


2 3 4 5 6 7 8 9 10
Number of cells


Figure 4-4. NEP (pW/Hzl/2) with various number of cells.

The NEP mostly depends on the diode characteristics. For a given diode, NEP and TSS can

be calculated. The junction barrier resistance and capacitance are bias dependent, so the optimum

bias point can be determined. Also, there is flexibility of choosing the number of diode cells and

area of the Schottky diode cell in CMOS. The remaining parameters for the detector design are

the number of cells and diode bias voltage. Figure 4-4 shows the NEP at the various number of

0.32 x 0.32 |tm2 Schottky diode cells in the 130-nm CMOS. The NEP varies from 2 to 5

pW/Hz1/2 and the minimum number of cells shows the lowest NEP of 2.3 pW/Hz/2. The


_









capacitance is a dominant factor in NEP calculation at 250 GHz. The structure with the minimum

number of cells has the smallest capacitance and has the best NEP calculated using (4.19). The

frequency is 250 GHz, the ideality factor (n) is 1.3, the white temperature ratio (tw) is 1.2 [34],

the series resistance (Rs) is 13 Q, the noise comer frequency is (fN) is 1 VMHz, and the video

frequency (fv) is 10 VMHz in the NEP calculation. The junction capacitance increases with bias

voltage. The absorbed power (PB) decreases with the increase of the capacitance and the NEP

decreases. The RB decreases with bias voltage from 2380 to 300 Q when the applied bias

changed from 0.2 to 0.5 V. The absorbed power increases with bias voltage when the junction

capacitance effect is neglected. So, the optimum bias voltage can be found. Figure 4-5 shows the

NEP at various bias voltage of diode. The figure shows the minimum point at 0.35 V and NEP is

about 2 pW/Hz1/2. Figure 4-6 shows thefc at various bias voltage of diode. Thefc is defined in

(4.13) and included in NEP. When the operating frequency of the detector is f, the absorbed

power by the junction barrier is half of RF power (P). Thef, in Figure 4-6 has highest value at

0.4 V and the lowest NEP is at the bias voltage of 0.35 V. The minimum number of cells and

optimum bias point is required to obtain the lowest NEP for a given Schottky barrier diode cell.



















-"'

I
















Figure 4-5.












N
-C
0





























u0
r -
C.)














Figure 4-6.


0.2 0.25 0.3 0.35 0.4 0.45
Diode Vias (V)


NEP (pW/Hz1/2) with varying diode bias voltage.


0.35
Diode Vias (V)


f, with varying diode bias voltage.









C7 is a 400-fF capacitor and its impedance is close to short at 180 GHz, so C7 provides isolation

to RF. It is straight forward to design the input matching circuits, when the diode is followed by

a low pass filter.

To evaluate the detector, a source for modulated 180-GHz signal is needed. Since, such a

source is not widely available. A 180-GHz signal generator has been integrated with the detector.

CMOS millimeter-wave VCO's with -100-GHz fundamental operating frequency have been

reported [10]. To obtain even higher frequencies, push-push topologies have been utilized to

achieve operation at 131 [36] and 192 GHz [11] in 90 and 130-nm CMOS technologies. To the

192-GHz VCO, buffers (M3-M6) are added to monitor the fundamental output (Figure 4-6). This

lowers the frequency at push-push port to -182 GHz. The amplitude of this VCO is modulated

by changing the gate voltage of M7, or the bias current (Ibias) of the oscillator. The modulating

signal is AC-coupled to M7 through a capacitor (C3). A shunt 50-Q (Ri) termination resistor is

added to make the input amplitude at gate of My more predictable. The bypass capacitor, C4 is an

AC-short for the signal near 180GHz, while it presents high impedance for the modulating

signal. Since changing Ibias also modifies the drain voltage of VCO core transistors thus the

capacitances of L-C tanks [11], the input signal should also modulate the output frequency.

4.4.2 Experiment Results

Figure 4-8 shows the voltage waveforms of modulation and detected signals across a 50 Q

load, when the VCO is modulated with a 10 MHz sine wave with 0.1 V amplitude. VDD of VCO

is 1.75 V. The dc bias voltage at gate of My (Vbias) is 0 V. The 10-MHz input frequency is chosen

to attenuate the un-intended feed through of modulation signal through C5 (50fF). The detected

signal frequency is the same as that for the modulation signal. Figure 4-8 also shows the voltage





































Figure 4-15.





N
I
-1-





0


CU
05
z



U,









Figure 4-16.


10-1 100 101
Frequency (MHz)

Voltage gain of amplifier with various load capacitors.


10-1 100 101
Frequency (MHz)

Equivalent input noise of amplifier.









Figure 4-18. Series resistance and capacitance at zero bias of Schottky diode.


Ohmic


Schottky
Contact


Insulator


n-well


Figure 4-19. Cross section of the Schottky barrier diode.


0 50 100 150 200 250
Frequency (GHz)


300 350 400


Figure 4-20. Calculated tangential sensitivity of the detector.









CHAPTER 5
OPTICAL MEASUREMENT METHODS FOR MILLIMETER AND SUBMILLIMETER
WAVE OSCILLATORS

5.1 Introduction

The measurement of submillimeter-wave oscillator is challenging. The output power of

oscillator typically decreases with operating frequency. The harmonics mixer loss increases with

frequency. The down converted signal could be smaller than the noise level and can not be

detected. Also, high-frequency probes are not available at THz. Off the shelf electrical probes go

up to 325 GHz. To overcome the difficulties an optical technique is utilized. Power from an on-

chip antenna can be measured using a bolometer and the frequency spectrum of circuits can be

measured using a Fourier transform infrared spectroscopy (FTIR) [37]. A combination of optical

and electronic measurement techniques is required for terahertz systems.

5.2 Bolometer

A bolometer is an instrument for detecting and measuring radiation, e.g., visible light,

infrared radiation, and ultraviolet radiation, in amounts as small as one millionth of an erg [38].

The bolometer was invented in 1880 by Samuel P. Langley. It consists of a radiation-sensitive

resistance element in one branch of a Wheatstone bridge. Changes in radiation cause changes in

the electrical resistance of the element. The radiation-sensitive element may be a platinum strip,

a semiconductor film, or any other substance whose resistance is altered by slight changes in the

amount of radiant energy falling on it, which heats the element [38]. Figure 5-1 shows a silicon

bolometer (HD-3, IR Lab) with a preamplifier. The silicon bolometer element is mounted in the

configuration in conjunction with a parabolic cone collector. The composite silicon element

mounted on a cylindrical cavity. Liquid Helium is used to cool the bolometer to 4.20K. The

change in radiation results resistance change. This will appear at the amplifier output. The optical








responsivity of the bolometer is 1.1 x 104 (V/W). The bolometer elements have limited

bandwidth and silicon bolometer elements have constant responsivity up to THz.


Figure 5-1. Bolometer with preamplifier.


100Hz JL

Figure 5-2. Power measurement using a bolometer and a lock-in amplifier.

A bolometer and a lock in amplifier have been used to measure radiated power from an on-

chip antenna. The lock-in amplifier (ITHACO 393) is a homodyne receiver with an low pass

filter with extremely lower bandwidth ( -0.1 Hz) and use mixing, to convert the signal's phase

and amplitude to DC [39]. We modulated the supply (VDD) of oscillator with 100 Hz. The

modulated signals go to bolometer and lock in amplifier mixes the signal from bolometer and









CHAPTER 6
MILLIMETER-WAVE AND SUBMILLIMETER VOLTAGE CONTROLLED OSCILLATOR
IN CMOS TECHNOLOGY

6.1 Introduction

As new wireless services continue to be introduced, the available spectrum becomes

crowded. This has increased interests for wireless system at higher frequencies where larger

bandwidths are available. The uses of millimeter and sub-millimeter-waves in radars, remote

sensing, advanced imaging, and bio-agent and chemical detection [4], [40] have been studied. A

key limitation for wide scale utilization of these is the high cost of circuits. Monolithic

millimeter and sub-millimeter wave integrated circuits can provide the size, weight, and

performance advantages. Traditionally, high electron mobility transistor (HEMT) and

heterojunction bipolar transistor (HBT) MMIC technologies have been utilized in millimeter-

wave applications due to their higher power capacity and superior low noise performance.

With the rapid advance of high frequency capability of CMOS technology, it is becoming

possible to make CMOS circuits operating in the millimeter-wave frequencies [11], [41]. A

millimeter-wave CMOS VCO with 140-GHz fundamental operating frequency has been reported

[11]. For the millimeter-wave and submillimeter-wave communications, a simple transmitter can

be made using a VCO with a VDD modulation circuit and an antenna. Signals received from an

antenna can be recovered using a Schottky barrier diode detector. In this case, the oscillator

frequency determines the maximum operating frequency of the system. The communication

range is set by the output power of oscillator, when a power amplifier is not available. To design

a VCO with good phase noise performance, and acceptable output power, the fundamentals of

oscillators must be understood.









coupled transistor pair generates differential signals and eliminates the concern for even-mode

oscillation. At the virtual ground node, the differential fundamental signals are attenuated, and

the 2nd harmonic is extracted. Quarter-wavelength transmission lines provide high impedance at

the 2nd harmonic frequency. Two transmission lines and PMOS transistors are used for the

symmetry. The grounded coplanar wave guide is used for transmission line. A microstrip needs a

wider ground plane. A coplanar waveguide confines fields in a relatively small area and shows

stable characteristic impedance over a wide frequency range. Compared to a CPW, a grounded

coplanar waveguide has an additional ground plane at bottom. The ground plane isolates the

lossy silicon substrate and reduces coupling to other circuits. The signal line width is 1 lum and

gap is 3um. Simulated loss is about 1.6 dB/mm at 250GHz. The metal 1 and 2 layers are shunted

together and used for the ground plane. The pad layer is used for the signal line. The extracted

2nd harmonics at push-push node is radiated through an on-chip patch antenna.

Fully differential inverters with programmable delays are used to form a ring oscillator.

The ring oscillator in Figure 6-9 generates about 10 30 MHz square waves and turns on and off

the PMOS current source of push-push VCO and generate amplitude modulated output. The

buffer stages control the amplitude of signal from the ring oscillator. A 125-GHz AM modulate

signal is measured at the buffer output. The on-chip 30 pF bypass capacitor is used for the ring

oscillator. However, this is not sufficient at 10 MHz. An off-chip 0.1-20 pF bypass capacitors are

used on the PCB. The on-chip patch antenna is formed using a pad layer and size of patch is 330

x 315 |tm2. The ground plane of patch is formed using the metal 1 and 2 layers. The dielectric

thickness from the ground plane to patch is about 7 |tm. The width of patch is 330 |tm. The

simulated antenna efficiency is about 32 % and directivity is about 5 at 250 GHz. A 20 |tm x 40









-10


e Modulaton Off
-B- Modulaton On
-20



S-30



0 -40-



-50
I4o







-60
125 125.1 125.2 125.3
Frequency (GHz)

Figure 6-12. Output spectrum of the VCO with modulation and without modulation.

Figure 6-12 shows the fundamental output of VCO with and without modulation. The

ring oscillator is turned on and generates square wave around 12 MHz. The carrier frequency is

shifted down about 120 MHz when the modulation is on. 125-GHz amplitude modulated signals

are measured at the fundamental output. Figure 6-13 shows the measured spectrum of the 250-

GHz push-push VCO. The 250-GHz second harmonic is generated by the push-push VCO and

radiated through an on-chip patch antenna. The spectrum is measured using an Fourier transform

infrared spectroscopy (FTIR). The 10 mil beam splitter and silicon bolometer are used in the

FTIR measurements. Only the background noise is observed when the supply voltage of VOC

was off. The second harmonic power from the antenna is about -34 dBm measured. Table 5-1

summarizes the performance of the 250 GHz VCO.


V V























5,
e -1














Figure 6-13.


Table 6-1


w me= I I w 0
50 200 250
Frequency [GHz]


Spectrum of the push-push VCO.


Summary of 250-GHz push- O


Chip size 1100 tmm x 670 |tm Patch size 330 tmm x 315 |tm
VDD 1.6 V ANT directivity 5.1
Bias current 13mA ANT efficiency 32 %

Frequency 250.4 GHz Reflection 50 Q
coefficient
Tuning range 4 GHz Fundamental -20 dBm
Power
2nd harmonic -32 dBm Technology UMC 90nm CMOS
power









S J Active
M Polysilicon
Cont


Vial
Mr =.. Metal2
G l ] Via2
Metal3



0.6rrl M2 M2 M2 M2









Figure 6-16. Layout of cross-coupled transistors.

The resistance of a contact is about 60 Q. To decrease the parasitic resistance, multiple contacts

on the transistor gates are required. Each finger has 2 contacts on each side and connected using

metal 2. The sources are connected together using the metal 1 layer. The transistors are directly

cross connected from the drain to gate using the metal 2 and metal 3 layers. The top metal layer

thickness is about 2 |tm and has larger fringing capacitance than the lower metal layers. The

lower metal layers are used to connect the transistor gates. The width of each finger is about

0.6[tm. Polysilicon dummy gates are also included for each finger.

Figure 6-17 shows the differential circular inductor used in the push-push oscillator. To

reduce the parasitic capacitance to substrate, only the top metal layer is used. The top metal layer









is about 2 [m thick and about 2 |tm above the silicon substrate. The diameter is about 20 [m and

metal width is 1.6 Gm. The skin depth of copper with conductivity of 5.25 x 107 S/m at 200 GHz

is about 0.155 [m. The metal width is about 10 times the skin depth. The polysilicon layer is

used to form a patterned ground shield. The inductance can be increased by removing the

patterned ground shield. However, the polysilicon ground shield is used to satisfy the density

rules. Metal 1 and 2 layers are used to form a ground grid. The pitch is 2.5 [m and width of each

metal layers are about 1 am. The estimation of inductance and quality factor is important to

properly set the operating frequency of the oscillator and output power. Ansoft HFSS is used for

simulation and extraction of S-parameters. The effective inductance is about 40 pH and Qconv is

about 8. This low value is caused by the skin effect and loss caused by the silicon substrate.









Figure 6-17. Structure of circular inductor for the 4-GHz oscillator.
.c ,* .,, .


















Figure 6-17. Structure of circular inductor for the 410 GHz oscillator.
,, ~.. .. ,












Figure 6-17. Structure of circular inductor for the 410-GHz oscillator.










500


450


400


350 1


30(


Figure 6-20.


0D


160 180 200 220 240
Width (W) and Length (L) of patch (pm)

Resonant frequencies of the on-chip patch antennas.


n1


401


c 30

Iu


201


2~ 3 4


2 3 4 5
Dielectric thickness (pim)

Figure 6-21. Efficiency with various dielectric thicknesses.


10I





































180 200 220 240
Width (W) and Length (L) of patch ([tm)


Figure 6-22.


Directivity and efficiency for varying sizes of patch.


x


DirTotal

4.6966e+000
4.3846e+000
4.0727e+000
3.7607e+000
3.4487e+000
3.1367e+000
2.8248e+000
2.5128e+000
2.2008e+000
1.8889e+000
1.5769e+000
1.2649e+000
9.5293e-001
6.4095e-001
3. 2898-001
1.7005e-002



Y


Figure 6-23. On-chip patch antenna radiation pattern.


t4
U,
L.


160


40



0
30 a
U,




20





10










between the resonant frequencies of patch antenna and oscillator. The output power can be
improved by using a better back-end process. The chip size is 390 x 640 itm2 in Figure 6-28. The
supply voltage is 1.5 volt and bias current is about 11 mA. When the bias current is changed
from 11 to 7 mA, the oscillation frequency of oscillator is decreased from 413 to 410 GHz in
Figure 6-30.



0.15 .,
--Power On
--Power Off
410GHz->

i 0.1




E 0.05





50 200 250 300 350 400 450
Frequency [GHz]
Figure 6-29. Spectrum of the 410-GHz push-push oscillator measured using an FTIR.









4131


8 9 10 11
Bias Current [mA]


Figure 6-30. Frequency and power of push-push oscillator at varying bias currents.


InP Fundamental
InP Push-push
SiGe Fundamental
SiGe Push-push
CMOS Fundamental
CMOS Push-push

A


410GHz VCO-+





189GHz VCO
A. o
** 0


A


1995


2000
Year


0


2005


2010


Figure 6-31. Operating frequencies of published VCO.


20



15



10
0

5


412[


4111-


4101


/in


-rAj7


o1


400 V


300 V


200


100[


1990









Operating frequencies of published VCO's with years are shown in Figure 6-31. Until 2000,

published papers used InP devices to implement millimeter-wave oscillators. SiGe fundamental

and push-push VCO's operating at the millimeter-wave frequencies were first reported around

2000. The CMOS fundamental and push-push VCO's operating in millimeter frequencies around

2000. The 189-GHz fundamental oscillator and 410-GHz push-push oscillator are also plotted in

Figure 6.31. The 410-GHz push-push VCO has the highest operating frequency among the

VCO's fabricated with 3-terminal devices in all transistor technologies.

Table 6-2. Calculated and measured power.
Measured Power -47 dBm
2nd Harmonic Power -49 dBm
Antenna loss 7 dB
Mismatch loss 2 dB
Calculated Push-push Pout -40 dBm
Simulated Pout with inductor Q of 6 @200GHz, bypass cap Q -38dBm
of 1 @400GHz and Rsub of 200Q
Table 6-3 compares the operating frequency and output power of recently published

millimeter-wave and submillimeter-wave VCO's implemented in InP, SiGe, and CMOS

technologies. The highest operating frequency of the VCO using InP technology is 346GHz. The

highest operating frequency of SiGe VCO's reached 278GHz in 2007.









Tabe -3Comnari son with recently reported VCO's in lnP SiC~e and CMOS techno~logies~


Year Freq(GHz) Pout(dBm) Topology Technology Ref
1993 131 -8 Fundamental InP [48]
1995 213 -30 Fundamental [49]
1999 108 -5.6 Push-push [50]
1999 134 -10 Fundamental [51]
2000 150 -10 Fundamental [52]
2001 147 -19 Fundamental [53]
2005 215 -10 Push-push [54]
2007 346 -16 Fundamental [55]
2003 150 -5 Push-push SiGe [56]
2004 115 -14 Fundamental [57]
2004 100 12 Fundamental [58]
2005 190 -4.5 Push-push [59]
2007 278 -20 Push-push [60]
2005 114 -26 Push-push CMOS [13]
2005 131 -11 Push-push [36]
2006 140 -19 Fundamental [61]
2006 192 -20 Push-push [12]
2008 189 -27 Fundamental [54]
2008 410 -49 Push-push [54]


Table 6-4. Summary of 410GHz push-push VCO.
Chip size 390 |tm x 640 |tm Patch size 200 |tm x 200 |tm
VDD 1.5 V ANT directivity 5
Bias current 11mA ANT efficiency 22 %

Frequency 410 GHz Reflection 50
coefficient
Tuning range 3 GHz Fundamental -27 dBm
Power
2nd harmonic -49 dBm Technology TI 45nm CMOS
power


Table6-3









6.8 Summary

A 250 GHz push-push oscillator with an on-chip patch antenna fabricated using a 90-nm

CMOS process is demonstrated. A ring oscillator is included for generation of 250-GHz AM

signals. 125-GHz AM signals are directly measured using a waveguide probe. A 410 GHz push-

push oscillator with an on-chip patch antenna fabricated using low leakage transistors of a 45-nm

CMOS process with 6 metal layers is demonstrated. The 410-GHz operating frequency is the

highest among the circuits fabricated using transistors including those fabricated in III-V

technologies.









CHAPTER 7
SUMMARY AND FUTURE WORK

7.1 Summary

Use of on-chip antennas at high frequencies makes systems compact and lower cost as well

as potentially improving their performance. At 60GHz, communication using antennas over 30

meters can have lower loss than that using transmission lines. The impact of realistic metal

interference structures which can significantly modify the characteristics of on-chip antennas,

such as a power grid, local clock trees and data lines have been investigated primarily using EM

simulations. In the presence of a power grid, the antenna pair IS121 can be traded off for improved

stability of antennas characteristics and the predictability of on-chip antenna characteristics.

Microstrip patch antennas are popular for their low profile, for the ease with which they

can be configured to specialized geometries, and their low cost when produced in large

quantities. The radiation mechanism of patch antenna is discussed, and the simple design

equations for the patch antenna size and input impedance are presented. The impact of bond

wires on on-chip patch antenna performance is presented. The bond wires at the distance of 50

jtm from a patch antenna change radiation direction by -13 and decrease the input resistance by

about 4 Q.

A 182-GHz Schottky diode detector with an AM modulator is demonstrated in a foundry

130-nm CMOS technology. The detector consists of a 180-GHz RF matching circuit, a Schottky

diode, a low pass filter, and an amplifier. The diode formed with 16 of 0.32gm x 0.32gm cells

connected in parallel. This detector proves the possibility to build a detector operating near the

top end of millimeter wave range using CMOS.

The output power of oscillator may decrease with operating frequency. The harmonics

mixer loss increases with frequency. The down converted signal at the harmonic mixer output









could be smaller than the noise level, which makes the measurement not possible. Also, probes

that work at THz are not possible. Off the shelf electrical probes go up to 325 GHz. To overcome

the difficulty of electrical measurement techniques, optical techniques are utilized. The power

and spectrum can be measured using a bolometer and FTIR. A 250-GHz push-push oscillator

with an on-chip patch antenna fabricated using a 90-nm CMOS process is demonstrated. A ring

oscillator included for the generation of 250 GHz AM signals. A 410 GHz push-push oscillator

with an on-chip patch antenna is fabricated using the low leakage transistors of a 45-nm CMOS

process with 6 metal layers. The 410-GHz operating frequency is the highest among the circuits

fabricated in any technology including the III-V technologies. These suggest the possibility of

CMOS THz systems.









7.2 Future work

7.2.1 250-GHz Detector Measurement with a High Power Source

The input power to the detector is about -70dBm and is smaller than the sensitivity of

detector and the amplitude modulate signal could not be detected. A novel Schottky barrier diode

in foundry CMOS that uses a polysilicon gate ring for separating the Schottky and n-well contact

is realized. This new Schottky barrier diode increases the cut-off frequency by -2 X over a

conventional SBD structure [62]. By using these Schottky barrier diodes, the sensitivity can be

improved and make the detection of amplitude modulate signal possible.

7.2.2 Output Power Improvement of THz VCO

The output power of 410GHz oscillator is about -50 dBm. The inductor, bypass capacitor

and substrate resistance affect the output power of the push-push oscillators. The push-push

oscillator output power can be improved by increasing quality factor of inductors and capacitors

and optimizing the substrate resistance as well as better matching the antenna to the oscillator

outpout frequency.









APPENDIX
FTIR MEASUREMENT PARAMETERS

Advanced Resolution 0.1 cm-1 Sample Scan 512 scans

Save Data from 1cm-1 to 40 cm1 Result spectrum Transmittance

Optic Beamsplitter Mylar 250[tm Optical Filter OPEN

Aperture 3; 10mm Detector 1 ; Bolometer

Scanner velocity 8; 14.864kHz Sample signal gain 4

Acquisition Wanted high 100 cm- Wanted low 0 cm1

frequency limit frequency limit

FT size 32k High pass filter Open

Low pass filter 7; 137 Hz Acquisition Mode Single Sided

Correlation Mode No

FT Phase Resolution 16 Phase 55

interferogrampoints

Phase correction Mertz Apodization function Norton-Beer,

mode Medium

Zero filling Factor 4 Interferogram size 4470 points

FT size 32k









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BIOGRAPHICAL SKETCH

Eunyoung Seok was born in Sangju, South Korea, in 1973. He received the B. E and M.S

degree in electrical and computer engineering from Yeungnam University, Kyongsan, South

Korea in 1999, 2001 respectively. He received his Ph.D. degree in electrical and computer

engineering from the University of Florida, Gainesville in 2008 and has been with Silicon

Microwave Integrated Circuits and Systems (SIMICS) research group since 2003.

During the summer of 2006, he interned at Texas Instruments where he was involved in

RF circuits design. His current research interests are in analysis and design of microwave,

millimeter and THz circuits and systems in CMOS.





PAGE 1

CMOS MILLIMETER AND SUBMI LLIMETER-WAVE COMPONENTS By EUNYOUNG SEOK A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2008 1

PAGE 2

2008 Eunyoung Seok 2

PAGE 3

To my parents 3

PAGE 4

ACKNOWLEDGMENTS I would like to begin by tha nking my advisor, Professor Ke nneth K. O, whose constant encouragement and patient guidance provided a clea r path for my research. I would also like to thank Dr. Gijs Bosman and Dr. William Eisens tadt for helpful suggestions and their time commitment in serving on my committee. Also, I am grateful to Dr. David Tanner for the FTIR measurements. Without his invalu able guidance and encouragement, this work could not have come to fruition. I would like to thank the former SiMI CS members Dong-Jun Yang, Seong-Mo Yim, Zhenbiao Li, J. Branch, Ran Li, Xiaoling Guo, Jose Bohorquez, Jason Branch, Jie Chen, Seon-ho Hwang, Changhua Cao, Yu Su, Yanping Ding, Haif eng Xu, Chikuang Yu, Aravind Sugavanam, Jau-Jr Lin. I have been quite fortunate to have worked with my colleagues Kwangchun Jung, Swaminathan Sankaran, Ning Zhang, Chuying Mao, Hsinta Wu, Myoung Hwang, Shashank Nallani Kiron, Wuttichai Lerdsitomboon, Dongha Shim, Kyujin Oh, Gayathri Devi Sridharan, Minsoon Hwang, Tie Sun and Ruonan Han. The discu ssions with them and their advice were immensely helpful for this work. Much appreciation goes to Texas Instrument s (TI) for funding this work. My special thanks go to Albert Yen at UMC Inc. for chip fabrication. Thanks also go to Dr. Chih-Ming Hung at TI and Dr. Brian A. Fl oyd at IBM for helpful technical discussions. I would like to express my sincere appreciation to the Dr. H yun Kyu Yu, Dr. Sang-Hun Chai and Dr. Jae-Sang Cha. I am grateful to the support from UMC, IBM and TI for research support and chip fabrication. I would also like to acknowledge the support from Al Ogden for bonding the chips and Daniel J. Arenas for the measurements using an FTIR. I am deeply thankful to my parents for their constant interest and support. Their love and encouragement are the source of my strength. 4

PAGE 5

TABLE OF CONTENTS page ACKNOWLEDGMENTS ...............................................................................................................4 LIST OF TABLES ...........................................................................................................................7 LIST OF FIGURES .........................................................................................................................8 ABSTRACT ...................................................................................................................................12 1 INTRODUCTION................................................................................................................. .14 1.1 An Overview of Millimeter and Submillimeter-Wave Technology .................................14 1.2 Submillimeter-Wave Circuits in CMOS Technology .......................................................16 1.3 Overview of the Dissertation ............................................................................................17 2 PREDICTABILITY IMPROVEMEN T OF ON-CHIP DIPOLE ANTENNA CHARACTERISTICS............................................................................................................20 2.1 Introduction .......................................................................................................................20 2.2 Antenna Fundamentals and Definitions ............................................................................20 2.2.1 Directivity ...............................................................................................................20 2.2.2 Gain ........................................................................................................................21 2.2.3 Antenna Input Impedance .......................................................................................21 2.2.4 Antenna Efficiency .................................................................................................22 2.2.5 Bandwidth ...............................................................................................................22 2.3 Signal Transmission Using Antennas and Transmission Lines ........................................23 2.4 An Overview of Intra-chip Wireless Clock Distribution System .....................................25 2.5 Antenna Measurements and Simulations ..........................................................................26 2.6 The Impact of Power Grids on Antenna Performance ......................................................31 3.7 Design Rules for On-Chip Dipole Antennas ....................................................................39 2.8 Summary ...........................................................................................................................41 3 PATCH ANTENNAS IN CMOS TECHNOLOGY...............................................................42 3.1 Advantages of On-Chip Antennas for Submillimeter-Wave System ...............................42 3.2 Fundamentals of Microstrip Patch Antenna .....................................................................42 3.3 Microstrip Patch Antennas on CMOS Technology ..........................................................51 3.3 The Impact of Bond Wires on On -Chip Patch Antenna Performance ..............................51 3.4 Summary ...........................................................................................................................54 4 MILLIMETER-WAVE SCHOTTKY DI ODE DETECTORS IN CMOS TECHNOLOGY..................................................................................................................... 55 4.1 Introduction .......................................................................................................................55 4.2 A Schottky Barrier Diode in CMOS Technology.............................................................55 5

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4.3 Sensitivity Analysis of Schottky Barrier Diode ................................................................56 4.4 A 182GHz Schottky Barrier Diod e Detector with a Modulator .......................................65 4.4.1 Design Considerations ............................................................................................65 4.4.2 Experiment Results .................................................................................................66 4.5 A Schottky Barrier Diode Detector with an On-Chip Patch Antenna in 90nm CMOS ...71 4.5.1 Design Considerations ............................................................................................71 4.5.2 Experiment Results .................................................................................................74 4.6 Summary ...........................................................................................................................77 5 OPTICAL MEASUREMENT ME THODS FOR MILLIMETER AND SUBMILLIMETER WAVE OSCILLATORS.......................................................................78 5.1 Introduction .......................................................................................................................78 5.2 Bolometer.........................................................................................................................78 5.3 FTIR ..................................................................................................................................80 5.4 Interferogram ....................................................................................................................82 5.5 Summary ...........................................................................................................................86 6 MILLIMETER-WAVE AND SUBMILLI METER VOLTAGE CONTROLLED OSCILLATOR IN CMOS TECHNOLOGY..........................................................................87 6.1 Introduction .......................................................................................................................87 6.2 Basic Operating Principles of Oscillator..........................................................................88 6.3 LC Resonant Tanks...........................................................................................................89 6.4 Ring Oscillator ..................................................................................................................90 6.5 Push-Push Oscillator .........................................................................................................93 6.6 A 250 GHz CMOS Push-Push VCO with AM Modulation .............................................94 6.6.1 Design Considerations ............................................................................................94 6.6.2 Experiment Results .................................................................................................96 6.7 410-GHz CMOS Push-Push VCO ..................................................................................100 6.7.1 Design Considerations ..........................................................................................100 6.7.2 Experiment Results ...............................................................................................110 6.8 Summary .........................................................................................................................116 7 SUMMARY AND FUTURE WORK..................................................................................117 7.1 Summary .........................................................................................................................117 7.2 Future work .....................................................................................................................119 7.2.1 250-GHz Detector Measurement with a High Power Source ..............................119 7.2.2 Output Power Improvement of THz VCO ...........................................................119 APPENDIX FTIR MEASUREMENT PARAMETERS...........................................................120 LIST OF REFERENCES .............................................................................................................121 BIOGRAPHICAL SKETCH .......................................................................................................126 6

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LIST OF TABLES Table page 2-1 Simulation results of antenna pairs at 24 GHz in the presence of interference structures shown in Figure 2-13. ........................................................................................40 2-2 Design rules. ......................................................................................................................41 6-1 Summary of 250-GHz push-push VCO. ............................................................................99 6-2 Calculated and measured power. .....................................................................................114 6-3 Comparison with recently reported VCOs in InP, SiGe, and CMOS technologies. ......115 6-4 Summary of 410-GHz push-push VCO. ..........................................................................115 7

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LIST OF FIGURES Figure page 1-1 fT and fmax of transistors in InP, SiGe, and CMOS technology. .........................................16 2-1 Attenuation by antenna pairs and transmission lines at 60 GHz. ......................................24 2-2 Intra-chip clock distribution system. ..................................................................................25 2-3 On-chip dipole antenna measurement setup. .....................................................................27 2-4 Simulated and measured structure. ....................................................................................27 2-5. Comparison of simulation and measur ement data of control structure. ............................28 2-6. A simulated and measured structure. .................................................................................29 2-7 Comparison of simulation with measurements data in the presence of an interference structure. .............................................................................................................................30 2-8 Cross section of the interference structures and on-chip antennas. ...................................31 2-9 On-chip antennas with interference structures (a) a planar view of a linear dipole antenna pair with perpendicula r power lines, (b) parallel power lines, (c) power grid, (d) power grid with data lines ............................................................................................32 2-10 Simulation results of structures in Figure 2-8. ...................................................................34 2-11 (a) S12(dB), (b) Phase (C) real part of input impedance, and (d) imaginary of input impedance of an antenna pa ir (5-mm separation) versus distance D1 and D2. The dashed line is simulated data and blac k line is curved fitted lines at 24 GHz. ..................38 2-12 Conceptual division of the chip area. A: area near the antenna. B: area under the power grid. .........................................................................................................................39 2-13 (a) Antenna with a power gri d, (b) antenna with a power gr id and local clock trees, (c) antenna with a power grid and data line s, and (d) antenna with a power grid and dummy fills. .......................................................................................................................39 3-1 Halfwavelength rectangular microstrip patch antenna. ..................................................45 3-2 50reflection coefficients of patch ante nnas with varying substrate thickness............47 3-3 Input resistance and radiation efficiency of patch antennas at varying dielectric thicknesses. ........................................................................................................................48 3-4 50reflection coefficients for varying patch sizes. .......................................................49 8

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3-5 Resonant frequencies and radiation efficiency for varying patch antenna size. ................49 3-6 50reflection coefficients of patch antennas for varying dielectric constants. .............50 3-7 Cross section of a patc h antenna with bond wires. ............................................................52 3-8 Input resistance of patch antennas wi th varying distances to bond wires. .........................52 3-9 On-chip patch antenna directivity wi th varying distances to bond wires. .........................53 3-10 Radiation pattern of patch antenna wi th varying distances to bond wires ( =0). ............53 4-1 A Schottky diode implemented in CMOS process. ...........................................................56 4-2 Equivalent circuit model of Schottky barrier diode. ..........................................................59 4-3 Noise equivalent circuit model of the Schottky diode. ......................................................61 4-8 10-MHz input and output signals (VDD=1.75 and 0.3 V). .................................................67 4-9 10-MHz input and output signals (Vdiode=1.78 and 0 V). ..................................................68 4-10 Spectra of modulated and unmodulated carriers (~91 GHz). ...........................................68 4-11 Power at 91GHz (fo) and 182GHz (2fo) signals on the push-push port versus Vbias plot .............................................................................................................................69 4-12 Detector output amplitude vers us input modulation power. Vbias = 0 V and VDD = 1.75 V .. ......................................................................................................................70 4-13 Die photograph of detector with modulator .......................................................................71 4-14 Schematic of 250-GHz Schottky diode detector. ...............................................................72 4-15 Voltage gain of amplifier with various load capacitors. ....................................................73 4-16 Equivalent input noise of amplifier. ...................................................................................73 4-17 Die photograph of detector with a patch antenna ..............................................................74 4-18 Series resistance and capacitance at zero bias of Schottky diode. .....................................76 4-19 Cross section of the Schottky barrier diode. ......................................................................76 4-20 Calculated tangential sensitivity of the detector. ...............................................................76 4-21 Path loss between two patch antennas. ..............................................................................77 5-1 Bolometer with preamplifier. .............................................................................................79 9

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5-2 Power measurement using a bolometer and a lock-in amplifier. ......................................79 5-3 FTIR measurement setup. .................................................................................................80 5-4 Michelson interferometer. .................................................................................................81 5-5 Null points of beam splitters. ............................................................................................82 5-6 Reflected and combined waveforms at 400 GHz. ............................................................83 5-7 Interferogram with mirror velocity (VM) of 10 cm/sec. ....................................................84 5-8 Interferogram with finite mirror movement. .....................................................................85 5-9 Measurement setup using an FTIR. ..................................................................................86 6-1 Feedback of an oscillatory system. ...................................................................................88 6-2 Feedback oscillatory system with a frequency selective network. ....................................89 6-3 LC resonators (a) Ideal LC tank, (b) real istic LC tank and (c) equivalent parallel RLC tank. ...........................................................................................................................89 6-4 A ring oscillator realized using five inverters. ...................................................................90 6-5 A ring oscillator realized using fully differential inverters. ...............................................91 6-6 A fully differential inverter with programmable delays. ...................................................92 6-7 Oscillators (a) fundamental oscillator, (b) oscillator with a frequency doubler and (c) push-push oscillator. .....................................................................................................93 6-8 Push-push VCO. ................................................................................................................94 6-10 Die microphotograph of 250-GHz AM modulated signal generator. ................................96 6-11 Output spectrum of the 125-GHz VCO.............................................................................97 6-12 Output spectrum of the VCO with modulation and without modulation. ..........................98 6-14 Schematic of a Push-push VCO with on-chip patch antenna and buffers for the fundamental outputs. ........................................................................................................100 6-15 Schematic of a Push-push VCO with on-chip patch antenna without the buffers for the fundamental outputs. ..................................................................................................101 6-16 Layout of cross-coupled transistors. ................................................................................102 6-17 Structure of circular induct or for the 410-GHz oscillator. ...............................................103 10

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6-18 Grounded coplanar waveguide. .......................................................................................104 6-19 On-chip patch antenna. ....................................................................................................105 6-20 Resonant frequencies of the on-chip patch antennas. ......................................................106 6-21 Efficiency with various dielectric thicknesses. ................................................................106 6-22 Directivity and efficiency for varying sizes of patch.......................................................107 6-23 On-chip patch antenna radiation pattern. .........................................................................107 6-24 2nd harmonic power at the push-push node (Qbypass = 0.2, Rsub = 200 ). ........................108 6-25 2nd harmonic power at the push-push node (Qind = 6, Qbypass = 0.2). ................................109 6-26 Die microphotograph of push-push os cillator with output buffers. .................................110 6-27 Output spectrum of the 189-GHz fundamental Oscillator. ..............................................110 6-28 Die microphotograph of push-push osci llator without output buffers. ............................111 6-29 Spectrum of the 410-GHz push-push osci llator measured using an FTIR. .....................112 6-30 Frequency and power of push-push osci llator at varying bias currents. ..........................113 6-31 Operating frequencies of published VCO. .......................................................................113 11

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Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy CMOS MILLIMETER AND SUBMILLI METER-WAVE COMPONENTS By Eunyoung Seok May 2008 Chair: Kenneth K. O Major: Electrical and Computer Engineering With continued introduction of new wireless applications, the available spectrum is becoming crowded. Because of this, interests for developing circuits and systems operating at higher frequencies have been increasing larger bandwidth and propagation properties of signals in the frequency range from 100 GHz to 3 THz have le d to the recent increase in research efforts. For the communication over 30m, use of antennas are better than using transmission lines at the frequency above 60 GHz. Use of on-chip antennas at high frequencies makes systems compact and lower cost, as well as potentially impr ove their performance. The impact of realistic metal interference structures which can signifi cantly modify the characteristics of on-chip antennas, such as a power grid, local clock trees and data lines have been investigated using EM simulations. In the presence of a power grid, the antenna pair |S 12 | can be traded off for improved stability of antennas characteristics and the predic tability of on-chip antenna characteristics. The radiation of a patch antenna is due to the fringing fields. The ground plane in the patch antenna decreases the c oupling to near by circuits. The design of patch antenna in CMOS processes is limited by the fixed relatively low dielectric thicknesses. These limit the input resistance and efficiency. The bond wires change th e radiation direction by ~13 at the distance 12

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of 50 m from a patch for 250 GHz operation and decrease the input resistance by about 4 Increasing the separation to 150 m, make the impact of bond wires negligible. A 182-GHz Schottky diode detector is demonstrated in foundry 130-nm CMOS technology. A 182-GHz AM modulator is implem ented by changing the gate bias of PMOS current source of a push-push osci llator which utilizes the 2 nd order harmonics. The operation is verified by the observation of 91-GHz AM signal s at the fundamental using an OML harmonic mixer. The noise performance of a 250 GHz Scho ttky barrier diode detect or with an on-chip patch antenna in 90 nm CMOS also have analyzed. To overcome the difficulties of electrical measurement techniques for submillimeter-wave circuits, optical techniques are utilized. The power and sp ectrum of 250-GHz and 410-GHz push-push oscillators have been measured usin g a bolometer (HD-3, IR Lab) and FTIR (IFS 113v, Bruker). A 250-GHz pushpush osci llator with an onchip patch antenna fabricated using a 90-nm CMOS process is demonstrated. A ring oscillator is incorporated for the generation of 250-GHz AM signals. The 125-GHz AM signal is measured using a harmonic mixer and a spectrum analyzer. The radiated second harmonic power from the patch antenna is about -32 dBm. A 410-GHz pushpush oscillator with an on-chip patch antenna fabricated using low leakage transistors of a 45-nm CMOS process with 6 metal layers is demonstrated. The patch antenna size is 200 x 200 m 2 The radiated second harmonic pow er from the patch antenna is about -49 dBm. The 410-GHz opera ting frequency is the highest among the transistor circuits fabricated in any technology including the III-V technologies. These sugge st the possibility of CMOS THz systems. 13

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CHAPTER 1 INTRODUCTION 1.1 An Overview of Millimeter and Submillimeter-Wave Technology As more wireless services continue to be introduced, the available spectrum becomes crowded. Because of this, there has been a trend of developing circuits and systems operating at higher frequencies where wider bands are av ailable. In 2001, the Federal Communications Commission (FCC) set aside a c ontinuous block of 7 GHz of spectrum between 57 and 64 GHz for wireless communications. The unlicensed 7-GHz bandwidth is wide enough to accommodate high data rate communications such as wireless gi gabit Ethernets, wireless USBs, and wireless high definition televisions (HDTV) [1] A 76-77 GHz frequency band is assigned for automotive radars. Automotive radars are employed in advan ced cruise control systems, which can actuate accelerators and brakes to control the distances of other vehicles [2] Imaging systems operating around 94 GHz have been used for medical applic ations and observations of earth atmosphere [3]. The millimeter-wave imaging systems can have higher resolution th an microwave imaging systems. The wide bandwidth of millimeter-wav e makes it possible to communicate at high speed and the short wavelength of millimeter-wave makes automotive radar and imaging systems compact. The potential bandwidth and pr opagation properties of carriers in the frequency range from 300 GHz to 3 THz have led to the recent increas ed investment and research in terahertz technology. The major interest in terahertz technology is almost exclusively with the radio astronomy [4]. The rotational energy level of im portant molecules in biology and astrophysics, such as water, oxygen, chlorine and nitrogen co mpounds are in the terahe rtz range [5]. These levels can be used to unambiguously to identify these molecules in remote environments. Radio astronomers have identified hundreds of molecules in space and have thereby gained a great 14

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amount of understanding of the st ructure and dynamics of the Universe, particularly with regard to the formation of stars in mo lecular clouds [6], [7]. There ar e now worldwide initiatives in terahertz technology. The uses of terahertz in adva nced imaging, and bio-agent and chemical detection [4], [6] have been extensively studied. It s ability to penetrate objects enables the imaging systems to detect concealed weapons. Chemists use tera hertz spectroscopy to study the structure and dynamics of a wide range of molecules. Other applications of terahertz technology include plasma diagnostics, studies of solid-state physic s, compact range radars and more recently studies of biological macromolecules, such as DNA and proteins. In addition, terahertz radiation is nonionizing radiation, therefore health risks are minimal. These characteristics are due to the unique electromagnetic properties of terahertz radiation and can not be duplicated in other regions of the spectrum [6]. A key limitation for wide scale utilization of millimeter-wave systems is the high cost of circuits. Additionally, industrial and commercial applications of m illimeter-wave require compact and portable systems. Integration of transmitters, detectors, and on-chip antennas [8], as well as, baseband digital signal processing (DSP) circuits in CMOS should allow single-chip realization [8] of compact and low cost millimeter and sub-millimeter-wave systems. The development of terahertz technologies is impeded by the lack of standards and the inability to perform precise measurements to ch aracterize noise, power, dielectric constants, and scattering parameters of systems and components operating at terahertz [9]. Optical measurement techniques and microwave measurement technique s are both required for terahertz systems. Power can be measured using a bolometer and frequency spectrum of the circuits can be measured using a Fourier transfor m infrared spectroscopy (FTIR). 15

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1.2 Submillimeter-Wave Circuits in CMOS Technology With the rapid advance of high frequency capability for SiGe BiCMOS and CMOS technology, the operating frequencies of millimet er-wave fundamental VCOs have reached up to 140 GHz [10], [11] The fundame ntal oscillation frequency is limited by the unity power gain frequency( ) of the transistors. The unity power gain frequency increases with the scaling of CMOS technology and the VCO opera ting frequency is expected to continue to increase. To obtain even higher operating frequencies, a pushpush VCO [12], [13] using the second harmonic operating up to 192 GHz has been dem onstrated in a 130-nm CMOS technology [12], [14]. maxf Figure 1-1. f T and f max of transistors in InP, SiGe, and CMOS technology. 16

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Advanced CMOS technology and frequency doub ling techniques are key factors for the implementation of millimeter and sub-millimete r-wave VCOs. Figure 1-1 shows the required f max and f T of transistors in various technologies. The measured f max and f T of an NMOS transistor [63] of a 65-nm CMOS technology are plotte d. The required f max of NMOS transistor becomes higher than SiGe tec hnology in 2011. The required f max based on the international technology roadmap for semiconductors (ITRS) reaches over 1THz around 2010 and suggests the possibility of CMOS THz systems. The carrier transport in Schottky diodes only relies on the majority carrier conduction, in contrast to that in p-n junction diodes where th e carrier transport involves both the minority and majority carrier. Since there are no minority carrier storage effects, these devices are potentially capable of operation up to the frequencies approaching the recipr ocal of dielectric relaxation time of the semiconductor crystal [15]. However the series resistance and junction capacitance typically limit the high frequency capability be fore reaching the limit set by the dielectric relaxation. Schottky diodes with a cutoff fre quency of greater than 1 THz have been demonstrated in the UMC 130-nm digital CMOS process [16]. Using such diodes, it should be possible to implement detectors operating in the high end of millimeter-wave to lower end of sub-millimeter-wave range in CMOS. 1.3 Overview of the Dissertation This research focuses on the design and characterization of millimeter-wave and submillimeter-wave transmitters and Schottky diode detectors. The primary goal is to demonstrate the feasibility of implementing the components including antennas. Instruments using traditional microwave measurement techniques are not av ailable for terahertz measurements, so a combination of optical measurement techniques and microwave measurement methods must be used to characterize the sub-millimeter-wave transmitters and diode detectors. This research also 17

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seeks to investigate the feasibility of implementing circuits for future terahertz radios, sensor networks, and imaging systems using CMOS technology. Since on-chip antennas are necessary components, antenna structures that can be fabricated in silicon substrates are invest igated and presented in chapters 2 and 3. Chapter 2 discusses onchip dipole antennas. It is found that these characteristics are strongly influenced by near by metal structures [17]. In order to enable circuits and system design with these constraints, a set of design rules for increasing the predictability of on-chip antenna characteri stics are developed and presented. Various interference structures are di scussed and their impact on on-chip antenna characteristics are studied. The impact of on-chip metal interference structures, such as power grids, local clock trees and data lines to on-c hip antennas performance has been investigated using Ansoft High Frequency Structure Simulator (HFSS). Chapter 3 reviews the fundamentals of patc h antennas. The key parameters of patch antennas are discussed. There are limitations on antenna performance when the patch and dipole antennas are implemented in a CMOS technology. A 3-D electromagnetic simulator is used to compare with the theoretical analysis. The results clearly show the factors which limit the performance of on-chip antenna fabricated in CMOS technol ogy. Patch antennas also have interference phenomenon w ith metal lines in near fields region. Design rules should be defined for optimum performance while k eeping the chip area acceptable. Also bond wires and packages are need for systems. The minimum allowable distance between antenna and bond wire are discussed. Chapter 4 describes the design of sub-millimeter-wave detectors. The basic set of detector parameters, tangential sensitivity, responsivity, a nd noise equivalent power (NEP) are reviewed. Optimization and trade-off of det ector design for better sensit ivity are presented. Since sub18

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millimeter-wave sources are not widely availa ble, the amplitude modulated VCO has been designed and described. Design an d analysis of a 250 GHz Schottky barrier diode detector with an on-chip patch antenna in 90nm CMOS also has been discussed in chapter 4. Instruments using traditional microwave t echniques are not widely available for THz oscillator measurements. The optical measurement techniques are presented in chapter 5. The basics of the Michelson interferometer are presen ted to describe the operating principle of FTIR system. The FTIR system can specify spect rum of millimeter-wave and submillimeter-wave oscillators. Using a bolometer and a lock-in am plifier, power of the THz oscillator can be measured. Chapter 6 reviews the fundamentals of VCO. The design and measurements of 250GHz push-push VCO with an on-chip patch antenna is presented. Also a 410GHz push-push oscillator with an on-chip patch antenna is discussed in chapter 6. Finally, this research work is briefly summarized and possible future works are suggested in Chapter 7. 19

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CHAPTER 2 PREDICTABILITY IMPROVEMEN T OF ON-CHIP DIPOLE ANTENNA CHARACTERISTICS 2.1 Introduction An on-chip antenna is expected to be a critical component for millimeter and submillimeter-wave circuits and systems. A concern fo r on-chip antennas is how their characteristics are modified by nearby metal structures [17]. The effects of metal structures near on-chip antenna for intra-chip clock distribution system have been studied. A set of design rules for antenna layout has been proposed to improve predictability of an tenna characteristics to improve predictability of antenna charac teristics [18], [19]. To describe the performance of an antenna, definitions of various parameters are fist pr esented. Definitions of antenna parameters are specified. Antenna pair performance is compared with various transmission schemes using the Friis transmission equation [23]. 2.2 Antenna Fundamentals and Definitions Key antenna parameters includ ing directivity, gain, antenna input impedance, and antenna efficiency are summarized in this section. More de tailed discussions of these parameters can be found in the references [20], [21]. 2.2.1 Directivity The directivity D and the gain G are the most important parameters of an antenna. The directivity of an antenna is defined as the ratio of the radiation intensity ( U, power per solid angle) in a given direction fr om the antenna to the radiation intensity averaged over all directions. The average radiation intensity is eq ual to the total power radiated by the antenna divided by 4 If the direction is not specified, the dire ction of maximum radiation intensity is implied. The directivity can be expressed as 20

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radP U U U D ),(4),( ),(0 (2.1) where, D is the directivity, U is the radiation intensity, U 0 is the radiation intensity of an isotropic source, and P rad is the total radiated power. The di rectivity is a dimensionless ratio 1. 2.2.2 Gain The gain of an antenna defined as the ratio of the radiation in tensity, in a given direction, to the radiation intensity that would be obtained if the power delivered to the antenna were radiated isotropically. The radia tion intensity corresponding to the is otropically radiated power is equal to the power delivered to the antenna divide by 4 The gain G of an antenna is an actual or realized quantity which is less than the directivity D due to losses in the antenna. De P P Gt in max),( PowerInputTotal Intensity Radiation 4 (2.2) where is the total antenna efficiency. te 2.2.3 Antenna Input Impedance Input impedance is defined as the impedance pr esented by an antenna at its terminals or the ratio of the voltage to current at a pair of terminals. A LrAjXRRZ (2.3) where, is antenna impedance at the terminal, is the radiation re sistance of antenna, is the loss resistance of the antenna and is the antenna reactance at the terminal. AZ rR LR AX 21

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2.2.4 Antenna Efficiency The total antenna efficiency is used to take into account lo sses at the input terminals and within the structure of the ante nna. The losses of antennas may be caused by the mismatch with a transmission line and te R I 2 losses caused in the conductor and dielectric. dcrteeee (2.4) where, is reflection efficiency re )1(2 is conduction efficiency and is dielectric efficiency. ce de Its not easy to separate and sometimes. The conduction-dielectric efficiency can be used to describe antenna efficien cy. The conduction-dielectric efficiency is defined as the ratio of the power delivered to the radiation resistance to the power delivered to + ce de cde cde rR rR LR Lr r cdRR R e (2.5) 2.2.5 Bandwidth The bandwidth of an antenna is defined as the range of frequencies within which the performance of the antenna with re spect to some characteristics conforms to a specified standard. The bandwidth can be considered to be the range of frequencies, on e ither side of a center frequency (usually the resonance frequency, patte rn, beamwidth, polarizati on, side lobe level, gain, beam direction, radiation e fficiency) are within an acceptab le value of thos e at the center frequency. For broadband antennas, the bandwidth is usually expressed as the ratio of the upperto lower frequencies of acceptable operation. For example, a 10:1 bandwidth indicates that the upper frequency is 10 times greater than the lower. For narrow bandwidth antennas, the bandwidth is expressed as a percentage of the frequency difference (upper minus lower) over the center frequency of the bandwidth. For example a 5-% bandwidth indicates that the frequency 22

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range for acceptable operation is 5 % of the cente r frequency. Because the characteristics (input impedance, pattern, gain, polariza tion, etc) of an antenna do not necessarily vary in the same may, there is no one bandwidth for antenna. Usually there is a distinction made between pattern and input impedance variations. Accordingly pa ttern bandwidth and impedance bandwidth are separately specified to em phasize this distinction. 2.3 Signal Transmission Using An tennas and Transmission Lines Antennas are transducers designed to tran smit or receive electromagnetic waves. Alternatively, electromagnetic energy can be transported usin g transmission lines. At low frequencies and short distances, transmission lines are practical. But at high frequencies and long distances, use of antennas can be better because of available bandwidth. If a transmission line is used to send signal between a transmitter and a r eceiver, the power loss in a transmission line is proportional to R is the communication distance and Re2 is the attenuation constant of a transmission lines. If antennas are used in a line of sight configuration, the received power is proportional to As the distance increases at high fr equencies, the signal losses and the costs of using transmission lines become large, a nd thus the use of antennas can be advantageous over use of transmission lines [21], [22]. 2/1 R Figure 2-1 shows the attenuation cased by antenna pairs and transmission lines. The attenuation constant of microstrip, coaxial cab le, and waveguide are assumed to be 60, 13, and 3 dB/meter respectively. Antenna gain is 4 dBi. The Friis transmission formula [23] is used to compare power transfer using antennas a nd using transmission lines at 60 GHz. 2 24 R GG PPrt tr (2.6) P r and P t are received power at a receiver antenna and transmitted power from a transmitter antenna respectively. G t and G r are the gain of the transmitter and receiver antenna. The equation 23

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assumes that the antennas are in unobstructed free sp ace, with no multipath. This condition is difficult to achieve in practical situations, due to reflections from buildings, and most importantly reflections from the ground. One situ ation where the equation is reasonably accurate is in satellite communications when there is ne gligible atmospheric absorption. Another situation is in anechoic chambers specifically designed to minimize reflections [21]. 0.1 1 10 100 0 20 40 60 80 Path Length (m)Attenuation (dB) Antenna Microstrip Coaxial Cable Waveguide Figure 2-1. Attenuation by antenna pairs and transmission lines at 60 GHz. The is wavelength in free space and R is distance between transmitter and receiver antenna in equation (2.6). The communication distance is varied from 0.1 to 100 meters. Signal transmission using the transmission line is pref erred for short ranges. Signal transmission using 24

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antennas has advantage over usi ng transmission lines over 30 meters in Figure 2-1. An exception to this is optical cable communication [21]. 2.4 An Overview of Intra-chip Wi reless Clock Distribution System The increases of operating frequency and the die size projection to 2.4 x 2.4 cm 2 for CMOS circuits have led to the investigation of wireless interconnection within and between ICs. Uses of on-chip antennas [24], [ 25] as an alternative interconn ect for clock distribution (Figure 2-2) have been investigated [ 26], [27] to reduce skew and alle viate the dispersi on problem [8], [28]. Figure 2-2. Intra-chip clock distribution system. This intra-chip wireless clock distribution system has a transmitter in the center of the chip and distributed receivers across the chip to rece ive the global clock and provide the local clock. The wireless system uses on-chip antennas to transmit and receive the global clock signal. In 25

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addition, to reduce the size of onchip antennas, a much higher gl obal clock frequency which is about 20 GHz is generated by the transmitter and used as the global clock. Be cause of this, at the receiver side, the high frequenc y global clock is divided down to a lower frequency for local clocking [28]. On-chip antennas could also be used in comm unication links for sensor networks, radio frequency identifiers (RFIDs), and single chip radars. On-chip antennas/inductors have also been used as near field couplers in RFIDs [8]. In all these app lications, on-chip antennas are colocated with circuits and the associated interconn ects such as power grids, clock trees, and data lines. An on-chip antenna is also expected to be a critical component for millimeter and submillimeter-wave circuits and systems. A concern fo r on-chip antennas is how their characteristics are modified by nearby metal structures [17]. Because of this, the effects of metal structures near on-chip antenna for intra-chip cl ock distribution system have been studied. The metal structures significantly affect the on-chip antenna characteristics, such as gain, phase, and antenna input impedance [17], [18]. Approaches to better guarantee the characte ristics of on-chip antennas are critical to provide predictability for the design community. The impact of power grid on the characteristics of on-chip antennas has been presented. The metal structures near an on-chip antenna in the presence of a power grid have greatly reduced impact on antenna characteristics. Exploiting this, a set of desi gn rules for antenna layout ha s been proposed to improve predictability of antenna characteristics [18], [19]. 2.5 Antenna Measurements and Simulations The Finite Difference Time Domain Method (FDTD) and Fi nite Element Method (FEM) have been used for evaluation of a power grid [29] and other interference structures for on-chip antennas [30]. In order to validate the simulation re sults, a set of representative test structures consisting of 2-mm long linear dipole antenna pairs and varying interference structures have 26

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been simulated using High Frequency Structur e Simulator (HFSS) and compared with the measurements. The test structures were fabric ated using the UF thre e metal layer process on 20 -cm silicon substrates [17]. The measuremen t setup is shown in Figure 2-3. This setup includes an HP network analyzer, baluns, semi-r igid cables and signal-si gnal probes [25], [26]. Baluns are used to convert the singled-ended signal to differential signal and vice versa. Figure 2-3. On-chip dipole antenna measurement setup. Figure 2-4. Simulated and measured structure. 27

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(a) 22 23 24 25 26 20 40 60 80 Frequency(GHz)Real(Z11) Simulation Measurement (b) 22 23 24 25 26 -80 -60 -40 -20 0 Frequency(GHz)|S12| [dB] Simulation Measurement Figure 2-5. Comparison of simulation and measurement data of control structure. 28

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The metal layers were separated using PECVD SiO 2 layers. Figure 2-4 shows a structure which has been simulated and measured. The two 2-mm long linear dipole antennas are separated by 5 mm. Figure 2-6 shows a structur e with two 3-mm long and 100m wide metal bars (interference structure) which run parallel to the antennas. The spacing to antenna is 50 m. Figure 2-5 and 27 also show the simulated and measured |S 12 |, as well as phase, for the antenna pairs without and with the interference structure. Between 22 and 26 GHz, the presen ce of interference structure lowers |S 12 | between the antenna pair by ~ 20 dB. The simulated |S 12 | is in within 3-4 dB of the measurements especially at frequencies higher than 24. The measured and simulated phases are within 20 degrees of each other. Figure 2-6. A simulated and measured structure. 29

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(a) 22 23 24 25 26 -80 -60 -40 -20 0 Frequency(GHz)|S12| [dB] Simulation Measurement (b) 22 23 24 25 26 -150 -100 -50 0 50 100 Frequency(GHz)Phase [degree] Simulation Measurement Figure 2-7. Comparison of simulation with m easurements data in the presence of an interference structure. 30

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Having verified reasonable correspondence between the measurement and simulation results, 3D EM simulations are used to more rapidly evaluate the impact of a wide variety of interference structures. 2.6 The Impact of Power Grids on Antenna Performance Figure 2-8. Cross section of the interference structures and on-chip antennas. In particular, design rules for antenna layout have been deve loped for a back-end process with 5 metal layers of Al separated by SiO 2 layers. The substrate resistivity is 20 -cm and thickness is 0.5mm. An aluminum metal plate is us ed in the back side of silicon substrate to represent a heat sink. For the EM simulation, actual structures mu st be simplified to shorten computation time and to reduce the memory requirement. This simplification may cause simulation errors, by the simulations should be verified with various simulation structural configurations. The resu lts of EM simulation are affected by the boundary condition. A choice of boundary condition varies results even for the sa me structures at th e same frequency. An appropriate air box and a boundary layer are requi red for accurate simulations. The perfectly 31

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matched layer (PML) is used fo r radiation boundary. The power grid is formed using metal 5, data lines are formed in metal 2-4 layers in Figure 2-8. Figure 2-9. On-chip antennas with interference structures, (a) a pl anar view of a linear dipole antenna pair with perpendicu lar power lines, (b) parall el power lines, (c) power grid, (d) power grid with data lines 32

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(a) 22 23 24 25 26 -80 -60 -40 -20 0 Frequency(GHz)|S12| [dB] Control Perpen Parallel Power grid Data Lines (b) 22 23 24 25 26 -40 0 40 80 120 Frequency(GHz)Phase [degree] Control Perpen Parallel Power grid Data Lines 33

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(c) 22 23 24 25 26 40 45 50 55 60 65 Frequency(GHz)Real(Z11) Control Perpen Parallel Power grid Data Lines (d) 22 23 24 25 26 -60 -40 -20 0 20 40 60 Frequency(GHz)Imag(Z11) Control Perpen Parallel Power grid Data Lines Figure 2-10. Simulation results of structures in Figure 2-8. 34

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The width and pitch of power lines are 250 m. Figure 2-9 shows some of the simulated power line structures. Figure 2-10 shows the simulated results. The parallel metal lines in Figure 3-10(a) decrease |S 12 | by 25 dB at 24 GHz. The perpendicu lar structure in Figure 2-10(b) increases |S 12 | by 6 dB and decreases the imagin ary part of input impedance by 8. The power grid shown in Figure 2-10(c) decreases gain by 18 dB and changes input impedance from 52 to 42. The structures with the parallel power lines and power grid in Figure 2-10 have similar input impedance, because the near field intera ction is dominated by the parallel lines. 20m wide data lines are placed in metal 3 layer as sh own in Figure 2-10(d). The length of data lines is 2 mm, separation is 20 m, and distance to antenna is 1.5 mm. Compared to the simulation results for the structures in Figur es 2-9(c) and (d), the input impe dance, gain, and phase of this structure show little difference. When the polarization of the incident wave is parallel to a densely packed wire grid, the reflection coefficien t for the wire grid is close to -1. The power grid acts like a metal plate reflecting incident waves, therefore data lines have relatively small effects on the antenna performance. Input impedance, and magnitude and phase of S 12 for antenna pairs (5-mm separation) are simulated at varying separations between the power grid and antenna at 24 GHz. Figure 2-11 indicates that |S 12 | (dB) linearly depends on D1 and D2 in Figure 2-9. The power grid has significant effects on the characteristics of on-ch ip antennas. Compared to the control case, |S 12 | is reduced by ~20 dB. This is due to the destructive interference effects of reflected waves from the power grid. This is indeed a significant redu ction. However, much of this can be recovered by using an AlN propagating layer in conjunction with antennas on thinned substrates. It has been shown recently that the gain can be improved by 10, 15 and 20 dB for 0.5, 1 and 2-cm antenna pair separations [17] over the best previously reporte d results by thinning the substrate 35

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from 500 m to 100 m [31]. The cause for input impedance change is the near field coupling between the antenna and power grid. The separation D1 has mo re significant effects on the antenna performance than D2. |S 12 | (dB) is degraded dB/50 m. The phase does not change much with the variations of D1 and D2. The linea r dependency of input impedance is about 1 /50 m. The dependences of |S 12 |(dB), phase, real and imaginary part of impedance can be expressed as linear combinations of D1 and D2 in conj unction with a constant as given below. 11067.12.692104.7)(2 3 12D D dBS (2.7.1) 1103.1941.3321022 2D D Phase (2.7.2) 11077.148.352107.1)(Re2 3 11D D Zal (2.7.3) 11006.337.402102)Im(2 3 11D D Z (2.7.4) (a) 300 350 400 450 -65 -60 -55 -50 -45 -40 D2( m) Control D1:275 m D1:325 m D1:375 m D1:425 m D1:475 m 36

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(b) 300 350 400 450 -10 0 10 20 30 40 50 60 D2( m) Control D1:275 m D1:325 m D1:375 m D1:425 m D1:475 m (c) 37

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(d) 300 350 400 450 -35 -30 -25 -20 -15 D2( m) Control D1:275 m D1:325 m D1:375 m D1:425 m D1:475 m Figure 2-11. (a) S 12 (dB), (b) Phase (C) real part of i nput impedance, and (d) imaginary of input impedance of an antenna pair (5 -mm separation) versus distance D1 and D2. The dashed line is simulated data a nd black line is curved fitted lines at 24GHz. These equations can be used during the layout of antennas and power grid D1 and D2 are in m. 38

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3.7 Design Rules for On-Chip Dipole Antennas 275 m 275 m A B H trees 200 m Figure 2-12. Conceptual division of the chip ar ea. A: area near the antenna. B: area under the power grid. (a) (b) (c) (d) Figure 2-13. (a) Antenna with a power grid, (b) antenna with a power grid and local clock trees, (c) antenna with a power grid and data lines, and (d) antenna with a power grid and dummy fills. 39

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Table 2-1. Simulation results of antenna pairs at 24 GHz in the presence of interference structures shown in Figure 2-13. Structure Real(Z 11 ) Im (Z 11 ) |S 12 |(dB) Phase() (a) 42.6 -30 -60.4 40 (b) 41.8 -34 -60.2 43 (c) 42.8 -30 -60.5 36 (d) 40.5 -26 -60.2 27 The power grid acts like a meta l plate reflecting incident wave s, so data lines, the local clock trees, and dummy fills have relatively small effects on the antenna performance. The simulation results are listed in Table 2-1. For the wireless clock distribution system, because the transmitted clock is frequency divided by 8, the phase variations of 1% of a period or skew for the actual clock correspond to 28 degrees for the transmitted clock signal. One percent is onetenth of the typical skew/jitter tolerance and this can be used as the criterion to determine acceptability of variations. Based on this, all th e structures in Table 2-1 are acceptable. The presence of a power grid reduces |S 12 |, however it makes the antenna characteristics to be almost independent of other metal structures. This allows definition of a relatively simple set of design rules for on-chip antennas. Table 2-2 lists the design rules when followed should make on-chip antenna characteristics more predictable. 40

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Table 2-2. Design rules. 1 Wide power lines directly over antenna should be avoided in region A. D1 and D2 are 255 m and 275 m. 2 Any metal structures can be placed in region B. 3 Perpendicular metal lines to antenna off by 200 m away are acceptable (Figure 2-12). 4 To run multiple perpendicular metal lines over antennas, the characteristics of antennas must be simulated using an EM software. 5 Short (length < 100 m, width < 20 m, and space > 20 m) discontinuous metal lines are acceptable in the region A. These lines can be connected to transistors. 6 Local clock trees can be pl aced over the area A and B. 7 Dummy fills (size:10 m x 10 m and space > 10 m) are acceptable in regions A and B 2.8 Summary The signal transmission using transmission line and antennas are compared. At millimeter and sub-millimeter-wave frequencies, use of antennas for information transmission has advantage over use of transmission lines. The imp act of realistic metal interference structures which can significantly modify the characteristic s of on-chip antennas, such as a power grid, local clock trees and data lines have been inve stigated primarily using EM simulations. In the presence of a power grid, the antenna pair |S 12 | can be traded off for improved stability of antenna characteristics. This can be exploited to define a set of design rules to improve the predictability of on-chip antenna characteristi cs in the presence of other metal structures. 41

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CHAPTER 3 PATCH ANTENNAS IN CMOS TECHNOLOGY 3.1 Advantages of On-Chip Antennas for Submillimeter-Wave System As the operating frequency is increased, wa velengths of electromagnetic waves and antenna sizes become smaller. Use of on-chip antennas at the upper millimeter and submillimeter-wave frequencies need to occupy a small chip area and avoids the difficulty of interconnection between on-chip components and an external antenna. Th e parasitic inductance of bond wires for making the connection between on-chip components and an external antenna impedes signal transmission as well as causi ng coupling between bond wi res. Since bond wires can cause unwanted resonance and radiation, they can degrade stability and cause electromagnetic interference with other chips an d systems. On-chip antennas can make systems compact and reduce the loss and coupli ng problems caused by the bond wires. On-chip antennas can be co-located with di gital and analog circuits, which is a key technology for realizing a true si ngle chip radio [8]. For sensors, radars and imaging systems digital signal processing is necessary. For sp ectroscopy, Fourier transformation is needed to detect and increase sensitivity to molecules with multiple resonant frequencies [32]. Digital signal processing techniques can increase the re solution of radar and imaging systems. The precise control of physical dimensions in CMOS integrated circuits results high yield of millimeter-wave arrays with a large number of elements, which is necessary to lower cost. 3.2 Fundamentals of Micro strip Patch Antenna As discussed in chapter 2, the performance of dipole antennas is significantly degraded by the conduction in the substrate. Co nductivity of silicon substrates used in CMOS fabrication is about 2 to 20 -cm. The energy in the reactive near fiel d around the antenna is dissipated by the conductive silicon substrate. In addition, the characteristics of dipole antennas are significantly 42

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affected by metal structure near the antennas. The technique to make antenna characteristics more predictable proposed in chapter 2 degrades antennas gain. The options are limited for intrachip communications. For inter-chip applications, especially when the desired signal transmission is perpendicular to the chip surf ace, there is a better option. The loss caused by the conductive silicon substrate can be avoided by putting a metal plate between the antenna and silicon substrate, although this metal plate increases capacitance and decreases radiation efficiency. A patch antenna [21] is consistent with these. In addition, the ground plane reduces the impact of near by metal structur es on the antenna characteristics. Microstrip antennas are popular with antenna engineers for their low profile, for the ease with which they can be configured to speciali zed geometries, and low cost when produced in large quantities [21]. Figure 3-1 shows an edge-fed microstrip antenna. At the bottom, there is a ground plane, and a dielectric s ubstrate separates the patch a nd ground plane. A rectangular patch is fed from a microstrip transmission line. The patch length is about half wavelength. The substrate thickness h is much le ss than a wavelength. The patch an tenna belongs to the class of resonant antennas and its resonant characteristic is responsible for the narrow bandwidth [21]. The radiation from microstrip antennas occurs fr om the fringing fields between the edge of the microstrip antenna conductor and ground plane. Th e fringing fields act to extend the effective length of the patch. Thus, the length of a half-wave patch is slightly less than a half wavelength of dielectric substrate material. 43

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(a) Geometry of the edge fed patch antenna. (b) Side view showing the electric fields. 44

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l s (c) Top view of the patch antenna. Figure 3-1. Halfwavelength rectangular microstrip patch antenna. An approximate value for the length of a resonant half-wavelength patch is r dL 49.049.0 (3.1) where, is the free-space wavelength, d is the wavelength in the substrate, and r is the relative dielectric constant of substrate. The region between the conductors acts as a ha lf-wavelength transmi ssion-line cavity that is open-circuited at its e nds. Figure 3-1(b) shows th e electric fields associated with the standing wave mode in the dielectric. The electric fiel d lines are perpendicular to the conductors as required by the boundary conditions and look much like those in a parallel plate capacitor. The fringing fields at the ends are exposed to the upper half-space and are responsible for the radiation. The standing wave mode with a half-wavelength separa tion between the ends leads to 45

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electric fields that are of opposite phases. Theref ore, the total fringing fields at the edges are 180 out of phase and equal in magnitude. The peak radi ation is in the +z direction. The radiation edge can be thought as a slot. The widt h of a slot is often taken to e qual to the substrate thickness. The patch radiation is lin early polarized in the x-z plane, that is parallel to the electric fields in the slots. The radiation pattern of a r ectangular patch antenna is ra ther broad with the maximum direction normal to the plane of the antenna. Pa ttern computation for the rectangular patch is easily performed by first creating equiva lent magnetic surface currents. nEMas 2 (3.2) where, is the fringe electric field in each of the edge slot. aE The factor of 2 comes from the image of the magnetic current in th e electric ground plane. The far-field components are ),(sincos ),(cos f EE fEEo o (3.3) where, cossin 2 cos sinsin 2 sinsin 2 sin ),( L W W f (3.4) is the usual free-space phase constant and equal to ( /2 ). The first factor in equation (3.4) is the pattern factor fo r a uniform line source of width W. The second factor is the array factor for a two-element array along the x-ax is corresponding to th e edge slot [21]. Typical input impedances at the edge of a re sonant rectangular patc h range from 100 to 400. An approximate expression for the input impe dance of a resonant edge-fed patch is 46

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)( 1 902 W L Zr r A (3.5) 0 0.2 -0.2 0.5 -0.5 1 -1 2 -2 5 -5 .2.5125 4m 5m 6m 7m 8m 9m 10m 240GHz 260GHz Resonant frequencies Figure 3-2. 50reflection coefficients of patch ante nnas with varying substrate thickness. The substrate thickness of dielectric layer between the patch and ground plane is a dominant design factor of patch an tennas. There is a great deal of flexibility for the choice of dielectric thicknesses of a microstrip patch ante nna design when a printed circuit board (PCB) is used. However, a given CMOS pr ocess has a fixed dielectric th ickness between the top to bottom metal layers. Figure 3-2 shows the 50reflection coefficient of patch antennas with varying dielectric thicknesses. The patch antenna size is about 300 m. A patch antenna with a 4 m thick dielectric layer has the smallest input im pedance at its resonant frequency and a patch antenna with a 10 m thick dielectric layer has the larg est input impedance at its resonant frequency. Relative dielectric constant of substrate is 3.7 an d conductivity of metal is 4.6 10 7 Simens/meter. Figure 3-3 shows th e input resistance and radiation e fficiency of patch at varying 47

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dielectric thicknesses. When the thickness is 10 m, the efficiency approaches 45% and the resistance becomes about 140 5 6 7 8 9 10 0.2 0.4 0.6 0.8 1 EfficiencyDielectric thickness [ m] 5 6 7 8 9 10 40 60 80 100 120 140 Input resistance [ ] Figure 3-3. Input resistance and radiation efficiency of patch antennas at varying dielectric thicknesses. The input resistance can be controlled by a qua rter wave length transformer formed by the antenna feed. A thicker substrate increases efficiency and input resistance. CMOS processes with thicker dielectric layers are pr eferred for patch antenna design. Figure 3-4 shows the 50 reflection coefficient of patch antennas with varying different patch sizes. The trajectory of input impedance of patch antennas on a smith chart is mainly determined by the dielectric layer thickness. The patch size determines the resonant frequency. 48

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0 0.2 -0.2 0.5 -0.5 1 -1 2 -2 5 -5 .2.5125 296m 304m Figure 3-4. 50reflection coefficients for varying patch sizes. 290 295 300 305 310 245 250 255 260 265 Resonant Frequency (GHz)Size of a square patch antenna( m) 290 295 300 305 310 0.29 0.3 0.31 0.32 Efficienc y Figure 3-5. Resonant frequencie s and radiation efficiency for varying patch antenna size. 49

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0 0.2 -0.2 0.5 -0.5 1 -1 2 -2 5 -5 .2.5125 r=3.2 r=3.6 r=4 Figure 3-6. 50reflection coefficients of patch ante nnas for varying dielectric constants. The frequency range in Figure 3-4 is from 240 to 260 GHz. If the patch size is increased, then the reflection coefficients rotate clockwise and the resonant frequency goes down. There is a little change of input impedance at the reso nant frequency. Figure 3-5 shows the resonant frequencies and radiation efficien cies of patch antennas with varying sizes. As a patch becomes smaller, the resonant frequency increases and dielectric thickness to wavelength ratio becomes higher. This increases the input resistance and radiation effici ency. The efficiency of patch antenna improves with frequency, while the size becomes smaller. Cleary, use of on-chip antennas becomes easier at higher operating frequencies. Figure 3-6 shows the 50 reflection coefficients of patc h antennas for varying dielectric constants. The dielectric layer thickness is 8 m. The patch antenna size is about 310 x 310 m 2 50

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Increasing the dielectric constant decreases the wavelength in the dielec tric and decreases the resonant frequency at given patch size. The ch anges in dielectric constants do not significantly modify the trajectory in a smith chart and rotate the trajectory. 3.3 Microstrip Patch Antennas on CMOS Technology Dielectric layers in a CMOS process have various thicknesses and dielectric constants. Antenna simulations solve a structure with dimensions on the order of a comparable with wavelength. For example a dipole antenna has a half wavelength and the surrounding air box is about 3/4 wavelength. So, simulation structures are bigger than that for discrete devices such as capacitors and inductors. It is not efficient in tim e to include all dielectrics in EM simulation. Sometimes, it is not possible to include all the diel ectric layers. An effective dielectric constant can be used in simulations. First, a small section of a microstrip with all the dielectric layers can be simulated and propagation constant and characteristic impedance of the microstrip can be extracted. Second, a small section of a microstrip using a dielectric la yer with an effective dielectric constant can be simulated. Propagation constant a nd characteristic impedance can be matched with the microstrip with all the dielectric layers by adjusting the effective dielectric constant. 3.3 The Impact of Bond Wires on On -Chip Patch Antenna Performance As discussed at chapter 2, a concern for on-ch ip antennas is how their characteristics are modified by nearby metal structures. The interfer ence study in chapter 2 shows that the metal structures significantly affect the on-chip antenna characteristic s, such as gain, phase, and antenna input impedance and the impact on on-chip antenna performance increases with the size of metal structures. Approaches to guarantee the characteristics of on-chip antennas are critical for communication circuits and systems with on-chip antennas. The ground plane of the patch 51

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antenna decreases the interference to nearby circ uits. How the patch antenna characteristics are modified by nearby bond wire s is another concern. Figure 3-7. Cross section of a patch antenna with bond wires. 50 100 150 200 250 300 350 400 450 90 95 100 105 110 Distance ( m) Figure 3-8. Input resistance of patch antenna s with varying distances to bond wires. 52

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Figure 3-9. On-chip patch antenna directivity with varying distances to bond wires. Figure 3-10. Radiation pattern of patch antenna with varyi ng distances to bond wires ( =0). 53

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To study this, the effects of bond wires near on-chip antenna have been simulated. The Ansoft HFSS has been used for this purpose. Three bond wires are place near an on-chip patch antenna. The bond wire length is about 1mm in Figure 3-7. The distance from the bond wires to antenna has been changed and the antenna input impedance, resonant frequency, di rectivity, efficiency and radiation pattern have been simulated. Figure 3-8 shows the input resistance of on-chip patch antenna with varying distance to bond wires from 50 to 450 m with 100 m steps. The input resistance maintains about 101 for spacing greater than 150 m. The input resistance becomes 97 at 50 m. Figure 3-9 shows on-chip patch antenna directivity with varying di stances to bond wires. The directivity is about 5 down to 250 m. It gradually decreases and reaches 4.3 at 50 m. The efficiency of patch antenna is about 32 % for all cases. Figure 3-10 shows the radiation pattern of patch antenna with varying distances to bond wires at =0. Ideally, directio n of peak radiation is normal to antenna patch antenna surface ( =0, =0 ). The maximum radiation directions are 360 (0), 359, 356, 351, 347, 340 at the distances of 450, 350, 250, 150, 50 m, respectively. 3.4 Summary This chapter presented the basic properties of patch antenna. The radiation mechanism of radiation on patch antenna is di scussed and the simple equations for the patch antenna size and input impedance are presented. Th e design of patch ante nna in CMOS processes is limited by the fixed dielectric layer thickness, which limits the input resistance and efficiency. The impact of bond wires on on-chip patch antenna performance is presented. The bond wires change radiation direction by ~13 at the distance of 50 m and decrease the input resistance by 4 The minimum distance from antenna to the bond wires can be set to 150 m based on input resistance changes. 54

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CHAPTER 4 MILLIMETER-WAVE SCHOTTKY DIODE D ETECTORS IN CMOS TECHNOLOGY 4.1 Introduction The uses of millimeter and sub-millimeter-waves in radars, remote sensing, advanced imaging, and bio-agent and chemical detection [4 ], [40] have been ex tensively studied. A key limitation for wide scale utilization of these is the high cost of circuits. A 182-GHz Schottky diode detector fabricated in f oundry 130-nm CMOS technology is pr esented in this chapter. The design of a Schottky barrier diode detector with an on-chip patch antenna in 90nm CMOS process also discussed. Integrat ion of those type of detectors with an on-chip antenna and baseband electronics in CMOS s hould allow single-chip realizatio n of low cost millimeter and submillimeter-wave systems [33]. 4.2 A Schottky Barrier Diode in CMOS Technology Schottky barrier diodes due to their high operating frequencies and a low forward-voltage drop have been widely used. Operation of the Schottky barrier diode depends only on the majority carrier conduction, in contrast to pn junction diodes which rely on both majority and minority carriers for their operations [16]. Th e series resistance and junction capacitance determines the frequency response for Schottky diodes. Schottky diodes with a cutoff frequency greater than 1 THz have been demonstrated in the UMC 130-nm digital CMOS process [16]. The diodes are formed by blocking n + implant over selected diffusi on regions in a n-well. The formation of diode requires no modifications to the existing CMOS flow [16]. A cross-section of a representative Schottky barrier diod e cell is shown in Figure 4-1. A CoSi 2 -Si junction forms the Schottky diode. Ohmic contacts around the Schott ky contact form the second terminal. To improve f cutoff given in (4.1), both the series resistance R s and the capacitance C o must be lowered [16]. 55

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Figure 4-1. A Schottky diode implemented in CMOS process. To minimize R s at given C o the diode is formed by para llel connecting minimum area Schottky contacts (0.32 x 0.32 m 2 ) os cutoffCR f 2 1 (4.1) Using such diodes, it should be possible to implement dete ctors operating in the high end of millimeter-wave to the lower end of sub-millime ter-wave bands. To investigate this, a detector operating ~180 GHz has been implemented in th e 130-nm CMOS process using a diode formed with 16 of the 0.32 x 0.32 m 2 cells connected in parallel. The series resistance of the Schottky diode is about 10 and junction capacitance is 12 fF at zero bias. 4.3 Sensitivity Analysis of Schottky Barrier Diode The tangential sensitivity and noi se equivalent power (NEP) are used to describe detector performance. Noise equivalent power is defined as the RF input power required to produce an output signal-to-noise ratio of unity, for signal with a bandwidth of the square root of one hertz [34]. The assumption of unit band width is useful for examini ng devices operating at video frequencies in the 1/ f noise region. Tangential sensitivity (TSS) is the lowest signal power level 56

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for which the detector will have a specified signal-to-noise ratio at the output. Agilent Technologies specifies TSS at the output signal-to-noise ratio of 8 dB. The units for TSS are dBm or milli-watts. In this chapter, the basic operation of detector s is reviewed [34], [35] The noise equivalent power is derived as a function of the id eality factor (n), series resistance (R S ), and junction capacitance (C B ). The noise equivalent power and tangentia l sensitivity are related to each other, and these parameters entirely depend on the id eality factor, series resistance and junction capacitance. The derivation shows the relation. It was assumed that all of the available RF power is absorbed by the device. The current-voltage function of a nonlinear de vice can be denoted by )( vfi (4.2) and tAVv cos0 (4.3) where, is dc bias voltage and ac input voltage is 0V cos At Expanding (4.2) with a power series around and substituting (4.3) 0V )cos()(0tAVfvfi (4.4.1) 5 0 )5( 4 0 )4( 3 0 )3( 2 0 )2( 0 )1( 0)cos( 120 )( )cos( 24 )( )cos( 6 )( )cos( 2 )( )cos)(()( tA Vf tA Vf tA Vf tA Vf tAVfVf (4.4.2) ) 8 4cos2cos43 ( 24 )( )3coscos3( 46 )( 2cos1 22 )( )cos)(()(3 0 )4( 3 0 )3( 2 0 )2( 0 )1( 0tt A Vf tt A Vf t A Vf tAVfVf (4.3.3) tf A Aff A f A IiVficos 8 644 )()3( 3 )1( )4( 4 )2( 2 0 0 (4.4.4) 57

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The average ac power, P absorbed by the device can be found by multiplying (4.4.4) with the input voltage, tA cos and integrating over one period. This leads to the following expression for P tAIiVvIi cos0 0 0 (4.5.1) t A f A AftAf A f A 2cos1 28 cos 644)3( 3 )1( )4( 4 )2( 2 (4.5.2) 2 )3( 3 )1( )4( 4 )2( 2cos 8 cos 644 tAf A AftAf A f A (4.5.3) )3( 2 )1( 2 0 0 082 1 f A f A dtIiVv T PT (4.5.4) The first term in the bracket on the right-ha nd side of (4.4.4) is the detected current i the time average of quantity incrementally increased due to the application of ac power. The ratio of to P is called the current respons ivity and can be written as. i )3( 2 )1( 2 )4( 4 )2( 282 644 f A f A f A f A P i (4.6.1) )1( )3(2 )2( )4(2 )1( )2(8 1 16 1 2 1 f fA f fA f f (4.6.2) 2 1 01 1 (4.6.3) where, )1( )3( )2( )4(8 16 2 12 2 2 1 )1( )2( 0f fA f fA f f 58

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This current responsivity can be approximated as, 1 10210 (4.7) where, )1( )3( )2( )4( )1(2 8 1 f f f f f P The quantity, 0 is the low-level current responsiv ity of the device. The quantity shows how at a given power level, the detector respons e deviates from true the square law operation. 1 exp v nkT q IiS (4.8) where, n is a number greater than unity. RSCBRB V I V1 V2 I1I2 Figure 4-2 Equivalent circuit m odel of Schottky barrier diode. Figure 4-2 shows an equivalent circuit mode l of Schottky barrier diodes. The elements R B and C B are, respectively, the incremental resistance and capacitance associated with the junction, while R B S is the parasitic series resistance associat ed with the silicon substrate and contact. S BIIq nkT R 0 (4.9) 2/1 001 BV V C CB (4.10) 59

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The part of power absorbed in the device is dissipated in the parasitic series resistance R S A simple analysis of the equivalent circuit in Figure 4-2 yiel ds the following relation for the ratio of the power absorbed in R B ( P B B B ) to the total RF power, P 2 2 22 2 22SBB SB SBB SBRRCRR RRCRR V P (4.11) 2 2 22SBB SB B BRRCRR R V P (4.12) 2 22 2/11 1c B S SBB SB B Bff R R RRCRR R P P (4.13) where, 2/1 2/12 1BSB B S cRRC R R f The ratio of and is i BP B S BP IInkT q nkT q P i08 1 1 2 (4.14) and 2 0/11 1 2 'c B Sff R R nkT q P i (4.15) where, 0 is the low-level current responsivity for the device. In order to calculate the sensitivity of Scho ttky diode, the noise prope rties of device must be known. Schottky diodes exhibit 1/ f noise, in addition to white noise. The noise of Schottky diodes can be characterized in te rms of noise temperature ratio t The incremental detected current corresponding to a given input power P is simply 60

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PiiS 0 (4.16) Ni Si 2/14 V NR kTt i Figure 4-3. Noise equi valent circuit model of the Schottky diode. The white noise current in the device is 2/14 V NR kTt i for a unit bandwidth. The noise equivalent power is th at input power which results in equal output signal and noise power, or equivalently, equal signal and noise current at the output. 0 Ni NEP (4.17) A device with 1/ f nose has a noise temperature ratio given by the expression, V N wf f tt 1 (4.18) where, is the noise corner frequency, the video frequency, and is the white-noise temperature ratio. Nf Vf wt )/( 1 11 4 22/1 2 2/1 2/1HzW f f f f R R R kTt q nkT NEPV N C B S B w (4.19) The NEP in equation (4.19) depends on the ideality factor (n), series resistance (R S ), and junction capacitance (C B ). It also depends on RF frequency ( f ), noise corner frequency (f N ), and video frequency ( f V ). 61

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Tangential sensitivity ( TSS ) is the lowest signal power le vel for which the detector will have a specified signal-tonoise ratio at the output. TSS can be expressed in (4.20), where B is the bandwidth of signal. )( log58 dBm B ENP TSSdB dB (4.20) Figure 4-4. NEP (pW/Hz 1/2 ) with various number of cells. The NEP mostly depends on the diode characte ristics. For a given diode, NEP and TSS can be calculated. The junction barr ier resistance and capacitance are bias dependent, so the optimum bias point can be determined. Also there is flexibility of choosi ng the number of diode cells and area of the Schottky diode cell in CMOS. The remaining paramete rs for the detector design are the number of cells and diode bias voltage. Figu re 4-4 shows the NEP at the various number of 0.32 x 0.32 m 2 Schottky diode cells in the 130-nm CMOS. The NEP varies from 2 to 5 pW/Hz 1/2 and the minimum number of cells shows the lowest NEP of 2.3 pW/Hz 1/2 The 62

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capacitance is a dominant factor in NEP calcula tion at 250 GHz. The structure with the minimum number of cells has the smallest capacitance an d has the best NEP calculated using (4.19). The frequency is 250 GHz, the ideality factor (n ) is 1.3, the white temperature ratio ( t w ) is 1.2 [34], the series resistance (R S ) is 13 the noise comer frequency is ( f N ) is 1 MHz, and the video frequency ( f V ) is 10 MHz in the NEP calculation. The junction capacitance increases with bias voltage. The absorbed power ( P B) decreases with the increase of the capacitance and the NEP decreases. The R B B B decreases with bias voltage from 2380 to 300 when the applied bias changed from 0.2 to 0.5 V. The absorbed power increases with bias voltage when the junction capacitance effect is neglected. So, the optimum bias voltage can be found. Figure 4-5 shows the NEP at various bias voltage of diode. The figure shows the minimum point at 0.35 V and NEP is about 2 pW/Hz 1/2 Figure 4-6 shows the f c at various bias voltage of diode. The f c is defined in (4.13) and included in NEP. When the operating frequency of the detector is f c the absorbed power by the junction barrier is half of RF power ( P ). The f c in Figure 4-6 has highest value at 0.4 V and the lowest NEP is at the bias voltage of 0.35 V. The minimum number of cells and optimum bias point is required to obtain the lowe st NEP for a given Schottky barrier diode cell. 63

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Figure 4-5. NEP (pW/Hz 1/2 ) with varying diode bias voltage. Figure 4-6. f c with varying diode bias voltage. 64

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4.4 A 182GHz Schottky Barrier Diode Detector with a Modulator 4.4.1 Design Considerations The diode described in section 4.2 can be us ed to implement a millimeter-wave detector. A detector operating ~180 GHz has been implemente d using Schottky barrier diode fabricated in the 130-nm CMOS [33]. The diode is formed with 16 of 0.32 x 0.32 m 2 cells connected in parallel. The series resistance of Schottky diode is about 10 and junction capacitance is 12 fF at zero bias. The detector shown in Figure 4-7 co nsists of a matching circuit, a Schottky diode, a low pass filter, and an amplifier for driving 50 The diode has been fo rward biased through an 1-k (R3) resistor. The detector i nput impedance is conjugately matched to the signal source impedance at the frequency of 180GHz with C 5 C 6 and L 7 The low pass filter consists of C 7 C 8 and L 8 It has a corner frequency of ~10 GHz The diode has poor isolation and input matching changes with the circuits connected to the second terminal. Because of this, impedance of low pass filter and amplifie r stage should be considered for the matching at 180 GHz. VoscVbiasIN OUT VdiodeVamp Detector Low pass Filter R1R2C3M7C4Trans.Line M1M2M4M6M3M5L1L2L3L5L6L4 VctrlVbufVbuf +Vout,1f -Vout,1f C5C6L7C7L8C8VC M12M8M9R5SV M10M11R3 VCO R4 Figure 4-7. Schematics of modulator and detector. 65

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C 7 is a 400-fF capacitor and its impedance is close to short at 180 GHz, so C 7 provides isolation to RF. It is straight forward to design the input matching circuits, when the diode is followed by a low pass filter. To evaluate the detector, a source for modulat ed 180-GHz signal is needed. Since, such a source is not widely available. A 180-GHz signal generator has been integrated with the detector. CMOS millimeter-wave VCOs with ~100-GHz f undamental operating frequency have been reported [10]. To obtain even higher frequencies, push-push topologies have been utilized to achieve operation at 131 [36] and 192 GHz [11] in 90 and 130-nm CMOS technologies. To the 192-GHz VCO, buffers (M 3 -M 6 ) are added to monitor the fundame ntal output (Figure 4-6). This lowers the frequency at push-push port to ~182 GHz. The amplitude of this VCO is modulated by changing the gate voltage of M 7 or the bias current (I bias ) of the oscillator. The modulating signal is AC-coupled to M 7 through a capacitor (C 3 ). A shunt 50(R 1 ) termination resistor is added to make the input amplitude at gate of M 7 more predictable. The bypass capacitor, C 4 is an AC-short for the signal near 180GHz, while it presents high impedance for the modulating signal. Since changing I bias also modifies the drain voltage of VCO core transistors thus the capacitances of L-C tanks [11] the input signal should also modulate the output frequency. 4.4.2 Experiment Results Figure 4-8 shows the voltage waveforms of modulation and detected signals across a 50 load, when the VCO is modulated with a 10 MHz sine wave with 0.1 V amplitude. V DD of VCO is 1.75 V. The dc bias voltage at gate of M 7 (V bias ) is 0 V. The 10-MHz input frequency is chosen to attenuate the un-intended feed through of modulati on signal through C 5 (50fF). The detected signal frequency is the same as that for the modul ation signal. Figure 4-8 also shows the voltage 66

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waveform when the V DD for VCO is 0.3 V at which the VCO no longer oscillates. The detected signal is nearly flat, indicating that as expected, the presence of a carri er is critical for detection. 0 20 40 60 80 100 120 140 160 180 200 -0.2 -0.1 0 0.1 0.2 Amplitude(V) 0 20 40 60 80 100 120 140 160 180 200 -60 -30 0 30 60 Amplitude(mV)Time (ns) Figure 4-8. 10-MHz input and output signals (V DD =1.75 and 0.3 V). Figure 4-9 shows the detector output with V diode =1.78 and 0V. The V osc is biased at 0.3 V. When the V diode biased at zero voltage or I diode = 0, the detector output is undetectable, indicating that the unwanted coupling is not propagating through the ground or power lines. The signals propagate through the Scho ttky diode and diode. Figure 4-10 shows the spectra at the fundamental output (f o ) with and without 0.1-V amplitude 10-MHz single tone modulation signal at V bias (M 7 ) of 0 V. The AM side bands at the multiples of 10 MHz away from the carrier are s een due to the squaring of modulation signal. The carrier frequency in Figure 4-10 is shifted down by ~ 80 MHz probably due to the change of dc bias by the modulating signal. 67

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0 40 80 120 160 200 -80 -40 0 40 80 Amplitude(mV)Time(ns) Vdiode=1.78V Vdiode=0V Figure 4-9. 10-MHz input and output signals (V diode =1.78 and 0 V). Figure 4-10. Spectra of modulated and un-modulated carriers (~91 GHz). 68

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The peaks have a finite bandwidth because the oscillator is free running, and the FM signal could not be distinguished. To avoid loading the push -push port, the modulation is monitored at the fundamental output port. Another concern for the circuit is whether the detector is sensing th e modulated signals at fundamental or the second harmonic. To examine this, a VCO test structure has been measured with Agilent 11970W (75-110GHz) and OML M05HWD (140 to 220 GHz) harmonic mixers, and an E4448A spectrum analyzer. Th e bias current is 15mA and V DD is 1.75V. Figure 4-11 shows the power levels at the push-push port near the fundamental (f o ~ 91GHz) and two times the fundamental frequency (2f o ~ 182GHz) versus V bias at the gate of M 7 The power level for 182-GHz signal is ~-20dBm after de-embeddi ng the harmonic mixer and waveguide probe losses. Figure 4-11. Power at 91GHz (f o ) and 182GHz (2f o ) signals on the push-push port versus V bias plot. 69

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Due to the coupling through the substrate a nd metal interconnects, the signal near f o (~-32 dBm) also appears at the push-push port. The matc hing circuit preceding the Schottky diode should further attenuate the signal near f o by ~10 dB. Additionally, th e power of signal near f o is relatively constant while the signal at 2fo changes by ~2 dB over the bias range. This means the input signal more strongly m odulates the signals near 2f o Because of these, the circuit in this V bias range should be detecting th e 182-GHz modulated signal. As the diode detector bias current (I diode ) is increased, the output power increases because of a larger diode current change for a given input voltage swing. At much higher currents, the output power drops with input power. The output power is peaked at the diode current and voltage of around 0.7mA and 0.45 V. Figure 4-11 shows the detector output power versus the amplitude of modulation signal at 10 MHz. The V bias and V DD of modulator are 0 and 1.75 V. The detected signal power increases monotonically with the input amplitude. Although, data are not included, the circuit has been used to detect signals with modulation frequency up to 1 GHz. Figure 4-12. Detector output amplitude versus input modulation power. V bias =0 V and V DD =1.75 V. 70

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Figure 4-13. Die photograph of detector with modulator A micrograph of the circuit is shown in Figure 4-13. The chip size is 1120 x 600 m 2 including bond pads. 4.5 A Schottky Barrier Diode Detector with an On-Chip Patch Antenna in 90nm CMOS 4.5.1 Design Considerations A 250-GHz Schottky detector with an on-chip patch antenna is also implemented in this chapter. The diode is formed with 14 cells (0.32 x 0.32 m 2 ) connected in parallel. The estimated series resistance of Schottky diode is about 25 and junction capacitance is 6 fF at zero bias. The measured series resistance of Schottky diode is about 120 and junction capacitance is about 10 fF at zero bias. The large series resi stance is caused by the shallow trench isolation (STI). The detector consists of an on-chip patch antenna, a matching circuit, Schottky diode, low-pass filter, and amplifier. The Schottky barrier diode is connected in shunt to reduce the impact of parasitic capacitance associated with the n-well. 71

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Figure 4-14. Schematic of 250-GHz Schottky diode detector. The On-chip patch antenna has a patch area of 330 x 315 m 2 Metal 1 and 2 are connected together and used as ground. The pad layer is used to form the patch. The diode has been forward biased through a 2.5-k (R 1 ) resistor. T.L 1 T.L 2 and C 1 comprise a matching circuit and provide 50 at the on-chip antenna. C 1 is a 20-fF metal capacitor a nd presents high impedance to baseband signals. C 2 is a 100-fF capacitor. C 2 is almost a short at RF. C 1 and C 2 provide isolation between RF and baseband signals and simplifies the design of circuit. The transmission line is a grounded coplanar waveguide (GCPW). The ground pl ane of GCPW is made of metal 1-2 and pad layer is used for signal line. Amplifier, C 3 and C 4 have a band-pass response. The amplifier has low-pass response and the series capacitors have high pass-filter, so the band-pass response function is filters the low and high frequency noise. The pa ss band is 1 300 MHz with a load composed of 1 M load resistor in parallel with a 10 pF capacitor. Figure 4-15 shows the voltage gain of the amplifier with 1 M load and varying load cap acitances. With 1 pF load capacitor, the gain and bandwidth becomes the largest. As the load capacitor increases, 72

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Figure 4-15. Voltage gain of amplif ier with various load capacitors. 10-1 100 101 102 5 5.5 6 6.5 7 Frequency (MHz)Equivalent Input No ise (nV/sqrt(Hz)) Figure 4-16. Equivalent input noise of amplifier. 73

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gain and bandwidth decreases. Th e amplifier generates noise and increases NEP. The noise of amplifier can be specified with an input noise voltage over frequency. Simulations show the minimum noise voltage of ~ 5 HznV / within the 1-30 MHz pass band in Figure 4-16. 4.5.2 Experiment Results Figure 4-17. Die photograph of de tector with a patch antenna Schottky barrier diode in the UMC 90-nm CMOS is used to implement a millimeter-wave detector. A detector operating ~250 GHz has been implemented. The chip size is 550 x 1100 m 2 The measured series resistan ce of Schottky diode is about 120 and junction capacitance is about 10fF at zero bias as shown in Figure 4-18. The estimated C B was about 6 fF and 74

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measured C B is about 10 fF. The estimated R S was about 24 and measured R S is about 124 The main reason of increase of series resistance is caused by the thicker sallow trench isolation (STI). Figure 4-19 shows the cross section of a Schottky diode in the 90-nm CMOS. The depth of STI is about 0.4 m. As the Schottky diode area become s narrow, the current can flow only through narrow area between the STIs. The resistance increases with increasing STI depth and by decreasing Schottky diode area. The increased junction capacitance (C B ) and series resistance (R s ) decreases the cut-off frequency and degrades the sensitivity of the detector in Figure 4-19. The tangential sensitivity increased from 68 dBm to -56dBm. A 250-GHz AM transmitter has been used as the signal source. The output power of the AM transmitter is about -34 dBm and path loss of the transmitter and the diode detect or is about 36 dB at 1cm separation in Figure 420. The antenna directivity is 5 and the efficiency is about 32 % in the path loss calculation. The input power to the detector is about -70dBm and is smaller than the sensitivity of detector and the amplitude modulate signal could not be detected. 15 16 17 18 19 20 6 8 10 12 14 16 18 20 CB(fF)Frequency (GHz) 15 16 17 18 19 20 40 60 80 100 120 140 Rs ( ) Estimation Estimation 75

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Figure 4-18. Series resistance and capaci tance at zero bias of Schottky diode. Figure 4-19. Cross section of the Schottky barrier diode. Figure 4-20. Calculated tangential sensitivity of the detector. 76

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Figure 4-21. Path loss between two patch antennas. 4.6 Summary Key parameters that are used to specify dete ctor performance are presented. The NEP of diode detector has been estimated to be~2 HzpW / A 182-GHz Schottky diode detector fabricated in foundry 130-nm CMOS technology is demonstrated. A 182GHz AM modulator is implemented by changing the gate bias of PMOS and verified by the measurement of 91-GHz AM signals using OML harmonic mixer at the fundamental buffer output. When the VCO is modulated with a 10 MHz sine wave with 0.1-V amplitude, 10 MHz signal with 45mV amplitude is detected at the de tector output. Design and analysis of a 250-GHz Schottky barrier diode detector with an on-chip patch antenna im plemented in 90-nm CMOS are also discussed. 77

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CHAPTER 5 OPTICAL MEASUREMENT METHODS FO R MILLIMETER AND SUBMILLIMETER WAVE OSCILLATORS 5.1 Introduction The measurement of submillimeter-wave oscillator is challenging. The output power of oscillator typically decreases with operating fr equency. The harmonics mixer loss increases with frequency. The down converted signal could be smaller than the noise level and can not be detected. Also, high-frequency prob es are not available at THz. Of f the shelf electrical probes go up to 325 GHz. To overcome the difficulties an optic al technique is utilized. Power from an onchip antenna can be measured using a bolometer and the frequency spectrum of circuits can be measured using a Fourier transform infrared spec troscopy (FTIR) [37]. A combination of optical and electronic measurement techniques is required for terahertz systems. 5.2 Bolometer A bolometer is an instrument for detecting and measuring radiation, e.g., visible light, infrared radiation, and ultraviolet radiation, in amounts as small as one millionth of an erg [38]. The bolometer was invented in 1880 by Samuel P. Langley. It consists of a radiation-sensitive resistance element in one branch of a Wheatston e bridge. Changes in radiation cause changes in the electrical resistance of the element. The radiation-sensitive element may be a platinum strip, a semiconductor film, or any other substance whose resistance is altered by slight changes in the amount of radiant energy falling on it, which heats the element [38]. Figure 5-1 shows a silicon bolometer (HD-3, IR Lab) with a preamplifier. The silicon bolometer element is mounted in the configuration in conjunction wi th a parabolic cone collector. The composite silicon element mounted on a cylindrical cavity. Li quid Helium is used to cool the bolometer to 4.2K. The change in radiation results resistance change. This will appear at the amplifier output. The optical 78

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responsivity of the bol ometer is 1.1 10 4 (V/W). The bolometer elements have limited bandwidth and silicon bolometer elements ha ve constant responsivity up to THz. RL12K Bolometer J-FET 120 F Vout VBias9 V window Vacuum valve Nitrogen can Helium can Parabolic cone collector Bolometer Figure 5-1. Bolometer with preamplifier. Figure 5-2. Power measurement using a bolometer and a lock-in amplifier. A bolometer and a lock in amplifier have been used to measure radiated power from an onchip antenna. The lock-in amplifier (ITHACO 39 3) is a homodyne receiver with an low pass filter with extremely lower bandwidth ( ~0.1 Hz) and use mixing, to convert the signal's phase and amplitude to DC [39]. We modulated the supply (V DD ) of oscillator with 100 Hz. The modulated signals go to bolometer and lock in amplifier mixes the signal from bolometer and 79

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100 Hz pulse from the signal generator. The meas ured power is the radi ated power through the on-chip antenna. 5.3 FTIR The FTIR (IFS 113v, Bruker) system shown in Figure 5-3 consists of a source, an interferometer, and a silicon bolometer. The desi gn of many interferomet ers used for infrared spectrometry today is based on that of the twobeam interferometer or iginally designed by Michelson in 1891. Many other bolometer source optical path Interferometer source bolometer PC (FFT) mirror beam splitter Movable mirror Figure 5-3. FTIR measurement setup. two-beam interferometers have subsequently been designed that may be more useful than the Michelson interferometer for specific applications Nevertheless, the theory behind all scanning two-beam interferometers is similar, and the general theory of interferometry is most readily understood by studying the way in which a simple Michelson inte rferometer is used for the measurement of infrared spectra [38]. The Michelson interferometer is a device that can divide a beam of radiation into two paths and then recombine the two beams after a path di fference has been introduced. The variation of intensity of the beam emerging from the interf erometer is measured as a function of path 80

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difference by a detector. The simplest form of the Michelson interferomet er is shown in Figure 5-4. It consists of a beamsplitter, fixed mirro r and movable mirror. The beamsplitter divides a beam from the source to the fixed mirror and movable mirror. It combines the reflected beams from the fixed mirror and the movable mirror. F M O Figure 5-4. Michelson interferometer. An ideal beamsplitter transmits 50% of incident beam and reflects 50 % at all frequency range. Beamsplitters are made w ith thin dielectrics and have non-ideality caused by thickness as well as loss of dielectrics. The finite thickne ss causes multiple reflections in beamsplitters. So reflectance and transmittance depend on frequency and beamsplitters have a finite bandwidth. Figure 5-5 shows transmittance of FTIR with beamsplitters (Mylar, r =3.2). A mercury source is used and 7-mil and 5-mil beamsplitter are used to measure the transmittance. The 7-mil beamsplitter has a null point around 500 GHz a nd 5-mil beamsplitter has one around 780 GHz. No signal is detected at null points. The approp riate beamsplitter must be properly chosen to measure the spectrum of millimeter-wave and submillimeter-wave oscillators. A 7-mil beamsplitter has been used for 250-GHz VCO meas urements and a 5-mil beamsplitter has been used for 410-GHz oscillator measurements. 81

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0 200 400 600 800 1000 -0.2 0 0.2 0.4 0.6 0.8 Frequency (GHz) 5-mil beam splitter 7-mil beam splitter Null point Null point Figure 5-5. Null points of beam splitters. 5.4 Interferogram Consider an idealized situation where a sour ce produces a pure sign al tone sine wave. Assume the beam splitter is non-absorbing film whose reflectance and transmittance are both exactly 50 %. The path difference between beam s that travel to the fixed and movable mirrors and back to the beam splitter is 2(OM-OF) in Figure 5-4. This path difference is 2. When the fixed and movable mirrors are placed at the sa me distance from the beamsplitter (zero path length difference), the two beams are in phase on recombination at the beamsplitter. At this point, the beams constructively inte rfere in Figure 5-6(a). The beam that is reflected by a mirror at normal incidence undergoes a phase change of 90. The phase of the transmitted beam is unchanged. 82

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Figure 5-6. Reflected and combined waveforms at 400 GHz. For the beam incident to the detector, th e beams to fixed and movable mirrors both undergo a total phase change of 270 and they ar e in phase at the beam splitter. If the movable mirror is displaced a distance of as in Figure 5-6(b) the path length is 0.5 At the beamsplitter, the beams are out of phase and destructively interfere. The amplitude of signals incident to the detector is zero. Once again, if the movable mirror is displaced a distance of as in Figure 5-6(c) the path length is At the beamsplitter, the beams are in phase and constructively interfere. If the mirror is move d at constant velocity, the constructive and destructive interference occurs continuously. The amplit ude of signal to the detector is sinusoidal. Assuming the frequency of signal from the source is 400GHz, the period is 2.5 ps and wavelength in air is 0.75 mm. 83

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) 2 2cos1()(0 I (5.1) ) 2 2cos1()(0t V tIM (5.2) where V M is mirror velocity and tVM Figure 5-7. Interferogram with mirror velocity (V M ) of 10 cm/sec. Referring to the Inteferogram in Figure 5-7, the output of bo lometer, shows the amplitude of signal from the interferometer. The intensity of combined beam as a function of the position of movable mirror can be expresse d by (5.1). The mirror velocity is known, so equation (5.1) can be expressed in (5.2) and waveform in Figure 5-7(a) can be converted to waveform shown in Figure 5-7 (b). If the mirror velo city is 10cm/sec then the dete cted waveform is about 267 Hz. Finally, the 400 GHz signal can be indentified by detecting a 267 Hz sine wave. Figure 5-8 shows an interferogram with finite mirror mo vement. The mirror movement is limited and the 84

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FTIR system scan small portion of the interf eromgram. The recovered spectrum is convolved with a sinc function in the frequency domain. In stead of having an impul se, a sinc function will appear in frequency domain. Figure 5-8. Interferogram with finite mirror movement. Figure 5-9 shows the measurement setup with FTIR. A bolometer, interferometer and source are shown in Figure 5-9. The fabricat ed chips are mounted on PCBs and placed on the source position. The measured spectrum shows the signals from the source with noise. 200 to 1000 scans are made to average out the noise. Each measurement takes several hours. The background noise is time variant an d should be measured for each experiment. When the source turned off, the measured signal is the background. 85

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5.5 Summary This chapter presented the measurement of millimeter-wave and submillimeter-wave oscillators using FTIR system. Instruments usin g traditional electronic measurement techniques are not widely available for THz oscillator measurements. The operating principle of the Michelson interferometer is presented to describe the operation of an FTIR system. An FTIR system can specify spectra of millimeter-wave and submillimeter-wave oscillators. Using a bolometer and a lock-in amplifier, power of the THz oscillator can be estimated. Figure 5-9. Measurement setup using an FTIR. 86

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CHAPTER 6 MILLIMETER-WAVE AND SUBMILLIMETER VOLTAGE CONTROLLED OSCILLATOR IN CMOS TECHNOLOGY 6.1 Introduction As new wireless services continue to be introduced, the available spectrum becomes crowded. This has increased in terests for wireless system at higher frequencies where larger bandwidths are available. The uses of millimeter and sub-millimeter-waves in radars, remote sensing, advanced imaging, and bio-agent and chemical detection [4], [40] have been studied. A key limitation for wide scale utilization of th ese is the high cost of circuits. Monolithic millimeter and sub-millimeter wave integrated circuits can provide the size, weight, and performance advantages. Traditionally, high electron mobility transistor (HEMT) and heterojunction bipolar transistor (HBT) MMIC t echnologies have been utilized in millimeterwave applications due to thei r higher power capacity and supe rior low noise performance. With the rapid advance of high frequency capab ility of CMOS technology, it is becoming possible to make CMOS circuits operating in the millimeter-wave frequencies [11], [41]. A millimeter-wave CMOS VCO with 140-GHz fundame ntal operating frequency has been reported [11]. For the millimeter-wave and submillimeter-wave communications, a simple transmitter can be made using a VCO with a V DD modulation circuit and an ante nna. Signals received from an antenna can be recovered using a Schottky barrier diode detector. In this case, the oscillator frequency determines the maximum operating frequency of the system. The communication range is set by the output power of oscillator, when a power amplifier is not available. To design a VCO with good phase noise performance, a nd acceptable output power, the fundamentals of oscillators must be understood. 87

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6.2 Basic Operating Principles of Oscillator An oscillator is a circuit that converts energy from a power source to ac energy by generating a periodic output. The circuit has a self-sustaining mechanism that allows its own noise to grow and eventually become a periodic signal [42], [43]. An oscillator can be represented as a feedback ci rcuit shown in Figure 6-1. Figure 6-1. Feedback of an oscillatory system. )(1 )( )( )(sH sH sX sY (6.1) For s = j 0 H(j 0 ) = 1, then, the closed loop gain approaches infinity at 0 Under this condition, the circuit amplifies its own noise components at 0 A noise component at 0 experiences a total gain of unity and returning to the adder. After the adder, the signals are amplified again by the amplifier and continue to grow until the nonlinearity limits the amplitude. As the amplitude increases, the amplifier saturate s, dropping the loop gain to a low value at the peaks of waveform. Barkhausens criteria specify two conditions for steady oscillation. The loop gain, |H(j 0 )|, must be equal to unity, and the total phase shift around loop, H(j 0 ) must be equal to zero. Most RF oscillators include an LC tank as a frequenc y selective network for frequency stability as shown in Figure 6-2. The resonator consists of i nductor and capacitance of the cross-couple transistor. 88

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Figure 6-2. Feedback osci llatory system with a frequency selective network. The estimation of inductance and the quality factor of inductors are critical for determining the resonant frequency and output power of oscillators. 6.3 LC Resonant Tanks L1 C1 L1 RsC1 Lp RpCp (a) (b) (c) Figure 6-3. LC resonators (a) Ideal LC tank, (b) realistic LC tank and (c) equivalent parallel RLC tank. The inductor L 1 placed in parallel with a capacitor C 1 in Figure 6-3(a) resonates at a frequency 11 0/1 CL At this frequency, the impedances of the inductor, 01 jL and the capacitor, ) /(101 jC are equal and opposite, therefore yieldi ng infinite impedance. In practice, inductors and capacitors have parasitic resistances. The ci rcuit in Figure 6-3(b) can be transformed to that in (c) to simplify the analysis. 89

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L s pQ L L R LL 1 11 1 2 2 1 (6.2) 2 22 1 21Ls s s pQR R RL R (6.3) where, s LRLQ/1 The parallel network has th e similar reactance at high but has the resistance times the series resistance. The quality factor of the RLC resonant tank in Figure 6-3(c) can be defined as LQ 2 LQ pppp pCLRLRQ // /0 (6.4) where, ppCL /10 is resonant frequency of RLC tank in Figure 6-3 (c). The R s is the series resistance of inductor due to th e finite conductance of metal. R s increases with frequency because of the skin effect [22]. High is desirable to reduce power loss. At 200GHz, the skin depth of the conductor with a conductivity of 5.3 x 10 LQ 7 S/m is about 0.15 m. It will be challenging to achieve high inductors Q in the submillimeter-wave frequency. 6.4 Ring Oscillator One of the most popular ways of realizing digita l-output CMOS VCO is to use a ring oscillator [44]. A ring os cillator in Figure 6-3 is realized by placing an odd nu mber of open-loop inverting amplifiers in a feedback loop. The circuit is a form of negative feedback and the loop gain will be greater than unity when the pha se shift around the loop becomes greater than 180 Figure 6-4. A ring oscillator r ealized using five inverters. 90

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Each half-period, the signal will prop agate around the loop with an inversion. Assuming each inverter has a delay of inv and there are n inverters, then we have, inv2n T (6.5) inv osc2 11nT f (6.6) where, T is the oscillation period of oscillator. The operating frequency of ring oscillator is inversely proportional to the number of stages and delay of each inverter stage in (6.5). By ma king the delay of the inverters voltage controlled, the oscillating frequency can be voltage controlle d. In most integrated ring oscillators, fully differential inverters are used to obtain better power-supply rejection as shown in Figure 6-5. An even number of inverters can be used and inve rsion required around the loop can be achieved by simply interchanging the output polarity be fore feeding them back to the input. Figure 6-5. A ring oscillator realized using fully differential inverters. Figure 6-6 shows a fully differential inverter with a programmable delay cell. The current source and loads are made voltage programma ble capability. Assuming the current-source and loads are proportional to V cntl with a constant proportionality constant of K bias cntrlbias BVKI (6.7) 91

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The current I B is proportional to V cntrl in (6.7). The delay of each inverter is proportional to the bandwidth of inverter. m L invg C where, C L is the load capacitance of the inverter and g m is the transconductance of the drive transistors of the inverter. VcntlVin +Vout Vin Vout + Vcntlb VDDVDD 2IB Figure 6-6. A fully differential i nverter with programmable delays. Since, the transconductance is proportional to the square root of bias current ( B mIg ), the delay is inversely proportional to the square root of bias current (I B ) and square root of V cntl and therefore, operating frequency of ring oscillator is inversely proportional to the square root of V cntl ( cntl oscVf /1 ). 92

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6.5 Push-Push Oscillator Figure 6-7. Oscillators (a) funda mental oscillator, (b) oscillator with a frequency doubler and (c) push-push oscillator. Figure 6-7 shows three design approaches to generate submillimeter-wave signals. The first approach in Figure 6-7 (a) is to design a fundamental oscill ator at the desired frequency. This is straightforward, but the devices must have sufficient gain at the frequency of interest. A traditional approach is to design an oscillator an d include a frequency doubler as shown in Figure 6-7 (b). The oscillator is operating at half of output frequency. Additional filters and amplifiers may be needed. This increases th e circuit size and complexity. A pushpush oscillator in Figure 6-7(c) is a compact version of the oscillat or with frequency doubler A pushpush oscillator consists of two fundamental osci llators operating at half desired frequency. The oscillator works at lower frequency, so the Q of resonators is higher especially due to higher varactor Q. The tunning range is also higher varactors are availa ble. The maximum oscillation frequency of VCO is limited by the unity maximum available power gain frequency, f max of a transistor. Oscillation frequency higher than f max of device can be obtaine d using push-push topology. A pushpush VCO [12], [13] operatin g up to 192 GHz has been demonstrated in a 130-nm CMOS technology [12], [14]. 93

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6.6 A 250 GHz CMOS Push-Push VCO with AM Modulation 6.6.1 Design Considerations VDDVDDPatch Antenna M1M2M3M4T.L1T.L2L1L2C3C4 VBUF M5M6 VBUF M7M8 f1 + f1 -2f1 L4 L3 L5 L6 + + + VTUNE VAC 10-stage ring oscillator M9M11M13M15M10M12M14M16 VGT VGB Figure 6-8. Push-push VCO. A 250-GHz CMOS push-push VCO is demonstr ated. The VCO uses the nMOS crosscoupled topology [45], [10] shown in Figure 6-8. The resonator consists of a single-loop circular inductor and accumulation mode MOS varactors. The bi as current is injected in the middle of the inductor through a PMOS transistor, M 3 The use of a PMOS current source allows utilization of the full range of the varactor wit hout requiring tuning voltages above V DD or below zero [11]. In addition, the buffer for driving the 50load utilizes two tapered stages to lower the capacitance added to the LC tanks. The cross co upled core transistor size is 8.4 m. The varactors are formed by two 0.5 x 0.18 m 2 fingers with contacts on both sides. The inductor trace was formed using the top metal 9 (copper) layer with a thickness of ~1 m. The diameter of circular inductor is about 38 m and metal width is 2.4 m. The effective inductance ( /)(11Zimag ) is about 140 pH and quality factor ( ) is about 13. In the push-push oscillator, the cross)(/)(11 11YrealYimag 94

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coupled transistor pair generate s differential signals and elimin ates the concern for even-mode oscillation. At the virtual gr ound node, the differential fundamen tal signals are attenuated, and the 2 nd harmonic is extracted. Quarter-wavelength transmission lines provide high impedance at the 2 nd harmonic frequency. Two transmission lines and PMOS transistors are used for the symmetry. The grounded coplanar wa ve guide is used for transmi ssion line. A microstrip needs a wider ground plane. A coplanar waveguide confines fields in a relatively small area and shows stable characteristic impedance over a wide frequency range. Compared to a CPW, a grounded coplanar waveguide has an ad ditional ground plane at bottom The ground plane isolates the lossy silicon substrate and redu ces coupling to other circuits. The signal line width is 11um and gap is 3um. Simulated loss is about 1.6 dB/mm at 250GHz. The metal 1 and 2 layers are shunted together and used for the ground plane. The pad layer is used for the si gnal line. The extracted 2 nd harmonics at push-push node is radiat ed through an on-chip patch antenna. Fully differential inverters with programmable delays are used to form a ring oscillator. The ring oscillator in Figure 6-9 generates about 10 30 MHz square wa ves and turns on and off the PMOS current source of push-push VCO a nd generate amplitude modulated output. The buffer stages control the amplitude of signal from the ring oscillator A 125-GHz AM modulate signal is measured at the buffer output. The onchip 30 pF bypass capacitor is used for the ring oscillator. However, this is not suffi cient at 10 MHz. An off-chip 0.1-20 F bypass capacitors are used on the PCB. The on-chip patch antenna is formed using a pad layer and size of patch is 330 x 315 m 2 The ground plane of patch is formed using the metal 1 and 2 layers. The dielectric thickness from the ground plane to patch is about 7 m. The width of patch is 330 m. The simulated antenna efficiency is about 32 % and directivity is a bout 5 at 250 GHz. A 20 m x 40 95

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m inset is used to decrease input resistance of patch. The input resistance is 50 at 250 GHz. The bandwidth of patch is about 10 GHz. 6.6.2 Experiment Results Figure 6-10. Die microphotograph of 250-GHz AM modulated signal generator. The fabricated 250 GHz VCO with a patch ante nna is shown in Figure 6-10. The size of the circuit is 667 x 1100 m 2 The fundamental signal of VCO is measured on-wafer with an Agilent E4448A spectrum analyzer and an Agilent 11970W harmonic mixer. A 75-120 GHz Wband wave-guide probe is used to measure the VCO fundamental output. 96

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Figure 6-11. Output spectrum of the 125-GHz VCO. Figure 6-11 shows the measured spectrum of the VCO at fund amental output buffers with modulation turned off. The supply voltage is 1.6 volt and bias current is 13 mA. The conversion loss of harmonic mixer is about 40 dB and the insertion loss of probe is about 2 dB around 120 GHz. Thus, the output is estimated to be around -20 dBm. The VC O can be turned by varying bias currents about 4 GHz from 125 to 129 GHz. 97

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Figure 6-12. Output spectrum of the VC O with modulation and without modulation. Figure 6-12 shows the fundamental output of VCO with and wit hout modulation. The ring oscillator is turned on and generates square wave around 12 MHz. The carrier frequency is shifted down about 120 MHz when the modulation is on. 125-GHz amplitude modulated signals are measured at the fundamental output. Figu re 6-13 shows the measured spectrum of the 250GHz push-push VCO. The 250-GHz second harmoni c is generated by the push-push VCO and radiated through an on-chip patch antenna. The sp ectrum is measured using an Fourier transform infrared spectroscopy (FTIR). The 10 mil beam splitter and silicon bolometer are used in the FTIR measurements. Only the background noise is observed when the supply voltage of VOC was off. The second harmonic power from the antenna is about -34 dB m measured. Table 5-1 summarizes the performance of the 250 GHz VCO. 98

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Figure 6-13. Spectrum of the push-push VCO. Table 6-1. Summary of 250-GHz push-push VCO. Chip size 1100 m x 670 m Patch size 330 m x 315 m V DD 1.6 V ANT directivity 5.1 Bias current 13mA ANT efficiency 32 % Frequency 250.4 GHz Reflection coefficient 50 Tuning range 4 GHz Fundamental Power -20 dBm 2 nd harmonic power -32 dBm Technology UMC 90nm CMOS 99

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6.7 410-GHz CMOS Push-Push VCO 6.7.1 Design Considerations Two versions of 410-GHz push-push oscillators with and without the buffer for the fundamental output are fabricated in a 45-nm CMOS technology. Figur e 6-14 shows a push-push oscillator with an on-chip patch antenna. The two stage tapered buffers like the 250-GHz VCO are used in order to reduce the capacitive load in the oscillator core. The transistor size of the first buffer is about 3 m and the transistor size of the second buffer is about 12 m [37]. Figure 6-15 show the oscillator without buffers. The os cillator once again includes an on-chip patch antenna. VDDVDDPatch Antenna M1M2M3M4V1V1T.L1T.L2L1L2C1C2 VBUF T.L3T.L4M5M6 VBUF T.L6M7M8T.L5 f1 + f1 -2f1 Buffer Buffer Oscillator Core Figure 6-14. Schematic of a Push-push VCO with on-chip patch antenna and buffers for the fundamental outputs. 100

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Figure 6-15. Schematic of a Push-push VCO with on-chip patch antenna without the buffers for the fundamental outputs. To increase the operating frequency of push-push VCO, the output buffer is omitted for the second version shown in Figure 6-15. The fundamental operating frequency of VCO in Figure 615 is increased about 16 GHz. The va ractor is not used to increase the operating frequency and to reduce the loss caused by the varactors. The width of the cross-coupled transistors is about 10 m. The cross-coupled transistors need careful layout to reduce parasitic resistan ce and capacitance. Figure 6-16 shows the layout of cross-coupled transistors. The transistor M 1 is shown at the top and M 2 at the bottom in Figure 6-16. Transistor gates are contacted on bot h ends and folded into multiple fingers. 101

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Figure 6-16. Layout of cro ss-coupled transistors. The resistance of a contact is about 60 To decrease the parasitic resistance, multiple contacts on the transistor gates are required. Each finger has 2 contacts on each side and connected using metal 2. The sources are connected together using the metal 1 layer. The transistors are directly cross connected from the drain to gate using th e metal 2 and metal 3 layers. The top metal layer thickness is about 2 m and has larger fringing capacitance than the lower metal layers. The lower metal layers are used to connect the tran sistor gates. The width of each finger is about 0.6 m. Polysilicon dummy gates are also included for each finger. Figure 6-17 shows the differential circular in ductor used in the push-push oscillator. To reduce the parasitic capacitance to substrate, only the top metal layer is used. The top metal layer 102

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is about 2 m thick and about 2 m above the silicon substrate. The diameter is about 20 m and metal width is 1.6 m. The skin depth of copper with conductivity of 5.25 x 10 7 S/m at 200 GHz is about 0.155 m. The metal width is about 10 times th e skin depth. The polysilicon layer is used to form a patterned ground shield. The inductance can be increased by removing the patterned ground shield. However, the polysilicon ground shield is used to satisfy the density rules. Metal 1 and 2 layers are used to form a ground grid. The pitch is 2.5 m and width of each metal layers are about 1 m. The estimation of inductance and quality factor is important to properly set the operating frequency of the oscillator and output pow er. Ansoft HFSS is used for simulation and extraction of S-parameters. The effective inductance is about 40 pH and Q conv is about 8. This low value is caused by the skin e ffect and loss caused by the silicon substrate. Figure 6-17. Structure of circular inductor for the 410-GHz oscillator. 103

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The operating frequency of oscillator is determined by the capacitance of the cross-coupled transistor and the circular inductor. The capacitance can be estimated by (6.9) [11]. db gd gs totalCCCC 4 (6.9) where, is gate-to-source capacitance, is gate-to-drain capacitance and is drain-to body capacitance. The simulated C gsC gdC dbC gs C gd and C db are 3.8, 2.3, and 3 fF respectively, The operating frequency ( )2/(1LC f ) of the oscillator is about 205 GHz with a 40-pH inductor. The capacitances are extr acted using CADENCE simulations. The transmission line length in Figure 6-18 is about quarter wave which is about 90nm. Grounded transmission lines are used for the transmission line. Figure 6-15 show the grounded coplanar waveguide. Signal line width (W) is 6 m and gap (G) between the signal line and ground line is 4m. The simulated loss of grounded coplan ar waveguide is about 2.5 dB/mm at 400 GHz. Figure 6-18. Grounded coplanar waveguide. 104

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Figure 6-19. On-chip patch antenna. The on-chip antenna consists of a patch, di electric and a ground plane as shown in Figure 6-19. The pad layer is used for the patc h and the dielectric thickness is about 4 m. The metal1-5 layers shunted together are used to the ground plan e to reduce ohmic re sistance and satisfy design rules. When a detector is fabricated in the same chip, the shielding of the antenna is important. As mentioned, the ground plane shield s the antenna from the lossy silicon substrate and reduces the signal coupling with near by circuits. The patch size is 200 x 200 m 2 Figure 620 shows the resonant frequencie s of the on-chip patch antennas with a square patch size. The resonant frequency is decreased from 320 to 430 GHz when the patch si ze creases from 240 to 180 m in the TI 45-nm process. 105

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Figure 6-20. Resonant frequencie s of the on-chip patch antennas. Figure 6-21. Efficiency with various dielectric thicknesses. 106

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Figure 6-22. Directivity and efficiency for varying sizes of patch. Figure 6-23. On-chip patch antenna radiation pattern. Y X Z 107

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The antenna efficiency versus the dielectric thickn esses is plotted in Figu re 6-21. To increase the dielectric layer thickness, the pa d layer is used for the patch in stead of the top metal layer. Figure 6-22 shows the di rectivity and efficiency for vary ing patch sizes. The smaller patch antenna has better efficiency at a given dielectric thickness. Fi gure 6-23 shows the patch antenna radiation pattern. The directivity is the hi ghest in Z-direction a nd directivity is 5. 6 8 10 12 14 16 -40 -35 -30 -25 -20 -15 -10 Inductor Q Output Power (dBm) Figure 6-24. 2 nd harmonic power at the push-push node (Q bypass = 0.2, R sub = 200 ). Figure 6-24 and 6-25 shows the simulated 2 nd harmonic power at the push-push node using cadence. The output power increases from -38 to -14 dBm when inductor Q ind (L/R) is increased from 6 to 15. Q bypass is 0.2 and the substrate resistance, R sub of transistor is 200 If the Q ind is 4 then the push-push oscillator no longer oscillat es. Figure 6-21 shows the 2 nd harmonic power with various subs trate resistance with Q ind of 6 and Q bypass of 0.2. When the R sub is 200, 108

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the output power is about -38 dBm. If R sub can be very small value or large value then the power consumption at the substrate decreases and the 2 nd harmonic power increases. The quality factor of circular inductor has the most dominant effects on the the 2 nd harmonic output power. Figure 6-24 also suggests that the output power can be increased up to -15 dBm by increasing the quality factor of inductor using a better backend process. 0 200 400 600 800 1000 -38 -36 -34 -32 -30 Rsub ()Output Power (dBm) Figure 6-25. 2 nd harmonic power at the push-push node (Q ind = 6, Q bypass = 0.2). 109

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6.7.2 Experiment Results GND GND VDDVBUFV1 GND GND f1 +f1 -2f1 Figure 6-26. Die microphotograph of pushpush oscillator with output buffers. Figure 6-27. Output spectrum of the 189-GHz fundamental Oscillator. 110

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GND GND VDDVDDV1 Figure 6-28. Die microphotograph of push-pus h oscillator wit hout output buffers. Figure 6-26 shows the push-push os cillator with buffers. A fundame ntal signal is measured using an OML harmonic mixer with a GGB waveguide prove. Figure 6-27 shows spectrum of the fundamental signal of the push-push oscillator A 189GHz signal has been measured. Loss of harmonic mixer according to OML is about 60 dB. The measured data are de-embedded and plotted in Figure 6-27. The chip size is 350 840 m 2 A die microphotograph of the version of the push-push oscillator is shown in Figure 6-28. Not including the buffers increa ses the output frequency. Figure 6-29 shows the spectrum of push-push oscillator measured using an FTIR. There is a 410-GHz signal and also the fundamental output is seen the figure. The 2 nd harmonic power measured with a bolometer is about -49 dBm. The low output power form the oscillator is due to the low gain of transistors at the frequency and losses of from thin metal laye rs and dielectrics, as well as the mismatch 111

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between the resonant frequencies of patch ante nna and oscillator. The output power can be improved by using a better back-end process. The chip size is 390 x 640 m 2 in Figure 6-28. The supply voltage is 1.5 volt and bi as current is about 11 mA. When the bias current is changed from 11 to 7 mA, the oscillation frequency of oscillator is decrease d from 413 to 410 GHz in Figure 6-30. Figure 6-29. Spectrum of the 410-GHz push-push oscillator measured using an FTIR. 112

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Figure 6-30. Frequency and power of push-push oscillator at varying bias currents. 1990 1995 2000 2005 2010 100 200 300 400 Frequency (GHz)Year 410GHz VCO 189GHz VCO InP Fundamental InP Push-push SiGe Fundamental SiGe Push-push CMOS Fundamental CMOS Push-push Figure 6-31. Operating frequencies of published VCO. 113

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Operating frequencies of published VCOs with years are shown in Figure 6-31. Until 2000, published papers used InP devices to implement millimeter-wave oscillators. SiGe fundamental and push-push VCOs operating at the millimeter-wave frequencies were first reported around 2000. The CMOS fundamental and push-push VCO s operating in millimeter frequencies around 2000. The 189-GHz fundamental oscillator and 410-GHz push-push oscillator are also plotted in Figure 6.31. The 410-GHz push-push VCO has th e highest operating frequency among the VCOs fabricated with 3-terminal de vices in all transi stor technologies. Table 6-2. Calculated and measured power. Measured Power -47 dBm 2 nd Harmonic Power -49 dBm Antenna loss 7 dB Mismatch loss 2 dB Calculated Push-push Pout -40 dBm Simulated Pout with inductor Q of 6 @200GHz, bypass cap Q of 1 @400GHz and Rsub of 200 -38dBm Table 6-3 compares the operating freque ncy and output power of recently published millimeter-wave and submillimeter-wave VCOs implemented in InP, SiGe, and CMOS technologies. The highest operating frequency of the VCO using InP technology is 346GHz. The highest operating frequency of SiGe VCOs reached 278GHz in 2007. 114

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Table 6-3. Comparison with recently reported VCOs in InP, SiGe, and CMOS technologies. Year Freq(GHz) Pout(dBm) Topology Technology Ref 1993 131 -8 Fundamental [48] 1995 213 -30 Fundamental [49] 1999 108 -5.6 Push-push [50] 1999 134 -10 Fundamental [51] 2000 150 -10 Fundamental [52] 2001 147 -19 Fundamental [53] 2005 215 -10 Push-push [54] 2007 346 -16 Fundamental InP [55] 2003 150 -5 Push-push [56] 2004 115 -14 Fundamental [57] 2004 100 12 Fundamental [58] 2005 190 -4.5 Push-push [59] 2007 278 -20 Push-push SiGe [60] 2005 114 -26 Push-push [13] 2005 131 -11 Push-push [36] 2006 140 -19 Fundamental [61] 2006 192 -20 Push-push [12] 2008 189 -27 Fundamental [54] 2008 410 -49 Push-push CMOS [54] Table 6-4. Summary of 410GHz push-push VCO. Chip size1 390 m x 640 m Patch size 200 m x 200 m V DD 1.5 V ANT directivity 5 Bias current 11mA ANT efficiency 22 % Frequency 410 GHz Reflection coefficient 50 Tuning range 3 GHz Fundamental Power -27 dBm 2 nd harmonic power -49 dBm Technology TI 45nm CMOS 115

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6.8 Summary A 250 GHz pushpush oscillator wi th an on-chip patch antenna fabricated using a 90-nm CMOS process is demonstrated. A ring oscillator is included for generation of 250-GHz AM signals. 125-GHz AM signals are directly m easured using a waveguide probe. A 410 GHz push push oscillator with an on-chip patch antenna fabr icated using low leakage transistors of a 45-nm CMOS process with 6 metal layers is demonstrated. The 410-GHz operating frequency is the highest among the circuits fabricated using tr ansistors including those fabricated in III-V technologies. 116

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CHAPTER 7 SUMMARY AND FUTURE WORK 7.1 Summary Use of on-chip antennas at high frequencies ma kes systems compact and lower cost as well as potentially improving their pe rformance. At 60GHz, communi cation using antennas over 30 meters can have lower loss than that using tran smission lines. The impact of realistic metal interference structures which can significantly m odify the characteristics of on-chip antennas, such as a power grid, local clock trees and data lines have been investigated primarily using EM simulations. In the presence of a power grid, the antenna pair |S 12 | can be traded off for improved stability of antennas characteristics and the predic tability of on-chip antenna characteristics. Microstrip patch antennas are popular for their low profile, for the ease with which they can be configured to specialized geometries and their low cost when produced in large quantities. The radiation mechan ism of patch antenna is discu ssed, and the simple design equations for the patch antenna size and input impedance are pr esented. The impact of bond wires on on-chip patch antenna pe rformance is presented. The bond wires at the distance of 50 m from a patch antenna change radiation direction by ~13 and decrease the input resistance by about 4 A 182-GHz Schottky diode detector with an AM modulator is demonstrated in a foundry 130-nm CMOS technology. The detector consists of a 180-GHz RF matching circuit, a Schottky diode, a low pass filter, and an amplifier. The diode formed with 16 of 0.32 m x 0.32 m cells connected in parallel. This detector proves the po ssibility to build a detector operating near the top end of millimeter wave range using CMOS. The output power of oscillator may decreas e with operating frequency. The harmonics mixer loss increases with frequency. The dow n converted signal at the harmonic mixer output 117

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could be smaller than the noise level, which makes the measurement not possible. Also, probes that work at THz are not possible. Off the shelf electrical pr obes go up to 325 GHz. To overcome the difficulty of electrical measurement technique s, optical techniques are utilized. The power and spectrum can be measured using a bolometer and FTIR. A 250-GHz pushpush oscillator with an on-chip patch antenna fabricated using a 90-nm CMOS process is demonstrated. A ring oscillator included for the ge neration of 250 GHz AM signal s. A 410 GHz pushpush oscillator with an on-chip patch antenna is fabricated using the low leakage transistors of a 45-nm CMOS process with 6 metal layers. The 410-GHz operati ng frequency is the highest among the circuits fabricated in any technology incl uding the III-V technologies. Th ese suggest the possibility of CMOS THz systems. 118

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7.2 Future work 7.2.1 250-GHz Detector Measurement with a High Power Source The input power to the detector is about -70d Bm and is smaller than the sensitivity of detector and the amplitude modulate signal could not be detected. A novel Schottky barrier diode in foundry CMOS that uses a polysilicon gate ri ng for separating the Schottky and n-well contact is realized. This new Schottky barrier diode increases the cut-off fr equency by ~2 X over a conventional SBD structure [62]. By using these Schottky barrier diodes, the sensitivity can be improved and make the detection of amplitude modulate signal possible. 7.2.2 Output Power Improvement of THz VCO The output power of 410GHz oscillator is about -50 dBm. The inductor, bypass capacitor and substrate resistance affect the output power of the pushpush oscillators. The push-push oscillator output power can be improved by increasing quality factor of inductors and capacitors and optimizing the substrate resistance as well as better matching the antenna to the oscillator outpout frequency. 119

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APPENDIX FTIR MEASUREMENT PARAMETERS Advanced Resolution 0.1 cm -1 Sample Scan 512 scans Save Data from 1cm -1 to 40 cm -1 Result spectrum Transmittance Optic Beamsplitter Mylar 250m Optical Filter OPEN Aperture 3 ; 10mm Detector 1 ; Bolometer Scanner velocity 8 ; 14.864kHz Sample signal gain 4 Acquisition Wanted high frequency limit 100 cm -1 Wanted low frequency limit 0 cm -1 FT size 32k High pass filter Open Low pass filter 7; 137 Hz Ac quisition Mode Single Sided Correlation Mode No FT Phase Resolution 16 Phase interferogrampoints 55 Phase correction mode Mertz Apodization function Norton-Beer, Medium Zero filling Factor 4 Interferogram size 4470 points FT size 32k 120

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BIOGRAPHICAL SKETCH Eunyoung Seok was born in Sangju, South Korea, in 1973. He received the B. E and M.S degree in electrical and computer engineerin g from Yeungnam University, Kyongsan, South Korea in 1999, 2001 respectively. He received his Ph.D. degree in electrical and computer engineering from the University of Florida, Gainesville in 2008 and ha s been with Silicon Microwave Integrated Circuits and Syst ems (SIMICS) research group since 2003. During the summer of 2006, he interned at Te xas Instruments where he was involved in RF circuits design. His current research intere sts are in analysis and design of microwave, millimeter and THz circuits and systems in CMOS. 126