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Design of Wideband Communication Circuits

Permanent Link: http://ufdc.ufl.edu/UFE0021634/00001

Material Information

Title: Design of Wideband Communication Circuits
Physical Description: 1 online resource (154 p.)
Language: english
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2008

Subjects

Subjects / Keywords: Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The wideband wireless communication system (e.g., Ultra-Wideband (UWB)) is becoming popular for its capability to achieve high data rate wireless transmission. With the progress on CMOS technology in recent years, it could achieve comparable performances at high frequencies to other compound materials (e.g., GaAs) but with much lower cost. Therefore, implementing wideband circuits using CMOS technology has become one of the most important topics in the RF circuit design. In this study, several wideband CMOS circuits along a receiver chain were designed and tested using various novel design techniques. Low noise amplifiers (LNAs) are one of the most critical components in a receiver design. Three LNAs were designed and measured using a 90 nm CMOS technology. The LNAs adopt a modified resistive feedback topology for wideband input matching and gain-bandwidth extension. All of the LNAs were measured with chip-on-board package and electrostatic discharge (ESD) protection diodes at all the ports. Two of the LNAs were designed for the UWB application and one of the LNA was designed for the multi-band application. Tradeoffs between the noise figure (NF), bandwidth, and gain will be demonstrated in the proposed LNAs. Mixers are also of focus in this doctorial research. Several wideband passive mixers were designed and tested. At first, board level mixers using GaN devices were designed and measured. GaN devices have the property of high breakdown voltage. Therefore, they can be used in high power and high linearity applications. The transistors were modeled specially in the linear region to accurately estimate the performance of the passive mixers. Three passive mixers were fabricated using GaN HEMT transistors with different gate lengths. The results show good linearity performance. Next, two passive mixers were designed and tested using a 0.18 ?m CMOS technology. A fundamental passive mixer and a sub-harmonic passive mixer were made. The fundamental passive mixer achieves a very wide bandwidth for UWB devices. The sub-harmonic passive mixer utilizes the second harmonic of the local oscillator (LO) signal achieving a high LO-IF leakage. The chip includes a sub-harmonic mixer, a voltage controlled oscillator (VCO), and a quadrature generation circuitry. Finally, a wideband VCO and a UWB frequency synthesizer were considered and designed. The switching band VCO implemented in 0.18 ?m CMOS achieves a tuning range from 3 GHz to 5 GHz. Switching inductors and capacitors were used to change the oscillating frequencies. Next, a frequency synthesizer used for the multi-band orthogonal frequency division multiplexing (MB-OFDM) UWB system was designed. The simulated synthesizer can generate twelve bands ranging from 3 GHz to 10 GHz using the sub-harmonic mixing technique. Various spurious reduction methods were implemented to reduce the interferences caused by the spurious signals.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Thesis: Thesis (Ph.D.)--University of Florida, 2008.
Local: Adviser: Lin, Jenshan.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2008
System ID: UFE0021634:00001

Permanent Link: http://ufdc.ufl.edu/UFE0021634/00001

Material Information

Title: Design of Wideband Communication Circuits
Physical Description: 1 online resource (154 p.)
Language: english
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2008

Subjects

Subjects / Keywords: Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The wideband wireless communication system (e.g., Ultra-Wideband (UWB)) is becoming popular for its capability to achieve high data rate wireless transmission. With the progress on CMOS technology in recent years, it could achieve comparable performances at high frequencies to other compound materials (e.g., GaAs) but with much lower cost. Therefore, implementing wideband circuits using CMOS technology has become one of the most important topics in the RF circuit design. In this study, several wideband CMOS circuits along a receiver chain were designed and tested using various novel design techniques. Low noise amplifiers (LNAs) are one of the most critical components in a receiver design. Three LNAs were designed and measured using a 90 nm CMOS technology. The LNAs adopt a modified resistive feedback topology for wideband input matching and gain-bandwidth extension. All of the LNAs were measured with chip-on-board package and electrostatic discharge (ESD) protection diodes at all the ports. Two of the LNAs were designed for the UWB application and one of the LNA was designed for the multi-band application. Tradeoffs between the noise figure (NF), bandwidth, and gain will be demonstrated in the proposed LNAs. Mixers are also of focus in this doctorial research. Several wideband passive mixers were designed and tested. At first, board level mixers using GaN devices were designed and measured. GaN devices have the property of high breakdown voltage. Therefore, they can be used in high power and high linearity applications. The transistors were modeled specially in the linear region to accurately estimate the performance of the passive mixers. Three passive mixers were fabricated using GaN HEMT transistors with different gate lengths. The results show good linearity performance. Next, two passive mixers were designed and tested using a 0.18 ?m CMOS technology. A fundamental passive mixer and a sub-harmonic passive mixer were made. The fundamental passive mixer achieves a very wide bandwidth for UWB devices. The sub-harmonic passive mixer utilizes the second harmonic of the local oscillator (LO) signal achieving a high LO-IF leakage. The chip includes a sub-harmonic mixer, a voltage controlled oscillator (VCO), and a quadrature generation circuitry. Finally, a wideband VCO and a UWB frequency synthesizer were considered and designed. The switching band VCO implemented in 0.18 ?m CMOS achieves a tuning range from 3 GHz to 5 GHz. Switching inductors and capacitors were used to change the oscillating frequencies. Next, a frequency synthesizer used for the multi-band orthogonal frequency division multiplexing (MB-OFDM) UWB system was designed. The simulated synthesizer can generate twelve bands ranging from 3 GHz to 10 GHz using the sub-harmonic mixing technique. Various spurious reduction methods were implemented to reduce the interferences caused by the spurious signals.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Thesis: Thesis (Ph.D.)--University of Florida, 2008.
Local: Adviser: Lin, Jenshan.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2008
System ID: UFE0021634:00001


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DESIGN OF WIDEBAND COMMUNICATION CIRCUITS


By

TIENYU CHANG




















A DESSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2008



































O 2008 Tienyu Chang









ACKNOWLEDGMENTS

I would like to express my deepest gratitude to my advisor Dr. Jenshan Lin. He provides

me a research environment with free thinking and he lets me to explore what my interests are.

Without his support and guidance, I can hardly finish this doctorial study. I would also like to

thank my committee members, Dr. Rizwan Bashirullah, Dr. William Eisenstadt, and Dr. Fan Ren.

They gave me a lot of precious comments during the defense and proposal to make my study

more complete. I specially thank Mrs. Wenhsing Wu for her help during the first couple of years

fabrication and bond-wiring the GaN devices; and Dr. Fan Ren for his generous offering of his

lab equipment for testing and bond wiring.

For the several years that I've lived in Florida, I would like to thank all of my lab mates for

their companies and supports. Some of them are already graduated (Xiuge Yang, Yanming Xiao,

Ashok Verma, SangWon Ko, and Hyeopgoo Yeo), and some of them are still here (Lance Covert,

Mingqi Chen, Fu-Yi Han, Zhen-Ning Low, Changzhi Li, Yan Yan, Austin Chen, and Mingkai

Mu). Of course, there are some visitors from Taiwan (Ching-Ku Liao, Chih-Ming Wang, and

Jian-Ming Wu). With them, I had a great time here in Florida.

I would like to thank my parents, my brother and sister for their un-conditional

encouragement and supports. At last, in several years, my love Yu-Ping Huang has taken care of

me and supported me no matter what. This dissertation belongs to all of you.











TABLE OF CONTENTS


page

ACKNOWLEDGMENT S .............. ...............3.....


LI ST OF T ABLE S ................. ...............7................


LI ST OF FIGURE S .............. ...............8.....


AB S TRAC T ............._. .......... ..............._ 14...


CHAPTER


1 INTRODUCTION .............. ...............16....


1.1 A Brief Historical Sketch of Ultra-Wideband (UWB) Technology ................. ...............18
1.2 Brief Review on UWB Technology .............. ...............18............. ...
1.2. 1 Pul se-B ased UWB Sy stem s.......................... .................. ...................1
1.2.2 Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB.....20
1.3 Design Challenges and Scope of This Study ........._._._.......... ......_.. ........2
1.4 Outline of the Dissertation. ................ ......................... ......................24


2 PASSIVE COMPONENT S .............. ...............25....

2.1 Inductors .................. ...... .............2
2.1.1 In CMOS 0.18 Cpm Technology .............. ...............25....
2.1.1 In CMOS 90 nm Technology .............. ...............26....
2.2 Capacitors .............. ...............3 0....
2.3 Varactors ................. ...............3.. 1.............


3 DESIGN OF WIDEBAND LOW NOISE AMPLIFIERS (LNAs) .............. ....................34


3.1 Topology Survey .............. ............ ..............3
3.1.1 Bandpass Filter Input Matching .............. ...............35....
3.1.2 Distributed Amplifier ................. ................ .................. ...........36
3.1.3 Common Gate Amplifier............... ...............3
3.1.4 Resistive Feedback Amplifier ................ ..................._ ................38
3.2 Theoretical Analysi s.............. ... .. ........ ... ... .......... ...........3
3.2. 1 Basic Structure of Resistive Feedback Amplifiers ................. ......................3 9
3.2.2 R-C Feedback through a Source Follower .............. ...............41....
3.2.3 Input Gate Feedback Inductor .............. ...............45....
3.2.4 Active Inductor Load ................. ...............47........... ..
3.2.4 Noise Analysis............... .. ...............4
3.2.5 Bond Wires and ESD Diodes .............. ...............51....
3.2.6 Neutralization Capacitors .............. ...............53....












3.3 Circuit Design of Proposed LNAs .................. ...............53...___ ...
3.3.1 T SMC Digital 90 nm CMO S Technol ogy ....._.__._ ..... ... .__. .. ............5
3.3.2 ESD Diodes .............. ...............54....
3.3.3 LN A 1 .............. ...............55....
3.3.4 LNA 2 ........._.___..... ._ __ ...............57...
3.3.5 LNA 3 .............. ....... .. .......... .......5
3.4 Measurement Results of Proposed LNAs ................. ...............59........... ..
3.4.1 The Resistive Load UWB LNA (LNA 1)............... ...............60...
3.4.2 The High Gain Wideband LNA (LNA 2)............... ...............63...
3.4.3 The Active Inductor Load UWB LNA (LNA 3) ................ ............... ...._...66
3.5 Conclusions............... ..............6


4 DESIGN OF WIDEBAND PAS SIVE MIXERS ....._.................. ............... .....7

4.1 GaN Passive M ixers .............. ..... ..... ... ...........7
4. 1.1 Modeling of GaN Transistors in the Linear Region ................. ............ .........72
4. 1.2 Design of GaN Resistive Mixers ................. ...............75..............
4.1.3 Measurement Results............... ...............76
4.2 CMOS Passive Mixer .............. ... ....... ..... ..........8
4.2. 1 Discussion on CMOS Resistive Ring Mixer ................. ................ ......... .80
4.2.2 Design of CMOS Resistive Ring Mixer ................. ...............84........... ..
4.2.3 Simulation and Measurement Results .............. ...............86....
4.3 CMOS Passive Harmonic Pumped Mixer ................. ...............90...............
4.3.1 Discussions on Each Block .............. ...... ...... ..........9
4.3.2 Measurement Results of the Resistive Harmonic Mixer ................. ................. 100
4.4 Conclusions............... ..............10


5 CONSIDERATION AND DESIGN OF AN UWB FREQUENCY SYNTHESIZER. ........105


5.1 A Switching Band Voltage Controlled Oscillator (VCO) ................ ......................105
5.1.1 Design of the Switching Band VCO .............. ...............106....
5.1.2 Experimental Results ................. .............. ...............110....
5.2 Introduction to MB-OFDM UWB Frequency Synthesizers ................. ............... .....113
5.2. 1 PLL with an Ultra Fast Settling Time ................. ...............116............
5.2.2 Switching Between Multiple PLLs ................. .......... ..... ........... ......11
5.2.3 Switching Between Different Frequencies Using Mixers ................ ................12 1
5.3 The Proposed OFDM UWB Frequency Synthesizers .............. ........... ............12
5.3.1 Effect of Spurious Signals in Frequency Synthesizers on BER performance.......122
5.3.2 Scheme of Frequency Generation .............. ...............125....
5.3.3 Block Diagram of the Frequency Synthesizer ........................_. ................127
5.4 Spurious Signals from the Frequency Synthesizers ......_.._............... ................1 28
5.4. 1 Spurious Signals from Mixers ........._._.._.......... ...............128.
5.4.2 Subharmonic Mixers .............. .. ...............129...
5.4.3 Filtering Out the Spurious Signals .............. ...............131....
5.4.4 Square Wave Harmonic Reduction ............... .... ...............136
5.4.5 Implementation of a Harmonic Reduction Circuit ......____ ..... .....__..........139
5.5 Schematics and Simulation Results ................ .............143............ ..













5.6 Conclusions............... ..............14


6 SUMMARY AND FUTURE WORKS .............. ...............146....


6. 1 Summary ................. ...............146................
6.2 Future Works .............. ...............147....


REFERENCES .............. ...............149....



BIOGRAPHICAL SKETCH ................. ...............154......... ......










LIST OF TABLES


Table page

1-1 Various data rates of the MB-OFDM UWB system ................. ................. ..........22

3-1 Measured performance compared with prior published works............... ..................7

4-1 Summary of the GaN resistive mixers ................. ...............79........... ..

4-2 Summary of the III-V resistive mixers from existing publications ................. ................80

4-3 Summarize of the fundamental passive mixer and the subharmonic passive mixer........104

5-1 Performance summary of the band switching VCO ........._..._.._ ....._._. ...............1 13

5-2 Center frequencies plan for OFDM UWB ................. ...............114........... ..

5-3 Operating distances for OFDM UWB system with different channel conditions and
date rate ................. ...............115................

5-4 Relation of LO frequencies of different bands ................. ...............126.............











LIST OF FIGURES


Figure page

1-1 WPAN technologies with different usable range and data rate. ............. ....................17

1-2 FCC regulation of UWB spectral mask for indoor communication systems.. ................... 19

1-3 UWB pulse waveforms ................. ...............20................

1-4 Spectrum utilizing plan for the MB-OFDM UWB system .................... ...............2

1-5 Scope diagram of this doctorial research ................. ...............23........... ..

2-1 Cross section diagram of a TSMC 1P6M 0. 18 Clm mixed-mode CMOS process. ............26

2-2 Physical diagram of a differential inductors in HFSS. ............. ...............27.....

2-3 Model used for differential inductors. ............. ...............27.....

2-4 Fitting results of a differential inductor in 0. 18 Clm CMOS .............. .....................2

2-5 Side-view of a multi-layered inductor in a 90 nm CMOS technology. ............. ................28

2-6 HFSS diagrams of a stacked differential inductor in a 90 nm CMOS technology with
w=6 Clm, r=130 Clm, and s=2 Clm.HFSS diagram of a stacked differential inductor in
a 90 nm CMOS technology............... ...............2

2-7 Simul ati on re sults of a 2 nH different al inductor in a 90 nm CMO S technol ogy.. ..........29

2-8 MIM capacitor's graphs. ................ ...................... ......... ..................30

2-9 Top views of an interdigital capacitor. ............. ...............3......1

2-10 Cross section of an A-MOS varactor ................. ...............32........... ..

2-11 Simulated capacitance values versus biasing voltages of an A-MOS varactor. ................32

2-12 Cross-section view of an I-MOS varactor. ............. ...............33.....

2-13 Simulated capacitance values versus bi asing voltages of an I-MO S varactor. ..................3 3

3-1 Results of an input matching wideband LNA from Bevilacqua, etc. ............. .................35

3-2 Results of the distributed LNA. ................ ...............36...............

3-3 Results of the common gate LNA ................. ...............37........... ..

3-4 Results of the resistive feedback LNA ................. ...............39........... ..











3-5 Basic structure of a resistive feedback amplifier. .............. ...............40....

3-6 Schematic of a resistive feedback amplifier feeding back through a source follower.......41

3-7 Small signal equivalent model of the circuit in Figure 3-6 ................. ............ .........42

3-8 Simulation results of the effects of load capacitance CL On input impedance for a
resistive feedback amplifier. .............. ...............43....

3-9 Simulation results of the effects of Cr on input impedance for a resistive feedback
am plifier. .............. ...............44....

3-10 Schematic of a resistive feedback amplifier feeding back with a peaking inductor
inside the feedback loop............... ...............46..

3-11 Traj ectories of pole locations with increasing value of gate inductor in resistive
feedback amplifier. ............. ...............47.....

3-12 Simulation results of the voltage gain versus frequency using equation (3-7). .................48

3-13 An active inductor load's graphs .............. ...............48....

3-14 Frequency response of magnitude of input impedance. ........ ................. ...............49

3-15 Equivalent model of wideband LNA' s input stage with package and ESD diodes
added. .............. ...............51....

3-16 Smith Chart of S11 simulation results from DC to 15 GHz ....._____ ... ... ...._ _...........52

3-17 Layout of ESD diodes ................. ...............54........... ...

3-18 Schematic of LNA 1 (biasing circuits not shown) ................. ...............55........... .

3-19 Schematic of LNA 2 (biasing circuits not shown) ................. ...............57........... .

3-20 Schematic of LNA 3 (biasing circuits not shown) ................. ...............59........... .

3-21 Chip photo of LNAl (area=0.58mm x 0.22mm with pad)............__.. ......_ .........60

3 -22 Measurement (solid line) and simulation (dashed line) results of voltage gain for
LN A l. ............. ...............61....

3-23 Measurement (solid line) and simulation (dashed line) results of S11 for LNAl. .............61

3 -24 Measurement results of S22 and S12 for LNAl ................. ...............62...........

3-25 Measurement (solid line) and simulation (dashed line) results of NF for LNAl..............62

3-26 Measured linearity results for LNAl............... ...............63....











3-27 Chip photo of LNA2 (area=0.56mm x 0.42mm with pad). ........... _.. ......_..........64

3-28 Measurement (solid line) and simulation (dashed line) results of voltage gain for
LN A 2. ............. ...............64.....

3-29 Measurement (solid line) and simulation (dashed line) results of S11 for LNA2. ............65

3-30 Measurement results of S22 and S12 for LNA2 ................. ...............65........... .

3-31 Measurement (solid line) and simulation (dashed line) results ofNF for LNA2 .............66

3-32 Measured linearity results for LNA2 .............. ...............66....

3-33 Chip photo of the LNA 3 (area=0.3 8mm x 0.36mm with pad). ................ ................67

3-34 Measurement (dotted line) and simulation (dashed line) results of voltage gain for
LNA 3 ......... ................ ......................... .................. ............67

3-35 Measurement (dotted line) and simulation (dashed line) results of S11 for LNA3......_....68

3-36 Measured results of S12 and S22 for LNA3 ................ ................... ...............68

3-37 Measurement (dots) and simulation (dashed line) results of NF for LNA3. .................. ....69

3-38 Measured linearity results for LNA3 ................ ...................... ..................69

4-1 Die photo of one of the GaN HEMT devices with a device area of 200 Cpm x 1 Cpm......... 72

4-2 Equivalent circuit model used for GaN HEMT devices. ............. ........ .............7

4-3 Modeled Rds VeTSus gate bias on GaN devices with different gate lengths. ......................74

4-4 Measured and simulated conversion loss versus LO power for GaN devices with
different gate lengths............... ...............75

4-5 Schematic of the single-FET resistive mixer. ................ ............... ......... ...._..76

4-6 Photo of the GaN mixer board ................. ...............77........... ..

4-7 Measured conversion loss versus RF frequency. .............. ...............78....

4-8 Measured conversion loss versus RF power. .............. ...............78....

4-9 Two-tone IIP3 measurement result of the GaN resistive mixers ................. ................ .79

4-10 Schematics of the resistive mixer. ................ ...............81...............

4-11 Conversion loss versus frequency of CMOS resistive mixers with different gate
lengths. .............. ...............8 2....











4-12 Schematic of the wideband resistive ring mixer ................. ...............84..............

4-13 Chip photo of the fabricated mixer (chip size including the pads: 0.95 mm x 0.65
m m ). .............. ...............85....

4-14 Measurement and simulation results of conversion loss versus RF frequency with
fixed IF frequency 500 MHz............... ...............86..

4-15 Input PldB and IIP3 versus RF frequency. ............. ...............88..___ .

4-16 Measurement results of conversion loss versus LO power. The measurements were
conducted for ten RF frequencies from 1 GHz to 10 GHz. ............. .....................8

4-17 Measurement results of the RF return loss from 100 MHz to 12 GHz. ...........................89

4-18 Measurement results of the NF of the wideband passive mixer. ................. ................. 89

4-19 Systematic blocks of the subharmonic mixer with an integrated VCO.................... .........91

4-20 A 5 GHz VCO' s diagrams. ............. ...............92.....

4-21 Schematic of a current mode divide-by-2 circuit. ....._____ .... ... .__ ..........__.....9

4-22 Simulation results of the divider input and output. ....._____ .... ... .__ ...........__....9

4-23 Variation of channel resistance. ..........._ ..... ..__ ...............94..

4-24 Variation in conductance .............. ...............95....

4-25 Schematic of a resistive harmonic double balanced mixer .................... ...............9

4-26 Transient simulation of input and output. .....__.......____ ............ ................96

4-27 Output spectrums of the subharmonic mixer ................. ...............98 ......... ..

4-28 Different RF input biasing levels with differential LO signals............... ................9

4-29 Simulation results of a subharmonic passive mixer with different RF bias conditions.....99

4-30 Die photo with an area of 0.85mm x 0.7mm. ....._ .....___ ....... .._ ........0

4-3 1 Effects of RF bias on the conversion loss of the mixer. ........... ..... ._ ..............101

4-32 Measurement and simulation results of conversion gain of the mixer. .........................101

4-33 Measured LO leakage to the IF and RF ports with varying LO frequency. ....................102

4-34 Measured PldB, IIP2, and IIP3 of the passive subharmonic mixer. ............. ..... .........._103











5-1 Schematic of the switching band VCO ................. ...............107........... ..

5-2 Schematic of resonant tank. ........................... ........109

5-3 Die photo of the switching band VCO ................. ...............110.............

5-4 Measured conversion loss versus offset frequency ................. ............................111

5-5 The tuning capability of the switching band VCO. ................ ...........................1 12

5-6 Frequency plan chart of the OFDM UWB ................. ...............114.............

5-7 Frequency hopping diagram between the different bands. ................ ......................116

5-8 Block diagram of an integral-N frequency synthesizer. ................ ........................1 16

5-9 Block diagram with mathematical modeling of integral-N PLL. ................ ................11 7

5-10 Settling behaviors of a fast switching PLL ................. ...............118.............

5-11 A MB-OFDM UWB frequency synthesizer using multiple PLLs ................. ...............119

5-12 A MB-OFDM UWB frequency synthesizer using two swapping PLLs. ................... ......120

5-13 Two implementation of MB-OFDM UWB frequency synthesizers ............... .... ..........._121

5-14 Spurious signals of a frequency synthesizer. ........................... ........122

5-15 Simulation diagram of effect on BER due to spurious signals in a frequency
synthesizer. ........... __. .... ...............123...

5-16 Simulation result of BER with various spurious signal levels. ...........__..................124

5-17 Testing environment of the spurious signal test. ..........__...... .........__........125

5-18 Scheme of the frequency generation for a MB-OFDM UWB frequency synthesizer.....127

5-19 Block diagram of the MB-OFDM UWB frequency generator. ................. ................ 128

5-20 Spurious signals from a mixer. ............. ...............129....

5-21 Load of a subharmonic mixer. ............. .....................130

5-22 Single-side-band mixers with imbalanced inputs. ............. ...............132....

5-23 Signal isolation of SSB mixer due to imbalanced inputs ................. .......................133

5-24 Filter of the outputs of a SSB mixer. ............. ...............133................

5-25 A polyphase filter's diagrams. ......... .................. ................ ...............134











5-26 Simulation result of a three-stage polyphase filter. ............. .....................135

5-27 Polyphase filter with a single-side-band mixer ................. ...............136........... ..

5-28 Simulation results show the effect of a polyphase filter ................. .......................136

5-29 Harmonics of a square wave. .............. ...............137....

5-30 Effect of square wave harmonics on SSB mixers ......... ................. ........._.._.. ..13

5-31 Square waves with different 450 phase differences and the resulting waveform after
summation. ........._.._.. ...._... ...............138....

5-32 Using ring oscillator to generate multiphase signals. ............. ...............140....

5-33 Use a divider to generate quadrature signals .............. ...............140....

5-34 Cascade dividers for 450 phase difference. .............. ...............141....

5-35 The phase detection circuitry. .............. ...............142....

5-36 Phase detection circuit after divide-by-2 blocks ................. ........._._. ...._... ....14

5-37 Schematic of the MB-OFDM UWB frequency synthesizer. ................ ............... .....143

5-38 Simulation results showing the transition time switching from one band to the other....144

5-39 Simulation results showing the spectrum of the signal before the transition, and the
spectrum of the signal after the transition ................. ...............145........... ..









Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

DESIGN OF WIDEBAND COMMUNICATION CIRCUITS

By

Tienyu Chang

May 2008

Chair: Jenshan Lin
Major: Electrical and Computer Engineering

The wideband wireless communication system (e.g. Ultra-Wideband (UWB)) is becoming

popular for its capability to achieve high data rate wireless transmission. With the progress on

CMOS technology in recent years, it could achieve comparable performances at high frequencies

to other compound materials (e.g. GaAs) but with much lower cost. Therefore, implementing

wideband circuits using CMOS technology has become one of the most important topics in the

RF circuit design.

In this study, several wideband CMOS circuits along a receiver chain were designed and

tested using various novel design techniques. Low noise amplifiers (LNAs) are one of the most

critical components in a receiver design. Three LNAs were designed and measured using a 90

nm CMOS technology. The LNAs adopt a modified resistive feedback topology for wideband

input matching and gain-bandwidth extension. All of the LNAs were measured with chip-on-

board package and electrostatic discharge (ESD) protection diodes at all the ports. Two of the

LNAs were designed for the UWB application and one of the LNA was designed for the multi-

band application. Tradeoffs between the noise figure (NF), bandwidth, and gain will be

demonstrated in the proposed LNAs.









Mixers are also of focus in this doctorial research. Several wideband passive mixers were

designed and tested. At first, board level mixers using GaN devices were designed and measured.

GaN devices have the property of high breakdown voltage. Therefore, they can be used in high

power and high linearity applications. The transistors were modeled specially in the linear region

to accurately estimate the performance of the passive mixers. Three passive mixers were

fabricated using GaN HEMT transistors with different gate lengths. The results show good

linearity performance.

Next, two passive mixers were designed and tested using a 0. 18 Cpm CMOS technology. A

fundamental passive mixer and a sub-harmonic passive mixer were made. The fundamental

passive mixer achieves a very wide bandwidth for UWB devices. The sub-harmonic passive

mixer utilizes the second harmonic of the local oscillator (LO) signal achieving a high LO-IF

leakage. The chip includes a sub-harmonic mixer, a voltage controlled oscillator (VCO), and a

quadrature generation circuitry.

Finally, a wideband VCO and a UWB frequency synthesizer were considered and designed.

The switching band VCO implemented in 0.18 Cpm CMOS achieves a tuning range from 3 GHz

to 5 GHz. Switching inductors and capacitors were used to change the oscillating frequencies.

Next, a frequency synthesizer used for the multi-band orthogonal frequency division

multiplexing (MB-OFDM) UWB system was designed. The simulated synthesizer can generate

twelve bands ranging from 3 GHz to 10 GHz using the sub-harmonic mixing technique. Various

spurious reduction methods were implemented to reduce the interference caused by the spurious

signals.









CHAPTER 1
INTTRODUCTION

Wireless communication has already become part of our life in the 21st century. It started

from the cell phones in the late 20th century. At the time, only the voice data is transmitted

wirelessly through cell phones. Now people are trying to get every kind of digital data, from a

text message, to a voice clip, and even to a movie with a high resolution HDTV format, to be

transmitted through the air,

Because the differences in the natures of the signals transmitting, several standards have to

be set up for each special needs. One of which is for the Wireless Personal Area Network

(WPAN). It focuses on the development of short distance wireless networks. These networks

address wireless networking of portable and mobile computing devices such as PCs, PDAs,

peripherals, cell phones and consumer electronics. Depending on different requirements on the

transmission speed and operating range, standards that could be chosen from are list in Figure 1-

1. While the operating range needs to be high, we have standard IEEE Wireless Local Area

Network (WLAN) 802.11la/b/g/n (e.g. WiFi) working for us. While the data rate and operating

range is lower, but ultra-low power is needed to extend the battery life time, Bluetooth is at the

help. As for extremely high data rate transmissions of hundreds of mega bytes per second, Ultra-

Wideband (UWB) comes into play.

Because of the uniqueness in the extreme high data rate transmission comparing to other

communication systems, the transceiver design of the UWB systems is very different with the

rest of narrow band based communication systems and it posts a lot of interests on the design of

UWB circuits. Therefore, wideband wireless (especially UWB) communicating systems will be

the main focus in this dissertation among all the wireless communications.












1000 UWB
short 480Mbps @ 2m
Distance 200Mbps @ 4m
Fast download

100o 110Mbps @ 10m
UW B 802. 110r promises
v Room-range 100Mbps @ 100m
High-definition
F Qu.ality of service. 0.1lli
10 streaming
Data Networking


Bluetooth

1 10 100
Range (m) Source: Texas Instruments

Figure 1-1. WPAN technologies with different usable range and data rate.



The goal of an UWB system is to provide a short range but high data rate wireless

transmission. The first application of UWB technology is to replace the cables that connected

between machines in the offices or home. Cables are always bothering people for their easily get

tangled up. However, UWB is not just a cable replacement technology. With the help of UWB

technology, all of them could be connected together wirelessly. With the connectivity, we have

the ability to control all the equipment at the same time and make them working with each other.

UWB could change the way we use our electronic products. In the age of wireless

communication and interconnectivity, the UWB communication system will be integrated into

PCs. Mobile phones and handheld devices, digital cameras and camcorders as well as all many

of the consumer electronics and home entertainment systems. Using the UWB technology, they

will be able to share multimedia content with very large amount of data.









1.1 A Brief Historical Sketch of UWB Technology

It was started at Feb 14, 2002 when Federal Communications Commission (FCC) allocated

7500 MHz of spectrum for unlicensed use for UWB devices in the 3.1 to 10.6 GHz frequency

band [2]. Prior to January 2003, the IEEE conducted study groups to investigate the possibility of

pursuing a standard based upon the new spectrum. The IEEE 802 committees setup a new

802. 15.3a committee put out a call for proposals to develop WPANs. Because of the large

number of proposals makes the selection process slow.

After couple of meetings and discussions, two proposals are left to be decided. One of

which is based on Multiband OFDM technology and the other is based on direct sequence

technology. Because the fundamental technologies of the two standards are quite different, the

supporters on each side could not set a Einal conclusion. Furthermore, because UWB needs to be

operated over extremely short range, it is particularly vulnerable to interference. As a result, the

process became jammed for years.

Finally, the OFDM supporters elected to continue the work on standardization outside of

the IEEE 802. 15.3a task group. This outside group gradually formalized their relationship and

started an organization called "Multiband OFDM Alliance" (MBOA). Eventually this group

became known as the WiMedia Alliance. As a result, technical specification development and

certification and interoperability activities are unified in the WiMedia Alliance. On January 2006,

after three years of a j ammed process in IEEE 802. 15.3a, supporters of both proposals supported

the shut down of the IEEE 802. 15.3 a task group without conclusion.

1.2 Brief Review on UWB Technology

The power spectral emission mask of the UWB systems by FCC is illustrated in Figure 1-2.

The regulation allows spectrum sharing with low emission limit (-41.3 dBm/MHz Equivalent

Isotropically Radiated Power (EIRP)) where the transmitted signal doesn't cause harmful











interference to others. An UWB system is defined as any devices that emits signals with a

fractional bandwidth more than 0.2 or a bandwidth of at least 500 MHz at all time of


transmissions. There are two popular standards implementing UWB signals, one is to generate a

short pulse with wide bandwidth, and the other one is to use Multi-band Orthogonal Frequency

Division Multiplexing (MB-OFDM).


-40-

S-45



E I 1 .10 10.6
1.99







S-70
SGPS
Band
0.96 1.60
1 5 10 20 30 40
Frequency in GHz


Figure 1-2. FCC regulation of UWB spectral mask for indoor communication systems.



1.2.1 Pulse-Based UWB Systems

The earliest radio implemented in the late 19th century and 20th century was the pulse-

based impulse radio. Spark gaps and arc discharges between carbon electrodes were the principal

mechanisms to produce radio signals in the early 20th century.


The pulse-based UWB signal and its spectrmm are shown in Figure 1-3. An extremely short

pulse of few nano-seconds has its spectrmm crossed over very wideband. The spectrmm width

could be controlled by transmitting pulses with different pulse durations. The signal could be











modulated using several different ways including pulse-position modulation (PPM), pulse-


amplitude modulation (PAM), on-off keying (OOK), and binary phase-shift keying (BPSK). The

whole UWB spectrum could be also divided into several groups as a multiband system to reduce

interference using methods similar to frequency hopping radio.

The main advantage of pulse-based UWB system is that the transmitter has a very simple


design. Its disadvantages are that it is difficult to collect significant multi-path energy using

single RF chain; and the system is very sensitive to group delay variations introduced by analog

front-end components.


1 0


-10
0.5

~5, -20


-30


-0.5 -40
-10 -5 0 5 10 0 2 4 6 8 10
Time (ns) Frequency (GHz)
(a) (b)


Figure 1-3. UWB pulse waveforms in (a) time domain, and in (b) frequency domain.



1.2.2 Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB


Band Group #1 Band Group #2 Band Group #3 Band Group #4 Balnd G~roup #5~
Band Band Band iBand Band Band Band Band Band iBand Band Band iBanld Band




3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 "10296
MHz MVHz MHz MHz MVHz MHz MHz MUHz MIHz MHz MHz2 MHz MHz MUHz



Figure 1-4. Spectrum utilizing plan for the MB-OFDM UWB system.









The standard MB-OFDM UWB utilizes all or part of the spectrum between 3.1-10.6 GHz

and supports data rates of up to 480 Mb/s. As shown in Figure 1-4, the whole UWB spectrum is

divided into 14 bands, each with a bandwidth of 528 MHz. The first 12 bands are then grouped

into 4 band groups consisting of 3 bands, and the last two bands are grouped into a fifth band

group. This multi-band technique could be used to separate the application of UWB systems to

avoid interference. The well known OFDM technique is implemented on this UWB system. A

total of 110 sub-carriers (100 data carriers and 10 guard carriers) are used per band. In addition,

12 pilot subcarriers allow for coherent detection. Frequency-domain spreading, time-domain

spreading, and forward error correction (FEC) coding are provided for optimum performance

under a variety of channel conditions.

The transmitting data rate is scalable from 55 MB/s to 480 MB/s. In realistic multi-path

environments, 1 10 Mb/s of data transmission could be operated within 10 meters in distance; 200

Mb/s could be operated within 4 meters in distance; and 480 Mb/s could be operated within 2

meters. Table 1-1 shows operating modes with different transmitting data rates of the MB-

OFDM UWB system. The data rate could be calculated from FsymNIBP6s/6, where Fsym IS the

symbol rate which is 3.2 Msym/s for the system.

This MB-OFDM UWB standard is getting more and more popular compared to the

previous pulse-based UWB system. Therefore, MB-OFDM UWB system will be the research

topic in this PhD study. There are many good introductory papers, such as [4], [5], and [6],

describing the channel and the hardware of a MB-OFDM UWB system.

1.3 Design Challenges and Scope of This Study

The transceiver of a wideband communication system is very different from that of the

conventional narrow band systems. First of all, the design of wideband RF blocks is harder than

narrow band blocks, such as amplifier. Electronic theory tells us the gain-bandwidth product is










about constant. For circuits with higher bandwidth, the gain would be smaller than narrow band

ones. Therefore, multiple stages might have to cascade to boost up the gain so that the power

consumption would be higher. Performance of low cost CMOS technology is not fast enough to

have sufficient gain in the higher gigahertz region. Cost always plays the dominant role in which

technology will survive. In order to operate at that high frequency, usually huge power

consumption is needed and a lot of inductor peaking is necessary, which makes the chip size

bigger and the cost of fabrication higher. Because of this reason, most attempted commercial

UWB products are still focused on Mode 1, which covers the part of the UWB frequency

bandwidth, with frequency range from about 3 to 5 GHz.




Table 1-1. Various data rates of the MB-OFDM UWB system.

DataRateCoding Coded Bits, /Info Bits /
(M/) Modulation Rate FDS TDS 6 OFDM Symbol 6 OFDM Symbol
(R) (ACBPG5 [ Gr. :I
53,3 O~PSK 1/3 YES YES 300 100
80 O~PSK 1/2 YES YES 300 150
106,7 OPSK 1/3 NO YES 600 2DD
160 OIPSK 1/2 NO YES 600 300
200 Q~PSK 5/8 NO YES 600 37~5
320 DCM 1/2 NO NO 1 200 600
400 DCMv 5/B NO NO 1 200 750
480 DCM 3/4 NO NO 1200 900


Second, because of the property in the wide frequency bandwidth, the interference is more

serious where the spurious tones fall inside the signal spectrum. The regulation from FCC states

that the power density is small compared to other narrowband systems, which means there will

be strong out-of-band blockers. Also, the UWB covers the 5 GHz band which has application as

IEEE 802.11la. There will be some coexisting issues that have to be dealt with. Some techniques

are used to overcome the interference problem such as notching out certain band as in [7].










Third, the fast frequency hopping is difficult to deal with. In the standard, 9 ns transition

time is required switching from one band to another. Traditional PLLs could not stabilize in this

short period of time. Switching between PLLs is another way. However, more area and more

power consumption are necessary. Other possibilities of frequency synthesizing techniques are

like using direct digital synthesizer (DDS). However, the capability of using CMOS to

implement DDS is still questionable.


Antenna
Chap 4
I ID


I 900haps

LNA Con rol

Chap 3







Figure 1-5. Scope diagram of this doctorial research.



For most of the papers about MB-OFDM UWB systems so far, only the first frequency

bands from about 3 GHz to 5 GHz are focused on [8]. This shortens the UWB products coming

out time since it has simpler structure compared to devices covering all the bands. However, the

challenging wideband components and system specifications are still needed to obtain for future

developments. The works in this dissertation are trying to solve some of the problems mentioned

before. First, some of the RF components, including LNAs, mixers, and VCOs, are designed to

be wideband for use in an UWB system.









1.4 Outline of the Dissertation

This dissertation describes the works on several wideband components that the author

designed. In first part of Chapter 2, discussion on some of the passive components that will be

used in the circuits is given. In the latter part, a CMOS wideband VCO is developed using

switching inductors and capacitors. Chapter 3 states about wideband LNAs. Introductory on

CMOS wideband LNA is first given, and then a new type of wideband LNA is proposed. Three

LNAs were fabricated with different bandwidth and gain. In Chapter 4, several kinds of mixers

are discussed. First, an on board passive mixer using direct band-gap device GaN was designed

using transmission lines for high linearity and high power applications. Next, a CMOS wideband

passive mixer covering UWB frequency range is proposed. At last, a CMOS subharmonic

wideband passive mixer is proposed and measured. Chapter 5 discusses about the frequency

synthesizer used in a MB-OFDM UWB system. A multi-band VCO utilizing switching

resonance tanks is introduced. The insufficiency in the tuning range of the VCO leads to the

design of a mixer-based frequency synthesizer. The synthesizer is used to generate 12 bands

ranging from 3 GHz to 10 GHz using the subharmonic mixing technique described in Chapter 4.

Chapter 6 is the conclusions and future works.









CHAPTER 2
PASSIVE COMPONENTS

On chip passive components that are often used in the RF integrated circuits include

inductors, capacitors, resistors, and varactors. At higher frequencies where the wavelength

becomes comparable to the chip size, transmission lines can be used in substitute of discrete

capacitors and inductors. In this section, inductors, capacitors, and varators will be described.

Two kinds of technologies are mainly used in this research, 0. 18 Clm CMOS and 90 nm CMOS.

Descriptions of the passive components will be subdivided based on the technology if the

structures of them are different.

2.1 Inductors

2.1.1 In CMOS 0.18 pm Technology

Figure 2-1 shows the cross section of a TSMC 1P6M 0. 18 Clm mixed-mode CMOS process

chip. Although it is from TSMC, the UMC 0.18 Clm mixed-signal CMOS process is mostly

similar to the TSMC one except minor differences in the thicknesses of dielectric layers and

metal layers. In the mixed-mode process, metal six is made extra thick of about 2 Cpm in

thickness. Usually this metal layer is used as high power trace line since it has better capability in

transferring signals with higher power density compared to other thin metal of 0.5 Cpm thick. The

IR drop would also be smaller since it has smaller resistance per unit length. Also, this metal is

usually used for on chip inductors since it has lower sheet resistance for a high-Q inductor.

The simulation of inductors is done in HFSS from Ansoft Corporation. UMC provides a

convenient template for HFSS that we could use it to get the inductance value and the Q-value.

Figure 2-2 shows the physical structure in HFSS simulation. Using HFSS, two-port S-parameters

are obtained. In order to use the inductor in time-domain simulation software such as SPICE of

Cadence Spectre, lumped model has to be created. Figure 2-3 shows the lumped equivalent









circuit of the differential inductor. This circuit is then put into Agilent ADS design system and

using it to fit the S-parameters obtained from HFSS. Figure 2-4 demonstrates one of the fitting

results of a differential inductor up to 20 GHz using the lumped equivalent model. Two curves

match pretty well.


Figure 2-1. Cross section diagram of a TSMC 1P6M 0. 18 Clm mixed-mode CMOS process.

2.1.1 In CMOS 90 nm Technology

Some of the designs in this proposal are in digital 90 nm CMOS process. For the pure

digital process, there is no thick metal layer as in 0.18 Clm for high-Q inductors. Fortunately, for

the 1P9M (one poly and nine metal layers) process that we used, there are a lot of metal layers

for us to use from. Hence, multiple layers of metal could be stacked together to form an

equivalent thick metal for inductor. As of the 0. 18um CMOS, the stacked inductor is also

designed using HF SS.























Figure 2-2. Physical diagram of a differential inductor in HFSS.


Ind1 CTwlmLE," O nd2







Body

Figure 2-3. Model used for differential inductors.


Figure 2-5 shows the side-view of a multi-layered differential inductor. For either UMC or

TSMC 1P9M digital CMOS 90 nm processes, M9 has thickness of about 8 kA meters; M8 and

M7 have thicknesses of 5 kA meters. Vias are used extensively to connect the layer from M7 to

M8 and from M8 to M9. The equivalent thickness is greatly increased so that the series

resistance of the inductors will decrease and the Q-value will increase. The trade-off of using

stacked layers of metal layers is that the parasitic capacitance of such an inductor will be larger

compared to the one using thick metal layer.











`i


1 GHz) /


/1 i




Freq (0.1 to 20.


(a)


Freq (0.1 to 20.1 GHz)








(b)


----- model
HF SS


-5

S-10-
vi -15-

-20
0 2 4 6 8 10 12 14 16 18 20 22
(d) Freq (GHz)


02 4 6
(c)


8 10 12 14 16 18 20 22
Freq (GHz)


0 2 4 6 8 10 12 14 16 18 20 22
Freq (GHz)


Figure 2-4. Fitting results of a differential inductor in 0. 18 Clm CMOS of (a) S1 1 in Smith Chart,
(b) S21 in polar diagram, (c) magnitude of S11, (d) magnitude of S21, and (e)
inductance and Q values.


Figure 2-5. Side-view of a multi-layered inductor in a 90 nm CMOS technology.


























Figure 2-6. HFSS diagrams of (a) overview, and (b) top view, of a stacked differential inductor
in a 90 nm CMOS technology with w=6 Clm, r=130 Clm, and s=2 lm.


14 15

12 j/ ; 1



Q 6 0
4 -5
2
\-10

-2 -15
0 2 4 6 8 10 12 14 16 18 20
Frequency (GHz)

Figure 2-7. Simulation results of a 2 nH differential inductor in a 90 nm CMOS technology.


Figure 2-7 shows one of the simulation results of inductance value and Q extracted from

HFSS. The simulated inductor has inner radius of 130 Cpm, turns of 4, width of 8 Cpm, and spacing

between turns of 2 pm. From the simulation, inductance value is about 2 nH, and Q is more than

10 from 5 GHz to 10 GHz. These numbers are good compared to the inductors using thick top

metal in 0. 18 Cpm CMOS process. Of course, higher Q could be obtained if the inductor area is

increased with large inner radius.



































RI~


111111V


2.2 Capacitors

Two kinds of lumped capacitors are used in this proposal. First one is the metal-insulator-

metal (MIM) capacitor. MIM capacitors have large capacitance density of about 1 fF/Cpm2 foT

0. 18 Cpm CMOS technology. Figure 2-8 illustrates the physical structure of a MIM capacitor and

the equivalent circuit it uses to model the parasitic components accompanied with the capacitor.

Since the vertical distance between the metal layers is large so that the capacitance value is small,

an extra layer of CTM is added in between M5 and M6 as shown in Figure 2-1 for 0. 18 Cpm

mixed-mode CMOS technology. Extra masks are needed if the designers want to have CTM

layer in the process.


Rtop Cmim Rbot
Top c ggy ( M, n Bottom
Ltop Lbot
CoxT


Iia5


(a) (b)
Figure 2-8. MIM capacitor's graphs of (a) a physical structure and (b) an equivalent circuit
model .



For digital CMOS 90 nm technology that we used in this study, there are no MIM

capacitors provided. Therefore, interdigital capacitors are used instead. Figure 2-9 shows the top

view of such the capacitor. Multi-fingers of thin metal traces are interdigitally placed as close as

possible. It utilizes the fringing capacitance between the sides of the metals. The minimum

lateral metal distance which is determined by the processing tolerances set in the design rules

could be much smaller than the vertical distance between the metals. In TSMC 90 nm CMOS


Rsub Csu










technology, the minimum spacing between two adj acent traces of the same metal is set to be 0. 14

Cpm, which is smaller than the vertical distance of about 0.4 pm. Therefore, lateral capacitances

have larger contribution to the total capacitance value compared to the vertical capacitances.

0 0000 0 000


0
0
0
0

0-
0~


0 000 00 000


Figure 2-9. Top views of an interdigital capacitor.



More metal layers we use in the capacitor, the higher capacitance density we can get.

Metal 2 to Metal 6 are stacked to form the interdigital capacitor in our design because these

metal layers have the same design rules so that the capacitor' s shape could be uniform. For metal

layers above metal 6, metal thickness increases so that the minimum trace width in the design

rules also increases. In this design, the capacitance density is about 1.8 fF/Cpm2, which is even

larger than the MIM capacitor in 0.18 Cpm CMOS technology. However, since interdigital

capacitors utilize lower metal which is closer to the substrate compared to MIM capacitors,

parasitic capacitances to substrate are also larger than those of MIM capacitors.

2.3 Varactors

In RF circuits, varacters are mostly used in VCO design. There are three types of varactors

that are widely implemented in modern CMOS technology: diodes, inversion-mode MOS (I-

MOS) capacitors, and accumulation-mode MOS (A-MOS) capacitors [10].
























Figure 2-10. Cross section of an A-MOS varactor.


Cross-section of an A-MOS varactor is shown in Figure 2-10. The varactor is composed by

substituting the drain and source diffusion region of a PMOS with n implant. While the gate

voltage is greater than the bulk voltage, the MOS device enters the accumulation region, where

the voltage at the interface between gate oxide and semiconductor is positive and high enough to

allow electrons to move freely. Simulated capacitance values versus biasing voltages of an A-

MOS varactor are shown in Figure 2-11. It is implemented in CMOS 0. 18 Cpm technology with

the width and length value of 50 Cpm and 0.5 pm. The model of these varactors is provided by the

foundry.

330

280


0 230

'G 180

130

80
-1.8 -1.3 -0.8 -0.3 0.2 0.7 1.2 1.7
VGB (V)

Figure 2-1 1. Simulated capacitance values versus biasing voltages of an A-MOS varactor.
























Figure 2-12. Cross-section view of an I-MOS varactor.



The other kind of varactors that we use is I-MOS varactor. While the foundry does not

provide the model for A-MOS capacitors, I-MOS capacitor is another choice with the use of just

MOS model itself. The cross-section view of an I-MOS capacitor is shown in Figure 2-12. It is

just a simple PMOS with the body connects to the highest supply voltage and drain and source

connected with each other. While the gate to body larger than the threshold voltage, the MOS

enters inversion region, where the region MOS devices operate under the saturation region.

Figure 2-13 shows simulation results using 0.18 Cpm mixed-mode CMOS technology with an I-

MOS capacitor with size of 50 Cpm times 0.5 pm.

250

210

S170

~130

U 90

50
-1.8 -1.4 -1 -0.6 -0.2 0.2 0.6 1 1.4 1.8
VCG (V)

Figure 2-13. Simulated capacitance values versus biasing voltages of an I-MOS varactor.









CHAPTER 3
DESIGN OF WIDEBAND LOW NOISE AMPLIFIERS

In this chapter, wideband LNAs are designed and implemented in a 90 nm CMOS

technology. First of all, the popular topologies on designing wideband LNAs used today are

discussed. Tradeoffs between these topologies have to be made when choosing an appropriate

one. Next, a new modified resistive feedback topology is proposed. The topology includes gate

inductors inside the feedback loop, R-C feedback networks, and neutralization capacitors.

Furthermore, since for a wideband amplifier, high-Q inductor is not necessary, active inductors

could be used for small area design. An LNA with an active inductor load will be demonstrated.

Three LNAs were designed with different specifications using the topologies proposed in

this chapter. Two of the LNAs achieve wide bandwidth up to 8-9 GHz with about 16 dB of

voltage gain, while the third LNA achieves a 23 dB gain with a bandwidth of 3 GHz. The three

LNAs were co-designed with ESD capacitances and packaging bond-wires. Theoretical analysis

along with simulation and measurement results will be presented.

3.1 Topology Survey

The challenges in designing wideband LNAs include the followings: (1) a wideband

matching to the antenna has to cover the entire operating bandwidth, which depends on the

specifications and applications; (2) the need for a low noise performance in order to improve the

sensitivity of the wideband receiver; (3) low power consumption in order to extend the battery

lifetime of a handheld device; (4) sufficient gain to reduce the noise contributed from latter

stages, e.g. mixers; (5) a small chip size to reduce the cost in manufacturing wideband receivers.

After the booming of wideband communications as described in Chapter 1, wideband

LNAs are one of the most popular topics in IC related j ournals. The design topologies of

wideband LNAs people use broadly could be generally categorized as:










(a) Bandpass filter input matching: adding a matching network at the input.


(b) Distributed amplifier: cascading multiple gain stages to extend the bandwidth.


(c) Common gate amplifier: use of a common gate input stage for 50 0Z wideband matching.


(d) Resistive Feedback: use a resistive feedback to widen matching and gain bandwidth.





RD
L,


L1 C1 Le IBUMS


L2 -,C2 Ls



(a) (b)


108 10'o 10" 10m"
Frequency [Hz] Frequency [Hz]
(c) (d)

Figure 3-1. Results of (a) schematic, (b) chip photo, (c) gain, and (d) return loss, of an input
matching wideband LNA from Bevilacqua, etc.



3.1.1 Bandpass Filter Input Matching

In 2004, Bevilacqua [1l], and [12], proposed the first CMOS ultra-wideband LNA with the

use of an input matching network. Figure 3-1 summarizes of the wideband LNA, including the










graphs of gain, schematic, photo, and return loss. In this design, an input band-pass matching

networking comprising of inductors and capacitors are added at the gate of the input transistor.

However, from the chip photo, it shows that Hyve inductors are used in this LNA, which occupies

a lot of chip area. Therefore, this kind of topology is not suitable for the low cost ultra-wideband

transceiver and is not considered in this design.


Rd set
(40 05) Ld Ld
Vd (1.2nH) (3.3 nH) (3.3 nH) (1.2 nH) Otu
Rd (70ohm) M2 M4 M6


1 Ibias I


Inplt- Rg (70 hm) 8 10 g 18)
(1 nH) Lg Lg (1 nH)
(23 nH) (2.3 nH) M7---
Rg_set--

(a) (b)










0 13 46 7 0 2 0 1



Frequency [GHz] Frequlency [G~lz]
(c) (d)

Figure 3-2. Results of (a) schematic, (b) chip photo, (c) gain, and (d) return loss, of the
distributed LNA.



3.1.2 Distributed Amplifier

Distributed amplifier is the de facto topology that microwave engineers would think of

when designing a wideband amplifier. A distributed amplifier absorbs the parasitic capacitances

of the transistors into the design and adds inductors to form the whole circuit into an equivalent










distributed transmission line. This topology usually has a very wide bandwidth and is proved to

be a very effective way to design wideband amplifiers even in the mm-wave domain.

Figure 3-2 illustrates an example in [13] of the above mentioned ultra-wideband

distributed LNA. In this design, eight inductors were added with three-stage cascoded amplifiers

to form a pseudo-transmission line. The results have shown acceptable gain and matching

performance as shown in Fig 3-2 (c) and (d). However, eight inductors shown in Fig 3-2 (b)

occupy a lot of chip area, and make it costly. Also, power consumption is usually large for

distributed amplifiers because of the multiple amplifying stages.


1.E+08 1.E+09 1.E+10 0.G' 10G~d~jz
Freqlency, 12
(c) (d)

Figure 3-3. Results of (a) schematic, (b) chip photo, (c) gain, and (d) return loss, of the common
gate LNA.










3.1.3 Common Gate Amplifier

Another technique for an input wideband 50 0Z matching is the use of common gate input

stages. In 2005, Chehrazi, etc [14] realized a common gate wideband LNA on ultra-wideband

application. Schematics, photo, and the measurement results of the LNA are shown in Figure 3-3.

Since 1/gm determines the input impedance, gm is pretty much a fixed value determined by the

external termination. Because of this, the gain of the common gate stage is usually small. In

Chehrazi's work, a common gate stage and a common source stage are used in parallel to boost

up the gain. With the use of multiple amplifying branches, noise canceling technique was also

first used in a wideband LNA design. Also, in this paper, packaging effects are first added into

the design of a wideband LNA.

3.1.4 Resistive Feedback Amplifier

The last common used technique for a wideband matching is the use of resistive feedback

resistor to widen the bandwidth but with the sacrifice in gain. In [15], Kim, etc. published an

ultra-wideband LNA using such technique. Schematic, photo, and the results are shown in Figure

3-4. As shown in the figure, the chip size is much smaller compared to that of a distributed

amplifier or an input band-pass matching amplifier. This is because the less use in inductors.

However, the bandwidth is still not enough to cover the whole UWB range which is from 3 GHz

to 10 GHz.

With the introduction on the wideband LNA design given in this section, it is shown that

there is still a long way to go to make certain kinds of LNAs into production. In real productions,

realities like ESD protection circuits and packaging effect have to be carefully considered while

designing an LNA. Therefore, in this study we focus on adding more realities in designing

wideband LNAs with the considerations mentioned above. Also, the performances have to be

improved .




















I


I OUT
cl
C2
L V
r hi
v~rM,
I,, I:bill
r,


(a) (b)












S-50-- -- 1
.v S1
2
Frqeny(Gz
-(c)








32 Thoeia Analysi











Important parameters while designing wideband LNAs include gain, bandwidth, return


loss, noise figure, and linearity. In this section, the proposed LNA will be built step-by-step


mainly based on the concerns of gain flatness, matching condition and noise figure.


3.2.1 Basic Structure of Resistive Feedback Amplifiers


Basic structure of a resistive feedback amplifier is shown in Figure 3-5. The input signal is


fed into a common source transistor through a source with impedance Rs. Load resistor RL









connects supply voltage Vdd and output node, and feedback resistor Rf is connected through

output node and input of the transistor.

The input impedance could be derived as

Rf + RL R
R,= (1 ) (3-1)
1 + g,,,R ni RL



Vdd


RL



Rs Rf







Figure 3-5. Basic structure of a resistive feedback amplifier.


where gm is the transconductance of the input transistor, and the approximation is valid while

gmRL >>1, which is typical. Voltage gain, defined by output magnitude divided by one-half of

Vin which is the available input voltage magnitude under impedance matched condition, of this

feedback amplifier under impedance is given by

V,,,, RL 8n,Rf 1) RL~n,Rf R,
A = (3 -2)
1/2,,(R + RL ) (Rf +RL) R,

Approximation is valid while gmRf >>1. In order to get higher gain, Rf is desired to be

larger compared to Ri since it is a fixed value determined by the previous stage. According to

equation (3-1), in order to maintain the same value of input impedance, gmRL has to be increased

with bigger Rf.


















Cc ~Rf
T Mr Ib






Figure 3-6. Schematic of a resistive feedback amplifier feeding back through a source follower.


For an amplifier with voltage gain of 17 dB (7 in decimal), feedback resistor Rf would be

350 G2. In order to get input impedance equal to 50 02, RL has to be 233 0Z with gm equal to 50-

mA/V. These numbers will be used for comparison with another case later.

3.2.2 R-C Feedback through a Source Follower

Figure 3-6 shows the schematic of a resistive feedback amplifier feeding back through a

source follower instead of directly feedback through output node. CL and Cr represent the load

capacitance and the feedback capacitor which will be added later. The effects of these capacitors

are ignored for now. For low frequencies, the input impedance could be derived as

1 + g,, Rf 1 R
R,= ~ (3-3)
Kn,(l (+ g,, 4) g,, ,

where gmi and gm2 are the transconductances of transistor M1 and M2, TOSpectively. The

approximations stand when gmlRL >>1 and gm2Rf >>1. Voltage gain under impedance matched

condition at low frequencies can be expressed as

R
Av = -g,,,,R = (3 -4)









For having the same voltage gain as in the previous case, feedback resistor Rf has be 350 0Z

and RL has to be 140 0Z with gmi equal to 50 mA/V for 50 0Z input matching. Compared to the

traditional resistive feedback, for the same voltage gain, required value for RL is dropped by 40%.

With just a little bit increase in the output capacitance due to M2, the bandwidth, which is

determined by the RC time constant, is still larger than the previous case. Therefore, feedback

through a source follower will be used in substitute to the traditional resistive feedback in this

article.

Vout
Vin

Zin Cin S mlvin RL CL E m2Vout








Cc

Figure 3-7. Small signal equivalent model of the circuit in Figure 3-6.



Now, the capacitors are taken back into consideration to examine frequency response of

the amplifier. Figure 3-7 shows the equivalent small signal model of the circuit in Figure 3-6.

Bandwidth of the circuit needs to be considered while designing a wideband amplifier. Cin is

added to represent the input capacitance and CL is the load capacitance. Cc is the feedback

capacitor that is in parallel with the feedback resistor. It will be explained later for its use.

The input impedance of Figure 3-7 without Cr could be derived as

1 1+ gm2Rf 1 1+ gm2Rf 1+ sR,C, 35
Z, //( 35
SsC,, Em2 (1mglRr) sC, Em2 8l~mlR) 1+ s RLC,
1+ g,,R,











1 20
SCL=0fF
100 -CL=50fF
SCL=100fF
E 80 CL=150fF
\Icas CL=200fF
60 '0



20

0
20




CL=0fF t


-40 -CL=50fF
SCL=100fF
SCL=150fF
-60 CL=200fF

-80
0 5 10 15 20
Frequency (GHz)


Figure 3-8. Simulation results of the effects of load capacitance CL On input impedance for a
resistive feedback amplifier.




Equation (3-5) represents a first-order impedance with a zero and a pole with dc magnitude

of Ri (equation (3-3)) in parallel with input capacitor Cin. The zero of the impedance is located at


frequency of 1/ 2xnRL L and the pole is located at frequency of (1+gmlRL)/ 2xnRL L. The pole

frequency is about a voltage gain times higher than the zero frequency. Figure 3-8 shows

simulation results on the effects of varying load capacitances CL On input impedances. It shows

that the real part of impedance value will rise at low frequencies due to the effect of a low


frequency zero and then decrease due to the pole at higher frequencies. The higher the value of

the load capacitance, the lower the frequency input impedance rises due to further lower zero


frequencies. Similar results also occur for the imaginary part of the impedance.












I X ~~Cf=20fFf=
80 Cf20
Cf=40fF
S60

u40



20

20








E --~Cf-40fF
--60 fGf
SCf-80fF
-80
0 5 10 15 20
Frequency (GHz)

Figure 3-9. Simulation results of the effects of Cr on input impedance for a resistive feedback
amplifier.



Intuitively, the rise of the input impedance is due to the lack of gain at high frequencies

since the equation of input impedance is approximately equal to feedback resistor divided by

gain of the amplifier. At high frequencies, gain is dropped due to poles. This could be solved

either increasing high frequency gain or reducing the feedback impedance at higher frequencies.

Therefore, a capacitor Cr could be added in parallel to the feedback resistor to obtain the second

attempt reducing the feedback impedance. Input impedance with capacitor Cr is shown as


1+s RC
1, 1+g,,,,R, +si 1+ g,,, Ri (3-6)
'sC,,, g,,,(1+ g,,R, ) 1+ s R,C, 1+ sRfCf
1+ g,,R










From the equation, it is seen that an extra pole and zero pair are added to the transfer

function. The new zero is located at frequency of (1+gm2Rf)/ 2~nRrCf and the new pole is located

at frequency of 1/ 2nRrCf. For this term, it has zero frequency higher than the pole frequency, on

the contrary to the previous term. With proper value of Cc to control the locations of the new zero

and pole, the extra zero-pole pair could be used to flatten frequency response of the impedance.

Figure 3-9 shows the simulation results of using a capacitor in parallel with feedback

resistor with different values while the load capacitance is 200fF. It can be seen that the use of

feedback parallel capacitor greatly reduce the peaking in input impedances at high frequencies.

3.2.3 Input Gate Feedback Inductor

Without any further modification on circuit topology, voltage gain of a resistive feedback

amplifier is still not flat for wide bandwidth. Some methods can be used to extend the bandwidth.

One of which is put an inductor on in series with the load resistor for bandwidth extension [1 l].

Here a new way placing an inductor L, inside the feedback path at the gate of the input transistor

is proposed.

Figure 3-10 shows the schematic of such an implementation with an inductor at the gate of

the input transistor inside the feedback loop. Voltage gain could be expressed on impedance

matched condition into

-g,,,R, -g,lR, (3-7)
s1 s )1 ( s R,C, +R,C,, 2 LgC,, +R,C,,,RLC, 3 L,C,,,R,C,
>>'1 >>,2 >>,2 2 2 2

where the gate inductor adds another pole on the voltage gain transfer function. Wpt, Wp2, and wp3

are the three roots of the denominator, and f,l, fp2, and fp3 are their corresponding frequencies.

Figure 3-11 illustrates the traj ectories of increasing L, of pole locations for the proposed

amplifier. One of the roots at frequency of f,l is located on the negative real axis and the other










two roots at fp2 and fp3 are COmplex conjugate to each other. The added inductor creates a high

frequency real pole fpi as shown in the figure; on the other hand, it moves the other two poles

away from the zero frequency. Since the added pole is located at higher frequency, it does not

affect the bandwidth that much. However, pushing away the other two poles extends the

bandwidth almost by double. However, it can be seen that the traj ectories of two complex poles

curve downwards above certain inductance value. Therefore, there is an optimum value of the

inductor that is needed to use using this technique. Otherwise, the bandwidth will be shrinking

instead of increasing.



Vdd

CL JRL


Vot



Rf

M I

Rs L,






Figure 3-10. Schematic of a resistive feedback amplifier feeding back with a peaking inductor
inside the feedback loop.



Figure 3-12 shows the simulation results using equation (3-7) with various inductor values.

In this case, Cin=300 fF, CL=150 fF, gm=80 mA/V, RL=200 02, and Rs=50 02, are all typical

values while designing a wideband amplifier. It shows bandwidth of voltage gain becomes

greater with the increased value of inductors. However, peaking becomes too big eventually and










it degrades the bandwidth. Optimum value of the inductor in this simulation is about 0.4 nH.

Comparing to root traj ectory simulation in Figure 3-1 1, poles also start moving toward real axis

while inductor value higher than about 0.4 nH. The two results are consistent with each other.

Note that with the further increasing of L,, S11 might become greater than 0 dB at high

frequencies. It will cause the amplifier to oscillate and has to be considered carefully.










-5 -


-15


feedbak ampifier



3.2.4nceain Aciv Inuco Lo




Toue31 .Ta enac bndidth of thle LoaiNA, ihicraigvlu fg inductor shn ekn ehiu 1]is uesedinthe





design. Inductor shunt peaking is accomplished by series a resistor and an inductor as a load of

an amplifier. Traditionally, passive inductors are used in LNA designs. However, large area

consumption due to high-Q inductors is undesired due to the increase in cost. Active inductor

could be used in substitute to a passive inductor. Schematic and equivalent circuit of an active

inductor is shown in Figure 3-13.












20





8 14

k 12
-4 Lg=0nH
-e Lg=0.1nH
10 -*- Lg=0.2nH
-EI Lg=0.3nH
8~ -n- Lg=0.4nH
-v Lg=0.5nH
6~ -A Lg=0.6nH

0 5 10 15 20
Frequency (GHz)

Figure 3-12. Simulation results of the voltage gain versus frequency using equation (3-7).


V,



Cgs 1) mlvgs CL

ML R' T T




Zin | Zin

(a) (b)

Figure 3-13. An active inductor load's graphs of (a) schematic, and (b) equivalent circuit.



As shown in Figure 3-13 (a), an active inductor is realized by a common gate transistor

with a series resistor R, on gate. In Figure 3-13 (b), gate-source capacitance Cs, and load

capacitance CL are added in the equivalent circuit. Figure 3-14 shows frequency response of the

active inductor. The transfer function has a zero and two poles. These points determine four

operation regions shown in Figure 3-14. It could be shown that Z1=1/CsR, and P1=gm/(Cgs+CL).









Since P2 is located at a much higher frequency, it can be omitted without consideration here.

From Figure 3-14, it can be seen the circuit acts as a resistor at low frequencies in region (I), and

as an inductor in series with a resistor in (II). Finally, it behaves as a capacitor in (IV). Therefore,

this circuit could be used in region (I) and (II). Use relations of pole and zero, design constraint

gmR,>(Cgs+CL) gs, has to be satisfied for P1>Z1. As a result, an active inductor is equivalent to a

resistor with value of 1/gm in series with an inductor with value of Leq gsR,/gm. This active

inductor will be the load of the proposed LNA to have peaking at the output.




|Zin|





(II) (IV)
1/gm I


Z1 P, P2

Figure 3-14. Frequency response of magnitude of input impedance.



3.2.4 Noise Analysis

For noise analysis of MOSFET transistors, only channel thermal noises are considered in

hand calculation. They have power spectral density of 4kTrgd0 per unit frequency, where K is the

Boltzmann Coefficient, T is the absolute temperature, r is the fitting value for noise model, and

gd0 is the channel conductance while drain-to-source bias is equal to zero.

Output impedance under input impedance matched condition of Ri=Rf/gmlRL COuld be

derived as










R,, = R R, (R + R,) R, 38
at R, Rf + g,,R,R, 2
1+ g,,R,
Rf + R,

Some of the important noise sources could be derived as

FR 1 RL 2 mlRL 2 39
R,R, 2 2 gm1 2RLRs

F( ~ O 2 mlR )2 1(3-10)
R 2 2 go R, a,
1 R
( )2 8mlR )2
RfR, 2g,R R, _f 1
F ~ (3-11)
R 8mnlRL 2 gm12R 2R, g,,R,

Fr, ~22(3-12)
a2 gnm2R, gnm RL

,where FRL, Fhll, FRf, FM12 are the noise factors of four of the most important noise contributors in

this wideband feedback amplifier, and they are thermal noises generated by load resistor RL,

transistor M1, transistor M2, and feedback resistor Rf. a in equation (3-12) is equal to gm/gdo. The

total noise factor could be presented as

Fro, ~1+ FH + FM, + FM2 FRI (3-13)

In order to have some feeling about the noise performance of this circuit, an example is

given in the following. For an LNA with 15 dB (5.6) voltage gain, gmi is chosen to be 50 mA/V,

RL is 112 G2. Rf is set to be 280 0Z for input impedance matched to 50 G2. gm2 does not have to be

as large as gmi because its purpose is only to provide a feeding back path instead of gain. It is set

to be 20 mA/V. For all the transistors, r/a is assumed to be typical of 1.33. Using equations (3-

9) (3-13), the results are calculated that FRL=0.071, Fh11=0.532, FRf-0.178, and FM12=0.042.

Ftot=1.823(2.6 dB).

Noise figure of 2.6 dB is acceptable for a wideband LNA. Of course, this number will be

bigger in real LNAs because a lot of parasitic resistors are omitted in the hand calculations. From










the numbers above, it can be seen that the maj or noise contribution is the transistor that amplifies

the signal, which generates about 60% of the additional noises from the LNA.

Observing equation (3-9) (3-12), it can be seen that in order to get lower the noise figure,

gmlRL term has to be increased. It can be done in two respects: increasing gmi, which will add

more input capacitance to the amplifier for bigger input transistor, or burn more power; and

increasing RL, which will lower the output pole and also means lower bandwidth. Depending on

the design aspects on bandwidth and gain, different noise figure could be obtained through

certain trade-offs according to the design guidelines above.

3.2.5 Bond Wires and ESD Diodes

As CMOS technology's continually shrinking the thickness of gate oxide, CMOS circuits

become more and more sensitive to ESD. Since LNAs behave as an entering gate of a receiver

chip from the off chip antenna, ESD protection mechanism has to be used preventing permanent

damages on the chip.




Rf
(package)
VinK I ~ II I~-l M1
Lb L,






Figure 3-15. Equivalent model of wideband LNA's input stage with package and ESD diodes
added.



Incoming signals of LNAs are usually at very high frequencies, hence adding ESD diodes

could be detrimental to the performance of the LNA because of the extra parasitic capacitors. In










[17] and [18], ESD diodes are connected through an ESD inductor so that the capacitance due to

ESD diodes will not affect directly to the performance of LNAs. However, due to the area

concern, inductors are not preferred in the design. Especially while LNA has differential inputs,

two inductors are necessary, which will consume large amount of area. Therefore, ESD diodes

are still added directly to the inputs, and circuit techniques are used to reduce the effect of

performance reduction due to them.

From simulation, once a capacitor with value of couple of hundreds femto-Farads, which

represents capacitance of ESD diodes, added to the inputs of LNA, matching would become very

bad. Also from the simulation, if an inductor, which represents package's inductance, matching

would become bad. However, if both of the capacitor and inductor are added, it actually forms a

low pass network as shown in Figure 3-15, where Cesd and Lb are ESD capacitance and package

inductor, respectively, and helps matching to certain point.






xx + + -x Lb=1.5n


x-+- Lb=2.0nH

-o-Cesd=75fF
Cesd=1 50fF x
-x- Cesd=225fF
--Cesd=300fF B b




(a) (b)

Figure 3-16. Smith Chart of S1 simulation results from DC to 15 GHz on effects of (a) ESD
diode capacitance with Lb=1.5 nH, and (b) bond wire inductance, with Cin=250 fF.


Figure 3-16 shows the S11 simulation results from DC to 15 GHz on Smith Chart to

examine the effects of ESD capacitors and packaging inductors. Figure 3-16 (a) shows that with









the 1.5 nH packaging inductance (equivalent to 1.5mm bond wire), Cesd moves the input

impedance toward the origin. As well, in Figure 3-16 (b), Lb alSO helps matching. Therefore,

both of the ESD capacitances and packaging inductors have to be considered carefully in

simulation while designing LNAs.

3.2.6 Neutralization Capacitors

Finally, neutralization capacitors are added to cancel out the gate to drain capacitance of

input transistors through providing equivalent negative capacitor. In order to use neutralization

capacitors, differential structure has to be used. Some benefits also come with the differential

circuit, like increased immunity to common noise, de-sensitivity to ground and supply packaging

inductors, and so on, with the trade-off of larger chip area and double the power consumption.

Neutralization capacitors are connected from gate of plus input transistor to drain of the negative

input transistor, and vice versa. From simulation results, neutralization capacitors boost up the

bandwidth of the amplifier and improve input matching at high frequencies. However, extra

feedback loops make the circuit easier to oscillate. Circuit' s stability has to be examined

carefully.

3.3 Circuit Design of Proposed LNAs

Practical design considerations will be addressed in this section. A little bit on description

of the technology are delivered first. Then, ESD protection devices that are used will be

presented. In order to test the capability of the proposed structure, three wideband LNAs are

designed using the structure proposed above. LNA 1 is designed using resistive loads to achieve

UWB bandwidth. LNA 2 is designed using resistive loads also but with lower bandwidth

comparing to LNA 1. LNA 3 is designed using active inductor loads and it achieves UWB

bandwidth as well. Throughout the process in designing these LNAs, tradeoffs on the

performances could be observed.








3.3.1 TSMC Digital 90 nm CMOS Technology

Prototype wideband LNAs are fabricated using TSMC digital 90 nm CMOS technology.

Thickness of gate oxide is about 16 A~m and it supports 1.2 V supply voltage. It has minimal

65nm physical gate length for core transistors. NMOS has about 0.34 V thresh-hold voltage and

0.32V for PMOS. The process has low-k (2.9) back-end dielectrics and dual-damascene copper

for metal layers. It has six thin metal layers, with a thicker metal layer seven on top with

thickness of about 0.5 lm. For the inductors that are used in the designs, Q-value is not high

enough for using only one metal layer. Three metal layers, metal five, six, and seven, are stacked

together by dense interconnects to form an equivalent thick metal. As for passive capacitors,

because of lack of metal-insulator-metal (MIM) process, metal two to metal six are stacked to

form interdigital capacitors. Capacitance density of interdigital capacitor is about 0.39 fF/Clm2


Nwell



Nwel





(a) (b)

Figure 3-17. Layout of ESD diodes for (a) n-diode, and (b) p-diode.


3.3.2 ESD Diodes

ESD diodes themselves will survive ~2000 V human body model (HBM). Their layouts

are shown in Figure 3-17 for both of n-diode and p-diode. P-diode is connected from input to

voltage supply node and n-diode is connected from input to ground node. Length of the fingers









of diodes is 25 Clm, and 5 fingers are used in parallel for each diode. The capacitance of each

diode is about 120 fF. Therefore, the extra capacitance that is added on the inputs due to ESD

protection of LNAs is about 240 fF.

3.3.3 LNA 1

Design goals for LNA 1 are that its 3 dB bandwidth over 7 GHz; voltage gain more than

15dB (5.6); NF lower than 4 dB; and S11 smaller than -10 dB over the entire bandwidth. First

assume that the load capacitance is about 200 fF. Inverse RC time constant must be higher than

7GHz for such a capacitor. Resistor value should be smaller than 115 G2. Having some margin,

resistor value is chosen to be 100 G2. For gain of 15 dB, according to equation (3-4), gmi has to be

56 mA/V. Input matching according to equation (3-3) determines Rf to be set to 280 G2.


rdd

RL~ I RL

Mb MM3Mb
Ib Ib
Vo Ib2 b1b1 Ib2 Vo



"D F,T Rfe Rf Cr T- ~DP
Vin' 0 M M171 OuuI Vin

Dn L Cn Cn Dn




Figure 3-18. Schematic of LNA 1 (biasing circuits not shown).



Figure 3-18 shows the schematic of the proposed LNA 1. The circuit has differential inputs

and differential outputs. Simulations are done in Cadence Spectre. Cascode stage is chosen so

that the outputs are isolated from the inputs and this makes the design easier. Due to the deep-









submicron CMOS, output resistance (ro) is pretty small (couple of hundreds ohms) while the

biasing current and device size (hence gm value) are large. Due to the restriction on small value

of the output resistance, gain will not increase in proportional to the load resistor.

Transistor Mb and current source Ib2 are USed to construct an output buffer for impedance

matching to 50 0Z to the test equipment. It has voltage gain of 0.45 (-6 dB) while a 50 0Z load is

connected to the outputs. Under the situation that the LNAs are used in SOC design, output

buffers could be removed and the LNA could be directly connected to the gate of input transistor

of the following mixer. Therefore, voltage gain specified here does not include the voltage

amplitude loss due to the output buffer.

Current source Ib is added to extract part of the current from the input transistors so that the

voltage drop along RL is reduced. For supply voltage of 1.2 V, voltage drop on the resistor could

not be more than 0.3 V while cascode stages are implemented. Also, the output nodes have to

bias the output buffers. For RL having value of 200 0Z and voltage drop along it is 0.3 V, the

current flowing through it has to be less than 1.5 mA. The value of current source Ib is then

determined by this.

After tuning the values of each component, final values for RL is 200 02, Rf is 250 02, Cc is

100 fF, Cn is 60 fF, and L, is 0.5 nH. Equivalent load resistance after parallel with ro is about

12002, which is close to hand calculation result. Input device size is 120 Clm/90 nm. Current

flowing through one side of the input stages is about 8 mA, and transconductance (gmi) is about

80mA/V.

Because of feedback employed in the circuit, stability has to be examined carefully. Phase

margin of the loop gain is more than 600. K-factor is always greater than one for all frequencies.









Simulation results are shown in Figure 3-22 and it will be discussed with measurement results in

Section 3-4.

3.3.4 LNA 2

Design goals for LNA 2 are that its 3 dB bandwidth over 2.5 GHz; voltage gain more than

23 dB (14); NF lower than 2 dB; and S11 smaller than -10 dB over the entire bandwidth. Load

capacitance is also assumed to be about 200 fF. Inverse RC time constant must be higher than

3GHz for such a capacitor. Resistor value should be smaller than 322 G2. Having some margin,

resistor value is chosen to be 300 G2. For gain of 23 dB, according to equation (3-4), gmi has to be

50 mA/V. Input matching according to equation (3-3) determines Rf to be set to 700 G2.





Rb ~7Rb
Vb ObP

Vdd

RL ~ RL

Mb MM3 Mb
Ib Ib
Vo Ib2 b1 b1~ (b2 Vo
M2l M2 V

DP~ CT ~Rfr Rf Tt DP
Vin Ctb~l M M Myl 0v I Vin
Dn4 LB Cn Cn ~ L Dn




Figure 3-19. Schematic of LNA 2 (biasing circuits not shown).



Figure 3-19 shows the final schematic of the proposed LNA. It is the same circuit with

LNA 1 except a dc control circuit is used to control the value of current source Ib based on the dc









voltage of output nodes. Common mode value of these nodes are sensed using large resistors Rb,

and then feed into the negative input of an operational amplifier OP. Plus node of the OP is

biased at Vb, with value about 0.9 V. If the common mode value of output nodes is less than Vb,

Ib will be increased to let less current flowing through RL, and common mode voltage will

increase through this negative feedback mechanism; vice versa.

After tuning the values of each component, final values for RL is 600 02, Rf is 800 02, Cf is

60 fF, Cn is 80 fF, and L, is 1.2 nH. Equivalent load resistance after parallel with ro is about 300

02, which is close to hand calculation result. Input device size is 400 Clm/90 nm. Current flowing

through one side of the input stages is about 8mA, and transconductance (gmi) is about 60 mA/V.

Simulation results will be shown in Figure 3-24 along with measurement results in Section

3-4.

3.3.5 LNA 3

Design goals for the LNA 3 are that its 3 dB bandwidth over 7 GHz; voltage gain more

than 17 dB (7); NF lower than 4 dB; and S11 smaller than -10 dB over the entire bandwidth.

Figure 3-20 shows the schematic of the proposed LNA. The circuit has differential inputs

and differential outputs. Cascode stage is chosen so that the outputs are isolated from the inputs

and this makes the design easier. Current Ib is USed to determine the current flowing through the

active inductor. Transistor Mb and current source Ib2 are USed to construct an output buffer.

Under the situation that the LNAs are used in SOC design, output buffers could be removed and

the LNA could be directly connected to the gate of input transistor of the following mixer.

Neutralization capacitors Cn and feedback capacitor Cr parallel with Rf [9] are used to extend the

bandwidth and matching.

The component values are Rf of 300 02, Cc of 150 fF, and Cn of 60 fF. Transistor size for

active inductor is 8 Clm/0.18 Clm, and R, is 1.5 kGZ. gml and gmL are about 60 mA/V and 5









mA/V, respectively. Input device size is 150 Clm/90 nm. Current flowing through one side of the

input stages is about 8 mA.

Because of feedback paths employed in the circuit, stability has to be examined carefully.

Phase margin of the loop gain is more than 600. K-factor is always greater than one for all

frequencies. Simulation results are shown in Figure 3-26 and will be compared with

measurement results.


Rg gVg Rp


Vdd2
Vdd1


ML ML

Mb M21 2 Mb

Vo Ib2 2 ~Vo
Ib Ib 1
M3 M3h '

D, f fRf D,

Vin+ O I M1 M1'I O ~Vin

Dn C= Cn= Dn




Figure 3-20. Schematic of LNA 3 (biasing circuits not shown).

3.4 Measurement Results of Proposed LNAs

The three proposed wideband LNAs are fabricated in TSMC digital CMOS 90 nm

technology. Measurements are done on 1.6 mm thick FR4 dielectricc constant = 4.2) boards with

chip-on-board package. 50 0Z microstrip lines are used on the board connecting bond wires from









the chip to the SMA connectors on the edge of the board. S-parameters are measured using

Agilent E8361 PNA series network analyzer; Noise figure is measured using Agilent E4448A

PSA series spectrum analyzer; two Merrimac MFR-12457 wideband directional couplers are

used to convert single ended signals from measurement equipment to differential inputs of the

chips; vice versa at the output ports.










0.58 mm

Figure 3-21. Chip photo of LNAl (area=0.58mm x 0.22mm with pad).



3.4.1 The Resistive Load UWB LNA (LNA 1)

Voltage gain is obtained from the measurement S21 data and de-embedded the gain loss

through the output buffer. Voltage loss due to the output buffer, which is a simple source

follower has output impedance of 50 02, is about 7 dB (0.45). In real system-on-chip (SOC)

implementations, LNA outputs could be directly connected to the following stage instead of

through output buffers. Therefore, voltage gain is a more significant metric compared to power

gain, which is S21.

The die photo of this LNA is shown in Figure 3-21 with chip dimension of 0.58 mm x 0.22

mm. Active area, which excludes the area of bond pads, of this chip is about 0.066 mm2. Bond

wires are made manually with approximately 1mm in length for the RF pads. However, length

mismatches for the two input ports and two output ports are inevitable, which might degrade the

performance to certain degree.





Figure 3-22 to Figure 3-25 show measurement results of the LNA with simulation results.

Voltage gain is flat around 17 dB over wide bandwidth. The 3 dB bandwidth is from 0.2 GHz to

9 GHz. The measurement data has already subtracted the loss due to FR4 boards through

subtracting two measurement data of chip with board and board only.


012345678910
Frequency (GHz)

Figure 3-22. Measurement (solid line) and simulation (dashed line) results of voltage gain for
LNAl.





-10




0 1 24 5 68 9 1
Frqec Gz

Figure-2 3-3 Measuemen (sli lie n imuain(ahdln)rslso i o N

Fiur 3-3sosmaueetrslso elcincefcet.I hw htSri oe




thanr 3-10d vrveywdbn. Measuredn results aree bete ta simulator dsed ln rst one becus theLA1




directional couplers themselves are already matched to 50 G2. Figure 3-24 shows the measured










reverse isolation and output return loss. The reverse isolation is better than 30 dB but has higher

value between frequencies from 6 GHz to 9 GHz. Since output is constructed as a source

follower stage, the output return loss is greater than 10 dB throughout all the frequencies.




-10 S22



I -30 --

~g-40

5;-50 S12

-60
012345678910
Frequency (GHz)

Figure 3-24. Measurement results of S22 and S12 for LNAl.

12

10









012345678910
Frequency (GHz)

Figure 3-25. Measurement (solid line) and simulation (dashed line) results of NF for LNAl.



Figure 3-25 shows the NF performance. Measurement results follow the trend of

simulation ones. NF has minimum value at 3 GHz of 4.2 dB, and it rises to 7.5 dB at 7.5 GHz

due to insufficiency in the gain of the amplifier.










Note that the NF is measured with output buffer. It could be derived that the noise factor

related to output buffer is

4bypr vby rR, 4y,4,, 1
F 0. 13 (3-14)


where rbuffer, buffer are the coefficients related to noise and rbuffer Obuffer=1.33. If the noise

contribution of the output buffer is removed, the minimum NF of this LNA is actually 3.9 dB,

which is 0.4 dB improved compared to the measurement data.

Figure 3-26 shows the measured linearity results with both IIP3 and IIP2 which is

important for direct conversion receivers. Input third-order-intermodulation product (IIP3) is

about -8 dBm and IIP2 is better than 8 dBm. This LNA consumes about 20 mW of power

(excluding output buffers) with 1.2 V supply voltage.



IIP2
10



Fi0
IIP3


-0261
Frequency (GHz)

Figure 3-26. Measured linearity results for LNAl.



3.4.2 The High Gain Wideband LNA (LNA 2)

The die photo of this LNA is shown in Figure 3-27 with chip dimension of 0.56 mm x 0.42

mm. Active area, which excludes the area of bonding pads, of this chip is about 0. 134 mm2. This




















































r--- _L -plr
r
r r
r /
4*`
I*
4


LNA occupies greater chip area compared to LNAl mainly because it uses two larger inductors.


Bond wires are made manually with approximately 1.5-2 mm in length for all the RF pads.


Figure 3-28 to Figure 3-32 show the measurement results of the LNA with simulation

results. From Figure 3-28, voltage gain is about 22.5 dB over wide bandwidth and starts to fall at


2.7 GHz. The 3 dB bandwidth is from 0.2GHz to 3.2 GHz. Figure 3-29 shows the measurement


results of reflection coefficients. It shows that S11 is lower than -10 dB over very wideband.


0.56 mm

Figure 3-27. Chip photo of LNA2 (area=0.56mm x 0.42mm with pad).


28







1 20




8


0 1 2 3 4
Frequency (GHz)

Figure 3-28. Measurement (solid line) and simulation (dashed line) results of voltage gain for
LNA2 .


Figure 3-30 shows the measurement results of the output return loss and the reverse

isolation. The output return loss is better than 20 dB across the whole bandwidth and the reverse










isolation is better than 30 dB. Figure 3-31 shows the NF performance. Measurement results

follow the trend of simulation ones. NF has minimum value at 3 GHz of 1.76dB. NF from 1 GHz

to 3 GHz is below 3 dB. This low NF and high gain makes this wideband LNA a good candidate

for multi-band receivers. The noise contribution of output buffer is about 0.03 (0. 1 dB better)

according to equation (3-14). Output buffer has much smaller noise contribution compared to

LNA 1 because of the voltage gain is much bigger.







-25


-30



0 1 2 3 4
Frequency (GHz)

Figure 3-29. Measurement (solid line) and simulation (dashed line) results of S11 for LNA2.





-10





-70
0 23
Frqeny(Gz
Fiur -3.Mesueen eslt f 2 ad 1 FrLN2

Figure 03-3 hw h esrdlnaiyrslswt ohIP n I2wihi

important j fo ietcneso rcies nu hrdodritrouaio rdcIP)i
















41 ,



0 1 2 3 4
Frequency (GHz)
Figure 3-31i. Measurement (solid line) and simulation (dashed line) results of NF for LNA2.


IIP2


about -9 dBm and IIP2 is better than 6 dBm. This LNA consumes about 25 mW of power
(excluding output buffers) with a 1.2 V supply voltage.


0 0.5 1 1.5 2
Frequency (GHz)
Figure 3-32. Measured linearity results for LNA2.


2.5 3


3.4.3 The Active Inductor Load UWB LNA (LNA 3)
Die photo of this LNA 3 is shown in Figure 3-33 with chip dimension of 0.38 mm x
0.36mm. Active area, which excludes the area of bond pads, of this chip is about 0.034 mm2
Bond wires are made manually with approximately 1mm in length for the RF pads.














































20




~g12







012345678910
Frequency (GHz)

Figure 3-34. Measurement (dotted line) and simulation (dashed line) results of voltage gain for
LNA3 .


Figure 3-34 to Figure 3-38 show the measurement results of the LNA along with

simulation results. Figure 3-34 shows that the voltage gain is flat around 17 dB over wide

bandwidth. The 3 dB bandwidth is from 0.2 GHz to 9.2 GHz. The measurement data has already

subtracted the loss due to FR4 boards through subtracting two measurement data of chip with

board and board only. Figure 3-35 shows measurement results of reflection coefficients. It shows

that S11 is lower than -10 dB over very wideband. Measured results are better than simulated

ones because the directional couplers themselves are already matched to 50 G2.


0.38mm

Figure 3-33 Chip photo of the LNA 3 (area=0.3 8mm x 0.36mm with pad).













-10





-30


-40
012345678910
Frequency (GHz)

Figure 3-35. Measurement (dotted line) and simulation (dashed line) results of S11 for LNA3.



Figure 3-36 shows the measurement results of the output return loss and the reverse

isolation. The output return loss is better than 10 dB across the whole bandwidth and the reverse

isolation is better than 20 dB. Figure 3-37 shows the NF performance. Measurement results

follow the trend of simulation ones. NF has minimum value at 6.8 GHz of 3.4 dB.




-10 S22

~ 20



0/3 50



-60


0123456
Frequency (GHz)


Figure 3-36. Measured results of S12 and S22 for LNA3.


7 8 910


Figure 3-38 shows the measured linearity results with both IIP3 and IIP2 which is

important for direct conversi on receivers. Input third-order-intermodul ati on product (IIP3) i s

about -8 dBm and IIP2 is better than 8 dBm. This LNA consumes about 16 mW of power





















*~ *

*~ *
*
*


012345678910

Frequency (GHz)

Figure 3-37. Measurement (dots) and simulation (dashed line) results of NF for LNA3.

12

1 u

E`6 IIP2
~g4

0
dd -2
m I IIP3
-4


-10
0 2 4 6 8 10
Frequency (GHz)


Figure 3-38. Measured linearity results for LNA3.



3.5 Conclusions

In this study, design theory and considerations of proposed wideband LNA structure are


presented. The design employs capacitors and inductors along the feedback path, and

neutralization capacitors between input transistors. Packaging and ESD diodes are co-designed in


(excluding output buffers) with 1.2 V, 1.4 V, and 1.7 V supply voltages. However, most of the

current is flowing from 1.2 V power supply.











the simulation. Depending on the specification, gain, bandwidth, and NF are trade offs between

each other. Three LNAs were fabricated using pure digital CMOS 90 nm technology. These

LNAs achieve good performance in gain, bandwidth, and NF. Also they occupy small chip area

compared with other published LNAs. Table 3-1 summarizes the performance of the LNAs that

were fabricated in this study and their performances are compared with other published data.



Table 3-1. Measured performance compared with prior published works

CMOS BW Voltage NF(B) IP3 Package Power Vdd Area
Process (GHz) gain (dB) (dBm)/ED (W (V (m )

LNA 1 Dig. 90nm 0.2-9 17 4.2 min -8 y/y 20 (diff) 1.2 0.066
LNA 2 Dig. 90nm 0.2-3.2 22.5 1.76 min -9 y/y 25 (diff) 1.2 0.134
LNA 3 Dig. 90nm 0.2 8 17 3.4 min -9 y/y 16 (diff) 1.4 0.034

[20] 1-7 17 2.4 min -4.1 y/n 25 (diff) 1.4 0.019

[21] Dig. 90nm 0-6 17.4 2.5 min -6 n/y 9.8 1.2 0.0017
[22] 180nm 1.3-10.7 8.5 4.4 5.3 8 n/n 4.5 1.8 1
[22] 180nm 1.3-12.3 8.2 4.6 5.5 8 n/n 4.5 1.8 1
[19] RF 90nm 0.5-8.2 25 2.2 3.8 -4 n/n 42 2.7 0.025
[23] 180nm 1.2-11.9 9.7 4.5 5.1 -6.2 n/n 20 1.8 0.59
[24] Dig. 90nm 2-11 12 5.5 min -4 n/n 17 1.2 0.696
[25] 180nm 3.1-10.6 10.9 12 4.7 -10 n/n 10.57 1.5 0.665
[ll] 180nm 2.3-9.2 9.3 4 -8 -16 y/n 9 1.8 0.66
[26] 180nm 0.6-22 8.1 4.3 6.1 x n/n 52 1.3 1.35
[17] 130nm 3.1-10.6 15.3 2.04-2.98 <-5.1 y/v 9 1.2 0.87









CHAPTER 4
DESIGN OF WIDEBAND PASSIVE MIXERS

In this chapter, the behavior of resistive mixers is studied. The study begins with a board

level design of resistive mixers using Gallium Nitride (GaN) high electron mobility transistor

(HEMT) devices. Because of the inadequate modeling of GaN transistors operating in the linear

region, a linear model was developed and used in the design of resistive mixers. Three resistive

mixers were made with GaN transistors with different lengths and their results were compared

and examined.

After examining the performance of the GaN resistive mixers, focus is diverted to the

popular CMOS process for more integration of the circuit. First of all, a CMOS wideband

resistive mixer was made using the 0.18 Clm CMOS technology. The resistive mixer covers a

wide frequency range up to 11 GHz. Next, a subharmonic pumped CMOS passive mixer with an

integrated VCO and a quadrature generation circuitry is examined at the end of the chapter. The

mixer has a better performance in the isolation between the LO to the output ports comparing to

the previous wideband mixer and can be used in low leakage applications, such as the

implementation of a frequency synthesizer discussed in Chapter 5.

4.1 GaN Passive Mixers

Wide bandgap semiconductor devices using GaN and SiC materials have drawn a lot of

attention recently. These devices have high breakdown voltages and therefore are suitable for

high power circuits. These high power circuits can be used in applications like satellite

communications, warfare systems, and cellular base stations. GaN-based devices have been

shown to have high power handling capability at microwave frequencies above X-band, and have

potential to generate high power at millimeter-wave frequencies as high as 100 GHz [27].









Several GaN circuits have been demonstrated, such as high speed switches [28], [29]; low

phase noise VCOs [30], [31]; power amplifiers [32]; and passive mixers [30], [33], [34]. The

previously reported GaN passive mixers had various conversion loss and linearity performances.

In order to examine the behavior of a GaN passive mixer, passive mixers were made in this

subsection.


















Figure 4-1. Die photo of one of the GaN HEMT devices with a device area of 200 Cpm x 1 pm.


4.1.1 Modeling of GaN Transistors in the Linear Region

GaN HEMT transistors were provided by the Airforce. It provided devices with different

gate lengths and gate widths. Die photo of one of the GaN HEMT devices with a device area of

200 Cpm x 1 Cpm is shown in Figure 4-1. IC-CAP modeling software was used to obtain the

Curtice cubic model for the measured DC and AC performance and the parameters were further

optimized in Agilent Advanced Design System (ADS) simulator. However, from the simulation

results and the measurement data, some important mixer parameters can not be predicted well.

These parameters include the optimum gate bias voltage, and the LO power requirement for

achieving certain conversion loss performance. This is due to the fact that a resistive mixer is










operated in the linear region of a transistor and the Curtice model is mainly focused on the active

region. Therefore, efforts were made on the device modeling in the linear region.




Gae g Rg CdRgd Rd Ld Drain


Cp Cp CgsCp p
-Cds Rds '
-- -- ~Rgs---



Ls


Rs

Source


Figure 4-2. Equivalent circuit model used for GaN HEMT devices.



In this work, accurate models in linear region at different gate bias voltages were created

based on measured data. The small-signal equivalent circuit model shown in Figure 4-2 was used.

L,, R,, Ld, Rd, Ls, and Rs are the parasitic components associated with the transistor interconnects

to the pads of three ports. C, models the capacitance of the pads. Cds, Cdg, Cgs, and Rds are

transistor parameters that vary with the gate bias. Small-signal s-parameters were measured at

different gate biases with source grounded and drain biased at 0 V. The gate bias was varied

from -7 V to -2 V with 0.5 V step. The use of small-signal model reduces the complexity of

modeling and gives an accurate model in linear region, which is critical to the design of resistive

FET mixer.










The most important parameter that controls the conversion loss is the value of turn-on

resistance Rds. The behavior of Rds WaS CUTVe-fitted using the sum of two hyperbolic tangent

functions with different weights:

R,=% +R, tanh(aV, +F )+R, tanh(bV, +V,) (4-1)

,where Ro, R1, R2, a, b, Vb1, Vb2 are COnstants and V, is the gate bias. Two hyper-tangent terms

are used here because using only one term is not enough to fit the measured data very well. One

hyper-tangent term has a steeper slope whereas the other has a slower slope at the transition

region of Rds from turn-on to turn-off, which is critical for resistive mixer performance.


10s



10
-A- 0.75um
-1 1.00um
E` i-EI-- 1.20um



103



102


-7-6 -5 -4 -3 -
Gate Bias (V)

Figure 4-3. Modeled Rds VeTSus gate bias on GaN devices with different gate lengths.



The model fitting results of Rds for the three GaN devices with different sizes of 300 Cpm x

0.75 Cpm, 300 Cpm x 1 Cpm, and 300 Cpm x 1.2 Cpm are shown in Figure 4-3. As shown in the figure,

the device with smallest gate length has the lowest value of turn-on resistance. The turn-on











resistances are 12.6 02, 15 02, and 23 0Z for gate lengths of 0.75 Cpm, 1.0 Cpm, and 1.2 Cpm,


respectively.

4.1.2 Design of GaN Resistive Mixers

The model of the transistors from the previous section was used in the Agilent Advanced


Design System (ADS) to simulate the conversion loss. The IF power was obtained using Fast

Fourier Transform of the transient data simulated by ADS. The simulation results of the


conversion loss versus LO power is shown in Figure 4-4 with comparison to measurement results

that will be discussed later.



18

17tZ "s -- mea 0.75um
-A- mea 1.00um
-e mea 1.20um
161 "'--8-- sim 0.75um
m --a-- sim 1.00um
15 --e-- sim 1.20um


14




12




10


5 7.5 10 12.5 15
LO Power (dBm)


Figure 4-4. Measured and simulated conversion loss versus LO power for GaN devices with
different gate lengths.



The circuit was simulated with RF, LO and IF frequencies of 1.7 GHz, 1.9 GHz, and 200


MHz, respectively. The gates were biased at -5 V, -4.5 V and -4.7 V for the gate length of 0.75


Cpm, 1.0 Cpm, and 1.2 Cpm, respectively, where the lowest conversion loss for each circuit was










obtained. From the figure, it can be seen that the mixer using 0.75 Cpm device has the lowest

conversion loss since the turn-on channel resistance is the lowest among the three devices. The

figure also indicates that the conversion loss does not change much when LO power is increased

above 14 dBm, which matches pretty well with the measurement results.

Figure 4-5 shows the schematic of these single resistive mixers. LO is applied to the gate,

RF is applied to the drain, and the IF is generated at the source. Quarter wavelength transmission

lines are used in the RF and LO matching network as RF chokes. The open-circuited 1/4 line at

the IF end is used as LO and RF short to improve the LO-IF and RF-IF isolations.




Bond
Wire IYI~ RF


L~ GaNRFMatching
I I HEMT
LO
Matching I n


Gate Bypass IF
Bias Cap

h/4 @RF



Figure 4-5. Schematic of the single-FET resistive mixer.



4.1.3 Measurement Results

The circuits were fabricated on FR4 substrate with thickness of 1.6 mm. The dielectric

constant is 4.4 and the loss tangent is 0.022 at 2 GHz. Picture of one of the resistive GaN mixers

is shown in Figure 4-6. The three mixers were biased at their optimum bias points where the

minimum conversion losses were achieved. The optimum gate bias for devices with gate length










of 0.75 Cpm, 1 Cpm, and 1.2 Cpm were -5.2 V, -4.3 V, and -3.2 V, respectively. The bias voltage

were set to be just below the turn on voltage of each transistor, which allowed the LO signal to

turn on and off the channel effectively.




















Figure 4-6. Photo of a GaN mixer board.



Figure 4-4 shows the measurement results of conversion loss versus LO power, in

comparison to the simulation results. For all the devices, the optimum LO power is 14 dBm. If

the LO swing is too small, the channel cannot turn on completely, therefore the conversion loss

will be higher. Simulated results are also shown in this graph. It matches pretty well for the

simulated data and measured data.

Figure 4-7 shows the frequency response of the conversion losses. It can be seen that all

three mixers have the lowest conversion loss at 1.7 GHz, where the mixers were designed for.

Figure 4-8 shows the conversion loss versus RF power, at RF=1.7 GHz and LO=1.9 GHz. The

LO power was fixed at 14 dBm. From the graph, we can see that the conversion loss of device

with the smallest gate length is the best among all. The conversion losses are 9.5 dB, 10.5 dB,










and 1 1.8 dB for devices with gate lengths of 0.75 Cpm, 1.0 Cpm, and 1.2 Cpm, respectively. The

input 1 dB compression points (PldB) are 11 dBm, 11 dBm, and 12 dBm, respectively.


1.55 1.6 1.65 1.7 1.75 1.8
RF Frequency (GHz)


Figure 4-7. Measured conversion loss versus RF frequency.


15

14 300um x 0.75um
-1 300um x 1.0um
-- 300um x 1.2um
~13

012




10


-5 0 5 1(
RF Power (dBm)


Figure 4-8. Measured conversion loss versus RF power.


Figure 4-9 shows the two-tone third-order intercept point (IIP3) measurement results. The

figure shows both the fundamental and the 3rd order inter-modulation products with two-tone RF
























































LO Power
(dBm)
14
14
14


Gate Bias
(V)
-5.2
-4.3
-3.2


input at 1.7 GHz and 1.701 GHz. By extrapolating the measured data in the figure, IIP3 of 27

dBm, 25 dBm, and 24 dBm were obtained for the devices with gate length of 0.75 Cpm, 1 Cpm, and

1.2 Cpm, respectively.


O 5 10 15 20 25
RF Power (dBm)

Figure 4-9. Two-tone IIP3 measurement result of the GaN resistive mixers.


In conclusion, three GaN resistive mixers were designed, tested, and compared. The test

results show that these GaN resistive mixers have comparable performance to other mixers using

wide bandgap devices as well as GaAs HEMT devices. Table 4-1 shows the summary of the

performance of the mixers and Table 4-2 shows the comparison with other published results.


Table 4-1. Summary of the GaN resistive mixers

Gate Length CL (dB) PldB IIP3
(um) (dBm) (dBm)
0.75 9.5 11 27
1.0 10.5 11 25
1.2 11.8 12 24









Table 4-2. Summary of the III-V resistive mixers from existing publications
IIP3 LO Power
Technology Freq. (GHz) CL (dB) PldB (dBm)
(dBm) (dBm)
This AlGaN/GaN-
1.7 -0.2 9.5 10 26 14
work HEMT
[28] SiC-MESFET 5.175 -0.25 7.8 X 30 23
AlGaN/GaN-
[28] 5.175 -0.25 7.3 X 36 30
HEMT
AlGaN/GaN-
[29] 12.4 -2.4 17 30 40 20
HEMT
[30] SiC Diode 0.5 -0.1 12 x x x
[35] InP MODFET 95.5 -1.5 9 8 x 8
[36] GaAs G-FET 5.2 -0.95 5.5 16 23 10
[36] GaAs D-FET 5.2 -0.95 7.4 4 13 0



4.2 CMOS Passive Mixer

In the previous section, the design of board level resistive mixer is shown. In this section, a

wideband resistive down-converting mixer was designed and fabricated using TSMC mixed-

mode 0.18 Clm CMOS technology. Wideband matching at the RF ports and source follower at

output buffer at IF ports were used to achieve wideband frequency response. This resistive mixer

covers a wide frequency range from 1 GHz to 11 GHz with 7 + 0.5 dB conversion loss. The

output buffer stage consumes 3 mW, which is much lower than previously published wideband

active mixers. This mixer is suitable for low power UWB devices.

4.2.1 Discussion on CMOS Resistive Ring Mixer

Techniques to derive the conversion loss of a passive mixer can be found in [3 7]. In order

to get the idea of how the bandwidth and conversion loss of the resistive mixers are determined,

three different CMOS technologies were used in the simulation to observe performances in the

frequency responses and conversion loss. The models used in this study are provided by TSMC.

Figure 4-10(a) shows the schematic of the simulated passive mixers using different gate

lengths and widths. Figure 4-10(b) shows the equivalent circuit while the mixer is operating and









this Figure will be discussed later. In the simulation, all of the transistors are provided with the

same power of LO signals at the gates.



V LO CL LO o-



V O LO- LO o-


(a)


V, 4 Cch~f+C Rt(t) Rt(t-T/2) Cch(t-T/2)+C,
~~Cchf) c~h -T/2)+ 2C, Ccht> c~h(t-T/2)+ 2C,
III I ) I (II.

Va Cch(t-T/2)+C, Rt(t-T/2>) Rt(1)) Cch ] L /1


(b)

Figure 4-10. Schematics of (a) a double-balanced CMOS resistive mixer, (b) an equivalent
circuit of the resistive mixer.


Figure 4-11 shows the conversion loss of a double-balanced resistive mixer versus

frequency from 1 GHz to 20 GHz using three different CMOS technologies with gate lengths of

180 nm, 90 nm, and 65 nm. Four curves of conversion losses are shown in each graph with

different W/L ratios equal to 400, 300, 200, and 100. From Figure 4-11, several conclusions can

be made. First, for a certain technology, the smaller the ratio of W/L is, the higher the conversion

loss is. This is due to the turn-on resistor is smaller when the device is larger. Also, the smaller

W/L is, the conversion loss is more flat. Second, for different technologies, with the same W/L

ratio, the resistive mixer with smaller L has more flat conversion loss. Third, with the same W/L

ratio, devices with larger gate length have lower conversion loss.










The reason that the conversion loss is lower for larger length devices is that the turn-on

resistance is larger for deep submicron devices. When the gate length is getting smaller, the

electron mobility is also getting lower due to the high electric field at the gate as shown:


p = o (4-2)
S 1 + 0(VGS VTH


, where pu~ is the effective mobility, 90 is the low field mobility, B is a fitting parameter, VGS and


VTH are gate-source voltage and threshold voltage, respectively. 0 is approximately inversely

proportional to the thickness of gate-oxide. Therefore, the short channel effect of the transistor

makes the mixer conversion loss higher.

8.5

7.5 180nm

6.5

5.5

8i 4.5T -*- W/L = 400
a3 8.5 -#- W/L = 300
m-A- W/L = 200
S 7.5 90m-- W/L = 100



0 5.5

4.5
8.5

7.5 65nm

6.5

5.5

4.5
1 4 7 10 13 16 19
Frequency (GHz)

Figure 4-11. Conversion loss versus frequency of CMOS resistive mixers with different gate
lengths.









The bandwidth dependency on the gate length could be described as follow. Determination

of the bandwidth can be seen from Figure 4-11l(b). Rs is the source equivalent resistor from the

previous stage; Rt is the time-variant resistors of the transistors since they switch on and off

according to the LO signals, which has a period of T; CL is the load capacitance; Cch is the

channel capacitance of the transistors; and Cj is the junction capacitance of the transistors. For

transistors operating at different regions, channel capacitance varies according to the LO signal.

While the transistor is off, the channel capacitance is small (depletion capacitance) and while the

transistor is on (operated in linear region for a resistive mixer), the channel capacitance becomes

WLCox/2, where Cox is the oxide capacitance.

The bandwidth of the mixer is determined by the pole location located at the input of the

RF ports. The pole location can be seen as 1/RsCtot. Assume that the mixer is driven by an LO

signal with a square wave in the waveform shape, Rt(t) for one pair of the transistors is zero and

Rt(t-T/2) is infinity. If the passive mixer is divided into two half circuits since the double

balanced mixer is symmetrical in structure, the equivalent input capacitance is equal to

Cot,=2Ceh(t)+2Ceh(t-T/2)+4Cj. Since for CMOS transistors with a smaller gate length, under the

same W/L ratio, the channel capacitance as long as junction capacitance are smaller comparing

to transistors with larger gate length. As a result, the pole location of passive mixers with smaller

gate lengths is larger than the one with larger gate lengths.

In conclusion, resistive mixers with larger gate length will have narrower frequency

response, but will have lower conversion loss; on the other hand, resistive mixers with shorter

gate length will have wider bandwidth but will have higher conversion loss. Furthermore,

because transistors with smaller gate lengths have smaller capacitance comparing to transistors

with larger gate lengths, the bandwidth is also larger.










4.2.2 Design of CMOS Resistive Ring Mixer

A wideband passive mixer was designed using 180 nm CMOS technology. Figure 4-12

shows the schematic of the resistive ring mixer. Double balanced ring structure is used because

of the superior performance of the isolation between ports and the cancellation of the even-order

harmonics. At the RF input port, series inductors of 1.4 nH and shunt capacitors of 90 fF are

used for matching. In addition, shunt resistors of 250 R are used to improve the wideband

matching.


Figure 4-12. Schematic of the wideband resistive ring mixer.


No matching circuits are used at the LO port in order to reduce the circuit area. Without

the LO matching circuitry, the LO power needed to drive the resistive mixer to minimum

conversion loss is slightly higher, but the difference of 1- 1.5 dB in simulation is not significant.

In our simulation, LO power needed for the circuit is about 8 dBm to make the conversion loss

minimum.










At the IF output port, source followers are used for impedance matching to 50 R, since the

lumped elements needed for 50 R impedance matching at 500 1VHz IF would occupy too much

space on chip. Shunt capacitors to ground are used to make the LO and RF signals shorted to

ground and improve the LO-to-IF and RF-to-IF isolation. DC blocking capacitors are placed in

series to block DC biases of the source followers from the resistive mixer core.


Vb Vg Vdd GND




GND~ ~~ GND


RF+ Ilk c LO+


GND lgjC-sIii Plijl GND


RF-I .P LO-"


GND liiin IIi!IGND




GND IF GND IF- GND

Figure 4-13. Chip photo of the fabricated mixer (chip size including the pads: 0.95 mm x 0.65
mm).



Three DC biases for output buffer are supplied externally when measuring the circuit. The

optimum values for Vb, Vg, and Vdd are 0.5 V, 0.5 V, and 1 V, respectively. Increasing the value

of Vdd above 1 V does not make a significant difference on the mixer performance. Decreasing

the value of Vdd WOuld increase the loss. Therefore, the lowest possible bias of 1 V is chosen to

lower the power consumption of the output buffer. The current flow through the source follower

is about 3 mA; therefore the power consumption is 3 mW. Figure 4-13 shows the die










microphotograph of the resistive ring mixer. The size of the chip is measured 0.95 mm x 0.65

mm.

4.2.3 Simulation and Measurement Results

This mixer was measured on-wafer. Signal generators were used to generate the RF and

LO signals. Spectrum analyzer was used to measure the converted signal at the IF port. External

baluns were used at RF, LO, and IF ports. All the measurement losses from the baluns and the

cables were carefully calibrated using the network analyzer.

20



15 -*- Measurement
v, ------ Simulation

c 10



0 5



01 2 4 6 8 10 12
RF Frequency (GHz)

Figure 4-14. Measurement and simulation results of conversion loss versus RF frequency with
fixed IF frequency 500 MHz.



Figure 4-14 shows the measured conversion loss from 1 GHz to 12 GHz. The solid line

with symbols indicates the measured data, whereas the dashed line indicates the simulated data

using CADENCE SPECTRE. LO frequency is 500 MHz higher than the corresponding RF

frequency, so that the IF frequency is fixed at 500 MHz. From the figure, the conversion loss is

within 7+0.5 dB from 1 GHz to 11 GHz, which covers the entire UWB band. The Vdd for the

bias circuitry is set at 1 V, and the current consumption is 3 mA. The total power consumption is









3 mW. The measurement results and simulation results are quite consistent with each other as

shown in the Eigure.

Figure 4-15 shows the measurement results for input 1 dB compression point (PldB) and

input third-order intercept point (IIP3) for the CMOS wideband resistive ring mixer. It is well

known that resistive mixer has better linearity performance compared to the active mixers

because the transistors are operating in the linear region. For the linearity measurement, LO

power of 9dBm was applied to the resistive mixer. As shown in the Eigure, PldB is 5+1 dBm for

1 GHz to 12 GHz. IIP3 was measured with two RF input signals separated by 10 MHz. Third-

order inter-modulation products were at 480 MHz and 520 MHz, where the first-order signals

were at 500 MHz and 510 MHz. As shown in the Eigure, IIP3 is within 9-13 dBm from 1 GHz to

12 GHz. This wideband mixer has very good linearity performance, which makes it suitable for

high dynamic range UWB receivers.

Figure 4-16 shows the measured performance of conversion loss versus LO power. In

resistive mixers, LO voltage swing has to be large enough to let the channel resistance of the

transistor reaches its lowest limit, so that the conversion loss could be minimized. However,

there is a limit of conversion loss where it will not improve any further with the increase of LO

power. The measurement was conducted at ten different frequencies from 1 GHz to 10 GHz,

with 1 GHz step. All the 10 curves in Figure 4-16 show the same trend that the higher the LO

power, the smaller the conversion loss. The conversion loss approaches to a limit when the LO

power is over 9 dBm, which is why 9 dBm of LO power was chosen in the previous

measurements. If higher conversion loss can be tolerated in some applications, the requirement

of LO power can be reduced. For example, for 10 dB conversion loss, LO power can be reduced











by half from 9 dBm to 6 dBm. Figure 4-16 also shows that the LO power requirement is almost

the same from 1 GHz to 10 GHz.


20


PldB
-* IIP3


E
m

~c, 10
a
o
r
co 5
m
o
a


2 4 6 8
RF Frequency (GHz)

Figure 4-15. Input PldB and IIP3 versus RF frequency.


25




8' 20

O


c 15
O



0 10


6
LO Power (dBm)


Figure 4-16. Measurement results of conversion loss versus LO power. The measurements were
conducted for ten RF frequencies from 1 GHz to 10 GHz.


Figure 4-17 shows the measurement result of S11 for the RF port from 100 MHz to 12 GHz.

The S11 was measured single-ended using GSGSG probe with one port terminated with 50 R.










The RF input matching is very wideband. The minimum return loss occurs at 3.5 GHz with 32

dB return loss. The overall return loss is better than 10 dB from 100 MHz to 6 GHz.




-5

-10

m -15

-20

-25

-30

-35
0 2 4 6 8 10 12
RF Frequency (GHz)


Figure 4-17. Measurement results of the RF return loss from 100 MHz to 12 GHz.


O 2 4 6 8 10
Frequency (GHz)

Figure 4-18. Measurement results of the NF of the wideband passive mixer.


Figure 4-18 shows the measurement result of the NF of the wideband passive mixer across

the frequency from 1 GHz to 10 GHz. The NF measurement was conducted using two different

LO power of 7 dBm and 10 dBm. The NF measurement was done at a fixed IF frequency of 500










MHz. While the LO signal is 7 dBm, the NF is around 11 dB and goes higher at frequencies

above 6 GHz. While the LO signal is 10 dBm, the minimum NF is 9.5 dB and also goes higher at

frequencies higher than 7 GHz.

In this mixer design, the double balanced structure was used in the resistive mixer to

improve the isolation. Across the whole band from 1 GHz to 11 GHz, the measured RF-to-LO

isolation is -3911 dB, and LO-to-RF isolation is -3711 dB. However, the isolation is not good

enough in certain applications such as the frequency synthesizer described in Chapter 5. With the

isolation, LO signal will leak to the output and cause spurious signals at the output. In order to

solve this problem, subharmonic mixer structure will be examined in the next section for the

improvements in the LO to output isolation.

4.3 CMOS Passive Harmonic Pumped Mixer

Subharmonic mixers draw a lot of attention recently in direct conversion receivers. One of

the biggest problem in implementing direct conversion receiver is that the feed-through of LO

signal might corrupt the receiving signal and saturate the gain stages along the receiving chain.

Also, subharmonic mixers become popular at millimeter wave where a low phase noise LO is not

readily available.

Traditionally mixers use fundamental LO signal and generate output frequencies of four= /72

~fLO. As for subharmonic mixers, they use second, third, or even higher order harmonics of LO

signals to realize the frequency conversion. The output frequency of a subharmonic mixer is




,where n is the order of harmonic it uses.

To date, subharmonic mixers are published using all different kinds of materials, including

III-V compound semiconductors, SiGe, or HBTs. Recently CMOS mixers appear more and more










frequently on the research j ournals due to the ability of integration. In [3 8], double balanced

Gilbert cell subharmonic mixer was presented using BiCMOS process at PCS band. In [39],

performances of CMOS subharmonic mixers were analyzed in detail. In [40], transformer and

quadrature couplers were used as baluns and quadrature phase shifters in a CMOS Gilbert cell

subharmonic mixer. In [41], subharmonic CMOS mixers were exemplified even at millimeter-

wave frequencies using source-pumped LO or gate-pumped LO.

In this design, a ring str-ucture passive subharmonic mixer is first demonstrated using a

1P6M 0.18 Clm mixed-mode CMOS process with MIM capacitors and thick top metal for

inductors. A VCO is integrated with the subharmonic mixer. Quadrature phases of the VCO are

generated using divide-by-2 circuits. In section 4.3.1, schematics and system blocks are shown,

and in section 4.3.2, simulation and measurement results are provided.

RF Input

LO
BuffersMatching

RF
VCO 10

DIV-2 900o, LO IFJ Buffer Output

2700

Passive Subharmonic Mixer



Figure 4-19. Systematic blocks of the subharmonic mixer with an integrated VCO.



4.3.1 Discussions on Each Block

Figure 4-19 shows the block diagram of the passive subharmonic mixer with integrated LO

in this design. Four phases feeding into the subharmonic mixer are generated by a differential

VCO with a divide-by-2 circuit. For passive mixers, it is good to hard switch on and off on the










gate of the transistors. Therefore, LO buffers are added to amplify the signals' swing feeding into

the mixer.

A broadband matching circuitry is added at the RF input ports. Biasing is also applied from

the RF matching circuit. It is tricky for the RF and LO signals in a passive mixer so that optimum

conversion gain could be gotten. At the outputs, an output buffer is added for the measurement

purpose.

Vdd


5.35

S5.25

5.15

S5.05

FZ 4.95

4.85
Ib 0 0.5 1 1.5 2
Control Voltace (V)

(a) (b)

Figure 4-20. A 5 GHz VCO's diagrams of (a) the schematic, and (b) the oscillation frequency.



Following shows the schematic and simulation results of individual blocks.

1. VCO and Divide-by-2 circuitry: Figure 4-20(a) shows the schematic of the 5 GHz VCO.

Configuration is a standard cross-coupled NMOS oscillator. The output is connected to

a divide-by-2 circuit through a RC level shifter. The inputs of a divide-by-2 circuit have

to be biased properly to get a more reliable dividing operation. Figure 4-20(b) shows the

simulated output frequency of the VCO. The VCO has output frequencies range from










4.9 GHz to 5.3 GHz for the control voltage change from 0 V to 1.8 V. The tuning range

of the VCO is about 8% to the center frequency.

Divide-by-2 circuit is shown in Figure 4-21. Output of the VCO is first leveled

shifted through a RC level shifter, then feed into the divide-by-2 circuit. The divider is

implemented as cross-coupled current mode latches. Figure 4-22 shows the simulation

results of the signal feeding into the divider and the signal output from the divider. VCO

generates frequency of 5.1GHz and the divider successfully divides the input frequency

to one half.


Figure 4-21. Schematic of a current mode divide-by-2 circuit.



2. Mixer Core: Since resistive mixers mix incoming signals through the modulation of the

channel resistance of the transistors, it is worth to observe the variation in resistance of a

traditional resistive mixer and a resistive subharmonic mixer. Figure 4-23 and Figure 4-

24 show schematic and simulation results of the testing in variation in conductance of










single NMOS transistor and a pair of NMOS transistors with differential gate-pumped

LO signals.


2.5

2.1


1.3

0.9
1.9

1.7-


O 1.3

1.1
16n 17n 18n 19n 20n
Time (s)

Figure 4-22. Simulation results of the divider input and output.



LO 00
LOOo

INO |I IC
T
LO 1800

(a) (b)


Figure 4-23. Variation of channel resistance of a (a) single NMOS with gate pumped LO, and a
(b) parallel NMOS pair with differentially pumped LO.



The conductance of the channel resistance of a NMOS transistor is shown in Figure

4-24(a). The transistor is turned on every LO cycle of 400 MHz. The conductance of the

channel resistance of a pair of NMOS transistors is shown in Figure 4-24(b). The

differential LO signals alternatively turn on the transistors within the NMOS pair. This

is equivalent to using a LO signal which is two times the frequency using here. As a










result, this pair of the transistors could be used in substitute with the NMOS transistors

in the traditional resistive mixer.


20m
2 16m
B 12m
Q 8mm


0.0 10n 20n 30n
Time (s)
(a)
20m
16mhn
a, 12m




0.0 10n 20n 30n
Time (s)
(b)

Figure 4-24. Variation in conductance of a (a) resistive mixer, and a (b) resistive harmonic
mixer.


Figure 4-25 shows the schematic of the proposed resistive harmonic double

balanced mixer. The structure is similar to the original resistive mixer, with single

NMOS becomes a parallel NMOS pairs. Gates of each transistor pairs are driven by the

LO signals with 180o phase difference. As a result, four phases are needed for a

harmonic balanced mixer.

Figure 4-26 and 4-27 show the transient simulation result and the correspondent

spectrum. Input signal is at 5.1 GHz and the VCO is oscillated at 5.35 GHz. The IF

output frequency is at 250 MHz. From the simulation result, the conversion loss of this

resistive subharmonic mixer is about 4 dB.











LO 00


RF+ C r IF+

T
LO 1800


LO_9001 ~ LO_2700 LO_900-1 -~ LO_2700


LO 00


IF-C DRF-

T
LO 1800


Figure 4-25. Schematic of a resistive harmonic double balanced mixer.



100~m : v (f"/111/et25 A0A11l/netl4); tran (V)









0010 2n 0n40


Figure 4-26.Transient smuainoiptadotu.

3.~~~~~~e~ RF bisn and a1 machng:Wi~le) then RFsgasaefe noasbaroiasv








piu erform Taniets. igureio 4-2 ilustrtstredfeetRbispnsaml ,, and upt







9, relatively to the four phases of LO signals. From (1 to 9, the biasing points are









moving higher toward the crossing points of four phases of the LO signals with a

voltage potential difference of AV. Figure 4-29 shows the simulation results of the RF

and IF signals of a subharmonic passive mixer with the three RF bias conditions

described in Figure 4-28. With bias condition (1, the RF signal is modulated by the IF

signal where the RF waveform has an envelope with frequency equal to the IF

frequency. Also can be seen from Figure 4-29(a), the IF signal is also modulated by the

RF signal. This is because that at a certain biasing point, transistors on different

branches in a sub-harmnic mixer (along the arrow shown in Figure 1) turn on at the

same time because the overlap in the waveforms of quadrature signals. Since the

transistors in each branch are in series to each other in a passive mixer, turning on two

transistors at the same time shorts the positive and negative nodes of the RF signal.

Similar analysis also applies to the IF signals.


Under the bias condition 9, the RF and IF signals do not interfere with each other

as shown in Figure 4-29(b). However, the magnitude of the IF signal is small (and thus

a higher conversion loss). This is because the transistors do not have enough of gate

voltage to be fully turned on completely. For a passive mixer, a large LO swing is

desired so that it can completely turn-on the switching transistors to achieve a good

mixing performance with less conversion loss.

The optimum biasing point would be the condition 9 in Figure 4-28, where the

crossing points of the four phases LO signals are about a threshold voltage higher than

the RF biasing point. In this case, no short circuit would happen during the mixer

operation while the quadrature LOs turn on the transistors sequentially, and this pertain

the signal magnitude of the RF signal. However, the tradeoff would be the need of a












higher LO swing comparing to a fundamental passive ring mixer so that the transistors


still have enough of gate voltage to be fully turned on. In order to have a high LO swing,


inverters are used as buffers in this design to have a rail-to-rail LO swing. However,


steep edges after the inverters are not desired or that the LO crossing points shown in


Figure 4-28 would be too high. As a result, the buffers were intentionally designed to


have smaller sizes so that the LO waveforms can be smoother.


-: dB20(df tlwa vew49s 1 11() 2e -08



RF @i2 5.1GHz
-- -17.24dBy


















B.010G 20G


-1 0m: dB20(dftlvwavew49s112() 2e-0~8
LSB
-20 e-21.41dBy

-so a

-40 0

-50 0













-1107


-10.0

-20.0

-ae-e

-40.0




-50.0









-110


(a) Input spectrum (b) Output spectrum


Figure 4-27. Output spectrums of the subharmonic mixer' s (a) input and (b) output.




Third, how to determine the sizes of the switching transistors? It is known that the


turn on resistance is smaller for bigger devices. The value required for turn on resistance


is set by the output frequency of the mixer. In this design, the output frequency is about


several hundred MHz. Because the frequency is not high, the device size could not be


that big. Device size of 20 Clm/0. 18 Clm is chosen in this design.





LOGo L90o L0l80o LO270o


(3) ......... ........ ...A









Figure 4-28. Different RF input biasing levels with differential LO signals.



Bias condition 1


50 40
30 20
20

-10 I Ill I I I II
S-20
-30
-50 -40


rlYk 1, hIYI


.rUIC,


.~1.


~WYI~ '~IW~FI''


1 111' 111'


Bias condition 2


50 40
30
o 20



-30-2

-50 -40


Bias condition (3)


50 40
30.
o 20



-30-2

-50 -40
0 2 4 6 8 10 0


3 6 9 12
(b)


Time (ns)


Figure 4-29. Simulation results of the (a) RF waveforms, and (b) IF waveforms, of a
subharmonic passive mixer with different RF bias conditions.









4.3.2 Measurement Results of the Resistive Harmonic Mixer

The proposed subharmonic passive mixer with an integrated quadrature LO was fabricated

using a 0.18 Cpm mixed-mode CMOS technology. The technology has six metal layers with a

thicker top metal layer for high-Q on chip inductors. Metal-insulator-metal (MIM) capacitors are

also provided in the technology. Die photo of the fabricated circuit is shown in Figure 4-30. The

chip has an area of 0.85 mm x 0.7 mm. External wideband baluns were used to convert

differential signals to single ended signals.
























Figure 4-30. Die photo with an area of 0.85mm x 0.7mm.



The measured tuning frequency of the VCO is from 4.9 GHz to 5.3 GHz. The relationships

between the RF bias condition and the conversion loss are shown in Figure 4-31. As described in

the previous section, the conversion loss is minimal while the RF signal is biased at 1 V, which

would be about a threshold voltage lower than the crossing points of the four phases of LO.

Figure 4-32 shows the voltage conversion gain versus frequency. The gain de-embeds the loss





__I_~


due to the output buffers and other measurement setups. In the measurement, the VCO is running

at a fixed frequency of 5 GHz (LO is running at half the frequency of the VCO). The RF signal is

swept from 3.5 to 7 GHz with the output IF frequencies varying accordingly. The lowest

conversion loss of -5.8 dB is achieved at 5.2 GHz. The mixer can be used from 3.5 GHz to 6.7

GHz within 3 dB gain variation.


-4






-10



-12


0.8 0.9 1 1.
RF Bias (V)

Figure 4-31i. Effects of RF bias on the conversion loss of the mixer.




O


-2
Fs
~ -4
r:
ed
13
-6
r:
o
k
a~ -8
o
U
-10

-12


3.5 4 4.5 5 5.5 6 6.5 7
RF Frequency (GHz)

Figure 4-32. Measurement and simulation results of conversion gain of the mixer.










Figure 4-33 shows the measured LO power leakage to the RF and IF ports. The l xLO

leakages to the RF port and IF port are about -35 dBm and -45 dBm across the LO tuning band;

and the 2xLO leakages are around -60 dBm and -65 dBm. Figure 4-34 shows the measured

linearity performance of the mixer. The 1 dB compression point is -10 dBm, the IIP3 is -2 dBm,

and the IIP2 is 26 dBm. The subharmonic passive mixer itself does not consume power, while

the power consumption of other components, including a VCO, divide-by-two circuits, LO

buffers, and IF buffers, is 25 mA under a 1.8 V supply voltage.


SLO-RF Leakage
-10 LO-IF Leakage
S2LO-RF Leakage
j -20 2LO-RF Leakage
3 -30
a-40
P~-50
i~-60
~i-70
-80
2.45 2.5 2.55 2.6 2.65
LO Frequency (GHz)

Figure 4-33. Measured LO leakage to the IF and RF ports with varying LO frequency.


4.4 Conclusions

In this chapter, several kinds of resistive mixers with different topologies and fabrication

topologies are presented. First, a board level GaN resistive mixer is discussed in detail with

modeling and mixer performance. Next, a 0.18 Clm CMOS resistive ring mixer on TSMC mixed-

mode technology was designed, fabricated, and measured. The resistive ring mixer has very wide

bandwidth covering from 1GHz to 11GHz with 7+0.5 dB conversion loss. Finally, a

subharmonic CMOS resistive mixer is also measured. The subharmonic mixer is suitable for










direct conversion receiver because of its immunity to LO feed through problem. The

subharmonic mixer will be used in the OFDM-UWB frequency synthesizer in Chapter 5. It helps

the frequency synthesizer to have smaller LO leakage at the output. The two CMOS passive

mixers are summarized in Table 4-3.


-20




-60
O
-80


-30 -20 -10 0 10 20 30
Input Power (dBm)
Figure 4-34. Measured PldB, IIP2, and IIP3 of the passive subharmonic mixer.










Table 4-3. Summarize of the fundamental passive mixer and the subharmonic passive mixer

Fundamental Mixer Subharmonic Mixer

Process TSMC 0.18um CMOS TSMC 0.18um CMOS
RF Frequency 1GHz -11GHz 3.5GHz 6.8GHz
LO Frequency RF Frequency + 500MHz 4.9GHz 5.3GHz
Conversion Gain -6dB -5.8dB
IIP3/IIP2 10dBm/- -2dBm/25Bm
LO/2LO-to-IF isolation -35dB/- -45dBm/-65dBm
LO/2LO-to-RF isolation -37dB/- -35dBm/-63dBm

Chip Size 0.95mm x 0.65mm 0.85mm x 0.7mm
Supply Voltage IV 1.8V
Power Consumption 6mW 45mW









CHAPTER 5
CONSIDERATION AND DESIGN OF AN UWB FREQUENCY SYNTHESIZER

At the beginning of this chapter, a switching band VCO was designed and tested. The

design considerations about a switching band VCO are also provided. This switching band VCO

has a tuning range from 3 GHz to 4.3 GHz.

Although the tuning range of the switching band VCO is large, it still lacks the ability to

tune the whole UWB spectrum from 3 GHz to 10 GHz. Furthermore, because of the special

requirements on the wide frequency covering range and the ultra fast switch time, traditional

PLLs could not be used in this design. As a result, a frequency synthesizer based on single-side-

band (SSB) mixers with only one VCO used for a MB-OFDM UWB system was designed and

simulated.

The structure of Chapter 5 is listed as follows. Section 5.1 describes a switching multi-

band VCO. Brief introduction to the frequency synthesizer is given in Section 5.2; topology that

is used in this study is presented in Section 5.3; concerns about spurious signals are given in

Section 5.4; finally simulation results of the CMOS implementation of the ideas are shown in

Section 5.5.

5.1 A Switching Band VCO

Voltage controlled oscillators (VCOs) usually utilize the change in capacitance value of

varactors to make the frequency tuning. However, the capacitance variation of capacitance in

varactors is limited if a wideband VCO is needed. There are several reasons why the VCOs with

wideband tuning range are wanted. First of all, because of the reduction of the supply voltage in

sub-micron CMOS technology, the voltage variation that is used on varactors also reduces. This

limits the variation in capacitance of varactors. Second, multi-band transceivers are getting

popular since engineers are trying to design universal transceiver, which could be used in










conjunction with a fast adaptive signal processing chip and adaptively modified the configuration

to fit different communication standards. In this case, the VCO has to run at frequencies covering

the whole bands. Third, because of process variation, running frequency of a VCO will be

different from wafer to wafer. In order to increase the yield so to reduce the cost of making the

chips, extensive calibration techniques are employed on modern CMOS communication chips.

People in [42] use extensive varactor bands and digitally control the capacitance in the resonant

tank to cope with the variation in the temperature, process, and voltage.

In order to design a VCO with wide tuning frequency range, concept of switching resonant

tank is proposed in [43], [44], and [45]. Either inductor or capacitor could be switched to change

the resonance frequency of the tank. However, papers presented so far do not have the ability to

switch both of the inductors and the capacitor. In this design, a switching band VCO was

designed to show the ability of the switching resonant using both switching inductors and

switching capacitors. Design considerations will be provided in Section 5.1.1; experiment results

will be provided in Section 5.1.2.

5.1.1 Design of the Switching Band VCO

In order to change running frequencies using switching resonant tanks, two components

could be used to switch, one is capacitor, and the other one is inductor. Switching capacitors is

desired as the first thought because the area occupied of inductors is usually big and makes the

chip huge and costly. In order for an oscillator to start oscillate, the criteria

GmUo2L2 Rs=GmQind2Rs> 1 should be fulfilled, where Gm is the effective transconductance of the

VCO core transistor, ao is the oscillation radian frequency, L is the inductance value in the

resonant tank, Rs is the equivalent series resistance of the inductor, and Qind is the Q-factor of the

inductor. In general, Q factor of inductors are roughly on the same order for certain technology.

In order to maintain power consumption (Gm) to some acceptable value, Rs has to be increased.









From equation Qind=coL/Rs, it can be seen that inductance value has to be larger while Rs is

increased. For a VCO with extreme wide tuning range, e.g. highest frequency to lowest

frequency ratio of 1.5, keeping inductance value the same might not be a good choice. For an

oscillator, small inductor in the resonant might cause the oscillator failing oscillate due to

insufficiency in feedback gain. While a switching oscillator is running at low frequency mode,

inductor value should be increased compared to the high frequency mode. Therefore, switching

inductor is desired while the tuning range is extremely wide.








Mb M 2 Mb
Tuning Tank
L1 VL L1

LbL2 M ML L2 L





C~C2 2 1

| Vc

| Vc; ~1 VC2 Vc, Vc1~




Figure 5-1. Schematic of the switching band VCO.


However, too many switching inductors would make chip size too large. Two switching

inductors are used in this design. Three levels of tuning mechanism are used in this VCO from

coarse tuning to fine tuning. Switching inductor set the first level of tuning frequency. Two bits









of switching capacitors are used as second level of tuning frequency. Finally, varactors are used

as the third level of tuning frequency, and they make the output frequencies of the VCO

continuous throughout the spectrum. As a result, there are totally eight different frequency

settings for this switching band VCO.

Figure 5-1 shows the schematic of this switching band VCO. M1 and M2 form the PMOS

cross coupled pair to provide feedback for oscillation. Mi provides the bias current. Lls and L2S

are resonant inductors. L2S could be switched on and off using switches ML C1S, C2S, and Cvs

form the resonant capacitance. Both of C1 and C2 COuld be switched on and off using transistors

Mel and Mc2.

Leeson-Cutler' s Formula is presented as

2kTF m A
L(Am)=10log{ [1+( o) ](1+ )} (5-1)
Ps 2QL~ IW

,where k is Boltzmann's constant, T is the absolute temperature, F is noise factor of the core

transistors, Ps is the average power dissipated in the oscillation tank, wo is the oscillation

frequency, QL is the total quality factor of the tank, Ano is the offset from the carrier, and Amil/f3

is the corner frequency between the 1/f3 and 1/f2 regions. From the formula, it could be seen that

phase noise of an oscillator is controlled by the Q factor of the resonant tank for certain

technology and power of the signal. Figure 5-2 shows the equivalent circuits of switching

inductors while the switch is on or off. For switching band VCOs, in order to make the phase

noise stays constant for all bands, Q have to be the same whether switches are on or off. While

the switch is off, the Q factor is


(1+ ')Q.
w(L, +L,) m(L, +L,) L, (5 -2)
R, +R1 R, +R1 L, Q.
L, Q










While the switch is on, the Q factor is


Qo = = -= 0, (5-3)
R + RoN R,

where Q1 and Q2 are the Q factors for inductors L1 and L2. Ron is the turn on resistor of the

switch. The approximation in equation (5-3) is while Ron is much smaller then the series

resistance of inductor L1. This means the transistor size has to be large enough to make the turn

on resistor almost negligible compared to the series resistance of the inductor. Make equation (5-

2) and (5-3) equal will lead to Q1=Q2. As a result, Q factor of the two inductors has to be

designed equally so that the phase noise would be kept the same for all the switching bands.

VL=0V VL=1.8V



R1I R1



,C ,C

RON

L2 L2



(a) (b)

Figure 5-2. Schematic of resonant tank when (a) low frequency mode, and (b) high frequency
mode.



The two capacitors in the capacitor bank are designed to have capacitance ratio of two to

one. In this case, the total capacitance value could be varied from three unit capacitance to zero

unit capacitance. Also, the Q factors of capacitors in the resonant tank should be kept constant

for all switching bands. Q factor of a capacitor is defined as Qc=Res/coC, where Res is the series

resistance to the capacitor. To keep Qc the same, Res has to be changed according to the value of










capacitance C. Therefore, the size of switching transistors control the capacitors should be scaled

in proportional to the value of capacitors.

The switching band VCO is designed and fabricated using TSMC 0.18 Cpm CMOS mixed-

mode technology. The technology has six metal layers with top metal layer of 2Cpm thickness for

high-Q inductors. The inductors used here have octave shape to increase the Q value compared

to square inductors. Values of two inductors are 0.46 nH and 0.3 1 nH. Q factors of these

inductors are 10 at 5 GHz. The small values of inductors are used for intention to have wider

tuning range. The two capacitors are implemented in MIM capacitors with values of 850 fF and

430 fF. All of the NMOS switches are made large so that the turn on resistor is small to reduce

the Q factor of the resonant tank. For the switching inductor, the switch size is 600Cpm/0. 18 pm.

For the switching capacitors, switches have size of 600 Cpm/0. 18 Cpm and 300Cpm/0. 18 Cpm for the

larger capacitor and the smaller capacitor, respectively. The output buffers use large inductors to

drive external 50 R equipment.


















Figure 5-3. Die photo of the switching band VCO.



5.1.2 Experimental Results

Figure 5-3 shows the die photo of the proposed VCO. The chip has size of 730 Cpm in

























100







111







101


000


length and 660 Cpm in width. Measurements are done with GSGSG probes, and phase noise is

measured using HP/Agilent 70420A baseband phase noise test set. The three control bits are set

externally. 1.8V supply voltage is used with about 11ImA current flowing through the core VCO.


1E+03 1E+04 1E+05 1E+06 1E+03
Offset Frequency (Hz)

Figure 5-4. Measured conversion loss versus offset frequency.


While VL is set to 1.8 V, VCO is operating in low band; while VL is set to 0 V, VCO is

operating in high band. Each of the bands could be subdivided into four sub-bands that are

controlled by switching on and off capacitors. In each of these two bands, two capacitors are

switched on and off using Vax and Vc2. Varactors are tuned from 0 V to 1.8 V. For low band,










frequency of the VCO could be tuned from 2.89 GHz to 3.45 GHz, which is about 17.7 % of

tuning range; for high band, frequency of the VCO could be tuned from 3.59 GHz to 4.3 GHz,

which is about 18 % of tuning range. The operating frequencies of the VCO are about 7 % lower

compared to simulation ones due to the error in estimating capacitances of traces. Also, some

pieces of traces attribute certain amount of inductance are not considered when doing the

simulation.


4.5







Figue 55. he tnin caabiity f te sitchng andVCO


Mesre haenos i bot-10d~/z t1 ~ aa fo teosilaig rquny

For~~~~~~f th ihs w adtephs os rp oaot-05dcH t17 eaain

Measurement~~ phs os eut r but5d os hntesmlainoe lodet ea






eaho h u-ad.Figure 5-5. ilutae he tuning frequeny rang of each different controlO



so tettings. Four sbbands, ine low s bndhae frequencie bovering5 eac/h othe a itl btn sea ameon







as the four sub-bands in high band.

In summary, an eight-band digitally controlled band-switching VCO using 0.18 Cpm CMOS










technology is demonstrated. Design methodology is described. The measurement results show

that the VCO covers two bands of 2.9 3.45 GHz and 3.6 4.3 GHz. Phase noise of the VCO

stays constant around -110 dBc/Hz at 1 IVHz offset across all bands. Table 5-1 summarizes the

performance of this band-switching VCO.


Table 5-1. Performance summary of the band switching VCO

Tuning PN@100KHz PN@11VHz
DclDC2DL Freq (GHz)
Range (%) (dBc/Hz) (dBc/Hz)
110 2.89-3.08 6.4 -88.31 -108.98
010 2.97-3.18 6.83 -88.04 -111.36
100 3.01-3.22 6.7 -86.71 -108.29
000 3.19-3.45 7.8 -89.34 -111.75
111 3.59-3.86 7.13 -88.35 -110.24
011 3.68-3.97 7.58 -83.54 -111.27
101 3.83-4.14 7.78 -73.74 -105.51
001 3.93-4.3 8.99 -85.31 -106.23

*C1 is on/off for Dcl=1/0; C2 is on/off for DC2=1/0; L is on/off for DL=0/1



5.2 Introduction to MB-OFDM UWB Frequency Synthesizers

Due to the requirement of high data rate wireless transmissions, large spectrum bandwidth

was released for this purpose. Because of the extremely crowded spectrum usage at lower GHz

frequencies, FCC released 3-10 GHz spectrum for the use of ultra-wideband (UWB) applications.

Couples of different groups are working on setting up standards for use of this wide spectrum.

Two standards occupy most of the markets now. One of which is based on the pulse-wave

transmission, which transmit ultra short pulses (ultra-wide bandwidth) as digital signals. These

kinds of systems were used in sensor applications or radar applications for military purposes.

The other group of people is trying to modify the existing mature standards people use on

wireless communication and fit them into ultra-wideband systems so that the developing time










might be shorter. One of the most important standards come out is the use of multi-band OFDM

signals [46]. This alliance adapted the mature OFDM technology that is used in IEEE 802.11Ia

and 802. 11Ig. First of all, the whole ultra-wideband is divided into several narrower bands, and

each narrow band signals are transmitted using the OFDM modulation. The transmission data

rate of this specification is ranged from 53 Mbps to 480 Mbps depends on the coding schemes

and operating distances.



Table 5-2.. Center frequencies plan for OFDM UWB
Band Group 1 2 3 4 5
BAND ID 1 2 3 4 5 6 7 8 9 1() 11 12 13 14
Center Freq 3432 396() 4488 5()16 5544 6()72 66()( 7128 7656 8184 8712 924() 9768 1()296
(1VHz)




3980 MHz 5544 MHz 7128 MHz 8712 MHz 10296 MLHz
-528 MHz +528 MHz -58528 MHz +528 MH28 Mz +2Mz -528 MHz +528 MHz -528 MHz





SBand Group 1 Band Group 2 Band Group 3 Band Group 4 Bn ru


Figure 5-6. Frequency plan chart of the OFDM UWB.



The whole 3-10 GHz band is divided into 14 sub-bands. Each sub-band has bandwidth of

528 MHz. Table 5-2 lists all the central frequencies of each of sub-bands and Figure 5-6

illustrates the frequency planning of this OFDM UWB system. The 14 sub-bands are categorized

into five groups. Band group 1 is mandatory when developing MB-OFDM devices and other

four band groups are optional. The use of those four bands is reserved for future use and it has

more flexibility when designing the devices. Most of the developments in this system today are










maj or focused on band group 1 because at lower frequencies chips could be made on mature and

cheap CMOS technology. Switching between the frequency bands is controlled by the time

frequency coding. The time frequency coding provides frequency diversity gain and robustness

to interference.

The maximum distances at which the multi-band OFDM system can achieve package error

rate of 8 % for a 90 % link success probability are listed in Table 5-3. The testing was done

under different channels from all white Gaussian Channel (AWGN) to channels with large delay

spread. The operating distances are in the range of 10 meters, which is far enough for short range

high data rate transmission systems such as the linking the DVD player to a digital television.



Table 5-3. Operating distances for OFDM UWB system with different channel conditions and
date rate

LOS : -4m NLOS : -4m NLOS :4-10m RMS delay spread :
Range AWGN
CM 1 CM2 CM3 25ns CM4
110 Mbps 21.4m 12.0m 12.0m 11.5m 10.9m
200 Mbps 14.6m 7.4m 7.1m 7.5m 6.6m
480 Mbps 9.3m 3.2m 3.0m N/A N/A



Figure 5-7 illustrates timing diagram of band switching operations between the different

sub-bands of an MB-OFDM UWB system. It is noticed that the guard interval, which also equals

the transition time between bands to bands, has only a period of 9.5 ns. There are several ways to

achieve frequency hopping for a frequency synthesizer at this kind of speed. First is the use of

ultra fast settling time phase-lock-loops (PLLs). The second method is to use multiple PLLs and

select outputs from different PLLs when the center frequency has to be changed. Third, using up-

conversion mixers, down conversion mixers, and switches in combination to make the selection










of frequencies fast. A briefing on how the previous designs were done for such a frequency

synthesizer will be given in the following sections.


9.5 ns Guard Intenral for
Tx/Rx Switching
f+792
Band #3
f+264
312.5 ns
Band #2
f-264
Band #1


Frequency Period 937.5ns Tirne
(MHz)

Figure 5-7. Frequency hopping diagram between the different bands.


5.2.1 PLL with an Ultra Fast Settling Time

PLL is usually implemented as a frequency synthesizer in a communication system

because of its capability to generate a stable output frequency. Since the 528 MHz frequency

resolution in MB-OFDM UWB systems is pretty wide, the use of integral-N frequency

synthesizers would suffice.



S PFD I
LoFilter I

VCO


Divider



Figure 5-8. Block diagram of an integral-N frequency synthesizer.



Figure 5-8 shows the block diagrams of an integral-N frequency synthesizer. Basic

operation of an integral-N frequency synthesizer could be briefly described as follows. The










divider divides the frequency of VCO output signal N times and compares its phase with the

input reference clock in phase frequency detector (PFD). PFD generates pulses if there are phase

differences between the two signals. Pulses from PFD are filtered through a low pass loop filter

and generates a control signal which the magnitude is determined by the amount of phase

difference. The control signal then controls the output frequency of the VCO. Phases of signals

after the divider and the input reference clock would be locked through negative feedback, and

this also guarantees the output signal frequency would be exactly equal to N times the frequency

of the input reference signal.


Charge Loop
PFD Pump Filter VCO
SIcp H(f) k out



Divider





Figure 5-9. Block diagram with mathematical modeling of integral-N PLL.



Figure 5-9 shows the block diagram of an integral-N PLL with frequency domain model of

each block [47]. For a second order, type-II frequency synthesizer, the frequency domain transfer

function is:

1 1+s/w
H(s) = (5-4)
sC 1+s/wp


,where C is determined by the values of the capacitors in the loop filter and wz and w, are zero

and pole frequencies in the transfer function.

The open loop gain is










KI pH (s)
A(s) = (5-5)
ircNs


,and the closed loop gain is


~out A(s)
= G(s) = (5-6)
1+ A(s)



Closed Loop Step Response 1 1 PA L op Fr quec fl F pon

I llll~~~~~~




02 3
IIj



-02 0~ 2 4 0 6 0 8 1 12 1 4 116 1 8 Z 0 10 10 1 in 101
Time (seconds) x 108 Frequency (Hz)
(a) (b)

Figure 5-10. Settling behaviors of (a) a step response, and (b) closed loop frequency response, of
a fast switching PLL.



Settling behavior and stability analysis could be got from these equations. Figure 5-10

shows the closed loop step response and the closed loop frequency response. These graphs were

generated using PLL Design Assistant software by Michael Perrott from MIT. This PLL has

settling time about 10 ns. However, the cutoff frequency which determines the 3 dB roll off point

in the frequency response is at 500 MHz. Reference frequency is typically about 10 times higher

than the cutoff frequency and it will lead the reference frequency as high as 5 GHz. The

implementation with a reference signal running at 5 GHz would usually consume a lot of power

on CMOS chips and make this solution unattractive since the phase detector and charge pump











circuits would not work very well at this high frequency unless they draw huge current. Also,

from Section 5-1, it can be seen that it is extremely difficult to have a VCO running through all

the UWB bandwidth. Therefore, the traditional integral-N PLL methodology is out of

consideration while designing UWB frequency synthesizers.

5.2.2 Switching Between Multiple PLLs



Vu Band Slect

-~i~ 0-36dB
th Order
,7 SK Filler

Band 0-14 dB
Select
Gain 1s IIit-Order
Switlch 1 PLL IPILG PUl.. Bla sie
Band

inkc ths o cnt

quradrature




Figure 5-11. A MB-OFDM UWB frequency synthesizer using multiple PLLs in [48].



Since the traditional PLLs are not fast enough to satisfy the timing requirement of MB-

OFDM UWB system as shown in the previous section, one of the straight forward way is to use

several PLLs running at different frequencies and select from them using the switches in a


frequency synthesizer. For example, if three frequency bands are required, three PLLs will be

implemented and switched between each other in a frequency synthesizer according to digital

control signals. In [48], Razavi etc. presented a three-band MB-OFDM UWB frequency


synthesizer. Figure 5-11 shows the block diagram of the implementation. Three PLLs are shown

in the block diagram. Selecting time between them is fast enough to satisfy the requirement of

the specification. This design only generates the three frequencies in group 1 bands. If more










frequency bands have to be implemented in the design, then more than three PLLs have to be put

on the same chip. In the standard, 14 bands are spreads over 3- to 10-GHz. Using this

architecture, 14 PLLs have to be implemented, which is unrealistic and the whole chip area will

be bulky and consumes a lot of power.





Frequency 93. n / 4:1 MUX select

II Q I
4488 I1II
S3125 ns -2+

3432 I I

-c tTime 2Mi
9.5 ns Iref clock
Chnerld select
(a) (b)

Figure 5-12. A IVB-OFDM UWB frequency synthesizer using two swapping PLLs. Illustrations
of (a) timing diagram, and (b) simplified block diagram, in [49].



A smart way to reduce the number of PLLs is to effectively utilize the time between each

symbol for PLL to reach its steady condition. Figure 5-12 [49] illustrates one of the

implementations of this idea. The transition of two switching bands is 9.5 ns, which is too short

for a PLL to response. However, the symbol period of 312.5 ns is long enough for a PLL to

stabilize. Two PLLs are used alternatively in this synthesizer. While one PLL is set to a certain

frequency, the other PLL has already started to tune to the next frequency. Therefore, the settling

time is relaxed from 9.5 ns to about 320 ns which greatly reduce the speed requirements of a

PLL with the use of one extra PLL.










5.2.3 Switching Between Different Frequencies Using Mixers

The most popular scheme used in the designing of UWB frequency synthesizers is to use

mixers to switch between different bands. Since mixers are not used in feedback systems like

PLLs, the settling time only depends on the loading capacitances and the currents to charge them.

A useful architecture is the use of single-side-band (SSB) mixers that can generate two bands,

one of up-side band and one of lower-side band. As a result, mixers are extensively used in the

multi-band OFDM UWB frequency synthesizers. Figure 5-13 illustrates two of the

implementations from [50] and [51] using mixers in frequency synthesizers. Through careful

frequency planning and proper design, only one PLL is necessary in the frequency synthesizer.

In [5 1], several different frequency plans using this kind of technique are proposed, and the

publication gives us an idea of the trade-offs between different schematics.



+2 *y 2
3960MHz 3432MHd
3%ounzr Slsthed Buffer
7920MHs 4488MIIz
SSB miner
4 HTY pLL 5 23MHzl I -5 gMHi fGg gg 26dG 2 1
+3+ + 52sunz (r. 2 + 2 +2' +

nevu y O.Sel. Select +2C 60 +2 30


(3rd harm)
Signal Conditioner--'I Swltahed Buffer

(a) (b) t~neou

Figure 5-13. Two implementation of MB-OFDM UWB frequency synthesizers in (a) [50], and
in (b) [51].



5.3 The Proposed OFDM UWB Frequency Synthesizer

The main problem in using single-side-band mixers in a frequency synthesizer is the

spurious tones generated from the mixers. While using a PLL, the spectrum of the output signal

is a pure sinusoidal wave. However, signals from a mixer suffer from the nonlinearities of the










mixer itself. The output signal will not be a clean sinusoidal signal but a signal with large

harmonic terms and intermodulation terms. Spurious signals in a frequency synthesizer would

degrade bit error rate (BER) performance comparing to pure sinusoidal waves.

Under most conditions, spurious signals are far away from the target frequencies and they

could be easily filtered out. However, in MB-OFDM UWB frequency synthesizers, filters with

very wide tuning range have to be designed since the whole frequency span is 7 GHz wide. A lot

of filters might necessary be implemented either on chip or off chip. Therefore, the most serious

problem about designing a MB-OFDM UWB frequency synthesizer is to clean the output

spectrum.

5.3.1 Effect of Spurious Signals in Frequency Synthesizers on BER performance

In order to get the ideas of how spurious signals affect BER performance of a MB-OFDM

UWB system, simulation is performed in Agilent Advanced Design System (ADS). Figure 5-14

illustrates the diagram of spurious signals generated from a frequency synthesizer. Signal at fo is

the desired LO frequency; signals at f, and fi are the upper-side band spurious signal and lower-

side band spurious signal which are mainly generated due to the nonlinearity of mixers. The

desired frequency has signal amplitude of 0 dB, which is a reference to the spurious signals and

the spurious signals have the signal amplitude of -A dB.


OdB



-A dB -A dB


fi fo f,

Figure 5-14. Spurious signals of a frequency synthesizer.











Figure 5-15 shows the simulation block diagram of the effect on BER due to spurious

signals in a MB-OFDM UWB system. In this simulation, direct conversion receiver is assumed

since this architecture is easier to be integrated on a single chip without many external


components. UWB OFDM function blocks generate OFDM signals through IFFT, and then the

signals are up-converted to the RF frequency using spurious contaminated LO signals. In this

simulation, three transmitters are added together to represent the input signal to the receiver. The

transmitter in the center represents the desired signal with LO at frequency fo, and the other two

transmitters represent interference signals due to spurious tones from LO at frequency fh and fi.


Spurious signals have following gain stages of -A dB. At the receiving end, input signals with

interference are down-converted to baseband through a down-converting mixer and a LO at


frequency fo. Baseband signal is further processed by FFT and the data are recovered. BER

detector detects the error due the interference made by spurious tones in the frequency

synthesizer.


I
I
I
I


Figure 5-15. Simulation diagram of effect on BER due to spurious signals in a frequency
synthesizer.










Figure 5-16 shows the simulation results of BER performance versus signal to noise ratio

with different signal levels of spurious tones in the frequency synthesizer. BER degradations due

to the spurious signals are compared with the perfect OFDM system. It can be shown while

interference gets larger, BER degrades more as expected. Assume that only Idb degradation in

BER is acceptable due to interference tones so that the whole system performance does not

change a lot. This figure indicates that at least 25 dB of suppression to the desired signal on

spurious signal is necessary.



10'








10~ + BER/ No interference
+ BER/ Interference 25dB lower
+ BER/ Interference 20dB lower
+ BER/ Interference 15dB lower
lo0 + BER/ Interference 10dB lower

S2 4 6 8O~B 10 12 14


Figure 5-16. Simulation result of BER with various spurious signal levels.


However, the scheme in the simulation above is optimistic. In a communication system,

usually the interference's magnitude is much higher than the desired signal's magnitude because

the interference could be much closer to the receiver. From the specification [46], transmitted

power of a MB-OFDM UWB signal is set to have a limit of -9.9 dBm. While the OFDM UWB

system is set in the highest speed mode, the sensitivity of the receiver is -80.5 dBm, which is

measured when the transmitter and receiver are 10 meters away. Assume that the interference is









put 1 meter away from the receiver. Under the condition of line of sight (LOS), the path loss of

the interference signal is 44.2 dB. Therefore, the input signal strength of the interference signal is

-54.1 dBm (output power-path loss at 1 m = -9.9 dBm 44.2 dB). In order to make the system

work, the interference signals with input signal level of -54.1IdBm and the desired signal with

signal level of sensitivity(-80.5 dBm), the down-converted signals still have to satisfy the 25 dB

suppression from the conclusion of previous section. Therefore, the spurious LO signal from the

frequency synthesizer should be 51dB lower than the LO signal (-54.1 dBm + spurious level

suppression < -80.5 dBm 25 dB). Figure 5-17 illustrates the testing environment that described

above. As a summary, the spurious signals from the frequency synthesizer should be more than

50 dB lower than the desired LO signal.


1 meter



Interferencel1

10 meter
1 meter Receiver


U7 17

Transmitter Interference2

Figure 5-17. Testing environment of the spurious signal test.


5.3.2 Scheme of Frequency Generation

The frequency generating plan has to be made. This depends on how many frequency

bands are planned to be generated and how many PLLs will be implemented. Table 5-4 lists all










the frequencies that are defined in the MB-OFDM UWB standard. Each band has 528 MHz

interval between each other. After some simple mathematical manipulation, it is found out that

all of the frequencies are the multiples of 264 MHz, and the ratios between the LO frequency and

264 MHz are shown in the table. Therefore, 264 MHz seems to be a good choice as the reference

frequency. If 264 MHz is used as the reference frequency, the only problem is that the

frequencies are all odd multiples of the reference frequency. In circuit design, divide-by-2 is

easier to be implemented in IC at high frequencies, thus these frequencies could not be generated

directly using the reference signal.



Table 5-4. Relation of LO frequencies of different bands
Center Freq (MHz) 3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296
N (Freq +264M) 13 15 17 19 21 23 25 27 29 31 33 35 37 39



The easiest way to generate all the listed frequencies is to use 528 MHz as a reference and

make it multiply certain times to the output frequencies. Since it is easier to generate a frequency

that is even multiple times of the reference frequency, the wanted frequencies are generated

through up- or down-converting mixers. The scheme is shown in Figure 5-18.

The frequency generating scheme is shown in Figure 5-18. Fourteen frequencies are

divided into four groups, and each group contains four frequencies except the last group which

contains two frequencies. In this design, only the frequencies in the first three groups will be

generated. The central frequency of each group will be generated at first, and the four

frequencies will be made through mixers by adding or subtracting either 264 MHz or 792 MHz.

VCO generates the central frequency of group three at 8448 MHz through a PLL with the

reference frequency of 528 MHz. The center frequency of group one comes out after a divide

8448 MHz by two. As for the center frequency of group two, it is generated by adding the center










frequency of group one and group three and then divides it by 2. This scheme is easily

implemented with the only use of mixers, divide-by-2 circuits, and switches.


I Group 1 | Group 2 Group 3 Group 4


~I I I~f I


3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296


1528x8 58 10 1528x121 58 14 528x161 581
I___ J1 I_ ]_ I ]__
528x7 528x9 528x11~ 528x13 528x15 528x17 528x19
SVCO
Divide-by-2




Divide-by-2


Figure 5-18. Scheme of the frequency generation for a MB-OFDM UWB frequency synthesizer.



5.3.3 Block Diagram of the Frequency Synthesizer

Figure 5-19 is the block diagram of the proposed frequency synthesizer. Output frequency

of the PLL is set to be 8448 MHz. After it divides by two, 4224 MHz which is the center

frequency of group 1 appears. Up-converting mixer mixes 4224 MHz and half of 4224 MHz and

generates 6336 MHz which is the center frequency of group 2. A three inputs' selector switched

between the different central frequencies. Four frequencies in each band groups are generated by

up-converting or down-converting mixers using 792 MHz and 264 MHz signals which are also

generated on chip through the dividers. In this way, there are 3 times 2 times 2 which is 12

different frequencies will be generated from this frequency synthesizer.





























Figure 5-19. Block diagram of the IVB-OFDM UWB frequency generator.


5.4 Spurious Signals from the Frequency Synthesizers

Some nonlinear properties of the mixer and the signals leaking through the selectors or

silicon substrate cause spurious signals which will degrade the performance of recovering the

data. Some of the mechanism of spurious signals will be discussed below.

5.4.1 Spurious Signals from Mixers

Figure 5-20 shows some of the possible spurious signals that occur at the output of a mixer.

The RF input of the mixer is at frequency wl and wl'; the LO input is at frequency w2. wl' is

cause by the leakage of the selector and the isolation of the selector equals to sel(dB). From the

output, except the desired output at frequencies of w2+wl and w2-wl, it also contains several

other frequency components. LO signals is leaking to the output with amplitude A2-IsoLO (dB),

where IsoLO is the isolation of the mixer, at frequency w2. The mixing of the leaking signal

from the selector and the LO with amplitude of G (Al-sel), where G is the gain of the mixer. The

rest signals in Figure 5-20 are third-order products, e.g. w2-(2wl'-wl) caused by the mixer.










Al A1G A1G
G(Al-sel) G(Al-sel)
Al-sel A-sL

wl' w1 A2II I I I I
ri="ir:w2-wl w2-wl' w2 w2+wl' w2+wl
w2~n~-(2l-l' w2(2l-w)w2(wl-l)w-(w-w'
w2

Figure 5-20. Spurious signals from a mixer.



The methods that we used on the frequency synthesizer are listed as follow:

1. Sub-harmonic mixers are used so that the frequency of LO leakage is far away from the

desired frequency.


2. Third-order nonlinearity has to be reduced. Therefore, passive mixers are used instead

of active mixers with the trade-off of the converting gain.


3. The imbalance of the quadrature signals in the single sideband mixers.


4. The odd-order harmonics of the square waves which are generated from the digital

dividers or buffers.


5.4.2 Sub-harmonic Mixers

In this design, sub-harmonic mixers are used instead of fundamental mixers in order to

reduce the LO leakage and other higher order spurious signals. Demonstration of a CMOS sub-

harmonic mixer is in Chapter 4. Figure 5-21 reviews the operating of a subharmonic mixer.

Figure 5-21 (a) shows the schematic of the load of a subharmonic mixer. With the shifting

between the LO signals with different phases as shown in Figure 5-21 (b), the outcome is like

using an LO frequency that is twice as its real frequency.

The Use of subharmonic mixers greatly separates the frequency distance of LO frequency

and output frequency. For example, if the output frequency needed is at 8712 MHz, for a










fundamental mixer the LO should be at 8448 MHz which is very close to 8712 MHz; for a

subharmonic mixer the LO will be at 4224 MHz. Under this circumstances, the LO leakage

would not be a problem since the spurious signals could be easily filtered away.

However, using subharmonic mixers adds the complexity in the design. We need multiple

phases of the LO signals for the use of mixers. Normally, subharmonic mixers need four phases

of the LO signals. However, for up-converting mixers or down-converting mixers, four extra

phases are necessary since single side band mixers need I- and Q-quadrature signals. As a result,

totally eight phases have to be generated on chip.


LO 00

RF+C D r IF+


LO 1800


LO_900-1 ~ LO_2700 LO_900-1 -~ LO_2700


LO 00


IF C (a) (0 RF



Figure 5-21. Load of a subharmonic mixer.



Also, in order to reduce the inter-modulation terms from the mixers, mixers with higher

linearity are preferred. Basically there are two categories of mixers: active mixer and passive

mixer. Passive mixers usually have higher linearity compared to active mixers. Therefore,

passive mixers are chosen to be used in the frequency synthesizer design because of its better

linearity .









5.4.3 Filtering Out the Spurious Signals

The other source of the spurious signals is from the single-side-band (SSB) mixers. While

quadrature signals are fed into the SSB mixer, the imbalance in the amplitude and phase of the

input signals and the imbalance in the mixer gain and phase will make the cancellation of the

other side band imperfect.

The block diagram of a SSB is shown in Figure 5-22 [52]. A SSB mixer is composed of

two identical mixers. These two mixers are fed with quadrature signals of wl and w2. In the

figure, Oz, 62, >1, and A2 TepfeSent the imbalance in phase and in magnitude. These imbalances

might come from the quadrature signal generator or the mixer itself, or the combination of the

two.


The output signal could be represented as

OUT = cos(wzt) cos(w2t~ ( )1 2 B)Sin(wzt + 0)sin(w~t + 2) (5-7)

Scos(w, + w2 )t + cos(w, w2 t (1+ 2,+)[Sin(W~t) + 8, cos(w,t)][sin(w2t) 2, COS(W2t
Scos(w, + w2 )t + cos(w, w2 )t f (1+ 2A )[cos(w, + w2)t cos(w, w2 )t + 0 cos(w,t) sin(w2t
+ 02 COS(W~t) sin(w2t~
S2 cos(w, f w2 )t + 2A cos(w, T w2)t + (1 + 2A)[20 sin(w, + w2)t + 20 sin(w, w2 t
S2 cos(wl f w2 )t + 2A cos(w, T w2)t + 20[sin(w, + w2)t + sin(w, w2)t] (5-8)


In equation (5-8), only the first term is the wanted signal, and the rest terms are the

spurious signals from the imbalance of the circuitry. It shows that while the upper-side-band

mixer is designed, lower -side-band signal component also exists, and vice versa. The power

ratio between the signals to spurious signals ratio from (5-8) is


Pow[cos(w, +w2)]
(5-9)
Pow[cos(w, w2 )t 2 + 2










Figure 5-23 illustrates (5-9), showing the signal power ratio between the wanted signal and

the un-wanted signal, which is isolation, of a SSB mixer due to the imbalanced inputs. The

numbers on the graph shows the isolation in dB. With typical imbalance ofA = 5%,0 = 5", the

signal ratio is

Wanted 1
= 94 = 20dB (5-10)
Un wanted 0.052 +0.092


cos(wzt)
cos(w,t)
cos(w t) cos(w',t)+
900
(1+ A)(1+A,) sin(wt t+ B)sin(wt t+0 8)


(1+ A ) sin(v',t + 9,)
(1+ A,) sin(w,t + 82 )


Figure 5-22. Single-side-band mixers with imbalanced inputs.



Obviously, this isolation is not good enough for this frequency synthesizer. If 30 dB of

isolation is necessary, amplitude imbalance has to be within 3% and phase imbalance has to be

within 2o. There are two ways to solve this problem, one is to reduce the imbalance from the

quadrature generator and the mixers, and the other one is to use filtering at the post processing at

the output of the SSB mixer to filter out the unwanted bands. Calibration is usually implemented

on chip to increase the quadrature accuracy. However, the digital control part is pretty complex.

As for the filtering, if the two bands are close with each other, then a filter with very high-Q

value is necessary, which is also unavailable on chip. However, if the two bands are far away,

then filtering might be a good choice to reduce the output spurious signals.















25 15
023 0 20






4 -0 3 -0.2 -0 1 0 0.1 02 0.3 04
Amp Imbalance


Figure 5-23. Signal isolation of SSB mixer due to imbalanced inputs.




1LP HPF


(a) (b)

Figure 5-24. Filter (a) upper-side-band, and (b) lower-side-band, of the outputs of a SSB mixer.



The two scenarios of filtering a SSB mixer are shown in Figure 5-24. If the output is

selected to the lower-side-band, then a low pass filter (LPF) in Figure 5-24(a) has to be used to

filter the higher frequency; if the output is selected to the upper-side-band, then a high pass filter

(HPF) in Figure 5-24(b) has to be used to filter the lower frequency. Therefore, two kind of

filters need to be implemented, a LPF and a HPF, and a switch is necessary to switch anyone of

them depends on which side band is wanted. Also, multiple orders of the LPFs and HPFs might

be needed if the isolation requirement is stringent.

It seems the straightforward way filtering using LPFs and HPFs are a little bit complex and

not efficient. Poly phase filter might be very useful in this kind of situation. Although the idea of










polyphase filters was proposed decades ago, the gain of popularity was after [53] and [54], which

designed receivers and mixers using polyphase filters on chip to obtain the performance of high

image rej section.



~L~ ~~-r 01 i

8 02 bl, b3 c3 c4 dl, d2,
a2 d3, d4
v4 P~~ 03 i2 i4a
c2 cl
84, ~~Vc 04 ab2, b4b bc
(b) a3

(a) Unbalanced Input (b)

Figure 5-25. A polyphase filter's diagrams of (a) schematic, and (b) signal components.


Polyphase filters utilize the Hilbert Transform so that it is able to filter the negative

frequency. Negative frequency here physically means the phase of the input frequency. Figure 5-

25 (a) illustrates the schematic of a polyphase filter. Multiple phases of the inputs are inserted

into the filter. Mathematically, four input signals could be represented as a superposition of four

orthogonal basis functions as shown in Figure 5-25(b). As shown in the figure, an unbalanced

input could be decomposed into the combination of groups of signals with different phase

relationship, which are counterclockwise signal components (ai in the figure), anti-polar

components (bi in the figure), clockwise signal components (ci in the figure), and a dc

component (di in the figure). These four components also form the basis functions of the

incoming signal set. The polyphase filter will only passes the counterclockwise components and

filters out the clockwise component. As for the signals of bi and di, they can be eliminated

through sensing the outputs differentially. This special property of the poly phase filter makes it










very useful in filtering the image signal since the image signal has the different phase

relationship with the wanted signal.


OutI+

OutQ+

DutI-

~~to-


::Z


~LOO
I
~ L900
2

VL1 80"

VL270"
I
I
I


0 5 10 15 -15 -10 -5 0
freq, GHz freq, GHz


Figure 5-26. Simulation result of a three-stage polyphase filter.


A test on a polyphase filter is made in the ADS software. Figure 5-26 shows the simulation

results of the filter. It is a three-stage polyphase filter, and the filter frequency is set to be about -

10GHz. The left graph shows the filtering response for only a one-stage filter. It can be see that

the roll of at -10GHz is sharp to about -80dB with perfect components. However, due to the

variation in the components on chip and the bandwidth requirement, higher-order filters are used.

Right graph shows the filtering response of the three-stage polyphase filter. It shows that the

filtering is so deep to -100 GHz at around -10 GHz.

Figure 5-27 shows the simulation schematic of a single-side-band mixer with a post

polyphase filter filtering the image signal. There are 50 phase difference and 5% amplitude















































ml0

m11

mi1
ind Delta=5.280E8
-100- /dep Delta=-24.434
deta mode C
-150-

-200-


5 6 7 8 9 10 11 12 13 14 1


difference in the mixer and the quadrature generator. From Figure 5-28, it shows that without the


polyphase fi1ter, the isolation of the image frequency and the wanted frequency is about -24 dB.

With the polyphase fi1ter, the isolation increases to -40 dB. This is 15 dB improvements due to


the polyphase fi1ter.










sinw,,t cosII / o_, smnwzot




-1-

Polyphase




Figure 5-27. Polyphase fi1ter with a single-side-band mixer.


freq, GHz


. -7


freq, GHz


Figure 5-28. Simulation results show the effect of a polyphase fi1ter.



5.4.4 Square Wave Harmonic Reduction

The other source of spurious signals from a frequency synthesizer is from the harmonics of


square waves. Figure 5-29 shows three of the lower orders of the harmonics. After doing Fourier









transform of a square wave, odd order terms come out. The amplitudes of these terms are 1/3, 1/5

for 3rd order and 5th order, respectively. Since the signals from dividers and inverter buffers are

all square waves, these harmonics are needed to be filtered out since it would cause spurious

signals in a frequency synthesizer.

Figure 5-30 shows the square wave effect on a SSB mixer. Here, only the 3rd order and 5th

order terms are considered since they are closer to the output frequency and their amplitude are

the bigger than higher order terms. As in the figure, for a lower-side-band mixer, the 3rd, 7th,

11Ith... Orders of the IF signal will be appear on the upper side, and 5th, 9th, 13th ... Orders will

be appear on the lower side. Since polyphase filters are put after the SSB mixers, we can check if

the filter can filter the spurious terms due to these harmonic terms. Since four phases are needed

for a polyphase filter, for a lower-side-band mixer, the wanted RF frequency would be

cos(w,t) cos(wLt) + sin(wet) sin(wLt) = cos(wLO ~ t (5-11)

cos(wl~t>sin(wot) -sin(wl~t) cos(wot) = sin(wo IF >t (5-12)


for in-phase signals and quadrature signals. Note that these signals are differential, therefore

there are totally four signals from these equations and they will be the inputs to the polyphase

filter. For the 3rd order harmonic, the output terms will be


cos(3wl~t) cos(wot) sin(3wl~t) sin(wot) = cos(wo + 3wlF)t (5-13)

cos(3w,t) sin(wLt) + sin(3w,t) cos(wLt) = sin(wLO + 3w, )t (5-14)







T '1 3 5 ~
Ts Ts Ts


Figure 5-29. Harmonics of a square wave.



































0 0 1 "I I '


1. -

,, _: I I i I C I


1St order


cos(w,,t) +
cos(; n,,t)+
cos(wLOt
cos(5wat)


wLo-9wlF
900


sin(wet) + sin(w,,o
-sinc:a i)+
sin(5w,t)I

Figure 5-30. Effect of square wave harmonics on SSB mixers.


WLO"IF WLo+7wlF


cos(wo T w;,)t +
COS(Wo + 3wz,)t +
cos(wzo+T5wz,)t


1.


(b)


L'C-


0 2 4 6 8 10
time, nsec


Figure 5-31. Square waves with different 450 phase differences and the resulting waveform after
summation.



The equation (5-13) and (5-14) show the output components of a SSB mixer due to 3rd

order harmonic term from the IF. The filtering of a polyphase filter comes from the different


phase relationship between the wanted signal and the spurious signal. Comparing these equations,

it could be seen that the phase relationship are the same for both the wanted signals and spurious


signals. Although the equations are for the 3rd order terms, they could also be modified for

higher order terms. Therefore, polyphase filters could not filter the spurious signals coming from


)(ca









the harmonics of the IF signals. Some other methods have to be implemented to reduce these

harmonics.

The straight forward way is still to put a filter after the SSB mixer. However, for the same

reason, the filter has to be high-Q if the frequency separation is narrow. The other way that we

can use is to reduce the harmonics using the methods in [55] and [56].


a(t) = [(cos(wt) sin(wt)) + 1(cos(3wt) + sin(3wt)) -1(cos(5wt) sin(5wt))] (5-15)
~i3 5

b (t)= 2[cos( wt) 1cos(3wt)+ cos( 5wt)] (5-16)


c(t) = [(cos(wt) + sin(wt)) + 1(cos(3wt) sin(3wt)) 1(cos(5 wt) + sin(5wt))] (5-17)
~i3 5

d(t) = a(t) +b(t) +c(t) = A os~n I)I (5-18)


The harmonic reduction circuitry sums a square wave with different phases to cancel out

3rd and 5th order terms. Figure 5-3 1 illustrate the operation of harmonic cancellation circuit. As

shown in the figure, three phases with 450 phase deviation are necessary. Equations (5-16), (5-

17), and (5-18) shows the Fourier series up to the 5th order term. They represent square waves

with phases of -450, Oo, +450, respectively. Once these three terms are added, the summation of

them is as (5-19) and Figure 5-31. It can be seen that it perfectly canceled out the 3rd order and

5th order terms from a square wave in the trade-off that multiple phases of square waves are

needed. The spectral result of the harmonic canceling circuit is shown in the right graph of

Figure 5-31. It is clear that 3rd and 5th order are ideally gone.

5.4.5 Implementation of a Harmonic Reduction Circuit

For a harmonic reduction circuit, not only quadrature signals are necessary, but also signals

with 450 phase. There are several ways to get multiphase signals. The easiest way is to use

differential ring oscillators as shown in Figure 5-32 [57]. However, the frequency limitation of










ring oscillator is usually not very high. In this frequency synthesizer, the oscillator needs to be

run at almost 5GHz. Therefore, ring oscillator is not a good choice here.


Figure 5-32. Using ring oscillator to generate multiphase signals.



Another way to generate multiphase signals is to use frequency dividers. A divide-by-2

circuit could generate quadrature signals of the incoming signal. Figure 5-33 shows a CMOS

divider proposed in [58]. From the figure, the phase relationships of the outputs are noted on the

graph and it is known which node has zero phases and which node is quadrature and so on. In

other words, the phase relationships with each other are well determined through a divide-by-2

circuit.


100


2700


Figure 5-33. Use a divider to generate quadrature signals [58].


As mentioned earlier, 450 phase has to be used in the harmonic reduction circuitry.

Therefore, two dividers could be cascaded to provide those phases as shown in Figure 5-34. If

multiple phases of frequency f are needed, the input signal of the first divider should be at










frequency four times of f The in-phase and quadrature phase signals from the first stage divider

drive the latter stages of dividers, and each latter divider will generate four phases. Using this

way, it can get eight phases from the divider chain.



-900
Divider
-180"
-270o
INI Divider

-900

-2700'





2T
4T

Figure 5-34. Cascade dividers for 450 phase difference.



However, only the phase relationships of the four local inputs from one divider can be

determined. There are no internal feedback mechanism let us know the relationships between the

two dividers at the output. For example, if one node of a divider is set to be as zero degree, then

any of the four outputs of the other divider could have 450 phase difference compared to the zero

degree one. For harmonic reduction circuit, the exactly relationship of the phases have to be

determined. Therefore, extra testing circuits have to be added to test the phase relationship

between the output nodes.

Figure 5-35 lists the waveforms of signals with eight different phases. The relationships of

these phases are shown clearly on this figure. Four signals from the top half graph are from the

first divider, and four signals from the bottom half graph are from the second divider. Since the

relationship between the two dividers is unknown, testing has to be done. One of the easiest ways










is to use Oo and 900 signals as sampling signals on all the four phases from the second divider. As

shown in Figure 5-35, the sampling results of these phases are different. Therefore, simple logic

circuit could be used to distinguish which one has only 450 phase difference to the reference of

Oo. The circuit implementation is straightforward as shown in Figure 5-36.







900
Divider 1j



2700







Divider 22 1




3150 11,



Figure 5-35. The phase detection circuitry.


D Q


Test IN 0 yCLK Control



D Q-

900
SCLK


Figure 5-36. Phase detection circuit after divide-by-2 blocks.


142










5.5 Schematics and Simulation Results

Figure 5-37 shows the overall schematics of the MB-OFDM UWB frequency synthesizer.

In this section more detailed simulation results and schematics will be shown. There are four

control signals that set the output frequency. Two bits of the control signals determine which

frequency would be selected from the big switch shown in Figure 5-37, one bit of the control

signal sets the upper side band mixing or lower side band mixing, and the remaining one bit sets

the IF mixing frequency whether be 264 MHz or 792 MHz.


QVCO
8448MHz


SH SSB Polyphase


LPF


Harmonic Rejection

Figure 5-37. Schematic of the MB-OFDM UWB frequency synthesizer.



The chip is designed and simulated using an UMC digital 90nm low-k CMOS technology.

Only two passive spiral inductors are implemented on the chip using 3-metal stacked round

shape inductor discussed in Chapter 2.










Figure 5-3 8 shows one of the simulation results. In the Eigure, the graph shows the

switching moment between two frequencies. The control signal is changed at time equals to 50

ns. Before 50 ns, the running frequency is at 4.488 GHz, and after 50 ns, the signal is running at

7.656 GHz. It can be seen that the transition time is extremely short. It only takes about 3 ns for

the frequency synthesizer to switch from one band to the other.


200







O

-100


-200
49 52 55 58
Time (ns)

Figure 5-38. Simulation results showing the transition time switching from one band to the other.


From the time domain signals, it can be seen that spurious signals exist to corrupt the

waveform of the output signals. It is important to see what the spectral components of these

signals are. Figure 5-39(a) and (b) shows the spectrum of the signal before and after the

frequency transition of the frequency synthesizer. As shown in the spectrum, some of strong

spurious tones exist. These are mainly due to the non-ideal mixers and the harmonics of the

square waves. However, due to the fi1ters added in front of the 264 IVHz and 792 IVHz signals,

the spurious tones are far away from the wanted signal. All of the signals are at least 1 GHz away

from the desired frequency. These spurious tones could be easily removed using filters in the










receiver chain or the transmitter chain. Therefore, these spurious tones should not cause too

many problems.

5.6 Conclusions

At the beginning of the chapter, a switching band VCO was designed and measured.

Although the VCO achieves wide tuning range, it can not be used in an UWB frequency

synthesizer because of the lack in the frequency covering range from 3 to 10 GHz. Therefore, a

low spurious MB-OFDM UWB frequency synthesizer is proposed. This frequency synthesizer

has capability of generating 12 out of the 14 bands that are described in the UWB standard. It

utilizes techniques such as sub-harmonic mixers, harmonic reduction circuits, and polyphase

filters, to purify the output signal. The chip is designed using UMC CMOS 90 nm technology.

However, at the time of defense, this chip is not completed. This chip has to be done in the future

by other members in the RFSOC group.




Frequency 1 Frequency 2 (i
0 -4.488GHz 7.656GHz





-20
a, -20-



-30
-40-

-40 > -50
0 3.33 6.67 10 0 3.33 6.67 10
Frequency (GHz) Frequency (GHz)
(a) (b)

Figure 5-39. Simulation results showing (a) the spectrum of the signal before the transition, and
(b) the spectrum of the signal after the transition.









CHAPTER 6
SUMMARY AND FUTURE WORKS

6.1 Summary

Wideband wireless communication system (e.g. Ultra-Wideband system) is becoming

popular for its capability to achieve high data rate wireless transmission. With the progress on

CMOS technology in recent years, it could achieve comparable performances at high frequencies

to other compound materials (e.g. GaAs) but with much lower cost. Therefore, implementing

wideband circuits using CMOS technology has become one of the most important topics in the

RF circuit design.

In this study, several wideband CMOS circuits along in the receiver chain were designed

and tested using various novel technologies. Wideband LNAs utilizing a modified resistive

feedback topology were demonstrated. All of the LNAs were measured with package and ESD

protection diodes using digital 90 nm CMOS technology. These LNAs could be used in UWB

devices or multiband receivers. Three wideband LNAs are designed and tested. Different

requirement in the bandwidth of the LNA results in different gain. The trade-off between the

gain-bandwidth is also examined. LNAl has a bandwidth of 9 GHz and a voltage gain of 17 dB.

The noise figure is within 4 dB to 6 dB from 1 GHz to 7 GHz. LNA 2 achieves a bandwidth of

3.2 GHz with 22 dB of voltage gain. The noise figure of the LNA is ranging from 1.8 dB to 3 dB

from 1 GHz to 3 GHz. LNA3 uses an active inductor load to achieve a small chip area. The LNA

has a bandwidth of 8 GHz with a voltage gain of 16 dB. Noise figure is ranging from 3 dB to 5.5

dB from 1 GHz to 8 GHz.

Next, two CMOS passive mixers were designed and tested. One of the passive mixers

achieves very wide bandwidth for UWB devices. The passive mixer has conversion loss of 6.5

dB from 1 GHz to 10 GHz. For linearity, input PldB is about 5 dB and IIP3 is about 11 dBm.










Also, in order to implement the passive mixer in a direct conversion receiver, problem of LO

feed-through could be solved by using a harmonic passive mixer. It is also implemented using

0.18 Clm CMOS technology. For this mixer, the measured voltage conversion loss is about 6 dB.

Also, the signal source and the IQ generation circuitry were designed on chip to reduce the

components counts externally.

Other than the CMOS technology, GaN devices are also in the interests for researchers.

The special property of the GaN device is that it can handle large power for its high break down

voltage. Models of the GaN devices in linear region were created. Behavior of conversion loss

with LO power is well predicted using the developed model. Three down-conversion mixers

were designed for RF frequency of 1.7 GHz and IF frequency of 200 MHz using LO frequency

of 1.9 GHz. GaN HEMT devices with gate width of 300 um, and gate lengths of 1.2, 1.0, and

0.75 um were used in the mixers.

Finally, the voltage controlled oscillators (VCOs) and frequency synthesizers were

considered and designed. A switching band VCO achieving 20% of tuning range for 3 GHz and

5 GHz was demonstrated. Switching inductors and capacitors were used to change the oscillating

frequencies. Next, a frequency synthesizer used for MB-OFDM UWB system was designed. The

synthesizer generates 12 bands ranging from 3 GHz to 10 GHz using subharmonic mixing

technique. Various spurious reduction methods were implemented to reduce the interference

caused by the spurious signals.

6.2 Future Works

The UWB frequency synthesizer is not finished at the point of graduation. Due to its

complexity, it needs couple of more tape outs to make it realized in CMOS technology. This task

will be followed by other members from RFSOC lab. The techniques that are used in the

frequency synthesizer can also be used in other applications such as a system to remotely detect









of the heartbeats and respirations [59]. With the structure proposed in this dissertation, the

making of a frequency hopping frequency synthesizer can be easier.

After demonstrations of the concepts on each block in a wideband receiver, a system level

design has to be considerate thoroughly. These blocks, like mixers, VCOs, LNAs, and frequency

synthesizers, could be used in the design of wideband systems including MB-OFDM UWB

system or wideband software configurable radio front end. However, the whole system

integration will be a design into another level that whole team of engineers have to work on, and

it will not be in the scope of this PhD study.










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PhD Dissertation, University of Florida, Spring 2007.









BIOGRAPHICAL SKETCH

Tienyu Chang received the B.S. degree in electrophysics from National Chiao Tung

University, Hsingchu, Taiwan, R.O.C., in 2000, and the M. S. degree in electrical engineering

from National Taiwan University, Taipei, Taiwan, R.O.C., in 2002. He is currently working

toward the Ph.D. degree in electrical engineering at the University of Florida, Gainesville,

Florida, USA.

His research interests are in the areas of radio-frequency/millimeter-wave integrated

circuits and analog circuits.





PAGE 1

1 DESIGN OF WIDEBAND COMM UNICATION CIRCUITS By TIENYU CHANG A DESSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2008

PAGE 2

2 2008 Tienyu Chang

PAGE 3

3ACKNOWLEDGMENTS I would like to express my deepest gratitude to my advisor Dr. Jenshan Lin. He provides me a research environment with free thinking and he lets me to explore what my interests are. Without his support and guidance, I can hardly fi nish this doctorial study. I would also like to thank my committee members, Dr. Rizwan Bashir ullah, Dr. William Eisenstadt, and Dr. Fan Ren. They gave me a lot of precious comments dur ing the defense and proposal to make my study more complete. I specially tha nk Mrs. Wenhsing Wu for her help during the first couple of years fabrication and bond-wiring the GaN devices; and Dr Fan Ren for his generous offering of his lab equipments for testing and bond wiring. For the several years that Ive lived in Florida, I would like to thank al l of my lab mates for their companies and supports. Some of them ar e already graduated (Xiu ge Yang, Yanming Xiao, Ashok Verma, SangWon Ko, and Hyeopgoo Yeo), and so me of them are stil l here (Lance Covert, Mingqi Chen, Fu-Yi Han, Zhen-Ning Low, Changzhi Li, Yan Yan, Austin Chen, and Mingkai Mu). Of course, there are some visitors fr om Taiwan (Ching-Ku Liao, Chih-Ming Wang, and Jian-Ming Wu). With them, I had a great time here in Florida. I would like to thank my parents, my br other and sister for their un-conditional encouragement and supports. At last, in several y ears, my love Yu-Ping Huang has taken care of me and supported me no matter what. Th is dissertation bel ongs to all of you.

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4TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................3 LIST OF TABLES................................................................................................................. ..........7 LIST OF FIGURES................................................................................................................ .........8 ABSTRACT....................................................................................................................... ............14 CHAPTER 1 INTRODUCTION..................................................................................................................16 1.1 A Brief Historical Sketch of Ultra-Wideband (UWB) Technology.................................18 1.2 Brief Review on UWB Technology.................................................................................18 1.2.1 Pulse-Based UWB Systems....................................................................................19 1.2.2 Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB.....20 1.3 Design Challenges and Scope of This Study....................................................................21 1.4 Outline of the Dissertation................................................................................................24 2 PASSIVE COMPONENTS....................................................................................................25 2.1 Inductors.................................................................................................................. .........25 2.1.1 In CMOS 0.18 m Technology..............................................................................25 2.1.1 In CMOS 90 nm Technology.................................................................................26 2.2 Capacitors................................................................................................................. ........30 2.3 Varactors.................................................................................................................. .........31 3 DESIGN OF WIDEBAND LOW NOISE AMPLIFIERS (LNAs)........................................34 3.1 Topology Survey............................................................................................................ ..34 3.1.1 Bandpass Filter Input Matching.............................................................................35 3.1.2 Distributed Amplifier.............................................................................................36 3.1.3 Common Gate Amplifier........................................................................................38 3.1.4 Resistive Feedback Amplifier................................................................................38 3.2 Theoretical Analysis....................................................................................................... ..39 3.2.1 Basic Structure of Resis tive Feedback Amplifiers.................................................39 3.2.2 R-C Feedback through a Source Follower.............................................................41 3.2.3 Input Gate Feedback Inductor................................................................................45 3.2.4 Active Inductor Load..............................................................................................47 3.2.4 Noise Analysis........................................................................................................49 3.2.5 Bond Wires and ESD Diodes.................................................................................51 3.2.6 Neutralization Capacitors.......................................................................................53

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53.3 Circuit Design of Proposed LNAs....................................................................................53 3.3.1 TSMC Digital 90 nm CMOS Technology..............................................................54 3.3.2 ESD Diodes............................................................................................................54 3.3.3 LNA 1.................................................................................................................... .55 3.3.4 LNA 2.................................................................................................................... .57 3.3.5 LNA 3.................................................................................................................... .58 3.4 Measurement Results of Proposed LNAs.........................................................................59 3.4.1 The Resistive Load UWB LNA (LNA 1)...............................................................60 3.4.2 The High Gain Wideband LNA (LNA 2)...............................................................63 3.4.3 The Active Inductor Load UWB LNA (LNA 3)....................................................66 3.5 Conclusions................................................................................................................ .......69 4 DESIGN OF WIDEBAND PASSIVE MIXERS....................................................................71 4.1 GaN Passive Mixers.........................................................................................................71 4.1.1 Modeling of GaN Transistor s in the Linear Region...............................................72 4.1.2 Design of GaN Resistive Mixers............................................................................75 4.1.3 Measurement Results..............................................................................................76 4.2 CMOS Passive Mixer.......................................................................................................80 4.2.1 Discussion on CMOS Resistive Ring Mixer..........................................................80 4.2.2 Design of CMOS Resistive Ring Mixer.................................................................84 4.2.3 Simulation and Me asurement Results....................................................................86 4.3 CMOS Passive Harm onic Pumped Mixer........................................................................90 4.3.1 Discussions on Each Block....................................................................................91 4.3.2 Measurement Results of the Resistive Harmonic Mixer......................................100 4.4 Conclusions................................................................................................................ .....102 5 CONSIDERATION AND DESIGN OF AN UWB FREQUENCY SYNTHESIZER.........105 5.1 A Switching Band Voltage Controlled Oscillator (VCO)..............................................105 5.1.1 Design of the Switching Band VCO....................................................................106 5.1.2 Experimental Results............................................................................................110 5.2 Introduction to MB-OFDM UWB Frequency Synthesizers...........................................113 5.2.1 PLL with an Ultra Fast Settling Time..................................................................116 5.2.2 Switching Between Multiple PLLs......................................................................119 5.2.3 Switching Between Different Frequencies Using Mixers....................................121 5.3 The Proposed OFDM UWB Frequency Synthesizers....................................................121 5.3.1 Effect of Spurious Signals in Freque ncy Synthesizers on BER performance......122 5.3.2 Scheme of Frequency Generation........................................................................125 5.3.3 Block Diagram of the Frequency Synthesizer......................................................127 5.4 Spurious Signals from th e Frequency Synthesizers........................................................128 5.4.1 Spurious Signals from Mixers..............................................................................128 5.4.2 Subharmonic Mixers............................................................................................129 5.4.3 Filtering Out the Spurious Signals.......................................................................131 5.4.4 Square Wave Harmonic Reduction......................................................................136 5.4.5 Implementation of a Ha rmonic Reduction Circuit...............................................139 5.5 Schematics and Simulation Results................................................................................143

PAGE 6

65.6 Conclusions................................................................................................................ .....145 6 SUMMARY AND FUTU RE WORKS................................................................................146 6.1 Summary.................................................................................................................... .....146 6.2 Future Works............................................................................................................... ...147 REFERENCES..................................................................................................................... .......149 BIOGRAPHICAL SKETCH.......................................................................................................154

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7LIST OF TABLES Table page 1-1 Various data rates of the MB-OFDM UWB system..........................................................22 3-1 Measured performance compar ed with prior published works..........................................70 4-1 Summary of the GaN resistive mixers...............................................................................79 4-2 Summary of the III-V resistive mixers from existing publications...................................80 4-3 Summarize of the fundamental passive mixer and the subharmonic passive mixer........104 5-1 Performance summary of the band switching VCO........................................................113 5-2 Center frequencies plan for OFDM UWB.......................................................................114 5-3 Operating distances for OFDM UWB syst em with different channel conditions and date rate...................................................................................................................... ......115 5-4 Relation of LO freque ncies of different bands................................................................126

PAGE 8

8LIST OF FIGURES Figure page 1-1 WPAN technologies with different usable range and data rate.........................................17 1-2 FCC regulation of UWB spectral ma sk for indoor communication systems.....................19 1-3 UWB pulse waveforms......................................................................................................20 1-4 Spectrum utilizing plan for the MB-OFDM UWB system................................................20 1-5 Scope diagram of this doctorial research...........................................................................23 2-1 Cross section diagram of a TSMC 1P 6M 0.18 m mixed-mode CMOS process.............26 2-2 Physical diagram of a di fferential inductors in HFSS.......................................................27 2-3 Model used for differential inductors................................................................................27 2-4 Fitting results of a differential inductor in 0.18 m CMOS..............................................28 2-5 Side-view of a multi-layered i nductor in a 90 nm CMOS technology..............................28 2-6 HFSS diagrams of a stacked differentia l inductor in a 90 nm CMOS technology with w=6 m, r=130 m, and s=2 m.HFSS diagram of a stacked differential inductor in a 90 nm CMOS technology................................................................................................29 2-7 Simulation results of a 2 nH differen tial inductor in a 90 nm CMOS technology............29 2-8 MIM capacitors graphs.....................................................................................................30 2-9 Top views of an interdigital capacitor...............................................................................31 2-10 Cross section of an A-MOS varactor.................................................................................32 2-11 Simulated capacitance values versus bi asing voltages of an A-MOS varactor.................32 2-12 Cross-section view of an I-MOS varactor.........................................................................33 2-13 Simulated capacitance values versus bi asing voltages of an I-MOS varactor...................33 3-1 Results of an input matching wi deband LNA from Bevilacqua, etc.................................35 3-2 Results of the distributed LNA..........................................................................................36 3-3 Results of the common gate LNA......................................................................................37 3-4 Results of the resi stive feedback LNA...............................................................................39

PAGE 9

93-5 Basic structure of a resi stive feedback amplifier...............................................................40 3-6 Schematic of a resistive feedback amplifier feeding b ack through a source follower.......41 3-7 Small signal equivalent model of the circuit in Figure 3-6................................................42 3-8 Simulation results of the effects of load capacitance CL on input impedance for a resistive feedback amplifier...............................................................................................43 3-9 Simulation results of the effects of Cf on input impedance for a resistive feedback amplifier...................................................................................................................... .......44 3-10 Schematic of a resistive feedback amp lifier feeding back with a peaking inductor inside the feedback loop.....................................................................................................46 3-11 Trajectories of pole locat ions with increasing value of gate inductor in resistive feedback amplifier.............................................................................................................47 3-12 Simulation results of the voltage gain versus frequency using equation (3-7)..................48 3-13 An active inductor loads graphs.......................................................................................48 3-14 Frequency response of magnitude of input impedance......................................................49 3-15 Equivalent model of wideband LNAs input stage with package and ESD diodes added.......................................................................................................................... ........51 3-16 Smith Chart of S11 simulation results from DC to 15 GHz................................................52 3-17 Layout of ESD diodes...................................................................................................... ..54 3-18 Schematic of LNA 1 (biasing circuits not shown).............................................................55 3-19 Schematic of LNA 2 (biasing circuits not shown).............................................................57 3-20 Schematic of LNA 3 (biasing circuits not shown).............................................................59 3-21 Chip photo of LNA1 (ar ea=0.58mm x 0.22mm with pad)................................................60 3-22 Measurement (solid line) and simulation (dashed line) results of voltage gain for LNA1........................................................................................................................... ......61 3-23 Measurement (solid line) and si mulation (dashed line) results of S11 for LNA1..............61 3-24 Measurement results of S22 and S12 for LNA1...................................................................62 3-25 Measurement (solid line) and simulation (dashed line) results of NF for LNA1..............62 3-26 Measured linearit y results for LNA1.................................................................................63

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103-27 Chip photo of LNA2 (ar ea=0.56mm x 0.42mm with pad)................................................64 3-28 Measurement (solid line) and simulation (dashed line) results of voltage gain for LNA2........................................................................................................................... ......64 3-29 Measurement (solid line) and si mulation (dashed line) results of S11 for LNA2..............65 3-30 Measurement results of S22 and S12 for LNA2...................................................................65 3-31 Measurement (solid line) and simulation (dashed line) results of NF for LNA2..............66 3-32 Measured linearit y results for LNA2.................................................................................66 3-33 Chip photo of the LNA 3 (a rea=0.38mm x 0.36mm with pad).........................................67 3-34 Measurement (dotted line) and simulation (dashed line) results of voltage gain for LNA3........................................................................................................................... ......67 3-35 Measurement (dotted line) and simulation (dashed line) results of S11 for LNA3...........68 3-36 Measured results of S12 and S22 for LNA3......................................................................68 3-37 Measurement (dots) and simulation (d ashed line) results of NF for LNA3......................69 3-38 Measured linearit y results for LNA3.................................................................................69 4-1 Die photo of one of the GaN HEMT devices with a device area of 200 m x 1 m.........72 4-2 Equivalent circuit model used for GaN HEMT devices....................................................73 4-3 Modeled Rds versus gate bias on GaN devices with different gate lengths.......................74 4-4 Measured and simulated conversion loss versus LO power for GaN devices with different gate lengths......................................................................................................... .75 4-5 Schematic of the single-FET resistive mixer.....................................................................76 4-6 Photo of the GaN mixer board...........................................................................................77 4-7 Measured conversion lo ss versus RF frequency................................................................78 4-8 Measured conversion loss versus RF power......................................................................78 4-9 Two-tone IIP3 measurement result of the GaN resistive mixers.......................................79 4-10 Schematics of the resistive mixer......................................................................................81 4-11 Conversion loss versus frequency of CMOS resistive mixers with different gate lengths........................................................................................................................ ........82

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114-12 Schematic of the wideband resistive ring mixer................................................................84 4-13 Chip photo of the fabricated mixer (chip size including the pads: 0.95 mm x 0.65 mm)............................................................................................................................ ........85 4-14 Measurement and simulation results of conversion loss versus RF frequency with fixed IF frequency 500 MHz..............................................................................................86 4-15 Input P1dB and IIP3 versus RF frequency........................................................................88 4-16 Measurement results of conversion loss versus LO power. The measurements were conducted for ten RF frequencies from 1 GHz to 10 GHz................................................88 4-17 Measurement results of the RF return loss from 100 MHz to 12 GHz..............................89 4-18 Measurement results of the NF of the wideband passive mixer........................................89 4-19 Systematic blocks of the subharmonic mixer with an integrated VCO.............................91 4-20 A 5 GHz VCOs diagrams.................................................................................................92 4-21 Schematic of a current mode divide-by-2 circuit...............................................................93 4-22 Simulation results of th e divider input and output.............................................................94 4-23 Variation of channel resistance..........................................................................................94 4-24 Variation in conductance.................................................................................................. .95 4-25 Schematic of a resistive harmonic double balanced mixer................................................96 4-26 Transient simulation of input and output...........................................................................96 4-27 Output spectrums of the subharmonic mixer.....................................................................98 4-28 Different RF input biasing leve ls with differential LO signals..........................................99 4-29 Simulation results of a subharmonic passive mixer with different RF bias conditions.....99 4-30 Die photo with an area of 0.85mm 0.7mm...................................................................100 4-31 Effects of RF bias on the conversion loss of the mixer...................................................101 4-32 Measurement and simulation results of conversion gain of the mixer............................101 4-33 Measured LO leakage to the IF and RF ports with varying LO frequency.....................102 4-34 Measured P1dB, IIP2, and IIP3 of the passive subharmonic mixer................................103

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125-1 Schematic of the switching band VCO............................................................................107 5-2 Schematic of resonant tank..............................................................................................109 5-3 Die photo of the switching band VCO.............................................................................110 5-4 Measured conversion loss versus offset frequency..........................................................111 5-5 The tuning capability of the switching band VCO..........................................................112 5-6 Frequency plan chart of the OFDM UWB.......................................................................114 5-7 Frequency hopping diagram be tween the different bands...............................................116 5-8 Block diagram of an integr al-N frequency synthesizer...................................................116 5-9 Block diagram with mathemati cal modeling of integral-N PLL.....................................117 5-10 Settling behaviors of a fast switching PLL......................................................................118 5-11 A MB-OFDM UWB frequency s ynthesizer using multiple PLLs...................................119 5-12 A MB-OFDM UWB frequency synt hesizer using two swapping PLLs..........................120 5-13 Two implementation of MB-OFD M UWB frequency synthesizers................................121 5-14 Spurious signals of a frequency synthesizer....................................................................122 5-15 Simulation diagram of effect on BER due to spurious signals in a frequency synthesizer.................................................................................................................... ....123 5-16 Simulation result of BER with various spurious signal levels.........................................124 5-17 Testing environment of the spurious signal test..............................................................125 5-18 Scheme of the frequency generation for a MB-OFDM UWB frequency synthesizer.....127 5-19 Block diagram of the MB-O FDM UWB frequency generator........................................128 5-20 Spurious signals from a mixer.........................................................................................129 5-21 Load of a subharmonic mixer..........................................................................................130 5-22 Single-side-band mixers with imbalanced inputs............................................................132 5-23 Signal isolation of SSB mixe r due to imbalanced inputs.................................................133 5-24 Filter of the output s of a SSB mixer................................................................................133 5-25 A polyphase filters diagrams..........................................................................................134

PAGE 13

135-26 Simulation result of a three-stage polyphase filter..........................................................135 5-27 Polyphase filter with a single-side-band mixer................................................................136 5-28 Simulation results show the effect of a polyphase filter..................................................136 5-29 Harmonics of a square wave............................................................................................137 5-30 Effect of square wave harmonics on SSB mixers............................................................138 5-31 Square waves with different 45o phase differences and th e resulting waveform after summation...................................................................................................................... ..138 5-32 Using ring oscillator to generate multiphase signals.......................................................140 5-33 Use a divider to gene rate quadrature signals...................................................................140 5-34 Cascade dividers for 45o phase difference.......................................................................141 5-35 The phase detection circuitry...........................................................................................142 5-36 Phase detection circuit after divide-by-2 blocks..............................................................142 5-37 Schematic of the MB-OFDM UWB frequency synthesizer............................................143 5-38 Simulation results showing the transition time switching from one band to the other....144 5-39 Simulation results showing the spectrum of the signal before the transition, and the spectrum of the signal after the transition........................................................................145

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14Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DESIGN OF WIDEBAND COMM UNICATION CIRCUITS By Tienyu Chang May 2008 Chair: Jenshan Lin Major: Electrical and Computer Engineering The wideband wireless communication system (e.g. Ultra-Wideband (UWB)) is becoming popular for its capability to achieve high data ra te wireless transmissi on. With the progress on CMOS technology in recent years, it could achieve comparable performances at high frequencies to other compound materials (e.g. GaAs) but with much lower cost. Therefore, implementing wideband circuits using CMOS t echnology has become one of the mo st important topics in the RF circuit design. In this study, several wideband CMOS circui ts along a receiver chain were designed and tested using various novel desi gn techniques. Low noise amplifie rs (LNAs) are one of the most critical components in a receiver design. Three LNAs were designed and measured using a 90 nm CMOS technology. The LNAs adopt a modifi ed resistive feedback topology for wideband input matching and gain-bandwidth extension. Al l of the LNAs were measured with chip-onboard package and electrostatic discharge (ESD) protection diodes at all the ports. Two of the LNAs were designed for the UWB application and one of the LNA was designed for the multiband application. Tradeoffs between the noise figure (NF), bandwidth, and gain will be demonstrated in the proposed LNAs.

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15Mixers are also of focus in this doctorial research. Several wideband passive mixers were designed and tested. At first, boa rd level mixers using GaN devi ces were designed and measured. GaN devices have the property of high breakdown voltage. Therefore, they can be used in high power and high linearity applications. The transist ors were modeled specially in the linear region to accurately estimate the performance of the passive mixers. Three passive mixers were fabricated using GaN HEMT transistors with different gate lengths The results show good linearity performance. Next, two passive mixers were designed and tested using a 0.18 m CMOS technology. A fundamental passive mixer and a sub-harmonic passive mixer were made. The fundamental passive mixer achieves a very wide bandwidth for UWB devices. The sub-harmonic passive mixer utilizes the second harmonic of the local oscillator (LO) signal achieving a high LO-IF leakage. The chip includes a sub-harmonic mixer, a voltage controlled os cillator (VCO), and a quadrature generation circuitry. Finally, a wideband VCO and a UWB frequency s ynthesizer were considered and designed. The switching band VCO implemented in 0.18 m CMOS achieves a tuning range from 3 GHz to 5 GHz. Switching inductors and capacitors were used to change the oscillating frequencies. Next, a frequency synthesizer used for the multi-band orthogonal frequency division multiplexing (MB-OFDM) UWB system was designe d. The simulated synthesizer can generate twelve bands ranging from 3 GHz to 10 GHz usi ng the sub-harmonic mixing technique. Various spurious reduction methods were implemented to reduce the interference s caused by the spurious signals.

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16CHAPTER 1 INTRODUCTION Wireless communication has already b ecome part of our life in the 21st century. It started from the cell phones in the late 20th century. At the time, only the voice data is transmitted wirelessly through cell phones. Now people are tryi ng to get every kind of digital data, from a text message, to a voice clip, and even to a m ovie with a high resolution HDTV format, to be transmitted through the air, Because the differences in the natures of the signals transmitting, several standards have to be set up for each special needs. One of which is for the Wireless Personal Area Network (WPAN). It focuses on the development of short distance wireless networks. These networks address wireless networking of portable and mobile computing devices such as PCs, PDAs, peripherals, cell phones and consum er electronics. Depending on different requirements on the transmission speed and operating range, standard s that could be chosen from are list in Figure 11. While the operating range needs to be high, we have standard IEEE Wireless Local Area Network (WLAN) 802.11a/b/g/n (e.g. WiFi) worki ng for us. While the data rate and operating range is lower, but ultra-low power is needed to extend the battery life time, Bluetooth is at the help. As for extremely high data rate transmi ssions of hundreds of mega bytes per second, UltraWideband (UWB) comes into play. Because of the uniqueness in th e extreme high data rate tran smission comparing to other communication systems, the transceiver design of the UWB systems is very different with the rest of narrow band based communication systems and it posts a lot of interests on the design of UWB circuits. Therefore, wideband wireless (e specially UWB) communicating systems will be the main focus in this dissertation among all the wireless communications.

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17 Figure 1-1. WPAN technologies with di fferent usable range and data rate. The goal of an UWB system is to provide a short range but high data rate wireless transmission. The first application of UWB tec hnology is to replace the cables that connected between machines in the offices or home. Cables are always bothering people for their easily get tangled up. However, UWB is not just a cable replacement technology. W ith the help of UWB technology, all of them could be connected togeth er wirelessly. With th e connectivity, we have the ability to control all the equipments at the sa me time and make them working with each other. UWB could change the way we use our elec tronic products. In the age of wireless communication and interconnectivity, the UWB communication system will be integrated into PCs. Mobile phones and handheld devices, digital cameras and camcorders as well as all many of the consumer electronics and home entertai nment systems. Using the UWB technology, they will be able to share multimedia cont ent with very large amount of data. Range (m) Data Networking 802.11a/b/g/n 802.11n promises 100Mbps @ 100m Quality of service, streaming Room-range High-definition UWB Bluetooth UWB Short Distance Fast download 110Mbps @ 10m 480Mbps @ 2m 200Mbps @ 4m 1000 100 10 1 1 10100 Source: Texas InstrumentsData Rate (Mbps)

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181.1 A Brief Historical Sketch of UWB Technology It was started at Feb 14, 2002 when Federal Communications Commission (FCC) allocated 7500 MHz of spectrum for unlicensed use for UW B devices in the 3.1 to 10.6 GHz frequency band [2]. Prior to January 2003, the IEEE conducted study groups to investigate the possibility of pursuing a standard based upon the new spectrum. The IEEE 802 committees setup a new 802.15.3a committee put out a call for proposals to develop WPANs. Because of the large number of proposals makes th e selection process slow. After couple of meetings and discussions, two proposals are left to be decided. One of which is based on Multiband OFDM technology a nd the other is based on direct sequence technology. Because the fundamental technologies of the two standards are quite different, the supporters on each side could not set a final c onclusion. Furthermore, because UWB needs to be operated over extremely short range, it is particular ly vulnerable to interference. As a result, the process became jammed for years. Finally, the OFDM supporters el ected to continue the work on standardization outside of the IEEE 802.15.3a task group. This out side group gradually forma lized their relationship and started an organization called Multiband OFDM Alliance (MBOA). Eventually this group became known as the WiMedia Alliance. As a re sult, technical specification development and certification and interoperability activities are unified in the WiMedia Alliance. On January 2006, after three years of a jammed process in IEEE 802.15.3a, supporters of both proposals supported the shut down of the IEEE 802.15.3a task group without conclusion. 1.2 Brief Review on UWB Technology The power spectral emission mask of the UWB systems by FCC is illustrated in Figure 1-2. The regulation allows spectrum sharing with low emission limit (-41.3 dBm/MHz Equivalent Isotropically Radiated Power (EIRP)) where the transmitted signal doesnt cause harmful

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19interference to others. An UWB system is defi ned as any devices that emits signals with a fractional bandwidth more than 0.2 or a bandw idth of at least 500 MHz at all time of transmissions. There are two popul ar standards implementing UWB si gnals, one is to generate a short pulse with wide bandwidth, and the othe r one is to use Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM). Figure 1-2. FCC regulation of UWB spectra l mask for indoor communication systems. 1.2.1 Pulse-Based UWB Systems The earliest radio implemented in the late 19th century and 20th century was the pulsebased impulse radio. Spark gaps and arc discharg es between carbon electrodes were the principal mechanisms to produce radi o signals in the early 20th century. The pulse-based UWB signal and its spectrum ar e shown in Figure 1-3. An extremely short pulse of few nano-seconds has its spectrum cr ossed over very wideband. The spectrum width could be controlled by transmitting pulses with different pulse durations. The signal could be

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20modulated using several different ways incl uding pulse-position m odulation (PPM), pulseamplitude modulation (PAM), on-off keying (OOK) and binary phase-shift keying (BPSK). The whole UWB spectrum could be also divided into several groups as a multiband system to reduce interference using methods similar to frequency hopping radio. The main advantage of pulse-based UWB system is that the transmitter has a very simple design. Its disadvantages are that it is difficu lt to collect significant multi-path energy using single RF chain; and the system is very sensi tive to group delay variati ons introduced by analog front-end components. Figure 1-3. UWB pulse waveforms in (a) ti me domain, and in (b) frequency domain. 1.2.2 Multiband Orthogonal Frequency Divi sion Multiplexing (MB-OFDM) UWB Figure 1-4. Spectrum utilizing plan for the MB-OFDM UWB system. -10 -5 0 5 10 -0.5 0 0.5 1 Time (ns)Mag (V) 0 2 4 6 8 10 -40 -30 -20 -10 0 Frequency (GHz)Mag (dB)(a) (b)

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21The standard MB-OFDM UWB utilizes all or part of the spectrum between 3.1-10.6 GHz and supports data rates of up to 480 Mb/s. As shown in Figure 1-4, the whole UWB spectrum is divided into 14 bands, each with a bandwidth of 528 MHz. The first 12 bands are then grouped into 4 band groups consisting of 3 bands, and the last two bands are grouped into a fifth band group. This multi-band technique could be used to separate the application of UWB systems to avoid interference. The well known OFDM techni que is implemented on this UWB system. A total of 110 sub-carriers (100 data carriers and 10 guard carriers) are used per band. In addition, 12 pilot subcarriers allow for coherent detec tion. Frequency-domain spreading, time-domain spreading, and forward error co rrection (FEC) coding are provided for optimum performance under a variety of channel conditions. The transmitting data rate is scalable from 55 MB/s to 480 MB/s. In realistic multi-path environments, 110 Mb/s of data transmission coul d be operated within 10 meters in distance; 200 Mb/s could be operated within 4 meters in di stance; and 480 Mb/s could be operated within 2 meters. Table 1-1 shows operating modes with different transmitting data rates of the MBOFDM UWB system. The data rate could be calculated from FsymNIBP6S/6, where Fsym is the symbol rate which is 3.2 Msym/s for the system. This MB-OFDM UWB standard is getting mo re and more popular compared to the previous pulse-based UWB system. Therefore, MB-OFDM UWB system will be the research topic in this PhD study. There are many good introduc tory papers, such as [4], [5], and [6], describing the channel and the hard ware of a MB-OFDM UWB system. 1.3 Design Challenges and Scope of This Study The transceiver of a wideband communication syst em is very different from that of the conventional narrow band systems. First of all, th e design of wideband RF blocks is harder than narrow band blocks, such as amplifier. Electroni c theory tells us the gain-bandwidth product is

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22about constant. For circuits with higher bandwidth, the gain w ould be smaller than narrow band ones. Therefore, multiple stages might have to cascade to boost up the gain so that the power consumption would be higher. Performance of lo w cost CMOS technology is not fast enough to have sufficient gain in the higher gigahertz regi on. Cost always plays the dominant role in which technology will survive. In order to operate at that high frequency, usually huge power consumption is needed and a lot of inductor pe aking is necessary, which makes the chip size bigger and the cost of fabrication higher. Becau se of this reason, most attempted commercial UWB products are still focused on Mode 1, whic h covers the part of the UWB frequency bandwidth, with frequency ra nge from about 3 to 5 GHz. Table 1-1. Various data rate s of the MB-OFD M UWB system. Second, because of the property in the wide fr equency bandwidth, the interference is more serious where the spurious tones fall inside the signal spectrum. The regulation from FCC states that the power density is small compared to ot her narrowband systems, which means there will be strong out-of-band blockers. Also, the UWB c overs the 5 GHz band which has application as IEEE 802.11a. There will be some coexisting issues th at have to be dealt with. Some techniques are used to overcome the interf erence problem such as notchi ng out certain band as in [7].

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23Third, the fast frequency hopping is difficult to deal with. In the standard, 9 ns transition time is required switching from one band to another. Traditional PLLs could not stabilize in this short period of time. Switching be tween PLLs is another way. However, more area and more power consumption are necessary. Other possibili ties of frequency synthesizing techniques are like using direct digital synthesizer (DDS). However, the capability of using CMOS to implement DDS is still questionable. Figure 1-5. Scope diagram of this doctorial research. For most of the papers about MB-OFDM UWB systems so fa r, only the first frequency bands from about 3 GHz to 5 GHz are focused on [8]. This shortens the UWB products coming out time since it has simpler structure compared to devices covering all the bands. However, the challenging wideband components and system specifi cations are still needed to obtain for future developments. The works in this dissertation are trying to solve some of the problems mentioned before. First, some of the RF components, in cluding LNAs, mixers, and VCOs, are designed to be wideband for use in an UWB system. Band Control LNA Antenna A/D 90o A/D Chap 3 Chap 4 Chap 5

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241.4 Outline of the Dissertation This dissertation describes the works on se veral wideband component s that the author designed. In first part of Chapter 2, discussion on some of the passive components that will be used in the circuits is given. In the latter part, a CMOS wideband VCO is developed using switching inductors and capacitors. Chapter 3 states about wideband LNAs. Introductory on CMOS wideband LNA is first given, and then a new type of wideband LNA is proposed. Three LNAs were fabricated with different bandwidth and gain. In Chapter 4, several kinds of mixers are discussed. First, an on board passive mixe r using direct band-gap device GaN was designed using transmission lines for high linearity and high power applications. Next, a CMOS wideband passive mixer covering UWB frequency range is proposed. At last, a CMOS subharmonic wideband passive mixer is proposed and measur ed. Chapter 5 discusses about the frequency synthesizer used in a MB-OFDM UWB sy stem. A multi-band VCO utilizing switching resonance tanks is introduced. The insufficiency in the tuning range of the VCO leads to the design of a mixer-based frequency synthesizer. Th e synthesizer is used to generate 12 bands ranging from 3 GHz to 10 GHz using the subharm onic mixing technique de scribed in Chapter 4. Chapter 6 is the conclusions and future works.

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25CHAPTER 2 PASSIVE COMPONENTS On chip passive components that are often us ed in the RF integrated circuits include inductors, capacitors, resistors, and varactors. At higher frequencies where the wavelength becomes comparable to the chip size, transmission lines can be used in substitute of discrete capacitors and inductors. In this section, inducto rs, capacitors, and varators will be described. Two kinds of technologies are mainly used in this research, 0.18 m CMOS and 90 nm CMOS. Descriptions of the passive components will be subdivided based on the technology if the structures of them are different. 2.1 Inductors 2.1.1 In CMOS 0.18 m Technology Figure 2-1 shows the cross section of a TS MC 1P6M 0.18 m mixed-mode CMOS process chip. Although it is from TSMC, the UMC 0.18 m mixed-signal CMOS process is mostly similar to the TSMC one except minor differences in the thicknesses of dielectric layers and metal layers. In the mixed-mode process, metal six is made extra thick of about 2 m in thickness. Usually this metal layer is used as high power trace line since it has better capability in transferring signals with higher power dens ity compared to other thin metal of 0.5 m thick. The IR drop would also be smaller since it has smalle r resistance per unit length. Also, this metal is usually used for on chip inductors since it has lower sheet resistance fo r a high-Q inductor. The simulation of inductors is done in H FSS from Ansoft Corpor ation. UMC provides a convenient template for HFSS that we could use it to get the inductance value and the Q-value. Figure 2-2 shows the physical st ructure in HFSS simulation. Using HFSS, two-port S-parameters are obtained. In order to use th e inductor in time-domain simula tion software such as SPICE of Cadence Spectre, lumped model has to be crea ted. Figure 2-3 shows the lumped equivalent

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26circuit of the differential inducto r. This circuit is then put in to Agilent ADS design system and using it to fit the S-parameters obtained from HFSS. Figure 2-4 demonstrates one of the fitting results of a differential inductor up to 20 GHz us ing the lumped equivalent model. Two curves match pretty well. Figure 2-1. Cross section diagram of a TSMC 1P6M 0.18 m mixed-mode CMOS process. 2.1.1 In CMOS 90 nm Technology Some of the designs in this proposal are in digital 90 nm CMOS process. For the pure digital process, there is no thick metal layer as in 0.18 m for high-Q indu ctors. Fortunately, for the 1P9M (one poly and nine metal layers) process that we used, there are a lot of metal layers for us to use from. Hence, multiple layers of metal could be stacked together to form an equivalent thick metal for inductor. As of the 0.18um CMOS, the stacked inductor is also designed using HFSS.

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27 Figure 2-2. Physical diagram of a differential inductor in HFSS. Figure 2-3. Model used fo r differential inductors. Figure 2-5 shows the side-view of a multi-layered differential inductor. For either UMC or TSMC 1P9M digital CMOS 90 nm processes, M9 has thickness of about 8 kA meters; M8 and M7 have thicknesses of 5 kA meters. Vias are us ed extensively to connect the layer from M7 to M8 and from M8 to M9. The equivalent thickne ss is greatly increased so that the series resistance of the inductors will decrease and th e Q-value will increase. The trade-off of using stacked layers of metal layers is that the parasitic capacitance of such an inductor will be larger compared to the one using thick metal layer. Body Ind1 Ind2 CM

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28 Figure 2-4. Fitting results of a differential inducto r in 0.18 m CMOS of (a) S11 in Smith Chart, (b) S21 in polar diagram, (c) magnitude of S11, (d) magnitude of S21, and (e) inductance and Q values. Figure 2-5. Side-view of a multi-layere d inductor in a 90 nm CMOS technology. 2 4 68101214161820 0 22 -10 -5 0 5 10 -15 15 0 5 10 -5 15Freq (GHz) L (nH) Q -30 -20 -10 -40 0 S11 ( dB ) Freq (GHz) 2 4 6 8 10 12 14 16 1820 0 22 S11 Freq (0.1 to 20.1 GHz) S21 1.0 0.6 0.2 -0.2 -0.6 -1.0 Freq (0.1 to 20.1 GHz) (a) (b) -15 -10 -5 -20 0S21(dB) 24 6 8 10 12 14 16 18 20 0 22 Freq (GHz) (c) (d) (e) model HF SS M9 M8 M7

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29 Figure 2-6. HFSS diagrams of (a) overview, and (b) top view, of a stacked differential inductor in a 90 nm CMOS technology with w=6 m, r=130 m, and s=2 m. Figure 2-7. Simulation results of a 2 nH differential induct or in a 90 nm CMOS technology. Figure 2-7 shows one of the simulation result s of inductance value and Q extracted from HFSS. The simulated inductor has inner radius of 130 m, turns of 4, width of 8 m, and spacing between turns of 2 m. From the simulation, inductance value is about 2 nH, and Q is more than 10 from 5 GHz to 10 GHz. These numbers are good compared to the induc tors using thick top metal in 0.18 m CMOS process. Of course, higher Q c ould be obtained if the inductor area is increased with large inner radius. -2 0 2 4 6 8 10 12 14 0 2 4 68101214161820 Frequency (GHz) Q -15 -10 -5 0 5 10 15 Inductance (nH) r w s

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302.2 Capacitors Two kinds of lumped capacitors are used in this proposal. Firs t one is the metal-insulatormetal (MIM) capacitor. MIM capacitors have large capacitance density of about 1 fF/ m2 for 0.18 m CMOS technology. Figure 2-8 illustrates the physical structure of a MIM capacitor and the equivalent circuit it uses to model the parasitic components accompanied with the capacitor. Since the vertical distance between the metal layers is large so that the capacitance value is small, an extra layer of CTM is added in between M5 and M6 as shown in Figure 2-1 for 0.18 m mixed-mode CMOS technology. Extra masks are n eeded if the designers want to have CTM layer in the process. Figure 2-8. MIM capacitors gra phs of (a) a physical structure and (b) an equivalent circuit model. For digital CMOS 90 nm technology that we used in this study, there are no MIM capacitors provided. Therefore, interdigital capacito rs are used instead. Figure 2-9 shows the top view of such the capacitor. Multi-fi ngers of thin metal traces are in terdigitally placed as close as possible. It utilizes the fri nging capacitance between the sides of the metals. The minimum lateral metal distance which is determined by the processing tolerances set in the design rules could be much smaller than the vertical dist ance between the metals. In TSMC 90 nm CMOS ( b ) (a) M6 M5 MIM la y e r Via5

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31technology, the minimum spacing between two adjacent tr aces of the same metal is set to be 0.14 m, which is smaller than the vertical distance of about 0.4 m. Therefore, lateral capacitances have larger contribution to the total capacitance value compared to the vertical capacitances. Figure 2-9. Top views of an interdigital capacitor. More metal layers we use in the capacitor, the higher capacitance density we can get. Metal 2 to Metal 6 are stacked to form the in terdigital capacitor in our design because these metal layers have the same design rules so that the capacitors shape could be uniform. For metal layers above metal 6, metal thickness increases so that the minimum trace width in the design rules also increases. In this design, the capacitance density is about 1.8 fF/ m2, which is even larger than the MIM capacitor in 0.18 m CMOS technology. Howeve r, since interdigital capacitors utilize lower metal which is closer to the substrate compared to MIM capacitors, parasitic capacitances to substrate are al so larger than those of MIM capacitors. 2.3 Varactors In RF circuits, varacters are mostly used in VCO design. There are th ree types of varactors that are widely implemented in modern CM OS technology: diodes, inversion-mode MOS (IMOS) capacitors, and accumulation-mode MOS (A-MOS) cap acitors [10].

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32 Figure 2-10. Cross section of an A-MOS varactor. Cross-section of an A-MOS var actor is shown in Figure 2-10. The varactor is composed by substituting the drain and source diffusion region of a PMOS with n implant. While the gate voltage is greater than the bulk voltage, the MOS device enters the accumulation region, where the voltage at the interface between gate oxide and semiconductor is positive and high enough to allow electrons to move freely. Simulated capac itance values versus biasing voltages of an AMOS varactor are shown in Figure 211. It is implemented in CMOS 0.18 m technology with the width and length value of 50 m and 0.5 m. The model of these varactors is provided by the foundry. Figure 2-11. Simulated capacitance values vers us biasing voltages of an A-MOS varactor. G B B n+ n+ np VGB ( V ) 1.7 1.2 0.7 0.2 -0.3 -0.8 -1.3 -1.8 330 280 230 180 130 80 Capacitance (fF)

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33 Figure 2-12. Cross-section view of an I-MOS varactor. The other kind of varactors that we use is I-MOS varactor. While the foundry does not provide the model for A-MOS capac itors, I-MOS capacitor is another choice with the use of just MOS model itself. The cross-sect ion view of an I-MOS capacitor is shown in Figure 2-12. It is just a simple PMOS with the body connects to th e highest supply voltage and drain and source connected with each other. While the gate to body larger than the threshold voltage, the MOS enters inversion region, where the region MO S devices operate under the saturation region. Figure 2-13 shows simula tion results using 0.18 m mixed-mode CMOS technology with an IMOS capacitor with size of 50 m times 0.5 m. Figure 2-13. Simulated capacitanc e values versus biasing voltag es of an I-MOS varactor. VCG ( V ) 1 0.6 0.2 -0.2 -0.6 -1 -1.4 -1.8 250 Capacitance (fF) 1.4 1.8 210 170 130 90 50 G C C p + p + np n+ B

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34CHAPTER 3 DESIGN OF WIDEBAND LOW NOISE AMPLIFIERS In this chapter, wideband LNAs are designed and implemented in a 90 nm CMOS technology. First of all, the popul ar topologies on designing wi deband LNAs used today are discussed. Tradeoffs between these topologies have to be made when choosing an appropriate one. Next, a new modified resistive feedback t opology is proposed. The topology includes gate inductors inside the feedback loop, R-C fee dback networks, and ne utralization capacitors. Furthermore, since for a wideband amplifier, hi gh-Q inductor is not necessary, active inductors could be used for small area design. An LNA with an active inductor load will be demonstrated. Three LNAs were designed with different sp ecifications using the topologies proposed in this chapter. Two of the LNAs achieve wide bandwidth up to 8-9 GHz with about 16 dB of voltage gain, while the third LNA achieves a 23 dB gain with a bandwidth of 3 GHz. The three LNAs were co-designed with ESD capacitances and packaging bond-wires. Theoretical analysis along with simulation and measurement results will be presented. 3.1 Topology Survey The challenges in designing wideband LNAs include the followings: (1) a wideband matching to the antenna has to cover the entire operating ba ndwidth, which depends on the specifications and applications; (2) the need for a low noise performance in order to improve the sensitivity of the wideband receiver; (3) low pow er consumption in order to extend the battery lifetime of a handheld device; (4) sufficient ga in to reduce the noise contributed from latter stages, e.g. mixers; (5) a small chip size to reduc e the cost in manufactur ing wideband receivers. After the booming of wideband communicati ons as described in Chapter 1, wideband LNAs are one of the most popular topics in IC related journals. The design topologies of wideband LNAs people use broadly c ould be generally categorized as:

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35(a) Bandpass filter input matching: addi ng a matching network at the input. (b) Distributed amplifier: cascading multiple gain stages to extend the bandwidth. (c) Common gate amplifier: use of a common gate input stage for 50 wideband matching. (d) Resistive Feedback: use a resistive fee dback to widen matching and gain bandwidth. Figure 3-1. Results of (a) schematic, (b) chip pho to, (c) gain, and (d) return loss, of an input matching wideband LNA from Bevilacqua, etc. 3.1.1 Bandpass Filter Input Matching In 2004, Bevilacqua [11], and [12], proposed th e first CMOS ultra-wideband LNA with the use of an input matching network. Figure 3-1 su mmarizes of the wideband LNA, including the (a) (b) (c) (d)

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36graphs of gain, schematic, photo, and return lo ss. In this design, an input band-pass matching networking comprising of inductors and capacitors are added at the gate of the input transistor. However, from the chip photo, it shows that five i nductors are used in this LNA, which occupies a lot of chip area. Therefore, this kind of t opology is not suitable for the low cost ultra-wideband transceiver and is not co nsidered in this design. Figure 3-2. Results of (a) schematic, (b) chip photo, (c) gain, and (d) return loss, of the distributed LNA. 3.1.2 Distributed Amplifier Distributed amplifier is the de facto topology that microwav e engineers would think of when designing a wideband amplifier. A distribute d amplifier absorbs the parasitic capacitances of the transistors into the design and adds inductors to form the whole circuit into an equivalent (a) (b) ( c ) (d)

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37distributed transmission line. Th is topology usually has a very wi de bandwidth and is proved to be a very effective way to design wideband amplifiers even in the mm-wave domain. Figure 3-2 illustrates an example in [13] of the above mentioned ultra-wideband distributed LNA. In this design, eight inductors were added with three-stage cascoded amplifiers to form a pseudo-transmission line. The resu lts have shown acceptable gain and matching performance as shown in Fig 32 (c) and (d). However, eight inductors shown in Fig 3-2 (b) occupy a lot of chip area, and make it costl y. Also, power consumption is usually large for distributed amplifiers because of the multiple amplifying stages. Figure 3-3. Results of (a) schematic, (b) chip pho to, (c) gain, and (d) return loss, of the common gate LNA. (a) (b) (c) (d)

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383.1.3 Common Gate Amplifier Another technique for an input wideband 50 matching is the use of common gate input stages. In 2005, Chehrazi, etc [14] realized a common gate wideband LNA on ultra-wideband application. Schematics, photo, and the measuremen t results of the LNA are shown in Figure 3-3. Since 1/gm determines the input impedance, gm is pretty much a fixed value determined by the external termination. Because of this, the gain of the common gate stage is usually small. In Chehrazis work, a common gate stage and a co mmon source stage are used in parallel to boost up the gain. With the use of multiple amplifying branches, noise canceling technique was also first used in a wideband LNA design. Also, in this paper, packaging effects are first added into the design of a wideband LNA. 3.1.4 Resistive Feedback Amplifier The last common used technique for a wideband matching is the use of resistive feedback resistor to widen the bandwidth but with the sacr ifice in gain. In [15], Kim, etc. published an ultra-wideband LNA using such technique. Schema tic, photo, and the results are shown in Figure 3-4. As shown in the figure, the chip size is mu ch smaller compared to that of a distributed amplifier or an input band-pass matching amplifier. This is because the less use in inductors. However, the bandwidth is still not enough to co ver the whole UWB range which is from 3 GHz to 10 GHz. With the introduction on the wideband LNA design given in this section, it is shown that there is still a long way to go to make certain kinds of LNAs into production. In real productions, realities like ESD protection circui ts and packaging effect have to be carefully considered while designing an LNA. Therefore, in this study we focus on adding more r ealities in designing wideband LNAs with the considerations mentione d above. Also, the performances have to be improved.

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39 Figure 3-4. Results of (a) schematic, (b) chip pho to, (c) gain and return loss, of the resistive feedback LNA. 3.2 Theoretical Analysis Important parameters while designing wideba nd LNAs include gain, bandwidth, return loss, noise figure, and linearity. In this sect ion, the proposed LNA will be built step-by-step mainly based on the concerns of gain fl atness, matching condition and noise figure. 3.2.1 Basic Structure of Resist ive Feedback Amplifiers Basic structure of a resistive feedback amplifier is shown in Figure 3-5. The input signal is fed into a common source transistor through a source with impedance Rs. Load resistor RL (a) (b) (c)

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40connects supply voltage Vdd and output node, and feedback resistor Rf is connected through output node and input of the transistor. The input impedance could be derived as ) 1 ( 1 1L f m L m L f iR R g R g R R R (3-1) Figure 3-5. Basic structure of a resistive feedback amplifier. where gm is the transconductance of the input transistor, and the approximation is valid while gmRL >>1, which is typical. Voltage gain, define d by output magnitude divided by one-half of Vin which is the available input voltage magnit ude under impedance matched condition, of this feedback amplifier under impedance is given by i f L f f m L L f f m L in out vR R R R R g R R R R g R V V A ) ( ) ( ) 1 ( 2 / 1 (3-2) Approximation is valid while gmRf >>1. In order to get higher gain, Rf is desired to be larger compared to Ri since it is a fixed value determined by the previous stage. According to equation (3-1), in order to maintain the same value of input impedance, gmRL has to be increased with bigger Rf. Vout Vin Vdd Rf RL Rs

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41 Figure 3-6. Schematic of a resistive feedback am plifier feeding back th rough a source follower. For an amplifier with voltage gain of 17 dB (7 in decimal), feedback resistor Rf would be 350 In order to get input impedance equal to 50 RL has to be 233 with gm equal to 50mA/V. These numbers will be used for comparison with another case later. 3.2.2 R-C Feedback through a Source Follower Figure 3-6 shows the schematic of a resistive feedback amp lifier feeding back through a source follower instead of direc tly feedback through output node. CL and Cf represent the load capacitance and the feedback capacit or which will be added later. The effects of these capacitors are ignored for now. For low frequencies, the input impedance could be derived as L f m L m m f m iR R g R g g R g R1 1 2 21 ) 1 ( 1 (3-3) where gm1 and gm2 are the transconductances of transistor M1 and M2, respectively. The approximations stand when gm1RL >>1 and gm2Rf >>1. Voltage gain under impedance matched condition at low frequencie s can be expressed as i f L m vR R R g A 1 (3-4) Vout Vin Vdd Ib Rf RL Cf Rs CL M1 M2

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42For having the same voltage gain as in the previous case, feedback resistor Rf has be 350 and RL has to be 140 with gm1 equal to 50 mA/V for 50 input matching. Compared to the traditional resistive feedback, for the sa me voltage gain, required value for RL is dropped by 40%. With just a little bit increase in the output capacitance due to M2, the bandwidth, which is determined by the RC time constant, is still larger than the previous case. Therefore, feedback through a source follower will be used in substitute to the traditional resist ive feedback in this article. Figure 3-7. Small signal equivalent model of the circ uit in Figure 3-6. Now, the capacitors are taken back into cons ideration to examine frequency response of the amplifier. Figure 3-7 shows the equivalent small signal model of the circuit in Figure 3-6. Bandwidth of the circuit needs to be consid ered while designing a wideband amplifier. Cin is added to represent the input capacitance and CL is the load capacitance. Cf is the feedback capacitor that is in parallel with the feedback resistor. It will be explained later for its use. The input impedance of Figure 3-7 without Cf could be derived as ) 1 1 1 ) 1 ( 1 //( 1 ) 1 ( 1 // 11 1 2 2 1 2 2 L m L L L L L m m f m in L m m f m in iR g C R s C sR R g g R g sC R g g R g sC Z (3-5) Zin Cin gm1vin Rf Cf RL gm2vout Vou t CL Vin

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43 Figure 3-8. Simulation results of the effects of load capacitance CL on input impedance for a resistive feedback amplifier. Equation (3-5) represents a first-order impeda nce with a zero and a pole with dc magnitude of Ri (equation (3-3)) in parall el with input capacitor Cin. The zero of the impedance is located at frequency of 1/ 2 RLCL and the pole is located at frequency of (1+gm1RL)/ 2 RLCL. The pole frequency is about a voltage gain times hi gher than the zero frequency. Figure 3-8 shows simulation results on the effects of varying load capacitances CL on input impedances. It shows that the real part of impedance value will rise at low frequencies due to the effect of a low frequency zero and then decrease due to the pole at higher freque ncies. The higher the value of the load capacitance, the lower the frequency in put impedance rises due to further lower zero frequencies. Similar results also occur fo r the imaginary part of the impedance. 0 20 40 60 80 100 120 Real (Zin) (Ohm) 0 5 10 15 20 -80 -60 -40 -20 0 20 Frequency (GHz)Imag (Zin) (Ohm) CL=0fF CL=50fF CL=100fF CL=150fF CL=200fF CL=0fF CL=50fF CL=100fF CL=150fF CL=200fF CL CL

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44 Figure 3-9. Simulation resu lts of the effects of Cf on input impedance for a resistive feedback amplifier. Intuitively, the rise of the input impedance is due to the lack of gain at high frequencies since the equation of input impedance is approx imately equal to feedback resistor divided by gain of the amplifier. At high frequencies, gain is dropped due to poles. This could be solved either increasing high frequency ga in or reducing the feedback impedance at higher frequencies. Therefore, a capacitor Cf could be added in parallel to the feedback resistor to obtain the second attempt reducing the feedback impedan ce. Input impedance with capacitor Cf is shown as ) 1 1 1 1 1 1 ) 1 ( 1 //( 12 1 1 2 2 f f f m f f L m L L L L L m m f m in iC sR R g C R s R g C R s C sR R g g R g sC Z (3-6) 0 20 40 60 80 100 Real (Zin) (Ohm) 0 5 10 15 20 -80 -60 -40 -20 0 20 Frequency (GHz)Imag(Zin) (Ohm) Cf=0fF Cf=20fF Cf=40fF Cf=60fF Cf=80fF Cf=0fF Cf=20fF Cf=40fF Cf=60fF Cf=80fF Cf Cf

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45From the equation, it is seen that an extra pole and zero pair are added to the transfer function. The new zero is located at frequency of (1+gm2Rf)/ 2 RfCf and the new pole is located at frequency of 1/ 2 RfCf. For this term, it has zero frequenc y higher than the pole frequency, on the contrary to the previous term. With proper value of Cf to control the loca tions of the new zero and pole, the extra zero-pole pair could be used to flatten frequency response of the impedance. Figure 3-9 shows the simulation results of us ing a capacitor in parallel with feedback resistor with different values wh ile the load capacitance is 200fF. It can be seen that the use of feedback parallel capacitor greatly reduce the pe aking in input impedances at high frequencies. 3.2.3 Input Gate Feedback Inductor Without any further modification on circuit topo logy, voltage gain of a resistive feedback amplifier is still not flat for wide bandwidth. So me methods can be used to extend the bandwidth. One of which is put an inductor on in series with the load resistor for bandwidth extension [11]. Here a new way placing an inductor Lg inside the feedback path at th e gate of the input transistor is proposed. Figure 3-10 shows the schematic of such an impl ementation with an inductor at the gate of the input transistor inside th e feedback loop. Voltage gain co uld be expressed on impedance matched condition into 11 23 122(1)(1)(1) 1 222mLmL v g insinLLginLL LLsin pppgRgR A s ssLCRCRCLCRC RCRC sss www (3-7) where the gate inductor adds another pole on the voltage gain transfer function. wp1, wp2, and wp3 are the three roots of the denominator, and fp1, fp2, and fp3 are their corresponding frequencies. Figure 3-11 illustrates the trajectories of increasing Lg of pole locations for the proposed amplifier. One of the roots at frequency of fp1 is located on the negative real axis and the other

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46two roots at fp2 and fp3 are complex conjugate to each othe r. The added inductor creates a high frequency real pole fp1 as shown in the figure; on the ot her hand, it moves the other two poles away from the zero frequency. Since the added po le is located at highe r frequency, it does not affect the bandwidth that much. However, pus hing away the other two poles extends the bandwidth almost by double. Howeve r, it can be seen that the tr ajectories of two complex poles curve downwards above certain i nductance value. Therefore, ther e is an optimum value of the inductor that is needed to use using this tech nique. Otherwise, the bandwidth will be shrinking instead of increasing. Figure 3-10. Schematic of a resistive feedback amplifier feeding back with a peaking inductor inside the feedback loop. Figure 3-12 shows the simulation results using equation (3-7) with va rious inductor values. In this case, Cin=300 fF, CL=150 fF, gm=80 mA/V, RL=200 and Rs=50 are all typical values while designing a wideband amplifier. It shows bandwidth of voltage gain becomes greater with the increased value of inductors. Ho wever, peaking becomes too big eventually and Vout Vin Vdd Ib Rf RL Rs CL M1 M2 Lg

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47it degrades the bandwidth. Optimum value of the inductor in th is simulation is about 0.4 nH. Comparing to root trajectory simulation in Figur e 3-11, poles also start m oving toward real axis while inductor value higher than about 0.4 nH. Th e two results are consis tent with each other. Note that with the further increasing of Lg, S11 might become greater than 0 dB at high frequencies. It will cause the amplifier to oscillate and has to be considered carefully. Figure 3-11. Trajectories of pole locations with increasing value of gate inductor in resistive feedback amplifier. 3.2.4 Active Inductor Load To enhance bandwidth of the LNA, inductor sh unt peaking technique [16] is used in the design. Inductor shunt peaking is accomplished by series a resistor and an inductor as a load of an amplifier. Traditionally, pa ssive inductors are used in L NA designs. However, large area consumption due to high-Q inductors is undesire d due to the increase in cost. Active inductor could be used in substitute to a passive inducto r. Schematic and equivale nt circuit of an active inductor is shown in Figure 3-13. -30 -25 -20 -15 -10 -5 0 -15 -10 -5 0 5 10 15 Real (pole frequency) (GHz)Imag (pole frequency) (GHz)fp1 fp2 fp3 Increasing Lg

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48 Figure 3-12. Simulation results of the voltage gain versus frequency using equation (3-7). Figure 3-13. An active inductor loads graphs of (a) schematic and (b) equivalent circuit. As shown in Figure 3-13 (a), an active induc tor is realized by a co mmon gate transistor with a series resistor Rg on gate. In Figure 3-13 (b ), gate-source capacitance Cgs, and load capacitance CL are added in the equivalent circuit. Fi gure 3-14 shows frequency response of the active inductor. The transfer function has a zero and two poles These points determine four operation regions shown in Figure 3-14. It could be shown that Z1=1/CgsRg and P1=gm/(Cgs+CL). Rg Vdd ML Vg Cgs gm1vgs Zin Zin Rg CL (a) (b) 0 5 10 15 20 4 6 8 10 12 14 16 18 20 22 Frequency (GHz)Av (dB) Lg=0nH Lg=0.1nH Lg=0.2nH Lg=0.3nH Lg=0.4nH Lg=0.5nH Lg=0.6nH Lg

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49Since P2 is located at a much higher frequency, it can be omitted without consideration here. From Figure 3-14, it can be seen the circuit acts as a resistor at low frequencies in region (I), and as an inductor in series with a re sistor in (II). Finally, it behaves as a capacitor in (IV). Therefore, this circuit could be used in region (I) and (II). Use relations of pole and zero, design constraint gmRg>(Cgs+CL)/Cgs has to be satisfied for P1>Z1. As a result, an active indu ctor is equivalent to a resistor with value of 1/gm in series with an i nductor with value of Leq=CgsRg/gm. This active inductor will be the load of the proposed LNA to have peaking at the output. Figure 3-14. Frequency response of magnitude of input impedance. 3.2.4 Noise Analysis For noise analysis of MOSFET transistors, onl y channel thermal noise s are considered in hand calculation. They have pow er spectral density of 4kTrgd0 per unit frequency, where K is the Boltzmann Coefficient, T is the absolute temperat ure, r is the fitting value for noise model, and gd0 is the channel conductance while drai n-to-source bias is equal to zero. Output impedance under input impedance matched condition of Ri=Rf/gm1RL could be derived as f Z1 P1 P2 1/gm (I) (II) (III) (IV) |Zin|

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50 2 ) ( 11 1 L s L m f s f L s f s L m L outR R R g R R R R R R R R g R R (3-8) Some of the important noise s ources could be derived as s L m L m L s L RR R g R g R R R FL2 1 2 1 21 ) 2 /( ) 2 ( 1 (3-9) 1 1 1 2 1 2 0 11 ) 2 /( ) 2 (1 s m L m L s d MR g R g R R g F (3-10) L m s L m f L m L m L m f s f RR g R R g R R g R g R g R R R Ff1 2 2 1 2 1 2 1 2 11 ) 2 ( ) ( ) 2 ( 1 (3-11) 2 1 2 2 2) 1 ( 12L m s m MR g R g F (3-12) ,where FRL, FM1, FRf, FM2 are the noise factors of four of the most important noise contributors in this wideband feedback amplifier, and they ar e thermal noises generated by load resistor RL, transistor M1, transistor M2, and feedback resistor Rf. in equation (3-12) is equal to gm/gdo. The total noise factor could be presented as f LR M M R totF F F F F 2 11 (3-13) In order to have some feeling about the noise performance of this circuit, an example is given in the following. For an LNA with 15 dB (5.6) voltage gain, gm1 is chosen to be 50 mA/V, RL is 112 Rf is set to be 280 for input impedance matched to 50 gm2 does not have to be as large as gm1 because its purpose is only to provide a feed ing back path instead of gain. It is set to be 20 mA/V. For all the transistors, r/ is assumed to be typical of 1.33. Using equations (39) (3-13), the results are calculated that FRL=0.071, FM1=0.532, FRf=0.178, and FM2=0.042. Ftot=1.823(2.6 dB). Noise figure of 2.6 dB is acceptable for a wide band LNA. Of course, this number will be bigger in real LNAs because a lo t of parasitic resistors are omitte d in the hand calculations. From

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51the numbers above, it can be seen that the major noi se contribution is the tr ansistor that amplifies the signal, which generates about 60% of the additional noises from the LNA. Observing equation (3-9) (3-12), it can be seen that in order to get lower the noise figure, gm1RL term has to be increased. It can be done in two respects: increasing gm1, which will add more input capacitance to the amplifier for bi gger input transistor, or burn more power; and increasing RL, which will lower the output pole and also means lower bandwidth. Depending on the design aspects on bandwidth and gain, diffe rent noise figure coul d be obtained through certain trade-offs according to the design guidelines above. 3.2.5 Bond Wires and ESD Diodes As CMOS technologys continua lly shrinking the thickness of gate oxide, CMOS circuits become more and more sensitive to ESD. Since LNAs behave as an entering gate of a receiver chip from the off chip antenna, ESD protection mechanism has to be used preventing permanent damages on the chip. Figure 3-15. Equivalent model of wideband LN As input stage with package and ESD diodes added. Incoming signals of LNAs are usually at ve ry high frequencies, hence adding ESD diodes could be detrimental to the performance of the LNA because of the extra parasitic capacitors. In Vin Rf M1 Lg Lb (package) Cesd Cin

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52[17] and [18], ESD diodes are c onnected through an ESD inductor so that the capacitance due to ESD diodes will not affect directly to the performance of LNAs. However, due to the area concern, inductors are not preferred in the desi gn. Especially while LNA has differential inputs, two inductors are necessary, which will consume large amount of area. Therefore, ESD diodes are still added directly to the inputs, and circu it techniques are used to reduce the effect of performance reduction due to them. From simulation, once a capacitor with valu e of couple of hundreds femto-Farads, which represents capacitance of ESD diodes, added to the inputs of LNA, matching would become very bad. Also from the simulation, if an inductor, which represents packag es inductance, matching would become bad. However, if both of the capac itor and inductor are added, it actually forms a low pass network as shown in Figure 3-15, where Cesd and Lb are ESD capacitance and package inductor, respectively, and help s matching to certain point. Figure 3-16. Smith Chart of S11 simulation results from DC to 15 GHz on effects of (a) ESD diode capacitance with Lb=1.5 nH, and (b) bond wire inductance, with Cin=250 fF. Figure 3-16 shows the S11 simulation results from DC to 15 GHz on Smith Chart to examine the effects of ESD capacitors and packag ing inductors. Figure 3-16 (a) shows that with Cesp=0fF Cesd=75fF Cesd=150fF Cesd=225fF Cesd=300fF Lb=0nH Lb=0.5nH Lb=1.0nH Lb=1.5nH Lb=2.0nH (a) (b) Cesd Lb

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53the 1.5 nH packaging inductance (e quivalent to 1.5mm bond wire), Cesd moves the input impedance toward the origin. As well, in Figure 3-16 (b), Lb also helps matching. Therefore, both of the ESD capacitances and packaging indu ctors have to be considered carefully in simulation while designing LNAs. 3.2.6 Neutralization Capacitors Finally, neutralization capacitors are added to cancel out the gate to drain capacitance of input transistors through providing equivalent negative capacito r. In order to use neutralization capacitors, differential structure has to be used. Some benefits also come with the differential circuit, like increased immunity to common noi se, de-sensitivity to ground and supply packaging inductors, and so on, with the trade-off of larg er chip area and double the power consumption. Neutralization capacitors are connected from gate of plus input transistor to drain of the negative input transistor, and vice versa. From simula tion results, neutralization capacitors boost up the bandwidth of the amplifier and improve input ma tching at high frequencies. However, extra feedback loops make the circuit easier to osci llate. Circuits stability has to be examined carefully. 3.3 Circuit Design of Proposed LNAs Practical design considerations will be addresse d in this section. A little bit on description of the technology are delivered first. Then, ES D protection devices that are used will be presented. In order to test the capability of the proposed structure, three wideband LNAs are designed using the structure proposed above. LNA 1 is designed using resistive loads to achieve UWB bandwidth. LNA 2 is designed using resi stive loads also but with lower bandwidth comparing to LNA 1. LNA 3 is designed us ing active inductor loads and it achieves UWB bandwidth as well. Throughout the process in designing these LNAs, tradeoffs on the performances could be observed.

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543.3.1 TSMC Digital 90 nm CMOS Technology Prototype wideband LNAs are fabricated us ing TSMC digital 90 nm CMOS technology. Thickness of gate oxide is about 16 m and it supports 1.2 V supply voltage. It has minimal 65nm physical gate length for core transistors. NMOS has about 0.34 V thresh-hold voltage and 0.32V for PMOS. The process has low-k (2.9) back-end dielectrics and dual-damascene copper for metal layers. It has six thin metal layers, with a thicker metal layer seven on top with thickness of about 0.5 m. For the inductors that are used in the designs, Q-value is not high enough for using only one metal layer. Three metal la yers, metal five, six, and seven, are stacked together by dense interconnects to form an equiva lent thick metal. As for passive capacitors, because of lack of metal-insu lator-metal (MIM) process, metal two to metal six are stacked to form interdigital capacitors. Capacitance density of interdigital capacito r is about 0.39 fF/m2. Figure 3-17. Layout of ESD diodes for (a) n-diode, and (b) p-diode. 3.3.2 ESD Diodes ESD diodes themselves will survive ~2000 V human body model (HBM). Their layouts are shown in Figure 3-17 for both of n-diode a nd p-diode. P-diode is c onnected from input to voltage supply node and n-diode is connected from input to ground node. Length of the fingers Nwell Nwell N+ N+ N+ P+ P+ P+ P+ N+ P+ (a) (b)

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55of diodes is 25 m, and 5 fingers are used in parallel for each diode. The capacitance of each diode is about 120 fF. Therefore, the extra cap acitance that is added on the inputs due to ESD protection of LNAs is about 240 fF. 3.3.3 LNA 1 Design goals for LNA 1 are that its 3 dB bandwidth over 7 GHz; voltage gain more than 15dB (5.6); NF lower than 4 dB; and S11 smaller than -10 dB over the entire bandwidth. First assume that the load capacitan ce is about 200 fF. Inverse RC time constant must be higher than 7GHz for such a capacitor. Resistor value should be smaller than 115 Having some margin, resistor value is chosen to be 100 For gain of 15 dB, according to equation (3-4), gm1 has to be 56 mA/V. Input matching according to equation (3-3) determines Rf to be set to 280 Figure 3-18. Schematic of LNA 1 (biasing circuits not shown). Figure 3-18 shows the schematic of the proposed LNA 1. The circuit has differential inputs and differential outputs. Simulations are done in Cadence Spectre. Cascode stage is chosen so that the outputs are isolated fr om the inputs and this makes the design easier. Due to the deepVin + Vo + Vdd Vin -Vo Ib Ib Ib1 I b 2 Ib1 Ib2 Cn Cn RL RLLg Lg Mb Mb M3 M3 M2 M2 M1 M1 Rf Rf Cf Cf Dp Dp Dn Dn

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56submicron CMOS, output resistance (r0) is pretty small (couple of hundreds ohms) while the biasing current and device size (hence gm value) are large. Due to the restriction on small value of the output resistance, gain will not increa se in proportional to the load resistor. Transistor Mb and current source Ib2 are used to construct an output buffer for impedance matching to 50 to the test equipment. It has vol tage gain of 0.45 (-6 dB) while a 50 load is connected to the outputs. Under the situation that the LNAs are used in SOC design, output buffers could be removed and the LNA could be dire ctly connected to the gate of input transistor of the following mixer. Therefore, voltage gain specified here does not include the voltage amplitude loss due to the output buffer. Current source Ib is added to extract part of the current from the input transistors so that the voltage drop along RL is reduced. For supply voltage of 1.2 V, voltage drop on the resistor could not be more than 0.3 V while cascode stages are implemented. Also, the output nodes have to bias the output buffers. For RL having value of 200 and voltage drop along it is 0.3 V, the current flowing through it has to be less th an 1.5 mA. The value of current source Ib is then determined by this. After tuning the values of each component, final values for RL is 200 Rf is 250 Cf is 100 fF, Cn is 60 fF, and Lg is 0.5 nH. Equivalent load resistance after parallel with r0 is about 120 which is close to hand cal culation result. Input device size is 120 m/90 nm. Current flowing through one side of the input stages is about 8 mA, and transconductance (gm1) is about 80mA/V. Because of feedback employed in the circuit, stability has to be examined carefully. Phase margin of the loop gain is more than 600. K-factor is always greater than one for all frequencies.

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57Simulation results are shown in Fi gure 3-22 and it will be discussed with measurement results in Section 3-4. 3.3.4 LNA 2 Design goals for LNA 2 are that its 3 dB bandwidth over 2.5 GHz; voltage gain more than 23 dB (14); NF lower than 2 dB; and S11 smaller than -10 dB over the entire bandwidth. Load capacitance is also assumed to be about 200 fF. Inverse RC time constant must be higher than 3GHz for such a capacitor. Resistor value should be smaller than 322 Having some margin, resistor value is chosen to be 300 For gain of 23 dB, according to equation (3-4), gm1 has to be 50 mA/V. Input matching according to equation (3-3) determines Rf to be set to 700 Figure 3-19. Schematic of LNA 2 (biasing circuits not shown). Figure 3-19 shows the final schematic of the pr oposed LNA. It is the same circuit with LNA 1 except a dc control circuit is used to control the value of current source Ib based on the dc Vin + Vo + Vdd Vin Vo Ib Ib Ib1 I b 2 Ib1 Ib2 CnCnRL RL Lg Lg Mb Mb M3 M3 M2 M2 M1 M1 Rf Rf Cf Cf Dp Dp Dn Dn Rb Rb OP Vb

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58voltage of output nodes. Common mode value of these nodes are se nsed using large resistors Rb, and then feed into the negative input of an ope rational amplifier OP. Plus node of the OP is biased at Vb, with value about 0.9 V. If the common mode value of output nodes is less than Vb, Ib will be increased to let less current flowing through RL, and common mode voltage will increase through this negative feedback mechanism; vice versa. After tuning the values of each component, final values for RL is 600 Rf is 800 Cf is 60 fF, Cn is 80 fF, and Lg is 1.2 nH. Equivalent load resistance after parallel with r0 is about 300 which is close to hand calculation result. In put device size is 400 m/90 nm. Current flowing through one side of the input stages is about 8mA, and transconductance (gm1) is about 60 mA/V. Simulation results will be shown in Figure 324 along with measuremen t results in Section 3-4. 3.3.5 LNA 3 Design goals for the LNA 3 are that its 3 dB bandwidth over 7 GHz; voltage gain more than 17 dB (7); NF lower than 4 dB; and S11 smaller than -10 dB ove r the entire bandwidth. Figure 3-20 shows the schematic of the proposed LNA. The circuit has differential inputs and differential outputs. Cascode st age is chosen so that the out puts are isolated from the inputs and this makes the design easier. Current Ib is used to determine the current flowing through the active inductor. Transistor Mb and current source Ib2 are used to construct an output buffer. Under the situation that the LNAs are used in SOC design, output buffers could be removed and the LNA could be directly connect ed to the gate of input tran sistor of the following mixer. Neutralization capacitors Cn and feedback capacitor Cf parallel with Rf [9] are used to extend the bandwidth and matching. The component values are Rf of 300 Cf of 150 fF, and Cn of 60 fF. Transistor size for active inductor is 8 m/0.18 m, and Rg is 1.5 k gm1 and gmL are about 60 mA/V and 5

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59mA/V, respectively. Input device size is 150 m/90 nm. Current fl owing through one side of the input stages is about 8 mA. Because of feedback paths employed in the circ uit, stability has to be examined carefully. Phase margin of the loop gain is more than 600. K-factor is always gr eater than one for all frequencies. Simulation results are shown in Figure 3-26 and will be compared with measurement results. Figure 3-20. Schematic of LNA 3 (biasing circuits not shown). 3.4 Measurement Results of Proposed LNAs The three proposed wideband LNAs are fabr icated in TSMC digital CMOS 90 nm technology. Measurements are done on 1.6 mm thick FR4 (dielectric constant = 4.2) boards with chip-on-board package. 50 microstrip lines are used on th e board connecting bond wires from Vo + Vdd1 Vo Ib Ib Ib1 Ib2 Ib1 Cn Cn Rg Mb Mb M2 M2 M3 M3 M1 M1 Rf Rf Cf Cf Dp Dp Dn Dn Ib2 Vdd2 ML ML Rg Vg Vin Vin +

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60the chip to the SMA connectors on the edge of the board. S-parameters are measured using Agilent E8361 PNA series network analyzer; No ise figure is measured using Agilent E4448A PSA series spectrum analyzer ; two Merrimac MFR-12457 wideband directional couplers are used to convert single ended signals from measurement equipments to differential inputs of the chips; vice versa at the output ports. Figure 3-21. Chip photo of LNA1 (area=0.58mm x 0.22mm with pad). 3.4.1 The Resistive Load UWB LNA (LNA 1) Voltage gain is obtained from the measurement S21 data and de-embedded the gain loss through the output buffer. Voltage loss due to the output buffer, which is a simple source follower has output impedance of 50 is about 7 dB (0.45). In real system-on-chip (SOC) implementations, LNA outputs could be directly connected to the following stage instead of through output buffers. Therefore, voltage gain is a more significant metric compared to power gain, which is S21. The die photo of this LNA is shown in Figure 3-21 with chip dimension of 0.58 mm x 0.22 mm. Active area, which excludes the area of bond pads, of this chip is about 0.066 mm2. Bond wires are made manually with approximately 1mm in length for the RF pads. However, length mismatches for the two input ports and two output ports are inevitable, which might degrade the performance to certain degree. 0.22mm 0.58 m m

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61Figure 3-22 to Figure 3-25 show measurement re sults of the LNA with simulation results. Voltage gain is flat around 17 dB over wide band width. The 3 dB bandwidth is from 0.2 GHz to 9 GHz. The measurement data has already subt racted the loss due to FR4 boards through subtracting two measurement data of chip with board and board only. Figure 3-22. Measurement (solid line) and simulation (dashed line) results of voltage gain for LNA1. Figure 3-23. Measurement (solid line) a nd simulation (dashed line) results of S11 for LNA1. Figure 3-23 shows measurement results of re flection coefficients. It shows that S11 is lower than -10 dB over very wideband. Measured resu lts are better than simulated ones because the directional couplers themselves are already matched to 50 Figure 3-24 shows the measured 0 5 10 15 20 25 Voltage Gain(dB) 0 1 2 3456789 10 Frequency (GHz) -35 -30 -25 -20 -15 -10 -5 0 S11 (dB) 0 1 2 3456789 10 Frequency (GHz)

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62reverse isolation and output return loss. The reverse isolation is better than 30 dB but has higher value between frequencies from 6 GHz to 9 GHz. Since output is constructed as a source follower stage, the output return loss is grea ter than 10 dB throughout all the frequencies. Figure 3-24. Measurement results of S22 and S12 for LNA1. Figure 3-25. Measurement (solid line) and simulation (dashed line) results of NF for LNA1. Figure 3-25 shows the NF performance. M easurement results follow the trend of simulation ones. NF has minimum value at 3 GHz of 4.2 dB, and it rises to 7.5 dB at 7.5 GHz due to insufficiency in the gain of the amplifier. 0 2 4 6 8 10 12 0 1 2 3456789 10 Frequency (GHz)NF (dB) -60 -50 -40 -30 -20 -10 0 0 1 2 3456789 10 Frequency (GHz) S12(dB) & S22(dB) S22 S12

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63Note that the NF is measured with output buffe r. It could be derived that the noise factor related to output buffer is 13 0 ) ( 1 4 ) ( 42 1 2 1 L m buffer buffer L m o mbuffer buffer buffer MR g R g R g Fbuffer (3-14) where rbuffer, buffer are the coefficients related to noise and rbuffer/ buffer=1.33. If the noise contribution of the output buffer is removed, th e minimum NF of this LNA is actually 3.9 dB, which is 0.4 dB improved compared to the measurement data. Figure 3-26 shows the measur ed linearity results with both IIP3 and IIP2 which is important for direct conversion receivers. Input third-order-intermodulati on product (IIP3) is about -8 dBm and IIP2 is better than 8 dBm. This LNA consumes about 20 mW of power (excluding output buffers) w ith 1.2 V supply voltage. Figure 3-26. Measured li nearity results for LNA1. 3.4.2 The High Gain Wideband LNA (LNA 2) The die photo of this LNA is shown in Figure 3-27 with chip dimension of 0.56 mm x 0.42 mm. Active area, which excludes the area of bonding pads, of this chip is about 0.134 mm2. This -10 -5 0 5 10 15 0 2 46810 Frequency (GHz)IIP3 & IIP2 (dBm) IIP3 IIP2

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64LNA occupies greater chip area compared to LNA1 mainly because it uses two larger inductors. Bond wires are made manually with approximately 1.5-2 mm in length for all the RF pads. Figure 3-28 to Figure 3-32 show the measurem ent results of the LNA with simulation results. From Figure 3-28, voltage gain is about 22.5 dB over wide bandwidth and starts to fall at 2.7 GHz. The 3 dB bandwidth is from 0.2GHz to 3.2 GHz. Figure 3-29 shows the measurement results of reflection coefficients. It shows that S11 is lower than -10 dB over very wideband. Figure 3-27. Chip photo of LNA2 (area=0.56mm x 0.42mm with pad). Figure 3-28. Measurement (solid line) and simulation (dashed line) results of voltage gain for LNA2. Figure 3-30 shows the measurement results of the output return loss and the reverse isolation. The output return loss is better than 20 dB across the whole bandwidth and the reverse 8 12 16 20 24 28 0 1 2 3 4 Frequency (GHz)Voltage Gain (dB) 0.56 m m 0.42 mm

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65isolation is better than 30 dB. Figure 3-31 s hows the NF performance. Measurement results follow the trend of simulation ones. NF has mini mum value at 3 GHz of 1.76dB. NF from 1 GHz to 3 GHz is below 3 dB. This low NF and high gain makes this wideba nd LNA a good candidate for multi-band receivers. The noise contribution of output buffer is about 0.03 (0.1 dB better) according to equation (3-14). Out put buffer has much smaller noise contribution compared to LNA 1 because of the voltage gain is much bigger. Figure 3-29. Measurement (solid line) a nd simulation (dashed line) results of S11 for LNA2. Figure 3-30. Measurement results of S22 and S12 for LNA2. Figure 3-32 shows the measured linearity results with both IIP 3 and IIP2 which is important for direct conversion receivers. Input third-order-in termodulation product (IIP3) is -30 -25 -20 -15 -10 -5 0 0 1234 Frequency (GHz)S11 (dB) -70 -60 -50 -40 -30 -20 -10 0 0 1234 Frequency (GHz) S12 & S22 (dB) S22 S12

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66about -9 dBm and IIP2 is better than 6 dBm. This LNA consumes about 25 mW of power (excluding output buffers) with a 1.2 V supply voltage. Figure 3-31. Measurement (solid line) and simulation (dashed line) results of NF for LNA2. Figure 3-32. Measured li nearity results for LNA2. 3.4.3 The Active Inductor Load UWB LNA (LNA 3) Die photo of this LNA 3 is shown in Figur e 3-33 with chip dimension of 0.38 mm x 0.36mm. Active area, which excludes the area of bond pads, of this chip is about 0.034 mm2. Bond wires are made manually with approxima tely 1mm in length for the RF pads. 0 2 4 6 8 0 1234 Frequency (GHz)NF (dB) -10 -8 -6 -4 -2 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 3.5 Frequency (GHz)IIP3 & IIP2 (dBm) IIP3 IIP2

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67Figure 3-34 to Figure 3-38 show the meas urement results of the LNA along with simulation results. Figure 3-34 shows that the vo ltage gain is flat around 17 dB over wide bandwidth. The 3 dB bandwidth is from 0.2 GHz to 9.2 GHz. The measurement data has already subtracted the loss due to FR4 boards through subt racting two measurement data of chip with board and board only. Figure 3-35 shows measuremen t results of reflection coefficients. It shows that S11 is lower than -10 dB over very wideband. Measured results are better than simulated ones because the directional couplers themselves are already matched to 50 Figure 3-33 Chip photo of the LNA 3 (area=0.38mm x 0.36mm with pad). Figure 3-34. Measurement (dotted line) and simulation (dashed line) results of voltage gain for LNA3. 0 4 8 12 16 20 0 1 2 3456789 10 Frequency (GHz) Voltage Gain (dB) 0.38mm 0.36mm

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68 Figure 3-35. Measurement (dotte d line) and simulation (dashed lin e) results of S11 for LNA3. Figure 3-36 shows the measurement results of the output return loss and the reverse isolation. The output return loss is better than 10 dB across the whole bandwidth and the reverse isolation is better than 20 dB. Figure 3-37 s hows the NF performance. Measurement results follow the trend of simulation ones. NF ha s minimum value at 6.8 GHz of 3.4 dB. Figure 3-36. Measured results of S12 and S22 for LNA3. Figure 3-38 shows the measured linearity results with both IIP 3 and IIP2 which is important for direct conversion receivers. Input third-order-in termodulation product (IIP3) is about -8 dBm and IIP2 is better than 8 dBm. This LNA consumes about 16 mW of power -40 -30 -20 -10 0 0 1 2 3456789 10 Frequency (GHz) S11 (dB) -60 -50 -40 -30 -20 -10 0 0 1 2 3456789 10 Frequency (GHz) S12(dB) & S22(dB) S12 S22

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69(excluding output buffers) with 1.2 V, 1.4 V, an d 1.7 V supply voltages. However, most of the current is flowing from 1.2 V power supply. Figure 3-37. Measurement (dots) and simula tion (dashed line) results of NF for LNA3. Figure 3-38. Measured li nearity results for LNA3. 3.5 Conclusions In this study, design theory and considerat ions of proposed wide band LNA structure are presented. The design employs capacitors a nd inductors along the feedback path, and neutralization capacitors between input transistor s. Packaging and ESD diodes are co-designed in 0 2 4 6 8 10 0 1 2 3456789 10 Frequency (GHz) NF (dB) IIP2 IIP 3 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 0 2 46810 Frequency (GHz)IIP3 & IIP2 (dBm)

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70the simulation. Depending on the specification, ga in, bandwidth, and NF are trade offs between each other. Three LNAs were fabricated us ing pure digital CMOS 90 nm technology. These LNAs achieve good performance in gain, bandwidth and NF. Also they occupy small chip area compared with other published LNAs. Table 3-1 su mmarizes the performance of the LNAs that were fabricated in this study and their perfor mances are compared with other published data. Table 3-1. Measured performance compared with prior published works CMOS Process BW (GHz) Voltage gain (dB) NF (dB) IIP3 (dBm) Package /ESD Power (mW) Vdd (V) Area (mm2) LNA 1 Dig. 90nm 0.2-9 17 4.2 min -8 y/y 20 (diff) 1.2 0.066 LNA 2 Dig. 90nm 0.2-3.2 22.5 1. 76 min -9 y/y 25 (diff) 1.2 0.134 LNA 3 Dig. 90nm 0.2 8 17 3.4 min -9 y/y 16 (diff) 1.4 0.034 [20] Dig. 130nm 1-7 17 2.4 min -4.1 y/n 25 (diff) 1.4 0.019 [21] Dig. 90nm 0-6 17.4 2. 5 min -6 n/y 9.8 1.2 0.0017 [22] 180nm 1.3-10.7 8.5 4. 4 5.3 8 n/n 4.5 1.8 1 [22] 180nm 1.3-12.3 8.2 4. 6 5.5 8 n/n 4.5 1.8 1 [19] RF 90nm 0.5-8.2 25 2.2 3.8 -4 n/n 42 2.7 0.025 [23] 180nm 1.2-11.9 9.7 4.5 5.1 -6.2 n/n 20 1.8 0.59 [24] Dig. 90nm 2-11 12 5.5 min -4 n/n 17 1.2 0.696 [25] 180nm 3.1-10.6 10.9 12 4. 7 -10 n/n 10.57 1.5 0.665 [11] 180nm 2.3-9.2 9.3 4 8 -16 y/n 9 1.8 0.66 [26] 180nm 0.6-22 8.1 4.3 6.1 x n/n 52 1.3 1.35 [17] 130nm 3.1-10.6 15.3 2.04-2.98 <-5.1 y/y 9 1.2 0.87

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71CHAPTER 4 DESIGN OF WIDEBAND PASSIVE MIXERS In this chapter, the behavior of resistive mixers is studied The study begins with a board level design of resistive mixers using Gallium N itride (GaN) high electron mobility transistor (HEMT) devices. Because of the inadequate mode ling of GaN transistors operating in the linear region, a linear model was developed and used in the design of resistive mixers. Three resistive mixers were made with GaN transistors with di fferent lengths and their results were compared and examined. After examining the performance of the GaN re sistive mixers, focus is diverted to the popular CMOS process for more integration of the circuit. First of all, a CMOS wideband resistive mixer was made using the 0.18 m CM OS technology. The resistive mixer covers a wide frequency range up to 11 GHz. Next, a su bharmonic pumped CMOS passive mixer with an integrated VCO and a quadrature generation circuitr y is examined at the end of the chapter. The mixer has a better performance in the isolation be tween the LO to the output ports comparing to the previous wideband mixer and can be used in low leakage applications, such as the implementation of a frequency synt hesizer discussed in Chapter 5. 4.1 GaN Passive Mixers Wide bandgap semiconductor devices using Ga N and SiC materials ha ve drawn a lot of attention recently. These devices have high br eakdown voltages and theref ore are suitable for high power circuits. These high pow er circuits can be used in applications like satellite communications, warfare systems, and cellular ba se stations. GaN-based devices have been shown to have high power handli ng capability at microwave freque ncies above X-band, and have potential to generate high power at millimete r-wave frequencies as high as 100 GHz [27].

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72Several GaN circuits have been demonstrated such as high speed switches [28], [29]; low phase noise VCOs [30], [31]; pow er amplifiers [32]; and passive mixers [30], [33], [34]. The previously reported GaN passive mixers had vari ous conversion loss and lin earity performances. In order to examine the behavior of a GaN passi ve mixer, passive mixers were made in this subsection. Figure 4-1. Die photo of one of the Ga N HEMT devices with a device area of 200 m x 1 m. 4.1.1 Modeling of GaN Transist ors in the Linear Region GaN HEMT transistors were pr ovided by the Airforce. It prov ided devices with different gate lengths and gate widths. Die photo of one of the GaN HEMT devices with a device area of 200 m x 1 m is shown in Figure 4-1. IC-CAP modeling software was used to obtain the Curtice cubic model for the measured DC and AC performance and the parameters were further optimized in Agilent Advanced Design System ( ADS) simulator. However, from the simulation results and the measurement data, some important mixer parameters can not be predicted well. These parameters include the optimum gate bi as voltage, and the LO power requirement for achieving certain conversion loss performance. This is due to the fact that a resistive mixer is

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73operated in the linear region of a transistor and the Curtice model is mainly focused on the active region. Therefore, efforts were made on the device modeling in the linear region. Figure 4-2. Equivalent circuit model used for GaN HEMT devices. In this work, accurate models in linear region at different ga te bias voltages were created based on measured data. The small-signal equivale nt circuit model shown in Figure 4-2 was used. Lg, Rg, Ld, Rd, Ls, and Rs are the parasitic components associat ed with the transistor interconnects to the pads of three ports. Cp models the capacitance of the pads. Cds, Cdg, Cgs, and Rds are transistor parameters that vary with the gate bias. Small-signal s-parameters were measured at different gate biases with source grounded and dr ain biased at 0 V. The gate bias was varied from -7 V to -2 V with 0.5 V step. The use of small-signal model reduces the complexity of modeling and gives an accurate model in linear re gion, which is critical to the design of resistive FET mixer. Gate Source Cgd Rgd Cgs Rgs Cds Rds Cp Cp Ls Rs Cp Drain Rg Lg Cp Ld Rd

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74The most important parameter that controls the conversion loss is the value of turn-on resistance Rds. The behavior of Rds was curve-fitted using the su m of two hyperbolic tangent functions with diffe rent weights: ) tanh( ) tanh(2 2 1 1 0 b g b g dsV bV R V aV R R R (4-1) ,where R0, R1, R2, a, b, Vb1, Vb2 are constants and Vg is the gate bias. Two hyper-tangent terms are used here because using only one term is not enough to fit the measured data very well. One hyper-tangent term has a steeper slope whereas th e other has a slower slope at the transition region of Rds from turn-on to turn-off, which is cr itical for resistive mixer performance. Figure 4-3. Modeled Rds versus gate bias on GaN devices with different gate lengths. The model fitting results of Rds for the three GaN devices with different sizes of 300 m x 0.75 m, 300 m x 1 m, and 300 m x 1.2 m are shown in Figure 4-3. As shown in the figure, the device with smallest gate length has the lowest value of turn-on resistance. The turn-on -7 -6 -5 -4 -3 -2 101 102 103 104 105 Gate Bias (V)Rds (Ohm) 0.75um 1.00um 1.20um

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75resistances are 12.6 15 and 23 for gate lengths of 0.75 m, 1.0 m, and 1.2 m, respectively. 4.1.2 Design of GaN Resistive Mixers The model of the transistors from the previous section was used in the Agilent Advanced Design System (ADS) to simulate the conversio n loss. The IF power was obtained using Fast Fourier Transform of the transient data simulated by ADS. The simulation results of the conversion loss versus LO power is shown in Fi gure 4-4 with comparison to measurement results that will be discussed later. Figure 4-4. Measured and simu lated conversion loss versus LO power for GaN devices with different gate lengths. The circuit was simulated with RF, LO and IF frequencies of 1.7 GHz, 1.9 GHz, and 200 MHz, respectively. The gates were biased at -5 V, -4.5 V and -4.7 V for the gate length of 0.75 m, 1.0 m, and 1.2 m, respectively, where the lowest conversion loss for each circuit was 5 7.5 10 12.5 15 9 10 11 12 13 14 15 16 17 18 LO Power (dBm)Conversion Loss (dB) mea 0.75um mea 1.00um mea 1.20um sim 0.75um sim 1.00um sim 1.20um

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76obtained. From the figure, it can be seen that the mixer using 0.75 m device has the lowest conversion loss since the turn-on channel resistance is the lowest among the three devices. The figure also indicates that the c onversion loss does not change much when LO power is increased above 14 dBm, which matches pretty well with the measurement results. Figure 4-5 shows the schematic of these single re sistive mixers. LO is applied to the gate, RF is applied to the drain, and the IF is gene rated at the source. Quarter wavelength transmission lines are used in the RF and LO matching network as RF chokes. The open-circuited /4 line at the IF end is used as LO and RF short to improve the LO-IF and RF-IF isolations. Figure 4-5. Schematic of th e single-FET resistive mixer. 4.1.3 Measurement Results The circuits were fabricated on FR4 substrate with thickness of 1.6 mm. The dielectric constant is 4.4 and the loss tangent is 0.022 at 2 GHz. Picture of one of th e resistive GaN mixers is shown in Figure 4-6. The three mixers were biased at their optimum bias points where the minimum conversion losses were achieved. The optimum gate bias for devices with gate length LO RF IF Gate Bias /4 @ RF GaN HEMT LO Matchin g RF Matching Bond Wire Bypass Cap

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77of 0.75 m, 1 m, and 1.2 m were -5.2 V, -4.3 V, and -3.2 V, respectively. The bias voltage were set to be just below the turn on voltage of each transistor, which allowed the LO signal to turn on and off the channel effectively. Figure 4-6. Photo of a GaN mixer board. Figure 4-4 shows the measurement results of conversion loss versus LO power, in comparison to the simulation results. For all th e devices, the optimum LO power is 14 dBm. If the LO swing is too small, the channel cannot turn on completely, therefore the conversion loss will be higher. Simulated results are also shown in this graph. It matches pretty well for the simulated data and measured data. Figure 4-7 shows the frequency response of the conversion losses. It can be seen that all three mixers have the lowest conversion loss at 1.7 GHz, where the mixers were designed for. Figure 4-8 shows the conversion loss versus RF power, at RF=1.7 GHz and LO=1.9 GHz. The LO power was fixed at 14 dBm. From the graph, we can see that the conversion loss of device with the smallest gate length is the best among all. The convers ion losses are 9.5 dB, 10.5 dB,

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78and 11.8 dB for devices w ith gate lengths of 0.75 m, 1.0 m, and 1.2 m, respectively. The input 1 dB compression points (P1dB) are 11 dBm, 11 dBm, and 12 dBm, respectively. Figure 4-7. Measured conversi on loss versus RF frequency. Figure 4-8. Measured c onversion loss versus RF power. Figure 4-9 shows the two-tone third-order intercept point (IIP3) measurement results. The figure shows both the fundamental and the 3rd orde r inter-modulation products with two-tone RF -5 0 5 10 15 9 10 11 12 13 14 15 RF Power (dBm)Conversion Loss (dB) 300um x 0.75um 300um x 1.0um 300um x 1.2um 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 8 9 10 11 12 13 14 15 RF Frequency (GHz)Conversion Loss (dB) 300um x 0.75um 300um x 1.0um 300um x 1.2um

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79input at 1.7 GHz and 1.701 GHz. By extrapolating the measured da ta in the figure, IIP3 of 27 dBm, 25 dBm, and 24 dBm were obtained fo r the devices with gate length of 0.75 m, 1 m, and 1.2 m, respectively. Figure 4-9. Two-tone IIP3 measuremen t result of the GaN resistive mixers. In conclusion, three GaN resistive mixers we re designed, tested, and compared. The test results show that these GaN resistive mixers have comparable performance to other mixers using wide bandgap devices as well as GaAs HEMT devices. Table 41 shows the summary of the performance of the mixers and Table 4-2 show s the comparison with other published results. Table 4-1. Summary of th e GaN resistive mixers Gate Length (um) CL (dB) P1dB (dBm) IIP3 (dBm) LO Power (dBm) Gate Bias (V) 0.75 9.5 11 27 14 -5.2 1.0 10.5 11 25 14 -4.3 1.2 11.8 12 24 14 -3.2 0 5 10 15 20 25 30 -70 -60 -50 -40 -30 -20 -10 0 10 20 RF Power (dBm) 1st and 3rd Order Outputs (dBm)

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80Table 4-2. Summary of the III-V resi stive mixers from existing publications Technology Freq. (GHz) CL (dB) P1dB (dBm) IIP3 (dBm) LO Power (dBm) This work AlGaN/GaNHEMT 1.7 0.2 9.5 10 26 14 [28] SiC-MESFET 5.175 0.25 7.8 X 30 23 [28] AlGaN/GaNHEMT 5.175 0.25 7.3 X 36 30 [29] AlGaN/GaNHEMT 12.4 2.4 17 30 40 20 [30] SiC Diode 0.5 0.1 12 x x x [35] InP MODFET 95.5 1.5 9 8 x 8 [36] GaAs G-FET 5.2 0.95 5.5 16 23 10 [36] GaAs D-FET 5.2 0.95 7.4 4 13 0 4.2 CMOS Passive Mixer In the previous section, the design of board leve l resistive mixer is shown. In this section, a wideband resistive down-conver ting mixer was designed and fa bricated using TSMC mixedmode 0.18 m CMOS technology. Wideband matchi ng at the RF ports and source follower at output buffer at IF ports were used to achieve wideband frequency response. This resistive mixer covers a wide frequency range from 1 GHz to 11 GHz with 7 0.5 dB conversion loss. The output buffer stage consumes 3 mW, which is mu ch lower than previously published wideband active mixers. This mixer is suitable for low power UWB devices. 4.2.1 Discussion on CMOS Resistive Ring Mixer Techniques to derive the conversion loss of a passive mixer can be found in [37]. In order to get the idea of how th e bandwidth and conversion loss of th e resistive mixers are determined, three different CMOS technologies were used in the simulation to observe performances in the frequency responses and conversion loss. The mode ls used in this study are provided by TSMC. Figure 4-10(a) shows the schematic of the simu lated passive mixers using different gate lengths and widths. Figure 4-10(b) shows the equivalent circu it while the mixer is operating and

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81this Figure will be discussed later. In the simula tion, all of the transistors are provided with the same power of LO signa ls at the gates. Figure 4-10. Schematics of (a) a double-balanced CMOS resistive mixer, (b) an equivalent circuit of the resistive mixer. Figure 4-11 shows the convers ion loss of a double-balanced resistive mixer versus frequency from 1 GHz to 20 GHz using three diffe rent CMOS technologies with gate lengths of 180 nm, 90 nm, and 65 nm. Four curves of conve rsion losses are shown in each graph with different W/L ratios equal to 400, 300, 200, and 100. From Figure 4-11, se veral conclusions can be made. First, for a certain technology, the sma ller the ratio of W/L is, the higher the conversion loss is. This is due to the turnon resistor is smaller when the device is larger. Also, the smaller W/L is, the conversion loss is more flat. Second, for different technologies, with the same W/L ratio, the resistive mixer with smaller L has more flat conversion loss. Third, with the same W/L ratio, devices with larger gate le ngth have lower conversion loss. CL Rs CL Rs Rs Rt(t) Rt(t-T/2) Rt(t-T/2) Rt(t) LO Vrf LO LO LO (a) (b) Cch(t-T/2)+Cj Cch(t)+ Cj Cch(t)+ Cch(t-T/2)+ 2Cj Cch(t)+ Cch(t-T/2)+ 2Cj Cch(t)+ Cj Cch(t-T/2)+Cj Vrf Rs Vrf Vrf

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82The reason that the conversion loss is lower fo r larger length devices is that the turn-on resistance is larger for deep submicron devices. When the gate length is getting smaller, the electron mobility is also getting lower due to th e high electric field at the gate as shown: 01()eff GSTHVV (4-2) where eff is the effective mobility, 0is the low field mobility, is a fitting parameter, VGS and VTH are gate-source voltage and th reshold voltage, respectively. is approximately inversely proportional to the thickness of gate-oxide. Therefor e, the short channel effect of the transistor makes the mixer conversion loss higher. Figure 4-11. Conversion loss vers us frequency of CMOS resistiv e mixers with different gate lengths. 4.5 5.5 6.5 7.5 8.5 4.5 5.5 6.5 7.5 8.5 1 4 7101316 19 Frequency (GHz) 4.5 5.5 6.5 7.5 8.5 180n m 90n m 65n m W/L = 400 W/L = 300 W/L = 200 W/L = 100 Conversion Loss (dB)

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83The bandwidth dependency on the gate length co uld be described as follow. Determination of the bandwidth can be s een from Figure 4-11(b). Rs is the source equivale nt resistor from the previous stage; Rt is the time-variant resistors of the transistors since they switch on and off according to the LO signals, which has a period of T; CL is the load capacitance; Cch is the channel capacitance of the transistors; and Cj is the junction capacitance of the transistors. For transistors operating at different regions, channe l capacitance varies according to the LO signal. While the transistor is off, the channel capacitance is small (depletion capacitance) and while the transistor is on (operated in linear region for a resistive mixer), the ch annel capacitance becomes WLCox/2, where Cox is the oxide capacitance. The bandwidth of the mixer is determined by the pole location located at the input of the RF ports. The pole location can be seen as 1/RsCtot. Assume that the mixer is driven by an LO signal with a square wave in the waveform shape, Rt(t) for one pair of the transistors is zero and Rt(t-T/2) is infinity. If the passive mixer is divided into two half circuits since the double balanced mixer is symmetrical in structure, the equivalent input capacitance is equal to Ctot=2Cch(t)+2Cch(t-T/2)+4Cj. Since for CMOS transistors with a smaller gate length, under the same W/L ratio, the channel capac itance as long as junction cap acitance are smaller comparing to transistors with larger gate length. As a resu lt, the pole location of pass ive mixers with smaller gate lengths is larger than the one with larger gate lengths. In conclusion, resistive mixers with larger gate length will have narrower frequency response, but will have lower conversion loss; on the other hand, resistive mixers with shorter gate length will have wider bandwidth but wi ll have higher conversion loss. Furthermore, because transistors with smaller gate lengths ha ve smaller capacitance comparing to transistors with larger gate lengths, the bandwidth is also larger.

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844.2.2 Design of CMOS Resistive Ring Mixer A wideband passive mixer was designed us ing 180 nm CMOS technology. Figure 4-12 shows the schematic of the resistive ring mixer. Double balanced ring structure is used because of the superior performance of the isolation betw een ports and the cancella tion of the even-order harmonics. At the RF input port, series inductors of 1.4 nH and shunt capacitors of 90 fF are used for matching. In add ition, shunt resistors of 250 are used to improve the wideband matching. Figure 4-12. Schematic of the wideband resistive ring mixer. No matching circuits are used at the LO port in order to reduce the circuit area. Without the LO matching circuitry, the LO power need ed to drive the resistive mixer to minimum conversion loss is slightly higher, but the difference of 11.5 dB in simulation is not significant. In our simulation, LO power needed for the circ uit is about 8 dBm to make the conversion loss minimum. RF Vb Vg + Vdd Vb Vg + + -LO IF Vdd

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85At the IF output port, so urce followers are used for impedance matching to 50 since the lumped elements needed for 50 impedance matching at 500 MH z IF would occupy too much space on chip. Shunt capacitors to ground are used to make the LO and RF signals shorted to ground and improve the LO-to-IF and RF-to-IF isol ation. DC blocking cap acitors are placed in series to block DC biases of the source followers from the resistive mixer core. Figure 4-13. Chip photo of the fabricated mi xer (chip size including the pads: 0.95 mm x 0.65 mm). Three DC biases for output buffer are supplied externally when measuring the circuit. The optimum values for Vb, Vg, and Vdd are 0.5 V, 0.5 V, and 1 V, respectively. Increasing the value of Vdd above 1 V does not make a significant diffe rence on the mixer performance. Decreasing the value of Vdd would increase the loss. Therefore, the lo west possible bias of 1 V is chosen to lower the power consumption of the output buffe r. The current flow through the source follower is about 3 mA; therefore the power consum ption is 3 mW. Figure 4-13 shows the die IF IFGND GND GND LO+ LOGND GND GND GND GND GND RF+ RFGND Vdd Vg Vb

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86microphotograph of the resistive ring mixer. The size of the chip is measured 0.95 mm x 0.65 mm. 4.2.3 Simulation and Measurement Results This mixer was measured on-wafer. Signal gene rators were used to generate the RF and LO signals. Spectrum analyzer was used to measure the converted signal at the IF port. External baluns were used at RF, LO, and IF ports. All the measurement losses from the baluns and the cables were carefully calibrated using the network analyzer. 1 2 4 6 8 10 12 20 15 10 5 0 RF Frequency (GHz)Conversion Loss (dB) Measurement Simulation Figure 4-14. Measurement and simulation results of conversion loss versus RF frequency with fixed IF frequency 500 MHz. Figure 4-14 shows the measured conversion lo ss from 1 GHz to 12 GHz. The solid line with symbols indicates the measured data, wherea s the dashed line indicates the simulated data using CADENCE SPECTRE. LO frequency is 500 MHz higher than th e corresponding RF frequency, so that the IF freque ncy is fixed at 500 MHz. From the figure, the conversion loss is within 7.5 dB from 1 GHz to 11 GHz, which covers the entire UWB band. The Vdd for the bias circuitry is set at 1 V, a nd the current consumption is 3 mA The total power consumption is

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873 mW. The measurement results and simulation resu lts are quite consistent with each other as shown in the figure. Figure 4-15 shows the measurement results fo r input 1 dB compre ssion point (P1dB) and input third-order intercept point (IIP3) for the CMOS wideband resistive ring mixer. It is well known that resistive mixer has better linearity performance comp ared to the active mixers because the transistors are operating in the line ar region. For the linea rity measurement, LO power of 9dBm was applied to the resistive mixer. As shown in th e figure, P1dB is 5 dBm for 1 GHz to 12 GHz. IIP3 was measured with two RF input signals separated by 10 MHz. Thirdorder inter-modulation products were at 480 MHz and 520 MHz, where the first-order signals were at 500 MHz and 510 MHz. As shown in the fi gure, IIP3 is within 9-13 dBm from 1 GHz to 12 GHz. This wideband mixer has very good linearity performance, which makes it suitable for high dynamic range UWB receivers. Figure 4-16 shows the measured performance of conversion loss versus LO power. In resistive mixers, LO voltage swing has to be la rge enough to let the chan nel resistance of the transistor reaches its lowest limit, so that the conversion loss could be minimized. However, there is a limit of conversion loss where it will no t improve any further with the increase of LO power. The measurement was conducted at ten different frequencies from 1 GHz to 10 GHz, with 1 GHz step. All the 10 curves in Figure 4-16 show the same trend that the higher the LO power, the smaller the conversion loss. The conv ersion loss approaches to a limit when the LO power is over 9 dBm, which is why 9 dBm of LO power was chosen in the previous measurements. If higher conversion loss can be to lerated in some applic ations, the requirement of LO power can be reduced. For example, for 10 dB conversion loss, LO power can be reduced

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88by half from 9 dBm to 6 dBm. Figure 4-16 also sh ows that the LO power requirement is almost the same from 1 GHz to 10 GHz. 2 4 6 8 10 12 -5 0 5 10 15 20 RF Frequency (GHz)P1dB and IIP3 (dBm) P1dB IIP3 Figure 4-15. Input P1dB and IIP3 versus RF frequency. 2 4 6 8 10 25 20 15 10 5 LO Power (dBm)Conversion Loss (dB) Figure 4-16. Measurement results of conversion loss versus LO power. The measurements were conducted for ten RF frequencies from 1 GHz to 10 GHz. Figure 4-17 shows the measurement result of S11 for the RF port from 100 MHz to 12 GHz. The S11 was measured single-ended using GSGSG probe with one port terminated with 50

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89The RF input matching is very wideband. The mi nimum return loss occurs at 3.5 GHz with 32 dB return loss. The overall return loss is better than 10 dB from 100 MHz to 6 GHz. 0 2 4 6 8 10 12 -35 -30 -25 -20 -15 -10 -5 0 RF Frequency (GHz)S11 (dB) Figure 4-17. Measurement results of th e RF return loss from 100 MHz to 12 GHz. Figure 4-18. Measurement results of th e NF of the wideband passive mixer. Figure 4-18 shows the measurement result of the NF of the wideband passive mixer across the frequency from 1 GHz to 10 GHz. The NF m easurement was conducted using two different LO power of 7 dBm and 10 dBm. The NF measurement was done at a fixed IF frequency of 500 0 2 4 6 8 10 12 14 16 024681012 Frequency (GHz)NF (dB) 0 2 4 6 8 10 12 14 16 024681012 Frequency (GHz)NF (dB) LO=10dBm LO=7dBm

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90MHz. While the LO signal is 7 dBm, the NF is around 11 dB a nd goes higher at frequencies above 6 GHz. While the LO signal is 10 dBm, the mi nimum NF is 9.5 dB and also goes higher at frequencies higher than 7 GHz. In this mixer design, the double balanced stru cture was used in the resistive mixer to improve the isolation. Across the whole band fr om 1 GHz to 11 GHz, the measured RF-to-LO isolation is -39 dB, and LO-to-RF isolation is -37 dB. However, the isolation is not good enough in certain applications such as the frequency synthesizer de scribed in Chapter 5. With the isolation, LO signal will leak to the output and cause spurious si gnals at the output. In order to solve this problem, subharmonic mixer structure will be examined in the next section for the improvements in the LO to output isolation. 4.3 CMOS Passive Harmonic Pumped Mixer Subharmonic mixers draw a lot of attention r ecently in direct conversion receivers. One of the biggest problem in implementing direct conver sion receiver is that the feed-through of LO signal might corrupt the receiving signal and saturate the gain stages along the receiving chain. Also, subharmonic mixers become popular at millim eter wave where a low phase noise LO is not readily available. Traditionally mixers use fundamental LO signal and generate out put frequencies of fout= fin fLO. As for subharmonic mixers, they use second, third, or even higher order harmonics of LO signals to realize the frequenc y conversion. The output freque ncy of a subharmonic mixer is LO in outnf f f (4-3) where n is the order of harmonic it uses. To date, subharmonic mixers are published using all different kinds of materials, including III-V compound semiconductors, SiGe, or HBTs. Recently CMOS mixers appear more and more

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91frequently on the research journals due to the ability of integration. In [38], double balanced Gilbert cell subharmonic mixer was presented us ing BiCMOS process at PCS band. In [39], performances of CMOS subharmonic mixers were analyzed in detail. In [40], transformer and quadrature couplers were used as baluns and qua drature phase shifters in a CMOS Gilbert cell subharmonic mixer. In [41], subharmonic CMOS mi xers were exemplified even at millimeterwave frequencies using sourcepumped LO or gate-pumped LO. In this design, a ring structure passive subha rmonic mixer is first demonstrated using a 1P6M 0.18 m mixed-mode CMOS process with MIM capacitors and thick top metal for inductors. A VCO is integrated with the subharm onic mixer. Quadrature phases of the VCO are generated using divide-by-2 circui ts. In section 4.3.1, schematics and system blocks are shown, and in section 4.3.2, simulation a nd measurement results are provided. Figure 4-19. Systematic blocks of the s ubharmonic mixer with an integrated VCO. 4.3.1 Discussions on Each Block Figure 4-19 shows the block diagram of the pa ssive subharmonic mixer with integrated LO in this design. Four phases feeding into the subharmonic mixer are generated by a differential VCO with a divide-by-2 circuit. For passive mixers, it is good to hard switch on and off on the VCO DIV-2 0oLO Buffers LO RF IF Matching Buffe r 90o180o270o RF Input IF Out p u t Passive Subharmonic Mixe r

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92gate of the transistors. Therefore, LO buffers ar e added to amplify the sign als swing feeding into the mixer. A broadband matching circuitry is added at the RF input ports. Biasing is also applied from the RF matching circuit. It is tricky for the RF an d LO signals in a passiv e mixer so that optimum conversion gain could be gotten. At the outputs, an output buffe r is added for the measurement purpose. Figure 4-20. A 5 GHz VCOs diagrams of (a) th e schematic, and (b) the oscillation frequency. Following shows the schematic and simu lation results of individual blocks. 1. VCO and Divide-by-2 ci rcuitry: Figure 4-20(a) shows th e schematic of the 5 GHz VCO. Configuration is a standard cross-coupled NM OS oscillator. The out put is connected to a divide-by-2 circuit th rough a RC level shifter. The inputs of a divide-by-2 circuit have to be biased properly to get a more reliabl e dividing operation. Fi gure 4-20(b) shows the simulated output frequency of the VCO. Th e VCO has output frequencies range from Ib Vdd Vc (a) 4.85 4.95 5.05 5.15 5.25 5.35 0 0.5 11.5 2 Control Voltage (V) (b) Frequency (GHz)

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934.9 GHz to 5.3 GHz for the control voltage ch ange from 0 V to 1.8 V. The tuning range of the VCO is about 8% to the center frequency. Divide-by-2 circuit is shown in Figure 421. Output of the VCO is first leveled shifted through a RC level shifter, then feed into the divide-by-2 ci rcuit. The divider is implemented as cross-coupled current mode latches. Figure 4-22 shows the simulation results of the signal feeding in to the divider and the signal ou tput from the divider. VCO generates frequency of 5.1GHz and the divi der successfully divides the input frequency to one half. Figure 4-21. Schematic of a curre nt mode divide -by-2 circuit. 2. Mixer Core: Since resistive mixers mix in coming signals through th e modulation of the channel resistance of the transistors, it is wort h to observe the varia tion in resistance of a traditional resistive mixer and a resistive subharmonic mixer. Fi gure 4-23 and Figure 424 show schematic and simulation results of th e testing in variation in conductance of Ib Vdd I b Vdd Vin + 0o 180o 90o 270 o0o180o90o 270o

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94single NMOS transistor and a pair of NMOS transistors with differential gate-pumped LO signals. Figure 4-22. Simulation results of the divider input and output. Figure 4-23. Variation of channel resistance of a (a) single NMOS with gate pumped LO, and a (b) parallel NMOS pair w ith differentially pumped LO. The conductance of the channel resistance of a NMOS transistor is shown in Figure 4-24(a). The transistor is turned on every LO cycle of 400 MHz. The conductance of the channel resistance of a pair of NMOS tran sistors is shown in Figure 4-24(b). The differential LO signals alternatively turn on the transistors within the NMOS pair. This is equivalent to using a LO signal which is two times the frequency using here. As a IN LO_0oLO_180o IN LO_0o (a) (b) 2.5 2.1 1.7 1.3 0.9 1.9 1.7 1.5 1.3 1.1 16n 17n 18n 19n 20n Time (s)In p ut ( V ) Out p ut ( V )

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95result, this pair of the transistors could be used in substitute with the NMOS transistors in the traditional resistive mixer. Figure 4-24. Variation in conductance of a (a) resistive mixer, and a (b) resistive harmonic mixer. Figure 4-25 shows the schematic of the proposed resistive harmonic double balanced mixer. The structure is similar to the original resistive mixer, with single NMOS becomes a parallel NMOS pairs. Gates of each transistor pairs are driven by the LO signals with 180o phase difference. As a result, four phases are needed for a harmonic balanced mixer. Figure 4-26 and 4-27 show the transient simulation result and the correspondent spectrum. Input signal is at 5.1 GHz and the VCO is oscillated at 5.35 GHz. The IF output frequency is at 250 MHz. From the si mulation result, the conversion loss of this resistive subharmonic mixer is about 4 dB. 20m 16m 12m 8m 4m 0 0.0 10n 20n 30n Time ( s ) 20m 16m 12m 8m 4m 0 Conductance (mho) 0.0 10n 20n 30n Time (s) ( a ) ( b ) Conductance (mho)

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96 Figure 4-25. Schematic of a resistive harmonic double balanced mixer. Figure 4-26. Transient simula tion of input and output. 3. RF biasing and matching: While the RF si gnals are fed into a subharmonic passive mixer, they have to be biased properly so that the conversion loss can achieve optimal performances. Figure 4-28 illustrates three different RF bias points, namely and relatively to the four pha ses of LO signals. From to the biasing points are RF+ RFIF+ IFLO_0oLO_180oLO_0oLO_180oLO_90o LO_270oLO_90oLO_270o

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97moving higher toward the crossing points of four phases of the LO signals with a voltage potential difference of V. Figure 4-29 shows the simulation results of the RF and IF signals of a subharmonic passive mi xer with the three RF bias conditions described in Figure 4-28. With bias condition the RF signal is modulated by the IF signal where the RF waveform has an enve lope with frequency equal to the IF frequency. Also can be seen from Figure 4-29(a), the IF sign al is also modulated by the RF signal. This is because that at a ce rtain biasing point, tr ansistors on different branches in a sub-harmnic mixer (along the arrow shown in Figure 1) turn on at the same time because the overlap in the wa veforms of quadrature signals. Since the transistors in each branch are in series to each other in a passive mixer, turning on two transistors at the same time shorts the positive and negative nodes of the RF signal. Similar analysis also ap plies to the IF signals. Under the bias condition the RF and IF signals do not interfere with each other as shown in Figure 4-29(b). However, the ma gnitude of the IF signal is small (and thus a higher conversion loss). This is because th e transistors do not ha ve enough of gate voltage to be fully turned on completely. For a passive mixer, a large LO swing is desired so that it can completely turn-on the switch ing transistors to achieve a good mixing performance with less conversion loss. The optimum biasing point would be the condition in Figure 4-28, where the crossing points of the four phases LO signals are about a threshol d voltage higher than the RF biasing point. In this case, no short circuit would happen during the mixer operation while the quadrature LOs turn on the transistors sequentially and this pertain the signal magnitude of the RF signal. Howe ver, the tradeoff would be the need of a

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98higher LO swing comparing to a fundamental passive ring mixer so that the transistors still have enough of gate voltage to be fully tu rned on. In order to have a high LO swing, inverters are used as buffers in this design to have a rail-to-rail LO swing. However, steep edges after the inverters are not desired or that the LO crossing points shown in Figure 4-28 would be too high. As a result, the buffers were intentionally designed to have smaller sizes so that the LO waveforms can be smoother. Figure 4-27. Output spectrums of the subha rmonic mixers (a) i nput and (b) output. Third, how to determine the sizes of the sw itching transistors? It is known that the turn on resistance is smaller for bigger devi ces. The value required for turn on resistance is set by the output frequency of the mixer. In this design, the output frequency is about several hundred MHz. Because the frequency is not high, the device size could not be that big. Device size of 20 m/0.18 m is chosen in this design. RF @ 5.1GHz -17.24dBv LSB -21.41dBv (a) Input spectrum (b) Output spectrum

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99 Figure 4-28. Different RF input biasing levels with differential LO signals. Figure 4-29. Simulation result s of the (a) RF waveforms, and (b) IF waveforms, of a subharmonic passive mixer with different RF bi as conditions. Time (ns) (a) (b) 10 8 6 4 2 0 -50 -30 10 30 50 -10 -50 -30 10 30 50 -10 Bias condition Bias condition Bias condition 0 3 6 9 12 15 -40 -20 0 20 40 Amplitude (mV) -50 -30 10 30 50 -10 -40 -20 0 20 40 -40 -20 0 20 40 LO0o LO90oLO180oLO270o V

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1004.3.2 Measurement Results of the Resistive Harmonic Mixer The proposed subharmonic passive mixer with an integrated quadratur e LO was fabricated using a 0.18 m mixed-mode CMOS technology. The t echnology has six metal layers with a thicker top metal layer for high-Q on chip induc tors. Metal-insulator-met al (MIM) capacitors are also provided in the technology. Die photo of the fabricated circu it is shown in Figure 4-30. The chip has an area of 0.85 mm 0.7 mm. Extern al wideband baluns we re used to convert differential signals to single ended signals. Figure 4-30. Die photo with an area of 0.85mm 0.7mm. The measured tuning frequency of the VCO is from 4.9 GHz to 5.3 GHz. The relationships between the RF bias condition a nd the conversion loss are shown in Figure 4-31. As described in the previous section, the conversi on loss is minimal while the RF signal is biased at 1 V, which would be about a threshold voltage lower than the crossing points of the four phases of LO. Figure 4-32 shows the voltage conv ersion gain versus frequency. The gain de-embeds the loss

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101due to the output buffers and other measurement setups. In the measurement, the VCO is running at a fixed frequency of 5 GHz (L O is running at half the frequenc y of the VCO). The RF signal is swept from 3.5 to 7 GHz with the output IF frequencies varying accordingly. The lowest conversion loss of -5.8 dB is achieved at 5.2 GHz The mixer can be used from 3.5 GHz to 6.7 GHz within 3 dB gain variation. Figure 4-31. Effects of RF bias on the conversion loss of the mixer. Figure 4-32. Measurement and simulation re sults of conversion ga in of the mixer.

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102Figure 4-33 shows the measured LO power leakage to the RF and IF ports. The 1LO leakages to the RF port and IF port are about -35 dBm and -45 dBm across the LO tuning band; and the 2LO leakages are around -60 dBm and -65 dBm. Figure 4-34 shows the measured linearity performance of the mixer. The 1 dB compression point is -10 dBm, the IIP3 is -2 dBm, and the IIP2 is 26 dBm. The subharmonic passiv e mixer itself does not consume power, while the power consumption of othe r components, including a VCO, divide-by-two circuits, LO buffers, and IF buffers, is 25 mA under a 1.8 V supply voltage. Figure 4-33. Measured LO leakage to the IF and RF ports with varying LO frequency. 4.4 Conclusions In this chapter, several kinds of resistive mi xers with different topologies and fabrication topologies are presented. First, a board level Ga N resistive mixer is di scussed in detail with modeling and mixer performance. Next, a 0.18 m CMOS resistive ring mixer on TSMC mixedmode technology was designed, fabr icated, and measured. The resistive ring mixer has very wide bandwidth covering from 1GHz to 11GHz w ith 7.5 dB conversion loss. Finally, a subharmonic CMOS resistive mixer is also meas ured. The subharmonic mixer is suitable for -80 -70 -60 -50 -40 -30 -20 -10 0 2.45 2.5 2.55 2.6 2.65 LO Frequency (GHz) Leakage Power (dBm) LO-RF Leaka g e LO-IF Leakage 2LO-RF Leakage 2LO-RF Leaka g e

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103direct conversion receiver because of its immunity to LO feed through problem. The subharmonic mixer will be used in the OFDM-UWB frequency synthesizer in Chapter 5. It helps the frequency synthesizer to ha ve smaller LO leakage at the output. The two CMOS passive mixers are summarized in Table 4-3. -30 -20 -10 0 10 20 30 -100 -80 -60 -40 -20 0 20 40 Input Power (dBm)Output Power (dBm) Figure 4-34. Measured P1dB, IIP2, and IIP3 of the passive subharmonic mixer.

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104Table 4-3. Summarize of th e fundamental passive mixer and the subharmonic passive mixer Fundamental Mixer Subharmonic Mixer ProcessTSMC 0.18um CMOSTSMC 0.18um CMOS RF Frequency1GHz -11GHz3.5GHz 6.8GHz LO FrequencyRF Frequency + 500MHz4.9GHz 5.3GHz Conversion Gain-6dB-5.8dB IIP3/IIP210dBm/--2dBm/25Bm LO/2LO-to-IF isolation-35dB/--45dBm/-65dBm LO/2LO-to-RF isolation-37dB/--35dBm/-63dBm Chip Size0.95mm x 0.65mm0.85mm x 0.7mm Supply Voltage1V1.8V Power Consumption6mW45mW

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105CHAPTER 5 CONSIDERATION AND DESIGN OF AN UWB FREQUENCY SYNTHESIZER At the beginning of this chapter, a sw itching band VCO was designed and tested. The design considerations about a switching band VC O are also provided. This switching band VCO has a tuning range from 3 GHz to 4.3 GHz. Although the tuning range of the switching band VC O is large, it still lacks the ability to tune the whole UWB spectrum from 3 GHz to 10 GHz. Furthermore, because of the special requirements on the wide frequenc y covering range and the ultra fast switch time, traditional PLLs could not be used in this design. As a re sult, a frequency synthesi zer based on single-sideband (SSB) mixers with only one VCO used for a MB-OFDM UWB system was designed and simulated. The structure of Chapter 5 is listed as fo llows. Section 5.1 describes a switching multiband VCO. Brief introduction to th e frequency synthesizer is give n in Section 5.2; topology that is used in this study is presented in Section 5. 3; concerns about spurious signals are given in Section 5.4; finally simulation results of the CMOS implementa tion of the ideas are shown in Section 5.5. 5.1 A Switching Band VCO Voltage controlled oscillator s (VCOs) usually utilize the ch ange in capacitance value of varactors to make the frequenc y tuning. However, the capacitan ce variation of capacitance in varactors is limited if a wideband VCO is needed There are several reas ons why the VCOs with wideband tuning range are wanted. First of all, be cause of the reduction of the supply voltage in sub-micron CMOS technology, the voltage variation that is used on varactors also reduces. This limits the variation in capacitance of varactors. Second, multi-band transceivers are getting popular since engineers ar e trying to design universal transc eiver, which could be used in

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106conjunction with a fast adaptive si gnal processing chip and adaptiv ely modified the configuration to fit different communication standards. In this case, the VCO has to run at frequencies covering the whole bands. Third, because of process va riation, running freque ncy of a VCO will be different from wafer to wafer. In order to increa se the yield so to reduc e the cost of making the chips, extensive calibration techniques are employed on modern CMOS communication chips. People in [42] use extensive varactor bands and digitally control the capacitance in the resonant tank to cope with the variation in th e temperature, process, and voltage. In order to design a VCO with wide tuning frequency range, concept of switching resonant tank is proposed in [43], [44], a nd [45]. Either inductor or capacitor could be switched to change the resonance frequency of the tank. However, pape rs presented so far do not have the ability to switch both of the inductors and the capacito r. In this design, a switching band VCO was designed to show the ability of the switchi ng resonant using both switching inductors and switching capacitors. Design considerations will be provided in Section 5.1.1; experiment results will be provided in Section 5.1.2. 5.1.1 Design of the Switching Band VCO In order to change running frequencies usi ng switching resonant tanks, two components could be used to switch, one is capacitor, and the other one is inductor. Switching capacitors is desired as the first thought because the area occu pied of inductors is usually big and makes the chip huge and costly. In order for an os cillator to start os cillate, the criteria Gm2L2/Rs=GmQind 2Rs>1 should be fulfilled, where Gm is the effective transconductance of the VCO core transistor, is the oscillation radian frequenc y, L is the inductance value in the resonant tank, Rs is the equivalent series resistance of the inductor, and Qind is the Q-factor of the inductor. In general, Q factor of inductors are roughly on the same order for certain technology. In order to maintain power consumption (Gm) to some acceptable value, Rs has to be increased.

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107From equation Qind= L/Rs, it can be seen that inductance value has to be larger while Rs is increased. For a VCO with extreme wide tuni ng range, e.g. highest frequency to lowest frequency ratio of 1.5, keeping inductance valu e the same might not be a good choice. For an oscillator, small inductor in the resonant might cause the oscillator fa iling oscillate due to insufficiency in feedback gain. While a switching oscillator is running at low frequency mode, inductor value should be increased compared to the high frequency mode. Therefore, switching inductor is desired while the t uning range is extremely wide. Figure 5-1. Schematic of the switching band VCO. However, too many switching inductors would make chip size too large. Two switching inductors are used in this design. Three levels of tuning mechanism are used in this VCO from coarse tuning to fine tuning. Sw itching inductor set the first level of tuning frequency. Two bits VL Tuning Tank Vc VC1 VC2 VC2VC1LbLb L1L1L2L2 ML MLMb MbMi M1 M2C1 C1C2C2CvCvMc1 Mc2Mc2Mc1

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108of switching capacitors are used as second level of tuning frequenc y. Finally, varactors are used as the third level of tuning frequency, and they make the output frequencies of the VCO continuous throughout the spectrum. As a result, there are totally eight different frequency settings for this switching band VCO. Figure 5-1 shows the schematic of this switching band VCO. M1 and M2 form the PMOS cross coupled pair to provide feedback for os cillation. Mi provides the bias current. L1s and L2s are resonant inductors. L2s could be switched on and off using switches ML. C1s, C2s, and Cvs form the resonant capacitance. Both of C1 and C2 could be switched on and off using transistors Mc1 and Mc2. Leeson-Cutlers Formula is presented as )} 1 ]( ) 2 ( 1 [ 2 log{ 10 ) (3/ 1 2 0 f L sQ P kTF L (5-1) ,where k is Boltzmann's constant, T is the absolu te temperature, F is noise factor of the core transistors, Ps is the average power dissipated in the oscillation tank, w0 is the oscillation frequency, QL is the total quality factor of the tank, is the offset from the carrier, and 1/f3 is the corner frequency between the 1/f3 and 1/f2 regions. From the formula, it could be seen that phase noise of an oscillator is controlled by the Q factor of the resonant tank for certain technology and power of the signa l. Figure 5-2 shows the equiva lent circuits of switching inductors while the switch is on or off. For switching band VCOs, in order to make the phase noise stays constant for all bands, Q have to be the same whether switches are on or off. While the switch is off, the Q factor is 1 2 1 2 2 1 2 2 1 2 1 2 1 2 1) 1 ( ) ( ) ( Q Q L L Q L L R R L L R R L L Qoff (5-2)

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109While the switch is on, the Q factor is 1 1 1 1 1Q R L R R L QON on (5-3) where Q1 and Q2 are the Q factors for inductors L1 and L2. Ron is the turn on resistor of the switch. The approximation in equation (5-3) is while Ron is much smaller then the series resistance of inductor L1. This means the transistor size has to be large enough to make the turn on resistor almost negligible compared to the seri es resistance of the i nductor. Make equation (52) and (5-3) equal will lead to Q1=Q2. As a result, Q factor of the two inductors has to be designed equally so that the phase noise would be kept the same for all the switching bands. Figure 5-2. Schematic of resonant tank when (a) low frequency mode, and (b) high frequency mode. The two capacitors in the capacitor bank are de signed to have capacitance ratio of two to one. In this case, the total capac itance value could be varied from three unit capacitance to zero unit capacitance. Also, the Q factors of capacitors in the resonant tank should be kept constant for all switching bands. Q factor of a capacitor is defined as Qc=Rcs/ C, where Rcs is the series resistance to the capacitor. To keep Qc the same, Rcs has to be changed acco rding to the value of L1 L2R2R1C RON VL=0V VL=1.8V L1 L2 R2 R1 C (a) (b)

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110capacitance C. Therefore, the size of switching transist ors control the capacito rs should be scaled in proportional to the value of capacitors. The switching band VCO is designed and fabricated using TSMC 0.18 m CMOS mixedmode technology. The technology has six meta l layers with top metal layer of 2 m thickness for high-Q inductors. The inductors us ed here have octave shape to increase the Q value compared to square inductors. Values of two inductors are 0.46 nH and 0.31 nH. Q factors of these inductors are 10 at 5 GHz. The small values of in ductors are used for intention to have wider tuning range. The two capacitors are implemented in MIM capacitors with values of 850 fF and 430 fF. All of the NMOS switches are made large so that the turn on resist or is small to reduce the Q factor of the resonant tank. For th e switching inductor, the switch size is 600 m/0.18 m. For the switching capacitors, switches have size of 600 m/0.18 m and 300 m/0.18 m for the larger capacitor and the smaller cap acitor, respectively. The output buffers use large inductors to drive external 50 equipments. Figure 5-3. Die photo of the switching band VCO. 5.1.2 Experimental Results Figure 5-3 shows the die photo of the proposed VCO. The chip has size of 730 m in

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111length and 660 m in width. Measurements are done w ith GSGSG probes, and phase noise is measured using HP/Agilent 70420A baseband phase noi se test set. The thr ee control bits are set externally. 1.8V supply voltage is used with about 11mA current flowing through the core VCO. Figure 5-4. Measured conversion loss versus offset frequency. While VL is set to 1.8 V, VCO is operating in low band; while VL is set to 0 V, VCO is operating in high band. Each of the bands could be subdivided into four sub-bands that are controlled by switching on and off capacitors. In each of these two bands, two capacitors are switched on and off using Vc1 and Vc2. Varactors are tuned from 0 V to 1.8 V. For low band, 101 001 Offset Frequency (Hz) 110 010 000 011 111 100

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112frequency of the VCO could be tuned from 2. 89 GHz to 3.45 GHz, which is about 17.7 % of tuning range; for high band, frequency of the VCO could be tuned from 3.59 GHz to 4.3 GHz, which is about 18 % of tuning range. The operati ng frequencies of the VCO are about 7 % lower compared to simulation ones due to the error in estimating capacitances of traces. Also, some pieces of traces attribute certa in amount of inductance are not considered when doing the simulation. Figure 5-5. The tuni ng capability of the switching band VCO. Measured phase noise is about -110 dBc/Hz at 1 MHz away from the oscillating frequency. For the highest two bands, the phase noise drops to about -105 dBc/Hz at 1MHz separation. Measurement phase noise results are about 5 dB wo rse than the simulation ones also due to metal parasitics in the layout. Graphs of measured phase noi se are shown in Figure 5-4. Eight plots are presented for each of the sub-bands. Figure 5-5 illustrates the tuning frequency range of each different control settings. Four sub-bands in low band have frequencies covering each other a little bit and same as the four sub-bands in high band. In summary, an eight-band digitally controlled band-switching VCO using 0.18 m CMOS 110 010 100 000 111 011 101 001 VC1VC2VL

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113technology is demonstrated. Desi gn methodology is described. Th e measurement results show that the VCO covers two bands of 2.9 3.45 GHz and 3.6 4.3 GHz. Phase noise of the VCO stays constant around -110 dBc/Hz at 1 MHz offset across all bands. Table 5-1 summarizes the performance of this band-switching VCO. Table 5-1. Performance summa ry of the band switching VCO ` 5.2 Introduction to MB-OFDM UWB Frequency Synthesizers Due to the requirement of high data rate wire less transmissions, large spectrum bandwidth was released for this purpose. Because of the extremely crowded spectrum usage at lower GHz frequencies, FCC released 3-10 GHz spectrum for the use of ultra-wideband (UWB) applications. Couples of different groups are working on setting up standards for use of this wide spectrum. Two standards occupy most of the markets now One of which is based on the pulse-wave transmission, which transmit ultra short pulses (ultra-wide bandwidth) as digital signals. These kinds of systems were used in sensor applica tions or radar applications for military purposes. The other group of people is trying to modify the existing mature standards people use on wireless communication and fit them into ultr a-wideband systems so th at the developing time DC1DC2DL Freq (GHz) Tuning Range (%) PN@100KHz (dBc/Hz) PN@1MHz (dBc/Hz) 110 2.89-3.08 6.4 -88.31 -108.98 010 2.97-3.18 6.83 -88.04 -111.36 100 3.01-3.22 6.7 -86.71 -108.29 000 3.19-3.45 7.8 -89.34 -111.75 111 3.59-3.86 7.13 -88.35 -110.24 011 3.68-3.97 7.58 -83.54 -111.27 101 3.83-4.14 7.78 -73.74 -105.51 001 3.93-4.3 8.99 -85.31 -106.23 *C1 is on/off for DC1=1/0; C2 is on/off for DC2=1/0; L is on/off for DL=0/1

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114might be shorter. One of the most important standards come out is the use of multi-band OFDM signals [46]. This alliance adapted the mature OFDM technology that is used in IEEE 802.11a and 802.11g. First of all, the whole ultra-wideba nd is divided into several narrower bands, and each narrow band signals are transmitted using the OFDM modulation. The transmission data rate of this specification is ranged from 53 Mbps to 480 Mbps depends on the coding schemes and operating distances. Table 5-2. Center freque ncies plan for OFDM UWB Band Group 1 2 3 4 5 BAND_ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Center Freq (MHz) 3432 3960 4488 5016 5544607266007128765681848712 9240 976810296 Figure 5-6. Frequency plan chart of the OFDM UWB. The whole 3-10 GHz band is divided into 14 sub-bands. Each sub-ba nd has bandwidth of 528 MHz. Table 5-2 lists all th e central frequencies of each of sub-bands and Figure 5-6 illustrates the frequency planning of this OFDM UWB system. The 14 sub-bands are categorized into five groups. Band group 1 is mandatory when developing MB-O FDM devices and other four band groups are optional. The use of those f our bands is reserved for future use and it has more flexibility when designing the devices. Most of the developments in this system today are

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115major focused on band group 1 because at lower fre quencies chips could be made on mature and cheap CMOS technology. Switchi ng between the frequency ba nds is controlled by the time frequency coding. The time fre quency coding provides frequency diversity gain and robustness to interferences. The maximum distances at wh ich the multi-band OFDM system can achieve package error rate of 8 % for a 90 % link success probability are listed in Table 5-3. The testing was done under different channels from all white Gaussian Channel (AWGN) to channels with large delay spread. The operating distances ar e in the range of 10 meters, which is far enough for short range high data rate transmission systems such as the linking the DVD player to a digital television. Table 5-3. Operating distances for OFDM UWB system with di fferent channel conditions and date rate Range AWGN LOS : 0-4m CM1 NLOS : 0-4m CM2 NLOS : 4-10m CM3 RMS delay spread : 25ns CM4 110 Mbps 21.4m 12.0m 12.0m 11.5m 10.9m 200 Mbps 14.6m 7.4m 7.1m 7.5m 6.6m 480 Mbps 9.3m 3.2m 3.0m N/A N/A Figure 5-7 illustrates timing diagram of band switching opera tions between the different sub-bands of an MB-OFDM UWB system. It is noti ced that the guard interv al, which also equals the transition time between bands to bands, has only a period of 9.5 ns. There are several ways to achieve frequency hopping for a frequency synthesize r at this kind of speed First is the use of ultra fast settling time phase-lock-loops (PLLs). The second method is to use multiple PLLs and select outputs from different PLLs when the cente r frequency has to be changed. Third, using upconversion mixers, down conversion mixers, and sw itches in combination to make the selection

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116of frequencies fast. A briefing on how the prev ious designs were done for such a frequency synthesizer will be given in the following sections. Figure 5-7. Frequenc y hopping diagram between the different bands. 5.2.1 PLL with an Ultra Fast Settling Time PLL is usually implemented as a frequenc y synthesizer in a communication system because of its capability to gene rate a stable output frequenc y. Since the 528 MHz frequency resolution in MB-OFDM UWB systems is pretty wide, the use of integral-N frequency synthesizers would suffice. Figure 5-8. Block diagram of an integral-N frequency synthesizer. Figure 5-8 shows the block diagrams of an integral-N frequency synthesizer. Basic operation of an integral-N frequency synthesizer could be briefly desc ribed as follows. The PFD Loop Filter Divider VCO

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117divider divides the frequency of VCO output signal N times and compares its phase with the input reference clock in phase fr equency detector (PFD). PFD generates pulses if there are phase differences between the two signals. Pulses from PFD are filtered thr ough a low pass loop filter and generates a control signal which the magn itude is determined by the amount of phase difference. The control signal then controls the output frequency of the VCO. Phases of signals after the divider and the input reference clock would be locked through negative feedback, and this also guarantees the output signal frequency would be exactly equal to N times the frequency of the input reference signal. Figure 5-9. Block diagram with mathem atical modeling of integral-N PLL. Figure 5-9 shows the block diagram of an inte gral-N PLL with frequency domain model of each block [47]. For a second order, type-II freque ncy synthesizer, the frequency domain transfer function is: p zw s w s sC s H / 1 / 1 1 ) ( (5-4) where C is determined by the values of the capacitors in the loop filter and wz and wp are zero and pole frequencies in the transfer function. The open loop gain is 1 VCO Icp H(f) jf kv N 1 Loop Filter Charge Pump PFD out in Divide r +

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118 Ns s H I K s Acp v) ( ) ( (5-5) ,and the closed loop gain is ) ( 1 ) ( ) ( s A s A s Gin out (5-6) Figure 5-10. Settling behaviors of (a) a step response, and (b) clos ed loop frequency response, of a fast switching PLL. Settling behavior and stability analysis c ould be got from these equations. Figure 5-10 shows the closed loop step response and the clos ed loop frequency response. These graphs were generated using PLL Design Assistant software by Michael Perrott from MIT. This PLL has settling time about 10 ns. However, the cutoff fre quency which determines the 3 dB roll off point in the frequency response is at 500 MHz. Refere nce frequency is typically about 10 times higher than the cutoff frequency and it will lead th e reference frequency as high as 5 GHz. The implementation with a reference signal running at 5 GHz would usually consume a lot of power on CMOS chips and make this solution unattractiv e since the phase detector and charge pump ( b ) ( a )

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119circuits would not work very well at this hi gh frequency unless they draw huge current. Also, from Section 5-1, it can be seen that it is ex tremely difficult to have a VCO running through all the UWB bandwidth. Therefore, the traditi onal integral-N PLL methodology is out of consideration while designing UW B frequency synthesizers. 5.2.2 Switching Between Multiple PLLs Figure 5-11. A MB-OFDM UWB frequency synthesizer using multiple PLLs in [48]. Since the traditional PLLs are not fast enough to satisfy the timing requirement of MBOFDM UWB system as shown in the previous secti on, one of the straight forward way is to use several PLLs running at different frequencies and select from them using the switches in a frequency synthesizer. For example, if three frequency bands are required, three PLLs will be implemented and switched between each other in a frequency synthesizer according to digital control signals. In [48], Razavi etc. presented a thr ee-band MB-OFDM UWB frequency synthesizer. Figure 5-11 shows the block diagram of the implementation. Three PLLs are shown in the block diagram. Selecting time between them is fast enough to satisfy the requirement of the specification. This design only generates the three frequenc ies in group 1 bands. If more

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120frequency bands have to be implemented in the desi gn, then more than three PLLs have to be put on the same chip. In the standard, 14 bands are spreads over 3to 10-GHz. Using this architecture, 14 PLLs have to be implemented, wh ich is unrealistic and the whole chip area will be bulky and consumes a lot of power. Figure 5-12. A MB-OFDM UWB frequency synthe sizer using two swappi ng PLLs. Illustrations of (a) timing diagram, and (b) simplified block diagram, in [49]. A smart way to reduce the number of PLLs is to effectively utilize the time between each symbol for PLL to reach its steady condition. Figure 5-12 [49] illustrates one of the implementations of this idea. The transition of two switching bands is 9.5 ns, which is too short for a PLL to response. However, the symbol period of 312.5 ns is long enough for a PLL to stabilize. Two PLLs are used alternatively in th is synthesizer. While one PLL is set to a certain frequency, the other PLL has already started to tune to the next frequency. Therefore, the settling time is relaxed from 9.5 ns to about 320 ns wh ich greatly reduce the speed requirements of a PLL with the use of one extra PLL. (a) (b)

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1215.2.3 Switching Between Different Frequencies Using Mixers The most popular scheme used in the designing of UWB frequency synt hesizers is to use mixers to switch between different bands. Since mixers are not used in feedback systems like PLLs, the settling time only depends on the loading capacitances and the currents to charge them. A useful architecture is the use of single-sideband (SSB) mixers that can generate two bands, one of up-side band and one of lower-side band. As a result, mixers are extensively used in the multi-band OFDM UWB frequency synthesizers. Figure 5-13 illustrates two of the implementations from [50] and [51] using mixers in frequenc y synthesizers. Through careful frequency planning and proper desi gn, only one PLL is necessary in the frequency synthesizer. In [51], several different frequency plans usi ng this kind of technique are proposed, and the publication gives us an idea of the trad e-offs between different schematics. Figure 5-13. Two implementation of MB-OFDM UWB frequency synthesi zers in (a) [50], and in (b) [51]. 5.3 The Proposed OFDM UWB Frequency Synthesizer The main problem in using single-side-band mixers in a frequency synthesizer is the spurious tones generated from the mixers. While using a PLL, the spectrum of the output signal is a pure sinusoidal wave. However, signals from a mixer suffer from the nonlinearities of the (a) (b)

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122mixer itself. The output signal will not be a clean sinusoidal signal but a signal with large harmonic terms and intermodulation terms. Spuri ous signals in a freque ncy synthesizer would degrade bit error rate (BER) performan ce comparing to pure sinusoidal waves. Under most conditions, spurious signals are far away from the target frequencies and they could be easily filtered out. However, in MB -OFDM UWB frequency synthesizers, filters with very wide tuning range have to be designed sinc e the whole frequency span is 7 GHz wide. A lot of filters might necessary be implemented either on chip or off chip. Therefore, the most serious problem about designing a MB-OFDM UWB fre quency synthesizer is to clean the output spectrum. 5.3.1 Effect of Spurious Signals in Freque ncy Synthesizers on BER performance In order to get the ideas of how spurious signals affect BER perf ormance of a MB-OFDM UWB system, simulation is performed in Agilent Advanced Design System (ADS). Figure 5-14 illustrates the diagram of spurious signals generated from a frequency synthesizer. Signal at f0 is the desired LO frequency; signals at fu and fl are the upper-side band spurious signal and lowerside band spurious signal which are mainly gene rated due to the nonlinearity of mixers. The desired frequency has signal amplitude of 0 dB, wh ich is a reference to the spurious signals and the spurious signals have th e signal amplitude of A dB. Figure 5-14. Spurious signals of a frequency synthesizer. 0dB AdB AdB f 0 fu f l

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123Figure 5-15 shows the simulation block diagra m of the effect on BER due to spurious signals in a MB-OFDM UWB system In this simulation, direct conversion receiver is assumed since this architecture is easie r to be integrated on a singl e chip without many external components. UWB OFDM function blocks generate OFDM signals through IFFT, and then the signals are up-converted to the RF frequency using spurious contaminated LO signals. In this simulation, three transmitters are added together to represent the input signal to the receiver. The transmitter in the center represents the de sired signal with LO at frequency f0, and the other two transmitters represent interference signals due to spurious tones from LO at frequency fh and fl. Spurious signals have following gain stages of A dB. At the receiving end, input signals with interferences are down-converted to baseband through a down-c onverting mixer and a LO at frequency f0. Baseband signal is further processed by FFT and the data are recovered. BER detector detects the error due the interferen ces made by spurious tones in the frequency synthesizer. Figure 5-15. Simulation diagram of effect on BER due to spurious si gnals in a frequency synthesizer. UWB OFDM LOspu1 A UWB OFDM LO 1 UWB OFDM LOspu2 -A UWB OFDM Receiver LO BER Detector T X RX

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124Figure 5-16 shows the simulation results of BER performance versus signal to noise ratio with different signal levels of spurious tones in the frequency synthesize r. BER degradations due to the spurious signals are compared with th e perfect OFDM system. It can be shown while interference gets larger, BER de grades more as expected. Assume that only 1db degradation in BER is acceptable due to interference tones so that the whole system performance does not change a lot. This figure indica tes that at least 25 dB of suppr ession to the desired signal on spurious signal is necessary. Figure 5-16. Simulation result of BER with various spurious signal levels. However, the scheme in the simulation above is optimistic. In a communication system, usually the interferences magnitude is much hi gher than the desired signals magnitude because the interference could be much closer to the receiver. From the specification [46], transmitted power of a MB-OFDM UWB signal is set to have a limit of -9.9 dBm. While the OFDM UWB system is set in the highest speed mode, the sens itivity of the receiver is -80.5 dBm, which is measured when the transmitter and receiver are 10 meters away. Assume that the interference is 0 2 4 6 8 10 12 14 10-4 10-3 10-2 10-1 EbNo(dB)BER BER/ No interference BER/ Interference 25dB lower BER/ Interference 20dB lower BER/ Interference 15dB lower BER/ Interference 10dB lower

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125put 1 meter away from the receiv er. Under the condition of line of sight (LOS), the path loss of the interference signal is 44.2 dB. Therefore, the input signal strengt h of the interfer ence signal is -54.1 dBm (output power-path loss at 1 m = -9.9 dBm 44.2 dB). In order to make the system work, the interference signals with input signal le vel of -54.1dBm and the desired signal with signal level of sensitivity(-80.5 dB m), the down-converted signals st ill have to satisfy the 25 dB suppression from the conclusion of previous secti on. Therefore, the spurious LO signal from the frequency synthesizer should be 51dB lower th an the LO signal (-54.1 dBm + spurious level suppression < -80.5 dBm 25 dB). Figure 5-17 illustrates the testi ng environment that described above. As a summary, the spurious signals from the frequency synthesizer should be more than 50 dB lower than the desired LO signal. Figure 5-17. Testing environmen t of the spurious signal test. 5.3.2 Scheme of Frequency Generation The frequency generating plan has to be made. This depends on how many frequency bands are planned to be generated and how many PLLs will be implemented. Table 5-4 lists all Receiver Transmitter Interference1 Interference2 1 meter 1 meter 10 meter

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126the frequencies that are defined in the MB-OFDM UWB standard. Each band has 528 MHz interval between each other. After some simple mathematical manipulation, it is found out that all of the frequencies are the multiples of 264 MH z, and the ratios between the LO frequency and 264 MHz are shown in the table. Therefore, 264 MHz seems to be a good choice as the reference frequency. If 264 MHz is used as the refere nce frequency, the only problem is that the frequencies are all odd multiples of the reference frequency. In circuit design, divide-by-2 is easier to be implemented in IC at high frequencie s, thus these frequencie s could not be generated directly using the reference signal. Table 5-4. Relation of LO fr equencies of different bands The easiest way to generate all the listed fre quencies is to use 528 MHz as a reference and make it multiply certain times to the output frequencies. Since it is easier to generate a frequency that is even multiple times of the reference frequency, the wanted frequencies are generated through upor down-converting mixers. Th e scheme is shown in Figure 5-18. The frequency generating scheme is shown in Figure 5-18. Fourteen frequencies are divided into four groups, and each group contains four frequencies except the last group which contains two frequencies. In this design, only the frequencies in the first three groups will be generated. The central frequency of each group will be generated at first, and the four frequencies will be made through mixers by addi ng or subtracting either 264 MHz or 792 MHz. VCO generates the central frequency of gr oup three at 8448 MHz thr ough a PLL with the reference frequency of 528 MHz. The center freq uency of group one comes out after a divide 8448 MHz by two. As for the center frequency of group two, it is generated by adding the center Center Freq (MHz) 3432 3960 4488 50165544607266007128765681848712 9240 976810296 N (Freq264M) 13 15 17 19 21 23 25 27 29 31 33 35 37 39

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127frequency of group one and group three and then divides it by 2. This scheme is easily implemented with the only use of mixers divide-by-2 circuits, and switches. Figure 5-18. Scheme of the frequency genera tion for a MB-OFDM UWB frequency synthesizer. 5.3.3 Block Diagram of the Frequency Synthesizer Figure 5-19 is the block diagram of the proposed frequency synthesize r. Output frequency of the PLL is set to be 8448 MHz. After it divides by two, 4224 MH z which is the center frequency of group 1 appears. Up-converting mixer mixes 4224 MHz and half of 4224 MHz and generates 6336 MHz which is the center frequency of group 2. A th ree inputs selector switched between the different central frequencies. Four frequencies in each band groups are generated by up-converting or down-converting mixers using 792 MHz and 264 MHz signa ls which are also generated on chip through the dividers. In this way, there are 3 times 2 times 2 which is 12 different frequencies will be generate d from this frequency synthesizer. 10296 9768 9240 8712 8184 7656 7128 6600 6072 5544 5016 4488 3960 3432 528x7 528x8 528x9 528x10 528x11 528x12 528x13 528x14 528x15 528x16 528x17 528x18 528x19 Divide-by-2 VCO Divide-by-2 Group 1 Group 2 Group 3 Group 4

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128 Figure 5-19. Block diagram of the MB-OFDM UWB frequency generator. 5.4 Spurious Signals from the Frequency Synthesizers Some nonlinear properties of the mixer and th e signals leaking thr ough the selectors or silicon substrate cause spurious signals which will degrade the perfor mance of recovering the data. Some of the mechanism of spuri ous signals will be discussed below. 5.4.1 Spurious Signals from Mixers Figure 5-20 shows some of the possible spurious signals that occur at the output of a mixer. The RF input of the mixer is at frequency w1 a nd w1; the LO input is at frequency w2. w1 is cause by the leakage of the selector and the isolati on of the selector equals to sel(dB). From the output, except the desired output at frequencies of w2+w1 and w2-w1, it also contains several other frequency components. LO signals is leaking to the output with amplitude A2-IsoLO (dB), where IsoLO is the isolation of the mixer, at frequency w2. The mixing of the leaking signal from the selector and the LO with amplitude of G (A1-sel), where G is the gain of the mixer. The rest signals in Figure 5-20 are third-order pr oducts, e.g. w2-(2w1-w1) caused by the mixer. PD CP /2 264MHz 8448MHz 2112MHz /8 /2 6336MHz SH SSB Mixer 4224MHz /N /8 792MHz

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129 Figure 5-20. Spurious signals from a mixer. The methods that we used on the freque ncy synthesizer are listed as follow: 1. Sub-harmonic mixers are used so that the fr equency of LO leakage is far away from the desired frequency. 2. Third-order nonlinearity has to be reduced. Th erefore, passive mixers are used instead of active mixers with the trad e-off of the converting gain. 3. The imbalance of the quadrature signals in the single sideband mixers. 4. The odd-order harmonics of the square waves which are generated from the digital dividers or buffers. 5.4.2 Sub-harmonic Mixers In this design, sub-harmonic mixers are used instead of fundamental mixers in order to reduce the LO leakage and other higher order sp urious signals. Demonstration of a CMOS subharmonic mixer is in Chapter 4. Figure 5-21 reviews the operating of a subharmonic mixer. Figure 5-21 (a) shows the schematic of the load of a subharmonic mixer. With the shifting between the LO signals with different phases as shown in Figure 5-21 (b ), the outcome is like using an LO frequency that is twice as its real frequency. The Use of subharmonic mixers greatly separate s the frequency distance of LO frequency and output frequency. For example, if the output frequency needed is at 8712 MHz, for a A1-sel w1 A2 w2 A2-IsoLO w2 w2+w1 A1G w2+w1 A1 w1 G(A1-sel) w2-w1 w2-w1 w2-(2w1-w1) w2-(2w1-w1) w2-(2w1-w1) G(A1-sel) A1G w2-(2w1-w1)

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130fundamental mixer the LO should be at 8448 MH z which is very close to 8712 MHz; for a subharmonic mixer the LO will be at 4224 MHz. Under this circumstances, the LO leakage would not be a problem since the spurious signals could be easily filtered away. However, using subharmonic mixers adds the complexity in the design. We need multiple phases of the LO signals for th e use of mixers. Normally, subharmonic mixers need four phases of the LO signals. However, for up-converting mixers or down-converting mixers, four extra phases are necessary since single side band mixers need Iand Q-quadrature signals. As a result, totally eight phases have to be generated on chip. Figure 5-21. Load of a subharmonic mixer. Also, in order to reduce the inter-modulation te rms from the mixers, mixers with higher linearity are preferred. Basica lly there are two categories of mixers: active mixer and passive mixer. Passive mixers usually have higher linearity compared to active mixers. Therefore, passive mixers are chosen to be used in the fr equency synthesizer design because of its better linearity. RF+ RFIF+ IFLO_0o LO_180o LO_0o LO_180o LO_90o LO_270o LO_90oLO_270o (a) (b)

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1315.4.3 Filtering Out the Spurious Signals The other source of the spurious signals is from the single-side-band (SSB) mixers. While quadrature signals are fed into the SSB mixer, th e imbalance in the amplitude and phase of the input signals and the imbalance in the mixer ga in and phase will make the cancellation of the other side band imperfect. The block diagram of a SSB is shown in Fi gure 5-22 [52]. A SSB mixer is composed of two identical mixers. These two mixers are fed with quadrature signals of w1 and w2. In the figure, 1 2 1, and 2 represent the imbalance in phase and in magnitude. These imbalances might come from the quadrature signal generator or the mixer itself, or the combination of the two. The output signal could be represented as ) sin( ) sin( ) 1 )( 1 ( ) cos( ) cos(2 2 1 1 2 1 2 1 t w t w t w t w OUT (5-7) ] ) sin( ) [sin( 2 ) cos( 2 ) cos( 2 ] ) sin( 2 ) sin( 2 )[ 2 1 ( ) cos( 2 ) cos( 2 )] sin( ) cos( ) sin( ) cos( ) cos( ) )[cos( 2 1 ( ) cos( ) cos( )] cos( ) )][sin( cos( ) )[sin( 1 ( ) cos( ) cos(2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 2 2 1 1 2 1 2 1 1 2 1 2 1 2 2 2 1 1 1 2 1 2 1 2 1t w w t w w t w w t w w t w w t w w t w w t w w t w t w t w t w t w w t w w t w w t w w t w t w t w t w t w w t w w In equation (5-8), only the first term is th e wanted signal, and the rest terms are the spurious signals from the imbalance of the ci rcuitry. It shows that while the upper-side-band mixer is designed, lower side-band signal compone nt also exists, and vice versa. The power ratio between the signals to spurio us signals ratio from (5-8) is 2 2 2 1 2 11 ] ) [cos( ] ) [cos( t w w Pow t w w Pow (5-9) ( 5-8 )

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132Figure 5-23 illustrates (5-9), showing the signal power ratio between the wanted signal and the un-wanted signal, which is isolation, of a SSB mixer due to the imbalanced inputs. The numbers on the graph shows the isolati on in dB. With typical imbalance of05 %, 5 the signal ratio is dB wanted Un Wanted 20 94 09 0 05 0 12 2 (5-10) Figure 5-22. Single-side-band mi xers with imbalanced inputs. Obviously, this isolation is not good enough for this frequency synthesizer. If 30 dB of isolation is necessary, amplitude imbalance has to be within 3% and phase imbalance has to be within 2o. There are two ways to solve this problem, one is to reduce the imbalance from the quadrature generator and the mixers, and the other one is to use filtering at the post processing at the output of the SSB mixer to filter out the unwanted bands. Calibration is usually implemented on chip to increase the quadrature accuracy. Howeve r, the digital control part is pretty complex. As for the filtering, if the two bands are close wi th each other, then a filter with very high-Q value is necessary, which is also unavailable on chip. However, if the two bands are far away, then filtering might be a good choice to reduce the output spurious signals. ) cos(1t w) sin( ) 1 (1 1 1 t w) sin( ) 1 (2 2 2 t w ) cos(2t w 090 ) sin( ) sin( ) 1 )( 1 ( ) cos( ) cos(2 2 1 1 2 1 2 1 t w t w t w t w

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133 Figure 5-23. Signal isolation of SSB mixer due to imbalanced inputs. Figure 5-24. Filter (a) upper-side-band, and (b) lower-side-band, of the outputs of a SSB mixer. The two scenarios of filtering a SSB mixer are shown in Figure 5-24. If the output is selected to the lower-side-band, then a low pass filter (LPF) in Figure 5-24(a) has to be used to filter the higher frequency; if the output is selected to the upper-side-band, then a high pass filter (HPF) in Figure 5-24(b) has to be used to f ilter the lower frequency. Therefore, two kind of filters need to be implemented, a LPF and a HPF, and a switch is necessary to switch anyone of them depends on which side band is wanted. Also multiple orders of the LPFs and HPFs might be needed if the isolation requirement is stringent. It seems the straightforward way filtering using LPFs and HPFs are a little bit complex and not efficient. Poly phase filter might be very usef ul in this kind of situation. Although the idea of LPF HPF (a) (b) 10 15 20 25 30

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134polyphase filters was proposed decades ago, the ga in of popularity was afte r [53] and [54], which designed receivers and mixers us ing polyphase filters on chip to obtain the performance of high image rejection. Figure 5-25. A polyphase filters diagrams of (a) schematic, and (b) signal components. Polyphase filters utilize the H ilbert Transform so that it is able to filter the negative frequency. Negative frequency he re physically means the phase of the input frequency. Figure 525 (a) illustrates the schematic of a polyphase fi lter. Multiple phases of the inputs are inserted into the filter. Mathematically, f our input signals could be represen ted as a superposition of four orthogonal basis functions as shown in Figure 5-25 (b). As shown in the figure, an unbalanced input could be decomposed into the combinati on of groups of signals with different phase relationship, which are counter clockwise signal components (ai in the figure), anti-polar components (bi in the figure), clockwise signal components (ci in the figure), and a dc component (di in the figure). These four components also form the basis functions of the incoming signal set. The polyphase filter will on ly passes the counterclockwise components and filters out the clockwise component. As for the signals of bi and di, they can be eliminated through sensing the outputs differentially. This sp ecial property of the poly phase filter makes it O1 O3 O2 O4 1 1 V2 2 V3 3 V4 4 V = + + + (a) (b)Unbalanced Input i1 i2 i3 i4 a1 a2 a3 a4 b1, b3 b2, b4 c1 c2 c3 c4 d1, d2, d3, d4(b)

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135very useful in filtering the image signal since the image signal has the different phase relationship with the wanted signal. Figure 5-26. Simulation result of a three-stage polyphase filter. A test on a polyphase filter is made in the ADS software. Figure 5-26 shows the simulation results of the filter. It is a three-stage polyphase filter, and the filter frequency is set to be about 10GHz. The left graph shows the filtering response for only a one-stage filter. It can be see that the roll of at -10GHz is sharp to about -80dB with perfect components. However, due to the variation in the components on chip and the band width requirement, higher-o rder filters are used. Right graph shows the filtering re sponse of the three-stage polypha se filter. It shows that the filtering is so deep to -100 GHz at around -10 GHz. Figure 5-27 shows the simulation schematic of a single-side-band mixer with a post polyphase filter filtering the image signal. There are 5o phase difference and 5% amplitude -10-50510 -1515 -100 -50 0 -150 50 freq, GHz -10-50510 -1515 -80 -60 -40 -20 0 -100 20 freq, GHz0 10 VOutI+ 0 290 V0 3180 V 0 4270 VOutIOutQ+ OutQ-

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136difference in the mixer and the quadrature generato r. From Figure 5-28, it shows that without the polyphase filter, the isolation of the image freque ncy and the wanted frequency is about -24 dB. With the polyphase filter, the isolation increases to -40 dB. This is 15 dB improvements due to the polyphase filter. Figure 5-27. Polyphase filter wi th a single-side-band mixer. Figure 5-28. Simulation results show the effect of a polyphase filter. 5.4.4 Square Wave Harmonic Reduction The other source of spurious signals from a fr equency synthesizer is from the harmonics of square waves. Figure 5-29 shows three of the lo wer orders of the harmonics. After doing Fourier t wIFcost wLOsint wIFsin + 090 Polyphase I+ IQ + Q 67891011121314 51 5 -200 -150 -100 -50 0 -250 50 freq, GHz m10 m11 m11 ind Delta= dep Delta=-24.434 delta mode ON 5.280E8 67891011121314 515 -100 -80 -60 -40 -20 0 -120 20 freq, GHz m8 m9 m9 ind Delta= dep Delta=-39.924 delta mode ON 5.280E8

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137transform of a square wave, odd order terms come out. The amplitudes of these terms are 1/3, 1/5 for 3rd order and 5th order, respectively. Since th e signals from dividers and inverter buffers are all square waves, these harmonics are needed to be filtered out since it would cause spurious signals in a frequency synthesizer. Figure 5-30 shows the square wave effect on a SSB mixer. Here, only the 3rd order and 5th order terms are considered since they are closer to the output frequency and their amplitude are the bigger than higher order terms. As in the fi gure, for a lower-side-band mixer, the 3rd, 7th, 11th orders of the IF signal will be appear on the upper side, and 5th, 9th, 13th orders will be appear on the lower side. Since polyphase filt ers are put after the SSB mixers, we can check if the filter can filter the spurious terms due to these harmonic terms. Since four phases are needed for a polyphase filter, for a lower-side-band mixer, the wanted RF frequency would be t w w t w t w t w t wIF LO LO IF LO IF) cos( ) sin( ) sin( ) cos( ) cos( (5-11) t w w t w t w t w t wIF LO LO IF LO IF) sin( ) cos( ) sin( ) sin( ) cos( (5-12) for in-phase signals and quadratur e signals. Note that these signals are differential, therefore there are totally four signals from these equation s and they will be the inputs to the polyphase filter. For the 3rd order harmonic, the output terms will be t w w t w t w t w t wIF LO LO IF LO IF) 3 cos( ) sin( ) 3 sin( ) cos( ) 3 cos( (5-13) t w w t w t w t w t wIF LO LO IF LO IF) 3 sin( ) cos( ) 3 sin( ) sin( ) 3 cos( (5-14) Figure 5-29. Harmonics of a square wave. Ts 3 Ts 1 Ts Fourier f Ts 51 1/3 1/5

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138 Figure 5-30. Effect of square wave harmonics on SSB mixers. Figure 5-31. Square waves with different 45o phase differences and the resulting waveform after summation. The equation (5-13) and (5-14) show the out put components of a SSB mixer due to 3rd order harmonic term from the IF. The filtering of a polyphase filter comes from the different phase relationship between the wanted signal and the spurious signal. Co mparing these equations, it could be seen that the phase relationship are the same for both the want ed signals and spurious signals. Although the equations are for the 3rd orde r terms, they could also be modified for higher order terms. Therefore, polyphase filters could not filter the spurious signals coming from 0.5 0.0 1.0 0.5 1.0 0.0 1.5 0.5 0.0 1.0 2468 010 1 2 3 0 4 time, nsec ), (a) (b) (c) (d) 1s t order 7s t order ) 5 cos( ) 3 cos( ) cos( t w t w t wIF IF IF ) sin( t wLO) 5 sin( ) 3 sin( ) sin( t w t w t wIF IF IF ) cos( t wLO 090 t w w t w w t w wIF LO IF LO IF LO) 5 cos( ) 3 cos( ) cos( f wLO-wIF wLO+3wIF wLO-5wIF wLO+7wIF wLO-9wIF

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139the harmonics of the IF signals. Some other me thods have to be implemented to reduce these harmonics. The straight forward way is still to put a filte r after the SSB mixer. However, for the same reason, the filter has to be high-Q if the freque ncy separation is narrow. The other way that we can use is to reduce the harmonics us ing the methods in [55] and [56]. ))] 5 sin( ) 5 (cos( 5 1 )) 3 sin( ) 3 (cos( 3 1 )) sin( ) [(cos( 2 ) ( wt wt wt wt wt wt t a (5-15) )] 5 cos( 5 1 ) 3 cos( 3 1 ) [cos( 2 2 ) (wt wt wt t b (5-16) ))] 5 sin( ) 5 (cos( 5 1 )) 3 sin( ) 3 (cos( 3 1 )) sin( ) [(cos( 2 ) ( wt wt wt wt wt wt t c (5-17) ) cos( ) ( ) ( ) ( ) ( wt A t c t b t a t d (5-18) The harmonic reduction circuitr y sums a square wave with different phases to cancel out 3rd and 5th order terms. Figure 5-31 illustrate the operation of harmonic cancellation circuit. As shown in the figure, three phases with 45o phase deviation are necessa ry. Equations (5-16), (517), and (5-18) shows the Fourier series up to the 5th order term They represent square waves with phases of -45o, 0o, +45o, respectively. Once these three te rms are added, the summation of them is as (5-19) and Figure 5-31. It can be s een that it perfectly cance led out the 3rd order and 5th order terms from a square wave in the trad e-off that multiple phases of square waves are needed. The spectral result of the harmonic cance ling circuit is shown in the right graph of Figure 5-31. It is clear that 3r d and 5th order are ideally gone. 5.4.5 Implementation of a Harmonic Reduction Circuit For a harmonic reduction circuit, not only quadrature signals ar e necessary, but also signals with 45o phase. There are several ways to get multi phase signals. The eas iest way is to use differential ring oscillators as shown in Figure 5-32 [57]. Howe ver, the frequency limitation of

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140ring oscillator is usually not very high. In this frequency synthesi zer, the oscillator needs to be run at almost 5GHz. Therefore, ring oscillator is not a good choice here. Figure 5-32. Using ring oscillator to generate multiphase signals. Another way to generate multiphase signals is to use frequency di viders. A divide-by-2 circuit could generate quadrature signals of the incoming signal. Figure 5-33 shows a CMOS divider proposed in [58]. From the figure, the ph ase relationships of the outputs are noted on the graph and it is known which node has zero phases and which node is quadrature and so on. In other words, the phase relationships with each other are well determined through a divide-by-2 circuit. Figure 5-33. Use a divider to ge nerate quadrature signals [58]. As mentioned earlier, 45o phase has to be used in th e harmonic reduction circuitry. Therefore, two dividers could be cascaded to pr ovide those phases as shown in Figure 5-34. If multiple phases of frequency f are needed, the input signal of the first divider should be at IN+ IN0o 180o 90o 270o 0o 180o 270o 90o

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141frequency four times of f. The in-phase and quadrature phase si gnals from the first stage divider drive the latter stages of dividers, and each latte r divider will generate four phases. Using this way, it can get eight phases from the divider chain. Figure 5-34. Cascade dividers for 45o phase difference. However, only the phase relationships of the four local inputs from one divider can be determined. There are no internal feedback mech anism let us know the relationships between the two dividers at the output. For exam ple, if one node of a divider is set to be as zero degree, then any of the four outputs of the other divider could have 45o phase difference compared to the zero degree one. For harmonic reduction circuit, the ex actly relationship of the phases have to be determined. Therefore, extra testing circuits have to be added to test the phase relationship between the output nodes. Figure 5-35 lists the waveforms of signals with eight different phases. The relationships of these phases are shown clearly on this figure. Four signals from the top ha lf graph are from the first divider, and four signals from the bottom ha lf graph are from the second divider. Since the relationship between the two divide rs is unknown, testing has to be done. One of the easiest ways Divider Divider Divider IN 0o 90o 180o 270o 90o 180o 270o 0o T 2T 4T

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142is to use 0o and 90o signals as sampling signals on all the f our phases from the second divider. As shown in Figure 5-35, the sampling results of thes e phases are different. Th erefore, simple logic circuit could be used to distinguish which one has only 45o phase difference to the reference of 0o. The circuit implementation is strai ghtforward as shown in Figure 5-36. Figure 5-35. The phase detection circuitry. Figure 5-36. Phase detection ci rcuit after divide-by-2 blocks. Divider 2 01 00 10 11 CLK D Q CLK D Q 0o 90o Test IN Control 0o 90o 180o 270o 45o 135o 225o 315o Divider 1

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1435.5 Schematics and Simulation Results Figure 5-37 shows the overall schematics of the MB-OFDM UWB fr equency synthesizer. In this section more detailed simulation result s and schematics will be shown. There are four control signals that set the output frequency. Two bits of the control signals determine which frequency would be selected from the big switc h shown in Figure 5-37, one bit of the control signal sets the upper side band mixing or lower si de band mixing, and the remaining one bit sets the IF mixing frequency whether be 264 MHz or 792 MHz. Figure 5-37. Schematic of the MB -OFDM UWB frequency synthesizer. The chip is designed and simulated using an UMC digital 90nm low-k CMOS technology. Only two passive spiral inductors are implem ented on the chip using 3-metal stacked round shape inductor discussed in Chapter 2. PD CP 264MHz QVCO 8448MHz/4 1056MHz 3168MHSH SSB Mixe r /24224MHz /N /4 I Q /2 /2 2112MHz sel1 Polyphase Filter 1 1 2 Harmonic Rejection LPF

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144Figure 5-38 shows one of the simulation resu lts. In the figure, the graph shows the switching moment between two frequencies. The c ontrol signal is change d at time equals to 50 ns. Before 50 ns, the running frequency is at 4. 488 GHz, and after 50 ns, the signal is running at 7.656 GHz. It can be seen that the transition time is extremely short. It only takes about 3 ns for the frequency synthesizer to switch from one band to the other. Figure 5-38. Simulation results showing the transition time switching from one band to the other. From the time domain signals, it can be seen that spurious signals exist to corrupt the waveform of the output signals. It is important to see what the spectral com ponents of these signals are. Figure 5-39(a) and (b) shows the spectrum of th e signal before and after the frequency transition of the frequency synthesize r. As shown in the spectrum, some of strong spurious tones exist. These are mainly due to the non-ideal mixers a nd the harmonics of the square waves. However, due to the filters ad ded in front of the 264 MHz and 792 MHz signals, the spurious tones are far away from the wanted si gnal. All of the signals are at least 1 GHz away from the desired frequency. These spurious tones could be easily removed using filters in the 200 100 0 -100 200 49 52 55 58 Time ( ns ) Out p ut

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145receiver chain or the transmitter chain. Therefor e, these spurious tones should not cause too many problems. 5.6 Conclusions At the beginning of the chapter, a swit ching band VCO was de signed and measured. Although the VCO achieves wide tuning range, it can not be used in an UWB frequency synthesizer because of the lack in the frequenc y covering range from 3 to 10 GHz. Therefore, a low spurious MB-OFDM UWB frequency synthesi zer is proposed. This frequency synthesizer has capability of generating 12 out of the 14 bands that are described in the UWB standard. It utilizes techniques such as sub-harmonic mixers, harmonic re duction circuits, and polyphase filters, to purify the output signal. The chip is designed using UMC CMOS 90 nm technology. However, at the time of defense, th is chip is not completed. This ch ip has to be done in the future by other members in the RFSOC group. Figure 5-39. Simulation results showing (a) the sp ectrum of the signal before the transition, and (b) the spectrum of the signal after the transition. Frequency 1 @ 4.488GHz Frequency 2 @ 7.656GHz 0 -20 -30 Frequency (GHz) Relative Am p ( dB ) 3.33 6.67 10 0 -10 -40 Frequency (GHz) 3.33 6.67 10 0 -50 -20 -30 0 -40 -10Relative Am p ( dB ) (a) (b)

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146CHAPTER 6 SUMMARY AND FUTURE WORKS 6.1 Summary Wideband wireless communication system (e.g. Ultra-Wideband system) is becoming popular for its capability to achieve high data ra te wireless transmissi on. With the progress on CMOS technology in recent years, it could achieve comparable performances at high frequencies to other compound materials (e.g GaAs) but with much lower cost. Therefore, implementing wideband circuits using CMOS t echnology has become one of the mo st important topics in the RF circuit design. In this study, several wideband CMOS circuits along in the receiver chain were designed and tested using various novel technologies. Wideband LNAs u tilizing a modified resistive feedback topology were demonstrat ed. All of the LNAs were measured with package and ESD protection diodes using digital 90 nm CMOS t echnology. These LNAs could be used in UWB devices or multiband receivers. Three wideba nd LNAs are designed and tested. Different requirement in the bandwidth of the LNA results in different gain. The trade-off between the gain-bandwidth is also examined. LNA1 has a ba ndwidth of 9 GHz and a voltage gain of 17 dB. The noise figure is within 4 dB to 6 dB from 1 GHz to 7 GHz. LNA 2 achieves a bandwidth of 3.2 GHz with 22 dB of voltage gain. The noise fi gure of the LNA is ranging from 1.8 dB to 3 dB from 1 GHz to 3 GHz. LNA3 uses an active inducto r load to achieve a small chip area. The LNA has a bandwidth of 8 GHz with a voltage gain of 16 dB. Noise figure is ranging from 3 dB to 5.5 dB from 1 GHz to 8 GHz. Next, two CMOS passive mixers were design ed and tested. One of the passive mixers achieves very wide bandwidth for UWB devices. The passive mixer has conversion loss of 6.5 dB from 1 GHz to 10 GHz. For linearity, input P 1dB is about 5 dB and IIP3 is about 11 dBm.

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147Also, in order to implement the passive mixer in a direct conversion receiver, problem of LO feed-through could be solved by using a harmonic passive mixer. It is also implemented using 0.18 m CMOS technology. For this mixer, the m easured voltage conversi on loss is about 6 dB. Also, the signal source and the IQ generation circuitry were designed on chip to reduce the components counts externally. Other than the CMOS technology, GaN devices are also in th e interests for researchers. The special property of the GaN device is that it can handle large power for its high break down voltage. Models of the GaN devi ces in linear region were created Behavior of conversion loss with LO power is well predic ted using the developed model. Three down-conversion mixers were designed for RF frequency of 1.7 GHz a nd IF frequency of 200 MHz using LO frequency of 1.9 GHz. GaN HEMT devices w ith gate width of 300 um, and gate lengths of 1.2, 1.0, and 0.75 um were used in the mixers. Finally, the voltage controlled oscillator s (VCOs) and frequency synthesizers were considered and designed. A switching band VCO achieving 20% of tuning range for 3 GHz and 5 GHz was demonstrated. Switching inductors and cap acitors were used to change the oscillating frequencies. Next, a frequency synthesizer used for MB-OFDM UWB system was designed. The synthesizer generates 12 bands ranging from 3 GHz to 10 GHz using subharmonic mixing technique. Various spurious reduc tion methods were implemented to reduce the interferences caused by the spurious signals. 6.2 Future Works The UWB frequency synthesizer is not finished at the point of graduation. Due to its complexity, it needs couple of more tape outs to make it realized in CMOS technology. This task will be followed by other members from RFSOC lab. The techniques that are used in the frequency synthesizer can also be used in other applications such as a system to remotely detect

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148of the heartbeats and respirations [59]. With the structure proposed in this dissertation, the making of a frequency hopping frequency synthesizer can be easier. After demonstrations of the concepts on each block in a wideband receiver, a system level design has to be considerate t horoughly. These blocks, like mi xers, VCOs, LNAs, and frequency synthesizers, could be used in the desi gn of wideband systems including MB-OFDM UWB system or wideband software configurable ra dio front end. However, the whole system integration will be a design into another level that whole team of engineers have to work on, and it will not be in the scope of this PhD study.

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149REFERENCES [1] S. Wood, UWB Standards, WiMedia Alliance White Paper, http://www.wimedia.org. [2] First report and order, revision of part 15 of th e commissions rules regarding ultra-wideband transmission systems, Federal Communications Commission (FCC), ET Docket 98, Feb. 14, 2002. [3] G. R. Aiello and G. D. Rogerson, Ultra-wideband wireless systems, IEEE Microwave Magazine, Jun. 2003. [4] D. Porcino and W. Hirt, Ultra-wideband radio technology: potenti al and challenges ahead, IEEE Communications Magazine, Jul. 2003. [5] High Ra te Ultra Wideband PHY and MAC Standard, ECMA International, Dec. 2005 (http://www.ecma-international.org/ publications/files/ ECMA-ST/ECMA368.pdf). [6] A. Batra, J. Balakrishnan, R. Aiello, J. R. Foerster, and A. Dabak, Design of a multiband OFDM system for realistic UWB channel environments, IEEE Trans. Microwave Theory Tech., vol. 52, NO. 9, pp. 2123-2138, Sep. 2004. [7] S. Roy, J. R. Foerster, V. S. Somay azulu, and D. G. Leeper, Ultrawideband radio design: the promise of high-speed, sh ort range wireless connectivity, Proceedings of the IEEE., vol. 92, NO. 2, pp. 295-311, Feb. 2004. [8] L. Yang and G. B. Giannakis, Ultra -wideband communications: an idea whose time has come, IEEE Signal Processing Magazine, vol. 21, Issue 6, pp. 26-54, Nov. 2004. [9] G. Cusmai, M. Brandolini, P. Rossi, a nd F. Svelto, A 0.18-um CMOS selective receiver front-end for UWB applications, IEEE Journal of Solid-State Circuits, vol. 41, NO. 8, pp. 17641771, Aug. 2006. [10] P. Andreani and S. Mattisson, On the use of MOS varactors in RF VCOs, IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, Jun. 2000. [11] A. Bevilacqua and A. Niknejad, An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers, IEEE Journal of Solid-State Circuits, vol. 39, no.12, pp. 2259-2268, Dec. 2004. [12] Ismail, A.; Abidi, A.A., A 3-10-GHz low-noise amplifier with wideband LCladder matching network, IEEE Journal of Solid-State Circuits, vol. 39, no.12,pp. 22692277, Dec. 2004 [13] F. Zhang and P.Kinget, Low-power programmable gain CMOS distributed LNA, IEEE Journal of Solid-State Circuits, vol. 41, no.6, pp. 1333-1343, Jun. 2006.

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154BIOGRAPHICAL SKETCH Tienyu Chang received the B.S. degree in electrophysics from National Chiao Tung University, Hsingchu, Taiwan, R.O.C., in 2000, and the M.S. degree in electrical engineering from National Taiwan University, Taipei, Taiw an, R.O.C., in 2002. He is currently working toward the Ph.D. degree in electr ical engineering at the Univer sity of Florida, Gainesville, Florida, USA. His research interests are in the areas of radio-frequency/millimeter-wave integrated circuits and analog circuits.


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