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Optimization Stability of Gate Dielectrics on Gallium Nitride

Permanent Link: http://ufdc.ufl.edu/UFE0021288/00001

Material Information

Title: Optimization Stability of Gate Dielectrics on Gallium Nitride
Physical Description: 1 online resource (198 p.)
Language: english
Creator: Hlad, Mark Steven
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2007

Subjects

Subjects / Keywords: breakdown, dielectrics, gan, oxides, passivation
Materials Science and Engineering -- Dissertations, Academic -- UF
Genre: Materials Science and Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The application of gallium nitride (GaN)-based devices requires the use of a gate dielectric to reduce gate leakage, passivate surface traps, and provide isolation between devices. It is critical for the insulator to remain chemically and thermally stable at high temperatures (i.e. 1000 degrees C) during device fabrication and operation. More importantly, it must possess good electrical characteristics such as a high breakdown field, low flatband voltage shift, and low interface trapped charge (Dit). A new dielectric material, known as scandium gallium oxide ((Sc2O3)x(Ga2O3)1-x), was investigated. Growth conditions of MgxScyOz and MgO were also optimized to enhance their environmental stability and improve their electrical results. All dielectric films were deposited by molecular beam epitaxy (MBE), which uses independent sources to precisely control the film thickness and stoichiometry. Initial films on GaN were characterized by using a wide variety of techniques to determine the crystal structure, surface roughness, chemical composition, and film thickness. Electrical diodes were then fabricated for electrical testing such as current-voltage and capacitance-voltage measurements. Continuous and digital growth techniques for (Sc2O3)x(Ga2O3)1-x revealed segregation of Ga at the surface. The segregation was eliminated by utilizing a growth technique in which the Ga shutter was closed for a set amount of time towards the end of the growth while the O and Sc shutters remained open. A poor breakdown field of 0.15 MV/cm was obtained due to the presence of free Ga metal in the film. Growth of MgxScyOz at low oxygen pressures showed breakdown fields as high as 4 MV/cm and Dit values in the low 10^11 ev^-1cm^-2 range, but flatband voltage shift values ranging from 3.83-5.30 V were also obtained. The large flatband voltage shifts were attributed to defects generated from the mixed Sc (+3) and Mg (+2) valences. Optimization of MgO growth parameters at low oxygen pressures and low growth rates showed improved environmental stability and good electrical results on both u-GaN and p-GaN. The use of a new processing scheme in which the ohmic metal is deposited prior to MgO showed good feasibility as it displayed comparable electrical results to the old scheme involving MgO deposition prior to ohmic metallization.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Mark Steven Hlad.
Thesis: Thesis (Ph.D.)--University of Florida, 2007.
Local: Adviser: Abernathy, Cammy R.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2007
System ID: UFE0021288:00001

Permanent Link: http://ufdc.ufl.edu/UFE0021288/00001

Material Information

Title: Optimization Stability of Gate Dielectrics on Gallium Nitride
Physical Description: 1 online resource (198 p.)
Language: english
Creator: Hlad, Mark Steven
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2007

Subjects

Subjects / Keywords: breakdown, dielectrics, gan, oxides, passivation
Materials Science and Engineering -- Dissertations, Academic -- UF
Genre: Materials Science and Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The application of gallium nitride (GaN)-based devices requires the use of a gate dielectric to reduce gate leakage, passivate surface traps, and provide isolation between devices. It is critical for the insulator to remain chemically and thermally stable at high temperatures (i.e. 1000 degrees C) during device fabrication and operation. More importantly, it must possess good electrical characteristics such as a high breakdown field, low flatband voltage shift, and low interface trapped charge (Dit). A new dielectric material, known as scandium gallium oxide ((Sc2O3)x(Ga2O3)1-x), was investigated. Growth conditions of MgxScyOz and MgO were also optimized to enhance their environmental stability and improve their electrical results. All dielectric films were deposited by molecular beam epitaxy (MBE), which uses independent sources to precisely control the film thickness and stoichiometry. Initial films on GaN were characterized by using a wide variety of techniques to determine the crystal structure, surface roughness, chemical composition, and film thickness. Electrical diodes were then fabricated for electrical testing such as current-voltage and capacitance-voltage measurements. Continuous and digital growth techniques for (Sc2O3)x(Ga2O3)1-x revealed segregation of Ga at the surface. The segregation was eliminated by utilizing a growth technique in which the Ga shutter was closed for a set amount of time towards the end of the growth while the O and Sc shutters remained open. A poor breakdown field of 0.15 MV/cm was obtained due to the presence of free Ga metal in the film. Growth of MgxScyOz at low oxygen pressures showed breakdown fields as high as 4 MV/cm and Dit values in the low 10^11 ev^-1cm^-2 range, but flatband voltage shift values ranging from 3.83-5.30 V were also obtained. The large flatband voltage shifts were attributed to defects generated from the mixed Sc (+3) and Mg (+2) valences. Optimization of MgO growth parameters at low oxygen pressures and low growth rates showed improved environmental stability and good electrical results on both u-GaN and p-GaN. The use of a new processing scheme in which the ohmic metal is deposited prior to MgO showed good feasibility as it displayed comparable electrical results to the old scheme involving MgO deposition prior to ohmic metallization.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Mark Steven Hlad.
Thesis: Thesis (Ph.D.)--University of Florida, 2007.
Local: Adviser: Abernathy, Cammy R.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2007
System ID: UFE0021288:00001


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445415d53261c4dbf3b3940600ad40f91a6a922e







OPTIMIZATION STABILITY OF GATE DIELECTRICS ON GALLIUM NITRIDE


By

MARK STEVEN HLAD

















A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2007

































2007 Mark Steven Hlad

































To my family and friends









ACKNOWLEDGMENTS

I want to praise God for giving me the opportunity to receive a Ph.D. and work with and

learn from such great professors and students. God's grace is truly sufficient for me as He has

provided me the strength when I am weak and the encouragement to press onward under any set

of circumstances. I would also like to thank Dr. Abernathy for welcoming me into her group and

helping me to broaden my knowledge of electronic materials (especially when it involved

thermodynamics and kinetics). I can't give enough thanks to Dr. Gila. He constantly challenged

me, and he took the time to explain crucial concepts and give instruction on how to use certain

tools (i.e. Rusty). More importantly, he provided a valuable friendship. The flag football

practices and games were a lot of fun, and he was always willing to talk about anything

(especially gator football). I want to give thanks to Dr. Lin, Dr. Norton, and Dr. Pearton for

making themselves available to answer my questions and for helping me to understand important

concepts. Thanks to Dr. Lambers for allowing me to use the AES and XPS instruments. He

provided enjoyable discussions and helped me with my thin film characterization. I want to

thank Andy Gerger for performing SEM and AFM characterization and some of the MBE

growths.

I also want to thank many of the friends that I have met during my time at the University of

Florida. My friends in Campus Crusade for Christ have given me constant encouragement and

have challenged me to grow in Christ. My community group on Tuesday nights has provided

both fellowship and accountability. I want to give thanks to my boys in the gym, Rob Humkey

and Alex Tamayo. They made the workouts tough and they were even better friends to hang

with at the football games and other events. Thanks should also go to Peter Zawaneh and

Michael Nash, who have been good friends to lean on when my research work was not working

and I was completely frustrated. The last friend that I would like to thank is Dr. Omar Bchir. He









is one of the brightest individuals I have ever met, and he inspired me to go to graduate school. I

was fortunate enough to work with him at Intel for 6 months, and I have learned a great deal

from him.

Finally, I would like to give thanks to all of my family members. Their constant prayers

were an encouragement and provided me the strength I needed to finish. My brother has been a

role model to me my whole life, and he has inspired me to work hard and grow in Christ. One of

his comments to a friend said it best as he commented "Mark does everything that I do, but he

does it better." I want to give a special thanks to my mom and dad. They have provided me so

much love and support. I am truly blessed as they have sacrificed time and individual gain so

that I could be successful.









TABLE OF CONTENTS

page

A CK N O W LED G M EN T S ................................................................. ........... ............. .....

L IS T O F T A B L E S ................................................................................. 9

LIST OF FIGURES .................................. .. .... ..... ................. 10

ABSTRAC T ............... ................................... ............... 15

CHAPTER

1 INTRODUCTION ............... ............................ .............................. 17

M motivation .......... ... ........................................................17
D issertation O outline .................................................................... .. ............ 18

2 BACKGROUND AND LITERATURE REVIEW ..................................... ...............20

Introduction to MOSFET Device ............................... ........... .......................... 20
Basic Operation of e-mode n-channel MOSFET ................................. ................ 21
Ideal and R eal M O S C apacitors ............................................... ............ ............... 22
Properties and Characteristics of Dielectric Materials ............................................23
Current Collapse and RF D ispersion........................................ ........................... 24
C rystalline D ielectrics on G aN .............................................................................. ........ 26
G adolinium O xide ................. ........ ............................ .. .......... .. .............27
Scandium O xide ................................................................... 28
M agnesium Oxide .................................. ................ .. ............30
M agnesium Calcium Oxide .............................................. ........ ......................... 32
G allium G adolinium O xide ..................................................................... ..................34
A m orphous D ielectrics on G aN ...................................................................... ..................35
S ilic o n N itrid e ........................................................................................................... 3 5
Silicon D dioxide ............................................................................................... ....... 36
G aN Su rface C lean in g .................................................................. ..................................3 7
U V -O 3 C leaning ................................................................... 38
In -situ C le a n in g ............................................................................................................... 3 8
E x -situ C le a n in g .....................................................................................................3 9

3 EXPER IM EN TA L A PPR O A CH ..................................................................................... 50

M molecular B eam E pitaxy ................................................................50
S u b state P rep aratio n ................................................................................................. 52
S ilic o n ................................................................................................................. 5 2
Gallium nitride ......................... ................ 53
Scandium Gallium Oxide Growth ................................. ...............................54
M agnesium Oxide Grow th ............................................ .. .. 54


6









M agnesium Scandium Oxide Growth ........................................ ......................... 55
S ta rt- U p .................................................................................................................... 5 5
M O S Capacitor Fabrication............................................................................... 56
P hotolithography ....................................................... 56
E thing ..... . ..........................................................57
M e ta lliz atio n .............................................................................................................. 5 9
A n n ealin g ................................................................6 0
Materials Characterization...................................... 61
Scanning Electron Microscopy (SEM) ................................................................61
Atom ic Force M icroscopy (AFM ) .................. ............................. ................. 62
Reflective High Energy Electron Diffraction (RHEED) ..............................................63
E llip so m etry ............................................................................................................. 6 4
Transmission Electron Microscopy (TEM) ........................................64
X-Ray Diffraction (XRD)............................................65
X-Ray Photoelectron Spectroscopy (XPS)................................... .. .........65
Auger Electron Spectroscopy (AES) ..................................................................... 67
Current-V oltage (I-V ) M easurem ents ....................................................... 67
Capacitance-Voltage (C-V) Measurements .........................................68

4 GROWTH AND CHARACTERIZATION OF SCANDIUM GALLIUM OXIDE ..............86

Continuous Growth of (Sc203)x(Ga203)1- ....................................................... 87
Digital Growth of (Sc203)(Ga203)1-x .................................................................. .....................88
Growth with Closure of Ga Shutter ............................... ......................... ..............89
Electrical Testing of (Sc203)(Ga203)1 ..................................................................... 90

5 OPTIMIZATION OF MAGNESIUM OXDE .......................... ...............115

MgO Growth at Low Growth Rates and Oxygen Pressures .......................... ............... 115
Results of M g ScyO ............................................................................ .................................116

6 METALLIZATION STUDY WITH MAGNESIUM OXIDE .................... 133

M etallization Study on u-G aN ............................................................. 135
E electrical R results on p-G aN ......................................................................... .....................138

7 SUMMARY AND FUTURE WORK ....................................................... ...................161

Summary of (Sc203)x(Ga203)1x on GaN ............... ............................................. 161
Summary of MgO Growth Optimization.................................... ...............162
Summary of Electrical Results for MgScyOz ............. ..................................163
Summary of Metallization Study for MgO.................................................................164
Summary of Electrical Results for MgO on p-GaN.......................................................165

APPENDIX

A PROCESSING INFORMATION AND DETAILS .............................................................. 167









Indium R em ov al ...............................................................167
Surface Preparation.......... ...... ......... ........ ........ ...........168
P h o to re sist..........................................................................................................1 6 9
S u rface C o atin g ................ ...................................................................... .. ... .. .... .... 16 9
Factors Affecting Resist Thickness................................ ....................170
Acceleration ........... .................. ............... ............... 171
Spin D effects and A rtifacts............. ..................................................... ............... 171
S o ft B ak e ..........................................................................17 3
Exposure .............. ...................... ...................................174
D ev elo p m en t ............................................................................................17 5
H a rd B a k e ...........................................................................................................1 7 6

B CV CURVES AND MEASUREMENTS ............. .......... ........... 182

C V C u rv e s ...................................................................................................................... 1 8 2
D it C alcu nation s ................................................................................ 183
V FB D term nation ............. ........................................................................ 186

L IST O F R E F E R E N C E S ...............................................................................................190

BIOGRAPHICAL SKETCH ......................................................................... ......... ................... 198

































8









LIST OF TABLES


Table page

2-1 Properties of previously used dielectrics ............ ................................... .................41

4-1 Auger peak-to-peak ratios for Ga:O, Sc:O, and Sc:Ga as function of the amount of
time that the Ga shutter was closed towards the end of the growth..............................92

4-2 Characteristic binding energies of possible phases present in (Sc203)x(Ga203)1-x............93

4-3 Breakdown voltage as a function of decreasing Ga cell temperature.............................94

5-1 Breakdown field values (at 1 mA/cm2) of tested diodes before and after various wet
processing treatm ents .................................................... ...... .. ........ .... 120

5-2 Electrical results for MgxScyOz films on GaN for increasing Sc cell temperatures ........121

6-1 Electrical results for MgO films on u-GaN with various surface pre-treatments ..........141

A-1 Change in resist thickness for a given parameter .............. .........................................177

A-2 Causes of spin-induced defects or artifacts.................................. ........................ 178









LIST OF FIGURES


Figure page


2-1 Cross-section illustration of a depletion mode n-MOSFET ..........................................42

2-2 Cross-section illustration of an enhancement mode n-channel MOSFET ........................43

2-3 E-m ode n-channel M O SFET ................................................. ............................... 44

2-4 N -channel M O SF E T ...................................................................... .... ......................... 4 5

2-5 Energy band diagram for ideal p-type MOS capacitor at VG = 0 ...................................46

2-6 Energy band diagrams for ideal n- and p-type MOS capacitors under an applied bias....47

2-7 Valence band and conduction band offsets with respect to GaN for previously
researched dielectrics............................................. ........... 48

2-8 Auger peak-to-peak ratios for C:Ga, C:O, and Ga:O on GaN with UV-O3 treatments
of 1, 3, 5, and 10 m inutes............. .... ........................................................ ........ ........... 49

3-1 Illustration of a typical K nudsen effusion cell............................................................... 70

3-2 Top view sketch of Riber 2300 MBE system used for oxide growth............................71

3-3 AFM images showing pits at surface of as-received Uniroyal GaN .............................72

3-4 AFM images showing MOCVD GaN grown by the Abernathy group ............................ 73

3-5 RHEED images of pre-treated GaN surface ....................................... ................74

3-6 RHEED photos of GaN surface showing a (1x3) pattern following an in-situ anneal
a t 7 0 0 0 C ............................................................................... 7 5

3-7 Illustration of M OS capacitors that were fabricated .............................. ................ ... 76

3-8 Diagram of pattern in the mask used to open windows for the ohmic pad....................77

3-9 Diagram of pattern in the mask used to deposit ohmic pad .............................................78

3-10 Diagram of pattern in the mask used to deposit metal gate ........................................79

3-11 Sketches of bi-layer photoresist stack........................................................................... 80

3-12 AES surface scans of as-received and etched (Sc203)x(Ga203)1-x films on GaN .............81









3-13 Dry etching of (Sc203)x(Ga203)1-x on GaN and Si along with a reference piece of
GaN in a CH4/H2/Ar chemistry ...................................................................... 82

3-14 Etch selectivity of (Sc203)x(Ga203)1-x over GaN for a CH4/H2/Ar etch chemistry ..........83

3-15 P possible R H E E D patterns ...................................................................... .....................84

3-16 An image of the penetration depth and interaction volume of an electron beam in a
material ....................................................... 85

4-1 RHEED image of (Sc203)x(Ga203)1-x on GaN during and after growth...........................95

4-2 TEM SAD pattern of (Sc203)x(Ga203)1-x on GaN ...........................................................96

4-3 HRTEM image of (Sc203)x(Ga203)1-x on GaN ............... ............................... 97

4-4 AFM images of (Sc203)x(Ga203)1-x on GaN for a continuous growth ............................. 98

4-5 AES analysis of continuous growth for (Sc203)x(Ga203)1-x on GaN............................. 99

4-6 Diagram of a digital growth technique in which the Sc and Ga shutters are alternated
for a given time sequence while the oxygen shutter is open continuously throughout
the entire grow th. .......................................... ........................... 100

4-7 AFM images of (Sc203)x(Ga203)1-x on GaN for a digital growth..............................101

4-8 AES analysis of digital growth for (Sc203)x(Ga203)1-x on GaN...................................102

4-9 Diagram of growth technique in which the Ga shutter is closed towards the end of
the growth for a designated amount of time while the Sc and O shutters are open
c o n tin u o u sly ...................................... .................................................. 1 0 3

4-10 Change in Auger peak-to-peak ratios as a function of the amount of time that the Ga
shutter is closed towards the end of growth...........................................................104

4-11 AES analysis of growth with Ga shutter closure for (Sc203)x(Ga203)1-x on GaN..........105

4-12 AES depth profile of growth with Ga shutter closure for (Sc203)x(Ga203)1-x on Si.......106

4-13 Low magnification cross-section TEM image of (Sc203)x(Ga203)1-x on GaN with a
thin Sc203 layer at the GaN/oxide interface ........................................ ............... 107

4-14 High magnification cross-section TEM image of (Sc203)x(Ga203)1-x on GaN with a
thin Sc203 layer at the GaN/oxide interface ........................................ ............... 108

4-15 AFM images of (Sc203)x(Ga203)1-x on GaN for a growth with the Ga shutter closed
tow ard s th e en d ........................................................................ 10 9

4-16 Current-voltage (I-V) plot of (Sc203)x(Ga203)1-x film deposited at 1000C ..................110









4-17 Ga LMM level shows a 6 eV difference between the Ga203 and Ga metal peaks.........111

4-18 Ga 2p3/2 level shows a 2 eV difference between the Ga203 and Ga metal peaks .........112

4-19 Ga 3d level shows a 2 eV difference between the Ga203 and Ga metal peaks.............113

4-20 Sc 2p3/2 level only shows the presence of a Sc203 phase............................................... 114

5-1 Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 1 minute DI
w after treatm en t ...................................... ................................................ 12 2

5-2 Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 3 minute
treatm ent in developer .................. ......................................... .. ......... 123

5-3 Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 10 minute
treatm ent in PG rem over ........................................................... .. ............... 124

5-4 Current-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 10900C. ... 125

5-5 Capacitance-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of
1090 C ......................................................... ................................. 126

5-6 Capacitance-voltage plot of two different scanning ranges for a MgxScyOz film on u-
GaN at a Sc cell temperature of 1090 C............................................................ ........ 127

5-7 Current-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 11350C. ... 128

5-8 Capacitance-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of
113 5 C ......................................................... ................................. 12 9

5-9 Current-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 11800C ....130

5-10 Capacitance-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of
11800C ............ ............... .......... .............................. ..... ...... .................... 131

5-11 Normalized capacitance-voltage (C-V) plots of MgxScyOz films on GaN at Sc cell
temperatures of 10900C, 11350C, and 11800C...................................................... 132

6-1 Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-03 surface pre-
tre atm e n t ............................................................................. 14 2

6-2 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 surface
pre-treatm ent ..................................... .................................. .......... 143

6-3 Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-03 and 10 min
N H 4 H surface pre-treatm ent......... ..................................... ................. ............... 144









6-4 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 and 10
m in N H 40H surface pre-treatm ent ....................................................... ............. 145

6-5 Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-03 and 1 min BOE
surface pre-treatment ................................. .. .. .......... ..............146

6-6 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 and 1 min
B O E surface pre-treatm ent ...................................................................... ..................147

6-7 Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-03 and 10 min in-
situ N2 plasma anneal at 7000C surface pre-treatment ......................................... 148

6-8 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 and 10
min in-situ N2 plasma anneal at 7000C surface pre-treatment.......................................149

6-9 Current-voltage (I-V) plot for MgO on u-GaN with four different surface pre-
tre atm e n ts ...................................... .................................................... 1 5 0

6-10 Capacitance-voltage (C-V) plot for MgO on u-GaN with four different surface pre-
treatm ents .............................................................................................. 15 1

6-11 Current-voltage (I-V) measurements for different ohmic metals on p-GaN ................152

6-12 Current-voltage (I-V) plot for MgO on p-GaN with a standard surface pre-treatment
(3 min HCl:H20 (1:1), 25 min UV-O3, and 5 min BOE) .............................................153

6-13 Capacitance-voltage (C-V) plot for MgO on p-GaN with a standard surface pre-
treatment (3 min HCl:H20 (1:1), 25 min UV-O3, and 5 min BOE) ..............................154

6-14 Current-voltage (I-V) plot for MgO on p-GaN with a 25 min UV-O3 and 1 min BOE
surface pre-treatment ................................. .. .. .......... ..............155

6-15 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 and 1 min
B O E surface pre-treatm ent ...................................................................... ..................156

6-16 Current-voltage (I-V) plot for MgO on p-GaN with a 25 min UV-03 surface pre-
tre atm e n t ............................................................................. 1 5 7

6-17 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 surface
pre-treatm ent ............... .......... ................... ............. .......... 158

6-18 Current-voltage (I-V) plot for MgO on p-GaN with three different surface pre-
treatm ents .............................................................................................. 159

6-19 Capacitance-voltage (C-V) plot for MgO on p-GaN with three different surface pre-
tre atm e n ts ...................................... .................................................... 1 6 0

A-1 Diagram s of w getting vs. contact angle................................................ ........ ....... 179









A-2 Resist thickness vs. spin speed for Shipley 1818 PR............................ .....................180

A-5 Sidewall profiles of photoresist features................................ ................................. 181

B-l MOS capacitance-voltage curves for a p-type semiconductor ......................................187

B-2 High frequency CV measurement for an ideal MOS capacitor.................................. 188

B-3 Illustration of ideal and real CV plots... ........................ ..... ............... 189









Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

OPTIMIZATION STABILITY OF GATE DIELECTRICS ON GALLIUM NITRIDE

By

Mark Steven Hlad

August 2007

Chair: Cammy Abernathy
Major: Materials Science and Engineering

The application of gallium nitride (GaN)-based devices requires the use of a gate dielectric

to reduce gate leakage, passivate surface traps, and provide isolation between devices. It is

critical for the insulator to remain chemically and thermally stable at high temperatures (i.e.,

10000C) during device fabrication and operation. More importantly, it must possess good

electrical characteristics such as a high breakdown field, low flatband voltage shift, and low

interface trapped charge (Dit). A new dielectric material, known as scandium gallium oxide

((Sc203)x(Ga203)-x), was investigated. Growth conditions of MgxScyOz and MgO were also

optimized to enhance their environmental stability and improve their electrical results.

All dielectric films were deposited by molecular beam epitaxy (MBE), which uses

independent sources to precisely control the film thickness and stoichiometry. Initial films on

GaN were characterized by using a wide variety of techniques to determine the crystal structure,

surface roughness, chemical composition, and film thickness. Electrical diodes were then

fabricated for electrical testing such as current-voltage and capacitance-voltage measurements.

Continuous and digital growth techniques for (Sc203)x(Ga203)1-x revealed segregation of

Ga at the surface. The segregation was eliminated by utilizing a growth technique in which the

Ga shutter was closed for a set amount of time towards the end of the growth while the O and Sc









shutters remained open. A poor breakdown field of 0.15 MV/cm was obtained due to the

presence of free Ga metal in the film.

Growth of MgxScyOz at low oxygen pressures showed breakdown fields as high as 4

MV/cm and Dit values in the low 1011 ev-cm-2 range, but flatband voltage shift values ranging

from 3.83-5.30 V were also obtained. The large flatband voltage shifts were attributed to defects

generated from the mixed Sc (+3) and Mg (+2) valences.

Optimization of MgO growth parameters at low oxygen pressures and low growth rates

showed improved environmental stability and good electrical results on both u-GaN and p-GaN.

The use of a new processing scheme in which the ohmic metal is deposited prior to MgO showed

good feasibility as it displayed comparable electrical results to the old scheme involving MgO

deposition prior to ohmic metallization.









CHAPTER 1
INTRODUCTION

Motivation

The modern microelectronics industry is primarily based on silicon technology. As the

demands for increased device speed rise, the semiconductor industry continues to decrease the

size of transistors on integrated circuits (ICs) and increase the number of transistors per chip to

meet Moore's law (number of transistors on ICs doubles every 18 months). Although great

success has been achieved with silicon based devices, silicon does have a couple limitations.

Due to the low band gap (1.1 eV) of silicon, it cannot be used in devices operating under

high temperature and/or high power regimes. It is also an indirect band gap semiconductor,

which makes it an inefficient light emitter. Because of these limitations with silicon, much

research has been devoted to compound semiconductors to find materials that have direct band

gaps for efficient light emission and wide band gaps for high power, high temperature

applications. Gallium nitride is a compound semiconductor that has both of these characteristics.

The wide band gap (3.4 eV) of GaN allows it to be used in high power RF devices such as

military radar and broadband communication links. Its direct band gap allows it to be used in

photonic devices such as light emitting diodes (LEDs), laser diodes, and UV detectors. It also

has a low sensitivity to ionizing radiation, which makes it suitable for satellite based

communication networks.

With all of the potential that GaN has, there is a need for a dielectric in certain GaN-based

devices. AlGaN/GaN high electron mobility transistors (HEMTs) typically experience current

collapse and rf dispersion (discussed in Chapter 2), which is a decrease in the maximum current

and an increase in the knee voltage due to surface and bulk traps. The application of a dielectric

serves to passivate the surface traps, allowing a significant increase in the max current under rf









conditions in which the gate bias is pulsed. A second desire for using a dielectric is to reduce

leakage current from one device to another by isolating devices and interconnects (Mesa

isolation). The dielectric can also be employed underneath the gate to reduce gate leakage into

the semiconductor. This allows the fabrication of a metal oxide (or insulator) semiconductor

field effect transistor (MOSFET) which can be made into a complementary device that is

required for logic circuits.

Dissertation Outline

The objective of the study was to grow a novel gate dielectric with a high breakdown

voltage so that it could be employed in a stacked gate dielectric in an enhancement mode

MOSFET. The study also included optimization of some previously used crystalline dielectrics

to enhance the stability and electrical characteristics of the films.

The background and literature review is discussed in Chapter 2. It contains general

information on MOSFETs, characteristics of a good dielectric, properties of previously used

dielectrics, and a brief overview of rf dispersion and the current collapse effect. A thorough

literature review is provided on previously used dielectrics on GaN and various cleaning

techniques that have been used on GaN. Chapter 3 discusses the experimental parameters that

were used in growing the oxides as well as characterization methods that were used to analyze

the deposited thin films. All the major processing steps for the fabrication of MOS capacitors

were also provided. Growth and characterization details of (Sc203)x(Ga203)1-x are discussed in

Chapter 4. Information on different growth techniques and structural and chemical

characterization are given. Chapter 4 also includes current-voltage (I-V) results for

(Sc203)x(Ga203)1-x and the use of various growth conditions to find the optimal conditions that

give the best electrical results. Growth optimization of MgO and addition of Sc to MgO to form

MgxScyOz are discussed in Chapter 5. The study includes electrical characterization of new









growth conditions for MgO, and the feasibility of adding Sc to MgO to form a more stable oxide

film. A metallization study on u-GaN and electrical results for MgO on p-GaN are provided in

Chapter 6. The metallization study includes electrical results for various surface treatments on

samples with ohmic pads deposited on GaN prior to oxide deposition. Chapter 7 includes final

conclusions and recommendations for future experiments.









CHAPTER 2
BACKGROUND AND LITERATURE REVIEW

Introduction to MOSFET Device

The basic circuit functions performed by the metal oxide semiconductor field effect

transistor (MOSFET) are current amplification and controlled switching of the device off and on.

Its utilization of an insulating layer (i.e. oxide) between the metal gate electrode and

semiconductor layer provides isolation of devices and interconnects, insulation of the gate to

reduce gate leakage, and passivation of surface states that induce rf dispersion. The MOSFET

device is tolerant of high temperatures and provides better linearity (broader transconductance

vs. gate voltage) compared to a metal semiconductor field effect transistor (MESFET).

The MOSFET is a three terminal device which uses a metal gate to control a conducting

channel that electrons or holes (depending on the type of conducting channel) flow through from

a metal source to a metal drain. The two types of MOSFET devices are depletion mode

("normally on") and enhancement mode ("normally off'). In the depletion mode MOSFET

(Figure 2-1), the semiconductor material beneath the oxide is doped with the same type of

material as the source and drain regions.1 A conducting channel is already present at a gate

voltage of zero, so a gate voltage must be applied to turn the device off. The depletion mode

MOSFET is most commonly used as a resistor. In the enhancement mode (e-mode) MOSFET

(Figure 2-2), the semiconductor material beneath the oxide is lightly doped to create a region of

opposite type to the material under the source and drain regions. A conducting channel is not

present at a gate voltage of zero, so a gate voltage must be applied to create a conducting channel

and turn the device on. The e-mode MOSFET is most commonly used as a switch. An e-mode

n-channel device will be used for further description regarding the basic operation of a

MOSFET.2









Basic Operation of e-mode n-channel MOSFET

An e-mode n-channel device has n+ source and drain regions that have been implanted or

diffused into a lightly doped p-type substrate. At a gate voltage of zero, there is no conducting n-

channel between the n+ regions, so no current can flow from the drain to the source. This can be

understood with the band diagram of the MOSFET (at equilibrium) in Figure 2-3a. At

equilibrium, the Fermi level is flat and a potential barrier is present that prevents the flow of

electrons from the source to the drain. As a positive bias is applied to the gate, the valence band

moves away from the Fermi level and a depletion region begins to form as holes underneath the

gate oxide are repelled. A corresponding negative charge (ionized acceptors) is induced in the p-

type channel, and the barrier for electrons between the source, channel, and drain is reduced.

Further reduction of the barrier will lead to the formation of a channel in which electrons flow

from the source to the drain. The minimum gate voltage required to induce this channel is

known as the threshold voltage (VT). Increasing the gate voltage beyond the threshold voltage

will induce more negative charges in the channel (making it more conducting) as minority carrier

electrons generated in the bulk will drift across the depletion layer to the surface layer (inversion

layer) of charge.

Applying a drain bias initially increases the drain current linearly (Figure 2-3b). However,

as more drain current flows in the channel, more ohmic voltage drop occurs along the channel,

and eventually a drain bias is reached that causes the conducting channel to pinch-off and the

drain current to saturate. Pinch-off will occur when the difference between the gate voltage and

drain bias is equal to the threshold voltage (Figure 2-4). Increasing the drain bias further will

move the pinch-off point farther into the channel and closer to the source end.

For GaN MOSFETs, the formation of a conducting channel is completely dependent upon

an external source of inversion charge since the minority carrier generation rate is very low for









GaN (the generation rate is too low at even higher temperatures of 3000C). The source of this

charge consists of n regions in the source and drain created by Si implantation and subsequent

activation annealing. The application of a gate bias is then used to draw electrons from the

source and drain under the gate region to form a conducting channel.

Ideal and Real MOS Capacitors

The ideal MOS capacitor (Figure 2-5) has a flatband condition where the energy difference

between the metal work function (Om) and semiconductor work function ((s) is zero at an

applied bias of zero. Under an applied bias, three distinct operation modes exist which are

known as accumulation, depletion, and inversion (Figure 2-6).3 In accumulation, majority

carriers accumulate at the surface of the semiconductor, forming a larger carrier concentration

than the doping concentration in the bulk of the semiconductor. For a p-type semiconductor, the

valence and conduction bands will bend up, and for an n-type semiconductor, the bands will

bend down. In both cases, the intrinsic Fermi level (Ei) is farther away from the Fermi level (EF)

of the semiconductor. In depletion, majority carriers are depleted near the semiconductor

surface. The bands will bend down in p-type material and will bend up in n-type material, with

the bands bending far enough for Ei to equal EF at the surface. Under inversion, the bands bend

down strongly enough in the p-type material so that Ei lies below EF at the surface, and the bands

bend up strongly enough in the n-type material so that Ei lies above EF at the surface. Majority

carriers at the surface of the semiconductor have been further depleted and minority carriers are

collected at the surface.

For a real MOS capacitor, a work function difference typically exists between the metal

gate and semiconductor, along with various charges in the oxide and at the oxide/semiconductor

interface. The combination of these real effects induces a charge (positive or negative depending









on the various oxide charges and metal-semiconductor work function difference) at the surface

of the semiconductor and causes band bending to occur at equilibrium (Vg = 0). To eliminate the

band bending and achieve a flat band condition, a flatband voltage (VFB) in Equation 2-1 must be

applied to account for these real effects:


VF = (m -Q- (2-1)


where VFB is the flatband voltage (measured in volts), Oms is the work function difference

(measured in volts) between the work function of the metal (0m) and the work function of the

semiconductor (Os), Qi includes the various oxide and interface charges (measured in C/cm2),

and Ci is the capacitance of the insulator (measured in F/cm2).

Properties and Characteristics of Dielectric Materials

For a material to be an effective dielectric, it needs to possess the following characteristics:

chemical and thermal stability, a dielectric constant higher than the semiconductor, a wide band

gap with confinement at both edges, and a lattice constant and thermal expansion coefficient

close to that of the underlying substrate. Large differences in the lattice constants can create

defects such as misfit dislocations in the underlying substrate that can serve as trapping centers.

If the growth occurs at high temperatures, large differences in the thermal expansion coefficients

can produce stress at the interface during cooling that will relieve itself through the formation

and propagation of dislocations. High operating temperatures with wide band gap

semiconductor devices makes thermal stability an absolute necessity for the dielectric. In

addition to needing a larger band gap than the semiconductor, large valence band and conduction

band offsets with respect to the semiconductor are highly desirable. A higher dielectric constant

than the semiconductor is needed to prevent the formation of a high electric field in the dielectric

that can lead to potential breakdown of the dielectric. Characteristic values of previously used









dielectric materials on GaN are shown in Table 2.14-6 and band offsets with respect to GaN are

shown in Figure 2-7.

Effectiveness of the dielectric can also be determined through analysis of the charges at the

dielectric/semiconductor interface and in the dielectric itself. Positive or negative charges

trapped at the dielectric/semiconductor interface are known as interface trapped charge (or

interface state density). The trapped charge is due to structural defects (i.e. dislocations),

dangling bonds, and impurities. The interface state density (Dit) should have a value less than or

equal to 1011 eV cm-2 for a device to be successful. Charges trapped in the first 2-3 monolayers

of the dielectric due primarily to structural defects are known as fixed dielectric charge (Qf).

Positive or negative charges in the bulk of the dielectric due to trapped holes or electrons are

dielectric trapped charge (Qot). These charges can be injected into the dielectric from the gate or

semiconductor under large gate biases. Mobile dielectric charge (Qm) is attributed to ionic

impurities that can drift under an applied electric field. It is critical to minimize the amount of

charge in the insulator as trapped or mobile charges can cause shorting and effect the depletion

of a semiconductor.

The integrity of the oxide can be determined from current-voltage measurements by

calculating the breakdown field of the oxide. The breakdown field (in MV/cm) provides a

measure of how much gate voltage can be applied before the oxide breaks down and charges

flow freely from the gate to the semiconductor. It is extremely important to limit the number of

defects (such as dislocations and pinholes) and charges in the dielectric as they can serve as

electrical pathways that can lead to premature breakdown.

Current Collapse and RF Dispersion

Two phenomena that are known for limiting the electrical output (i.e. output power, drain

current, etc.) of MESFET and HEMT devices includes RF dispersion and current collapse.









Under RF dispersion, the output power and drain current at high frequencies are significantly

lower than projected due to trapping states at the surface. In contrast, current collapse is a

reduction in the drain current and distortion in the dc I-V characteristics that occurs a under a

large drain-source voltage due to traps in the bulk of the material.

Surface trapping has typically been identified through gate lag measurements where the

drain current is measured while the gate is pulsed from pinch-off to a value where turn-on

occurs.8'9 The surface traps are typically associated with dangling bonds, ions adsorbed from the

atmosphere, and dislocation defects. Under a large negative gate bias, electrons are injected

from the gate into surface states between the gate and drain electrodes, which creates a virtual

gate.10-12 The virtual gate depletes electrons from the conducting channel of a MESFET and the

2DEG of a HEMT, causing a reduction in the output current.13 Applying a positive bias to the

gate will not increase the drain current instantaneously because the change in the potential of the

virtual gate is slow. To reduce the effect of rf dispersion, a dielectric can be deposited at the

surface of the semiconductor to passivate the surface trapping states. Including the dielectric

underneath the gate metal to make a MOSFET or MOSHEMT device allows the dielectric to

simultaneously passivate surface traps and reduce gate leakage.

Buffer trapping has typically been identified through drain lag measurements where the

drain current is measured while the drain-source voltage is pulsed.8 Another indicator of buffer

trapping is when a shift in the threshold voltage is observed between dc and pulsed I-V

measurements.9 Traps in the buffer layer are typically associated with dislocation defects and

vacancies. Under a large drain-source bias, a high electric field builds up and accelerates

electrons through the conducting channel of a MESFET or MOSFET and the 2DEG channel of a

HEMT. At a high enough electric field, electrons have sufficient kinetic energy to overcome









local potential barriers and are injected (hot electron stress) into deep trapping centers in the GaN

buffer layer or AlGaN layer (for a HEMT device).7'14'15 The trapped electrons then lead to

current collapse by extending the depletion region and reducing the sheet charge in a HEMT or

the density of carriers in the MESFET or MOSFET conducting channel. The effect of current

collapse is an increase in the knee voltage and a decrease in the max drain current.

The primary way to significantly reduce or eliminate current collapse is to optimize the

growth conditions of the GaN buffer layer and AlGaN layer (in a HEMT device) so that both

layers are of high crystal quality with very few dislocation defects and vacancies. Illumination

with light and elevated temperatures have also shown success in reducing the current collapse

effect.7'16'17 Temperatures as high as 155C in GaN MESFETs completely eliminated the current

collapse effect as electrons were thermally emitted from deep level traps. Drain characteristics

measured at a gate bias of 0 V under a xenon lamp showed an increase in the drain current as the

wavelength of light decreased. The increase in drain current with decreasing wavelength (720 to

360 nm) indicated a wide distribution of trap levels instead of a single trap with a defined energy

level. Further analysis of the deep level traps in a GaN MESFET by photoionization

spectroscopy indicated that the traps were located at 1.8 and 2.85 eV below the conduction

band. 17

Crystalline Dielectrics on GaN

The following sections provide a summary on the most important crystalline dielectrics

that have been developed for use as gate oxides on GaN. The general trend shows that a lower

Dit value is obtained as the lattice mismatch is reduced between the crystalline dielectric and

GaN substrate. Oxide films grown at lower (i.e. 1000C) substrate temperatures have typically

shown a greater breakdown voltage compared to films grown at higher substrate temperatures









(i.e. 3000C or greater). All of the crystalline dielectrics discussed below were deposited by gas

source molecular beam epitaxy (GSMBE).

Gadolinium Oxide

Gadolinium oxide (Gd203) films have been deposited by MBE as a gate dielectric in GaN

MOSFETs.18-24 An elemental Gd source and ECR oxygen plasma source were used to deposit

70 nm thick films. Changes in the substrate temperature did not significantly change the

deposition rate and O/Gd ratio. A Dit value of 3x1011 cm-2eV-1 (obtained from Terman method)

and a breakdown field of 3 MV/cm were measured for a quasi-amorphous film grown at

1000C.18 However, the film showed poor thermal stability as it re-crystallized and produced a

second phase after being annealed to 10000C in N2 for 30 seconds.

A single crystal film deposited at 6500C showed good thermal stability upon annealing to

10000C in N2 for 30 seconds.19 The surface roughness of the annealed sample was 0.60 nm

compared to a value of 0.56 nm for the as-grown sample. AES depth profiling also showed an

abrupt oxide/nitride interface for the as-grown and annealed samples. A breakdown field of 0.3

MV/cm was measured for the fabricated GaN device structure. TEM showed a high

concentration of dislocations in the film that served as leakage paths and were responsible for the

low breakdown field. The highly defective single crystal layer was a result of nanometer size

voids in the GaN surface and the 20% lattice mismatch between Gd203 (111) and GaN

(0001).19,20

To reduce the gate leakage and improve the breakdown field of the device, amorphous

SiO2 was deposited on top of Gd203.21'22 The stacked gate dielectric of SiO2 (30 nm)/Gd203 (70

nm) maintained the interfacial properties of Gd203/GaN while using the SiO2 layer to reduce

current leakage by terminating the dislocations in the oxide layer. The breakdown field of the









device improved from 0.3 to 0.8 MV/cm, and modulation was demonstrated up to a gate bias of

7 V. The reverse leakage current was measured at -10 pA for a gate-source bias (VGS) of-10 V,

and it remained below 10 nA past VGS = -70 V. The main limitation of Gd203 is its large lattice

mismatch with GaN. The larger band gaps and smaller lattice mismatch to GaN make MgO and

Sc203 dielectric films more desirable to use than Gd203 films.

Scandium Oxide

Scandium oxide (Sc203) deposited by MBE is another dielectric that has recently been

used in GaN MOSFETs24-28 and AlGaN/GaN HEMT4,28-39 devices. An elemental Sc source and

RF oxygen plasma source have been used to deposit the films at substrate temperatures ranging

from 100-6000C.28 Changes in the substrate temperature, Sc cell temperature, or oxygen

pressure have shown no change in the Sc:O ratio. Breakdown fields as high as 3.3 MV/cm (80-

100 nm oxide film) and Dit values as low as 5x1011 eV-lcm2 (calculated by Terman method)

have been measured for GaN MOS capacitors.25'28 A significant flatband voltage shift has also

been observed, indicating the presence of fixed oxide charge. N+ drain regions were used in a

separate Sc203/p-GaN device to overcome the low minority carrier generation rate in GaN and

provide a source of inversion charge.26

An AlGaN/GaN MOSHEMT was compared to a metal-gate HEMT to observe the effect of

Sc203 as a gate dielectric. The drain current reached a maximum value over 0.8 A/mm for the

MOSHEMT and was -40% higher compared to the conventional HEMT.36 The device was also

modulated to a gate voltage of 6 V, and the threshold voltage shifted to more negative values

(from -4 V to -5.5 V). Pulsed conditions showed a 10% decrease in IDs relative to DC

conditions indicating that the Sc203 dielectric (10 nm) effectively minimized the current collapse

seen in unpassivated devices. Other Sc203 MOSHEMT devices have shown significantly better









power-added efficiency (27%) relative to a conventional HEMT (5%).30 Scandium oxide

passivated HEMTs have also shown effective suppression of surface states created by high

energy proton irradiation (40 MeV protons at a fluence equivalent to -10 years in low-earth

orbit), making them attractive candidates for space and terrestrial applications experiencing high

fluxes of ionizing radiation.31'37

Surface cleaning has played a vital role in obtaining improved electrical characteristics

with Sc203 passivation. A 25 min UV/03 treatment, followed by heating at 3000C for 5 min, and

then deposition of Sc203 (10 nm) at 1000C, provided a greater increase in fmax, fT, IDS, and gm

compared to depositing Sc203 at 1000C without any surface pre-treatment.33 The only poor

result from the pre-treatment was a slight increase in the reverse leakage current, which was

attributed partially to thermal degradation of the gate contact. A cleaning temperature of 700C

would be ideal prior to oxide deposition for cleaning the surface more thoroughly, but any pre-

cleaning temperatures above 3500C deteriorates the gate metal of the HEMT.34

A major advantage with Sc203 compared to MgO is that it provides stable passivation over

long periods of time. DC characteristics showed no change in GaN-cap HEMT performance

over a period greater than 5 months for devices passivated with Sc203 while MgO passivated

devices lost some of their effectiveness after 5 months.4'35 Comparison to a device passivated

with PECVD SiNx showed that Sc203 was more effective in restoring the drain current.

Scandium oxide produced complete recovery of the drain-source current, and SiNx provided only

-70-75% recovery.4 AlGaN/GaN HEMTs (0.5 x 100 [tm2) passivated with Sc203 led to a 3 dB

increase in output power at 4 GHz compared to a 1.8 dB increase for PECVD SiNx.35 The main

limitation with Sc203 is its 9% lattice mismatch with GaN. As stated previously, a larger lattice

mismatch produces a greater number of defects which can lead to a higher interface trap density.









Magnesium Oxide

Magnesium oxide (MgO) deposited by MBE has also been employed as a gate dielectric in

GaN MOSFETs28'40-48 and AlGaN/GaN HEMT4'28'33-39 devices. An elemental Mg source and RF

oxygen plasma source have been used to deposit the films at substrate temperatures of 100C.28

Cross-section TEM images show that the first 4 nm of the deposited film was single crystal, and

then it became polycrystalline as the film rotated. Changes in oxygen pressure have shown a

significant impact on the growth rate, Mg/O ratio, morphology, and electrical characteristics of

the MgO/GaN didoes.40 A Dit value of 3.4x1011 eV cm-2 (Terman method) and a breakdown

field of 4.4 MV/cm (90 nm oxide film) were obtained at an oxygen pressure of x10-5 Torr

compared to values of 1.8x1012 eV1 cm-2 and 1.2 MV/cm at a pressure of 7x105 Torr. The fixed

oxide charge was also shown to decrease with decreasing pressure. The low minority carrier

generation rate in GaN has made inversion at room temperature difficult in GaN MOS devices.

However, inversion was demonstrated in an MgO/p-GaN MOS diode at room temperature in the

dark when n+ regions were implanted in the device.41 The n+ regions served as the source of the

minority carriers needed for inversion at room temperature. Other MgO films were grown at

350C, but those films were extremely rough (rms of 4.07 nm compared to 1.26 nm for MgO

films at 1000C), had a low breakdown voltage, and were too leaky to obtain C-V results from.42

An AlGaN/GaN MOSHEMT was compared to a metal-gate HEMT to observe the effect of

MgO as a gate dielectric. The drain-source current for the MOSHEMT was -20% higher

compared to the conventional HEMT.29 The pulsed drain current matched the DC drain current

indicating that the MgO dielectric (10 nm) effectively eliminated the current collapse seen in

unpassivated devices. Magnesium oxide passivated HEMTs have also shown effective

suppression of surface states created by high energy proton irradiation (40 MeV protons at a









fluence equivalent to -10 years in low-earth orbit), making them attractive candidates for space

and terrestrial applications experiencing high fluxes of ionizing radiation.37

A comparison between MgO and SiNx passivation films on GaN-capped HEMTs revealed

that the MgO film was more effective in mitigating current collapse. The SiNx film produced

-70-75% recovery of the drain-source current while the MgO film produced complete recovery

of the current.4 Passivated AlGaN/GaN HEMTs (0.5x100 [tm2) with MgO led to a 3 dB increase

in output power at 4 GHz compared to a 1.8 dB increase for PECVD SiNx.35

The role of cleaning prior to deposition of MgO passivation on AlGaN/GaN HEMTs has

taken on great significance in optimizing the performance of the device.33'34 Deposition of MgO

without prior in-situ or ex-situ treatment showed an increase in IDS, gm, fT, and fMAx, and a

reduction in reverse leakage current compared to devices with no passivation or pre-treatment.33

A 25 min UV-03 treatment, followed by heating at 3000C for 5 min, and then cooling to 1000C

for deposition of MgO produced better dc and rf results than the deposited MgO films that did

not receive any pre-treatment. Similarly to Sc203, the surface treatment and passivation did

produce an increase in the gate leakage current.

A major limitation of MgO is its poor environmental stability.43 It has been shown to

deteriorate over time when left uncapped due to the reaction with water vapor in the ambient

forming MgOH.35 To preserve the stability of MgO, a capping layer, such as Sc203 (5-10 nm),

can be deposited on top of the MgO immediately following the MgO growth.34 Films grown at

lower growth rates (-1 nm/min) have also shown more stability as they have shown no

deterioration after being exposed to air over a period of months. The lower growth rate films

have not appeared to etch in water in contrast to higher growth rate films which generally etch in

water within 10 seconds.









An additional limitation of MgO is its poor thermal stability.43 Annealed (10000C for 2

minutes) MgO/GaN diodes have shown significant roughening at the MgO/GaN interface,

degradation of the oxide, and an order of magnitude increase in the Dit. This presents severe

processing issues as ohmic contacts typically require high annealing temperatures (i.e., 750C for

30 seconds with n-GaN). It appears that changes in the processing sequence or the use of a

Sc203 capping layer would be needed to prevent these deleterious effects.

Magnesium Calcium Oxide

The desire to decrease the lattice mismatch with GaN and improve the passivation effect of

the dielectric has led to the development of MgCaO.49-51 The films have been deposited by MBE

using Mg and Ca elemental sources and an RF oxygen plasma source. Both CaO and MgO have

the same rocksalt crystal structure with similar dielectric constants and bandgap energies.

However, the (111) plane of MgO has a -6.5% lattice mismatch to the GaN (0001) plane, and the

(111) plane of CaO has a 6.8% lattice mismatch to the GaN (0001) plane. Since Vegard's law

can be applied to systems with components that have the same crystal structure, a 50-50 mixture

of MgO and CaO should produce a lattice matched oxide to GaN. This is highly desirable as

previous results have shown a decreasing Dit value and greater passivation effect for crystalline

oxides with decreasing lattice mismatch to GaN. Initial growths at substrate temperatures of

1000C and 3000C with all three (Mg, Ca, and 0) shutters open simultaneously showed Ca and O

segregation at the surface.49 To prevent this segregation from occurring, a digital growth at

3000C was employed which involved repeatedly altering the Mg and Ca shutter sequences at 10

sec intervals during continuous exposure from the oxygen plasma. An Auger depth profile

showed a film of uniform composition, and XRD results showed no evidence of phase separation

into either binary phase. A shoulder on the right of the GaN (004) peak was observed in the









XRD spectra, indicating the MgCaO (222) plane. The convenient aspect of the digital growth is

that it allows the utilization of various shutter sequences so that the lattice constant of MgCaO

can be finely tuned to that of GaN. This concept has been seen in passivation studies

incorporating MgCaO as the dielectric.

Two MgCaO films with different compositions (Mgo.sCao.sO and Mgo.25Cao.750) were

compared to a MgO film regarding their effectiveness in passivating an AlGaN/GaN HEMT.50

Both of the MgCaO samples showed increases in the drain saturation current with a 4.5%

increase for Mgo.sCao.sO and a 1% increase for Mgo.25Cao.750. The MgO sample showed a 10%

decrease in the drain saturation current which was attributed to strain applied on the nitride

HEMT by the oxide. Successful use of MgCaO as a passivation layer has also been confirmed

with Hall measurements. An increase in sheet carrier density of 15% was seen for unprocessed

HEMT material that was passivated with MgCaO and used as a Hall effect sample. Thermal

testing was then applied to the samples to measure their stability by annealing them at 1000C in a

box furnace open to room ambient. No appreciable decrease in the sheet carrier density was

observed over the 25 day anneal.49

The main limitations of MgCaO are its poor environmental and thermal stability.50

Although uncapped MgCaO has shown less severe degradation after annealing than MgO, it still

requires a capping layer of Sc203 (5 nm). The use of the capping layer provided dramatic

improvement in the thermal stability of the oxide as XRR results revealed little change in the

interface roughness of the MgCaO/GaN interface after a 10000C anneal for 2 min. In

comparison to MgO films, MgCaO films have also been etched in water within 10 seconds.

Films with lower growth rates that are richer in Mg have provided better stability than Ca rich or

perfectly matched films, but further investigation must be done to grow a more stable film.









Gallium Gadolinium Oxide

Good electrical results with (Ga203)x(Gd203)1-x deposited on GaAs54-58 led to the study of

(Ga203)x(Gd203)1-x/GaN MOSFETs59 and MOS capacitor60'61 structures. The oxide layer was

deposited by electron-beam evaporation from a single crystal Ga5Gd3012 garnet source at

-5500C. Characterization with TEM revealed that 2-3 monolayers of Gd203 initially formed

with the remaining oxide film containing a fine-grained polycrystalline mixture of Ga203 and

Gd203. A breakdown field of 3 MV/cm was achieved for a MOS diode with an oxide thickness

of 19.5 nm and film roughness of 3 nm.60 A Dit value of less than 101 eV cm-2 was estimated

from C-V curves for a MOS diode with an oxide film -17 nm thick.61 No shifts in the flatband

voltage appeared with changes in frequency (ranged from 20 Hz to 1 MHz), and negligible

capacitance hysteresis loops were found for C-V measurements with biasing voltages sweeping

up and down.

An 8.5 nm thick layer that was annealed at 7000C showed leakage currents ranging from

10-5 tol0-9 A/cm2. The high leakage current was attributed to a rough GaN surface even though

the substrate was heated to 6500C prior to deposition to remove surface contaminants.61

Although the diode showed a high leakage current, XRR results revealed that the

(Ga203)x(Gd203)1-x/GaN interface and the integrity of the oxide remained stable for RTA

treatments up to 9500C. Thermal stability was also seen in a (Ga203)x(Gd203)1-x/GaN depletion

mode MOSFET as the I-V characteristics showed improvement upon heating to 4000C.59 The

improvement was attributed to a reduction in the parasitic resistances in the device. A gate

breakdown voltage >35 V was achieved for the d-mode MOSFET compared to 16 V for a Pt

Schottky gate on the same GaN epilayer. The lower breakdown voltage and significant gate

leakage current for the Pt Schottky gate diode demonstrated the need for the (Ga203)x(Gd203)1-x









gate dielectric. A limitation of (Ga203)x(Gd203)1-x is the control of the stoichiometry which is

heavily dependent on the substrate temperature and usage of the garnet source.5

Amorphous Dielectrics on GaN

The next two sections provide a summary on the amorphous dielectrics of Si02 and SiNx

on GaN and AlGaN/GaN HEMTs. The majority of research on these two dielectrics has been on

Si. Their ease of processing and good chemical stability has led to the attractiveness of utilizing

them in GaN-based devices.

Silicon Nitride

Plasma enhanced chemical vapor deposition (PECVD) has commonly been used to deposit

Si3N4 at 3000C.62-70 A Dit value of 6.5x1011 eV- cm-2 (calculated by the Terman method) and a

breakdown field of 1.5 MV/cm were reported for a Si3N4 (100 nm)/n-GaN insulator-

semiconductor.63 Electrical measurements also revealed a flatband voltage shift of 3.07 V.

Analysis of the insulating layer by XPS revealed that it was slightly silicon rich. A lower Dit

value of 5x1010 eV-cm-2 (calculated by the Terman method) was obtained for a Si3N4/GaN

structure that had an NH40H treatment (15 min) followed by an N2 plasma treatment (1 min)

before deposition of the insulating layer.64 The lower Dit value shows the importance of a clean

substrate surface prior to deposition. A similar structure with SiO2 as the gate dielectric received

the same pretreatment as the Si3N4/GaN structure and it had a higher Dit value of 3.0x1011 eV

1 -2
cm

Passivating AlGaN/GaN HEMTs with Si3N4 has proven more effective than using SiO2.

This was attributed to the high density of SiO2/GaN interface states which is reported to be 10

times higher than that for Si3N4.65 The effectiveness of passivation with Si02 and Si3N4 was

tested by comparing 10 nm layers deposited by PECVD on AlGaN/GaN HEMTs.67 The Si02

MOSHFET showed a greater reduction in dc current with an increase in the input rf drive, and









the Si3N4 MISHFET had an output power that exceeded the SiO2 MOSHFET by 3 dB for a large

input rf drive. Both results revealed the greater degree of current collapse in the SiO2

MOSHFET. Bernat et. al. also showed that Si3N4 has a greater impact on DC performance than

SiO2 for AlGaN/GaN HEMTs.65 Unpassivated devices had an IDs = 0.45 A/mm, passivation

with SiO2 gave 0.54 A/mm, and passivation with Si3N4 gave 0.68 A/mm. Hall effect

measurements showed a greater increase in sheet carrier density after passivation with Si3N4 than

with SiO2.

The use of Si3N4 to prevent gate leakage has shown good results. The leakage current for a

MISHFET only increased from 90 pA/mm at room temperature to 1000 pA/mm at 3000C,

remaining 3-4 orders of magnitude lower than an HFET with identical geometry.67 The dc

saturation current also remained fairly constant from 25 to 2500C. A limitation ofPECVD Si3N4

is the incorporation of hydrogen which can migrate into the gate metallization or into GaN.36

Another limitation is that it has a lower dielectric constant of 7.5 compared to 9.5 for GaN.

Silicon Dioxide

Different techniques such as radio-frequency sputtering e-beam evaporation63, and most

commonly PECVD63,72-76, have been used to deposit SiO2. E-beam evaporated SiO2 (100 nm

thick) yielded a Dit value of 5.3x101 eV- cm2 (calculated by the Terman method) and a

breakdown field of 1.8 MV/cm for an n-GaN MOS structure.63 Electrical measurements also

revealed a flatband voltage shift of 2.85 V. Analysis of XPS data revealed a peak with a binding

energy of 100.14 eV (Si20), indicating that a silicon-rich oxide layer was deposited. A lower Dit

value of 2.5x1011 eV-cm-2 and a higher breakdown field of 2.5 MV/cm were obtained using

PECVD for a 100 nm thick film.63 It also had a lower flatband voltage shift of 1.55 V. The XPS

data for the PECVD deposited film showed closer agreement to the reported SiO2 composition.









It was suggested that reduction in the interface state density was due to the composition of the

SiO2 layer.

The use of SiO2 in AlGaN/GaN MOSHFETs has produced extremely low gate leakage

currents.74-76 A MOSHFET leakage current of 100 pA was measured at room temperature under

a gate bias of-20 V for a 10 nm thick film grown by PECVD.74 This value was six orders of

magnitude smaller than an HFET with similar gate dimensions. Another MOSHFET structure

(15 nm thick oxide film grown by PECVD) showed a leakage current of 1 pA/mm at 300 OC,

which was approximately four orders of magnitude lower than an HFET with similar gate

dimensions.76 The MOSHFET also showed good thermal stability as the gate leakage remained

below 60 pA/mm at 200 OC for 36 h under bias (Vds = 20 V, Vgs = -2 V, Isd ~ 0.42 A/mm). After

being subjected to an extremely high thermal stress at 8500C for 1 min, the drain saturation

current only decreased by 20% and the leakage current increased up to 20 tA. Although SiO2

has shown good results, its biggest limitation is that its dielectric constant (; = 3.9) is

considerably lower than that of GaN (s = 9.5). This could cause a large electric field to build up

in the dielectric and cause it to breakdown.

GaN Surface Cleaning

A clean surface prior to oxide deposition is critical as surface defects and impurities can

influence the overall quality of the device (i.e., Dit) and the crystal quality of the deposited film.

Numerous wet chemical treatments and in-situ methods have been used to obtain clean GaN

surfaces prior to deposition. Some of the wet chemistry treatments have included the use of

NH40H64'66,77'79, F78-80, and HC178-s to reduce the amount of carbon and oxygen contamination

on the surface. In-situ methods have included a N2 plasma treatment64'66'79, a N2/H2 plasma

treatment79, a H plasma treatments, NH3 flux annealing80'83'84, Ga flux annealing80-83, and









deposition of Ga followed by annealing to evaporate the grown Ga monolayers81-83 from the

surface. Ultraviolet-ozone (UV-O3) cleaning33'79'80,85 is an ex-situ method that has been used to

reduce surface carbon contamination.

UV-03 Cleaning

UV-O3 has been shown to be very effective in removing both organic and inorganic

contamination with the exception of inorganic salts.85 The cleaning mechanism begins when the

contaminant molecules are excited and/or dissociated with the absorption of short wavelength

UV light (i.e., 254 nm). Atomic oxygen and ozone simultaneously form when 02 absorbs UV

light with a wavelength below 245 nm (ozone is primarily formed at 185 nm wavelength). Even

more atomic oxygen is formed at higher wavelengths (i.e., 254 nm) when ozone is dissociated by

the absorption of UV light. The excited contaminant molecules react with the atomic oxygen to

form volatile species such as CO2, H20, etc.85 Figure 2-8 shows the effectiveness of a 5 min

UV-O3 treatment at removing carbon contamination from the GaN surface following photoresist

removal with acetone.

In-situ Cleaning

In-situ plasma treatments have shown success in removing carbon and oxygen

contamination from the GaN surface. Cleaning with a hydrogen plasma showed effective

removal of carbon and halogen species at temperatures as low as 4000C, but it showed only

moderate success in removing oxygen.80 The use of an in-situ thermal treatment with an H2N2

plasma or an N2 plasma at 7500C for 5 min produced a clean GaN surface within the detection

limits of AES.79 However, SIMS data revealed the presence of significant amounts of carbon

(-3x1020 cm-3) and oxygen (-2x1022 cm-3) on the surface. These results show that all three









plasma treatments were effective at reducing the carbon and oxygen contamination, but further

cleaning studies must be examined to obtain completely clean GaN surfaces.

In-situ vacuum annealing has also been used to remove surface contaminants to less than

the AES detection limits. However, annealing at 8000C has shown incomplete removal of

oxygen and carbon from the surface as primarily C-H bonded carbon remains at temperatures

ranging from 600-9500C.80 X-ray photoelectron spectroscopy data indicated that complete

desorption does not occur until 950C. Annealing the surface up to 9500C is not an effective

process as GaN begins to sublimate at -8000C. Other in-situ vacuum anneals have been

performed in NH3 (excellent scavenger of hydrocarbons), following Ga deposition at room

temperature, and following Ga deposition at temperatures around 6000C.

Ex-situ Cleaning

Ex-situ wet treatments have been used to reduce surface contamination and become even

more effective when combined with an in-situ cleaning process. Treatment with a HCl:H20

(1:1) solution reduced the as-received O/N ratio from 0.39 to 0.21 and the as-received C/N ratio

from 0.28 to 0.24.78 Further in-situ annealing at 6500C for 15 minutes reduced both ratios to

0.14. Treatment with an HF:H20 (1:1) solution reduced the as-received O/N ratio from 0.39 to

0.26 and the as-received C/N ratio from 0.28 to 0.18.78 Further in-situ annealing at 6500C for 15

minutes reduced the O/N and C/N ratios to 0.17 and 0.13 respectively. Characterization with

AES and XPS has shown the abilities of a warm (50-600C) NH40H solution to significantly

reduce the amount of oxygen contamination at the surface.77 An in-situ N2 plasma treatment (1

min) following a 15 min NH40H treatment was shown to reduce the Ditto 5xl010 eV cm-2

(calculated by the Terman method) for a Si3N4/GaN structure.64 Since each of these ex-situ wet

treatments is effective at reducing the level of oxygen contamination at the surface, either of









these treatments could be used following a UV-03 treatment to strip the formed native oxide


layer.









Table 2-1. Properties of previously used dielectrics.
Material Structure Lattice constant (A) Band gap (eV) ; a (K-1) Tmp (K)
SiO2 Amorphous NA 9.0 3.9 0.5x10-6 1900
SiNx Amorphous NA 5.0 7.5 3.3x10-6 2173
(Ga203)x- Polycrystalline 4.7 14.2 2023
(Gd203)1-x
Ga203 Hexagonal a = 0.498, c = 1.343 4.4 10.0 2013
Gd203 Bixbyite 10.8130 5.3 11.4 1.0x10-5 2668
Sc203 Bixbyite 9.8450 6.3 14.0 2678
MgO Rock salt 4.2112 8.0 9.8 1.3x10-5 3073
*Value could not be found










VG=O


source


gate


drain


+n-GaN -I I- -




n-GaN


A


VG gate


source drain


+n-GaN "- --




n-GaN


B

Figure 2-1. Cross-section illustration of a depletion mode n-MOSFET. A) Device is in the
"ON" state with VG= 0. B) Device is in the "OFF" state with VG< 0. [Reprinted
with permission from B.P. Gila, 2000. Growth and Characterization of Dielectric
Materials for Wide Bandgap Semiconductors. PhD dissertation (pg. 21, Figure 2-2).
University of Florida, Gainesville, Florida.]















VG=O


VG>O


source


gate


gate


drain


Figure 2-2. Cross-section illustration of an enhancement mode n-channel MOSFET. A) Device
is in the "OFF" state with VG= 0. B) Device is in the "ON" state with VG> 0.


n --- nGa


p-GaN



























Source Channel Drain
U1 p Hi

Ec 400 -,/ -- Fc`',
@ 0 @.. 77777-7-7-7-. 1 H




A


i

IC
//
/, i



B


Figure 2-3. E-mode n-channel MOSFET. A) 3-D view of MOSFET and equilibrium band
diagram along channel. B) ID-VD curve for MOSFET as a function of gate voltage.
[Streetman, Ben; Banerjee, Sanjay, Solid State Electronic Devices, 5th Edition,
2000, pg. 256, Figure 6-10. Reprinted by permission of Pearson Education, Inc.,
Upper Saddle River, NJ]













M 4,
'S ^r ; .

. ~ ~ ~ ~ t *._ ... 91, "'. _-__ _


Depl-unn region
Depleuon region -'


t---.


LaH er channel)


" (


Pin ch-Tff


/


--- --- -- -


Pinch- l -f







...-!



L__._. ......p


I'1


Figure 2-4. N-channel MOSFET. A) Formation of conducting channel with VG > VT. B) Onset
of saturation with VG VD = VT. C) Strong saturation with VG VD < VT.
[Streetman, Ben; Banerjee, Sanjay, Solid State Electronic Devices, 5th Edition,
2000, pg. 258, Figure 6-11. Reprinted by permission of Pearson Education, Inc.,
Upper Saddle River, NJ]


_~ __~__















EC
g (I{.


-I- -- E




Metal Oxid Semiconductor

Figure 2-5. Energy band diagram for ideal p-type MOS capacitor at VG = 0. [Streetman, Ben;
Banerjee, Sanjay, Solid State Electronic Devices, 5th Edition, 2000, pg. 261, Figure
6-12. Reprinted by permission of Pearson Education, Inc., Upper Saddle River, NJ]












p-TYPE






--- Ec

EF
t E




E- EE

EF
+ + *+ Ev


V -I


/- Ei
E
4. -.-... EV


E----Ec
'---E1 [C)


Figure 2-6. Energy band diagrams for ideal n- and p-type MOS capacitors under an applied bias.
A) Accumulation. B) Depletion. C) Inversion. [Reprinted with permission from
B.P. Gila, 2000. Growth and Characterization of Dielectric Materials for Wide
Bandgap Semiconductors. PhD dissertation (pg. 130, Figure A1-3). University of
Florida, Gainesville, Florida.]


n-TYPE


V










E F


7-
V>o
Er4














I 111 Gd2O3
!GNSiO21 -M


C203MgO


GGG I


Figure 2-7. Valence band and conduction band offsets with respect to GaN for previously
researched dielectrics. GGG represents (Ga203)x(Gd203)1-x.












7.5
7.0
7-- C:Ga ratio
6.5
65 -*-- C:O ratio
6.0 -
O 60 Ga:O ratio
*- 5.5-
L 5.0
.L 4.5
4.0
0. 3.5
6 3.0
2.5
2.0
1.5
1.0
0.5
0.0 I ,
0 2 4 6 8 10

UV-O time (minutes)

Figure 2-8. Auger peak-to-peak ratios for C:Ga, C:O, and Ga:O on GaN with UV-03 treatments
of 1, 3, 5, and 10 minutes.









CHAPTER 3
EXPERIMENTAL APPROACH

Molecular Beam Epitaxy

Molecular beam epitaxy (MBE) was used to deposit the oxide films. It allows films with

abrupt interfaces and very smooth surfaces to be deposited in an ultra-high vacuum environment

using high purity sources. The high purity sources can be controlled independently from each

other by using ovens called Knudsen cells (Figure 3-1). The flux of atoms emitted from the cell

is represented by Equation 3-1:

F 1. 18x1022(P)(a) (3-1)
d 2 (MT)1/2

where F is the flux (in atoms/cm2) of the Knudsen cell, a is the orifice area (in cm2) of the cell, P

is the vapor pressure (in torr) inside the cell, T is the temperature (in degrees Kelvin) of the cell,

M is the atomic mass (in amu) of the element in the cell, and d is the distance (in cm) from the

cell to the substrate. The ability to change the flux of atoms emitted from the cell allows a high

degree of control over the stoichiometry of the deposited film. The purity of the atomic beam

emitted from the cell is dependent upon the purity of the source and the vacuum level in the

chamber.86

The high vacuum inside the chamber is one of the attractive qualities of MBE that provides

a clean environment and allows highly pure films to be grown. Precise control of the substrate

temperature in MBE also allows control of the microstructure of the deposited films. The growth

rate is dependent on the flux of the elements to the substrate, the ratio of the elements, and the

substrate temperature. Lower substrate temperatures and higher fluxes can be used to produce

amorphous or fine-grained polycrystalline films. Higher substrate temperatures and lower fluxes

can be used to produce single crystal films.









A Riber 2300 MBE system (Figure 3-2) was used for all of the oxide growths. The growth

chamber was pumped down to a range of 1-5x10-9 torr using an Oxford Cryo-Torr 8 cryopump.

The MBE system is equipped with a Reflective High Energy Electron Diffraction (RHEED) gun

to provide in-situ characterization of the oxide film during growth. It also provides information

on the substrate surface prior to growth. The MBE system contains six ports with five of them

containing Knudsen cells (3 Riber 125 LK's with 25 cc crucibles, 1 Varian 0981-4135 with a 40

cc crucible, and 1 EPI 91-734 with a 25 cc crucible) for various sources (Sc, Ga, Mg, Ca, and

Sm) and the remaining port containing the oxygen plasma source. The temperature of the

Knudsen cells is controlled by a FICS 10 controller that adjusts the power output of an external

power supply whose power cables are connected to two posts on the cell.

An MDP21 radio frequency (rf) source from Oxford Applied Research was used as the

oxygen source for the growths. It was operated at a frequency of 13.56 MHz with a forward

power of 300 W and a reflected power of 2-3 W. Oxygen (99.995%) was supplied to the plasma

head using a high purity 8161c Unit (Celerity) 02 mass flow controller (MFC) that had a 3 sccm

full scale range. The plasma is generated as soon as a high enough voltage is applied between

the two electrodes to create an electric field in the reactor that exceeds the breakdown field of the

gas. As soon as the high voltage arc flashes between the two electrodes, a large number of

dissociated atoms are created. The dissociated atoms and undissociated molecules then escape

into the vacuum environment through an array of fine holes in the aperture plate. The electrical

potential remains low enough so that negligible currents of ions and electrons will escape from

the discharge tube.

The substrate temperature was measured using a back side thermocouple in close

proximity to the substrate holder. The substrate thermocouple was calibrated by using pieces of









gallium antimonide (GaSb) and indium antimonide (InSb), which have melting points of 707C

and 5250C respectively. The pieces of GaSb and InSb were heated in the growth position under

a nitrogen plasma to reduce the chance of losing Sb. Loss of the group V species during heating

would result in an incorrect melting temperature.

Substrate Preparation

All substrates received an ex-situ and in-situ surface treatment prior to oxide deposition to

remove any surface contamination. A clean surface prior to deposition is critical as surface

defects and impurities can influence the overall quality of the device (i.e., Dit), the metal contact

resistance/stability, the crystal quality of the deposited film, and the epitaxial defects. Prior to

treating the surfaces, the substrates were inspected under a microscope, and an RMS roughness

was determined by AFM as a reference value. The substrates used for oxide deposition included

Si and GaN.

Silicon

Phosphorous doped (n-type) Si substrates from Wacker-Chemitronic GMBH were used for

the oxide growths involving initial calibrations. The substrates were 50 mm wafers with a (100)

orientation. The low cost and wide availability of Si made it more feasible to use when

calibrating the thickness, growth rate, composition, or uniformity of the dielectric films.

Each Si sample received an ex-situ treatment in buffered oxide etch (BOE) solution (6:1

NH4F:HF in water) to remove the native oxide layer. After removing the native oxide, the

sample was rinsed in deionized water and blown dry with an N2 gun. An rms value of 0.08 nm

was measured with AFM following this surface treatment. After receiving an ex-situ treatment,

the Si sample was immediately indium mounted to a molybdenum block and then placed under

vacuum inside the load lock of the Riber 2300 MBE system. The sample was then cleaned in-









situ by heating it up to 2000C to drive off any moisture that collected on the surface between the

time it was etched in BOE and placed under vacuum.

Gallium nitride

Gallium nitride (GaN) wafers were provided by Uniroyal and the Abernathy group (GaN

wafers were grown using a Veeco MOCVD system). The Uniroyal wafers were used for

calibrations on GaN due to their higher surface roughness and pits (Figure 3-3) that were seen on

the surface by AFM. Some of the pits had a depth as great as -114 nm which is much greater

than the thickness of the oxide films. The GaN wafers provided by the Abernathy group were

used for oxide growths that involved characterization of the crystal structure of the oxide and

fabrication of the oxide to make MOS capacitors for electrical testing. The Abernathy group

GaN wafers (Figure 3-4) had a lower surface roughness (rms as low as 0.134 nm using a 1 |tm

scan) compared to the Uniroyal GaN.

Each GaN sample received an ex-situ treatment starting with a 3 min HCl:H20 (1:1)

solution to degrease the sample and remove as much oxygen and carbon contamination as

possible. After removing the sample from the solution, it was rinsed in deionized water and

blown dry with an N2 gun. It was then given a 25 min UV-03 treatment in a UVOCS UVO

cleaner (model number 42-220) to remove any residual carbon. The sample was finally placed in

a 5 min BOE solution to remove the native oxide formed from the UV-03 treatment and then

rinsed in deionized water and dried with an N2 gun. Successful removal of the native oxide was

observed with RHEED images of the surface. The RHEED pattern of the surface with the native

oxide showed arcs, and the RHEED pattern of the BOE treated surface showed streaks (Figure 3-

5).









After receiving an ex-situ treatment, the GaN sample was immediately indium mounted to

a molybdenum block and then placed under vacuum inside the load lock of the Riber 2300 MBE

system. The sample was then given an in-situ thermal treatment at 7000C for 10 min to remove

any oxygen or carbon contamination on the surface that was not removed during the ex-situ

treatments. The room temperature RHEED pattern showed a (lxl) surface (Figure 3-5b), and a

(1x3) pattern appeared after the in-situ thermal treatment at 7000C (Figure 3-6).

Scandium Gallium Oxide Growth

Scandium gallium oxide films were deposited using a 99.999% pure Sc rod and 99.9999%

pure Ga ingot. The Sc Knudsen cell temperatures ranged from 11700C to 12000C and the Ga

Knudsen cell temperatures ranged from 7000C to 8840C. A substrate temperature of 1000C was

used with an oxygen pressure ranging from 8x10-6 Torr to 1. 1x105 Torr with an Oxford RF

plasma source at 300 W forward power and 2-3 W reflective power. Sample rotation was kept

constant at 15 rpm during the film growth. Numerous growth techniques were employed to grow

a continuous film with good electrical properties. These growth techniques are discussed in

chapter 4.

Magnesium Oxide Growth

Magnesium oxide films were grown using a 99.99% pure Mg rod at Knudsen cell

temperatures ranging from 3400C to 3600C. A substrate temperature of 1000C was used, and

films were deposited at low growth rates ranging from 0.8-1.4 nm/min since MgO films at lower

growth rates showed more stability during processing. The oxygen pressure was kept below

5x10-6 Torr with an Oxford RF plasma source at 300 W forward power and 2-3 W reflective

power. The samples were rotated during the film growth at 15 rpm.









Magnesium Scandium Oxide Growth

Magnesium scandium oxide films were grown with a fixed Mg cell temperature of 3400C

and an increasing Sc cell temperature ranging from 10900C to 11800C. A substrate temperature

of 1000C was used for all growths. The oxygen pressure was kept below 4x10-6 Torr with an

Oxford RF plasma source at 300 W forward power and 2-3 W reflective power. The samples

were rotated during the film growth at 15 rpm. The thickness and growth rate of the deposited

films increased with increasing Sc cell temperature.

Start-Up

After the samples received their ex-situ treatment and were placed under vacuum in the

load lock, liquid nitrogen was run through the cryo-panels, which served to decrease the thermal

interaction of the Knudsen cells and lower the pressure of the growth chamber. The Knudsen

cell for each source that was needed was raised at a rate of 1000C every 10 minutes until the

desired temperature was reached. The samples were transferred on a trolley to the buffer

chamber, and then a sample was loaded into the growth chamber using the manipulator (or

transfer) arm. The sample then received an in-situ thermal treatment facing towards the sources.

After receiving the thermal treatment, the sample was cooled to the desired substrate temperature

facing away from the sources. Once the substrate temperature was reached, the oxygen plasma

was lit and the desired oxygen pressure was adjusted with the 02 MFC. After reaching 90 mV

on the photodiode for the plasma, the shutters for the oxygen source and source material were

opened. The sample was then moved into the growth position facing towards the sources and

rotated at 15 rpm for the duration of the growth.









MOS Capacitor Fabrication

After the oxide films were deposited and the samples removed from the MBE system and

molybdenum block, they were processed to make MOS capacitors seen in Figure 3-7. The first

processing step involved opening up ohmic windows so that the exposed oxide could be etched

away (Figure 3-8). The second step was used to deposit ohmic contacts in the areas of oxide

that were etched away (Figure 3-9). However, a thin ring of GaN between the oxide island and

ohmic contact was left open so that the oxide could be electrically isolated from the ohmic pad.

The final processing step involved depositing metal gates of 50 |tm or 100 |tm in diameter on top

of the oxide island (Figure 3-10). Fabrication of the MOS capacitors allowed IV and CV

measurements to be taken which helped to determine the performance of the oxide. The key

processing steps involved photolithography, etching, metallization, and annealing. A complete

description of the lithography steps and more detailed information regarding lithography are

given in Appendix A.

Photolithography

Shipley 1818 was used as the photoresist (PR) in each lithography step. A Laurell WS-

400A 6NPP/Lite was used to spin the PR on the samples. Dynamic dispense was used to apply

the PR as it was dispensed at 1000 rpm (and acceleration of 1200 rpm/sec) and spun to a final

speed of 5000 rpm (and acceleration of 1500 rpm/sec). A spin speed of 5000 rpm corresponded

to a thickness range of 2.0-2.2 |tm depending on the conditions of the PR and conditions inside

the photolithography room. The samples were then given a soft bake on a Thermolyne hot plate

at 1250C for 1.5-2 minutes.

A Karl Suss MA6 mask aligner was used to align the sample to the pattern in the mask and

then expose the sample with a mercury xenon lamp at a 365 nm wavelength. Hard contact mode









was used which presses the sample firmly against the mask to minimize any diffraction effects.

Other parameters included an Al gap of 100 |tm, WEC offset of 0, and WEC type as contact.

The exposure time was calibrated based on the PR thickness and exposure dose.

After exposure, the samples were developed in either Rohm and Haas MF-319 developer

or AZ 300 MIF developer at room temperature. The development time was 30-60 seconds,

depending on the exposure time. After developing the samples, they were rinsed in DI water and

then blown dry with an N2 gun. A post bake at 1100C for 1 minute was then applied to samples

that were etched in the subsequent processing step. A post bake was not used when the next step

was metallization.

For cases in which the metal gates were lifting off the oxide, the use of LOR 3B was used

in a bi-layer stack with 1818. The LOR 3B was spun onto the sample at the same dispense and

final spin speeds as the 1818 resist. However, it was baked at 1500C for 5 minutes, which

produced a thickness of -0.25 |tm (needs to be about 1.2-1.3 times the thickness of the deposited

metal). It also received the same exposure and development times as the 1818 since the 1818 was

coated over the top of it. The high development rate of the LOR 3B provides an undercut profile

(Figure 3-11) of the film below the 1818, making it attractive for metal lift-off

Etching

A wet etching chemistry is desirable for oxide films on p-GaN as dry etching of p-GaN has

been shown to cause plasma damage, which can lead to an increase in sheet resistance of the p-

GaN and conversion to an n-GaN surface at high ion fluxes or ion energies.87'88 Etching times

were determined based on numerous samples (with the MOS capacitor patterns) etched at

different times which were then analyzed with Auger Electron Spectroscopy (AES) to see if the

oxide was completely removed from the GaN substrate. The type of etching chemistry depended









upon the type of oxide. It was found that a 2% H3P04 solution at room temperature could etch a

40-60 nm MgO film in 10-12 seconds. A H2S04:H20 (1:1) solution was used for etching

(Sc203)x(Ga203)1-x since it previously showed successful removal of Sc203 films on GaN. It was

determined that a 12 minute etch could remove a -33 nm thick film (Figure 3-12).

Dry etching is advantageous for processing of smaller features where the undercut

produced from lateral etching during the wet etch must be limited or completely eliminated.

More importantly, dry etching is desirable for stacked gate dielectrics in which the bottom

dielectric has a much greater selectivity over the top dielectric for a given wet etching solution.

The extremely high selectivity of the bottom dielectric could lead to a situation where over

etching the top dielectric causes etching and complete removal of the bottom dielectric from the

substrate. Finding a dry etch chemistry where the top dielectric etches selectively over the

bottom dielectric would prevent over etching and would allow the bottom dielectric to serve as

an etch-stop layer.

Any dry etching was performed in a Unaxis Shuttlelock Reactive Ion etcher (RIE) with

Inductively Coupled Plasma (ICP) module. The system was equipped with a 2 kW inductively

coupled power supply (13.56 MHz RF) and a 600 W RIE power supply (13.56 MHz RF). The

ICP power is used to generate reactive ions and neutrals in the chamber that chemically react

with species at the surface. This chemical component of the dry etching process leads to

isotropic etching that is selective (gases are chosen for different reactions). The RIE power

(substrate bias) is used to accelerate the energetic ions to the substrate with the purpose of

driving the surface chemical reactions rapidly and physically dislodging atoms from the surface

by sputtering. This physical component leads to anisotropic etching with no selectivity. The

process pressure in the chamber can be increased to increase the density of reactive species, but









an increase in the pressure lowers the mean free path which can affect the energy the ions strike

the substrate with.

Samples were transferred and etched on a 4" Si wafer carrier with a number of available

gases (SF6, BC13, C2, CHF3, 02, Ar, H2, CH4, N2) for etching. A thicker PR (Shipley 1045) was

used for patterning since it held up better and longer to stronger dry etching conditions compared

to thinner resists. Dry etching chemistries varied depending on the type of oxide due to the

volatilities of the etch products involved. A CH4/H2/Ar mixture was found to etch

(Sc203)x(Ga203)1-x at rates ranging from 5-32.5 nm/min at a process pressure of 5 mTorr (Figure

3-13). More importantly, the GaN did not show any detectable etching (given the -2 nm

resolution of the stylus profilometer) at the same etching conditions. Due to the higher

selectivity of (Sc203)x(Ga203)1-x over GaN in the CH4/H4/Ar chemistry, this chemistry is suitable

for selective removal of (Sc203)x(Ga203)1-x from GaN substrates (Figure 3-14).

Metallization

A Kurt Lesker CMS-18 multi target sputter deposition tool was used to sputter the ohmic

contacts and metal gates. Sputtering involves the ejection of atoms from a solid metal target due

to the momentum transfer from bombarding energetic ions (i.e., Ar+). A DC voltage is

maintained across plane parallel electrodes with the metal target serving as the cathode and the

substrate (or sample) serving as the anode. A large supply of energetic ions in the interelectrode

region is accelerated to the material target under an applied electric field. Once the energetic

ions strike the target, atoms are dislodged from the metal target by momentum transfer. The

dislodged metal atoms then deposit on the substrate. The sputter yield depends on the ion flux of

the target, the probability that the impact of the energetic ion ejects a target atom, and the

transport of the sputtered material across the interelectrode region to the substrate.









Ohmic contacts on n-GaN or u-GaN consisted of a multi-layer structure of Ti (20 nm)/ Al

(80 nm)/ Pt (40 nm)/ Au (80 nm). The Ti layer reacts with nitrogen to form TiN which makes

the ohmic, the Al layer controls the TiN reaction, the Pt layer is a diffusion barrier to prevent Al

and Au from reacting, and the Au layer is used for making contact to probe tips since the layer

does not oxidize. Ohmic contacts on p-GaN consisted of a bi-layer structure of Ni (50 nm)/Au

(80 nm). Gate contacts on the dielectric included a bi-layer structure of Pt (30 nm)/Au (120 nm).

Gate contact sizes of 50 |tm or 100 |tm were used for the MOS capacitors.

After metal deposition, metal lift-off was performed in a sonicator. Samples were

immersed in a beaker of MicroChem Nano Remover PG, which was then transferred into the

sonication bath. Samples experiencing difficulty with lift off were heated up to 50-600C for 30

minutes on a Thermolyne hot plate before using the sonicator again. Once lift-off was complete,

samples were rinsed in isopropanol then DI water and finally blown dry with an N2 gun.

Annealing

Ohmic contacts on the samples were annealed in the MBE system or an AG Associates

HeatPulse 610 RTA system. Annealing conditions were strongly dependent on the doping

density of the n- and p-GaN material. Oxides on n-GaN or u-GaN were primarily annealed for

45 seconds at 4000C in the growth chamber. Other samples were annealed at 7000C for 30

seconds in the RTA system under an N2 ambient. Oxides on p-GaN were annealed at 3000C for

1 min in the RTA system under an N2 ambient. Indium on the backside of the samples was

removed (refer to Appendix A regarding the procedure) prior to annealing the samples in the

RTA system.









Materials Characterization

Numerous characterization techniques were used to analyze the deposited oxide films. The

four primary areas of characterization included surface, structural, chemical, and electrical

analysis. Surface analysis is important for future processing of the material as etching and

deposition of metal to form contacts is sensitive to the morphology and roughness of the surface.

Structural analysis is critical in determining the crystal structure, crystal phases, and types of

defects present within the film. These characteristics are crucial to the effectiveness of the

dielectric, as a polycrystalline film with numerous defects would provide multiple pathways for

gate leakage to occur. Chemical analysis is extremely important in determining the amount and

type of species within the film as well as how the species are bonded. Electrical analysis is

critical in measuring the performance of the oxide and determining the optimum growth

parameters that produce the best electrical results. Most of the following characterization

methods can be found in reference 89.

Scanning Electron Microscopy (SEM)

Scanning Electron Microscopy (SEM) is used for analyzing the topography and surface

morphology of samples. High magnifications (up to 500,000x for field emission SEM) and good

depth of field make SEM attractive for surface analysis. The technique uses an electron beam as

its source with beam energies ranging from 0.5 keV to 30 keV. Interaction of the beam with the

sample produces backscattered electrons (BSE) and secondary electrons (SE). Elastic scattering

is responsible for backscattered electrons in which the trajectory of the beam electron is changed

without altering the kinetic energy of the electrons. Backscattered electrons are used for atomic

number or compositional contrast. Inelastic scattering is responsible for secondary electrons in

which energy is transferred from the beam electrons to atoms of the specimen, resulting in

emitted electrons with energies less than 50 eV. Secondary electrons strongly affect the









topographical image. An important limitation of SEM is that samples must be conductive to

prevent charging (causes distortions in image) from occurring. Since the deposited oxide films

are not conductive, they can be coated with carbon or a lower beam voltage can be used to

minimize the charging.

A JEOL 6400 and JEOL JSM-6335F were used to characterize the oxide films. The JEOL

6400 is a thermionic emission SEM that uses a tungsten filament. Thermionic emission occurs

when enough heat is applied to the filament so that electrons can overcome the work function of

the material and escape from the material itself. Some of the disadvantages of thermionic

emission include relatively low brightness, evaporation of the cathode material, and thermal drift

during operation. The JEOL JSM-6335F is a field emission SEM that uses a LaB6 filament.

Field emission occurs by applying an electric field (that can be concentrated to an extreme level)

to reduce the potential barrier that electrons need to overcome. The primary advantage of the

field emission SEM is its high spatial resolution (<2 nm which is 3-6 times better than an SEM

utilizing thermionic emission). Both instruments were used for analyzing as-grown oxide films

and samples that were processed as diodes for electrical testing. They were useful for detecting

obvious defects or pinholes that were attributed to shorting in specific MOS capacitors.

Atomic Force Microscopy (AFM)

Atomic Force Microscopy (AFM) can also provide information on the topography and

morphology as well as the root mean square (RMS) roughness of the surface. An AFM

Dimension 3100 in tapping mode was used for measuring the surface roughness of the oxide

films and as-received GaN substrates as well as the surface morphology and topography of as-

grown oxide samples and processed diodes. In tapping mode, the tip of the stylus (made of

Si3N4) is brought into close proximity to the surface so the van der Waals forces between the

probe tip and surface atoms of the sample can be measured. These forces depend on the probe









geometry, the nature of the sample, contamination on the sample surface, and distance between

the probe tip and sample surface. The forces lead to deflection of the cantilever which holds the

tip at the end. The deflection is then measured by a laser spot that is reflected off the tip and

collected with a photodiode. The intensity of the reflected light is processed as the height for

that point on the surface. Rastering the tip across the sample surface allows a 3-D map to be

created, which can be used to calculate the RMS roughness.

Sensitivity of the AFM depends greatly on the sensitivity of the deflection and sharpness

of the tip. The tapping mode tips used to characterize the oxide samples and GaN substrates had

a tip radius of 5 nm and deflection sensitivity of -0.01 nm. Contact mode is an alternate AFM

method that can be used, but the tip radius is -20 nm, which greatly reduces the resolution.

Reflective High Energy Electron Diffraction (RHEED)

Reflective high energy electron diffraction (RHEED) provides information on the growth

mode (2-D or 3-D), surface crystal structure, surface roughness, and surface orientation. The

surface analysis is a result of an electron beam (5-100 kV) at low impact angles (<5) which

allows electrons to pass through the top few atomic layers of the surface. After reflecting off the

surface, electrons strike a phosphorescent screen and form a diffraction pattern. The generated

diffraction pattern helps to characterize the substrate surface prior to growth, the growth

initiation mode, and the quality of the deposited films during and after growth.

Analysis by RHEED was conducted in-situ in the modified Riber 2300 MBE system

(mentioned previously) at a beam voltage of 6 kV. Single crystal surfaces showed a spotty or

streaky pattern, polycrystalline surfaces showed a ringed pattern, and amorphous surfaces

showed almost no pattern at all (Figure 3-15). A pattern with streaky lines indicated a smooth









surface growing layer-by-layer (2D), and a spotty pattern indicated a rough surface with

islanding growth (3D).

Ellipsometry

Ellipsometry is used for determining the thickness and optical constants (n and k) of

dielectric films. The technique involves the use of plane-polarized light which reflects off a

sample at a given angle and is then analyzed for a change in the polarization. Analysis of the

change in polarization yields two parameters (the azimuth and phase difference) from which the

optical properties are calculated. A Rudolph V-530044 Auto EL IV ellipsometer was used for

characterization of the oxide films.

Transmission Electron Microscopy (TEM)

Transmission electron microscopy (TEM) is a valuable instrument for providing

microstructural analysis of thin films. Its high lateral resolution (-0.15 nm) allows it to provide

detailed analysis of the morphology, defects present in the film, the atomic structure, and an

accurate calculation of the lattice constant. The high lateral resolution is obtained by using an

extremely thin simple which interacts with a focused beam of electrons. The transmitted and

forward scattered electrons form an image on the other side of the sample and a diffraction

pattern in the back focal plane. The thin samples are prepared by using a focused ion beam

(FIB) instrument which uses a beam of Ga+ ions to sputter atoms from the surface so the sample

can be thinned down or a particular area of interest can be precisely milled. A FIB FEI Strata

DB (dual beam) 235 was used to prepare the oxide films, and a TEM 2010F operating at 400

keV was used for high-resolution analysis of the oxide/GaN interface and crystal structure of the

oxide films.









X-Ray Diffraction (XRD)

X-ray diffraction (XRD) is used for determining the crystal phases and crystal structure

present in bulk films. The principle of XRD is governed by Bragg's law in Equation 3-2:

nA= 2dsinO (3-2)

where n is the number of whole wavelengths, X is the wavelength of the incident x-ray (1.5406 A

for Cu Ka), d is the spacing between planes (A), and 0 is the Bragg angle (degrees).

Constructive interference of x-rays for certain atomic planes produces characteristic diffraction

peaks. The diffraction spectrum produced from the measurement helps to determine if the film is

amorphous, polycrystalline, or single crystal. The full width at half max (FWHM) of a

diffraction peak can also be used in determining the crystal quality of the film.

A Philips APD 3720 x-ray powder diffractometer was used to characterize the oxide films.

Samples were analyzed using a Cu Kc x-ray source, and a 20 range of 20-850 was scanned

using 0.020 increments. Crystal phases were identified by standards taken from the JCPDS

Powder Diffraction File. All identified peaks were calibrated to the GaN (004) peak position (20

= 73.0780). A Phillips MPD 1880/HR with a 5-crystal analyzer and Cu Kc x-ray source was

used for x-ray reflectivity (XRR) measurements. Measurements included film thickness and

interfacial roughness at the air/oxide interface and oxide/GaN interface.

X-Ray Photoelectron Spectroscopy (XPS)

X-ray photoelectron spectroscopy (XPS) was used to look at chemical bonding in the

deposited films by measuring the binding energies of atoms in the top few monolayers. It uses x-

rays as its source to eject photoelectrons from the sample. Due to the small escape depth

(depends on KE of photoelectron and material through which it travels) of the photoelectrons,

XPS is limited to surface analysis (top few monolayers). The kinetic energy of the









photoelectrons is measured by a hemispherical analyzer and the binding energy is calculated

using Equation 3-3:

BE = hu KE 4sp (3-3)

where hu is the energy of the incident x-ray (1486.6 eV for Al and 1256.6 eV for Mg), KE is the

kinetic energy (in eV) of the photoelectron, 4sp is the work function of the spectrometer, and BE

is the binding energy (in eV) of the photoelectron. The electron binding energy is highly

influenced by its chemical surroundings. The general trend is that binding energy increases with

increasing charge on the atom.

The characteristic peaks produced in the spectrum were identified using handbooks

containing previously determined standards. The handbooks show the energies of core and

valence level electrons and Auger electrons for atoms in their zero-valence state and their

different oxidation states when bonded to other chemical species. This information was used to

identify the chemical constituents present in the film and whether any of the constituents were

bonded to each other.

Both Mg and Al anodes were used depending on the possible interference of Auger lines

with XPS lines. The photoelectron binding energy remains the same regardless of which anode

is used, but the binding energy of the Auger electron changes (KE of Auger electron does not

change with change in anode). This allows Auger lines to be separated from XPS lines in

situations where Auger lines overlap XPS lines. In situations where multiple XPS peaks overlap

each other, the peaks must be deconvoluted by using RBD Analysis Suite software. Depth

profiles were used to analyze any chemical changes at the bulk or oxide/GaN interface. A

Perkin-Elmer PHI 5100 ESCA system was used for all XPS characterization.









Auger Electron Spectroscopy (AES)

Chemical composition and film uniformity was determined by Auger Electron

Spectroscopy (AES). Auger electron spectroscopy is a three electron process that uses an

electron beam as its source. The electron beam ejects a core electron from an atom, creating an

atomic inner shell vacancy which will be filled by an electron from a higher energy (outer) shell.

As the electron drops from the higher to lower energy shell, it releases energy as an x-ray or by

ejecting electron (the "Auger electron") from one of the outer shells of the atom. Due to the low

energy (typically in the range of 50 eV to 3 keV) of Auger electrons, the escape depth is very

small (a few monolayers), limiting AES to surface analysis (Figure 3-16).90

As the kinetic energy of the Auger electrons is measured, a plot forms with peaks

characteristic of the atoms and energy levels from which the Auger electrons originated. The

kinetic energies and footprint of the peaks can be used to identify elements present in the sample

by referring to previously determined standards. The atomic composition of the identified

elements can be calculated to + 10 atomic percent. Film uniformity and analysis of the bulk can

be conducted with depth profiles. All depth profiles were taken using the 3-point method. A

Perkin-Elmer PHI 660 Scanning Auger Multiprobe was used for all AES characterization.

Current-Voltage (I-V) Measurements

A Hewlett Packard Model 4145 was used to make current-voltage measurements.

Compliance was set at 100 nA, and the voltage was swept in both negative and positive

directions until the forward and reverse breakdowns were reached. Voltages were extracted from

the I-V plot at 19.6 nA for diodes with 50 um gates and at 78.5 nA for diodes with 100 um gates.

These currents correspond to a current density of 1 mA/cm2 (typical breakdown voltages are

reported at this current density) for their respective gates. The extracted voltages were then









divided by the dielectric film thickness to determine the forward and reverse breakdown

voltages.

Dielectric breakdown is often characterized in three distinct modes.91 Mode A failures

occur at low breakdown voltages and are attributed to defects within the dielectric, defects at the

oxide/substrate interface, pinholes in the dielectric, and scratches. Mode B failures occur at

intermediate breakdown voltages and are attributed to dielectric thinning. Mode C failures occur

at high breakdown voltages and are attributed to the intrinsic nature of the dielectric.

Capacitance-Voltage (C-V) Measurements

A Hewlett Packard Model 4284 LCR connected to a Lab View based PC was used to make

capacitance-voltage measurements. The LCR meter supplied a voltage signal of superimposed

analog current (AC) and direct current (DC). The width of the bias range was chosen depending

on the doping density of the substrate. Higher doped substrates required the use of larger bias

ranges (ex. a range from 6 V to -6 V was used on an n-GaN substrate with a doping density of

lxl017 cm-3) to fully deplete the high concentration of majority carriers. Since high positive or

negative gate biases can inject carriers into the oxide (this leads to oxide trapped charge) and/or

influence the movement of mobile charges within the oxide, low doped substrates were typically

used so that low gate biases could be applied in a small bias range (ex. a range from 2 V to 0 V

was used on a u-GaN substrate with a doping density of lx1016 cm-3).

Devices were cycled at frequencies ranging from 10 kHz to 1 MHz in both series (Cs-Rs)

and parallel (Cp-Rp) modes at an oscillation voltage of 50 mV. Both low and high bias sweep

rates were also used. All devices were swept from accumulation to depletion by going from

positive to negative voltages for devices on n-type substrates and negative to positive voltages

for devices on p-type substrates. The data from the C-V curve was used to determine the









interface state density, flat band voltage shift, and dielectric constant. Information and equations

on how to calculate these values can be found in Appendix B.










Atoms or atom clusters


PBN crucible
Source material
-- Ta Heater element

Thermocouple





Figure 3-1. Illustration of a typical Knudsen effusion cell. [Reprinted with permission from B.P.
Gila, 2000. Growth and Characterization of Dielectric Materials for Wide Bandgap
Semiconductors. PhD dissertation (pg. 37, Figure 3-1). University of Florida,
Gainesville, Florida.]









SOLID
SOURCE


RF PLASMA


SOLID
SOURCE
/EED Gun





4 REED Gun


Figure 3-2. Top view sketch of Riber 2300 MBE system used for oxide growth. [Reprinted with
permission from B.P. Gila, 2000. Growth and Characterization of Dielectric
Materials for Wide Bandgap Semiconductors. PhD dissertation (pg. 38, Figure 3-2).
University of Florida, Gainesville, Florida.]























I I
"' r .





W F .
*-


p.


p *


a' -^
S..-<* .* T

.-<-f^.. .




t ; 'a
rr 1.1*


* S


Figure 3-3. AFM images showing pits at surface of as-received Uniroyal GaN. A) 3-D image of

20 |tm scan. B) 2-D image of 20 |tm scan.























































Figure 3-4. AFM images showing MOCVD GaN grown by the Abernathy group. A) 3-D image
of 5 |tm scan. B) 2-D image of 5 |tm scan.
















































Figure 3-5. RHEED images of pre-treated GaN surface. A) After UV-03 treatment. B) After
BOE treatment of UV-03 treated surface. [Reprinted with permission from B.P. Gila,
2000. Growth and Characterization of Dielectric Materials for Wide Bandgap
Semiconductors. PhD dissertation (pg. 43, Figure 3-7). University of Florida,
Gainesville, Florida.]




















































Figure 3-6. RHEED photos of GaN surface showing a (1x3) pattern following an in-situ anneal
at 7000C. A) <11-20> crystal direction. B) <1-100> crystal direction. [Reprinted
with permission from B.P. Gila, 2000. Growth and Characterization of Dielectric
Materials for Wide Bandgap Semiconductors. PhD dissertation (pg. 44, Figure 3-8).
University of Florida, Gainesville, Florida.]



































1 Oxide
Ohmic Pad GaN
Gate


Figure 3-7. Illustration of MOS capacitors that were fabricated. A) Entire design layout of all 60
diodes made from 3 mask sets. B) Blown-up image of one of the diodes.


S3 K3 K3 K3 S3
S3 S3 S3 S3 S3


S3 S3 S3 S3 S3
S3 S3 S3 S3 S3


ED ED ED ED ED
ED ED ED ED ED


S3 S3 S3 S3 S3
SD SD S3 S3 SD
























Figure 3-8. Diagram of pattern in the mask used to open windows for the ohmic pad. Black
region contained oxide that was etched away. Circular white region contained oxide
that was protected by PR during the etching.



























Figure 3-9. Diagram of pattern in the mask used to deposit ohmic pad. Black region is GaN that
metal is deposited on. Circular white region contains thin GaN ring and oxide island
protected by PR.
























Figure 3-10. Diagram of pattern in the mask used to deposit metal gate. Black region contains
ohmic pad, thin GaN ring, and part of oxide island protected by PR. Circular white
region contains part of oxide island that metal gate is deposited on top of.














substrate


A






substrate


B

Figure 3-11. Sketches of bi-layer photoresist stack. A) Undercut profile of LOR 3B underneath
the 1818 layer. B) Discontinuous metal film deposition due to undercut (provides
ease for metal lift-off).












2000-

1500-

1000.

500-

0-

-500-

-1000-

-1500-

-2000-







600

400

200

0

-200

-400

-600

-800


500 1000 1500

Kinetic Energy (eV)


500 1000 1500


2000


2000


Kinetic Energy (eV)

B

Figure 3-12. AES surface scans of as-received and etched (Sc203)x(Ga203)1-x films on GaN. A)
As-received. B) 12 minute etch shows complete removal of film.











300 W ICP
5 CH410 H2,5 Ar
350,


300-


C
250-

E 200-

150-

100-

50-
w -


GGaN
Si
Ref
v DC Bias


Z


20 30 40 50 60
RF Power (W)


120



100



80


6
60


5 CH4/10 H2I5 Ar
35 W RF


250-


0 50 100 150 200 250 300
ICP Power (W)


160


140


120 >
V)

100 M


80


B

Figure 3-13. Dry etching of (Sc203)x(Ga203)1-x on GaN and Si along with a reference piece of
GaN in a CH4/H2/Ar chemistry. A) Fixed ICP power (300 W) with increasing RF
chuck power. B) Fixed RF chuck power (35 W) with increasing ICP power.


GaN
---- Si
Ref
- DC Bias


























20 25 30 35 40 45 50 55 60 65
RF Power (W)

A


0 50 100 150 200 250 300
ICP (W)

B


Figure 3-14. Etch selectivity of (Sc203)x(Ga203)1-x over GaN for a CH4/H2/Ar etch chemistry.
A) Fixed ICP power (300 W) with increasing RF chuck power. B) Fixed RF chuck
power (35 W) with increasing ICP power.






















































Figure 3-15. Possible RHEED patterns. A) Amorphous diffraction pattern. B) Polycrystalline
diffraction pattern. C) Single crystal diffraction pattern. [Reprinted with permission
from B.P. Gila, 2000. Growth and Characterization of Dielectric Materials for Wide
Bandgap Semiconductors. PhD dissertation (pg. 47, Figure 3-11). University of
Florida, Gainesville, Florida.]

















Sample Surface
50-500A


Backscattered
S= Electrons

E = Ec Characteristic
Continuum lX-Rays
X-Rays




I I
I I.S.E. Resolution I
I E
X-Ray Resolution

Figure 3-16. An image of the penetration depth and interaction volume of an electron beam in a
material. It shows that Auger electrons only have an escape depth at the top 1.0 nm
of the surface. [Reprinted with permission from B.P. Gila, 2000. Growth and
Characterization of Dielectric Materials for Wide Bandgap Semiconductors. PhD
dissertation (pg. 50, Figure 3-14). University of Florida, Gainesville, Florida.]









CHAPTER 4
GROWTH AND CHARACTERIZATION OF SCANDIUM GALLIUM OXIDE

The objective of this work was to grow (Sc203)x(Ga203)1-x as an amorphous film that could

be used in a stacked gate dielectric with a crystalline oxide. Previous trends have shown that the

smaller the lattice mismatch to GaN, the smaller the Dit. However, dislocation defects in the

crystalline oxide (due to the lattice mismatch with GaN) act as current leakage paths that limit

the breakdown voltage. Depositing an amorphous dielectric on top of the crystalline oxide

would allow the properties of the oxide/GaN interface to be maintained while reducing the

current leakage by terminating dislocating defects in the crystalline oxide. Previous results of a

stacked gate dielectric with SiO2 deposited on top of Gd203 showed improvement of the

breakdown field from 0.3 MV/cm to 0.8 MV/cm.19'20

For (Sc203)x(Ga203)1-x to serve as a suitable dielectric in GaN-based devices, it must have

a larger band gap and dielectric constant than GaN. There are no electrical properties listed for

(Sc203)x(Ga203)1-x in literature, so the properties of Gd203, Sc203, and (Ga203)x(Gd203)1x will

be discussed to make predictions on the band gap and dielectric constant of (Sc203)x(Ga203)1-x.

Both Sc203 and Gd203 have a bixbyite crystal structure, but Sc203 has a larger band gap (6.3 eV

compared to 5.3 eV) and a larger dielectric constant (14.0 eV compared to 11.4 eV) compared to

Gd203. Based on the superior electrical properties of Sc203, it is believed that using Sc203 in

place of Gd203 will only enhance the properties of the ternary oxide system. The band gap and

dielectric constant of (Ga203)x(Gd203)1-x are 4.7 eV and 14.2 respectively, so any improvement

in these values for (Sc203)x(Ga203)1-x will place them well above the values for GaN. It will also

be critical for the oxide to have confinement with respect to both the valence and conduction

bands of GaN. Both Gd203 and Ga203 are not confined with respect to the valence band of GaN,

but (Ga203)x(Gd203)1-x has confinement with respect to both bands of GaN. Since Sc203 also









has confinement at both bands, it is believed that (Sc203)x(Ga203)-x will have confinement at

both bands, and the use of Sc203 might widen the confinement at each band.

Continuous Growth of (Sc203)x(Ga203)1-x

The use of Sc and Ga in the oxide films included two purposes. Since previous Sc203

films deposited at 1000C using a high Sc flux were polycrystalline, it was hopeful that adding Ga

would frustrate the Sc203 lattice and promote amorphous film growth. The second purpose was

using Sc to stabilize Ga in the 3+ oxidation state. While Sc has a single oxidation state of 3+, Ga

has multiple oxidation states of 3 2+, and 1 It is believed that the addition of an

electropositive element in a ternary phase will stabilize the higher oxidation state for a metal

with multiple oxidation states (examples include KMnO4, SrFeO4, and BaPbO3).55'56

Low substrate temperatures and high growth rates (due to high flux of material) are

typically used to foster amorphous film growth in MBE. Therefore, a substrate temperature of

1000C was used, and cell temperatures of 11900C (corresponding to a Sc203 growth rate of 3.2

nm/min) and 8840C (corresponding to a Ga203 growth rate of 2.3 nm/min) were used for Sc and

Ga respectively. The RF oxygen plasma was set at a pressure of 8.0x10-6 Torr with a forward

power of 300 W. A continuous growth was used in which all three shutters were simultaneously

open during the growth. During the growth and at the end of the growth, RHEED showed a light

arc (Figure 4-1) indicative of polycrystalline film growth. Characterization with TEM also

showed arcs in the SAD pattern (Figure 4-2), and a HRTEM image in Figure 4-3 shows the

rotation of grains in different directions. Analysis with XRD revealed no peaks (except for those

of the GaN and sapphire), providing further evidence that a fine-grained polycrystalline film was

present with no preferred orientation. Characterization with AFM showed an RMS roughness of









5.65 nm for a 1 |tm scan and an RMS roughness of 6.78 nm for a 5 |tm scan (Figure 4-4). The

high surface roughness was associated with the extremely high growth rate of 6.0 nm/min.

An AES surface scan revealed that the films were rich in Sc with a Sc to Ga peak-to-peak

ratio of 2.25 (Figure 4-5a). Further analysis with a depth profile revealed surface segregation of

Ga (Figure 4-5b). One of the mechanisms that drives surface enrichment is the segregation of

the species with the weakest bond.92 The segregation of Ga was attributed to the weaker bond

between Ga and O compared to Sc and O. Looking at the electronegativity values for Sc (1.2)

and Ga (1.82), it can be seen that Sc is much more electropositive than Ga and has a higher

reactivity in forming a compound with O (3.44).93 Segregation is generally eliminated by

growing in a kinetically limited regime at low temperatures and high growth rates.94-96 Since the

surface enrichment of Ga in (Sc203)x(Ga203)1-x occurred under these growth conditions,

alternative growth techniques were investigated to eliminate the Ga segregation.

Digital Growth of (Sc203)x(Ga203)1-x

In an attempt to eliminate the segregation of Ga at the surface, a digital growth technique

was used. This technique was previously used for MgCaO to prevent the segregation of Ca.47

The digital growth involved repeatedly alternating the opening and closing of the Sc and Ga

shutters at 10 second intervals (10:10) during continuous exposure from the oxygen plasma

(Figure 4-6). A polycrystalline RHEED pattern was present for the entire growth, and no peaks

appeared in the XRD scan except for peaks from the substrate. AFM showed an RMS roughness

of 4.12 nm for a 1 |jm scan and an RMS roughness of 5.01 nm for a 5 |tm scan (Figure 4-7). The

surface roughness was lower compared to the surface roughness for the continuous growth. This

was attributed to the lower growth rate of 3.0 nm/min compared to the 6.0 nm/min growth rate









for the continuous growth. The AES depth profile in Figure 4-8 shows that the digital growth

technique did not eliminate the segregation of Ga at the surface of the films.

Growth with Closure of Ga Shutter

A third growth technique was employed which involved closing the Ga shutter towards the

end of the growth for a certain amount of time while the Sc and O shutters remained open

continuously (Figure 4-9). This technique was previously employed to eliminate the segregation

of In in the growth of InGaN.97 The oxygen pressure was also increased to 1.2x10-5 Torr to

increase the VI/III ratio. Various times were investigated to determine the optimal time that

would successfully eliminate the surface enrichment of Ga. Table 4-1 and Figure 4-10 show that

the Sc:O and Sc:Ga ratios increase with increasing time that the Ga shutter was closed towards

the end of the growth, and the Ga:O ratio decreases with increasing time. It was determined that

closing the Ga shutter for the final 90 seconds of a 6 minute growth successfully eliminated the

segregation of Ga (Figure 4-11).

It can also be seen in the depth profile that the intensities of the Sc and O increase and the

intensity of the Ga decreases at the oxide/GaN interface. This same effect was also present in

samples with (Sc203)x(Ga203)1-x on Si (Figure 4-12). Further analysis with HRTEM showed a

very thin, faint line at the interface (Figures 4-13). This same occurrence was seen in a HRTEM

cross-sectional image of (Ga203)x(Gd203)1-x on GaAs.98 The thin layer on GaAs (2-3

monolayers) was identified as single crystal Gd203. The initial formation of a Gd203 layer was

attributed to Gd (electronegativity of 1.2) having a higher reactivity with oxygen and being more

electropositive compared to Ga (electronegativity of 1.82). Since Sc has the same

electronegativity value as Gd and has a much greater value than Ga, it appears that a similar

trend is present in the (Sc203)x(Ga203)1-x film with the thin layer at the interface representing

Sc203 (Figure 4-14).









Characterization with AFM revealed an RMS roughness of 2.98 nm for a 1 |tm scan and an

RMS roughness of 3.79 nm for a 5 |tm scan (Figure 4-15). The large surface roughness was a

result of the high 5.5 nm/min growth rate. However, the surface roughness was lower compared

to the surface roughness for the continuous and digital growths. This was attributed to the

elimination of the Ga surface segregation.99

Electrical Testing of (Sc203)x(Ga203)1-x

After fabricating MOS capacitors, current-voltage (I-V) measurements were taken to

determine the breakdown voltage. Figure 4-16 shows that the (Sc203)x(Ga203)1-x film (33 nm)

has a poor breakdown field of 0.15 MV/cm at 1 mA/cm2. The leakage current is so high that the

oxide appears to be more of a conductor. The low breakdown field is indicative of a mode A

failure, which is due to defects or pinholes in the oxide or defects at the oxide/semiconductor

interface. The film was analyzed further with XPS to determine the root cause of the premature

breakdown.

The National Institute of Standards and Technology (NIST) XPS database100 was used to

reference the characteristic binding energies of all the possible chemical species present in the

(Sc203)x(Ga203)1-x film (Table 4-2). The objective of the XPS analysis was to determine if free

Ga or Sc metal was present in the film that could act as a dopant atom and create an electrical

pathway between the metal gate and GaN substrate. Figures 4-17 to 4-19 indicate the presence

of both Ga203 and Ga metal phases. A 6 eV difference between the two phases is seen for the

Ga LMM (Auger) energy level, and a 2 eV difference between the two phases is seen for both

the Ga 2p3/2 and 3d energy levels. Analysis of the Sc 2p3/2 energy level (Figure 4-20) revealed

that only the Sc203 phase is present. A peak at 401.9 eV corresponding to Sc203 is present, but









no peak appears at 398.3 eV, which is indicative of Sc metal. It can be seen from the XPS data

that the free Ga metal present in the film was responsible for the poor breakdown field.

After determining the root cause of the breakdown, (Sc203)x(Ga203)1-x films were grown at

lower Ga cell temperatures to eliminate the free Ga metal present in the oxide. The Sc cell

temperature was also reduced to make more O atoms available to the Ga atoms and to reduce the

overall metal to oxygen ratio, which was higher than desired. Table 4-3 shows that the

breakdown voltage increases as the Ga cell temperature decreases. However, the breakdown

voltages were still poor. Below a cell temperature of 6750C, Ga was no longer detected in the

films using AES. Current-voltage measurements were also taken for digital and continuous films

grown at various combinations of high and low Ga and Sc cell temperatures, but the breakdown

fields were all lower than 0.5 MV/cm. Because of the poor breakdown voltages for the

(Sc203)x(Ga203)1-x films, no C-V measurements were made.

It does not appear that (Sc203)x(Ga203)1-x is a feasible dielectric for GaN-based devices.

Previous results with (Gd203)x(Ga203)1-x on GaAs revealed that the breakdown field strength

increased as the films became richer in Gd.55'56 A film with a Gd concentration of 14% had a

breakdown field of-1.9 MV/cm, and the breakdown field increased to 2.5 MV/cm with an

increase in the Gd concentration to 20%. However, the best results were obtained with a pure

Gd203 film as it had an even higher breakdown field of 3.5 MV/cm. It appears that this same

trend is present for (Sc203)x(Ga203)1-x as films with increasing amounts of Sc exhibited higher

breakdown fields with a pure Sc203 film having the highest breakdown field (-2.70 MV/cm). It

is believed that the incorporation of Ga into the films creates defects that diminish the insulating

properties of the oxide.









Table 4-1. Auger peak-to-peak ratios for Ga:O, Sc:O, and Sc:Ga as function of the amount of
time that the Ga shutter was closed towards the end of the growth.
Ga shutter closure time (sec) Ga:O Sc:O Sc:Ga
0 0.21 0.48 2.25
30 0.18 0.54 3.10
45 0.14 0.56 3.90
60 0.11 0.59 4.44
75 0.11 0.60 5.38
90 0.11 0.61 5.66
120 0.08 0.65 7.96









Table 4-2. Characteristic binding energies of possible phases present in (Sc203)x(Ga203)1-x.
Element Spectral Line Phase Binding Energy (eV)
Ga LMM (Auger) Ga203 191.2
Ga LMM (Auger) Ga 185.3
Ga 2p3/2 Ga203 20.5
Ga 2p3/2 Ga 18.5
Ga 3d Ga203 1117.8
Ga 3d Ga 1116.5
Sc 2p3/2 Sc203 401.9
Sc 2p3/2 Sc 398.3









Table 4-3. Breakdown voltage as a function of decreasing Ga cell temperature.
Sample TGa (C) Ts, (C) tox (nm) G (nm/min) Vbd (MV/cm) at 1 mA/cm2
1 865 1190 33 5.5 0.15
2 770 1180 47 2.4 0.70
3 750 1180 42 2.1 1.00
4 725 1180 40 2.0 1.40

































Figure 4-1. RHEED image of (Sc203)x(Ga203)1-x on GaN during and after growth.

































Figure 4-2. TEM SAD pattern of (Sc203)x(Ga203)1-x on GaN.


































Figure 4-3. HRTEM image of (Sc203)x(Ga203)1-x on GaN.














































Figure 4-4. AFM images of (Sc203)x(Ga203)1-x on GaN for a continuous growth. A) 1 |tm scan
with RMS roughness of 5.65 nm. B) 5 |tm scan with RMS roughness of 6.78 nm.


200nm
000"aftw1k,











2000


1000


-1000


-2000


-3000


Kinetic Energy (eV)

A


80000

70000

60000

50000

40000

30000


20000-

10000 Ga


0 20 40 60 80

Cylces

B

Figure 4-5. AES analysis of continuous growth for (Sc203)x(Ga203)1-x on GaN. A) Surface
scan. B) Depth profile.











0


inL..Fi.D~]Li


Figure 4-6. Diagram of a digital growth technique in which the Sc and Ga shutters are alternated
for a given time sequence while the oxygen shutter is open continuously throughout
the entire growth.


2






















































Figure 4-7. AFM images of (Sc203)x(Ga203)1-x on GaN for a digital growth. A) 1 |tm scan with
RMS roughness of 4.12 nm. B) 5 rtm scan with RMS roughness of 5.01 nm.









2000

1500

1000

500

0

-500

-1000

-1500

-2000


Kinetic Energy (eV)

A


80000


60000



40000


20000

Ga


0 10 20 30 40 50 60

Cycles

B

Figure 4-8. AES analysis of digital growth for (Sc203)x(Ga203)1-x on GaN. A) Surface scan. B)
Depth profile.










-.. I-----

---- --------------------------------------[


Figure 4-9. Diagram of growth technique in which the Ga shutter is closed towards the end of the
growth for a designated amount of time while the Sc and O shutters are open
continuously.

























Sc:Ga ratio
2-

0.0 0.5 1.0 1.5 2.1

Ga Shutter Closure Time (sec)

A

1-

-A- Ga:O ratio
Sc:O ratio



-I







~~~ ~- ---------- -- _____ __ ^


Ga Shutter Closure Time (sec)

B

Figure 4-10. Change in Auger peak-to-peak ratios as a function of the amount of time that the Ga
shutter is closed towards the end of growth. A) Sc:Ga. B) Ga:O and Sc:O.












3000


2000


1000


0


-1000


-2000


-3000








80000


0 10 20 30 40
Cycles


2000


50 60 70


Figure 4-11. AES analysis of growth with Ga shutter closure for (Sc203)x(Ga203)1-x on GaN. A)
Surface scan. B) Depth profile.


500 1000 1500

Kinetic Energy (eV)

A


60000



40000



20000










50000 S


40000


) 30000
C

O
S20000


10000
Si
Ga
/--

0 II II
0 20 40 60 80
Cycles

Figure 4-12. AES depth profile of growth with Ga shutter closure for (Sc203)x(Ga203)1-x on Si.


































Figure 4-13. Low magnification cross-section TEM image of (Sc203)x(Ga203)1-x on GaN with a
thin Sc203 layer at the GaN/oxide interface.



































Figure 4-14. High magnification cross-section TEM image of (Sc203)x(Ga203)1-x on GaN with a
thin Sc203 layer at the GaN/oxide interface.






















































Figure 4-15. AFM images of (Sc203)x(Ga203)1-x on GaN for a growth with the Ga shutter closed
towards the end. A) 1 |tm scan with RMS roughness of 2.98 nm. B) 5 |tm scan with
RMS roughness of 3.79 nm.











1.00E-007-



5.00E-008-



SO.OOE+000-
0)

0 -5.00E-008-



-1.OOE-007

-1.0 -0.5 0.0 0.5 1.0

Voltage (V)
Figure 4-16. Current-voltage (I-V) plot of (Sc203)x(Ga203)1-x film deposited at 1000C. Film
stoichiometry was rich in Sc.








22000


20000
Ga
18000-
S. / 6 eV
16000-


C" 14000-

O
0 12000-


10000-
I I I I I I '
194 192 190 188 186 184 182

Binding Energy (eV)

Figure 4-17. Ga LMM level shows a 6 eV difference between the Ga203 and Ga metal peaks.














:Ga
160000-
U-


0
0 140000.


120000-

1121 1120 1119 1118 1117 1116 1115 1114

Binding Energy(eV)

Figure 4-18. Ga 2p3/2 level shows a 2 eV difference between the Ga203 and Ga metal peaks.









5000- Ga0

4500 2eV

4000

U 3500
S3000 02s Ga
3000-

S2500

O 2000

1500

1000

500 ,,I,, ,
26 24 22 20 18 16

Binding Energy (eV)

Figure 4-19. Ga 3d level shows a 2 eV difference between the Ga203 and Ga metal peaks.









70000 3/2


60000


U 50000


40000
0

30000


20000 ,
408 406 404 402 400 398

Binding Energy (eV)

Figure 4-20. Sc 2p3/2 level only shows the presence of a Sc203 phase.









CHAPTER 5
OPTIMIZATION OF MAGNESIUM OXDE

Previous results with MgO showed the best electrical results (i.e., 4.4 MV/cm breakdown

field and Dit value of 1x1011 eV-cm-2) at low oxygen pressures (high Mg to O ratio) and high

growth rates.38 However, further optimization is needed to make the films more environmentally

and thermally stable. Films grown at higher growth rates show deterioration in air after a few

days and etch in DI water within 10 seconds. Considering the number of processing steps that

require a DI rinse and the fact that most developers are water based (i.e., AZ 300 MIF developer

is 97.5% water), it is essential to find a set of growth parameters to improve the environmental

stability of MgO.

MgO Growth at Low Growth Rates and Oxygen Pressures

Utilizing both lower growth rates (<1.3 nm/min) and oxygen pressures (<5x106 Torr and

Mg:O ratio of 0.68) improved the environmental stability immensely. Films showed no

deterioration in air over a period of a few months, and fabricated MOS capacitors maintained

breakdown fields greater than 3.5 MV/cm (at 1 mA/cm2) after receiving a variety of wet

processing treatments. The wet treatments included DI water, AZ 300 MIF developer, and PG

remover (Table 5-1) since these are the common wet chemicals that samples are treated with

during processing. Sixty diodes from an as-received MgO sample were measured, and then the

sample was cleaved into 3 separate pieces with each piece receiving one of the three wet

treatments. A 1 minute rinse in DI water showed no etching or degrading of the MgO film as the

tested diode had a forward breakdown voltage of 14.9 V (3.82 mV/cm) at 1 mA/cm2 before the

treatment and 14.8 V (3.79 MV/cm) after the treatment (Figure 5-1). A 3 minute treatment in

developer also revealed no deterioration of the MgO film as the tested diode had a forward

breakdown voltage of 14.1 V (3.62 MV/cm) at 1 mA/cm2 before the treatment and 14.5 V (3.72









MV/cm) after the treatment (Figure 5-2). A 10 minute treatment in PG remover showed no

effect on the MgO film as the measured diode had a forward breakdown voltage of 14.1 V (3.62

MV/cm) at 1 mA/cm2 before the treatment and 13.8 V (3.54 MV/cm) after the treatment (Figure

5-3). Despite the improved environmental stability, MgO is not thermally stabile as high

temperature anneals (10000C for 2 minutes) cause degradation due to increased surface and

interfacial roughnesses.41 The addition of a Sc203 cap has been shown to provide thermal

stability, but the use of the capping layer adds an additional processing step since it must be dry

etched prior to wet etch removal of the MgO layer.32 This provided motivation to determine if

the addition of Sc to MgO (MgxScyOz was formed) could increase the environmental and thermal

stability of the film.

Results of MgxScyOz

Previous results revealed that MgxScyOz degraded and etched at a much slower rate than

MgO, but significant degradation occurred after annealing.101 Since the previous MgxScyOz

films were grown at high oxygen pressures and growth rates, it was hopeful that lower oxygen

pressures and growth rates could enhance the stability of the film as these growth conditions did

for MgO. The electrical results of MgxScyOz were also investigated to determine if any

improvements are made in the breakdown voltage, flatband voltage shift, or Dit with the addition

of Sc to MgO.

Three separate films were deposited on u-GaN using a substrate temperature of 1000C, an

oxygen pressure less than 4x10-6 Torr, a Mg cell temperature of 3400C (corresponds to 1.3

nm/min MgO growth rate), and increasing Sc cell temperatures of 1090 C, 1135 C, and

11800C (corresponds to Sc203 growth rate of 1.1 nm/min). The growth with the Sc cell

temperature at 10900C yielded a growth rate of 1.47 nm/min with a film thickness of 43.7 nm.









Figure 5-4 shows that the film had a forward breakdown voltage of 15.7 V (3.59 MV/cm

breakdown field) at 1 mA/cm2. Thirty six out of 60 diodes were tested, and 10 of the 36 (28 %)

diodes had a breakdown voltage greater than 10 V. A Dit of 4.0x1011 eV-cm-2 was calculated at

0.4 eV below the conduction band using the Terman method. Despite the good breakdown

voltage and Dit, the film had an extremely high flatband voltage shift of 5.30 V at a frequency of

10 kHz (Figure 5-5). Besides the presence of fixed oxide charge (Qox) and interface trapped

charge (Dit), oxide trapped charge (Qot) was also present from the large applied gate bias of 12 V

(wide scanning range from 12 to 0 V was used to obtain distinct accumulation and depletion

regions). When using the same frequency and scanning rate but applying a smaller gate bias of

10 V (scanning range was from 10 V to 2 V), a lower flatband voltage shift of 4.65 V was

obtained. Given the flatband voltage shift difference of 0.65 V between the two scans, it appears

that the larger bias injected more carriers into the oxide (Figure 5-6). Since a positive flatband

voltage shift indicates the accumulation of negative charges in the oxide, it appears that the large

positive bias injected electrons from the semiconductor into the oxide.89

The deposition with the Sc cell temperature at 11350C had a growth rate of 1.84 nm/min

with a film thickness of 55.1 nm. A forward breakdown voltage of 22.0 V (3.99 MV/cm

breakdown field) was obtained at 1 mA/cm2 (Figure 5-7). Thirty five out of 60 diodes were

tested, and 17 of the 35 (48%) diodes had a breakdown voltage greater than 20 V. A Dit of

2.2x101 eV- cm2 was calculated at 0.4 eV below the conduction band using the Terman method.

The film had a large flatband voltage shift of 4.35 V at a frequency of 10 kHz, and a small hump

was present in the C-V curve between 2 V and 4 V (Figure 5-8). The hump is indicative of a

specific trap in the oxide that could be a result of a defect incurred during sample preparation

from one of the cleaning steps or from In mounting the sample. It is also possible that the solid









solubility limit of Sc in MgO was reached under these growth conditions, and the formation of

two phases (MgO and Sc203) led to the creation of a trap. A lower flatband voltage shift of 3.89

V was obtained by using a scanning range with a smaller gate bias of 10 V (sweep from 10 V to

0 V). The 0.46 V difference between the two scans was once again an indicator of trapped oxide

charge present in the film as the scan using the larger bias injected more carriers into the oxide.

The film deposited with a Sc cell temperature at 11800C produced a growth rate of 2.26

nm/min with a film thickness of 67.7 nm. A forward breakdown voltage of 26.7 V (3.94 MV/cm

breakdown field) was achieved at 1 mA/cm2 (Figure 5-9). Twenty seven out of 60 diodes were

tested, and 14 of the 27 (52%) diodes had a breakdown voltage greater than 25 V. A Dit of

1.0x101 eV- cm2 was calculated at 0.4 eV below the conduction band using the Terman method.

A flatband voltage shift of 3.83 V was obtained at a frequency of 10 kHz, and a small hump was

also present in the C-V curve between 1 V and 3 V (Figure 5-10). A lower flatband voltage shift

(VFB = 2.91 V) was obtained once again by using a sweep range with a lower applied gate bias

(sweep from 10 V to 0 V).

All three MgxScyOz films had breakdown fields greater than 3.5 MV/cm and Dit values in

the low 1011 eV- cm2 range, but they also had flatband voltage shifts of 3 V or greater (Table 5-

2). Given the different valences of Sc (3 ) and Mg (2 ) and the different crystal structures and

lattice constants for MgO and Sc203, it is expected that the two would have a low solid

solubility. It is believed that the low solubility of the two compounds and mixed valences

generate a large number of defects within the oxide that are responsible for the large flatband

voltage shift.

The previous trend with MgO showed that better electrical results (Vbd and Dit) were

obtained at higher Mg:O ratios.38 This same trend is apparent for the MgxScyOz films as the









flatband voltage shift and Dit decreased with increasing metal to oxygen ratio due to the

increasing Sc cell temperature at constant oxygen pressure and Mg cell temperature (Figure 5-

11). Although the films showed high breakdown fields and low Dit values, the large flatband

voltage shifts make MgxScyOz a poor dielectric to use on GaN. Because of the large flatband

voltage shifts, the thermal and environmental stability of the films at the new growth conditions

were not investigated.









Table 5-1. Breakdown field values (at 1 mA/cm2) of tested diodes before and after various wet
processing treatments.
Wet treatment Vbd (MV/cm) at 1 mA/cm2 Vbd (MV/cm) at 1 mA/cm2
before treatment after treatment
1 min DI H20 3.82 3.79
3 min developer 3.62 3.72
10 min PG remover 3.62 3.54









Table 5-2. Electrical results for MgxScyOz films on GaN for increasing Sc cell temperatures.
Parameter MgxScyOz MgxScyOz MgxScyOz
(Ts =10900C) (Tsc=11350C) (Ts =11800C)
tox (nm) 43.7 55.1 67.7
G (nm/min) 1.47 1.84 2.26
Vhd (MV/cm) 3.59 3.99 3.94


at 1 mA/cm2
Dit (eV- cm-2)
at Eo-0.4 eV
VFB (V)
Diodes tested
Diodes > 10 V
Diodes > 20 V
Diodes > 25 V


4.0x1011

5.30
36/60 (60%)
10/36 (28%)


2.2x1011

4.35
35/60 (58%)

17/35 (48%)
17/35 (48%)


1.0x1011

3.83
27/60 (45%)


14/27 (52%-
---------------
14/27(152%)









1.00E-007


-- As-received
--- 1 nin DI -0 treatment


5.00E-008 -



0. OOOE+000
0)


S-5.00E-008




-1.00E-007 -
-20 -10 0 10

Voltage (

Figure 5-1. Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 1 minute DI
water treatment. Breakdown field was 3.82 MV/cm at 1 mA/cm2 before the treatment
and 3.79 MV/cm after the treatment. Compliance was 100 nA.









1.00E-007



8.00E-008


6.00E-008



4.00E-008


<[

***
C
Q)
L_
L

0


-- As-received
A- 3 nin Developer treatment


2.00E-008 /-



O.OOE+000 *- &A ,, ,. t A A A N
0 2 4 6 8 10 12 14

Voltage (V)

Figure 5-2. Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 3 minute
treatment in developer. Breakdown field was 3.62 MV/cm at 1 mA/cm2 before the
treatment and 3.72 MV/cm after the treatment. Compliance was 100 nA.









-- As-received
-A- 10 nin PG Remover treatment


< 6.00E-008 /



L. 4.00E-008 -



2.00E-008-



0.00E+000-
0 2 4 6 8 10 12 14 16

Voltage ()

Figure 5-3. Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 10 minute
treatment in PG remover. Breakdown field was 3.62 MV/cm at 1 mA/cm2 before the
treatment and 3.54 MV/cm after the treatment. Compliance was 100 nA.


1.00E-007.


-I-I









1.OOE-007-


5.00E-008-


L.
L.

0


0.OOE-+00 -


-5.00E-008-




-1.00E-007-_
-20 -10 0 10

Vdtae ()

Figure 5-4. Current-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 10900C.
Breakdown field was 3.59 MV/cm at 1 mA/cm2 for a film thickness of 43.7 nm.
Compliance was 100 nA.


















LL
4)



40.

CL
0


1.40E-011


1.20E-011


1.00E-011


8.00E-012


6.00E-012


4.00E-012


2.00E-012 -


0.OOE+000 I I I, i
0 2 4 6 8 10 12

Voltage (V)

Figure 5-5. Capacitance-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of
1090C. Flatband voltage shift of 5.30 V and Dit of 4.0x011 eV cm-2 was calculated
from the C-V curve taken at a frequency of 10 kHz.









1.40E-011-


1.20E-011-


LL 1.00E-011-
0)
r 8.00E-012-


0 6.00E-012-
(0
,.
4.00E-012-


2.00E-012-


0.OOE~00-


*


I"



i



--- 10to2Vscan
-*--- 12toVscan


2
2


4
4


6


Vdtage (V)

Figure 5-6. Capacitance-voltage plot of two different scanning ranges for a MgxScyOz film on u-
GaN at a Sc cell temperature of 1090C. Flatband voltage shift difference of 0.65 V
appears between the two curves with different applied gate biases.











1.00E-007-


8.00E-008-


, 6.00E-008-


. 4.00E-008-
L_


2.00E-008-


0.00E+000-


I


5


10 15
Vdtage (V)


Figure 5-7. Current-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1135C.
Breakdown field was 3.99 MV/cm at 1 mA/cm2 for a film thickness of 55.1 nm.
Compliance was 100 nA.































0 2 4 6 8
Voltage (v)


10 12


Figure 5-8. Capacitance-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of
11350C. Flatband voltage shift of 4.35 V and Dit of 2.2x101 eV cm-2 was calculated
from the C-V curve taken at a frequency of 10 kHz.


1.00E-011


8.00E-012


6.00E-012


4.00E-012


2.00E-012


0004
LL

cm)

(D
CL

M

L)










1.00E-007-


8.00E-008-


S6.00E-008-

()
. 4.00E-008-


2.00E-008-


0.00E+000-


) 5 10 15 20 25 3
Voltage (V)


Figure 5-9. Current-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 11800C.
Breakdown field was 3.94 MV/cm at 1 mA/cm2 for a film thickness of 67.7 nm.
Compliance was 100 nA.










1.00E-011


8.00E-012 -
LL

0 6.00E-012 -
C
cA
M 4.00E-012 -
0.
CL
0
2.00E-012 -



O.OOE+000 ,, ,
0 2 4 6 8 10 12

Voltage (V)

Figure 5-10. Capacitance-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of
11800C. Flatband voltage shift of 3.83 V and Dit of 1.0x011 eV cm-2 was calculated
from the C-V curve taken at a frequency of 10 kHz.








1.0-


0.8 -



x 0.6- / *
0
/o
O .
IC




0.2- + Tc-- 1180 C, T= 150 C
S_ Tsc 1135 OC, T= 150 oC
,Tsc 1090 C, T= 150 C
0.0 1, 1 1 ,
0 2 4 6 8 10 12
Voltage (V)

Figure 5-11. Normalized capacitance-voltage (C-V) plots of MgxScyOz films on GaN at Sc cell
temperatures of 10900C, 1135C, and 11800C.









CHAPTER 6
METALLIZATION STUDY WITH MAGNESIUM OXIDE

The processing scheme for fabrication of a MOS capacitor (discussed in chapter 2)

includes oxide deposition prior to deposition of ohmic metal pads. The disadvantage of this

sequence of steps is that the oxide is annealed at extremely high temperatures (i.e., >750C in

RTA) during the ohmic anneal. High temperature annealing of MgO causes deterioration of the

MgO/GaN interface and the oxide itself.41 This problem could be avoided if the sequence of

steps was reversed so that the ohmic metal pads are deposited prior to oxide deposition. Besides

maintaining the stability of the oxide, the change in the processing scheme would provide other

important advantages as well.

Prior to ohmic metal deposition, it is extremely important to remove residual PR from the

exposed ohmic windows on the substrate surface since it can effect the contact resistance and

possibly lead to removal of the ohmic pad during metal lift-off. Most cleaning steps include an

oxygen treatment to remove the residual PR, followed by a wet treatment (i.e., BOE or HC1) to

remove the native oxide formed on the substrate surface from the oxygen treatment. With the

current processing scheme, no cleaning treatment is applied to the GaN surface prior to ohmic

metal deposition. This is done to avoid etching or degrading the oxide (covered by PR from

patterning for ohmic metallization) during the wet treatment to remove the native oxide.

Considering that MgO etches in a 2% H3PO4 solution in 10-12 seconds, a 3-5 minute wet

treatment with BOE or HC1 would severely degrade and etch the oxide. Depositing the ohmic

pads before oxide deposition would allow the GaN surface to be thoroughly cleaned prior to

metal deposition since there would be no oxide present that could be affected by the wet

treatment.









Another advantage of depositing the ohmic pads prior to oxide deposition would be the

simultaneous annealing of the pads and cleaning of the GaN surface. The current GaN surface

pre-treatment procedure includes a 7000C in-situ anneal for 10 minutes before the sample is

cooled to the desired substrate temperature for oxide deposition. Since the MBE system is at

such a low pressure (i.e., 5x10-9 Torr), the same ohmic contact that is annealed in the RTA (at

760 Torr) at >7500C can be adequately annealed at lower temperatures in the MBE system. The

MBE system also provides a much cleaner environment for annealing. An advantage for p-type

GaN is that the activation anneal can be performed at the same annealing temperature as that

used for the ohmic contacts and GaN surface cleaning treatment. Being able to perform all of

these functions in one step would eliminate extra steps in the fabrication process and provide

higher throughput.

If the processing scheme is changed so that the ohmic metallization is completed before

deposition of the oxide, two critical factors must be met. The first factor is that a surface

treatment procedure must be found that can effectively clean the GaN surface without affecting

the ohmic contact. Poor cleaning of the GaN surface could lead to a high Dit value and influence

the overall quality of the growing film. Typical wet treatments that are used to degrease the

substrate surface and remove the native oxide from the surface could lead to etching or

degradation of the ohmic contact. The second factor is that a surface treatment must be found

that will produce comparable electrical results (i.e., Dit, VFB, and Vbd) with the results previously

achieved using the old processing scheme with oxide deposition prior to ohmic metallization. It

is extremely important to find a suitable surface treatment since the current processing scheme

for the fabrication of an enhancement mode MOSFET includes ohmic metallization prior to

oxide deposition.









Metallization Study on u-GaN

Using the new processing scheme, a metallization study was performed on u-GaN

(ND-5xl016 cm-3 measured by Hall) with deposition of MgO. Cleaning of the GaN surface prior

to ohmic metallization included a 25 min UV-03 treatment followed by a 5 min BOE treatment.

After ohmic metal deposition, metal lift-off was performed to remove the excess metal and

obtain the patterned ohmic pads. Multiple surface cleaning pre-treatments were then used to

determine the one with the best electrical characteristics. Electrical results of the various surface

treatments were also compared to the surface treatment that was used in the old processing

scheme (standard: 3 min HCl:H20 (1:1), 25 min UV-03, and 5 min BOE). The following

surface treatments were analyzed: 1) 25 min UV-03, 2) 25 min UV-03 + 10 min NH40H, 3) 25

min UV-03 + 1 min BOE, and 4) 25 min UV-O3 + in-situ anneal at 7000C for 10 min under an

N2 plasma. Treatment of the surface with only UV-O3 excluded the use of wet chemicals to

remove any possibility of them having an effect on the ohmic contacts. The application of wet

treatments such as NH40H and BOE were used to remove as much of the native oxide formed

from the UV-O3 treatment without damaging the ohmic pads. The fourth treatment included the

use of an N2 plasma to form volatile species at the surface that would desorb from the surface

during the in-situ anneal. The MgO thin films were deposited at a substrate temperature of

1000C, an Mg cell temperature of 3400C, and an oxygen pressure less than 5x10-6 Torr.

All of the samples had a thickness of 39.0 nm, corresponding to a growth rate of 1.3

nm/min. The sample with the UV-O3 treatment had a breakdown voltage of 15.3 V (3.92

MV/cm) at 1 mA/cm2 (Figure 6-1). Sixty MOS capacitors were tested with 33 out of 60 (55 %)

having breakdown voltages greater than 10 V. A Dit of 2.0x011 eV- cm2 was calculated at 0.4

eV below the conduction band using the Terman method. A flatband voltage shift of 0.46 V was









calculated from the C-V curve in Figure 6-2. The flatband voltage shift was a result of the

metal-semiconductor work function difference (calculated as Dms = 1.43 eV assuming a work

function of 5.6 eV for platinum), interface trapped charge (Dit), and fixed oxide charge (Qox).

The fixed oxide charge was attributed to possible dangling bonds at the GaOx/MgO interface that

were formed during oxidation of the GaN surface from the UV-03 treatment or possible dangling

bonds present at grain boundaries or dislocations in the MgO film.

The sample with the UV-03 and NH4OH treatment included the use of a wet treatment in

an attempt to remove the native oxide formed from the UV-03 step. It had a breakdown voltage

of 15.7 V (4.02 MV/cm) at 1 mA/cm2 (Figure 6-3). Sixty diodes were tested with 39 out of the

60 diodes (65%) having a breakdown voltage greater than 10 V. A Dit of 1.8x1011 ev-^cm-2 at 0.4

eV below the conduction band was calculated using the Terman method. A flatband voltage

shift of 0.63 V was calculated from the C-V curve in Figure 6-4. Since this value is comparable

to the value obtained from the sample with only the UV-03 treatment, it is believed that the

NH4OH treatment was not successful in removing the native oxide layer formed from the UV-

03.

The combination of a UV-03 and BOE treatment was then used since BOE is commonly

used to strip the native oxide from the GaN surface. However, a short BOE treatment of only 1

minute was used since longer periods of time can lead to degradation or complete removal of the

ohmic pads. The sample with this treatment had a breakdown voltage of 14.4 V (3.69 MV/cm)

at 1 mA/cm2 (Figure 6-5). Sixty diodes were measured with 32 out of 60 diodes (53%) having a

breakdown voltage greater than 10 V. A Dit of 2.0x1011 eV-cm-2 was calculated at 0.4 eV below

the conduction band using the Terman method. A flatband voltage shift of 0.64 V was

determined using the C-V curve in Figure 6-6. Given the comparable flatband voltage shift with









the previous two surface pre-treatments, it is believed that the 1 min BOE treatment was unable

to remove the native oxide layer formed from the UV-03 treatment. It is desirable to use a

longer BOE treatment, but that could lead to damage of the ohmic contacts.

The sample treated with UV-03 and an in-situ anneal under an N2 plasma produced a

breakdown voltage of 14.9 V (3.82 MV/cm) at 1 mA/cm2 (Figure 6-7). Sixty MOS capacitors

were measured with 38 out of 60 (63%) having a breakdown voltage greater than 10 V. A Dit of

2.0x101 eV- cm2 was calculated at 0.4 eV below the conduction band using the Terman method.

A flatband voltage shift of 0.41 V was determined from the C-V curve in Figure 6-8.

All four surface pre-treatments had breakdown fields of -3.70 MV/cm or greater (Figure 6-

9 and Table 6-1), Dit values around 2.0x011 eV- cm2, and flatband voltage shifts of 0.63 V or

less (Figure 6-10). Looking at the ohmic contacts for each sample under an optical microscope

revealed that the contacts were not damaged by any of the treatments. It appears that the pre-

treatment with the in-situ N2 plasma anneal is the best surface treatment since it yielded the

lowest flatband voltage shift. However, all of the electrical values were representative of the

best MOS capacitor from each sample and do not represent the entire sampling set. More

capacitors would need to be fabricated and tested to determine a specific trend as to which pre-

treatment offers the best starting surface to grow on. The difference in the flatband voltage shifts

among the samples is also within the error of the measurement and calculations used in

determining the value.

Electrical values for the standard surface pre-treatment were taken from a different GaN

wafer in which MgO was deposited prior to ohmic metal deposition. The values included a

breakdown field of 3.67 MV/cm, a Dit of 1.0x1011 ev-cm-2 at 0.4 eV below the conduction band,

and a flatband voltage shift of 0.18 V. Since the results are comparable to the electrical results









obtained from the samples with the different surface pre-treatments, the new fabrication scheme

is a feasible process for fabricating future MOS capacitors and e-mode MOSFETs.

Electrical Results on p-GaN

A similar study was performed on p-GaN (NA-4x1017 cm-3 measured by Hall) with

deposition of MgO. However, a suitable ohmic contact was not available that could be annealed

in-situ at 7000C for 10 min. Metal stacks of Ni/Au and Pt/Au were researched, but the in-situ

anneal caused deterioration of the contacts and extremely high contact resistances (Figure 6-11).

Without the availability of a suitable ohmic contact for the in-situ anneal, the study was

performed by preparing (includes sample cleaning and mounting) and growing on samples

without ohmic metal. However, two different surface treatments, which could be used if ohmic

metal was present on p-GaN prior to sample preparation and growth, were analyzed for their

feasibility. The following surface pre-treatments on p-GaN were used in comparison to the

standard pre-treatment (3 min HCl:H20 (1:1), 25 min UV-03, and 5 min BOE): 1) 25 min UV-

03 and 2) 25 min UV-O3 + 1 min BOE. Following sample preparation, the MgO thin films were

deposited at a substrate temperature of 1000C, a Mg cell temperature of 3400C, and an oxygen

pressure less than 5x10-6 Torr. Metal gates (Pt/Au) were then sputter deposited, and In metal

was soldered along the edge of the sample to make an ohmic contact to the p-GaN.

Since all three samples were grown simultaneously, they had the same thickness of 37.6

nm, which corresponded to a growth rate of 1.25 nm/min. The sample with the standard surface

treatment had a breakdown voltage of-15.9 V (4.23 MV/cm) at 1 mA/cm2 (Figure 6-12). Thirty

out of 60 diodes were tested with 12 out of the 30 diodes (40%) having a breakdown voltage less

than -10 V. The C-V curve in Figure 6-13 shows distinct regions of accumulation and deep

depletion as the gate voltage is swept from negative to positive voltages at a frequency of 10









kHz. The broad curve is obtained because of the large bias range that was used to deplete the

high density of carriers (apparent carrier concentration was measured as 1.5x1018 cm-3 from C-V

curve). These C-V results are in contrast to previous C-V results for p-GaN MOS capacitors

with SiO2 as the dielectric. Previous results revealed a curve more representative of results for

an n-GaN MOS capacitor as the curve showed an increasing capacitance as the gate bias was

swept from negative to positive voltages.102 The C-V curve obtained in this study is the typical

curve that would be expected for a p-GaN MOS capacitor.

The other two surface treatments yielded similar electrical results. The sample that

received the surface pre-treatment with UV-03 and BOE had a breakdown voltage of -13.4 V

(3.56 MV/cm) at 1 mA/cm2 (Figure 6-14). Thirty out of 60 diodes were tested with 17 out of the

30 diodes (56 %) producing breakdown voltages less than -10 V. The C-V curve in Figure 6-15

(measured at 10 kHz) shows distinct regions of accumulation and deep depletion. The MgO

sample with only the UV-O3 pre-treatment had a breakdown voltage of -13 V (3.46 MV/cm) at 1

mA/cm2 (Figure 6-16). Thirty out of 60 diodes were tested with 15 out of the 30 diodes (50%)

having a breakdown voltage less than -10 V. The measured C-V curve (Figure 6-17) showed the

same trend as the other two samples with distinct accumulation and deep depletion regions over

a wide bias range (-8 V to 7 V).

After comparing the electrical results from the three different surface pre-treatments, it

appears that the two metallization surface treatments (25 min UV-O3 + 1 min BOE and 25 min

UV-03) are feasible for the new processing scheme in which ohmic metal is deposited prior to

oxide deposition. All three samples had breakdown fields of-3.5 MV/cm or greater with more

than 40% of the tested diodes breaking down at voltages less than -10 V (Figure 6-18). Although

the sample with the standard pre-treatment had the highest breakdown voltage out of the three,









its value was representative of one diode and not the whole set of diodes. Looking at the C-V

results in Figure 6-19, it can be seen that all three samples have a large negative flatband voltage

shift. The large flatband voltage shift is primarily attributed to the high metal-semiconductor

work function difference and oxide trapped charge (Qot). Assuming a work function of 5.6 eV

for platinum, a work function difference of -1.78 eV was calculated for the samples. Since the

flatband voltage shift was negative, it is believed that the large negative gate bias injected holes

from the semiconductor into the oxide, resulting in an equivalent negative charge in the

semiconductor. It is also a possibility that trapped electrons in the oxide were injected from the

oxide into the surface of the semiconductor. Further analysis of the C-V curve reveals that the

Dit is very similar for all three samples, but the sample with the UV-03 and BOE treatment

appears to have a slightly lower Dit based on its steeper slope.









Table 6-1. Electrical results for MgO films on u-GaN with various surface pre-treatments. The
oxide was deposited following ohmic metal deposition.
Surface pre- Vbd (MV/cm) Dit (eV-'cm-) VFB (V) Diodes > 10 V
treatment at 1 mA/cm2 at Ec-0.4 eV
25 min UV-03 3.92 2.0x101 0.46 33/60 (55%)
25 min UV-03 + 4.02 1.8x1011 0.63 39/60(65%)
10 min NH40H
25 min UV-03 + 3.69 2.0x011 0.64 32/60(53%)
1 min BOE
25 min UV-03 + 3.82 2.0x1011 0.41 38/60(63%)
N2 plasma anneal










1.00E-007.


6.00E-008-
C

4.00E-008-
0
2.00E-008-


O.OOE-K+000

0 2 4 6 8 10 12 14 16 18

dtage (V)

Figure 6-1. Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-03 surface pre-
treatment. Breakdown field was 3.92 MV/cm at 1 mA/cm2 for a film thickness of 39
nm. Compliance was 100 nA.









1.40E-011-


1.20E-011-


1.00E-011-


8.00E-012-


6.00E-012-


4.00E-012-


2.00E-012-


O.OOE+000-


voltage (V)

Figure 6-2. Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 surface
pre-treatment. Measurement was taken at a frequency of 10 kHz.


0004
LL

cm)
(D



CL


L)











1.00E-007-


5.00E-008-



S0.OOE+000-
0*


-5.00E-008-



-1.00E-007-


voltage (V)


Figure 6-3. Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-03 and 10 min
NH40H surface pre-treatment. Breakdown field was 4.02 MV/cm at 1 mA/cm2 for a
film thickness of 39 nm. Compliance was 100 nA.













1.40E-011


1.DE-O111


1.COE-O11*


8.OOE-012.


6.OOE-012.


4.00E-12.


200E-012.


0.0 0.5 1.0 1.5


vdtage (

Figure 6-4. Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 and 10 min
NH40H surface pre-treatment. Measurement was taken at a frequency of 10 kHz.


LL
%w)

0
(U

EO

(U











8.00E-012


LL 6.00E-012
(D)
0





0 2.00E-012



O.OOE+O00


0.5 1.0 1.5


Voltage ()


Figure 6-5. Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-03 and 1 min BOE
surface pre-treatment. Breakdown field was 3.69 MV/cm at 1 mA/cm2 for a film
thickness of 39 nm. Compliance was 100 nA.











8.00E-012-




LL 6.00E-012-

(D)
0
C
4.00E-012-




S42.00E-012-




0.00E+000 -


0.5
0.5


1.0
1.0


1.5
1.5


SI.
2.0


Voltage (V)

Figure 6-6. Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 and 1 min
BOE surface pre-treatment. Measurement was taken at a frequency of 10 kHz.










1.00E-007.


6.00E-008-
CD

S4.00E-008-

0
2.00E-008-


0.OOE-+00-
I I I I I I I I
0 2 4 6 8 10 12 14 16

Votage ()

Figure 6-7. Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-03 and 10 min in-
situ N2 plasma anneal at 7000C surface pre-treatment. Breakdown field was 3.82
MV/cm at 1 mA/cm2 for a film thickness of 39 nm. Compliance was 100 nA.









1.20E-011


0004
LL

cm)

(D
CL



L)


1.00E-011


8.00E-012


6.00E-012


4.00E-012


2.00E-012


-1.0 -0.5 0.0 0.5 1.0 1.5


Voltage (V)

Figure 6-8. Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 and 10 min
in-situ N2 plasma anneal at 7000C surface pre-treatment. Measurement was taken at a
frequency of 10 kHz.









1.00E-007-


8.00E-008-



6.00E-008-



4.00E-008-



2.00E-008-



0.00E+000
(


- 25 in LV-O
-*-25 nin nUV


25 nin UV-O
10ninI-14O
25rinLW-O3
in-situ NI pla
-- 25ninUV-O
1 nin BOE


k-I -- ---'**** -M--


I I
J 2


SI
4


6
6


S//










.
/*



/*
,MOVO' I
.' ,


8


10 12
10 12


14
14


16


voltage (V)

Figure 6-9. Current-voltage (I-V) plot for MgO on u-GaN with four different surface pre-
treatments. Breakdown field was measured at 1 mA/cm2 with a film thickness of 39.0
nm. Compliance was 100 nA.


C
C

04)
L.
L.
3
0





















0.4-


0.2-


n I


u.u
-0.5


11/
/f
0,t
//*1i


0.8-



0.6-


0.0


0.5


-- 25 in UV-0+
in-situ N2 plasma
---25 rrin -O3+
10 rin NH4OH
25 nin -O3
-- 25 nin -O3+
1 in BOE


1.0


1.5


2.0


Voltage (V)

Figure 6-10. Capacitance-voltage (C-V) plot for MgO on u-GaN with four different surface pre-
treatments. Measurements were taken at a frequency of 10 kHz.


1.0-


4.I




ii




/0/ ,41/~iy~f~


x
0

c3












0.0000010


0.0000005


0.0000000


-0.0000005


-0.0000010


0 5


Voltage (V)

A


1.00E-007,


5.00E-008,



O.OOE+000



-5.00E-008


-1.00E-007


-10 -5 0 5


Voltage (V)

B

Figure 6-11. Current-voltage (I-V) measurements for different ohmic metals on p-GaN. A)
Pt/Au (50 nm/80 nm). B) Ni/Au (50 nm/80 nm). Compliance was set at 1 pA for
Pt/Au and 100 nA for Ni/Au.











1.00E-007-



5.00E-008-



0.OOE+000-



-5.00E-008-



-1.00E-007-


-20


-10 0 10 20 30 4


Vdta (V)

Figure 6-12. Current-voltage (I-V) plot for MgO on p-GaN with a standard surface pre-treatment
(3 min HCl:H20 (1:1), 25 min UV-03, and 5 min BOE). Breakdown field was 4.23
MV/cm at 1 mA/cm2 for a film thickness of 37.6 nm. Compliance was 100 nA.


L.
0

















LL

04)
0
C
Cu
Efw
(D


7.00E-012-



6.50E-012-



6.00E-012-



5.50E-012-



5.00E-012-



4.50E-012-



4.00E-012-


-8
-8 -6


6


Vdtage (

Figure 6-13. Capacitance-voltage (C-V) plot for MgO on p-GaN with a standard surface pre-
treatment (3 min HCl:H20 (1:1), 25 min UV-03, and 5 min BOE). Measurement was
taken at a frequency of 10 kHz.


---


, '










O.0E+000-


-2.00EE-008-


,< -4.00E-008-


L. -6.00E-008-
L


-8.00E-008-


-1.00E-007 -


-14 -12 -10 -8 -6 -4 -2 0

Vtae (V)

Figure 6-14. Current-voltage (I-V) plot for MgO on p-GaN with a 25 min UV-03 and 1 min BOE
surface pre-treatment. Breakdown field was 3.56 MV/cm at 1 mA/cm2 with a film
thickness of 37.6 nm. Compliance was 100 nA.










6.50E-012.


6.00E-012-


5.50E-012-


5.00E-012-


4.50E-012-


4.00E-012-


3.50E-012 ,i
-8 -6 -4 -2 0 2 4 6 8


Vtage (V)


Figure 6-15. Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 and 1 min
BOE surface pre-treatment. Measurement was taken at a frequency of 10 kHz.


LL

0)
0

CU

0.

CU











O.0E+000-


-2.00EE-008-


,< -4.00E-008-
e-

L. -6.00E-008-
L


-8.00E-008-


-1.00E-007 -


-14 -12 -10 -8 -6 -4 -2 0

Vtae (V)

Figure 6-16. Current-voltage (I-V) plot for MgO on p-GaN with a 25 min UV-03 surface pre-
treatment. Breakdown field was 3.46 MV/cm at 1 mA/cm2 with a film thickness of
37.6 nm. Compliance was 100 nA.










6.50E-012-


6.00E-012-



5.50E-012-



5.00E-012-



4.50E-012-



4.00E-012


4. . ._


I I
.8 -6


I I I *
-2 0 2 4


Vdtage (V)

Figure 6-17. Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-03 surface
pre-treatment. Measurement was taken at a frequency of 10 kHz.


ii

O
0
(D


O

O.
(O
0











0.OOE+000 O m IIIaAisa A iAAAAAAAAAAAAAAA
i A
*" A'
/ /A
*/ A
-2.E-00E38 / /
A


-4. OOE-008 /


L.. -6.OOE-008 -

3 --standard: 3 rrin HCI:HO

8.OOE-008- 25 nin W-0+5 nin OE
25 inW-03
/ -A25 nin WL 3

-1.E-00E7 I AAA 1 nin BOE


-18 -16 -14 -12 -10 -8 -6 -4 -2 0

voltage ()

Figure 6-18. Current-voltage (I-V) plot for MgO on p-GaN with three different surface pre-
treatments. Breakdown field was measured at 1 mA/cm2 with a film thickness of 37.6
nm. Compliance was 100 nA.








1.00 -

0.95-

0.90 ,,

0.85-

o 0.80
0
0 0.75- I

0.70 -\ 25 nin U-O
0.65 --25 rin UV-O +
0.65- 3
1 in BOE
0.60- Standard: 3 in HCI:H2F
25 rin UV-3+ 5 min BOE
0.55 1 1 1 1 1 1 1
-8 -6 -4 -2 0 2 4 6 8

Voltage ()

Figure 6-19. Capacitance-voltage (C-V) plot for MgO on p-GaN with three different surface pre-
treatments. Measurements were taken at a frequency of 10 kHz.









CHAPTER 7
SUMMARY AND FUTURE WORK

Summary of (Sc203)x(Ga203)1-x on GaN

Scandium gallium oxide was researched as a candidate dielectric for GaN-based electronic

devices. The objective was to deposit the oxide as an amorphous film in a stacked gate dielectric

so that it could terminate leakage paths (i.e., dislocations) in the underlying crystalline oxide

film. Termination of the leakage paths would enhance the breakdown voltage of the overall

stacked gate dielectric while maintaining the properties at the GaN/crystalline oxide interface.

Low substrate temperatures and high source temperatures were initially used to drive amorphous

film growth. Characterization with RHEED, XRD, and TEM revealed the growth of a fine-

grained polycrystalline film under these conditions. Further characterization with Auger showed

surface segregation of Ga for the continuous growth technique (all shutters open continuously

during the growth). The surface segregation was attributed to the stronger bond between the Sc

and O compared to the Ga and O. A digital growth technique (opening of Sc and Ga shutters is

alternated while the O is open continuously during the growth) was then employed to eliminate

the Ga segregation, but it was unsuccessful. A third growth technique was used which involved

closing the Ga shutter for a set amount of time towards the end of the growth while the O and Sc

shutters were open continuously. This technique was successful as a uniform film was obtained.

After fabricating MOS capacitors, IV measurements were taken to determine the

breakdown field of the oxide film. Initial films (-33 nm) had extremely poor breakdown fields

of 0.15 MV/cm at 1 mA/cm2. Further analysis with XPS revealed the presence of a Ga metal

phase in addition to the Ga203 and Sc203 phases. Premature breakdown of the film was

attributed to the free Ga metal that was essentially acting as a dopant which made the film

conductive. New growth conditions were used to eliminate the free Ga metal by lowering the Ga









cell temperature. As the Ga cell temperature decreased, the breakdown field increased, but the

values were still poor as the highest value reached was only 1.40 MV/cm (at 1 mA/cm2). A

similar trend has previously been reported for (Ga203)x(Gd203)-x on GaAs as the breakdown

voltage increased with an increase in the concentration of Gd.55'56 The highest breakdown field

for that system was achieved for a pure Gd203 film. The same phenomena is seen for

(Sc203)x(Ga203)1x on GaN as the highest breakdown field was achieved for a pure Sc203 film

(-2.7 MV/cm at 1 mA/cm2). The addition of Ga to Sc203 only served to diminish the insulating

properties of the film. No further research is recommended for (Sc203)x(Ga203)1-x on GaN.

Summary of MgO Growth Optimization

Previous electrical results for MgO on GaN are very promising as a breakdown field of 4.4

MV/cm (at 1 mA/cm2) and a Dit as low as 1x1011 eV- cm-2 have been achieved. The

disadvantages of MgO are its poor environmental and thermal stability. Its poor environmental

stability has made it extremely difficult to process as it can etch in DI water within 10 seconds.

Optimization of the film growth was desired to enhance the environmental stability of the film in

both water and air. Since the best electrical results have been obtained at low oxygen pressures,

new growth conditions (substrate temperature remained at 1000C) included a low oxygen

pressure and a low Mg cell temperature to produce a low growth rate. Depositing MgO at a low

growth rate was found to significantly enhance its environmental stability. Fabricated MOS

capacitors with the optimized growth conditions maintained breakdown field values greater than

3.5 MV/cm (at 1 mA/cm2) after receiving three separate processing wet treatments. The three

separate wet treatments included 1 minute in DI water, 3 minutes in AZ 300 MIF developer, and

10 minutes in PG remover. The samples also showed no visible deterioration following their wet

treatments. Despite the improved environmental stability, MgO has not shown good thermal









stability at high temperatures. Any high temperature applications will require it to be capped

with Sc203.

The improved environmental stability of MgO was achieved at an oxygen pressure of

4.5x10-6 Torr and a growth rate of-1.3 nm/min. Previous results showed an increase in the

breakdown field and decrease in the Dit as the Mg:O ratio increased with decreasing oxygen

pressure. Oxygen pressures lower than 4.5x10-6 Torr should be investigated along with lower

growth rates to determine if there is any improvement in the electrical results. It will also be

critical to maintain a high Mg:O ratio (i.e., 0.68) under these conditions.

Given the lower lattice mismatch for MgO on GaN compared to Sc203 on GaN, MgO has

shown better electrical results than Sc203. Since MgCaO can be perfectly lattice matched to

GaN, it is expected that it would have better electrical results than MgO. However, it has shown

even worse environmental stability in air and water. Since the growth conditions for MgCaO

have not been optimized, new conditions (i.e., low oxygen pressure and low growth rate) should

be researched to determine if any improvements can be made to enhance the environmental

stability of the film. Results of previous dielectrics (MgO, Gd203, and Sc203) have been

obtained at a substrate temperature of 100'C. Since MgCaO has been primarily deposited at

3000C, growth at 1000C should also be studied for any improvements in the electrical results or

stability of the film.

Summary of Electrical Results for MgxScyOz

Given the -6.5% lattice mismatch between MgO and GaN and the 9.2% lattice mismatch

with Sc203, it was hopeful that adding Sc to MgO (to form MgxScyOz) would reduce the lattice

mismatch and provide increased stability. Previous research on MgxScyOz showed improved

stability over MgO, but no electrical results were taken. Since MgO showed both good stability









and electrical results at low oxygen pressures and growth rates, MgxScyOz films were evaluated

at these same conditions. Three separate films were grown at increasing Sc cell temperatures

(10900C, 1135C, and 11800C) with a constant substrate temperature (1000C), Mg cell

temperature (3400C), and oxygen pressure (<5x10-6 Torr). All three MgxScyOz films had

breakdown fields greater than 3.5 MV/cm and Dit values in the low 1011 eV cm-2 range, but they

also had flatband voltage shifts of 3 V or greater. The large flatband voltage shifts were

attributed to the different valences of Sc (+3) and Mg (+2) which could generate dangling bonds

and defects in the film. Because of the large flatband voltage shift for MgxScyOz, no further

studies are recommended for this dielectric.

Summary of Metallization Study for MgO

A metallization study was performed in which the feasibility of a new processing scheme

was evaluated regarding the deposition of ohmic contacts prior to oxide deposition. The new

processing scheme offers numerous advantages such as thorough cleaning of the GaN surface

prior to ohmic metal deposition, fewer processing steps the oxide has to undergo, and

simultaneous annealing of the ohmic contacts and in-situ cleaning of the GaN surface prior to

growth. A variety of surface pre-treatments were evaluated to determine their affect on the

ohmic contacts and their effectiveness at cleaning GaN with ohmic pads on the surface. The

surface pre-treatments included a 25 min UV-03 treatment, 25 min UV-03 and 10 min NH4OH

treatment, 25 min UV-03 and 1 min BOE treatment, and 25 min UV-03 and 10 min in-situ N2

plasma anneal at 7000C.

All four treatments yielded breakdown fields of -3.70 MV/cm or greater, Dit values around

2.0x101 eV- cm2, flatband voltage shifts of 0.63 V or less, and no damage to the ohmic pads on

the GaN surface. Given the small sampling set that was tested, further diodes should be









fabricated and tested to determine which pre-treatment provides the optimal surface to grow on

and to look for any observable trends as to which cleaning pre-treatment offers the best starting

surface to grow on. The concern of incorporating a new surface pre-treatment in place of the

standard pre-treatment was that it would not sufficiently clean the surface, which would result in

a higher Dit. All the surface pre-treatments had low Dit values that compared favorably with the

value from the standard pre-treatment. However, the values were calculated using the Terman

method whose accuracy depends on accurate knowledge of constants and values for the substrate

and oxide, graphical differentiation of the 4s-Vg curve, and substrate doping. Closer inspection

of the Dit values should be made by taking measurements with more accurate techniques such as

the ac conductance method or hi-lo method. Characterization with XPS should also be done to

determine the exact nature of the GaN surface following each treatment. An available nitride

MBE system that is currently having an XPS/UPS system installed will allow for in-situ

monitoring.

The values from the metallization study showed comparable electrical results to the

standard surface pre-treatment (3 min HCl:H20, 25 min UV-03, and 5 min BOE) that was used

in the old processing scheme in which oxide is deposited prior to ohmic metal deposition. These

results support the feasibility of the new processing scheme. Further studies should include the

optimized MgO growth conditions and incorporation of one of the surface pre-treatments in the

fabrication of an e-mode p-GaN MOSFET.

Summary of Electrical Results for MgO on p-GaN

Electrical data was obtained from MgO on p-GaN with the use of three different sample

pre-treatments. The three sample pre-treatments included a standard treatment (3 min HCl:H20

(1:1), 25 min UV-03, and 5 min BOE), a 25 min UV-03 and 1 min BOE treatment, and a 25 min









UV-03 treatment. The latter two treatments were sample pre-treatments that could be used if

ohmic metal was deposited prior to sample preparation and oxide deposition. All three samples

showed similar electrical results for the breakdown field, flatband voltage shift, and Dit. Since

the two surface pre-treatments that would be used with ohmic metal on the surface showed

comparable results to the standard surface pre-treatment, it appears that the deposition of ohmic

contacts prior to oxide deposition would be a feasible process on p-GaN.

Further analysis of MOS capacitors on p-GaN should be conducted on low doped material

to minimize the number of injected carriers, since the use of highly doped material typically

requires large gate biases to fully deplete the semiconductor surface of majority carriers.

However, a suitable ohmic contact must be found that will remain stable during the 7000C in-situ

anneal, and it must provide a low contact resistance to low doped p-GaN. The use of transition

metal borides, such as TiB2103 and W2B104, has gained recent attention in ohmic contacts on p-

GaN due to their excellent thermal stability and their ability to act as a diffusion barrier in the

Ni/Au contact. Reasonable contact resistances were obtained with these transition metal borides

at annealing temperatures over 8000C on p-GaN material with a doping density of lxl017 cm-3

Further studies should be conducted with p-GaN material having a doping density in the 1015 cm

3 range to determine if minimal contact resistances can be achieved with these transition metal

borides. The study should also include 7000C in-situ anneals in the MBE system to investigate

the thermal stability of the contact and the effect on the contact resistance.









APPENDIX A
PROCESSING INFORMATION AND DETAILS

Each processing step is critical to the success of the device and overall yield as unwanted

defects from a step could lead to premature failure of a device, or poor quality control of one step

could lead to problems with the next step. The following sections will include important

information related to microlithography as well as more detailed information for the processing

steps used in fabricating the MOS capacitors. The information given in the following sections

can be found in references 105-107.

Indium Removal

Before samples were processed to make diodes, indium (used in mounting the sample to

the molybdenum block) was removed from the backside of samples that were going to be

annealed in the RTA. This was to prevent indium from possibly contaminating the RTA

chamber during the anneal. The first step was to coat the front side (side with oxide) of the

sample with photoresist (PR). The sample was then placed in crystal bond on a glass slide

(crystal bond is applied to glass slide on a hot plate to create a viscous wax) with the backside of

the sample facing up. It is critical to make sure the hot plate is warm enough to melt the crystal

bond, but not too warm so that the PR is hard baked to the oxide surface. Once each edge of the

sample was covered by the crystal bond, the glass slide was removed and cooled with an N2 blow

gun. A cutip was then soaked with an HC1:H20 (1:3) solution and applied to the backside of the

sample. The combination of rubbing with a cutip and scraping with a razor removed indium

from the backside of the sample. After the indium was removed, the glass slide was placed back

on the hot plate to melt the crystal bond and allow for the removal of the sample. As soon as the

sample was removed, it was placed in acetone to lift off the PR and crystal bond. After the

acetone completely removed the PR and crystal bond, the sample was rinsed in isopropanol (15-









30 sec) followed by deionized (DI) water (15-30 sec). The sample was then dried with an N2

blow gun. Before resist was spun on the sample to be patterned, further cleaning of the sample

surface was required.

Surface Preparation

The primary reasons for cleaning the sample prior to coating it with resist are to enhance

the wetting and adhesion of the PR to the surface (critical for developing and etching) and to

avoid the formation of pinholes in the PR. The surface tension of the PR must be less than the

surface tension of the substrate for wetting to occur. The degree of wettability is given in

Equation A-1:

Ysv = Ysl + YivCOsO (A-l)

where Ysv (in dynes/cm) is the interfacial energy of the solid-vapor interface, Ysi (in dynes/cm) is

the interfacial energy of the solid-liquid interface, yiv (in dynes/cm) is the interfacial energy of

the liquid-vapor interface, and 0 is the contact angle. Generally, a contact angle less than 900

produces a wettable surface and a contact angle greater than 900 leads to a non-wettable surface

(Figure A-i). Although a low contact angle and high surface energy are desirable for wetting,

they also produce a hydrophilic surface that is attractive for adsorption of water. Water adsorbed

on the surface can lead to poor adhesion of PR to the underlying substrate which could cause lift

off during the etch process, undercutting at window edges, or complete loss of small features. In

cases of poor adhesion to the surface, the surface can be primed with a silane compound (ex.

hexamethyldisilazane-HMDS) which will lower the surface tension of the substrate to match the

surface tension of the resist and make the surface hydrophobic.

Typical contaminants that must be removed prior to resist coating include dust particles (in

any room or from cleaving sample), metal particles from metal lift-off, residual PR from









previous lithography processes, and solvent or water residue. The process that was used to clean

the surface of the samples included the following steps: 1) 3 min soak in acetone with ultrasonic

agitation 2) 3 min soak in methanol with ultrasonic agitation 3) 3 min soak in DI water with

ultrasonic agitation 4) Blow dry with N2 gun 5) 125 C bake on hot plate for 5 min to drive off

most of the adsorbed water 6) Cool sample with N2 blow gun. As soon as the cleaning process

was completed, PR was spun onto the sample as quickly as possible to minimize the amount of

time for water adsorption.

Photoresist

Shipley S1818 (positive resist which develops upon exposure to light) was used to coat all

of the samples. It was stored in a refrigerator to extend the life time of the resist as bacterial

growth can lead to aging of PR. Before samples were coated, a 20 mL amber bottle containing

1818 was wrapped up in aluminum foil (to prevent possible exposure to UV light) and given 30

minutes to come to room temperature. The final two numbers of the resist indicate the typical

thickness that can be spun, which in this case would be 1.8 |tm. The use of a thicker resist made

metal lift-off easier and reduced the number of pinholes. Although the resolution is lower for

thicker resists, it was not an issue in fabricating the MOS capacitors since the feature sizes were

so large. Since resist performance (ex. thickness, exposure time, develop time) can change as the

PR ages, quality control checks were performed every few months to look for any noticeable

changes.

Surface Coating

After receiving a thorough cleaning treatment, samples were placed on top of a small

opening in the vacuum chuck of the Laurell spinner. The opening allowed an applied vacuum to

draw the sample into intimate contact with the vacuum chuck. The desired program was then









selected on the keypad next to the spinner. The program contained two steps, with the first step

involving a low spin speed (1000 rpm) for dispensing the resist, and the second step involving a

higher spin speed (5000 rpm) to reach the desired thickness of the resist. The application of

dispensing the resist at a lower spin speed allowed the resist to spread across the sample before

stepping to the higher spin speed. It is critical to step to the final spin speed as soon as the resist

is dispensed, so that the amount of solvent evaporation (increased solvent evaporation produces a

thicker film of PR) is minimized.

A plastic syringe was used to dispense the resist to the spinning sample. Since the amount

of pressure used to dispense the resist is chosen depending on the resist viscosity and surface

energy of the sample, a higher pressure is typically used for low energy surfaces and/or high

viscosity resists. The higher pressure is used to provide the resist enough force to completely

wet the surface. After spinning the sample at 5000 RPM for 30 sec, the samples were removed

from the vacuum chuck for a soft bake. Profilometer measurements taken following the soft

bake (i.e., 125 C for 1.5-2.0 minutes) showed that a spin speed of 5000 rpm for 30 seconds

yielded a thickness of 2.0-2.2 |tm.

Factors Affecting Resist Thickness

The primary factors that affect the thickness of the resist are the viscosity of the PR and the

spin speed. As seen in Equation A-2, the thickness increases for slower spin speeds and higher

viscosities:


t = (A-2)


where t (in [tm) is the thickness of the resist, t (in cP) is the viscosity of the resist, t* (in seconds)

is the spreading time which is usually on the order of seconds, and co (in rpm) is the spin speed.

Figure A1-2 displays a spin speed curve for Shipley 1818 PR that was coated on Si at various









spin speeds (3000, 4000, 5000, and 6000 rpm) to determine the thickness of the resist. Other

factors that can influence the final resist thickness include humidity, atmospheric pressure,

temperature (resist, chuck, wafer, ambient environment, and soft bake), acceleration, and air

flow. Their affect on the resist thickness along with other factors mentioned earlier is shown in

Table A-1.

Acceleration

An acceleration rate of 1000-1500 rpm/sec was used in transitioning from the dispense

speed to the final spin speed. Further optimization of the acceleration rate is needed as it can

affect film uniformity and the number of spin-induced defects. Film uniformity generally

increases as acceleration is increased, but spin-induced defects are generated at high acceleration

rates (i.e., 20000 rpm/sec). High acceleration rates can produce a greater concentration of

atomized resist particles (can be minimized with a suitable exhaust) that can re-deposit on the

sample surface. Particles that re-deposit on the surface as a spherical shape are usually dry or

low in solvent and will block UV light. This creates an island of resist pattern where one should

not be present after development. Particles that re-deposit on the surface as half domes (also

known as color spots or fish eyes) are rich in solvent and will focus the UV light. This leads to

partial development and a crater shaped pattern defect. Since low acceleration rates can also

induce defects, there is a narrow operating range that must be found which will produce a resist

film of uniform thickness and low defect concentration.

Spin Defects and Artifacts

Although acceleration is the main spin defect contributor, other factors can produce defects

as well. Some of the factors include surface or resist contamination, air bubbles in the dispensed

resist, and very high spin speeds (aerosol particles are generated if a wafer is spun too fast).

Contaminants on the surface and particles or air in the resist are common sources of pinholes.









Pinholes pose serious problems as unwanted etching or metal deposition (in later processing

steps) can occur through tiny holes in the resist. Some of the methods to reduce the pinhole

density include using a thick resist, using a double coat resist process (rely on mismatch of

pinholes in each layer), and thorough cleaning of the sample surface.

Striations (radial stripes) or colored bands in the resist are indicative of thickness variations

that are primarily due to non-uniform drying of the solvent during the final spin step. Therefore,

the spin time must be chosen carefully to allow the solvent concentration enough time to

decrease uniformly across the sample. Surface contamination can also cause striations to form

due to poor wetting and adhesion. For thick coatings (>2 [tm), a recommended technique to

reduce the striations includes allowing the resist to sit on the surface for a set time before

spinning (ex. 15 seconds for 2 |tm thick resist). This technique was not used for any of the

sample coatings, but it should be studied in future processing optimization analyses. Another

method that can be used to minimize the striations is to make sure the resist is dispensed at the

center of the sample and not at multiple locations.

Since the radial velocity is greatest at the edge of the sample, the solvent evaporates there

more quickly, producing a thicker amount of resist at the edges. This residual ridge in the resist

is known as the edge bead. A recommended method to remove the edge bead is to use an EBR

(edge bead removal) solvent that partially dissolves the edge bead away after being spun onto the

sample following resist coating. However, this method was not used so that the number of

processing steps could be minimized. Any effects the edge bead could have on the exposure or

developer times was removed by making sure that only the center of the sample (where the resist

thickness was more uniform) was exposed to the pattern. All other types of spin defects and

artifacts are included in Table A-2.









Soft Bake

Although the spin coating removes the majority of the solvent (80-90%) from the resist, a

soft bake is required to evaporate the residual spinning solvent and densify the resist. If the

excess solvent is not removed from the resist, it can make the required exposure dose for pattern

transfer unpredictable. Incomplete removal of solvent can also leave the resist tacky, making the

sample stick to the mask during pattern alignment and making it more susceptible to particulate

contamination. Besides its use to primarily drive out the remaining solvent from the resist film,

the soft bake is used for removing internal stresses in the resist, closing voids and/or pinholes,

and enhancing the adhesion between the sample surface and resist.

The soft bake step was performed using a Thermolyne hot plate. A hot plate was used

since convection ovens can lead to trapping of the solvent in the resist. Entrapped solvent can

then form micro bubbles that become pinholes (popped bubbles) during further drying of the PR.

Using a hot plate allowed the solvent to outgas before the surface of the resist hardened.

Finding the suitable soft bake temperature and time is critical in determining reproducible

exposure and develop times. If the soft bake temperature is too high, the photosensitive

component may become partially degraded, requiring a higher exposure dose or longer exposure

time. A high soft bake temperature with a short bake time can also lead to the formation of

pinholes as the solvent is not given sufficient time to outgas. If the soft bake temperature is too

low, the remaining solvent may interfere with the radiation chemistry and development rates

(exposed and unexposed areas will dissolve equally), requiring different exposure-development

combinations. It is also critical to find soft bake conditions that provide reproducible dissolution

rates for the exposed and unexposed regions of the resist. After performing numerous processing









optimization experiments, it was found that a soft bake temperature of 125 C for a time of 1.5-2

minutes produced the most reproducible exposure and development times.

Exposure

After receiving a soft bake, each sample was placed on a 2" Si alignment wafer (held in

place by vacuum) which was inserted on top of the sample stage of the mask aligner. Channel 1,

corresponding to 365 nm wavelength light, was selected on the constant intensity controller. The

exposure dose (in mW/cm2) of the aligner was fixed, so only the exposure time could be varied.

The exposure time was initially calibrated by using samples of as-received Si and GaN. The

calibrated exposure time was then checked and finalized by using a GaN sample with MBE

deposited oxide (each oxide is calibrated). Since different surfaces reflect different fractions of

light, the oxide on GaN sample provided the most ideal case for the exposure.

The reflected light at the substrate/resist interface can interfere with the transmitted light

from the optical source of the mask aligner to form standing waves. Standing waves produce

two undesirable effects with the first one being undesirable horizontal ridges (reflective

notching) in the resist sidewalls that correspond to peaks and troughs in the standing wave

intensity. The second effect is that standing waves affect the total amount of light captured by

the resist. Since the amount of light absorbed by the resist changes dramatically with a slight

change in resist thickness, the exposure dose or time is highly sensitive to changes in resist

thickness. This results in a swing curve which is a sinusoidal variation of the exposure dose (Eo)

for varying resist thicknesses. The curves are generated by interference between incoming and

outgoing light waves due to a phase difference between them. The swing between the maximum

(where destructive interference occurs) and minimum (where constructive interference occurs)









points on the curve is represented by a thickness change of k/4n, where X is the exposure

wavelength (in nm) and n is the index of refraction of the resist.

There are multiple methods that can be used to reduce the effects of standing waves. One

of the methods includes a post exposure bake to reduce or eliminate the horizontal ridges in the

resist sidewalls created by the standing waves. However, a post exposure bake will not work to

reduce the swing curves. Dyed resists or antireflective coatings (ARC) are recommended for

reducing swing curves. Dyed resists utilize a higher optical density to suppress the reflection of

light, but too much opacity can reduce the exposure at the bottom of the resist. An ARC is a thin

layer of opaque organic material or heavily dyed polymer that is coated on the substrate surface

underneath the resist layer. The ARC has a high enough optical absorption to separate the resist

from the optical behavior of the substrate by absorbing the reflected light. To avoid adding any

complexity to the fabrication process, none of these methods were used to process the samples.

Instead of reducing the standing waves, a maximum point on the swing curve was targeted to

counter any changes in the resist thickness and prevent any occurrences of underexposure, which

can lead to scumming of the resist.

Development

Rohm and Haas MF 319 developer or AZ 300 MIF developer (both are metal-ion free)

were used to develop the exposed samples. The develop time is a strong function of the

exposure dose or time, so any exposure changes will lead to changes in the development time.

The development time was generally 30-60 seconds. The amount of time was determined by

monitoring the dissolution of the resist in the solution. As the resist was dissolving, a dark cloud

would form above the sample. Agitation was used to increase the development rate (kinetics of

development are mass transport limited) and remove the dissolved resist (dark cloud) away from









the sample since resist can re-deposit in the features under static development. Once the dark

cloud dissipated, the sample was removed from the solution, rinsed in water, and then dried with

an N2 blow gun. The developed features on the sample were then analyzed under a microscope

with filtered light to look for any features that had not fully developed.

The profiles of the features are heavily dependent on the combination of the exposure and

develop times. Overcut profiles are indicative of overexposure due to reflected exposure rays,

and undercut profiles are indicative of overdevelopment due to partial removal of unexposed

resist (Figure A-3). The development rate depends on the soft bake conditions, developer

temperature, solution agitation, and concentration or type of developer. Causes of insufficient

development include use of a high soft bake temperature, weakened developer solution, incorrect

exposure dose or time, or incorrect development time.

Hard Bake

Following development of the patterned sample, it can be given a hard bake to remove the

developer, moisture, and any remaining solvent (complete removal of casting solvent can only be

accomplished by baking the resist above its Tg). This helps to improve the adhesion of the resist

to the substrate for further processing steps such as wet or dry etching. Determining what hard

bake conditions to use depends on factors such as the resist thickness, exposure dose, type of

resist and developer, etchant and conditions, image profile, and subsequent processing steps (PR

removal, volatility, temperature). Since longer and hotter hard bake conditions can make

residual PR difficult to remove, a hard bake of 1100C for 60 sec on a Thermolyne hot plate was

used. Samples were not given a hard bake when the next processing step was metallization (i.e.

metal sputtering) since a soft resist was desired for metal lift-off.









Table A-1. Change in resist thickness for a given parameter.
Parameter Resist Thickness Reason
RPM increases Decreases Centrifugal force thins the resist as more
resist is spun off the substrate
Viscosity increases Increases Less resist is spun off the substrate due to its
slower molecular movement, and there is a
lower concentration of solvent to evaporate
Resist temperature Increases Rate of solvent evaporation increases with
increases an increase in temperature
Humidity increases Decreases Amount of solvent evaporation decreases
due to a lower exchange of spinning
solvent molecules in an environment
abundant with H20
Airflow increases Increases Rate of solvent evaporation increases
Atmospheric (barometric) Increases Greater solvent volatility at lower pressures
pressure decreases accelerates the rate of evaporation
Acceleration increases Decreases Centrifugal force thins the resist as more
resist is spun off the substrate
Soft bake temperature Increases Rate of solvent evaporation increases
increases









Table A-2. Causes of spin-induced defects or artifacts.
Spin Defect or Artifact Cause
Cloudy film Excess moisture
Comets Bubbles or particles from resist dispense
Swirls Volatile solvent
Pinholes Surface contamination; air or particles in resist
Striations Surface contamination; non-uniform solvent drying; dispense at
multiple locations










YIv
Contact angle (0)
/ liquid


contact angle (0)
Ylv


Figure A-1. Diagrams of wetting vs. contact angle. A) Wetting occurs for low contact angle (0).
B) Non-wetting occurs for high contact angle (0).












2.9-


2.8-


2.7-


2.6-


2.5-


2.4-


2.3-


2.2-


300 350 400 450
3000 3500 4000 4500


500
5000


5500 6000


Spin Speed (RPM)

Figure A-2. Resist thickness vs. spin speed for Shipley 1818 PR.


U^^


Z. I


-4











Resist


Resist


Resist Resist






B

Figure A-3. Sidewall profiles of photoresist features. A) Undercut profile from overexposure. B)
Overcut profile from overdevelopment.









APPENDIX B
CV CURVES AND MEASUREMENTS

CV Curves

The measured capacitance of a MOS capacitor consists of two capacitors in series. The

two capacitors include a voltage-independent gate oxide capacitor and a voltage-dependent

semiconductor capacitor. In accumulation, the series capacitance is represented by the oxide

capacitance shown in Equation B-l:


C O = (B-1)
ox

where Cox is the capacitor of the oxide (measured in F/cm2), ;ox is the dielectric constant of the

oxide, So is the permittivity of free space (8.854x10-14 F/cm), and tox is the thickness of the oxide

film (measured in cm).

In depletion, the semiconductor surface becomes depleted of majority carriers under the

applied gate bias (holes are depleted in p-type material with increasing gate voltage and electrons

are depleted in n-type material with decreasing gate voltage), causing a decrease in the measured

capacitance. The overall capacitance is now represented by the series connection of the oxide

capacitance (Cox) and depletion layer capacitance (Cd) seen in Equation B-2:

1 1 1
S + (B-2)
C Cox Cd

Under strong inversion, minority carriers are generated in the bulk and then drift across the

depletion region to form a surface layer of charge. However, this will only occur if a low (-1-

100 Hz) frequency is applied and if the gate bias is changed slowly. The low frequency and slow

changing gate bias allow the minority carriers enough time to respond to the ac probe frequency









and dc voltage signal. The overall capacitance is now represented by the oxide capacitance once

again (Figure B-la).

For high (-1 MHz) frequency measurements at slow changing gate biases, the minority

carrier generation rate is too low as the minority carriers do not have enough time to respond to

the ac voltage signal. The semiconductor depletion layer capacitance is now at a minimum,

corresponding to a maximum depletion width. The overall measured capacitance is also at a

minimum and is represented by the series capacitance of the oxide and semiconductor depletion

layer (Figures B-lb and B-2). For high or low frequency measurements at a large gate bias

sweep rate, the generation rate of minority carriers is too low and the measured capacitance can

go into deep depletion (Figure B-lc).

Dit Calculations

The frequency and gate bias sweep rate can have a significant effect on the response of

interface states at the oxide/semiconductor interface. As the applied gate bias changes, the

surface potential of the MOS device changes, which causes the interface states (whose positions

with respect to the band edges are fixed) in the bandgap to move above or below the Fermi level.

Since energy levels below the Fermi level have a higher probability of occupying an electron, an

interface state moving above the Fermi level would likely give up a trapped electron (or

equivalently capture a hole) while an interface state moving below the Fermi level would likely

capture an electron (or give up a hole). The stored charge from the interface states gives rise to a

capacitance which is in series with the depletion layer capacitor (the combination of the two

would be in series with the oxide capacitance). At very high (-1 MHz) frequencies, the interface

states do not have time to respond. At low (-1-100 Hz) frequencies and/or low gate bias sweep

rates, the interface states can respond quickly to the voltage changes and follow the ac probe

frequency.









The Terman method was used to calculate the Dit value from the measured CV data. The

method relies on measurements taken at sufficiently high frequencies in which interface traps do

not respond. Although the interface traps do not respond to the ac probe frequency, they do

respond to slow gate bias sweep rates. As the interface trap occupancy changes with gate bias,

the CV curve stretches out along the gate axis (change in slope of real CV curve from ideal curve

in Figure B-3 indicates the presence of interface traps). To determine the Dit, a theoretical CV

curve must be constructed and compared to the experimental curve.

The total theoretical capacitance is given by the series capacitance of the oxide and

semiconductor. To calculate the theoretical semiconductor capacitance (Cs), the semiconductor

flatband capacitance (CFBS) is calculated from Equation B-3:


CFBS o (B-3)
LD

where CFBS is the semiconductor flatband capacitance (in F/cm2), Ss is the dielectric constant of

GaN (5.3 at high frequencies), So is the permittivity of free space (8.854x10-14 F/cm), and LD is

the Debye length (in cm). The Debye length is calculated from Equation B-4:

k TE, E,
LD ~ qN (B-4)
q2N

where LD is the Debye length (in cm), kB is Boltzmann's constant (1.38x10-23 J/k), T is the

temperature (in K), Ss is the dielectric constant of GaN (5.3 at high frequencies), So is the

permittivity of free space (8.854x10-14 F/cm), q is the hole or electron charge (1.6x10-19 C), and

N is the effective carrier density (in cm-3). The effective carrier density can be calculated from

Equation B-5:


N = 2 1 1 (B-5)
qE,E,A2 O(l/C2)/8V









where N is the effective carrier density (in cm-3), Ss is the dielectric constant of GaN (5.3 at high

frequencies), So is the permittivity of free space (8.854x10-14 F/cm), q is the hole or electron

charge (1.6x10-19 C), A is the area of metal gate (in cm), and a (1/C2)/0 V is the slope of the

experimental 1/C2 vs. Vg plot.

After calculating the flatband capacitance of the semiconductor, the theoretical

semiconductor capacitance can be calculated from Equation B-6:108

C, = 2-05Sgn(V)CFB(eV )[- (V + 1) + ev (B-6)

where Cs is the semiconductor capacitance in (F/cm2); V is the non-dimensional band bending

(in V); Sgn(V) returns a value of 1 for positive values of V, 0 for a value of 0 for V, and -1 for

negative values of V; and CFBS is semiconductor flatband capacitance (in F/cm2). The non-

dimensional band bending is used in Equation B-7 to calculate the surface potential:

=kVT (B-7)
q

where ,s is the surface potential (in eV), kB is Boltzmann's constant (8.62x10-5 eV/K), V is the

non-dimensional band bending (in V), T is the temperature (in K), and q is the hole or electron

charge (1.6x10-19 C).

After constructing the theoretical curve by plotting the theoretical total capacitance vs. the

surface potential, a surface potential value is found for a given capacitance value. The gate

voltage from the experimental curve is then found for the same capacitance value. Repeating the

procedure for other points allows an 4s vs. Vg curve to be constructed. The Dit can be determined

from this curve using Equation B-8:


D= ox V 1 (B-8)
q 0, ] q









where Dit is the interface state density (in eV- cm-2), Cox is the oxide capacitance (in F/m2), q is

the hole or electron charge (1.6x10-19 C), VG is the gate bias (in V), 4s is the surface potential (in

eV), and Cs is the surface capacitance (in F/m2).

VFB Determination

For an ideal MOS capacitor, the metal and semiconductor work functions are equal at a

gate bias of 0 V. However, in a real MOS capacitor, there is typically a metal-semiconductor

work function (Dms) difference and oxide and interface charges that produce a flatband voltage

(VFB) shift (parallel shift of real plot from ideal plot is seen in Figure B-3). The flatband voltage

is the voltage required to achieve the flat band condition where the energy bands are flat. A

negative flatband voltage shift indicates a positive oxide charge that induces an equivalent

negative charge in the semiconductor. A positive flatband voltage shift indicates a negative

oxide charge that induces an equivalent positive charge in the semiconductor.

To determine the flatband voltage shift, the theoretical CV curve must be compared to the

experimental CV curve. The first step is to locate the normalized theoretical capacitance (C/Cox)

at a gate bias of 0 V. The same value is then located on the normalized experimental capacitance

curve with the corresponding gate bias value. This gate bias value represents the flatband

voltage of the MOS capacitor. Another method that can be used to determine the flatband

voltage shift experimentally includes plotting (1/Chf)2 VS. VG-89 The gate bias at the lower knee

of the curve represents the flatband voltage.



















ui0.6


0.4 C
I

0.2-
SEMICONDUCTOR
BREAKDOWN

V--- 0 Vmin VT -+V
V(VOLTS)

Figure B-1. MOS capacitance-voltage curves for a p-type semiconductor. A) Low frequency.
B) High frequency. C) Deep depletion. [Reprinted with permission from B.P. Gila,
2000. Growth and Characterization of Dielectric Materials for Wide Bandgap
Semiconductors. PhD dissertation (pg. 129, Figure A1-2). University of Florida,
Gainesville, Florida.]










ct


Accumulation

-I- linulato-


Depletion
C/-
-| insulator
T CsastIrate





V /


Inversion
C-nsulator
Cs State, (min)


Figure B-2. High frequency CV measurement for an ideal MOS capacitor. [Reprinted with
permission from B.P. Gila, 2000. Growth and Characterization of Dielectric
Materials for Wide Bandgap Semiconductors. PhD dissertation (pg. 131, Figure Al-
4). University of Florida, Gainesville, Florida.]
















Ideal


Real


0 V


Figure B-3. Illustration of ideal and real CV plots. Shift in real curve indicates flatband voltage
shift, and change in slope of real curve indicates interface traps. [Reprinted with
permission from B.P. Gila, 2000. Growth and Characterization of Dielectric
Materials for Wide Bandgap Semiconductors. PhD dissertation (pg. 132, Figure Al-
5). University of Florida, Gainesville, Florida.]









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BIOGRAPHICAL SKETCH

Mark Steven Hlad was born in Great Falls, Montana, and moved to Lynn Haven, Florida,

after only a few months old. He is the son of Dennis and Jan Hlad and brother to Paul Hlad.

After graduating from Mosley High School in 1998, he attended Gulf Coast Community College

for a couple years before attending the University of Florida in 2000. He received his bachelor's

degree in chemical engineering in 2003 and had the opportunity during that time to perform

undergraduate research studies with Dr. Omar Bchir on WNx thin films as diffusion barriers for

copper metallization. He then began to pursue a doctoral degree in materials science and

engineering in the summer of 2003 under Dr. Cammy Abernathy with research on gate

dielectrics (grown by MBE) on GaN MOSFETs. He completed his philosophy of doctorate in

the summer of 2007 in materials science and engineering. Post graduation plans include ajob as

a packaging engineer with Intel Corporation in Chandler, Arizona.





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1 OPTIMIZATION STABILITY OF GATE DIELECTRICS ON GALLIUM NITRIDE By MARK STEVEN HLAD A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2007

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2 2007 Mark Steven Hlad

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3 To my family and friends

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4 ACKNOWLEDGMENTS I want to praise God for giving me the opportu nity to receive a Ph.D. and work with and learn from such great professors and students. Gods grace is truly sufficient for me as He has provided me the strength when I am weak and the encouragement to press onward under any set of circumstances. I would also like to thank Dr. Abernathy for welcoming me into her group and helping me to broaden my knowledge of electro nic materials (especially when it involved thermodynamics and kinetics). I cant give enough thanks to Dr. Gila. He constantly challenged me, and he took the time to explain crucial concep ts and give instruction on how to use certain tools (i.e. Rusty). More importantly, he provi ded a valuable friendshi p. The flag football practices and games were a lot of fun, and he was always willing to talk about anything (especially gator football). I want to give thanks to Dr. Lin, Dr. Norton, and Dr. Pearton for making themselves available to answer my questions and for helping me to understand important concepts. Thanks to Dr. Lambers for allowing me to use the AES and XPS instruments. He provided enjoyable discussions and helped me with my thin film characterization. I want to thank Andy Gerger for performing SEM and AF M characterization and some of the MBE growths. I also want to thank many of the friends that I have met during my time at the University of Florida. My friends in Campus Crusade for Ch rist have given me cons tant encouragement and have challenged me to grow in Christ. My community group on Tuesday nights has provided both fellowship and accountability. I want to give thanks to my boys in the gym, Rob Humkey and Alex Tamayo. They made the workouts toug h and they were even better friends to hang with at the football games and other events. Thanks should also go to Peter Zawaneh and Michael Nash, who have been good friends to lean on when my research work was not working and I was completely frustrated. The last friend that I would like to thank is Dr. Omar Bchir. He

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5 is one of the brightest individuals I have ever met, and he inspired me to go to graduate school. I was fortunate enough to work with him at Intel for 6 months, and I have learned a great deal from him. Finally, I would like to give than ks to all of my family memb ers. Their constant prayers were an encouragement and provided me the strengt h I needed to finish. My brother has been a role model to me my whole life, and he has inspired me to work hard and grow in Christ. One of his comments to a friend said it best as he commented Mark doe s everything that I do, but he does it better. I want to give a special thanks to my mom and dad. They have provided me so much love and support. I am trul y blessed as they have sacrificed time and individual gain so that I could be successful.

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6 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................4 LIST OF TABLES................................................................................................................. ..........9 LIST OF FIGURES................................................................................................................ .......10 ABSTRACT....................................................................................................................... ............15 CHAPTER 1 INTRODUCTION..................................................................................................................17 Motivation..................................................................................................................... ..........17 Dissertation Outline........................................................................................................... .....18 2 BACKGROUND AND LI TERATURE REVIEW................................................................20 Introduction to MOSFET Device...........................................................................................20 Basic Operation of e-mode n-channel MOSFET............................................................21 Ideal and Real MOS Capacitors......................................................................................22 Properties and Characteristics of Dielectric Materials....................................................23 Current Collapse and RF Dispersion...............................................................................24 Crystalline Dielectrics on GaN...............................................................................................26 Gadolinium Oxide...........................................................................................................27 Scandium Oxide..............................................................................................................28 Magnesium Oxide...........................................................................................................30 Magnesium Calcium Oxide.............................................................................................32 Gallium Gadolinium Oxide.............................................................................................34 Amorphous Dielectrics on GaN..............................................................................................35 Silicon Nitride................................................................................................................ .35 Silicon Dioxide................................................................................................................36 GaN Surface Cleaning........................................................................................................... .37 UV-O3 Cleaning..............................................................................................................38 In-situ Cleaning...............................................................................................................38 Ex-situ Cleaning..............................................................................................................39 3 EXPERIMENTAL APPROACH...........................................................................................50 Molecular Beam Epitaxy........................................................................................................50 Substrate Preparation.......................................................................................................52 Silicon.......................................................................................................................52 Gallium nitride.........................................................................................................53 Scandium Gallium Oxide Growth...................................................................................54 Magnesium Oxide Growth..............................................................................................54

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7 Magnesium Scandium Oxide Growth.............................................................................55 Start Up..........................................................................................................................55 MOS Capacitor Fabrication....................................................................................................56 Photolithography.............................................................................................................56 Etching........................................................................................................................ .....57 Metallization.................................................................................................................. ..59 Annealing...................................................................................................................... ..60 Materials Characterization..................................................................................................... .61 Scanning Electron Microscopy (SEM)............................................................................61 Atomic Force Microscopy (AFM)...................................................................................62 Reflective High Energy Elect ron Diffraction (RHEED).................................................63 Ellipsometry................................................................................................................... .64 Transmission Electron Microscopy (TEM).....................................................................64 X-Ray Diffraction (XRD)................................................................................................65 X-Ray Photoelectron Spectroscopy (XPS)......................................................................65 Auger Electron Spectroscopy (AES)...............................................................................67 Current-Voltage (I-V) Measurements.............................................................................67 Capacitance-Voltage (C-V) Measurements.....................................................................68 4 GROWTH AND CHARACTERIZATION OF SCANDIUM GALLIUM OXIDE..............86 Continuous Growth of (Sc2O3)x(Ga2O3)1-x.............................................................................87 Digital Growth of (Sc2O3)x(Ga2O3)1-x.....................................................................................88 Growth with Closure of Ga Shutter........................................................................................89 Electrical Testing of (Sc2O3)x(Ga2O3)1-x.................................................................................90 5 OPTIMIZATION OF MAGNESIUM OXDE......................................................................115 MgO Growth at Low Growth Rates and Oxygen Pressures.................................................115 Results of MgxScyOz.............................................................................................................116 6 METALLIZATION STUDY WITH MAGNESIUM OXIDE.............................................133 Metallization Study on u-GaN..............................................................................................135 Electrical Results on p-GaN.................................................................................................138 7 SUMMARY AND FUTURE WORK..................................................................................161 Summary of (Sc2O3)x(Ga2O3)1-x on GaN..............................................................................161 Summary of MgO Growth Optimization..............................................................................162 Summary of Electrical Results for MgxScyOz......................................................................163 Summary of Metallization Study for MgO...........................................................................164 Summary of Electrical Results for MgO on p-GaN.............................................................165 APPENDIX A PROCESSING INFORMATION AND DETAILS..............................................................167

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8 Indium Removal................................................................................................................. ..167 Surface Preparation............................................................................................................ ...168 Photoresist.................................................................................................................... .........169 Surface Coating................................................................................................................ ....169 Factors Affecting Resist Thickness...............................................................................170 Acceleration...................................................................................................................171 Spin Defects and Artifacts.............................................................................................171 Soft Bake...................................................................................................................... ........173 Exposure....................................................................................................................... ........174 Development.................................................................................................................... .....175 Hard Bake...................................................................................................................... .......176 B CV CURVES AND MEASUREMENTS.............................................................................182 CV Curves...................................................................................................................... ......182 Dit Calculations.................................................................................................................. ...183 VFB Determination................................................................................................................186 LIST OF REFERENCES.............................................................................................................190 BIOGRAPHICAL SKETCH.......................................................................................................198

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9 LIST OF TABLES Table page 2-1 Properties of previ ously used dielectrics...........................................................................41 4-1 Auger peak-to-peak ratios for Ga:O, Sc :O, and Sc:Ga as function of the amount of time that the Ga shutter was closed towards the end of the growth...................................92 4-2 Characteristic binding energies of possible phases present in (Sc2O3)x(Ga2O3)1-x............93 4-3 Breakdown voltage as a function of decreasing Ga cell temperature................................94 5-1 Breakdown field values (at 1 mA/cm2) of tested diodes before and after various wet processing treatments.......................................................................................................120 5-2 Electrical results for MgxScyOz films on GaN for increasing Sc cell temperatures........121 6-1 Electrical results for MgO films on uGaN with various surface pre-treatments............141 A-1 Change in resist thic kness for a given parameter.............................................................177 A-2 Causes of spin-induced defects or artifacts......................................................................178

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10 LIST OF FIGURES Figure page 2-1 Cross-section illustration of a depletion mode n-MOSFET.............................................42 2-2 Cross-section illustration of an enhancement mode n-channel MOSFET........................43 2-3 E-mode n-channel MOSFET............................................................................................44 2-4 N-channel MOSFET......................................................................................................... 45 2-5 Energy band diagram for ideal p-type MOS capacitor at VG = 0.....................................46 2-6 Energy band diagrams for ideal na nd p-type MOS capacitors under an applied bias....47 2-7 Valence band and conduction band offsets with respect to GaN for previously researched dielectrics.........................................................................................................48 2-8 Auger peak-to-peak ratios for C:Ga, C:O, and Ga:O on GaN with UV-O3 treatments of 1, 3, 5, and 10 minutes...................................................................................................49 3-1 Illustration of a t ypical Knudsen effusion cell..................................................................70 3-2 Top view sketch of Riber 2300 MBE system used for oxide growth...............................71 3-3 AFM images showing pits at surface of as-received Uniroyal GaN................................72 3-4 AFM images showing MOCVD GaN grown by the Abernathy group............................73 3-5 RHEED images of pre-treated GaN surface.....................................................................74 3-6 RHEED photos of GaN surface showing a (1x3) pattern following an in-situ anneal at 700 C.............................................................................................................................75 3-7 Illustration of MOS capac itors that were fabricated.........................................................76 3-8 Diagram of pattern in the mask used to open windows for the ohmic pad.......................77 3-9 Diagram of pattern in the mask used to deposit ohmic pad..............................................78 3-10 Diagram of pattern in the mask used to deposit metal gate..............................................79 3-11 Sketches of bi-layer photoresist stack...............................................................................80 3-12 AES surface scans of as-received and etched (Sc2O3)x(Ga2O3)1-x films on GaN.............81

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11 3-13 Dry etching of (Sc2O3)x(Ga2O3)1-x on GaN and Si along with a reference piece of GaN in a CH4/H2/Ar chemistry..........................................................................................82 3-14 Etch selectivity of (Sc2O3)x(Ga2O3)1-x over GaN for a CH4/H2/Ar etch chemistry..........83 3-15 Possible RHEED patterns.................................................................................................84 3-16 An image of the penetration depth and interaction volume of an electron beam in a material....................................................................................................................... .......85 4-1 RHEED image of (Sc2O3)x(Ga2O3)1-x on GaN during and after growth...........................95 4-2 TEM SAD pattern of (Sc2O3)x(Ga2O3)1-x on GaN............................................................96 4-3 HRTEM image of (Sc2O3)x(Ga2O3)1-x on GaN.................................................................97 4-4 AFM images of (Sc2O3)x(Ga2O3)1-x on GaN for a continuous growth.............................98 4-5 AES analysis of continuous growth for (Sc2O3)x(Ga2O3)1-x on GaN................................99 4-6 Diagram of a digital growth technique in which the Sc and Ga s hutters are alternated for a given time sequence while the oxyge n shutter is open continuously throughout the entire growth.............................................................................................................. 100 4-7 AFM images of (Sc2O3)x(Ga2O3)1-x on GaN for a digital growth...................................101 4-8 AES analysis of digital growth for (Sc2O3)x(Ga2O3)1-x on GaN.....................................102 4-9 Diagram of growth technique in which the Ga shutter is closed towards the end of the growth for a designated amount of tim e while the Sc and O shutters are open continuously................................................................................................................... ..103 4-10 Change in Auger peak-topeak ratios as a function of the amount of time that the Ga shutter is closed toward s the end of growth.....................................................................104 4-11 AES analysis of growth with Ga shutter closure for (Sc2O3)x(Ga2O3)1-x on GaN..........105 4-12 AES depth profile of growth with Ga shutter closure for (Sc2O3)x(Ga2O3)1-x on Si.......106 4-13 Low magnification cros s-section TEM image of (Sc2O3)x(Ga2O3)1-x on GaN with a thin Sc2O3 layer at the GaN/oxide interface....................................................................107 4-14 High magnification cros s-section TEM image of (Sc2O3)x(Ga2O3)1-x on GaN with a thin Sc2O3 layer at the GaN/oxide interface....................................................................108 4-15 AFM images of (Sc2O3)x(Ga2O3)1-x on GaN for a growth with the Ga shutter closed towards the end................................................................................................................109 4-16 Current-voltage (I-V) plot of (Sc2O3)x(Ga2O3)1-x film deposited at 100 C....................110

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12 4-17 Ga LMM level shows a 6 eV difference between the Ga2O3 and Ga metal peaks.........111 4-18 Ga 2p3/2 level shows a 2 eV difference between the Ga2O3 and Ga metal peaks...........112 4-19 Ga 3d level shows a 2 eV difference between the Ga2O3 and Ga metal peaks...............113 4-20 Sc 2p3/2 level only shows the presence of a Sc2O3 phase................................................114 5-1 Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 1 minute DI water treatment................................................................................................................ .122 5-2 Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 3 minute treatment in developer......................................................................................................123 5-3 Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 10 minute treatment in PG remover..................................................................................................124 5-4 Current-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1090 C....125 5-5 Capacitance-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1090 C.............................................................................................................................126 5-6 Capacitance-voltage plot of two different scanning ranges for a MgxScyOz film on uGaN at a Sc cell temperature of 1090 C..........................................................................127 5-7 Current-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1135 C....128 5-8 Capacitance-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1135 C.............................................................................................................................129 5-9 Current-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1180 C....130 5-10 Capacitance-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1180 C.............................................................................................................................131 5-11 Normalized capacitance-voltage (C-V) plots of MgxScyOz films on GaN at Sc cell temperatures of 1090 C, 1135 C, and 1180 C................................................................132 6-1 Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-O3 surface pretreatment...................................................................................................................... ....142 6-2 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-O3 surface pre-treatment.................................................................................................................. ..143 6-3 Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-O3 and 10 min NH4OH surface pre-treatment..........................................................................................144

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13 6-4 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-O3 and 10 min NH4OH surface pre-treatment..................................................................................145 6-5 Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-O3 and 1 min BOE surface pre-treatment.......................................................................................................146 6-6 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-O3 and 1 min BOE surface pre-treatment..............................................................................................147 6-7 Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-O3 and 10 min insitu N2 plasma anneal at 700 C surface pre-treatment....................................................148 6-8 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-O3 and 10 min in-situ N2 plasma anneal at 700 C surface pre-treatment.........................................149 6-9 Current-voltage (I-V) plot for MgO on u-GaN with four different surface pretreatments..................................................................................................................... ....150 6-10 Capacitance-voltage (C-V) plot for MgO on u-GaN with four different surface pretreatments..................................................................................................................... ....151 6-11 Current-voltage (I-V) measurements for different ohmic metals on p-GaN..................152 6-12 Current-voltage (I-V) plot for MgO on p-GaN with a standard surface pre-treatment (3 min HCl:H2O (1:1), 25 min UV-O3, and 5 min BOE)................................................153 6-13 Capacitance-voltage (C-V) plot fo r MgO on p-GaN with a standard surface pretreatment (3 min HCl:H2O (1:1), 25 min UV-O3, and 5 min BOE)................................154 6-14 Current-voltage (I-V) plot for MgO on p-GaN with a 25 min UV-O3 and 1 min BOE surface pre-treatment.......................................................................................................155 6-15 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-O3 and 1 min BOE surface pre-treatment..............................................................................................156 6-16 Current-voltage (I-V) plot for MgO on p-GaN with a 25 min UV-O3 surface pretreatment...................................................................................................................... ....157 6-17 Capacitance-voltage (C-V) plot for MgO on p-GaN with a 25 min UV-O3 surface pre-treatment.................................................................................................................. ..158 6-18 Current-voltage (I-V) plot for MgO on p-GaN with three different surface pretreatments..................................................................................................................... ....159 6-19 Capacitance-voltage (C-V) plot for Mg O on p-GaN with three different surface pretreatments..................................................................................................................... ....160 A-1 Diagrams of wetting vs. contact angle............................................................................179

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14 A-2 Resist thickness vs. spin speed for Shipley 1818 PR......................................................180 A-5 Sidewall profiles of photoresist features.........................................................................181 B-1 MOS capacitance-voltage curv es for a p-type semiconductor.......................................187 B-2 High frequency CV measurement for an ideal MOS capacitor......................................188 B-3 Illustration of id eal and real CV plots.............................................................................189

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15 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy OPTIMIZATION STABILITY OF GATE DIELECTRICS ON GALLIUM NITRIDE By Mark Steven Hlad August 2007 Chair: Cammy Abernathy Major: Materials Science and Engineering The application of gallium nitride (GaN)-based devices requires the use of a gate dielectric to reduce gate leakage, passivate surface traps, and provide isolation between devices. It is critical for the insulator to remain chemically and thermally stable at high temperatures (i.e., 1000 C) during device fabricati on and operation. More impor tantly, it must possess good electrical characteristics such as a high breakdown field, low flatband voltage shift, and low interface trapped charge (Dit). A new dielectric material, known as scandium gallium oxide ((Sc2O3)x(Ga2O3)1-x), was investigated. Growth conditions of MgxScyOz and MgO were also optimized to enhance their environmental stab ility and improve their electrical results. All dielectric films were de posited by molecular beam epitaxy (MBE), which uses independent sources to precisely control the film thickness and stoichiometry. Initial films on GaN were characterized by using a wide variety of techniques to determine the crystal structure, surface roughness, chemical composition, and fi lm thickness. Electrical diodes were then fabricated for electrical testing such as curr ent-voltage and capacitance-voltage measurements. Continuous and digital growth techniques for (Sc2O3)x(Ga2O3)1-x revealed segregation of Ga at the surface. The segregation was eliminat ed by utilizing a growth technique in which the Ga shutter was closed for a set amount of time to wards the end of the growth while the O and Sc

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16 shutters remained open. A poor breakdown fi eld of 0.15 MV/cm was obtained due to the presence of free Ga metal in the film. Growth of MgxScyOz at low oxygen pressures showed breakdown fields as high as 4 MV/cm and Dit values in the low 1011 ev-1cm-2 range, but flatband voltage shift values ranging from 3.83-5.30 V were also obtained. The large flat band voltage shifts were attributed to defects generated from the mixed Sc (+3) and Mg (+2) valences. Optimization of MgO growth parameters at low oxygen pressures and low growth rates showed improved environmental st ability and good electrical resu lts on both u-GaN and p-GaN. The use of a new processing scheme in which th e ohmic metal is deposited prior to MgO showed good feasibility as it displayed comparable elec trical results to the old scheme involving MgO deposition prior to ohmic metallization.

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17 CHAPTER 1 INTRODUCTION Motivation The modern microelectronics industry is pr imarily based on silicon technology. As the demands for increased device speed rise, the se miconductor industry continues to decrease the size of transistors on integr ated circuits (ICs) and increase the number of transistors per chip to meet Moores law (number of transistors on ICs doubles every 18 months). Although great success has been achieved with silicon based de vices, silicon does have a couple limitations. Due to the low band gap (1.1 eV) of silicon, it cannot be used in devices operating under high temperature and/or high power regimes. It is also an indirect band gap semiconductor, which makes it an inefficient light emitter. B ecause of these limitations with silicon, much research has been devoted to compound semiconducto rs to find materials that have direct band gaps for efficient light emission and wide band gaps for high power, high temperature applications. Gallium nitride is a compound semiconduc tor that has both of these characteristics. The wide band gap (3.4 eV) of GaN allows it to be used in high power RF devices such as military radar and broadband communication links. Its direct band gap allows it to be used in photonic devices such as light emitting diodes (LEDs) laser diodes, and UV de tectors. It also has a low sensitivity to ionizing radiation, wh ich makes it suitable for satellite based communication networks. With all of the potential that GaN has, there is a need for a dielectric in certain GaN-based devices. AlGaN/GaN high electron mobility transi stors (HEMTs) typically experience current collapse and rf dispersion (discussed in Chapter 2), which is a decrease in the maximum current and an increase in the knee voltage due to surface and bulk traps. The application of a dielectric serves to passivate the surface traps, allowing a significant incr ease in the max current under rf

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18 conditions in which the gate bias is pulsed. A second desire for using a dielectric is to reduce leakage current from one device to another by isolating devices a nd interconnects (Mesa isolation). The dielectric can also be employed underneath the gate to re duce gate leakage into the semiconductor. This allows the fabricati on of a metal oxide (or insulator) semiconductor field effect transistor (MOSF ET) which can be made into a complementary device that is required for logic circuits. Dissertation Outline The objective of the study was to grow a novel gate dielectric with a high breakdown voltage so that it could be employed in a stack ed gate dielectric in an enhancement mode MOSFET. The study also included optimization of some previously used crystalline dielectrics to enhance the stability and electrical characteri stics of the films. The background and literature review is disc ussed in Chapter 2. It contains general information on MOSFETs, characteristics of a g ood dielectric, properties of previously used dielectrics, and a brief overview of rf dispersion and the current collapse effect. A thorough literature review is provided on previously used dielectric s on GaN and various cleaning techniques that have been used on GaN. Chapte r 3 discusses the experime ntal parameters that were used in growing the oxides as well as char acterization methods that were used to analyze the deposited thin films. All the major processing steps for the fabrication of MOS capacitors were also provided. Growth a nd characterization details of (Sc2O3)x(Ga2O3)1-x are discussed in Chapter 4. Information on different growth techniques and structural and chemical characterization are given. Chapter 4 also includes current-voltage (I-V) results for (Sc2O3)x(Ga2O3)1-x and the use of various growth conditi ons to find the optimal conditions that give the best electrical results. Growth optimization of MgO and addition of Sc to MgO to form MgxScyOz are discussed in Chapter 5. The study in cludes electrical char acterization of new

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19 growth conditions for MgO, and the feasibility of adding Sc to MgO to form a more stable oxide film. A metallization study on u-GaN and electrical results fo r MgO on p-GaN are provided in Chapter 6. The metallization study includes electri cal results for various surface treatments on samples with ohmic pads deposited on GaN prio r to oxide deposition. Chapter 7 includes final conclusions and recommendations for future experiments.

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20 CHAPTER 2 BACKGROUND AND LITERATURE REVIEW Introduction to MOSFET Device The basic circuit functions performed by th e metal oxide semiconductor field effect transistor (MOSFET) are current amplification and controlled switching of the device off and on. Its utilization of an insula ting layer (i.e. oxide) between the metal gate electrode and semiconductor layer provides isolation of devices and interconnects, insulation of the gate to reduce gate leakage, and passiva tion of surface states that in duce rf dispersion. The MOSFET device is tolerant of high temperatures and pr ovides better linearity (b roader transconductance vs. gate voltage) compared to a metal semic onductor field effect transistor (MESFET). The MOSFET is a three terminal device which uses a metal gate to control a conducting channel that electrons or holes (depending on the type of conduc ting channel) flow through from a metal source to a metal drain. The two t ypes of MOSFET devices are depletion mode (normally on) and enhancement mode (normally off). In the depletion mode MOSFET (Figure 2-1), the semiconductor material beneath the oxide is doped with the same type of material as the source and drain regions.1 A conducting channel is al ready present at a gate voltage of zero, so a gate voltage must be app lied to turn the device o ff. The depletion mode MOSFET is most commonly used as a resistor In the enhancement mode (e-mode) MOSFET (Figure 2-2), the semiconductor mate rial beneath the oxide is lightly doped to create a region of opposite type to the material under the source an d drain regions. A conducting channel is not present at a gate voltage of zero, so a gate voltage must be app lied to create a conducting channel and turn the device on. The e-mode MOSFET is most commonly used as a switch. An e-mode n-channel device will be used for further desc ription regarding the basic operation of a MOSFET.2

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21 Basic Operation of e-mode n-channel MOSFET An e-mode n-channel device has n+ source and drain regions that have been implanted or diffused into a lightly doped p-t ype substrate. At a gate volta ge of zero, there is no conducting nchannel between the n+ regions, so no current can flow from the drain to the source. This can be understood with the band diagram of the MO SFET (at equilibrium) in Figure 2-3a. At equilibrium, the Fermi level is flat and a potential barrier is present that prevents the flow of electrons from the source to the drain. As a pos itive bias is applied to the gate, the valence band moves away from the Fermi level and a depletio n region begins to form as holes underneath the gate oxide are repelled. A corre sponding negative charge (ionized acceptors) is induced in the ptype channel, and the barrier for electrons betw een the source, channel, and drain is reduced. Further reduction of the barrier will lead to the formation of a channel in which electrons flow from the source to the drain. The minimum gate voltage required to induce this channel is known as the threshold voltage (VT). Increasing the gate volta ge beyond the threshold voltage will induce more negative charges in the channe l (making it more conducting) as minority carrier electrons generated in the bulk will drift across the depletion layer to th e surface layer (inversion layer) of charge. Applying a drain bias initially increases the drain current line arly (Figure 2-3b). However, as more drain current flows in the channel, mo re ohmic voltage drop occurs along the channel, and eventually a drain bias is reached that ca uses the conducting channel to pinch-off and the drain current to saturate. Pinch-off will occur when the difference between the gate voltage and drain bias is equal to the thresh old voltage (Figure 2-4) Increasing the drain bias further will move the pinch-off point farther into the ch annel and closer to the source end. For GaN MOSFETs, the formation of a conduc ting channel is completely dependent upon an external source of inversion charge since the minority carrier generation rate is very low for

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22 GaN (the generation rate is too low at even higher temperatures of 300 C). The source of this charge consists of n+ regions in the source and drain create d by Si implantation and subsequent activation annealing. The applica tion of a gate bias is then us ed to draw electrons from the source and drain under the gate region to form a conducting channel. Ideal and Real MOS Capacitors The ideal MOS capacitor (Figure 2-5) has a fl atband condition where the energy difference between the metal work function ( m) and semiconductor work function ( s) is zero at an applied bias of zero. Under an applied bias, three distinct operation modes exist which are known as accumulation, depletion, and inversion (Figure 2-6).3 In accumulation, majority carriers accumulate at the surface of the semiconduc tor, forming a larger carrier concentration than the doping concentration in the bulk of the semiconductor. For a p-type semiconductor, the valence and conduction bands will bend up, and fo r an n-type semiconductor, the bands will bend down. In both cases, the intrinsic Fermi level (Ei) is farther away from the Fermi level (EF) of the semiconductor. In depletion, majority carriers are depleted near the semiconductor surface. The bands will bend down in p-type mate rial and will bend up in n-type material, with the bands bending far enough for Ei to equal EF at the surface. Under inversion, the bands bend down strongly enough in the ptype material so that Ei lies below EF at the surface, and the bands bend up strongly enough in the n-type material so that Ei lies above EF at the surface. Majority carriers at the surface of the semiconductor have been further depleted and minority carriers are collected at the surface. For a real MOS capacitor, a work function difference typically exists between the metal gate and semiconductor, along with various char ges in the oxide and at the oxide/semiconductor interface. The combination of th ese real effects induces a charge (positive or negative depending

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23 on the various oxide charges and metal-semiconduc tor work function difference) at the surface of the semiconductor and causes band bending to occur at equilibrium (Vg = 0). To eliminate the band bending and achieve a flat ba nd condition, a flatband voltage (VFB) in Equation 2-1 must be applied to account for these real effects: i i ms FBC Q V (2-1) where VFB is the flatband voltage (measured in volts), ms is the work function difference (measured in volts) between the work function of the metal ( m) and the work function of the semiconductor ( s), Qi includes the various oxide and interface charges (measured in C/cm2), and Ci is the capacitance of the insulator (measured in F/cm2). Properties and Characteristic s of Dielectric Materials For a material to be an effective dielectric, it needs to possess the following characteristics: chemical and thermal stability, a dielectric cons tant higher than the semiconductor, a wide band gap with confinement at both e dges, and a lattice constant and thermal expansion coefficient close to that of the underlying substrate. Large differences in the latti ce constants can create defects such as misfit dislocations in the underlying substrate that can serve as trapping centers. If the growth occurs at high temperatures, large differences in the thermal expansion coefficients can produce stress at the interf ace during cooling that will relie ve itself through the formation and propagation of dislocations. High ope rating temperatures with wide band gap semiconductor devices makes thermal stability an absolute necessity for the dielectric. In addition to needing a larger band gap than th e semiconductor, large valence band and conduction band offsets with respect to the semiconductor are hi ghly desirable. A higher dielectric constant than the semiconductor is needed to prevent the fo rmation of a high electric field in the dielectric that can lead to potentia l breakdown of the dielectric. Characte ristic values of previously used

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24 dielectric materials on GaN are shown in Table 2.14-6 and band offsets with respect to GaN are shown in Figure 2-7. Effectiveness of the dielectric can also be determined through analysis of the charges at the dielectric/semiconductor interface and in the diel ectric itself. Positive or negative charges trapped at the dielectric/semiconductor interf ace are known as interface trapped charge (or interface state density). The tra pped charge is due to structural defects (i.e. dislocations), dangling bonds, and impurities. The interface state density (Dit) should have a value less than or equal to 1011 eV-1cm-2 for a device to be successful. Charge s trapped in the first 2-3 monolayers of the dielectric due primarily to structural defects are known as fixed dielectric charge (Qf). Positive or negative charges in the bulk of the dielectric due to trapped holes or electrons are dielectric trapped charge (Qot). These charges can be injected in to the dielectric from the gate or semiconductor under large gate biases Mobile dielectric charge (Qm) is attributed to ionic impurities that can drift under an applied electric fi eld. It is critical to minimize the amount of charge in the insulator as trapped or mobile ch arges can cause shorting and effect the depletion of a semiconductor. The integrity of the oxide can be determin ed from current-voltage measurements by calculating the breakdown field of the oxide. The breakdown field (in MV/cm) provides a measure of how much gate voltage can be appl ied before the oxide breaks down and charges flow freely from the gate to the semiconductor. It is extremely important to limit the number of defects (such as dislocations a nd pinholes) and charges in the di electric as they can serve as electrical pathways that can lead to premature breakdown. Current Collapse and RF Dispersion Two phenomena that are known for limiting the el ectrical output (i.e. output power, drain current, etc.) of MESFET and HEMT devices in cludes RF dispersion and current collapse.

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25 Under RF dispersion, the output power and drain current at high frequencies are significantly lower than projected due to trapping states at the surface.7 In contrast, current collapse is a reduction in the drain current and distortion in the dc I-V charact eristics that occurs a under a large drain-source voltage due to trap s in the bulk of the material. Surface trapping has typically been identifie d through gate lag measurements where the drain current is measured while the gate is pulsed from pinch-off to a value where turn-on occurs.8,9 The surface traps are typica lly associated with dangling bonds, ions adsorbed from the atmosphere, and dislocation defects. Under a la rge negative gate bias, electrons are injected from the gate into surface states between the ga te and drain electrodes, which creates a virtual gate.10-12 The virtual gate depletes electrons fr om the conducting channel of a MESFET and the 2DEG of a HEMT, causing a redu ction in the output current.13 Applying a positive bias to the gate will not increase the drain current instantane ously because the change in the potential of the virtual gate is slow. To reduce the effect of rf dispersion, a dielectric can be deposited at the surface of the semiconductor to pa ssivate the surface trapping states. Including the dielectric underneath the gate metal to make a MOSFET or MOSHEMT device allows the dielectric to simultaneously passivate surface traps and reduce gate leakage. Buffer trapping has typically been identifie d through drain lag m easurements where the drain current is measured while th e drain-source voltage is pulsed.8 Another indicator of buffer trapping is when a shift in the threshold vol tage is observed betw een dc and pulsed I-V measurements.9 Traps in the buffer layer are typically associated with dislocation defects and vacancies. Under a large drai n-source bias, a high electric field builds up and accelerates electrons through the conducting ch annel of a MESFET or MOSFET and the 2DEG channel of a HEMT. At a high enough electric field, electrons have sufficient kinetic energy to overcome

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26 local potential barriers and are in jected (hot electron stress) into deep trapping centers in the GaN buffer layer or AlGaN layer (for a HEMT device).7,14,15 The trapped electr ons then lead to current collapse by extending the depletion region and reducing the sheet charge in a HEMT or the density of carriers in the MESFET or MOSF ET conducting channel. The effect of current collapse is an increase in the knee voltage and a decrease in the max drain current. The primary way to significantly reduce or eliminate current collapse is to optimize the growth conditions of the GaN buf fer layer and AlGaN layer (in a HEMT device) so that both layers are of high crystal quality with very fe w dislocation defects and vacancies. Illumination with light and elevated temperatures have al so shown success in reducing the current collapse effect.7,16,17 Temperatures as high as 155 C in GaN MESFETs completely eliminated the current collapse effect as electrons were thermally emitted from deep level traps. Drain characteristics measured at a gate bias of 0 V under a xenon lamp showed an increase in the drain current as the wavelength of light decreased. The increase in dr ain current with decreasing wavelength (720 to 360 nm) indicated a wide distributio n of trap levels instead of a single trap with a defined energy level. Further analysis of the deep level traps in a GaN MESFET by photoionization spectroscopy indicated that th e traps were located at 1.8 and 2.85 eV below the conduction band.17 Crystalline Dielectrics on GaN The following sections provide a summary on th e most important crystalline dielectrics that have been developed for use as gate oxide s on GaN. The general tr end shows that a lower Dit value is obtained as the lattice mismatch is reduced between the crystalline dielectric and GaN substrate. Oxide films grown at lower (i.e. 100 C) substrate temperatures have typically shown a greater breakdown voltage compared to films grown at higher substrate temperatures

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27 (i.e. 300 C or greater). All of the cr ystalline dielectrics discussed below were deposited by gas source molecular beam epitaxy (GSMBE). Gadolinium Oxide Gadolinium oxide (Gd2O3) films have been deposited by MBE as a gate dielectric in GaN MOSFETs.18-24 An elemental Gd source and ECR oxygen plasma source were used to deposit 70 nm thick films. Changes in the substrate temperature did not significantly change the deposition rate and O/Gd ratio. A Dit value of 3x1011 cm-2eV-1 (obtained from Terman method) and a breakdown field of ~3 MV/cm were m easured for a quasi-amorphous film grown at 100 C.18 However, the film showed poor thermal st ability as it re-crystal lized and produced a second phase after being annealed to 1000 C in N2 for 30 seconds. A single crystal film deposited at 650 C showed good thermal stab ility upon annealing to 1000 C in N2 for 30 seconds.19 The surface roughness of the annealed sample was 0.60 nm compared to a value of 0.56 nm for the as-grown sample. AES depth profiling also showed an abrupt oxide/nitride interface for the as-grown and annealed samples. A breakdown field of 0.3 MV/cm was measured for the fabricated Ga N device structure. TEM showed a high concentration of dislocations in the film that served as leakage paths and were responsible for the low breakdown field. The highly defective single crystal layer was a result of nanometer size voids in the GaN surface and the 20% lattice mismatch between Gd2O3 (111) and GaN (0001).19,20 To reduce the gate leakage and improve th e breakdown field of the device, amorphous SiO2 was deposited on top of Gd2O3.21,22 The stacked gate dielectric of SiO2 (30 nm)/Gd2O3 (70 nm) maintained the interfacial properties of Gd2O3/GaN while using the SiO2 layer to reduce current leakage by terminating the dislocations in the oxide laye r. The breakdown field of the

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28 device improved from 0.3 to 0.8 MV/cm, and modula tion was demonstrated up to a gate bias of 7 V. The reverse leakage current was meas ured at ~10 pA for a gate-source bias (VGS) of V, and it remained below 10 nA past VGS = -70 V. The main limitation of Gd2O3 is its large lattice mismatch with GaN. The larger band gaps and smaller lattice mismatch to GaN make MgO and Sc2O3 dielectric films more desirable to use than Gd2O3 films. Scandium Oxide Scandium oxide (Sc2O3) deposited by MBE is another dielectric that has recently been used in GaN MOSFETs24-28 and AlGaN/GaN HEMT4,28-39 devices. An elemental Sc source and RF oxygen plasma source have been used to depos it the films at substrate temperatures ranging from 100-600 C.28 Changes in the substrate temperat ure, Sc cell temperature, or oxygen pressure have shown no change in the Sc:O rati o. Breakdown fields as high as 3.3 MV/cm (80100 nm oxide film) and Dit values as low as 5x1011 eV-1cm-2 (calculated by Terman method) have been measured for GaN MOS capacitors.25,28 A significant flatband voltage shift has also been observed, indicating the pres ence of fixed oxide charge. N+ drain regions were used in a separate Sc2O3/p-GaN device to overcome the low minority carrier generation rate in GaN and provide a source of inversion charge.26 An AlGaN/GaN MOSHEMT was compared to a me tal-gate HEMT to observe the effect of Sc2O3 as a gate dielectric. The drain current reached a maximum value over 0.8 A/mm for the MOSHEMT and was ~40% higher compared to the conventional HEMT.36 The device was also modulated to a gate voltage of 6 V, and the threshold voltage sh ifted to more negative values (from ~-4 V to -5.5 V). Pulsed c onditions showed a 10% decrease in IDS relative to DC conditions indicating that the Sc2O3 dielectric (10 nm) effectively minimized the current collapse seen in unpassivated devices. Other Sc2O3 MOSHEMT devices have shown significantly better

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29 power-added efficiency (27%) relati ve to a conventional HEMT (5%).30 Scandium oxide passivated HEMTs have also shown effective suppression of surface states created by high energy proton irradiation (40 Me V protons at a fluence equivale nt to ~10 years in low-earth orbit), making them attractive candidates for spa ce and terrestrial applic ations experiencing high fluxes of ionizing radiation.31,37 Surface cleaning has played a vital role in ob taining improved electr ical characteristics with Sc2O3 passivation. A 25 min UV/O3 treatment, followed by heating at 300 C for 5 min, and then deposition of Sc2O3 (10 nm) at 100 C, provided a greater increase in fmax, fT, IDS, and gm compared to depositing Sc2O3 at 100 C without any surface pre-treatment.33 The only poor result from the pre-treatment wa s a slight increase in the reverse leakage current, which was attributed partially to thermal degradation of the gate contact. A cleaning temperature of 700 C would be ideal prior to oxide deposition for cleaning the surf ace more thoroughly, but any precleaning temperatures above 350 C deteriorates the gate metal of the HEMT.34 A major advantage with Sc2O3 compared to MgO is that it provides stable passivation over long periods of time. DC characteristics s howed no change in GaN-cap HEMT performance over a period greater than 5 mont hs for devices passivated with Sc2O3 while MgO passivated devices lost some of their effectiveness after 5 months.4,35 Comparison to a device passivated with PECVD SiNx showed that Sc2O3 was more effective in rest oring the drain current. Scandium oxide produced complete recove ry of the drain-source current, and SiNx provided only ~70-75% recovery.4 AlGaN/GaN HEMTs (0.5 x 100 m2) passivated with Sc2O3 led to a 3 dB increase in output power at 4 GHz comp ared to a 1.8 dB increase for PECVD SiNx.35 The main limitation with Sc2O3 is its 9% lattice mismatch with GaN. As stated previously, a larger lattice mismatch produces a greater number of defects wh ich can lead to a higher interface trap density.

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30 Magnesium Oxide Magnesium oxide (MgO) deposited by MBE has also been employed as a gate dielectric in GaN MOSFETs28,40-48 and AlGaN/GaN HEMT4,28,33-39 devices. An elemental Mg source and RF oxygen plasma source have been used to deposit the films at substrat e temperatures of 100 C.28 Cross-section TEM images show th at the first 4 nm of the deposite d film was single crystal, and then it became polycrystalline as the film ro tated. Changes in oxygen pressure have shown a significant impact on the growth rate, Mg/O rati o, morphology, and electrical characteristics of the MgO/GaN didoes.40 A Dit value of 3.4x1011 eV-1cm-2 (Terman method) and a breakdown field of 4.4 MV/cm (90 nm oxide film) were obtained at an oxygen pressure of 1x10-5 Torr compared to values of 1.8x1012 eV-1 cm-2 and 1.2 MV/cm at a pressure of 7x10-5 Torr. The fixed oxide charge was also shown to decrease with decreasing pressure. Th e low minority carrier generation rate in GaN has made inversion at ro om temperature difficult in GaN MOS devices. However, inversion was demonstrated in an Mg O/p-GaN MOS diode at ro om temperature in the dark when n+ regions were implanted in the device.41 The n+ regions served as the source of the minority carriers needed for inversion at room temperature. Other MgO films were grown at 350 C, but those films were extremely rough (rm s of 4.07 nm compared to 1.26 nm for MgO films at 100 C), had a low breakdown voltage, and were too leaky to obtain C-V results from.42 An AlGaN/GaN MOSHEMT was compared to a me tal-gate HEMT to observe the effect of MgO as a gate dielectric. The drain-sour ce current for the MOSHEMT was ~20% higher compared to the conventional HEMT.29 The pulsed drain current matched the DC drain current indicating that the MgO dielectric (10 nm) effectively eliminated the current collapse seen in unpassivated devices. Magnesium oxide passiv ated HEMTs have also shown effective suppression of surface states cr eated by high energy proton irradi ation (40 MeV protons at a

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31 fluence equivalent to ~10 years in low-earth orbit), making them attractive candidates for space and terrestrial applicatio ns experiencing high fluxes of ionizing radiation.37 A comparison between MgO and SiNx passivation films on GaN-capped HEMTs revealed that the MgO film was more effective in mitigating current collapse. The SiNx film produced ~70-75% recovery of the drain-source current wh ile the MgO film produced complete recovery of the current.4 Passivated AlGaN/GaN HEMTs (0.5x100 m2) with MgO led to a 3 dB increase in output power at 4 GHz compared to a 1.8 dB increase for PECVD SiNx.35 The role of cleaning prior to deposition of MgO passivation on AlGaN/GaN HEMTs has taken on great significan ce in optimizing the performance of the device.33,34 Deposition of MgO without prior in-situ or ex-situ tr eatment showed an increase in IDS, gm, fT, and fMAX, and a reduction in reverse leakage current compared to devices with no passivation or pre-treatment.33 A 25 min UV-O3 treatment, followed by heating at 300 C for 5 min, and then cooling to 100 C for deposition of MgO produced better dc and rf results than the deposit ed MgO films that did not receive any pre-treatment. Similarly to Sc2O3, the surface treatment and passivation did produce an increase in the gate leakage current. A major limitation of MgO is its poor environmental stability.43 It has been shown to deteriorate over time when left uncapped due to the reaction w ith water vapor in the ambient forming MgOH.35 To preserve the stability of MgO, a capping layer, such as Sc2O3 (5-10 nm), can be deposited on top of the MgO immediately following the MgO growth.34 Films grown at lower growth rates (~1 nm/min) have also s hown more stability as they have shown no deterioration after being exposed to air over a pe riod of months. The lower growth rate films have not appeared to etch in wate r in contrast to higher growth ra te films which generally etch in water within 10 seconds.

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32 An additional limitation of MgO is its poor thermal stability.43 Annealed (1000 C for 2 minutes) MgO/GaN diodes have shown significa nt roughening at the MgO/GaN interface, degradation of the oxide, and an or der of magnitude increase in the Dit. This presents severe processing issues as ohmic contacts typically require high annealing temperatures (i.e., 750 C for 30 seconds with n-GaN). It a ppears that changes in the proc essing sequence or the use of a Sc2O3 capping layer would be needed to pr event these deleterious effects. Magnesium Calcium Oxide The desire to decrease the lattice mismatch with GaN and improve the passivation effect of the dielectric has led to the development of MgCaO.49-51 The films have been deposited by MBE using Mg and Ca elemental sources and an RF oxygen plasma source. Both CaO and MgO have the same rocksalt crystal structure with simila r dielectric constants and bandgap energies. However, the (111) plane of MgO has a -6.5% lat tice mismatch to the GaN (0001) plane, and the (111) plane of CaO has a 6.8% la ttice mismatch to the GaN (0001) plane. Since Vegards law can be applied to systems with components that ha ve the same crystal stru cture, a 50-50 mixture of MgO and CaO should produce a lattice matched oxi de to GaN. This is highly desirable as previous results have shown a decreasing Dit value and greater passivat ion effect for crystalline oxides with decreasing lattice mismatch to GaN. Initial growths at substrate temperatures of 100 C and 300 C with all three (Mg, Ca, and O) shutte rs open simultaneously showed Ca and O segregation at the surface.49 To prevent this segregation fr om occurring, a digital growth at 300 C was employed which involved repeatedly alte ring the Mg and Ca shutter sequences at 10 sec intervals during continuous exposure from the oxygen plasma. An Auger depth profile showed a film of uniform composition, and XRD re sults showed no evidence of phase separation into either binary phase. A shoulder on the ri ght of the GaN (004) peak was observed in the

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33 XRD spectra, indicating the MgCaO (222) plane. Th e convenient aspect of the digital growth is that it allows the utilization of various shutter sequences so that the lattice constant of MgCaO can be finely tuned to that of GaN. This concept has been seen in passivation studies incorporating MgCaO as the dielectric. Two MgCaO films with different compositions (Mg0.5Ca0.5O and Mg0.25Ca0.75O) were compared to a MgO film regarding their effectiveness in passivating an AlGaN/GaN HEMT.50 Both of the MgCaO samples showed increases in the drain saturation current with a 4.5% increase for Mg0.5Ca0.5O and a 1% increase for Mg0.25Ca0.75O. The MgO sample showed a 10% decrease in the drain saturation current which wa s attributed to strain applied on the nitride HEMT by the oxide. Successful use of MgCaO as a passivation layer has also been confirmed with Hall measurements. An increase in sheet carrier density of 15% was seen for unprocessed HEMT material that was passivated with MgCaO and used as a Hall effect sample. Thermal testing was then applied to the samples to m easure their stability by annealing them at 100 C in a box furnace open to room ambient. No appreciab le decrease in the sheet carrier density was observed over the 25 day anneal.49 The main limitations of MgCaO are its poor environmental and thermal stability.50 Although uncapped MgCaO has shown less severe degr adation after anneali ng than MgO, it still requires a capping layer of Sc2O3 (5 nm). The use of the capping layer provided dramatic improvement in the thermal stability of the oxide as XRR results revealed little change in the interface roughness of the MgCa O/GaN interface after a 1000 C anneal for 2 min. In comparison to MgO films, MgCaO films have also been etched in water within 10 seconds. Films with lower growth rates that are richer in Mg have provided be tter stability than Ca rich or perfectly matched films, but furt her investigation must be done to grow a more stable film.

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34 Gallium Gadolinium Oxide Good electrical results with (Ga2O3)x(Gd2O3)1-x deposited on GaAs54-58 led to the study of (Ga2O3)x(Gd2O3)1-x/GaN MOSFETs59 and MOS capacitor60,61 structures. The oxide layer was deposited by electron-beam eva poration from a single crystal Ga5Gd3O12 garnet source at ~550 C. Characterization with TEM re vealed that 2-3 monolayers of Gd2O3 initially formed with the remaining oxide film containing a fine-grained polycrystalline mixture of Ga2O3 and Gd2O3. A breakdown field of 3 MV/cm was achieved for a MOS diode with an oxide thickness of 19.5 nm and film roughness of 3 nm.60 A Dit value of less than 1011 eV-1cm-2 was estimated from C-V curves for a MOS diode with an oxide film ~17 nm thick.61 No shifts in the flatband voltage appeared with changes in frequency (ranged from 20 Hz to 1 MHz), and negligible capacitance hysteresis lo ops were found for C-V measurements with biasing voltages sweeping up and down. An 8.5 nm thick layer that was annealed at 700 C showed leakage currents ranging from 10-5 to10-9 A/cm2. The high leakage current was attri buted to a rough GaN surface even though the substrate was heated to 650 C prior to deposition to remove surface contaminants.61 Although the diode showed a high leakage cu rrent, XRR results revealed that the (Ga2O3)x(Gd2O3)1-x/GaN interface and the in tegrity of the oxide remained stable for RTA treatments up to 950 C. Thermal stability was also seen in a (Ga2O3)x(Gd2O3)1-x/GaN depletion mode MOSFET as the I-V characteristics showed improvement upon heating to 400 C.59 The improvement was attributed to a reduction in th e parasitic resistances in the device. A gate breakdown voltage >35 V was achieved for the d-mode MOSFET compared to 16 V for a Pt Schottky gate on the same GaN epilayer. The lower breakdown voltage and significant gate leakage current for the Pt Schottky gate diode demonstrated the need for the (Ga2O3)x(Gd2O3)1-x

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35 gate dielectric. A limitation of (Ga2O3)x(Gd2O3)1-x is the control of the stoichiometry which is heavily dependent on the substrate temper ature and usage of the garnet source.57 Amorphous Dielectrics on GaN The next two sections provide a summa ry on the amorphous dielectrics of SiO2 and SiNx on GaN and AlGaN/GaN HEMTs. The majority of research on these two dielectrics has been on Si. Their ease of processing and good chemical stability has led to the attractiveness of utilizing them in GaN-based devices. Silicon Nitride Plasma enhanced chemical vapor deposition (PECVD) has commonly been used to deposit Si3N4 at 300 C.62-70 A Dit value of 6.5x1011 eV-1cm-2 (calculated by the Terman method) and a breakdown field of 1.5 MV/cm were reported for a Si3N4 (100 nm)/n-GaN insulatorsemiconductor.63 Electrical measurements also reveal ed a flatband voltage shift of 3.07 V. Analysis of the insulating layer by XPS revealed that it was slightly silicon rich. A lower Dit value of 5x1010 eV-1cm-2 (calculated by the Terman method) was obtained for a Si3N4/GaN structure that had an NH4OH treatment (15 min) followed by an N2 plasma treatment (1 min) before deposition of the insulating layer.64 The lower Dit value shows the importance of a clean substrate surface prior to depositi on. A similar structure with SiO2 as the gate dielectric received the same pretreatment as the Si3N4/GaN structure and it had a higher Dit value of 3.0x1011 eV1cm-2. Passivating AlGaN/GaN HEMTs with Si3N4 has proven more effective than using SiO2. This was attributed to the high density of SiO2/GaN interface states whic h is reported to be 10 times higher than that for Si3N4.65 The effectiveness of passivation with SiO2 and Si3N4 was tested by comparing 10 nm layers deposited by PECVD on AlGaN/GaN HEMTs.67 The SiO2 MOSHFET showed a greater reduction in dc current with an increas e in the input rf drive, and

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36 the Si3N4 MISHFET had an output power that exceeded the SiO2 MOSHFET by 3 dB for a large input rf drive. Both results revealed the greater degree of current collapse in the SiO2 MOSHFET. Bernat et. al. also showed that Si3N4 has a greater impact on DC performance than SiO2 for AlGaN/GaN HEMTs.65 Unpassivated devices had an IDS = 0.45 A/mm, passivation with SiO2 gave 0.54 A/mm, and passivation with Si3N4 gave 0.68 A/mm. Hall effect measurements showed a greater increase in sheet carrier density af ter passivation with Si3N4 than with SiO2. The use of Si3N4 to prevent gate leakage has shown good results. The leakage current for a MISHFET only increased from 90 pA/mm at room temperature to 1000 pA/mm at 300 C, remaining 3-4 orders of magnitude lower than an HFET with identical geometry.67 The dc saturation current also remained fairly constant from 25 to 250 C. A limitation of PECVD Si3N4 is the incorporation of hydrogen which can migrat e into the gate metallization or into GaN.36 Another limitation is that it has a lower dielectr ic constant of 7.5 compared to 9.5 for GaN. Silicon Dioxide Different techniques such as radio-frequency sputtering71, e-beam evaporation63, and most commonly PECVD63,72-76, have been used to deposit SiO2. E-beam evaporated SiO2 (100 nm thick) yielded a Dit value of 5.3x1011 eV-1cm-2 (calculated by the Terman method) and a breakdown field of 1.8 MV/cm fo r an n-GaN MOS structure.63 Electrical measurements also revealed a flatband voltage shift of 2.85 V. Analys is of XPS data revealed a peak with a binding energy of 100.14 eV (Si2O), indicating that a silicon-rich ox ide layer was deposited. A lower Dit value of 2.5x1011 eV-1cm-2 and a higher breakdown field of 2.5 MV/cm were obtained using PECVD for a 100 nm thick film.63 It also had a lower flatband voltage shift of 1.55 V. The XPS data for the PECVD deposited film showed closer agreement to the reported SiO2 composition.

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37 It was suggested that reduction in the interface state density was due to the composition of the SiO2 layer. The use of SiO2 in AlGaN/GaN MOSHFETs has produ ced extremely low gate leakage currents.74-76 A MOSHFET leakage current of 100 pA was measured at room temperature under a gate bias of V for a 10 nm thick film grown by PECVD.74 This value was six orders of magnitude smaller than an HFET with similar ga te dimensions. Another MOSHFET structure (15 nm thick oxide film grown by PEC VD) showed a leakage current of 1 A/mm at 300 C, which was approximately four orders of magn itude lower than an HFET with similar gate dimensions.76 The MOSHFET also showed good thermal st ability as the gate leakage remained below 60 pA/mm at 200 C for 36 h under bias (Vds = 20 V, Vgs = -2 V, Isd ~ 0.42 A/mm). After being subjected to an extremely high thermal stress at 850 C for 1 min, the drain saturation current only decreased by 20% and th e leakage current increased up to 20 A. Although SiO2 has shown good results, its biggest limitati on is that its dielectric constant ( = 3.9) is considerably lower than that of GaN ( = 9.5). This could cause a la rge electric field to build up in the dielectric and cause it to breakdown. GaN Surface Cleaning A clean surface prior to oxide deposition is critical as surface defects and impurities can influence the overall qualit y of the device (i.e., Dit) and the crystal quality of the deposited film. Numerous wet chemical treatments and in-situ methods have been used to obtain clean GaN surfaces prior to deposition. Some of the wet chemistry treatments have included the use of NH4OH64,66,77,79, HF78-80, and HCl78-80 to reduce the amount of carbon and oxygen contamination on the surface. In-situ me thods have included a N2 plasma treatment64,66,79, a N2/H2 plasma treatment79, a H plasma treatment80, NH3 flux annealing80,83,84, Ga flux annealing80-83, and

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38 deposition of Ga followed by annealing to evaporate the grown Ga monolayers81-83 from the surface. Ultraviolet-ozone (UV-O3) cleaning33,79,80,85 is an ex-situ method that has been used to reduce surface carbon contamination. UV-O3 Cleaning UV-O3 has been shown to be very effectiv e in removing both or ganic and inorganic contamination with the exception of inorganic salts.85 The cleaning mechanism begins when the contaminant molecules are excited and/or dissoc iated with the absorption of short wavelength UV light (i.e., 254 nm). Atomic oxygen and ozone simultaneously form when O2 absorbs UV light with a wavelength below 245 nm (ozone is primarily formed at 185 nm wavelength). Even more atomic oxygen is formed at higher waveleng ths (i.e., 254 nm) when ozone is dissociated by the absorption of UV light. The excited contamin ant molecules react with the atomic oxygen to form volatile species such as CO2, H2O, etc.85 Figure 2-8 shows the ef fectiveness of a 5 min UV-O3 treatment at removing carbon contaminati on from the GaN surface following photoresist removal with acetone. In-situ Cleaning In-situ plasma treatments have sh own success in removing carbon and oxygen contamination from the GaN surface. Cleani ng with a hydrogen plasma showed effective removal of carbon and halogen specie s at temperatures as low as 400 C, but it showed only moderate success in removing oxygen.80 The use of an in-situ thermal treatment with an H2/N2 plasma or an N2 plasma at 750 C for 5 min produced a clean Ga N surface within the detection limits of AES.79 However, SIMS data revealed th e presence of significant amounts of carbon (~3x1020 cm-3) and oxygen (~2x1022 cm-3) on the surface. These resu lts show that all three

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39 plasma treatments were effective at reduci ng the carbon and oxygen contamination, but further cleaning studies must be examined to obtain completely clean GaN surfaces. In-situ vacuum annealing has also been used to remove surface contaminants to less than the AES detection limits. However, annealing at 800 C has shown incomplete removal of oxygen and carbon from the surface as primarily C-H bonded carbon remains at temperatures ranging from 600-950 C.80 X-ray photoelectron spectroscopy data indi cated that complete desorption does not occur until 950 C. Annealing the surface up to 950 C is not an effective process as GaN begins to sublimate at ~800 C. Other in-situ vacuum anneals have been performed in NH3 (excellent scavenger of hydrocarbons), following Ga deposition at room temperature, and following Ga de position at temperatures around 600 C. Ex-situ Cleaning Ex-situ wet treatments have been used to reduce surface contamination and become even more effective when combined with an in-situ cleaning process. Treatment with a HCl:H2O (1:1) solution reduced the as-r eceived O/N ratio from 0.39 to 0.21 and the as-received C/N ratio from 0.28 to 0.24.78 Further in-situ annealing at 650 C for 15 minutes reduced both ratios to 0.14. Treatment with an HF:H2O (1:1) solution reduced the as -received O/N ratio from 0.39 to 0.26 and the as-received C/N ratio from 0.28 to 0.18.78 Further in-situ annealing at 650 C for 15 minutes reduced the O/N and C/N ratios to 0.17 and 0.13 respectively. Characterization with AES and XPS has shown the abilities of a warm (50 C) NH4OH solution to significantly reduce the amount of oxygen contamination at the surface.77 An in-situ N2 plasma treatment (1 min) following a 15 min NH4OH treatment was shown to reduce the Dit to 5x1010 eV-1cm-2 (calculated by the Terman method) for a Si3N4/GaN structure.64 Since each of these ex-situ wet treatments is effective at reducing the level of oxygen contamination at the surface, either of

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40 these treatments could be used following a UV-O3 treatment to strip the formed native oxide layer.

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41 Table 2-1. Properties of pr eviously used dielectrics. Material Structure Lattice constant () Band gap (eV) (K-1) Tmp (K) SiO2 Amorphous NA 9.0 3.9 0.5x10-6 1900 SiNx Amorphous NA 5.0 7.5 3.3x10-6 2173 (Ga2O3)xPolycrystalline 4.7 14.2 2023 (Gd2O3)1-x Ga2O3 Hexagonal a = 0.498, c = 1.343 4.4 10.0 2013 Gd2O3 Bixbyite 10.8130 5.3 11.4 1.0x10-5 2668 Sc2O3 Bixbyite 9.8450 6.3 14.0 2678 MgO Rock salt 4.2112 8.0 9.8 1.3x10-5 3073 *Value could not be found

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42 A B Figure 2-1. Cross-section illustration of a depleti on mode n-MOSFET. A) Device is in the ON state with VG = 0. B) Device is in the OFF state with VG < 0. [Reprinted with permission from B.P. Gila, 2000. Grow th and Characterization of Dielectric Materials for Wide Bandgap Semiconductors. PhD dissertation (pg. 21, Figure 2-2). University of Florida, Gainesville, Florida.] n-GaN +n-GaN source gate drain VG=0 n-GaN +n-GaN source gate drain VG<0 + + + + + + + + + +

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43 A B Figure 2-2. Cross-section illustration of an enha ncement mode n-channel MOSFET. A) Device is in the OFF state with VG = 0. B) Device is in the ON state with VG > 0. p-GaN source gate drain VG=0 n+ n+ p-GaN source gate drain VG>0 n+ n+ -

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44 Figure 2-3. E-mode n-channel MOSFET. A) 3-D view of MOSFET and equilibrium band diagram along channel. B) ID-VD curve for MOSFET as a function of gate voltage. [Streetman, Ben; Banerjee, Sanjay, Solid State Electronic Devices, 5th Edition, 2000, pg. 256, Figure 6-10. Reprinted by permission of Pearson Education, Inc., Upper Saddle River, NJ] B A

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45 Figure 2-4. N-channel MOSFET. A) Fo rmation of conducting channel with VG > VT. B) Onset of saturation with VG VD = VT. C) Strong saturation with VG VD < VT. [Streetman, Ben; Banerjee, Sanjay, Solid State Electronic Devices, 5th Edition, 2000, pg. 258, Figure 6-11. Reprinted by permission of Pearson Education, Inc., Upper Saddle River, NJ] A B C

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46 Figure 2-5. Energy band diagram for ideal p-type MOS capacitor at VG = 0. [Streetman, Ben; Banerjee, Sanjay, Solid St ate Electronic Devices, 5th Edition, 2000, pg. 261, Figure 6-12. Reprinted by permission of Pearson E ducation, Inc., Upper Saddle River, NJ]

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47 Figure 2-6. Energy band diagrams for ideal nan d p-type MOS capacitors under an applied bias. A) Accumulation. B) Depletion. C) Inve rsion. [Reprinted with permission from B.P. Gila, 2000. Growth and Characteriza tion of Dielectric Materials for Wide Bandgap Semiconductors. PhD dissertation ( pg. 130, Figure A1-3). University of Florida, Gainesville, Florida.]

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48 Figure 2-7. Valence band and conduction band offs ets with respect to GaN for previously researched dielectrics. GGG represents (Ga2O3)x(Gd2O3)1-x.

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49 Figure 2-8. Auger peak-to-peak ratios for C:Ga, C:O, and Ga:O on GaN with UV-O3 treatments of 1, 3, 5, and 10 minutes. 0246810 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 Peak-to-peak ratioUV-O3 time (minutes) C:Ga ratio C:O ratio Ga:O ratio

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50 CHAPTER 3 EXPERIMENTAL APPROACH Molecular Beam Epitaxy Molecular beam epitaxy (MBE) was used to depos it the oxide films. It allows films with abrupt interfaces and very smooth surfaces to be deposited in an ultra-high vacuum environment using high purity sources. The high purity sour ces can be controlled independently from each other by using ovens called Knudsen cells (Figure 3-1). The flux of atoms emitted from the cell is represented by Equation 3-1: 2 / 1 2 22) ( ) )( ( 10 18 1 MT d a P x F (3-1) where F is the flux (in atoms/cm2) of the Knudsen cell, a is the orifice area (in cm2) of the cell, P is the vapor pressure (in torr) inside the cell, T is the temperature (in degrees Kelvin) of the cell, M is the atomic mass (in amu) of the element in the cell, and d is the distance (in cm) from the cell to the substrate. The ability to change the flux of atoms emitted from the cell allows a high degree of control over th e stoichiometry of the deposited film The purity of the atomic beam emitted from the cell is dependent upon the purit y of the source and the vacuum level in the chamber.86 The high vacuum inside the chamber is one of the attractive qualities of MBE that provides a clean environment and allows highly pure films to be grown. Precise co ntrol of the substrate temperature in MBE also allows control of the mi crostructure of the deposited films. The growth rate is dependent on the flux of the elements to the substrate, the ratio of the elements, and the substrate temperature. Lower substrate temper atures and higher fluxes can be used to produce amorphous or fine-grained polycrystalline films. Higher substrate temper atures and lower fluxes can be used to produce single crystal films.

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51 A Riber 2300 MBE system (Figure 3-2) was used for all of the oxide growths. The growth chamber was pumped down to a range of 1x10-9 torr using an Oxford Cryo-Torr 8 cryopump. The MBE system is equipped with a Reflec tive High Energy Electron Diffraction (RHEED) gun to provide in-situ characterizati on of the oxide film during growth. It also provides information on the substrate surface prior to growth. The MBE system contains six ports with five of them containing Knudsen cells (3 Ribe r 125 LKs with 25 cc crucible s, 1 Varian 0981-4135 with a 40 cc crucible, and 1 EPI 91-734 with a 25 cc crucible ) for various sources (Sc, Ga, Mg, Ca, and Sm) and the remaining port containing the oxyge n plasma source. The temperature of the Knudsen cells is controlled by a FICS 10 controller that adjusts the power output of an external power supply whose power cables are connect ed to two posts on the cell. An MDP21 radio frequency (rf) source from Oxford Applied Research was used as the oxygen source for the growths. It was operate d at a frequency of 13.56 MHz with a forward power of 300 W and a reflected power of 2-3 W. Oxygen (99.995%) was supplied to the plasma head using a high purity 8161c Unit (Celerity) O2 mass flow controller (M FC) that had a 3 sccm full scale range. The plasma is generated as soon as a high enough voltage is applied between the two electrodes to create an electric field in the reactor that exceeds th e breakdown field of the gas. As soon as the high voltage arc flashe s between the two electrodes, a large number of dissociated atoms are created. The dissociated atoms and undissociated molecules then escape into the vacuum environment through an array of fine holes in the aperture plate. The electrical potential remains low enough so that negligible cu rrents of ions and electrons will escape from the discharge tube. The substrate temperature was measured us ing a back side thermocouple in close proximity to the substrate holder. The substrat e thermocouple was calibrated by using pieces of

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52 gallium antimonide (GaSb) and indium antimonide (InSb), which have melting points of 707C and 525C respectively. The pieces of GaSb and In Sb were heated in the growth position under a nitrogen plasma to reduce the chance of losi ng Sb. Loss of the group V species during heating would result in an incorrect melting temperature. Substrate Preparation All substrates received an ex-situ and in-situ surface treatment prior to oxide deposition to remove any surface contamination. A clean surf ace prior to deposition is critical as surface defects and impurities can influence the overall quality of the device (i.e., Dit), the metal contact resistance/stability, the crystal quality of the de posited film, and the epitaxial defects. Prior to treating the surfaces, the substrates were in spected under a microscope, and an RMS roughness was determined by AFM as a reference value. Th e substrates used for oxide deposition included Si and GaN. Silicon Phosphorous doped (n-type) Si substrates from Wacker-Chemitronic GMBH were used for the oxide growths involving initia l calibrations. The substrates were 50 mm wafers with a (100) orientation. The low cost and wi de availability of Si made it more feasible to use when calibrating the thickness, growth rate, compositi on, or uniformity of the dielectric films. Each Si sample received an ex-situ treatment in buffered oxide etch (BOE) solution (6:1 NH4F:HF in water) to remove the native oxide la yer. After removing the native oxide, the sample was rinsed in deionized water and blown dry with an N2 gun. An rms value of 0.08 nm was measured with AFM following this surface treatm ent. After receiving an ex-situ treatment, the Si sample was immediately indium mounted to a molybdenum block and then placed under vacuum inside the load lock of the Riber 2300 MBE system. The sample was then cleaned in-

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53 situ by heating it up to 200 C to drive off any moisture that collected on the surface between the time it was etched in BOE and placed under vacuum. Gallium nitride Gallium nitride (GaN) wafers were provide d by Uniroyal and the Abernathy group (GaN wafers were grown using a Veeco MOCVD syst em). The Uniroyal wafers were used for calibrations on GaN due to their higher surface ro ughness and pits (Figure 3-3) that were seen on the surface by AFM. Some of the pits had a de pth as great as ~114 nm which is much greater than the thickness of the oxide films. The GaN wafers provided by the Abernathy group were used for oxide growths that involved characteri zation of the crystal stru cture of the oxide and fabrication of the oxide to make MOS capacito rs for electrical testi ng. The Abernathy group GaN wafers (Figure 3-4) had a lower surface roughness (rms as low as 0.134 nm using a 1 m scan) compared to the Uniroyal GaN. Each GaN sample received an ex-situ treatment starting with a 3 min HCl:H2O (1:1) solution to degrease the sample and remove as much oxygen and carbon contamination as possible. After removing the sample from the solution, it was rinsed in deionized water and blown dry with an N2 gun. It was then given a 25 min UV-O3 treatment in a UVOCS UVO cleaner (model number 42-220) to remove any residua l carbon. The sample was finally placed in a 5 min BOE solution to remove the native oxide formed from the UV-O3 treatment and then rinsed in deionized water and dried with an N2 gun. Successful removal of the native oxide was observed with RHEED images of the surface. The RHEED pattern of the su rface with the native oxide showed arcs, and the RHEED pattern of th e BOE treated surface showed streaks (Figure 35).

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54 After receiving an ex-situ treatment, the Ga N sample was immediately indium mounted to a molybdenum block and then placed under vacuum inside the load lock of the Riber 2300 MBE system. The sample was then given an in-situ thermal treatment at 700 C for 10 min to remove any oxygen or carbon contamination on the surfa ce that was not removed during the ex-situ treatments. The room temperature RHEED pattern showed a (1x1) surface (Figure 3-5b), and a (1x3) pattern appeared after the in-situ thermal treatment at 700 C (Figure 3-6). Scandium Gallium Oxide Growth Scandium gallium oxide films were depos ited using a 99.999% pure Sc rod and 99.9999% pure Ga ingot. The Sc Knudsen cell temperatures ranged from 1170 C to 1200 C and the Ga Knudsen cell temperatures ranged from 700 C to 884 C. A substrate temperature of 100 C was used with an oxygen pressure ranging from 8x10-6 Torr to 1.1x10-5 Torr with an Oxford RF plasma source at 300 W forward power and 2 W reflective power. Sample rotation was kept constant at 15 rpm during the film growth. Nume rous growth techniques were employed to grow a continuous film with good electr ical properties. These growth techniques are discussed in chapter 4. Magnesium Oxide Growth Magnesium oxide films were grown using a 99.99% pure Mg rod at Knudsen cell temperatures ranging from 340 C to 360 C. A substrate temperature of 100 C was used, and films were deposited at low growth rates rangi ng from 0.8.4 nm/min since MgO films at lower growth rates showed more stability during pr ocessing. The oxygen pressure was kept below 5x10-6 Torr with an Oxford RF plasma source at 300 W forward power and 2 W reflective power. The samples were rotated duri ng the film growth at 15 rpm.

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55 Magnesium Scandium Oxide Growth Magnesium scandium oxide films were grow n with a fixed Mg cell temperature of 340 C and an increasing Sc cell temperature ranging from 1090 C to 1180 C. A substrate temperature of 100 C was used for all growths. The oxygen pressure was kept below 4x10-6 Torr with an Oxford RF plasma source at 300 W forward pow er and 2 W reflective power. The samples were rotated during the film growth at 15 rpm. The thickness and growth rate of the deposited films increased with increasing Sc cell temperature. Start Up After the samples received their ex-situ tr eatment and were placed under vacuum in the load lock, liquid nitrogen was run through the cryopanels, which served to decrease the thermal interaction of the Knudsen cells and lower the pr essure of the growth chamber. The Knudsen cell for each source that was need ed was raised at a rate of 100 C every 10 minutes until the desired temperature was reached. The sample s were transferred on a trolley to the buffer chamber, and then a sample was loaded into the growth chamber using the manipulator (or transfer) arm. The sample then received an in-situ thermal treatment facing towards the sources. After receiving the thermal treatment, the sample was cooled to the desire d substrate temperature facing away from the sources. Once the substr ate temperature was reached, the oxygen plasma was lit and the desired oxygen pressure was adjusted with the O2 MFC. After reaching 90 mV on the photodiode for the plasma, the shutters for the oxygen source and source material were opened. The sample was then moved into the growth position facing to wards the sources and rotated at 15 rpm for th e duration of the growth.

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56 MOS Capacitor Fabrication After the oxide films were deposited and th e samples removed from the MBE system and molybdenum block, they were processed to make MOS capacitors seen in Figure 3-7. The first processing step involved opening up ohmic windows so that the e xposed oxide could be etched away (Figure 3-8). The second step was used to deposit ohmic contacts in the areas of oxide that were etched away (Figure 3-9). However, a thin ring of GaN between the oxide island and ohmic contact was left open so that the oxide co uld be electrically isolated from the ohmic pad. The final processing step involve d depositing metal gates of 50 m or 100 m in diameter on top of the oxide island (Figure 310). Fabrication of the MOS ca pacitors allowed IV and CV measurements to be taken which helped to de termine the performance of the oxide. The key processing steps involved photolithography, etch ing, metallization, and annealing. A complete description of the lithography st eps and more detailed inform ation regarding lithography are given in Appendix A. Photolithography Shipley 1818 was used as the photoresist (PR) in each lithography step. A Laurell WS400A 6NPP/Lite was used to spin the PR on the samples. Dynamic dispense was used to apply the PR as it was dispensed at 1000 rpm (and accel eration of 1200 rpm/sec) and spun to a final speed of 5000 rpm (and acceleration of 1500 rpm/s ec). A spin speed of 5000 rpm corresponded to a thickness range of 2.0.2 m depending on the conditions of the PR and conditions inside the photolithography room. The samples were then given a soft bake on a Thermolyne hot plate at 125 C for 1.5 minutes. A Karl Suss MA6 mask aligner was used to alig n the sample to the pattern in the mask and then expose the sample with a mercury xenon lamp at a 365 nm wavelength. Hard contact mode

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57 was used which presses the sample firmly against the mask to minimize any diffraction effects. Other parameters included an Al gap of 100 m, WEC offset of 0, and WEC type as contact. The exposure time was calibrated based on the PR thickness and exposure dose. After exposure, the samples were developed in either Rohm and Haas MF-319 developer or AZ 300 MIF developer at room temperat ure. The development time was 30 seconds, depending on the exposure time. After developing th e samples, they were rinsed in DI water and then blown dry with an N2 gun. A post bake at 110 C for 1 minute was then applied to samples that were etched in the subsequent processing ste p. A post bake was not used when the next step was metallization. For cases in which the metal gates were lifti ng off the oxide, the use of LOR 3B was used in a bi-layer stack with 1818. The LOR 3B was spun onto the sample at the same dispense and final spin speeds as the 1818 resi st. However, it was baked at 150 C for 5 minutes, which produced a thickness of ~0.25 m (needs to be about 1.2.3 times the thickness of the deposited metal). It also received the same exposure a nd development times as the 1818 since the 1818 was coated over the top of it. The high development ra te of the LOR 3B provides an undercut profile (Figure 3-11) of the film below the 1818, making it attract ive for metal lift-off. Etching A wet etching chemistry is desirable for oxide films on p-GaN as dry etching of p-GaN has been shown to cause plasma damage, which can lead to an increase in sheet resistance of the pGaN and conversion to an n-GaN surface at high ion fluxes or ion energies.87,88 Etching times were determined based on numerous samples (with the MOS capacitor patterns) etched at different times which were then analyzed with Auger Electron Spectroscopy (AES) to see if the oxide was completely removed from the GaN substr ate. The type of etching chemistry depended

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58 upon the type of oxide. It was found that a 2% H3PO4 solution at room temperature could etch a 40 nm MgO film in 10 seconds. A H2SO4:H2O (1:1) solution was used for etching (Sc2O3)x(Ga2O3)1-x since it previously showed successful removal of Sc2O3 films on GaN. It was determined that a 12 minute etch could remove a ~33 nm thick film (Figure 3-12). Dry etching is advantageous for processi ng of smaller features where the undercut produced from lateral etching during the wet etch must be limited or completely eliminated. More importantly, dry etching is desirable for stacked gate dielectrics in which the bottom dielectric has a much greater se lectivity over the top di electric for a given wet etching solution. The extremely high selectivity of the bottom dielectric could l ead to a situation where over etching the top dielectric causes etching and comp lete removal of the bottom dielectric from the substrate. Finding a dry etch chemistry where the top dielectric etches selectively over the bottom dielectric would prevent over etching and would allow th e bottom dielectric to serve as an etch-stop layer. Any dry etching was performed in a Unaxis Shuttlelock Reactive I on etcher (RIE) with Inductively Coupled Plasma (ICP) module. Th e system was equipped with a 2 kW inductively coupled power supply (13.56 MHz RF) and a 600 W RIE power supply (13.56 MHz RF). The ICP power is used to generate reactive ions and neutrals in the chamber that chemically react with species at the surf ace. This chemical component of the dry etching process leads to isotropic etching that is selective (gases are chosen for different reactions). The RIE power (substrate bias) is used to accelerate the energe tic ions to the substrate with the purpose of driving the surface chemical reac tions rapidly and physically dislodging atoms from the surface by sputtering. This physical component leads to anisotropic etching wi th no selectivity. The process pressure in the chamber can be increased to increase the density of reactive species, but

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59 an increase in the pressure lowers the mean free path which can affect th e energy the ions strike the substrate with. Samples were transferred and etched on a 4 Si wafer carrier with a number of available gases (SF6, BCl3, Cl2, CHF3, O2, Ar, H2, CH4, N2) for etching. A thicker PR (Shipley 1045) was used for patterning since it held up better and longer to stronger dry etching conditions compared to thinner resists. Dry etching chemistries va ried depending on the type of oxide due to the volatilities of the etch products involved. A CH4/H2/Ar mixture was found to etch (Sc2O3)x(Ga2O3)1-x at rates ranging from 5.5 nm/min at a process pressure of 5 mTorr (Figure 3-13). More importantly, the GaN did not show any detectable etching (given the ~2 nm resolution of the stylus profilometer) at the same etching conditions. Due to the higher selectivity of (Sc2O3)x(Ga2O3)1-x over GaN in the CH4/H4/Ar chemistry, this chemistry is suitable for selective removal of (Sc2O3)x(Ga2O3)1-x from GaN substrates (Figure 3-14). Metallization A Kurt Lesker CMS-18 multi target sputter depo sition tool was used to sputter the ohmic contacts and metal gates. Spu ttering involves the ejection of atom s from a solid metal target due to the momentum transfer from bombarding energetic ions (i.e., Ar+). A DC voltage is maintained across plane parallel electrodes with the metal target serving as the cathode and the substrate (or sample) serving as the anode. A larg e supply of energetic ions in the interelectrode region is accelerated to the material target und er an applied electric fi eld. Once the energetic ions strike the target, atoms are dislodged from the metal target by momentum transfer. The dislodged metal atoms then deposit on the substrat e. The sputter yield depends on the ion flux of the target, the probability that the impact of the energetic ion ejects a target atom, and the transport of the sputtered material across the interelectrode region to the substrate.

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60 Ohmic contacts on n-GaN or u-GaN consisted of a multi-layer structure of Ti (20 nm)/ Al (80 nm)/ Pt (40 nm)/ Au (80 nm). The Ti la yer reacts with nitrogen to form TiN which makes the ohmic, the Al layer controls the TiN reaction, th e Pt layer is a diffusion barrier to prevent Al and Au from reacting, and the Au layer is used for making contact to probe tips since the layer does not oxidize. Ohmic contacts on p-GaN consis ted of a bi-layer struct ure of Ni (50 nm)/Au (80 nm). Gate contacts on the dielectric included a bi-layer structure of Pt (30 nm)/Au (120 nm). Gate contact sizes of 50 m or 100 m were used for the MOS capacitors. After metal deposition, metal lift-off was pe rformed in a sonicator. Samples were immersed in a beaker of MicroChem Nano Remo ver PG, which was then transferred into the sonication bath. Samples experiencing diffi culty with lift off were heated up to 50 C for 30 minutes on a Thermolyne hot plate before using th e sonicator again. Once lift-off was complete, samples were rinsed in isopropanol then DI water and finally blown dry with an N2 gun. Annealing Ohmic contacts on the samples were annealed in the MBE system or an AG Associates HeatPulse 610 RTA system. Annealing condi tions were strongly de pendent on the doping density of the nand p-GaN material. Oxides on n-GaN or u-GaN were primarily annealed for 45 seconds at 400 C in the growth chamber. Other samples were annealed at 700 C for 30 seconds in the RTA system under an N2 ambien t. Oxides on p-GaN were annealed at 300 C for 1 min in the RTA system under an N2 ambient. Indium on the backside of the samples was removed (refer to Appendix A regarding the proce dure) prior to annealing the samples in the RTA system.

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61 Materials Characterization Numerous characterization techniques were used to analyze the deposited oxide films. The four primary areas of characterization include d surface, structural, ch emical, and electrical analysis. Surface analysis is important for futu re processing of the material as etching and deposition of metal to form contacts is sensitiv e to the morphology and roughness of the surface. Structural analysis is critical in determining th e crystal structure, crys tal phases, and types of defects present within the film. These characte ristics are crucial to the effectiveness of the dielectric, as a polycrystalline film with numerous defects would provide multiple pathways for gate leakage to occur. Chemical analysis is extremely important in determining the amount and type of species within the film as well as how the species are bonded. El ectrical analysis is critical in measuring the performance of th e oxide and determining the optimum growth parameters that produce the best electrical resu lts. Most of the following characterization methods can be found in reference 89. Scanning Electron Microscopy (SEM) Scanning Electron Microscopy (SEM) is used for analyzing the topography and surface morphology of samples. High magnifications (up to 500,000x for field emission SEM) and good depth of field make SEM attractiv e for surface analysis. The technique uses an electron beam as its source with beam energies ranging from 0.5 keV to 30 keV. Interaction of the beam with the sample produces backscattered electrons (BSE) a nd secondary electrons (S E). Elastic scattering is responsible for backscattered el ectrons in which the trajectory of the beam electron is changed without altering the kinetic energy of the electrons Backscattered electron s are used for atomic number or compositional contrast. Inelastic scattering is responsib le for secondary electrons in which energy is transferred from the beam el ectrons to atoms of the specimen, resulting in emitted electrons with energies less than 50 eV Secondary electrons strongly affect the

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62 topographical image. An important limitation of SEM is that samples must be conductive to prevent charging (causes distortions in image) fr om occurring. Since the deposited oxide films are not conductive, they can be coated with car bon or a lower beam voltage can be used to minimize the charging. A JEOL 6400 and JEOL JSM-6335F were used to characterize the oxide films. The JEOL 6400 is a thermionic emission SEM that uses a tu ngsten filament. Thermionic emission occurs when enough heat is applied to the filament so that electrons can overcome the work function of the material and escape from the material itse lf. Some of the disadvantages of thermionic emission include relatively low brightness, evapor ation of the cathode material, and thermal drift during operation. The JEOL JSM-6335F is a field emission SEM that uses a LaB6 filament. Field emission occurs by applying an electric field (that can be con centrated to an extreme level) to reduce the potential barrier that electrons n eed to overcome. The primary advantage of the field emission SEM is its high spatial resolution (<2 nm which is 3 times better than an SEM utilizing thermionic emission). Both instruments were used for analyzing as-grown oxide films and samples that were processed as diodes for elec trical testing. They we re useful for detecting obvious defects or pinholes that we re attributed to shorting in speci fic MOS capacitors. Atomic Force Microscopy (AFM) Atomic Force Microscopy (AFM) can also provide information on the topography and morphology as well as the root mean square (RMS) roughness of the surface. An AFM Dimension 3100 in tapping mode was used for measuring the surface roughness of the oxide films and as-received GaN substrates as well as the surface morphology and topography of asgrown oxide samples and processed diodes. In tapping mode, the tip of the stylus (made of Si3N4) is brought into close proximity to the surface so the van der Waals forces between the probe tip and surface atoms of the sample can be measured. These forces depend on the probe

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63 geometry, the nature of the sample, contamina tion on the sample surface, and distance between the probe tip and sample surface. The forces lead to deflection of the cantilever which holds the tip at the end. The deflection is then measured by a laser spot that is reflected off the tip and collected with a photodiode. The intensity of the reflected light is processed as the height for that point on the surface. Rastering the tip ac ross the sample surface allows a 3-D map to be created, which can be used to calcul ate the RMS roughness. Sensitivity of the AFM depends greatly on the sensitivity of the deflection and sharpness of the tip. The tapping mode tips used to charact erize the oxide samples and GaN substrates had a tip radius of 5 nm and deflec tion sensitivity of ~0.01 nm. Contact mode is an alternate AFM method that can be used, but the tip radius is ~20 nm, which greatly reduces the resolution. Reflective High Energy Electron Diffraction (RHEED) Reflective high energy electron diffraction (RHEED) provides information on the growth mode (2-D or 3-D), surface crys tal structure, surface roughness, and surface orientation. The surface analysis is a result of an electron beam (5 kV) at low impact angles (<5 ) which allows electrons to pass through th e top few atomic layers of the surface. After reflecting off the surface, electrons strike a phosphor escent screen and form a diffr action pattern. The generated diffraction pattern helps to characterize the s ubstrate surface prior to growth, the growth initiation mode, and the quality of the de posited films during and after growth. Analysis by RHEED was conducted in-situ in the modified Riber 2300 MBE system (mentioned previously) at a beam voltage of 6 kV Single crystal surface s showed a spotty or streaky pattern, polycrystalline surfaces s howed a ringed pattern, and amorphous surfaces showed almost no pattern at all (Figure 3-15). A pattern with streaky lines indicated a smooth

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64 surface growing layer-by-layer (2D), and a spo tty pattern indicated a rough surface with islanding growth (3D). Ellipsometry Ellipsometry is used for determining the thickness and optical constants (n and k) of dielectric films. The technique involves the us e of plane-polarized light which reflects off a sample at a given angle and is then analyzed fo r a change in the polarization. Analysis of the change in polarization yields two parameters (t he azimuth and phase difference) from which the optical properties are calculated. A Rudolph V-530044 Auto EL IV ellipsometer was used for characterization of the oxide films. Transmission Electron Microscopy (TEM) Transmission electron microscopy (TEM) is a valuable instrument for providing microstructural analysis of thin films. Its high lateral re solution (~0.15 nm) allows it to provide detailed analysis of the morphology, defects presen t in the film, the atomic structure, and an accurate calculation of the lattic e constant. The high lateral re solution is obtained by using an extremely thin simple which interacts with a fo cused beam of electrons. The transmitted and forward scattered electrons form an image on th e other side of the sample and a diffraction pattern in the back focal plane. The thin sa mples are prepared by using a focused ion beam (FIB) instrument which uses a beam of Ga+ ions to sputter atoms from the surface so the sample can be thinned down or a particular area of interest can be precisely milled. A FIB FEI Strata DB (dual beam) 235 was used to prepare the oxide films, and a TEM 2010F operating at 400 keV was used for high-resolution analysis of the oxide/GaN interface and crystal structure of the oxide films.

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65 X-Ray Diffraction (XRD) X-ray diffraction (XRD) is used for determini ng the crystal phases and crystal structure present in bulk films. The principle of XR D is governed by Braggs law in Equation 3-2: sin 2 d n 3-2) where n is the number of whole wavelengths, is the wavelength of the incident x-ray (1.5406 for Cu K d is the spacing betw een planes (), and is the Bragg angle (degrees). Constructive interference of x -rays for certain atomic planes produces characteristic diffraction peaks. The diffraction spectrum produced from the measurement helps to determine if the film is amorphous, polycrystalline, or si ngle crystal. The full widt h at half max (FWHM) of a diffraction peak can also be used in determin ing the crystal quality of the film. A Philips APD 3720 x-ray powder diffractometer was used to characterize the oxide films. Samples were analyzed using a Cu K x-ray source, and a 2 range of 20 was scanned using 0.02 increments. Crystal phases were iden tified by standards taken from the JCPDS Powder Diffraction File. All id entified peaks were calibrated to the GaN (004) peak position (2 = 73.078 ). A Phillips MPD 1880/HR with a 5-crystal analyzer and Cu K x-ray source was used for x-ray reflectivity (XRR) measurements Measurements included film thickness and interfacial roughness at th e air/oxide interface and oxide/GaN interface. X-Ray Photoelectron Spectroscopy (XPS) X-ray photoelectron spectrosc opy (XPS) was used to look at chemical bonding in the deposited films by measuring the bi nding energies of atoms in the top few monolayers. It uses xrays as its source to eject phot oelectrons from the sample. Due to the small escape depth (depends on KE of photoelectron and material through which it travels) of the photoelectrons, XPS is limited to surface analysis (top fe w monolayers). The kinetic energy of the

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66 photoelectrons is measured by a hemispherical analyzer and the binding energy is calculated using Equation 3-3: BE = h KE SP (3-3) where h is the energy of the incident x-ray (1486.6 eV for Al and 1256.6 eV for Mg), KE is the kinetic energy (in eV) of the photoelectron, SP is the work function of the spectrometer, and BE is the binding energy (in eV) of the photoelect ron. The electron binding energy is highly influenced by its chemical surroundings. The gene ral trend is that binding energy increases with increasing charge on the atom. The characteristic peaks produced in th e spectrum were id entified using handbooks containing previously determined standards. The handbooks show the energies of core and valence level electrons and Auge r electrons for atoms in thei r zero-valence state and their different oxidation states when bonded to other chem ical species. This information was used to identify the chemical constituents present in th e film and whether any of the constituents were bonded to each other. Both Mg and Al anodes were used depending on the possible interference of Auger lines with XPS lines. The photoelectron binding energy remains the same regardless of which anode is used, but the binding energy of the Auger el ectron changes (KE of A uger electron does not change with change in anode). This allows Auger lines to be separated from XPS lines in situations where Auger lines overlap XPS lines. In situations where multiple XPS peaks overlap each other, the peaks must be deconvoluted by using RBD Analysis Suite software. Depth profiles were used to analyze any chemical cha nges at the bulk or oxi de/GaN interface. A Perkin-Elmer PHI 5100 ESCA system wa s used for all XPS characterization.

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67 Auger Electron Spectroscopy (AES) Chemical composition and film uniform ity was determined by Auger Electron Spectroscopy (AES). Auger electron spectrosco py is a three electron process that uses an electron beam as its source. The electron beam ejects a core electron from an atom, creating an atomic inner shell vacancy which will be filled by an electron from a higher energy (outer) shell. As the electron drops from the higher to lower en ergy shell, it releases energy as an x-ray or by ejecting electron (the Auger electro n) from one of the outer shells of the atom. Due to the low energy (typically in the range of 50 eV to 3 keV) of Auger electrons, the escape depth is very small (a few monolayers), limiting AES to surface analysis (Figure 3-16).90 As the kinetic energy of the Auger electrons is measured, a plot forms with peaks characteristic of the atoms and energy levels fr om which the Auger electrons originated. The kinetic energies and footprint of the peaks can be used to identify elements present in the sample by referring to previously determined standard s. The atomic composition of the identified elements can be calculated to + 10 atomic percent. Film uniform ity and analysis of the bulk can be conducted with depth profiles. All depth pr ofiles were taken using the 3-point method. A Perkin-Elmer PHI 660 Scanning A uger Multiprobe was used for all AES characterization. Current-Voltage (I-V) Measurements A Hewlett Packard Model 4145 was used to make current-voltage measurements. Compliance was set at 100 nA, and the voltage was swept in both negative and positive directions until the forward and reverse breakdowns were reached. Voltages were extracted from the I-V plot at 19.6 nA for diodes with 50 um gates and at 78.5 nA for diodes with 100 um gates. These currents correspond to a current density of 1 mA/cm2 (typical breakdown voltages are reported at this current density) for their respec tive gates. The extract ed voltages were then

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68 divided by the dielectric film thickness to determine the forward and reverse breakdown voltages. Dielectric breakdown is often charac terized in three distinct modes.91 Mode A failures occur at low breakdown voltages and are attributed to defects within the diel ectric, defects at the oxide/substrate interface, pinholes in the dielectric, and scratche s. Mode B failures occur at intermediate breakdown voltages and are attributed to dielectric th inning. Mode C failures occur at high breakdown voltages and are attributed to the intrinsic na ture of the dielectric. Capacitance-Voltage (C-V) Measurements A Hewlett Packard Model 4284 LCR connected to a Lab View based PC was used to make capacitance-voltage measurements. The LCR mete r supplied a voltage signal of superimposed analog current (AC) and direct cu rrent (DC). The width of the bias range was chosen depending on the doping density of the substrate. Higher do ped substrates required the use of larger bias ranges (ex. a range from 6 V to -6 V was used on an n-GaN substrate with a doping density of 1x1017 cm-3) to fully deplete the high concentration of majority carriers. Since high positive or negative gate biases can inject ca rriers into the oxide (this leads to oxide trapped charge) and/or influence the movement of mobile charges within the oxide, low doped substrates were typically used so that low gate biases could be applied in a small bias range (ex. a range from 2 V to 0 V was used on a u-GaN substrate with a doping density of 1x1016 cm-3). Devices were cycled at frequencies rangi ng from 10 kHz to 1 MHz in both series (Cs-Rs) and parallel (Cp-Rp) modes at an oscillation voltage of 50 mV. Both low and high bias sweep rates were also used. All devices were swep t from accumulation to depletion by going from positive to negative voltages for devices on n-type substrates and negative to positive voltages for devices on p-type substrates The data from the C-V curve was used to determine the

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69 interface state density, flat band voltage shift, and dielectric constant. Information and equations on how to calculate these values can be found in Appendix B.

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70 Figure 3-1. Illustration of a typical Knudsen effusi on cell. [Reprinted with permission from B.P. Gila, 2000. Growth and Characterization of Dielectric Materials for Wide Bandgap Semiconductors. PhD dissertation (pg. 37, Fi gure 3-1). University of Florida, Gainesville, Florida.] PBN crucible Source material Ta Heater element Thermocouple Atoms or atom clusters

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71 Figure 3-2. Top view sketch of Riber 2300 MBE syst em used for oxide growth. [Reprinted with permission from B.P. Gila, 2000. Growth and Characterization of Dielectric Materials for Wide Bandgap Semiconductors PhD dissertation (pg. 38, Figure 3-2). University of Florida, Gainesville, Florida.] RF PLASMA SOURCE SOLID SOURCE RHEED Gun Load/lock Buffer chamber SOLID SOURCE Manipulator Arm

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72 A 4.0m B Figure 3-3. AFM images showing pits at surface of as-received Uniroyal GaN. A) 3-D image of 20 m scan. B) 2-D image of 20 m scan.

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73 A 1.0m B Figure 3-4. AFM images showing MOCVD GaN gr own by the Abernathy group. A) 3-D image of 5 m scan. B) 2-D image of 5 m scan.

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74 A B Figure 3-5. RHEED images of pre-tr eated GaN surface. A) After UV-O3 treatment. B) After BOE treatment of UV-O3 treated surface. [Reprinted w ith permission from B.P. Gila, 2000. Growth and Characterization of Di electric Materials for Wide Bandgap Semiconductors. PhD dissertation (pg. 43, Fi gure 3-7). University of Florida, Gainesville, Florida.]

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75 A B Figure 3-6. RHEED photos of GaN surface showing a (1x3) pattern following an in-situ anneal at 700 C. A) <11-20> crystal direction. B) <1-100> crystal direction. [Reprinted with permission from B.P. Gila, 2000. Grow th and Characterization of Dielectric Materials for Wide Bandgap Semiconductors PhD dissertation (pg. 44, Figure 3-8). University of Florida, Gainesville, Florida.]

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76 A B Figure 3-7. Illustration of MOS capac itors that were fabricated. A) Entire design layout of all 60 diodes made from 3 mask sets. B) Bl own-up image of one of the diodes. Ohmic Pad GaN Gate Oxide

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77 Figure 3-8. Diagram of pattern in the mask used to open windows for the ohmic pad. Black region contained oxide that was etched awa y. Circular white re gion contained oxide that was protected by PR during the etching.

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78 Figure 3-9. Diagram of pattern in the mask used to deposit ohmic pad. Black region is GaN that metal is deposited on. Circular white regi on contains thin GaN ring and oxide island protected by PR.

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79 Figure 3-10. Diagram of pattern in the mask used to deposit meta l gate. Black region contains ohmic pad, thin GaN ring, and part of oxide island protected by PR. Circular white region contains part of oxide island th at metal gate is deposited on top of.

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80 A B Figure 3-11. Sketches of bi-layer photoresist stac k. A) Undercut profile of LOR 3B underneath the 1818 layer. B) Discontinuous metal film deposition due to undercut (provides ease for metal lift-off). substrate LOR 3B 1818 LOR 3B substrate 1818

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81 A B Figure 3-12. AES surface scans of as-received and etched (Sc2O3)x(Ga2O3)1-x films on GaN. A) As-received. B) 12 minute etch show s complete removal of film. 500100015002000 -2000 -1500 -1000 -500 0 500 1000 1500 2000 O Sc GadN(E)Kinetic Energy (eV)500100015002000 -800 -600 -400 -200 0 200 400 600 S C N O GadN(E)Kinetic Energy (eV)

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82 A B Figure 3-13. Dry etching of (Sc2O3)x(Ga2O3)1-x on GaN and Si along with a reference piece of GaN in a CH4/H2/Ar chemistry. A) Fixed ICP pow er (300 W) with increasing RF chuck power. B) Fixed RF chuck power (35 W) with increasing ICP power. 050100150200250300 0 50 100 150 200 250 GaN Si Ref Etch Rate (A/minute)ICP Power (W)60 80 100 120 140 160 5 CH4/ 10 H2/ 5 Ar 35 W RF DC Bias DC Bias (V)2030405060 0 50 100 150 200 250 300 350 GaN Si Ref 5 CH4/ 10 H2/ 5 ArEtch Rate (A/minute)RF Power (W)60 80 100 120 DC Bias DC Bias (V)300 W ICP

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83 A B Figure 3-14. Etch selectivity of (Sc2O3)x(Ga2O3)1-x over GaN for a CH4/H2/Ar etch chemistry. A) Fixed ICP power (300 W) with increasing RF chuck pow er. B) Fixed RF chuck power (35 W) with increasing ICP power. 050100150200250300 0 2 4 6 8 10 12 14 SelectivityICP (W)20253035404550556065 0 2 4 6 8 10 12 14 16 SelectivityRF Power (W)

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84 A B C Figure 3-15. Possible RHEED patterns. A) Amor phous diffraction pattern. B) Polycrystalline diffraction pattern. C) Single crystal diffraction pattern. [Reprinted with permission from B.P. Gila, 2000. Growth and Characteri zation of Dielectric Materials for Wide Bandgap Semiconductors. PhD dissertation (pg. 47, Figure 3-11). University of Florida, Gainesville, Florida.]

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85 Figure 3-16. An image of the penetration depth a nd interaction volume of an electron beam in a material. It shows that Auger electrons only have an escape de pth at the top 1.0 nm of the surface. [Reprinted with perm ission from B.P. Gila, 2000. Growth and Characterization of Dielectric Material s for Wide Bandgap Semiconductors. PhD dissertation (pg. 50, Figure 314). University of Florid a, Gainesville, Florida.]

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86 CHAPTER 4 GROWTH AND CHARACTERIZATION OF SCANDIUM GALLIUM OXIDE The objective of this work was to grow (Sc2O3)x(Ga2O3)1-x as an amorphous film that could be used in a stacked gate dielectric with a crysta lline oxide. Previous trends have shown that the smaller the lattice mismatch to GaN, the smaller the Dit. However, dislocation defects in the crystalline oxide (due to the lattice mismatch w ith GaN) act as current leakage paths that limit the breakdown voltage. Depositing an amorphous dielectric on top of the crystalline oxide would allow the properties of the oxide/GaN in terface to be maintained while reducing the current leakage by terminating dislocating defects in the crystalline oxide. Previous results of a stacked gate dielectric with SiO2 deposited on top of Gd2O3 showed improvement of the breakdown field from 0.3 MV/cm to 0.8 MV/cm.19,20 For (Sc2O3)x(Ga2O3)1-x to serve as a suitable dielectric in GaN-based devices, it must have a larger band gap and dielectric constant than GaN. There are no electrical properties listed for (Sc2O3)x(Ga2O3)1-x in literature, so the properties of Gd2O3, Sc2O3, and (Ga2O3)x(Gd2O3)1-x will be discussed to make predictions on the band gap and dielectric constant of (Sc2O3)x(Ga2O3)1-x. Both Sc2O3 and Gd2O3 have a bixbyite crys tal structure, but Sc2O3 has a larger band gap (6.3 eV compared to 5.3 eV) and a larger dielectric cons tant (14.0 eV compared to 11.4 eV) compared to Gd2O3. Based on the superior el ectrical properties of Sc2O3, it is believed that using Sc2O3 in place of Gd2O3 will only enhance the properties of the ternary oxide system. The band gap and dielectric constant of (Ga2O3)x(Gd2O3)1-x are 4.7 eV and 14.2 respectively, so any improvement in these values for (Sc2O3)x(Ga2O3)1-x will place them well above the values for GaN. It will also be critical for the oxide to have confinement with respect to both the valence and conduction bands of GaN. Both Gd2O3 and Ga2O3 are not confined with respec t to the valence band of GaN, but (Ga2O3)x(Gd2O3)1-x has confinement with respect to both bands of GaN. Since Sc2O3 also

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87 has confinement at both bands, it is believed that (Sc2O3)x(Ga2O3)1-x will have confinement at both bands, and the use of Sc2O3 might widen the conf inement at each band. Continuous Growth of (Sc2O3)x(Ga2O3)1-x The use of Sc and Ga in the oxide film s included two purposes. Since previous Sc2O3 films deposited at 100 C using a high Sc flux were polycryst alline, it was hopeful that adding Ga would frustrate the Sc2O3 lattice and promote amorphous fi lm growth. The second purpose was using Sc to stabilize Ga in the 3+ oxidation state. While Sc has a single oxidation state of 3+, Ga has multiple oxidation states of 3+, 2+, and 1+. It is believed th at the addition of an electropositive element in a ternary phase will stabilize the higher oxidation state for a metal with multiple oxidation states (examples include KMnO4, SrFeO4, and BaPbO3).55,56 Low substrate temperatures and high growth rates (due to high flux of material) are typically used to foster amorphous film growth in MBE. Therefore, a substrate temperature of 100 C was used, and cell temperatures of 1190 C (corresponding to a Sc2O3 growth rate of 3.2 nm/min) and 884 C (corresponding to a Ga2O3 growth rate of 2.3 nm/min) were used for Sc and Ga respectively. The RF oxygen plas ma was set at a pressure of 8.0x10-6 Torr with a forward power of 300 W. A continuous growth was used in which all three shutters were simultaneously open during the growth. During th e growth and at the end of th e growth, RHEED showed a light arc (Figure 4-1) indicative of polycrystalline film growth. Ch aracterization with TEM also showed arcs in the SAD pattern (Figure 4-2) and a HRTEM image in Figure 4-3 shows the rotation of grains in different di rections. Analysis with XRD re vealed no peaks (except for those of the GaN and sapphire), providing further evidence that a fine-gra ined polycrystalline film was present with no preferred orientation. Charact erization with AFM showed an RMS roughness of

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88 5.65 nm for a 1 m scan and an RMS roughness of 6.78 nm for a 5 m scan (Figure 4-4). The high surface roughness was associated with the extremely high growth rate of 6.0 nm/min. An AES surface scan revealed that the films were rich in Sc with a Sc to Ga peak-to-peak ratio of 2.25 (Figure 4-5a). Furthe r analysis with a depth profile revealed surface segregation of Ga (Figure 4-5b). One of the mechanisms that dr ives surface enrichment is the segregation of the species with the weakest bond.92 The segregation of Ga was attributed to the weaker bond between Ga and O compared to Sc and O. Looking at the electr onegativity values for Sc (1.2) and Ga (1.82), it can be seen th at Sc is much more electropos itive than Ga and has a higher reactivity in forming a compound with O (3.44).93 Segregation is generally eliminated by growing in a kinetically limited regime at low temperatures and high growth rates.94-96 Since the surface enrichment of Ga in (Sc2O3)x(Ga2O3)1-x occurred under these growth conditions, alternative growth techniques were inves tigated to eliminate the Ga segregation. Digital Growth of (Sc2O3)x(Ga2O3)1-x In an attempt to eliminate the segregation of Ga at the surface, a di gital growth technique was used. This technique was previously used for MgCaO to prevent the segregation of Ca.47 The digital growth involved repeatedly alterna ting the opening and closing of the Sc and Ga shutters at 10 second intervals (10:10) dur ing continuous exposure from the oxygen plasma (Figure 4-6). A polycrystalline RHEED pattern was present for th e entire growth, and no peaks appeared in the XRD scan except for peaks from the substrate. AFM showed an RMS roughness of 4.12 nm for a 1 m scan and an RMS roughness of 5.01 nm for a 5 m scan (Figure 4-7). The surface roughness was lower compared to the surf ace roughness for the continuous growth. This was attributed to the lower grow th rate of 3.0 nm/min compared to the 6.0 nm/min growth rate

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89 for the continuous growth. The AES depth profil e in Figure 4-8 shows that the digital growth technique did not eliminate the se gregation of Ga at the surface of the films. Growth with Closure of Ga Shutter A third growth technique was employed which involved closing the Ga shutter towards the end of the growth for a certain amount of tim e while the Sc and O shutters remained open continuously (Figure 4-9). This technique was previously employe d to eliminate the segregation of In in the growth of InGaN.97 The oxygen pressure was also increased to 1.2x10-5 Torr to increase the VI/III ratio. Vari ous times were investigated to determine the optimal time that would successfully eliminate the surface enrichment of Ga. Table 4-1 and Figure 4-10 show that the Sc:O and Sc:Ga ratios increase with increasi ng time that the Ga shutter was closed towards the end of the growth, and the Ga:O ratio decreases with increasing time. It was determined that closing the Ga shutter for the final 90 seconds of a 6 minute growth successfully eliminated the segregation of Ga (Figure 4-11). It can also be seen in the de pth profile that the intensities of the Sc and O increase and the intensity of the Ga decreases at the oxide/GaN in terface. This same effect was also present in samples with (Sc2O3)x(Ga2O3)1-x on Si (Figure 4-12). Further an alysis with HRTEM showed a very thin, faint line at the interface (Figures 4-13 ). This same occurrence was seen in a HRTEM cross-sectional image of (Ga2O3)x(Gd2O3)1-x on GaAs.98 The thin layer on GaAs (2-3 monolayers) was identified as single crystal Gd2O3. The initial formation of a Gd2O3 layer was attributed to Gd (electronega tivity of 1.2) having a higher reac tivity with oxygen and being more electropositive compared to Ga (electrone gativity of 1.82). Since Sc has the same electronegativity value as Gd and has a much gr eater value than Ga, it appears that a similar trend is present in the (Sc2O3)x(Ga2O3)1-x film with the thin layer at the interface representing Sc2O3 (Figure 4-14).

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90 Characterization with AFM revealed an RMS roughness of 2.98 nm for a 1 m scan and an RMS roughness of 3.79 nm for a 5 m scan (Figure 4-15). The large surface roughness was a result of the high 5.5 nm/min growth rate. However, the surface roughness was lower compared to the surface roughness for the c ontinuous and digital growths. This was attributed to the elimination of the Ga surface segregation.99 Electrical Testing of (Sc2O3)x(Ga2O3)1-x After fabricating MOS capacitors, currentvoltage (I-V) measurements were taken to determine the breakdown voltage. Figure 4-16 shows that the (Sc2O3)x(Ga2O3)1-x film (33 nm) has a poor breakdown field of 0.15 MV/cm at 1 mA/cm2. The leakage current is so high that the oxide appears to be more of a conductor. Th e low breakdown field is indicative of a mode A failure, which is due to defects or pinholes in the oxide or defects at the oxide/semiconductor interface. The film was analyzed further with XPS to determine the root cause of the premature breakdown. The National Institute of Standards and Technology (NIST) XPS database100 was used to reference the characteristic bindi ng energies of all the possible chemical species present in the (Sc2O3)x(Ga2O3)1-x film (Table 4-2). The obj ective of the XPS analysis was to determine if free Ga or Sc metal was present in the film that coul d act as a dopant atom and create an electrical pathway between the metal gate and GaN substrate. Figures 4-17 to 4-19 indicate the presence of both Ga2O3 and Ga metal phases. A 6 eV difference between the two phases is seen for the Ga LMM (Auger) energy level, a nd a 2 eV difference between th e two phases is seen for both the Ga 2p3/2 and 3d energy levels. Analysis of the Sc 2p3/2 energy level (Figure 4-20) revealed that only the Sc2O3 phase is present. A peak at 401.9 eV corresponding to Sc2O3 is present, but

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91 no peak appears at 398.3 eV, which is indicative of Sc metal. It can be seen from the XPS data that the free Ga metal presen t in the film was responsible for the poor breakdown field. After determining the root cause of the breakdown, (Sc2O3)x(Ga2O3)1-x films were grown at lower Ga cell temperatures to eliminate the free Ga metal present in the oxide. The Sc cell temperature was also reduced to make more O atoms available to the Ga atoms and to reduce the overall metal to oxygen ratio, which was higher than desired. Table 4-3 shows that the breakdown voltage increases as the Ga cell te mperature decreases. However, the breakdown voltages were still poor. Be low a cell temperature of 675 C, Ga was no longer detected in the films using AES. Current-voltage measurements were also taken for digital and continuous films grown at various combinations of high and lo w Ga and Sc cell temperatures, but the breakdown fields were all lower than 0.5 MV/cm. B ecause of the poor breakdown voltages for the (Sc2O3)x(Ga2O3)1-x films, no C-V measurements were made. It does not appear that (Sc2O3)x(Ga2O3)1-x is a feasible dielectric for GaN-based devices. Previous results with (Gd2O3)x(Ga2O3)1-x on GaAs revealed that the breakdown field strength increased as the films became richer in Gd.55,56 A film with a Gd concentration of 14% had a breakdown field of ~1.9 MV/cm, and the breakdo wn field increased to 2.5 MV/cm with an increase in the Gd concentration to 20%. Howe ver, the best results we re obtained with a pure Gd2O3 film as it had an even highe r breakdown field of 3.5 MV/cm. It appears that this same trend is present for (Sc2O3)x(Ga2O3)1-x as films with increasing am ounts of Sc exhibited higher breakdown fields with a pure Sc2O3 film having the highest brea kdown field (~2.70 MV/cm). It is believed that the incorporation of Ga into th e films creates defects that diminish the insulating properties of the oxide.

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92 Table 4-1. Auger peak-to-peak ratios for Ga:O, Sc:O, and Sc:G a as function of the amount of time that the Ga shutter was closed towards the end of the growth. Ga shutter closure time (sec) Ga:O Sc:O Sc:Ga 0 0.21 0.48 2.25 30 0.18 0.54 3.10 45 0.14 0.56 3.90 60 0.11 0.59 4.44 75 0.11 0.60 5.38 90 0.11 0.61 5.66 120 0.08 0.65 7.96

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93 Table 4-2. Characteristic binding energies of possibl e phases present in (Sc2O3)x(Ga2O3)1-x. Element Spectral Line Phase Binding Energy (eV) Ga LMM (Auger) Ga2O3 191.2 Ga LMM (Auger) Ga 185.3 Ga 2p3/2 Ga2O3 20.5 Ga 2p3/2 Ga 18.5 Ga 3d Ga2O3 1117.8 Ga 3d Ga 1116.5 Sc 2p3/2 Sc2O3 401.9 Sc 2p3/2 Sc 398.3

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94 Table 4-3. Breakdown voltage as a function of decreasing Ga cell temperature. Sample TGa ( C) TSc ( C) tox (nm) G (nm/min) Vbd (MV/cm) at 1 mA/cm2 1 865 1190 33 5.5 0.15 2 770 1180 47 2.4 0.70 3 750 1180 42 2.1 1.00 4 725 1180 40 2.0 1.40

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95 Figure 4-1. RHEED image of (Sc2O3)x(Ga2O3)1-x on GaN during and after growth.

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96 Figure 4-2. TEM SAD pattern of (Sc2O3)x(Ga2O3)1-x on GaN.

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97 Figure 4-3. HRTEM image of (Sc2O3)x(Ga2O3)1-x on GaN. GaN (Sc2O3)x(Ga2O3)1-x

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98 A B Figure 4-4. AFM images of (Sc2O3)x(Ga2O3)1-x on GaN for a continuous growth. A) 1 m scan with RMS roughness of 5.65 nm. B) 5 m scan with RMS roughness of 6.78 nm. 1.0m 200nm

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99 A B Figure 4-5. AES analysis of continuous growth for (Sc2O3)x(Ga2O3)1-x on GaN. A) Surface scan. B) Depth profile. 500100015002000 -3000 -2000 -1000 0 1000 2000 Sc O GadN(E)Kinetic Energy (eV)020406080 0 10000 20000 30000 40000 50000 60000 70000 80000 Ga Ga N O ScCounts (A.U.) Cylces

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100 Figure 4-6. Diagram of a digital gr owth technique in which the Sc and Ga shutters are alternated for a given time sequence while the oxyge n shutter is open continuously throughout the entire growth. Sc Ga O t

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101 A B Figure 4-7. AFM images of (Sc2O3)x(Ga2O3)1-x on GaN for a digital growth. A) 1 m scan with RMS roughness of 4.12 nm. B) 5 m scan with RMS roughness of 5.01 nm. 1.0m 200nm

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102 A B Figure 4-8. AES analysis of digital growth for (Sc2O3)x(Ga2O3)1-x on GaN. A) Surface scan. B) Depth profile. 500100015002000 -2000 -1500 -1000 -500 0 500 1000 1500 2000 Sc Ga OdN(E)Kinetic Energy (eV)0102030405060 0 20000 40000 60000 80000 Sc O N Ga GaCounts (A.U.)Cycles

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103 Figure 4-9. Diagram of growth technique in which th e Ga shutter is closed towards the end of the growth for a designated amount of time while the Sc and O shutters are open continuously. t Sc Ga O

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104 A B Figure 4-10. Change in Auger peak -to-peak ratios as a function of the amount of time that the Ga shutter is closed towards the end of grow th. A) Sc:Ga. B) Ga:O and Sc:O. 0.00.51.01.52.0 2 3 4 5 6 7 8 Sc:Ga ratioPeak-to-Peak RatioGa Shutter Closure Time (sec)0.00.51.01.52.0 0 1 Ga:O ratio Sc:O ratioPeak-to-Peak RatioGa Shutter Closure Time (sec)

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105 A B Figure 4-11. AES analysis of growth with Ga shutter closure for (Sc2O3)x(Ga2O3)1-x on GaN. A) Surface scan. B) Depth profile. 500100015002000 -3000 -2000 -1000 0 1000 2000 3000 Sc Ga OdN(E)Kinetic Energy (eV)010203040506070 0 20000 40000 60000 80000 N O O Sc Sc Ga GaCounts (A.U.)Cycles

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106 Figure 4-12. AES depth profile of grow th with Ga shutter closure for (Sc2O3)x(Ga2O3)1-x on Si. 020406080 0 10000 20000 30000 40000 50000 Si Ga O ScCountsCycles

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107 Figure 4-13. Low magnification cr oss-section TEM image of (Sc2O3)x(Ga2O3)1-x on GaN with a thin Sc2O3 layer at the GaN/oxide interface. GaN (Sc2O3)x(Ga2O3)1-x Sc2O3 Pt

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108 Figure 4-14. High magnification cr oss-section TEM image of (Sc2O3)x(Ga2O3)1-x on GaN with a thin Sc2O3 layer at the GaN/oxide interface. GaN (Sc2O3)x(Ga2O3)1-x Sc2O3

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109 A B Figure 4-15. AFM images of (Sc2O3)x(Ga2O3)1-x on GaN for a growth with the Ga shutter closed towards the end. A) 1 m scan with RMS roughness of 2.98 nm. B) 5 m scan with RMS roughness of 3.79 nm. 1.0m 200nm

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110 Figure 4-16. Current-voltage (I-V) plot of (Sc2O3)x(Ga2O3)1-x film deposited at 100 C. Film stoichiometry was rich in Sc. -1.0-0.50.00.51.0 -1.00E-007 -5.00E-008 0.00E+000 5.00E-008 1.00E-007 Current (A)Voltage (V)

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111 Figure 4-17. Ga LMM level shows a 6 eV difference between the Ga2O3 and Ga metal peaks. 194192190188186184182 10000 12000 14000 16000 18000 20000 22000 Ga2O3GaCounts (A.U.)Binding Energy (eV) 6 eV

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112 Figure 4-18. Ga 2p3/2 level shows a 2 eV difference between the Ga2O3 and Ga metal peaks. 11211120111911181117111611151114 120000 140000 160000 180000 200000 Ga Ga2O3Counts (A.U.)Binding Energy (eV) 2 eV

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113 Figure 4-19. Ga 3d level shows a 2 eV difference between the Ga2O3 and Ga metal peaks. 262422201816 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 O 2s Ga Ga2O3Counts (A.U.)Binding Energy (eV) 2 eV

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114 Figure 4-20. Sc 2p3/2 level only shows the presence of a Sc2O3 phase. 408406404402400398 20000 30000 40000 50000 60000 70000 2p1/22p3/2Counts (A.U.)Binding Energy (eV)

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115 CHAPTER 5 OPTIMIZATION OF MAGNESIUM OXDE Previous results with MgO showed the best electrical results (i.e., 4.4 MV/cm breakdown field and Dit value of 1x1011 eV-1cm-2) at low oxygen pressures (hi gh Mg to O ratio) and high growth rates.38 However, further optimization is needed to make the films more environmentally and thermally stable. Films grown at higher grow th rates show deterioration in air after a few days and etch in DI water within 10 seconds. Considering the number of processing steps that require a DI rinse and the fact that most developers are water based (i.e., AZ 300 MIF developer is 97.5% water), it is essential to find a set of growth parameters to improve the environmental stability of MgO. MgO Growth at Low Growth Rates and Oxygen Pressures Utilizing both lower growth rates (<1.3 nm/min) and oxygen pressures (<5x106 Torr and Mg:O ratio of 0.68) improved the environmen tal stability immensely. Films showed no deterioration in air over a period of a few mont hs, and fabricated MOS capacitors maintained breakdown fields greater than 3.5 MV/cm (at 1 mA/cm2) after receiving a variety of wet processing treatments. The wet treatments included DI water, AZ 300 MIF developer, and PG remover (Table 5-1) since thes e are the common wet chemicals th at samples are treated with during processing. Sixty diodes from an as-receiv ed MgO sample were measured, and then the sample was cleaved into 3 separate pieces w ith each piece receiving one of the three wet treatments. A 1 minute rinse in DI water showed no etching or degrading of the MgO film as the tested diode had a forward breakdown volta ge of 14.9 V (3.82 mV/cm) at 1 mA/cm2 before the treatment and 14.8 V (3.79 MV/cm) after the treatme nt (Figure 5-1). A 3 minute treatment in developer also revealed no dete rioration of the MgO film as the tested diode had a forward breakdown voltage of 14.1 V (3.62 MV/cm) at 1 mA/cm2 before the treatment and 14.5 V (3.72

PAGE 116

116 MV/cm) after the treatment (Figure 5-2). A 10 minute treatment in PG remover showed no effect on the MgO film as the measured diode had a forward breakdown voltage of 14.1 V (3.62 MV/cm) at 1 mA/cm2 before the treatment and 13.8 V (3.54 MV/cm) after the treatment (Figure 5-3). Despite the improved environmental stab ility, MgO is not thermally stabile as high temperature anneals (1000 C for 2 minutes) cause degradatio n due to increased surface and interfacial roughnesses.41 The addition of a Sc2O3 cap has been shown to provide thermal stability, but the use of the cappi ng layer adds an additional proces sing step since it must be dry etched prior to wet etch removal of the MgO layer.32 This provided motivation to determine if the addition of Sc to MgO (MgxScyOz was formed) could increase the environmental and thermal stability of the film. Results of MgxScyOz Previous results revealed that MgxScyOz degraded and etched at a much slower rate than MgO, but significant degradat ion occurred after annealing.101 Since the previous MgxScyOz films were grown at high oxygen pressures and growth rates, it was hopeful that lower oxygen pressures and growth rates could enhance the stabili ty of the film as these growth conditions did for MgO. The electrical results of MgxScyOz were also investigated to determine if any improvements are made in the breakdown voltage, flatband voltage shift, or Dit with the addition of Sc to MgO. Three separate films were deposited on uGaN using a substrate temperature of 100 C, an oxygen pressure less than 4x10-6 Torr, a Mg cell temperature of 340 C (corresponds to 1.3 nm/min MgO growth rate), and increasing Sc cell temperatures of 1090 C, 1135 C, and 1180 C (corresponds to Sc2O3 growth rate of 1.1 nm/min). The growth with the Sc cell temperature at 1090 C yielded a growth rate of 1.47 nm/m in with a film thickness of 43.7 nm.

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117 Figure 5-4 shows that the film had a fo rward breakdown voltage of 15.7 V (3.59 MV/cm breakdown field) at 1 mA/cm2. Thirty six out of 60 diodes we re tested, and 10 of the 36 (28 %) diodes had a breakdown voltage greater than 10 V. A Dit of 4.0x1011 eV-1cm-2 was calculated at 0.4 eV below the conduction band using the Terman method. Despite the good breakdown voltage and Dit, the film had an extremely high flatband voltage shift of 5.30 V at a frequency of 10 kHz (Figure 5-5). Besides the presence of fixed oxide charge (Qox) and interface trapped charge (Dit), oxide trapped charge (Qot) was also present from the la rge applied gate bias of 12 V (wide scanning range from 12 to 0 V was used to obtain distinct accumulation and depletion regions). When using the same frequency and sc anning rate but applying a smaller gate bias of 10 V (scanning range was from 10 V to 2 V), a lower flatband voltage shift of 4.65 V was obtained. Given the flatband voltage shift difference of 0.65 V between the two scans, it appears that the larger bias in jected more carriers into the oxide (F igure 5-6). Since a positive flatband voltage shift indicates the accumula tion of negative charges in the oxide, it appears that the large positive bias injected electrons from the semiconductor into the oxide.89 The deposition with the Sc cell temperature at 1135 C had a growth rate of 1.84 nm/min with a film thickness of 55.1 nm. A forw ard breakdown voltage of 22.0 V (3.99 MV/cm breakdown field) was obtained at 1 mA/cm2 (Figure 5-7). Thirty five out of 60 diodes were tested, and 17 of the 35 (48%) diodes had a breakdown voltage greater than 20 V. A Dit of 2.2x1011 eV-1cm-2 was calculated at 0.4 eV below the conduction band using the Terman method. The film had a large flatband voltage shift of 4.35 V at a frequency of 10 kHz, and a small hump was present in the C-V curve between 2 V and 4 V (Figure 5-8). The hump is indicative of a specific trap in the oxide that could be a resu lt of a defect incurred dur ing sample preparation from one of the cleaning steps or from In mounting the sample. It is also possible that the solid

PAGE 118

118 solubility limit of Sc in MgO was reached unde r these growth conditions, and the formation of two phases (MgO and Sc2O3) led to the creation of a trap. A lower flatband voltage shift of 3.89 V was obtained by using a scanning range with a sm aller gate bias of 10 V (sweep from 10 V to 0 V). The 0.46 V difference between the two scans was once again an indica tor of trapped oxide charge present in the film as the scan using the la rger bias injected more carriers into the oxide. The film deposited with a Sc cell temperature at 1180 C produced a growth rate of 2.26 nm/min with a film thickness of 67.7 nm. A forward breakdown voltage of 26.7 V (3.94 MV/cm breakdown field) was achieved at 1 mA/cm2 (Figure 5-9). Twenty seven out of 60 diodes were tested, and 14 of the 27 (52%) diodes had a breakdown voltage greater than 25 V. A Dit of 1.0x1011 eV-1cm-2 was calculated at 0.4 eV below the conduction band using the Terman method. A flatband voltage shift of 3.83 V was obtained at a frequency of 10 kHz, and a small hump was also present in the C-V curve between 1 V and 3 V (Figure 5-10). A lower flatband voltage shift (VFB = 2.91 V) was obtained once again by using a sw eep range with a lower applied gate bias (sweep from 10 V to 0 V). All three MgxScyOz films had breakdown fields greater than 3.5 MV/cm and Dit values in the low 1011 eV-1cm-2 range, but they also had flatband voltage shifts of ~3 V or greater (Table 52). Given the different valences of Sc (3+) and Mg (2+) and the different crystal structures and lattice constants for MgO and Sc2O3, it is expected that the two would have a low solid solubility. It is believed th at the low solubility of the two compounds and mixed valences generate a large number of defect s within the oxide that are re sponsible for the large flatband voltage shift. The previous trend with MgO showed that better electrical results (Vbd and Dit) were obtained at higher Mg:O ratios.38 This same trend is apparent for the MgxScyOz films as the

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119 flatband voltage shift and Dit decreased with increasing metal to oxygen ratio due to the increasing Sc cell temperature at constant oxygen pressure and Mg cell temperature (Figure 511). Although the films showed high breakdown fields and low Dit values, the large flatband voltage shifts make MgxScyOz a poor dielectric to use on GaN. Because of the large flatband voltage shifts, the thermal and environmental stab ility of the films at the new growth conditions were not investigated.

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120 Table 5-1. Breakdown fiel d values (at 1 mA/cm2) of tested diodes before and after various wet processing treatments. Wet treatment Vbd (MV/cm) at 1 mA/cm2 Vbd (MV/cm) at 1 mA/cm2 before treatment after treatment 1 min DI H2O 3.82 3.79 3 min developer 3.62 3.72 10 min PG remover 3.62 3.54

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121 Table 5-2. Electrical results for MgxScyOz films on GaN for increasing Sc cell temperatures. Parameter MgxScyOz MgxScyOz MgxScyOz (TSc =1090 C) (TSc =1135 C) (TSc =1180 C) tox (nm) 43.7 55.1 67.7 G (nm/min) 1.47 1.84 2.26 Vbd (MV/cm) 3.59 3.99 3.94 at 1 mA/cm2 Dit (eV-1cm-2) 4.0x1011 2.2x1011 1.0x1011 at Ec-0.4 eV VFB (V) 5.30 4.35 3.83 Diodes tested 36/60 (60%) 35/60 (58%) 27/60 (45%) Diodes > 10 V 10/36 (28% ) ---------------------------------Diodes > 20 V ----------------17/35 (48%) -----------------Diodes > 25 V --------------------------------14/27 (52%)

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122 Figure 5-1. Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 1 minute DI water treatment. Breakdown field was 3.82 MV/cm at 1 mA/cm2 before the treatment and 3.79 MV/cm after the treatment. Compliance was 100 nA. -20-10010 -1.00E-007 -5.00E-008 0.00E+000 5.00E-008 1.00E-007 As-received 1 min DI H2O treatmentCurrent (A)Voltage (V)

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123 Figure 5-2. Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 3 minute treatment in developer. Breakdow n field was 3.62 MV/cm at 1 mA/cm2 before the treatment and 3.72 MV/cm after the treatment. Compliance was 100 nA. 02468101214 0.00E+000 2.00E-008 4.00E-008 6.00E-008 8.00E-008 1.00E-007 As-received 3 min Developer treatmentCurrent (A)Voltage (V)

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124 Figure 5-3. Current-voltage (I-V) plot of MgO film (39 nm thick) before and after a 10 minute treatment in PG remover. Breakdown field was 3.62 MV/cm at 1 mA/cm2 before the treatment and 3.54 MV/cm after the treatment. Compliance was 100 nA. 0246810121416 0.00E+000 2.00E-008 4.00E-008 6.00E-008 8.00E-008 1.00E-007 As-received 10 min PG Remover treatmentCurrent (A)Voltage (V)

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125 Figure 5-4. Current-vol tage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1090 C. Breakdown field was 3.59 MV/cm at 1 mA/cm2 for a film thickness of 43.7 nm. Compliance was 100 nA. -20-10010 -1.00E-007 -5.00E-008 0.00E+000 5.00E-008 1.00E-007 Current (A)Voltage (V)

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126 Figure 5-5. Capacitancevoltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1090 C. Flatband voltage shift of 5.30 V and Dit of 4.0x1011 eV-1cm-2 was calculated from the C-V curve taken at a frequency of 10 kHz. 024681012 0.00E+000 2.00E-012 4.00E-012 6.00E-012 8.00E-012 1.00E-011 1.20E-011 1.40E-011 Capacitance (F)Voltage (V)

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127 Figure 5-6. Capacitance-volta ge plot of two different scanning ranges for a MgxScyOz film on uGaN at a Sc cell temperature of 1090 C. Flatband voltage shift difference of 0.65 V appears between the two curves with different applied gate biases. 024681012 0.00E+000 2.00E-012 4.00E-012 6.00E-012 8.00E-012 1.00E-011 1.20E-011 1.40E-011 10 to 2 V scan 12 to 0 V scanCapacitance (F)Voltage (V)

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128 Figure 5-7. Current-vol tage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1135 C. Breakdown field was 3.99 MV/cm at 1 mA/cm2 for a film thickness of 55.1 nm. Compliance was 100 nA. 0510152025 0.00E+000 2.00E-008 4.00E-008 6.00E-008 8.00E-008 1.00E-007 Current (A)Voltage (V)

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129 Figure 5-8. Capacitancevoltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1135 C. Flatband voltage shift of 4.35 V and Dit of 2.2x1011 eV-1cm-2 was calculated from the C-V curve taken at a frequency of 10 kHz. 024681012 0.00E+000 2.00E-012 4.00E-012 6.00E-012 8.00E-012 1.00E-011 Capacitance (F)Voltage (V)

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130 Figure 5-9. Current-vol tage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1180 C. Breakdown field was 3.94 MV/cm at 1 mA/cm2 for a film thickness of 67.7 nm. Compliance was 100 nA. 051015202530 0.00E+000 2.00E-008 4.00E-008 6.00E-008 8.00E-008 1.00E-007 Current (A)Voltage (V)

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131 Figure 5-10. Capacitance-voltage plot of MgxScyOz film on u-GaN at Sc cell temperature of 1180 C. Flatband voltage shift of 3.83 V and Dit of 1.0x1011 eV-1cm-2 was calculated from the C-V curve taken at a frequency of 10 kHz. 0246810120.00E+000 2.00E-012 4.00E-012 6.00E-012 8.00E-012 1.00E-011 Capacitance (F)Voltage (V)

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132 Figure 5-11. Normalized capacita nce-voltage (C-V) plots of MgxScyOz films on GaN at Sc cell temperatures of 1090 C, 1135 C, and 1180 C. 024681012 0.0 0.2 0.4 0.6 0.8 1.0 TSc= 1180 oC, TMg= 150 oC TSc= 1135 oC, TMg= 150 oC TSc= 1090 oC, TMg= 150 oCC/CoxVoltage (V)

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133 CHAPTER 6 METALLIZATION STUDY WITH MAGNESIUM OXIDE The processing scheme for fabrication of a MOS capacitor (discussed in chapter 2) includes oxide deposition prior to deposition of ohmic metal pa ds. The disadvantage of this sequence of steps is that the oxide is annealed at extremel y high temperatures (i.e., >750 C in RTA) during the ohmic anneal. High temperatur e annealing of MgO cause s deterioration of the MgO/GaN interface and the oxide itself.41 This problem could be avoided if the sequence of steps was reversed so that the ohmic metal pads are deposited prior to oxide deposition. Besides maintaining the stability of the oxide, the change in the processing scheme would provide other important advantages as well. Prior to ohmic metal deposition, it is extremel y important to remove residual PR from the exposed ohmic windows on the substrate surface si nce it can effect the contact resistance and possibly lead to removal of the ohmic pad during metal lift-off. Most cleaning steps include an oxygen treatment to remove the residual PR, follo wed by a wet treatment (i.e., BOE or HCl) to remove the native oxide formed on the substrat e surface from the oxygen tr eatment. With the current processing scheme, no cleaning treatment is applied to the GaN surface prior to ohmic metal deposition. This is done to avoid etchi ng or degrading the oxide (covered by PR from patterning for ohmic metallization) during the wet treatment to remove the native oxide. Considering that MgO etches in a 2% H3PO4 solution in 10 seconds, a 3 minute wet treatment with BOE or HCl would severely degr ade and etch the oxide. Depositing the ohmic pads before oxide deposition would allow the GaN surface to be thoroughly cleaned prior to metal deposition since there would be no oxide present that could be affected by the wet treatment.

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134 Another advantage of depositing the ohmic pads prior to oxide deposition would be the simultaneous annealing of the pads and cleaning of the GaN surface. The current GaN surface pre-treatment procedure includes a 700 C in-situ anneal for 10 minutes before the sample is cooled to the desired substrate temperature for oxide deposition. Since the MBE system is at such a low pressure (i.e., 5x10-9 Torr), the same ohmic contact that is annealed in the RTA (at 760 Torr) at >750 C can be adequately annealed at lower temperatures in the MBE system. The MBE system also provides a much cleaner envir onment for annealing. An advantage for p-type GaN is that the activation anneal can be perfor med at the same annealing temperature as that used for the ohmic contacts and GaN surface clea ning treatment. Being able to perform all of these functions in one step would eliminate extr a steps in the fabricat ion process and provide higher throughput. If the processing scheme is changed so that the ohmic metallization is completed before deposition of the oxide, two critical factors must be met. The first factor is that a surface treatment procedure must be found that can eff ectively clean the GaN su rface without affecting the ohmic contact. Poor cleaning of the GaN surface could lead to a high Dit value and influence the overall quality of the growing film. Typical wet treatments that are used to degrease the substrate surface and remove the native oxide from the surface could lead to etching or degradation of the ohmic contact. The second fa ctor is that a surface treatment must be found that will produce comparable electrical results (i.e., Dit, VFB, and Vbd) with the results previously achieved using the old processing scheme with oxi de deposition prior to ohmic metallization. It is extremely important to find a suitable surfac e treatment since the cu rrent processing scheme for the fabrication of an enhancement mode MOSFET includes ohmic metallization prior to oxide deposition.

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135 Metallization Study on u-GaN Using the new processing scheme, a metallization study was performed on u-GaN (ND~5x1016 cm-3 measured by Hall) with deposition of MgO. Cleaning of the GaN surface prior to ohmic metallizati on included a 25 min UV-O3 treatment followed by a 5 min BOE treatment. After ohmic metal deposition, metal lift-off wa s performed to remove the excess metal and obtain the patterned ohmic pads. Multiple surface cleaning pre-treatments were then used to determine the one with the best electrical characte ristics. Electrical resu lts of the various surface treatments were also compared to the surface treatment that was used in the old processing scheme (standard: 3 min HCl:H2O (1:1), 25 min UV-O3, and 5 min BOE). The following surface treatments were analyzed: 1) 25 min UV-O3, 2) 25 min UV-O3 + 10 min NH4OH, 3) 25 min UV-O3 + 1 min BOE, and 4) 25 min UV-O3 + in-situ anneal at 700 C for 10 min under an N2 plasma. Treatment of the surface with only UV-O3 excluded the use of wet chemicals to remove any possibility of them having an effect on the ohmic contacts. The application of wet treatments such as NH4OH and BOE were used to remove as much of the native oxide formed from the UV-O3 treatment without damaging the ohmic pads. The fourth treatment included the use of an N2 plasma to form volatile species at the surface that would desorb from the surface during the in-situ anneal. The MgO thin films were deposited at a substrate temperature of 100 C, an Mg cell temperature of 340 C, and an oxygen pressure less than 5x10-6 Torr. All of the samples had a th ickness of 39.0 nm, corresponding to a growth rate of 1.3 nm/min. The sample with the UV-O3 treatment had a breakdown voltage of 15.3 V (3.92 MV/cm) at 1 mA/cm2 (Figure 6-1). Sixty MOS capacitors were tested with 33 out of 60 (55 %) having breakdown voltages greater than 10 V. A Dit of 2.0x1011 eV-1cm-2 was calculated at 0.4 eV below the conduction band using the Terman method. A flatband voltage shift of 0.46 V was

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136 calculated from the C-V curve in Figure 6-2. Th e flatband voltage shift was a result of the metal-semiconductor work function difference (calculated as ms = 1.43 eV assuming a work function of 5.6 eV for platinum ), interface tra pped charge (Dit), and fixed oxide charge (Qox). The fixed oxide charge was attributed to possible dangling bonds at the GaOx/MgO interface that were formed during oxidation of the GaN surface from the UV-O3 treatment or possible dangling bonds present at grain boundaries or dislocations in the MgO film. The sample with the UV-O3 and NH4OH treatment included the use of a wet treatment in an attempt to remove the native oxide formed from the UV-O3 step. It had a breakdown voltage of 15.7 V (4.02 MV/cm) at 1 mA/cm2 (Figure 6-3). Sixty diodes we re tested with 39 out of the 60 diodes (65%) having a breakdown voltage greater than 10 V. A Dit of 1.8x1011 ev-1cm-2 at 0.4 eV below the conduction band was calculated us ing the Terman method. A flatband voltage shift of 0.63 V was calculated from the C-V curve in Figure 6-4. Since this value is comparable to the value obtained from the sample with only the UV-O3 treatment, it is believed that the NH4OH treatment was not successful in removing the native oxide layer formed from the UVO3. The combination of a UV-O3 and BOE treatment was then used since BOE is commonly used to strip the native oxide from the GaN su rface. However, a short BOE treatment of only 1 minute was used since longer periods of time can l ead to degradation or co mplete removal of the ohmic pads. The sample with this treatmen t had a breakdown voltage of 14.4 V (3.69 MV/cm) at 1 mA/cm2 (Figure 6-5). Sixty diodes were measur ed with 32 out of 60 diodes (53%) having a breakdown voltage greater than 10 V. A Dit of 2.0x1011 eV-1cm-2 was calculated at 0.4 eV below the conduction band using the Terman method. A flatband voltage shift of 0.64 V was determined using the C-V curve in Figure 6-6. Gi ven the comparable flatband voltage shift with

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137 the previous two surface pre-trea tments, it is believed that th e 1 min BOE treatment was unable to remove the native oxide layer formed from the UV-O3 treatment. It is desirable to use a longer BOE treatment, but that could l ead to damage of the ohmic contacts. The sample treated with UV-O3 and an in-situ anneal under an N2 plasma produced a breakdown voltage of 14.9 V (3.82 MV/cm) at 1 mA/cm2 (Figure 6-7). Sixty MOS capacitors were measured with 38 out of 60 (63%) having a breakdown voltage greater than 10 V. A Dit of 2.0x1011 eV-1cm-2 was calculated at 0.4 eV below the conduction band using the Terman method. A flatband voltage shift of 0.41 V was determin ed from the C-V curve in Figure 6-8. All four surface pre-treatments had breakdown fi elds of ~3.70 MV/cm or greater (Figure 69 and Table 6-1), Dit values around 2.0x1011 eV-1cm-2, and flatband voltage shifts of 0.63 V or less (Figure 6-10). Looking at the ohmic contact s for each sample under an optical microscope revealed that the contacts were not damaged by a ny of the treatments. It appears that the pretreatment with the in-situ N2 plasma anneal is the best surf ace treatment since it yielded the lowest flatband voltage shift. However, all of th e electrical values were representative of the best MOS capacitor from each sample and do no t represent the entire sampling set. More capacitors would need to be fabricated and tested to determine a specific trend as to which pretreatment offers the best starti ng surface to grow on. The difference in the flatband voltage shifts among the samples is also within the error of the measurement and ca lculations used in determining the value. Electrical values for the sta ndard surface pre-treatment were taken from a different GaN wafer in which MgO was deposited prior to ohm ic metal deposition. The values included a breakdown field of 3.67 MV/cm, a Dit of 1.0x1011 ev-1cm-2 at 0.4 eV below the conduction band, and a flatband voltage shift of 0.18 V. Since the results are compar able to the electrical results

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138 obtained from the samples with the different su rface pre-treatments, the new fabrication scheme is a feasible process for fabricating future MOS capacitors and e-mode MOSFETs. Electrical Results on p-GaN A similar study was performed on p-GaN (NA~4x1017 cm-3 measured by Hall) with deposition of MgO. However, a suitable ohmic c ontact was not available that could be annealed in-situ at 700 C for 10 min. Metal stacks of Ni/Au and Pt/Au were researched, but the in-situ anneal caused deterioration of the contacts and ex tremely high contact resistances (Figure 6-11). Without the availability of a suitable ohmic contact for the in-situ anneal, the study was performed by preparing (incl udes sample cleaning and moun ting) and growing on samples without ohmic metal. However, two different su rface treatments, which could be used if ohmic metal was present on p-GaN prior to sample prep aration and growth, were analyzed for their feasibility. The following surf ace pre-treatments on p-GaN were used in comparison to the standard pre-treatment (3 min HCl:H2O (1:1), 25 min UV-O3, and 5 min BOE): 1) 25 min UVO3 and 2) 25 min UV-O3 + 1 min BOE. Following sample preparation, the MgO thin films were deposited at a substrate temperature of 100 C, a Mg cell temperature of 340 C, and an oxygen pressure less than 5x10-6 Torr. Metal gates (Pt/Au) were th en sputter depos ited, and In metal was soldered along the edge of the sample to make an ohmic contact to the p-GaN. Since all three samples were grown simultaneously, they had the same thickness of 37.6 nm, which corresponded to a growth rate of 1.25 nm /min. The sample with the standard surface treatment had a breakdown voltage of -15.9 V (4.23 MV/cm) at 1 mA/cm2 (Figure 6-12). Thirty out of 60 diodes were tested with 12 out of the 30 diodes (40%) having a breakdown voltage less than -10 V. The C-V curve in Figure 6-13 s hows distinct regions of accumulation and deep depletion as the gate voltage is swept from ne gative to positive voltages at a frequency of 10

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139 kHz. The broad curve is obtained because of the large bias range that was used to deplete the high density of carriers (apparent carrier concentration was measured as 1.5x1018 cm-3 from C-V curve). These C-V results are in contrast to previous C-V results for p-GaN MOS capacitors with SiO2 as the dielectric. Previous results revealed a curve more representative of results for an n-GaN MOS capacitor as the curve showed an increasing capacitance as the gate bias was swept from negative to positive voltages.102 The C-V curve obtained in this study is the typical curve that would be expected for a p-GaN MOS capacitor. The other two surface treatments yielded sim ilar electrical results. The sample that received the surface pre-treatment with UV-O3 and BOE had a breakdown voltage of -13.4 V (3.56 MV/cm) at 1 mA/cm2 (Figure 6-14). Thirty out of 60 diode s were tested with 17 out of the 30 diodes (56 %) producing breakdown voltages less than -10 V. The C-V curve in Figure 6-15 (measured at 10 kHz) shows distinct regions of accumulation and deep depletion. The MgO sample with only the UV-O3 pre-treatment had a breakdown voltage of -13 V (3.46 MV/cm) at 1 mA/cm2 (Figure 6-16). Thirty out of 60 diodes were tested with 15 out of the 30 diodes (50%) having a breakdown voltage less than -10 V. The measured C-V curve (Figure 6-17) showed the same trend as the other two samples with dist inct accumulation and deep depletion regions over a wide bias range (-8 V to 7 V). After comparing the electrical results from th e three different surface pre-treatments, it appears that the two metallizat ion surface treatments (25 min UV-O3 + 1 min BOE and 25 min UV-O3) are feasible for the new processing scheme in which ohmic metal is deposited prior to oxide deposition. All three samp les had breakdown fields of ~3.5 MV/cm or greater with more than 40% of the tested diodes br eaking down at voltages less than -10 V (Figure 6-18). Although the sample with the standard pre-treatment had the highest breakdown voltage out of the three,

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140 its value was representative of one diode and not the whole set of diodes. Looking at the C-V results in Figure 6-19, it can be seen that all th ree samples have a large negative flatband voltage shift. The large flatband voltage shift is primarily attributed to the high metal-semiconductor work function difference a nd oxide trapped charge (Qot). Assuming a work function of 5.6 eV for platinum, a work function difference of -1.78 eV was calculated for the samples. Since the flatband voltage shift was negative, it is believed that the large negative ga te bias injected holes from the semiconductor into the oxide, resultin g in an equivalent negative charge in the semiconductor. It is also a possi bility that trapped el ectrons in the oxide we re injected from the oxide into the surface of the semiconductor. Furt her analysis of the C-V curve reveals that the Dit is very similar for all three samples, but the sample with the UV-O3 and BOE treatment appears to have a slightly lower Dit based on its steeper slope.

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141 Table 6-1. Electrical results for MgO films on uGaN with various surface pre-treatments. The oxide was deposited following ohmic metal deposition. Surface preVbd (MV/cm) Dit (eV-1cm-2) VFB (V) Diodes > 10 V treatment at 1 mA/cm2 at Ec-0.4 eV 25 min UV-O3 3.92 2.0x1011 0.46 33/60 (55%) 25 min UV-O3 + 4.02 1.8x1011 0.63 39/60 (65%) 10 min NH4OH 25 min UV-O3 + 3.69 2.0x1011 0.64 32/60 (53%) 1 min BOE 25 min UV-O3 + 3.82 2.0x1011 0.41 38/60 (63%) N2 plasma anneal

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142 Figure 6-1. Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-O3 surface pretreatment. Breakdown field was 3.92 MV/cm at 1 mA/cm2 for a film thickness of 39 nm. Compliance was 100 nA. 024681012141618 0.00E+000 2.00E-008 4.00E-008 6.00E-008 8.00E-008 1.00E-007 Current (A)Voltage (V)

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143 Figure 6-2. Capacitance-voltage (C-V) pl ot for MgO on p-GaN with a 25 min UV-O3 surface pre-treatment. Measurement was taken at a frequency of 10 kHz. 0.00.51.01.52.02.5 0.00E+000 2.00E-012 4.00E-012 6.00E-012 8.00E-012 1.00E-011 1.20E-011 1.40E-011 Capacitance (F)Voltage (V)

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144 Figure 6-3. Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-O3 and 10 min NH4OH surface pre-treatment. Breakdown field was 4.02 MV/cm at 1 mA/cm2 for a film thickness of 39 nm. Compliance was 100 nA. -20-10010 -1.00E-007 -5.00E-008 0.00E+000 5.00E-008 1.00E-007 Current (A)Voltage (V)

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145 Figure 6-4. Capacitance-voltage (C-V) pl ot for MgO on p-GaN with a 25 min UV-O3 and 10 min NH4OH surface pre-treatment. Measurement was taken at a frequency of 10 kHz. 0.00.51.01.52.0 0.00E+000 2.00E-012 4.00E-012 6.00E-012 8.00E-012 1.00E-011 1.20E-011 1.40E-011 Capacitance (F)Voltage (V)

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146 Figure 6-5. Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-O3 and 1 min BOE surface pre-treatment. Breakdown fi eld was 3.69 MV/cm at 1 mA/cm2 for a film thickness of 39 nm. Compliance was 100 nA. 0.00.51.01.52.0 0.00E+000 2.00E-012 4.00E-012 6.00E-012 8.00E-012 Capacitance (F)Voltage (V)

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147 Figure 6-6. Capacitance-voltage (C-V) pl ot for MgO on p-GaN with a 25 min UV-O3 and 1 min BOE surface pre-treatment. Measuremen t was taken at a frequency of 10 kHz. 0.00.51.01.52.0 0.00E+000 2.00E-012 4.00E-012 6.00E-012 8.00E-012 Capacitance (F)Voltage (V)

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148 Figure 6-7. Current-voltage (I-V) plot for MgO on u-GaN with a 25 min UV-O3 and 10 min insitu N2 plasma anneal at 700 C surface pre-treatment. Breakdown field was 3.82 MV/cm at 1 mA/cm2 for a film thickness of 39 nm. Compliance was 100 nA. 0246810121416 0.00E+000 2.00E-008 4.00E-008 6.00E-008 8.00E-008 1.00E-007 Current (A)Voltage (V)

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149 Figure 6-8. Capacitance-voltage (C-V) pl ot for MgO on p-GaN with a 25 min UV-O3 and 10 min in-situ N2 plasma anneal at 700 C surface pre-treatment. Measurement was taken at a frequency of 10 kHz. -1.0-0.50.00.51.01.52.0 0.00E+000 2.00E-012 4.00E-012 6.00E-012 8.00E-012 1.00E-011 1.20E-011 Capacitance (F)Voltage (V)

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150 Figure 6-9. Current-voltage (I-V) plot for Mg O on u-GaN with four different surface pretreatments. Breakdown field was measured at 1 mA/cm2 with a film thickness of 39.0 nm. Compliance was 100 nA. 0246810121416 0.00E+000 2.00E-008 4.00E-008 6.00E-008 8.00E-008 1.00E-007 25 min UV-O3 25 min UV-O3+ 10 min NH4OH 25 min UV-O3+ in-situ N2 plasma 25 min UV-O3+ 1 min BOE Current (A)Voltage (V)

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151 Figure 6-10. Capacitance-voltage (C-V) plot for MgO on u-GaN with four different surface pretreatments. Measurements were taken at a frequency of 10 kHz. -0.50.00.51.01.52.0 0.0 0.2 0.4 0.6 0.8 1.0 25 min UV-O3+ in-situ N2 plasma 25 min UV-O3+ 10 min NH4OH 25 min UV-O3 25 min UV-O3+ 1 min BOEC/CoxVoltage (V)

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152 A B Figure 6-11. Current-voltage (I-V) measurements for different ohmic metals on p-GaN. A) Pt/Au (50 nm/80 nm). B) Ni/Au (50 nm/80 nm). Compliance was set at 1 A for Pt/Au and 100 nA for Ni/Au. -10-50510 -0.0000010 -0.0000005 0.0000000 0.0000005 0.0000010 Current (A)Voltage (V)-10-50510-1.00E-007 -5.00E-008 0.00E+000 5.00E-008 1.00E-007 Current (A)Voltage (V)

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153 Figure 6-12. Current-voltage (I-V) plot for MgO on p-GaN with a standard surface pre-treatment (3 min HCl:H2O (1:1), 25 min UV-O3, and 5 min BOE). Breakdown field was 4.23 MV/cm at 1 mA/cm2 for a film thickness of 37.6 nm. Compliance was 100 nA. -20-10010203040 -1.00E-007 -5.00E-008 0.00E+000 5.00E-008 1.00E-007 Current (A)Voltage (V)

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154 Figure 6-13. Capacitance-voltage (C-V) plot for MgO on p-GaN with a standard surface pretreatment (3 min HCl:H2O (1:1), 25 min UV-O3, and 5 min BOE). Measurement was taken at a frequency of 10 kHz. -8-6-4-20246 4.00E-012 4.50E-012 5.00E-012 5.50E-012 6.00E-012 6.50E-012 7.00E-012 Capacitance (F)Voltage (V)

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155 Figure 6-14. Current-voltage (I-V) plot for MgO on p-GaN with a 25 min UV-O3 and 1 min BOE surface pre-treatment. Breakdown fi eld was 3.56 MV/cm at 1 mA/cm2 with a film thickness of 37.6 nm. Compliance was 100 nA. -14-12-10-8-6-4-20-1.00E-007 -8.00E-008 -6.00E-008 -4.00E-008 -2.00E-008 0.00E+000 Current (A)Voltage (V)

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156 Figure 6-15. Capacitance-voltage (C-V) pl ot for MgO on p-GaN with a 25 min UV-O3 and 1 min BOE surface pre-treatment. Measuremen t was taken at a frequency of 10 kHz. -8-6-4-202468 3.50E-012 4.00E-012 4.50E-012 5.00E-012 5.50E-012 6.00E-012 6.50E-012 Capacitance (F)Voltage (V)

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157 Figure 6-16. Current-voltage (I-V) plot for MgO on p-GaN with a 25 min UV-O3 surface pretreatment. Breakdown field was 3.46 MV/cm at 1 mA/cm2 with a film thickness of 37.6 nm. Compliance was 100 nA. -14-12-10-8-6-4-20-1.00E-007 -8.00E-008 -6.00E-008 -4.00E-008 -2.00E-008 0.00E+000 Current (A)Voltage (V)

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158 Figure 6-17. Capacitance-voltage (C-V) pl ot for MgO on p-GaN with a 25 min UV-O3 surface pre-treatment. Measurement was taken at a frequency of 10 kHz. -8-6-4-20246 4.00E-012 4.50E-012 5.00E-012 5.50E-012 6.00E-012 6.50E-012 Capacitance (F)Voltage (V)

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159 Figure 6-18. Current-voltage (I-V) plot for Mg O on p-GaN with three different surface pretreatments. Breakdown field was measured at 1 mA/cm2 with a film thickness of 37.6 nm. Compliance was 100 nA. -18-16-14-12-10-8-6-4-20-1.00E-007 -8.00E-008 -6.00E-008 -4.00E-008 -2.00E-008 0.00E+000 standard: 3 min HCl:H2O+ 25 min UV-O3+ 5 min BOE 25 min UV-O3 25 min UV-O3+ 1 min BOECurrent (A)Voltage (V)

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160 Figure 6-19. Capacitance-voltage (C-V) plot for MgO on p-GaN with three different surface pretreatments. Measurements were taken at a frequency of 10 kHz. -8-6-4-202468 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 25 min UV-O3 25 min UV-O3+ 1 min BOE Standard: 3 min HCl:H2O+ 25 min UV-O3+ 5 min BOEC/CoxVoltage (V)

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161 CHAPTER 7 SUMMARY AND FUTURE WORK Summary of (Sc2O3)x(Ga2O3)1-x on GaN Scandium gallium oxide was researched as a candidate dielectric for GaN-based electronic devices. The objective was to depo sit the oxide as an amorphous film in a stacked ga te dielectric so that it could terminate leak age paths (i.e., dislocations) in the underlying crystalline oxide film. Termination of the leakage paths woul d enhance the breakdown voltage of the overall stacked gate dielectric while maintaining the prop erties at the GaN/crystalline oxide interface. Low substrate temperatures and high source temper atures were initially used to drive amorphous film growth. Characterization with RHEED, XRD, and TEM reve aled the growth of a finegrained polycrystalline film unde r these conditions. Further char acterization with Auger showed surface segregation of Ga for the continuous growth technique (all shutters open continuously during the growth). The surface segregation was attributed to the str onger bond between the Sc and O compared to the Ga and O. A digital growth technique (ope ning of Sc and Ga shutters is alternated while the O is open continuously during the growth) wa s then employed to eliminate the Ga segregation, but it was unsuccessful. A third growth technique was used which involved closing the Ga shutter for a set amount of time to wards the end of the growth while the O and Sc shutters were open continuously. This technique was successful as a uniform film was obtained. After fabricating MOS capacitors, IV meas urements were taken to determine the breakdown field of the oxide film. Initial film s (~33 nm) had extremely poor breakdown fields of 0.15 MV/cm at 1 mA/cm2. Further analysis with XPS rev ealed the presence of a Ga metal phase in addition to the Ga2O3 and Sc2O3 phases. Premature breakdown of the film was attributed to the free Ga metal that was esse ntially acting as a dopant which made the film conductive. New growth conditions were used to eliminate the free Ga metal by lowering the Ga

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162 cell temperature. As the Ga cell temperature decreased, the breakdown field increased, but the values were still poor as the highest va lue reached was only 1.40 MV/cm (at 1 mA/cm2). A similar trend has previously been reported for (Ga2O3)x(Gd2O3)1-x on GaAs as the breakdown voltage increased with an increa se in the concentration of Gd.55,56 The highest breakdown field for that system was achieved for a pure Gd2O3 film. The same phenomena is seen for (Sc2O3)x(Ga2O3)1-x on GaN as the highest breakdown field was achieved for a pure Sc2O3 film (~2.7 MV/cm at 1 mA/cm2). The addition of Ga to Sc2O3 only served to diminish the insulating properties of the film. No furthe r research is recommended for (Sc2O3)x(Ga2O3)1-x on GaN. Summary of MgO Growth Optimization Previous electrical results fo r MgO on GaN are very promising as a breakdown field of 4.4 MV/cm (at 1 mA/cm2) and a Dit as low as 1x1011 eV-1cm-2 have been achieved. The disadvantages of MgO are its poor environmental and thermal stability. Its poor environmental stability has made it extremely difficult to process as it can etch in DI wa ter within 10 seconds. Optimization of the film growth was desired to e nhance the environmental stability of the film in both water and air. Since the be st electrical results have been obtained at low oxygen pressures, new growth conditions (substrat e temperature remained at 100 C) included a low oxygen pressure and a low Mg cell temperature to produ ce a low growth rate. Depositing MgO at a low growth rate was found to signifi cantly enhance its environmental stability. Fabricated MOS capacitors with the optimized growth conditions maintained breakdown field values greater than 3.5 MV/cm (at 1 mA/cm2) after receiving three separate pr ocessing wet treatments. The three separate wet treatments included 1 minute in DI water, 3 minutes in AZ 300 MIF developer, and 10 minutes in PG remover. The samples also sh owed no visible deterioration following their wet treatments. Despite the improved environmen tal stability, MgO has not shown good thermal

PAGE 163

163 stability at high temperatures. Any high temper ature applications will require it to be capped with Sc2O3. The improved environmental stability of MgO was achieved at an oxygen pressure of 4.5x10-6 Torr and a growth rate of ~1.3 nm/min. Pr evious results showed an increase in the breakdown field and decrease in the Dit as the Mg:O ratio increased with decreasing oxygen pressure. Oxygen pressures lower than 4.5x10-6 Torr should be investigated along with lower growth rates to determine if there is any improveme nt in the electrical resu lts. It will also be critical to maintain a high Mg:O ra tio (i.e., 0.68) under these conditions. Given the lower lattice mismatch for MgO on GaN compared to Sc2O3 on GaN, MgO has shown better electrical results than Sc2O3. Since MgCaO can be perf ectly lattice matched to GaN, it is expected that it woul d have better electrical results than MgO. However, it has shown even worse environmental stability in air and water. Since the grow th conditions for MgCaO have not been optimized, new conditions (i.e., lo w oxygen pressure and low growth rate) should be researched to determine if any improvement s can be made to enhance the environmental stability of the film. Results of previous dielectrics (MgO, Gd2O3, and Sc2O3) have been obtained at a substrat e temperature of 100 C. Since MgCaO has been primarily deposited at 300 C, growth at 100 C should also be studied for any impr ovements in the electrical results or stability of the film. Summary of Electrical Results for MgxScyOz Given the -6.5% lattice mismat ch between MgO and GaN and the 9.2% lattice mismatch with Sc2O3, it was hopeful that adding Sc to MgO (to form MgxScyOz) would reduce the lattice mismatch and provide increased st ability. Previous research on MgxScyOz showed improved stability over MgO, but no electr ical results were taken. Since MgO showed both good stability

PAGE 164

164 and electrical results at low oxyge n pressures and growth rates, MgxScyOz films were evaluated at these same conditions. Three separate films were grown at increasing Sc cell temperatures (1090 C, 1135 C, and 1180 C) with a constant substrate temperature (100 C), Mg cell temperature (340 C), and oxygen pressure (<5x10-6 Torr). All three MgxScyOz films had breakdown fields greater than 3.5 MV/cm and Dit values in the low 1011 eV-1cm-2 range, but they also had flatband voltage shifts of ~3 V or gr eater. The large flatband voltage shifts were attributed to the different vale nces of Sc (+3) and Mg (+2) which could generate dangling bonds and defects in the film. Because of the large flatband voltage shift for MgxScyOz, no further studies are recommended for this dielectric. Summary of Metallization Study for MgO A metallization study was performe d in which the feasibility of a new processing scheme was evaluated regarding the deposition of ohmic contacts prior to oxide deposition. The new processing scheme offers numerous advantages such as thorough cleaning of the GaN surface prior to ohmic metal deposition, fewer proce ssing steps the oxide has to undergo, and simultaneous annealing of the ohmic contacts an d in-situ cleaning of the GaN surface prior to growth. A variety of surface pre-treatments we re evaluated to determine their affect on the ohmic contacts and their effectiveness at clean ing GaN with ohmic pads on the surface. The surface pre-treatments included a 25 min UV-O3 treatment, 25 min UV-O3 and 10 min NH4OH treatment, 25 min UV-O3 and 1 min BOE treat ment, and 25 min UV-O3 and 10 min in-situ N2 plasma anneal at 700 C. All four treatments yielded breakdown fields of ~3.70 MV/cm or greater, Dit values around 2.0x1011 eV-1cm-2, flatband voltage shifts of 0.63 V or le ss, and no damage to the ohmic pads on the GaN surface. Given the small sampling se t that was tested, further diodes should be

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165 fabricated and tested to determine which pretreatment provides the optimal surface to grow on and to look for any observable trends as to whic h cleaning pre-treatment o ffers the best starting surface to grow on. The concern of incorpora ting a new surface pre-treatment in place of the standard pre-treatment was that it would not suffi ciently clean the surface, which would result in a higher Dit. All the surface pre-treatments had low Dit values that compared favorably with the value from the standard pre-treatment. However, the values were calcul ated using the Terman method whose accuracy depends on accurate knowledge of constants and values for the substrate and oxide, graphical differentiation of the s-Vg curve, and substrate doping. Closer inspection of the Dit values should be made by taking measuremen ts with more accurate techniques such as the ac conductance method or hi-lo method. Charac terization with XPS should also be done to determine the exact nature of the GaN surface following each treatment. An available nitride MBE system that is currently having an X PS/UPS system installed will allow for in-situ monitoring. The values from the metallization study show ed comparable electrical results to the standard surface pre-tr eatment (3 min HCl:H2O, 25 min UV-O3, and 5 min BOE) that was used in the old processing scheme in which oxide is deposited prior to ohmic metal deposition. These results support the feasibility of the new processing scheme. Fu rther studies should include the optimized MgO growth conditions and incorporati on of one of the surface pre-treatments in the fabrication of an e-mode p-GaN MOSFET. Summary of Electrical Re sults for MgO on p-GaN Electrical data was obtained from MgO on p-Ga N with the use of three different sample pre-treatments. The three sample pre-treatmen ts included a standard treatment (3 min HCl:H2O (1:1), 25 min UV-O3, and 5 min BOE), a 25 min UV-O3 and 1 min BOE treatment, and a 25 min

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166 UV-O3 treatment. The latter two treatments were sa mple pre-treatments that could be used if ohmic metal was deposited prior to sample prep aration and oxide deposit ion. All three samples showed similar electrical results for the br eakdown field, flatband voltage shift, and Dit. Since the two surface pre-treatments that would be used with ohmic metal on the surface showed comparable results to the standard surface pre-tr eatment, it appears that the deposition of ohmic contacts prior to oxide deposition would be a feasible process on p-GaN. Further analysis of MOS capacitors on p-Ga N should be conducted on low doped material to minimize the number of injected carriers, si nce the use of highly doped material typically requires large gate biases to fully deplete th e semiconductor surface of majority carriers. However, a suitable ohmic contact must be found that will remain stable during the 700 C in-situ anneal, and it must provide a lo w contact resistance to low doped p-GaN. The use of transition metal borides, such as TiB2 103 and W2B104, has gained recent attenti on in ohmic contacts on pGaN due to their excellent thermal stability and th eir ability to act as a diffusion barrier in the Ni/Au contact. Reasonable contact resistances were obtained with these transition metal borides at annealing temperatures over 800 C on p-GaN material with a doping density of ~1x1017 cm-3. Further studies should be conducted with p-Ga N material having a doping density in the 1015 cm3 range to determine if minimal contact resistan ces can be achieved with these transition metal borides. The study should also include 700 C in-situ anneals in the MBE system to investigate the thermal stability of the contact a nd the effect on the contact resistance.

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167 APPENDIX A PROCESSING INFORMATION AND DETAILS Each processing step is critical to the succe ss of the device and overall yield as unwanted defects from a step could lead to premature failure of a device, or poor qual ity control of one step could lead to problems with the next step. The following sections will include important information related to microlithography as well as more detailed information for the processing steps used in fabricating the MOS capacitors. The information given in the following sections can be found in references 105-107. Indium Removal Before samples were processed to make diode s, indium (used in mounting the sample to the molybdenum block) was removed from the b ackside of samples that were going to be annealed in the RTA. This was to preven t indium from possibly contaminating the RTA chamber during the anneal. The first step was to coat the front side (s ide with oxi de) of the sample with photoresist (PR). The sample wa s then placed in crystal bond on a glass slide (crystal bond is applied to glass slide on a hot plate to create a vi scous wax) with the backside of the sample facing up. It is criti cal to make sure the hot plate is warm enough to melt the crystal bond, but not too warm so that the PR is hard ba ked to the oxide surface. Once each edge of the sample was covered by the crystal bond, the glas s slide was removed and cooled with an N2 blow gun. A cutip was then soaked with an HCl:H2O (1:3) solution and applied to the backside of the sample. The combination of rubbing with a cutip and scraping with a razor removed indium from the backside of the sample After the indium was removed, the glass slide was placed back on the hot plate to melt the crystal bond and allow for the removal of the sample. As soon as the sample was removed, it was placed in acetone to lift off the PR and crystal bond. After the acetone completely removed the PR and crystal bond, the sample was rinsed in isopropanol (15

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168 30 sec) followed by deionized (DI) water (15 sec). The sample was then dried with an N2 blow gun. Before resist was spun on the sample to be patterned, further cleaning of the sample surface was required. Surface Preparation The primary reasons for cleaning the sample prio r to coating it with resist are to enhance the wetting and adhesion of the PR to the surf ace (critical for developi ng and etching) and to avoid the formation of pinholes in the PR. The su rface tension of the PR mu st be less than the surface tension of the substrate for wetting to oc cur. The degree of wettability is given in Equation A-1: sv = sl + lvcos (A-1) where sv (in dynes/cm) is the interfacial en ergy of the solid-vapor interface, sl (in dynes/cm) is the interfacial energy of the solid-liquid interface, lv (in dynes/cm) is the in terfacial energy of the liquid-vapor interface, and is the contact angle. Genera lly, a contact angle less than 90 produces a wettable surface and a contact angle greater than 90 leads to a non-wettable surface (Figure A-1). Although a low contact angle a nd high surface energy are desirable for wetting, they also produce a hydrophilic surf ace that is attractive for adsorpti on of water. Water adsorbed on the surface can lead to poor adhesion of PR to the underlying substrate which could cause lift off during the etch process, undercut ting at window edges, or complete loss of small features. In cases of poor adhesion to the surface, the surf ace can be primed with a silane compound (ex. hexamethyldisilazane-HMDS) which will lower the surface tension of the s ubstrate to match the surface tension of the resist and make the surface hydrophobic. Typical contaminants that must be removed prio r to resist coating in clude dust particles (in any room or from cleaving sample), metal part icles from metal lift-o ff, residual PR from

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169 previous lithography processes, and solvent or water residue. The process that was used to clean the surface of the samples included the following st eps: 1) 3 min soak in acetone with ultrasonic agitation 2) 3 min soak in metha nol with ultrasonic agitation 3) 3 min soak in DI water with ultrasonic agitation 4) Blow dry with N2 gun 5) 125 C bake on hot plate for 5 min to drive off most of the adsorbed water 6) Cool sample with N2 blow gun. As soon as the cleaning process was completed, PR was spun onto the sample as qui ckly as possible to minimize the amount of time for water adsorption. Photoresist Shipley S1818 (positive resist which develops upon exposure to light) was used to coat all of the samples. It was stored in a refrigerator to extend the life time of the resist as bacterial growth can lead to aging of PR. Before samp les were coated, a 20 mL amber bottle containing 1818 was wrapped up in aluminum foil (to preven t possible exposure to UV light) and given 30 minutes to come to room temperature. The fina l two numbers of the resi st indicate the typical thickness that can be spun, whic h in this case would be 1.8 m. The use of a thicker resist made metal lift-off easier and reduced the number of pinholes. Although the resolution is lower for thicker resists, it was not an issue in fabricati ng the MOS capacitors since the feature sizes were so large. Since resist performance (ex. thicknes s, exposure time, develop time) can change as the PR ages, quality control checks were performed every few mont hs to look for any noticeable changes. Surface Coating After receiving a thorough cleaning treatment samples were placed on top of a small opening in the vacuum chuck of the Laurell spinne r. The opening allowed an applied vacuum to draw the sample into intimate contact with th e vacuum chuck. The desired program was then

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170 selected on the keypad next to the spinner. The program contained two steps, with the first step involving a low spin speed (1000 rpm) for dispen sing the resist, and the second step involving a higher spin speed (5000 rpm) to reach the desire d thickness of the resist. The application of dispensing the resist at a lower spin speed allowe d the resist to spread across the sample before stepping to the higher spin speed. It is critical to step to the fina l spin speed as soon as the resist is dispensed, so that the amount of solvent evaporation (increas ed solvent evaporation produces a thicker film of PR ) is minimized. A plastic syringe was used to dispense the re sist to the spinning sample. Since the amount of pressure used to dispense th e resist is chosen depending on the resist viscosity and surface energy of the sample, a higher pressure is typi cally used for low energy surfaces and/or high viscosity resists. The higher pressure is used to provide the resist e nough force to completely wet the surface. After spinning the sample at 5000 RPM for 30 sec, the samples were removed from the vacuum chuck for a soft bake. Profilometer measurements taken following the soft bake (i.e., 125 C for 1.5.0 minutes) showed that a sp in speed of 5000 rpm for 30 seconds yielded a thickness of 2.0.2 m. Factors Affecting Resist Thickness The primary factors that affect the thickness of the resist are the viscos ity of the PR and the spin speed. As seen in Equation A-2, the thic kness increases for slower spin speeds and higher viscosities: 5 0 t t (A-2) where t (in m) is the thickness of the resist, (in cP) is the viscos ity of the resist, t* (in seconds) is the spreading time which is us ually on the order of seconds, and (in rpm) is the spin speed. Figure A1-2 displays a spin speed curve for Sh ipley 1818 PR that was coated on Si at various

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171 spin speeds (3000, 4000, 5000, and 6000 rpm) to determ ine the thickness of the resist. Other factors that can influence the final resist thickness include humidity, atmospheric pressure, temperature (resist, chuck, wafer, ambient enviro nment, and soft bake), acceleration, and air flow. Their affect on the resist thickness along wi th other factors mentione d earlier is shown in Table A-1. Acceleration An acceleration rate of 1000 rpm/sec was us ed in transitioning from the dispense speed to the final spin speed. Further optimiza tion of the acceleration rate is needed as it can affect film uniformity and the number of spin -induced defects. Film uniformity generally increases as acceleration is increased, but spin-ind uced defects are generated at high acceleration rates (i.e., 20000 rpm/sec). High acceleration rates can produce a grea ter concentration of atomized resist particles (can be minimized with a suitable exha ust) that can re-deposit on the sample surface. Particles that re-deposit on the surface as a spherical shape are usually dry or low in solvent and will block UV light. This crea tes an island of resist pattern where one should not be present after development. Particles that re-deposit on the surface as half domes (also known as color spots or fish eyes) are rich in so lvent and will focus the UV light. This leads to partial development and a crater shaped patter n defect. Since low acceleration rates can also induce defects, there is a narro w operating range that must be found which will produce a resist film of uniform thickness and low defect concentration. Spin Defects and Artifacts Although acceleration is the main spin defect contributor, other factors can produce defects as well. Some of the factors include surface or resist contamination, air bubbles in the dispensed resist, and very high spin speeds (aerosol particle s are generated if a wafer is spun too fast). Contaminants on the surface and pa rticles or air in the resist are common sources of pinholes.

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172 Pinholes pose serious problems as unwanted etch ing or metal deposition (in later processing steps) can occur through tiny hol es in the resist. Some of the methods to reduce the pinhole density include using a thick re sist, using a double coat resist process (rely on mismatch of pinholes in each layer), and thor ough cleaning of the sample surface. Striations (radial stripes) or colored bands in the re sist are indicative of thickness variations that are primarily due to non-unifo rm drying of the solven t during the final spin step. Therefore, the spin time must be chosen carefully to allow the solvent concentration enough time to decrease uniformly across the sample. Surface cont amination can also cause striations to form due to poor wetting and adhesion. For thick coatings (>2 m), a recommended technique to reduce the striations includes al lowing the resist to sit on the surface for a set time before spinning (ex. 15 seconds for 2 m thick resist). This techniqu e was not used for any of the sample coatings, but it should be studied in fu ture processing optimization analyses. Another method that can be used to minimize the striations is to make sure the resist is dispensed at the center of the sample and not at multiple locations. Since the radial velocity is greatest at the edge of the sample, the solvent evaporates there more quickly, producing a thicker amount of resist at the edges. This residual ridge in the resist is known as the edge bead. A recommended method to remove the edge bead is to use an EBR (edge bead removal) solvent that partially dissolv es the edge bead away after being spun onto the sample following resist coating. However, this method was not used so that the number of processing steps could be minimized. Any effect s the edge bead could have on the exposure or developer times was removed by maki ng sure that only the center of the sample (where the resist thickness was more uniform) was exposed to the pa ttern. All other types of spin defects and artifacts are included in Table A-2.

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173 Soft Bake Although the spin coating removes the majority of the solvent (80-90 %) from the resist, a soft bake is required to evaporate the residual spinning solvent and densify the resist. If the excess solvent is not removed from the resist, it can make the required exposure dose for pattern transfer unpredictable. Incomplete removal of so lvent can also leave the resist tacky, making the sample stick to the mask during pattern alignmen t and making it more susceptible to particulate contamination. Besides its use to primarily drive out the remaining solvent from the resist film, the soft bake is used for removing internal stre sses in the resist, closi ng voids and/or pinholes, and enhancing the adhesion between the sample surface and resist. The soft bake step was performed using a Th ermolyne hot plate. A hot plate was used since convection ovens can lead to trapping of the solvent in the resist. Entrapped solvent can then form micro bubbles that become pinholes (popped bubbles) during furthe r drying of the PR. Using a hot plate allowed the solvent to outgas before the surface of the resist hardened. Finding the suitable soft bake te mperature and time is critical in determining reproducible exposure and develop times. If the soft ba ke temperature is t oo high, the photosensitive component may become partially degraded, requ iring a higher exposure dose or longer exposure time. A high soft bake temperature with a shor t bake time can also lead to the formation of pinholes as the solvent is not given sufficient time to outgas. If the soft bake temperature is too low, the remaining solvent may interfere with the radiation chemistry and development rates (exposed and unexposed areas will dissolve equally), requiring di fferent exposure-development combinations. It is also critical to find soft bake conditions that prov ide reproducible dissolution rates for the exposed and unexposed regions of th e resist. After performing numerous processing

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174 optimization experiments, it was found th at a soft bake temperature of 125 C for a time of 1.5 minutes produced the most reproducible exposure and development times. Exposure After receiving a soft bake, each sample was placed on a 2 Si alignment wafer (held in place by vacuum) which was inserted on top of the sample stage of the mask aligner. Channel 1, corresponding to 365 nm wavelength light, was select ed on the constant inte nsity controller. The exposure dose (in mW/cm2) of the aligner was fixed, so only the exposure time could be varied. The exposure time was initially cal ibrated by using samples of as -received Si and GaN. The calibrated exposure time was then checked a nd finalized by using a GaN sample with MBE deposited oxide (each oxide is cal ibrated). Since different surfaces reflect different fractions of light, the oxide on GaN sample provided the mo st ideal case for the exposure. The reflected light at the substrate/resist in terface can interfere with the transmitted light from the optical source of the mask aligner to form standing waves. Standing waves produce two undesirable effects with the first one bei ng undesirable horizont al ridges (reflective notching) in the resist sidewa lls that correspond to peaks a nd troughs in the standing wave intensity. The second effect is that standing wa ves affect the total amount of light captured by the resist. Since the amount of light absorbed by the resist cha nges dramatically with a slight change in resist thickness, th e exposure dose or time is highly sensitive to changes in resist thickness. This results in a sw ing curve which is a sinusoidal variation of the exposure dose (Eo) for varying resist thicknesses. The curves ar e generated by interference between incoming and outgoing light waves due to a pha se difference between them. The swing between the maximum (where destructive interference occurs) and mini mum (where constructive interference occurs)

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175 points on the curve is represente d by a thickness change of /4n, where is the exposure wavelength (in nm) and n is the i ndex of refraction of the resist. There are multiple methods that can be used to reduce the effects of standing waves. One of the methods includes a post e xposure bake to reduce or eliminat e the horizontal ridges in the resist sidewalls created by the st anding waves. However, a post exposure bake will not work to reduce the swing curves. Dyed resists or anti reflective coatings (ARC) are recommended for reducing swing curves. Dyed resi sts utilize a higher optical dens ity to suppress the reflection of light, but too much opacity can redu ce the exposure at the bottom of the resist. An ARC is a thin layer of opaque organic material or heavily dyed polymer that is coated on the substrate surface underneath the resist layer. The ARC has a high enough optical absorption to separate the resist from the optical behavior of the substrate by ab sorbing the reflected light To avoid adding any complexity to the fabrication process, none of th ese methods were used to process the samples. Instead of reducing the standing waves, a maxi mum point on the swing curve was targeted to counter any changes in the resi st thickness and prevent any occu rrences of underexposure, which can lead to scumming of the resist. Development Rohm and Haas MF 319 developer or AZ 300 MIF developer (both are metal-ion free) were used to develop the exposed samples. The develop time is a strong function of the exposure dose or time, so any exposure changes w ill lead to changes in the development time. The development time was generally 30 seconds. The amount of time was determined by monitoring the dissolution of the resist in the solution. As th e resist was dissolving, a dark cloud would form above the sample. Agitation was used to increase the development rate (kinetics of development are mass transport limited) and remove the dissolved resist (dark cloud) away from

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176 the sample since resist can re-deposit in the f eatures under static development. Once the dark cloud dissipated, the sample was re moved from the solution, rinsed in water, and then dried with an N2 blow gun. The developed features on the samp le were then analyzed under a microscope with filtered light to look for any features that had not fully developed. The profiles of the features are heavily dependent on the co mbination of the exposure and develop times. Overcut profiles are indicative of overexposure due to reflected exposure rays, and undercut profiles are indicative of overdevel opment due to partial removal of unexposed resist (Figure A-3). The development rate depends on the soft bake conditions, developer temperature, solution agitation, a nd concentration or type of developer. Causes of insufficient development include use of a high soft bake temp erature, weakened developer solution, incorrect exposure dose or time, or incorrect development time. Hard Bake Following development of the patterned sample, it can be given a hard bake to remove the developer, moisture, and any remaining solvent (c omplete removal of casting solvent can only be accomplished by baking the resist above its Tg). This helps to improve the adhesion of the resist to the substrate for further processing steps such as wet or dry etching. Determining what hard bake conditions to use depends on factors such as the resist thickness, exposure dose, type of resist and developer, etchant and conditions, imag e profile, and subsequent processing steps (PR removal, volatility, temperature). Since longe r and hotter hard bake conditions can make residual PR difficult to remove, a hard bake of 110C for 60 sec on a Thermolyne hot plate was used. Samples were not given a hard bake when the next processing step was metallization (i.e. metal sputtering) since a soft resist was desired for metal lift-off.

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177 Table A-1. Change in resist th ickness for a given parameter. Parameter Resist Thickness Reason RPM increases Decreases Centrifuga l force thins the resist as more resist is spun off the substrate Viscosity increases Increases Less resi st is spun off the substrate due to its slower molecular movement, and there is a lower concentra tion of solvent to evaporate Resist temperature Increases Rate of solvent evaporation increases with increases an increase in temperature Humidity increases Decr eases Amount of solvent evaporation decreases due to a lower exchange of spinning solvent molecules in an environment abundant with H2O Airflow increases Increases Rate of solvent evaporation increases Atmospheric (barometric) Increases Great er solvent volatility at lower pressures pressure decreases accelerates the rate of evaporation Acceleration increases Decreases Centrif ugal force thins the resist as more resist is spun off the substrate Soft bake temperature Increases Ra te of solvent evaporation increases increases

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178 Table A-2. Causes of spin-i nduced defects or artifacts. Spin Defect or Artifact Cause Cloudy film Excess moisture Comets Bubbles or partic les from resist dispense Swirls Volatile solvent Pinholes Surface contamination; air or particles in resist Striations Surface contamination; nonuniform solvent drying; dispense at multiple locations

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179 A B Figure A-1. Diagrams of wetting vs contact angle. A) Wetting o ccurs for low contact angle (). B) Non-wetting occurs for high contact angle (). substrate sv lv sl Contact angle ( ) liquid substrate sv lv sl Contact angle () liquid

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180 Figure A-2. Resist thickness vs. spin speed for Shipley 1818 PR. 3000350040004500500055006000 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Resist thickness (um)Spin Speed (RPM)

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181 A B Figure A-3. Sidewall profiles of phot oresist features. A) Undercut profile from overexposure. B) Overcut profile from overdevelopment. Substrate Resist Resist Substrate Resist Resist

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182 APPENDIX B CV CURVES AND MEASUREMENTS CV Curves The measured capacitance of a MOS capacitor co nsists of two capacitors in series. The two capacitors include a voltage -independent gate oxide capac itor and a voltage-dependent semiconductor capacitor. In accumulation, the seri es capacitance is represented by the oxide capacitance shown in Equation B-1: ox o ox oxt C (B-1) where Cox is the capacitor of the oxide (measured in F/cm2), ox is the dielectric constant of the oxide, o is the permittivity of free space (8.854x10-14 F/cm), and tox is the thickness of the oxide film (measured in cm). In depletion, the semiconductor surface become s depleted of majority carriers under the applied gate bias (holes are depl eted in p-type material with in creasing gate voltage and electrons are depleted in n-type material with decreasing gate voltage), causing a decrease in the measured capacitance. The overall capacitance is now repr esented by the series connection of the oxide capacitance (Cox) and depletion layer capacitance (Cd) seen in Equation B-2: d oxC C C 1 1 1 (B-2) Under strong inversion, minority carriers are generated in the bulk and then drift across the depletion region to form a surface layer of charge. However, this will only occur if a low (~1 100 Hz) frequency is applied and if the gate bias is changed slowly. The low frequency and slow changing gate bias allow the minority carriers enough time to respond to the ac probe frequency

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183 and dc voltage signal. The overall capacitance is now represented by the oxide capacitance once again (Figure B-1a). For high (~1 MHz) frequency measurements at slow changing gate biases, the minority carrier generation rate is too low as the minority carriers do not have enough time to respond to the ac voltage signal. The semiconductor deplet ion layer capacitance is now at a minimum, corresponding to a maximum depletion width. The overall measured capaci tance is also at a minimum and is represented by the series capac itance of the oxide and semiconductor depletion layer (Figures B-1b and B-2). For high or low frequency measurements at a large gate bias sweep rate, the generation rate of minority carriers is too low and the measured capacitance can go into deep depletion (Figure B-1c). Dit Calculations The frequency and gate bias sweep rate can have a significant eff ect on the response of interface states at the oxide/se miconductor interface. As the a pplied gate bias changes, the surface potential of the MOS device changes, which causes the in terface states (whose positions with respect to the band edges are fixed) in the bandgap to move above or below the Fermi level. Since energy levels below the Fermi level have a higher probability of oc cupying an electron, an interface state moving above the Fermi level w ould likely give up a trapped electron (or equivalently capture a hole) while an interface state moving below the Fermi level would likely capture an electron (or give up a hole). The stored charge from the interface states gives rise to a capacitance which is in series with the deple tion layer capacitor (the combination of the two would be in series with the oxide capacitance). At very high (~1 MHz) frequencies, the interface states do not have time to respond. At low (~ 1 Hz) frequencies and/or low gate bias sweep rates, the interface states can respond quickly to the voltage changes and follow the ac probe frequency.

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184 The Terman method was used to calculate the Dit value from the measured CV data. The method relies on measurements taken at sufficien tly high frequencies in which interface traps do not respond. Although the interface traps do not respond to the ac probe frequency, they do respond to slow gate bias sweep rates. As the interface trap occupancy ch anges with gate bias, the CV curve stretches out along the gate axis (change in slope of real CV curve from ideal curve in Figure B-3 indicates the presence of interface traps). To determine the Dit, a theoretical CV curve must be constructed and compar ed to the experimental curve. The total theoretical capacitance is given by the series capacitan ce of the oxide and semiconductor. To calculate the th eoretical semiconductor capacitance (Cs), the semiconductor flatband capacitance (CFBS) is calculated from Equation B-3: D o s FBSL C (B-3) where CFBS is the semiconductor flatband capacitance (in F/cm2), s is the dielectric constant of GaN (5.3 at high frequencies), o is the permittivity of free space (8.854x10-14 F/cm), and LD is the Debye length (in cm). The Debye le ngth is calculated from Equation B-4: N q T k Lo s B D 2 (B-4) where LD is the Debye length (in cm), kB is Boltzmanns constant (1.38x10-23 J/k), T is the temperature (in K), s is the dielectric constant of GaN (5.3 at high frequencies), o is the permittivity of free space (8.854x10-14 F/cm), q is the hole or electron charge (1.6x10-19 C), and N is the effective carrier density (in cm-3). The effective carrier density can be calculated from Equation B-5: V C A q No s/ ) / 1 ( 1 22 2 (B-5)

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185 where N is the effectiv e carrier density (in cm-3), s is the dielectric constant of GaN (5.3 at high frequencies), o is the permittivity of free space (8.854x10-14 F/cm), q is the hole or electron charge (1.6x10-19 C), A is the area of metal gate (in cm), and (1/C2)/ V is the slope of the experimental 1/C2 vs. Vg plot. After calculating the flatba nd capacitance of the semic onductor, the theoretical semiconductor capacitance can be calculated from Equation B-6:108 5 0 5 0) 1 ( ) 1 ( ) ( 2 V V FBS se V e C V Sgn C (B-6) where Cs is the semiconductor capacitance in (F/cm2); V is the non-dimensional band bending (in V); Sgn(V) returns a value of 1 for positive values of V, 0 for a value of 0 for V, and -1 for negative values of V; and CFBS is semiconductor flatband capacitance (in F/cm2). The nondimensional band bending is used in Equati on B-7 to calculate the surface potential: q VT kB s (B-7) where s is the surface potential (in eV), kB is Boltzmanns constant (8.62x10-5 eV/K), V is the non-dimensional band bending (in V), T is the temperature (in K), and q is the hole or electron charge (1.6x10-19 C). After constructing the theoreti cal curve by plotting the theore tical total capacitance vs. the surface potential, a surface poten tial value is found for a given capacitance value. The gate voltage from the experimental curve is then f ound for the same capacitance value. Repeating the procedure for other points allows an s vs. Vg curve to be constructed. The Dit can be determined from this curve using Equation B-8: q C V q C Ds s G ox it 1 (B-8)

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186 where Dit is the interface state density (in eV-1cm-2), Cox is the oxide capacitance (in F/m2), q is the hole or electron charge (1.6x10-19 C), VG is the gate bias (in V), s is the surface potential (in eV), and Cs is the surface capacitance (in F/m2). VFB Determination For an ideal MOS capacitor, th e metal and semiconductor work functions are equal at a gate bias of 0 V. However, in a real MOS capacitor, there is typical ly a metal-semiconductor work function ( ms) difference and oxide and interface char ges that produce a flatband voltage (VFB) shift (parallel shift of real plot from ideal pl ot is seen in Figure B3). The flatband voltage is the voltage required to achieve the flat ba nd condition where the energy bands are flat. A negative flatband voltage shift indicates a positiv e oxide charge that induces an equivalent negative charge in the semiconductor. A positiv e flatband voltage shift indicates a negative oxide charge that induces an equivalent positive char ge in the semiconductor. To determine the flatband voltage shift, the th eoretical CV curve must be compared to the experimental CV curve. The first step is to locate the normalized th eoretical capacitance (C/Cox) at a gate bias of 0 V. The same value is th en located on the normalized experimental capacitance curve with the corresponding gate bias value. This gate bias value represents the flatband voltage of the MOS capacitor. Another method that can be used to determine the flatband voltage shift experimenta lly includes plotting (1/Chf)2 vs. VG.89 The gate bias at the lower knee of the curve represents the flatband voltage.

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187 Figure B-1. MOS capacitanc e-voltage curves for a p-type semi conductor. A) Low frequency. B) High frequency. C) Deep depletion. [Reprinted with permission from B.P. Gila, 2000. Growth and Characterization of Dielectric Materials for Wide Bandgap Semiconductors. PhD dissertation (pg. 129, Figure A1-2). University of Florida, Gainesville, Florida.]

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188 Inversion Depletion CinsulatorCsubstrate, (min) CinsulatorCsubstrate CinsulatorAccumulation C VG 0 + Figure B-2. High frequenc y CV measurement for an ideal MO S capacitor. [Reprinted with permission from B.P. Gila, 2000. Grow th and Characterization of Dielectric Materials for Wide Bandgap Semiconductors PhD dissertation (pg. 131, Figure A14). University of Florida, Gainesville, Florida.]

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189 Figure B-3. Illustration of ideal and real CV plots. Shift in real curve indicates flatband voltage shift, and change in slope of real curve indicates interface traps. [Reprinted with permission from B.P. Gila, 2000. Grow th and Characterization of Dielectric Materials for Wide Bandgap Semiconductors PhD dissertation (pg. 132, Figure A15). University of Florida, Gainesville, Florida.] Ideal Real C V 0

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198 BIOGRAPHICAL SKETCH Mark Steven Hlad was born in Great Falls, Mo ntana, and moved to Lynn Haven, Florida, after only a few months old. He is the son of Dennis and Jan Hl ad and brother to Paul Hlad. After graduating from Mosley Hi gh School in 1998, he attended Gulf Coast Community College for a couple years before attending the University of Florida in 2000. He received his bachelors degree in chemical engineering in 2003 and had the opportunity during that time to perform undergraduate research studies with Dr. Omar Bchir on WNx thin films as diffusion barriers for copper metallization. He then began to pursu e a doctoral degree in materials science and engineering in the summer of 2003 under Dr. Cammy Abernathy with research on gate dielectrics (grown by MBE) on GaN MOSFETs. He completed his philosophy of doctorate in the summer of 2007 in materials science and engin eering. Post graduation plans include a job as a packaging engineer with Intel Corporation in Chandler, Arizona.