<%BANNER%>

Design of Multi-Gigabit Serial Link Transceiver Using Bandwidth-Efficient Half-Symbol-Rate-Carrier Offset Quadrature Pha...

Permanent Link: http://ufdc.ufl.edu/UFE0021264/00001

Material Information

Title: Design of Multi-Gigabit Serial Link Transceiver Using Bandwidth-Efficient Half-Symbol-Rate-Carrier Offset Quadrature Phase Shift Keying Modulation
Physical Description: 1 online resource (137 p.)
Language: english
Creator: Yeo, Hyeopgoo
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2007

Subjects

Subjects / Keywords: hsrc, oqpsk
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: My research introduces new quadrature phase-shift-keying (QPSK) modulation techniques for high-speed data communication systems that use two orthogonal half-symbol-rate-carrier (HSRC) signals by which channel bandwidth requirements are reduced compared to that of the conventional non-return-to-zero (NRZ) modulation. The proposed HSRC offset-QPSK (HSRC-OQPSK) improves spectral efficiency by reducing the side lobes of the signal spectrum. In addition, HSRC minimum-shift keying (HSRC-MSK) modulation is also introduced. The performances and the simulation results of the proposed modulation techniques are studied and compared with those of the conventional ones. Using the proposed HSRC-OQPSK modulation, a prototype transmitter generating the HSRC-OQPSK signal was designed and built. Measurement results confirm the theory that the proposed HSRC-OQPSK modulation improves spectral efficiency by reducing the second lobe of the signal spectrum by 10dB. Furthermore, the HSRC-OQPSK modulation reduces the first null bandwidth by 25% compared to the standard Non-Return-to-Zero (NRZ) modulation. Like NRZ, HSRC-OQPSK uses a 2-level data decision which enables a simpler transceiver architecture than multi-level pulse amplitude modulations (PAM), such as 4-PAM and duobinary. My research also examines a modified Costas loop for the clock and data recovery (CDR) involving HSRC-OQPSK modulation. Behavioral model simulation has verified analysis of the proposed CDR. The carrier frequency of the HSRC-OQPSK signal is quarter data rate. Hence the proposed CDR is comparable to quarter-rate CDR using quadrature-phase VCO (QVCO), which relaxes the timing constraints and allows a simple structure as well. The HSRC-OQPSK transceivers are implemented and simulated with TSMC and UMC 0.18?m CMOS technology to prove the theoretical performance. The theory and the measurement results show that it is feasible to increase the data-rate in wire-line communications using low-cost channels.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Hyeopgoo Yeo.
Thesis: Thesis (Ph.D.)--University of Florida, 2007.
Local: Adviser: Lin, Jenshan.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2007
System ID: UFE0021264:00001

Permanent Link: http://ufdc.ufl.edu/UFE0021264/00001

Material Information

Title: Design of Multi-Gigabit Serial Link Transceiver Using Bandwidth-Efficient Half-Symbol-Rate-Carrier Offset Quadrature Phase Shift Keying Modulation
Physical Description: 1 online resource (137 p.)
Language: english
Creator: Yeo, Hyeopgoo
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2007

Subjects

Subjects / Keywords: hsrc, oqpsk
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: My research introduces new quadrature phase-shift-keying (QPSK) modulation techniques for high-speed data communication systems that use two orthogonal half-symbol-rate-carrier (HSRC) signals by which channel bandwidth requirements are reduced compared to that of the conventional non-return-to-zero (NRZ) modulation. The proposed HSRC offset-QPSK (HSRC-OQPSK) improves spectral efficiency by reducing the side lobes of the signal spectrum. In addition, HSRC minimum-shift keying (HSRC-MSK) modulation is also introduced. The performances and the simulation results of the proposed modulation techniques are studied and compared with those of the conventional ones. Using the proposed HSRC-OQPSK modulation, a prototype transmitter generating the HSRC-OQPSK signal was designed and built. Measurement results confirm the theory that the proposed HSRC-OQPSK modulation improves spectral efficiency by reducing the second lobe of the signal spectrum by 10dB. Furthermore, the HSRC-OQPSK modulation reduces the first null bandwidth by 25% compared to the standard Non-Return-to-Zero (NRZ) modulation. Like NRZ, HSRC-OQPSK uses a 2-level data decision which enables a simpler transceiver architecture than multi-level pulse amplitude modulations (PAM), such as 4-PAM and duobinary. My research also examines a modified Costas loop for the clock and data recovery (CDR) involving HSRC-OQPSK modulation. Behavioral model simulation has verified analysis of the proposed CDR. The carrier frequency of the HSRC-OQPSK signal is quarter data rate. Hence the proposed CDR is comparable to quarter-rate CDR using quadrature-phase VCO (QVCO), which relaxes the timing constraints and allows a simple structure as well. The HSRC-OQPSK transceivers are implemented and simulated with TSMC and UMC 0.18?m CMOS technology to prove the theoretical performance. The theory and the measurement results show that it is feasible to increase the data-rate in wire-line communications using low-cost channels.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Hyeopgoo Yeo.
Thesis: Thesis (Ph.D.)--University of Florida, 2007.
Local: Adviser: Lin, Jenshan.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2007
System ID: UFE0021264:00001


This item has the following downloads:


Full Text
xml version 1.0 encoding UTF-8
REPORT xmlns http:www.fcla.edudlsmddaitss xmlns:xsi http:www.w3.org2001XMLSchema-instance xsi:schemaLocation http:www.fcla.edudlsmddaitssdaitssReport.xsd
INGEST IEID E20101211_AAAAAG INGEST_TIME 2010-12-11T08:17:58Z PACKAGE UFE0021264_00001
AGREEMENT_INFO ACCOUNT UF PROJECT UFDC
FILES
FILE SIZE 25271604 DFID F20101211_AAAFDZ ORIGIN DEPOSITOR PATH yeo_h_Page_071.tif GLOBAL false PRESERVATION BIT MESSAGE_DIGEST ALGORITHM MD5
b3cf27e4181f2c332ec362f834535dfa
SHA-1
f30949535af208fb5f6b47c788845baa7cdb6bf7
1006149 F20101211_AAAEYT yeo_h_Page_023.jp2
a3f4a5c09f3c57399efd09d7195d106f
e2bac5aca5a5e8bf64a17661beb52c5000f18a02
3219 F20101211_AAAFFC yeo_h_Page_005.txt
45284359117bb2ff3a24db138465d959
c32ab1618836c77178967ae647fe889a38cb69a0
79787 F20101211_AAAFEN yeo_h_Page_066.jp2
e06a10d4121dcc701d4e4f7a807baaa8
9b637a59ede2571c9bcb39457a9885f62ba8152d
37579 F20101211_AAAEZH yeo_h_Page_045.pro
b824eceb4df8b5aa620257e5973852bf
65a196e571146f00b4fb8bd38604a35b307e4508
F20101211_AAAEYU yeo_h_Page_121.tif
71f44a81ff7bcfac5cd6dfe79963fad2
f7b7c1066999de6d3bfac969f3312ab1694a6484
F20101211_AAAFFD yeo_h_Page_078.tif
156c698d29d345253f18386fe9bb7460
a15db5a45b8318e6e2a9dec9237ed963f14cd9e2
93751 F20101211_AAAFEO yeo_h_Page_112.jpg
aed6e61cad17931862de02507b7d0a3b
3ace5fcf48075f6f6a5b5653e2d73fdc662e5d84
F20101211_AAAEZI yeo_h_Page_076.tif
5f1d542b1a6f8c2fcbb741e5526ea581
0c116017912740b268c92e25532541e33338fdd2
1053954 F20101211_AAAEYV yeo_h_Page_059.tif
97608842676ac4cf66288cd7a4ba616e
a2704a615bd90c1df39ea9585f42dc6ab3037a7c
7674 F20101211_AAAFFE yeo_h_Page_012thm.jpg
93518ceabfeb9cf2318de5be6ca2b7ab
451e0e81de4d1b6bf6f20826c168965b713c3a2d
F20101211_AAAFEP yeo_h_Page_010.tif
e1c3078104f881413160559e35704890
a327fd86a63618181b02f510ff08258105832133
60409 F20101211_AAAEZJ yeo_h_Page_098.jpg
58bb509f0b6149343283fa22e1f94133
3b5ff7500c6d280a0dad9bef25f407ecfd0363eb
1051912 F20101211_AAAEYW yeo_h_Page_076.jp2
35ad0912da0b57a2da5caee28e5ba438
4a5cb78e4ec87f28839650db91b77dfd5c62b0d1
F20101211_AAAFEQ yeo_h_Page_008.tif
99f520817e721711a3b806a63731730f
f609f309589976233a19f43758d95084ab39f1a6
1051985 F20101211_AAAEZK yeo_h_Page_011.jp2
7826c510cf5d9c86c83ce441055c6563
8043c2d27562eeccdb7049a5f190e306b23b6e8c
20166 F20101211_AAAEYX yeo_h_Page_046.pro
c167b941625565a2ebc24f8957a45ab0
d38fc75f91796c234ceec890f18b6167748f181b
6178 F20101211_AAAFFF yeo_h_Page_100thm.jpg
85d8608b6b5445f089f138bc86e8beee
506e67d2b474a559f1f9a82e48eed46b7427b8d5
22997 F20101211_AAAFER yeo_h_Page_040.QC.jpg
0b6aeb007c42908b23202eedb856cb7f
9cb51dd658cd93a1536f6df3215be4d66c1af29b
42252 F20101211_AAAEZL yeo_h_Page_011.QC.jpg
926f8edf405cb389e41308fbfd3b64f4
13a09ff2b6e076e1f7864e06f7825c595b65c0b3
1509 F20101211_AAAEYY yeo_h_Page_082.txt
d73e30ad44f0a11be61d0a77d5ef8c4d
e90136232748277099161e589e0ada4aefd0cb38
35066 F20101211_AAAFFG yeo_h_Page_094.pro
2ac52028b159fff123efcd7517b7a000
bc35279f3de97e25280736545e1caccf54fa0423
60813 F20101211_AAAFES yeo_h_Page_008.pro
3a171a99b139103179d5aff856377d2a
2db6ea7e2cb615c6d3888eca7a4087f1492dd282
1989 F20101211_AAAEZM yeo_h_Page_125.txt
6efdb201d3b697677c0893512952466f
aae3f7333839a2b079aedbcb8a37195c9e810773
F20101211_AAAFFH yeo_h_Page_050.tif
a31732920bb5464373bb9564a2f3accd
5f59e13e972477b71cea031e11780c5800023b7a
94648 F20101211_AAAFET yeo_h_Page_032.jpg
c9f3c76dc86ee8d2b479c4533c26bd64
ebb6e666c4f371eb2740cc057f05921cabddf72e
92562 F20101211_AAAEZN yeo_h_Page_123.jpg
0d85dc7f1d1babae896b7435fc51b79b
d5f432415ce7ba8bb3e2634fef57f4b5e40180b1
F20101211_AAAEYZ yeo_h_Page_024.tif
0c3a2376a188e4aff90f181c0f0b6490
8e031c09ecb430d135f4bc84915939fc944ab5c9
7356 F20101211_AAAFFI yeo_h_Page_074thm.jpg
430ee2c61c9f347bc0bbe7f817b34a1d
5029f414a1b9181b2b6dcf71ceebad11d81b22d3
7727 F20101211_AAAFEU yeo_h_Page_076thm.jpg
ab1fba215d46a8edcf626345f71a7414
9d6bf000fad3752144f5c1c0d89d6b7a9abac95e
81047 F20101211_AAAEZO yeo_h_Page_041.jpg
b6595ad5076e396038edd7d099d12c79
e951923feb13228bb7f3e2547fa7e67746c2d859
117263 F20101211_AAAFFJ yeo_h_Page_133.jp2
846493cbb2b0fcf974febfe81aa72eed
53760c582450019a168df14c9e0e02599b2777f2
8374 F20101211_AAAFEV yeo_h_Page_069thm.jpg
965d247537673727de98f52e68843bbf
457e4986630c96a97e49362ef65a9fef10315b93
108292 F20101211_AAAEZP yeo_h_Page_080.jpg
e65942af04f7f4073d64c7c01c6a7eb2
a18b4a95412ff1d175f75be5252f757ee2cfd1db
113723 F20101211_AAAFFK yeo_h_Page_022.jp2
c4576b0a033e7332c4b2a61ea104e230
7439da933330d9b31c08b01ecc83db1cb790f4e4
1822 F20101211_AAAFEW yeo_h_Page_007thm.jpg
434ed1eef6a79672790b1c60588d1143
fd4fc457302334c01d15fc008517a3d43a4a0625
81921 F20101211_AAAEZQ yeo_h_Page_113.jp2
0bb9ebe251f53e7f0ee0bd7aa3e82b98
c97e8be7c035aef9f7089257e593afaa62875d5f
F20101211_AAAFGA yeo_h_Page_137.tif
bcb36f6b58ce13ddaf2fdc0b09a61835
86eefa44519f52648abafedae0e7d5b63fca4321
F20101211_AAAFFL yeo_h_Page_006.tif
39fa215d903cd7eda63c5c3c85fa637d
acbc5709fdade6af9849d160f5e005f08c12ec82
6883 F20101211_AAAFEX yeo_h_Page_111thm.jpg
3e5ede503c66be66c2ff781033f33873
c830f7765e7a5c4a7c47c04aa39e8f0c1e6ad300
36360 F20101211_AAAEZR yeo_h_Page_131.pro
7bd33ee0f179f80a2d5583db84205179
f3d24835f767a85b4f1765fc2b3b845f7065fa4c
6685 F20101211_AAAFFM yeo_h_Page_087thm.jpg
9a3e5ae8690cdc2dd6b841d8678dfd32
d990b6b250d83fb7a24ce7dd2d1f0477d5fb533b
91852 F20101211_AAAFEY yeo_h_Page_120.jpg
fb4aced847e9b9185fd208ecdb819d64
c97c69e20008f91c906f3d0bc17ebf5df8ac5f42
33467 F20101211_AAAEZS yeo_h_Page_063.pro
319fc31b5d1045deaa0c7f3fa6eee51e
0fc20f630d68bfc65d0f66f095e58766e7887aa6
1581 F20101211_AAAFGB yeo_h_Page_111.txt
ca967e8fc18cf514fc84520213ca1ef5
4097bc337fa617e843a0fac1698ca6619a5a1864
75297 F20101211_AAAFFN yeo_h_Page_087.jpg
fac13a777f368fcd310ee08fecfc460d
1032e51b6fdf3b3670429f3e6a5036f3a088d42b
5353 F20101211_AAAFEZ yeo_h_Page_136thm.jpg
c3d863934c5996c536ab34f6501368e6
5565e0bad2ca92cb8c89aa2536e1c5bd3200eff2
66871 F20101211_AAAEZT yeo_h_Page_052.jpg
f6e0760bd0ebd05685fdc89bbd060b87
b1bd47225f89bdc24d95e24133b3f093e9f7c658
32419 F20101211_AAAFGC yeo_h_Page_125.QC.jpg
091242f9a7c874513dad68aee7ac444e
99cb89e8756632ce35f80a35442c990dc4909289
6286 F20101211_AAAFFO yeo_h_Page_065thm.jpg
0d08bb888a4193e853c2e00934bb2407
4ce22e02e259fc367d267874d0d50fa0462348e7
7479 F20101211_AAAEZU yeo_h_Page_089thm.jpg
2115ebb73905e949fa7481e931999ec6
0438bbff48a06b65bb36c21946252b1909c07a7b
17992 F20101211_AAAFGD yeo_h_Page_049.pro
309858cd455a254bbbdb112c49a3b43d
5d1951b49919fd7c51b36897b23ed1e361b00214
6928 F20101211_AAAFFP yeo_h_Page_043thm.jpg
95b2fc97acafda683ff6a6bcb6b15669
a62778356f7919ebb7960c24121fbe9fe8b9f6ac
104520 F20101211_AAAEZV yeo_h_Page_053.jpg
14a8c3eb88b30eaf4eb37bcc9e00d0ce
c8c9acd8a5acd09a884aa0a3393fda5ba383965c
85888 F20101211_AAAFGE yeo_h_Page_062.jpg
608cf6a25168166a2891f4bf628c2750
d1a0421af3c0a9214c5a34f6b49406dece3330c3
1154 F20101211_AAAFFQ yeo_h_Page_002.QC.jpg
92be76b5f134abc83d0543417bebb86b
066cd51222045c3d735b870c3150d166f7a9de2d
43134 F20101211_AAAEZW yeo_h_Page_096.pro
ae47413ea14a1fbb96ed6266da9b2467
3f7b70295dca84abaf935989c87baac967eda4c0
867475 F20101211_AAAFGF yeo_h_Page_054.jp2
52bb44b9b57cb57422a05b0b59a1dcc5
ffa480f227f43276de10963f2c9342fed5c4e60a
27603 F20101211_AAAFFR yeo_h_Page_083.pro
2f61764f194124e9bff5034934c28499
8fab6c9cfd5d8a46a400641bcf9798a8a812ca28
62685 F20101211_AAAEZX yeo_h_Page_099.jpg
a08187f22a1a0c30e02d294a0d5f2f9a
797c61ca944d075c20d2b5eba492288ed4ccff37
8537 F20101211_AAAFFS yeo_h_Page_130thm.jpg
e836463d14a020befb442d50c0fa0274
e8b330b6429fb1d60390ddf34c72a4d7937f84a5
80978 F20101211_AAAEZY yeo_h_Page_034.jp2
e765067336fa72438d864a6099b78a64
5ab5b8c8f8275756f3c8db933c237bf9c2c1edeb
1142 F20101211_AAAFGG yeo_h_Page_095.txt
dc4e395d18a7764edf965465ffb89a4e
05617103433221bb56bd4fe6f66709fde65f3bba
50616 F20101211_AAAFFT yeo_h_Page_014.jp2
26ff6b45cbc4aa4213380becf8e31c72
4342f81cbf13c55f2cafaa6b032dbc8352c2f7d9
F20101211_AAAEZZ yeo_h_Page_080.tif
42baaff575494ee5fb7afa13e8498281
a9c3c46a07cbfbdd72b62cbe6cf9ef135b752076
78614 F20101211_AAAFGH yeo_h_Page_111.jpg
b962b7126ef2f7cf2e765db060442c62
96e3f477960b9e42334b43757649ce4025f1c395
F20101211_AAAFFU yeo_h_Page_082.tif
8ac2e6901d059ae84e2022398fc2d35f
603ed67071e901d975b4be84b6d544cd1fd805e4
6886 F20101211_AAAFGI yeo_h_Page_104thm.jpg
3ad53ccdc2d8657b9f69df4d0afcecb8
7c1b84c7fce85cb67ec2694460bd727e9c3f0d43
87670 F20101211_AAAFFV yeo_h_Page_086.jpg
fd914bedb15fbb9bc799b32435235384
93a80ee14c846b715e66242e275acdcd9ed730fc
32360 F20101211_AAAFGJ yeo_h_Page_088.pro
9d20bf87ca892ab59f367b1cec09877d
b604fabed94597406e5dd516cd611732f70f3984
19075 F20101211_AAAFFW yeo_h_Page_036.pro
7a28d32d0483d56997eb17ed3f4f1ffc
c3adea178e32ee49c7eb0f195440d5fbb33979b3
26061 F20101211_AAAFGK yeo_h_Page_039.QC.jpg
915c313f9a155fbaf63ea50c430faeaa
9f7703e83b3b964e1c38e73d575848ee6676561a
28273 F20101211_AAAFFX yeo_h_Page_023.QC.jpg
3c15e8923f334f08581ed511bfc9e4d8
ba1700bae696febfc60a1e4d69d59b5945696a86
26196 F20101211_AAAFHA yeo_h_Page_074.QC.jpg
c3a0fb0f1c313588d2c3b93b2ce40aab
04312e2c5b55b394619d9adb4cdfcfeb5002ca9f
7425 F20101211_AAAFGL yeo_h_Page_062thm.jpg
8e8a631adb9ef8b1438f88586d5cb595
f7f179262c919498cf7888322069f81011a21f3c
95168 F20101211_AAAFFY yeo_h_Page_119.jpg
70bd370927a7ab77bdc70abb7df3f192
ab19fe01d869afc80e016eca584a4fb88e4f8514
29487 F20101211_AAAFHB yeo_h_Page_005.QC.jpg
d4e0c406971b1144764f818e0c33c34e
04a5be3225c1b24848d24b96ca6e6eac8282796a
7286 F20101211_AAAFGM yeo_h_Page_095thm.jpg
83459e7fee2772b9bfdedb7a3a703535
71e1c1025e6e2ba5dde368dc0581cfc95575319a
8006 F20101211_AAAFFZ yeo_h_Page_081thm.jpg
c902ef14936dc9c29cf63967c8bd651c
9db7c3ce33df67ee525d2f6d3ff84a5a071cdd34
31092 F20101211_AAAFHC yeo_h_Page_015.QC.jpg
e84e7da30838947ce0e66c94d17324cd
ce7b8bf2878e8612729bf6bef0dbce0f703ca81e
859 F20101211_AAAFGN yeo_h_Page_014.txt
caf0b0af7832dfe5b568273619071d9b
8c4b229cc1c3c3e2afdfa0cd2e08c4ab9a081d6f
1353 F20101211_AAAFHD yeo_h_Page_073.txt
27c3ef10afec4f15a06a5b59f3e9e8dd
0c332118074f39770f55df35c55007f0c5e27f98
36881 F20101211_AAAFGO yeo_h_Page_134.QC.jpg
c03f5e6ca1681d5527f098475162a7c2
009b68c36c16c4c7394ee8207b9d917aaf4b4bb9
36297 F20101211_AAAFHE yeo_h_Page_026.pro
ee57339169c4117f6ee0c9c8be0c6105
75c98a6377a77a58d19538bdbede34e1b86799c7
28970 F20101211_AAAFGP yeo_h_Page_107.pro
1cd8f287e772c50772c61539e958c3e2
0c888fd3eeb03ac9e34ba37131be5063996b8f96
46771 F20101211_AAAFHF yeo_h_Page_102.pro
444c009ca1f17b1681d2f6f0ae6300aa
8e1151e398c177807e38478c67bd99205407271a
8311 F20101211_AAAFGQ yeo_h_Page_082thm.jpg
9f2234d326a6be25db5416073c13ef92
19c67ece8264106f8eada536c3200641cc42609e
93461 F20101211_AAAFHG yeo_h_Page_028.jp2
5fb6743dddd592067332c4a741f75495
35fef2162f7f06d2fb24cd133700f6a3bc32dec9
49774 F20101211_AAAFGR yeo_h_Page_128.pro
2eb91db97ab7f777d8031db7fee1c5b0
e814ef7c036e2ae2d512a9d10835f45488e3d409
49773 F20101211_AAAFGS yeo_h_Page_124.pro
aa9b77586f4bab457fbdedc8f4ef98f4
fd6750b974eec58d9e98e184e69038bb246c15cb
28157 F20101211_AAAFHH yeo_h_Page_090.QC.jpg
688883d1de05725cb722a078d80630c6
99de299e1fed93bc28400837dd4bc6bee6ff9df6
F20101211_AAAFGT yeo_h_Page_038.tif
fcaa3dd4811c207f81da9d4d68d9e6ba
89bb0b719e82f418de402d70d840ed52203595b0
42542 F20101211_AAAFHI yeo_h_Page_112.pro
533220733c46b66b55b4d7c6ddfd60b3
8a9c1e0ecd0d80f741dcde11500d1efb508c68fa
1038102 F20101211_AAAFGU yeo_h_Page_084.jp2
f64334179d4e5f3c013399e82313cb6d
e575bebc6398ec598644b2eee06610ed0e4a198f
32301 F20101211_AAAFHJ yeo_h_Page_106.QC.jpg
a6b635be0a1853c1cf5bf7a386e9496c
23552fc11e08932f12ecd367c7f022d640592002
65251 F20101211_AAAFGV yeo_h_Page_065.jpg
c8414eca1f867418e1f09ad37080106f
5c3f139122da34d71cacc6f900f67110e8a5d925
1051972 F20101211_AAAFHK yeo_h_Page_118.jp2
d2a52a6bd6e445c56af30f7bb98da98f
f68358197dc6f0db16fd3cdbe5ed471849b4f8f3
27161 F20101211_AAAFGW yeo_h_Page_041.QC.jpg
428d2aba49ef1e7a59aebd50087827de
8884193d1a92a6f620ea83c504e6113e4de4b72e
28149 F20101211_AAAFIA yeo_h_Page_064.QC.jpg
5dc0d3ffe97f3309a7f3cb0de973d344
45fa5d7a122cf41b85ccba682ee267ae43787ea7
553 F20101211_AAAFHL yeo_h_Page_001.txt
af077fc579bef5d8492270260f53e7e9
dc38cd566ec79a7a8d1e4a5e10ceafa4fe212396
41542 F20101211_AAAFGX yeo_h_Page_116.pro
61cc4fcbb90f0dace60659cf85f1b00e
b42a3ac3f551e4a7850a6545d26b16944d5a6249
72828 F20101211_AAAFIB yeo_h_Page_049.jpg
6b4c46fc10b0dcc5198684175d3f48e3
f0ea2f9c7230ee003ae808aed6fe613b87c87ea7
46154 F20101211_AAAFHM yeo_h_Page_127.pro
a8ceedca086a5a6c2aaa2dfcf160faf8
91a36cba3a124d541d9aecfa29014d17f2af80d2
112886 F20101211_AAAFGY yeo_h_Page_042.jp2
16373ef2202e59e9749db8ea27f6744d
b5ce11ebbc947d479fa8f0e95e9817f0332b99c2
81514 F20101211_AAAFIC yeo_h_Page_035.jp2
1a963f159cfd5ae5f99c89215a7a6697
2cb17acd93277b9f6c4dac7ec584e1c6fbc2a915
98078 F20101211_AAAFHN yeo_h_Page_033.jpg
521a8a40076ac52a6330a248cdc2c7fd
7d922c58021881efaebb1449a552c3b4a9389d52
37554 F20101211_AAAFGZ yeo_h_Page_008.QC.jpg
9815efd9df8080e2a6b09b57b3beb85b
cae44ab626aed3cd5b135cd22a18a650107e723f
27455 F20101211_AAAFID yeo_h_Page_027.pro
5f24e96adde6e05c083ea15d9d89956d
d366dbb148cdf8609ec78db98bb562253d6d3480
1342 F20101211_AAAFHO yeo_h_Page_027.txt
7ef0454e9f4c20bf5f58e2000ba83ec7
5aa496d38ce17089ff64408c728aeda9983ecae5
129119 F20101211_AAAFIE yeo_h_Page_005.jpg
38119ee8d5a9320d4b5b506a81b8e70b
e7ecb9d5837217a39f6c4c1f26f0eeb179cf5247
25581 F20101211_AAAFHP yeo_h_Page_114.pro
e46aecec057ce4023846819492a4c907
35a9f65b68eea41f28c9dbaaec47af94ed920d44
8727 F20101211_AAAFIF yeo_h_Page_007.pro
83bba961c635e076af24ff8d9e2cf780
cecc17893be83b350f267c6c58579b8f2a596c3c
34725 F20101211_AAAFHQ yeo_h_Page_128.QC.jpg
337e2cdfed0c1592cb7ca0cf82550b70
7ed15043c28526e4b7d90dfe57428d49ea3cc309
9298 F20101211_AAAFIG yeo_h_Page_132thm.jpg
95524980dd904ecc5b3f5e80873d8acb
6e62297eed97e69c0e4bf8d7a4dfd206ea02e954
2429 F20101211_AAAFHR yeo_h_Page_134.txt
d6bdb3da678bc7a9eb454f2388477cf5
2787d905d31295d0560817da0f904f0153d36d86
25873 F20101211_AAAFIH yeo_h_Page_063.QC.jpg
4dafb3b9f54213b64f15e89b60fd8ad7
f98d494cffcee5d1308e307ac0beaff345338427
F20101211_AAAFHS yeo_h_Page_014.tif
ac8876e2b869ed448318941b73e5cb5d
3c721d3ced5facb5d6ce6dae8723e035867f0db2
957 F20101211_AAAFHT yeo_h_Page_087.pro
61ea191c47f0e26225f97c90661f2956
c4d01efc5c906dace7500de4e54ebc6d739b7fb6
8707 F20101211_AAAFII yeo_h_Page_106thm.jpg
437dc1f6e5536317dbaf9c62a6c31f5f
199d0c659ebaddb4f0595945957c8e854e7f7a2c
F20101211_AAAFHU yeo_h_Page_112.tif
c440513c4503e9cdfe6c51022fa1b042
75eba68df9bcc306b9c9d0efcbf4b3bb99f4683b
613604 F20101211_AAAFIJ yeo_h_Page_114.jp2
9721b8bfa8f390c1f11bb36e1dea7294
d91998060f26d8d47a4eb32ac4ca808fee214c2b
2073 F20101211_AAAFHV yeo_h_Page_130.txt
4fbe351c4b313a14f6a4650549582b44
ee7e9a6e805ca433df97934fc1d0d5163b3726b4
9325 F20101211_AAAFIK yeo_h_Page_008thm.jpg
83d85a58c06f2db040096e06019850f0
99c079099b60d959b1dcb0def49d3b370287d31e
70867 F20101211_AAAFHW yeo_h_Page_068.jpg
e0bfda5a019bf7fd4f6fa0a54eb739bd
b1d8c6173881fa7b56aa20ba07f4ccc8b52256f8
46844 F20101211_AAAFIL yeo_h_Page_015.pro
dab8d4af263e7c1840d0a3c53a333bc4
9ce0f4d4347c7635a3b3588117a9a7b34e788853
75333 F20101211_AAAFHX yeo_h_Page_021.jp2
acc0bd2a3266b83e48622a446420069d
663e37a2b4624a3c73ea0729f2ed501c476b88d4
1832 F20101211_AAAFJA yeo_h_Page_028.txt
fb08996c5c7f154803e23fc465e67e92
4a3e8afa2819231140218ecedc648273fe154687
21990 F20101211_AAAFIM yeo_h_Page_087.QC.jpg
55509a3ac20b6a20a90187003490871a
f0584cdd0a22fe08257d2cf19b4b57f3932f6df0
6430 F20101211_AAAFHY yeo_h_Page_083thm.jpg
9626576fe735805d8ac208472f5f74d1
45a8fa2d6e6a33622d12026425bab88a711f1e01
34715 F20101211_AAAFJB yeo_h_Page_136.pro
efb863456231439f769cf106320e7254
1e997c0fe0dfa0b0509aa0308a7a1261813cbbc6
6824 F20101211_AAAFIN yeo_h_Page_105thm.jpg
9cc407e81415a2bfb6565d7c24fd7cf2
d486bdf7f27640cbb4fe24182380d02ed9bb4de1
28147 F20101211_AAAFHZ yeo_h_Page_103.pro
263d0ad89be67aefdb612d908499c87f
56c683d13aaf40912aaa9c5d3abc0ddb2df8db90
48743 F20101211_AAAFJC yeo_h_Page_014.jpg
99f301fc5214892047372cc3867cc802
104cde58bd1eca3cd4db82500741c78dd8a1a213
16370 F20101211_AAAFIO yeo_h_Page_070.pro
1b42b9016fdc0359d492e15ac0d41029
0907d0764803eeaaa756d21261e12690e0c0386b
65307 F20101211_AAAFJD yeo_h_Page_078.jpg
05216ae0e18541a51f4f7c2ee8b73c2c
2010fd4aa8159d647cd5e726b7f52d1566b11603
F20101211_AAAFIP yeo_h_Page_015.tif
b20714d473cf640359f91ca6141ff294
c898960bd392af0e4fd1f455aca229c2b49265d4
878592 F20101211_AAAFJE yeo_h_Page_121.jp2
7a0c5bd8a98241284a58094d20124a2d
2aec765e9dca389b9ca1d9b1cbdc9ba07e41b214
1051970 F20101211_AAAFIQ yeo_h_Page_005.jp2
63726623a0da037e1922d78f5c15b6b7
62289a1fb01813e0ae6f10ae974b62915804029c
37631 F20101211_AAAFJF yeo_h_Page_082.pro
bd18f52f857f6ca3a4246d83e896efd1
a7615a5e3c7b1425e5b30a585dacd6e32d0c0d50
84209 F20101211_AAAFIR yeo_h_Page_113.jpg
3bd79e419cebf62b1b6e1d41dc32a11a
69f062ba3f093b849bf7c9cc34e412cca077db41
107857 F20101211_AAAFJG yeo_h_Page_004.jp2
da47c0d1ae889c3934d34ad4727c4342
999ab1ef407600b84ae34a4e4f8a8c63ea747ce4
928724 F20101211_AAAFIS yeo_h_Page_049.jp2
fabd995904eb395bbeceeea70f2e68d2
47da90d476eb15086db7baf66f7565cf0d42bfa4
1044787 F20101211_AAAFJH yeo_h_Page_090.jp2
2a809304597fad52e6855a6a02cfa92c
3101d17b9ee37455b5af52ddef8116995040c799
80929 F20101211_AAAFIT yeo_h_Page_074.jpg
a7eb622666bd5a5c55b5a8f451105011
7392b4c693bc314e2d56d46a48de744ef5f3abb7
F20101211_AAAFJI yeo_h_Page_102.tif
6ebad568b984be84a03b958b151fd7a3
6b2acbe24b675a0e279062be64639e1cb7496d2e
85258 F20101211_AAAFIU yeo_h_Page_062.jp2
a75c82e98f32f0c444749dbe586f6141
50cb898d882c7604f790df0b9e3fc77e29692e2d
1300 F20101211_AAAFIV yeo_h_Page_081.txt
f8e5fc8db815e3788528956a4c72f39d
95934462b8fd1f9114e9991fb552cc4e0d959ea0
8173 F20101211_AAAFJJ yeo_h_Page_037thm.jpg
3b5ca280147f75ab0fde7073ae104141
fa7f62979f4bae232db2fb4dc3458bf19c7eac62
1999 F20101211_AAAFIW yeo_h_Page_091.txt
730d60dd2b5dfb5bed2bde1a86d60c34
e272dc9e2c1fb2df65d046af3c7240850879635f
202491 F20101211_AAAFJK UFE0021264_00001.xml FULL
7ccf3838952c87b5044e6361a8b1a1ce
211b4bd6c9a9dbf9ebe7b7507cb1d6e64866ce2a
F20101211_AAAFIX yeo_h_Page_032.tif
c32e36a0b417319a45700cd45d958c40
5cc52c7ec59450a0434c70f5d19918ef15a3d29a
87444 F20101211_AAAFKA yeo_h_Page_028.jpg
0ed1ebf472edf4425f8f65ed70dcffe5
2b20b6768f220864ce822c158c405997ae3db0e3
F20101211_AAAFIY yeo_h_Page_039.tif
13f840395e3051b05d3e1f80222a548b
cc1e82b770f44eedb33af2644f715e86ebe73b6f
69717 F20101211_AAAFKB yeo_h_Page_029.jpg
3e11f3adc1ae1935f8b270ce1acd751a
11c341d8b647cd3660be1b8118cf7d3893dc26d9
58605 F20101211_AAAFKC yeo_h_Page_030.jpg
8d8ad55153cc911e4405a1a59a113838
4f1255e25c0b58619265ef0f7070ec1a4f19436d
31111 F20101211_AAAFJN yeo_h_Page_001.jpg
66fa58c00c496a59fb0d156d429fc899
8bbbc4f9d0ccdad5cdf37042fc7e169d9c2d9d7b
2092 F20101211_AAAFIZ yeo_h_Page_055.txt
200c53389789426d3cb0c5fa8e017667
ce9a08335bcf00235a7ef8c51dffab7cd0cc00a4
77686 F20101211_AAAFKD yeo_h_Page_035.jpg
6a638cd5f5dfc710013e3e09f7c1805b
1e3daa6435e026facf04b186757d9637562bc797
3840 F20101211_AAAFJO yeo_h_Page_002.jpg
2922b0de4dc13e7999c4a7c31fbee198
acb815aeb2edc3cfac6b9363d9c656376963d66d
74364 F20101211_AAAFKE yeo_h_Page_036.jpg
e742ac44e2bad763429a7a2c1af5ba2a
db8ad9191fd2f783567155a7eb7df3bc94deaefb
127178 F20101211_AAAFJP yeo_h_Page_006.jpg
9ef844d56092e61732a6ccbbc14686a9
6015ce23bf297cc6279fcd0fd299801b170031d2
91960 F20101211_AAAFKF yeo_h_Page_037.jpg
e02a75981acbd30974c6506395c40da7
62298521e8c035be60956852ab9920c2a673d5e4
140690 F20101211_AAAFJQ yeo_h_Page_009.jpg
1b34788bf0ae511ee89854fd4b6142a8
7878b602d9f007c1fec83e787d4c2f901f061d67
72546 F20101211_AAAFKG yeo_h_Page_044.jpg
ab771e5b8161e4fc6845dc0260f1e843
f25dfbd9b10df2dcf6eae4cafa5ceda1558ecec4
115379 F20101211_AAAFJR yeo_h_Page_012.jpg
07b636095aa9bd44dd84e2c6acc8d11e
d15a7653bb5204eb9e589c21f4bb21bcfa787039
86501 F20101211_AAAFKH yeo_h_Page_045.jpg
30a808cb1513f2b62fe4c07fca185484
fafd83fcbf4b4822869e8705b108d413c8ea8362
96741 F20101211_AAAFJS yeo_h_Page_013.jpg
466520d025ced2dd81415676e1df7b3d
97bcacc5984883984b2aa9c6a467f9daad19b923
83346 F20101211_AAAFKI yeo_h_Page_047.jpg
aebf2ce5aa1300a68faae969980a485f
c2e7cfde7e31d164d675f0861dda26fe887efc88
112818 F20101211_AAAFJT yeo_h_Page_017.jpg
471ee8a4004ddaede44ee80dbf733156
51404ffd0e7ae116c8a3c01a3f99f9707c1b3d28
96912 F20101211_AAAFKJ yeo_h_Page_048.jpg
e04787d902156909af2419358957ea2f
ba41d1fc327b92e9f61ea32dd7d2c3687e2aa3da
75043 F20101211_AAAFJU yeo_h_Page_021.jpg
059e48945eceb485398ecf79a0dedd45
a0867a11c47882bbe8c573b218f54cbcbdf5d2a5
108608 F20101211_AAAFJV yeo_h_Page_022.jpg
22b7cfc5e1b18046033658392dd2fbea
aaa3f1dc4f52e2402a83dcbc6db39722b4ec50de
110761 F20101211_AAAFKK yeo_h_Page_051.jpg
040fdcd0deae448abf16af0c77539f9b
7bfd0faf66c2fc2c299b3a63cae0b2412b689a32
87576 F20101211_AAAFJW yeo_h_Page_023.jpg
b7235f5adf9e12e3049c49a1fbb93c94
db653464ddd220ed696dcb7c86d7f420eb5282b2
73253 F20101211_AAAFKL yeo_h_Page_054.jpg
23dbab41d2462f812d3d49bd5f6cc88e
0a7d435f721f80ac788f326cdb7515f46eaaf91f
100097 F20101211_AAAFJX yeo_h_Page_024.jpg
9206de3be1f099e674978b51e6c09bb0
66511532d7347b304f41872e79739f8bca824d75
87017 F20101211_AAAFLA yeo_h_Page_092.jpg
7d5f7081d57a6ac9da9ee829bda82178
a26ac6e46c3b3345199ecf6864dcc71a825edd00
86167 F20101211_AAAFKM yeo_h_Page_056.jpg
5be32497078a5a0a64e2ec9cb92793c2
9e2de06c87cf5a5d8404679efa98f7371e395219
112073 F20101211_AAAFJY yeo_h_Page_025.jpg
c9f35685d6671deac1552d0878d33823
e60aefebd46282a68965d69a796fd2eca1b7cf32
88566 F20101211_AAAFLB yeo_h_Page_094.jpg
d529d1290ab2bb84fff6df76862f3d22
5983465afeef91d993dda99b1e038e575631a42b
56680 F20101211_AAAFKN yeo_h_Page_059.jpg
cfbf2db030e5bcf09cab0eb05730623a
77b15c2dde150a72f7e852aa6cec79d60e299a07
65231 F20101211_AAAFJZ yeo_h_Page_027.jpg
6dce6827c324258e8a7d4173e0b8906c
076f33a68ac2f24b0ff182a8cbc8ecc07ebe0e66
59814 F20101211_AAAFLC yeo_h_Page_100.jpg
a841b0009769178303c11ad197a78648
3d00d5167706be71d1c8a2c06995d70935c670bc
76898 F20101211_AAAFKO yeo_h_Page_063.jpg
01d4ec40568b410fcf5bfa49af290946
9fb879cd5836e84b7436e79eea25c09c3283d3ed
97627 F20101211_AAAFLD yeo_h_Page_102.jpg
c2b659f3fbbda98a42fb80f9535ab662
496a2153b8c5dc001bdbce7828becb66340e7ff2
81753 F20101211_AAAFKP yeo_h_Page_066.jpg
94a7e3da08a7ca2708d62b9739f8c2f4
eba014566895e178e9075113af143ebd54361c0b
71528 F20101211_AAAFLE yeo_h_Page_103.jpg
9bf49a2b24b3211deed424ce1c178f73
53e7e0c3e3e42762f2606c927d5f01cc5d388ef0
69272 F20101211_AAAFKQ yeo_h_Page_067.jpg
ecc5d4953c6411b19dba6ff640f02762
0e5ca0f7d9153f218eb91fdfb84c0d4981b5230e
68206 F20101211_AAAFLF yeo_h_Page_104.jpg
bc5caa84ae1f6e5852270bdfc01f328c
61331a4656054455d1775f9adcee96fe4d6e0e8c
71866 F20101211_AAAFKR yeo_h_Page_070.jpg
77469c3699c9cf7e101d33cd10bede5b
f10555474b10e5b137e594c3d5e725ea9bbbe716
77247 F20101211_AAAFLG yeo_h_Page_105.jpg
921bba594807f061123401221e49457b
35fdbbd155be403a2387f871c3b73441be581cbd
73856 F20101211_AAAFKS yeo_h_Page_073.jpg
e6edfd01b2bbe9540611da800863c98f
fcdaaf9aec3ade1193d28ff150c4a30b49d02dd0
70226 F20101211_AAAFLH yeo_h_Page_107.jpg
f2fcf2109dc7d9411379e2495bf8b461
c7b5da96cb0c7466142987ae70d4b592f1bb8aa4
79814 F20101211_AAAFKT yeo_h_Page_075.jpg
3c6a6b9096caddf4051a5bf21df94a8b
5fcdaafca7365436d6157ba087744b8d7ad27530
89260 F20101211_AAAFLI yeo_h_Page_109.jpg
720345ba25ea3b4a3ebfaf3581f2db5d
677a1ee6c5e8a1f65a9afe910bef7fb41c7eea61
102110 F20101211_AAAFKU yeo_h_Page_077.jpg
0f8acb716d471e99639e70271c020ecf
9eae194094e0dd1b651b48b7c167751a6d250487
76427 F20101211_AAAFLJ yeo_h_Page_110.jpg
bb26e205b6759c81ead4675807b6e5c7
c32400bf3f5749d198537cf0e48cd368a16383f7
79367 F20101211_AAAFKV yeo_h_Page_079.jpg
c56d5cf5d944ca57922010e5bea93058
1514a9201f806a8a16cdb9616c19c49d06706f19
55264 F20101211_AAAFLK yeo_h_Page_115.jpg
d78800b13967a5fc2fa670013b97dbb9
25ae6652b153269af21a7100636e8436fce6a0f8
101818 F20101211_AAAFKW yeo_h_Page_082.jpg
760a7e5b58cb078932c707c777e20e3e
272b466f18a9687f95b265a2dc01eeda57c38e9a
78072 F20101211_AAAFKX yeo_h_Page_083.jpg
bdc20385235cefc582115d1187c9528d
076ae1ecb7054f4d53d33c7b5280253534ca3b86
876154 F20101211_AAAFMA yeo_h_Page_020.jp2
7e47077b81a597557061ed3103eed15f
6641965e2214b2ce05f881a46bfe7f89c483195f
80326 F20101211_AAAFLL yeo_h_Page_121.jpg
52f190eff7e9f4a555ca25cf06f88069
eb360a8f1eb1d1445296cca2fc0150c5f4e7c8f5
89850 F20101211_AAAFKY yeo_h_Page_085.jpg
46b5001c3128022307c4cabdedb2fe0a
0543f7f5d66bbad2124c6fbc86d6cd856dc0ee10
1051979 F20101211_AAAFMB yeo_h_Page_024.jp2
00ff0a6f216e07dea55e8da95c5f2bcb
50840e1d74ea81166b04c1d55de603a8c08c8c2a
103573 F20101211_AAAFLM yeo_h_Page_122.jpg
d1dc99b8478660f1d1dca25f4f27ddbc
7e5307d59c30535559c25b0bd7e03c0e3cd95110
102598 F20101211_AAAFKZ yeo_h_Page_091.jpg
299730b0f54ba70e3c783fe6c34f427f
6e30873680b1342c3cc8c47669e46bf1f355c593
1051949 F20101211_AAAFMC yeo_h_Page_026.jp2
c1653549849030fb8f324ca0d24597b7
f884083cdfae384f8d1ffe86cc17e90568138894
107742 F20101211_AAAFLN yeo_h_Page_124.jpg
0319e40aff1628777f4b9aa8c9a2b12f
614b1eb19390884fe50d68b156b19a31ea32fd22
82911 F20101211_AAAFMD yeo_h_Page_031.jp2
3dfb0394c7739c1b8be85a19e1fc0247
8cb8ff0b0eb1d8df2faac635e0022755e7f98ac4
100888 F20101211_AAAFLO yeo_h_Page_125.jpg
e73036d0f61ad47971aafc36eff35245
b09375cb760e09747c7e5520b39fd1bf284d1593
F20101211_AAAFME yeo_h_Page_032.jp2
6f12ebd75f497ab7cffa414de4ea9210
6d54c32d5838a0eef9ebc9d6b47804a5e8ebe1e5
92050 F20101211_AAAFLP yeo_h_Page_129.jpg
14500f6c282d63c809961e4ef58ab516
7317a7fac9fec909603f3be1f15e0e7e0f97d41f
1040920 F20101211_AAAFMF yeo_h_Page_037.jp2
fef2163e46722048f11ebf2b15c36286
1f9fcb885c410d84f7f4a16aff43d3c5a85826f1
84912 F20101211_AAAFLQ yeo_h_Page_131.jpg
9df1d788fce8ef7618dda1df0d96b681
ce7d2975fabcaab136ac413ffc9e01217d727bde
865134 F20101211_AAAFMG yeo_h_Page_039.jp2
c1d2369f3be32f20103c87cfa4138283
99494db58e6c5a19b996b1a56303bd44a9fbe573
135528 F20101211_AAAFLR yeo_h_Page_135.jpg
3eaa70aaaffd49d6afbbbe52ef30ec1d
ef44af47bc5b179ff790c2ae6b8da2cfee2ab0ef
706105 F20101211_AAAFMH yeo_h_Page_040.jp2
20450e00a6f7e9da30b0dbe2a3123a06
0c1050910cb0269477cdf04ef5d807675fc8a290
74008 F20101211_AAAFLS yeo_h_Page_136.jpg
86e972aa8b97bc0288d06fe4b69b661e
3e954bb21832a93e52c4db3f376c0b57ef612792
852011 F20101211_AAAFMI yeo_h_Page_041.jp2
bdb13d0f72ec4c1f0b4fecf3fcc41479
c034eb21846cf2869d000bf4e2e236711ab04f53
5017 F20101211_AAAFLT yeo_h_Page_002.jp2
3e169d1c3bf5220b24c41bad7991727e
04cbdbbd722f55b6c70698608a38fb6b629dfbf0
923437 F20101211_AAAFMJ yeo_h_Page_045.jp2
e69656f86afcf887855c50c389d476b4
dc6208d34beb0aedfdd39149157adac814412d1c
1051982 F20101211_AAAFLU yeo_h_Page_006.jp2
56b40fa405922af607b0bd1a4cb65b89
647dfaa6ce8613731e01f101cbd0c6f836776cfa
1051961 F20101211_AAAFMK yeo_h_Page_050.jp2
ba16f92806f8ae2366dbfc03083edfc7
23ebe7e0f00a568b8c3ee2ab2e732c395e4cdbc3
1051930 F20101211_AAAFLV yeo_h_Page_008.jp2
10a4723991970dabe405ad346df87653
d6f520e9934b97ce36db3526b2168b30c206cd02
89430 F20101211_AAAFML yeo_h_Page_056.jp2
7ea75dc00121a5026214a0f1ea27eb37
26630ff4bdf95cfb205e4fc2a0f1ea7a9f898a40
1051976 F20101211_AAAFLW yeo_h_Page_009.jp2
1f825775a7456ecfba032e5bfb9fa0ed
9ae88ba517c154671eb48e57923c2a45cbb86c38
1051953 F20101211_AAAFNA yeo_h_Page_085.jp2
47abeddcfac072a1123c2ee0ad745f9a
7459f1c581e1de45467b5088540f3f184bbee182
1051847 F20101211_AAAFLX yeo_h_Page_010.jp2
816e0218615304823d15413edafcb2f8
0e944a92649c6560420bc21b91b2a32f238d3ae9
F20101211_AAAFNB yeo_h_Page_086.jp2
7ac7bb2f8e73bdeff632e1c2ebc0a0cc
39de2ada7904ef91b75362a767ac980ede7c427a
745105 F20101211_AAAFMM yeo_h_Page_057.jp2
ab29749404d3126d0ec358f41a25d4b8
c1ce47bd792fd602744adc628d963dae754ce532
912270 F20101211_AAAFLY yeo_h_Page_016.jp2
402c02b990c9334a8766f7bb225cba56
a76428a6393cccb4b0f42e8d76c8462a91831d7e
1051980 F20101211_AAAFNC yeo_h_Page_087.jp2
334deb41c23e3a939b20bf3af44f4e4a
f7e574d7cb2776b132a8a720e214eb65446ad891
34400 F20101211_AAAFMN yeo_h_Page_058.jp2
12a8412e08b581e34ab4087a8e77d421
f78c3c6040292afe671504f7315b58d99d33be7e
F20101211_AAAFLZ yeo_h_Page_018.jp2
4b0435830eaf351cc162b7127e199852
aa566f72d1f59a63b0a8404318e6b83b4db1b9d4
1051926 F20101211_AAAFND yeo_h_Page_089.jp2
b3f125b8c3130e0c78f019056bf9d232
8a9921e04ecdb76402b7ce2f85e7914e9b3052ff
60964 F20101211_AAAFMO yeo_h_Page_059.jp2
fd475ee8075f37ef2c374d9460f41bfe
524ac8535c9181d17fb1163a53da497f0908ae00
858392 F20101211_AAAFNE yeo_h_Page_092.jp2
a5b2a22789e2cc657eee1dd2d3b1d86f
41d5192cac58019d790453e29d988c2fd1589c20
89696 F20101211_AAAFMP yeo_h_Page_061.jp2
23e27ef04c9d83d8c75f1ef1ee815962
3938cd91120c48a90b8b1ffb29861fbe0c45d748
113316 F20101211_AAAFNF yeo_h_Page_093.jp2
65e326c2531066ca3c70385cc2d5e18d
e4a871640ada527cb0d69b2b6902963294e07055
77874 F20101211_AAAFMQ yeo_h_Page_063.jp2
2b93b169dfdebafa0852b503a5f99e9e
5dd4d4a06c0796b5ee980a9f60bcec7d1c0be167
692226 F20101211_AAAFNG yeo_h_Page_095.jp2
11104685af8543c432600736c3016342
7daad135b1b2fd2fe189f7f9f6c953b2a1fb4fd6
63561 F20101211_AAAFMR yeo_h_Page_065.jp2
3e5a292a47e198647a9a648a798d0fa8
7add026381f384722e37dc6ea64f465dfee9a6b8
96360 F20101211_AAAFNH yeo_h_Page_096.jp2
44eb8b1af060d33129a0bdbb621cfd0e
a02c3896457bc0086ff897c480c3a3dd1e833c1f
892508 F20101211_AAAFMS yeo_h_Page_070.jp2
45186977cc4440e530a1b72825d958c4
df256ae65e94adf5c219580b1e1c61fc6d3d628e
67754 F20101211_AAAFNI yeo_h_Page_099.jp2
81ee95b857828ea803b2fbf530a76ffb
1a7aee7537b648998972d2c3f9bf009434be03d4
112134 F20101211_AAAFMT yeo_h_Page_072.jp2
0976bf28456eaade78acdbe970f18f12
b9a29e59e7a594d9bccc94660dd90da3d0b2cfd3
763211 F20101211_AAAFNJ yeo_h_Page_101.jp2
69243df56d61411b69e65863178dcb36
d2dd1a4bbc7caa962dfe4ecbbbbf8bcf4716d6b2
962048 F20101211_AAAFMU yeo_h_Page_074.jp2
960e652c2816d7a3c7a8f37595b8751c
da0142e75d0eebcdf8fb971d1ac6d510ed389dca
726087 F20101211_AAAFNK yeo_h_Page_104.jp2
c17268624c17557eaffe5caa411c53e6
26916875a44d24663f865536b276854c364bc5b9
800908 F20101211_AAAFMV yeo_h_Page_078.jp2
5a4e8000767a47f24150db93b3c80c2b
db4be6c3f4582ffdd04c7e60ec070f0e1ded91e6
69811 F20101211_AAAFNL yeo_h_Page_107.jp2
fa23300c274a1703ad1e43aff193fb91
f6a96d6ce9518a9a8623129b1c9940013ed343d2
889239 F20101211_AAAFMW yeo_h_Page_079.jp2
e9bd148794756df16572d89462643b4d
dc3c2059eb92a89349e29660294dd9b02f20212d
987660 F20101211_AAAFNM yeo_h_Page_109.jp2
e8c6b10570f6ac0a7da27d52794ff261
2730b1c26e29a34677f1775cf29906c05e34a867
112366 F20101211_AAAFMX yeo_h_Page_080.jp2
ea4241e2c46b98e2a1fe216d8022f40d
8070fe464ec7f4db1a0d3125935dbfdad7baf76e
140203 F20101211_AAAFOA yeo_h_Page_135.jp2
756b42fcdff5eafc6ab68c36c8e2e397
daf0375c09cda2ec77284ae4a6c49f407384ab57
1051977 F20101211_AAAFMY yeo_h_Page_082.jp2
a0ad44a2890c7a8e385eed86dbe4a5d7
cf8ea8705cde08152d8870fac758d2d2fe31195b
48346 F20101211_AAAFOB yeo_h_Page_137.jp2
8f421e38390e27c0811cbd0401a8d452
69ddea195f31f25834860b7c6fe44eda11ef04bd
816689 F20101211_AAAFNN yeo_h_Page_110.jp2
d0deaec0bba94ddc24e169bac2439438
00100b649d81c94647ce0bdd8481806cfbfaef4a
916691 F20101211_AAAFMZ yeo_h_Page_083.jp2
e1a77ba21ca4c2d9a5117e8bd221fec8
7561b84818108927e038b53686ac2e98722f1af1
F20101211_AAAFOC yeo_h_Page_002.tif
e8bd34f572f3f6f3d5e79d7c15591283
7216615158187e24305e53a24173794300a41b0c
95897 F20101211_AAAFNO yeo_h_Page_112.jp2
b43b8f3eb8a7fb538f9030c1e804275b
cc4c75e5a9cfafbdb43dcc99f18975feded979e0
F20101211_AAAFOD yeo_h_Page_003.tif
6fa97915002fed1b0fbd2e6014fe6307
057a4ac5caec586379585624c8829328d0a31795
513681 F20101211_AAAFNP yeo_h_Page_115.jp2
7b27072c739aea1b8b2fb8e64512c637
8b32ed949c336be898ce639cc6a7f53608e5ec6f
F20101211_AAAFOE yeo_h_Page_007.tif
31f5cd578220d445af946c914a602ede
df21aa13ffef841bab53de413e80d2dd6c260a55
1024544 F20101211_AAAFNQ yeo_h_Page_116.jp2
a9a08de10e969db38d9dcf3b3d9976e6
8307247dcbec4f5cd50128ee12d8a28f5d881e49
F20101211_AAAFOF yeo_h_Page_009.tif
4b3641d14b4006813831186935cae3dc
82c270c940e298acbe47515e1ed8e6d4054b589f
816680 F20101211_AAAFNR yeo_h_Page_117.jp2
61ee0a3393c5a7114888eeb347663058
039c03ee7cee94e186ff0fea72da0af918a76a9a
F20101211_AAAFOG yeo_h_Page_013.tif
7bdac4dfd287b97280f07620fa915e9c
18efa3c619ab7cbfab223525fe7b15d2af5aaff0
F20101211_AAAFNS yeo_h_Page_122.jp2
a7ab8cd884178e82457369aed11939e2
c0486182653cf23dd12c5c5c3db96fda8422c12b
F20101211_AAAFOH yeo_h_Page_018.tif
94ee218258238f0a8e59188dfdb6f6e3
4e3470750415b7b13db6dd61b3f6ba6f10cc1d2b
F20101211_AAAFNT yeo_h_Page_123.jp2
9068d32f926c4f979be8205b33c44e44
e8c87181d022a16a6fa14aecd6373a956c44ff4d
F20101211_AAAFOI yeo_h_Page_020.tif
0fc6365655df464b8092d1aaa678e065
75a68a82ea73c6b04529ca6869350584c0b1f4e5
111515 F20101211_AAAFNU yeo_h_Page_124.jp2
6ed176dfc561cefa4c77aacee7208c52
27a17eecbb97028cd9ac8b56a2a8d52b80e86155
F20101211_AAAFOJ yeo_h_Page_028.tif
30a1fbd9e6d0739f5f6979ba821204dc
c3cd0f913beb0d9ba18f72c8b91d7924120d644e
38125 F20101211_AAAFNV yeo_h_Page_126.jp2
5d2ad968a4852c8ee328caf245ee67ca
2ed7a1b1b8f84e93a4684966047fc869d6bafda4
F20101211_AAAFOK yeo_h_Page_029.tif
b7b6779b2c91dfeec8edab449fcba0ed
b3b0be0583e714f81a2f5bfdeb97c6d25c26d53d
F20101211_AAAFOL yeo_h_Page_031.tif
c9df8e2426aac75cc4830ee669434a22
6f9a352a4e99788ba0060f5898deea4293fae9a4
104723 F20101211_AAAFNW yeo_h_Page_127.jp2
5315e952871ef165872fafef00cb51c4
9907c7d04e1c76662d5880a5c0a76b37611eaee6
F20101211_AAAFPA yeo_h_Page_060.tif
90c4c7cfd331e883b88e08d28f25e9c1
7697d4eee9953b1cf799ffd1063a4627ec7bce8c
F20101211_AAAFOM yeo_h_Page_035.tif
2ff3033f7cbc037ffacd87d6d991b055
be44645ead1fabdaf8c96fab2b9731777cf1184d
109976 F20101211_AAAFNX yeo_h_Page_128.jp2
6bac7ad7ce683ee815d369bf77e5bdf8
20e23c15bc959ab0849d670c97ce435070fd5dcd
F20101211_AAAFPB yeo_h_Page_063.tif
c9818b12b1789f71a1c371775e6d4909
2c75e059d4a80218c9887ab317cc4a38ce1829f1
F20101211_AAAFON yeo_h_Page_040.tif
7ebcadc9321f2911aad13cf0ada0322b
21aa49f025fcd8104dd2c27cda308231b3d740e2
897935 F20101211_AAAFNY yeo_h_Page_131.jp2
ae7eb1d99644dba4defa0a39fe26d4f7
6badd682723da83bdadee15753ef0ca6b1ccc7e0
F20101211_AAAFPC yeo_h_Page_065.tif
e5e6f22256376c47691e588362197403
0ca7f80132924aa35d53b1eb39ce61e71e2eceb8
1032764 F20101211_AAAFNZ yeo_h_Page_132.jp2
126cfdfc31db27a0d355f4dda0b607b5
63d8093c4bf565c6c4ad2786cbf1b6ab432372b2
F20101211_AAAFPD yeo_h_Page_066.tif
25dffb31c2f7bdccf16b886a5ba8861c
ed0ad4046e075e9f4f75ab20f91e187a2d605349
F20101211_AAAFOO yeo_h_Page_041.tif
61806aaa39497f728e5d461f58eef62d
b62cbe07408c1082d5d218d25a222d1cbf7bebd7
F20101211_AAAFPE yeo_h_Page_067.tif
1d3b260b2e01ccc19918215e056b8cbb
314a3ef4c0a8f9918c2285c1101829bdfb43da84
F20101211_AAAFOP yeo_h_Page_042.tif
398e6a2d645b49eaa76310456df41d97
1b08ecd18fa7ac5d057ccdadf3169267b3221ef4
F20101211_AAAFPF yeo_h_Page_069.tif
4e68d45818adedcb692ebf889faf3430
d4ea8d13158c7cc5c8c37f2074b57d70fa22df2f
F20101211_AAAFOQ yeo_h_Page_043.tif
0d4d05c44bb8d65f3a08ac7ab48f72ab
12547682ffa9386eb371a8266222341ea7722e70
F20101211_AAAFPG yeo_h_Page_073.tif
e271d9793a1001d684c860d01922b7d6
f72b76a67bf1104e9375be36ef6f6d9bc4a0c75c
F20101211_AAAFOR yeo_h_Page_044.tif
196d8d7927528654a13341aea40e8160
ace2911172b62f7858a45ff0a38f6baa682fee2b
F20101211_AAAFPH yeo_h_Page_074.tif
0fddccf312991e3685e1ef20490ed678
d99cb40fd6710b09f853e637bea08bdbedfd1a7f
F20101211_AAAFOS yeo_h_Page_045.tif
e01129cf5a4d6cb0349a23b2890ea012
4e598031ffbd9396d35ed93544df3bc8ad97e91a
F20101211_AAAFPI yeo_h_Page_077.tif
c57efee7beb25f2d4cb74c00cacc7afa
4db465c12705a952954401cd3bbdeb084e6d36f0
F20101211_AAAFOT yeo_h_Page_046.tif
c7d556edaa86413012ce57869bae971d
1d60b1c696809362598f0845b90a72f434ef5adb
F20101211_AAAFPJ yeo_h_Page_079.tif
a29997b8dd43c6852caa11e238f9d282
0fce04998fb738e9866581b5bb21ff57ffad96cc
F20101211_AAAFOU yeo_h_Page_047.tif
c877db2e6b9c244fc193ffd870eec327
5591071ac1b151c05bdfec4d7472f919525232e5
F20101211_AAAFPK yeo_h_Page_081.tif
0a12754906c8b377fd609405f43c8eea
96cc88dbd8fc26dcd1bc39a16de121871e372d4e
F20101211_AAAFOV yeo_h_Page_048.tif
fa9505d1939829166fef0c9019d907dc
d6c5933b60d11d0041d1c67bbdddaf699302e5b1
F20101211_AAAFPL yeo_h_Page_084.tif
45f15378cddd89ee57f61dcc7e1e08c3
9a7d6e35c80a6deb78c06cada47612fcb10853c2
F20101211_AAAFOW yeo_h_Page_049.tif
1014cb37a83b8bf8e3458d50b5f5ee36
2c385dddecf31060a02847dba25a6e896508f8fb
F20101211_AAAFPM yeo_h_Page_085.tif
7147a5faa4f0ed38395aaeda4b839e3d
3e7e26d7e02230e89d9ca1cc94a579ca37823b6f
F20101211_AAAFOX yeo_h_Page_054.tif
b9543e20422382b98f6837ca1ae8bdb7
2136fa627a5db0e3a100beb162d8c23ea798c086
F20101211_AAAFQA yeo_h_Page_113.tif
8a64e17a1b0dda059884a4f87b680d34
fbd2e40d4aab81171570bf7b48eb8d88658adbdb
F20101211_AAAFPN yeo_h_Page_086.tif
152a50c998cf8f2d08602907354d636e
c0815d2f2d60cf89a78c24f9a8ce0b0e44e1d07c
F20101211_AAAFOY yeo_h_Page_057.tif
a0a6f3ee044f5fe9f5e2d5939c848421
46bdd5b037ff93d283f0310f22305a9824b53dbd
F20101211_AAAFQB yeo_h_Page_117.tif
ff35a311f171bf788e222de62a2cc2d0
b3f0d4b01b233c4a3db4a1a5e2364ffd386b30ae
F20101211_AAAFPO yeo_h_Page_087.tif
30016ac95a30762a3e93e535fd8ce93e
8e10424219da55b38ba9c34ca4cfe8b0ba7d2487
F20101211_AAAFOZ yeo_h_Page_058.tif
8b8d0d88297c5414f2a4a61bc23bdc32
429911a154a8eec0be8fe15d7ee6baa4e981443c
F20101211_AAAFQC yeo_h_Page_118.tif
f718fc9911a0993e4580587fe5e0d29d
07dda8db9359895e9051aa712fcadbdc53a6911a
F20101211_AAAFQD yeo_h_Page_119.tif
363a4f245c3da5eb2d2979d706536b24
5106d150d18afb7e48316ecdf4dc402bad3b1476
F20101211_AAAFPP yeo_h_Page_090.tif
4f292353b12b1582c2c1e157e3e6e8fb
0d0abe1f5eecee0947b61a04cb1ba4ab22e50c28
F20101211_AAAFQE yeo_h_Page_120.tif
a60ef25767c0720423d9f768cd40811a
5a862be0d12ec7a04419069ad0920d2cd66d2fe1
F20101211_AAAFPQ yeo_h_Page_092.tif
35ae287f67b7e5da4ef755e2fda5dd98
9d8e8f3195d201d012990253c9f0302bf7e92b84
F20101211_AAAFQF yeo_h_Page_122.tif
ff4212326f90ef827339e096be01917d
9dac649340640936e880bf7fa2ea9d7074038aa8
F20101211_AAAFPR yeo_h_Page_093.tif
dfea43014adceff25937cb26b952e7fe
549cc51176bc1a3e3b1e99da56b5c942196121f8
F20101211_AAAFQG yeo_h_Page_123.tif
93895679f74e8a9ea1ddd8533025b4f5
a95147c640d728a4025f4455bf8149006132714e
F20101211_AAAFPS yeo_h_Page_095.tif
05fae060a6180036ec8d6ad7c02ebdb9
49317489dd7cfe4a5eaee9eecd3a772fe9f0b155
F20101211_AAAFQH yeo_h_Page_124.tif
1637605b5dccab17c65305b7b5e6caec
eb308830f3cc2c7b1beed5de57fc5220c7b8da17
F20101211_AAAFPT yeo_h_Page_096.tif
ac1d4a55060eaad9e5cb96162639539f
26414d92d621990120e1ddf3a6face3bf20ea1fb
F20101211_AAAFQI yeo_h_Page_127.tif
8b5eea5c67816213be62dfae77643a46
35c7fde7e05ab1a20e3898f3a10772c98102fac3
F20101211_AAAFPU yeo_h_Page_099.tif
0331cc180dfe942b7142cc1ead5cfc61
08b3250f201b714a0291369bec4edd58fce3ed3a
F20101211_AAAFQJ yeo_h_Page_128.tif
e7e14f54a24d060b81099e145185f128
038452c79bd6e42d4370a80f70e2fdb91299b521
F20101211_AAAFPV yeo_h_Page_100.tif
50f485dbc46ab38dbd1dafa328ac5000
9a11049cb50a30b4f948377fffb27f97b243ad52
F20101211_AAAFQK yeo_h_Page_129.tif
4e6a04b9889e87cb2a58db34deb93388
13b1e34626630489ed8b413e1834b279e1996725
F20101211_AAAFPW yeo_h_Page_101.tif
84b263e7a051b1e1325ab73c4a7bd65f
a22148aa6cefa6d96303921877ff17bc2fc8edae
F20101211_AAAFQL yeo_h_Page_130.tif
bf951f411cb4345b7e5a290b2822f35e
a9f03f4df2e2d4341644e0f544356956545b8223
F20101211_AAAFPX yeo_h_Page_103.tif
f74904a5fbf7b3b8bb086945317f7f1d
64c364c2721629b58ea1739705144da994d36661
54410 F20101211_AAAFRA yeo_h_Page_025.pro
6eccc951750d34055222f5a763de34f9
c649755998a71f9d32f31d89e089b723fe9949dc
F20101211_AAAFQM yeo_h_Page_131.tif
02e4959662cac4455d1131985937bb92
40bae8042f39993b323c5716b8ba06ef34bb55fd
F20101211_AAAFPY yeo_h_Page_108.tif
5b439bccb614f418ed8f835a892b0c6a
b78b4e89669789403ddd5433b57aa3d4fe4010cb
41530 F20101211_AAAFRB yeo_h_Page_028.pro
dff20e07da126949adec9636b1dbf78d
d2c52fc6abc469f822e8d96fe921025a049e3a0b
F20101211_AAAFQN yeo_h_Page_134.tif
cb6f7d570aec1f2d776b565114690114
2acfd4a953f45cb5704c0016ce21bf9447c2b945
F20101211_AAAFPZ yeo_h_Page_111.tif
f0a7e3c895dd69aff1b329b4f33a3c33
bfd491743595517a713fc089db78718b0fab6ce3
24088 F20101211_AAAFRC yeo_h_Page_029.pro
8a73ffc4f67f804dd1223f8747c36759
45eb6515b127a4c9f282f686d54dc9309a1e4069
F20101211_AAAFQO yeo_h_Page_135.tif
b42c41bb6c18bfc57a2af6af3211073f
4fd62857883d561c4bb27499d9cf968a5d816d6b
21715 F20101211_AAAFRD yeo_h_Page_030.pro
31bbdfba149f0d23b415f75ebc340fc0
8d11f8b5313a7750381ceb386401a598ed945927
F20101211_AAAFQP yeo_h_Page_136.tif
84c3884337955de6fc9536fe4351cd74
4f6326f6a84113b5d4eb455cfa50475c746b22dd
29732 F20101211_AAAFRE yeo_h_Page_039.pro
44359a9e2adcb0c01aa2dff8459f119f
c903d3d095b1f8f376d15e872329a68dc1cc7a4f
28187 F20101211_AAAFRF yeo_h_Page_040.pro
60fc3bcb2663d234b39f045a4fbdbab8
d8d1e8639f28d6d0f5a8e8a8dcd6ffe7d17f41a2
775 F20101211_AAAFQQ yeo_h_Page_002.pro
4015b076ef36dcd68f49ef08749af6df
760488de50642e2c961fa6856ac5b41263262459
32452 F20101211_AAAFRG yeo_h_Page_041.pro
048de20a71ae5cd4e0b3ab0391e06a84
9be63def4a17c3c374c8c7f3a07cd32a6ed46c55
905 F20101211_AAAFQR yeo_h_Page_003.pro
4b4f78b81cd2c2a38d29a5fb54752a3d
59ae4cf40a443c502cc4d9488c4be5bda0d17902
21273 F20101211_AAAFRH yeo_h_Page_044.pro
9e814d13bcbf8c57901fe73e26cf7c20
57effea5830867aa0b7250a70e416706e8ae886e
48666 F20101211_AAAFQS yeo_h_Page_004.pro
b26b8f79cd44d3e7ac9d8e182d4877b6
f405b8fe54ce02202961ad2670261b8fd2f8c6e6
32753 F20101211_AAAFRI yeo_h_Page_047.pro
17caa8a7089a3aa9c1a690217e6d9d5a
ca1fd0389cd2015ed817929e6418dfc7257ea375
68685 F20101211_AAAFQT yeo_h_Page_009.pro
f762757bf4cb604d1b52149b894c605e
c4221eeb1f4fcce90f0220b7e9fc5222bb50c22a
44230 F20101211_AAAFRJ yeo_h_Page_048.pro
faea54a3d8552f11ae6563b5fbdb080c
6472d9d938531272b162fdeff063d11ddb8a48d5
69581 F20101211_AAAFQU yeo_h_Page_011.pro
8a6858c5f07176ba77b486c50303f7ef
efe34a6ac5dfaa704286f73eec19e1d85118f6ba
96460 F20101211_AAAEOI yeo_h_Page_026.jpg
a1bf4e91d4e7cc789b01838ff5c305b0
bfe49d616a0c8f694dba4c756c7ced7113d30bba
14665 F20101211_AAAFRK yeo_h_Page_050.pro
0166fe2d6aa6f9e38b4686da6b524aba
25844671036413f299e81e8520dd59988d267bf8
55707 F20101211_AAAFQV yeo_h_Page_012.pro
73ab57aeef37cd8d91c1b10c167f2c71
5bc89d40ae0695c36216d201c27f504a6ad7e817
F20101211_AAAEOJ yeo_h_Page_050thm.jpg
f56d511624e2b2224f4fdb170e3a7d5d
7f24f3f0a65582aee4b7bb835a18101880c5438f
52892 F20101211_AAAFRL yeo_h_Page_051.pro
19e1d1230c0ede455a8a148162bb7617
ec89e3273d5a6e57df0b5e7e2c79ec3afd91d909
42787 F20101211_AAAFQW yeo_h_Page_013.pro
84f266a0e0802ead5ee472a91d4e2299
27361f18d0319b29b937105fee977714f55f1396
21438 F20101211_AAAFSA yeo_h_Page_079.pro
20ee5f96846749fc51886ce6dc14bba1
a2dca4774bfb6fb0ca4f30d41d49474c915aa882
26011 F20101211_AAAEOK yeo_h_Page_043.QC.jpg
5e2ec484d5db1ce51c64b1fadd57aaf8
a871370a00299b903865177ed85bd5543fc6298b
30204 F20101211_AAAFRM yeo_h_Page_052.pro
5b2211fbd61e71233e7c3a291de664a2
451f4e41ce176a45999b3a5c865c87ea24b16a2a
31846 F20101211_AAAFQX yeo_h_Page_020.pro
1a6542a1021400e04a22147b45db771c
3ad37ae99fa27913ebbb58c2b98e945ae21ebcb5
51923 F20101211_AAAFSB yeo_h_Page_080.pro
96cd90556d5441a60b3897e7622f6421
e3fccf4e647d070d6b3d731c5dd05c867a830650
1051974 F20101211_AAAEOL yeo_h_Page_033.jp2
5df783896b65fc36404adc6d775fc527
25685bfe8e5f27f7e0e5050fce344a1e8d939a49
23626 F20101211_AAAFRN yeo_h_Page_054.pro
a69b26ca8c75b972f1cd68b05d583fcc
be8011d614982de574d4b7c4ef93dfd5b13ec709
26674 F20101211_AAAFQY yeo_h_Page_023.pro
5f5afc0720d36e0e858701af782bf99c
22df2563c02af25facf91ce6f22a24008535c68f
64671 F20101211_AAAEPA yeo_h_Page_098.jp2
3ed7454a59ca7bbee1f10984539e3f46
5e6d903d2983326939f6ed5058417128885ac5cd
30195 F20101211_AAAFSC yeo_h_Page_084.pro
7021b115e59f344c0871e259a12ba4ba
1936dd5a32b9dd0580b655233b307e1581a35123
633 F20101211_AAAEOM yeo_h_Page_126.txt
1c517bac2a699c73e6eb2e46ef2ba903
efa4ff3b7e6d71e2c044efdb85b09346f5b6e3c0
38764 F20101211_AAAFRO yeo_h_Page_056.pro
fbb7b3f8a82d94d865afc35b18df6e4e
90ec17bdad0bb66dae166c1d44090a717928392c
34437 F20101211_AAAFQZ yeo_h_Page_024.pro
a79ea9882af2f49b2c56b0f01903d10e
d36eb6d4b1c0b0ffb84f91d046008fd325f51f88
F20101211_AAAEPB yeo_h_Page_001.tif
1f863adae4570abf767b2dee0a115db1
ccc7d336bd8c250d8559cb790a7258f409ceae6c
25460 F20101211_AAAFSD yeo_h_Page_092.pro
eeeb1750640bb1a4ffebf5c96c0d81fd
6049824cc7d89f26c4fe2f659da9dbc51911c339
F20101211_AAAEON yeo_h_Page_107.tif
afaab3839d00459a6bafb92e3d836892
49c34f7bc4958c104dd9780a868f47bc77d733cc
42742 F20101211_AAAFRP yeo_h_Page_060.pro
11072804c148cc812c0db955eb796ca0
02a2e077ea4300df4d3605ccd193b5a00e2f4c36
34343 F20101211_AAAEPC yeo_h_Page_035.pro
4368ede926a85f8d93970b808764bf91
36a4864370a4e3605ec953bb1e333a2b45f9283c
25295 F20101211_AAAFSE yeo_h_Page_095.pro
b05d72334c9b75844654522715dd77bf
18c5ae434f0676d896849a1779d52cdfcafe8a87
27761 F20101211_AAAEOO yeo_h_Page_057.pro
724fc5a793578b7207c5b0d6880a465d
cc1ca4c523e9cbdde3b83dc65864d588f3e0a75a
38618 F20101211_AAAFRQ yeo_h_Page_064.pro
c5a898823e794509330e6bf6a77c3570
051db7b641f5c48a5dfe4f8975820470a4a9eb0c
1049 F20101211_AAAEPD yeo_h_Page_119.txt
f51e6c46b272ef0ec305c84bbf789f82
2cc31e58718a56cdfb0dd0b74a8636c0c1c17b06
27830 F20101211_AAAFSF yeo_h_Page_099.pro
c61bbacc01cf218fce59e83df230da45
99f522c5b14ada5d31650d1a9904034a07a5f9d5
8197 F20101211_AAAEPE yeo_h_Page_048thm.jpg
6c0bcb426ae30c2f83ddc480d43125bd
305a76c1d5e58ffb0befc75824640a226ab5ff89
30790 F20101211_AAAFSG yeo_h_Page_101.pro
64d021bf392a56e47c69628578dfbf16
f364cf150dbb010ed449ac1f0c1895a244a09a59
31654 F20101211_AAAEOP yeo_h_Page_069.QC.jpg
06f1c1109e53d01748afa3f89a44f6bb
6b2cc39539d3b22dc70b380c46e3ed3622dba105
22065 F20101211_AAAFRR yeo_h_Page_065.pro
4b953b9816853756d90ecb96e07c1c82
decfbe241ae4d02d2cbe5964c07c3be4529573d7
60225 F20101211_AAAEPF yeo_h_Page_134.pro
a235afb3cc360a205071aa32a48eb49d
0069070371dea8f8a3653e4a111880d77907b230
26950 F20101211_AAAFSH yeo_h_Page_104.pro
33a9c2707bb0bec27878d4ccc0346a3a
e86e11c3cea1f2b639d54132a9d211ec878ebdeb
999791 F20101211_AAAEOQ yeo_h_Page_130.jp2
b7444569955b9caa836daac78f0eaf3c
f71f030d621bc4db2386d9cbe92ad9387bbc061f
24575 F20101211_AAAFRS yeo_h_Page_067.pro
a250ae54c9ed6033f79fa4df501fdf04
ea61745b40c39170a17d2f52ce3d07dbb3b4bd69
7929 F20101211_AAAEPG yeo_h_Page_085thm.jpg
799cf7d24781c0279e5268649c0e43e0
81ba9d83f4658a2de16bf49761491a912cf95800
36770 F20101211_AAAFSI yeo_h_Page_106.pro
3850f0989c516db4a41e800ae9fa3227
868e0375f50200f19c58e06a55c4f6eabce92c99
F20101211_AAAEOR yeo_h_Page_132.tif
4dfd73f198d91528507d3fb1ab1b37ce
3d6fbd3a92f0d364d04e80da75c261994598d658
23234 F20101211_AAAFRT yeo_h_Page_068.pro
db1c6e967897bf6c586f5fdc68a1a1ab
13dfe0979f2ccb5593c981d39726d59b2dcaed08
67526 F20101211_AAAEPH yeo_h_Page_027.jp2
ee3b25ac2b48181d1d7e4e2315eadc3a
752726d15b7fe4cf8a5f17c2c4d6f26c5a245db3
15629 F20101211_AAAFSJ yeo_h_Page_108.pro
f6ca87512281b28017b9bd63c15524da
c6e7edab22645adec1d5432b9938c2f2960ab928
73262 F20101211_AAAEOS yeo_h_Page_010.pro
b0f22d9ff086ca2c2103de43f659e6af
516f28728f9c1609c8780e14400d45c426614c19
26905 F20101211_AAAFRU yeo_h_Page_069.pro
eb3f1a12a434672ce8eeb3832adeae3b
b0d0cedf04f5033de82cdfc977fd41f894df47a2
F20101211_AAAEPI yeo_h_Page_088.tif
f1d28cdc6e3ecdfca8178429a0efcff5
dcf2e07063247f076ac82be492a296ec7be39f71
35203 F20101211_AAAFSK yeo_h_Page_111.pro
7c9ca179159a2e6896154859ad18f4c8
e1fad342baf91af96f98c1b0dbbe4f5ebedd69ef
8297 F20101211_AAAEOT yeo_h_Page_055thm.jpg
451e0c1ebd7ca06a45313ee1483b4591
6c1057e48d290fd678e687fe7119ca1b97ebf611
27316 F20101211_AAAFRV yeo_h_Page_071.pro
54b2daf8fe1467735812718fa83a3a96
e5308317a2aaf1e878c7594fbb2d25edabb24e54
18242 F20101211_AAAFSL yeo_h_Page_115.pro
01e8b592a7723e668b7a85ff76172388
73c1b34ad6203667686be84a19fe57cb5154f2f1
86763 F20101211_AAAEOU yeo_h_Page_064.jpg
5f6c814e6556247c38d73f09dbfad721
d27e406fbd704bf5c5d0968b41ed6cb1905b4dca
51376 F20101211_AAAFRW yeo_h_Page_072.pro
6354f96c43f2d4762e54938d0d0d2d8c
0ce22045265ebaeb899646b8a4ce73f0b3b7dcc1
1051986 F20101211_AAAEPJ yeo_h_Page_017.jp2
b35e89c8fb49ba8df7ba78b3115f6cf2
e855e42ad76cfa0dec4d718ebdfe464a4da74d7b
F20101211_AAAFTA yeo_h_Page_029.txt
21a4ace79548e45974a12c848db9be7e
04712e89df7823cc0e6614e4bc7e7571b91081c5
29943 F20101211_AAAFSM yeo_h_Page_117.pro
6756d8f7a44d7a48f0fc1e5013de48f7
43d8bc373843966e96591d602d3559ed2e18093e
1542 F20101211_AAAEOV yeo_h_Page_085.txt
85ae0e1bdc9cc7c0c38cef6826369cf5
a00f0f6d3f41b0729c2b64bd141158c850aef59c
19132 F20101211_AAAFRX yeo_h_Page_074.pro
456a9dff989685ad31e86285c5faab8a
e8b100a2dee9f8fe582176572530e4a26d5d81e4
F20101211_AAAEPK yeo_h_Page_126.tif
0073f1078a1fe1751d13ccbb4ceead12
2bc138330de4af893716fda355a687cef9504fa4
1061 F20101211_AAAFTB yeo_h_Page_032.txt
0b7650736d18037f4bac1299dd496f19
85ba3f5269cb812a92fd976d58bc5c2e935a037d
31112 F20101211_AAAFSN yeo_h_Page_118.pro
5fe3b2ff783a57ddab1e3593b674da78
12b8bbeaca05c7266f42c2dc32eda60d749815f8
28675 F20101211_AAAEOW yeo_h_Page_020.QC.jpg
fefceb63e8c8b853487f3dbb2193ee3f
9c43bb76c669c981f119f8748812fea820a4a520
24935 F20101211_AAAFRY yeo_h_Page_076.pro
849b9c4cd69ab900d5936f4ea5bc4f0a
fe04cf1ca57e08b353b9a4b563dbd11dc97b073c
24097 F20101211_AAAEPL yeo_h_Page_083.QC.jpg
902b268c4e954eebb497005830fadae3
b6493bf0e78d1ba01da486c9ad4f6380f9262f5b
1811 F20101211_AAAFTC yeo_h_Page_033.txt
31a25127d5c09f1050ce6f58f52b3e6f
73120551cf6818d4a49e866184d363a5a0b8773b
26869 F20101211_AAAFSO yeo_h_Page_119.pro
46bb94782ee63d3d547b0d13304b9056
d9305832092ee5dde28402a190d7fcd0c8cbaba2
7100 F20101211_AAAEOX yeo_h_Page_110thm.jpg
425e870536003d9b78322ea61d370086
499a5e86ac457cd3ccf5599a4945438359b7cc0f
15679 F20101211_AAAFRZ yeo_h_Page_078.pro
9309b59d47db3edd9880b8c583c6f1ea
385b06666831b82a4af039af64b42bed6383d00c
F20101211_AAAEQA yeo_h_Page_068.tif
663781dc7a6ed90d6c08081c3e32bf3f
1d1461dd9f735c8a3a5344e2abcb1f5f78141734
977672 F20101211_AAAEPM yeo_h_Page_036.jp2
afc7af1d0c6baeb1a4812468035ceb8a
f957b1cfed7a391102fc663904e01e002365b569
1785 F20101211_AAAFTD yeo_h_Page_035.txt
ba5bdfb4552e116c3e62307c6da00018
67af961d84e09bdddeeddf14a0fa58654fa9024b
41134 F20101211_AAAFSP yeo_h_Page_130.pro
9830c30bfeaa65befa4de7c5c96f2051
731f20ac6c6e2084b6828407c5bbb7178a9f8c9d
8031 F20101211_AAAEOY yeo_h_Page_032thm.jpg
22d791065b800925d20b121837566ee7
638a0a724dcdbfa13abdcaf6df610b10b149543f
7529 F20101211_AAAEQB yeo_h_Page_086thm.jpg
8d390a92af53fae72d59b84a94195bd5
3c7b20dceb4fe814ef82277191dc517cfb05f8fd
32371 F20101211_AAAEPN yeo_h_Page_112.QC.jpg
05d0a229fc47e3d1abb242d882d9b43a
bf978a38d59fa9611365e0613d7d8158d9f722f2
886 F20101211_AAAFTE yeo_h_Page_036.txt
15b9bee160f49bf19ed74e1d9a03fb89
1fb545d326460edbdf775e0e61267c4315ab10ac
65853 F20101211_AAAFSQ yeo_h_Page_135.pro
083a4fb13f3aa7af7c5de6bba1cb557e
6ac1ca13bea43012b2c37cb648e1a8d2766fb823
30749 F20101211_AAAEOZ yeo_h_Page_060.QC.jpg
ea9a9d441ba8e9f786b938aab6a468c1
67e8dbe0e64f3ffb7bcdc9eb3c9fb8140a676efc
60123 F20101211_AAAEQC yeo_h_Page_030.jp2
28d30bc35ae4ad6fc506ffdf0a0d591f
468210a4f6212b7792d26ec475f9a12d7877c0b4
1051942 F20101211_AAAEPO yeo_h_Page_046.jp2
3af0d571ea7659c5a75ad86c117248a6
f6523d86d4ce6a9d36443c4fc56fda71886b7dd0
1552 F20101211_AAAFTF yeo_h_Page_039.txt
78754b707f6c07db601abe2b7b064b8a
abed7e5e9357994d36859e506472c210738c6840
20140 F20101211_AAAFSR yeo_h_Page_137.pro
00bf08266820c02309d51bfddddfef95
e14749aa74b0be627980708429703340dfffab04
835652 F20101211_AAAEQD yeo_h_Page_044.jp2
393a0cbd5cda724f2245f40aabe1aaf5
67e07130ebb3359e9f4dbc3dd2094d6c7d03f8eb
30813 F20101211_AAAEPP yeo_h_Page_061.QC.jpg
54c13c4b1448451297d08c74697a742e
388f51fba8b6faf49b4460272e3f1a7a0f9e29b2
1182 F20101211_AAAFTG yeo_h_Page_040.txt
b8ceafad3c76e16af6b21e83085c482b
5f98da646a2a8c5189f4a3b7df627b557f51b48a
842 F20101211_AAAEQE yeo_h_Page_078.txt
8b306641045d36e5bb3528ae2209f279
42a32b351abfc851046b796728eb9159805fc378
F20101211_AAAFTH yeo_h_Page_041.txt
b49bc3041890436c17b83f42d251ec16
a5d18cf36e0dfab0848f98c24f6b2923b27d18d4
82 F20101211_AAAFSS yeo_h_Page_002.txt
64f85c0ae5b4daa4bc1b8f6a58630fad
92cbe0c2061f4853eb679c08630f2eee9b542591
1780 F20101211_AAAEQF yeo_h_Page_122.txt
4bc578fd1f36db928338a29dfb2d2de1
31f1e0961dbb5309a5dc7f4fc852db21a003fc30
84896 F20101211_AAAEPQ yeo_h_Page_019.jpg
9da466036b5580826f5acab02e5472d8
7347ed0e3f98bfaadc3f4accf7e93556547b7f7b
2151 F20101211_AAAFTI yeo_h_Page_045.txt
35c26e4f5397faaffd7e83b8ba6b548d
3ffa9e77dd52d4329015d55805f84ed8fd91433c
390 F20101211_AAAFST yeo_h_Page_007.txt
d5c9f1b93ac5b11bd3eb6a04a2d3efb7
ce2fc7e07c39965f81479b8ee9098906df4a57bc
1337 F20101211_AAAEQG yeo_h_Page_063.txt
9241d412a7123cb5dd6dd09ea836604d
4b25a1f7763573e843c818ef134865b8fd6e09d9
878045 F20101211_AAAEPR yeo_h_Page_094.jp2
46215aca0f108fdb5ae351120806633c
8b693d0d594e2702361cc041dfa845c846aa9b07
1451 F20101211_AAAFTJ yeo_h_Page_047.txt
eb22c76131a72d8eb5000d961d2d8df2
8493787aaa2c6a09a6c57e92a3677934ce455886
2867 F20101211_AAAFSU yeo_h_Page_009.txt
381e0e07dff55226959fe0d69b17821b
feb1d903cf7b40289fe26f10bdcea807853fbf94
75667 F20101211_AAAEQH yeo_h_Page_043.jpg
0052408c5959a88d84c60f123546b708
d121130eb9683bb5fc8b2b18c20e4af33849b521
F20101211_AAAEPS yeo_h_Page_091thm.jpg
ddea3e6dfba33d1301584c2e339a04f8
c72f9a6feed9746698a4103eb822cb5d7761fa84
1836 F20101211_AAAFTK yeo_h_Page_048.txt
1a589bc0a08ed5a7510910eb9a373507
d451a3b051fd8139c1817bc742b62011a08acf90
2797 F20101211_AAAFSV yeo_h_Page_011.txt
834affa57f70b8d5506a1597a5ea926c
5cbc19871b76413f55da7144e6a1ad01cb25cdb4
29293 F20101211_AAAEQI yeo_h_Page_131.QC.jpg
8da8ed75a58c9b74e748af1f84119956
b19967cf3c0e74411efe525340061ac3a77e4844
5179 F20101211_AAAEPT yeo_h_Page_003.jp2
1974ab4cc248bb144138a3ec8e5e3bd3
f79a39a0cabbdb2407819152546cd2c8dc41c3ba
918 F20101211_AAAFTL yeo_h_Page_050.txt
9e873e61550d56681645b80788e86e9f
db3f292e4928a08e0f227d9c6787e2bae9c7876c
2270 F20101211_AAAFSW yeo_h_Page_012.txt
dd124ea78c2a276cee210ca2a6e9ee17
98d779218e61497725902e07c1814b0c0258ffd1
1663 F20101211_AAAEQJ yeo_h_Page_106.txt
4cbbc1a4d3c78b1980ed479edf47509a
6008fa0ee8671ac0d8aa0d9ba912189746b76cf1
19300 F20101211_AAAEPU yeo_h_Page_030.QC.jpg
e782ccc1c9fa898c1f3c1d9bdb76afca
726e09674bb2fa0f52a02875718d4318579e5472
1263 F20101211_AAAFUA yeo_h_Page_083.txt
10bd15e06ae1f2bca4dd26e1c84d98f5
802f6285d47b497ff1e891d2aa528d4baf4c6b47
2121 F20101211_AAAFTM yeo_h_Page_051.txt
41bfe03d53219566abea07983088ffdc
e38339c739678b654362d7e30340d43dccf4bca5
1089 F20101211_AAAFSX yeo_h_Page_016.txt
162183864627397164ece5440f295423
c398ef755c1b0d622c486d88c369980ecab964eb
1888 F20101211_AAAEQK yeo_h_Page_013.txt
a4be066c107c34594ed1a55c7db1e106
cf1b6a587cbab48bc78f2fde51634b5e0893ebfa
77590 F20101211_AAAEPV yeo_h_Page_006.pro
e3ca4aa5cdb938feb5fae64a725ee9a4
24ea2ec385b5131b17e7108b4d71f044c7dd9d9f
863 F20101211_AAAFUB yeo_h_Page_086.txt
06c7cbeec8f10e7d85537a228b4bbe80
85d374d74c984582cd94faf4dc00b3594c379865
1211 F20101211_AAAFTN yeo_h_Page_052.txt
f7580a9ac589e1994e4c062ac1be2322
3a0a4478de0b30b8c96de572a25fe441f4641a78
1082 F20101211_AAAFSY yeo_h_Page_023.txt
463585d7e37a4377b606012277fdb1d3
8d2b773ca3b746b0c6becb03c18dc68289aaddf8
F20101211_AAAEQL yeo_h_Page_036.tif
c4a0c5032619875a12a60ef20f11680c
09c54b365ecfe51c6e6c27df32b1251b317d7b5e
75932 F20101211_AAAEPW yeo_h_Page_038.jpg
5eff6e97740a104637a9f2b52d8038ef
57799007bc39c659bc158b64d53e112aaeaeb4e0
1474 F20101211_AAAFUC yeo_h_Page_088.txt
6356f08f3f3b8afb53a29a08e2f808a6
3303d31612224785b7f584a7ec5205e49feb7368
2061 F20101211_AAAFTO yeo_h_Page_053.txt
2793b6efd9cc19f931d9d4142da77a8d
69d28889f64292a58236916625b82098d1cbae78
2145 F20101211_AAAFSZ yeo_h_Page_025.txt
78b0b53bc3750ee59ef4f738db5e732f
b99c4bdb5c59d252267727e6ee95d182db05051d
25858 F20101211_AAAERA yeo_h_Page_031.QC.jpg
13c14d37389ce397b10d9160b6ba574f
b8297627e5e171eb8cca77c2f86f4514cad5c5ec
22376 F20101211_AAAEQM yeo_h_Page_105.pro
816c8650179531f9ed17691512d83ea5
2f7ae67fd30aa31928a7e412e270f85c454995b5
7537 F20101211_AAAEPX yeo_h_Page_120thm.jpg
b628120838e2145bfa305c376f56d660
19592e31e2b0c20f6fd7b8b826d413249d080b86
829 F20101211_AAAFUD yeo_h_Page_089.txt
9fef26f9afac736dace6fe50ca663400
11882ff7ef8bc6a926f7dd6897340bd6ad964f7e
1084 F20101211_AAAFTP yeo_h_Page_054.txt
3766434115f1fb15b12843dc66c9f3c7
d405b051669b606ef266c76bb4ab7c9cbb89fb24
51819 F20101211_AAAERB yeo_h_Page_093.pro
029896792929fef2c3164000b227ffae
65be268ab5311bb1c92b7c1040c8c9696b12073c
1826 F20101211_AAAEQN yeo_h_Page_037.txt
6e4ef95bc675fc4ddbaed32fe548b735
fad3dffbbf8fd26f1802e53c409500ae7debbb5c
F20101211_AAAEPY yeo_h_Page_104.tif
8b9bb60fe6e6b13d807c8cfefa6bc3f7
a5d86dcf15ce4c8e326853733e3155db540ae786
1421 F20101211_AAAFUE yeo_h_Page_090.txt
a79cdcdbf8e7035a4ffcef08a605bac9
fba2e21d74e5de7cbc1f5a7f07306a2ded28bd1d
1705 F20101211_AAAFTQ yeo_h_Page_064.txt
9cf6af1b3bfd40453bfd4be613c69dc5
6b96167eeb437ffb6d4650f5258939753a608978
32545 F20101211_AAAERC yeo_h_Page_110.pro
02f41a5c9445753138421d9dc871f849
efb13f2241223d5edd24f5b59d9687d67cd269bb
F20101211_AAAEQO yeo_h_Page_022.tif
31874db1e7d56b2abb887f826cd55b4b
5068d2ffaedf9c17bd419f1f0f48653cf3a19729
32488 F20101211_AAAEPZ yeo_h_Page_077.QC.jpg
38409ece303cc0c1b26e05cfcef0d796
c3f925db46774da96ac490449b31eb65b5b7c2a1
1214 F20101211_AAAFUF yeo_h_Page_092.txt
f06d6858d9ab969a0fa653e49000419b
212c50186d3f882b50fc558df0eb2ff5c5719364
912 F20101211_AAAFTR yeo_h_Page_065.txt
ae0c23114197989758a509fe4686b812
e3141e58d995dd2f886e392e9ab30c02b17367c9
7497 F20101211_AAAERD yeo_h_Page_015thm.jpg
602466834662156e0ac94ceb383465af
f86f9e3902cc37f8baf99713e5fc804e93390578
39271 F20101211_AAAEQP yeo_h_Page_009.QC.jpg
f8decc83f048a9523088b47d351f8cbd
a53d2d54492e26201bcaf274aa6c7c2669df1ecc
2071 F20101211_AAAFUG yeo_h_Page_093.txt
cf6eed6b3512dd3e3a98ca313dedb29b
0757e296337af28010c8a139fac54636656e6e88
1102 F20101211_AAAFTS yeo_h_Page_067.txt
91687b0bf08ceca85b3a05250dd4ca2b
2353be141131f283bbeedcbdb719dc74d1125262
34663 F20101211_AAAERE yeo_h_Page_066.pro
cc516eaff83f7f60bf0db8884baa5aac
add38ec16627125e00376828ca2ec67c46c452f3
158237 F20101211_AAAEQQ yeo_h_Page_010.jpg
d440d2fa75f1c1ca299505e1633ce295
82eac555fb9448671e5645564069b4d031b3f6b9
1565 F20101211_AAAFUH yeo_h_Page_094.txt
87b0624f763f816d713915ce2aab7de2
2607c0c8a4a9d1e9a6b23d074e8017a60a6c7099
1963 F20101211_AAAERF yeo_h_Page_128.txt
5151ac86fa07338da6893aa13bc1b87c
dac217737c1ecb7f08db38bf4cfc5dbec67932d9
1893 F20101211_AAAFUI yeo_h_Page_096.txt
2bd537d42899326ab94b5acc6bc71fda
55b526d41372ddc101107b0ce9839ea44e441236
1106 F20101211_AAAFTT yeo_h_Page_069.txt
1a08efa7132a76d82e91112cac2b4e15
2f65cc76173f3e754cacf249f4c72714a5836f96
F20101211_AAAERG yeo_h_Page_011.tif
8e3f29fa73e4374855fd3c1e30c91063
f29aaef5fce263621def6d3bf02ba08fed213ad4
6602 F20101211_AAAEQR yeo_h_Page_006thm.jpg
2075bd809a0d78dd6f8b3e16f949cbe0
d0f264d95fd31d14c17de6dcb80070a5e843f39c
1483 F20101211_AAAFUJ yeo_h_Page_097.txt
47c9028b50905ebd3320dd0c87f7767e
5750d77173d96f3b3233169da66b433f6b5eb633
743 F20101211_AAAFTU yeo_h_Page_070.txt
8d66951d12c66e90e80a321137991b42
dbde91fd816292eb8de3ec5f4a6e4945affcc55d
35199 F20101211_AAAERH yeo_h_Page_132.QC.jpg
f0bbbebfa8368227cdf98f5eadfef67e
0c7de3fddff922a0a78ad525560cf050c77f82f1
7838 F20101211_AAAEQS yeo_h_Page_090thm.jpg
011b2d5bca6c80bff0c74a10c5d8e4f4
307939417edebf450dfa0207970a7726edd6dca2
1191 F20101211_AAAFUK yeo_h_Page_099.txt
db4aecb3c85a7c623fd6fdc88ff24693
d7a32c08b2ec1350f8b2a78d9164fc35329a3185
1662 F20101211_AAAFTV yeo_h_Page_071.txt
6dcc42f7f47d81ba193735b96ed97a74
0ca9d102a50ea2387e3117563e900fd4036ff855
1491 F20101211_AAAERI yeo_h_Page_031.txt
67771427e6459cc4f39e771e701a2cb4
755ec7518ba6f193965983c123af1577b8009cd5
24146 F20101211_AAAEQT yeo_h_Page_098.pro
6064bfaa84f4cd87752183d937eabfe2
097f10d16ef34959e9e78860f9bef62ff2bbd72d
1365 F20101211_AAAFUL yeo_h_Page_103.txt
b8e1430eb5930660a731a0fe4a12c256
2b6efec8cefdf8a6b50b41fe9a1eca5a84ffcb2e
773 F20101211_AAAFTW yeo_h_Page_074.txt
2efe1f4a16d5283bfabeb58622f4093e
a5308d679f37133d4ef503c5848dfdccaaf3f896
30726 F20101211_AAAERJ yeo_h_Page_088.QC.jpg
927e4c17848e366a00572f219d759a10
611fc6fe7b4214f82ce42afb75c06a4fe6842e25
76502 F20101211_AAAEQU yeo_h_Page_136.jp2
d61b10ba85a303bdd2d703e48ee3ce13
8fb482cb48e370e777ca2c307dc4b4041813a2bf
2393 F20101211_AAAFVA yeo_h_Page_001thm.jpg
2c28840989431776507325e6af4357e9
141504efa4416c03ef5968da973ff30e6b711f83
1178 F20101211_AAAFUM yeo_h_Page_105.txt
b68b2076d25e84377193efaeefded57b
235dc775bd1a59a55a47d6e5857f4a8bcd715dc1
1055 F20101211_AAAFTX yeo_h_Page_075.txt
6d363a22607f5a4c8a419ea8d722bfd7
807aae997a408298df85d7a32922e7c7a0828380
100121 F20101211_AAAERK yeo_h_Page_069.jpg
2e5539c3c1ac9cd0fc251e833f5a386e
0b48f8ec1694a4711b270b0e0a7437902dc93191
9403 F20101211_AAAEQV yeo_h_Page_009thm.jpg
b59734da89837c09beabcc886e2cb596
3edc665b4b14f68b2c2d36c1bf3830e6e73fb199
9378 F20101211_AAAFVB yeo_h_Page_001.QC.jpg
a01ca44eecc273c29cc04bb1543c5339
12d7d756efc717b3ae1acb39479c3d7506040a95
866 F20101211_AAAFUN yeo_h_Page_108.txt
36a4aa7c5e835cf36836177cdf7eae3c
6bb58c89efb06f7257339576ac55b7b2d86be951
908 F20101211_AAAFTY yeo_h_Page_079.txt
d48f86a56057fc4549c634d57c95032b
7789ded15c25a1bf7f71dad093fb1090279edc18
7515 F20101211_AAAERL yeo_h_Page_123thm.jpg
222b7441e7d16c92102d5aa281195128
2e24a1eda668a72649e1c77755b5c054bab1bebe
22994 F20101211_AAAEQW yeo_h_Page_049.QC.jpg
2f654ad6dca3c2d4f0fe126322717096
7df4f727c34871e512272efa6fd4aca9b1b591f9
536 F20101211_AAAFVC yeo_h_Page_003thm.jpg
2e53890ac482f080222a04dc200c326e
83129e07467a8428ca37e4c17c36ed09661f12cf
1587 F20101211_AAAFUO yeo_h_Page_109.txt
6057dda90c770164a04560f4974a617c
26093a105e607e54112e533973712a96812012a8
2049 F20101211_AAAFTZ yeo_h_Page_080.txt
eb4d97412d069d10ec6a573dfa211668
ea013f3074f38456d9c13660ae9ef130353a2dd6
98654 F20101211_AAAERM yeo_h_Page_048.jp2
b8ee6f49b03a3be5eb618bb9b9be79fd
4e6a3fc2dc1c3a6a5366a9bac24c2174dd029f13
30425 F20101211_AAAEQX yeo_h_Page_097.pro
6879fb582a93c14d816f9ba83ddeb3ed
f951970734189d4e12cd2368a256d752ed5a7063
24728 F20101211_AAAESA yeo_h_Page_044.QC.jpg
037cd1a2a9d0704817153ba59c8cd8be
7e279e4385c9dd04e1942357bcd329aa3d978dda
1160 F20101211_AAAFVD yeo_h_Page_003.QC.jpg
e75c301211ad2d8f75399b762b3bf93d
f2ce1c98101b1464d86e78c3b4970fa4f47d1b13
1758 F20101211_AAAFUP yeo_h_Page_110.txt
d44d58014ea9a7b16b49a0788935e419
dbf5ad336b34dc4cb603c3dc43460400025f2003
F20101211_AAAERN yeo_h_Page_004.tif
de83a2b5dd44751543fadf12130d651d
fe8e708ba348a2f8eae5e83f2e3ad8245451b087
75265 F20101211_AAAEQY yeo_h_Page_005.pro
2418c9e4fdb3110acf362e1d9b891700
7589448aadcda577270af58c0b76db245a456abd
678148 F20101211_AAAESB yeo_h_Page_067.jp2
2444c53571ca5fbe5bf16e4ef235c323
01970ace9f4d5038c52f2af5bdf55f4ab272030b
33436 F20101211_AAAFVE yeo_h_Page_004.QC.jpg
ad16e1e6ae6e08fb9022d72ea5d82328
9dc14985db9fbdd93a8047ef2ba8de36807801ef
1839 F20101211_AAAFUQ yeo_h_Page_112.txt
bc750903d2aee33601e62e9e017daf1e
3bdda1113a02f34fcc25119670710ed8ee82499a
F20101211_AAAERO yeo_h_Page_055.tif
31043273e215fbf57adea1203fc3b748
deaac773da5815b5513495c455e600f2910bd458
21896 F20101211_AAAEQZ yeo_h_Page_121.pro
f472152faaca6ce4740c8e8099d088b6
95bf6977b5c3162eeedeb907bc499cab464134f4
7791 F20101211_AAAESC yeo_h_Page_102thm.jpg
30433fa88d86ca0d0d2e654d75ca0a49
3631190cbc9e75d4cf3f7efc42eabfedf1361bbc
7131 F20101211_AAAFVF yeo_h_Page_005thm.jpg
b5bb29f03d81557c91f19e4e97814cf8
62a1ca5cabacd124d6e26431ee483b916635c7a0
1376 F20101211_AAAFUR yeo_h_Page_113.txt
26891b6c955f0a0eb530bf8070d5d296
e151ad996a8328b54c35677b085f8079b72cb73e
1156 F20101211_AAAERP yeo_h_Page_098.txt
71dd424623e73f440f5d14f9f7224a2d
b8b7fba8865fdc7e7106914441f202f930873edf
1477 F20101211_AAAESD yeo_h_Page_034.txt
ed9e8e920def27784f55352c87ec38ce
59d94d18cc258521d73509e170e3653a13d0b170
28305 F20101211_AAAFVG yeo_h_Page_006.QC.jpg
eaa55755b2eff8aa4d4f1f8d63a51d47
e341edf326e73badb0b3f93986004a4f202071f4
1741 F20101211_AAAFUS yeo_h_Page_116.txt
651226b98acabe2061530a10c3d69292
d94607dbc55ad5e1b184b8fd7c6698e27e57d936
29523 F20101211_AAAERQ yeo_h_Page_090.pro
63a25176a8f9ce83c52d2f71b8286b39
b8068e300e89a61cc8884cd25a4e63dbbc365355
92552 F20101211_AAAESE yeo_h_Page_060.jpg
353405c6d28ff5e8c61b4f3dc4d15f40
8a28b50fb0c2e9affd96ab6070f6ac1ae2698217
9943 F20101211_AAAFVH yeo_h_Page_010thm.jpg
c299ed07d5e8789eeb935b4f769ca7cd
fa06209c48d7b537ec01ab1953b9bdee7e59a854
1434 F20101211_AAAFUT yeo_h_Page_118.txt
db75632e36d91510ee006fd9355b7a3d
229ad4b7f7fb10e6cc458a0bd076761fa8ee8cb4
1557 F20101211_AAAERR yeo_h_Page_021.txt
d726be74baabf2667a72e116c01b7063
a76d469e8fdbd43d38924be1313ce12cd791f5bc
523 F20101211_AAAESF yeo_h_Page_002thm.jpg
f948cabebfd5a6fd817a2fa7834f0896
f238c0216cf31df5f480584ecdc0c775a7b56c3c
43490 F20101211_AAAFVI yeo_h_Page_010.QC.jpg
81546ea982bdef9e42f6ff60dbdeaed8
dddc84c1c361137678966f38261cfffb68c1dd97
8761 F20101211_AAAESG yeo_h_Page_072thm.jpg
6ef289408887f8356b095d14d8a77764
e563371eee7ad36b0f32c1fa206e060d58ba54ee
7336 F20101211_AAAFVJ yeo_h_Page_013thm.jpg
1c737c3b56d4c3a5ab7566048b9d8b66
f0ad209c06f181bb73f6f0c10e3b6d6443d3fa2e
761 F20101211_AAAFUU yeo_h_Page_123.txt
cb3b49209f3a5b6b5619f2ae14e22b05
d5f7295bff0b89dea126f810d48f0fde232b3f51
30012 F20101211_AAAERS yeo_h_Page_037.QC.jpg
a4b26815c7a363cd777d5778a50bb9ed
b4aee0d6979eb4d9b5fc971d6078b84cdd0d46e3
F20101211_AAAESH yeo_h_Page_051.tif
88a0a50efd23f2fc9bd4018150630c11
6432e95a8d6ca3604486822f0ae0b3101c87a46a
29753 F20101211_AAAFVK yeo_h_Page_013.QC.jpg
8f4c8a814725c806ec2b9d038f2501cb
109d1b623d956ad8ea814d3baf36d8043ceb895a
2030 F20101211_AAAFUV yeo_h_Page_124.txt
2ae1d58c89f288f527634070097bb4f9
24206369824d3ba7aefa82f7cf833df8052e86de
5416 F20101211_AAAERT yeo_h_Page_115thm.jpg
00fd4f0231e94db4b15e7a640f4a8af9
00c1f2211c05105a8ffd1c127e4b7ceab32d8e01
8749 F20101211_AAAESI yeo_h_Page_051thm.jpg
fdd80efc4c676ba24e0d35968ef359ac
ad2589f85634fb78566ead8633769cdb74f5d03a
15914 F20101211_AAAFVL yeo_h_Page_014.QC.jpg
bf777f72309e0b182bcb22c6030fa381
d764e47b09cd408c2eeed8648c403cf0d84ac5a0
1929 F20101211_AAAFUW yeo_h_Page_127.txt
fffb209ea9564091e740e8f2a7478b6c
d9bcbdc0481c2319546a4ffbd58568e1e4b9bd03
846665 F20101211_AAAERU yeo_h_Page_073.jp2
8e3903746d4fb7d06956a4b412faaa5e
3886411678d69877700082633e0bb3d91d6d680b
8452 F20101211_AAAESJ yeo_h_Page_121thm.jpg
895126ddc12e5c05de73022bdb6c37b4
c883549b651e8cf88f30d738975cc2ee9b0b87d0
8108 F20101211_AAAFWA yeo_h_Page_026thm.jpg
f92939f5fc0813d9ccc5162ee947c0c5
9e429cb399b1ff2302b143707d88b42bba5b203a
7775 F20101211_AAAFVM yeo_h_Page_016thm.jpg
c5aebcbbbd23f94aeaacdcf52352fc45
4d6873963d6fb95efd8b29c030407f1e5003a4e3
1984 F20101211_AAAFUX yeo_h_Page_132.txt
6870416827821b4b57ed027cef45d04c
eb7160ed6702bc2ccf8d35af038f2060eb746da9
31391 F20101211_AAAERV yeo_h_Page_048.QC.jpg
aee8c84b9692d0ba806910fe9021d6fd
e0d1b725fa8116a8bcbbff49ea9770ee33496146
131246 F20101211_AAAESK yeo_h_Page_134.jp2
6ffc37ba57730b30885ee575895b99e0
f434a58a6ed8aff256232e913e6c45073a3ff7c6
31771 F20101211_AAAFWB yeo_h_Page_026.QC.jpg
3eeff34a9cffc79b321976636b8fde4f
778f9fdef400c295c7cd56b1712e933de8f13d44
27488 F20101211_AAAFVN yeo_h_Page_016.QC.jpg
5b00884a4f002cc14c906b92b3e37214
28378243c7d4d3e63293046b066b44139f0d4d7b
2242 F20101211_AAAFUY yeo_h_Page_133.txt
8de019c8c5fb73c26718166a0e3ee0b4
2504d20925deb85bfbf3b6314f5dcb079aea71f7
76592 F20101211_AAAERW yeo_h_Page_039.jpg
325308a379bc64cda73243d79048cb37
6993c0b65a4f4759f7f18cf13f0ba93f980cfc93
104419 F20101211_AAAESL yeo_h_Page_004.jpg
23695d5b73339a310c79e63528c5e004
093a7383d5e6efe46742fce81c012a8ad818ce68
30240 F20101211_AAAFWC yeo_h_Page_028.QC.jpg
5ccf41fd553d39ff402f82d9aec7102a
9a3b4197890759910d050dc4513b315b3376050d
9538 F20101211_AAAFVO yeo_h_Page_017thm.jpg
ef967cd725d62827415ec81c9a899e5a
b57ca0f24ee5ae8679abd3a9e26a03be7b87957c
2649 F20101211_AAAFUZ yeo_h_Page_135.txt
340d62449fed3ea17f52db7a297f518c
bb8ef25a59c68d4fd9d3ab5a456a8587281cfc99
15271 F20101211_AAAERX yeo_h_Page_137.QC.jpg
5e1127ca71d8acbd9293e4b63db25062
c3747b7fcc6e6717181d13fab38fa7c0f848666a
33859 F20101211_AAAETA yeo_h_Page_034.pro
c85e1b29e89e4ccb30345fe058ea86c0
ecc4440c4e06ef27368e6484caa37555f0e47759
748086 F20101211_AAAESM yeo_h_Page_043.jp2
a8f98ac8fea06233838ea5fb5272428b
0f90ca8f097d988d2a4b90dd7022d7b8e8937fee
6339 F20101211_AAAFWD yeo_h_Page_029thm.jpg
45970fd26abd837bdee5e038998dddfd
663f4a1715f6243f25db2db2b46086ee64121eac
37218 F20101211_AAAFVP yeo_h_Page_017.QC.jpg
9296275f909583636cd31b321fa003bc
1612abef7dd1a9a08bda4bb4c69962c20473b783
9792 F20101211_AAAERY yeo_h_Page_001.pro
2010c6e1b4300530a33b133fc97d9b6f
df9c7070b239e5c76894bda90e743d314fc5001b
895132 F20101211_AAAETB yeo_h_Page_047.jp2
2fb4df73dfcf207bddc02cff8b1f433f
1e19bdcab1e122fb8048b7bd14015291497822c4
F20101211_AAAESN yeo_h_Page_026.tif
c5283b3624e3025b31f9b0e2a5fb4b50
055a02ba1580982493685e0363ef5f22c96568c0
5180 F20101211_AAAFWE yeo_h_Page_030thm.jpg
de76d7a2992aece4fc801517009b7611
ef9882c7325feebf62438a381b3f75713a4e92d1
8579 F20101211_AAAFVQ yeo_h_Page_018thm.jpg
6a864556bbeee01768685e32b4218404
a7ac37c1a69fce1a1cde48ce630091961b192c31
19982 F20101211_AAAERZ yeo_h_Page_016.pro
38d800fe99e850f168e8bd0d3812d452
47be14d7a924d01a17ddb4e6bc6690d906ec3fb4
9305 F20101211_AAAETC yeo_h_Page_135thm.jpg
5c182a89c5b9b473db037df216a864fc
c93d12e1c2466be974fcff7629dbf39c4cc7e8ed
7543 F20101211_AAAESO yeo_h_Page_096thm.jpg
5c212f31f064aa74811161495a72bcfa
217d621dc67d84fb5280decf0fe23d50b12c4e7e
6518 F20101211_AAAFWF yeo_h_Page_031thm.jpg
ecb5a753362d9211400df0bd6349fe5b
36ff08b5bf939da7e584610d7cdb058d51a513f3
28791 F20101211_AAAFVR yeo_h_Page_019.QC.jpg
4d8847c34295eb0ed5659ded451674ab
f50f80a8fa8049b320746ef2a3406acdff37bc95
71387 F20101211_AAAETD yeo_h_Page_095.jpg
8c119c5b558a7264b170772fdf47abe1
d795d9fdfee36225ec55119bc7d1e491a5b3dd3d
F20101211_AAAESP yeo_h_Page_064.tif
6bddcd62ba22fc072ffdfb47f4e0e9a2
bfe6f58df2c1ad6ecb47162450f8eb4f30adbb7c
6962 F20101211_AAAFWG yeo_h_Page_034thm.jpg
8b012b8cf78aabaae9c1289048696d77
7cb23e8eb07f0d8f88f9584a4b0ff34598d0093e
7633 F20101211_AAAFVS yeo_h_Page_020thm.jpg
adb9ee8dbe18b1b68fb3a04400d9fa45
93a60d5dab54800029b1225535731c5e1dc91c85
78368 F20101211_AAAETE yeo_h_Page_111.jp2
83d4ba43ae1727421124fde0fb7a9c75
571b198954a65ba810f383663db698ccee96868a
9895 F20101211_AAAESQ yeo_h_Page_011thm.jpg
c0177faffe200a4bb76073d555eff452
a4932d0901fa1d76a7d3077146b9ec172c411eea
25400 F20101211_AAAFWH yeo_h_Page_034.QC.jpg
745e9755045db4a1ccce2c369663a026
ed0d894bf110f19c39a3e7a4fe5fe2f9156f6f1b
7279 F20101211_AAAFVT yeo_h_Page_021thm.jpg
19f1c77deb030fe4cef0c4ef7bed1bb4
a9f3f0abaf21adbeda84f94359108e2654458d37
1958 F20101211_AAAETF yeo_h_Page_004.txt
48d4711f9764b2a37792989059decd74
c7e907efcacfa52e713a5fffbad77e1e2fb80c5a
79799 F20101211_AAAESR yeo_h_Page_020.jpg
f5f7e97760d6781ab8b0e40bab115d11
ee1154092381d433fb12c2a9d6039e5fb72db29b
6784 F20101211_AAAFWI yeo_h_Page_035thm.jpg
e97e7b75bd37a644e6651a80c96a7d6f
1891dade4032078489f19986b7888b77062ac354
26054 F20101211_AAAFVU yeo_h_Page_021.QC.jpg
cbd0e944d6815407834ea3c50c694e82
83654843fcb283dec534514173374d3e871d10b0
F20101211_AAAETG yeo_h_Page_116.tif
7c61b489f36ddc8ffbf466ef57b1472b
3d62bdf2c3834247e5ff7916842a9ba2e5cc1989
1269 F20101211_AAAESS yeo_h_Page_076.txt
e5fd0efda4b746c78bc768021a78fc51
73165946c14bd7284fc8d62558a1a1a143f8a1fe
25733 F20101211_AAAFWJ yeo_h_Page_035.QC.jpg
1faa8918fb7acbd57261a2aeb537ea40
092f6bdce57be79c19e2f5e9499b58b5aef1e732
37679 F20101211_AAAETH yeo_h_Page_122.pro
bbf2630911774c78f934f00b986f9629
24afb85189b330b574ce4d7c95425267789e268e
6946 F20101211_AAAFWK yeo_h_Page_036thm.jpg
73fc97c5e9e9140d139fd42022b66b59
a8ab6fb1d11a06d9486f490ceae940800f66f8af
8654 F20101211_AAAFVV yeo_h_Page_022thm.jpg
3f39904e6dac43ce21f42cab740de4c1
0f5b6778e2bde795d179329cf8af022a5f8baeec
91 F20101211_AAAETI yeo_h_Page_003.txt
cb9a23620b8ef35a75406a4d98c0343c
65f4ac5995f133a3129b919ff7c9b6a3a7cbc701
F20101211_AAAEST yeo_h_Page_075.tif
8cdabf1edc6b5987a9b0e882fe2eef09
bff424a40cdf7a40a5d1a4481ab927a14b73bb01
24346 F20101211_AAAFWL yeo_h_Page_036.QC.jpg
6d31992ecb567d4d1c9d41a3995d76ef
8ac464b8313d2a7e8444b1d226d789a865ed0619
7341 F20101211_AAAFVW yeo_h_Page_023thm.jpg
1bcc2837234801a48d046d593b4b66cf
d3f116ed29bdc92912267c62b3df8398d9c90d06
F20101211_AAAETJ yeo_h_Page_034.tif
373c1d5b6fd8649fef534f0c5e835fd6
7224a8920ad1abcc7138f137267b397df9101c34
2431 F20101211_AAAESU yeo_h_Page_008.txt
df7d23f6d08c5028d023bb809124bd55
f20e19ba3fdb396b1892f056fb813de143d8685c
6968 F20101211_AAAFXA yeo_h_Page_054thm.jpg
6be7077fceec556117c3a98df77ca7c8
2ddb2adbd4e480b511135b480dc77748b806b45f
7061 F20101211_AAAFWM yeo_h_Page_038thm.jpg
ee5b25d82ef6106d4a8973cc2db24ed3
fcd530da6501b3b218a11d72a7adab9d85bc8ebb
8425 F20101211_AAAFVX yeo_h_Page_024thm.jpg
1809ab0a87455a834dced0b0f604a2c0
7f5102f4345e0f563acca7b517d487aea78c08ab
25029 F20101211_AAAETK yeo_h_Page_054.QC.jpg
e74126e739f56cc961e4cef5803e55c8
c89b4c1c30960d8c35d79a2e88b9e95623599b1c
32668 F20101211_AAAESV yeo_h_Page_033.QC.jpg
1b0a8e9e05e9ec31e931ba3b2dea62af
547860eb6f72389cdfccb1abb5293f22f00e13b6
28568 F20101211_AAAFXB yeo_h_Page_056.QC.jpg
b65ac8a9eccf24b80d5047fe1d84b955
a334b6325a1160c47e529a677dbe2d2372094d6e
25553 F20101211_AAAFWN yeo_h_Page_038.QC.jpg
f3ef5c257b4b4a3e26516a8c5a8fafc2
dce6ec5c0f18c658579b671240f576a7d4d53479
F20101211_AAAFVY yeo_h_Page_025thm.jpg
5ccc92d257a8a3a71e39c4546fca0c08
c5cddf2e6542630d6f460b687be2107103c44da3
27401 F20101211_AAAETL yeo_h_Page_076.QC.jpg
892ba76cdb8bae1f3458e8d644fc378b
ea0752c5a0425c41757a9247fe88346190280bc3
37180 F20101211_AAAESW yeo_h_Page_037.pro
96be4ff343ec84924febaa5bc3b67c42
89d908914a9bc2805c8f5a5ea1e82e84ecce66e7
4263 F20101211_AAAFXC yeo_h_Page_058thm.jpg
2f58a734c972a7c3c3148e3362936513
a04674712f03d79887289387400686427f56cd66
7086 F20101211_AAAFWO yeo_h_Page_039thm.jpg
302cd7dc28b7aa75e6eb7d208da2ed3d
8eaeee0280747217545a6d27eb49ecacf759ccc9
36056 F20101211_AAAFVZ yeo_h_Page_025.QC.jpg
dc34ee24f921a7aa9e30d9883e94d162
1ea0767cd21d2d67b304fea2ed662fba73956158
1321 F20101211_AAAEUA yeo_h_Page_038.txt
a4de58684530f17b02153b683b200288
0e934ff57f6f5aee479b3c4e2399a51c3517bd67
1806 F20101211_AAAETM yeo_h_Page_056.txt
631cd7cacbd09f35558909efa475328e
e47ceb381d4b501aa2408c6397c2d47457273096
8376 F20101211_AAAESX yeo_h_Page_033thm.jpg
66547960b6d2a87e7f28d6337d504048
32c6a08a1aa3db26ce7e9d807a4c07b1e3c78ab2
5717 F20101211_AAAFXD yeo_h_Page_059thm.jpg
47cc3da6d00501191fb77a59253e322e
4aa89531312306251dc5a70c17621fa3383da538
6666 F20101211_AAAFWP yeo_h_Page_040thm.jpg
0ec2553b13e71e4117704215f1da4375
5c2c53bb84b3c366339cd3d8a7b09d868ee90043
81520 F20101211_AAAEUB yeo_h_Page_097.jpg
a8a5e97d25db40d40e4ce0f1ffee60d0
ab6c169e80113675819815b7be3678f1fda822ea
21282 F20101211_AAAETN yeo_h_Page_014.pro
78244b69abd7193e86d87eb220e30070
0b9b55f30cabca0b9b67f39a88a4439fd3c3ad60
72877 F20101211_AAAESY yeo_h_Page_046.jpg
76bc065325fbbbff905c57e24e29dc2d
4a574f8d09b77c194ced53fd54e77c38c6e3c96f
19307 F20101211_AAAFXE yeo_h_Page_059.QC.jpg
0282caae4326a2563ce42a6726d2d2c8
a06f9df4122ba805271dba4616b1c29c0a860ed0
7669 F20101211_AAAFWQ yeo_h_Page_041thm.jpg
09f76c436c2e2339844eaf51576fb260
6f4a7bdf3fe3ff7818705635b90d8141e133fddf
101159 F20101211_AAAEUC yeo_h_Page_015.jp2
40b1778d78a51fd882837736dc19ad17
7867350a3f9cc1801f0448d38e6c81bd3426ca91
79840 F20101211_AAAETO yeo_h_Page_031.jpg
cfdaa6776304fbc741eb0965ca780c5c
49b6424b0b14bd26b5018a3679c023af124fe1a6
1689 F20101211_AAAESZ yeo_h_Page_131.txt
29b09c55971c49b27e0ae4eb74f32257
febbf8471da25c978f72076c61cd1c5c4ec48c5a
7778 F20101211_AAAFXF yeo_h_Page_064thm.jpg
b9509125f13966d7e90971681711636e
b1766f2337a5e8f6a95ef93c88fd983a4e7c902a
F20101211_AAAFWR yeo_h_Page_042thm.jpg
7c4f1b79349daba218de13b81a8a63fe
4bc205df84e68580445a30964a0fd3534e8a33f4
1345 F20101211_AAAEUD yeo_h_Page_030.txt
158b105b52a2cad9fed05defc427be4c
6ac75a74e562e27011d69a3e9273d81b6e8e51fe
1420 F20101211_AAAETP yeo_h_Page_136.txt
f9c1019c955d65690ce29efdd8165d23
66e2a258f26709d172fc302988027c8ac7473ac3
24504 F20101211_AAAFXG yeo_h_Page_067.QC.jpg
d07c82465c229b53647ec713d89ce2a0
9e4225faedc862c47a37529d5dff1925a631e859
6059 F20101211_AAAFWS yeo_h_Page_046thm.jpg
a2a7f24aae0ace61c03fddccd10205ac
55b0a20c233b8bb810a41f1ae1051bdee4971306
38626 F20101211_AAAEUE yeo_h_Page_132.pro
711e8cbf0f15aa36618b426e65710181
857d220fd192a47e7e35ee150a46a445856c2fee
1350 F20101211_AAAETQ yeo_h_Page_107.txt
44f47efe707d11d29be3b27533db254a
c402952024bf41c6fe8f88effe1a8334bb34ea97
6901 F20101211_AAAFXH yeo_h_Page_070thm.jpg
44596451ac7db7bd58e470cd5bcf067c
dca603189144dd06cd1c2448250f44e735dd5e51
23589 F20101211_AAAFWT yeo_h_Page_046.QC.jpg
9aaaf7f70a25eedb481c4feb7667dbfc
e21d646b7edf2c92f8cda7aa14a0b8678d4082cf
979 F20101211_AAAEUF yeo_h_Page_068.txt
74af2e4b33ce518dc1ca36eb2710863a
d324019e2e3f4552a1677a156974a9877a56db32
32012 F20101211_AAAETR yeo_h_Page_012.QC.jpg
73e5d790b1d06d7ebf7adee1916c8cb3
fe4ed559350b42049ff6594c0a9f527352e772fd
24447 F20101211_AAAFXI yeo_h_Page_070.QC.jpg
66dde2a4b7cfb8fd230d0aea1ca6a29b
0c1e21ac12ec0541dbd474e390285a6f335cdc87
28667 F20101211_AAAFWU yeo_h_Page_047.QC.jpg
c56efbb9f32ee75800ea8fa4764cdc57
2ba3a770a9c44fdaa64a3405415d3a0d639a181e
108833 F20101211_AAAETS yeo_h_Page_093.jpg
fe1df8dd3b2a69ba43284c06d0d0f7c6
0973c9f443a6c8380126d6a52f3c0e3a32b2d379
19725 F20101211_AAAFAA yeo_h_Page_115.QC.jpg
32cb74e62eacbe87a2b7ba1a65680728
8972244cf26bb16604ff81870d76ed7a64a896d2
32170 F20101211_AAAEUG yeo_h_Page_130.QC.jpg
54ea629f99827b95f7377c148e0fd243
9937fbba4dd276d16541a488001a26d170622e45
8504 F20101211_AAAFXJ yeo_h_Page_071thm.jpg
ce9c8ca53d9031a93aff8667aa0e49cd
69d9ecc250ea1573df2b91bcf24e9a78b8dda218
6340 F20101211_AAAFWV yeo_h_Page_049thm.jpg
1b17681f57d91fe50c5eab086457d229
04c033685fcf22e9f88eb8c307736edff93eff18
112688 F20101211_AAAETT yeo_h_Page_133.jpg
feaaf747adeb8c10ccdb2a398d6f92a6
76811f9c955d1c76d4d97c82e2db7cfff34a1dea
F20101211_AAAFAB yeo_h_Page_125.tif
2a22a78ea502cab05a71ee3083563122
7fa07dde028f0abbff87d66b6edd3a8ac09e3948
14142 F20101211_AAAEUH yeo_h_Page_058.QC.jpg
f45fc1b71fd9c3de4bff2af79a8d2ae6
767b50bda706d09edda6378ec7a2c2ee61582534
30087 F20101211_AAAFXK yeo_h_Page_071.QC.jpg
b2292f35a2ff7b9eb57129679c43ff03
be83fbedd9a7f70bee9492929006532fb01a3321
5752 F20101211_AAAFAC yeo_h_Page_114thm.jpg
cdc9d45f5e812dbad2fc22fb9fec4a9e
a50e0cc43bcea3537200452e85b87bea5c3ee70f
33331 F20101211_AAAEUI yeo_h_Page_019.pro
f66532bc3aa7c050355848df45fc8ab3
8caa6a5d17a37718f2c4740e18d0b2e9435bb3d1
26392 F20101211_AAAFXL yeo_h_Page_075.QC.jpg
dc857c3726c86828dd11b7d19c1ec8c2
1e91603e48208c6e3be5d9e26507d7f4ab714152
26522 F20101211_AAAFWW yeo_h_Page_050.QC.jpg
935c0945ed7b005c9cc6f92527315053
3159448f99384a4035f4fdd142358d46f89eb4f7
F20101211_AAAETU yeo_h_Page_033.tif
9cf8122c47b055e7096b6fa940dabc42
6a963d91f17dc9110bb0f418dfc33f73049b7277
89494 F20101211_AAAFAD yeo_h_Page_061.jpg
aab2fde490422d3d4f7ced639bbcd15a
171b62483517d73aa6f2a3ea8615e1077da52964
35360 F20101211_AAAEUJ yeo_h_Page_080.QC.jpg
6687ba28ea0d8dc11044cbeec1177652
175f86b117fbd0ae7e7de152b6a5f27572039a4b
29780 F20101211_AAAFYA yeo_h_Page_094.QC.jpg
8e25224c17d140c219ed94216c187e9a
742a7f12771f9d15ed1ec45dbb8044f029a5e1b9
7889 F20101211_AAAFXM yeo_h_Page_077thm.jpg
ca4d28f0cbc5484eb71dffd8245606f8
1112df01ed8ee31717e949f51a05f87b8eede676
35295 F20101211_AAAFWX yeo_h_Page_051.QC.jpg
f0a5b27fbe26cc6000ba53e24b381c22
0b59daf287e05f594356f9507a936db7a44d47d4
35674 F20101211_AAAETV yeo_h_Page_022.QC.jpg
c34571ee22a473b67156b23dfebd222a
a37cad56a985f85e24725f19609a9038086140bc
15763 F20101211_AAAFAE yeo_h_Page_126.pro
5a50cd4fc49ecfbfb23dc32da68fdf99
4a9c20c2553078a13483843be0d964cfeab7240a
47582 F20101211_AAAEUK yeo_h_Page_091.pro
b0edd813f4f3927ecea1bf4890b37a66
a2cd45de049a2af2432fb37b27ec04c81ced7ed3
30597 F20101211_AAAFYB yeo_h_Page_096.QC.jpg
5d5af45915a3a704eaa9da737824906f
7bd8f91ba280705f9f77233c47cd6bfb4b09cbd2
28049 F20101211_AAAFXN yeo_h_Page_081.QC.jpg
dbd45a9b93dd57fddca98e5e182b1be5
31a30006d80d1beec19c7c230e7fdfd5d6b730e3
21319 F20101211_AAAFWY yeo_h_Page_052.QC.jpg
4cfefb71a7620d4fe08c5af9854b12b4
6a1c6de116184ab561d51a89b7c48c1db4eb1f03
103749 F20101211_AAAETW yeo_h_Page_125.jp2
e19e76fa0cc493981bcdb35dffa603ed
27badded67771e17ac92d064c6abc2e4ed9c2485
27110 F20101211_AAAFAF yeo_h_Page_038.pro
2eb79bd65143b576cec265497a964600
bb7db2c2b66b3633646757f1a7dc45d61ce0334b
1510 F20101211_AAAEUL yeo_h_Page_066.txt
597c206a7937dac088e5214d771b814f
5e0db45a9422e0771daa534c04dbf59363fdcd54
7577 F20101211_AAAFYC yeo_h_Page_097thm.jpg
5dcf919ab42cdeaa69a22854214dd97f
5f3b314a18edeec7b1b1853e2508b1a1467a9d20
32239 F20101211_AAAFXO yeo_h_Page_082.QC.jpg
d6ad62c53be93dee4b0cd7120b1c281a
2ff8efdb2902ecd439abedf5fe8acf45a2ae5aff
8298 F20101211_AAAFWZ yeo_h_Page_053thm.jpg
768059f9adade079c67ba4fd611bf784
eec3c7e5cec72d869518698a7ea4d93090545dee
F20101211_AAAETX yeo_h_Page_081.jp2
51219617a7071fa67d5d41b27e7ea604
8b7180a3c9f016f99ba7f96916d09de3775a6c6b
1486 F20101211_AAAFAG yeo_h_Page_062.txt
03caa38d9bc7862e7ce01d7356765305
159db0ba804dada9fe601f344329d656069b0209
1414 F20101211_AAAEVA yeo_h_Page_020.txt
88b329aac93f3f0b2c8f31f7ad33be7f
811f12f131d2d8f0770a37d403d720cd2b235e08
34521 F20101211_AAAEUM yeo_h_Page_042.QC.jpg
4d797c77e422dc1634a98eaec61942c2
f7652c982f3cc9f96b8e475883b674a02baf09d7
27568 F20101211_AAAFYD yeo_h_Page_097.QC.jpg
3b331a47c01b50161f5d1365a3cbc080
785803ac0d2d6998767856856df6e61061678854
28622 F20101211_AAAFXP yeo_h_Page_084.QC.jpg
5f35964008bb2b54ff2f2f9a6d599de7
415d25914f072584098e26b464be15e7f9ba6a3f
6845 F20101211_AAAETY yeo_h_Page_073thm.jpg
4c208708a5a41b696580f8cc79fd9d65
8b420116873fb1ba297f526462e687b282ded387
783007 F20101211_AAAFAH yeo_h_Page_097.jp2
cadb34f7a8542e2576b03768b45e457f
e6da0baa3d5756f03a2230e3d1a65d07f9c8d4a9
5266 F20101211_AAAEVB yeo_h_Page_052thm.jpg
4f8732efb225dda17524d686dfab733a
e4d9634c8212e36e39b6a6b30ff6c8f23015b2ff
987 F20101211_AAAEUN yeo_h_Page_044.txt
c3778c029e7f95a591a83eb0eb8c127b
c0e99176cdb6fe9bdf18d72ad95b0333232a97e7
5702 F20101211_AAAFYE yeo_h_Page_098thm.jpg
6bde465f224ca0e0e7550c6e46882cc2
32f6e6cfad0f2e9466712e6313ef52cd96c1a45b
29914 F20101211_AAAFXQ yeo_h_Page_085.QC.jpg
1d6b775785675dcb9dab95ff8e2c869d
a2c445fb0f0db19fe7a3b8d57b1b37ca88ee374a
20997 F20101211_AAAETZ yeo_h_Page_078.QC.jpg
f44a563334757994ef335c0b5d7d5b5b
f5c5e598bdf871ca09260de48efa437d7874adab
99351 F20101211_AAAFAI yeo_h_Page_118.jpg
6d20d58ee93917bc5798688941c81e52
6fa314a2dfc17b669ad4193aa7e17b243416ab2a
1051960 F20101211_AAAEVC yeo_h_Page_075.jp2
1d4f7f622029b84a00319dea0f363815
533f2adb6d6e86edc28d009550422e3f66250935
2112 F20101211_AAAEUO yeo_h_Page_022.txt
bcc508a4440022871a9eccb0620bc784
f1945e6faf711810663b2d9cd0995e3825247f88
20778 F20101211_AAAFYF yeo_h_Page_098.QC.jpg
f99b886e6e5e97fdbea95692cebd9cdf
f44d01547eb33fe7b393ed9b141855cbd72caad4
27445 F20101211_AAAFXR yeo_h_Page_086.QC.jpg
0b3924e19e8fed30bfdcf7487a26e15c
1f545a460d7a43c28ad9eef65cfa09edb4a59fc5
100957 F20101211_AAAFAJ yeo_h_Page_127.jpg
f26d4747776e7a643d9175a632e87a40
629b1eaa9ccf2a0e4a631c928c582041356d6efe
6771 F20101211_AAAEVD yeo_h_Page_067thm.jpg
b3516362ae6ce94ce4d8d59bb57e93ea
a67cc451e3ec4e8b6a2a2241ed0ebf7c8db2844b
71148 F20101211_AAAEUP yeo_h_Page_029.jp2
00be1e60a9b1ba90a086ab77b70c6a3f
9b8cdb95d4e3a3c994792f4351c9517f9bbc1643
21568 F20101211_AAAFYG yeo_h_Page_099.QC.jpg
df3a3c90ccc2eb609f753f7aeb8bb670
5592c5943b8535b1045314f99289202f9a098e16
7917 F20101211_AAAFXS yeo_h_Page_088thm.jpg
6a8f8479e055a4c3127b8735f3e696e3
b40c4588f2de9c5eb924949d2b3c0ed2ee3368df
1325 F20101211_AAAFAK yeo_h_Page_114.txt
30cc0ab4bea7f48af5c8b6d756ab9ff9
4bcd276c2baa3070b9a45c2a9e076367bcd72a5b
6795 F20101211_AAAEVE yeo_h_Page_044thm.jpg
aa220787767ff337d27e949e2277570f
f2cc3db22c873181cc7e34e9bc3bec04d965b3c3
96284 F20101211_AAAEUQ yeo_h_Page_015.jpg
43c4e94a97cfcde63bd3b9265abfaa4c
3cd8adeab17f09e2e52db0ba5d1511d9d4d1aa17
32539 F20101211_AAAFYH yeo_h_Page_102.QC.jpg
24375c4bb25e433221d8431adf681a5f
53db025d25a39a3d51ea6bfa6d0a73b4ac1ac994
27130 F20101211_AAAFXT yeo_h_Page_089.QC.jpg
daa896bc2fd7af4c529b136291961b18
3a4532228f8937e7a7a68ca91763a6ab1402cf19
1814 F20101211_AAAFBA yeo_h_Page_060.txt
42397d877de773859bacccf4766df5ce
1626ebf094f0b8cb9d087a6336436458bb6d1809
103284 F20101211_AAAFAL yeo_h_Page_102.jp2
1697fe7c5b484730031f2e8436bf4317
d79bd2aea35d0e49e53256bbbc4960a301866004
1499 F20101211_AAAEVF yeo_h_Page_026.txt
1607dca6d82e0b34055eca1b7f73acad
02e2b33d2b36e4bb57c13a043f6ca739473c9ab3
30590 F20101211_AAAEUR yeo_h_Page_129.QC.jpg
b6103bbdb60e0aeec6a2c41cca51f48f
5d9e87c452d8e3158475e4c81c357daa7be7f884
23888 F20101211_AAAFYI yeo_h_Page_103.QC.jpg
73fefc91d239a777815aabb77d343890
47cb26623047a877927fc2d0fec5afb2ca478ce8
33817 F20101211_AAAFXU yeo_h_Page_091.QC.jpg
464c862fb2264d17a6a22b903807a77c
c10a6f7ecf3d5409cc1bd0ac4c6a6a8ec635b17f
21189 F20101211_AAAFAM yeo_h_Page_027.QC.jpg
b25dd34d81d366dc9c01dea9cce4f59f
222d20d259f1d5087f905dc241118baeea073592
31442 F20101211_AAAEVG yeo_h_Page_085.pro
c2bbeb04598a4bd08f55ce45f647d6ca
f046d6f6d4221f4d4aa60ba03d642567818320b5
F20101211_AAAEUS yeo_h_Page_094.tif
59db05a2075d3d079600a59da13c25b5
b537e84cdc6c60333f7fba23356c0cb2d28bc64e
22999 F20101211_AAAFYJ yeo_h_Page_104.QC.jpg
3bd1e0db6bd6c7f236957dbb3a545f9f
a3eb69e7c424be0f86f05fdd8781d7e1fa1455e9
7932 F20101211_AAAFXV yeo_h_Page_092thm.jpg
a7fc22c64bb9b418022d617c8edd0bfb
83d5f20064aaadd64aae4bfb607f14736e3ce586
95451 F20101211_AAAFBB yeo_h_Page_116.jpg
de928b91ee0ec87cc876572dc9514f0e
89a6256f499125ffe165502a64050d10fdedee0c
24839 F20101211_AAAFAN yeo_h_Page_068.QC.jpg
dcae1789bc38f93087ba4403982360f8
fa0ae4818f4f0c1390acb84bfc2bba08a16b4520
32405 F20101211_AAAEVH yeo_h_Page_021.pro
b3d1d4236efd40a0032ac285399e59ae
d4257036b47e13505a524916489eba2e2ea38e80
20737 F20101211_AAAEUT yeo_h_Page_007.jpg
b4ae4ab4d1fb958ca56528a4653d8165
b4acd5b1d7e14474cdc5f135d1c9e4701510877a
6551 F20101211_AAAFYK yeo_h_Page_107thm.jpg
7908d13b25361a15d2c57c19d584fa3b
e24cc873d091a3aad77ec419684ccf75902d4d58
29552 F20101211_AAAFXW yeo_h_Page_092.QC.jpg
a34d6de0eea6cd005030844bb0bb9ce3
53eb3d71b9ce6fba64e0f6430c9511129d19d82b
F20101211_AAAFBC yeo_h_Page_023.tif
c20720ffc4abca04c427ae3b22d63799
1a12ba882a698636abceda172d134f8c21d5dc64
1470 F20101211_AAAFAO yeo_h_Page_024.txt
3af90e74f3e4a6dc63bd51ebccccf081
ea57adc2abec82526489bad0aebd14e3abeec739
8102 F20101211_AAAEVI yeo_h_Page_112thm.jpg
e42e6b626d2bd4949317ff11e5f3fdab
23f74b07ed89fba993dc4d92103a973a84621943
6456 F20101211_AAAEUU yeo_h_Page_063thm.jpg
1a4962db810b41a9158137bb5c8928ca
d6621d4245c6bb4382a174dff78847ae19f3fffb
23250 F20101211_AAAFYL yeo_h_Page_107.QC.jpg
88170a5aea411239a48d532b90dd7f2b
61c63aefb22cf7993df20a34edfabed0af42381b
8623 F20101211_AAAFAP yeo_h_Page_124thm.jpg
eeb28cbebc42d305db00debd3a59a2e0
407fa65a94b7d50b5391e132fb871b8b51e322fd
8401 F20101211_AAAEVJ yeo_h_Page_060thm.jpg
dcbf216bdf95c2775ad9eb928c873276
6cf193791f46b650ce0cc092b7e491ae493ea6e6
F20101211_AAAFBD yeo_h_Page_091.tif
34411d4a1e4aec54aaf18a9771dfd80c
0d7566bec8a6bd6fd303c14f2e632390a197cd33
2952 F20101211_AAAFZA yeo_h_Page_126thm.jpg
60950bed42a9ba636d4a335cfda69d9e
ad9b1121b396b0285784c8b102f60a25484409f7
25622 F20101211_AAAFYM yeo_h_Page_108.QC.jpg
554a7fd48e553b400d6d88b6dfff3e3c
b6eaa1d2c357ceab9d7942063e972ee96d7de7fd
8769 F20101211_AAAFXX yeo_h_Page_093thm.jpg
28d99042cee25f49ccdb87a40ea062b5
ab4b00527e8f0b48f19b818ebcced967e467fd1f
30125 F20101211_AAAFAQ yeo_h_Page_081.pro
583f4dd3bf3befbbed9e47cdd022c54f
fbb7d5cc51bd58ba536a3f4f25e951effa3a64b0
105860 F20101211_AAAEVK yeo_h_Page_091.jp2
8900daa6596a7ece16f71e13889a800d
c98e7e6c2de52bd5e366ca3c349085f4215b60b9
24554 F20101211_AAAEUV yeo_h_Page_059.pro
642622e6265ad6f18a2db38e49987a26
23d5cdef9fdee4927578ee524bb221ea99675aa2
F20101211_AAAFBE yeo_h_Page_056.tif
702d48fa5676f07c525345e80b80ba72
1ab90535e18d60ef671ef41084f2ee18c4444e1f
F20101211_AAAFZB yeo_h_Page_127thm.jpg
9e80c9941600ef2b8b2b8f662f96f96c
0865a15886f0e1a63ddafc655d146315eae90e8c
8049 F20101211_AAAFYN yeo_h_Page_113thm.jpg
d65f1976144401b3e83b24c8dbdd25fa
5d93fe3386c5ea6867809717ff8b8138053fb4bb
35644 F20101211_AAAFXY yeo_h_Page_093.QC.jpg
a315b379c7ecc80c2b396d3e38d09eac
362571a77f38a1e68b2ee64b2dbbddfaaf93b414
28195 F20101211_AAAFAR yeo_h_Page_066.QC.jpg
cb5f8cfb4f274f3720504d4dc19d18f7
7a93e55fd173a2005cc40227cd8f7540998fa413
6214 F20101211_AAAEVL yeo_h_Page_027thm.jpg
c7dad6a945f9445a9a6fe0d045f39a17
438cd1aea61493a638b390a37807851526118448
77373 F20101211_AAAEUW yeo_h_Page_034.jpg
d871974d2927dd08d8cb091615714883
920ed3dc190ce841f66d1dd01ceac069477b12c3
28611 F20101211_AAAFBF yeo_h_Page_043.pro
689f9ed576e43b673685572227c90164
52cf9de67d2fbc4e8efdbbb098b14d93dac10b36
34010 F20101211_AAAFZC yeo_h_Page_127.QC.jpg
4cf1ca5ff2820254f004a3c54b3cbcd6
e39b0737ba39201446a78216e27cad9584318aee
28719 F20101211_AAAFYO yeo_h_Page_113.QC.jpg
d67156539f9784542f9fcac5b801616a
1dc6108d2f91c511db1dd3ceb84e41d697a578b2
7684 F20101211_AAAFXZ yeo_h_Page_094thm.jpg
93f46beec2e7107e59eb97a6beb204fc
3d47c772afa543c343605358be611e08adbe855f
20642 F20101211_AAAEWA yeo_h_Page_086.pro
4eb8c508c29d965d7822c3bafeeaec42
528aa5a19cd2d0b382472275d596f21db6cf554e
1519 F20101211_AAAFAS yeo_h_Page_019.txt
de8dc80e5b410974de6bc3c5b59d2506
6b6243b2df177ef8d549f0e6ea7d785f8dcbec00
95542 F20101211_AAAEVM yeo_h_Page_088.jpg
b918c5812ea95473192f411c37356e6a
c38156df49b610c5fdb860fd8ec97ac817d4d5cc
34130 F20101211_AAAEUX yeo_h_Page_053.QC.jpg
b0a7d58ffb3bce4cd9a147e6fe8a0544
5a935d5895ccc6df8f4a4c4a24d9efb058f9cd71
23608 F20101211_AAAFBG yeo_h_Page_029.QC.jpg
c3cd01a3026471c27cfc3715a37e6104
b0d78e37b3477952c045e8874b391b453cc36ff6
8815 F20101211_AAAFZD yeo_h_Page_128thm.jpg
d78be6dd13116c3d2b748a5a607afdbe
ca6161e4828680e5180e437297ef569993a2b7d6
8524 F20101211_AAAFYP yeo_h_Page_116thm.jpg
c29a9e3c21f31995dff82f372dcebd3d
9b39ca2ff69af624873dda9ae641ec7df8422867
17746 F20101211_AAAEWB yeo_h_Page_089.pro
3f71f8f52002be46aa0f99abbd6d207e
014745b3b15255505906d0710f4a8983220119d2
F20101211_AAAFAT yeo_h_Page_005.tif
124c40361e2ad6f1f0246c415cf239c8
b449caa84b061b946cdd95242b3ec37dbe93c41a
24889 F20101211_AAAEVN yeo_h_Page_105.QC.jpg
8cb70d0874d779049019e01731d4ad7c
416e056d38649cbb739e73d69975066f024931dd
882533 F20101211_AAAEUY yeo_h_Page_105.jp2
4d32e10297a22e6bea9ce575a92445ba
8e178ec1deb3a72312dca2c6ce087a22602313b6
73549 F20101211_AAAFBH yeo_h_Page_057.jpg
76c465c3a84d0593b8f2266486008ed8
941154ba5321c39097cdede8b2b5ed817eb37983
8084 F20101211_AAAFZE yeo_h_Page_129thm.jpg
df3069e56934e3d9fd20e94b0754ef32
b1cb17a4bccc86ed7ab4cf3704a52a23d75990ea
32557 F20101211_AAAFYQ yeo_h_Page_116.QC.jpg
f153442596eb7effb234562b8f4ecc15
4b57fc1470bff91383660ba0c0ba42d5cea465d0
F20101211_AAAEWC yeo_h_Page_017.tif
7e213e820ba889c772ab3b8b71e473b8
c9287d8c2cf826ef5aee6f7715685356c06d9c44
1051939 F20101211_AAAFAU yeo_h_Page_055.jp2
2503f2c93ab81951605f5da196dddcc4
6718f7a9bbbd844eb3e4ef5377ae9cef71f3fd45
F20101211_AAAEVO yeo_h_Page_070.tif
d066ffea5e1f9e724c7fb3d46f7d80c3
45f0ff91a1c73a64e9770bc921d20809104b63e4
824298 F20101211_AAAEUZ yeo_h_Page_038.jp2
31a2a5ca868e28b13f7a48e1784e0530
45c58ca1425f78144a45166c38fb7c3bfec16fa0
1051878 F20101211_AAAFBI yeo_h_Page_012.jp2
ebe452469bd91392e3e440f155edd4f3
93b93211e930601d3a0735e92dce80156fa71f41
8119 F20101211_AAAFZF yeo_h_Page_131thm.jpg
17ce1bad214f6de605f4756718fe1d29
e719be646244de92ca1cc921683367926dc914ce
7327 F20101211_AAAFYR yeo_h_Page_117thm.jpg
97439b45a9c8312f79c2eb9e5c007fbc
491878fa651235b82694becc3dc2ac232cebf969
6980 F20101211_AAAEWD yeo_h_Page_075thm.jpg
a25a7722a7c4a91cac0fd8dd1a7886a3
956bdd5a2742c3c808dd598752361fe082857c66
24952 F20101211_AAAFAV yeo_h_Page_117.QC.jpg
50f9c599ab41e4736da27fda75dbb642
2f155a46c27ee8fcdaea4f7c671074197e7955ab
F20101211_AAAEVP yeo_h_Page_012.tif
0e3ca63e6401971ea9c5739bfd952669
055f4d171f202fda36d4e45575c1cba0b2834f3c
101505 F20101211_AAAFBJ yeo_h_Page_106.jpg
704438013d971d03618a1835a3482fc6
773902da40dd4f08718ce5e55fffd37995428cea
8603 F20101211_AAAFZG yeo_h_Page_133thm.jpg
602b287d5baed0d3537d191d42046c33
de927603742069b4f9fd98bd5f6729430af9c4db
7846 F20101211_AAAFYS yeo_h_Page_118thm.jpg
5514c4c8d353aa0d4242b305f4834be1
a876e885147bdcb5e58d75160c0dd644a1df2168
F20101211_AAAEWE yeo_h_Page_097.tif
44d1eccfbf73b3538caead564b571718
5dc3399ad59983603331b001b4dba6a769925760
F20101211_AAAFAW yeo_h_Page_133.tif
64458b98d4449228115c26fad5ea1260
4d4ce6e93c413137aaf7097f71dea9b1fe49271f
8352 F20101211_AAAEVQ yeo_h_Page_079thm.jpg
148f50ec96e204c6b5e5967382380ca1
3926de2ddab73332f46fceaa0d20d7e1f5c2c3a1
20015 F20101211_AAAFBK yeo_h_Page_032.pro
dfab337043ab7b22f781c262f0ce63fd
88ce9f4ae3b145ce938c0805bb52f326d7d3f18e
37955 F20101211_AAAFZH yeo_h_Page_135.QC.jpg
099c504f9e7b0cafad7a7fcd1ca36a6e
31b770d946b6905f7cb5e58d8c2647f149f4afaf
8772 F20101211_AAAFYT yeo_h_Page_119thm.jpg
ac724a8518b9460fa496553ce59a5a72
a652adff31f2f7fd7a9e136904802d76c3827962
7464 F20101211_AAAEWF yeo_h_Page_056thm.jpg
314b4a123a2728db7b8718aa75ff9ebf
e65b0ab5ae8f339d11f2bdf10199bb6d37a573ea
1196 F20101211_AAAFAX yeo_h_Page_104.txt
50fb78becabca71f51bfcd9bb504b6bc
872b445f1e6d8a3f11c32a5c7a8a8c7095e0cb41
35292 F20101211_AAAEVR yeo_h_Page_126.jpg
ba1e3e98b41aa23ead6251bf29d7e62e
c6cd6adf7d61516da47ea4d04b56da81c9a506d1
F20101211_AAAFCA yeo_h_Page_052.tif
5f81f15dc2334091d08bca28cadc0189
c352a8b7f82d616822112c211e9cb20b931b42e8
1307 F20101211_AAAFBL yeo_h_Page_046.txt
70bd00ac078b442d553ce32f3bdd6dfd
0959f47ee582a5491152293e9db861e64b198201
21825 F20101211_AAAFZI yeo_h_Page_136.QC.jpg
54d2559d8250952ea40d2465c45f18a8
7e1aa72c097c50cf68318fad0de27505408d2b51
29220 F20101211_AAAFYU yeo_h_Page_120.QC.jpg
3b350cfdbeade8b573a8bed882688850
b4d828ad17c4a3136c7b555236a225f6cfd696f4
F20101211_AAAEWG yeo_h_Page_077.pro
889cc328aec3dddb2c661f18e6363e1c
35e15d729ccdab3c37bac14c752e200e554b056f
5783 F20101211_AAAFAY yeo_h_Page_078thm.jpg
aa74beee6b61c3f404b529f3f4983c62
e8ee7fbd9f1e730ee7bd6b06ef9d8775b985889c
69438 F20101211_AAAEVS yeo_h_Page_040.jpg
d7414eb5afd8aeee8fa76c9c8a0e7ed8
10ee3fa6b546caf746a7f44eb3b7d78c182f1c98
6853 F20101211_AAAFCB yeo_h_Page_057thm.jpg
0119e838d86046b148c4e687954c124a
745dfa037c092397e50e92edf7e0de6727581d28
21337 F20101211_AAAFBM yeo_h_Page_114.QC.jpg
dcb86a3d1befdd056851066cb3742f6d
d55fe86733735f26085f35a0c97a9c9b47a280a0
156614 F20101211_AAAFZJ UFE0021264_00001.mets
541d5fc2239e5d0d145620f52f9ad6fc
4c91492d834079347630603fa9d2037e4b3c725f
27564 F20101211_AAAFYV yeo_h_Page_121.QC.jpg
388e8ba34049f32c94978179cf104619
a05104ea32b878c3800fa3536c5fb10c083a9e9e
5837 F20101211_AAAEWH yeo_h_Page_099thm.jpg
2a76ed58c13085c7c50260d940599864
9eb0680c547530b5f281be000915dd984dfeae68
314922 F20101211_AAAFAZ yeo_h_Page_007.jp2
c1292d0a5a00a4221f4db5eb0673e93c
650f8535b120892bf6bbbe7211e59a533c77abe8
7679 F20101211_AAAEVT yeo_h_Page_045thm.jpg
d8294fb7ea42ecbf2d98dcbc62796508
99447cf4dc987c712227fb3bbbbb7f6369e46c51
89808 F20101211_AAAFBN yeo_h_Page_089.jpg
1c3dcbca0a7d9f7c7954a55502908a89
35289a981fdc9cb82373b14c7f3dd3a4c9b42584
8415 F20101211_AAAFYW yeo_h_Page_122thm.jpg
22dfb9f08cbae57fdc46df4ee542b585
8864bfd87641dd8e3a472c10bcd17cab13dc8148
151590 F20101211_AAAEWI yeo_h_Page_011.jpg
cae00873fd5cc8f35be494f41214ceac
173210480be27604acfc9a9e1efdfe510b4393a5
1824 F20101211_AAAEVU yeo_h_Page_061.txt
4bed153afb27aa38431551fbee0c21dd
fbbc0854a82fe28b1de347fe7dda709f5e9b0741
31455 F20101211_AAAFCC yeo_h_Page_018.QC.jpg
1f5fa482beeb02ec023c11d90d6bde64
93ec1aa5cf0894a9e1ba814c07169745e1dbd6fb
2991 F20101211_AAAFBO yeo_h_Page_010.txt
d99bafa20c57ad53b98ff58ebaa83558
e97f72f8b46a77561516e5d90a4e822e22851942
33830 F20101211_AAAFYX yeo_h_Page_122.QC.jpg
794c3ae0260540cece19c134cca032b7
abd0b9c361b3e4ec5dccd987185f7348ffa51a96
1222 F20101211_AAAEWJ yeo_h_Page_101.txt
20d6e363439ada93e82bb7fe0ebcca8d
022421662aac5edf800a8ffdfd06a0896d8bd269
6590 F20101211_AAAEVV yeo_h_Page_103thm.jpg
0ef084db3933e363886075d00fd4c21d
11cbb482661f0440abc718cc07053f55764c8451
F20101211_AAAFCD yeo_h_Page_037.tif
43207852f38e55b9a6b403fcc4dd2944
fdf6b430b4bf4a9bf035f5ab10165b695cb3bdb7
116071 F20101211_AAAFBP yeo_h_Page_051.jp2
953c85e3411dfe57ce255efa9cb5f0f4
dba11008ee7d7f57e52b1456c853abb394295ee3
981064 F20101211_AAAEWK yeo_h_Page_019.jp2
f8890d8a82d0bc3c4bb8d181f03ab8cf
a5f66f8ed9286a7476ddb57b07a4b85a1073c7ab
24486 F20101211_AAAFCE yeo_h_Page_101.QC.jpg
5c722698945b95e8dbc6835302dda82b
5e610c68a00ea52e6192a5e295831bc6ca80721a
33134 F20101211_AAAFBQ yeo_h_Page_055.QC.jpg
5e8e79d939c9316ff7ee89f7d971e5b7
776b13ef1b6d5a0080fc863e7f664eda8a335643
27610 F20101211_AAAFYY yeo_h_Page_123.QC.jpg
feb29076dbf33bc4956e5381b3538e07
29056eae819f334838043575d8300395897804c1
52885 F20101211_AAAEWL yeo_h_Page_022.pro
bc1690f7243b8cbd66d0a6f1920ba4e9
389d4e6748fef67f2f6a5ff0146577538858b29a
1515 F20101211_AAAEVW yeo_h_Page_059.txt
0fac2c404b5f9c2bc2ec0464218449a6
2818f4b491e0b2b9cf8a0be713a3d5a2f11c87cc
1051957 F20101211_AAAFCF yeo_h_Page_088.jp2
3a98de2a515600840761f4309a9778a8
87724fb2d730d7035e52508bf3673aeaaeb4657c
699377 F20101211_AAAFBR yeo_h_Page_068.jp2
c8b25b1313d0e4ff2cb67ffde7ed5aba
f87b938071e97dbf7fc94f2a83823e13076c656f
8167 F20101211_AAAFYZ yeo_h_Page_125thm.jpg
df3d82c65c414895fca521099b311789
23acf20e5d17a1a5d93c6130314442def78ad580
F20101211_AAAEWM yeo_h_Page_025.tif
9ffa4e6232a58691a760cfdf973e672d
e1f881dd6130fae855dcbb1831e4bf621624900e
32887 F20101211_AAAEVX yeo_h_Page_024.QC.jpg
d4a6bca1bb9939d6defd25a40cdb53fe
6824e02cf24ccfc8e9bbde2d541bfad93c0ad929
37023 F20101211_AAAFCG yeo_h_Page_062.pro
c8502f30e2851536283c7ce8fbf2c8f7
0bdfe5241b1a5393bf340826a9bde82c288520e8
28062 F20101211_AAAEXA yeo_h_Page_120.pro
602a59c41424f035b332e04a9476dd7d
fd9b75127a8d600da53a8bc4e471f35a66cd4f79
7505 F20101211_AAAFBS yeo_h_Page_084thm.jpg
649bef608dad866fd165786994f61396
3333e82228df4e94b5c8af0ceebad7ed4680b73c
30983 F20101211_AAAEWN yeo_h_Page_118.QC.jpg
c339540eb2181eeebf8e91315f00ec3d
6b98547f7b76ad53dd780c523c2d6d89dafc46d8
32905 F20101211_AAAEVY yeo_h_Page_113.pro
c663f584777444b7509b16c837357091
af8ad76456af456bba577c2609d58df4f5c9f9f0
844 F20101211_AAAFCH yeo_h_Page_049.txt
adbfbe7ce56b75694fd356a850ee3c79
6bf4e9c1746b96cf932500b8796fbaab35a46ac4
46484 F20101211_AAAEXB yeo_h_Page_125.pro
67a93ef310f5529b374c468743b88a64
0352a3502ab33467b18a09519701ae4b5ef5af47
26725 F20101211_AAAFBT yeo_h_Page_110.QC.jpg
424b99d710bf052f5a51eefa4362bb2a
211b895702d80d1edb8a60d5021a0508b8628d4a
8968 F20101211_AAAEWO yeo_h_Page_134thm.jpg
aa86a382e608697e9a40b257d2688a43
9d5d3e2b66016422ac2e5d64217825cccfa9c6e7
117688 F20101211_AAAEVZ yeo_h_Page_025.jp2
5081f4e36d4fea8717ac3b6259bdee45
236eeead46dea8ad87f424e08d83e76d3f119f55
709251 F20101211_AAAFCI yeo_h_Page_103.jp2
78b339caefa5994f2c1ec3ffdfc02d16
7c8aa7e28117056dd996a96e14590c6ea1209928
22298 F20101211_AAAEXC yeo_h_Page_065.QC.jpg
d597d03755650fb9bee2e58975e3e0aa
93083dd3d7fbf04b77aced2584ab751571a7a74e
1051947 F20101211_AAAFBU yeo_h_Page_071.jp2
3018ed4147d18c2b68fd3153670acdd4
b30b986d23d18023c877aeb02def968d9622a4fc
8349 F20101211_AAAEWP yeo_h_Page_004thm.jpg
2d98a33fc3c54693cc0605f308faca96
38a776effcb479679491ef0872ca271272c2501f
F20101211_AAAFCJ yeo_h_Page_030.tif
591dd4c2e9cb155f31906353ebbf275d
248b061dc989396bb894f65aed9b2c0ac5409992
41637 F20101211_AAAEXD yeo_h_Page_033.pro
361abcde0a37073421eb4fd53ac8dac8
a42abbe154cd535cad679ccca3b453db7516230c
54849 F20101211_AAAFBV yeo_h_Page_133.pro
9cb919bc671817e0955d60b8c03e19f1
634b7722bf981cbea8f4d3908e600e97851e72d1
7388 F20101211_AAAEWQ yeo_h_Page_047thm.jpg
1c84b2d1313bc7e668f8d0aebf930812
4617c2f8574014364b91c6d106c8619d17d004cb
94173 F20101211_AAAFCK yeo_h_Page_096.jpg
f9a72bca87eb55a98b87be9d4926c2c7
5109f6881684817744d4d1ae62c10b53f276e0e0
19601 F20101211_AAAEXE yeo_h_Page_100.QC.jpg
5e52626e18b8b41822fe52739dad2240
405afadb07356ed16d1bfcb875eb381836ac214d
3816 F20101211_AAAFBW yeo_h_Page_137thm.jpg
e402bcd4d8a9e5342f90a02379e549a0
085fb71bae7cb4a057b8896dcfe390db50d5b9c8
F20101211_AAAEWR yeo_h_Page_106.jp2
2762a2bd798b64f2ce1d7a0a024f8ae0
dc3f012c3602edea84d77114b38bfa573055a96a
F20101211_AAAFDA yeo_h_Page_105.tif
710792e0903fc89864f1436c416146e8
262f9b52ec9d156667b70087173af69133a9f3fd
F20101211_AAAFCL yeo_h_Page_110.tif
04bf2319379738ffa1a1428c583ba3da
898aa8cdf299d19b86e74491692cd3c6cce7773d
3996 F20101211_AAAEXF yeo_h_Page_003.jpg
7affac4b1e0db5ed32318beeaacd0004
131e40222ea7e97d0eeddb8a36415eb6c23d5c10
108166 F20101211_AAAFBX yeo_h_Page_042.jpg
58e72db0c36ffb1049e7cb2259512571
27c2f1576095125e02a4f4ca6cb61e4f8b74ae66
6584 F20101211_AAAEWS yeo_h_Page_101thm.jpg
0ce3892c134ba8d1c0557f94461c2c24
e9d1d3be79926a8c3fa496f9a1017b0544717349
6526 F20101211_AAAFDB yeo_h_Page_007.QC.jpg
aafdb6ecc4d7e4879df93064a714e850
d04eba5fb2e0eb81100c634a51bc0f9116ff809d
68819 F20101211_AAAFCM yeo_h_Page_052.jp2
c8ec1790d74ad547550c3e0a4d6f3360
2bcb58f13198a1415e4fa6c85c7c638c70fbc0a7
34997 F20101211_AAAEXG yeo_h_Page_124.QC.jpg
f09fba3c639eb1a685ab1ac36453422a
f367b4879cc8022ad57bbc18cdd9882b7f8aa2e2
F20101211_AAAFBY yeo_h_Page_077.jp2
d2d26655735639ea40ffcc30c635acef
5f519c731f0d72a147e3ae547eeba0a3aa7b8002
F20101211_AAAEWT yeo_h_Page_089.tif
65fa21ea51d5bfbf4c29e46032d8f53e
1de6e6f83ef2b845ffa8a0a491c36e587b03eefb
28351 F20101211_AAAFDC yeo_h_Page_062.QC.jpg
ffecf7a8256d45efa1ad236abfb879c0
cf9ec19ce3e65447a0fe9b04a36514fec6bfc4c0
2023 F20101211_AAAFCN yeo_h_Page_017.txt
8a573664fd4fc5de55a127a66dc1acac
206bc809663b486ad89211f45ffc2cad70c94e4f
49916 F20101211_AAAEXH yeo_h_Page_053.pro
de537200b1915d6c43a9f830e348c075
96e61f0a23f3de8b75340aa39a400bd13b86ab44
1051971 F20101211_AAAFBZ yeo_h_Page_119.jp2
62221a801b17bbbe16d928136109870b
04e16f2c947346ca7008467b4a38dda1f1e8fd94
24344 F20101211_AAAEWU yeo_h_Page_095.QC.jpg
8b06cb5546b341c8443a2d156db5bc9f
f7ff8d55aaf6e2a04127973f84f148f0797716d0
4077768 F20101211_AAAFCO yeo_h.pdf
80555a37cefc2d2acaa37f817db7a4d2
374188f8423f1d3ae6ef5500de14f20eb27523f1
1561 F20101211_AAAEXI yeo_h_Page_043.txt
a003773d351fcdee95612f1f4229428d
af4f00ca7fa2ad5f6698a9621db06c10b37d5d0e
96057 F20101211_AAAEWV yeo_h_Page_130.jpg
fabc89862a0f795830752db4434129b8
3a9ad70e11dea578bbd82def9315ec8011bc405f
83062 F20101211_AAAFDD yeo_h_Page_076.jpg
090a2792fb30cf26e5d50b3a0bca7054
d2cc3553d4476659533f82ef1c65c8ff10e006df
81528 F20101211_AAAFCP yeo_h_Page_050.jpg
b709caa6a4c870312ebd4c5ca1be5502
c1423b9f83268573cd44dd9b7474c92d252274da
45395 F20101211_AAAEXJ yeo_h_Page_055.pro
405775554c31977d9543358e51d9a05b
5a8a52f3541424c44b7049d82b6f85719b11a0ab
1294 F20101211_AAAEWW yeo_h_Page_117.txt
5533f1dd18a382b6f22b7e8bbe32db9c
ea9b2557ae067c2d3a6a106257d7b353a4e137db
98724 F20101211_AAAFDE yeo_h_Page_013.jp2
617e121a39180e39432e004e5effd9c4
3d974d81b922ce0a522f22633f0f80109c309073
F20101211_AAAFCQ yeo_h_Page_072.tif
ebb4c488ea20b9e4dcbce175e361c310
d4b3cdb739c27aacc8f4f1f21ee12b47a16b94f0
77112 F20101211_AAAEXK yeo_h_Page_117.jpg
9db247c6aa05c4eda7ab10f9f066a15f
8a9d424f4105eee8663afd3032920017a3e0f352
61951 F20101211_AAAFDF yeo_h_Page_114.jpg
bcc1c868267aed38bafb7338e4eb96dc
c9defbe0b9cfc64c7280e7047a2c9e80af0cc8f5
86293 F20101211_AAAFCR yeo_h_Page_090.jpg
deff242a5075eac3e8b46e6451e4d044
acf6832dcdb899c6806a467ec9d840c339489787
19002 F20101211_AAAEXL yeo_h_Page_123.pro
7b03108336b148128f2e77800d7aeb7d
98934cfa1ca4806afc2ab3f6ff805c7573336641
1132 F20101211_AAAEWX yeo_h_Page_115.txt
5eb148906c673c6427df4f93a9ea40b0
f94b1d9a26e1fb726ace756d3a5b9643b6551c6c
7352 F20101211_AAAFDG yeo_h_Page_066thm.jpg
675e485f798057b721e87c61f860dc1b
1bd3cf903090d6fcedb5df0d21b13f33386ea9d5
1370 F20101211_AAAEYA yeo_h_Page_084.txt
b625ba7492fc583b9ea1ba1a1a8b8a8d
124d1f389084e3c9458284d751177af957bde8f2
79862 F20101211_AAAFCS yeo_h_Page_016.jpg
b7b12ed7097a97dece5787ec726cee31
9ddab7b9728bb6fa362feb44cf16dd1b38daed68
F20101211_AAAEXM yeo_h_Page_027.tif
ff1863ec8fdbbc5732024f4a68b61e38
895e973753eddcc1b430d083bfc22f5bd117b791
26363 F20101211_AAAEWY yeo_h_Page_111.QC.jpg
90625a3f89cb3a5f91136d9d4c5f0a51
80306b15c0c2676e79b3d7b86c4c3ce13c387235
31213 F20101211_AAAFDH yeo_h_Page_032.QC.jpg
b026dddaa17fde974a44f3166d9b49a9
a6fffa013adc4c5922dc30bd67503cb2ccf0aea8
40854 F20101211_AAAEYB yeo_h_Page_061.pro
e47cd065eff68a782615463570506705
b1d42f2a5a353db48553f364f27b23a9418cc86e
1108 F20101211_AAAFCT yeo_h_Page_100.txt
a200fcfd3623b793778724103f3d90b7
5c711309957663fe7b4cf8888855c0dfbfb3942c
32240 F20101211_AAAEXN yeo_h_Page_109.pro
692805329b1b06773d479f398efb9d21
4c460543e22538b0386692740c6b01ae47fb297f
853 F20101211_AAAEWZ yeo_h_Page_137.txt
cf44d7a789d5dba86d0f9eb66c37010c
cf9bfdac65a8d3cf273142090fac673baebaa8b7
910 F20101211_AAAFDI yeo_h_Page_121.txt
ac1a072657c62a7a8db9f715a70d22a5
bac15126eb06e603f18b3d2f2d46f87c9903d62a
8481 F20101211_AAAEYC yeo_h_Page_080thm.jpg
020ab2d27667561bbb7738cccc0fe2de
0537bc6124bef6afd6bc47d1e999e64c4bad9c46
614969 F20101211_AAAFCU yeo_h_Page_100.jp2
9e4b6f7b9ab423c55dceb2c9c3b4cba9
7383ce167844d1a2c380afba5fe42df984cafbe4
35020 F20101211_AAAEXO yeo_h_Page_072.QC.jpg
114a9d8ea900ddeec710b2773ce5f38f
129ea78e434ae736be84d21e959d35566529caf0
F20101211_AAAFDJ yeo_h_Page_115.tif
0ddc821cd78f872e660d8deb478f0582
f1b53d1462cc745d72cf37788b93f49f47a54e8e
86546 F20101211_AAAEYD yeo_h_Page_064.jp2
3ad48d082f2eee402d45bbcff1e68864
e0dd9248851d184ad7903b66fdcec766acabb810
F20101211_AAAFCV yeo_h_Page_016.tif
99388f21e59e2e8579b469615ce9a0b1
fa4c80d8f831e0a07eb81ee23c4c441d4f3977d5
F20101211_AAAEXP yeo_h_Page_021.tif
da04350fa1bf465984aaf04dbaf146ca
7c3f1feb3d9596f6b989297caedfa9afb8dfdf16
25399 F20101211_AAAFDK yeo_h_Page_057.QC.jpg
ce30293b3b0f19c7a9eba9bd1dee9c7e
5eeb920500ec20368e39232db44baf8d174ea58d
90806 F20101211_AAAEYE yeo_h_Page_071.jpg
0bfd599bc3be0f22700b1100fb59798c
a8edb7d8d8d0b303a6090180865578d8fc64ed20
7855 F20101211_AAAFCW yeo_h_Page_109thm.jpg
d83c3f07ee5e4a0020545b4c9899d2c3
acdd9b8f51a960e3b5da16db9489442b2dfc2e67
96202 F20101211_AAAEXQ yeo_h_Page_132.jpg
85daa3bdbedb2e2c6e5e6adfa03eacdf
26804d51ead8e293133aa2f6ccc8503d5a4c1515
95468 F20101211_AAAFDL yeo_h_Page_081.jpg
76b7d39f96e9a56311cf4ee5a3f88d2e
8ed59870e02eba41e8b7976aeb0bf9df8dc3d384
F20101211_AAAEYF yeo_h_Page_109.tif
2e78953231b0890a9b3505d30a6b7640
b3eb610f9ae705d35a2ea91e7eeb5b4bfa34177b
42073 F20101211_AAAFCX yeo_h_Page_129.pro
32efeaf18412b1366b5b999b0de447d4
65ed9e5032628663372658bc538eeab712a040fd
F20101211_AAAEXR yeo_h_Page_062.tif
4e05dcb3364f4217760a3a144fdac6b3
7fc8354b58d1de14797c8562072d3c5d7d222b2c
2044 F20101211_AAAFEA yeo_h_Page_042.txt
b2062a36df87785521654cb308b65845
a4bcf02163d21c2a2cd6f7904a2f40f9a1a5dfcd
34057 F20101211_AAAFDM yeo_h_Page_133.QC.jpg
24a51746fd1501d074bffc2e8e5a2175
2eba2e549d9d947ad045545096d598203b943943
107710 F20101211_AAAEYG yeo_h_Page_053.jp2
13e64c6bd7c69922d8984d1cca2805d2
c932918dd49796d63cbfd14f95506e6c19b9b9a6
7230 F20101211_AAAFCY yeo_h_Page_068thm.jpg
5eae816c9da6c6485531012f56fbd4ba
3863b1c90e991e81306e8d4c43840dbc7f32a928
32234 F20101211_AAAEXS yeo_h_Page_119.QC.jpg
c948f1eddbbe44d3be88109d8ac62495
cd9bed587ee49edef57e6cdafc8fbc2c4ce3c800
90538 F20101211_AAAFEB yeo_h_Page_018.jpg
8804cf6def2f8e6bfacda5733457dfbd
7b8d4a81d9104dfaa0ff6906088581b6c2e75f3a
101266 F20101211_AAAFDN yeo_h_Page_055.jpg
86b0561b10b3259cfd259f785a3f36e4
24063f0550493deff712df448116d2923256f9b6
49577 F20101211_AAAEYH yeo_h_Page_017.pro
daf7fe74e24945b9080cd2db1c0a9982
034bbf7021bd059f824725e267807389b9f88e9b
106194 F20101211_AAAFCZ yeo_h_Page_072.jpg
304fe3e33e2bab180c36cc06007e8e48
a5bbd9a2cf10944feb0f6995f8d8ad5f01c8a5f6
52020 F20101211_AAAEXT yeo_h_Page_042.pro
6cef743ca8889e82c946034270ed50ff
236082cd044ceb791d86ece286dde7babec0834f
8022 F20101211_AAAFEC yeo_h_Page_061thm.jpg
2722b27c124af792cd1f1a62e4d01a63
7aeaf875688bcd0e173d44789a20916017b5d9db
28451 F20101211_AAAFDO yeo_h_Page_079.QC.jpg
e6cdc0f035e03a1f3bdb36c72061c8b1
ffb460be721da998d00f04e482dfe1749682dc7d
F20101211_AAAEYI yeo_h_Page_061.tif
4d7e206b2e60bbd90ce1e930db0b79d7
24d3715d8f06c9b663b4fa4a528244b4a27773e6
34875 F20101211_AAAEXU yeo_h_Page_058.jpg
6d6087792906e1fc254598c668f053cb
b9c674f7027170eba86a640b5bbad96d459e6567
7787 F20101211_AAAFED yeo_h_Page_028thm.jpg
f4cbdf271a6384aaa0f52d71d52c580f
f6762f9bbe6372c52ce6b09d23bdb4e88d290639
F20101211_AAAFDP yeo_h_Page_120.jp2
b06e11262438edb788b7731b71fcfb83
cd3de64d07506b7a8af999dd3f76324dc0c27c89
24368 F20101211_AAAEYJ yeo_h_Page_073.QC.jpg
a594c2da960f1571d96778e3d7f1bbb5
ef013af2e9a012571ccaf802f4cadd1a4a9333f4
2039 F20101211_AAAEXV yeo_h_Page_072.txt
872d3201b890960af71b5c1aa2cf1013
1c4c4d05ed64a740607314ce6dd12cb8250d598f
3299 F20101211_AAAFDQ yeo_h_Page_006.txt
d98d3aeb43b10603430be3edbec4cc23
2045e31ce98fde4d190e95928521d2b7ce22eebe
30750 F20101211_AAAEYK yeo_h_Page_045.QC.jpg
eb6a2f50c20968e82816391b61d81a77
2cb825a3df20c751445c5f5042e587098148a23e
F20101211_AAAEXW yeo_h_Page_106.tif
eb074d025b070f24210fc1b19e2a1462
10c1febad9f41430c776d9b2f41e6427d8d178f2
94488 F20101211_AAAFEE yeo_h_Page_129.jp2
b8f264ceb7e4ddc9efb5daccab43234d
cf6c1eaffc2c8190977b7a04dac874c3547cd863
7804 F20101211_AAAFDR yeo_h_Page_019thm.jpg
169f8c3416c5405e47a03cc3dc978f80
b8d401b455fbfbe1434e073dc1411e8cf7284d86
766 F20101211_AAAEYL yeo_h_Page_058.txt
cd681c034d22fb0b732f851f00fea239
97a222da3d22df5643439d99cf6c4ed5a2d5748a
11773 F20101211_AAAEXX yeo_h_Page_058.pro
afcdfc6c4abf0a44beb70128b8850b2f
1ee82e0ca6fc80d01daa2bd4aa77d61bf86ed469
28248 F20101211_AAAFEF yeo_h_Page_109.QC.jpg
c3f623c28d4c6e9075584e95a89bfcd2
38b322aa358cb1c173f00358561be17585840286
72686 F20101211_AAAEZA yeo_h_Page_101.jpg
d1fa28d7fa4759caf7b99974f0749657
542d18b0dcdedadd4bee3503943469073ba4ac07
23754 F20101211_AAAFDS yeo_h_Page_100.pro
bb0dfd1ac53fd1f70a152d19a2ec2739
1f3289d994094889c51e1bc71e9f268ef3f59867
1327 F20101211_AAAEYM yeo_h_Page_018.txt
6865322e8e333932eb269010007850d2
55818713893c4640ae5d09d407c98926e0dce30c
45400 F20101211_AAAFEG yeo_h_Page_137.jpg
be72b0cbf2e473dc3801ad2654e30979
075fd06e3fbbedd20d53164e2457ce4108623b51
25685 F20101211_AAAEZB yeo_h_Page_018.pro
ede8fb97740bceb8eaa35d934ab0da06
46274c98797a71c35ff93b7f023f2a160cbe6656
F20101211_AAAFDT yeo_h_Page_098.tif
59f8a95ac4fb671c8b40f16fa923bd27
9a8c435a29b5ed4a01a93bf236264b5870135307
34818 F20101211_AAAEYN yeo_h_Page_031.pro
72541ef5040a68b51cbb2da6e19c8ad3
c19e6a7955f3304f26396f2402b8afd09f290745
F20101211_AAAEXY yeo_h_Page_053.tif
7d9de4b57d50bda2afde24a407f6be92
bfdd5af11ca129a6bc711981b71c7e54662c8f98
126732 F20101211_AAAFEH yeo_h_Page_134.jpg
6e74092a6d29770d6e878324da6788ed
295657ee4b06e7fd5ef6cf19d2ca599e8778b4a4
12315 F20101211_AAAEZC yeo_h_Page_126.QC.jpg
b34748fcf632f975302f7f63f00ebcbd
568a3cdaf6e8c781459d5e5d03891765818a6874
978767 F20101211_AAAFDU yeo_h_Page_060.jp2
5fc021ed59bd545d1dcbc18e5efd58c8
ef32eba1fbf8d76f0529dfdedc5b8f144315877f
F20101211_AAAEYO yeo_h_Page_019.tif
a538619cd68f8388d250d023e32da31e
00e4890cdd8198a9c8377bd1f0f9162ca1926102
7217 F20101211_AAAEXZ yeo_h_Page_108thm.jpg
35d1b3b4f464e70af56e2c576598f46b
d3d7de7bdce8e61119bce91496caf11a5c7d7a0b
4074 F20101211_AAAFEI yeo_h_Page_014thm.jpg
d9a3e7abebf97785ecb35c6feebfdb10
2803120b704e387481e6d1383aaba8eada0f1d24
1980 F20101211_AAAFDV yeo_h_Page_102.txt
66039639ca8c42735cbd3154b1ced923
ce2bd49b37a8421d0aa189b2d9d3c9efd1da2efe
77166 F20101211_AAAEYP yeo_h_Page_108.jpg
731a100408a897192aedd56f2f9079fd
cbf3568265bc317e4638019bec058411b0c1fcc8
130585 F20101211_AAAFEJ yeo_h_Page_008.jpg
b55515c4973c82fe942a96d03b6552f9
71c83065fe7525286083f571defc352069d93d1a
1137 F20101211_AAAEZD yeo_h_Page_057.txt
9039d4bd55bb17711e1b9b6fd556c9b8
56cbd790c3fa87339280493af6c4600b6a714d6f
1908 F20101211_AAAFDW yeo_h_Page_129.txt
81b00fce2b69ff0fbaf13c1cd646343b
ca9706f84f705b70bc306e6bfe501e7568e48652
824012 F20101211_AAAEYQ yeo_h_Page_108.jp2
a5a7314a2e05d8cd2f6e540fbb487419
1ccc49d22d8eb066514cfe6a45eb8bf44915a388
F20101211_AAAFEK yeo_h_Page_083.tif
45f8f387b33fc28546438d465487d3e4
fc7b2334369925f59dde80bda36f72458c8b5b81
1967 F20101211_AAAEZE yeo_h_Page_015.txt
9887f2778d63b635906133ee627fe763
802712edd937edb6258338a324b9b1251e5076e9
1673 F20101211_AAAFDX yeo_h_Page_077.txt
0ac70f54655cf5cd16f73746f6ff6fcc
defe907240ba515051de90943b64703073b798e1
141 F20101211_AAAEYR yeo_h_Page_087.txt
87af25da95bfd68d081caa72a2de5743
f67ce09b0d3bb00d613942ec8569be2c371c38ed
105578 F20101211_AAAFFA yeo_h_Page_128.jpg
be8378beff220ae6a094487762836d31
01361c7b27d3f82564c646a5660773391d08e5ce
22904 F20101211_AAAFEL yeo_h_Page_075.pro
462d3a78e55f73cbbff775049f077932
e4524b46951e7c9649d56fa4a852f5173758dbeb
28473 F20101211_AAAEZF yeo_h_Page_001.jp2
c4d8579c2a62dbc25acc07a4ed563d36
2bc73db0488498dc27a5d749874e491327385971
88156 F20101211_AAAFDY yeo_h_Page_084.jpg
34545f7efdaff1216a22ae993d9666a2
37c11c2d2b5aee12860828534ca751d41a5e70e7
1051850 F20101211_AAAEYS yeo_h_Page_069.jp2
720cf8a3ea37ca7f1a3ae1f7b0cd7d93
bef557464312ac6c9ff584007dab3d63cbe67a61
F20101211_AAAFFB yeo_h_Page_114.tif
0b5e77e03f0dcb04f755388b9891699f
b68e94776f509fac088a21b6acd7dedb3c1aeebd
F20101211_AAAFEM yeo_h_Page_120.txt
fd311124a3bff7d0888a679775fbb7ec
4115385a9119d758b672e1605994d0ce1cc0e340
29080 F20101211_AAAEZG yeo_h_Page_073.pro
144ead65978561b87f676f5432705d0e
59a8acf5e04f02062935dac0f05687067da49f7b







DESIGN OF MULTI-GIGABIT SERIAL LINK TRANSCEIVER USING BANDWIDTH-
EFFICIENT HALF-SYMBOL-RATE-CARRIER OFFSET QUADRATURE PHASE SHIFT
KEYING MODULATION




















By

HYEOPGOO YEO


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2007
































O 2007 Hyeopgoo Yeo


































To my parents and family









ACKNOWLEDGMENTS

I express my sincere gratitude to my supervisory committee chair, Dr. Jenshan Lin, for his

support throughout the course of this work. I also thank Professors William R. Eisenstadt,

Rizwan Bashirullah, and Li-Chien Shen for their advice on this work and their willing service

and guidance on my research. Without their invaluable support and encouragement, my

exploration in the research could not have come to fruition. I appreciate their interest in my work

and valuable suggestions and comments from the research proposal to its realization.

I thank my fellow colleagues (Tien-Yu Chang, Mingqi Chen, Lance Covert, Sangwon Ko,

Changzhi Li, Zehn Ning Low, Yachi Liu, Zivin Park) in the Radio Frequency Silicon on Chip

(RFSOC) Group for all the help they offered. My thanks also go to my other colleagues in

Electrical and Computer Engineering for their helpful discussion, advice, and friendship (Jongsik

Ahn, Kooho Jung, Sudeep, Jeashin Kim, Jeaseok Kim, Kwangchun Jung, Eunyoung Seok,

Dongha Sim, Kyujin Oh, Minsun Hwang, Seon-Ho Hwang). Their support and advice have

contributed immensely to my work. Also, I thank all of the friends who made my years at the

University of Florida such an enj oyable chapter of my life (Jangsup Yoon, SeungHwan Kim,

Sanghoon Choi, Jiwoon Yang, Choongeol Cho, Okjune Jeon). I acknowledge TSMC and UMC

for the technical and state-of-art fabrication support. I thank Inphi Corp. and Agilent

Technologies for their help on test equipment.

I dedicate this work and my deepest love to my parents who have given me utmost trust

and support throughout the years. I express my profound thanks to my wife, Seungyun Lee, for

her endless and unconditional love and support, and my dearest children, One and Myoung.

Without them, it would not have been possible to pursue my graduate studies.











TABLE OF CONTENTS


page

ACKNOWLEDGMENT S .............. ...............4.....


LI ST OF T ABLE S ............ ...... .__ ...............7....

LI ST OF FIGURE S .............. ...............8.....


AB S TRAC T ........._. ............ ..............._ 13...

CHAPTER


1 INTRODUCTION ................. ...............15.......... ......

1.1 Motivations............_.__ ........._. .. ... .........___........1
1.2 Compensation Techniques of High Frequency Signal ........._..._......_._ ........._.....19
1.2. 1 Pre-Emphasis Signal ........._.._ ..... .___ ...............19...
1.2.2 Broadb and Circuit Techni que ........._.._ ..... .___ ...............20.
1.3 Modulation Techniques ...................... ...............22
1.3.1 Conventional Modulation Techniques ...................... ............... ........2
1.3.2 Modulation Technique Using Half-Symbol-Rate-Carrier (HSRC).............._...__.....24
1.3.2. 1 Why Not Carrier Modulation? ..........._.._........_ ...............25.

2 HSRC PHASE SHIFT KEYING (PSK) MODULATIONS .............. .....................2


2.1 Binary Modulation............... ...............2
2.2 Quadrature M odulations ...................... .............. .........2
2.2.1 HSRC Quadrature PSK (QPSK) Modulation............... ...............2
2.2.2 HSRC Offset QPSK (OQPSK) Modulation ................. .............................28
2.2.3 HSRC Minimum Shift Keying (MSK) Modulation .............. ....................3
2.3 Signal Spectrum ................. ...............3.. 1....__. ..
2.4 Bit Error Rate (BER) Performance ............... ................. ...............33 ...
2.5 DC-Free Signaling Based on HSRC-OQPSK Modulation............... ...............4
2.5 Measurement of the HSRC-OQPSK Signal ................ ............... ........ ...._...45
2.6 Summary ............ ..... ._ ............... 1....

3 HSRC-OQPSK TRANSMITTER .............. ...............53....

3.1 Transceiver Architecture .............. .. .................... .......5
3.1.1 A Conventional Serial Link Transceiver Architecture.............__ ..........___.....53
3.1.2 A Conceptual HSRC-OQPSK Transceiver Architecture ................... ...............53
3.2 HSRC-OQPSK Transmitter Architecture ................. ....___ .....__ ...........5
3.2 Circuit Implementation................. ... ............5
3.2. 1 Current-mode-logic (CML) Circuit .......___............_. ............... 57. ...
3.2.2 CML Double-Edge Triggered D flip-flop .............. ...............61....
3.2.3 Resistive Load Gilbert Mixer ............ ....._._. ...............62












3.2.4 Quadrature Phase Clock Generator .............. ...............63....
3.2.5 I/Q Channel Signal Combining .............. ...............66....
3.2.6 Output Buffer. .........__.. ..... .__. ...............66...
3.3 Chip Design ................. ...............69...
3.3.1 Rev. 1 Transmitter ............... ...............69....
3.3.2 Rev. 2 Transmitter ........._.___..... .___ ...............71..
3.4 Measurement. ........._.___..... .__. ...............76....
3.4.1 Rev. 1 transmitter .............. ...............76....
3.4.2 Rev. 2 transmitter .............. ...............8 1....


4 HSRC-OQPSK RECEIVER DESIGN .............. ...............91....


4. 1 Receiver Architecture ........._._... ......___ ...............91...
4.2 HSRC-OQPSK Receiver (Rev. 1) .............. ...............91....
4.3 HSRC-OQPSK Receiver (Rev. 2) .............. ....... .. ...............9
4.3.1 Polarity-Type Costas Loop for Carrier Synchronization.............. ................. 9
4.3.2 A New Clock and Data Recovery (CDR) based on the Modified Costas Loop.....96
4.3.2.1 Phase detector characteristics............... ............9
4.3.2.2 Loop analysis............... ...............10
4.3.2.3 Noise characteristics............... ............10
4.3.3 Behavioral Model Simulations .................._._._ ......... ............0
4.3.3.1 Phase error................. ...............106
4.3.3.2 Time domain simulation............... ..............10
4.4 Chip Design (Rev. 2) ................. ...............110.......... ...
4.4. 1 Circuit Implementation ................. ...............111...............
4.4. 1.1 Sample/hold circuit ................. ...............111..............
4.4. 1.2 Quadrature VCO (QVCO) ................. ......... ......... ..........12
4.4. 1.3 Voltage-to-current (V/I) converter ....._.._................. ........_.._.. ....114
4.4.2 Circuit Simulations ................. ...............115..............
4.4.3 Layout ....__. ................. .......__. ..........11
4.5 Measurement (Rev.2) .............. ...............120....
4.6 Summary ................. ...............125......... ......


5 SUMMARY AND SUGGESTIONS FOR FUTURE WORK ................. ............. .......127


5.1 Summary ........._.._.. ..... .._. ...............127...
5.2 Four-fold Ambiguity Issue .............. ...............130....


LIST OF REFERENCES ........._..... ...._... ...............133....


BIOGRAPHICAL SKETCH ........._.._.. ...._... ...............137....










LIST OF TABLES

Table page

2-1 Summary of components used in the measurement ................. ................ ......... .48

4-1 Transceiver (Rev.2) performance summary .............. ...............124....

5-1 Performance comparison of the different modulations ................. ........................129










LIST OF FIGURES


Figure page

1-1 Characteristics of a PCB trace channel with various lengths. ............. .....................16

1-2 Basic information of eye diagram. ................. ...._._ ...............16. ..

1-3 Eye diagram of the 10Gbps signal at the far-end after tracing (a) 0. 1" (b) 10" (c) 20"
PCB channel ................. ...............17.................

1-4 High data-rate transmission with (a) a conventional parallel bus (b) a serial link. ...........18

1-5 Pre-emphasis of NRZ signal and received signal with/without pre-emphasis. ...............19

1-6 Frequency domain representation of the pre-emphasis technique of the transmitted
signal. 20

1-7 Active inductor (a) realized with NMOS source follower (b) small signal equivalent
circuit (c) simplified model............... ...............21.

1-8 Comparison of PAM-2 and PAM-4 signal spectrum ................. ................. ..........23

1-9 Basic digital modulation schemes (a) baseband data (b) ASK (c) FSK (d) PSK. .............24

1-10 Simplified spectrums of carrier modulation signals (a) using carrier signal higher
than data-rate (b) using half-symbol-rate-carrier signal. ............. .....................2

2-1 HSRC-BPSK modulation: baseband data sequences and modulated signal. ....................27

2-2 HSRC-QPSK and OQPSK (a) modulation scheme, (b) QPSK time domain
waveforms, (c) OQPSK time domain waveforms. ............. ...............29.....

2-3 HSRC-MSK (a) modulation scheme (b) time domain waveforms. ................. ...............30

2-4 Normalized power spectral density for HSRC modulations............... ... ...........3

2-5 Modulated time domain signals of HSRC-OQPSK and its symbol energies. .................. .33

2-6 Gaussian distribution of different energy symbols for HSRC-OQPSK modulation. ........36

2-7 Comparison of theoretical and simulated BER performance of HSRC modulations. .......3 7

2-8 The demodulated signal (a) demodulation process of I(or Q) channel (b)
demodulated peak signal (Es,p) Of the HSRC-OQPSK. ............. ........ .............3

2-9 Comparison of the BER performance between the symbol time (matched filter) and
the bit time integration of HSRC-OQPK signal. ................ ...............39........... ..











2-10 Frequency response of the band-limited channel modeled with a one pole low-pass
filter. .............. ...............40....

2-11 Comparison of simulated BER performance of the PAM-2 (NRZ) and HSRC-
OQPSK modulation with band-limited channel. ............. ...............41.....

2-12 DC-free modulation based on HSRC-OQPSK (a) modulation scheme (b) time-
domain waveforms. .........._.... ...............43.__... ......

2-13 Comparison of the spectra between NRZ and the dc-free signals. .............. ................44

2-14 A prototype HSRC-OQP SK transmitter and measurement setup .........._. ............_......45

2-15 A 500MHz branch-line hybrid quadrature power splitter structure for HFSS
simulation. ........... ..... .._ ...............46....

2-16 Simulated and measured characteristics of the 500MHz branch-line hybrid
quadrature power splitter (a) S-parameters (b) phases. ............. ...............46.....

2-17 Measured characteristics of the HSRC-OQPSK modulation (equivalent 2Gbps
random data input) (a) time domain waveform (b) spectrum. ................... ...............4

2-18 Comparison of the theoretical and measured waveforms of HSRC-OQPSK
m odulation. ............. ...............50.....

2-19 Comparison of the measured and theoretical spectrum of the HSRC-OQPSK signal. .....50

3-1 A simplified conventional transceiver for a serial data link. ............. .....................5

3-2 A conceptual HSRC-OQPSK transceiver architecture .................... ............... 5

3-3 A HSRC-OQP SK transmitter architecture ................. ...............55...............

3-4 A structure of the DET F/F and data and clock synchronization by inserting (a) delay
unit (b) a MUX as a delay unit. ..........._ ..... ..__ ...............56.

3-5 A fully differential (a) CML buffer and (b) differential input voltage versus output
voltages. ............. ...............58.....

3-6 Characteristics of a differential pairs versus differential input voltage (a) drain
currents (b) transconductance. ............. ...............60.....

3-7 CML Circuits (a) D-latch (b) analog multiplexer (c) double-edge triggered flip-flop......61

3-8 A resistive load Gilbert mixer. ................. ...............63.._.... ...

3-9 Two different delay control circuit (a) a current-starved inverter (b) a shunt
capacitive inverter ................. ...............64.................










3-10 A fully differential (a) shunt capacitor inverter with cross-coupled PMOS active load
and (b) two-stage ring oscillator. ............. ...............65.....

3-11 Injection-locked LC QVCO. .............. ...............66....

3-12 Combining I and Q channel signal by direct connecting outputs. ............. ...................67

3-13 Three stage output buffer with open drain output stage. ............. .....................6

3-14 Output buffer (a) differential three-stage output buffer (b) doubly terminated
structure ................. ...............68.................

3-15 HSRC-OQPSK transceiver chip using TSMC 0.18Cpm CMOS technology. .....................69

3-16 HSRC-OQPSK modulation signal (a) time domain waveforms (b) signal spectrum..._....70

3-17 Transmitter die photo implemented by UMC 0.18Cpm CMOS technology. ......................71

3-18 Linearity simulation of resistive Gilbert mixer using UMC 0. 18Cpm CMOS
technology (a) conversion gain vs. LO power, (b) conversion gain vs. RF input
frequency, (c) input referred 1dB compression. ............. ...............73.....

3-19 HSRC-OQPSK modulation signal (a) time domain waveforms (b) signal spectrum..._....74

3-20 Simulated dc-free signaling (a) time domain waveforms (b) signal spectrum ..................75

3-20 Test board for the Rev. 1 HSRC-OQPSK transmitter (transceiver) implemented by
TSMC 0.18Cpm CMOS Technology. .............. ...............76....

3-21 Measured spectrums and phase noise of the transmitter' s QVCO implemented by
TSMC 0.18Cpm CMOS technology (center frequency of 2.5GHz with 5MHz span and
47 KHz RBW) (a) free-running mode (b) inj ection-locked mode (c) comparison of
the phase noises between free-running and injection-locked modes ................ ...............77

3 -22 Simplified test setups for (a) 2.5Gbps (5Gbps equivalent) (b) 10Gbps random input
for the transmitter. ........... ..... ._ __ ...............79....

3-23 Eye-diagram of the HSRC-OQPSK transmitted signal implemented by TSMC
0.18Cpm CMOS technology. ............. ...............81.....

3 -24 Test board for the Rev. 2 transmitter implemented by UMC 0.18Cpm CMOS
technol ogy ................. ...............82.................

3-25 Measured spectrums and phase noise of the transmitter' s QVCO implemented by
UJMC 0.18Cpm CMOS technology (center frequency of 2.25GHz with 100MHz span
and 910 KHz RBW) (a) free-running mode (b) inj ection-locked mode (c) comparison
of the phase noises between the free-running and the inj ection-locked modes. ................83

3-26 Characteristics of channels used in the measurement ................. ......... ................85










3-27 Eye-diagram of HSRC-OQPSK transmitted signal implemented by UMC 0.18Cpm
CMOS technology after (a) 2" PCB trace, (b) 5" PCB trace, (c) 10" PCB trace, (d)
20" PCB trace, (e) 19" SATA cable, in response to 4.86Gbps (both I and Q channel
input with 2.43 Gbps pseudo random bit stream (PRB S) sequence of 231-1). ................... .86

3-28 Spectrum of 4.86Gbps dc-free signal ........._..__......_ ... ...............88

3-29 Eye-diagram of the HSRC-OQPSK transmitted signal with 9.72Gbps PRB S
sequence of (a) 2 -1 (ideal eye-opening is depicted with blue line), (b) 231-1. .................89

3-30 Signal spectrum in response to9.72Gbps PRB S sequence of 2 -1.............__ ............_ 53

4-1 HSRC-QOP SK receiver (Rev. 1) architecture incorporated with quarter-rate PD...........92

4-2 Quarter-rate phase detector (a) architecture (b) waveforms (for 40Gbps NRZ). ..............92

4-3 HSRC-OQPSK receiver architecture incorporated with a CDR ................. ................. .94

4-4 Polarity-type Costas loop for QPSK signal carrier recovery. .............. ....................9

4-5 A modified Costas loop for the HSRC-OQPSK signal clock and data recovery. .............97

4-6 Early and late sampling time of I/Q data. ..........__.......__.....__ ...............100

4-7 Averaged phase detector characteristic of the proposed CDR loop. ............. ..............101

4-8 Equivalent linear model of proposed CDR for HSRC-OQPSK. ........._. .................103

4-9 Open loop gain characteristics of the proposed CDR loop............_ ... ......_._........104

4-10 Phase error characteristic with SNR (S-curve) of the proposed CDR loop. ................... .105

4-11 Phase error simulations of the CDR for the HSRC-OQPSK signal with MatLab
Simulink behavioral models. ............. ...............106....

4-12 Behavioral model simulation result of the phase error for the proposed CDR using
M ATLAB ................. ...............107................

4-13 HSRC-OQPSK Transceiver Model with QVCO for Time-Domain Simulation. ............108

4-14 Time-domain response of phase error signal for the VCO frequency control .................1 08

4-15 Time-domain response of phase error signal for the VCO frequency control with 100
I/Q mismatch ................. ...............109................

4-16 Normalized settling time and peak-peak ripple voltage in locking state vs. I/Q
mismatch ................. ...............110................

4-17 A high-speed differential sample/hold (S/H) circuit ................. .......... ................1 11










4-18 A ping-pong structure differential sample/hold circuit ................. ........................112

4-19 LC quadrature VCO (LC-QVCO). ................ ......... ...............113 ....

4-20 Simulated QVCO's tuning range and its gain. ................. .....___............. ....14

4-21 A differential to single-ended V/I converter. ...._.._................. ......._.........11

4-22 A detailed receiver architecture. ....._.._................ ........._.._ ....... 11

4-23 Time-domain simulation setup with a HSRC-OQPSK transmitter and 10cm
transmission line with characteristic impedance of 5002. ................ .........__..........116

4-24 Simulation of the locking behavior of the proposed CDR loop ................. ................. .1 17

4-25 I/Q data of the transmitter and the receiver in the proper phase locked state. .................1 18

4-26 HSRC-OQPSK receiver chip fabricated with UMC 0. 18Cpm CMOS technology. ..........119

4-27 Receiver test board ................. ...............120...............

4-28 Simplified receiver (transceiver) measurement setups (a) for 2.5Gbps input
(equivalent data-rate of 5Gbps), (b) for 10Gbps data-rate ........._.__....... ..._. ..........121

4-29 Phase noise performance of the receiver' s VCO in free-running and locking states. .....122

4-30 Measured jitter of recovered clock in response to 4.86Gbps (both I and Q channel
input with 2.43Gbps PRB S sequence of 231-1). ......____ .... ... .__ .........__.......2

4-30 Recovered I (or Q) channel eye-diagrams in response to 4.86Gbps (both I and Q
channel input with 2.43 Gbps PRB S sequence of 231-1). ................ .......................123

5-1 A differentially coded HSRC-OQPSK transceiver architecture to resolve the fourfold
ambiguity issue (a) the receiver includes a 2:1 multiplexer for serializing I/Q channel
data (b) alternative architecture without using a multiplexer. ............. ....................13

5-2 An example of a conceptual architecture for resolving four-fold ambiguity issue
using eight bits SYNC field. ............. ...............132....









Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

DESIGN OF MULTI-GIGABIT SERIAL LINK TRANSCEIVER USINTG BANDWIDTH-
EFFICIENT HALF-SYMBOL-RATE-CARRIER OFFSET QUADRATURE PHASE SHIFT
KEYING MODULATION

By

Hyeopgoo Yeo

August 2007

Chair: Jenshan Lin
Maj or: Electrical and Computer Engineering

My research introduces new quadrature phase-shift-keying (QPSK) modulation techniques

for high- speed data communicate on sy stem s that use two orthogonal half- symb ol -rate-carri er

(HSRC) signals by which channel bandwidth requirements are reduced compared to that of the

conventional non-return-to-zero (NRZ) modulation. The proposed HSRC offset-QPSK (HSRC-

OQPSK) improves spectral efficiency by reducing the side lobes of the signal spectrum. In

addition, HSRC minimum-shift keying (HSRC-MSK) modulation is also introduced. The

performances and the simulation results of the proposed modulation techniques are studied and

compared with those of the conventional ones.

Using the proposed HSRC-OQPSK modulation, a prototype transmitter generating the

HSRC-OQPSK signal was designed and built. Measurement results confirm the theory that the

proposed HSRC-OQPSK modulation improves spectral efficiency by reducing the second lobe

of the signal spectrum by 10dB. Furthermore, the HSRC-OQPSK modulation reduces the first

null bandwidth by 25% compared to the standard Non-Return-to-Zero (NRZ) modulation. Like

NRZ, HSRC-OQPSK uses a 2-level data decision which enables a simpler transceiver









architecture than multi-level pulse amplitude modulations (PAM), such as 4-PAM and

duobinary.

My research also examines a modified Costas loop for the clock and data recovery (CDR)

involving HSRC-OQPSK modulation. Behavioral model simulation has verified analysis of the

proposed CDR. The carrier frequency of the HSRC-OQPSK signal is quarter data rate. Hence the

proposed CDR is comparable to quarter-rate CDR using quadrature-phase VCO (QVCO), which

relaxes the timing constraints and allows a simple structure as well.

The HSRC-OQPSK transceivers are implemented and simulated with TSMC and UMC

0.18Cpm CMOS technology to prove the theoretical performance. The theory and the

measurement results show that it is feasible to increase the data-rate in wire-line communications

using low-cost channels.









CHAPTER 1
INTTRODUCTION

1.1 Motivations

These days, a demand for high data rate transmission through low cost band-limited

channels (e.g., copper trace on FR4 PWBs and CAT-5 cables) is increasing. Data transmission

with binary format, (represented by non-return-to-zero (NRZ) format) to receive data looks very

simple and clear. However, it is a real challenge to high data rate communications over the band-

limited channel because of impaired signal loss, reflections, and crosstalk. Although parallel I/O

data transmission is efficient for short length data communications, it suffers from a large data

skew and jitter for the aforementioned reasons. Obviously, those problems will be more severe as

data rates and channel lengths increase. The high speed point-to-point link, a serial link, can

overcome these kinds of bottlenecks. It offers high data transmission, up to multi-gigabit data

transmission, over a long PCB trace, and a cable line. The transmitted signal bandwidth for the

point-to-point links increases directly proportional to the data rate. Since a low cost channel,

such as a PCB trace (e.g., copper cable), has low-pass characteristics, the high frequency loss of

the transmitted data is unavoidable, as shown in Figure 1-1. This frequency dependent low-pass

characteristic largely comes from the skin effect of the material as well as dielectric loss of the

material. Figure 1-1 also shows the frequency characteristics of the FR4 PCB with various

lengths. 10 GHz signal attenuated about 20dB in 5002 characteristic impedance of 20" length

with a tangential loss of 0.023. Besides board trace, a board attachment, a connector, and IC

package make parasitics. Unfortunately, these cause nonlinear effects such as reflection,

resonance, and ripple.

















-0 -20 -1 15'




20'
-30 1111
0 2 4 6 8 10 12 14 16

freq, GHz

Figure 1-1 Characteristics of a PCB trace channel with various lengths.


The non-return-to-zero (NRZ) signal, which is the same as PAM-2, is commonly used for

digital systems including high speed serial links. The NRZ signal, defined as binary data, can be

very simple because the signal has 2-levels and is easily implemented by digital circuits. An eye

diagram is usually used to estimate signal quality. The signal is chopped into equal periods and

accumulated onto one plot. The eye diagram gives visual information regarding signal usefulness

in data communication systems [1].

Unit Interval










Zero-crossing Ideal sampling point
jitter

Figure 1-2 Basic information of eye diagram.










Figure 1-3 shows an example of the eye diagrams for various trace lengths. The 10Gbps

random binary data is applied to the input port and the output signal is monitored. The eye

diagram has no jitter components and its opening is very clear with 0.1" channel trace. However,

as the PCB trace increases, distortion and jitter components are introduced to the signal and the

eye opening is almost closed after 20" trace, as shown in Fig. 1-3(a).







-0 2-0 2 -0 2
-20 20 40 0 8 10 12 14 16 18 20 22 -2 0 0 4 60 80 00 20 40 60 80 00 20 20 0 20 40 60 80 100 120 140 160 180 200 220
time, psec time, psec time, psec

(a) (b) (c)

Figure 1-3 Eye diagram of the 10Gbps signal at the far-end after tracing (a) 0. 1" (b) 10" (c) 20"
PCB channel.


Conventional parallel buses are used for short range data links such as system buses

between CPU and the main memory to increase the data-rate. However, there are several crucial

limitations to increase data-rate to infinity. First, in high-speed parallel buses, signal jitter and

data skew occur due to the crosstalk between signals, which causes a synchronization problem

between the signal lines at the receiver-end. The synchronization mismatch prevents the

appropriate data transmission between the transmitter and the receiver even though a precise

clock signal is used for the data fetch. Figure 1-4 shows the example of data skew between the

signal lines and the misaligned data arrival at the receiver-end, which causes the wrong data

transfer. Moreover, the skew problem is getting more severe as the clock frequency goes high [2].

Instead of using parallel buses, point-to-point communication called a serial link is used to

resolve the skew problem. This communication uses a low-swing signal instead of a

conventional large swing signal with the terminations which prevent the signal reflection. The










low-swing signaling can also reduce the power dissipation. However, to convert the parallel-bit

data into a serial data, the clock frequency should be increased by the parallel bit times for

maintaining the data-rate. However, this method can resolve the data skew between the data in

parallel bits, hence, the synchronization problem can be fixed even if the jitter is introduced to

the signal. Of course, the duration of the data fetch timing is reduced due to the jitter in the signal.

Figure 1-4(b) shows the example of the serial link.


Tx Rx

Parallel Bus : :


Crosta1 1 IitrSe

(II
SeriI I Ii

I Bckln PB UE thret pIc ln I I
ex)I ISP:48Ml
(II
Figure~I 1 Hg aart rnmsi wt a ovnin prle u b rIa ik

Since~~I I eilln ssavr ihfeunycokcmae oaprle u ytm h










commnicaion (Baohwockmplnane PCB, USB, Ether cy net, y Optca link) nlan rc









the transmitted data at the receiver, including clock and data recovery (CDR) using the

transmitted signal.

1.2 Compensation Techniques of High Frequency Signal

1.2.1 Pre-Emphasis Signal

There are two primary approaches to improving high speed data link limitation over the

low-cost channel. First is a direct compensation of the signal's high frequency component during

transmission and reception. Pre-emphasis of the PAM-4 transmitted signal with an equalizer

implemented by a multi-tap finite impulse response (FIR) filter has been demonstrated in [3-4].

The equalization distorts the transmitted signal by giving the signal high frequency energy,

hence, the signal arriving at the receiver-end has more power compared to the non pre-emphasis

signal, which are shown in Figure 1-5. However, it is still challenging to implement the equalizer

in the GHz range with CMOS technology [5].

Pre-emphasis
Signal



Received Signal


/Received Signal without
apre-emphasis







Figure 1-5 Pre-emphasis of NRZ signal and received signal with/without pre-emphasis.


Figure 1-6 depicts the pre-emphasis in the frequency domain. The band-limited channel is

characterized as a low-pass characteristic as discussed in the previous section. The FIR filter for










the pre-emphasis of the signal should have a high-pass characteristic to compensate the energy of

high-frequency signal which will be attenuated more than the lower frequency signal energy.

However, this technique is very challenging in GHz range with CMOS technology as well as

requires high speed sampling DAC, ADC for the PAM-4 signal, which increase the system

complexities [3-4].


Transmitted Signal




Received Signal
Channel










Figure 1-6 Frequency domain representation of the pre-emphasis technique of the transmitted
signal.


1.2.2 Broadband Circuit Technique

Besides the direct compensation of high frequency components, broadband circuit

techniques to broaden the limitation of the operation frequency of the circuit, such as an inductor

peaking, capacitive degeneration, a Cherry-Hooper limiting amplifier, and a fT doubling, can be

classified as compensation techniques of the high frequency signal [6].

Inductive peaking is one of the broadband techniques widely used to increase the

bandwidth of the amplifier. However, a passive inductor integrated in chip occupies a large chip

area. An active inductor implemented by an active device such as a MOS can be used to save the









chip area. Detailed active inductor analysis is presented in [6]. Figure 1-7 shows the active

inductor implemented with a PMOS device and its equivalent models.

VDD Rs


II M1CGS VR2 R1 Zout

Zout Vx



Figure 1-7 Active inductor (a) realized with NMOS source follower (b) small signal equivalent
circuit (c) simplified model [6].


The small-signal equivalent circuit is obtained as (1-1), (1-2), and the impedance of the output

node is derived as (1-3).

jCOCGsV1 + gmV1 = -Ix (1-1)

jaoCcsV1Rs + V1 = -Vx (1-2)


Zo,= (1-3)
g,,,g + jeiCGS

Note that if Rs >> 1/gm, absolute value of the Zout is increasing with frequency, which behaves

like an inductor and is modeled as depicted in Figure 5-1(c) where R1= Rs 1/gm, R2 = l/gn.

Then the value of the inductor, L is obtained as (1-4).


L = CGS, Rs 1, (1-4)


To get a high quality (Q) factor of the active inductor, we must maximize R1 and minimize

R2. Since the Q of the parallel combination of R1 and L is represented by Rl/moL and R1/L =

gm/Ccs, Rs does not affect the Q factor significantly. However, the active inductor mainly

suffers from its voltage headroom for the operation. To relieve voltage headroom, a modified









active inductor with NMOS has been developed; however, the achievable bandwidth of the

circuit is limited compared to those using a passive inductor.

Other broadband techniques such as a capacitive degeneration, a Cherry-Hooper limiting

amplifier, are studied well in [6].

1.3 Modulation Techniques

1.3.1 Conventional Modulation Techniques

Pulse amplitude modulation (PAM) -strictly baseband PAM- signal is most often used in

high-speed data communications, such as a serial link communication because it is easy to define

its level of "1" or "O" and implement with a simple digital circuit. However, it needs a relatively

large bandwidth requirement for the data transmission. For high-speed serial link over the band-

limited channel, it is important to reduce the bandwidth requirement of the transmitted signal

because the channel has low-pass characteristics, as discussed in the previous section. Multi-

PAM (e.g. 4-PAM) which reduces signal bandwidth requirement has been introduced and

demonstrated to increase the data-rate [3]. Duobinary, which is characterized as a 3-level PAM,

has also been introduced [7]. However, in these multi-PAMs, it is difficult to maintain the linear

spacing between levels in low-voltage and low-power application and as a result the system's

performances are degraded. The level spacing also causes complexity in the transceiver design

not only because the received signal needs to be linearly amplified but also because the multi-

PAM signal requires accurate reference voltages.

Second is a modulation technique that reduces the transmitted bandwidth signal, such as

multi-level pulse-amplitude modulation (PAM). Four-level PAM (known as PAM-4) signaling

for serial links using CMOS technology has been proposed and demonstrated over the band-

limited channels [3], [8]. Obviously, the PAM-4 data rate is double that of a non-return-to-zero

(NRZ) with the same bandwidth signal because the former uses four-levels instead of two-levels.










Figure 1-8 shows the signal spectrums of baseband PAM-2 and PAM-4. The PAM-4 signal

occupies exactly half of the bandwidth of PAM-2 signal. However, the multi-level signal reduces

the signal energy hence degrading the BER performance. Moreover, electrical limitations of the

system such as low supply voltage resulting from device scaling make the system design more

difficult. For example, the level spacing of the PAM-M signal is inversely proportional to (M-1).

Therefore the level is much smaller in low voltage systems, which are vulnerable to noise and

also require a more precise ADC for the reliable communications. Recently, duobinary signaling,

a 3-level PAM, for the backplane serial link has been introduced and demonstrated for serial

links applications [9]. The duobinary signal has only three signal levels which offer higher signal

energy than the PAM-4 signal within the same voltage system.

10 1I


1.5
flBR (Hzlbit/s)


Figure 1-8 Comparison of PAM-2 and PAM-4 signal spectrum.









1.3.2 Modulation Technique Using Half-Symbol-Rate-Carrier (HSRC)

On the other hand, a carrier modulation such as a phase-shit-keying (PSK) modulation is

difficult to be used in the serial link data communications because the carrier signal makes

baseband data to the passband signal. Figure 1-9 shows basic digital modulation schemes using

carrier signals. Digital modulation is using an analog carrier signal to modulate the binary digital

sequences. The basic digital modulation schemes are depicted in Figure 1-5. Amplitude-shift-

keying (ASK) is the modulation technique that mixes the baseband binary data with a carrier

signal. The carrier signal is generated when the data is high, otherwise the amplitude of the

carrier goes zero. Frequency-shift-keying (FSK) modulation has two different frequency carrier

signals representing one or zero data. Baseband data is used for the information of the frequency

to be generated from the carrier signal generator which will be usually implemented by a voltage

controlled oscillator (VCO). Phase-shift-keying modulation uses one carrier frequency signal

different from the FSK. The phase of the carrier signal is changed as the baseband data changes.


1 00 01

















(d)

Figure 1-9 Basic digital modulation schemes (a) baseband data (b) ASK (c) FSK (d) PSK.









1.3.2.1 Why Not Carrier Modulation?

These carrier modulation techniques shift the spectrum of the baseband data to the carrier

frequency, as shown in Figure 1-10(a). Usually the carrier frequency is much higher than the

baseband data-rate. Applied to the baseband data communications, the carrier modulation shifts

the baseband data information to the carrier frequency so that the required bandwidth to transfer

the baseband information would be increased as shown in Figure 1-10(a). Consequently, it is

inevitable to waste the required bandwidth of the channel with this carrier modulation.

What happens in the PSK signal if the carrier signal is sub-symbol-rate? Figure 1-10(b)

shows the spectrum where a half-symbol-rate carrier is used as a carrier modulation signal. Both

main lobes of spectrums at positive and negative frequency are overlapped. The modulated

signal is characterized as a passband signal due to the carrier modulation; however, the spectrum

of the signal looks like that of a baseband signal, as depicted in Figure 1-10(b). This signal

would be called the pseudo-baseband signal. Quadrature modulation using two orthogonal carrier

signals can be defined. With this quadrature modulation quadrature PSK (QPSK) technique,

the bandwidth requirement of the baseband data can be reduced by half compared to the PSK

modulation using a single carrier signal [10]. What if the quadrature modulation uses the HSRC

signal? As mentioned earlier, the spectrums are overlapped as shown in Figure 1-10(b) so that

the modulation reduces the first-null bandwidth of the spectrum by 25% than that of non-return-

zero (NRZ) modulation.

My research mainly focuses on a signal modulation technique to reduce the bandwidth of

the transmitted signal. Modulations based on PSK are proposed and analyzed. The conventional

PSK type modulations are well-studied in [10-11]. The proposed high speed data links signal

modulation techniques modulating digital data with a half-symbol-rate carrier using phase-shift

keying (named as HSRC-PSK).


















Required Bandhn/dth


(a) (b)

Figure 1-10 Simplified spectrums of carrier modulation signals (a) using carrier signal higher
than data-rate (b) using half- symb ol -rate-carri er signal.


Like binary phase-shift keying (BPSK) and quadrature phase-shift keying (QPSK) used in

wireless systems using radio frequency (RF) carriers, this HSRC-PSK modulation technique can

be extended to quadrature type modulations using two orthogonal carrier signals, such as QPSK,

offset-QPSK (OQPSK), minimum shift keying (MSK) modulations popularly used in wireless

communications. These quadrature type PSK modulations can increase the data rate with nearly

equal signal energy [9]. The proposed half-symbol-rate carrier modulation technique is similar to

conventional modulation techniques. However, their properties are not identical and the analysis

is given in this report. Effectively, the half-symbol-rate-carrier modulation performs waveform

shaping on the data bits when transmitted through band-limited channels. The signal spectrums

of proposed modulations are derived in analytical form and their bit error rate performances are

simulated. The results are compared to conventional modulations.

The HSRC-OQPSK signaling is especially chosen as a possible modulation candidate for

high speed serial links, implemented and simulated by TSMC and UMC 0. 18um CMOS

technology.









CHAPTER 2
HSRC PHASE SHIFT KEYINTG (PSK) MODULATIONS

2.1 Binary Modulation

A binary PSK (BPSK) signal whose sinusoidal carrier amplitude is Ac can be represented

by (2-1) where m(t) is the binary data signal, Tb is the bit period, fe, is the frequency of carrier,

and Oc is the phase of the carrier [12].


s(t) = m(t) A, cos(2zft + 8c) 0

Let us now consider a special case where fc=1/2Tb (NygUISt bandwidth) and Oc=-n/2. With

this condition, the BPSK signal can be represented by (2-2).




s~~t) =O)-A sn t 0


Since the carrier signal frequency is within the baseband, this modulation is similar to

signal waveform shaping rather than modulation. The baseband data are mixed with a carrier

whose frequency is the same as one half of the symbol rate, fc=1/2Ts, where Ts is the symbol

period, and T,= Tb in BPSK. Figure 2-1 shows the concept of half-symbol-rate-carrier BPSK

(HSRC-BPSK) modulation.







sin( r/Tb)t

Figure 2-1 HSRC-BPSK modulation: baseband data sequences and modulated signal.









2.2 Quadrature Modulations

2.2.1 HSRC Quadrature PSK (QPSK) Modulation

HSRC-QPSK modulation is similar to a conventional QPSK modulation. The conventional

QPSK signal can be represented in (2-3), where m; and mQ are the data sequences in their in-

phase (I) and the quadrature-phase (Q) components, respectively, andf, is the carrier frequency

which is generally larger than the symbol rate.

1 1
s(t) = mi (t) cos 2(7Ct + mo (t) sin 2(3Ct (2-3)


However, for multi-Gb/s data communications (i.e. backplane serial link), it is often

unpractical to generate a carrier frequency higher than the symbol rate. To address this issue, the

HSRC-QPSK modulation is proposed, as shown in Figure 2-2(a). The HSRC-QPSK signal is

obtained by substituting QPSK's carrier frequency, as f=1/(4Tb), where Tb is the bit-period,

which is the half-symbol-rate-carrier frequency, as shown in (2-4).



s~t)= 1t m(co t+ 1mei,(t~i (2-4)
JZ~2Tb Z 2Tb


Since the carrier frequency is lower than the data-rate, the phase of the carrier signal can

affect the modulated signal's properties. Therefore, the phase of the carrier signal is fixed to

define this modulation. The theoretical time domain HSRC-QPSK waveforms are shown in

Figure 2-2(b).


2.2.2 HSRC Offset QPSK (OQPSK) Modulation

The HSRC-OQPSK shares the same architecture as HSRC-QPSK shown in Fig. 2-2(a). Its

signal is obtained by staggering (offsetting) I and Q by Tb, as shown in Figure 2-2(c). The

HSRC-OQPSK signal can also be defined by (2-3) but using offset sequences of m; and mQ [13].












m (t)


Parallel -sm(7t/2T )t

m,(t) A Is (t)










3 ~ Tb 5Tb 8b b



0 2Tb 5b 6Tb 9b



o Tb 3Tb 5Tb 8bb




Tb 3Tb 5Tb 7b 9b

s~(c)


m2 ,

s;r Z 4 6b 8b



0 2Tb 4T 6Tb STE
s,(r)


0 2T, 4T 6T, STE




0 2T, T,, 6T, ST,




(b)


Figure 2-2 HSRC-QPSK and OQPSK (a) modulation scheme, (b) QPSK time domain
waveforms, (c) OQPSK time domain waveforms.



This is the same as the direct combination of conventional MSK's I/Q channels without the

mixing of the carrier frequency. As shown in Figure 2-2(c), the combined signal is free from any

discrete transitions. If the in-phase signal is at its peak of either positive or negative value, the


quadrature-phase signal is zero at every 2TI,. On the other hand, if the quadrature-phase signal is

at its peak of either positive or negative value, the in-phase signal is zero at every 2TI,. Therefore,

the combined signal has no discrete transitions.










2.2.3 HSRC Minimum Shift Keying (MSK) Modulation

The HSRC-MSK modulation can be obtained by applying the HSRC signal to the

conventional MSK modulation format as described in (2-5) and shown in Fig. 2-3(a). As shown

in Fig. 2-3(b), the data sequences of I/Q channels are the same as those of the OQPSK as well as

the proposed HSRC-OQPSK. The resulting HSRC-MSK time domain data sequences are the

same as the original data sequences.



s(t) = m, (t) cos t + m, (t) sin t (2-5)




mi(t) sif i
172 172 17 2, 172 m Serial cos(x/2T,) cos(x/2T )t st
ml m, I Pa Illel sm(12/2Tb )t smbx/2Th )t

0 2Tb 4Tb 6Tb 8Tb ,( s,(t)
(a)



0 2Tb 4Tb 6Tb 8Tb
m (t) m3 m5
m, l
rb bT 5Tb 7Tb 9T,



0 2Tb 4Tb 6Tb 8Tb



Tb bT 5Tb 7Tb 9T,

s(t)~~f

Tb bT 5Tb 7Tb 9Tb
(b)

Figure 2-3 HSRC-MSK (a) modulation scheme (b) time domain waveforms.









The modulated signal described in (2-5) has the same data sequences to those of the

original binary data which is shown in Figure 2-3(a). This is similar to raised-cosine

approximation (RCA) signaling [14].


2.3 Signal Spectrum

Since the frequency of the carrier signal is lower than the data-rate, the carrier signal can

be effectively considered as a spectral pulse-shaping. The spectral pulse-shaping function of the

proposed modulations is derived as shown in (2-6) by applying the similar approach described in

[10]. Note that the pulse-shaping function of HSRC-QPSK and HSRC-OQPSK are different,

although the pulse-shaping functions of the conventional QPSK and OQPSK are the same.


:0 < t < 2Tb for HSRC QPSK

:0 < t < 2Tb for HSRC OQPSK

:0 < t < 2Tb for HSRC MSK
:elsewhere


(2-6)


a (t) =


The normalized power spectral densities, S(f), are derived by the Fourier transforms of (2-

6), S(f)=|GVf)|2/T, where G(f) is the Fourier transform of any given g(t) [10]. Using this equation

and combining with trigonometric identities of sin(x)=(e'x-e-ix)/2j, cos(x)=(e'x+e-ix)/2, the final

forms ofSVf) can be equated as (2-7). Their plots are shown in Figure 2-4.


:HSRC-QPSK

:HSRC -OQPSK

:HSRC -MSK


(2-7)


2 Tb 4




-2T


16TbT bCO C7~s 24

S~f.)= <-T coZT
,2 1 -16 f Tb24i
sin 27zff









10
NRZ (PAM-2)
--* HSRC-MSK
0+ **** HSRC-QPSK
** --- HSRC-OQPSK(MSK)


mj -10 R \. I Lir






C~SI I at i

-60 1 I is t
0 0.5 1. 2 2.5
flB (Hzbi/s
Figure 2- omlzdpwr pcrldniyfo SCmdltos








thgue o 4nvetonalie NRZ. pcra est frHR odltos

Frthe fisid nul obes, h SR-PS HSRC-OQPSK shrsteampue-apin wthu the lconventioa

MS.75b Therefore, their HiSRC-OQPSK ponwitaer spectra desiy sh% ouldals e ietica toe frthatof






MSK, which is presented in [1 l]. Also, they fall off more rapidly (1/4') than those of the

conventional NRZ (1/f2) [1l]. The side lobes of the HSRC-MSK fall off even more rapidly (1//)

and therefore the high frequency components can be further suppressed [14].










Recent semiconductor technologies scaled down the transistor size, which results in the

reduction of supply voltage. In low voltage circuits, PAM-4 modulation, that requires linear

amplification, is more difficult to maintain the same spacing between levels. The HSRC-OQPSK

is expected to have advantages over this because it does not need to space levels. Especially, for

the amplifiers to be operating at power saturation, MSK has superior performance to QPSK [13].

For bandwidth efficiency, the spectrum of HSRC-OQPSK, which is the same as MSK, contains

99% of the total signal power within the bandwidth, B-(1.2/Tb), while for QPSK and PAM-4, the

99% bandwidth increase to B~(8/Tb) [13], [15]. Therefore, it is expected that the HSRC-OQPSK

should have the effective signal spectrum in band-limited channel, such as backplane serial link.


2.4 Bit Error Rate (BER) Performance

The BER performances are characterized using a coherent demodulation with a matched

filter in Additive-White-Gaussian-Noi se (AWGN) channel for the proposed HSRC modulations

are simulated via MATLAB. The HSRC-QPSK signal has only one symbol energy, E,.

Therefore, it is expected to follow the same BER performance of the conventional QPSK, as

shown in Figure 2-7.


E E E E
s, st ,I s, t s,p _I sf






E 'E E E'
sf s, p s, t s, t

Figure 2-5 Modulated time domain signals of HSRC-OQPSK and its symbol energies.


For the HSRC-OQPSK, the BER performance result is different from that of the

conventional OQPSK, due to the existence of three different symbol energies namely, Es~r, Es y,









Es,p. For the case where the quadrature symbols are evenly transmitted, an example of s(t)

illustrating the three different energies is described in Figure 2-5.

The upper sequences are for the I channel while the lower sequences are for the Q channel.

The different three symbol energies can be calculated by integrating the square of the modulated

signal (Ils(t)|2dt) over a 2 bit-time (2Tb), aS Shown in (2-8)~(2-10). Es,r is the symbol energy for

the case where only one of the 2 bits transits between its high and low points. This symbol

energy is the same as that of the conventional QPSK, Es. Es f is for the case where both 2 bits

remain in its high or low points (remains flat). Finally, Es,p is when the signal peaks by

consecutive transitions. Note that the final terms in (2-9), (2-10), Es7f, Es,p are expressed in scalar-

multiples of Est by kf, k,, respectively.


E,,, = A inl + 2d (2-8)


E,, 2- C in + d =kE,, k (2-9)







The average probability of errors of s(t) can be calculated using (2-10), where M~is the

number of different types of symbols [10], [12]. As was the case in Figure 2-5, this equation

assumes that M~ symbols are evenly transmitted, where s, represents one of2 Mpossible symbols

of the modulation signal.



Pe~)= (e |, se)(s1)= [ ee|s)(-1









If we define noise energy to be N, the BER can be expressed in terms of energy-per-

symbol (or bit) to the noise-density ratio of the three energies, as shown in (2-12)~(2-14). Note

that in the final terms of (2-13) and (2-14), the noises are scaled to an effective values, so that the

signal energies can be considered as a function of Es>.

E, E
= -(2-12)
N N

Es,J f, s,t Es,t
(2-13)
N N N /k,

Es ~ kp -E, Es~
(2-14)
N N N/k,

In the AWGN channel, the noise N, has a Gaussian distribution with the mean being 0 and

the variance being V/2No. Hence, the scaled effective noises of N/kf and N/k, also have Gaussian

distributions where the means are 0 and variances are V2No/kf2 and V2No/k,2, TOSpectively. With

these parameters, the probability of errors for each symbol can be obtained by integrating the

Gaussian distribution functions over the error decision section as shown in Figure 2-6. Therefore,

the BER of HSRC-OQPSK in AWGN channel can be derived as (2-15), where Eb=Es/2 and

Qx=1 Jexp -x' /2 .








The 1/2 weight in the first term and the 1/4 in the second and last terms account for the fact

that Es~r occurs twice as often as Esf or E,,, in an evenly transmitted quadrature symbols. As

shown in Figure 2-7, (2-15) fits well with the results obtained from MATLAB.











........ Es,t/N
Es,r/N
-------- Es,pfN


2L


Fiur -6Gas iandstrbto fdfeeteeg ymosfrHR-QS ouain






samue as6 thssat o therbuo HSCOQS' caseeand therg rsublts symbol nergie and te BER f HSRC





OQPSK are shown in (2-16), (2-17), and (2-18), respectively.


E ,t, = A sin cos jdt = A,2Tb (2-16)

? 2Tb 2T

E = A, sinI ~ + cos I 1dt = 2A,2Tb. (2-17)




P,' = 3 O Q +T. I -(3 Q O (2-18)


The analytical results are compared with those obtained from the MATLAB simulation as

shown in Figure 2-7. From the results, we observe that the HSRC-QPSK modulation has no

degradation of BER performance as compared to the conventional QPSK, which has almost the










same BER performance as that of the NRZ modulation. Therefore, HSRC-QPSK can be used as

a modulation technique for high-speed broadband communications with less bandwidth

requirement while keeping similar BER performance of NRZ. On the other hand, the HSRC-

OQPSK and HSRC-MSK modulations have less BER performances but having even more

efficient signal spectrum characteristics as described in the previous section.

100
-Theoretical QPSK
Theoretical HSRC-MSK
-1 -*- Theoretical HSRC-OQPSK
10 @".9, simulated HSRC-QPSK
Simulated HSRC-MSK
S) Simulated HSRC-OQPSK
10-2




10




104 b



0 5 10 15 20
EblNO (dB)


Figure 2-7 Comparison of theoretical and simulated BER performance of HSRC modulations.


The BER performances of the proposed HSRC PSKs' are calculated by demodulation with

the matched filer. Generally, the demodulation with a matched filter enables the system to have

the best performance. However, a different result is obtained in the HSRC-OQPSK modulation.

Figure 2-8 shows demodulation process of I (or Q) channel at the HSRC-OQPSK receiver which

is presented in Chapter 4 in detail and the demodulated peak signal of the HSRC-OQPSK, which

has a low symbol energy, E,,. The carrier signals are mixed with the incoming signals, as shown

in Figure 2-8. The demodulated signals at the first half bit time and the last half bit time periods










have negative values while the signal at the middle bit time period is positive. Therefore, the

integration of the demodulated HSRC-OQPSK signal over the period of 2Tb is less than that over

the period of Tb, as shown in Figure 2-8.

Carrier Signal




Input Signal













Bit Period (Tb)

: Symbol Period (2Tb)
(b)
Figure 2-8 The demodulated signal (a) demodulation process of I(or Q) channel (b)
demodulated peak signal (Es,p) Of the HSRC-OQPSK.


Since a matched filter is not used in the actual realization of the receiver (the level decision

is made by a clocked flip-flop (FF)) which is discussed in Chapter 4, the integrated value of the

demodulated signal over the period of Tb produce more realistic BER performance. The signal

energy is calculated as (2-19).


E = 2 -Ia Af cos + -sn d -T E s,t ; -(-9


Since the BER performance of the HSRC-OQPSK modulation is mainly determined by

third term of (2-15), the BER performance with the symbol energies of (2-19) can be represented

as (2-20) approximately.











P~ .j1 Q2,, (2-20)2


Figure 2-9 shows the theoretical BER performance using symbol energies of (2-19) and

simulated BER performance. From the simulation results, the difference of the BER

performances between the theoretical PAM-2 (NRZ) and the HSRC-OQPSK is approximately

4dB instead of 8dB (shown in Figure 2-7). The difference between the theoretical and simulated

BER performance is caused the noise amount integrated during the bit time period is, Tb, iS

different from the total noise introduced in the AWGN channel. Although, the absolute values of

the BER performance using an AWGN channel would be different from that using a band-

limited channel, the difference of the BER performance is comparable to those in the band-

limited channel.

100
Reoretical PAM-2 (NRZ)
Theoretical HSRC-OQPSK (Tb time integration)
--- Teoretical HSRC-OQPSK (2Tb time integration)
10-1 Simulated HSRC-OQPSK (Tbtime integration)





10 \


w10

10~1



10
0 5 10 15 20
EblNO (dB)
Figure 2-9 Comparison of the BER performance between the symbol time (matched filter) and
the bit time integration of HSRC-OQPK signal.










To estimate the BER performance in the band-limited channel, a simple low-pass filter

having one pole, which is characterizing a band-limited channel, is added to the channel. The

transfer function is (2-21) and Figure 2-10 shows the frequency response of (2-21). The

characterized channel is comparable to the band-limited channel which has the loss of

0.75dB/GHz approximately.


3 -10'0
H (s) =
s + 3 10'0


(2-21)


-8


-10


-12
0 2 4


Figure 2-10 Frequency response of the
filter.


6 8 10 12 14 16
Frequency (GHz)
band-limited channel modeled with a one pole low-pass


Figure 2-11 shows the simulated results of the 10Gbps system. Approximately, 5dB more

signal power is needed with the band-limited channel modeled as (2-21) to get the same BER

performance, which is caused energy loss of the transmitted signal in the band-limited channel

modeled as (2-21). From the frequency response depicted in Figure 2-10, 5GHz signals which is

comparable to 10Gbps data rate are losing their energy of 4dB by the band-limited channel.









However, the difference (4dB) of the signal to noise ratio per bit (Eb No) between the NRZ and

the HSRC-OQPSK is almost the same as the simulation result without the band-limited channel.

If the signal power is enough compared to noise introduced in the channel, the energy loss of the

signal in the band-limited channel mainly determines the BER performance of the system.


100
aSimulated PAM-2 (NRZ)
Simulated HSRC-OQPSK

10-1 n



10-2






10-4



10
0 5 10 15 20
EblNO (dB)
Figure 2-11 Comparison of simulated BER performance of the PAM-2 (NRZ) and HSRC-
OQPSK modulation with band-limited channel.


2.5 DC-Free Signaling Based on HSRC-OQPSK Modulation

The ac coupled interconnect gives several advantages over the dc coupled interconnect.

First, the ac coupled channel would provide more flexible interconnection between the various

signal standards [16]. Second, the ac coupled interconnect allows high density and low-power

chip-to-chip communication. Recently, an ac coupled interconnect (ACCI) for the chip-to-chip

communication has been introduced and its performance demonstrated [17]. It enables low

power properties as well as high density I/Os. Moreover, an on-chip capacitor formed under pad









blocks the de levels of the signal line which allows communication between the chips using a

different voltage level. However, capacitive coupling interconnect suffers from the "zero

wander" effect [16]. The capacitive coupling characterized as a high pass filter tends to cut off

the dc or low frequency information. However, it is very difficult to compensate the loss of the

signal where an ac coupled interconnect is used in a long line channel, such as a high-speed

serial links because both low and high frequency signal information should be compensated due

to the high frequency signal loss in the channel being characterized as a low pass filter.

Therefore, a modulation technique that removes the dc or low frequency component seems to be

more effective in this long line channel communication to relieve this "zero wander" problem

effectively .

This section investigates a modulation technique that removes the dc component in the

signal, which is relied on half-symbol-rate-carrier offset QPSK (HSRC-OQPSK) modulation.

The proposed dc-free signaling can not only remove the dc and low frequency components but

also maintain the (first-null) bandwidth of non-return-to-zero (NRZ) signal which is use in data

communication of the most conventional digital systems. In telecommunications, the transmitted

data are often encoded with 8B/10B [18] that converts 8-bit symbols to 10-bit symbols for proper

dc balance to guarantee clock and data recovery (CDR) operation at the receiver. This encoding

scheme will increase the transmitted data bandwidth by 20%. However, the 8B/10B encoding

might not be necessary for this modulation because the modulated signal includes the carrier

signal and no dc components. Consequently, this dc-free signaling will decrease the required

bandwidth by 20% effectively. As analyzed in section 2.4, approximately 4dB more signal to

noise ratio per bit is required to get the same BER performance of the NRZ modulation.










Decreasing data-rate by half, TB=2Tb, with maintaining data offset of Tb of (2-4), we can

get another modulation which can be characterized as a half bit time, TB/2, offset QPSK using a

quadrature symbol-rate-carrier (HRC) signal. The signal can be obtained as (2-22) simply by

substituting 2b= TB Of (2-4). Figure 2-12 shows the modulation scheme and its time domain

waveforms.


s(t) = mI(t'cos t+ mo~~tysin (2-22)



n~t()mt)s)
m, nt3 4, 6 n, Serial -cos(>r/T,)t / s(t)
nt #Es ms Parallel ~si ~rTB)t
0 2T, 4T, 6T, 8T, m (t selt)
(a)
m,(t) my nr

0 2T, 4T, 6T, 8T,


s;(t)



0 2T, 4T, 6T, 8T,
se(t)

0.5T 2.5T, 45T 6.5T 8.5T,



0. 5T, 2. 5T, 4.5 T, 6. 5T, 8. 5T,
(b)
Figure 2-12 DC-free modulation based on HSRC-OQPSK (a) modulation scheme (b) time-
domain waveforms.


Unlike conventional OQPSK modulation, data offset of the dc-free modulation using SRC

signal is half bit time not 1-bit time as shown in Figure 2-10. As shown in Fig 1(b), there are no

discrete transitions in the signal like HSRC-OQPSK, from which we can expect the side lobes of












the signal spectrum to be suppressed like those of MSK. The pulse shaping function of the signal


can be represented as (2-23).





g(t)= sm 08 0 elsewhere


The normalized power spectral density, SVf), is derived by the Fourier transform of (2-23),


SVf)=|GVf)|2/T, where GVf) is the Fourier transform of g(t). The resulting power spectral density is


represented as (2-24).


4 sin 2xff
SCf) = 4T _f1'2


(2-24)


Figure 2-13 shows the theoretical spectrums ofNRZ and dc-free signals. The first null


point of the spectrum of the dc-free signal is located at fB' TB, which is the same as that of the


conventional NRZ.


m
S

v,
A
cu-i


ti -2
a,
a
(I)
L
a, -3
o
a
a, -4
N
(U
E

z


1.5
flBR (Hzlbit/s)


Figure 2-13 Comparison of the spectra between NRZ and the dc-free signals.











The carrier signal moves the dc information of the data to the other frequency range


without increasing bandwidth of the signal transmitted. Moreover, the side lobes of the dc-free


modulation fall off more rapidly (1//') than conventional NRZ (1/f2)


2.5 Measurement of the HSRC-OQPSK Signal


A prototype HSRC-OQPSK transmitter was built and tested because the HSRC-OQPSK is


the most feasible modulation to be implemented for high-speed wire-line data communications,


such as a backplane serial link. The block diagram of the transmitter with test setup is shown in


Figure 2-14.

1/Q Modulator

1Gbps Data I Data ~cM1

Spectrum
180. Power I Analyzer
Splitter 180.Frequency
Doubling g
90~ Pwer

CK Branch LinePoeCmb r
180~ Power -o
Splitter Oscilloscope
Q Data M
500MHz Clock
Signal Generator

"5MHz Pulse 1GHz Clock


Bit Pattern CokI
Generator

Figure 2-14 A prototype HSRC-OQPSK transmitter and measurement setup.



Two wide-band mixers, with a bandwidth of 50~4200MHz, are used as I/Q channel


mixers. A 500MHz quadrature branch-line hybrid power splitter which is constructed with PCB


is used to generate quadrature carrier signals. Figure 2-15 shows the structure of the branch-line


hybrid power splitter. The port2 and port3 received the signal power split equally from port


with a phase offset of 900. Of course, the symmetrical S-parameter characteristic can be observed












due to the symmetric structure. The characteristics of S-parameters are simulated with Ansoft


HFSS and compared to the measured data in terms of their magnitude and phase information, as


shown in Figure 2-16. The splitter can be integrated into a single chip using the passive elements


approach [19].

























Figure 2-15 A 500MHz branch-line hybrid quadrature power splitter structure for HFSS
simulation.






-10t' -

,-15 -- -



T -25--
---- Sirqaulated S12
-30 -- slpmuLaeasl3 -
SInlulated S23
e---a Measured S12
-35 -
W Measured S13
Mes5ured S23
-40--


00 30 40 00 60 70 0
Frequency (MHz)

(a)


Figure 2-16 Simulated and measured characteristics of the 500MHz branch-line hybrid
quadrature power splitter (a) S-parameters (b) phases.

















a,

a,
o
90
r
a,
o 60
a,
v,
m
r
a


200 300 400 500 600 700 800
Frequency (MHz)
(b)
Figure 2-16 (continued).


The two quadrature output signals are split again by using 1800 power splitters. The Oo



signals of the 1800 power splitters are used for the quadrature carriers while the 1800 signals are


fed into the mixer M3 to generate a 1GHz clock signal for the digital bit pattern generator' s


external clock. The bit pattern generator generates 1Gbps pseudo random data for the


transmitter' s I channel. The HSRC-OQPSK modulation requires a serial-to-parallel conversion


with 1-bit time offset. To simplify the test, a 5MHz pulse is inj ected into the Q channel input to


represent fixed-pattern data bits. Time delay from the bit pattern generator is adjusted to


synchronize the I channel data and the carrier signal. Consequently, the overall transmitter data


rate is equivalent to 2Gbps.


Agilent N4906A 3.6Gbps serial Bit Error Rate Tester (BERT) is used to generate 1Gbps


pseudo random data. Agilent 54832D 4Gsa/s oscilloscope and Agilent E4448A spectrum


analyzer are used to monitor the time domain waveforms and output signal spectrum,


respectively. Table I summarizes the components used in the measurement.










Table 2-1 Summary of components used in the measurement.


Device

Mixer (M1, M2)

Mixer (M3)

900 Power Splitter

1800 Power Splitter
Power
Combiner/Divider

Signal Generator

Function Generator

BERT

Oscilloscope

Spectrum Analyzer


Function

I/Q channel mixer

Frequency Doubler

Dividing I/Q channel carrier

Frequency double

I/Q channel signal combine

500MHz carrier source

5MHz pulse for Q channel

1Gbps I channel data
Monitoring time domain
waveform

Monitoring signal spectrum


Model

Mini-Circuits ZXO5-42MH-S

Mini-Circuits ZXO5-30W

Quadrature Hybrid (Branch
Line)
Mini-Circuits ZFSCJ-2-4

Agilent 11636A

Agilent E8254A

Agilent 33120A

Agilent N4906A

Agilent 548320

Agilent E4448A


Frequency Range

5 ~ 4200MHz

300 ~ 4000MHz

500MHz

50 ~ 1000MHz

DC ~ 18GHz

250KHz ~40GHz

15MHz

3.6Gbps Serial
BERT
1GHz /4Gsa/s

3Hz ~ 50GHz


Figure 2-17 shows the measured HSRC-OQPSK time domain waveform and its spectrum.

Since the HSRC-OQPSK signal follows the MSK signal spectrum, the first null point of the

spectrum must be located at 1.5GHz because the equivalent data rate is 2Gbps. Time domain

waveform is also well-matched with the theoretical waveform shown in Figure 2-2(c).

Both time domain waveforms and frequency domain spectrum were measured and

compared to the theoretical predictions. Figure 2-18 shows the measured HSRC-OQPSK time

domain waveform and the theoretical prediction.

For comparison purposes, a fixed pattern of sequences '110' was used for the data pattern

instead of random bit patterns. Therefore, the data sequence of the I channel is

'll0110110......'. Measured waveform matches well with the theoretical waveform as shown in






























Rtten 10 dB


Figure 2-12. A phase mismatch between the data and the carrier signal caused the difference in

waveform .


1


Start Gl Hz btop b.000 ljHz
Res BW 3 MHz UBW 3 MHz Sweep 8.36 ms (601 ats)

(b)

Figure 2-17 Measured characteristics of the HSRC-OQPSK modulation (equivalent 2Gbps
random data input) (a) time domain waveform (b) spectrum.


Random data sequences were fed into the I channel to measure the signal spectrum. As

shown in Figure 2-19, the measured broadband spectrum matches very well with the theoretical

spectrum of a 2Gbps random bit stream. The spectrum's first null is located at 1.5GHz which is


Ref 0 dBm
Norm
Log
10
dB/r











the same as the theoretical value. Other null points match the theoretical predictions as well. The

difference between the measured spectrum's main lobe and second lobe is approximately 23dB,

which agrees with the theoretical value.


10 15 20 25 30 35
Time (ns)
Figure 2-18 Comparison of the theoretical and measured waveforms of HSRC-OQPSK
modulation.


-10
-Theoretical Spectrum
-20

m -30

S-40

S-50








-90
0 1 2 3 4
Frequency (GHz)
Figure 2-19 Comparison of the measured and theoretical spectrum of the HSRC-OQPSK signal.









2.6 Summary

The HSRC-PSK modulations are proposed to optimize spectral efficiency for high data-

rate transmission over band-limited channels. The analysis and simulation results show that the

proposed modulations can be used in high-speed data communications, such as a backplane

serial link.

In the past, a multi-PAM signal (e.g., PAM-4) has been demonstrated to increase the data-

rate in band-limited channels [3]. However, in PAM-4 modulation, it is difficult to maintain the

linear spacing between levels in low-voltage and low-power application and as a result the

system's performances are degraded. The level spacing also causes complexity in the transceiver

design not only because the received signal needs to be linearly amplified but also because PAM-

4 signaling requires accurate reference voltages.

The proposed HSRC modulations not only reduced the bandwidth requirement but also can

be easily implemented in deep submicron integrated circuit technologies with low supply

voltages. The proposed HSRC-QPSK signal has irregular timing transitions and therefore a new

phase detector design for clock and data recovery (CDR) and a matched filter for the

demodulation are required. On the other hand, since such irregular transition does not exist in

HSRC-OQPSK, the HSRC-OQPSK signaling can be used effectively in band-limited wire-line

applications with maximum spectral efficiency. This modulation might be able to optimize the

spectral efficiency for baseband high data rate transmission over band-limited channels.

Compared to the conventional NRZ modulation, the proposed modulation greatly reduces the

bandwidth requirements. For bandwidth efficiency, the HSRC-OQPSK spectrum, which is the

same as the MSK spectrum, contains 99% of the total signal power within the bandwidth of B -

(1.2/Tb). In comparison, PAM-4 has much larger 99% bandwidth of B (8/Tb) [13], [15].

Therefore, it is expected that the proposed HSRC-OQPSK modulation should have an efficient










signal spectrum in band-limited channels. And this spectrum efficiency will reduce the high

frequency crosstalk noise between the signal lines which may improve the performance of the

multi-port serial communication links. In addition, dc-free signaling based on the HSRC-OQPSK

modulation has been introduced. The dc-free signaling is expected to have good performance in

ac coupled channel applications including a flip-chip ACCI.

Measurement results verified that the HSRC-OQPSK modulation can be effectively used

in band-limited wire-line applications requiring spectral efficiency, such as the backplane serial

link. Moreover, because it requires only a two-level decision, the HSRC-OQPSK transmitter can

be implemented in a simpler architecture than PAM-4 and is suitable for low-voltage systems. In

addition, a QPSK carrier recovery structure can be used for the HSRC-OQPSK modulation

which enables flexible design of the receiver, which will be discussed in Chapter 4.

For the HSRC-MSK modulation, it can greatly minimize crosstalk noise compared to the

conventional ones, since the high frequency components are further suppressed [14].









CHAPTER 3
HSRC-OQPSK TRANSMITTER

3.1 Transceiver Architecture

3.1.1 A Conventional Serial Link Transceiver Architecture

Prior to the HSRC-OQPSK transmitter detail, the conventional transceiver and a

conceptual HSRC-OQPSK transceiver need to be investigated. Conventional quadrature

modulation transceiver architectures are investigated in [20-21]. Figure 3-1 shows the simplified

transceiver structure of a conventional serial link. The transmitter has a serializer which converts

the parallel data into serial data using a clock generated from a phase-locked loop (PLL). An

output buffer amplifies the converted serial data for driving a channel. The receiver has a clock

and data recovery (CDR) circuit that includes a phase and frequency detector (PFD). Besides a

CDR, the receiver includes a retimer, and a deserializer. Passing through the channel, the

transmitted signal is amplified with a limiting amplifier allowing the signal to travel through a

CDR. In the CDR circuit, the incoming signal restores a clock used as the clock of the decision

circuit. After the decision, the data may convert to parallel data by a deserializer. Typically, a

reference clock for precise frequency detection is also used to avoid false locking conditions,

which is not depicted in Figure 3-1.

3.1.2 A Conceptual HSRC-OQPSK Transceiver Architecture

Figure 3-2 shows a conceptual HSRC-OQPSK transceiver structure. The signal modulation

uses two mixers and one combiner circuit while two mixers, matched filters and decision circuits

are used for demodulation. This system architecture is basically the same as conventional QPSK

modulation and demodulation system. The quarter-rate clock and data recovery (CDR) is

incorporated with the HSRC-OQPSK receiver because the frequency of the carrier signal is half-

symbol-rate which is comparable to the quarter-data-rate of the system.













Transmitter
Serializer


Receiver
Deserializer

F/F \
Lim iter

CDR





CK




VCO


Channel
.

Jittered
Data







Phase
Detector

Low-Pass
Filter


Data


Figure 3-1 A simplified conventional transceiver for a serial data link.


Though a matched filter for the QPSK signal demodulation improves system performance,


it is hard to implement the matched filter operating at giga-hertz frequency range. So, the


matched filter should be replaced by other circuits which allow the high-speed operation. A high-


speed flip-flop (F/F), and appropriate retiming circuit for the incoming data can replace the


matched filter. The detailed transmitter architecture is discussed in this chapter and the detail


receiver architecture is presented in Chapter 4.


Transmitter


Out
Rx


Linear
Amplifier


Channel


In
Tx


Out.


Receiver


Figure 3-2 A conceptual HSRC-OQPSK transceiver architecture.











3.2 HSRC-OQPSK Transmitter Architecture

Figure 3-3 shows the simplified HSRC-OQPSK transmitter architecture which is basically

the same as the conventional OQPSK modulation system architecture. The received data are

separated into the I and Q channels with 1 bit-time offset by a serial-to-parallel logic which is

comprised of two double-edge-triggered (DET) F/Fs, as shown in Figure 3-3. The separated data

are mixed with the quadrature HSRC signals of each channel and then combined by wiring


outputs of the I/Q mixers for generating the modulated signal, as shown in Fig. 2. For the bit

error rate (BER) test purposes, the HSRC signal is generated by an inj ection-locked LC voltage

controlled oscillator (VCO) whose inj section clock is also used in the clock of the external 2: 1

multiplexer (serializer) of the receiver, which will be discussed in Chapter 4.



I Channel
DET F/F -
Delay te
DaaSelal to tPa Hlel Out
Delay Injection-Locked

-DET F/F
Q Channel
Injection Clock


Figure 3-3 A HSRC-OQPSK transmitter architecture.


In this transmitter architecture, the phase synchronization of the clock and data is crucial to

produce an undistorted modulation signal. To maximize the modulated signal spectrum

bandwidth efficiency, the data should be synchronized with the carrier signal of each channel.

Synchronization mismatch caused from the clock to data output delay of the DET F/F should be

cancelled out by inserting a delay component between the VCO outputs and the mixer inputs, as

shown in Figure 3-4(a). Most of the circuits in this transmitter design have been implemented

with current mode logic (CML) circuits which are discussed in section 3.2.1 in more detail. CML









circuits offer low delay variation due to its supply independent low-swing voltage characteristic

[22]. From the simulation results, the delay variation is less than 10% of the various supply

voltages and processes. Synchronized delay lines or RC delay circuits could be reasonable

solutions, as shown in Figure 3-4(a). However, a delay line for several tens of pico-seconds is a

long line to be integrated and makes severe signal attenuation. Rev. 1 transmitter implemented

TSMC 0.18Cpm CMOS technology uses a RC delay circuit for the synchronization. However,

delay mismatch might occur because the flip-flop delay is not fixed over the various voltage,

temperature, and process conditions during the operation. In general, a buffer as a delay unit can

be an effective solution for the compensation of the delay mismatch problem [6]. Rev. 2

transmitter using UMC 0.18Cpm CMOS technology employs a buffer as a delay unit. Since a

delay of the DET F/F is mainly determined by a MUX, a matching delay buffer can be

implemented by inserting the same MUX to the signal path, as shown in Figure 3-4(b). The

MUX input ports are tied together and the selection port is logically fixed to select one of the two

inputs. Consequently, equal delays can be inserted in the signal paths.

Delayed
Data

I/Q DataFF




Delay

Clock
(Sinusoidal)

(a)

Figure 3-4 A structure of the DET F/F and data and clock synchronization by inserting (a) delay
unit (b) a MUX as a delay unit.









DET F/F


Figure 3-4 (continued).

3.2 Circuit Implementation

3.2.1 Current-mode-logic (CML) Circuit

A fully differential CML type circuit is widely used for the lower signal voltage and

high-speed digital system. As discussed and analyzed in [22], the CML logic has several

advantages over conventional digital logic. The logic has supply voltage independent output

swing. The differential pair with low input and output voltage swing offers high-speed operation.

Figure 3-5 shows a CML buffer circuit and its characteristic of output voltage versus input

voltage. The detailed analysis of the basic differential pair with resistive loads is presented in

[23]. The maximum output voltage swing is determined by tail current Iss and load resistance

RD, which varies VDD to VDD-RDISS as the differential input varies -oo to oo, as shown in Figure 3-

4. The NMOS logic parts are pulled up with load resistors.

The minimum and maximum input common mode level which allows Ml, M2 to stay in

the saturation region is analyzed in (3-1) [23].



















V,, I Vln2








(a)



VDD





VDD-RDl SSRDS


Vni1 Vln2


(b)

Figure 3-5 A fully differential (a) CML buffer and (b) differential input voltage versus output
voltages.



VGS1 + (VGS3+ VGS3 n~V,CM <: min VDD- RDVT Ip, VDD (3-1)



We have Voutl=VDD-RDID1 and Vout2=VDD-RDID2 and Voutl-Vout2=RD 1D2-1D1). Since the virtual

ground node, P, is equal to YEnl-VGS1 and yn2 VGS2, we get equation (3-2).

ynl yEn2 = VGS1 VGS2 (3 -2)









The relationship between VGS and ID is represented as (3-3) for a square-law device, where

pn, is the mobility of the NMOS device, Cox is the gate oxide capacitance, Wis the device width,

and L is the device length.


IVS-VT (3-3)
2 L

Using (3-3), (3-2) can be represented as (3-4).

2I, 2I,
ni -n2 D1WD2W(3 -4)

L L

Squaring two sides of (3-4) with the constraints of k; + o2 = SS, we get (3-5).

n 22 W Iss 2 );T (3-5)



Squaring the two sides again and then, we finally get the equation which represents the

relationship between the output current difference, (ID1 Io2), and the input voltage difference,

(yEnl yEn2), given in (3-6).

1 W 4I
IID D2Z -n o 1 n s 1 n (3 -6)
2 L W


By differentiating the two sides of (3-6), transconductance, Gm, is obtained as (3-7) where Ayn=



4I,
ahD 1 W p,C, W/IL (3-7)
G= ==-,C~
a BAR 2 L 4I, _y
pU,Car W/L '










Equation (3-7) implies that G,, drops to zero for Al',,, = J2Iss/ ,CoxW L) What if AT ,

exceeds the value which makes G,, to be zero? In this case, one transistor drives the total tail

current, Iss, input because the other transistor is approaching the turn-off mode. Thus, 101 = SS

and Al ,,l = VGS1 lTm where Al,,, = J2Iss/ AW,i WL and M2 is turned off for All,, > Al',, .

Figure 3-6 shows the relationship between the lD and AT ,, and the characteristic of G,,.

Gm
ID2 ID1





-avni +avini avin -avni +avln avn,



(a) (b)

Figure 3-6 Characteristics of a differential pairs versus differential input voltage (a) drain
currents (b) transconductance [19].


As analyzed so far, the differential pair shown in Figure 3-4(a) can be used for a small

signal amplifier whose maximum differential input voltage is AT ,,3. Within AT ,,2, the differential

amplifier could have a high small gain which is dependant on RD and Iss. In case of using it as a

digital logic which is called CML, it is better to guarantee AT ;, > AT ,,; for the maximum signal

output. Typically, the value ofnY ,,; does not exceed several-hundred mV for the high-speed

operation. Therefore, the differential CML logic uses a smaller input signal than a conventional

logic. Since the differential structure cancels the even mode harmonic terms, it is obvious that

the differential CML buffer is more linear than conventional CMOS logic and not easily affected

by common mode noise, which becomes more important in the low-voltage systems. The

differential structure gives us a one-stage buffer while the conventional CMOS needs a two-










stage, greatly reducing the delay of the buffer. Moreover, the characteristics of the CML logic

are strongly related to the tail current Iss and use a smaller logic signal. Delay variation due to

voltage, temperature, and process could be very small compared to conventional CMOS logic.

3.2.2 CML Double-Edge Triggered D flip-flop

A CML is widely used in high-speed digital logic because its low-swing voltage enables

high-speed operation [22], [24]. For this reason, most of the circuits used in this transceiver

design are CML circuits.

A CML DET F/F consists of a CML latch and a CML-style analog MUX, as shown in

Figure 3-7(a). The basic structure of the CML DET F/F is the same as a conventional one. Two

latches are selected by an analog multiplexer with a clock signal, shown in Figure 3-5(c). Due to

its high-speed and low delay variation characteristics, the CML latch offers good system

performance. Input transistors sense and track the input data differentially and cross-coupled

transistors store that data [24]. The clock signal selects tracking modes and storing modes. The

input transistors are tracking the input signal when the clock is high and cross-coupled transistors

are storing the input data when the clock signal is low.





R, (R Ro, RoT
Vout- Vout+VotVu+



V+Vinl+- r ~ ~ _Vin2-
V,._ Vlni-- Vin2+
CLL- sel+ I sel-





(a) (b)

Figure 3-7 CML Circuits (a) D-latch (b) analog multiplexer (c) double-edge triggered flip-flop.






















Figure 3-7 (continued).

The MUX also can be implemented with CML style digital logic which offers a more

flexible interface with CML latches than a conventional full-swing high-speed logic as well as

high-speed operation. The clock signal of the MUX selects one of the latches which stores the

previous data, so that the DET F/F can transfer the data when both the rising-edge and the

falling-edge clock signals occur.

3.2.3 Resistive Load Gilbert Mixer

One maj or difference between the conventional serial link transmitter and the HSRC-

OQPSK transmitter is mixing the data with the carrier signal using an analog mixer shown in

Figure 3-3. I and Q channel mixers generate an analog signal instead of a digital signal like NRZ.

Since the data input encompasses wide-band signals up to several GHz, a wide band mixer

should be used in this system. A resistive load Gilbert mixer has been chosen for this system

because it has wide bandwidth operation. It offers a direct output-to-input interface without any

voltage level shifting because it has basically the same structure as a CML circuit. Moreover, I

and Q channel signal combining can be obtained by connecting the outputs of the mixer in the

channels, which is discussed in section 3.2.2.5. The load resistor, RD USes the value of 2.5KGZ for

both Rev. I and Rev.2 transmitter. Figure 3-8 shows a resistive load Gilbert mixer.





















Vin2-)
Vinl+


Figure 3-8 A resistive load Gilbert mixer.


3.2.4 Quadrature Phase Clock Generator

Quadrature-phase carrier signals whose frequency is half-symbol-rate are needed for the

modulation. This can be simply implemented by using a two stage differential ring oscillator as

shown in Figure 3-9(b). To control the delay of each stage to varying the clock frequency, there

are two ways of controlling the propagation delay. One is the current starved approach and the

other is the shunt capacitive approach [25]. Figure 3-8 shows the current-starved and the shunt

capacitive inverter. In the current-starved inverter, Vctl controls the resistance of M4 through

current mirroring. This variable resistance controls the charging and discharging timing. In the

shunt capacitor inverter, control voltage, Vctl, adjust the resistance of M3 which is connected to

the output of the inverter. The other output of M3 is connected to a load capacitor. Therefore, the

shunt resistance of M3 controls the effective load capacitance seen by the output node of the

inverter. Decreasing the resistance of M3, the effective load capacitance seen by the output node

becomes large, producing more delay. From [25], the shunt capacitance topology has better










linear and noise rej section characteristics than the current-starved topology. However, the shunt

capacitance topology occupies a larger area due to the lumped capacitor.


M1

M2 M
Vin Vout VnVu
M3 M2

Vctl M4 Vctl M



(a) (b)

Figure 3-9 Two different delay control circuit (a) a current-starved inverter (b) a shunt capacitive
mnverter.


Figure 3-10 shows fully differential a shunt capacitive type inverter and two stage ring

oscillator. It is common that the fully differential circuit has better power supply insensitivity.

Each differential inverter has cross-coupled PMOS load and shunt capacitor with a control

NMOS. The phase difference of this adj acent node is 900.


It is known that LC oscillators allow large output swing at higher frequency with lower

voltage and make less phase noise than ring oscillators described in this section do [6]. For these

reasons an LC VCO, especially, an injection-locked quadrature-phase LC QVCO has been

chosen in this work. For the bit-error-rate (BER) test, the HSRC-OQPSK receiver needs an

external 2:1 mux for serializing I and Q channel data, which will be discussed in detail in

Chapter 4. To synchronize both the transmitter and the receiver outputs for the BER test, the

inj ected clock signal can also be used as an external reference clock. Moreover, the inj section

locked clock signal also helps to overcome failure in locking the receiver' s CDR loop that comes









from the frequency mismatch between the transmitter and the receiver due to the design variation

(e.g., process variation).


(b)

Figure 3-10 A fully differential (a) shunt capacitor inverter with cross-coupled PMOS active load
and (b) two-stage ring oscillator.


An injection-locked LC divider is introduced as a high frequency divider for the phase-

locked loop or low-power quadrature LO generation [26]. An external 5GHz clock is inj ected

into the VCO for generating 2.5GHz quadrature clock signals by which data modulation

performed. Figure 3-8 shows the structure of an inj ection-locked quadrature phase VCO [26].

The Q of the inductor for the LC tanks is approximately 8 and its value is 3.8nH. The varactor

value is 677fF with a fixed MIM capacitor of 329fF which offers approximately 20% tuning










range with a simulated 2mA tail current. The outputs of each stage are followed by a voltage

follower buffer not shown in Figure 3-11.







Vlout+ Y Vlout- VC~out+ rI VCout-



Vent


a+ Vln] -


Figure 3-11 Injection-locked LC QVCO.


3.2.5 I/Q Channel Signal Combining

The basic architecture of the HSRC-OQPSK transmitter follows that of a QPSK

modulator. Therefore, both I and Q channel signals must be combined together to generate the

HSRC-OQPSK signal. Since the mixer is operated in current mode, a combined signal of the I

and Q channels can easily be implemented by wiring both outputs of the I/Q channel mixers, as

shown in Figure 3-12. This makes the transmitter structure simple to implement.

3.2.6 Output Buffer

An output buffer of Rev. 1 transmitter has been designed with an open-drain structure as

shown in Figure 3-13. The output buffer has a differential three-stage cascaded structure

enabling the output buffer to have enough current to drive the 5002 load. The last-stage of the

open drain buffer is pulled up with a 5002 external resistor for the measurement. The resistor

values of each stage, R1, R2 are 55002, 14002, respectively which are implemented with on-chip

poly resistors. The DC bias currents, II, I2, IS, of the buffer are 1.5mA, 6mA, 15mA

respectively.





























Figure 3-12 Combining I and Q channel signal by direct connecting outputs.




R Ri R2 R2 Vu






1 \i 2 V 3


Figure 3-13 Three stage output buffer with open drain output stage.


The high impedance output of the output buffer used in Rev. 1 transmitter may cause the

inter-symb ol-interference (ISI) due to the mi matches [6], [27]. In order to minimize the

mismatch between the near-end (transmitter) and the far-end (receiver) and improve the signal

quality, an on-chip resistor of 6002 is used in the Rev. 2 transmitter. Figure 3-10 shows the

differential output buffer with an on-chip terminated resistor. A drawback of the double

termination is unavoidable increasing power consumption. It would double the power dissipation

in order to deliver the same voltage swing at the receiver end because the buffer needs twice the

tail current compared to the open-drain structure.










For the HSRC-OQPSK signal, linear amplification (without limiting output with limiting

amplifier [28]) is needed for generating the modulated signal since the modulated signal should

be kept undistorted. Therefore, a buffer is designed with the constraints of limited voltage gain

and maximum current gain. The resistor values of each stage, R1, R2, and R3 are 55002, 14002,

and 6002, respectively which is implemented with on-chip poly resistors. The DC bias currents,

II, I2, IS, of the buffer are 1.5mA, 6mA, 15mA respectively. The DC coupled output signal is

directly interfaced with the inputs with the pull-up of the receiver which enables double

termination. The architecture of the transceiver and detail test setup is discussed in Chapter 4.


Channel


(b)

Figure 3-14 Output buffer (a) differential three-stage output buffer (b) doubly terminated
structure.









3.3 Chip Design


3.3.1 Rev. 1 Transmitter

An integrated HSRC-OQPSK transmitter (Rev. 1) was designed and fabricated using

TSMC 0. 18um CMOS technology. The chip includes a serial-to-parallel logic, an inj ection-

locked LC VCO, mixers, and output buffers. Total chip size is 2000Cpm X 2000Cpm which

includes a transmitter and a receiver. The transmitter core without pads occupies 598Cpm X

575Cpm. Figure 3-15 shows the entire HSRC-OQPSK transceiver chip. The transmitter is

located at the lower right corner of the chip. The design includes a transmitter which modulates

the binary signal into HSRC-OQPSK signal. The transmitter consists of DET F/Fs, mixers, an

inj ection-locked VCO, and output buffers.























Figure 3-15 HSRC-OQPSK transceiver chip using TSMC 0.18Cpm CMOS technology.


The time domain simulation of the Rev. 1 transmitter is performed using Cadence Spectre.

For the transmitter simulation, a random bit stream in the Cadence adhl library is used for

generating 10Gbps random data.

























T im e (n s)


(a)


-10

-20

-30

-40

-50

-60

-70

-80

-90

-100


- Simulation
----- Theoretical


Frequency (GHz)


(b)

Figure 3-16 HSRC-OQPSK modulation signal (a) time domain waveforms (b) signal spectrum.


A 5GHz reference clock is inj ected into the transmitter for locking the VCO. The


generated 10Gbps serial data fed into the transmitter are separated into I and Q channel data. The

clock frequency is half-symbol-rate of the channel data, therefore, a double-edge triggered flip-


flop (DETFF) is used as a serial-to-parallel logic for each channel. The simulated time domain











waveforms and their spectrum without an external load are shown in Figure 3-16. The

spectrum's first generated signal null is approximately 6.7GHz which is a little bit lower than

theoretical value of 7.5GHz while the difference between the main lobe and the second lobe is

less than 20dB which is higher than the theoretical value of 23dB as shown in Figure 3-16(b).

3.3.2 Rev. 2 Transmitter

Rev. 2 transmitter has been designed and fabricated in UMC 0. 18um CMOS technology.

The chip occupies 1130Cpm X 1240Cpm. Figure 3-11 shows a simulation structure for the

transmitter. As discussed earlier, the design includes a transmitter which modulates the binary

signal into the HSRC-OQPSK signal. The transmitter consists of flip-flops, mixers, an inj ection-

locked VCO, and output buffers.


vboc vbo vdd gnd Osc- Osc


vdd
vddd


gnd
g nd ..

i i IlOut-
ckin


Out+
ckin-R ~

gnd
gnd

vdd
vdd



vblL vbvcd vcnt Ibmod gnd Dinl Din-




Figure 3-17 Transmitter die photo implemented by UMC 0.18Cpm CMOS technology.










The power and ground rings made by metal 5 are placed around the chip. To protect

circuits, the electrostatic discharges (ESD) circuits implemented by MOS devices are attached to

the DC bias lines. Octagon shape pads are used for the high speed signal. Pads for output signals

depicted as "Out+" and "Out-' are placed as close to the modulator logic as possible.

The architecture of the inj ection-locked LC VCO for Rev. 2 transmitter also has the same

architecture as shown in Figure 3-11i. The Q of the inductor for the LC tanks is approximately 8

and its value is 3.8nH. The varactor value is 677fF with a fixed metal-insulator-metal (MIM)

capacitor of 329fF which offers approximately 20% tuning range with a simulated 2mA tail

current.

Similarly, the simulation has performed for the Rev.2 transmitter implemented by UMC

0.18Cpm CMOS technology. The conversion gain and input referred 1dB compression point of

the mixer are simulated using the Cadence Spectre [29] with the port resistance of 2.5KG2

because a high impedance logic interface, rather than a 5002, is employed in the digital system.

Up-conversion gain and 1dB gain compression are simulated as shown in Figure 3-7.

Conversion gain is less than -1dB if the LO power is larger than -20dBm which roughly

corresponds to a single-ended peak-peak voltage amplitude of 230mV in a 2.5KGZ system. Figure

3-18(b) shows the conversion gain as the input RF frequency increases. For the 4GHz input, the

conversion gain is -1.03dB. The input referred 1dB compression is -23.08dBm with the port

resistance of 2.5KG2, LO frequency of 2.5GHz, RF input frequency of 3GHz, and output

frequency of 5.5GHz.

For the transmitter simulation, a random bit stream in the Cadence adhl library is used for

generating 10Gbps random data. A 5GHz reference clock is inj ected into the transmitter for

locking the frequency of VCO. The generated 10Gbps serial data fed into the transmitter are












separated into I and Q channel data. The clock frequency is half-symbol-rate of the channel data,


therefore, a double-edge triggered flip-flop (DETFF) is used as a serial-to-parallel logic for each


channel .


-0 3-
-04-

S-06-
m
C~-0 7
E -081
os

S-09-
-10-
-11-


LO Powe~r=-10dBm (2 5GHz)
(Port Resistance= 2 5Kohm)


RF lnput Frequ ncy=3GHz
Port Resistance=2 5Kohm


LO Power (dBm)
(a)


1 0 1 5 2 0 2 5 3 0 35 4 0
RF Input Freqeuncy (GHz)
(b)


Input Referred 1d B Compressi


Port Resistance=2.5Kohm

Output Freqeuncy=5.5GHz
LO Freqeuncy=2.5GHz


-50 -40 -30 -20 -10
Input Power (dBm)
(c)

Figure 3-18 Linearity simulation of resistive Gilbert mixer using UMC 0. 18Cpm CMOS
technology (a) conversion gain vs. LO power, (b) conversion gain vs. RF input
frequency, (c) input referred 1dB compression.



The time domain simulation of the HRSC-OQPSK transmitter is performed using the


Cadence Spectre. The simulated time domain waveforms and their spectrum without an external


load and channel are shown in Figure 3-19. The spectrum's first generated signal null is 7.5GHz









while the first null point of 10Gbps NRZ data spectrum is 10GHz. The signal spectrum

bandwidth is reduced and the side lobes of the spectrum are greatly suppressed as well. The

difference between the main-lobe and the second-lobe of the spectrum is more than 20dB, which

agrees with the theoretical analysis of the spectrum of HSRC-OQPSK.


Tim e (ns)
(a)


- Simulation
--- Theoretical


10
Frequency (GHz)
(b)


Figure 3-19 HSRC-OQPSK modulation signal (a) time domain waveforms (b) signal spectrum.


Figure 3-20 shows that the time domain waveforms of the dc-free signal using HSRC-

OQPSK transmitter. The spectrum's first generated signal null is 5GHz which agrees with the


-20

-30 .

-40ji











value of the theoretical spectrum. DC components of the signal have been reduced more than

theoretical values because the I and the Q channel data have been correlated every other bit due

to the fact that the 2.5Gbps data are being inj ected to I and Q channel simultaneously with just

half bit time data offset by serial-to-parallel logic. However, it is quite well-matched with

theoretical values to be considered 5Gbps signal effectively. The difference between the main

lobe and the second lobe is approximately 20dB while the difference is 13dB for the NRZ, which


agrees well with the analytical form of the dc-free spectrum derived as (2-21).


51 0
Tim e (ns)
(a)


-20

-30


E -40




S-60

-70

-80

-a


Simulation
Theoretical


0D 5 10 15 20
Frequency (GHz)
(b)

Figure 3-20 Simulated dc-free signaling (a) time domain waveforms (b) signal spectrum










3.4 Measurement


3.4.1 Rev.1 transmitter

Figure 3-12 shows the simplified evaluation board structure and an actual photograph. A

chip has attached to the pad on the PCB board using conductive epoxy as shown in Figure 3-20.

The pad is connected to the backside ground plane through via hole. And the signals of the chip

are connected directly to the PCB trace via wire-bond. All the ground pads are down bonded to

the pad. Thermal epoxy covers the chip for the purpose of protection. Rev. 1 transmitter's output

buffer structure is open drain, hence, external chip resistors of 6202 are attached to the output

signal lines, as shown in Figure 1-13. 11002 chip resistors are attached to differential signal lines

of data input and inj section clock inputs.

Thermal px
Signal wire bondingronD






Ground Plane
(a)


















(b)

Figure 3-20 Test board for the Rev. 1 HSRC-OQPSK transmitter (transceiver) implemented by
TSMC 0.18Cpm CMOS technology.










From the measurement results, the measured frequency tuning range of the VCO is

2.28GHz ~ 2.58GHz, which is approximately 12.3% from the center frequency 2.43GHz. The

center frequency of the VCO has shifted lower from the simulated center frequency

approximately 2.8%, which is caused from the layout parasitics such as routing metals, which are

not considered in the simulation phase. Figure 3-21 shows the QVCO's signal spectrums for both

free-running and inj ection-locked states. Figure 3-21(a) shows the spectrum of the VCO in the

free running state. The center frequency is 2.5GHz with 5MHz span. Figure 1-14(b) shows the

spectrum of the VCO when the 5GHz clock is inj ected for the inj ection-locking of the QVCO.

The inj section clock signal is generated from the Agilent E8254A signal generator. The carrier

power is measured approximately -5dBm with single-ended output. However, the carrier power

estimated -3dBm if the PCB trace and cable loss are taken into account. The characteristic of the

noise floor in the inj ection-locked mode is much lower than that in the free-running mode.

Ref 0 dBrn Atten 18 dB


18 I;



47.0 kHz





Sete FI.500f)A~ 00 GH Span5 M
R W1 47 E.H VB 7EHI Sep2.6is(61p





TS C0.8mCOtehooy(enter freqenc of 2.Gzwih5Hz span and~



47 KHz RBW) (a) free-running mode (b) inj ection-locked mode (c) comparison of
the phase noises between free-running and inj ection-locked modes.






















































100K
Frequency Offset (Hz)


Figure 3-21 (continued)

The spectrums show that the noise floor characteristic has been improved more than -

30dB. The phase noise has been measured by the Agilent E4448A spectrum analyzer that offers

the phase noise measurement mode. Figure 3-21(c) shows the phase noise comparison of the two


(
| |


RBW
47.0 kHz


2
C


Ref 0 dBm
LoNorm r


10
dB/


Atten 10 dB


r 2.500 000 GHz
W 47 kHz


Lg~v
W1 S;
S3 Fl

(f):



Center
Res B


UBW 47 kHz

(b)


Span 5 MHz
Sweea 2.76 ms (601 ats)


-40


-60


& -80


~-100
Z

~-120


-140


-160O










states which are the free-running and the inj ection-locked state. Measured results show that the

phase noise of free-running and injection-locked QVCO signal is -1 11dBc and -136dBc at 1MHz

frequency offset, respectively.

Agilent 86100B wideband oscilloscope has been used to get the eye-diagram of the signal.

The simplified test setup for 2.5Gbps and 10Gbps BER test are shown in Figure 3-22(a), (b),

respectively. Since 2.5Gbps random input is inj ected into both I and Q channel simultaneously,

the transmitted signal can be characterized as a 5Gbps signal equivalently even though the data

of I and Q channel are correlated to every other bit.


I Wideband
Oscilloscope


(b)

Figure 3-22 Simplified test setups for (a) 2.5Gbps (5Gbps equivalent) (b) 10Gbps random input
for the transmitter.









For the 2.5Gbps measurement, 5GHz clock signal from the signal generator has been

inj ected to the transmitter for the VCO locking and a half frequency signal generated from the

VCO of the chip is fed into the Agilent 4903A BERT for the external clock. Then BERT

generated the 2.5Gbps synchronized to the clock inside the chip. 10Gbps test setup is more

simple because the 1/2 sub-rate clock from the BERT can be used as an inj section clock of the

transmitter. Since the sub clock output of the BERT has the fixed phase with the data output, a

phase shifter between the sub clock signal output of the BERT and the clock input of the

transmitter for the timing offset between the input data and the clock.

The eye-diagram of the transmitter signal is shown in Figure 3-23. However, the

measurement could not get the proper eye-opening of the transmitted signal. Despite the

reasonable simulation results, the transmitted signal suffers from huge jitter components and two

eye-openings depicted in Figure 3-23 have different shapes even in 2.5Gbps data-rate due to the

delay mismatch between the data and the clock. The measured eye-diagram of the modulated

signal is shown in Figure 3-23. The delay mismatch is mainly caused from a delay unit

composed by a RC. The RC delay unit shown in Figure 3-4(a) does not compensate the delay

mismatch effectively because its characteristic varies much with the temperature and the voltage

and the process conditions. ISI noise due to the reflection of the high impedance node of open

drain output buffer could be another reason for this result. For the 10Gbps transmitted signal,

jitter components are introduced to the modulated signal, something that is not shown in this

dissertation. The eye-diagram of the HSRC-OQPSK signal is different from that of the NRZ

signal. As analyzed in Chapter 2, the low-energy symbol signal that practically determines the

BER performance also affects the eye-opening size directly.










Two eye-openings in Figure 3-23 are not identical to each other because the delay

mismatch between the clock and the data signals. A RC delay unit which is used in Rev. 1

transmitter offers a fixed delay. The limitation of the delay matching comes from the variation of

the resistive value due to the process conditions or the delay variations of the F/F over various

voltage, temperature, and process conditions.









45mV/d iv








50ps/d~iv :-



Figure 3-23 Eye-diagram of the HSRC-OQPSK transmitted signal implemented by TSMC
0.18Cpm CMOS technology.


3.4.2 Rev. 2 transmitter

Rev. 2 transmitter has been designed and fabricated separately with the receiver. Figure 3-

14 shows a die photo of the transmitter test board. The chip is attached to the chip pad which is

also used down bond ground. The signals are connected to the PCB signal traces directly via

wire-bond. The down bonded grounds are connected to the backside ground plane. Thermal

epoxy covers the chip for the protection purpose. Surface mount type capacitor of

approximately 100CLF as bypass capacitors are attached between the power and the ground as









shown in Figure 3-24. Data and clock input signals are terminated with the external 5002

resistors. The board has oscillator signal outputs for the purpose of monitoring as well as

modulated signal outputs.
















Figure 3-24 Test board for the Rev. 2 transmitter implemented by UMC 0.18Cpm CMOS
technology.


Figure 3-25 shows signal spectrum of the Rev. 2 transmitter' s VCO. The measured tuning

range of the VCO is approximately 2. 18GHz ~ 2.44GHz, which is representing the tuning range

of 12% frequency. The center frequency of the VCO has been shifted to approximately 10%

lower frequency than simulation. It is caused from the parasitics such as a routing metal

capacitance and resistors during the layout, which are not considered in the simulation phase.

Post-layout simulation with equivalent circuits modeled layout parasitics would improve the

mismatch problem. Figure 3-25(a), (b) show the frequency spectrum of the VCO both free-

running and injection-locked states, respectively. As is the case of Rev. 1, we can investigate the

noise floor of the spectrum of the inj ection-locked state that has been lowered than that of the

free-running state. The measured phase noise of the VCO is shown in Figure 3-25(c). To

measure the phase noise of the VCO, Agilent E4448A spectrum analyzer is used. The phase

noise performance of the VCO in the free-running state is approximately -1 10dBc/Hz at 1MHz





















0 dBm Atten 10 dB -1.29 dBm







-Mrer
2.244500000 GHz
-1.29 dBm





C. I~n m uc, ram


Mkrl 2.250 0 GHz
dBm Atten 10 dB 1.24 dBm


offset, while the -140dBc/Hz at 1MHz offset when the VCO is locked with the inj section clock.


The phase noise performance of the VCO of the Rev. 2's transmitter is almost the same as that of


Rev.1i's VCO implemented using TSMC 0. 18Cpm CMOS technology.


Mkrl 2.244 5 GHz


Ref ~
Norm
Log
10
dB/






LAny

W1 S
S3 F


C


en er z
Res BW 910 kHz


p~ani zu
Sweep 1 ms (601 pts)


UBW 910 kHz


Ref 0 r
Norm
Log
10
dB/


Center 2.250 0 GHz
Res BW 910 kHz


Span 1 0 MHz
Sweep 1 ms (601 pts)


UBW 910 kHz


Figure 3-25 Measured spectrums and phase noise of the transmitter' s QVCO implemented by
UJMC 0.18Cpm CMOS technology (center frequency of 2.25GHz with 100MHz span
and 910 KHz RBW) (a) free-running mode (b) inj ection-locked mode (c) comparison
of the phase noises between the free-running and the inj ection-locked modes.


LsAv


S3 F

Elf):
FTun
Swp


















o -80 -r~yr~H1~,tr


S-100 -






-160

-160LK 10K1
Offset Frequency (Hz)
(c)

Figure 3-25 (continued).

Figure 3-26 shows the measured eye-diagram of the transmitted signal where the 2.43Gbps

231-1 pSeudo random bit streams (PRB S) are inj ected into the transmitter that generates 4.86Gbps

transmitted signal equivalently. From the measurement results, the clock and data

synchronization using a buffer insertion depicted in Figure 3-4 can effectively be working to

generate the HSRC-OQPSK modulated signal. Compared to Rev. 1 transmitter using a RC delay

unit for compensating delay mismatch, a clear eye-opening has been obtained. The buffer

insertion as a delay unit discussed in section 3.2.1 can effectively make good compensation of

the delay mismatch while the RC delay unit used in Rev.1i's transmitter did not compensate the

delay mismatch effectively.

SMA connectors are used to connect the channels in the test board shown in Figure 3-24.

The characteristic impedance of 5002 channel 6.2mil FR-4 PCB board and tangential loss is

approximately 0.023. Since the PCB channel has a low-pass characteristic as discussed in










Chapter 1, the detected signal power at the receiver end drops as the channel length increases.

Therefore, the eye-opening is getting smaller as the channel increases and eye-opening would be

closed after tracing a long channel.

Figure 3-26 shows the measured channel characteristics used in the measurement. Three

different lengths of PCB trace and one SATA of 19" length cable are used to compare the

performances. The measured results show that 20" trace has a loss of 13dB at 6GHz while the 5"

channel is approximately 3dB.


10





-10





-30 -
PCB-5"
PCB-10O"
-40 -
...PCB-20"
8ATA-1 9"

-50
0 2 4 6 8 10 12
Frequency (GHz)


Figure 3-26 Characteristics of channels used in the measurement.


The measured peak-to-peak small eye-opening of the transmitted signal after tracing 2"

PCB trace with a SMA cable is about 300mV without equalization of the signal at the trace end.

Peak-to-peak eye-opening of the flat signal which has the largest symbol energy (Eqf) is

approximately 400mV. The eye-opening after tracing the 10" channel is reduced to 150mV. And

less than 80mV eye-opening has been obtained after 20" trace. Another serial link channel,









serial-ATA (SATA) cable, has been used for this experiment to evaluate the performance of the

transmitter. A 19" SATA cable with 2" PCB trace to connected transmitter is used to obtain the

eye-diagram. Figure 3-16(d) shows the eye-diagram after 19" SATA cable trace. More balanced

eye-diagram has been obtained compared to PCB trace because the differential signals are

strongly coupled than PCB channels used in the measurement.


(b)

Figure 3-27 Eye-diagram of HSRC-OQPSK transmitted signal implemented by UMC 0.18Cpm
CMOS technology after (a) 2" PCB trace, (b) 5" PCB trace, (c) 10" PCB trace, (d)
20" PCB trace, (e) 19" SATA cable, in response to 4.86Gbps (both I and Q channel
input with 2.43 Gbps pseudo random bit stream (PRB S) sequence of 23'1)



























































Figure 3-27 (continued).










Figure 3-28 shows spectrum of the 4.86Gbps dc-free signal. High frequency components

of the signal are suppressed due to the signal loss at the test board and the limitation of the

operating frequency of the circuit. However, the nulls at dc and the other frequency of the

spectrum are quite well matched with the theoretical values.

-10
SMeasurement
-20C ---- Theoretical

-30 1nlllll IIIIIIII '1.












-100


0 5 10 15
Frequency (GHz)
Figure 3-28 Spectrum of 4.86Gbps dc-free signal.


Figure 3-29 shows the measured eye-diagram of the HSRC-OQPSK signal in response to

9.72Gbps PRBS sequence of 2 -1. The measured eye-diagram shows that the HSRC-OQPSK

signal generates the similar eye-diagram shape to that of the duobinary signal [30]. A major

difference of the signal eye-diagram between the HSRC-OQPSK and duobinary signals is that

HSRC-OQPSK has no decision references because it uses only a two-level decision while the

duobinary signal needs the two decision level to decide the logical value of the signal [9], [30-

31]. Therefore, it is better for the HSRC-OQPSK signal to open the side eye-diagram wide

enough depicted with a blue diamond shape (ideal eye-opening). Actually, the HSRC-OQPSK










signal can be obtained based on the duobinary decoding scheme assuming the high frequency

components of the signal are filtered out at the band-limited channel. However, every 3rd and 4th

bit data should be reversed to get the proper HSRC-OQPSK signal.


'liCc;
S
~t ~j
Lh
".~ trb~"~


~i


(b)

Figure 3-29 Eye-diagram of the HSRC-OQPSK transmitted signal with 9.72Gbps PRBS
sequence of (a) 2 -1 (ideal eye-opening is depicted with blue line), (b) 23'1.


As discussed in Chapter 2, the consecutive transition signal which has low signal energy

makes the diamond shape eye-diagram depicted with a blue line in Figure 3-29(a). The signals










suffer from severe attenuation of the signal energy as shown in Figure 3-30. The small eye-

opening is less than 60mV which is smaller than the simulation results which will affect the BER

performance of the transceiver. The BER performance will be discussed in Chapter 4. The

attenuation of the signal mainly comes from the limit of the circuit' s operating frequency. And

the delay mismatch also prevents enlarging the eye-opening of the signal. Broadband circuit

techniques such as a fr doubling of the output buffer are needed to increase the signal quality and

maximize the eye-opening. The spectrum shown in Figure 3-27(c) also represents the high

frequency attenuation of the signal and there are no side lobes of the signal above 10GHz which

are supposed to follow the theoretical spectrum corresponding to the red line. The performance

of the HSRC-OQPSK transceiver associated with the transmitter is discussed in Chapter 4.


-10
Measurement
-20 Theoretical

-30










-80

-90

-100
0 5 10 15 20
Frequency (GHz)
Figure 3-30 Signal spectrum in response to9.72Gbps PRBS sequence of 2 -1.









CHAPTER 4
HSRC-OQPSK RECEIVER DESIGN

4.1 Receiver Architecture

A conceptual HSRC-OQPSK receiver architecture which is based on that of a QPSK has

been depicted in Figure 3-2. Different from the conventional serial link receiver that uses a PAM

signal, the HSRC-OQPSK receiver uses a carrier signal which is quarter data-rate frequency for

the demodulation. Therefore, a quarter-rate CDR must be incorporated with the receiver. A

quarter-rate PD as a CDR for the conventional PAM signal has been introduced and

demonstrated [32]. The HSRC-OQPSK receiver (Rev. 1) designed with TSMC 0.18Cpm CMOS

technology uses the same PD architecture introduced in [32].

To improve the performance of the proposed HSRC-OQPSK receiver, a new CDR

architecture has been proposed for the Rev. 2 receiver and implemented using UMC 0.18Cpm

CMOS technology. The proposed CDR has been modified from a Costas loop which is often

used for the carrier recovery loop for the BPSK and QPSK signal. The details are discussed in

section 4.3.

4.2 HSRC-OQPSK Receiver (Rev. 1)

Figure 4-1 shows the HSRC-OQPSK receiver architecture with a quarter-rate CDR. The

input buffer amplifies the incoming signal followed by I and Q channel mixers. As described in

the conceptual receiver architecture, the receiver has I and Q channels. I and Q channel mixers

are demodulating the received signal using the quarter data-rate carrier signals recovered by a

CDR loop. DET F/Fs followed by I/Q mixers determine the retimed data of I and Q channels. To

recover the clock which is quarter data-rate, a conventional quarter-rate PD [32] has been

adopted for the Rev. 1 receiver. Originally, the quarter-rate PD has been proposed for the

40Gbps NRZ signal relaxing timing requirements and reducing the cost of fabrication [32].













Signal In


Figure 4-1 HSRC-QOPSK receiver (Rev. 1) architecture incorporated with quarter-rate PD.


Figure 4-2(a) shows the phase detector (PD) architecture employed in the Rev. 1 receiver.

The PD is introduced in [32]. F/Fs strobe the data by using multi-phase VCO signal and

determine the polarity of the phase error by using XOR gates. The outputs of two consecutive

XOR gates are connected to the differential V/I converters which determine the phase error.

Figure 4-2(b) shows the timing diagram of the PD.

I~n
in O@CKS1 an 12 pa, -

Din CK D-~-1 CIz C
a or ob a cK45
CK315
Os To LPF Qo a1' 2,


GK71 Dgrq 0 K


Din Oinb~ D, cirl---~

(a) (b)

Figure 4-2 Quarter-rate phase detector (a) architecture (b) waveforms (for 40Gbps NRZ) [32].


The Rev. 1 receiver has been fabricated with TSMC 0.18Cpm CMOS technology. The

simulated maximum current of the PD in the Rev. 1 receiver is approximately 200CLA.









In the measurement, however, the PD has failed to appraise the performance of the receiver

for the HSRC-OQPSK signal. There might be several reasons. First, the transmitter signal itself

was not good enough for the receiver due to the limited performance of the transmitter. Second,

the PD employed in the receiver is originally for the NRZ signal. The PD has the best

performance when the signal has a sharp transition like the NRZ signal and not like the HSRC-

OQPSK signal. Since the meta-stable behavior of the F/F will lead to the finite gain of the PD

[32], the HSRC-QOPSK signal having no discrete transition like NRZ would increase the meta-

stable behavior in F/Fs. Consequently, the PD gain might be decreased significantly.

4.3 HSRC-OQPSK Receiver (Rev. 2)

Figure 4-3 shows the proposed HSRC-OQPSK receiver structure. The receiver is based on

a Costas loop (often used as a carrier recovery loop of a conventional QPSK demodulator) [33-

34]. Two mixers separate the incoming modulated signal into the I and Q channel for the signal

demodulation. After passing through the mixer, the I/Q channel signals are fed into the DET F/Fs

clocked with quarter data-rate frequency carrier signals recovered by the CDR loop. The loop

also allows the retimed I/Q channel data. Generally, a carrier recovery loop as well as a Costas

loop has LPFs in order to get rid of the high frequency components in the I and Q channel path

and get the phase error to control the VCO of the receiver. Unlike a conventional carrier

recovery loop, the proposed CDR does not include LPFs. Since the carrier recovery of the

HSRC-OQPSK receiver is basically the same as the symbol synchronization of the QPSK

demodulation process, it is expected that the proposed CDR loop (algorithm) can be effectively

applied for the symbol synchronization loop of the QPSK demodulation as well. The detailed

analysis of the proposed receiver integrated with a CDR loop will be discussed.


















Signa I



DET FIF
Q II I I Q Data



-PP S/H



Figure 4-3 HSRC-OQPSK receiver architecture incorporated with a CDR.


4.3.1 Polarity-Type Costas Loop for Carrier Synchronization

A Costas loop is commonly used as a carrier recovery loop for the QPSK type modulation

signal. The Costas loop was first introduced in [35]. A couple of modified Costas loops have

been proposed and their performances analyzed in [33-34]. Other structures for the carrier

recovery loops for the QPSK signals are introduced and analyzed in [36-41].

Figure 4-4 shows a polarity-type Costas loop for the QPSK type signal proposed in [33].

The polarity-type Costas loop is a kind of hard-limited carrier recovery loop which is known to

have a better performance than that of the non-limited type carrier recovery loops in a higher

signal-to-noise ratio (SNR) situation [10], [34]. Input signals of the polarity-type Costas loop are

mixed with quadrature carriers generated from a quadrature VCO (QVCO) and separated into the

I and the Q channel by the mixers. The I/Q channel signals pass through low-pass filters (LPFs)

to get rid of the high-frequency components which have no significance for generating the

control signal. These signals are mixed again with the limited signals from the other channel, as

shown in Figure 4-4.














Signal Loo Fite







Figure 4-4 Polarity-type Costas loop for QPSK signal carrier recovery.


In QPSK modulation, the signal coming into the Costas loop can be defined as (4-1),

where S is the average received signal power, m;(t), mQ(t) are the data sequences of -!- of I/Q


channel, we is the carrier frequency and 8, is the phase of the signal.


s(t)= i[m,(t)- sin(mot +B)+m,(t)- cos(ot +B)1 (4-1)


The phase error signal controlling the VCO frequency is generated by subtracting these

two signals from each channel. Assume VCO signal has an amplitude of 1/JS and a frequency

of wc, then the low frequency output of the polity-type Costas loop can be represented using

trigonometric operations as (4-2), where 0= Oi-8o, 8o is the phase of the VCO signal [42].



e(t>= 1 m,(t)sin# +m,(t)cos~sgn~m,(t)cosa-m,(t)sina
2 (4-2)
[m,(t)cos(- m, (t)sin dsgn m, (t)sin #+ my t)cos E


Then the low frequency phase error can be rewritten as (4-3).










cos# -- # <-
4 4

e~) 4 4

ilj- cos# < #



4.3.2 A New Clock and Data Recovery (CDR) based on the Modified Costas Loop

Figure 4-5 shows the proposed CDR loop which is basically the same as the HSRC-

OQPSK receiver structure. Since the CDR offers retimed data similar to other CDRs do, it can be

used as a receiver. The proposed CDR loop for the HSRC-OQPSK modulation and its analysis

and simulation results are presented in this section.

Note that the HSRC-OQPSK modulation inherits the properties of the QPSK modulation

even though its carrier frequency is lower than the data-rate. Therefore, it is expected that the

polarity-type Costas loop shown in Figure 4-4, can be used as a clock (carrier) recovery loop for

the HSRC-OQPSK signal. However, there are a couple of limitations in implementing a CDR

loop and demodulating the HSRC-OQPSK signal. First, since the data-rate HSRC-OQPSK

signal is higher than its carrier frequency, LPFs in I/Q channels selecting low frequency

components cannot be used for the phase detector output in the Costas loop. Second, a coherent

demodulation of the QPSK signal with a matched filter consisting of an integrate/dump and a

decision circuit is very difficult to implement in the GHz range. Also, a bit-time delay between

the I and the Q channel data should be properly compensated for the phase error detection as

well as the demodulation. Consequently, the conventional Costas loop should be modified for the

CDR of HSRC-OQPSK signal. A new CDR loop for HSRC-OQPSK signal modified from the

Costas loop is proposed and shown in Figure 4-5.


















Signal~ III(L~~
Ca vco +

--DET FIF



-PP S/H
Os


Figure 4-5 A modified Costas loop for the HSRC-OQPSK signal clock and data recovery.


The modulated signals fed into the CDR are split into the I/Q channels and mixed with

quadrature carrier signal generated from QVCO. The LPFs shown in Figure 4-2 are removed and

the limiters are replaced by DET F/Fs. Sample/hold (S/H) circuits sampling both clock edges

hold the signal of each channel by 2 bit-time for the proper evaluation of the phase error. The

demodulated signals, I and Q, are sampled by sample/holds and DET F/Fs. The sampled signals,

Is and QF, QS, and IF, are mixed for the final evaluation of the phase error. The sampling time of

the I and Q channel are offset by 1 bit-time. Therefore, the CDR loop evaluates the phase error

every 1 bit-time. The details are analyzed and a behavioral model simulation will be presented.

4.3.2.1 Phase detector characteristics

The received HSRC-OQPSK signal can be represented as (4-4) [43], where Tb is a bit time

and 8, is an arbitrary phase of the incoming signal.



s(t)= mt-i +g+ mt-cs + (4-4)









For the QVCO signals of the CDR, they can be assumed as (4-5), where 8o is the initial phase of

the QVCO signals.



cI (t)= sin +0 ,t c ( o + 45



Then I/Q signals can be obtained as (4-6), (4-7) by multiplying two signals represented as (4-4),

(4-5) using trigonometric operations.






I(t) = Im(t-cs ++0-cs0-)
2p fn Tb ,".1 (4-6)








Since the samplings of S/Hs and F/Fs are taking place at the zero crossing points of carrier

signals defined in (4-5), one can obtain the sampling time of each channel by setting

c;(tQ)=cQ(t,)=0. Therefore, the sampling time for the I/Q channels are defined as (4-8).



tr = Tb 1 2 S to T 2 S (4-8)



Now, one can define the sampled signals using (4-8). The sampled signals, Is(t) and Qs(t) shown

in Figure 4-3, can be calculated as (4-9), (4-10) by substituting (4-8) into (4-6), (4-7)

respectively, where 0= Oi-8o.










Is (t> = m, (t, )- cos f m, (tz)- sin #

Qs~t = mi,(ty)- sin # + m,(ty )- cos #


(13)

(14)


Similarly, IF and QF Signals can be determined by limiting the sampled signals which are

obtained by taking sgn[Is(tz)], sgn[Qs(tQ)]. For these signals, the phase difference between the

received signal and the carrier signal determines the values oflF- and QF. Therefore, IF and QF are

represented as (4-11), (4-12), respectively.


37r i
4 4

--<<
4 4

-<~-
4 4

_ 4

4 4


(4-11)







(4-12)


The data sequences of m; and mQ should be specified for determining the phase error, e(t).

Figure 4-4 illustrates the early and late sampled I/Q channel data when the phase difference, 0, is

either positive or negative. When 0<0, the sampling time is earlier than the ideal sampling time

while the sampling time is later than the ideal sampling time when 0<0, as shown in Figure 4-6.

Consequently, data constraints related to the phase difference can be stated as (4-13).


(4-13)


m, (t )

IFti= I I I)

-m (tz)





m, to


m (tz) = mdt
m; (tz) = m/t









@<0
milli) millo)






m,(ti) mo(t,)

Figure 4-6 Early and late sampling time of I/Q data.


Now, the phase error e(t), represented as (4-14), can be estimated. The CDR loop evaluates

the phase error every bit-time because the Is(tz) and QF(tQ) or Qs(tQ) and IF(tz) are overlapped by

a bit time.


e(t)= Qs(t)IF(tr) Is(t)QF(tQ)


(4-14)


With the data constraints in (4-13), the phase error, e(t), is obtained as (4-15) if it is assumed that

the amplitude of the ml, mQ are unity.


1+ m, (t,)- mejt,)cos(1 mtr et i

(1+ m, (t,)- m, ty))sin ~


'i (1+ m,(t,)- m,(g))- cos


4

44


(4-15)


Still, the values of mQ(tz)-mQ(tQ) when 0<0 and m;(t)-m (tQ) when 0>0 cannot be fixed to

finalize e(t) because the random data sequences are uncorrelated. The values can be either -1 or 1

which is dependant on the data sequences. The undetermined value of -1 or 1 leads to two









possible results of e(t). The coefficients of each term of (4-15) will be zero or +2 when the value

is -1 or 1, respectively. Then, the averaged phase error can be rewritten as (4-16) with the

assumptions that I/Q channel data sequences occur equally likely with symbol time and the phase

error process is changing slowly over the large number of symbol periods. Consequently, the

averaged phase error is equivalent to that of the polarity-type Costas loop. Its plot is shown in

Figure 4-7.


4 4

4 4
-<<--
4 4


(4-16)


:14


:14 /2


Figure 4-7 Averaged phase detector characteristic of the proposed CDR loop.


The proposed CDR loop based on the polarity-type Costas loop can be characterized as a

linear phase detector, as shown in Figure 4-5. A linear phase detector (PD) generates an error

signal linearly proportional to phase error. The output of the PD goes to zero when the loop is

locked while a non-linear PD is pumping the charge even with the loop in a locked state. It is

known that a linear PD produces lower j itter compared to non-linear PD due to less charge pump


cos#

e~)a
cos#


-3;4/2


37c/4r Q









activities [44-45]. Therefore, the proposed CDR is expected to generate less clock jitter noise

compared to non-linear type PD. Moreover, the carrier frequency of the proposed CDR loop for

HSRC-OQPSK signal is quarter data-rate, hence, the loop is equivalent to quarter-rate CDR for

NRZ signal. As a result, the proposed CDR can relax the timing constraints of the receiver

system. In addition, the proposed CDR allows retimed I/Q channel data as shown in Figure 4-1,

similar to that of other CDRs [6]. In addition, although the proposed CDR has been developed

for the clock recovery of the serial link transceiver system, the concept can also be applied to the

symbol synchronization of the QPSK signal in wireless communications.

One drawback of the proposed CDR is that there are four stable locking points over the 2n

radian period, only one of which has proper phase information. A differential encoding in the

transmitter can resolve this four-fold phase ambiguity problem at the cost of 3dB reduced signal

power [10]. And, other methods for phase ambiguity resolution have been introduced in [46].

However, this four-fold ambiguity issue is for future work.

4.3.2.2 Loop analysis

The modified Costas loop can be represented by the equivalent model, as shown in Figure

4-8. The Ka is the gain of the combiner, K, is the VCO gain, and F(S) is the function of the loop

filter. Transient response of the loop cannot be characterized easily; however, the loop can be

modeled as a linear system with assumptions that the phase error, 0, changes slowly over a large

amount of the symbol period [40].

Assuming no noise is added in this loop, then the overall transfer function of the closed

loop is calculated as (4-17).


a, (s) K K,, F(s)
H(s)= (4-17)
8( s+K KF(s)


























VCO

Figure 4-8 Equivalent linear model of proposed CDR for HSRC-OQPSK.


Since the transfer function of the loop filter can affect the overall transfer function of the

system, the loop filter should be carefully chosen to stabilize the system. A lead/lag network is

widely used as a loop filter because it offers an increased open loop phase margin of the system

by inserting zero to the transfer function [6]. The transfer function can be rewritten by using the

parameters from circuit implementation. Ka=180CLA/V is obtained from the circuit simulation and

K,=120MHz/V, as shown in Figure 4-18. A lead/lag network with R,=7KGZ and C,=30pF is used

for the simulation purpose to reduce the simulation time and the required memory. With these

parameters, the closed loop gain of the system is represented as (22). The zero of the closed loop

of the transfer function is located at 1/RC,. In real design for the measurement, the closed loop

bandwidth of IMHz has been chosen which is examined in a later section.

KaK, RKCs +1)

H(s)= Cz (4-18)
s2 +K KR s+ KU
SC_










The stability issues of the type I and type II PLL are discussed thoroughly in [6], [47-48].

The phase margin of the system's open loop transfer function is often used to examine the

stability of the system shown in Figure 4-7. The characteristics of the open loop transfer function


show an approximately 900 phase margin at the gain crossover which will lead to stable locking


of the system.


nnn


-40dsldec

-20dsldec


Frequency (Hz)


Figure 4-9 Open loop gain characteristics of the proposed CDR loop.


4.3.2.3 Noise characteristics

The phase error characteristic, S-curve, which is expressed in terms of signal-to-noise ratio

(SNR), can be calculated by averaging the value of the phase error as (4-19) [33]. Obviously, the

loop of the system includes the noise term depicted in Figure 4-6.

g(#)= E[e(t)| #] (4-19)

As we have discussed in the previous section, the phase error of the proposed CDR loop

based on the modified Costas loop is equivalent to that of the polarity-type Costas loop.










Therefore, the averaged phase error of the proposed CDR can also be considered to have the

same value as that of the polarity-type Costas loop. Consequently, the phase error characteristic

can be represented as the equivalent form as derived in [33]. The S-curve for the QPSK signal,

that is M=-4 in [33], is represented as (4-20), where R=S/2NoB, S is the signal power, No is the

Gaussian noise spectral density, B is the noise bandwidth, a;;=sin[(2m-1)7/4], b,;=cos[(2m-


1)7/4], and Q(x)= 1 Sexp x / 2 -





+~ si (a, sin~ bi cosf)


-MS(-(- atcos-b +hsina) )-Qi(a,cosi+bisine~ )42






SNR, the S-curve performs like as sin40 [33].



0.8 ----1 d

0.6 3d

a, 0.4 i

o 0.2e \:



E -.
z -0.4t

-0.6

-0.8

-1670 -100 -50 0 50 100 150
Phase Error (deg)


Figure 4-10 Phase error characteristic with SNR (S-curve) of the proposed CDR loop.











The S-curve gives the ability to estimate the characteristics of the CDR loop when the

noise is inj ected. However, the HSRC-OQPSK signal is used as a wide-band signal utilizing a

band-limited channel such as a PCB board trace. The band-limited channel having low-pass

characteristics may affect the S-curve behaviors.

4.3.3 Behavioral Model Simulations

4.3.3.1 Phase error

To verify the functionalities of the proposed CDR, the proposed CDR is designed by

behavioral models using MATLAB Simulink. A transmitter generating the HSRC-OQPSK


signal is also modeled, as shown in Figure 4-11.



nerator




la00 Podc7 an Surc2 a ErorR e claer~slay HOOPSKP
Randorn-I nd ntegrUnplro e ltoprllCnv rate r
Converte
p~n onProduct1 Prdut Sa ple Relay1
Random-lteaer ndibld1t

HSRC-OQPSK Transitte and Hold4lx


Simlin beavoral models.Rla



TheR-QS t transmitter and th eevrsrcue odled b eairlcmoet r






basically the same as described in the previous section. The transmitter generates HSRC-OQPSK


signals using random data. The generated HSRC-OQPSK signal is fed into the receiver directly.

A F/F in the receiver is modeled by a S/H and a limiter, as shown in Figure 4-11.

For the phase error simulation, the QVCO signals modeled with ideal sinusoidal sources

with phase offset of 900 are used in both the transmitter and the receiver. An integrator of the











CDR accumulates the phase error generated from the phase mismatch of the carrier signals

between the transmitter and the CDR loop. The phase mismatch can easily be modeled by


changing the phase of the carrier signal. The simulation result of the averaged phase error fits

well with the analytical form obtained in (4-16), as shown in Figure 4-12.


08-

06-

E- 04-



S02-

0-O 0 -






-20 -1 5 -1 0 -0 5 0 0 0 5 1 0 1 5 2 0
Theta (Phase Difference)


Figure 4-12 Behavioral model simulation result of the phase error for the proposed CDR using
MATLAB .



4.3.3.2 Time domain simulation

The system is modeled with data-rate of lbps and the frequency of the carrier is 0.25Hz.

The reduced data-rate and the carrier frequency can be considered as 10Gbps and 2.5GHz


respectively in actual implementation.

Two VCOs with a phase difference of 900 replaced the ideal carrier signals in order to

model a QVCO, as shown as Figure 4-13. And the loop filter (LF) is characterized with a

transfer function which is equivalent to the characteristics of a series RC network given in the


loop analysis section.










The phase error signal, e(t), changes the frequency of the modeled QVCO. Figure 4-14

shows the simulation result of the phase error, e(t), which controls the frequency of the QVCO.

The initial frequency of the QVCO is 0.247Hz with a gain of 0.012Hz/V which are comparable

to 2.47GHz and 120MHz/V in a 10Gbps system, respectively.


Figure 4-13 HSRC-OQPSK Transceiver Model with QVCO for Time-Domain Simulation.


0.5

No 1/Q Mismatch
0.4
locking time

S0.3



2 0.1



SO



-0.1 -


Time Step (t) x 104


Figure 4-14 Time-domain response of phase error signal for the VCO frequency control.










In the locking state, approximately after 3700 time steps in Figure 4-14, the control voltage

is not changing because no error signal is generated from the loop. Ideally, the phase detector

(PD) of the loop would not generate an error signal while the non-linear PDs, such as a bang-

bang PD, have a charge inj section even in the locking state, which causes large control voltage

transitions in a type II PLL [6], [47]. However, high frequency components might be inj ected at

this control signal because of unavoidable mismatches in circuits, such as a device and an I/Q

mismatches in actual circuits.

Phase differences are added to one of the VCOs in order to observe the I/Q mismatch-

effects. Figure 4-15 illustrates the simulation of phase error, e(t), when the case of the phase


mismatch is 100. The locking time and ripple voltage of the phase error signal increase, as shown


in Figure 4-15. The ripple voltage directly affects the clock jitter making it degrade the system

performance .

0.5

10. 1/Q Mismatch
0.4
locking time

L0 .3 -



0 pea-peakripple

o





-0 *0
Time Step (t) x 104


Figure 4-15 Time-domain response of phase error signal for the VCO frequency control with 100
I/Q mismatch.












Figure 4-16 shows the normalized locking time and peak-peak ripple voltage in the locking

process. Since the locking time changes for random data sequences, the simulation results are

obtained from the average value of 5-time repeated simulation results. to is the average locking

time of control voltage when no I/Q mismatch has occurred. From the simulation results shown

in Figure 4-16, the locking time and peak-peak ripple voltage are almost proportional to the

amount of I/Q mismatch. Needless to say, it is important to reduce the ripple voltage because it

directly affects the QVCO's phase noise.





-0.04

o40-



+;- 0.02 -
20-1

.0 0.01
1 0-


0 0.00

SI II I '' '

0 2 4 6 8 10
I/Q Mismatch (deg)


Figure 4-16 Normalized settling time and peak-peak ripple voltage in locking state vs. I/Q
mismatch.



4.4 Chip Design (Rev. 2)

Since all the components can be characterized as a linear model in the behavioral model

simulation, the simulation is well-matched with the theoretical results. However, there are many

non-linear factors in circuit implementation such as a VCO gain, a clock jitter, or a clock feed

through of a S/H circuit.



110










In this chapter, the proposed receiver combined with a CDR is implemented and simulated

with UMC 0.18Cpm CMOS technology. The receiver consists of an input buffer, mixers, S/Hs,

F/Fs, a V/I converter, and a QVCO. Most of the circuits are designed with CML style circuits;

this is much the same for the transmitter design.

4.4.1 Circuit Implementation

4.4.1.1 Sample/hold circuit

[49] proposed a high speed S/H circuit, sampling bandwidth up to 7GHz with 0.25Cpm

CMOS technology, as shown in Figure 4-17. In tracking mode where the clock is high, the S/H

circuit operates as a differential amplifier. In the sampling mode when the clock falls, PMOS

loads and tail current source are turned off making the output nodes isolated so that the S/H

circuit is holding the sampled signal. M2 provides a low resistance differential load for wide

bandwidth operation. Ml pulls up the tail node to quickly turn off the input transistors, which

allows the amplifier bandwidth to be close to the sampling bandwidth [49].






outM outP



Vin M1I ~ I Vref


clk

bias



Figure 4-17 A high-speed differential sample/hold (S/H) circuit [49].


As mentioned in the previous section, a S/H circuit for the proposed CDR loop should

sample the input signal at both clock edges and maintain the signal until the next clock edge










(either rising or falling) occurs because the clock frequency of the loop for each channel is half-

symbol-rate. A ping-pong (PP) structure S/H circuit [50] can be used for this purpose. An analog

MUX selects one of S/Hs which are tracking the input signal alternately.

Figure 4-18 shows a differential double clock edge sampled S/H circuit based on the PP

structure S/H. The structure of the S/H shown in Figure 4-18 is equivalent to that of DET F/F.

However, the analog multiplexer of the S/H should linearly amplify the sampled signal without

limiting the output. Since the analog multiplexer shares the same structure of the mixer shown in

Figure 3-6, the linearity characteristics can be applied for the analog MUX.



Data _T IS/H

nalog-Ou
MUX



CLK


Figure 4-18 A ping-pong structure differential sample/hold circuit.


4.4.1.2 Quadrature VCO (QVCO)

As discussed in Chapter 3, a two-stage ring oscillator using a current-starved inverter or

shunt capacitor inverter can generate the quadrature clock signal. However, a LC QVCO has

been designed for the receiver to improve the phase noise of the carrier signal, as is the same

reason for that of the transmitter design. The proposed CDR loop is comparable to the quarter-

rate CDR of the NRZ signal. Typically, a quarter-rate CDR needs multi-phase clock signals for

the proper phase error estimation [32]. However, the proposed CDR for the HSRC-OQPSK

modulation uses quadrature-phase clock signals. Figure 4-19 shows the LC-QVCO structure [6].

A cross-coupled NMOS generates a negative resistance increasing the Q of LC tanks. The










outputs of one VCO, I+ and I-, are fed into the inputs of the other VCO, which generates

quadrature-phase outputs; Q+ and Q-. The Q+ and Q- are also fed into the inputs of the other

VCO. Detail analysis of the QVCO is found in [6].






Vc J ~ L~ ~ I











Figure 4-19 LC quadrature VCO (LC-QVCO).


The Q of inductor is approximately 8 with a value of 3.9nH. A higher value inductor has

chosen to get a large voltage swing to provide a clock signal for the appropriate operation of the

S/H circuit. The varactor value of 730fF with a fixed MIM capacitor of 320fF is used. The

frequency of VCO is controlled by a voltage of node vc, which changes the capacitances of the

varactors.

Figure 4-20 shows simulated QVCO's tuning range and its gain. The QVCO achieves a

tuning range of approximately 10% of the center frequency, 2.5GHz, and a maximum gain of

120MHz/V in the Cadence Spectre simulation. The VCO gain is relatively small, but a varactor

diode is chosen to get more linear tuning performance instead of using a MOS varactor. The

pull-in range is limited due to the small QVCO tuning range and its gain. However, the linear

tuning performance of the QVCO and low phase noise improve the system reliability as well as











reduce the jitter noise. The tail current of each NMOS is 2mA, therefore, each VCO stage


consumes 4mA. A voltage follower is used as an output buffer of the QVCO, which is not shown


in Figure 4-19. The phase noise of -117dBc/Hz at 1MHz offset is achieved in the Cadence


Spectre simulation.



2.62

2 .60-

2 .58-

2.56-
Kvco=120MHzN
N 2 .54-




2.46




2.44-

2.42-

-0. 2 0.0 0.2 0.4 0.6 0. 8 1 .0 1 .2 1 .4 1 .6
ControlI Voltage (V)


Figure 4-20 Simulated QVCO's tuning range and its gain.



4.4.1.3 Voltage-to-current (V/I) converter

A simple differential input to single ended output V/I converter is designed which is


illustrated in Figure 4-21. The simulated current gain is approximately 180CLA/V. A lead/lag


network as a loop filter is attached to the output node of the V/I converter. For more flexibility


to choose the loop filter, the VCO control line can be externally accessed. Therefore, the value of


the components of a loop filter can easily be replaced.



















Vin+


Figure 4-21 A differential to single-ended V/I converter.


4.4.2 Circuit Simulations

Figure 4-22 shows the detailed receiver structure. A buffer is inserted as a delay unit to

compensate the delay between the mixer output and the clock signal of the PP S/H, DET F/F.

The I/Q mixer outputs are tied directly together for combining the signal and followed by a

differential to single-ended V/I converter. The lead/lag type loop filter is attached to the control

node of the VCO.



-PP S/H



IF_ I I data
DET F/FF
V/1
Input Buffer Con ICverter
Signal in I dly dl acan


-DET F/F R,
Q OF Q dataC


-PP S/H
Os


Figure 4-22 A detailed receiver architecture.


bias ~











For the receiver simulation, the transmitter and the receiver are connected via a channel of

10cm transmission line with 5002 characteristic impedance modeled with RLC elements. Figure

4-23 shows the simplified simulation setup.


Transmitter Receiver
Data In


Signal tt D VCO HCDR





Figure 4-23 Time-domain simulation setup with a HSRC-OQPSK transmitter and 10cm
transmission line with characteristic impedance of 5002.


Since the output buffer of the Rev. 2 transmitter has been terminated with the on-chip

resistor, the external 5002 pull-up resistor has been attached to the receiver input. Both the source

and the end termination structure can minimize the signal reflections; however, the power would

be increased to transfer the signal compared to the open-drain structure which is used in Rev.1i's

transmitter. As used in the behavioral model simulation, a LF with R,=7KGZ, C,=30pF and

C=2pF is attached to the VCO control node for the simulation purpose. To decrease the ripple of

the control voltage distorting the phase of VCO, a small value of a capacitor is added to the node

in parallel. A 2pF capacitor is attached for this reason, as shown in Figure 4-23. Note that this

would not much change the characteristics of the closed loop time and frequency responses [6].

However, the much lower loop bandwidth has been realized in actual design to avoid high

frequency jitter noise. The loop parameters are chosen to ensure zero of a loop transfer function

located at lower frequency than the closed loop pole. These values are C=12nF, C,=150nF,










R,=5502 which are externally added to the test board. In this condition, the closed loop bandwidth


is approximately 200KHz and the phase margin is more than 600.


Figure 4-24 shows the simulated phase error signal, e(t), which illustrates the locking

behavior of the CDR. As discussed in behavioral simulation, if the I/Q channels are perfectly

matched, there is no charge inj section from the PD output when it is locking. However, a circuit' s

non-linearities make the I/Q mismatch which introduces high-frequency noises, that is, creates

the difference between behavioral and circuit simulations. From the result, the estimated locking

time of the CDR loop is approximately 500ns with the loop filter in Figure 4-24. The tuning

range of less than 50MHz is achieved by the simulation.


1.00


0.95-


0 .90-


0.85-


0.0 0.5 1 .0 1.5 2.0 2 .5


Time (us)

behavior of the proposed CDR loop.


Figure 4-24 Simulation of the locking


Since the receiver has no multiplexer for serializing retimed I/Q data, the I/Q data of the

transmitter and the receiver are compared, as shown in Figure 4-25. The transmitted data are










recovered by a demodulation process in the receiver after approximate Ins delay. Figure 4-25

shows the simulation results where the CDR locked the loop with the proper phase.



1 9, v: Tx a Data Transmitter Data Q Channel




1.S a: Tx I Data Transmitter Data I Channel

1 10

S0 : Rx Q Data Receiver Out Q Channel

1 20

1.B Receiver Out I Channel



2.0180u 2.0220u 2.0260u 2.0300u 2.0340L
tirne s )


Figure 4-25 I/Q data of the transmitter and the receiver in the proper phase locked state.


As mentioned in the previous section, the HSRC-OQPSK CDR has a four-fold phase

ambiguity as is the case of the conventional OQPSK modulation. Therefore, the CDR loop may

be locked in four possible phase points. Since only one phase has the proper phase relationship,

the phase ambiguity should be resolved for the proper data acquisition. As discussed before, a

differential coding with loss of 3dB power efficiency or other methods can fix this problem [10],

[46]. Intuitively, it might be also resolved with training bits at the initializing steps of the

communication. However, this fourfold phase ambiguity issue is for future work which is

discussed in Chapter 5.









4.4.3 Layout

The prototype receiver is designed and fabricated in UMC 0.18Cpm CMOS technology.

Figure 4-26 show the layout structure of the HSRC-OQPSK receiver.


Figure 4-26 HSRC-OQPSK receiver chip fabricated with UMC 0.18Cpm CMOS technology.


Four inductors for the quadrature VCO (QVCO) occupy the most part of chip, varactors

are place in the center and the demodulation logics with CDR are placed on right side of the

chip. The power and ground ring is placed around the chip, which are not shown in the die photo

because the power and ground ring is metal layers. Input signal pads are placed close to the

demodulation logic. The chip has 26 pads including 8 differential signal inputs and outputs

which are operated up to 10Gbps, 11 power and ground, 5 biases, and VCO control outputs for

the external loop filter with the total chip size of 1185Cpm X 1260Cpm. The bypass capacitor for

the power and ground has been placed at the unused chip area with the value of more than 60pF.









4.5 Measurement (Rev.2)

The same test of the transmitter' s has been used for the receiver. Figure 4-27 shows the test

board which is the same board as that of the transmitter' s. Bypass capacitor of approximately

100CLF are attached between the power and the ground. The I and Q channel outputs are to be

connected to the external 2:1 mux for the BER test. VCO outputs are for monitoring the locked-

state of the CDR loop and the recovered clock signal.






















Figure 4-27 Receiver test board.


Figure 4-28(a), (b) show the simplified 2.5Gbps and 10Gbps receiver measurement setups,

respectively. The signals are depicted with a single signal line for the simplification while the

actual signals are differential. Since it is not easy to estimate the receiver's performance with a

conventional signal generator because the proposed HSRC-OQPSK signal is different from the

conventional NRZ signal, the HSRC-QOPSK receiver incorporated with the proposed CDR

requires HSRC-QOPSK modulated signal to evaluate the receiver' s performance. Therefore, the









HSRC-OQPSK transmitter output is connected to the receiver input via a channel as shown in

Figure 4-28.

A 2.5GHz VCO signal output of the transmitter is fed into the external clock input of the

Agilent 4093A BERT for the 2.5Gbps BER test. An external 2:1 mux (Inphi 20709SE) operating

up to 20Gbps is located at the receiver output for serializing the I and Q channel data. The

serialized data is fed back into the BERT for the BER performance test of the receiver.


(b)

Figure 4-28 Simplified receiver (transceiver) measurement setups (a) for 2.5Gbps input
(equivalent data-rate of 5Gbps), (b) for 10Gbps data-rate.


Figure 4-29 shows the phase noise performance of the VCO. The red line in Figure 4-24

represents the phase noise of the receiver' s VCO signal in locked-state. The phase noise of the










recovered clock is approximately -87dBc/Hz at 50KHz offset. The 2.43Gbps random data has

been fed into the transmitter to generate the HSRC-OQPSK signal which is the source signal of

the receiver. The measured tracking range of the CDR is approximately 301VHz.

-40
rpe-|rugn n g
-50 _~ikt _l~ _LLL: _--~ ~-_ c-k

-60-

70t f~~ ri

'~-80






-110 -


-12 U 10K 1\/
Offset Frequency (Hz)


Figure 4-29 Phase noise performance of the receiver' s VCO in free-running and locking states.


Figure 4-30O illustrates the measured j itter of the recovered clock in response to 2.43 Gbps

PRBS sequence of 231-1. Since the modulated signal cannot be generated by BERT, the

transmitter outputs which generate the HSRC-OQPSK signal are connected to the receiver' s

inputs for the measurement. The measured rms j itter and the peak-to-peak j itter of the recovered

clock by the CDR loop are equivalent to 6.5ps and 39.9ps respectively.

Figure 4-31 shows the recovered I or Q channel data output when the 231-1 PRBS input has

been used. As shown in Figure 4-23, the BER test has been performed using 2.5Gbps and

10Gbps test setups, respectively with three different ( 5", 10", 20" ) FR-4 PCB channels and a

19" SATA cable. From the measurement results, BER of < 10-9 have been achieved up to 10"

PCB channel and a SATA cable where 2.43Gbps 231-1 PRB S is used while BER of 10-4 is









achieved where a 20" PCB channel is used. However, the BER of <10-9 has been achieved where

2.43Gbps 2 -1 PRBS is used. The power consumption of the receiver core is approximately

130mW from a 1.8V supply excluding power consumption of the output buffers for the I and Q

channel data, which is driving the input of the external 2:1 mux for serializing the data and

output buffer of the VCO for the purpose of monitoring.


Figure 4-30 Measured jitter of recovered clock in response to 4.86Gbps (both I and Q channel
input with 2.43Gbps PRB S sequence of 231-)


Figure 4-30 Recovered I (or Q) channel eye-diagrams in response to 4.86Gbps (both I and Q
channel input with 2.43 Gbps PRB S sequence of 23'1)










Unfortunately, it has been failed to evaluate the performance of the receiver at 9.72Gbps

because there are no reasonable BER performance and recovered eye-diagrams from the

measurement. One of the main reason of the failure in recovering the 9.72Gbps data is that the

transmitted signal generated from the transmitter does not have enough energy in a peak signal

which has the signal energy of E, analyzed in Chapter 2. Eye-opening mismatches in the

transmitted data-rate of 9.72Gbps eye-diagram shown in Figure 3 -27(a) caused a slight

synchronization mismatch between the clock and the data and it might affect the performance of

the receiver. Another reason for failure in recovering data might be from the CDR performance

of the receiver. However, it is hard to evaluate the CDR performance itself without the HSRC-

QOPSK modulated signal because there is no equipment that generates the ideal 10Gbps HSRC-

QOPSK signal. Although it has failed to recover 9.72Gbps transmitted data at the receiver which

is originally designed for recovering up to 10Gbps transmitted data, we could get a much

improved system performance if the low-noise and the broadband circuit design are considered

to design the transceiver. And frequency compensation techniques, such as a pre-emphasis of the

signal at the transmitter or the equalizing signal at the receiver-end using filter will also greatly

help in increasing the performance of the transceiver. However, these are put to future work.

Table 4-1 summarizes the performance of the receiver.


Table 4-1 Transceiver (Rev.2) performance summary

Data Rate 4.86Gbps (2.43Gb/s I/Q input)
@2 sequence of 231
BER Performance < 10-9 @ up to 10" PCB channel and 19" SATA cable
@ 4.86Gb/s PRBS input < 10-4 @ 20" PCB channel
(2.43 Gb/s PRB S I/Q input) @2 -1
< 10-9 @ 20" PCB channel
Phase Noise (recovered clock) -87dBc @ 50KHz offset









Table 4-1 (continued)
6.5ps (rms), 39.9ps (p -p)
Recovered clock jitter @ .3bsPESo 31-

30MHz
CDR tracking range.
(Loop Bandwidth 200KHz)
Power consumption Tx + Rx : 200mW @ 1.8V
~Tx: 1130 x1240Cpm2
Die SizeRx: 1185 x 1260pm2
Technology UMC 0.18Cpm CMOS

4.6 Summary

This chapter proposed a HSRC-OQPSK receiver incorporated with a new CDR loop, and

demonstrated its viability of increasing the data-rate in high-speed serial link system by using the

HSRC-OQPSK modulation. The proposed receiver has been designed with UMC 0.18Cpm CMOS

technology and the analysis has been compared with the simulation results. From the simulation

results, the time domain signals and the spectrum of the HSRC-OQPSK modulation fit well with

theoretical analyses.

This paper also proposed a CDR based on the Costas loop for the HSRC-OQPSK

modulation. The proposed CDR is comparable to a quarter-rate CDR of NRZ modulation

because it uses quarter data-rate frequency clock. Therefore, the proposed CDR can improve the

timing constraints of the receiver' s clock and data recovery. The CDR incorporated with the

receiver is simulated and compared to the analytical results. Moreover, the CDR uses a QVCO

instead of multi-phase VCO which is applied to a conventional quarter-rate CDR hence it offers

a simple receiver structure. The circuit simulation results of the phase error and the locking

behavior relatively fit well with the behavioral model simulation. In addition, the proposed CDR,

characterized as a linear PD, can lower the jitter noise [44-45].

The HSRC-OQPSK transceiver can easily be implemented with a low-voltage technology

due to the reason that it uses two level data decision while a multi-PAM (e.g., 4-PAM) system [3]









needs reference voltages and the level spacing which is difficult to maintain linear levels in a

low-voltage system for data decisions. Moreover, this allows a simple transceiver architecture.

The measurement results show the feasibility of using the HSRC-OQPSK as a modulation

technique offering a simple transceiver architecture for the high-speed wire-line

communications, such as a serial link. Moreover, the HSRC-OQPSK modulation and the

receiver can enable a serial link system to achieve higher data-rate without aiding a reference

clock in low-voltage wire-line communication systems.









CHAPTER 5
SUMMARY AND SUGGESTIONS FOR FUTURE WORK

5.1 Summary

The HSRC-PSK modulations are proposed to optimize spectral efficiency for high data-

rate transmission over band-limited channels. The analysis and simulation results show that the

proposed modulations can be used in high-speed data communications, such as a backplane

serial link.

In the past, a multi-PAM signal (e.g., 4-PAM) has been demonstrated to increase the data-

rate in band-limited channels [3]. However in 4-PAM modulation, it is difficult to maintain the

linear spacing between levels in low-voltage and low-power application and as a result the

system's performances are degraded. The level spacing also causes complexity in the transceiver

design not only because the received signal needs to be linearly amplified but also because 4-

PAM signaling requires accurate reference voltages.

The proposed HSRC modulations not only reduced the bandwidth requirement but also can

be easily implemented in deep submicron integrated circuit technologies with low supply

voltages. Three HSRC-PSK modulations named HSRC-QPSK, HSRC-OQPSK, and HSRC-

MSK are introduced and analyzed in terms of their spectrums and BER performances.

The HSRC-QPSK modulation can reduce the required bandwidth without any BER

performance degradation compared to the NRZ modulation. However, it is hard to implement a

HSRC-QPSK demodulator with a conventional circuit technique due to the difficulty in realizing

a matched filter in GHz range. The demodulation method for HSRC-QPSK is still under

investigation.

The HSRC-MSK modulation can minimize crosstalk noise compared to the conventional

ones, since the high frequency components are maximally suppressed [14] among the introduced









three quadrature HSRC-PSK modulations. However, it does not help to reduce the required

bandwidth of the transmitted signal because the first null bandwidth is the same as that of the

NRZ modulation.

The HSRC-OQPSK modulation has been chosen as a feasible modulation technique which

can be used in high-speed wire-line data communications. A prototype HSRC-OQPSK

transmitter has been designed with discrete components to verify the theory. Measurement

results confirmed that the proposed modulations can be effectively used in band-limited wire-line

applications requiring spectral efficiency, such as the backplane serial link. Moreover, because it

requires only a two-level decision, the HSRC-OQPSK transmitter can be implemented in a

simpler architecture than 4-PAM and is suitable for low-voltage systems. The HSRC-OQPSK

spectrum, which is the same as the MSK spectrum, contains 99% of the total signal power within

the bandwidth of B (1.2/Tb). In COmparison, 4-PAM which has the same signal spectrum as

that of QPSK has a much larger 99% bandwidth of B (8/Tb) [13]. Therefore, it is expected that

the proposed HSRC-OQPSK modulation should have an efficient signal spectrum in band-

limited channels and also this spectrum efficiency will reduce the high frequency crosstalk noise

between the signal lines which may improve the performance of the multi-port serial

communication links.

Moreover, a fully reference-less serial link transceiver using the HSRC-OQPSK

modulation has been proposed and demonstrated its viability of increasing data-rate in high-

speed serial link system. The proposed transceiver has been designed with UMC 0.18Cpm CMOS

technology and the analysis has been compared with the simulation results. From the simulation

results, the time domain signals and the spectrum of the HSRC-OQPSK modulation fit well with

the theoretical analyses.










A QPSK carrier recovery loop can be used for the proposed HSRC modulations which

enables flexible design of the receiver. A new CDR loop for the HSRC-OQPSK based on the

polarity-type Costas loop has been proposed and implemented by the UMC 0.18Cpm CMOS

technology. This paper also proposed a CDR based on the Costas loop for the HSRC-OQPSK

modulation. The proposed CDR is comparable to a Iquarter-rate CDR of the NRZ modulation

because it uses a quarter data-rate frequency clock. Therefore, the proposed CDR can improve

timing constraints of the receiver' s clock and data recovery. Moreover, the HSRC-OQPSK

allows a simple transceiver architecture which can easily be implemented with a low-voltage

technology due to the reason that it uses two-level data decision while a multi-PAM (e.g., PAM-

4) system [3] needs reference voltages and the level spacing which is difficult to maintain linear

levels in a low-voltage system for data decisions. Table 5-1 summarizes and compares the

characteristics of the conventional modulations and the proposed HSRC-OQPSK modulation.


Table 5-1 Performance comparison of the different modulations.


PAM-2 .HSRC-
PAM-4 Duobmnary
(NRZ) OQPSK

Main lobe bandwidth
Transmitted 1/T;, 1/2T, 1/2T, 3/4T,
(first null)
Signal
Spectrum Difference between 13dB 13dB 13dB 23dB
main and second lobe

'CDR Clock Frequency Full Rate Half Rate Full Rate Quarter Rate

# of Level 2 4 3 2
Data
Decision Threshold 1 3 21
Decision
Decision Interval Th 2T;, T;, 2T;,




Half and quarter data rate CDR has been developed for the PAM signaling [32], [5 1].











The results show that the HSRC-OQPSK modulation and the transceiver can enable a


serial link system to achieve a higher data-rate without aiding a reference clock in low-voltage

wire-line communication systems.

5.2 Four-fold Ambiguity Issue

As mentioned in Chapter 4, the proposed CDR based on the Costas loop has a fourfold


ambiguity problem. Only one out of the four stable locking points has proper phase information.

The differentially encoded data can resolve this four-fold ambiguity problem with 3dB signal to

noise ratio (SNR) degradation [10]. A transmitter with differentially encoded data input can be


implemented using a XOR gate and a F/F, as shown in Figure 5-1. It is essential for the

architecture of Figure 5-1(a) to have a parallel-to-serial logic which is implemented with a 2: 1

multiplexer in the receiver. The alternative architecture decoding the data in the receiver without


using a 2: 1 multiplexer is shown in Figure 5-1(b). The I and Q channels of the receiver generate

the demodulated data which are offset with one bit-time, Tb, OffSet, hence, the architecture shown

in Figure 5-1(b) can also be used to decode the modulated data.


Transceiver 1Tasie

Data In
D Q HSRC-OQPSK
Transmitter

Channel


HSRC-OQPSK
Receiver
(Include 2 1 m l le
Data Out with l/Q Inputs)
Q D





(a)

Figure 5-1 A differentially coded HSRC-OQPSK transceiver architecture to resolve the fourfold
ambiguity issue (a) the receiver includes a 2:1 multiplexer for serializing I/Q channel
data (b) alternative architecture without using a multiplexer.











Transceiver 1Tasie

Data In
D Q -HSRC-OQPSK
Transmitter

Channel



Data OHSRC OQPSK
CKD






(b)

Figure 5-1 (continued).

Another approach to resolve the fourfold ambiguity issue is synchronization at the protocol

layer. Every serial data link communications almost all data communications needs

synchronization, that is initialization of the data communications. Bits are sent out to the channel

from the least-significant bit (LSB) to the most-significant bit (MSB). All packets start with a

synchronization (SYNC) field, which is coded for the maximum edge transition rate. It is used

by CDR to recover the clock and data synchronization. A SYNC filed is defined to be eight bits

in length for full/low speed and 32 bits for high speed in the USB specification 2.0 [52] as an

example. Packet identifier (PID) follows the SYNC field. The USB specification 2.0 protocol

detail is presented in [52].

The protocol detail is not discussed in this chapter; however, a conceptual resolution of

the fourfold ambiguity by using a SYNC field. As described before, the SYNC field is coded to

make maximum edge transition in order to give more gain to the circuitry which aligns the

incoming data. However, the HSRC-OQPSK should have different SYNC to maximize edge

transition because it uses a carrier for the modulation. The carrier signal transforms the original











transmitted data sequences. To make it simple, assume the SYNC Hield is eight bit as is the case

for full/low speed of USB specification 2.0 and the SYNC field of the initial transmitter of

'10010110' has the maximum edge transition.

The data is split into I and Q channel '1001' and '0110' for the transmitter. After

demodulated at the receiver, four possible data sequences exist on the I and Q channel. When the

CDR locks the loop with a proper locking phase, the data sequences are the same as the

transmitted ones which are '1001' and '0110' for the I and Q channels of the receiver,


respectively. If the loop is locked with -!900 phase offset, one of the I/Q channels would recover


the transmitted data reversely from the original data which are '0110', '0110' or '1001', '1001'.

Both the I/Q data are inverted -' 0110' and '1001'- on condition that the CDR loop is locked


with the 1800 phase offset. With these four possible SYNC Hields at the receiver, we can estimate


at which phase the CDR loop is locked. Figure 5-2 shows the conceptual four-fold ambiguity

resolution method using a SYNC Hield.


( ~I Dntrol
I Data Out

CK


I D D D Q D QLogical Operation
HSRC-OQPSK (Control signals generate
Receiverlogical1 If the SYNC of Q
Is Inverted from expected
D Q D Q D Q D Q value, otherwise logical 0)

CKB

Q Data Out
4 oto




Figure 5-2 An example of a conceptual architecture for resolving four-fold ambiguity issue using
eight bits SYNC Hield.










LIST OF REFERENCES

[1] A. B. Carson, P. B. Crilly, and Janet C. Rutledge, Conanunication Systems, New York:
McGraw-Hill, 2001, ch. 11.

[2] G. Lawday, "On the buses" IEE Review, pp. 44-47, Jan. 2004.

[3] R. Farjad-Rad, C.-K. Ken Yang, M. A. Horowitz, and T. H. Lee, "A 0.3-Clm CMOS 8-Gb/s
4-PAM serial link transceiver," IEEE Journal ofSolid-State Circuits, vol. 35, no.5 pp. 757-
764, May 2000.

[4] J. T. Stonick, G.-Y. Wei Yang, J. L. Sonntag, and D. K. Weinlader, "An adaptive PAM-4
5Gb/s backplane transceiver in 0.25Cpm CMOS," IEEE Journal ofSolid-State Circuits, vol.
38, no.3 pp. 436-443, Mar. 2003.

[5] R. Farj ad-Rad, "A CMOS 4-PAM Multi-Gbps Serial Link Transceiver," Ph.D.
dissertation, Dept. Elct. Eng., Stanford Univ., Stanford, CA, 2000.

[6] B. Razavi, Design oflntegrated Circuits for Optical Conanunications, McGraw-Hill, 2003.

[7] P. Kabal, S. Pasupathy "Partial-response signaling," IEEE Transactions on
Conanunications, vol. 23, no. 9, pp. 921-934, Sep. 1975.

[8] M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos, "High-speed electrical signaling:
overview and limitations," IEEE Micro, pp. 12-24, Jan. 1998.

[9] J. H. Sinsky, M. Duelk, and A. Adamiecki, "High-speed electrical backplane transmission
using duobinary signaling," IEEE D ansaction on M~icrowave Theory and Techniques, vol.
53, no. 1, pp. 152-160, Jan. 2005.

[10] J. G. Proakis, Digital Conanunications, New York: McGraw-Hill, 1995.

[1l] D. R. Smith, Digital Transnzission Systems, New York: Van Nostrand Reinhold, 1985, ch.


[12] T. S. Rappaport, Wireless Conanunications, NJ: Upper Saddle River, Prentice Hall, 1996,
ch. 5.

[13] S. Pasupathy, "Minimum shift keying: a spectrally efficient modulation," IEEE
Communications Magazine, pp. 14-22, July 1979.

[14] R. Bashirullah, W. Liu, and R. Cavin, "Cross-talk reduction for interconnect-limited bus
based on raised cosine signaling," Proceeding of 2002 CICC, pp. 5 13-51 6

[15] S. A. Gronemeyer, and A. L. McBride, "MSK and offset QPSK modulation," IEEE
Transactions on Conanunications, vol. 24, no. 8, pp. 809-820, Jul. 1976.










[16] T. J. Gabara and W. C. Fischer, "Capacitive coupling and quantized feedback applied to
conventional CMOS technology," IEEE Journal ofSolid-State Circuits, vol. 32, no. 3, pp.
419-427, Mar. 1997.

[17] L. Luo, J. M. Wilson, S. E. Mick, J. Xu, L. Zhang, and P. D. Franzon, "3Gb/s AC coupled
chip-to-chip communication using a low swing pulse receiver," IEEE Journal of Solid-
State Circuits, vol. 41, no. 1, pp. 287-296, Jan. 2006.

[ 18 ] Part3: Carrier sense multiple access nI ithr collision detection (CSM~A CD) access method
and physical layer specification, IEEE Standards 802.3-2002.

[19] J. Yoon, and W. Eisenstadt, "Lumped passive circuit for 5GHz embedded test of RF
SoCs," IEEE ISCAS, pp. 1241-1244, May 2004.

[ 20] T. H. Lee, The Design of CM~OS Radio-Frequency hItegrated Circuits, 2nd, MA:
Cambridge University Press, 1998, ch. 18.

[21] B. Razavi, RF2\~icroelctronics, NJ: Upper Saddle River, Prentice Hall PTR, 1997, ch. 5.

[22] P. Heydari, "Design and analysis low-voltage current-mode logic buffers," Proceedings of
I' ISQEDO3, pp. 293-298, 2003.

[23] B. Razavi, Design ofAnalog CM~OS Integrated Circuits, New York: McGraw-Hill, 2003.

[24] P. Heydari, and R. Mohanavelu, "Design of ultrahigh-speed low-voltage CMOS CML
buffres and latches," IEEE Transactions on YISI Systents, vol. 12, No. 10, pp. 1081-1093,
Oct. 2004.

[25] M. G. Johnson, and E. L. Hudson, "A variable delay line PLL for CPU-coprocessor
synchronization," IEEE Journal ofSolid-State Circuits, vol. 23, no.5 pp. 1218-1223, Mar.
1988.

[26] A. Mazzanti, P. Uggetti, and F. Svelto, "Analysis and design of LC dividers for quadrature
generation," IEEE Journal ofSolid-State Circuits. vol.39, no.9, pp. 1425-1433, Sep. 2004

[27] H. Johnson, and M. Graham, High-SpeedDigitalDesign, 1st, Prentice Hall PTR, 1993.

[28] S. Galal, and B. Razavi, "10-Gb/s limiting amplifier and laser/modulator driver in 0. 18-Cpm
CMOS technology," IEEE Journal ofSolid-State Circuits, vol. 38, no. 12, pp. 2138-2146,
Dec. 2003.

[29] Affirnza Spectre Circuit Simulator User Guide, Cadence Design Systems Inc., San Jose,
CA, 2000.

[30] A. Adamiecki, M. Duelk, and J. H. Sinsky, "25Gbit/s electrical duobinary transmission
over FR-4 backplanes," IEE Electronics Letters, vol. 41, no. 14, pp. 826-827, Jul. 2005.










[31] K. Yamaguchi, K. Sunaga, S. Kaerlyama, T. Nedachi, M. Takamiya, K. Nose, Y.
Nakagawa, M. Sugawara, and M. Fukaishi, "12Gb/s Duobinary signaling with x2
oversampled edge equalization," ISSCC 2005 IEEEhInternational, pp. 584-585

[32] J. Lee and B. Razavi, "A 40-Gb/s clock and data recovery circuit in 0. 18um CMOS
technology," IEEE Journal of Solid-State Circuits, vol. 3 8, no. 12, pp. 2 18 1~-2190, Dec.
2003

[33] H. C. Osborne, "A generalized "polity-type" Costas loop for tracking MPSK signals,"
IEEE Transactions on Conanunications, vol. 30, no. 10, pp. 2289-2296, Oct. 1982.

[34] M. K. Simon, "Tracking performance of Costas loop with hard-limited in-phase channel,"
IEEE Transactions on Conanunications, vol. 26, no.4, pp. 420-432, Apr. 1978.

[35] J. P. Costas, "Synchronous communications," Proceedings of the IRE, vol. 44, no. 12, pp.
1713-1718, Dec. 1956.

[36] W. C. Lindsey and M. K. Simon, "Carrier synchronization and detection of polyphase
signals," IEEE Transactions on Conanunications, vol. 20, no.3, pp. 441-454, Jun. 1972.

[37] A. Leclert, and P. Vandamme, "Universal carrier recovery loop for QASK and PSK signal
sets," IEEE Transactions on Conanunications, vol. 31, no.1i, pp. 130-136, Jan. 1983.

[38] M. K. Simon and J. G. Smith, "Carrier synchronization and detection of QASK signal
sets," IEEE Transactions on Conanunications, vol. 20, no.2, pp. 98-106, Feb. 1974.

[39] M. K. Simon, "On the optimality of the MAP estimation loop for carrier phase tracking
BPSK and QPSK signals," IEEE Transactions on Communications, vol. 27, no. 1, pp. 158-
165, Jan. 1979.

[40] C. L. Weber, and W. K. Alem, "Demod-remod coherent tracking receiver for QPSK and
SQPSK," IEEE Transactions on Conanunications, vol. 28, no. 12, pp. 1945-1954, Dec.
1980.

[41] C. L. Weber, and W. K. Alem, "Performance analysis of demod-remod coherent receiver
for QPSK and SQPSK input," IEEE Transactions on Conanunications, vol. 28, no. 12, pp.
1954-1968, Dec. 1980.

[ 42] R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications, New Y ork:
M~cGraw-Hill, 2003, ch. 9.

[43] H. Yeo, Y. Lee, J. Chen, and J. Lin, "Half-symbol-rate-carrier offset QPSK transmitter for
bandwidth-efficient high-speed data communications," IEEE Microwave and Wireless
Components Letters, vol. 17, no. 6, pp. 466-468, June 2007.

[44] S. B. Anand, and B. Razavi, "A CMOS clock recovery circuit for 2.5Gb/s NRZ data,"
IEEE Journal ofSolid-State Circuits, vol. 36, no.3, pp. 432-439, Mar. 2001.










[45] C. R. Hoggie, "A self correcting clock recovery circuit," IEEE Journal ofLightwave
Technology, vol. 3, no. 6, pp. 1312-1314, Dec. 1985

[46] E. R. Cacciamani. and C. J. Wolej sza, Jr. "Phase ambiguity resolution in a four-phase PSK
communications system," IEEE Transactions on Conanunication Technology, vol. 19,
no.6, pp. 1200-1210, Dec. 1971.

[ 47] B. Razavi, M~onolithic Phasee-LockeadLoops and' Clock Recovely Circuits, NJ: Piscataway,
IEEE Press, 1996.

[48] F. M. Gardner, "Charge-pump phase locked loops," IEEE Transactions on
Conanunications, vol. 28, no. 11, pp. 1849-1858, Nov. 1980.

[49] C.-K. Ken Yang, V. Stojanovic, S. Modjtahedi, M. A. Horowitz, and W. F. Ellersick, "A
serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-Cpm
CMOS," IEEE Journal ofSolid-State Circuits, vol. 36, no. 11, pp. 1684-1691, Dec. 2001.

[50] M. H. Shakiba, D. A. Johns, and K. W. Martin, "BiCMOS circuits for analog Viterbi
decoders," IEEE Transactions on Circuits and' Systems, vol. 45, no. 12, pp. 1527-1537,
Dec. 1998.

[51] J. Savoj, and B. Razavi, "10-Gb/s CMOS clock and data recovery circuit with a half-rate
binary phase/frequency detector," IEEE Journal ofSolid'-State Circuits, vol. 3 8, no.1i, pp.
13-21, Jan. 2003.

[ 52] thriversal Serial Bus Specifications, revision 2.0, Apr.. 2000.









BIOGRAPHICAL SKETCH

Hyeopgoo Yeo was born in Seoul, Korea, in 1968. He received his B.S. and M. S. degrees

in electronic engineering from Yonsei University, Seoul, Korea, in 1991 and 1993, respectively.

He also received his M. S. degree in electrical and computer engineering from the University of

Florida, Gainesville, USA, in 2003.

From 1993 to 1999, he worked as a design engineer at Samsung Electronic Co. Ltd.,

Kihung, Kyounggi-do, Korea, where he performed CMOS ASIC cell library design and

development.

He is currently pursuing his Ph.D. degree as a graduate research assistant at the University

of Florida. His research interests involve RF/analog circuit design, high-speed digital systems.

He is particularly interested in high-speed serial links.





PAGE 1

1 DESIGN OF MULTI-GIGABIT SERIAL LI NK TRANSCEIVER USING BANDWIDTHEFFICIENT HALF-SYMBOL-RATE-CARRIE R OFFSET QUADRATURE PHASE SHIFT KEYING MODULATION By HYEOPGOO YEO A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2007

PAGE 2

2 2007 Hyeopgoo Yeo

PAGE 3

3 To my parents and family

PAGE 4

4 ACKNOWLEDGMENTS I express my sincere gratitude to my superv isory committee chair, Dr. Jenshan Lin, for his support throughout the course of this work. I also thank Professors William R. Eisenstadt, Rizwan Bashirullah, and Li-Chien Shen for thei r advice on this work an d their willing service and guidance on my research. Without their in valuable support and encouragement, my exploration in the research could not have come to fruition. I apprec iate their interest in my work and valuable suggestions and comments from the research proposal to its realization. I thank my fellow colleagues (Tien-Yu Ch ang, Mingqi Chen, Lance Covert, Sangwon Ko, Changzhi Li, Zehn Ning Low, Yachi Liu, Zivin Pa rk) in the Radio Frequency Silicon on Chip (RFSOC) Group for all the help they offered. My thanks also go to my other colleagues in Electrical and Computer Engineering for their he lpful discussion, advice, and friendship (Jongsik Ahn, Kooho Jung, Sudeep, Jeashin Kim, Jeaseok Kim, Kwangchun Jung, Eunyoung Seok, Dongha Sim, Kyujin Oh, Minsun Hwang, Seon-Ho Hwang). Their support and advice have contributed immensely to my work. Also, I thank all of the friends who made my years at the University of Florida such an enjoyable ch apter of my life (Jan gsup Yoon, SeungHwan Kim, Sanghoon Choi, Jiwoon Yang, Choongeol Cho, Okj une Jeon). I acknowledge TSMC and UMC for the technical and state-of -art fabrication support. I thank Inphi Corp. and Agilent Technologies for their help on test equipments. I dedicate this work and my deepest love to my parents who have given me utmost trust and support throughout the years. I express my profound thanks to my wife, Seungyun Lee, for her endless and unconditional love and support, and my dearest children, One and Myoung. Without them, it would not have been po ssible to pursue my graduate studies.

PAGE 5

5 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................4LIST OF TABLES................................................................................................................. ..........7LIST OF FIGURES................................................................................................................ .........8ABSTRACT....................................................................................................................... ............13 CHAPTER 1 INTRODUCTION..................................................................................................................151.1 Motivations................................................................................................................ .......151.2 Compensation Techniques of High Frequency Signal.....................................................191.2.1 Pre-Emphasis Signal...............................................................................................191.2.2 Broadband Circuit Technique.................................................................................201.3 Modulation Techniques....................................................................................................221.3.1 Conventional Modulation Techniques...................................................................221.3.2 Modulation Technique Using Ha lf-Symbol-Rate-Carrier (HSRC)........................241.3.2.1 Why Not Carrier Modulation?.............................................................................252 HSRC PHASE SHIFT KEYING (PSK) MODULATIONS..................................................272.1 Binary Modulation.......................................................................................................... ..272.2 Quadrature Modulations...................................................................................................282.2.1 HSRC Quadrature PSK (QPSK) Modulation.........................................................282.2.2 HSRC Offset QPSK (OQPSK) Modulation...........................................................282.2.3 HSRC Minimum Shift Keying (MSK) Modulation...............................................302.3 Signal Spectrum............................................................................................................ ....312.4 Bit Error Rate (BER) Performance...................................................................................332.5 DC-Free Signaling Based on HSRC-OQPSK Modulation...............................................412.5 Measurement of the HSRC-OQPSK Signal.....................................................................452.6 Summary.................................................................................................................... .......513 HSRC-OQPSK TRANSMITTER..........................................................................................533.1 Transceiver Architecture..................................................................................................533.1.1 A Conventional Serial Link Transceiver Architecture...........................................533.1.2 A Conceptual HSRC-OQPSK Transceiver Architecture.......................................533.2 HSRC-OQPSK Transmitter Architecture.........................................................................553.2 Circuit Implementation.....................................................................................................573.2.1 Current-mode-logic (CML) Circuit........................................................................573.2.2 CML Double-Edge Triggered D flip-flop..............................................................613.2.3 Resistive Load Gilbert Mixer.................................................................................62

PAGE 6

6 3.2.4 Quadrature Phase Clock Generator........................................................................633.2.5 I/Q Channel Signal Combining..............................................................................663.2.6 Output Buffer..........................................................................................................663.3 Chip Design................................................................................................................ ......693.3.1 Rev. 1 Transmitter..................................................................................................693.3.2 Rev. 2 Transmitter..................................................................................................713.4 Measurement................................................................................................................ .....763.4.1 Rev.1 transmitter....................................................................................................763.4.2 Rev. 2 transmitter...................................................................................................814 HSRC-OQPSK RECEIVER DESIGN...................................................................................914.1 Receiver Architecture...................................................................................................... .914.2 HSRC-OQPSK Receiver (Rev. 1)....................................................................................914.3 HSRC-OQPSK Receiver (Rev. 2)....................................................................................934.3.1 Polarity-Type Costas Loop for Carrier Synchronization........................................944.3.2 A New Clock and Data Recovery (CDR ) based on the Modified Costas Loop.....964.3.2.1 Phase detector characteristics.......................................................................974.3.2.2 Loop analysis..............................................................................................1024.3.2.3 Noise characteristics...................................................................................1044.3.3 Behavioral Model Simulations.............................................................................1064.3.3.1 Phase error..................................................................................................1064.3.3.2 Time domain simulation.............................................................................1074.4 Chip Design (Rev. 2)......................................................................................................1104.4.1 Circuit Implementation.........................................................................................1114.4.1.1 Sample/hold circuit....................................................................................1114.4.1.2 Quadrature VCO (QVCO).........................................................................1124.4.1.3 Voltage-to-current (V/I) converter.............................................................1144.4.2 Circuit Simulations...............................................................................................1154.4.3 Layout...................................................................................................................1194.5 Measurement (Rev.2).....................................................................................................1204.6 Summary.................................................................................................................... .....1255 SUMMARY AND SUGGESTIONS FOR FUTURE WORK.............................................1275.1 Summary.................................................................................................................... .....1275.2 Four-fold Ambiguity Issue.............................................................................................130LIST OF REFERENCES.............................................................................................................133BIOGRAPHICAL SKETCH.......................................................................................................137

PAGE 7

7 LIST OF TABLES Table page 2-1Summary of components used in the measurement...........................................................484-1Transceiver (Rev.2) performance summary....................................................................1245-1Performance comparison of the different modulations....................................................129

PAGE 8

8 LIST OF FIGURES Figure page 1-1Characteristics of a PCB trace channel with various lengths............................................161-2Basic information of eye diagram......................................................................................161-3Eye diagram of the 10Gbps signal at the fa r-end after tracing (a) 0.1 (b) 10 (c) 20 PCB channel.................................................................................................................... ...171-4High data-rate transmission with (a) a conve ntional parallel bus (b) a serial link............181-5Pre-emphasis of NRZ signal and receiv ed signal with/without pre-emphasis..................191-6Frequency domain representation of the pre-emphasis technique of the transmitted signal. 201-7Active inductor (a) realized with NMOS s ource follower (b) small signal equivalent circuit (c) simplified model................................................................................................211-8Comparison of PAM-2 and PAM-4 signal spectrum.........................................................231-9Basic digital modulation schemes (a) ba seband data (b) ASK (c) FSK (d) PSK..............241-10 Simplified spectrums of carrier modulati on signals (a) using car rier signal higher than data-rate (b) using half -symbol-rate-carrier signal....................................................262-1HSRC-BPSK modulation: baseband data sequences and modulated signal.....................272-2HSRC-QPSK and OQPSK (a) modulation scheme, (b) QPSK time domain waveforms, (c) OQPSK time domain waveforms.............................................................292-3HSRC-MSK (a) modulation scheme (b) time domain waveforms....................................302-4Normalized power spectral density for HSRC modulations..............................................322-5Modulated time domain signals of HS RC-OQPSK and its symbol energies....................332-6Gaussian distribution of different energy symbols for HSRC-OQPSK modulation.........362-7Comparison of theoretical and simulated BER performance of HSRC modulations........372-8The demodulated signal (a) demodulati on process of I (or Q) channel (b) demodulated peak signal ( Es,p) of the HSRC-OQPSK......................................................382-9Comparison of the BER performance between the symbol time (matched filter) and the bit time integration of HSRC-OQPK signal................................................................39

PAGE 9

9 2-10 Frequency response of the band-limited channel modeled with a one pole low-pass filter......................................................................................................................... ...........402-11 Comparison of simulated BER perf ormance of the PAM-2 (NRZ) and HSRCOQPSK modulation with band-limited channel................................................................412-12 DC-free modulation based on HSRC-OQ PSK (a) modulation scheme (b) timedomain waveforms.............................................................................................................432-13 Comparison of the spectra betw een NRZ and the dc-free signals.....................................442-14 A prototype HSRC-OQPSK tran smitter and measurement setup......................................452-15 A 500MHz branch-line hybrid quadrat ure power splitter structure for HFSS simulation..................................................................................................................... ......462-16 Simulated and measured characterist ics of the 500MHz branch-line hybrid quadrature power splitter (a) S-parameters (b) phases......................................................462-17 Measured characteristics of the HSRC-OQPSK modulation (equivalent 2Gbps random data input) (a) time do main waveform (b) spectrum............................................492-18 Comparison of the theoretical a nd measured waveforms of HSRC-OQPSK modulation..................................................................................................................... ....502-19 Comparison of the measured and theore tical spectrum of the HSRC-OQPSK signal......503-1A simplified conventional transcei ver for a serial data link..............................................543-2A conceptual HSRC-OQPSK tr ansceiver architecture......................................................543-3A HSRC-OQPSK transmitter architecture.........................................................................553-4A structure of the DET F/F and data and clock synchronization by inserting (a) delay unit (b) a MUX as a delay unit...........................................................................................563-5A fully differential (a) CML buffer and (b) differential input voltage versus output voltages....................................................................................................................... .......583-6Characteristics of a differential pairs ve rsus differential input voltage (a) drain currents (b) transconductance............................................................................................603-7CML Circuits (a) D-latch (b ) analog multiplexer (c) double-e dge triggered flip-flop......613-8A resistive load Gilbert mixer............................................................................................633-9Two different delay control circuit (a) a current-starved inverter (b) a shunt capacitive inverter............................................................................................................ ..64

PAGE 10

10 3-10 A fully differential (a) sh unt capacitor inverter with cross-coupled PMOS active load and (b) two-stage ring oscillator........................................................................................653-11 Injection-locked LC QVCO...............................................................................................663-12 Combining I and Q channel signal by direct connecting outputs......................................673-13 Three stage output buffer w ith open drain output stage....................................................673-14 Output buffer (a) differential threestage output buffer (b) doubly terminated structure...................................................................................................................... ........683-15 HSRC-OQPSK transceiver chip using TSMC 0.18 m CMOS technology......................693-16 HSRC-OQPSK modulation signal (a) time domain waveforms (b) signal spectrum........703-17 Transmitter die photo implemented by UMC 0.18 m CMOS technology.......................713-18 Linearity simulation of resi stive Gilbert mixer using UMC 0.18 m CMOS technology (a) conversion gain vs. LO pow er, (b) conversion gain vs. RF input frequency, (c) input referred 1dB compression.................................................................733-19 HSRC-OQPSK modulation signal (a) time domain waveforms (b) signal spectrum........743-20 Simulated dc-free signaling (a) time domain waveforms (b) signal spectrum..................753-20 Test board for the Rev. 1 HSRC-OQPSK transmitter (transceiver) implemented by TSMC 0.18 m CMOS Technology...................................................................................763-21 Measured spectrums and phase noise of the transmitters QVCO implemented by TSMC 0.18 m CMOS technology (center frequency of 2.5GHz with 5MHz span and 47 KHz RBW) (a) free-running mode (b) inje ction-locked mode (c) comparison of the phase noises between free-runn ing and injection-locked modes.................................773-22 Simplified test setups for (a) 2.5Gbps (5Gbps equivalent) (b) 10Gbps random input for the transmitter............................................................................................................ ...793-23 Eye-diagram of the HSRC-OQPSK tr ansmitted signal implemented by TSMC 0.18 m CMOS technology................................................................................................813-24 Test board for the Rev. 2 transmitter implemented by UMC 0.18 m CMOS technology..................................................................................................................... .....823-25 Measured spectrums and phase noise of the transmitters QVCO implemented by UMC 0.18 m CMOS technology (center frequency of 2.25GHz with 100MHz span and 910 KHz RBW) (a) free-running mode (b ) injection-locked mode (c) comparison of the phase noises between the free-r unning and the injection-locked modes.................833-26 Characteristics of channels used in the measurement........................................................85

PAGE 11

11 3-27 Eye-diagram of HSRC-OQPSK tr ansmitted signal implemented by UMC 0.18 m CMOS technology after (a) 2 PCB trace, (b ) 5 PCB trace, (c) 10 PCB trace, (d) 20 PCB trace, (e) 19 SATA cable, in re sponse to 4.86Gbps (both I and Q channel input with 2.43Gbps pseudo random bit stream (PRBS) sequence of 231-1).....................863-28 Spectrum of 4.86Gbps dc-free signal.................................................................................883-29 Eye-diagram of the HSRC-OQPSK transmitted signal with 9.72Gbps PRBS sequence of (a) 27-1 (ideal eye-opening is depict ed with blue line), (b) 231-1..................893-30 Signal spectrum in response to9.72Gbps PRBS sequence of 27-1.....................................534-1 HSRC-QOPSK receiver (Rev. 1) architectur e incorporated with quarter-rate PD............924-2Quarter-rate phase detector (a) archit ecture (b) waveforms (for 40Gbps NRZ)...............924-3HSRC-OQPSK receiver architecture incorporated with a CDR........................................944-4Polarity-type Costas loop for QPSK signal carrier recovery.............................................954-5A modified Costas loop for the HSRC-OQP SK signal clock and data recovery..............974-6Early and late sampli ng time of I/Q data.........................................................................1004-7Averaged phase detector characteristic of the proposed CDR loop................................1014-8Equivalent linear model of proposed CDR for HSRC-OQPSK......................................1034-9Open loop gain characteristics of the proposed CDR loop..............................................1044-10 Phase error characteristic with SN R (S-curve) of the proposed CDR loop.....................1054-11 Phase error simulations of the CDR for the HSRC-OQPSK signal with MatLab Simulink behavioral models............................................................................................1064-12 Behavioral model simulati on result of the phase erro r for the proposed CDR using MATLAB.........................................................................................................................1074-13 HSRC-OQPSK Transceiver Model with QVCO for Time-Domain Simulation.............1084-14 Time-domain response of phase error signal for the VCO frequency control.................1084-15 Time-domain response of phase error signa l for the VCO frequency control with 10 I/Q mismatch................................................................................................................... .1094-16 Normalized settling time and peak-peak ripple voltage in locking state vs. I/Q mismatch....................................................................................................................... ...1104-17 A high-speed differential sample/hold (S/H) circuit........................................................111

PAGE 12

12 4-18 A ping-pong structure differe ntial sample/hold circuit....................................................1124-19 LC quadrature VCO (LC-QVCO)...................................................................................1134-20 Simulated QVCOs tuning range and its gain..................................................................1144-21 A differential to singl e-ended V/I converter....................................................................1154-22 A detailed receiver architecture.......................................................................................1154-23 Time-domain simulation setup with a HSRC-OQPSK transmitter and 10cm transmission line with characteristic impedance of 50 .................................................1164-24 Simulation of the locking beha vior of the proposed CDR loop.......................................1174-25 I/Q data of the transmitter and the re ceiver in the proper phase locked state..................1184-26 HSRC-OQPSK receiver chip fabricated with UMC 0.18 m CMOS technology...........1194-27 Receiver test board....................................................................................................... ....1204-28 Simplified receiver (transceiver) meas urement setups (a) for 2.5Gbps input (equivalent data-rate of 5Gbps ), (b) for 10Gbps data-rate...............................................1214-29 Phase noise performance of the receivers VCO in free-running and locking states......1224-30 Measured jitter of reco vered clock in response to 4.86Gbps (both I and Q channel input with 2.43Gbps PRBS sequence of 231-1)................................................................1234-30 Recovered I (or Q) channel eye-diagra ms in response to 4.86Gbps (both I and Q channel input with 2.43G bps PRBS sequence of 231-1)..................................................1235-1A differentially coded HSRC-OQ PSK transceiver architecture to resolve the fourfold ambiguity issue (a) the receiver includes a 2:1 multiplexer for serializing I/Q channel data (b) alternative architectur e without using a multiplexer..........................................1305-2An example of a conceptual architecture for resolving four-fold ambiguity issue using eight bits SYNC field.............................................................................................132

PAGE 13

13 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DESIGN OF MULTI-GIGABIT SERIAL LI NK TRANSCEIVER USING BANDWIDTHEFFICIENT HALF-SYMBOL-RATE-CARRIE R OFFSET QUADRATURE PHASE SHIFT KEYING MODULATION By Hyeopgoo Yeo August 2007 Chair: Jenshan Lin Major: Electrical and Computer Engineering My research introduces new quadrature phase -shift-keying (QPSK) modulation techniques for high-speed data communication systems that use two orthogonal half-symbol-rate-carrier (HSRC) signals by which channel bandwidth requir ements are reduced compared to that of the conventional non-return-to-zero (NRZ) modulation. The proposed HSRC offset-QPSK (HSRCOQPSK) improves spectral efficiency by reducing the side lobes of the signal spectrum. In addition, HSRC minimum-shift keying (HSRC-MS K) modulation is also introduced. The performances and the simulation results of th e proposed modulation techniques are studied and compared with those of the conventional ones. Using the proposed HSRC-OQPSK modulati on, a prototype transmitter generating the HSRC-OQPSK signal was designed and built. Measur ement results confirm the theory that the proposed HSRC-OQPSK modulation improves spectral efficiency by reducing the second lobe of the signal spectrum by 10dB. Furthermore, the HSRC-OQPSK modulation reduces the first null bandwidth by 25% compared to the standard Non-Return-to-Zero (NRZ) modulation. Like NRZ, HSRC-OQPSK uses a 2-level data deci sion which enables a simpler transceiver

PAGE 14

14 architecture than multi-level pulse amplitude modulations (PAM), such as 4-PAM and duobinary. My research also examines a modified Costas loop for the clock and data recovery (CDR) involving HSRC-OQPSK modul ation. Behavioral model simulation has verified analysis of the proposed CDR. The carrier frequency of the HSRCOQPSK signal is quarter data rate. Hence the proposed CDR is comparable to quarter-rate CDR using quadrature-phase VCO (QVCO), which relaxes the timing constraints and a llows a simple structure as well. The HSRC-OQPSK transceivers are implemen ted and simulated with TSMC and UMC 0.18 m CMOS technology to prove the theoretical performance. The theory and the measurement results show that it is feasible to increase the data-rate in wire-line communications using low-cost channels.

PAGE 15

15 CHAPTER 1 INTRODUCTION 1.1 Motivations These days, a demand for high data rate transmission through low cost band-limited channels (e.g., copper trace on FR4 PWBs and CA T-5 cables) is increasing. Data transmission with binary format, (represented by non-return-tozero (NRZ) format) to receive data looks very simple and clear. However, it is a real challenge to high data rate comm unications over the bandlimited channel because of impaired signal loss, reflections, and crosstal k. Although parallel I/O data transmission is efficient for short length da ta communications, it suffers from a large data skew and jitter for the aforementioned reasons. O bviously, those problems will be more severe as data rates and channel lengths increase. The high speed point-t o-point link, a se rial link, can overcome these kinds of bottlenecks. It offers high data transmission, up to multi-gigabit data transmission, over a long PCB trace, and a cable line. The transmitted signal bandwidth for the point-to-point links increases dire ctly proportional to the data ra te. Since a low cost channel, such as a PCB trace (e.g., copper cable), has lowpass characteristics, the high frequency loss of the transmitted data is unavoidable, as shown in Figure 1-1. This fre quency dependent low-pass characteristic largely comes from the skin effect of the material as well as dielectric loss of the material. Figure 1-1 also shows the frequency characteristics of the FR4 PCB with various lengths. 10 GHz signal atte nuated about 20dB in 50 characteristic impedance of 20 length with a tangential loss of 0.023. Besides board trac e, a board attachment, a connector, and IC package make parasitics. Unfortunately, thes e cause nonlinear effect s such as reflection, resonance, and ripple.

PAGE 16

16 2468101214 016 -25 -20 -15 -10 -5 -30 0 freq, GHzdB(S(2,1))5" 10" 20" 15" Figure 1-1 Characteristics of a PCB trace channel with various lengths. The non-return-to-zero (NRZ) signal, which is the same as PAM-2, is commonly used for digital systems including high speed serial links. The NRZ signal, de fined as binary data, can be very simple because the signal has 2-levels and is easily implemented by digital circuits. An eye diagram is usually used to estimate signal qual ity. The signal is chopped into equal periods and accumulated onto one plot. The eye diagram gives vi sual information regarding signal usefulness in data communica tion systems [1]. Zero-crossing jitter Unit Interval SNR at the sampling point ISI Ideal sampling point Figure 1-2 Basic information of eye diagram.

PAGE 17

17 Figure 1-3 shows an example of the eye diag rams for various trac e lengths. The 10Gbps random binary data is applied to the input por t and the output signal is monitored. The eye diagram has no jitter components and its opening is very clear with 0.1 channel trace. However, as the PCB trace increases, distortion and jitter components are introduced to the signal and the eye opening is almost closed after 20 trace, as shown in Fig. 1-3(a). 0.1" 020406080100120140160180200 -20220 0.0 0.2 0.4 0.6 0.8 1.0 -0.2 1.2 time, psec 020406080100120140160180200 -20220 0.0 0.2 0.4 0.6 0.8 1.0 -0.2 1.2 time, psec10" 020406080100120140160180200 -20220 0.0 0.2 0.4 0.6 0.8 1.0 -0.2 1.2 time, psec20" (a) (b) (c) Figure 1-3 Eye diagram of the 10G bps signal at the far-end after tr acing (a) 0.1 (b) 10 (c) 20 PCB channel. Conventional parallel bu ses are used for short range data links such as system buses between CPU and the main memory to increase th e data-rate. However, there are several crucial limitations to increase data-rate to infinity. Firs t, in high-speed parallel buses, signal jitter and data skew occur due to the crosstalk between signals, which causes a synchronization problem between the signal lines at th e receiver-end. The synchroniza tion mismatch prevents the appropriate data transmission between the tran smitter and the receiver even though a precise clock signal is used for the data fetch. Figure 1-4 shows the example of data skew between the signal lines and the misaligned da ta arrival at the receiver-end which causes the wrong data transfer. Moreover, the skew probl em is getting more severe as the clock frequency goes high [2]. Instead of using paralle l buses, point-to-point communication called a serial link is used to resolve the skew problem. This communicati on uses a low-swing signal instead of a conventional large swing signal w ith the terminations which pr event the signal reflection. The

PAGE 18

18 low-swing signaling can also redu ce the power dissipation. However, to convert the parallel-bit data into a serial data, the clock frequency s hould be increased by the parallel bit times for maintaining the data-rate. However, this method can resolve the data skew between the data in parallel bits, hence, the synchroni zation problem can be fixed even if the jitter is introduced to the signal. Of course, the duration of the data fetc h timing is reduced due to the jitter in the signal. Figure 1-4(b) shows the exam ple of the serial link. TxRxParallel Bus Serial LinkCrosstalk, Jitter, Skew (Backplane PCB, USB, Ethernet, Optical link) ex) USB2 : 480Mb/s(a) (b) TxRxParallel Bus Serial LinkCrosstalk, Jitter, Skew (Backplane PCB, USB, Ethernet, Optical link) ex) USB2 : 480Mb/s(a) (b) Figure 1-4 High data-rate transmission with (a) a conventional parallel bus (b) a serial link. Since a serial link uses a very high frequency cl ock compared to a parallel bus system, the signal quality gets more influenced from the limit ation of the data bandwid th due to the loss of high frequency energy in the band-limited channe l which has normally a low-pass characteristic as investigated before. Therefore, it remains a challenging problem in the high-speed serial link communications as to how to compensate the high-frequency energy of the signal and recover

PAGE 19

19 the transmitted data at the receiver, includi ng clock and data recovery (CDR) using the transmitted signal. 1.2 Compensation Techniques of High Frequency Signal 1.2.1 Pre-Emphasis Signal There are two primary approaches to impr oving high speed data link limitation over the low-cost channel. First is a direct compensati on of the signals high frequency component during transmission and reception. Pre-emphasis of th e PAM-4 transmitted signal with an equalizer implemented by a multi-tap finite impulse response (FIR) filter has been demonstrated in [3-4]. The equalization distorts the transmitted signa l by giving the signal high frequency energy, hence, the signal arriving at the receiver-end has more power compared to the non pre-emphasis signal, which are shown in Figure 1-5. However, it is still challenging to implement the equalizer in the GHz range with CMOS technology [5]. Pre-emphasis Signal Received Signal Received Signal without pre-emphasis Figure 1-5 Pre-emphasis of NRZ signal and re ceived signal with/without pre-emphasis. Figure 1-6 depicts the pre-emphasis in the fr equency domain. The band-limited channel is characterized as a low-pass characteristic as disc ussed in the previous section. The FIR filter for

PAGE 20

20 the pre-emphasis of the signal should have a high -pass characteristic to compensate the energy of high-frequency signal which will be attenuated more than th e lower frequency signal energy. However, this technique is very challenging in GHz range with CMOS technology as well as requires high speed sampling DAC, ADC for th e PAM-4 signal, which increase the system complexities [3-4]. +Channel Equalizing Received Signal Transmitted Signal +Channel Equalizing Received Signal Transmitted Signal Figure 1-6 Frequency domain representation of the pre-emphasis technique of the transmitted signal. 1.2.2 Broadband Circuit Technique Besides the direct compensation of high frequency components, broadband circuit techniques to broaden the limitation of the operation frequency of the circuit, such as an inductor peaking, capacitive degeneration, a Cherry-Hooper limiting amplifier, and a fT doubling, can be classified as compensation techniques of the high frequency signal [6]. Inductive peaking is one of the broadband techniques widely used to increase the bandwidth of the amplifier. However, a passive i nductor integrated in chip occupies a large chip area. An active inductor implemented by an active device such as a MOS can be used to save the

PAGE 21

21 chip area. Detailed active induc tor analysis is presented in [6]. Figure 1-7 shows the active inductor implemented with a PMOS device and its equivalent models. M1 VDD RS Zout R1R2 Zout L RS CGS IXVX + + V1 Figure 1-7 Active inductor (a) r ealized with NMOS source follower (b) small signal equivalent circuit (c) simplified model [6]. The small-signal equivalent circuit is obtained as (1-1), (1-2), and the impedance of the output node is derived as (1-3). j CGSV1 + gmV1 = -IX (1-1) j CGSV1RS + V1 = -VX (1-2) GS m S GS outC j g R C j Z 1 (1-3) Note that if RS >> 1/gm, absolute value of the Zout is increasing with frequency, which behaves like an inductor and is modeled as depicted in Figure 5-1(c) where R1= RS 1/gm, R2 = 1/gm. Then the value of the inductor, L is obtained as (1-4). m S m GSg R g C L 1 (1-4) To get a high quality (Q) factor of the activ e inductor, we must maximize R1 and minimize R2. Since the Q of the parallel combination of R1 and L is represented by R1/ L and R1/L = gm/CGS, Rs does not affect the Q f actor significantly. However, the active inductor mainly suffers from its voltage headroom for the opera tion. To relieve voltage headroom, a modified

PAGE 22

22 active inductor with NMOS has been develope d; however, the achievable bandwidth of the circuit is limited compared to those using a passive inductor. Other broadband techniques such as a capacitive degeneration, a Cherry-Hooper limiting amplifier, are studied well in [6]. 1.3 Modulation Techniques 1.3.1 Conventional Modulation Techniques Pulse amplitude modulation (PAM) -strictly ba seband PAMsignal is most often used in high-speed data communications, such as a serial link communication because it is easy to define its level of 1 or and implement with a simple digital circuit. However, it needs a relatively large bandwidth requirement for the data transm ission. For high-speed seri al link over the bandlimited channel, it is important to reduce the bandwidth requirement of the transmitted signal because the channel has low-pass ch aracteristics, as discussed in the previous section. MultiPAM (e.g. 4-PAM) which reduces signal bandwidth requirement has been introduced and demonstrated to increase the data-rate [3]. Duobi nary, which is characterized as a 3-level PAM, has also been introduced [7]. However, in these multi-PAMs, it is difficult to maintain the linear spacing between levels in low-voltage and low-pow er application and as a result the systems performances are degraded. The level spacing al so causes complexity in the transceiver design not only because the received signal needs to be linearly amplified but also because the multiPAM signal requires accura te reference voltages. Second is a modulation technique that reduces the transmitted bandwidth signal, such as multi-level pulse-amplitude modulation (PAM). Four-level PAM (known as PAM-4) signaling for serial links using CMOS technology has been proposed and demonstrated over the bandlimited channels [3], [8]. Obvious ly, the PAM-4 data rate is doubl e that of a non-return-to-zero (NRZ) with the same bandwidth signal because the former uses four-levels instead of two-levels.

PAGE 23

23 Figure 1-8 shows the signal spectrums of baseband PAM-2 and PAM-4. The PAM-4 signal occupies exactly half of the ba ndwidth of PAM-2 signal. However, the multi-level signal reduces the signal energy hence degrading the BER perfor mance. Moreover, electrical limitations of the system such as low supply voltage resulting from device scaling make the system design more difficult. For example, the level spacing of the PAM-M signal is inversel y proportional to (M-1). Therefore the level is much smaller in low volta ge systems, which are vulnerable to noise and also require a more precise ADC for the re liable communications. Recently, duobinary signaling, a 3-level PAM, for the backplane serial link ha s been introduced and demonstrated for serial links applications [9]. The duobina ry signal has only three signal levels which offer higher signal energy than the PAM-4 signal with in the same voltage system. 0 0.5 1 1.5 2 2.5 3 -60 -50 -40 -30 -20 -10 0 10 f/BR (Hz/bit/s)Normalized Power Spectral Density (dB)PAM-2 PAM-4 Figure 1-8 Comparison of PAM2 and PAM-4 signal spectrum.

PAGE 24

24 1.3.2 Modulation Technique Using Half -Symbol-Rate-Carrier (HSRC) On the other hand, a carrier modulation such as a phase-shit-keying (PSK) modulation is difficult to be used in the se rial link data communications because the carrier signal makes baseband data to the passband signal. Figure 19 shows basic digital m odulation schemes using carrier signals. Digital modulation is using an analog carrier signal to modulate the binary digital sequences. The basic digital modulation schemes are depicted in Figure 1-5. Amplitude-shiftkeying (ASK) is the modulation technique that mi xes the baseband binary data with a carrier signal. The carrier signal is ge nerated when the data is high, otherwise the amplitude of the carrier goes zero. Frequency-shif t-keying (FSK) modulation has tw o different frequency carrier signals representing one or zero da ta. Baseband data is used for th e information of the frequency to be generated from the carrier signal generator which will be usually implemented by a voltage controlled oscillator (VCO). Phase-shift-keyi ng modulation uses one carrier frequency signal different from the FSK. The phase of the carrier signal is changed as the baseband data changes. 1 0 01 (a) (b) (c) (d) 1 0 01 (a) (b) (c) (d) Figure 1-9 Basic digital modul ation schemes (a) baseband data (b) ASK (c) FSK (d) PSK.

PAGE 25

25 1.3.2.1 Why Not Carrier Modulation? These carrier modulation techniques shift the sp ectrum of the baseband data to the carrier frequency, as shown in Figure 1-10(a). Usually the carrier frequency is much higher than the baseband data-rate. Applied to the baseband data communications, the carrier modulation shifts the baseband data information to the carrier fre quency so that the require d bandwidth to transfer the baseband information would be increased as shown in Figure 1-10(a). Consequently, it is inevitable to waste the require d bandwidth of the channel w ith this carrier modulation. What happens in the PSK signal if the carri er signal is sub-sym bol-rate? Figure 1-10(b) shows the spectrum where a half-sym bol-rate carrier is used as a carrier modulation signal. Both main lobes of spectrums at positive and ne gative frequency are ove rlapped. The modulated signal is characterized as a pa ssband signal due to th e carrier modulation; however, the spectrum of the signal looks like that of a baseband signal, as depicted in Figure 1-10(b). This signal would be called the pseudo-baseband signal. Quad rature modulation using two orthogonal carrier signals can be defined. With th is quadrature modulation quadra ture PSK (QPSK) technique, the bandwidth requirement of the baseband data can be reduced by half compared to the PSK modulation using a single carrier signal [10]. What if the qua drature modulation uses the HSRC signal? As mentioned earlier, the spectrums are overlapped as shown in Figure 1-10(b) so that the modulation reduces the first-null bandwidth of the spectrum by 25% than that of non-returnzero (NRZ) modulation. My research mainly focuses on a signal modul ation technique to re duce the bandwidth of the transmitted signal. Modulations based on PSK are proposed and analyzed. The conventional PSK type modulations are well-studied in [ 10-11]. The proposed high speed data links signal modulation techniques modulating di gital data with a half-symbol-ra te carrier using phase-shift keying (named as HSRC-PSK).

PAGE 26

26 fc -fc Signal Bandwidth Required Bandwidth fc=1/4Tb Signal Bandwidth Required Bandwidth -fc=-1/4Tb (a) (b) Figure 1-10 Simplified spectrums of carrier modul ation signals (a) using carrier signal higher than data-rate (b) using half -symbol-rate-carrier signal. Like binary phase-shift keyi ng (BPSK) and quadrature phase-shi ft keying (QPSK) used in wireless systems using radio frequency (RF) car riers, this HSRC-PSK mo dulation technique can be extended to quadrature type modulations usin g two orthogonal carrier signals, such as QPSK, offset-QPSK (OQPSK), minimum shift keying (M SK) modulations popularl y used in wireless communications. These quadrature type PSK modulati ons can increase the data rate with nearly equal signal energy [9]. The proposed half-symbol-ra te carrier modulation t echnique is similar to conventional modulation techniques. However, thei r properties are not iden tical and the analysis is given in this report. Effec tively, the half-symbol -rate-carrier modulatio n performs waveform shaping on the data bits when transmitted through band-limited channels. The signal spectrums of proposed modulations are derive d in analytical form and their bit error rate performances are simulated. The results are compared to conventional modulations. The HSRC-OQPSK signaling is especially chos en as a possible modulation candidate for high speed serial links, implemented a nd simulated by TSMC and UMC 0.18um CMOS technology.

PAGE 27

27 CHAPTER 2 HSRC PHASE SHIFT KEYING (PSK) MODULATIONS 2.1 Binary Modulation A binary PSK (BPSK) signal whose sinusoidal carrier amplitude is Ac can be represented by (2-1) where m ( t ) is the binary data signal, Tb is the bit period, fc, is the frequency of carrier, and c is the phase of the carrier [12]. b c c cT t t f A t m t s 0 2 cos ) ( ) ( (2-1) Let us now consider a special case where fc=1/2 Tb (Nyquist bandwidth) and c=/2. With this condition, the BPSK signal can be represented by (2-2). b b cT t t T A t m t s 0 sin ) ( ) ( (2-2) Since the carrier signal fr equency is within the baseband, this modulation is similar to signal waveform shaping rather than modulation. The baseband data are mixed with a carrier whose frequency is the same as one half of the symbol rate, fc=1/2 Ts, where Ts is the symbol period, and Ts= Tb in BPSK. Figure 2-1 shows the concep t of half-symbol-rate-carrier BPSK (HSRC-BPSK) modulation. -1 1 m ( t ) 1 1 s ( t ) 1 1 -1 1 sin (/ Tb) t -1 1 m ( t ) 1 1 -1 1 m ( t ) 1 1 s ( t ) 1 1 -1 1 s ( t ) 1 1 -1 1 sin (/ Tb) t Figure 2-1 HSRC-BPSK modulation: baseband data sequences and modulated signal.

PAGE 28

28 2.2 Quadrature Modulations 2.2.1 HSRC Quadrature PSK (QPSK) Modulation HSRC-QPSK modulation is similar to a conve ntional QPSK modulation. The conventional QPSK signal can be repres ented in (2-3), where mI and mQ are the data sequences in their inphase (I) and the quadrature-phase (Q) components, respectively, and fc is the carrier frequency which is generally larger than the symbol rate. t f t m t f t m t sc Q c I 2 sin ) ( 2 1 2 cos ) ( 2 1 ) ( (2-3) However, for multi-Gb/s data communications (i.e. backplane serial link), it is often unpractical to generate a carrier fr equency higher than the symbol ra te. To address this issue, the HSRC-QPSK modulation is propos ed, as shown in Figure 2-2( a). The HSRC-QPSK signal is obtained by substituting QPSK s carrier frequency, as fc=1/(4 Tb), where Tb is the bit-period, which is the half-symbol-rate-carrier frequency, as shown in (2-4). t T t m t T t m t sb Q b I 2 sin ) ( 2 1 2 cos ) ( 2 1 ) ( (2-4) Since the carrier frequency is lower than the data-rate, the phase of the carrier signal can affect the modulated signals pr operties. Therefore, the phase of the carrier signal is fixed to define this modulation. The theoretical time domain HSRC-QPSK waveforms are shown in Figure 2-2(b). 2.2.2 HSRC Offset QPSK (OQPSK) Modulation The HSRC-OQPSK shares the same architecture as HSRC-QPSK shown in Fig. 2-2(a). Its signal is obtained by staggeri ng (offsetting) I and Q by Tb, as shown in Figure 2-2(c). The HSRC-OQPSK signal can also be defined by (2-3) but using offset sequences of mI and mQ [13].

PAGE 29

29 m ( t ) m1m2m3m4m5m8m6m7 0 2Tb4Tb6Tb8Tb m ( t ) m1m2m3m4m5m8m6m7 0 2Tb4Tb6Tb8Tb t Tb2 cos 2 1 mI( t ) mQ( t ) Serial to Parallel s(t) sI( t ) sQ( t ) m ( t ) t Tb2 sin 2 1 t Tb2 cos 2 1 mI( t ) mQ( t ) Serial to Parallel s(t) sI( t ) sQ( t ) m ( t ) t Tb2 sin 2 1(a)m ( t ) m1m2m3m4m5m8m6m7 0 2Tb4Tb6Tb8Tb m ( t ) m1m2m3m4m5m8m6m7 0 2Tb4Tb6Tb8Tb t Tb2 cos 2 1 mI( t ) mQ( t ) Serial to Parallel s(t) sI( t ) sQ( t ) m ( t ) t Tb2 sin 2 1 t Tb2 cos 2 1 mI( t ) mQ( t ) Serial to Parallel s(t) sI( t ) sQ( t ) m ( t ) t Tb2 sin 2 1m ( t ) m1m2m3m4m5m8m6m7 0 2Tb4Tb6Tb8Tb m ( t ) m1m2m3m4m5m8m6m7 0 2Tb4Tb6Tb8Tb t Tb2 cos 2 1 mI( t ) mQ( t ) Serial to Parallel s(t) sI( t ) sQ( t ) m ( t ) t Tb2 sin 2 1 t Tb2 cos 2 1 mI( t ) mQ( t ) Serial to Parallel s(t) sI( t ) sQ( t ) m ( t ) t Tb2 sin 2 1(a) sI( t ) 0 2Tb4Tb6Tb8Tb sI( t ) 0 2Tb4Tb6Tb8Tb sQ( t ) 0 2Tb4Tb6Tb8Tb sQ( t ) 0 2Tb4Tb6Tb8Tb s ( t ) 0 2Tb4Tb6Tb8Tb s ( t ) 0 2Tb4Tb6Tb8Tb(b) (c) m5m7mI( t ) m30 2Tb4Tb6Tb8Tbm1Tb9Tb3Tb5Tb7Tb mQ( t ) m2m4m6m8 s sI( t ) 0 2Tb4Tb6Tb8Tb sQ( t ) Tb9Tb3Tb5Tb7Tb m5m 0 2Tb4Tb6Tb8Tb mI( t ) m1m3m7 mQ( t ) m2m4m6m80 2Tb4Tb6Tb8Tb s ( t ) s ( t ) Tb9Tb3Tb5Tb7Tb sI( t ) 0 2Tb4Tb6Tb8Tb sI( t ) 0 2Tb4Tb6Tb8Tb sQ( t ) 0 2Tb4Tb6Tb8Tb sQ( t ) 0 2Tb4Tb6Tb8Tb s ( t ) 0 2Tb4Tb6Tb8Tb s ( t ) 0 2Tb4Tb6Tb8Tb(b) (c) m5m7mI( t ) m30 2Tb4Tb6Tb8Tbm1 m5m7mI( t ) m30 2Tb4Tb6Tb8Tbm1Tb9Tb3Tb5Tb7Tb mQ( t ) m2m4m6m8Tb9Tb3Tb5Tb7Tb mQ( t ) m2m4m6m8 s sI( t ) 0 2Tb4Tb6Tb8Tb s sI( t ) 0 2Tb4Tb6Tb8Tb sQ( t ) Tb9Tb3Tb5Tb7Tb sQ( t ) Tb9Tb3Tb5Tb7Tb m5m 0 2Tb4Tb6Tb8Tb mI( t ) m1m3m7 m5m 0 2Tb4Tb6Tb8Tb mI( t ) m1m3m7 mQ( t ) m2m4m6m80 2Tb4Tb6Tb8Tb mQ( t ) m2m4m6m80 2Tb4Tb6Tb8Tb s ( t ) s ( t ) Tb9Tb3Tb5Tb7Tb s ( t ) s ( t ) Tb9Tb3Tb5Tb7Tb Figure 2-2 HSRC-QPSK and OQPSK (a) modu lation scheme, (b) QPSK time domain waveforms, (c) OQPSK time domain waveforms. This is the same as the direct combination of conventional MSKs I/Q channels without the mixing of the carrier frequency. As shown in Fi gure 2-2(c), the combined signal is free from any discrete transitions. If the in-phase signal is at it s peak of either positive or negative value, the quadrature-phase signal is zero at every 2 Tb. On the other hand, if th e quadrature-phase signal is at its peak of either positive or negative va lue, the in-phase sign al is zero at every 2 Tb. Therefore, the combined signal has no discrete transitions.

PAGE 30

30 2.2.3 HSRC Minimum Shift Keying (MSK) Modulation The HSRC-MSK modulation can be obtaine d by applying the HS RC signal to the conventional MSK modulation format as described in (2-5) and shown in Fig. 2-3(a). As shown in Fig. 2-3(b), the data sequences of I/Q channels are the same as those of the OQPSK as well as the proposed HSRC-OQPSK. The resulting HSRCMSK time domain data sequences are the same as the original data sequences. t T t m t T t m t sb Q b I 2 sin ) ( 2 cos ) ( ) (2 2 (2-5) sI( t ) 0 2Tb4Tb6Tb8Tb sQ( t ) Tb3Tb5Tb7Tb9Tb s ( t ) Tb3Tb5Tb7Tb9Tb m4m6mI( t ) m0m20 2Tb4Tb6Tb8Tb mQ( t ) m1m3m5m7Tb3Tb5Tb7Tb9Tb t Tb2 cos t Tb2 sin t Tb2 cos mI( t ) mQ( t ) Serial to Parallel s(t) sI( t ) sQ( t ) m ( t ) t Tb2 sinm ( t ) m0m1m2m3m4m7m5m6 0 2Tb4Tb6Tb8Tb (a) (b) sI( t ) 0 2Tb4Tb6Tb8Tb sI( t ) 0 2Tb4Tb6Tb8Tb sQ( t ) Tb3Tb5Tb7Tb9Tb sQ( t ) Tb3Tb5Tb7Tb9Tb s ( t ) Tb3Tb5Tb7Tb9Tb s ( t ) Tb3Tb5Tb7Tb9Tb m4m6mI( t ) m0m20 2Tb4Tb6Tb8Tb m4m6mI( t ) m0m20 2Tb4Tb6Tb8Tb mQ( t ) m1m3m5m7Tb3Tb5Tb7Tb9Tb mQ( t ) m1m3m5m7Tb3Tb5Tb7Tb9Tb t Tb2 cos t Tb2 sin t Tb2 cos mI( t ) mQ( t ) Serial to Parallel s(t) sI( t ) sQ( t ) m ( t ) t Tb2 sin t Tb2 cos t Tb2 sin t Tb2 cos mI( t ) mQ( t ) Serial to Parallel s(t) sI( t ) sQ( t ) m ( t ) t Tb2 sinm ( t ) m0m1m2m3m4m7m5m6 0 2Tb4Tb6Tb8Tb m ( t ) m0m1m2m3m4m7m5m6 0 2Tb4Tb6Tb8Tb (a) (b) Figure 2-3 HSRC-MSK (a) modulation sc heme (b) time domain waveforms.

PAGE 31

31 The modulated signal described in (2-5) has the same data sequences to those of the original binary data which is shown in Figur e 2-3(a). This is similar to raised-cosine approximation (RCA) signaling [14]. 2.3 Signal Spectrum Since the frequency of the carrier signal is lower than the data-rate, the carrier signal can be effectively considered as a spectral pulse -shaping. The spectral pulse -shaping function of the proposed modulations is derived as shown in (2-6) by applying the similar approach described in [10]. Note that the pulse-shaping function of HSRC-QPSK and HSRC-OQPSK are different, although the pulse-shaping functions of the c onventional QPSK and OQPSK are the same. elsewhere T t T t T t T t T t T t t gb b b b b b; 0 MSK HSRC for 2 0 ; 2 sin OQPSK HSRC for 2 0 ; 2 sin QPSK HSRC for 2 0 ; 4 2 sin2 (2-6) The normalized power spectral densities, S ( f ), are derived by the Four ier transforms of (26), S ( f )=| G ( f )|2/ T where G ( f ) is the Fourier tran sform of any given g ( t ) [10]. Using this equation and combining with trigonometric identities of sin ( x )=( ejxe-jx)/2 j cos ( x )=( ejx+ e-jx)/2, the final forms of S ( f ) can be equated as (2-7). Their plots are shown in Figure 2-4. MSK HSRC ; 4 1 2 2 sin OQPSK HSRC ; 16 1 2 cos 16 QPSK HSRC ; 16 1 2 cos 16 1 82 2 2 2 2 2 2 2 2 2 2 2 b b b b b b b b b b bT f fT fT T T f fT T T f fT T f T f S (2-7)

PAGE 32

32 0 0.5 1 1.5 2 2.5 3 -60 -50 -40 -30 -20 -10 0 10 f/BR (Hz/bit/s)Normalized Power Spectral Density (dB)NRZ (PAM-2) HSRC-MSK HSRC-QPSK HSRC-OQPSK(MSK) Figure 2-4 Normalized power spect ral density for HSRC modulations. The first null point of the HSRC-QPSK and HSRC-OQPSK spectrum are located at 0.75 Tb. Therefore, their first-null bandwidths ar e reduced by 25% compar ed to the first-null bandwidth of the conventional NRZ, alternat ively known as baseband binary pulse-amplitudemodulation (PAM-2). However, the first-null bandwidth of the HSRCMSK is the same as that of the conventional NRZ. For the side lobes, HSRC-OQPSK shares th e same pulse-shaping with the conventional MSK. Therefore, the HSRC-OQPSK power spectral de nsity should also be identical to that of MSK, which is presented in [11]. Al so, they fall off more rapidly (1/ f4) than those of the conventional NRZ (1/ f-2) [11]. The side lobes of the HSRC-MSK fall off even more rapidly (1/ f6) and therefore the high frequency compone nts can be further suppressed [14].

PAGE 33

33 Recent semiconductor technologies scaled down th e transistor size, which results in the reduction of supply voltage. In low voltage ci rcuits, PAM-4 modulati on, that requires linear amplification, is more difficult to maintain the same spacing between levels. The HSRC-OQPSK is expected to have advantages over this because it does not need to space levels. Especially, for the amplifiers to be operating at power saturation, MSK has superi or performance to QPSK [13]. For bandwidth efficiency, th e spectrum of HSRC-OQPSK, which is the same as MSK, contains 99% of the total signal power within the bandwidth, B (1.2/ Tb), while for QPSK and PAM-4, the 99% bandwidth increase to B (8/ Tb) [13], [15]. Therefore, it is expected that the HSRC-OQPSK should have the effective signal spectrum in bandlimited channel, such as backplane serial link. 2.4 Bit Error Rate (BER) Performance The BER performances are characterized usi ng a coherent demodulation with a matched filter in Additive-White-Gaussian-Noise (AWGN) channel for the proposed HSRC modulations are simulated via MATLAB. The HSRC-QPSK signal has only one symbol energy, Es. Therefore, it is expected to follow the same BER performance of the conventional QPSK, as shown in Figure 2-7. s ( t ) Es,t Es,tEs,tEs,tEs,fEs,pEs,pEs,fs ( t ) Es,t Es,tEs,tEs,tEs,fEs,pEs,pEs,f Figure 2-5 Modulated time domain signals of HSRC-OQPSK and its symbol energies. For the HSRC-OQPSK, the BER performance result is different from that of the conventional OQPSK, due to the existence of three different symbol energies namely, Es,t, Es,f,

PAGE 34

34 Es,p. For the case where the quadrature symbols are evenly transmitted, an example of s ( t ) illustrating the three different energies is described in Figure 2-5. The upper sequences are for the I channel while the lower sequences are for the Q channel. The different three symbol energies can be calcu lated by integrating the s quare of the modulated signal ( | s ( t )|2dt ) over a 2 bit-time (2 Tb), as shown in (2-8)~(2-10). Es,t is the symbol energy for the case where only one of the 2 bits transits between its high and low points. This symbol energy is the same as that of the conventional QPSK, Es. Es,f is for the case where both 2 bits remain in its high or low poi nts (remains flat). Finally, Es,p is when the signal peaks by consecutive transitions. Note that the final terms in (2-9), (2-10), Es,f, Es,p are expressed in scalarmultiples of Es,t by kf, kp, respectively. dt T t A EbT b c t s 2 2 0 2 ,4 2 sin (2-8) 2 ; 4 2 sin 2, 2 0 2 f t s f T b c f sk E k dt T t A Eb (2-9) 2 ; 4 2 sin 2, 2 2 2 p t s p T T b c p sk E k dt T t A Eb b (2-10) The average probability of errors of s ( t ) can be calculated using (2-10), where M is the number of different types of sy mbols [10], [12]. As was the case in Figure 2-5, this equation assumes that M symbols are evenly transmitted, where si represents one of M possible symbols of the modulation signal. M i i e i i e es P M s P s P P1| 1 | (2-11)

PAGE 35

35 If we define noise energy to be N the BER can be expressed in terms of energy-persymbol (or bit) to the noise-dens ity ratio of the three energies, as shown in (2-12)~(2-14). Note that in the final terms of (2-13) and (2-14), the noises are scaled to an effective values, so that the signal energies can be considered as a function of Es,t. N E N Es t s, (2-12) f t s t s f f sk N E N E k N E /, (2-13) p t s t s p p sk N E N E k N E /, (2-14) In the AWGN channel, the noise N has a Gaussian distribution with the mean being 0 and the variance being No. Hence, the scaled effective noises of N / kf and N / kp also have Gaussian distributions where the means are 0 and variances are No/ kf 2 and No/ kp 2, respectively. With these parameters, the probability of errors for each symbol can be obtained by integrating the Gaussian distribution functions over the error de cision section as shown in Figure 2-6. Therefore, the BER of HSRC-OQPSK in AWGN channe l can be derived as (2-15), where Eb= Es/2 and xdx x x Q 2 / exp 2 12. 0 0 02 2 4 1 2 2 4 1 2 2 1 N E Q N E Q N E Q Pb b b e (2-15) The 1/2 weight in the first term and the 1/4 in the second and last terms account for the fact that Es,t occurs twice as often as Es,f or Es,p, in an evenly transmitted quadrature symbols. As shown in Figure 2-7, (2-15) fits well with the results obtained from MATLAB.

PAGE 36

36 Nominal Energy Low Energy High Energy sE sE 0 2 22 1 2 N 0 2 22 1 2 N 0 22 1 N 2 22 exp 2 1 sE x x f Es,t/ N Es,p/ N Es,f/ N Figure 2-6 Gaussian distributi on of different energy symbol s for HSRC-OQPSK modulation. The HSRC-MSK also has different BER from th at of the conventiona l MSK, due to its existence of two different symbol energies namely, Es,t,m, Es,f,m. The analysis approach is the same as that of the HSRC-OQPSKs case and the results symbol energies and the BER of HSRCOQPSK are shown in (2-16), (2-1 7), and (2-18), respectively. b c T b b c m t sT A dt T t T t A Eb2 2 2 0 2 2 2 ,2 cos 2 sin (2-16) b c T b b c m f sT A dt T t T t A Eb2 2 2 0 2 2 2 ,2 2 cos 2 sin (2-17) 0 02 3 2 2 1 2 3 4 2 1 N E Q N E Q Pb b e (2-18) The analytical results are compared with t hose obtained from the MATLAB simulation as shown in Figure 2-7. From the results, we observe that the HSRCQPSK modulation has no degradation of BER performance as compared to the conventional QPSK, which has almost the

PAGE 37

37 same BER performance as that of the NRZ modu lation. Therefore, HSRC-QPSK can be used as a modulation technique for high-speed broa dband communications with less bandwidth requirement while keeping similar BER perfor mance of NRZ. On the other hand, the HSRCOQPSK and HSRC-MSK modulations have less BER performan ces but having even more efficient signal spectrum characteristics as described in the previous section. 0 5 10 15 20 10-6 10-5 10-4 10-3 10-2 10-1 100 Eb/N0 (dB)BER Theoretical QPSK Theoretical HSRC-MSK Theoretical HSRC-OQPSK Simulated HSRC-QPSK Simulated HSRC-MSK Simulated HSRC-OQPSK Figure 2-7 Comparison of theoretical and simu lated BER performance of HSRC modulations. The BER performances of the proposed HSRC PSKs are calculated by demodulation with the matched filer. Generally, the demodulation with a matched filter enables the system to have the best performance. However, a different re sult is obtained in the HSRC-OQPSK modulation. Figure 2-8 shows demodulation process of I (or Q) channel at the HSRC-OQPSK receiver which is presented in Chapter 4 in detail and the de modulated peak signal of the HSRC-OQPSK, which has a low symbol energy, Es,p. The carrier signals are mixed w ith the incoming signals, as shown in Figure 2-8. The demodulated signal s at the first half bit time and the last half bit time periods

PAGE 38

38 have negative values while the signal at the mi ddle bit time period is po sitive. Therefore, the integration of the demodulated HS RC-OQPSK signal over the period of 2 Tb is less than that over the period of Tb, as shown in Figure 2-8. + Bit Period ( Tb) Symbol Period (2 Tb) (a) (b) Carrier Signal Input Signal Figure 2-8 The demodulated signal (a) demodul ation process of I (or Q) channel (b) demodulated peak signal ( Es,p) of the HSRC-OQPSK. Since a matched filter is not used in the actual realization of the receiver (the level decision is made by a clocked flip-flop (FF)) which is disc ussed in Chapter 4, the integrated value of the demodulated signal over the period of Tb produce more realistic BER performance. The signal energy is calculated as (2-19). 2 1 ; 2 sin 4 2 cos 2 2' 2 2 p t s p T T b b c p sk E k dt T t T t A Eb b (2-19) Since the BER performance of the HSRC-OQ PSK modulation is mainly determined by third term of (2-15), the BER perf ormance with the symbol energies of (2-19) can be represented as (2-20) approximately.

PAGE 39

39 02 2 1 4 1 N E Q Pb e (2-20) Figure 2-9 shows the theoretical BER performa nce using symbol energies of (2-19) and simulated BER performance. From the simu lation results, the difference of the BER performances between the theoretical PAM-2 (NRZ) and the HSRC-OQPSK is approximately 4dB instead of 8dB (shown in Figure 2-7). The di fference between the theoretical and simulated BER performance is caused the noise amount integrated during the bit time period is, Tb, is different from the total noise in troduced in the AWGN channel. A lthough, the absolute values of the BER performance using an AWGN channel would be different from that using a bandlimited channel, the difference of the BER perf ormance is comparable to those in the bandlimited channel. 0 5 10 15 20 10-6 10-5 10-4 10-3 10-2 10-1 100 Eb/N0 (dB)BER Theoretical PAM-2 (NRZ) Theoretical HSRC-OQPSK (Tb time integration) Theoretical HSRC-OQPSK (2Tb time integration) Simulated HSRC-OQPSK (Tb time integration) Figure 2-9 Comparison of the BER performance be tween the symbol time (matched filter) and the bit time integration of HSRC-OQPK signal.

PAGE 40

40 To estimate the BER performance in the band-limited channel, a simple low-pass filter having one pole, which is character izing a band-limited channel, is added to the channel. The transfer function is (2-21) and Figure 2-10 shows the frequency response of (2-21). The characterized channel is comparable to the band-limited channel which has the loss of 0.75dB/GHz approximately. 10 1010 3 10 3 ) ( s s H (2-21) 0 2 4 6 8 10 12 14 16 -12 -10 -8 -6 -4 -2 0 Frequency (GHz)H(s) (dB) Figure 2-10 Frequency response of the band-limited channel mode led with a one pole low-pass filter. Figure 2-11 shows the simulated results of th e 10Gbps system. Approximately, 5dB more signal power is needed with the band-limited ch annel modeled as (2-21) to get the same BER performance, which is caused energy loss of the transmitted signal in the band-limited channel modeled as (2-21). From the frequency response depicted in Figure 2-10, 5GHz signals which is comparable to 10Gbps data rate are losing th eir energy of 4dB by the band-limited channel.

PAGE 41

41 However, the difference (4dB) of th e signal to noise ratio per bit ( Eb/ N0) between the NRZ and the HSRC-OQPSK is almost the same as the simulation result without the band-limited channel. If the signal power is en ough compared to noise introduced in the channel, the energy loss of the signal in the band-limited channel mainly dete rmines the BER performance of the system. 0 5 10 15 20 10-5 10-4 10-3 10-2 10-1 100 Eb/N0 (dB)BERSimulated PAM-2 (NRZ) Simulated HSRC-OQPSK Figure 2-11 Comparison of simulated BER pe rformance of the PAM-2 (NRZ) and HSRCOQPSK modulation with band-limited channel. 2.5 DC-Free Signaling Based on HSRC-OQPSK Modulation The ac coupled interconnect gi ves several advantages over the dc coupled interconnect. First, the ac coupled channel would provide more flexible interconnectio n between the various signal standards [16]. Second, the ac coupled in terconnect allows high density and low-power chip-to-chip communication. Recently, an ac couple d interconnect (ACCI) for the chip-to-chip communication has been introduced and its perf ormance demonstrated [17]. It enables low power properties as well as hi gh density I/Os. Moreover, an on-chip capacitor formed under pad

PAGE 42

42 blocks the dc levels of the signal line which allows communi cation between the chips using a different voltage level. However, capacitive coupling interconnect su ffers from the zero wander effect [16]. The capacitiv e coupling characterized as a hi gh pass filter tends to cut off the dc or low frequency information. However, it is very difficult to compensate the loss of the signal where an ac coupled interconnect is used in a long line channel, such as a high-speed serial links because both low and high freque ncy signal information should be compensated due to the high frequency signal loss in the channel being characterized as a low pass filter. Therefore, a modulation technique that removes the dc or low frequency component seems to be more effective in this long line channel commun ication to relieve this zero wander problem effectively. This section investigates a modulation techni que that removes the dc component in the signal, which is relied on half-symbol-ratecarrier offset QPSK (HSRC-OQPSK) modulation. The proposed dc-free signaling can not only remo ve the dc and low frequency components but also maintain the (first-null) bandwidth of non-re turn-to-zero (NRZ) signal which is use in data communication of the most conventional digital systems. In telecommunications, the transmitted data are often encoded with 8B/10B [18] that co nverts 8-bit symbols to 10-bit symbols for proper dc balance to guarantee clock a nd data recovery (CDR) operation at the receiver. This encoding scheme will increase the transmitted data ba ndwidth by 20%. However, the 8B/10B encoding might not be necessary for this modulation b ecause the modulated signal includes the carrier signal and no dc components. Consequently, this dc-free signaling will decrease the required bandwidth by 20% effectively. As analyzed in section 2.4, approximately 4dB more signal to noise ratio per bit is requir ed to get the same BER perf ormance of the NRZ modulation.

PAGE 43

43 Decreasing data-rate by half, TB=2 Tb, with maintaining data offset of Tb of (2-4), we can get another modulation which can be characterized as a half bit time, TB/2, offset QPSK using a quadrature symbol-rate-carrier (H RC) signal. The signal can be obtained as (2-22) simply by substituting 2 Tb= TB of (2-4). Figure 2-12 shows the modulation scheme and its time domain waveforms. t T t m t T t m t sB Q B I sin ) ( 2 1 cos ) ( 2 1 ) ( (2-22) (a) (b) 0 mI( t ) 2TB4TB6TB8TB m1 m3m5m70.5TB( =Tb) 2.5TB6.5TB4.5TB 8.5TB mQ( t ) m2m4 m6m8sI( t ) 0 2TB4TB6TB8TB0 0.5TB2.5TB4.5TB6.5TB sQ( t ) 8.5TB s ( t ) 0.5TB2.5TB4.5Tb6.5Tb8.5Tb 0 0 2TBm ( t ) m1m2m3 m4m5m6 m7m8 Serial to Parallel 1 t TBcos22 mI( t ) mQ( t ) sQ( t ) sI( t ) s ( t ) 4TB6TB8TB T t sin2 12B(a) (b) 0 mI( t ) 2TB4TB6TB8TB m1 m3m5m7 0 mI( t ) 2TB4TB6TB8TB m1 m3m5m70.5TB( =Tb) 2.5TB6.5TB4.5TB 8.5TB mQ( t ) m2m4 m6m80.5TB( =Tb) 2.5TB6.5TB4.5TB 8.5TB mQ( t ) m2m4 m6m8sI( t ) 0 2TB4TB6TB8TB0 sI( t ) 0 2TB4TB6TB8TB0 0.5TB2.5TB4.5TB6.5TB sQ( t ) 8.5TB 0.5TB2.5TB4.5TB6.5TB sQ( t ) 8.5TB s ( t ) 0.5TB2.5TB4.5Tb6.5Tb8.5Tb s ( t ) 0.5TB2.5TB4.5Tb6.5Tb8.5Tb 0 0 2TBm ( t ) m1m2m3 m4m5m6 m7m8 Serial to Parallel 1 t TBcos22 mI( t ) mQ( t ) sQ( t ) sI( t ) s ( t ) 4TB6TB8TB T t sin2 12B 0 0 2TBm ( t ) m1m2m3 m4m5m6 m7m8 Serial to Parallel 1 t TBcos22 1 t TBcos22 mI( t ) mQ( t ) sQ( t ) sI( t ) s ( t ) 4TB6TB8TB T t sin2 12B T t sin2 12B Figure 2-12 DC-free modulation based on HSRC -OQPSK (a) modulation scheme (b) timedomain waveforms. Unlike conventional OQPSK modul ation, data offset of the dc-free modulation using SRC signal is half bit time not 1-b it time as shown in Figure 2-10. As shown in Fig 1(b), there are no discrete transitions in the signal like HSRC-OQPSK, from which we can expect the side lobes of

PAGE 44

44 the signal spectrum to be suppre ssed like those of MSK. The pulse shaping function of the signal can be represented as (2-23). elsewhere T t T t t gB B0 2 0 sin (2-23) The normalized power spectral density, S( f ), is derived by the Four ier transform of (2-23), S ( f ) =|G ( f )|2/ T where G( f ) is the Fourier transfor m of g(t). The resulting power spectral density is represented as (2-24). 2 2 2 24 1 2 sin 4 B B BT f fT T f S (2-24) Figure 2-13 shows the theoretical spectrums of NRZ and dc-free signals. The first null point of the spectrum of the dc-free signal is located at fB=1/ TB, which is the same as that of the conventional NRZ. 0 0.5 1 1.5 2 2.5 3 -60 -50 -40 -30 -20 -10 0 10 f/BR (Hz/bit/s)Normalized Power Spectral Density (dB)NRZ dc-free Figure 2-13 Comparison of the spectra be tween NRZ and the dc-free signals.

PAGE 45

45 The carrier signal moves the dc information of the data to the other frequency range without increasing bandwidth of the signal transm itted. Moreover, the side lobes of the dc-free modulation fall off more rapidly (1/ f4) than conventional NRZ (1/ f-2). 2.5 Measurement of the HSRC-OQPSK Signal A prototype HSRC-OQPSK transmitter was bui lt and tested because the HSRC-OQPSK is the most feasible modulation to be implemented for high-speed wire-line data communications, such as a backplane serial link. The block diagram of the transmitter with test setup is shown in Figure 2-14. CK I DataI/Q ModulatorSpectrum Analyzer Bit Pattern Generator 500MHz Clock Signal Generator 90o 90 Power Splitter 180 Power Splitter 180 Power Splitter 180o 180o Oscilloscope Branch Line5MHz Pulse Function Generator Power Combiner Q Data M1 M2 M3 External Clock In1GHz Clock 1Gbps Data Frequency Doubling Figure 2-14 A prototype HSRC-OQPSK transmitter and measurement setup. Two wide-band mixers, with a bandwidth of 50~4200MHz, are used as I/Q channel mixers. A 500MHz quadrature branch-line hybrid pow er splitter which is constructed with PCB is used to generate quadrature carrier signals. Figure 2-15 shows the structure of the branch-line hybrid power splitter. The port2 and port3 received the signal pow er split equally from port1 with a phase offset of 90 Of course, the symmetrical S-parame ter characteristic can be observed

PAGE 46

46 due to the symmetric structure. The characterist ics of S-parameters are simulated with Ansoft HFSS and compared to the measured data in term s of their magnitude and phase information, as shown in Figure 2-16. The splitter can be integrated into a single chip usin g the passive elements approach [19]. Figure 2-15 A 500MHz branch-line hybrid quadr ature power splitter structure for HFSS simulation. 200 300 400 500 600 700 800 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 Frequency (MHz)Magnitude (dB) S12 S13 S23 Simulated S12 Simulated S13 Simulated S23 Measured S12 Measured S13 Measured S23 (a) Figure 2-16 Simulated and measured characte ristics of the 500MHz branch-line hybrid quadrature power splitter (a) S-parameters (b) phases.

PAGE 47

47 200 300 400 500 600 700 800 0 30 60 90 120 150 Frequency (MHz)Phase Difference (degree)Simulated Measured (b) Figure 2-16 (continued). The two quadrature output signals are split ag ain by using 180 power splitters. The 0 signals of the 180 power splitter s are used for the quadrature car riers while the 180 signals are fed into the mixer M3 to generate a 1GHz cloc k signal for the digital bit pattern generators external clock. The bit pattern generator generates 1Gbps pseudo random data for the transmitters I channel. The HSRC-OQPSK modula tion requires a serial-to-parallel conversion with 1-bit time offset. To simplify the test, a 5MHz pulse is injected into the Q channel input to represent fixed-pattern data bits. Time delay fr om the bit pattern generator is adjusted to synchronize the I channel data and the carrier si gnal. Consequently, the overall transmitter data rate is equivalent to 2Gbps. Agilent N4906A 3.6Gbps serial Bi t Error Rate Tester (BERT) is used to generate 1Gbps pseudo random data. Agilent 54832D 4Gsa/s oscilloscope and Agilent E4448A spectrum analyzer are used to monitor the time do main waveforms and output signal spectrum, respectively. Table I summarizes the co mponents used in the measurement.

PAGE 48

48 Table 2-1 Summary of component s used in the measurement. Device Function Model Frequency Range Mixer (M1, M2) I/Q channel mixer Mini-Circuits ZX05-42MH-S 5 ~ 4200MHz Mixer (M3) Frequency Doubler Mi ni-Circuits ZX05-30W 300 ~ 4000MHz 90 Power Splitter Dividing I/Q channel carrier Quadrature Hybrid (Branch Line) 500MHz 180 Power Splitter Frequency double Mi ni-Circuits ZFSCJ-2-4 50 ~ 1000MHz Power Combiner/Divider I/Q channel signal combine Agilent 11636A DC ~ 18GHz Signal Generator 500MHz carrier sour ce Agilent E8254A 250KHz ~ 40GHz Function Generator 5MHz pulse for Q channel Agilent 33120A 15MHz BERT 1Gbps I channel data Agilent N4906A 3.6Gbps Serial BERT Oscilloscope Monitoring time domain waveform Agilent 548320 1GHz / 4Gsa/s Spectrum Analyzer Monitoring signal spectrum Agilent E4448A 3Hz ~ 50GHz Figure 2-17 shows the measured HSRC-OQPSK time domain waveform and its spectrum. Since the HSRC-OQPSK signal follows the MSK si gnal spectrum, the first null point of the spectrum must be located at 1.5GHz because the equivalent data rate is 2Gbps. Time domain waveform is also well-matched with the th eoretical waveform shown in Figure 2-2(c). Both time domain waveforms and frequency domain spectrum were measured and compared to the theoretical predictions. Fi gure 2-18 shows the measured HSRC-OQPSK time domain waveform and the theoretical prediction. For comparison purposes, a fixed pattern of sequ ences was used for the data pattern instead of random bit patterns. Therefore, the data sequence of the I channel is Measured waveform matches well with the theoretical waveform as shown in

PAGE 49

49 Figure 2-12. A phase mismatch between the data and the carrier signal caused the difference in waveform. 100mV/div 2ns/div 100mV/div 2ns/div (a) (b) Figure 2-17 Measured characte ristics of the HSRC-OQPSK m odulation (equivalent 2Gbps random data input) (a) time domain waveform (b) spectrum. Random data sequences were fed into the I channel to measure the signal spectrum. As shown in Figure 2-19, the measured broadband spect rum matches very well with the theoretical spectrum of a 2Gbps random bit stream. The spectr ums first null is located at 1.5GHz which is

PAGE 50

50 the same as the theoretical value. Other null point s match the theoretical predictions as well. The difference between the measured spectrums main lobe and second lobe is approximately 23dB, which agrees with the theoretical value. 10 15 20 25 30 35 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 Time (ns)Amplitude (V)Theoretical Waveform Measured Waveform Figure 2-18 Comparison of the theoretical and measured waveforms of HSRC-OQPSK modulation. 0 1 2 3 4 5 -90 -80 -70 -60 -50 -40 -30 -20 -10 Frequency (GHz)Power Spectral Density (dBm) Theoretical Spectrum 23dB Figure 2-19 Comparison of the measured and theo retical spectrum of the HSRC-OQPSK signal.

PAGE 51

51 2.6 Summary The HSRC-PSK modulations are proposed to optimize spectral efficiency for high datarate transmission over band-limited channels. The analysis and simulation results show that the proposed modulations can be used in high-spee d data communications, such as a backplane serial link. In the past, a multi-PAM signal (e.g., PAM-4) has been demonstrated to increase the datarate in band-limited channels [3]. However, in PA M-4 modulation, it is difficult to maintain the linear spacing between levels in low-voltage a nd low-power application and as a result the systems performances are degraded. The level sp acing also causes complexity in the transceiver design not only because the received signal needs to be linearly amplified but also because PAM4 signaling requires accurate reference voltages. The proposed HSRC modulations not only reduced the bandwidt h requirement but also can be easily implemented in deep submicron inte grated circuit technol ogies with low supply voltages. The proposed HSRC-QPSK signal has irre gular timing transitions and therefore a new phase detector design for clock and data recovery (CDR) and a matched filter for the demodulation are required. On the other hand, sin ce such irregular transi tion does not exist in HSRC-OQPSK, the HSRC-OQPSK signa ling can be used effectivel y in band-limited wire-line applications with maximum spectral efficiency. This modulation might be able to optimize the spectral efficiency for baseband high data rate transmission over band-limited channels. Compared to the conventional NRZ modulation, the proposed modulation greatly reduces the bandwidth requirements. For bandwidth efficien cy, the HSRC-OQPSK spectrum, which is the same as the MSK spectrum, contains 99% of th e total signal power within the bandwidth of B (1.2/ Tb). In comparison, PAM-4 has much larger 99% bandwidth of B (8/ Tb) [13], [15]. Therefore, it is expected that the proposed HSRC-OQPSK modulation should have an efficient

PAGE 52

52 signal spectrum in band-limited channels. And th is spectrum efficiency will reduce the high frequency crosstalk noise between the signal lines which may im prove the performance of the multi-port serial communication links. In a ddition, dc-free signaling based on the HSRC-OQPSK modulation has been introduced. Th e dc-free signaling is expected to have good performance in ac coupled channel applications including a flip-chip ACCI. Measurement results verified that the HSRC-OQPSK modulati on can be effectively used in band-limited wire-line applicatio ns requiring spectral efficiency, such as the backplane serial link. Moreover, because it requires only a twolevel decision, the HSRC-OQPSK transmitter can be implemented in a simpler arch itecture than PAM-4 and is suitable for low-voltage systems. In addition, a QPSK carrier recovery structure can be used for the HSRC-OQPSK modulation which enables flexible design of the receiver which will be discussed in Chapter 4. For the HSRC-MSK modulation, it can greatly mi nimize crosstalk noise compared to the conventional ones, since the high frequenc y components are furt her suppressed [14].

PAGE 53

53 CHAPTER 3 HSRC-OQPSK TRANSMITTER 3.1 Transceiver Architecture 3.1.1 A Conventional Serial Li nk Transceiver Architecture Prior to the HSRC-OQPSK transmitter deta il, the conventional transceiver and a conceptual HSRC-OQPSK transceiver need to be investigated. Conventional quadrature modulation transceiver architectures are investigated in [20-21]. Figure 3-1 shows the simplified transceiver structure of a conventional serial link. The transmitter has a se rializer which converts the parallel data into serial data using a clock generated fr om a phase-locked loop (PLL). An output buffer amplifies the converted serial data for driving a channel. The receiver has a clock and data recovery (CDR) circuit that includes a phase and freque ncy detector (PFD). Besides a CDR, the receiver includes a retimer, and a de serializer. Passing th rough the channel, the transmitted signal is amplified w ith a limiting amplifier allowing th e signal to travel through a CDR. In the CDR circuit, the incoming signal rest ores a clock used as th e clock of the decision circuit. After the decisi on, the data may convert to parallel data by a deserializer. Typically, a reference clock for precise freque ncy detection is also used to avoid false locking conditions, which is not depicted in Figure 3-1. 3.1.2 A Conceptual HSRC-OQPSK Transceiver Architecture Figure 3-2 shows a conceptual HSRC-OQPSK tr ansceiver structure. The signal modulation uses two mixers and one combiner circuit while two mixers, matched filters and decision circuits are used for demodulation. This system architectur e is basically the same as conventional QPSK modulation and demodulation system. The quarter -rate clock and data recovery (CDR) is incorporated with the HSRC-OQPSK receiver becaus e the frequency of the car rier signal is halfsymbol-rate which is comparable to the quarter-data-rate of the system.

PAGE 54

54 nTransmitter LimiterJittered Data PLL CDR F/F n Receiver Phase Detector Low-Pass Filter VCO Data CK Serializer Deserializer Channel nTransmitter LimiterJittered Data PLL CDR F/F n Receiver Phase Detector Low-Pass Filter VCO VCO Data CK Serializer Deserializer Channel Figure 3-1 A simplified conventional tr ansceiver for a serial data link. Though a matched filter for the QPSK signal demodulation improves system performance, it is hard to implement the matched filter operating at giga-hertz frequency range. So, the matched filter should be replaced by other circ uits which allow the high-speed operation. A highspeed flip-flop (F/F), and appropriate retiming circuit for the incoming data can replace the matched filter. The detailed transmitter architecture is discussed in this chapter and the detail receiver architecture is presented in Chapter 4. Serial to Parallel I Q LO 90 T Q LO 90 T In OutTransmitter Receiver I dt dt Parallel to Serial Quarter-Rate CDR Quarter-Rate CDR Rx Out Tx In Channel ChannelLinear Amplifier Serial to Parallel I Q LO 90 T I Q LO 90 90 T T Q LO 90 90 T T In OutTransmitter Receiver I dt dt dt dt Parallel to Serial Quarter-Rate CDR Quarter-Rate CDR Rx Out Tx In Channel ChannelLinear Amplifier Figure 3-2 A conceptual HSRC-OQ PSK transceiver architecture.

PAGE 55

55 3.2 HSRC-OQPSK Transmitter Architecture Figure 3-3 shows the simplified HSRC-OQPSK tr ansmitter architecture which is basically the same as the conventional OQPSK modulation system architecture. The received data are separated into the I and Q channels with 1 bit-tim e offset by a serial-to-pa rallel logic which is comprised of two double-edge-triggered (DET) F/Fs as shown in Figure 3-3. The separated data are mixed with the quadrature HSRC signals of each channel and then combined by wiring outputs of the I/Q mixers for generating the modu lated signal, as shown in Fig. 2. For the bit error rate (BER) test purposes, the HSRC signal is generated by an injection-locked LC voltage controlled oscillator (VCO) whose injection clock is also used in the clock of the external 2:1 multiplexer (serializer) of the receiver, which will be discussed in Chapter 4. Data InInjection-Locked VCO 90oI Channel Q Channel DET F/F Delay Delay Transmitted Signal Out DET F/F Injection Clock Serial to Parallel with 1-bit offset Figure 3-3 A HSRC-OQPSK transmitter architecture. In this transmitter architecture, the phase synchr onization of the clock and data is crucial to produce an undistorted modulation signal. To maximize the modulated signal spectrum bandwidth efficiency, the data should be synchr onized with the carrier signal of each channel. Synchronization mismatch caused from the clock to data output delay of the DET F/F should be cancelled out by inserting a delay component between the VCO outputs and the mixer inputs, as shown in Figure 3-4(a). Most of the circuits in this transmitter design have been implemented with current mode logic (CML) ci rcuits which are discussed in s ection 3.2.1 in more detail. CML

PAGE 56

56 circuits offer low delay variation due to its s upply independent low-swing voltage characteristic [22]. From the simulation results, the delay va riation is less than 10% of the various supply voltages and processes. Synchronized delay line s or RC delay circuits could be reasonable solutions, as shown in Figure 3-4(a). However, a de lay line for several tens of pico-seconds is a long line to be integrated and makes severe signal attenuation. Rev.1 transmitter implemented TSMC 0.18 m CMOS technology uses a RC delay circ uit for the synchronization. However, delay mismatch might occur because the flip-fl op delay is not fixed over the various voltage, temperature, and process conditions during the operation. In genera l, a buffer as a delay unit can be an effective solution for the compensation of the delay mismatch problem [6]. Rev. 2 transmitter using UMC 0.18 m CMOS technology employs a buffer as a delay unit. Since a delay of the DET F/F is mainly determined by a MUX, a matching delay buffer can be implemented by inserting the same MUX to the signal path, as shown in Figure 3-4(b). The MUX input ports are tied together and the selection port is logically fixed to se lect one of the two inputs. Consequently, equal delays can be inserted in the signal paths. F/F Clock (Sinusoidal) I/Q Data Delayed Data Delay F/F Clock (Sinusoidal) I/Q Data Delayed Data Delay (a) Figure 3-4 A structure of the D ET F/F and data and clock synchr onization by inserting (a) delay unit (b) a MUX as a delay unit.

PAGE 57

57 D Clock (sinusoidal)DET F/F Q Logical 0 or 1 I/Q Channel Signal MUX F/F F/F MUX (b) Figure 3-4 (continued). 3.2 Circuit Implementation 3.2.1 Current-mode-logic (CML) Circuit A fully differential CML type circuit is wi dely used for the lower signal voltage and high-speed digital system. As discussed and analyzed in [22], the CML logic has several advantages over conventional digi tal logic. The logic has supp ly voltage independent output swing. The differential pair with low input and output voltage swi ng offers high-speed operation. Figure 3-5 shows a CML buffer circuit and its ch aracteristic of output voltage versus input voltage. The detailed analysis of the basic differe ntial pair with resistive loads is presented in [23]. The maximum output voltage swi ng is determined by tail current ISS and load resistance RD, which varies VDD to VDD-RDISS as the differential input varies to as shown in Figure 34. The NMOS logic parts are pulled up with load resistors. The minimum and maximum input common mode level which allows M1, M2 to stay in the saturation region is an alyzed in (3-1) [23].

PAGE 58

58 Vin1Vin2 Vout2Vout1 ISSRDRD P VDD (a) VDDVout1Vout2VDD-RDISS RDISS Vin1 Vin2 (b) Figure 3-5 A fully differential (a) CML buffer a nd (b) differential input voltage versus output voltages. DD TH SS D DD CM in GS GS GSV V I R V V V V V 2 min, 3 3 1 (3-1) We have Vout1=VDD-RDID1 and Vout2=VDD-RDID2 and Vout1-Vout2=RD(ID2-ID1). Since the virtual ground node, P, is equal to Vin1VGS1 and Vin2 VGS2, we get equation (3-2). Vin1 Vin2 = VGS1 VGS2 (3-2)

PAGE 59

59 The relationship between VGS and ID is represented as (3-3) fo r a square-law device, where n is the mobility of the NMOS device, Cox is the gate oxide capacitance, W is the device width, and L is the device length. L W C I V Vox n D TH GS2 12 (3-3) Using (3-3), (3-2) can be represented as (3-4). L W C I L W C I V Vox n D ox n D in in 2 1 2 12 2 (3-4) Squaring two sides of (3-4) with the constraints of ID1 + ID2 = ISS, we get (3-5). 2 1 2 2 12 2D D SS ox n in inI I I L W C V V (3-5) Squaring the two sides again and then, we fi nally get the equation which represents the relationship between the out put current difference, ( ID1 ID2), and the input voltage difference, ( Vin1 Vin2), given in (3-6). 2 2 1 2 1 2 14 2 1in in ox n ss in in ox n D DV V L W C I V V L W C I I (3-6) By differentiating the two sides of (3-6), transconductance, Gm is obtained as (3-7) where Vin = ( Vin1 Vin2). 2 24 2 4 2 1in ox n SS in ox n SS ox n in D mV L W C I V L W C I L W C V I G (3-7)

PAGE 60

60 Equation (3-7) implies that Gm drops to zero for L W C I Vox n SS in2 What if Vin exceeds the value which makes Gm to be zero? In this case, one transistor drives the total tail current, ISS, input because the other transistor is approaching the turn-off mode. Thus, ID1 = ISS and Vin1 = VGS1 VTH where L W C I Vox n SS in21 and M2 is turned off for Vin > Vin1. Figure 3-6 shows the relationship between the ID and Vin and the characteristic of Gm. + Vin1GmVin1 Vin (a) (b) Figure 3-6 Characteristics of a differential pair s versus differential input voltage (a) drain currents (b) tran sconductance [19]. As analyzed so far, the differential pair shown in Figure 3-4(a) can be used for a small signal amplifier whose maximum differential input voltage is Vin1. Within Vin1, the differential amplifier could have a high small gain which is dependant on RD and ISS. In case of using it as a digital logic which is called CML, it is better to guarantee Vin > Vin1 for the maximum signal output. Typically, the value of Vin1 does not exceed several-hundred mV for the high-speed operation. Therefore, the differen tial CML logic uses a smaller i nput signal than a conventional logic. Since the differential st ructure cancels the even mode harmonic terms, it is obvious that the differential CML buffer is more linear than conventional CMOS logic and not easily affected by common mode noise, which b ecomes more important in the low-voltage systems. The differential structure gives us a one-stage buf fer while the conventional CMOS needs a two-

PAGE 61

61 stage, greatly reducing the delay of the buffer. Moreover, the characteristics of the CML logic are strongly related to the tail current ISS and use a smaller logic sign al. Delay variation due to voltage, temperature, and process could be very small compared to conventional CMOS logic. 3.2.2 CML Double-Edge Triggered D flip-flop A CML is widely used in high-speed digital logic because its low-swing voltage enables high-speed operation [22], [24]. For this reason, mo st of the circuits used in this transceiver design are CML circuits. A CML DET F/F consists of a CML latch a nd a CML-style analog MUX, as shown in Figure 3-7(a). The basic structur e of the CML DET F/F is the same as a conventional one. Two latches are selected by an analog multiplexer with a clock signal, shown in Figure 3-5(c). Due to its high-speed and low delay variation charac teristics, the CML latch offers good system performance. Input transistors sense and track the input data differen tially and cross-coupled transistors store that data [24]. The clock signa l selects tracking modes and storing modes. The input transistors are tracking the input signal when the clock is hi gh and cross-coupled transistors are storing the input data when the clock signal is low. CLKCLK+ Vout+ VoutVin+ VinRDRD ISSselsel+ Vout+ VoutVin1+ Vin1Vin2RDRDISS Vin2+ (a) (b) Figure 3-7 CML Circuits (a) D-latch (b) analog multiplexer (c) double-edge triggered flip-flop.

PAGE 62

62 MUX D Q D Q Data CLK Out (c) Figure 3-7 (continued). The MUX also can be implemented with CML style digital logic which offers a more flexible interface with CML latches than a conve ntional full-swing high-sp eed logic as well as high-speed operation. The clock signal of the M UX selects one of the latches which stores the previous data, so that the DET F/F can transf er the data when both the rising-edge and the falling-edge clock signals occur. 3.2.3 Resistive Load Gilbert Mixer One major difference between the conventional serial link transmitter and the HSRCOQPSK transmitter is mixing the data with the ca rrier signal using an analog mixer shown in Figure 3-3. I and Q channel mixers generate an an alog signal instead of a digital signal like NRZ. Since the data input encompasses wide-band signals up to several GHz, a wide band mixer should be used in this system. A resistive load Gilbert mixer ha s been chosen for this system because it has wide bandwidth operation. It offers a direct output-to-input interface without any voltage level shifting because it has basically th e same structure as a CML circuit. Moreover, I and Q channel signal combining can be obtained by connecting the outputs of the mixer in the channels, which is discussed in section 3.2.2.5. The load resistor, RD uses the value of 2.5K for both Rev. 1 and Rev.2 transmitter. Figure 3-8 shows a resistive load Gilbert mixer.

PAGE 63

63 Vin1Vin1+ Vout+ VoutVin2+ Vin2Vin2+ RDRDISS Figure 3-8 A resistive load Gilbert mixer. 3.2.4 Quadrature Phase Clock Generator Quadrature-phase carrier signals whose freque ncy is half-symbol-rate are needed for the modulation. This can be simply implemented by us ing a two stage differen tial ring oscillator as shown in Figure 3-9(b). To control the delay of each stage to varying the clock frequency, there are two ways of controlling the propagation delay. One is the current starved approach and the other is the shunt capac itive approach [25]. Figure 3-8 show s the current-starved and the shunt capacitive inverter. In the current-starved inverter, Vctl controls the resistance of M4 through current mirroring. This variable resistance contro ls the charging and discharging timing. In the shunt capacitor invert er, control voltage, Vctl, adjust the resistance of M3 which is connected to the output of the inverter. The other output of M3 is connected to a load ca pacitor. Therefore, the shunt resistance of M3 controls the effective load capacitance seen by the output node of the inverter. Decreasing the resistance of M3, the ef fective load capacitance seen by the output node becomes large, producing more delay. From [25], the shunt capacitance topology has better

PAGE 64

64 linear and noise rejection charac teristics than the cu rrent-starved topology. However, the shunt capacitance topology occupies a larger area due to the lumped capacitor. Vctl Vin M1 M2 M3 M4 Vout M1 Vctl Vin Vout M2 M3 (a) (b) Figure 3-9 Two different de lay control circuit (a) a current-starv ed inverter (b) a shunt capacitive inverter. Figure 3-10 shows fully differential a shunt cap acitive type inverter and two stage ring oscillator. It is common that the fully differential circuit ha s better power supply insensitivity. Each differential inverter has cross-coupled PMOS load and shunt capacitor with a control NMOS. The phase difference of this adjacent node is 90. It is known that LC oscillators allow large ou tput swing at higher frequency with lower voltage and make less phase noise than ring oscillators described in this section do [6]. For these reasons an LC VCO, especially, an injecti on-locked quadrature-phase LC QVCO has been chosen in this work. For the bit-error-rate (BER) test, the HSRC-OQPSK receiver needs an external 2:1 mux for serializing I and Q channe l data, which will be discussed in detail in Chapter 4. To synchronize both the transmitter and the receiver outputs for the BER test, the injected clock signal can also be used as an ex ternal reference clock. Moreover, the injection locked clock signal also helps to overcome failu re in locking the receive rs CDR loop that comes

PAGE 65

65 from the frequency mismatch between the transmitter and the receiver due to the design variation (e.g., process variation). M1 Vin+ + Vout M2 M3 VinVctl M1 M2 M3 (a) Vin+ VinVout+ VoutVctl Vin+ VinVout+ VoutVctl Vctl 90o270o180o0o (b) Figure 3-10 A fully differential (a ) shunt capacitor inverter with cross-coupled PMOS active load and (b) two-stage ring oscillator. An injection-locked LC divider is introduced as a high frequency divider for the phaselocked loop or low-power quadrat ure LO generation [26]. An exte rnal 5GHz clock is injected into the VCO for generating 2.5GHz quadrat ure clock signals by which data modulation performed. Figure 3-8 shows the structure of an injection-locked quadrature phase VCO [26]. The Q of the inductor for the LC tanks is approx imately 8 and its value is 3.8nH. The varactor value is 677fF with a fixed MIM capacitor of 329fF which offers approximately 20% tuning

PAGE 66

66 range with a simulated 2mA tail current. The out puts of each stage are followed by a voltage follower buffer not shown in Figure 3-11. Vinj + VQoutVIoutVcnt VIout+ VQout+ Figure 3-11 Injection-locked LC QVCO. 3.2.5 I/Q Channel Signal Combining The basic architecture of the HSRC-OQPSK transmitter follows that of a QPSK modulator. Therefore, both I and Q channel signals must be combin ed together to generate the HSRC-OQPSK signal. Since the mixer is operated in current mode, a combined signal of the I and Q channels can easily be implemented by wi ring both outputs of the I/Q channel mixers, as shown in Figure 3-12. This makes the transmitter structure simple to implement. 3.2.6 Output Buffer An output buffer of Rev. 1 transmitter has be en designed with an ope n-drain structure as shown in Figure 3-13. The output buffer has a differential three-stag e cascaded structure enabling the output buffer to have enough current to drive the 50 load. The last-stage of the open drain buffer is pulled up with a 50 external resistor for the measurement. The resistor values of each stage, R1, R2 are 550 140 respectively which are implemented with on-chip poly resistors. The DC bias currents, I1, I2 I3, of the buffer are 1.5mA, 6mA, 15mA respectively.

PAGE 67

67 Vin1Vin1+ Vout+ VoutVin2+ Vin2Vin2+ RDRDISS Vin1Vin1+ Vout+ VoutVin2+ Vin2Vin2+ RDRDISS Signal Out + Figure 3-12 Combining I and Q channel si gnal by direct connecting outputs. Vin Vout I1R1R1 I2R2R2 + I3 + Figure 3-13 Three stage output buffer with open drain output stage. The high impedance output of the output buffe r used in Rev.1 transmitter may cause the inter-symbol-interference (ISI) due to the mismat ches [6], [27]. In order to minimize the mismatch between the near-end (transmitter) a nd the far-end (receiver) and improve the signal quality, an on-chip resistor of 60 is used in the Rev. 2 transmitter. Figure 3-10 shows the differential output buffer with an on-chip terminated resistor. A drawback of the double termination is unavoidable increasing power cons umption. It would double the power dissipation in order to deliver the same voltage swing at the receiver end because th e buffer needs twice the tail current compared to the open-drain structure.

PAGE 68

68 For the HSRC-OQPSK signal, lin ear amplification (without li miting output with limiting amplifier [28]) is needed for generating the m odulated signal since the modulated signal should be kept undistorted. Therefore, a buffer is desi gned with the constraints of limited voltage gain and maximum current gain. The resistor valu es of each stage, R1, R2, and R3 are 550 140 and 60 respectively which is implemented with on-chip poly resistors. The DC bias currents, I1, I2, I3, of the buffer are 1.5mA, 6mA, 15mA respectively. The DC coupled output signal is directly interfaced with the inputs with the pull-up of the receiver which enables double termination. The architecture of the transceiver and detail test setup is discussed in Chapter 4. Vin Vout I1R1R1 I2R2R2 + I3 + R3 R3 (a) Transmitter ChannelReceiver+ VinISSRDRD VDD RLRL (b) Figure 3-14 Output buffer (a) di fferential three-stage output buffer (b) doubly terminated structure.

PAGE 69

69 3.3 Chip Design 3.3.1 Rev. 1 Transmitter An integrated HSRC-OQPSK transmitter (Rev. 1) was designed and fabricated using TSMC 0.18um CMOS technology. The chip include s a serial-to-parallel logic, an injectionlocked LC VCO, mixers, and outpu t buffers. Total chip size is 2000 m X 2000 m which includes a transmitter and a receiver. The tr ansmitter core without pads occupies 598 m X 575 m. Figure 3-15 shows the entire HSRC-OQ PSK transceiver chip. The transmitter is located at the lower right corner of the chip. The design includes a transmitter which modulates the binary signal into HSRC-OQPSK signal. The tr ansmitter consists of DET F/Fs, mixers, an injection-locked VCO, and output buffers. Receiver (Demodulator) Transmitter (Modulator) Receiver (Demodulator) Transmitter (Modulator) Figure 3-15 HSRC-OQPSK transcei ver chip using TSMC 0.18 m CMOS technology. The time domain simulation of the Rev. 1 transmitter is performed using Cadence Spectre For the transmitter simulation, a random bit stream in the Cadence adhl library is used for generating 10Gbps random data.

PAGE 70

70 120121122123124125 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 Vout (V)Time (ns) (a) 0 5 10 15 20 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Frequency (GHz)Spectrum (dB) Simulation Theoretical (b) Figure 3-16 HSRC-OQPSK modulati on signal (a) time domain waveforms (b) signal spectrum. A 5GHz reference clock is injected into the transmitter for locking the VCO. The generated 10Gbps serial data fed into the transm itter are separated into I and Q channel data. The clock frequency is half-symbol-rate of the channe l data, therefore, a doubl e-edge triggered flipflop (DETFF) is used as a serial -to-parallel logic for each cha nnel. The simulated time domain

PAGE 71

71 waveforms and their spectrum without an ex ternal load are show n in Figure 3-16. The spectrums first generated signal null is approxim ately 6.7GHz which is a little bit lower than theoretical value of 7.5GHz while the difference between the main lobe and the second lobe is less than 20dB which is higher than the theore tical value of 23dB as shown in Figure 3-16(b). 3.3.2 Rev. 2 Transmitter Rev. 2 transmitter has been designed and fabricated in UMC 0.18um CMOS technology. The chip occupies 1130 m X 1240 m. Figure 3-11 shows a simulation structure for the transmitter. As discussed earlier, the design incl udes a transmitter which modulates the binary signal into the HSRC-OQPSK signal. The transmitter consists of flip-flops, mixers, an injectionlocked VCO, and output buffers. Modulator Logic Varactors Injection-Locked LC VCO DC Blocking Cap. gnd vbmod Din+ DinOut+ OutOsc-Osc+ vbo vboc ckin+ ckinvbILvbvco vcnt gnd gnd gnd gnd gnd vdd vdd vdd vdd vdd Figure 3-17 Transmitter die phot o implemented by UMC 0.18 m CMOS technology.

PAGE 72

72 The power and ground rings made by metal 5 are placed around the chip. To protect circuits, the electrostatic discharges (ESD) circ uits implemented by MOS de vices are attached to the DC bias lines. Octagon shape pads are used for the high speed signal. Pads for output signals depicted as Out+ and Out are placed as close to the modulator logic as possible. The architecture of the injection-locked LC VCO for Rev. 2 transmitter also has the same architecture as shown in Figure 3-11. The Q of the inductor for th e LC tanks is approximately 8 and its value is 3.8nH. The varactor value is 677fF with a fixed metal-insulator-metal (MIM) capacitor of 329fF which offers approximately 20% tuning range with a simulated 2mA tail current. Similarly, the simulation has performed for the Rev.2 transmitter implemented by UMC 0.18 m CMOS technology. The conversion gain a nd input referred 1dB compression point of the mixer are simulated using the Cadence Spectre [29] with the port resistance of 2.5K because a high impedance logic interface, rather than a 50 is employed in the digital system. Up-conversion gain and 1dB gain compression are simulated as shown in Figure 3-7. Conversion gain is less than -1dB if the LO power is larger than -20dBm which roughly corresponds to a single-ende d peak-peak voltage amplitude of 230mV in a 2.5K system. Figure 3-18(b) shows the conversion gain as the input RF frequency increases. For the 4GHz input, the conversion gain is -1.03dB. The input referr ed 1dB compression is -23.08dBm with the port resistance of 2.5K LO frequency of 2.5GHz, RF i nput frequency of 3GHz, and output frequency of 5.5GHz. For the transmitter simulation, a random bit stream in the Cadence adhl library is used for generating 10Gbps random data. A 5GHz reference clock is injected into the transmitter for locking the frequency of VCO. Th e generated 10Gbps serial data fed into the transmitter are

PAGE 73

73 separated into I and Q channel data. The clock fr equency is half-symbol-rate of the channel data, therefore, a double-edge triggered flip-flop (DETFF) is used as a serial-to-parallel logic for each channel. -45-40-35-30-25-20-15-10-505 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 Port Resistance=2.5Kohm RF Input Frequncy=3GHzConversion Gain (dB)LO Power (dBm)1.01.52.02.53.03.54.0 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 LO Power=-10dBm (2.5GHz) (Port Resistance=2.5Kohm)Up-Conversion Gain (dB)RF Input Freqeuncy (GHz) (a) (b) -50-40-30-20-10 -55 -50 -45 -40 -35 -30 -25 -20 Output Freqeuncy=5.5GHz LO Freqeuncy=2.5GHz Port Resistance=2.5Kohm Input Referred 1dB Compression=-23.80dBm Output Power (dBm)Input Power (dBm) (c) Figure 3-18 Linearity simulation of re sistive Gilbert mixer using UMC 0.18 m CMOS technology (a) conversion gain vs. LO pow er, (b) conversion gain vs. RF input frequency, (c) input referred 1dB compression. The time domain simulation of the HRSC-OQP SK transmitter is performed using the Cadence Spectre The simulated time domain waveforms a nd their spectrum w ithout an external load and channel are shown in Figure 3-19. The sp ectrums first generated signal null is 7.5GHz

PAGE 74

74 while the first null point of 10Gbps NRZ data spectrum is 10GHz. The signal spectrum bandwidth is reduced and the si de lobes of the spectrum are gr eatly suppressed as well. The difference between the main-lobe and the second-l obe of the spectrum is more than 20dB, which agrees with the theoretical analysis of the spectrum of HSRC-OQPSK. 101102103104105106 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 Vout (V)Time (ns) (a) (b) Figure 3-19 HSRC-OQPSK modulati on signal (a) time domain waveforms (b) signal spectrum. Figure 3-20 shows that the time domain wave forms of the dc-free signal using HSRCOQPSK transmitter. The spectrums first generated signal null is 5GHz which agrees with the

PAGE 75

75 value of the theoretical spectrum. DC components of the signal have been reduced more than theoretical values because the I and the Q channel data have been correlated every other bit due to the fact that the 2.5Gbps data are being inj ected to I and Q channel simultaneously with just half bit time data offset by se rial-to-parallel logic. However, it is quite well-matched with theoretical values to be considered 5Gbps signa l effectively. The diff erence between the main lobe and the second lobe is appr oximately 20dB while the differen ce is 13dB for the NRZ, which agrees well with the analytical form of the dc-free spectrum derived as (2-21). 50.050.551.051.552.0 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 Amplitude (V)Time (ns) (a) 0 5 10 15 20 -90 -80 -70 -60 -50 -40 -30 -20 Frequency (GHz)Signal Spectrum (dB) Simulation Theoretical (b) Figure 3-20 Simulated dc-free signaling (a) tim e domain waveforms (b) signal spectrum

PAGE 76

76 3.4 Measurement 3.4.1 Rev.1 transmitter Figure 3-12 shows the simplified evaluation boa rd structure and an actual photograph. A chip has attached to the pad on the PCB board using conductive epoxy as shown in Figure 3-20. The pad is connected to the backside ground plan e through via hole. And the signals of the chip are connected directly to th e PCB trace via wire-bond. All the ground pads are down bonded to the pad. Thermal epoxy covers the chip for the pu rpose of protection. Rev. 1 transmitters output buffer structure is open drain, henc e, external chip resistors of 62 are attached to the output signal lines, as shown in Figure 1-13. 110 chip resistors are attached to differential signal lines of data input and in jection clock inputs. Chip Ground Down Bonding PCB FR4 BoardVia Hole Chip Pad Signal Trace Ground Plane Thermal epoxy (encapsulating)Signal wire bonding (a) (b) Figure 3-20 Test board for the Rev. 1 HSRC-OQ PSK transmitter (transceiver) implemented by TSMC 0.18 m CMOS technology.

PAGE 77

77 From the measurement results, the measured frequency tuning range of the VCO is 2.28GHz ~ 2.58GHz, which is approximately 12. 3% from the center frequency 2.43GHz. The center frequency of the VCO has shifted lo wer from the simulated center frequency approximately 2.8%, which is caused from the layout parasitics such as routing metals, which are not considered in the simulati on phase. Figure 3-21 shows the QVCOs signal spectrums for both free-running and injection-locked states. Figure 3-21(a) shows the spectrum of the VCO in the free running state. The center frequency is 2. 5GHz with 5MHz span. Figure 1-14(b) shows the spectrum of the VCO when the 5GHz clock is in jected for the injection-locking of the QVCO. The injection clock signal is generated from th e Agilent E8254A signal generator. The carrier power is measured approximately -5dBm with single-ended output. Howeve r, the carrier power estimated -3dBm if the PCB trace and cable loss ar e taken into account. The characteristic of the noise floor in the injection-locked mode is much lower than that in the free-running mode. (a) Figure 3-21 Measured spectrums and phase noi se of the transmitters QVCO implemented by TSMC 0.18 m CMOS technology (center frequency of 2.5GHz with 5MHz span and 47 KHz RBW) (a) free-running mode (b) inje ction-locked mode (c) comparison of the phase noises between free-runn ing and injection-locked modes.

PAGE 78

78 (b) 10K 100K 1M -160 -140 -120 -100 -80 -60 -40 Frequency Offset (Hz)Phase Noise (dBc)free-running injection-locked (c) Figure 3-21 (continued) The spectrums show that the noise floor ch aracteristic has been improved more than 30dB. The phase noise has been measured by the Ag ilent E4448A spectrum analyzer that offers the phase noise measurement mode. Figure 3-21(c ) shows the phase noise comparison of the two

PAGE 79

79 states which are the free-running a nd the injection-locked state. M easured results show that the phase noise of free-running and injection-locked QVCO signal is -111dBc and -136dBc at 1MHz frequency offset, respectively. Agilent 86100B wideband oscilloscope has been used to get the eye-diagram of the signal. The simplified test setup for 2.5Gbps and 10Gbps BER test are shown in Figure 3-22(a), (b), respectively. Since 2.5Gbps random input is inje cted into both I and Q channel simultaneously, the transmitted signal can be characterized as a 5Gbps signal equivalently even though the data of I and Q channel are correl ated to every other bit. Wideband Oscilloscope CK Data In Transmitter Signal Out ChannelTrigger In 50 O 2.5GHz VCO Signal Spectrum Analyzer Signal Generator VCO Out External Clock In 5GHz Clock 2.5Gbps Trigger Out BERT (a) Wideband Oscilloscope CK Data In Transmitter Signal Out ChannelTrigger In 50OSpectrum Analyzer VCO Out 5GHz Clock 10Gbps Trigger Out 1/2 sub clock BERT Phase Shifter (b) Figure 3-22 Simplified test setups for (a) 2.5G bps (5Gbps equivalent) (b) 10Gbps random input for the transmitter.

PAGE 80

80 For the 2.5Gbps measurement, 5GHz clock signal from the signal generator has been injected to the transmitter for the VCO locking and a half frequency signal generated from the VCO of the chip is fed into the Agilent 4903A BERT for the external clock. Then BERT generated the 2.5Gbps synchronized to the clock inside the chip. 10Gbps test setup is more simple because the 1/2 sub-rate clock from the BERT can be used as an injection clock of the transmitter. Since the sub clock output of the BE RT has the fixed phase with the data output, a phase shifter between the sub clock signal outpu t of the BERT and th e clock input of the transmitter for the timing offset between the input data and the clock. The eye-diagram of the transmitter signal is shown in Figure 3-23. However, the measurement could not get the proper eye-opening of the transmitted signal. Despite the reasonable simulation results, the transmitted sign al suffers from huge jitter components and two eye-openings depicted in Figure 323 have different shapes even in 2.5Gbps data-rate due to the delay mismatch between the data and the clock. The measured eye-diagram of the modulated signal is shown in Figure 3-23. The delay mi smatch is mainly caused from a delay unit composed by a RC. The RC delay unit shown in Figure 3-4(a) does not compensate the delay mismatch effectively because its characteristic va ries much with the temperature and the voltage and the process conditions. ISI noise due to th e reflection of the high impedance node of open drain output buffer could be another reason for this result. For the 10Gbps transmitted signal, jitter components are introduced to the modulated signal, something that is not shown in this dissertation. The eye-diagram of the HSRC-OQPSK signal is diffe rent from that of the NRZ signal. As analyzed in Chapter 2, the low-ener gy symbol signal that practically determines the BER performance also affects the eye-opening size directly.

PAGE 81

81 Two eye-openings in Figure 3-23 are not id entical to each other because the delay mismatch between the clock and the data signa ls. A RC delay unit which is used in Rev. 1 transmitter offers a fixed delay. The limitation of the delay matching comes from the variation of the resistive value due to the pr ocess conditions or the delay vari ations of the F/F over various voltage, temperature, and process conditions. 45mV/div 50ps/div 45mV/div 50ps/div Figure 3-23 Eye-diagram of the HSRC-OQPSK transmitted si gnal implemented by TSMC 0.18 m CMOS technology. 3.4.2 Rev. 2 transmitter Rev. 2 transmitter has been designed and fabricated separately with the receiver. Figure 314 shows a die photo of the transmitt er test board. The chip is atta ched to the chip pad which is also used down bond ground. The signals are conn ected to the PCB signal traces directly via wire-bond. The down bonded grounds are connecte d to the backside ground plane. Thermal epoxy covers the chip for the protection purpose. Surface mount type capacitor of approximately100 F as bypass capacitors are attached be tween the power and the ground as

PAGE 82

82 shown in Figure 3-24. Data and clock input si gnals are terminated with the external 50 resistors. The board has oscill ator signal outputs for the purpo se of monitoring as well as modulated signal outputs. Figure 3-24 Test board for the Rev. 2 transmitter implemented by UMC 0.18 m CMOS technology. Figure 3-25 shows signal spectrum of the Rev. 2 transmitters VCO. The measured tuning range of the VCO is approximately 2.18GHz ~ 2.44GHz, which is representing the tuning range of 12% frequency. The center frequency of th e VCO has been shifted to approximately 10% lower frequency than simulation. It is caused from the parasi tics such as a routing metal capacitance and resistors during the layout, which are not consid ered in the simulation phase. Post-layout simulation with equi valent circuits modeled layout parasitics would improve the mismatch problem. Figure 3-25(a), (b) show the frequency spectrum of the VCO both freerunning and injection-locked states, respectively. As is the case of Rev. 1, we can investigate the noise floor of the spectrum of the injection-locked state that has been lowered than that of the free-running state. The measured phase noise of the VCO is shown in Figure 3-25(c). To measure the phase noise of the VCO, Agilent E4448A spectrum analyzer is used. The phase noise performance of the VCO in the free-runni ng state is approximately -110dBc/Hz at 1MHz

PAGE 83

83 offset, while the -140dBc/Hz at 1MHz offset when the VCO is locked with the injection clock. The phase noise performance of the VCO of the Rev. 2s transmitter is almost the same as that of Rev.1s VCO implemented using TSMC 0.18 m CMOS technology. (a) (b) Figure 3-25 Measured spectrums and phase noi se of the transmitters QVCO implemented by UMC 0.18 m CMOS technology (center frequency of 2.25GHz with 100MHz span and 910 KHz RBW) (a) free-running mode (b ) injection-locked mode (c) comparison of the phase noises between the free-r unning and the injection-locked modes.

PAGE 84

84 10K 100K 1M -160 -140 -120 -100 -80 -60 -40 Offset Frequency (Hz)Phase Noise (dBc) free-running injection-locked (c) Figure 3-25 (continued). Figure 3-26 shows the measured eye-diagram of the transmitted signal where the 2.43Gbps 231-1 pseudo random bit streams (PRBS) are injected into the transmitter that generates 4.86Gbps transmitted signal equivalently. From the m easurement results, the clock and data synchronization using a buffer inse rtion depicted in Figure 3-4 can effectively be working to generate the HSRC-OQPSK modulated signal. Comp ared to Rev.1 transmitter using a RC delay unit for compensating delay mismatch, a clear eye-opening has been obtained. The buffer insertion as a delay unit discu ssed in section 3.2.1 can effec tively make good compensation of the delay mismatch while the RC delay unit used in Rev.1s transmitter did not compensate the delay mismatch effectively. SMA connectors are used to connect the channe ls in the test board shown in Figure 3-24. The characteristic impedance of 50 channel 6.2mil FR-4 PCB board and tangential loss is approximately 0.023. Since the PCB channel has a low-pass characteristic as discussed in

PAGE 85

85 Chapter 1, the detected signal power at the recei ver end drops as the channel length increases. Therefore, the eye-opening is getting smaller as the channel increases and eye-opening would be closed after tracing a long channel. Figure 3-26 shows the measured channel charact eristics used in the measurement. Three different lengths of PCB trace and one SATA of 19 length cable are used to compare the performances. The measured results show that 20 trace has a loss of 13dB at 6GHz while the 5 channel is approximately 3dB. 0 2 4 6 8 10 12 -50 -40 -30 -20 -10 0 10 Frequency (GHz)S21 (dB)PCB-5" PCB-10" PCB-20" SATA-19" Figure 3-26 Characteristics of cha nnels used in the measurement. The measured peak-to-peak small eye-opening of the transmitted signal after tracing 2 PCB trace with a SMA cable is about 300mV without equalization of the signal at the trace end. Peak-to-peak eye-opening of the flat signa l which has the largest symbol energy ( Es,f) is approximately 400mV. The eye-ope ning after tracing the 10 channel is reduced to 150mV. And less than 80mV eye-opening has been obtained af ter 20 trace. Another serial link channel,

PAGE 86

86 serial-ATA (SATA) cable, has been used for this experiment to evaluate the performance of the transmitter. A 19 SATA cable with 2 PCB trace to connected tran smitter is used to obtain the eye-diagram. Figure 3-16(d) shows the eye-diagra m after 19 SATA cable trace. More balanced eye-diagram has been obtained compared to PCB trace because the differential signals are strongly coupled than PCB channels used in the measurement. 60mV/div 50ps/div 60mV/div 50ps/div (a) 60mV/div 50ps/div 60mV/div 50ps/div (b) Figure 3-27 Eye-diagram of HSRC-OQPSK transmitted signal implemented by UMC 0.18 m CMOS technology after (a) 2 PCB trace, (b ) 5 PCB trace, (c) 10 PCB trace, (d) 20 PCB trace, (e) 19 SATA cable, in re sponse to 4.86Gbps (both I and Q channel input with 2.43Gbps pseudo random bit stream (PRBS) sequence of 231-1).

PAGE 87

87 60mV/div 50ps/div 60mV/div 50ps/div (c) 60mV/div 50ps/div 60mV/div 50ps/div (d) 60mV/div 50ps/div 60mV/div 50ps/div (e) Figure 3-27 (continued).

PAGE 88

88 Figure 3-28 shows spectrum of the 4.86Gbps dc -free signal. High frequency components of the signal are suppressed due to the signal loss at the test board and the limitation of the operating frequency of the circuit. However, the nulls at dc and the other frequency of the spectrum are quite well matched with the theoretical values. 0 5 10 15 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Frequency (GHz)Signal Spectrum (dBm) Measurement Theoretical Figure 3-28 Spectrum of 4.86Gbps dc-free signal. Figure 3-29 shows the measured eye-diagram of the HSRC-OQPSK signal in response to 9.72Gbps PRBS sequence of 27-1. The measured eye-diagram shows that the HSRC-OQPSK signal generates the similar eye-diagram shape to that of the duobinary signal [30]. A major difference of the signal eye-diagram between th e HSRC-OQPSK and duobina ry signals is that HSRC-OQPSK has no decision references because it uses only a two-level decision while the duobinary signal needs the two decision level to d ecide the logical value of the signal [9], [3031]. Therefore, it is better for the HSRC-OQ PSK signal to open the si de eye-diagram wide enough depicted with a blue diamond shape (ide al eye-opening). Actually, the HSRC-OQPSK

PAGE 89

89 signal can be obtained based on the duobinary decoding scheme assuming the high frequency components of the signal are fi ltered out at the band-limite d channel. However, every 3rd and 4th bit data should be reversed to get the proper HSRC-OQPSK signal. 60mV/div 20ps/div ideal eye-opening 60mV/div 20ps/div 60mV/div 20ps/div ideal eye-opening (a) 100mV/div 100ps/div 100mV/div 100ps/div (b) Figure 3-29 Eye-diagram of the HSRC-OQPSK transmitted si gnal with 9.72Gbps PRBS sequence of (a) 27-1 (ideal eye-opening is depict ed with blue line), (b) 231-1. As discussed in Chapter 2, the consecutive transition signal whic h has low signal energy makes the diamond shape eye-diagram depicted with a blue line in Figu re 3-29(a). The signals

PAGE 90

90 suffer from severe attenuation of the signal energy as shown in Figure 3-30. The small eyeopening is less than 60mV which is smaller than the simulation results which will affect the BER performance of the transceiver. The BER perf ormance will be discussed in Chapter 4. The attenuation of the signal mainly comes from th e limit of the circuits operating frequency. And the delay mismatch also prevents enlarging the eye-opening of the signal. Broadband circuit techniques such as a fT doubling of the output buffer are need ed to increase the signal quality and maximize the eye-opening. The spectrum shown in Figure 3-27(c) also represents the high frequency attenuation of the signal and there are no side lobes of the signal above 10GHz which are supposed to follow the theoretical spectrum corresponding to the red line. The performance of the HSRC-OQPSK transceiver associated with the transmitter is discussed in Chapter 4. Figure 3-30 Signal spectrum in res ponse to9.72Gbps PRBS sequence of 27-1.

PAGE 91

91 CHAPTER 4 HSRC-OQPSK RECEIVER DESIGN 4.1 Receiver Architecture A conceptual HSRC-OQPSK receiver architectur e which is based on that of a QPSK has been depicted in Figure 3-2. Different from the conventional serial link r eceiver that uses a PAM signal, the HSRC-OQPSK receiver us es a carrier signal which is quarter data-rate frequency for the demodulation. Therefore, a quarter-rate CDR must be incorporated with the receiver. A quarter-rate PD as a CDR for the conventi onal PAM signal has been introduced and demonstrated [32]. The HSRC-OQPSK recei ver (Rev. 1) designed with TSMC 0.18 m CMOS technology uses the same PD arch itecture introduced in [32]. To improve the performance of the pr oposed HSRC-OQPSK r eceiver, a new CDR architecture has been proposed for the Rev. 2 receiver and implemented using UMC 0.18 m CMOS technology. The proposed CDR has been m odified from a Costas loop which is often used for the carrier recovery loop for the BPSK and QPSK signal. The details are discussed in section 4.3. 4.2 HSRC-OQPSK Receiver (Rev. 1) Figure 4-1 shows the HSRC-OQPSK receiver ar chitecture with a quarter-rate CDR. The input buffer amplifies the incoming signal followe d by I and Q channel mixers. As described in the conceptual receiver architecture, the receiver has I and Q channels. I and Q channel mixers are demodulating the received signal using the qu arter data-rate carrier signals recovered by a CDR loop. DET F/Fs followed by I/ Q mixers determine the retimed data of I and Q channels. To recover the clock which is quart er data-rate, a conventional qu arter-rate PD [32] has been adopted for the Rev. 1 receiver. Originally, th e quarter-rate PD has been proposed for the 40Gbps NRZ signal relaxing timing requirements a nd reducing the cost of fabrication [32].

PAGE 92

92 Signal in VCO DET F/F DET F/F 90oI Q e IDataQData LFCICQ Quarter-rate PD Figure 4-1 HSRC-QOPSK receiver (Rev. 1) archite cture incorporated with quarter-rate PD. Figure 4-2(a) shows the phase detector (PD) ar chitecture employed in the Rev. 1 receiver. The PD is introduced in [32]. F/Fs strobe the data by using multi-phase VCO signal and determine the polarity of the phase error by us ing XOR gates. The outputs of two consecutive XOR gates are connected to the differential V/ I converters which determine the phase error. Figure 4-2(b) shows the timing diagram of the PD. (a) (b) Figure 4-2 Quarter-rate phase detector (a) ar chitecture (b) waveforms (for 40Gbps NRZ) [32]. The Rev. 1 receiver has been fabricated with TSMC 0.18 m CMOS technology. The simulated maximum current of the PD in the Rev.1 receiver is approximately 200 A.

PAGE 93

93 In the measurement, however, the PD has failed to appraise the performance of the receiver for the HSRC-OQPSK signal. There might be severa l reasons. First, the transmitter signal itself was not good enough for the receiver due to the limi ted performance of the transmitter. Second, the PD employed in the receiver is originally for the NRZ signal. The PD has the best performance when the signal has a sharp transi tion like the NRZ signal and not like the HSRCOQPSK signal. Since the meta-stable behavior of the F/F will lead to the finite gain of the PD [32], the HSRC-QOPSK signal havi ng no discrete transition like NRZ would increase the metastable behavior in F/Fs. Consequently, the PD gain might be decreased significantly. 4.3 HSRC-OQPSK Receiver (Rev. 2) Figure 4-3 shows the proposed HSRC-OQPSK r eceiver structure. The receiver is based on a Costas loop (often used as a carrier recove ry loop of a conventiona l QPSK demodulator) [3334]. Two mixers separate the in coming modulated signal into the I and Q channel for the signal demodulation. After passing through the mixer, the I/Q channel signals are fed into the DET F/Fs clocked with quarter data-rate frequency carri er signals recovered by the CDR loop. The loop also allows the retimed I/Q channel data. Generall y, a carrier recovery loop as well as a Costas loop has LPFs in order to get rid of the high fr equency components in the I and Q channel path and get the phase error to c ontrol the VCO of the receiver. Unlike a conventional carrier recovery loop, the proposed CDR does not incl ude LPFs. Since the carr ier recovery of the HSRC-OQPSK receiver is basically the same as the symbol synchronization of the QPSK demodulation process, it is expect ed that the proposed CDR loop (algorithm) can be effectively applied for the symbol synchronization loop of the QPSK demodulation as well. The detailed analysis of the proposed rece iver integrated with a CD R loop will be discussed.

PAGE 94

94 Signal InVCO DET F/F PP S/H DET F/F PP S/H 90o LF I Qe+ Is Qs I Data Q Data Figure 4-3 HSRC-OQPSK receiver architec ture incorporated with a CDR. 4.3.1 Polarity-Type Costas Loop for Carrier Synchronization A Costas loop is commonly used as a carrier recovery loop for the QPSK type modulation signal. The Costas loop was first introduced in [35]. A couple of modifi ed Costas loops have been proposed and their performances analyzed in [33-34]. Other structures for the carrier recovery loops for the QPSK signals are introduced and analyzed in [36-41]. Figure 4-4 shows a polarity-type Costas loop fo r the QPSK type signa l proposed in [33]. The polarity-type Costas loop is a kind of hard-limited carrier recovery loop which is known to have a better performance than that of the nonlimited type carrier rec overy loops in a higher signal-to-noise ratio (SNR) situa tion [10], [34]. Input si gnals of the polarity-type Costas loop are mixed with quadrature carriers generated from a quadrature VCO (QVCO) and separated into the I and the Q channel by the mixers. The I/Q chan nel signals pass through low-pass filters (LPFs) to get rid of the hi gh-frequency components which have no significance for generating the control signal. These signals are mixed again with the limited signals from the other channel, as shown in Figure 4-4.

PAGE 95

95 Signal in VCO 90o LPF LPF Loop Filter -1 +1 -1 +1+ Figure 4-4 Polarity-type Costas loop for QPSK signal carrier recovery. In QPSK modulation, the signa l coming into the Costas loop can be defined as (4-1), where S is the average received signal power, mI( t ), mQ( t ) are the data sequences of 1 of I/Q channel, c is the carrier frequency and i is the phase of the signal. i c Q i c It t m t t m S t s cos sin (4-1) The phase error signal contro lling the VCO frequency is ge nerated by subtracting these two signals from each channel. Assume VCO signal has an amplitude of S 1 and a frequency of c, then the low frequency output of the polity -type Costas loop can be represented using trigonometric operations as (4-2), where =i-o, o is the phase of the VCO signal [42]. cos sin sgn sin cos sin cos sgn cos sin 2 1 t m t m t m t m t m t m t m t m t eQ I Q I Q I Q I (4-2) Then the low frequency phase erro r can be rewritten as (4-3).

PAGE 96

96 4 3 4 cos 4 4 sin 4 4 3 cos t e (4-3) 4.3.2 A New Clock and Data Recovery (CDR) based on the Modified Costas Loop Figure 4-5 shows the proposed CDR loop which is basically the same as the HSRCOQPSK receiver structure. Since th e CDR offers retimed data simila r to other CDRs do, it can be used as a receiver. The proposed CDR loop fo r the HSRC-OQPSK modula tion and its analysis and simulation results are presented in this section. Note that the HSRC-OQPSK modulation inheri ts the properties of the QPSK modulation even though its carrier frequency is lower than th e data-rate. Therefore, it is expected that the polarity-type Costas loop shown in Figure 4-4, can be used as a clock (carrier) recovery loop for the HSRC-OQPSK signal. However, there are a couple of limitations in implementing a CDR loop and demodulating the HSRC-OQPSK signal. First, since the data-rate HSRC-OQPSK signal is higher than its carrier frequency, LPFs in I/Q channels selecting low frequency components cannot be used for the phase detector output in the Costas l oop. Second, a coherent demodulation of the QPSK signal with a matched filter consisting of an integrate/dump and a decision circuit is very difficult to implement in the GHz range. Also, a bit-time delay between the I and the Q channel data should be properl y compensated for the phase error detection as well as the demodulation. Conseque ntly, the conventional Costas l oop should be modified for the CDR of HSRC-OQPSK signal. A new CDR loop for HSRC-OQPSK signal modified from the Costas loop is proposed a nd shown in Figure 4-5.

PAGE 97

97 Signal in VCO DET F/F PP S/H DET F/F PP S/H 90o I Qe+ ISQSIFQF LFCICQ Figure 4-5 A modified Costas loop for the HSRC-OQPSK signal clock and data recovery. The modulated signals fed into the CDR are sp lit into the I/Q cha nnels and mixed with quadrature carrier signal genera ted from QVCO. The LPFs shown in Figure 4-2 are removed and the limiters are replaced by DET F/Fs. Sample /hold (S/H) circuits sampling both clock edges hold the signal of each channel by 2 bit-time for the proper evaluation of the phase error. The demodulated signals, I and Q, are sampled by samp le/holds and DET F/Fs. The sampled signals, IS and QF, QS, and IF, are mixed for the final evaluation of the phase error. The sampling time of the I and Q channel are offset by 1 bit-time. Th erefore, the CDR loop evaluates the phase error every 1 bit-time. The details are analyzed and a behavioral model simulation will be presented. 4.3.2.1 Phase detector characteristics The received HSRC-OQPSK signal can be represented as (4-4) [43], where Tb is a bit time and i is an arbitrary phase of the incoming signal. i b Q i b IT t t m T t t m t s 2 cos 2 1 2 sin 2 1 (4-4)

PAGE 98

98 For the QVCO signals of the CDR, they can be assumed as (4-5), where o is the initial phase of the QVCO signals. o b Q o b IT t t c T t t c 2 cos 2 2 sin 2 (4-5) Then I / Q signals can be obtained as (4-6), (4-7) by multiplying two signals represented as (4-4), (4-5) using trigonometric operations. o i o i b Q o i o i b IT t t m T t t m t I sin sin 2 1 cos cos 2 1 (4-6) o i o i b Q o i o i b IT t t m T t t m t Q cos cos 2 1 sin sin 2 1 (4-7) Since the samplings of S/Hs and F/Fs are taki ng place at the zero cros sing points of carrier signals defined in (4-5), one can obtain the sampling time of each channel by setting cI( tQ)= cQ( tI)=0. Therefore, the sampling time for the I/Q channels are defined as (4-8). o b Q o b IT t T t 2 2 1 (4-8) Now, one can define the sampled signals using (4-8). The sampled signals, IS( t ) and QS( t ) shown in Figure 4-3, can be calculated as (4-9), (4 -10) by substituting (4 -8) into (4-6), (4-7) respectively, where =i-o.

PAGE 99

99 sin cos I Q I I St m t m t I (13) cos sin Q Q Q I St m t m t Q (14) Similarly, IF and QF signals can be determined by limiting the sampled signals which are obtained by taking sgn[ Is( tI)], sgn[ Qs( tQ)]. For these signals, the phase difference between the received signal and the carrier signal determines the values of IF and QF. Therefore, IF and QF are represented as (4-11), (4-12), respectively. 4 3 4 4 4 4 4 3 I Q I I I Q I Ft m t m t m t I (4-11) 4 3 4 4 4 4 4 3 Q I Q Q Q I Q Ft m t m t m t Q (4-12) The data sequences of mI and mQ should be specified for determining the phase error, e ( t ). Figure 4-4 illustrates the early and late sample d I/Q channel data when the phase difference, is either positive or negative. When <0, the sampling time is earlier than the ideal sampling time while the sampling time is later th an the ideal sampling time when <0, as shown in Figure 4-6. Consequently, data constraints related to th e phase difference can be stated as (4-13). 0 0 Q I I I Q Q I Qt m t m t m t m (4-13)

PAGE 100

100 mImQmQ( tI) mQ( tQ) mI( tI) mI( tQ) <0 >0 mImQmQ( tI) mQ( tQ) mI( tI) mI( tQ) <0 >0 Figure 4-6 Early and late sampling time of I/Q data. Now, the phase error e ( t ), represented as (4-14), can be estimated. The CDR loop evaluates the phase error every bit-time because the IS( tI) and QF( tQ) or QS( tQ) and IF( tI) are overlapped by a bit time. e ( t )= QS( t ) IF( tI) IS( t ) QF( tQ) (4-14) With the data constraints in (4-13), the phase error, e ( t ), is obtained as (4-15) if it is assumed that the amplitude of the mI, mQ are unity. 4 3 4 cos 1 4 0 sin 1 0 4 sin 1 4 4 3 cos 1 Q I I I Q I I I Q Q I Q Q Q I Qt m t m t m t m t m t m t m t m t e (4-15) Still, the values of mQ( tI)mQ( tQ) when <0 and mI( tI)mI( tQ) when >0 cannot be fixed to finalize e ( t ) because the random data sequences are uncorre lated. The values can be either -1 or 1 which is dependant on the data sequences. The un determined value of -1 or 1 leads to two

PAGE 101

101 possible results of e ( t ). The coefficients of each term of (4-15) will be zero or when the value is -1 or 1, respectively. Then the averaged phase error can be rewritten as (4-16) with the assumptions that I/Q channel data sequences occu r equally likely with symbol time and the phase error process is changing slowly over the large number of sym bol periods. Consequently, the averaged phase error is equivalent to that of the polarity-type Co stas loop. Its plot is shown in Figure 4-7. 4 3 4 cos 4 4 sin 4 4 3 cos t e (4-16) /4 /2 e 3 /4 /4 /2 -3 /4 /4 /2 e 3 /4 /4 /2 -3 /4 Figure 4-7 Averaged phase detector ch aracteristic of the proposed CDR loop. The proposed CDR loop based on the polarity-type Costas loop can be characterized as a linear phase detector, as shown in Figure 4-5. A linear phase dete ctor (PD) generates an error signal linearly proportional to phase error. The output of the PD goes to zero when the loop is locked while a non-linear PD is pumping the charge even with the loop in a locked state. It is known that a linear PD produces lowe r jitter compared to non-linear PD due to less charge pump

PAGE 102

102 activities [44-45]. Therefore, the proposed CDR is expected to generate less cl ock jitter noise compared to non-linear type PD. Moreover, the carrier frequency of the proposed CDR loop for HSRC-OQPSK signal is quarter data-rate, hence, the loop is eq uivalent to quarter-rate CDR for NRZ signal. As a result, the proposed CDR can relax the timing constraints of the receiver system. In addition, the proposed CDR allows retim ed I/Q channel data as shown in Figure 4-1, similar to that of other CDRs [6]. In addi tion, although the proposed CDR has been developed for the clock recovery of the serial link transceive r system, the concept can also be applied to the symbol synchronization of the QPSK signal in wireless communications. One drawback of the proposed CDR is that th ere are four stable locking points over the radian period, only one of whic h has proper phase information. A differential encoding in the transmitter can resolve this four-fold phase ambiguity problem at the cost of 3dB reduced signal power [10]. And, other methods for phase ambiguity resolution ha ve been introduced in [46]. However, this four-fold ambigu ity issue is for future work. 4.3.2.2 Loop analysis The modified Costas loop can be represented by the equivalent model, as shown in Figure 4-8. The Ka is the gain of the combiner, Kv is the VCO gain, and F(S) is the function of the loop filter. Transient response of the loop cannot be characterized easily; however, the loop can be modeled as a linear system with as sumptions that the phase error, changes slowly over a large amount of the symbol period [40]. Assuming no noise is added in th is loop, then the overall tran sfer function of the closed loop is calculated as (4-17). s F K K s s F K K s s s Hv a v a i o (4-17)

PAGE 103

103 VCO Ka F(s) + Kv/s nie 0o 0i O/ Figure 4-8 Equivalent linear mode l of proposed CDR for HSRC-OQPSK. Since the transfer function of the loop filter can affect the overall transfer function of the system, the loop filter should be carefully chosen to stabilize the system. A lead/lag network is widely used as a loop filter because it offers an increased open loop phase margin of the system by inserting zero to the transfer function [6]. The transfer functi on can be rewritten by using the parameters from circuit implementation. Ka=180 A/V is obtained from the circuit simulation and Kv=120MHz/V, as shown in Figure 4-18. A lead/lag network with Rp=7K and Cp=30pF is used for the simulation purpose to reduce the simulation time and the required memory. With these parameters, the closed loop gain of the system is represented as (22). The zero of the closed loop of the transfer function is located at 1/ RpCp. In real design for the measurement, the closed loop bandwidth of 1MHz has been chosen which is examined in a later section. z v a p v a p p z v aC K K s R K K s s C R C K K s H 21 (4-18)

PAGE 104

104 The stability issues of the t ype I and type II PLL are discu ssed thoroughly in [6], [47-48]. The phase margin of the systems open loop tran sfer function is often used to examine the stability of the system shown in Figure 4-7. The characteristics of the open loop transfer function show an approximately 90 phase margin at the gain crossover which will lead to stable locking of the system. 100 102 104 106 108 1010 -100 0 100 200 300 400 Open Loop Gain, |Hopen| (dB) 100 102 104 106 108 1010 -180 -160 -140 -120 -100 -80 Frequency (Hz)Phase, Hopen (deg)-40dB/dec -20dB/dec Figure 4-9 Open loop gain character istics of the proposed CDR loop. 4.3.2.3 Noise characteristics The phase error characteristic, S-curve, which is expressed in terms of signal-to-noise ratio (SNR), can be calculated by averaging the value of the phase error as (419) [33]. Obviously, the loop of the system includes the noise term depicted in Figure 4-6. | t e E g (4-19) As we have discussed in the previous sect ion, the phase error of the proposed CDR loop based on the modified Costas l oop is equivalent to that of the polarity-type Costas loop.

PAGE 105

105 Therefore, the averaged phase er ror of the proposed CDR can also be considered to have the same value as that of the polarity-type Costas loop. Consequently, the phase error characteristic can be represented as the equivalent form as de rived in [33]. The S-curve for the QPSK signal, that is M =4 in [33], is repres ented as (4-20), where R = S /2 N0B S is the signal power, N0 is the Gaussian noise spectral density, B is the noise bandwidth, am= sin [(2 m -1) /4], bm= cos [(2 m 1) /4], and xdx x x Q 2 / exp 2 12. sin cos 2 sin cos 2 cos sin 4 sin 4 1 sin cos 2 sin cos 2 cos sin 4 sin 4 1 ,4 1 4 1 l l l l l l l l l l l l l lb a R Q b a R Q b a b a R Q b a R Q b a R g (4-20) The phase error gain of the CDR loop is dependa nt on the SNR, as shown in Figure 4-8. In low SNR, the S-curve performs like as sin4 [33]. -150 -100 -50 0 50 100 150 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Phase Error (deg)Normalized S-Curve0dB 10dB 20dB 30dBdB Figure 4-10 Phase error charac teristic with SNR (S-curve) of the proposed CDR loop.

PAGE 106

106 The S-curve gives the ability to estimate th e characteristics of the CDR loop when the noise is injected. However, the HSRC-OQPSK si gnal is used as a wide -band signal utilizing a band-limited channel such as a PCB board trace. The band-limited channel having low-pass characteristics may affect the S-curve behaviors. 4.3.3 Behavioral Model Simulations 4.3.3.1 Phase error To verify the functionalities of the propos ed CDR, the proposed CDR is designed by behavioral models using MATLAB Simulink. A transmitter generating the HSRC-OQPSK signal is also modeled, as shown in Figure 4-11. HSRC-OQPSK Transmitter Modified CostasLoop Structure Integrator HSRC-OQPSK Transmitter Modified CostasLoop Structure Integrator Figure 4-11 Phase error simulati ons of the CDR for the HSRC -OQPSK signal with MatLab Simulink behavioral models. The transmitter and the recei ver structures modeled by behavioral components are basically the same as described in the previ ous section. The transmitter generates HSRC-OQPSK signals using random data. The generated HSRC-OQPSK signal is fed into the receiver directly. A F/F in the receiver is modeled by a S/ H and a limiter, as shown in Figure 4-11. For the phase error simulation, the QVCO signals modeled with ideal sinusoidal sources with phase offset of 90 are used in both the transmitter and the receiver. An integrator of the

PAGE 107

107 CDR accumulates the phase error generated from the phase mismatch of the carrier signals between the transmitter and the CDR loop. Th e phase mismatch can easily be modeled by changing the phase of the carrier signal. The simu lation result of the averaged phase error fits well with the analytical form obtained in (4-16), as shown in Figure 4-12. -2.0-1.5-1.0-0.50.00.51.01.52.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 e (Normalized Phase Gain)Theta (Phase Difference) Figure 4-12 Behavioral m odel simulation result of the phase error for the proposed CDR using MATLAB. 4.3.3.2 Time domain simulation The system is modeled with data-rate of 1bps and the frequency of the carrier is 0.25Hz. The reduced data-rate and the carrier frequenc y can be considered as 10Gbps and 2.5GHz respectively in actual implementation. Two VCOs with a phase difference of 90 repl aced the ideal carrier signals in order to model a QVCO, as shown as Figure 4-13. And th e loop filter (LF) is characterized with a transfer function which is equiva lent to the characteristics of a series RC network given in the loop analysis section.

PAGE 108

108 The phase error signal, e(t), changes the fr equency of the modeled QVCO. Figure 4-14 shows the simulation result of the phase error, e( t), which controls the frequency of the QVCO. The initial frequency of the QVCO is 0.247Hz with a gain of 0.012Hz/V which are comparable to 2.47GHz and 120MHz/V in a 10 Gbps system, respectively. Quadrature VCO Loop Filter Quadrature VCO Loop Filter Figure 4-13 HSRC-OQPSK Transceiver Model w ith QVCO for Time-Domain Simulation. Figure 4-14 Time-domain response of phase e rror signal for the VCO frequency control.

PAGE 109

109 In the locking state, approxima tely after 3700 time steps in Fi gure 4-14, the control voltage is not changing because no error signal is generate d from the loop. Ideally, the phase detector (PD) of the loop would not generate an error signal while the non-linear PDs, such as a bangbang PD, have a charge injection even in the lo cking state, which causes large control voltage transitions in a type II PLL [6 ], [47]. However, high frequency components might be injected at this control signal because of unavoidable mismatch es in circuits, such as a device and an I/Q mismatches in actual circuits. Phase differences are added to one of the VCOs in order to observe the I/Q mismatcheffects. Figure 4-15 illustrates the simulation of phase error, e ( t ), when the case of the phase mismatch is 10. The locking time and ripple voltage of th e phase error signal increase, as shown in Figure 4-15. The ripple voltage directly aff ects the clock jitter maki ng it degrade the system performance. Figure 4-15 Time-domain response of phase error signal for the VCO frequency control with 10 I/Q mismatch.

PAGE 110

110 Figure 4-16 shows the normalized locking time and peak-peak ripple voltage in the locking process. Since the locking time changes for random data sequences, the simulation results are obtained from the average value of 5time repeated simulation results. t0 is the average locking time of control voltage when no I/Q mismatch ha s occurred. From the simulation results shown in Figure 4-16, the locking time and peak-peak ripple voltage are almost proportional to the amount of I/Q mismatch. Needless to say, it is im portant to reduce the ri pple voltage because it directly affects the QVCOs phase noise. 0246810 0 10 20 30 40 50 I/Q Mismatch (deg)Normalized Locking Time (t-t0)/t00.00 0.01 0.02 0.03 0.04 Ripple Voltage in locking State (V) Figure 4-16 Normalized settling time and peak-pea k ripple voltage in locking state vs. I/Q mismatch. 4.4 Chip Design (Rev. 2) Since all the components can be characterized as a linear model in the behavioral model simulation, the simulation is well-matched with th e theoretical results. However, there are many non-linear factors in circuit implementation such as a VCO gain, a clock jitter, or a clock feed through of a S/H circuit.

PAGE 111

111 In this chapter, the proposed receiver combin ed with a CDR is implemented and simulated with UMC 0.18 m CMOS technology. The receiver consis ts of an input buffer, mixers, S/Hs, F/Fs, a V/I converter, and a QVCO. Most of the circuits are desi gned with CML style circuits; this is much the same for the transmitter design. 4.4.1 Circuit Implementation 4.4.1.1 Sample/hold circuit [49] proposed a high speed S/H circuit, sa mpling bandwidth up to 7GHz with 0.25 m CMOS technology, as shown in Figure 4-17. In tr acking mode where the clock is high, the S/H circuit operates as a differential amplifier. In the sampling mode when the clock falls, PMOS loads and tail current source are turned off ma king the output nodes isolat ed so that the S/H circuit is holding the sampled si gnal. M2 provides a low resistan ce differential load for wide bandwidth operation. M1 pulls up the tail node to quickly turn off the input transistors, which allows the amplifier bandwidth to be close to the sampling bandwidth [49]. Vin clk bias Vref outP outM clkb M2 M1 Figure 4-17 A high-speed differentia l sample/hold (S/H) circuit [49]. As mentioned in the previous section, a S/H circuit for the proposed CDR loop should sample the input signal at both clock edges and maintain the signal until the next clock edge

PAGE 112

112 (either rising or falling) occurs because the cloc k frequency of the loop for each channel is halfsymbol-rate. A ping-pong (PP) struct ure S/H circuit [50] can be used for this purpose. An analog MUX selects one of S/Hs which are tr acking the input si gnal alternately. Figure 4-18 shows a differenti al double clock edge sample d S/H circuit based on the PP structure S/H. The structure of the S/H shown in Figure 4-18 is equivalent to that of DET F/F. However, the analog multiplexer of the S/H shoul d linearly amplify the sampled signal without limiting the output. Since the analog multiplexer shares the same structure of the mixer shown in Figure 3-6, the linearity characteristic s can be applied for the analog MUX. Analog MUX S/H S/H Data CLK Out Figure 4-18 A ping-pong stru cture differential sample/hold circuit. 4.4.1.2 Quadrature VCO (QVCO) As discussed in Chapter 3, a two-stage ring os cillator using a current -starved inverter or shunt capacitor inverter can generate the quadr ature clock signal. However, a LC QVCO has been designed for the receiver to improve the phase noise of the carrier signal, as is the same reason for that of the transmitter design. The proposed CDR loop is comparable to the quarterrate CDR of the NRZ signal. Typically, a quarter-rate CDR needs multi-phase clock signals for the proper phase error estimation [32]. Howe ver, the proposed CDR for the HSRC-OQPSK modulation uses quadrature-phase clock signals. Figure 4-19 show s the LC-QVCO structure [6]. A cross-coupled NMOS generates a negative re sistance increasing the Q of LC tanks. The

PAGE 113

113 outputs of one VCO, I+ and I-, are fed into the inputs of the other VCO, which generates quadrature-phase outputs; Q+ and Q-. The Q+ and Qare also fed into the inputs of the other VCO. Detail analysis of the QVCO is found in [6]. Vb IQI+ c c Q+ QI+ Q+ c c IVc Figure 4-19 LC quadrat ure VCO (LC-QVCO). The Q of inductor is approxima tely 8 with a value of 3.9nH A higher value inductor has chosen to get a large voltage swing to provide a clock signal for the appropriate operation of the S/H circuit. The varactor valu e of 730fF with a fixed MIM ca pacitor of 320fF is used. The frequency of VCO is controlled by a voltage of node vc, which changes the capacitances of the varactors. Figure 4-20 shows simulated QVCOs tuning range and its gain. The QVCO achieves a tuning range of approximately 10% of the cente r frequency, 2.5GHz, and a maximum gain of 120MHz/V in the Cadence Spectre simulation. The VCO gain is relatively small, but a varactor diode is chosen to get more linear tuning performance instead of using a MOS varactor. The pull-in range is limited due to the small QVCO tuning range and its gain. However, the linear tuning performance of the QVCO an d low phase noise improve the system reliability as well as

PAGE 114

114 reduce the jitter noise. The tail current of each NMOS is 2mA, therefore, each VCO stage consumes 4mA. A voltage follower is used as an output buffer of the QVCO, which is not shown in Figure 4-19. The phase noise of -117dBc/ Hz at 1MHz offset is achieved in the Cadence Spectre simulation. -0.20.00.20.40.60.81.01.21.41.6 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 2.62 Kvco=120MHz/VFrequency (GHz)Control Voltage (V) Figure 4-20 Simulated QVCOs tuning range and its gain. 4.4.1.3 Voltage-to-current (V/I) converter A simple differential input to single ende d output V/I converter is designed which is illustrated in Figure 4-21. The simulated current gain is approximately 180 A/V. A lead/lag network as a loop filter is attached to the output node of the V/I converter. For more flexibility to choose the loop filter, the VCO control line can be exte rnally accessed. Ther efore, the value of the components of a loop filter can easily be replaced.

PAGE 115

115 Vin+ bias VinIout Figure 4-21 A differential to single-ended V/I converter. 4.4.2 Circuit Simulations Figure 4-22 shows the detailed r eceiver structure. A buffer is inserted as a delay unit to compensate the delay between the mixer output and the clock signal of the PP S/H, DET F/F. The I/Q mixer outputs are tied directly togeth er for combining the signal and followed by a differential to single-ended V/I converter. The lead /lag type loop filter is a ttached to the control node of the VCO. Signal inQVCO DET F/F PP S/H DET F/F PP S/H 90o I QVcISQSIFQFCICQ V/I Converter wired delay delayInput Buffer I data Q data CpCzRz Figure 4-22 A detailed receiver architecture.

PAGE 116

116 For the receiver simulation, the transmitter and the receiver are connect ed via a channel of 10cm transmission line with 50 characteristic impedance mode led with RLC elements. Figure 4-23 shows the simplified simulation setup. CK Data In Transmitter Signal Out D Receiver Channel 50 O I Q QVCO Rz Cz Cp CDR Figure 4-23 Time-domain simulation setup with a HSRC-OQPSK transmitter and 10cm transmission line with characteristic impedance of 50 Since the output buffer of the Rev. 2 transmitter has been terminated with the on-chip resistor, the external 50 pull-up resistor has been attached to the receiver input. Both the source and the end termination structure can minimize th e signal reflections; however, the power would be increased to transfer the signal compared to the open-drain structure wh ich is used in Rev.1s transmitter. As used in the behavioral model simulation, a LF with Rz=7K Cz=30pF and Cp=2pF is attached to the VCO control node for th e simulation purpose. To decrease the ripple of the control voltage distorting the phase of VCO, a small value of a capacito r is added to the node in parallel. A 2pF capacitor is attached for this reason, as shown in Figure 4-23. Note that this would not much change the characteristics of th e closed loop time and fr equency responses [6]. However, the much lower loop bandwidth has be en realized in actua l design to avoid high frequency jitter noise. The loop pa rameters are chosen to ensure zero of a loop transfer function located at lower frequency than the closed loop pole. These values are Cp=12nF, Cz=150nF,

PAGE 117

117 Rz=55 which are externally added to the test board. In this condition, the closed loop bandwidth is approximately 200KHz and the phase margin is more than 60. Figure 4-24 shows the simula ted phase error signal, e ( t ), which illustrates the locking behavior of the CDR. As discu ssed in behavioral simulation, if the I/Q channels are perfectly matched, there is no charge injection from the PD output when it is locking. However, a circuits non-linearities make the I/Q mismatch which intr oduces high-frequency nois es, that is, creates the difference between behavioral and circuit simulations. From the result, the estimated locking time of the CDR loop is approximately 500ns with the loop filter in Figure 4-24. The tuning range of less than 50MHz is achieved by the simulation. 0.00.51.01.52.02.5 0.70 0.75 0.80 0.85 0.90 0.95 1.00 Vcnt (V)Time (us) Figure 4-24 Simulation of the locking behavior of the proposed CDR loop. Since the receiver has no multiplexer for serial izing retimed I/Q data, the I/Q data of the transmitter and the receiver are compared, as shown in Figure 4-25. The transmitted data are

PAGE 118

118 recovered by a demodulation process in the rece iver after approximate 1ns delay. Figure 4-25 shows the simulation results where the CDR locked the loop with the proper phase. Transmitter Data Q Channel Transmitter Data I Channel Receiver Out Q Channel Receiver Out I Channel Figure 4-25 I/Q data of the transmitter and th e receiver in the proper phase locked state. As mentioned in the previ ous section, the HSRC-OQPSK CDR has a four-fold phase ambiguity as is the case of th e conventional OQPSK modulation. Therefore, the CDR loop may be locked in four possible phase points. Since on ly one phase has the prop er phase relationship, the phase ambiguity should be re solved for the proper data acqui sition. As discussed before, a differential coding with loss of 3dB power efficiency or other methods can fix this problem [10], [46]. Intuitively, it might be also resolved with training bits at the initializing steps of the communication. However, this fourfold phase am biguity issue is for future work which is discussed in Chapter 5.

PAGE 119

119 4.4.3 Layout The prototype receiver is desi gned and fabricated in UMC 0.18 m CMOS technology. Figure 4-26 show the layout structur e of the HSRC-OQPSK receiver. Varactors QuadratureVCOgnd vbrevoutQ+outQDinDin+ outIoutI+ vbi vbcp osc+ oscvbvcolpfout vcnt gnd gnd gnd gnd gnd vdd vdd vdd vboc vbo Demodulation with CDR vdd Varactors QuadratureVCOgnd vbrevoutQ+outQDinDin+ outIoutI+ vbi vbcp osc+ oscvbvcolpfout vcnt gnd gnd gnd gnd gnd vdd vdd vdd vboc vbo Demodulation with CDR vdd Figure 4-26 HSRC-OQPSK receiver ch ip fabricated with UMC 0.18 m CMOS technology. Four inductors for the quadrature VCO (QVCO) occupy the most part of chip, varactors are place in the center and the demodulation logics with CDR are placed on right side of the chip. The power and ground ring is placed around th e chip, which are not shown in the die photo because the power and ground ring is metal5 layers. Input signal pads are placed close to the demodulation logic. The chip has 26 pads in cluding 8 differential signal inputs and outputs which are operated up to 10Gbps, 11 power and ground, 5 biases, and VCO control outputs for the external loop filter with the total chip size of 1185 m X 1260 m. The bypass capacitor for the power and ground has been placed at the unused chip area with the value of more than 60pF.

PAGE 120

120 4.5 Measurement (Rev.2) The same test of the transmitters has been used for the receiver. Figure 4-27 shows the test board which is the same board as that of the transmitters. Bypass capacitor of approximately 100 F are attached between the power and the gr ound. The I and Q channel outputs are to be connected to the external 2:1 mux for the BER test. VCO outputs are for monitoring the lockedstate of the CDR loop and the recovered clock signal. Figure 4-27 Receiver test board. Figure 4-28(a), (b) show the simplified 2.5G bps and 10Gbps receiver measurement setups, respectively. The signals are depicted with a si ngle signal line for the simplification while the actual signals are differential. Sin ce it is not easy to estimate th e receivers performance with a conventional signal generator because the propos ed HSRC-OQPSK signal is different from the conventional NRZ signal, the HSRC-QOPSK r eceiver incorporated with the proposed CDR requires HSRC-QOPSK modulat ed signal to evaluate the receive rs performance. Therefore, the

PAGE 121

121 HSRC-OQPSK transmitter output is connected to th e receiver input via a channel as shown in Figure 4-28. A 2.5GHz VCO signal output of the transmitter is fed into the external clock input of the Agilent 4093A BERT for the 2.5Gbps BER test An external 2:1 m ux (Inphi 20709SE) operating up to 20Gbps is located at the receiver output for serializing the I and Q channel data. The serialized data is fed back into the BERT for the BER performance test of the receiver. CK Data In Transmitter Signal Out 2.5GHz VCO Signal Signal Generator VCO Out External Clock In 5GHz Clock 2.5Gbps Data InBERT D Receiver Channel 50ohm IDataQData2:1 MUX (external) Phase Shifter (a) BERT CK Data In Transmitter Signal Out 1/2 sub clock 10Gbps Data In D Receiver Channel 50ohm IDataQData2:1 MUX (external) Phase Shifter Phase Shifter (b) Figure 4-28 Simplified receiver (transceiver) m easurement setups (a) for 2.5Gbps input (equivalent data-rate of 5Gbps ), (b) for 10Gbps data-rate. Figure 4-29 shows the phase noise performance of the VCO. The red line in Figure 4-24 represents the phase noise of the receivers VC O signal in locked-state. The phase noise of the

PAGE 122

122 recovered clock is approximately -87dBc/Hz at 50KHz offset. The 2.43Gbps random data has been fed into the transmitter to generate the HSRC-OQPSK signal which is the source signal of the receiver. The measured tracking range of the CDR is approximately 30MHz. 10K 100K 1M -120 -110 -100 -90 -80 -70 -60 -50 -40 Offset Frequency (Hz)Phase Noise (dBc)free-running locking Figure 4-29 Phase noise performan ce of the receivers VCO in free-running and locking states. Figure 4-30 illustrates the measured jitter of th e recovered clock in response to 2.43Gbps PRBS sequence of 231-1. Since the modulated signal cannot be generated by BERT, the transmitter outputs which generate the HSRC-OQ PSK signal are connected to the receivers inputs for the measurement. The measured rms jitter and the peak-to-peak jitter of the recovered clock by the CDR loop are equivalent to 6.5ps and 39.9ps respectively. Figure 4-31 shows the recovered I or Q channel data output when the 231-1 PRBS input has been used. As shown in Figure 4-23, the BER test has been performed using 2.5Gbps and 10Gbps test setups, respectively w ith three different ( 5, 10, 20 ) FR-4 PCB channels and a 19 SATA cable. From the measurement results, BER of < 10-9 have been achieved up to 10 PCB channel and a SATA cable where 2.43Gbps 231-1 PRBS is used while BER of 10-4 is

PAGE 123

123 achieved where a 20 PCB channel is used. However, the BER of <10-9 has been achieved where 2.43Gbps 27-1 PRBS is used. The power consumption of the receiver core is approximately 130mW from a 1.8V supply exclud ing power consumptions of the output buffers for the I and Q channel data, which is driving the input of the external 2:1 mux for serializing the data and output buffer of the VCO for the purpose of monitoring. 50mV/div 10ps/div p-pjitter 50mV/div 10ps/div p-pjitter Figure 4-30 Measured jitter of recovered clock in response to 4.86Gbps (both I and Q channel input with 2.43Gbps PRBS sequence of 231-1). 100mV/div 100ps/div 100mV/div 100ps/div Figure 4-30 Recovered I (or Q) channel eye-diag rams in response to 4.86Gbps (both I and Q channel input with 2.43G bps PRBS sequence of 231-1).

PAGE 124

124 Unfortunately, it has been failed to evaluate the performance of the receiver at 9.72Gbps because there are no reasonable BER performa nce and recovered eye-diagrams from the measurement. One of the main reason of the failu re in recovering the 9.72 Gbps data is that the transmitted signal generated from the transmitter does not have enough energy in a peak signal which has the signal energy of Es,p analyzed in Chapter 2. Eye-opening mismatches in the transmitted data-rate of 9.72Gbps eye-diagra m shown in Figure 3-27(a) caused a slight synchronization mismatch between the clock and the data and it might affect the performance of the receiver. Another reason for failure in rec overing data might be from the CDR performance of the receiver. However, it is hard to evaluate the CDR perf ormance itself without the HSRCQOPSK modulated signal because there is no eq uipment that generates the ideal 10Gbps HSRCQOPSK signal. Although it has failed to recover 9.72Gbps transmitted data at the receiver which is originally designed for recovering up to 10Gbps transmitted data, we could get a much improved system performance if the low-noise a nd the broadband circuit design are considered to design the transceiver. And fr equency compensation techniques, such as a pre-emphasis of the signal at the transmitter or the equalizing signal at the receiver-end using filter will also greatly help in increasing the performance of the transcei ver. However, these are put to future work. Table 4-1 summarizes the performance of the receiver. Table 4-1 Transceiver (Rev.2) performance summary Data Rate 4.86Gbps (2.43Gb/s I/Q input) @ sequence of 231-1 < 10-9 @ up to 10 PCB channel and 19 SATA cable < 10-4 @ 20 PCB channel BER Performance @ 4.86Gb/s PRBS input (2.43Gb/s PRBS I/Q input) @27-1 < 10-9 @ 20 PCB channel Phase Noise (recovered cloc k) -87dBc @ 50KHz offset

PAGE 125

125 Table 4-1 (continued) Recovered clock jitter 6.5ps (rms), 39.9ps (p -p) @ 2.43Gbps PRBS of 231-1 CDR tracking range 30MHz (Loop Bandwidth 200KHz) Power consumption Tx + Rx : 200mW @ 1.8V Die Size Tx: 1130 x 1240 m2 Rx: 1185 x 1260 m2 Technology UMC 0.18 m CMOS 4.6 Summary This chapter proposed a HSRC-OQPSK receiver incorporated with a new CDR loop, and demonstrated its viability of incr easing the data-rate in high-speed serial link system by using the HSRC-OQPSK modulation. The proposed rece iver has been designed with UMC 0.18 m CMOS technology and the analysis has been compared w ith the simulation results. From the simulation results, the time domain signals and the spect rum of the HSRC-OQPSK modulation fit well with theoretical analyses. This paper also proposed a CDR based on the Costas loop for the HSRC-OQPSK modulation. The proposed CDR is comparable to a quarter-rate CDR of NRZ modulation because it uses quarter data-rate frequency clock. Therefor e, the proposed CDR can improve the timing constraints of the receivers clock and data recovery. The CDR incorporated with the receiver is simulated and compared to the anal ytical results. Moreover, the CDR uses a QVCO instead of multi-phase VCO which is applied to a conventional quarter-rate CDR hence it offers a simple receiver structure. The circuit simulation results of the phase error and the locking behavior relatively fit well with the behavioral model simulation. In addition, the proposed CDR, characterized as a linear PD, can lower the jitter noise [44-45]. The HSRC-OQPSK transceiver can easily be im plemented with a low-voltage technology due to the reason that it uses two level data d ecision while a multi-PAM (e.g., 4-PAM) system [3]

PAGE 126

126 needs reference voltages and the level spacing which is difficult to maintain linear levels in a low-voltage system for data deci sions. Moreover, this allows a simple transceiver architecture. The measurement results show the feasibility of using the HSRC-OQPSK as a modulation technique offering a simple transceiver architecture for the high-speed wire-line communications, such as a serial link. Mor eover, the HSRC-OQPSK modulation and the receiver can enable a serial li nk system to achieve higher data -rate without aiding a reference clock in low-voltage wire-l ine communication systems.

PAGE 127

127 CHAPTER 5 SUMMARY AND SUGGESTIONS FOR FUTURE WORK 5.1 Summary The HSRC-PSK modulations are proposed to optimize spectral efficiency for high datarate transmission over band-limited channels. The analysis and simulation results show that the proposed modulations can be used in high-spee d data communications, such as a backplane serial link. In the past, a multi-PAM signal (e.g., 4-PAM) ha s been demonstrated to increase the datarate in band-limited channels [3]. However in 4-PA M modulation, it is difficult to maintain the linear spacing between levels in low-voltage a nd low-power application and as a result the systems performances are degraded. The level sp acing also causes complexi ty in the transceiver design not only because the received signal needs to be linearly amplified but also because 4PAM signaling requires accurate reference voltages. The proposed HSRC modulations not only reduced the bandwidt h requirement but also can be easily implemented in deep submicron inte grated circuit technol ogies with low supply voltages. Three HSRC-PSK modulations named HSRC-QPSK, HSRC-OQPSK, and HSRCMSK are introduced and analyzed in terms of their spectrums and BER performances. The HSRC-QPSK modulation can reduce the required bandwidth without any BER performance degradation compared to the NRZ m odulation. However, it is hard to implement a HSRC-QPSK demodulator with a conve ntional circuit technique due to the difficulty in realizing a matched filter in GHz range. The demodul ation method for HSRC-QPSK is still under investigation. The HSRC-MSK modulation can minimize crosst alk noise compared to the conventional ones, since the high frequency components are maximally suppressed [14] among the introduced

PAGE 128

128 three quadrature HSRC-PSK modulations. Howeve r, it does not help to reduce the required bandwidth of the transmitted signal because the firs t null bandwidth is the same as that of the NRZ modulation. The HSRC-OQPSK modulation has been chosen as a feasible modulation technique which can be used in high-speed wire-line data communications. A pr ototype HSRC-OQPSK transmitter has been designed with discrete components to verify the theory. Measurement results confirmed that the proposed modulations can be effectively used in band-limited wire-line applications requiring spectral efficiency, such as the backplane serial link. Moreover, because it requires only a two-level decision, the HSRC-OQPSK transmitter can be implemented in a simpler architecture than 4-PAM and is suitab le for low-voltage systems. The HSRC-OQPSK spectrum, which is the same as the MSK spectrum, contains 99% of the to tal signal power within the bandwidth of B (1.2/ Tb). In comparison, 4-PAM which has the same signal spectrum as that of QPSK has a much larger 99% bandwidth of B (8/ Tb) [13]. Therefore, it is expected that the proposed HSRC-OQPSK modula tion should have an efficient signal spectrum in bandlimited channels and also this spectrum efficiency will reduce the high frequency crosstalk noise between the signal lines which may improve the performance of the multi-port serial communication links. Moreover, a fully reference-less serial link transceiver usi ng the HSRC-OQPSK modulation has been proposed and demonstrated its viability of increasing data-rate in highspeed serial link system. The proposed tran sceiver has been designed with UMC 0.18 m CMOS technology and the analysis has been compared w ith the simulation results. From the simulation results, the time domain signals and the spect rum of the HSRC-OQPSK modulation fit well with the theoretical analyses.

PAGE 129

129 A QPSK carrier recovery loop can be us ed for the propoed HSRC modulations which enables flexible design of the receiver. A new CDR loop for the HSRC-OQPSK based on the polarity-type Costas loop has been proposed and implemented by the UMC 0.18 m CMOS technology. This paper also pr oposed a CDR based on the Cost as loop for the HSRC-OQPSK modulation. The proposed CD R is comparable to a 1quarter-rate CDR of the NRZ modulation because it uses a quarter data-r ate frequency clock. Therefore, the proposed CDR can improve timing constraints of the receivers clock and data recovery. Mor eover, the HSRC-OQPSK allows a simple transceiver architecture which can easily be implemented with a low-voltage technology due to the reason that it uses two-le vel data decision while a multi-PAM (e.g., PAM4) system [3] needs reference voltages and the leve l spacing which is difficult to maintain linear levels in a low-voltage system for data deci sions. Table 5-1 summarizes and compares the characteristics of the conventional modulati ons and the proposed HS RC-OQPSK modulation. Table 5-1 Performance comparison of the different modulations. PAM-2 (NRZ) PAM-4 Duobinary HSRCOQPSK Main lobe bandwidth (first null) 1/ Tb 1/2 Tb 1/2 Tb 3/4 Tb Transmitted Signal Spectrum Difference between main and second lobe 13dB 13dB 13dB 23dB 1CDR Clock Frequency Full Rate Half Rate Full Rate Quarter Rate # of Level 2 4 3 2 Decision Threshold 1 3 2 1 Data Decision Decision Interval Tb 2 Tb Tb 2 Tb 1 Half and quarter data rate CDR has been developed for the PAM signaling [32], [51].

PAGE 130

130 The results show that the HSRC-OQPSK m odulation and the transceiver can enable a serial link system to achieve a higher data-rate without aiding a referenc e clock in low-voltage wire-line communication systems. 5.2 Four-fold Ambiguity Issue As mentioned in Chapter 4, the proposed CD R based on the Costas loop has a fourfold ambiguity problem. Only one out of the four stable locking points has proper phase information. The differentially encoded data can resolve this four-fold ambiguity prob lem with 3dB signal to noise ratio (SNR) degradation [10]. A transmitter with differentially encoded data input can be implemented using a XOR gate and a F/F, as sh own in Figure 5-1. It is essential for the architecture of Figure 5-1(a) to have a parallel-to-serial logic which is implemented with a 2:1 multiplexer in the receiver. The alternative archit ecture decoding the data in the receiver without using a 2:1 multiplexer is shown in Figure 5-1(b). The I and Q channels of the receiver generate the demodulated data which are offset with one bit-time, Tb, offset, hence, the architecture shown in Figure 5-1(b) can also be used to decode the modulated data. HSRC-OQPSK Transmitter D Q CK HSRC-OQPSK Receiver (include 2:1 multiplxer with I/Q inputs) Data In Data Out CK Q D Transceiver 1 ChannelTransceiver 2 (a) Figure 5-1 A differentially coded HSRC-OQPSK transceiver architect ure to resolve the fourfold ambiguity issue (a) the receiver includes a 2:1 multiplexer for serializing I/Q channel data (b) alternative architecture without using a multiplexer.

PAGE 131

131 HSRC-OQPSK Transmitter D Q CK HSRC-OQPSK Receiver Data In Data Out CK Q D Transceiver 1 ChannelTransceiver 2I Q (b) Figure 5-1 (continued). Another approach to resolve the fourfold ambi guity issue is synchroni zation at the protocol layer. Every serial data li nk communications almost a ll data communica tions needs synchronization, that is initializat ion of the data communications. B its are sent out to the channel from the least-significant bit (LSB) to the most-s ignificant bit (MSB). All packets start with a synchronization (SYNC) field, whic h is coded for the maximum edge transition rate. It is used by CDR to recover the clock and data synchronizati on. A SYNC filed is defined to be eight bits in length for full/low speed and 32 bits for high speed in the USB specification 2.0 [52] as an example. Packet identifier (PID ) follows the SYNC field. The USB specification 2.0 protocol detail is presented in [52]. The protocol detail is not disc ussed in this chapter; however a conceptual resolution of the fourfold ambiguity by using a SYNC field. As described before, the SYNC field is coded to make maximum edge transition in order to give more gain to the circuitry which aligns the incoming data. However, the HSRC-OQPSK should have different SYNC to maximize edge transition because it uses a carrier for the modula tion. The carrier signal tr ansforms the original

PAGE 132

132 transmitted data sequences. To make it simple, assu me the SYNC field is eight bit as is the case for full/low speed of USB specification 2.0 and th e SYNC field of the initial transmitter of has the maximu m edge transition. The data is split into I and Q channel and for the transmitter. After demodulated at the receiver, four possible data sequences exist on the I and Q channel. When the CDR locks the loop with a proper locking phase the data sequences are the same as the transmitted ones which are and fo r the I and Q channels of the receiver, respectively. If the loop is locked with 90 phase offset, one of the I/Q channels would recover the transmitted data reversely fr om the original data which ar e or Both the I/Q data are inverted and 1001 on condition that the CDR loop is locked with the 180 phase offset. With these four possible SYNC fields at the receiver, we can estimate at which phase the CDR loop is locked. Figure 5-2 shows the conceptual four-fold ambiguity resolution method using a SYNC field. D Q CKB HSRC-OQPSK Receiver I Q D Q CK D Q D Q D Q D Q D Q D Q 4 4 I Data Out Q Data Out Logical Operation(Control signals generate logical 1 if the SYNC of I/Q is inverted from expected value, otherwise logical 0)I Control Q Control Figure 5-2 An example of a conceptual architectur e for resolving four-fold ambiguity issue using eight bits SYNC field.

PAGE 133

133 LIST OF REFERENCES [1] A. B. Carson, P. B. Crilly, and Janet C. Rutledge, Communication Systems New York: McGraw-Hill, 2001, ch.11. [2] G. Lawday, On the buses IEE Review pp. 44-47, Jan. 2004. [3] R. Farjad-Rad, C.-K. Ken Yang, M. A. Horo witz, and T. H. Lee, A 0.3-m CMOS 8-Gb/s 4-PAM serial link transceiver, IEEE Journal of Solid-State Circuits vol. 35, no.5 pp. 757764, May 2000. [4] J. T. Stonick, G.-Y. Wei Yang, J. L. Sonnt ag, and D. K. Weinlade r, An adaptive PAM-4 5Gb/s backplane transceiver in 0.25 m CMOS, IEEE Journal of Solid-State Circuits vol. 38, no.3 pp. 436-443, Mar. 2003. [5] R. Farjad-Rad, A CMOS 4-PAM Multi-Gbps Serial Link Transceiver, Ph.D. dissertation, Dept. Elct Eng., Stanford Univ., Stanford, CA, 2000. [6] B. Razavi, Design of Integrated Circu its for Optical Communications McGraw-Hill, 2003. [7] P. Kabal, S. Pasupathy Partial-response signaling, IEEE Transactions on Communications vol. 23, no. 9, pp. 921-934, Sep. 1975. [8] M. Horowitz, C.-K. K. Yang, and S. Sidi ropoulos, High-speed electrical signaling: overview and limitations, IEEE Micro pp. 12-24, Jan. 1998. [9] J. H. Sinsky, M. Duelk, and A. Adamiecki, High-speed electrical backplane transmission using duobinary signaling, IEEE Transaction on Microwave Theory and Techniques vol. 53, no.1, pp. 152-160, Jan. 2005. [10] J. G. Proakis, Digital Communications New York: McGraw-Hill, 1995. [11] D. R. Smith, Digital Transmission Systems New York: Van Nostrand Reinhold, 1985, ch. 6. [12] T. S. Rappaport, Wireless Communications NJ: Upper Saddle River, Prentice Hall, 1996, ch. 5. [13] S. Pasupathy, Minimum shift keying: a spectrally effici ent modulation, IEEE Communications Magazine pp. 14-22, July 1979. [14] R. Bashirullah, W. Liu, and R. Cavin, Cross-talk reduction for interconnect-limited bus based on raised cosine signaling, Proceeding of 2002 CICC pp. 513-516 [15] S. A. Gronemeyer, and A. L. McBr ide, MSK and offset QPSK modulation, IEEE Transactions on Communications vol. 24, no. 8, pp. 809-820, Jul. 1976.

PAGE 134

134 [16] T. J. Gabara and W. C. Fischer, Capaci tive coupling and quantized feedback applied to conventional CMOS technology, IEEE Journal of Solid-State Circuits vol. 32, no. 3, pp. 419-427, Mar. 1997. [17] L. Luo, J. M. Wilson, S. E. Mick, J. Xu, L. Zhang, and P. D. Franzon, Gb/s AC coupled chip-to-chip communication usin g a low swing pulse receiver, IEEE Journal of SolidState Circuits vol. 41, no. 1, pp. 287-296, Jan. 2006. [18] Part3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specification IEEE Standards 802.3-2002. [19] J. Yoon, and W. Eisenstadt, Lumped pa ssive circuit for 5GHz embedded test of RF SoCs, IEEE ISCAS pp. 1241-1244, May 2004. [20] T. H. Lee, The Design of CMOS Radio-Freque ncy Integrated Circuits, 2nd MA: Cambridge University Press, 1998, ch. 18. [21] B. Razavi, RF Microelctronics NJ: Upper Saddle River, Prentice Hall PTR, 1997, ch. 5. [22] P. Heydari, Design and analysis low-voltage current-mode logic buffers, Proceedings of 4th ISQED03 pp. 293-298, 2003. [23] B. Razavi, Design of Analog CMOS Integrated Circuits New York: McGraw-Hill, 2003. [24] P. Heydari, and R. Mohanavelu, Design of ultrahigh-speed lo w-voltage CMOS CML buffres and latches, IEEE Transactions on VLSI Systems vol. 12, No.10, pp. 1081-1093, Oct. 2004. [25] M. G. Johnson, and E. L. Hudson, A variable delay line PLL for CPU-coprocessor synchronization, IEEE Journal of Solid-State Circuits vol. 23, no.5 pp. 1218-1223, Mar. 1988. [26] A. Mazzanti, P. Uggetti, and F. Svelto, Ana lysis and design of LC dividers for quadrature generation, IEEE Journal of Solid-State Circuits vol.39, no.9, pp.1425-1433, Sep. 2004 [27] H. Johnson, and M. Graham, High-Speed Digital Design 1st, Prentice Hall PTR, 1993. [28] S. Galal, and B. Razavi, -Gb/s limiti ng amplifier and laser/modulator driver in 0.18m CMOS technology, IEEE Journal of Solid-State Circuits vol. 38, no.12, pp. 2138-2146, Dec. 2003. [29] Affirma Spectre Circuit Simulator User Guide Cadence Design Systems Inc., San Jose, CA, 2000. [30] A. Adamiecki, M. Duelk, and J. H. Sins ky, Gbit/s electrical duobinary transmission over FR-4 backplanes, IEE Electronics Letters vol. 41, no.14, pp. 826-827, Jul. 2005.

PAGE 135

135 [31] K. Yamaguchi, K. Sunaga, S. Kaerlyama, T. Nedachi, M. Takamiya, K. Nose, Y. Nakagawa, M. Sugawara, and M. Fukais hi, Gb/s Duobinary signaling with x2 oversampled edge equalization, ISSCC 2005 IEEE International pp. 584-585 [32] J. Lee and B. Razavi, A 40-Gb/s cloc k and data recovery circuit in 0.18um CMOS technology, IEEE Journal of Solid-State Circuits vol. 38, no.12, pp. 2181~2190, Dec. 2003 [33] H. C. Osborne, A generalized politytype Costas loop for tracking MPSK signals, IEEE Transactions on Communications vol. 30, no. 10, pp. 2289-2296, Oct. 1982. [34] M. K. Simon, Tracking performance of Co stas loop with hard-limited in-phase channel, IEEE Transactions on Communications vol. 26, no.4, pp. 420-432, Apr. 1978. [35] J. P. Costas, Synchronous communications, Proceedings of the IRE vol. 44, no.12, pp. 1713-1718, Dec. 1956. [36] W. C. Lindsey and M. K. Simon, Ca rrier synchronization and detection of polyphase signals, IEEE Transactions on Communications vol. 20, no.3, pp. 441-454, Jun. 1972. [37] A. Leclert, and P. Vanda mme, Universal carrier recovery loop for QASK and PSK signal sets, IEEE Transactions on Communications vol. 31, no.1, pp. 130-136, Jan. 1983. [38] M. K. Simon and J. G. Smith, Carrier synchronization and de tection of QASK signal sets, IEEE Transactions on Communications vol. 20, no.2, pp. 98-106, Feb. 1974. [39] M. K. Simon, On the optimality of the MAP estimation loop for carrier phase tracking BPSK and QPSK signals, IEEE Transactions on Communications, vol. 27, no. 1, pp. 158165, Jan. 1979. [40] C. L. Weber, and W. K. Alem, Demod-re mod coherent tracking r eceiver for QPSK and SQPSK, IEEE Transactions on Communications vol. 28, no. 12, pp. 1945-1954, Dec. 1980. [41] C. L. Weber, and W. K. Alem, Performan ce analysis of demod-remod coherent receiver for QPSK and SQPSK input, IEEE Transactions on Communications vol. 28, no. 12, pp. 1954-1968, Dec. 1980. [42] R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications New York: McGraw-Hill 2003, ch. 9. [43] H. Yeo, Y. Lee, J. Chen, and J. Lin, Half-symbol-rate-carrier offset QPSK transmitter for bandwidth-efficient high-speed data comm unications, IEEE Microwave and Wireless Components Letters, vol. 17, no. 6, pp. 466-468, June 2007. [44] S. B. Anand, and B. Razavi, A CMOS clock recovery circuit for 2.5Gb/s NRZ data, IEEE Journal of Solid-State Circuits vol. 36, no.3, pp. 432-439, Mar. 2001.

PAGE 136

136 [45] C. R. Hoggie, A self co rrecting clock recovery circuit, IEEE Journal of Lightwave Technology vol. 3, no. 6, pp. 1312-1314, Dec. 1985 [46] E. R. Cacciamani. and C. J. Wolejsza, Jr. Phase ambiguity resoluti on in a four-phase PSK communications system, IEEE Transactions on Communication Technology vol. 19, no.6, pp. 1200-1210, Dec. 1971. [47] B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits NJ: Piscataway, IEEE Press, 1996. [48] F. M. Gardner, Charge-pump phase locked loops, IEEE Transactions on Communications vol. 28, no.11, pp. 1849-1858, Nov. 1980. [49] C.-K. Ken Yang, V. Stojanovic, S. Modjtahe di, M. A. Horowitz, and W. F. Ellersick, A serial-link transceiver based on 8-GSam ples/s A/D and D/A converters in 0.25m CMOS, IEEE Journal of Solid-State Circuits vol. 36, no.11, pp. 1684-1691, Dec. 2001. [50] M. H. Shakiba, D. A. Johns, and K. W. Martin, BiCMOS circu its for analog Viterbi decoders, IEEE Transactions on Circuits and Systems vol. 45, no.12, pp. 1527-1537, Dec. 1998. [51] J. Savoj, and B. Razavi, -Gb/s CMOS cl ock and data recovery circuit with a half-rate binary phase/frequency detector, IEEE Journal of Solid-State Circuits vol. 38, no.1, pp. 13-21, Jan. 2003. [52] Universal Serial Bus Sp ecifications, revision 2.0 Apr.. 2000.

PAGE 137

137 BIOGRAPHICAL SKETCH Hyeopgoo Yeo was born in Seoul, Korea, in 1968. He received his B.S. and M.S. degrees in electronic engineering from Yonsei Univer sity, Seoul, Korea, in 1991 and 1993, respectively. He also received his M.S. degree in electrical an d computer engineering from the University of Florida, Gainesville, USA, in 2003. From 1993 to 1999, he worked as a design en gineer at Samsung Electronic Co. Ltd., Kihung, Kyounggi-do, Korea, where he perfor med CMOS ASIC cell library design and development. He is currently pursuing his Ph.D degree as a graduate research assistant at the University of Florida. His research interests involve RF/ana log circuit design, high-s peed digital systems. He is particularly interested in high-speed serial links.