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An integrated multichannel neural recording system with spike outputs

University of Florida Institutional Repository

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Iwouldliketoexpressmysinceregratitudetomyadvisor,Dr.JohnG.Harris,forhissupportandencouragementinthepastyears.Noneofthisworkcouldbepossiblewithouthissupportandguidance.Dr.Harrishasalwaysencouragedmetolearnmore,tothinkindierentperspectivesandtoimprovemyself.Theexpertiseandwisdomhecontinuestosharemakesmeabetterengineerandabetterperson.IalsowishtoextendagraciousthankyoutoDr.JoseC.Principe,whoisleadingthelabandprovidingdirectionforus.IwouldliketothankDr.RobertM.Fox,foralltheknowledgeIlearnedfromhiscoursesandDr.JustinC.Sanchez,forallthehelphegavemeduringmyresearch.ThroughoutmyPhDresearch,DuChenstandsoutinhelpingmeunderstandcomplementarymetal-oxide-siliconeld-eecttransistors(CMOS)neuralrecordingdesign.Iamverygratefulforherkindnessandguidance.IwouldliketothankXinQi,DongmingXu,ChristyRogersandJieXuforallofthediscussionsaboutmyresearch.Furtheron,Iwanttothanktherestofstudentsinmylab;especiallyJin,Xiaoxiang,Kwansun,Meena,Dazhi,MarkandTom,formakingthelabafunplacetoliveandwork.Iwouldliketoexpressmydeepestappreciationtomywife,LinZhang,forhergreatloveandsupport.Finally,IamespeciallygratefultomymotherandmybrotherinChinafortheirloveandsupport.Idedicatethisdissertationtothem. 4

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page ACKNOWLEDGMENTS ................................. 4 LISTOFTABLES ..................................... 7 LISTOFFIGURES .................................... 8 ABSTRACT ........................................ 11 CHAPTER 1INTRODUCTION .................................. 12 1.1ExtracellularNeuralSignalProperties .................... 12 1.2NeuralRecordingSystemOverview ...................... 14 1.2.1Electrodes ................................ 16 1.2.2Preamplier ............................... 17 1.2.3ReadoutElectronicsandSomeDataReductionDiscussion ..... 18 1.3UniversityofFloridaBrainMachineInterfaceProject ............ 19 1.4ResearchGoal .................................. 20 2SECOND-STAGEAMPLIFIERDESIGN ..................... 21 2.1AmplierStructure ............................... 21 2.2OperationalTransconductanceAmplierDesign ............... 25 2.3NoiseAnalysis .................................. 28 2.4MeasurementResults .............................. 30 3ANOVELTRANSCONDUCTANCEAMPLIFIERANDBIPHASICINTEGRATE-AND-FIRENEURON ........................ 32 3.1Introduction ................................... 32 3.2TransconductanceAmplier .......................... 34 3.3Integrate-and-FireNeuron ........................... 38 3.3.1IdealIntegrate-and-FireNeuronandNonidealities .......... 38 3.3.2BiphasicIntegrate-and-FireNeuronandNonidealityAnalysis .... 40 3.4OperationalTransconductanceAmplierDesign ............... 51 3.4.1CircuitDescription ........................... 52 3.4.2NoiseandPowerConsideration .................... 53 3.5ChipLayout ................................... 55 3.6CadenceSimulationResults .......................... 55 3.7MeasurementResults .............................. 57 3.7.1Single-ToneInput ............................ 58 3.7.2Neural-SimulatorInput ......................... 62 3.8Practicalissues ................................. 70 3.8.1SignalDependentReferenceoftheComparator ............ 71 5

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.... 73 4EIGHT-CHANNELBIPHASICINTEGRATE-AND-FIREWITHADDRESSEVENTREPRESENTATIONREADOUT ..................... 83 4.1Introduction ................................... 83 4.2AddressEventRepresentationStructure ................... 85 4.2.1Arbiter .................................. 86 4.2.2RowInterface .............................. 87 4.2.3LatchandLatchControl ........................ 87 4.2.4ThroughputControl ........................... 90 4.3ChipLayout ................................... 91 4.4MeasurementResults .............................. 92 4.4.1One-ChannelInput ........................... 92 4.4.2Two-ChannelInput ........................... 96 4.4.3Three-ChannelInput .......................... 99 4.4.4Four-ChannelInput ........................... 101 4.4.5Eight-ChannelInput .......................... 102 4.5NonidealIssues ................................. 105 4.5.1TimingErrorForcedbytheReadoutClock .............. 106 4.5.2SpikeDelayandSpikeLoss ....................... 108 4.5.3NoiseIssue ................................ 109 5SINGLE-STAGETRANSCONDUCTANCEAMPLIFIERANDBIPHASICINTEGRATE-AND-FIRENEURON ........................ 111 5.1Introduction ................................... 111 5.2Single-StageTransconductanceAmplier ................... 111 5.3SimulationResults ............................... 116 5.3.1CadenceSimulation ........................... 116 5.3.2MatlabSimulation ............................ 118 5.4NoiseandPowerConsideration ........................ 122 6CONCLUSIONS ................................... 124 REFERENCES ....................................... 126 BIOGRAPHICALSKETCH ................................ 129 6

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Table page 2-1Characteristicsofsecond-stageamplier ...................... 30 3-1Spike-ratecomparison ................................ 65 3-2Statisticsresultsonthereconstructedsignals .................... 67 3-3Statisticsresultsonthezeroedreconstructedsignals ................ 68 3-4Reconstructedneuralsignalspikesortingstatistics ................ 69 4-1Eight-channelchipmeasurementsummary ..................... 106 7

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Figure page 1-1Typicalextracellularneuronrecordingtechniques ................. 13 1-2Typicalneuralrecordingsystemarchitecture .................... 14 1-3Threegenerationsofrecordingsystem ....................... 19 2-1Schematicsofsecond-stageamplier ........................ 22 2-2Resistor-feedbackamplieralternatingcurrentvoltage(AC)amplituderesponse ........................................ 23 2-3Capacitor-feedbackamplierACamplituderesponse ............... 24 2-4SchematicoftheOperationalTransconductanceAmplier(OTA)withclassABoutputstage ...................................... 25 2-5ACresponseoftheclassABOTA .......................... 26 2-6SchematicoftheOTAwithclassAoutputstage .................. 27 2-7ACresponseoftheclassAOTA .......................... 28 2-8Measurementresultsfromneuralsignalsimulator ................. 31 3-1Schematicofthebiphasicpulseconverter ...................... 33 3-2Schematicofthegmamplier ............................ 34 3-3Equivalentcircuitofthegmamplier ........................ 35 3-4ACresponseofthegmamplier ........................... 37 3-5Idealtwo-stagesystemforspikerepresentation ................... 38 3-6Schematicoftheintegrate-and-re(IF)neuron .................. 38 3-7SchematicofthepracticalIFneuron ........................ 41 3-8Impulseresponseofthegmamplier ........................ 42 3-9Simulatedtimedomainresults ............................ 44 3-10Simulatedtimedomainresults ............................ 45 3-11signal-to-noiseratio(SER)vs.sinewavefrequency ................ 49 3-12SERvs.bypassresistance .............................. 51 3-13SERvs.outputresistance .............................. 52 8

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.............................. 53 3-15SchematicoftheOTA ................................ 54 3-16Layoutofthesingle-channelbiphasicIFneuronchip ............... 56 3-17ReconstructedSERvs.inputsignalfrequency ................... 57 3-18SERvs.singletonefrequency ............................ 58 3-19Spikeratevs.sinewavefrequency .......................... 59 3-20Measuredreconstructiontimedomainresultexample ............... 60 3-21Thresholdvs.spikerate ............................... 61 3-22Thresholdvs.SER .................................. 62 3-23Measuredreconstructiontimedomainresultexample ............... 64 3-24Measuredreconstructiontimedomainresultexample ............... 66 3-25Spikesortingresultbasedonreconstructedneuralsignal ............. 68 3-26Comparisonbetweenthecorrectlyidentiedactionpotential(bluesolidline)andthemissingactionpotentials(reddottedlines) ................ 70 3-27Sixactionpotentialclasses .............................. 71 3-28Principalcomponentanalysiscorrespondingtothesixtemplates ......... 72 3-29Comparatorbiascurrentvs.SER .......................... 74 3-30EquivalentcircuitofgmblockwithDCoset ................... 75 3-31SERvs.estimatedDCoset ............................. 77 3-32SERvs.DCoset .................................. 78 3-33SERvs.comparatorthreshold ............................ 80 3-34SERvs.inputsingletonefrequency ......................... 81 4-1Blockdiagramofthe8-channeladdress-event-representation(AER)recordingsystem ......................................... 84 4-2Schematicofthearbitercell ............................. 86 4-3Schematicoftherowinterface ............................ 87 4-4Schematicsofthelatchcellandlatchcontrol .................... 88 4-5SchematicofthethroughputcontrolblockforclockedAER ............ 90 9

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....... 91 4-7Clockfrequencyvs.SER(onechannel) ....................... 93 4-8Clockfrequencyvs.outputspikerate(onechannel) ................ 94 4-9Measuredreconstructiontimedomainresultexample ............... 95 4-10Clockfrequencyvs.SER(twochannels) ...................... 97 4-11Clockfrequencyvs.outputspikerate(twochannels) ............... 98 4-12Measuredreconstructiontimedomainresultexample ............... 99 4-13Clockfrequencyvs.SER(threechannels) ..................... 100 4-14Clockfrequencyvs.outputspikerate(threechannels) .............. 101 4-15Clockfrequencyvs.SER(fourchannels) ...................... 102 4-16Clockfrequencyvs.outputspikerate(fourchannels) ............... 103 4-17Clockfrequencyvs.SER(eightchannels) ..................... 104 4-18Measuredreconstructiontimedomainresultexample ............... 105 4-19Clockfrequencyvs.SER(onechannelMatlabsimulation) ............ 107 4-20Clockfrequencyvs.SER(eightchannelMatlabsimulation) ........... 108 4-21Channelnumbervs.SER(Matlabsimulation) ................... 109 5-1Schematicofsinglestagegmamplier ....................... 111 5-2Equivalentcircuitofthesinglestagegmamplier ................. 113 5-3Equivalentcircuitofthesinglestagegmamplierwithnegativeinput ...... 113 5-4Simulatedtimedomainexample ........................... 116 5-5Simulatedtimedomainexample ........................... 117 5-6SERvs.lowfrequencysignalamplitude ...................... 119 5-7SERvs.loadcapacitance .............................. 120 5-8SERvs.inputsignalamplitude ........................... 121 5-9SERvs.inputcapacitance .............................. 122 5-10SERvs.bypassresistance .............................. 123 10

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Theincreasingneedforimplantabledevicesinbiologicalsignalrecordingsystemsrequirescompact,ultralow-powerandlow-noiseelectronics.Thecontinuousevolutionofintegratedcircuittechnologiespartiallyhelpsinmeetingtheserequirementsbyallowingfortherealizationofmorecomplexfunctionsinagivensiliconarea.Theshrinkingpowersupplyhelpsreducingthepowerconsumption,ontheotherhand,italsobringsnewchallengesintermsofnoise. Thepurposeofthisresearchistoinvestigatethefeasibilityofamulti-channelneuralrecordingsystemwithspikeoutputs.Themulti-channelsystemimposesfourmajorconstraints:largecommunicationbandwidth,simpleandcompactcircuit,lownoiseandlowpower.Theproposedsolutionistodesignanovelandsimplecurrentgeneratorwhichcanbedirectlyusedforbiphasicspikerepresentation.Thecurrentgeneratorcanconverttheinputalternatingcurrentvoltage(AC)voltagetooutputACcurrent,whileeliminatingthedirectcurrentvoltage(DC)voltage.Byusingthiscurrentgenerator,thetotalsystemismorecompactandlessnoisy.IntegratingtheACcurrent,theoutputofeachchannelisabiphasicspiketrain.Thesemulti-channelspiketrainsarethentransmittedusingtheaddresseventrepresentation(AER),whichcanimprovethecommunicationeciency.Preliminarytheoreticalanalysis,simulationresultsandchipmeasurementsshowsuitabilityforneuralrecordingapplications. 11

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Scientistshavelongrecognizedtheimportanceoftheneuronasbasicunitforinformationprocessingandinformationstorageinthehumanbrain.Unfortunately,theexperimentalmethodologiestorecordneuralelectricalactivity(localeldpotentialsandextracellularactionspotentialsorspikes)infreelybehavinganimalshavebecomepracticalonlyrecently,andstillposemanychallenges.Withup-to-dateexperimentaltechniquesandanalyticaltools,scientistshavebeenabletoextractneuralinformationanduseittogeneratereal-timecommandsforcontrollingmechanicalinterfaces[ 1 ]orstimulatingprostheses[ 2 ],leadingtothegrowingeldofBrain-MachineInterfaces(BMI). Tobetterunderstandandutilizethemechanisminneuralinformationprocessing,scientistsrequiremanysimultaneousneuralrecordingsfrombehavingsubjects.Thusitisnecessarytobuildmicroelectronicarrayswithhundredsofelectrodesandimplantthemintothebrain.Despiteagreatdealofprogressduringthepastdecades,theconstraintsonpowerconsumption,noiseperformanceandbandwidthrequiredtorecordandwirelesslytransmittheactivityfromasmallportionofthecortexarebeyondthestate-of-the-artinmicroelectronicsandpackaging.TheresearchproposedhereinaddressestheIChardwareimplementationofalow-powermultichannelneuralrecordingsystem.Inthissystem,anovelvoltage-to-currentconvertermakesthebiphasicspikerepresentationpractical.Theaddresseventrepresentation(AER)structureisusedtoimprovethecommunicationchannelutilizationeciency. 12

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1-1 ).Therelevantfrequenciesoftheseactionpotentialsrangefrom100Hztoabout7KHz[ 3 ].Normally,actionpotentialwaveformsareusuallyeitherbiphasicortriphasicwithpulsewidthsrangingfrom0.4msto3ms[ 4 ].Actionpotentialsgeneratedelectrochemicallybyindividualneuronsarethecommonlyrecordedneuralsignal.Aftertheactionpotentialisreleased,theneuronneedsasmallamounttime(typicallyabout1ms)beforeitcangenerateanotherspike,calledtherefractoryperiod. Figure1-1. Typicalextracellularneuronrecordingtechniques AsshowninFig. 1-1 ,eachelectrodeissurroundedbyseveralneurons.Thesignalsfromtheclosestneuronsarestrongandcanberegardedassignals;whilethesignalsfromfartherneuronsarenormallyattenuatedtoomuchandtheycanbethoughtasnoise.Oneelectrodemayrecordasmanyasfourorveneurons.Theresultingnoisefromdistantneuronsinadditiontothermalnoisefromelectrodescanbeashighas20Vrms.Thesignaltonoiseratios(SNR)thereforerangefrom0dBto12dB[ 4 ].Duetotheunavoidableelectrochemicaleectsattheelectrode-tissueinterface,largeDCosetsariseacrossthe 13

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6 ],whichismuchlargerthantheneuralsignalstobemeasured. Besidesactionpotentialsfromindividualneurons,researchersarealsointerestedinactivitiesoflargegroupsofneurons.Thesynchronousringofmanyneuronsneartheelectroderesultsinalowfrequencyoscillation,whichiscalledtheLocalFieldPotential(LFP).TheenergyoftheLFPinprimatepre-motorandmotorcortexhasbeenshowntocorrelatewithspecicarmreachmovementparameters[ 7 ].ThefrequencyrangeoftheLFPisnormallylessthan100Hzandcouldextenddowntolessthan1Hz. 1-2 Figure1-2. Typicalneuralrecordingsystemarchitecture 14

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Lowerpowerconsumptionisalsoanimportantconsiderationtoavoiddamagingsurroundingtissue.Researchershaveshownthataheatuxofonly80mW/cm2cancausenecrosisinmuscletissue[ 8 ]whichseverelyrestrictsthepowerbudgetforamultiplechan-nelneuralrecordingsystem.Batteriespoweringtheimplantmustbeeitherperiodicallyreplacedorfrequentlyrecharged. Sincetheneuralsignalstoberecordedhaveamplitudesoftensofmicrovoltswithfrequencyrangingfrom1Hzto7KHz,alownoiseandlowfrequencyband-passltermustbeused.ConsideringsuchtinyneuralsignalsaresuperimposedonmuchlargerDCosetsintroducedbytheelectrodes,thesystemmustaccommodatelargeinputosetsatthepreampliers,whichleavestheACcouplingsystemagoodchoice. Becausemostofthepreamplierscanprovideanintermediategainofaround40dB,theoutputsignalfromthepreamplierisstillsmall.Asecondstageamplierisnormallyusedtofurtherboostthesignal.Thenaloutputsignalcanbetransmittedinananalogformatorindigitalformatafteranalog-to-digitalconversion. 15

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Therearetwomajorclassesofelectrodes:passiveandactive.Passiveelectrodesaredenedasoneswhichdonothaveanyelectroniccircuitontheelectrodesubstrate[ 9 ].Threebasicpassiveelectrodeswidelyusedbyneurophysiologistsaremetal,glassmicropipetteandphotoengravedmicroelectrodes.Activeelectrodesarecharacterizedasoneswhichincludeelectroniccircuitsonthesamesubstrateastherecordingelectrodes.Theon-chipcircuitscanbeusedtoamplifytherecordedsignal,andchangetheoutputdataformat.Thecircuitscanalsopotentiallyminimizetheeectsofleakagefromtheoutputwires,thereforeimprovingtheaccuracyoftherecordedsignals.TherstknownattempttofabricateanactivemicroelectrodearraywasmadebyWisein1975attheUniversityofMichigan[ 10 ]. Tooptimizetheperformanceoftheelectrodes,threeaspectsshouldbecarefullyconsideredintermsofACfrequencyresponse,DCdrift,andnoiselevel: 1.TheACfrequencyresponse:Sincethefrequencyoftherecordingsignalextendsfrombelow1Hztoaround7KHz,theelectrodesmustnotattenuatethesignalwithinthisfrequencyband. 2.TheDCshift:OneofthemajorchallengesininterfacingelectronicstoarecordingelectrodeistherandomwanderingoftheDCvoltage.TheDCpotentialbetweenanelectrolyteandametalelectrodeissubjecttosubstantialvariationsandcanbeashighas50mVforagoldsurface,whichisaround1000timeslargerthantheneuralsignaltoberecorded. 16

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4 ].Theelectrodenoiseresultsfromtheneuralbackgroundnoiseandthermalnoisewhichisrelatedtotherecordingbandwidth. Toachieveaverylowcutofrequency,alargetimeconstantisrequired,whichmeanseitheralargecapacitor,alargeresistororboth.SomeinstrumentationampliersutilizeexternalcapacitorsintherangeofnanoFaradstocreatealowenoughcut-ofrequency[ 4 ].Suchlargecapacitorsareimpracticalforfully-integratedapplicationswithcurrenttechnology.Whenamultichannelrecordingsystemisconsidered,thisproblembecomesevenmoresevere. BasedonHarrison'sdesign[ 6 ],ChenandHarrisfromtheUniversityofFloridahaveuseddiode-connectedPMOStransistorsactingas\pseudo-resistors"todevelopalow-powerlow-noisefullyintegratedneuralamplier(bioamplier)[ 11 ].The\pseudo-resistor"hashugeresistance(greaterthan100G)whileoccupyingaverysmallarea.Thispropertymakesitpracticaltofullyintegrateanamplierwithaverylowcutofrequency. 17

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4 12 ].Formultichannelneuralrecordingsystems,thenumberofoutputleadswillincreaseasthenumberofrecordingchannelsincreases.Ananalogmultiplexercanbeusedtoreducetheoutputleads[ 13 ].Theampliedanalogsignalcanalsobedigitizedandthentransmitted. Formoreadvancedsystems,thedataandpowertransferbetweentheimplantunitandtheoutsideworldcanbeachievedthroughawirelesschannel.Recordedsignalscouldbedigitizedbeforetransmissionwhichrequiresanon-chipADCtoenhancethesignal-to-noiseratio(SNR).Toreducethedatarate,limitedon-chipdigitalprocessingsuchascompression[ 14 ]andspikedetectioncanbeused.Ontheotherhand,theADCandmodulatorsincreasethedieareaandpowerconsumptionofthesystem. Comparedtoanalog,digitalsignalsaremuchmorerobusttotransmit,areeasytostoreandcanbeprocessedbypowerfuldigitalalgorithms.However,aconventionalADCusingNyquistperiodicsamplingisnotasuitablechoiceduetoitslargepowerconsumptionwhenincreasingtheresolution.Onesolutiontothislimitistoemploytheintegrate-and-re(IF)representation[ 11 15 ].Single-directionspikerepresentationhasbeenproventoreducetherequiredtransmissiondatawhilestillkeepingthesignaldelity[ 11 15 ].However,togenerateunidirectionalIFspikes,theexistingsingle-directionspikegeneratorhastoshiftthecurrenttoguaranteeonlypositiveoutputs.Theresultingprob-lemistheshiftingDCincreasestheoverallringrateandthuswastescommunicationbandwidth,andalsowastespower.Tosolvethisproblem,thebiphasicspikerepresenta-tionwasdevelopedforfurtherdatareduction[ 5 ]. Anotherchoicetocompressthetransmissiondataistojusttransmittheexacttimingofeachactionpotential,whichisassociatedwiththespikedetectiontechnique.Eventhoughthereisadebateaboutwhethertheneuralinformationisencodedintherate 18

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16 ].Thedetailedinformationaboutspikedetectionandspikesortingcanbefoundin[ 16 ]. 17 ]. Figure1-3. Threegenerationsofrecordingsystem Fig. 1-3 showsthethreegenerationsofhardwarerecordingsystemproposedintheUFBMIproject.Intherstgeneration,theneuralsignalwillbedirectlyampliedby80dBandtheanalogoutputwillbesampledwithacommercialproduct.Inthesecondgeneration,thedierentialneuralsignalwillberstampliedby40dB.TheboostedsignalwillthenbeencodedbyabiphasicIFneuron.Whentherearemorethanonechannelinthissystem,anAERreadoutcircuitisneededtomultiplexthesechannels.Thethirdgenerationremovesthepreamplierusedinthesecondgeneration.Whennecessary, 19

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1-3 ).InChapter3,anovelvoltage-to-currentconverterispresented(thesecondblockingeneration2inFig. 1-3 ).Thiscurrentgeneratormakesthebiphasicspikerepresentationpractical.Thesimulationresultswhenusedasthesecondstagearepresentedtherewithsomesystemanalysis.Somechipmeasurementresultsincludingthesingletoneandneuralsimulatorsignalwillalsobegiven.Chapter4combinesthewidelyusedaddresseventrepresentation(AER)tothespikerepresentation(thefourthblockingeneration2inFig. 1-3 ),anda8-channelbiphasicIFAERsystemisproposed.Thissystemtransfers8channelbiphasicIFoutputswith4readoutleadsandthusgreatlyimprovesthecommunicationchanneleciency.Somesimulationandchipmeasurementresultswillbeshowninthischapter.Thebiphasicspikerepresentationdiscussedinchapter2hastobeusedinthesecondstage,wheretherststageconvertsthedierentialneuralsignalintosingle-endedsignalandbooststhesignallevel.Tosimplifythecircuitdesign,thesinglestagebiphasicspikecircuitisproposed.TheCadencesimulationandcircuitanalysiswillbegiveninchapter5(therstblockingeneration3inFig. 1-3 ).Atlast,theconclusionsarediscussedinChapter6. 20

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Alow-noise40dBbio-preamplierwasdesignedandtestedaspartoftheUniversityofFloridaBMIproject[ 11 ].However,consideringthetypicalneuralsignalshaveamplitudesof50{500V[ 3 ],theoutputfromthepreamplierhasamplitudeof5{50mV,whichisstilltoosmallforinputtocommercialADCs.Therefore,asecond-stageamplierisdesignedtofurtheramplifythesignal. 6 ]andlaterusedbyCheninthepreamplier[ 11 ],whichusesacapacitor-feedbacknetwork.Anotherversionconsistsofaresistor-feedbacknetwork.Fig. 2-1 showstheschematicofeachamplier.Bothstructuresoperatewitha2.5Vpowersupply. Intheresistor-feedbackamplier,R1andC1consistofahigh-passlter,whichcanremovetheDCcomponentoftheoutputsignalfromthepreamplier.Withoutthishigh-passlter,theoutputDCosetfromthepreampliercaneasilydrivethesecond-stageamplierintothesaturationregion.ThemidbandgainisdeterminedbytheratioofthetworesistorsR3=R2.ThisampliercircuitwasfabricatedintheAMI0.6three-metaltwo-polyprocesswithadesignedgainof40dB.Usingpolyresistors,R1wassetto9.4M,R2to14.29KandR3to1.429M(allthesevaluewereextractedinCadencefromthelayout).C1wassetto180pFusingpoly-to-polycapacitors.C2wasusedtosimulatetheexternalcapacitorload(includingthepackageandtheprobe)andwassetto16pF.Thiscapacitorwasnotinsidethechiplayout.Sincetheextracellularactionpotentialsrangefromapproximately100Hzto7KHzinthefrequencydomain[ 3 ],C1andR1needtoprovideacutofrequencylowerthan100Hz.Thechosenvaluessetthecutofrequencyat94Hz. ThesimulatedfrequencyresponseusingCadencespectreSisgiveninFig. 2-2 .Theamplierwasdesignedtohavealowcutofrequencyof94Hzandhighcutofrequency 21

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(b) Figure2-1. Schematicsofsecond-stageamplier:(a)Resistor-feedbacknetwork;(b)Capacitor-feedbacknetwork(therealcircuithas6diode-connectedtransis-tors). of19KHz,withthemidbandgainof40dB.Sincethepreamplierhascutofrequenciesof0.3Hzand5.4KHz[ 5 ],thehighcutofrequencyofthesecond-stageamplierwillnothavemucheectonthenaloutputsignal.The94Hz-low-cuto-frequencywillremovetheLocalFieldPotential(LFP)signalfromthepreamplieroutputsignal.Thisisoneofthedisadvantagesofthisstructure,howevermostneuronresearchersignoretheLFPanyway.Inthisresistor-feedbackstructure,on-chipresistorsandcapacitorsrequiresuchhugeresistanceandcapacitancethattheytakeuptoomuchchiparea.Infact,theresistorandcapacitortogetherusemorethan90percentofthelayoutareainthetestchip.Thisisthemajordisadvantagesofthisstructure.Anotherdisadvantageisthattheresistorscontinuouslyconsumepower,whichisveryserioussincethevaluablelayoutareaprevents 22

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Resistor-feedbackamplieralternatingcurrentvoltage(AC)amplitudere-sponse Thecapacitor-feedbackamplierwasdesignedtoavoidtheabovedisadvantagesintheresistor-feedbackamplier.Inthisstructure,thecapacitorratioC1/C3determinesthemidbandgain,whileVrefand6diode-connectedtransistorstogetherprovidestheDCoperationbias.Itwasclaimedthatwhenthevoltagedierenceacrossasinglediode-connectedtransistorislessthan0.2V,thediode-connectedtransistorcanbeviewedasa\pseudo-resistor"witharesistancelargerthan1011[ 11 ].Sincemostactionpotentials 23

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Capacitor-feedbackamplierACamplituderesponse Comparedtotheresistor-feedbackamplier,thiscapacitor-feedbackversionhastwoadvantages.First,sincethesignalpathisjustacapacitornetwork,nopowerwillbeconsumed.Second,thelayoutofthiscircuitisalsomuchmoreareaecient.Forexample,inthetestedchip,thepoly-to-polycapacitorsC1andC3weresetas20pFand200fFrespectively.C2wasusedtosimulatetheexternalloadcapacitorandwassetto16pF.Thiscapacitorwasnotincludedinthechiplayout.Thediode-connectedtransistorsnormallyareminimumsize(1.5/0.6in0.6technology).Fig. 2-3 showsthesimulatedfrequencyresponseusingCadencespectreSwheretheamplierhascutofrequenciesof0.3Hzand19KHzwiththemidbandgainof39.9dB.BoththeLFPandtheactionpotentialswillbeampliedwiththisamplier.Similartotheresistor-feedbackamplier,thisstructurealsohasaDCosetproblem,whichpossiblycomesfromthesubstratecurrentofthediode-connectedtransistors.ThisDCosetincreaseswiththenumberof 24

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SchematicoftheOperationalTransconductanceAmplier(OTA)withclassABoutputstage Fig. 2-4 showstherstdesignoftheOTAusedinthe40dBsecond-stageampliers.ThisisatypicaltwostageOTA.TherststageisaP-typeinputdierentialpairloadedwithWilsoncurrentmirrors.Acascodecurrentmirrorisusedtoconvertthedierentialoutputintoasingle-endedoutput.DuetothehighoutputimpedanceofthecascodecurrentmirrorandtheWilsoncurrentmirror,therststageprovidesalargegain: whereGmisthetransconductanceofdierentialinputpair,andRoutisthecascodecurrentmirroroutputresistanceparallelconnectedwiththeWilsoncurrentmirroroutput 25

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Thesecondstageisavoltagefollowerfollowedbyasimpleclass-ABoutputstage.M13andM16areDCvoltageshifterswhileM17andM18formapush-pullcommon-sourceoutputstage.Thissecondstagealsoprovidesintermediatesignalgain,gm17(ro17kRL)orgm18(ro18kRL),dependingonwhichtransistorisactive.Thevoltageshiftercontrolsthequiescentcurrentoftheoutputstageandtheclass-ABoutputstagecansinkorsourcemorecurrentwhennecessary.Inaddition,thiscommon-sourceoutputstageprovidesarail-to-railoutputrange,whichisexpectedinthis40dBsecond-stageam-plier.TheCadencesimulationshowsthattheoutputDCvoltagerangesfromVSS+0.4VtoVDD-0.4V.ThisDCoutputrangeisenoughformostactionpotentials.However,whentheactionpotentialamplitudeisgreaterthan400V,therewillbesomedistortionintheoutput.IncreasingthequiescentcurrentcanincreasetheoutputDCrangewhileconsumingmorepower. ACresponseoftheclassABOTA 26

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18 ].Assumingthat10pFwillbeprovidedbytheexternalload,thenatotalloadcapacitorof16pFshouldbeusedinthesimulation.WhenC1issetto2.5pFandtheOTAisloadedbya16pFcapacitor,thesimulatedACresponseisgiveninFig. 2-5 .TheDCgainis137dBandthephasemarginis90owith-40dBfeedbackratio. SchematicoftheOTAwithclassAoutputstage TheclassABoutputstageisgoodatprovidingalargeloadcurrenttoaresistiveload.Inourcase,theloadwillmostlikelybeacapacitor,therefore,asimpleclassAoutputstageOTAwillbegoodenoughforthisamplier.Fig. 2-6 showstheseconddesignoftheOTA.ComparedtotheclassABOTA,bothcongurationshavethesamerststage.Intermsofthesecondstage,theclassAOTAjustusesM13andM14forDClevelshift.M15andM16areusedtoprovidetheclassAoutputstage.ThegainfromtherststageissameasthatofclassABOTA,whilethegainfromthesecondstage 27

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ACresponseoftheclassAOTA isgm16(ro16kro15kRL).RandC1areusedtoprovidetheMillercompensationandtheirvalueshavetobedeterminedfromCadencesimulationwithaloadcapacitor.Whentheloadcapacitorof16pFisusedintheCadencesimulator,RandC1canbesetto175Kand2.5pFrespectivelytoachievearound90ophasemarginfor40dBamplier(seeFig. 2-7 ).TheDCgainofthisclassAOTAisaround126dB,whichisalittlebitlowerthanthatofclassAB. Bothoftherail-to-railOTAshaveatwostagestructureandtherststagehasahugegain,thusthesecondstagehaslittlecontributiontoinput-referrednoiseandwillbeneglectedintheanalysis.Intherststage,M7M10arecommongatetransistorsandtheirnoisecontributionisnegligible.Assumingthatthiscircuitisperfectlymatched, 28

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FromEq. 2{3 ,itisclearthattheinput-referredthermalnoisecanbereducedbyin-creasinggm1ordecreasinggm3andgm11.Thestraightforwardapproachtoachievetheseistoincrease(W/L)1;2ordecrease(W/L)3;4;5;6,(W/L)11;12.However,thesizesandthetransconductanceofM3M6andM11M12arerelatedtothesecondandthirdnon-dominantpolesby!i'gmi=Ci,whereCiisthetotalcapacitanceseenbythegateofMi.Reducingtheirsizes(reducingthegm)willpushthesepolesclosetothezeroandmayintroducestabilityproblems.Consequently,thereisatradeobetweenstabilityandinputreferredthermalnoise. SincetheickernoiseisinverselyproportionaltotheWLofthetransistors,onemethodtodecreasetheickernoiseistoincreasethetransistorarea.However,withtheincreaseofthetransistorarea,theassociatedparasiticcapacitorsarealsoincreased,thereforepossiblyintroducingthestabilityconcerns.Ontheotherhand,thetotalinput-referrednoiseofthecapacitor-feedbackamplierisrelatedtothatofOTAby: whereC1,C3areshowninFig. 2-1 andCinisOTAinputparasiticcapacitor.WithincreasingWLoftheinputtransistors,Cinandalso 19 ]andPMOStransistorsarechosenforthedierentialpairforthisreason. 29

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Characteristicsofsecond-stageamplier Capacitor-feedbackAmp Resistor-feedbackAmp 5V 5V Powerconsumption Gain InputDCoset 15mV 15mV Lowcutofrequencies Highcutofrequencies Layoutarea VSS+0.45VDD-0.5 VSS+0.45VDD-0.5 Duringallthemeasurementsetups,theOTAwasbiasedwith8Acurrent.First,theDCcharacteristicsweretestedbasedon10resistor-feedbackampliers.Ofthe10channels,4channels'DCosetwerelessthan1mV;3werelessthan2mV;2werelessthan3mVand1waslessthan5mV.TheresultingmaximumoutputDCosetislessthan500mV.Apparently,suchsmallDCosetisnotabigissueinthisapplicationconsideringthepowersupplyandthesignaldynamicrange,whichwillalsobeveriedbythefollowingmeasurementresults. AnAgilent33220Asignalgeneratorwasusedinthetesting.ThemeasurementresultsaresimilartotheCadencesimulation.Thegainisaround40dB,andthecutofrequenciesalsomatchtheCadencesimulation.TheminimumandmaximumDCoutputvaluesare0.45VandVDD-0.5V.Oneofthechipsincludestherst40dBamplierdesignedbyChen[ 11 ]cascadedbytheresistor-feedback40dBamplierandthiscascaded80dBamplierwasalsotested.ThesignalfromtheAgilent33220Awasrstattenuatedby40dBandthenfedintothe80dBamplierasinputandthemeasurementresultsverifythesimulation.Thespecicationsofthesetwosecond-stageampliersarelistedinTable 2-1 30

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2-8 .Theneuralactionpotentialswithamplitudeofaround1:0Vareclearandthetotalgainisaround80dB.Whenthesetwostageswerefabricatedinthesamechip,nomatterwhethertheoutputfromthepreampliertoinputofthesecond-stageamplierwasinternallyorexternallyconnected,therewasalwaysasteadyoscillationoncetheinputisconnectedtotheneuralsignalsimulator.Theoscillationfrequencyisaround6KHzanditcanbenelyadjustedbythebiascurrent.However,thesesamesetupsalwaysworkverywellwiththeAgilent33220Asignalgenerator.Wesuspectthatthisoscillationcomesfromtheinputimpedancemismatchandthesubstratepowersupplykick-backduetotheheavysubstratedoping. Measurementresultsfromneuralsignalsimulator:(a)Resultsfromthecapacitor-feedbackamplier;(b)Resultsfromtheresistor-feedbackamplier;(c)Neuralsignalsimulatoroutput. 31

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20 ]. Inspiredbyresearchresultsinneurosciencethatsuggestbiologicalsystemsrepresentsensoryinformationusingthetimingofall-or-nothingactionpotentials[ 21 ],alow-powerpulsesignalrepresentationcircuithasbeenproposedforneuralrecordingapplications[ 11 15 ].Thiscircuitconvertsananalogvoltagewaveformtoapulsetrainandtheoriginalanalogsignalcanbereconstructedwithadigitalalgorithmundercertainassumptions.Theexistingpulseoutputcircuitconvertsthevoltagetoacurrentthatwasshiftedtoguaranteepositiveonlyoutputs.Thepositivecurrentwasthenfedintoasimpleintegrate-and-re(IF)neruoncircuitforgeneratingaspiketrain.EventhoughthiscircuithasbeenshowntoencodetheoriginalsignalwithhighSNR(103dBinMatlabsimulation),therearestillmajorimprovementsnecessarytoreducethedatarateandtheoverallpowerconsumption. Byshiftingthecurrentsothatthereisonlypositivecurrent,theoverallringrate,thepowerconsumptionandtherequiredcommunicationbandwidthhavebeengreatlyincreased.Theextremecaseisthatwhenthesignalduringsomeperiodiszero,theshiftedsignalwillstillgenerateunnecessaryspikes. 32

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Schematicofthebiphasicpulseconverter Tosolvethisproblem,abiphasicspikerepresentationisproposed[ 11 ].Ratherthanshiftthesignaltobepositiveonly,abiphasicmodespikegeneratorsusingtwocomparatorswithdierentthresholdsisimplementedinFig. 3-1 .Asinglecapacitorisusedtointegratetheinputcurrentbutapositiveandnegativethresholdareimplementedusingtwocomparators.Whenthevoltageacrossthecapacitorrisesabovethepositivethreshold,a\positive"spikeisgenerated;similarlya\negative"pulseiscreatedwhenthevoltagedropsbelowthenegativethreshold.Aftereitherspikeisgenerated,thevoltageonthecapacitorisresettoamidrangevoltagevaluebythedigitalcontrolcircuit.Whentheinputcurrentiszero-valued,nospikewillbegenerated;ontheotherhand,iftheamplitudeoftheinputcurrentishigh,theringratewillbecorrespondinglyhigh.Asimulationforaspeechsignalhasshownthatthisstructuredramaticallyreducetheringratewithoutsacricingthesignaldelity[ 5 ]. Eventhoughthiscircuithasmanyadvantagescomparedtotheunidirectionalpulserepresentation,thecircuittogeneratetherequiredcurrenthasbeenaproblembecausethiscurrentgeneratormustbeabletorejecttheDCcomponentofthesignalandconvertonlytheACvoltagetoACcurrent.ProperDCbiasingmustbesettoallowtheOTA(operationaltransconductanceamplier)tooperateinasuitableregion.Atthesame 33

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Schematicofthegmamplier Fig. 3-2 showstheschematicofthegmamplier,whereM1andM2aretwodiode-connectedPMOStransistors.Theyactas\pseudo-resistors"withhugeresistancegreaterthan1011.Fromtheintuition,thishugeresistorcanbeviewedastheDCpasspathandACstoppathorthiscircuitcanbeseenasaDCclosedloopandACopenloop.Theclose-loopedDCcongurationforcestheDCvoltagesatthenegativeinputnodeandoutputnodeoftheOTAtofollowtheDCvoltagexedbythepositiveinputnodeVrefwhiletheopen-loopedACcongurationfullyutilizesthehighopen-loopgainofthisOTA.ThiscircuitrejectstheDCsignalandampliestheACsignalofinterest,whichmakesitsuitableforthecurrentgenerator.AnotheradvantageofthiscircuitisthattheOTAisconguredasavoltagefollowerforDCoperationsothattheDCosetintroducedbytheinputdierentialpairwillnotbeamplied.Forexample,iftheOTAhasa5mVoset,whichisatypicalvalue,thentheoutputosetwillbealsoaround5mV.Thisosetrangeistolerableformoderateaccuracyapplications.Forthespecialneuralrecording 34

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Figure3-3. Equivalentcircuitofthegmamplier Tounderstandtowhichextentthisgmamplierworks,adetailedtransferfunctionanalysisisconducted.Tosimplifythederivation,theOTAismodelledasonewithtransconductanceofgmandoutputresistanceofr0.TheequivalentcircuitofthegmamplierisshowninFig. 3-3 wherethe\pesudo-resistor"isrepresentedbyRandtheloadcapacitor(orintegratingcapacitor)byCL. Firstnotethat (IxGmVx)(r0 thatis, 1+Gm(r0 HereRxistheimpedancelookingintotherightsideofthecircuit.Basedonthisequation,thetotalcurrentIxcanbewrittenas DerivingtherelationshipbetweenVinandVoutgives: 35

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3{1 toEq. 3{4 ,thetotaltransferfunctionofthisgmampliercanbewrittenas (1+j!C1R)(1+j!CLr0)+r0(Gm+j!C1):(3{5) Basedonthistransferfunction,itisapparentthatthissystemhasonezeroandtwopoles.Thezeroliesattheoriginsothatthegainrstincreasesat20dBperdecade.Itisdiculttolocatethesetwopolesforthegeneralcase.However,insomespecialcases,thesetwopolescanbesolved. Tosolveforthesetwopoles,thedenominatorissetequaltozero: (1+j!C1R)(1+j!CLr0)+r0(Gm+j!C1)=0:(3{6) Iftheparametershavethesetypicalvalues: Eq. 3{6 canbesimpliedas (j!)2RC1r0CL+(j!)RC1+r0Gm'0:(3{11) whichcanbefurthersimpliedas (j!+r0Gm Twopolesarestraightforward: 36

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3{5 canberewrittenas !0 !0)2+1 !0)+1:(3{14) with ACresponseofthegmamplier:(a)Amplitudeoftheamplierresponse;(b)Phaseshiftoftheamplierresponse. Fig. 3-4 showsthefrequencyamplituderesponseandthecorrespondingphaseshiftfromaCadencesimulationusingR=1011,theotherparametersaresetbyEq. 3{8 toEq. 3{10 .ThesimulationresultsmatchwithEq. 3{14 verywellexceptthatthepeakgainhaslessthan10dBdierence. 37

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3.3.1IdealIntegrate-and-FireNeuronandNonidealities Idealtwo-stagesystemforspikerepresentation Theidealintegrate-and-re(IF)neuroncanbeconsideredasalow-passlterwithapoleatzeroandtheoutputresistanceofinnity.Thereforealltheinputcurrentgoesintothecapacitor.Inaddition,tosatisfyingthebandwidthrequirement,thesignalmustbelteredrst.Theidealtwo-stageIFsystemcanbeshownasFig. 3-5 Figure3-6. Schematicoftheintegrate-and-re(IF)neuron Inthetimedomain,theoperationofthisIFneuroncanbesimplydescribedasfollows.OncethevoltageontheloadcapacitorVcapcrossesthethresholdVth,aspikeisgeneratedandthevoltageisresettotheanalogground.Aftersomerefractoryperiod,the 38

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3-6 ).Thespiketimestieandtibmustsatisfythefollowingrelation: Infact,aftertheneuronisreset,thenewintegrationprocesscanbeviewedastheresponsewithinputofx(t)andthesystemimpulseresponseh(t).IntheidealIFneuron,theimpulseresponseis1 3{16 Therearetwosignalreconstructionmethodsfromthespiketrain:theiterativemethodandtheclose-formorweightedlow-passkernelWLPKmethod.Interestedreaderscanndadetaileddiscussionin[ 5 ]and[ 15 ].Forthereader'sconvenience,theWLPKmethodisbrieylistedhere. Assumethepulsewidthismuchlessthanthepulsetimeintervalandcanbeignored,thespiketrainoutputcanbewrittenas Asucientboundaryconditionforperfectreconstructionrequires: 2fmax;8i(3{18) wherefmaxinthemaximumfrequencyofthebandlimitedinputsignalx(t).LetRti+1tix(t) 39

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15 ]. Followingtheabovereconstructionprocedure,theMatlabsimulationcanreconstructtheoriginalsignalx(t)withSER(signaltoerrorpowerratio)of103dB.However,inarealisticsystem,thereisalwaysniteoutputresistanceduetothecurrentgeneratorblock.Duringtheintegrationprocess,theresistorleakssomecurrentandintroducesanerrorinreconstruction.ThisneuronmodeliscalledtheleakyIFneuron.Forexample,iftheOTAisusedtogeneratethecurrent,theoutputresistanceoftheintegratoristheoutputresistanceoftheOTA,whichisnormallyverylarge(seeFig. 3-7 ).Inthiscase,theintegrationisnolongeranidealprocess.Thevoltageontheloadcapacitorisinfacttheconvolutionofthecurrentandthesystemimpulseresponseet r0C.Thesignalcanstillbeperfectlyreconstructedifthevalueofr0isknownexactly.Thedetailedanalysisforthisproblemcanbefoundin[ 15 ].Actually,thisleakyIFmodelcanbeusedtorelaxtheconstraintontheamplier.Forexample,aresistance-knownresistorcanbeintentionallyaddedparalleltotheloadcapacitor.Inthiscase,theaddedresistanceismuchlessthantheOTA'soutputresistance,andtheleakagefromtheOTA'soutputresistancecanbeignored.Sincetheaddedresistanceisalreadyknown,itcanbedirectlyusedforperfectreconstruction.Theotherbenetofusingthismodelisthattheleakagecanreducetheoutputspikerate,whichcanfurtherrelaxtherequirementonthepowerconsumptionandthecommunicationbandwidth. 3-1 byFig. 3-2 leadstothebiphasicIFneuronimplementation.Thiscurrentgeneratorisasecond-ordersystemandtheoutputresistanceisaectedbythefeedback,sothattheanalysiswillbemorecomplicated. First,theintegrationprocessneedstobeanalyzedbeforefurtheranalysis.Everytimeaftertheneuronisreset,thevoltageonthecapacitorfollowstheconvolutionbetweentheinputsignalVin(t)andthesystemresponseh(t).So,therststepistoestimatethe 40

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SchematicofthepracticalIFneuron systemimpulseresponseh(t).BasedonEq. 3{11 ,thes-domaintransferfunctionis: (1+sC1R)(1+sCLr0)+r0(Gm+sC1):(3{22) WiththeassumptionsthatGmR1,RC1CLr0;r0C1,r0Gm1andGm 4C1r20,whicharetrueinourapplication,thetransferfunctioncanbefurthersimpliedas s2C1RCLr0+sC1R+r0Gm=Gm 2CLr0)2+(Gm 4C21r20)Gm 2CLr0)2+Gm 2CLr0 2CLr0)2+Gm 2CLr0 2CLr0)2+Gm Considerthat1 2CLr0q 2CLr0r (3{24) 41

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Impulseresponseofthegmamplier WiththeparametersspeciedbyEq. 3{8 3{9 andEq. 3{10 ,andR=1011,theimpulseresponseisplottedinFig. 3-8 .Thisisacosinewavewithexponentialdecayingamplitude.Duringthesystemoperation,whenthevoltageontheloadcapacitorCLVoutequalsthethreshold,aspikeisgenerated.Atthesametime,thevoltageonthecapacitorisresettoanalogground.Afterthereset,thenextintegrationstagebeginswithinitialstateofVout(tib)=0untilVout(tie)=Vthandthesecondspikeisgenerated.ThisprocesscanbedescribedastheconvolutionbetweentheinputvoltagesignalVin(t)andtheimpulseresponsefromtheinputvoltagetotheoutputvoltageh(t)(thisimpulseresponsehasalreadyincludedtheintegrationcapacitor): 42

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CL=Vth:(3{26) wherei(t)meansthecorrespondingcurrentintegratedovertheintegrationcapacitor.TheintegrationinthisequationisusedtorepresenttheIFneuron'sintegrationprocess.Theexpressionofi(t)canbederivedfromEq. 3{24 toEq. 3{26 Theclose-formreconstructionalgorithmforthebiphasicspiketrainisverysimilartothatoftheunidirectionalspiketrain.Chenhasthedetailedproofin[ 5 ].ThemaindierenceisthatVthhasjustonevalueintheunidirectionalspiketrain(seeEq. 3{21 )whileithavetwovaluesinthebiphasicspiketrain.Iftheleakycurrentisnotconsideredinthereconstructionalgorithm,theachievedSERisaround80dB.Theerrorsignalisdenedasthedierencebetweentheoriginalsignalandthereconstructedsignal.TheSERisthepowerratiobetweentheoriginalsignalandtheerrorsignal. Fig. 3-9 showsthereconstructedsignalcomparedtotheoriginalsignal.Theoriginalsignalisthesuperpositionofvesinewaveswithfrequencyof0.1Hz,10Hz,100Hz,1000Hzand5000Hzrespectivelyandamplitudeof0.03V.Thepositiveandnegativethresholdsare0.4Vand-0.4Vrespectively.ThestepsizeintheMatlabsimulationis1ns.Thetotalnumberofspikeswithin1.8msis171.ThecircuitparametersusedfortheMatlabsimulationarethesameasthoseusedforgeneratingtheimpulseresponseinFig. 3-8 .Theoriginalsignalandthereconstructedsignalarenormalizedforeasycomparison. 43

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Simulatedtimedomainresults:(a)ThesignalontheloadcapacitorVcap;(b)Comparisonbetweentheoriginalsignalandthereconstructedsignal(bothsignalsarenormalized);(c)Errorsbetweentheoriginalsignalandtherecon-structedsignal. Ifthecircuitparametersareknown,thecoecientmatrixAinEq. 3{20 canberecalculatedusingthefollowingequation: Thiscoecientmatrixiscalibratedwiththeimpulseresponse,sothatthereconstructionsignalcanachievemuchhigherSER.ThereconstructedsignalusingthismatrixisshowninFig. 3-10 andtheachievedSERis102dB. Evenifitispossiblethattheoriginalsignalcanbeperfectlyreconstructedfromthespiketraingivenknownparameters,inpracticetheparametersr0andRareusuallysignal-andprocess-dependenttermsandexhibitsomenonlinearityandunpredictability. 44

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Simulatedtimedomainresults:(a)Comparisonbetweenoriginalsignalandreconstructedsignal(bothsignalsarenormalized);(b)Errorsbetweenorigi-nalsignalandreconstructedsignal. Forexample,r0isinverselyproportionaltothebiascurrentintheoutputstage,andRisespeciallydependentonthevoltageacrossthetwo\pseudo-resistors".Itisdiculttohave\perfect"reconstructionperformancebyapplyingtheclose-formalgorithm.There-fore,wecantreatthissystemasanidealneuronduringreconstructionandinvestigatetheperformancelimitationduetothecurrentleakage. Iftheaccuratechargeleakagethroughtheoutputresistorcanbecalculated,theexactintegrationvalueoftheinputsignaloverthisintegrationperiodcanbeobtainedandtheoriginalsignalcanbeperfectlyreconstructedmathematically.Therefore,itishelpfultoestimatethereconstructionperformancebyinvestigatingtherelationshipbetweenthechargeleakageandtheinputsignal.SincethebiphasicIFneuronusestheACcoupling 45

PAGE 46

and cos(x)1x2 Tosimplifythenotation,aandbareusedtorepresent1 2CLr0andq 3{25 ,wecanobtain: 2Ti2+a (3{30) 46

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(3{31) Thereforetheleakagechargefori-thintegrationperiodis: Thereasonthatabsolutevalueisusedhereisthattheoutputcurrenthasreversedphasecomparedtotheinput.Theerrorisjustintroducedbyabsolutecharge. Thecorrespondingnoisepowerduetotheleakagechargecanbecalculatedas(usingEq. 3{21 ): 47

PAGE 48

TheSER(signaltoerrorratio)duetotheleakageis: (3{35) whereE[(Pih0i(t))2]PiE[(h0i(t))2]isusedfortherstapproximation.Duringthesecondapproximation,thelasttermofthedenominatorisignoredbecauseitisverysmallcomparedtothersttwoterms. Eq. 3{35 showsthedependenceoftheSERontheparametersofthebiphasicIFneuronandinputsignal.TheSERcanbeimprovedbyincreasingtheOTAoutputresistancer0orincreasingthebypassresistanceR.ThisargumentisconsistentwithEq. 3{24 .BasedonEq. 3{24 ,whenr0increases,theslowerexponentialdecaywillintroducelessleakagecharge.IfRisincreased,thecosinewavehassmallerfrequencyandtheslowercosinedecaycanimprovetheSER.LargerC1alsoleadstoalargerSERbyreducingthecosinewavefrequency.IncreasingGmorreducingCLalsoreducesthechargeleakageandincreasestheSER.ActuallybothofGmandCLhavetwodierenteects.First,theydeterminethegainandthereforeaectthespikefrequency.Ontheotherhand,theyalsoalternatethecosinewavefrequencyoftheimpulseresponseandchangetheleakageerror.However,comparedtothesecondeect,therstoneismore 48

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3{35 alsoindicatesthattheSERisproportionaltoE[V2in].ThereasonisthatalargerinputsignalamplitudeincreasesthespikefrequencyandhenceincreasestheSER.Itisshownthattheunidirectional-spikereconstructedsignalSERdecreaseswhentheinputsignalfrequencyincreases[ 15 ].However,inthebiphasicIFrepresentation,thefrequencyhaslittleeectontheSER,whichcanbeseenfromEq. 3{35 .ToverifytheSER'sfrequencyindependence,theresultsfromaMatlabsimulationandEq. 3{35 aregiveninFig. 3-11 .TheparametersofthebiphasicIFneuronare:C1=20pF,Vth=0.4V,Gm=30u1,r0=2:6109,R=1011,andtheinputisasingletonewithdierentfrequencyandsameamplitudeof30mV. signal-to-noiseratio(SER)vs.sinewavefrequency Basedontheaboveanalysis,thedirectiontoimproveSERisclear.DuetothepracticalsignalpropertiesandavailableCMOSprocesstechnology,therearenotmany 49

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SeveralsimulationsareruninMatlabtovalidatetheabovediscussion.Withoutadditionaldeclarations,theparametersofthebiphasicIFneuronare:C1=20pF,Vth=0.4V,Gm=30u1,r0=2:6109,R=1011,andthesignalisthesuperpositionofvesineswavewiththesameamplitudeof30mVanddierentfrequenciesof0.1Hz,10Hz,100Hz,1000Hzand5000Hz.InthefollowingguresthedottedlinewithstarsandthesolidlinewithcirclesrepresenttheresultsfromtheMatlabsimulationandEq. 3{35 ,respectively.AlltheMatlabsimulationswererunwiththestepsizeof1ns. Fig. 3-12 showsthedependenceoftheSERonthebypassresistorR.Theequationmatchesthesimulationverywellwithaslopeof20dB/decade.BothcurvespredictthatthereisaSERsaturationwhenRisabove1012.Thisisduetoothernonidealfactors. Fig. 3-13 showsthedependenceoftheSERontheOTAoutputresistorr0.Whenr0<109,theequationmatchesthesimulationverywellwithaslopeof20dB/decade.BothcurvespredictthatthereisaSERsaturationwhenRisabove1010.However,thereisaround12dBdierencebetweenthesaturationSERvalues.ComparedtoFig. 3-12 ,thesaturationhereoccursearlierthanthatofthebypassresistor.Otherthanthat,SERcorrespondingtothesaturationoutputresistoris3dBlowerthanthatofbypassresistorfromtheMatlabsimulation.ThesedierencesmeanthatthebypassresistorplaysamoreimportantroleinincreasingSER. 50

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SERvs.bypassresistance Fig. 3-14 showsthedependenceofSERontheinputcapacitorC1.WhenC1>0.1nF,theequationmatchesthesimulationwell.Otherwise,thedierencebetweentheequationandthesimulationis8dBmaximum.ThereisalsoaSERsaturationinthisgure. 51

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SERvs.outputresistance 3-15 showstheschematicoftheOTAusedinthebiphasicIFneuron.TheOTAisatypicalsingle-stageCMOSamplierwithaP-typeinputdierentialpairoperatingfroma2.5Vpowersupply.Theinputdierentialpairisloadedwithacascodecurrentmirror.Anothercascodecurrentmirrorisusedtoconvertthedierentialoutputtosingle-endedoutput.ThecascodecurrentmirrorsgiveahighoutputresistanceforthisOTA: wherebothRout10andRout14aretheoutputresistancefromacascodecurrentmirror,thus: 52

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SERvs.inputcapacitance ThisOTAjusthasonedominantpoleat!=1 3-15 arecommongatetransistors,andtheirthermalnoisecontributionisnegligible.TheinputpairM1andM2haveidenticalsizeandtheirtransconductanceisdenotedasgm1.ThecascodecurrentmirrorsM3M8alsohaveidenticalsizeandthetransconductanceisdenotedasgm3.ThetransconductanceofM11andM12isdenotedasgm11sincetheyarealsomatchedinthecircuitdesign.Therefore,theOTAinput-referredthermalnoiseshouldbe: 53

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SchematicoftheOTA Ifgm1isincreasedorgm11andgm3aredecreased,theinput-referredthermalnoisecanbedecreased.Themoststraightforwardapproachistoincrease(W/L)1;2ortodecrease(W/L)38;11;12.However,noticingthatM11isassociatedwiththerstnondominantpoleandM3,M4areassociatedwiththesecondnondominantpoles,reducingthesizesofthesetransistorswillreducethetransconductanceofthesetransistorsandpushthesenondominantpolestozero,possiblydegradingthestability.Consequently,thereisatradeobetweentheinput-referredthermalnoiseandstability. Theickernoiseisanothermajornoisesourceinlow-frequencyCMOScircuits.ItcanbedecreasedbyincreasingtheareasoftheCMOStransistors.However,theareasarealsorelatedtothenondominantpolesasdiscussedabove,whichputsarestrictionontheickernoiseperformance. Powerconsumptionisanotherbigconcerninlow-powercircuitdesign.ThestaticpowerconsumptionofthisOTAisdirectlydeterminedbythebiascurrent,whichissetto8Ainthesimulationandchipmeasurement.Reducingthiscurrentcanreducethepower 54

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3-13 showsthathigherSERcanbeachievedwhentheOTA'soutputresistanceincreases. However,therearealsosomedrawbacksonreducingthebiascurrentorpowerconsumption.ThemostimportantdrawbackisrelatedtothetransconductanceoftheOTA.Eq. 3{35 indicatesthatthereconstructionSERisdirectlyproportionaltoG2m.Therefore,higheraGmcangeneratehigherSERfromthereconstructedsignal.Increasingthebiascurrentcandirectlyincreasethetransconductance.Actually,whenGmincreases,moreoutputspikescanbegenerated,whichagainincreasesthedynamicpowerconsumption.TheabovediscussionindicatesthatwehavetotradeothepowerconsumptionwiththeSER. 3-16 .Therearethreecomponents:thegmamplier,thecomparatorsandthedigitalcontrolblock.Theyarepoweredbyindividualpowersupplytoreducethecrosscoupling,andeachpowersupplyhasitsownbypasscapacitor.Guardringsarealsousedtoeliminatethekickbacknoisefromthedigitalcircuit.Thesethreepartsareseparatedasfaraspossible.Thetotallayoutareaincludingthepadsis2.25mm2. 22 ].Thisdigitalblockisconcatenatedtothegmamplier,thusnishingthesingle-channelcircuitdesignwiththe0.6mCMOSprocess.TheCadencesimulationisrunforthesinglechannel.Theinputsignalisasinewavewithamplitudeof20mV.Thefrequencyissweptfrom1KHzto10KHzandtheinputsignallastsfor2ms.Thebiascurrentofthegmblockissetto8uAandtheintegrationcapacitorissetto20pF.ThespiketrainisthendirectlyreadoutandthesignalisreconstructedinMatlabusingtheclosed-formalgorithm.The4-parametersinewavettingmethodisusedtoestimatethe 55

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Layoutofthesingle-channelbiphasicIFneuronchip inputsignalfromthereconstructedsingletonesignalbyndingthebest-ttingsinewave[ 23 ]: Thedierencebetweenthereconstructedsignalandthettedsignalaredenedastheerror.TheSER(signaltoerrorratio)isdenedasthepowerratioofthettedsignaltotheerror.TheSERvs.inputsignalfrequencyisshowninFig. 3-17 .ThereconstructedSERvaluesrangefrom51dBto57.5dB,whichmeansmorethan8ENOB(eectivenumberofbits).ThedierencebetweentheSERinFig. 3-17 andtheMatlabsimulatedSERisduetothenonlinearityofthegmblockandthesignaldependenceoftheanalogcomparator.ThenitenumberofpulsesandthecomputationalprecisionofMATLAB 56

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ReconstructedSERvs.inputsignalfrequency alsointroducesomeerror.Therearesometradeosbetweenthereconstructionaccuracyandthepowerconsumptionofthesystem,whichwillbediscussedinthefollowingsections. 5 ].Inthegmblock,the20pFcapacitorwasimplementedwithapolycapacitorandthebiascurrentofthegmblockis8uA.Withthepowersupplyof2.5V,thestaticpowerconsumptionisaround80uW.TheDCvoltageacrosstheintegratorcapacitorwasbiasedat0Vwithavoltagefollower.Thechiphasbeensuccessfullytested. 57

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SERvs.singletonefrequency 3-18 .Fromthisgure,itisapparentthatthetestedSERisveryclosetothesimulationresults,whichprovesthatthepreviousanalysisiscorrect.Inthehighfrequencyregion,the40mVpeaktopeak 58

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Spikeratevs.sinewavefrequency inputcangenerateashighas55dBreconstructedsignal(whichmeansaround9ENOB),andthe20mVpeaktopeakinputcanalsohas50dBSER,whichisveryclosetothesimulated51dB.Duringthelowfrequencyregion,theSERisalittlebitlower.ThereisnodirectrelationshipbetweentheSERandtheinputsignalamplitude.ThestatisticsofthespikeratearealsoshowninFig. 3-19 .Itisveryclearthatthespikeratereduceswithincreasingfrequency.Thisreductiontrendisnotapparentinthelowfrequencyregionbutitismoreobviousinthehighfrequencyregion.Whentheinputsignalamplitudeisdoubled,thespikerateisalmostdoubledasexpected. Fig. 3-20 showsanexampleofthebiphasicpulsetrainoutputandtheoinerecon-structedsignal.Theinputsignalisa1KHzsinewavewith20mVpeak-to-peakamplitude.TheredcurveFig. 3-20 (b)isthereconstructedsinewavefromthepulsetrainshowedinFig. 3-20 (a)andthebluecurveisthe4-parameterttingsinewave.Fig. 3-20 (c)istheerrorbetweenthereconstructedsignalandthettingsignal.Thisreconstructedsignalhas45dBSER. 59

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Measuredreconstructiontimedomainresultexample:(a)Pulseoutput;(b)Reconstructedsingletonesignal(red)andthe4-parameterttedsingletonesignal(blue);(c)Error. Oneapparentresultisthatwhenthebiphasiccomparatorthresholdisreduced,theoutputspikeratewillbeincreased.Theincreasingspikeraterequiresmorecommuni-cationbandwidth.Ontheotherhand,moreoutputspikesalsoconsumemoredynamicpower.Therefore,itisbenecialtoincreasethecomparatorthresholdtoreducethespikerate. InunidirectionalIFneuronsystem,theACsignalisshiftedbyaDCcomponentandtheintegratedabsolutecurrentisaconstant.Theresultingspikerateisindependentoftheinputsignalfrequency.However,inthebiphasicIFneuronsystem,whentheinputsignalchangesfrompositivevaluetothenegativevalue(orviceverse),theintegratedchargeafterthelastspikegetscanceledbytheopposite-polarcharge,therefore,thetotalspikerateisdependentontheinputsignalfrequency.whentheinputsignalfrequencyincreases,thechargegetscanceledmoreoften,andtheresultingspikeratereduceswiththeincreasingfrequency.ThisanalysisactuallyveriesthestatisticsfromFig. 3-19 60

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Thresholdvs.spikerate Whentheinputsignalfrequencyislowandtherearemanyoutputspikesgeneratedduringeachhalfperiod,thecanceledchargecanbeneglected,thespikeratecanbeviewedasfrequencyindependentanditcanbewrittenas whereVinmeanstheinputsignalamplitude.Toverifytherelationshipbetweenspikerateandthecomparatorthreshold,anothertestwasconducted.Inthistesting,a800Hz40mVpeak-to-peaksingletonewasxedastheinputwhilethebiphasiccomparatorthresholdwasvariedfrom0.2Vto1.0V.ThegeneratedspiketrainwasthencollectedwiththelogicanalyzerandtheinputsignalwasreconstructedwithMatlaboinecode.ThemeasurementresultandtheresultfromEq. 3{41 withGm=60SareshowninFig. 3-21 .Fromthisgure,theoutputspikeratedecreasesfrom160Kpulses/s(withthethresholdof0.2V)tolessthan40Kpulses/s(withthethresholdof1.0V).Thistrendissimilartotheequation. 61

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Thresholdvs.SER WearealsointerestedinhowtheSERwillchangewiththereducedspikerate.ThemeasurementresultisshowninFig. 3-22 .TheSERisreducedfrom52dBto47dBwiththeincreasingthresholdandreducingspikerate,whichissomewhatexpected.Fortunately,theSERdoesnotvaryverymuch.Thistestingprovidesustherelationshipbetweenthespikerate(orcommunicationchannelbandwidthandpowerconsumption)andthereconstructionSER.Itisapparentthatthespikeratecanbegreatlyreducedwithoutsacricingtheaccuracyverymuch.Ofcoursealimitwillbereachedwherethedistancebetweenspikesviolatesthesamplingassumption. 3 ]andlastsfor1-1.5ms[ 4 ].WiththebiphasicIFencoding,theoutputspikerateissupposedtobehighintheactionpotentialregion.Ontheotherhand,ifthereisjustnoiseduringthatperiod,theoutputspikerateis 62

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Somemeasurementswereconductedtoevaluatetheperformanceofthisapplication.TheBionic128ChannelNeuralSignalSimulatorandanAgilent1693Alogicanalyzerwerethetwoprimaryinstrumentsinthistestingsetup.Asdiscussedinthepreviouschapter,theNeuralSignalSimulatorcanprovideaprerecordedneuralsignal.TheactionpotentialoutputfromthisNeuralSignalSimulatorisaround200Vpeak-to-peak.Thissignalistootinytogenerateaspikeoutput.Basedonthesingletonetesting,wethinkthatthereasonableinputsignalrangeisaround20mVpeak-to-peak.ThepreamplierdesignbyChen[ 11 ]wasusedastherststagetoboosttheneuralsignalandtoconvertthedierentialneuralsignaltoasingle-endedsignal.FollowingtheoutputofthepreamplierwerethegmblockandthebiphasicIFblock.AnAgilent1693Alogicanalyzerwasusedtorecordthebiphasicspiketrain.ThecollectedspiketrainisthenfedintoMatlaboinecode.Duringthenoiseregion,therewereveryfewspikeoutputsandthetimedelaybetweenconsecutivespikescanbegreaterthantheNyquistperiodoftheinputsignal.Asaresult,theconvergentconditionforclose-formalgorithmcannotbemetandwehavetousetheiterationalgorithmforreconstruction[ 5 ].Aftercarefulcomparison,itwasfoundthatthereconstructionsignalafterthe5thiterationprovidesthebestdelity. Fig. 3-23 showsanexampleofthebiphasicpulsetrainoutputandtheoinerecon-structedneuralsignal.Inthisexample,thebiphasiccomparatorthresholdwassetto0.4V.Theshownsignallastsfor30ms.Itisapparentthatthemeasurementresultsver-ifytheexpectation.Duringtheactionpotentialregion,therearehighspikerateoutput;ontheotherhand,whenthereisnointerestingneuralsignal,thegeneratedspikerateisverysparseasexpected.Sincethenoiseregionisnotinterestingtous,lowsignaldelitycanbetoleratedbuttheactionpotentialregionsarekeptwithhigheraccuracy.Statistical 63

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Measuredreconstructiontimedomainresultexample:(a)Pulseoutput;(b)Reconstructedneuralsignal. measureshavebeenusedtocomparethespikerateduringdierentsignalregionsandthemeasurementresultsarelistedinTable 3-1 .Inthistable,thebiphasiccomparatorthresholdhasbeensweptfrom0.2Vto0.9V,andthespikeratehasbeencalculatedduringthreedierentsignalregions.Oneisso-calledspikeburstregion,whichmeansthatisalargenumberofactionpotentialsgeneratedinasequenceandeachspikelastsfor5ms.Thesecondregionisanoiseregion,wherenoactionpotentialsaregenerated.Thelastactionpotentialregionmeansthetimeregionconcentratingoneachspikepeakwhichisnormally1ms.Bycomparingthespikeratedierenceamongthethreesignalregions,itisapparentthatthecommunicationbandwidthissaved.Forexample,whenthethresholdissetto0.4V,thespikerateduringtheactionpotentialisaround28Kpulses/s,whichisveryhigh.However,ifweaveragethespikerateduringthetotal5ms,thespikerateisdroppedto6.9Kpulses/s.Withinthesamesetup,theoutputspikerateisjust1.9Kpulses/swhenthereisnoactionpotential. 64

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Spike-ratecomparison Spikeburst Noiseregion Actionpotential 15.3K/s 6.5K/s 56.3K/s 300mV 10K/s 2.3K/s 37.8K/s 400mV 6.9K/s 1.9K/s 28K/s 500mV 6.3K/s 1.8K/s 22.5K/s 600mV 6.27K/s 1.4K/s 17.8K/s 700mV 4.5K/s 1.3K/s 12K/s 800mV 4.5K/s 0.6K/s 11.8K/s 900mV 4.2K/s 0.5K/s 10K/s Similartotheprevioussubsection,westillneedtoevaluatetheperformanceofthissystem.Thedicultyinthiscaseisthatwedonothavetheoriginalorttingsignal,thereforetheSERcannotbeusedinthisoccasion.Eveniftheoriginalsignalcanbeobtained,itisunfairtocalculatetheSERforallthesignalregion,becausetheusefulsignalisjusttheactionpotential.Thisbiphasicpulseencodingisintendedtoachievelowersignalaccuracyinnoiseregionandtoachievehighersignaldelityinactionpotentialregion. Severalmethodshavebeenproposedtocomparetheperformance.Therstmethodistocalculatethecross-correlationcoecientbetweenthereconstructedsignalandtheneuralsignal.Inthistestingsetup,theoutputfromtheneuralsimulatorispredenedandcanbeobtainedbyotheruniformedsamplinginstrument.TheTucker-DavisTechnologies(TDT)RA8GAisusedtorecordtheneuralsimulatoroutputwiththesamplingrateof24414.1Hz.Fig. 3-24 (a)showsonesectionoftheTDTrecordedneuralsignal.Theothersignalsshowninthisgurearethereconstructedneuralsignalwiththresholdof0.3v,0.5Vand0.9Vrespectively.Thecross-correlationcoecientbetweentheTDTrecordedneuralsignalandthereconstructedsignalislistedinTable 3-2 Ifthecross-correlationbetweentwosignalsisone,theycanbeexactlythesameortheycandierinamplitude.Toexcludetheamplitudeconfusion,thesecondmethodisusedtocalculatethemeanabsoluteerror(MAE)betweenthereconstructedsignalandthe 65

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Measuredreconstructiontimedomainresultexample:(a)TDTrecordedsignal;(b)Reconstructedsignal(Vth=0.3V);(c)Reconstructedsignal(Vth=0.5V);(d)Reconstructedsignal(Vth=0.9V). TDTrecordedsignalanditcanbedescribedwiththefollowingequation: whereVTDT(i)meanstheTDTrecordedsamplesandVrecon(i)indicatesthereconstructedsignalsamples. Therootmeansquareerror(RMSE)betweenthereconstructedsignalandtheTDTrecordedsignalhasalsobeencalculated: Whencalculatingtheseerrors,thepeaktopeakamplitudesoftheTDTrecordedsignalandthereconstructedsignalshavebeenrstnormalizedtoone.BothoftheMAEandRMSEresults(expressedinpercentage)arelistedinTable 3-2 66

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Statisticsresultsonthereconstructedsignals cross-correlationcoecient MAE(%) RMSE(%) 0.84 3.3 4.7 300mV 0.82 3.3 5.0 400mV 0.83 3.4 4.9 500mV 0.82 3.6 5.0 600mV 0.80 3.8 5.4 700mV 0.77 3.6 5.2 800mV 0.75 4.5 6.0 900mV 0.75 4.6 6.0 Actually,thenoiseregionsintheTDTrecordedsignalandthereconstructedsignalsarenotimportantbecausetheydonotcarryanyusefulinformation.Sincethereareveryfewspikeoutputsgeneratedinthoseregions,thereconstructedsignalsinthoseregionsshouldbepoorintermsofsignaldelity.Tobetterevaluatethesignaldelityintheusefulsignalregions(actionpotentials),wecanintentionallyzeroallthenoiseregionsandrepeatthecross-correlationcoecients,MAEandRMSEcalculation(inthesecalculations,thesignallengthhasbeenreducedcorrespondingly).TheresultsfromthezeroedsignalsarelistedinTable 3-3 .Comparingtheresultsintheabovetwotables,itisapparentthattheRMSEandMAEfromthezeroedsignalsarealwayssmallerthanthosecorrespondingunmodiedsignals.Ontheotherhand,thecross-correlationcoecientsfromthezeroedsignalsaregreaterthanthosefromunmodiedsignals.Thisobservationshowsthatthesignaldelityintheactionpotentialregionsisbetterthanthoseinthenoiseregionasexpected. AnothermethodtoevaluatethereconstructedneuralsignalistodosomespikesortingontheTDTrecordedsignalandthereconstructedsignal.Tosomeresearchers,itisthespiketimingandthespikeshapethataremostimportantsincethespikeshapeindicatesfromwhichneuronthisactionpotentialistransmitted.Infact,spikesortinghasbeenusedtoachievedatareduction.Inourevaluationprocess,ifthespikesortingresultsareveryclose(whichmeansthatiftheactionpotentialintheTDTrecordedsignalisclassiedtobeinthesameclassinthereconstructedsignalcase),itcanbesafely 67

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Statisticsresultsonthezeroedreconstructedsignals cross-correlationcoecient MAE(%) RMSE(%) 0.88 1.7 4.0 300mV 0.86 1.8 4.3 400mV 0.87 1.7 4.1 500mV 0.87 1.7 4.1 600mV 0.85 1.9 4.5 700mV 0.84 1.9 4.4 800mV 0.80 2.1 4.8 900mV 0.82 2.0 4.6 saidthatthekeyfeaturesoftheactionpotentialarekept.Theoutputfromtheneuralsimulatorispredened,andthereare3classesofactionpotentialineachchannel.Thetestingsetupusestwochannelsfordierentialinputandthereforetherearetotal6classesofactionpotentialsintheTDTrecordedsignalandthereconstructedsignal.Eachclassofactionpotentialisrepeatedafter30msinthespikeburstregion.Theachievedsignalisthe6classesofspikesrepeatingthemselvesafter30ms,ascanbeseeninFig. 3-24 Spikesortingresultbasedonreconstructedneuralsignal(Eachpaneloftherst6panelindicatesalltheactionpotentialsinthatpanelbelongtothesameclass;thelastpanelisthereconstructedsignal.) 68

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Reconstructedneuralsignalspikesortingstatistics(missingactionpotentials/totalactionpotentials) class1 class2 class3 class4 class5 class6 0/17 0/16 0/16 0/16 0/16 0/16 200mV 0/17 0/16 0/16 0/16 0/16 0/16 300mV 0/17 0/16 0/16 0/16 0/16 0/16 400mV 0/17 0/16 0/16 0/16 0/16 0/16 500mV 0/17 0/16 0/16 0/16 0/16 0/16 600mV 0/17 0/16 0/16 0/16 1/16 0/16 700mV 0/17 0/16 0/16 0/16 2/16 0/16 800mV 0/17 0/16 0/16 0/16 7/16 1/16 900mV 0/17 2/16 0/16 0/16 11/16 4/16 ApopularalgorithmcalledSpike2isusedtodothespikesorting.Spike2isapowerfuldataacquisitionsystemwhichcanalsododatacapture,experimentcontrol,recordingandanalysis.Spike2isalsoapopularneuralsoftwareforspikedetectionandspikesorting.Spike2identiesandsortssingleandmulti-unitactivitybothon-lineando-line.Itcanmarkspikesusingsimplethresholdcrossings.Formulti-unitactivity,Spike2containstoolsforsortingspikesbasedonthespikewaveformshape.AlleventscrossingathresholdarecapturedandacombinationoftemplatematchingandclustercuttingbasedonPrincipalComponentAnalysis(PCA)isthenusedtosortspikesintodierentclasses. Fig. 3-25 showsanexampleofspikesortingresultsfromSpike2.Theneuralsignalisreconstructedfromthebiphasicpulseoutputwiththresholdof0.4V.Eachrowoftherstsixrowsindicatesalltheactionpotentialsbelongingtothesametemplate.Itisclearthattherearetotalofsixclassesofactionpotentialsfoundinthereconstructedneuralsignal.Infact,alltheactionpotentialsarecorrectlysortedinthisexample.Withtheextractedsixtemplates,alltheotherreconstructedneuralsignalsandtheTDTrecordedsignalsaresortedbySpike2.TheresultsarelistedinTable 3-4 .Wecanseethatforathresholdlessthan0.7V,theSpike2sortingresultsofthereconstructedsignalareveryclosetothatofTDTrecordedsignal.ThiscomparisonveriesthatthisbiphasicIFencodingworkswellforneuralsignal. 69

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Comparisonbetweenthecorrectlyidentiedactionpotential(bluesolidline)andthemissingactionpotentials(reddottedlines) Onemaywonderwhatisthereasonforthemisclassiedactionpotentials.Wemadesomecomparisonshere.Sincemostofthemissingactionpotentialsarefromclass5,somemissingactionpotentialsfromthisclassareplottedtocomparetothecorrectlyclassiedactionpotential.ThisplotisshowninFig. 3-26 .Itisapparentthattheamplitudeisresponsibleforthemissbecausethecorrectlyidentiedactionpotentialhasalargeamplitudeinbothdirectionswhilethemissingactionspotentialshavemuchlessamplitudeinthenegativedirection. Fig. 3-27 showsthesixtime-domaintemplatesusedintheSpike2sorting.Oneachtemplateplot,thenumberonthetopleftmarkstheclassnumberandthesetemplatenumbersareorderedtomatchwiththoseinFig. 3-25 .ThecorrespondingprincipalcomponentanalysisonthesixspiketemplatesisshowninFig. 3-28 70

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Sixactionpotentialclasses(Thenumberonthelefttopmarkstheclassnumber) andthesimulationresults.Forexample,theCadencesimulationshowsthattherecon-structedSERisalwaysgreaterthan50dB,whilethechipmeasurementwiththesameinputsignalandsamesetupshowsanSERatmost50dB.Somepracticalissuescontributetothisdierence.Wewilldiscusstheseissuesinthissection. 71

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Principalcomponentanalysiscorrespondingtothesixtemplates time.Ifthedelaybetweentherecordingtimingandtheexacttimeisxed,thisdelaywillnotaectthereconstructionaccuracyanditshowsitselfasasimpledelaybetweenthereconstructedsignalandtheoriginalsignal.Orwecanseeitfromanotherpoint,attherecordedtiming,thevoltageacrossovertheintegrationcapacitorisalreadygreaterthanthethresholdusedinthereconstruction.Ifthedierencebetweentheaccuratethresholdandthethresholdusedinreconstructionisxed,thisthresholddierencewillnotaectthereconstructionaccuracyanditshowsitselfasanamplitudedierencebetweenthereconstructedsignalandtheoriginalsignal.Ontheotherhand,ifthedelayissignaldependent,orthethresholddierenceissignaldependent,someerrorwillbeintroducedinreconstruction.Unfortunately,detailedanalysisbyWei[ 15 ]provedthatthisdelayorthisthresholddierenceissignaldependent. 72

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15 ]analysis,therelationshipbetweenthebiascurrentofthecomparatorandreconstructedSERcanbederivedas kVthCo;compfavg:(3{44) where 3(Vmax1)(Vmax+1)24p 2:5(Vmax1)(Vmax+1)1:5:(3{45) Intheaboveequations,Vmaxistheamplitudeofgminputsignal,Ibiasisthebiascurrentofthecomparatordierentialpair,Co;compistheoutputcapacitanceofthecomparator,=CoxW Lisalsodeterminedbythecomparatordierentialpairandfavgdenotestheoutputpulserate.Basedontheseequations,itcanbefoundthatincreasingthebiascurrent(orthecomparatorpowerconsumption)canincreasereconstructionSER.ThistradeobetweentheSERandpowerconsumptionisveryusefulbecausewecanestimatetheminimumnecessarypowerconsumptionforsomespecicSERormaximumsignalaccuracyundersomepowerbudgetrequirement. ACadencesimulationwasruntoverifythisrelationship,andthesimulationresultisshowninFig. 3-29 .Whenthebiascurrentincreases,theSERalsoincreases.Whenthebiascurrentistoolarge,theSERsaturates.ThereasonfortheSERdroppingathighbiascurrentisnotclear. 3-2 )isthe\pseudo-resistor".InthepreviousMatlabsimulationandcircuitanalysis,itisassumedthatthis\pseudo-resistor"helpsformanidealvoltagefollowerforDCoperationandaopen-loopamplierforACoperation.Duringthechipmeasurement,wefoundthatthisresistorintroducesalargeDCosetwhenitworkedintheDCvoltagefollowerconguration.ConsideringthisDCosetVOS1inadditiontotheOTADCosetVOS2,theequivalentcircuitofFig. 3-2 canbeplottedinFig. 3-30 .IfVrefissettoground,intheidealcase(noresistorDCoset 73

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Comparatorbiascurrentvs.SER ornoOTADCoset),theDCvoltageintheoutputwillalsobeground.However,whenthereisaDCoset,theDCvoltageovertheintegrationcapacitorwillbe: 1+A:(3{46) whereAistheDCvoltagegainoftheOTA,anditsvalueisgreaterthan60dB(refertoFig. 3-4 ).Equation 3{46 canbefurthersimpliedasVoutOS=VOS2VOS1withoutintroducingmucherror.TheDCosetofdierentialinputpairinCMOSprocessisnormallylessthan5mV(refertoTable 2-1 )whilethe\pseudo-resistor"introducedosetVOS1ismuchlargerthan5mV(around100mV).Therefore,themajorpartoftheoutputDCosetiscontributedbyVOS1. Duringthechipmeasurement,itwasexpectedtosettheDCvoltageofVouttobeground(becausethelowerplateofcapacitorC2isalsoconnectedtoground).Inthiscase,afteraspikeisgenerated,theresetclockcanresetVouttogroundandthenewintegrationstartsfromground.Unfortunately,itisverydiculttosettheDCvoltageofVoutto 74

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EquivalentcircuitofgmblockwithDCoset groundinpracticaloperation.WecananalyzehowVOS1canaectthereconstructedsignalSER. Duringtheintegrationoperation,whenapulseisgenerated,thevoltageacrosstheintegrationcapacitorisresettoground.Aftereachreset,thefollowingintegrationisasuperpositionoftwotransitions.OneisthenormalintegrationasdiscussedinEq. 3{25 .Anothertransitionistheresponseofthevoltagefollowerwhentheoutputvoltageisforcedtosomeunstablevalue.ThisDCresponsecanbedescribedas whereisthetimeconstantofthevoltagefollower.Thetotalintegrationprocesscanbedescribedas whereVin(t)isthevoltageinputandtheh(t)istheimpulseresponsefromEq. 3{24 .ReplacingthesimpliedVoutOS,Eq. 3{48 canbefurthersimpliedas 75

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First,wecanestimatebasedonFig. 3-4 .WhentheOTAisconguredasavoltagefollower,the-3dBfrequencyisaround2105Hz,whichcorrespondto1u.FromFig. 3-19 andTable 3-1 ,werealizethatthespikerateisalwayslessthan100K/s,whichmeansthattheintegrationtimeforeachspikeislongerthan10us.Fort10us,1etie=1.Thisinformationcanhelptofurthersimplifytheaboveequationto: Fromtheaboveequation,itisclearthatthe\pseudo-resistor"introducedDCosetaddssomeconstanttothethreshold.InunidirectionalIFencoding,thiswilljustaddanamplitudecoecientVthVOS1 IfVOS1canbeaccuratelyestimated,wecancalculatetheexactintegrationvaluefortwodierentspikes,andtheDCosetintroducederrorcanberemovedfromthereconstructedsignal.Thisestimationcanbedonewithsomecalibrationprocessespriortoeachmeasurement.Forexample,asinewavecanbesetasinputandthegeneratedspikescanbereconstructedbysweepingtheVOS1.TheoptimalVOS1shouldcorrespondtothehighestSER.Fig. 3-31 givesanexamplehowtoestimatetheDCoset.InthisMatlabsimulation,a1000Hzsingletonewithamplitudeof0.03VwastheinputandtherealDCosetwassetto5mV.Thethresholdwas0.4V.Duringthereconstruction,theestimated 76

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SERvs.estimatedDCoset osetwassweptfrom0to10mV,andthereconstructedSERwasplottedinthisgure.Itisclearthatonlywhentheestimatedosetisequaltotheactualoset,theSERisreachingthemaximum.Whentheestimatedosetisgreaterorlessthantheactualoset,theSERdrops. EvenifitispossiblethattheoriginalsignalcanbeperfectlyreconstructedfromthespiketraingiventheDCosetvoltage,inpracticethisosetvaluecannotbeaccuratelyevaluated.Forexample,thisDCosetisnotaconstantthroughallthetimeperiod,instead,itisasignaldependentoset[ 24 ].Thereforeitwillbeinsightfultoignoretheosetintroducedbythe\resistor"duringreconstructionandinvestigatetheresultedperformancelimitation. Followingthepreviousanalysisinthischapter(fromEq. 3{30 toEq. 3{35 ),wecanderivetherelationshipbetweentheSERandtheDCoset.Similartothenotationsusedintheaboveequations,westillassumeiastheaccurateintegrationchargeduringeachspikeperiod,andassumeastheidealintegrationwhentherearenoleakageortheDCoset.Wefurtherassumeasthecorrespondingpartwhenthereisosetintroducederror 77

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whereaandbareusedtorepresent1 2CLr0andq SERvs.DCoset 78

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(3{53) whereagaintheapproximationismadeduetoCLVthGmVinTi.Sincethetwonoisesources(DCosetintroducednoiseandleakageintroducednoise)arenotrelatedtoeachother,theexpectationoftheadditionisequaltotheadditionoftheexpectation.Thepowerofthesignalisrewrittenforthereader'sconvenience: 79

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1 (3{55) whereE[(Pih0i(t))2]PiE[(h0i(t))2]isusedfortherstapproximation.Inaddition,theresultfromEq. 3{35 hasbeendirectlyusedforsimplication.ToverifytherelationshipbetweenSERandDCoset,theresultsfromaMatlabsimulationandEq. 3{55 aregiveninFig. 3-32 .TheparametersofthebiphasicIFneuronare:C1=20pF,Vth=0.4V,Gm=30u1,r0=2:6109,R=1011,andtheinputisa1000Hzsingletonewithamplitudeof30mV.TheMatlabsimulationusesastepsizeof1nsandthesignallengthis6ms.BothoftheequationsandMatlabsimulationpredictthatthereisasignicantdropinSERastheosetincreasestoevenafewmVbutthisalsoreectsthefactthattheinputsignalamplitudeisonly20mV. SERvs.comparatorthreshold 80

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3{55 andMatlabsimulationaregiveninFig. 3-33 .ThesimulationparametersaresimilartowhatareusedinFig. 3-32 exceptthattheDCosetissetto5mV.Bothofthetwocurvespredictthatwhenthethresholdincreases,theSERalsoincreases. SERvs.inputsingletonefrequency AnothersimulationisdonetodisplaytherelationshipbetweenSERandinputsingletonefrequencywith5mVDCoset.Fig. 3-34 tellsusthattheSERisindependentofthesingletonefrequency.ThissimulationresultmatcheswiththerealtestingresultsasshowninFig. 3-18 Eq. 3{55 showsthatSERisdependentonmanyfactors,forexample,the\pseudo-resistor"introducedDCosetandsomeothercircuitfactors.SincetherelationshipbetweenSERandthecircuitfactorshasbeendiscussedintheprecioussubsections,itmaybeinsightfulifwejustfocusontherelationshipbetweenSERandtheDCoset.Wecan 81

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3{53 as (3{56) herethenoiseintroducedbytheleakageisignored.ThepowerofthesignalisstillthesameasEq. 3{54 .TheresultingSERcanbederivedasfollows: WhilethisapproximationcannotprovideaccuratevaluesofSER,itclearlyshowshowtheDCosetaectsthereconstructedSER.Fromthisequation,itisclearthatwhentheosetisreducedorthethresholdisincreased,theSERcanbeincreased. 82

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AvariationoftheAERprotocolhasbeensuccessfullyemployedinthetime-to-rst-pulseimagerchipdesignedwithintheCNELlab[ 25 26 27 ].Inthetime-to-rst-pulseimagerchip,anasynchronousdigitalarbiterisusedtoscanotheaddressbusesofallthepixels.Onceapixelgeneratesaspike,arequestsignalissenttothearbiter.Uponacknowledgement,theaddressorthecorrespondingpixelcanbetransmitted.ThedrawbackofthisAERprotocolariseswhentwoormorepulsesreatnearlythesametime.Inthiscase,theAERstructurewilljusttransmitoneofthepulseswhiletheother 83

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Figure4-1. Blockdiagramofthe8-channeladdress-event-representation(AER)recordingsystem Theblockdiagramofan8-channelrecordingsystemisshowninFig. 4-1 .8channelsofthebiphasicspikegeneratorarearrangedasa44neuronarray.Tofacilitatethelayout,bothpositiveandnegativespikeoutputsofeachneuronarearrangedinthesamerowbutindierentcolumn.Oneshouldbearinmindthatthisarrangementisnotoptimalintermsoftransmissionspeed,becauseamaximumof2neuronsineachrowcangeneratethespikesatthesametime.Ontheotherhand,ifallpositivespikesarearrangedintworowswhileallnegativespikesareputinanothertworows,andwhenallneuronsinthesamerowgeneratethespikesatthesametime,thenjustonerowaddressneedstobetransmitted.Thissystemoperatesasfollows: 84

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requestlineispulleddowntosendarowrequest. 2.Rowselectandcolumnrequest:TherowarbiterselectsarowfromthespikingrowsbymakingcorrespondingRow selhighandtheselectedrowaddressisstoredandencodedbytherowaddressencoder.AftertheRow selisreceived,allthespikingneuronsinthatrowcansendoutcolumnrequestsbypullingdownCol request.Inthis8-channelsystem,2columnsatmaximumcansendthisrequestsignalsimulantaneously. 3.Columnselectandreset:Thecolumnlatchrecordsallcolumnrequestsofthecurrentlyringneruonsintheselectedrow.Oncethisisdone,twostepsaretakenatthesametime:1.thecolumnarbiterbeginstoencodethecolumnaddress;2.thelatchedneuronsinthatrowareallresetandtheycanbegintointegrateagain;theresetedneuronswillthereforewidthdrawthecorrespondingrowrequestsignal.Subsequently,theothervalidRow requestcanbeprocessedbytherowarbiter,whiletherowinterfacecitcuitstillblocksanewRow selfrombeingissueduntilalllatchedneuronshavebeenprocessedbythecolumnarbiterandcolumnaddressencoder. Inthefollowingsection,theclockedAERcircuitschemewillbedescribedindetail.Accuratespiketimingiscrucialforsignalreconstruction.TheprimarydrawbackoftheAERprotocolisthepotentialtimingjitterorevenspikeloss,whichaddsdistortiontothereconstructedsignal.Theseimperfectionswillalsobeaddressedinthischapter. 25 26 27 ]. MostofthedetailedcircuitsoftheAERprotocolwereoriginallydesignedbyBoahen[ 28 ].Forthereader'sconvenience,theyarebrieydescribedinthissection. 85

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4-2 isthebasicunitfortherowarbitertreeandcolumnarbitertree.ThisarbitercircuitwasoriginallyusedbyBoahen[ 28 ].Anarbitertreeisbuiltfromtwo-inputarbitercellsusingabinarytreearchitecture. Figure4-2. Schematicofthearbitercell Eacharbitercellhastwolowerportsandoneupperport.Eachlowerporthasonerequestinput(Req in)andselectoutput(Sel out).Theupperporthasonerequestoutput(Req out)andoneselectinput(Sel in).Wheneveroneortwoloweractive-highports,Req in in outhigh.Oncethecurrentarbiterrequesttotheupperlevelisacknowledged,i.e.,Sel in=0,theacknowledgmentsignalwillberelayedtooneofthelowerportsbyzeroingSel out out in in 86

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28 ]. 4-3 isusedtocontrolwhetherarowcanbeselectedbytherowarbiter[ 28 ].Thereisonerowinterfacecircuitforeachrow.OnlywhentheRow sel ensignalfromthelatchcontrolcircuitisenabled,theselectsignalArbiter selfromthearbitercanbetransferredtotherowselectsignalRow sel. Figure4-3. Schematicoftherowinterface 4-4 areusedtoincreasethethroughputoftheasynchronousreadout[ 28 ].Eachcolumnhasonelatchcellandthewholearrayhasjustonelatchcontrolblock.Theimportantcontrolsignalsinclude: request nisthecolumnrequestsignalgoingtothecolumnarbiter. 87

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(b) Figure4-4. Schematicsofthelatchcellandlatchcontrol:(a)latchcell;(b)latchcontrol. sel nisthecolumnacknowledgmentsignalfromthecolumnarbiter. sel engoestotherowinterface(seeFig. 4-3 ),whichenablesthenewrowselectionsignalgoingintotheneuronarray. data readyisvalidafterrequestoncoxhavealreadyenteredthelatchcell.Thissignal,togetherwithrow sel,resettheneuronwhichhaveredintheselectedrow. address triggertriggerstherowaddressencodertoupdatetherowaddress. Onethingneedtokeepinmindisthatsignalb,lpandgaresharedbyalllatchcells. 88

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request=0.ThenwehaveCol sel=0,g=1,lp=0,b=1,Row sel en=1andLatch data ready=1. Oncearowsendsarequesttotherowarbiter,withRow sel en=1,theselectsignalfromtherowarbitercanreachtheneuronunitandRow sel=1(seeFig. 4-3 ).ThentheneuronunitcansendthecolumnrequestsignalbymakingCox=0andpushinguplp.Sinceb=1atthistime,Cox=0cangoaheadtosendarequestsignaltothecolumnarbiterbymakingCol request=1,whichfurtherpullsdowng.Thechangeofgandlpleadtob=0whichstopsalltheincomingcolumnrequests.Simultaneously,Row sel en=0disablestherowinterfacefunctionsandguaranteesnonewrowselectisgranted.Atthesametime,theactiveLatch data readyandRow selresetallspikingneuronsintheselectedrow,whichfurtherdisablesthecolumnrequestsignalCox.Inaddition,Row address triggertriggerstherowaddressupdate. Inidealsituation,allthespikesoutputwillbetransmitted,withorwithoutadelay.However,spikelosscanhappenintherealchiptest.Beforeweexplainhowspikedrophappens,let'stakealookathowthespikegettransferred.Whenthereisaspikegetgenerated,itrstsendstherowrequestsignaltotherowarbiter.Whentherowrequestsignalisacknowledged,thecolumnindexesofalltheneuronsthatarespikinginthesamerowwillbesavedinabuer.Afterthat,arowresetsignalwillbecombinedwiththespikeoutput(anANDgateisused)toresetallthespikingneuronsfromthesamerow.Whichmeansthatifthisneuronwithinthisrowishavingaspikeoutput,therowresetsignalcantakeeecttothisneuronandresetit;however,ifthisneuronisnotgeneratingaspikeoutput,therowresetsignaldoesnothaveanyeectonthisneuron.Afterthisresetprocess,theseneuronswithspikeoutputscanbeginanothernewintegrationperiod.Iftherearetwoneurons(AandB)fromthesamerowgeneratespikesoneafteranother,andtherstneuronAsendstherowrequestsignalwhilethesecondneuronBisstillintegrating.Whentherowrequestsignalisacknowledged,thebuerbeginstorecord 89

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Aftereachcolumnisserviced,thecorrespondingCol selwillbesettoonewhich,withtheaidofb=0,canremovethecolumnrequestbymakingCol request=0.Withtheremovalofthecolumnrequestsignal,Col selwillalsoberesettozero.Whenallthecolumnrequestsignalsareprocessed,allCol requestandCol selaresettozero,whichmakesg=1.Whenallspikingneuronsarereset,Cox=1,whichmakeslp=1.Bothlp=1andg=1resetallthecontrolsignalsbacktotheirinitialconditions,andallthelatchcellsarereadyforupcomingrowandcolumnrequests. SchematicofthethroughputcontrolblockforclockedAER ThethroughputcontrolblockshowninFig. 4-5 wasrstintroducedbyGuo[ 27 ]tosimplifythechiptesting.Withtheaidoftwononoverlappingclocks,thisreadoutsystem 90

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26 ].ThesignalCol arbiter selcomesfromthecolumnarbiter,thesignalCol selgoestothelatchcell,andthesignalCol encoder intriggersthecolumnaddressencoder.Tofacilitatethechiptesting,thiscircuitisalsousedintheeight-channelbiphasicIFchip. Chiplayoutofthe8-channelbiphasicIFneuronwithAERreadout ThelayoutofthischipwithpadsisshowninFig. 4-6 .ThereareeightchannelsofbiphasicIFneuronsandeachchannelincludesthreecomponents:thegmamplier,thecomparatorsandthedigitalcontrolblock.ThesameblocksfromalleightchannelssharethesamepowersupplyandtheAERcircuitusesthedigitalcontrolblockpowersupply.Therearetotalthreepowersupplies.Bypasscapacitorisputasmuchaspossibleto 91

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92

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Figure4-7. Clockfrequencyvs.SER(onechannel) ThemeasurementresultofonechanneltestisgiveninFig. 4-7 .Inthistesting,theinputofthechosenchannelissettoa1000Hzsingletonewithamplitudeof40mVpeak-to-peak,andthethresholdofthecomparatorwassetto0.4V.Thereadoutclockwassweptfrom100KHzto4MHz.Afterthelogicanalyzercapturedthefour-bitaddresscode,aMatlabprogramwasruntorestorethecorrespondingbiphasicpulse.Theclose-formalgorithmwasusedtoreconstructthesingletonesignal,andthettingalgorithmusedinthepreviouschapterwasusedtocalculatetheSER.EachSERiscalculatedbasedontwoperiodsofthereconstructedsignal.Fromthisgure,itisclearthatthereconstructedsignalSERmostlyrangesfrom35dBto45dBwiththemaximumSERofaround43dBcorrespondingtoareadoutclockof1MHzand3MHz.Thisguredoesnotgiveaclear 93

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3-18 ,thereconstructedSERwiththesameinputsignaland0.4Vthresholdis45dB.Fig. 3-22 indicatesthatwhenthethresholdincreases,theSERisreduced.Basedonthisdata,theAERcircuitwithproperreadoutclockintroducesverylittleerror,andthiserrorcontributestothisSERgapbetween45dBand43dB.Whentheclockfrequencyistooslow,theSERmightberestrictedbythelowreadoutthroughputrateandpoortimedomainresolution.Whenthefrequencyistoohigh,itisverylikelythatthefastclocktransitionwillintroducesomenoiseinsidethechippackage,andthisnoisecanreducethereconstructedSER.Therefore,thereisatradeowhenwedecidewhichreadoutclockfrequencytochoose. Figure4-8. Clockfrequencyvs.outputspikerate(onechannel) 94

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4-8 showsthereadoutspikefrequencyandcorrespondingoutputspikerate.Whentheclockfrequencyislow,itisclearthatthespikerateisincreasingwithfasterreadoutclock.Thisrelationshipisreasonable,becausehigherreadoutfrequencymeanslargerthroughput.Inthereadoutprocess,whenaspikeisgenerated,itsendstherequestformodulation.Onlywhenthisspikeisreadout,thisneuroncanintegrateforthenextspike.Onlyonespikecanbesentoutduringeachclockperiod.Whentheclockfrequencyishigh,thegeneratedspikecanbequicklysentout,thenewintegrationperiodcanbeinitiatedsooner,andthespikerateishigher.Ontheotherhand,iftheclockfrequencyislow,theneuronhastowaitforalongertimebeforeitcanstartanotherintegration,andthespikerateislower.However,whenthereadoutfrequencyishigherthan1MHz,thespikerateisreducedeventhoughthereadoutclockfrequencyisincreasing.Thepossibleexplanationisthatwhentheclockfrequencyistoohigh,itinjectsmorenoiseintothechipsubstrate.Thisnoiseaectsthissystem,forexample,thisnoisecanmakethe\pseudo-resistor"introducedDCosetmoreunpredictable. Figure4-9. Measuredreconstructiontimedomainresultexample:(a)Reconstructedsin-gletonesignal(red)andthe4-parameterttedsingletonesignal(blue);(b)Error. Fig. 4-9 showsanexampleoftheoinereconstructedsignalbasedontheAERchipmeasurement.Theinputsignalisa1KHzsinewavewith40mVpeak-to-peakamplitude. 95

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4-9 (a)isthereconstructedsinewaveandthebluecurveisthe4-parameterttingsinewave.Fig. 4-9 (b)istheerrorbetweenthereconstructedsignalandthettingsignal.Thisreconstructedsignalhas35dBSERandthecorrespondingreadoutcontrolclockfrequencyis1.1MHz.Onestrangeobservationfromthisgureisthatthelargeerrorbetweenthereconstructedsignalandthettingsignalalwayshappensatthehighsignalamplituderegion,thissuggeststhatthedelayedspikereadoutprocessisresponsibleforthiserror. Thesetupweusedwastheworstcase.Whentheinputhasthemaximumamplitude,bothchannelsaregeneratingthedensestspiketrain,andbothwillcompetetousetheAERreadoutcircuittosendoutthespikes.Inthiscase,someoftheoutputspikeshavetobedelayedorevenlost.Therefore,thereconstructedsignalsfromthissetupwillbelower.Ontheotherhand,whentheinputhasaninputamplitudeofzero,therewillbenospikefromeitherchannel,andtheAERreadoutcircuitwillbewasted.Infact,inrealapplication,thetwochannelswillhavetheirindividualinput,andtherewillbealwayssomedierencebetweenthetwoinputs. 96

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Clockfrequencyvs.SER(twochannels) ThemeasurementresultoftwochannelstestingisgiveninFig. 4-10 .Inthistesting,theoutputfromtheAgilent33220Asignalgeneratorissettoa1000Hzsingletonewithamplitudeof40mVpeak-to-peak,andthethresholdofthecomparatorwassetto0.4V.Thereadoutclockwassweptfrom100KHzto4MHz.Afterthelogicanalyzercapturedthefour-bitaddresscode,aMatlabprogramwasruntorestorethecorrespondingbiphasicpulse.Theclose-formalgorithmwasusedtoreconstructthesingletonesignal,andthettingalgorithmwasusedtocalculatetheSER.EachSERiscalculatedbasedontwoperiodsofreconstructedsignal,andtheplottedSERistheaverageSERbetweenthesetwochannelsoverthesametimeperiod.Fromthisgure,itisclearthatthereconstructedsignalaverageSERmostlyrangesfrom30dBto35dBwiththemaximumSERofaround37dBcorrespondingtoreadoutclockof400KHz. Fig. 4-11 showsthereadoutspikefrequencyandcorrespondingaverageoutputspikerateoverthetwochannels.Whentheclockfrequencyislow,itisclearthatthespikerateisincreasingwithfasterreadoutclock.Thistrendissimilartothatintheonechannel 97

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Clockfrequencyvs.outputspikerate(twochannels) case(seeFig. 4-8 ).However,whenthereadoutfrequencyishigherthan1MHz,thespikerateisreducedeventhoughthereadoutclockfrequencyisincreasing.Surprisingly,thistrendisalsosimilartothathappenedintheone-channelcase(seeFig. 4-8 ).ComparedtoFig. 4-8 ,thespikeratesinthetwo-channelcasearenormallylessthanthoseintheone-channelcase.Forexample,themaximumspikerateintheone-channelcaseis80Kpulsepersecond,whilethemaximuminthetwo-channelcaseisaround70Kpulse/s. Fig. 4-12 showsthemeasuredtimedomainexamplefromtheabovetwo-channelsetup.ThereconstructedsignalandthettedsignalfromtherstchannelisshowninFig. 4-12 (a)andthecorrespondingSERis43dB.Fig. 4-12 (b)givesthereconstructedsignalandthettedsignalfromthesecondchannelandtheSERis30dB.TheerrorsbetweenthereconstructedsignalandthettedsignalareshowninFig. 4-12 (c)withtheredonecorrespondingtochanneloneandtheblueonecorrespondingtochanneltwo.Thismeasurementresultscorrespondtothe400KHzreadoutclockfrequency.Comparedtothe 98

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Measuredreconstructiontimedomainresultexample:(a)Reconstructedsingletonesignal(red)andthe4-parameterttedsingletonesignal(blue)fromtherstchannel;(b)Reconstructedsingletonesignal(red)andthe4-parameterttedsingletonesignal(blue)fromthesecondchannel;(c)Errorfromtherstchannel(red)andfromthesecondchannel(blue). resultsshowninFig. 4-7 ,wecanndthattherstchannel'sSER(43dB)isalmostequaltothemaximumSERachievedinonechannelcase.However,theSERfromthesecondchannelismuchworsethanthatfromtherstchannel.Thisresultdoesnotmeanthatthereconstructedsignalfromtherstchannelisalwaysbetterthanthatfromthesecondchannel.Infact,sometimethesignalfromthesecondchannelhasahigherSERthanthatofchannelone. 99

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Figure4-13. Clockfrequencyvs.SER(threechannels) ThemeasurementresultofthreechannelstestingisgiveninFig. 4-13 .TheshownSERistheaveragedSERoverthethreechannelsduringthesame2msperiod.Fromthisgure,itisclearthatthereconstructedsignalaverageSERmostlyrangesfrom26dBto32dBwiththemaximumSERofaround32dBcorrespondingtoreadoutclockof200KHzand900KHz.TheSERwiththeclockfrequencylowerthan1MHzishigherthanthatcorrespondingtothefrequencyhigherthan1MHz.Surprisingly,thisobservationalsoappliestothetwo-channelcase(seeFig. 4-10 ). Fig. 4-14 showstheaveragespikeratecorrespondingtodierentreadoutclockfrequencies.Similartothoseinthetwo-channelandone-channelcases,thespikeraterstincreaseswiththefasterclockandthendropswhentheclockfrequencyfurtherincreases. 100

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Clockfrequencyvs.outputspikerate(threechannels) ThemeasurementresultoffourchannelstestingisgiveninFig. 4-15 .TheshownSERistheaveragedSERoverthefourchannelsduringthesame2msperiod.Fromthisgure,itisclearthatthereconstructedsignalaverageSERmostlyrangesfrom20dBto32dBwiththemaximumSERofaround32dBcorrespondingtoreadoutclockof2MHz.Inthisgure,evenwhentheclockfrequencyishigherthan1MHz,theSERdoesnotdrop.Thisisdierentfromthetwo-channelandthree-channelcases.Thereasonisthatwhenwe 101

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Clockfrequencyvs.SER(fourchannels) havetoomanyactivechannels,theimprovementfromthefasterclockfrequencyorwidercommunicationbandwidthismoredominantthanthenoiseintroducedbytheclock. Fig. 4-16 showstheaveragespikeratecorrespondingtodierentreadoutclockfrequencies.Dierentfromwhatweobserveintheone-,two-andthree-channelcases,wendthatthespikerateisalwaysincreasingwiththeincreasingclockfrequency.ThistrendisconsistentwiththeSERtrendinfourchannelscase:bothofSERandspikeratedoesnotdecreasewhenclockfrequencyisfaster. 102

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Clockfrequencyvs.outputspikerate(fourchannels) channelcanbeassignedupto25KHzbandwidth,whichisgreatlybelowwhatweobservedintheprevioustesting.ThethresholdsofthebiphasicIFcomparatorsweresetto0.4Vandthemeasurementwerebasedon2mstimeperiod. ThemeasurementresultofeightchannelstestingisgiveninFig. 4-17 .TheaverageSERovereightchannelsmostlyrangesfrom16dBto28dBwiththemaximumSERofaround28dBcorrespondingtoreadoutclockof3MHz.Inthisgure,evenwhentheclockfrequencyishigherthan1MHz,theSERdoesnotdrop,thisissimilartowhatweobservedinthecaseoffourchannelsanditisdierentfromthoseintwochannelsandthreechannels.Thereasonisthesameaswhatwediscussedintheprevioussection. Fig. 4-18 showstheexampleofreconstructedsignal(red)andthettedsignal(blue)fromalltheeightchannels.Thecorrespondingreadoutclockfrequencyis3MHzandtheaverageSERisaround28dB. 103

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Clockfrequencyvs.SER(eightchannels) SometrendscanbefoundfromthevesetupsandthetestingresultsinthisAERchipmeasurement.First,whenthereadoutclockisfaster,thethroughputislargerandthepulsescanbemoreaccuratelyreadout.ThemeasurementresultsshowthatthespikerateandSERisincreasingwithfasterreadoutfrequencyinlowfrequencyrangeandthisisconsistentwiththeexpectation.Thedrawbackofhigherreadoutclockfrequencyismoreintroducednoise,therefore,theSERisnotnecessarilyincreasedwithfasterreadoutclockinhigherfrequencyrange.Infact,whentheactivechannelnumberislarger,themorebenetcanbeprovidedbythehigherreadoutclockfrequency.Whenthechannelnumberissmall,thehigherreadoutfrequencydoesnotimprovethethroughputverymuch,sothenoiseismoredominant.Howeverwhenthenumberofchannelsislarge,thehigherreadoutclockimprovesthereadspikerategreatly,thusthedrawbackofnoisereachesabalance.Theobservedresultsverifythispoint.Whenthechannelnumberincreasesfromonetoeight,theSERkeepsincreasingwithhigherclockfrequency.Therearetwomethodstoavoidthisreadoutclockdrawback.Oneoptionistousesomedelicate 104

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Measuredreconstructiontimedomainresultexample(redistherecon-structedsingletonesignalandtheblueisthe4-parameterttedsingletonesignal) layouttoreducetheclock-introducednoise.Anotheroptionistouseaclock-freeAERcircuittoreadoutthesepulses. Second,correspondingtothesamereadoutclockfrequency,themorechannelsareactive,thelessaverageSERcanbeachieved,asshowninTable 4-1 (therstrowinthistablecomesfromthesingle-channelchipmeasurement).Thisisobviousbecausewhenthechannelnumberislarge,thereismorepossibilityforthespikestoencountercollisions,getdelayedorevenbedroppedduringthereadout.Themeasurementresultsalsoverifythispoint.Maybesomebetterreadoutcircuitcanavoidthisproblem. 105

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Eight-channelchipmeasurementsummary MaximumaverageSER(dB) Readoutclock(Hz) 45 N/A 1 43 1M 2 37 400K 3 31.5 900K 4 31.5 2M 8 27.5 3M 15 ]andChen[ 22 ].Intheircases,thetimingjitterrefertotheerrorintroducedbytherecordingdevice.ThiserrorsourceisstillthereintheAERchipwejustmeasured.Inadditiontothis,however,thereisamoreseveretimingerrorduetothereadoutclock.Inthecaseofonechannel,whenaspikeisgeneratedbytheneuron,ithastobeprocessedbytheAERreadoutpart.Tomakethingsworse,thisspikecanonlybeprocessedonceperclockperiod.Whenaspikeisrecorded,theonlythingweknowisthatthisspikewasgeneratedduringthepreviousreadoutclockperiod.Theexactspiketimeisunknown.Sincethistiminguncertaintyisontheorderof1s,theothertimingjitter(mostlyontheorderof1ns)canbeignored.EventhoughthistimingerrorisdierentfromthetimingjitterdiscussedbyWeiandChen,theyworkinthesamewaytoaectthereconstructedsignal.Therefore,theirconclusionwillbedirectlycitedhere. Weiconcludedthatwiththesamplingfrequencyincreasing,theSERoftherecon-structedsignalwillbeimproved[ 15 ].Thisconclusionisverystraightforward.Tocheckthevalidityofthisconclusioninourcase,someMatlabsimulationsarerun.Inthissimu-lation,aneight-channelbiphasicIFneuronAERchipwasconsidered.Theparametersofeachneuronarethesameasthoseusedinthepreviouschapter(C1=CL=20pF,Vth= 106

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Clockfrequencyvs.SER(onechannelMatlabsimulation) 4-19 .Fromthissimulation,itisclearthattheSERisincreasingfrom35dBto80dBwhenthereadoutclockfrequencyincreasesfrom100KHzto200MHz.Inthelowclockfrequencyrange,TheoverallsimulationSERisaround7dBhigherthanthatofmeasurementresult.Duetothenoise,thefasterreadoutclockwasnotusedinthemeasurement. 107

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Clockfrequencyvs.SER(eightchannelMatlabsimulation) 26 ].SomeMatlabsimulationsareruntocheckhowthesefactorsaectthereconstructionSER.Therstsimulationistorunalltheeightchannelneurons,andthereadoutclockwassweptfrom100KHzto200MHz.Alltheneuronsweresettothesameparametersaslistedintheprevioussection.InthisMatlabsimulation,justspikedelayisconsideredintheAERreadoutprocess.Whenthereareseveralchannelsaregeneratingspikes,allthewaitingspikeshavetobetransferredinsomepriorityassignedtothechannels.Thereadoutbeginsattherisingedgeofeachclockperiodandendsattherisingedgeofthefollowingclockperiod.Thechannelcanbeginanotherintegrationprocessonlyaftertherowitbelongstohasbeenchosen.ThereconstructedaverageSERovertheeightchannelsislistedinFig. 4-20 108

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Figure4-21. Channelnumbervs.SER(Matlabsimulation) AnotherMatlabsimulationwasruntochecktherelationshipbetweenSERandactivechannelnumber.Inthissimulation,thereadoutclockfrequencyissetto4MHz.ThesimulationresultispresentedinFig. 4-21 .Theresultisconsistenttowhatweobservedinthechipmeasurement:whentherearemoreactivechannels,theaveragedSERisdropping. 109

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ThesenoisecanaecttheoperationofthebiphasicIFneuronthroughthesubstrateorthroughtheripplesonthepowerline.Theycanalsodirectlydistorttheinputsignal.Consideringtheinputsignalhassmallamplitude,thisdistortioncanbeabigissue.Aguardringcanreducethesubstratenoise.Itisalsowisetoseparatetheanalogcircuitsfromthedigitaloutputasfaraspossible.Bothmethodshavebeenusedinthetestchip.Anothersolutionistodesignmorerobustcircuitswithhigherpowerrejectionratio.Withahigherpowerrejectionratio,theripplesonthepowerlinewillhavelesseectonthecircuitoperation. Anothermethodtoincreasethecircuitrobustnessistodesignadierential-modeinputcircuit.Forexample,ifthecircuithasadierential-modeinputpair,thedistortiontotheinputsignalcanbegreatlyreduced.Inthiscase,thisdistortionshowsitselfasacommonmodenoise,whichcanberejectedbythedierentialinputpair. 110

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Schematicofsinglestagegmamplier 111

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5-1 showstheschematicofthenewsinglestagegmamplier,whereM1andM2,M3andM4arefourdiode-connectedPMOStransistors.Theyactas\pseudo-resistors"withresistancegreaterthan1011.M1,M2andC1constructahighpasslter;andM3,M4andC2alsoconstructanotherhighpasslter.Sincethese\pseudo-resistors"havehugeresistance,thecutofrequencyofthesehighpassltersareverylow(lessthan1Hz).Intuitively,thisgmampliercanbeseparatedintotwocircuits.OneofthemisaDCloop,whichincludesthefour\pseudo-resistors"andtheloadcapacitorCL.TheDCloopisactuallyaDCvoltagefollower,andtheoutputDCvoltageoverCLisfollowingthevoltageVref.ThisDCloopisusedtoxtheDCoperationpointofthiscircuit.Ontheotherhand,whentheACloopisconsidered,thefour\pseudo-resistors"canbeignored,andthisOTAworksinopen-loopwithhugegain.Inoneword,thisgmamplierrejectstheDCcomponentoftheinputsignalandampliestheACcomponent. Intheparameterconguration,thetwoinputbrancheswillbesettobeidenticalsothatthisgmamplierwillamplifyonlythedierential-modeinputsignal.Thisiswhatwedesirefortheneuralsignalapplication.DuetotheDCdrift,areferencesignalisnormallyusedtocanceltheDCdriftintheneuralsignal[ 6 ]. Sincetheneuralsignalnormallyhastheamplitudeof50{500VandtheOTAwillhasaDCosetofaround1mV,thereisaconcernaboutwhethertheDCosetwillsuppresstheinterestingpartofaneuralsignal.Infact,theDCosetwillappearontheloadcapacitorwithoutbeingampliedwhiletheneuralsignalwillbeboostedupbytheopen-loopgain(normally80dB).Theresultistheneuralsignalwiththeamplitudeof0.5{5Voverlapsonthe5mVDCoset. Tobetterunderstandhowthisgmamplierworks,thetransferfunctionisderived.SimilartowhatwedidinChapter3,theequivalentcircuitofthegmamplierisgiveninFig. 5-2 wherer0representstheoutputresistanceoftheOTAandGmisthetranscon-ductanceoftheOTA.Thecircuitinthisgurelookscomplicated,soweusesuperpositionmethodtosolvethisproblem.First,weassumetheinputterminalVinisgrounded.In 112

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Equivalentcircuitofthesinglestagegmamplier thiscase,thecircuitissimilartoFig. 3-3 ,andwecandirectlywritedowntherelationshipbetweenVin+andVoutas (1+j!C1R)(1+j!CLr0)+r0(Gm+j!C1)Vin+(5{1) Second,weassumethatinputterminalVin+isgrounded,whichreducesFig. 5-2 toFig. 5-3 Figure5-3. Equivalentcircuitofthesinglestagegmamplierwithnegativeinput Wenoticethat Therefore, 113

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and CombiningEq. 5{3 toEq. 5{6 ,wecanachievetherelationshipbetweenVoutandVin: Inpractice,C1issetequaltoC2,whichcansimplifytheaboveequationto (1+!C1R)(1+j!CLr0)+r0(Gm+j!C1)Vin(5{8) ComparingEq. 5{8 toEq. 5{1 ,wecanndtheyareverysimilar.Thismakessense,becausetheyaresymmetricalinthecircuitstructure.Combinethesetwoequations,thenaloutputcanbewrittenas (1+!C1R)(1+j!CLr0)+r0(Gm+j!C1)(Vin+Vin)+j!r0C1 ItisclearfromEq. 5{9 thattheoutputisamplieddierentialinputoverlappingwithasmallsignalproportionaltoVin+.Apparently,therstterm(amplieddierentialsignal)iswhatwedesiredinourapplicationwhilethesecondisthenoise.Fortunately,thersttermhasamuchhighergainthanthatofthesecondterm.Forexample,ifGm=301061andR=1011areused(therearethenormalvaluesusedinthecircuit),thegaindierencewillbearound130dB.Thereforewhenthecommon-modesignalandthedierential-modesignalhavecomparableamplitude,thesecondtermcanbeignoredintheanalysiswithoutintroducingmuchinaccuracy.Somedetailedanalysisaboutthiswillbefoundinthefollowingsections.IfweseparateEq. 5{9 intotwoparts 114

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3-4 gaveagoodexamplewhattheACresponselookslike. Ifweignoretheseconditem,anduseVintorepresentVin+Vin,Eq. 5{9 canbesimpliedto (1+!C1R)(1+j!CLr0)+r0(Gm+j!C1)Vin ThissimpliedequationisverysimilartoEq. 3{22 .IfwereviewthederivationinEq. 3{23 again,wecanndthefollowinganalysisresultsinChapter3canbedirectlyusedherebecausethetransferfunctioninEq. 3{22 wasnallysimpliedtoEq. 5{10 tofacilitatethederivation.TheSERequationinEq. 3{35 canalsobedirectlyusedinthisapplication. Eventhoughtherearemanysimilaritiesbetweenthesingle-stagegmamplierandthesecond-stagegmamplierinChapter3,extrasimulationsarestillnecessarytondthebestparametersset.Inthecaseofthesecond-stagegmamplier,theinputsignalgoesfromtheoutputofthepreamplierwherethedierentialneuralsignalisconvertedintosingle-endedsignalwithbeingampliedby40dB.Ifweconsiderthattheneuralsignalhasanamplitudeof100V,forexample,theinputsignalforthesecond-stagegmamplierhastheamplitudeofaround10mV.Inthisoccasion,moderategainforsecond-stagegmamplierisgoodenoughtogenerateenoughpulsesforreconstruction.Intermsofthesingle-stagegmamplier,however,highgainisneededtoboostthesignalof100Vsothatsomepulsescanbegenerated.Thereareseveralwaystoincreasethegain,forexample,wecandecreasetheloadcapacitor,wecanalsoincreasethetransconductanceoftheOTA.Thesimulationmaygivesomecluesaboutwhichwaycanbedonetoachievethat. Onemayarguethatthegaindoesnotneedtobehighifthethresholdisreducedproperly.InChapter3,itismentionedthattheOTAinputDCosetisaround5mV,andthisosetputstherstlimitforthecomparatorthreshold.The\pseudo-resistor" 115

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IfwetakeafurtherlookatthenoiseterminEq. 5{9 ,wemayndthatitisreallynotabigproblem.Recallinthecaseofsecond-stagegmamplier,theinputsignalistheoutputofthepreamplier[ 5 ].Thepreamplierhassimilarstructuretothesingle-stagegmampliersothatthenoisetermwasalsoincludedintheoutputofthepreamplier.Basedonthis,itcanbeconcludedthatthenoise(ortheimperfectionindierentialamplier)isampliedandintegratedinbothgmampliers. 5.3.1CadenceSimulation Simulatedtimedomainexample:(a)Twoinputsignals;(b)Outputspikes. Connectingthesingle-stagegmampliertothedigitalblockdesignedbyChen[ 5 ]nishesthedesignofsingle-stagebiphasicIFneuronusingAMI0.6mtechnique.AsimulationwasruninCadencetoverifythecircuitanalysis.Inthiscircuitsimulation,the 116

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5-4 showstheinputsandthespikeoutputfromthisCadencesimulation. Figure5-5. Simulatedtimedomainexample:(a)Reconstructedsignal(red)andttedsignal(blue);(b)Errorbetweenthereconstructedsignalandthettedsignal. ThegeneratedspiketrainwasreadoutandreconstructedbyaMatlabprogram.Toevaluatethisreconstructedsignal,anotherarticialsignalofsuperpositionoffoursingletones(100Hz,500Hz,1000Hzand5000Hz)wasgenerated.Hereweassumethedierentialamplierremovedthecommonmodesignalof60Hzsinewaveandjustthedierential 117

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5-5 (a).TheerrorbetweenthereconstructedsignalandthettedsignalisalsogiveninFig. 5-5 (b).TheresultsshowninFig. 5-5 (a)showsthatthecommonmodesignalisreallyremovedandtheampliedsignal(orthereconstructedsignal)iscomposedmostlybythedierentialmodesignaleventhoughthecommon-modesignalismuchstrongerthanthedierential-modesignal.Thisisexactlywhatweexpected. TheMatlabsimulationusestheconvolutionbetweentheinputsandtheimpulseresponsesfromthetransferfunction.Tomakethesimulationmorepractical,thenoiseterminEq. 5{9 isalsoincludedinthesimulation.Withoutspecialmention,allthecircuitparametersusedinthefollowingMatlabsimulationare:C1=C2=20pF,Vth=0.1V,Gm=30u1,r0=2:6109,R=1011,CL=1pF,andtheinputisa1000Hzsingletonewith400Vpeak-to-peakamplitudedierential-modesignalsuperposingona600mVpeak-to-peak60Hzcommon-modesinewave. TherstsimulationistocheckhowtheDCshiftcanaectthereconstructionSER.Inthissimulation,alltheotherparameterswerexedwhiletheamplitudeofthe60Hzsignalwassweptfrom0.01Vto300V.ThereconstructedSERisshowninFig. 5-6 .Fromthisgure,itisclearthatwhenthecommon-modesignalhasanamplitudelessthanorequalto10V,thereconstructedsignalwillnotbeaected.Actually,theDCshiftin 118

PAGE 119

SERvs.lowfrequencysignalamplitude neuralsignalsisalwayslessthan10V,therefore,thisshiftwillnotaecttherealneuralsignals. Thesecondsimulationisruntondthebestloadcapacitorforthisgmamplier.Inthissimulation,alltheotherparameterswerekeptxedwhiletheloadcapacitancewassweptfrom0.1pFto10pF.ThecorrespondingSERisgiveninFig. 5-7 .ItisclearthattheSERdropswiththeincreasingloadcapacitance.Thisisreasonablebecausewhentheloadcapacitanceisdecreased,theoutputspikerateisrapidlyincreasing.OnemaywonderwhythemaximumSERinthisplotisaround60dBwhilethesimulationresultinChapter3canbeashighas80dB.Toexplainthispoint,wemayneedtotakeanotherlookatEq. 3{35 ,whichisrepeatedhereforthereader: Intheaboveequation,increasinginputsignalamplitudeorreducingtheloadcapacitancecanbothincreasetheSER.Comparedtoreducingtheloadcapacitor,increasinginputsignalamplitudemaybemoreecientduetotheirdierentpowerfunctioncoecients. 119

PAGE 120

SERvs.loadcapacitance Toverifythisrelationship,anotherMatlabsimulationwasrunwheretheinputsignalamplitudewassweptfrom100Vto2mV.ThesimulationresultsareshowninFig. 5-8 wheretheSERincreasesfrom42dB(inputsignalamplitudeis0.1mV)to80dB(inputamplitudeisaround2mV). EventhoughEq. 5{11 indicatessomewaystoincreasetheSER,therearesomepracticallimits.Forexample,theneuralsignalamplituderangesfrom50Vto500V,whichisoutofourcontrol.Theloadcapacitorcannotbereducedinnitelyeither.TheparasiticcapacitorwillbeassociatedtotheOTAoutputnomatterwhetherwereallyputapolycapacitorthere.Ontheotherhand,iftheloadcapacitoristoosmall,the-3dBfrequencywillbemovedawayfromtheoriginalpoint,andthissystemmaybecomeunstable.IfwecheckFig. 5-1 again,theDCloopisavoltagefollower.Ifthissystemisnotstable,somenoiseintheDCinputwillmakethesystemoscillateanddestroythissystem.Actually,Cadencesimulationshowsthatthesystemisstillstablewhentheloadcapacitanceisgreaterthan1pF. 120

PAGE 121

SERvs.inputsignalamplitude SimilartowhatwedidinChapter3,thebypassresistanceRandtheinputcapaci-tanceCwerealsoswepttochecktherelationshipbetweentheseparametersandthere-constructionSER.ThesimulationresultsareshowninFig. 5-9 andFig. 5-10 respectively.ItisclearfromFig. 5-9 thattheSERincreaseswiththeincreasinginputcapacitance.However,nitelayoutareapreventsusfromusingahugecapacitor.A20pF-capacitorwasusedinthechipdesign.Fig. 5-10 showsthattheSERincreaseswiththeincreasingbypassresistance.Intherst-stagegmamplier,sincethevoltageacrossthe\pseudo-resistor"isaround0.1V(comparedto0.4Vinthesecond-stagegmamplier),thebypassresistanceshouldbealittlebithigherthanthatinthesecond-stagecase. ComparingallthesimulationresultsfromFig. 5-7 toFig. 5-10 ,itcanbefoundthatforawiderangeofinputcapacitance,outputcapacitanceandbypassresistance,theSERofreconstructedsignalisalwaysbelow60dB.However,whentheinputsignalamplitudeisincreasedabove500V,theSERrisesabove60dB.Whentheamplitudeincreasesto2mV,theSERisaround80dB.Therefore,itcanbeconcludedthattheinputsignalamplitudeisanimportantreasontothelowerSERachievedintherst-stagegmamplier. 121

PAGE 122

SERvs.inputcapacitance Sincetheinputsignalinthisrst-stagegmblockisveryweak,GmmayhavetobesettoalargevaluetogenerateenoughspikesandahigherreconstructionSER.Therearetwomethodstoachievethis.Therstoneistouselargertransistorsfortheinputpair,however,thismaydegradethestability.Theotheroptionistoincreasethebiascurrent.Bydoingthis,thestaticpowerconsumptionwillbeincreased.WithlargerGm,therewillbemorespikeoutputs,dynamicpowerconsumptionwillbeincreasedandthecommunicationbandwidthwillalsobeincreased.Therefore,thereisatradeobetweenpowerconsumption,communicationbandwidthandSER. 122

PAGE 123

SERvs.bypassresistance 123

PAGE 124

Twofully-integratedCMOSsecond-stageamplierswithmidbandgainofaround40dBhavebeendemonstrated.BothcircuitscanrejecttheDCosetintroducedbythepreamplierandhavearail-to-railoutputrange.Thecapacitor-feedbackversionhasapassbandfrom0.3Hzto19KHz.Theresistor-feedbackversionrangesfrom94Hzto19KHz.ThesepropertiesmakeitpracticaltocascadethemtothepreamplierdesignedbyChen[ 5 ]toformatotal80dBneuralamplier.Bothampliersweredesignedwitha0.6mCMOSprocess.Thequiescentpowerdissipationofthesecond-stageampliersislessthan120Wunder5Vpowersupply. ThereconstructionalgorithmforunidirectionalIFspikeencodinghasbeendescribed[ 21 ]andseveralcircuitstogeneratethespikeshavealsobeenimplemented[ 5 15 ].TheunidirectionalIFcircuitsshifttheACsignaltoguaranteesingle-directionthusresultinginpowerwaste.Toreducepowerconsumption,abiphasicspikeencodingalgorithmwasproposedbyChen[ 5 11 ].However,generatingthebidirectionalinputcurrenthasbeenaproblem.Inthisresearch,anovelsecond-stagegmamplierwithfully-integrated0.6mCMOSprocesshasbeendesignedandfabricated.Cadencesimulationandcircuitanalysishaveproventhatthiscircuitissuitableforthebiphasicspikerepresentation.SimulationresultsgivethereconstructedsignalwithSERupto85dBwhenconsideringthedigitalcontrolcircuitideal.ThechipmeasurementfoundthattheSERforsingletoneinputcanachieve55dBSER.Theneuralsimulatorwasalsousedinthechiptesting.BoththereconstructedneuralsignalandtheTDTrecordedneuralsignalwereprocessedbyacommercialspikesorterandthesortingresultsshowedthatbothsignalshavesimilarresults. Toreducetheoutputconnectionwires,theAERprotocolhasbeenusedtotransmitthespikeoutputfrom8channelsofthebiphasicspikegenerators.Thecircuitsimplement-ingthismultichannelrecordingsystemhavebeendesignedandfabricated.Thechiphas 124

PAGE 125

TofurthersimplifythebiphasicIFsystem,asingle-stagegmamplierwasdesignedtoreplacethesecond-stagegmamplier.Thenewgmampliercandirectlyamplifythedierential-modeneuralsignal.TheCadencesimulationsandMatlabsimulationsshowedthatthisnewsystemisworkingwhileachievingworsesignaldelitycomparedtotherst-stagegmamplier. ThemajornoveltyofthisworkisthattwocompactACcurrentgeneratorsaredesigned.Therstgmamplierworksforsingle-endedhigherinputsignalamplitudewhilethesecond-stagegmampliercanworkfordierential-modesignalwithmuchlowerinputsignalamplitude.Thesecurrentgeneratorscanbeusedtodesignamultichannelsystemwithsimpleanalogtodigitalencodingimplementedinhardwareandthecomplexdigitalreconstructionprocessimplementedinsoftware.Suchatradeoiswellsuitedforlow-powerimplantedbioengineeringrecordingsystems. 125

PAGE 126

[1] M.A.L.Nicolelis,\Actionfromthoughts,"Nature,vol.409,pp.403{407,2001. [2] F.T.Hambrecht,\Naturalandarticialsensorsinneuralprosthesis,"inTech.Digest,IEEESolid-StateSensorConf.,1984,pp.5{7. [3] K.D.Wise,AMultichannelMicroprobeforBiopotentialRecording,Ph.D.disserta-tion,StandfordUniversity,1969. [4] I.Obeid,AWirelessmultichannelneuralrecordingplatformforreal-timebrainmachineinterface,Ph.D.dissertation,DepartmentofBiomedicalEngineering,DukeUniversity,Durham,NC,2004. [5] D.Chen,AnUltra-lowPowerNeuralRecordingSystemUsingPulseRepresentations,Ph.D.dissertation,DepartmentofElectricalandComputerEngineering,UniversityofFlorida,Gainesville,FL,May2006. [6] R.R.HarrisandC.Charles,\Alow-powerlow-noiseCMOSamplierforneuralrecordingapplications,"IEEEJournalofSolid-StateCircuits,vol.38(6),pp.958{965,2003. [7] N.M.NeihartandR.R.Harrison,\Alow-powerFMtransmitterforuseinneuralrecordingapplication,"in26thAnnualInternationalConferenceoftheIEEEEMBS,2004. [8] T.Seese,H.Harasaki,G.Saide,andC.Davies,\Characterizationoftissuemor-phology,angiogenesis,andtemperatureintheadaptiveresponseofmuscletissuetochronicheating,"Lab.Invest.,vol.78(12),pp.1553{1562,1998. [9] K.Naja,\Solid-statemicrosensorsforcorticalnerverecording,"IEEEEngineeringinMedicineandBiology,vol.June/July,pp.375{387,1994. [10] K.D.WiseandJ.B.Angell,\Alow-capacitancemultielectrodprobeforuseinextracelluarneuraphysiology,"IEEETransactiononBiomedicalengineering,vol.BME-22,pp.212{219,1975. [11] D.Chen,J.G.Harris,andJ.C.Principe,\Abio-amplierwithpulseoutput,"inProc.ofthe26thAnnualInternationalConferenceoftheIEEEEMBS,2004,pp.4071{4074. [12] Tucker-DavisTechnologies,\Preampliers,headstages,andmicrowirear-rays,"[updated2006;cited29November2006].Availablefrom [13] J.JiandK.D.Wise,\AnimplantabelCMOScircuitinterfaceformultiplexedmicroelectroderecordingarrays,"IEEEJournalofSolid-StateCircuits,vol.20(6),pp.433{443,1992. 126

PAGE 127

T.Akin,K.Naja,andR.M.Bradley,\Awirelessimplantabelmultichanneldigitalneuralrecordingsystemforamicromachinedsieveelectrode,"IEEEJournalofSolid-StateCircuits,vol.33(1),pp.109{118,1998. [15] D.Wei,Time-basedanalog-to-digitalconverters,Ph.D.dissertation,DepartmentofElectricalandComputerEngineering,UniversityofFlorida,Gainesville,FL,2005. [16] C.L.Rogers,J.G.Harris,J.C.Principe,andJ.C.Sanchez,\AnanalogVLSIimplementationofamulti-scalespikedetectionalgorithmforextracellularneuralrecordings,"inProceedingsofthe2ndInternationalIEEEEMBSConference,2005,pp.213{216. [17] CNEL,\Brainmachineinterfaceresearchgoal,"[updated2006;cited29Novem-ber2006].Availablefrom [18] MOSIS,\Packagehandbook,"[updated2006;cited29November2006].Availablefrom [19] C.Jakobson,I.Bloom,andY.Nemirovsky,\1/fnoiseinCMOStransistorsforanalogapplicationsfromsubthresholdtosaturation,"Solid-StateElectronics,vol.42(10),pp.1807{1817,1998. [20] J.C.Candy,\Anoverviewofbasicconcepts,"inDelta-SigmaDataConverters:Theory,DesignandSimulation,R.SchreierS.R.NorsworthyandG.C.Temes,Eds.,pp.1{43.JohnWileyandSons,Hoboken,NewJersey,1997. [21] A.A.LazarandL.T.Toth,\Timeencodingandperfectrecoveryofbandlimitedsignals,"inProc.ICASSP'03,2003. [22] D.Chen,Y.Li,J.G.Harris,andD.Xu,\AsynchronousbiphasicpulsesignalcodinganditsCMOSrealization,"inISCAS,2006. [23] [24] I.SeoandR.M.Fox,\Comparisonofquasi-/pseudo-oatinggatetechniquesandlow-voltageapplications,"AnalogIntegratedCircuitsandSignalProcessing,vol.47,pp.183{192,2006. [25] X.Qi,X.Guo,andJ.G.Harris,\Atime-to-rstspikeCMOSimager,"inISCAS,2004,pp.IV{824{7. [26] X.Qi,ATime-To-First-SpikeCMOSImageSensor,Ph.D.dissertation,Univ.ofFlorida,Gainesville,2004. 127

PAGE 128

X.Guo,ATime-basedAsynchronousReadoutCMOSImageSensor,Ph.D.disserta-tion,Univ.ofFlorida,Gainesville,2002. [28] K.A.Boahen,\Point-to-pointconnectivitybetweenneuromorphicchipsusingaddressevents,"IEEETranscactionsonCircuitsandSystemsII,vol.47,pp.416{434,2000. 128

PAGE 129

YuanLiwasborninYichang,China.HereceivedaB.SdegreeinphysicsfromWuhanUniversity,China,in1998.HealsoreceivedaM.SdegreeinelectricalengineeringfromSouthChinaUniversityofTechnology,in2001andaM.SdegreeinphysicsfromMississippiStateUniversityin2003.HereceivedthePh.D.degree(undertheguidanceofDr.JohnG.Harris)inelectricalengineeringin2007fromtheUniversityofFlorida,Gainesville,Florida.Since2003,Dr.LihasbeenaresearchassistantintheComputationalNeuroEngineer-ingLab(CNEL)attheUniversityofFlorida.Hisresearchinterestsincludeanalog/mixedsignalintegratedcircuitdesign,neuralrecordingsystemdesignandbiologicallyinspiredsignalprocessing. 129


Permanent Link: http://ufdc.ufl.edu/UFE0018102/00001

Material Information

Title: An integrated multichannel neural recording system with spike outputs
Physical Description: Mixed Material
Language: English
Creator: Li, Yuan ( Dissertant )
Harris, John G. ( Thesis advisor )
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2007
Copyright Date: 2007

Subjects

Subjects / Keywords: Electrical and Computer Engineering thesis, Ph. D.
Dissertations, Academic -- UF -- Electrical and Computer Engineering
Genre: bibliography   ( marcgt )
non-fiction   ( marcgt )
theses   ( marcgt )

Notes

Abstract: The increasing need for implantable devices in biological signal recording systems requires compact, ultra low-power and low-noise electronics. The continuous evolution of integrated circuit technologies partially helps in meeting these requirements by allowing for the realization of more complex functions in a given silicon area. The shrinking power supply helps reducing the power consumption, on the other hand, it also brings new challenges in terms of noise. The purpose of this research is to investigate the feasibility of a multi-channel neural recording system with spike outputs. The multi-channel system imposes four major constraints: large communication bandwidth, simple and compact circuit, low noise and low power. The proposed solution is to design a novel and simple current generator which can be directly used for biphasic spike representation. The current generator can convert the input alternating current voltage (AC) voltage to output AC current, while eliminating the direct current voltage (DC) voltage. By using this current generator, the total system is more compact and less noisy. Integrating the AC current, the output of each channel is a biphasic spike train. These multi-channel spike trains are then transmitted using the address event representation (AER), which can improve the communication efficiency. Preliminary theoretical analysis, simulation results and chip measurements show suitability for neural recording applications.
General Note: Title from title page of source document.
General Note: Document formatted into pages; contains 129 pages.
General Note: Includes vita.
Thesis: Thesis (Ph. D.)--University of Florida, 2007.
Bibliography: Includes bibliographical references.
General Note: Text (Electronic thesis) in PDF format.

Record Information

Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
Resource Identifier: aleph - 003874759
System ID: UFE0018102:00001

Permanent Link: http://ufdc.ufl.edu/UFE0018102/00001

Material Information

Title: An integrated multichannel neural recording system with spike outputs
Physical Description: Mixed Material
Language: English
Creator: Li, Yuan ( Dissertant )
Harris, John G. ( Thesis advisor )
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2007
Copyright Date: 2007

Subjects

Subjects / Keywords: Electrical and Computer Engineering thesis, Ph. D.
Dissertations, Academic -- UF -- Electrical and Computer Engineering
Genre: bibliography   ( marcgt )
non-fiction   ( marcgt )
theses   ( marcgt )

Notes

Abstract: The increasing need for implantable devices in biological signal recording systems requires compact, ultra low-power and low-noise electronics. The continuous evolution of integrated circuit technologies partially helps in meeting these requirements by allowing for the realization of more complex functions in a given silicon area. The shrinking power supply helps reducing the power consumption, on the other hand, it also brings new challenges in terms of noise. The purpose of this research is to investigate the feasibility of a multi-channel neural recording system with spike outputs. The multi-channel system imposes four major constraints: large communication bandwidth, simple and compact circuit, low noise and low power. The proposed solution is to design a novel and simple current generator which can be directly used for biphasic spike representation. The current generator can convert the input alternating current voltage (AC) voltage to output AC current, while eliminating the direct current voltage (DC) voltage. By using this current generator, the total system is more compact and less noisy. Integrating the AC current, the output of each channel is a biphasic spike train. These multi-channel spike trains are then transmitted using the address event representation (AER), which can improve the communication efficiency. Preliminary theoretical analysis, simulation results and chip measurements show suitability for neural recording applications.
General Note: Title from title page of source document.
General Note: Document formatted into pages; contains 129 pages.
General Note: Includes vita.
Thesis: Thesis (Ph. D.)--University of Florida, 2007.
Bibliography: Includes bibliographical references.
General Note: Text (Electronic thesis) in PDF format.

Record Information

Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
Resource Identifier: aleph - 003874759
System ID: UFE0018102:00001


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AN INTE GRATED MULTICHANNEL NEURAL RECORDING SYSTEM WITH SPIKE(
OUTPUTS



















By
YUAN LI


















A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY


UNIVERSITY OF FLORIDA

2007

































Copyright 2007

by
Yuan Li


































To my family









ACKENOWLED GMENTS

I would like to express my sincere gratitude to my advisor, Dr. .John G. Harris, for his

support and encouragement in the past years. None of this work could be possible without

his support and guidance. Dr. Harris has ak- -l-s encouraged me to learn more, to think in

different perspectives and to improve myself. The expertise and wisdom he continues to

share makes me a better engineer and a better person.

I also wish to extend a gracious thank you to Dr. .Jose C. Principe, who is leading the

lah and providing direction for us. I would like to thank Dr. Robert 31. Fox, for all the

knowledge I learned from his courses and Dr. .Justin C. Sanchez, for all the help he gave

me during my research.

Throughout my PhD research, Du Chen stands out in helping me understand

complementary nietal-oxide-silicon field-effect transistors (C'jIOS) neural recording design.

I am very grateful for her kindness and guidance. I would like to thank Xin Qi, Dongnming

Xu, C'!n -l i- Rogers and .Jie Xu for all of the discussions about my research. Further on, I

want to thank the rest of students in my lah; especially .Jin, Xi I. ::;; .Il- Kwansun, Meena,

Dazhi, Mark and Tomi, for making the lah a fun place to live and work.

I would like to express my deepest appreciation to my wife, Lin Z1! .Il-- for her great

love and support. Finally, I am especially grateful to my mother and my brother in Chan!~ I

for their love and support. I dedicate this dissertation to them.









TABLE OF CONTENTS


pagfe


ACKNOWLEDGMENTS

LIST OF TABLES.

LIST OF FIGURES

ABSTRACT

CHAPTER

1 INTRODUCTION


1.1 Extracellular Neural Signal Properties
1.2 Neural Recording System Overview.
1.2.1 Electrodes
1.2.2 Preamplifier
1.2.3 Readout Electronics and Some Data Reduction
1.3 University of Florida Brain Machine Interface Project
1.4 Research Goal.

2 SECOND-STAGE AMPLIFIER DESIGN


Discussion


Amplifier Structure
Operational Transconductance
Noise Analysis.
Measurement Results.


Amplifier Desigfn.


3 A NOVEL TRANSCONDUCTANCE AMPLIFIER AND BIPHASIC
INTEGRATE-AND-FIRE NEURON.

3.1 Introduction.
3.2 Transconductance Amplifier
3.3 Integrate-and-Fire Neuron.
3.3.1 Ideal Integrate-and-F'ire Neuron and Nonidealities
3.3.2 Biphasic Integrate-and-Fire Neuron and Nonideality Analysis
3.4 Operational Transconductance Amplifier Design.
3.4.1 Circuit Description
3.4.2 Noise and Power Consideration
3.5 Chip Layout.
3.6 Cadence Simulation Results
3.7 Measurement Results.
3.7.1 Single-Tone Input.
3.7.2 Neural-Simulator Input.
3.8 Practical issues
3.8.1 Signal Dependent Reference of the Comparator .























































124

126i

129


3.8.2 "Pseudo-Resistor" Introduced Direct Current Voltagfe Offset


4EIGHT-CHANNEL BIPHASIC INTE GRATE-AND-FIRE WITH
EVENT REPRESENTATION READOUT .......


ADDRESS


Introduction .....
Address Event Represt
4.2.1 Arbiter ....


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96;
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105
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109


entation S


structure .



. .
. .



. .
. .
. .
. .
. .


Clock


4.2.2 Row Interface .....
4.2.3 Latch and Latch Control
4.2.4 Througfhput Control ...
4.3 Chip Layout ......
4.4 Measurement Results ......
4.4.1 One-C'l .Ill., I Input ...
4.4.2 Two-C'l Iall., I Input ...
4.4.3 Three-C'l .Ill., I Input ..
4.4.4 Four-C'l Iall., I Input ...
4.4.5 Eigfht-C'l .Ill., I Input ..
4.5 Nonideal Issues ...... .


4.5.1 Timing Error Forced by the Readout


4.5.2
4.5.3


Spike Delay and Spike Loss ......
Noise Issue ...


5 SINGLE-STAGE TRANSCONDUCTANCE AMPLIFIER AND BIPHASIC
INTEGRATE-AND-FIRE NEURON.

5.1 Introduction.
5.2 Singfle-Stagfe Transconductance Amplifier.
5.3 Simulation Results
5.3.1 Cadence Simulation.
5.3.2 Matlab Simulation. .. ...... ....
5.4 Noise and Power Consideration

6 CONCLUSIONS ..........

REFERENCES ......... . .. . .

BIOGRAPHICAL SKETCH . . .










LIST OF TABLES

Table page

2-1 C'!I. .) ..teristics of second-stage amplifier ...... .. :30

:3-1 Spike-rate comparison ......... . .. 65

:3-2 Statistics results on the reconstructed signals .... .. . 67

:3-:3 Statistics results on the zeroed reconstructed signals .. .. .. .. 68

:3-4 Reconstructed neural signal spike sorting statistics ... .. .. .. 69

4-1 Eight-channel chip measurement summary ..... .. 106










LIST OF FIGURES

Figure page

1-1 Typical extracellular neuron recording techniques .... .. 1:3

1-2 Typical neural recording system architecture ..... .. 14

1-3 Three generations of recording system . ...... .. 19

2-1 Schematics of second-stage amplifier . ...... .. 22

2-2 Resistor-feedback amplifier alternating current voltage (AC) amplitude
response ......... . ... . 2:3

2-3 Capacitor-feedback amplifier AC amplitude response .. .. .. 24

2-4 Schematic of the Operational Transconductance Amplifier (OTA) with class AB
output stage ......... . .. 25

2-5 AC response of the class AB OTA ........ .. 26

2-6 Schematic of the OTA with class A output stage .... .. .. 27

2-7 AC response of the class A OTA ......... .. 28

2-8 1\easurenient results front neural signal simulator .... .. :31

:3-1 Schematic of the hiphasic pulse converter ...... .... 3:3

:3-2 Schematic of the gm amplifier ......... .. :34

:3-3 Equivalent circuit of the gm amplifier . ..... .. :35

:3-4 AC response of the gm amplifier ......... ... :37

:3-5 Ideal two-stage system for spike representation .... .. :38

:3-6 Schematic of the integrate-and-fire (IF) neuron .... .. :38

:3-7 Schematic of the practical IF neuron . ..... .. 41

:3-8 Impulse response of the gm amplifier . ..... .. 42

:3-9 Simulated time domain results ......... .. .. 44

:3-10 Simulated time domain results ......... .. .. 45

:3-11 signal-to-noise ratio (SER) vs. sine wave frequency ... ... .. 49

:3-12 SER vs. bypass resistance ......... . 51

:3-13 SER vs. output resistance ......... . 52










:3-14

:3-15

:3-16

:3-17

:3-18

:3-19

:3-20

:3-21

:3-22

:3-2:3

:3-24

:3-25

:3-26


:3-27

:3-28

:3-29

:3-:30

:3-:31

:3-:32

:3-:3:3

:3-:34


SER vs. input capacitance.

Schematic of the OTA

Layout of the single-channel hiphasic IF neuron chip

Reconstructed SER vs. input signal frequency.

SER vs. single tone frequency

Spike rate vs. sine wave frequency.

Measured reconstruction time domain result example.

Threshold vs. spike rate

Threshold vs. SER

Measured reconstruction time domain result example.

Measured reconstruction time domain result example.

Spike sorting result based on reconstructed neural signal

Comparison between the correctly identified action potential (1
and the missing action potentials (red dotted lines)

Six action potential classes.

Principal component analysis corresponding to the six templat

Coniparator hias current vs. SER.

Equivalent circuit of gm block with DC offset

SER vs. estimated DC offset .

SER vs. DC offset

SER vs. coniparator threshold.

SER vs. input single tone frequency .


blue


solid


line)


es.


4-1 Block diagram of the 8-channel address-event-representation (AER) recording
system.

4-2 Schematic of the arbiter cell.

4-:3 Schematic of the row interface.

4-4 Schematics of the latch cell and latch control.

4-5 Schematic of the throughput control block for clocked AER .











4-6 Chip layout of the 8-channel biphasic IF neuron with AER readout


4-7 Clock frequency vs. SER (one channel) ......


. 93

. 94

. 95

. 97

. 98

. 99

.. 100

.. 101

.. 102

.. 103

.. 104

.. 105

. 107

. . 108

.. 109

. 111

.. 113

input ... .. 113

.. 116

.. 117

.. 119

.. 120

.. 121

.. 122

.. 123


4-8

4-9

4-10

4-11

4-12

4-13

4-14

4-15

4-16

4-17

4-18

4-19

4-20

4-21

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10


Clock frequency vs. output spike rate (one channel) ......

Measured reconstruction time domain result example .....

Clock frequency vs. SER (two channels) .....

Clock frequency vs. output spike rate (two channels) .....

Measured reconstruction time domain result example .....

Clock frequency vs. SER (three channels) .....

Clock frequency vs. output spike rate (three channels) .....

Clock frequency vs. SER (four channels) .....

Clock frequency vs. output spike rate (four channels) .....

Clock frequency vs. SER (eight channels) .....

Measured reconstruction time domain result example .....

Clock frequency vs. SER (one channel Matlab simulation) ...

Clock frequency vs. SER (eight channel Matlab simulation) ..

C'I .Ill., I number vs. SER (Matlab simulation) ......

Schematic of single stage gm amplifier .....

Equivalent circuit of the single stage gm amplifier ......

Equivalent circuit of the single stage gm amplifier with negative

Simulated time domain example ......

Simulated time domain example ......

SER vs. low frequency signal amplitude .....

SER vs. load capacitance .....

SER vs. input signal amplitude .....

SER vs. input capacitance ......

SER vs. bypass resistance .....









Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

AN INTEGRATED MULTICHANNEL NEURAL RECORDING SYSTEM WITH SPIKE(
OUTPUTS

By

Yuan Li

May 2007

Cl.! ny~: John G. Harris
Major Department: Electrical and Computer Engineering

The increasing need for intplantable devices in biological signal recording systems

requires compact, ultra low-power and low-noise electronics. The continuous evolution of

integrated circuit technologies partially helps in meeting these requirements by allowing

for the realization of more complex functions in a given silicon area. The shrinking power

supply helps reducing the power consumption, on the other hand, it also brings new

challenges in terms of noise.

The purpose of this research is to investigate the feasibility of a multi-channel neural

recording system with spike outputs. The niulti-channel system imposes four 1!! i r~

constraints: large coninunication bandwidth, simple and compact circuit, low noise and

low power. The proposed solution is to design a novel and simple current generator which

can he directly used for hiphasic spike representation. The current generator can convert

the input alternating current voltage (AC) voltage to output AC current, while eliminating

the direct current voltage (DC) voltage. By using this current generator, the total system

is more compact and less noisy. Integrating the AC current, the output of each channel

is a hiphasic spike train. These niulti-channel spike trains are then transmitted using the

address event representation (AER), which can improve the coninunication efficiency.

Preliminary theoretical analysis, simulation results and chip measurements show suitability

for neural recording applications.









CHAPTER 1
INTRODUCTION

Scientists have long recognized the importance of the neuron as basic unit for

information processing and information storage in the human brain. Unfortunately, the

experimental methodologies to record neural electrical activity (local field potentials and

extracellular actions potentials or spikes) in freely behaving animals have become practical

only recently, and still pose many challenges. With up-to-date experimental techniques

and analytical tools, scientists have been able to extract neural information and use it

to generate real-time commands for controlling mechanical interfaces [1] or stimulating

prostheses [2], leading to the growing field of Brain-Machine Interfaces (BMI).

To better understand and utilize the mechanism in neural information processing,

scientists require many simultaneous neural recordings from behaving subjects. Thus it is

necessary to build microelectronic arrays with hundreds of electrodes and implant them

into the brain. Despite a great deal of progress during the past decades, the constraints on

power consumption, noise performance and bandwidth required to record and wirelessly

transmit the activity from a small portion of the cortex are beyond the state-of-the-art in

microelectronics and packaging. The research proposed herein addresses the IC hardware

implementation of a low-power multichannel neural recording system. In this system,

a novel voltage-to-current converter makes the biphasic spike representation practical.

The address event representation (AER) structure is used to improve the communication

channel utilization efficiency.

1.1 Extracellular Neural Signal Properties

The fluid inside of a neuron is high in potassium concentration while the outside

extracellular liquid is high in sodium concentration. The neural membrane contains

potassium, sodium and numerous other ion channels. These channels are closed in

the resting state. When a neuron receives sufficient stimuli from other neurons, its

cell membrane depolarizes and causes ionic currents to flow in its extracellular space.

Consequently, an extracellular signal is generated from the electrical charge imbalance










(among Na, K(, Cl and other ions) on either side of the biological membrane. When

measured extracellularly, the extracellular potential raises and an action potential (also

called a spike) normally with 50-500 pV in amplitude can be observed (see Fig. 1-1).

The relevant frequencies of these action potentials range from 100Hz to about 7 K(Hz [3].

Normally, action potential waveforms are usually either biphasic or triphasic with pulse

widths ranging from 0.4 ms to 3 ms [4]. Action potentials generated electrochemically by

individual neurons are the commonly recorded neural signal. After the action potential

is released, the neuron needs a small amount time (typically about 1 ms) before it can

generate another spike, called the refractory period.

Extracellular Signal
Extracellular Fluid + + + + + + + +
+, + +

+ Neuron +i -/i I I
++++




I:'+ + +Electrde -









Figure 1-1. Typical extracellular neuron recording techniques


As shown in Fig. 1-1, each electrode is surrounded by several neurons. The signals

from the closest neurons are strong and can be regarded as signals, while the signals from

farther neurons are normally attenuated too much and they can be thought as noise. One

electrode may record as many as four or five neurons. The resulting noise from distant

neurons in addition to thermal noise from electrodes can be as high as 20 pVms. The

signal to noise ratios (SNR) therefore range from OdB to 12dB [4]. Due to the unavoidable

electrochemical effects at the electrode-tissue interface, large DC offsets arise across the











recording sites. The amplitude of these DC offsets ranges from 1 V to 2 V [6], which is

much larger than the neural signals to be measured.

Besides action potentials from individual neurons, researchers are also interested in

activities of large groups of neurons. The synchronous firing of many neurons near the

electrode results in a low frequency oscillation, which is called the Local Field Potential

(LFP). The energy of the LFP in primate pre-motor and motor cortex has been shown to

correlate with specific arm reach movement parameters [7]. The frequency range of the

LFP is normally less than 100 Hz and could extend down to less than 1 Hz.

1.2 Neural Recording System Overview

Fr-om an engineering perspective, the functional building blocks of a neural recording

system are the electrodes, the pre-amplification filtering stages, and the coding and

transmission of the recorded signals. Electrodes are inserted into the tissue in the brain for

measuring the extracellular neural signal. Since the amplitude of the neural signal can be

as low as tens of pVms, it must be amplified before further processing. Then, the boosted

signal can be transmitted away from the subject for further processing. The typical neural

recording system architecture is shown in Fig. 1-2.


Innplantable HuDnt-Ad



Ele mmdes Amliiato Repm snna tion -I



lla nsmissio n
Channel

n aanas Cis Re c oS Is2cio Reeie -



Sig-na1Prc ess Back-Ad



Figure 1-2. Typical neural recording system architecture










1\ost current neuronal recording systems use wires to transmit the signal from the

electrodes out of the skin. For these systems, the animal must he tethered, which restricts

the subject's movements. The wires must he harnessed in a fashion to avoid entangling.

In addition, putting the wire through the skin can potentially cause infection at the

points where the wires break the skin for chronic implants. To get around these problems,

some research groups propose to implant the electrodes and use a wireless channel to

transmit the signal. In this case, some significant extra circuits such as oscillators,

modulators, and power amplifiers are required. Whether a wireless or wired system is

used, all the implanted parts must he as small and as lightweight as possible, especially

if multiple channels are to be recorded. In addition, some other factors also need careful

consideration.

Lower power consumption is also an important consideration to avoid damaging

surrounding tissue. Researchers have shown that a heat flux of only 80 mW/cH72 can cause

necrosis in muscle tissue [8] which severely restricts the power budget for a multiple chan-

nel neural recording system. Batteries powering the implant must he either periodically

replaced or frequently recharged.

Since the neural signals to be recorded have amplitudes of tens of microvolts with

frequency ranging from 1 Hz to 7 K(Hz, a low noise and low frequency hand-pass filter

must he used. Considering such tiny neural signals are superimposed on much larger DC

offsets introduced by the electrodes, the system must accommodate large input offsets at

the preamplifiers, which leaves the AC coupling system a good choice.

Because most of the preamplifiers can provide an intermediate gain of around 40dB,

the output signal from the preamplifier is still small. A second stage amplifier is normally

used to further boost the signal. The final output signal can he transmitted in an analog

format or in digital format after analog-to-digital conversion.










1.2.1 Electrodes

The electrodes are the first stage of the neural recording system. Therefore, the

properties of the electrodes greatly impact the performance of the total system. The more

accurate the neural recordings are from the electrodes, the higher the SNR of the output

signal will be. In order to record the extracellular neural signal from a few neurons, the

electrodes must he comparable to the size of the neurons (normally 50 pm or less). The

tips of the electrodes must he sharp enough to penetrate the tissue. In addition to the

physical requirements, the electrodes must also be biologically compatible so that they can

continue to record the neural signals over extended periods of time from months to years.

There are two major classes of electrodes: passive and active. Passive electrodes

are defined as ones which do not have any electronic circuit on the electrode substrate

[9]. Three basic passive electrodes widely used by neurophysiologists are metal, glass

micropipette and photoengraved microelectrodes. Active electrodes are characterized as

ones which include electronic circuits on the same substrate as the recording electrodes.

The on-chip circuits can he used to amplify the recorded signal, and change the output

data format. The circuits can also potentially minimize the effects of leakage from the

output wires, therefore improving the accuracy of the recorded signals. The first known

attempt to fabricate an active microelectrode array was made by Wise in 1975 at the

University of 1\ichigan [10].

To optimize the performance of the electrodes, three aspects should be carefully

considered in terms of AC frequency response, DC drift, and noise level:

1. The AC frequency response: Since the frequency of the recording signal extends from
below 1 Hz to around 7 K(Hz, the electrodes must not attenuate the signal within this
frequency hand.

2. The DC shift: One of the 1 in r~ challenges in interfacing electronics to a recording
electrode is the random wandering of the DC voltage. The DC potential between an
electrolyte and a metal electrode is subject to substantial variations and can he as
high as 50 mV for a gold surface, which is around 1000 times larger than the neural
signal to be recorded.










3. The noise level: It is expected that the input-referred electrode noise must be
significantly smaller than the amplitude of the measured signal. Since the amplitude
of the neural signal could be as low as 50 pV, it is important that the total input
noise is below 20 pVms [4]. The electrode noise results from the neural background
noise and thermal noise which is related to the recording bandwidth.

1.2.2 Preamplifier

Because the neural signal to be recorded has such a low amplitude, it must be

amplified before it can be further processed. The properties of the signals also put some

restrictions on the preamplifier. The preamplifier should have very low noise, have suitable

frequency response, consume very low power, and be fully integrated. Since the frequency

range of interest ranges from below 1 Hz to around 7 K(Hz, the preamplifier must reject

high frequency signals to improve the SNR. Considering the large DC shift associated with

the electrodes, the amplifier should also be able to reject the DC signal while passing the

AC signal. The noise performance of the preamplifier is also very important, because the

noise introduced in this stage will be carried and amplified by the following amplifier.

To achieve a very low cutoff frequency, a large time constant is required, which means

either a large capacitor, a large resistor or both. Some instrumentation amplifiers utilize

external capacitors in the range of nano Farads to create a low enough cut-off frequency

[4]. Such large capacitors are impractical for fully-integrated applications with current

technology. When a multichannel recording system is considered, this problem becomes

even more severe.

Based on Harrison's design [6], CI..~ .. and Harris from the University of Florida

have used diode-connected PMOS transistors acting as pI-' s to l -resistors" to develop a

low-power low-noise fully integrated neural amplifier (bioamplifier) [11]. The pI-' to 1 -

resistor" has huge resistance (greater than 100G0) while occupying a very small area.

This property makes it practical to fully integrate an amplifier with a very low cutoff

frequency.










1.2.3 Readout Electronics and Some Data Reduction Discussion

The amplified signal needs to be transferred for further signal processing. The simple

and straightforward readout method is to directly transmit the amplified analog signal

[4, 12]. For multichannel neural recording systems, the number of output leads will

increase as the number of recording channels increases. An analog multiplexer can he used

to reduce the output leads [13]. The amplified analog signal can also be digitized and then

transmitted.

For more advanced systems, the data and power transfer between the implant unit

and the outside world can he achieved through a wireless channel. Recorded signals could

be digitized before transmission which requires an on-chip ADC to enhance the signal-

to-noise ratio (SNR). To reduce the data rate, limited on-chip digital processing such

as compression [14] and spike detection can he used. On the other hand, the ADC and

modulators increase the die area and power consumption of the system.

Compared to analog, digital signals are much more robust to transmit, are easy

to store and can he processed by powerful digital algorithms. However, a conventional

ADC using Nyquist periodic sampling is not a suitable choice due to its large power

consumption when increasing the resolution. One solution to this limit is to employ the

integrate-and-fire (IF) representation [11, 15]. Single-direction spike representation has

been proven to reduce the required transmission data while still keeping the signal fidelity

[11, 15]. However, to generate unidirectional IF spikes, the existing single-direction spike

generator has to shift the current to guarantee only positive outputs. The resulting prob-

lem is the shifting DC increases the overall firingf rate and thus wastes communication

bandwidth, and also wastes power. To solve this problem, the hiphasic spike representa-

tion was developed for further data reduction [5].

Another choice to compress the transmission data is to just transmit the exact timing

of each action potential, which is associated with the spike detection technique. Even

though there is a debate about whether the neural information is encoded in the rate










of the spikes or with individual timing, both sides agree that the recording of the exact

timing of the spikes is crucial for further data on~ lli--- However, for extracellular neural

recording systems, multiple neurons are recorded on the same electrode, and in this case a

simple spike timing is not enough to distinguish among these neurons. Spike sorting can

be used to tag each spike before the transmission [16]. The detailed information about

spike detection and spike sorting can be found in [16].

1.3 University of Florida Brain Machine Interface Project

The University of Florida BMI project is one part of a multi-university DARPA-

sponsored project. The final target is to develop a new generation of tools in which direct

brain machine interfaces (BMIs) are used to allow subjects to interact seamlessly with a

v-1I r ii of actuators and sensory devices through the expression of their voluntary brain

activity [17].


Preamhp fie~ 2nd-st899 COmmercial / ss e~m

-' i i~ll2ndmStager Biphasic IF i AER


.. 0 amplifier (D. Chenl utpe ouao




Figure 1-3. Three generations of recording system


Fig. 1-3 shows the three generations of hardware recording system proposed in the

UF BMI project. In the first generation, the neural signal will be directly amplified by

80dB and the analog output will be sampled with a commercial product. In the second

generation, the differential neural signal will be first amplified by 40dB. The boosted

signal will then be encoded by a biphasic IF neuron. When there are more than one

channel in this system, an AER readout circuit is needed to multiplex these channels. The

third generation removes the preamplifier used in the second generation. When necessary,










the final outputs from any of the three generations can he transferred with either wireless

or wired channels.

1.4 Research Goal

The goal of this research is to develop a multichannel neural recording system.

The organization of this dissertation is as follows: C'!s Ilter 2 introduces a second-stage

amplifier design, which can he cascaded to the preamplifier to provide an 80dB gain for

the following ADC process (the second block in generation 1 in Fig. 1-:3). In C'! Ilpter

:3, a novel voltage-to-current converter is presented (the second block in generation 2 in

Fig. 1-3). This current generator makes the hiphasic spike representation practical. The

simulation results when used as the second stage are presented there with some system

analysis. Some chip measurement results including the single tone and neural simulator

signal will also be given. C'!s Ilter 4 combines the widely used address event representation

(AER) to the spike representation (the fourth block in generation 2 in Fig. 1-:3), and a

8-channel hiphasic IF AER system is proposed. This system transfers 8 channel hiphasic

IF outputs with 4 readout leads and thus greatly improves the communication channel

efficiency. Some simulation and chip measurement results will be shown in this chapter.

The hiphasic spike representation discussed in chapter 2 has to be used in the second

stage, where the first stage converts the differential neural signal into single-ended signal

and boosts the signal level. To simplify the circuit design, the single stage hiphasic spike

circuit is proposed. The Cadence simulation and circuit analysis will be given in chapter

5 (the first block in generation :3 in Fig. 1-:3). At last, the conclusions are discussed in









CHAPTER 2
SECOND-STAGE AMPLIFIER DESIGN

A low-noise 40dB bio-preamplifier was designed and tested as part of the University of

Florida BMI project [11]. However, considering the typical neural signals have amplitudes

of 50-500pV [3], the output from the preamplifier has amplitude of 5-50 mV, which is still

too small for input to commercial ADCs. Therefore, a second-stage amplifier is designed to

further amplify the signal.

2.1 Amplifier Structure

The second-stage amplifier has been implemented in two different structures. One of

the structures was originally proposed by Harrison in [6] and later used by C'I. 1. in the

preamplifier [11], which uses a capacitor-feedback network. Another version consists of a

resistor-feedback network. Fig. 2-1 shows the schematic of each amplifier. Both structures

operate with a +2.5V power supply.

In the resistor-feedback amplifier, R1 and C1 consist of a high-pass filter, which can

remove the DC component of the output signal from the preamplifier. Without this high-

pass filter, the output DC offset from the preamplifier can easily drive the second-stage

amplifier into the saturation region. The midband gain is determined by the ratio of the

two resistors R3/R2. This amplifier circuit was fabricated in the AMI 0.6p three-metal

two-poly process with a designed gain of 40dB. Using poly resistors, R1 was set to 9. 1j10,

R2 to 14.29KOR and R3 to 1.429MS2 (all these value were extracted in Cadence from the

layout). C1 was set to 180pF using poly-to-poly capacitors. C2 was used to simulate

the external capacitor load (including the package and the probe) and was set to 16pF.

This capacitor was not inside the chip layout. Since the extracellular action potentials

range from approximately 100Hz to 7K(Hz in the frequency domain [3], C1 and R1 need to

provide a cutoff frequency lower than 100Hz. The chosen values set the cutoff frequency at
94Hz.

The simulated frequency response using Cadence spectreS is given in Fig. 2-2. The

amplifier was designed to have a low cutoff frequency of 94Hz and high cutoff frequency










Vin Vou


R1 C


R2 R3 "






M1 C3 M2

Vin C1

Vout
OTA



Vref

(b)

Figure 2-1. Schematics of second-stage amplifier: (a) Resistor-feedback network; (b)
Capacitor-feedback network (the real circuit has 6 diode-connected transis-
tors).


of 19K(Hz, with the midland gain of 40dB. Since the preamplifier has cutoff frequencies

of 0.3Hz and 5.4K(Hz [5], the high cutoff frequency of the second-stage amplifier will not

have much effect on the final output signal. The 94Hz-low-cutoff-frequency will remove

the Local Field Potential (LFP) signal from the preamplifier output signal. This is one

of the disadvantages of this structure, however most neuron researchers ignore the LFP

anyway. In this resistor-feedback structure, on-chip resistors and capacitors require such

huge resistance and capacitance that they take up too much chip area. In fact, the resistor

and capacitor together use more than 90 percent of the layout area in the test chip. This

is the 1 in r~ disadvantages of this structure. Another disadvantage is that the resistors

continuously consume power, which is very serious since the valuable layout area prevents










us from further increasing the resistance. The power consumed by the resistor is inversely

proportional to R3, and proportional to the mean square of the output voltage. Such

power waste must be avoided in low-power applications. In addition, the input DC offset

of the operational transconductance amplifier (OTA) ptI i-s an important role here. When

there is no DC offset, the output DC voltage equals the reference voltage. However, if

Vo,f J 0, then Vout Vey = 100 x Vogy, which will possibly push the OTA out of its linear

region. Therefore, care must be taken in circuit design and chip layout to reduce the input

DC offset. In terms of the circuit design, the mismatch of the input differential pair has

the largest contribution to the offset voltage. Increasing the areas of these transistors can

reduce the DC offset with the added risk of degrading the OTA's stability. A common-

centroid layout was used to reduce transistor mismatch.

AC response


530




O3 20-

10~ -


100 101 102 103 104 10s 106
Frequency (Hz)

Figure 2-2. Resistor-feedback amplifier alternating current voltage (AC) amplitude re-
sponse


The capacitor-feedback amplifier was designed to avoid the above disadvantages in

the resistor-feedback amplifier. In this structure, the capacitor ratio C1/C3 determines

the midband gain, while Vey and 6 diode-connected transistors together provides the

DC operation bias. It was claimed that when the voltage difference across a single diode-

connected transistor is less than 0.2V, the diode-connected transistor can be viewed as a

pI-'' w l -resistor" with a resistance larger than 1010R [11]. Since most action potentials










have amplitude less than 250pV, which means the dynamic region will be less than 2.5V

after 80dB amplifier, 6 diode-connected transistors are enough to provide acceptable

linearity.

AC response




35 -











10 10 0 0 0


Frequency (Hz)


Figure 2-3. Capacitor-feedback amplifier AC amplitude response


Compared to the resistor-feedback amplifier, this capacitor-feedback version has

two advantages. First, since the signal path is just a capacitor network, no power will

be consumed. Second, the layout of this circuit is also much more area efficient. For

example, in the tested chip, the poly-to-poly capacitors C1 and C3 were set as 20pF and

200fF respectively. C2 was used to simulate the external load capacitor and was set to

16pF. This capacitor was not included in the chip layout. The diode-connected transistors

normally are minimum size (1.5p/0.6p in 0.6p technology). Fig. 2-3 shows the simulated

frequency response using Cadence spectreS where the amplifier has cutoff frequencies

of 0.3Hz and 19K(Hz with the midband gain of 39.9dB. Both the LFP and the action

potentials will be amplified with this amplifier. Similar to the resistor-feedback amplifier,

this structure also has a DC offset problem, which possibly comes from the substrate

current of the diode-connected transistors. This DC offset increases with the number of










the diode-connected transistors. Fortunately, the measurement results indicate that the

DC offset with 6 11-~ lalo-resistors" is .l.h-- li-- less than 500mV, which will not affect the

OTA's linear operation very much. If necessary, Vre; can be used to adjust the output DC

offset .

2.2 Operational Transconductance Amplifier Design


Figure 2-4. Schematic of the Operational Transconductance Amplifier (OTA) with class
AB output stage


Fig. 2-4 shows the first design of the OTA used in the 40dB second-stage amplifiers.

This is a typical two stage OTA. The first stage is a P-type input differential pair loaded

with Wilson current mirrors. A cascode current mirror is used to convert the differential

output into a single-ended output. Due to the high output impedance of the cascode

current mirror and the Wilson current mirror, the first stage provides a large gain:


A = GmRout


(2-1)


where Gm is the transconductance of differential input pair, and Rout is the cascode

current mirror output resistance parallel connected with the Wilson current mirror output










resistance:


Rout rV 9m10o10o1oo2 .' Aus,~o8ro6 (2-2)

The second stage is a voltage follower followed by a simple class-AB output

stage. M13 and M16 are DC voltage shifters while M17 and M18 form a push-pull

common-source output stage. This second stage also provides intermediate signal gain,

9ml'7(rol7||RL) or gmis(rols||IRL), depending on which transistor is active. The voltage

shifter controls the quiescent current of the output stage and the class-AB output stage

can sink or source more current when necessary. In addition, this common-source output

stage provides a rail-to-rail output range, which is expected in this 40dB second-stage am-

plifier. The Cadence simulation shows that the output DC voltage ranges from VSS+0.4V

to VDD-0.4V. This DC output range is enough for most action potentials. However, when

the action potential amplitude is greater than 400 pV, there will be some distortion in

the output. Increasing the quiescent current can increase the output DC range while

consuming more power.








50



100-


102 100 102 104 106
0rqecy(z

Figure~~~5 --.A epneoftecasA











Unlike the single-stage OTA which uses a load capacitor to provide compensation,

the two-stage OTA has to include the Miller capacitor C1 for compensation. A Cadence

simulation has been run to choose an appropriate C1. With a DIP40 package, the max-

imum capacitor associated with the pin is around 5.3pF [18]. Assuming that 10pF will

be provided by the external load, then a total load capacitor of 16pF should be used in

the simulation. When C1 is set to 2.5pF and the OTA is loaded by a 16pF capacitor, the

simulated AC response is given in Fig. 2-5. The DC gain is 137dB and the phase margin is

900 with -40dB feedback ratio.

VDD








lblas Vout1 u
Vmn Vmn-
M1 M





MS M3M4 M6 M14


VSS


Figure 2-6. Schematic of the OTA with class A output stage


The class AB output stage is good at providing a large load current to a resistive

load. In our case, the load will most likely be a capacitor, therefore, a simple class A

output stage OTA will be good enough for this amplifier. Fig. 2-6 shows the second design

of the OTA. Compared to the class AB OTA, both configurations have the same first

stage. In terms of the second stage, the class A OTA just uses M13 and M14 for DC

level shift. M15 and M16 are used to provide the class A output stage. The gain from

the first stage is same as that of class AB OTA, while the gain from the second stage














m 50-



1-2 100 102 104 106








-100-

10-2 100 102 104 106
Frequency (Hz)

Figure 2-7. AC response of the class A OTA


is 9ml6 Fol6 Frol5 IIL). R and C1 are used to provide the Miller compensation and their

values have to be determined from Cadence simulation with a load capacitor. When the

load capacitor of 16pF is used in the Cadence simulator, R and C1 can be set to 175KOR

and 2.5pF respectively to achieve around 900 phase margin for 40dB amplifier (see Fig. 2-

7). The DC gain of this class A OTA is around 126dB, which is a little bit lower than that

of class AB.

2.3 Noise Analysis

Compared to the preamplifier, the noise performance in the second-stage amplifier

is less crucial but it still needs some attention. The following analysis concentrates on

the thermal noise and the flicker noise, because they are the 1!! ri ~ noise sources in this

low-frequency C110OS application.

Both of the rail-to-rail OTAs have a two stage structure and the first stage has a

huge gain, thus the second stage has little contribution to input-referred noise and will

be neglected in the analysis. In the first stage, M7~-M10 are common gate transistors

and their noise contribution is negligible. Assuming that this circuit is perfectly matched,










which means that M3~M6 (indicated by M3) have the same size, M1 and M2 (indicated

by M1) have the same size and so do M11 and M12 (indicated by M11), the input-referred

thermal noise is:
16isT gm3 gm11
viTA = [ (1 +2 + )]af (2-3)
'Uni*/* I @l gml

From Eq. 2-3, it is clear that the input-referred thermal noise can be reduced by in-

creasing gmi or decreasing gm3 and gmit. The straightforward approach to achieve these

is to increase (W/L)1,2 or decrease (W/L)3,4,5,6, (W/L)11,12. However, the sizes and the

transconductance of M3~M6 and M11~M12 are related to the second and third non-
dominant ~ ~ lr plsb ~g/,whre is the total capacitance seen by the gate of Mi.

Reducing their sizes (reducing the gm) will push these poles close to the zero and may

introduce stability problems. Consequently, there is a tradeoff between stability and input

referred thermal noise.

Since the flicker noise is inversely proportional to the WL of the transistors, one

method to decrease the flicker noise is to increase the transistor area. However, with

the increase of the transistor area, the associated parasitic capacitors are also increased,

therefore possibly introducing the stability concerns. On the other hand, the total input-

referred noise of the capacitor-feedback amplifier is related to that of OTA by:

~C1 C3 +0
U i,amp i,OTA 2(24

whereI C1, C3) are~ shownIII in i. 2-1 ~I a ind0 is OTA input parasitic capacitor. With

increasing WL of the input transistors, Ci, and also U i~,am will be increased. As a result,

there is a tradeoff between the amplifier input-referred flicker noise, OTA input-referred

total noise and system stability. It is also believed that PMOS devices experience less

flicker noise than NMOS devices [19] and PMOS transistors are chosen for the differential

pair for this reason.









Table 2-1. C'!I. .) .:teristics of second-stage amplifier

Parameter Capacitor-feedback Amp Resistor-feedback Amp
Supply voltage 5V 5V
Power consumption ~120p-W ~120p-W
Gain ~40dB ~40dB
Input DC offset 1~5mV 1~5mV
Low cutoff frequencies <1Hz ~94Hz
High cutoff frequencies ~19K(Hz ~19K(Hz
Layout area ~66400p~m2 ~860000p~m2
Output DC range VSS+0.45~VDD-0.5 VSS+0.45~VDD-0.5


2.4 Measurement Results

The amplifier with class AB OTA has been fabricated using the AMI 0.6um process

with a DIP40 package. All the capacitors were implemented with poly 1 .v. ir The chip

has been successfully tested.

During all the measurement setups, the OTA was biased with 8pA current. First,

the DC characteristics were tested based on 10 resistor-feedback amplifiers. Of the 10

channels, 4 channels' DC offset were less than 1 mV; 3 were less than 2 mV; 2 were

less than 3 mV and 1 was less than 5mV. The resulting maximum output DC offset is

less than 500mV. Apparently, such small DC offset is not a big issue in this application

considering the power supply and the signal dynamic range, which will also be verified by

the following measurement results.

An Agilent 33220A signal generator was used in the testing. The measurement results

are similar to the Cadence simulation. The gain is around 40dB, and the cutoff frequencies

also match the Cadence simulation. The minimum and maximum DC output values are

0.45V and VDD-0.5V. One of the chips includes the first 40dB amplifier designed by C'I. 1.

[11] cascaded by the resistor-feedback 40dB amplifier and this cascaded 80dB amplifier was

also tested. The signal from the Agilent 33220A was first attenuated by 40dB and then fed

into the 80dB amplifier as input and the measurement results verify the simulation. The

specifications of these two second-stage amplifiers are listed in Table 2-1.









The Bionic 128 Channel Neural Signal Simulator was also used for the testing. Two

setups were used in this testing. The first setup is C'I. i.'s 40dB preamplifier and second-

stage 40dB amplifiers which were fabricated in individual chips and cascaded externally.

One of the measurement results from this setup is given in Fig. 2-8. The neural action

potentials with amplitude of around +1.0V are clear and the total gain is around 80dB.

When these two stages were fabricated in the same chip, no matter whether the output

from the preamplifier to input of the second-stage amplifier was internally or externally

connected, there was ah-- .1-< a steady oscillation once the input is connected to the neural

signal simulator. The oscillation frequency is around 6K(Hz and it can be finely adjusted

by the bias current. However, these same setups ahr-l- .- work very well with the Agilent

33220A signal generator. We suspect that this oscillation comes from the input impedance

mismatch and the substrate power supply kick-back due to the heavy substrate doping.





O2

-0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015




02- -

-0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015
2x10-4




-0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015
Time (second)


Figure 2-8. Measurement results from neural signal simulator: (a) Results from the
capacitor-feedback amplifier; (b) Results from the resistor-feedback amplifier;
(c) Neural signal simulator output.









CHAPTER 3
A NOVEL TR ANSCONDITCTANCE AMPLIFIER AND BIPHASIC
INTEGRATE-AND-FIRE NEITRON

3.1 Introduction

Compared to analog signals, digital signals are much more robust to transmit, easily

storable and can he processed by powerful digital algorithms. The most popular A/D

converter is based on periodic Nyquist-Rate sampling, which can he loosely defined as a

converter which generates a uniformly spaced series of binary output values corresponding

to an instantaneous input value. The resolution of such an A/D converter is limited by

the power budget of the particular application. a E A/D converters are coninonly used

to relax the requirements on the analog circuit at the expense of more complicated digital

circuitry [20].

Inspired by research results in neuroscience that -II__- -r biological systems represent

sensory information using the timing of all-or-nothing action potentials [21], a low-power

pulse signal representation circuit has been proposed for neural recording applications

[11, 15]. This circuit converts an analog voltage waveform to a pulse train and the original

analog signal can he reconstructed with a digital algorithm under certain assumptions.

The existing pulse output circuit converts the voltage to a current that was shifted to

guarantee positive only outputs. The positive current was then fed into a simple integrate-

and-fire (IF) neruon circuit for generating a spike train. Even though this circuit has been

shown to encode the original signal with high SNR (103 dB in Matlah simulation), there

are still 1! in r~ intprovenients necessary to reduce the data rate and the overall power

consumption.

By shifting the current so that there is only positive current, the overall firing rate,

the power consumption and the required coninunication bandwidth have been greatly

increased. The extreme case is that when the signal during some period is zero, the shifted

signal will still generate unnecessary spikes.











Positive pulse


Negative pulse


Buffer OR


Figure 3-1. Schematic of the hiphasic pulse converter


To solve this problem, a hiphasic spike representation is proposed [11]. Rather

than shift the signal to be positive only, a hiphasic mode spike generators using two

comparators with different thresholds is intpleniented in Fig. 3-1. A single capacitor is

used to integrate the input current but a positive and negative threshold are intpleniented

using two comparators. When the voltage across the capacitor rises above the positive

threshold, a pull six,- spike is generated; similarly a n!, y~,.1ii pulse is created when the

voltage drops below the negative threshold. After either spike is generated, the voltage

on the capacitor is reset to a midrange voltage value by the digital control circuit. When

the input current is zero-valued, no spike will be generated; on the other hand, if the

amplitude of the input current is high, the firing rate will be correspondingly high. A

simulation for a speech signal has shown that this structure dramatically reduce the firing

rate without sacrificing the signal fidelity [5].

Even though this circuit has many advantages compared to the unidirectional pulse

representation, the circuit to generate the required current has been a problem because

this current generator must he able to reject the DC component of the signal and convert

only the AC voltage to AC current. Proper DC hiasing must he set to allow the OTA

(operational transconductance amplifier) to operate in a suitable region. At the same










time, the output resistance should be high enough for reducing the leaky current. In this

chapter, a novel and simple current generator to generate biphasic spikes is proposed.

Matlab simulation results and chip measurements will be shown. Following these, some

nonideal factors in this circuit are discussed.

3.2 Transconductance Amplifier




M1 M2


Vin n Vu
OTA


Vref


Figure 3-2. Schematic of the gm amplifier


Fig. 3-2 shows the schematic of the gm amplifier, where M1 and M2 are two diode-

connected PMOS transistors. They act as pI'I I''-resistors" with huge resistance greater

than 10110. From the intuition, this huge resistor can be viewed as the DC pass path

and AC stop path or this circuit can be seen as a DC closed loop and AC open loop. The

close-looped DC configuration forces the DC voltages at the negative input node and

output node of the OTA to follow the DC voltage fixed by the positive input node Ve;

while the open-looped AC configuration fully utilizes the high open-loop gain of this OTA.

This circuit rejects the DC signal and amplifies the AC signal of interest, which makes

it suitable for the current generator. Another advantage of this circuit is that the OTA

is configured as a voltage follower for DC operation so that the DC offset introduced by

the input differential pair will not be amplified. For example, if the OTA has a 5 mV

offset, which is a typical value, then the output offset will be also around 5 mV. This offset

range is tolerable for moderate accuracy applications. For the special neural recording










application in this biphasic spike generator, if the thresholds are set to hundreds of mV,

this 5mV-offset is also tolerable.

Vin C~1 R Vout


IVx GmVrO C





Figure 3-3. Equivalent circuit of the gm amplifier


To understand to which extent this gm amplifier works, a detailed transfer function

analysis is conducted. To simplify the derivation, the OTA is modelled as one with

transconductance of gm and output resistance of ro. The equivalent circuit of the gm

amplifier is shown in Fig. 3-3 where the "pesudo-resistor" is represented by R and the load

capacitor (or integrating capacitor) by CL.

First note that

(I,- m~)( ro ) + IR = V,. (3-1)
1 + juoC Lro

that is,

R, = 1+pocro (3-2)

Here R, is the impedance looking into the right side of the circuit. Based on this equation,

the total current I, can be written as


I, = (3-3)
+R

Deriving the relationship between 1Ms and Vout gives:


jw1









Combining Eq. 3-1 to Eq. 3-4, the total transfer function of this gm amplifier can be

written as
Vout jwroC1(1 GmR)
H(w) =.(3-5)
En(1 + jwC1R)(1 + jwcC Lro) + ro(Gm + jwC1)
Based on this transfer function, it is apparent that this system has one zero and two poles.

The zero lies at the origin so that the gain first increases at 20dB per decade. It is difficult

to locate these two poles for the general case. However, in some special cases, these two

poles can be solved.

To solve for these two poles, the denominator is set equal to zero:


(1 + jwC1R)(1 + jwCero) + ro(Gm + jwC, ) = 0. (3-6)


If the parameters have these typical values:


R =1013R;(7


Ci = CL = 20pF, (3-8)

Gm = 30 x 10-6 -1, _9)

ro = 2.67x 109R (310)

Eq. 3-6 can be simplified as


(jW)2 C 1T0 L (o'R 1 TOGm ~V 0. (3-11)


which can be further simplified as


(ju(j + ro- 1 (3-12)
RCI roCL

Two poles are straightforward:


I cpl TO, p 2 3 )
RCI roCr,










Practically, R can not be very large, for example, R implemented with diode-connected

transistor just has a resistance on the order of 10110. In the general case, Eq. 3-5 can be

rewritten as


H(w) =wo

9 /( )2 1 jaL

;l RC1 '


(3-14)


with


G~ml
Ho 7


Gmro
RC ro CL


(3-15)


10-2 101 100 101 102 103 104 105 106 107


-100

S-200

2 -300


102 103
Frequency (Hz)


Figure 3-4. AC response of the gm amplifier: (a) Amplitude
Phase shift of the amplifier response.


of the amplifier response, (b)


Fig. 3-4 shows the frequency amplitude response and the corresponding phase shift

from a Cadence simulation using R = 10110, the other parameters are set by Eq. 3-8 to

Eq. 3-10. The simulation results match with Eq. 3-14 very well except that the peak gain

has less than 10dB difference.









3.3 Integrate-and-Fire Neuron

3.3.1 Ideal Integrate-and-Fire Neuron and Nonidealities


H (w)


H, (W)


x(t) --


Sy(t)


pl, p2


Figure :3-5. Ideal two-stage system for spike representation


The ideal integrate-and-fire (IF) neuron can he considered as a low-pass filter with a

pole at zero and the output resistance of infinity. Therefore all the input current goes into

the capacitor. In addition, to satisfying the bandwidth requirement, the signal must he

filtered first. The ideal two-stage IF system can he shown as Fig. :3-5.


-Current x(t)


SVcap


pulse

Comparato


CT


Figure :3-6. Schematic of the integrate-and-fire (IF) neuron


In the time domain, the operation of this IF neuron can he simply described as

follows. Once the voltage on the load capacitor up, crosses the threshold Vax, a spike is

generated and the voltage is reset to the analog ground. After some refractory period, the









neuron begins to integrate again (see Fig. 3-6). The spike times tie and tib muSt SatiSfy the

following relation:





In fact, after the neuron is reset, the new integration process can be viewed as the

response with input of x(t) and the system impulse response h(t). In the ideal IF neuron,
the impulse response is in the s-domain and 1ut) in the time donmain. The system

response with x(t) as input can be written as Eq. 3-16.

There are two signal reconstruction methods from the spike train: the iterative

method and the close-form or weighted low-pass kernel WLPK( method. Interested readers

can find a detailed discussion in [5] and [15]. For the reader's convenience, the WLPK(

method is briefly listed here.

Assume the pulse width -r is much less than the pulse time interval and can be

ignored, the spike train output can be written as


p(t) = Cf(- ) (3-17)
iEZ

A sufficient boundary condition for perfect reconstruction requires:


ti 1 tis I (3-18)


where &0~, in the maximum fr-equency of the bandlimited input signal x(t). Let Sew, ~dl

= Vth,h'(t) = 2f,,,sinc(2;Trked,), and as = (ti 1 + ti)/2.


H = [h'(t as)]l (3-19)


Aij h'(t a )dt (3-20)

x(t) = CVthA-1H (3-21)










Often A is not full rank and regularization-type techniques are necessary to compute the

inverse [15].

Following the above reconstruction procedure, the Matlab simulation can reconstruct

the original signal x(t) with SER (signal to error power ratio) of 103dB. However, in

a realistic system, there is ak--ws- finite output resistance due to the current generator

block. During the integration process, the resistor leaks some current and introduces an

error in reconstruction. This neuron model is called the leaky IF neuron. For example,

if the OTA is used to generate the current, the output resistance of the integrator is the

output resistance of the OTA, which is normally very large (see Fig. 3-7). In this case,

the integration is no longer an ideal process. The voltage on the load capacitor is in fact

the convolution of the current and the system impulse response e roC The signal can still

be perfectly reconstructed if the value of ro is known exactly. The detailed an~ ll-k- for

this problem can be found in [15]. Actually, this leaky IF model can be used to relax the

constraint on the amplifier. For example, a resistance-known resistor can be intentionally

added parallel to the load capacitor. In this case, the added resistance is much less than

the OTA's output resistance, and the leakage from the OTA's output resistance can be

ignored. Since the added resistance is already known, it can be directly used for perfect

reconstruction. The other benefit of using this model is that the leakage can reduce the

output spike rate, which can further relax the requirement on the power consumption and

the communication bandwidth.

3.3.2 Biphasic Integrate-and-Fire Neuron and Nonideality Analysis

Replacing the current source in Fig. 3-1 by Fig. 3-2 leads to the biphasic IF neuron

implementation. This current generator is a second-order system and the output resistance

is affected by the feedback, so that the analysis will be more complicated.

First, the integration process needs to be analyzed before further analysis. Every time

after the neuron is reset, the voltage on the capacitor follows the convolution between

the input signal I%,(t) and the system response h(t). So, the first step is to estimate the











VYint) OTA


Current x(t)

rO 5ITVcap


pulse

..Comarto


Figure 3-7. Schematic of the practical IF neuron

system impulse response h(t). Based on Eq. 3-11, the s-domain transfer function is:


Vout (s) sroC1(1 GmR)
%,(8) (1 + Sc/iR)(1 +sC cro) +(ro(G +SC/)


H(s)


(3-22)


With the assumptions that GmR >> 1, RC1 >> Caro, roC1, roGm >> 1 and >- ,\

which are true in our application, the transfer function can be further simplified as

Vout (S)
H (s)=


sro C GmR

2CL (s + )2 _Gm__ _
2C~roCT RCLE

CL (s + lr)2 CCGlm

J 2C ro G+
C~ (S2Ciero) C1RCE


1,~


2CLro
1 2 z-) 1CGm


(323)


Con~sider th~at

= {e 2CL'o cos( t)
CL CI RQ L
Gm GmC:
~ {e 2CL'o cos( t)}
CL CI RC:L


1/ CRC/L r
e cero
2CLro Gm


.Gm
smn( t)}
C1 RCL


h(t)


t > 0


(3-24)












x 10"
15


S0-



-0 5-








0 0 01 0 02 0 03 0 04 0 05 0 06 0 07 0 08 0 09 0 1
Time (s)



Figure 3-8. Impulse response of the gm amplifier


With the parameters specified by Eq. 3-8, 3-9 and Eq. 3-10, and R = 10110, the

impulse response is plotted in Fig. 3-8. This is a cosine wave with exponential decaying

amplitude. During the system operation, when the voltage on the load capacitor CL us,

equals the threshold, a spike is generated. At the same time, the voltage on the capacitor

is reset to analog ground. After the reset, the next integration stage begins with initial

state of Vout(tib) = 0 until V,,t(tie) = Vth and the second spike is generated. This process

can be described as the convolution between the input voltage signal I%,(t) and the

impulse response from the input voltage to the output voltage h(t) (this impulse response

has already included the integration capacitor):


%,he- Vttdt= a (3-25)










If ro and R are infinite, the impulse response is simply a step function, and the integration

is ideal. In the above equation, the integration does not represent the IF neuron's integra-

tion process, but means the convolution between the input and the impulse response. Or

the above equation can be rewritten as a more familiar format:


It ~td= Vt. (3-26)

where i(t) means the corresponding current integrated over the integration capacitor. The

integration in this equation is used to represent the IF neuron's integration process. The

expression of i(t) can be derived from Eq. 3-24 to Eq. 3-26.

The close-form reconstruction algorithm for the biphasic spike train is very similar

to that of the unidirectional spike train. Cl.,~ i. has the detailed proof in [5]. The main

difference is that Vth has just one value in the unidirectional spike train (see Eq. 3-21)

while it have two values in the biphasic spike train. If the leaky current is not considered

in the reconstruction algorithm, the achieved SER is around 80dB. The error signal is

defined as the difference between the original signal and the reconstructed signal. The

SER is the power ratio between the original signal and the error signal.

Fig. 3-9 shows the reconstructed signal compared to the original signal. The original

signal is the superposition of five sine waves with frequency of 0.1 Hz, 10 Hz, 100Hz,

1000Hz and 5000Hz respectively and amplitude of 0.03V. The positive and negative

thresholds are 0.4V and -0.4V respectively. The step size in the Matlab simulation is

Ins. The total number of spikes within 1.8 ms is 171. The circuit parameters used for

the Matlab simulation are the same as those used for generating the impulse response

in Fig. 3-8. The original signal and the reconstructed signal are normalized for easy

comparison.




























-Onginal
Reconstructed
0 02 04 06 08 1 12 14 16 18

2x1 0- 4c
-15-

~05-
S0-
-0 5-
O 02 04 06 08 1 12 14 16 18
Time (ms)




Figure 3-9. Simulated time domain results: (a) The signal on the load capacitor V,,p; (b)
Comparison between the original signal and the reconstructed signal (both
signals are normalized); (c) Errors between the original signal and the recon-
structed signal.


If the circuit parameters are known, the coefficient matrix A in Eq. 3-20 can be

recalculated using the following equation:



Aij =I h'(t ad~h(t t, 1)dt (3-27)


This coefficient matrix is calibrated with the impulse response, so that the reconstruction

signal can achieve much higher SER. The reconstructed signal using this matrix is shown

in Fig. 3-10 and the achieved SER is 102dB.

Even if it is possible that the original signal can be perfectly reconstructed from

the spike train given known parameters, in practice the parameters To and R are usually

signal- and process-dependent terms and exhibit some nonlinearity and unpredictability.














08-
O6-
04-
O 2


-0 2-
-0 4~ -Onginal
-0 60 02 04 06 08 1 12 14 16 18



1105 (b)



L05-



-0 5-



-1 50 02 04 06 08 1 12 14 16 18
Time (ms)




Figure 3-10. Simulated time domain results: (a) Comparison between original signal and
reconstructed signal (hoth signals are normalized); (b) Errors between origi-
nal signal and reconstructed signal.



For example, ro is inversely proportional to the bias current in the output stage, and R

is especially dependent on the voltage across the two pI- m lo'-resistors". It is difficult to

have "perfect" reconstruction performance by applying the close-form algorithm. There-

fore, we can treat this system as an ideal neuron during reconstruction and investigate the

performance limitation due to the current leakage.

If the accurate charge leakage through the output resistor can he calculated, the exact

integration value of the input signal over this integration period can he obtained and the

original signal can he perfectly reconstructed mathematically. Therefore, it is helpful to

estimate the reconstruction performance by investigating the relationship between the

charge leakage and the input signal. Since the hiphasic IF neuron uses the AC coupling









structure, only the AC component of the signal can affect the reconstruction performance.

Assume that 1%, and 1Ms are the value of I%,(t) and the value of the first-order derivative

at t = ti respectively. When the integration period is very short, I%,(t) can be assumed to

be a linear function of time t, and it can be approximated as 1%, + I%,(t ti) for the i-th

integration period. To simplify the derivation, some Taylor series approximations are used:

e" m 1 + x, ifx
and
x2
cos(x) a 1 -,ifx
To simplify the notation, a and b are used to represent andre

spectively in the following derivation. Based on the integration equation 3-25, we can
obtain:




0 = CLv,,

-Gm ,tee,-~csbtI-td




-Gm (K,, + 8,t)e"(T -c)cos(b(T, t))dt




-Gm(K + Tis) eacos(bt)di + GmK,T tearcos(bt)di

-G(n+ gs (1 + at)(1 )dt
/W, b2t
+C o 2 d
a b2 2 3~
-G(% + i)i+Ti2 _-T3)+ m"(
2 6i 2 3

-GbT + Ti2 _- -T3) GmV4,(1Ti2 -T3) (330)
2 6i 2 6i









Where the higher order of Ti than 4-th are ignored in the last step. Since the integration

is treated as ideal process in reconstruction, the accurate integration of IK,(t) over the i-th

integration period is:


tii





T2b


ti))dt


(3-31)


+GzaT3
6i


(3-32)


The reason that absolute value is used here is that the output current has reversed phase

compared to the input. The error is just introduced by absolute charge.

The corresponding noise power due to the leakage charge can be calculated as (using

Eq. 3-21):


=E[(I%,(t) V4,(t))2]


G2E [(it i(t)(O )j]






E :~[(h (t))2] {E[(T%:, T22 + E[(%, T)2] + E[(1%, T,3)21

E[(h()2] E[(, ( )2 ] + E[(1K, ( )3 2


Pnoise,leakage


a( CVT
E[M" Gmu 3 2""j


(333)









where the approximation is made due to CLt My GmITi. The signal power is:


Psignal = E [(lEn(t))2]







The SER (signal to error ratio) due to the leakage is:

Psignal
SERleakage
Pnoise,leakage

E[a2 (cL4wh 2] + E ( cs 4 +E[ )22 1
4GmV, n1 3 GmV, n n, 36 GmV, n


T;~E [ ]2 + ,c h2 En [1 ]n + E

V2 4(3-35)
Eh [ L + ,h2 E [ ]

where, E[(Ei & ()L)2 C E[(h (t))2] is used for the first approximation. During the

second approximation, the last term of the denominator is ignored because it is very small

compared to the first two terms.

Eq. 3-35 shows the dependence of the SER on the parameters of the biphasic IF

neuron and input signal. The SER can be improved by increasing the OTA output

resistance ro or increasing the bypass resistance R. This argument is consistent with

Eq. 3-24. Based on Eq. 3-24, when ro increases, the slower exponential decay will

introduce less leakage charge. If R is increased, the cosine wave has smaller frequency

and the slower cosine decay can improve the SER. Larger C1 also leads to a larger SER

by reducing the cosine wave frequency. Increasing Gm or reducing CL also reduces the

charge leakage and increases the SER. Actually both of Gm and CL have two different

effects. First, they determine the gain and therefore affect the spike frequency. On the

other hand, they also alternate the cosine wave frequency of the impulse response and

change the leakage error. However, compared to the second effect, the first one is more











dominant. Smaller Vth can increase the spike frequency and increase the SER. Eq. 3-35

also indicates that the SER is proportional to E[1M(]. The reason is that a larger input

signal amplitude increases the spike frequency and hence increases the SER. It is shown

that the unidirectional-spike reconstructed signal SER decreases when the input signal

frequency increases [15]. However, in the biphasic IF representation, the frequency has

little effect on the SER, which can be seen from Eq. 3-35. To verify the SER's frequency

independence, the results from a Matlab simulation and Eq. 3-35 are given in Fig. 3-11.

The parameters of the biphasic IF neuron are: Cz = 20pF, Vth = +0.4V, Gm = 30an2-1, ro

=2.6 x 1090, R = 10 0S, and the input is a single tone with different frequency and same

amplitude of 30mV.



SSimulation
** ** Equation
80 -













40 -


30 -



102 103 104
Sine wave frequency (Hz)



Figure 3-11. signal-to-noise ratio (SER) vs. sine wave frequency


Based on the above analysis, the direction to improve SER is clear. Due to the

practical signal properties and available CijlOS process technology, there are not ]rn Ilw










options to combine. For example, the average firingf rate is related to the communication

bandwidth of the readout circuit and is usually a predefined number. Therefore, reducing

Vth, increasing Gm and reducing CL increases SER by increasing the spike rate are not

good choices under the bandwidth constraint. ro and R can be changed without affecting

the spike rate, however, the available fabrication technology and circuit design prohibit us

from freely choosing the values. This leaves C1 as the only choice. However, limited chip

layout area restricts large capacitance.

Several simulations are run in Matlab to validate the above discussion. Without

additional declarations, the parameters of the biphasic IF neuron are: C1 = 20pF, Ms =

+0.4V, Gm = 30an2-1, ro = 2.6 x 1090, R = 1010S, and the signal is the superposition

of five sines wave with the same amplitude of 30mV and different frequencies of 0.1Hz,

10Hz, 100Hz, 1000Hz and 5000Hz. In the following figures the dotted line with stars and

the solid line with circles represent the results from the Matlab simulation and Eq. 3-35,

respectively. All the Matlab simulations were run with the step size of Ins.

Fig. 3-12 shows the dependence of the SER on the bypass resistor R. The equation

matches the simulation very well with a slope of 20dB/decade. Both curves predict that

there is a SER saturation when R is above 10120. This is due to other nonideal factors.

Fig. 3-13 shows the dependence of the SER on the OTA output resistor ro. When

ro < 1090, the equation matches the simulation very well with a slope of 20dB/decade.

Both curves predict that there is a SER saturation when R is above 10100. However, there

is around 12dB difference between the saturation SER values. Compared to Fig. 3-12,

the saturation here occurs earlier than that of the bypass resistor. Other than that, SER

corresponding to the saturation output resistor is 3dB lower than that of bypass resistor

from the Matlab simulation. These differences mean that the bypass resistor pIIl i. a more

important role in increasing SER.














SEquation
85 H *--Simulation : : ::

80~ ; .. . *

75-

70-

a 65-

5f 60-

55-

50 I ;

45 :: : :.--:: i::ii. ..

40 -::: ::I--:: I :::II: ::

35
108 109 1010 101 1012 1013
Bypass resistance (Ohm)



Figure 3-12. SER vs. bypass resistance


Fig. 3-14 shows the dependence of SER on the input capacitor Cz. When C1 > 0.1nF,

the equation matches the simulation well. Otherwise, the difference between the equation

and the simulation is 8dB maximum. There is also a SER saturation in this figure.

3.4 Operational Transconductance Amplifier Design

Based on the previous discussion about SER, it is apparent that one option in OTA

design is to make the output resistance as high as possible. Alternatively, we can add an

explicit leak resistance of known value. Then the requirement of high output resistance

of the OTA can be relaxed. As we discussed in the previous section, this leaky integrator

will bring other benefits. The other factors under consideration are power consumption,

transconductance Gm, noise issues and stability.













SEquation
95 H *-Simulation...

90-

85 -



m 75-

a 70-

65-

60-

55-

50 -

45
107 108 109 1010 101 1012
Output resistance (Ohm)



Figure 3-13. SER vs. output resistance


3.4.1 Circuit Description

Fig. 3-15 shows the schematic of the OTA used in the biphasic IF neuron. The OTA

is a typical single-stage C110OS amplifier with a P-type input differential pair operating

from a +2.5V power supply. The input differential pair is loaded with a cascode current

mirror. Another cascode current mirror is used to convert the differential output to

single-ended output. The cascode current mirrors give a high output resistance for this

O TA:

ro = Routlo || Routl4 (3-36)


where both Routlo and Routl4 are the output resistance from a cascode current mirror,

thus:

Routlo 9mglorol27010 (3 37
























78 -8


76-


74-


72-


70
10-12 10~1 10-10 10-9
Input capacitance (F)


Figure 3-14. SER vs. input capacitance


Routl4 gml4To6Tol4 (338)


This OTA just has one dominant p~ole at to = -- ,1 which guarantees that it is stab~le in

most cases.

3.4.2 Noise and Power Consideration

M7~M10 and M13, M14 in Fig. 3-15 are common gate transistors, and their thermal

noise contribution is negligible. The input pair M1 and M2 have identical size and their

transconductance is denoted as gmi. The cascode current mirrors M3~M8 also have

identical size and the transconductance is denoted as gm3. The transconductance of M11

and M12 is denoted as gmit since they are also matched in the circuit design. Therefore,

the OTA input-referred thermal noise should be:

16isT gm3 l >lm 119
U i,OTA =[ (1 +2 + )]f 3-9
8*/ I ml Yml


































Figure 3-15. Schematic of the OTA


If g,lz is increased or g,ll1 and g,,23 are decreased, the input-referred thermal noise can

he decreased. The most straightforward approach is to increase (W/L)1,2 or to decrease

(W/L):38,11,12~. However, noticing that M111 is associated with the first nondominant

pole and 313, 314 are associated with the second nondominant poles, reducing the sizes

of these transistors will reduce the transconductance of these transistors and push these

nondominant poles to zero, possibly degrading the stability. Consequently, there is a

tradeoff between the input-referred thermal noise and stability.

The flicker noise is another 1! in r~ noise source in low-frequency C110OS circuits. It

can he decreased by increasing the areas of the C110OS transistors. However, the areas are

also related to the nondominant poles as discussed above, which puts a restriction on the

flicker noise performance.

Power consumption is another hig concern in low-power circuit design. The static

power consumption of this OTA is directly determined by the bias current, which is set to

8 p-A in the simulation and chip measurement. Reducing this current can reduce the power










consumption. On the other hand, reducing the bias current can also increase the output

resistance of the OTA because ro oc 1/I. Fig. :3-13 shows that higher SER can he achieved

when the OTA's output resistance increases.

However, there are also some drawbacks on reducing the bias current or power

consumption. The most important drawback is related to the transconductance of

the OTA. Eq. :335 indicates that the reconstruction SER is directly proportional to

G2>. Therefore, higher a G,, can generate higher SER from the reconstructed signal.

Increasing the bias current can directly increase the transconductance. Actually, when

G,, increases, more output spikes can he generated, which again increases the dynamic

power consumption. The above discussion indicates that we have to trade off the power

consumption with the SER.

3.5 Chip Layout

The layout of this chip with pads is shown in Fig. :3-16. There are three components:

the gm amplifier, the comparators and the digital control block. They are powered by

individual power supply to reduce the cross coupling, and each power supply has its own

bypass capacitor. Guard rings are also used to eliminate the kick back noise from the

digital circuit. These three parts are separated as far as possible. The total layout area

including the pads is 2.25mm2

3.6 Cadence Simulation Results

The digital control circuits of the single-channel hiphasic IF neuron were designed

by C'I. n! [22]. This digital block is concatenated to the gm amplifier, thus finishing the

single-channel circuit design with the 0.6 pm C \!OS process. The Cadence simulation

is run for the single channel. The input signal is a sine wave with amplitude of 20mV.

The frequency is swept from 1K(Hz to 10K(Hz and the input signal lasts for 2ms. The bias

current of the gm block is set to 8uA and the integration capacitor is set to 20pF. The

spike train is then directly read out and the signal is reconstructed in 1\atlah using the

closed-form algorithm. The 4-parameter sine wave fittingf method is used to estimate the







































Figure 3-16. Layout of the single-channel biphasic IF neuron chip

input signal from the reconstructed single tone signal by finding the best-fitting sine wave

[23]:

x(t) = A cos(cot + 8) + C (3-40)

The difference between the reconstructed signal and the fitted signal are defined as the

error. The SER (signal to error ratio) is defined as the power ratio of the fitted signal to

the error. The SER vs. input signal frequency is shown in Fig. 3-17. The reconstructed

SER values range from 51dB to 57.5dB, which means more than 8 ENOB (effective

number of bits). The difference between the SER in Fig. 3-17 and the Matlab simulated

SER is due to the nonlinearity of the gm block and the signal dependence of the analog

comparator. The finite number of pulses and the computational precision of MATLAB














57 -


56C -J


55 -


54


53


52


51


50
103 104
Frequency (Hz)


Figure 3-17. Reconstructed SER vs. input signal frequency


also introduce some error. There are some tradeoffs between the reconstruction accuracy

and the power consumption of the system, which will be discussed in the following

sections.

3.7 Measurement Results

A single channel chip containing a biphasic integrate-and-fire (IF) neuron has been

fabricated using the AMI 0.6um process with a DIP40 package. The gm block is described

in the precious section of this chapter, and the biphasic pulse generator has been described

by C'I. i.[1,]. In the gm block, the 20pF capacitor was implemented with a poly capacitor

and the bias current of the gm block is 8uA. With the power supply of +2.5V, the static

power consumption is around 80uW. The DC voltage across the integrator capacitor was

biased at OV with a voltage follower. The chip has been successfully tested.













20m~p-p inp








3.755 40mTp-p input

Th is eaueet wr o snl oe nu* Aiet322Asga
generator ~ ~ ~ ~ ~ *a sdi h etn.Tesnl tn rqec a wp rm5
to70Hzadte nu mpiuear 0V ekt pa n50m ek opa



respecive40 -h hehl ftebpai Fnurnws~.V h uptfo h










Fgre 3-18. SER vs. singe le one-fr loih.Frec frequency, rudsxpro


Thnl ee freostmaurtementse wre fosr a inged toe input. A inAgilen 33220Aro ths ignal

gener atorn w has sdi the testedSRing T eycoet he singetnefe ueny aso rswepts fromh 50Hz

to 00Hzan the peiou nptampitud ascret 20m phea tog prqeaky aeind 40mVpekt peak pa











90t 4
x ** e20mVp-p input
40mVp-p input
80t *



S70



60


50-



40~ -


30
102 103 104
Frequency (Hz)


Figure :3-19. Spike rate vs. sine wave frequency


input can generate as high as 55dB reconstructed signal (which means around 9 ENOB),

and the 20mV peak to peak input can also has 50dB SER, which is very close to the

simulated 51dB. During the low frequency region, the SER is a little bit lower. There is

no direct relationship between the SER and the input signal amplitude. The statistics of

the spike rate are also shown in Fig. :3-19. It is very clear that the spike rate reduces with

increasing frequency. This reduction trend is not apparent in the low frequency region

but it is more obvious in the high frequency region. When the input signal amplitude is

doubled, the spike rate is almost doubled as expected.

Fig. :3-20 shows an example of the hiphasic pulse train output and the offline recon-

structed signal. The input signal is a 1K(Hz sine wave with 20mV peak-to-peak amplitude.

The red curve Fig. :3-20 (b) is the reconstructed sine wave from the pulse train showed in

Fig. :3-20 (a) and the blue curve is the 4-parameter fitting sine wave. Fig. :3-20 (c) is the

error between the reconstructed signal and the fitting signal. This reconstructed signal has

45dB SER.













a,
o
a
n
E


0 0.5 1 1 .5 2 2.5 3 3.5 4 4.5 5
(b)


(a)


CO
SReconstructed
E 40-
a,- Fitted
S20
S0-
Q 20
0 0.5 1 1 .5 2 2.5 3 3.5 4 4.5 5
(c)
0.1


0

Q -0.1 ;
0 0.5 1 1 .5 2 2.5 3 3.5 4 4.5 5
Time (ms)

Figure 3-20. 1\easured reconstruction time domain result example: (a) Pulse output; (b)
Reconstructed single tone signal (red) and the 4-parameter fitted single tone
signal (blue); (c) Error.


One apparent result is that when the hiphasic comparator threshold is reduced, the

output spike rate will be increased. The increasing spike rate requires more communi-

cation bandwidth. On the other hand, more output spikes also consume more dynamic

power. Therefore, it is beneficial to increase the comparator threshold to reduce the spike

rate.

In unidirectional IF neuron system, the AC signal is shifted by a DC component and

the integrated absolute current is a constant. The resulting spike rate is independent of

the input signal frequency. However, in the hiphasic IF neuron system, when the input

signal changes from positive value to the negative value (or vice verse), the integrated

charge after the last spike gets canceled by the opposite-polar charge, therefore, the total

spike rate is dependent on the input signal frequency. when the input signal frequency

increases, the charge gets canceled more often, and the resulting spike rate reduces with

the increasing frequency. This analysis actually verifies the statistics from Fig. 3-19.











o Measurement
i Equation


120 -\

~100~ -

80-

60-

40


20.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Threshold (V)

Figure 3-21. Threshold vs. spike rate


When the input signal frequency is low and there are many output spikes generated

during each half period, the canceled charge can be neglected, the spike rate can be viewed

as frequency independent and it can be written as

20, G,
Spikerate = (3-41)


where 1%, means the input signal amplitude. To verify the relationship between spike rate

and the comparator threshold, another test was conducted. In this '. -1y! a 800Hz 40mV

peak-to-peak single tone was fixed as the input while the biphasic comparator threshold

was varied from +0.2V to +1.0V. The generated spike train was then collected with

the logic analyzer and the input signal was reconstructed with Matlab offline code. The

measurement result and the result from Eq. 3-41 with Gm = 60pS are shown in Fig. 3-21.

From this figure, the output spike rate decreases from 160K~pulses/s (with the threshold

of +0.2V) to less than 40K~pulses/s (with the threshold of +1.0V). This trend is similar to

the equation.



















50


49 -9


48


47


40
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Threshold (V)

Figure :3-22. Threshold vs. SER


We are also interested in how the SER will change with the reduced spike rate.

The measurement result is shown in Fig. :3-22. The SER is reduced front 52dB to 47dB

with the increasing threshold and reducing spike rate, which is somewhat expected.

Fortunately, the SER does not vary very much. This testing provides us the relationship

between the spike rate (or coninunication channel bandwidth and power consumption)

and the reconstruction SER. It is apparent that the spike rate can he greatly reduced

without sacrificing the accuracy very much. Of course a limit will be reached where the

distance between spikes violates the sampling assumption.

3.7.2 Neural-Simulator Input

The specific application of this hiphasic IF encoding is for neural signals. Neural

signals are composed of action potentials (the signal) and noise. Typically, the action

potential is about 50-500 pV in amplitude [:3] and lasts for 1-1.5 me [4]. With the hiphasic

IF encoding, the output spike rate is supposed to be high in the action potential region.

On the other hand, if there is just noise during that period, the output spike rate is










ideally low to save the coninunication channel bandwidth. Since the action potential is

of interest, it is desired to reserve high coninunication bandwidth for them. It is assumed

that this hiphasic IF encoding method can make full use of the coninunication channel

bandwidth.

Some measurements were conducted to evaluate the performance of this application.

The Bionic 128 C'll Iall., I Neural Signal Simulator and an Agilent 169:3A logic analyzer were

the two primary instruments in this testing setup. As discussed in the previous chapter,

the Neural Signal Simulator can provide a prerecorded neural signal. The action potential

output front this Neural Signal Simulator is around 200 pV peak-to-peak. This signal is

too tiny to generate a spike output. Based on the single tone testing, we think that the

reasonable input signal range is around 20m V peak-to-peak. The preaniplifier design

by ('I!. in [11] was used as the first stage to boost the neural signal and to convert the

differential neural signal to a single-ended signal. Following the output of the preaniplifier

were the gm block and the hiphasic IF block. An Agilent 169:3A logic analyzer was used

to record the hiphasic spike train. The collected spike train is then fed into 1\atlah offline

code. During the noise region, there were very few spike outputs and the time delay

between consecutive spikes can he greater than the Nyquist period of the input signal. As

a result, the convergent condition for close-fornt algorithm can not he met and we have to

use the iteration algorithm for reconstruction [5]. After careful comparison, it was found

that the reconstruction signal after the 5th iteration provides the best fidelity.

Fig. :3-2:3 shows an example of the hiphasic pulse train output and the offline recon-

structed neural signal. In this example, the hiphasic coniparator threshold was set to

+0.4V. The shown signal lasts for :30nis. It is apparent that the measurement results ver-

ify the expectation. During the action potential region, there are high spike rate output;

on the other hand, when there is no interesting neural signal, the generated spike rate is

very sparse as expected. Since the noise region is not interesting to us, low signal fidelity

can he tolerated but the action potential regions are kept with higher accuracy. Statistical














0.5-

S0 -

-0.5

-1
0 0.005 0.01 0.015 0.02 0.025 0.03


1x 10-5 (b)


0.5-




S-0.5-

-1
0 0.005 0.01 0.015 0.02 0.025 0.03
Time (s)

Figure :3-2:3. 1\easured reconstruction time domain result example: (a) Pulse output; (b)
Reconstructed neural signal.


measures have been used to compare the spike rate during different signal regions and

the measurement results are listed in Table :3-1. In this table, the hiphasic comparator

threshold has been swept from +0.2V to +0.9V, and the spike rate has been calculated

during three different signal regions. One is so-called spike burst region, which means

that is a large number of action potentials generated in a sequence and each spike lasts

for 5m~s. The second region is a noise region, where no action potentials are generated.

The last action potential region means the time region concentrating on each spike peak

which is normally 1m~s. By comparing the spike rate difference among the three signal

regions, it is apparent that the communication bandwidth is saved. For example, when the

threshold is set to +0.4V, the spike rate during the action potential is around 28K~pulses/s,

which is very high. However, if we average the spike rate during the total 5m~s, the spike

rate is dropped to 6.9K~pulses/s. Within the same setup, the output spike rate is just

1.9K~pulses/s when there is no action potential.









Table :3-1. Spike-rate comparison

Threshold Spike burst Noise region Action potential
200mV 15.:3K/s 6.5K(/s 56.:3K/s
:300mV 10K(/s 2.:3K/s :37.8K(/s
400mV 6.9K(/s 1.9K(/s 28K(/s
500mV 6.:3K/s 1.8K(/s 22.5K(/s
600mV 6.27K(/s 1.4K(/s 17.8K(/s
700mV 4.5K(/s 1.:3K/s 12K(/s
800mV 4.5K(/s 0.6K(/s 11.8K(/s
900mV 4.2K(/s 0.5K(/s 10K(/s


Similar to the previous subsection, we still need to evaluate the performance of

this system. The difficulty in this case is that we do not have the original or fitting

signal, therefore the SER can not he used in this occasion. Even if the original signal

can he obtained, it is unfair to calculate the SER for all the signal region, because the

useful signal is just the action potential. This hiphasic pulse encoding is intended to

achieve lower signal accuracy in noise region and to achieve higher signal fidelity in action

potential region.

Several methods have been proposed to compare the performance. The first method

is to calculate the cross-correlation coefficient between the reconstructed signal and the

neural signal. In this testing setup, the output front the neural simulator is predefined and

can he obtained by other uniformed sampling instrument. The Tucker-Davis Technologies

(TDT) R A8GA is used to record the neural simulator output with the sampling rate

of 24414.1Hz. Fig. :3-24 (a) shows one section of the TDT recorded neural signal. The

other signals shown in this figure are the reconstructed neural signal with threshold of

+0.:3v, +0.5V and +0.9V respectively. The cross-correlation coefficient between the TDT

recorded neural signal and the reconstructed signal is listed in Table :3-2.

If the cross-correlation between two signals is one, they can he exactly the same or

they can differ in amplitude. To exclude the amplitude confusion, the second method is

used to calculate the mean absolute error ( \! AE) between the reconstructed signal and the












1x10 5


(a) 1x105


^0.5, 11 111 ll- 0.5





S0 0.1 0.2 0.3 0.4 0.5r~uwr i 0 0. 02 03 04 05

S111 x 10 (c) 1111 x1 0111111111 (d)1 1 I




0. -I I- 0.5


-1 -1
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Time (s) Time (s)


sinl;() eontuce signa (Vh=03V) (c ecntuce sga





1i 1

where VTT0 en h D eore ape n re.)iniae h eosrce






Li 1

W e calcltn thes errrs the pea to1 pea ampitde of1 the TD reore signal 11 1I 1111

adtercnsrce signalsII hav been first111 noralze to one Bot of th A n





RMSE results (Mexpressd icn perucin tageae listedin reuTabamle : 3-2.Treore









Table :3-2. Statistics results on the reconstructed signals

Threshold cross-correlation coefficient MAE(%o) RMSE(%o)
200mV 0.84 :3.3 4.7
:300mV 0.82 :3.3 5.0
400mV 0.8:3 :3.4 4.9
500mV 0.82 :3.6 5.0
600mV 0.80 :3.8 5.4
700mV 0.77 :3.6; 5.2
800mV 0.75 4.5 6;.0
900mV 0.75 4.6 6;.0


Actually, the noise regions in the TDT recorded signal and the reconstructed signals

are not important because they do not carry any useful information. Since there are

very few spike outputs generated in those regions, the reconstructed signals in those

regions should be poor in terms of signal fidelity. To better evaluate the signal fidelity

in the useful signal regions (action potentials), we can intentionally zero all the noise

regions and repeat the cross-correlation coefficients, MAE and R MSE calculation (in these

calculations, the signal length has been reduced correspondingly). The results front the

zeroed signals are listed in Table :3-:3. Comparing the results in the above two tables, it is

apparent that the RMSE and MAE front the zeroed signals are ahr-l- 0 smaller than those

corresponding unniodified signals. On the other hand, the cross-correlation coefficients

front the zeroed signals are greater than those from unniodified signals. This observation

shows that the signal fidelity in the action potential regions is better than those in the

noise region as expected.

Another method to evaluate the reconstructed neural signal is to do some spike

sorting on the TDT recorded signal and the reconstructed signal. To some researchers,

it is the spike timing and the spike shape that are most important since the spike shape

indicates from which neuron this action potential is transmitted. In fact, spike sorting

has been used to achieve data reduction. In our evaluation process, if the spike sorting

results are very close (which means that if the action potential in the TDT recorded

signal is classified to be in the same class in the reconstructed signal case), it can he safely










Table 3-3. Statistics results on the zeroed reconstructed signals

Threshold cross-correlation coefficient MAE(%o) RMSE(%o)
200mV 0.88 1.7 4.0
300mV 0.86 1.8 4.3
400mV 0.87 1.7 4.1
500mV 0.87 1.7 4.1
600mV 0.85 1.9 4.5
700mV 0.84 1.9 4.4
800mV 0.80 2.1 4.8
900mV 0.82 2.0 4.6


said that the key features of the action potential are kept. The output from the neural

simulator is predefined, and there are 3 classes of action potential in each channel. The

testing setup uses two channels for differential input and therefore there are total 6 classes

of action potentials in the TDT recorded signal and the reconstructed signal. Each class

of action potential is repeated after 30ms in the spike burst region. The achieved signal is

the 6 classes of spikes repeating themselves after 30ms, as can be seen in Fig. 3-24.



O 00001




0o 00001




-000001~
0 00001



0002 004 006 008 010 012 014 016 018 020 022 024 026 028 030 032 034 036 038 040 042 044 046 048


Figure 3-25. Spike sorting result based on reconstructed neural signal (Each panel of the
first 6 panel indicates all the action potentials in that panel belong to the
same class, the last panel is the reconstructed signal.)









Table :3-4. Reconstructed neural signal spike sorting statistics (missing action potentials
/total action potentials)

signal class 1 class 2 class 3 class 4 class 5 class 6
TDT recorded 0/17 0/16 0/16 0/16 0/16 0/16
200mV 0/17 0/16 0/16 0/16 0/16 0/16
:300mV 0/17 0/16 0/16 0/16 0/16 0/16
400mV 0/17 0/16 0/16 0/16 0/16 0/16
500mV 0/17 0/16 0/16 0/16 0/16 0/16
600mV 0/17 0/16 0/16 0/16 1/16 0/16
700mV 0/17 0/16 0/16 0/16 2/16 0/16
800mV 0/17 0/16 0/16 0/16 7/16 1/16
900mV 0/17 2/16 0/16 0/16 11/16 4/16


A popular algorithm called Spike2 is used to do the spike sorting. Spike2 is a powerful

data acquisition system which can also do data capture, experiment control, recording and

analysis. Spike2 is also a popular neural software for spike detection and spike sorting.

Spike2 identifies and sorts single and niulti-unit activity both on-line and off-line. It can

mark spikes using simple threshold crossings. For niulti-unit activity, Spike2 contains tools

for sorting spikes based on the spike waveform shape. All events crossing a threshold are

captured and a combination of template matching and cluster cutting hased on Principal

Component Analysis (PCA) is then used to sort spikes into different classes.

Fig. :3-25 shows an example of spike sorting results front Spike2. The neural signal is
reconstructed front the hiphasic pulse output with threshold of +0.4V. Each row of the

first six rows indicates all the action potentials belonging to the same template. It is clear

that there are total of six classes of action potentials found in the reconstructed neural

signal. In fact, all the action potentials are correctly sorted in this example. With the

extracted six templates, all the other reconstructed neural signals and the TDT recorded

signals are sorted by Spike2. The results are listed in Table :3-4. We can see that for

a threshold less than +0.7V, the Spike2 sorting results of the reconstructed signal are

very close to that of TDT recorded signal. This comparison verifies that this hiphasic IF

encoding works well for neural signal.










x 10-6








5-

4- :

3-






5 10 15 20 25 30 35 40
Sample Number

Figure 3-26. Comparison between the correctly identified action potential (blue solid line)
and the missing action potentials (red dotted lines)


One may wonder what is the reason for the misclassified action potentials. We made

some comparisons here. Since most of the missing action potentials are from class 5, some

missing action potentials from this class are plotted to compare to the correctly classified

action potential. This plot is shown in Fig. 3-26. It is apparent that the amplitude is

responsible for the miss because the correctly identified action potential has a large

amplitude in both directions while the missing actions potentials have much less amplitude

in the negative direction.

Fig. 3-27 shows the six time-domain templates used in the Spike2 sorting. On each

template plot, the number on the top left marks the class number and these template

numbers are ordered to match with those in Fig. 3-25. The corresponding principal

component analysis on the six spike templates is shown in Fig. 3-28.

3.8 Practical issues

The previous Matlab simulation and circuit analysis are based on ideal assumptions.

After circuit measurements, we realized there is a gap between the measurement results






































Figure 3-27. Six action potential classes (The number on the left top marks the class
number)


and the simulation results. For example, the Cadence simulation shows that the recon-

structed SER is ah-li-w greater than 50dB, while the chip measurement with the same

input signal and same setup shows an SER at most 50dB. Some practical issues contribute

to this difference. We will discuss these issues in this section.

3.8.1 Signal Dependent Reference of the Comparator

The biphasic IF encoding operation is realized using two identical comparators. If

Vth for example is set as one of the thresholds, when the voltage across the integration

capacitor crosses the threshold, the output of the comparator starts to change. When

the comparator output voltage reaches a high voltage, the logic analyzer reads out the

state and we assume that the recorded timing is the time when the integration voltaget

reaches the threshold. However, this recording timing is somewhat later than the exact











File Edit View Cluster

























PCA of 97 events with 28 points. press F1 for help


Figure 3-28. Principal component analysis corresponding to the six templates


time. If the delay between the recording timing and the exact time is fixed, this delay will

not affect the reconstruction accuracy and it shows itself as a simple delay between the

reconstructed signal and the original signal. Or we can see it from another point, at the

recorded timing, the voltage across over the integration capacitor is already greater than

the threshold used in the reconstruction. If the difference between the accurate threshold

and the threshold used in reconstruction is fixed, this threshold difference will not affect

the reconstruction accuracy and it shows itself as an amplitude difference between the

reconstructed signal and the original signal. On the other hand, if the delay is signal

dependent, or the threshold difference is signal dependent, some error will be introduced in

reconstruction. Unfortunately, detailed analysis by Wei [15] proved that this delay or this

threshold difference is signal dependent.










Realizing this error source, it is of interest to reduce this signal dependent error.

One apparent solution is to make the comparator's transition fast. Following Wei's [15]

analysis, the relationship between the bias current of the comparator and reconstructed

SER can be derived as

SER = ~.(3-44)
kQ thCo,comp favy
where

k = 1+ 4Vl ) 4 ( ,-1 (3-45)
3(Vmx )(Vax +1)2 2.5(Vmax 1)(Vmax + 1)15'
In the above equations, Vmax is the amplitude of gm input signal, lhas is the bias current

of the comparator differential pair, Co,comp is the output capacitance of the comparator,

P = pCom4 is also determined byi the comparator differential pair and ~f,,, denotes the

output pulse rate. Based on these equations, it can be found that increasing the bias

current (or the comparator power consumption) can increase reconstruction SER. This

tradeoff between the SER and power consumption is very useful because we can estimate

the minimum necessary power consumption for some specific SER or maximum signal

accuracy under some power budget requirement.

A Cadence simulation was run to verify this relationship, and the simulation result

is shown in Fig. 3-29. When the bias current increases, the SER also increases. When the

bias current is too large, the SER saturates. The reason for the SER dropping at high bias

current is not clear.

3.8.2 "Pseudo-Resistor" Introduced Direct Current Voltage Offset

An important device used in the gm block (see Fig. 3-2) is the p--' IIII1 -resistor".

In the previous Matlab simulation and circuit analysis, it is assumed that this 1-

resistor" helps form an ideal voltage follower for DC operation and a open-loop amplifier

for AC operation. During the chip measurement, we found that this resistor introduces a

large DC offset when it worked in the DC voltage follower configuration. Considering this

DC offset Vost in addition to the OTA DC offset VOS2, the equivalent circuit of Fig. 3-2

can be plotted in Fig. 3-30. If Vey is set to ground, in the ideal case (no resistor DC offset













64t -

62-


60 -

58-

56t -

54-

52-

50
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Ibias (uA)

Figure 3-29. Comparator bias current vs. SER


or no OTA DC offset), the DC voltage in the output will also be ground. However, when

there is a DC offset, the DC voltage over the integration capacitor will be:

A(VOS2 Vost)
Voutos =(3-46)
1+A

where A is the DC voltage gain of the OTA, and its value is greater than 60dB (refer to

Fig. 3-4). Equation 3-46 can be further simplified as Voutos = VOS2 Vost without

introducing much error. The DC offset of differential input pair in C \!OS process is

normally less than 5mV (refer to Table 2-1) while the pI-' III )-resistor" introduced offset

Vost is much larger than 5mV (around 100mV). Therefore, the 1!! r ~ part of the output

DC offset is contributed by Vost.

During the chip measurement, it was expected to set the DC voltage of Vout to be

ground (because the lower plate of capacitor C2 is also connected to ground). In this case,

after a spike is generated, the reset clock can reset Vout to ground and the new integration

starts from ground. Unfortunately, it is very difficult to set the DC voltage of Vout to










R Vos1


Vin C1

Vout
OTAO



Vos2 1'


Vref

Figure 3-30. Equivalent circuit of gm block with DC offset


ground in practical operation. We can analyze how Vost can affect the reconstructed

signal SER.

During the integration operation, when a pulse is generated, the voltage across the

integration capacitor is reset to ground. After each reset, the following integration is a

superposition of two transitions. One is the normal integration as discussed in Eq. 3-25.

Another transition is the response of the voltage follower when the output voltage is forced

to some unstable value. This DC response can be described as


Vout = Voutos(1 e-t/'). (3-47)


where -r is the time constant of the voltage follower. The total integration process can be

described as

Vm = Voutos(1 e"-s/) + i T(t)hi(tie )dlt. (3-48)
f ib
where I%,(t) is the voltage input and the h(t) is the impulse response from Eq. 3-24.

Replacing the simplified Voutos, Eq. 3-48 can be further simplified as


Vth = Vos1(1 e-tie/r) + ,thte-t.(3-49)










Rearrangfingf this equation, we can get:


Vth Vos1(1 e-tie/') = ,thte-t.(3-50)


First, we can estimate -r based on Fig. 3-4. When the OTA is configured as a voltage

follower, the -3dB frequency is around 2 x 10sHz, which correspond to -r lu. From

Fig. 3-19 and Table 3-1, we realize that the spike rate is ahr-l- .- less than 100K(/s, which

means that the integration time for each spike is longer than 10us. For t > 10us,

1 e-tie/7 m 1. This information can help to further simplify the above equation to:


Vth Vost ,thti t (3-51)


From the above equation, it is clear that the pI-' III' -resistor" introduced DC offset

adds some constant to the threshold. In unidirectional IF encoding, this will just add an

amnplitude c~oeffic~ien t h-OS belitween the r~econstructled signal and the original signal.

However, in the biphasic IF encoding system, it can introduce a nonlinear error. This

can be easily understood, because when this offset make one directional threshold bigger,

it also make another threshold absolute value less. The result will be the spikes in one

direction will be ahr-l- .- be more than those in another direction. In some extreme cases

when the offset item Vost is too large, there will be only one directional spike can be

generated. In fact, both of the above cases have been observed in chip measurements.

If Vost can be accurately estimated, we can calculate the exact integration value

for two different spikes, and the DC offset introduced error can be removed from the

reconstructed signal. This estimation can be done with some calibration processes prior to

each measurement. For example, a sine wave can be set as input and the generated spikes

can be reconstructed by sweeping the Vost. The optimal Vost should correspond to the

highest SER. Fig. 3-31 gives an example how to estimate the DC offset. In this Matlab

simulation, a 1000Hz single tone with amplitude of 0.03V was the input and the real DC

offset was set to 5mV. The threshold was +0.4V. During the reconstruction, the estimated

















70-





60-





50
0 1 2 3 4 5 6 7 8 9 10
Estimated Vofe (mV)


Figure 3-31. SER vs. estimated DC offset


offset was swept from 0 to 10mV, and the reconstructed SER was plotted in this figure.

It is clear that only when the estimated offset is equal to the actual offset, the SER is

reaching the maximum. When the estimated offset is greater or less than the actual offset,

the SER drops.

Even if it is possible that the original signal can be perfectly reconstructed from the

spike train given the DC offset voltage, in practice this offset value can not be accurately

evaluated. For example, this DC offset is not a constant through all the time period,

instead, it is a signal dependent offset [24]. Therefore it will be insightful to ignore the

offset introduced by the "resistor" during reconstruction and investigate the resulted

performance limitation.

Following the previous analysis in this chapter (from Eq. 3-30 to Eq. 3-35), we can

derive the relationship between the SER and the DC offset. Similar to the notations used

in the above equations, we still assume 8i as the accurate integration charge during each

spike period, and assume 8 as the ideal integration when there are no leakage or the DC

offset. We further assume 8 as the corresponding part when there is offset introduced error











but no leakage introduced error. Therefore, the charge difference of i-th integration period

between the accurate integration and the ideal integration is:


|Osi- e| = | (e -e)+ (e )|

=|(CL~os) + (8 8)|

=CLV, + Gm1~,(aT~ b2T/) + Gm1naT/
2 6; 6;


used to represent anld / for simplification as before.


(3-52)


where a and b are


Simulation
Equation|


75

70-

65-

r60 -



50-

45-

40-


h


25 30


15
Offset (V


Figure 3-32. SER vs. DC offset








The noise power is:

Raoise, o f fset+leaka~ge


-E[(l~() lh ~(t)(O ))2





-E[( (h (t))2)]E[ (H, -) + (R )]2

-E[( (h (t))2)]E [[Q T~+ (O )1]2

-E[((h (t))2) ((L us 2 + E[(R 1)2

r(-E[(( ) s2+GE(,I)


SGE[(T~,~" (h ())2L >s + G [( )2


+G E[(%, ( )3 2 + G E[(IR, ( )3 21
(3-53)


where again the approximation is made due to CLt Eg GmK~,T;. Since the two noise
sources (DC offset introduced noise and leakage introduced noise) are not related to each
other, the expectation of the addition is equal to the addition of the expectation. The
power of the signal is rewritten for the reader's convenience:


= [(lKn(t))2]

-E[(~ k (t)04)2]

Ei- [(C h (t))2]E[(lMa)2]


Psiagnal


(354)










The equation of SER is very complicated, however, we can start with -:

1 Pnoise,o ffset+leakage
SE Roff set+leakage Psignal
Vo V 1 Of Vt ( 1
S( )2+ E ,, ,[ ]+ E I" [ ]
Vth 16G ri 36GER2 12 4
(3-55)

w.here E[(E hl())2] E[(h ())2] 1S used for the first approximation. In addition, the


result from Eq. 3-35 has been directly used for simplification. To verify the relationship

between SER and DC offset, the results from a Matlab simulation and Eq. 3-55 are given

in Fig. 3-32. The parameters of the biphasic IF neuron are: C1 = 20pF, Vth = +0.4V,

Gm = 30an2-1, ro = 2.6 x 1090, R = 1010S, and the input is a 1000Hz single tone with

amplitude of 30mV. The Matlab simulation uses a step size of Ins and the signal length is

6ms. Both of the equations and Matlab simulation predict that there is a significant drop

in SER as the offset increases to even a few mV but this also reflects the fact that the

input signal amplitude is only 20mV.


~tSimulation
60~ 0 Equationa

58t a /

56 -


54 -


0.2 0.3 0.4 0.5 0.6
Vth (V)

Figure 3-33. SER vs. comparator threshold


0.7 0.8 0.9 1











The results about how SER changes with increasing threshold from Eq. :355 and

1\atlah simulation are given in Fig. :3-:33. The simulation parameters are similar to what

are used in Fig. :3-:32 except that the DC offset is set to 5mV. Both of the two curves

predict that when the threshold increases, the SER also increases.

50


57-


56-


55-
LIJ

54-


53-


2000 3000 4000 5000 6000 7000 8000
Frequency (Hz)


9000 10000


Figure :3-:34. SER vs. input single tone frequency


Another simulation is done to display the relationship between SER and input single

tone frequency with 5mV DC offset. Fig. :3-:34 tells us that the SER is independent of the

single tone frequency. This simulation result matches with the real testing results as shown

in Fig. :3-18.

Eq. :355 shows that SER is dependent on many factors, for example, the pI-' II a l-

resistor" introduced DC offset and some other circuit factors. Since the relationship

between SER and the circuit factors has been discussed in the precious subsections, it may

be insightful if we just focus on the relationship between SER and the DC offset. We can










simplify Eq. 3-53 as


E [(K, (t) ll, (t)) 2




G2 [C(h (h(t))2)]E[(04 )2]
C2


noise,o offset


_356)


here the noise introduced by the leakage is ignored. The power of the signal is still the

same as Eq. 3-54. The resulting SER can be derived as follows:


Psignal
Pooise,offset

E[V,2,

Vos


SERoffset


(357)


While this approximation can not provide accurate values of SER, it clearly shows how

the DC offset affects the reconstructed SER. From this equation, it is clear that when the

offset is reduced or the threshold is increased, the SER can be increased.









CHAPTER 4
EIGHT-CHANNEL BIPHASIC INTEGRATE-AND-FIRE WITH ADDRESS EVENT
REPRESENTATION READOUT

4.1 Introduction

The biphasic spike representation circuit has been described in the previous chapter

as a single-channel system. Each system has two pulse output channels: one for positive

spikes and one for negative spikes. When several such systems are put in a single chip

to simultaneously record the multichannel neural signal activity, the required number of

dedicated output wires increases. In order to reduce the connection wires and make use

of the communication channel, the Address Event Representation (AER) protocol is used

to multiplex several pulse output channels. In this multiplexing scheme, an .l-i-achronous

digital arbiter monitors the output of all the integfrate-and-fire neurons. In the proposed

circuits, a 4-bit address will encode the 8 channel neurons since each channel has both of

positive and negative spikes. Once the 4-bit address is generated by the AER protocol,

it can be further modulated onto a single channel for wireless transmission. There are

many possible modulation schemes such as frequency modulation or width modulation.

Frequency modulation requires an oscillator, which increases the circuit complexity. With

width modulation, the address can be encoded with the appropriate pulse width or the

time between two pulses. This mechanism ensures that extremely simple and low power

hardware be used.

A variation of the AER protocol has been successfully emploi-edI in the time-to-first-

pulse imager chip designed within the CNEL lab [25, 26, 27]. In the time-to-first-pulse

imagfer chip, an .I-i-nchronous digital arbiter is used to scan off the address buses of

all the pixels. Once a pixel generates a spike, a request signal is sent to the arbiter.

Upon acknowledgement, the address or the corresponding pixel can be transmitted. The

drawback of this AER protocol arises when two or more pulses fire at nearly the same

time. In this case, the AER structure will just transmit one of the pulses while the other



















Vth+ Reset
lin
DigitalRosl
Reset Block
M1 C

Vth-
Vmid _
Row request~


1


Latches


Throughput control


pulse is buffered. By doing this, this delay will change the firing times of the pulses. With

fast digital electronics, this latency can be made small enough for most applications.


8 channel
4 x4 neuron array


aO


.c c
o
cc <
0




Latch Control


I/O


Column Arbiter


Column Address Encoder

1/O


Figure 4-1i. Blo ck di agram of the 8-channel address-event-represent ation (AER) recording
system


The block diagram of an 8-channel recording system is shown in Fig. 4-1. 8 channels

of the biphasic spike generator are arranged as a 4 x 4 neuron array. To facilitate the

layout, both positive and negative spike outputs of each neuron are arranged in the

same row but in different column. One should bear in mind that this arrangement is not

optimal in terms of transmission speed, because a maximum of 2 neurons in each row can

generate the spikes at the same time. On the other hand, if all positive spikes are arranged

in two rows while all negative spikes are put in another two rows, and when all neurons in

the same row generate the spikes at the same time, then just one row address needs to be

transmitted. This system operates as follows:










1. Integrate and row request: After reset, each neuron begins to integrate the current.
Once the voltage over the capacitor (C) is across a threshold, a corresponding
positive or negative spike is generated. The Row_request~ line is pulled down to send
a row request.

2. Row select and column request: The row arbiter selects a row from the spiking rows
by making corresponding Row_sel high and the selected row address is stored and
encoded by the row address encoder. After the Row_sel is received, all the spiking
neurons in that row can send out column requests by pulling down Col_request~.
In this 8-channel system, 2 columns at maximum can send this request signal
simulantaneously.

3. Column select and reset: The column latch records all column requests of the
currently firing neruons in the selected row. Once this is done, two steps are taken
at the same time: 1. the column arbiter begins to encode the column address; 2.
the latched neurons in that row are all reset and they can begin to integrate again;
the reseted neurons will therefore withdraw the corresponding row request signal.
Subsequently, the other valid Row_request~ can be processed by the row arbiter,
while the row interface citcuit still blocks a new Row_sel from being issued until
all latched neurons have been processed by the column arbiter and column address
encoder.

In the following section, the clocked AER circuit scheme will be described in detail.

Accurate spike timing is crucial for signal reconstruction. The primary drawback of the

AER protocol is the potential timing jitter or even spike loss, which adds distortion to the

reconstructed signal. These imperfections will also be addressed in this chapter.

4.2 Address Event Representation Structure

AER is an .l-inchronous readout scheme implemented with digital circuits. Unlike

other digital circuits, the .I-i-itchronous AER structure is difficult to simulate with

standard Verilog or VHDL languages. Instead, CADENCE SpectreS is used as the

simulator in this design. The digital .I-i-itchronous readout circuit mainly consists of a row

arbiter tree, a column arbiter tree, a column latch, a column latch control, a row interface

and a throughput control block. The throughput block has already been successfully

emploi-e d in the time-to-first-pulse imager chip within the CNEL lab [25, 26, 27].

Most of the detailed circuits of the AER protocol were originally designed by Boahen

[28]. For the reader's convenience, they are briefly described in this section.










4.2.1 Arbiter

The arbiter cell shown in Fig. 4-2 is the basic unit for the row arbiter tree and column

arbiter tree. This arbiter circuit was originally used by Boahen [28]. An arbiter tree is

built from two-input arbiter cells using a binary tree architecture.

< ~Req~out
Sel out 1~


Req~in_1 NAND Req~out








Reqin_2 NAND Req~out-

Sel out 2~


Figure 4-2. Schematic of the arbiter cell


Each arbiter cell has two lower ports and one upper port. Each lower port has one

request input (Req_in) and select output (Sel_out~). The upper port has one request

output (Req_out) and one select input (Sel_in~). Whenever one or two lower active-high

ports, Req_in_1 and Req_in_2, makes a request, the arbiter cell relan~ the request signal

to the upper level by making Req_out high. Once the current arbiter request to the upper

level is acknowledged, i.e., Sel_in~=0, the acknowledgment signal will be rel lindI to one of

the lower ports by zeroing Sel_out_1~ or Sel_out_2~. For example, if just one port sends

the request, then this port will be granted with the acknowledgment, however, if both

ports make the request at the same time, then just one of them can be granted with the

acknowledgment depending on the competition. Only when both lower input ports reset

their request signals, i.e., Req_in_1 = 0 and Req_in_2 = 0, the request to the upper level

can be reset to zero. In this case, even just one lower input can be selected when both sent

the request, the unselected port will be serviced closely following the previously selected










one. This property can speed up the arbiter tree when many channel are frequently active

[28].

4.2.2 Row Interface

The row interface shown in Fig. 4-3 is used to control whether a row can be selected

by the row arbiter [28]. There is one row interface circuit for each row. Only when the

Row_sel_en signal from the latch control circuit is enabled, the select signal Arbiter_sel~

from the arbiter can be transferred to the row select signal Row_sel.

VDD





Row sel o







Row~request~ Arbiter request



Figure 4-3. Schematic of the row interface


4.2.3 Latch and Latch Control

The latch and latch control circuits shown in Fig. 4-4 are used to increase the

throughput of the .I-i-nchronous readout [28]. Each column has one latch cell and the

whole array has just one latch control block. The important control signals include:

* cox~ is the request signal, shared by all the neurons in the same column.

* b is used to control whether the request signals from cox~ are allowed to enter the
latch cells.

* Ip monitors whether there is request signal on the cox~.

* g~ indicates whether there is still valid data inside the latch cells.

* Col_request_n is the column request signal going to the column arbiter.












VDD


Col sel n


Rowsc _data_ready


Row_address_trigger

(b)

Figure 4-4. Schematics of the latch cell and latch control: (a) latch cell, (b) latch control.


* Col_sel_n is the column acknowledgment signal from the column arbiter.


* Row_sel_en goes to the row interface (see Fig. 4-3), which enables the new row
selection signal going into the neuron array.

* latch_data_ready is valid after request on cox~ have already entered the latch cell.
This signal, together with row_sel, reset the neuron which have fired in the selected
row.


* row_address_trigger tri r--is the row address encoder to update the row address.

One thing need to keep in mind is that signal b, Ip and g~ are shared by all latch

cells.










The operations of latch and latch control are described as below: Initially, Cox~ = 1

and reset signal makes RES~ = 0, which further makes Col_request = 0. Then we have

Col_sel = 0, g~ = 1, Ip = 0, b = 1, Row_sel_en = 1 and Latch_data_ready = 1.

Once a row sends a request to the row arbiter, with Row_sel_en = 1, the select signal

from the row arbiter can reach the neuron unit and Row _sel = 1 (see Fig. 4-3). Then

the neuron unit can send the column request signal by making Cox~ = 0 and pushing

up Ip. Since b = 1 at this time, Cox~ = 0 can go ahead to send a request signal to the

column arbiter by making Col_request = 1, which further pulls down g~. The change of

g~ and Ip lead to b = 0 which stops all the incoming column requests. Simultaneously,

Row_sel_en = 0 disables the row interface functions and guarantees no new row select

is granted. At the same time, the active Latch_data_iP..).10 and Row_sel reset all spiking

neurons in the selected row, which further disables the column request signal Cox~. In

addition, Row_address_trigger tri r--is the row address update.

In ideal situation, all the spikes output will be transmitted, with or without a delay.

However, spike loss can happen in the real chip test. Before we explain how spike drop

happens, let's take a look at how the spike get transferred. When there is a spike get

generated, it first sends the row request signal to the row arbiter. When the row request

signal is acknowledged, the column indexes of all the neurons that are spiking in the same

row will be saved in a buffer. After that, a row reset signal will be combined with the

spike output (an AND gate is used) to reset all the spiking neurons from the same row.

Which means that if this neuron within this row is having a spike output, the row reset

signal can take effect to this neuron and reset it, however, if this neuron is not generating

a spike output, the row reset signal does not have any effect on this neuron. After this

reset process, these neurons with spike outputs can begin another new integration period.

If there are two neurons (A and B) from the same row generate spikes one after another,

and the first neuron A sends the row request signal while the second neuron B is still

integrating. When the row request signal is acknowledged, the buffer begins to record










the column index of the spiking neurons (at this time, just neuron A is recorded because

neuron B does not generates spike yet). When the buffer finishes the recording and

the row reset signal begins to reset neuron A, neuron B just generates a spike. In this

occasion, because both A and B have spike outputs, the row reset signal reset both of

them. The result is that neuron B will begin a new integration period while its previous

spike gets dropped.

After each column is serviced, the corresponding Col_sel will be set to one which,

with the aid of b = 0, can remove the column request by making Col_request = 0. With

the removal of the column request signal, Col_sel will also be reset to zero. When all the

column request signals are processed, all Col_request and Co" e r e t eo hc

makes g~ = 1. When all spiking neurons are reset, Co~=1 hc aksl .Bt

Ip = 1 and g~ = 1 reset all the control signals back to their initial conditions, and all the

latch cells are ready for upcoming row and column requests.

4.2.4 Throughput Control

Col arbiter sel




RE1







Col encoder In




Col sel


Figure 4-5. Schematic of the throughput control block for clocked AER


The throughput control block shown in Fig. 4-5 was first introduced by Guo [27] to

simplify the chip testing. With the aid of two nonoverlapping clocks, this readout system










can achieve a speed above 50Mv~z [26]. The signal C/ol_ccarbiters~ se comes: fromr thle columnlr

arbiter, the signal Col_sel goes to the latch cell, and the signal Col_encoder_in triggers

the column address encoder. To facilitate the chip testing, this circuit is also used in the

eight-channel biphasic IF chip.

4.3 Chip Layout


Figure 4-6. Chip layout of the 8-channel biphasic IF neuron with AER readout


The layout of this chip with pads is shown in Fig. 4-6. There are eight channels of

biphasic IF neurons and each channel includes three components: the gm amplifier, the

comparators and the digital control block. The same blocks from all eight channels share

the same power supply and the AER circuit uses the digital control block power supply.

There are total three power supplies. Bypass capacitor is put as much as possible to










improve the performance. Guard rings are also used to eliminate the kick back noise from

the digital circuit. The total layout area including the pads is 9mm2

4.4 Measurement Results

An eight-channel biphasic integrate and fire (IF) neuron chip with clocked AER

readout circuit has been fabricated using the AMI 0.6um process with a DIP40 package.

The single channel circuit has been described in the precious chapter. Since the time

required by the Cadence simulator to simulate the AER chip is very long (greater than

one week for a 1ms transient simulation), no simulation results are provided. However, this

eight-channel chip has been successfully tested.

4.4.1 One-Channel Input

We are very curious how the AER readout circuit affects the reconstructed signal's

SER. The first measurement was conducted to answer this question. Two Agilent 33220A

signal generators were used in the testing. In this test setup, just one channel of the eight

channels was coupled to the output from one signal generator and all the inputs of the

other seven channels were grounded. Another Agilent 33220A signal generator was used

to generate the required clock for the throughput control block. The generated biphasic

spikes are modulated by the AER circuit and the final chip outputs are four bits of

address codes. An Agilent 1693A logic analyzer was used to record the four bits of address

information and this logic analyzer operated in the .-i-nchronous mode with a sampling

rate of 5ns. With this setup, the only difference between this chosen channel and the

single channel chip is that the channel in the AER chip has the AER readout circuit while

the single channel chip has the spike output directly coupled to the logic analyzer. It is

apparent that the chosen channel in the AER chip should have lower reconstruction SER

than that from the single chip of biphasic IF neuron. There are two factors responsible

for the SER difference. First, there is a time delay introduced by the AER circuit, and

each generated pulse needs to wait for some time before it can be modulated into the final

four-bit address code, while in the case of single channel chip, each generated spike can










be directly read out by the logic analyzer. Second, the control clock for the throughput

control block also introduces some error. The applied maximum clock frequency was

10MHz, with the period of 100ns, while the logic analyzer worked with a 5ns sampling

rate. Therefore, the time resolution for the AER chip is larger than 100ns.












W 30









105 106 107
Frequency (Hz)

Figure 4-7. Clock frequency vs. SER (one channel)


The measurement result of one channel test is given in Fig. 4-7. In this '. -1t! the

input of the chosen channel is set to a 1000Hz single tone with amplitude of 40mV peak-

to-peak, and the threshold of the comparator was set to +0.4V. The readout clock was

swept from 100K(Hz to I ll11. After the logic analyzer captured the four-bit address code,

a Matlab program was run to restore the corresponding biphasic pulse. The close-form

algorithm was used to reconstruct the single tone signal, and the fittingf algorithm used

in the previous chapter was used to calculate the SER. Each SER is calculated based on

two periods of the reconstructed signal. From this figure, it is clear that the reconstructed

signal SER mostly ranges from 35dB to 45dB with the maximum SER of around 43dB

corresponding to a readout clock of 1MHz and 3MHz. This figure does not give a clear










relationship between the readout clock frequency and the reconstructed SER, however,

one observation is that the readout frequency corresponding to above 40dB is greater

or equal to 0.9MHz. From the single channel chip measurement result in Fig. 3-18, the

reconstructed SER with the same input signal and +0.4V threshold is 45dB. Fig. 3-22

indicates that when the threshold increases, the SER is reduced. Based on this data,

the AER circuit with proper readout clock introduces very little error, and this error

contributes to this SER gap between 45dB and 43dB. When the clock frequency is too

slow, the SER might be restricted by the low readout throughput rate and poor time

domain resolution. When the frequency is too high, it is very likely that the fast clock

transition will introduce some noise inside the chip package, and this noise can reduce

the reconstructed SER. Therefore, there is a tradeoff when we decide which readout clock

frequency to choose.

x 104













K4-








105 106 107
Frequency (Hz)

Figure 4-8. Clock frequency vs. output spike rate (one channel)














































4U
-Fitted
0eosrce


-40
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2


Figure 4-8 shows the readout spike frequency and corresponding output spike rate.

When the clock frequency is low, it is clear that the spike rate is increasing with faster

readout clock. This relationship is reasonable, because higher readout frequency means

larger throughput. In the readout process, when a spike is generated, it sends the request

for modulation. Only when this spike is read out, this neuron can integrate for the next

spike. Only one spike can be sent out during each clock period. When the clock frequency

is high, the generated spike can be quickly sent out, the new integration period can be

initiated sooner, and the spike rate is higher. On the other hand, if the clock frequency

is low, the neuron has to wait for a longer time before it can start another integration,

and the spike rate is lower. However, when the readout frequency is higher than 1MHz,

the spike rate is reduced even though the readout clock frequency is increasing. The

possible explanation is that when the clock frequency is too high, it injects more noise into

the chip substrate. This noise affects this system, for example, this noise can make the

1I-' II4 -resistor" introduced DC offset more unpredictable.


E
a,
o
a
n
E


(b)



S0


-1
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ms)

Figure 4-9. Measured reconstruction time domain result example: (a) Reconstructed sin-
gle tone signal (red) and the 4-parameter fitted single tone signal (blue), (b)
Error.



Fig. 4-9 shows an example of the offline reconstructed signal based on the AER chip

measurement. The input signal is a 1K(Hz sine wave with 40mV peak-to-peak amplitude.










The red curve Fig. 4-9 (a) is the reconstructed sine wave and the blue curve is the 4-

parameter fitting sine wave. Fig. 4-9 (b) is the error between the reconstructed signal

and the fitting signal. This reconstructed signal has 35dB SER and the corresponding

readout control clock frequency is 1.1MHz. One strange observation from this figure is

that the large error between the reconstructed signal and the fittingf signal ahr-l- .- happens

at the high signal amplitude region, this -II__- -H that the d.1 li-. I spike readout process is

responsible for this error.

4.4.2 Two-Channel Input

In the two-channel input measurement setup, we make two of the eight channels

to share the same input from one Agilent 33220A signal generator, and the inputs of

all the other six channels are grounded. Another Agilent 33220A was again used to

generate the readout clock. This measurement setup is actually the worst case for the two

channels since spikes are likely to occur at exactly the same time. If there is some phase

delay between these two inputs, for example, when the input of one channel hit the peak

amplitude, this channel will generate the densest pulse train, if at the same time, the input

of the second channel has the amplitude of zero, and the second channel will not generate

any spike. If this is the case, all the AER sources will be automatically assigned to the

first channel. Virtually, this two channel case equals the one channel case.

The setup we used was the worst case. When the input has the maximum amplitude,

both channels are generating the densest spike train, and both will compete to use the

AER readout circuit to send out the spikes. In this case, some of the output spikes have

to be deb i-- II or even lost. Therefore, the reconstructed signals from this setup will be

lower. On the other hand, when the input has an input amplitude of zero, there will be

no spike from either channel, and the AER readout circuit will be wasted. In fact, in real

application, the two channels will have their individual input, and there will be ahr-7- .-

some difference between the two inputs.

















30: -



;25-










105 106
Frequency (Hz)

Figure 4-10. Clock frequency vs. SER (two channels)


The measurement result of two channels testing is given in Fig. 4-10. In this testing,

the output front the Agilent :33220A signal generator is set to a 1000Hz single tone with

amplitude of 40mV peak-to-peak, and the threshold of the comparator was set to +0.4V.

The readout clock was swept from 100K(Hz to Il111. After the logic analyzer captured

the four-bit address code, a 1\atlah program was run to restore the corresponding hiphasic

pulse. The close-fornt algorithm was used to reconstruct the single tone signal, and the

fitting algorithm was used to calculate the SER. Each SER is calculated based on two

periods of reconstructed signal, and the plotted SER is the average SER between these

two channels over the same time period. Front this figure, it is clear that the reconstructed

signal average SER mostly ranges fron1:30dB to :35dB with the nmaxiniun SER of around

:37dB corresponding to readout clock of 400K(Hz.

Fig. 4-11 shows the readout spike frequency and corresponding average output spike

rate over the two channels. When the clock frequency is low, it is clear that the spike rate

is increasing with faster readout clock. This trend is similar to that in the one channel










x 104


( 3-



2-:




105 106
Frequency (Hz)

Figure 4-11. Clock frequency vs. output spike rate (two channels)


case (see Fig. 4-8). However, when the readout frequency is higher than 1MHz, the spike

rate is reduced even though the readout clock frequency is increasing. Surprisingly, this

trend is also similar to that happened in the one-channel case (see Fig. 4-8). Compared

to Fig. 4-8, the spike rates in the two-channel case are normally less than those in the

one-channel case. For example, the maximum spike rate in the one-channel case is 80K(

pulse per second, while the maximum in the two-channel case is around 70K( pulse/s.

Fig. 4-12 shows the measured time domain example from the above two-channel

setup. The reconstructed signal and the fitted signal from the first channel is shown in

Fig. 4-12 (a) and the corresponding SER is 43dB. Fig. 4-12 (b) gives the reconstructed

signal and the fitted signal from the second channel and the SER is 30dB. The errors

between the reconstructed signal and the fitted signal are shown in Fig. 4-12 (c) with the

red one corresponding to channel one and the blue one corresponding to channel two. This

measurement results correspond to the 400K(Hz readout clock frequency. Compared to the










(a)
> 40 Reconstructed





0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
(b)
40 Reconstructed
a 20~ -- ~Fitted


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2






Panel error
-4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ms)

Figure 4-12. Measured reconstruction time domain result example: (a) Reconstructed
single tone signal (red) and the 4-parameter fitted single tone signal (blue)
from the first channel; (b) Reconstructed single tone signal (red) and the 4-
parameter fitted single tone signal (blue) from the second channel; (c) Error
from the first channel (red) and from the second channel (blue).


results shown in Fig. 4-7, we can find that the first channel's SER (43dB) is almost equal

to the maximum SER achieved in one channel case. However, the SER from the second

channel is much worse than that from the first channel. This result does not mean that

the reconstructed signal from the first channel is ah-li-w better than that from the second

channel. In fact, sometime the signal from the second channel has a higher SER than that

of channel one.

4.4.3 Three-Channel Input

In the three-channel input measurement setup, all three chosen channel shared the

same input: 1000Hz single tone with 40mV peak-to-peak amplitude. One Agilent 33220A

signal generator was used to provide this single tone. Another Agilent 33220A was used

to generate the readout clock and the clock frequency was swept from 100K(Hz to I ll11.











Since all three channels share the exactly same input, this is the worst case in the three-

channel setup. The threshold of the hiphasic IF coniparators were set to +0.4V. The

nicasurenient are based on 2nis time period.


32

30

28

26

24

rr22

20

18

16

14

12


Frequency (Hz)


Figure 4-1:3. Clock frequency vs. SER (three channels)


The measurement result of three channels testing is given in Fig. 4-1:3. The shown

SER is the averaged SER over the three channels during the same 2nis period. Front this

figure, it is clear that the reconstructed signal average SER mostly ranges front 26dB to

:32dB with the nmaxiniun SER of around :32dB corresponding to readout clock of 200K(Hz

and 900K(Hz. The SER with the clock frequency lower than 131Hz is higher than that

corresponding to the frequency higher than 131Hz. Surprisingly, this observation also

applies to the two-channel case (see Fig. 4-10).

Fig. 4-14 shows the average spike rate corresponding to different readout clock

frequencies. Similar to those in the two-channel and one-channel cases, the spike rate first

increases with the faster clock and then drops when the clock frequency further increases.