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MOSFET PIEZORESISTANCE COEFFICIENTS ON (100) SILICON By NIDHI MOHTA A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE UNIVERSITY OF FLORIDA 2006 Copyright 2006 by Nidhi Mohta ACKNOWLEDGMENTS I would like to thank my advisor, Dr. Scott E. Thompson, for all the support, encouragement and assistance he has given me throughout my graduate studies, and for the opportunity to work with him in the SWAMP group. Despite being really busy, he always found time for his students to discuss research and other technical deliberations. I will always adore his innovative thinking and diligent commitment to research, which I tried to imbibe during my work tenure. I will be ever grateful to Dr. Thompson for encouraging me to take up an internship with the Process Technology team at Intel, while still working on my thesis. His advice has been valuable in helping my make a sound career decision. I am also very thankful to Dr. Toshikazu Nishida and Dr. William R. Eisenstadt for supporting my research activities and for their guidance and support as my supervisory committee. I would like to thank the SWAMP group and all its members for their warm support during my research. I appreciate the efforts of Teresa Stevens for being an excellent program assistant. I thank Guangyu Sun for being a friend and source of inspiration when I first j oined the group. I would like to thank Min Chu, Andrew Koehler, Umamaheshwari Aghoram, Sagar Suthram, Ji Song Lim, Xiaodong Yang, Youngsung Choi, Kehuey Wu, Xiaoliang Lu and Niray Shah for all the research related discussions they've always found time for. We've spent many a long night in the lab trying to finish homework and prepare for quizzes, and getting into long discussions on research and life in general. I thank them for being good friends and for creating an enj oyable work environment over the years. I thank Ashok Verma for his love, support, patience, encouragement and his unwavering belief in me, like I believe in him. There has never been a single course or research related question of mine he has not tried to understand and answer to his best despite being so busy with his PhD research. My time at the university would not be complete without Swasti Mishra, who has been an incredibly understanding roommate and caring friend. During my internship at Intel, I had an opportunity to work with stateoftheart process technologies and learn a lot of new, exciting things. I thank the Process Technology and Collateral team in Folsom team and especially Kirupa Pushparaj for being a great industry mentor and supporting me with my thesis writing while balancing a busy schedule at work. I thank my loving parents, my brother Varun, and each member of my family, without whose support and motivation, my achievements would have been incomplete. I owe by being here to them. I would also like to thank all my friends, colleagues and teachers in the United States, and back home, for their overwhelming love and trust in my efforts, and for making me believe in myself. TABLE OF CONTENTS page ACKNOWLEDGMENT S ................. ...............3...._.__ ..... LIST OF TABLES ....... ................ ........___.........7 LI ST OF FIGURE S .............. ...............8..... AB S TRAC T ............._. .......... ..............._ 1 1.. CHAPTER 1 INTRODUCTION .............. ...............13.... Introducti on ................. ...............13................. Stress and Strain .............. ...............13.... Future Scalability of Strain ................. ...............17................ Focus and Organization of the Thesis .............. ...............18.... Summary ................. ...............20................. 2 STRAINED SILICON MODELING AND PIEZORESISTANCE .............. .....................2 Introducti on .............. .. ... .. .._ .... ... .. ........ .........2 Strained Si Modeling and Need for Piezoresistance Coefficients ................ ............... ....23 Definition of Piezoresistance Coefficients .................. ........... ....... ....... ............2 Relation between Strained Silicon CMOS and Piezoresistance Effect ................... ........25 Graphical Representation of Piezoresistance Coefficients Definition of Surface Longitudinal and Transverse Piezoresistance Coefficients .............. ....................2 Summary ................. ...............28................. 3 STRAIN EFFECTS ON THE VALENCE AND CONDUCTION BAND ............... ... ............31 Physics of Strained Silicon ................. ...............3.. 1............. Electron Transport ................. ...............3.. 1.............. Hole Transport .................... ....... ........ .... ......... ... ... .........3 Importance of a Larger OutofPlane Mass for the Top versus Second Band........................34 StateoftheArt Strain Technologies............... ..............3 Sum m ary ................. ...............3.. 8.............. 4 WAFER BENDING EXPERIMENT AND MOBILITY ENHANCEMENT EXTRACTION ON STRAINED SILICON MOSFETS .............. ...............44.... Wafer Bending Experiments on MOSFETs .................... ...............44. Uniaxial Stress: FourPoint Bending Apparatus Illustration ................. ................. ...._45 Biaxial Stress: ConcentricRing Bending Apparatus .............. ...............48.... Error Analysis............... ...............49 Extracting Mobility, Threshold Voltage and Electric Field from Drive Current ................... 51 Extraction of Piezoresistance Coefficients from Drive Current ................. ............. .......53 Sum m ary ................. ...............54.......... ...... 5 EXPERIMENTAL RESULTS AND DISCUSSION .............. ...............60.... Introducti on ................. ...............60................. Experimental Results ................ ........... ...............61....... Description of devices measured ................. ...............61................ Effect of surface electric field ............................... ....... .................6 Surface piezoresistance coefficients of pMOSFETS in [100] direction ................... ......63 Surface piezoresistance coefficients of nMOSFETS in [100] direction ................... ......64 Effects of outofplane uniaxial stress ......._..__ ........__ ....._._ ...........6 Sum mary .............._ ....... ...............68..... 6 SUMMARY AND FUTURE WORK .............. ...............82.... Sum mary .............._ ....... ...............82..... Future Work............... ...............84.. LI ST OF REFERENCE S .............._ ....... ...............8 5.... BIOGRAPHICAL SKETCH .............. ...............90.... LIST OF TABLES Table page 11 Elastic stiffness and compliance coeffcients for Si. ............. ...............21..... 51 Measured long channel pMOSFET piezoresistance coeffcients in this work (in blue) compared against other works and against Smith's [Smi52] bulk data in units of 10 12 cm2/dyne. The data in blue refers to this work ................. ...............79............. 52 Measured long channel nMOSFET piezoresistance coeffcients in this work (in blue) compared against other works and against Smith's [Smi52] bulk data in units of 10 12 cm2/dyne ................. ...............80......._._ .... 53 Measured long channel nMOSFET piezoresistance coeffcients along [100] channel compared against a) bulk picoeffcients measured on an ntype resistor on the same process and b) against Smith's [Smi52] bulk data in units of 1012 cm2/dyne. ...............81 54 Measured stress types needed for enhancing n/pMOSFET currents. ................. ...............81 LIST OF FIGURES Figure page 11 Stress components acting on an infinitesimal cubic element [RanO5]. ............. .................22 21 Illustration of the definitions of longitudinal and transverse stress (Adopted from [Klo94]).................. .............3 31 MO SFET schematic device cross section (standard orientation) ................. ............... ....3 9 32 Ellipsoids of constant electron energy in reciprocal ("k") space each corresponding to one of the degenerate conduction band valleys. a) For this case, the four orange colored valleys are in the plane of the silicon and the two green colored valleys are out of the plane. b) Energy level at the bottom of the six conduction band valleys. Application of advantageous strain splits the energy level as shown, removing the degeneracy (i.e the equivalence in energy) between the a2 and A4 valleys. ......................39 33 Hole constant energy surfaces obtained from 6 band kp calculations for common types of stresses (a) unstressed, (b) longitudinal compression on (100) wafer, (c) longitudinal compression on (110) wafer, (d) biaxial tension. ................ ............... ....40 34 Simplified schematic of the hole intervalley phonon scattering process. High stress and splitting larger than the optical phonon energy (60meV) are required to suppress scattering. .............. ...............40.... 35 Simplified valence band energy vs. k diagram for strained silicon under longitudinal uniaxial compression and biaxial tension. ............. ...............41..... 36 Simplified schematic of valence band splitting of strained Si as a function of gate overdrive. ............. ...............41..... 37 Schematic diagram of the biaxially strainedSi MOSFET on relaxed SilxGex layer. (Adopted from [Mey04]) .............. ...............42.... 38 Strained Si pchannel MOSFET a) process flow, b) TEM cross sectional view...................42 39 Dual stress liner process architecture with tensile and compressive silicon nitride capping layers over NMOS and PMOS. ............. ...............43..... 41 Illustration of Si channel orientation a) Si (001) surface, b) MOSFET schematic device cross section [100] channel orientation............... ..............5 42 The apparatus, jig, used to apply uniaxial stress to the substrate.(a) In this picture, uniaxial compressive and tensile stresses are generated on the upper and lower surfaces of the substrate respectively. (b) Illustration of calculating the uniaxial stress on a bent substrate. The substrate is simply supported. Four loads applied by cylinders are approximated by four point forces, P. The deflection at any point on the upper surface is designated by y(x). (c) When the parallel ridges are closer on plate A, and farther apart on plate B uniaxial compression is applied. The reverse is true for uniaxial tension. ............. ...............56..... 43 The apparatus, jig, used to apply biaxial stress to the substrate. In this picture, biaxial compressive and tensile stresses are generated on the upper and lower surfaces of the substrate respectively. Illustration of simulating biaxial stress on a bending plate (substrate). The plate (substrate) is simply supported. The deflection at any point on the upper surface is designated by w(r). ............. ...............57..... 44 Finite element analysis simulation of the bending plate (substrate) [Kwu05]. (a) The radial stresses at the center of the top, middle, and bottom planes of the bending plate vs. the displacement of the smaller ring are shown. (b) Illustration of top, middle, and bottom planes of the plate. ................ ...............58............... 45 Snapshot of the lDSVG characteristic and threshold voltage/transconductance extraction from Kiethley 4200SCS Semiconductor Parameter Analyzer. ................... ......59 51 Si channel orientation, (001) surface and MOSFET schematic device cross section [ 100] channel orientation.. ............ ...............70..... 52 Mobility enhancement vs. stress for six kinds of stresses, biaxial tensile and compressive and uniaxial longitudinal and transverse, tensile and compressive along [110] channel direction. [Kwu05]. The mobility enhancements are extracted at 0.7MV/cm. The solid lines are the model predictions: blue: [Kwu05], orange: Wang et al. [WanO3]. The symbols are experimental data: blue circle: [Kwu05], green triangle: Thompson et al. [Tho04], orange diamond: Wang et al. [WanO4], and purple square: Gallon et al. [Gal04]............... ...............71 53 sicoeffcient of pMOSFETS vs. stress, including longitudinal and transverse ri coeffcients for [110] direction and transverse sicoeffcient for [001] direction from an earlier work[Kwu05]. The solid lines are the model predictions: blue: [Kwu05], orange: Wang et al. [WanO4]. The symbols are experimental data: blue circle: this work, green triangle: Smith [20], orange diamond: Wang et al. [WanO4], and purple square: Gallon et al. [Gal04]. ............. ...............72..... 54 Effect of Uniaxial Longitudinal Tensile stress on Bulk ntype resistor and NMOSFETs (indicated as surface tension) oriented along [100] direction on (001) Si.........................73 55 Effect of Uniaxial Transverse Tensile stress on Bulk ntype resistor and nMOSFETs (indicated as surface tension) oriented along [100] direction on (001) Si.........................73 56 Effect of Biaxial Tensile and Compressive stress on and nand pMOSFETs oriented along [100] direction on (001) Si............... ...............74... 57 (100) Surface Piezoresistance coeffcient vs. bulk Piezoresistance coeffcients (a) nMOSFET (b) pMOSFET. Thicker lines indicate the surface value and thinner lines denote the bulk value. Solid lines are longitudinal piezoresistance coeffcients and dashed lines are transverse piezoresistance coefficients. (Courtesy: Chu, Min) [ Tho06] .............. ...............75.... 58 Constant energy contour for bulk Hole constantenergy band surfaces for the top band obtained from sixband k p calculations for common types of 1GPa stresses: (a) unstressed,(b) biaxial tension, (c) longitudinal compression on (001) wafer, and (d) longitudinal compression on (110) wafer (note significant differences in stress induced band warping altering the effective mass). [Tho06] .............. ....................7 59 Illustration of mobility enhancement due to band shift for (100) / [100] NMOS under transverse tensile stress. .............. ...............77.... 510 Band shift for (100) / <110> longitudinal tensile stress. ................ .......... ...............78 Abstract of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Master of Science MOSFET PIEZORESISTANCE COEFFICIENTS ON (100) SILICON By Nidhi Mohta December 2006 Chair: Scott E. Thompson Major Department: Electrical and Computer Engineering Simple MOSFET geometric scaling has driven the industry to date but as the transistor gate length drops to 35 nm and the gate oxide thickness to~1 nm, physical limitations such as offstate leakage current and power density make geometric scaling an increasingly challenging task. In order to extend Moore's law, processinduced strain has emerged as the new scaling vector for industry. The strain effects are characterized by a combination of band structure alteration, effective mass changes, band splitting, and hole repopulation. Piezoresistance coefficients are used as a metric to explain the performance improvement of devices under stress. This thesis is an experimental study of piezoresistance effects in both n and ptype silicon and mobility enhancement in strained silicon Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Fourpoint and concentricring wafer bending experiments are used to apply external stresses to the MOSFET devices. Mobility enhancement and hence devicelevel piezoresistance coefficients have been extracted by applying uniaxial and biaxial mechanical stress on (100) MOSFETs to benchmark with conventional bulk piezoresistance coefficients, where (100) denotes the substrate orientation of silicon. A study of piezoresistance coefficients measured on different channel orientations and both (100) and (110) silicon surfaces is presented. Piezoresistance measured on a (100) surface for MOSFETS oriented along the [100] channel direction has been reported for the first time. The data in this study indicates that: (1) uniaxial transverse stress for nMOSFETS in the [100] direction results in increased mobility (2) an almost constant drive current is observed for pMOSFETS along a [100] channel direction on (100) wafer. (3) in the outofplane direction, compressive stress is a better for pMOSFETs current enhancement, rather than tensile stress. A simple qualitative argument for this difference is presented by investigating the effect of the surface electric field on carrier mobility under stress. It is shown that 2D quantization in the inversion layer results in the MOSFET piezoresistance coeffieients to be different from the bulk piezoresistance coeffieients. These devicelevel piezoresistance coefficients study provides a guideline for performing aggressive strain engineering on MOSFETs. CHAPTER 1 INTTRODUCTION Introduction Strain is today a widely accepted technique of enhancing transistor performance, especially when we are scaling down to nanometer dimensions. This thesis is a study of MOSFET piezoresistance coefficients which is an important parameter to quantify mobility enhancement due to strained silicon. For the past 4 decades, geometric scaling of silicon CMOS transistors has enabled not only an exponential increase in circuit integration density Moore's Law but also a corresponding enhancement in the transistor performance itself. Simple MOSFET geometric scaling has driven the industry to date but as the transistor gate length drops to 35 nm [Cha03], [Bai04], [Chi04] and the gate oxide thickness to ~1 nm, physical limitations such as offstate leakage current and power density make geometric scaling an increasingly challenging task. Also, thin oxide results in high electric field in the channel. This results in a reduction of carrier mobility together with high channel doping. In order to continue CMOS device scaling and historical performance improvement trends, the industry needs a new scaling vector. Starting at the 90 nm technology generation, mobility enhancement through uniaxial process induced strained silicon has emerged as the next scaling vector being widely adopted in logic technologies [Cha03], [Chi04], [Tho04].The mobility enhancement results from strain fundamentally altering the electronic band structure of silicon. Stress and Strain Since the thesis is primarily concentrated around stress and strain in MOSFETs, it is essential to understand the basics of engineering mechanics like stress, strain and mechanical properties. When a force is applied on a fixed body, it deforms in its shape. If the deformation is small enough, it returns to its original shape once the applied force is removed. This is described as the linear elastic behavior of the body and the deformation is considered to be within the elastic limit. Stress (0) is defined as force per unit area AA acting on the surface of a solid. Its unit is Pascal (Pa). cr= lim,' A>0) Any stress on an isotropic solid body can be expressed as a stress matrix o in a cartesian coordinate system as a 3x3 matrix, (Equation 12) yx p yz (12) Szx Kzy Xzz The stress matrix is symmetric with r, = r, and the 3x3 matrix can be simplified into the 6 xl stress vector below: zxx Stress is a vector which has two components: normal and shear component. Normal or Hydrostatic Stress: Force per unit area, acting normal to the area is called the normal stress g' Shear Stress: Force per unit area, acting tangential to area, i.e. along the plane of the surface, is called the shear stress K '. As a rule of thumb, tensile stresses are considered positive and compressive stresses as negative. To understand the stresses and strains in depth, consider an infinitesimal cube as shown in Figure 11. The figure shows normal and shear stresses in x, y and z directions acting on different planes of the cube. The first subscript identifies the face on which the stress is acting, and the second subscript identifies the direction. The X ii' components are the normal stresses while the ic ij' components are the shear stresses. Strain 'E' is defined as change in length of an obj ect under force, compared to its original length. It is a unit less quantity. Normal strain is the relative lattice constant change. E = ao (14) where ao and a is the lattice constant before and after strain respectively. Similar to stress, strain also can be represented as a 6xl matrix, as is shown in Equation 15. zz 2E, Poisson ratio 'u', one more important property of the material, is the ratio of lateral contraction strain to longitudinal extension strain in the direction of the tensile stress. Stress and strain are related to each other by the material property called Young's Modulus 'C' as C = d/e. Hence, the Young' s modulus defines the stiffness of the material. The relationship between stress and strain in terms of stiffness coefficients is shown in Equation 16. x, ~1 12 0CC, 0 0 Xw 12, 11, 12, 0 0 S, Xzz 12, 12, 12 0 0 0 Ez K 0 0 0 C, 0 0 2E yz 44yz (16) K 0 0 0 0 C4 0 2E zxK~ 4O 4 zx2E where the coefficients C11, C12 and C44 are COnstant for a given material. Reversibly, the relation can be also be expressed as S = E, where S gives the compliance coefficients of the given material. Table 11 shows the values of stiffness and compliance coefficients for silicon. Motivation Device level piezoresistance coefficients are of great value to device and process engineers in evaluating the types of processinduced stress than can contribute to mobility enhancement which in turn improves transistor performance. Different types of stress are required for device mobility enhancement as indicated from Si bulk piezoresistance coefficients [Smi52]. For channel direction [110], longitudinal tensile and outofplane compressive stress for nMOSFETs and longitudinal compressive stress for pMOSFETs are used [Tho04]. However, some characteristics of strained devices cannot be explained by the bulk piezoresistance coefficients. Also, there isn't enough published data on the piezoresistance observed along strained [100] channel devices. In this work, upon application of uniaxial transverse stress on a [100] nMOSFET it is observed that surface and bulk piezoresistance values not only differ in magnitude but also in sign. However, based on the previous bulk Si piezoresistance coefficients [Smi52], there is actually mobility degradation observed on the nMOSFETs. Also this work reports the bestfit piezoresistance coefficient nL Of nMOSFET from experiments as 38.55x10 11Pa1, which is smaller than 102x1011Pal [Smi52]. Surface longitudinal piezoresistance coefficient for [100] channel is much smaller than bulk value, which means that the <100> channel MOSFETs have smaller mobility enhancement than bulk Si. Therefore, the previously reported bulk piezoresistance coefficients should be modified for strained device engineering. In this work, devicelevel piezoresistance coefficients were directly extracted from Si n/pMOSFETs by applying uniaxial and biaxial stress in different channel direction on (100) surfaces. Future Scalability of Strain When pursuing performance features to extend Moore's law, it is important to consider how the performance enhancement scales as the device feature size is reduced. The classical equations for MOSFET transport for long channel devices show that the drain current is inversely proportional to the channel length. puWC, Vdj~ d(hin) L 2J~ d17 puWC, V~ d(sat)g 2L (18) However as the MOSFET carrier transport becomes ballistic, the carrier transport can best be described by carrier injection at the source [LunO2]. The drain current in saturation, d" is given by Idsat) = WC1, < v(0) > V, V) (19) where(v(0))is the average velocity of carrers at the source and (ox(V, V,) is the charge density [LunO2]. In the limit where channel length goes to zero, I(go)) is the unidirectional thermal velocityUT since the velocity at the beginning of the channel is set by carriers inj ected from the thermal equilibrium source [LunO3], UT is given by I2kBTL UT=i ~m,~W2 t(110) Thus in the nanoscale channel limit, the drain current becomes d, = W C ox ~V,V, ) V xm t (111) From Equation 111, it can be seen that straininduced decrease in the effective mass will still enhance the drive current in ballistic MOSFETs which has been a historical concern for mobility enhancement techniques. This serves as the motivation for this work, as peizoresistivity will be shown as an important parameter in quantifying mobility enhancement through strain. Furthermore, at higher strain levels than in stateoftheart production today, reduction in effective mass continues due to increased repopulation of valleys/bands. This phenomenon is even more pronounced for holes. Also, when at higher strain the valence band splitting (~ 25meV at 100 MPa to ~55meV at 1 GPa) becomes greater then the optical phonon energy, the hole mobility will further be enhanced by a reduction in scattering rate. Experimental and theoretical work suggests much larger mobility enhancement is achievable at higher strain. Ratios of stressed to unstressed mobilities of 4 and 1.7 have been reported experimentally for holes and electrons [Hoy02], respectively. The problem of dislocations in the strained layer at higher levels of strain will have to be addressed by changing thermal cycles and controlling growth. Focus and Organization of the Thesis This thesis will mainly focus on reporting measured Piezoresistance coefficients of MOSFETS on (100) silicon wafer and oriented along two maj or crystal axes, [100] and [1 10] directions. The effect of surface electric field on stress has been explained and incorporated in the piezoresistance model for the first time and as a result, device level piezoresistance coefficients show sharp contrast with bulk piezoresistance first reported by Smith [Smi52]. A comparative study will be made with all reported piezoresistance coefficients in literature which can be easily understood and provide quick, accurate predictions for the types of stress that contribute to mobility enhancement in strainedSi MOSFETs. Most of the experimental work has not studied the piezoresistance observed along the [100] direction of n and p type MOSFETs. A simple physical model is developed that provides insight into the physics of mobility enhancement under the combined influence of stress and surface electric field. Chapter 1 begins with an introduction to the history of strain, definitions and relation between stress and strain. Future scalability of silicon into the ballistic regime is discussed. In chapter 2, a thorough understanding of piezoresistance coefficients is developed and the relationship between strained silicon CMOS and piezoresistance is outlined which serves as the basis for experimental results in the future chapters. In chapter 3, an explanation of the valence and conduction band physics under strain is given. The importance of a large outofplane mass for mobility enhancement is explained in detail. This is followed by a discussion of stateofthe art strained technologies used today and why the industry is adopting uniaxial stress. In Chapter 4, experiments designed to measure piezoresistance are presented. The fourpoint and concentricring wafer bending experiments are used to apply the uniaxial and biaxial stresses respectively. The technique used to extract piezoresistance on bulk ntype silicon resistors has been described. This is followed by a brief discussion on uncertainty and error analysis. The main factor contributing to the linear drain current increase will be identified from analyzing the variables in the linear drain current equation. Chapter 5 discusses the experimental results obtained and the physics behind the observed piezoresistance in detail. The electron and hole mobility and the mobility enhancement are extracted from the drain current in the linear region (Idlin). The mobility enhancement vs. stress will be plotted. The n: coefficients will then be calculated from the mobility enhancement vs. stress. The reasoning behind the observed change in magnitude and even sign of the device level piezoresistance coefficients when compared to bulk piezoresistance values is stated. The effect of vertical electrical field on the carrier mobility and splitting in the energylevels due to inversion layer confinement is explained. Finally, chapter 6 summarizes the thesis and provides recommendation for the future work. Summary In this chapter, strain is introduced as a vector to extend Moore's law and to ensure continual MOSFET performance enhancement. The relation between stress and strain is outlined. This is followed by a discussion on the main motivation behind this work and the focus and organization of this thesis. In the following chapter, a thorough understanding of piezoresistance coefficients is developed and the relationship between strained silicon CMOS and piezoresistance is outlined. This will serves as the basis for experimental results in the future chapters . Table 11. Elastic stiffness and compliance coefficients for Si. Compliance Coefficients (10"~Nlcm2) 1.657 0.650 0.7956 S,, S, S44 0.768 0.214 1.250 Figure 11. Stress components acting on an infinitesimal cubic element [RanO5]. CHAPTER 2 STRAINED SILICON MODELING AND PIEZORESISTANCE Introduction The first section of this chapter introduces the relation between the piezoresistive effect and strained silicon MOSFET. This is followed by a discussion on the piezoresistance coefficients, their need, and relevance to understanding strainenhanced electron and hole mobility for the industry. The piezoresistive effect arises because silicon is a cubic crystal with anisotropic material properties. As a consequence, stress applied along different directions/surface orientations of silicon results in making the piezoresistance coefficients to be a function of crystal direction and orientation. Appropriate numerical analysis of the effect of MOSFET carrier mobility under stress in terms of piezoresistance coefficients is provided. The technique of extraction of piezoresistance coefficients reported in this work from drive current and mobility enhancement is explained. Finally, the literature todate on piezoresistance coefficients is briefly reviewed. Strained Si Modeling and Need for Piezoresistance Coefficients Many previous works [Wel94], [Nay94],[Fis96], [Tak96] have pointed out that the main factors that affect mobility are: the change in the averaged longitudinal effective mass due to relative carrier distribution on different valleys (NMOS) or bands (PMOS); the change in intervalley carrier scattering rate due to the energy splitting between different valleys or bands. (More details and insight into the physical mechanism responsible for this mobility enhancement is given in chapter Historically, it has been difficult to model strainenhanced mobility due to the uncertainty in the inversion layer scattering parameters [Fis02] [Fis03] [Tak96] and numerical complexity that forces many early approximations during the modeling process. It is possible that using conventionally accepted scattering parameters, electron and hole mobility enhancements could be under or over predicted [Fis02] [Tak96]. Another example is the Hield dependence of hole mobility enhancement for uniaxial compression and biaxial tensile stress that was first observed experimentally [Tho04] but not predicted. Experimental data sometimes helps in gaining more insight into a complex physical mechanism than predictive modeling. Because of these modeling difficulties, the most effective approach at predicting and understanding strainenhanced electron and hole mobility for the industry has been the empirically measured piezoresistance coefficients [Tho06]. Piezoresistance coefficients are generally measured at low strain and low field, primarily due to the limits imposed by the existing wafer bending setup which will be discussed later in chapter 4. Additionally, piezoresistance coefficients have the benefit of capturing mobility enhancement primarily resulting from changes is conductivity mass, which will be shown later in this chapter. Definition of Piezoresistance Coefficients Since C. S Smith [Smi53] first discovered the piezoresistance effect of semiconductors having anisotropic band structures such as silicon 50 years ago, the semiconductors have found applications in pressure and mechanical stress sensors [Kan91]. The piezoresistance effect in strained silicon is defined as the stressinduced resistance change. The exact definition of piezoresistance coefficients can be expressed as Equation 21: S=1 R, Ro 1 AR X Ro Z Ro(21) where, Ro and RX are the unstressed and stressed resistances, X is the uniaxial stress and AR is the change of resistance under certain stress. Thus, the value of ri coefficient is determined by the value of AR with stress [Klo94]. Since R = pA /L where p is the resistivity, A is the crosssectional area, and L is the length; the resistance change may either be due to a combination of resistivity change and/or change in geometry. Furthermore, the work done in reference [Kan91] explains that the change of resistance is somewhat linearly dependent on stress within the range of our measurement (50400MPa). The relative change in resistance is given by: AR Al Aw At Ap =+ (22) Rlwtp where, 1, w, t and p represent the length, width, thickness and resistivity respectively. For a semiconductor, the dimensional change under stress can be neglected for the stresses of interest used in the experiments in this work (<500 MPa) compared to the change of resistivity [Kan91]. Thus, the change in resistance is mainly due to the change of resistivity. Next, we will establish the relation between this piezoresistive effect as seen in a semiconductor with the mobility enhancement resulting from strained silicon MOSFETS. Relation between Strained Silicon CMOS and Piezoresistance Effect The strain effects responsible for the transduction physics of micromachined piezoresistive sensors is closely related to mobility enhancement in strained silicon CMOS [Kwu05]. The strain effect on the valence and conduction band of silicon can be used to explain and quantify the piezoresistance effect in n and ptype strained silicon as well as the electron and hole mobility enhancement in strainedSi MOSFETs. The stressstrain relationship has been explored in chapter. From equation (22), it follows that the ri coefficient may be expressed in terms of resistivity change or conversely in terms of conductivity change as follows: S=1 AR 1 Ap 1 As Z Ro Z Po Z Goi (23) The resistivity of a semiconductor can be expressed as Equation 24: p =1 (24) qpu,n +qpu,p where, p. and o are the resistivity and conductivity respectively and q p, and up are electron charge, electron mobility and hole mobility respectively. The electron and hole concentration are represented by n and p respectively. This conductivity change is directly related to mobility change since 0= qpp where q is the electronic charge, pn,p, is the electron and hole mobility, p is the hole concentration and n is the electron concentration. Hence, assuming that for a certain semiconductor under steady state n and p are constant, it can be concluded that piezoresistance coefficients are mainly determined by the change in carrier mobility with stress. The effect of mechanical stress on mobility can be developed by the following equations. Under uniaxial stress, the normalized mobility variations reduce to [Bra0 1] u = ns 2 o (25) ~~s 2 44 O,I (26) where, n, = n,, +012 Hence, we can reduce equations (25) and (26) to get an expression for mobility under stress as [Tho06] where the subscripts  and I refer to the directions parallel and transverse to the current flow in the plane of the MOSFETs, is the fractional change in mobility, 0 and a, are the longitudinal and transverse stresses and 4i and r are the piezoresistance coefficients expressed in Pal or 1012 CM2/dyne. Two types of uniaxial stresses are defined in Figure 21 in order to distinguish the two kinds of ai coefficients, longitudinal and transverse [Klo94]. Longitudinal stress implies it means that the uniaxial stress, electric field, and electric current are all in the same direction. Transverse stress implied that the electric field is parallel to the electric current but normal to the applied uniaxial stress. This is illustrated in more detail in Figure 21. Graphical Representation of Piezoresistance Coefficients Definition of Surface Longitudinal and Transverse Piezoresistance Coefficients Yozo Kanda [Kan82] plotted the bulk longitudinal and transverse piezoresistance coefficients as a function of the crystal directions for orientations in the (100), (1 10), (21 1) planes. In this way, the value of piezoresistance coefficient for different channel directions can be seen clearly and can be compared directly. The method of generating surface piezoresistance coefficients is the same while the process is slight different from that introduced in [Kan82]. In crystal with cubic symmetry, such as Si and Ge, the bulk pi coefficient tensor is given by ai~ g,~ O 0 0 x g, O 0 0 x 4, O 0 0 (28) The tensor is used to calculate the longitudinal and transverse piezoresistance coefficient for any arbitrary direction as shown below [Kan82] st= , (, x), 2 +n, n + n, 1, (29) 4f = x,,2 + (x,,l jZ1? x,)~ If121~ + n2, n2)+ n, n( (210) For the calculation of surface piezoresistance coefficient, the symmetrical 3D tensor was not used instead a 2D form was used which is applicable to an inversion layer [Col68] 21 22 'T4(211) 41 42 44 As the tensor is symmetric, for both (100) and (110) surface of Si, the tensor reduces to [Col68]: x2 2 (212) 0 0 zi44 For (100) surface, "ir = #22 and "1r2 = i21 Using coordinate transformation to find the longitudinal and tranverse piezoresistance coefficient in any arbitrary direction, the final result obtained is shown below El x1,4 121212 12 12 +i22 1 2Ki4412 12 (213) x, = x,31,21 + i12 12 2 i21 12 22 12m2 + 2K44~1 ~2 1 2 (214) where nl is the surface longitudinal piezoresistance coefficient and nt is the surface transverse piezoresistance coefficient. It is this difference in bulk and surface coefficients that will lead to some interesting physics about the mobility enhancement in a 2D quantized inversionlayer MOSFET to be presented with the results in chapter 5. Summary In this chapter, the relation between the piezoresistive effect and strained silicon MOSFET was elaborated, which will serve as a foundation for understanding the experimental results. This was followed by a discussion on the piezoresistance coefficients, their need, and relevance to understanding strainenhanced electron and hole mobility for the industry. Appropriate numerical analysis of the effect of MO SFET carrier mobility under stress in terms of piezoresistance coefficients was provided. The technique of extraction of piezoresistance coefficients reported in this work from drive current and mobility enhancement is explained. Finally, the literature todate on piezoresistance coefficients is briefly reviewed. Chapter 3 discusses the physics of strained silicon, its implications and stateoftheart strained technologies. Stres sed Transverse Z E' ,+V 1 . Stressed Longitudinal zt E~ Vz I.I Unstre ssed I. E Electric Field X" Stress Figure 21 Illustration of the definitions of longitudinal and transverse stress (Adopted from [Klo94]). CHAPTER 3 STRAIN EFFECTS ON THE VALENCE AND CONDUCTION BAND Physics of Strained Silicon Strained Si has been studied for 50 years but only recently have some of the subtleties of carrier transport in a strained 2dimensional MOSFET inversion layer been fully understood or possibly appreciated [Wel94 ], [Nay94], [Tho03], [Fis96]. The carrier mobility is given by qr na (31) where Z is the scattering rate and n2 is the conductivity effective mass. Strain achieves mobility enhancement by the following two primary factors: (a) Reduction in the conductivity effective mass and (b) Reduction in the scattering rate or (c) a combination of both. For electrons, both mass and scattering changes are now generally accepted as important for mobility enhancement [Yua01]. However, for holes, only mass change due to band warping [Tho03] appears to plays a significant role at today's manufacturable (< 1GPa) stress levels since strain induced valence band splitting is smaller than for the conduction band. Furthermore, though there has been much focus on reduced inplane mass to increase mobility, increasing the outofplane mass for electrons and holes is now understood to be equally important for maintaining the mobility enhancement at high vertical fields (see Figure 31 for definition of in and outofplane). In the next section, electron transport in strained silicon is explained, which is better understood. This is followed by a discussion on hole transport which until recently [Tho03] was less understood, but which has some interesting physics with practical implications. Electron Transport For electron transport in bulk silicon at room temperature, the conduction band is comprised of six degenerate valleys as shown in Figure 32a. These valleys are of equal energy as shown by A6 in Figure 32b. The degeneracy reflects the cubic symmetry of the silicon lattice. The effective mass for any direction is the reciprocal of the curvature of the electron energy function in that direction. Consequently, the effective mass of each ellipsoid is anisotropic, with the transverse mass (perpendicular to the axis) given by mt = 0.19mo being significantly smaller than the longitudinal mass (parallel to the axis) given by m' = 0.98mo where mo is the free electron mass. For unstressed bulk silicon, the total electron conductivity mass, n2 is obtained by adding the contributions of the six degenerate valleys and is given by Equation 32, nt 1I 2 4 (32) For MOSFETs on a (001) wafer, advantageous strain removes the degeneracy between the four inplane valleys (A4) and the two outofplane valleys (A2) by splitting them in energy, as shown in Figure 32b. Due to the lower energy of the A2 valleys they are preferentially occupied by electrons. The electron mobility partly improves via a reduced inplane and increased outof plane m* due to the favorable mass of the A2 valleys resulting in more electrons with an inplane transverse effective mass (m, = 0.19mo) and outofplane longitudinal mass (m' = 0.98mo). For a given strain, quantifying the effective mass reduction and comparing it to the enhanced mobility shows that mass reduction gain alone explains only part of the mobility enhancement [Tak96]. Hence, electron scattering must also be reduced due to the conduction valleys splitting into two sets of energy levels, which lowers the rate of intervalley phonon scattering between the A2 and A4 valleys. Quantifying the improvement due to scattering has been difficult using acceptable scattering parameters but reduced scattering is still believed to account for the rest of the mobility enhancement [Yua01i]. Many types of stress increase the electron mobility via increased population in the A2 valley (inplane biaxial and uniaxial tensile and out of plane uniaxial compressive stress are some examples). Hole Transport For holes, the valence band structure of silicon is more complex than the conduction band. It is this complex band structure and valence band warping under strain that results in much larger hole than electron mobility enhancement and the reason strained pMOSFETs are a key focus in advanced logic technologies. The band warping is also responsible for why different types of strain (namely the technologically important biaxial tensile and uniaxial compressive stress) behave differently. For unstrained silicon at room temperature, holes occupy the top two bands: heavy and light hole bands. The unstrained constant energy surfaces for the two bands are shown in Figure 33 and highlight the large heavy hole mass along the <110 > direction (common MOSFET channel orientation). With the application of strain, the hole effective masses become highly anisotropic due to band warping and the energy levels become mixtures of the pure heavy, light and splitoff bands. Thus, the light and heavy hole bands lose their meaning and holes increasingly occupy the top band at higher strain due to the energy splitting. The warped valence bands are shown in Figure 33 for the three most common types of stresses studied by the industry (biaxial tensile and longitudinal uniaxial compressive stress on (100) and (110) wafers). To achieve high hole mobility, it is key for the top band to have a low inplane conductivity mass (i.e. a narrow width to constant energy surface along <110>) since it is difficult at manufacturable stress levels to significantly enhanced hole mobility through reduced intervalley scattering. This is because valence band splitting under strain is small (as compared to the conduction band). Hole intervalley scattering is not significantly reduced for stress < 1GPa since the bands' splitting needs to be comparable to the optical phonon energy (60meV) to appreciably suppress intervalley phonon scattering (see Figure 34). Thus, the key to providing large hole mobility is favorable band warping in the top band and enough band splitting to primarily populate the top band. As seen in Figure 33, the narrower constant energy surface in the <110 > direction for uniaxial compression on both (100) and (110) wafers creates a 40% smaller inplane mass as compared to biaxial tensile stress. Also, as seen in Figure 33 for biaxial tensile stress, the outofplane mass (z / <001> direction) for the second band is larger then the top band (reverse is true for compressive stress). Figure 3 5 summarizes the key features for the top band in the simple 2dimensional energy vs. k diagram. The light, top band, outofplane mass for biaxial tensile stress creates an interesting effect for carrier transport in the 2dimensional MOSFET inversion layer that will be discussed in the next section and explains why biaxial tensile stress gives significant mobility enhancement at high stress but only to lose the mobility enhancement at high vertical fields. Importance of a Larger OutofPlane Mass for the Top versus Second Band In a MOSFET, 2dimensional surface confinement in the inversion layer also shifts the valence bands and the conduction valleys. Whether the confinement induced shift adds to or reduces (cancels) the strain induced splitting simply depends on the magnitude of the outof plane masses (valence band splitting is more complicated but this simple model captures the essential physics). Bands or valleys with a "light" out of plane mass will have a larger energy level shift relative to bands with a "heavy" mass (similar to the increasing ground state energy of a quantum well as the particle mass decreases). Hence, when the top most occupied band (or valley) has a lower outofplane mass compared to the next occupied band, the splitting is reduced or lost with surface confinement. Figure 36 pictorially shows the energy level shift with confinement for both uniaxial and biaxial stress. Etop represents the top band with large outofplane mass for uniaxial stress and small for biaxial stress (relative to the second band). Hence, the top band will have a small shift in energy due to confinement from high vertical field for uniaxial stress but large shift for biaxial stress. Second represents the second band. As seen in the figure, the stress induced band splitting (Etop E bottom) is increased for uniaxial stress but decreased for biaxial tensile stress. Thus, strain favors occupation of the top band for both types of stresses; however, confinement favors occupation of the top band for uniaxial compressive stress and second band for biaxial tensile stress. The net effect is strain and confinement is additive for uniaxial compressive stress but subtractive for biaxial tensile stress. The competing effects of strain and surface confinement on the band splitting is one of the reasons for the loss in mobility enhancement in biaxially strained silicon pMOSFETs at high electric fields. However, in nMOSFETs at high electric fields, the outofplane mass for the A2 valleys is high because in the outofplane direction, the mass is given by the longitudinal mass (m, = 0.98mo) Hence the band splitting for NMOS at high electric fields is preserved. The increased valence band splitting with confinement maintains the stress enhanced mobility at high vertical fields and is one of the key reasons uniaxial stress is being widely adopted [Wel94], [Zha05], [Gha03], [Gil04]. StateoftheArt Strain Technologies Two basic approaches of implementing strain on MOSFETS exist A global approach where stress is introduced across the entire substrate and the other is a local approach where stress is engineered into the device by means of epitaxial layers and/or high stress nitride capping layers. Most of the pioneering work on strained silicon has focused on biaxial global stress using a wafer based approach of a thin strained silicon layer on a thick relaxed SilxGex virtual substrate to stretch the Si channel. High biaxial tensile stress can been shown to increase the hole mobility [Mey04]. Figure 37 [Kwu05], [Mey04] is a schematic diagram of the biaxial strained Si MOSFET using relaxed SilxGex. However, for the first and second generation strained silicon MOSFETs being adopted in all high performance logic technologies [Tho04], [Gha03], [Gil04] the industry is adopting process induced uniaxial stress, which will be the focus of this section. Although both biaxial tensile and uniaxial compressive stresses can improve the hole mobility, the efficacies of the two stresses are different. Uniaxial process induced stress (as opposed to biaxial) is being pursued since larger hole mobility enhancement can be achieved at low strain and because of significantly smaller stress induced nchannel MOSFET threshold voltage shift [Tho04]. For uniaxial compressive stress, about 50% hole mobility enhancement can be achieved with about 500MPa [ Tho04b], [Tho04c]; however, biaxial tensile stress needs more than 1GPa to be able to increase the hole mobility. In fact, at low biaxial tensile stress, the hole mobility is actually degraded [ Rim02], [Rim03], [Fis02], [Fis03], which is contradictory to the theoretical prediction made by Oberhuber et al. [Obe98]. Because of these and other differences between uniaxial and biaxial stress, the highest drive current enhancement on short channel devices for uniaxial stress (1.46mA/Cm and 0.88mA/Cm for n and pchannel devices, respectively) [Bai04] has already significantly surpassed biaxial stress (0.85 mA/Cm and 0.45mA/Cm for n and for p channel, respectively) [WanO3]. Three stateoftheart techniques to introduce uniaxial strain in the Si channel will be described next. In the first approach [Tho04] reported by Intel, Texas Instruments and Applied Materials Inc., a local epitaxial film is grown in the source and drain regions which introduces uniaxial stress into the silicon channel. The process flow consists of the following steps shown in Figure 38(a). First, the Si source and drain are etched creating a silicon recess. Next, SiGe (for p channel) or SiC for nchannel is epitaxially grown in the source and drain. This creates primarily a uniaxial compressive or tensile stress respectively, in the channel of the MOSFET. For 17% Ge, 500 to 900 MPa of channel stress is created depending on the proximity of the SiGe to the channel. Impressive 6090% drive current enhancements on short devices (~3 5 nm) have been demonstrated, which offers greater device performance than nearly any other Si device enhancement concepts. A second lower cost technique to introduce strain in the MOSFET is with a tensile and/or compressive capping layer [Pid04], [YanO4] as shown in Figure 39. The capping fi1ms are introduced either as a permanent layer post salicide as discussed here or as a sacrifieial layer before source and drain anneal to be discussed next. This dual capping layer approach has been recently enabled by the creation of very high compressive and tensile stress SiN. SiN layers with > 2.0 GPa of tensile stress and >2.5GPa of compressive stress have recently been developed by Applied Materials. IBM, AMD and Fujitsu [Pid04], [YanO4] have reported a CMOS architecture as shown in Figure 15 in which high tensile and high compressive silicon nitride layers are selectively deposited on NMOSFET and PMOSFET respectively. This Dual Stress Liner (DSL) architecture creates longitudinal uniaxial tensile and compressive stress in the silicon channel to simultaneously improve both n and pchannel transistors. The process flow consists of a uniform deposition of a high tensile Si3N4 liner post silicidation over the entire wafer followed by patterning and etching the fi1m off pchannel transistors. Next, a highly compressive SiN layer is deposited and this film is patterned and etched from nchannel regions. High stress compressive films can induce channel stress comparable in magnitude to the first generation embedded SiGe in the source and drain. The advantages of dual stress liner flow over epitaxial SiGe are reduced process complexity and integration issues. Capping layers can also introduce strain into the silicon channel via a stress memorization of the polySi gate [Hao04]. In this approach, a highly tensile nitride capping layer acts as a temporary stressor. The flow consists of the following steps: (i) polySi gate amorphization, (ii) deposition of a high stress SiN layer on top of the polySi gate, (iii) recrystallization of the polySi gate during source/drain anneal, and (iv) removal of the SiN layer. After removal of the polySi capping layer some stress remains in the polySi gate and Si channel. Nchannel transistor enhancement of > 10 % has been reported with this technique. Summary In this chapter, the physics of strained silicon was discussed in detail. Strain introduces advantageous anisotropy in silicon by altering the valence and conduction band structures and/or scattering rates. Favorable carrier repopulation and reduced intervalley scattering result in higher mobility enhancement for unaixal stress compared to biaxial stress, and this enhancement is maintained even at high vertical electric field. SiGe in the source and drain, dual stress liners and stress memorization techniques have been introduced into stateoftheart MOSFETS. The next chapter discusses wafer bending techniques used in the experimental setup of this work and explains the method of extraction of piezoresistance coefficients from the drive current enhancement. It~d bS; 1  d, Channel Direction <1 Out of plane<01 Figure 31. MOSFET schematic device cross section (standard orientation) "t A4 Figure 32. Ellipsoids of constant electron energy in reciprocal ("k") space each corresponding to one of the degenerate conduction band valleys. a) For this case, the four orange colored valleys are in the plane of the silicon and the two green colored valleys are out of the plane. b) Energy level at the bottom of the six conduction band valleys. Application of advantageous strain splits the energy level as shown, removing the degeneracy (i.e the equivalence in energy) between the a2 and A4 valleys. Strained Si (a) Unstrained Unstressed 1G Pa of Stress (b) (d) Biaxial E (100) > tlop second Uniaxial ("1 10) Uniaxial <"110>2 k k k (a) Heavy holes Light holes Figure 33. Hole constant energy surfaces obtained from 6 band kp calculations for common types of stresses (a) unstressed, (b) longitudinal compression on (100) wafer, (c) longitudinal compression on (110) wafer, (d) biaxial tension. AE > hwo AE ~hmo, /' AE = 0 Unstressed High stress > 1GP~a Moderate stress <14GPra Figure 34. Simplified schematic of the hole intervalley phonon scattering process. High stress and splitting larger than the optical phonon energy (60meV) are required to suppress scattering. Channel direction <"110> Outofplane <001> Figure 35. Simplified valence band energy vs. k diagram for strained silicon under longitudinal uniaxial compression and biaxial tension. Low Vertical Field Uniaxial Biaxiarl S iO, Etoa Second . , Etop second Second Band splitting due to strain Splitting (increases) / (decreases) under confinement Figure 36. Simplified schematic of valence band splitting of strained Si as a function of gate overdrive . Inplane <110> Uniaxial High Vertical Field rb Substrate e e*+e~ e~.~ 'Relaxed SiGe ** . b~~~+* IrC~ * Figure 37. Schematic diagram of the biaxially strainedSi MOSFET on relaxed Si lxGex layer. (Adopted from [Mey04]) G~ate SiGe epitaxial growth (b) (a) Figure 38. Strained Si pchannel MOSFET, a) process flow, b) TEM cross sectional view Tensile Nitride Compressivle Nitride stress Figure 39. Dual stress liner process architecture with tensile and compressive silicon nitride capping layers over NMOS and PMOS. CHAPTER 4 WAFER BENDING EXPERIMENT AND MOBILITY ENHANCEMENT EXTRACTION ON STRAINED SILICON MOSFETS In this chapter, wafer bending experiments designed to measure Piezoresistance coefficients as described the in previous chapters are presented. The electron and hole mobility enhancement vs. stress is extracted and the Fr coefficients of n and ptype silicon are subsequently calculated. Concentricring and fourpoint bending apparatus are used to apply six kinds of mechanical stress to the channels the MOSFETS under test. These are: Biaxial tensile, biaxial compressive, uniaxial longitudinal tensile and compressive and uniaxial transverse tensile and compressive stresses. The stress range used in these experiments is 50MPa to 350MPa. MOSFETs from 90nm technology [Tho04a], [Tho04b], [Tho02] with the channels oriented along [100] direction on (001) wafers are used in the experiments. Uniaxial Tension is also applied on ntype resistors on the same wafer belonging to 90 nm technology as well. This is done to measure and compare piezoresistance coefficients on bulk silicon where the effect of surface electric field is absent with device level coefficients. First, the fourpoint bending apparatus used to apply uniaxial stress will be explained in detail and equations for calculating the uniaxial stress will be derived. For the concentricring bending jig used to apply biaxial stress, nonlinear bending relations are used. Methods used to extract threshold voltage and mobility under a given gate bias are explained. Finally, a brief discussion on error and uncertainly analysis associated with stress calibration is reviewed followed by a summary of the chapter. Wafer Bending Experiments on MOSFETs An illustration of a (001) silicon surface is shown in Figure 41(a). As seen in the figure, the [100] crystallographic direction is oriented at 450 from the wafer notch (which is oriented along [110] direction). Rectangular wafer strips with the n and p channel devices were prepared by sawing the wafer using an opticalcleaver. Care was taken to ensure the edges were as smooth as possible and free of defects. Figure 41(b) shows the MOSFET crosssection with [100] being the channel direction and the [110] axis represented as the direction outoftheplane of silicon. In this work, uniaxial stress is applied along the [100] direction and a corresponding biaxial stress is also applied on the device that translates into an equivalent outofplane stress. Uniaxial Stress: FourPoint Bending Apparatus Illustration Uniaxial stress is applied to the channel of a MOSFET using fourpoint bending technique. Figure 42(a) and 42(b) are pictures of the apparatus used to bend the substrate and the illustrations of calculating the uniaxial stress. As shown in Figure 32(b), the upper and lower surfaces of the substrate will experience uniaxial compressive and tensile stress along [100] direction, respectively. Reference [Tim76] describes the equations used to quantify the applied stress on both the surfaces under the following assumptions: (i) The substrate is simply supported. (ii) Four loads applied by four cylinders are approximated by four point forces, P. Using Figure 42(b), the deflection at any point on the upper surface is represented by y(x) [Kwu05]. As there is no deflection at the end points, it can be assumed that y(0)=0 and y(L)=0. Using the above assumption the stress on the upper and lower surfaces at the center of the substrate are given by Equation 41 and Equation 42, EH opev (41) EH axoe (42) where E = 1.302 x 10" Pa [Bra72] is the Young' s modulus of crystalline silicon along the [100] direction on (001) substrate, H is the substrate thickness, r is the radius of curvature [Tim76] , which is given by Equation 43, 1 MPa (43) r El. El. where 2M = Pa is the moment for a I x < L/2, and IZ = bH /12 is the moment of inertia for a substrate with rectangular cross section and width of b. Using Equation 41 and 42, equation 4 2 can be written as, [Tim76] M~H PaH oxpe (44) xup' 2I 2I M~H PaH oxlowe;. (45) 2I2 2I For 0 I x I a, the moment 2M = Px and d~y El = M~ = Px (46) = dx~C The solution for the second order differential equation is given by Equation 47, 1 P y= x +Czx+C(47) where C1 and C2 are integration constants. For a I x < L,/2, the moment M = Px P(x a)= Pa and [Tim76] d~y El. = M~ = Pa (48) dx~C Solving Equation 48, it can be written that 1=I Pa (49 where C3 and C4 are integration constants. The four integration constants can be determined from the boundary conditions [Tim76]: (i) the slope dy/dx determined from Equations 37 and 39 should be equal at x = a, (ii) the slope dy/dx = 0 at x = L/2, i.e., at the center of the substrate, (iii) at x = a, y determined from Equations 37 and 39 should be equal, and (iv) at x = 0, y = 0 . With these four boundary conditions, Equations 37 and 39 can be simplifies as Equations 410 and 411 respectively, [Tim76] 1 fP Pa(L a) Oxa(0 y= x + x 0xa(0 ElZ 6 2 1 Pa PaL Pa3 y= ~x +x alx< L/2 (411) ElZ 2 2 6 Using Equations 410 and 411, the deflection at x = a and x = L/2 are represented as shown in Equation 412 and 413, Pa2 L 2a\ y,= =  (412) x E, \2 31 y L=~\P 3LZ 4a' (413) 24El Measuring the deflection at x = a, P/II can be obtained as P Ey,, x~a (414) I L( 2a\3 Using above equations the stress on the upper and lower surfaces is given by, EHy,_ cr xpev (415) 2 a3 cr ~EHyx=a 46 "xlowev L 2a6 2a\3 The radius of curvature can also be simplified as, (Equation 417), 1 Pa yxa(417 r El. L 23 The assumptions used to obtain Equations 415 and 416 has been verified by FEM elsewhere [Kwu05] and it holds valid within the deflection range of 0.91mm, which is greater than the deflection used in the piezoresistive measurements in this work. Figure 43 is a simple illustration of how tensile stress is generated on the lower surface and a compressive stress is simultaneously generated on the top one. The exact opposite holds when the positions of the force applying rods are changed as shown in Figure 43 i.e. compressive stress is generated on the lower surface and a tensile stress is simultaneously generated on the top one. Biaxial Stress: ConcentricRing Bending Apparatus Biaxial stress is applied to the channel of the n and p channel MOSFETs using concentric ring bending. Figure 43(a) and 43(b) are pictures of the apparatus used to bend the substrate and an illustration for simulating the biaxial stress. In the case of beams, for uniaxial stress state, even deflections comparable to the plate thickness produce large stresses in the middle plane and contribute to stress stiffing. Hence, one should use large deflection to calculate deflections and stresses in a plate [Kwu05]. This translates to a nonlinear analysis unlike a linear displacement stress relationship associated with uniaxial stress. Finite element analysis (FEM) using ABAQUS that considers both the nonlinearity and orthotropic property of Si has been used from an earlier work [Kwu05] to calculate the biaxial stress from the measured deflections. The stress calibration is illustrated by a simulation of stresses on the top and bottom plates as shown in Figure 44. [Mul99] As shown in Figure 44, on the bottom plane of the substrate, the stress at the center is tensile as expected while, on the top plane, the center stress appears as compressive first, then gradually decreases and finally becomes tensile. This can be explained by the nonlinearity of bending plate with large deflection [Kwu05]. At small deflection (<< the thickness of substrate 0.77 mm), the stress on the top and bottom planes are of nearly the same magnitude but opposite sign, as shown in Figure 44. The magnitude of the tensile stress on the top plane is additive due to substrate stretching while the magnitude of the compressive stress is reduced by the additional tensile stress. The corresponding load is about 4500N or 10001b when displacement reaches 0.89mm. The maximum deflection achieved in this work is about 0.46mm, corresponding to about 1100N or 2501b. Error Analysis In this subsection, the sources of uncertainty in the applied stress will be estimated. There are four major sources of uncertainty in applied uniaxial stress using the fourpoint bending jig shown in Figure 42. They are: a) Uncertainty is the starting point of bending. b) The second source of uncertainty is the micrometer for setting the displacement. c) The third source is the variation of the substrate thickness. The typical thickness of a 12 inches (300mm) wafer is 775+20Cl. The uncertainty in wafer thickness is 0.02mm. d) The uncertainty associated with wafer alignment in the bending apparatus. The wide spread in piezoresistive coefficient values in p type silicon makes the parameter extraction process highly sensitive to measurement errors. The four point bending loading fixture has a number of sources of experimental error and five predominant sources of error can we summarized as [Bea92] a) Weight Measurement Error b) Length Measurement Error c) Loading Symmetry Error d) Beam Rotation Error due to wafer/substrate angle misalignment and e) Probe Force Errors It has been shown that Xn44 is Smaller than (nll + X22z) in ntype silicon [Bea92] and hence this small ratio of (nl + X:22) 2:44 Should make calibration errors much less of a problem with Piezoresistance measurement on nchannel MOSFET. A detailed error analysis has been done by Beaty et al [Bea92] and is beyond the scope of this work. An approach to reducing the errors in the measured values of (nl + X22z) is to avoid trying to determine individual values of A R/R. The following recommendations could help in minimizing error in the measurement technique and more accurate stress calibration a) Wheatstone bridge techniques that can directly measure the quantities (ARx/Rx + ARy/R,) and (ARx/Rx AR,/R,). b) Using four point probing technique instead of a two point probe technique to minimize contact resistance while measuring the Piezoresistance of n and p type resistors. It is often difficult or impossible to accurately measure the contact resistance of the pads when in contact with the probe tips and a fourpoint probing technique is one of the most common methods for measuring resistivity [Sch90]. In the four point probing technique, current is inj ected into the material via the outer two electrodes. The resultant electric potential distribution is measured via the two inner electrodes. By using separate electrodes for the current inj section and for the determination of the electric potential, the contact resistance between the metal electrodes and the material will not show up in the measured results. Because the contact resistance can be large and can strongly depend on the condition and materials of the electrodes, it is easier to interpret the data measured by the fourpoint probe technique than results gathered by twopoint probe techniques. Hence, the resistance measured is more accurate and the source of error arising due to the contact resistance is eliminated. c) Statistical data collection is often the primary solution to obtaining accurate values of piezoresistive coefficients in ptype silicon. [Bea92] Variation of Piezoresistive coefficients from die to die and wafer to wafer should be taken into account for greater confidence in the stress calibration method. Other factors such as temperature, humidity and room conditions are usually kept constant during the experiment and hence their effect on the measurement can be considered negligible. The bending apparatus and the microscopic/stage combination is always kept covered in a walled, closed probe station with no source of light in it and hence optical generation is also not considered as a significant factor to the changes in resistance. Extracting Mobility, Threshold Voltage and Electric Field from Drive Current In this section, the methods of extracting the Fr coefficients from mobility enhancement will be described. The effective mobility will be extracted from the drain current in the linear region (low drain bias) for a longchannel MOSFET. At low drain bias VDS, the linear drain current of an ideal MOSFET can be approximated as IDS f Co L VGS V,)VS ,(418) and the effective mobility p ,f can then be expressed as I, #4, W DS,(419) where Cox is the gate oxide capacitance, W and L are the channel width and length respectively, and VGS and Vr are the gate bias voltage and threshold voltage respectively. The linear region threshold voltage is extracted by drawing a tangent line to the lDSVGS CUTVe at the point where the slope is the largest and extending it to intercept the x axis. The gate voltage at the intercept is defined as the threshold voltage. (Vgs=Vt). This indicates the onset of inversion in the MOSFET channel. Figure 45 is a plot of the lDSVGS CUTVe and threshold voltage extraction using the Keithley 4200SCS Semiconductor Parameter Analyzer. Also, an additional curve proportional to the gradient of the lDSVG CUTVe, iDS/8VGSy defined as the transconductance, is also shown to help to determine the point with the largest slope on the 1DS GS CUTVe. Also, the effective vertical electric field Egfis expressed as [Tau98] E = b n,(420) where 9 is a fitting parameter and equal to 1/3 for holes, Qb is the bulk depletion charge, Q,,, = Co, (VGS V) is the inversion charge, and es is the dielectric constant of silicon. At the interface of gate oxide and silicon channel using the electric displacement continuity [Tau98] equations and the expression for electric field at the surface, the effective vertical field Egf can then be obtained in terms of the depletion and inversion charge densites as E, =,(421) Es Es where Eox is approximated by VGs / tox, which is valid for VDs< the gate oxide capacitance. Extraction of Piezoresistance Coefficients from Drive Current In chapter 2, from equation (21), piezoresistance was defined as Fr=1 R, R, 1 AR X R, Z R, (422) However, it can also be shown that the change in resistance DR/RO is proportional to change in drive current. From Ohm's law V = IR ARch =(423) where Ix is the drain current of the MOSFET after application of stress and Io is the unstressed current. Vyx VI AR = o (424) Ixl AR = (425) Ixlo RoI R AI AR = > = (426) Ix a, x AR AIAc (427) R In cr Of course, here it has been assumed that upon application of stress, the dimensional changes are negligible when compared to the change of resistivity. Hence, all other factors in the mobility expression in equation 419 are constant and get canceled out. This approach has been used in chapter 5 to extract device level piezoresistance coefficients on (100) wafer along the (100) channel direction. Summary In this chapter, the wafer bending experiments to generate uniaxial and biaxial mechanical strain was discussed in detail. The fourpoint bending and concentric ring bending techniques were elaborated upon with the relevant mathematical analysis and simulation results. This was followed by a discussion on uncertainty analysis associated with stresscalibration; the main factors contributing to the uncertainty were identified as starting point of bending, micrometer displacement, wafer misalignment and variation of substrate thickness. The technique used to extract mobility, threshold voltage and electric field from the drive current are described. And the approach used to extract piezoresistance from drive current enhancement in turn, is also described. Chapter 5 will discuss the experimental results obtained and build a physical insight/reasoning into the physics behind the observed piezoresistance coefficients. X', [ {1 0] (a) G ate Chavnnel Direction [100] Out of plane [110] (b) Figure 41. Illustration of Si surface a) b) MOSFET schematic device cross section [100] channel orientation. x", [11 o] ( 001 Si)i (a) Parallel Ridges r b) Top Ring W lt Load Bottom Ring , Support a lt (b) (c) Figure 42. The apparatus, jig, used to apply uniaxial stress to the substrate. (a)In this picture, uniaxial compressive and tensile stresses are generated on the upper and lower surfaces of the substrate respectively. (b) Illustration of calculating the uniaxial stress on a bent substrate. The substrate is simply supported. Four loads applied by cylinders are approximated by four point forces, P. The deflection at any point on the upper surface is designated by y(x). (c) When the parallel ridges are closer on plate A, and farther apart on plate B uniaxial compression is applied. The reverse is true for uniaxial tension. Biaxial Colmpressionte Figure 43 The apparatus, jig, used to apply biaxial stress to the substrate. In this picture, biaxial compressive and tensile stresses are generated on the upper and lower surfaces of the substrate respectively. Illustration of simulating biaxial stress on a bending plate (substrate). The plate (substrate) is simply supported. The deflection at any point on the upper surface is designated by w(r). 500  Bottom Plane 400  S300 Middle Plane 200  100 0. 0.6 ..8 200 _Maximum Displacement Top Plane 300 Used Displacement of Small Ring (mm) (a) Top Plane / Middle Bottom Plane Plane (b) Figure 44. Finite element analysis simulation of the bending plate (substrate) [Kwu05]. (a) The radial stresses at the center of the top, middle, and bottom planes of the bending plate vs. the displacement of the smaller ring are shown. (b) Illustration of top, middle, and bottom planes of the plate. Figure 45. Snapshot of the lDSVGS characteristic and threshold voltage/transconductance extraction from Kiethley 4200SCS Semiconductor Parameter Analyzer. 06/28/2005 21:51:53 M OSFET Th h ld V lt M GM [11111~~ 1.3E04 ... re o o' "'3 'V 'age 'ax~ .............. .2.2E04 1 .2E04 : : 2.OE04 1 .1E04 : 1.8E04 1.0E04 1.6E04 9.0E05 8v .0E05 1 .: (~: : I l 4E04 7.0E05+ 1. :' :: i~ : 2E04 6 .0E05 .C : : : : 1.OE04 4.0E05 3.0E055 : : : : 4.OE05 2.0E05 1.0E0 5 .C .: .~ ~: : : : : .:. . 2 .OE0 5 ThreholdVolage V]:Gate Voltage (V) Data:VT = 4. ODBB2e001 G, CHAPTER 5 EXPERIMENTAL RESULTS AND DISCUSSION Introduction In this chapter, piezoresistance coefficients are revisited. Experimental results from the wafer bending experiment in chapter 4 are discussed. Many previous works have reported piezoresistance coefficients and used them to analyze MOSFET performance under stress [Gal04], [Bra01], [WanO3]. However, most of those works use bulk piezoresistance coefficients directly and only a few of them [Dor73], [Fis03] investigate surface piezoresistance coefficients, which take into account the effect of 2D inversionlayer confinement due to surface electric Hield. In this chapter, the measurements for both bulk Si and MOSFETs are presented. The results show that differences do exist between bulk and confined cases. This is followed by a simple qualitative picture in terms of carrier repopulation, band splitting and scattering rates to explain the differences between device level (MOSFET) and bulk piezoresistance. In order to investigate the piezoresistance effect due to the outofplane stress induced by capping layers, an equivalent inplane biaxial stress has been used to investigate the piezoresistance coefficient of the outofplane direction. It had been shown in chapter 2 that piezoresistance coefficients are mainly determined by the change in carrier mobility with stress. Since inprocess strain is typically introduced longitudinal or perpendicular to the channel, the mechanical stress effect on mobility can be expressed by equation 27: U, where the sub scripts  and I refer to the directions parallel and transverse to the current flow in the plane of the MOSFETs, ~Uis the fractional change in mobility, O and "I are the longitudinal and transverse stresses and nI and ir~ are the piezoresistance coefficients expressed in Pa1 or 1012 cm2/dyne. They can be expressed in terms of the three fundamental cubic piezoresistance coefficients "ir, "i12 and "i44 for a (001) wafer and five coefficients for a (110) wafer. Under uniaxial stress, the normalized mobility variations reduce to [Bra01] ~u s no2 and ~I 2snoP where, n 11 12n Many previous works [Wel94], [Nay94],[Fis96], [Tak96] have pointed out that the main factors that affect mobility are: (1) the change in the averaged longitudinal effective mass due to relative carrier distribution on different valleys (NMOS) or bands (PMOS); (2) the change in intervalley carrier scattering rate due to the energy splitting between different valleys or bands. The following section provides the measured results of the work done and the detailed explanation in terms of the factors mentioned above. Experimental Results Description of devices measured The devices used in the experiment are from 90nm technology having 10Clm channel length and 12A+ thin gate oxide thickness. Kiethley 4200SCS Semiconductor Parameter Analyzer is used to measure the IDsVGs characteristics with gate voltage VGS Swept from 0 to 1.2V for n channel MOSFETS and drain voltage VDS fixed at 50mV. A similar negative bias is applied to p channel devices. The experimental setup for applying stress using fourpoint bending to generate uniaxial loading [Bea92] and measuring the IV curves was shown in chapter 4, Figure 42. The stress was applied by a standard fourpointbending method along Si channel direction. Figure 5 1(a) shows the simple schematic of a (001) surface and figure 51(b) illustrates a MOSFET crosssectional view indicating the inplane and outofplane directions. Concentric ring bending apparatus as illustrated in chapter 4, Figure 43 was used to apply biaxial stress on the devices. Both p and nMOSFETS oriented along the [100] channel were measured. Figure 52 and Figure 53 show the results reported in an earlier work [Kwu05] for pMOSFET Piezoresistance coefficients oriented along the [110] direction on a (001) surface. The corresponding values of piezoresistance are reported for comparison with the [100] data in table 51 and table 52. Figures 54 and 55 how the measured result for nMOSFET [100] channel under longitudinal and transverse uniaxial stress, respectively. These results are averages over 3 sets of measurements. The results of both nMOSFETS and pMOSFETS under inplane biaxial stress are shown in Figure 54. All the measured devices had the same gate length of 10 Clm. The stress range used in the experiments was < 350 MPa, beyond which the silicon strips failed due to edge defects . The longitudinal and transverse piezoresistance coefficients of our work and other works for the (100) and (110) wafers oriented in the [100] and [110] channel directions are summarized in Table 51. For the case of uniaxial transverse stress on a [100] NMOS, surface and bulk values not only differ in magnitude, but also in sign. A qualitative explanation for this observation is explained in the next section. The experimental data also show an almost constant drive current for the case of [100] PMOSFETS on (100) wafer, which is indicated by the low values of their piezoresistance. (9. 10 x 1012 cm2 dynee and 6. 19 cm2/dyne respectively). Piezoresistance coefficients for bulk silicon were found using test 1 square ohm nwell resistors of W/L 46.7 pum The values are reported in Table 53 and compared with the inversion layer piezoresistance coefficients. Figure 55 shows the effect of uniaxial longitudinal tension on a [100] nwell resistor measured on the same wafer as the MOSFETs. Effect of surface electric field In order to clarify the piezoresistance effect of MOSFET, not only the effect of external stress has to be investigated, but also the effect of surface electric field. When adding perpendicular electric field, the band structure of both conduction band and valence band will change. This is because on the application of vertical electrical field under certain types of stress there is strong coupling of the electric field with the wave function [Wang04] [Tho06]. Neglecting spin orbit coupling [Cha72], it is seen that this energy change caused by electric field will enhance or sometimes compensate the effect of stress. Since MOSFETs are working under certain gate voltage, the bulk values of piezoresistance coefficients are not always precise. The effect of this gate field should be considered. Experimental data from this work for nMOSFETs and pMOSFETs is plotted together with Smith's bulk data in Figure 56a and Figure 56b, respectively. After coordinate transformation for an arbitrary channel direction, the values of surface longitudinal and bulk piezoresistance coefficients is shown below ai~ = xl,,, + %i12 1212 21 ~,1,2m 12 22,m + 2xi,1,2 1 (57) 4, = xi,1,2~l~ 2 ~,1,2 12 21 ~i,1,2 22 1im2m, + 2xi,l2 1 2m (58) where 4i is the longitudinal piezoresistance coefficient and 4i is the transverse piezoresistance coefficient. Surface piezoresistance coefficients of pMOSFETS in [100] direction The experimental results showed negligible/very little drive current enhancement for pMOSFETS under longitudinal or transverse compressive stress and hence the low value of their piezoresistance, as see in Table 51. Table 51 also shows that for pMOSFET, the bulk Piezoresistance coefficient values [Smi52] and measured surface piezoresistance upon application of both longitudinal and transverse stresses are very similar in value. This can be explained by the result of 6band k p calculation for valence band shown in Figure 57. From band calculations, we can find that the constant energy contour under strain for bulk Si and MOSFET are similar [Tho04]. The energy structure doesn't change much from bulk to surface, and thus both the carrier repopulation and scattering rate are similar for bulk and surface cases, which indicates that the piezoresistance coefficients are also similar. Surface piezoresistance coefficients of nMOSFETS in [100] direction The experimental result in Figure 56 and Figure 57 shows that the bulk piezoresistance coefficients are quite different from their (100) surface counterparts for the case of uniaxial tension on nMOSFETS. The most obvious differences are: (1) Transverse piezoresistance coefficients have different sign for bulk case and surface case; (2) Surface longitudinal piezoresistance coefficient for [100] channel is much smaller than bulk value, which means that the [100] channel MOSFETs have smaller mobility enhancement than bulk Si. Transverse Tension: A simple qualitative physical reasoning for (1) is developed below. In the case of bulk silicon, the calculation of band splitting caused by strain shows that valleys 1 and 2 have lower energy while valley 3 has higher energy (See Figure 58). Thus most electrons will favorably occupy the lower energy state and distribute on valleys 1 and 2. Since valley 2 has larger longitudinal effective mass, the mobility of bulk Si will decrease(ir~= 53.4). For MOSFET (Figure 44b), under the electric field, valley 1 will have lower energy because of its largest outofplane effective mass (this is explained in greater detail in chapter 3). However, when increasing the transverse tensile stress, band splitting calculations show that valley 1 will have even lower energy while valley 3 will have the highest energy. This will result in a different carrier repopulation scheme than bulk silicon Thus, most electrons will distribute on valley 1. Thus, with increasing strain, the magnitude of bandsplitting increases and valley 3 will move even higher while valley 1, 2 move even lower. This will make the electrons that used to be in valley 3 redistribute to valley 1 or 2. Bands or valleys with a "light" outofplane mass will shift more in energy relative to bands with a "heavy" mass. Since there are more electrons on valley 2 with strain, combined with the fact that valley 2 has the largest longitudinal effective mass, the mobility will decrease a little bit. (But not much since most of the electrons are already at valley 1.) However, with increasing strain, valley 3 and valley 1, 2 split further apart which will cause a reduction in scattering rate. The reduction in scattering rate compensates the larger effective mass and makes the mobility increase a little bit ("1r= 12.77). From the discussion above, we can see that bulk value is not always working for the case of modern day MOSFET. The mobility enhancement largely depends on the crystal symmetry of the certain surface direction. Since piezoresistance coefficients are measured experimentally, we should use devicelevel MOSFET inversionlayer coefficients and not bulk silicon values. Effects of outofplane uniaxial stress There are many ways to induce strain on MOSFETs, such as nitride capping layer, SiGe doped source and drain region or epitaxial SiGe layer. Among these methods, some of them affect the total channel mobility by introducing an outofplane uniaxial stress while some affect the mobility by introducing an inplane uniaxial/biaxial stress. In this work, an inplane biaxial stress is applied to analyze the effect of outofplane uniaxial stress. We know that the strain tensor can be equivalently decomposed into three matrices [Chu95], where e =Strace shear100 shear11 (9 F,= + e, + e, 0 09 1510 Errace 0 E +E +e (510 0 0 E, + E, + E, represents the fractional change of the volume, while Equation 511, 1 0 O, (ex, (F fE= r 0,, Ex, O E5, (511) represents the shear strain created by stress along [100] and [111], respectively. It is important to identify which component of strain contributes to change in mobility. Since hydrostatic strain only shifts the energy position of the bands but does not cause band splitting, it doesn't affect mobility much. In the case of shear strain, it removes symmetry and splits degenerate bands, thus cause the total mobility to change [Chu05]. As a result, when comparing the effects of inplane biaxial stress and outofplane uniaxial stress, we only need to compare the shear strain matrix caused by the stress. It has been shown that [Kwu05] that the inplane biaxial tensile stress Xb, can be represented by an equivalent outofplane uniaxial compressive stress ,,,,, of the same magnitude. The following analysis supports the statement above. For outofplane uniaxial stress [Chu95] [Bra73]: t 0 ex, = z,. = 0 (512) Ex S11 S, S,, O 0 0 0 E, S,, S, S,, O 0 0 0 E, S,, S, S,, O 0 0 (513) fry O O O S44 E, 0 0 0 0 S44 0 0 E 0 0 0 0 0 S44 0 > Ex = Sa, (514) > E = Sit" (515) >e= Sil", (516) :. eheari = 0 (517) :.. e osa0 (S2 S~1)a,, O (518) 0 0 2 ( CS,, S For inplane biaxial stress, [Kwu05][Gua06]: oZ = 0 ax = "w = (519) E, S1 S, S,, O 0 0 a E, S, S, S,, O 0 0 a E. S, S, S,, O 0 0 0 (520) E, 0 0 0 S44 0 0 0 Ey 0 0 0 0 O S4 0 0 E, 0 0 0 0 0 S4 0 >e=(S,, + S',)o (521) > E, = (S,, + S1Z,) (522) > e= 2Szo(523) .". siear111= 0 (524) (S,, S,,)a 0 0 : shearmes 3 S,S3)0(5 0 0 2(S,, S,,zI(525 Equations 518 and 525 show that under the same magnitude of stress, the shear strain caused by these two types of stress are the same in magnitude. This indicates that both stress split bands in the same way and cause the same mobility change. It is worth mentioning that the above qualitative discussion uses bands and outofplane masses and is presented only to help understand the physics. Correct and more accurate physical treatment requires selfconsistent solution to Schrodinger' s and Poisson' s equations to calculate the subband energy shifts in the confined MOSFET inversion layer. Quantummechanical calculations and confinement induced bandsplitting has been calculated with a single valley and many valley model with Schrodinger's equation elsewhere [Ste72], [Fis03],[Cha92] which can be shown to be in agreement with this simple qualitative model that can indeed capture the correct physics. Summary This chapter presented the experimental results along with simple qualitative reasoning. The differences observed between the conventional bulk piezoresistance coefficients and those in the surfaceinversion layer of the MOSFETs were reported. It was shown that is imperative to include the effect of vertical electric field and stress on the carrier mobility to develop insight into the reasons for mobility enhancement in the inversionlayer MOSFET. Results in this work indicate that(1)Transverse piezoresistance coefficients have different sign for bulk case and surface case; (2) Surface longitudinal piezoresistance coefficient for [100] channel is much smaller than bulk value, which means that the [100] channel MOSFETs have smaller mobility enhancement than bulk Si and (3) Uniaxial Compressive stress on pMOSFETS shows little or no change in drive current enhancement. A simple qualitative physical model in terms of carrier repopulation, out of plane masses, bandsplitting and scattering was used to explain the mechanisms responsible. A more numerically intensive and accurate physical treatment requires self consistent solution to Schrodingers and Poisson's equations to calculate the subband energy shifts in the confined MOSFET inversion layer for which the reader is referred elsewhere [Thp06] [Fis04]. Finally, the effects of outofplane uniaxial stress were listed. An inplane biaxial stress can be modeled by an equivalent outofplane uniaxial stress. It was shown that both split the bands in a similar way and hence cause the same mobility change. This fact is particularly useful in modeling processinduced strain applied on the gate of MOSFETS (on which an outofplane stress actually applies through a capping later etc.) by an equivalent in plane biaxial stress that can be measured using existing mechanical waferbending techniques. The next chapter is a summary of the thesis and provides recommendations for future work. X [ {~ 0 ] [110] Figure 51. Si channel orientation, (001) surface and MOSFET schematic device cross section [100] channel orientation. X', [11~0] X,[1 00] (~001 Si ) SThompson et al. 20040. Uniaxial Longitudinal 0.4 Compression A 0.3 Symbol: experimental data Line: model prediction uniaxial Transverse Tension Gallon et al. 2004 ~f~t r0.2 2004 Biaxial 500 250 5 c Stress! / Pa Figure 52. Mobility enhancement vs. stress for six kinds of stresses, biaxial tensile and compressive and uniaxial longitudinal and transverse, tensile and compressive along [110] channel direction. [Kwu05]. The mobility enhancements are extracted at 0.7MV/cm. The solid lines are the model predictions: blue: [Kwu05], orange: Wang et al. [WanO3]. The symbols are experimental data: blue circle: [Kwu05], green triangle: Thompson et al. [Tho04], orange diamond: Wang et al. [WanO4], and purple square: Gallon et al. [Gal04]. Symbol: experimental data Line: model prediction Smith's longitudnal 7I 44,3 tnnsrsenrom I I I longitudinal I[1103 O 500 5 5. E 0 *I transverse 7I 4,,3 Wang et al. Smith's transverse nI ,3alo t l transverse 7I111ol trannsverse 7I ,3o 1.0E09 1.5E09 stress / MPa Figure 53. sicoeffcient of pMOSFETS vs. stress, including longitudinal and transverse ri coeffcients for [110] direction and transverse r ~coeffcient for [001] direction from an earlier work[Kwu05]. The solid lines are the model predictions: blue: [Kwu05], orange: Wang et al. [WanO4]. The symbols are experimental data: blue circle: this work, green triangle: Smith [20], orange diamond: Wang et al. [WanO4], and purple square: Gallon et al. [Gal04]. o  0 50 100 150 200 250 Stress (MPa) Figure 54. Effect of Uniaxial Longitudinal Tensile stress on Bulk ntype resistor and NMOSFETs (indicated as surface tension) oriented along [100] direction on (001) Si. 150 Stress (MPa) 300 Figure 55. Effect of Uniaxial Transverse Tensile stress on Bulk ntype resistor and n MOSFETs (indicated as surface tension) oriented along [100] direction on (001) Si. 150 Stress (M Pa) 300 Figure 56. Effect of Biaxial Tensile and Compressive stress along [100] direction on (001) Si. on and nand pMOSFETs oriented [010] 110 10 9 80 70 [010] 110 10 9 80 70 10 n [100] 17n 90 100 90 100 Figure 57. (100) Surface Piezoresistance coefficient vs. bulk Piezoresistance coefficients (a) nMOSFET (b) pMOSFET. Thicker lines indicate the surface value and thinner lines denote the bulk value. Solid lines are longitudinal piezoresistance coefficients and dashed lines are transverse piezoresistance coefficients. (Courtesy: Chu, Min) [Tho06] Relaxed Si (_ (a) b) Top Band Second Band B axial (01) Uniaxial (001) Unlinxial (11"0) Figure 58 Constant energy contour for bulk Hole constantenergy band surfaces for the top band obtained from sixband k p calculations for common types of 1GPa stresses: (a) unstressed,(b) biaxial tension, (c) longitudinal compression on (001) wafer, and (d) longitudinal compression on (110) wafer (note significant differences in stress induced band warping altering the effective mass). [Tho06] [00lo1] nsile /Varlley 2,3 Without Strain Slight increase in total effective mass SValley 2 Valleyr 1 Rm Decrease in scatteringt~ rate With Strain Figure 59. Illustration of mobility enhancement due to band shift for (100) / [100] NMOS under transverse tensile stress. Tr80s'.l'91Se Tensile Unstrained Ie fetv mass \ Incl eS~SS v'alley 2 ml ~[1 00] Ch~lannel Direction Tl3n! [010] Tei Valley 3 R t Valley 2,3 V4al ley Valley 1I SWithout Strain C With Strain Figure 510. Band shift for (100) / <110> longitudinal tensile stress. Valley 2,3 ~1 o.19mo , S0.315mno Table 51 Measured long channel pMOSFET piezoresistance coefficients in this work (in blue) compared against other works and against Smith's [Smi52] bulk data in units of 1012 cm2/dyne. The data in blue refers to this work. Channel PMOSFET Cll "12 "12 [9mi52] 8.8 [9mi52] 1.1 [Col68] 1 [Col68] 23.8 [Col68] 23.8 [100O] [Uch04] 14.2 [PanO6] 1 [PanO6] 26 [PanOS] 20 [this work] 9.10 6.19 13.2 [Smi52] 71.8 [Smi52] 66.3 [Bra01 a] 50.0 [B ra01 a]45.0 [B ra01 b] 41 .5 [Bra01 b] 38.5 [Bra01 c] 60.0 [B ra1 c]40.0 [[Gal03] 60 [G3al03]08.3 [Gal03] 45.5 [Uch04] 78.8 [11it0] [Col68] 23.8 [Col68] 38.2 [Col168] 38.2 [PanO6] 118 [PanOG] 86 [PanOG] 34 [this work]r 71.7 33.8 20 Table 52 Measured long channel nMOSFET piezoresistance coefficients in this work (in blue) compared against other works and against Smith's [Smi52] bulk data in units of 1012 cm2/dyne. Channel NMOSFET "L "T Blaxial 11cl C12 CI44)y2 (Hy, q 4744)/2 1 [Smi52] 102 [Smi52] 53.4 [Uch04] 63.1 [Ham91] 54.7 [1 00] [PanOG] 59 [PanOS] 10 [PanOS] 64 [this work] 38.515 18.7 24.5 [Smi52] 31.6 [Smi52] 17.6 [Uch04] 46.2 [Uch04] 74 [B ra01 a] 45.0 [Bra01 a] 35.0 [Bra01] 32.0 [Bra01b]~ 26.0 [Bra01 c;] 50.0 [Bra01 c;] 35.0 [G~al03] 42.8 [Gal03] 21.2 [G~al03] 19.7 [110] [Iri04] 39.5 [Deg04] 34.7 [Ham91] 14.7 [Ham9S1] 8.1 [PanO6] 6;7 [PanOG] OS [PanO6] 68 [this wo~rk]5.5 14.5 21.4 Table 53 Measured long channel nMOSFET piezoresistance coefficients along [100] channel compared against a) bulk picoefficients measured on an ntype resistor on the same process and b) against Smith's [Smi52] bulk data in units of 1012 cm2/dyne. NMOSFET [1 00] L CT ("11 12 lr44)/2 (11 ~12~444 2 This Work 38.55 18.7 (Surface%) This Work 24. 5 17.7 (Bulk) [Smi52] 1 02 53.4 Table 54 Measured stress types needed for enhancing n/pMOSFET currents. Device PMOS NMOS Channel [1 00] [110] [1 00] [1101] Longitudinal Compressive Tensile Tensile Neg. change ++ ++ +++ Transverse Compressive Tensile Tensile Tensile Neg. change +++ ++ ++ CHAPTER 6 SUMMARY AND FUTURE WORK Summary The work presented in this thesis is motivated by the fact that strain is being adopted in all modern day logic technologies to achieve performance improvement in CMOS technologies and the need for empirical device level piezoresistance coefficients by industry to quantify mobility enhancement. In Chapter 1, strain is introduced as a vector to extend Moore's law and continue historical MOSFET performance enhancement. The relation between stress and strain is also outlined. For isotropic solids strain is a linear function of stress. The two are related to each other through the elastic properties of Si. The relation between the piezoresistive effect and strained silicon MOSFET was elaborated in chapter 2, which serves as a foundation for understanding the experimental results.. This is followed by a discussion on the need of piezoresistance coefficients and their relevance to understand strainenhanced electron and hole mobility is presented in chapter 2. Appropriate numerical analysis of the effect of MOSFET carrier mobility under stress in terms of piezoresistance coefficients is provided. In chapter 3, the underlying physics of strained silicon MOSFETs has been presented. In equilibrium state silicon is isotropic in nature and strain introduces advantageous anisotropy in silicon by altering the valence and conduction band structures and/or scattering rates. Favorable carrier repopulation and reduced intervalley scattering result in higher mobility enhancement for unaixal stress compared to biaxial stress, and this enhancement is maintained even at high vertical electric field. SiGe in the source and drain, dual stress liners and stress memorization techniques have been introduced into stateof theart MOSFETS. Mechanical stress can be introduced in the channel of a device to measure the change in the performance of device i.e. mobility. A discussion of the wafer bending techniques used in the experimental setup of this work has been provided in chapter 4. The fourpoint bending and concentric ring bending techniques are elaborated upon with the relevant mathematical analysis and simulation results. The method to extract piezoresistance coefficients from drive current enhancement is also presented. The change in mobility is studied for different kind of stress types namely Uniaxial and Biaxial. Discussion on uncertainty analysis associated with stress calibration has been presented. The main factors contributing to the uncertainty are identified as starting point of bending, micrometer displacement, wafer misalignment and variation of substrate thickness. Chapter 5 presented the experimental results along with simple qualitative reasoning. The differences observed between the conventional bulk piezoresistance coefficients and those in the surfaceinversion layer of the MOSFETs were reported. It was shown that is imperative to include the effect of vertical electric field and stress on the carrier mobility to develop insight into the reasons for mobility enhancement in the inversionlayer MOSFET. Results in this work indicate that: (1)transverse piezoresistance coefficients have different sign for bulk case and surface case; (2) surface longitudinal piezoresistance coefficient for [100] channel is much smaller than bulk value, which means that the [100] channel MOSFETs have smaller mobility enhancement than bulk Si and (3) uniaxial compressive stress on pMOSFETS shows little or no change in drive current enhancement. A simple qualitative physical model in terms of carrier repopulation, out of plane masses, bandsplitting and scattering was used to explain the mechanisms responsible. A more numerically intensive and accurate physical treatment requires self consistent solution to Schrodingers and Poisson's equations to calculate the subband energy shifts in the confined MOSFET inversion layer for which the reader is referred elsewhere [Thp06] [Fis04]. Finally, the effects of outofplane uniaxial stress were listed. An inplane biaxial stress can be modeled by an equivalent outofplane uniaxial stress. It was shown that both split the bands in a similar way and hence cause the same mobility change. This fact is particularly useful in modeling processinduced strain applied on the gate of MOSFETS (on which an outofplane stress actually applies through a capping later etc.) by an equivalent in plane biaxial stress that can be measured using existing mechanical waferbending techniques. Today strain is being adopted in all high performance logic technologies. SiGe in the source and drain, dual stress liners and stress memorization techniques have been introduced into stateoftheart MOSFETS. Strain will continue to scale well into future logic technology generations as the MOSFET enters the ballistic regime. Future Work In Chapter 1, it was established that strain will continue to scale as the MOSFET enters into the ballistic regime. It will be interesting to investigate if it would be possible to break the performance limit even when mobility saturates, through other strain effects like band splitting and carrier repopulation. The need for more accurate stress calibration, especially for biaxial stress is essential. A strain gage used to directly measure the surface strain instead of force could eliminate somec calibration errors and it is recommended as future work. 4 point probing technique that eliminates contact resistance instead of the 2 point probing technique for resitors is also recommended. Also, it would interesting to investigate the piezoresistance effects as a function of temperature and doping concentration and it is recommended as future work. LIST OF REFERENCES [Aba01] "ABAQUS/CAE." Providence, Rhode Island: ABAQUS, Inc., 2001. [Bai04] P. Bai C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S.H. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, and M. 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Mogab, "Embedded SiGe S/D PMOS on Thin Body SOI Substrate with Drive Current Enhancement," in Proc. Symp. VLSI Technology 2005, pp. 2627, June 2005. BIOGRAPHICAL SKETCH Nidhi Mohta was born on April 12, 1983, in Madhya Pradesh, India. She has loving parents, Deepali and Mahendra Mohta. She received her Bachelor of Electronics and Communication Engineering in 2004 at University of Madras, Chennai, India. Her hobbies include reading, dancing, and astronomy. Nidhi Mohta joined the Master of Science program in the Electrical and Computer Engineering Department at University of Florida in fall 2004. She has been working as a research assistant with Dr. Scott Thompson and the SWAMP Center since 2005. She is currently interning with the Process Technology and Collateral Team in Intel Incorporation, Folsom, California. 