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Fully Integrated CMOS Receiver for a 24-GHz Single Chip Radio-MicroNode

Permanent Link: http://ufdc.ufl.edu/UFE0017517/00001

Material Information

Title: Fully Integrated CMOS Receiver for a 24-GHz Single Chip Radio-MicroNode
Physical Description: 1 online resource (141 p.)
Language: english
Creator: Su, Yu
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: antenna, cmos, linearity, lna, lpf, mixer, nf, synthesizer, vga
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The speed improvement of silicon devices has made implementation of silicon integrated circuits operating at 10GHz and higher feasible. This trend has made it possible to integrate a single chip radio using on-chip antennas. This had led to the proposal of a 24-GHz true single chip CMOS radio. This Ph.D. work demonstrated a fully integrated receiver chain, and a transceiver incorporating the receiver, transmitter designed by C. Cao and the frequency synthesizer designed by Y. Ding. Twenty-four gigahertz single-ended and differential LNAs have been demonstrated. With 1.2-V supply, the single-ended LNA has 6-dB gain and 5-dB noise figure consuming 2.3-mW power. The differential LNA has 6-dB gain and ~5.3-dB while consuming 4-mW power. From these, it is found that substrate resistance and parasitic capacitance of CMOS devices significantly degrade the gain and power efficiency of LNA. By adding an inductor at the gate of common gate stage of a cascode amplifier, negative resistance can be generated to increase the output impedance and transconductance of LNA. A 26-GHz LNA using this topology achieves 8.4-dB gain and ~5-dB noise figure while only consuming 0.8-mW power. A 20-GHz RF front-ended including an LNA and a mixer is demonstrated. It achieves 9-dB conversion gain and 6.6-dB noise figure. This RF front-end only consumes 12.8-mW power from a 1.5-V supply. Using this RF front-end with an on-chip antenna as a receiver, AM signal transmitted by an on-chip antenna 5m away has been successfully picked up and down-converted to intermediate frequency (IF). For the first time, this demonstrated the feasibility of a pair of ICs communicating with each other over free space using on-chip antennas. To increase receiver gain, an IF amplifier is added to the RF front-end. It achieves 29.5-dB gain consuming 17.7-mW power from a 1.5-V supply. These results showed that it is feasible to implement low power 24-GHz communication devices with reasonable performance using a 130-nm CMOS technology. A fully integrated receiver is demonstrated. It consists of an RF front-end, IF amplifier, passive mixer, variable gain amplifier (VGA) and lower pass filter (LPF). It utilizes dual down conversion which requires one 21.3-GHz frequency synthesizer and a divide-by-8 circuit to generate the second local oscillator signal. A distributed transmitter/receiver switch is used to share the use of one on-chip antenna by the receiver and transmitter. A wireless communication link is demonstrated using fully integrated receiver and transmitter. A ~21.7-GHz single tone generated by the transmitter is successfully picked up and down-converted to baseband by the receiver which is 5m away from the transmitter. This demonstration is a great step toward the realization of a single chip radio.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Yu Su.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: O, Kenneth K.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0017517:00001

Permanent Link: http://ufdc.ufl.edu/UFE0017517/00001

Material Information

Title: Fully Integrated CMOS Receiver for a 24-GHz Single Chip Radio-MicroNode
Physical Description: 1 online resource (141 p.)
Language: english
Creator: Su, Yu
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: antenna, cmos, linearity, lna, lpf, mixer, nf, synthesizer, vga
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The speed improvement of silicon devices has made implementation of silicon integrated circuits operating at 10GHz and higher feasible. This trend has made it possible to integrate a single chip radio using on-chip antennas. This had led to the proposal of a 24-GHz true single chip CMOS radio. This Ph.D. work demonstrated a fully integrated receiver chain, and a transceiver incorporating the receiver, transmitter designed by C. Cao and the frequency synthesizer designed by Y. Ding. Twenty-four gigahertz single-ended and differential LNAs have been demonstrated. With 1.2-V supply, the single-ended LNA has 6-dB gain and 5-dB noise figure consuming 2.3-mW power. The differential LNA has 6-dB gain and ~5.3-dB while consuming 4-mW power. From these, it is found that substrate resistance and parasitic capacitance of CMOS devices significantly degrade the gain and power efficiency of LNA. By adding an inductor at the gate of common gate stage of a cascode amplifier, negative resistance can be generated to increase the output impedance and transconductance of LNA. A 26-GHz LNA using this topology achieves 8.4-dB gain and ~5-dB noise figure while only consuming 0.8-mW power. A 20-GHz RF front-ended including an LNA and a mixer is demonstrated. It achieves 9-dB conversion gain and 6.6-dB noise figure. This RF front-end only consumes 12.8-mW power from a 1.5-V supply. Using this RF front-end with an on-chip antenna as a receiver, AM signal transmitted by an on-chip antenna 5m away has been successfully picked up and down-converted to intermediate frequency (IF). For the first time, this demonstrated the feasibility of a pair of ICs communicating with each other over free space using on-chip antennas. To increase receiver gain, an IF amplifier is added to the RF front-end. It achieves 29.5-dB gain consuming 17.7-mW power from a 1.5-V supply. These results showed that it is feasible to implement low power 24-GHz communication devices with reasonable performance using a 130-nm CMOS technology. A fully integrated receiver is demonstrated. It consists of an RF front-end, IF amplifier, passive mixer, variable gain amplifier (VGA) and lower pass filter (LPF). It utilizes dual down conversion which requires one 21.3-GHz frequency synthesizer and a divide-by-8 circuit to generate the second local oscillator signal. A distributed transmitter/receiver switch is used to share the use of one on-chip antenna by the receiver and transmitter. A wireless communication link is demonstrated using fully integrated receiver and transmitter. A ~21.7-GHz single tone generated by the transmitter is successfully picked up and down-converted to baseband by the receiver which is 5m away from the transmitter. This demonstration is a great step toward the realization of a single chip radio.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Yu Su.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: O, Kenneth K.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0017517:00001


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0ab64945f357500ad2d71c92ce81d7bc
97a461cf2fce2d7a7eb8f1433eccb1a473f8a1a2







FULLY INTEGRATED CMOS RECEIVER FOR
A 24-GHZ SINGLE CHIP RADIO-MICRONODE




















By

Yu Su


















A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2009




































O 2009 Yu Su



































To my parents and my wife









ACKNOWLEDGMENTS

I would like to begin by thanking my advisor, Professor Kenneth K. O, whose constant

encouragement and patient guidance provided a clear path for my research. His great vision led

to success of our proj ect. I would like to thank Dr. Robert M. Fox for his guidance in my

baseband analog circuitries design. I would also like to thank Dr. Khai Ngo and Dr. Gloria J.

Wiens for helpful suggestions and their time commitment in serving on my committee.

Much appreciation goes to Defense Advanced Research Proj ects Agency (DARPA) for

funding this work. My special thanks go to Albert Yen at UMC Inc. and Geoff Dawe at Bitwave

Semiconductor Inc. for chip fabrication. Also I would like to thank Dr. Jenshan Lin for the use of

his group's measurement equipment. Much appreciation goes to my former TI colleagues, Siraj

Akhtar and Chih-Ming Hung for their encouragement and help to finish this dissertation.

I have been quite fortunate to have worked with my colleagues in the C1Node proj ect,

Changhua Cao, Yanping Ding, and Jau-Jr Lin, whose helpful discussions, recommendations and

friendship have speeded up my research. I fondly remember the "crazy" times during tapeouts,

struggles and excitements during measurements. It is a great 4-year period to work with them. I

wish them best in their future career and I believe they will achieve great success. Li Gao, her

elder-sister-style made me get quickly adapted to the new environment when I joined the

SIMICS research group. Also, I would like to thank the other former and current colleagues in

SIMICS group for their helpful advice and discussions. Some names are listed here: Seong-Mo

Yim, Dong-Jun Yang, Zhenbiao Li, Xiaoling Guo, Ran Li, Haifeng Xu, and Chikuang Yu.

Aravind. Sugavanam, Jie Chen, Eunyoung Seok, Kwangchun Jung, Swaminathan Sankaran,

Chuying Mao, Seon-Ho Hwang, Ning Zhang, Shashank, Myoung Hwang, Wuttichai

Levdensitboon, Zhe Wang, Dongha Shim and Kyujin Oh. I also like to thank my friends outside









of the research group. Ashok K. Verma and Xiuge Yang also worked with us on the CLNode

proj ect. Ming He and Xiaoxiang Gong shared the same passion with me for Gator basketball and

football. Tao Zhang, Qizhang Yin, Xiaoqing Zhou and Xueqing Wang had nice BBQ parties

with us. Yanming Xiao and Changzhi Li helped me a lot on using measurement equipment.

I am grateful to my parents for their love and encouragement since childhood. I would like

to thank my wife, Cuiwei Wang. Her unconditional support and care enabled me to focus on

research work over the long period of time. Finally, I would like to thank my two lovely

daughters, ShiYing Su and XinYan Su for happiness and j oy they bring to me.












TABLE OF CONTENTS


page

ACKNOWLEDGMENT S .............. ...............4.....


LIST OF TABLES ................ ...............8............ ....


LI ST OF FIGURE S .............. ...............9.....


AB S TRAC T ............._. .......... ..............._ 13...


CHAPTER


1 INTRODUCTION ................. ...............15......... .....


1.1 Low Power Wireless Network ................. ...............15......... ....
1.2 On-Chip Antenna ................. ...............16...............
1.3 CLNode System .............. ...... ...............17.
1.4 Organization of the Dissertation ................. ......... ...............19.....


2 CINODE SY STEM OVERVIEW ................. ...............21................

2.1 Introduction .................. ... ......... ......... .............2
2.2 Super-Heterodyne and Homodyne Receiver............... ...............22
2.3 Baseline PHY ............... ... .. ........ ........... ... ...........2
2.3.1 Direct Sequence Spread Spectrum (DS/SS)...................................... 2
2.3.2 Differential Chip Detection of Direct Sequence Spread Spectrum (DS/SS-
DC D ) ................ .... ....... ...............3.. 0....
2.3.3 Modulation Format .............. ...............34....
2.4 Summ ary .............. ...............37....


3 LOW NOISE AMLIFER DESIGN .............. ...............39....


3.1 Introduction .............. ... ... __ ...............39...
3.2 Noise Sources in MOS Device............... ...............39.
3.3 Topologies of LNAs ................. ...............43................
3.3.1 Gain of CS-LNA .............. ...............45....
3.3.2 Noise Factor of CS-LNA .............. ...............47....
3.3.3 Noise Factor of Cascode Amplifier ................. ...............50...............
3.4 24GHz CMOS LNA Implementation .............. ...............53....
3.4.1 A 24-GHz Single-Ended CMOS LNA................ ...............53..
3.4.2 A 24-GHz Differential CMOS LNA ................. ...............57...............
3.4.3 Device Characteristic ............... ..... .... .... .........6
3.4.4 A 26-GHz CMOS LNA with Negative Impedance .............. .....................6
3.5 Summ ary .............. ...............70....


4 20GHZ RF FRONT END DESIGN .............. ...............72....












4.1 Introduction .............. ....._.. ...............72......
4.2 Active M ixer ............... ...............72....
4.2.1 Conversion Gain .............. ...............74....
4.2.2 Noise in Active Mixer ................. ....._. ._ ...............76.....
4.2.3 Thermal Noise from Switching Pair .............. ...............77....
4.3 A 20-GHz Font End with On-chip Antenna .............. .... .... ...... ............8
4.4 A 20-GHz RF Front End Including LNA, Mixer and IF Amplifier .............................89
4.5 Sum m ary .............. ...............91....

5 BUILDING BLOCKS OF RECEIVER ................. ...............93........... ...


5.1 Introduction ................. ...............93.................
5.2 Passive M ixer ................. ............... ...............93......
5.3 Variable Gain Amplifier (VGA) .............. ...............95....
5.4 Baseband Low Pass Filter (LPF) ................. ...............98...............
5.5 Frequency Divider................... ..............10
5.6 Image Rej section Filter in LNA ................. ...............108........... ..
5.7 Integration of Transceiver ................. ...............110...............
5.8 Sum m ary ................. ...............113......... ......


6 FULLY INTEGRATED RECEIVER AND WIRELESS LINK DEMONSTRATION OF

CINODE TRANS CEIVER ................. ...............114................

6.1 Introduction ............... .. ... .......... ........ .... ............11
6.2 Receiver Measurement Using External LO Source ................. .........................114
6.3 Receiver Measurement Using On-chip Frequency Synthesizer .............. .................121
6.4 Wireless Communication Link Demonstration ................. .............................125


7 SUMMARY AND FUTURE WORK .............. ...............129....


7.1 Summary ...................... ...............129
7.2 Suggested Future Work ................. ...............13. 0..............


APPENDIX DERIVATION OF NOISE FACTOR OF CS-LNA ................. ............ .........132


REFERENCE S .............. ...............13 4...


BIOGRAPHICAL SKETCH ................. ...............141......... ......











LIST OF TABLES

Table page

2-1 Link bud get of CINode ............... ...............37....

3-1 Summary of performance of single-ended and differential LNA. .................. ...............61

3-2 Performance comparison between LNAs above 20GHz. ................... ............... 7

4-1 Performance of the RF front-end ..........._......._ ....__....._ ...............86

4-2 Performance comparison between our down-converter and the one in [75]. ....................91

5-1 Measured and simulated in-band loss and corner frequency of the LPF. ................... .....107

6-1 Power table of the receiver. ................ ...............119..._.... ....

6-2 RX performance summary. .............. ...............121....

6-3 Frequency synthesizer performance summary ................. ...............122........... ...











LIST OF FIGURES


Fiare page

1-1 A conceptual C1Node system. ............. ...............18.....

1-2 Typical C1Node device size ................. ...............18........... ...

2-1 Super-heterodyne structure. ............. ...............23.....

2-2 Direct conversion receiver. ............. ...............24.....

2-3 Simplified RF transceiver block diagram. ............. ...............25.....

2-4 Receiver frequency plan. ............. ...............26.....

2-5 BER for BPSK with frequency offset. .............. ...............27....

2-6 BPSK modulation and BPSK spreading scheme. ............. ...............28.....

2-7 D S/S S BP SK system block diagram ............ ..... ._ ...............30

2-8 Differential chip detection block diagram. ............. ...............31.....

2-9 ReurdE oatBRo104..............3

2-10 Block diagram of 16-ary orthogonal modulation ................. ...............34..............

2-11 16-ary orthogonal detector with DCD. ................ ...............35........... ..

2-12 AWGN performance in 16-ary orthogonal detector. ............. ...............36.....

3-1 Cross section of a MOSFET channel consisting of a gradual channel region (I) a
velocity saturation region (II). ............. ...............39.....

3-2 Induced Gate Noise............... ...............42.

3-3 Two types of LNA topologies ................. ...............44...............

3-4 CS-LNA and its equivalent circuit ................. ...............46...............

3-5 Output resistance effect on gain ................. ...............47...............

3-6 Noise sources in CS-LNA ................. ...............48........... ...

3-7 Schematic of cascode amplifier. ............. ...............50.....

3-8 Schematic calculating output noise current from common-source stage...........................51











3-9 Noise contribution from a cascode amplifier ................. ...............52........... ..

3-10 Single-ended LNA. ............. ...............55.....


3-11 S-parameter of the LNA ................. ...............56........... ...


3-12 Noise figure of the LNA. ................ ...............56...............

3-13 IIP3 measurement of the LNA ................. ...............57...............


3-14 Differential LNA................ ...............58..


3-15 S-parameters of differential LNA. ............. ...............59.....

3-16 NF of the differential LNA. ............. ...............59.....


3-17 IIP3 of the differential LNA. ............. ...............60.....

3-18 Sub state network of a MO SFET ................. ...............61..............


3-19 Extracted Rdb and Cdb............. ............6


3-20 Rsub effect on output resistance of a cascode amplifier ......... ................. ...............63

3-21 Schemes for generating negative resistance. ............. ...............64.....


3 -22 The LNA with an inductor at the gate of M2 ................. ...............66...........


3-23 S-parameters and NF measurement of the LNA ................. ...............67..............


3-24 Stability circles............... ...............68

3-25 IIP3 of the LNA. ................ ......................... .................. ............69


4-1 Switching mode of mixer ................. ...............73........... ...

4-2 Active mixer ................. ...............73........... ....


4-3 Mixer gain drop from ideal switching. ............. ...............76.....

4-4 Frequency translation of white noise in a transconductor. ................ .......................77


4-5 Time varying transconductance G(t). ............. ...............78.....


4-6 NF vs. LO power of Mixer. ............_......___ ...............80.

4-7 Schematic of LNA and Mixer ................. ...............81...............


4-8 Die micrograph and antenna cross section ................. ...............82.............




10











4-9 Reflection coefficient at IF and RF ports ................. ...............83..............

4-10 The Gain and NF vs. Frequency plots for 20-GHz downconverter ................. ...............84

4-11 Linearity of down-converter. ............. ...............85.....

4-12 Interchip wireless communication over free space. .............. ...............87....

4-13 Received spectrum. ............. ...............88.....

4-14 IF amplifier schematic. ............. ...............89.....

4-15 A Front-end with an IF amplifier............... ...............9

4-16 Measured matching properties at IF and RF ports ................. ............... ......... ...90

4-17 Power gains at input and image frequencies. .............. ...............91....

5-1 Diagram of Clnode receiver. ............. ...............93.....

5-2 Passive mixer. ............. ...............94.....


5-3 Gain vs. LO power in a passive mixer. .............. ...............94....

5-4 Schematic of the VGA and its basic amplification stage ................. ................ ...._.95

5-5 Gain control scheme. ............. ...............96.....

5-6 Measurement setup of the VGA using differential amplifiers as Baluns. .................. .......97

5-7 VGA gain vs. gain control step ................. ...............98........... ..

5-8 Capacitive voltage divider in the configuration for gain step 4 ................. ................ ..98

5-9 Half-sine and 2nd-order Butterworth filter frequency response. ............. .....................99

5-10 A)A lossy biquad and B)its equivalent circuit ................. ...............100.............

5-11 Schematic of the LPF ................. ...............101........... ...


5-12 LPF V out and Idd vs. Vgme........ ...............102

5-13 N ear-square-law of Idd vs. V gme. ............. ...............103

5-14 Frequency response and tuning of LPF. ................ ................. ...................104

5-15 LPF cut-off frequency vs.Sqrt(Idd)........ ...............104

5-16 LPF including device output resistance. ............. ...............105....











5-17 Simulated LPF IP3............... ...............106..

5-18 Block diagram of the 2: 1 static frequency divider ................. ................ ......... .10

5-19 Schematic of the 2: 1 static frequency divider ................. ...............108........... .

5-20 2-stage LNA with notch filters at the image frequency. ................. ................10

5-21 Input impedance of the notch filter vs. frequency. ................ ................ ......... .109

5-22 Distributed switching for the receiver and transmitter. ................ .......... .............110

5-23 A) Integration of the frequency synthesizer, transmitter and receiver. ................... .........1 12

5-24 Inverter chain is used to drive the passive mixer ................. ...............113............

6-1 Die micrograph of the transceiver and baseband processor ................. .....................1 15

6-2 Receiver board and die wire bonding. ................ ...............115........... ..

6-3 Receiver baseband signal output spectrum. ................ ...............117..............

6-4 Gain vs. frequency of the receiver with an on-chip antenna connected to the RF input
pad s. .............. .. ...............117......... ......

6-5 Receiver noise floor illustrating the filter characteristic ................. .......................118

6-6 Frequency response of RX gain and NF. ............. ...............120....

6-7 IP3 measurement of whole RX chain. ................ ........................ ..............120

6-8 PLL-based frequency synthesizer. .............. ...............121....

6-9 The output spectrum the RX when the LO is driving from synthesizer. .........................123

6-10 The output spectrum of RX when the LO is generated using an on-chip synthesizer.....123

6-11 Phase noise of the baseband signal. ............. ...............124............. ...

6-12 Baseband power versus different VGA gain setting ................. ......... ................1 24

6-13 Wireless communication link between the transmitter and receiver. ............. ................126

6-14 Transmitter on board and die wirebonding. .............. ...............126....

6-15 Wireless link measurement setup and environment ................. ................. ........ 127

6-16 Receiver output spectrum. ............. ...............127....

A-1 Noise sources in CS-LNA. ................ .............132............ ...









Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

FULLY INTEGRATED CMOS RECEIVER FOR
A 24-GHZ SINGLE CHIP RADIO-MICRONODE

Yu Su

May, 2009

Chair: Kenneth K. O
Maj or: Electrical and Computer Engineering

The speed improvement of silicon devices has made implementation of silicon integrated

circuits operating at 10GHz and higher feasible. This trend has made it possible to integrate a

single chip radio using on-chip antennas. This had led to the proposal of a 24-GHz true single

chip CMOS radio. This Ph.D work demonstrated a fully integrated receiver chain, and a

transceiver incorporating the receiver, transmitter designed by C. Cao and the frequency

synthesizer designed by Y. Ding.

Single-ended and differential LNAs operating at 24GHz have been demonstrated. With

1.2-V supply, the single-ended LNA has 6-dB gain and 5-dB noise figure consuming 2.3-mW

power. The differential LNA has 6-dB gain and ~5.3-dB while consuming 4-mW power. From

these, it is found that substrate resistance and parasitic capacitance of CMOS devices

significantly degrade the gain and power efficiency of LNA. By adding an inductor at the gate of

common gate stage of a cascode amplifier, negative resistance can be generated to increase the

output impedance and transconductance of LNA. A 26-GHz LNA using this topology achieves

8.4-dB gain and ~5-dB noise figure while only consuming 0.8-mW power.

A 20-GHz RF front-ended including an LNA and a mixer is demonstrated. It achieves 9-

dB conversion gain and 6.6-dB noise figure. This RF front-end only consumes 12.8-mW power

from a 1.5-V supply. Using this RF front-end with an on-chip antenna as a receiver, AM signal









transmitted by an on-chip antenna 5m away has been successfully picked up and down-converted

to intermediate frequency (IF). For the first time, this demonstrated the feasibility of a pair of ICs

communicating with each other over free space using on-chip antennas. To increase receiver

gain, an IF amplifier is added to the RF front-end. It achieves 29.5-dB gain consuming 17.7-mW

power from a 1.5-V supply. These results showed that it is feasible to implement low power 24-

GHz communication devices with reasonable performance using a 130-nm CMOS technology.

A fully integrated receiver is demonstrated. It consists of an RF front-end, IF amplifier,

passive mixer, variable gain amplifier (VGA) and lower pass filter (LPF). It utilizes dual down

conversion which requires one 21.3-GHz frequency synthesizer and a divide-by-8 circuit to

generate the second local oscillator signal. A distributed transmitter/receiver switch is used to

share the use of one on-chip antenna by the receiver and transmitter. A wireless communication

link is demonstrated using fully integrated receiver and transmitter. A ~21.7-GHz single tone

generated by the transmitter is successfully picked up and down-converted to baseband by the

receiver which is 5m away from the transmitter. This demonstration is a great step toward the

realization of a single chip radio.









CHAPTER 1
INTRODUCTION

1.1 Low Power Wireless Network

The rapid evolution of wireless communications technology has resulted in a strong drive

toward implementation of high-performance radio frequency (RF) circuits in silicon, particularly

Complementary Metal-Oxide-Semiconductor (CMOS), for its lower cost and higher level of

integration. With low cost and low power advantage of CMOS, RF products incorporating the

standards for cellular phone and ultra wide band standard, as well as Bluetooth and 802.11x for

wireless local area network (WLAN) applications are being developed and deployed.

It is now widely acknowledged that these standards are not well suited for a wide range of

sensor network applications due to the high cost of nodes as well as the high power consumption

resulting from complex protocols. To address this, a standard called ZigBee [1] is proposed. Its

main goal is to standardize and enable inter-operability of products within a home or a building.

The ZigBee standard builds on the physical communication layers specified by the IEEE

802.15.4 standard [2]. The ZigBee defines the network, security and application software. Zigbee

networks operate in the 2.4-GHz Industrial-Scientific-Medical (ISM) band, the same band as

802.11lb WLAN networks, Bluetooth and others.

ZigBee networks better address the unique needs of sensors and control devices. Sensors

and controls do not need high bandwidth. However, they do need low latency and very low

energy consumption for long battery life. The devices are idle for most time. The network

supports data transmission rates up to 250kbps at a range of up to 30 meters. This data rate is

lower than the 802.11lb WLAN (11 Mbps) and Bluetooth (1 Mbps) devices, but the power

consumption of Zigbee devices is significantly lower. Users can expect batteries to last many

months or even years.









1.2 On-Chip Antenna

For the low power wireless network applications, it is possible to implement a single chip

radio which packages both baseband electronics and radio in a single chip [3]. To totally

eliminate the potentially costly external transmission line connections, integration of antennas is

desirable if their performance is adequate. The research on fabrication of antennas on semi-

conducting substrate goes back to the late 1980's. These early efforts included an on-chip

antenna integrated with a 95-GHz IMPATT diode oscillator on a high resistive silicon substrate

[4] and an on-chip antenna integrated with a 43.4-GHz IMPATT diode oscillator on a GaAs

substrate [5]. High resistive silicon substrates have also been used to fabricate MEMS based

antennas operating at 90 to 802GHz [6]. However, the use of IMPATT diode circuits limits the

types of radios that can be built. Furthermore, the substrates are not compatible with the low cost

mainstream silicon process technologies. The speed improvement of silicon devices has made

implementation of silicon integrated circuits operating at 10GHz and higher feasible. At 10GHz,

a quarter wave dipole antenna needs to be only 7.5 and ~2.2 mm in free space and silicon,

respectively, making integration of an antenna for wireless communication possible.

On-chip antennas could potentially be used to relieve the bottleneck associated with global

signal distribution inside integrated circuits. The first proposed uses of an on-chip antenna

fabricated in a conventional foundry process are clock distribution [7] and data communication

[8], [9]. Several transmitters [10], [l l] and receivers [l l] with on-chip antennas for wireless

clock distribution have been demonstrated. Signal from a transmitter incorporating a 10-GHz

VCO, buffer and antenna fabricated in a BiCMOS technology [15] has also been picked up by an

external horn antenna. Recently, a clock transmitter [16] and receiver [17] using 2-mm on-chip

zigzag antennas for clock distribution have achieved 5-ps peak-peak jitter. These suggested the










potential to communicate over free space using true single chip CMOS and BiCMOS radios with

on-chip antennas.

Having the ability to form antennas on-chip with almost no cost penalty provides greater

design flexibility. It is no longer necessary to force the antenna interface to be at 5002 and share

the transmitting and receiving antennas. Each interface could be independently optimized. The

receiving antenna can be made to have impedance higher than 5002 which gives better noise

performance. The impedance of transmitting antenna can be made lower than 5002, releasing the

high Q requirement of matching network which can reduce the output signal swing at given

output power. Especially in a class E power amplifier, the lower voltage swing reduces the

voltage stress on devices. Using passive on-chip components in combination with the freedom to

choose impedance level should allow integration of tunable bandpass filters with the relax

performance requirements.

1.3 yNode System

Exploiting this new possibility, a sensor node called C1Node, which incorporates on-chip

antennas, a transceiver, a digital baseband processor, a sensor, and potentially even a battery, has

been proposed [18].

Figure 1-1 shows the conceptual diagram of a IrNode. It is capable of 100kbps wireless

transmission and reception at ~24GHz over a short distance (typically 1 to 5 meters, and the

range can be extended to ~30m at the cost of increased transmit power). Groups of C1Nodes can

form self-organizing wireless communication networks that signal in a wide frequency band

(100MHz) at amplitude below the background noise level. Such nodes could help to accelerate

the realization of Smart Dust vision [19].










The C1Node packaging has the potential of being very simple. The SoC CMOS chip

communicates off-chip via wireless signaling. The only wire connections are battery

connections. A C1Node package only needs to provide mechanical and chemical protection, while

allowing RF signal transmission. In contrast, a device with an off-chip antenna must have a

package providing well-controlled impedance connection to external passive components

including an antenna. Since C1Nodes are operating at ~24GHz, all the passive components can be

easily integrated on-chip. A C1Node network can be viewed as a modified Zigbee network

operating at 24GHz.


Figure 1-1. A conceptual IrNode system.


Figure 1-2. Typical C1Node device size.


BATTERY


Size 5A and 10
Batteries










When packaged with a battery, a CLNode can be as small as ~3 mm x 3 mm x 5 mm can

have a mass less than 20 milligrams, and has a battery life of 1 to 30 days. The size of CLNode

device is usually limited by the battery dimensions. Presently, an m&m sized communication

node shown in Figure 1-2 is being developed.

1.4 Organization of the Dissertation

This Ph.D work focuses on the design and characterization of receiver chain for the 24-

GHz radio, The goals of this work are to develop the receiver in main-stream CMOS technology

including an on-chip antenna and integrate it with a transmitter designed by C. Cao and a

synthesizer developed by Y. Ding as well as to demonstrate communication using the

transceiver.

First, a brief overview of the whole system design is given in Chapter 2. Direct Sequence

Spread Spectrum (DS/SS) differential chip detection (DCD) is utilized to mitigate the deleterious

effects of frequency offset and phase noise. A low noise amplifier (LNA), the first gain stage in

the receiver chain, plays an important role in determining the noise performance of whole

system. Its design methodology is discussed in Chapter 3. The low output resistance of short-

channel transistors limits the amplifier gain. The excess channel thermal noise and induced gate

noise hurt the noise performance. Approaches to achieve the reasonable gain and noise

performance while consuming low power are investigated. Three design examples are given in

Chapter 3. The conversion gain and noise performance of active mixers are discussed in Chapter

4. Demonstration of a 20-GHz RF front-end with on-chip antenna is also presented in this

chapter. The RF front-end is used to receive amplitude modulated (AM) signal transmitted from

an on-chip antenna 5-m away and to down-convert this signal to intermediate frequency (IF). For

the first time, we demonstrate that it is feasible for two ICs to communicate over free space via

on-chip antennas.









Chapter 5 discusses the building blocks in the receiver chain including variable gain

amplifier (VGA), low pass filter (LPF), 8:1 frequency divider, image rej section filter in LNA and

passive mixer. A distributed switch topology is used to share the use of one on-chip antenna by

the transmitter and receiver. Chapter 6 presents a fully integrated receiver implemented in a 130-

nm CMOS technology. It is characterized with an external LO source as well as with an on-chip

frequency synthesizer. In addition, a wireless communication link over 5m has been established

using the fully integrated transmitter and receiver. Finally, this research work is summarized and

possible future works are suggested in chapter 7









CHAPTER 2
CINODE SYSTEM OVERVIEW

2.1 Introduction

An RF receiver has two important performance criteria: sensitivity and selectivity.

Sensitivity is defined as the lowest power level at which the receiver can recover the information

with a required bit-error-rate (BER). Receiver selectivity is a measure of the receiver' s ability to

rej ect signals in adj acent channels or outside of band while receiving wanted signal.

The receiver sensitivity is critically determined by the noise performance of a system

which is specified using noise figure (NF). It is related to the noise factor which measures the

degradation of signal-to-noise ratio as the signal is processed through a system.

F=
Sou, Nost(2-1)

where noise figure (NF) is an equivalent representation in decibels.

In a system consisting of n-stages, if the individual noise factor and gain of system

components are known, the overall noise factor can be calculated by Friis equation [31] ,


Fsv = F, + + 3 ~~
G G; G G,G2, G,-1 (2-2)

Equation 2-2 shows the overall system noise factor is determined by the first few stages if they

have sufficient gain to suppress the noise contribution from the following stages. The sensitivity

level of a receiver is defined by

Sensitivity level = -174dBm /Hz +10logl0O(BW) +NF +Eb lo, (2-3)

where the first three terms represent the noise floor at system input, NF is the noise figure of

receiver, Eb oN is the required energy per data bit over variance of noise at minimum BER

requirement. The receiver sensitivity level is directly related to the noise figure of receiver. To









minimize the overall noise figure, the noise figure of individual building blocks in the receiver

must be reduced and the distribution of gain along the receiver chain has to be properly chosen.

If noise figure of individual blocks is fixed, it is desirable to have high gain in the first few stages

to suppress the noise contribution from the following stages. However, such kind of gain

distribution degrades receiver selectivity.

Receiver selectivity characterizes the ability of a receiver to pick out the wanted signal in

the presence of a strong adj acent channel or alternate band signals. The selectivity is affected by

many factors such as linearity of individual blocks and gain distribution along the receiver chain.

As discussed before, higher gain used in the early stages of receiver reduces the noise figure.

However, this will place a tighter linearity requirement on the subsequent receiver blocks. Power

consumption is another performance metric. Noise figure and linearity of a receiver can be

improved by increasing the power consumption of receiver. For portable applications, the trade-

off is between providing satisfactory receiver performance and power consumption.

We will briefly go over two types of receiver architectures: super-heterodyne and

homodyne. Then, we will talk about the dual down conversion structure used in this work. The

choice of architectures places different emphases on the trades-offs among performance, power

consumption and complexity. Unlike conventional radios which generally use an off-chip crystal

frequency reference, the single-chip radio will use an on-chip voltage control oscillator (VCO)

which increases the frequency offset between TX and RX, and phase noise. As mentioned,

DS/SS DCD is used to mitigate these deleterious effects.

2.2 Super-Heterodyne and Homodyne Receiver

A super-heterodyne receiver can have excellent selectivity. In a super-heterodyne receiver,

as illustrated in Figure 2-1, the incoming RF signal is picked up by an antenna and filtered by a

band select filter following the antenna to attenuate the out of band signals. The LNA amplifies









the signal while introducing a minimal amount of noise. Then, the signal is first down-converted

to intermediate frequency (IF) using a mixer and local oscillator (LO) signal generated by a

phase lock loop (PLL). There is an image rej ect filter between the LNA and mixer. This filter is

to significantly attenuate the signals in the image band. The LO signal can be tuned to down

convert any wanted in-band channel to a fixed IF. The tuning of the LO signal is achieved by

setting the divider ratio of PLL. The IF stages can then use a fixed band pass filter which can

attenuate unwanted signals. Selectivity is therefore determined by the IF filter. The signal at IF is

down-converted once more to baseband using LO2 with fixed frequency. The baseband circuitry

performs additional channel filtering and adds variable gain to reduce the dynamic range

requirement of analog-to-digital converter (ADC).

The excellent selectivity of a super-heterodyne receiver is due to the high quality factor Q

networks formed using off-chip passive components, which are not available for the receivers

integrated in a chip.

Image
BPF Reject Filter IF Filter 7 V~GL- t C ADC


VG ADC
LO1
LO2_Q


Figure 2-1. Super-heterodyne structure.

A direct-conversion receiver can eliminate the need for high-Q off-chip passive

components. The receiver directly down-converts in-band signal to baseband using only one LO

signal without utilizing an IF stage, as shown in Figure 2-2. Unwanted signal can be easily

removed at baseband. Direct-conversion architecture is better suited for integrated receiver.

However, there are several problems for this architecture. One problem is DC offset. LO signal










can leak either to the mixer input or to the antenna. The radiated LO signal leaking to the antenna

can be reflected and picked up by the receiver. In these situations, LO signals are self-mixed and

results in DC offset [24]. The unwanted DC offset is interference to the wanted signal. One

approach to eliminate the DC offset is utilizing an AC coupling capacitor between mixer output

and baseband circuitry. This method effectively high-pass filter this signal. Applicability of this

technique highly depends on the system settling time, modulation scheme and bandwidth. For

wide-bandwidth system, the pole of high pass-filter can be set relatively high without

significantly degrading SNR. Later on, we will discuss how to deal with the AC-coupling issue

in the true single chip radio. Other design issue in direct conversion is I/Q phase accuracy and

amplitude mismatch. It's particularly challenging to provide perfect I/Q signals at higher

frequencies. For example, a quarter wavelength in silicon at 24GHz is ~900Clm. A 10-Clm line

length difference between I/Q signal traces will translate to 1-degree phase difference. So it will

be challenging to implement a direct conversion receiver with such high RF frequencies.



BPF VG I~;~Sk ADC


VG ADC




Figure 2-2. Direct conversion receiver.

A C1Node only has one channel for low data rate communication. Unlike most of radios

which require variable LO frequencies for different channel selection, a C1Node makes use of

LO1 and LO2 in super-heterodyne structure with both fixed and they are generated using a single

frequency source. Shown in Figure 2-3 is a block diagram of the transceiver. It consists of a

transmitter, receiver and frequency synthesizer. The transceiver utilizes dual conversion









architecture [20]. Two LO signals are at 21.3GHz and 2.7GHz, respectively. They are generated

by using only one 21.3-GHz frequency synthesizer and a frequency divide-by-8 circuit.


RX ~ IVG~- LPF
Two 5b
LNAMP)- LO2 I ADC

VG- LPF

BUFFER I- 8:1 LO2_Q TIMING RECOVERY
& DEMODULATOR
LO1
PLL IL BUFFER t481V~e
MICROPROCESSOR
BUFFER


AMPMODULATOR IBETNTCOODCEHRP

STX


Figure 2-3. Simplified RF transceiver block diagram.

On the receiver side, an incoming 24-GHz signal is picked up by an on-chip antenna,

amplified by a low noise amplifier (LNA), down-converted to IF at 2.7GHz and then down-

converted to baseband to generate quadrature I and Q signals. These two signals are amplified by

variable gain amplifiers (VGA), filtered by lower pass filters (LPF) and then digitized by two

100-1VHz, 5-bit analog-to-digital converters (ADCs). The receiver frequency plan is depicted in

Figure 2-4. The image channel is located at 18.6GHz, which is 5.4GHz away from the desired

RF channel. This unwanted image signal can be attenuated by the tuned response of LNA and

mixer. On the transmitter side, its frequency plan is the same as the receiver. The baseband I and

Q are first modulated to 2.7GHz by a modulator [21] implementing an MSK-like constant

envelope phase-shift modulation. The modulated signal is then converted to 24GHz by an up-

conversion mixer. The up-converted 24-GHz signal is delivered to the on-chip antenna through









an on-chip power amplifier (PA) [22]. Since the 24-GHz transmitter output signal is 2.7GHz

away from the 21.3-GHz operating frequency of the synthesizer, LO pulling by the PA is

eliminated [23].




L2=1/9 fRF L0l=8/9 fRF R F,
Image



DC 2.7 18.6 21.3 24 GHz

Figure 2-4. Receiver frequency plan.

2.3 Baseline PHY

Unlike most modern communication systems which depend on a stable crystal-based

frequency reference, the RF subsystem of CINodes will use an on-chip frequency reference with

poor phase noise and large frequency offset. The operating frequency of CINode is 24GHz with

relatively low bit rate (100kbps). A subtle LO frequency offset between that of the transmitter

and that of the receiver can cause severe performance degradation. To mitigate this, modulation

and receiver processing methods were developed. To discus this, let us consider a BPSK system

in which the received signal is given by

r(t) = -EAp, (t) cos27(Ct + n(t), (2-4)

where n(t) is Additive White Gaussian Noise (AWGN) process with noise spectral density of

No/2. Assuming a receiver uses cos24t to demodulate the incoming signal, the average bit

error probability is given by


Pb = Q~a )~, (2-5)









where


a= cos(2x(f, )t)dt


sin(2( f, ~f )T)
(2-6)
2x(f ~f)T

where T is the symbol duration time which is 10CIS for 100kbps data rate. The frequency offset is

defined in terms of ppm,


FreqOff(pplm) = x 106.




1.E+001E0


(2-7)


1.E-04


1.E-06

1.E-08

1.E-10


0 2 4 6
Eb No


8 10 12


Figure 2-5. BER for BPSK with frequency offset.

Figure 2-5 shows the average bit error probability (BER) for BPSK coherent demodulation

with 0-ppm, 0.5-ppm and 1-ppm frequency offset. To maintain BER of 10-4 with 1-ppm

frequency offset, Eb/No must be increased by more than 3dB from 0-ppm case. Unfortunately,

even 1-ppm tolerance which translates to 24 k
achieve. One way to mitigate the frequency offset and poor phase noise of on-chip reference









frequency source is to use direct sequence spread spectrum (DS/SS) differential chip detection

(DCD) [25].

2.3.1 Direct Sequence Spread Spectrum (DS/SS)

Spread spectrum is a technique to spread the transmitted signal power over a broad

spectrum. Spreading spectrum reduces power transmitted at any one frequency so that it would

reduce interference to others and make the detection of the presence of signals difficult. It is also

less susceptible to interference at any one frequency and makes jamming difficult.



b (t)





a (t) bf


s (t)





Figure 2-6. BPSK modulation and BPSK spreading scheme.

One way to spread signals is to modulate the transmitted data signal by a high rate pseudo-

random sequence of phase-modulated pulses before mixing the signal up to the carrier frequency

for transmission. This spreading method is called direct sequence spread spectrum [26] Suppose

the data signal is


b(t) = JZ& bk T(t kT), (2-8)









where bk is the symbol sequence and Tis the symbol duration. We modulate the data signal b(t)

by spreading signal a(t) or a PN code, which is





where a, is called signature sequence and W(t) is called the chip waveform. We impose the

condition that T = NT, where N, referred at the processing gain or the spreading gain, is the

number of chips in a symbol and To is the chip duration. Then the spread spectrum signal is given

by

s(t) = b(t)a(t), (2-10)

There are many spreading schemes. For example, a spreading scheme with BPSK modulation

which means bk = +1 and BPSK spreading which means a, = +1 is illustrated in Figure where

spreading gain is only 4. The power spectrum of the spread signal s(t)is given by

sin 2 oTc /2)
O, (m) = PTC (2-11)
(m~T / 2)2

Compare this to the power spectrum of the original data signal.

sin2 (mT /2)
Ob (m) = PT (2-12)
(mT /2)2

We see that the spectrum is spread N times wider by the multiplication of the PN sequence.

This is illustrated in Figure 2-7. This figure shows a wireless link including a transmitter, a

channel and a matched filter receiver. One great feature of DS/SS is the low probability of

detection. It means that it is hard for an unintended receiver to detect the presence of the signal.

When the processing gain is significantly large, the spread spectrum signal can be below the

white noise floor, as shown in Figure 2-7. A receiver without the proper PN code can not

despread the received signal. The RF subsystems size of only ~3 mm x 3 mm and the signal in a










wide frequency band below background noise level make the radio physically and electrically

invisible.


noise n(t)
B ay b(t) s(t) e r(t) (t)


PN code a(t) PN Code a(t)

Transmitter Rcie

Filter
Data signal Original data signal PT

m after spreading No No

-2n/Tr 2n/T -2n/To, w0 2n/To -2nr/To -2n/Tr 2n/TT 2n/To,
Modulated Data Receiver Inout Demodulator

Figure 2-7. DS/SS BPSK system block diagram.

2.3.2 Differential Chip Detection of Direct Sequence Spread Spectrum (DS/SS-DCD)

The RF subsystem for CINode will utilize an on-chip frequency reference to generate the

LO signals which could have higher phase noise and larger frequency offset. To mitigate these,

DS/SS DCD can be utilized [25]. The application of differential detection at chip level rather

than data symbol level significantly improves receiver robustness to large carrier phase drift

since the phase variation could be considered negligible within a pair of chip interval.

Figure 2-8 shows the basic processing step used in differential chip detection [27]. The

transmitted signal d, is modulated by random phase 8k and frequency offset co, and corrupted by

white noise signal n Then the sampled baseband signal is


rk = dke(T+k + k (2-13)

where To is the chip rate. The output of differential chip detector is


ck = Re {;}ly_ ) (2-14)










rk = dk k a Re{- } +kck



*, _, j(m(k-1)Tc+Hk-1)






Figure 2-8. Differential chip detection block diagram.

Let' s ignore phase noise 8k for this moment to examine effect of the frequency offset. Then

Equation 2-14 becomes

ck = Re {dkdk-le~rT }= dkdk-1 COS(COTc). (2-15)

When the frequency offset co is small compared to the chip rate l/To cos~rnT,) is


approximately equal to 1, then cis close to the desired differentially detected signal ck = dkd .

As the frequency offset increases relative to the chip rate, the cosine factor becomes less than

unity and reduces the signal level, which in turn degrades the receiver sensitivity. Frequency-

offset tolerance can be made arbitrarily high by simply increasing the chip rate. However, for a

fixed data rate, increasing the chip rate requires increasing the processing gain (chips per

symbol), which leads to higher implementation cost and degraded sensitivity for DS/SS-DCD.

When the phase drift and noise are considered, assuming that the noise samples, nk


andnk-1, and the chip samples, dk anddk-1, are uncorrelated, the input and output chip SNRs are

d2 E
SNR, = k (2 16)

--2 --2 --2
dfdfe E) eE SNR2
SNRDC __ 1 (2-17)
djng_ +dn nn_ 22o+ 2SNR,, +1









where E is the mean energy loss factor due to the frequency offset and phase noise. It will be

discussed in detailed later and assumed to be constant for this moment. For large input SNR, the

DCD SNR is approximately equal to half of the input SNR which means 3-dB degradation.

However, for the low input SNR levels typical in DS/SS receivers (below OdB), the DCD SNR

approaches the square of the input SNR. SNRDCD can be converted to an effective (Eb N C) DD


Eb e (Eb o 727
( )DcD ,(2-18)
N2(Eb li) iN +Gp

where G; is the processing gain. For large Gp, (EbN C), DDis


Eh 1 b
( b DD a ,(2-19)
No c G' I~NO

Equation 2-19 shows that each doubling of the processing gain requires a 1.5dB increase

in (Eb lN,) 7; to maintain (Eb N ) DCD the same or bit error probability.

The mean energy loss factor in Equation 2-17 given in [25] is

E = cos(coTc)e ~"~i". (2-20)

,is the variance of AO, which is defined by,

as, = a, s,_ (2-21)

It can be written in Z-domain,

aO(Z) = B(Z)He (Z), (2-22)

where H, (Z) is the phase transfer function produced by differential chip detection,

Ho(Z)=1-Z (2-23)

The frequency response of H, (Z) is obtained by setting Z = e'2T~ :


Ho(f)= 1-e ',J IHB(f ) 2 = 2Sin(7Cc ) 2 (2-24)









GiveTn the nnXpowe sprctral densiPty Po ( f) for the LO phase noise


O 2 P, (f) He (f) 2 df. (2-25)


Since H, (f) has a highpass filter nature, it helps to suppress close-in LO phase noise. Assuming

that chip matched filter (C1VF) effectively limits the bandwidth of the phase noise to 1 / 2T a

simple analytical model is (equation (19) in [25]),

e= cs~m~~exp-13.5K},(2-26)


K= o JPf,= (2-27)
G Rb


22

20

ii18

S16
-* AWGN

12
B ~-2 AWGN w ith K=0.01 and =
(h=2TT Rc/10O
10
1 10 100 1000 10000
Processing Gain, Gp

Figure 2-9. Required Eb/No at BER of 10-4

Using Equation 2-19 and 2-26, Eb 0, required at BER=10-4 with different processing gain

is shown in Figure 2-9 for three different situations: only AWGN channel without frequency

offset and phase noise (w = 0 and K = 0 ), AWGN channel with phase noise (m = 0 and

K = 0.01) and AWGN channel with phase noise (K = 0.01) and frequency offset of









0. 1 R, (m = 2x-R, /10). Based on Equation 2-18 and 2-26, the presence of phase noise (K = 0.01)

will cause ~1.2-dB energy loss and frequency offset of 0. 1 R, will cause additional ~2-dB energy

loss. To achieve the same BER of 10-4, the Eb/N0 in the presence of phase noise (K = 0.01)

needs to be increased from 0.7 to 1.2dB compared to the case with only AWGN. Additional

frequency offsets of 0. 1 R, requires extra from 1 to 1.6dB increase in Eb/NO.

2.3.3 Modulation Format

4-bit
Symbol PN Sequence
Value Selection

s o ~~D if f e m n ia l P S a p

Bis Serial sl ctkOPK bk
Parallel .Mod. mft






Figure 2-10. Block diagram of 16-ary orthogonal modulation.

As shown in Figure 2-10, the radio uses a DS/SS in which each data symbol is represented

by one of 16 different PN sequences. One PN sequence represents 4 bits. These PN sequences

are selected to be approximately orthogonal. The format can be viewed as 16-ary orthogonal

modulation. The selected PN sequence which contains 2048 chips is passed to the chip level

differential encoder. Then the encoded chip sequence is modulated onto the carrier using Offset

QPSK (OQPSK) with half-sine pulse shaping which is Minimum Shift Keying (MSK). The

corresponding power spectral density (PSD) is

16Tb COs [2xTb(f )l COs' [2xiTb( f)
~( f )= + ,(2-28)
ai [1 -16T/"(f J)2 ]3 [1-16T/lb(f + J)? ] 1










where Tb is the average bit interval. The spectrum for MSK decays roughly as l /f4 Figure 2-11

shows a block diagram of the 16-ary orthogonal demodulator [28]. The demodulator consists of a

differential chip detector followed by an optimal coherent detector for orthogonal signaling. The

differential chip detector removes phase offsets between transmitter and receiver, and it mitigates

the impact of frequency offsets as well as phase noise.


4-bit
PN Sequence Symbol
ct~kMatched Filters Estimate

Chipsod
Matched \l IP"d
Fitr 'Differential sParallel Bits
rcut) Chip e $ Seoial
t= kTo Detection ags







Figure 2-11. 16-ary orthogonal detector with DCD.

Similar to Equation 2-18, Eb 0N at the input of the PN sequence matched filter in Figure

2-Figure 2-11 is

-2
Eb E (Eb ~o 22
( )DD, (2-29)
No D 2(Eb~:N 0 in +Gp / B

where G, is the processing gain for one symbol, defined here as the number of chips per symbol

and B is the number of bits per symbol. For M-ary orthogonal signaling where each symbol

represents B bits, the average symbol error probability (Ps ) [29] is

12i1 -C[ 12i1 %e2hiJ 21 ~ 2EV
P, = [1 /d)- Xp(--(y 1)2 ]dy, (2-3 0)










E E,
S= 4( bDD(2-3 1)
No No

The~ coI~rresponding bit error probabUIily (Pb j IS

M /2
Pb = (2-32)
M-1

Using Equation 2-30, 2-31 and 2-32, the required Eb 0N at BER of 10-4 with different

processing gain to tolerate different frequency offset in the 16-ary orthogonal detector is shown

in Figure 2-12.


18
17 Gp=2048
Gp=1024
16

S15 Gp=512

S14 Gp=256

S13 Gp=128

12
Gp=64


10
1 10 100 1000
Stability (ppm) at 24GHz

Figure 2-12. AWGN performance in 16-ary orthogonal detector.

However, in real implementation, noise and chip samples are not completely uncorrelated.

The set of 16 PN sequences are not perfectly orthogonal. All these factors will cause

performance degradation. One of the goals for the integrated frequency reference is to +100ppm

stability, which could produce a worst-case frequency offset 200ppm between a transmitter and a

receiver. At the 24 GHz operating frequency this translates to a 4.8 MHz offset. Using 10% of

the chip rate as our rule of thumb for acceptable offset, then the chip rate must be on the order of









48 Mchip/s. The processing gain Gp required to achieve this chip rate will depend on the desired

data rate. For the 100 kpbs assumed here, the 16-ary symbol rate would be 25 k-symbol/second,

and a processing gain of G,=2048 would give a chip rate of 51.2 Mchip/s. This is slightly larger

than the desired 48 Mchip/s, but it allows G, to be a power-of-2 which simplifies

implementation. It is shown in Figure 2-12, to tolerate 130-ppm frequency offset, processing

gain of2048 and Eb/No of 17.5dB are needed. In addition, with G,=2048, the phase noise

requirement is greatly relaxed. According to [28], a phase noise level of -65dBc/Hz at 1-MHz

frequency offset only causes 0.5dB Eb/No degradation. Based on the Eb/No of 18dB which

tolerates the frequency offset and phase noise, the link budget of receiver is given in Table 2-1.

Table 2-1. Link budget of CINode.
Spec Targeted Number
TX Output Power 10 dBm
Communication Range 5 m
Antenna Pair Gain -84 dB
Antenna Direction Loss 4 dB
Received Power -78 dBm
Thermal Noise -174 dBm/Hz
Bandwidth (100 kb/s) 50 dB
Eb/No 18 dB
RX Noise Figure 10 dB
Sensitivity -96 dBm
Link Margin 18 dB


2.4 Summary

This chapter reviewed the communication system for CLNodes including RF front-end

architecture and baseline physical layer. A dual down conversion architecture is selected. This

architecture uses only one frequency synthesizer and divide-by-8 circuit to generate two LO

signals. Unlike most radios which use crystal frequency reference, reducing the chip area. Unlike









most radios which use a crystal frequency reference, the RF subsystem uses an on-chip VCO as

the frequency reference. Poor phase noise and frequency offset of the VCO could significantly

degrade the system performance. DS/SS-DCD is utilized to mitigate these effects. This chapter

described the relationship between the frequency offset tolerance and processing gain. The

tradeoff between the receiver sensitivity and processing gain is also discussed. To tolerate 130-

ppm frequency offset and -65dBc/Hz phase noise at IMHz offset, Eb/No of 18dB is required.

From this specification, sensitivity target for this radio is -96dBm.









CHAPTER 3
LOW NOISE AMLIFER DESIGN

3.1 Introduction

Modern receiving systems must often process very weak signals. The noise added by a

receiver corrupts these weak signals. One approach to reduce the effect of the receiver noise is to

make the received signal stronger. This can be accomplished by raising the signal power

transmitted in the direction of receiver. This is eventually limited by government regulations,

engineering considerations, or economics. Another way is to increase the amount of power the

receiving antenna can collect, for example, by increasing the aperture of receiving antenna. The

other approach is to minimize the noise of receiving system. Lowering receiver noise has the

same effect on the output signal-to-noise ratio as improving any one of the other quantities.

Increasing the transmitting power or increasing aperture of antenna can be costly compared to

the small cost of improving the LNA noise performance.

3.2 Noise Sources in MOS Device






S r i D

Lelec A L




Figure 3-1. Cross section of a MOSFET channel consisting of a gradual channel region (I) a
velocity saturation region (II).

The noise in RF building blocks is contributed by the active components (transistors) and

passive components such as resistors and inductors. Resistors contribute thermal noise. In

MOSFETs, there are two maj or sources of noise at low frequencies (~1MHz and below): 1/f









noise and thermal noise. 1/f noise is caused by carrier number fluctuation [31], [33] and mobility

fluctuation [34] in the channel. It is a low frequency phenomenon. In tuned RF amplifiers

designs, due to the high operating frequency, the channel thermal noise is the main concern.

Thermal noise is generated by random motion of channel carriers. In short channel devices, due

to velocity saturation, the channel can be divided into two sections [38]: a gradual channel region

and a velocity saturation region, shown in Figure 3-1.

In gradual region described in [35], the drain current is

dV
I, = -puWQ,(x) (3-1)
dx

where pu is the mobility, W is the channel width and Q, is the inversion layer charge per unit

width at position x along the channel. Rewriting Equation 3-1 as

dx
I, = -dV (3 -2)
puWQ (x)

giving the resistance AR of a small segment Ax in the channel


AR = (3-3)
p~WQ, (x)

The spectral density of this small resistor is

4kThx
Av2 =(3-4)
pUWQ, (x)

This "local" noise will cause noise in the drain current. Integrating Equation 3-1 along the

channel gives

W
I, = l p V(x)dV(x) (3-5)
L "`

Now, let' s assume there is voltage perturb Av at position x in the channel, Equation 3-5 is

rewritten as










I, = p ,"[ Q,' C (x)dV + Q, ~~(x)dV]. (3-6)


Local conductance is defined from Equation 3-6,

BI, W
g(x)= (x). (3 -7)
BAv L

which specifies how small voltage change in the channel causes the change of drain current.

Combining Equation 3-4 and 3-7 gives the contribution of small segment Ax in the channel to

noise spectral density of drain current in gradual channel region,

ai2- ,,\ ~V = k WQ), (x)
Ai gx22 kT 2 A. (3-8)

The total channel thermal noise density is the integral of Equation 3-10 along the channel, giving


I = 4kT .(3-9)


Qzny is inversion layer charge per transistor width. This equation is valid for any model,

provided the appropriate expression is used for Qmy,. Particularly, for models using the gradual-

channel-approximation (GCA) [36], Qzny is


Q,,s =LC, (V-V) (3-10)

Then, it can be rewritten as classic channel thermal noise spectral density [37]

id2 = 4kTyg, (3-11)

where y is 2/3 and g,n is the transcondutance of the transistor.

Noise generated in the velocity saturation region (II) is treated differently in various

previously reported papers [39]-[40]. Channel resistance in region II is derived in [3 8] while in

[39] the thermal noise of this region is calculated based on inverse charge and excessive electron

temperature. However, it is argued in [40] that noise from this region is zero because the carriers

do not respond to the finite voltage fluctuation when they travel at saturation velocity. Even









though noise generation mechanism in this region is not clear now, it has been reported that in

[30], [41] that short-channel NMOS devices in saturation exhibit noise far in excess of values

predicted by long-channel theory. y is typically 2-3. It generally increases with drain current as

well as Va. As drain-to-source voltage is increased, the electric field within the channel

increases, generating hot carriers. Transistors operating in weak inversion have a spectral density

id2 = 2qlD. (3-12)


assuming V, > 5k It is interesting to observe that the expression for weak inversion is just

like that of shot noise [36] In weak inversion the current in the channel is controlled by the

height of source-channel barrier which is lowered by increasing the gate voltage.


G





Vch1 c~h2 c~h3 ch



Figure 3-2. Induced Gate Noise.

The MOS can also be viewed as an RC distributed network with R representing channel

resistance and C representing the gate capacitance, as shown in Figure 3-2. At high frequencies,

the local voltage fluctuation in the channel due to thermal noise couples to the gate through the

oxide capacitance, inducing the gate noise current to flow. The spectral density of gate induced

noise [37] is

w02 2
i2 = 4kT -6 gS (3-13)
g 5g,









where 6=4/3 for long channel device. Since the channel noise and induced gate noise are

physically generated by the same noise source, they are correlated. The correlation coefficient is


c = = -J j = j0.3 95. (3-14)
V32


The gate thermal noise arises from the resistance of gate material. The noise introduced by

the intrinsic portion of the gate structure of width W and channel length L is given by

R, W
1,2 4kT g'4(3-15)
g~i3 L

R,, is the sheet resistance of gate material. The factor of three arises from a distributed

effect [42]. It will be lowered by a factor of four if the gate is connected from both sides. For

ultra deep submicron CMOS, gate current depends mainly on gate-source voltage bias and gate

area. Just as any current across the junction, gate leakage exhibits shot noise with current

density i = 2qlG, COmbined with induced gate noise, it will limit noise performance.

3.3 Topologies of LNAs

In an RF receiver, the input signal from an antenna is amplified by an LNA. As shown in

Friis equation, to sufficiently suppress the noise contribution from following stages, an LNA

should have high gain and its noise contribution to the system should be low. In portable devices,

the power consumption should also be low. One of LNA' s functions is to provide right input

impedance, generally 5002, as required by the preceding band-select filter. Otherwise, the

insertion loss and pass-band ripple of the filter will be degraded. Even without a preceding filter,

the LNA needs to provide proper impedance to the antenna.

However, simply shunting a 50-02 resistor at the input will significantly degrade the noise

performance of the amplifier. Generally used topology is common-gate (CG) and source

degenerated common-source (CS) topology, as shown in Figure 3-3.























A B


Figure 3-3. Two types of LNA topologies. A) CG-LNA and B) CS-LNA

The input impedance of the CG-LNA stage is approximately 1/gmy of the input transistor

Ml, while that of the CS-LNA is


Z,,, = s(Lg + L) +-~ + L
sC C


= s(Lg + Ls) + + my~ L, (3-16)
sC,

n, is specified by choosing L, and Ls to resonate with C,, at the operating frequency. Its

real part wr)Ls is set to 5002. A fundamental difference between these two input matching

networks is that CS-LNA uses a series resonant circuit while CG-LNA employs a parallel

resonant circuit. The quality factors of two input networks are

moC R, 1
QCGLNA_ gs s CS-LNA= (3-17)
2 2mCgsR,

Typically, QCG-LN < 1 While QCS-LNA > 1 It is well known that sensitivity of Zn to

component variation is proportional to the quality factor of matching network. Hence, CG-LNA

with its lower Q parallel resonant network is more robust against typical component variations.










Moreover, parasitic capacitance at the CG-LNA input is naturally absorbed into LC tank. The

effective transconductance of the CS-LNA is


Gni,CS-LMA nigle __ni (3-18)
m,C,(R, +m,L,) mR,1+L"


With the input matched to R,,

GnS-M __ T ). (3-19)
mCS2R, rqR

In contrast, the effective input tranconducance of CG-LNA under perfect input matching

conditions is

1 1
Gn,CG-LMA nil (3 -20)
2 2R

The value of coT 00 typically is in the range of 3~5, depending on the operating frequency

and the technology. Therefore, CS-LNA provides higher gain than its conventional common-gate

counterpart. Especially, in high frequency circuits, the gain boosting by input matching network

is often utilized.

3.3.1 Gain of CS-LNA

To drive the complete gain of CS-LNA, a simplified circuit shown in Figure 3-4 is

analyzed. In CS-LNA, the short-circuit transconductance G,, is given in Equation 3-18, and

output impedance is Zload lf To is SUFFiciently large. However, with CMOS device scaling, ro of

intrinsic transistor becomes smaller and its effect has to be considered into gain calculation.

Extra-Element-Theorem (EET) [43] is utilized to make calculation much easier. This method is a

powerful way to identify the effect of one particular element on whole network. Following the

procedure in [43], ro is assigned as an extra element and initially it is assumed open. The voltage

gain is











Vo,,(m)jg ,Zload( Ogs
(3-21)
V,,(m) m ,


1 1
Where so = and Q =
(Lg +L,)C, "",C,,R,






Rs. L Jgyu



Lsk Ls





A B


Figure 3-4. CS-LNA and its equivalent circuit.

The impedance Z,, seen by ro with & ,, adjusted to yield Vo,,,=0 is


Z,,= ,L (3-22)


The impedance Zd seen by ro with & ,,=0 at resonant frequency is

Z sL
Zdload s.(3-23)
2 2

The complete voltage gain at resonant frequency is



g,,,Z~oa gs &7
H = (3-24)
2 Zload m 'LL,
1+
2ro











When m2gL <<1 and|I jmL, |<<| Zload |, Equation 3-24 can be simplified as



H = Kela s(3-25)
2 Zoa
1+ la
2ro

The effect of finite output resistance ro on gain of the amplifier is shown in Figure 3-5.

When ro is same as Zload, gain drop is 3.5dB compared to an amplifier having an infinite output

resistance. Rewriting Equation 3-25 as


H = E gsZod-2o(3-26)


It indicates output node has parallel combination of Zload and 2ro 2ro is the output

resistance of common-source tuned LNA.






-2



mv -6





-8
-9
O 2 4 6 8 10
ro/l~oad


Figure 3-5. Output resistance effect on gain.

3.3.2 Noise Factor of CS-LNA

It is first discussed in [47] that gate induced noise could play an important role in noise

performance in high frequency LNAs. Figure 3-6 shows the network including three noise









sources: gate induced noise i,, channel thermal noise id and source voltage noise v,2. Output short

circuit noise current ii is calculated.





II ig cq ) Pi di








Figure 3-6. Noise sources in CS-LNA.

It is easy to show that the relationship between the output noise current in; and gate

induced noise i, and channel thermal noise id is given by

S( Z, + Z, ) Z, + Z, + 1 s C,,
nl, = + id (3 -27)
1 / s C + Zg + ( p + 1) Zs fZ, + Z, + Z, + 1 s C,,

where p= o,/ ljm, is the MOSFET current gain from gate to drain. If Z, and Z, are defined as

R,+jw~L, and jwL,, Equation 3-27 can be rewritten as

I~liE1+ m,, R, + jw(L, + L,) +I 1+
n1 g T,jm R, d LT L,
R, Rs(3-28)

At the resonant frequency, this relationship can be rewritten as

1 myT
.I, = 7 [i ( Q) d] (3-29)
1+
R,

Similarly, the output noise current due to input voltage noise source v,, is


7 g" (3-30)
v,, 1+ s(g,,L, + C,,R, ) +s2Cg,(LR + L')

At the resonant frequency, it is simplified as










i,, my %,,,0'(3-3 1)
7;, 4,(Rs + m,Ls) 2

The total output noise current is

ii =i,21 + 72. (3 -32)

Noise factor of the amplifier will be ratio of total output noise power (i,) to the output noise

power contributed by input noise source (v,).


if (ig,id) i2 n ;1 g d
F= 1+ (3 -3 3)


The detailed derivation is given in Appendix A. It is shown in Equation A-5.



F = + (3-34)


The result is the same as that in [47], [48]. Unlike the procedure taken in [47] which

calculates uncorrelated and correlated parts in gate induced noise separately, the derivation here

directly gives total output noise current spectral density including the correlation between gate

induced noise and channel thermal noise. Including gate inductor resistance, noise factor is


F = F + (3 -3 5)
R,

Noting that

R, m n ,L,/ Q nd an l801gS,
an R, -(3-36)
Rs Rs Q nd T mg

Substituting Equation 3-34 and 3-26 into Equation 3-35 results in


egs 7-2 c ~J + 6(1+Q,)s/5 u, (-7
F1l= + + .(-7
ilnd g









3.3.3 Noise Factor of Cascode Amplifier

An LNA is generally implemented with a cascode stage to improve the stability by

isolating the input port from output port voltage variation, as shown in Figure 3-7. The isolation

makes the design more straightforward. At low frequencies, for long channel device which has

high output resistance, the noise contribution from the upper transistor M2 is believed to be

much lower than that from the bottom transistor Ml. It is suggested [49], [50] that optimal

choice of M2 is about same as Ml. Other author [5 1] has suggested ratio of width of M2 and Ml

ranging from 0.55 to 0.75.


Zload



M2G~

Rs L
Ml









Figure 3-7. Schematic ofcascode amplifier.

For an LNA operating near 20GHz, the effects of drain-to-body capacitance on noise

performance and effects of M2 should be more carefully considered. The noise contribution

from M2 to output noise can be readily derived using Equation 3-27 where Z, = 0 and

Z, = 2ro //(1/sCdb) Here ro is output resistance of Ml.

ptZ Z, +1/lsC,
z ag + ""i (3 -3 8)
n_ /SCgs + (p +1)Z, PZ, + Z, + 1/sC d









At ~20 GHz, 2ro >>| 1/sCdb giVing


p ig + C, ic;
SC,jw jcmr (3-39)

Where C,. = 1 + Cri, /C, the spectral density of output noise current due to M2 is


2 ij Ci2-c,
7,, (3-40)


p, is the current gain of M2.







ix \+I I ro C'db




Figure 3-8. Schematic calculating output noise current from common-source stage.

To calculate the noise contribution from M1 to output, the current derived in Equation 3-27

can be treated as the short circuit current in Norton equivalent network with output resistance of

2ro, as modeled in Figure 3-8. It can be shown


7,, 1 (3-41)
1 + C, C, + p,

Since the noise from M1 and M2 are uncorrelated, the spectral density (PSD) of total

output noise current is superposition of three noise sources: source, Ml and M2.


.2z *2 2 2 22 2 7 c22- 2c #2 r 2 2 2' 21Zi in1.?( l2Qr)l 22
i," = 7,," + i," 2 s 2,










d.5+pf2/' 21cC,
F = Fl+ 4- w (3 -42)


Fl is defined in Equation 3-36. W2 and W1 are the width ofM2 and Ml, respectively. This

equation shows there is an optimal selection of Os, to minimize noise factor.








a, 3 Noise Factor

22
Noise of M1

Gate indcutor
Noise of M2 noise


0 1 2 3 4 5 6 7 8 9 10
gs,

Figure 3-9. Noise contribution from a cascode amplifier.

To illustrate how Qgs affects noise factor, Equation 3-41 is used to calculate total noise

factor and noise contributions from different noise sources. Since there is no accurately measured

y and 6 ever reported for a 0. 13-Cpm technology, we assume y and 6 in short-channel device are 2

and 4, three times of their counterparts of long channel devices. Here Qznd is set to be 20, which

is the measured value for an inductor test structure around 24GHz. C, is assumed to be 2. M2 and

Ml are assumed to have same width.

Figure 3-9 shows that noise factor has a minimum point for at optimal Qgsop. Noise factor

rapidly decreases with increasing Qg, until reaching the minimum point, then slowly increasing

with slope proportional to 6/5+1/Qznd. It indicates that gate induced noise from Ml begins to









dominate. The noise contribution from M2 monotonically decreases with Qgs. Noise Eigure only

varies ~0.1IdB for Qgs from 2 to 3. It could be labeled as an "optimal" region since noise factor

does not change much due to the Qgs variations resulting from technology variation.

3.4 24GHz CMOS LNA Implementation

Following the theoretical analysis of the LNA design, several circuits have been

implemented in the UMC 130-nm CMOS logic process. In BSIM3v3 model, thermal channel

noise factor y is Eixed to be 2/3 and induced gate noise factor is ignored. These inaccurate

modeling parameters will cause selection of Qgs and the noise simulation results inaccurate. Qgs

in the design are set to 3.2 and it can tolerate 10% component variations [51]. Higher Qgs means

smaller transistor size for a fixed resonant frequency and it also means lower power consumption

for a Eixed gate bias of Ml. In the 130-nm technology, supply voltage is 1.2V and voltage

headroom is limited. These LNAs are designed to operate at ~24GHz which is the working

frequency of CLNode, while consuming as little power as possible.

3.4.1 A 24-GHz Single-Ended CMOS LNA

Figure 3-10(A) shows the schematic of the single-ended LNA. The CMOS transistors M1

and M2 chosen in this circuit are 14 Eingers with total width of 14Cpm. The measured cut-off

frequency fT is about 60~70GHz. Two 6-pF bypass capacitors are put between Vdd, Vg2 and

ground to eliminate any inductance effect associated with wires connected to these two nodes.

The bypass capacitors are implemented with accumulation-mode MOS capacitors in an n-well

with capacitance density of ~11IfF/Cpm2. Since capacitors C1 and Ct in the signal path are for

capacitively transforming impendence and de-coupling the dc output of the amplifier, voltage

drop across this kind of capacitor may cause capacitance shift. More importantly, the large

parasitic capacitance and substrate reactance associated with the n-well will degrade the gain

performance, especially that of C1 These two capacitors are implemented with metal-to-metal









capacitor structures. The other benefit of metal-to-metal capacitor is much higher Q than that of

MOS capacitors. Using Metal 5-8 gives a capacitance density of ~26fF/100Cpm2. The parasitic

capacitance to ground is ~20% of desired capacitance. UMC 0. 13 Cm technology offers 8 copper

layers. The skin depth (in Cpm) in copper at frequency f(in GHz) is

1 2.1
6(;um>)=. (3-43)


where C=1.26x10-6 (H in) and o = 5.8x107 /Gm for copper. At 24GHz, the skin depth is 0.42Cpm.

To reduce the resistive loss, stacked metal layers are preferred to implement inductors to increase

quality factor (Q) [55]. Especially, the resistance of L, degrades the NF of the LNA. However,

use of multiple metal layers significantly increases the parasitic capacitance and lowers the self-

resonance frequency of the 1-nH gate inductor (Lg). Because of this, the inductors are

implemented using the 0.8-Cpm-thick top metal layer. The metal thickness is twice of the skin

depth so that whole vertical dimension of metal layer is conducting AC current. To reduce the

resistive loss, a wider inductor trace is preferred. But, once again, increasing parasitic

capacitance lowers the self-resonance. To balance these two opposite tendencies, the inductor

trace width of 3 Cm is used. The space between inductor traces is set to 3 Cm to reduce the

proximity effect. A polysilicon ground shield is placed underneath the inductor [52]-[54] to

reduce the loss resulting from capacitive coupling to silicon substrate. Since the Q of output

network is dependent on Qd of load inductor Ld(0.73nH), to tolerate the process variation, QdiS

set to 14. The trace width is 2Cpm for Ld. Ls in the circuit is only 120pH and it is designed with a

short metal line. Figure 3-10(B) shows the die microphotograph. The chip size is 500Cpm x

320Cpm including pads.

The circuit is probed with GGB ground-signal (GS) probes. Ml is biased using an off-chip

bias tee. The gate voltage of M2 is set to Vdd. The S-parameters are measured with an HP85 10C









network analyzer. The measurement result is shown in Figure 3-11. Biased at 1.9mA from a 1.2-

V supply, |S21| has a peak of 6.1IdB at 23.5GHz. The minimum NF is 5dB, as shown in Figure 3-

12. The linearity is measured with 2 tone input signals at 23.5GHz and 23.51GHz. Input referred

third-order intercept point (IIP3) is -6dBm, as shown in Figure 3-13.



Cbypass2 L


C1
Out

Vdz 2 M 2O
C2






L,


B

Figure 3-10. Single-ended LNA. A) a schematic and B) a die photo.





























I I


IS221


|S121


2 23


Meter of the LNA.


10



0
o

-10



S-20


-30



-40
2:


Figure 3-11. S-para


9



7




L.
Z

3



1


2 23 24 25 2

Frequency (GHz)


Figure 3-12. Noise figure of the LNA.


24
Frequency (GHz)

















E -20


0 -40


-60

-6dBm
-80
-25 -20 -15 -10 -5 0

Pin (dBm)

Figure 3-13. IIP3 measurement of the LNA.

3.4.2 A 24-GHz Differential CMOS LNA

A single-ended LNA is sensitive to parasitic ground inductance. The end of the source

degeneration inductor (Ls) connected to ground is supposed to be at the same potential as the

ground bond pad. However, there is always voltage drop between these two points because there

is always some finite impedance between them which can have a large effect on amplifier

performance. Even worse, it can form a parasitic feedback loop from following stages, and the

amplifier can become potentially unstable. Generally, this issue is not severe on-chip since the

distance between these two points is sufficiently short. However, at 24GHz and higher, this can

no longer be neglected. An alternative is to exploit the virtual ground located at the symmetry

point of a differential structure. Any series parasitic impedance connected to common-mode

nodes will not affect input matching impedance. Another important advantage of differential

topology is common-mode signal rejection. To maximize common-mode rej section at high

frequencies, it is important to keep symmetry in layout.






















L,


tIn-


L,


Figure 3-14. Differential LNA (a) Schematic and (b) Die photo.



















Is?21


-20


-30


-40


20 21


22 23
Frequency (GHz)


25 26


Figure 3-15. S-parameters of differential LNA.





8




6








22 23 24 25
Frequency (GHz)


Figure 3-16. NF of the differential LNA.

















E -20


0 -40





0 -2.4dBm

-30 -25 -20 -15 -10 -5 0

Pin (dBm)

Figure 3-17. IIP3 of the differential LNA.

At the same DC bias, a differential LNA consumes twice as much power of that of a

single-ended amplifier with the same gain and NF. The linearity of differential LNA is improved

because input power is split and each of input devices only sees half of voltage compared to

single-ended counterpart. The schematic of the differential LNA is shown in Figure 3-14(A). An

additional inductor Loom is added at the common node of input differential pair (Ml and M2) to

resonate with parasitic capacitances of Ls> and Ls2. This increases the impedance at resonant

frequency and enhances the common-mode rej section. The die photo is shown in Figure 3-14(B).

The differential LNA occupies 500 Cpm x 660 Cpm including bond pads, which is ~2x of the

single-ended one.

The LNA is measured with ground-signal-signal-ground (GSSG) probes. The single-ended

output of network analyzer is converted to differential signals using a balun. The measured S-

parameters are shown in Figure 3-15. At 23.5GHz, |S21| is 6dB at 1.2-V Vdd. The dc bias current









is 3.3mA. Power consumption is 4mW. The measured NF of the differential LNA is 5.3dB at

23.5GHz, shown in Figure 3-16. Figure 3-17 shows the linearity measurement result. The IIP3 of

differential LNA is -2.4dBm, ~3dB higher than that of a single-ended one. Table 3-1 summaries

the performance of the single-ended and differential LNAs.

Table 3-1. Summary of performance of single-ended and differential LNA.
Current Power Gain NF IIP3
LNAToolgy(mA) (mA) (dB) (dB) (dBm)

Single-ended LNA 1.9 2.3 6.1 5 -6
Differential LNA 3.3 4 6 5.3 -2.4


3.4.3 Device Characteristic


Drain oDrain

R, R,
Gat rdbGate Cldb Rdb

Rsub

C~sb V Csb Rsb
A B

Figure 3-18. Substrate network of a MOSFET. A) Simple substrate network. B) Substrate
network model of [45].

The measured gain of LNA is significantly lower than that of simulated one which is

~13dB. One maj or reason of the mismatch is inaccurate device modeling. Although BSIM3

model has been demonstrated accuracy in device's DC characteristics and sufficiently validated

for relatively low frequency applications, it requires modifications for uses at 24GHz [44]. One

important factor is that substrate resistance is neglected in BSIM3v3 model. To take account for

the effect of substrate resistance, two ways for augmenting the core transistor based on BSIM3v3

model are shown in Figure 3-18. Both models use extrinsic capacitances to account for

source/drain body junction capacitances. The diode capacitances of MOSFETs are set to zero. So









bias-dependant capacitance has to be extracted from measurement instead of being defined by

simulator. Figure 3-18(A) shows the approach of connecting a resistor to the bulk node. The

output impedance consists of Crdb in series with Rsub. When the transistor is off (gate bias is

zero), ro of the transistor is large so that the real part of impedance looking into the drain node is

Rsub at low frequencies. It is expected that at high frequencies C~sb tends to bypass the signal,

reducing the real part of substrate impedance from Rsub towards zero. However, the measurement

shows a constant R over a large frequency range [44]. Simply adding a substrate resistance to the

bulk node of the transistor does not properly model the substrate resistance effect. A new

BSIM3v3 RF model [45] is realized by adding Rg, Rdb and Rsb as shown in Figure 3-18(B). The

substrate resistance and drain junction capacitance can be extracted after converting S-

parameters to y-parameters,

Res = real(1/l(y22 + yl 2))
(3-44)
c, = 1/(m-imag(1/(y22 + yl 2))).


60 20

55
19
50

S45 18 n

40
17
35

30 16
10 15 20 25
Frequency [GHz]


Figure 3-19. Extracted Rdb and Cdb.










Since source is connected to ground, Rsb can not be extracted. Rsb and Rdb may not be the

same since they are determined by the layout. The extracted Rdb and Cdb are shown in Figure 3-

19. At 24GHz, Rdb is ~4202 and Cdb is ~18sfF, giving an equivalent parallel output resistance


Re, = Rdb( )2 = 3.2Kn (3-45)
out dRdb

This means Rdb further lowers the output resistance of the transistor, considering smaller ro

of short channel devices. The total output resistance is Ro,//ro, which means significant reduction

of gain. Rdb and Rsb also contribute to output noise. A cascode amplifier is simulated with 14-Cpm

wide common source and common gate transistors.


14


12-


10-


g c~ IW/o Rsub

o 6-


W/ Rsub





5 10 15 20 25 30
Frequency [GHz]


Figure 3-20. Rsub effect on output resistance of a cascode amplifier.

The amplifier output resistance with and without Rsub is plotted in Figure 3-20. At lower

frequencies, Rsub does not make much difference. However, at 24-GHz operating frequency, the

output resistance drops by ~30% in the presence of Rsub.









3.4.4 A 26-GHz CMOS LNA with Negative Impedance

To achieve higher gain, there are two choices: cascading more stages or boosting single

stage LNA gain by consuming more power. However, increasing power is not acceptable for

CLNode applications. To overcome the loss associated with substrate resistance, negative

resistance is generated in the signal path [58]. Cross-coupled VCO-like circuitry has been

demonstrated in [46]. But it introduces additional power consumption.













A B

Figure 3-21. Schemes for generating negative resistance. A) Source follower with capacitive
load. B) Gate inductor at a common-gate amplifier.

Figure 3-21(A) shows a source-follower with a capacitive load. The impedance looking

into the gate is

1 my1
Zll + (3 -46)
ml" gs 2

The circuit generates negative resistance -wr/2C. In [57], such a source-follower was

used after an amplifier containing an inductive load. The negative resistance compensates the

resistive loss in the inductor causing effective Q of the inductor to increase. However, the

stability of whole circuit must be ensured which requires proper selection of the value of

capacitance C. To implement the source follower it requires one extra stage which means more

power consumption. Figure 3-21 (B) shows another means of generating negative resistance. It is









well known that a series gate inductor in a common-gate amplifier introduces negative resistance

looking into the source. The impedance looking into the source of transistor, assuming ro is

relatively large (~ 3kaZ), is

Rln 1/g,, m2LU 4 (3-47)

where m, is go, ,. In a cascode amplifier, the negative resistance (the second term in right

hand side) can be generated without adding an additional stage that consumes power by simply

adding a gate series inductor in the common-gate stage as shown in Figure 3-22 (A).

Incidentally, the LNA in [56] is configured in the same way. The resonant frequency of Lg2- gs2

series network is much higher than the tuned frequency and it is proposed to create a notch in

|S12| to improve the stability. Looking at the output impedance of cascode amplifier, when the

impedance looking into the drain ofMI is defined as Zd1, the output impedance and

transconductance at drain node of M2 are,


Zd, 1) Zd/ (3 -48)
1~W mCgs mZL my~l 3 + jmZd1 /T

G,, m,((C,(wL, 1/C)-1jm-,).(3 -49)

Increasing Lg2 l0WeTS the resistance in the denominator which increases the output

impedance and increases transcoductance. At a given gain, this allows the transconductance or

bias current to be lowered, which further increases ro of the transistors and output impedance. At

the resonant frequency, the total simulated impedance at M2 drain node including Zd2,

impedance of Ld and impedance looking into capacitive transformer (C1, C2 and 50-02 load) is

increased to 701 from 49202 when Lg2 of 0.76nH is added, while the short circuit

transconductance at this node is increased by ~ 15%. These increase the gain by 4.1dB despite

the slight decrease of the voltage gain of common-source stage. The load inductor Ld is 0.68nH.










Lg2 is 0.76nH which gives Lg2-Cgs2 SerieS resonant frequency of ~36GHz. A microphotograph of

the LNA is shown in Figure 3-22 (B). The chip size is 0.45x0.36mm2 including the bond pads.

The S-parameters of LNA are measured on-wafer using an Agilent E8361A network

analyzer and are shown in Figure 3-23(A).




byas Ld


Lg2 )\Zd2 C1 Out

Vg22
Sbypass1 Zd1


Figure 3-22. The LNA with an inductor at the gate of M2. (A) Schematic and (B) Die photo.













o' -1 0

E, -20

3 -30



4 -50

-60
20 22 24 26 28

Frequecy (GHz)


30 32 34


20 22 24 26 28 30 32 34
Frequency (GHz)



Figure 3 -23. S-parameters and NF measurement of the LNA.

The maximum transducer gain (|S21|) is 8.4dB at 26.2GHz, while the reverse isolation |S12l

is -19.6dB. |Sy;| is -8.9dB and |S22| is -5.4dB at 26.2 GHz. S22 is mistuned due to the C1 being

~50% larger. The dc bias current is 0.8mA and VDD is 1.0V. When the supply voltage is

increased to 1.2V, |S21| can be increased to 13dB with power consumption of 2.4mW. Noise

figures are measured using an HP8970B noise figure meter and an external mixer, and the de-










embedding technique was discussed in [59]. Limited by the instrument, noise figures are

measured only up to 26.5GHz. The measured NF is ~5 dB at 26.2GHz, which is shown in Figure

3-23(B).



**** 31.2G~
~~* VSWR=1 0:1 .~~I'~. *
J .r ''*~ 30.5GHz ~ 30.5GHz
i --~~l 29.8GHz X 29.8GHz
S3. 29.1GHz 29 1G
28.4GHz 84r

'27.7GHz *27.7GHz

** ... t.... .... .." 2 GHz
26.3GHz 27GHz 26.3GHz

A B



Figure 3-24. Stability circles of A) input and B) output.

Stability is a serious issue for using negative resistance cancellation techniques. The

stability factor, K ranges between 0 and 1 from 26.4 to 31.3GHz. Bl is always larger than 0. In

this frequency range, the amplifier is not unconditionally stable. This is due to the mismatch

between peak |S21| and output matching (|S22l) frequeci~es. The input and output stability circles

for 26.3 to 30.5GHz are drawn using the measured S-parameters and shown in Figure 3-24(A)


using method in [60]. The LNA is stable in ~75% of the Ts plane. The LNA input typically sees

the output of a filter or an antenna whose impedances can significantly vary, and this is a


potential limitation. As shown in Figure 3-24(B), the LNA is stable in ~90% of the TL p 800.

Since the LNA will eventually be integrated with other components that have known and well

controlled impedances, it should be possible to make sure the load for the LNA is within the

stable region. Simulations indicate that the potential instability near the tuned frequency is not an

inherent consequence of using the negative resistance circuit and it should be possible to re-tune









the circuit so that is unconditionally stable over a bandwidth of 10 GHz around the tuned

frequency.


20
10

-0
-0-Fundamental
E -20


S-40
-50
-60 r IM3
-70 i -13dBm
-80
-40 -30 -20 -10 0
Pn (dBm)

Figure 3-25. IIP3 of the LNA.

The input referred third order intercept point (IIP3) of LNA is measured with two-tone

input signals at 26.2 and 26.21GHz. IIP3 is -13dBm, as shown in Figure 3-25. This is ~7dB lower

than that of the amplifier without the negative resistance circuit. The simulated voltage drop

across the gate and source of M2 is 1.8 times of that of Ml and the linearity of this circuit is

limited by M2.

Table 3-2 compares the performance of CMOS LNAs working above 20GHz. The LNA

with a gate inductor at M2 has reasonable gain and NF performance compared to most of the

previously reported LNAs while consuming significantly lower power. Compared to the 24-GHz

single-ended LNA without Lg2 fabricated in the same 130-nm CMOS process, the power gain is

~ 2 dB higher while consuming ~ one-third of the power. It should be possible to achieve gain of










~16dB by using a two stage design and doubling the power consumption. Even after this, the

circuit should consume power that is more than 5 x lower.

Table 3-2. Performance comparison between LNAs above 20GHz.

Circuit Metrics This work [58] W/O Lg2 [62] [64] [59]

0.13-plm 0.13-plm 0.18-plm 0.18-plm 0.13-plm
Process
CMOS CMOS CMOS CMOS CMOS

Type Single Single Single Single Differential

Frequency
26.2 24 23.7 24 20
(G Hz)

Gain (dB) 8.4 6.2 12.9 13.1 9

Noise Figure
5 5 5.6 3.9 5.5
(d B)
Bandwidth
3.7 4 ~2.5 ~4.8 ~5.3
(G Hz)
Supy1 1.2 1.8 1 1.2
Voltage (V)

Power (mW) 0.8 2.2 54 14 24



3.5 Summary

In this chapter, the topologies of CG-LNA and CS-LNA are compared. It shows with the

same DC bias current, the CS-LNA achieves higher gain because of quality factor of the input

network. Because of this, CS-LNA is better suited for low-power applications, like CLNode. Then

noise figure of CS-LNA and cascode LNA are analyzed. An "optimal" region of quality factor

Qgs of input L-C-R network is found to be 2-3 to minimize noise figure. Within this region, the

design can tolerate the component variations of ~ + 10% .

Single-ended and differential LNAs working at ~24GHz have been implemented in a

digital 130-nm CMOS technology. By comparing simulated and measured LNA performance, it

is found that the substrate resistance and junction capacitance play important roles in

determining the gain of LNA. By judicious use of negative resistance, a 26-GHz LNA achieving










a gain of 8.4dB and a noise figure of ~5dB at DC power consumption of 0.8mW and Vdd of 1.0

V is demonstrated. This work has shown that adding a gate inductor to the common-gate stage in

a cascode amplifier can significantly improve the power efficiency.









CHAPTER 4
20GHZ RF FRONT END DESIGN

4.1 Introduction

An RF front-end including an LNA and a mixer is key component in modern

communication systems. The LNA amplifies weak received signal and suppresses the noise

contribution from the mixer. The mixer actually performs frequency translation. This chapter

first discusses mixer design in section 4.2. Then a 20-GHz RF front-end implemented in a 130-

nm CMOS technology is demonstrated in section 4.3. Using this RF front-end with an on-chip

antenna as a receiver, 20-GHz AM signal transmitted from 5-m away is successfully picked up

and down-converted to intermediate frequency (IF). An RF front-end with additional IF

amplifying stage is presented in section 4.4.

4.2 Active Mixer

A mixer in a wireless receiver down-converts an incoming RF signal to an IF. This allows

amplification to take place at lower frequency [65] and relaxes the selectivity of IF fi1ter. The

earliest radios used 2nd-order non-linearity in devices and later on used analog multiplication to

accomplish the frequency translation. When local oscillator (LO) signal for the multiplication is

high enough, it eventually drives the circuit to work in a switching mode. The principle of

switching is illustrated in Figure 4-1. RF signal, represented as a sinusoidal rf(t), is multiplied by

a mixing function, an ideal square wave local oscillator, LO(t) varying between +1 and -1. The

LO signal toggles the polarity of RF signal at the output. It is easy to see the frequency

translation in the frequency domain. The spurs in the output spectrum can be filtered out. RF

signal can be either current or voltage and a mixer can be either active or passive. An active

mixer consists of a transconductor (M3) and switching pairs (Ml and M2) for current

commutation, as shown in Figure 4-2.









Frequency Domain


Time Domain


Input


MIAixing


Functions L


O utp ut ,,,,,


Desired
O utp ut


Figure 4-1. Switching mode of mixer.


LO>


Figure 4-2. Active mixer. A) Single-balanced mixer. B) Equivalent circuit.


LO -









4.2.1 Conversion Gain

In an active mixer, the switches reverse the polarity of the load current at the LO

frequency. The transcondutance current is

I,, (t) = gV,, cos~mt). (4-1)

The LO is a square wave generating a mixing function, it can be expressed as Fourier

series,


4/OI) sin(ksi)


The output current will be the product of the current I,7(t) and mixing function VLO(t), then

output voltage is this current times output load, RL-

4 1
Vo,,,(t) = gRL [COS(cLt) cos(3mLt) -]V, cos~m,ft), (4-3)
xi 3

Ignoring the harmonics of LO gives

4\1 1
Vout)=gmVR,- -cos(m,,-m wo)t +- cos(m, ,+mso)t). (4-4)
xij2 2

Eliminating the up-converted term, the resulting down-converted signal at output is


Vo, (t) = gV,,RL, COS(Of L O,)t. (4-5)

Therefore, assuming a perfect square wave LO, the voltage conversion gain through the

mixer is given by the well known expression


A, = gRL 2. (4-6)

The expression only holds when the LO voltage is large compared to the Vg,-Vth of the

switching devices. However, this assumption is barely satisfied in most cases where the LO is

driven by the output of an on-chip VCO or PLL, which is generally a sinusoidal wave. More









accurate voltage gain estimation is given in [66]. It takes into account the time when both of

switches are conducting current by averaging the voltage gain over one period of the local

oscillator. When the differential LO amplitude is sufficient high, only one transistor in the

switching pair carries DC current from M3, turning off the other. It is found in [67] that this

amplitude is (V,~g -Vth, SWWhere (Vgs -Vth)SW' iS the DC gate overdrive of switching transistors

is. If the LO amplitude is less than this critical value, both transistors are conducting current.

Assuming the local oscillator can be represented as a sinusoidal wave, V,,o(t) = Vo sin(rnto),

the time that the switches move from the state when both switches conduct current, denoted tBAL,

to another state when only one of the two devices are conducting current can be determined by

the following relationship:

VLO,(t) = JZ(V, -V~h SW = VL~O Sin(CO~LOtWrL). (4-7)

Assuming sin(x) eyx for small x, this gives


1/(Vg -Vh )SW
BAL th(4-8)
VL O LO

During time 4tBAL in one LO period, both switches are on and the RF current appears at the

common mode nodes of the differential pair which does not contribute to differential output

current. Only the current during the period when one switch is on contributes to output voltage.

So the conversion gain can be rewritten as [66],

12\ 4t 2 2 (V~g Vh)1
Av = gRLI-1~ BAL mRL gs S ). (4-9)
TLO x xVLO

Figure 4-3 shows mixer gain changes from ideal switching in Eq. (4-6) with ratio of LO signal

amplitude to(V, -Vth)SW. To make a mixer work with less than 3-dB gain drop from the ideal

switching, an LO signal amplitude should be at least 3 x (V, -Vth)SW














-2


-4


C-6
C')
-8


-10
1 1.5 2 2.5 3 3.5 4

V~ol(Vgs-Vth )sw


Figure 4-3. Mixer gain drop from ideal switching.

4.2.2 Noise in Active Mixer

The noise analysis in a mixer is different from the traditional white noise analysis for linear

and time invariant systems. In a mixer, the frequency domain method is suitable for RF noise in

the transconductor, but not for the noise from the switching pair. The noise of switching pair can

be solved using a stochastic differential equation (SDE) [68], [69]. However, it involves

numerical solution not intuitive. So the mixer noise analysis follows the method in [70].

Let's assume ideal switching for a mixer. The mixing function in Equation 4-2 only

generates signals at fundamental frequency and its odd harmonics. As shown in Figure 4-4, The

LO frequency and its odd harmonics will down-convert the respective frequency band of white

noise to IF [71]. The noise is uncorrelated at each sideband and frequency, and various noise

power contributions can be simply summed. The total output spectral density at IF due to

transconductor M3 in Figure 4-2 is

iz =i-2 2 +1 _1+-=32 2 x=3. (4-10)
In 3 5n x 8






























I l' i i l' i i i











fII











Figure 4-4. Frequency translation of white noise in a transconductor.

4.2.3 Thermal Noise from Switching Pair

When LO voltage is much greater than J(V, -P)th SWOf the switches, the LO switches

behave like the common gate stage of a cascode amplifier and there is minimal output noise


where i~ is the channel thermal noise of M3. The first term is the white noise at fLO fF down-

converted by the fundamental of LO, the second term is noise at 3fLO fF down-converted by the

third harmonic of the LO, whose amplitude is one third of the main harmonic of the LO, and so

on. Equation 4-10 says that the thermal noise current in the transconductor is totally transferred

to mixer output, just like in an amplifier. This is due to the fact that the noise is periodically

inverted without changing the general properties of noise in time domain [63].


SI I I

























Tiangle Approximation

G(t)T


contribution from the switching transistors. When LO voltage is less than Z(Vg -V )sw of the


switches, the LO switches behave like a differential pair.


VLO


G(t)f


Figure 4-5. Time varying transconductance G(t).
During the time interval A in Figure 4-5, both Ml and M2 are turned on and contribute to

the output noise. It is shown in [70] that the time variant noise PSD at one output port is

4kTy( 1 gml, 2 m2 )2) = 4kTy( Em, i, Em2
Emi 1+ gm /gm2 gm2 I6m2g, gml +m 8m2 (4-1 1)

The corresponding total output noise PSD of the mixer, which is twice of that at one port, is


gml' m2


(4-12)


Where

gml' m2










is the transconductance of differential pair. As shown in Figure 4-5, the transconductance and


output noise is periodic. V, is "threshold voltage" which is (VT~ -V~,,, determining whether

one transistor or both transistors conduct current. When VLO > |Vx|, the differential signal is so

strong that only one transistor is on while the other is turned off.

The time-average PSD at the output is


if = 8kTY m G~~qrt)dt kyyG (4-13)


The output noise is dependent on the average of G(t). As shown in Figure4-5, G(t) can be

approximated as a triangle shape with a period of TLO/2. G(t) is determined by the smaller of gmi

or gm2. It reaches the maximum when gmi and gm2 are equal. This point is located at zero crossing

of VLo which means the gate bias of Ml and M2 are equal. The average of G(t) can be calculated

by the area of one triangle divided by a half period of LO. The area of triangle is determined by

the peak transconductance and turn-on time A of both transistors.

Considering


V, = VL sin(mt) 4- =arcsin w /m-A = L
LO LO

Gm A. 2 g,V,V 2I,
G = =-x __-(4-14)
TLO,2 iLO iVLO

Total output noise spectral density is given as

2I,
i,2 = 4kTygm, + 8kTy--- (4-15)


The same conclusion on mixer noise dependence on LO signal amplitude and bias current

is given in [71]. The mixer in [72] is the same as the mixer used in this work. A NF vs. LO

power plot is shown Figure 4-6. It shows that increasing LO power lowers noise figure.























-3 -2 0 1 2
LOPwr dm

Figue 4-. N vs.LO pwerof Mxer
Inmie dsgn hgerbascurnticrassth rascnucaceofM adthreoe h
coneriongan. Evntog h uptniecnrbte yM n 2aeicesdb B
show inEuto -5niefgreomxri eue.AlrerL mltd nrae h

conerio ganadrdcsteniecotiuino wthn ai.Icesn h hne








mixer. (~m





Aovrso 20-Gz RFe front-en wth a oup n-cipe antenna has bee1 n dvlpd to dremonstreated the


foneasibiiyof i aNod e ocept o oe the no overall owrcosmtion of thecin par nreceivgter the ainof

wdthowncovete is kept as low eaus poissiblewhie g acd hirevnsufiiently lownvso gise figure. ully







dffeentiialciuitso Cd thought consm moeower t oeare utilied omk h connupino ection to the a o









dipole antenna without using a balun as well as to better rej ect the common-mode noise from the

digital circuits which will eventually be integrated.

Vdd


Ld1 ~~ Ld2 Ld3 Ld4



M 4~ LO -~M7 M8 M~-(9 1~

L3
M1 M2 1iM 6HC

L,1 ~Lg2MS6

RF+ Lsi Ls2 RF-C12


L1 5~L2



Figure 4-7. Schematic of LNA and Mixer.

Figure 4-7 shows the schematic of the RF Front-end including an LNA and a mixer. The

LNA utilizes the cascode topology. Source degeneration is used to generate resistance for input

matching. The output of LNA is capacitively coupled to the mixer. The mixer is double-balanced

Gilbert cell type. The conversion gain of the mixer is ~1dB. A differential inductor is inserted

between the drain nodes of two Tran conductors (MS and M6) to tune out the capacitance at

these two nodes. This increases the mixer gain and improves the image rej section of down-

converter [79]. For testing, each IF output is matched to 5002. The current sources in the LNA

and mixer are replaced by inductors to provide larger voltage headroom. Shielded pads are put

underneath both RF and LO ports to prevent the loss of signal and noise coupling associated with









substrate resistance [80]. Ground rings are placed around the transistors at minimum distance to

reduce the substrate loss. The gate of LNA and mixer are biased through 5-kGZ polysilicon

resistors. The LNA and mixer have separate supplies and large on-chip bypass capacitors are

placed between each supply and ground.


3mm-long zigzag dipole







Metal 1-4
0.88mm

.. Vias

Feed-line
Pad

0.83mm

Figure 4-8. Die micrograph and antenna cross section.

The performance of wireless communication is critically dependent on antenna. The recent

work [81] has shown on-chip antennas built on moderate-resistivity substrates (5-20 02)

sufficient for use up to 5m and possibly larger separations. The antenna used in this work is a

3mm-long zigzag dipole with a bend angle of 300, shown in Figure 4-8. The 3-mm length

corresponds to ~1/4 at 20GHz in free space. To reduce the antenna resistance, antenna built with

a thick metal layer is preferred. However, the technology only offers 0.34Cpm-thick metal 1-6

layers. The antenna is implemented in metal 1-4 layers to make the thickness of metal layers

used to fabricate on-chip antennas comparable to that of the previous work [81]. The design rule

limits the maximum metal width to 10Cpm. To satisfy the maximum metal-width rule, the antenna

is formed with 3-parallel 8Cpm traces separated by 0.8Cpm. The antenna is located ~50Cpm from the










chip edge. It is shown in [81] that closer distance between on-chip antenna and chip edge reduces

the attenuation due to lossy substrate. The die micrograph is shown in Figure 4-8. Antenna traces

cannot be seen, since they are built with the lowest 4 metal layers.The antenna is drawn to

illustrate the size and shape of the whole circuit. The antenna area is 3mm x 120Cpm while the RF

front-end excluding the antenna is 880 x 830Cpm2. The total area is 1.1mm2


. -10




-15

S-20


S-5


S-10






ct-20


18 20 22
(b) RF frequency (GHz)


1.5 2.5 3.5
(a) IF frequency (GHz)


Figure 4-9. Reflection coefficient at IF and RF ports.

To characterize the downconverter performance, the antenna is cut from the LNA and

mixer. S-parameters are measured at IF and RF ports by using HP8510C network analyzer. RF,

IF and LO ports are probed using ground-signal-signal-group (GSSG) probes. The reflection

coefficient is shown in Figure 4-9. At IF port, the reflection coefficient is below -10dB from

2.4GHz to 3.1GHz. At RF port, the reflection coefficient is below -10dB from 19.5GHz to

21.1GHz. The RF input and IF outputs are well matched at their respective frequencies.










10 12


5 _RF

10
Image rejection
o 20dB at 20GHz




o -A-1.5-V Vddc
0..-10 1.2-V Vdd

RF Images
-15


-20 4
18 19 20 21 22

RF Frequency (GHz)


Figure 4-10. The Gain and NF vs. Frequency plots for 20-GHz downconverter.

The conversion gain and noise figure measurements are performed at 1.5-V and 1.2-V

supply voltage. The results are shown in Figure 4-10. The power gain is measured as a function

of the RF input frequency. The LO frequency 3GHz below the RF frequency was swept with the

RF frequency. The external LO power applied to one LO port is 2dBm, equivalent to a peak-to-

peak voltage swing of 0.8V. The power gain of RF image is also measured. It is measured at the

corresponding RF image frequency. For instance, the image of 20-GHz RF signal is located at

14GHz, two times IF frequency away from the 20-GHz RF frequency. The image rej section of the

front-end is 24dB at 20GHz. This performance is achieved by using large IF and properly tuning

LNA and mixer. The single side band (SSB) NF is measured as a function of the RF input

frequency with fixed LO frequency of 17GHz.












40

20

EO
20


a 40

S-60

O 80

-100
-40 -30 -20 -10 0

Input Power (dBm)


A


40

20



-20

0- -40

-60
O
-80

-100
-40 -30 -20 -10 0
Input power (dBm)


B

Figure 4-11. Linearity of down-converter at Vdd of A) 1.2V and B) 1.5V.









Besides being the first receiver fabricated in a low cost foundry process to have an on-chip

antenna, the circuit achieves 9 and 6.6dB conversion gain and SSB noise figure at 20GHz,while

consuming extremely low power of 12.8mW with Vdd=1.5V. Compared to the LNA and mixer

combination of a 17-GHz front-end fabricated in a 130-nm CMOS technology [62], which has

been shown to possess competitive overall performance as receivers fabricated using a 100-GHz

fr SiGe BiCMOS technology [77], [78], the down-converter has comparable noise performance

while consuming less than half of the power. When the supply voltage is reduced to 1.2V, the

circuit has a maximum power gain of 7dB, minimum NF of 7.2dB. The power consumption is

less than 25% of the LNA and mixer in [62]. The linearity is measured with two RF tones at

20GHz and 20.02GHz with LO signal of 17GHz. Figure 4-11 shows the IIP3 measurement with

supply voltage of 1.2V and 1.5V. Table 4-1 summaries the measurement results.

Table 4-1. Performance of the RF front-end
Supply Voltage 1.5V 1.2V
RF 20GHz
IF 3GHz
Chip Area 1.1mm2
Power Consumption 12.8mW 7.3mW
LNA Current 4.7mA 2.8mA
Mixer Current 3.8mA 3.3mA
Power Gain 9dB 7dB
Noise Figure 6.6dB 7.2dB
Input IP3 -10.9dBm -11dBm


The operation of RF front-end with an on-chip antenna is demonstrated by transmission of

an AM signal and down conversion of this signal to IF. The measurement setup is shown in

Figure 4-12(A). The transmitted signal is generated by an Agilent 8254A. A 20-GHz carrier is

amplitude modulated with 100-k
modulation depth: m, the power difference in dB between that for a carrier and the sideband on

either side is expressed as,










Esu /E, = -201og(m) + 6 dB. (4-16)

Esub represents the power level of an either sideband while Ec represents carrier power level. For

m=50%, the power level difference between is 12dB.



GS e r Blu GSS


ea ~BalunG











BaluB











Figure 4-12. Interchip wireless communication over free space. A) Measurement setup and B)
Measurement environment.

The single-ended AM signal is converted to balanced signals using a balun and fed to a

transmitting antenna which is a 3-mm on-chip zigzag dipole with a signal-signal (SS) probe. The

power delivered to the antenna is 10dBm. The transmitting antenna is placed on a mobile probe

stand made of Derlin [81], which is type of plastic with dielectronic constant of ~3.7. The probe

stand is located 5m away from the receiver. The receiver is mounted on a thick glass substrate

isolating the effect from the metal chuck underneath. The RF, LO and IF biases are provided










using GSSG probes and DC probes. The IF output is amplified using an external amplifier with

26-dB gain. The measurement environment is shown in Figure 4-12(B) which is in the 5th-flOOT

lab.


-30
-IF signal

-50 -53.8dBm Noise floor of
-66.d~m 66d~ spectrum analyzer

-70



-90



-110



-1 30
2.9995 3 3.0005

Frequency (GHz)

Figure 4-13. Received spectrum.

The received (resolution bandwidth of 300Hz) spectrum is examined by using an HP8563E

spectrum analyzer. The output spectrum is shown in Figure 4-13. The power at 3GHz IF is ~-

53.8dBm. The power gain between transmitting antenna and receiving antenna is calculated to be

~-99dB including the effects of metal structures. The two sidebands 100kHz away from the IF

have power levels of ~-66.5dBm and -66dBm, which are 12.7 and 12.2dB lower than that of the

carrier. Those power levels are close to the theoretical values. This indicates that the transmitting

RF signal is picked up by antenna and down-converted by RF front-end. The extra sidebands in

the spectrum are due to spurs of signal generator. The background noise is ~2dB higher than that










of spectrum analyzer due to the noise resulting from the thermal noise of received signal and

noise of the down-converter.

For the first time, this work [82] shows that a pair of ICs with a compact on-chip antenna

can communicate over free space and it is feasible to implement a low-power 20-GHz down-

converter using mainstream digital CMOS technology.

4.4 A 20-GHz RF Front End Including LNA, Mixer and IF Amplifier

The previous RF down-converter with LNA and mixer has only 9-dB gain. A two-stage IF

amplifier is added to increase the overall gain to better suppress noise contributed by following

analog baseband stages such as variable gain amplifier and low pass filter. Its schematic is shown

in Figure 4-14. Figure 4-15 shows the diagram of this RF front-end. The circuit was once again

implemented using UMC 130-nm CMOS logic technology. The die photograph is shown in

Figure 4-15. The input/output reflection coefficients were measured with an HP8510C network

analyzer, and shown in Figure 4-16. The circuit was once again implemented using UMC 130-

nm CMOS logic technology.


Vout


Figure 4-14. IF amplifier schematic.











Mixer


Figure 4-15. A Front-end with an IF amplifier


2 2.5 3 3.5 4 20 21 22 23 24 25
Frequency (GHz) Frequency (GHz)


Measured matching properties at IF and RF ports.


90


Figure 4-16.











25

20 -4-- RF Gain
C-5-- RF Image Gain
.c 15

c 10




-5


19 19.5 20 20.5 21 21.5 22
Frequency (GHz)

Figure 4-17. Power gains at input and image frequencies.

The conversion gain is measured at varying RF and LO frequencies, keeping the constant

3-GHz IF. As shown in Figure 4-17, the maximum power gain achieved is 24dB at 20.5GHz.

The image rej section ratio is ~23dB. At 1.5-V Vdd, this RF front end only consumes 17.7-mW

power while achieving 29.5-dB gain. Compared to the front-end with LNA, mixer and IF

amplifier reported in [76] which achieves 34.7-dB at 58-mW power consumption, our circuit

shows a significant power reduction. Table 4-2 compares the circuit in [76] and our circuit.

Table 4-2. Performance comparison between our down-converter and the one in [76].
Circuit metrics [76] Our work
Vdd (V) 1.5 1.2 1.5
LNA Power (mW) 5.2 3.5 3.5
Mixer Power (mW) 27 3.8 3.8
IF Power (mW) 25.8 7.5 10.4
Total Power (mW) 58 14.8 17.7
Gain (dB) 34.7 24 29.5


4.5 Summary

This chapter first presented the CLNode system requirement, then demonstrated an 20-GHz

RF front-end with an on-chip antenna which can receive transmitted AM signal and down-










convert IF. This RF front-end consumes much lower power compared to those previously

reported circuits. For the first time, we demonstrated the feasibility of a pair of ICs

communicating with each other using on-chip antennas over free space. A RF down-converter

including LNA, mixer and IF amplifier which achieves comparable gain performance while

consuming much lower power has been demonstrated. These works show that it is feasible to

implement low power 24-GHz communication devices.









CHAPTER 5
BUILDING BLOCKS OF RECEIVER

5.1 Introduction

This chapter discusses the design of building blocks in the RF receiver except the RF front-

end presented in the previous chapter. Figure 5-1 shows a diagram of the receiver. The passive

mixer is briefly described in section 5.2. Variable gain amplifier (VGA) design is discussed in

section 5.3. A 2nd-order Butterworth low pass filter (LPF) design is presented in section 5.4. The

divided-by-8 circuit is briefly described in section 5.5. The image rej section filter in LNA is

discussed in section 5.6. Since the integrated transceiver shares one antenna, to reduce the loss

associated with a conventional T/R switch, a distributed switch method described in section 5.7

is utilized. In this section, driving LO from the synthesizer is also briefly described.


passive mixer
active mixer VGLPF -
baseband
LN IF ALO2 I
signal
VG LPF

BUFFER 8:1 LO2_Q

LO1

Figure 5-1. Diagram of Clnode receiver.

5.2 Passive Mixer

The second down-conversion in the receiver chain is accomplished with a passive mixer,

which consumes no dc power. MOSFETs can be easily used to realize the passive mixer. The

advantage of passive mixer over active mixer is its higher linearity and lower 1/f noise. But a

passive mixer does not provide conversion gain and isolation between RF and IF ports. Figure 5-

2 shows a passive double-balanced mixer consisting of four transistors in a bridge configuration.
































































































5 10


Figure 5-3. Gain vs. LO power in a passive mixer.





The differential signals LO and LO turn on and turn off transistors to change the polarity of



voltage at IF port. For instance, when LO is high and LO is low, Ml and M4 are turned on and



IF port has the same polarity as RF port. On the other hand, when LO is low and LO is high, M2



and M3 are turned on and IF port has the opposite polarity as RF port.


ItLLL


IF


Figure 5-2. Passive mixer.


111 111 111 I 111 I jl 11 111 11 111 11111 111 I I 11 1111 111 II II 11) III (tll Illi-VI~l IIIII 11 111
i I
i I
i I
'~~ '~~ '~~ '~' '~~ '~' I'~' ~~' '~'~~ '~~ '~~ '~~"~~
i i
i i r
i i i
i i
~~. ~I~. ~~~, .~, ~~, ~~, ~~..~~. ~~. ~~.
i I
i I
i
I
~ ~
i i
i i
r' ii
.i i i
~ i i
r
i r
i i
iC i i i
9 i ;
cP i i i
i
c
ri i i i i
~ J i I ;
i i
r
i i
ii i i i


-
0


-18



,-2


-"15 -10 -5 0
LO Power (dBm)










The passive mixer was designed and implemented in a 130-nm CMOS technology by A.

Verma [83]. All four transistors have width of 100 pm. This passive mixer is measured with 2.7-

GHz RF and 2.6-GHz LO frequency. This sets IF at 100MHz. The passive mixer conversion gain

vs. LO power is plotted in Figure 5-3. It shows that 2-dBm LO power corresponding to 0.4-V

voltage amplitude will give ~6-dB loss. This passive mixer was modified for integration into

Einal receiver design.


5.3 Variable Gain Amplifier (VGA)

Vbias Vbias


Figure 5-4. Schematic of the VGA and its basic amplification stage.

A VGA adjusts receiver gain according to the received signal amplitude. The VGA needs

to support 8 6-dB steps. A 6-dB amplifier is shown in Figure 5-4. Two R1 resistors form

common mode feedback with two upper PMOSs. Two R2 resistors form source degeneration. If

R2 is much smaller than the output impedance of two NMOS transistors, amplifier









transconductance is 1/R2. If R1 is much smaller than the output impedance of two PMOS

transistors, the output resistance of the amplifier is R1. Then, the amplifier gain is defined by

R1/R2. DC offset must be taken care of for circuits with high gain. The baseband circuit will

have three high-pass filters, one in front of the VGA to handle offsets from the preceding stages,

one in front of the last four stages of the VGA and one in front of the LPF to handle the offsets

from the VGA. The poles of filters are located at ~200k
capacitor and a 500-kGZ resistor.

















In bOut




Figure 5-5. Gain control scheme.

The gain control method is shown in Figure 5-5. There are eight switches attached to the

output of eight amplifier stages. These switches are controlled by b0-b7 generated by a 3-bit

decoder. At each gain step setting, there is only one gate voltage set to high while all other are

set to low. For instance, if the control pattern is "00000001", only the switch controlled by b7 is

on and gain is 48dB. If the control pattern is "10000000" then the only switch controlled by b0 is

on and the VGA has the lowest gain of 6dB.









To measure the VGA, differential input signal has to be generated. A Balun used at high

frequencies to convert single-ended signal to differential ones is replaced by a discrete

differential amplifier (AD8138) [84]. As shown in Figure 5-6, two printed circuit boards (PCBs)

are connected to the input and output of VGA by semi-rigid cables and two pairs of GSSG

probes.


Function Spectrum
Generator Analyzer

Semi-rigid cables & GSSG probes



On-chip
p : ;V GA





Figure 5-6. Measurement setup of the VGA using differential amplifiers as Baluns.

To measure the gain of VGA, two steps are needed. First a THRU structure on a GGB

calibration substrate is used to connect two PCBs using the semi-rigid cables and GSSG probes.

With a 2-MHz sine wave generated from an Agilent 33120A function generator, the power (Pthru)

read from the spectrum analyzer is recorded. Then the TRHU structure is replaced by the VGA

circuit. The output power (PVGA) at varying gain control selection has been measured. The ratio

between PVGA and Pthru giVCS the voltage gain. The measured gain are shown in Figure 5-7. The

VGA gain ranges from -10dB to 35dB over 8 control steps. However, the overall gain is 13dB

lower than the design target.

The gain suddenly drops at step 4. This can be explained using Figure 5-8. When the step 4

is chosen, switch B3 is turned on and it bypasses all the following 4 gain stages and connects

Couple and Cload in SeTiCS forming a capacitive voltage divider. Clad is single ended input









capacitance of AD8138 which is 2pF while Ccouple is 1.5pF, attenuation is 7.3dB. In normal

operation, the VGA will not see such large capacitive load, and no such gain drop occurs.


I2 3 4 5 6 7
Gain Step


O


-10 I


Figure 5-7. VGA gain vs. gain control step.


Vbias


Vbias





Ccouple


B3L


Figure 5-8. Capacitive voltage divider in the configuration for gain step 4.

5.4 Baseband Low Pass Filter (LPF)

The LPF implements the functions of the chip matched filter (CMF) and anti-aliasing filter

for the ADC. A second-order Butterworth filter provides a good approximation to the spectral


I load




































- half-sine filter

-2nd-order Butterworth filter


shape of the ideal half-sine chip pulse sin(nit / Tc)I-r (t) and~ is a practical^' chic for the at-alias

filter. In particular, the Butterworth filter should be designed for a nominal bandwidth of ~

0.3Re, where R, is the chip rate of 51.2 MHz. This leads to a filter bandwidth of 15.36 MHz.

Figure 5-9 compares the frequency response of the half-sine filter and 2nd-order Butterworth

filter. The CMF's equivalent noise bandwidth is the primary factor that affects the performance,

while the output pulse shape has only weak influence. The equivalent two-sided noise bandwidth

is 0.62R, for the half-sine filter. For a 2nd-order Butterworth filter, the equivalent noise

bandwidth is 1.11 x BW3dB [85] Since its 3-dB bandwidth is chosen as 0.3Re, the equivalent

noise bandwidth for this filter is ~0.67R,. Two noise bandwidths would lead to a 0.3-dB

difference in output noise power between two filters.


O


-10


S-20





-50


0 1 2 3
Normalized freqeuncy (flR,)

Figure 5-9. Half-sine and 2nd-order Butterworth filter frequency response.

The LPF can be implemented differentially without employing a common mode feedback

(CMFB) loop [86] as shown in Figure 5-10(A).The common-mode voltage is set by adding a

diode-connected NMOS at the internal node of a conventional Gyrator.










gm0Z


1/gm


1/gm


A B

Figure 5-10. A)A lossy biquad and B)its equivalent circuit.

Impedance looking into the Gyrator is

sC 1
Z= ,+ (5-1)
g,, g,,

Effectively, Z is the series connection of an inductor with value of C/g,, and a resistor

with value of 1/ gm, The equivalent circuit is shown in Figure 5-10(B). It can be shown that


2g,,
FLP 2g"(5-2)
"'+ ++1
2 g, g,,

When g,,, is chosen to be 2g,,, this expression becomes


Vou 1
0"' -(5-3)
----+---+1
2 g2 g,,

which can be rewritten as

Vou 1
2" (5-4)
"+- +1


where coo is -A g,,,C and Q is 1/JZ It is a 2nd order Butterworth-type LPF.









The feature of this circuit is that every transconductor output voltage is determined by

diode-connected circuit. This eliminates the requirement of common-mode feedback circuit. The

positive transconductance in Figure 5-10(A) can be implemented using a negative transconductor

and a gain stage with -1800-degree phase shift. It turns out that in a differential circuit, it is not

necessary to implement such a gain stage. We can connect out-of-phase output signal to the

negative transconductor.




4Io 2Iod Out+



1 I~



IV

I4 4Io 2Io Oult-





Bias circuitry Core of the LPF

Figure 5-11. Schematic of the LPF.

The pseudo-differential circuit implementation is shown in Figure 5-11. All the NMOS

transcondutors in the LPF have the same gs To implement positive gm in Figure 5-10(A), the

negative output is connected to a negative g,.When the value of C' s are fixed, the cutoff

frequency of LPF is determined by gm which can be controlled by the bias voltage ygm The

current source in Figure 5-11 is implemented with a PMOS current mirror. The current in whole

circuit is determined by Vgm, so that the bias voltage for PMOS current mirror should be










controlled by Vgme The filter exploits the near-square-law behavior of long (2Cpm) NMOSFETs to


partially cancel nonlinearity. Considering the long channel drain currents of two input NMOS

transistors


If = (V + k d n2 With f = Pn xW,



I, (V, ) (5-5)
2 2

where VdiS differential input. Subtraction of I, and Id TOSults in the differential output

current lo


I, = I~ I, = p(V, vn) d (5-6)

Hence, the differential output current is linear with the differential input voltage.


1 -----------8.00E-04
Vout mea

8 -- Vout sim ,~ 7.00 E-04
-A--~ IDDYme AAA 6.00E-04
0.7 -1 A IDD sim AA~a
A 5.00E-04
0.6 A

0.5 4.00E-04 a

0.4 A3.00E-04
0.3 -A
AAA 2.00E-04
0.2 -A
0.1 1.00E-04

0 rrrrlrrrrr 0.00E+00
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vgmc[V]

Figure 5-12. LPF Vout and Idd vs. Vgme.

A test circuit is fabricated in a 130-nm CMOS technology. The size of NMOS transistors is

1.2Cpm/2Cpm and that of PMOS transistors is 2.4Cpm/2Cpm. A Long-channel device suffers less

channel-modulation effect and works closely in the square-law region. Measured DC










characteristics with a 1.2-V power supply are shown in Figure 5-12. A plot of measured 1I]Tvs.


Vg,e, from 0.5V to 0.8V is shown in Figure 5-13. The plot clearly shows that the NMOS

transistors are working in the square-law region.


0.025


0.02


0- 0.015


a0.01


C~0.005



0.4 0.5 0.6 0.7 0.8 0.9

Vgmc [V]

Figure 5-13. Near-square-law of Idd vs. Vgme.

The AC response is tested with GSSG probes using an Agilent 5230A 4-port PNA. The

network analyzer can cove a frequency range from 300 k
to first use E-cal to calibrate four cables and then use port-extension function to calibrate out

probe phase delay. Measured 4-port S-parameters are imported into Spectre using an N-port

component in analogLib. An AC analysis results in the LPF frequency response in Figure 5-14.

Since device g,, is proportional to~lj~ Equation 5-4 indicates that LPF corner frequency is


proportional to JI. The measured corner frequency vs. J is shown in Figure 5-1_5. The

corner frequency varies from 24.2 to 44.2MHz by 1.83 times (or +29% tuning range) when

~J~is changed by 1.91 times. It indicates that the corner frequency is close to linear with g,, .





-10


-15


-20


-Vgmc=0.5


-Vgmc=0.55


Vgmc=0.6 -Vgmc=0.65


-Vgmc=0.7

-Vgmc=0.8


Vgmc=0.75


-25 -


-30 -
1.00E+05


1.00E+06


1.00E+07


1.00E+


Freq [Hz]


Figure 5-14. Frequency response and tuning of LPF.


LI.
3 5
O


0.005


0.01


0.015


0.02


0.025


Sqrt(ldd) [sqrt(A)]

Figure 5-15. LPF cut-off frequency vs.Sqrt(Idd).










Equation 5-4 indicates the ideal in-band gain of LPF should be OdB while both simulation

and measurement show in-band loss. The discrepancy can be explained by taking the device

output resistance into account. The ideal LPF network in Figure 5-10(A) is redrawn using

different diode-connected NMOS transconductance gg and g~ as illustrated in Figure 5-16.


gg and g~ represent the equivalent transconductance combining gm and the device output

resistance.





b 1
gm = gm + b (5-7)


As shown in Figure 5-16, r ~, is that of a parallel combination of four NMOS and PMOS


output resistance, while robut is that of a parallel combination of two NMOS and PMOS output

resistance.


2gm
VinaZ



VLP






Figure 5-16. LPF including device output resistance.

The transfer function in Figure 5-16 can be shown as

VLP 2gZ (g -gi + g )
22 h (5-8)
+ sc +1
g, -g +g gm -g +gi










where the in-band gain is


2g2
a b (5-9)
g,, -g,, + g2,

Since g," and g~b are both greater than g,, the in-band gain is less than 1. Let' s examine

how the in-band gain changes with bias current. To the 1st-oder approximation, assuming


g,, = a TJ, 1/ra, = mlbra andl/r ,, = nlbras Eqluation 5-9 is rewritten as


2a2
A = (5-10)
22u m nJ+ buras

It shows that the LPF in-band loss increases with bias current. This trend has been verified

by the simulation and measurement. Equation 5-8 also indicates that LPF corner frequency and

network Q are affected by the device output resistance.








m-40-

0 -60-

S-80-

-1 00 A

-120
-30 -25 -20 -15 -10 -5 0
Input Power [dBm1

Figure 5-17. Simulated LPF IP3.

IP3 of LPF is simulated by using two input tones at 7MHz and 8MHz with 0.6-V Vgme.

Output power of fundamental tone at 7MHz and 3rd-order intermodulation distortion tone at

6MHz are plotted in Figure 5-17. Simulated LPF IP3 is 6.4dBm, or -6.6dBVrms and PldB










simulated at 7MHz is -6.8dBm, or -19.8dBVrms. Table 5-1 compares the measured and

simulated results of in-band loss and corner frequency.

Table 5-1. Measured and simulated in-band loss and corner frequency of the LPF.
Measured .Simulated
Measured mn-band Simulated mn-band
Vgma cut-off frequency cut-off frequency
loss(dB) loss(dB)
(MHz) (MHz)
0.50 0.59 24.2 0.73 24.2
0.55 1 28.2 0.78 28..2
0.6 1.34 31.2 0.84 30.2
0.65 1.76 35.2 0.9 34.2
0.7 1.95 38.2 0.99 37.2
0.75 2.3 42.2 1.13 39.2
0.8 2.8 44.2 1.49 41.2


5.5 Frequency Divider

As shown in Figure 2-3, the radio uses dual down-conversion architecture. The first LO

signal is at 21.3GHz generated by a frequency synthesizer and the second LO signal of ~2.7GHz

is generated by a frequency divide-by-8 circuit. This divider is implemented by cascading three

2:1 current mode static frequency dividers.





D QI -D QI OUT

-Db Qb Db Qb OUTb

CK
CKb


Figure 5-18. Block diagram of the 2: 1 static frequency divider.

The divider shown in Figure 5-18 was designed by Changhua Cao [87]. For completeness,

its function is briefly described. The divider is based on the master-slave D-type flip-flop in

which the inverted slave outputs are connected to the master inputs. This type of divider can

achieve a wide operating frequency range, consuming a smaller silicon area while generating









quadrature signals. As shown in Figure 5-19, each master-slave flip-flop is implemented using

current mode logic (CML). The master and slave stages consist of an evaluate stage (M1,3,4) and

a latch stage (M2,5,6). The current sources in conventional CML latches are omitted in Figure 5-

19 for low voltage operation.



M7 M t

OUT

I Ij jtill hYt~i"


IK II( In ~- 1 K~GC

I I I----------------------------









|CK(C M1 C)b M2 |C CK



M |






JL(C~C +C )s2
























Notch filter Notch filter



Figure 5-20. 2-stage LNA with notch filters at the image frequency.


1200

1000

S800

S600

S400

200


10 15 fsig20 fRF 25 30
Frequency [GHz]

Figure 5-21. Input impedance of the notch filter vs. frequency.

When the inductor and capacitors are ideal without any loss, at image frequency, the

impedance of filter will be zero while at RF frequency the impedance of filter is open. This will

provide infinite image rej section. However, in real circuit, passive components have finite Q. The

filter impedance |Z(s)|I including the resistances of inductor and capacitors is plotted in Figure 5-

21. The impedance is not zero atJmage and infinite at foRF. However, the magnitude of impedance





atJmage is still much lower than that at fw which makes the gain at the image much lower than

that at RF. The 2-stage LNA combined with notch filters should have image rej section up to

40dB.

5.7 Integration of Transceiver

The CLNode uses time division duplex (TDD) which means only either the transmitter or

receiver is active at a time. This allows the use of one antenna instead of two. This reduces the

chip area by ~3mm x 0.12mm.


Vg2


PA


LNA


Figure 5-22. Distributed switching for the receiver and transmitter.

Generally, a T/R switch is required to control the connection between the receiver and

transmitter to the antenna. However, it is difficult to implement 24-GHz single-pole double-

throw (SPDT) switches with low insertion loss in bulk CMOS processes. For example, switches

implemented in a 130-nm CMOS process achieve 1.8-dB insertion loss at 15GHz [89]. For a


TxEn -









switch operating at 24GHz, the insertion loss can easily go above 2.5dB. The switch will degrade

the input SNR and increase noise figure of the receiver chain. Because of this, instead of using a

T/R switch, the switching function is merged into the PA and receiver [90], as shown in Figure

5-22. In the transmit mode, varactor Ctune is adjusted to make PA output impedance close to 5002.

At the same time, TxEn is set high to turn on transistor Mtune to short the gate of Ml to ground.

This also reduces voltage swing on the gate of Ml. The impedance looking into the receiver will

be coLg which is ~150jGZ. This assures the impedance matching between the antenna and PA

output to deliver maximum power while protecting the LNA. When the receiver is on, Ctune is

adjusted to make the PA output impedance inductive impedance of ~100jGZ at 24GHz and TxEn

is low to turn off Mtune. In simulations, these increase the noise figure by 1.3 dB and decrease

output power of PA by 0.8dB.

The synthesizer provides the 21.3-GHz LO signals to the receiver and transmitter. To

assure sufficient LO drive, four separate buffers are inserted between the synthesizer and each

mixer and divider in the receiver and transmitter. These buffers are implemented with tuned

amplifiers. Figure 5-23(A) shows the frequency synthesizer output to these different buffers.

Figure 5-23(B) shows the location of these buffers on the chip. Consuming 4-mA DC current

from a 1.5-V supply, the frequency synthesizer output buffers provide ~0.4V signal to the TX

and RX buffer inputs.

The 8:1 divider of receiver needs to drive the gate of passive mixer at ~2.7GHz. Instead of

using a tuned amplifier which consumes too much area, an inverter chain is used as 2.7-GHz

buffers, as shown in Figure 5-24. The interconnection between the divider output and passive

mixer is longer than 1mm and is modeled as a transmission line. A 3-stage tapered buffer at the

divider output drives a transmission line and a large buffer that directly drives the passive mixer.













RX down-conversion mixer

RX divider







TX up-conversion mixer

TX divider


Figure 5-23. A) Integration of the frequency synthesizer, transmitter and receiver. B) LO buffers
between receiver, transmitter and frequency synthesizer.














Passive
8:1 Divider
mixer




Figure 5-24. Inverter chain is used to drive the passive mixer.

5.8 Summary

In this chapter, the key building blocks in a RF receiver implemented in a 130-nm CMOS

technology are presented. These blocks are VGA, LPF, frequency divider, passive mixer, LO

buffers and image rej section filter in the LNA. Lastly, a distributed switch has been incorporated

into the receiver and transmitter to lower switch loss.









CHAPTER 6
FULLY INTEGRATED RECEIVER AND WIRELESS LINK DEMONSTRATION OF CINODE
TRANSCEIVER

6.1 Introduction

Following the successful implementation of individual building blocks, the blocks were

integrated into a receiver chain. The receiver was also integrated with the transmitter [87]and

frequency synthesizer [91]. The receiver has been characterized using an external LO source as

well as LO provided by the frequency synthesizer. Using the transceiver [93], wireless

communication up to 5m has been demonstrated. This completes the goal of demonstrating the

feasibility of implementing a transceiver with on-chip antennas for general purpose

communication. This chapter will first present the measurement results of receiver in section 6.2.

The frequency synthesizer is briefly described and receiver measurement results with the

frequency synthesizer are discussed in section 6.3. Finally, the wireless communication link

between the receiver and transmitter that are 5m apart is demonstrated in section 6.4.

6.2 Receiver Measurement Using External LO Source

The receiver as well as the transmitter and frequency synthesizer is implemented in the

UJMC 130-nm logic CMOS. The die micrograph of CINode transceiver is shown in Figure 6-1.

This 5mm x 5mm die also includes a 3mm x 3mm baseband processor developed by S. Hwang.

The effective receiver area excluding the bonding pads is ~ 3mm2. Similarly, the effective

transmitter area is ~1.5mm x 0.8mm and the frequency synthesizer is ~0.8mm x 0.5mm. The on-

chip antenna is 3.8mm long and built in metal layers 6-8. A large area of p-well block is placed

underneath the on-chip antenna to reduce substrate loss [14].

Among 29 pads of the receiver for outputs and bias, 8 pads are bonded and the rest of the

pads are connected using a 21-pin DC probe. Of the 8 wire bonded pads, 4 pads are baseband AC

output pads. To drive the 50-02 load of spectrum analyzer, 0-dB gain buffers using AD8138 on a












.... shamssilnesmassems
i .. -- mageagama mssu
eMI .. g.. g a
n1 **r



LA aggage ~~



gam e M







Figure~II 6-.Demcorp ftetasevradbaseband processor











1 11111111111=









Figure 6-2. Rie irga o h anceiver boar baeand die wre bndin









PCB board are added. The differential input capacitance of AD8138 is 1-pF. The board also

facilitates wire bonding of the transmitter and frequency synthesizer. The receiver board and an

enlarged photo illustrating receiver bonding are shown in Figure 6-2. The board is fabricated

using FR-4 with dielectric constant of ~4.5. The board thickness is 60mil. The surface finish is

soft bondable gold for the wire bonding. The outputs of baseband I/Q signal are connected to

measurement equipment using standard SMA connectors attached to the board. The ground

plane is cut out underneath the die to reduce the reflection problem that can degrade the dipole

antenna performance.

The receiver is first characterized using an external LO signal. The single-ended signal

output of a signal generator is converted to differential by an off-chip balun and then fed as

inputs to the drivers for the RF active mixer and divider. This is done using a GSSG probe.

Figure 6-3 shows the baseband output when RF input signal frequency fry, is 21.605GHz with -

90-dBm available power to the input of the receiver. The antenna is connected to the RF input

pads of receiver during the measurements. This shifts down the turned frequency response. LO

signal frequency, fLO, is 19.2GHz. The baseband signal is supposed to be frt-fLO/8x9 which is

5MHz, as shown in Figure 6-4. This result shows that the receiver has successfully down-

converted RF input to baseband using dual down-conversion. The baseband power is -22.2dBm.

The corresponding receiver gain is 67.8dB. (This estimation is based on the assumption that the

antenna impedance is well matched to 5002 and the power delivered to the input GSSG pad is

evenly divided between the on-chip antenna and the receiver.) When TxEn signal in Figure 5-22

is set to 1.2V, the LNA gate is shunted to ground and the baseband signal disappears. The

frequency response is shown in Figure 6-4. RF and LO frequencies are varied to keep the

baseband output frequency at 5MHz.The receiver gain peaks between 21.5GHz and 22.5GHz.















-22.2dBm


-20




0

-60






-80


2.5 3 3.5 4 4.5 5 5.5 6

Baseband Frequency [MHz]

Figure 6-3. Receiver baseband signal output spectrum.


70


65





S55


Em~ 50


6.5 7 7.5


20 21 22 23 24

RF F ransllan ICy 01171

Figure 6-4. Gain vs. frequency of the receiver with an on-chip antenna connected to the RF
input pads.














-20


S-40


a,-60


-80


-1 00
0 10 20 30 40 50
Frequency [MHz]

Figure 6-5. Receiver noise floor illustrating the filter characteristic.

The baseband LPF frequency response is characterized by looking at the frequency

response of noise floor, as shown in Figure 6-5. This figure spans from DC to 50MHz. There is a

dip at DC which shows the high pass filtering of DC offset cancellation. A 5-MHz baseband

signal down-converted from RF is also shown. The 3-dB cutoff frequency is ~23MHz. Using an

HP8508A vector voltmeter, baseband I/Q signal mismatch is measured. It is found gain

mismatch is 1.4dB and phase mismatch is 8.50. The main cause could be mismatch between LO

lines driving I/Q passive mixers, as shown in Figure 6-1. These lines have quite different shapes

even though they have the same length. The better way is to route LO lines closely and then split

I/Q lines at a symmetric point which has same distance to I/Q mixers. The power consumption of

receiver is summarized in Table 6-1. Total receiver power consumption is 58.9mW. The signal

path including LNA, mixer, IF amplifier, baseband amplifier, LPF and output buffer consumes

34.9-mW power, while the LO buffers and divider consume 24-mW.









Table 6-1. Power table of the receiver.
Receiver blocks Vdd (V) Current (mA) Power (mW)
LNA 1.5 4 6
Mixer 1.5 3 4.5
LO1 Driver (for
1.5 6 9
mixer and divider)
IF Amp 1.4 11 15.4
LO2 Driver (for
1.5 7 10.5
passive mixer)
Divider 1.5 3 4.5
Baseband 1.5 2 3
Output Buffer 3 2 6
Total 58.9


All the measurements discussed so far are made using receivers with an on-chip antenna.

To make accurate gain and NF measurements, on-chip antennas on two boards are cut from the

receiver. One board shows that when input RF signal is at 21.605GHz with -83.6-dBm power

and LO signal is at 19.2GHz, 5-MHz baseband signal power is -11.3dBm which translates to

72.3-dB Rx gain. Then noise performance s characterized by terminating the external balun at

RX input with a 50-02 resistor. The noise floor at 5-MHz baseband output is -38.2dBm with a

100-k
NF=-3 8.2-(- 174+72.3 +5 0) = 13 5dB

Note this NF number is single side band (SSB) NF. The noise at 5-MHz is contributed by

two RF side bands at 21.605GHz and 21.595GHz, respectively. Since signals will also be present

at these two side bands, double side band (DSB) NF which is relevant for the system is 10.5dB,

or 3dB lower than SSB NF. Figure 6-6 depicts the gain and DSB NF of the receiver on another

board as a function of the input frequency, showing a 66.5-dB peak gain and 12.5-dB NF at

21.6GHz. IP3 is tested using a 19.2-GHz LO signal and two RF input signals at 21.605GHz and

21.60502GHz. Figure 6-7 shows the measured IIP3 is -60dBm. These two "blockers" are in band









and no filtering on down-converted baseband "blockers" causes IP3 limited by last stage. The

measured performance is summarized in Table 6-2.


19 21 23 25 27
RF frequency [GHz]


Figure 6-6. Frequency response of RX gain and NF.


20

10


-85 -80 -75 -70
RF input power [dBm]

Figure 6-7. IP3 measurement of whole RX chain.


-65 -60 -55









Table 6-2. RX performance summary.
Circuit metrics Measured results
Peak gain 72.3dB
Noise Figure (DSB) 10.5dB
IIP3 (two in-band tones) -60dBm
Power consumption 58.9mW
Technology 130-nm logic CMOS
Area 3mm2


6.3 Receiver Measurement Using On-chip Frequency Synthesizer

A fully integrated receiver has also been characterized with an on-chip frequency

synthesizer. The frequency synthesizer is designed by Y. P. Ding and the synthesizer integration

was accomplished with her help. Its design has been discussed in [91]. A simple functional

description of frequency synthesizer is given here for completeness.


PFD and CP Loop Filter VCO
9rer(s) ~out(S)
I ~ Ipl2xC I ZF(S) I IKvco/S


~div(S)
Divider

-N


Figure 6-8. PLL-based frequency synthesizer.

Figure 6-8 depicts a block diagram of integer-N PLL-based frequency synthesizer. A phase

and frequency detector (PFD) compares the phase and frequency difference between the

reference signal and frequency divided VCO output. The PFD generates pulses with width

proportional to phase difference. The charge pump (CP) senses the pulse width and inj ects the

corresponding amount of current into the loop filter. The loop filter voltage is used to control the









VCO and the filter also attenuates the unwanted spurious tones produced by the charge pump.

With the PLL locked, VCO output frequency tracks the input reference frequency with a ratio of

N:1i. N is the divider ratio. For the measurements, N is set to 256. The performance of the

frequency synthesizer is summarized in Table 6-3.

Table 6-3. Frequency synthesizer performance summary.
Circuit metrics Measured results

Prescaler power 6mA @ 1.5V (9mW)
VCO power 5mA @ 1.2V(6mW)
VCO buffer power 3mA @ 1.2V(3.6mW)
PLL output buffer power 10mA @ 1.2V (12mW)
PLL total power 31.8mW
VCO tuning range 2.5GHz (13.4%)
In band phase noise -65dBc/Hz @ 50k Out of band phase noise -121dBc/Hz @ 20MHz
PLL locking range 1 7.5 GHz- 19.7GHz
Reference spurs 33-37dB below carrier


A 16-pin probe is used to provide bias and reference signal to the PLL. The divide ratio of

the PLL is 256. With RF input signal at 21.7GHz and PLL reference signal at 75.33MHz, the

baseband output signal is at 21.7GHz-75.3 3MHzx256/8 x9=4.96MHz. The baseband spectrum is

shown in Figure 6-9. RF input power is -70dBm. Figure 6-10 shows the output spectrum of the

baseband signal with a reduced span. Because the LO is generated by a synthesizer, the baseband

signal shows a similar skirt shape spectrum as the synthesizer output.

The measured phase noise of baseband signal is shown in Figure 6-11. This shows that the

frequency synthesizer is working properly with the receiver. Measuring the phase noise from

baseband signal could be an effective way to evaluate the phase noise performance of an

integrated frequency synthesizer if there is no other way to access the PLL output. Outside the










ATTEN
RL


10dB
OdBm


MKR -13.68dBm
4.97MHz


10dBI


CENTER 5MHz SPAN 10MHz
*RBW 9. 1kHz *VBW 1 kHz SWP 864ms

Figure 6-9. The output spectrum the RX when the LO is driving from synthesizer


ATTEN
RL


10dB
OdBm


MKR -12.1idBm
4.96MHz


10dBI


CENTER 4.96MHz SPAN 2.000MHz
*RBW 3.0 kHz *VBW 100Hz SWP 51.98sec


Figure 6-10. The output spectrum of RX when the LO is generated using an on-chip synthesizer.
The span is reduced to 2MHz to show the skirt.






















LO loop bandwidth
RX LPF cutoff frequency


Carrier Power -12.6 dBm
Ref -40.00dBclHz
10.00 dB/


Atten 10 dB


100 MHz


10 kHz Frequency Offset

Figure 6-11. Phase noise of the baseband signal.


1 2 3 4 5
Gain control step

Figure 6-12. Baseband power versus different VGA gain setting.


6 7










loop bandwidth of the PLL, the noise floor is determined by input and receiver noise shaped by

the low pass filter. Integrating phase noise -64dBc/Hz at 50-k
bandwidth shows a -9-dB RX SNR. Since system Eb/No requirement is 18dB and data rate and

noise bandwidth are 100k
means that measured RX SNR meets system requirement. Figure 6-12 shows the output power of

bandband signal versus the VGA gain setting. The input RF signal is at 21.7GHz with -70dBm

available power while the reference for the frequency synthesizer is at 75.33MHz. When the

control bits BoB1B2 of VGA change from "1 10" to "000", the baseband power changes from -

48.7dbm to -16.4dBm. The average gain step is 6.4dB which is close to simulated 6-dB per gain

step.

6.4 Wireless Communication Link Demonstration

With the receiver and frequency synthesizer working together, it is feasible to demonstrate

a wireless communication link between the transmitter and receiver using on-chip antennas. The

transmitter has been designed and characterized by Changhua Cao [87]. Figure 6-13 shows the

building blocks in the transceiver. A single-tone signal is generated from TX and delivered to an

on-chip antenna by a PA. At 5m away, the receiver picks up the signal and down-converts it to

baseband.

Figure 6-15 shows the setup and environment for wireless link demonstration. The receiver

is placed on the probe station in a metal cage. A 5-mm thick glass substrate is attached to the

bottom of the receiver board to reduce the effect of metal chuck on the on-chip antenna. A 21-pin

probe and a 16-pin probe are landed on pads for biasing the receiver and PLL. However, these

DC pins could affect receiver antenna by disturbing EM field near the antenna. This effect needs

to be further investigated. Out side the cage, the transmitter is placed on a cart 5m away. All the






































Figure 6-13. Wireless communication link between the transmitter and receiver.


edFllillk9



Figure 6-14. Transmitter on board and die wirebonding.












































I10 ..II.ill..1.11.1.11,11.ll.I 1.11.,111.11,. .11.1II....
M II5 Ill II


Figure 6-15. Wireless link measurement setup and environment.


ATTEN
RL


10dB
OdBm


MKR -38.3dBm
4.825MHz


10dBI


CENTER 4.925MHz
*RBW 1 kHz


SPAN
*VBW 1 kHz


5MHz
SWP 6sec


Figure 6-16. Receiver output spectrum.









bias lines are connected by patch cords to dc sources. The transmitter total power consumption is

128mW

Both TX and RX synthesizers work in integer-N mode with a divide ratio of 256. With a

75.3 5-MHz TX reference frequency, transmitter board transmits single tone signal at ~21.7GHz.

The frequency was limited by the maximum frequency of synthesizer integrated with the

transmitter. A horn antenna with 20-dBi gain located at 3m away from the transmitter picks up

~-73dBm power. The PLL reference frequency on the receiver side is 75.33MHz. The receiver

baseband output is at 4.825MHz with power of -3 8.30dBm as shown in Figure 6-16. This is the

first time a fully integrated CMOS transceiver pair has established a wireless communication

link using on-chip antennas.

6.5 Summary

A fully integrated 24-GHz CMOS receiver is demonstrated for the first time. One receiver

achieves a 72.5-dB peak gain and 10.5-dB NF at 21.6GHz. The whole receiver consumes 58.9-

mW power. Working with an on-chip frequency synthesizer, for the first time a wireless

communication link has been successfully established between a fully integrated transmitter and

a receiver with on-chip antennas that are separated by 5m. The RF portion of CINode has been

successfully implemented. This is a maj or step toward the realization of a true single chip radio.









CHAPTER 7
SUMMARY AND FUTURE WORK

7.1 Summary

Imagine a tiny radio only packaged with a battery! The possibility of a single chip radio

has become more realistic than ever with the demonstration of a fully integrated 24-GHz CMOS

transceiver communicating using on-chip antennas. This Ph.D work demonstrated a fully

integrated transceiver [93] including a receiver, a transmitter [87] and a synthesizer [91].

The receiver chain consists of an LNA, an active mixer, an IF amplifier, a passive mixer,

variable gain amplifiers and low pass filters for baseband I/Q signals. All the circuits are

differential to reduce the impact of switching noise of digital circuits which will eventually be

integrated with the transceiver. High frequency LNA design is analyzed in terms of gain and

noise Eigure. Substrate resistance has been found to be a critical factor which degrades LNA

performance. To reduce this effect, a unique topology using an inductor at the gate of common

gate stage in a cascode LNA has been demonstrated to boost the gain while greatly reducing the

power consumption. The 26-GHz LNA only consumes 0.8-mW power while achieving 8-dB

gain. A 20-GHz RF front-end including an LNA and mixer achieves 9-dB gain and 6.6-dB NF

while consuming 12.8-mW power from a 1.5-V supply. Using this front-end and an on-chip

antenna, AM signal transmitted from 5-m away was successfully picked up and down-converted

to IF frequency. Finally, an entire receiver chain is integrated in the UMC 130-nm logic CMOS

technology. The receiver achieves 72.5-dB gain and 10.5-dB DSB NF with 58.9-mW power

consumption. A 5-m wireless communication link is established using a receiver and a

transmitter both working with an on-chip frequency synthesizer and an antenna. ~21.7-GHz

single tone signal generated by the transmitter is down-converted to ~5-MHz using the receiver.

This is the first time a wireless link is demonstrated between a pair of fully integrated CMOS









transceivers with on-chip antennas. This is a maj or milestone toward the realization of a single-

chip radio. Lastly, this work has shown that 24-GHz RF circuits with acceptable performance

and power efficiency can be implemented using thel30-nm CMOS.

7.2 Suggested Future Work

The work presented in this thesis has shown the feasibility of implementing a single chip

radio. To incorporate these circuits into real applications and products, there are still much to do.

The list of suggested future works includes:

Co-design of an on-chip antenna and circuits: One unique feature of CLNode is to integrate

an on-chip antenna. However, its advantage has not been fully exploited. The antenna, LNA and

PA were treated as separate blocks and make each of them matched to 5002. Logic questions are:

since now we have the feasibility to control on-chip antenna impedance, is 50-02 matching an

optimum option? Even if the impedance change may have deleterious effect on PA output power

and LNA NF, is there an optimum matching impedance for the whole wireless link between a

transmitter and a receiver? The answers to these questions will be fundamental contributions

from this work.

On-chip bias reference generation: As shown in Figure 6-2, to make the receiver,

transmitter and frequency synthesizer work simultaneously, more than 60 DC lines have to be

connected from the chips to external DC sources. It takes great efforts to properly connect these

wires and it is time consuming. Bias circuits should be incorporated into the chip.

Automatic Gain Control (AGC): The gain control in the current version is implemented

using a manually controlled variable gain amplifier. To automatically control the gain, two

options can be considered. One is to use commonly used AGC which has a power detector to

sense the signal amplitude and adjust the gain settings. Another is to use the baseband processor

to sense the BER to adjust the gain settings.









Integration with ADC and baseband processor: This is the last maj or step toward a fully

integrated radio. Since the baseband processor designed by Seon-Ho Hwang is fully functional,

Integration of the RF transceiver with the baseband processor and ADC should be possible in

near future. This will indeed be exciting!









APPENDIX
DERIVATION OF NOISE FACTOR OF CS-LNA

Figure A-1 shows 3 noise sources in CS-LNA: channel thermal noiseid, induced gate noise


i, and source voltage noise v, To calculate noise factor of CS-LNA, one important step is to

calculate correlation between channel thermal noise and gate induced noise. The detailed

derivation is given here.





Z,,








Noise factor of CS-LNA is

nt 1; g n 1
F= 1+ (A-1)
i 2 vnl n2vnl

From Equation 3-28 and 3-31, we know that

K 02
i 2 n gs -, 4kTR,~ (A-2)



i (i g,i ) = ii (+j )i s+ (A-3)

R,

Where



[i (1 +jQ,) id T g
100 10










=Iz T (1+Q,)+i +2Re, i~\~ m (1+ jQg ))


2 |c m


(1+ ~ ,) + i,


4kT-2|c g,,, .


= 4kT~g, ,(1 +Q~ )/5 +4kTyg,,,


Substituting Equation A-2 and A-3 into Equation A-1, the result is


4kT .2 |c | g" ~


4kTLg,, (1 +Q e,) / 5 + 4kTyg,,


1

(1 +WL )


(A-4)


F = 1+


g,2 2
4 kTR
4"


When LNA input is matched to source impedance where mLs = R the above equation

can be rewritten as


(A-5)
g,(2Q R,


F = 1+


=I2 OT j










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BIOGRAPHICAL SKETCH

Yu Su was born in 1974. He received his B.S. degree in 1996 from the Dept. of Electrical

Engineering of Xi'an Jiaotong University in Xi'an, China. His specialty was semiconductor

device. In 1999, he received his M.S. degree from Tsinghua University. From August 2000 to

December 2002, he was with the University of South Florida as a research assistant. Since 2003,

he was a Ph.D student in Silicon Microwave Integrated Circuits and Systems (SIMICS) research

group of University of Florida. He has been working on radio frequency CMOS circuit design.

He received the Analog Device outstanding student designer award in 2003. From March 2007

to March 2009, he has been working as a RFIC designer in Texas Instruments, Inc. He received

his Ph.D from the University of Florida in May 2009.





PAGE 1

1 FULLY INTEGRATED CMOS RECEIVER FOR A 24 GHZ SINGLE CHIP RADIO MICRONODE By Yu Su A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DO CTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2009

PAGE 2

2 2009 Y u Su

PAGE 3

3 To my parent s and my wife

PAGE 4

4 ACKNOWLEDGMENTS I would like to begin by thanking my advisor, Professor Kenneth K. O, whose constant encouragemen t and patient guidance provided a clear path for my research. His great vision led to success of our project. I would like to thank Dr. Robert M. Fox for his guidance in my baseband analog circuitries design. I would also like to thank Dr. Khai Ngo and Dr. Glori a J. Wiens for helpful suggestions and their time commitment in serving on my committee. Much appreciation goes to Defense Advanced Research Projects Agency (DARPA) for funding this work. My special thanks go to Albert Yen at UMC Inc. and Geoff Dawe at Bitwave Semiconductor Inc. for chip fabrication. Also I would like to thank Dr. Jenshan Lin for the use of Much appreciation goes to my former TI colleagues, Siraj Akhtar and Chih Ming Hung for their encouragement an d help to finish this dissertation. I have been quite fortunate to have worked with my colleagues in the Node project, Changhua Cao, Yanping Ding, and Jau Jr Lin, whose helpful discussions, recommendations and struggles and excitements during measurements. It is a gr eat 4 year period to work with them. I wish them best in their future career and I believe they will achieve great success. Li Gao, her elder sister style made me get quickly adapted to the new environment when I joined the SIMICS research group. Also, I w ould like to thank the other former and current colleagu es in SIMICS group for their helpful advice and discussions. Some names are listed here: Seong Mo Yim, Dong Jun Yang, Zhenbiao Li, Xiaoling Guo, Ran Li, Haifeng Xu, and Chikuang Yu. Aravind. Sugavanam Jie Chen, Eunyoung Seok, Kwangchun Jung, Swaminathan Sankaran, Chuying Mao, Seon Ho Hwang, Ning Zhang, Shashank, Myoung Hwang, Wuttichai Levdensitboon, Zhe Wang, Dongha Shim and Kyujin Oh. I also like to thank my friends out side

PAGE 5

5 of the research group. A shok K. Verma and Xiuge Yang also worked with us on the project. Ming He and Xiaoxiang Gong share d the same passion with me for G ator basketball and football. Tao Zhang, Qizhang Yin, Xiaoqing Zhou and Xueqing Wang had nice BBQ parties with us. Yanming Xiao and Changzhi Li helped me a lot on using measu re ment equipment I am grateful to my parents for their love and encouragement since childhood. I would like to thank my wife, Cuiwei Wang. Her unconditional support and car e enabled me to focus on research work over the long period of time. Finally, I woul d like to thank my two lovely daughters, ShiYing Su and XinYan Su for happiness and joy they bring to me.

PAGE 6

6 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ ............... 4 LIST OF TABLES ................................ ................................ ................................ ........................... 8 LIST OF FIGURES ................................ ................................ ................................ ......................... 9 ABSTRACT ................................ ................................ ................................ ................................ ... 13 CHAPTER 1 INTRODUCTION ................................ ................................ ................................ .................. 15 1.1 Low Power Wireless Network ................................ ................................ ...................... 15 1.2 On Chip Antenna ................................ ................................ ................................ .......... 16 1.3 ode System ................................ ................................ ................................ ............... 17 1.4 Organization of the Dissertation ................................ ................................ ................... 19 2 NODE SYSTEM OVERVIEW ................................ ................................ ............................ 21 2.1 Introduction ................................ ................................ ................................ ................... 21 2.2 Super Heterodyne and Homodyne Receiver ................................ ................................ 22 2.3 Baseline PHY ................................ ................................ ................................ ................ 26 2.3.1 Direct Sequence Spread Spectrum (DS/SS) ................................ ...................... 28 2.3.2 Differential Chip Detection of Direct Sequence Spread Spectrum (DS/SS DCD) ................................ ................................ ................................ ................. 30 2.3.3 Modulation Format ................................ ................................ ........................... 34 2.4 Summary ................................ ................................ ................................ ....................... 37 3 LOW NOISE AMLIFER DESIGN ................................ ................................ ........................ 39 3.1 Introduction ................................ ................................ ................................ ................... 39 3.2 Noise Sources in MOS Device ................................ ................................ ...................... 39 3.3 Topologies of LNA s ................................ ................................ ................................ ...... 43 3.3.1 Gain of CS LNA ................................ ................................ ............................... 45 3.3.2 Noise Factor of CS LNA ................................ ................................ .................. 47 3.3 .3 Noise Factor of Cascode Amplifier ................................ ................................ ... 50 3.4 24GHz CMOS LNA Implementation ................................ ................................ ........... 53 3.4.1 A 24 GHz Single Ended CMOS LNA ................................ .............................. 53 3.4.2 A 24 GHz Differential CMOS LNA ................................ ................................ 57 3.4.3 Device Characteristic ................................ ................................ ........................ 61 3.4. 4 A 26 GHz CMOS LNA with Negative Impedance ................................ .......... 64 3.5 Summary ................................ ................................ ................................ ....................... 70 4 20GHZ RF FRONT END DESIGN ................................ ................................ ....................... 72

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7 4.1 Introduction ................................ ................................ ................................ ................... 72 4.2 Active Mixer ................................ ................................ ................................ ................. 72 4.2.1 Conversion Gain ................................ ................................ ............................... 74 4.2.2 Noise in Active Mixer ................................ ................................ ....................... 76 4.2.3 Thermal Noise from Switching Pair ................................ ................................ 77 4.3 A 20 GHz Font End wi th On chip Antenna ................................ ................................ 80 4.4 A 20 GHz RF Front End Including LNA, Mixer and IF Amplifier ............................. 89 4.5 Summary ................................ ................................ ................................ ....................... 91 5 BUILDING BLOCKS OF RECEIVER ................................ ................................ .................. 93 5.1 Introduction ................................ ................................ ................................ ................... 93 5.2 Passive Mixer ................................ ................................ ................................ ................ 93 5.3 Variable Gain Amplifier (VGA) ................................ ................................ ................... 95 5.4 Baseband Low Pass Filter (LPF) ................................ ................................ ................... 98 5.5 Frequency Divider ................................ ................................ ................................ ....... 107 5.6 Image Rejection Filter in LNA ................................ ................................ ................... 108 5.7 Integration of Transceiver ................................ ................................ ........................... 110 5.8 Summary ................................ ................................ ................................ ..................... 113 6 FULLY INTEGRATED RECEIVER AND WIRELESS LINK DEMONTRATION OF NODE TRANSCEIVER ................................ ................................ ................................ .... 114 6.1 Introduction ................................ ................................ ................................ ................. 114 6.2 Receiver Measurement Using External LO Source ................................ .................... 114 6.3 Receiver Measurement Using On chip Frequency Synthesizer ................................ 121 6.4 Wireless Communication Link Demonstration ................................ ........................... 125 7 SUMMARY AND FUTURE WORK ................................ ................................ .................. 129 7.1 Summary ................................ ................................ ................................ ..................... 129 7.2 Suggested Future Work ................................ ................................ ............................... 130 APPENDIX DERIVATION OF NOISE FACTOR OF CS LNA ................................ ............... 132 REFERENCES ................................ ................................ ................................ ............................ 134 BIOGRAPHICAL SKETCH ................................ ................................ ................................ ....... 141

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8 LIST OF TABLES Table page 2 1 Link budget of Node. ................................ ................................ ................................ ....... 37 3 1 Summary of performance of single ended and differential LNA. ................................ ..... 61 3 2 P erformance comparison between LNAs above 20GHz. ................................ .................. 70 4 1 Performance of the RF front end ................................ ................................ ....................... 86 4 2 Performance com parison between our down converter and the one in [75]. .................... 91 5 1 Measured and simulated in band loss and corner frequency of the LPF. ........................ 107 6 1 Power table of the receiver. ................................ ................................ ............................. 119 6 2 RX performance summary. ................................ ................................ .............................. 121 6 3 Frequency synthesizer performance summary. ................................ ................................ 122

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9 LIST OF FIGURES Figure page 1 1 A conceptual Node system. ................................ ................................ ............................. 18 1 2 Typical Node de vice size. ................................ ................................ ................................ 18 2 1 Super heterodyne structure. ................................ ................................ ............................... 23 2 2 Direct conversion receiver. ................................ ................................ ................................ 24 2 3 Simplified RF transceiver block diagram. ................................ ................................ ......... 25 2 4 Receiver frequency plan. ................................ ................................ ................................ ... 26 2 5 BER for BPSK with freque ncy offset. ................................ ................................ ............... 27 2 6 BPSK modulation and BPSK spreading scheme. ................................ .............................. 28 2 7 DS/SS BPSK system block diagram. ................................ ................................ ................. 30 2 8 Differential chip detection block diagram. ................................ ................................ ........ 31 2 9 Required E b /N o at BER of 10 4 ................................ ................................ .......................... 33 2 10 Block diagram of 16 ary orthogonal modulation. ................................ .............................. 34 2 11 16 ary orthogonal detector with DCD. ................................ ................................ .............. 35 2 12 AWGN performance in 16 ary orthogonal detector. ................................ ......................... 36 3 1 Cross section of a MOSFET channel consisting of a gradual channel region (I) a velocity saturation region (II). ................................ ................................ ........................... 39 3 2 Induced Gate Noise ................................ ................................ ................................ ............ 42 3 3 Two types of LNA topologies. ................................ ................................ ........................... 44 3 4 CS LNA and its equivalent circuit. ................................ ................................ .................... 46 3 5 Output resistance effect on gain. ................................ ................................ ........................ 47 3 6 Noise sources in CS LNA. ................................ ................................ ................................ 48 3 7 Schematic of cascode amplifier. ................................ ................................ ........................ 50 3 8 Schematic calculating output noise current from common source stage. .......................... 51

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10 3 9 Nois e contribution from a cascode amplifier. ................................ ................................ .... 52 3 10 Single ended LNA. ................................ ................................ ................................ ............ 55 3 11 S parameter of the LNA. ................................ ................................ ................................ .... 56 3 12 Noise figure of the LNA. ................................ ................................ ................................ ... 56 3 13 IIP3 measurement of the LNA. ................................ ................................ .......................... 57 3 14 Differential LN A ................................ ................................ ................................ ................ 58 3 15 S parameters of differential LNA. ................................ ................................ ..................... 59 3 16 NF of the differential LNA. ................................ ................................ ............................... 59 3 17 IIP 3 of the differential LNA. ................................ ................................ .............................. 60 3 18 Substrate network of a MOSFET. ................................ ................................ ...................... 61 3 19 Extracted R db and C db ................................ ................................ ................................ ........ 62 3 20 R sub effect on output resistance of a cascode amplifier. ................................ ..................... 63 3 21 Schemes for generating negative resistance. ................................ ................................ ..... 64 3 22 The LNA with an inductor at the gate of M2. ................................ ................................ .... 66 3 23 S parameters and NF measurement of the LNA. ................................ ............................... 67 3 24 Stability circles ................................ ................................ ................................ .................. 68 3 25 IIP3 of the LNA. ................................ ................................ ................................ ................ 69 4 1 Switching mode of mixer. ................................ ................................ ................................ .. 73 4 2 Active mixer. ................................ ................................ ................................ ...................... 73 4 3 Mixer gain drop from ideal switching. ................................ ................................ .............. 76 4 4 Frequency translation of white noise in a transconductor. ................................ ................ 77 4 5 Time varying transconductance G(t). ................................ ................................ ................ 78 4 6 NF vs. LO power of Mixer. ................................ ................................ ............................... 80 4 7 Schematic of LNA and Mixer. ................................ ................................ ........................... 81 4 8 Die micrograph and antenna cross section. ................................ ................................ ........ 82

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11 4 9 Reflection coefficient at IF and RF ports. ................................ ................................ .......... 83 4 10 The Gain and NF vs. Frequency plots for 20 GHz downconverter. ................................ .. 84 4 11 Linearity of down converter ................................ ................................ ............................. 85 4 12 Interchip wireless communication over free space. ................................ ........................... 87 4 13 Received spectrum ................................ ................................ ................................ ............ 88 4 14 IF amplifier schematic. ................................ ................................ ................................ ...... 89 4 15 A Front end with an IF amplifier ................................ ................................ ....................... 90 4 16 Measured matching properties at IF and RF ports. ................................ ............................ 90 4 17 Power gains at input and image frequencies. ................................ ................................ ..... 91 5 1 D iagram of node receiver. ................................ ................................ ............................... 93 5 2 Passive mixer. ................................ ................................ ................................ .................... 94 5 3 Gain vs. LO power in a passive mixer. ................................ ................................ .............. 94 5 4 Schematic of the VGA and its basic amplification stage. ................................ .................. 95 5 5 Gain control scheme. ................................ ................................ ................................ ......... 96 5 6 M easurement setup of the VGA using differential amplifiers as Baluns. ......................... 97 5 7 VGA gain vs. gain control step. ................................ ................................ ......................... 98 5 8 Capacitive vo ltage divider in the configuration for gain step 4. ................................ ........ 98 5 9 Half sine and 2 nd order Butterworth filter frequency response. ................................ ........ 99 5 10 A)A lossy biquad and B)its equivalent circuit. ................................ ................................ 100 5 11 Schematic of the LPF. ................................ ................................ ................................ ...... 101 5 12 LPF V out and I dd vs. V gmc ................................ ................................ ................................ 102 5 13 Near square law of I dd vs. V gmc ................................ ................................ ...................... 103 5 14 Frequency response and tuning of LPF. ................................ ................................ .......... 104 5 15 LPF cut off frequency vs.Sqrt(I dd ). ................................ ................................ .................. 104 5 16 LPF including device output resistance. ................................ ................................ .......... 105

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12 5 17 Simulated L PF IP 3 ................................ ................................ ................................ ........... 106 5 18 Block diagram of the 2:1 static frequency divider. ................................ .......................... 107 5 19 Schematic of the 2:1 static frequency divider. ................................ ................................ 108 5 20 2 stage LNA with notch filters at the image frequency. ................................ .................. 109 5 21 Input impedance of the notch filter vs. frequency. ................................ .......................... 109 5 22 Distributed switching for the receiver and transmitter. ................................ ................... 110 5 23 A) Integration of the frequency synthesizer, transmitter and r eceiver. ............................ 112 5 24 Inverter chain is used to drive the passive mixer. ................................ ............................ 113 6 1 Die micrograph of the transceiver and baseband proc essor. ................................ ............ 115 6 2 Receiver board and die wire bonding. ................................ ................................ ............. 115 6 3 Receiver baseband signal output spectrum. ................................ ................................ ..... 117 6 4 Gain vs. frequency of the receiver with an on chip antenna connected to the RF input pads. ................................ ................................ ................................ ................................ 117 6 5 Receiver noise floor illustrating the filter ch aracteristic. ................................ ................. 118 6 6 Frequency response of RX gain and NF. ................................ ................................ ......... 120 6 7 IP3 measurement of whole RX chain. ................................ ................................ ............. 120 6 8 PLL based frequency synthesizer. ................................ ................................ ................... 121 6 9 The output spectrum the RX when the LO is driving from synthesizer. ......................... 123 6 10 The output spectrum of RX when the LO is generated using an on chip synthesizer. .... 123 6 11 Phase noise of the baseband signal. ................................ ................................ ................. 124 6 12 Baseband power versus different VGA gain setting. ................................ ....................... 124 6 13 Wireless communication link between the transmitter and receiver. .............................. 126 6 14 Transmitter on board and die wirebonding. ................................ ................................ ..... 126 6 15 Wireless link measurement setup and environment. ................................ ........................ 127 6 16 Receiver output spectrum. ................................ ................................ ............................... 127 A 1 Noise sources in CS LNA. ................................ ................................ ............................... 132

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13 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy FULLY INTEGRATED CMOS RECEIVER FOR A 24 GHZ SINGLE CHIP RADIO MICRONODE Yu Su May, 2009 Chair: Kenneth K. O Major: Electrical and Com puter Engineering The speed improvement of silicon devices has made implementation of silicon integrated circuits operating at 10GHz and higher feasible. This trend has made it possible to integrate a single chip radio using on chip antennas. This had led to the proposal of a 24 GHz true single chip CMOS radio. This Ph.D work demonstrated a fully integrated receiver chain, and a transceiver incorporating the receiver, transmitter designed by C. Cao and the frequency synthesizer designed by Y. Ding. S ingl e ended and differential LNA s operating at 24GHz have been demonstrated. With 1.2 V supply, the single ended LNA has 6 dB gain and 5 dB noise figure consuming 2.3 mW power. The differential LNA has 6 dB gain and ~5.3 dB while consuming 4 mW power. From the se, it is found that substrate resistance and parasitic capacitance of CMOS devices significantly degrade the gain and power efficiency of LNA. By adding an inductor at the gate of common gate stage of a cascode amplifier negative resistance can be genera ted to increase the output impedance and transconductance of LNA. A 26 GHz LNA using this topology achieves 8.4 dB gain and ~5 dB noise figure while only consuming 0.8 mW power. A 20 GHz RF front ended including an LNA and a mixer is demonstrated. It achi eves 9 dB conversion gain and 6.6 dB noise figure. This RF front end only consumes 12.8 mW power from a 1.5 V supply. Using this RF front end with an on chip antenna as a receiver, AM signal

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14 transmitted by an on chip antenna 5m away has been successfully p icked up and down converted to intermediate frequency (IF). For the first time, this demonstrated the feasibility of a pair of IC s communicating with each other over free space using on chip antennas. To increase receiver gain, an IF amplifier is added to the RF front end. It achieves 29.5 dB gain consuming 17.7 mW power from a 1.5 V supply. These results showed that it is feasible to implement low power 24 GHz communication devices with reasonable performance using a 130 nm CMOS technology. A fully integr ated receiver is demonstrated. It consists of an RF front end, IF amplifier, passive mixer, variable gain amplifier (VGA) and lower pass filter (LPF). It utilizes dual down conversion which requires one 21.3 GHz frequency synthesizer and a divid e by 8 circ uit to generate the second local oscillator signal A distributed transmitter/receiver switch is used to share the use of one on chip antenna by the receiver and transmitter. A wireless communication link is demonstrated using fully integrated receiver and transmitter. A ~21.7 GHz single tone generated by the transmitter is successfully picked up and down converted to baseband by the receiver which is 5m away from the transmitter. This demonstration is a great step toward the realization of a single chip ra dio

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15 CHAPTER 1 INTRODUCTION 1.1 Low Power Wireless Network The rapid evolution of wireless communications technology has resulted in a strong drive toward implementation of high performance radio frequency (RF) circuits in silicon, particularly Compleme ntary Metal Oxide Semiconductor (CMOS), for its lower cost and higher level of integration. With low cost and low power advantage of CMOS, RF products incorporating the standards for cellular phone and ultra wide band standard, as well as Bluetooth and 802 .11x for wireless local area network (WLAN) applications are being developed and deployed. It is now widely acknowledged that these standards are not well suited for a wide range of sensor network applications due to the high cost of nodes as well as the h igh power consumption resulting from complex protocols. To address this, a standard called ZigBee [1] is proposed. Its main goal is to standardize and enable inter operability of products within a home or a buil ding. The ZigBee standard builds on the physical communication layers specified by the IEEE 802.15.4 standard [2] The ZigBee defines the network, security and application software. Zigbee networks operate in th e 2.4 GHz Industrial Scientific Medical (ISM) band, the same band as 802.11b WLAN n etworks, Bluetooth and others. ZigBee networks better address the unique needs of sensors and control devices. Sensors and controls do not need high bandwidth. However, the y do need low latency and very low energy consumption for long battery life. The devices are idle for most time. The network supports data transmission rates up to 250kbps at a range of up to 30 meters. This data rate is lower than the 802.11b WLAN (11 Mbp s) and Bluetooth (1 Mbps) devices, but the power consumption of Zigbee devices is significantly lower. Users can expect batteries to last many months or even years.

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16 1.2 On Chip Antenna For the low power wireless network applications, it is possible to impl ement a single chip radio which packages both baseband electronics and radio in a single chip [3] To totally eliminate the potentially costly external transmission line connections, integration of antennas is d esirable if their performance is adequate. The research on fabrication of antennas on semi conducting substrate goes back to the chip antenna integrated with a 95 GHz IMPATT diode oscillator on a high resisti ve silicon substrate [4] and an on chip antenna integrated with a 43.4 GHz IMPATT diode oscillator on a GaAs substrate [5] High resistive silicon substrates have als o been used to fabricate MEMS based antennas operating at 90 to 802GHz [6] However, the use of IMPATT diode circuits limits the types of radios that can be built. Furthermore, the substrates are not compatible with the low cost mainstream silicon process technologies. The speed improvement of silicon devices has made implementation of silicon integrated circuits operating at 10GHz and higher feasible. At 10GHz, a quarter wave dipole antenna needs to be only 7.5 and ~2.2 mm in free space and silicon, respectively, making integration of an antenna for wireless communication possible. On chip antennas could potentially be used to relieve the bottleneck associated with global signal distribution inside integrated cir cuits. The first proposed uses of an on chip antenna fabricated in a conventional foundry process are clock distribution [7] and data communication [8] [9] Several transmitters [10] [11] and receivers [11] with on chip antennas for wireles s clock distribution have been demonstrated. Signal from a transmitter incorporating a 10 GHz VCO, buffer and antenna fabricated in a BiCMOS technology [15] has also been picked up by an external horn antenna. Recently, a clock transmitter [16] and receiver [17] using 2 mm on chip zigzag antennas for clock distribution have achieved 5 ps peak peak jitter. These suggested th e

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17 potential to communicate over free space using true single chip CMOS and BiCMOS radios with on chip antennas. Having the ability to form antennas on chip with almost no cost penalty provides greater design flexibility. It is no longer necessary to force the transmitting and receiving antennas. Each interface could be independently optimized. The noise performance The impedance o high Q requirement of matching network which can reduce the output signal swing at given output power. Especially in a class E power amplifier, the lower voltage swing reduces the voltage str ess on devices. Using passive on chip components in combination with the freedom to choose impedance level should allow integration of tunable bandpass filters with the relax performance requirements. 1.3 Exploiting this new possibility, a se nsor node called Node, which incorporates on chip antennas, a transceiver, a digital baseband processor, a sensor, and potentially even a battery, has been proposed [18] Figure 1 1 shows the conceptual diagram of a Node. It is capable of 100kbps wireless transmission and reception at ~24GHz over a short distance (typically 1 to 5 meters, and the range can be extended to ~30m at the cost of increased transmit power). Groups of Nodes can form self organizing wireless communication networks that signal in a wide frequency band (100MHz) at amplitude below the background noise level. Such nodes could help to accelerate the realization of Smart Dust vision [19]

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18 The Node packaging has the potential of being very simple. The SoC CMOS chip communicates off chip via wireless signaling. The only wire connections are battery connections. A Node package only needs to provide mechanic al and chemical protection, while allowing RF signal transmission. In contrast, a device with an off chip antenna must have a package providing well controlled impedance connection to external passive components including an antenna. Since Node s are opera ting at ~24GHz, all the passive components can be easily integrated on chip. A Node network can be viewed as a modified Zigbee network operating at 24GHz. Figure 1 1. A conceptual Node system. F igure 1 2 Typical Node device size. Size 5A and 10 B atteries

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19 When packaged with a battery, a Node can be as small as ~3 mm x 3 mm x 5 mm can have a mass less than 20 milligrams, and has a battery life of 1 to 30 days. The size of Node device is usually limited by the battery dimensions. Presently, an m&m sized communication node shown in F igure 1 2 is being developed. 1.4 Organization of the Dissertation This Ph.D work focuses on the design and characterization of receiver chain for th e 24 GHz radio, The goals of this work are to develop the receiver in main stream CMOS technology including an on chip antenna and integrate it with a transmitter designed by C. Cao and a synthesizer developed by Y. Ding as well as to demonstrate communica tion using the transceiver. First, a brief overview of the whole system design is given in Chapter 2. Direct Sequence Spread Spectrum (DS/SS) differential chip detection (DCD) is utilized to mitigate the deleterious effects of frequency offset and phase no ise. A low noise amplifier (LNA), the first gain stage in the receiver chain, plays an important role in determining the noise performance of whole system. Its design methodology is discussed in Chapter 3. The low output resistance of short channel transis tors limits the amplifier gain. The excess channel thermal noise and induced gate noise hurt the noise performance. Approaches to achieve the reasonable gain and noise performance while consuming low power are investigated. Three design examples are given in Chapter 3. The conversion gain and noise performance of active mixers are discussed in Chapter 4. Demonstration of a 20 GHz RF front end with on chip antenna is also presented in this chapter. The RF front end is used to receive amplitude modulated (AM) signal transmitted from an on chip antenna 5 m away and to down convert this signal to intermediate frequency (IF). For the first time, we demonstrate that it is feasible for two IC s to communicate over free space via on chip antennas.

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20 Chapter 5 discusse s the building blocks in the receiver chain including variable gain amplifier (VGA), low pass filter (LPF), 8:1 frequency divider, image rejection filter in LNA and passive mixer. A distributed switch topology is used to share the use of one on chip antenn a by the transmitter and receiver. Chapter 6 presents a fully integrated receiver implemented in a 130 nm CMOS technology. It is characterized with an external LO source as well as with an on chip frequency synthesizer. In addition, a wireless communicatio n link over 5m has been established using the fully integrated transmitter and receiver. Finally, this research work is summarized and possible future works are suggested in chapter 7

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21 CHAPTER 2 NODE SYSTEM OVERVIE W 2.1 Introduction An RF receiver has tw o important performance criteria: sensitivity and selectivity. Sensitivity is defined as the lowest power level at which the receive r can recover the information with a required bit error rate (BER). ab ility to reject signals in adjacent channels or outside of band while receiving wan ted signal. The receiver sensitivity is critically determined by the noise performance of a system which is specified using noise figure ( NF ). It is related to the noise fac tor which measures the degradation of signal to noise ratio as the signal is processed through a system. (2 1) where noise figure ( NF ) is an equivalent representation in decibels. In a system consisting of n stages, if the individual n oise factor and gain of system components are known, the overall noise factor can be calculated by Friis equation [31] (2 2 ) E quation 2 2 shows the overall system noise factor is determine d by the first few stages if they have sufficient gain to suppress the noise contribution from the following stages. The sensitivity level of a receiver is defined by Sensitivity level (2 3) where the first three terms represent the noi se floor at system input, is the noise figure of receiver, is the required energy per data bit over variance of noise at minimum BER requirement. The receiver sensitivity level is directly related to the noise figure of receiver. To

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22 minimize the overall noise figure, the noise figure of individual building blocks in the receiver must be reduced and the distribution of gain along the receiver chain has to be properly chosen. If noise figure of individual blocks is fix ed, it is desirable to have high gain in the first few stages to suppress the noise contribution from the following stages. However, such kind of gain distribution degrades receiver selectivity. Receiver selectivity characterizes the ability of a receiver to pick out the wanted signal in the presence of a strong adjacent channel or alternate band signals. The selectivity is affected by many factors such as linearity of individual blocks and gain distribution along the receiver chain. As discussed before, h igher gain used in the early stages of receiver reduce s the noise figure. However, this will place a tighter linearity requirement on the subsequent receiver blocks. Power consumption is a nother performance metric. N oise figure and linearity of a receiver can be improved by increasing the power consumption of receiver. For portable applications, the trade off is between providing satisfactory receiver performance and power consumption. We will briefly go over two types of receiver architectures: super hete rodyne and homodyne. Then, we will talk about the dual down conversion structure used in this work. The choice of architectures places different emphases on the trades offs among performance, power consumption and complexity. Unlike conventional radios wh ich generally use an off c hip crystal frequency reference the single chip radio will use an on chip voltage control oscillator (VCO) which increases the frequency offset between TX and RX, and phase noise. As mentioned, DS/SS DCD is used to mitigate these deleterious effects. 2.2 Super Heterodyne and Homodyne Receiver A super heterodyne receiver can have excellent selectivity. In a super heterodyne receiver, as illustrated in F igure 2 1 the incoming RF signal is p icked up by an antenna and filtered by a band select filter following the antenna to attenuate the out of band signals. The LNA amplifies

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23 the signal while introducing a minimal amount of noise. Then, the signal is first down converted to intermediate frequ ency (IF) using a mixer and local oscillator (LO) signal generated by a phase lock loop (PLL). There is an image reject filter between the LNA and mixer. This filter is to significantly attenuate the signals in the image band. The LO signal can be tuned t o down convert any wanted in band channel to a fixed IF. The tuning of the LO signal is achieved by setting the divider ratio of PLL. The IF stages can then use a fixed band pass filter which can attenuate unwanted signals. Selectivity is therefore determi ned by the IF filter The signal at IF is down converted once more to baseband using LO2 with fixed frequency. The baseband circuitry performs additional channel filtering and adds variable gain to reduce the dynamic range requirement of analog to digital converter (ADC). The excellent selectivity of a super heterodyne receiver is due to the high quality factor Q networks formed using off chip passive components, which are not available for the receivers integrated in a chip. F igure 2 1 Super heterodyne structure. A direct conversion receiver can eliminate the need for high Q off chip passive components. The receiver directly down converts in band signal to baseband using only one LO signal withou t utilizing an IF stage, as shown in Figure 2 2 Unwanted signal can be easily removed at baseband. Direct conversion architecture is better suited for integrated receiver. However, there are several problems for this architecture. One problem is DC offset LO signal LNA AMP VGA VGA LO1 LO2_Q LO2_I ADC ADC BPF Image Reject Filter IF Filter

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24 can leak either to the mixer input or to the antenna. The radiated LO signal leaking to the antenna can be reflected and picked up by the receiver. In these situations, LO signal s are self mixed and results in DC offset [24] The unwanted DC offset is interference to the wanted signal. One approach to eliminate the DC offset is utilizing an AC coupling capacitor between mixer output and baseband circuitry. This method effectively high pass filter this signal. Applicability of this technique highly depends on the system settling time, modulation scheme and bandwidth. For wide bandwidth system the pole of high pass filter can be set relatively high without significantly degrading SNR. Later on, we will discuss how to deal with the AC coupling issue in the true single chip radio. Other design issue in direct conversion is I/Q phase accuracy and frequencies. For exam ple, a quarter wavelength in silicon at 24GHz is ~900 m m line length difference between I/Q signal traces will translate to 1 degree phase difference. So it will be challenging to implement a direct conversion receiver with such high RF frequencies. Figure 2 2 Direct co nversion receiver. Node only has one channel for low data rate communication. Unlike most of radios which require variable LO frequencies for different channel selection, a Node makes use of LO1 and LO2 in super heterodyne structure with both fixed and they are generated using a single frequency source. Shown in Figure 2 3 is a block diagram of the transceiver. It consists of a transmitter, receiver and frequency synthesizer. The trans ceiver utilizes dual conversion LNA VGA VGA LO1 _Q LO1 _I ADC ADC BPF

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25 ar chitecture [20] Two LO signals are at 21.3GHz and 2.7GHz, respectively. They are generated by using only one 21.3 GHz frequency synthesizer and a frequency divide by 8 circuit. Figure 2 3 Simplified RF transceiver block diagram. On the receiver side an incoming 24 GHz signal is picked up by an on chip antenna, amplified by a low noise amplifie r (LNA), down converted to IF at 2.7GHz and then down converted to baseband to generate quadrature I and Q signals. These tw o signals are amplified by variable gain amplifiers (VGA), filtered by lower pass filters (LPF) and then digitized by two 100 MHz, 5 bit analog to digital converters (ADC s ). The receiver frequency plan is depicted in Figure 2 4 The image channel is locate d at 18.6GHz, which is 5.4GHz away from the desired RF channel. This unwanted image signal can be attenuated by the tuned response of LNA and mixer. On the transmitter side, its frequency plan is the same as the receiver. The baseband I and Q are first mo dulated to 2.7GHz by a modulator [21] implementing an MSK like constant envelope phase shift modulation. The modulated signal is then converted to 24GHz by an up conversion mixer. The up converted 24 GHz signal is delivered to the on chip antenna through TIMING RECOVERTY & DEMODULATOR Two 5b ADC LNA AMP VGA VGA LPF LPF MICROPROCESSOR BIT TO CHIP ENCODER BUFFER MOD ULATOR 8:1 divider & Muti Phase BUFFER PLL BUFFER AMP AMP PA RX 8:1 LO1 LO2_Q LO2_I TX

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26 an on chip power amplifier (PA) [22] Since the 24 GHz transmitter output signal is 2.7GHz away from the 21.3 GHz operating frequency of the synthesizer, LO pulling by the PA is eliminated [23] Figure 2 4 Receiver frequency plan. 2.3 Baseline PHY Unlike most modern communication systems which depend on a stable crystal based frequency reference the RF subsystem of Nodes will use an on chip frequency reference with poor phase noise and large frequency offset. The operating frequency of Node is 24GHz with relatively low bit rate (100kbps). A subtle LO frequency offset between that of the transm itter and that of the receiver can cause severe performance degradation. To mitigate this, modulation and receiver processing methods were developed. To discus this, let us consider a BPSK system in which the received signal is given by (2 4) where n(t) is Additive White Gaussian Noise (AWGN) process with noise spectral density of N 0 /2. Assuming a receiver uses to demodulate the incoming signal, the average bit error probability is given by ( 2 5)

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27 where (2 6) where T is the symbol duration time which is 10S for 100kbps data rate. The frequency offset is defined in terms of ppm, (2 7) Figure 2 5. BER for BPSK with frequency offset. Figure 2 5 shows the average bit error probability (BER) for BPSK coherent demodulation with 0 ppm, 0.5 ppm and 1 ppm frequency offset. To maintain BER of 10 4 with 1 ppm frequency offset, E b /N o must be increased by more th an 3dB from 0 ppm case Unfortunately, even 1 ppm tolerance which translates to 24 kHz for a 24 GHz carrier is extremely difficult to achieve. One way to mitigate the frequency offset and poor phase noise of on chip reference 1 ppm 0.5 ppm No frequency offset

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28 frequency source is to use dir ect sequence spread spectrum (DS/SS) differential chip detection (DCD) [25] 2.3.1 Direct Sequence Spread Spectrum (DS/SS) Spread spectrum is a technique to spread the transmitted signal power over a broad spect rum. Spreading spectrum reduces power transmitted at any one frequency so that it would reduce interference to others and make the detection of the presence of signals difficult. It is also less susceptible to interference at any one frequency and makes ja mming difficult. Figure 2 6 BPSK modulation and BPSK spreading scheme. One way to spread signals is to modulate the transmitted data signal by a high rate pseudo random sequence of phase modulated pulses before mixing the si gnal up to the carrier frequency for transmission. This spreading method is called direct sequence spread spectrum [26] Suppose the data signal is (2 8) b(t) a(t) s(t)

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29 where is the s ymbol sequence and T is the symbol duration. We modulate the data signal b(t) by spreading signal a(t) or a PN code, which is (2 9) where is called signature sequence and is called the chip wave form. We impose the condition that where N referred at the processing gain or the spreading gain, is the number of chips in a symbol and is the chip duration. Then the spread spectrum signal is given by (2 10) There are many spreading schemes. For example, a spreading scheme with BPSK modulation which means and BPSK spreading which means is illustrated in Figure where spreading gain is only 4. The power spectrum of the spread signal is given by (2 11) Compare this to the power spectrum of the original data signal (2 12) W e see that the spectrum is spre ad N times wider by the multiplication of the PN sequence. This is illustrated in Figure 2 7 This figure shows a wireless link including a transmitter, a channel and a matched filter receiver. One great feature of DS/SS is the low probability of detection It means that it is hard for an unintended receiver to detect the presence of the signal. When the processing gain is significantly large, the spread spectrum signal can be below the white noise floor, as shown in Figure 2 7 A receiver without the proper PN code can not despread the received signal. The RF subsystems size of only ~3 mm 3 mm and the signal in a

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30 wide frequency band below background noise level make the radio physically and electrically invisible. Figure 2 7 DS/SS BPSK system block diagram. 2.3.2 Differential Chip Detection of Direct Sequence Spread Spectrum (DS/SS DCD) The RF subsystem for Node will utilize an on chip frequency reference to generate the LO signals which could have higher phase noise and larger frequency offset. To mitigate these, DS/SS DCD can be utilized [25 ] The application of differential detection at chip level rather than data symbol level significa ntly improves receiver robustness to large carrier phase drift since the phase variation could be considered negligible within a pair of chip interval. Figure 2 8 shows the basic processing step used in differential chip detection [27] The transmitted signal k white noise signal Then the sampled baseband signal is (2 13) where is the chip rate. The output of differential chip detector is (2 14) Transmitter Channel PN code a(t) Receiver PN Code a(t) noise n(t) Original data signal Filter Demodulator Modulated Data Data signal after spreading N 0 N 0 Receiver Input c 0 c c c PT c PT Binary data s(t) r (t)

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31 Figure 2 8 Differential chip detection block diagram. k for this moment to examine effect o f the frequency offset. Then Equation 2 14 becomes (2 15) is approximately equal to 1, then is close to the des ired differentially detected signal As the frequency offset increases relative to the chip rate, the cosine factor becomes less than unity and reduces the signal level, which in turn degrades the receiver sensitivity. Frequency offset tolerance can be made arbitrarily high by simply increasing the chip rate. However, for a fixed data rate, increasing the chip rate requires increasing the processing gain (chips per symbol), which leads to higher implementation cost and degraded sensitivi ty for DS/SS DCD. When the phase drift and noise are considered, assuming that the noise samples, and and the chip samples, and are uncorrelated, the input and output chip S NR s are (2 16) (2 17) T c =c k e j ( k ) +n k

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32 where is the mean energy loss factor due to the frequency offset and phase noise. It will be discussed in detailed later and assumed to be constant for this moment. For l arge input SNR, the DCD SNR is approximately equal to half of the input SNR which means 3 dB degradation. However, for the low input SNR levels typical in DS/SS receivers (below 0dB), the DCD SNR approaches the square of the input SNR. can be converted to an effective (2 18) where is the processing gain. For large is (2 19) Equation 2 19 shows that each doubling of the processing gain requires a 1.5dB increase in to maintain the same or bit error probability. T he mean energy loss factor in Equation 2 17 given in [25] is (2 20) is the variance of which is defined by, (2 21) It can be written in Z domain, (2 22) where is the phase transfer function produced by differential chip detection, (2 23) The frequency response of is obtained by setting : (2 24)

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33 Given the power spectral density fo r the LO phase noise, (2 25) Since has a highpass filter nature, it helps to suppress close in LO phase noise. Assuming that chip matched filter (CMF) effectively limits the bandwidth of the phase noise to a simple analytical model is (equation (19) in [25] ), (2 26) (2 27) Figure 2 9 Required E b /N o at BER of 10 4 Using Equation 2 19 and 2 26 required at BER=10 4 with different processing gain is shown in Figure 2 9 for three different situations: only AWGN channel without frequency offset and phase noise ( and ), AWGN channel with phase noise ( and ) and AWGN channel with phase noise ( ) and frequency offset of

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34 0.1 ( B ased on Equation 2 18 and 2 26 the presence of phase noise ( ) will cause ~1.2 dB energy loss and frequency offset of 0.1 will cause additional ~2 dB energy loss. To achieve the same BER of 10 4 the E b /N 0 in the presence of phase n oise ( ) needs to be increased from 0.7 to 1.2dB compared to the case with only AWGN. Additional frequency offsets of 0.1 requires extra from 1 to 1.6dB increase in E b /N 0 2.3.3 Modulation Format Figure 2 10 Block diagram of 16 ary orthogonal modulation As shown in Figure 2 10 the radio uses a DS/SS in which each data symbol is represented by one of 16 different PN sequences. One PN sequence repr esents 4 bits. These PN sequences are selected to be approxi mately orthogonal. The format can be viewed as 16 ary orthogonal modulation. The selected PN sequence which contains 2048 chips is passed to the chip level differential encoder. Then the encoded c hip sequence is modulated onto the carrier using Offset QPSK (OQPSK) with half sine pulse shaping which is Minimum Shift Keying (MSK). The corresponding power spectral density (PSD) is (2 28) s 0 s 1 s M 1 PN Sequence Selection Half Sine Pu lse Shape p(t) Bits Serial to Parallel 4 bit Symbol Value m(t) Differential Encoding OQPSK Mod. z 1

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35 where is the average bi t interval. The spectrum for MSK decays roughly as Figure 2 11 shows a block diagram of the 16 ary orthogonal demodulator [28] The demodulator consists of a differential chip detector follo wed by an optimal coherent detector for orthogonal signaling. The differential chip detector removes phase offsets between transmitter and receiver, and it mitigates the impact of frequency offsets as well as phase noise. Figu re 2 11 16 ary orthogonal detector with DCD. Similar to Equation 2 18 at the input of the PN sequence matched filter in Figu re 2 Figure 2 11 is (2 29) where is the processing gain for one symbol, defined here as the number of chips per symbol and is the number of bits per symbol. For M ary orthogonal signaling where each symbol represents B bits, the average symbol error probability ( ) [29] is (2 30) r(t) Bits C hip Matched Filter r i,k s 0 s 1 Parallel to Serial t=kT c 4 bit Symbol Estimate PN Sequence Matched Filters Choose Largest Differential Chip Detection

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36 (2 31) The corresponding bit error probability ( ) is (2 32) Using Equation 2 30, 2 31 an d 2 32 the required at BER of 10 4 with different processing gain to tolerate different frequency offset in the 16 ary orthogonal detector is shown in Figure 2 12. Figure 2 12 AWGN performance in 16 ary or thogonal detector. However, in real implementation, noise and chip samples are not completely uncorrelated. The set of 16 PN sequences are not perfectly orthogonal. All these factors will cause performance degradation. One of the goals for the integrated f requency reference is to 100ppm stability, which could produce a worst case frequency offset 200ppm between a transmitter and a receiver. At the 24 GHz operating frequency this translates to a 4.8 MHz offset. Using 10% of the chip rate as our rule of thu mb for acceptable offset, then the chip rate must be on the order of

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37 48 Mchip/s. The processing gain Gp required to achieve this chip rate will depend on the desired data rate. For the 100 kpbs assumed here, the 16 ary symbol rate would be 25 k symbol/seco nd, and a processing gain of G p =2048 would give a chip rate of 51.2 Mchip/s. This is slightly larger than the desired 48 Mchip/s, but it allows G p to be a power of 2 which simplifies implementation. It is shown in Figure 2 12 to tolerate 130 ppm frequency offset, processing gain of 2048 and E b /N o of 17.5dB are needed. In addition, with G p =2048, the phase noise requirement is greatly relaxed. According to [28] a phase n oise level of 65dBc/Hz at 1 MHz frequency offset only causes 0.5dB E b /N o degradation. Based on the E b /N o of 18dB which tolerates the frequency offset and phase noise, the link budget of receiver is given in Table 2 1 Table 2 1 Link budget of N ode. Spec Targeted Number TX Output Power 10 dBm Communication Range 5 m Antenna Pair Gain 84 dB Antenna Direction Loss 4 dB Received Power 78 dBm Thermal Noise 174 dBm/Hz Bandwidth ( 100 kb/s) 50 dB E b /N o 18 dB RX Noise Figure 10 dB Sensitivity 96 dBm Link Margin 18 dB 2.4 Summary This chapter reviewed the communication syst end architecture and baseline physical layer. A dual down conversion architecture is selected. This architecture uses only one frequency synthesizer and divide by 8 circuit to generate two LO signals. Unlike most radios whi ch use crystal frequency reference, reducing the chip area. Unlike

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38 most radios which use a crystal frequency reference, the RF subsystem uses an on chip VCO as the frequency reference. Poor phase noise and frequency offset of the VCO could significantly de grade the system performance. DS/SS DCD is utilized to mitigate these effects. This chapter described the relationship between the frequency offset tolerance and processing gain. The tradeoff between the receiver sensitivity and processing gain is also dis cussed. To tolerate 130 ppm frequency offset and 65dBc/Hz phase noise at 1MHz offset, E b /N o of 18dB is required. From this specification, sensitivity target for this radio is 96dBm.

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39 CHAPTER 3 LOW NOISE AMLIFER DE SIGN 3.1 Introduction Modern receiving systems must often process very weak signals. The noise added by a receiver corrupts these weak signals. One approach to reduce the effect of the receiver noise is to make the received signal stronger. This can be accomplished by raising the signal power transmitted in the direction of receiver. This is eventually limited by government regulations, engineeri ng considerations, or economics. Another way is to increase the amount of power the receiving antenna can collect, for example, by increasing the aper ture of receiving antenna. The other approach is to minimize the noise of receiving system. Lowering receiver noise has the same effect on the output signal to noise ratio as improving any one of the other quantities. Increasing the transmitting power or i ncreasing aperture of antenna can be costly compared to the small cost of improving the LNA noise perform ance. 3.2 Noise Sources in MOS Device Figure 3 1 Cross section of a MOSFET channel consisting of a gradual channel regio n (I) a velocity saturation region (II). The noise in RF building blocks is contributed by the active components (transistors) and passive components such as resistors and inductors. Resistors contribute thermal noise. In MOSFET s there are two major sourc es of noise at low frequencies (~1MHz and below): 1/f L eff I II L elec S S D

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40 noise and thermal noise. 1/f noise is caused by carrier number fluctuation [31] [33] and mobility fluctuation [34] in the channel. It is a low frequency phenomenon. In tuned RF amplifiers designs, due to the high operating frequency, the channel thermal noise is the main concern. Thermal noise is generated by random moti on of channel carriers. In short channel devices, due to velocity saturation, the channel can be divided into two sections [38] : a gradual channel region and a velocity saturation region, shown in Figure 3 1. In gradual region described in [35] the drain current is (3 1) where is the mobility, is the channel width and is the inversion lay er charge per unit width at position along the channel. Rewriting Equation 3 1 as (3 2) giving the resistance of a small segm x in the channel (3 3) The spectral density of this small resistor is (3 4) current. Integrating Equation 3 1 along the channel gives (3 5) at position in the channel, Equation 3 5 is rewritten as

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41 (3 6) Local conductance is defined from E quation 3 6 (3 7) which specif ies how small voltage change in the channel causes the chan ge of drain current. Combining Equation 3 4 and 3 7 x in the channel to noise spectral density of drain current in gradual channel region, (3 8) The total channel thermal no ise density is the integral of Equation 3 10 along the channel, giving (3 9) Q inv is inversion layer charge per transistor width. This equation is valid for any model, provided the appropriate expression is used for Q inv Particularly, for models using the gradual channel approximation (GCA) [36] Q inv is (3 10) Then, it can be rewritten as classic channel thermal noise spectral density [37] (3 11) g m is the transcondutance of the transistor. Noise generated in the velocity saturation region (II) is treated differently in various previously reported papers [39] [40] Channel resistance in region II is derived in [38] while in [39] the thermal noise of this region is calculated based on inverse charge and excessive electron temperature. However, it is argued in [40] that noise from this region is zero because the carriers do not respond to the finite voltage fluctuation when they travel at saturation velocity. Ev en

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42 though noise generation mechanism in this region is not clear now, it has been reported that in [30] [41] that short channel NMOS devices in saturation exhibit no ise far in excess of values predicted by long channel theory. 3. It generally increases with drain current as well as V ds As drain to source voltage is increased, the electric field within the channel increases, generating hot carriers. Transistors operating in weak inversion have a spectral densit y (3 12) assuming It is interesting to observe that the expression for weak inversion is just like that of shot noise [36] In weak inversion the current in the channel is controlled by the height of source channel barrier which is lowered by increasing the gate voltage. Figure 3 2 Induced Gate Noise The MOS can also be viewed as an RC distributed network with R representing channel resi stance and C representing the gate capacitance, as shown in Figure 3 2 At high frequencies, the local voltage fluctuation in the channel due to thermal noise couples to the gate through the oxide capacitance, inducing the gate noise current to flow. The spectral density of gate induced noise [37] is (3 13) i g S D G v ch1 v ch2 v ch3 v ch4

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43 where =4/3 for long channel device. Since the channel noise and induced gate noise are physically generated by the same noise source, they are correlated. The correlation coefficient is (3 14) The gate thermal noise arises from the resistan ce of gate material. The noise introduced by the intrinsic portion of the gate structure of width W and channel length L is give n by (3 15) R g,sq is the sheet resistance of gate material. The factor of three arises from a distributed effect [42] It will be lowered by a factor of four if the gate is connected from both sides. For ultra deep submicron CMOS, gate current depends mainly on gate source voltage bias and gate area. Just as any cur rent across the junction, gate leakage exhibits shot noise with current density combined with induced gate noise, it will limit noise performance. 3.3 Topologies of LNA s In an RF receiver, the input signal from an antenna is amplified by an LNA. As shown in Friis equation, to sufficiently suppress the noise contribution from following stages, an LNA should have high gain and its noise contribution to the system should be low. In portable devices, the power consumption should also be low select filter. Otherwise, the insertion loss and pass band ripple of the filter will be degraded. Even without a preceding filter, the LNA needs to provide proper impedance to the antenna. However, simply shunting a 50 performance of the amplifier. Generally used topology is common gate (CG) and source degenerated common source (CS) topol ogy, as shown in Figure 3 3.

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44 Figure 3 3 Two types of LNA topologies. A) CG LNA and B ) CS LNA The input impedance of the CG LNA stage is approximately 1/ g m1 of the input transistor M1, while that of the CS LNA is (3 16) Z in is specified by choosing L g and L s to resonate with C gs at the operating frequency. Its real part T L s A fundamental difference between these two input matching networks is that CS LNA uses a series resonant circuit while CG LNA employs a parallel resonant circuit. The quality factors of two input networks are (3 17) Typically, while It is well known that sensitivity of Z in to component variation is proportional to the quality factor of matching network. Hence, CG LNA with its lower Q parallel resonant network is more robust ag ainst typical component variations. Z load Z load R s R s L g L s A B M1 M1

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45 Moreover, parasitic capacitance at the CG LNA input is naturally absorbed into LC tank. The effective transconductance of the CS LNA is (3 18) With the input matched to R s (3 1 9) In contrast, the effective input tranconducance of CG LNA under perfect input matching conditions is (3 20) T 0 typically is in the range of 3~5, depending on the operating frequency and the technology. Therefore, CS LNA provides higher gain than its conventional common gate counterpart. Especially, in high frequency circuits, the gain boosting by input matching network is often utilized. 3.3.1 Gain of CS LNA To drive the complete gain of CS LNA, a simplified circuit shown in Figure 3 4 is analyzed. In CS LNA, the short circuit transconductance G m is given in Equation 3 18 and output impedance is Z load if r o is sufficiently large. However, with CMOS device scaling, r o of intrinsic transistor becomes smaller and its ef fect has to be considered into gain calculation. Extra Element Theorem (EET) [43] is utilized to make calculation much easier. This method is a powerful way to identify the effect of one particular element on w hole network. Following the procedure in [43] r o is assigned as an extra element and initially it is assumed open. The voltage gain is

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46 (3 21) Where and Figure 3 4 CS LNA and its equivalent circuit. The impedance Z n seen by r o with V in adjusted to yield V out =0 is (3 22) The impedance Z d seen by r o with V in =0 at resonant frequency is (3 23) The complete voltage gain at resonant frequency is (3 24) r o Z loa d d Z loa d L s L g R s r o R s L g L s C gs V out V in i A B

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47 When and Equation 3 24 can be simplified as (3 25) The effect of finite output resistance r o on ga in of the amplifier is shown in Figure 3 5 When r o is same as Z load gain drop is 3.5dB compared to an amplifier having an infinite output resistance. Rewriting Equation 3 25 as (3 26) It indi cates output node has parallel combination of and is the output resistance of common source tuned LNA. Figure 3 5 Output resistance effect on gain. 3.3.2 Noise Fa ctor of CS LNA It is first discussed in [47] that gate induced noise could play an important role in noise performance in high frequency LNA s Figure 3 6 shows the network including three noise

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48 sources: gate ind uced noise i g channel thermal noise i d and source voltage noise v n Output short circuit noise current i 1 is calculated. Figure 3 6 Noise sources in CS LNA. It is easy to show that the relationship between the output noise current i n 1 and gate induced noise i g and channel thermal noise i d is given by (3 27) where is the MOSFET current gain from gate to drain. If Z g and Z s are defined as R s + g and s Equation 3 27 can be rewrit ten as (3 28) At the resonant f requency, this relationship can be rewritten as (3 29) Similarly, the output noise current due to input voltage noise source is (3 30) At the resonant frequency, it is simplified as v n i d C gs i 1 =i n1 +i n2 Z g Z s i i g

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49 (3 31) The total output noise current is i 1 =i n1 +i n2 (3 32) Noise factor of the amplifier will be ratio of total output noise power ( i n ) to the output noise power contributed by input noise sour ce ( v n ). (3 33) The detailed derivation is given i n Appendix A. It is shown in Equation A 5. (3 34) The result is the same as that in [47] [48] Unlike the procedure taken in [47] which calculates uncorrelated and correlated parts in gate induced noise separately, the derivation here directly gives total output noise current spectr al density including the correlation between gate induced noise and cha nnel thermal noise. I ncluding gate inductor resistance, noise factor is (3 35) Noting that and (3 36) Substituting Equati on 3 34 and 3 26 into Equation 3 35 results in (3 37)

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5 0 3.3.3 Noise Factor of Cascode Amplifier An LNA is generally implemented with a cascode stage to improve the stability by isolating the input port from output port voltage variation as shown in Figure 3 7 The isolation makes the design more straightforward. At low frequencies, for long channel device which has high output resistance, the noise contribution from the upper transistor M2 is be lieved to be much lower than that from the bottom transistor M1. It is suggested [49] [50] that optimal choice of M2 is a bout same as M1. Other author [51] has suggested ratio of width of M2 and M1 ranging from 0.55 to 0.75. Figure 3 7 S chematic of cascode amplifier. For an LNA operating near 20GHz, the effects of drain to body capacitance on noise performance and effects of M2 should be more carefully considered. The noise contribution from M2 to output noise can be readily derived using Equation 3 27 where and Here is output re sistance of M1. (3 38) Z load R s L g L s M1 M2

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51 At ~20 GHz, giving (3 39) Where the spectral density of output noise current due to M2 is (3 40) is the c urrent gain of M2. Figure 3 8 Schematic calculating output noise current from common source stage. To calculate the noise contribution from M1 to output, the current derived in Equation 3 27 can be treated as the short circui t current in Norton equivalent network with output resistance of 2 r o as modeled in Figure 3 8 It can be shown (3 41) Since the noise from M1 and M2 are uncorrelated, the spectral density (PSD) of total output noise current is superp osition of three no ise sources: source, M1 and M2. C gs i n_1 i i x 2 i C db 2r 0

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52 (3 42) F 1 is defined in Equation 3 36. W 2 and W 1 are the width of M2 and M1, respectively. This equation shows there is an optimal selection of Q gs to minimize no ise factor. Figure 3 9 Noise contribution from a cascode amplifier. To illustrate how Q gs affects noise factor, Equation 3 41 is used to calculate total noise factor and noise contributions from different noise sources. Sin c e there is no accurately measured channel device are 2 and 4, three times of their counterparts of long channel devices. Here Q ind is set to be 20, which is the measured value for a n inductor test structure around 24GHz. C r is assumed to be 2. M2 and M1 are assumed to have same width. Figure 3 9 shows that noise factor has a minimum point for at optimal Q gs_opt Noise factor rapidly decreases with increasing Q gs until reaching the mi nimum point, then slowly increasing with slope proportional to Q ind It indicates that gate induced noise from M1 begins to

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53 dominate. The noise contribution from M2 monot onically decreases with Q gs Noise figure only varies ~0.1dB for Q gs r does not change much due to the Q gs variations resulting from technology variation. 3.4 24GHz CMOS LNA Implementation Following the theoretical analysis of the LNA design, several circuits have been implemented in the UMC 130 nm CMOS logic process. In B SIM3v3 model thermal channel modeling parameters will cause selection of Q gs and the noise simulation results inaccurate. Q gs in the design are set to 3.2 and it can tolerate 10% component variations [51] Higher Q gs means smaller transistor size for a fixed resonant frequency and it also means lower power consumption for a fixed gate bias of M1. In the 130 nm technology, supply vol tage is 1.2V and voltage headroom is limited. These LNA s are designed to operate at ~24GHz which is the working frequency of 3.4.1 A 24 GHz Single Ended CMOS LNA Figure 3 10 (A ) shows the schematic of the single ended LNA. The CMOS transistors M 1 and M 2 The measure d cut off frequency f T is about 60~70GHz. Two 6 pF bypass capacitors are put between V dd V g2 and ground to eliminate any inductance effect associated with wires connected to these two nodes. The bypass capacitors are implemented with accumulation mode MOS capacitors in an n well 2 Since capacitors C 1 and C 2 in the signal path are for capacitively transforming impendence and de coupling the dc output of the amplifier, voltage drop across this kind of capacitor may cause capacitance shift. More importantly, the large parasitic capacitance and substrate reactance associated with the n well will degrade the gain performance, especially that of C 1 These two capacitors are implemented with metal to metal

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54 capacitor structures The other benefit of metal to metal capacitor is much higher Q than that of MOS capacitor s. Using Metal 5 2 The parasitic f (in GHz) is (3 43) 6 ( H/m 7 m To reduce the resistive loss, stacked metal layers are preferred to implement inductors to increase quality factor ( Q ) [55] Especially, the resistance of L g degrades the NF of the LNA. However, use of multiple metal layers significantly increases the parasitic capacitance and lowers the self resonance frequency of the 1 nH gate inductor ( Lg ). Because of this, the inductors are implemented using the 0.8 thick top metal layer. The metal thickness is twice of the skin depth so that whole vertical dimension of metal layer is conducting AC current. To reduce the resistive loss, a wider inductor trace is preferre d. But, once again, increasing parasitic capacitance lowers the self resonance. To balance these two opposite tendencies, the inductor proximity effect. A polysilicon ground shield is placed underneath the inductor [52] [54] to reduce the loss resulting from capacitive coupling to silicon substrate. Since the Q of output network i s dependent on Q d of load inductor L d (0.73nH), to tolerate the process variation, Q d is set to 14. The trace wid L d L s in the circuit is only 120pH and it is designed with a short metal line. Figure 3 10 The circuit is probed wit h GGB ground signal (GS) probes. M1 is biased using an off chip bias tee. The gate voltage of M2 is set to Vdd. The S parameters are measured with an HP8510C

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55 network analyzer. The measurement result is shown in Figure 3 11 Biased at 1.9mA from a 1.2 V supply, | S 21 | has a peak of 6.1dB at 23.5GHz. The minimum NF is 5dB, as shown in Figure 3 12 The linearity is measured with 2 tone input signals at 23.5GHz and 23.51GHz. Inpu t referred third order intercept point (IIP3) is 6dBm, as shown in Figure 3 13 B Figure 3 10 Single ended LNA A) a schematic and B ) a die photo. L s L g L d V g2 Out In C bypass2 C bypass1 C 1 C 2 M 2 M 1 V dd Out In GND GND V g2 V dd L g L d L s C bypass1 C bypass2 A

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56 Figure 3 11 S parameter of the LNA. Figure 3 12 Noise figure of the LNA.

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57 Figure 3 13 IIP3 measurement of the LNA. 3.4.2 A 24 GHz Differential CMOS LNA A single ended LNA is sensitive to parasitic ground ind uctance. The end of the source degeneration inductor ( L s ) connected to ground is supposed to be at the same potential as the ground bond pad. However, there is always voltage drop between these two points because there is always some finite impedance betwe en them which can have a large effect on amplifier performance. Even worse, it can form a parasitic feedback loop from following stages, and the amplifier can become potentially unstable. Generally, this issue is not severe on chip since the distance betwe en these two points is sufficiently short. However, at 24GHz and higher, this can no longer be neglected. An alternative is to exploit the virtual ground located at the symmetry point of a differential structure. Any series parasitic impedance connected to common mode nodes will not affect input matching impedance. Another important advantage of differential topology is common mode signal rejection. To maximize common mode rejection at high frequencies, it is important to keep symmetry in layout.

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58 Figure 3 14 Differential LNA (a) Schematic and (b) D ie photo. In+ In L g L g L d L d L com Out Out+ V g2 V dd V g2 V dd B GND GND GND GND L d M 1 M 3 L d M 2 M 4 L s 1 L s 2 L g L g In+ In L com m Out Out+ A

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59 Figure 3 15 S parameters of differential LNA. Figure 3 16 NF of the differential LNA.

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60 Figure 3 17 IIP 3 o f the differential LNA At the same DC bias, a differential LNA consumes twice as much power of that of a single ended amplifier with the same gain and NF. The linearity of differential LNA is improved because input power is split and each of input devices only sees half of voltage compared to single ended counterpart. The schematic of the differential LNA is shown in Figure 3 14 (A). An additional inductor L com is added at the common node of input differential pair (M1 and M2) to resonate with parasitic capacitances of L s1 and L s2 This increases the impedance at resonant frequency and enhances the common mode rejection. The die photo is shown in Figure 3 1 4 (B ). single ended one. The LNA is measured with ground signal signal ground (GSSG) probes. The single ended output of network analyzer is converted to differential signal s using a balun. The measured S parameters are shown in Figure 3 15 At 23.5GHz, |S 21 | is 6dB at 1.2 V V dd The dc bias current

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61 is 3.3mA. Power consumption is 4mW. The measured NF of the differential LNA is 5.3dB at 23.5GHz, shown in Figure 3 16 Figure 3 17 shows the linearity measurement result. The IIP3 of differential LNA is 2.4dBm, ~3dB higher than that of a single ended one. Table 3 1 summaries the performance of the single ended and differential LNA s Table 3 1. Summary of performance of single ended and differential LNA. LNA Topology Current (mA) Power (mA) Gain (dB) NF (d B) IIP3 (dBm) Single ended LNA 1.9 2.3 6.1 5 6 Differential LNA 3.3 4 6 5.3 2.4 3.4.3 Device Characteristic Figure 3 18 S ubstrate network of a MOSFET. A) Simple substrate network. B ) Substrate network model of [45] The measured gain of LNA is significantly lower than that of simulated one which is ~13dB. One major reason of the mismatch is inaccurate device modeling. Although BSIM3 model has been demonstrated accuracy in de for relatively low frequency applications, it requires modifications for uses at 24GHz [44] One important factor is that substrate resistance is neglected in BSIM3v3 model. To take account for the effect of substrate resistance, two ways for augmenting the core transistor based on BSIM3v3 model are shown in Figure 3 18 Both models use extrinsic capacitances to account for source/drain body junction capacitances. The diode capacitances of MOSFET s are set to zero. So A B Gate Drain Drain Gate C jdb C jsb R sub C jdb R db C jsb R sb R g R g

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62 bias dependant capacitance has to be extracted from measurement instead of being defined by simulator. Figure 3 18 (A ) shows the approach of connecting a resistor to the bulk node. The output impedance consists of C jdb in series with R sub When the transistor is off (gate bias is zero), r o of the transistor is large so that the real part of impedance looking into the d rain node is R sub at low frequencies. It is expected that at high frequencies C js b tends to bypass the signal, reducing the real part of substrate impedance from R sub towards zero. However, the measurement shows a constant R over a large frequency range [44] Simply adding a substrate resistance to the bulk node of the transistor does not properly model the substrate resistance effect. A new BSIM3v3 RF model [45] is re alized by adding R g R db and R sb as shown in Figure 3 18 (B ). The substrate resistance and drain junction capacitance can be extracted after converting S parameters to y parameters, (3 44) Figure 3 19 Extracted R db and C db

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63 Since source is connected to ground, R sb can not be extracted. R sb and R db may not be the same since they are determined by the layout. The extracted R db and C db are shown in Figure 3 19 At 24GHz, R db C db is ~18fF, giving an equivalent parallel output resistance (3 45) This means R db further lowers the output resistance of the transistor, considering smaller r o of short channel devices. The total output resistance is R out // r o which means significant reduction of gain. R db and R s b also contribute to output noise. A cascode amplifier is simulated with 14 wide common source and common gate transistors. Figure 3 20 R sub effect on output resistance of a cascode amplifier. The amplifier output resistance with and without R sub is plotted in Figure 3 20 At lower frequencies, R sub does not make much difference. However, at 24 GHz operating frequency, the output resistance drops by ~30% in the presence of R sub

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64 3.4.4 A 26 GHz CMOS LNA with Negative Impedance To achieve higher gain, there are two choices: cascading more stages or boosting single stage LNA gain by con suming more power. However, increasing power is not acceptable for resistance is generated in the signal path [58] Cross coupled VCO like circuitry has been demonstrat ed in [46] But it introduces additional power consumption. Figure 3 21 Schemes for generating negative resistance. A) Source follower with capacitive load. B) Gate inductor at a common gate amplifier. Figure 3 21(A) shows a source follower with a capacitive load. The impedance looking into the gate is (3 46) The circuit generates negative resistance T 2 C In [57] such a source follower was used after an amplifier containing an inductive load. The negative resistance compensates the resistive loss in the inductor causing effective Q of the inductor to in crease. However, the stability of whole circuit must be ensured which requires proper selection of the value of capacitance C. To implement the source follower it requires one extra stage which means more power consumption. Figure 3 21 ( B ) shows another me ans of generating negative resistance. It is r o C gs r o C gs Z in2 Z in1 A B

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65 well known that a series gate inductor in a common gate amplifier introduces negative resistance looking into the source. The impedance looking into the source of transistor assuming r o is relatively large (~ 3 k ), is (3 47) where is g m /C gs In a cascode amplifier, the negative resistance ( the second term in right hand side ) can be generated without adding an additional stage that consumes power by simply adding a gate series inductor in the common gate stage as shown in Figure 3 22 ( A ). Incidentally, the LNA in [56] is configured in the same way. The resonant frequency of L g2 C gs2 series network is much higher than the tune d frequency and it is proposed to create a notch in | S 12 | t o improve the stability. Looking at the output impedance of cascode amplifier, when the impedance looking into the drain of M1 is defined as Z d1 the output impedance and transconductance at drain node of M2 are, (3 48) (3 49) Increasing L g2 lowers the resistance in the denominator which increases the output impedance and increases transcoductance. At a given gain, this allows the transconductance or bias c urrent to be lowered, which further increases r o of the transistors and output impedance At the resonant frequency, the total simulated impedance at M2 drain node including Z d2 impedance of L d and impedance looking into capacitive transformer ( C 1 C 2 and 50 L g2 of 0.76nH is added, while the short circuit transconductance at this node is increased by ~ 15%. These increase the gain by 4.1dB despite the slight decrease of the voltage gain of common source stage. The load inductor L d is 0.68nH.

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66 L g 2 is 0.76nH which gives L g2 C gs2 series resonant frequency of ~36GHz. A microphotograph of the LNA is shown in Figure 3 22 ( B ). The chip size is 0.45x0.36mm 2 including the bond pads. The S parameters of LNA are measured on wafer using an Agilent E8361A network analyzer and are shown in Figure 3 23(A) Figure 3 22 The LNA with a n indu ctor at the gate of M2. (A) Schematic and (B ) Die photo. In Out L g V g2 V dd L g2 L d GND GND B In Out A

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67 Figure 3 23 S parameters and NF measurement of the LNA. The maximum transducer gain (| S 21 |) is 8.4dB at 26.2GHz, while the reverse isolatio n | S 12 | is 19.6dB. | S 11 | is 8.9dB and | S 22 | is 5. 4dB at 26.2 GHz. S 22 is mistuned due to the C 1 being ~50% larger. The dc bias current is 0.8mA and V DD is 1.0V. When the supply voltage is increased to 1.2V, | S 2 1 | can be increased to 13dB with power cons umption of 2.4mW. Noise figures are measured using an HP8970B noise figure meter and an external mixer, and the de |S 21 | NF B |S 22 | |S 11 | |S 12 | A

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68 embedding technique was discussed in [59] Limited by the instrument, noise figures are measured only up to 26.5GHz. The measured NF is ~5 dB at 26.2GHz, which is shown in Figure 3 23 (B ). Figure 3 24. Stability circles of A) input and B ) output. Stability is a serious issue for using negative resistance cancellation t echniques The stability factor, K ranges between 0 and 1 from 26.4 to 31.3GHz. B1 is always larger than 0. In this frequency range, the amplifier is not unconditionally stable. This is due to the mismatch between p eak | S 21 | and output matching (| S 22 |) frequencies. The input and output stability circles for 26.3 to 30.5GHz are drawn using the measured S parameters and shown in Figure 3 24(A) using method in [60] The LNA is stable in ~75% of the S plane. The LNA input typically sees the output of a filter or an antenna whose impedances can significantly vary, and this is a potential limitation. A s shown in Figure 3 24(B) the LNA is stable in ~90% of the L plane. Since t he LNA will eventually be integrated with other components that have known and well controlled impedances it should be possible to make sure the load for the LNA is within the stable region. Simulations indicate that the potential instability near the tun ed frequency is not an inherent consequence of using the negative resistance circuit and it should be possible to r e tune A B

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69 the circuit so that is unconditio nally stable over a bandwidth of 10 GHz around the tuned frequency. Figu re 3 25 IIP3 of the LNA. The input referred third order intercept point (IIP 3 ) of LNA is measured with two tone input signals at 26.2 and 26.21GHz. IIP 3 is 13dBm, as shown in Figure 3 25 This is ~7dB lower than that of the amplifier without the negativ e resistance circuit. The simulated voltage drop across the gate and source of M2 is 1.8 times of that of M1 and the linearity of this circuit is limited by M2. Table 3 2 compares the performance of CMOS LNA s working above 20GHz. The LNA with a gate induc tor at M2 has reasonable gain and NF performance compared to most of the previously reported LNA s while consuming significantly lower power. Compared to the 24 GHz single ended LNA without L g2 fabricated in the same 130 nm CMOS process, the power gain is ~ 2 dB higher while consuming ~ one third of the power. It should be possible to achieve gain of

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70 ~16dB by using a two stage design and doubling the power consumption Even after this, the circuit should consume power that is more than 5 lower. Table 3 2 P erformance comparison between LNA s above 20GHz. Circuit Metrics This work [58] W/O L g2 [62] [64] [59] Process 0.13 C MOS 0.13 CMOS 0.18 C MOS 0.18 CMOS 0.13 CMOS Type Single Single Single Single Differential Frequency (GHz) 26.2 24 23.7 24 20 Gain (dB) 8.4 6.2 12.9 13.1 9 Noise Figure (dB) 5 5 5.6 3.9 5.5 Bandwidth (GHz) 3.7 4 ~2.5 ~4. 8 ~5.3 Supply Voltage (V) 1 1.2 1.8 1 1.2 Power (mW) 0.8 2.2 54 14 24 3.5 Summary In this chapter, the topologies of CG LNA and CS LNA are compared. It shows with the same DC bias current, the CS LNA achieves higher gain because of quality factor of the input network. Because of this, CS LNA is better suited for low power applications, noise figure of CS Q gs of input L C R network is found to be 2 3 to minimize noise figure. Within this region, the design can tolerate the component variations of ~ Single ended and differential LNA s working at ~24GHz have been implemented in a digital 130 nm CMOS technology. By comparing simulated and measured LNA performance, it is found that the substrate resistance and junction capacitance play important roles in determining the gain of LNA. By judicious use of negative resistance a 26 GHz LNA achieving

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71 a gain of 8.4dB and a noise figure of ~5dB at DC power consumption of 0.8mW and V dd of 1.0 V is demonstrated. This work has shown that adding a gate inductor to the common gate stage in a cascode amplifier can significantly improve the power efficiency.

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72 CHAPTER 4 20GHZ RF FRONT END D ESIGN 4.1 Introduction An RF front end including an LNA and a mixer is key component in modern communication s ystems The LNA amplifies weak received signal and suppresses the noise contribution from the mixer. The mixer actually performs frequency translation. This chapter first discusses mixer design in section 4.2. Then a 20 GHz RF front end implemented in a 13 0 nm CMOS technology is demonstrated in section 4.3. Using this RF front end with an on chip antenna as a receiver, 20 GHz AM signal transmitted from 5 m away is successfully picked up and down converted to intermediate frequency (IF). An RF front end with additional IF amplifying stage is presented in section 4.4. 4 .2 Active Mixer A mixer in a wireless receiver down converts an incoming RF signal to an IF. This allows amplification to take place at lower frequency [65] and relaxes the selectivity of IF filter. The earliest radios used 2 nd order non linearity in devices and later on used analog multiplication to accomplish the frequency translation. When local oscillator (LO) signal for the multiplication is hig h enough, it eventually drives the circuit to work in a switching mode. The principle of switching is illustrated in Figure 4 1 RF sign al, represented as a sinusoidal rf(t), is multiplied by a mixing function, an ideal square wave local oscillator, LO(t) varying between +1 and 1. The LO signal toggles the polarity of RF signal at the output. It is easy to see the frequency translation in the frequency domain. The spurs in the output spectrum can be filtered out. R F signal can be either current or voltage and a mixer can be either active or passive. An active mixer consists of a transconductor (M3) and switching pairs (M1 and M2) for current commutation, as shown in Figure 4 2.

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73 Figure 4 1 Switching mode of mixer. Figure 4 2 Active mixer. A ) Single balanced mixer. B ) Equivalent circuit. R L R L g m V(t) i(t) R L R L V(t) M1 M2 M3 A B

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74 4.2.1 Conversion Gain In an active mixer, the switches reverse the polarity of the load current at the LO frequency. The transcondutance current is (4 1) The LO is a square wave generating a mixing function, it can be expressed as Fourier series, (4 2) The output current will be the product of the current I rf (t) a nd mixing function V LO (t) then output voltage is this current times output load, R L (4 3) Ignoring the harmonics of LO gives (4 4) Eliminating the up converted term, the resulting down converted signal at output is (4 5) Therefore, assuming a perfect square wave LO, the voltage conversion gain through the mixer is given by the well known expression (4 6) The expression only holds when the LO voltage is large compared to t he V gs V th of the switching devices. However, this assumption is barely satisfied in most cases where the LO is driven by the output of an on chip VCO or PLL, which is generally a sinusoidal wave. More

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75 accurate voltage gain estimation is given in [66] It takes into account the time when both of switches are conducting current by averaging the voltage gain over one period of the local oscillator. When the differential LO amplitude is sufficient high, only one tra nsistor in the switching pair carries DC current from M3, turning off the other. It is found in [67] that this amplitude is where is the DC gate overdrive of switching tr ansistors is. If the LO amplitude is less than this critical value, both transistors are conducting current. Assuming the local oscillator can be represented as a sinusoidal wave, t he time that the switches move from the state whe n both switches conduct current denoted t BAL to another state when only one of the two devices are conducting current can be determined by the following relationship: (4 7) Assuming for small this gives (4 8) During time 4 t BAL in one LO period, both switches are on and the RF current appears at the common mode nodes of the differential pair which does not contribute to differential output current. Only the current during t he period when one switch is on contributes to output voltage. So the conversion gain can be rewritten as [66] (4 9) Figure 4 3 shows mixer gain changes from ideal switching in Eq. (4 6) wi th ratio of LO signal amplitude to To make a mixer work with less than 3 dB gain drop from the ideal switching, an LO signal amplitude should be at least 3

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76 Figure 4 3 Mixer gain dro p from ideal switching. 4.2.2 Noise in Active Mixer The noise analysis in a mixer is different from the traditional white noise analysis for linear and time invariant systems. In a mixer, the frequency domain method is suitable for RF noise in the transcon ductor, but not for the noise from the switching pair. The noise of switching pair can be solved using a stochastic differential equation (SDE) [68] [69] However, i t involves numerical solution not intuitive. So the mixer noise analysis follows the method in [70] ixer. The mixing function in Equation 4 2 only generates signals at funda mental frequency and its odd harmonics. As shown in Figure 4 4 The LO frequency and its odd harmonics will down convert the respective frequency band of white noise to IF [71] The noise is uncorrelated at each sideband and frequency, and various noise power contributions can be simply summed. The total output spectral density at IF due to transconductor M3 in Figure 4 2 is (4 10)

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77 where is the channel thermal noise of M3 The first term is the white noise at f LO f IF down converted by the fundamental of LO, the second term is noise at 3f LO f IF down converted by the third harmonic of the LO, whose amplitude is one third of the main harm onic of the LO, and so on. Equation 4 10 says that the thermal noise current in the transconductor is totally transferred to mixer output, just like in an amplifier. This is due to the fact that the noise is periodically inverted without changing the gene ral properties of noise in time domain [63] Figure 4 4 Frequency translation of white noise in a transconductor. 4.2.3 Thermal Noise f rom Switching Pair When LO voltage is much g reater than of the switches, the LO switches behave like the common gate stage of a cascode amplifier and there is minimal output noise f LO 3f LO 5f LO 1 1/3 1/5 f IF f IF

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78 contribution from the switching transistors. When LO voltage is less than of t he switches, the LO switches behave like a differential pair. Figure 4 5 Time varying transconductance G(t). Figure 4 5 both M1 and M2 are turned on and contribute to the output noise. It is shown in [70] that the time variant noise PSD at one output port is (4 11) T he corresponding total output noise PSD of the mixer, which is twice of that at one port, is (4 12) W here G(t) V x V x V LO (t) G(t) Triangle Approximation

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79 is the transconductance of differential pair. As shown in Figure 4 5 the transconductance and output nois e is periodic. V x determining whether one transistor or both transistors conduct current. When V LO > |V x |, the differential signal is so strong that only one transistor is on while the other is turned of f. The time average PSD at the output is (4 13) The output noise is dependent on the average of G(t). As shown in Figure4 5 G(t) can be approximated as a triangle shape with a period of T LO /2. G(t) is determined by the smaller of g m1 or g m2 It reaches the maximum when g m1 and g m2 are equal. This point is located at zero crossing of V LO which means the gate bias of M1 and M2 are equal. The average of G(t) can be calculated by the area of one triangle divided by a half period of LO. Th e area of triangle is determined by the peak transconductance and turn Considering (4 14) Total output noise spectral density is given as (4 15) The same conc lusion on mixer noise dependence on LO signal amplitude and bias current is given in [71] The mixer in [72] is the same as the mixer used in this work. A NF vs. LO p ower plot is shown Figure 4 6 It shows that increasing LO power lowers noise figure.

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80 Figure 4 6 NF vs. LO power of Mixer In mixer design, higher bias current increases the transconductance of M3 and therefo re the conversion gain. Even though the output noise contributed by M1 and M2 are increased by I B as shown in Equation 4 15 noise figure of mixer is reduced. A larger LO amplitude increases the conversion gain and reduces the noise contribution of switchin g pair. Increasing the channel width of M3 is desirable because this increase g m3 and therefore the conversion gain and reduces the noise figure. However, larger channel width of M3 introduces parasitic capacitance, which can degrade the performance at hig h frequencies and increases the load for the circuit driving the mixer. 4.3 A 20 GHz Font End with On c hip Antenna A 20 GHz RF front end with an on chip antenna has been developed to demonstrate the consumption of the receiver, the gain of down converter is kept as low as possible while achieving sufficiently low noise figure. Fully differential circuits thou gh consume more power are utilized to make the connection to the

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81 dipole antenna without using a balun as well as to better reject the common mode noise from the digital circuits which will eventually be integrated. Figure 4 7 Schematic of LNA and Mixer. Figure 4 7 shows the schematic of the RF Front end including an LNA and a mixer. The LNA utilizes the cascode topology. Source degeneration is used to generate resistance for input matching. The output of LNA is capacitively coupled to the mixer. The mixer is double balanced Gilbert cell type. The conversion gain of th e mixer is ~1dB. A differential inductor is inserted between the drain nodes of two Tran conductors (M5 and M6) to tune out the capacitance at these two nodes. This increases the mixer gain and improves the image rejection of down converter [79] and mixer are replaced by inductors to provide larger voltage headroom. Shielded pads are put underneath both RF and LO ports t o prevent the l oss of signal and noise coupling associated with L g1 L g2 LO+ IF V dd RF+ RF LO+ LO IF+ M1 M2 M3 M4 M5 M6 M7 M8 L d1 L d2 L d3 L d4 L2 L1 L3 L s1 L s2 C1 C2 M9 M10

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82 substrate resistance [80] Ground rings are placed around the transistors at minimum distance to reduce the substrate loss. The gate of LNA and mixer are biased t hrough 5 resistors. The LNA and mixer have separate supplies and large on chip bypass capacitors are placed between each supply and ground. Figure 4 8 Die micrograph and antenna cross section. The performance of wireless communication is critically dependent on antenna. The recent work [81] has shown on chip antennas built on moderate resistivity substrates (5 20 sufficient for use up to 5m and possibly larger sep arations. The antenna used in this work is a 3mm long zigzag dipole with a bend angle of 30, shown in Figure 4 8 The 3 mm length a thick metal layer is prefe thick metal 1 6 layers. The antenna is implemented in metal 1 4 layers to make the thickness of metal layers used to fabricate on chip antennas comparable to that of the previous work [ 81] The design rule width rule, the antenna is formed with 3 LNA Mixer Pad Vias Metal 1 4 Feed line 3mm long zigzag dipole 0.88mm 0.83mm

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83 chip edge. It is shown i n [81] that closer distance between on chip antenna and chip edge reduces the attenuation due to lossy substrate. The die micrograph is shown in Figure 4 8. Antenna traces cannot be seen, since they are built wi th the lowest 4 metal layers.The antenna is drawn to front 2 The total area is 1.1mm 2 Fi gure 4 9 Reflection coefficient at IF and RF ports. To characterize the downconverter performance, the antenna is cut from the LNA and mixer. S parameters are measured at IF and RF ports by using HP8510C network analyzer. RF, IF and LO ports are probed u sing ground signal signal group (GSSG) probes. The reflection coefficient is shown in Figure 4 9 At IF port, the reflection coefficient is below 10dB from 2.4GHz to 3.1GHz. At RF port, the reflection coefficient is below 10dB from 19.5GHz to 21.1GHz. Th e RF input and IF outputs are well matched at their respective frequencies.

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84 Figure 4 10 The Gain and NF vs. Frequency plots for 20 GHz downconverter. The conversion gain and noise figure measurements are performed at 1.5 V and 1.2 V supply voltage. The results are shown in Figure 4 10 The power gain is measured as a function of the RF input frequency. The LO frequency 3GHz below the RF frequency was swept with the RF frequency. The external LO power applied to one LO port is 2 dBm, equivalent to a peak to peak voltage swing of 0.8V. The power gain of RF image is also measured. It is measured at the corresponding RF image frequency. For instance, the image of 20 GHz RF signal is located at 14GHz, two times IF frequency away from the 20 GHz RF frequency. The image rejection of the front end is 24dB at 20GHz. This performance is achieved by using large IF and properly tuning LNA and mixer. The single side band (SSB) NF is measured as a function of the RF input frequency with fixed L O frequency of 17GHz.

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85 A B Figure 4 11 Linearity of down converter at V dd of A) 1.2V and B ) 1.5V

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86 Besides being the first receiver fabricated in a low cost foundry process to have an on chip antenna, the circuit achieves 9 and 6.6dB conversion gain and SSB noise figure at 20GHz,while consuming extremely low power of 12.8mW with V dd =1.5V. Compared to the LNA and mixer combination of a 17 GHz front end fabricated in a 130 nm CMOS technology [62] which has been shown to possess competitive overall performance as receivers fabricated using a 100 GHz f T SiGe BiCMOS technology [77] [78] the down converter has comparable noise performance while consuming less than half of the power. When the supply voltage is reduced to 1.2V, the circuit has a maximum power gain of 7dB, minimum NF of 7.2dB. The power consumption is less than 25% of the LNA and mixer in [62] The linearity is measured with two RF tones at 20GHz and 20.02GHz with LO signal of 17GHz. Figure 4 11 shows the IIP3 measurement with supply voltage of 1.2V and 1.5V. Table 4 1 summaries the measurement results. Table 4 1. Performance of the RF front end Supply Voltage 1.5V 1.2V RF 20GHz IF 3GHz Chip Area 1.1mm 2 Power Consumption 12.8mW 7.3mW LNA Current 4.7mA 2.8mA Mixer Current 3.8mA 3.3mA Power Gain 9dB 7dB Noise Fi gure 6.6dB 7.2dB Input IP3 10.9dBm 11dBm The operation of RF front end with an on chip antenna is demonstrated by transmission of an AM signal and down conve rsion of this signal to IF. The measurement setup is shown in Figure 4 12(A). The transmitted signal is generated by an Agilent 8254A. A 20 GHz carrier is amplitude modulated with 100 kHz sinewave with modulation depth of 50%. For a given modulation depth: m the power difference in dB between that for a ca rrier and the sideband on either side is expressed as,

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87 dB. (4 16) E sub represents the power level of an either sideband while E c represents carrier power level. For m =50%, the power level difference between is 12dB. A Figure 4 12 Interchip wireless c ommunication over free space. A) Measurement setup and B ) Measurement environment. The single ended AM signal is conve rted to balanced signals using a balun and fed to a transmitting antenna which is a 3 mm on chip zigzag dipole with a signal signal (SS) probe. The power delivered to the antenna is 10dBm. The transmitting antenna is placed on a mobile probe stand made of Derlin [81] which is type of plastic with dielectronic constant of ~3.7. The probe stand is located 5m away from the receiver. The receiver is mounted on a thick glass substrate isolating the effect from the me tal chuck underneath. The RF, LO and IF biases are provided Receiver Transmitting Antenna 5m LO O IF DC Chip B Spectrum Analyze r Signal Generator Balun Balun GSSG Probe IF Amp GSSG Probe R X 3GHz TX R X

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88 using GSSG probes and DC probes. The IF output is amplified using an external amplifier with 26 dB gain. The measurement environment is shown in Figure 4 12(B) which is in the 5 th floor lab. Figur e 4 13. Received spectrum. The received (resolution bandwidth of 300Hz) spectrum is examined by using an HP8563E spectrum analyzer. The output spectrum is shown in Figure 4 13. The power at 3GHz IF is ~ 53.8dBm. The power gain b etween transmitting antenna and receiving antenna is calculated to be ~ 99dB including the effects of metal structures. The two sidebands 100kHz away from the IF have power levels of ~ 66.5dBm and 66dBm, which are 12.7 and 12.2dB lower than that of the ca rrier. Those power levels are close to the theoretical values. This indicates that the transmitting RF signal is picked up by antenna and down converted by RF front end. The extra sidebands in the spectrum are due to spurs of signal generator. The backgrou nd noise is ~2dB higher than that

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89 of spectrum analyzer due to the noise resulting from the thermal noise of received signal and noise of the down converter. For the first time, this work [82] shows that a pair o f IC s with a compact on chip antenna can communicate over free space and it is feasible to implement a low power 20 GHz down converter using mainstream digital CMOS technology. 4.4 A 20 GHz RF Front End Including LNA, Mixer and IF Amplifier The previous RF down converter with LNA and mixer has only 9 dB gain. A two stage IF amplifier is added to increase the overall gain to better suppress noise contributed by following analog baseband stages such as variable gain amplifier and low pass filter. Its schemati c is shown in Figure 4 14 Figure 4 15 shows the diagram of this RF front end. The circuit was once again implemented using UMC 130 nm CMOS logic technology. The die photog raph is shown in Figure 4 15 The input/output reflection coefficients were measured with an HP8510C network analyzer, and shown in Figure 4 16 The circuit was once again implemented using UMC 130 nm CMOS logic technology. Figure 4 14 IF amplifier schematic. V in V out L d1 L d1 L d 2 L d 2 M 1 M 2 M 3 M 4 M 6 M 7 M 8 M 9

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90 Figure 4 15 A Front end with an IF amplifier Figure 4 16 Measured matchin g properties at IF and RF ports.

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91 Figure 4 17 Power gains at input and image frequencies. The conversion gain is measured at varying RF and LO frequencies, keeping the constant 3 GHz IF. As shown in Figure 4 17 the maximum power gain achieved is 24dB at 20.5GHz. The image rejection ratio is ~23dB. At 1.5 V Vdd, this RF front end only consumes 17.7 mW power while achieving 29.5 dB gain. Compared to the front end with LNA, mixer and IF a mplifier reported in [76] which achieves 34.7 dB at 58 mW power consumption, our circuit shows a significant power reduction. Table 4 2 compares the circuit in [76] and our circuit. Table 4 2. Performance comparison between our down converter and the one in [76] Circuit metrics [76] Our work V dd ( V) 1.5 1.2 1.5 LNA Power (mW) 5.2 3.5 3.5 Mixer Power (mW) 27 3.8 3.8 IF Power (mW) 25.8 7.5 10.4 Total Power (mW) 58 14.8 17.7 Gain (dB) 34.7 24 29.5 4.5 Summary ed an 20 GHz RF front end with an on chip antenna which can receive transmitted AM signal and down

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92 convert IF. This RF front end consumes much lower power compared to those previously reported circuits. For the first time, we demonstrated the feasibility of a pair of IC s communicating with each other using on chip antennas over free space. A RF down converter including LNA, mixer and IF amplifier which achieves comparable gain performance while consuming much lower power has been demonstrated. These works show that it is feasible to implement low power 24 GHz communication devices

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93 CHAPTER 5 BUILDING BLOCKS OF R ECEIVER 5.1 Introduction This chapter discusses the design of building blocks in the RF receiver except the RF front end presented in the previo us chapter. Figure 5 1 shows a diagram of the receiver. The passive mixer is briefly described in section 5.2. Variable gain amplifier (VGA) design is discussed in section 5.3. A 2 nd order Butterworth low pass fil ter (LPF) design is presented in section 5.4. The d ivided by 8 circuit is briefly described in section 5.5. The image rejection filter in LNA is discussed in section 5.6. Since the integrated transceiver shares one antenna, to reduce the loss associated wi th a conventional T/R switch, a distributed switch method described in section 5.7 is utilized. In this section, driving LO from the synthesizer is also briefly described. Figure 5 1 Diagram of node receiver. 5.2 Passive Mi xer The second down conversion in the receiver chain is accomplished with a passive mixer, which consumes no dc power. MOSFET s can be easily used to realize the passive mixer. The advantage of passive mixer over active mixer is its higher linearity and low er 1/f noise. But a passive mixer does not provide conversion gain and isolation between RF and IF ports. Figure 5 2 shows a passive double balanced mixer consisting of four transistors in a bridge configuration. LNA IF Amp VGA VGA LPF LPF BUFFER 8:1 LO1 LO2_Q LO2_I baseband signal passive mixer active mixer

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94 The differential signals and turn on and turn off transistors to change the polarity of voltage at IF port. For instance, when is high and is low, M1 and M4 are turned on and I F port has the same polarity as RF port. On the other hand, when is low and is high, M2 and M3 are turned on and IF port has the opposite polarity as RF port. Figure 5 2 Passive mixer. Figure 5 3 Gain vs. LO power in a passive mixer. + + C L M1 M2 M3 M4

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95 The passive mixer was designed and implemented in a 130 nm CMOS technology by A. Verma [83] s measured with 2.7 GHz RF and 2.6 GHz LO frequency. This sets IF at 100MHz. The passive mixer conversion gain vs. LO power is plotted in Figure 5 3. It shows that 2 dBm LO power corresponding to 0.4 V voltage ampl itude will give ~6 dB loss. This passive mixer was modified for integration into final receiver design. 5.3 Variable Gain Amplifier (VGA) Figure 5 4. Schematic of the VGA and its basic amplification stage. A VGA adjusts rec eiver gain according to the received signal amplitude. The VGA needs to support 8 6 dB steps. A 6 dB amplifier is shown in Figure 5 4. Two R1 resistors form common mode feedback with two upper PMOS s Two R2 resisto rs form source degeneration. If R2 is much smaller than the output impedance of two NMOS transistors amplifier V bias V bias R1 R1 R2 R2 In+ In Out Out+

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96 transconductance is 1/R2. If R1 is much smaller than the output impedance of two PMOS transistors the output resistance of the amplifier is R1. Then, the amplifier gain is defined by R1/R2. DC offset must be taken care of for circuits with high gain. The baseband circuit will have three high pass filters, one in front of the VGA t o handle offsets from the preceding stages, one in front of the la st four stages of the VGA and one in front of the LPF to handle the offsets from the VGA. The poles of filters are located at ~200kHz defined by a 1.5 pF AC coupling capacitor and a 500 Figure 5 5. G ain control s cheme. The gain control method is shown in Figure 5 5. There are eight switches attached to the output of eight amplifier stages. These switches are controlled by b0 b7 generated by a 3 bit decoder. At each gain st ep setting, there is only one gate voltage set to high while all other are ntrolled by b0 is on and the VGA has the lowest gain of 6dB. b0 b1 b5 b6 b7 In Out

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97 To measure the VGA, differential input signal has to be generated. A Balun used at high frequencies to convert single ended signal to differential ones is replaced by a discrete differential ampl ifier (AD8138) [84] As shown in Figure 5 6, two printed circuit boards (PCB s ) are connected to the input and output of VGA by semi rigid cables and two pairs of GSSG pr obes. Figure 5 6. Measurement setup of the VGA using differential amplifiers as Baluns. To measure the gain of VGA, two steps are needed. First a THRU structure on a GGB calibration substrate is used to connect two PCB s usi ng the semi rigid cables and GSSG probes. With a 2 MHz sine wave generated from an Agilent 33120A function generator, the power (P thru ) read from the spectrum analyzer is recorded. Then the TRHU structure is replaced by the VGA circuit. The output power ( P VGA ) at varying gain control selection has been measured The ratio between P VGA and P thru gives the voltage gain. The measured gain are shown in Figure 5 7 The VGA gain ranges from 10dB to 35dB over 8 control s teps. However, the overall gain is 13dB lower than the design target. T he gain suddenly drops at step 4. This can be explained using Figure 5 8. When the step 4 is chosen, switch B3 is turned on and it bypasses all the following 4 gain stages and connects C couple and C load in series forming a capacitive voltage divider. C load is single ended input On chip VGA Function Generator Spectrum Analyzer AD8138 AD8138 Semi rigid cables & GSSG probes

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98 capacitance of AD8138 which is 2pF while C couple is 1.5pF attenuation is 7.3dB In normal operation, the VGA will not s ee such large capacitive load, and no such gain drop occurs Figure 5 7. VGA gain vs. gain control step. Figure 5 8. Capacitive voltage divider in the configuration for gain step 4. 5.4 Baseband Low Pass Filter (LPF) The LPF implements the functions of the chip matched filter (CMF) and a nti aliasing filter for the ADC. A second order Butterworth filter provides a good approximation to the spectral V bias V bias B3 C load C couple

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99 shape of the ideal half sine chip pulse and is a practical choice for the anti alias filter. In particular, the Butterworth filter should be designed for a nominal bandwidth of ~ 0.3R c where R c is the chip rate of 51.2 MHz. This leads to a filter bandwidth of 15.36 MHz. Figure 5 9 compares the frequency response of the half sine filter and 2nd order Butterworth while the output pulse shape has o nly weak influence. The equivalent two sided noise bandwidth is 0.62R c for the half sine filter. For a 2nd order Butterworth filter, the equivalent noise bandwidth is 1.11 x BW 3dB [85] Since its 3 dB bandwidth is chosen as 0.3R c the equivalent noise bandwidth for this filter is ~0.67R c Two noise bandwidths would lead to a 0.3 dB difference in output noise power between two filters. Figure 5 9. Half sine and 2 nd order Butterwort h filter frequency response. The LPF can be implemented differentially without employing a common mode feedback (CMFB) loop [86] as shown in Figure 5 10(A ). The common mode voltage is set by adding a diode connec ted NMOS at the internal node of a conventional Gyrator.

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100 Figure 5 10. A) A lossy biquad and B) its equivalent circuit. Impedance looking into the Gyrator is (5 1) Effectively, Z is the series connection of an inductor with value of and a resistor with value of The equivalent circuit is shown in Figure 5 10( B ). It can be shown that (5 2) When is chosen to be this expression becomes (5 3) which can be rewritten as (5 4) where 0 is and Q is It is a 2 nd order Butterworth type LPF. V LP g m0 g m c g m g m g m c 1/g m c 1/g m c/g m 2 A B g m0 V LP V in Z V in

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101 The feature of this circuit is that every tr ansconductor output voltage is determined by diode connected circuit. This eliminates the requirement of common mode feedback circuit. T he positive transconductance in Figure 5 10 (A) can be implemented u sing a nega tive transconductor and a gain stage with 180 degree phase shift. It turns out that in a differential circuit, it is not necessary to implement such a gain stage. We can connect out of phase output signal to the negative transconductor. Figure 5 11. Schematic of the LPF. The pseudo differential circuit implementation is shown in Figure 5 11. All the NMOS transcondutors in the LPF have the same To implement positive in Figure 5 10( A ), the negative output is connected to a negative .When the value of C frequency of LPF is determined by which can be controlled by the bias voltage The cu rrent source in Figure 5 11 is implemented with a PMOS current mirror. The current in whole circuit is determined by so that the bias voltage for PMOS current mirror should be 4I o 2I o 4I o 2I o In+ In Out+ Out V gmc Bias circuitry Core of the LPF

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102 controlled by The filter exploits the near square s to partially cancel nonlinearity. Considering the long channel drain current s of two input NMOS transistors with (5 5) where is differential input. Subtraction of and results in the differential output current : (5 6) Hence, the differential output current is linear with the differential input vo ltage. Figure 5 12. LPF V out and I dd vs. V gmc A test circuit is fabricated in a 130 nm CMOS technology. The s ize of NMOS transistor s is that of PMOS transistors channel device suffers less channel modulation effect and works closely in the square law region. Measured DC

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103 characteristics with a 1.2 V power supply are shown in Figure 5 12. A plot of measu red vs. from 0.5V to 0.8V is shown in Figure 5 13. The plot clearly shows that the NMOS transistors are working in the square law region. Figure 5 13. Near square law of I dd vs. V gmc The AC response is tested with G SSG probes using an Agilent 5230A 4 port PNA. The network analyzer can cove a frequency range from 300 kHz to 20GHz. The calibration steps are to first use E cal to calibrate four cabl es and then use port extension function to calibrate out probe phase delay. Measured 4 port S parameters are imported into Spectre using an N po rt component in analogLib. An AC analysis results in the LPF frequency response in Figure 5 14 Since device is proportional to Equation 5 4 indicates that LPF corner frequency is proportional to The measured corner frequency vs. is shown in Figure 5 15. The co rner frequency varies fr om 24.2 to 44.2MHz by 1.83 times (or 29% tuning range) when is changed by 1.91 times. It indicates that the corner frequency is close to linear with

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104 Figure 5 14. Frequency response and tuning of LPF. Figure 5 15. LPF cut off frequency vs. Sqrt(I dd )

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105 Equation 5 4 indicates the ideal in band gain of LPF should be 0dB while both simulation and measurement show in band loss. The discrepancy can be explained by t aking the device output resistance into account. The ideal LPF network in Figure 5 10 ( A) is redrawn using different diode connected NMOS transconductance and as illustrated in Figure 5 16 and represent the equivalent transconductance combining and the device output resistance. (5 7) As shown in Figure 5 16 is that of a par allel combination of four NMOS and PMOS output resistance while is that of a parallel combination of two NMOS and PMOS output resistance. Figure 5 16. LPF i ncluding device output resistance. The transfer function in Figure 5 16 can be shown as (5 8) V LP 2g m g m a c g m g m g m b c Z Vin

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106 where the in band gain is (5 9) Since and are both greater than the in how the in band gai n changes with bias current. To the 1 st oder approximation, assuming and E quation 5 9 is rewritten as (5 10) It shows that the LPF in band loss increases with bias current. This trend has been verified by the simulation and measurement. Equation 5 8 also indicates that LPF corner frequency and network Q are affected by the device output resistance. Figure 5 17. Simulated LPF IP 3 IP 3 of LPF is simulated by using two input tones at 7MHz and 8MHz with 0.6 V V gmc Output power of fundamental tone at 7MHz and 3 rd or der intermodulation distortion tone at 6MHz are plotted in Figure 5 17. Simulated LPF IP 3 is 6.4dBm, or 6.6dBVrms and P 1dB

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107 simulated at 7MHz is 6.8dBm, or 19.8dBVrms. Table 5 1 compares the measured and simulated results of in band loss and corner frequency. Table 5 1. Measured and simulated in band loss and corner frequency of the LPF. V gmc Measured in band loss(dB) Measured c ut off frequency (MHz) Simulated in band loss(dB) Simulated c ut off frequency (MHz) 0.50 0.59 24.2 0.73 24.2 0.55 1 28.2 0.78 28..2 0.6 1.34 31.2 0.84 30.2 0.65 1.76 35.2 0.9 34.2 0.7 1.95 38.2 0.99 37.2 0.75 2.3 42.2 1.13 39.2 0.8 2.8 44.2 1.49 41.2 5.5 Frequency Divider As show n in Figure 2 3 the radio uses dual down conversion architecture. The first LO signal is at 21.3GHz generated by a frequency synthesizer and the second LO signal of ~2.7GHz is generated by a frequency divide by 8 circuit. This divider is implement ed by cascading three 2:1 current mode static frequency dividers. Figure 5 18. Block diagram of the 2:1 static frequency divider. The divider shown in Figure 5 18 was designed by Changhua Cao [87] For completeness, its function is briefly described. Th e divider is based on the master slave D type flip flop in which the inverted slave outputs are connected to the master inputs. This type of divider can achieve a wide operating freq uency range, consuming a smaller silicon area while generating CK b D D b Q Q b D D b Q Q b CK OUT OUT b

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108 quadrature signals. As shown in Figure 5 19 each master slave flip flop is impl emented using current mode logic (CML). The master and slave stages con sist of an evaluate stage (M 1,3,4 ) and a latch stage (M 2,5,6 ). The current sources in conventi onal CML latches are omitted in Figure 5 19 for lo w voltage operation. Figure 5 19. Sche matic of the 2:1 static frequency divider. 5.6 Image Rejection Fil t er in LNA The final receiver design includes an extra LNA stage and incorporates image rejection filter in the LNA. To improve the image rejection, two notch filters used in [88] are added in the LNA stage, as shown in Figure 5 20 The impedance looking into the notch filter is (5 11) The image frequency is located at the zero of Z(s) and RF frequency is located at a pole of Z(s) and CK CK b CK CK b OUT OUT B M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 8 M st r to Se Filter e

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109 Figure 5 20. 2 stage LNA with notch filters at the image frequency. Figure 5 21. Input impedance of the notch filter vs. frequ ency. When the inductor and capacitors are ideal without any loss, at image frequency, the impedance of filter will be zero while at RF frequency the impedance of filt er is open. This will provide infinite image rejection. However, in real circuit, passiv e components have finite Q. The filter impedance | Z(s) | including the resistances of inductor and capacitors is plotted in Figure 5 21. The impedance is not zero at f image and infinite at f RF .. However, the magnitu de of impedance In Out Z Notch filter Notch filter C 1 C 2 L

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110 at f image is still much lower than that at f RF which makes the gain at the image much lower than that at RF. The 2 stage LNA c ombined with notch filters should have image rejection up to 40dB. 5.7 Integration of Transceiver time division duplex (TDD) which means only either the transmitter or receiver is active at a time. This allows the use of one antenna instead of two. This reduces the chip area by ~3mm x 0.12mm. Figure 5 22. Distributed sw itching for the receiver and transmitter. Generally, a T/R switch is required to control the connection between the receiver and transmitter to the antenna. However, it is difficult to implement 24 GHz single pole double throw (SPDT) switches with low ins ertion los s in bulk CMOS processes. For example, switches implemented in a 130 nm CMOS process achieve 1.8 dB insertion loss at 15GHz [89] For a L s L g L d V g2 C 1 C 2 M 2 M 1 Matching Network TxEn C tune PA LNA M tune

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111 switch operating at 24GHz, the insertion loss can easily go above 2.5dB. The switch will degrade the input SNR and increase noise figure of the re ceiver chain. Because of this, instead of using a T/R switch, the switching function is merged into the PA and receiver [90] as s hown in Figure 5 22. In the transmit mode varactor C tune At the same time, TxEn is set high to turn on transistor M tune to short the gate of M1 to ground. This also reduces voltage swing on the gate of M1. The i mpedance looking into the receiver will output to deliver maximum power while protecting the LNA. When the receiver is on, C tune is adjusted to make the PA out put impedance is low to turn off M tune In simulation s th ese in crease the noise figure by 1.3 dB and d ecrease output power of PA by 0.8dB The synthesizer provides the 21.3 GHz LO signals to the receiver and transmitter. To assure sufficient LO drive, four separate buffers are inserted between the synthesizer and each mixer and divider in the receiver and transmitter. These buffers are implemented with tuned amplifiers. Figure 5 23 (A ) shows the frequency synthesizer output to these different buffers. Figure 5 23 (B ) shows the location of these buffers on the chip. Consuming 4 mA DC current from a 1.5 V supply, the frequency syn t hesizer output buffers provide ~0.4V signal to the TX and RX buffer inputs. The 8:1 divider of receiver needs to drive the gate of passive mixer at ~2.7GHz. Instead of using a tuned amplifier which consumes too much area, a n inverter chain is used as 2.7 GHz buffers, as shown in Figure 5 24. The interconnection between the divider output and passive mixer is longer than 1mm and is modeled as a transmission line. A 3 stage tapered buffer at the divider output drives a transmission line and a large buffer th at directly drives the passive mixer.

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112 Figure 5 23 A) Integration of the frequency synthesiz er, transmitter and receiver. B ) LO buffers between receiver, transmitter and frequency synthesizer. PLL RX down conversion mixer RX divider TX up conversion mixer TX divider PLL RX TX _8 buffer buffer buffer buffer LO1 LO1 LO 2 LO2 A B buffer

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113 Fi gure 5 24. Inverter chain is used to drive the passive mixer. 5.8 Summary In this chapter, the key building blocks in a RF receiver implemented in a 130 nm CMOS technology are presented. These blocks are VGA, LPF, frequency divider, passive mixer, LO buf fers and image rejection filter in the LNA. Lastly, a distributed switch has been incorporated into the receiver and transmitter to lower switch loss 8:1 Divider Passive mixer

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114 CHAPTER 6 FULLY INTEGRATED REC EIVER AND WIRELESS L INK DEMONTRATION OF NODE TRANSCEIVER 6.1 Introduct ion Following the successful implementation of individual building blocks the blocks were integrated into a receiver chain. The receiver was also integrated with the transmitter [87] and frequency synthesizer [91] The receiver has been characterized using an external LO source as well as LO provided by the frequency synthesizer. Using the transceiver [93] wireless communication up to 5m has been demonstrated. This co mpletes the goal of demonstrating the feasibility of implementing a transceiver with on chip antennas for general purpose communication. This chapter will first present the measurement results of receiver in section 6.2. The frequency synthesizer is briefl y described and receiver measurement result s with the frequency synthesizer are discussed in section 6.3. Finally, the wireless communication link between the receiver and transmitter that are 5m apart is demonstrated in section 6.4. 6.2 Receiver Measureme nt Using External LO S ource The receiver as well as the transm itter and frequency synthesizer is implemented in the UMC 130 nm logic CMOS. The die micrograph of Node transceiver is shown in Figure 6 1 This 5mm 5mm die also includes a 3mm 3mm baseband processor developed by S. Hwang. The effective receiver area excluding the bonding pads is ~ 3mm 2 Similarly, the effective transmitter area is ~ 1.5mm 0.8mm and the frequency synthesizer is ~ 0.8mm 0.5mm. The o n chip antenna is 3.8mm long and built in metal layers 6 8. A l arge area of p well block is placed underneath the on chip antenna to reduce substrate loss [14] Among 29 pads of the receiver for outputs and bia s, 8 pads are bonded and the rest of the pads are connected using a 21 pin DC probe. Of the 8 wire bonded pads, 4 pads are baseband AC output pads. To drive the 50 spectrum analyzer, 0 dB gain buffers using AD8138 on a

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115 Figure 6 1. Die micrograph of the transceiver and baseband processor. Figure 6 2. Receiver board and die wire bonding. AD8138 Baseband signal I Q

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116 PCB board are added The differential input capacitance of AD8138 is 1 pF. The board also facilitates wire bonding of the transmitter and frequency synthesizer. The receiver board and an enlarged photo illustrating receiver bonding are shown in Figure 6 2. The board is fabricated using FR 4 with dielectric constan t of ~4.5. The board thickness is 60mil. The surface finish is soft bondable gold for the wire bonding. The outputs of baseband I/Q signal are connected to measurement equipment using standard SMA connectors attached to the board. The ground plane is cut out underneath the die to reduce the reflection problem that can degrade the dipole antenna performance. The receiver is first characterized using an external LO signal. The single ended signal output of a signal generator is co nverted to differential by a n off chip balun and then fed as inputs to the drivers for the RF active mixer and divider. This is done using a GSSG probe. Figure 6 3 shows the baseband output when RF input signal frequency f rf is 21.605GHz with 90 dBm available power to the input of the receiver. The antenna is connected to the RF input pads of receiver during the measurements. This shift s down the turned frequency response. LO signal frequency, f LO is 19.2GHz. The baseband signal is suppo sed to be f rf f LO /89 which is 5MHz, as shown in Figure 6 4 This result shows that the receiver has successfully down converted RF input to baseband using dual down conversion. The baseband power is 22.2dBm. The corresponding receiver gain is 67.8dB. (This estimation is based on the assumption that the antenna impedance is the power delivered to the input GSSG pad is evenly divided between the on chip antenna and the receiver. ) When TxEn signal in Figure 5 22 is set to 1.2V, the LNA gate is shunt ed to ground and the baseband signal disappears. The fre quency response is shown in Figure 6 4. RF and LO frequencies are varied to keep the baseband output frequency at 5MHz.The receiver gain peaks between 21.5GHz and 22.5GHz.

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117 Figure 6 3. Receiver baseband signal output spectrum. F igure 6 4. Gain vs. frequency of the receiver with an on chip antenna connected to the RF input pads.

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118 Figure 6 5. Receiver noise floor illustrating the filter characteristic. The baseband LPF freq uency response is characterized by looking at the frequency response of noise floor, as shown in Figure 6 5 This figure spans from DC to 50MHz. There is a dip at DC which shows the high pass filter ing of DC offset cancellation. A 5 MHz baseband signal down converted from RF is also shown. The 3 dB cutoff frequency is ~23MHz. Using an HP8508A vector voltmeter, baseband I/Q signal mismatch is measured. It is found gain mismatch is 1.4dB and phase mismatch is 8.5 Th e main cause could be mismatch between LO lines driving I/Q passive mixers, as shown in Figure 6 1 These lines have quite different shapes even though they have the same leng th. The better way is to route LO lines closely and the n split I/Q lines at a symmetric point which has same distance to I/Q mixers. The power consumption of receiver is summarized in Table 6 1 Total receiver power consumption is 58.9mW. The signal path including LNA, mixer, IF amplifier, baseband amplifier, LPF and output buffer consumes 34.9 mW power while the LO buffers and divider consume 24 mW.

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119 Table 6 1. Power table of the receiver. Receiver blocks V dd (V) Current (mA) Power (mW) LNA 1.5 4 6 Mixer 1.5 3 4.5 LO1 Driver (for mi xer and divider) 1.5 6 9 IF Amp 1.4 11 15.4 LO2 Driver (for p assive mixer) 1.5 7 10.5 Divider 1.5 3 4.5 Baseband 1.5 2 3 Output Buffer 3 2 6 Total 58.9 All the measurements discussed so far are made using receivers with an on chip antenna. To make accurate gain an d NF measurements, on chip antennas on two boards are cut from the receiver. One board shows that when input RF signal is at 21.605GHz with 83.6 dBm power and LO signal is at 19.2GHz, 5 MHz baseband signal power is 11.3dBm which translates to 72.3 dB Rx gain. Then noise performance s charactereized by terminating the external balun at RX input with a 50 The n oise floor at 5 MHz baseband output is 38.2dBm with a 100 kHz spectrum analyz er resolution bandwidth. From these, NF is NF= 38.2 ( 174+72.3+50) = 13.5dB Note this NF number is single side band ( SSB ) NF. The n oise at 5 MHz is contributed by two RF side bands at 21.605GHz and 21.595GHz, respectively. Since signal s will also be present at these two side bands, double side band ( DSB ) NF which is relevant for the system is 10.5dB, or 3dB lower than SSB NF. Figure 6 6 depicts the gain and DSB NF of the receiver on another board as a function of the input frequency, showing a 66.5 dB peak gain and 12.5 dB NF at 21.6GHz. IP 3 is tested using a 19.2 GHz LO signal and two RF input signals at 2 1.605GHz and 21.60502GHz. Figure 6 7 shows the measured IIP 3 is

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120 and no filtering on down 3 limited by last stage. The measured perform ance is summarized in Table 6 2. Figure 6 6. Frequency response of R X gain and NF. Figure 6 7. IP3 measurement of whole R X chain.

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121 Table 6 2. RX performance summary. Circuit metrics Measured res ults Peak gain 72. 3 dB Noise Figure (DSB) 10.5dB IIP 3 (two in band tones) 60dBm Power consumption 58.9mW Technology 130 nm logic CMOS Area 3mm 2 6.3 Receiver Measurement Using On c hip Frequency Synthesizer A fully integrated receiver has also been c haracterized with an on chip frequency synthesizer. The frequency synthesizer is designed by Y. P. Ding and the synthesizer integration was accomplished with her help. Its design has been discussed in [91] A si mple functional description of frequency synthesizer is given here for completeness. Figure 6 8. PLL based frequency synthesizer. Figure 6 8 depicts a block diagram of integer N PLL based frequency synthesizer. A phase and fr equency detector (PFD) compares the phase and frequency difference between the reference signal and frequency divided VCO output. The PFD generates pulses with width proportional to phase difference. The charge pump (CP) senses the pulse width and injects the corresponding amount of current into the loop filter. The loop filter voltage is used to control the Z F (s) K VCO /s N ref (s) + I p /2 PFD and CP Loop Filter VCO Divider out (s) div (s)

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122 VCO and the filter also attenuates the unwanted spurious tones produced by the charge pump. With the PLL locked, VCO output frequency tracks the input reference frequency with a ratio of N:1. N is the divider ratio. For the measurements, N is set to 256. The performance of the frequency synthesizer is summarized in Table 6 3. Table 6 3 Frequency synthesizer performance summary. Circuit metrics Measure d results Prescaler power 6mA @ 1.5V (9mW) VCO power 5mA @ 1.2V(6mW) VCO buffer power 3mA @ 1.2V(3.6mW) PLL output buffer power 10 mA @ 1.2V (12mW) PLL total power 31.8mW VCO tuning range 2.5GHz (13.4%) In band phase noise 65dBc/Hz @ 50kHz Out of b and phase noise 121dBc/Hz @ 20MHz PLL locking range 17.5GHz 19.7GHz Reference spurs 33 37dB below carrier A 16 pin probe is used to provide bias and reference signal to the PLL. The divide ratio of the PLL is 256. With RF input signal at 21.7GHz and P LL reference signal at 75.33MHz, the baseband output signal is at 21.7GHz 75.33MHz256/89=4.96MHz. The baseband spectrum is shown in Figure 6 9. RF input power is 70dBm. Figure 6 10 shows the output spectrum of the baseband signal with a reduced span. Be cause the LO is generated by a synthesizer, the baseband signal shows a similar skirt shape spectrum as the synthesizer output. The measured phase noise of baseband signal is shown in Figure 6 11. This shows that the frequency synthesizer is working proper ly with the receiver. Measuring the phase noise from baseband signal could be an effective way to evaluate the phase noise performance of an integrated frequency synthesizer if there is no other way to access the PLL output. Outside the

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123 Figure 6 9. The output spectrum the RX when the LO is driving from synthesizer. Figure 6 10 The output spectrum of RX when the LO is generated using an on chip synthesizer. The span is reduced to 2MHz to show the skirt. ATTEN 10 dB MKR 12.1 dBm RL 0dBm 10dB/ 4.96M Hz CENTER 4.96MHz SPAN 2. 000MHz *RBW 3.0 kHz *VBW 100Hz SWP 51.98 sec skirt ATTEN 10 dB MKR 13.68 dBm RL 0dBm 10dB/ 4.97M Hz CENTER 5MHz SPAN 10 MHz *RBW 9.1 kHz *VBW 1k Hz SWP 864ms

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124 Figure 6 11. Phase noise of the baseband signal. Figure 6 12. Baseband power versus different VGA gain setting. 10 kHz Frequency Offset 100 MHz Carrier Power 12.6 dBm Atten 1 0 dB Ref 4 0.00dBc/Hz 10.00 dB/ LO loop bandwidth RX LPF cutoff frequency

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125 loop bandwidth of the PLL, the noise floor is determined by input and receiver noise shaped by the low pass filter. Integrating phase noise 64dBc/Hz at 50 kHz offset across two 10MHz bandwidth shows a 9 dB RX SNR. Since system E b /N o requirement is 18dB and data rate and noise bandwidth are 100kHz and 51.2MHz, respectively, system SNR requirement is 9dB. This means that measured RX SNR meets system requirement. Figure 6 12 shows the output power of bandband signal versus the VGA gain setting. The input RF signal is at 21.7GHz with 70dBm av ailable power while the reference for the frequency synthesizer is at 75.33MHz. When the control bits B 0 B 1 B 2 48.7dbm to 16.4dBm. The average gain step is 6.4dB which is close to simulated 6 dB per gain step. 6.4 Wireless Communication Link Demonstration With the receiver and frequency synthesizer working together, it is feasible to demonstrate a wireless communication link between the transmitter and receiver using on chip antennas. The tr ansmitter has been designed and characterized by Changhua Cao [87] Figure 6 13 shows the building blocks in the transceiver. A single tone signal is generated from TX a nd delivered to an on chip antenna by a PA. At 5m away, the receiver picks up the signal and down converts it to baseband. Figure 6 15 shows the setup and environment for wireless link demonstration. The receiver is placed on the probe station in a metal cage. A 5 mm thick glass substrate is attached to the bottom of the receiver board to reduce the effect of metal chuck on the on chip antenna. A 21 pin probe and a 16 pin probe are landed on pads for biasing the re ceiver and PLL. However, these DC pins could affect receiver antenna by disturbing EM field near the antenna. This effect needs to be further investigated. Out side the cage, the transmitter is placed on a cart 5m away. All the

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126 Figure 6 13. Wireless communication link between the transmitter and receiver. Figure 6 14. Transmitter on board and die wirebonding. Header MODULATOR 8:1 divider & Muti Phase BUFFER PLL BUFFER AMP AMP PA On chip TX LNA AMP VGA VGA LPF LPF BUFFER On chip RX 8:1 LO2_Q LO2_I PLL 5m Reference frequency input

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127 Figure 6 15. Wireless link measurement setup and envir onment. Figure 6 16. Receiver output spectrum. ATTEN 10 dB MKR 38.3 dBm RL 0dBm 10dB/ 4.825M Hz CENTER 4.925MHz SPAN 5 MHz *RBW 1 kHz *VBW 1k Hz SWP 6 sec 5m RX Bias PLL Bias Receiver Transmitter TX PLL Bias

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128 bias lines are connected by patch cords to dc sources. The transmitter total power consumption is 128mW Both TX and RX synthesizers work in integer N mode with a divide ratio of 256. With a 75.35 MHz TX reference frequency, transmitter board transmits single tone signal at ~21.7GHz. The frequency was limited by the maximum frequency of synthesizer integrated with the transmitter. A horn antenna with 20 dBi gain located at 3m away from the transmitter picks up ~ 73dBm power. The PLL reference frequency on the receiver side is 75.33MHz. The receiver baseband output is at 4.825MHz with power of 38.30dBm as shown in Figure 6 16. This is the first time a fully integrated CMOS transcei ver pair has established a wireless communication link using on chip antennas. 6.5 Summary A fully integrated 24 GHz CMOS receiver is demonstrated for the first time. One receiver achieves a 72.5 dB peak gain and 10.5 dB NF at 21.6GHz. The whole receiver c onsumes 58.9 mW power. Working with an on chip frequency synthesizer for the first time a wireless communication link has been successfully established between a fully integrated transmitter and a receiver with on chip antennas that are separated by 5m. T he RF portion of Node has been successfully implemented. This is a major step toward the realization of a true single chip radio.

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129 CHAPTER 7 SUMMARY AND FUTURE W ORK 7.1 Summary Imagine a tiny radio only packaged with a battery! The possibility of a s ingle chip radio has become more realistic than ever with the demonstration of a fully integrated 24 GHz CMOS transceiver communicating using on chip antennas. This Ph.D work demonstrated a fully integrated trans ceiver [93] including a receiver, a transmit ter [87] and a synthesizer [91] The receiver chain consists of an LNA, an active mixer, an IF amplifier, a passive mixer, variable gain amplifiers and low pass filt ers for baseband I/Q signals. All the circuits are differential to reduce the impact of switching noise of digital circuits which will eventually be integrated with the transceiver. High frequency LNA design is analyzed in terms of gain and noise figure. S ubstrate resistance has been found to be a critical factor which degrades LNA performance. To reduce this effect, a unique topology using an inductor at the gate of common gate stage in a cascode LNA has been demonstrated to boost the gain while greatly re ducing the power consumption. The 26 GHz LNA only consumes 0.8 mW power while achieving 8 dB gain. A 20 GHz RF front end including an LNA and mixer achieves 9 dB gain and 6.6 dB NF while consuming 12.8 mW power from a 1.5 V supply. Using this front end and an on chip antenna, AM signal transmitted from 5 m away was successfully picked up and down converted to IF frequency. Finally, an entire r eceiver chain is integrated in the UMC 130 nm logic CMOS technology. The receiver achieves 72.5 dB gain and 10.5 dB DSB NF with 58.9 mW power consumption. A 5 m wireless communication link is established using a receiver and a transmitter both working with an on chip frequency synthesize r and an antenna. ~21.7 GHz single tone signal generated by the transmitter is down converted to ~5 MHz using the receiver. This is the first time a wireless link is demonstrated between a pair of fully integrated CMOS

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130 transceivers with on chip antennas. This is a major milestone toward the realization of a single chip radio. Lastly, this work has shown that 24 GHz RF circuits with acceptable performance and power efficiency can be implemented using the 130 nm CMOS. 7.2 Suggested Future Work The work presented in this thesis has shown the feasibility of implementing a single chip radio. To incorporate these circuits into real application s and products, there are still much to do. The list of suggested future works includes: Co design of an on chip antenna and circuits: an on chip antenna. However, its advantage has not been fully exploited. T he antenna, LNA and PA were treated as separate blocks and make each question s are : since now we have the f easibility to control on chip antenna impedance, is 50 optimum option? Even if the impedance change may have deleterious effect on PA output power and LNA NF, is there an optimum matching impedance for the whole wireless link between a transm itter and a receiver? The answer s to these question s will be fundamental contribution s from this work. On chip bias reference generation: As shown in Figure 6 2 to make the receiver, transmitter and frequency synt hesizer work simultaneously, more than 60 DC lines have to be connected from the chips to external DC sources. It takes great effort s to properly connect these wires and it is time consuming. Bias circuits should be incorporated into the chip. Automatic Gain Control (AGC): The gain control in the current version is implemented using a manually controlled variable gain amplifier. To automatically control the gain, two options can be considered. One is to use commonly used AGC which has a power detector to sense the signal amplitude and adjust the gain settings. Another is to use the baseband processor to sense the BER to adjust the gain settings.

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131 Integration with ADC and baseband processor: This is the last major step toward a fully integrated radio. Since the baseband processor designed by Seon Ho Hwang is fully functional, Integration of the RF transceiver with the baseband processor and ADC should be possible in near future. This will indeed be exciting!

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132 APPENDIX DERIVATION OF NOISE FACTOR OF CS LN A Figure A 1 shows 3 noise sources in CS LNA: channel thermal noise induced gate noise and source voltage noise To calculate noise factor of CS LNA, one important step is to calculate correlati on between channel thermal noise and gate induced noise. The detailed derivation is given here. Figure A 1 Noise sources in CS LNA. Noise factor of CS LNA is (A 1) From Eq uation 3 28 and 3 31 we know t hat (A 2) (A 3) Where v n i d C gs i 1 =i n1 +i n2 Z g Z s i i g

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133 Substituting Equation A 2 and A 3 into Equation A 1 the result is (A 4) When LNA input is matched to source impedance where the above equation can be rewritten as (A 5)

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BIOGRAPHICAL SKETCH Yu Su was born in 1974. He received his B.S. degree in 1996 from the Dept. of Electrical an, China. His specialty was semiconduct or device. In 1999, he received his M.S. degree from Tsinghua University From Aug ust 2000 to December 2002, he was with the University of South Florida as a research assistant. Since 2003, he was a Ph.D student in S ilicon Microwave Integrated Circuits and Systems (SIMICS) research group of University of Florida. He has been working on radio frequency CMOS circuit design. He received the Analog Device outstanding student designer award in 2003. From March 2007 to Marc h 20 09, he has been working as a RF IC designer in Texas Instruments, Inc. He received his Ph.D from the University of Florida in May 2009.