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Thick-Gate-Oxide MOS Structures with Sub-Design-Rule Channel Lengths for Digital and Radio Frequency Circuit Applications

Permanent Link: http://ufdc.ufl.edu/UFE0017513/00001

Material Information

Title: Thick-Gate-Oxide MOS Structures with Sub-Design-Rule Channel Lengths for Digital and Radio Frequency Circuit Applications
Physical Description: 1 online resource (137 p.)
Language: english
Creator: Xu, Haifeng
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2007

Subjects

Subjects / Keywords: amplifier, circuit, cmos, digital, frequency, integrated, io, level, oxide, power, radio, receive, shifter, switch, thick, transceiver, transmit, varactor, vco, voltage
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The potential digital and radio frequency (RF) applications and advantages of thick-gate-oxide metal-oxide-semiconductor (MOS) structures with sub-design-rule (SDR) channel lengths in standard complementary MOS (CMOS) technologies are investigated. This is a low-cost solution for scaling down thick-gate-oxide transistors, which does not require any modifications to the existing foundry technologies. This concept provides a new perspective to the down-scaling of thick-gate-oxide transistors. The maximum drain voltage for the drive transistors with a thick-gate oxide of 3.3-to-1.8-V level shift circuits in 0.18-micro m CMOS processes is 1.8 V. The drain current is increased by reducing the gate length to 0.26 from 0.35 micro m. Measurements show the SDR MOS transistor has sufficient drain-to-source breakdown voltage for 1.8-V operation. At the same gate capacitance, the SDR transistor delivers more than 1.6 times the drain current of the conventional thick-gate-oxide transistor. Simulations indicate the propagation delay of 3.3-to-1.8-V level shift circuits can be reduced by 20% without process modifications. Then, for the first time, we proposed a composite MOS transistor structure by combining a 0.12-?m long thin-gate-oxide transistor with a 0.22-micro m long thick-gate-oxide (SDR) transistor in a 0.13-micro m CMOS process. The composite transistor has more than 2 times the drain current of the conventional thick-oxide transistor, while having the same breakdown voltage. 3.3-V I/O transistors with better combination of drive current, threshold voltage and breakdown voltage are realized in conventional CMOS technologies without process modifications. Simulations suggest that 40% reduction in the propagation delay for a 1.2-to-3.3-V level shifter is expected. The concept of SDR transistors can also be used to improve the performance of RF/analog circuits. Measurements show that the composite MOS transistor has higher fT and fmax than the 3.3-V transistor when VGS is below 1.2 V. If the VGS-VT is set to ~ 0.25 V in a practical bias condition for linear power amplifiers, fT of the composite transistor is 15 GHz and 20% higher than that of the 3.3-V transistor. This characteristics can potentially improve RF power amplifier gain and power efficiency. Using 3-stack thick-gate-oxide transistors with a 0.26-?m SDR channel length, a 31.3-dBm 900-MHz bulk CMOS transmit/receive (T/R) switch with insertion losses of 0.5 and 1.0 dB in transmit (TX) and receive (RX) modes has been successfully demonstrated. The effects of feedforward capacitance in the switch are analyzed. Through another 28-dBm T/R switch operating at 2.4 GHz with IL of 0.8/1.2 dB in TX/RX modes, it is demonstrated that 2-stack configuration can be used to trade-off IP1dB for better loss performance. It is suggested that integration of a bulk CMOS T/R switch for cellular applications is a realizable goal by using thick-gate-oxide SDR MOS transistors. Lastly, the use of the SDR MOS structures as varactors in VCO circuits is investigated. This study shows that Qmin of SDR varactors at 24 GHz is 5 times that of thin-gate-oxide structures. The varactor tuning range is decreased from ~ 65% to ~ 40%. Its application for 50-GHz narrow tuning range VCOs with better power consumption and phase noise performance is projected.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Haifeng Xu.
Thesis: Thesis (Ph.D.)--University of Florida, 2007.
Local: Adviser: O, Kenneth K.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2007
System ID: UFE0017513:00001

Permanent Link: http://ufdc.ufl.edu/UFE0017513/00001

Material Information

Title: Thick-Gate-Oxide MOS Structures with Sub-Design-Rule Channel Lengths for Digital and Radio Frequency Circuit Applications
Physical Description: 1 online resource (137 p.)
Language: english
Creator: Xu, Haifeng
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2007

Subjects

Subjects / Keywords: amplifier, circuit, cmos, digital, frequency, integrated, io, level, oxide, power, radio, receive, shifter, switch, thick, transceiver, transmit, varactor, vco, voltage
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The potential digital and radio frequency (RF) applications and advantages of thick-gate-oxide metal-oxide-semiconductor (MOS) structures with sub-design-rule (SDR) channel lengths in standard complementary MOS (CMOS) technologies are investigated. This is a low-cost solution for scaling down thick-gate-oxide transistors, which does not require any modifications to the existing foundry technologies. This concept provides a new perspective to the down-scaling of thick-gate-oxide transistors. The maximum drain voltage for the drive transistors with a thick-gate oxide of 3.3-to-1.8-V level shift circuits in 0.18-micro m CMOS processes is 1.8 V. The drain current is increased by reducing the gate length to 0.26 from 0.35 micro m. Measurements show the SDR MOS transistor has sufficient drain-to-source breakdown voltage for 1.8-V operation. At the same gate capacitance, the SDR transistor delivers more than 1.6 times the drain current of the conventional thick-gate-oxide transistor. Simulations indicate the propagation delay of 3.3-to-1.8-V level shift circuits can be reduced by 20% without process modifications. Then, for the first time, we proposed a composite MOS transistor structure by combining a 0.12-?m long thin-gate-oxide transistor with a 0.22-micro m long thick-gate-oxide (SDR) transistor in a 0.13-micro m CMOS process. The composite transistor has more than 2 times the drain current of the conventional thick-oxide transistor, while having the same breakdown voltage. 3.3-V I/O transistors with better combination of drive current, threshold voltage and breakdown voltage are realized in conventional CMOS technologies without process modifications. Simulations suggest that 40% reduction in the propagation delay for a 1.2-to-3.3-V level shifter is expected. The concept of SDR transistors can also be used to improve the performance of RF/analog circuits. Measurements show that the composite MOS transistor has higher fT and fmax than the 3.3-V transistor when VGS is below 1.2 V. If the VGS-VT is set to ~ 0.25 V in a practical bias condition for linear power amplifiers, fT of the composite transistor is 15 GHz and 20% higher than that of the 3.3-V transistor. This characteristics can potentially improve RF power amplifier gain and power efficiency. Using 3-stack thick-gate-oxide transistors with a 0.26-?m SDR channel length, a 31.3-dBm 900-MHz bulk CMOS transmit/receive (T/R) switch with insertion losses of 0.5 and 1.0 dB in transmit (TX) and receive (RX) modes has been successfully demonstrated. The effects of feedforward capacitance in the switch are analyzed. Through another 28-dBm T/R switch operating at 2.4 GHz with IL of 0.8/1.2 dB in TX/RX modes, it is demonstrated that 2-stack configuration can be used to trade-off IP1dB for better loss performance. It is suggested that integration of a bulk CMOS T/R switch for cellular applications is a realizable goal by using thick-gate-oxide SDR MOS transistors. Lastly, the use of the SDR MOS structures as varactors in VCO circuits is investigated. This study shows that Qmin of SDR varactors at 24 GHz is 5 times that of thin-gate-oxide structures. The varactor tuning range is decreased from ~ 65% to ~ 40%. Its application for 50-GHz narrow tuning range VCOs with better power consumption and phase noise performance is projected.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Haifeng Xu.
Thesis: Thesis (Ph.D.)--University of Florida, 2007.
Local: Adviser: O, Kenneth K.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2007
System ID: UFE0017513:00001


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THICK-GATE-OXIDE MOS STRUCTURES
WITH SUB-DESIGN-RULE CHANNEL LENGTHS
FOR DIGITAL AND RADIO FREQUENCY CIRCUIT APPLICATIONS

















By

HAIFENG XU


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY


UNIVERSITY OF FLORIDA


2007






























@ 2007 Haifeng Xu
































To my parents and my wife









ACKNOWLEDGMENTS


I want to express my deep gratitude and appreciation to my advisor, Professor Kenneth K.

O, for his patient, constant encouragement and devotion. He guided me through the transition

from a student to an electrical engineer. Under his supervision, I had opportunities to work in

microelectronics, which eventually became a joy for me. Also much appreciation goes to Profes-

sor Rizwan Bashirullah, Professor Huikai Xie and Professor Oscar D. Crisalle for their helpful

suggestions to my research. I would like to thank them for their interests in this work and serving

on my Ph.D. supervisory committee.

I would like to thank all the former and current colleagues in the SiMICS research group

for their helpful discussions, advice and friendship. Some names are listed here: Chikuang Yu,

Xiaoling Guo, Brian Floyd, Chih-Ming Hung, Feng-Jung Huang, Kihong Kim, Yochuol Ho,

Namkyu Park, Xi Li, Zhenbiao Li, Seong-Mo Yim, Dong-Jun Yang, Narasimhan Trichy Raj ago-

pal, Ran Li, Tod Dickson, Jason Branch, James Caserta, Wayne Bomstad, Jose Bohorquez,

Aravind Sugavanam, Jie Chen, Jau-Jr Lin, Li Gao, Changhua Cao, Yanping Ding, Yu Su,

Eun-Young Seok, Kwang-Chun Jung, Swaminathan Sankaran, Hsin-ta Wu, Chuying Mao, Ning

Zhang, Seon-Ho Hwang, Nallani Shashank Kiron, Myoung Hwan Hwang, Zhe Wang, Wuttichai

Lerdsitsomboon, Dongha Shim, and Kyujin Oh.

Finally, I am grateful to my parents, my sister and her family. At last, but not least, I want

to thank my wife for her love, patience, encouragement and tolerance. She has been beside me

every single day, bright or dark. I can not imagine walking through all these days without her

companionship.










TABLE OF CONTENTS


I W Le


ACKNOWLEDGMENTS ...

LIST OF TABLES ......

LIST OF FIGURES ....... .


.. 9


ABSTRACT .......................

CHAPTER

1 INTRODUCTION .......... .......

1.1 CMOS Technology .......... ....
1.1.1 History of CMOS Transistors ......
1.1.2 From Digital to Analog .........
1.2 Transistor Scaling ................
1.2.1 Transistor Scaling Guidelines ......
1.2.2 Issues for Transistor Scaling .......
1.3 Thick-Gate-Oxide MOS Transistor .........
1.4 Motivation ...................
1.5 Methodology ..................
1.6 Overview of the Dissertation ............

2 HIGH-TO-LOW LEVEL SHIFTER APPLICATION. .. .. .

2.1 Introduction .............. ... .. ..
2.2 Sub-Design-Rule (SDR) MOS Transistor Structure
2.3 DC Characteristics of SDR MOS Transistors .. .. .
2.3.1 Current Drive Capability . .
2.3.2 Voltage Handling Capability .. .. .. .


............ .. .. .30

....................30
....... .. .. .. .. .. .32
............ .. .. .34
............ .. .. .34
..... . .. .. .37


2.3.3 Optimization of MOS Transistors for Level Shifter Application
2.4 Capacitance Property of SDR-26 MOS Transistor ..........
2.5 High-to-low Level Shifter Speed Performance .......... .
2.6 Summary.

3 LOW-TO-HIGH LEVEL SHIFTER APPLICATION. ...._ .

3.1 Introduction ......_ ...._ _.....
3.2 Composite MOS Transistor Structure ................
3.3 Composite MOS Transistors in a 0.18-Cim Process .........
3.3.1 Current and Breakdown Characteristics ..........
3.3.2 Subthreshold Current Leakage Issues ............
3.4 Composite MOS Transistors in a 0.13-Cim Process ....._ .


S 49










3.4.1 Current Characteristics ....._ ....__
3.4.2 Voltage Handling Capability ....._ .....
3.5 Composite MOS Transistor Capacitance Property ......_ _
3.6 Composite-22 MOS Transistors for Level Shifter Application .....
3.7 Low-to-high Level Shifter Speed Performance ..........
3.8 Summary ............................

4 RADIO FREQUENCY POWER AMPLIFIER APPLICATION . .

4.1 Introduction ............. ........... ... ...
4.1.1 CMOS RF Power Amplifiers. ......... .. .
4.1.2 Classification of CMOS RF Power Amplifiers .. .. . .
4.1.3 Thick-Gate-Oxide MOS Transistors in Linear Power Amplifiers.
4.2 AC Characteristics of Composite-22 MOS Transistor . ..
4.2.1 fT and fmax .......... ......... ..
4.2.2 Measurements for fT and fmax .......... -...
4.3 Summary ............................

5 TRANSMIT/RECEIVE SWITCH APPLICATION. .......... ..

5.1 Introduction ..........................
5.1.1 CMOS Transmit/Receive Switches .......... ..
5.1.2 Techniques to Improve Power Handling Capability ......
5.2 CMOS T/R Switches Using Sub-Design-Rule Transistors .......
5.2.1 Design of SDR T/R Switches.
5.2.2 900-MHz SDR T/R Switch ................
5.2.3 2.4-GHz SDR T/R Switch ........_.....
5.3 Discussion ........ ........ ......
5.4 Summary ........ ........ ....._


.. .. .76

......76
.. .. .76
.. .. .77
.. .. .78
.. .. .79


6 HIGH-Q MOS VARACTOR APPLICATION . .

6.1 Introduction .......... .........
6.1.1 CMOS Voltage-Controlled Oscillator ......
6.1.2 MOS Varactors ...............
6.1.3 Sub-Design-Rule MOS Varactors .......
6.2 High Frequency Characteristics of SDR MOS Varactors ..
6.2.1 Device Structure .......... ...
6.2.2 Measurements and Discussions ........
6.3 Summary ......................

7 SUMMARY AND SUGGESTION FOR FUTURE WORK ....

7.1 Summary ......................
7.2 Suggestion for Future Work. ..............
7.2.1 Application in high power T/R switches .....
7.2.2 Application in high-Q varactors ......_


.......111












APPENDIX MODEL FILE FOR SDR-26 MOS TRANSISTORS . . .. 129


LIST OF REFERENCES ......__ .. . .... .. 130


BIOGRAPHICAL SKETCH ......__ .. . .. .. .. 137










LIST OF TABLES


Table Pagg

1-1 Scaling strategies for CMOS transistors ......... .. . .. 21

1-2 Two types of transistors available in a standard CMOS technology .. .. .. .. . .. 25

2-1 Breakdown voltages of sub-design-rule MOS transistors ... .. . 37

2-2 Speed performance of level shifters using the SDR-26 and conventional 3.3-V MOS
transistors as the drive transistors ......... . .. .. 47


3-1 Breakdown voltages and threshold voltages for the composite-18, and the conventional
3.3-V and 1.8-V MOS transistors ......... . .. .. 55


3-2 Measured threshold voltages of the composite transistors, and the conventional 1.2-V,
3.3-V transistors .......... . ...... ... . .. 62


3-3 Breakdown voltages for the composite transistors, and the conventional 3.3-V and 1.2-V
transistors ............. .......... ......... .....64


3-4 Speed performance comparison of level shifters using the composite-22 and convention-
al 3.3-V MOS transistors ...._ . ._ ... .. 74


5-1 Performance summary of CMOS T/R switches. . ... ... .. 105










LIST OF FIGURES


Eiutre Dante

1-1 First MOSFET structure proposed in 1928 from Lilienfeld's US patent application.. .. 16

1-2 Illustration of MOSFET scaling proposed in Dennard's paper. .. .. .. . .. 17

1-3 Typical floorplan for the mixed-signal system design. . ... . .. 19

1-4 Scaling parameters in CMOS transistors. ......... . . .. 20

2-1 Low-to-high and high-to-low level shifters (LS) used as the interface circuits along the
paths between the circuits with different signaling levels. ..... .. .. .. .. 30

2-2 Typical high-to-low level shifter, using 3.3-V drive transistors at the interface between
3.3-V and 1.8-V circuitries. .......... . ..... . .. 31

2-3 Cross-section of the sub-design-rule (SDR) MOS structure.. ... .. .. . .. 33

2-4 Test structure layout of a set of SDR MOS transistors for DC measurements.. .. .. .. 34

2-5 Normalized ID-VGS for different SDR MOS transistors at VDS = 1.8 V. .. .. .. .. 35

2-6 Measured threshold voltages of SDR MOS transistors with different channel lengths. 36

2-7 Comparison of normalized ID-VDS between SDR-26 and conventional 3.3-V MOS
transistors. ............. ..........................39

2-8 Comparison of normalize ID-VGS between SDR-26 and conventional 3.3-V MOS
transistors in both linear and logarithm scales, when VDS = 1.8 and 0.05 V. .. .. .. .. 40

2-9 Simulated gate capacitance of longer channel 3.3-V MOS transistors, and extrapolated
gate capacitance of SDR-26 MOS transistors.. ......... .. . .. 42

2-10 Simulated ID-VDS and ID-VGS curves of the SDR-26 and 3.3-V MOS transistors. The
simulations also match the measured currents for both types of transistors.. .. .. .. .. 43

2-11 Schematics of level shifter circuits in simulation. Version A uses conventional MOS
transistors as drive transistors, while Version B uses SDR-26 MOS transistors. .. .. .. 44

2-12 Comparison of the SDR-26 and conventional 3.3-V MOS transistors used as the drive
transistors in 3.3-to-1.8-V level shifters. ......... .. . .. 46

3-1 Typical low-to-high level shifter, using thick-gate-oxide drive transistors at the interface
between low-VDD and high-VDD circuitries.. .......... .. .. .. . .. 49










3-2 Layout of the composite MOS transistor. Only 2 cells are shown here. .. .. .. .. .. .. 51

3-3 Cross-section of the composite MOS transistor. ........ .... . .. 52

3-4 Equivalent schematics of the composite MOS transistor. ... .. . 53

3-5 Test structure layout of the composite-18, conventional 3.3-V thick-oxide and
conventional 1.8-V thin-oxide MOS transistors for DC measurements.. .. .. .. .. .. 54

3-6 Normalized ID-VDS of the composite-18, conventional 3.3-V thick-oxide and
conventional 1.8-V thin-oxide MOS transistors.. ......... .. . .. 55

3-7 ID-VGS curves in a logarithm scale for the composite-18, conventional 3.3-V and 1.8-V
MOS transistors with VDS = 0.05 V and VDD (1.8/3.3 V). .... .. .. .. .. 56

3-8 Illustration of source current matching between (A) the composite-18 transistors and (B)
the conventional 1.8-V MOS transistors.. ......... . . .. 57

3-9 Calculation of the voltage at the shared diffusion region (VM(a)) by using source current
matching. ............. .......... ......... .....59

3-10 Test structure layout of a group of the composite MOS transistors for DC measurements. 61

3-11 Normalized ID-VGS plots for the composite and the conventional 3.3-V transistors with
VDS = 3.3 V, and the conventional 1.2-V transistor with VDS =1.2 V... .. .. .. .. .. 62

3-12 Layout of the AC test structures for the composite MOS transistor and the open
structure........ .......66.......

3-13 Measured gate capacitance of the composite transistors with different lengths of SDR
sub-transistors, compared to those of the conventional 1.2-V and 3.3-V transistors. .. 67

3-14 ID-VDS characteristics of the composite-22, conventional 3.3-V and 1.2-V MOS
transistors when gate capacitances (C g) are the same. . ... . .. 69

3-15 Comparison of ID-VGS curves for the composite-22 and conventional 3.3-V MOS
transistors in linear and logarithm scales at fixed gate capacitance. .. .. .. ._. 70

3-16 Schematics of level shifter circuits in simulation. . .... ... .. 72

3-17 Comparison of the composite-22 and conventional 3.3-V MOS transistors used in 3.3-
to-1.8-V level shifters. ......... .......... ... . .73

4-1 Simplified block diagram of a typical RF transceiver. . .._ .. .. 76

4-2 Small-signal lumped microwave network model of a MOSFET. . . 79










4-3 Measured current gain (h21), maximum available gain (MAG) and unilateral power gain
(Gmax) for the composite-22 and conventional 3.3-V thick-gate-oxide transistors. .. 83

4-4 fT and fmax for the composite-22 MOS transistor and conventional 3.3-V thick-gate-
oxide transistors. ......... .......... . .. 84


4-5 gm, output resistance (ro) and intrinsic gain of the composite-22 and conventional 3.3-
V/1.2-V transistors when the overdrives (VGS-VT) are around 0.25 V. .. .. .. .. .. .. 85

5-1 T/R switch in a typical TDD RF transceiver.. ......... .. .. . .. 87

5-2 Simplified schematic of the T/R switch with 3-stack sub-design-rule (SDR) length
transistors. ............. ..........................92

5-3 Cross-section of the 3-stack transistors in the SDR T/R switch. ... .. .. .. .. 93

5-4 Detailed schematic of the 3 -stack transistors (M 1-M3) including the parasitic shunt
paths. ............. .......... ......... .......94

5-5 Voltage distributions for the 3-stack SDR switches with and without the feed-forward
capacitors, when the input power is 30 dBm. ......... .. .. . .. 95

5-6 Impact of feed-forward capacitance (OX, lX, 2X and 3X) on the peak voltages across
transistors M1-M3 (VDGl?~V DG3P VSGl?~VSG3P).. . . . 97

5-7 Die photo of the 3-stack SDR T/R switch.. ......... .. . .. 99

5-8 Measured insertion loss of the SDR switch using 3 stack SDR transistors, compared to
that of the switch using 2 stack 0.34-mm length transistors.. ... .. .. . .. 100

5-9 Measured isolation and return loss for the SDR T/R switch using 3 stack SDR channel
length transistors. ......... .......... .. . .. 100

5-10 Linearity measurement results of the 3-stack SDR switch with source/drain biased at 3
and 0 V, and with (lX) and without the feed-forward capacitors.. .. . .. 101

5-11 Simplified schematic of the T/R switch for 2.4-GHz applications using 2-stack SDR
transistors without feed-forward capacitors. ......... .. .. .. . .. 102

5-12 Die photo of the T/R switch for 2.4-GHz applications using 2-stack SDR transistors
without feed-forward capacitors. ......... . .. .. 103

5-13 Measured insertion loss and isolation of the 2-stack SDR switch for 2.4-GHz
applications. ......... .......... . . .. 104

5-14 IPldB measurement of the 2-stack SDR switch working at 2.4 GHz. .. .. .. .. .. .. 104










5-15 Detail of linearity measurement results around 1-dB compression point for the 3-stack
SDR switch. ............. ............. ......... 106


5-16 Measured DC current through the n-p-n-p sandwich structure from source/drain,
through body to p-substrate_ .......... . .... . .. 107

5-17 Measured breakdown characteristics of a single SDR transistor. .. .. .. . .. 108

6-1 Schematic of a typical differential CMOS voltage-controlled oscillator. .. .. .. .. 1 12

6-2 Cross-section of MOS varactor structures. ......... .. . .. 113


6-3 Layout and equivalent circuit model of a MOS varactor. .... .. .. .. .. .. 1 17

6-4 C-V and Q-V characteristics of the thick-gate-oxide (TK) and thin-gate-oxide (TN)
varactors with L= 0.24 Clm.. .......... . ..... . .. 119

6-5 Measurement data of Qmin and y vs channel length for thick-gate-oxide (TK) and thin-
gate-oxide (TN) varactors. ......... . ...... .. . .119

6-6 Varactor design space formed by Qmin and tuning range y. ..... .. .. . .. 121

7-1 Additional nodes to connect feedforward capacitors in a 4-transistor stack of SDR T/R
switches....... ....... 127........


7-2 Spacing between poly gate and diffusion connections in MOS varactor structures.. .. 128









Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

THICK-GATE-OXIDE MOS STRUCTURES
WITH SUB-DESIGN-RULE CHANNEL LENGTHS
FOR DIGITAL AND RADIO FREQUENCY CIRCUIT APPLICATIONS

By

Haifeng Xu

August 2007

Chair: Kenneth K. O
Maj or: Electrical and Computer Engineering

The potential digital and radio frequency (RF) applications and advantages of

thick-gate-oxide metal-oxide-semiconductor (MOS) structures with sub-design-rule (SDR) chan-

nel lengths in standard complementary MOS (CMOS) technologies are investigated. This is a

low-cost solution for scaling down thick-gate-oxide transistors, which does not require any modi-

fications to the existing foundry technologies. This concept provides a new perspective to the

down-scaling of thick-gate-oxide transistors.

The maximum drain voltage for the drive transistors with a thick-gate oxide of

3.3-to-1.8-V level shift circuits in 0. 18-Clm CMOS processes is 1.8 V. The drain current is

increased by reducing the gate length to 0.26 from 0.35 Clm. Measurements show the SDR MOS

transistor has sufficient drain-to-source breakdown voltage for 1.8-V operation. At the same gate

capacitance, the SDR transistor delivers more than 1.6 times the drain current of the conventional

thick-gate-oxide transistor. Simulations indicate the propagation delay of 3.3-to-1.8-V level shift

circuits can be reduced by 20% without process modifications. Then, for the first time, we pro-

posed a composite MOS transistor structure by combining a 0.12-Clm long thin-gate-oxide transis-

tor with a 0.22-Clm long thick-gate-oxide (SDR) transistor in a 0. 13-Clm CMOS process. The









composite transistor has more than 2 times the drain current of the conventional thick-oxide tran-

sistor, while having the same breakdown voltage. 3.3-V I/O transistors with better combination of

drive current, threshold voltage and breakdown voltage are realized in conventional CMOS tech-

nologies without process modifications. Simulations suggest that 40% reduction in the propaga-

tion delay for a 1.2-to-3.3-V level shifter is expected.

The concept of SDR transistors can also be used to improve the performance of RF/analog

circuits. Measurements show that the composite MOS transistor has higher fT and fmax than the

3.3-V transistor when VGS is below 1.2 V. If the VGS-VT is set to ~ 0.25 V in a practical bias con-

dition for linear power amplifiers, fT of the composite transistor is 15 GHz and 20% higher than

that of the 3.3-V transistor. This characteristics can potentially improve RF power amplifier gain

and power efficiency.

Using 3-stack thick-gate-oxide transistors with a 0.26-Clm SDR channel length, a

31.3-dBm 900-MHz bulk CMOS transmit/receive (T/R) switch with insertion losses of 0.5 and

1.0 dB in transmit (TX) and receive (RX) modes has been successfully demonstrated. The effects

of feedforward capacitance in the switch are analyzed. Through another 28-dBm T/R switch oper-

ating at 2.4 GHz with IL of 0.8/1.2 dB in TX/RX modes, it is demonstrated that 2-stack configu-

ration can be used to trade-off IPldB for better loss performance. It is suggested that integration of

a bulk CMOS T/R switch for cellular applications is a realizable goal by using thick-gate-oxide

SDR MOS transistors. Lastly, the use of the SDR MOS structures as varactors in VCO circuits is

investigated. This study shows that Qmin of SDR varactors at 24 GHz is 5 times that of

thin-gate-oxide structures. The varactor tuning range (y) is decreased from ~ 65% to ~ 40%. Its

application for 50-GHz narrow tuning range VCOs with better power consumption and phase

noise performance is proj ected.









CHAPTER 1
INTTRODUCTION

Thick-gate-oxide metal-oxide-semiconductor (MOS) transistors in addition to

thin-gate-oxide high performance MOS transistors are commonly used in standard complemen-

tary MOS (CMOS) processes. Their high breakdown voltage and low off-current are preferred in

many applications. This study is interested in further scaling down the thick-gate-oxide MOS

transistors and exploiting this further scaled devices in both digital and analog circuit designs.

Since this study is related to scaling, the evolution and development trend of CMOS tech-

nology is an excellent place to start with.

1.1 CMOS Technology

1.1.1 History of CMOS Transistors

The concept of MOSFETs (metal-oxide-semiconductor field-effect transistors) was first

proposed as early as 1928 by Julius Edgar Lilienfeld in his US patent (Figure 1-1) [Lil28]. The

conductivity between the S node (source) and D node (drain) can be modulated by the transverse

electric field applied through the G (gate). Unfortunately, this idea did not become practical until

1958 when the thermally grown oxide were developed by Atalla to reduce the surface state den-

sity and solve the electrical instability of the MOS transistors [Ata59].

Building on these and others, Kahng and Atalla successfully developed the first modern

MOSFET in 1960. Their structure was very similar to that of modern MOS transistors, and con-

sisted of a thermally grown gate-oxide layer over an n-type inversion channel between two n /p

junctions on a p-type silicon substrate [Kah60, Kah76]. About the same time, Kilby and Noyce

separately invented the monolithic integrated circuit (IC) concept [Kil76, Noy61]. This technol-















AI2033------




AII




I


Figure 1-1. First MOSFET structure proposed in 1928 from Lilienfeld's US patent
application.

ogy laid the foundation for the development of ICs, initially using BJTs (bipolar junction transis-

tors), then using MOSFETs [Sah88].

A maj or breakthrough in IC technology occurred when a CMOS (complementary

metal-oxide-semiconductor) inverter circuit was invented by Frank Wanlass and Chih-Tang Sah

in 1963 [Wanl63]. In CMOS technology, both n-type and p-type MOSFETs are fabricated in the

same silicon chip, and the circuits using CMOS logic has almost zero static power consumption.

CMOS integrated circuits became successful in many then-advanced electronic products because

of low overall power consumption and prolonged battery life time. In 1968, Noyce and Moore

started a MOS integrated circuit manufacturing company (Intel), leading to volume production in

1970. A new era of CMOS integrated circuit production has been opened.

Probably one of the most influential techniques on MOSFET design was proposed by

Dennard and co-researchers around 1973 [Den74]. They presented the way to reduce the transis-


Cu2S
S












GATE t~foO 00A GATE 9 t*2ool L' = L/k
N+ F1 + tox ,o/k
N+ IIVds'= Vds/k
_IjL ~C--L: N A '=kNA
-- 7 L k = 5




A B

Figure 1-2. Illustration of MOSFET scaling proposed in Dennard's paper. (A)
State-of-the-art MOSFET structure. (B) Down-scaled MOSFET structure
following the scaling law.



tor dimensions without compromising the current-voltage characteristics. This has been known as

the scaling law of MOSFETs (illustrated in Figure 1-2). Compared to bipolar devices, CMOS

transistors are relatively easy to fabricate. The ability to scale makes CMOS technology even

more attractive. Engineers and researchers have been able to scale down the feature size and push

CMOS technology forward. The channel length of MOSFETs has decreased from several micron

meters in Dennard's time, to submicron, and to nano-meters nowadays.

Since its first use in commercial products, CMOS technology has been growing very fast.

Just tracing back to year 1982, for example, integrated circuits manufactured using CMOS pro-

cesses were only 12% of the market including BJT, BiCMOS, NMOS, PMOS, TTL and other

technologies. However, this percentage almost reversed by the year 2003. The share of CMOS

technology jumped to 82% [Vee03]. Considering the fact that the whole IC market had increased

from $10.2B to $175B during the same period, the growth of CMOS technologies is indeed amaz-

mng.









1.1.2 From Digital to Analog

Scaling is one remarkable feature of CMOS technology. When the dimensions are

reduced, MOS transistors can achieve higher speed performance due to lower capacitance, lower

supply voltage and higher drive current. By reducing the transistor size, more functions can be

integrated in the same chip area, and the cost of the same functionality is decreased. Additionally,

CMOS gates have low power consumption. Power is dissipated only during switching of the cir-

cuit. This allows hundreds of millions of CMOS transistors to be integrated on a single silicon

chip before the heat management becomes problematic. CMOS technology is the dominant one in

VLSI production today, and its advance will remain the primary driving force for the IC industry.

RF (radio frequency) and analog circuits were traditionally fabricated using bipolar tran-

sistors due to its higher transconductance, better matching, lower noise and higher speed. Mean-

while MOS transistors have been steadily scaled down and this has improved the speed of MOS

transistors. As a matter of fact, the intrinsic speed of MOS transistors has been increased by more

than three orders of magnitude in the past 30 years and becomes comparable to that of bipolar

counterparts. This has enabled use of CMOS technology for RF applications. With the modest

transistor performance, CMOS technology has the advantage that both analog and complex digital

circuits can be inexpensively integrated into the same silicon chip. Analog/mixed signal CMOS

circuit design is under rapid development, including RF applications [HuaQ98, Abi04]. It is the

clear trend today to use CMOS digital circuits combined with CMOS analog circuits whenever

possible because of the higher level of integration and low cost, thus providing highly reliable

SoC (system-on-chip) solutions, as illustrated in Figure 1-3 [Sin99].











0000000000
Low amplitude
Analogue circuits Medium amplitude [
O I I analogue circuits

O II ~High amplitude [
O II ~analogue circuits '

O II -\p+ Guard Ring [
O ~High speed 1
Lo s~gpee~du digital circuits I
DI II~igitearloutputll [




Figure 1-3. Typical floorplan for the mixed-signal system design.


1.2 Transistor Scaling

1.2.1 Transistor Scaling Guidelines

CMOS technology evolution has followed the path of scaling down for pursuing higher

speed, higher integration, lower power consumption and lower cost. However, the progress of

scaling is not arbitrary even if allowed by the lithography. The short channel effect (SCE) which

leads to the decrease of the threshold voltage is an undesirable aspect of scaling and should be

controlled with the help of advancement in device design and process technology. Therefore, cer-

tain design guidelines are always followed. There are two methods often mentioned:

+constant-field scaling
+ constant-voltage scaling

In the first scaling scenario, both horizontal and vertical dimensions in Figure 1-4, such as

channel length L, width W, gate thickness tox, junction depth Xj, etc., are proportionally scaled

down by a factor of k. At the same time, it is required to decrease the applied voltage (VDD) and
















Sn+ source -----zn ri

dm WD I




p-substrate, NA


Figure 1-4. Scaling parameters in CMOS transistors.

increase the doping concentration (NA or ND) by the same factor. The maximum drain depletion

width (WD in Figure 1-4), given by


2ssif Ybi + VDD) 2ssiVDD JDD 1
W oc ac (1-1)
D qN NA k '


is also scaled down approximately by k. The key point in this scenario is that the electric field (5)

remains unchanged by the scaling, so that the reliability of scaled CMOS transistors is no worse

than that of the original device. This concept is illustrated in Figure 1-2 and the scaling rules for

device and circuit parameters are specified in Table 1-1.

For the constant-field scaling, the drift current (ID) decreases by a factor k. Interestingly,

the circuit delay (z ~ CVDD 1D) is still improved by k because the capacitance (C ~ WL/tox) and

the voltage are scaled down by a factor of k2 in total. Moreover the power density (~ P/WL) is

kept the same. This means that, by following the constant-field scaling, the circuits can speed up

by the same factor while maintaining the power density of the silicon chip.










Table 1-1. Scaling strategies for CMOS transistors


constant-5
scaling factor
(k>1)
1/k
k
1/k
1
1/k
1/k
1/k
1
1
1/k
1/k2
k2
1


constant-V
scaling factor
(k>1)
1/k
k2
1
k
1/k
1/k
k
k2
1/k
1/k2
k
k2
k3


generalized
scaling factor
(1 1/k
ak
alk
a
1/k
1/k
a2/k
2


1/uk

a3/k2
k2
3


Param eters


Dimension (L,W, tox, Xj, etc.)
Doping concentration (NA, ND)
Voltage (VDD)
&-field (~ VDDox,)

Depletion-layer width (Wd)
Capacitance (C ~ WL/tox)
Drift current (ID ~ WDD2/Ltox)
Drift current per width (~ ID/W)
Channel resistance (Ron ~ VDD ID)
Circuit delay (z ~ CVDD ID)
Power per circuit (P ~ VDD D)
Circuit density (~ 1/WL)
Power density (~ P/WL)


Under the second scaling scheme (constant-voltage scaling), the MOS transistor's hori-

zontal and vertical dimensions again are scaled down by k. Different from the last scenario, the

applied voltage in this case remains the same, thus the electric field has to be increased by k. The

maximum channel depletion width (Wdm in Figure 1-4) is expressed as


4ssikTln(Na/ni) 4ssikT(const) 11
Wdm 2 2 oc -ck
q NA q NA N


(1-2)


To assure that the maximum channel depletion width (Wdm) and the maximum drain depletion

width (WD) in Equation 1-1 are scaled down by factor of k, the doping concentration (NA or ND)









should be increased by k2. The constant-voltage scaling rules for device and circuit parameters are

also listed in Table 1-1.

Under the constant-voltage strategy, the drift current is increased by k. Consequently, the

circuit delay is improved even faster (by k2). However, the benefit is countered by the drastic

increase of power density by a factor of k3. Even worse, scaling up electric field may cause

hot-carrier and oxide reliability problems in the scaled MOS transistors.

The constant-field scaling is a clear and simple approach to the design of scaled MOS

transistors. However, the requirement of reducing the voltage by the same factor as the device

physical dimension is too conservative. Because of certain non-scalable effects and reluctance to

depart from the standardized voltage levels of the previous generations, the supply voltage is sel-

dom scaled in proportion to the channel length. Actually, the electric field has been gradually ris-

ing over the generations rather than staying constant [Cha01]. On the other hand, the

constant-voltage scaling scheme puts a very loose constraint on the electric field and allows it to

increase by the same factor as the dimensions are scaled down. The performance can be improved

fast. However, the MOS transistor is no longer reliable and the circuit heating becomes unman-

ageable.

In reality, CMOS technology development has followed the steps between the con-

stant-field scaling and the constant-voltage scaling. This mixed scaling method is expressed as the

generalized scaling in Table 1-1. When the device dimensions are reduced by k, the electric field

is allowed to scale up by a smaller factor a (1
power density are scaled to a/k (< 1) and a3 (< k3), respectively. The generalized scaling can

relieve the reliability problems and alleviate the severeness of the package heat removal problem.









1.2.2 Issues for Transistor Scaling

Even though the CMOS scaling guidelines discussed above have served the industry well,

there are some non-scalable effects that are not taken into account and make the scaling guidelines

impractical sometimes.

To keep improving the speed performance of MOS transistors, an important assumption

implicitly used is that the threshold voltage (VT) can be always scaled down together with the

supply voltage (VDD) so that sufficient VDD/VT ratio is maintained. However, the off current (lowf)

will exponentially increase when the threshold voltage VT is scale down, as given by


W ..fkm2 _(qVT) (mkT)
loff = uoCox(m 1)I --I e (1-3)


where m is 1 + ox representing the efficiency that the gate controls the inversion layer. Funda-
W,
kT
mentally, the thermal voltage is non-scalable with the process parameters. The off current

(logf), therefore, will increase beyond the reasonable limit if there is no compromise in VDD VT

ratio, i.e., slowing down the scaling of threshold voltage.

The off current directly contributes to the static power consumption of the chip. Even

though the latter is only a small fraction of the total power dissipation nowadays, it is expected to

become more problematic for future technologies when the CMOS technology is further scaled

down and the number of transistors per chip is increased.

Over the last decade, many techniques have been reported to reduce the static power dissi-

pation in VLSI. Among those, the multi-threshold CMOS transistor and variable threshold CMOS

transistor are promising techniques to reduce the static power while maintaining high perfor-

mance in active mode [McP00, YamTOO]. The basic idea is to use lower-VT MOS transistors

along the critical signal paths for high speed and higher-VT~ MOS transistor in the non-critical por-









tion of the same chip without affecting the high performance portion. For one CMOS process,

these types of transistors with different threshold voltages can be achieved in several ways

[Ani03].

+ Body effect (VSB): Change the threshold voltage by applying different biases at the
body of MOS transistors. Control signals at the body nodes are required. Changing VT
is less efficient because VT is proportional to the square root of VSB

+ Ion implantation (Na): Extra process steps are needed. Both process complexity and
cost are increased. It is an efficient way to adjust VT and already widely used in exist-
ing CMOS processes [Wei00].

+Different channel lengths (L): Scale down the MOS transistor further and intention-
ally introduce more short channel effect to lower the VT. Scaling should be carefully
designed and controlled.

+ Multiple oxide thicknesses (tox): Transistors with different gate-oxide thicknesses can
be fabricated in the same wafer. This technique complicates the process, but the
higher gate-oxide thickness for high-VT~ MOS transistor can reduce the gate capaci-
tance and suppress both the dynamic and static power dissipation [Che95, 095,
Ima00, Tho01].

1.3 Thick-Gate-Oxide MOS Transistor

As to the multiple oxide thickness technique, dual-gate-thickness CMOS processes are the

most commonly used approach. Two different thicknesses of gate-oxide-layers can be fabricated

in the same process. The thin-gate-oxide MOS transistors are optimized to take full advantage of

the process parameters (physical dimension, doping profile, etc.) and operate at the highest possi-

ble speed. Due to smaller dimensions, the voltage swings they can tolerate at the gate and drain

nodes are lower. On the contrary, the thick-gate-oxide MOS transistors also have larger horizontal

dimension in addition to the thicker gate-oxide-layer. Its speed performance is not as good as that

of the thin-gate-oxide transistors due to the longer channel length, while they have much lower

leakage current and are able to handle higher voltage swings at the gate and drain.










Table 1-2. Two types of transistors available in a standard CMOS technology


Thin-oxide Thick-oxide
Parameters
transistor transistor

Gate thickness (nm) 4.5 6.8

Minimum channel length 0.18 0.35
specified in design rule (Cim)
Gate voltage (V) 1.8 3.3

Drain voltage (V) 1.8 3.3



With the continuous scaling of thin-oxide MOS transistors, the thick-oxide MOS transis-

tors became part of the standard offering from the CMOS foundries. In a 0. 18-Clm CMOS foundry

technology, for instance, both the thin-oxide transistor and the thick-oxide transistor are available.

Compared in Table 1-2 are the dimensions and applied voltages of the two types of transistors.

Including the thick-gate-oxide MOS transistor as the standard offering of CMOS technol-

ogy, of course, increases the process complexity, and in turn the cost of chip fabrication. However,

several reasons make the efforts worthwhile in modern CMOS technologies.

The first one among them, as discussed in Section 1.2.2, is that the thick-gate-oxide tran-

sistors can be used as the sleep transistors to disable the core circuits, therefore providing a tech-

nique to effectively control the circuit leakage current and significantly reduce the standby power

consumption. Second, the dual-gate-thickness processes give the option that the core circuits use

more advanced CMOS transistors to operate at higher frequencies, while the I/O interface blocks

using the thick-gate-oxide MO S transistors can bridge the core circuits with those implemented in

the older generations of technologies, or the peripheral circuits which usually employ higher volt-

ages and operate at lower speed. Third, the thick-gate-oxide transistor is also beneficial for RF









and analog circuit design. While the higher transistor fT is certainly welcomed as the technology

advances, the lower supply voltage of thin-gate-oxide transistors causes some serious problems. It

can impair the ability to handle large signals. This limits the power handling capability of amplifi-

ers, reduces the dynamic range, and worsens the phase noise of local oscillators. These can be

bypassed by realizing critical analog circuits with the thick-gate-oxide MOS transistors [Abi04].

1.4 Motivation

In present CMOS technologies, the polysilicon gates on the thin-gate-oxide and the

thick-gate-oxide transistors are formed at the same time. The thin-gate-oxide transistor has a

shorter feature length than that for thick-gate-oxide transistor. Therefore, the thick-gate-oxide

MOS transistor could have the same length as the thin-gate-oxide transistor, and the lithography

limitation is not a barrier to further shorten the thick-gate-oxide MOS transistor. Technically, it is

feasible to shrink the length of the thick-gate-oxide transistor to less than the minimum specified

in the design rule, and down to that for the thin-gate-oxide transistor.

With the steady scaling of thin-gate-oxide transistors, they can operate faster and tolerate

smaller voltage swings. On the other hand, the performance of 3.3-V thick-gate-oxide transistors

has remained standstill. Essentially, they are the devices belonging to an older generation. The

gap between the device characteristics of these two types of MOS transistors, such as supply volt-

age and current drive capability and so on, are becoming greater. Thick-gate-oxide transistors

with a certain degree of scaling with a better combination of current and voltage characteristics

can bridge this gap. To improve the performance of thick-gate-oxide MOS transistor for certain

applications as will be discussed, it is possible to scale down the horizontal dimensions of

thick-gate-oxide transistors to keep up with the scaling trend.









A goal of this research is to explore low cost solutions for scaling down the

thick-gate-oxide MOS transistor without modifying the existing foundry technologies. More spe-

cifieally, the thick-gate-oxide transistors with a channel length less than the design rule specifiea-

tion is the focus of this study. They are named the SDR (sub-design-rule) MOS transistors.

The device characteristics of SDR transistors will be different from that of the normal

transistors, and in turn they may not be used in the conventional ways. To exploit this opportunity,

possible applications in both digital and RF circuits for the SDR MOS transistors are explored.

Careful design and good control of the SDR MOS transistor's length are of importance.

1.5 Methodology

The SDR MOS transistors are structures that have channel lengths shorter than the mini-

mum length required by the design rule. Their characterization data and models are not at hand.

Study and optimization of the SDR MOS transistors, or structures consisting of the SDR MOS

transistors, can typically be done in two ways:

The first one is to use the simulation techniques to predict the performance and to opti-

mize structures at the same time. This method requires detailed process information provided by

the foundries. Even with that, the Einal characteristics still strongly depend on the accuracy of the

available fabrication parameters [McSO2]. This information is proprietary in nature and is not

readily available. This method is a difficult option for university research.

The second method is to implement a variety of structures in a systematic manner and to

Eind out the optimal layout. Usually, multiple layout parameters should be varied, and a large

array of test structures should be tested. More intensive measurements are the drawback of this

method, but it can directly provide the Einal performance results. The second method is a practical

way for this work.









For each potential applications of the SDR MOS structures detailed in the following chap-

ters (including both digital and RF circuits), a series of test structures are designed based on scien-

tific insight and experience, then fabricated in foundry processes and evaluated for optimization.

1.6 Overview of the Dissertation

This dissertation starts with the applications of SDR MOS structures in digital interface

circuits. In Chapter 2, a conventional high-to-low level shifter circuit and the typical problems are

discussed. In this particular situation, the current drive capability and voltage tolerance can be

traded-off. Thick-gate-oxide MOS transistors with different sub-design-rule channel lengths are

measured and analyzed. It is shown that such MOS transistors can improve the current drive capa-

bility without over-stress. A high-to-low level shift circuit using such SDR MOS transistors will

also be discussed. In Chapter 3, the application in the low-to-high level shifter circuit--the coun-

terpart in the reverse direction of I/O paths, is also studied. A composite MOS transistor consist-

ing of a SDR MOS transistor and a conventional thin-gate-oxide transistor is proposed. It will be

shown that the composite MOS transistors, when properly designed, can provide higher current

drive capability without compromising the voltage tolerance. The speed performance of a

low-to-high level shifter using the composite MOS transistors as the drive transistors are com-

pared to the case using the conventional transistors.

Then, building on the concept and characteristics of the SDR structures discussed in digi-

tal circuits, the potential for RF applications of the SDR MOS structures is evaluated. In Chapter

4, the potential application of the composite MOS transistors in RF power amplifiers is examined.

A T/R switch with power handling capability above 31 dBm is presented in Chapter 5. SDR MOS

transistors, along with other circuit techniques, are used to achieve this performance. The

trade-off between power handling capability and switch loss is also discuss. In Chapter 6, the high









frequency performance of SDR MOS structures used as varactors is presented. The higher quality

factor (Q) makes the SDR MOS varactors suitable for millimeter-wave low power and lower

phase noise voltage-controlled oscillator (VCO) applications.

Lastly, the dissertation is summarized and some future work is suggested in Chapter 7.


























































Low-to-high and high-to-low level shifters (LS) used as the interface
circuits along the paths between the circuits with different signaling
levels.


CHAPTER 2
HIGH-TO-LOW LEVEL SHIF TER APPLICATION

2.1 Introduction

As MOS transistors have scaled down along with the operating voltage [SIA05], the high

voltage input/output (I/O) transistors have become part of a standard technology offering to pro-

vide the option to maintain compatibility to the systems using circuits fabricated in the preceding

generations of technologies or other peripheral circuits [O95]. For instance, in 1.8-V 0. 18-Clm

CMOS processes, 3.3-V 0.35-Clm I/O transistors with a thicker gate oxide layer are available.

Unlike the 1.8-V thin-oxide transistor, the 3.3-V thick-oxide transistor requires a longer channel

to support the 3.3-V drain voltage, which in turn limits its drain current.

As shown in Figure 2-1, digital circuits with different signaling levels will employ differ-

ent voltages, for example, 1.8 V and 3.3 V, etc. These different voltages represent the same logic


hl~h-\~j ,j olil~tl ~rtnrtl,7rlon~l I~11ITs


Figure 2-1.









level and they should be translated in both directions by the interface circuits. Therefore, both the

high-to-low and low-to-high level shifters are often used in the I/O circuits along the signal paths.

In this chapter, we will look into the high-to-low level shifter circuit and investigate the

potential application of the thick-oxide MOS transistors with channels shorter than the minimum

length specified in the design rule to improve the current drive capability.

Figure 2-2 shows a typical 3.3-to-1.8-V level shifter circuit [Wang01]. The 3.3-V

thick-oxide transistors (M5/M6) have to be used here as the drive transistors, because the 3.3-V

signal swings at the gates. However, the drain-to-source voltage (VDS) of the drive transistors in

this case only switches between 0 and 1.8 V. Because of this, the channel length chosen to handle


3.3 V


1.8V V


-e


3.3-V Drive Transistor

Level Shifter

Typical high-to-low level shifter, using 3.3-V drive transistors at the
interface between 3.3-V and 1.8-V circuitries.


Figure 2-2.


3. 3-V Transistors


1.8-V Transistors









3.3 V is excessive, and unnecessarily limits the drain current of M5/M6. The drain current (ID) Of

MOS transistors in the saturation region is given by following [Gra04]:



ID ox (V~~(GS VT)2, (2-1)


and in the linear region,



ID ox V,3(GS-VT- VDS)VDS (2-2)


where, C1 is carrier mobility, Cox is unit capacitance of gate oxide, W is channel width, L is chan-

nel length, VGS is gate-source voltage, and VT is threshold voltage which is also dependent on L.

When the gate length L of the thick-oxide layer is scaled further the drain current will pro-

portionally increase. Additionally, the shorter gate length will introduce more significant short

channel effect (SCE). Threshold voltage VT could be lowered, and the drain current will increase

even more. We refer to this type of further scaled thick-oxide MOS transistor as the

sub-design-rule transistor (SDR transistor).

In general, circuit designers can not violate the design rules of a process to reduce the

channel length arbitrarily. However, in this particular application the high-to-low level shifter,

as will be discussed, there is some design space to improve the device and circuit performance.

We will push the process limit while not applying excessive stress to devices.

2.2 Sub-Design-Rule (SDR) MOS Transistor Structure

In this chapter, the thick-gate-oxide sub-design-rule (SDR) MOS structures fabricated in a

conventional 0.18-Clm foundry digital CMOS technology without any process modification are

under investigation. In this technology, the minimum channel length for the conventional 3.3-V

thick-gate-oxide nMOS transistors is 0.35 Clm. On the other hand, the minimum channel length











Thick Oxide POLY

Gate
ouce I rain






n+ 1 n+

LDRc = 0.35 Cim

p-substrate

Substrate


Figure 2-3. Cross-section of the sub-design-rule (SDR) MOS structure.


for 1.8-V thin-gate-oxide nMOS transistors is 0. 18 Clm. To further push forward the drive current

performance of the thick-gate-oxide device, channel length for SDR MOS transistors can be

between 0. 18 and 0.3 5 Clm. Figure 2-3 shows the cross-section of this type of devices. SDR MOS

transistors have the same structure as the conventional 3.3-V thick-gate-oxide MOS transistors,

except that the channel lengths are scaled to less than 0.35 Clm, the minimum specification in the

design rule.

These SDR MOS transistors with channel lengths of 0.30, 0.28, 0.26, 0.24 and 0.22 Clm

(SDR-30, -28, -26, -24, -22 MOS transistor) will be examined and compared to the characteristics

of conventional 0.35-Clm long 3.3-V thick-gate-oxide MOS transistors in Sections 2.3 and 2.4.

These lengths are about 86%, 80%, 74%, 68% and 63% of that of the conventional 3.3-V transis-

tor, respectively.









2.3 DC Characteristics of SDR MOS Transistors

To exam the DC characteristics, a series of DC test structures of SDR MOS transistors

with the same width (4.65 Clm) are fabricated. Figure 2-4 shows the layout of a group of the test

structures. An HP4155A (semiconductor parameter analyzer) and a DC probe station are

employed for the measurements.

SDR Transistors

















Figure 2-4. Test structure layout of a set of SDR MOS transistors for DC
measurements.



2.3.1 Current Drive Capability

ID-VGS curves of these SDR MOS transistors at VDS = 1.8 V are shown on the right side

of Figure 2-5. Drain currents in the plot are normalized to unit channel width. By scaling the

thick-gate-oxide transistor from 0.30 to 0.22 Clm, current drive capability is significantly

increased.

As shown from Equation 2-1 and 2-2, there are two main factors leading to the drain cur-

rent mecreases.

(a) Increase of (~ratio, or effectively decrease of L











10-4


10-0b 0.24 tm a-
E -0.6 `
0.26pCm E
10-8 0.28pCm -r
-rs ~0.30pCm
S0.4
o 10-10 V~


10-12 0.


10-14 '0.0
0.0 1.0 2.0 3.0
Vs (V)

Figure 2-5. Normalized ID-VGS for different SDR MOS transistors at VDS = 1.8 V.

(b) Increase of (VGS -VT) and (VGS -VT -1 VDS due to

decrease of VT

Comparing the SDR-22 to the SDR-30 MOS transistor, for example, the current ratio at

VGS = 3.3 V and VDS = 1.8 V is about 1.4. Now the SDR MOS transistors are biased in the linear

region. This current difference is largely due to the increase of( ratio, or the decrease ofL.

The VGS -V T -1 VD S) = (?3.- VT 09) term gives a relatively smaller improvement fac-

tor for different SDR MOS transistors with lowered threshold voltages.

The high-VDS data in Figure 2-5 clearly show that the down-ward shift of threshold volt-

age (VT) occurs when SDR MOS transistor is scaled from 0.30 to 0.22 Clm. The exact dependence

of threshold voltage on channel length can be extracted from the low-VDS measurement results,

which is plotted in Figure 2-6. When biased at low over-drive condition (VGS ~ 1.0 V), these SDR














0.8


0.6


0.4


0.2


0.0 I
0.0 0.2 0.3 0.4 0.5 0.6
L (Clm)

Figure 2-6. Measured threshold voltages of SDR MOS transistors with different
channel lengths.


MOS transistors are in saturation region and the drain current improvement in percentage is even

more dramatic than high over-drive case (VGS ~. 3.0 V). This is because, when VGS approaches

threshold voltages (VTl), the term (VGS VT)2 is a stronger function of VT,; and gives a more sig-

nificant current increase in percentage.

As shown in Figure 2-6, the threshold voltages of SDR MOS transistors abruptly drops

when the channel length is shorter than 0.35 Clm, the minimum design rule specification. It is

expected that at certain point, the threshold voltage can be negative, which means this SDR MOS

structure will be always on and is no longer a normal transistor. This threshold voltage change sets

the lower limit for the channel length of a functional SDR MOS transistor. An SDR MOS transis-

tor can not be much lower than 0.22 Clm in this particular CMOS process.

Once again in Figure 2-5, the logarithm scale plots on the left side reveal the subthreshold

characteristics of these SDR MOS transistors. Unless the channel length reaches 0.22 Clm, all









SDR MOS transistors have almost same subthreshold slope and normal subthreshold behaviors.

Higher subthreshold currents are as expected for the SDR MOS transistors because the threshold

voltage is lowered. However, the drain leakage current at VGS = 0 V is still well below 1 nA/Clm

and considered within the controllable scope [SIA05]. Within a certain range of channel lengths,

we do have some opportunities for optimization of SDR MOS transistors.

2.3.2 Voltage Handling Capability

The breakdown voltage (VBK) sets the maximum voltage that can be applied either across

the drain and source, or across the gate and drain. When VDS approaches the breakdown voltage,

the drain current of device rapidly increases, even abruptly jumps which should be always

avoided. Therefore, a sufficient voltage margin should be reserved between the transistor's opera-

tional voltages and its breakdown voltages. When breakdown occurs, ID VDS curves will bend

the most. We can expect the greatest curvature around the breakdown voltage along the curves.

For consistency and ease of comparison, breakdown voltages for these MOS transistors are mea-

sured at the drain-to-source voltage (VDS) when the second derivatives of ID to VDS reach the

maximum.

The lowering of breakdown voltages in SDR MO S transistors is one of the most important

effects resulting from further scaling down of the channel length. Listed in Table 2-1 are the mea-



Table 2-1. Breakdown voltages of sub-design-rule MOS transistors

0.22 0.24 0.26 0.28 0.30 0.35
L (pm)(SDR-26) (3.3-V)

VGs= 1.01 ~ 4.7 ~ 4.8 ~ 5.0 ~ 5.1 ~ 5.3 ~ 6.4
VBK (V) 1.4

VGs=0 ~ 8.4 ~8.4 ~8.4 ~ 8.6









sured breakdown voltages of SDR MOS transistors, together with that of the conventional 3.3-V

MOS transistor.

At VGS = 1.0 / 1.4 V, the breakdown voltages of these SDR MOS transistors drop from

that of the 3.3-V transistor by 1.1 ~ 1.7 V. The reason is that the punch-through between the drain

and source occurs more easily when the channel becomes shorter. This effect limits the maximum

voltage that can be applied to the drain node of SDR transistors. We need to sacrifice some volt-

age handling capability to obtain the current advantage of these SDR transistors. In Section 2.3.3,

there will be more discussions on the proper selection of channel length of SDR MOS transistors

particularly for the 3.3-to-1.8-V level shifter application.

The off-state breakdown voltages measured at VGS = 0 V show no obvious degradation

due to the scaling of the SDR MOS transistors down to 0.26 Clm. The gate oxide of SDR transis-

tors is shorter than the conventional 3.3-V transistor, while the thickness is the same as that of the

conventional transistor. The gate dielectric layer should sustain similar voltage across it, either

between the drain and gate, or between the gate and source. This means that these SDR MOS

transistors can tolerate as much gate-to-drain voltage (VGD) as the conventional 3.3-V MOS tran-

sistor. Therefore, the gates of SDR MOS transistors can be biased up to 3.3 V without excessively

stressing the MOS structures.

2.3.3 Optimization of MOS Transistors for Level Shifter Application

The 3.3-to-1.8-V level shifter circuit is an excellent example of digital application for

SDR MOS transistors. The conventional 3.3-V MOS transistors (M5/M6 in Figure 2-2) can easily

be replaced by the SDR MOS transistors for drive current enhancement.

Because the gate oxide layer of SDR MOS transistors is sufficient to handle the 3.3-V

swing from the preceding circuitry, there is no undermining of voltage tolerance at its gate node.









On the drain side, the SDR transistors replacing M5/M6 only need to sustain 1.8-V, instead of

3.3-V swing. The breakdown voltage necessary for the 1.8-V operation could be lower. The volt-

age margin (VBK-VDD) reserved for the conventional 3.3-V MOS transistors with 3.3-V supply

voltage is about 3.1 V (6.4V-3.3V). The measurement results in Table 2-1 indicate that the

0.26-Clm long SDR transistor (SDR-26) has high enough breakdown voltage (~ 5.0V), so that an

adequate margin (5.0V-1.8V=3.2V) is kept for its operation with 1.8-V supply. Furthermore, in

this level shifter application, the gates of drive transistors (M5/M6) are swept quickly from 0 V to

3.3 V, with drain biased no higher than 1.8 V. The drive transistors enter linear region almost

instantaneously, and for only a small portion of time the transistors stay in saturation region.

Because of these, the level shifters using the SDR-26 transistors should be resistant to the hot-car-

rier related performance degradation [Tak95].

1.0
M SDR-26

0.8 VGS=
0 ~1.8V
#3.3V

0. l28 3.3V
22.8V
#2.3V )

S0.4 -2.3V
~l1.8V

1.8V
I1.3V _)
0.2
I 1.3V
0.8V )C
1( 0.8V

Vs (V)

Figure 2-7. Comparison of normalized ID-VDS between SDR-26 and conventional
3.3-V MOS transistors.









The SDR-26 MOS transistor is 26% shorter than the conventional 3.3-V transistor. Its

threshold voltage is 0.66 V, which is 0. 18 V lower than that of the 3.3 -V transistor. When M5/M6

in Figure 2-2 are replaced by SDR-26 MOS transistors, the gate overdrive (VGS-VT = 3.3-VT) iS

increased by about 7%.

The ID per unit width (Clm) versus VDS curves of SDR-26 and 3.3-V MOS transistors are

shown in Figure 2-7. Biased at the same gate-to-source voltage (VGS), the SDR-26 MOS transis-

tor delivers more than 1.28 times the current of the 3.3-V transistor. In Figure 2-8, the ID-VGS

curves of SDR-26 and 3.3-V transistors are also compared. The linear scale plots once again show

that the drain current of the SDR-26 transistor is at least 1.28 times that of the 3.3-V transistor,

and this current enhancement is even more substantial for low VGS (~ 1 V). The shaded area in

Figure 2-8 clearly illustrates the current increase.


0.8




0.6


10-4


10-6










10-12


10-14
0.0


Figure 2-8.


-/ SDR-26, Vs=1.8V ~ 0.2
~73.3-V, VDs=1.8V
SSDR-26, VDs=0.05V
3.3-V, VDs=0.05V
CD E '0.0
1.0 2.0 3.0
Vs (V)

Comparison of normalize ID-VGS between SDR-26 and conventional
3.3-V MOS transistors in both linear and logarithm scales, when VDS
1.8 and 0.05 V.









Normal subthreshold behaviors can be observed by the logarithm scale plots in Figure 2-8.

SDR-26 and 3.3-V MOS transistors have same subthreshold slopes at both low and high VDS,

indicating the short channel effects are still well controlled in SDR-26 MOS transistors. The leak-

age current of SDR-26 transistors at high VDS is increased to 10-12 from 10-14 A/Clm, which is

still lower than the specification for low voltage transistors in more advanced CMOS processes

[SIA05]. Additionally, since the number of I/O drive transistors used in an integrated circuit is

limited, this increased leakage is tolerable.

2.4 Capacitance Property of SDR-26 MOS Transistor

Speed performance in digital circuits usually can be evaluated by the propagation delay

(td), as well as the rise time (zr) and the fall time (zf). From Equation 2-3, we can see both the cur-

rent drive capability (lo) of preceding stage and gate capacitance (Cload) as the load to preceding

stage strongly affect the speed performance.


Cload AV
td I(2-3)


All data compared above, however, are measured at the same channel width (W) for

SDR-26 and 3.3-V MOS transistors. Compared to the 3.3-V transistors with unit width, the

SDR-26 transistors have the same gate-oxide thickness but shorter length, therefore less gate

capacitance. For a fairer comparison, the drain current should be normalized to the same gate

capacitance. Therefore, it is necessary to study the dependence of gate capacitance on the channel

length of SDR MOS transistors.

Approximately, the gate capacitance (CGS) of MOS structures has the linear relation with

length L as shown below:











CGS = CGSO-W+y- Cox-W-L,


(2-4)


where, y represents the constant for saturation region or linear region. Simulation data of

longer-channel 3.3-V thick-oxide MOS transistors between 0.35 and 1.0 Clm long are plotted in

Figure 2-9. The unit gate capacitance of 0.3 5-Clm long 3.3-V MOS transistors is 1.67 fF/Clm as

simulated. The linear fitting line is drawn in Figure 2-9, and it can be used to extrapolate the gate

capacitance (CGS) of SDR MOS transistors. The SDR-26 MOS transistor of interest is expected to

have unit gate capacitance of 1.33 fF/Clm, which is only 79.6% of that of the minimum length

3.3-V MOS transistors. Compared at the same gate capacitance which acts as the load to preced-

ing stage, a SDR-26 transistor is 25.6% wider and this increases its drive current to about 60%

higher than that of the conventional 3.3 -V MOS transistor.

5.0 .....


0.0 0.2 0.4 0.6 0.8 1.0
Channel Length (Cim)

Simulated gate capacitance of longer channel 3.3-V MOS transistors, and
extrapolated gate capacitance of SDR-26 MOS transistors.


Figure 2-9.










2.5 High-to-low Level Shifter Speed Performance

Between SDR-26 and 0.35-Clm long conventional 3.3-V MOS transistors, the increases of

drain current in both fixed channel width and fixed gate capacitance cases are described in the

previous sections. To interpret such improvements to the speed performance in a level shifter cir-

cuit, Cadence Spectre simulator is used to estimate the difference.

At first, modeling of SDR-26 MOS transistors is necessary. Based on the conventional

3.3-V transistor's model file, we built a model to approximately describe the behavior of the

SDR-26 transistor by modifying a few parameters, such as gate oxide thickness (tox), threshold

voltage (vth0), mobility (uO) and saturation velocity (vsat) (see APPENDIX). Shown in

Figure 2-10 are the simulated ID-VDS and ID-VGS for both the SDR-26 and 3.3-V MOS transis-

tors, with the same channel width. The plots match the measurement results. This simulation con-

1.0
...simulated
measured

0.8-
ID-Vs of SDR-26


S0.6 ~ ID-Vs of 3.3-V

L Vcs =3.V ,-

0.4 ,
SID-VGs of SDR-26 ,' VDs = 1.8 V


0.2 ',*',-
,'J ,-' ,,* ID-VGs of 3.3-V


0.0
0.0 1.0 2.0 3.0
VDs /VGs (V)

Figure 2-10. Simulated ID-VDS and ID-VGS curves of the SDR-26 and 3.3-V MOS
transistors. The simulations also match the measured currents for both
types of transistors.









firm that the "created" model file gives 1.28 times the drain current of the conventional 3.3-V

transistors. The SDR-26 and 3.3-V MOS transistors have gate capacitance of 6.23 and 7.85 fF,

respectively, so that the capacitance ratio is 0.79. These changes reflect the measured improve-

ment of current drive capability discussed in Section 2.3.3 and gate capacitance change discussed

in Section 2.4.

Secondly, the same 3.3-to-1.8-V level shifter structure shown in Figure 2-2 is used in sim-

ulation. Two versions of level shifters under comparison are shown in Figure 2-11. Version A rep-




3.3-V inverter 1.8-V inverter

-L~ level shifter A
1.8V
I I conventional 3.3-V


A5 A6 A7



L _a outputA
Version A ja

Version B input level shifter B
1.8V
I I outputB


I B5 B6 MB7



DR-26


3.3-V circuitry 1.8-V circuitry

Figure 2-11. Schematics of level shifter circuits in simulation. Version A uses
conventional MOS transistors as drive transistors, while Version B uses
SDR-26 MOS transistors.









resents the conventional implementation, and the conventional 3.3-V MOS transistors are used as

the drive transistors (M1A M2A) in the level shifter. The 3-stage 3.3-V inverter chain (Al through

A3) preceding the level shifter generates an input signal whose shape is approximately indepen-

dent of the number of propagation stages. Similarly, the 3-stage conventional 1.8-V inverter chain

(A5 through A7) is also used following the level shifter to maintain the same capacitive loading

for the level shifter [Tau98]. All these inverters use the conventional 3.3/1.8-V nMOS/pMOS

transistors. The version B is the same as version A, except that the two drive transistors (MIB/

M2B) are replaced by the SDR-26 MOS transistors. These two SDR-26 transistors in version B

are 26% wider than their counterparts in version A, so that the inverters A3 and B3 will see the

same capacitive loads.

In Figure 2-12, both the pull-down and pull-up cases for the level shifters are examined. In

both Figure 2-12 (a) and (b), the input signals (Figure 2-11) for different implementations are the

same and overlaid. This is possible because the drive transistors of these two versions give the

same capacitive load to the preceding stages. The same input signals with 3.3-V swing are

delayed differently and level-shifted to output signals with 1.8-V swing. The time differences of

output signals for both pull-down and pull-up cases directly show the improved speed perfor-

mance of the level shifter implemented by using the SDR-26 transistors over the conventional

3.3-V transistors.

The data extracted from the waveforms are listed in Table 2-2, including the pull-down

propagation delay (zn) and the pull-up propagation delay (zp), and the fall time (zf), the rise time

(zr). A nearly 20% improvement in the propagation delay is expected from this 3.3-to-1.8-V level

shifter circuit using SDR-26 MOS transistors. This speed improvement is obtained without any





















































Figure 2-12. Comparison of the SDR-26 and conventional 3.3 -V MOS transistors used
as the drive transistors in 3.3-to-1.8-V level shifters. (A) propagation
delay in pull-down case (zn); (B) propagation delay in pull-up case (zp).


process modifications, therefore using SDR-26 transistors is a low-cost solution. There is no

change in the circuit configuration.










Table 2-2. Speed performance of level shifters using the SDR-26 and conventional 3.3-V
MOS transistors as the drive transistors

version A version B delay
(conventional 3.3-V) (SDR-26) improvement

pull-down delay (ps) zIs= 28.2 ze = 23.5 16.7%

pull-up delay (ps) UpA = 47.4 zpB = 38.2 19.4%

fall time (ps) IfA = 64.67 Its = 47.55 26.5%

rise time (ps) ZrA = 100.94 ZrB = 66.94 33.7%


2.6 Summary

Level shifters are crucial for digital CMOS I/O interface circuits to translate different volt-

age levels back and forth. Level shifting needs extra stages, and introduces extra delays, which

should be limited to minimum. In a high-to-low level shifter, the drive transistors have to be real-

ized by using thick-oxide high-voltage MOS transistors to withstand the high voltage swing at

gate node. The drain nodes of drive transistors, however, only need to handle low voltage swing.

These characteristics of high-to-low level shifters provide the opportunities for use of SDR MOS

transistors which have higher current drive capability.

In this chapter, a 3.3-to-1.8-V level shifter circuit using a 0. 18-Clm CMOS foundry tech-

nology is studied. The conventional 3.3-V MOS transistor is compared to a series of thick-oxide

SDR MOS transistors. The measurement results show that, in this particular application, the

0.26-Clm long SDR MOS transistor (SDR-26) can deliver 1.28 times the drain current as the con-

ventional one, while maintaining sufficient breakdown voltages to tolerate the signal swing at the

gate and drain nodes. When replacing the conventional 3.3-V drive transistors in the 3.3-to-1.8-V

level shifter, the SDR-26 transistors are 25.6% wider and can provide 60% more drain current. In









simulations, this current enhancement translates into a nearly 20% reduction in the propagation

delay.

The use of SDR MOS transistors in the high-to-low level shifters should not be limited

only to this 0.18-Clm technology by all means. This concept should be viable in other more

advanced technologies. In general, this application of SDR MOS transistors provides another way

to exploit the scaling of CMOS technologies. This study shows that further scaling and optimizing

the thick-oxide MOS devices are feasible and can provide useful benefits.









CHAPTER 3
LOW-TO-HIGH LEVEL SHIFTER APPLICATION

3.1 Introduction

Another circuit needed in the input/output (I/O) blocks is a low-to-high level shifter cir-

cuit. Figure 3-1 shows the schematic of a conventional low-to-high level shifter [Koo05, TanO2].

Thick-gate-oxide high-voltage MOS transistors are used as the drive transistors (M15/M17) here,

because they have to sustain high-VDD signal swing at the drain nodes. A problem with this

implementation is that the gates of thick-gate-oxide high-voltage drive transistors (M 15/M17)

with higher threshold voltage are driven by a circuit whose output switches only between 0 and


I ~Drive Transistors

Level Shifter


Figure 3-1.


Typical low-to-high level shifter, using thick-gate-oxide drive transistors
at the interface between low-VDD and high-VDD circuitries.


Thin-gate-oxide Transistors


Thick-gate-oxide Transistors









low-VDD. Because of this, the gate overdrive (VGS-VT) is small, thus the drive current is limited.

These in turn limit the switching speed of I/O circuits.

In the previous chapter, we have studied a typical 3.3-to-1.8-V CMOS level shifter, and

the way to improve the speed performance by using the SDR MOS transistors. Could this idea of

using thick-oxide sub-design-rule (SDR) MOS transistor become an inspiration to build another

structure suitable for low-to-high level shifter circuits?

Extensive efforts have been taken to improve the voltage and power handling capability of

the MOS transistors, while still keeping the drain current and gm high [Ma99, BucO3, Lia03,

MenO4]. In these cases, geometry and/or doping profile need to be modified. Unfortunately, these

solutions usually are either incompatible with standard CMOS technologies, or require certain

modifications to existing foundry processes and increase the fabrication cost.

In this chapter, we want to take advantage of the SDR MOS transistor concept, and build a

novel composite structure suitable for use in the low-to-high level shifter, which is fully compati-

ble with the standard CMOS processes from the foundries.

3.2 Composite MOS Transistor Structure

As discussed, the thin-gate-oxide MOS transistor has higher unit drain current and faster

speed performance. This device is suitable for low power circuits because the voltage tolerance is

limited. On the contrary, the thick-gate-oxide MOS transistor has lower unit drain current and

slower speed performance. However, this type of device is preferable for high voltage, high power

situation due to the thicker gate dielectric layer. To combine the advantages of these two types of

MOS devices, a composite MOS transistor structure is proposed in this chapter [Xu05].

The composite MOS transistor consists of a series combination of a conventional

thin-oxide transistor (TN sub-transistor) and a sub-design-rule thick-oxide sub-transistor (SDR










Poly Gate 2


Implant
Mask

Source

g~~~~ | I -iffusion
Mask
A I I


Drain
4 -Thick Oxide
5 | 5Mask



Poly Gate 1

Figure 3-2. Layout of the composite MOS transistor. Only 2 cells are shown here.


sub-transistor). A layout of such a composite MOS transistor is shown in Figure 3-2. A multi-

ple-finger layout is employed, and two cells are shown here as illustration.

The cross-section along dashline AB (see Figure 3-2) is also drawn in Figure 3-3. The TN

sub-transistor and SDR sub-transistor share an n+ diffusion region in the middle without metal

connection. The diffusion on the left side of TN sub-transistor acts as a source, and the diffusion

on the right side of SDR sub-transistor acts as a drain. Their polysilicon gates are connected

together by metal layers to form a single gate, and their bodies are connected together through the

p-substrate. Such a four-terminal structure functions as a single MOS transistor. The equivalent

circuit of the composite MOS transistor as well as its simplified version are shown in Figure 3-4.

Compared to the conventional thin-oxide transistor (TN sub-transistor), the composite

transistor has lower drain current due to the additional SDR sub-transistor in series combination.











Thin Oxide POLY Thick Oxide


Gatel Gate2
ource ....... ........... ..... rain










shared Ulttusion p-substrate


TN Sub-transistor SDR Sub-transistor
Substrate


Figure 3-3. Cross-section of the composite MOS transistor.

On the other hand, the SDR sub-transistor helps the composite transistor to tolerate a larger volt-

age drop across its drain and gate, and across its drain and source than the thin-oxide transistor.

This of course increases the breakdown voltage of composite transistor structure compared to that

of the thin-oxide transistor alone. The composite structure is similar to the cascode configuration

with a common gate stage using a thick-oxide transistor, which has been proposed to improve the

voltage handling capability [Web03]. However, besides the gate connections, another key differ-

ence is that the channel length of SDR sub-transistor is significantly shorter than the minimum

length of the conventional thick-oxide transistors. This modification increases the drain current.

Because of the strong short channel effects, the SDR sub-transistor has lower threshold voltage

and the dramatically increased leakage current if it is used with a 3.3-V supply. Therefore, such an

SDR sub-transistor does not work normally by its own, and should be used in series combination

with a conventional TN sub-transistor. It is expected that the drain current of the composite MOS










SDR Sub-transistor

Drain

Gate2 'l Drain



Gate Sub Gate Sub




Source

Gatel 1

f Source
TN Sub-transistor

Figure 3-4. Equivalent schematics of the composite MOS transistor.

transistor is somewhere in between those of the conventional thick-oxide and conventional

thin-oxide transistors, as will be discussed in the following sections.

3.3 Composite MOS Transistors in a 0.18-Cim Process

The first composite MOS transistor was fabricated in the same 0.18-Clm CMOS technol-

ogy as the SDR MOS transistors discussed in Chapter 2. This composite structure will be referred

as composite-18 transistor and it consists of a 0. 18-Clm long thin-oxide transistor (TN transistor)

and a 0. 18-Clm long thick-oxide transistor (SDR-18 sub-transistor). This combination of channel

lengths is intended to diminish the drain current degradation caused by the SDR transistor in

series. However, having this thin oxide as part of the gate inevitably sets the maximum

gate-to-source voltage to 1.8 V.










To study its possible advantages over conventional transistors, a 0.35-Clm long 3.3-V

thick-oxide and a 0. 18-Clm long 1.8-V thin-oxide MOS transistor were also fabricated in the same

technology for comparison. All the transistors have the same channel width (23.25 Clm). The lay-

out of the DC test structures is shown in Figure 3-5. A semiconductor parameter analyzer

(HP4155A) and a DC probe station are employed for the measurements.


Transistors
















Figure 3-5. Test structure layout of the composite-1 8, conventional 3.3-V thick-oxide
and conventional 1.8-V thin-oxide MOS transi stores for DC
measurements .


3.3.1 Current and Breakdown Characteristics

Figure 3-6 shows the measured ID per unit width versus VDS. The gates of composite-18,

conventional 3.3-V and 1.8-V transistors are biased up to 1.8 V, 3.3 V and 1.8 V, respectively. The

composite-18 transistor at VGS = 1.8 V can deliver as much current as the 3.3-V transistor biased

at VGS = 3.3 V. If biased at the same gate voltage (VGS = 1.8 V), the composite-18 transistor pro-

vides about 3 times of the saturation current of the 3.3-V transistor. This drive capability is even

comparable to that of a 1.8-V transistor. This result is surprisingly good.
















E C 3.3V




) I L ~Q~ -~ )2.3V


0r.8v 0.8v 1.8V

O.3V ( .3V

0.0 1.0 2.0 3.0
Vs (V)


Figure 3-6. Normalized ID-VDS of the composite-18, conventional 3.3-V thick-oxide
and conventional 1.8-V thin-oxide MOS transistors.

The breakdown voltages (VBK's) and threshold voltages (VT's) of these three types of

transistors are listed in Table 3-1. The composite-18 transistor has comparable breakdown voltage

as the 3.3 -V transistor. This is about 50% higher than that of the 1.8-V transistor. Furthermore, the

composite-1 8 transistor still has the same low threshold voltage as that of the 1.8-V transistor,

which is 0.4 V below that of the 3.3-V transistor. This in turn further increases the current drive

capability of the composite-1 8 transistor compared to that for the conventional 3.3-V transistor.

Table 3-1. Breakdown voltages and threshold voltages for the composite-18, and the
conventional 3.3-V and 1.8-V MOS transistors

3. 3-V composite-1 8 1.8-V

VGs=0 ~ 9.0 ~ 9.0 ~ 6.5
VBK (V)
VGs=1.8/3.3 ~ 5.5 ~ 6.5 ~ 4.0

VT (V) VDs=0.05 ~ 0.9 ~ 0.5 ~ 0.5









3.3.2 Subthreshold Current Leakage Issues

As shown in Figure 3-7, the ID-VGS curves in a logarithm scale reveal the subthreshold

behaviors of the composite-18, conventional 3.3-V and 1.8-V MOS transistors. For low VDS

cases (VDS = 0.05 V), all three types of transistors have the same subthreshold slopes and the nor-

mal subthreshold behaviors can be observed. However, when the VDS is biased at VDD (3.3 V for

the composite-18 and 3.3-V transistors, 1.8 V for the 1.8-V transistors), the composite-1 8 transis-

tor obviously has abnormal subthreshold behavior compared to the other two conventional tran-

sistors. The drain leakage current of the composite-1 8 transistor around VGS = 0 levels off, and is

significantly higher than expected.

The cause of this behavior is that abnormally high voltage is present at the shared diffu-

sion region of the composite structure (VM(a) in Figure 3-8 (a)), producing higher leakage current


10-2 :VDs = 1.8/3.3 V


10-4


10-6 VDs = 0.05 V


O 10-8


10-10
composite-18
12 3.3-V
10-1
S1.8-V

10-14
0.0 1.0 2.0 3.0
Vs (V)

Figure 3-7. ID-VGS curves in a logarithm scale for the composite-18, conventional
3.3-V and 1.8-V MOS transistors with VDS = 0.05 V and VDD (1.8/3.3 V).






















































B

Figure 3-8. Illustration of source current matching between (A) the composite-18
transistors and (B) the conventional 1.8-V MOS transistors.


through the drain to body [Cha01]. We are not able to directly measure the voltage at this node

(VM~a)) because there is no pad connection for the node in the test structure. However, this prob-

lem can be solved by using source current matching to calculate the voltage of the shared diffu-

sion region.

Using two DC test structures, the currents at any nodes of the composite-18 and the 1.8-V

transistors can be measured separately. The gate current is usually negligible, and other current


A

ID(b) ID1(b)


(b)
Sp-substrate
(b B1b


(1.8-V Transistor)









paths in the composite-1 8 and conventional 1.8-V MOS transistors are shown together in

Figure 3-8. It is obvious that, the source currents (Is(a), IS(b)) are

for the composite-18 transistor,


Is )-I)=I2 B ) ) (3-1)

for the 1.8-V transistor,


(b) _(b) (b) (b) (b)
Ig D B 1 B (3 -2)

The TN sub-transistor is exactly the same structure as the conventional 1.8-V transistor,

therefore each of the source current (Is(a) and IS(b)) is the same monotonic function of Vy~a) and

Vy~b). Despite the discrepancy in the drain current or the body current between the two transistor

structures, each of the transi stores should have the same VM (i.e., VMO ) = VM(a)) when the source

currents are same (I,(a) = I, 3).~ Therefore, we can match the source currents of the these transis-

tors, and get the voltage of shared diffusion region (VM(a)) by reading the drain voltage of the

1 .8-V tran si stor (VyO~b)

The Is-VDS curves of the composite-1 8 and 1.8-V MOS transistors are drawn together in

Figure 3-9 to demonstrate the method of source current matching. When VGS is between 1.0 and

0.4 V as shown in Figure 3-9 (a), the matched voltages at the shared diffusion region (Vy(a)) are

only between 1.4 and 1.8 V. Just like what we have seen in Figure 3-7, there is no significant

increase of the drain leakage current. When VGS is further lowered as shown in Figure 3 -9 (b) and

(c), however, it is evident that the matched voltage (VM(a)) increases quickly and could be higher

than 2.2 V. This is consistent with the deviation of subthreshold current from the normal seen in

Figure 3-7. The worst case occurs at VGS = 0 V, when the matched voltage at the shared diffusion











4.0e-3


3.0Oe-3


2.0e-3


1.0e-3


0.0
0
2.0e-6


1.5e-6


1.0e-6


5.0Oe-7


0.0
0.0
8.0e-9 r-


1.0 2.0 3.0


6.0e-9


4.0e-9


2.0e-9


0.0 1.0 2.0 3.0

VM(b) or VD (V)

Calculation of the voltage at the shared diffusion region (Vy(a)) by using
source current matching. (A) VGS-1.0~0.4 V; (B) VGS-0.3~0.2 V; (C)
VGS=0.1~0.0 V


Figure 3-9.









reaches the highest. This increased voltage (VM(a)) at the shared diffusion is higher than the nom-

inal value (1.8 V), and it can cause the gate-oxide wear-out and the hot-carrier related perfor-

mance degradation in the TN sub-transistor. This undermines the reliability of the composite-1 8

transistors even though VM(a) is not sufficient to cause breakdown. Therefore, the 0.18-Clm long

SDR sub-transistor can not sustain sufficient voltage drop to protect the TN sub-transistor. In this

0.18-Clm CMOS process, an SDR sub-transistor with a channel length longer than 0.18 Clm is nec-

essary for the composite transistor.

Because of these, the composite MOS transistors should not only be checked for the

breakdown voltages, but also checked for the subthreshold leakage currents to assure that each

sub-transistor inside the composite structures is reliable throughout the operation voltage ranges.

3.4 Composite MOS Transistors in a 0.13-Cim Process

In the second realization, a series of DC test structures of different composite MOS tran-

sistors with the same width (2.96 Clm) is fabricated in a foundry 0.13-Clm CMOS technology. The

TN sub-transistors in all these composite transistors have the minimum length for conventional

1.2-V transistors, which is 0. 12 Clm. The SDR sub-transistors of these structures include lengths

of 0.20, 0.22, 0.23, 0.25, and 0.27 Clm. The lengths of the SDR sub-transistors are used as the

names of different composite transistors, for instance, composite-27 and so forth. Figure 3-10

shows the layout of a DC test structure. For better die area efficiency, the DC pads for drain and

body node connections are shared by three transistor structures. In the same process, the conven-

tional 0. 12-Clm long 1.2-V thin-oxide transistor and conventional 0.34-Clm long 3.3-V thick-oxide

transistors are also fabricated for comparison.










composite transistors














Figure 3-10. Test structure layout of a group of the composite MOS transistors for
DC measurements.

3.4.1 Current Characteristics

ID-VGS curves of the composite MOS transistors at VDS = 3.3 V are compared to those of

the conventional 3.3-V and 1.2-V transistors in Figure 3-11. The drain currents in the plot are nor-

malized to unit channel width.

As shown in the linear scale plots in Figure 3-11, reducing the length of thick-gate-oxide

SDR sub-transistor in the composite structure from 0.27 to 0.20 Clm significantly increases the

drain current, and makes the drain current approach that of the conventional 1.2-V transistor. For

example, between the composite-20 (0.20-Clm long SDR transistor) and composite-27 (0.27-Clm

long transistor), the current ratio at VGS = 1.2 V is more than 2. Even though it is not straightfor-

ward to calculate the effective (~ratio for these composite transistors the use of thick-oxide

SDR MOS structures in the composite transistor design contributes to the drain current increase.

In addition, the threshold voltage of SDR sub-transistor decreases when it is scaled, as dis-

cussed in Section 2.3. The SDR sub-transistor sets the limit for channel formation, until its thresh-

old voltage is lowered to that of the TN sub-transistor. When the SDR sub-transistor is scaled











10-3 1 0.8


comp-20
10-5 comp-22
comp-23 -0.6
comp-25-
h comp-27
S10-7


10-9


10-11composite 0.2
c0 3.3-V


10-13 AA ~ 'I 0.0
0.0 1.0 2.0 3.0
VGS O/


Figure 3-11. Normalized ID-VGS plots for the composite and the conventional 3.3-V
transistors with VDS = 3.3 V, and the conventional 1.2-V transistor with
VDS =1.2 V.

from 0.27 to 0.22 Clm, the threshold voltage of the composite transistor decreases. The high-VDS

measurement results in Figure 3-11 show the down-ward shift of threshold voltage (VT) with the

SDR sub-transistor length. The threshold voltages of the composite transistors extracted from the

low-VDS measurement data are listed in Table 3-2. These values are closer to that of the 1.2-V

transistor, rather than to that of the 3.3-V transistor. The composite-22 transistor has about the


Table 3-2. Measured threshold voltages of the composite transistors, and the
conventional 1.2-V, 3.3-V transistors


transistors 1.2-V com-22 com-23 com-25 com-27 3.3-V


VT(V) ~ 0.46 ~0.46 ~ 0.48 ~0.52 ~0.56 ~ 0.72









same threshold voltage as the conventional 1.2-V transistor, which is 0.26 V below that of the

3.3-V transistor. In the case of 1.2-to-3.3-V level shifter, the overdrive (VGS-VT) of drive transis-

tor is relatively small (~ 0.5 V) and can be significantly increased in percentage by decreasing the

threshold voltage. When biased at the maximum gate voltage (VGS = 1.2 V), the drive transistors

are still in saturation region. Therefore, the square of overdrive for the composite-20 and compos-

ite-27 transistors, for instance, can differ by about


GVS VT20) (1.2 0.46) .4 3)

(VGS- VT27)2 (1.2 -0.56)2

As discussed, the voltage protection for the TN sub-transistor is degraded when its SDR

sub-transistor becomes shorter. To examine this important aspect of the composite MOS transis-

tors the subthreshold behaviors, ID-VGS curves are plotted in logarithm scale in Figure 3-11. In

the first case, the drain leakage current of composite-27 MOS transistor is well below that of the

conventional 1.2-V transistor. This is because the voltage at the shared diffusion region (VM(a>))is

well below 1.2 V. The 0.27 Clm length for SDR sub-transistor is too long, and the drain current

increase is limited. For the composite-20 transistor, the drain leakage current around VGS = 0 V is

even higher than that of the 1.2-V transistor. When the drain is biased at 3.3 V, the 0.20-Clm long

SDR sub-transistor did not sustain sufficient voltage drop so that the voltage at the shared diffu-

sion is higher than 1.2 V and the drain current is increased. This leads to potential reliability

issues at the shared diffusion region inside the composite-20 transistor structure.

Between these two extreme cases, the composite-22 MOS transistor has the similar sub-

threshold characteristics as the 1.2-V transistor, including that for the worst case when VGS = 0 V

This indicates that the voltage of the shared diffusion region goes up to 1.2 V. The 0.22-Clm long









SDR sub-transistor provides sufficient voltage protection to the 0.12-Clm long TN sub-transistor

for the whole 3.3-V operating range. This is also consistent with the threshold voltage measure-

ment results which suggest that the channel formation is no longer hindered by the SDR sub-tran-

si stor.

The combination of channel lengths in the composite-22 transistor gives a better trade-off

between the drive current capability and the reliability property, and the composite-22 MOS tran-

sistor is the optimal for the use as the drive transistors in the 1.2-to-3.3-V level shifter circuits.

3.4.2 Voltage Handling Capability

The breakdown voltage (VBK) sets the maximum voltage that can be applied either across

the drain and source, or across the gate and drain. When VDS approaches the breakdown voltage,

drain current of the device increases rapidly, even jumps abruptly which should be always

avoided. Therefore, sufficient voltage margin should be reserved between the transistor's opera-

tional voltage range and its breakdown voltages. The same measurement method for breakdown

voltage described in Section 2.3.2 is employed here for the composite transistors, and the results

are listed in Table 3-3 together with those of the conventional 3.3-V and 1.2-V MOS transistors.

While the threshold voltages are close to that of the conventional 1.2-V transistor, the

composite MOS transistors have comparable breakdown voltages as that of the 3.3-V transistor,


Table 3-3. Breakdown voltages for the composite transistors, and the conventional 3.3-V
and 1.2-V transistors

Transistors comp-20 com p-22 com p-23 3.3-V 1 .2-V


VGs=1.2 ~8.9 ~ 9.2 ~9.5 ~ 6.1 ~ 3.4
VBK
(V) VGs=0 ~7.0 ~9.0 ~9.0 ~ 7.5 ~ 4.6









which is around two times that of the 1.2-V transistor. The breakdown voltages of composite tran-

sistors significantly increase when the SDR sub-transistors are added. The reason is that before

the VDS reaches the breakdown voltage, a large portion of the voltage is dropped across the SDR

sub-transistor, and the shared diffusion region is kept below the breakdown voltage of the 1.2-V

transistor. This in turn allows the drain nodes of the composite MOS transistors to be biased at a

higher voltage.

When the SDR sub-transistor is longer, the protection from or the voltage drop across the

SDR sub-transistor increases, therefore the breakdown voltage of the composite structure

becomes higher. Among the different composite structures, the composite-22 MOS transistor is

the shortest one which has sufficient breakdown voltage for 3.3-V supply operation. This high

voltage handling capability is combined with the low threshold voltage of the conventional 1.2-V

transistor.

Having the thin-oxide as part of the gate in the composite MOS transistor structures sets

the maximum gate-to-source voltage (VGS) to only 1.2 V. However, the asymmetric composite

structures, from the gate to the drain, make it almost ideally suited for the asymmetric voltage

swings in the 1.2-to-3.3-V level shifter circuits.

3.5 Composite MOS Transistor Capacitance Property

The speed performance of digital circuits usually is evaluated by propagation delay (td),

as well as the rise time (zr) and the fall time (zf). Equation 2-3 indicates that both current drive

capability (lo) of preceding stage and gate capacitance (Cload) as the load to the preceding stage

determine the speed performance. The data compared in Section 3.4, however, are measured at

the same channel width (W) for all transistors. The transistor structures have different gate capac-













Composite
Transistors .........


Tr a~n it

open





Layout of the AC test structures for the composite MOS transistor and
the open structure.


Figure 3-12.


itance due to different channel lengths. For a fairer comparison of current drive capability, the

drain current should be normalized to the same gate capacitance.

The AC test structures of composite and conventional transistors are fabricated in the

same 0.13-Clm CMOS technology mentioned in Section 3.4. All transistors have the same channel

width of 44.4 Clm. Figure 3-12 shows the layout of four of these AC structures. The ground pads

(GND) are shared by two adj acent structures here due to the area efficiency consideration. The

gate capacitance are extracted from the measured S-parameters. An AC open structure is also

measured to remove the impact of the capacitance associated with the pad frame and metal con-

nections. An HP8510C network analyzer and an AC probe station are employed in these measure-

ments.

The measured gate capacitances of the composite and conventional 1.2-V MOS transistors

are plotted in Figure 3-13. It is shown that the gate capacitance of composite transistors has

approximately linear dependence on the length of the SDR sub-transistor. The y-axis intercept of


I=


I=
gtfi~t????











Composite
160 c
v 1.2-V

y-interdept 200
m120







80




1.2-V and 33-Vtranitos





gate overlap in the o SDR sub-transistor. An hsitreti sepcte ige hahegt

Fiue31.Maue aecapacitance of the convetioal .2- transistor slbldbytetinl in t Figure 3-13
The composte-22 f MSD sbtransistor h s gt capaciane tof 157 ofF Thisi compaed tiotat
of tecnvetioal .34-m long 3.3-V MO transistors i h ne fFgr -3 ttesm

witthe copoie-2transistor has about 34% higher gatel capacitance thanatd it the 3.3su-Vtransis-o n


tor (117 e fF) The widveth ofa thcmost-22 transistor, ashoubld b te oringly 74% of thtote 3.3-V





transistor to have the same gate capacitance. For instance, a 7.4-Clm wide composite-22 transistor

should have the same gate capacitance of 26 fF as a 10-Clm wide minimum-length 3.3-V transis-

tor.









3.6 Composite-22 MOS Transistors for Level Shifter Application

A set of composite MOS transistors with varying length SDR sub-transistors has been

investigated in the preceding sections. Composite structures consisting of two sub-transistors in

series have higher current drive capability compared to the 3.3-V transistor because the effective

threshold voltages are lowered. At the same time, these composite transistors can handle higher

voltage swing at the drain nodes because the SDR sub-transistors sustain a large portion of the

drain-to-source voltage and provide the voltage protection for the TN sub-transistors.

When the SDR sub-transistor is shorter, the voltage drop across it becomes smaller and the

drain current of the composite structure becomes higher. On the other hand, the voltage protection

from the SDR sub-transistor tends to be diminished and drain voltage tolerance of the composite

structure is lower.

As discussed, the composite-22 MOS transistor consisting of a 0. 12-Clm long TN sub-tran-

sistor and a 0.22-Clm long SDR sub-transistor is considered to be well suited for use in

1.2-to-3.3-V level shifter circuits. The thin-oxide layer in the composite-22 structure limits the

maximum gate-to-source voltage to only 1.2 V, and this still fulfills the voltage swing requirement

in the case of 1.2-to-3.3-V level shifter circuits. At the drain side of composite-22 transistor, the

breakdown voltage is comparable to that of a conventional 3.3-V transistor. The composite-22

MOS transistors are ready to replace the conventional 3.3-V MOS transistors (M15/M17 in

Figure 3-1) to improve the speed performance.

The composite-22 MOS transistor has the same drawn length as the conventional 3.3-V

transistor. Its threshold voltage is only 0.46 V, which is 0.26 V lower than that of the 3.3-V tran-

sistor (0.72 V). When M15 and M17 in Figure 3-1 are replaced by the composite-22 MOS transis-

tors, the gate overdrive (VGS-VT = 1.2-VT) is increased by about 54%.
















6.0 -w 1.2-V, W= 13. 1 Clm, CSS= 26fF

V s=0.9V

4.0-




2.0 12 VGs=1.2V
VGs=0.6 GS- G =0.9
G =0.

0.0 O O
0.0 1.0 2.0 3.0

VDS (V

Figure 3-14. ID-VDS characteristics of the composite-22, conventional 3.3-V and 1.2-V
MOS transistors when gate capacitances (Cgg) are the same.


Considering the difference in unit gate capacitance for the composite-22, the conventional

3.3-V and 1.2-V MOS transistors, ID-VDS curves in Figure 3-14 are compared at different widths.

The transistor widths are 7.4, 10.0 and 13.1 Clm, respectively, so that the gate capacitance, or the

capacitive loads to the preceding inverter stage, are all 26 fF. Biased at the same gate-to-source

voltage (VGS), the composite-22 MOS transistor can deliver more than 2 times the current of

3.3-V transistor.

In Figure 3-15, ID-VGS curves of the composite-22 and conventional 3.3-V transistors are

also compared. Once again, all drain currents were normalized by keeping the gate capacitance at

26 fF. In the log scale plots, the normal subthreshold behaviors are observed at both VDS=3.3 V

and VDS=0.05 V. At VDS=3.3 V, the off-state current for composite-22 is comparable to that of the











10-2


-6.0
10-4


10-6
1 4.0

~108 I,


10-10 1,
I MOcomp-22, VDS=3.3V 2.0
Mcomp-22, VDS=0.05V
10-12 I
S3.3-V, VDS= 3.3V
I 3.3-V, VDS=0.05V
10-14 I O 0 0.0
0.0 1.0 2.0 3.0

VGS O/

Figure 3-15. Comparison of ID-VGS curves for the composite-22 and conventional
3.3-V MOS transistors in linear and logarithm scales at fixed gate
capacitance, with VDS = 3.3/0.05 V.

1.2-V transistor at VDS=1.2 V (~1nA/Clm). However, it is almost 4 decades higher than that for

the 3.3-V transistor. Because the number of I/O transistors used in an integrated circuit is limited,

the higher leakage should be tolerable. The linear scale plots show once again that ID of the com-

posite-22 transistor is at least 2 times that of the 3.3-V transistor. The improvement of IDS at low

VGS is even more dramatic due to the lower threshold voltage of composite transistor. With its

drain connected to 3.3 V and gate swept from 0 V to 1.2 V, it is clearly shown by the shaded area

in Figure 3-15 that the composite-22 transistor can deliver larger current than the conventional

3.3-V transistor. This higher drain current at given gate capacitance suggests that the 3.3-V drive

transistors in the 1.2-to-3.3-V level shifter circuit (M15/M17 in Figure 3-1) can be replaced by the

composite-22 transistors to reduce the propagation delay.









3.7 Low-to-high Level Shifter Speed Performance

In the previous section, the composite-22 and the minimum length conventional 3.3-V

MOS transistors are studied. Based on the DC and AC properties from measurements, the pro-

posed composite-22 transistor has higher drive current than the 3.3-V transistor. Cadence Spectre

simulator is used in this section to estimate the improvement in the speed performance for the

1.2-to-3.3-V level shifters when the 3.3-V drive transistors are replaced by the composite-22 tran-

sistors.

First, modeling of SDR-26 MOS transistors is necessary. Based on the conventional 3.3-V

transistor's model, we built a model file to approximately describe the behavior of composite-22

transistor by modifying several parameters, such as gate oxide thickness (tox), threshold voltage

(vth0), mobility (uO) and saturation velocity (vsat). The simulation results match the 2.68 times

the drain current, and 1.34 times the gate capacitance of the conventional 3.3-V transistors at

fixed channel width. These modifications reflect the improvement of current drive capability dis-

cussed in Section 3.4. 1 and the increase of gate capacitance measured in Section 3.5, respectively.

The same 1.2-to-3.3-V level shifter structure shown in Figure 3-1 is used for simulations.

Figure 3-16 shows the two simulated versions. Version A is the level shifter circuit using the con-

ventional 3.3-V nMOS transistors as the drive transistors (M8A M9A). Two conventional 3.3-V

pMOS transistors (M10A M11A) are used as the cross-coupled load. The 3-stage conventional

1.2-V inverter chain (Al through A3) preceding the level shifter generates the input signal, whose

shape is independent of the number of propagation stages. The 3-stage conventional 3.3-V

inverter chain (A5 through A7) is also used following the level shifter to maintain the same capac-

itive loading of each stage Tau98. In version B, all components are the same as version A, except

that the two drive transistors (Mgn/M9B) are replaced by the composite-22 MOS transistors in









1.2-V inverter 3.3-V inverter


o3.


M10A~


3V | conventional 3.3-V


1


r -- -3.3V output output


p level shifter B
1.2-V circuitry 3.3-V circuitry


Figure 3-16. Schematics of level shifter circuits in simulation. Version A uses
conventional 3.3-V MOS transistors as drive transistors; Version B uses
composite-22 MOS transistors as drive transistors.

Order to tolerate the 3.3-V swing and deliver higher drain current to the following stage. The

width of composite-22 transistors in version B are only 74% of their counterparts in version A, so

that the stages A3 and B3 can see the same capacitive loads.

Figure 3-17 shows the input and output waveforms of both level shifters for the pull-down

and pull-up cases. In either Figure 3-17 (a) or Figure 3-17 (b), the input signals in those two ver-



















































Figure 3-17. Comparison of the composite-22 and conventional 3.3 -V MO S transistors
used in 3.3-to-1.8-V level shifters. (A) propagation delays in pull-down
case (zn), (B) propagation delays in pull-up case (zp).

sions are the same and overlaid on each other. This is because, in both versions, the drive transis-

tors (M8A and M8B, M9A and M9B) give the same capacitive load to the preceding stages. The

same input signals with 1.2-V swing are delayed differently and shifted to output signals with










Table 3-4. Speed performance comparison of level shifters using the composite-22 and
conventional 3.3-V MOS transistors

version A version B delay
(conventional 3.3-V) (composite-22) improvement

pull-down delay (ps) znA = 124 znB = 82 34%

pull-up delay (ps) zpA = 165 zpB = 93 44%

fall time (ps) zfA = 221 IfB = 119 46%

rise time (ps) zrA = 194 zrB = 103 47%



3.3-V swing. The time differences of output signals for both pull-down and pull-up cases directly

show the improved speed performance of the level shifter implemented by using the compos-

ite-22 transistors over the conventional 3.3-V transistors.

The data extracted from the waveforms are listed in Table 3-4, including the pull-down

propagation delay (zn), pull-up propagation delay (zp), fall time (zf), and rise time (zr). A propaga-

tion delay improvement of around 40% can be expected from this 1.2-to-3.3 -V level shifter circuit

by using the composite-22 MOS transistors instead of conventional 3.3-V transistors. This speed

improvement is obtained without any process modifications. In addition, there is no change in the

circuit configuration, and it is convenient for circuit designers to use.

3.8 Summary

Level shifters are crucial for digital CMOS I/O interface circuits to translate different volt-

age levels back and forth. The level shifting requires extra stages and introduces additional propa-

gation delay, which should be limited to minimum. In a low-to-high level shifter, the drive

transistors have to be realized by using thick-oxide high-voltage MOS transistors to stand the high

voltage swing at the drain nodes. The gate nodes of drive transistors, however, only need to han-









dle low voltage swing. These requirements provide opportunities for use of the SDR thick-oxide

MOS transistors.

The composite MOS transistor structure using the SDR thick-oxide MOS transistor is pro-

posed. With its asymmetric voltage characteristics from gate to drain, the composite transistor is

well suited as the drive transistors in the low-to-high level shifter circuits, since it can deliver

higher drain current than the conventional thick-oxide high-voltage MOS transistors.

The composite transistors using two different foundry CMOS processes are discussed in

this chapter. First, the composite-18 structure was implemented in a 0.18-Clm CMOS foundry

technology. The potential reliability issues at the internal shared diffusion region is discovered,

and the criteria to monitor this problem is discussed. In the second implementation using a

0.13-Clm CMOS technology, the measurements show that a 0.22-Clm long SDR thick-oxide MOS

transistor in series with a conventional thin-oxide transistor (composite-22) is the optimal combi-

nation for use in the 1.2-to-3.3-V level shifter circuits. This composite-22 transistor can deliver

more than 2 times the drain current as the conventional thick-oxide transistors, while still having

sufficient breakdown voltages and protecting the TN sub-transistors for 3.3-V swing at the drain

node. This current enhancement translates to about 40% reduction in the propagation delay.

The use of composite MOS transistors in the low-to-high level shifters to improve the

speed performance is feasible in the 0.18-Clm and 0.13-Clm CMOS technologies. This concept

should be applicable in other more advanced technologies. In a more general term, this study on

low-to-high level shifters successfully demonstrates another application of the SDR thick-oxide

MOS structure, namely in digital I/O circuits. Further scaling of the thick-oxide MOS transistors

should be feasible to optimize the performance of digital I/O circuits.









CHAPTER 4
RADIO FREQUENCY POWER AMPLIFIER APPLICATION

4.1 Introduction

4.1.1 CMOS RF Power Amplifiers

A typical CMOS RF transceiver is shown in Figure 4-1. Along the transmitting path, the

power amplifier (PA) is the final active stage for delivering a sufficient amount of power through

the T/R switch and antenna to the propagation media. Because the RF signal level becomes the

largest level at this point, the design considerations and methods for PA are different from those

for other RF blocks for small signals.

In the design of CMOS power amplifier circuit, the output power level and power effi-

ciency are two of the most important specifications. To deliver high power level signal, typically

the power amplifier itself becomes the most power-consuming block in the RF transceiver. Poor

power efficiency will cause self-heating problem, and large power consumption will shorten the

battery life for portable wireless communication devices. These performance will eventually be

limited by the power transistor characteristics, such as breakdown voltage, current limitations and

maximum power dissipation [Smi98].



Antenna

PATransmit~ter I n


Synthesizer Bsbn
Circuits
LO

I ] Rece iver



Figure 4-1. Simplified block diagram of a typical RF transceiver.









In CMOS power amplifier design, two types of power efficiency are widely used: drain

efficiency (DE) and power added efficiency (PAE). Their definitions are as below:

Pu
DE = ot ,(4-1)
Supply

Pou P. P P .u~ nj=D
PAE = ou n ot 1 i E1 1.(4-2)
Pspl P PG
suplysupply ouu

Psupply is the power consumption from the DC supply, Pin is the input power, Pout is the power

delivered the output load and Go is the power gain of the PA. If the power gain of the amplifier

(Go) is high enough (which is not always true for PA's final stage), DE and PAE are close to each

other.

4.1.2 Classification of CMOS RF Power Amplifiers

Power amplifiers are classified according to their mode of operation, i.e. the bias condition

for power transistors and the nature of output network. Traditionally, there are several categories

of power amplifiers: class A, AB, B, C, D, E, F, etc.

Class-A power amplifiers are biased such that its conduction angle is 3600. The amplifier

operates linearly over the full input and output ranges. The output is the sinusoidal waveform of

the same frequency as the input, and the output amplitude is a linear function of the input ampli-

tude. Among all PA's categories, class-A power amplifier has the highest linearity and the poorest

efficiency. This type of amplifiers always consumes DC power even though there is no output sig-

nal. If the power amplifier is biased so that the conduction angle is between 1800 and 3600, it is

referred to as class-AB. If the amplifier output is a linear function of the input over half (1800) of

the input waveform, then it is categorized as class-B. This mode of operation can have a greater

efficiency than class-A due to the reduced conduction angle. If the linear conduction angle is less









than 1800, it is a class-C power amplifier. From class-A to class-C power amplifiers, there is

increasing distortion in the output waveform, or the linearity of the amplifiers becomes worse.

A main source of power amplifier inefficiency is the dissipation in the power transistors.

Like a class-A amplifier, the current follows continuously through the MOS transistor while the

VDS is non-zero. If VDS can be made to zero while the current flows, there will be no power dissi-

pation in a transistor and the drain efficiency (DE) will approach 100%. This is the basic idea

behind class-D, E, and F power amplifiers.

For power amplifiers under these categories, the power transistors usually operate in a

switching mode, and cooperate with the output network to reduce or eliminate the non-zero over-

lap between current and voltage waveforms at the drain node. The input signal waveform is not

preserved, just the frequency is. Therefore, these categories are also referred to as non-linear

power amplifiers.

4.1.3 Thick-Gate-Oxide MOS Transistors in Linear Power Amplifiers

Some wireless communication systems, like EDGE, WCDMA transceivers, have very

strict linearity requirements, therefore the linear power amplifiers are necessary. Class-A or AB

power amplifiers are often useful in these applications. However, as mentioned, the efficiency is a

serious concern. When the saturation voltage (VDSsat) is considered, the maximum drain effi-

ciency for a class-A power amplifier is [Smi98]:



(DE)max = 1 VV 2 (4-3)
supply

For the case using the 3.3-V thick-oxide MOS transistor, Vsupply is 3 V and VDSsat is about 0.2 V,

therefore (DE)max is up to 44%. On the other hand, for the case of the 1.2-V thin-oxide MOS tran-

sistor, VDSsat doesn't change much and it takes more percentage of the Vsupply (1 V). The effi-









ciency drops to 32%. For such power amplifier applications, high voltage MOS transistors are

preferable.

The composite MOS transistor (proposed in Chapter 3) has the high voltage handling

capability like a conventional 3.3-V MOS transistor, while its current drive capability is better

than the 3.3-V transistor when VGS is limited up to 1.2 V. In this chapter, we will examine the

high frequency capability of the composite-22 MOS transistor amplifiers. The better frequency

response could lead to higher power gain (Go), therefore, increasing the PAE of a power amplifier

in Equation 4-2.

4.2 AC Characteristics of Composite-22 MOS Transistor

4.2.1 fT and fmax

fT (cut-off frequency) and fmax (maximum frequency of oscillation) are often used as the

figures of merits for high frequency performance of a transistor. The small-signal model of a

MOS transistor is shown in Figure 4-2. Aside from the well-known lumped elements, two extra

elements are included. The charging resistance (ri) accounts for the distributed effect along the

channel, and its value is about 1/(5gm). The gate resistance here is split into an intrinsic part (Rg,i)

and an extrinsic part (Rg,e)



RgI Rg,i Cgd rd


I "s Cs
9dsl Cdb
Ti 9 m~gs


intrinsic transistor



Figure 4-2. Small-signal lumped microwave network model of a MOSFET.









fT is defined as the frequency where the extrapolated current gain (h21) decreases to unity,

as expressed below:


h21 o F = 1, (4-4)



where, ii is the input current and io is the short circuit output current. For this model, the cut-off

frequency can be written as [Man99]


gm gm
f = (4-5)
T 2 2~ 2nCo
2 g (mr.C gs Cgd


Here, it is assumed that IgmriCgs Cgd < Cg, and Cg = Cgs+Cgd. fT has simple definition and is

easy to measure. However, fT does not provide the frequency response information for the transis-

tor power gain.

fmax is the frequency where the maximum available gain (MAG) of a transistor is equal to

unity. It also represents the highest frequency that a transistor could possibly oscillate in a circuit.

The maximum available gain (MAG) is the power gain obtained by a device when the input and

output ports are conjugately matched to the impedance of the source and load simultaneously.

This figure of merit provides a fundamental limit on how much power gain one can achieve from

a device at a given frequency. Under the simultaneous conjugate match condition,

Eg = Tin" =MS, L = out" =ML, the maximum available gain can be written as

[Gon97] :


MAG _S1K-.(4-6)


where K stands for Kurokawa's stability factor and can be calculated by










K = S SZS, S,, (4-7)
2 S21I S12I

When K is less than 1, MAG is not defined. This is the typical case that a transistor operates at

lower frequency range and is potentially unstable. When operating frequency is sufficiently high,

K becomes greater than 1 and MAG can be calculated from the S-parameters.

Another power gain called the unilateral power gain (Gmax) was also proposed in [Mas54]

to estimate the fmax. According to this definition, additional feedback network is introduced to the

transistor of interest so that there is no reverse transmission of signals from the output to the input

of this combined network (the transistor of interest, and the additional feedback network). For a

two-port network, the unilateral power gain (Gmax) is described by the y-parameters [Gup92]:


1 Y21 Y122
G =-x .(4-8)
max 4 (Re(yll ) Re(y22))- Re(y21) Relyl12)

Furthermore, by applying the transistor parameters accounted by the model shown in Figure 4-2,

the unilateral power gain (Gmax) can be expressed as


(fT/)
G (4-9)
ma 4g, i (ds + m gd/8 g 41 gds

It is reasonable to assume that (Rg + r.) gd < Rg g -m C d/C for RF applications, and

the unilateral power gain (Gmax) can be further simplified as

fT
G (4-10)
max2
8Ig, i gd 1









Ideally, Gmax has the dependence of 20dB/dec on frequency, and fmax can be simply expressed as

Equation 4-11



f t(4-11)
max s~ng, i Cgd


Interestingly, the frequency at which Gmax attains the unity is also the frequency at which

the MAG of the device becomes unity. Therefore, both power gains discussed above will be used

to estimate fmax-

4.2.2 Measurements for fT and fmax

The AC test structures of composite-22 and conventional 3.3-V thick-gate-oxide MOS

transistors discussed in Section 3.5 are used for fT and fmax measurements. As discussed, an AC

open structure is also measured to remove the capacitance associated with the pad frame and

metal connections. An HP8510C network analyzer and an AC probe station are employed. The

measurement frequency is up to 26GHz, which is limited by the network analyzer.

In Figure 4-3, hl21 2, MAG and Gmax extracted from the S-paramneters are plotted in a log-

arithm scale. For the composite-22 MOS transistor, the gate and drain are biased at 0.8 and 3.0 V,

respectively. For the conventional 3.3-V MOS transistor, the gate and drain are biased at 2.0 and

3.0 V, respectively. For MAG curves, each one has a turning point. For frequencies below this

turning point, the K factor in Equation 4-7 is less than 1, thus the calculated MAG is invalid.

When the frequency is higher than this turning point, K becomes greater than 1, therefore the

extracted MAG is valid. Interestingly, the valid portions of MAG curves merge with the Gmax

curves, and lead to the same fmax values.













20 ---~

Sh21 2 Up
E 15 pont



IK>1) '
cy :MAG iK<1)



composite-2 :



0.4 1.0 10 40
Frequency (GHz)

Figure 4-3. Measured current gain (h21), maximum available gain (MAG) and
unilateral power gain (Gmax) for the composite-22 and conventional 3.3-V
thick-gate-oxide transistors.


The extracted fT and fmax for multiple samples are shown as function of gate bias condi-

tion in Figure 4-4. If VGS is below 1.2 V, the composite-22 transistor has higher fT than the 3.3-V

MO S transistor. fT of the composite-22 transistor reaches the peak value of 15 GHz at VGS=0.8 V.

However, this advantage is overturned when VGS of the 3.3-V transistor is increased above 1.2 V.

fT of the 3.3-V transistor reaches the peak value of 19 GHz at VGS=2.0 V. fma of the compos-

ite-22 transistor reaches peak value of 29 GHz at VGS=0.8 V. While fmax of the 3.3-V transistor

reaches 37.5 GHz at VGS=2.0 V.

In general, the composite-22 MOS transistor has lower fT and fmax than the conventional

3.3-V transistor. However, this is not true if we consider the practical bias conditions at the tran-

sistor gate for an amplifier. When the overdrive (VGS-VT) is set to around 0.25 V, for instance, the




83












VT r VDs = 3.0V
40 -v comp p.5o



N 30 4
Imax




10 t



II I composite-22


0.0 1.0 2.0 3.0

Vs (V)

Figure 4-4. fT and fmax for the composite-22 MOS transistor and conventional 3.3-V
thick-gate-oxide transistors. Threshold voltages for both transistors are
labeled by VTcomp and VT3.3V. Gate overdrives of 0.25 V are also labeled.

composite-22 transistor has ~ 20% higher fT and comparable fmax compared to the conventional

3.3-V transistor. With better frequency response, the composite-22 MOS transistor may slightly

increase the gain of amplifiers (Go) and PAE as calculated in Equation 4-2. However, the

improvement by using composite-22 transistor is expected to be marginal, or even none for some

bias conditions.

There is another consideration of using composite-22 transistors in conventional analog

amplifier circuits. The intrinsic gain (gm-ro) is one of the key parameters to characterize amplifier

transistor, and it specifies the highest voltage gain that can be possibly provided by a transistor.

Compared in Figure 4-5 are gm, output resistances (ro) and intrinsic gain of the compos-

ite-22, conventional 3.3-V and 1.2-V transistors. The overdrives (Vois-VT) for all transistors are












c~Composite-22
S3.3-V


20 -







10


0.0 1.0 2.0 3.0

3.0
c~Composite-22
C:~ 1 .2-V

c 2.0







0 .0


0.00L 1.0 2.0 3.0
40
c~Composite-22
S3.3-V


00

E 20







0.0 1.0 2.0 3.0

Vs (V)


Figure 4-5. gm, output resistance (ro) and intrinsic gain of the composite-22 and
conventional 3.3-V/1.2-V transistors when the overdrives (VGS-VT) are
around 0.25 V.









kept around 0.25 V. The transistor widths are scaled so that the drain currents for all transistors are

about the same. The composite-22 transistor has similar gm, but about 1/2 output resistance of the

conventional 3.3-V transistor. This low output resistance degrades the intrinsic gain, as well as

fmax, of the composite transistor. The intrinsic gain of composite transistor is about 1/2 that of the

3.3-V transistor. In addition, the 1.2-V transistor has only about 1/2 output resistance compared to

the composite transistor. However, the higher gm of 1.2-V transistor compensates so that its intrin-

sic gain is comparable to that of the composite transistor. Finally, the composite transistor doesn't

show superior characteristics in conventional analog amplifier applications.

4.3 Summary

In this chapter, use of the composite-22 MOS transistor in RF power amplifier circuits is

examined. At first, the RF power amplifier circuit of a transceiver and its large signal characters

are introduced. Output power level and efficiency are the two of the most important specifications

for power amplifiers. Power amplifiers in different classes need compromises between the linear-

ity and power efficiency. PA design in certain applications prefer high-voltage (thick-oxide) MOS

transistors due to the high breakdown voltages.

The composite-22 MOS transistor can handle the same drain voltage swing like the con-

ventional 3.3-V MOS transistor. fT and fmax are measured for the device's speed characteristics. In

general, the composite-22 MOS transistor is not superior to the conventional 3.3-V transistor.

When considering the practical gate bias conditions, the measurements show that the compos-

ite-22 MOS transistor has slightly higher fT and comparable fmax compared to the conventional

3.3-V transistor. Additionally, the composite transistor shows lower intrinsic gain than the 3.3-V

transistor. The composite transistors demonstrate only marginal, or even no advantages over the

3.3-V transistors for RF and analog amplifier circuits.









CHAPTER 5
TRANSMIT/RECEIVE SWITCH APPLICATION

5.1 Introduction

A high performance transmit/receive (T/R) switch is a key building block of the radio fre-

quency (RF) front end of time-division duplexing (TDD) communication systems. In this chapter,

the potential use of thick-gate-oxide SDR MOS transistors in RF switch circuits in order to

improve the performance is discussed.

5.1.1 CMOS Transmit/Receive Switches

A simplified block diagram of a TDD RF transceiver is shown in Figure 5-1. Both trans-

mitter and rec eiver are connect to an antenna (ANT) through a si ngl e-p ol e-doubl e-through

(SPDT) T/R switch. Either a transmitter or a receiver is on one at a time. In receive mode, a T/R

switch connects the antenna to the receiver path, which usually starts with a low noise amplifier

(LNA) or a filter. The signal collected by the antenna which is very weak goes through the switch

and is fed into the LNA. The loss of T/R switch increases the noise figure of LNA by the same


Antenna






ocA

N T/R switch






Receiver Transmitter


Figure 5-1. T/R switch in a typical TDD RF transceiver.









amount. Therefore, the T/R switch should have low loss (<1 dB) to reduce its impact on receiver

sensitivity. In transmit mode, the T/R switch connects the antenna to the transmit path or power

amplifier (PA). The T/R switch should handle high power signal without excessive distortion and

loss. Obviously, high power handling capability and low loss are desirable for the T/R switch.

Also, the T/R switch must have sufficiently high isolation to block the transmit signal from being

fed into the input of receiver.

Key figures of merit for a T/R switch include insertion loss (IL), isolation, return loss, and

power handling capability. The insertion loss measures the power loss through the switch when

the switch is on. At off-state, the switch loss is characterized by isolation. By measuring two-port

S-parameters of a switch, insertion loss and isolation can be expressed as Equation 5-1, or 5-2 in

dB.


IL, isolation=- or (5-1)




(IL)dB, (isolation)dlB = -201og( S21 ). (5-2)

Return loss measures how much power is reflected back from any ports of the switch. This param-

eter describes how severe the mismatch at the port is and can be expressed using Equation 5-3, or

5-4 in dB.


return loss = ,or (5-3)



(return loss)dB = -201og( S,, ). (5-4)


Power handling capability of a switch is usually represented by its 1-dB compression point

(PldB), or the input referred one (IPldB). PldB is defined as the output power where the power









gain of switch drops from the small signal power gain by 1 dB. Higher PldB denotes a higher

power handling capability. This parameter is fundamentally determined by the non-linearities of

the switch. Another parameter commonly used to characterize the linearity of a switch is the

third-order intercept point (IP3 or input referred one IIP3). This parameter is defined as the power

level at which the linearly extrapolated output power of desired signal and that of the third order

intermodulation component intersect. The input referred IP3 is denoted as IIP3.

Using CMOS technology, potentially all RF front end and baseband circuits can be inte-

grated into a single chip. This has been the motivation of tremendous effort for finding ways to

implement high performance RF building blocks in bulk CMOS technologies. However, the com-

mercial RF switch modules are implemented almost exclusively in GaAs technology. This has

impeded the fully exploiting the low cost potential of CMOS solutions.

Mobility of electrons in silicon is only ~ 1/6 of that in GaAs [Sze02]. Compared to GaAs

devices, CMOS transistors have higher channel sheet resistance (pch), which is directly related to

the switch's insertion loss. The insertion loss increases with higher channel resistance (Rch). And

the channel resistance is equal to pch W.However, the channel width (W) can not be arbitrarily

increased because a larger source/drain area increases the capacitance. This increases the switch

loss because of the associated substrate resistance.

Combatting the substrate loss is another design requirement in RF CMOS switch design.

To lower the insertion loss in CMOS technology, channel length (L) needs to be scaled down.

Since the parasitic capacitance is also reduced with scaling, the insertion loss improves

[HuaF01b]. However, technology scaling inevitably reduces the transistor breakdown voltage

which is already relatively low. This makes it even more difficult to achieve high power handling

performance .









In such a junction isolated silicon technology, one more challenge in designing high power

switches is the possibility of forward biasing the source/drain-to-body junction diodes during

large voltage swings at the input and output of the switch [Lar98]. These forward biased junctions

will distort the output signal, thus limit the power handling capability (IPldB). This may also

inj ect minority carriers into the body of the nearby transistors and trigger latch-up. Even after

applying DC bias at source/drain to increase the reverse bias of the those junctions, the power per-

formance of CMOS switches is still limited to around 20 dBm.

The 30-dBm RF signal, for instance, corresponds to a ~ 20-V peak-to-peak voltage swing

at the input and output ports of a T/R switch with termination of 50-02 load. If directly applied to

MOS transistor nodes, such high voltage swing could easily forward bias the junctions of MOS

transistors, and even damage the transistors. In CMOS processes, it is extremely difficult to

deliver power in excess of 30 dBm through a T/R switch.

5.1.2 Techniques to Improve Power Handling Capability

With the continuous speed improvement of technologies from generation to generation,

bulk CMOS radio-frequency (RF) transceivers and power amplifiers have proven to be produc-

tion worthy. To date, an RF CMOS block which has not found wide spread use is a transmit/

receive (T/R) switch [HuaF01la, HuaFO4]. Key reasons for this are that bulk CMOS switches have

limited power handling capability as measured by input referred 1-dB compression point (IPldB)

and relatively high insertion loss (IL). The power handling capability can be improved while

slightly degrading IL by connecting the body nodes of NMOS transistors through high resistance

[Li03, OhnO4]. By making the high impedance connection to the body using a parallel LC tank,

IPldB of 28.5 dBm and IL of 1.5 dB have been achieved at 2.4 GHz [Tal04]. It has been suggested

that similar performance should be achievable by using NMOS transistors in isolated p-wells of









triple well CMOS processes while eliminating the need for the LC tank which consumes a signif-

icant area and makes the switch narrow band. However, to date, the highest IPldB reported for

switches using isolated p-wells is only 20 dBm with IL of 1.1 dB at 5.8 GHz [Yeh05].

The work presented in this chapter demonstrates the techniques for increasing IPldB of T/

R switches well beyond 20 dBm using NMOS transistors in isolated p-wells, while reducing the

insertion loss degradation. The techniques are used to demonstrate a 900 MHz single-pole-dou-

ble-throw (SPDT) switch with IPldB of 31.3 dBm, and IL's of 0.5 and 1.0 dB in transmit (TX) and

receive (RX) modes. Isolation is better than 29 dB up to 1 GHz. The techniques are also utilized

to demonstrate a 2.4 GHz SPDT switch with IPldB of 28 dBm, and IL's of 0.8 and 1.2 dB in TX

and RX modes. Isolation is better than 24 dB up to 2.4 GHz. The switches are fabricated using the

transistors of UMC 130-nm mixed mode CMOS process with a thicker gate-oxide layer in order

to reliably support the required voltage swing.

5.2 CMOS T/R Switches Using Sub-Design-Rule Transistors

5.2.1 Design of SDR T/R Switches

The switch circuit schematic is shown in Figure 5-2. It is formed with a series transistor

M4 (Width = 925 Clm) on the TX leg and 3-stack series transistors M6-M8 (Width = 1115 Clm) on

the RX leg, and 3-stack shunt transistors M1-M3 (Width = 370 Clm) on the TX node, and a shunt

transistor M5 (Width = 370 Clm) on the RX node. The gate and body nodes of all transistors are

biased through 10-kaZ non-silicide polysilicon resistors (R's in Figure 5-2). TX and RX nodes as

well as the sources of Ml and M5 are biased at 3V to improve the power handling capability

[HuaF01la]. The switches were turned on and off by varying the control voltage (GTX, GRX in

Figure 5-2) from 2 to 6 V [HuaF01a]. The switch can be controlled using a circuit similar to that

in [Poi03] and the control voltages can be generated using a voltage doubler [Poi03].











GRX


GTX


ANT


R

; M6


I RR
R M3 R I~~J I
M5 GTX
G RX M2
-R R

M1V
C2



Figure 5-2. Simplified schematic of the T/R switch with 3-stack sub-design-rule
(SDR) length transistors.

The stacked shunt transistors M1-M3 and series transistors M6-M8 are used to sustain

higher voltage swings and therefore to improve the power handling of T/R switch [McG91,

OhnO4, Sch90]. Stacking, however, significantly increases the IL ofRX leg. Based on the discus-

sions in Chapter 2, it is possible to reduce the channel length of thick-gate-oxide transistors below

that permitted by the design rule to lower the on-resistance thus reducing the IL degradation.

To exploit this, all the transistors were implemented using 3.3-V transistors with a

sub-design-rule (SDR) channel length [Xu05]. The drawn length of SDR transistors in this switch

design is 0.26 Clm instead of 0.34 Clm required for 3.3-V transistors. DC measurements indicate its

on-resistance is reduced by ~ 25%. Since the gates of 3.3-V and 1.2-V transistors are simulta-

neously formed, the SDR channel length transistors can be formed without any process modifica-

tions. This switch does not utilize impedance transformation to increase IPldB [HuaFO4] and the

peak-to-peak voltage the switch must handle is ~20 V at 30-dBm input power.





















-well /\ p>-well /t \ p-well

~\de~e~p-n-well_ ,'~ : de~e~p-n-well ,I I 1 d\ce~ep-n-well_ ,'

p-ubstrate

Figure 5-3. Cross-section of the 3-stack transistors in the SDR T/R switch.


Each NMOS transistor of the switch is located in an isolated p-well (Figure 5-3) to allow

the body node to float and follow the RF signal thus increasing IPldB [Li03,OhnO4,Tal04,Yeh05].

This is similar to the phenomenon that happens in switches fabricated in GaAs as well as silicon

on sapphire (SOS) and silicon on insulator (SOI) processes [Miy95,Joh97,YamK99,TinO3] To

ensure the isolated p-wells are not AC grounded through the series combination of

p-well-to-deep-n-well and deep-n-well-to-p-sub state j unction capacitances (~ 1 pF), the sub state

resistance is increased by using the p-well implantation block (width of ~20 Clm), using a small

number of substrate contacts (4 per transistor), and adding a 1-kaZ resistor in series with the sub-

strate contacts as shown in Figure 5-3.

Even after applying these measures, the body nodes of MOSFET's are not perfectly iso-

lated. Figure 5-4 shows a more detailed schematic for the stacked transistors M1-M3. The shunt

paths from body to AC ground consisting of C,,g's due to the series combination of

p-well-to-deep-n-well and deep-n-well-to-p-sub state j unction capacitances, and sub state resis-

tances (Rsub1 Rsub3) make the voltage swing unevenly distributed among these 3-stack MOS-











V -
DG3 10kaZ r parasitic
4 I Cwell ;shunt

VSG3M + paths
VD2
GRX VDG Rsb


VDG1 D Rsub2
10kaZ
ICwell


VD1
VV, Rsub1
C1k~






Figure 5-4. Detailed schematic of the 3-stack transistors (M1-M3) including the
parasitic shunt paths.

FET's. These shunt paths reduce the voltage swing across the drains and gates of M2 and Ml,

while increasing the swing across the drain and gate of M3. This is clearly seen as the grey curves

in Figure 5-5(a) which shows the simulated drain-to-gate voltages of M1-M3. The input power

level is 30 dBm. In general, the top transistors M3 and M8 sustain higher gate-to-body and

drain-to-gate voltages than the bottom transistors Ml and M6.

Building on the feed-forward technique proposed for GaAs T/R switches [Miy95], the

switch in this work incorporates feed-forward metal capacitors (C3=C4=50 fF and C5=C6=150

fF) between the drain and body nodes, and between the drain and gate nodes of M3 and M8. The

extra capacitances (lX case) reduce the impedance across the gates and drains of M3 and M8, and











4.5





o


0.5




-1.5
0


T/2 T
Time


13.0


-2.0



-7.0


T/2 T
Time


Figure 5-5.


Voltage distributions for the 3-stack SDR switches with and without the
feed-forward capacitors, when the input power is 30 dBm. (A) Drain-to-
gate voltages (VDGl~VDG3) for transistors M1-M3. (B) Voltage
waveforms at different nodes along the TX shunt path (M1-M3).









help the gate nodes follow the high swing nodes more closely. This makes the voltage swing at

TX and ANT nodes more evenly distributed among the 3 stacked MOSFET's.

Also shown in Figure 5-5(a) is the simulated drain-to-gate voltages of M1-M3 with lX

feed-forward capacitors (C3-C6). With the help of feed-forward capacitance, the voltage drop

across M3 is reduced by about 1 V, while those across M2 and Ml sustain larger portions of the

total input voltage. Figure 5-5(b) shows the simulated voltages of drain nodes for M1-M3 once

again at input power of 30 dBm. The maximum voltage including the 3-V DC bias is 13 V.

Despite this, the peak voltage drops across gate oxide (Figure 5-5(a)) and between drains and

sources (Figure 5-5(b)) are ~ 3.5 V to ensure reliable operation when feed-forward capacitors are

used. This modification of voltage distribution among M1-M3 enables the stack as a whole to

withstand a larger voltage swing before any one is turned on or damaged. The feed-forward metal

capacitors (C3-C6) are formed using metal layers 1 through 3 and incorporated as part of the tran-

sistor layout.

Simulated drain-to-gate and source-to-gate peak voltages for M1-M3 (VDGl? ~ VDG3 >

VSGl? ~ VSG3P) versus different feed-forward capacitance are plotted in Figure 5-6. The values of

feed-forward capacitors (C3-C6) are varied among 0, lX (C3=C5=50 fF and C4=C6=150 fF), 2X

and 3X. It shows again that, when the feed-forward capacitors (lX) are added, the drain-to-gate

peak voltages of transistors M1-M3 are closer to each other, therefore, the voltage swings are

more evenly distributed. The peak voltage of M3 is reduced from over 4.6 V to 3.8 V, which is

tolerable for the 3.3 -V thicker gate oxide transistor. The drain-to-gate peak voltage of M3 (VDG3P

in Figure 5-6) and the resulting stress can be further reduced by increasing the feed-forward

capacitances.
























1.0 i.
OX 1X 2X 3X
Feed-fonrward Capacitance

Figure 5-6. Impact of feed-forward capacitance (OX, lX, 2X and 3X) on the peak
voltages across transistors M1-M3 (VDGl?~VDG3P, VSGl?~VSG3 -~

Larger feed-forward capacitance, however, increases the portion of total voltage swing

applied across the gate oxide layer of Ml, and eventually, Ml becomes the most stressed transis-

tor among the three stacked transistors. There is an optimal value for the feed-forward capacitor to

evenly distribute the voltage across the 3-stack transistors. Figure 5-6 suggests that the voltage

distribution is better balanced when the capacitance is doubled (2X case). If the capacitance is tri-

pled (3X case), the peak voltage across Ml (VSGlP) becomes larger than that of M3 (VDG3 )-

Compared to the switch without feed-forward capacitance, the simulations suggest about 1.5 and

2.3 dB increases in IPldB at 900 MHz for the lX and 2X cases.

A potential side effect of increasing C3-C6 is the degradation of insertion loss resulting

from the increases of losses due to input mismatch and through the transistor stack. Simulations

show that IL at 900 MHz increases by 0.03 and 0.08 dB for the lX and 2X cases. An optimal

feed-forward capacitor values should be between lX and 2X. In this work, 900-MHz switches


S4.0


3.0
o

0. 2.0









with no feed-forward capacitors and that with C3=C4=50 fF and C5=C6=150 fF (lX case) are

fabricated and compared in Section 5.2.2.

The impedances of polysilicon resistors in Figure 5-2 are almost constant with frequency

up to several GHz, while the impedances of parasitic capacitors are frequency dependent. At suf-

ficiently low frequencies, the floating-body resistances are not high enough compared to the

impedances of capacitive voltage divider structures. Therefore, the voltage division among

M1-M3 and among M6-M8, as well as power handling capability is expected to be weakly depen-

dent on frequency. For the 900 MHz switch, the simulated power handling capability is almost

flat from ~ 650 MHz to ~ 2.4 GHz. In this range, IPldB varies by +/- 1 dB, demonstrating the

broadband characteristics.

Lastly, two 20-pF bypass capacitors (Cl and C2) connect the sources of Ml and M5 to AC

ground, while blocking DC current flow. The inter-metal shuffled metal capacitor structure

[Sow0 1] consisting of metal layers 1 to 8 is used here for high chip area efficiency.

5.2.2 900-MHz SDR T/R Switch

A T/R switch operating at 900 MHz using such 3-stack SDR transistors (as shown in

Figure 5-2) was implemented in the UMC 130-nm mixed mode triple-well CMOS technology. A

die photograph of the circuit is shown in Figure 5-7. The active area is about 300 Clm by 3 80 Clm

or ~ 0. 11 mm2. Including the additional area of voltage doubler circuitry with a 200-pF capacitor

(< 0.05 mm2), the SDR switch is still almost 3.5 times smaller than the area of the switch using an

LC-tank connection to the body node [Tal04].

Three GS/SG probes with 150-Clm pitch were used at the RF signal ports for all measure-

ments. A 6-pin DC probe was used to provide bias and control signals. One of the three ports was

terminated with a 50-02 load through an AC coupling capacitor in the measurement setup.
































650clm

Figure 5-7. Die photo of the 3-stack SDR T/R switch.

Two-port S-parameters are measured using an HP8510C network analyzer. Figure 5-8

shows the measured IL of the SDR CMOS T/R switch. At 900MHz, IL's for TX and RX legs are

0.5 and 1.0 dB, respectively. A T/R switch using only 2-stack 0.34-Clm length MOSFET's instead

of 3-stack 0.26-Clm length SDR transistors is also measured for comparison. The length of 0.34

Clm is the minimum allowed by the design rules for 3.3-V transistors. Its IL of RX leg is ~0.2 dB

higher than that for the switch using 3-stack SDR channel length transistors. Isolation and return

loss of SDR CMOS T/R switch as shown in Figure 5-9 are better than 29 dB and 20 dB at 900

MHz, respectively.

Linearity measurements were carried out using an HP-E4421B signal generator together

with an external power amplifier and an HP8563E spectrum analyzer. Figure 5-10 shows the mea-

surement results of SDR CMOS T/R switch at 900MHz. IPldB at TX mode is about 31.3 dBm,













2.0 2-stack of 0.34-Cpm 3.3-V transistors


S1.5 R
f~io





0.0
0.5 1.0 1.5 2.0 2.5 3.0
Frequency (GHz)
Figure 5-8. Measured insertion loss of the SDR switch using 3 stack SDR transistors,
compared to that of the switch using 2 stack 0.34-Clm length transistors.

which is the highest ever reported for bulk CMOS T/R switches. As mentioned, TX and RX nodes

as well as the sources of Ml and M5 are biased at 3V, and the switches were turned on and off by

varying the control voltage from 2 to 6 V. Compared to IPldB for the switch using 2-stack


40




E 30


O 2


40




30 c
O


10 L*


* 10


0.5 1.0 1.5 2.0 2.5 3.0
Frequency (GHz)
Figure 5-9. Measured isolation and return loss for the SDR T/R switch using 3 stack
SDR channel length transistors.











40~ -1 *4

20 _8e :I I -120

E~ Eo

-20 w/o cap Ell I -20
o vbias=0V E |I
-40 t3rdorder II I -l -40
I a II
-60~ d l EllI -60
~I III
-80 10 20 30 40 -8

Pin (d Bm)

Figure 5-10. Linearity measurement results of the 3-stack SDR switch with source/
drain biased at 3 and 0 V, and with (lX) and without the feed-forward
capacitors.


0.34-Clm length MOSFET's, this value is about 5 dB higher. These clearly illustrate the benefits of

using SDR transistors. IIP3 of the SDR CMOS switch is 42 dBm. When the source and drain

nodes are biased at 0 V, IPldB drops to 26 dBm due to forward biased junctions. The linearity of

the SDR CMOS T/R switches with and without the additional feed-forward capacitors are also

compared in Figure 5-10. The additional capacitors improve IPldB for the SDR switch by about

1.3 dB.

Finally, to examine the reliability characteristics, the SDR CMOS T/R switch is stressed

around IPldB (31.3 dBm) for 10 hours. The stress was carried out for both conditions when ANT

pad is connected to a 50-02 load and when it is left open to examine the effects of antenna mis-

match. The measured S-parameters showed no difference before and after the stresses. This

experiment verifies that the 3-stack switch circuit using SDR MOS transistors can successfully

handle more than 31-dBm RF signal without reliability problems.









5.2.3 2.4-GHz SDR T/R Switch

In the 900-MHz T/R switch, 3-stack transistor structure was chosen and the power han-

dling capability was significantly improved. On the other hand, the necessary stacking limited the

insertion loss performance at the switch's RX leg. The 900-MHz switch demonstrated reasonable

insertion loss (< 1 dB) only up to ~ 1 GHz. There is design trade-off between IPldB and IL, or

alternatively between IPldB and operating frequency because IL increases with frequency. If

power handling requirement of a T/R switch can be relaxed to some extent, fewer number of

stacked transistors can be used so that IL performance can be improved. Furthermore, such a T/R

switch can potentially operate at higher frequencies while keeping the same acceptable IL perfor-

mance. To further investigate such design trade-off, a 2.4-GHz T/R switch for wireless LAN

(WLAN) applications using SDR transistors has been implemented and presented in this section.



IG RX
G ANT
Ro R R

TX M4f AN M7 M6 RX


R R R RR
R R
M2 ~I
~M5 GTX
G RX
-R R

M1 VC2 -



Figure 5-11. Simplified schematic of the T/R switch for 2.4-GHz applications using
2-stack SDR transistors without feed-forward capacitors.

































Figure 5-12. Die photo of the T/R switch for 2.4-GHz applications using 2-stack SDR
transistors without feed-forward capacitors.


By using these techniques discussed in Section 5.2.1, an SDR T/R switch operating at 2.4

GHz was designed and implemented in the same CMOS foundry process. Figure 5-11 shows the

simplified schematic of this 2.4-GHz T/R switch. In this case, 2-stack SDR transistors (M1-M2

and M6-M7) are chosen to compensate the increased insertion loss along the RX leg at 2.4 GHz,

however, with its power handling capability compromised. The die photo of such T/R switch cir-

cuit is shown in Figure 5-12, and its active area is about 300 Clm by 300 Clm or ~ 0.09 mm2

Once again, the two-port S-parameters are measured using an HP8510C network analyzer

and shown in Figure 5-13. It clearly indicates that the 1L at RX leg is shifted down by stacking

only two SDR transistors and this switch yields acceptable performance even at higher frequen-

cies. The measured insertion loss at 2.4 GHz is about 0.8 and 1.2 dB for TX and RX legs, respec-

tively. Its isolation performance at 2.4 GHz is better than 24 dB. Large-signal performance is also










characterized as plotted in Figure 5-14. Measured at 2.4 GHz, its IPldB is greater than 28 dBm,

which is ~ 3dB lower than that of the 3-stack switch circuit.


0.0 L


-10


0.5 1.0 1.5 2.0 2.5 3.0

Frequency (GHz)

Figure 5-13. Measured insertion loss and isolation of the 2-stack SDR switch for
2.4-GHz applications.


h
E
m


o
a


-10
O


10 20 30
Pin (d Bm)


Figure 5-14. IPldB measurement of the 2-stack SDR switch working at 2.4 GHz.









In this design, power handling capability is sacrificed for better loss performance, or for

higher operating frequency. Using SDR MO S transistors, a T/R switch with better combination of

power and loss performances is achieved for 2.4-GHz wireless application. The insertion losses of

0.8 and 1.2 dB for TX and RX legs at 2.4 GHz are the lowest reported to date for a bulk CMOS

switch with IPldB greater than 25 dBm. It is also noted that this 2.4-GHz SDR T/R switch does

not use feed-forward capacitance for transistors M2 and M7. Based on the experience of the

3-stack T/R switches in Section 5.2. 1, IPldB of this 2-stack switch is expected to increase further

by about 1 dB when properly sized feed-forward capacitors are used. The performance of this

2.4-GHz and other T/R switches discussed are summarized and compared in Table 5-1.


Table 5-1. Performance summary of CMOS T/R switches.

3-stack 3-stack 2-stack
T/R 2-stack work work work
SDR w/ SDR w/o SDR w/o
switches 0.34-Cpm [OhnO4] [Tal04] [Yeh05]
cap cap cap

Frqeny 0.9 0.9 0.9 2.4 5.0 2.4 5.8
(GHz)

IL TX 0.5 0.5 0.5 0.8 1.0 1.5 1.1
(dB) RX 1.0 1.0 1.2 1.2 1.4 1.6 1.1

Return
>20 >19 >19 >13 >17 >12
Loss (d B)
Isolation
>29 >29 >31 >24 >22 >17 27
(d B)

IPdB 31.3 30 26.5 28 22.7 28.5 20
(dBm)

IIP3 (dBm) 42

chip area
0.11 0.11 0.09 0.09 <0.1 0.56 0.03
(mm2>









5.3 Discussion

The output power of these SDR T/R switches is normal functions of the available input

power, as long as the input power is kept below IPldB. When the nominal input power level is suf-

ficiently high, however, the output power of switches abruptly drops and then saturates with the

available power from source. This effect sets the limit on the switch power handling capability.

This behavior is reversible in that when the input power is lowered again, the output power recov-

ers. The measurement results for the 900-MHz SDR T/R switch (Figure 5-10) are magnified in

detail and shown in Figure 5-15.

This output power level drop has weak dependence on the bias conditions of drains/

sources, p-wells and deep n-wells. As shown in Figure 5-16, the measured leakage current

through the vertical drain/source-p-well-n-well-p-sub path is only on the order of 1 mA, which is

much smaller compared to that flowing through the switch transistors (peak current of ~ 200 mA).


32

31

30

E 29 -/


o" 27 I

26~ ml

-I
25
25 26 27 28 29 30 31 32 33
Pin (d Bm)

Figure 5-15. Detail of linearity measurement results around 1-dB compression point for
the 3-stack SDR switch. Output power drops abruptly if the nominal input
power is above certain point.










10.0


8.0







2.0

0.0

S2 4 6 8 10 12
Voltage (V)

Figure 5-16. Measured DC current through the n-p-n-p sandwich structure from source/
drain, through body to p-substrate.

Furthermore, cutting off all the shunt transistors (M1-M3 and MS) from the circuit using a

focused ion beam had almost no effect on the power drop. The only change that significantly

affected the power level at which the drop occurred is leaving the RX node floating instead of ter-

minating with a 50-02 load after cutting off all the shunt transistors. Under this condition, the mea-

sured power drop occurs at ~5-dB higher input power level. The low current through the vertical

drain/source-p-well-n-well-p-sub path and the strong dependence on RX node termination sug-

gest that the power drop is not caused by latch-up phenomenon.

Instead, we believe that the cause is the breakdown of 3-transistor stacks (M1-M3 and

M6-M8). The breakdown characteristics of a single SDR transistor is measured and shown in

Figure 5-17. It is noted that the breakdown voltage decreases with VGS. When the voltage swings

at TX and ANT nodes are small, the capacitively coupled voltage swings at the gates, thus VGS,

are also small. Therefore, each SDR transistors can tolerate higher voltage swing without con-



















E 0.6







0.0 2.0 4.0 6.0 8.0
Vs (V)


Figure 5-17. Measured breakdown characteristics of a single SDR transistor.

ducting measurable current. When the input voltage swing is sufficiently increased, the coupled

voltage swing at gate weakly turns on the devices and simultaneously lowers the breakdown volt-

age. This clamps the output voltage and power at a reduced level. An associated abrupt imped-

ance change also causes power mismatch at the switch input and contributes to the sudden output

power drop. This can be proved by observation that a sudden power change at the switch's input

port occurs at the same time when the output power abruptly drops. Interestingly, when the avail-

able power from source is then reduced, the measured output power follows a different path

(labeled by stars in Figure 5-15). This is because the breakdown voltage is still low and mismatch

is sever until the RF signal power, thus the gate-to-source voltage swing, is low enough. Then the

breakdown voltage increases and the output power follows the input linearly again.

A positive consequence of this power drop and clamping is that when the switch is

severely mismatched, the resulting high voltage will be clamped, thus protecting the switch from

permanent damages.









5.4 Summary

A T/R switch is usually the first building block in a TDD (Time Division Duplex) radio

system. Its performance is crucial to both the transmitter and receiver operations. The key param-

eters to characterize a CMOS T/R switch have been introduced. The current techniques to

improve the performance and the inherent process limits of switches implemented in CMOS tech-

nologies have been discussed.

In this chapter, the focus of our investigation is the use of the SDR NMOS transistors in

radio frequency T/R switch circuits. Design techniques for improving the power handing capabil-

ity of bulk CMOS T/R switches to above 30 dBm while maintaining acceptable insertion loss

have been demonstrated using the UMC 130-nm mixed-mode triple-well CMOS technology.

Stacked sub-design-rule (SDR) channel length NMOS transistors with a thicker gate oxide layer

are used to improve the power handling capability while keeping IL low. Use of a thicker gate

oxide layer of 3.3-V transistors in SDR transistors enables ~3.5-V drop across the transistors

without reliability concerns. Isolated p-wells and p-well blocks are used to improve the float-

ing-body effect.

At 900 MHz, a switch incorporating 3-stack SDR transistors located in isolated p-wells

exhibits IPldB of 30 dBm. By using feed-forward capacitors, IPldB is increased to 31.3 dBm. The

power handling capability is limited by a new mechanism. A decrease of drain-to-source break-

down voltages of the TX shunt and RX series stacked transistors due to un-intentional turning-on

of the transistors by RF input is suggested as the likely cause for a sudden output power drop. The

switch achieves 0.5-dB and 1.0-dB insertion losses in the transmit and receive modes. This switch

has 0.2 dB lower insertion loss in receive mode and 5 dB higher IPldB in transmit mode compared

to that for a switch using 2-stack design rule compliant 3.3-V transistors. At 2.4 GHz, a switch









utilizing 2-stack SDR transistors exhibits IPldB of 28 dBm. The insertion losses for transmit and

receive modes are 0.8 and 1.2 dB, which should be acceptable for 802.11b and g applications.

Lastly, this work suggests that integration of a bulk CMOS T/R switch for cellular applications is

a realizable goal by using thick-gate-oxide SDR MOS transistors.









CHAPTER 6
HIGH-Q MOS VARACTOR APPLICATION

6.1 Introduction

In preceding chapters, use of the sub-design-rule (SDR) MOS structures in transistors for

different circuit applications and their benefits have been demonstrated. Actually, an SDR MOS

structure is naturally a high quality varactor. This is because thick-gate-oxide layer has smaller

gate capacitance, and furthermore, using sub-design-rule channel lengths for MOS varactors can

reduce the series resistance. In this chapter, the performance of SDR MOS varactor structures are

presented and compared to those of conventional thin-gate-oxide MOS varactors.

6.1.1 CMOS Voltage-Controlled Oscillator

Local oscillators (LO) generate periodic output signals for both transmitter and receiver

(LO signals in Figure 4-1). Furthermore, LO frequency should be adjustable but precisely con-

trolled for different channels according to the wireless communication system design. Such func-

tion is usually realized using a voltage-controlled oscillator (VCO) in a phase-locked loop.

For many reasons, a differential implementation of the oscillator is usually chosen

[Por00]. A typical VCO in a CMOS technology is shown in Figure 6-1. These two cross coupled

MOSFETs (M1-M2) provide the negative resistance, and the L-C tank makes the circuit resonate

at the desired frequency. In order to control the oscillation frequency, varactors (Cvar) are included

as part of the L-C tuning tank.

In general, higher quality factor (Q) for the L-C tank is preferred in VCO design, because

(1) the output noise shaping function is sharper, (2) power dissipation of circuit is lower, and (3)

noise inj ected from MOSFETs is reduced [Raz0 1]. Noise performance and power consumption

requirements are very strict in a wireless communication system. Therefore, much efforts have










VDD

Vbias 3N 1






Vout+ ~Vout-
var, var


M1 ~IM2




Figure 6-1. Schematic of a typical differential CMOS voltage-controlled oscillator.


been expended to improve the voltage-controlled oscillator (VCO) design, and more specifically

to realize a high-Q and low parasitic LC-tank.

Q of inductors increases with operating frequency (QL ~ coL/Rs, where L is inductance, Rs

is series resistance) so that this is less of concern when operating frequency is increased. Unfortu-

nately, Q of capacitors/varactors is inversely proportional to frequency (QC ~ 1/coCRs, where C is

capacitance, Rs is series resistance). Studies have shown that, at frequencies lower than 10 GHz,

the Q of L-C tanks is usually limited by the on-chip inductors. However, above 20 GHz and in the

millimeter-wave range, Q of capacitors/varactors becomes more problematic for the overall L-C

tank [Cao06a, Cao06b].

6.1.2 MOS Varactors

Conventionally, on-chip varactors have been implemented with p-n junctions under

reverse bias or MOS capacitors in accumulation/depletion regions. The latter structure has dem-









onstrated higher Q factor and wider tuning capability over the former one when the voltage sup-

ply is scaled down [Sve99, Por00]. Therefore, MOS varactors are often used in VCO circuits.

The cross-section of a typical MOS varactor is shown in Figure 6-2. The top and bottom

plates are formed by silicided polysilicon and n-well, and are separated by the same high quality

gate oxide layer as that of MOSFET's. Since the gate oxide layer is very thin, the MOS varactor

has a high intrinsic capacitance-area ratio, especially when it is biased in the accumulation mode

[Hun98].

This varactor structure is very similar to an n-channel MOSFET with the exception of

being fabricated in an n-well instead of the normal p-substrate. This choice was made to eliminate

the parasitic pn-junction capacitances at source and drain that would otherwise limit the tuning

range. An alternative structure using a p-channel MOSFET in a p-well/substrate has a lower qual-

ity factor due to lower carrier mobility.

The operation principle of varactors is to change the capacitance of a MOS structure by

varying the gate voltage, which changes the operation region among accumulation, depletion, and

inversion [Soo98, Mol02]. By applying positive voltage between the gate and n-well, the Si sur-

Metal12



Metall
Poly





n-well

p-substrate

Figure 6-2. Cross-section of MOS varactor structures.









face is accumulated and the varactor capacitance equals the gate oxide capacitance. If the applied

voltage is reversed, the Si surface layer is depleted and the series capacitance decreases. The max-

imum capacitance per unit area of the varactor corresponds to a heavily accumulated surface and

equals the unit area gate oxide capacitance (Cox 8080x/tox). On the other side, the minimum value

(Cd) is reached when the voltage between the gate and n-well is negative and beyond the thresh-

old voltage. In this case, an inversion layer is formed under the gate. At low frequencies (~ k
this effect brings the value of capacitance close to the gate oxide one. However, at high frequen-

cies where the varactor is supposed to operate in VCOs, this effect is not seen and the capacitance

remains at its minimum value. The difference between Cox and Cd indicates the capacitance tun-

ing capability for varactors.

Ideally, total varactor capacitance can be varied between the maximum and the minimum

as in Equations 6-1 and 6-2.


Cmax = Cox Atot= Cox -W -L N (6-1)


Cmin = Cd -Atot= Cd -W -L -N (6-2)

Here, W and L are the finger width and length, and N is the total number of fingers.

The series resistance Rs of the varactor usually is dominated by n-well and gate resis-

tances, and can be calculated as following [Hun98]:

1 1 11 L
s 3 2 2 N (On"W poy



12 W -L -N (R unn, L + R, poly W ), (6-3)









where, Ronn and ROpoly are the sheet resistances of n-well and polysilicon gate, respectively. The

factor 1/3 accounts for the spreading effect, while two 1/2 factors account for the double-sided

contacts for both poly gate and n-well.

The minimum varactor quality factor (Qmin) is obtained when the capacitance is the larg-

est. From Equations 6-1 and 6-3, Qmin is expressed as

1 12
Qmi (6-4)
min RsCmax a Co(Rnn, L2 + R oly W2


Obviously, Qmin is a monotonic function of L (or W) and it is preferable to use minimum dimen-

sions for both L and W to increase Q.

Another important parameter for a varactor is its capacitance tuning range (y). Without

losing the generality, y can be defined as


C -C -C C C
y= max mm max mm ox dx10,(6-5)
(C + C )/2 C C,
max mim max o


where y is independent of dimension parameters L (or W). Higher y suggests better capacitance

tuning capability, and in turn, wider VCO frequency tuning range.

Until now, parasitic capacitances associated with gate overlap and interconnect layers

have not yet been taken into account. However, those parasitics can be comparable to the varactor

capacitance itself. Therefore, a parasitic term Cpar(W, L, N) should be added to Equations 6-1 and

6-2. In a typical varactor layout, L is much smaller than W. The gate overlap capacitance and the

fringe capacitance between the gate and metal connections dominate in Cpar and they both are

proportional to W N. The overlap area capacitance between metal2 and poly gate is relatively

smaller. Even thought Cpar should be a complicate function of W L and N in general, it is still a









good approximation to assume Cpar(W, L, N) ac W N. Now, Equations 6-1 and 6-2 should be

modified as below,


Cmax = Cox Atot + Cpar(W, L, N)= Cox W L N + P W N, (6-6)


Cmin Cd Atot + Cpar(W, L, N)= Cd W L N + p W N (6-7)

Here, p is a constant representing the total parasitic capacitance per unit width.

Accordingly, Equations 6-4 and 6-5 should also be modified:

12
Qmin ,~,,L ~o.W)Cli~ (6-8)




max mm ox d
Ye x 100 %. (6-9)
max C +P
ox L

From Equation 6-8, it is noted that Qmin is no longer a monotonic function of L. With a given W,

Qmin reaches the peak value when L satisfies the Equation 6-10.


Ron Co 3 Ron
2 -~u L + -u ~L2 = W2 (6-10)
O~poly O [poly

Also, the capacitance tuning range (y) has dependence on L as suggested in Equation 6-9. When L

decreases, more contribution of total capacitance will come from parasitics, which is independent

of varactor gate voltage. In turn, this additional parasitic capacitance will degrade y.

6.1.3 Sub-Design-Rule MOS Varactors

As suggested by the Equation 6-4 or 6-8, the thick-gate-oxide MOS structure inherently

has higher quality factor due to thicker gate-oxide layer (tox) and lower gate capacitance (Cox).

The capacitance area density is smaller compared to the thin-gate-oxide MOS structure. However,

this is not a serious issue for circuits operating above ~ 1 GHz.









The Q factor can be further improved if the SDR thick-gate-oxide MOS structures are

employed to reduce the channel length. In addition, there are no reliability issues for SDR MOS

structures in varactor applications because the "source" and "drain" are always tied together to

form the bottom plate connection. However, decreasing channel length L will degrade the varac-

tor tuning range (y). Therefore, the trade-off of Q factor and the varactor tuning range (y) is an

important issue in high-Q varactor design. In the next section, the difference and possible advan-

tages of thick-gate-oxide SDR MOS varactors over its conventional thin-gate-oxide counterpart

are discussed.

6.2 High Frequency Characteristics of SDR MOS Varactors

6.2.1 Device Structure

One-port AC test structures of thick-gate-oxide (TK) SDR and conventional MOS varac-

tors are fabricated in the same 0.13-Clm CMOS technology as mentioned in Section 3.4.

Figure 6-3 shows a layout and an equivalent circuit model of those varactors. The drawn finger




Lmetal
poly
contact

Rmetal


I ~RgateI


I Cpar sCva I,
m etalII
d iffusionII

varactor



Figure 6-3. Layout and equivalent circuit model of a MOS varactor.









channel lengths include 0.12, 0.18, 0.24 and 0.3 Clm (SDR varactors), and 0.36 Clm (conventional

TK varactor). All the drawn finger width (W) is 0.9 Clm. Besides those, one more conventional

TK varactor of 5.0 Clm by 1.0 Clm is also fabricated to illustrate the better tuning range case. To

investigate the difference of SDR varactors over thin-gate-oxide (TN) varactors, another group of

TN varactor structures with the same dimensions listed above are also built.

As discussed before, a pad frame structure with no device is fabricated as "AC open" in

order to de-embed the capacitance of the pad frame and metal connections. Again, a structure

with device replaced by a wide metal line is also fabricated as "AC short" to de-embed the extra

series resistance and inductance introduce by metal connection (Rmetal and Lmetal in Figure 6-3).

A network analyzer (HP8510C) is employed for S-parameter measurements.

6.2.2 Measurements and Discussions

All thick-gate-oxide and thin-gate-oxide varactor test structures are characterized. As an

example, Figure 6-4 only shows the extracted capacitance and quality factor at 24 GHz versus

gate voltage for TK-24 and TN-24 varactors with channel length at 0.24 Clm. The TN-24 varactor

demonstrates wider tuning range than the TK-24, while the quality factor can be as low as ~ 20.

The TK-24 varactor, using SDR channel length, can increase the quality factor to above 100.

Qmin measured at 24 GHz and tuning range y for different test structures are plotted

together in Figure 6-5. With a decreasing channel length, y for both TK and TN varactors

decreases relatively smoothly. Also, as expected, TK structures have smaller tuning range than

TN ones. y values shift down from ~ 65% for TN to ~ 40% for TK structures. On the other hand,

measured Qmin increases rapidly in both TK and TN cases, when varactor channels become

shorter. It is noted that using SDR channel can improve Qmin of TK varactors even more dramati-

cally. At a length of 0.36 Clm, the TK varactor has Qmin of 48, which is 3 times that of the TN var-










200


60


-160



-120 p,
--

-80



-40



-0


40




20 '


Gate Voltage (V)


Figure 6-4.


C-V and Q-V characteristics of
thin-gate-oxide (TN) varactors with L


the thick-gate-oxide
=0.24 Clm.


(TK) and


100

-1
80 c









40


120


0 0.2


0.4 0.6 0.8
Channel Length (Cim)


Figure 6-5.


Measurement data of Qmin and y vs channel
(TK) and thin-gate-oxide (TN) varactors.


length for thick-gate-oxide









actor. When the length is shorten to 0.24 Clm in SDR region, TK varactor's Qmin can jump to

above 100. It is improved by almost 5 times compared to the corresponding TN varactor. It is

noted that, at extreme high Qmin situation, the series resistance (Rs) is only several ohms and

much smaller than the reactance of capacitor. This makes it difficult to extract reliable Qmin for

those SDR varactors with the channel length below 0.24 Clm

Those four lines drawn in Figure 6-5 are calculated Qmin and y from Equations 6-8 and

6-9. P is extracted from the measurement results by data fitting. The 1st-order approximation fits

most measurement results well. Interestingly, the data points at length of 1.0 Clm significantly

deviate from the calculated plots. The reasons include that, for these structures, the gate connec-

tions are single-sided, the channel width of 5 Clm rather than 0.9 Clm is used and the metal connec-

tions have no overpass above the poly gate. There are more series resistance and less percentage

of parasitic capacitance compared to predictions from the Equations 6-8 and 6-9, therefore, data

show lower Qmin and higher tuning range.

Equation 6-8 also suggests that, at very small L, term R lyW2 may be comparable or

exceed Renw L2, and Qmin may drop when L is further reduced. For this 0.13-Clm CMOS pro-

cess, the critical channel lengths calculated by Equation 6-10 are ~ 0.1 and ~ 0.08 Clm for TK and

TN varactors, respectively. These lengths are below the lithography limit, therefore, shrinking

channel length can always improve Qmin of MOS varactors.

Qmin and tuning range are two major parameters for varactor design. To clearly show the

trade-off between them, curves of Qmin versus tuning range y, once again, are plotted in

Figure 6-6. TN varactors have superior tuning range to the thicker ones. However, their Qmin are

well below 40. By using SDR varactors, Qmin can be dramatically improved. The design space is










120 7

100-


,E mnin1

S60_


40 -



20

0 20 40 60 80 100
Tuning Range y (%)

Figure 6-6. Varactor design space formed by Qmin and tuning range y.

extended to region of higher-Qmin-lower-y combination. Fortunately, the degradation of y is rela-

tively small in this space.

So, tuning range can be traded off for high-Q performance in SDR varactors. For example,

such varactors can be used in a dual-conversion receiver [Li03] operating around 50 GHz [Che06,

Luo05]. The incoming signal is down-converted twice by using two VCOs. The first VCO oper-

ates at higher but Eixed frequency, so the wanted channel will not be centered around the first

intermediate frequency (IFl). However, the second VCO has a wide tuning range and will guaran-

tee that the wanted channel is centered around Eixed frequency (IF2 or DC) by the second

down-conversion. SDR varactors, which have limited tuning range but superb quality factor fit

well to the first VCO application. The significantly improved Qmin of this type of varactors can

improve the total L-C tank Q and result in better phase noise performance and lower power con-

sumption. Even though the margin for the parasitic capacitance due to the core transistors should









be reserved, it is believed that the varactor capacitance tuning range (y) of ~ 40% is sufficient for

the first VCO to compensate the process, temperature and supply variations.

6.3 Summary

In this chapter, use of the SDR MOS structures as varactors in VCO circuits is studied to

investigate the feasibility of exploiting higher Q components. A series of SDR varactors are fabri-

cated and characterized. Their performance is compared to that of the conventional

thin-gate-oxide MOS varactors.

Qmin and tuning range (y) are very important parameters for varactor design. However,

Qmin of thin-gate-oxide MOS varactors is limited at frequencies above ~ 20 GHz. Qmin-y design

space for MOS varactors can be greatly expanded by using thick-gate-oxide SDR structures. A

combination of extreme high Qmin and modest tuning range (y) is achieved and its possible appli-

cations in VCOs is discussed. Using SDR varactors can improve the phase noise and power con-

sumption performances of VCO's operating at frequencies above 20 GHz.









CHAPTER 7
SUMMARY AND SUGGESTION FOR FUTURE WORK

7.1 Summary

Conventional thick-gate-oxide MOS transistors are often part of standard offering in com-

mercial CMOS technologies. They have many advantages, such as higher breakdown voltage,

higher power handling capability and lower drain leakage current. Compared to the

thin-gate-oxide transistors, low-current low-speed characteristics limit the usage and the perfor-

mance of thick-gate-oxide transistors in many circuits. Because the lithography limit in these pro-

cesses is significantly lower, the high voltage performance can be traded off to improve their high

frequency performance.

A goal of this research has been to find approaches to improve the performance of

thick-gate-oxide MOS transistors without modifying the existing foundry technologies. It has

proven the sub-design-rule (SDR) channel length transistors is an easy and effective way to

improve the characteristics of transistors with thick-gate-oxide in different circuit applications.

The dissertation began with the exploration of using SDR transistors in digital I/O circuits.

In Chapter 2, a single SDR transistor was investigated as the starting point. Its application in a

3.3-to-1.8-V level shifter circuit using a 0. 18-Clm CMOS foundry technology is studied. A series

of thick-oxide SDR MOS transistors are compared to the conventional 3.3-V MOS transistors.

The measurements suggest that the 0.26-Clm long SDR MOS transistor (SDR-26) can deliver 1.28

times the drain current as the conventional one, while maintaining sufficient breakdown voltages

to tolerate the signal swing at the gate and drain nodes. The conventional 3.3-V drive transistors

in the 3.3-to-1.8-V level shifter can be replaced by 25.6% wider SDR-26 transistors to provide

60% more drain current. In simulations, this current enhancement translates into a nearly 20%

reduction in the propagation delay.









Following that, the composite MOS transistor, consisting of a SDR thick-oxide MOS tran-

sistor and a conventional thin-oxide transistor, was proposed in Chapter 3. Its low threshold volt-

age makes it well suited as the drive transistors in the low-to-high level shifter circuits. In a

0. 13-Clm CMOS technology, the measurement results show that a 0.22-Clm long SDR thick-oxide

MOS transistor in series with a conventional thin-oxide transistor (composite-22) is the optimal

combination for use in the 1.2-to-3.3-V level shifter circuits. This composite-22 transistor can

deliver more than 2 times the drain current as the conventional thick-oxide transistors, while still

having sufficient breakdown voltages and protecting the TN sub-transistors for 3.3-V swing at the

drain node. This current enhancement translates to about 40% reduction in the propagation delay.

The study has successfully identified the circuit benefits of using the SDR MOS transis-

tors or the composite MOS transistors in level shift circuits. This concept of further shrinking

thick-gate-oxide transistors is also applicable to other more advanced technologies. In general,

use of the SDR MOS transistors provides another way to exploit the scaling of CMOS technolo-

gles.

Building on their digital I/O circuit applications, the role of SDR transistors in RF/analog

applications is investigated. In Chapter 4, use of the composite MOS transistors in RF power

amplifier (PA) circuits was examined. For power amplifiers, the output power level and the power

efficiency are the two key specifications. Compromise between the linearity and power efficiency

are necessary for power amplifiers in different classes. High-voltage (thick-oxide) MOS transis-

tors are preferred for certain PA designs.

The composite-22 MOS transistor can handle the same drain voltage swing like the con-

ventional 3.3-V MOS transistors. fT and fmax of the devices are measured. In general, the compos-

ite-22 MOS transistor is not superior to the conventional 3.3-V transistor. When considering the









practical gate bias conditions (0 < VGS-VT < 0.25 V), the measurements show that the compos-

ite-22 MOS transistor has higher fT and comparable fmax than the conventional 3.3-V

thick-gate-oxide transistors. At best, the improvements ofRF power amplifier gain and efficiency

are expected to be marginal. The lower intrinsic gain of the composite transistor limit its applica-

tions in analog amplifier circuits.

Use of the SDR MOS transistors in radio frequency T/R switch circuits was the research

focus of Chapter 5. In this chapter, design techniques for improving the power handing capability

of bulk CMOS T/R switches to above 30 dBm while maintaining acceptable insertion loss have

been demonstrated using the UMC 130-nm mixed-mode triple-well CMOS technology. Stacked

sub-design-rule (SDR) channel length NMOS transistors with a thick-gate-oxide layer are used to

improve the power handling capability while keeping IL below 1 dB. Use of a thick-gate-oxide

layer of 3.3-V transistors in SDR transistors enables ~3.5-V drop across the transistors without

reliability concerns. Isolated p-wells and p-well blocks are used to improve the floating-body

effect.

At 900 MHz, a switch incorporating 3-stack SDR transistors located in isolated p-wells

exhibits IPldB of 30 dBm. By using feed-forward capacitors, IPldB is increased to 31.3 dBm. A

decrease of drain-to-source breakdown voltages for the TX shunt and RX series stacked transis-

tors due to un-intentional turning-on of the transistors by RF input is suggested as the likely cause

for a sudden output power drop. The switch achieves 0.5-dB and 1.0-dB insertion losses in the

transmit and receive modes. This switch has 0.2 dB lower insertion loss in receive mode and 5 dB

higher IPldB in transmit mode compared to that for a switch using 2-stack design rule compliant

3.3-V transistors. To demonstrate the trade-off between power handling capability and switch

loss, a 2.4-GHz switch utilizing 2-stack SDR transistors is built. It exhibits IPldB of 28 dBm and









its insertion losses for transmit and receive modes are 0.8 and 1.2 dB, respectively, compared to

0.5 and 1.0 dB for the switch with 31.3-dBm IPldB. This 2.4-GHz T/R switch should be accept-

able for 802.11lb and g applications. This work suggested that integration of a bulk CMOS T/R

switch for cellular applications no longer appears to be an unrealizable goal.

In Chapter 6, use of the SDR MOS structures as varactors is discussed. The SDR MOS

varactors have higher quality factor (Q) than thin-gate-oxide varactors. A series of SDR varactors

were fabricated and characterized. Their performance benefits in VCO applications were explored

in comparison to the conventional thin-gate-oxide MOS varactors.

The minimum Q (Qmin) and tuning range (y) are important parameters for varactor design.

However, Qmin of thin-gate-oxide MOS varactors is limited at frequencies above ~ 20 GHz. The

Qmin-Y design space for MOS varactors can be greatly expanded by using thick-gate-oxide SDR

structures. A combination of extremely high Qmin and modest tuning range (y) is achieved and its

possible applications in VCOs are discussed. This can be used to reduce high frequency (> ~20

GHz) VCO phase noise and power consumption.

7.2 Suggestion for Future Work

Based on the study presented in this dissertation, additional works on SDR MOS struc-

tures are suggested.

7.2.1 Application in high power T/R switches

This study demonstrated that it is feasible to build CMOS T/R switches with power han-

dling capability above 30 dBm. It is difficult but will be interesting to improve this performance

even higher. One possible way is to stack more SDR transistors in the high voltage paths. The

optimal SDR channel length should be experimentally investigated.










GRX


ANT


Figure 7-1. Additional nodes to connect feedforward capacitors in a 4-transistor stack
of SDR T/R switches.


More number of stacking transistors means more flexibility for the voltage division

among them. Feedforward capacitance technique should still improve the T/R switch power han-

dling capability. There are additional nodes to add the feedforward capacitors. For example,

capacitors can be connected to the drain node of the second top transistor in the stack (C31i, C32 in

Figure 7-1), and the source node of the bottom transistor in the stack (C 11, C12 in Figure 7-1),

which otherwise usually sustain higher voltage swings. Optimization of capacitance value and

location should be further examined.

7.2.2 Application in high-Q varactors

The varactor structures used in this work have capacitance around 40 fF. The associated

series resistance is only several ohms and sometimes difficult to measure. This becomes particu-

larly problematic when the length of SDR varactor decreases below 0.24 Clm. Varactor structures

with a smaller number of fingers should provide sufficient series resistance and facilitate the

investigation of SDR varactors with even higher Q.

Capacitance tuning range (y) of SDR MOS varactors is inferior to that of thin-gate-oxide

ones. The reason is the percentage of parasitic capacitance is higher. It should be helpful if the

























p-substrate

Figure 7-2. Spacing between poly gate and diffusion connections in MOS varactor
structures.



spacing between poly gate and metal connections of diffusions is further increased (Figure 7-2).

One way is to increase distance between the poly gate and diffusion contacts. The increase in chip

area and additional series resistance along the diffusion region and metal connections are the

drawbacks. Another way is to use metal3 layer as the overpass connection. This method does not

change the area consumption, and the series resistance will slightly increase due to the extra via

connections. Varactor test structures with different S1 and S2 should be fabricated along with the

control structure. The trade-off among tuning range, series resistance and chip area should be

investigated.










APPENDIX
MODEL FILE FOR SDR-26 MOS TRANSISTORS

The model used in simulation for the SDR-26 MOS transistors are based on that of the


conventional 3.3-V MOS transistor. Those modified parameters are highlighted.




6: type=n minr-le-60 Imin=3.5e-07 noimod=1 ef=0.907 af=0.9065 kf=8.704e-29 Imax=5e-07 dxl3 wmin=1.28e-06

+ dxw3 wmax=1.008e-05 dxw3 tnom=25 version=3.2 tox= 1.5 6.8e-09 toxm=1.5 6.8e-09 xj=1.7e-07

+ nch=5.26e+17 Iln=-1 lwn=1 wln=1 wwn=1 lint=4e-08 11=0 lw=0 lwl=0 wint=3e-08 wl=0

+ ww=0 wwl=0 mobmod=1 binunit=2 xl= 2e-08 + dxl3 xw=0 + dxw3 dwg-0 dwb=0

+ Idif=9e-08 hdif=hdifu3 rsh=6.8 rd=0 rs=0 vth0= -0.18 + 0.8654908 + dvthn3 Ivth0=-1.656396e-08

+ wvth0=1.422681e-09 pvth0=-6.085174e-16 kl=0.7481822 Ikl=1.029616e-07 wkl=-1.008557e-07

+ pkl=2.007025e-14 k2=0.189703 Ik2=-9.366277e-08 wk2=8.466009e-09 pk2=7.544907e-15

+ k3=0 dvt0=0 dvtl=0 dvt2=0 dvt0w=0 dvtlw=0 dvt2w=0 nlx=0 w0=0 k3b=0 vsat= 1.7 93128.79

+ Ivsat=-0.00085 15 152 wvsat=-0.004630455 pvsat=1.852182e-09 ua=-6.66533 8e-10 lua=-9.53 3202e-17

+ wua=-1.002899e-15 pua=3.95669e-22 ub=2.115918e-18 lub=2.187213e-25 wub=5.45836e-25

+ pub=-4.393103e-31 uc=2.631281e-10 luc=-3.906129e-17 wuc=-1.204542e-16 puc=2.977803e-23

+ rdsw=545 prwb=0 prwg=0 wr-1 u0=1.43 0.04367778 lu0=3.770848e-10 wu0=-1.023911e-08

pu0=2.667197e-15









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BIOGRAPHICAL SKETCH


Haifeng Xu was born in Xi'an, China, in June 1975. He received the B.S. degree in Phys-

ics from Nanjing University, Nanjing, China, in 1996, and the M.S. and Ph.D. degrees in electri-

cal and computer engineering from the University of Florida, Gainesville, FL, USA, in 2002 and

2007, respectively. He joined the Silicon Microwave Integrated Circuits and Systems (SiMICS)

Research Group in the Department of Electrical and Computer Engineering at University of Flor-

ida in 2000. In 2001, he worked on radio frequency (RF) integrated circuit design as a summer

intern at IBM Boston Design Center, Chelmsford, MA, USA. His research interests include

CMOS RF integrated circuits, RF power amplifiers, monolithic microwave IC (MMIC) compo-

nents and digital I/O circuits.





PAGE 1

1 THICK-GATE-OXIDE MOS STRUCTURES WITH SUB-DESIGN-RULE CHANNEL LENGTHS FOR DIGITAL AND RADIO FRE QUENCY CIRCUIT APPLICATIONS By HAIFENG XU A DISSERTATION PRESENTE D TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2007

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2 2007 Haifeng Xu

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3 To my parents and my wife

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4 ACKNOWLEDGMENTS I want to express my deep gratitude and appr eciation to my advisor, Professor Kenneth K. O, for his patient, constant encouragement a nd devotion. He guided me through the transition from a student to an electrical engineer. Under his supervision, I had opportunities to work in microelectronics, which eventually became a joy for me. Also much appr eciation goes to Professor Rizwan Bashirullah, Professor Huikai Xie and Professor Oscar D. Crisalle for their helpful suggestions to my research. I woul d like to thank them for their in terests in this work and serving on my Ph.D. supervisory committee. I would like to thank all the former and curr ent colleagues in the SiMICS research group for their helpful discussions, advice and friends hip. Some names are list ed here: Chikuang Yu, Xiaoling Guo, Brian Floyd, Chih-Ming Hung, Fe ng-Jung Huang, Kihong Kim, Yochuol Ho, Namkyu Park, Xi Li, Zhenbiao Li, Seong-Mo Yi m, Dong-Jun Yang, Nara simhan Trichy Rajagopal, Ran Li, Tod Dickson, Jason Branch, James Caserta, Wayne Bomstad, Jose Bohorquez, Aravind Sugavanam, Jie Chen, Jau-Jr Lin, Li Gao, Changhua Cao, Yanping Ding, Yu Su, Eun-Young Seok, Kwang-Chun Jung, Swaminatha n Sankaran, Hsin-ta Wu, Chuying Mao, Ning Zhang, Seon-Ho Hwang, Nallani Shashank Kiron, Myoung Hwan Hwang, Zhe Wang, Wuttichai Lerdsitsomboon, Dongha Shim, and Kyujin Oh. Finally, I am gratef ul to my parents, my si ster and her family. At la st, but not least, I want to thank my wife for her love, patience, encour agement and tolerance. Sh e has been beside me every single day, bright or dark. I can not imagi ne walking through all these days without her companionship.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS . . . . . . . . . . . . . 4 LIST OF TABLES . . . . . . . . . . . . . . . 8 LIST OF FIGURES . . . . . . . . . . . . . . . 9 ABSTRACT . . . . . . . . . . . . . . . . 13 CHAPTER 1INTRODUCTION . . . . . . . . . . . . . . 15 1.1CMOS Technology . . . . . . . . . . . . 15 1.1.1History of CMOS Transistors . . . . . . . . 15 1.1.2From Digital to Analog . . . . . . . . . . 18 1.2Transistor Scaling . . . . . . . . . . . . . 1 9 1.2.1Transistor Scaling Guidelines . . . . . . . . 19 1.2.2Issues for Transistor Scaling . . . . . . . . . 23 1.3Thick-Gate-Oxide MOS Transistor. . . . . . . . . . 24 1.4Motivation . . . . . . . . . . . . . . 26 1.5Methodology . . . . . . . . . . . . . . 27 1.6Overview of the Dissertation. . . . . . . . . . . 28 2HIGH-TO-LOW LEVEL SHIFTER APPLICATION. . . . . . . . 30 2.1Introduction . . . . . . . . . . . . . . 30 2.2Sub-Design-Rule (SDR) MOS Transistor Structure . . . . . 32 2.3DC Characteristics of SD R MOS Transistors . . . . . . . 34 2.3.1Current Drive Capability. . . . . . . . . . 34 2.3.2Voltage Handling Capability. . . . . . . . . 37 2.3.3Optimization of MOS Transistors for Level Shifter Application . . 38 2.4Capacitance Property of SDR-26 MOS Transistor . . . . . . 41 2.5High-to-low Level Shifter Speed Pe rformance . . . . . . . 43 2.6Summary . . . . . . . . . . . . . . 47 3LOW-TO-HIGH LEVEL SHIFTER APPLICATION. . . . . . . . 49 3.1Introduction . . . . . . . . . . . . . . 49 3.2Composite MOS Transistor Structure . . . . . . . . . 50 3.3Composite MOS Transistors in a 0.18m Process. . . . . . 53 3.3.1Current and Breakdown Characteristics . . . . . . 54 3.3.2Subthreshold Current Leakage Issues . . . . . . . 56 3.4Composite MOS Transistors in a 0.13m Process. . . . . . 60

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6 3.4.1Current Characteristics . . . . . . . . . . 61 3.4.2Voltage Handling Capability. . . . . . . . . 64 3.5Composite MOS Transistor Capacita nce Property . . . . . . 65 3.6Composite-22 MOS Transistors for Level Shifter Application. . . . . 68 3.7Low-to-high Level Shifter Speed Performance . . . . . . 71 3.8Summary . . . . . . . . . . . . . . 74 4RADIO FREQUENCY POWER AMPLIFIER APPLICATION . . . . . 76 4.1Introduction . . . . . . . . . . . . . . 76 4.1.1CMOS RF Power Amplifiers. . . . . . . . . 76 4.1.2Classification of CMOS RF Power Amplifiers. . . . . . 77 4.1.3Thick-Gate-Oxide MOS Transistors in Linear Power Amplifiers. . 78 4.2AC Characteristics of Composite-22 MOS Transistor . . . . . . 79 4.2.1fT and fmax . . . . . . . . . . . . 79 4.2.2Measurements for fT and fmax . . . . . . . . 82 4.3Summary . . . . . . . . . . . . . . 86 5TRANSMIT/RECEIVE SWITCH APPLICATION. . . . . . . . 87 5.1Introduction . . . . . . . . . . . . . . 87 5.1.1CMOS Transmit/Receive Switches. . . . . . . . 87 5.1.2Techniques to Improve Power Handling Capability . . . . 90 5.2CMOS T/R Switches Using Sub-De sign-Rule Transistors. . . . . . 91 5.2.1Design of SDR T/R Switches . . . . . . . . 91 5.2.2 900-MHz SDR T/R Switch . . . . . . . . . 98 5.2.3 2.4-GHz SDR T/R Switch. . . . . . . . . . 102 5.3Discussion . . . . . . . . . . . . . . 106 5.4Summary . . . . . . . . . . . . . . 109 6HIGH-Q MOS VARACTOR APPLICATION . . . . . . . . 111 6.1Introduction . . . . . . . . . . . . . . 111 6.1.1CMOS Voltage-Controlled Oscillator. . . . . . . 111 6.1.2MOS Varactors . . . . . . . . . . . 112 6.1.3Sub-Design-Rule MOS Varactors. . . . . . . . 116 6.2High Frequency Characteristics of SDR MOS Varactors . . . . . 117 6.2.1Device Structure . . . . . . . . . . . 117 6.2.2Measurements and Discussions. . . . . . . . . 118 6.3Summary . . . . . . . . . . . . . . 122 7SUMMARY AND SUGGESTION FOR FU TURE WORK. . . . . . 123 7.1Summary . . . . . . . . . . . . . . 123 7.2Suggestion for Future Work. . . . . . . . . . . 126 7.2.1Application in high power T/R switches. . . . . . . 126 7.2.2Application in high-Q varactors . . . . . . . . 127

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7 APPENDIX MODEL FILE FOR SDR-26 MOS TRANSISTORS . . . . . 129 LIST OF REFERENCES . . . . . . . . . . . . . 130 BIOGRAPHICAL SKETCH . . . . . . . . . . . . 137

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8 LIST OF TABLESTable page 1-1Scaling strategies for CMOS transistors . . . . . . . . . 21 1-2Two types of transistors available in a standard CMOS technology. . . . . 25 2-1Breakdown voltages of sub-design-ru le MOS transistors . . . . . . 37 2-2Speed performance of level shifters using the SDR-26 and conventional 3.3-V MOS transistors as the drive transistors . . . . . . . . . . 47 3-1Breakdown voltages and thre shold voltages for the compos ite-18, and the conventional 3.3-V and 1.8-V MOS transistors . . . . . . . . . . 55 3-2Measured threshold voltages of the compos ite transistors, and the conventional 1.2-V, 3.3-V transistors. . . . . . . . . . . . . . . 62 3-3Breakdown voltages for the composite tran sistors, and the conventional 3.3-V and 1.2-V transistors. . . . . . . . . . . . . . . . 64 3-4Speed performance comparis on of level shifters using th e composite-22 and conventional 3.3-V MOS transistors. . . . . . . . . . . . . 74 5-1Performance summary of CMOS T/R switches. . . . . . . . 105

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9 LIST OF FIGURESFigure page 1-1First MOSFET structure proposed in 1928 from Li lienfelds US patent application.. 16 1-2Illustration of MOSFET scaling propos ed in Dennards paper. . . . . . 17 1-3Typical floorplan for the mixed-signa l system design. . . . . . . 19 1-4Scaling parameters in CMOS transistors. . . . . . . . . . 20 2-1Low-to-high and high-to-low le vel shifters (LS) used as the interface circuits along the paths between the circuits with diffe rent signaling levels. . . . . . . 30 2-2Typical high-to-low level shif ter, using 3.3-V drive transist ors at the interface between 3.3-V and 1.8-V circuitries.. . . . . . . . . . . . 31 2-3Cross-section of the sub-design-ru le (SDR) MOS structure.. . . . . . 33 2-4Test structure layout of a set of SDR MOS tran sistors for DC measurements.. . . 34 2-5Normalized ID-VGS for different SDR MO S transistors at VDS = 1.8 V. . . . 35 2-6Measured threshold voltages of SDR MOS tran sistors with different channel lengths. 36 2-7Comparison of normalized ID-VDS between SDR-26 and conventional 3.3-V MOS transistors. . . . . . . . . . . . . . . . 39 2-8Comparison of normalize ID-VGS between SDR-26 and conventional 3.3-V MOS transistors in both linear and logarithm scales, when VDS = 1.8 and 0.05 V.. . . 40 2-9Simulated gate capacitance of longer channel 3.3-V MOS tran sistors, and extrapolated gate capacitance of SDR-26 MOS transistors.. . . . . . . . . 42 2-10Simulated ID-VDS and ID-VGS curves of the SDR-26 and 3.3-V MOS transistors. The simulations also match the measur ed currents for both types of tr ansistors.. . . 43 2-11Schematics of level shifter circuits in simulation. Version A uses conventional MOS transistors as drive transistors, while Version B uses SDR-26 MO S transistors. . 44 2-12Comparison of the SDR-26 and conventiona l 3.3-V MOS transistors used as the drive transistors in 3.3-to-1.8-V level shifters. . . . . . . . . . 46 3-1Typical low-to-high level shifte r, using thick-gate-oxide driv e transistors at the interface between low-VDD and high-VDD circuitries.. . . . . . . . . 49

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10 3-2Layout of the composite MOS tran sistor. Only 2 cells are shown he re. . . . 51 3-3Cross-section of the composite MOS tr ansistor. . . . . . . . . 52 3-4Equivalent schematic s of the composite MOS transistor. . . . . . . 53 3-5Test structure layout of the compos ite-18, conventional 3.3V thick-oxide and conventional 1.8-V thin-oxide MOS transistors for DC measurements.. . . . 54 3-6Normalized ID-VDS of the composite-18, conventional 3.3-V thick-oxide and conventional 1.8-V thin-oxide MOS transistors.. . . . . . . . 55 3-7ID-VGS curves in a logarithm scale for the composite-18, conventional 3.3-V and 1.8-V MOS transistors with VDS = 0.05 V and VDD (1.8/3.3 V).. . . . . . 56 3-8Illustration of source current matching be tween (A) the composite18 transistors and (B) the conventional 1.8-V MOS transi stors.. . . . . . . . . . 57 3-9Calculation of the voltage at the shared diffusion region (VM (a)) by using source current matching. . . . . . . . . . . . . . . . 59 3-10Test structure layout of a group of the composit e MOS transistors for DC measurements. 61 3-11Normalized ID-VGS plots for the composite and the conventional 3.3-V transistors with VDS = 3.3 V, and the conventional 1.2-V transistor with VDS =1.2 V.. . . . 62 3-12Layout of the AC test st ructures for the composite MOS transistor and the open structure.. . . . . . . . . . . . . . . . 66 3-13Measured gate capacitance of the composit e transistors with diffe rent lengths of SDR sub-transistors, compared to those of the conventional 1.2-V and 3.3-V transistors.. 67 3-14ID-VDS characteristics of the composit e-22, conventional 3.3-V and 1.2-V MOS transistors when gate capacitances (Cgg) are the same.. . . . . . . 69 3-15Comparison of ID-VGS curves for the composite-22 and conventional 3.3-V MOS transistors in linear and logarithm scales at fixed gate capacitance. . . . . 70 3-16Schematics of level shifter circuits in simulation.. . . . . . . . 72 3-17Comparison of the composite-22 and conve ntional 3.3-V MOS transistors used in 3.3to-1.8-V level shifters.. . . . . . . . . . . . . 73 4-1Simplified block diagram of a typical RF transceiver. . . . . . . 76 4-2Small-signal lumped microwave network model of a MOSFET. . . . . 79

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11 4-3Measured current gain (h21), maximum available gain (M AG) and unilateral power gain (Gmax) for the composite-22 and conventional 3.3-V thick-gate-oxide transistors. a . 83 4-4fT and fmax for the composite-22 MOS transistor and conventional 3.3-V thick-gateoxide transistors. . . . . . . . . . . . . . . 84 4-5gm, output resistance (ro) and intrinsic gain of the composite-22 and conventional 3.3V/1.2-V transistors when the overdrives (VGS-VT) are around 0.25 V. . . . 85 5-1T/R switch in a typical TDD RF transceiver.. . . . . . . . . 87 5-2Simplified schematic of th e T/R switch with 3-stack sub-design-rule (SDR) length transistors. . . . . . . . . . . . . . . . 92 5-3Cross-section of the 3-stack transistors in the SD R T/R switch.. . . . . 93 5-4Detailed schematic of the 3-stack transi stors (M1-M3) including the parasitic shunt paths. . . . . . . . . . . . . . . . . 94 5-5Voltage distributions for th e 3-stack SDR switches with and without the feed-forward capacitors, when the input power is 30 dBm. . . . . . . . . 95 5-6Impact of feed-forward capacitance (0X, 1X, 2X and 3X) on the peak voltages across transistors M1-M3 (VDG1 p~VDG3 p, VSG1 p~VSG3 p).. . . . . . . . 97 5-7Die photo of the 3-stack SDR T/R switch.. . . . . . . . . . 99 5-8Measured insertion loss of th e SDR switch using 3 stack SD R transistors, compared to that of the switch using 2 stack 0.34-mm length transi stors.. . . . . . 100 5-9Measured isolation and return loss for th e SDR T/R switch usi ng 3 stack SDR channel length transistors.. . . . . . . . . . . . . . 100 5-10Linearity measurement result s of the 3-stack SDR switch wi th source/drain biased at 3 and 0 V, and with (1X) and without the feed-forwa rd capacitors.. . . . . 101 5-11Simplified schematic of the T/R switch for 2.4-GHz appl ications using 2-stack SDR transistors without feed-forward capacitors. . . . . . . . . 102 5-12Die photo of the T/R switch for 2.4-GHz applications using 2stack SDR transistors without feed-forward capacitors .. . . . . . . . . . . 103 5-13Measured insertion loss and isolation of the 2-st ack SDR switch for 2.4-GHz applications.. . . . . . . . . . . . . . . 104 5-14IP1dB measurement of the 2-stack SD R switch working at 2.4 GHz. . . . 104

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12 5-15Detail of linearity measurement result s around 1-dB compression point for the 3-stack SDR switch.. . . . . . . . . . . . . . . 106 5-16Measured DC current through the n-p-np sandwich structure from source/drain, through body to p-substrate.. . . . . . . . . . . . 107 5-17Measured breakdown characteristics of a single SD R transistor. . . . . 108 6-1Schematic of a typica l differential CMOS voltage -controlled oscillator. . . . 112 6-2Cross-section of MOS varactor struct ures. . . . . . . . . 113 6-3Layout and equivalent ci rcuit model of a MOS varactor. . . . . . . 117 6-4C-V and Q-V characteristics of the thickgate-oxide (TK) and thin-gate-oxide (TN) varactors with L = 0.24 m.. . . . . . . . . . . . 119 6-5Measurement data of Qmin and vs channel length for thickgate-oxide (TK) and thingate-oxide (TN) varactors.. . . . . . . . . . . . 119 6-6Varactor design space formed by Qmin and tuning range . . . . . 121 7-1Additional nodes to connect feedforward capac itors in a 4-transist or stack of SDR T/R switches.. . . . . . . . . . . . . . . . 127 7-2Spacing between poly gate and diffusion connect ions in MOS varactor structures.. 128

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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy THICK-GATE-OXIDE MOS STRUCTURES WITH SUB-DESIGN-RULE CHANNEL LENGTHS FOR DIGITAL AND RADIO FRE QUENCY CIRCUIT APPLICATIONS By Haifeng Xu August 2007 Chair: Kenneth K. O Major: Electrical and Computer Engineering The potential digital and radio frequency (RF) applications and advantages of thick-gate-oxide metal-oxide-semiconductor (MOS) structures with sub-de sign-rule (SDR) channel lengths in standard complementary MOS (CMO S) technologies are investigated. This is a low-cost solution for scaling down thick-gate-oxide transistors, which doe s not require any modifications to the existing foundr y technologies. This concept provi des a new perspective to the down-scaling of thick-ga te-oxide transistors. The maximum drain voltage for the drive tr ansistors with a thick-gate oxide of 3.3-to-1.8-V level shift circuits in 0.18m CMOS processes is 1.8 V. The drain current is increased by reducing the gate length to 0.26 from 0.35 m. Measurements show the SDR MOS transistor has sufficient drain-to-source breakdow n voltage for 1.8-V operation. At the same gate capacitance, the SDR transistor delivers more than 1.6 times the drain current of the conventional thick-gate-oxide transistor. Si mulations indicate the propagation delay of 3.3-to-1.8-V level shift circuits can be reduced by 20% without process modifications. Then, for the first time, we proposed a composite MOS transist or structure by combining a 0.12m long thin-gate-oxide transistor with a 0.22m long thick-gate-oxide (SDR) transistor in a 0.13m CMOS process. The

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14 composite transistor has more than 2 times the dr ain current of the conventional thick-oxide transistor, while having the same breakdown voltage. 3.3V I/O transistors with better combination of drive current, threshold voltage and breakdown voltage are realiz ed in conventional CMOS technologies without process modifica tions. Simulations suggest that 40% reduction in the propagation delay for a 1.2-to-3.3-V level shifter is expected. The concept of SDR transistors can also be us ed to improve the performance of RF/analog circuits. Measurements show that the composite MOS transistor has higher fT and fmax than the 3.3-V transistor when VGS is below 1.2 V. If the VGS-VT is set to ~ 0.25 V in a practical bias condition for linear power amplifiers, fT of the composite transistor is 15 GHz and 20% higher than that of the 3.3-V transistor. This characteristics can potentially imp rove RF power amplifier gain and power efficiency. Using 3-stack thick-gate-oxi de transistors with a 0.26m SDR channel length, a 31.3-dBm 900-MHz bulk CMOS transmit /receive (T/R) switch with insertion losses of 0.5 and 1.0 dB in transmit (TX) and receive (RX) modes has been successfully demonstrated. The effects of feedforward capacitan ce in the switch are analyzed. Th rough another 28-dBm T/R switch operating at 2.4 GHz with IL of 0.8/1.2 dB in TX/RX m odes, it is demonstrated that 2-stack configuration can be used to trade-off IP1dB for better loss performance. It is suggested that integration of a bulk CMOS T/R switch for cellular applications is a realizable goal by using thick-gate-oxide SDR MOS transistors. Lastly, the use of the SDR MO S structures as varactors in VCO circuits is investigated. This study shows that Qmin of SDR varactors at 24 GHz is 5 times that of thin-gate-oxide structures. The varactor tuning range ( ) is decreased from ~ 65% to ~ 40%. Its application for 50-GHz narrow tuning range VCOs with better power consumption and phase noise performance is projected.

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15 CHAPTER 1 INTRODUCTION Thick-gate-oxide metal-oxide-semiconducto r (MOS) transistors in addition to thin-gate-oxide high performan ce MOS transistors are commonly used in standard complementary MOS (CMOS) processes. Th eir high breakdown voltage and low off-current are preferred in many applications. This study is interested in further scaling down the thick-gate-oxide MOS transistors and exploiting this fu rther scaled devices in both di gital and analog circuit designs. Since this study is related to scaling, the evolution and deve lopment trend of CMOS technology is an excellent place to start with. 1.1 CMOS Technology 1.1.1 History of CMOS Transistors The concept of MOSFETs (metal-oxide-semico nductor field-effect tr ansistors) was first proposed as early as 1928 by Julius E dgar Lilienfeld in his US patent ( Figure1-1 ) [ Lil28 ]. The conductivity between the S node (s ource) and D node (drain) can be modulated by the transverse electric field applied through the G (gate). Unfortuna tely, this idea did not become practical until 1958 when the thermally grown oxide were devel oped by Atalla to reduce the surface state density and solve the electrical inst ability of the MOS transistors [ Ata59 ]. Building on these and others, Kahng and Atalla successfully developed the first modern MOSFET in 1960. Their structure was very similar to that of modern MOS transistors, and consisted of a thermally grown gate -oxide layer over an n-type inversion channel between two n+/p junctions on a p-type silicon substrate [ Kah60 Kah76 ]. About the same time, Kilby and Noyce separately invented the monolithic integrated circuit (IC) concept [Kil76 Noy61 ]. This technol-

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16 ogy laid the foundation for the development of ICs, initially using BJTs (b ipolar junction transistors), then using MOSFETs [ Sah88 ]. A major breakthrough in IC technology oc curred when a CMOS (complementary metal-oxide-semiconductor) inve rter circuit was invented by Fr ank Wanlass and Chih-Tang Sah in 1963 [ Wanl63 ]. In CMOS technology, both n-type and p-type MOSFETs are fabricated in the same silicon chip, and the circuits using CMOS logic has almost zero stat ic power consumption. CMOS integrated circuits became successful in many then-advanced elect ronic products because of low overall power consumption and prolonge d battery life time. In 1968, Noyce and Moore started a MOS integrated circui t manufacturing company (Intel), leading to volume production in 1970. A new era of CMOS integrated circuit production has been opened. Probably one of the most influential techniques on MOSFET design was proposed by Dennard and co-researchers around 1973 [ Den74 ]. They presented the way to reduce the transisFigure 1-1.First MOSFET st ructure proposed in 1928 from Lilienfelds US patent application. Cu2S Al2O3Al S D G S D G

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17 tor dimensions without compromising the currentvoltage characteristics. This has been known as the scaling law of MOSFETs (illustrated in Figure1-2 ). Compared to bipolar devices, CMOS transistors are relatively easy to fabricate. The ability to scale makes CMOS technology even more attractive. Engineers and re searchers have been able to sc ale down the feature size and push CMOS technology forward. The channel length of MOSFETs has decreased from several micron meters in Dennards time, to subm icron, and to nano-meters nowadays. Since its first use in commer cial products, CMOS technology has been growing very fast. Just tracing back to year 1982, for example, in tegrated circuits manuf actured using CMOS processes were only 12% of the market including BJT, BiCMOS, NMOS, PMOS, TTL and other technologies. However, this percentage almost reversed by the year 2003. The shar e of CMOS technology jumped to 82% [ Vee03 ]. Considering the fact that th e whole IC market had increased from $10.2B to $175B duri ng the same period, the growth of CMOS technologies is indeed amazing. Figure 1-2.Illustration of MOSFET scaling proposed in Dennards paper. (A) State-of-the-art MOSFET structure. (B) Down-scaled MOSFET structure following the scaling law. A B L=L/k tox=tox/k Vds=Vds/k NA=kNAk=5

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18 1.1.2 From Digital to Analog Scaling is one remarkable feature of CM OS technology. When the dimensions are reduced, MOS transistors can achieve higher speed performance due to lower capacitance, lower supply voltage and higher drive current. By reduc ing the transistor size, more functions can be integrated in the same ch ip area, and the cost of the same functionality is decreased. Additionally, CMOS gates have low power consumption. Power is dissipated only during switching of the circuit. This allows hundreds of millions of CMOS transistors to be integrated on a single silicon chip before the heat manageme nt becomes problematic. CMOS te chnology is the dominant one in VLSI production today, and its advance will remain the primary driving force for the IC industry. RF (radio frequency) and anal og circuits were trad itionally fabricated using bipolar transistors due to its higher transconductance, bett er matching, lower noise and higher speed. Meanwhile MOS transistors have been steadily scaled down and this has improved the speed of MOS transistors. As a matter of fact the intrinsic speed of MOS transi stors has been increased by more than three orders of magnitude in the past 30 y ears and becomes comparable to that of bipolar counterparts. This has enabled use of CMOS t echnology for RF applications. With the modest transistor performance, CMOS te chnology has the advantage that both analog and complex digital circuits can be inexpensively in tegrated into the same silicon chip. Analog/mixed signal CMOS circuit design is under rapid developm ent, including RF applications [ HuaQ98 Abi04 ]. It is the clear trend today to use CMOS di gital circuits combined with CMOS analog circuits whenever possible because of the higher level of integrati on and low cost, thus providing highly reliable SoC (system-on-chip) solutions, as illustrated in Figure1-3 [ Sin99 ].

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19 1.2 Transistor Scaling 1.2.1 Transistor Scaling Guidelines CMOS technology evolution has followed the path of scaling down for pursuing higher speed, higher integration, lower power consumption and lower co st. However, the progress of scaling is not arbitrary even if allowed by the lithography. Th e short channel effect (SCE) which leads to the decrease of the threshold voltage is an undesirable aspect of scaling and should be controlled with the help of advancement in devi ce design and process tec hnology. Therefore, certain design guidelines are always follow ed. There are two met hods often mentioned: constant-field scaling constant-voltage scaling In the first scaling scenario, both hor izontal and vertical dimensions in Figure1-4 such as channel length L, width W, gate thickness tox, junction depth Xj, etc., are proportionally scaled down by a factor of k. At the sa me time, it is required to decrease the applied voltage (VDD) and Figure 1-3.Typical floorplan for the mixed-signal system design. Low amplitude analogue circuits Medium amplitude analogue circuits High amplitude analogue circuits p+ Guard Ring Low speed digital circuits High speed digital circuits Digital output buffers

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20 increase the doping concentration (NA or ND) by the same factor. The maximum drain depletion width (WD in Figure1-4 ), given by ,(1-1) is also scaled down appr oximately by k. The key point in this scenario is that the electric field ( E ) remains unchanged by the scaling, so that the reliability of scaled CMOS transistors is no worse than that of the original device This concept is illustrated in Figure1-2 and the scaling rules for device and circuit parameters are specified in Table1-1 For the constant-field sc aling, the drift current (ID) decreases by a factor k. Interestingly, the circuit delay ( CVDD/ID) is still improved by k because the capacitance (C ~ WL/tox) and the voltage are scaled down by a factor of k2 in total. Moreover the power density (~ P/WL) is kept the same. This means that, by following the constant-field scaling, the circuits can speed up by the same factor while maintaining the power density of the silicon chip. Figure 1-4.Scaling parameters in CMOS transistors. WD xj toxWdm L VDD Gate n+ source n+ drain p-substrate, NAWD2 sibiVDD+ qNA-------------------------------------2 siVDDqNA-------------------VDDNA---------1 k -=

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21 Under the second scaling scheme (constant-voltage scaling) the MOS transistors horizontal and vertical dimensions again are scaled down by k. Different from the last scenario, the applied voltage in this ca se remains the same, thus the electric field has to be increased by k. The maximum channel depletion width (Wdm in Figure1-4 ) is expressed as .(1-2) To assure that the maximu m channel depletion width (Wdm) and the maximum drain depletion width (WD) in Equation 1-1 are scaled down by factor of k, the dopi ng concentration (NA or ND) ParametersconstantE scaling factor (k>1) constant-V scaling factor (k>1) generalized scaling factor (1<
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22 should be increased by k2. The constant-voltage sc aling rules for device a nd circuit parameters are also listed in Table1-1 Under the constant-voltage strategy, the drif t current is increased by k. Consequently, the circuit delay is improved even faster (by k2). However, the benefit is countered by the drastic increase of power density by a factor of k3. Even worse, scaling up electric field may cause hot-carrier and oxide relia bility problems in the scaled MOS transistors. The constant-field scal ing is a clear and simple appro ach to the design of scaled MOS transistors. However, the requirement of reduci ng the voltage by the same factor as the device physical dimension is too conserva tive. Because of certain non-scalab le effects and reluctance to depart from the standardized voltage levels of the previous generations, the supply voltage is seldom scaled in proportion to the channel length. Actu ally, the electric field has been gradually rising over the generations rather than staying constant [ Cha01 ]. On the other hand, the constant-voltage scaling scheme put s a very loose constraint on the el ectric field and allows it to increase by the same factor as the dimensions are scaled dow n. The performance can be improved fast. However, the MOS transistor is no longer reliable and the circuit heating becomes unmanageable. In reality, CMOS technol ogy development has followed the steps between the constant-field scaling and th e constant-voltage scaling. This mixe d scaling method is expressed as the generalized scaling in Table1-1 When the device dimensions are reduced by k, the electric field is allowed to scale up by a smaller factor (1<
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23 1.2.2 Issues for Tr ansistor Scaling Even though the CMOS scaling guidelines discu ssed above have served the industry well, there are some non-scalable effect s that are not taken into account and make the scaling guidelines impractical sometimes. To keep improving the speed performance of MOS transistors, an important assumption implicitly used is that the threshold voltage (VT) can be always scaled down together with the supply voltage (VDD) so that sufficient VDD/VT ratio is maintained. However, the off current (Ioff) will exponentially increase when the threshold voltage VT is scale down, as given by ,(1-3) where m is representing the efficiency that the gate controls the inversion layer. Fundamentally, the thermal voltage is non-scalable with the process parame ters. The off current (Ioff), therefore, will increase be yond the reasonable limit if there is no compromise in VDD/VT ratio, i.e., slowing down the sc aling of threshold voltage. The off current directly contributes to the static power consumption of the chip. Even though the latter is only a small fraction of the total power dissip ation nowadays, it is expected to become more problematic for fu ture technologies when the CM OS technology is further scaled down and the number of transist ors per chip is increased. Over the last decade, many tech niques have been reported to reduce the static power dissipation in VLSI. Among those, the multi-threshold CMOS transistor and variable threshold CMOS transistor are promising techniques to reduce th e static power while ma intaining high performance in active mode [ McP00 YamT00 ]. The basic idea is to use lower-VT MOS transistors along the critical signal path s for high speed and higher-VT MOS transistor in the non-critical porIoffuoCoxW L ----m1 kT q -----2eqVT mkT = 1 3toxWdm----------+ kT q ------

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24 tion of the same chip without affecting the high performance portion. Fo r one CMOS process, these types of transistors with different thre shold voltages can be achieved in several ways [ Ani03 ]. Body effect (VSB): Change the threshold voltage by applying different biases at the body of MOS transistors. C ontrol signals at the body node s are required. Changing VTis less efficient because VT is proportional to the square root of VSB. Ion implantation (Na): Extra process steps are needed Both process complexity and cost are increased. It is an efficient way to adjust VT and already widely used in existing CMOS processes [ Wei00 ]. Different channel lengths (L): Scale down the MOS transistor further and intentionally introduce more short cha nnel effect to lower the VT. Scaling should be carefully designed and controlled. Multiple oxide thicknesses (tox): Transistors with different gate-oxide thicknesses can be fabricated in the same wafer. This technique complicates the process, but the higher gate-oxide thickness for high-VT MOS transistor can reduce the gate capacitance and suppress both the dynamic and static power dissipation [ Che95 O95 Ima00 Tho01 ]. 1.3 Thick-Gate-Oxide MOS Transistor As to the multiple oxide thic kness technique, dualgate-thickness CMOS processes are the most commonly used approach. Two different thickn esses of gate-oxide-lay ers can be fabricated in the same process. The thin-gate-oxide MOS tran sistors are optimized to take full advantage of the process parameters (physical dimension, doping profile, etc.) a nd operate at the highest possible speed. Due to smaller dimensions, the voltage sw ings they can tolerate at the gate and drain nodes are lower. On the contrary, the thick-gate-oxide MOS transist ors also have larger horizontal dimension in addition to the thic ker gate-oxide-layer. Its speed pe rformance is not as good as that of the thin-gate-oxide transistors due to the lo nger channel length, while they have much lower leakage current and are able to handle highe r voltage swings at the gate and drain.

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25 With the continuous scaling of thin-oxide MOS transistors, the th ick-oxide MOS transistors became part of the standard offe ring from the CMOS foundries. In a 0.18m CMOS foundry technology, for instance, both the thin -oxide transistor and the thickoxide transistor are available. Compared in Table1-2 are the dimensions and applied volta ges of the two types of transistors. Including the thick-gate-oxide MOS transistor as the standard offering of CMOS technology, of course, increases the proces s complexity, and in turn the cost of chip fabrication. However, several reasons make the efforts wort hwhile in modern CMOS technologies. The first one among them, as discussed in Section 1.2.2 is that the thick-gate-oxide transistors can be used as the sleep transistors to di sable the core circuits, therefore providing a technique to effectively control the circuit leakage current and signi ficantly reduce the standby power consumption. Second, the dual-gate-thickness processe s give the option that the core circuits use more advanced CMOS transistors to operate at higher frequencies, while th e I/O interface blocks using the thick-gate-oxide MOS tran sistors can bridge the core circ uits with those implemented in the older generations of technologi es, or the peripheral circuits which usually employ higher voltages and operate at lower speed. Third, the thick-ga te-oxide transistor is also beneficial for RF Parameters Thin-oxide transistor Thick-oxide transistor Gate thickness (nm)4.56.8 Minimum channel length specified in design rule ( m) 0.180.35 Gate voltage (V)1.83.3 Drain voltage (V)1.83.3 Table 1-2.Two types of transistors av ailable in a standa rd CMOS technology

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26 and analog circuit design. While the higher transistor fT is certainly welcomed as the technology advances, the lower supply voltage of thin-gate-oxide transistors cau ses some serious problems. It can impair the ability to handle large signals. This limits the power handli ng capability of amplifiers, reduces the dynamic range, and worsens the pha se noise of local osc illators. These can be bypassed by realizing crit ical analog circuits with the th ick-gate-oxide MOS transistors [ Abi04 ]. 1.4 Motivation In present CMOS technologies, the polysil icon gates on the thin-gate-oxide and the thick-gate-oxide transistors are formed at the same time. The thin-gate-oxide transistor has a shorter feature length than that for thick-gate-oxi de transistor. Therefore, the thick-gate-oxide MOS transistor could have the sa me length as the thin-gate-oxide transistor, and the lithography limitation is not a barrier to furt her shorten the thick-gate-oxide MO S transistor. Technically, it is feasible to shrink the length of the thick-gate-oxi de transistor to less than the minimum specified in the design rule, and down to that for the thin-gate-oxide transistor. With the steady scaling of thin-gate-oxide transi stors, they can operate faster and tolerate smaller voltage swings. On the other hand, the pe rformance of 3.3-V thickgate-oxide transistors has remained standstill. Essentially, they are the devices belonging to an older generation. The gap between the device characteristi cs of these two types of MOS tr ansistors, such as supply voltage and current drive capability and so on, are becoming greater. Thick-ga te-oxide transistors with a certain degree of scaling with a better combination of cu rrent and voltage characteristics can bridge this gap. To improve the performance of thick-gate-oxi de MOS transistor for certain applications as wi ll be discussed, it is possible to s cale down the horizontal dimensions of thick-gate-oxide transistors to keep up with the scaling trend.

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27 A goal of this research is to explore low cost solutions for scaling down the thick-gate-oxide MOS transistor without modifying the existing foundry technologies. More specifically, the thick-gate-oxide tran sistors with a channel length less than the design rule specification is the focus of this study. They are na med the SDR (sub-design-rule) MOS transistors. The device characteristics of SDR transistors will be differ ent from that of the normal transistors, and in turn they may not be used in the conventional ways. To exploit this opportunity, possible applications in both dig ital and RF circuits for the SD R MOS transistors are explored. Careful design and good control of the SDR MO S transistors length are of importance. 1.5 Methodology The SDR MOS transistors are structures that have channel lengths shorter than the minimum length required by the design rule. Their char acterization data and models are not at hand. Study and optimization of the SDR MOS transistor s, or structures consisting of the SDR MOS transistors, can typically be done in two ways: The first one is to use the simulation tec hniques to predict the performance and to optimize structures at the same time. This method requires detailed process information provided by the foundries. Even with that, the final character istics still strongly depend on the accuracy of the available fabrication parameters [ McS02 ]. This information is proprie tary in nature and is not readily available. This method is a di fficult option for uni versity research. The second method is to implement a variety of structures in a systematic manner and to find out the optimal layout. Usually, multiple la yout parameters should be varied, and a large array of test structures should be tested. More intensive measurem ents are the drawback of this method, but it can directly provi de the final performance results. The second method is a practical way for this work.

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28 For each potential applications of the SDR MOS structures de tailed in the following chapters (including both digital and RF circuits), a series of test stru ctures are designed based on scientific insight and experience, then fabricated in foundry processe s and evaluated for optimization. 1.6 Overview of the Dissertation This dissertation starts with the applications of SDR MOS structures in digital interface circuits. In Chapter 2 a conventional high-to-low level shifte r circuit and the t ypical problems are discussed. In this partic ular situation, the current drive capa bility and voltage tolerance can be traded-off. Thick-gate-oxide MOS transistors with different sub-design-ru le channel lengths are measured and analyzed. It is shown that such MO S transistors can improve the current drive capability without over-stress. A high -to-low level shift circuit using such SDR MOS transistors will also be discussed. In Chapter 3 the application in the low-to-high level shifter circuit the counterpart in the reverse direction of I/O paths, is also studied. A composit e MOS transistor consisting of a SDR MOS transistor and a conventional thin -gate-oxide transistor is proposed. It will be shown that the composite MOS transistors, wh en properly designed, can provide higher current drive capability without compromising the volta ge tolerance. The speed performance of a low-to-high level shifter using the composite MO S transistors as the drive transistors are compared to the case using th e conventional transistors. Then, building on the concept and characteristics of the SDR structures discussed in digital circuits, the potential for RF applications of the SDR MO S structures is evaluated. In Chapter 4 the potential application of th e composite MOS transistors in RF power amplifiers is examined. A T/R switch with power handling capability above 31 dBm is presented in Chapter 5 SDR MOS transistors, along with other circuit techniques, are used to achieve this performance. The trade-off between power handling capability and switch loss is also discuss. In Chapter 6 the high

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29 frequency performance of SDR MOS structures used as varactors is presented. Th e higher quality factor (Q) makes the SDR MOS varactors suitab le for millimeter-wave low power and lower phase noise voltage-controlled os cillator (VCO) applications. Lastly, the dissertation is summarized a nd some future work is suggested in Chapter 7 .

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30 CHAPTER 2 HIGH-TO-LOW LEVEL SHIFTER APPLICATION 2.1 Introduction As MOS transistors have scaled dow n along with the operating voltage [ SIA05 ], the high voltage input/output (I/O) transist ors have become part of a st andard technology offering to provide the option to maintain compatibility to the systems using circuits fabricated in the preceding generations of technologies or other periphera l circuits [ O95 ]. For instance, in 1.8-V 0.18m CMOS processes, 3.3-V 0.35m I/O transistors with a thicker gate oxide layer are available. Unlike the 1.8-V thin-oxide transistor, the 3.3-V thick-oxide transistor requires a longer channel to support the 3.3-V drain voltage, which in turn limits its drain current. As shown in Figure2-1 digital circuits with different signaling levels wi ll employ different voltages, for example, 1.8 V and 3.3 V, etc. These different voltages represent the same logic low/high LS high/low LS low/high LS high/low LS high-VDD I/O circuit low-VDD core circuit Figure 2-1.Low-to-high and high-to-low leve l shifters (LS) used as the interface circuits along the paths between the circuits with different signaling levels. high-VDD older generation circuits or peripheral circuits

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31 level and they should be translated in both directions by the interf ace circuits. Therefore, both the high-to-low and low-to-high level shifters are often used in the I/O circuits along the signal paths. In this chapter, we will look into the high-to -low level shifter circuit and investigate the potential application of the thick-oxide MOS transi stors with channels shorter than the minimum length specified in the design rule to improve the current drive capability. Figure2-2 shows a typical 3.3-to-1.8-V level shifter circuit [ Wang01 ]. The 3.3-V thick-oxide transistors (M5/M6) ha ve to be used here as the dr ive transistors, because the 3.3-V signal swings at the gates. Howe ver, the drain-to-source voltage (VDS) of the drive transistors in this case only switches between 0 and 1.8 V. Because of this, the channel length chosen to handle Figure 2-2.Typical high-to-low level shifter, using 3.3V drive transistors at the interface between 3.3-V and 1.8-V circuitries. 1.8 V M4 M3 3.3 V 3.3-V Drive Transistor In M6 M5 M8 M7 Out 1.8-V Transistors 3.3-V Transistors M2 M1 Level Shifter

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32 3.3 V is excessive, and unnecessari ly limits the drain current of M5/M6. The drain current (ID) of MOS transistors in the saturati on region is given by following [ Gra04 ]: ,(2-1) and in the linear region, ,(2-2) where, is carrier mobility, Cox is unit capacitance of gate oxide, W is channel width, L is channel length, VGS is gate-source voltage, and VT is threshold voltage which is also dependent on L. When the gate length L of the thick-oxide layer is scaled fu rther the drain current will proportionally increase. Additionally, the shorter ga te length will introduce more significant short channel effect (SCE). Threshold voltage VT could be lowered, and the dr ain current will increase even more. We refer to this type of furthe r scaled thick-oxide MO S transistor as the sub-design-rule transist or (SDR transistor). In general, circuit designers can not violate the design rules of a process to reduce the channel length arbitrarily. However, in this particular application the high-to-low level shifter, as will be discussed, there is some design spa ce to improve the device and circuit performance. We will push the process limit while not applying excessive stress to devices. 2.2 Sub-Design-Rule (SDR) MOS Transistor Structure In this chapter, the thick-gate-oxide sub-desi gn-rule (SDR) MOS structures fabricated in a conventional 0.18m foundry digital CMOS technology with out any process modification are under investigation. In this tec hnology, the minimum channel le ngth for the conventional 3.3-V thick-gate-oxide nMOS transistors is 0.35 m. On the other hand, the minimum channel length ID1 2 -CoxW L ----VGSVT 2= ID CoxW L ----VGSVT 1 2 -VDS VDS=

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33 for 1.8-V thin-gate-oxide nMOS transistors is 0.18 m. To further push forward the drive current performance of the thick-gate-o xide device, channel length fo r SDR MOS transistors can be between 0.18 and 0.35 m. Figure2-3 shows the cross-section of th is type of de vices. SDR MOS transistors have the same structure as the conve ntional 3.3-V thick-gate-oxide MOS transistors, except that the channel lengths are scaled to less than 0.35 m, the minimum specification in the design rule. These SDR MOS transistors with cha nnel lengths of 0.30, 0.28, 0.26, 0.24 and 0.22 m (SDR-30, -28, -26, -24, -22 MO S transistor) will be examined a nd compared to the characteristics of conventional 0.35m long 3.3-V thick-gate-oxide MO S transistors in Sections 2.3 and 2.4 These lengths are about 86%, 80%, 74%, 68% and 63% of that of the conventional 3.3-V transistor, respectively. Figure 2-3.Cross-section of the su b-design-rule (SDR) MOS structure. p-substrate POLY Thick Oxide Source Drain Substrate Gate n+ n+ LDRC = 0.35 m

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34 2.3 DC Characteristics of SDR MOS Transistors To exam the DC characteristics, a series of DC test structures of SDR MOS transistors with the same width (4.65 m) are fabricated. Figure2-4 shows the layout of a group of the test structures. An HP4155A (semic onductor parameter analyzer) and a DC probe station are employed for the measurements. 2.3.1 Current Drive Capability ID-VGS curves of these SDR MOS transistors at VDS = 1.8 V are shown on the right side of Figure2-5 Drain currents in the plot are normalized to unit channel width. By scaling the thick-gate-oxide tran sistor from 0.30 to 0.22 m, current drive capability is significantly increased. As shown from Equation 2-1 and 2-2 there are two main factors leading to the drain current increases. (a)Increase of ratio, or effectively decrease of L. Figure 2-4.Test structure layout of a set of SDR MOS transistors for DC measurements. SDR Transistors G D S B G D S B G D S B W L ----

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35 (b)Increase of and due to decrease of VT. Comparing the SDR-22 to the SDR-30 MOS transi stor, for example, the current ratio at VGS = 3.3 V and VDS = 1.8 V is about 1.4. Now the SDR MOS transistors ar e biased in the linear region. This current difference is largely due to th e increase of ratio, or the decrease of L. The term gives a relative ly smaller improvement factor for different SDR MOS transistor s with lowered threshold voltages. The high-VDS data in Figure2-5 clearly show that the down-ward shift of threshold voltage (VT) occurs when SDR MOS transist or is scaled from 0.30 to 0.22 m. The exact dependence of threshold voltage on channel lengt h can be extracted from the low-VDS measurement results, which is plotted in Figure2-6 When biased at low over-drive condition (VGS ~ 1.0 V), these SDR Figure 2-5.Normalized ID-VGS for different SDR MOS transistors at VDS = 1.8 V. 0.0 0.2 0.4 0.6 0.8 0.01.02.03.0 10-1410-1210-1010-810-610-4ID / width (mA/ m)ID / width (A/m)VGS (V) 0.22m0.24m0.26m0.28m0.30m V GS V T V GS V T 1 2 -V DS W L ----V GS V T 1 2 -V DS 3.3V T 0.9 =

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36 MOS transistors are in saturation region and the dr ain current improvement in percentage is even more dramatic than high over-drive case (VGS ~ 3.0 V). This is because, when VGS approaches threshold voltages (VT), the term is a stronger function of VT, and gives a more significant current increase in percentage. As shown in Figure2-6 the threshold voltages of SDR MOS transistors abruptly drops when the channel length is shorter than 0.35 m, the minimum design rule specification. It is expected that at certain point, the threshold voltage can be nega tive, which means this SDR MOS structure will be always on and is no longer a normal transi stor. This threshold voltage change sets the lower limit for the channel length of a func tional SDR MOS transistor. An SDR MOS transistor can not be much lower than 0.22 m in this particular CMOS process. Once again in Figure2-5 the logarithm scale plots on the le ft side reveal the subthreshold characteristics of these SDR MOS transist ors. Unless the channel length reaches 0.22 m, all Figure 2-6.Measured threshold voltages of SDR MOS transistors with different channel lengths. 0.00.2 0.4 0.5VT (V)L ( m) 0.0 0.2 0.4 0.6 0.8 1.0 0.30.6VGSVT 2

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37 SDR MOS transistors have almost same subthreshold slope and nor mal subthreshold behaviors. Higher subthreshold currents are as expected fo r the SDR MOS transistors because the threshold voltage is lowered. However, the drain leakage current at VGS = 0 V is still well below 1 nA/ m and considered within the controllable scope [ SIA05 ]. Within a certain range of channel lengths, we do have some opportunities for opt imization of SDR MOS transistors. 2.3.2 Voltage Handling Capability The breakdown voltage (VBK) sets the maximum voltage that can be applied either across the drain and source, or acro ss the gate and drain. When VDS approaches the breakdown voltage, the drain current of device rapidly increases, even abruptly jumps which should be always avoided. Therefore, a sufficient vol tage margin should be reserved between the transistors operational voltages and its breakdown voltages. When breakdown occurs, ID VDS curves will bend the most. We can expect the greatest curvat ure around the breakdown voltage along the curves. For consistency and ease of comparison, breakdow n voltages for these MOS transistors are measured at the drain-to-source voltage (VDS) when the second derivatives of ID to VDS reach the maximum. The lowering of breakdown voltages in SDR MOS transistors is one of the most important effects resulting from fu rther scaling down of the channel length. Listed in Table2-1 are the meaL ( m) 0.220.240.26 (SDR-26) 0.280.300.35 (3.3-V) VBK (V) VGS=1.0/ 1.4 ~ 4.7~ 4.8~ 5.0~ 5.1~ 5.3~ 6.4 VGS=0 -~ 8.4 ~8.4~8.4 ~ 8.6 Table 2-1.Breakdown voltages of s ub-design-rule MOS transistors

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38 sured breakdown voltages of SDR MOS transistors, together with that of the conventional 3.3-V MOS transistor. At VGS = 1.0 / 1.4 V, the breakdown voltages of these SDR MOS transistors drop from that of the 3.3-V transi stor by 1.1 ~ 1.7 V. The reason is that the punch-through between the drain and source occurs more easily when the channel b ecomes shorter. This effect limits the maximum voltage that can be applied to the drain node of SDR transistors. We need to sacrifice some voltage handling capability to obtain the curren t advantage of these SDR transistors. In Section 2.3.3, there will be more discussions on the proper se lection of channel length of SDR MOS transistors particularly for the 3.3-to-1.8V level shifter application. The off-state breakdown vol tages measured at VGS = 0 V show no obvious degradation due to the scaling of the SD R MOS transistors down to 0.26 m. The gate oxide of SDR transistors is shorter than the conventional 3.3-V transistor while the thickness is the same as that of the conventional transistor. The gate dielectric layer should sustain similar volta ge across it, either between the drain and gate, or between the gate and source. Th is means that these SDR MOS transistors can tolerate as much gate-to-drain voltage (VGD) as the conventional 3.3-V MOS transistor. Therefore, the gates of SDR MOS transist ors can be biased up to 3.3 V without excessively stressing the MOS structures. 2.3.3 Optimization of MOS Transist ors for Level Shifter Application The 3.3-to-1.8-V level shifter circuit is an ex cellent example of digital application for SDR MOS transistors. The conventiona l 3.3-V MOS transi stors (M5/M6 in Figure2-2 ) can easily be replaced by the SDR MOS transist ors for drive current enhancement. Because the gate oxide layer of SDR MOS tr ansistors is sufficient to handle the 3.3-V swing from the preceding circuitr y, there is no undermining of volta ge tolerance at its gate node.

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39 On the drain side, the SDR transistors replaci ng M5/M6 only need to sustain 1.8-V, instead of 3.3-V swing. The breakdown voltage necessary for the 1.8V operation could be lower. The voltage margin (VBK-VDD) reserved for the conventional 3.3V MOS transistors with 3.3-V supply voltage is about 3.1 V (6.4V-3.3V). The measurement results in Table2-1 indicate that the 0.26m long SDR transistor (SDR-26) has high e nough breakdown voltage (~ 5.0V), so that an adequate margin (5.0V-1.8V=3.2V) is kept for it s operation with 1.8-V supply. Furthermore, in this level shifter application, the gates of drive transistors (M5/M6) are sw ept quickly from 0 V to 3.3 V, with drain biased no higher than 1.8 V. Th e drive transistors enter linear region almost instantaneously, and for only a sm all portion of time the transistors stay in saturation region. Because of these, the level shifte rs using the SDR-26 tran sistors should be resi stant to the hot-carrier related performance degradation [ Tak95 ]. Figure 2-7.Comparison of normalized ID-VDS between SDR-26 and conventional 3.3-V MOS transistors. 0.01.02.03.0 VDS (V) 0.0 0.2 0.4 0.6 0.8 1.0ID /width (mA/m) SDR-26 3.3-V 0 ~ 1.8V VGS= 2.8V 2.3V 0.8V 1.3V 1.8V 2.8V 2.3V 1.8V 1.3V 0.8V 3.3V 3.3V

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40 The SDR-26 MOS transistor is 26% shorter than the conve ntional 3.3-V transistor. Its threshold voltage is 0.66 V, whic h is 0.18 V lower than that of the 3.3-V transistor. When M5/M6 in Figure2-2 are replaced by SDR-26 MOS transistors, the gate overdrive (VGS-VT = 3.3-VT) is increased by about 7%. The ID per unit width ( m) versus VDS curves of SDR-26 and 3.3-V MOS transistors are shown in Figure2-7 Biased at the same gate-to-source voltage (VGS), the SDR-26 MOS transistor delivers more than 1.28 times th e current of the 3.3-V transistor. In Figure2-8 the ID-VGS curves of SDR-26 and 3.3-V transi stors are also compared. The line ar scale plots once again show that the drain current of the SDR-26 transistor is at least 1.28 times that of the 3.3-V transistor, and this current enhancement is even more substantial for low VGS (~ 1 V). The shaded area in Figure2-8 clearly illustrates the current increase. Figure 2-8.Comparison of normalize ID-VGS between SDR-26 and conventional 3.3-V MOS transistors in both linear and logarithm scales, when VDS = 1.8 and 0.05 V. 0.01.02.03.0 VGS (V) 0.0 0.2 0.4 0.6 0.8ID / width (mA/m) 10-1410-1210-1010-810-610-4ID / width (A/m) SDR-26, VDS=1.8V 3.3-V, VDS=0.05V SDR-26, VDS=0.05V 3.3-V, VDS=1.8V

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41 Normal subthreshold behavi ors can be observed by the logarithm scale plots in Figure2-8 SDR-26 and 3.3-V MOS transistors have same subthreshold slopes at both low and high VDS, indicating the short channel effect s are still well controlled in SD R-26 MOS transistors. The leakage current of SDR-26 transistors at high VDS is increased to 10-12 from 10-14 A/ m, which is still lower than the specification for low voltage transistors in more advanced CMOS processes [ SIA05 ]. Additionally, since the number of I/O drive transistors used in an integrated circuit is limited, this increased leakage is tolerable. 2.4 Capacitance Property of SDR-26 MOS Transistor Speed performance in digital circuits usually can be evaluated by the propagation delay ( d), as well as the rise time ( r) and the fall time ( f). From Equation 2-3 we can see both the current drive capability of preced ing stage and gate capacitance (Cload) as the load to preceding stage strongly affect the speed performance. (2-3) All data compared above, however, are meas ured at the same channel width (W) for SDR-26 and 3.3-V MOS transistors. Compared to the 3.3-V transistors with unit width, the SDR-26 transistors have the same gate-oxide th ickness but shorter length, therefore less gate capacitance. For a fairer comparison, the drain current should be normaliz ed to the same gate capacitance. Therefore, it is necessary to study the dependenc e of gate capacita nce on the channel length of SDR MOS transistors. Approximately, the gate capacitance (CGS) of MOS structures has the linear relation with length L as shown below: Io d Cload VIo--------------------=

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42 ,(2-4) where, represents the constant for saturation re gion or linear region. Simulation data of longer-channel 3.3-V thick-oxide MO S transistors between 0.35 and 1.0 m long are plotted in Figure2-9. The unit gate capacitance of 0.35m long 3.3-V MOS transistors is 1.67 fF/ m as simulated. The linear fi tting line is drawn in Figure2-9, and it can be used to extrapolate the gate capacitance (CGS) of SDR MOS transistors. Th e SDR-26 MOS transistor of interest is expected to have unit gate capacitance of 1.33 fF/ m, which is only 79.6% of that of the minimum length 3.3-V MOS transistors. Compared at the same gate capacitance whic h acts as the load to preceding stage, a SDR-26 transistor is 25.6% wider and this increases its drive current to about 60% higher than that of the conventional 3.3-V MOS transistor. C GS C GSO W C ox WL + = Figure 2-9.Simulated gate ca pacitance of longer channel 3.3-V MOS transistors, and extrapolated gate capacitance of SDR-26 MOS transistors. 0.00.20.40.60.81.0 Channel Length (m) 0.0 1.0 2.0 3.0 4.0 5.0Gate capacitance / width (fF/m) Longer Channel 3.3-V Extrapolation (0.26m, 1.33fF/m)(0.35m, 1.67fF/m) SDR region

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43 2.5 High-to-low Level Shifter Speed Performance Between SDR-26 and 0.35m long conventional 3.3-V MOS tran sistors, the increases of drain current in both fixed channel width and fixe d gate capacitance cases are described in the previous sections. To interpret such improvements to the speed performance in a level shifter circuit, Cadence Spectre simulator is used to estimate the difference. At first, modeling of SDR-26 MOS transist ors is necessary. Based on the conventional 3.3-V transistors model file, we built a model to approximately describe the behavior of the SDR-26 transistor by modifying a few parameters, such as gate oxide thickness (tox), threshold voltage (vth0), mobility (u0) and saturation velocity (vsat) (see APPENDIX ). Shown in Figure2-10 are the simulated ID-VDS and ID-VGS for both the SDR-26 and 3.3-V MOS transistors, with the same channel width. The plots matc h the measurement result s. This simulation conFigure 2-10.Simulated ID-VDS and ID-VGS curves of the SDR-26 and 3.3-V MOS transistors. The simulations also match the measured currents for both types of transistors. measured simulated0.01.02.03.0 VDS / VGS (V) 0.0 0.2 0.4 0.6 1.0ID / width (A/m)0.8ID-VDS of SDR-26 ID-VDS of 3.3-V ID-VGS of 3.3-V ID-VGS of SDR-26 VGS = 3.3 V VDS = 1.8 V

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44 firm that the created model file gives 1.28 ti mes the drain current of the conventional 3.3-V transistors. The SDR-26 and 3.3-V MOS transist ors have gate capacitance of 6.23 and 7.85 fF, respectively, so that the capac itance ratio is 0.79. These changes reflect the measured improvement of current drive ca pability discussed in Section 2.3.3 and gate capacitanc e change discussed in Section 2.4 Secondly, the same 3.3-to-1.8-V le vel shifter structure shown in Figure2-2 is used in simulation. Two versions of level shifters under comparison are shown in Figure2-11 Version A repFigure 2-11.Schematics of level shifter circuits in simulation. Version A uses conventional MOS transistors as driv e transistors, wh ile Version B uses SDR-26 MOS transistors. B1 B2 B3 B5 B6 B7B4 A1 A2 A3 A5 A6 A7A41.8V 1.8V SDR-26 conventional 3.3-V input outputA 3.3-V inverter 1.8-V inverter 3.3-V circuitry 1.8-V circuitry level shifter A outputB Version AM2AM1AM2BM1Blevel shifter B Version B

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45 resents the conventional implement ation, and the conventional 3.3-V MOS transistors are used as the drive transistors (M1A/M2A) in the level shifter. The 3-st age 3.3-V inverter chain (A1 through A3) preceding the level shifter generates an input signal whose shape is approximately independent of the number of propagation stages. Similarly, the 3-stage conventional 1.8-V inverter chain (A5 through A7) is also used following the level shifter to maintain the same capacitive loading for the level shifter [ Tau98 ]. All these inverters use th e conventional 3.3/1.8-V nMOS/pMOS transistors. The version B is the same as vers ion A, except that the two drive transistors (M1B/ M2B) are replaced by the SDR-26 MOS transistors. These two SDR-26 transistors in version B are 26% wider than their counterpa rts in version A, so that the inverters A3 and B3 will see the same capacitive loads. In Figure2-12 both the pull-down and pull-up cases for th e level shifters are examined. In both Figure2-12 (a) and (b), th e input signals ( Figure2-11 ) for different implementations are the same and overlaid. This is possible because the dr ive transistors of these two versions give the same capacitive load to the preceding stages The same input signals with 3.3-V swing are delayed differently and level-shif ted to output signals with 1.8-V swing. The time differences of output signals for both pull-down and pull-up cases directly show the im proved speed performance of the level shifter implemented by usin g the SDR-26 transistors over the conventional 3.3-V transistors. The data extracted from the waveforms are listed in Table2-2 including the pull-down propagation delay ( n) and the pull-up propagation delay ( p), and the fall time ( f), the rise time ( r). A nearly 20% improvement in the propagation delay is expect ed from this 3.3-to-1.8-V level shifter circuit using SDR-26 MOS transistors. This speed improve ment is obtained without any

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46 process modifications, therefore using SDR-26 transistors is a low-cost solution. There is no change in the circuit configuration. Figure 2-12.Comparison of the SDR-26 a nd conventional 3.3-V MOS transistors used as the drive transistors in 3.3-to-1.8-V level shifters. (A) ) propagation delay in pull-down case ( n); (B) propagation de lay in pull-up case ( p). outputA outputB input outputA outputB input A B n Bn A p Ap B

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47 2.6 Summary Level shifters are crucial for di gital CMOS I/O interface circui ts to translate different voltage levels back and forth. Level shifting needs extra stages, and introduces extra delays, which should be limited to minimum. In a high-to-low leve l shifter, the drive transi stors have to be realized by using thick-oxide high-vol tage MOS transistors to withstand the high voltage swing at gate node. The drain nodes of driv e transistors, however, only need to handle low voltage swing. These characteristics of high-to-low level shifte rs provide the opportuniti es for use of SDR MOS transistors which have highe r current drive capability. In this chapter, a 3.3-to-1.8-V level shifter circuit using a 0.18m CMOS foundry technology is studied. The conventional 3.3-V MOS transistor is compared to a series of thick-oxide SDR MOS transistors. The measurement results s how that, in this par ticular application, the 0.26m long SDR MOS transistor (SDR-26) can deli ver 1.28 times the drain current as the conventional one, while maintaining su fficient breakdown voltages to to lerate the signal swing at the gate and drain nodes. When replacing the convent ional 3.3-V drive transist ors in the 3.3-to-1.8-V level shifter, the SDR-26 transi stors are 25.6% wider and can provi de 60% more drain current. In version A (conventional 3.3-V) version B (SDR-26) delay improvementpull-down delay (ps) nA = 28.2 nB = 23.516.7% pull-up delay (ps) pA = 47.4 pB = 38.2 19.4% fall time (ps) fA = 64.67 fB = 47.55 26.5% rise time (ps) rA = 100.94 rB = 66.94 33.7% Table 2-2.Speed performance of level shif ters using the SDR-26 and conventional 3.3-V MOS transistors as the drive transistors

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48 simulations, this current enhancement translates into a nearly 20% reduction in the propagation delay. The use of SDR MOS transistors in the high-t o-low level shifters should not be limited only to this 0.18m technology by all means. This concep t should be viable in other more advanced technologies. In general, this applicat ion of SDR MOS transistors provides another way to exploit the scaling of CMOS technologies. This study shows th at further scaling and optimizing the thick-oxide MOS devices are feasib le and can provide useful benefits.

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49 CHAPTER 3 LOW-TO-HIGH LEVEL SHIFTER APPLICATION 3.1 Introduction Another circuit needed in the input/output (I/O) blocks is a low-to-high level shifter circuit. Figure3-1 shows the schematic of a convent ional low-to-high level shifter [ Koo05 Tan02 ]. Thick-gate-oxide high-volta ge MOS transistors are used as th e drive transistors (M15/M17) here, because they have to sustain high-VDD signal swing at the drain nodes. A problem with this implementation is that the gates of thick-gate -oxide high-voltage driv e transistors (M15/M17) with higher threshold voltage are driven by a ci rcuit whose output switches only between 0 and Figure 3-1.Typical low-to-high level shifter, using thick-ga te-oxide drive transistors at the interface between low-VDD and high-VDD circuitries. High-VDDLow-VDDDrive Transistors Out In M14 M18 M20 M19 M17 M16 M15 M13 Thin-gate-oxide TransistorsT hick-gate-oxide Transistors M12 M11 Level Shifter

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50 low-VDD. Because of this, th e gate overdrive (VGS-VT) is small, thus the drive current is limited. These in turn limit the switching speed of I/O circuits. In the previous chapter, we have studied a typical 3.3-to-1.8-V CMOS level shifter, and the way to improve the speed perf ormance by using the SD R MOS transistors. C ould this idea of using thick-oxide sub-desi gn-rule (SDR) MOS transi stor become an inspiration to build another structure suitable for low-to-high level shifter circuits? Extensive efforts have been ta ken to improve the voltage a nd power handling capability of the MOS transistors, while still keeping the drain current and gm high [ Ma99 Buc03 Lia03 Men04 ]. In these cases, geometry and/or doping profile need to be modified. Unfortunately, these solutions usually are either incompatible with standard CMOS technologi es, or require certain modifications to existing foundry proces ses and increase the fabrication cost. In this chapter, we want to take advantage of the SDR MOS tr ansistor concept, and build a novel composite structure suitable for use in the low-to-h igh level shifter, which is fully compatible with the standard CMOS processes fro m the foundries. 3.2 Composite MOS Transistor Structure As discussed, the thin-gate-oxide MOS transist or has higher unit drain current and faster speed performance. This device is suitable for low power circuits because the voltage tolerance is limited. On the contrary, the th ick-gate-oxide MOS transistor has lower unit drain current and slower speed performance. However, this type of device is prefer able for high vo ltage, high power situation due to the thicker gate dielectric layer. To combine the advantages of these two types of MOS devices, a composite MOS transistor structure is proposed in this chapter [ Xu05 ]. The composite MOS transistor consists of a series combination of a conventional thin-oxide transistor (TN sub-tr ansistor) and a sub-design-rule th ick-oxide sub-transistor (SDR

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51 sub-transistor). A layout of such a co mposite MOS transist or is shown in Figure3-2 A multiple-finger layout is employed, and two ce lls are shown here as illustration. The cross-section along dashline AB (see Figure3-2 ) is also drawn in Figure3-3 The TN sub-transistor and SDR s ub-transistor share an n+ diffusion region in the middle without metal connection. The diffusion on the left side of TN sub-transistor acts as a source, and the diffusion on the right side of SDR sub-transistor acts as a drain. Their polysilic on gates are connected together by metal layers to form a single gate, and their bodies ar e connected together through the p-substrate. Such a four-termina l structure functions as a single MOS transistor. The equivalent circuit of the composite MOS tr ansistor as well as its simp lified version are shown in Figure3-4. Compared to the conventional thin-oxide tran sistor (TN sub-transi stor), the composite transistor has lower drain current due to the addi tional SDR sub-transistor in series combination. Poly Gate 1 Drain Source Thick Oxide Mask Implant Mask Diffusion Mask Poly Gate 2 A B Figure 3-2.Layout of the composite MOS tr ansistor. Only 2 cells are shown here.

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52 On the other hand, the SDR sub-transistor helps the composite transistor to tolerate a larger voltage drop across its drain and gate, and across its drain and source than the thin-oxide transistor. This of course increases the break down voltage of composite transist or structure compared to that of the thin-oxide transistor alone The composite structure is sim ilar to the cascode configuration with a common gate stage using a thick-oxide transistor, which ha s been proposed to improve the voltage handling capability [ Web03 ]. However, besides the gate connections, another key difference is that the channel length of SDR sub-transistor is signifi cantly shorter than the minimum length of the conventional thick-oxi de transistors. This modificati on increases the drain current. Because of the strong short channel effects, the SDR sub-transistor has lower threshold voltage and the dramatically increased leak age current if it is used with a 3.3-V supply. Therefore, such an SDR sub-transistor does not work normally by its own, and should be used in series combination with a conventional TN sub-transist or. It is expected that the dr ain current of the composite MOS p-substrate POLY Thin Oxide Thick Oxide Source Drain Substrate Gate2 Gate1 n+ n+ n+ SDR Sub-transistor TN Sub-transistor Shared Diffusion F igure 3-3.Cross-section of th e composite MOS transistor.

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53 transistor is somewhere in between those of the conventional thick-oxide and conventional thin-oxide transistors, as will be discussed in the following sections. 3.3 Composite MOS Transistors in a 0.18m Process The first composite MOS transistor was fabricated in the same 0.18m CMOS technology as the SDR MOS tran sistors discussed in Chapter 2 This composite stru cture will be referred as composite-18 transistor and it consists of a 0.18m long thin-oxide transistor (TN transistor) and a 0.18m long thick-oxide transistor (SDR-18 sub-tr ansistor). This combination of channel lengths is intended to diminish the drain current degradation caused by the SDR transistor in series. However, having this th in oxide as part of the gate inevitably sets the maximum gate-to-source voltage to 1.8 V. Figure 3-4.Equivalent schematics of the composite MOS transistor. Drain Source Sub TN Sub-transistor SDR Sub-transistor Gate1 Gate Gate2 Drain Source Sub Gate

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54 To study its possible advantages ove r conventional transistors, a 0.35m long 3.3-V thick-oxide and a 0.18m long 1.8-V thin-oxide MOS transistor were also fabricated in the same technology for comparison. All the transist ors have the same channel width (23.25 m). The layout of the DC test structures is shown in Figure3-5 A semiconductor parameter analyzer (HP4155A) and a DC probe station are employed for the measurements. 3.3.1 Current and Breakdown Characteristics Figure3-6 shows the measured ID per unit width versus VDS. The gates of composite-18, conventional 3.3-V and 1.8-V transist ors are biased up to 1.8 V, 3.3 V and 1.8 V, respectively. The composite-18 transistor at VGS = 1.8 V can deliver as much curren t as the 3.3-V transistor biased at VGS = 3.3 V. If biased at the same gate voltage (VGS = 1.8 V), the compos ite-18 transistor provides about 3 times of the saturati on current of the 3.3-V transistor. This drive capability is even comparable to that of a 1.8-V transi stor. This result is surprisingly good. Transistors G D S B G2 G D S B G1 D S B Figure 3-5.Test structure layout of the composite-18, conventional 3.3-V thick-oxide and conventional 1.8-V thin-oxi de MOS transistors for DC measurements.

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55 The breakdown voltages (VBKs) and threshold voltages (VTs) of these three types of transistors are listed in Table3-1 The composite-18 transistor ha s comparable breakdown voltage as the 3.3-V transistor. This is a bout 50% higher than that of the 1.8-V transistor. Furthermore, the composite-18 transistor still has the same low threshold voltage as that of the 1.8-V transistor, which is 0.4 V below that of the 3.3-V transistor. This in turn fu rther increases the current drive capability of the composite-18 transistor compared to that for the conventional 3.3-V transistor. 0.01.0 2.0 3.0 VDS (V) 0.0 0.2 0.4 0.6 0.8ID / width (mA/m) composite-18 1.8-V 3.3-V 1.8V 1.3V 0.8V 0.3V1.3V 0.3V 0.8V 1.8V 3.3V 2.8V 2.3V 1.8V 1.3V Figure 3-6.Normalized ID-VDS of the composite-18, c onventional 3.3-V thick-oxide and conventional 1.8-V thin -oxide MOS transistors. 3.3-Vcomposite-181.8-V VBK (V) VGS=0~ 9.0~ 9.0~ 6.5 VGS=1.8/3.3~ 5.5~ 6.5~ 4.0 VT (V)VDS=0.05~ 0.9~ 0.5~ 0.5 Table 3-1.Breakdown voltages and threshol d voltages for the composite-18, and the conventional 3.3-V and 1.8-V MOS transistors

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56 3.3.2 Subthreshold Current Leakage Issues As shown in Figure3-7 the ID-VGS curves in a logarithm s cale reveal the subthreshold behaviors of the composite-18, conventional 3.3-V and 1.8-V MOS transistors. For low VDS cases (VDS = 0.05 V), all th ree types of transistor s have the same subthr eshold slopes and the normal subthreshold behavi ors can be observed. Ho wever, when the VDS is biased at VDD (3.3 V for the composite-18 and 3.3-V transistors, 1.8 V for the 1.8-V transistors), the composite-18 transistor obviously has abnormal subthreshold behavior compared to the other two conventional transistors. The drain leakag e current of the compos ite-18 transistor around VGS = 0 levels off, and is significantly higher than expected. The cause of this behavior is that abnormall y high voltage is present at the shared diffusion region of the co mposite structure (VM (a) in Figure3-8 (a)), producing higher leakage current Figure 3-7.ID-VGS curves in a logarithm scale for the composite-18, conventional 3.3-V and 1.8-V MOS tr ansistors with VDS = 0.05 V and VDD (1.8/3.3 V). 0.01.02.03.0 10-1410-1210-1010-810-610-410-2 composite-18 1.8-V 3.3-V VGS (V)ID (A)VDS = 1.8/3.3 V VDS = 0.05 V ( s u b t h r e s h o l d r e g io n )

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57 through the drain to body [ Cha01 ]. We are not able to directly measure the voltage at this node (VM (a)) because there is no pad connection for the node in the test structure. However, this problem can be solved by using source current matching to calculate the voltage of the shared diffusion region. Using two DC test structures, the currents at any nodes of the co mposite-18 and the 1.8-V transistors can be measured sepa rately. The gate current is usually negligible, and other current Figure 3-8.Illustration of source current matching be tween (A) the composite-18 transistors and (B) the conven tional 1.8-V MOS transistors. n+ n+n+ IS (a)IS (a)ID1 (a)IB1 (a)ID (a) = ID2 IB (a) = IB1 (a) + IB2(TN Sub-transistor)(SDR Sub-transistor) IB2VDp-substrate n+n+ IS (b)IS (b)IB1 (b)ID (b) = ID1 (b) IB (b) = IB1 (b)(1.8-V Transistor) VM (b)p-substrate B A VM (a)

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58 paths in the composite-18 and conventional 1.8V MOS transistors are shown together in Figure3-8 It is obvious that, the source currents (IS (a), IS (b)) are for the composite-18 transistor, ,(3-1) for the 1.8-V transistor, .(3-2) The TN sub-transistor is exactly the same structure as the conventional 1.8-V transistor, therefore each of the source current (IS (a) and IS (b)) is the same monotonic function of VM (a) and VM (b). Despite the discrepancy in th e drain current or the body curren t between the two transistor structures, each of the transistors should have the same VM (i.e., VM (b) = VM (a)) when the source currents are same (IS (a) = IS (b)). Therefore, we can match the source currents of the these transistors, and get the voltage of shared diffusion region (VM (a)) by reading the drain voltage of the 1.8-V transistor (VM (b)). The IS-VDS curves of the composite-18 and 1.8-V MO S transistors are drawn together in Figure3-9 to demonstrate the method of source current matching. When VGS is between 1.0 and 0.4 V as shown in Figure3-9 (a), the matched voltages at the shared diffusion region (VM (a)) are only between 1.4 and 1.8 V. Just like what we have seen in Figure3-7 there is no significant increase of the drain leakage current. When VGS is further lowered as shown in Figure3-9 (b) and (c), however, it is evident that the matched voltage (VM (a)) increases quickly and could be higher than 2.2 V. This is consistent with the deviati on of subthreshold current from the normal seen in Figure3-7 The worst case occurs at VGS = 0 V, when the matched voltage at the shared diffusion IS a ID a IB a ID2IB2IB1 a + ID1 a IB1 a === IS b ID b IB b ID1 b IB1 b ==

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59 Figure 3-9.Calculation of the voltage at the sh ared diffusion region (VM (a)) by using source current matching. (A) VGS=1.0~0.4 V; (B) VGS=0.3~0.2 V; (C) VGS=0.1~0.0 V 0.0 1.0e-3 2.0e-3 3.0e-3 4.0e-3 0.0 5.0e-7 1.0e-6 1.5e-6 2.0e-6 0.01.02.03.0 0.0 2.0e-9 4.0e-9 6.0e-9 8.0e-9 0.01.02.03.0 0.01.02.03.0VM (b) or VD (V)IS (A) IS (A) IS (A) B A CVGS=0.1 VGS=0.0 VGS=0.2 VGS=0.3 VGS=1.0 0.9 0.8 0.7 0.6 0.5 0.4 composite-18 1.8-V VM (a) = VM (b) VM (a) = VM (b) VM (a) = VM (b) composite-18 1.8-V matched VM (a) composite-18 1.8-V matched VM (a) composite-18 1.8-V matched VM (a)

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60 reaches the highest. This increased voltage (VM (a)) at the shared diffusi on is higher than the nominal value (1.8 V), and it can cause the gate-oxi de wear-out and the hot -carrier re lated performance degradation in the TN sub-transistor. This undermines the reliability of the composite-18 transistors even though VM (a) is not sufficient to caus e breakdown. Therefore, the 0.18m long SDR sub-transistor can not sustain sufficient voltage drop to protect the TN sub-transistor. In this 0.18m CMOS process, an SDR s ub-transistor with a chan nel length longer than 0.18 m is necessary for the composite transistor. Because of these, the composite MOS transi stors should not only be checked for the breakdown voltages, but also checked for the subthreshold leakage currents to assure that each sub-transistor inside the composite structures is reliable throughout the operation voltage ranges. 3.4 Composite MOS Transistors in a 0.13m Process In the second realization, a seri es of DC test structures of different composite MOS transistors with the same width (2.96 m) is fabricated in a foundry 0.13m CMOS technology. The TN sub-transistors in all these composite tran sistors have the minimum length for conventional 1.2-V transistors, which is 0.12 m. The SDR sub-transistors of th ese structures include lengths of 0.20, 0.22, 0.23, 0.25, and 0.27 m. The lengths of the SDR sub-transistors are used as the names of different composite transistors, for instance, composite-27 and so forth. Figure3-10 shows the layout of a DC test stru cture. For better die area effici ency, the DC pads for drain and body node connections are shared by three transistor structures. In the same process, the conventional 0.12m long 1.2-V thin-oxide tran sistor and conventional 0.34m long 3.3-V thick-oxide transistors are also fabricated for comparison.

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61 3.4.1 Current Characteristics ID-VGS curves of the composite MOS transistors at VDS = 3.3 V are compared to those of the conventional 3.3-V an d 1.2-V transistors in Figure3-11 The drain currents in the plot are normalized to unit channel width. As shown in the linear scale plots in Figure3-11 reducing the length of thick-gate-oxide SDR sub-transistor in the com posite structure from 0.27 to 0.20 m significantly increases the drain current, and makes the drain current appro ach that of the conventi onal 1.2-V transistor. For example, between the composite-20 (0.20m long SDR transistor) and composite-27 (0.27m long transistor), the current ratio at VGS = 1.2 V is more than 2. Even though it is not straightforward to calculate the effective ratio for thes e composite transistors, the use of thick-oxide SDR MOS structures in the compos ite transistor design contributes to the drain current increase. In addition, the threshold voltage of SDR sub-transistor decreases when it is scaled, as discussed in Section 2.3 The SDR sub-transistor se ts the limit for channel fo rmation, until its threshold voltage is lowered to that of the TN sub-tr ansistor. When the SDR sub-transistor is scaled Figure 3-10.Test structure layout of a gr oup of the composite MOS transistors for DC measurements. SG1G2G3B D1D2D3composite transistors W L ----

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62 from 0.27 to 0.22 m, the threshold voltage of the com posite transistor d ecreases. The high-VDS measurement results in Figure3-11 show the down-ward shift of threshold voltage (VT) with the SDR sub-transistor length. The thre shold voltages of the composite transistors extracted from the low-VDS measurement data are listed in Table3-2 These values are closer to that of the 1.2-V transistor, rather than to that of the 3.3-V tran sistor. The composite-22 transistor has about the Figure 3-11.Normalized ID-VGS plots for the composite and the conventional 3.3-V transistors with VDS = 3.3 V, and the conventi onal 1.2-V transistor with VDS =1.2 V. 0.01.02.03.0 0.0 0.2 0.4 0.6 0.8 composite 1.2-V 3.3-V 10-1310-1110-910-710-510-3 ID (A)VGS (V)ID (mA)comp-20 comp-22 comp-23 comp-25 comp-27 transistors1.2-Vcom-22com-23com-25com-273.3-V VT(V)~ 0.46~0.46~ 0.48~0.52~0.56~ 0.72 Table 3-2. Measured threshold voltages of the composite transistors, and the conventional 1.2-V, 3.3-V transistors

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63 same threshold voltage as the conventional 1.2-V transistor, which is 0.26 V below that of the 3.3-V transistor. In the case of 1.2-to-3.3-V level shifter, the overdrive (VGS-VT) of drive transistor is relatively small (~ 0.5 V) and can be significantly increased in percentage by decreasing the threshold voltage. When biased at the maximum gate voltage (VGS = 1.2 V), the drive transistors are still in saturation re gion. Therefore, the square of overdri ve for the composite-20 and composite-27 transistors, for in stance, can differ by about .(3-3) As discussed, the voltage protection for the TN sub-transistor is de graded when its SDR sub-transistor becomes shorter. To examine this important aspect of the composite MOS transistors the subthreshold behaviors, ID-VGS curves are plotted in logarithm scale in Figure3-11 In the first case, the drain leakage current of compos ite-27 MOS transistor is well below that of the conventional 1.2-V transistor. This is because the voltage at the shar ed diffusion region (VM (a)) is well below 1.2 V. The 0.27 m length for SDR sub-transistor is too long, and the drain current increase is limited. For the composite-20 transistor, the drain leakage current around VGS = 0 V is even higher than that of the 1.2-V transistor. When the drain is biased at 3.3 V, the 0.20m long SDR sub-transistor did not sustain sufficient voltage drop so that the voltage at the shared diffusion is higher than 1.2 V and the drain current is increased. This leads to potential reliability issues at the shared diffusion region insi de the composite-20 transistor structure. Between these two extreme cases, the compos ite-22 MOS transistor has the similar subthreshold characteristics as the 1.2-V transist or, including that for th e worst case when VGS = 0 V. This indicates that the voltage of the shar ed diffusion region goe s up to 1.2 V. The 0.22m long V GS V T20 2 V GS V T27 2 --------------------------------------1.20.46 2 1.20.56 2 ------------------------------1.34 ==

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64 SDR sub-transistor provides suffic ient voltage protection to the 0.12m long TN sub-transistor for the whole 3.3-V operating range. This is also consistent with the th reshold voltage measurement results which suggest that the channel formation is no l onger hindered by the SDR sub-transistor. The combination of channel lengths in the com posite-22 transistor gi ves a better trade-off between the drive current capability and the reli ability property, and the composite-22 MOS transistor is the optimal for the use as the drive transistors in the 1.2-to-3.3-V level shifter circuits. 3.4.2 Voltage Handling Capability The breakdown voltage (VBK) sets the maximum voltage that can be applied either across the drain and source, or acro ss the gate and drain. When VDS approaches the breakdown voltage, drain current of the device increases rapidly, even jumps abruptly which should be always avoided. Therefore, sufficient voltage margin s hould be reserved between the transistors operational voltage range and its br eakdown voltages. The same meas urement method for breakdown voltage described in Section 2.3.2 is employed here for the compos ite transistors, and the results are listed in Table3-3 together with those of the conventional 3.3-V and 1.2-V MOS transistors. While the threshold vo ltages are close to that of the conventional 1.2-V transistor, the composite MOS transistors have comparable brea kdown voltages as that of the 3.3-V transistor, Transistorscomp-20comp-22comp-233.3-V1.2-V VBK (V) VGS=1.2~8.9~ 9.2~9.5~ 6.1~ 3.4 VGS=0 ~7.0 ~9.0 ~9.0 ~ 7.5~ 4.6 Table 3-3.Breakdown voltages for the composite transistors, and the conventional 3.3-V and 1.2-V transistors

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65 which is around two times that of the 1.2-V transi stor. The breakdown voltages of composite transistors significantly increase when the SDR sub-tr ansistors are added. The reason is that before the VDS reaches the breakdown voltage, a large porti on of the voltage is dropped across the SDR sub-transistor, and the shared diffusion region is kept below the breakdown voltage of the 1.2-V transistor. This in turn allows the drain nodes of the composite MOS transist ors to be biased at a higher voltage. When the SDR sub-transistor is longer, the pr otection from or the voltage drop across the SDR sub-transistor increases, therefore the breakdown voltage of the composite structure becomes higher. Among the different composite st ructures, the composite-22 MOS transistor is the shortest one which has sufficient breakdow n voltage for 3.3-V s upply operation. This high voltage handling capability is combined with th e low threshold voltage of the conventional 1.2-V transistor. Having the thin-oxide as part of the gate in the composite MOS transistor structures sets the maximum gate-to-source voltage (VGS) to only 1.2 V. However, the asymmetric composite structures, from the gate to the drain, make it almost ideally suited for the asymmetric voltage swings in the 1.2-to-3.3-V level shifter circuits. 3.5 Composite MOS Transistor Capacitance Property The speed performance of digital circuits usually is evaluated by propagation delay ( d), as well as the rise time ( r) and the fall time ( f). Equation 2-3 indicates that both current drive capability of preceding st age and gate capacitance (Cload) as the load to the preceding stage determine the speed performance. The data compared in Section 3.4 however, are measured at the same channel width (W) for all transistors. The transistor struct ures have different gate capacIo

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66 itance due to different channel lengths. For a fairer comparison of current drive capability, the drain current should be normalized to the same gate capacitance. The AC test structures of composite and c onventional transistors ar e fabricated in the same 0.13m CMOS technology mentioned in Section 3.4 All transistors have the same channel width of 44.4 m. Figure3-12 shows the layout of four of these AC structures. The ground pads (GND) are shared by two adjacent structures here due to the area efficiency consideration. The gate capacitance are extracted fr om the measured S-parameters. An AC open structure is also measured to remove the impact of the capacitance associated with the pad frame and metal connections. An HP8510C network analyzer and an AC probe station are employed in these measurements. The measured gate capacitances of the composite and conve ntional 1.2-V MOS transistors are plotted in Figure3-13. It is shown that the gate capac itance of composite transistors has approximately linear dependence on the length of th e SDR sub-transistor. The y-axis intercept of Figure 3-12.Layout of the AC test structures for the co mposite MOS transistor and the open structure. GNDGND D2G2 G1D1 GNDGND D4G4 G3D3 Composite Transistors 3.3-V Transistor open (no device)

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67 the extrapolation line represents the total capaci tance associated with the TN sub-transistor and gate overlap in the SDR sub-transistor. And this intercept is as expected higher than the gate capacitance of the conventi onal 1.2-V transistor, as labeled by the triangle in Figure3-13. The composite-22 MOS transistor has gate capacitance of 157 fF. This is compared to that of the conventional 0.34m long 3.3-V MOS transistors in the inset of Figure3-13. At the same width, the composite-22 transistor has about 34% higher gate capacitance than the 3.3-V transistor (117 fF). The width of the composite-22 tran sistor should be only 74% of that of the 3.3-V transistor to have the same gate capacitance. For instance, a 7.4m wide composite-22 transistor should have the same gate capacitance of 26 fF as a 10m wide minimum-length 3.3-V transistor. Figure 3-13.Measured gate ca pacitance of the composite transistors with different lengths of SDR sub-transi stors, compared to those of the conventional 1.2-V and 3.3-V transistors. 1.2-V transistor 1.2-V composite y-intercept 0.00.10.20.3 0 40 80 120 160 Length of SDR Sub-transistor (m)Gate Capacitance (fF) composite-22: 157fF f (GHz)Capacitance (fF)137 5 150 100 2003.3-V: 117fF

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68 3.6 Composite-22 MOS Transistors for Level Shifter Application A set of composite MOS transistors with va rying length SDR sub-transistors has been investigated in the preceding sect ions. Composite structures consis ting of two sub-transistors in series have higher current drive capability compar ed to the 3.3-V transistor because the effective threshold voltages are lowered. At the same time these composite transistors can handle higher voltage swing at the drain nodes because the SDR sub-transistors sustain a large portion of the drain-to-source voltage and pr ovide the voltage protection for the TN sub-transistors. When the SDR sub-transistor is shorter, the voltage drop acro ss it becomes smaller and the drain current of the composite structure becomes higher. On the other hand, the voltage protection from the SDR sub-transistor tends to be diminish ed and drain voltage tole rance of the composite structure is lower. As discussed, the composite-22 MOS transistor cons isting of a 0.12m long TN sub-transistor and a 0.22m long SDR sub-transistor is consider ed to be well suited for use in 1.2-to-3.3-V level shifter circuits. The thin-oxide layer in the composite-22 structure limits the maximum gate-to-source voltage to only 1.2 V, and this still fulfills the voltage swing requirement in the case of 1.2-to-3.3-V level shifter circuits. At the drain side of composite-22 transistor, the breakdown voltage is comparable to that of a conventional 3.3-V transistor. The composite-22 MOS transistors are ready to replace the c onventional 3.3-V MOS transistors (M15/M17 in Figure3-1 ) to improve the speed performance. The composite-22 MOS transistor has the sa me drawn length as the conventional 3.3-V transistor. Its threshold voltage is only 0.46 V, wh ich is 0.26 V lower than that of the 3.3-V transistor (0.72 V). When M15 and M17 in Figure3-1 are replaced by the composite-22 MOS transistors, the gate overdrive (VGS-VT = 1.2-VT) is increased by about 54%.

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69 Considering the difference in unit gate cap acitance for the composite-22, the conventional 3.3-V and 1.2-V MOS transistors, ID-VDS curves in Figure3-14 are compared at different widths. The transistor widths are 7.4, 10.0 and 13.1 m, respectively, so that the gate capacitance, or the capacitive loads to the preceding inverter stage, are all 26 fF. Bi ased at the same gate-to-source voltage (VGS), the composite-22 MOS transistor can de liver more than 2 times the current of 3.3-V transistor. In Figure3-15 ID-VGS curves of the composite-22 an d conventional 3.3-V transistors are also compared. Once again, all drain currents we re normalized by keeping the gate capacitance at 26 fF. In the log scale plots, the normal s ubthreshold behaviors are observed at both VDS=3.3 V and VDS=0.05 V. At VDS=3.3 V, the off-state curren t for composite-22 is comp arable to that of the Figure 3-14.ID-VDS characteristics of the compos ite-22, conventional 3.3-V and 1.2-V MOS transistors when gate capacitances (Cgg) are the same. comp-22, W=7.4 m, iii Cgg=26fF 1.2-V, wwii W=13.1 m, Cgg=26fF 0.01.02.03.0VDS (V) 0.0 2.0 4.0 6.0 8.0 ID (mA) 3.3-V, wwii W=10.0 m, Cgg=26fF VGS=1.2V VGS=0.9V VGS=0.3V VGS=0.6V VGS=1.2V VGS=0.6V VGS=0.9V VGS=1.2V VGS=0.3V VGS=0.9V VGS=0.6V

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70 1.2-V transistor at VDS=1.2 V (~1nA/ m). However, it is almost 4 decades higher than that for the 3.3-V transistor. Because the numb er of I/O transistors used in an integrated circuit is limited, the higher leakage should be tolerable. The linear scale plots show once again that ID of the composite-22 transistor is at least 2 times that of the 3.3-V transistor. The improvement of IDS at low VGS is even more dramatic due to the lower thre shold voltage of composit e transistor. With its drain connected to 3.3 V and gate swept from 0 V to 1.2 V, it is clearly shown by the shaded area in Figure3-15 that the composite-22 transistor can deli ver larger current than the conventional 3.3-V transistor. This higher drain current at given gate capacita nce suggests that the 3.3-V drive transistors in the 1.2-to-3.3-V le vel shifter circuit (M15/M17 in Figure3-1 ) can be replaced by the composite-22 transistors to reduce the propagation delay. Figure 3-15.Comparison of ID-VGS curves for the composite-22 and conventional 3.3-V MOS transistors in linear a nd logarithm scales at fixed gate capacitance, with VDS = 3.3/0.05 V. comp-22, VDS=0.05V comp-22, VDS=3.3V 10-1410-1210-1010-810-610-410-2ID (A) 3.3-V, wwii VDS=0.05V 3.3-V, wwii VDS=3.3V 0.01.02.03.0VGS (V) 0.0 2.0 4.0 6.0ID (mA)

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71 3.7 Low-to-high Level Shifter Speed Performance In the previous section, th e composite-22 and the minimu m length conventional 3.3-V MOS transistors are studied. Ba sed on the DC and AC propertie s from measurements, the proposed composite-22 transistor has higher drive current than the 3 .3-V transistor. Cadence Spectre simulator is used in this section to estimate the improvement in the speed performance for the 1.2-to-3.3-V level shifters when the 3.3-V drive transist ors are replaced by th e composite-22 transistors. First, modeling of SDR-26 MOS transistors is necessary. Ba sed on the conventional 3.3-V transistors model, we built a model file to appr oximately describe the behavior of composite-22 transistor by modifying several parameters, such as gate oxide thickness (tox), threshold voltage (vth0), mobility (u0) and saturation velocity (vsat). The simulation re sults match the 2.68 times the drain current, and 1.34 times the gate cap acitance of the conventi onal 3.3-V transistors at fixed channel width. These modificat ions reflect the improvement of current drive capability discussed in Section 3.4.1 and the increase of gate capacitance measured in Section 3.5 respectively. The same 1.2-to-3.3-V level shifter structure shown in Figure3-1 is used for simulations. Figure3-16 shows the two simulated versions. Version A is the level shifter circuit using the conventional 3.3-V nMOS transistor s as the drive transistors (M8A/M9A). Two conventional 3.3-V pMOS transistors (M10A/M11A) are used as the cross-coupled load. The 3-stage conventional 1.2-V inverter chain (A1 through A3 ) preceding the level shifter ge nerates the input signal, whose shape is independent of the number of propa gation stages. The 3-stage conventional 3.3-V inverter chain (A5 through A7) is al so used following the level shif ter to maintain the same capacitive loading of each stage Tau98 In version B, all components ar e the same as version A, except that the two drive transistors (M8B/M9B) are replaced by the compos ite-22 MOS transistors in

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72 order to tolerate the 3.3-V swing and deliver hi gher drain current to the following stage. The width of composite-22 transistors in version B are only 74% of thei r counterparts in version A, so that the stages A3 and B3 can see the same capacitive loads. Figure3-17 shows the input and output waveforms of both level shifters for the pull-down and pull-up cases. In either Figure3-17 (a) or Figure3-17 (b), the input signals in those two verFigure 3-16.Schematics of level shifter ci rcuits in simulation. Version A uses conventional 3.3-V MOS transistors as drive transistors; Version B uses composite-22 MOS transistor s as drive transistors. A1 3.3V Composite-22 conventional 3.3-V in 3.3-V inverter 1.2-V inverter 1.2-V circuitry 3.3-V circuitry A2 A3 A5 A6 A7 A4 B1 3.3V B2 B3 B5 B6 B7 B4 level shifter B version A outputA outputBversion B M8AM9AM8BM9BoutputA outputB level shifter A M11AM10AM11BM10B

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73 sions are the same and overlaid on each other. This is because, in both versions, the drive transistors (M8A and M8B, M9A and M9B) give the same capacitive load to the preceding stages. The same input signals with 1.2-V swi ng are delayed differently and sh ifted to output signals with Figure 3-17.Comparison of th e composite-22 and conventio nal 3.3-V MOS transistors used in 3.3-to-1.8-V level shifters. (A) propagation delays in pull-down case ( n), (B) propagation delays in pull-up case ( p). A B input outputB outputA input outputB outputA n Bn A p Bp A outputB outputA outputB outputA

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74 3.3-V swing. The time differences of output signals for both pulldown and pull-up cases directly show the improved speed performance of the le vel shifter implemented by using the composite-22 transistors over the c onventional 3.3-V transistors. The data extracted from the waveforms are listed in Table3-4 including the pull-down propagation delay ( n), pull-up propagation delay ( p), fall time ( f), and rise time ( r). A propagation delay improvement of around 40% can be expected from th is 1.2-to-3.3-V leve l shifter circuit by using the composite-22 MOS transistors instead of conventional 3.3-V tran sistors. This speed improvement is obtained wi thout any process modifications. In addition, there is no change in the circuit configuration, and it is convenient for circuit designers to use. 3.8 Summary Level shifters are crucial for di gital CMOS I/O interface circui ts to translate different voltage levels back and forth. The le vel shifting requires extra stages and introduces additional propagation delay, which should be limited to minimu m. In a low-to-high level shifter, the drive transistors have to be realized by using thick-oxide high-voltage MOS transistors to stand the high voltage swing at the drain nodes. The gate nodes of drive transistors, however, only need to han-version A (conventional 3.3-V) version B (composite-22) delay improvementpull-down delay (ps) nA = 124 nB = 8234% pull-up delay (ps) pA = 165 pB = 93 44% fall time (ps) fA = 221 fB = 119 46% rise time (ps) rA = 194 rB = 103 47% Table 3-4.Speed performance comparison of level shifters using the composite-22 and conventional 3.3-V MOS transistors

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75 dle low voltage swing. These requirements provide opportunities for use of the SDR thick-oxide MOS transistors. The composite MOS transistor structure using the SDR thickoxide MOS transistor is proposed. With its asymmetric voltage characteristics from gate to dr ain, the composite transistor is well suited as the drive transistors in the low-to -high level shifter circui ts, since it can deliver higher drain current than the conventional thick-oxide high-voltage MOS transistors. The composite transistors usi ng two different foundry CMOS processes are discussed in this chapter. First, the composite18 structure was implemented in a 0.18m CMOS foundry technology. The potential reliability issues at th e internal shared diffusion region is discovered, and the criteria to monitor this problem is discussed. In the second implementation using a 0.13m CMOS technology, the measurements show that a 0.22m long SDR thick-oxide MOS transistor in series with a conventional thin-oxi de transistor (composite22) is the optimal combination for use in the 1.2-to-3.3-V level shifter circ uits. This composite-22 transistor can deliver more than 2 times the drain current as the convent ional thick-oxide transistors, while still having sufficient breakdown voltages and protecting the TN sub-transistors for 3.3V swing at the drain node. This current enhancement translates to about 40% reduction in the propagation delay. The use of composite MOS transistors in the low-to-high level shifters to improve the speed performance is feasible in the 0.18m and 0.13m CMOS technologies. This concept should be applicable in other more advanced technologies. In a more general term, this study on low-to-high level shifters successfully demonstrat es another application of the SDR thick-oxide MOS structure, namely in digital I/O circuits. Fu rther scaling of the thic k-oxide MOS transistors should be feasible to optimize the performance of digital I/O circuits.

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76 CHAPTER 4 RADIO FREQUENCY POWER AMPLIFIER APPLICATION 4.1 Introduction 4.1.1 CMOS RF Power Amplifiers A typical CMOS RF transceiver is shown in Figure4-1 Along the transmitting path, the power amplifier (PA) is the fina l active stage for delivering a suff icient amount of power through the T/R switch and antenna to the propagation media. Because the RF signal level becomes the largest level at this point, the design considerati ons and methods for PA ar e different from those for other RF blocks for small signals. In the design of CMOS power amplifier circ uit, the output power level and power efficiency are two of the most impor tant specifications. To deliver high power level signal, typically the power amplifier itself becomes the most powerconsuming block in the RF transceiver. Poor power efficiency will cause self-heating problem and large power consum ption will shorten the battery life for portable wirele ss communication devices. These pe rformance will eventually be limited by the power transistor ch aracteristics, such as breakdown voltage, current limitations and maximum power dissipation [ Smi98 ]. IF and Baseband Circuits Transmitter Receiver SynthesizerT/R Switch PA Antenna LO LOFigure 4-1.Simplified block diagra m of a typical RF transceiver.

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77 In CMOS power amplifier desi gn, two types of power efficiency are widely used: drain efficiency (DE) and power added efficiency (PAE). Their definitions are as below: ,(4-1) .(4-2) Psupply is the power consumption from the DC supply, Pin is the input power, Pout is the power delivered the output load and Go is the power gain of the PA. If the power gain of the amplifier (Go) is high enough (which is not alwa ys true for PAs final stage) DE and PAE are close to each other. 4.1.2 Classification of CMOS RF Power Amplifiers Power amplifiers are classified according to th eir mode of operation, i.e. the bias condition for power transistors and the nature of output ne twork. Traditionally, ther e are several categories of power amplifiers: class A, AB, B, C, D, E, F, etc. Class-A power amplifiers are biased such that its conduction angle is 360 The amplifier operates linearly over the full input and output ranges. The output is the sinusoidal waveform of the same frequency as the input, and the output am plitude is a linear func tion of the input amplitude. Among all PAs categories, cl ass-A power amplifier has the hi ghest linearity and the poorest efficiency. This type of amplif iers always consumes DC power even though there is no output signal. If the power amplifier is biased so that the conduction angle is between 180 and 360 it is referred to as class-AB. If the amplifier output is a linear f unction of the input over half (180 of the input waveform, then it is categorized as cl ass-B. This mode of operation can have a greater efficiency than class-A due to the reduced conductio n angle. If the linear conduction angle is less DE P out P supply -------------------= PAE P out P in P supply ------------------------P out P supply -------------------1 P in P out ----------- DE1 1 G o ------- ===

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78 than 180 it is a class-C power amplifier. From cl ass-A to class-C power amplifiers, there is increasing distortion in the output waveform, or the linearity of the amplifiers becomes worse. A main source of power amplifier inefficiency is the dissipation in the power transistors. Like a class-A amplifier, the current follows continuously through the MOS transistor while the VDS is non-zero. If VDS can be made to zero while the curren t flows, there will be no power dissipation in a transistor and the drain efficiency (DE) will approach 100%. This is the basic idea behind class-D, E, and F power amplifiers. For power amplifiers under th ese categories, the power tran sistors usually operate in a switching mode, and cooperate with the output network to reduce or eliminate the non-zero overlap between current and voltage waveforms at the drain node. The input signal waveform is not preserved, just the frequency is. Therefore, thes e categories are also referred to as non-linear power amplifiers. 4.1.3 Thick-Gate-Oxide MOS Transist ors in Linear Power Amplifiers Some wireless communication systems, like EDGE, WCDMA transceivers, have very strict linearity requirements, therefore the linear power amplifiers are necessary. Class-A or AB power amplifiers are often useful in these appl ications. However, as ment ioned, the efficiency is a serious concern. When the saturation voltage (VDSsat) is considered, the maximum drain efficiency for a class-A power amplifier is [ Smi98 ]: .(4-3) For the case using the 3.3-V th ick-oxide MOS transistor, Vsupply is 3 V and VDSsat is about 0.2 V, therefore (DE)max is up to 44%. On the other hand, for the case of the 1.2-V th in-oxide MOS transistor, VDSsat doesnt change much and it ta kes more percentage of the Vsupply (1 V). The effiDE max1 2 -1 VDSsatVsupply----------------- 2=

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79 ciency drops to 32%. For such power amplifier applications, high voltage MOS transistors are preferable. The composite MOS transistor (proposed in Chapter 3 ) has the high voltage handling capability like a conventional 3.3-V MOS transistor while its current drive capability is better than the 3.3-V transistor when VGS is limited up to 1.2 V. In this chapter, we will examine the high frequency capability of the composite-22 MOS transistor amplifiers. The better frequency response could lead to higher power gain (Go), therefore, increasing th e PAE of a power amplifier in Equation 4-2 4.2 AC Characteristics of Composite-22 MOS Transistor 4.2.1 fT and fmaxfT (cut-off frequency) and fmax (maximum frequency of oscilla tion) are often used as the figures of merits for high frequency performance of a transistor. The small-signal model of a MOS transistor is shown in Figure4-2 Aside from the well-known lumped elements, two extra elements are included. The charging resistance (ri) accounts for the distributed effect along the channel, and its value is about 1/(5gm). The gate resistance here is split into an intrinsic part (Rg,i) and an extrinsic part (Rg,e). + Rg,eRg,iCgdrdgdsCdbCgsrivgsgmvgs intrinsic transistor Figure 4-2.Small-signal lumped micr owave network model of a MOSFET.

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80 fT is defined as the frequency wher e the extrapolated current gain (h21) decreases to unity, as expressed below: ,(4-4) where, ii is the input current and io is the short circuit output current. For this model, the cut-off frequency can be written as [ Man99 ] .(4-5) Here, it is assumed that << Cg, and Cg = Cgs+Cgd. fT has simple definition and is easy to measure. However, fT does not provide the frequency re sponse information for the transistor power gain. fmax is the frequency where the maximum available gain (MAG) of a transistor is equal to unity. It also represents the highest frequency that a transistor coul d possibly oscillat e in a circuit. The maximum available gain (MAG ) is the power gain obtained by a device when the input and output ports are conjugately matc hed to the impedance of the s ource and load simultaneously. This figure of merit provides a fundamental limit on how much pow er gain one can achieve from a device at a given frequency. Under th e simultaneous conjugate match condition, the maximum available gain can be written as [ Gon97 ]: .(4-6) where K stands for Kurokawas stabil ity factor and can be calculated by h 21 ff T = i o i i ---ff T = 1 == f T g m 2 C g 2 g m r i C gs C gd 2 -------------------------------------------------------------------g m 2 C g ------------= gmriCgsCgd Sin MS== Lout ML== MAG S21S12---------KK 2 1 =

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81 .(4-7) When K is less than 1, MAG is not defined. This is the typical case that a transistor operates at lower frequency range and is poten tially unstable. When operating frequency is sufficiently high, K becomes greater than 1 and MAG can be calculated from the S-parameters. Another power gain called the unilateral power gain (Gmax) was also proposed in [ Mas54 ] to estimate the fmax. According to this definition, additional feedback network is introduced to the transistor of interest so that there is no reverse transmission of signals from the output to the input of this combined network (the tr ansistor of interest, and the a dditional feedback network). For a two-port network, the un ilateral power gain (Gmax) is described by the y-parameters [ Gup92 ]: .(4-8) Furthermore, by applying the transistor pa rameters accounted by the model shown in Figure4-2 the unilateral power gain (Gmax) can be expressed as .(4-9) It is reasonable to assume th at for RF applications, and the unilateral power gain (Gmax) can be further simplified as .(4-10) K 1S212 S122 S11S22S 21S122 + 2S21S12-----------------------------------------------------------------------------------------= G max 1 4 -y 21 y 12 2 Rey 11 Rey 22 Rey 21 Rey 12 ---------------------------------------------------------------------------------------------------= G max f T f 2 4R gi g ds g m C gd C g + 4r i g ds + ---------------------------------------------------------------------------------------R gi r i + g ds R gi g m C gd C g G max f T 8 R gi C gd f 2 --------------------------------------

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82 Ideally, Gmax has the dependence of 20dB /dec on frequency, and fmax can be simply expressed as Equation 4-11 .(4-11) Interestingly, the fr equency at which Gmax attains the unity is al so the frequency at which the MAG of the device becomes unity. Therefore, both power gains discusse d above will be used to estimate fmax. 4.2.2 Measurements for fT and fmaxThe AC test structures of composite-22 and conventional 3.3-V thick-gate-oxide MOS transistors discussed in Section 3.5 are used for fT and fmax measurements. As discussed, an AC open structure is also measured to remove th e capacitance associated with the pad frame and metal connections. An HP8510C network analyzer and an AC probe station are employed. The measurement frequency is up to 26GHz, wh ich is limited by the network analyzer. In Figure4-3 MAG and Gmax extracted from the S-parameters are plotted in a logarithm scale. For the composite22 MOS transistor, the gate and dr ain are biased at 0.8 and 3.0 V, respectively. For the conventional 3.3-V MOS transi stor, the gate and drain are biased at 2.0 and 3.0 V, respectively. For MAG curves, each one ha s a turning point. For frequencies below this turning point, the K factor in Equation 4-7 is less than 1, thus the calculated MAG is invalid. When the frequency is higher than this turning point, K becomes greater than 1, therefore the extracted MAG is valid. Interestingly, the va lid portions of MAG curves merge with the Gmax curves, and lead to the same fmax values. f max f t 8 R gi C gd ---------------------------= h21 2

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83 The extracted fT and fmax for multiple samples are shown as function of gate bias condition in Figure4-4 If VGS is below 1.2 V, the composit e-22 transistor has higher fT than the 3.3-V MOS transistor. fT of the composite-22 tran sistor reaches the peak value of 15 GHz at VGS=0.8 V. However, this advantage is overturned when VGS of the 3.3-V transistor is increased above 1.2 V. fT of the 3.3-V transistor reaches the peak value of 19 GHz at VGS=2.0 V. fmax of the composite-22 transistor reaches p eak value of 29 GHz at VGS=0.8 V. While fmax of the 3.3-V transistor reaches 37.5 GHz at VGS=2.0 V. In general, the composite-22 MOS transistor has lower fT and fmax than the conventional 3.3-V transistor. However, this is not true if we consider the prac tical bias conditions at the transistor gate for an amplif ier. When the overdrive (VGS-VT) is set to around 0.25 V, for instance, the Figure 4-3.Measured current gain (h21), maximum available gain (MAG) and unilateral power gain (Gmax) for the composite-22 and conventional 3.3-V thick-gate-oxide transistors. MAG Gmax (K>1) (K>1) (K<1)turning pointh21 2 composite-22 3.3-V0.41.040 10 0 10 15 20 25 Frequency (GHz) 5 -5, MAG, Gmax (dB)h21 2

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84 composite-22 transistor has ~ 20% higher fT and comparable fmax compared to the conventional 3.3-V transistor. With better frequency response, the composite-22 MOS tr ansistor may slightly increase the gain of amplifiers (Go) and PAE as calculated in Equation 4-2 However, the improvement by using composite-22 transistor is expected to be marginal, or even none for some bias conditions. There is another considerati on of using composite-22 transi stors in conventional analog amplifier circuits. The intrinsic gain (gm ro) is one of the key parameters to characterize amplifier transistor, and it specifies the hi ghest voltage gain that can be possibly provided by a transistor. Compared in Figure4-5 are gm, output resistances (ro) and intrinsic gain of the composite-22, conventional 3.3-V and 1.2-V transistors. The overdrives (VGS-VT) for all transistors are Figure 4-4.fT and fmax for the composite-22 MOS tran sistor and conventional 3.3-V thick-gate-oxide transistors. Thres hold voltages for both transistors are labeled by VT comp and VT 3.3V. Gate overdrives of 0.25 V are also labeled. fTfmax fTfmaxVDS=3.0V composite-22 3.3-V VDS = 3.0V composite-22 3.3-V fTfmaxfmaxfT 0.25V 0.25V VT 3.3VVT comp 0.01.02.03.0 VGS (V)fT and fmax (GHz)10 0 20 30 40

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85 Figure 4-5.gm, output resistance (ro) and intrinsic gain of the composite-22 and conventional 3.3-V/1.2-V transist ors when the overdrives (VGS-VT) are around 0.25 V. Output Resistance (k) 0.01.02.03.0 0.0 1.0 2.0 3.0 Composite-22 1.2-V 3.3-V gm (ms) 0.01.02.03.0 0 10 20 30 gmro 0.01.02.03.0 0 10 20 30 40 VDS (V) Composite-22 1.2-V 3.3-V Composite-22 1.2-V 3.3-V

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86 kept around 0.25 V. The transistor widths are scaled so that the drain currents for all transistors are about the same. The composite22 transistor has similar gm, but about 1/2 output resistance of the conventional 3.3-V transistor. This low output resist ance degrades the intrinsic gain, as well as fmax, of the composite transistor. The intrinsic gain of composite transi stor is about 1/2 that of the 3.3-V transistor. In addition, the 1.2V transistor has only about 1/2 output resistance compared to the composite transistor. However, the higher gm of 1.2-V transistor compen sates so that its intrinsic gain is comparable to that of the composite transist or. Finally, the composite transistor doesnt show superior characteri stics in conventional anal og amplifier applications. 4.3 Summary In this chapter, use of the composite-22 MOS tr ansistor in RF power amplifier circuits is examined. At first, the RF power amplifier circuit of a transceiver and its large signal characters are introduced. Output power level and efficiency are the two of the most important specifications for power amplifiers. Power amplifiers in differ ent classes need compromises between the linearity and power efficiency. PA desi gn in certain applications prefer high-voltage (thick-oxide) MOS transistors due to the high breakdown voltages. The composite-22 MOS transistor can handle th e same drain voltage swing like the conventional 3.3-V MOS transistor. fT and fmax are measured for the devices speed characteristics. In general, the composite-22 MOS tr ansistor is not superior to the conventional 3.3-V transistor. When considering the practical gate bias conditions, the measurements show that the composite-22 MOS transistor has slightly higher fT and comparable fmax compared to the conventional 3.3-V transistor. Additionally, the composite transistor shows lowe r intrinsic gain than the 3.3-V transistor. The composite transi stors demonstrate only marginal, or even no advantages over the 3.3-V transistors for RF and analog amplifier circuits.

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87 CHAPTER 5 TRANSMIT/RECEIVE SWITCH APPLICATION 5.1 Introduction A high performance transmit/recei ve (T/R) switch is a key bui lding block of the radio frequency (RF) front end of time-div ision duplexing (TDD) communicati on systems. In this chapter, the potential use of thick-gate-o xide SDR MOS transistors in RF switch circuits in order to improve the performance is discussed. 5.1.1 CMOS Transmit/Receive Switches A simplified block diagram of a TDD RF transceiver is shown in Figure5-1 Both transmitter and receiver are conn ect to an antenna (ANT) th rough a single-pole-double-through (SPDT) T/R switch. Either a tran smitter or a receiver is on one at a time. In receive mode, a T/R switch connects the antenna to the receiver path, which usually starts with a low noise amplifier (LNA) or a filter. The signal collected by the an tenna which is very weak goes through the switch and is fed into the LNA. The loss of T/R switc h increases the noise figure of LNA by the same Antenna Figure 5-1.T/R switch in a typical TDD RF transceiver. Receiver Transmitter T/R switch LNA PA

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88 amount. Therefore, the T/R switch should have lo w loss (<1 dB) to reduce its impact on receiver sensitivity. In transmit mode, the T/R switch co nnects the antenna to the transmit path or power amplifier (PA). The T/R switch should handle high power signal without ex cessive distortion and loss. Obviously, high power handl ing capability and low loss are desirable for the T/R switch. Also, the T/R switch must have sufficiently high isolation to block the transmit signal from being fed into the input of receiver. Key figures of merit for a T/R sw itch include insertion loss (I L), isolation, return loss, and power handling capability. The insertion loss meas ures the power loss through the switch when the switch is on. At off-state, the switch loss is characterized by isolation. By measuring two-port S-parameters of a switch, in sertion loss and isolation can be expressed as Equation 5-1 or 5-2 in dB. or(5-1) .(5-2) Return loss measures how much power is reflected back from a ny ports of the switch. This parameter describes how severe the mismatch at the port is and can be expressed using Equation 5-3 or 5-4 in dB. or(5-3) .(5-4) Power handling capability of a switch is usua lly represented by its 1dB compression point (P1dB), or the input referred one (IP1dB). P1dB is defined as the output power where the power ILisolation 1 S21 2-----------= IL dBisolation dB20S21 log = return a loss 1 S11 2------------= return a loss dB20S11 log =

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89 gain of switch drops fr om the small signal power gain by 1 dB. Higher P1dB denotes a higher power handling capability. This parameter is f undamentally determined by the non-linearities of the switch. Another parameter commonly used to characterize the linearit y of a switch is the third-order intercept point (IP3 or input referred one IIP3). This parameter is defined as the power level at which the linearly extrapolated output power of desired signal and that of the third order intermodulation component inte rsect. The input referred IP3 is denoted as IIP3. Using CMOS technology, potentially all RF fr ont end and baseband circuits can be integrated into a single chip. This has been the mo tivation of tremendous effort for finding ways to implement high performance RF building blocks in bulk CMOS technologies. However, the commercial RF switch modules are implemented almo st exclusively in GaAs technology. This has impeded the fully exploiting the low cost potential of CMOS solutions. Mobility of electrons in silicon is only ~ 1/6 of that in GaAs [ Sze02 ]. Compared to GaAs devices, CMOS transistors have hi gher channel sheet resistance ( ch), which is directly related to the switchs insertion loss. The insertion lo ss increases with higher channel resistance (Rch). And the channel resistance is equa l to However, the channel wi dth (W) can not be arbitrarily increased because a larger source/drain area incr eases the capacitance. This increases the switch loss because of the associated substrate resistance. Combatting the substrate loss is another desi gn requirement in RF CMOS switch design. To lower the insertion loss in CMOS technology channel length (L) needs to be scaled down. Since the parasitic capacitance is also reduced with scaling, the in sertion loss improves [ HuaF01b ]. However, technology scaling inevitably reduces the transist or breakdown voltage which is already relatively low. This makes it even more difficult to achieve high power handling performance. chL W -----

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90 In such a junction isolated silicon technol ogy, one more challenge in designing high power switches is the possibility of forward biasi ng the source/drain-to-bo dy junction diodes during large voltage swings at the i nput and output of the switch [ Lar98 ]. These forward biased junctions will distort the output signal, thus li mit the power handling capability (IP1dB). This may also inject minority carriers into the body of the ne arby transistors and tri gger latch-up. Even after applying DC bias at source/drain to increase the reverse bias of the thos e junctions, the power performance of CMOS switches is still limited to around 20 dBm. The 30-dBm RF signal, for instance, corresponds to a ~ 20-V peak-to-peak voltage swing at the input and output ports of a T/R switch with termination of 50load. If directly applied to MOS transistor nodes, such high voltage swing c ould easily forward bias the junctions of MOS transistors, and even damage the transistors. In CMOS processes, it is extremely difficult to deliver power in excess of 30 dBm through a T/R switch. 5.1.2 Techniques to Improve Power Handling Capability With the continuous speed improvement of technologies from generation to generation, bulk CMOS radio-frequenc y (RF) transceivers and power ampl ifiers have proven to be production worthy. To date, an RF CMOS block which has not found wide spread use is a transmit/ receive (T/R) switch [ HuaF01a HuaF04 ]. Key reasons for this are th at bulk CMOS switches have limited power handling capability as measured by input referred 1-dB compression point (IP1dB) and relatively high insertion loss (IL). The power handling capability can be improved while slightly degrading IL by conn ecting the body nodes of NMOS tran sistors through high resistance [ Li03 Ohn04 ]. By making the high impedance connecti on to the body using a parallel LC tank, IP1dB of 28.5 dBm and IL of 1.5 dB ha ve been achieved at 2.4 GHz [ Tal04 ]. It has been suggested that similar performance should be achievable by using NMOS transi stors in isolated p-wells of

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91 triple well CMOS processes whil e eliminating the need for the LC tank which consumes a significant area and makes the switch narrow band. However, to date, the highest IP1dB reported for switches using isolated p-wells is only 20 dBm with IL of 1.1 dB at 5.8 GHz [ Yeh05 ]. The work presented in this chapter dem onstrates the techniques for increasing IP1dB of T/ R switches well beyond 20 dBm usi ng NMOS transistors in isolated p-wells, while reducing the insertion loss degradation. The techniques are used to demons trate a 900 MHz single-pole-double-throw (SPDT) switch with IP1dB of 31.3 dBm, and ILs of 0.5 a nd 1.0 dB in transmit (TX) and receive (RX) modes. Isolation is better than 29 dB up to 1 GHz. The techniques are also utilized to demonstrate a 2.4 GHz SPDT switch with IP1dB of 28 dBm, and ILs of 0.8 and 1.2 dB in TX and RX modes. Isolation is better than 24 dB up to 2.4 GHz. The sw itches are fabricated using the transistors of UMC 130-nm mixed mode CMOS pro cess with a thicker gate -oxide layer in order to reliably support the required voltage swing. 5.2 CMOS T/R Switches Using Sub-Design-Rule Transistors 5.2.1 Design of SDR T/R Switches The switch circuit schematic is shown in Figure5-2 It is formed with a series transistor M4 (Width = 925 m) on the TX leg and 3-stack series transistors M6-M8 (Width = 1115 m) on the RX leg, and 3-stack shunt transistors M1-M3 (Width = 370 m) on the TX node, and a shunt transistor M5 (Width = 370 m) on the RX node. The gate and body nodes of all transistors are biased through 10-k non-silicide polysilic on resistors (Rs in Figure5-2 ). TX and RX nodes as well as the sources of M1 and M5 are biased at 3V to improve the power handling capability [ HuaF01a ]. The switches were turned on and off by va rying the control voltage (G_TX, G_RX in Figure5-2 ) from 2 to 6 V [ HuaF01a ]. The switch can be controlled using a circuit similar to that in [ Poi03 ] and the control voltages can be generated using a voltage doubler [ Poi03 ].

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92 The stacked shunt transistors M1-M3 and seri es transistors M6-M8 are used to sustain higher voltage swings and therefore to im prove the power handling of T/R switch [ McG91, Ohn04 Sch90 ]. Stacking, however, significantly increases the IL of RX leg. Based on the discussions in Chapter 2 it is possible to reduce th e channel length of thick-ga te-oxide transistors below that permitted by the design rule to lower the on-resistance thus reducing the IL degradation. To exploit this, all the transistors were implemented using 3.3-V transistors with a sub-design-rule (SDR ) channel length [ Xu05 ]. The drawn length of SDR tr ansistors in this switch design is 0.26 m instead of 0.34 m required for 3.3-V transistors. DC measurements indicate its on-resistance is reduced by ~ 25%. Since the ga tes of 3.3-V and 1.2-V tr ansistors are simultaneously formed, the SDR channel length transistor s can be formed without any process modifications. This switch does not utilize im pedance transformation to increase IP1dB [ HuaF04 ] and the peak-to-peak voltage the switch must handle is ~20 V at 30-dBm input power. Figure 5-2.Simplified schematic of the T/ R switch with 3-st ack sub-design-rule (SDR) length transistors. RX G_TX G_TX G_RX G_RX ANT TX M3 M2 M1 M4 M8 M7 M6 M5 C1 C2 C4 C3 C5 C6 R R R R R R R R R R R R R R R R

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93 Each NMOS transistor of the switch is located in an isolated p-well ( Figure5-3 ) to allow the body node to float and follow th e RF signal thus increasing IP1dB [ Li03 Ohn04 Tal04,Yeh05 ]. This is similar to the phenomenon that happens in switches fabricat ed in GaAs as well as silicon on sapphire (SOS) and silicon on insulator (SOI) processes [ Miy95 Joh97 YamK99 Tin03 ]. To ensure the isolated p-wells are not AC grounded through the series combination of p-well-to-deep-n-well and deep-n-well-to-p-substrat e junction capacitances (~ 1 pF), the substrate resistance is increased by using the p-we ll implantation block (width of ~20 m), using a small number of substrate contacts (4 per transistor), and adding a 1-k resistor in series with the substrate contacts as shown in Figure5-3 Even after applying these measures, the body nodes of MOSFETs are not perfectly isolated. Figure5-4 shows a more detailed schematic for the stacked transistors M1-M3. The shunt paths from body to AC ground consisting of Cwells due to the series combination of p-well-to-deep-n-well and deep-n-well-to-p-substr ate junction capacitances, and substrate resistances (Rsub1 Rsub3) make the voltage swing unevenly distributed among these 3-stack MOSFigure 5-3.Cross-section of the 3-stac k transistors in the SDR T/R switch. deep-n-well deep-n-well deep-n-well DNW p-well p-well p-well

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94 FETs. These shunt paths reduce the voltage swi ng across the drains and gates of M2 and M1, while increasing the swing across th e drain and gate of M3. This is clearly seen as the grey curves in Figure5-5 (a) which shows the simulated drain-to-g ate voltages of M1-M3. The input power level is 30 dBm. In general, the top transi stors M3 and M8 sustain higher gate-to-body and drain-to-gate voltages than the bottom transistors M1 and M6. Building on the feed-forward techniqu e proposed for GaAs T/R switches [ Miy95 ], the switch in this work incorporates feed-forwa rd metal capacitors (C3=C4=50 fF and C5=C6=150 fF) between the drain and body node s, and between the drain and gate nodes of M3 and M8. The extra capacitances (1X case) reduce the impedance ac ross the gates and drai ns of M3 and M8, and Figure 5-4.Detailed schema tic of the 3-stack transi stors (M1-M3) including the parasitic shunt paths. VTXC1 VD2 VDG1+VSG1+ -VS1 VDG2+VD1VDG3+CwellRsub1Rsub3Rsub2CwellCwell parasitic shunt paths M2M1M3 G_RX VSG2+ -VSG3+ 10k 10k 10k

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95 Figure 5-5.Voltage distributions for the 3stack SDR switches w ith and without the feed-forward capacitors, when the input power is 30 dBm. (A) Drain-togate voltages (VDG1~VDG3) for transistors M1-M3. (B) Voltage waveforms at different nodes along the TX shunt path (M1-M3). -1.5 0.5 2.5 4.5 Voltage (V)Time with cap (1X) without cap VDG3VDG1VDG2Vsg_M20T T/2 -7.0 -2.0 3.0 8.0 13.0 Voltage (V)Time with cap (1X) without cap VTXVD2VD1VS10T T/2 VDS3VDS1VDS2A B

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96 help the gate nodes follow the high swing nodes mo re closely. This make s the voltage swing at TX and ANT nodes more evenly distributed among the 3 stacked MOSFETs. Also shown in Figure5-5 (a) is the simulated drain-to-g ate voltages of M1-M3 with 1X feed-forward capacitors (C3-C6). With the help of feed-forward capacitance, the voltage drop across M3 is reduced by about 1 V, while those across M2 and M1 sustain larger portions of the total input voltage. Figure5-5 (b) shows the simulated voltages of drain nodes for M1-M3 once again at input power of 30 dBm. The maximum voltage including the 3-V DC bias is 13 V. Despite this, the peak voltage drops across gate oxide ( Figure5-5 (a)) and between drains and sources ( Figure5-5 (b)) are ~ 3.5 V to ensure reliable ope ration when feed-forward capacitors are used. This modification of voltage distributi on among M1-M3 enables the stack as a whole to withstand a larger voltage swing before any one is turned on or damaged. The feed-forward metal capacitors (C3-C6) are formed usi ng metal layers 1 through 3 and inco rporated as part of the transistor layout. Simulated drain-to-gate and source-to-gate peak voltages for M1-M3 (VDG1 p ~ VDG3 p, VSG1 p ~ VSG3 p) versus different feed-forwa rd capacitance are plotted in Figure5-6 The values of feed-forward capacitors (C3-C6 ) are varied among 0, 1X (C3=C5=50 fF and C4=C6=150 fF), 2X and 3X. It shows again that, when the feed-forwar d capacitors (1X) are added, the drain-to-gate peak voltages of transistors M1-M 3 are closer to each other, therefore, the voltage swings are more evenly distributed. The peak voltage of M3 is reduced from over 4.6 V to 3.8 V, which is tolerable for the 3.3-V thicker gate oxide transi stor. The drain-to-gate peak voltage of M3 (VDG3 p in Figure5-6 ) and the resulting stress ca n be further reduced by in creasing the feed-forward capacitances.

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97 Larger feed-forward capacitance, however, in creases the portion of total voltage swing applied across the gate oxide layer of M1, and ev entually, M1 becomes the most stressed transistor among the three stacked transist ors. There is an optim al value for the feed-forward capacitor to evenly distribute the voltage ac ross the 3-stack transistors. Figure5-6 suggests that the voltage distribution is better ba lanced when the capacitance is doubled (2 X case). If the capacitance is tripled (3X case), the pe ak voltage across M1 (VSG1 p) becomes larger than that of M3 (VDG3 p). Compared to the switch without feed-forward cap acitance, the simulations suggest about 1.5 and 2.3 dB increases in IP1dB at 900 MHz for the 1X and 2X cases. A potential side effect of increasing C3-C6 is the degradation of insertion loss resulting from the increases of losses due to input mismat ch and through the transistor stack. Simulations show that IL at 900 MHz increases by 0.03 and 0.08 dB for the 1X and 2X cases. An optimal feed-forward capacitor values should be betwee n 1X and 2X. In this work, 900-MHz switches Figure 5-6.Impact of feed-forward cap acitance (0X, 1X, 2X and 3X) on the peak voltages across transistors M1-M3 (VDG1 p~VDG3 p, VSG1 p~VSG3 p). Peak Voltage (V)Feed-forward Capacitance 0X1X2X3X 1.0 2.0 3.0 4.0 5.0 C3=C4=50 fF C5=C6=150 fF VDG3 pVSG3 pVDG2 pVSG2 pVDG1 pVSG1 p

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98 with no feed-forward capacitors and that with C3=C4=50 fF and C5=C6=150 fF (1X case) are fabricated and compared in Section 5.2.2. The impedances of polysilicon resistors in Figure5-2 are almost constant with frequency up to several GHz, while the impedances of para sitic capacitors are fre quency dependent. At sufficiently low frequencies, the floating-body resi stances are not high enough compared to the impedances of capacitive voltage divider structures. Therefore, the voltage division among M1-M3 and among M6-M8, as well as power handling capability is expected to be weakly dependent on frequency. For the 900 MHz switch, the simulated power handling capability is almost flat from ~ 650 MHz to ~ 2.4 GHz. In this range, IP1dB varies by +/1 dB demonstrating the broadband characteristics. Lastly, two 20-pF bypass capacitors (C1 and C2) connect th e sources of M1 and M5 to AC ground, while blocking DC current flow. The inte r-metal shuffled metal capacitor structure [ Sow01 ] consisting of metal layers 1 to 8 is us ed here for high chip area efficiency. 5.2.2 900-MHz SDR T/R Switch A T/R switch operating at 900 MHz using such 3-stack SDR transistors (as shown in Figure5-2 ) was implemented in the UMC 130-nm mixe d mode triple-well CMOS technology. A die photograph of the circuit is shown in Figure5-7 The active area is about 300 m by 380 m or ~ 0.11 mm2. Including the additional area of voltage do ubler circuitry with a 200-pF capacitor (< 0.05 mm2), the SDR switch is still almost 3.5 times sm aller than the area of the switch using an LC-tank connection to the body node [ Tal04 ]. Three GS/SG probes with 150m pitch were used at the RF signal ports for all measurements. A 6-pin DC probe was used to provide bias and control signals. One of the three ports was terminated with a 50load through an AC coupling cap acitor in the measurement setup.

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99 Two-port S-parameters are measured using an HP8510C network analyzer. Figure5-8 shows the measured IL of the SDR CMOS T/R sw itch. At 900MHz, ILs for TX and RX legs are 0.5 and 1.0 dB, respectively. A T/ R switch using only 2-stack 0.34m length MOSFETs instead of 3-stack 0.26m length SDR transistors is also meas ured for comparison. The length of 0.34 m is the minimum allowed by the design rules for 3.3-V transistors. Its IL of RX leg is ~0.2 dB higher than that for the switch using 3-stack SDR channel length transistors. Isolation and return loss of SDR CMOS T/R switch as shown in Figure5-9 are better than 29 dB and 20 dB at 900 MHz, respectively. Linearity measurements were carried out using an HP-E4421B signal generator together with an external power amplifier and an HP 8563E spectrum analyzer. Figure5-10 shows the measurement results of SDR CM OS T/R switch at 900MHz. IP1dB at TX mode is about 31.3 dBm, Figure 5-7.Die photo of the 3-stack SDR T/R switch.

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100 which is the highest ever repor ted for bulk CMOS T/R switches. As mentioned, TX and RX nodes as well as the sources of M1 and M5 are biased at 3V, and the switches were turned on and off by varying the control voltage from 2 to 6 V. Compared to IP1dB for the switch using 2-stack Figure 5-8.Measured insertion loss of the SDR switch us ing 3 stack SDR transistors, compared to that of th e switch using 2 stack 0.34m length transistors. 0.51.01.52.02.53.0 0.0 0.5 1.0 1.5 2.0 2.5 Insertion Loss (dB)Frequency (GHz) TX RX 3-stack of SDR transistors (0.26 m) 2-stack of 0.34-m 3.3-V transistorsFigure 5-9.Measured isolation and return loss for the SDR T/R switch using 3 stack SDR channel length transistors. 0.51.01.52.02.53.0 10 20 30 40 10 20 30 40 TX RX TX RXIsolation (dB)Return Loss (dB)Frequency (GHz) 3-stack of SDR transistors

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101 0.34m length MOSFETs, this value is about 5 dB higher. These clearly illustrate the benefits of using SDR transistors. IIP3 of the SDR CMOS switch is 42 dBm. When the source and drain nodes are biased at 0 V, IP1dB drops to 26 dBm due to forward bi ased junctions. The linearity of the SDR CMOS T/R switches with and without th e additional feed-forward capacitors are also compared in Figure5-10 The additional capacitors improve IP1dB for the SDR switch by about 1.3 dB. Finally, to examine the reliability characteristics, the SDR CMOS T/R switch is stressed around IP1dB (31.3 dBm) for 10 hours. The stress was ca rried out for both conditions when ANT pad is connected to a 50load and when it is left open to examine the effects of antenna mismatch. The measured S-parameters showed no di fference before and after the stresses. This experiment verifies that the 3-stack switch ci rcuit using SDR MOS transi stors can successfully handle more than 31-dBm RF si gnal without reliability problems. Figure 5-10.Linearity measurement results of the 3-stack SDR switch with source/ drain biased at 3 and 0 V, and with (1X) and without the feed-forward capacitors. 010203040 Pin (dBm) -80-80 -60-60 -40-40 -20-20 00 2020 4040Pout (dBm) Vbias=3V w/o cap Vbias=0V 3rd order IIP3 = 42 dBm IP1dB = 31.3 dBm IP1dB = 26 dBm IP1dB = 30 dBm

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102 5.2.3 2.4-GHz SDR T/R Switch In the 900-MHz T/R switch, 3stack transistor structure wa s chosen and the power handling capability was significantly improved. On the other hand, the necessary stacking limited the insertion loss performance at the switchs RX leg. Th e 900-MHz switch dem onstrated reasonable insertion loss (< 1 dB) only up to ~ 1 GH z. There is design trade-off between IP1dB and IL, or alternatively between IP1dB and operating frequency because IL increases with frequency. If power handling requirement of a T/R switch can be relaxed to some extent, fewer number of stacked transistors can be used so that IL performance can be improved. Furthermore, such a T/R switch can potentially operate at higher frequencies while keeping the same acceptable IL performance. To further investigate such design trade-off, a 2.4-GHz T/R switch for wireless LAN (WLAN) applications using SDR tr ansistors has been implemented and presented in this section. Figure 5-11.Simplified schema tic of the T/R switch for 2.4-GHz applications using 2-stack SDR transistors without feed-forward capacitors. RX G_TX G_TX G_RX G_RX ANT TX M2 M1 M4M7 M6 M5 C1 C2 R R R R R R R R R R R R

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103 By using these tech niques discussed in Section 5.2.1 an SDR T/R switch operating at 2.4 GHz was designed and implemented in the same CMOS foundry process. Figure5-11 shows the simplified schematic of this 2.4-GHz T/R switch. In this case, 2-stack SDR transistors (M1-M2 and M6-M7) are chosen to compensate the incr eased insertion loss along the RX leg at 2.4 GHz, however, with its power handlin g capability compromised. The di e photo of such T/R switch circuit is shown in Figure5-12 and its active area is about 300 m by 300 m or ~ 0.09 mm2. Once again, the two-port S-para meters are measured using an HP8510C network analyzer and shown in Figure5-13 It clearly indicates that the IL at RX leg is shifted down by stacking only two SDR transistors and this switch yields acceptable perf ormance even at higher frequencies. The measured insertion loss at 2.4 GHz is about 0.8 and 1.2 dB for TX and RX legs, respectively. Its isolation performance at 2.4 GHz is better than 24 dB. Large-signal performance is also Figure 5-12.Die photo of the T/R switch for 2.4-GH z applications us ing 2-stack SDR transistors without f eed-forward capacitors.ANT TX RX S/DNW Sub G_RX Body G_TX C1 C2 M1 M2 M4 M7 M6 M5

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104 characterized as plotted in Figure5-14 Measured at 2.4 GHz, its IP1dB is greater than 28 dBm, which is ~ 3dB lower than that of the 3-stack switch circuit. Figure 5-13.Measured insertion loss and is olation of the 2-stack SDR switch for 2.4-GHz applications. 0.51.01.52.02.53.0 0.0 1.0 2.0 3.0 4.0 10 20 30 40 RXInsertion Loss (dB)Isolation (dB)Frequency (GHz) TX RX TX 2-stack SDR Figure 5-14.IP1dB measurement of th e 2-stack SDR switch working at 2.4 GHz. 0102030 -10 0 10 20 30 Pout (dBm)Pin (dBm)@ 2.4 GHz 2-stack SDR 28 dBm

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105 In this design, power handling capability is sacr ificed for better loss performance, or for higher operating frequency. Using SD R MOS transistors, a T/R switch with better combination of power and loss performances is ac hieved for 2.4-GHz wire less application. The insertion losses of 0.8 and 1.2 dB for TX and RX legs at 2.4 GHz are the lowest reported to date for a bulk CMOS switch with IP1dB greater than 25 dBm. It is also no ted that this 2.4-GHz SDR T/R switch does not use feed-forward capacitanc e for transistors M2 and M7. Ba sed on the experience of the 3-stack T/R switches in Section 5.2.1 IP1dB of this 2-stack switch is e xpected to increase further by about 1 dB when properly sized feed-forward capacitors are used. The performance of this 2.4-GHz and other T/R switch es discussed are summarized and compared in Table5-1 T/R switches3-stack SDR w/ cap 3-stack SDR w/o cap 2-stack 0.34m 2-stack SDR w/o cap work [ Ohn04 ] work [ Tal04 ] work [ Yeh05 ]Frequency (GHz) 0.90.90.92.45.02.45.8 IL (dB) TX0.50.50.50.81.01.51.1 RX1.01.01.21.21.41.61.1 Return Loss (dB) >20>19>19>13>17>12Isolation (dB) >29>29>31>24>22>1727 IP1dB (dBm) 31.33026.52822.728.520 IIP3 (dBm) 42-----chip area (mm2) 0.110.110.090.09<0.10.560.03 Table 5-1.Performance summar y of CMOS T/R switches.

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106 5.3 Discussion The output power of these SDR T/R switches is normal functions of the available input power, as long as the input power is kept below IP1dB. When the nominal input power level is sufficiently high, however, the output power of switches abruptly drops and then saturates with the available power from source. This effect sets the limit on the sw itch power handling capability. This behavior is reversible in that when the input power is lowered ag ain, the output power recovers. The measurement results fo r the 900-MHz SDR T/R switch ( Figure5-10 ) are magnified in detail and shown in Figure5-15 This output power level drop has weak depe ndence on the bias conditions of drains/ sources, p-wells and deep n-wells. As shown in Figure5-16 the measured leakage current through the vertical drain/source-p -well-n-well-p-sub path is only on the order of 1 mA, which is much smaller compared to that flowing through th e switch transistors (peak current of ~ 200 mA). Figure 5-15.Detail of linearity measuremen t results around 1-dB compression point for the 3-stack SDR switch. Output power drops abruptly if the nominal input power is above certain point. 252627282930313233 24 25 26 27 28 29 30 31 32 Pin (dBm)Pout (dBm) IP1dB

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107 Furthermore, cutting off all the shunt transist ors (M1-M3 and M5) from the circuit using a focused ion beam had almost no effect on the power drop. The only change that significantly affected the power level at which the drop occurre d is leaving the RX node floating instead of terminating with a 50load after cutting off all the shunt tr ansistors. Under this condition, the measured power drop occurs at ~5-dB higher input pow er level. The low current through the vertical drain/source-p-well-n-well-p-s ub path and the strong dependence on RX node termination suggest that the power drop is not caused by latch-up phenomenon. Instead, we believe that the cause is the br eakdown of 3-transistor stacks (M1-M3 and M6-M8). The breakdown characteristics of a singl e SDR transistor is measured and shown in Figure5-17 It is noted that the brea kdown voltage decreases with VGS. When the voltage swings at TX and ANT nodes are small, the capacitively coupled voltage swings at the gates, thus VGS, are also small. Therefor e, each SDR transistors can tolera te higher voltage swing without conFigure 5-16.Measured DC cu rrent through the n-p-n-p sa ndwich structur e from source/ drain, through body to p-substrate. 12 10 8 6 4 2 0 Voltage (V) 10.0 8.0 6.0 4.0 2.0 0.0Current (mA)

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108 ducting measurable current When the input voltage swing is sufficiently increased, the coupled voltage swing at gate weakly turns on the devices and simultan eously lowers the breakdown voltage. This clamps the output voltage and power at a reduced level. An associated abrupt impedance change also causes power mismatch at the switch input and contributes to the sudden output power drop. This can be proved by observation that a sudden power change at the switchs input port occurs at the same time when the output power abruptly drops. Interestingly, when the available power from source is then reduced, the me asured output power foll ows a different path (labeled by stars in Figure5-15 ). This is because the breakdown vo ltage is still lo w and mismatch is sever until the RF signal pow er, thus the gate-to-source volta ge swing, is low enough. Then the breakdown voltage increases and the output power follows the input linearly again. A positive consequence of this power drop a nd clamping is that when the switch is severely mismatched, the resulting high voltage wi ll be clamped, thus protecting the switch from permanent damages. Figure 5-17.Measured breakdown characteri stics of a single SDR transistor. 0.02.04.06.08.0 0 20 40 ID (mA)VDS (V)VGS=0.7 0.6 0.5 0.4 0.3 0.20.1 breakdown region

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109 5.4 Summary A T/R switch is usually the first building block in a TDD (Time Division Duplex) radio system. Its performance is cruc ial to both the transmitter and receiver operations. The key parameters to characterize a CMOS T/R switch have been introduced. The current techniques to improve the performance and the i nherent process limits of switch es implemented in CMOS technologies have been discussed. In this chapter, the focus of our investigatio n is the use of the SDR NMOS transistors in radio frequency T/R switch circ uits. Design techniques for improving the power handing capability of bulk CMOS T/R switches to above 30 dBm while maintaining acceptable insertion loss have been demonstrated using the UMC 130-nm mixed-mode triple-well CMOS technology. Stacked sub-design-rule (SDR) channel length NMOS transistors with a th icker gate oxide layer are used to improve the power handling capability while keeping IL low. Use of a thicker gate oxide layer of 3.3-V transistors in SDR transi stors enables ~3.5-V drop across the transistors without reliability concerns. Isol ated p-wells and p-well blocks are used to improve the floating-body effect. At 900 MHz, a switch incorporating 3-stack SD R transistors located in isolated p-wells exhibits IP1dB of 30 dBm. By using fe ed-forward capacitors, IP1dB is increased to 31.3 dBm. The power handling capability is limited by a new m echanism. A decrease of drain-to-source breakdown voltages of the TX shunt and RX series stacked transistors due to un-intentional turning-on of the transistors by RF input is suggested as the likely cause for a sudden output power drop. The switch achieves 0.5-dB and 1.0-dB in sertion losses in the transmit an d receive modes. This switch has 0.2 dB lower insertion loss in receive mode and 5 dB higher IP1dB in transmit mode compared to that for a switch using 2-stack design rule compliant 3.3-V transistors. At 2.4 GHz, a switch

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110 utilizing 2-stack SDR tr ansistors exhibits IP1dB of 28 dBm. The insertion losses for transmit and receive modes are 0.8 and 1.2 dB, which should be acceptable for 802.11b and g applications. Lastly, this work suggests that in tegration of a bulk CMOS T/R switch for cellu lar applications is a realizable goal by using thickgate-oxide SDR MOS transistors.

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111 CHAPTER 6 HIGH-Q MOS VARACTOR APPLICATION 6.1 Introduction In preceding chapters, use of the sub-design-rule (SDR) MOS st ructures in transistors for different circuit applications a nd their benefits have been dem onstrated. Actually, an SDR MOS structure is naturally a high qual ity varactor. This is because th ick-gate-oxide layer has smaller gate capacitance, and furthermore, using sub-de sign-rule channel lengths for MOS varactors can reduce the series resistance. In th is chapter, the performance of SDR MOS varactor structures are presented and compared to those of c onventional thin-gateoxide MOS varactors. 6.1.1 CMOS Voltage-Controlled Oscillator Local oscillators (LO) genera te periodic output signals for both transmitter and receiver (LO signals in Figure4-1 ). Furthermore, LO frequency shoul d be adjustable but precisely controlled for different channels according to th e wireless communication sy stem design. Such function is usually realized using a voltage-contro lled oscillator (VCO) in a phase-locked loop. For many reasons, a differential implementati on of the oscillator is usually chosen [ Por00 ]. A typical VCO in a CMOS technology is shown in Figure6-1 These two cross coupled MOSFETs (M1-M2) provide the nega tive resistance, and the L-C ta nk makes the circuit resonate at the desired frequency. In order to control the oscilla tion frequency, varactors (Cvar) are included as part of the L-C tuning tank. In general, higher quality fact or (Q) for the L-C tank is pr eferred in VCO design, because (1) the output noise shaping function is sharper, (2 ) power dissipation of circuit is lower, and (3) noise injected from MOSFETs is reduced [ Raz01 ]. Noise performance and power consumption requirements are very strict in a wireless communication system. Therefore, much efforts have

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112 been expended to improve the voltage-controlled oscillator (VCO) design, and more specifically to realize a high-Q and low parasitic LC-tank. Q of inductors increases with operating frequency (QL ~ L/Rs, where L is inductance, Rs is series resistance) so that this is less of c oncern when operating freque ncy is increased. Unfortunately, Q of capacitors/v aractors is inversely pr oportional to frequency (QC ~ CRs, where C is capacitance, Rs is series resistance). Studies have s hown that, at frequencies lower than 10 GHz, the Q of L-C tanks is us ually limited by the on-chip inductors However, above 20 GHz and in the millimeter-wave range, Q of cap acitors/varactors becomes more problematic for the overall L-C tank [ Cao06a Cao06b ]. 6.1.2 MOS Varactors Conventionally, on-chip varactors have b een implemented with p-n junctions under reverse bias or MOS capacitors in accumulation/ depletion regions. The latter structure has demFigure 6-1.Schematic of a typical differen tial CMOS voltage-controlled oscillator. VDDM2 VbiasM1 L L VvarCvarCvarM3 Vout+Vout-

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113 onstrated higher Q factor and wi der tuning capability over the fo rmer one when the voltage supply is scaled down [ Sve99 Por00 ]. Therefore, MOS varactors ar e often used in VCO circuits. The cross-section of a typica l MOS varactor is shown in Figure6-2 The top and bottom plates are formed by silicided polysilicon and n-well, and are se parated by the same high quality gate oxide layer as that of MOSFETs. Since the gate oxide layer is very thin, the MOS varactor has a high intrinsic capacitance-area ratio, especially when it is biased in the accumulation mode [ Hun98 ]. This varactor structure is ve ry similar to an n-channel MOSFET with the exception of being fabricated in an n-well instead of the norma l p-substrate. This choice was made to eliminate the parasitic pn-junction capacitances at source and drain that would ot herwise limit the tuning range. An alternative structure using a p-channel MOSFET in a pwell/substrate has a lower quality factor due to lower carrier mobility. The operation principle of varactors is to ch ange the capacitance of a MOS structure by varying the gate voltage, which changes the operation region among accum ulation, depletion, and inversion [ Soo98 Mol02 ]. By applying positive voltage betwee n the gate and n-well, the Si surFigure 6-2.Cross-section of MOS varactor structures. Poly Metal2 p-substrate n-well Metal1n+ STI n+ STI

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114 face is accumulated and the varactor capacitance equals the gate oxi de capacitance. If the applied voltage is reversed, the Si surface layer is depleted and the series capacitance decreases. The maximum capacitance per unit area of the varactor co rresponds to a heavily accumulated surface and equals the unit area gate oxide capacitance (Cox= oox/tox). On the other side, the minimum value (Cd) is reached when the voltage between the gate and n-well is negative and beyond the threshold voltage. In this case, an inve rsion layer is formed under the ga te. At low frequencies (~ kHz), this effect brings the value of capacitance close to the gate oxide one. However, at high frequencies where the varactor is suppose d to operate in VCOs, this effect is not seen and the capacitance remains at its minimum value. The difference between Cox and Cd indicates the capacitance tuning capability for varactors. Ideally, total varactor capacitance can be varied between the maximum and the minimum as in Equations 6-1 and 6-2 ,(6-1) .(6-2) Here, W and L are the finger width and lengt h, and N is the total number of fingers. The series resistance Rs of the varactor usually is domin ated by n-well and gate resistances, and can be cal culated as following [ Hun98 ]: ,(6-3) CmaxCoxAtotCoxWLN = = CminCdAtotCdWLN = = Rs1 3 -1 2 -1 2 -1 N --RnwL W ----RpolyW L ----+ = 1 12WLN ------------------------------=RnwL2 RpolyW2 +

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115 where, R nw and R poly are the sheet resistances of n-well and polysilicon gate, respectively. The factor 1/3 accounts for the spr eading effect, while two 1/2 fact ors account for the double-sided contacts for both poly gate and n-well. The minimum varactor quality factor (Qmin) is obtained when the capacitance is the largest. From Equations 6-1 and 6-3 Qmin is expressed as .(6-4) Obviously, Qmin is a monotonic function of L (or W) and it is prefer able to use minimum dimensions for both L and W to increase Q. Another important parameter for a varact or is its capacitan ce tuning range ( ). Without losing the generality, can be defined as %,(6-5) where is independent of dimension parameters L (or W). Higher suggests better capacitance tuning capability, and in turn, wider VCO frequency tuning range. Until now, parasitic capacitances associated with gate overlap and interconnect layers have not yet been taken into account. However, thos e parasitics can be comp arable to the varactor capacitance itself. Theref ore, a parasitic term Cpar(W, L, N) should be added to Equations 6-1 and 6-2 In a typical varactor layout, L is much smalle r than W. The gate overlap capacitance and the fringe capacitance between the gate and metal connections dominate in Cpar and they both are proportional to The overlap area capacitance be tween metal2 and poly gate is relatively smaller. Even thought Cpar should be a complicate function of W, L and N in general, it is still a Qmin1 RsCmax--------------------12 CoxRnwL2 RpolyW 2+ ---------------------------------------------------------------------------== CmaxCmim CmaxCmim+ 2 ----------------------------------------CmaxCmim Cmax-----------------------------CoxCd Cox------------------100 == WN

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116 good approximation to assume Now, Equations 6-1 and 6-2 should be modified as below, ,(6-6) .(6-7) Here, is a constant representing the tota l parasitic capacitance per unit width. Accordingly, Equations 6-4 and 6-5 should also be modified: ,(6-8) %.(6-9) From Equation 6-8 it is noted that Qmin is no longer a monotonic function of L. With a given W, Qmin reaches the peak value when L satisfies the Equation 6-10 .(6-10) Also, the capacitan ce tuning range ( has dependence on L as suggested in Equation 6-9 When L decreases, more contribut ion of total capacitance will come fr om parasitics, which is independent of varactor gate voltage. In turn, this a dditional parasitic capacitance will degrade 6.1.3 Sub-Design-Rule MOS Varactors As suggested by the Equation 6-4 or 6-8 the thick-gate-oxide MOS structure inherently has higher quality factor due to thicker gate-oxide layer (tox) and lower gate capacitance (Cox). The capacitance area density is sm aller compared to the thin-gateoxide MOS structure. However, this is not a serious issue for circuits operating above ~ 1 GHz. CparWLN WN CmaxCoxAtotCparWLN CoxWLN WN + = + = CminCdAtotCparWLN CdWLN WN + = + = Qmin12 RnwL2 RpolyW 2+ Cox L --+ ------------------------------------------------------------------------------------------= CmaxCmim Cmax-----------------------------CoxCd Cox L --+ --------------------100 = 2 RnwRpoly---------------Cox -------L3 RnwRpoly---------------L2 +W2=

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117 The Q factor can be further improved if th e SDR thick-gate-oxide MOS structures are employed to reduce the channel length. In additi on, there are no reliability issues for SDR MOS structures in varactor applications because the source and drain are always tied together to form the bottom plate connection. However, decr easing channel length L will degrade the varactor tuning range ( ). Therefore, the trade-off of Q f actor and the varactor tuning range ( ) is an important issue in high-Q varactor design. In the next section, th e difference and possible advantages of thick-gate-oxide SDR MOS varactors ove r its conventional thin-g ate-oxide counterpart are discussed. 6.2 High Frequency Characteri stics of SDR MOS Varactors 6.2.1 Device Structure One-port AC test structures of thick-gate -oxide (TK) SDR and conventional MOS varactors are fabricated in the same 0.13m CMOS technology as mentioned in Section 3.4 Figure6-3 shows a layout and an equivalent circuit model of those varact ors. The drawn finger Figure 6-3.Layout and equivalent ci rcuit model of a MOS varactor. Cvar CparRgateRnwellRmetalLmetal L W diffusion metal poly contact varactor

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118 channel lengths include 0.12, 0.18, 0.24 and 0.3 m (SDR varactors), and 0.36 m (conventional TK varactor). All the draw n finger width (W) is 0.9 m. Besides those, one more conventional TK varactor of 5.0 m by 1.0 m is also fabricated to illustrat e the better tuning range case. To investigate the difference of SDR varactors over thin-gate-oxide (T N) varactors, another group of TN varactor structures wi th the same dimensions listed above are also built. As discussed before, a pad frame structure with no device is fabricat ed as AC open in order to de-embed the capacitan ce of the pad frame and metal connections. Again, a structure with device replaced by a wide metal line is also fabricated as AC short to de-embed the extra series resistance and inductan ce introduce by metal connection (Rmetal and Lmetal in Figure6-3 ). A network analyzer (HP8510C) is empl oyed for S-parameter measurements. 6.2.2 Measurements and Discussions All thick-gate-oxide and thin-gate-oxide varact or test structures are characterized. As an example, Figure6-4 only shows the extracted capacitance a nd quality factor at 24 GHz versus gate voltage for TK-24 and TN-24 va ractors with channel length at 0.24 m. The TN-24 varactor demonstrates wider tuning range than the TK-24, wh ile the quality factor can be as low as ~ 20. The TK-24 varactor, using SDR channel length, ca n increase the quality factor to above 100. Qmin measured at 24 GH z and tuning range for different test structures are plotted together in Figure6-5 With a decreasing channel length, for both TK and TN varactors decreases relatively smoothly. Al so, as expected, TK structures have smaller tuning range than TN ones. values shift down from ~ 65% for TN to ~ 40% for TK structur es. On the other hand, measured Qmin increases rapidly in both TK and TN cases, when varactor channels become shorter. It is noted that us ing SDR channel can improve Qmin of TK varactors even more dramatically. At a length of 0.36 m, the TK varactor has Qmin of 48, which is 3 times that of the TN var-

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119 Figure 6-4.C-V and Q-V characteristics of the thick-gate-oxide (TK) and thin-gate-oxide (TN) varactors with L = 0.24 m. 0 402060Capacitance (fF) -2-1012 0 80 160 40 120 200Quality Factor Q (TK-24)Q (TN-24) C (TK-24) C (TN-24)Gate Voltage (V) Figure 6-5.Measurement data of Qmin and vs channel length for thick-gate-oxide (TK) and thin-gate-oxide (TN) varactors. 0 4080120QminChannel Length (m) 00.20.40.6 0.81.0 0 40 80 20 60 100Tuning Range (%) (TK) (TN) Qmin (TK) Qmin (TN)

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120 actor. When the length is shorten to 0.24 m in SDR region, TK varactors Qmin can jump to above 100. It is improved by almost 5 times comp ared to the corresponding TN varactor. It is noted that, at extreme high Qmin situation, the series resistance (Rs) is only several ohms and much smaller than the reactance of capacitor. This makes it difficult to extract reliable Qmin for those SDR varactors with the channel length below 0.24 m Those four lines drawn in Figure6-5 are calculated Qmin and from Equations 6-8 and 6-9 is extracted from the measur ement results by data fitting. Th e 1st-order approximation fits most measurement results we ll. Interestingly, the data points at length of 1.0 m significantly deviate from the calculated plot s. The reasons include that, for these structures, the gate connections are single-sided, the channel width of 5 m rather than 0.9 m is used and the metal connections have no overpass above the poly gate. There ar e more series resistance and less percentage of parasitic capacitance compared to predictions from the Equations 6-8 and 6-9 therefore, data show lower Qmin and higher tuning range. Equation 6-8 also suggests that, at very small L, term may be comparable or exceed and Qmin may drop when L is further reduced. For this 0.13m CMOS process, the critical channel le ngths calculated by Equation 6-10 are ~ 0.1 and ~ 0.08 m for TK and TN varactors, respectively. Th ese lengths are below the lithogr aphy limit, therefore, shrinking channel length can always improve Qmin of MOS varactors. Qmin and tuning range are two major parameters for varactor design To clearly show the trade-off between them, curves of Qmin versus tuning range once again, are plotted in Figure6-6 TN varactors have superior tuning range to the thicker ones. However, their Qmin are well below 40. By usi ng SDR varactors, Qmin can be dramatically imp roved. The design space is RpolyW 2 RnwL2

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121 extended to region of higher-Qmin-lowercombination. Fortunately, the degradation of is relatively small in this space. So, tuning range can be traded off for high-Q performance in SDR varactors. For example, such varactors can be used in a dual-conversi on receiver [ Li03 ] operating around 50 GHz [ Che06 Luo05 ]. The incoming signal is down-converted twice by using two VCOs. The first VCO operates at higher but fixed frequency, so the want ed channel will not be centered around the first intermediate frequency (IF1). However, the second VCO has a wide tuning range and will guarantee that the wanted channel is centered around fixe d frequency (IF2 or DC) by the second down-conversion. SDR varactors, which have limite d tuning range but superb quality factor fit well to the first VCO applicat ion. The significantly improved Qmin of this type of varactors can improve the total L-C tank Q and result in bett er phase noise performance and lower power consumption. Even though the margin for the parasitic capacitance due to the core transistors should Figure 6-6.Varactor design space formed by Qmin and tuning range 20 60 80Qmin 0 20 4060 80100 Tuning Range (%) 100 40 120 0 TK TN 1/ higher lower Qmin

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122 be reserved, it is believed that th e varactor capacitan ce tuning range ( ) of ~ 40% is sufficient for the first VCO to compensate the proce ss, temperature and supply variations. 6.3 Summary In this chapter, use of the SDR MOS structures as varactors in VCO circuits is studied to investigate the feasibility of e xploiting higher Q compon ents. A series of SD R varactors are fabricated and characterized. Their performance is compared to that of the conventional thin-gate-oxide MOS varactors. Qmin and tuning range ( ) are very important parameters for varactor design. However, Qmin of thin-gate-oxide MOS varactors is l imited at frequencies above ~ 20 GHz. Qmindesign space for MOS varactors can be greatly expanded by using thickgate-oxide SDR structures. A combination of extreme high Qmin and modest tuning range ( ) is achieved and its possible applications in VCOs is discussed. Using SDR varactors can improve the phase noise and power consumption performances of VCOs oper ating at frequencies above 20 GHz.

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123 CHAPTER 7 SUMMARY AND SUGGESTIO N FOR FUTURE WORK 7.1 Summary Conventional thick-gate-oxide MO S transistors are of ten part of standa rd offering in commercial CMOS technologies. They have many advantages, such as higher breakdown voltage, higher power handling capability and lower dr ain leakage current. Compared to the thin-gate-oxide transistors, low-current low-spee d characteristics limit the usage and the performance of thick-gate-oxide transi stors in many circuits. Because th e lithography limit in these processes is significantly lower, the high voltage perf ormance can be traded of f to improve their high frequency performance. A goal of this research has been to find approaches to improve the performance of thick-gate-oxide MOS transist ors without modifying the exis ting foundry technologies. It has proven the sub-design-rule (SDR) channel length transistors is an easy and effective way to improve the characteristics of tran sistors with thick-gate-oxide in different circuit applications. The dissertation began with the exploration of using SDR transi stors in digital I/O circuits. In Chapter 2 a single SDR transistor was investigated as the starting point. Its application in a 3.3-to-1.8-V level shifter circuit using a 0.18m CMOS foundry technology is studied. A series of thick-oxide SDR MOS transist ors are compared to the conve ntional 3.3-V MOS transistors. The measurements suggest that the 0.26m long SDR MOS transistor (SDR-26) can deliver 1.28 times the drain current as the conventional one, while maintaining suffic ient breakdown voltages to tolerate the signal swing at the gate and dr ain nodes. The conventiona l 3.3-V drive transistors in the 3.3-to-1.8-V level shifter can be repl aced by 25.6% wider SDR-26 transistors to provide 60% more drain current. In simulations, this curr ent enhancement translates into a nearly 20% reduction in the propagation delay.

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124 Following that, the composite MOS transistor, consisting of a SDR thick-oxide MOS transistor and a conventional thin-oxi de transistor, was proposed in Chapter 3 Its low threshold voltage makes it well suited as the drive transistor s in the low-to-high level shifter circuits. In a 0.13m CMOS technology, the measurement results show that a 0.22m long SDR thick-oxide MOS transistor in series with a conventional thin-oxide transist or (composite-22) is the optimal combination for use in the 1.2-to -3.3-V level shifter circuits. Th is composite-22 transistor can deliver more than 2 times the drain current as th e conventional thick-oxide transistors, while still having sufficient breakdown voltages and protecting the TN sub-transistors for 3.3-V swing at the drain node. This current enhancement translates to about 40% reduction in the propagation delay. The study has successfully identified the circ uit benefits of usi ng the SDR MOS transistors or the composite MOS transistors in level shift circuits. This conc ept of further shrinking thick-gate-oxide transistors is also applicable to other more advanced technologies. In general, use of the SDR MOS transistors provides another way to exploit the scaling of CMOS technologies. Building on their digital I/O circuit applications the role of SDR transistors in RF/analog applications is investigated. In Chapter 4 use of the composite MOS transistors in RF power amplifier (PA) circuits was exam ined. For power amplif iers, the output power level and the power efficiency are the two key specifi cations. Compromise between the linearity and power efficiency are necessary for power amplifiers in different classes. High-vo ltage (thick-oxide) MOS transistors are preferred for certain PA designs. The composite-22 MOS transistor can handle th e same drain voltage swing like the conventional 3.3-V MOS transistors. fT and fmax of the devices are measure d. In general, the composite-22 MOS transistor is not supe rior to the conventional 3.3-V tr ansistor. When considering the

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125 practical gate bias conditions (0 < VGS-VT < 0.25 V), the measurements show that the composite-22 MOS transistor has higher fT and comparable fmax than the conventional 3.3-V thick-gate-oxide transistors. At best, the improve ments of RF power amplif ier gain and efficiency are expected to be marginal. The lower intrinsic ga in of the composite transistor limit its applications in analog amplifier circuits. Use of the SDR MOS transistors in radio fre quency T/R switch circuits was the research focus of Chapter 5 In this chapter, design techniques for improving th e power handing capability of bulk CMOS T/R switches to above 30 dBm wh ile maintaining acceptable insertion loss have been demonstrated using the UMC 130-nm mixedmode triple-well CMOS technology. Stacked sub-design-rule (SDR) channel lengt h NMOS transistors with a thickgate-oxide layer are used to improve the power handling capability while keepi ng IL below 1 dB. Use of a thick-gate-oxide layer of 3.3-V transistors in SD R transistors enables ~3.5-V drop across the transistors without reliability concerns. Isolated p-wells and p-we ll blocks are used to improve the floating-body effect. At 900 MHz, a switch incorporating 3-stack SD R transistors located in isolated p-wells exhibits IP1dB of 30 dBm. By using feed-forward capacitors, IP1dB is increased to 31.3 dBm. A decrease of drain-to-source br eakdown voltages for the TX shunt and RX series stacked transistors due to un-intentional turningon of the transistors by RF input is suggested as the likely cause for a sudden output power drop. The switch achieve s 0.5-dB and 1.0-dB insertion losses in the transmit and receive modes. This switch has 0.2 dB lower insertion loss in receive mode and 5 dB higher IP1dB in transmit mode compared to that for a switch using 2-stack design rule compliant 3.3-V transistors. To demonstrate the trade-of f between power handling capability and switch loss, a 2.4-GHz switch utilizing 2-stack SD R transistors is built. It exhibits IP1dB of 28 dBm and

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126 its insertion losses for transmit and receive m odes are 0.8 and 1.2 dB, respectively, compared to 0.5 and 1.0 dB for the switch with 31.3-dBm IP1dB. This 2.4-GHz T/R swit ch should be acceptable for 802.11b and g applications. This work s uggested that integration of a bulk CMOS T/R switch for cellular appli cations no longer appears to be an unrealizable goal. In Chapter 6 use of the SDR MOS structures as varactors is discussed. The SDR MOS varactors have higher quality factor (Q) than thin-gate-oxide varact ors. A series of SDR varactors were fabricated and char acterized. Their performanc e benefits in VCO applic ations were explored in comparison to the conventiona l thin-gate-oxide MOS varactors. The minimum Q (Qmin) and tuning range ( ) are important paramete rs for varactor design. However, Qmin of thin-gate-oxide MOS va ractors is limited at fre quencies above ~ 20 GHz. The Qmindesign space for MOS varactors can be greatly expanded by using thick-gate-oxide SDR structures. A combinatio n of extremely high Qmin and modest tuning range ( ) is achieved and its possible applications in VCOs ar e discussed. This can be used to reduce high frequency (> ~20 GHz) VCO phase noise and power consumption. 7.2 Suggestion for Future Work Based on the study presented in this disse rtation, additional works on SDR MOS structures are suggested. 7.2.1 Application in high power T/R switches This study demonstrated that it is feasible to build CMOS T/R switches with power handling capability above 30 dBm. It is difficult but will be interest ing to improve this performance even higher. One possible way is to stack more SDR transistors in the high voltage paths. The optimal SDR channel length should be experimentally investigated.

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127 More number of stacking tran sistors means more flexibil ity for the voltage division among them. Feedforward capacita nce technique should still impr ove the T/R switch power handling capability. There are additional nodes to add the feedforward capacitors. For example, capacitors can be connected to the drain node of the second top transi stor in the stack (C31, C32 in Figure7-1 ), and the source node of the bo ttom transistor in the stack (C11, C12 in Figure7-1 ), which otherwise usually sustain higher voltage swings. Optimization of capacitance value and location should be further examined. 7.2.2 Application in high-Q varactors The varactor structures used in this work have capacitance around 40 fF. The associated series resistance is only severa l ohms and sometimes difficult to measure. This becomes particularly problematic when the length of SDR varactor decreases below 0.24 m. Varactor structures with a smaller number of fingers should provide sufficient series resistance and facilitate the investigation of SDR var actors with even higher Q. Capacitance tuning range ( ) of SDR MOS varactors is inferi or to that of thin-gate-oxide ones. The reason is the percentage of parasitic capacitance is highe r. It should be helpful if the Figure 7-1.Additional nodes to connect feedforward capacito rs in a 4-transistor stack of SDR T/R switches. RX G_RX ANT M4M2 M1 C C M3 C31C32C11C12

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128 spacing between poly gate and metal connecti ons of diffusions is further increased ( Figure7-2 ). One way is to increase distance be tween the poly gate and diffusion contacts. The increase in chip area and additional series resist ance along the diffusion region and metal connections are the drawbacks. Another way is to use metal3 layer as the overpas s connection. This method does not change the area consumption, and th e series resistance will slightly increase due to the extra via connections. Varactor test structures with differ ent S1 and S2 should be fabricated along with the control structure. The trade-off among tuning range series resistance and chip area should be investigated. Figure 7-2.Spacing between po ly gate and diffusion c onnections in MOS varactor structures. Poly Metal2 p-substrate n-well Metal1n+ STI n+ STI S1 S2

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129 APPENDIX MODEL FILE FOR SDR-26 MOS TRANSISTORS The model used in simulation for the SDR-26 MOS transistors are based on that of the conventional 3.3-V MOS transistor. Those modified parameters are highlighted.... 6: type=n minr=1e-60 lmin=3.5e-07 noimod=1 ef=0.907 af =0.9065 kf=8.704e-29 lmax=5e-07 dxl3 wmin=1.28e-06 + dxw3 wmax=1.008e-05 dxw3 tnom=25 version=3.2 tox= 1.5 6.8e-09 toxm=1.5 6.8e-09 xj=1.7e-07 + nch=5.26e+17 lln=-1 lwn=1 wln=1 wwn=1 lint =4e-08 ll=0 lw=0 lwl=0 wint=3e-08 wl=0 + ww=0 wwl=0 mobmod=1 binunit=2 xl= 2e-08 + dxl3 xw=0 + dxw3 dwg=0 dwb=0 + ldif=9e-08 hdif=hdifn3 rsh=6.8 rd=0 rs=0 vth0= -0.18 + 0.8654908 + dvthn3 lvth0=-1.656396e-08 + wvth0=1.422681e-09 pvth0=-6.085174e-16 k1=0.7481822 lk1=1.029616e-07 wk1=-1.008557e-07 + pk1=2.007025e-14 k2=0.189703 lk2=-9.366 277e-08 wk2=8.466009e-09 pk2=7.544907e-15 + k3=0 dvt0=0 dvt1=0 dvt2=0 dvt0w=0 dvt1w=0 dvt2w=0 nlx=0 w0=0 k3b=0 vsat= 1.7 93128.79 + lvsat=-0.0008515152 wvsat=-0.004630455 pvsat=1. 852182e-09 ua=-6.665338e-10 lua=-9.533202e-17 + wua=-1.002899e-15 pua=3.95669e-22 ub=2 .115918e-18 lub=2.187213e-25 wub=5.45836e-25 + pub=-4.393103e-31 uc=2.631281e-10 luc=-3. 906129e-17 wuc=-1.204542e-16 puc=2.977803e-23 + rdsw=545 prwb=0 prwg=0 wr=1 u0=1.43 0.04367778 lu0=3.770848e-10 wu0=-1.023911e-08 pu0=2.667197e-15 ...

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137 BIOGRAPHICAL SKETCH Haifeng Xu was born in Xian, China, in June 1975. He received the B.S. degree in Physics from Nanjing University Nanjing, China, in 1996, and the M.S. and Ph.D. degrees in electrical and computer e ngineering from the University of Florida Gainesville, FL, USA, in 2002 and 2007, respectively. He joined the Silicon Microwave Integrated Ci rcuits and Systems (SiMICS) Research Group in the Department of Electrical and Computer Engineering at University of Florida in 2000. In 2001, he worked on radio frequency (RF) integrated circuit design as a summer intern at IBM Boston Design Center, Chelmsfor d, MA, USA. His research interests include CMOS RF integrated circuits, RF power ampl ifiers, monolithic microwave IC (MMIC) components and digital I/O circuits.