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Nonclassical Nanoscale CMOS: Performance Projections, Design Optimization, and Physical Modeling

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NONCLASSICAL NANOSCALE CMOS: PERFORMANCE PROJECTIONS,DESIGNOPTIMIZATION,ANDPHYSICALMODELING By SEUNG-HWAN KIM A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006

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-ToMy parents

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iii ACKNOWLEDGMENTS Iwouldliketoexpressmysincereappreciationtothechairman ofmysupervisorycommittee,ProfessorJerryG.Fossum,forhisguidance andsupportthroughoutthecourseofthiswork.Hisgreatknowledgein semiconductorphysicsmotivatedmydevotiontothefieldof semiconductordevices.Hewasarolemodelforme,putthingsinproper perspective,andcontributedtomypositiveattitude.Iwouldalsoliketo thankthemembersofmysupervisorycommittee(ProfessorsRobertFox, JingGuo,andSusanSinnott)fortheirguidanceandinterestinthiswork. IamgratefultoSamsungElectronics,FreescaleSemiconductor, andtheNationalScienceFoundationfortheirfinancialsupportandthe usefulinformation.IwouldalsoliketothankfellowstudentsJi-Woon Yang,VishalTrivedi,WeiminZhang,MurshedChowdhury,ZhichaoLu, SiddharthChouksey,andShishirAgarwalfortheirinsightfuland technicaldiscussionsandfriendships.Also,Ithankallofthefriendswho mademyyearsattheUniversityofFloridasuchanenjoyablechapterof my life. Imustexpressheartfeltthankstomymother(Kyung-LimLee), mysisters(Eun-Kyung,Yeon-Jung,andHee-Jung),andmybrother-inlaw(Dong-JuPark)fortheirconstantencouragement,support,help, sacrifice, and love throughout my studies.

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iv TABLE OF CONTENTS page ACKNOWLEDGEMENT.........................................................................iii LIST OF TABLES....................................................................................vi LIST OF FIGURES.................................................................................vii KEY TO ABBREVIATIONS......................................................................x ABSTRACT............................................................................................xii CHAPTER 1 INTRODUCTION...................................................................................1 2NONCLASSICAL CMOS: POTENTIAL NONCLASSICAL TECHNOLOGIES VERSUS A HYPOTHETICAL BULK-SILICON TECHNOLOGY.......................................................................................8 2.1 Introduction..................................................................................8 2.2 UFDG, UFPDB, and Simulation Conditions...............................10 2.3 Immunity to Short-Channel Effects............................................12 2.4 28nm Device Design....................................................................14 2.5 CMOS Performance Projections..................................................22 2.6 Thin-BOX FD/SOI CMOS............................................................32 2.7 Summary.....................................................................................35 3 BULK INVERSION IN FINFETS AND IMPLIED INSIGHTS ON EFFECTIVE GATE WIDTH.................................................................37 3.1 Introduction................................................................................37 3.2 Numerical Simulations...............................................................38 3.2.1 I-V Characteristics of DG and TG FinFETs......................40 3.2.2 Electric-Field Fringing Effects..........................................43 3.2.3 Bulk Inversion...................................................................43 3.3 Implied Insight of Bulk Inversion...............................................50 3.3.1 Proper Effective Gate Width.............................................50 3.3.2 Layout Area.......................................................................52 3.4 Summary.....................................................................................55

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v 4 MODELING AND SIGNIFICANCE OF FRINGE CAPACITANCE IN NONCLASSICAL CMOS DEVICES WITH GATE-SOURCE/DRAIN UNDERLAP..........................................................................................57 4.1 Introduction................................................................................57 4.2 Physical Insights from Numerical Simulations..........................58 4.2.1 Inner and Outer Fringe Capacitance................................58 4.2.2 BOX Fringe Capacitance in FD/SOI MOSFETs................61 4.3 Analytical Modeling....................................................................64 4.3.1 Weak Inversion.................................................................69 4.3.2 Strong Inversion................................................................72 4.4 Model Verification.......................................................................72 4.5 Model Implementation in UFDG (Ver. 3.5).................................74 4.6 Model Applications......................................................................76 4.7 Summary.....................................................................................84 5DOUBLE-GATEFINFETSWITHGATE-SOURCE/DRAINUNDERLAP: APPLICATIONSONSRAMCELLANDDESIGNOPTIMIZATIONFOR DEVICE SPEED...................................................................................86 5.1 Introduction................................................................................86 5.2 DG FinFETs without Underlap..................................................88 5.3 Threshold Voltage Modulation by Underlap...............................90 5.4 Applications on SRAM Cell.........................................................98 5.4.1 SRAM Cell Design.............................................................98 5.4.2 Sensitivity Issue in SRAM Cell.......................................103 5.4.3 SRAM Cell Scaling..........................................................108 5.5 Device Speed Issue....................................................................111 5.5.1 Using Long Straggle........................................................111 5.5.2 Sensitivity to Straggle.....................................................118 5.6 Summary...................................................................................120 6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK.................124 6.1 Summary...................................................................................124 6.2 Suggestions for Future Work....................................................127 APPENDIX A UPGRADES/REFINEMENTS OF UFDG CHARGE MODEL............131 A.1 Modeling of Junction Depletion Charge...................................131 A.2 Upgrading of Electron Charge Model in Weak Inversion.........133 B DG MOSFET GATE CAPACITANCE IN SATURATION REGION...137 REFERENCE LIST...............................................................................148 BIOGRAPHICAL SKETCH...................................................................154

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vi LIST OF TABLES Table page 5.1UFDG/Spice3-predicted sensitivity to the variation of straggle, fin width, and the channel length. . . . . . . . . . . . . . . .107

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vii LIST OF FIGURES Figure page 2.1UFDG-predicted threshold voltage roll-off and DIBL . . . . . .13 2.2UFDG-predicted current-gate voltage characteristics. . . . . . .16 2.3UFDG-predicted effects of separately varying toxf and toxb. . .18 2.4UFDG/UFPDB-predicted current-gate voltage characteristics . .20 2.5UFDG/ and UFPDB/Spice3-predicted propagation delays. . . . .23 2.6UFDG/ and UFPDB/Spice3-predicted propagation delays. . . . .24 2.7UFDGand UFPDB-predicted gate capacitances. . . . . . . . .27 2.8UFDG/Spice3-predicted loaded CMOS ring-oscillator delays . . .31 2.9UFDG/Spice3-predicted propagation delays. . . . . . . . . . .34 3.1Two-dimensional cross-section view of the DG FinFET. . . . . .39 3.2Davinci-predicted current-voltage characteristics . . . . . . . .41 3.3Davinci-predicted on-state current increase. . . . . . . . . . .42 3.4Davinci-predictedon-stateelectrondensityalongthetopfinsurface,at the center of the channel . . . . . . . . . . . . . . . . . .44 3.5Davinci-predictedon-stateelectrondensitydownthemiddleofthefin, at the center of the channel. . . . . . . . . . . . . . . . .45 3.6Medici-predicted electron density . . . . . . . . . . . . . .49 3.7Davinci-predictedon-stateelectrondensityatthemiddleofthetopfinbody surface, at the center of the channel. . . . . . . . . . . .51 3.8Calculated gate layout-area ratios of TG and DG FinFETs. . . . .54

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viii 4.1Medici-predicted low-frequency gate capacitance. . . . . . . . .59 4.2Medici-predicted low-frequency subthreshold gate capacitance . .62 4.3A schematic diagram of the gate-source/drain structure. . . . . .63 4.4Basic two-plate model for the fringe capacitance. . . . . . . . .65 4.5Schematics of the G-S/D underlap structure for the weak inversion analysis. . . . . . . . . . . . . . . . . . . . . . . . .66 4.6Illustration of how varying the actual lateral doping density profile changes the weak inversion effective channel length. . . . . . .68 4.7Schematic of the SG FD/SOI MOSFET with G-S/D underlap. . . .71 4.8UFDGand Medici-predicted gate capacitance . . . . . . . . .77 4.9UFDGand Medici-predicted current-voltage characteristics . . .79 4.10 UFDG/Spice3-predicted propagation delays . . . . . . . . . .81 4.11UFDGand Medici-predicted gate capacitance . . . . . . . . .82 5.1UFDG-predicted threshold voltage . . . . . . . . . . . . . .92 5.2Threshold voltage reduction. . . . . . . . . . . . . . . . .94 5.3UFDG-predicted on-state current and the increased source/drain series resistance . . . . . . . . . . . . . . . . . . . . .95 5.4UFDG-predicted threshold voltage . . . . . . . . . . . . . .97 5.5UFDG-predictedreadstaticnoisemarginversustheeffectivechannel length and schematics of 6-T SRAM cell. . . . . . . . . . . .99 5.6UFDG-predicted buttery curves . . . . . . . . . . . . . .101 5.7UFDG-predicted write-0 margin . . . . . . . . . . . . . .102 5.8UFDG/Spice3-predicted sensitivity of the optimal DG FinFET . .105 5.9UFDG-predicted read-SNM versus the physical gate length. . . .109 5.10UFDG-predicted buttery curves . . . . . . . . . . . . . .112

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ix 5.11UFDG-predicted write-0 margin . . . . . . . . . . . . . .113 5.12UFDG-predicted current-gate voltage characteristics. . . . . .114 5.13UFDG-predicted gate capacitance. . . . . . . . . . . . . .116 5.14UFDG/Spice3-predicted propagation delays per stage. . . . . .117 5.15UFDG/Spice3-predicted loaded CMOS ring-oscillator delays . . .119 5.16UFDG/Spice3-predictedsensitivitycomparisonofthetwounderlapped DG FinFET designs to the variation of straggle. . . . . . . . .121 5.17UFDG/Spice3-predictedsensitivitycomparisonofthetwounderlapped DG FinFET designs to the variation of straggle. . . . . . . . .122 A.1Representativepotentialvariationsinyatagivenxandcorresponding linear approximations . . . . . . . . . . . . . . . . . .134 B.1Medici-predicted gate capacitance at low and high VDS. . . . .138 B.2Medici-predicted saturation gate capacitance . . . . . . . . .140 B.3Medici-predicted saturation gate capacitance . . . . . . . . .141 B.4Medici-predicted electron density profile across the SOI film. . .143 B.5Integrated inversion charge and its differentiation. . . . . . .144 B.6Medici-predicted surface and bulk electron density and its differentiation. . . . . . . . . . . . . . . . . . . . . .146 B.7Equivalent circuits of a DG MOS capacitor in the strong inversion region. . . . . . . . . . . . . . . . . . . . . . . . . .147

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x KEY TO ABBREVIATIONS ADGasymmetrical double-gate BOXburied-oxide CMOScomplementary metal-oxide-semiconductor DGdouble-gate DIBLdrain-induced barrier lowering EOTequivalent oxide thickness FDfully depleted GIDLgate-induced-drain leakage G-S/Dgate-source/drain HPhigh performance LOPlow operating power LSTPlow standby power MOSFETmetal-oxide-semiconductor field-effect transistor PDpartially depleted QMquantum mechanical ROring oscillator SCEshort-channel effect S/Dsource/drain SDGsymmetrical double-gate SGsingle gate

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xi SNMstatic noise margin SOIsilicon-on-insulator SRAMstatic random access memory TGtriple-gate UFDGUniversity of Florida double-gate (model) UFPDBUniversityofFloridapartiallydepletedSOIandbulk MOSFET (model) UTBultra-thin body

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xii Abstract of Dissertation Presented to the Graduate SchooloftheUniversityofFloridainPartialFulfillment of the Requirements for the Degree of Doctor of Philosophy NONCLASSICAL NANOSCALE CMOS: PERFORMANCE PROJECTIONS,DESIGNOPTIMIZATION,ANDPHYSICALMODELING By Seung-Hwan Kim December 2006 Chairman: Jerry G. Fossum Major Department: Electrical and Computer Engineering Thisdissertationaddressesperformanceprojections,design optimization,andphysicalmodelingissuesofnonclassicalnanoscale CMOSdeviceswithUTBs,assessingtheirpotentialtobecomethebasisof the near-future mainstream semiconductor technology. WithregardtospeedandimmunitytoSCEs,DGMOSFETsare projectedtobegenerallysuperiortotheSGcounterpartsbecauseoftheir bettergatecontrolandhigherdrivecurrents.However,forlightloadsand moderatesupplyvoltages,asuboptimalSGFD/SOIMOSFETdesignfor bothLOPandHPCMOSapplicationsisfoundtoyieldspeedscomparable totheDGdesignsbasedontheirmuchlowerintrinsicCG,eventhoughits currentdriveismuchloweranditsSCEsaremuchmoresevere.Compared tononclassicalCMOSdesigns,thedelayofSGbulk-SiCMOSispredicted tobemuchlongerduemainlytoitshighCGintheweak/moderate inversion region and relatively low drive current.

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xiii RelativevaluesofIoninundoped-UTBDGandTGFinFETsare examinedvia3-Dnumericaldevicesimulations.Thesimulationresults revealsignificantbulkinversioninthefinbodies,whichlimitsthebenefit ofthethird(top)gateintheTGFinFETandwhichnegatestheutilityof thecommonlydefinedeffectivegatewidth(Weff=2hSi+wSi).Eventhe conceptofWefffortheTGFinFETisinvalidated,buttheproperWefffor theDGFinFETisdefined.Physicalinsightsattainedfromthesimulations furthersolidifyournotion,basedpreviouslyongatelayout-area inefficiency, that the third gate is neither desirable nor beneficial. ParasiticG-S/DfringecapacitanceinnonclassicalnanoscaleCMOS devicesisshown,using2-Dnumericalsimulations,tobeverysignificant, gatebias-dependent,andsubstantiallyreducedbywelldesignedG-S/D underlap.Analyticalmodelingoftheouterandinnercomponentsofthe fringecapacitanceisdevelopedandverifiedbythenumericalsimulations; aBOX-fringecomponentismodeledforSGFD/SOIMOSFETs.Withthe newmodelingimplementedinUFDG,UFDG/Spice3showshownanoscale DGCMOSspeedisseverelyaffectedbythefringecapacitance,andhow this effect can be moderated by optimal underlap. Basedonthetrade-offbetweenSCEsandIon,anoptimalunderlap, whichisdefinedbyshortLextand sL,isdefinedforSRAMapplications. ThisoptimizationgiveshighVtalongwithsmalllossofIon.FortheCMOS speedissue,devicesareoptimallydesignedwithlongLextand sLsincethe lattertendstodecreaseVtandthuskeepIonhigh,whiletheparasitic capacitanceinweakinversiondecreaseswiththeunderlap.Withregard tothesensitivityissue,relativelylongunderlap,viashortLextand sL,is generallybeneficialforboththeSRAMapplicationsandtheCMOSspeed.

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1 CHAPTER 1 INTRODUCTION Scale-downofdevicedimensionsinconventionalbulk-silicon CMOStechnologyhasbeenaprimarydrivingforceofthesemiconductor industrydevelopmentoverthepastthreedecades.Thebetterperformance withthesmallersizeofthedeviceshasbeenthebasisofthisdevelopment. However,forconventionalbulk-Si(andpartiallydepleted(PD)SOI) CMOS,continuedscalingmuchbeyondaphysicalgatelength(Lg)of ~50nm[Sem01]isdoubtful.Thisisbecauseofsevereshort-channeleffects (SCEs),highoff-stateleakagecurrents,andunacceptablylowIon/Ioffratios.Indeed,controllingthebodydopingwithinverysmalldimensions, whichisrequiredforSCEcontrol,hasbeenthemostdifficult technologicalchallengetoovercomeforfurtherscaling.Hence,thereisa growinginterestinnonclassicalfullydepleted(FD)SOIsingle-gate(SG) anddouble-gate(DG)MOSFETswithultra-thinbodies(UTBs),which haveinherentsuppressionofSCEs.Theirsmallintrinsicgatecapacitance inweak/moderateinversionand,especiallyforDGdevices,thehighIon/ Ioffratiostemmingfromthenearlyidealsubthresholdgateswingimply substantialCMOSspeedsuperiorityovertheclassicalSGcounterparts [Fos02].However,DGtechnologyiscomplex;theDGFinFET[His98, Hua99]iseasiesttofabricate,butitsprovenutilityisyearsaway.

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2 Contrarily,FD/SOISGtechnologyislesscomplicated;SOIUTBsand metal gates are the main obstacles in its development [Cho00]. Becauseofthetechnologicalcomplexitiesanddifficulties associatedwithDGCMOS,questionshavebeenposedaboutthe performanceadvantage,relativetoSGCMOS,thatitcanpotentially provide.Forexample,iftheDGMOSFETgivestwicethecurrent,butwith twicethegatecapacitance,thenexcessivedeviceparasiticsimpliedbythe complextechnologymightrenderinferiorperformance.Further,ithas beenarguedthatSCEsinthebulk-SiSGMOSFETcouldbeeffectively suppressedbysuper-halochanneldopingsuchthatbulk-SiCMOScould actuallybescaleddownto25nmchannellengths[Tau98].However,this argumentissimulation-based,andthereisuncertaintyaboutthephysical modelingassumed[Ge01]andwhethertheassumeddevicestructure couldevenbefabricated[Tau98].Nonetheless,givensuchahypothetical nanoscalebulk-SiCMOStechnology,moredetailedinsightsonthe relativeperformancepotentialsofnonclassicalUTBCMOSwouldbe usefulindecidinghowandiftheyshouldbeaggressivelypursued. Inchapter2,usingourprocess/physics-basedcompactmodels (UFDG[Fos03a]andUFPDB[Fos97])inSpice3,weprojectdevice characteristicsandCMOSperformancesofnonclassicalUTBCMOS technologies(FD/SOIandDG)andclassical,hypotheticalbulk-Si technologiesoptimizedattheLg=28nmnode.Comparisonsofpredicted SCEsofnonclassicaldevicesandspeed(ROdelays)ofthenonclassicaland classicalCMOStechnologiesaremade,andgoodphysicalinsights

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3 regardingtheirrelativecharacteristicsaregiven.Namely,wefirst compareasymmetricalandsymmetricalDG,andFD/SOISGdevicesvia simulationsdonewithourprocess/physics-basedcompactmodelUFDG [Fos03a,Fos04a],withemphasisontheirimmunitytoSCEs.Then,using UFDG,weoptimallydesignthesenonclassicaldevicesfor28nmgate length,andprojecttheircharacteristics,includingCMOSring-oscillator delays,whichwecomparewithprojectionsofahypothetical28nmbulk-Si SGCMOSdesignderived,usingourUFPDBcompactmodel[Fos97],from Tauretal.[Tau98].Interpretationsofthesimulationresultsgivegood physicalinsightsonthenonclassicaltechnologies,andindicatewhich onesmightbestreplacetheclassicaltechnologiesatnanoscalenodesof the SIA ITRS [Sem01]. WhiletheDGFinFEThasbecomealeadingdeviceoptionfor futurenanoscaleCMOS,thereisatechnologicallimittotheaspectratio (Rf)oftheSi-finheight(hSi)tothewidth(wSi).SincewSimustbeultrathinforgoodcontrolofSCEs[Fos04b],thislimitimpliessmalleffective gatewidth(commonlyassumedtobeWeff@ 2hSi)and,ostensibly,lowIonperpitch.ThereisthereforeinterestinmakingtheFinFETatriple-gate (TG)transistorbyactivatingthetopgate,yielding,fromasurface inversion-chargeperspective,Weff@ 2hSi+wSiasiscommonlyassumed, andalleviating,withadopedfin-body,thethin-wSirequirement[Doy03]. However,becauseoffin-cornereffects[Fos03b]andtechnological limitations[Tri03a],thefin-bodymustbeleftundoped,andsorelaxation ofthethin-wSi(i.e.,UTB)requirementforSCEcontrolfortheTGFinFET,

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4 relativetothatfortheDGdevice,isminimal[Fos04b].Nonetheless,the largerWefffortheTGdevicecouldmeansignificantlyhigherIonrelative to that of the DG FinFET even when wSi is thin for good SCE control. Inchapter3,tocheckthebenefitofactivatingthetopgateof FinFETs,relativevaluesofIoninundoped-bodyDGandTGFinFETsare examinedviathree-dimensional(3-D)numericaldevicesimulations [Dav03].Simulationresultsshowthatfin-bodybulkinversioninstrong inversionlimitsthebenefitofthethird(top)gateintheTGFinFET,and thecommonlydefinedWeffisinappropriateasanindicatorofIon.Thus, wedefinetheproperWefffortheDGFinFETreflectingbulkinversionand, basedonthisproper(re)definitionofWeff,examinethegatelayout-area issue [Yan05] of FinFET CMOS. NonclassicalnanoscalesiliconCMOSdevices,e.g.,DGandSG FD/SOIMOSFETswithundopedUTBs,shouldbedesignedwithgatesource/drain(G-S/D)underlap[Tri05a].Thebenefitsoftheunderlap includebettercontrolofSCEsviaagatebias-dependenteffectivechannel length(Leff)[Fos03c,Tri05a],aswellaseliminationofgate-induceddrain leakage(GIDL)[Tan05]andgate-drain/sourcetunnelingcurrents.The underlap,however,mustbeoptimallydesignedbecauseittendsto increasethesource/drain(S/D)seriesresistance(RSD)anddecreaseIon[She03, Tan05]. FringecapacitanceinclassicalMOSFETs,withG-S/Doverlap, wasmodeledsometimeago[Shr82],andsomemodelingwasrecently

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5 reported[Ban05]forDGMOSFETswithunderlap.However,themodeling ofBansaletal.[Ban05]focusedonabias-independentouter-fringe capacitance,anddidnotaddresstheVGSdependenceofitaswellasthe inner-fringe component, which is quite important in nanoscale devices. Inchapter4,weshow,bydeviceandcircuitmodelingand simulation,thesignificanceandgate-biasdependenceofparasiticfringe capacitanceinnonclassicalCMOSdeviceswithG-S/Dunderlap.Basedon theinsightsderivedfromnumericaldevicesimulations,wedevelopa completeanalyticalmodelforparasiticcapacitanceinnonclassicaldevices withG-S/Dunderlap,whichincludesboththeouter-andinner-fringe componentswithVGSdependences,aswellasaBOX-fringecomponentin theFD/SOIMOSFET.Thenewmodelingisverifiedby2-Dnumerical devicesimulations.UsinganewversionofUFDGwiththeparasiticfringe capacitancemodel,wecheckROdelaystoshowthattheimpliedunderlap designtradeoffforultimateCMOSspeedisaffectedsignificantlyby parasiticG-S/Dcapacitance,i.e.,fringecapacitance,innanoscaledevices. Asmentioned,DGFinFETswithundopedUTBsarevery attractiveforscaledCMOSduetotheirinherentbenefits,i.e.,betterSCE control,smallerintrinsicgatecapacitanceinweak/moderateinversion, andhighIon/Ioffratio.However,withtheultimatelimitofUTB,i.e.,~5nm [Tri03a]duetoseverequantizationeffectsandtechnologicaldifficulties, DGFinFETscalingtoandbeyondtheHP25nodewithLg=10nm[Sem05] seemstobeextremelydifficultsincethefinthicknessrequiredforSCE

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6 controliswSi@ Leff/2[Yan05]ifhighk gatedielectricisnotviable.Thus, forfurthergatelengthscalingto10nmandbeyond,nonclassicalCMOS deviceshavetobedesignedwiththeG-S/Dunderlap[Tri05a].Evenforthe Lg>10nmregimeor/andwhenareliablehighk gatedielectricis developed,theunderlapstructureshouldbequiteusefulinthedevice designforeffectinganoptimalSCEsvs.Iontrade-off[Kra06,Lim05, Tri05a]. ThisbenefitoftheunderlapstructureintheDGFinFETshould bemostusefulforSRAMapplications.ThisisbecausehighVttendsto givelargereadstaticnoisemargin(read-SNM)andwrite-margin[Guo05], andcanbeeasilyobtainedbySCEcontrolviatheeffectivechannellength (Leff)modulationintheweak-inversionregion[Fos03c].Ontheother hand,forthedevicespeedissue,withtheinsightgainedfromthe relationshipbetweentheS/DdopingprofileandVt(andthusIon),wecan minimizetheIonloss,stillkeepingtheparasiticcapacitancesmallby controllingtheextensionlength(Lext)andstraggle( sL).Thus,the underlap can also be quite useful in improving the device speed. Inchapter5,wefirstexploreSRAMcelldesignandscalingvia DGFinFETswithG-S/Dunderlap.Forthisstudy,DGFinFETswith underlaparefirstcharacterizedintermsofVtforvariousLext, sL,andwSivia2-Dnumerical[Med04]andanalyticalsimulations[Fos06a].The relationshipbetweenVtandread-SNMisverifiedtodefineanoptimal SRAMcell,fortheHP45nodewithLg=18nm[Sem05],withlargeread-

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7 SNMandwrite-marginaswellaslesssensitivitytoprocessvariationsof Lextand sL.Then,ascalabilitystudyofDGFinFET-basedSRAMcell, withandwithouttheG-S/Dunderlap,isdone.Finally,basedonthe insightgainedfromVtshiftandIonvariationby sLchanges,weoptimally design DG FinFETs to improve the device speed. InChapter6,thisdissertationisconcludedwithasummaryand suggestions for future works. AppendixesAandBdescribesupportingUFDGmodelstudies and a unique DG MOSFET feature, respectively.

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8 CHAPTER 2 NANOSCALECMOS:POTENTIALNONCLASSICALTECHNOLOGIES VERSUS A HYPOTHETICAL BULK-SILICON TECHNOLOGY 2.1 Introduction Forclassicalbulk-Siandpartiallydepleted(PD)SOICMOS, continuedscalingmuchbeyondaphysicalgatelengthof~50nm[Sem01] isdoubtfulbecauseofsevereshort-channeleffects(SCEs)and unacceptablylowIon/Ioffratio.Hence,thereisagrowinginterestin nonclassicalfullydepleted(FD)SOIsingle-gate(SG)anddouble-gate (DG)MOSFETswithultra-thinbodies(UTBs)becauseoftheirinherent suppressionofSCEs.Further,theirsmallintrinsicgatecapacitancein weak/moderateinversionand,especiallyforDGdevices,thehighIon/Ioffratiostemmingfromthenearlyidealsubthresholdgateswingimply substantialCMOSspeedsuperiorityovertheclassicalSGcounterparts [Fos02].However,DGtechnologyiscomplex;theDGFinFET[His98, Hua99]iseasiesttofabricate,butitsprovenutilityisyearsaway. Contrarily,FD/SOISGtechnologyislesscomplicated;UTBsandmetal gates are the main obstacles in its development [Cho00]. Becauseofthetechnologicalcomplexitiesanddifficulties associatedwithDGCMOS,questionshavebeenposedaboutthe performanceadvantagerelativetoSGCMOSthatitcanpotentially provide.Forexample,iftheDGMOSFETgivestwicethecurrent,butwith

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9 twicethegatecapacitance,thenexcessivedeviceparasiticsimpliedbythe complextechnologymightrenderinferiorperformance.Further,ithas beenarguedthatSCEsinthebulk-SiSGMOSFETcouldbeeffectively suppressedbysuper-halochanneldopingsuchthatbulk-SiCMOScould actuallybescaleddownto25nmchannellengths[Tau98].However,this argumentissimulation-based,andthereisuncertaintyaboutthephysical modelingassumed[Ge01]andwhethertheassumeddevicestructure couldevenbefabricated[Tau98].Nonetheless,givensuchahypothetical nanoscalebulk-SiCMOStechnology,moredetailedinsightsonthe relativeperformancepotentialsofnonclassicalUTBCMOSwouldbe useful in deciding how and if they should be aggressively pursued. Inthischapter,wefirstcompareasymmetricalandsymmetrical DG,andFD/SOISGdevicesviasimulationsdonewithourprocess/ physics-basedcompactmodelUFDG[Fos03a,Fos04a],withemphasison theirimmunitytoSCEs.Then,usingUFDG,weoptimallydesignthese nonclassicaldevicesfor28nmgatelength,andprojecttheir characteristics,includingCMOSring-oscillatordelays,whichwecompare withprojectionsofahypothetical28nmbulk-SiSGCMOSdesignderived, usingourUFPDBcompactmodel[Fos97],fromTauretal.[Tau98]. Interpretationsofthesimulationresultsgivegoodphysicalinsightsonthe nonclassicaltechnologies,andindicatewhichonesmightbestreplacethe classical technologies at nanoscale nodes of the SIA ITRS [Sem01].

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10 2.2 UFDG, UFPDB, and Simulation Conditions TheUFDGmodel[Fos03a,Fos04a]isgeneric,andhence applicabletoFD/SGMOSFETswithrelativelythickorthin[Fen03]back gateoxideaswellastobothasymmetrical(ADG)andsymmetrical(SDG) DGMOSFETs.Theprocess/physicsbasisofUFDGmakesitpredictiveand usefulfordoingthecomparativeprojections.Themodelparameterscanbe definedlargelyfromthedevicestructureandphysics.UFDGpredicts SCEsmainlyviaa2DsolutionofPoissonsequationintheUTBforweakinversionconditions[Yeh95].Inthestrong-inversionregion,the quantum-mechanicalcarrierconfinementisincorporatedinUFDGviathe derivationofaniterative,self-consistentsolution,dependentonbothgate voltagesVGfSandVGbS,ofthe1D(inx)SchrdingerandPoissonequations intheUTB/channel[Ge02].Thissolutionfurtherphysicallyaccountsfor thechargecouplingbetweenthefrontandbackgates,andproperlymodels thechargedistributionthroughouttheSi-filmUTB.UFDGalsoaccounts forthedependencesofcarriermobilityontheUTBthickness(tSi)aswell asonthetransverseelectricfield(Ex),andquasi-ballisticcarrier transportinscaleddevicesismodeledviacarrier-velocityovershoot, whichischaracterizedintermsofcarriertemperature[Ge01].Inaddition, UFDGincludestheparasitic(coupled)BJT(currentandcharge)and temperaturedependencewithouttheneedforanyadditionalparameters. TheUFPDBmodel[Fos97]isalsoprocess/physics-based,andis unifiedforapplicationtoPD/SOIaswellasbulk-SiSGMOSFETs.This

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11 modelisbasedonapresumedretrograded,orsuper-haloed,channel,and itphysicallyaccountsforpolysilicon-gatedepletion[Chi01],carrierenergyquantization[Chi01],carriervelocitysaturationwithpossible overshoot [Ge01], and gate-body tunneling current [Yan04]. Forthenonclassicaldevices,weassumeundopedbodiessince, technologically,dopantcontrolinUTBsisvirtuallyimpossible,asin extremelyscaledbulk-SiandPD/SOIMOSFETs.Then,sincethenumber ofnaturaldopantsinthebodywillactuallybezerowhendevice dimensionsareextremelyscaled,theUTBsaremodeledasintrinsic. However,toavoidnumericalinstabilitiesinUFDG,NB=1015/cm3isused forthesimulations.Indeed,suchasmallNBisvirtuallyequivalenttoNB=0[Tri03a].ForSDGandFD/SGdevices,weselectmetalgates(forVtcontrol),whilen+-andp+-polysilicongatesareassumedforADGdevices, butwithoutaccountingforgate-depletioneffects(whichisjustified somewhatbytherelativelylowEx).Thefrontandbackgate-oxide thicknesses(orEOTs)areassumedequalintheDGdevices,exceptfora briefanalysisoftheeffectsofunequalthicknessesinADGdevices.Forthe FD/SGdevices,athickburiedoxide(tBOX=200nm)onalightlydoped (1015/cm3)p-typeSisubstrateisassumed.Weignorethesource/drainfield fringingintheBOX[Yeh95],whichcanexacerbatetheSCEsthatare predominantlygovernedbytheUTB.Hence,itshouldbenotedthatthe actualeffectivechannellengths(Leff)ofgivenFD/SGdevicesmightbea bitlonger(by~3-5nm)thanthevaluesstated.However,iftheactual

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12 devicesweredesignedwithgate-source/drainunderlap[Tri05a],which willprobablybenecessary,thentheresultsofourstudyarereasonableas given.TheeffectsofthinningtBOXaresubsequentlyexamined.Forthe bulk-Si/SGCMOS,n+-andp+-polysilicongates,withgate-depletion effects,areassumedfornMOSFETandpMOSFET,respectively.We employaretrogradedchannel,whichadequatelyreflectsthesuper-halo dopingsuggestedbyTauretal.[Tau98],andVtistunedviathelower, surface doping density (NBL in UFPDB). 2.3 Immunity to Short-channel Effects WefirstcompareSCEsinthenonclassicalDGandFD/SG MOSFETs.UsingUFDG,wevarythegatelength(Lg,assumedtoequal Leff)from500nmto28nm,fixingtSiandthegate-oxidethickness(toxfand toxbfortheDGdevices)at10nmand3nm,respectively.Thepredicted thresholdvoltageroll-offs( D Vt(Lg)atVDS=50mV)oftheADG,SDG,and FD/SGn-channeldevicesarecomparedinFig.2.1.Here,foreachdevice, VtisdefinedviaIDS(VGS=Vt)=10-7Wg/Lg(A),andVtoftheLg=500nm deviceistakenasthereference.Asindicatedinthefigure,fortheADG andSDGdevices, D Vtisnegligibleandnosignificantdifferencesbetween thetwoDGdevicesareevidentdowntoLg~70nm.However,whenLgis scaledbelow~70nm,theADGMOSFETsshowsuperior D Vtcontrolover theSDGcounterparts.ThiscanbeexplainedbythehigherExand strongergate-gatechargecouplingintheADGdevices[Kim01].Forthe FD/SGMOSFETs,asclearlyshowninFig.2.1,theVtroll-offismuchmore

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13 Figure 2.1UFDG-predictedthresholdvoltageroll-off(solidline)and DIBL(dashline)versusgatelength(=Leff)oftheADG,SDG, andFD/SGn-channeldeviceswithtoxf=toxb=3nm(forFD/SG, tBOX=200nm)andtSi=10nm;VtisdefinedviaIDS(VGS=Vt) =10-7Wg/Lg[A]atVDS=50mV,and,foreachdevice,Vtofthe Lg=500nmdeviceistakenasthereference.DIBLisdefined via D V=Vt(VDS=50mV)-Vt(VDS=1.0V). 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20D V [V] 100Lg[nm] -0.18 -0.16 -0.14 -0.12 -0.10 -0.08 -0.06 -0.04 -0.02 0.00D Vt [V] ADG SDG FD/SG500 20 D VD Vt

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14 severethanthoseoftheDGcounterparts,implyingthatmuchthinner UTB will be necessary to control the SCEs in FD/SG CMOS. AlsoinFig.2.1,predictedDIBL(definedby D V=Vt(VDS=50mV) -Vt(VDS=1.0V))isgiven,showingsimilarsuperiorityoftheDGdevices overtheFD/SGdevice.And,asfor D Vt,theADGdeviceisbetterthanthe SDGdevicewithregardto D V.Thepredictedsubthresholdgateswing(S) showstrendssimilartothoseof D Vtand D VshowninFig.2.1.Also,we observethatforlongLg(>~70nm),Sapproachesitsidealvalue(60mVat 300K)forbothDGdevices,andnearlyso(61mV)fortheFD/SGdevice sincethebody-effectcoefficient(m=1+CBody/Coxf@ 1+Coxb/Coxf[Lim85]) is only slightly greater than unity due to the thick tBOX. 2.4 28nm Device Design TocompareclassicalandnonclassicalCMOSperformance potentials,wefirstuseUFDGandUFPDBtooptimallydesignthedevices attheLg=28nmnode.ConsidertheADGnMOSFETinitially.Toreduce theSCEsreflectedbyFig.2.1toacceptablevalues,twoapproachesare checked:thinningthegateoxideandthinningtheSi-filmthickness. UFDGshowsthatwhentoxf=toxb toxisdecreasedfrom3nmto1nmin theADGnMOSFET(tSiremainsfixedat10nm),theSCEs( D VandS)are steadilyandsignificantlyimproved.Further,becauseoftheloweringofS, Ioniscontinuallyincreased,andIoffisdecreased.However,thinningthe oxidethicknesstoward1nmisnotnecessarilyoptimalduetotheabrupt increaseofgate-tunnelingleakagecurrent[Gha00,Yan04].Indeed,forthe

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15 ADGdevice,limitingtoxat2nmmightbe,withthintSi,enoughto suppresssevereSCEs:wepredict D V~56mVandS~76mVforthistox. However,withn+-andp+-polysilicongates,thisADGdevice design,i.e.,tox=2nmandtSi=10nm,isnotviableforhigh-performance (HP)CMOSapplications[Sem01],evenwithmodificationoftSi;thelow Ioff(~5.0nA/ m m)reflectsatoo-lowIon.Rather,thisdesigncanbemade applicabletolow-operation-power(LOP)CMOS(Ioff~0.8nA/ m mfromthe ITRSroadmap[Sem01])byadjustingtSito8.6nm.Therefore,our pragmaticoptimalADGdesignisinitiallytakenastox=2nmandtSi= 8.6nm for LOP applications. Analogoustothinningtox,decreasingtSifrom10nmto6nmin theADGdevice(withtoxheldat3nm)alsoyieldssteadyimprovementin SCEcontrol(reductionsin D VandS),butsincethereductioninSis relativelysmall,theincreaseinIonisnotassignificantasthatobtained bythinningtox.WenotefurtherthatVtandIoffoftheADGdevicemight becontrolled,withoutmuchchangeinIon,byadjustingtSi,keepingthe pragmaticn+-andp+-polysilicongates,insteadofvaryingthechannel doping, which is not viable. ToassessthetwonotedapproachesforoptimizingtheADG devicedesign,weshowinFig.2.2UFDG-predictedIDS(VGS) characteristicsoftheinitiallyoptimizeddeviceandofonedesignedwith thesameIoffviathinnertSi(7.4nm)andthickertox(3nm).Asevidentin thisfigure,theformerdevice,withthethinnertox,showslowerSand

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16 Figure 2.2UFDG-predictedcurrent-gatevoltagecharacteristics,atlow andhighdrainvoltages,oftheinitiallyoptimized28nmADG deviceandofonedesignedwiththesameIoff(~0.76nA/mm) via thinner tSi and thicker tox. -0.10.10.30.50.70.91.1VGS [V] 10-1210-1110-1010-910-810-710-610-510-410-3IDS [A/ m m] tox=3nm, tSi=7.4nm tox=2nm, tSi=8.6nm VDS=1.0V VDS=50mV0

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17 higherIon,andhenceitissolidifiedasouroptimal28nmADGMOSFET for LOP applications. TogainmoreinsightonthisADGdevicedesign,weshowinFig. 2.3predictedeffectsofseparatelyvaryingtoxfandtoxb.InFig.2.3(a),we seethatvaryingonlytoxfofferssomecontrolofVt.However,wealsosee thatSandIonaredegradedwhenusingthickertoxfduetothedecreased sensitivityofthebodypotentialtothevoltagechangeonthefrontgate. Interestingly,however,inFig.2.3(b)weseethatvaryingonlytoxbismore effectiveincontrollingVt,withsmallereffectsonSandIon.Thisis becausetheADGMOSFEThasonlyonepredominantchannel,whichis closertothefront(n+)gate[Kim01].Thus,forADGdeviceswithn+-and p+-polysilicongates,varyingtoxb,withfixedtoxfforSCEcontrol,mightbe usefulforVttuning.However,forlow-standby-power(LSTP)applications withverylowIoff~1pA/ m m[Sem01],thisapproachtoVtcontrolshould also include tSi variation, as indicated in Fig. 2.3(b). Now,forafaircomparison,wedesigntheSDG(e.g.,aFinFET) andFD/SGnMOSFETswiththesamestructureastheoptimizedADG device,i.e.,withtox=2nmandtSi=8.6nm,andthesameIoff(~0.8nA/ m m)for LOPapplications.WegetthespecifiedIoffbytuningthemetal-gatework functions(whichmightnotbesoeasilydonetechnologically): FM=4.62V fortheSDGdevice,and FM=5.02VfortheFD/SGdevice.And,knowing theFD/SGMOSFETwillshowinferiorSCEcontrol,wealsodefineamore aggressive,optimalversionofitwithtox=1nmandtSi=5nm,whichare

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18 Figure 2.3UFDG-predictedeffectsof(a)separatelyvaryingtoxfinthe ADGdevicewithtoxbfixedat2nmand(b)separatelyvarying toxbintheADGdevicewithtoxffixedat2nm,showingsome controlofbothVtandS,andhowtheeffectsareenhanced when tSi is thinned to 6nm (shown in (b)).toxf=2, 2.5, 3, 3.5nm (from left to right) toxb=2nm tSi=8.6nm -0.10.10.30.50.70.91.1VGS [V] 10-1310-1210-1110-1010-910-810-710-610-510-410-3IDS [A/ m m] VDS=50mV VDS=1.0V 0 tSi=6nm toxf=2nm -0.10.10.30.50.70.91.1VGS [V] 10-1410-1310-1210-1110-1010-910-810-710-610-510-410-3IDS [A/ m m] VDS=50mV VDS=1.0V High VDS: toxb=2.5, 2, 1.5nm (from left to right) Low VDS: toxb=2.5, 2nm (from left to right) High VDS: toxb=2, 1.5, 1nm (from left to right) Low VDS: toxb=2, 1.5nm (from left to right) tSi=8.6nm 0(a) (b)

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19 closetothetechnologicallimitsofthesestructuralparameters.This optimaldeviceisalsodesigned,neglectingthepossiblesignificanceof gate-tunnelingleakage,tohavethesameIoff(with FM=4.51V)asthatof the optimized ADG device. Forthehypotheticalbulk-Si/SGnMOSFETdesign,weuse UFPDB,generallyfollowingTauretal.[Tau98]forSCEcontrol,butusing amoreaggressivelyscaledgateoxide,tox=1nmasfortheoptimalFD/SG device,withgatetunnelingstillneglected.Theretrogradedchannelis definedwithsurfacedopingdensityNBL=3.42 1018/cm3,apeakbody dopingdensity(NBH)of1019/cm3,andaneffectivedepletionthickness(TB) of14.2nm.ThenotedNBLofthisnMOSFET,withn+-polysilicongate,was tunedtoyieldIoffequaltothatofthenonclassicaldevices.Notethatthis channel/bodydopingprofileisprobablynotmanufacturable,renderinga hypothetical device. Figure2.4showsUFDG/UFPDB-predictedIDS(VGS) characteristicsofthetwooptimalDGdevices,ofthetwodesignedFD/SG devices,andofthebulk-Si/SGdevice.Clearly,thesuboptimalFDdevice withthethickertSi(=8.6nm)suffersfromsevereSCEs; D V @ 266mVand S @ 108mV.However,theSDGdevice,liketheADGdevicewiththesame tSi,showsgoodcontroloftheSCEs,withtheADGdevicebeingabit superiorinthisregard; D Vis42mVand72mVfortheADGandSDG devices,respectively,andSis72mVand74mV.Fortheoptimal,thinnertSi(=5nm)FD/SGdevice,goodSCEs( D V @ 43mVandS @ 71mV)andlarger

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20 Figure 2.4UFDG/UFPDB-predictedcurrent-gatevoltage characteristicsofthetwooptimallydesignedDG nMOSFETs,withtox=2nmandtSi=8.6nm,ofthetwo designedFD/SGnMOSFETs,i.e.,optimalFD/SGwith toxf=1nm,tBOX=200nm,andtSi=5nm,andsuboptimalFD/SG withtoxf=2nm,tBOX=200nm,andtSi=8.6nm,andofthe optimallydesignedbulk-Si/SGnMOSFET,withtox=1nmand TB=14.2nm,athighdrainvoltage;foralldevices,Lg=28nm and Ioff=0.76nA/ m m. -0.10.10.30.50.70.91.1VGS [V] 10-1010-910-810-710-610-510-410-3IDS [A/ m m] ADG SDG Suboptimal FD/SG Optimal FD/SG Bulk-Si SGVDS=1.0V 0 DIBL ( D V)ADG42mV SDG72mV Suboptimal FD/SG266mV Optimal FD/SG43mV Bulk-Si SG123mV

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21 Ion,relativetothesuboptimaldesign,arepredicted.Westress,however, thatiftheDGdeviceswerethinnedtotSi=5nm,theirSCEswouldbe virtuallynonexistent(asUFDGsimulationsshow).Forthebulk-Si/SG device,theSCEsareeffectivelysuppressedduetothethinTBasshownin theFig.2.4.NoteherethatsinceDIBLrendersaminoreffectonthedelay performance[Tau98],weselectedTBtogetrelativelysmallS(~80mV), sacrificingDIBL(~120mV)andnecessitatingthehighNBLtokeepIoffunder control. Asmentioned,theapplicationsofthedesignedADGdevice,with n+-andp+-polysilicongates,arelimitedtoLOP.Thus,forHP applications,wecanconsideronlythedefinedSDGandFD/SGdevices withnewmetalgates( FMis4.39VfortheSDGdevice,and4.69Vand 4.29VforthesuboptimalandoptimalFD/SGdevices,respectively),and thehypotheticalbulk-Si/SGdevicewithnewTB(17.5nm,tokeepS~ 80mV) and NBL (1018/cm3) for appropriate Ion/Ioff. FortheCMOStechnologies,theSDGandFD/SGpMOSFETsare designedtohavethesameIoffasthatoftheADGnMOSFETbyusing metalgatesandtuningtheworkfunctions.However,fortheADG pMOSFET,n+-andp+-polysilicongatesarestillassumed,butswitchedfor thebackandfrontgates,respectively.Thusthereisaslightdiscrepancy inIoffbetweenthetwoADGCMOSdevicesbecauseofthedifferent electronandholemobilities.Thebulk-SipMOSFETsarealsodesignedto havethespecifiedIoffbyadjustingNBLwithap+-polysilicongate,keeping

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22 TBandNBHthesameinthenMOSFETs.Forring-oscillatorsimulations, weassumethesource/drainareasofthebulk-SiCMOSdevicesaredefined based on lengths of 3 (pitch/2) [Sem01]. 2.5 CMOS Performance Projections TocompareCMOSspeeds,9-stageunloadedCMOS-inverterring oscillators(ROs)weresimulatedwithUFDGandUFPDBinSpice3. Predictedpropagationdelaysfortheclassicalandthefournonclassical devicedesigns(forLOP)areplottedinFig.2.5versussupplyvoltageVDD. Asexpected,theDGCMOSdesignsarefasterthantheSGones,including bulk-SiCMOS,overtheentirevoltagerange,whiletheADGandSDG CMOSdelaysarevirtuallythesame.Interestingly,theoptimalFD/SG designhascomparablespeedtotheDGCMOSdesigns:only~15%longer delayatVDD=1.2V.Further,thespeedofthesuboptimalFD/SGdesign isnotmuchworseathighVDD(~34%sloweratVDD=1.2V,comparedto theDGCMOS),althoughthedelaysaresignificantlylongeratVDD< ~1.0V.Contrarily,thepredictedROdelayforthebulk-SiSGCMOSis muchlongerthanthoseofallthenonclassicalCMOSdesignsoverthe entirevoltagerange,eventhoughthebulk-Sidevicesarehypotheticaland seemingly optimal. ForHP-applicableCMOS,i.e.,theSDG,theFD/SG,andthe bulk-Si/SGdesignsallwithIoff=0.7 m A/ m masnoted,theROsimulation results,showninFig.2.6,areveryinteresting.AsintheLOPCMOSRO results,theSDGdesignshowsspeedsuperiorityovertheoptimalFD/SG

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23 Figure 2.5UFDG/andUFPDB/Spice3-predictedpropagationdelays versussupplyvoltageof9-stageunloadedCMOS-inverter ringoscillatorscomprisingthefive28nmDG,FD/SG,and bulk-Si/SGLOPdevicedesigns.Gate-source/drainoverlapof 10%ofLgwasassumedforallgates.Threeofthefivedelay curvesarere-plottedintheinsetforbetterview.Theoffstate current of all devices was matched to 0.8nA/mm. 0.600.700.800.901.001.101.201.30 VDD [V] 0 5 10 15 20 25 30 35 40 45 50 55 60Delay/Stage [ps] SDG ADG Suboptimal FD/SG Optimal FD/SG Bulk-Si SG 0.60.70.80.91.01.11.21.3VDD [V] 2.0 2.5 3.0 3.5 4.0 4.5Delay/Stage [ps] SDG ADG Optimal FD/SG

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24 Figure 2.6UFDG/andUFPDB/Spice3-predictedpropagationdelays versussupplyvoltageof9-stageunloadedCMOS-inverter ringoscillatorscomprisingthefour28nmSDG,FD/SG,and bulk-Si/SGHPdevicedesigns.Gate-source/drainoverlapof 10%ofLgwasassumedforallgates.Theoff-statecurrentof all devices was matched to 0.7mA/mm. 0.60.70.80.91.01.11.2 VDD [V] 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5Delay/Stage [ps] SDG Suboptimal FD/SG Optimal FD/SG Bulk-Si SG

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25 andthebulk-Si/SGdesignsovertheentirevoltagerange.Surprisingly, however,thesuboptimaltSi=8.6nmFD/SGdesignactuallyyieldsshorter delayrelativetothatoftheSDGdesignforVDD>~0.95V;butforlower VDD,itbecomesslower.TheequivalentspeedperformanceforhigherVDDseemsinconsistentwiththepredictedcurrentsoftheFD/SGandSDG devicesforHP,whichcanbeinferredbyshiftingtheIDS(VGS) characteristicsforLOPinFig.2.4.TheFD/SGdeviceshowsmuchlower Ion (by ~37% at VDD = 1.0V). ToexplaintheseunexpectedsuboptimalFD/SGROresults,we considerintrinsicgatecapacitanceofthenonclassicaldevices.Inthe subthresholdregion,theinversionchargeisnegligible,andthusthegate capacitanceoftheintrinsicFD/SGMOSFETcanbeexpressedbythe seriescombinationofoxidecapacitanceandtheeffectivebodycapacitance [Lim85]: (2.1) whereCoxfisthefrontgateoxidecapacitanceandCBodyincludestheUTB depletioncapacitance,Cb= eSi/tSi,andtheburiedoxidecapacitance,Coxb= eox/toxb: .(2.2) ForthecommonthicktoxbforFD/SG,i.e.tBOX,CBodyin(2.2)isrelatively small,andhencesoisCGin(2.1).Indeed,thesubthreshold-regiongate C G 1 C oxf -----------1 C Body ----------------+ 1 C Body @ = C Body C oxb C b C oxb C b + --------------------------= C oxb C b C oxf @

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26 capacitanceoftheFD/SGdeviceisdefinedpredominantlybyparasitic capacitance,e.g.,thegate-source/drainoverlapcapacitance.Further,for VGSincreasingtostronginversion,theincreaseinCGdefinedbythe inversion-chargeis,inoursuboptimaltSi=8.6nmFD/SGdevice,deferred tohighervoltages(VGS~0.75V)becauseofthehighS.Therefore,the deviceshowsextremelysmallCG(includingtheparasitics)atlowVGS(~0.5V),asshownbytheUFDG-predictedcurveinFig.2.7.However, whenwethintSitogetbettercontroloftheSCEs,Sdecreases,andthe optimalFD/SGdeviceshows,alsoinFig.2.7,intermediate-VGSCGthatis muchlargerthanthatofthesuboptimalFD/SGdevice.Similarly,theDG devicesshowinFig.2.7,becauseofdeviceneutrality[Fos02],verysmall CGatlowVGS,buttheincreaseduetoinversionchargeoccursatlower VGSduetothelowS.ThecomparativeresultthenisthattheDGdevices showmuchhighergatecapacitancethanthesuboptimalFD/SGdeviceat allVGS.WebelievethattherelativeCG(VGS)curvesinFig.2.7, irrespectiveoftheIDS(VGS)characteristicsinferredfromFig.2.4,underlie the surprising RO results in Fig. 2.6. Unlikethenonclassicaldevices,CBodyoftheclassicalbulk-Si/SG deviceisdefinedbythelargedepletioncapacitance(i.e., eSi/TB),andhence CGisfiniteandsubstantiveasindicatedbytheUFPDB-predictedcurvein Fig.2.7.BecauseofthehighCGintheweak/moderateinversionregion,in additiontothearealsource/drainjunctioncapacitance,andthe polysilicon-gatedepletioneffectinstronginversion,thebulk-SiCMOS

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27 Figure 2.7UFDG-andUFPDB-predictedgatecapacitancesversusgate voltage,atlowdrainvoltage,forthefour28nmSDG,FD/SG, andbulk-Si/SGdevicedesigns.Gate-source/drainoverlapof 10% of Lg was assumed for all gates. -0.20.00.20.40.60.81.01.21.4VGS [V] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0CG [ m F/cm2] SDG Suboptimal FD/SG Optimal FD/SG Bulk-Si SG VDS=50mV

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28 speedismuchslowerthanthoseofthenonclassicalCMOSdesigns.The maineffectofthegatedepletionisreducedIon,asreflectedbythe decreasing CG for increasing VGS in Fig. 2.7. Thepropagationdelayreflectedbytheoscillationfrequencyof theROisdefinedbythepull-down(VDD-to-VDD/2)andpull-up(0-to-VDD/ 2)timesofaconstituentinverter.ThesetimesdependontheVDSdependentcurrents(IDS(t))inthedrivingtransistors,andonthe capacitiveloadattheoutputterminal,which,fortheunloadedRO,is predominantlythesumofthenMOSFETandpMOSFETgatecapacitances ofthenextstage(CGn(t)+CGp(t)).Wedefine,forpulldownintheSDGand thetwoFD/SGCMOSdesigns,thedynamiccurrentIDS(t)ofthedriving transistorbetweenVDS(t)=VDD,whichcorrespondstoVGS(t)=VDD/2, andVDS(t)=VDD/2.Similarly,wedefinethedynamicchargingcurrent (IQ(t))attheinverter-outputnode,whichisthegatecurrentofthenextstageinverter.WiththesetwodynamiccurrentsIDS(t)andIQ(t),wecan estimatethepull-downtime(tpd,whichiscomparabletothepull-uptime tpu)ofaconstituentinverterforeachdesign,andtherebyconfirmour belief about the surprising relative delays in Fig. 2.6. Tosimplifyourestimations,wedefineanaveragevalueofthe total gate-capacitance load, ,(2.3) and use it to approximate the pull-down delay as C G 2 V DD -----------I Q td0 t pd@

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29 .(2.4) Indeed,forVDD=0.65V,wegetusing(2.3)and(2.4) tpd@ 2.43psand 1.93psforsuboptimalFD/SGandSDG,respectively.However,forVDD= 1.2V,wefind tpd@ 1.49psand1.43psforFD/SGandSDG,respectively. (NotethattheestimateddelaysareabitshorterthanthepredictedRO delays(=(tpd+tpu)/2)inFig.2.6duetotheneglectedparasiticcapacitances suchasthegate-source/drainoverlapcapacitances.)Thus,these estimatedvaluesoftpdareinaccordwiththesurprisingresultsinFig.2.6, i.e.,thesignificantSDGspeedsuperiorityatlowvoltagesandthe comparable FD/SG speed at high voltages. Now,bydefininganaverage 1/IDSin(2.4)analogousto CGin (2.3),wecanevaluatethecontributionsofthedrivingcurrentandthe capacitiveloadindeterminingtheROdelaysforeachCMOSdesign.For VDD=0.65V,wegettheaverage-currentratio IDS(SDG)/ IDS(FD)@ ( 1/ IDS(FD))/( 1/IDS(SDG))=3.91,whereFDherereferstothesuboptimaltSi= 8.6nmdesign,andtheaverage-capacitanceratio CG(SDG)/ CG(FD)=3.09. ForVDD=1.2V,weget IDS(SDG)/ IDS(FD)=2.24and CG(SDG)/ CG(FD)=2.20. Theseratios,withreferenceto(2.4),explainthattheSDGspeed superiorityatlowvoltagescomesfromtherelativelyhighaveragedrive current(i.e., IDS(SDG)/ IDS(FD)> CG(SDG)/ CG(FD))intheSDGdevices.Also, theyexplainthatthesurprisingcomparableFDspeedathighVDDisdue totherelativelylowaveragegatecapacitance(i.e., IDS(SDG)/ IDS(FD)@ t pd td0 t pdC G 1 I DS V DS () --------------------------V DSdV DD V DD 2 @ =

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30 CG(SDG)/ CG(FD))intheFD/SGdevices.OtherROsimulationsdonewith UFDG/Spice3revealthatthisFD/SGspeedmeritathighVDDis maintainedwhenthegate-source/drainoverlapcapacitancesare increasedupto30%.However,fortheoptimalFD/SGdesignwithtSi= 5nm,wefindforallVDDthat CGand 1/IDSarecomparabletothe correspondingaveragesoftheDGdevice(i.e., CG(SDG)/ CG(FD)is1.06and 1.08and IDS(SDG)/ IDS(FD)is1.06and1.11forlowandhighVDD, respectively).Asaresult,weget,fromtheaverage CGand 1/IDS(or directlyusing(2.4)),thecomparabletpdfortheoptimalFD/SGcompared toSDG.AlltherelativeROdelaysofthenonclassicalCMOSinFig.2.6 arehenceexplained,andgoodphysicalinsightsregardingthemis attained. ThespeedcomparisonsinFigs.2.5and2.6werederivedfrom unloadedROsimulations.Withloading,weanticipatethattherelative performanceofthesuboptimalFD/SGCMOSwilldeterioratebecauseof itslowercurrentdrive.TheUFDG/Spice3-predictedloaded(CLoneach stage)ROdelaysplottedinFig.2.8versusCLconfirmthisanticipation. Hence,ingeneralapplications,DGCMOSshouldbesubstantivelyfaster thantheFD/SGcounterpart,especiallyforheavyloadsandlowsupply voltages.Nevertheless,itisinterestingtolearnthatforlightloadsand HP applications, suboptimal FD/SG can yield speeds comparable to DG.

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31 Figure 2.8UFDG/Spice3-predictedloaded(CLoneachstage)CMOS ring-oscillatordelaysversusCL,atVDD=1.2V,forthe28nm SDG and FD/SG device designs. -0.20.00.20.40.60.81.01.21.41.61.82.02.2 CL [fF] 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Delay/Stage [ps] SDG Suboptimal FD/SG Optimal FD/SGVDD=1.2V

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32 2.6 Thin-BOX FD/SOI CMOS FortheFD/SOISGdeviceswiththickBOX,ithasbeenreported thattheBOXfieldfringingandthecouplingbetweenthesource/drainand channelwilldegradetheSCEcontrol,andthususingthinBOX(<~40nm) fornanoscaleFD/SOIdevicesisbeneficialforimprovingSCEsandtheIon/ Ioffratio[Fen03].Also,itwasconfirmed[Num02]thatwhereasforlongLgdevicesSincreaseswithdecreasingtBOX,SforshorterLgisminimized fortBOX<50nm.However,thebenefitofthinningtBOXismuchreduced whentSiisultrathin[Tri03a]sincetheunderlyingfringing-fieldeffectin theBOXisreducedalongwiththeSCEsviatheUTB.Also,whentheBOX isthinned,theeffectivebodycapacitance[Lim85]andthesource/drain junctioncapacitance[Yeh95]willbeincreased,implyingthatthinBOX mayundermineFD/SOICMOSspeed.NotealsothattheincreasedCBodyimpliesaddedsensitivityoftheFD/SGdevicecharacteristics,e.g.,Vt[Lim85], to variations in tSi. Tosolidifyournotion[Tri03a]thatthinningtheBOXisnota judiciousdesignoption,weexamineitseffectsmorecloselyusingUFDG. WhentheBOXisthinneddownto20nminouroptimalFD/SGdevices, UFDGpredictsthattheintrinsicgatecapacitanceCGisincreasedabit, especiallyinthesubthresholdregion,whiletheaverage CGfromRO simulationstaysalmostconstantforVDD=1.2V.Theincreasecanbe explainedbytheincrementofCBodyin(2.2)withreducedtBOX(ortoxb). FortBOXthinneddownevenfurther,CGisestimatedtobecomparableto

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33 thatofthecorrespondinglyscaledbulk-SiMOSFET,whichisfiniteand substantiveforlowVGS[Fos02].However,thisestimationtendstobetoo highsinceUFDGdoesnotaccountforsubstrate,orback-gatedepletion under the (front) gate. InadditiontotheCGincrease,thinningtheBOXalsoincreases the(quasi-static)parasiticsource/draincapacitancestovaluesthatare comparabletoCGinthesubthresholdregion.Thisisbecausethesubstrate underthesource/draintendstobeinvertedinthenMOSFETand accumulatedinthepMOSFET,yieldingsource/draincapacitancesthat aredefinedmainlybytheCoxb.However,forhigh-speedtransientssuch astheROoscillations,theinversionchargeunderthesource/drainofthe nMOSFETcannotrespondtotheappliedtransientvoltage,thuscausing adeep-depletionconditioninthesubstrate.Therefore,theparasitic source/draincapacitancecanbeneglectedforthenMOSFET.The substrateaccumulationchargeinthepMOSFETcanrespond,however, andhencetheparasiticsource/draincapacitanceinitisdeterminedby Coxb,whichincreasesfordecreasingtBOX.Basedonthenotedincreasesin gateandsource/draincapacitances,wecanpredictthattheCMOSspeed willbesubstantiallydegradedwhentheBOXisaggressivelythinnedas suggestedin[Fen03].TheUFDG/Spice3-predictedROdelaysplottedin Fig.2.9versustBOXfortheoptimalFD/SGCMOSprovideclearevidence ofthespeeddegradation.Weincludeinthefigurepredicteddelays withoutaccountingforthearealsource/draincapacitance.Forthiscase,

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34 Figure 2.9UFDG/Spice3-predictedpropagationdelaysof9-stage unloadedCMOS-inverterringoscillatorscomprisingthe optimal28nmFD/SGdevicedesign,withtBOXthinneddown to15nm,atvariousvaluesofsupplyvoltage.Predicted delays for no areal source/drain capacitance are also shown. 10100 tBOX [nm] 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2Delay/Stage [ps] VDD=0.7V w/o areal CS/D VDD=0.9V w/o areal CS/D VDD=1.2V w/o areal CS/D VDD=0.7V VDD=0.9V VDD=1.2V

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35 weseethatthereisnegligibleeffectofvaryingtBOXontheROdelays.We thusconcludethattheeffectoftheincreasedparasiticsource/drain capacitanceinthepMOSFETispredominantindefiningthenotedspeed degradation caused by thinning the BOX. 2.7 Summary Usingourprocess/physics-basedcompactmodels(UFDGand UFPDB)inSpice3,wehaveprojecteddevicecharacteristicsandCMOS performancesofnonclassicalUTBCMOStechnologies(ADG,SDG,and twoversionsofFD/SOI,allofwhichwill,generally,requiremetalgates withtunedworkfunctionsforIoffcontrol)optimizedattheLg=28nmnode (whereLeff=Lgwasassumed),andcomparedthemwiththatofclassical, hypotheticalbulk-SiCMOSatthisnode.ComparisonsofpredictedSCEs ( D Vt, D V,andS)ofnonclassicaldevicesandspeeds(ROdelays)ofthe nonclassicalandclassicalCMOSweremade,andgoodphysicalinsights regardingtheirrelativecharacteristicsweregiven.WiththesameUTB thickness,theDGdeviceswereshowntobefarsuperiortotheFD/SG deviceswithregardtoSCEcontrol,andgenerallysuperiortoSGdevices, includingbulk-Sidevices,withregardtospeedbecauseofhigherdrive currents.However,aninterestinginsightwasnoted.Forlightloadsand moderatesupplyvoltages,asuboptimalFD/SGdesign(withthesametSi) forbothLOPandHPapplicationswasfoundtoyieldspeedscomparable totheDGdesigns,eventhoughitscurrentdrivesaremuchlowerandits SCEsaremuchmoresevere.Thissurprisingcomparisonwasshowntobe

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36 aresultoftheFD/SGdeviceshavingmuchlowerintrinsicgate capacitance,whichisduetotheirthickBOXandhighersubthreshold swing,andhencedeferredonsetofsignificantinversion-charge capacitance.AtlowerVDD,however,theDGdesignsaremuchfaster becauseoftheirmuchhigherdrivecurrents.WhentheFD/SGCMOS designwasoptimizedbyaggressivescalingoftheUTBthickness,itshighVDDspeeddiminished(butwasstillcomparabletothatofDGCMOS) becauseofhighergatecapacitanceatintermediategatevoltages,whileits low-VDDspeedimprovedduetoincreasedcurrent.Comparedtothe nonclassicalCMOS,thepredicteddelayofthebulk-Si/SGCMOSwas muchlongerduetoitshighgatecapacitanceintheweak/moderate inversionregion,inadditiontothearealsource/drainjunction capacitance,andrelativelylowdrivecurrentlimitedbypolysilicon-gate depletion.Finally,weusedUFDG/Spice3ROsimulationstoshowthatFD/ SOICMOSspeedisdegradedastheBOXisthinned,mainlybecauseof increasedsource/draincapacitanceinthepMOSFET,therebysuggesting thatsuchthinning,aimedatimprovedcontroloffieldfringingintheBOX, is not a good design tradeoff.

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37 CHAPTER 3 BULK INVERSION IN FINFETS AND IMPLIED INSIGHTS ON EFFECTIVE GATE WIDTH 3.1 Introduction Whilethedouble-gate(DG)FinFET(Fig.3.1(a))hasbecomea leadingdeviceoptionforfuturenanoscaleCMOS,thereisatechnological limittotheaspectratio(Rf)oftheSi-finheight(hSi)tothewidth(wSi). SincewSimustbeultra-thinforgoodcontrolofshort-channeleffects (SCEs)[Fos04b],thislimitimpliessmalleffectivegatewidth(commonly assumedtobeWeff@ 2hSi)and,ostensibly,lowon-statecurrent(Ion)per pitch.ThereisthereforeinterestinmakingtheFinFETatriple-gate(TG) transistorbyactivatingthetopgate(Fig.3.1(b)),yielding,fromasurface inversion-chargeperspective,Weff@ 2hSi+wSiasiscommonlyassumed, andalleviating,withadopedfin-body,thethin-wSirequirement[Doy03]. However,becauseoffin-cornereffects[Fos03b]andtechnological limitations[Tri03a],thefin-bodymustbeleftundoped,andsorelaxation ofthethin-wSi(i.e.,UTB)requirementforSCEcontrolfortheTGFinFET, relativetothatfortheDGdevice,isminimal[Fos04b].Nonetheless,the largerWefffortheTGdevicecouldmeansignificantlyhigherIonrelative to that of the DG FinFET even when wSi is thin for good SCE control. Inthischapter,weusethree-dimensional(3-D)numericaldevice simulationstoexaminetheincreaseinIon( D Ion)ofTGFinFETswith

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38 varyingRf=hSi/wSithatresultsfromactivationofthetopgate.Fromthe surfaceinversion-chargeperspective,weexpectarelativeincreaseinIonof D Weff/Weff(DG)@ wSi/(2hSi)=1/(2Rf).However,oursimulationresults contradictthisexpectation,andgiveinterestinginsightsconcerningfinbodybulkinversioninundopedFinFETs,evenintheon-condition,and implytheconsequentinappropriatenessofthecommonlydefinedWeffas anindicatorofIon.Basedonproper(re)definitionofeffectivegatewidth reflectingbulkinversion,wefurtherexaminethegatelayout-areaissue [Yan05] of FinFET CMOS. 3.2 Numerical Simulations WefirstuseDavinci[Dav03],a3-Dnumericaldevicesimulator, tosimulateDGandTGn-channelFinFETsasillustratedinFig.3.1.We assumeabruptsource/drainjunctions,andametallurgical,oreffective, channellength(Leff=Lgate)of25nm.Thegate-oxidethickness(tox=EOT) is1.2nmandtheburied-oxide(BOX)thicknessis200nm.FortheDG devices,thetop-gateoxidethicknessis50nm,whicheffectivelynegates thetopgateelectrode;itistoxfortheTGdevices.Basedon[Fos03b, Fos04b,Tri03a,Yan05],weassumeundopedSi-finbodieswithwSi=13nm ( @ Leff/2)andvariousvaluesofhSi.Forthreshold-voltage(Vt)control,a midgap metal gate is assumed. (Wenotethatthecarrier-transportmodelinginDavinciis deficientfornanoscaleFinFETssinceitisbasedmainlyonstudiesof single-gate(SG)bulkMOSFETs.Forexample,carriermobilityinUTB-fin

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39 Figure 3.1Two-dimensionalcross-sectionalviewof(a)theDGFinFET, specifyingxandzdirectionsinthefin-body,(b)theTG FinFET,showingthefin-bodydimensions,and(c)theDG FinFETwithoutthetopgatestack(thickoxideandmetal electrode). (a) (c)Buried SiO2Si Substrate Si SiO2Gate x z wSihSi(b)

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40 channelsdependsonwSiaswellasthetransverseelectricfield[Ess03, Tri04]asdoesthecarrier-energyquantization[Ge02],andDavincimisses thesewSidependences.Wehenceignorethequantizationandusethe standard,universalmobilitymodelinDavinci,butstressthattherelative results presented here are nonetheless meaningful.) 3.2.1 I-V Characteristics of DG and TG FinFETs Davinci-predictedcurrent-voltagecharacteristicsoftheDGand TGFinFETswithhSi=39nm(i.e.,Rf=3)areshowninFig.3.2.These characteristicsshowarelativeincreaseinIon(atVGS=VDS=1.0V)ofonly 5.4%intheTGdevice,muchlessthantheexpected16.7%(=1/(2Rf)).The insetofFig.3.2showssemi-logplotsofthecurrent-voltagecurves, revealingthesubthresholdcharacteristicsofthetwodevices.TheTGFinFETVtisonly~10mVhigherthanthatoftheDGFinFET (correspondingto~15%-lowerIoff).Thesmalldifferencebetweenthe subthresholdcharacteristicsdoesnotexplainthenoteddiscrepancyinthe relative D Ion.Suchasignificantdiscrepancyisalsopredictedforother valuesofRf,rangingfromabout1to5(non-integersbecauseoffinitemesh spacingforthenumericalsimulations),asillustratedinFig.3.3.Notefor Rf@ 1,theDavinci-predictedrelativeincreaseinIonduetothetopgateis only14.0%,asopposedtotheexpected54.2%.Thatis,IonoftheDG FinFETforthisextremecaseisalmost90%ofthatintheTGcounterpart, whichisconsistentwithnumericalresultsofBurenkovetal.[Bur02].Our

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41 Figure 3.2Davinci-predictedcurrent-voltagecharacteristicsofundoped n-channelDGFinFETs,withandwithoutthetopgatestack, andoftheTGcounterpart,allwithhSi=39nm,wSi=13nm, tox=1.2nm,tBOX=200nm,Leff=25nm,andmidgapmetal gate.Thesemi-logreplotsofthethreecurvesintheinset showthesubthresholdcharacteristics,andsmallvariations in Ioff and Vt among the three devices. 0.20.30.40.50.60.70.80.91.0VGS[V] 0 10 20 30 40 50 60IDS [ m A] DG FinFET DG FinFET w/o top gate stack TG FinFETVDS= 1.0V 0.00.10.20.30.40.5VGS [V] 10-1010-910-810-710-610-5IDS [A]

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42 Figure 3.3Davinci-predictedon-state(VGS=VDS=1.0V)current increase( D Ion)duetothetopgateoftheTGnFinFET, relativetotheDGnFinFETcurrent(Ion(DG)),versusthefin aspectratio;Leff=25nmandwSi=13nm.Alsoplottedisthe Weff-basedexpectationfortherelativecurrentincrease, defined by wSi/(2hSi) = 1/(2Rf). 0.51.01.52.02.53.03.54.04.55.05.5Rf 0 20 40 60 80 100D Ion/Ion(DG)[%] Expected (1/(2Rf)) Predicted

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43 resultshereclearlyshowthatthecommonlydefinedWeffisnotavalid indicator of relative values of Ion in TG and DG FinFETs. 3.2.2 Electric-Field Fringing Effects Apossibleexplanationforthesesurprisingresultsisthat electric-fieldfringingfromthesidewallgatesabovethefinintheDG FinFET(seeFig.3.1(a))inducessignificantinversionchargeinthetopfin surface.Indeed,exploitationofsuchfieldfringinghasbeenproposedto effectabottomgateextension[Par02].Tocheckthisexplanation,we simulatedtheDGFinFETwithitstopgatestack(thickoxideandmetal electrode)removedasillustratedinFig.3.1(c).Thepredictedcurrentvoltagecharacteristic,forRf=3,isincludedinFig.3.2.Weseethatthe field-fringingeffectisnegligiblysmallanddoesnotexplaintherelatively smallincreaseinIonofTGFinFETs;IonofthecompleteDGFinFET(Fig. 3.1(a))isonly1.5%higherthanthatofthesamedevicewithoutthetop gate stack. 3.2.3 Bulk Inversion Insightintotheactualexplanationfortheinterestingresultsin Figs.3.2and3.3isprovidedbytheDavinci-predictedelectrondensities (n)inthethreedevicesofFig.3.2(Rf=3).Basedonthex-zcoordinate systemshowninFig.3.1(a),n(x,z)atVGS=VDS=1.0V,takenfromthe centerofthechannel(y=Leff/2),isshowninFigs.3.4and3.5.(Theseare classicalsolutions;theeffectsofquantizationarenotedlater.Notethat ouruseofthepredictedcarrierdensitiestogiveinsightonthepredicted

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44 Figure 3.4Davinci-predictedon-stateelectrondensityalongthetopfin surface,atthecenterofthechannel(y=Leff/2),intheDG and TG nFinFETs of Fig. 3.2. 024681012z [nm] 101810191020n(x=0) [cm-3] DG FinFET DG FinFET w/o top gate stack TG FinFETVGS = VDS = 1.0V

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45 Figure 3.5Davinci-predictedon-stateelectrondensitydownthemiddle ofthefin,atthecenterofthechannel(y=Leff/2),intheDG and TG nFinFETs of Fig. 3.2. 05101520253035x [nm] 10181019n(z=6.5nm) [cm-3] DG FinFET DG FinFET w/o top gate stack TG FinFETVGS= VDS= 1.0V

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46 currentsintheDGandTGdevicesfurtherjustifiesourlackofconcern aboutthedeficienciesofthecarrier-transportmodelinginDavinci.)In Fig.3.4,thevariationofnacrossthetopsurface(n(x=0,z))intheDG FinFETwithoutthetopgatestackshowssubstantiveinversioncharge awayfromthesidewalls,i.e.,volume,or bulkinversion .Thepredicted n(x=0,z)ofthecompleteDGFinFETshowsamoderateincreaseduetothe notedfieldfringing.(Thetopmetalelectrodedoesnothing,aswe confirmedviasimulation.)Thefulleffectofthefieldfringingisreflected inFig.3.5wherethepredictedelectrondensitydownthemiddleofthefin (n(x,z=6.5nm))isshown.TheintegratedinversionchargeinbothDG FinFETstructures,however,reflectsthesmall1.5%benefitofthefield fringingtoIon.FortheTGFinFETinFigs.3.4and3.5,weseehigher electrondensitynearthetopfinsurfaceduetothethirdtopgate.But,as discussedwithreferencetoFigs.3.2and3.3,thatbenefitintheTGdevice is much less than that implied by the increased Weff. AsindicatedinFigs.3.4and3.5then,weinferthattheresults inFig.3.3,i.e.,lowerthanexpectedIoninTGFinFETsrelativetothatin theDGcounterparts,areduetothestrongbulkinversionthatoccursin theon-statecondition.Notethehighn(>2 1018cm-3)throughoutthefin bulk,awayfromthesurfaces,inallthreedevicestructures.ThebulkinversionchargeintheDGFinFETcontributessignificantlytoIon, perhapsdueinparttothefactthattheelectronmobilityinthefinbulk

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47 ( mb)canbehigherthanthatatthesurfaces( ms)[Ess03,Tri04]andhence the activation of the top gate is not very beneficial. Togivemorequantitativeexplanation,weexpresstheDG FinFETon-statecurrent,separatingoutsurface(Qis)andbulk(Qib) components of inversion-charge density: (3.1) wherevsandvbrepresenttheaveragecarriervelocitiesatthefinsurfaces andinthefinbulk,respectively.Notethatthevelocitiesdependon,in additionto msand mb,VDSwhichcontrolstheelectricfieldEy(x)and governsvelocitysaturation/overshootalongthechannel.Actually,(3.1)is areasonableexpressionifRfisgreaterthanone,whichmakesthe effectivewidthofthefin-bulkcomponentapproximatelyhSi.FortheRf= 3DGFinFETofFigs.3.4and3.5(withwSi=13nm),wefindsurprisingly largeQib>QisatVDS=VGS=1.0V,which,via(3.1),definesapredominant enhancement of Ion(DG)over that implied by Weff: .(3.2) Wenotethatvbandvsarecomparablebecauseofthetendencyforvelocity saturationalongmostoftheshortchannel.However,wecouldgeta mb> msbenefitwithvelocityovershoot,andhencemorecontributionofbulk inversion to Ion(DG)via (3.2). WiththesubstantivebulkinversionchargeintheDGFinFET definingIon(DG)asin(3.2),activationofthetopgate,renderingtheTG I onDG () W eff Q is v s h Si Q ib v b + @ I onDG () W eff Q is v s 1 Q ib v b 2 Q is v s ----------------+ @

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48 counterpart,resultsinonlyarelativelysmallincreaseinthetotal inversioncharge,atthetopsurfaceasshowninFig.3.5,andinIonas reflectedbyFigs.3.2and3.3.Weconfirmthenthat,indeed,the discrepanciesinFig.3.3betweentheactualandexpectedIonoftheTG FinFETrelativetotheDGFinFETaremainlyareflectionofthe significanceofthebulk-inversioncomponentofcurrentin(3.1)and(3.2). Infact,thisbulkcurrentisthepredominantcomponentofIon(DG)inallthe DGFinFETswesimulated.Itspredominancevariessomebecausethe notedfield-fringing(relative)benefittoIon(DG)increaseswithdiminishing Rf. Additionalsimulationsrevealthatthesignificantbulkinversion islinkedtotheundoped,thinbody.Becauseofnosignificantdepletion charge,theelectricpotentialandcarrierdensityinthesubthreshold regionareuniformthroughoutthethinbody[Tri03a],asexemplifiedby the2-DMedici[Med01]simulationresultsforarbitraryundopedDGand TG[Fos03b]FinFETsinFig.3.6.(Virtuallythesameuniformityobtains fortheSGfullydepleted(FD)SOIMOSFETwithundopedbodyandthick BOX[Tri03a].)Thismeansthattheoff-statecurrentinthesedevicesis proportionaltothecross-sectionalareaofthebody/channel:Ioff hSiwSi. Asthegatevoltage(VGS)isincreasedthen,thisuniformitytendstobe maintained,resultinginsignificantbulkinversionforstrong-inversion conditions.Thelevelofthebulkinversion,e.g.,n(x,z=wSi/2)whichimplies

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49 Figure 3.6Medici-predictedelectrondensity,versusgatevoltage, acrossthefin-body(vs.normalizedz/wSi)oflong-channelDG (wSi=20nm)andTG(atx=0forwSi=hSi=30nm) nFinFETs, both with midgap gate; VDS = 0V. 0.00.20.40.60.81.0z/wSi 10101011101210131014101510161017101810191020n [cm-3] VGS= 0V 0.1V 0.6V TG FinFET DG FinFET

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50 Qib/Qisin(3.2),isgovernedbytheelectronscreeningofthesurfaceelectric field, via Poissons equation without ionized dopant charge: ,(3.3) whichischaracterizedbytheDebyelengthLD 1/.Ittendstodiminish withincreasingwSi,butultimatelysaturates(at~2x1018cm-3),asshown inFig.3.7,becauseLDincreasesasndecreases.However,itshouldbe notedthatforverythickwSi,SCEsmightcontributetoformingthehigh n(x,z=wSi/2). 3.3 Implied Insight of Bulk Inversion 3.3.1 Proper Effective Gate Width BecauseofthenotedbulkinversionintheundopedDGFinFET, intheoff-aswellastheon-states,theeffectivewidthofthetwosidefin surfaces,2hSi,doesnotproperlyreflectalltheinversionchargeand current. The effective gate width should be defined simply as ,(3.4) with(3.2)modifiedaccordingly.(Notethattheeffectivegatewidthofthe planarSGFD/SOIMOSFET,withbulkinversion,isstilltheactualgate width(Wg),whichconveystheQibaswellastheQiscontributionsto current.)Thegatecapacitanceisalsoproperlydefinedby(3.4),i.e.,bythe areaLeffhSi,asevidentintheDGchargecharacterizationsin[Kim01]for asymmetrical-aswellassymmetrical-gatedevices.However,aproper dE dz -----qn e Si ------- @ n W effDG () h Si =

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51 Figure 3.7Davinci-predictedon-stateelectrondensityatthemiddleof thetopfin-bodysurface,atthecenterofthechannel(y=Leff/ 2),oftheDGFinFETwithoutthetopgatestackofFig.3.2, versus the fin width. 791113151719212325wSi [nm] 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2n (x=0, z=6.5nm) [ 1018cm-3] VGS= VDS= 1.0VDG FinFET w/o top gate stack

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52 effectivegatewidthfortheTGFinFETcannotbesodirectlydefined,as evidenced in Fig. 3.3. 3.3.2 Layout Area Wehavepreviouslyshown[Yan05],basedonthecommonly definedWeff=2hSi+wSi,thegatelayout-areainefficiencyofTGCMOS relativetoDGandFD/SOICMOSwhentheundopedTGfin-body dimensionsaremadecomparabletothegatelength(Lg)toeasethe fabrication[Doy03].ThebulkinversionnotedhereclearlyworsensthisTG inefficiency.FormoreviableTGCMOS,withtallerandthinnerfins(and widerWeff)asinSec.3.2,wefurtherexaminethelayout-areaefficiency, nowaccountingforbulkinversion,asfollows.ForagivenLgandcurrent drive,correspondingtothegateareaASG=LgWgforaplanarSGMOSFET (e.g.,anFD/SOIMOSFET),thearearequirementforthe(multi-fin)DG FinFETisADG=Lg[WgP/(hSifDG)],wherePisthepitchand,with referenceto(3.4),fDGisthecurrent-enhancementfactoraffordedbyDG relativetoSGwhenhSi=Wg.Typically,fDG>2[Fos02],butwewill assumefDG=2here,whichistantamounttolettingWeff=2hSifortheDG device.ThenfortheTGFinFET,wecanexpressATG=Lg[WgP/Weff(TG)], where, phenomenologically, we define ;(3.5) becauseofthebulkinversion,wSi(eff)
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53 .(3.6) ForRf=3,(3.6)andFig.3.3yieldwSi(eff)=4.2nm,muchlessthanthe actual wSi = 13nm. TherequiredgatelayoutareasfortheTGandDGFinFETswith Rf=3,relativetoASG,areplottedinFig.3.8versusLg;LgandPwere obtainedfromthe2003SIAITRS[Sem03]projectionsfortheHP(highperformance)andLSTP(low-standbypower)CMOSapplications,andwSiwassettoLg/2(=Leff/2)forSCEcontrol.Forcomparison,weincludeATG/ ASGthatresultswhenwSi(eff)=wSiisassumed,i.e.,whenbulkinversion isignoredasin[Yan05].WiththisassumptiontheneededTGareais underestimatedbyabout10%generallyforbothapplications.Theactual layout-arearatios,withbulkinversion,showonlyaminimalbenefitofthe thirdgaterelativetoDG-FinFETCMOS.FortheDGtechnologyrelative totheplanarSGCMOS,theresultsinFig.3.8areoverlypessimistic, showing,forexample,>60%moreareaneededforDGFinFETsintheHP application.Indeed,withfDG>2,whichislikely[Fos02],andRf>3,which isdoable,DG-FinFETCMOScanyieldsignificantlybetterlayout-area efficiencythantheSGtechnology[Yan05].Forexample,Rf 5alone renders DG more area-efficient than SG. Thesignificanceofbulkinversionimpliesmuchaboutnanoscale FinFETcharacteristicsanddesign.First,thecommonlydefinedWeffisnot avalidindicatorofrelativevaluesofcurrent(andcapacitance)inDGand w Sieff () 2 = h Si D I on I onDG () ----------------------

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54 Figure 3.8Calculatedgatelayout-arearatiosofTGandDGFinFETs withRf=hSi/wSi=3,relativetotheplanarSGMOSFET, versusgatelength;Lg(=Leff)andpitchforthecalculations wereobtainedfromthe2003ITRS[Sem03]projectionsfor HPandLSTPCMOStechnologies.Thepessimisticarea requirementsfortheDGFinFETresultedfromthe assumptions of low Rf and fDG (=2). 01020304050607080Lg [nm] 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2A/ASG DG FinFET TG FinFET TG FinFET (w/o bulk inversion) HP LSTP

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55 TGFinFETs;indeed,theadditionalIon,andinfactIoff,producedbythe topgateoftheTGdevicearesubstantivelysmallerthanwhatisimplied byWeff.Second,thetopgateisreallynotneededformoderateRf,whichis necessaryforgoodlayoutefficiency.Third,thegatelayout-areaadvantage oftheTGFinFETovertheDGcounterpartimpliedbyWeffisactually muchsmallerduetobulkinversion,andtheDGareaadvantageoverthe simpleTGdevicewithhSi~wSi~Lg,notedpreviouslyfromtheWeffperspective[Yan05],isenhanced.Fourth,althoughwedidnotconsider quantizationeffectsinthisstudy,wesurmisethattheywillactually enhancethebulk-inversioneffectsbecauseofthedeeperinversion-charge centroid in the quantum-mechanical solution [Ge02]. 3.4 Summary Three-dimensionalnumericalsimulationsofDGandTG FinFETshavingundopedthinbodieshaverevealedthesignificanceof bulk-inversioncurrentinIon,aswellasIoff,andtheconsequent insignificanceofthecommonlydefinedeffectivegatewidthin comparisonsofDGandTGcurrents.Infact,wehaveinferredthatthe properWeffforDGFinFETsishSi,whichcorrelateswiththetotal(surface plusbulk)inversioncharge;whereasameaningfulWeffcannotbedirectly definedforTGFinFETs.Thenewinsightsrevealedhereinexplainwhy theDGFinFETprovidesnearlythesameIonastheTGcounterpartforfin aspectratiosassmallastwo,butespeciallyforhigherRfwhichis desirableanddoable.DuetotherelativelysmallincreaseinIonofTG

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56 FinFETs,overtheDGcounterpartswithmoderateRf,theadvantageofTG devicesingatelayout-areaefficiencyisnotsignificant.Theinsightsthus furthersolidifyournotion,basedinitiallyonWeff-impliedTGlayout-area inefficiency[Yan05](andonthefactthataTGFinFET,withathintop dielectricandmoderateRf,ismoredifficulttofabricatethanaDGFinFET [Mat05]), that the third top gate is neither desirable nor beneficial.

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57 CHAPTER 4 MODELING AND SIGNIFICANCE OF FRINGE CAPACITANCE IN NONCLASSICAL CMOS DEVICES WITH GATE-SOURCE/DRAIN UNDERLAP 4.1 Introduction NonclassicalnanoscalesiliconCMOSdevices,e.g.,double-gate (DG)andsingle-gate(SG)fullydepleted(FD)SOIMOSFETswith undopedultra-thinbodies(UTBs),shouldbedesignedwithgate-source/ drain(G-S/D)underlap[Tri05a].Thebenefitsoftheunderlapinclude bettercontrolofshort-channeleffects(SCEs)viaagatebias-dependent effectivechannellength(Leff)[Fos03c,Tri05a],aswellaseliminationof gate-induceddrainleakage(GIDL)[Tan05]andgate-drain/source tunnelingcurrents.Theunderlap,however,mustbeoptimallydesigned becauseittendstoincreasetheS/Dseriesresistance(RSD)anddecrease Ion[She03,Tan05].Weshowinthischapter,bydeviceandcircuit modelingandsimulation,thattheimpliedunderlapdesigntradeofffor ultimateCMOSspeedisaffectedsignificantlybyparasiticG-S/D capacitance, i.e., fringe capacitance, in nanoscale devices. FringecapacitanceinclassicalMOSFETs,withG-S/Doverlap, wasmodeledsometimeago[Shr82],andsomemodelingwasrecently reported[Ban05]forDGMOSFETswithunderlap.However,themodeling ofBansaletal.[Ban05]focusedonabias-independentouter-fringe

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58 capacitance,anddidnotaddresstheVGSdependenceofitaswellasthe inner-fringecomponent,whichisquiteimportantinnanoscaledevices. Herein,usingphysicalinsightsderivedfromnumericaldevice simulations,wedevelopacompleteanalyticalmodelforparasitic capacitanceinnonclassicaldeviceswithG-S/Dunderlap,whichincludes boththeouter-andinner-fringecomponentswithVGSdependences,as wellasaBOX-fringecomponentintheFD/SOIMOSFET.Thenew modelingisverifiedby2-Dnumericaldevicesimulations.Further,the modelisimplementedinourprocess/physics-basedcompactmodelUFDG (Ver.3.5)[Fos06a],andusedinSpice3simulationstocheckthebenefitof G-S/DunderlapinreducingthefringecapacitanceandDGCMOS propagationdelay.Basedonphysicalinsightsattained,optimizationof theunderlapdesigntoeffectthebesttradeoffbetweenthecapacitance andRSDforCMOSspeedisexemplifiedattheLg=18nmtechnologynode of the SIA ITRS [Sem03]. 4.2 Physical Insights from Numerical Simulations 4.2.1 Inner and Outer Fringe Capacitance ThedependencesoftheparasiticcapacitanceonVGSandonthe G-S/DunderlaparereflectedinFig.4.1,whichshowslow-frequency,lowVDStotalgatecapacitance(CG)versusVGSpredictedbythe2-Ddevice simulatorMEDICI[Med04]foranLg=18nmundoped-UTBDGnMOSFET withandwithoutunderlap,andwithandwithoutafinitegateheight(tg). BecauseofthefloatingUTBandthenegligiblysmalljunctioncapacitance,

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59 Figure 4.1MEDICI-predictedlow-frequencygatecapacitanceversus gatevoltageforanLg=18nmDGnMOSFETwith(graded NSD(y)in20nmS/Dextensionwith11nmstraggle[Tri05a]) andwithout(abruptNSD(y))G-S/Dunderlap,andwithand withoutfinitegatethickness;undopedUTBswithtSi=14nm, tox=0.7nm, midgap gate. -0.20.00.20.40.60.8 VGS [V] 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0CG [fF/ m m] Underlap w/ tg=18nm Underlap w/ tg=0 Abrupt NSD(y) w/ tg=18nm Abrupt NSD(y) w/ tg=0 VDS = 50mV 1.0

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60 whichisinserieswiththeintrinsicgate-to-bodycapacitance,the subthresholdCGisdefinedexclusivelybytheextrinsicparasiticG-S/D capacitance,whichincludesbothinner-(Cif)andouter-fringe(Cof) components[Ban05].ThesameisessentiallytrueforSGFD/SOI MOSFETswiththickBOX[Kim05a].Forthetg=0simulationsofFig.4.1, Cofwasforcedtozerobyremovalofthespacerdielectricaswellasthegate stackfromthedevicedomain.NotefirsttheninFig.4.1howsignificant CifandCofare,relativetotheon-stateCG.(Forthesimulationswe assumedsilicon-dioxidespacers.Whentheyaresilicon-nitride,whichhas abouta1.8x-higherpermittivity,Cofisevenmoresignificantthanimplied inFig.4.1.)Forthetg=0cases,inwhichCof=0,notehowtheG-S/D underlapsignificantlyreducesthesubthresholdCG,i.e.,Cif,butmakesno differenceinstronginversion(atlowVDS).Thisreflectsthescreeningof theinnerG-S/Dfringingelectricfieldbyinversioncharge,whichforcesCif(andtheBOX-fringecapacitance,aswediscusslater)tozerowith increasingVGS.(AthighVDS,thereducedinversionchargenearthedrain couldunderminethisscreeningeffect,butfornanoscaledevices,the carriervelocitysaturationtendstokeeptheinversionchargehighenough tomakethisunderminingnegligible.)Then,withfinitetg,CGisincreased, withandwithoutunderlap,forallVGSbyCof.However,notethatCofis smallerinthedevicewithunderlapinthesubthresholdregion,butnotin stronginversion.ThisreflectstheshrinkingLeffwithincreasingVGSdue

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61 tothedecreasingDebyelengthdefinedbythestrong-inversioncharge:Leff Lg as VGS increases [Fos03c]. 4.2.2 BOX Fringe Capacitance in FD/SOI MOSFETs MoreinsightisgainedfromtheMEDICI-predictedsubthreshold (VGS=0)CGversusundoped-UTBthickness(tSi)inFig.4.2forFD/SOI nMOSFETs.Fortheassumedtg=0(Cof=0),theincreasingCGwithtSireflectsthedependenceofCifontSi.However,noteforallcases(different Lg,withandwithoutunderlap)thatCGfortSi 0remainsfinite,even thoughCifmustapproachzero.Analogoustotheshort-channeleffectofS/ DfieldfringingintheBOX[Tri03a],whichcaninducealeakagepathnear thebacksurface,weinferthatthefiniteCGattSi=0inFig.4.2is associatedwiththeBOX-fringecapacitance(Cbf).Notethatforincreasing VGS, Cbf, like Cif, will approach zero due to inversion-charge screening. BasedonthephysicalinsightsgainedfromFigs.4.1and4.2,we concludethattherearethreebasiccomponentsofparasiticfringe capacitanceinnonclassicaldeviceswithG-S/Dunderlap:Cof,Cif,andCbfasrepresentedinFig.4.3,allofwhichdependonVGS.Actually,Cbfas showninthefigureforSGFD/SOIMOSFETsisanapproximationforthe G-S/DcapacitancesupportedbythefringingfieldintheBOX.More exactly,thiscapacitance(perunitwidthW)isaseriescombinationofCbf(ascharacterizedinthenextsection),Cox=( eox/tox)Lg/2,andCb=( eSi/ tSi)Lg/2[Kim05a].However,fortypicalthintoxandtSi,Cbf<
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62 Figure 4.2MEDICI-predictedlow-frequencysubthresholdgatecapacitance versusundopedUTBthicknessforSGFD/SOInMOSFETswith twodifferentshortgatelengthsandassumedatgate(tg=0, whichmeansnoouter-fringecapacitance),withandwithoutG-S/ D underlap; tBOX = 200nm, midgap gate. Abrupt NSD(y), Lg=13nm & tox=0.7nm Underlap, Lg=13nm & tox=0.7nm Abrupt NSD(y), Lg=25nm & tox=1nm Underlap, Lg=25nm & tox=1nm 0123456 tSi [nm] 0.00 0.05 0.10 0.15 0.20 0.25 0.30CG [fF/ m m] VDS = 50mV VGS = 0V

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63 Figure 4.3Aschematicdiagramofthegate-source/drainstructureofa nonclassical(DGorSGFD/SOI)MOSFET,indicatingtheG-S/D underlap(witheffectivelengthLeSD)andthethreecomponents oftheparasiticfringecapacitance;CbfisuniquetotheFD/SOI device with thick BOX. tSitoxtgGateSource/DrainSi UTB LeSD CbfCofCifSpacer Dielectric(for FD/SOI with thick BOX)BOX

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64 thatCofisdefinedpredominantlybythegatesidewalls;thefringe capacitancefromthetopofthegateisnegligiblefortypical(high)tg.In stronginversion,CifandCbfareeffectivelyscreenedout,andCof(withLeff@ Lg)isthemainparasitic.AsLgisscaled,theparasiticcapacitance becomes more significant, and hence modeling it is crucial. 4.3 Analytical Modeling TomodeltheparasiticfringecapacitanceforSOI-based nanoscaleMOSFETswithG-S/Dunderlap,includingDGandSGFD/SOI devices,weextendthemodelingin[Shr82]basedontheinsightsgained inSec.4.2.Thebasicfringe-capacitancemodelstemsfromthatdefinedby twoseparated,conductingplatesatanangleqasshowninFig.4.4.A solutionofLaplacesequationincylindricalcoordinatesfortheelectric potentialwhenavoltageVisappliedasshownyields,viaGaussslaw,the charge(Q=CV)ontheplatesandthecapacitance(perunitwidth)it defines [Zah79]: (4.1) where e isthepermittivityoftheinsulatorbetweentwoplates,andr1,r2, and q arethegeometricalparametersdefinedinFig.4.4.Thefringing fieldfromtheendsoftheplatesisignored,assumingtheplatesarein closeproximity[Zah79].Touse(4.1)forthefringe-capacitance componentsinFig.4.3,thebasicG-S/Dstructureistransformedtothose ofFig.4.5,dependingontheunderlap,orinversioncondition:Fig.4.5(a) C e q -r2r1---ln =

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65 Figure 4.4Basictwo-platemodelforfringecapacitance(perunitwidthinz), withthecylindricalcoordinates(rand f )usedintheanalysis shown. f 0r1r2r 0 q+ + + + + + + + + + + + + + + + +_ _ _ _ _ _ _ _ _ + _V

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66 Figure 4.5Schematicsof(a)theG-S/Dunderlapstructurefortheweakinversionanalysis,withthereducedanglebdefinedafter replacingthehigher-permittivitysiliconwithoxide[Shr82], and(b)theabruptG-S/Dstructurewithnounderlapforthe strong-inversion analysis. tg tox tSiSource/Drain Gate Oxide Si Oxide b LeSD b ao o ac f g de tg toxSource/Drain Gate Oxide a b ao c(b)(a) Si UTB

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67 approximatestheunderlapstructureinweakinversion,witheffective LeSD,whereLeff@ Lg+2LeSD[Fos03c,Tri05a]);andFig.4.5(b)showsthe effectiveabruptG-S/Dstructurewithoutunderlapinstronginversion, withLeSD=0,whereLeff@ Lg[Fos03c,Tri05a].(Weareneglectingthe accumulationcondition.)AsillustratedinFig.4.6anddescribedin [Tri05a],LeSDisaneffectiveunderlapwithanabruptsource/drain-body junctionasdefinedbytheactualgradedlateraldopingprofileNSD(y)with finitestraggle( sL)intheS/Dextension;LeSDdependson sL,theextension length(Lext),andtSi.InFig.4.5(a),aswasdonein[Shr82],theplate-plate anglehasbeenreducedfrom p /2to b toeffectivelyaccountforthesilicon permittivity( eSi)beingaboutthree-timesthatoftheoxide( eox),whichwill be assumed in the use of (4.1): .(4.2) Further,weassumethatthespacerdielectricissilicon-dioxide.For silicon-nitridespacers, eoxinourresultsforCof(in(4.3)and(4.6))should be replaced by the permittivity of the nitride. ForUFDG,theVGSdependenceofthefringecapacitance(Cf)is accountedforbymodelingthevariouscomponentsinweakandstrong inversion,definingthecorrespondingchargecomponents(i.e.,CfVGS/D) andassigningthemtotheproperterminalsofthedevice,andthenlinking themodelsacrossthemoderate-inversionregiondefinedbycontour boundariesinVGfS-VGbSspace[Fos06b].Thelinksare(-D)cubicb pe ox 2 e Si -----------p 6 -@ =

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68 Figure 4.6Illustrationofhowvaryingtheactuallateraldopingdensity profileNSD(y)intheS/Dextensionchangestheweakinversioneffectivechannellength,ascharacterizedbythe effectiveG-S/DunderlapLeSDindicated,whichisdefinedby sL, Lext, and tSi as described in [Tri05a]. 2535455565758595y [nm] 101510161017101810191020NSD [cm-3] LgateLextLexty LeSD Leff(weak)NSD(y) LeSDsL Abrupt NSD(y) LeSD w/ LeSD=0Abrupt NSD(y)w/ effective LeSD 0

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69 polynomialsplinefunctionsofthetwogatevoltagesfortheterminal charges.TheUFDGaccountingfortheVGS-dependentLeff[Fos03c, Fos06b, Tri05a] is similarly facilitated by such regional modeling. 4.3.1 Weak Inversion Intheweak-inversionregion,theouter-fringecapacitance(Cofw) canbemodeledwith(4.1)bydefining,fromFig.4.5(a),r1= of= oc=LeSD, r2= ob+ bg=tox+tg,and q = a = p /2.Fortheinner-fringecapacitance(Cif)with (4.1),r1= o c+ cd= o a+ ab=tox/tan b +LeSD,r2= o c+ ce=tox/sin b +tSi,and q = b in (4.2). Thus, (4.3) and .(4.4) Notein(4.4)that,becauseofuncertaintyinLeSD(usedhereforCif,as opposedtothatusedtodefineLeff[Tri05a])duetothegradedNSD(y)in realdevices,weemploythetuningparameterfifbyreplacingLeSDby fifLeSD,whichcanbethoughtofasaneffectiveunderlaplengthforCif. Fromnumericalsimulations,wefindthatfifispositive,andgenerally comparabletobutlessthanunity.Tokeepthemodelsimple,yetrealistic, wehaveassumedLeSD toxtoget(4.3),andthentoget(4.4)thatLeSDis lessthanorequaltotox(1-cos b )/sin b +tSi@ 0.27tox+tSi,sinceotherwise de inFig.4.5(a)isnonexistent(i.e., o a+ ab> o c+ ce)andCifisundefinable C ofw 2 e ox p -----------t g t ox + L eSD -----------------ln = C if 6 e ox p -----------t ox t Si b sin + t ox b cos f if L eSD b sin + -------------------------------------------------------------ln =

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70 via(4.1).Theseassumptionsdonotlimitthemodelutilitysincetypically LeSD>toxandLeSD~4nm,whichis generallytoolongduetohighRSD[Fos03c]),theeffectfromtheregion bf isnottotallynegligible,andthusthemodeltendstounderestimateCofwa bit. ForDGdevices,thetotalparasiticG-S/Dcapacitanceinthe weak-inversionregionisapproximatedbyparallelcombinationof(4.3) and(4.4),appliedforbothgatescoupledtoboththesourceandthedrain. ForSGFD/SOIdevices,thereisonlythefrontgate,buttheBOX-fringe capacitancemustbeaccountedfor.FollowingourdiscussioninSec.4.2, stillusing(4.1),wecanmodelCbfinFig.4.3asindicatedinFig.4.7, wherethetwoplatescanbedefinedby aband cd.Thus,bydefining r1= bo= oc=LeSD/2, r2= ab+ bo= oc+ cd=LeSD/2+Lg/2, and q = g = p we get .(4.5) Forweakinversion,aswenotedpreviously,wecanassumethat(4.5) couplesthesource/drainandgatedirectly,ignoringanytSidependence, sinceaseriescombinationofCbf,Cox,andCbcanbesimplycharacterized asCbfduetoCbf<
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71 Figure 4.7SchematicoftheSGFD/SOIMOSFETwithG-S/Dunderlap, showing how the BOX-fringe capacitance is modeled. tox LeSD o Lg/2g BOX tSi Si UTBcd abSource/Drain Gate Oxide

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72 regionisapproximatedbytheparallelcombinationof(4.3),(4.4),and (4.5), applied to both the source and the drain. 4.3.2. Strong Inversion AsexplainedinSec.4.2,theouter-fringecapacitanceinthe strong-inversionregion(Cofs)shouldalwaysbedefinedbyaneffective abruptgate-source/drainstructurewithLeSD=0asshowninFig.4.5(b). ThismeansthatCofscanbeexpressed,asin[Shr82],with(4.1)bydefining r1= oa= ob=tox and r2= ob+ bc=tox+tgwith q = a = p /2. Thus, .(4.6) Noteherethatthefringing-fieldeffectsduetoregion oainFig.4.5(b), whichwasaccountedforin[Shr82]quasi-empirically,isnotsignificant becausetoxisultra-thininnanoscaleMOSFETsandtheinversioncharge tends to obviate any accumulation charge in the oa region. So,forstronginversion,whereCifandCbfarenegatedby inversion-chargescreening,theparasiticcapacitance,forbothDGandSG FD/SOIMOSFETs,isgivenby(4.6),appliedtothegate(s)coupledtoboth the source and the drain. 4.4 Model Verification Formodelverification,anLg=25nmundoped-UTBSGFD/SOI nMOSFETwithmidgapgate,andtox=1nm,tSi=6nm,tg=20nm,andtBOX=200nm,alongwiththeG-S/DunderlapdefinedbyNSD(y)ina30nmS/D extensionwitha15nmstraggle(whichyieldsLeSD=3.4nmforLeffin C ofs 2 e ox p -----------1 t g t ox ------+ ln =

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73 UFDG[Tri05a])isconsideredfirst.Forthisdeviceintheweak-inversion region(atVGS=0V),MEDICIpredictsforthetotalS/D(i.e.,SorD)fringe capacitance,Cf=Cofw+Cif+Cbf=0.111fF/ m m,whereCofw=0.039fF/ m m,Cif=0.047fF/ m m,andCbf=0.025fF/ m m.Inthestrong-inversionregion,Cf= Cofs=0.065fF/ m mispredicted.Forthesamedevice,ouranalyticalmodel predicts,inweakinversion,Cf=0.110fF/ m m,whichisthesumofCofw= 0.04fF/ m m,Cif=0.047fF/ m mwithfif=0.64in(4.4),andCbf=0.023fF/ m m, whileCofs=0.067fF/ m minstronginversion.Themodelpredictionsare very good. ForanLg=18nmundoped-UTBDGnMOSFETwithmidgap gate,andtox=0.7nm,tSi=14nm,andtg=18nm,alongwiththeG-S/D underlapdefinedbyNSD(y)ina20nmS/Dextensionwithan11nm straggle(LeSD=4.0nmforLeffinUFDG[Tri05a]),wegetCf=0.125fF/ m m intheweak-inversionregion(atVGS=0V)fromMEDICI,comprisingCofw=0.046fF/ m mandCif=0.079fF/ m m,whileourmodelpredictsCf=0.113fF/ m m,withCofw=0.034fF/ m mandCif=0.079fF/ m mwithfif=0.85.Inthe strong-inversionregion,MEDICIpredictsCofs=0.072fF/ m m,whichisalso predictedbyourmodel.Again,themodelpredictionsareverygood,except forCofw,forwhichthereisa26%error.Thisrelativelylargeerror, especiallyforDGdevices,comesfromtheignored bfregioninFig.4.5(a), whichmightcontributetoCofwwhenLeSisrelativelylarge.Nonetheless, ourmodeloverallagreesverywellwiththe2-Dsimulationresultsfrom MEDICI,includingadditionalonesforotherSGFD/SOI(withLg=13nm

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74 andLeSD=2.7nm)andDG(Lg=7nmandLeSD=2.0nm)MOSFETs, showinggenerally<15%errors.Wenotethatthetuningparameterfifin (4.4)tendstoincreaseandapproachunitywithdecreasingLeSD, especiallyforDGdevices.Forshortunderlaps,thesource/drain-body doping profile tends to be more abrupt, removing uncertainty in LeSD. 4.5 Model Implementation in UFDG (Ver. 3.5) Now,weimplementtheanalyticalmodelforparasiticfringe capacitanceinUFDG(Ver.3.5)[Fos06a,Fos06b],withtheVGSdependencesaccountedfor.Theprocess/physicsbasisofUFDG,with rigorousaccountingsforSCEs(viaa2-DsolutionofPoissonsequationin theUTB),quantization(QM)effects(viaaself-consistentsolutionofthe PoissonandSchrdingerequationsintheUTB[Ge02]thatdescribesthe bulkinversion[Kim05b]),andcarriertransportintheUTB/channel(viaa QM-basedmobilitymodel[Fos06b]withcarriertemperature-dependent velocityovershoot[Ge01]andcarrierinjection-velocitydefinedballisticlimitcurrent[Fos06b]),makesitquasi-predictiveandhenceusefulfor projectingnonclassicalnanoscaledevice/circuitperformance.The implementationwasfacilitatedbytheregionalanalysesforweakand stronginversionusedinUFDG,whicharelinkedby(-D)VGfS-and VGbS-basedcubicsplinesforcharge(andcurrent)acrossthemoderateinversionregiondefinedbycontourboundariesinVGfS-VGbSspace [Fos06b].TheUFDGaccountingfortheVGS-dependentLeff[Fos03c, Tri05a] was similarly facilitated by the noted regional modeling.

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75 Modelimplementationhasbeendoneasfollows.Atfirst,weuse aflag(CFF)toturnon(CFF=1)andoff(CFF=0)theparasiticfringe capacitancemodel.Then,tox+tgiscomparedtoLeSD,andifitissmaller thanLeSDortgiszero,CofissettobezerosinceCofshouldbezero,while (4.3)predictsanegativesolution.WhenitislargerthanLeSD,Cofis calculatedwith(4.3).AftertheCofcalculation,Cifcalculationwillfollow. AsmentionedinSec.4.3,thetotalparasiticG-S/DcapacitanceforDG devicesintheweak-inversionregionisapproximatedbythesetwo components,i.e.,CofandCif,appliedforbothgatescoupledtoboththe sourceandthedrain.Here,itshouldbenotedthatthemodelisaccurate foracertainrangeasdefinedinSec.4.3,andthusLeSDshouldbesettoa properconstantvaluewhenitisoutofthedefinedrange.So,forLeSD< tox,LeSDissettotoxforCofcalculations,while,forLeSD<0.27tox,LeSDis definedto0.27toxforCifcalculations.Therefore,forabruptcasewithout underlap,themodelcalculatesCofandCifwithLeSD=toxandLeSD= 0.27tox,respectively.Theseconstantvaluesareconsistentwiththosein [Shr82].Also,whenLeSD>0.27tox+tSi,CifissettozeroinUFDG,because themodelisnotdefinedinthisregion.ForSGFD/SOIdevices,theBOXfringecapacitanceisincludedinthetotalparasiticcapacitanceas explained.SincetheBOX-fringecapacitanceismodeledwiththe assumptionthattwoconductingplatesareplacedseparately,LeSDcannot bezero.Therefore,inUFDG,theminimumvalueofLeSDissetto1.2nm, which is empirically obtained from the numerical simulations.

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76 4.6 Model Applications WenowuseUFDG/Spice3toaccesstheeffectofCfonDGCMOS speedandtocheckthebenefitofanoptimalG-S/DunderlaponDGCMOS speed,aswellasshowmoreverificationofourfringecapacitancemodel. Todothis,weconsidertheHP45technologynode[Sem03]withLg=18nm (andsilicon-dioxidespacers).WeassumeDGMOSFETs(e.g.,FinFETs [Hua99])withamidgapgatewithtg=18nm,andundopedUTBswithtSi=Lg/2=9nm.(Actually,tSi=Leff/2givesgoodSCEcontrol[Yan05],so,for deviceswithunderlap,weareusingthinnertSithanisneeded.Wedothis becausewewanttocomparetheunderlap-deviceperformancewiththatof awell-tempereddevicewithoutunderlap,i.e.,onewithanabruptS/DbodyjunctionforwhichLeff@ Lg.)Throughoutthestudy,wegenerallyuse the2003ITRS[Sem03]asareference,exceptfortoxandRSDspecifications.Thegateleakagecurrentcanbecontrolledwiththickertox, e.g.,1.0nminsteadof0.7nmgivenintheITRS,enablingapragmaticyet optimalDGCMOS[Fos04b].TheG-S/Dunderlapregionimplies, comparedtotheabruptjunction,higherRSD,whichmustincludea component( D RSD)definedbyNSD(y).Noteherethatamorerigorous design optimization study of the underlap will be given in chapter 5. InFig.4.8,UFDG-predictedgatecapacitancesversusVGSare comparedwiththosefromMEDICIsimulationsfortheDGnMOSFET, withandwithout(abruptNSD(y))G-S/Dunderlap.Noteherethatforthe abruptNSD(y)withLeSD=0,(4.3)and(4.4)donotapplydirectly.However,

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77 Figure 4.8UFDG-andMEDICI-predictedgatecapacitanceversusgate voltagefortheLg=18nmDGnMOSFET(tSi=9nm,tox=1nm, tg=18nm,midgapgate),withandwithout(abruptNSD(y))GS/Dunderlap.Forthenear-optimalunderlap,LeSD=3.4nm isdefinedbyagradedNSD(y)ina15nmS/Dextensionwith 9nm straggle [Tri05a]. -0.20.00.20.40.60.81.0 VGS [V] 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4CG [fF/ m m] Abrupt NSD(y) w/ MEDICI Gradual NSD(y) w/ MEDICI LeSD=0 w/ UFDG LeSD=3.4nm w/ UFDG VDS=50mV

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78 forcaseslikethis,UFDGassumesfinitevaluesforLeSDthatmake(4.3) and(4.4)reasonablyconsistentwith[Shr82].Fortheunderlapcase,a near-optimalLeSD=3.4nm,withregardtotheCfvs.RSDtradeoff,was obtainedfromNSD(y)ina15nmS/Dextensionwitha9nmstraggle [Tri05a].Ascanbeseeninthefigurethen,withfiftunedtogivegood subthresholdCGmatches,thepredictedresultsareingoodagreement withthosefromMEDICIforbothdevicestructures,againshowingthe benefitoftheunderlapinreducingCGintheweak-inversionregion. However,asshownbytheUFDG(withRSDtunedtomatchIon)and MEDICIcurrent-voltagepredictionsinFig.4.9,Ionisslightlyloweredby theunderlapduetohigherRSD.(TheQMandvelocityovershootoptions werenotusedherebecausetheseeffectsarenotmodeledwellinMEDICI) NotealsothesubstantivereductioninIoffaffordedbytheunderlap,which isrelatedtoLeff>Lg[Fos03c,Tri05a].Thereisindeedanunderlap-design tradeoff regarding Ioff (or Leff), Ion (or RSD), and CG (or speed). ForCMOSspeedprojectionsandoptimal-underlapstudy,we mustensurethat D RSDiscorrelatedproperlywithLeffandCf,allofwhich dependonNSD(y)intheS/Dextension.WeassumedthatRSDispragmatic andconstant(=120 W m m+ D RSD)inthestrong-inversionregion,with D RSDevaluatedfromthedifferencebetweentheMEDICI-predictedIonfor theunderlap(withLeSDdefinedasnoted)andtheabrupt-NSD(y)devices, asnotedwithreferencetoFig.4.9.Then,withthetotalRSDdefined,and fifevaluatedasnotedwithreferencetoFig.4.8,weuseUFDG(withthe

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79 Figure 4.9UFDG-andMEDICI-predictedcurrent-voltage characteristicsoftheLg=18nmDGnMOSFETinFig.4.7, with and without the G-S/D underlap. 0.00.10.20.30.40.50.60.70.80.91.0 VGS [V] 10-1010-910-810-710-610-510-410-310-2IDS [A/ m m] Abrupt NSD(y) w/ MEDICI LeSD=0 w/ UFDG Gradual NSD(y) w/ MEDICI LeSD=3.4nm w/ UFDG VDS= 50mV 1.0V

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80 velocityovershoot[Ge01]andquantization[Ge02]optionsturnedon)in Spice3tosimulatea9-stageunloadedDGCMOS-inverterringoscillator. TheUFDG/Spice3-predictedpropagationdelaysfordifferentLg=18nm devicedesignsareplottedversussupplyvoltage(VDD)inFig.4.10.For comparison,resultsforaworst-caseabruptNSD(y)withG-S/Doverlap (definedas10%ofLg)capacitance,asinclassicalMOSFETs,areincluded inthefigure.Forthiscase,CfismodeledasdiscussedfortheabruptNSD(y)deviceofFig.4.8,andanoverlapcapacitanceequalto( eox/ tox)W(0.1Lg)isassumedatthesourceanddrain.Notethatsuchdesignis idealwhenonlyIonorRSDisconsidered[Tri05a],butitsspeedismuch slower(41%longerdelay)thanthatforthesamedevicestructure(i.e.,tox=1nmandtSi=9nm)withnear-optimalunderlap.Evenwithoutany overlapcapacitance,whichisnotrealistic,theabrupt-NSD(y)devicesare slower(5%longerdelay)thanthosewithunderlap.Indeedthen,the reductionofCGaffordedbywell-temperedunderlaptranslatestofaster CMOS speed. Wenowexploreoptimizationoftheunderlapdesign.Asnotedin Fig.4.9,Ioffofthedevicewithunderlapismuchlowerthanthatofthe abrupt-NSD(y)devicebecauseofthebetterSCEcontrol.Wecanthus considerincreasingtSiand/ortoxtolowerthethresholdvoltage(via enhancedSCEsandlessquantization[Tri03a])andmakeIoffroughly equaltothatoftheabrupt-NSD(y)device.IncreasingtSialonemay increaseIonabit,butitalsoincreasesCifasindicatedin(4.4)andas

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81 Figure 4.10UFDG/Spice3-predictedpropagationdelaysversussupply voltageof9-stageunloadedDGCMOS-inverterring oscillatorsforfivedifferentvariationsoftheLg=18nm devicedesignofFigs.4.8and4.9,withandwithouttheGS/Dunderlap.Fortheworst-casedesign,aG-S/Doverlapof 10%ofLgwasassumed.Forthethicktox=1.5nmdevice design,theVDD=1.0VdelaypredictedwiththeG-S/Dfringe capacitance completely removed is plotted as well. LeSD=0 w/ overlap (0.1Lg) LeSD=0 w/o overlap LeSD=3.4nm w/ tox=1nm & tSi=9nm LeSD=3.3nm w/ tox=1.5nm & tSi=9nm LeSD=3.3nm w/ tox=1nm & tSi=12nm 0.70.80.91.01.1 VDD [V] 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0Delay/Stage [ps] tox=1.5nm w/o Cf

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82 Figure 4.11UFDG-andMEDICI-predictedgatecapacitanceversusgate voltagefortheLg=18nmDGnMOSFETwiththeG-S/D underlap, for varying UTB and oxide thicknesses.tox=1nm & tSi=9nm w/ UFDG tox=1.5nm & tSi=9nm w/ UFDG tox=1nm & tSi=12nm w/ UFDG tox=1nm & tSi=9nm w/ MEDICI tox=1.5nm & tSi=9nm w/ MEDICI tox=1nm & tSi=12nm w/ MEDICI VDS = 50mV -0.20.00.20.40.60.81.0 VGS [V] 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4CG [fF/ m m]

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83 shownbytheUFDGandMEDICIsimulationresultsinFig.4.11.Thus,it doesnotdecreasethedelaymuchasshowninFig.4.10.Infact,thespeed isslightlydegraded,exceptforlowVDDwheretheIonincreaseismore significant.(Nonetheless,thisthickertSi=12nm @ Leff/2ismore pragmatictechnologically,stillyieldinggoodSCEcontrolandspeed performance.)Increasingtoxyieldsamorepragmaticbenefit.Fortox= 1.5nm,thedelayisactuallyabitshorter,asseeninFig.4.10,because boththeintrinsicgatecapacitanceandtheparasiticfringecapacitance (mainlyCofinstronginversion)arereducedwithincreasingtox,as reflectedinFig.4.11,whilethechannelcurrentandIondecreaseata lesserratebecauseofbulkinversionandmobilityenhancement[Kim05b]. However,themainbenefitofthickertoxisnotenhancedspeed,but restrictedgatetunnelingcurrentandavoidanceofahighk dielectric, withoutanyspeeddegradation.Forsuchpragmaticdesign,Fig.4.10 showsthatthecombinationofthickertoxwithnear-optimalG-S/D underlapyields32%improvementintheCMOSspeedatVDD=1.0V comparedtothatoftheabrupt-NSD(y)designwithtypicalG-S/Doverlap; itiseven9%fasterthanthatoftheidealabrupt-NSD(y)designwithout theoverlap.(And,itcouldbemademorepragmaticbyusingthickertSias we have intimated.) TheimpactoftheparasiticfringecapacitanceontheCMOS speedissevere.Toemphasizethisfinding,weincludeinFig.4.10the UFDG/Spice3-predictedring-oscillatordelayatVDD=1.0Vforthe

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84 pragmatictox=1.5nmdevicedesign,butwithCfcompletelyremoved.The resultisdramatic.Thedelayisreducedfrom2.7psto0.7ps,orbyabouta factoroffour!Thisresult,whichwouldbelargerforcommonsiliconnitridespacers,showsthattypicalG-S/Dfringecapacitanceinnanoscale DGCMOSdevices,evenwithoptimalG-S/Dunderlap,playsa predominant role in limiting speed. 4.7 Summary Using2-Dnumericaldevicesimulations,weshowedthatthe parasiticfringecapacitancesinnonclassicalnanoscaleMOSFETs,e.g., DGFinFETs,aresignificant,withimportantVGSdependencesduetothe gate-source/drainunderlapthatinfactreducesthecapacitance.With physicalinsightsfromthedevicesimulations,wedevelopedananalytical modelfortheparasiticcapacitance,includinginner-andouter-fringe components,andaBOX-fringecomponentforFD/SOIMOSFETs,allwith dependencesonVGSandontheunderlapstructure.Themodelwas verifiedgenerallybythenumericalsimulations,andimplementedinour process/physics-basedcompactmodel(UFDG-3.5).WithUFDGinSpice3, weshowed,viaring-oscillatorsimulations,thatreducingtheparasitic capacitanceviaoptimalunderlapdesigncanbequiteeffectivein improvingnanoscaleDGCMOSspeed,whichisbasicallydefinedbya tradeoffregardingthecapacitanceandsource/drainseriesresistance. Further,weshowedthat,foragivenunderlapstructure,increasingthe UTBthicknesstendstoslightlydegradethedevicespeedduetothe

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85 increasedinner-fringecapacitanceintheweak-inversionregion(butstill couldyieldagoodpragmaticdesign).However,increasingthegate-oxide thickness,withnear-optimalunderlap,cangiveapragmaticallyimproved DGCMOSdesignthatavoidsgatecurrentandhighk dielectric,without anyspeeddegradation;iffact,wepredictedthatthespeedcanactuallybe enhancedabit.Suchapragmaticdesignispossiblebecauseincreasingtoxreducesboththeparasiticfringecapacitanceandtheintrinsicgate capacitance,whiledecreasingthechannelcurrentandIonlessbecauseof bulk inversion and mobility enhancement. Nonetheless,westresstheseverityoftheG-S/Dfringecapacitanceeffectonspeedshownbyoursimulations.Wefoundthatthis parasiticcapacitanceispredominantinlimitingnanoscaleDGCMOS speed,evenwhenmoderatedbyanoptimalG-S/Dunderlap.(This statementappliestoclassicalCMOS,withoutunderlap,aswell.)Indeed, parasiticcapacitance,aswellasseriesresistance,arecrucialissuesinthe design of nanoscale CMOS.

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86 CHAPTER 5 DOUBLE-GATE FINFETS WITH GATE-SOURE/DRAIN UNDERLAP: APPLICATIONS ON SRAM CELL AND DESIGN OPTIMIZATION FOR DEVICE SPEED 5.1 Introduction Double-gate(DG)FinFETswithundopedultra-thinbodies (UTBs)areveryattractiveforscaledCMOSmainlyduetotheirexcellent suppressionofshort-channeleffects(SCEs),highon-stateversusoff-state currentratio(Ion/Ioff),andeliminationofthresholdvoltage(Vt)variations causedbystatisticaldopantfluctuationeffects.Highercarriermobility, whichcomesfromsmallertransverseelectricfieldandnegligibleimpurity scatteringintheundopedUTBs,andmuchsmallerparasiticjunction capacitancearetheadditionalbenefitsofDGFinFETs.However,withthe ultimatelimitoftheUTB,i.e., @ 5nm[Tri03a]duetoseverequantization effectsandtechnologicaldifficulties,DGFinFETscalingtoandbeyond theHP25nodewiththephysicalgatelength(Lg)of10nm[Sem05]seems tobeextremelydifficultsincethefinwidth(wSi)requiredforSCEcontrol iswSi@ Leff/2[Yan05]ifhighk gatedielectricisnotviable.Thus,for furthergatelengthscalingtoandbeyond10nm,DGFinFETshavetobe designedwithgate-source/drain(G-S/D)underlap[Tri05a].Evenforthe Lg>10nmregimeor/andwhenareliablehighk gatedielectricis developed,theunderlapstructureshouldbequiteusefulinthedevice

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87 designforeffectinganoptimalSCEsversusIontrade-off[Kra06,Lim05, Tri05a]. ThebenefitofanunderlapstructureintheDGFinFETshouldbe mostusefulforSRAMapplications.Thisisbecausethereadstaticnoise margin(read-SNM)andwrite-marginarenotdefinedbytheabsolute valueofIon,butbyVtandtherelativestrengthofIonamongthe transistorsinSRAMcell.NoteherethatVtcanbeeasilyincreasedbySCE control,withsomedegradationofIon,viatheeffectivechannellength (Leff)modulationintheweak-inversionregion[Fos03c].Also,notethat highVttendstogivelargeread-SNMandwrite-marginbasedonthelarge invertertrippoint,andsmallcellleakagecurrentsorstandbypowerdue tosmallIoff[Guo05].Ontheotherhand,forthedevicespeedissue,we confirmedthattheoptimallydesignedunderlap[Kim06]canreducethe propagationdelaybylimitingthefringecapacitance(Cf)inweak inversion.However,thisdesignapproachisvirtuallybasedonthetradeoffbetweenIonandtheparasiticcapacitanceinweakinversion.Therefore, withregardtothedevicespeed,broaderstudyabouttheunderlap optimization is needed. Inthischapter,wefirstexploreSRAMcelldesignandscalingvia DGFinFETswithG-S/Dunderlap.Forthisstudy,DGFinFETswiththe underlaparefirstcharacterizedintermsofVtwithvariousextension length(Lext),straggle( sL),andwSivia2-Dnumerical[Med04]and analyticalsimulations[Fos06a].TherelationshipbetweenVtandreadSNMisverifiedtodefineanoptimalSRAMcell,fortheHP45nodewith

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88 Lg=18nm[Sem05],withlargeread-SNMaswellaslargewrite-margin andgoodimmunitytoprocessvariationsofLextand sL.Then,ascalability studyoftheDGFinFET-basedSRAMcell,withandwithouttheG-S/D underlap,isdone.Finally,basedontheinsightgainedfromVtshiftand Ionvariationcausedby sLchanges,weoptimallydesignDGFinFETswith relatively high Ion to improve the device speed. 5.2 DG FinFET without Underlap ForHP45(Lg=18nm)applications[Sem05],wefirst characterizethepragmaticDGFinFETwithundopedUTBs,whichhas theequivalentoxidethickness(EOT)of1nmandwSiof9nm.Notehere thatEOT=1nm,insteadof<0.7nmgiveninITRS[Sem05],andwSi=Leff/ 2=9nm[Yan05]areessentialtocontrolthegateleakagecurrent[Yan04] andSCEsofaDGFinFETwithabruptS/D-extensiondoping,NSD(y), respectively.ForthisDGFinFETdesignwithamidgapmetalgate,UFDG [Fos06a],withtheaidofMedici[Med04],predictsIoffof2.96nA/ m mandIonof1.26mA/ m m.Here,thepredictedIoffisabouttwo-ordersofmagnitude lowerthanthelimitinITRS[Sem05],mainlyduetowell-controlledSCEs viathinwSiandthemidgapgate.Also,thesubthresholdswing(S)is predictedtobelessthan90mV/decduealsotothethinwSi.Ontheother hand,thepredictedIondoesnotmeetthecurrentlimit(2.05mA/ m m) projectedbyITRS[Sem05].Thisismainlybecauseoftheassumed,thick toxtocontrolgateleakagecurrent,andthemidgapgate.Inaddition,IonofthedesigneddeviceisfurtherdegradedbyhighS/Dseriesresistance (RSD=85 W m m),whichiscurrentlyviable,butmuchlargerthanthe

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89 specifiedvalue(RSD=53 W m m)attheHP45node[Sem05],andthe ballisticlimit[Tri05b],whichmightnotbeaccountedforinITRSIonprojections.Unfortunately,withouttheviablehighk gatedielectricand the technology reducing RSD further, this sacrifice of Ion is not avoidable. Nevertheless,theuseofthispragmaticDGFinFETdesignfor SRAMapplicationsisnotlimitedsince,asmentioned,therelative strengthofcurrentsamongtransistorsinSRAMcellismuchmore importantthantheirabsolutevalues.Inaddition,thepredictedVtofthe mentionedDGFinFETdesignisrelativelyhigh(Vt@ 0.29Vwhenitis definedviaIDS(VGS=Vt)=10-7Wg/Lg(A))duetotheassumedmidgapgate andwell-controlledSCEs.Therefore,wecaninferherethatthisDG FinFETdesignisgoodenoughforSRAMapplications.Indeed,UFDG/ Spice3predictsrelativelygoodread-SNM(177mV)andwritemargin (350mV)for1Vsupplyvoltage,whichareconsistentwiththeresultsfor thehigh-VtDGFinFETdesignspresentedin[Guo05].Thus,forSRAM study,thispragmaticDGFinFETdesignwithoutunderlapisusedasa reference, and compared to other DG FinFET designs with underlap. Forthedevicespeedissue,itseemstobeextremelydifficultto meettheCMOSspeedlimitinITRSduetothementionedIondegradation, whichisinevitable.Nevertheless,itisworthytostudythedesign optimizationoftheunderlaptoimprovethedevicespeedofDGFinFETs. So,theCMOSspeedissueofDGFinFETsisincludedinSec.5.5toshow thespeedsuperiorityoftheunderlappeddevicesovertheabrupt

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90 counterparts,andprovideanoptimaldesignapproachinusingthe underlap. 5.3 Threshold Voltage Modulation by Underlap Now,toincreaseVtoftheDGFinFETwiththefixedgate electrode,i.e.,amidgapgate,weemploytheunderlapstructure.The underlapisdefinedbyLextand sL[Tri05a],whichaffectthedevice characteristicsviatheeffectiveunderlap(LeSD,orparametersLeS/LeDin UFDG).Since,intheweak-inversionregion,LeffisdefinedbyLg+2LeSD[Fos03c],wecansimplycontrolSCEsbydefiningtheunderlap,andthus increaseVtofthegivendeviceaswellasdecreasingIoff,whileIonis sacrificedsomebytheincreasedS/Dseriesresistance( D RSD).Tocheck thiseffect,thepreviousDGFinFETdesignwithabruptNSD(y),i.e.,the devicewithwSi=9nmandtox=1nm,ismodifiedtohavetheunderlap definedbyvariousLextand sL.Then,thedevicecharacteristicsare comparedtothoseofthereferencedesign.Here,notethatforSRAM applicationstheDGFinFETdesignisfirstorientedtomakethedevice havehighVtratherthanhighIon,sincehighVtismorebeneficialforhigh read-SNMandwritemarginaswellaslowstandbypower.Then,basedon theinsightsgainedfromVtstudy,weoptimizeDGFinFETswithregard to Ion and CG in weak inversion to improve the device speed. ForthestudyofDGFinFETswithunderlap,andoftheSRAM celltheyconstitute,weuseUFDGandMediciinconcert.Foraparticular devicewithNSD(y)definedbyLextand sL,wefirstsimulateitwithMedici, predictingcurrent-voltagecharacteristics,SCEs,Ion,etc.(TheQMand

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91 velocityovershootoptionswerenotusedsincetheseeffectsarenot modeledwellinMedici.)ThenwecalibrateUFDGtotheMedici predictions,therebyinferringLeSD,Leff,and D RSD.Here, D RSDis evaluatedfromthedifferencebetweentheMedici-predictedIonforthe underlapandtheabrupt-NSD(y)device.WiththeFinFETmodelcard therebydefined,UFDG/Spice3withQM[Ge02]andvelocityovershoot model[Ge01]turnedonisfinallyusedfortheneededdevice/circuit simulations.NoteherethattoaccountfortheS/DdopanteffectsonVt,the work-functionofthegateelectrodeisaccordinglymodulatedsinceUFDG does not have a proper model or model parameter to project this effect. UFDG-predictedVtdependenceonLeff(orLeSD)fordifferentLextalongwithvarious sLisrepresentedinFig.5.1.Fromthissimulation result,welearntwothings:OneisthateventhoughshorterLextshowsa bitbetterimmunityto D Leff( D LeSD)andhigherVt,thevarious combinationsofLextand sLforthesameLeSDdonotaffectVtmuchwhen LeSDisnottooshort.TheotheroneisthatVtcanbesimplyincreasedby increasingLeSDviausingshorter sLforagivenLext.Aninterestingresult hereisthatVtdecreasesfasterforshorterLeSDandcanbeevensmaller thanthatoftheabruptNSD(y)device.ThisismainlyduetoS/Ddopants thatdiffuseintothechannel,whichhappenswhenlong sLisusedtoget shortLeSDforagivenLext.Forlongsymmetricaldouble-gate(SDG) devices, the threshold voltage is represented by [Tri05b]

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92 Figure 5.1UFDG-predictedthresholdvoltage(Vt)versustheeffective channellength(Leff);LeffisdefinedbyLg(=18nm)+2LeSD, wheredifferentLeSDcanbeobtainedbythevarious combinationofLextand sL;thedottedlineshowsVtofthe DGFinFETwiththeabruptNSD(y)dopingprofile;LeSDincreases with decreasing sL for a given Lext. Lext=18nm, sL=8-12nm Lext=15nm, sL=6-10nm Lext=12nm, sL=4-8nm Vt (0.295V) for abrupt NSD(y) 22 2.0 23 2.5 24 3.0 25 3.5 26 4.0 27 4.5 28 5.0 Leff [nm] LeSD [nm] 0.25 0.30 0.35 0.40Vt [V] sL

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93 ,(5.1) where FMSisthework-functiondifferencebetweengateandbody,QBis depletionchargedensitydefinedbythedopantsinthechannel(NB)via qNBtSi,and fcisthesurfacepotentialatVtdefinedby(kT/q)ln(1011cm-2/ tSini).S/DdopantsinthechannelcancontributetoreducingVtbythelast termin(5.1),i.e.,QB/Cox.Indeed,forLext=18nm,when sLisincreased from8nm(LeSD=4.8nm)to12nm(LeSD=2.4nm),Vtisreducedfrom0.40V to0.28V,i.e.,total D Vt=0.12VasreflectedinFig.5.2.Thisdecreaseis much larger than SCE-governed D Vt(SCE) [Tri03b] ( @ 0.07V), i.e., ,(5.2) where fFistheFermipotential, fcisthesurfacepotentialdefinedin(5.1), and l(SDG)=(tSi/2)[0.5(1+12tox/tSi)]1/2.Thus,theadditionalVtshift( @ 0.05V)inFig.5.2shouldbeexplainedbyQBin(5.1).Therefore,we concludethatthegeneralVtreductionisnotdefinedonlybySCEs governedLeff,butalsobyQB/Cox,especiallywhen sLislongtogetshort LeSD. So,toeffectivelyincreaseVtandthusutilizetheunderlapfor SRAMapplications,wehavetoemploytheunderlapdefinedbylongLeSDviashortLextand sL.However,longLeSDtendstodegradeIonduetothe increased D RSDasshowninFig.5.3.Inaddition,theaccesstimeinSRAM V t f c F MS Q B C ox --------- + = D V 2 D t L eff t Si () 2 e L eff 2 l f F f c V bi V bi V DS + () + () 12 e L eff 2 l ------------------------------------------------------------------------------------------------------------@

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94 Figure 5.2Thresholdvoltagereduction( D Vt)versustheeffective channellength(Leff)withLeff=27.8nmasthereference;the dottedlineshows D VtcausedonlybySCEsexpressedin (5.2). Eq. (5.2) 22 2.0 23 2.5 24 3.0 25 3.5 26 4.0 27 4.5 28 5.0 Leff [nm] LeSD [nm] -0.14 -0.12 -0.10 -0.08 -0.06 -0.04 -0.02 0.00D Vt [V] Lext=18nm, sL=8-12nm Lext=15nm, sL=6-10nm Lext=12nm, sL=4-8nmsL

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95 Figure 5.3UFDG-predictedon-statecurrent(Ion)andtheincreased source/drainseriesresistance( D RSD)causedbythe underlapversustheeffectivechannellength(Leff);the dotted line indicates Ion of the abrupt NSD(y) device. D RSDIon Ion of abrupt NSD(y) device 0 10 20 30 40 50D RSD [ mW m m] 22 2.0 23 2.5 24 3.0 25 3.5 26 4.0 27 4.5 28 5.0 Leff [nm] LeSD [nm] 1.1 1.2 1.3 1.4 1.5Ion [mA/ m m] Lext=18nm, sL=8-12 Lext=15nm, sL=6-10 Lext=12nm, sL=4-8

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96 cellisdefinedbythebit-lineloadcapacitanceandthedrivingcurrentof transistorsinSRAMcell.Therefore,severedegradationofRSDcancause theread/writeaccessfailure.So,althoughtheoptimalLeSDshouldbe defined to get high Vt, severe Ion degradation must be avoided. (NotefromadditionalUFDGsimulationresultsinFig.5.3that, forallLext,Ioncanevenbehigherthanthatoftheabrupt-NSD(y) counterpart(thedashline)whenLeSDisshort.Also,weseethat,forthe sameLeSD,IonishigherforlongerLext.Alloftheseobservationscanbe explainedbytheeffectofQB/Cox,ortheVtshiftreflectedinFig.5.2along withtherelativelysmall D RSD.Namely,Ionreductioncausedbythe increasedRSDintheunderlapisnotsosignificant,andthusIonincrement causedbytheVtshiftviaQB/Coxtendstoenhancethetotalon-state current.Becauseofhigher sLandthuslargerVtshift,thiseffectismore obviousforshortLeSD.Thesecharacteristicsoftheunderlaparequite usefulsincetheparasiticcapacitanceinweakinversioncanstillbemade smallbytheunderlap,whileIoncanbecomparableto(orevenlargerthan) thatoftheabrupt-NSD(y)case.Thus,wecanutilizethisinteresting characteristicoftheunderlaptoimprovethedevicespeedaswediscussin Sec. 5.5.) ForVtdependenceonwSivariation,weconfirminFig.5.4that, forthinnerwSi,Vtroll-offwithincreasing sLisabitsmallerandthe absolutevalueofVtismuchlargerduetobetterSCEimmunity.Thus, throughoutourstudy,weassumewSi=Lg/2,(exceptforLg<10nminthe

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97 Figure 5.4UFDG-predictedthresholdvoltage(Vt)versustheeffective channellength(Leff)forthedifferentfinwidth(wSi);Lextis fixedat12nm,andthedifferent sLdefinestheunderlap (LeSD) or the effective channel length (Leff). wSi=9nm wSi=10nm wSi=11nm 21 1.5 22 2.0 23 2.5 24 3.0 25 3.5 26 4.0 27 4.5 28 5.0 29 5.5 Leff [nm] LeSD [nm] 0.20 0.25 0.30 0.35 0.40 0.45Vt [V] sL=4-8nmsL

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98 SRAMscalingstudy),ratherthanLeff/2,whichisthemaximumfinwidth tocontrolSCEs[Yan05].Here,itshouldbenotedthatVtisdefinedby fcasin(5.1)andthusaffectedbywSiintheformofln(1/wSi)[Tri05b], although DfcforvaryingwSiisnegligiblysmall.Also,forshortLeSDdefinedbyhigh sL,thecontributionofQB/Coxto D Vtislargerforthicker wSisinceQBisdefinedbyqwSiNB[Tri05b].Nevertheless,wecaninferthat D Vtcausedby D wSiisdefinedpredominantlybySCEsthrough(5.2).The effectsoftoxvariationonVtshouldbesimilartothoseofwSivariation,and thusthinnertoxisdesirablefordeviceoptimizations.However,tocontrol gateleakagecurrentswithouthighk gatedielectric,thinningtoxisnota viableoptionfordeviceoptimizations.So,inthisstudy,wedonotconsider the option of changing tox. 5.4 Applications on SRAM Cell 5.4.1 SRAM Cell Design BasedonVtversusLeff(orLeSD)characteristicsofthe underlappedDGFinFETspresentedintheprevioussubsection,weexpect that,forthegiventoxandwSi,longLeSDdefinedbyshortLextandlow sLcouldbeagooddesignapproachforSRAMapplications.Indeed,asevident inFig.5.5(a),whichshowsUFDG-predictedread-SNMversusLeff(or LeSD)ofthe6-TSRAMcellshowninFig.5.5(b),composedofDGFinFETs withwSi=9nmandtox=1nm,theread-SNMgenerallyfollowstheVtvariationsshowninFig.5.1.Therefore,weconcludethat,forthegiventoxandwSi,makingLeSDlongbyselectingshortLextandlow sLcouldbea

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99 Figure 5.5(a)UFDG-predictedreadstaticnoisemargin(read-SNM) versustheeffectivechannellength(Leff)and(b)schematic of6-TSRAMcell[Cho06];read-SNMgenerallyfollowsVtLeffplotinFig.5.1;thedottedlinein(a)representsthe read-SNM of the abrupt NSD(y) device. read-SNM of abrupt NSD(y) device BLBL WL VDDN1N2 P1P2 N3 N4 VLVRAccess Access Driver/ pull-down Driver/ pull-down(b)(a) 22 2.0 23 2.5 24 3.0 25 3.5 26 4.0 27 4.5 28 5.0 Leff [nm] LeSD [nm] 170 180 190 200 210 220SNM [mV] Lext=18nm, sL=8-12nm Lext=15nm, sL=6-10nm Lext=12nm, sL=4-8nm sLV BLVBL

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100 gooddevicedesignapproachtogethighVtandthuslargeread-SNMin SRAMapplications.However,weinferthattheDGFinFETdesignwith LeSD=3.6nm,whichisdefinedbyLext=12nmand sL=6nm,canbean optimaldesign.Thisisbecause,forverylongLeSD,thereissevere reductionofIonaspredictedinFig.5.3,portendingpossibleread/write accessfailure.Noteherethatthetechnologicallowerlimitof sLseemsto beabout5nm,andthusthedefinedunderlapisdoable.Comparedtothe DGFinFETdesignwiththeabrupt-NSD(y),thisoptimalDGFinFEThas 29%higherVt,whileIonisonlyabout3%lower.Ityieldsread-SNMequal to 209mV, 18% higher than that of the abrupt-NSD(y) design. TheUFDG/Spice3-predictedbutterflycurveoftheoptimalDG FinFETdesignwithG-S/DunderlapisshowninFig.5.6,whichalso includesthebutterflycurveoftheabrupt-NSD(y)designforcomparison. Higherinvertertrippointandthushigherread-SNMofthedevicewith higher Vt are reflected in these butterfly curves. Also,thebenefitofhighVtinthewrite-0marginisshowninFig. 5.7,eventhoughitisverysmall.Therefore,bycontrollingSCEsviathe optimalunderlap,wecouldimproveread-SNMandwrite-margin,aswell as standby power as implied by very small Ioff. Toimprovetheread-SNMfurther,high b -ratio,i.e.,thesizeratiobetweenW/Lofthepull-downtransistor(i.e.,N1orN2inFig5.5(b)) andW/Loftheaccesstransistor(i.e.,N3orN4inFig.5.5(b))intheSRAM cell,isusuallyused.Indeed,wecouldincreasetheread-SNMto240mV

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101 Figure 5.6UFDG-predictedbutterflycurvesofthethreeLg=18nm SRAMcellscomposedofaDGFinFET(wSi=9nm,tox=1nm) withoutunderlapandtwounderlappedDGFinFETs(via Lext=12nmand sL=6nm)with b -rati o=1and2;VDD=1.0V. 0.00.20.40.60.81.0VL [V] 0.0 0.2 0.4 0.6 0.8 1.0VR [V] Abrupt NSD(y) LeSD=3.6nm LeSD=3.6nm w/ b -ratio=2 via longer Lg of access Tr. 177mV 240mV 209mV

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102 Figure 5.7UFDG-predictedwrite-0marginforthethreedifferentLg= 18nmSRAMcellsdefinedinFig.5.6:Forsimulations,VLandVRinFig.5.5(b)arefirstsetto1Vand0V,respectively. Then,V-BL-true(V BLinFig.5.5(b))issweptfrom1Vto0V, monitoring V-data-true (VL in Fig. 5.5(b)). 0.00.20.40.60.81.0 V-BL-true [V] 0.0 0.2 0.4 0.6 0.8 1.0V-data-true [V] Abrupt NSD(y) LeSD=3.6nm LeSD=3.6nm w/ b -ratio=2 via longer Lg of access Tr.

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103 with b -ratio=2viaincreasingthegatelengthoftheaccesstransistors,as indicatedinFig.5.6.However,whenhigh b -ratioisused,thewrite-margin tendstobedegradedasshowninFig.5.7.Thus,the b -ratioshouldbe optimizedbyeffectingthetrade-offbetweenread-SNMandwrite-margin. Anotherapproachtoincreasethe b -ratioandthusimproveread-SNM furtherisup-sizingthepull-downtransistorovertheaccesstransistor,by usingamulti-finFinFETfortheformer.OurUFDG-predictedresults showthatthiscelldesignapproachisthemosteffective,enhancingthe read-SNMto269mV.However,thisdesignmightnotbeanoptimalone duetothesubstantivelayout-areapenalty[Guo05]andwrite-margin reduction. 5.4.2 Sensitivity Issue in SRAM Cell AsimpliedinFigs.5.1and5.4,thinwSi,shortLext,and/orlow sLarebeneficialforbetterimmunitytotheprocess-inducedparameter variations.Tochecktheseeffectsmorethoroughly,thesensitivityofthe optimaldesigndevelopedinSec.5.4.1,i.e.,theDGFinFETwithLg= 18nm,tox=1nm,wSi=9nm,andtheunderlapLeSD=3.4nmdefinedby Lext=12nmand sL=6nm,isexaminedinthissubsectionbyvarying sL, wSi,andLg.Eventhoughithasbeenarguedthatthewriteoperationis mostsensitivetoparametricvariations[Bha05],thesensitivitystudyhere focusesontheread-SNMfluctuationstoevaluatetheobtainedsimulation results with other ones [Cho06].

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104 Figure5.8firstshowsUFDG/Spice3-predictedVt,Ion,andreadSNMvariationsfortheoptimalDGFinFETdesigncausedbythevariation ofstraggle( DsL).Here, DsLisassumedtobe 1nm,or 17%variationfrom thenormal sL=6nm.AsshowninFig.5.8(a), D Vtislessthan7%,which ismuchsmallerthanthatpredicted( D Vt= 24%for DsL@ 1nm,or10%)by Chowdhury[Cho06].Also,asshowninFig.5.8(b), D Iondueto DsLisless than5%,whilethatpredictedbyChowdhury[Cho06]isabout18%for DsL@ 1nm.BecauseofthebetterVtandIonimmunityto DsLoftheoptimally designedDGFinFET,theread-SNMvariations(circlesinFig.5.8(c)) causedby DsLisalsoverysmall(<4%),whilethemaximum D SNM predictedbyChowdhury[Cho06]is13%for DsL@ 1nm.Thehigher sensitivitiesin[Cho06]resultedbecausetheDGFinFETisdesignedwith long sL (= 9.5nm). WithregardtomismatcheffectsintheSRAMcell,wecheckthe D SNMthatresultswhenanaccess(N4inFig.5.5(b))orpull-down transistor(N2inFig.5.5(b))isreplacedwithonedefinedbyvaried sL.As showninFig.5.8(c),thepredicted D SNMcausedbythemismatchforthe accesstransistorvia DsL(1nm,or17%)issmall,beinglessthan5%.The DsLheredefinesonlyasmallchangeinthe b -ratiooftheSRAMcellvia theimplied D Leff(or D Vt)and/or D Ionoftheaccesstransistor.Asnotedin thepreviousdiscussionofthe b -ratioeffect,alarger(2x)changeinthe b ratioeffectsasizableSNMvariation.Similarresultsarepredictedfora mismatchedpull-downtransistorvia DsL,asindicatedinFig.5.8(c).

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105 Figure 5.8UFDG/Sprice3-predictedsensitivityoftheoptimalDG FinFETdesigntothevariationof sL;(a)Vt,(b)Ion,and(c) read-SNMvariations;themismatcheffectin(c)hasbeen checkedbyreplacinganaccess/pull-downtransistorwith the one defined by DsL. -1.0-0.500.51.0DsL[nm] -10 -5 0 5 10D SNM [%] No mismatch Mismatch for Access Transistor Mismatch for Pull-down Transistor -1.0-0.500.51.0DsL [nm] -10 -5 0 5 10D Ion [%] (c) (b) (a) -1.0 -16.7% -0.5 -8.3% 0 0 0.5 8.3% 1.0 16.7%DsL [nm] DsL [%] -10 -5 0 5 10D Vt [%]

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106 Indeed,theFinFETSRAMcellappearstobewellimmunetosuch mismatches defined by reasonable, random variations in sL. Also,forwSiandLgvariations,theoptimalDGFinFETdesign showsgoodimmunitywithregardto D Vt, D Ion,andthus D SNMwhen comparedwithcorrespondingresultspredictedbyChowdhury[Cho06]. Thiscanbeexplainedbythewell-temperedunderlapalongwiththisthin wSioftheoptimalDGFinFETdesign.Table5.1summarizesthe sensitivityoftheoptimalDGFinFETdesigntothevariationsof sL,wSi, andLg.Basedonthecomparisonofthesesimulationresultstothose predictedbyChowdhury[Cho06],whichisgenerallyconsistentwith [Guo05]showing D SNM @ 10%,weconfirmthattheDGFinFETdesign, withoptimalunderlap,inSec.5.4.1canbesuperiorintermsofthe sensitivity to the process-induced parameter variations. Finally,itshouldbenotedthatforahypotheticalLg=22nm bulk-SiSRAMcell, D SNMcausedbythebodydopantfluctuationhasbeen reportedtobeabout26%[Guo05],whichismuchlargerthanthatofthe 18nmDGFinFETcounterpart.Also,Samsudinetal.[Sam06]reported thatanLg=10nmFD/SOIsingle-gate(SG)deviceismorestablethanan Lg=35nmbulkMOSFETin6-TSRAMoperations.Sincethereported large D SNMismainlyduetolarge D Vtand D Ioncausedbythebodydopant fluctuation, D SNMcausedbythemismatchinthebulkSRAMcellseems tobeverysignificant.Notethatlarge D Ionduetolarge D Vtcancause significantSNMvariationswhentheaccesstransistorisinthemismatch.

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107 DsL : (+ / -) 1nm or (+ / -) 17% D wSi : (+ / -) 1 nm or (+ / -) 11% D Lg : (+ / -) 2 nm or (+ / -) 11% D Vt-6.3% / +3.6%-6.4% / +5.2%+4.1% / -6.7% D Ion+5.0% / -4.9%-0.3% / -0.3%-0.6% / +0.1% D SNM-3.8% / +1.3%-3.9% / +2.3%+0.9% / -2.8% D SNM by mismatch Access: -4.9% / +3.8% Pull-down: +4.1% / -3.9% -0.6% / +0.4% -3.3% / +2.2% +1.5% / -1.8% -3.9% / -3.5% Table 5.1 UFDG/Spice3-predictedsensitivityoftheoptimalDGFinFETdesignto thevariationsof sL,wSi,andLg.Notethattheassumedmismatches causedasymmetricbutterflycurves,andsothe D SNMgivenreflectsthe worse-case sensitivity defined with regard to VL or VR in Fig. 5.6.

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108 Therefore,thenanoscalebulkSRAMcellmightbelimitedinitsusage mainlyduetotheaccesstransistormismatch.WithregardtotheSRAM cellsize,theDGFinFETSRAMshouldhavenoareapenaltiesbecausethe FinFETexploitsthethirddimension;thelayoutareaisdefinedbythe half-pitch.Indeed,thelayoutareaoftheDGFinFET6-TSRAMcellis,at the90nmtechnologynode[Sem05],calculatedtobe0.36 m m2[Guo05], whichislessthanthat( @ 0.7 m m2)oftheconventionalplanarSRAMcell [Jun04].Therefore,wecaninferthattheSRAMcellbasedonthe nonclassicaldevices,includingDGFinFETs,hasbetterimmunityto intrinsicparameterfluctuationsthanthatbasedonbulk-SiMOSFETs, while it has no layout area penalties. 5.4.3 SRAM Cell Scaling Intheprevioussubsection,wehaveshownthattheunderlapin DGFinFETsisquiteusefulforSRAMapplicationssinceiteffectively increasesVt,andthusimprovesread-SNMandwrite-margin.Whenthe deviceisscaleddown,thebenefitoftheunderlapshouldbemoreobvious sinceSCEcontrolisgettingmoredifficultinthescaleddevice.So,wewill nowcheckthebenefitoftheunderlapontheSRAMscalabilityby comparingread-SNMofSRAMcellcomposedofDGFinFETswithand without the underlap. Fig.5.9showsUFDG-predictedread-SNMversusthephysical gatelength(Lg)of6-TSRAMcellcomposedofDGFinFETswithand withouttheunderlap.Forthesimulations,wSiwasassumedtobeLg/2to

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109 Figure 5.9(a)UFDG-predictedread-SNMversusthephysicalgate length(Lg)and(b)theread-SNMnormalizedbythesupply voltage(VDD)versusLgplot;in(a),therearetwotransition pointsduetoconstantwSiandVDD,whilethereisonlyone transition point in (b), which is due to a constant wSi. 4681012141618 Lg [nm] 40 60 80 100 120 140 160 180 200 220SNM [mV] Abrupt NSD(y) Underlap w/ Lext=12nm & sL=6nm 4681012141618 Lg [nm] 10 12 14 16 18 20 22 24SNM/VDD (x100) [%] Abrupt NSD(y) Underlap w/ Lext=12nm & sL=6nm (a) (b) wSi=Lg/2 VDD=0.7V wSi=5nm wSi=Lg/2 wSi=5nm

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110 controlSCE,exceptforthecasesofLg<10nmsince5nmisassumedtobe thelowerlimitofwSi[Tri03a].So,forLg<10nm,wSiiskepttobeequal to5nm.Fortheunderlapstructure,weassumedafixedS/Ddopingprofile, i.e.,Lext=12nmand sL=6nm,forallnodeapplications,conservatively keepingthestraggleabovethenotedlowerlimitof sL@ 5nm.Wewould expectsomewhatbetterresultsif sL=5nmwereassumed,andtherefore theresultsinFig.5.9arenotnecessarilythebestattainablewith underlappedFinFETs.Finally,thesupplyvoltagewasassumedtofollow the ITRS projections [Sem05]. Now,noteinFig.5.9thatbyusingtheunderlapstructurewecan improveread-SNMatallnodesbymorethan15%.Also,weseethatthe SRAMcellcanbescaleddowntotheendoftheroadmap,i.e.,Lg=5nm, viaDGFinFETswithG-S/Dunderlap,whiletheSRAMcellviaDG FinFETswithoutunderlaphasitsscalinglimitaroundatLg=10nm, mainly due to severe SCEs. Itisinterestingtonotethattheread-SNMversusLgplotshows twotransitionpointsasmarkedinFig.5.9(a):oneisatLg=10nm,where wSiislimitedat5nmandtheotheroneisatLg=7nm,whereVDDis limitedat0.7V.AlthoughitcanbeseenmoreclearlyfortheDGFinFET withoutunderlap,theread-SNMdecreasesatafasterratebeyondthe firsttransitionpointsincewSi=Lg/2isnotapplicablewhenLg<10nm, andthusmoreSCEscomein.Beyondthesecondtransitionpoint,the reductionrateoftheread-SNMisnotasfastasthatforLg>7nmsince

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111 VDDisnotscaled.Fig.5.9(b)showstheread-SNMnormalizedbyVDD,and thuscontainsonlyonetransitionpoint,i.e.,theoneatLg=10nm.Note thatthistransitionpointfortheunderlapcaseismoreevidentinFig. 5.9(b). Finally,inFig.5.10,thebutterflycurveofthe6-TSRAMcell composedofLg=5nmDGFinFETswiththeunderlapdefinedbyLext= 12nmand sL=6nmisexemplified,andcomparedtothoseoftheDG FinFETwith b -ratio=2viathelongerchannellengthfortheaccess transistorortwofinsforthepull-downtransistor.Asshown,wecan improveread-SNMby14%and17%byusinglongerLgforaccess transistorandtwofinsforthepull-downtransistor,respectively. However,ascanbeseeninFig.5.11,thewrite-0margintendstobe severely(morethan24%)degraded.Therefore,increasingthe b -ratioin SRAMcellshouldbeoptimallyselectedviawiththetrade-offbetween read-SNM and write margin. 5.5 Device Speed Issue 5.5.1 Using Long Straggle FromthestudyoftherelationbetweenS/DdopingprofileandVt(andthusIon)intheprevioussubsection,welearnedthatIonlosscaused bytheunderlapcanbeminimizedbyusinghigh sL.Toquantifythiseffect, UFDG-predictedcurrent-voltagecharacteristicsoftwodifferent underlappedDGFinFETdesignsareshowninFig.5.12,alongwiththat oftheDGFinFETwithoutunderlap.Asevidentinthefigure,theunderlap

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112 Figure 5.10UFDG-predictedbutterflycurvesofthethreeLg=5nm SRAMcellscomposedofDGFinFETs(wSi=5nm,tox= 0.9nm)withunderlap(viaLext=12nmand sL=6nm);three SRAMcellsaredifferentfromeachotherbythechannel lengthfortheaccesstransistoror/andthenumberoffinfor pull-down transistor. 0.00.10.20.30.40.50.6VL [V] 0.0 0.1 0.2 0.3 0.4 0.5 0.6VR [V] LeSD=2.9nm LeSD=2.9nm w/ b -ratio=2 LeSD=2.9nm w/ b -ratio=2 144mV 126mV 148mVvia longer Lg for access Tr. via more fin for pulldown Tr.0.7 0.7

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113 Figure 5.11UFDG-predictedwrite-0marginofthreedifferentLg=5nm SRAMcelldesignsdefinedinFig.5.10:Forsimulations,VLandVRinFig.5.5(b)arefirstsetto1Vand0V,respectively. Then,V-BL-true(V BLinFig.5.5(b))issweptfrom1Vto0V, monitoring V-data-true (VL in Fig. 5.5(b)). 0.00.10.20.30.40.50.60.7 V-BL-true [V] 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7V-data-true [V] LeSD=2.9nm LeSD=2.9nm w/ b -ratio=2 LeSD=2.9nm w/ b -ratio=2 via longer Lg for access Tr. via more fin for pulldown Tr.

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114 Figure 5.12UFDG-predictedcurrent-gatevoltagecharacteristics(a)in log-scaleand(b)linear-scaleofaDGFinFETdesignwithout underlapandtwounderlappeddesignsdefinedbyLext= 12nmand sL=6nm,andLext=18nmand sL=12nm;Lg= 18nm, tox= 1nm, tSi= 9nm, midgap gate. 0.00.20.40.60.81.01.2 VGS [V] 10-1110-1010-910-810-710-610-510-410-310-2IDS [A/ m m] Abrupt NSD(y) LeSD=3.6nm w/ Lext=12nm & sL=6nm LeSD=2.4nm w/ Lext=18nm & sL=12nmVDS=1.0V 0.00.20.40.60.81.01.2 VGS [V] 0.0 0.5 1.0 1.5 2.0IDS [mA/ m m] Abrupt NSD(y) LeSD=3.6nm w/ Lext=12nm & sL=6nm LeSD=2.4nm w/ Lext=18nm & sL=12nmVDS=1.0V(a)(b)

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115 withLext=12nmand sL=6nmeffectivelycontrolsSCEsandthus increasesVt,whileitdegradesIonsomedueto D RSD.Fortheunderlap designwithlongerLext(=18nm)andhigher sL(=12nm),duetosmallVtviatheS/Ddopantsinthechannel,i.e.,theeffectofQB/Cox,andthesmall subthresholdswing(S),UFDG-predictedIonishigherthanthatofabruptNSD(y)case.Here,notethattheVtreductioncausedbyQB/Coxis~50mV asdiscussedinsubsection5.3,andthustheaverageS/Ddopantdensityin thechannelisestimatedtobeNB~1.2 1018/cm3.Sincethevolumeofthe channelisVch=[Leff(=22.8nm) wSi(=9nm) Weff(=5wSi=45nm)],the actualnumberofdopantsinthechanneliscalculatedtobeNB Vch=11. Therefore,fortheunderlapdesignwithhigh sLtherandomdopanteffect ( D NB)inthechannelseemstobetolerable.Note,however,thatifthe actualdopantcountinthechannelweremuchbelow10,thedesignwould have to be refined. Further,thesubthresholdgatecapacitance(CG)forthetwo underlappeddevicesismuchlessthanthatoftheabrupt-NSD(y) counterpartasclearlyshowninFig.5.13.And,becauseofthisreducedCG, theunderlappeddesignsshowspeedsuperiorityovertheabrupt-NSD(y) counterpartasshowninFig.5.14.TheUFDG-predictedspeedbenefitof usingtheunderlapismorethan23%.Thisresultisconsistentwiththat inchapter4,whichshowedthattheunderlapisquiteeffectiveinreducing thefringecapacitanceandthustheCMOSdelay.Betweenthetwo underlapdesigns,thelongersLdesignshowsonly @ 5%shorterdelays.

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116 Figure 5.13UFDG-predictedgatecapacitance(CG)versusgatevoltage forthethree18nmDGFinFETdesignsdefinedinFig.5.12. -0.20.00.20.40.60.81.01.2 VGS [V] 0.0 0.2 0.4 0.6 0.8 1.0 1.2CG [fF/ m m] VDS=50mV Abrupt NSD(y) LeSD=3.6nm w/ Lext=12nm & sL=6nm LeSD=2.4nm w/ Lext=18nm & sL=12nm

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117 Figure 5.14UFDG/Spice3-predictedpropagationdelaysperstageversus supplyvoltageof9-stageunloadedCMOS-inverterring oscillatorscomprisingthreedifferent18nmDGFinFET designs defined in Fig. 5.12. 0.91.01.1 VDD [V] 1.5 2.0 2.5 3.0 3.5 4.0tpd [ps] Abrupt NSD(y) LeSD=3.6nm w/ Lext=12nm & sL=6nm LeSD=2.4nm w/ Lext=18nm & sL=12nm

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118 However,asshowninFig.5.15,whichrepresentstheUFDG/Spice3predictedloadedROdelays( tpd)versusloadcapacitance(CL)ofthethree different18nmDGFinFETdesignsdefinedinFig.5.12,thespeedbenefit ofthelongersLdesignisenhancedwithincreasingCL.Thisisbecause, when sLislongtogetshortLeSD,Ioniscomparableto(orevenhigher than)thatoftheabrupt-NSD(y)deviceduetolargeVtshiftbyQB/Coxin (5.1),whiletheparasiticcapacitanceinweakinversionisstillsmalldue tothedefinedunderlap.Ontheotherhand,thespeedbenefitoftheshortsLdesignovertheabrupt-NSD(y)counterpartisdegradedwhenCLincreases,duetosmallerIon.So,usinglong sLintheunderlapdesigncan beagooddesignapproachtokeepIonhighandfringecapacitancesmall, thusimprovingthedevicespeed.However,asimpliedinFig.5.1,Vtofthis longersLdesignseemstobeverysensitiveto D LeSDorLext/ sL.Therefore, theapplicabilityofthedesignwithlongLextand sLmightbelimitedby thesensitivityissue.Thus,inthenextsubsection,thesensitivityissueof thisoptimalDGFinFETdesignusinglong sLwillbediscussedinmore detail. 5.5.2 Sensitivity to Straggle Asmentionedinthesubsection5.3,VtisdefinedbybothSCEs andtheS/Ddopantsinthechannel,andthusverysensitiveto sLvariationswhen sLislong.So,inthissubsection,thesensitivityissue withregardtotheprocessinduced DsLwillbediscussedforthetwoDG FinFET designs with the underlap defined by long and short sL.

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119 Figure 5.15UFDG/Spice3-predictedloaded(CLoneachstage)CMOS ring-oscillatordelaysversusCL,atVDD=1.0V,forthethree different 18nm DG FinFET designs defined in Fig. 5.12. 0.00.10.20.30.40.5 CL [fF] 1.0 3.0 5.0 7.0 9.0 11.0tpd [ps] Abrupt NSD(y) LeSD=3.6nm w/ Lext=12nm & sL=6nm LeSD=2.4nm w/ Lext=18nm & sL=12nm

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120 Fig.5.16comparestheIonandCGvariationsoftheunderlapped DGFinFETwithlong sLtothoseofthecounterpartwithshort sL,when theprocess-induced sLvariationisassumedtobe 1nm.Notethat DsLof 1nmcorrespondsto 8.3%and 16.7%variationsfrom sL=12nmand 6nm,respectively.AsshowninFig.5.16(a),dueto DsL,Ionofthe underlappeddevicewithlonger sLvariesfrom+12%to-8%,whichis muchlargerthanthose( 5%)ofthedesignwithshorter sL.Ontheother hand,CGvariationsofthetwounderlappeddevicearecomparable,as showninFig.5.16(b).Here,itshouldbenotedthat D CGand D Ionvaryin thesamedirection.SincethedevicespeedcorrelateswithCV/I,andCand Ihere,i.e.,CGandIon,varyinthesamedirection,theeffectsof DsLonthe devicespeedshouldnotbesosignificant.Indeed,forthetwounderlapped designs,UFDG-predicted Dtpdismuchsmallerthan D Ionand D Cfasshown inFig.5.17(a).However,becauseofthelargevariationsofIon, Dtpdofthe longersLdesignreachesto @ 11%whenthereisheavyload;seeFig. 5.17(b).FortheshortersLdesign,thedelayvariationsfortheloadedcase aremuchlessthanthatofthelongersLdesign.Therefore,withregardto thedevicespeedissue,theoptimalunderlapforDGFinFETdeviceshas tobedefinedbythetrade-offbetweenthedeviceperformanceandthe sensitivity to the process-induced parameter variations. 5.6 Summary UsingMediciandUFDGsimulations,weconfirmedthatthe underlapisquiteeffectiveincontrollingSCEsandthusincreasingVtfor

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121 Figure 5.16UFDG/Spice3-predictedsensitivitycomparisonofthetwo underlappedDGFinFETdesignstothevariationof sL;(a) UFDG-predicted D Ionand(b)Medici-predicted D CGinweak inversion with the variation of sL.(a) -1.0 -8.3/-16.7% -0.5-4.2/-8.3%0 0 0.54.2/8.3%1.0 8.3/16.7%DsL [nm] DsL [%] -10 -5 0 5 10 15D Ion [%] -1.0-0.500.51.0DsL[nm] -10 -5 0 5 10D CG [%] Lext=18nm & sL=12nm Lext=12nm & sL=6nm Lext=18nm & sL=12nm Lext=12nm & sL=6nm(b)VDS=50mV

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122 Figure 5.17UFDG/Spice3-predictedsensitivitycomparisonofthetwo underlappedDGFinFETdesignstothevariationof sL;(a) UFDG-predictedunloadedand(b)loaded(CL=0.5fF) propagationdelayvariation( Dtpd)atVDD=1.0Vwith variation of sL. -1.0-0.500.51.0DsL [nm] -15 -10 -5 0 5 10Dtpd [%] CL=0.5fF -1.0 -8.3/-16.7% -0.5-4.2/-8.3%0 0 0.54.2/8.3%1.0 8.3/16.7%DsL [nm] DsL [%] -10 -5 0 5 10Dtpd [%] Lext=18nm & sL=12nm Lext=12nm & sL=6nm Lext=18nm & sL=12nm Lext=12nm & sL=6nm(a) (b)VDD=1.0V VDD=1.0V

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123 18nmFinFETs,whileitsacrificesIonduetotheincreaseRSD.However, forshortLeSDdefinedbylongLextand sL,VtisnotdefinedonlybySCEs butalsobytheS/DdopantsinthechannelviaQB/Cox,andthusvery sensitiveto DsL.Therefore,forSRAMapplications,whichrequirehighVt, theunderlaphastobedesignedwithlongLeSD,whichisdefinedbyshort Lextandlow sLduetothesensitivityissue.However,becauseoftheaccess time,severeIonreductionshouldbeavoided,andthustheoptimal underlapmustbedefinedbythetrade-offbetweenVtandIon.Ontheother hand,forthedevicespeedissue,becauseofthelargeVtshiftbyQB/Coxandsmall D RSDevenwiththeunderlap,IonofDGFinFETswiththe underlapdefinedbyhigh sLcanbecomparableto(orevenlargerthan) thatoftheabrupt-NSD(y)counterpartdevice,whilethegatecapacitance inweakinversionisreducedbytheunderlap.Thus,withthebenefitinIonandCGaffordedbythelong sL,wecouldenhancethedevicespeedbenefit intheunderlappeddevices,especiallywithheavyloads.However,because oftherelativelyseveresensitivityto DsL,theunderlapusinghigher sLshould be carefully designed.

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124 CHAPTER 6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK 6.1 Summary Thisdissertationaddressedperformanceprojections,design optimization,andphysicalmodelingissuesofnonclassicalnanoscale CMOS,includingfullydepletedSOIsingle-gate,double-gate,andtriplegateMOSFETs.Themajorcontributionsoftheresearcharesummarized as follows. Inchapter2,weprojecteddevicecharacteristicsandCMOS performancesofnonclassicalUTBCMOStechnologiesoptimizedattheLg=28nmnode,andcomparedthemwiththatofclassical,hypotheticalbulkSiCMOSatthisnode.WiththesameUTBthickness,theDGdeviceswere showntobefarsuperiortotheFD/SGdeviceswithregardtoSCEcontrol, andgenerallysuperiortoSGdevices,includingbulk-Sidevices,with regardtospeedbecauseofhigherdrivecurrents.However,aninteresting insightwasnoted.Forlightloadsandmoderatesupplyvoltages,a suboptimalFD/SGdesign(withthesametSi)forbothLOPandHP applicationswasfoundtoyieldspeedscomparabletotheDGdesigns,even thoughitscurrentdrivesaremuchloweranditsSCEsaremuchmore severe.ThissurprisingcomparisonwasshowntobearesultoftheFD/SG deviceshavingmuchlowerintrinsicgatecapacitance,whichisduetotheir thickBOXandhighersubthresholdswing,andhencedeferredonsetof

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125 significantinversion-chargecapacitance.AtlowerVDD,however,theDG designsaremuchfasterbecauseoftheirmuchhigherdrivecurrents. WhentheFD/SGCMOSdesignwasoptimizedbyaggressivescalingofthe UTBthickness,itshigh-VDDspeeddiminished(butwasstillcomparable tothatofDGCMOS)becauseofhighergatecapacitanceatintermediate gatevoltages,whileitslow-VDDspeedimprovedduetoincreasedcurrent. ComparedtothenonclassicalCMOS,thepredicteddelayofthebulk-Si/SG CMOSwasmuchlongerduetoitshighgatecapacitanceintheweak/ moderate-inversionregion,inadditiontothearealsource/drainjunction capacitance,andrelativelylowdrivecurrentlimitedbypolysilicon-gate depletion. Inchapter3,three-dimensionalnumericalsimulationsofDG andTGFinFETshavingundopedthinbodiesrevealedthesignificanceof bulk-inversioncurrentinIon,aswellasIoff,andtheconsequent insignificanceofthecommonlydefinedeffectivegatewidthin comparisonsofDGandTGcurrents.Infact,weinferredthattheproper WeffforDGFinFETsishSi,whichcorrelateswiththetotal(surfaceplus bulk)inversioncharge;whereasameaningfulWeffcannotbedirectly definedforTGFinFETs.Thenewinsightsrevealedhereinexplainwhy theDGFinFETprovidesnearlythesameIonastheTGcounterpartforfin aspectratiosassmallastwo,butespeciallyforhigherRfwhichis desirableanddoable.DuetotherelativelysmallincreaseinIonofTG FinFETs,overtheDGcounterpartswithmoderateRf,theadvantageofTG devicesingatelayout-areaefficiencyisnotsignificant.Theinsightsthus

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126 furthersolidifyournotion,basedinitiallyonWeff-impliedTGlayout-area inefficiency[Yan05](andonthefactthataTGFinFET,withathintop dielectricandmoderateRf,ismoredifficulttofabricatethanaDGFinFET [Mat05]), that the third top gate is neither desirable nor beneficial. Inchapter4,weshowed,with2-Dnumericaldevicesimulations, thattheparasiticfringecapacitancesinnonclassicalnanoscale MOSFETs,e.g.,DGFinFETs,areverysignificant,withimportantVGSdependencesduetothegate-source/drainunderlapthatinfactreduces thecapacitance.Withphysicalinsightsfromthedevicesimulations,we developedananalyticalmodelfortheparasiticcapacitance,including inner-andouter-fringecomponents,andaBOX-fringecomponentforFD/ SOIMOSFETs,allwithdependencesonVGSandontheunderlap structure.Themodelwasverifiedgenerallybythenumericalsimulations, andimplementedinourprocess/physics-basedcompactmodel(UFDG3.5).WithUFDGinSpice3,weshowed,viaring-oscillatorsimulations, thatreducingtheparasiticcapacitanceviaoptimalunderlapdesigncanbe quiteeffectiveinimprovingnanoscaleDGCMOSspeed,whichisbasically definedbyatrade-offregardingthecapacitanceandsource/drainseries resistance.Nonetheless,westresstheseverityoftheG-S/Dfringecapacitanceeffectonspeedshownbyoursimulations.Wefoundthatthis parasiticcapacitanceispredominantinlimitingnanoscaleDGCMOS speed, even when moderated by an optimal G-S/D underlap. Inchapter5,usingMedici/UFDGsimulations,weconfirmedthat theG-S/DunderlapisquiteeffectiveincontrollingSCEsandthus

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127 increasingVtforagivenDGFinFETstructure.However,forshortLeSDdefinedbylongLextandhigh sL,VtisnotdefinedonlybySCEsbutalso bytheS/DdopantsinthechannelviaQB/Cox.Therefore,forSRAM applications,whichrequireshighVt,theunderlaphastobedesignedwith longLeSD,whichisdefinedbyshortLextandlow sL.However,becauseof theaccesstime,severeIonreductionshouldbeavoided,andthusthe optimalunderlapmustbedefinedbythetrade-offbetweenVtandIon.On theotherhand,forthedevicespeedissue,wecanusehigh sLtogetshort LeSD.BecauseofthelargeVtshiftbyQB/Coxandsmall D RSDevenwiththe underlap,on-statecurrentcanbecomparabletothatofabrupt-NSD(y) FinFET,whiletheparasiticcapacitanceforweakinversionismade smallerbytheunderlap.Thus,withthebenefitinIonandCGaffordedby high sL,wecouldenhancethedevicespeedbenefitintheunderlaped devices,especiallywiththeheavyloads.However,becauseofthe relativelyseveresensitivityto DsL,theunderlapusinghigher sLshould be carefully designed. 6.2 Suggestions for Future Work Inchapter3,weshowedthatthereissignificancebulk-inversion currentinIon,aswellasIoff,forDGandTGFinFETswithundopedUTBs. Becauseofthisbulkinversion,thereareseveralinterestingfeaturesin thenonclassicaldeviceswithundopedbodies.Forexample,asintroduced inchapter3,theproperWeffforDGFinFETsishSi,whichcorrelateswith thetotal(surfaceplusbulk)inversioncharge.Also,becauseofthesmaller

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128 transverseelectricfieldintheundopedchannel,thecarriermobilityin thechanneltendstobehigherthanthatoftheconventionaldopedbulkSidevices.Finally,thebulkinversionreducesthegatecapacitance,and thusCGofDGFinFETstendstoreachCoxathighergatevoltages.Onthe otherhand,withregardtotheabnormalCGreductioninthesaturation region,whichisobservedinMedici[Med04]simulation,thebulkinversion canbeapossiblereasonasexplainedinappendixB.However,Taurus [Tau04]doesnotpredictthisabnormalityofCG.Therefore,itisworth examiningthedifferencebetweenMediciandTaurus,thatcausesthe differentpredictionsforthesaturationCG,andverifyiftheCGreduction isarealeffectornot.Also,iftheCGreductionisreal,appendixBshould be re-evaluated as a possible explanation for that. Intheunderlapstudy,wehaveassumedthatthesource/drain seriesresistance(RSD)isnotafunctionofVDS.ThisistruewhenLeSDis short.However,whenLeSDislong,RSDisseverelyaffectedbythedrain voltage.Since,forSRAMapplications,thepull-downtransistorandthe accesstransistorareworkingindifferentregionofoperation,thisVDSdependenceofRSDisquiteimportant.Forexample,whenthezero-state voltageisdefinedinSRAM,thepull-downtransistorisoperatinginthe linearregion,whiletheaccesstransistorisinthesaturationregion.So, withouttheproperanalyticalmodel,wecannotpredicttheexactzerostatevoltageandthusread-SNM.Therefore,theVDS-dependenceofRSDshouldbestudiedtoshowtherangeofLeSDwhichcanbeusedwithoutthe

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129 concernaboutthisVDS-dependence,and,ifnecessary,aVDS-dependent RSD model should be developed. Also,asshowninchapter5,theS/Ddopantsinthechanneltend toreduceVtofnonclassicalundoped-UTBdeviceswhen sLishightoget shortLeSD.ThiseffectwasnotimportantintheSRAMapplicationssince, forhighVtandread-SNM,longLeSDvialow sLisbeneficial.However, withregardtothedevicespeedissue,high sLseemstoyieldhigherIon, whichisbasicallyenabledbythelargeVtshiftcausedbytheS/Ddopants inthechannel.ThemainproblemhereisthatUFDGdoesnotincludeany physicalparameterormodeltoaccountforthisVtshift.NotethattheVtversus sLstudy,viaUFDG,inchapter5hasbeendonebymodulatingthe workfunctionofthegateelectrodetoproperlyaccountfortheVtshiftby theS/Ddopantsinthechannel,withtheaidofMedici.Therefore,with regardtotheS/Ddopantsinthechannel,aproperphysicalparameteror model is required for UFDG to predict Vt characteristics accordingly. EventhoughtheaccesstimeiscriticalindefiningiftheSRAM readorthewriteoperationissuccessfullycarriedoutornot,a comprehensivestudyhasnotbeendoneinthisdissertationmainlydueto theuncertaintyofthebit-linecapacitance.Inchapter5,thereadorthe writeoperationfailurehasbeenavoidedbydefiningtheoptimalunderlap, whichdoesnotreduceIonmuch,withtheassumptionthatIonofthe abrupt-NSD(y)deviceislargeenoughtomaketheSRAMcelloperate properly.However,becauseofthedifficultyincontrollingthegateleakage

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130 currentwithoutthehighk gatedielectricmaterialandtheincreasedS/D seriesresistanceduetotheextremelythinSOIfilm,theIonrequirement tendstobemoredifficulttomeetwiththedevicescaling.Thus,theaccesstimesimulation,withthepropervalueofthebit-linecapacitance,seems tobecomemoreimportant,andthusshouldbedonetocomplementthe SRAM cell study.

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131 APPENDIX A UPGRADES/REFINEMENTS OF UFDG CHARGE MODEL A.1 Modeling of Junction Depletion Charge Thedepletionregionchargeinthebody-source(/drain)junction, which defines the reverse-bias junction capacitance, is defined as ,(A.1) where,NBodyandtSidependonthestructureofthedevice.Thedepletion width at the neutral body/source junction, wdep, is defined as ,(A.2) where ,(A.3) ,(A.4) and .(A.5) NSisthedopingdensityinthesourceandnbisthecarrierdensityinthe extension,wheregatebiasdependentmodulationisnegligible,andfixed Q Sdep q W eff N Body t Si w dep = w dep w dep0 1 V BSeff V bi ---------------------- = w dep0 2 e Si V bi qN Body --------------------= V BSeff V bi V t 1 V bi V BS V t --------------------------exp + ln = V bi V bi0 SCEB () V t N S n b ------ln =

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132 at1019cm-3.SCEBisauserdefinedmodelparameterinUFDGandcan beapositivevaluebetween0and1[Cho06].Thebuilt-inpotentialVbi0in (A.5) is assumed to be ,(A.6) whereniistheintrinsiccarrierdensityatagiventemperature.Similar equationsforthedepletionchargeatthebody/drainjunction,QD,dep, require an effective VBD, i.e., VBD,eff. QS,depandQD,depareaddedtothetotalbodychargeinUFDG,and -QS,depand-QD,depareaddedtothetotalsourceanddraincharge, respectively, for charge neutrality. Therefore, we have ,(A.7) ,(A.8) and .(A.9) Here,itshouldbenotedthatthemodeleddepletioncharge,QS/ D,dep,atthejunctionbetweenthesource/drainandthebodyisafew electroncharges,whichareabouttwoordermagnitudelessthanthe fringecapacitancecharge[Kim06].Thus,wecanneglectthisjunction depletionchargeintermsofitsamount.However,thismodelseemstobe necessaryinUFDGforthemodelstability.Therefore,eventhoughQS/ D,depdoesnotcontributetoQBody,thismodelisimplementedintoUFDG. V bi0 E g 2 ------V t N Body n i -----------------ln + @ Q S Q S Q Sdep ,= Q D Q D Q Ddep ,= Q Body Q Body Q Sdep Q Ddep ++ =

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133 A.2 Upgrading of Electron Charge Model in Weak Inversion The diffusion length, Le, in the channel is defined as [Yeh05] ,(A.10) with ,(A.11) and ,(A.12) whereLeff=Lg+Les+Ledintheweakinversionregionand Ymin(x)isthe minimumpotentialinthebody.In(A.11)and(A.12),itisassumedthat Y inthebodynearthesourceanddrainisalinearfunctioninydirectionas showninFig.A.1.Thebuilt-inpotential,Vbi,atthevirtualsource-body boundaryisexpressedin(A.5).Betweeny=Ls/2andy=Ls/2+Leforagiven x,weassumeaconstant Y ,i.e., Ymin.Thisassumptiontendstomakethe potentialand,consequently,thetotalcharge(Qn)inthebodyunderestimated. However, the predicted error is negligible since Qn e(Y). Thetotalcharge,Qn,inthebodycanbeobtainedbythree partitionedchannelchargesiny,i.e.,QnB,QnS,andQnDasdefinedin Fig.A.1.Eachchargeiscomposedoffourpartitionedchannelchargeinx, assuminglinearvariationsofpotentialinxbetween Ymin,(xj)and Ymin,(xj+1)withj=0,1,2,and3.Thepartitionedchannelchargeinthe L e L eff L s L d L s 2V bi Y min x () [] y Y xy () y0 = ---------------------------------------------@ L d 2V bi Y min x () V DS + [] y Y xy () yL eff = ----------------------------------------------------------------@

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134 LefftSiLs/2Le+Ls/2+Ld/2Ld/2 y x VbiVbi+VDS Ymin(x) Y (y) = linear at a given x ymin Ymin,(xj) 0QnSjQnBjQnDj j=0, 1, 2, and 3 Ymin,(xj+1) FigureA.1Representativepotentialvariationsinyatagivenxandcorresponding linear approximations.

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135 middle of the body, QnBjwith j=0, 1, 2, and 3, is given by .(A.13) And,thepartitionedcharge,QnSj,inthebodynearthesourceis expressed by (A.14) (A.15) with YS(y=0) @ Vbiand YS(y=Ls/2) @ ( Ymin,(xj)+ Ymin,(xj+1))/2;j=0,1,2and3. WegetthesimilarexpressionwithregardtoQnDj,thepartitioned channelchargeinthebodynearthedrain,byreplacingLs/2and YS(y=0) @ VbiwithLd/2and YS(y=Leff) @ Vbi+VDS,respectively.Thetotal body charge, Qn, is then expressed by ,(A.16) wherej=0,1,2,and3.And,finally,thefrontgatetotalchargeis expressed as ,(A.17) with ,(A.18) where, FMSisthework-functiondifferencebetweenthefrontgatemetalQ nBj qW eff t Si n i 2 4N Body ----------------------------------V t L e L s 2 L d 2 ++ () e Y minxj1 + () V t () e Y minxj () V t () Y minxj1 + () Y minxj () -------------------------------------------------------------------------------------------------------------------------------------------------------------------@ Q nSj qW eff t Si n i 2 4N Body ----------------------------------e q Y S y () kT () 0 L s 2 dy @qW eff t Si n i 2 8N Body ----------------------------------= V t L s Y S yL s 2 = ()Y S y0 = () ------------------------------------------------------------------e Y S yL s 2 = () V t e Y S y0 = () V t Q n Q nBj jQ nSj jQ nDj j++ = Q Gf Q Gf Q n Q Gf C oxf W eff L e V GfS Y minx0 () F MS () =

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136 andthebody.Then,thebackgatetotalchargecanberepresentedbythe charge neutrality, i.e., ,(A.19) with ,(A.20) ,(A.21) and ,(A.22) where Qff and Qfb are the fixed frontand back-oxide charges. However,duetotheexistenceofthefringecapacitancecharge [Kim06],whichisaboutoneordermagnitudelargerthantheelectron chargeinweak-inversionregion,thismodeldoesnotseemtobe necessary in UFDG. So this model is not implemented in UFDG. Q Gb Q s Q d Q Gf Q b Q ff Q fb +++++ () = Q s Q nBj j 2 ------------------------Q nSj j+ = Q d Q nBj j 2 ------------------------Q nDj j+ = Q b W eff L eff qN Body t Si () =

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137 APPENDIX B DG MOSFET GATE CAPACITANCE IN SATURATION REGION Medici-predictedCG-VGScharacteristicsshowninFig.B.1 provideaninteresting,novelfeatureofsymmetricaldouble-gate(SDG) MOSFETswithundopedUTBs,i.e.,unusualgatecapacitance(CG) reductionatsaturationregion.Becauseofthechannellength modulation,CGissmalleratsaturationthanthatatlinearregionas representedinFig.B.1.WithincreasingVGSathighVDS,thechannel lengthmodulationislesseffectiveandthusCGshouldincreasewith increasingVGSasitdoesforlowVDS.However,asshowninFig.B.1,CGfor strong inversion at high VDS is decreasing with increasing VGS. However,Taurus[Tau04]simulationsdonotshowthis abnormality,andhencetheabnormalCGreductioninsaturationregion mayormaynotbereal.Therefore,morestudy,withasimulatorthat morephysicallymodelsthecarriertransportinthechannel(which governsCGathighVDS),isneeded.Inthisappendix,we,believingthe Medicisimulationresult,suggestapossibleexplanationforthisunusual CG reduction in saturation region. OnepossibleexplanationisbasedonVGS-dependentinnerfringecapacitance(Cif),whichisnegatedatstronginversionbythe inversionchargescreening.AthighVDS,duetothelessinvertedcharges

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138 Figure B.1Medici-predictedgatecapacitanceatlowandhighVDSversusgatevoltagefortheLg=18nmDGnMOSFET (tSi=9nm,tox=1nm,midgapgate)withoutG-S/Dunderlap and outer fringe capacitance, i.e., Cof=0 by tg=0. -0.20.00.20.40.60.81.01.2 VGS [V] 0.0 0.2 0.4 0.6 0.8 1.0 1.2CG [fF/ m m] VDS=50mV VDS=1.0V

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139 nearthedrain,Cifmightnotbecompletelyscreenedoutatsaturation region.WithincreasingVGS,inversionelectronsincreaseandthusCifcanbeeffectivelyscreenedoutbytheinversion-chargescreening. Consequently,Cif(andthusCG)candecreasewithincreasingVGS. However,Medici-predictedinverted-electrondensityofSDGdevicesin Fig.B.1ismorethan~1018/cm3nearthedrain,whichseemstobelarge enoughtoscreenoutCif.Inaddition,theobservedCGreductionismore severeforthedevicewiththinnertSi,whichhassmallerCif[Kim06],and evenlargerthanthetotalCifforthedevicewithtSi=3nmasshowninFig. B.2.Therefore,wecaninferthatCifisnotthereasonforthenegativeCGslope at saturation region observed in Fig. B.1. AnotherpossiblereasonfortheunusualCGreductionat saturationregionisDICE,whichis2-Deffectandthuslosesitseffect,i.e., chargeenhancement,withincreasingVGS.Tocheckthiseffect,a relativelylong-channeldevice(Lg=0.1 m m)withverythintox(=1nm)and tSi(=10nm),inwhich2-Deffectcanbeignored,issimulatedwithMedici forCG-VGScharacteristics.InFig.B.3,thesaturation-CGofthisdeviceis comparedtothoseofotherdeviceswiththickertSi(=50nm)orhigherbody doping(5x1018/cm3).WeseeforthisdevicethatCGisstilldecreasingat saturationregioneventhoughDICEor2-Deffectisvirtuallyeliminated withextremelythintoxandtSi.Rather,CGreductioncouldbenegatedfor thedevicewiththickertSiandcompletelyremovedbyhighbodydopingas

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140 Figure B.2Medici-predictedsaturationgatecapacitanceversusgate voltagefortheLg=18nmDGnMOSFET(tox=1nmand midgapgate)withvariousSOIfilmthickness;DGdevices areassumedtohaveabruptNSD(y)withouttheG-S/D underlap. -0.20.00.20.40.60.81.0 VGS [V] 0.0 0.2 0.4 0.6 0.8 1.0CG [fF/ m m] tSi=3nm tSi=6nm tSi=9nm VDS=1.0V

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141 Figure B.3Medici-predictedsaturationgatecapacitanceversusgate voltageforthreedifferentLg=0.1 m mDGMOSFETswith tox=1nm;devicesareseparatedfromeachotherbytheSOI film thickness and/or the body doping. 0.00.20.40.60.81.01.21.4 VGS [V] 0.0 1.0 2.0 3.0 4.0 5.0CG [fF/ m m] tSi=10nm, Undoped Body tSi=50nm, Undoped Body tSi=50nm, Nbody=5E18/cm3VDS=1.0V

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142 showninFig.B.3.Theseresultsimplythatthesaturation-CGreductionin Fig. B.1 is not caused by DICE. TherealexplanationcanbeinducedfromFig.B.4,whichshows theelectron-densityprofileacrosstheSOIfilmforthreedifferentdevices inFig.B.3.FromFigs.B.3andB.4,itisobviousthatCGreductionis moresevereforthedevicewithhigherinversionchargesinthebulkand canbenegatedbyeliminatingthebulkinversioncharges.Thus,wecan inferthatthenegativeCGslopeobservedinFig.B.1isfundamentally basedonthebulk-inversion[Kim05b],whichisastrongfunctionoftSiand the body doping. Basedonthisconclusion,wecanexplaintheunusualCGreductionatsaturationregionasfollows.FortherelativelylowVGSat highVDS,thebulkinversioncharge(Qinv(Bulk))isdominant,whilethe surfaceinversioncharge(Qinv(Sur))willbemoredominantwithincreasing VGS.WhenQinv(Sur)isgettinglarger,theincreasingrateofQinv(Bulk),i.e., Cinv(Bulk),shouldbegettingsmallerduetothesurfacechargescreening. Then,theincreasingrateofthetotalinversioncharge(Qinv),i.e.,Cinv,will decreasesinceQinvisdefinedbythesumofQinv(Sur)andQinv(Bulk). Consequently,basedonthedefinitionofthecapacitance,i.e.,C=dQ/dV, theinversioncapacitance(Cinv=dQinv/dVGS)canhaveanegativeslopeat saturationregionasexemplifiedinFig.B.5.NoteherethatCGreduction isobservedonlyforhighVDS.Thisisbecausebulkinversioncanbea

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143 Figure B.4Medici-predictedelectrondensityprofileacrosstheSOIfilm for three different devices in Fig. B.3. 0.00.20.40.60.81.0 x/tSi 101010111012101310141015101610171018101910201021n [cm-3] tSi=10nm, Undoped tSi=50nm, Undoped tSi=50nm, Nbody=5E18/cm3 VDS=1.0V VGS=1.0, 1.2, 1.4V

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144 Figure B.5Integratedinversioncharge(Qinv)aty=Lg/2andVDS=1.0V, anditsdifferentiation(dQinv/dVGS),whichisreflectingCinv, oftheDGdeviceinFig.B.1,i.e,Lg=18nmDGnMOSFET with tox=1nm and tSi=9nm. 0.00.10.20.30.40.50.60.70.80.91.01.1 VGS [V] 0 5 10 15 20 25 30 35 40Qinv [fC/ m m2] or Cinv [fF/ m m2] Qinv Cinv VDS=1.0V

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145 predominanteffectwhenVDSishighenoughtolowerthesurfacepotential and increase the potential in the bulk. TosupportourexplanationthatCinvdecreasesduetothe decreasingCinv(Bulk),theinvertedelectrondensity(n)andthe differentiationofit,i.e.,dn/dVGS,atthesurface(x=0ortSi)andthebulk (x=tSi/2)areplottedinFig.B.6forthedeviceinFig.B.5.Noteherethat thetotalinversionchargeQinvisdefinedbyqntSiandthusCinvis proportionaltodn/dVGS.Then,Cinv(Sur)andCinv(Bulk)canbereflectedby dn(x=0ortSi)/dVGSanddn(x=tSi/2)/dVGS,respectively.InFig.B.6,we clearlyseethatdn(x=tSi/2)/dVGShasanegativeslopebeyondaboutVGS=0.5V.Thus,sodoesCinv(Bulk)eventhoughVGS-dependenceofthe surfaceinversionlayerthicknessisnotaccountedhere.Consequently,we confirmthattheincreasingrateofbulkinversionchargeisdecreasing withincreasingVGSduetotheinversionchargescreening.Then,since CG for SDG devices can be expressed by [Kim01] (B.1) withCinv=Cinv(Sur)+Cinv(Bulk),CGcanhavethenegativeslopeshownin Fig.B.1,followingCinv(Bulk)reflectedbydn(x=tSi/2)/dVGS.Here, Cinv(Sur)andCinv(Bulk)areassumedtobeinparallelasshowninFig.B.7 becauseboththesurfaceandthebulkinversion-layerareconnectedto the source (or ground). C G 2C ox 1 C ox C inv -----------+ --------------------=

PAGE 159

146 Figure B.6Medici-predictedsurfaceandbulkelectrondensity(n)at y=Lg/2andVDS=1.0V,anditsdifferentiation(dn/dVGS)ofthe DGdeviceofFig.B.1;Cinv(Sur)andCinv(Bulk)isreflectedby dn(x=0 or tSi)/dVGS and dn(x=tSi/2)/dVGS, respectively. 0.00.10.20.30.40.50.60.70.80.91.01.1 VGS [V] 0.0 0.1 0.2 0.3 0.4 0.5n (x1020) [cm-3] x=0 or x=tSi x=tSi/2 0.00.10.20.30.40.50.60.70.80.91.01.1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4dn/dVGS (x1020) VDS=1.0V dn/dVGSn

PAGE 160

147 Figure B.7EquivalentcircuitsofaDGMOScapacitorinthestrong inversionregion;Cinv(Sur)andCinv(Bulk)areinparallelhere becauseboththesurfaceandthebulkinversion-layerare connected to the source (or ground). CoxfCoxbCinvf-Qsb-QsfQsf CinvbQsb VgfVgb CoxfCinv(Sur)-Qsf Vgf Cinv(Bulk)Qinv(Bulk)Qsf=Qinv(Sur)+Qinv(Bulk) Qinv(Sur)In Strong InversionCinvf=Cinv(Sur)+Cinv(Bulk)

PAGE 161

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154 BIOGRAPHICAL SKETCH Seung-HwanKimwasborninSeoul,Korea.HereceivedtheB.S. andM.S.degreesinmetallurgyandmaterialssciencefromHanyang University,Ansan,Gyeonggi-Do,Korea,in1995and1997,respectively.In 2002,hereceivedtheM.S.degreeinelectricalandcomputerengineering fromtheUniversityofFlorida,Gainesville.Since2002,hehasbeen pursuingaPh.D.degreeinelectricalengineeringattheUniversityof Florida, Gainesville. Inthesummerof2002and2004,hewasaninternattheProcess DevelopmentTeamandtheTCADTeam,respectively,ofSamsung Electronics,Korea.In2005,hewasselectedasoneoftherecipientsofthe KoreanGraduateStudentResearchAwardfromtheUniversityof FloridasKoreanstudentscholarshipandloanfund.Hisresearchinvolves simulation,analyses,design,andphysicalmodelingofnon-classical nanoscaleCMOS,suchasfullydepletedSOIsingle-andmulti-gate devices.


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Copyright Date: 2008

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NONCLASSICAL NANOSCALE CMOS: PERFORMANCE
PROJECTIONS, DESIGN OPTIMIZATION, AND PHYSICAL MODELING















By

SEUNG-HWAN KIM


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY


UNIVERSITY OF FLORIDA


2006





































-To-

My parents














ACKNOWLEDGMENTS

I would like to express my sincere appreciation to the chairman

of my supervisory committee, Professor Jerry G. Fossum, for his guidance

and support throughout the course of this work. His great knowledge in

semiconductor physics motivated my devotion to the field of

semiconductor devices. He was a role model for me, put things in proper

perspective, and contributed to my positive attitude. I would also like to

thank the members of my supervisory committee (Professors Robert Fox,

Jing Guo, and Susan Sinnott) for their guidance and interest in this work.

I am grateful to Samsung Electronics, Freescale Semiconductor,

and the National Science Foundation for their financial support and the

useful information. I would also like to thank fellow students Ji-Woon

Yang, Vishal Trivedi, Weimin Zhang, Murshed Chowdhury, Zhichao Lu,

Siddharth Chouksey, and Shishir Agarwal for their insightful and

technical discussions and friendships. Also, I thank all of the friends who

made my years at the University of Florida such an enjoyable chapter of

my life.

I must express heartfelt thanks to my mother (Kyung-Lim Lee),

my sisters (Eun-Kyung, Yeon-Jung, and Hee-Jung), and my brother-in-

law (Dong-Ju Park) for their constant encouragement, support, help,

sacrifice, and love throughout my studies.















TABLE OF CONTENTS

page


ACKN OW LED GEM ENT ...................................................................... iii

LIST OF TABLES ....................................................... ......................vi

LIST OF FIGU RES ..................................................... .....................vii

KEY TO ABBREVIATIONS ...................................................................x

A BSTRA CT ......................................................... ...........................xii

CHAPTER

1 IN T R O D U C T IO N ................................................................ ........... 1

2 NONCLASSICAL CMOS: POTENTIAL NONCLASSICAL
TECHNOLOGIES VERSUS A HYPOTHETICAL BULK-SILICON
TE C H N O LO G Y .................................................................................. 8

2 .1 In trodu action .............................................................................. .. 8
2.2 UFDG, UFPDB, and Simulation Conditions............................... 10
2.3 Immunity to Short-Channel Effects........................................... 12
2.4 28nm Device Design................................................................. 14
2.5 CMOS Performance Projections..................................................22
2.6 Thin-BOX FD/SOI CMOS.........................................................32
2 .7 S u m m ary ................................................................................. .. 3 5

3 BULK INVERSION IN FINFETS AND IMPLIED INSIGHTS ON
EFFECTIVE GATE WIDTH ......... ..................................................37

3.1 In trodu action ............................................................................ ... 37
3.2 N um erical Sim ulations ..............................................................38
3.2.1 I-V Characteristics of DG and TG FinFETs......................40
3.2.2 Electric-Field Fringing Effects..........................................43
3.2.3 Bulk Inversion.......................................... .................. 43
3.3 Implied Insight of Bulk Inversion...............................................50
3.3.1 Proper Effective Gate Width .............................................50
3.3.2 Layout Area.............................................. ..................52
3.4 Sum m ary ....................................................................... ....... 55









4 MODELING AND SIGNIFICANCE OF FRINGE CAPACITANCE IN
NONCLASSICAL CMOS DEVICES WITH GATE-SOURCE/DRAIN
U N D E R LA P ........................................................................... ........... 57

4.1 Introdu action .............................................................................. 57
4.2 Physical Insights from Numerical Simulations ..........................58
4.2.1 Inner and Outer Fringe Capacitance ...............................58
4.2.2 BOX Fringe Capacitance in FD/SOI MOSFETs ...............61
4.3 Analytical M odeling ....................................................................64
4.3.1 W eak Inversion ................................. ............................. 69
4.3.2 Strong Inversion............................................ ................. 72
4.4 M odel V erification.................................. .................................. 72
4.5 Model Implementation in UFDG (Ver. 3.5)...............................74
4.6 M odel Applications.......................................... .....................76
4.7 Sum m ary ........................................... ......... ................ ........... 84

5 DOUBLE-GATE FINFETS WITH GATE-SOURCE/DRAIN UNDERLAP:
APPLICATIONS ON SRAM CELL AND DESIGN OPTIMIZATION FOR
D EV ICE SPEED ..................................................................... .......86

5.1 In trodu action ............................................................................. 8 6
5.2 DG FinFETs without Underlap ...................................... ....88
5.3 Threshold Voltage Modulation by Underlap...............................90
5.4 Applications on SRAM Cell........................................................98
5.4.1 SRAM Cell Design............................................................ 98
5.4.2 Sensitivity Issue in SRAM Cell.................................... 103
5.4.3 SRAM Cell Scaling ......................................................... 108
5.5 D evice Speed Issue............................................................. .... 111
5.5.1 U sing Long Straggle..................................................... .. 111
5.5.2 Sensitivity to Straggle.................................................... 118
5.6 Sum m ary..................................................................... ....... 120

6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK............... 124

6.1 Sum m ary .................................................... ............................ 124
6.2 Suggestions for Future Work..................................................... 127

APPENDIX

A UPGRADES/REFINEMENTS OF UFDG CHARGE MODEL.......... 131

A. 1 Modeling of Junction Depletion Charge ................................ 131
A.2 Upgrading of Electron Charge Model in Weak Inversion......... 133

B DG MOSFET GATE CAPACITANCE IN SATURATION REGION ... 137

R E FE R E N C E L IST ............................................................................148

BIOGRAPHICAL SKETCH...................... .......................................154















LIST OF TABLES


Table page


5.1 UFDG/Spice3-predicted sensitivity to the variation of straggle, fin
width, and the channel length.............................. 107














LIST OF FIGURES


Figure page


2.1 UFDG-predicted threshold voltage roll-off and DIBL ............ 13

2.2 UFDG-predicted current-gate voltage characteristics ............ 16

2.3 UFDG-predicted effects of separately varying toxf and toxb .... 18

2.4 UFDG/UFPDB-predicted current-gate voltage characteristics .... 20

2.5 UFDG/ and UFPDB/Spice3-predicted propagation delays ........ 23

2.6 UFDG/ and UFPDB/Spice3-predicted propagation delays ........ 24

2.7 UFDG- and UFPDB-predicted gate capacitances ............... 27

2.8 UFDG/Spice3-predicted loaded CMOS ring-oscillator delays ...... 31

2.9 UFDG/Spice3-predicted propagation delays .................... 34

3.1 Two-dimensional cross-section view of the DG FinFET .......... 39

3.2 Davinci-predicted current-voltage characteristics ............... 41

3.3 Davinci-predicted on-state current increase. ................... 42

3.4 Davinci-predicted on-state electron density along the top fin surface, at
the center of the channel ................................... 44

3.5 Davinci-predicted on-state electron density down the middle of the fin,
at the center of the channel ................................. 45

3.6 Medici-predicted electron density ............................ 49

3.7 Davinci-predicted on-state electron density at the middle of the top fin-
body surface, at the center of the channel. ................... .. 51

3.8 Calculated gate layout-area ratios of TG and DG FinFETs ....... 54









4.1 Medici-predicted low-frequency gate capacitance ............... 59

4.2 Medici-predicted low-frequency subthreshold gate capacitance .... 62

4.3 A schematic diagram of the gate-source/drain structure .......... 63

4.4 Basic two-plate model for the fringe capacitance ................ 65

4.5 Schematics of the G-S/D underlap structure for the weak inversion
analysis ................................. ............ 66

4.6 Illustration of how varying the actual lateral doping density profile
changes the weak inversion effective channel length ............. 68

4.7 Schematic of the SG FD/SOI MOSFET with G-S/D underlap ...... 71

4.8 UFDG- and Medici-predicted gate capacitance ................. 77

4.9 UFDG- and Medici-predicted current-voltage characteristics ..... 79

4.10 UFDG/Spice3-predicted propagation delays ................... 81

4.11 UFDG- and Medici-predicted gate capacitance ................. 82

5.1 UFDG-predicted threshold voltage ........................... 92

5.2 Threshold voltage reduction ............................... 94

5.3 UFDG-predicted on-state current and the increased source/drain
series resistance ............... ........................ 95

5.4 UFDG-predicted threshold voltage ........................... 97

5.5 UFDG-predicted read static noise margin versus the effective channel
length and schematics of 6-T SRAM cell. ...................... 99

5.6 UFDG-predicted butterfly curves ........................... 101

5.7 UFDG-predicted write-0 margin ............................ 102

5.8 UFDG/Spice3-predicted sensitivity of the optimal DG FinFET ... 105

5.9 UFDG-predicted read-SNM versus the physical gate length. ...... 109

5.10 UFDG-predicted butterfly curves ........................... 112









5.11 UFDG-predicted write-0 margin ............................ 113

5.12 UFDG-predicted current-gate voltage characteristics ........... 114

5.13 UFDG-predicted gate capacitance. .......................... 116

5.14 UFDG/Spice3-predicted propagation delays per stage........... 117

5.15 UFDG/Spice3-predicted loaded CMOS ring-oscillator delays ..... 119

5.16 UFDG/Spice3-predicted sensitivity comparison of the two underlapped
DG FinFET designs to the variation of straggle ............... 121

5.17 UFDG/Spice3-predicted sensitivity comparison of the two underlapped
DG FinFET designs to the variation of straggle ............... 122

A. 1 Representative potential variations in y at a given x and corresponding
linear approximations .................................... 134

B.1 Medici-predicted gate capacitance at low and high VDS ......... 138

B.2 Medici-predicted saturation gate capacitance ................. 140

B.3 Medici-predicted saturation gate capacitance ................. 141

B.4 Medici-predicted electron density profile across the SOI film..... 143

B.5 Integrated inversion charge and its differentiation ............. 144

B.6 Medici-predicted surface and bulk electron density and its
differentiation .......................................... 146

B.7 Equivalent circuits of a DG MOS capacitor in the strong inversion
region.................................................. .147

















ADG

BOX

CMOS

DG

DIBL

EOT

FD

GIDL

G-S/D

HP

LOP

LSTP

MOSFET

PD

QM

RO

SCE

S/D

SDG

SG


KEY TO ABBREVIATIONS

asymmetrical double-gate

buried-oxide

complementary metal-oxide-semiconductor

double-gate

drain-induced barrier lowering

equivalent oxide thickness

fully depleted

gate-induced-drain leakage

gate-source/drain

high performance

low operating power

low standby power

metal-oxide-semiconductor field-effect transistor

partially depleted

quantum mechanical

ring oscillator

short-channel effect

source/drain

symmetrical double-gate

single gate









SNM static noise margin

SOI silicon-on-insulator

SRAM static random access memory

TG triple-gate

UFDG University of Florida double-gate (model)

UFPDB University of Florida partially depleted SOI and bulk
MOSFET (model)

UTB ultra-thin body














Abstract of Dissertation Presented to the Graduate
School of the University of Florida in Partial Fulfillment
of the Requirements for the Degree of Doctor of
Philosophy

NONCLASSICAL NANOSCALE CMOS: PERFORMANCE
PROJECTIONS, DESIGN OPTIMIZATION, AND PHYSICAL MODELING

By

Seung-Hwan Kim

December 2006

Chairman: Jerry G. Fossum
Major Department: Electrical and Computer Engineering

This dissertation addresses performance projections, design

optimization, and physical modeling issues of nonclassical nanoscale

CMOS devices with UTBs, assessing their potential to become the basis of

the near-future mainstream semiconductor technology.

With regard to speed and immunity to SCEs, DG MOSFETs are

projected to be generally superior to the SG counterparts because of their

better gate control and higher drive currents. However, for light loads and

moderate supply voltages, a suboptimal SG FD/SOI MOSFET design for

both LOP and HP CMOS applications is found to yield speeds comparable

to the DG designs based on their much lower intrinsic CG, even though its

current drive is much lower and its SCEs are much more severe. Compared

to nonclassical CMOS designs, the delay of SG bulk-Si CMOS is predicted

to be much longer due mainly to its high CG in the weak/moderate

inversion region and relatively low drive current.









Relative values of Ion in undoped-UTB DG and TG FinFETs are

examined via 3-D numerical device simulations. The simulation results

reveal significant bulk inversion in the fin bodies, which limits the benefit

of the third (top) gate in the TG FinFET and which negates the utility of

the commonly defined effective gate width (Weff = 2hsi + wsi). Even the

concept of Weff for the TG FinFET is invalidated, but the proper Weff for

the DG FinFET is defined. Physical insights attained from the simulations

further solidify our notion, based previously on gate layout-area

inefficiency, that the third gate is neither desirable nor beneficial.

Parasitic G-S/D fringe capacitance in nonclassical nanoscale CMOS

devices is shown, using 2-D numerical simulations, to be very significant,

gate bias-dependent, and substantially reduced by well designed G-S/D

underlap. Analytical modeling of the outer and inner components of the

fringe capacitance is developed and verified by the numerical simulations;

a BOX-fringe component is modeled for SG FD/SOI MOSFETs. With the

new modeling implemented in UFDG, UFDG/Spice3 shows how nanoscale

DG CMOS speed is severely affected by the fringe capacitance, and how

this effect can be moderated by optimal underlap.

Based on the trade-off between SCEs and Ion, an optimal underlap,

which is defined by short Lext and oL, is defined for SRAM applications.

This optimization gives high Vt along with small loss of Ion. For the CMOS

speed issue, devices are optimally designed with long Lext and oL since the

latter tends to decrease Vt and thus keep Ion high, while the parasitic

capacitance in weak inversion decreases with the underlap. With regard

to the sensitivity issue, relatively long underlap, via short Lext and oL, is

generally beneficial for both the SRAM applications and the CMOS speed.


xiii














CHAPTER 1
INTRODUCTION

Scale-down of device dimensions in conventional bulk-silicon

CMOS technology has been a primary driving force of the semiconductor

industry development over the past three decades. The better performance

with the smaller size of the devices has been the basis of this development.

However, for conventional bulk-Si (and partially depleted (PD) SOI)

CMOS, continued scaling much beyond a physical gate length (Lg) of

-50nm [SemOl] is doubtful. This is because of severe short-channel effects

(SCEs), high off-state leakage currents, and unacceptably low Ion/Ioff

ratios. Indeed, controlling the body doping within very small dimensions,

which is required for SCE control, has been the most difficult

technological challenge to overcome for further scaling. Hence, there is a

growing interest in nonclassical fully depleted (FD) SOI single-gate (SG)

and double-gate (DG) MOSFETs with ultra-thin bodies (UTBs), which

have inherent suppression of SCEs. Their small intrinsic gate capacitance

in weak/moderate inversion and, especially for DG devices, the high Ion/

Ioff ratio stemming from the nearly ideal subthreshold gate swing imply

substantial CMOS speed superiority over the classical SG counterparts

[Fos02]. However, DG technology is complex; the DG FinFET [His98,

Hua99] is easiest to fabricate, but its proven utility is years away.









Contrarily, FD/SOI SG technology is less complicated; SOI UTBs and

metal gates are the main obstacles in its development [ChoOO].

Because of the technological complexities and difficulties

associated with DG CMOS, questions have been posed about the

performance advantage, relative to SG CMOS, that it can potentially

provide. For example, if the DG MOSFET gives twice the current, but with

twice the gate capacitance, then excessive device parasitics implied by the

complex technology might render inferior performance. Further, it has

been argued that SCEs in the bulk-Si SG MOSFET could be effectively

suppressed by super-halo channel doping such that bulk-Si CMOS could

actually be scaled down to 25nm channel lengths [Tau98]. However, this

argument is simulation-based, and there is uncertainty about the physical

modeling assumed [GeOl] and whether the assumed device structure

could even be fabricated [Tau98]. Nonetheless, given such a "hypothetical"

nanoscale bulk-Si CMOS technology, more detailed insights on the

relative performance potentials of nonclassical UTB CMOS would be

useful in deciding how and if they should be aggressively pursued.

In chapter 2, using our process/physics-based compact models

(UFDG [Fos03a] and UFPDB [Fos97]) in Spice3, we project device

characteristics and CMOS performances of nonclassical UTB CMOS

technologies (FD/SOI and DG) and classical, hypothetical bulk-Si

technologies optimized at the Lg = 28nm node. Comparisons of predicted

SCEs of nonclassical devices and speed (RO delays) of the nonclassical and

classical CMOS technologies are made, and good physical insights









regarding their relative characteristics are given. Namely, we first

compare asymmetrical and symmetrical DG, and FD/SOI SG devices via

simulations done with our process/physics-based compact model UFDG

[Fos03a, Fos04a], with emphasis on their immunity to SCEs. Then, using

UFDG, we optimally design these nonclassical devices for 28nm gate

length, and project their characteristics, including CMOS ring-oscillator

delays, which we compare with projections of a hypothetical 28nm bulk-Si

SG CMOS design derived, using our UFPDB compact model [Fos97], from

Taur et al. [Tau98]. Interpretations of the simulation results give good

physical insights on the nonclassical technologies, and indicate which

ones might best replace the classical technologies at nanoscale nodes of

the SIA ITRS [Sem01].

While the DG FinFET has become a leading device option for

future nanoscale CMOS, there is a technological limit to the aspect ratio

(Rf) of the Si-fin height (hsi) to the width (wsi). Since wsi must be ultra-

thin for good control of SCEs [Fos04b], this limit implies small effective

gate width (commonly assumed to be Weff = 2hsi) and, ostensibly, low Ion

per pitch. There is therefore interest in making the FinFET a triple-gate

(TG) transistor by activating the top gate, yielding, from a surface

inversion-charge perspective, Weff = 2hsi + wsi as is commonly assumed,

and alleviating, with a doped fin-body, the thin-wsi requirement [Doy03].

However, because of fin-corner effects [Fos03b] and technological

limitations [Tri03a], the fin-body must be left undoped, and so relaxation

of the thin-wsi (i.e., UTB) requirement for SCE control for the TG FinFET,









relative to that for the DG device, is minimal [Fos04b]. Nonetheless, the

larger Weff for the TG device could mean significantly higher Ion relative

to that of the DG FinFET even when wsi is thin for good SCE control.

In chapter 3, to check the benefit of activating the top gate of

FinFETs, relative values of Ion in undoped-body DG and TG FinFETs are

examined via three-dimensional (3-D) numerical device simulations

[Dav03]. Simulation results show that fin-body bulk inversion in strong

inversion limits the benefit of the third (top) gate in the TG FinFET, and

the commonly defined Weff is inappropriate as an indicator of Ion. Thus,

we define the proper Weff for the DG FinFET reflecting bulk inversion and,

based on this proper (re)definition of Weff, examine the gate layout-area

issue [Yan05] of FinFET CMOS.

Nonclassical nanoscale silicon CMOS devices, e.g., DG and SG

FD/SOI MOSFETs with undoped UTBs, should be designed with gate-

source/drain (G-S/D) underlap [Tri05a]. The benefits of the underlap

include better control of SCEs via a gate bias-dependent effective channel

length (Leff) [Fos03c, Tri05a], as well as elimination of gate-induced drain

leakage (GIDL) [Tan05] and gate-drain/source tunneling currents. The

underlap, however, must be optimally designed because it tends to

increase the source/drain (S/D) series resistance (RSD) and decrease Ion

[She03, Tan05].

Fringe capacitance in classical MOSFETs, with G-S/D overlap,

was modeled some time ago [Shr82], and some modeling was recently






5

reported [Ban05] for DG MOSFETs with underlap. However, the modeling

of Bansal et al. [Ban05] focused on a bias-independent outer-fringe

capacitance, and did not address the VGS dependence of it as well as the

inner-fringe component, which is quite important in nanoscale devices.

In chapter 4, we show, by device and circuit modeling and

simulation, the significance and gate-bias dependence of parasitic fringe

capacitance in nonclassical CMOS devices with G-S/D underlap. Based on

the insights derived from numerical device simulations, we develop a

complete analytical model for parasitic capacitance in nonclassical devices

with G-S/D underlap, which includes both the outer- and inner-fringe

components with VGS dependence, as well as a BOX-fringe component in

the FD/SOI MOSFET. The new modeling is verified by 2-D numerical

device simulations. Using a new version of UFDG with the parasitic fringe

capacitance model, we check RO delays to show that the implied underlap

design tradeoff for ultimate CMOS speed is affected significantly by

parasitic G-S/D capacitance, i.e., fringe capacitance, in nanoscale devices.

As mentioned, DG FinFETs with undoped UTBs are very

attractive for scaled CMOS due to their inherent benefits, i.e., better SCE

control, smaller intrinsic gate capacitance in weak/moderate inversion,

and high lon/Ioff ratio. However, with the ultimate limit of UTB, i.e., -5nm

[Tri03a] due to severe quantization effects and technological difficulties,

DG FinFET scaling to and beyond the HP25 node with Lg = 10nm [Sem05]

seems to be extremely difficult since the fin thickness required for SCE









control is wsi = Leff/2 [Yan05] if high-k gate dielectric is not viable. Thus,

for further gate length scaling to 10nm and beyond, nonclassical CMOS

devices have to be designed with the G-S/D underlap [Tri05a]. Even for the

Lg > 10nm regime or/and when a reliable high-k gate dielectric is

developed, the underlap structure should be quite useful in the device

design for effecting an optimal SCEs vs. Ion trade-off [Kra06, Lim05,

Tri05a].

This benefit of the underlap structure in the DG FinFET should

be most useful for SRAM applications. This is because high Vt tends to

give large read static noise margin (read-SNM) and write-margin [Guo05],

and can be easily obtained by SCE control via the effective channel length

(Leff) modulation in the weak-inversion region [Fos03c]. On the other

hand, for the device speed issue, with the insight gained from the

relationship between the S/D doping profile and Vt (and thus Ion), we can

minimize the Ion loss, still keeping the parasitic capacitance small by

controlling the extension length (Lext) and straggle (0L). Thus, the

underlap can also be quite useful in improving the device speed.

In chapter 5, we first explore SRAM cell design and scaling via

DG FinFETs with G-S/D underlap. For this study, DG FinFETs with

underlap are first characterized in terms of Vt for various Lext, UL, and wsi

via 2-D numerical [Med04] and analytical simulations [FosOGa]. The

relationship between Vt and read-SNM is verified to define an optimal

SRAM cell, for the HP45 node with Lg = 18nm [Sem05], with large read-









SNM and write-margin as well as less sensitivity to process variations of

Lext and OL. Then, a scalability study of DG FinFET-based SRAM cell,

with and without the G-S/D underlap, is done. Finally, based on the

insight gained from Vt shift and Ion variation by oL changes, we optimally

design DG FinFETs to improve the device speed.

In Chapter 6, this dissertation is concluded with a summary and

suggestions for future works.

Appendixes A and B describe supporting UFDG model studies

and a unique DG MOSFET feature, respectively.














CHAPTER 2
NANOSCALE CMOS: POTENTIAL NONCLASSICAL TECHNOLOGIES
VERSUS A HYPOTHETICAL BULK-SILICON TECHNOLOGY

2.1 Introduction

For classical bulk-Si and partially depleted (PD) SOI CMOS,

continued scaling much beyond a physical gate length of -50nm [SemOl]

is doubtful because of severe short-channel effects (SCEs) and

unacceptably low lon/Ioff ratio. Hence, there is a growing interest in

nonclassical fully depleted (FD) SOI single-gate (SG) and double-gate

(DG) MOSFETs with ultra-thin bodies (UTBs) because of their inherent

suppression of SCEs. Further, their small intrinsic gate capacitance in

weak/moderate inversion and, especially for DG devices, the high Ion/Ioff

ratio stemming from the nearly ideal subthreshold gate swing imply

substantial CMOS speed superiority over the classical SG counterparts

[Fos02]. However, DG technology is complex; the DG FinFET [His98,

Hua99] is easiest to fabricate, but its proven utility is years away.

Contrarily, FD/SOI SG technology is less complicated; UTBs and metal

gates are the main obstacles in its development [ChoOO].

Because of the technological complexities and difficulties

associated with DG CMOS, questions have been posed about the

performance advantage relative to SG CMOS that it can potentially

provide. For example, if the DG MOSFET gives twice the current, but with









twice the gate capacitance, then excessive device parasitics implied by the

complex technology might render inferior performance. Further, it has

been argued that SCEs in the bulk-Si SG MOSFET could be effectively

suppressed by super-halo channel doping such that bulk-Si CMOS could

actually be scaled down to 25nm channel lengths [Tau98]. However, this

argument is simulation-based, and there is uncertainty about the physical

modeling assumed [GeOl] and whether the assumed device structure

could even be fabricated [Tau98]. Nonetheless, given such a "hypothetical"

nanoscale bulk-Si CMOS technology, more detailed insights on the

relative performance potentials of nonclassical UTB CMOS would be

useful in deciding how and if they should be aggressively pursued.

In this chapter, we first compare asymmetrical and symmetrical

DG, and FD/SOI SG devices via simulations done with our process/

physics-based compact model UFDG [Fos03a, Fos04a], with emphasis on

their immunity to SCEs. Then, using UFDG, we optimally design these

nonclassical devices for 28nm gate length, and project their

characteristics, including CMOS ring-oscillator delays, which we compare

with projections of a hypothetical 28nm bulk-Si SG CMOS design derived,

using our UFPDB compact model [Fos97], from Taur et al. [Tau98].

Interpretations of the simulation results give good physical insights on the

nonclassical technologies, and indicate which ones might best replace the

classical technologies at nanoscale nodes of the SIA ITRS [SemOl].









2.2 UFDG, UFPDB, and Simulation Conditions

The UFDG model [Fos03a, Fos04a] is generic, and hence

applicable to FD/SG MOSFETs with relatively thick or thin [Fen03] back

gate oxide as well as to both asymmetrical (ADG) and symmetrical (SDG)

DG MOSFETs. The process/physics basis of UFDG makes it predictive and

useful for doing the comparative projections. The model parameters can be

defined largely from the device structure and physics. UFDG predicts

SCEs mainly via a 2D solution of Poisson's equation in the UTB for weak-

inversion conditions [Yeh95]. In the strong-inversion region, the

quantum-mechanical carrier confinement is incorporated in UFDG via the

derivation of an iterative, self-consistent solution, dependent on both gate

voltages VGfs and VGbS, of the 1D (in x) Schrodinger and Poisson equations

in the UTB/channel [Ge02]. This solution further physically accounts for

the charge coupling between the front and back gates, and properly models

the charge distribution throughout the Si-film UTB. UFDG also accounts

for the dependence of carrier mobility on the UTB thickness (tsi) as well

as on the transverse electric field (Ex), and quasi-ballistic carrier

transport in scaled devices is modeled via carrier-velocity overshoot,

which is characterized in terms of carrier temperature [GeO 1]. In addition,

UFDG includes the parasitic (coupled) BJT (current and charge) and

temperature dependence without the need for any additional parameters.

The UFPDB model [Fos97] is also process/physics-based, and is

unified for application to PD/SOI as well as bulk-Si SG MOSFETs. This








model is based on a presumed retrograded, or super-haloed, channel, and

it physically accounts for polysilicon-gate depletion [Chi01], carrier-

energy quantization [Chi01], carrier velocity saturation with possible

overshoot [GeOl], and gate-body tunneling current [Yan04].

For the nonclassical devices, we assume undoped bodies since,

technologically, dopant control in UTBs is virtually impossible, as in

extremely scaled bulk-Si and PD/SOI MOSFETs. Then, since the number

of natural dopants in the body will actually be zero when device

dimensions are extremely scaled, the UTBs are modeled as intrinsic.

However, to avoid numerical instabilities in UFDG, Ng = 1015/cm3 is used

for the simulations. Indeed, such a small NB is virtually equivalent to NB

= 0 [Tri03a]. For SDG and FD/SG devices, we select metal gates (for Vt

control), while n+- and p'-polysilicon gates are assumed for ADG devices,

but without accounting for gate-depletion effects (which is justified

somewhat by the relatively low Ex). The front and back gate-oxide

thicknesses (or EOTs) are assumed equal in the DG devices, except for a

brief analysis of the effects of unequal thicknesses in ADG devices. For the

FD/SG devices, a thick buried oxide (tBox = 200nm) on a lightly doped

(1015/cm3) p-type Si substrate is assumed. We ignore the source/drain field

fringing in the BOX [Yeh95], which can exacerbate the SCEs that are

predominantly governed by the UTB. Hence, it should be noted that the

actual effective channel lengths (Leff) of given FD/SG devices might be a

bit longer (by -3-5nm) than the values stated. However, if the actual








devices were designed with gate-source/drain underlap [Tri05a], which

will probably be necessary, then the results of our study are reasonable as

given. The effects of thinning tBOX are subsequently examined. For the

bulk-Si/SG CMOS, n'- and p'-polysilicon gates, with gate-depletion

effects, are assumed for nMOSFET and pMOSFET, respectively. We

employ a retrograded channel, which adequately reflects the super-halo

doping suggested by Taur et al. [Tau98], and Vt is tuned via the lower,

surface doping density (NBL in UFPDB).

2.3 Immunity to Short-channel Effects

We first compare SCEs in the nonclassical DG and FD/SG

MOSFETs. Using UFDG, we vary the gate length (Lg, assumed to equal

Leff) from 500nm to 28nm, fixing tsi and the gate-oxide thickness (toxf and

toxb for the DG devices) at 10nm and 3nm, respectively. The predicted

threshold voltage roll-offs (AVt(Lg) at VDS=50mV) of the ADG, SDG, and

FD/SG n-channel devices are compared in Fig. 2.1. Here, for each device,

Vt is defined via IDs(VGs=Vt) = 10 7Wg/Lg (A), and Vt of the Lg = 500nm

device is taken as the reference. As indicated in the figure, for the ADG

and SDG devices, AVt is negligible and no significant differences between

the two DG devices are evident down to Lg ~ 70nm. However, when Lg is

scaled below -70nm, the ADG MOSFETs show superior AVt control over

the SDG counterparts. This can be explained by the higher Ex and

stronger gate-gate charge coupling in the ADG devices [KimOl]. For the

FD/SG MOSFETs, as clearly shown in Fig. 2.1, the Vt roll-off is much more





















/,'AVt


-0.02


-0.04


-0.06


-0.08


-0.10


-0.12


-0.14


-0.16


Figure 2.1


UFDG-predicted threshold voltage roll-off (solid line) and
DIBL (dash line) versus gate length (=Leff) of the ADG, SDG,
and FD/SG n-channel devices with toxf=toxb=3nm (for FD/SG,
tBox=200nm) and tsi=10nm; Vt is defined via IDs(VGS=Vt)
=10 7Wg/Lg [A] at VDS=50mV, and, for each device, Vt of the
Lg=500nm device is taken as the reference. DIBL is defined
via AV=Vt(VDs=50mV)-Vt(VDs= 1.0V).


0.00


A D G
i7I~ADG

, SDG

00Y FD/SG
M I



SAV
*' I .

c--
i '*: ...-. .
S;----

I I I I I I I I
100 500
Lg[nm]


-0.18


II I


0.20


0.18


0.16


0.14


0.12


0.10 <


0.08


0.06


0.04


0.02


0.00








severe than those of the DG counterparts, implying that much thinner

UTB will be necessary to control the SCEs in FD/SG CMOS.

Also in Fig. 2.1, predicted DIBL (defined by AV = Vt(VDs=50mV)

Vt(VDs=1.OV)) is given, showing similar superiority of the DG devices

over the FD/SG device. And, as for AVt, the ADG device is better than the

SDG device with regard to AV. The predicted subthreshold gate swing (S)

shows trends similar to those of AVt and AV shown in Fig. 2.1. Also, we

observe that for long Lg (> -70nm), S approaches its ideal value (60mV at

300K) for both DG devices, and nearly so (61mV) for the FD/SG device

since the body-effect coefficient (m = 1 + CBody/Coxf 1 + Coxb/Coxf [Lim85])

is only slightly greater than unity due to the thick tBox.

2.4 28nm Device Design

To compare classical and nonclassical CMOS performance

potentials, we first use UFDG and UFPDB to optimally design the devices

at the Lg = 28nm node. Consider the ADG nMOSFET initially. To reduce

the SCEs reflected by Fig. 2.1 to acceptable values, two approaches are

checked: thinning the gate oxide and thinning the Si-film thickness.

UFDG shows that when toxf = toxb tox is decreased from 3nm to Inm in

the ADG nMOSFET (tsi remains fixed at 10nm), the SCEs (AV and S) are

steadily and significantly improved. Further, because of the lowering of S,

Ion is continually increased, and loff is decreased. However, thinning the

oxide thickness toward Inm is not necessarily optimal due to the abrupt

increase of gate-tunneling leakage current [GhaOO, Yan04]. Indeed, for the









ADG device, limiting tox at 2nm might be, with thin tsi, enough to

suppress severe SCEs: we predict AV 56mV and S 76mV for this tox.

However, with n'- and p'-polysilicon gates, this ADG device

design, i.e., tox=2nm and tsi=10nm, is not viable for high-performance

(HP) CMOS applications [SemOl], even with modification of tsi; the low

loff (~5.0nA/pm) reflects a too-low Ion. Rather, this design can be made

applicable to low-operation-power (LOP) CMOS (loff ~ 0.8nA/im from the

ITRS roadmap [SemOl]) by adjusting tsi to 8.6nm. Therefore, our

pragmatic optimal ADG design is initially taken as tox = 2nm and tsi =

8.6nm for LOP applications.

Analogous to thinning tox, decreasing tsi from 10nm to 6nm in

the ADG device (with tox held at 3nm) also yields steady improvement in

SCE control (reductions in AV and S), but since the reduction in S is

relatively small, the increase in Ion is not as significant as that obtained

by thinning tox. We note further that Vt and loff of the ADG device might

be controlled, without much change in Ion, by adjusting tsi, keeping the

pragmatic n'- and p'-polysilicon gates, instead of varying the channel

doping, which is not viable.

To assess the two noted approaches for optimizing the ADG

device design, we show in Fig. 2.2 UFDG-predicted IDs(VGs)

characteristics of the initially optimized device and of one designed with

the same loff via thinner tsi (7.4nm) and thicker tox (3nm). As evident in

this figure, the former device, with the thinner tox, shows lower S and















10-3


10-4


10-5


10-6


10-7


10-8


10 -


10-10


10-11


10-12
-0.1


Figure 2.2


0 0.1 0.3 0.5 0.7 0.9 1.1
VGS M

UFDG-predicted current-gate voltage characteristics, at low
and high drain voltages, of the initially optimized 28nm ADG
device and of one designed with the same loff (-0.76nA/mm)
via thinner tsi and thicker tox.









higher Ion, and hence it is solidified as our optimal 28nm ADG MOSFET

for LOP applications.

To gain more insight on this ADG device design, we show in Fig.

2.3 predicted effects of separately varying toxf and toxb. In Fig. 2.3(a), we

see that varying only toxf offers some control of Vt. However, we also see

that S and Ion are degraded when using thicker toxf due to the decreased

sensitivity of the body potential to the voltage change on the front gate.

Interestingly, however, in Fig. 2.3(b) we see that varying only toxb is more

effective in controlling Vt, with smaller effects on S and Ion. This is

because the ADG MOSFET has only one predominant channel, which is

closer to the front (n') gate [KimOl]. Thus, for ADG devices with n'- and

p'-polysilicon gates, varying toxb, with fixed toxf for SCE control, might be

useful for Vt tuning. However, for low-standby-power (LSTP) applications

with very low loff IpA/pm [Sem01], this approach to Vt control should

also include tsi variation, as indicated in Fig. 2.3(b).

Now, for a fair comparison, we design the SDG (e.g., a FinFET)

and FD/SG nMOSFETs with the same structure as the optimized ADG

device, i.e., with tox=2nm and tsi=8.6nm, and the same loff (-0.8nA/pm) for

LOP applications. We get the specified loff by tuning the metal-gate work

functions (which might not be so easily done technologically): (M = 4.62V

for the SDG device, and M = 5.02V for the FD/SG device. And, knowing

the FD/SG MOSFET will show inferior SCE control, we also define a more

aggressive, optimal version of it with tox = Inm and tsi = 5nm, which are















10-3

10-4

10-5

10-6

10-7

10-8

10-9 / :

10-10

10-11 ,

10-12

10-13
-0.1 0 0.1





10-3

10-4 toxf

10-5

10-6

10-7

10-8 -

10-9 -/ // /

10-10 /

10-11

10-12

10-13 '

10-14
-0.1 0 0.1


0.3 0.5 0.7 0.9 1.1
VGS [V]


0.3 0.5 0.7 0.9 1.1
VGS [V]


UFDG-predicted effects of (a) separately varying toxf in the

ADG device with toxb fixed at 2nm and (b) separately varying

toxb in the ADG device with toxf fixed at 2nm, showing some
control of both Vt and S, and how the effects are enhanced
when tsi is thinned to 6nm (shown in (b)).


Figure 2.3









close to the technological limits of these structural parameters. This

optimal device is also designed, neglecting the possible significance of

gate-tunneling leakage, to have the same Ioff (with
the optimized ADG device.

For the hypothetical bulk-Si/SG nMOSFET design, we use

UFPDB, generally following Taur et al. [Tau98] for SCE control, but using

a more aggressively scaled gate oxide, tox = Inm as for the optimal FD/SG

device, with gate tunneling still neglected. The retrograded channel is

defined with surface doping density NBL = 3.42x1018/cm3, a peak body

doping density (NBH) of 1019/cm3, and an effective depletion thickness (Tg)

of 14.2nm. The noted NBL of this nMOSFET, with n+-polysilicon gate, was

tuned to yield loff equal to that of the nonclassical devices. Note that this

channel/body doping profile is probably not manufacturable, rendering a

hypothetical device.

Figure 2.4 shows UFDG/UFPDB-predicted IDs(VGS)

characteristics of the two optimal DG devices, of the two designed FD/SG

devices, and of the bulk-Si/SG device. Clearly, the suboptimal FD device

with the thicker tsi (= 8.6nm) suffers from severe SCEs; AV = 266mV and

S = 108mV. However, the SDG device, like the ADG device with the same

tsi, shows good control of the SCEs, with the ADG device being a bit

superior in this regard; AV is 42mV and 72mV for the ADG and SDG

devices, respectively, and S is 72mV and 74mV. For the optimal, thinner-

tsi (= 5nm) FD/SG device, good SCEs (AV 43mV and S = 71mV) and larger














10-3

VDS=
10-4


10-5


10-6


10-7


10-8


10-9



10-10 /

-0.1 0 0.1
-0.1 0 0.1


Figure 2.4


0.3 0.5 0.7 0.9 1.1
VGS M


UFDG/UFPDB-predicted current-gate voltage
characteristics of the two optimally designed DG
nMOSFETs, with tox=2nm and tsi=8.6nm, of the two
designed FD/SG nMOSFETs, i.e., optimal FD/SG with
toxf=lnm, tBox=200nm, and tsi=5nm, and suboptimal FD/SG
with toxf=2nm, tBox=200nm, and tsi=8.6nm, and of the
optimally designed bulk-Si/SG nMOSFET, with tox= nm and
TB=14.2nm, at high drain voltage; for all devices, Lg=28nm
and Ioff=0.76nA/pm.









Ion, relative to the suboptimal design, are predicted. We stress, however,

that if the DG devices were thinned to tsi = 5nm, their SCEs would be

virtually nonexistent (as UFDG simulations show). For the bulk-Si/SG

device, the SCEs are effectively suppressed due to the thin Tg as shown in

the Fig. 2.4. Note here that since DIBL renders a minor effect on the delay

performance [Tau98], we selected TB to get relatively small S (-80mV),

sacrificing DIBL (-120mV) and necessitating the high NBL to keep loff

under control.

As mentioned, the applications of the designed ADG device, with

n- and p+-polysilicon gates, are limited to LOP. Thus, for HP

applications, we can consider only the defined SDG and FD/SG devices

with new metal gates (
4.29V for the suboptimal and optimal FD/SG devices, respectively), and

the hypothetical bulk-Si/SG device with new Tg (17.5nm, to keep S ~

80mV) and NBL (1018/cm3) for appropriate Ion/Ioff.

For the CMOS technologies, the SDG and FD/SG pMOSFETs are

designed to have the same loff as that of the ADG nMOSFET by using

metal gates and tuning the work functions. However, for the ADG

pMOSFET, n+- and p+-polysilicon gates are still assumed, but switched for

the back and front gates, respectively. Thus there is a slight discrepancy

in loff between the two ADG CMOS devices because of the different

electron and hole mobilities. The bulk-Si pMOSFETs are also designed to

have the specified loff by adjusting NBL with a p-polysilicon gate, keeping









TB and NBH the same in the nMOSFETs. For ring-oscillator simulations,

we assume the source/drain areas of the bulk-Si CMOS devices are defined

based on lengths of 3 x (pitch/2) [Sem01].

2.5 CMOS Performance Projections

To compare CMOS speeds, 9-stage unloaded CMOS-inverter ring

oscillators (ROs) were simulated with UFDG and UFPDB in Spice3.

Predicted propagation delays for the classical and the four nonclassical

device designs (for LOP) are plotted in Fig. 2.5 versus supply voltage VDD.

As expected, the DG CMOS designs are faster than the SG ones, including

bulk-Si CMOS, over the entire voltage range, while the ADG and SDG

CMOS delays are virtually the same. Interestingly, the optimal FD/SG

design has comparable speed to the DG CMOS designs: only -15% longer

delay at VDD = 1.2V. Further, the speed of the suboptimal FD/SG design

is not much worse at high VDD (-34% slower at VDD = 1.2V, compared to

the DG CMOS), although the delays are significantly longer at VDD <

-1.0V. Contrarily, the predicted RO delay for the bulk-Si SG CMOS is

much longer than those of all the nonclassical CMOS designs over the

entire voltage range, even though the bulk-Si devices are hypothetical and

seemingly optimal.

For HP-applicable CMOS, i.e., the SDG, the FD/SG, and the

bulk-Si/SG designs all with loff = 0.7pA/im as noted, the RO simulation

results, shown in Fig. 2.6, are very interesting. As in the LOP CMOS RO

results, the SDG design shows speed superiority over the optimal FD/SG















4.5
4.5


60

55

50

45

40

_35
(,
0')
30

25
Do

20

15

10

5


I I I I I I


0.70


0.80


0.90 1.00
VDD [V]


1.10


1.20


1.30


Figure 2.5


UFDG/ and UFPDB/Spice3-predicted propagation delays
versus supply voltage of 9-stage unloaded CMOS-inverter
ring oscillators comprising the five 28nm DG, FD/SG, and
bulk-Si/SG LOP device designs. Gate-source/drain overlap of
10% of Lg was assumed for all gates. Three of the five delay
curves are re-plotted in the inset for better view. The off-
state current of all devices was matched to 0.8nA/mm.


I I I I


1.2 1.3 -


0 L
0.60

















-

A SDG
S-----o Suboptimal FDISG
o-o Optimal FDISG
\ Bulk-Si SG














------- E


1.5 I I I
0.6 0.7 0.8 0.9 1.0 1.1 1.2
VDD [


Figure 2.6


UFDG/ and UFPDB/Spice3-predicted propagation delays
versus supply voltage of 9-stage unloaded CMOS-inverter
ring oscillators comprising the four 28nm SDG, FD/SG, and
bulk-Si/SG HP device designs. Gate-source/drain overlap of
10% of Lg was assumed for all gates. The off-state current of
all devices was matched to 0.7mA/mm.


9.5 F


8.5


7.5


0-6.5

-I-,
T-5.5
>13


4.5


3.5


2.5


I I I I I I I I I I I I








and the bulk-Si/SG designs over the entire voltage range. Surprisingly,

however, the suboptimal tsi = 8.6nm FD/SG design actually yields shorter

delay relative to that of the SDG design for VDD > -0.95V; but for lower

VDD, it becomes slower. The equivalent speed performance for higher VDD

seems inconsistent with the predicted currents of the FD/SG and SDG

devices for HP, which can be inferred by shifting the IDs(VGS)

characteristics for LOP in Fig. 2.4. The FD/SG device shows much lower

Ion (by -37% at VDD = 1.0V).

To explain these unexpected suboptimal FD/SG RO results, we

consider intrinsic gate capacitance of the nonclassical devices. In the

subthreshold region, the inversion charge is negligible, and thus the gate

capacitance of the intrinsic FD/SG MOSFET can be expressed by the

series combination of oxide capacitance and the effective body capacitance

[Lim85]:


G ( 1 + 1 1 (2.1)
G C C CBody (2.1)
Soxf Body Bod

where Coxf is the front gate oxide capacitance and CBody includes the UTB

depletion capacitance, Cb = Esi/tsi, and the buried oxide capacitance, Coxb

= ox/toxb:

CoxbCb

l an hence isc in oxb21.e tbh sb h rso regoga
cBody oc + C, oxl < b' C fo (2 2)

For the common thick toxb for1 FD/SG, i.e. teBox, CBody in (2.2) is relatively

small, and hence so is CG in (2.1). Indeed, the subthreshold-region gate









capacitance of the FD/SG device is defined predominantly by parasitic

capacitance, e.g., the gate-source/drain overlap capacitance. Further, for

VGS increasing to strong inversion, the increase in CG defined by the

inversion-charge is, in our suboptimal tsi = 8.6nm FD/SG device, deferred

to higher voltages (VGS 0.75V) because of the high S. Therefore, the

device shows extremely small CG (including the parasitics) at low VGS

(-0.5V), as shown by the UFDG-predicted curve in Fig. 2.7. However,

when we thin tsi to get better control of the SCEs, S decreases, and the

optimal FD/SG device shows, also in Fig. 2.7, intermediate-VGS CG that is

much larger than that of the suboptimal FD/SG device. Similarly, the DG

devices show in Fig. 2.7, because of device neutrality [Fos02], very small

CG at low VGS, but the increase due to inversion charge occurs at lower

VGS due to the low S. The comparative result then is that the DG devices

show much higher gate capacitance than the suboptimal FD/SG device at

all VGs. We believe that the relative CG(VGS) curves in Fig. 2.7,

irrespective of the IDs(VGs) characteristics inferred from Fig. 2.4, underlie

the surprising RO results in Fig. 2.6.

Unlike the nonclassical devices, CBody of the classical bulk-Si/SG

device is defined by the large depletion capacitance (i.e., esi/TB), and hence

CG is finite and substantive as indicated by the UFPDB-predicted curve in

Fig. 2.7. Because of the high CG in the weak/moderate inversion region, in

addition to the areal source/drain junction capacitance, and the

polysilicon-gate depletion effect in strong inversion, the bulk-Si CMOS















4.0


3.5


3.0


2.5

E
0
LL 2.0
0

1.5

--

1.0


0.5
-B


0.0
-0.2


Figure 2.7


0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGS [V]

UFDG- and UFPDB-predicted gate capacitances versus gate
voltage, at low drain voltage, for the four 28nm SDG, FD/SG,
and bulk-Si/SG device designs. Gate-source/drain overlap of
10% of Lg was assumed for all gates.








speed is much slower than those of the nonclassical CMOS designs. The

main effect of the gate depletion is reduced Ion, as reflected by the

decreasing CG for increasing VGS in Fig. 2.7.

The propagation delay reflected by the oscillation frequency of

the RO is defined by the pull-down (VDD-to-VDD/2) and pull-up (0-to-VDD/

2) times of a constituent inverter. These times depend on the VDS-

dependent currents (IDs(t)) in the driving transistors, and on the

capacitive load at the output terminal, which, for the unloaded RO, is

predominantly the sum of the nMOSFET and pMOSFET gate capacitances

of the next stage (CGn(t) + CGp(t)). We define, for pull down in the SDG and

the two FD/SG CMOS designs, the dynamic current IDs(t) of the driving

transistor between VDs(t) = VDD, which corresponds to VGS(t) = VDD/2,

and VDs(t) = VDD/2. Similarly, we define the dynamic charging current

(IQ(t)) at the inverter-output node, which is the gate current of the next-

stage inverter. With these two dynamic currents IDS(t) and IQ(t), we can

estimate the pull-down time (tpd, which is comparable to the pull-up time

tpu) of a constituent inverter for each design, and thereby confirm our

belief about the surprising relative delays in Fig. 2.6.

To simplify our estimations, we define an average value of the

total gate-capacitance load,


CG p dt, (2.3)
VDD


and use it to approximate the pull-down delay as









pd VDD/2 1
fpd= _0 dtCGVDD IDS(VD s)dVDS. (2.4)

Indeed, for VDD = 0.65V, we get using (2.3) and (2.4) Tpd = 2.43ps and

1.93ps for suboptimal FD/SG and SDG, respectively. However, for VDD =

1.2V, we find ipd = 1.49ps and 1.43ps for FD/SG and SDG, respectively.

(Note that the estimated delays are a bit shorter than the predicted RO

delays (=(tpd+tpu)/2) in Fig. 2.6 due to the neglected parasitic capacitances

such as the gate-source/drain overlap capacitances.) Thus, these

estimated values of tpd are in accord with the surprising results in Fig. 2.6,

i.e., the significant SDG speed superiority at low voltages and the

comparable FD/SG speed at high voltages.

Now, by defining an average 1/IDs in (2.4) analogous to CG in

(2.3), we can evaluate the contributions of the driving current and the

capacitive load in determining the RO delays for each CMOS design. For

VDD = 0.65V, we get the average-current ratio IDS(SDG)/IDS(FD) = (1/

IDS(FD))/(1/IDS(SDG)) = 3.91, where FD here refers to the suboptimal tsi =

8.6nm design, and the average-capacitance ratio CG(SDG)/CG(FD) = 3.09.

For VDD = 1.2V, we get IDS(SDG)/IDS(FD) = 2.24 and CG(SDG)/CG(FD) = 2.20.

These ratios, with reference to (2.4), explain that the SDG speed

superiority at low voltages comes from the relatively high average drive

current (i.e., IDS(SDG)/IDS(FD) > CG(SDG)/CG(FD)) in the SDG devices. Also,

they explain that the surprising comparable FD speed at high VDD is due

to the relatively low average gate capacitance (i.e., IDS(SDG)/IDS(FD)









CG(SDG)/CG(FD)) in the FD/SG devices. Other RO simulations done with

UFDG/Spice3 reveal that this FD/SG speed merit at high VDD is

maintained when the gate-source/drain overlap capacitances are

increased up to 30%. However, for the optimal FD/SG design with tsi =

5nm, we find for all VDD that CG and 1/IDS are comparable to the

corresponding averages of the DG device (i.e., CG(SDG)/CG(FD) is 1.06 and

1.08 and IDS(SDG)/IDS(FD) is 1.06 and 1.11 for low and high VDD,

respectively). As a result, we get, from the average CG and 1/IDS (or

directly using (2.4)), the comparable tpd for the optimal FD/SG compared

to SDG. All the relative RO delays of the nonclassical CMOS in Fig. 2.6

are hence explained, and good physical insights regarding them is

attained.

The speed comparisons in Figs. 2.5 and 2.6 were derived from

unloaded RO simulations. With loading, we anticipate that the relative

performance of the suboptimal FD/SG CMOS will deteriorate because of

its lower current drive. The UFDG/Spice3-predicted loaded (CL on each

stage) RO delays plotted in Fig. 2.8 versus CL confirm this anticipation.

Hence, in general applications, DG CMOS should be substantively faster

than the FD/SG counterpart, especially for heavy loads and low supply

voltages. Nevertheless, it is interesting to learn that for light loads and

HP applications, suboptimal FD/SG can yield speeds comparable to DG.






















VDD=1.2V


I I I I


5.5


5.0


4.5


w 4.0
0..
c,)

3.5
>,

Q 3.0


2.5


2.0


1.5
-0.2


Figure 2.8


I I I I I I I I I I I I I I I I I I I I I I
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
CL [fF]

UFDG/Spice3-predicted loaded (CL on each stage) CMOS
ring-oscillator delays versus CL, at VDD=1.2V, for the 28nm
SDG and FD/SG device designs.


A-ASDG
E---- Suboptimal FDISG
e-e Optimal FDISG








2.6 Thin-BOX FD/SOI CMOS

For the FD/SOI SG devices with thick BOX, it has been reported

that the BOX field fringing and the coupling between the source/drain and

channel will degrade the SCE control, and thus using thin BOX (< -40nm)

for nanoscale FD/SOI devices is beneficial for improving SCEs and the Ion/

Ioff ratio [Fen03]. Also, it was confirmed [Num02] that whereas for long-

Lg devices S increases with decreasing tBox, S for shorter Lg is minimized

for tBox < 50nm. However, the benefit of thinning tBox is much reduced

when tsi is ultrathin [Tri03a] since the underlying fringing-field effect in

the BOX is reduced along with the SCEs via the UTB. Also, when the BOX

is thinned, the effective body capacitance [Lim85] and the source/drain

junction capacitance [Yeh95] will be increased, implying that thin BOX

may undermine FD/SOI CMOS speed. Note also that the increased CBody

implies added sensitivity of the FD/SG device characteristics, e.g., Vt

[Lim85], to variations in tsi.

To solidify our notion [Tri03a] that thinning the BOX is not a

judicious design option, we examine its effects more closely using UFDG.

When the BOX is thinned down to 20nm in our optimal FD/SG devices,

UFDG predicts that the intrinsic gate capacitance CG is increased a bit,

especially in the subthreshold region, while the average CG from RO

simulation stays almost constant for VDD = 1.2V. The increase can be

explained by the increment of CBody in (2.2) with reduced tBox (or toxb).

For tBox thinned down even further, CG is estimated to be comparable to









that of the correspondingly scaled bulk-Si MOSFET, which is finite and

substantive for low VGS [Fos02]. However, this estimation tends to be too

high since UFDG does not account for substrate, or back-gate depletion

under the (front) gate.

In addition to the CG increase, thinning the BOX also increases

the (quasi-static) parasitic source/drain capacitances to values that are

comparable to CG in the subthreshold region. This is because the substrate

under the source/drain tends to be inverted in the nMOSFET and

accumulated in the pMOSFET, yielding source/drain capacitances that

are defined mainly by the Coxb. However, for high-speed transients such

as the RO oscillations, the inversion charge under the source/drain of the

nMOSFET cannot respond to the applied transient voltage, thus causing

a deep-depletion condition in the substrate. Therefore, the parasitic

source/drain capacitance can be neglected for the nMOSFET. The

substrate accumulation charge in the pMOSFET can respond, however,

and hence the parasitic source/drain capacitance in it is determined by

Coxb, which increases for decreasing tBox. Based on the noted increases in

gate and source/drain capacitances, we can predict that the CMOS speed

will be substantially degraded when the BOX is aggressively thinned as

suggested in [Fen03]. The UFDG/Spice3-predicted RO delays plotted in

Fig. 2.9 versus tBox for the optimal FD/SG CMOS provide clear evidence

of the speed degradation. We include in the figure predicted delays

without accounting for the areal source/drain capacitance. For this case,




















-A VDD=0.7V
-- VDD=0.9V
0- VDD=1.2V
A-----A VDD=0.7V w/o area Cs/D
.----- VDD=0.9Vw/o real Cs/D
e----* VDD=1.2V w/o real Cs/D


B---------------------W---------


-------------------- -------------- ---------------


I I I I I I I


tBOX [nm]


Figure 2.9


UFDG/Spice3-predicted propagation delays of 9-stage
unloaded CMOS-inverter ring oscillators comprising the
optimal 28nm FD/SG device design, with tBox thinned down
to 15nm, at various values of supply voltage. Predicted
delays for no areal source/drain capacitance are also shown.


3.0 k


2.9
'..

' 2.8
()
-I-,
()
>2.7
2(

2.6


2.5 k


I I I I I I I I









we see that there is negligible effect of varying tBox on the RO delays. We

thus conclude that the effect of the increased parasitic source/drain

capacitance in the pMOSFET is predominant in defining the noted speed

degradation caused by thinning the BOX.

2.7 Summary

Using our process/physics-based compact models (UFDG and

UFPDB) in Spice3, we have projected device characteristics and CMOS

performances of nonclassical UTB CMOS technologies (ADG, SDG, and

two versions of FD/SOI, all of which will, generally, require metal gates

with tuned work functions for Ioff control) optimized at the Lg = 28nm node

(where Leff = Lg was assumed), and compared them with that of classical,

hypothetical bulk-Si CMOS at this node. Comparisons of predicted SCEs

(AVt, AV, and S) of nonclassical devices and speeds (RO delays) of the

nonclassical and classical CMOS were made, and good physical insights

regarding their relative characteristics were given. With the same UTB

thickness, the DG devices were shown to be far superior to the FD/SG

devices with regard to SCE control, and generally superior to SG devices,

including bulk-Si devices, with regard to speed because of higher drive

currents. However, an interesting insight was noted. For light loads and

moderate supply voltages, a suboptimal FD/SG design (with the same tsi)

for both LOP and HP applications was found to yield speeds comparable

to the DG designs, even though its current drives are much lower and its

SCEs are much more severe. This surprising comparison was shown to be









a result of the FD/SG devices having much lower intrinsic gate

capacitance, which is due to their thick BOX and higher subthreshold

swing, and hence deferred onset of significant inversion-charge

capacitance. At lower VDD, however, the DG designs are much faster

because of their much higher drive currents. When the FD/SG CMOS

design was optimized by aggressive scaling of the UTB thickness, its high-

VDD speed diminished (but was still comparable to that of DG CMOS)

because of higher gate capacitance at intermediate gate voltages, while its

low-VDD speed improved due to increased current. Compared to the

nonclassical CMOS, the predicted delay of the bulk-Si/SG CMOS was

much longer due to its high gate capacitance in the weak/moderate

inversion region, in addition to the areal source/drain junction

capacitance, and relatively low drive current limited by polysilicon-gate

depletion. Finally, we used UFDG/Spice3 RO simulations to show that FD/

SOI CMOS speed is degraded as the BOX is thinned, mainly because of

increased source/drain capacitance in the pMOSFET, thereby suggesting

that such thinning, aimed at improved control of field fringing in the BOX,

is not a good design tradeoff.














CHAPTER 3
BULK INVERSION IN FINFETS AND IMPLIED INSIGHTS ON
EFFECTIVE GATE WIDTH

3.1 Introduction

While the double-gate (DG) FinFET (Fig. 3.1(a)) has become a

leading device option for future nanoscale CMOS, there is a technological

limit to the aspect ratio (Rf) of the Si-fin height (hsi) to the width (wsi).

Since wsi must be ultra-thin for good control of short-channel effects

(SCEs) [Fos04b], this limit implies small effective gate width (commonly

assumed to be Weff = 2hsi) and, ostensibly, low on-state current (Ion) per

pitch. There is therefore interest in making the FinFET a triple-gate (TG)

transistor by activating the top gate (Fig. 3. 1(b)), yielding, from a surface

inversion-charge perspective, Weff = 2hsi + wsi as is commonly assumed,

and alleviating, with a doped fin-body, the thin-wsi requirement [Doy03].

However, because of fin-corner effects [Fos03b] and technological

limitations [Tri03a], the fin-body must be left undoped, and so relaxation

of the thin-wsi (i.e., UTB) requirement for SCE control for the TG FinFET,

relative to that for the DG device, is minimal [Fos04b]. Nonetheless, the

larger Weff for the TG device could mean significantly higher Ion relative

to that of the DG FinFET even when wsi is thin for good SCE control.

In this chapter, we use three-dimensional (3-D) numerical device

simulations to examine the increase in Ion (Alon) of TG FinFETs with









varying Rf = hsi/wsi that results from activation of the top gate. From the

surface inversion-charge perspective, we expect a relative increase in Ion

of AWeff/Weff(DG) wSi/(2hsi) = 1/(2Rf). However, our simulation results

contradict this expectation, and give interesting insights concerning fin-

body bulk inversion in undoped FinFETs, even in the on-condition, and

imply the consequent inappropriateness of the commonly defined Weff as

an indicator of Ion. Based on proper (re)definition of effective gate width

reflecting bulk inversion, we further examine the gate layout-area issue

[Yan05] of FinFET CMOS.

3.2 Numerical Simulations

We first use Davinci [Dav03], a 3-D numerical device simulator,

to simulate DG and TG n-channel FinFETs as illustrated in Fig. 3.1. We

assume abrupt source/drain junctions, and a metallurgical, or effective,

channel length (Leff = Lgate) of 25nm. The gate-oxide thickness (tox = EOT)

is 1.2nm and the buried-oxide (BOX) thickness is 200nm. For the DG

devices, the top-gate oxide thickness is 50nm, which effectively negates

the top gate electrode; it is tox for the TG devices. Based on [Fos03b,

Fos04b, Tri03a, Yan05], we assume undoped Si-fin bodies with wsi = 13nm

(=Leff/2) and various values of hsi. For threshold-voltage (Vt) control, a

midgap metal gate is assumed.

(We note that the carrier-transport modeling in Davinci is

deficient for nanoscale FinFETs since it is based mainly on studies of

single-gate (SG) bulk MOSFETs. For example, carrier mobility in UTB-fin













(a)


(b)


Figure 3.1


Two-dimensional cross-sectional view of (a) the DG FinFET,
specifying x and z directions in the fin-body, (b) the TG
FinFET, showing the fin-body dimensions, and (c) the DG
FinFET without the top gate stack (thick oxide and metal
electrode).









channels depends on wsi as well as the transverse electric field [Ess03,

Tri04] as does the carrier-energy quantization [Ge02], and Davinci misses

these wsi dependence. We hence ignore the quantization and use the

standard, universal mobility model in Davinci, but stress that the relative

results presented here are nonetheless meaningful.)

3.2.1 I-V Characteristics of DG and TG FinFETs

Davinci-predicted current-voltage characteristics of the DG and

TG FinFETs with hsi = 39nm (i.e., Rf = 3) are shown in Fig. 3.2. These

characteristics show a relative increase in Ion (at VGS = VDS = 1.0V) of only

5.4% in the TG device, much less than the expected 16.7% (= 1/(2Rf)). The

inset of Fig. 3.2 shows semi-log plots of the current-voltage curves,

revealing the subthreshold characteristics of the two devices. The TG-

FinFET Vt is only -10mV higher than that of the DG FinFET

(corresponding to -15%-lower loff). The small difference between the

subthreshold characteristics does not explain the noted discrepancy in the

relative Alon. Such a significant discrepancy is also predicted for other

values of Rf, ranging from about 1 to 5 (non-integers because of finite mesh

spacing for the numerical simulations), as illustrated in Fig. 3.3. Note for

Rf 1, the Davinci-predicted relative increase in Ion due to the top gate is

only 14.0%, as opposed to the expected 54.2%. That is, Ion of the DG

FinFET for this extreme case is almost 90% of that in the TG counterpart,

which is consistent with numerical results of Burenkov et al. [Bur02]. Our














60 1- lu
10-6

50 10-7
) / //'
10-8
40 -
10-9

13 0 1 0-1 .................. ...............
3) o-10-
S0.0 0.1 0.2 0.3 0.4 0.5
VGS [M]

20
VDS= 1.OV

10 D DG FinFET
SB- DG FinFETw/o top gate
ee TG FinFET
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

VGS [V]


Figure 3.2


Davinci-predicted current-voltage characteristics of undoped
n-channel DG FinFETs, with and without the top gate stack,
and of the TG counterpart, all with hsi = 39nm, wsi = 13nm,
tox = 1.2nm, tBox = 200nm, Leff = 25nm, and midgap metal
gate. The semi-log replots of the three curves in the inset
show the subthreshold characteristics, and small variations
in loff and Vt among the three devices.


1.0














100




80


r"



0
C(
0

0
<1


A-A Predicted

X---x Expected (1/(2Rf))


"X,


0 I I I I


0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Rf


Figure 3.3


Davinci-predicted on-state (VGS = VDS = 1.0V) current
increase (Alo) due to the top gate of the TG nFinFET,
relative to the DG nFinFET current (lon(DG)), versus the fin
aspect ratio; Leff = 25nm and wsi = 13nm. Also plotted is the
Weff-based expectation for the relative current increase,
defined by wsi/(2hsi) = 1/(2Rf).


I I l l I l I' '


`X,


X -









results here clearly show that the commonly defined Weff is not a valid

indicator of relative values of Ion in TG and DG FinFETs.

3.2.2 Electric-Field Fringing Effects

A possible explanation for these surprising results is that

electric-field fringing from the sidewall gates above the fin in the DG

FinFET (see Fig. 3.1 (a)) induces significant inversion charge in the top fin

surface. Indeed, exploitation of such field fringing has been proposed to

effect a bottom gate extension [Par02]. To check this explanation, we

simulated the DG FinFET with its top gate stack (thick oxide and metal

electrode) removed as illustrated in Fig. 3.1(c). The predicted current-

voltage characteristic, for Rf = 3, is included in Fig. 3.2. We see that the

field-fringing effect is negligibly small and does not explain the relatively

small increase in Ion of TG FinFETs; Ion of the complete DG FinFET (Fig.

3.1 (a)) is only 1.5% higher than that of the same device without the top

gate stack.

3.2.3 Bulk Inversion

Insight into the actual explanation for the interesting results in

Figs. 3.2 and 3.3 is provided by the Davinci-predicted electron densities

(n) in the three devices of Fig. 3.2 (Rf = 3). Based on the x-z coordinate

system shown in Fig. 3.1(a), n(x,z) at VGS = VDS = 1.0V, taken from the

center of the channel (y = Leff/2), is shown in Figs. 3.4 and 3.5. (These are

classical solutions; the effects of quantization are noted later. Note that

our use of the predicted carrier densities to give insight on the predicted















1020


Cr"
E

0
II
x
C:


1019


1018



Figure 3.4


0 2 4 6 8 10 12


z[nm]


Davinci-predicted on-state electron density along the top fin
surface, at the center of the channel (y = Leff/2), in the DG
and TG nFinFETs of Fig. 3.2.



















c"




E
E
0
LO
(D
11
II
N
C


1019


1018



Figure 3.5


0 5 10 15 20 25 30 35
x[nm]

Davinci-predicted on-state electron density down the middle
of the fin, at the center of the channel (y = Leff/2), in the DG
and TG nFinFETs of Fig. 3.2.









currents in the DG and TG devices further justifies our lack of concern

about the deficiencies of the carrier-transport modeling in Davinci.) In

Fig. 3.4, the variation of n across the top surface (n(x=0,z)) in the DG

FinFET without the top gate stack shows substantive inversion charge

away from the sidewalls, i.e., volume, or bulk inversion. The predicted

n(x=0,z) of the complete DG FinFET shows a moderate increase due to the

noted field fringing. (The top metal electrode does nothing, as we

confirmed via simulation.) The full effect of the field fringing is reflected

in Fig. 3.5 where the predicted electron density down the middle of the fin

(n(x,z=6.5nm)) is shown. The integrated inversion charge in both DG

FinFET structures, however, reflects the small 1.5% benefit of the field

fringing to Ion. For the TG FinFET in Figs. 3.4 and 3.5, we see higher

electron density near the top fin surface due to the third top gate. But, as

discussed with reference to Figs. 3.2 and 3.3, that benefit in the TG device

is much less than that implied by the increased Weff.

As indicated in Figs. 3.4 and 3.5 then, we infer that the results

in Fig. 3.3, i.e., lower than expected Ion in TG FinFETs relative to that in

the DG counterparts, are due to the strong bulk inversion that occurs in

the on-state condition. Note the high n (>2x1018cm3) throughout the fin

bulk, away from the surfaces, in all three device structures. The bulk-

inversion charge in the DG FinFET contributes significantly to Ion,

perhaps due in part to the fact that the electron mobility in the fin bulk








(rb) can be higher than that at the surfaces (js) [Ess03, Tri04] and hence

the activation of the top gate is not very beneficial.

To give more quantitative explanation, we express the DG

FinFET on-state current, separating out surface (Qis) and bulk (Qib)

components of inversion-charge density:

Ion(DG)= WeffQisVs hSiibvb (3.1)

where vs and vb represent the average carrier velocities at the fin surfaces

and in the fin bulk, respectively. Note that the velocities depend on, in

addition to ts and Pb, VDS which controls the electric field Ey(x) and

governs velocity saturation/overshoot along the channel. Actually, (3.1) is

a reasonable expression if Rf is greater than one, which makes the

effective width of the fin-bulk component approximately hsi. For the Rf =

3 DG FinFET of Figs. 3.4 and 3.5 (with wsi = 13nm), we find surprisingly

large Qib > Qis at VDS = VGS = 1.0V, which, via (3.1), defines a predominant

enhancement of lon(DG) over that implied by Weff:

Sibvb
I ,^-W Q v 1+-- (3.22)
on(DG) eff is s 2Q. v (

We note that vb and vs are comparable because of the tendency for velocity

saturation along most of the short channel. However, we could get a Pb >

Ps benefit with velocity overshoot, and hence more contribution of bulk

inversion to lon(DG) via (3.2).

With the substantive bulk inversion charge in the DG FinFET

defining lon(DG) as in (3.2), activation of the top gate, rendering the TG









counterpart, results in only a relatively small increase in the total

inversion charge, at the top surface as shown in Fig. 3.5, and in Ion as

reflected by Figs. 3.2 and 3.3. We confirm then that, indeed, the

discrepancies in Fig. 3.3 between the actual and expected Ion of the TG

FinFET relative to the DG FinFET are mainly a reflection of the

significance of the bulk-inversion component of current in (3.1) and (3.2).

In fact, this bulk current is the predominant component of lon(DG) in all the

DG FinFETs we simulated. Its predominance varies some because the

noted field-fringing (relative) benefit to lon(DG) increases with diminishing

Rf.

Additional simulations reveal that the significant bulk inversion

is linked to the undoped, thin body. Because of no significant depletion

charge, the electric potential and carrier density in the subthreshold

region are uniform throughout the thin body [Tri03a], as exemplified by

the 2-D Medici [MedOl] simulation results for arbitrary undoped DG and

TG [Fos03b] FinFETs in Fig. 3.6. (Virtually the same uniformity obtains

for the SG fully depleted (FD) SOI MOSFET with undoped body and thick

BOX [Tri03a].) This means that the off-state current in these devices is

proportional to the cross-sectional area of the body/channel: loff c hsiwsi.

As the gate voltage (VGs) is increased then, this uniformity tends to be

maintained, resulting in significant bulk inversion for strong-inversion

conditions. The level of the bulk inversion, e.g., n(x,z=wsi/2) which implies












1020

1019

1018

1017

1016

1015

1014

1013

1012

1011

1010


0.2


0.4


zlwsi


Figure 3.6


Medici-predicted electron density, versus gate voltage,
across the fin-body (vs. normalized z/wsi) of long-channel DG
(wsi = 20nm) and TG (at x = 0 for wsi = hsi = 30nm)
nFinFETs, both with midgap gate; VDS = OV.


C

t-


SDG FinFET
%% 0.6V o---o TG FinFET .

'"-l---^^ --- -----
'? *D- -- --- -------- -- C-- -6
@ @--- __-__._____..___-- .. __ ------------


.... --_.. ....... __..__-_ ____..... _Q __. ...__ ..--.--


....a------9-- ----..9 --------- ---- E -----------


0.1V


VGS = OV
S D, 0 a 0 a Q


0.0









Qib/Qis in (3.2), is governed by the electron screening of the surface electric

field, via Poisson's equation without ionized dopant charge:

dE qn (3.3)
dz- ESi

which is characterized by the Debye length LD oc 1/7n. It tends to diminish

with increasing wsi, but ultimately saturates (at -2x1018cm 3), as shown

in Fig. 3.7, because LD increases as n decreases. However, it should be

noted that for very thick wsi, SCEs might contribute to forming the high

n(x,z=wsi/2).

3.3 Implied Insight of Bulk Inversion

3.3.1 Proper Effective Gate Width

Because of the noted bulk inversion in the undoped DG FinFET,

in the off- as well as the on-states, the effective width of the two side fin

surfaces, 2hsi, does not properly reflect all the inversion charge and

current. The effective gate width should be defined simply as

Weff(DG) = hSi, (3.4)

with (3.2) modified accordingly. (Note that the effective gate width of the

planar SG FD/SOI MOSFET, with bulk inversion, is still the actual gate

width (Wg), which conveys the Qib as well as the Qis contributions to

current.) The gate capacitance is also properly defined by (3.4), i.e., by the

area Leffhsi, as evident in the DG charge characterizations in [KimOl] for

asymmetrical- as well as symmetrical-gate devices. However, a proper
















DG FinFET w/o top gate stack

VGS= VDS= 1.0V


4.2

4.0

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0


21 23 25


wsi [nm]


Figure 3.7


Davinci-predicted on-state electron density at the middle of
the top fin-body surface, at the center of the channel (y = Leff/
2), of the DG FinFET without the top gate stack of Fig. 3.2,
versus the fin width.


E
0
CO

i-i
0




(D
E

II
N
0
II
X
C-


15 17 19


7 9 11 13


, I I I I I I I I I








effective gate width for the TG FinFET cannot be so directly defined, as

evidenced in Fig. 3.3.

3.3.2 Layout Area

We have previously shown [Yan05], based on the commonly

defined Weff = 2hsi + wsi, the gate layout-area inefficiency of TG CMOS

relative to DG and FD/SOI CMOS when the undoped TG fin-body

dimensions are made comparable to the gate length (Lg) to ease the

fabrication [Doy03]. The bulk inversion noted here clearly worsens this TG

inefficiency. For more viable TG CMOS, with taller and thinner fins (and

wider Weff) as in Sec. 3.2, we further examine the layout-area efficiency,

now accounting for bulk inversion, as follows. For a given Lg and current

drive, corresponding to the gate area ASG = LgWg for a planar SG MOSFET

(e.g., an FD/SOI MOSFET), the area requirement for the (multi-fin) DG

FinFET is ADG = Lg[WgP/(hsifDG)], where P is the pitch and, with

reference to (3.4), fDG is the current-enhancement factor afforded by DG

relative to SG when hsi = Wg. Typically, fDG > 2 [Fos02], but we will

assume fDG = 2 here, which is tantamount to letting Weff = 2hsi for the DG

device. Then for the TG FinFET, we can express ATG = Lg[WgP/Weff(TG)],

where, phenomenologically, we define

Weff(TG) = 2hSi + Si(eff) (3.5)

because of the bulk inversion, wsi(eff) < wsi as defined, for fDG = 2, by the

simulation results in Fig. 3.3:










wSi(eff) 2hSi I o (3.6)
1 on(DG) -

For Rf = 3, (3.6) and Fig. 3.3 yield wsi(eff) = 4.2nm, much less than the

actual wsi = 13nm.

The required gate layout areas for the TG and DG FinFETs with

Rf = 3, relative to ASG, are plotted in Fig. 3.8 versus Lg; Lg and P were

obtained from the 2003 SIA ITRS [Sem03] projections for the HP (high-

performance) and LSTP (low-standby power) CMOS applications, and wsi

was set to Lg/2 (=Leff/2) for SCE control. For comparison, we include ATG/

ASG that results when wsi(eff) = wsi is assumed, i.e., when bulk inversion

is ignored as in [Yan05]. With this assumption the needed TG area is

underestimated by about 10% generally for both applications. The actual

layout-area ratios, with bulk inversion, show only a minimal benefit of the

third gate relative to DG-FinFET CMOS. For the DG technology relative

to the planar SG CMOS, the results in Fig. 3.8 are overly pessimistic,

showing, for example, >60% more area needed for DG FinFETs in the HP

application. Indeed, with fDG > 2, which is likely [Fos02], and Rf > 3, which

is doable, DG-FinFET CMOS can yield significantly better layout-area

efficiency than the SG technology [Yan05]. For example, Rf -- 5 alone

renders DG more area-efficient than SG.

The significance of bulk inversion implies much about nanoscale

FinFET characteristics and design. First, the commonly defined Weff is not

a valid indicator of relative values of current (and capacitance) in DG and


































0 10


30 40 50 60


Lg [nm]


Figure 3.8


Calculated gate layout-area ratios of TG and DG FinFETs
with Rf = hsi/wsi = 3, relative to the planar SG MOSFET,
versus gate length; Lg (=Leff) and pitch for the calculations
were obtained from the 2003 ITRS [Sem03] projections for
HP and LSTP CMOS technologies. The pessimistic area
requirements for the DG FinFET resulted from the
assumptions of low Rf and fDG (=2).


2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4


-ADG FinFET
e TG FinFET
HP a TG FinFET (wlo bulk inversion)




,-. a-BB B-B..


LSTP "----


IIIIIIIIIIIIIII


-Ba--B-B-B-- .









TG FinFETs; indeed, the additional Ion, and in fact loff, produced by the

top gate of the TG device are substantively smaller than what is implied

by Weff. Second, the top gate is really not needed for moderate Rf, which is

necessary for good layout efficiency. Third, the gate layout-area advantage

of the TG FinFET over the DG counterpart implied by Weff is actually

much smaller due to bulk inversion, and the DG area advantage over the

simple TG device with hsi wsi Lg, noted previously from the Weff

perspective [Yan05], is enhanced. Fourth, although we did not consider

quantization effects in this study, we surmise that they will actually

enhance the bulk-inversion effects because of the deeper inversion-charge

centroid in the quantum-mechanical solution [Ge02].

3.4 Summary

Three-dimensional numerical simulations of DG and TG

FinFETs having undoped thin bodies have revealed the significance of

bulk-inversion current in Ion, as well as loff, and the consequent

insignificance of the commonly defined effective gate width in

comparisons of DG and TG currents. In fact, we have inferred that the

proper Weff for DG FinFETs is hsi, which correlates with the total (surface

plus bulk) inversion charge; whereas a meaningful Weff cannot be directly

defined for TG FinFETs. The new insights revealed herein explain why

the DG FinFET provides nearly the same Ion as the TG counterpart for fin

aspect ratios as small as two, but especially for higher Rf which is

desirable and doable. Due to the relatively small increase in Ion of TG






56

FinFETs, over the DG counterparts with moderate Rf, the advantage of TG

devices in gate layout-area efficiency is not significant. The insights thus

further solidify our notion, based initially on Weff-implied TG layout-area

inefficiency [Yan05] (and on the fact that a TG FinFET, with a thin top

dielectric and moderate Rf, is more difficult to fabricate than a DG FinFET

[Mat05]), that the third top gate is neither desirable nor beneficial.














CHAPTER 4
MODELING AND SIGNIFICANCE OF FRINGE CAPACITANCE IN
NONCLASSICAL CMOS DEVICES WITH GATE-SOURCE/DRAIN
UNDERLAP

4.1 Introduction

Nonclassical nanoscale silicon CMOS devices, e.g., double-gate

(DG) and single-gate (SG) fully depleted (FD) SOI MOSFETs with

undoped ultra-thin bodies (UTBs), should be designed with gate-source/

drain (G-S/D) underlap [Tri05a]. The benefits of the underlap include

better control of short-channel effects (SCEs) via a gate bias-dependent

effective channel length (Leff) [Fos03c, Tri05a], as well as elimination of

gate-induced drain leakage (GIDL) [Tan05] and gate-drain/source

tunneling currents. The underlap, however, must be optimally designed

because it tends to increase the S/D series resistance (RsD) and decrease

Ion [She03, Tan05]. We show in this chapter, by device and circuit

modeling and simulation, that the implied underlap design tradeoff for

ultimate CMOS speed is affected significantly by parasitic G-S/D

capacitance, i.e., fringe capacitance, in nanoscale devices.

Fringe capacitance in classical MOSFETs, with G-S/D overlap,

was modeled some time ago [Shr82], and some modeling was recently

reported [Ban05] for DG MOSFETs with underlap. However, the modeling

of Bansal et al. [Ban05] focused on a bias-independent outer-fringe









capacitance, and did not address the VGS dependence of it as well as the

inner-fringe component, which is quite important in nanoscale devices.

Herein, using physical insights derived from numerical device

simulations, we develop a complete analytical model for parasitic

capacitance in nonclassical devices with G-S/D underlap, which includes

both the outer- and inner-fringe components with VGS dependence, as

well as a BOX-fringe component in the FD/SOI MOSFET. The new

modeling is verified by 2-D numerical device simulations. Further, the

model is implemented in our process/physics-based compact model UFDG

(Ver. 3.5) [FosOGa], and used in Spice3 simulations to check the benefit of

G-S/D underlap in reducing the fringe capacitance and DG CMOS

propagation delay. Based on physical insights attained, optimization of

the underlap design to effect the best tradeoff between the capacitance

and RSD for CMOS speed is exemplified at the Lg = 18nm technology node

of the SIA ITRS [Sem03].

4.2 Physical Insights from Numerical Simulations

4.2.1 Inner and Outer Fringe Capacitance

The dependence of the parasitic capacitance on VGS and on the

G-S/D underlap are reflected in Fig. 4. 1, which shows low-frequency, low-

VDs total gate capacitance (CG) versus VGS predicted by the 2-D device

simulator MEDICI [Med04] for an Lg = 18nm undoped-UTB DG nMOSFET

with and without underlap, and with and without a finite gate height (tg).

Because of the floating UTB and the negligibly small junction capacitance,














2.0

1.8

1.6

1.4


1.2
E
4- 1.0
4--

0.8

0.6

0.4


0.2


0.0
-0.2


Figure 4.1


0.0 0.2 0.4 0.6 0.8 1.0
VGS [V]

MEDICI-predicted low-frequency gate capacitance versus
gate voltage for an Lg = 18nm DG nMOSFET with (graded
NSD(y) in 20nm S/D extension with lnm straggle [Tri05a])
and without (abrupt NSD(y)) G-S/D underlap, and with and
without finite gate thickness; undoped UTBs with tsi=14nm,
tox=0.7nm, midgap gate.









which is in series with the intrinsic gate-to-body capacitance, the

subthreshold CG is defined exclusively by the extrinsic parasitic G-S/D

capacitance, which includes both inner- (Cif) and outer-fringe (Cof)

components [Ban05]. The same is essentially true for SG FD/SOI

MOSFETs with thick BOX [Kim05a]. For the tg = 0 simulations of Fig. 4.1,

Cof was forced to zero by removal of the spacer dielectric as well as the gate

stack from the device domain. Note first then in Fig. 4. 1 how significant

Cif and Cof are, relative to the on-state CG. (For the simulations we

assumed silicon-dioxide spacers. When they are silicon-nitride, which has

about a 1.8x-higher permittivity, Cof is even more significant than implied

in Fig. 4. 1.) For the tg = 0 cases, in which Cof = 0, note how the G-S/D

underlap significantly reduces the subthreshold CG, i.e., Cif, but makes no

difference in strong inversion (at low VDS). This reflects the screening of

the inner G-S/D fringing electric field by inversion charge, which forces Cif

(and the BOX-fringe capacitance, as we discuss later) to zero with

increasing VGS. (At high VDS, the reduced inversion charge near the drain

could undermine this screening effect, but for nanoscale devices, the

carrier velocity saturation tends to keep the inversion charge high enough

to make this undermining negligible.) Then, with finite tp, CG is increased,

with and without underlap, for all VGS by Cof. However, note that Cof is

smaller in the device with underlap in the subthreshold region, but not in

strong inversion. This reflects the shrinking Leff with increasing VGS due








to the decreasing Debye length defined by the strong-inversion charge: Leff

- Lg as VGS increases [Fos03c].

4.2.2 BOX Fringe Capacitance in FD/SOI MOSFETs

More insight is gained from the MEDICI-predicted subthreshold

(VGS = 0) CG versus undoped-UTB thickness (tsi) in Fig. 4. 2 for FD/SOI

nMOSFETs. For the assumed tg = 0 (Cof = 0), the increasing CG with tsi

reflects the dependence of Cif on tsi. However, note for all cases (different

Lg, with and without underlap) that CG for tsi -- 0 remains finite, even

though Cif must approach zero. Analogous to the short-channel effect of S/

D field fringing in the BOX [Tri03a], which can induce a leakage path near

the back surface, we infer that the finite CG at tsi = 0 in Fig. 4. 2 is

associated with the BOX-fringe capacitance (Cbf). Note that for increasing

VGS, Cbf, like Cif, will approach zero due to inversion-charge screening.

Based on the physical insights gained from Figs. 4. 1 and 4. 2, we

conclude that there are three basic components of parasitic fringe

capacitance in nonclassical devices with G-S/D underlap: Cof, Cif, and Cbf

as represented in Fig. 4. 3, all of which depend on VGS. Actually, Cbf as

shown in the figure for SG FD/SOI MOSFETs is an approximation for the

G-S/D capacitance supported by the fringing field in the BOX. More

exactly, this capacitance (per unit width W) is a series combination of Cbf

(as characterized in the next section), Cox = (eox/tox)Lg/2, and Cb = (eSi/

tsi)Lg/2 [Kim05a]. However, for typical thin tox and tsi, Cbf << Cox Cb, and

therefore this combination can be simply characterized as Cbf. We note








































1 2 3 4 5
tsi [nm]


Figure 4.2


MEDICI-predicted low-frequency subthreshold gate capacitance
versus undoped UTB thickness for SG FD/SOI nMOSFETs with
two different short gate lengths and assumed flat gate (tg = 0,
which means no outer-fringe capacitance), with and without G-S/
D underlap; tBox = 200nm, midgap gate.


0.30



0.25



0.20
E

0.15



0.10



0.05



0.00














Spacer Dielectric


Source/Drain


Gate
tg


LeSD


Si UTB


BOX

Cbf (for FD/SOI with thick BOX)


Figure 4.3


A schematic diagram of the gate-source/drain structure of a
nonclassical (DG or SG FD/SOI) MOSFET, indicating the G-S/D
underlap (with effective length LeSD) and the three components
of the parasitic fringe capacitance; Cbf is unique to the FD/SOI
device with thick BOX.









that Cof is defined predominantly by the gate sidewalls; the fringe

capacitance from the top of the gate is negligible for typical (high) tg. In

strong inversion, Cif and Cbf are effectively screened out, and Cof (with Leff

SLg) is the main parasitic. As Lg is scaled, the parasitic capacitance

becomes more significant, and hence modeling it is crucial.

4.3 Analytical Modeling

To model the parasitic fringe capacitance for SOI-based

nanoscale MOSFETs with G-S/D underlap, including DG and SG FD/SOI

devices, we extend the modeling in [Shr82] based on the insights gained

in Sec. 4. 2. The basic fringe-capacitance model stems from that defined by

two separated, conducting plates at an angle q as shown in Fig. 4. 4. A

solution of Laplace's equation in cylindrical coordinates for the electric

potential when a voltage V is applied as shown yields, via Gauss's law, the

charge (Q = CV) on the plates and the capacitance (per unit width) it

defines [Zah79]:


C Iln-) (4.1)


where e is the permittivity of the insulator between two plates, and r1, r2,

and 0 are the geometrical parameters defined in Fig. 4. 4. The fringing

field from the ends of the plates is ignored, assuming the plates are in

close proximity [Zah79]. To use (4.1) for the fringe-capacitance

components in Fig. 4. 3, the basic G-S/D structure is transformed to those

of Fig. 4. 5, depending on the underlap, or inversion condition: Fig. 4. 5(a)




















0


rl


Figure 4.4


r2


Basic two-plate model for fringe capacitance (per unit width in z),
with the cylindrical coordinates (r and 0) used in the analysis
shown.













(a)

LeSD

Oxide


oa


Gate tg


tox


Si -> Oxide


Source/Drain


Oxide


Source/Drain


Figure 4.5


c



Gate tg



b

tox
a ,o


Si UTB


Schematics of (a) the G-S/D underlap structure for the weak-
inversion analysis, with the reduced angle b defined after
replacing the higher-permittivity silicon with oxide [Shr82],
and (b) the abrupt G-S/D structure with no underlap for the
strong-inversion analysis.








approximates the underlap structure in weak inversion, with effective

LeSD, where Leff = Lg + 2LeSD [Fos03c, Tri05a]); and Fig. 4. 5(b) shows the

effective abrupt G-S/D structure without underlap in strong inversion,

with LeSD = 0, where Leff Lg [Fos03c, Tri05a]. (We are neglecting the

accumulation condition.) As illustrated in Fig. 4. 6 and described in

[Tri05a], LeSD is an effective underlap with an abrupt source/drain-body

junction as defined by the actual graded lateral doping profile NSD(y) with

finite straggle (GL) in the S/D extension; LeSD depends on OL, the extension

length (Lext), and tsi. In Fig. 4.5 (a), as was done in [Shr82], the plate-plate

angle has been reduced from n/2 to 3 to effectively account for the silicon

permittivity (esi) being about three-times that of the oxide (cox), which will

be assumed in the use of (4.1):

ox 7r
2Si P= 6 (4.2)
^Si t

Further, we assume that the spacer dielectric is silicon-dioxide. For

silicon-nitride spacers, cox in our results for Cof (in (4.3) and (4.6)) should

be replaced by the permittivity of the nitride.

For UFDG, the VGS dependence of the fringe capacitance (Cf) is

accounted for by modeling the various components in weak and strong

inversion, defining the corresponding charge components (i.e., CfVGs/D)

and assigning them to the proper terminals of the device, and then linking

the models across the moderate-inversion region defined by contour

boundaries in VGfS-VGbS space [FosOGb]. The links are ("2-D") cubic-
















1020 I --- --



1019 Abrupt NSD(Y)
w/ I LeSD=0 / GLI LeSDI


S1018 l NSD(y) I

Z



w/ effective
Leff(weak)
1016
LeSD LeSD


1015 I
25 35 45 55 65 75 85 95
y [nm]


Figure 4.6


Illustration of how varying the actual lateral doping density
profile NSD(y) in the S/D extension changes the weak-
inversion effective channel length, as characterized by the
effective G-S/D underlap LeSD indicated, which is defined by
GL, Lext, and tsi as described in [Tri05a].








polynomial spline functions of the two gate voltages for the terminal

charges. The UFDG accounting for the VGs-dependent Leff [Fos03c,

FosOGb, Tri05a] is similarly facilitated by such regional modeling.

4.3.1 Weak Inversion

In the weak-inversion region, the outer-fringe capacitance (Cofw)

can be modeled with (4.1) by defining, from Fig. 4. 5(a), rl=of=oc=LesD,

r2=ob+bg =tox+tp, and O=a=7c/2. For the inner-fringe capacitance (Cif) with

(4.1), rl=7o'c+cd=o'a+ab=tox/tanp+LesD, r2= 'c+ce=tox/sinp+tsi, and O=P3 in

(4.2). Thus,


C 2 g eSD t (4.3)
ofw 7r L eSD

and

6ox ( tox Sis }
C In cos + S sin (4.4)
f i oxcos + fLeSDsin

Note in (4.4) that, because of uncertainty in LeSD (used here for Cif, as

opposed to that used to define Leff [Tri05a]) due to the graded NSDO() in

real devices, we employ the tuning parameter fif by replacing LeSD by

fifLeSD, which can be thought of as an effective underlap length for Cif.

From numerical simulations, we find that fif is positive, and generally

comparable to but less than unity. To keep the model simple, yet realistic,

we have assumed LeSD 2 tox to get (4.3), and then to get (4.4) that LeSD is

less than or equal to tox(1-cosp)/sin3 + tsi = 0.27tox+tsi, since otherwise de

in Fig. 4. 5(a) is nonexistent (i.e., o'a+ab > o'c+ce) and Cif is undefinable








via (4.1). These assumptions do not limit the model utility since typically

LeSD > tox and LeSD < tsi [Tri05a]. In Fig. 4. 5(a), we also assumed that the

electric field from the region bf, including fringing field, does nothing to

Cofw and Cif since the gate generally suppresses accumulation charge in

the underlap region. However, when LeSD is large (> -4nm, which is

generally too long due to high RSD [Fos03c]), the effect from the region bf

is not totally negligible, and thus the model tends to underestimate Cofw

a bit.

For DG devices, the total parasitic G-S/D capacitance in the

weak-inversion region is approximated by parallel combination of (4.3)

and (4.4), applied for both gates coupled to both the source and the drain.

For SG FD/SOI devices, there is only the front gate, but the BOX-fringe

capacitance must be accounted for. Following our discussion in Sec. 4. 2,

still using (4.1), we can model Cbf in Fig. 4. 3 as indicated in Fig. 4. 7,

where the two plates can be defined by ab and cd. Thus, by defining

rl=bo=oc=LeSD/2, r2=ab+bo=oc+cd=LesD/2+Lg/2, and 0=y=7 we get


Cbf xIn C 1 + (4.5)
r LeSD


For weak inversion, as we noted previously, we can assume that (4.5)

couples the source/drain and gate directly, ignoring any tsi dependence,

since a series combination of Cbf, Cox, and Cb can be simply characterized

as Cbf due to Cbf<
MOSFETs, the total parasitic G-S/D capacitance in the weak-inversion
















Oxide


LeSD


Gate


Lg/2


I I
tox
Source/Drain Si UTB tsi
---------------- A-----------------------


BOX


Figure 4.7


Schematic of the SG FD/SOI MOSFET with G-S/D underlap,
showing how the BOX-fringe capacitance is modeled.








region is approximated by the parallel combination of (4.3), (4.4), and

(4.5), applied to both the source and the drain.

4.3.2. Strong Inversion

As explained in Sec. 4. 2, the outer-fringe capacitance in the

strong-inversion region (Cofs) should always be defined by an effective

abrupt gate-source/drain structure with LeSD = 0 as shown in Fig. 4. 5(b).

This means that Cofs can be expressed, as in [Shr82], with (4.1) by defining

ri=oa=ob=tox and r2=ob+bc=tox+tg with O=a=7c/2. Thus,


C 2 ln I 1+ (4.6)
ofs r t O)


Note here that the fringing-field effects due to region oa in Fig. 4. 5(b),

which was accounted for in [Shr82] quasi-empirically, is not significant

because tox is ultra-thin in nanoscale MOSFETs and the inversion charge

tends to obviate any accumulation charge in the oa region.

So, for strong inversion, where Cif and Cbf are negated by

inversion-charge screening, the parasitic capacitance, for both DG and SG

FD/SOI MOSFETs, is given by (4.6), applied to the gate(s) coupled to both

the source and the drain.

4.4 Model Verification

For model verification, an Lg = 25nm undoped-UTB SG FD/SOI

nMOSFET with midgap gate, and tox = Inm, tsi = 6nm, tg = 20nm, and tBox

= 200nm, along with the G-S/D underlap defined by NSD(y) in a 30nm S/D

extension with a 15nm straggle (which yields LeSD = 3.4nm for Leff in









UFDG [Tri05a]) is considered first. For this device in the weak-inversion

region (at VGS = OV), MEDICI predicts for the total S/D (i.e., S or D) fringe

capacitance, Cf= Cofw+Cif+Cbf = 0.111fF/pm, where Cofw = 0.039fF/pm, Cif

= 0.047fF/pm, and Cbf = 0.025fF/pm. In the strong-inversion region, Cf =

Cofs = 0.065fF/pm is predicted. For the same device, our analytical model

predicts, in weak inversion, Cf = 0.110fF/pm, which is the sum of Cofw =

0.04fF/pm, Cif = 0.047fF/pm with fif=0.64 in (4. 4), and Cbf = 0.023fF/pm,

while Cofs = 0.067fF/pm in strong inversion. The model predictions are

very good.

For an Lg = 18nm undoped-UTB DG nMOSFET with midgap

gate, and tox = 0.7nm, tsi = 14nm, and tg = 18nm, along with the G-S/D

underlap defined by NSD(y) in a 20nm S/D extension with an l nm

straggle (LeSD = 4.0nm for Leff in UFDG [Tri05a]), we get Cf= 0.125fF/pm

in the weak-inversion region (at VGS = 0V) from MEDICI, comprising Cofw

= 0.046fF/pm and Cif = 0.079fF/pm, while our model predicts Cf = 0.113fF/

pm, with Cofw = 0.034fF/pm and Cif = 0.079fF/pm with fif=0.85. In the

strong-inversion region, MEDICI predicts Cofs = 0.072fF/pm, which is also

predicted by our model. Again, the model predictions are very good, except

for Cofw, for which there is a 26% error. This relatively large error,

especially for DG devices, comes from the ignored bf region in Fig. 4. 5(a),

which might contribute to Cofw when Les is relatively large. Nonetheless,

our model overall agrees very well with the 2-D simulation results from

MEDICI, including additional ones for other SG FD/SOI (with Lg = 13nm








and LeSD = 2.7nm) and DG (Lg = 7nm and LeSD = 2.0nm) MOSFETs,

showing generally <15% errors. We note that the tuning parameter fif in

(4.4) tends to increase and approach unity with decreasing LeSD,

especially for DG devices. For short underlaps, the source/drain-body

doping profile tends to be more abrupt, removing uncertainty in LeSD.

4.5 Model Implementation in UFDG (Ver. 3.5)

Now, we implement the analytical model for parasitic fringe

capacitance in UFDG (Ver. 3.5) [FosOGa, Fos06b], with the VGS

dependence accounted for. The process/physics basis of UFDG, with

rigorous accounting for SCEs (via a 2-D solution of Poisson's equation in

the UTB), quantization (QM) effects (via a self-consistent solution of the

Poisson and Schrodinger equations in the UTB [Ge02] that describes the

bulk inversion [Kim05b]), and carrier transport in the UTB/channel (via a

QM-based mobility model [FosOGb] with carrier temperature-dependent

velocity overshoot [GeOl] and carrier injection-velocity defined ballistic-

limit current [Fos06b]), makes it quasi-predictive and hence useful for

projecting nonclassical nanoscale device/circuit performance. The

implementation was facilitated by the regional analyses for weak and

strong inversion used in UFDG, which are linked by ("2-D") VGfS- and

VGbs-based cubic splines for charge (and current) across the moderate-

inversion region defined by contour boundaries in VGfs-VGbS space

[FosOGb]. The UFDG accounting for the VGs-dependent Leff [Fos03c,

Tri05a] was similarly facilitated by the noted regional modeling.









Model implementation has been done as follows. At first, we use

a flag (CFF) to turn on (CFF = 1) and off (CFF = 0) the parasitic fringe

capacitance model. Then, tox + tg is compared to LeSD, and if it is smaller

than LeSD or tg is zero, Cof is set to be zero since Cof should be zero, while

(4.3) predicts a negative solution. When it is larger than LeSD, Cof is

calculated with (4.3). After the Cof calculation, Cif calculation will follow.

As mentioned in Sec. 4.3, the total parasitic G-S/D capacitance for DG

devices in the weak-inversion region is approximated by these two

components, i.e., Cof and Cif, applied for both gates coupled to both the

source and the drain. Here, it should be noted that the model is accurate

for a certain range as defined in Sec. 4.3, and thus LeSD should be set to a

proper constant value when it is out of the defined range. So, for LeSD <

tox, LeSD is set to tox for Cof calculations, while, for LeSD < 0.27tox, LeSD is

defined to 0.27tox for Cif calculations. Therefore, for abrupt case without

underlap, the model calculates Cof and Cif with LeSD = tox and LeSD =

0.27tox, respectively. These constant values are consistent with those in

[Shr82]. Also, when LeSD > 0.27tox + tsi, Cif is set to zero in UFDG, because

the model is not defined in this region. For SG FD/SOI devices, the BOX-

fringe capacitance is included in the total parasitic capacitance as

explained. Since the BOX-fringe capacitance is modeled with the

assumption that two conducting plates are placed separately, LeSD can not

be zero. Therefore, in UFDG, the minimum value of LeSD is set to 1.2nm,

which is empirically obtained from the numerical simulations.








4.6 Model Applications

We now use UFDG/Spice3 to access the effect of Cf on DG CMOS

speed and to check the benefit of an optimal G-S/D underlap on DG CMOS

speed, as well as show more verification of our fringe capacitance model.

To do this, we consider the HP45 technology node [Sem03] with Lg = 18nm

(and silicon-dioxide spacers). We assume DG MOSFETs (e.g., FinFETs

[Hua99]) with a midgap gate with tg = 18nm, and undoped UTBs with tsi

= Lg/2 = 9nm. (Actually, tsi = Leff/2 gives good SCE control [Yan05], so, for

devices with underlap, we are using thinner tsi than is needed. We do this

because we want to compare the underlap-device performance with that of

a well-tempered device without underlap, i.e., one with an abrupt S/D-

body junction for which Leff Lg.) Throughout the study, we generally use

the 2003 ITRS [Sem03] as a reference, except for tox and RSD

specifications. The gate leakage current can be controlled with thicker tox,

e.g., 1.Onm instead of 0.7nm given in the ITRS, enabling a pragmatic yet

optimal DG CMOS [Fos04b]. The G-S/D underlap region implies,

compared to the abrupt junction, higher RSD, which must include a

component (ARSD) defined by NSD(y). Note here that a more rigorous

design optimization study of the underlap will be given in chapter 5.

In Fig. 4. 8, UFDG-predicted gate capacitances versus VGS are

compared with those from MEDICI simulations for the DG nMOSFET,

with and without (abrupt NSD(y)) G-S/D underlap. Note here that for the

abrupt NSD(y) with LeSD = 0, (4.3) and (4.4) do not apply directly. However,

















o Abrupt NSD
Gradual NS
S --- LeSD=O w/
S LeSD=3.4n





.. ..- ..O _. .


(y) w/ MEDICI
D(Y) w/ MEDICI
UFDG
m w/UFDG o0

Q// /
0



0y


1.4


1.2



1.0



=- 0.8
U-
0
0.6


0.4


0.2


, , ,I i ,,i ,i I I , ,I I I , I ,I I


0.4
VGS []


Figure 4.8


UFDG- and MEDICI-predicted gate capacitance versus gate
voltage for the Lg = 18nm DG nMOSFET (tsi=9nm, tox=lnm,
tg=18nm, midgap gate), with and without (abrupt NSD(y)) G-
S/D underlap. For the near-optimal underlap, LeSD = 3.4nm
is defined by a graded NSD(y) in a 15nm S/D extension with
9nm straggle [Tri05a].


VDS=50mV


0.0 1
-0.


2


''''''''''''''''''' ''''''''''''''''''' ''''''''''''''''''' '''


A i


I









for cases like this, UFDG assumes finite values for LeSD that make (4.3)

and (4.4) reasonably consistent with [Shr82]. For the underlap case, a

near-optimal LeSD = 3.4nm, with regard to the Cf vs. RSD tradeoff, was

obtained from NSD(y) in a 15nm S/D extension with a 9nm straggle

[Tri05a]. As can be seen in the figure then, with fif tuned to give good

subthreshold CG matches, the predicted results are in good agreement

with those from MEDICI for both device structures, again showing the

benefit of the underlap in reducing CG in the weak-inversion region.

However, as shown by the UFDG (with RSD tuned to match Ion) and

MEDICI current-voltage predictions in Fig. 4. 9, on is slightly lowered by

the underlap due to higher RSD. (The QM and velocity overshoot options

were not used here because these effects are not modeled well in MEDICI)

Note also the substantive reduction in loff afforded by the underlap, which

is related to Leff > Lg [Fos03c, Tri05a]. There is indeed an underlap-design

tradeoff regarding loff (or Leff), Ion (or RSD), and CG (or speed).

For CMOS speed projections and optimal-underlap study, we

must ensure that ARSD is correlated properly with Leff and Cf, all of which

depend on NSD(y) in the S/D extension. We assumed that RSD is pragmatic

and constant (=120Q-Oim + ARSD) in the strong-inversion region, with

ARsD evaluated from the difference between the MEDICI-predicted Ion for

the underlap (with LeSD defined as noted) and the abrupt-NsD(y) devices,

as noted with reference to Fig. 4. 9. Then, with the total RSD defined, and

fif evaluated as noted with reference to Fig. 4. 8, we use UFDG (with the





79






10-2
1.0V
10-3
.... -- 9-..... --..... .. ... .. i

10-4 ,-* V S
VDS= 50mV


10-5


S106 0 Abrupt NsD(y) w/ MEDICI
S--- LeSD=0 w/UFDG
Gradual NsD(y) w/ MEDICI
10. 7 -,- LesD=3.4nm w/ UFDG





10-9



0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VGS [

Figure 4.9 UFDG- and MEDICI-predicted current-voltage
characteristics of the Lg = 18nm DG nMOSFET in Fig. 4. 7,
with and without the G-S/D underlap.








velocity overshoot [GeOl] and quantization [Ge02] options turned on) in

Spice3 to simulate a 9-stage unloaded DG CMOS-inverter ring oscillator.

The UFDG/Spice3-predicted propagation delays for different Lg = 18nm

device designs are plotted versus supply voltage (VDD) in Fig. 4. 10. For

comparison, results for a worst-case abrupt NSD(y) with G-S/D overlap

(defined as 10% of Lg) capacitance, as in classical MOSFETs, are included

in the figure. For this case, Cf is modeled as discussed for the abrupt-

NSD(y) device of Fig. 4. 8, and an overlap capacitance equal to ('ox/

tox)W(0.1Lg) is assumed at the source and drain. Note that such design is

ideal when only Ion or RSD is considered [Tri05a], but its speed is much

slower (41% longer delay) than that for the same device structure (i.e., tox

= Inm and tsi = 9nm) with near-optimal underlap. Even without any

overlap capacitance, which is not realistic, the abrupt-NsD(y) devices are

slower (5% longer delay) than those with underlap. Indeed then, the

reduction of CG afforded by well-tempered underlap translates to faster

CMOS speed.

We now explore optimization of the underlap design. As noted in

Fig. 4. 9, loff of the device with underlap is much lower than that of the

abrupt-NsD(y) device because of the better SCE control. We can thus

consider increasing tsi and/or tox to lower the threshold voltage (via

enhanced SCEs and less quantization [Tri03a]) and make loff roughly

equal to that of the abrupt-NsD(y) device. Increasing tsi alone may

increase Ion a bit, but it also increases Cif as indicated in (4.4) and as










































0.8 0.9 1.0
VDD [V]


Figure 4.10


UFDG/Spice3-predicted propagation delays versus supply
voltage of 9-stage unloaded DG CMOS-inverter ring
oscillators for five different variations of the Lg = 18nm
device design of Figs. 4. 8 and 4. 9, with and without the G-
S/D underlap. For the worst-case design, a G-S/D overlap of
10% of Lg was assumed. For the thick tox =1.5nm device
design, the VDD = 1.OV delay predicted with the G-S/D fringe
capacitance completely removed is plotted as well.


8.0


7.0


6.0


" 5.0


4.0

(U
Q 3.0


2.0


1.0


0.0
















- tox=1nm & tsi=9nm w/ UFDG
- tox=1.5nm & tsi=9nm w/ UFDG
.---. tox=lnm & tsi=12nm w/ UFDG
tox=1nm & tsi=9nm w/ MEDICI
o tox=1.5nm & tsi=9nm w/MEDICI
A tox=1nm & tsi=12nm w/ MEDICI


1.4


1.2



1.0


E
=- 0.8
U-
4--
0

0.6


0.4


0.2


0
DS 50m









VDs = 50mV


~I I I i ri ji ri ji I 'iji ri ri ri I I I i r r ri I I I I I I I I I i i ir j


0.4
VGS M


Figure 4.11 UFDG- and MEDICI-predicted gate capacitance versus gate
voltage for the Lg = 18nm DG nMOSFET with the G-S/D
underlap, for varying UTB and oxide thicknesses.


a
A A


0.0 1
-0.


2









shown by the UFDG and MEDICI simulation results in Fig. 4. 11. Thus, it

does not decrease the delay much as shown in Fig. 4. 10. In fact, the speed

is slightly degraded, except for low VDD where the Ion increase is more

significant. (Nonetheless, this thicker tsi = 12nm = Leff/2 is more

pragmatic technologically, still yielding good SCE control and speed

performance.) Increasing tox yields a more pragmatic benefit. For tox =

1.5nm, the delay is actually a bit shorter, as seen in Fig. 4. 10, because

both the intrinsic gate capacitance and the parasitic fringe capacitance

(mainly Cof in strong inversion) are reduced with increasing tox, as

reflected in Fig. 4. 11, while the channel current and Ion decrease at a

lesser rate because of bulk inversion and mobility enhancement [Kim05b].

However, the main benefit of thicker tox is not enhanced speed, but

restricted gate tunneling current and avoidance of a high-k dielectric,

without any speed degradation. For such pragmatic design, Fig. 4. 10

shows that the combination of thicker tox with near-optimal G-S/D

underlap yields 32% improvement in the CMOS speed at VDD = 1.0V

compared to that of the abrupt-NsD(y) design with typical G-S/D overlap;

it is even 9% faster than that of the ideal abrupt-NsD(y) design without

the overlap. (And, it could be made more pragmatic by using thicker tsi as

we have intimated.)

The impact of the parasitic fringe capacitance on the CMOS

speed is severe. To emphasize this finding, we include in Fig. 4. 10 the

UFDG/Spice3-predicted ring-oscillator delay at VDD = 1.0V for the









pragmatic tox = 1.5nm device design, but with Cf completely removed. The

result is dramatic. The delay is reduced from 2.7ps to 0.7ps, or by about a

factor of four! This result, which would be larger for common silicon-

nitride spacers, shows that typical G-S/D fringe capacitance in nanoscale

DG CMOS devices, even with optimal G-S/D underlap, plays a

predominant role in limiting speed.

4.7 Summary

Using 2-D numerical device simulations, we showed that the

parasitic fringe capacitances in nonclassical nanoscale MOSFETs, e.g.,

DG FinFETs, are significant, with important VGS dependence due to the

gate-source/drain underlap that in fact reduces the capacitance. With

physical insights from the device simulations, we developed an analytical

model for the parasitic capacitance, including inner- and outer-fringe

components, and a BOX-fringe component for FD/SOI MOSFETs, all with

dependence on VGS and on the underlap structure. The model was

verified generally by the numerical simulations, and implemented in our

process/physics-based compact model (UFDG-3.5). With UFDG in Spice3,

we showed, via ring-oscillator simulations, that reducing the parasitic

capacitance via optimal underlap design can be quite effective in

improving nanoscale DG CMOS speed, which is basically defined by a

tradeoff regarding the capacitance and source/drain series resistance.

Further, we showed that, for a given underlap structure, increasing the

UTB thickness tends to slightly degrade the device speed due to the









increased inner-fringe capacitance in the weak-inversion region (but still

could yield a good pragmatic design). However, increasing the gate-oxide

thickness, with near-optimal underlap, can give a pragmatically improved

DG CMOS design that avoids gate current and high-k dielectric, without

any speed degradation; if fact, we predicted that the speed can actually be

enhanced a bit. Such a pragmatic design is possible because increasing tox

reduces both the parasitic fringe capacitance and the intrinsic gate

capacitance, while decreasing the channel current and Ion less because of

bulk inversion and mobility enhancement.

Nonetheless, we stress the severity of the G-S/D fringe-

capacitance effect on speed shown by our simulations. We found that this

parasitic capacitance is predominant in limiting nanoscale DG CMOS

speed, even when moderated by an optimal G-S/D underlap. (This

statement applies to classical CMOS, without underlap, as well.) Indeed,

parasitic capacitance, as well as series resistance, are crucial issues in the

design of nanoscale CMOS.














CHAPTER 5
DOUBLE-GATE FINFETS WITH GATE-SOURE/DRAIN UNDERLAP:
APPLICATIONS ON SRAM CELL AND DESIGN OPTIMIZATION FOR
DEVICE SPEED

5.1 Introduction

Double-gate (DG) FinFETs with undoped ultra-thin bodies

(UTBs) are very attractive for scaled CMOS mainly due to their excellent

suppression of short-channel effects (SCEs), high on-state versus off-state

current ratio (lon/Ioff), and elimination of threshold voltage (Vt) variations

caused by statistical dopant fluctuation effects. Higher carrier mobility,

which comes from smaller transverse electric field and negligible impurity

scattering in the undoped UTBs, and much smaller parasitic junction

capacitance are the additional benefits of DG FinFETs. However, with the

ultimate limit of the UTB, i.e., 5nm [Tri03a] due to severe quantization

effects and technological difficulties, DG FinFET scaling to and beyond

the HP25 node with the physical gate length (Lg) of 10nm [Sem05] seems

to be extremely difficult since the fin width (wsi) required for SCE control

is wsi = Leff/2 [Yan05] if high-k gate dielectric is not viable. Thus, for

further gate length scaling to and beyond 10nm, DG FinFETs have to be

designed with gate-source/drain (G-S/D) underlap [Tri05a]. Even for the

Lg > 10nm regime or/and when a reliable high-k gate dielectric is

developed, the underlap structure should be quite useful in the device









design for effecting an optimal SCEs versus Ion trade-off [Kra06, Lim05,

Tri05a].

The benefit of an underlap structure in the DG FinFET should be

most useful for SRAM applications. This is because the read static noise

margin (read-SNM) and write-margin are not defined by the absolute

value of Ion, but by Vt and the relative strength of Ion among the

transistors in SRAM cell. Note here that Vt can be easily increased by SCE

control, with some degradation of Ion, via the effective channel length

(Leff) modulation in the weak-inversion region [Fos03c]. Also, note that

high Vt tends to give large read-SNM and write-margin based on the large

inverter trip point, and small cell leakage currents or standby power due

to small loff [Guo05]. On the other hand, for the device speed issue, we

confirmed that the optimally designed underlap [KimOG] can reduce the

propagation delay by limiting the fringe capacitance (Cf) in weak

inversion. However, this design approach is virtually based on the trade-

off between Ion and the parasitic capacitance in weak inversion. Therefore,

with regard to the device speed, broader study about the underlap

optimization is needed.

In this chapter, we first explore SRAM cell design and scaling via

DG FinFETs with G-S/D underlap. For this study, DG FinFETs with the

underlap are first characterized in terms of Vt with various extension

length (Lext), straggle (oL), and wsi via 2-D numerical [Med04] and

analytical simulations [FosOGa]. The relationship between Vt and read-

SNM is verified to define an optimal SRAM cell, for the HP45 node with