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Dedication  
Acknowledgement  
Table of Contents  
List of Tables  
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Abstract  
Introduction  
Circuit and operation  
Steadystate analysis of SRM  
Dynamic analysis of SRM  
Experimental verification  
Summary and future work  
References  
Biographical sketch 



Table of Contents  
Title Page
Page 1 Page 2 Dedication Page 3 Acknowledgement Page 4 Table of Contents Page 5 Page 6 List of Tables Page 7 List of Figures Page 8 Page 9 Page 10 Page 11 Abstract Page 12 Page 13 Introduction Page 14 Page 15 Page 16 Page 17 Page 18 Page 19 Page 20 Page 21 Page 22 Page 23 Page 24 Page 25 Page 26 Page 27 Page 28 Circuit and operation Page 29 Page 30 Page 31 Page 32 Page 33 Page 34 Page 35 Page 36 Page 37 Page 38 Steadystate analysis of SRM Page 39 Page 40 Page 41 Page 42 Page 43 Page 44 Page 45 Page 46 Page 47 Page 48 Page 49 Dynamic analysis of SRM Page 50 Page 51 Page 52 Page 53 Page 54 Page 55 Page 56 Page 57 Page 58 Page 59 Page 60 Page 61 Page 62 Page 63 Page 64 Page 65 Page 66 Page 67 Page 68 Page 69 Page 70 Page 71 Page 72 Page 73 Page 74 Page 75 Experimental verification Page 76 Page 77 Page 78 Page 79 Page 80 Page 81 Page 82 Page 83 Page 84 Page 85 Page 86 Page 87 Page 88 Page 89 Page 90 Page 91 Page 92 Page 93 Page 94 Page 95 Page 96 Page 97 Page 98 Page 99 Page 100 Page 101 Page 102 Page 103 Summary and future work Page 104 Page 105 References Page 106 Page 107 Page 108 Page 109 Page 110 Biographical sketch Page 111 

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HYSTERETIC MODULATION FOR POINT OF LOAD APPLICATION By SANTANU K. MISHRA A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006 Copyright 2006 by Santanu K. Mishra To My Grandparents ACKNOWLEDGMENTS I will like to express my sincere appreciation to my advisor, Dr. Khai D. T. Ngo, for his excellent academic guidance and continued financial support and my coadvisor, Dr. William R. Eisenstadt, for his helpful discussions, guidance, and kindness. I would also like to thank Dr. Vladimir A. Rakov and Dr. Oscar D. Crisalle for serving in my supervisory committee. I am very grateful to University of Florida for the fellowship that helped me start my research and Intersil Corporation for its financial support and projects. My special thanks go to my friends Jairaj Payyapalli, Rohit Badal, and Chandrasekhar Venkataraju for their constant encouragement. My sincere appreciation goes to my colleagues in Florida, Paiboon Nakmahachalasint, Bharath Kannan, and Jason Bullard for their helpful discussions. I would also like to thank my colleagues Mr. Steve Zhou and Mr. James Perry at International Rectifier for the helpful discussions and suggestions. Last but not the least, my very special thanks go to my parents and my uncle for being constant sources of inspiration throughout my life. My heartfelt appreciation goes to my wife, Madhumita, for her love and encouragement during the course of preparation for the defense. TABLE OF CONTENTS A C K N O W L E D G M E N T S ..............................................................................................................4 LIST OF TABLES ................. ........................ .. ........... ........................................ 7 L IST O F F IG U R E S ......................................................................... ................................... . 8 A B S T R A C T ............... ................................................................ .......................................... 12 CHAPTER 1 INTRODUCTION .................................. .. ........... ..................................... 14 R research B ackgrou n d ................. .......................................................................................... 14 Unique Requirements for POL Converters....................................................................... 16 Different Control Options for POL Converters................................................................ 16 Constant Switching Frequency Pulsewidth Modulation........................................... 17 Variable Switching Frequency Pulsewidth Modulation ........................................... 17 V 2c o n tro l S ch e m e ...........................................................................................................1 8 E enhanced V 2control Schem e......................................... ......................... ............... 19 F ocu s of T his D issertation ................................................... ............................................. 19 2 CIRCUIT AND OPERATION .................................................................... ................ 29 Circuit R ealization for the SRM .................................................................. ................ 29 A alternate Form of SR M R ealization ........................................... ....................... ............... 30 R ip p le S y n th e siz e r ..................................................................................................................3 1 Hysteretic Comparator.. ............................................ 32 Sufficient Condition for Proper SRM Operation................................................................. 33 3 STEADYSTATE ANALYSIS OF SRM .........................................................................39 C o n tro l L a w ............................................................................................................................ 3 9 Com m andtoduty Transfer Function ....................................... ...................... ................ 40 Sw itching F requ en cy ...................................................... ................................................ 4 1 Steadystate M odeling of SR M ..................................................................... ................ 42 D design E x am ple ...................................................................................................... ........ .. 4 3 4 DYNAMIC ANALYSIS OF SRM.................................................................................50 C ontroltooutput Transfer Function ....................................... ....................... ................ 50 Output Impedance .................................. .. ........... .....................................52 Audio Susceptibility .................................. .. .......... ............................. 55 L o o p G ain ............................................................................................................. ........ .. 5 5 In p u t Im p ed an ce ..................................................................................................................... 5 6 SR M D esign C riterion .............................................................. ..................................... 56 Transient M odeling of SR M ................ ........... ..................... .... ................ 58 Transient Modeling of the Synchronous Buck Converter ................................................ 59 Factors Affecting Transient Response............................................................................ 60 L o o p D e sig n ....................................................................................................................6 0 Trace Impedance .............................................................................................................61 Optimizing Dynamic Response for the SRM .................................................................... 61 5 EXPERIMENTAL VERIFICATION............................................................................. 76 SRM Design Based on Conventional Design Methodology ............................................... 76 C onv erter D esig n ............................................................................................................. 7 6 M o du lator D esig n ..................................................... ............................................... 7 8 D ynam ic D design ..............................................................................................................79 Filter Capacitor Requirement for Transients....................................................... 80 Feedback L oop D esign .................................................................. ............... 81 SR M C condition C heck ....................................................................... ............... 8 1 S im u la tio n ................................................................................................................8 2 Prototype D esign and Test Setup ........................................................ ................ 82 E x p e rim e n t ...............................................................................................................8 3 SRM Design with Optimizing Transient Response............................................................. 84 S p e c ifi c atio n : ...................................................................................................................8 4 P ow er Stage D esign : .................................................. .............................................. 84 U FE T Turnon Instant: .......................................................... ............ ... ....... .. ...... .. 85 D esign of the M odulator: ................................................ ........................................... 85 C om pensator D esign ........................... ............................................ 86 6 SUMMARY AND FUTURE WORK .......................................................... 104 L IST O F R E F E R E N C E S ....................................................... ................................................ 106 B IO G R A PH IC A L SK E T C H ........................................... ...................................................... 111 6 LIST OF TABLES Table page 11. Steadystate Operational Characteristics of Variable Frequency PWM ............................21 21. Relevant Specification of Opamp used in the design ............................. ..................... 34 31. Semiconductor Components used for Fabrication ................ ....................................45 32. D esign Procedure for E xam ple 1 ........................................ ....................... ................ 45 51. D esign Procedure for Exam ple 2 ........................................ ....................... ................ 87 52. Part Specification for D esign Exam ple 2...................................................... ................ 87 5.3. SRM Design Example for Optimal Transient Behavior................................................. 88 LIST OF FIGURES Figure page 11. Schem atic of distributed pow er architecture................................................. ................ 21 12. Schem atic of interim ediate bus architecture.................................................. ................ 22 13. Power supply regulators and its application domain. ...................................................22 14. Single phase synchronous buck converter .................................................... ................ 23 15. Interleaving of phases in a synchronous buck converter. .............................................23 16. A conventional P W M ................................................... .............................................. 24 17. Average current mode control implementation as a conventional PWM .........................24 18. Voltage hysteretic modulation and control waveforms. ......................... ..................... 24 19. Current hysteretic modulation and control waveforms ................................................25 110. Constanton time modulation and control waveforms..................................................25 111. Constantoff time modulation and control waveforms. ................................................25 112. V2control architecture ..................... .. ........... .....................................26 113. Operational waveforms of the V2control architecture.................................................26 114. Enhanced V 2control architecture ...................................... ....................... ................ 27 115. Impact of supply voltage variation on the enhanced V2control architecture.................27 116. Output voltage ripple with a low ESR capacitor ..........................................................28 21. Synchronous buck converter controlled by the SRM. ..................................................34 22. O operational w aveform s for the SR M ................................................................................. 35 23. Alternate way to realize the synthetic ripple modulator ..............................................35 24. Operational waveforms for the alternate synthetic ripple generator...............................36 25. Simplified implementation of Rowland voltage controlled current source....................36 26. Rowland voltage controlled current source with reduced feedback error ......................37 27. Im plem entation of hysteretic com parator .................................................... ................ 37 28. The switching waveforms of the hysteretic comparator...............................................38 29. The SRM operating condition with (dVcmd/dt )> (dVmod/dt). ......................................... 38 31. DC schematic of the SRM driving a synchronous buck converter.................46 32. Impact of delay on the control signal and switching frequency. ..................................46 33. Average modeling of the SRM driven buck converter................................................... 47 34. Step response comparison between average and realtime simulation...........................47 35. Experimental validation of the SRM design in example 1 ............................................. 47 36. The control and gatedrive signals with a higher hysteresis voltage ...............................48 37. Effect of reduced hysteretic window on the switching frequency................................48 38. Commandtooutput transfer function with a 7 A load.................................................49 39. Switching frequency as a function of the hysteresis voltage ........................................49 41. Sm all signal m odeling of the SR M ..................................... ...................... ................ 64 42. Controltooutput transfer functions of the SRM with design parameters in Table 32....64 43. Controltooutput transfer functions with load variation ..............................................65 44. Open loop output impedance of the SRM with parameters in Table 31 ................. 66 45. Open loop output impedance variation with filter capacitor ........................................67 46. Closed loop output impedance can pose resistive output impedance. (Type 2 compensator: R1=630, C2=600n, R2=10 K, C3=200 pF ) .............................................67 47. Impact of change in Vin on the output voltage for the SRM.........................................68 48. Effect of low and high frequency input noise on the output voltage Vo......................... 68 49. Basic philosophy of the loop design for faster transient response................................69 410. Type 2 com pensator and its sm all signal m odel ........................................... ................ 69 411. Input im pedance characteristics of the SRM ................................................ ................ 70 412: L arge signal behavior of the SR M ............................................................... ................ 71 413. Response of synchronous buck converter to load transient..........................................71 414. Synchronous buck converter response to load transient...............................................72 415. Impact of crossover frequency on the load step response.............................................72 416. Output voltage sense options for a POL ....................................................... ................ 73 417. Impact of distribution impedance on load transient and voltage regulation...................73 418. Automatic voltage positioning of output voltage helps transient design........................74 419. Optim izing large signal response of the SRM .............................................. ................ 74 420. Compensator design for optimum SRM dynamic response. .....................75 51. Miller injected turnon mechanism in a synchronous buck converter...............................89 52. Carefully gatedrive layout reduces the negative spike on the Vphase. ..........................89 53. Tight decoupling of the buck converter is essential to reducing noise on the Vphase. Sensitivity: 5 V /div and 500 ns/div...................................... ...................... ................ 89 54. The power converter design with gatedriver supply. ..................................................90 55. Transconductance am plifier im plem entation................................................ ................ 90 56. H ysteresis voltage generator........................................................................... ................ 91 57. Hysteretic level generator, comparator, and PWM latch circuit..................91 58. Controltooutput transfer function for the system in Table 5.1..................................92 59. The com pensator design for the SRM in Table 51......................................... ............... 92 510. L oop response of the design ................................................................... ................ 93 511. The ripple voltage on Vo, Vmod, and Vcmd for the designed system. ..............................94 512. Implementation of SRM driven synchronous buck using PSpice. ................94 513. Stepdow n transient sim ulation of SRM ....................................................... ................ 95 514. Stepup transient sim ulation of the SRM ...................................................... ................ 95 515. Prototype of the VRM with synchronous buck converter driven by the SRM ................. 96 516. Prototype test fixture for the V R M .................................................................. ................ 96 517. Steadystate perform ance for design exam ple 2 ........................................... ................ 97 518. Load release response of the SR M ....................................... ...................... ................ 97 519. Load stepup response of the SR M .................................................................. ................ 98 520. Fast response of the lower FET with the SRM to load release...................98 521. Fast response of the upper FET with the SRM to load stepup ...................99 522. V mod response to load stepup ...................................................................... ................ 99 523. V mod response to load release ...................................... ......................... ................ 100 524. Computation of output voltage characteristics to load release. ................................ 100 525. The controltooutput transfer function of the optimized design................................101 526. Loop design for the optimized design...... ............ .......... ..................... 101 527. Stepdown response of the optimized design........................................102 528. Stepdown response without the optimized design...... .... ................................... 102 529. Stepup response of the optimized design. ...... ... .......................... 103 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy HYSTERETIC MODULATION FOR POINT OF LOAD APPLICATION By Santanu K. Mishra December 2006 Chair: Khai D. T. Ngo Cochair: William R. Eisenstadt Major Department: Electrical and Computer Engineering Advancement in semiconductor technology has enabled the modem communication and data processing integrated circuits (ICs) to improve speed and integration density. The power supply to these ICs is continually required to deliver power at lower voltage and with stringent regulation requirements. Dynamic behavior of the power supply is normally improved by feeding the dynamic variables, such as the inductor current and the output voltage of the converter, into the pulse width modulator (PWM). Very fast dynamic response can be achieved by using both the peak and valley of the output voltage ripple to determine the switching instants, leading to the class of hysteretic modulators. The requirement to have lower supply voltage for the ICs also tightens the output voltage ripple requirement. In order to meet these requirements, capacitors with small equivalent series resistance (ESR) are used. This makes the natural output voltage ripple of the supply very small and corrupted for proper hysteretic operation. This dissertation describes a modulation scheme for modulator carrier wave generation from converter voltages with added dynamic variables. The resulting hysteretic modulator, identified here as the synthetic ripple modulator (SRM), allows proper hysteretic operation even with very small and noisy output voltage ripple. The steadystate operation of the SRM is derived and experimentally validated. Critical design parameters affecting the steadystate operation, such as the switching frequency, are quantified and validated. Small signal modeling technique is applied in order to characterize the dynamic behavior of the modulation scheme. Design equations are developed to device a comprehensive design technique for optimized transient response with minimum number of output capacitor. Average models are developed to help predict the steadystate and dynamic behavior of the modulator for faster simulation with minimal computational time. A synchronous buck converter with a 10.5 V input and 1.8 V/15 A output rating is designed to verify the steadystate and dynamic equations. The response of the VRM to dynamic load transition is verified with a 15 A load current step at a slew rate of 15 A/'s. Transients results show a 65 mV stepdown overshoot and a 37 mV stepup undershoot in output voltage, which matches very closely with the perdition. Results prove the superior response speed of the SRM without the inherent problems of the conventional hysteretic modulators. CHAPTER 1 INTRODUCTION Research Background The everadvancing field of data processing and communication poses new challenges for power supplies in these systems. The integrated circuit (IC) chips are continually powered by lower supply voltage. The low supply voltage not only increases the speed and integration density of the IC, but it also reduces the power consumption per clock cycle [14]. The increase in speed and integration density poses a high slew rate load for the power supply [510]. The fast dynamic characteristics and low supply voltage make the voltage regulation more difficult in a centralized power system in which power to the ICs and processors is supplied from a single supply far away from the load. In order to tightly regulate the output voltage under static and dynamic load conditions, dedicated power supplies of different voltage and current ratings are located near to the load. The impact of parasitic impedance between the power supply and the load on voltage regulation is reduced by this architecture [1113]. For highend computing and data communication applications, multiple processors are commonly used on one motherboard. Each processor demands very high current at a very low voltage. In order to efficiently supply power to this system, distributed power architecture (DPA) is used, as shown in Figure 11 [1416]. This architecture is comprised of a number of isolated voltage regulator modules (VRMs) powered from a 48V fully or quasiregulated rail. Each microprocessor is powered from a fully regulated isolated VRM in proximity. In order to reduce the cost and size of the power delivery system, intermediate bus architecture (IBA) is sometimes preferred, as shown in Figure 12. This system uses only one isolated power supply, which is known as the "bus converter". Depending on the application, the bus converter can be unregulated, semiregulated, or fully regulated [1718]. Several non isolated pointofload (POL) power supplies are powered from this bus converter and located near the load. The advantages of an IBA over a DPA can be summarized as follows: * Lower overall cost * Smaller board area * Higher efficiency * Higher reliability * Faster transient response Various topology choices are available for POL, as shown in Figure 13. A low dropout regulator (LDO) can be used when the differential voltage between the input and output is small, and the output current requirement is below 6 A. The LDOs exhibit poor dynamic performance. With an increase in the power rating and voltage conversion ratio, switching regulators prove more efficient. Apart from the location of the power supply with respect to the load, the choice of control strategy and number of output capacitor also have a significant effect on the dynamic performance of the POL [1920]. As the real estate on a motherboard is limited and expensive, it has prompted a significant research effort on devising new control schemes which will require a lower output capacitor without compromising dynamic response. Ultimately, any control scheme and capacitor configuration need to adhere to the stringent requirements that the POL has to satisfy, which can be summarized as follows: * High power density * High current density * Low output voltage deviation in both steadystate and transient load condition * Very low output voltage ripple * Small size * Lightweight by using smaller filter inductor and capacitor * Improved thermal performance and efficiency Unique Requirements for POL Converters Most POLs with output load demand above 6 A use the synchronous buck topology. The schematic and fundamental waveforms of this topology are shown in Figure 14. The output voltage is determined by the fraction of a switching cycle, DTs, for which the top switch is on. The bottom switch receives the complement of the top switching signal with some delays to avoid grounding of the supply. The inductor and the capacitor form the low pass filter for this topology. As the power output increases, a single phase synchronous buck topology becomes highly inefficient due to increased losses, and it requires a large number of output capacitors to meet the dynamic requirements, which make it impractical [2124]. The amount of output capacitor and filter size for a high output load can be minimized by employing the interleaving technique in a multiphase architecture. The interleaving technique, as shown in Figure 15, is implemented by connecting many single phase converters in parallel and phaseshifting their switching. The primary advantage of this technique is the decreased magnitude and increased frequency of the output voltage ripple. Current sharing between phases is very important for this architecture in order to maximize the thermal performance and reduce the stress on any particular phase. The master control IC normally ensures equal current distribution and phase shifting of the phases. The overall power rating of the output load decides the number of interleaved phases [2527]. Different Control Options for POL Converters There are many control techniques to choose from for a POL, depending on the design requirements. The basic approach in any control technique is to vary the switching time of the top switch in a synchronous buck converter in such a way that the output voltage follows a constant reference voltage. This section discusses some of these control techniques and their implications. Constant Switching Frequency Pulsewidth Modulation The voltage mode control is the most common control technique for a switching converter. In this scheme, a constant frequency ramp is compared with a constant Vcmd signal through an analog comparator to generate the switching pulses for the top switch. The fundamental waveforms and the expression for duty ratio are shown in Figure 16 The constant Vcmd signal is the output of a high gain error amplifier, which has the output voltage and a constant reference as its input. This scheme is optimized for regulation of output voltage and is not the best in terms of dynamics [2830]. In order to outperform the conventional pulsewidth modulation (PWM) approach in terms of speed, converter dynamic variables can be injected into the feedback loop. The average current mode control, as shown in Figure 17, is one such example. The inductor current is sensed and fed back to an error amplifier which compares this sensed current with a constant reference voltage. Similar to the conventional PWM, the output of the current error amplifier is compared to a constant frequency ramp. Unlike conventional PWM controllers, the average current mode control has two feedback loops. The inner loop is the current feedback loop, known as the "modulation loop." The outer loop is the voltage feedback loop, known as the "regulation loop" [3133]. Variable Switching Frequency Pulsewidth Modulation The operating frequency is loaddependent for this class of PWM. At light load the reduction in switching frequency improves the efficiency. Other advantages include superior transient response, low audio susceptibility, and simpler dynamics [34]. Figure 18 shows the voltage hysteretic modulation scheme [3536]. The basic idea is to use the output voltage ripple as a PWM ramp. The peak and valley of the ramp are used to generate the switching instants with the help of a hysteretic comparator. In order to make the switching immune to noise, a higher hysteretic window needs to be used, making the output voltage ripple bigger. Unlike voltage hysteretic control, current hysteretic modulation uses the sensed inductor current as the PWM ramp, as shown in Figure 19. In a constant ontime control scheme, the on time of the upper switch is fixed and the offtime is decided by a constant reference and slope of the PWM signal [3739]. Figure 110 shows the sensed current signal used as the ramp. The external ramp signal can also be used for this modulation scheme. Figure 111 describes the constant offtime control technique in which the offtime of the upper switch is constant and the ontime is varied according to a reference voltage. The switching frequency, commandtoduty ratio, and the control law for the previously mentioned variable frequency modulators are delineated in Table 11. As the equations suggest, the switching frequency is a function of input voltage Vin and output voltage Vo for all these variable switching frequency schemes. It can also be seen that the output voltage has a linear dependence on the command signal Vcmd. V2control Scheme The V2control scheme uses a combination of an output voltage ripple and an external ramp to generate the triangular carrier waveform for the PWM [4041]. Another modification of this scheme uses only the output voltage ripple in combination with a hysteretic comparator to generate the PWM signal for the buck switches. The basic circuit and operational waveform of this control technique are shown in Figure 112 and Figure 113. Since the output voltage is affected by the load transient, the level of the ramp changes with load. A step change in the ramp signal affects the duty cycle immediately before the slow error amplifier can react. Enhanced V2control Scheme As an enhancement to the V2 control technique, the enhanced V2control technique uses the sensed inductor current instead of the external ramp signal [42]. The schematic of this scheme is shown in Figure 114. The slope of the inductor current is affected by the input voltage. Any variation in the input voltage therefore affects the duty cycle within one cycle as shown in Figure 115. The use of output voltage for the PWM ramp ensures an excellent transient performance, which is similar to the V2control technique. Focus of This Dissertation As previously described, the next generation of POLs tends to use fewer output capacitors to save motherboard space. It also tends to use a capacitor with lower electrostatic resistance (ESR) to minimize output voltage ripple. In a power supply employing lower ESR capacitors, the output voltage ripple is not a triangular wave. Figure 116 shows the output voltage ripple of a power supply with a low ESR capacitor. The parabolic segments are created by the integration of triangular current by an ideal capacitor and jumps are created by equivalent series resistance (ESL). The peak and valley of the ripple therefore no longer coincide with the switching instants and with small peaktopeak magnitude, the noise susceptibility increases. This dissertation describes a modulation scheme for a modulator carrier wave generation from converter voltages with added dynamic variables. The resulting hysteretic modulator, identified here as the "synthetic ripple modulator" (SRM), allows a proper hysteretic operation even with a very small and noisy output voltage ripple. The steadystate operation of the SRM is derived and experimentally validated. Critical design parameters affecting the steadystate operation, such as the switching frequency, are quantified and validated. Small signal modeling technique is applied in order to characterize the dynamic behavior of the modulation scheme. Design equations are developed to devise a comprehensive design technique for an optimized transient response with a minimum number of output capacitor. Average models are developed to help predict the steadystate and dynamic behavior of the modulator for faster simulation with minimal computational time. Chapter 2 describes the basic circuit and operation of the SRM. This section also describes all the individual blocks to realize the SRM. Chapter 3 discusses the designoriented steadystate design equations for the SRM. The commandtoduty transfer function and switching frequency are quantified. Average models are developed and design methodology for this modulator is presented and verified using a 1.8 V/10 A prototype. Chapter 4 quantifies the dynamic behavior of the SRM. The small signal commandto output, audiosusceptibility, and output impedance equations are developed. These equations are used to design the feedback loop. The transient behavior of the SRM and its dependence on the design factors are also described in this section. Chapter 5 presents a comprehensive design solution for the modulator. A 1.8 V/ 15 A prototype is used to verify the developed design equations. Experimental verification shows a very good resemblance between the theory and practical results. Table 11. Steadystate Operational Characteristics of Variable Frequency PWM Modulator Switching Frequency CommandtoDuty Ratio DC Control Law Voltage f, =1 V VV esr V hysteretic V d) L VVm Vcmd V Current f =1 V* D = Vcmd *Ro V K * Hysteretic K) L K* V cmd Ro Vd + *T *K2 K K2 *D'*To Constant Vo 1 D cmd 2L 1 Vcmd R 2 '*L Vo onTime V To 1 To KR 2 *on S R 2*L Constant Vo 1 D = Vd =K2 +K2 * off Time Vn(1 To K*2 V 1 md o 2 L f R*(o 2*L 48 V  ~IsolatedE VEENpP Isolated VRM I in. ~IsolatedVR LI] Figure 11. Schematic of distributed power architecture. Figure 12. Schematic of intermediate bus architecture Multi Phase Synchronous Buck Vm vo 1 2 2 5 ........................................................................................... ............................................................ Single Phase Synchronous Buck Vm Vo 6A. c r Small (VinVo) Large Figure 13. Power supply regulators and its application domain. Vn=12 V Top Switch L Vgj VgL 7> 1L Bottom Switch j<> D.Ts ........ Vin L212~ Figure 14. Single phase synchronous buck converter. V n=12V Top Switch L rL ase V 12 2 itrol phase , t Si 01 Interleaved. Bottom Switch Phases .. .... ... I Vin=12 V V r er Vo Ripple S1 esrC trol phase  1o2 Figure 15. Interleaving of phases in a synchronous buck converter. VoD. i n Vcmd Vmod mod /WV JUL D Vcmd Dk Vp k Figure 16. A conventional PWM. Current EN^ Vcmd Figure 17. Average current mode control implementation as a conventional PWM. Vcmd +Vhys/2 d 4  cmdVhys/2 Hysteretic a +sr V a Comparator Vcmd Figure 18. Voltage hysteretic modulation and control waveforms. cmd Vin _n :7 E Vi n 1 2 oI Vcmd +Vhys/2 O in K 2.iL S cmd Vhys/2 Hysteret L Comparator Vcmd Figure 19. Current hysteretic modulation and control waveforms. V7 n Comparator Vcmd !I '! Figure 110. Constanton time modulation and control waveforms. Vcmd: "i" Constan L Co Toff Comparator Vcmd Figure 111. Constantoff time modulation and control waveforms. Ir Vef Voltage EA Figure 112. V2control architecture. Vcmd Figure 113. Operational waveforms of the V2control architecture. mod Q Load Release E i Voltage EA I ref Figure 114. Enhanced V2control architecture. mod cmd Figure 115. Impact of supply voltage variation on the enhanced V2control architecture. Figure 116. Output voltage ripple with a low ESR capacitor. CHAPTER 2 CIRCUIT AND OPERATION This chapter describes the fundamental operation and operational waveforms of the SRM driving a synchronous buck converter. The basic building blocks for the SRM are described, and the condition for proper operation of the modulator is analyzed. Circuit Realization for the SRM Figure 21 shows the schematic of a synchronous buck converter driven by the SRM. The gatedriver is fed from the output of the SRM. The gatedriver generates a complementary gate drive signal that drives switches of the synchronous buck converter. As previously described, the basic idea is to generate an artificial ripple which enables proper hysteretic mode operation, even when the natural ripple of the output is small, corrupted, and buried under a lot of noise. The artificial ripple is synthesized by regenerating the voltage across the inductor with a definite gain and adding it to the output voltage. The regeneration of this voltage is performed by feeding the voltage across the inductor into a transconductance amplifier, the output of which is fed into a resistor capacitor network level shifted by the output voltage. The main constituents of the SRM are a ripple synthesizer and a hysteretic compactor. In more general terms, the ripple synthesizer is essentially an integrator formed by a trans conductance amplifier with gain gmMod and a capacitor Cmod. The voltage across the Cmod is the synthetic ripple being sought. This ripple is stacked on the output voltage Vo to generate the modulating signal Vmod for the hysteretic comparator. As shown in Chapter 1, the carrier waveform needs to be piecewise linear in order to exhaust an ideal hysteretic PWM operation. As shown in Figure 22, the synthetic ripple is piecewise linear and triangularly shaped compared to the natural output voltage ripple. This triangular modulation signal results in smooth single point intersection of the hysteretic limits and the carrier wave for proper commutation of the power switches. The carrier magnitude can be controlled to have a much higher amplitude than the natural ripple. Under ideal operating conditions, the hysteretic limits are placed symmetrically around the reference signal Vcmd [43]. The rising edge of the synthetic ripple defines the ontime of the top switch UFET, whereas the falling edge defines the freewheeling interval during which the bottom switch LFET is on. The resistor, Rcmod, absorbs the DC current generated by the transconductance amplifier from the DC voltage across the inductor. Thus, Rcmod and inductor DC resistance rL provide the low frequency gain of the integrator. It will be shown later that the low frequency gain can be used to control the DC performance of the modulator. Even though voltage across the inductor is used to generate the carrier wave for the ripple regulator, in general, any AC converter waveform can be used for this carrier wave generation. The AC converter waveform can also be bonded to virtually any variable that needs to be regulated to realize fast and linear dynamic response [44]. Alternate Form of SRM Realization An alternate way of realizing the SRM is shown in Figure 23 [45]. Instead of sensing the voltage across the inductor, a pseudo buck converter is realized within the control circuit itself. When the PWM is high, the top fieldeffect transistor (FET) conducts. The control circuit imitates this behavior by having a differential voltage of (VinVo) across the transconductor, which creates the positive slope of Vmod. Similarly, when the bottom FET is turned on, the voltage across the transconductor is given by (Vo), which in turn creates the negative slope for Vmod. The advantage of this circuit is that no inductor current sensing is required. The operational waveforms are shown in Figure 24. It can also be noted that the lower hysteretic levels are defined as the Vcmd, which is the output of the voltage error amplifier. The switching frequency can be varied by changes in the Vhys signal. One of the major drawbacks of the architecture is that the output voltage is not added to the synthetic ripple at the output of the transconductor. This eliminates the load current feed forward mechanism, which is a major catalyst for good dynamic performance. Because the circuit does not use any high frequency signal from the converter, it is very easy to implement on a chip. Ripple Synthesizer The Howland current pump [4647] is an extremely versatile way to realize a transconductance amplifier, as shown in Figure 25. The simplest scheme uses one Opamp and four resistors. The relationship between the output current and input voltages can be expressed as Imod = (V V)x V + (2.1) Proper matching of external resistors is very important for this configuration to reduce feedback error. As shown in Figure 26, an extra Opamp can be used to minimize this feedback error. The expression for the output current in terms of the differential input voltage can be derived as Io = (V V ) X x 1 (2.2) R2 + 2R1 R This circuit is used for the implementation of the ripple synthesizer. Few design criteria need to be followed while designing the transconductance amplifier for this application. The input voltage to the ripple synthesizer is a high frequency switching signal. The amplitude of this signal varies between the differential voltage (VinVo) and Vo every switching cycle because most of today's POL applications use only one bias power supply, the following basic design rules must be followed for proper operation of the ripple regulator. * At any given instant in a switching cycle, the voltage at the input and output nodes for the Opamps in the ripple regulator must be within the common mode input range and output voltage swing specification. * The bandwidth of the Opamps must be sufficiently larger than the switching frequency of the buck converter. For example, a 1 MHz switching frequency buck regulator should use Opamps with bandwidth 30 MHz or above. * The slew rate of the Opamp must be sufficient to support the high frequency input of the ripple regulator. * The input bias currents Ibias for the Opamps must be much smaller than the output current Imod. This will ensure ideal operation of the ripple regulator. Based on the characteristic and design criteria of the SRM either AD8065/8066 or AD8057/8058 is chosen as the Opamp for the ripple regulator. To reduce a mismatch error, precision 1% resistors are used. The important characteristics of the Opamp with a single 5 V bias are shown in Table 21. Hysteretic Comparator The hysteretic comparator for this application is implemented using a twocomparator circuit, as shown in Figure 27. The advantage of this circuit is that the hysteretic voltage Vhys can be varied as per design requirements. The operational waveforms of this comparator are given in Figure 28. The adder and subtractor circuit generate the upper and lower hysteretic levels for the SRM, respectively. These levels are compared with Vmod to generate the set and reset signal for the NAND flipflop. The inputs of this flipflop are inverted. The output of this flipflop is the PWM signal for the gates of the synchronous buck converter. As with any comparator and digital circuit, there is a finite amount of delay from the modulation voltage Vmod to the PWM output Vpwm. This signal is fed into the gatedriver which has its own delay due to the large capacitive load posed by the input of the power FET. Sufficient Condition for Proper SRM Operation A sufficient condition for an ideal operation of the SRM is that the slope of Vcmd should be much smaller than the slope of Vmod. This condition arises from the fact that the output voltage of the error amplifier Vcmd could contain the amplified output voltage ripple. As a result, this signal may not be a purely DC signal, and it contains the switching frequency noise. If the noise is large enough, it will result in an undesired commutation of the power switches. Figure 29 shows a condition where the slope of Vcmd is more than that of Vmod. The sufficient condition for proper PWM operation for the SRM can therefore be identified as dvmod dcmd (2.3) dt dt The condition of having the slope of Vmod less than that of Vcmd is useful when it is desired to prolong the ontime of any of the switches. It can be shown that the condition in (2.3) is satisfied when: Gfg (f )< d L) (2.4) modmod "Lo Rmod nlod L (2.5) mod GfEA(fs) =Gain of the error amplifier at the switching frequency esrCo= ESR of the filter capacitor for the power stage gmMod= Transconductance of the ripple regulator In summary, this chapter presents the basic building blocks of the SRM. The nonidealities of the blocks, that are critical to fundamental SRM operation, are delineated. Alternate architecture to generate the synthetic ripple is presented. The design condition, for ideal PWM operation of the SRM, is described in form of a design equation. Table 21. Relevant Specification of Opamp used in the design Parameter AD8066 AD8057 3db Bandwidth 155 MHz 325 MHz Common mode Input Voltage range 02.4 V 0.93.4 V Input Bias Current 5 pA 0.5 A Output Voltage Swing 0.03 V4.95 V 0.9 V4.1 V Slew rate 160 V/us 700 V/us r q I UFET Lo Buck' IE__ F 0. IT esi T esr Hysteretic Gj Ripple Comparator  Synthesizer Figure 21. Synchronous buck converter controlled by the SRM. Vcmd Vphase Figure 2 Vcmd +Vhys/2 Vmod ......... ...... r.. ......... hy s ,' cmd Vhys/2 I V.. I V.... Xo . Vo 2. Operational waveforms for the SRM. Vi n E 1 L 2rL V _ mparator hys UT Vmod G + UT m  i, a Vin Comparator T Vcmd Figure 23. Alternate way to realize the synthetic ripple modulator. V hys Figure 24. Operational waveforms for the alternate synthetic ripple generator. R R V2 OPAMPOU VI R Rnod R Imod 4 Figure 25. Simplified implementation of Rowland voltage controlled current source. V phase Figure 26. Rowland voltage controlled current source with reduced feedback error. Comparator 1 UTm Vmod+ q V \v2 Vcmd Comparator 2 "suu Figure 27. Implementation of hysteretic comparator. Vm o d+ sil S! Figure 28. The switching waveforms of the hysteretic comparator. ............J Vmod .  C & VecmdVh vs ... . Figure 29. The SRM operating condition with (dVcmd/dt)> (dVmod/dt). CHAPTER 3 STEADYSTATE ANALYSIS OF SRM The analytical results for the steadystate operation of the SRM are derived in this section. The DC control law, commandtoduty transfer function, and switching frequency equations are derived in terms of the modulator design parameters ( gmMod, Vhys, Rcmod, Cmod) and converter parameters (rL, L etc.), assuming there is continuous conduction mode (CCM) operation of the synchronous buck converter. Control Law The control law for the SRM describes the relationship between the output voltage Vo and the command signal Vcmd. Figure 31 shows the DC schematic of the SRM, which can be used to derive the steadystate performance of the modulator. In the last section, the steadystate waveforms of the SRM are described, assuming there is an ideal operation of the modulator. In practice delays in the comparator, gatedrivers, and nonideal switches result in operational waveforms shown in Figure 32. The time periods ti and ti' are the delays incurred by the non ideal behavior of the circuit. As a result, Vmod is no longer confined between Vmod+ and Vmod and has a new peak identified as Vmod++ and Vmod. The differential (Vmod++Vmod+) is larger than (VmodVmod) for POL applications, where Vo is much smaller than Vin. Effectively, Vcmd changes to VcmdE and Vhys changes to VhysE. By definition VcmdE (Vmod++ Vmod) (3.1) 2 'hysE mod++ mod (3.2) Using Figure 32, the equations for the command and hysteresis signal are derived as Vcm =Vcmd mod (( Vo)t, V t) (3.3) 2. Cmod VhyE = Vh + gmod ((V Vo)t +V .t) (3.4) Cmod If the delays ti and ti' are comparable, VcmdE>Vcmd when Vin>2Vo, VcmdE Vin<2Vo. It can also be concluded from (3.4) that the overall hysteresis voltage is dependent on the input voltage Vin, assuming a comparable delay of t and ti'. The DC control law can be derived by equating the DC value of Vmod and the DC value of VcmdE and is given by: Vcm = Vo + Io x (rL gnMod Rcmod) (3.5) The above equation identifies the droop resistance as Rdroop = rL gmMod Rcmod (3.6) Using (35) and (36), the relationship between Vo and Vcmd can be expressed as follows. Vo VcmdE (3.7) + R droop It can be seen that Vo varies linearly with VcmdE and is load dependent. As shown in (3.5), the SRM naturally implements droop control with Rdroop being the droop resistance. The design of feedback loop is generally facilitated by the linear relationship between Vo and Vcmd. Commandtoduty Transfer Function The commandtoduty transfer function describes the switching intervals for the synchronous buck converter in terms of the modulator parameters and input voltage. The minimum and maximum switching time that can be achieved by the modulator varies depending on the control circuit, nonidealities such as delay time, bandwidth limitation, common mode range, and output swing for Opamps. The commandtoduty transfer function gives an insight into this switching period and helps the design around these extremes. The basic relationship between the duty and output voltage for a synchronous buck converter is expressed as D =v (3.8) Vn Using (3.7) and (3.8), the equation for the duty cycle can be expressed in terms of the command signal as follows: D V md (3.9) VnX + R 2 The duty cycle D is inversely proportional to the Vin and load current. If the switching frequency is fixed, this equation provides an insight into the extreme Vin and load current that can be supported by the modulator. Switching Frequency The switching frequency is inversely proportional to the switching time Ts. Using Figure 3 2 it can be shown that T =ton + toff = VhE (3.10) dv dvm mod mod dt dt where dVmod VmMod in )o (3.11) dt Cmod dvmod mMod o V (3.12) dt Cmod Substituting (3.11) and (3.12) into (3.10) yields the steadystate switching frequency expression as f 1 Vo Vo gmMod (3.13) S_ VhysE Cmod The switching frequency is inversely proportional to the hysteresis voltage VhysE and the ripple regulator capacitor Cmod. The transconductance and input voltage have direct proportionality to switching frequency. Unlike V2control, the switching frequency is not dependent on the converter parameters. It can also be noted that the SRM is a variable frequency modulator and its switching frequency varies with the change in output voltage. This characteristic is of particular importance for POL application because the power supply generally encounters high slew transient load, which causes an instantaneous change in the output voltage during transient. Another important advantage of having a variable frequency modulation is that the switching frequency reduces at light load when the converter goes into the discontinuous conduction mode. This improves the light load efficiency and elongates the battery life. Steadystate Modeling of SRM The average models can result in a reduced computational time in simulation and enhance the design cycle speed. The average model for the SRM is shown in Figure 33. The model describes the modulator as a high gain Opamp, which forces its input to be at the same potential. The synchronous buck converter is modeled with the popular threeterminal model [4849]. The output of the high gain Opamp essentially generates a voltage to make Vcmd and Vmod equal and is fed to the model of the converter. Figure 34 shows the comparison between the realtime model and the average model to a step change in Vcmd. The response of the average model to this step change in command signal Vcmd is similar to the response of the realtime model, but with a significant reduction in computation time. It is worth noting that the model is valid both under time and frequency domain which facilities the realtime and AC analysis of the modulator. Design Example The theory derived in this chapter is verified using a design example. The designed modulator drives a synchronous buck converter. The design of the SRM starts with the assumption that the power converter has already been designed, and the discrete semiconductor components used to implement the control blocks are known. The discrete semiconductors used for the design are tabulated in Table 31. As outlined in Table 32, Vhys is selected first. In this case for this example, the hysteresis voltage is chosen much larger than the steadystate output voltage ripple on Vo, 20 mV. In order to verify the design equations, Vhys was swept between 150 mV and 1.1 V although 0.7 V is listed in Table 32 as a nominal value. The transconductor is designed such that the output current is much larger than the bias current. For this example, the output of the transconductance amplifier has a minimum Imod of 135 iA, which is much larger than the sum of all the bias currents. To demonstrate that the SRM could provide more droop resistance than the resistance of the inductor, 40 mQ is specified for Rdroop. The droop resistance is used to calculate the Rcmod using (3.6). The switching frequency was swept between 300 kHz and 1 MHz although 420 kHz is specified as a nominal value in Table 32. The total delay ti is approximated from the datasheet to be 100 ns. The experimental waveforms shown in Figure 35 confirm this delay term. Using (3.4) and (3.13), Cmod was found to be 270 pF. Finally, Vcmd is found from (3.3) and (3.5) to be 2.12 V. As will be shown later, this voltage will automatically be set by an error amplifier by comparing the output voltage to a DC reference voltage. Figure 35 shows the switch node voltage in comparison to the control signals. When the top FET is turned on, the level of Vphase equals the input voltage Vin, which is 9.5 V for this design. A 100ns delay is observed between the instant Vmod intersects Vmodand the rise of switching node as predicted in Table 32. The rising and falling slope of the Vmod signal is observed to be 2.13 V/is and 0.5 V/ .is respectively, as predicted by (311) and (312). Apart from the high frequency noise due to parasitic impedances, the phenomena underlying the derivations of the design equations are indeed observed on the experimental waveforms. Figure 36 shows the control signals and the gatedrive signals for the top and bottom FET of the synchronous buck converter, with a higher value of hysteresis voltage. The maximum value of the bottom FET gate signals equals the 5 V gatedrive voltage provided by the gate driver. However, the maximum value of the top switch gatedrive is about 14.5 V, which is 5 V higher than the Vin. The levelshift for the top FET gatedrive is provided by a bootstrap circuit, which is comprised of a diode and a capacitor, and is part of the gatedriver design. The effect of reduced Vhys on the switching frequency is shown in Figure 37. With a hysteretic voltage of 0.3 V (VhysE=0.7 V), the switching frequency increases to 585 kHz. The relationship between the Vcmd and Vo is shown in Figure 38. As the command signal reduces, there seems to be a bias current mismatch in the ripple regulator which contributes to an increase in the transconductance. The overall error is less than 10 %, which confirms a good correlation between the experiment and the theory. The measured relationship between fs and Vhys is compared with the theoretical one, as shown in Figure 39. As the hysteresis voltage reduces, the noise exhausts significant impact on the switching frequency making it slightly higher than the predicted value. Table 31. Semiconductor Components used for Fabrication Parts Attributes Opamps AD8057 (SR: 1000 V/ts, BW: 325 MHz; Ibias=0.5 tA; Analog Comparator LT1720 (Delay: 13 ns; Ibias: 6 [iA; Linear Tech.) FlipFlop 74 ACT11074 (Delay: 9 ns; Texas Instruments) Gatedriver HIP 6603B (Delay: 30 ns; Transition time: 50 ns; Intersil) Table 32. Design Procedure for Example 1 Parameter Design Method Value Vo Specified 1.8V Vh Vo Ripple< gMod gmodVo>>Total Bias Current 75 [is RIpx Specified 40 mQ ri L Specified 5 mQ 1 tH R." Using (3.6) 107 kQ t Specified 420 kHz Vil Specified 9.5V t, Datasheet and measurements 100 ns Cnrd From (3.4) and (3.13) 270pF Lo Specified 10 A Vari From (3.3) and (3.5) 2.12V I Vcmd Figure 31. DC schematic of the SRM driving a synchronous buck converter. Ymod++ Vmod+     'VcrndE Vcmd r I mod V      Figure 32. Impact of delay on the control signal and switching frequency. Figure 33. Average modeling of the SRM driven buck converter. 0_0 10u 20u 30u 40u 50u 60u 70u 80u 90u lOOu Figure 34. Step response comparison between average and realtime simulation. TeK S OOMSo~s SOS AcqS Ch3 5.00 V % 50 mV 1.OOJAS Figure 35. Experimental validation of the SRM design in example 1. Tek m 50.sOMS/s I Ch3 s.OOV 1igl 10.0 V V Figure 36. The control and gatedrive signals with a higher hysteresis voltage. a 5.00 V Ch4 500mV 0 2 500mV 500ns Figure 37. Effect of reduced hysteretic window on the switching frequency. 61 Acqs T 1.8 1.7 1.6 1.5 > 1.4 1.3 1.2 1.5 1.6 1.7 1.8 1.9 2 Vcmd #Theory Exp Figure 38. Commandtooutput transfer function with a 7 A load. 1200  1000  800 o  0.1 0.26 0.4 0.66 0.7 0.856 Vhy3(V) 1 1.16 IExp  Prediction Figure 39. Switching frequency as a function of the hysteresis voltage. Vhys,=0.7 V : ._ _/L ^ CHAPTER 4 DYNAMIC ANALYSIS OF SRM The SRM is required to maintain a tight load regulation even under high slew rate load transitions. This chapter describes the design parameters that affect the dynamic performance of the SRM. The chapter starts with the derivation of controltooutput transfer function, which is instrumental in the design of the feedback loop. The audio susceptibility of the modulator is analyzed and verified. The output impedance characteristics of the modulator in open loop and closed loop configuration are derived. These results are used to design the voltage loop for stable operation and a fast transient response. The large signal transient behavior of the modulator and the synchronous buck converter are described. The design factors affecting the dynamic response of the modulator are identified. An optimized design methodology to obtain a very fast transient response is also described. Controltooutput Transfer Function The controltooutput transfer function is the small signal relationship between the command signal and the output voltage [29, 5052]. The control method for the SRM is dependent on the inductor current and output voltage. The inductive impedance responsible for the generation of inductor sense current is given by: z, (s) = r + s L (4.1) The output impedance of the synchronous buck converter is given by: zo(s)= R // + esrCo, (4.2) The load current is represented by the load resistance Ro. The output capacitor is represented by the filter capacitance Co and the equivalent series resistance esrCo. The output impedance of the transconductance amplifier is given by: Zmod (S) = Rcmod /i (4.3) Referring to Figure 41, the small signal expression of the carrier wave Vmod is given by: Vmod 0 o +l [ZL (S) g* g d Zmod(S)] (4.4) For a synchronous buck converter, the relationship between the inductor current and the output voltage is given by: v IL o (4.5) As the input voltage to the hysteretic comparator track each other it can be expressed as Vmod = cmd (4.6) The expression is valid for frequency range much below the switching frequency, and it is unable to predict the subharmonic behavior. The modeling technique is therefore sufficient for loop design for the SRM. Using (4.4)(4.6), the expression for the controltooutput transfer function is given by: G (s) = _vo z (S) (4.7) Vcmd Zo (s) + ZL (S) gMod Zmod (S) Assuming a minimum value of Ro>>esrCo, the above expression for the controltooutput transfer function can be expressed as Gq(s) G= / + /+ YOe .. + SO)mod) (4.8) C 1+s 1 + RP++ +s,2+.r 1 + oop SRo +Rdroop) esr mod Odroop o Ro +Rdroop) *esr mod Co droop) where G Ro (4.9) Ro +Rdroop )er CI (4.10) esrC CO Cdroop = (4.11) )mod = (4.12) RCmodCmod o)o (4.13) The two zeros for this transfer function originate from the filter capacitor and the ripple regulator. The zero originating from the filter capacitor is at a very high frequency due to very low ESR. Figure 42 shows the comparison between the theory and the experimental results with parameters of Table 32. The results show the cancellation of a pole and a zero resulting in an effective single pole response. Figure 43 shows the effect of the load on the transfer function. With an increase in the load, there is a reduction in the low frequency gain of the transfer function, as can be deduced from (4.9). The increase in the load also results in a reduction in the dominant pole frequency. Due to an effective single pole response for the controltooutput transfer function, the loop design becomes very simple for this modulator. Output Impedance The open loop and closed loop output impedance of the modulator are derived in this section. The open loop output impedance transfer function is derived by setting the command signal Vcmd to a DC voltage. The overall philosophy is to inject a small signal current into the output node and compare it with the output voltage variation, as shown in Figure 41. The output voltage expression is given by: o = zo(s)(io +i) (4.14) The expression for the inductor current can be obtained from (4.4) by setting the small signal variation of the command signal to zero. =7 (4.15) L (L (s) gMod Zmod (S)) (4.15) Replacing (4.15) into (4.14) the open loop output impedance is derived as Z o ,) = ZoLo + + ) + oop (4 .16) olK 1+s + k + Roo o + S Ro Rd. roop Ro +Rdp Mesr Mmod Mdoop Mo Ro + Rroop esr Nmod Mo Mdroop where ZL = o droop (4.17) Ro +Rdroop The open loop droop resistance Rdroop is defined in (3.6). Figure 44 shows the validation of the open loop impedance derived above. The circuit parameters are shown in Table 32. The low frequency characteristic of this equation is dictated by the parallel combination of load resistance Ro and droop resistance Rdroop, as shown in (4.17). The high frequency characteristic is dictated by the parallel combination of Rmod and ESR of the filter capacitor. A low frequency zero originates from the DC resistance (DCR) rL and the inductance L of the filter inductor. The second zero results from the ESR and the filter capacitor Co and is at a very high frequency due to very low ESR. The two poles are close to each other and make the overall open loop output impedance a single pole response. Ideally, the overall output impedance is expected to be resistive in order to facilitate that the modulator meets the adaptive voltage regulation requirements [53]. Figure 45 shows the impact of variation in filter capacitor on the open loop output impedance. With the increase in filter capacitor, the first zero moves to the left and the poles move to the right, and they help reduce the output impedance variation over frequency. The closed loop output impedance can be derived by taking into account the frequency response of the voltage error amplifier (VEA) on the command signal Vcmd. The relationship between the command and the output voltage is given by: Vcmd = GfA (s) (4.18) For type 2 compensation, GfEA(S) can be expressed as 1+0) Gif (s) = G  s 1+ S cop C =(R, C2 = (R2 C ), G o =R C2))C3 (4.19) The previous equation can be combined with (4.4) and (4.14) to find the expression for the closed loop output impedance as follows (z, (s)) (Z(o ZL gMod mod (4.20) z CL (L gJMod Zmod)+ Zo (1 G(sA (S)) Combining (4.2), (4.3), and (4.20), the expression for the closed loop output impedance is found out as Ro droop. 1+ 1+ (ZO, (s))CL = droop (4.21) Rdroop 1+ 1+ S +Ro. 1+ 1+S [1 GFEA(S)] O)droop o 0)J )mod ) )esr) In the above equation, GFEA is the compensator transfer function and it can be designed to achieve the requisite closed loop output impedance. Low frequency behavior is dictated by the droop resistance and the high frequency characteristics by the ESR of the filter capacitor. Figure 46 shows the comparison of open loop and closed loop output impedance. It also signifies the impact of compensation design on the closed loop impedance [54]. Audio Susceptibility The effect of input voltage variation on the output is minimal for the SRM due to the feed forward of the input voltage through the inductor current. As shown in Figure 47, any change in the input voltage results in a change in the slope of Vmod effectively changing the duty cycle. For example, if there is an instantaneous increase in the input voltage, the duty cycle is reduced within one switching cycle and minimizes the impact on output voltage. Using (4.4) and (4.14), it can be shown that the audio susceptibility of this modulator is zero. Gvg (s)= = 0 (4.22) Vg i' 0 1'cmd=0 Experimental verification proves the instantaneous response of the control circuit to a sudden change in input voltage, as shown in Figure 48. The injected input voltage noise consists of both low frequency and high frequency variations. The high frequency noise seems to impact the output voltage as it is much higher than the switching frequency and the converter is unable to respond to this kind of noise. Loop Gain The loop gain expression is determined by combining (4.8) and (4.19) as follows: G + s) = __1+_+ /_modIaJ (Gs) (4.23) S1 + R droop s t troop l+s dro od + Odroop + ) +droop mod .o 1 + droop ) This expression is used to design a fast and stable feedback loop for the SRM, as shown in Figure 49. The basic philosophy is to design the compensation in such a way that the zero of the compensator cancels out the single pole posed by the controltooutput transfer function. This can be effectively done by a type 2 compensator, as shown in Figure 410. The small signal model for this compensator is also shown. Because reference voltage Vref is the DC voltage desired at the output, it has little impact on the small signal response. Input Impedance The input impedance is an extremely important parameter for POL application. As delineated in Chapter 1, the output of the bus converter acts as a supply for a number of POLs. The input impedance of the POL therefore gives an understanding into the loading of the output bus converter. As the excitation for this impedance is same as the audio susceptibility, Vo is a constant. The input impedance for the SRM can be derived from the power conservation equation. in n out out The small signal perturbation of this equation can be expressed as follows: Vn in + In vn = 0 Therefore, the input impedance is derived as (4 .2 4 ) 'in =0 in Vo lo The above equation defines the input impedance of the SRM as a constant with an 1800 phase shift. The impedance characteristic is load dependent. With a higher load, the input impedance reduces. The input impedance characteristics for the example presented in Chapter 3 is shown in Figure 411. With an increase in load current the input impedance reduces. SRM Design Criterion In Chapter 2, the sufficient condition for proper PWM operation of the SRM was identified. This condition is quantified in terms of the parameters of the modulator and the converter in this section. The peaktopeak ripple on the command signal is the magnified version of the output voltage ripple through the voltage error amplifier. This can be expressed as Avcmd = G (fw ) Avout (4.25) GEA(fsw) = Gain of the compensator at the switching frequency Avout = Output voltage ripple The peaktopeak ripple on the output of the transconductance amplifier can be expressed in terms of the transconductor gain as Avmod = Gmod (fsw(AL) (4.26) Gmod (fsw)= Ripple regulator gain at the switching frequency (AiL) = Inductor current ripple As per the condition of proper PWM operation G A (fw) Avout < Gmod ( ) (AL) (4.27) Assuming the ripple output voltage ripple to be much smaller than the inductor current generated ripple at the output of the transconductance amplifier, the above expression can be expressed as follows Gf (fsw) The gain of the transconductance amplifier at the switching frequency is expressed as 1 Gmod (sw) = sL x god x = Rmod (4.29) SCmod The above equation assumes that at the switching frequency sL>>rL and (1/s.Cmod) << Rcmod. Using (4.28) and (4.29), the condition for the SRM design is derived as G (f) < mod (4.30) esrC 0 The output voltage ripple is assumed to be much smaller than the magnitude of the Vmod signal. In fact, that is one of the most important design criteria for proper hysteresis operation and a significant factor in development of this class of modulators. This equation quantifies the condition for proper operation of the SRM. Modern POLs are required to use less real estate on a motherboard, which limits the number to buck output capacitors. In order to further reduce the esrCo, highquality ceramic capacitors can be placed in parallel to the buck capacitor. Transient Modeling of SRM In this section, the response of the SRM to a high slew rate transient is analyzed and quantified in terms of switching time and switching frequency variation. During steadystate operation, the inductor current has an average component and a high frequency ripple component. The average component equals the output load current. Typically, the ESR of the capacitor is much smaller than the output load resistance. The high frequency ripple current in the inductor is therefore completely absorbed by the capacitor. This creates the output voltage ripple given by: Av, = esrCo AiL (4.31) Because the current in the inductor cannot change instantaneously when a sudden load step is applied, the differential between the inductor and load current is absorbed by the filter capacitor. The impact of load stepdown on the transient performance is shown Figure 412. When the load is stepdown instantaneously, the differential DC current between the inductor and the load flows through the ESR of the filter capacitor, causing it to increase by (esrCo.Alo) [55]. This causes a sudden reduction in the turnon time of the top FET, which has the effect to reduce the inductor current and reestablish the balance between the load and the inductor current. The change in one time is given by: At on = ton ton, (4.32) At esrC t esrC (433) Kt o t on d + erC(4.33) Note that the change in ontime for this modulator occurs even before the voltage error amplifier can respond. As the differential load current flow dictates the dynamic behavior of the SRM, it is referred to as the "load current feedforward mechanism." It should also be noted that there is a change in the switching frequency as a response to the load transient. A similar response is expected during load stepup. Transient Modeling of the Synchronous Buck Converter The design of the LC filter for the POL is often based on the load transient requirements and efficiency rather than the output voltage ripple. Assuming infinite bandwidth of the feedback loop and instantaneous transient response of the modulator, the synchronous buck converter can be modeled, as shown in Figure 413. Based on the models, the rate of change in the inductor current during stepup and stepdown transient can be expressed as (diL ) n ) (4.34) dt stepup diLl (4.35) Sdt )stepdwn L The input voltage for the POL is much larger than the output voltage. The rate of the rise of inductor current during stepup is therefore much faster than that during stepdown. Therefore, the stepdown transient dictates the number of output capacitors for certain transient specification. Figure 414 shows the response of the synchronous buck converter to load transient. The transient response of the output voltage can be divided into two parts. The step change in output voltage is the result of the ESR of the filter capacitor. The relatively slow push back to regulation is due to the output capacitor charge storage differential. The net change in output voltage change is expressed as AVomax = AVoap + (Alo esrCo) (4.36) This equation can be used to estimate the output capacitance required to meet a specific load regulation requirement as derived below CO (1 (Ao)2. L (4.37) 2 ( Vo) .AVocap The amount of filter capacitance required is directly proportional to the load transient step and the inductor size. In order to reduce the effective filter inductor size, a number of modules can be operated in parallel and is known as interleavingg." This improves the transient performance in a high current step system. It should also be noted that the capacitance requirement is the worst when the input voltage is minimum or the output voltage is maximum. Factors Affecting Transient Response Apart from choice of filter components of the synchronous buck converter, other factors can also affect the transient performance. The most important factor is the loop design. Loop Design The speed or the crossover frequency of the loop is one of the most important factors that affect the transient performance. Figure 415 shows the impact of this crossover frequency on the design in Table 32. When a 20 A transient is introduced, a 100 kHz crossover loop responds to it almost instantaneously and gets back the output voltage into regulation within 10 [is. When a 20 kHz crossover loop responds to the same transient, it has a much slower response leading to a higher voltage deviation from nominal, and it takes around 150 [s to get back to regulation. Unlike voltage mode control, which has a two pole response, the SRM poses a single pole response. Therefore, the feedback loop design is much easier and can be achieved with a simple compensation scheme. In order to achieve a fast dynamic response, the crossover frequency for the loop is set around onefifth of the switching frequency. For example, if the switching frequency is set at 250 kHz, the crossover frequency of the feedback loop is designed to be about 50 kHz. Trace Impedance The trace impedance, which leads from the output of the converter to the load, affects the transient behavior and steadystate behavior of the system. Two types of voltage sensing are implemented in a power system, as shown in Figure 416. The choice of the type of sensing is dependent on this trace impedance. In general, the distribution voltage drop in output power train leads and host board plane can be compensated by using a differential remote sense technique. If local sensing is implemented with large trace impedance, the output will have a permanent DC error with respect to the constant reference voltage. Therefore, even when the POL is located near the load, voltage sensing is always done remotely. As shown in Figure 417, the transient response to a 20 A step is affected by this trace impedance, owing to the distribution drop. The converter was operated at a 400 kHz switching frequency. The parameters for the converter and the modulator are given in Table 32. Optimizing Dynamic Response for the SRM In the previous section, it is identified that the load release is the worst case transient for POL application due to slow discharge of inductor energy after the transient. For modem POLs, in order to improve efficiency, the output voltage is reduced by introducing some droop in the output. This creates a minimum and maximum voltage bound for the output voltage known as load line characteristics. In order to fully utilize this window of tolerance, the output voltage is strategically placed near the maximum limit at no load and minimum limit at full load. This technique is known as automatic voltage positioning (AVP), as shown in Figure 418. The window helps to reduce the capacitor size required to meet the transient requirement. This section describes the design optimization of the modulator, in order to take full advantage of the AVP window and quickly get the converter back to regulation [56]. Figure 419 shows a close look at the buck converter response after a stepdown transient strikes. The current differential between the inductor and the load charges the output filter capacitor and causes a rise in the output voltage. During this time period tf the modulator forces the bottom FET to be on. The optimum time for the converter to start switching again is just before the output voltage reaches the upper limit of the AVP, such that the current in the inductor will come back to zero as the output voltage reaches the AVP limit at t3. The current charging the capacitor is the differential between the load current and the inductor current and is given by: ic(t) = t (4.38) tl Due to this charge current there is a voltage deviation at the output, which is given by: Vo(t)= Io* t +esrC Io 4.t (4.39) o0 t1 2 1 I The time period after with the output voltage resonates to maximum value can be found out as follows dv0(t) : t = (t Co esrCo) (4.40) dt In the above equation, time t, is a known quantity because the slope of inductor current and maximum current step is known. The equation also shows that, if the ESR is not neglected, the output voltage reaches the peak value prior to the inductor current reaching zero. The size of output capacitor can be calculated using (4.37) in order to meet certain maximum voltage specification AVomax. The instant at which the UFET can be turned on depends on two factors. The first one is the slew rate of the modulation signal Vmod and it is given by (3.12). The second one is the response of the compensator to the output voltage overshoot. As the output voltage rises it injects a current given by (VoVref)/Ri into the feedback node Vfb. This current creates the drop in the command signal Vcmd. This drop can be approximated as the drop across the resistor R2, as C2 has very high impedance and C1 has very low impedance at that frequency range. The simulation response of the compensator to a high slew rate load step is shown in Figure 420. The results show the comparison between the current through C3 and C2. It also shows the drop across R2 and C2, which confirm the above approximation. The change in Vcmd can be approximated as AVd =v(2) R (4.41) As shown in Figure 418, the net change is Vcmd and Vmod signal is given by: AVmod = AV + V (4.42) This behavior can be used to design the compensator and the modulator, such that the UFET of the buck converter can be turned on right before the output voltage crosses the maximum AVP limit. In summary, analysis that is critical to dynamic behavior of the SRM is described in this chapter. The small signal behavior is derived and validated. The design of the feedback loop, in order to obtain a fast and stable system, is described. Factors affecting the dynamic performance are quantified. The chapter concludes with a design philosophy for the modulator and the compensator, which ensures a fast dynamic response. Figure 41. Small signal modeling of the SRM. 1000 10000 100000 Frequency 100 0 E 0 10  a 020 30  t  90  100 100000 Frequency Figure 42. Controltooutput transfer functions of the SRM with design parameters in Table 32. 1000 10000 100000 LI4~~~4444~ I iiir~ Frequency 1000 10000 100000 Frequency VoNcmd_0.25_Exp VoNcmd_0.33_Exp VoNcmd_0.40_Exp VoNcmd_0.50_Exp Figure 43. Controltooutput transfer functions with load variation. 0 5 10 15 20 25 0 45 90 1000 10000 Output Impedance 10 20 30 40 1000 Frequency 225 180 135 10000 Frequency  Exp Theory Figure 44. Open loop output impedance of the SRM with parameters in Table 31. 100000 1000 100000 10000 a 12Z( 24 Z( I 36 60 L 100 1 ,10 1104 1 10 Figure 45. Open loop output impedance variation with filter capacitor. I r Compenisdaliii Open Loop Zo Closed Loop i ..=o 0 F iHzi Mag (dB.Q) Phiase (De(j) 0 50 a esrC., 150 200 250 120 '. ___ 100 1 .103 1 0 1 105 110 Figure 46. Closed loop output impedance can pose resistive output impedance. (Type 2 compensator: Ri=630, C2=600n, R2=10 K, C3=200 pF )  100 150 200 250 a3  300 1 106 Figure 47. Impact of change in Vin on the output voltage for the SRM. S50.o mV _____ 0 25.00 % Figure 48. Effect of low and high frequency input noise on the output voltage Vo. % % %%% .................. %' Compensator"'%. Loop Gain'%% ........................... o Controlt ControltoOutptut.... ',\ Frequency Figure 49. Basic philosophy of the loop design for faster transient response. C3 R2v ' f b RI SG s) G (s <iv v m I = ref (a)d ref Figure 410. Type 2 compensator and its small signal model. 0dB 1000 10000 100000 M,(g MIiiiia _ .... Plnase Ma( (P 1;1I 1000000 Frequency Figure 411. Input impedance characteristics of the SRM. Buck Converter 175 185 ,/) 185 100 Alo .esrQC Figure 412: Large signal behavior of the SRM. Vin L 2 L iL L rL (b) Figure 413. Response of synchronous buck converter to load transient. hys I.. t3 t2 :AV.UX    V0  ATI*esrC. Figure 414. Synchronous buck converter response to load transient. Figure 414. Synchronous buck converter response to load transient. GBW IMeg 20 0 .. .. . 0.          (A) : t(s) I . (IV : thz' V. __)OO2 EMz 550u 56Mu 57Ou sSou 5sou Figure 415. Impact of crossover frequency on the load step response. AI ti 1.02 1.0. 0.9 . 0,94  0.92 0.9 :* ., T .^ ............... .......... .... i................ ................ ........ .. ................ ................ F...............      .           )                   V./L t4 .............................. t .......... 540u Local Voltage Sense Remote Voltage Sense L trace 'p,* 2 1 \\^\^\ 2A A A VA I Ltrace SI Io Figure 416. Output voltage sense options for a POL. ZUHl I 0 ZHH           .  . .  .. I j I I . I j        Bfl    0 1(11) Zeo Tace Im c .775U .750U SELD 2nH:, IOhm:Trawe Impedanc .726U 0.800ms 0.900ms 1.000ms 1.100ms 1.200ms a U(Uo) U(Uol) Time Figure 417. Impact of distribution impedance on load transient and voltage regulation. in 1 1 1 1 1 1.284ms 1 ..... .T ... .. Figure 418. Automatic voltage positioning of output voltage helps transient design. AV J *V' Without AVP AI,*esrC. (b) Figure 419. Optimizing large signal response of the SRM. o.91u I I T I I V61 tdge bcrdsst ...... o U(Ucomp2) U(Ucmd) o U(Ufb) U(Ucmd) 100u  o I(R1) o I(C2) v I(C3) ^'   ' , o U(UtL) U(Uth) v U(Umod) 1.85U i i i 1.80V __. ..,., ,, ,,. 1.75U 1.89ms 1.9 0s 1.91ms 1.92ms Time Figure 420. Compensator design for optimum SRM dynamic response. 1.88ms a U(UO) 1.93ms  I i i i I : V(D 11 Ldg Hrosls C4 I _l ar CHAPTER 5 EXPERIMENTAL VERIFICATION This chapter presents two different design methodologies. The first design example is based on the design methodology presented in Chapter 3. The modulator is designed to meet critical parametric requirements. Based on the modulator, the feedback loop is designed to provide a stable and fast acting system. The second design example verifies the optimal transient theory developed in Chapter 4. The converter, modulator, and compensator are designed to meet a specific transient requirement with an optimal transient response. The optimal transient response helps the converter back into regulation in a minimum amount of time. The experimental verification shows a good corelation between the theory and the experiment for both design examples. SRM Design Based on Conventional Design Methodology This section describes the SRM design based on the conventional design methodology without any attempt of optimizing the dynamic response. The SRM design is based on the design methodology in Chapter 3. The compensator is designed to meet the stability criteria of the feedback loop and to provide a fast response to the load transient. Converter Design The synchronous buck converter is designed to have an output of 1.8 V with a 15 A rating. The nominal input voltage is 10.5 V. As the module is designed to have a single phase, the inductor size is specified as 0.82 .H in order to reduce the peaktopeak ripple current through it. The peaktopeak current ripple results in degradation of converter efficiency due to excessive switching loss in the top FET. Based on these initial specifications, the filter capacitor, the modulator, and the feedback loop are designed. There are three important design and layout considerations for a synchronous buck converter design. One of the most important considerations in designing a synchronous buck converter is to avoid a miller capacitorinduced dv/dt turnon of the LFET [57]. Figure 51 shows the mechanism of this fault turnon. The sharp rise in the Vphase, during the UFET turnon, is associated with an injection of charge into the gate of the LFET. Ideally, the gatedriver creates a low impedance node. However, during this high slew rate transient the interconnect inductance between the gatedrive output and the lower gate terminal results in high gate impedance. This results in an increase in the lower gate voltage VgL. If not designed properly, this voltage spike can result in the LFET turning on and causing a shootthrough between Vin and the ground. This fault turnon can be avoided by a proper choice of the LFET device as follows: (C,,)LFET (Cgd LFET (5.1) Therefore, IRF6678 is used as the LFET in this design which has Cgs=43 nC and Cgd=15 nC. This FET also has a very low onresistance of 2.3 mQ, which improves the overall efficiency. The next most important consideration pertains to proper layout of the board, as shown in Figure 52. For example, if there is a presence of parasitic inductance between the gatedriver ground and source of the LFET, it results in a negative ringing on the phase node. The ringing is a result of trapped energy circulation in the loop formed by the gate charge capacitor, internal gatedrive device, parasitic inductor, and lower FET diode. The negative ringing can result in voltage across the bootstrap capacitor Cb to exceed above Vc and leads to the failure of the gate driver [58]. Another important layout consideration is to have the input decoupling capacitor very close to the drain of the UFET and the source of the LFET in order to reduce the parasitic inductance. The parasitic inductance can result in heavy phase node ringing during the top FET turnon as shown in Figure 53. This ringing results in an increased switching loss and potential high frequency noise interference with other sensitive devices on the motherboard. The bias supply consists of a linear regulator comprised of an NPN device and a 6 V zener diode. This scheme gives a flexible onboard circuit to generate a bias voltage using the input supply. The major load on this supply is the gatedriver current, which is typically about 30 mA with a 250 kHz switching frequency for IRF6678. The complete power converter, gatedriver, and its bias supply design are shown in Figure 54. The power converter is realized using power FETs IRF6678 for both the top and bottom switch. The ISL6605 gatedriver accepts the square wave output signal of the PWM circuit as input and generates the gatedrive signal for the top and bottom switch. The input gate capacitance is specified as 5 nF and is driven by the gate driver with minimum delay. The rated overall transition delay for the gatedriver is specified within 30 ns for a 5 nF load. The power filter is realized using a powder core inductor. Powder cores have the advantage of significantly less temperature derating at the expense of higher core loss compared to ferrite cores. This inductor has a DC resistance of 1.8 mQ. Modulator Design Based on the converter specification, the modulator can be designed as delineated in Chapter 3 [59]. The design steps are outlined in Table 51 and are summarized below. The hysteresis voltage Vhys is selected first. For this example, the hysteresis voltage is chosen much larger than the steadystate output voltage ripple on Vo. Therefore, a 0.3 V hysteresis voltage is chosen. The ripple regulator is designed such that the output current of the transconductance amplifier is much larger than the input bias current of the Opamp. For this example, the trasconductance is specified as 55 [iS. Therefore, the output current of the transconductance amplifier has a minimum of 100 iA, which is much larger than the sum of all the bias currents. Note, the Opamp chosen for the design has a CMOS input stage and therefore has a very small input bias current in the Picoampere range. The droop resistance Rdroop is chosen as 14 mQ. The droop resistance is used to calculate the Remod using (3.6). The switching frequency is specified as 250 kHz. The discrete semiconductors used for the design are tabulated in Table 52. The total delay ti is approximated from the datasheet to be 100 ns. Using (3.4) and (3.13), Cmod can be calculated as 820 pF. The command voltage will automatically be set by the voltage error amplifier when the feedback loop is closed. Figure 55 shows the experimental implementation of the transconductor. The Opamp AD8066 is a dual amplifier with similar characteristics as AD8057. The value of Rm for the transconductor is calculated using (2.2). The input voltage to the ripple regulator is scaled down using an input resistive divider. The reduced input voltage helps the circuit to be within the input and output range of the Opamp. Figure 56 shows the implementation of the hysteresis voltage generator and it provides a low impedance supply for the hysteresis level generators. Figure 57 shows the implementation of the hysteresis level generator, which is fundamentally a combination of an analog adder and a subtractor. The adder is used to generate the upper level hysteresis Vmod+ and the subtractor is used to generate the lower level hysteresis Vmod. The hysteresis comparators are realized using the dual LT7120 comparator. The output of these comparators is fed into an NANDFF, which generates the PWM signal for the gatedriver. Table 52 summarizes all the components and its key parameters of specific importance to this design. Dynamic Design Most modern POLs are required to satisfy specific dynamic requirements under all load conditions. The worst case to maintain dynamic regulation is during a high slew rate stepdown transient, as identified in Chapter 4. This example explores the design of the filter capacitor and the SRM under this load transient condition. Filter Capacitor Requirement for Transients The design meets the following example transient requirements [60]: Load line=1.25 mQ + 19 mV (additional 50 mV during load release) The noload voltage of this design is 1.8 V. With a 15 A load step the required maximum voltage deviation is quantified from the above specification as AV ax = (15 xl1.25mQ)+ 38mV = 56.75mV (5.2) Thus, the maximum output voltage deviation during load stepup and stepdown equals 56.7 mV. Due to distribution impedance and component tolerances, a conservative target for this voltage deviation is about 45 mV. Based on this result, the number of output capacitors can be found. Assuming a 2 mQ ESR for the output capacitor, the net voltage deviation allowed by the capacitor is given by (4.36) as follows: AV = 45mV (15A 2mQ) = 15mV (5.3) Using (4.37), the output filter capacitor required is found out to be C =1 (15)2. 0.82k(1+0.2)=862uF 2 (10.51.8).15mV The inductor used has a tolerance of 20% and is reflected in the previous filter capacitor calculation. Therefore, three specialty polymer capacitors with a 330 iF specification are used for the design. Nominal input voltage of 10.5 V and output voltage of 1.8 V is assumed to the design. Feedback Loop Design The controltooutput transfer function for this design is calculated using (4.8). The experimental and theoretical comparison for this transfer function is shown in Figure 58. Results show a 4 kHz dominant pole for this design, which means the second pole is effectively canceled by the resultant zero from the modulator. The ESR zero is around 80 kHz and has little impact at low frequency. The transfer function gives a starting point for the design of the stable feedback loop and optimizing it for faster transient. The designed type 2 compensator is shown in Figure 59. The compensator is designed to have a zero at about 4 kHz and a pole at very high frequency. The theoretical verification and experimental verification of the loop gain are shown in Figure 510. The theoretical loop gain is predicted using (4.23). The crossover frequency is onefifth the switching frequency of 250 kHz. The phase margin of the design is shown to be 550 and the gain margin to be 18 dB. SRM Condition Check This check is performed to make sure that the condition specified in (4.30) is satisfied. For this design, the gain of the compensator at switching frequency can be calculated using (4.19) and is estimated to be 4.8. The value of Rmod for the design is calculated using (4.29) and Table 51 to be 55 mQ. The ESR of the filter capacitor is specified as 2 mQ. Using these parameters in (4.28) Rmod 55mn Gf (fW) < esrCm : 4.8 < 5mQ 27.5) (5.4) esrC0 2mQ ) The equation suggests that the peaktopeak ripple at the command signal is nearly four times smaller than the peaktopeak ripple at the output of the ripple regulator. This ensures a proper PWM switching instant determination by the hysteretic comparator. The simulated ripple is shown in Figure 511. The result shows a ripple of 300 mV at the output of the ripple regulator compared to a 65 mV ripple at the output of the voltage error amplifier. Simulation A simulation platform is developed using PSpice in order to predict the performance of the SRM as shown in Figure 512. The buck switches are realized using ideal switches. In order to simulate the turnon delays an input capacitance of 3 nF is included to simulate the gate capacitance. The onresistance is simulated with the help of a series resistor. All the Opamps, except the voltage EA, are simulated as an ideal voltage controlled voltage source. The voltage EA is modeled with a slew rate and bandwidth limit. A shootthrough protection circuit is included in the gatedriver to delay the gate signals and ensure that they are not high at the same time. A comprehensive filter capacitor model provided by the manufacturer is used to simulate the output filter capacitor. The stepup and stepdown transient responses are shown in Figure 513 and Figure 514. The load transient applied was a 15 A step with a rate of transition of 10 A/us. The simulation shows a voltage deviation of 55 mV for stepdown and 40 mV during the stepup transient. Also plotted is the current output of the ripple regulator. The current is pulsed at switching frequency due to its pulse input voltage. The peak output current is about 350 tA and the valley current equals 80 iA. Prototype Design and Test Setup The designed prototype is shown in Figure 515. The prototype was laidout using PCAD. In order to test this VRM, a test fixture was developed to simulate the host board of the POL. In order to simulate the extreme environment of the host board in a real application, only a 20 itF ceramic capacitor was used, which represents the bare minimum decoupling capacitor necessary for remote sensing. The test setup of the VRM and the test fixture is shown in Figure 516. An electronic load with a 15 A/Js current transition capability is used to simulate the actual load on the host board. Experiment Figure 517 shows the steadystate operation of the design. The switching frequency matches the designed value of 250 kHz. The output voltage ripple is close to the approximated value of 20 mV. There seems to be some injected noise because of the measurement setup. In order to verify experimental data with the theoretical prediction, the peaktopeak ripple at the Vmod node is predicted to be about 0.4 V and matches very well the experimental results in Figure 517. The positive slope of Vmod is predicted by (3.11) to be 0.5 V/its, which is close to the experimental results. Similarly, the negative slope is given by 0.12 V/its and matches closely with the predicted value. The response of the circuit to a 15 A transient with a rate of transition of 15 A/us is shown in Figure 518 and Figure 519. The stepup transient is about 65 mV and the stepdown transient is around 37 mV. As predicted in the Chapter 4, the stepdown transient is the worst edge as far as regulation is concerned. In practice, extra head room is provided in the specification for this transient. For example, VR 10.0 allows an extra 50 mV for 25 [is for this transient edge. During load release, the slope at which Vmod responds is predicted by (3.12), and the experimental results confirm this prediction. Figure 520 shows the response of the lower FET gate to the stepdown transition. The lower gate voltage turns on to respond to this load release almost immediately, ignoring some delay in the control circuit. Similarly, the response to load step up is also very fast, as shown in Figure 521. It can be observed that the control responds by not only increasing the duty cycle but also by the increase in switching frequency. The overall drop in output voltage during this transient is below 40 mV. In order to make the fast transient response more evident, the response of the hysteretic threshold limits are plotted with the Vmod for both the load transient edges in Figure 522 and Figure 523. SRM Design with Optimizing Transient Response This design example presents an SRM design methodology for an optimized transient response. The basic philosophy is to meet the specified dynamic voltage regulation requirements and get the voltage back to regulation in a minimum number of switching cycles. The specifications for this design are described as follows: Specification: 1. Vin=10.5 V,Vo=1.8 V,and o=15 A 2. Load line: 2 mQ 10 mV (Vtoi=20 mV, VtolR=30 mV during load release) 3. Alomax=15 A Power Stage Design: Chapter 4 identifies the load release as the worst case in terms of dynamics. The LC can be designed so the output resonates between Vomin to Vomax as inductor current goes to zero. The inductor is chosen as 0.82 .H in order to reduce the inductor ripple and switching loss. For this example the specified maximum voltage deviation is given by: AVomaxreq = 2mQ x 15 + 20mV = 50mV Similar to the previous example, due to distribution impedance and component tolerance, maximum allowed deviation in the output voltage is approximated as 45 mV. Using (4.36), the maximum voltage drop allowed across the filter capacitor is estimated as 15 mV. The required filter capacitor Co required to meet this transient specification is calculated using equation (4.37) and is equal to 850 .F. The 20% inductor tolerance is also taken into account for this calculation. The same capacitor combination is therefore used as in the previous design example, which is three 330 gF capacitors in parallel. UFET Turnon Instant: As described in the optimized design response in Chapter 4, after a load release transient, the UFET can be turned as the output voltage reaches the regulation limits. These regulation limits are defined by the load line. For this example, the regulation limits define a 30 mV droop in output voltage from full load to noload. The output voltage is therefore allowed to resonate to nearly 30 mV before the UFET is turned on. This condition defines the time instant at which the UFET is turned on. The output voltage characteristic is defined by (4.39). The output voltage characteristics can be used to compute the UFET turnon instant t2. Figure 524 shows the Mathcad simulation of the output voltage characteristic after the load transient hits. The output voltage resonates to a maximum value after 5 gs of the load transient. This conclusion is the same as predicted by (4.40). Without the intervention of the voltage EA, the output voltage reaches 30 mV after 10 gs of the transient strike. The modulator and the compensator should be designed so that the Vmod intersects the lower limit of the hysteretic signal VtL andl0 gs after the transient hits. Design of the Modulator: The hysteresis voltage is selected to avoid noise affecting the modulation signal. The noload value of the command signal Vcmd is equal to the output voltage. Because IR8057 is used as the error amplifier, the minimum output swing defines the lowest voltage to which Vcmd can swing. As the lower limit of the output swing is 0.9 V, a 0.4 V can be safely allowed for AVcmd. The calculation means the Vmod intersects the VtL at about 0.66 V below VtH, given by (4.42). Based on this information, (3.12) can be used to find the optimal value of gmMod/Cmod, and is given by 30 kS/F. Selecting Cmod=820 pF, gmMod can be calculated as 30 [iS. This gives the switching frequency of the modulator equal to 210 kHz. Compensator Design The controltooutput transfer function is shown in Figure 525. The loop resistor Ri is selected based on the current capability of the input pins of the voltage error amplifier. As explained in Chapter 4, the drop in the command Vcmd after a high slew rate transient is approximated as the voltage drop across the feedback resistor R2. If Ri is chosen as 630 Q, R2 can be calculated using (4.41) as approximately 10 kQ. The loop response for this compensation is shown in Figure 526. The crossover frequency is 40 kHz with a phase margin of 55. Table 5.3 summarizes the design presented in this section. The response of the designed system to a 15 A load stepdown at a rate of 10 A/'s is shown in Figure 527 and Figure 528. Figure 528 shows the response of the system without optimal design. It can be seen that the modulator takes about 8 to 10 cycles to get back to regulation. Figure 527 clearly shows the fast response and minimum cycle taken by the modulator to get back to regulation. The step down load response shows a predicted voltage overshoot of about 60 mV, which is reached after 5 [is of the load transient. The theory predicts the output reaching at 30 mV after 10 is, and is confirmed by the experiment. Similarly, the Figure 529 shows the load step down response. The transient is within the specification and confirms the superior design. This example confirms the superior dynamic response of the SRM with the optimized dynamic behavior. The modulator takes minimum time to get back to regulation. Table 51. Design Procedure for Example 2 Parameter Design Method Value Vo Specified 1.8V Vh_ Vo Ripple< gnMod _nMoaVo>>Total Bias Current 55 [S RI__ Specified 14mQ ri L Specified 1.8 mQ, 0.82 [tH R.___ Using (3.6) 137 kQ fs Specified 250 kHz Vil Specified 10.5 V ti Datasheet and measurements 100 ns Cnrd From (3.4) and (3.13) 820pF Lo Specified 15 A Table 52. Part Specification for Design Examp le 2 Parts Attributes Manufacturer FETs IRF6678 (Rdson=1.7 mQ, Qg=43 nC, Qgd=15 nC) International Rectifier Opamps AD8066 (SR: 160 V/gs, BW: 155 MHz; Ibias=1 pA) Analog Devices Comparator LT1720 (Delay: 13 ns; Ibias: 6 [iA; Linear Tech.) Linear Tech. FlipFlop 74 ACTI11074 (Delay: 9 ns; Texas Instruments) Texas Instruments Gatedriver HIP 6605B (Delay: 10 ns; Transition time: 10 ns; Intersil Filter Cap 3 X 330 [tF/ 7 mQ SPCapacitor Panasonic Inductor IHLP5050EZ, (0.82 [H, 2 mQ, Vishay) VishayDale Load 120 A output, 15 A/us (Max. Slew) Croma Table 5.3. SRM Design Example for Optimal Transient Behavior Power Stage Design Parameter Equation Value Comments AVm xq Specified 50 mV Selected based on specifications V Specified 10.5 V L, rL Select 0.82 pH, 1.8 mQ Selected to minimize switching loss AVpp (4.36) 20 mV Co (4.37) 850 pF 3 X 330 gF is selected for the design Modulator Design tf v(tf)=30 mV, (4.39) 10 ps Vhs Select 0.26 V Selected based on noise AV,, Select 0.4V Selected based on lower limit of the AVom Select 0.4V voltage EA AVrn (4.42) 0.66V giMadCn" (3.12) 36.67k Cnrd Select 820 pF gn"od gMo/Cnld 30 iS fs (3.13) 210kHz Compensator Design Se 630 Selected based on input current sourcng R Select limit ofthe negative terminal of VEA R2 (4.41) 9 k C2, C3 (4.23) 6.8 nF, 470 pF UFET Phase Phase LFET V gL Figure 51. Miller injected turnon mechanism in a synchronous buck converter. I Vphase Gate Drive LFET ve spike "....... Figure 52. Carefully gatedrive layout reduces the negative spike on the Vphase. Vpliase 4. Figure 53. Tight decoupling of the buck converter is essential to reducing noise on the Vphase. Sensitivity: 5 V/div and 500 ns/div. 89 Figure 54. The power converter design with gatedriver supply. F r^'Rm 2K phase 1i C1D LU \tnod V2 AD8066O I\ \ '  M UT1 +WS 8'.1U 05 R17 10k S 2 IN1 VA UT2 R12 I J 3 R15 10k +IN1 IN2  C R 0 VS +IN2 R2 4. RI 20p 37k U6 R18 10k R14 iGm Circu o it at Figure 55. Transconductance amplifier implementation. 1^ TLC271 R2 Offset NIAS SELECT :16 17 ys k I 2 IN U9 VDD D I 0.1u R31 K 3 IN+ OUT 6   R8 C21 6 OStuff R32 T GND Offset N2  No Stuff No StStuff Vhys Generator Figure 56. Hysteresis voltage generator. r  PWVIM Generator 1 74ACT11074 0.1uT PREN 1 4 ...+ N LT1720 VC l 8 UCLK 1PREN I +INA VCC nod 2 INA OUTA 7 12 VW yi,,i o  12 1CLRN 1QN ML INB OUTB 63 VG 11 VCC GND 4 +INB GND  A D U7 a 10 2CLRN 20N . \tnod C15T 0 2D 20 8 2CLK 2PREN 7 ML L __ Figur 57. H ei vg vUT1o Ar +VS 8 I  ch 2 IN1 VOUT2 7A  R25 k 3 k R21 R26 R22 Sk VS +IN2 5 k I R24 kS 6k Vmd Figure 57. Hysteretic level generator, comparator, and PWM latch circuit. 10o 30 100 1000 10000 100000 Theory  Experimental 90 100 1000 10000 100000 Theory Experimental Figure 58. Controltooutput transfer function for the system in Table 5.1. "l d R4 9No Stuff C18 C19 8n 47 md R39 AD8057 1 C22 R35 0 NC NC No Stuff No Stuff ^  7 +VS IN 2 A/I 0.1u R33630 R30 NcNC US Vs 1 1K R9 ICompensator Figure 59. The compensator design for the SRM in Table 51. 60 40 20  0 20  40  1.00 1.00E+03 1.00E+04  Exp_Phase Theory_Phase Figure 510. Loop response of the design. 1.00E+03 1.00E+04  Experimental Theory 180  160  140  120  100  80  60  40 1.001 1.00E+05 1.00E+05 E+02 4 All, "Ma T zz:_ 4 +02 E If F [N .786U t t ___ 0 U(Uo) U(Umod) o U(Ucmd) Time Figure 511. The ripple voltage on Vo, Vmod, and Vcmd for the designed system. Synchronous Buck I.I Compensator Figure 512. Implementation of SRM driven synchronous buck using PSpice.  ... ... .. .  .. .. .. .. ..    .. .. .   .... .   .. ...    .. ..  .. ....... 5Bi!!!Ai; } ;  , ^ , ^ A ^ .    . ^  ^   ^  OA. 200uA uB    SEL>> 1 00uA o I(U8) 1 .850U 1.8200U D U(Uout) .... .................. 2SU 1.2909ms 1.3000ms 1.3100ms 1.3280ms 1.3300ms 1.3400ms 1.350s ms 1.3600ms D U(UtL) U(Uth) v U(Unod) Time Figure 513. Stepdown transient simulation of SRM. I ft J  J  ' '  I I I . I I I, I I I, I  I I 15A  _, _.  _ ___ _ ... ._ _._ _ _. _._ _ . . __ . . . . . _  _ _ _ . , _ .. .. _ _ 5f".  4........... ;;            . . ^ .  ^    ^ o 1(11) 400uk4 20Buft= ,,  ,Ij I  u  O I(US) 1.78lU    1.741U' E U(Uout) 2=. ..."' ., ..../ .. ....... i .... 2 5U ,. . . .. . 930.Ous 940.0us 874.8us 880.0us 890.0us 900.0us 910.0us 920.0us c U(UtL) U(Uth) v U(Unod) Time Figure 514. Stepup transient simulation of the SRM. Input Socke \ Figure 515. Prototype of the VRM with synchronous buck converter driven by the SRM. Figure 516. Prototype test fixture for the VRM. M.4,Ops A Ch3 J ,11111 l 1i 11". i 2 1.00 % Figure 517. Steadystate performance for design example 2. Ir S I .. ." .1 10.0ps A Ch2 X 5.20mV ;gun] soo m  (a 20.20 % Figure 518. Load release response of the SRM. Ch3 i ,. I I Tek PreVu l  500mV %P 10.0 V (.h4 30.univ UOJ:7 Toek Pre Vu S I 'I. I. 1 * i i 510.OnlV ** U.OUps A ' .J 5.20mV km 20.20 % Figure 519. Load stepup response of the SRM. Chl 1.00 V :' I 1 1 i.". M 10.0ps A I. X 12.4r Ch3 5.00 V 0 1S OInV ..E i 20.20 % Figure 520. Fast response of the lower FET with the SRM to load release. [ iI . .. . .. . .. . . . SI r bk i k Stop m . . L..... .... .... .... .... .... .... .... .... r ^ a n  i 1.00 V 40 1.' I11 I % I.I M 4.OOps A i / S.20mV Ch3 20.0 V C14 50.o0 v *, . 1i 20.20 % Figure 521. Fast response of the upper FET with the SRM to load stepup. Chl SOOmV % .11 *M 20.Ops A , Ch3 SOOmV ] TU.OitV i ... Mi 21.00 % Figure 522. Vmod response to load stepup. Tek Stop L LO Chl 500SmV r _ 11 rI. M 20.0ps A cI Ch3 SOOmV 3 30.nmV * Is 21.00 s, Figure 523. Vmod response to load release. 0.06 0.04 Vo(t) 0.02 0\ 0 2 .16 4.106 6 106 8 .106 1 105 1.2 105 1.4105 t Figure 524. Computation of output voltage characteristics to load release. 