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Title Page  
Dedication  
Acknowledgement  
Table of Contents  
List of Tables  
List of Figures  
List of symbols and acronyms  
Abstract  
Introduction  
Digital pulse width modulator  
Digital synthetic ripple modul...  
Design and experimental implementation...  
Testing and analysis of digital...  
Conclusion  
Appendix A: Matlab functions  
References  
Biographical sketch 



Table of Contents  
Title Page
Page 1 Page 2 Dedication Page 3 Acknowledgement Page 4 Table of Contents Page 5 Page 6 Page 7 List of Tables Page 8 List of Figures Page 9 Page 10 Page 11 Page 12 Page 13 List of symbols and acronyms Page 14 Page 15 Abstract Page 16 Page 17 Introduction Page 18 Page 19 Page 20 Page 21 Digital pulse width modulator Page 22 Page 23 Page 24 Page 25 Page 26 Page 27 Page 28 Page 29 Page 30 Page 31 Page 32 Page 33 Digital synthetic ripple modulator Page 34 Page 35 Page 36 Page 37 Page 38 Page 39 Page 40 Page 41 Page 42 Page 43 Page 44 Page 45 Page 46 Page 47 Page 48 Page 49 Page 50 Page 51 Page 52 Page 53 Page 54 Page 55 Page 56 Page 57 Page 58 Page 59 Page 60 Page 61 Page 62 Page 63 Page 64 Page 65 Page 66 Page 67 Page 68 Page 69 Page 70 Page 71 Page 72 Page 73 Page 74 Page 75 Page 76 Page 77 Page 78 Page 79 Page 80 Page 81 Page 82 Page 83 Page 84 Page 85 Page 86 Page 87 Page 88 Page 89 Page 90 Page 91 Page 92 Page 93 Page 94 Page 95 Page 96 Page 97 Page 98 Page 99 Page 100 Page 101 Page 102 Page 103 Page 104 Page 105 Design and experimental implementation of digital synthetic ripple modulator Page 106 Page 107 Page 108 Page 109 Page 110 Page 111 Page 112 Page 113 Page 114 Page 115 Page 116 Page 117 Page 118 Page 119 Page 120 Page 121 Page 122 Page 123 Page 124 Page 125 Page 126 Page 127 Page 128 Page 129 Page 130 Page 131 Testing and analysis of digital SRM controlled buck converter Page 132 Page 133 Page 134 Page 135 Page 136 Page 137 Page 138 Page 139 Page 140 Page 141 Page 142 Page 143 Page 144 Page 145 Page 146 Page 147 Page 148 Page 149 Page 150 Page 151 Page 152 Page 153 Page 154 Page 155 Page 156 Page 157 Conclusion Page 158 Page 159 Appendix A: Matlab functions Page 160 Page 161 Page 162 Page 163 References Page 164 Page 165 Page 166 Page 167 Page 168 Page 169 Biographical sketch Page 170 

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DIGITAL SYNTHETIC RIPPLE MODULATOR FOR A DCDC CONVERTER By BHARATH BALAJI KANNAN A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006 Copyright 2006 by Bharath Balaji Kannan To the Almighty God. ACKNOWLEDGMENTS I would like to sincerely express my gratitude and appreciation for my advisor, Dr. Khai D.T. Ngo, for his constant encouragement and thoughtprovoking ideas that helped me in the development of this dissertation. I would also like to thank the Department of Electrical and Computer Engineering at the University of Florida, for providing me the necessary financial support. I would like to thank Dr. John G. Harris and Dr. William R. Eisenstadt for their valuable suggestions and for being on my dissertation committee. I would also like to thank Dr. JihKwon Peir for serving as my external committee member. I would also like to take this opportunity to thank Dr. Robert M. Fox, who helped me to acquire the skills in the field of integrated circuit design. I am also grateful to Dr. Jacob Hammer for helping me to secure the departmental financial assistance towards my research. I would also like to express my gratitude and appreciation to the College of Engineering, Anna University, India, for providing an ambient environment to study and learn. Last but not least, I would like to thank my parents, sister, brotherinlaw, and my resourceful friends who gave me the necessary impetus towards the development of this dissertation. TABLE OF CONTENTS A C K N O W L E D G M E N T S ..............................................................................................................4 L IST O F T A B L E S ......................................................................................................... ........ .. 8 LIST OF FIGURES ............................................. ............ ...........................9 LIST OF SYM BOLS AND ACRONYM N S............................................................ ................ 14 A B S T R A C T .......................................................................................................... ..................... 16 CHAPTER 1 INTRODUCTION .................................. .. ........... ............................. 18 1.1 Conventional Carrier Signal G generation ............................................. ..... ................ 19 1.2 Carrier Signals in Digitally Controlled DCDC Converters.......................................21 2 DIGITAL PULSE W IDTH M ODULATOR ..................................................... ................ 22 2.1 DPWM Modules in Digitally Controlled DCDC Converter....................22 2.2 DPWM Modules in Digitally Controlled DCAC Inverter ..... ................24 3 DIGITAL SYNTHETIC RIPPLE MODULATOR...........................................................34 3.1 D esign C concept of D SR M ............................................. ........................... ................ 34 3.1.1 Digital Inverse Tim ing Generator ........................ .... ................ 35 3.1.2 Extraction of Digital Timing Generator Parameters ........................................37 3.1.3. Scaling Approaches .................................................................. 39 3.1.4 Successive A ccum ulation .................................................................... ............... 42 3.2 Architecture of Digital Synthetic Ripple Modulator ...................................................44 3.3 Application Illustration of the Digital Synthetic Ripple Modulator...............................47 3.3.1 Design of Buck ConverterOutput LC filter............... ..................................... 49 3.3.2 Design of Digital Synthetic Ripple M odulator.................................. ................ 50 3.3.2.1 D igital tim ing generator ....................... ............................................... 50 3.3.2.2 O utput voltage A /D resolution .............................................. .................. 53 3.4 Modeling and Simulation of Digital SRM Based Buck Converter ................55 3.4.1 M odeling of PW M Sw itch .......................................... ....................... ............... 55 3.4.2 M modeling of Output LC filter ......................................................... 56 3.4.3 M odeling of D igital SRM C ontroller ................................................... ............... 56 3.4.4 Simulation of Adaptive Voltage Position for Digital SRM based Buck C o n v e rte r ............... ....... ..... .................................................................................... 5 9 3.4.5 Modeling of Dynamics involved in the Digital SRM Controller for a Buck C o n v erter..................................................................................................... ........ .. 6 5 3.4.6 Design Methodology for Digital SRM Controlling the Synchronous Buck C o n v e rte r.......................................... ....... .... ................................................. ......... 6 9 3.5 Performance Analysis of Digital Synthetic Ripple Modulator .........................................72 3.5.1 Openloop Linear Control of Controlled Variable with Command Signal ............72 3.5.2 Influence of Component Variations on the Digital SRM Performance ............ 72 3.5.3 Openloop Dynamic Response of the Digital SRM Controlled Buck C o n v erter.......................... ....... .... ............................................................... ......... 7 3 3.6 Advantages of Digital Synthetic Ripple M odulator .................................... ................ 73 4 DESIGN AND EXPERIMENTAL IMPLEMENTATION OF DIGITAL SYNTHETIC R IPPL E M O D U L A T O R ................................................... ............................................. 106 4.1 Experimental Implementation of Synchronous Buck Converter.............................. 106 4.1.1 Power M OSFET Design and Selection....... .......... ...................................... 107 4.1.2 Output Filter Inductor Selection...... .......... ........ ..................... 108 4.1.3 Output Filter Capacitor Selection...... .... ...... ..................... 109 4.1.4 Synchronous Buck G ate driver................... ................................................. 109 4.2 Experimental Implementation of Signal Conditioning Circuit.................................... 109 4.3 Hardware Implementation of DCDC Buck Converter and A/D Signal Conditioning C ircu it................................................... .... ........................................................... ........ 1 14 4.4 Experimental Implementation of the Digital Timing Generator ..................................114 4.5 Experimental Implementation of Digital Synthetic Ripple Modulator Controlling the D C D C B uck C onverter.................................................. ............................................ 115 5 TESTING AND ANALYSIS OF DIGITAL SRM CONTROLLED BUCK CONVERTER ...................................... ............ ............................. 132 5.1 DCDC Buck Converter Testing and Measurement..............................................132 5.2 Signal Conditioning Circuit Testing and Measurement ............................................134 5.3 Digital Synthetic Ripple Modulator Controlled Buck Converter Testing and M easurem ent .............................................. ... ... ......................... 135 5.3.1 D igital Inverse Tim ing G enerator Testing ................................... ..................... 137 5.3.2 Command to Output Transfer Characteristic of Digital Synthetic Ripple M odulator Controlled Buck Converter............................................. ................... 138 5.3.3 Load transient response StepResponse of Digital Synthetic Ripple Modulator C controlled B uck C onverter.............................................. .................... ............... 138 5.3.4 Variation of Switching Frequency Based on Load Conditions......................... 139 5.4 Future D irectives for R research ................. .......................................................... 139 6 C O N CLU SIO N ........................... ... ................................... ...... 158 6 .1 Su m m ary ...................................................................................................... ......... 158 6 .2 F future W ork .................................................................................................. .......... 158 APPENDIX M A T L A B F U N C T IO N S ....................................................... ................................................ 160 L IST O F R E F E R E N C E S ....................................................... ................................................ 164 B IO G R A PH IC A L SK E T C H .................................................... ............................................. 170 LIST OF TABLES Table page 21 D PW M architecture realizations .................. ............................................................... 27 22. Hardware/FPGA realization of DPWM module in DCDC converters ..............................28 23. DSP/Microcontroller realization of DPWM module in DCDC converters ........................29 24. Hardware/FPGA realization of DCAC PWM inverter control ....................30 25. DSP/Microcontroller realization of DCAC PWM inverter control................ 31 31. Sequential steps involved in Step Value generation......................................... ................ 74 32. D C D C converter specifications........................................... ......................... ................ 74 33. Scaling factor A pproxim nations ...................................................................... ................ 74 41. Comparison of time duration from simulations....................................... 117 42 Bill of materials for the synchronous buck DCDC converter.................. ...................117 43 Bill of materials for the A/D converter and signal conditioning circuit .............................117 44 Bill of materials for the FPGA based digital controller...... ......................................... 118 51 Equipm ent list and specifications ...................................... ........................ ................ 140 LIST OF FIGURES Figure page 21. Generic architecture of digitally controlled DCDC switching converter..........................32 22. Duty ratio based on hybrid DPWM (NDPWM=8bits) ...................................................... 32 23. Architecture of PWM inverter based 30 induction motor drive...................33 31. Conceptual implementation of digital duty ratio generation...........................................75 32. Inductor current indicating the current ripple and time intervals along with the buck converter inductor voltage ..................... ................................................................. 75 33. Scaling approaches for step value generation................................................... ................ 76 34. Timing error performance for various scaling factor approximations used in step value g en eratio n ......................................................................................................... ....... .. 7 6 35. Simulation analysis indicating percentage timing error based on binary multiplication scaling and A /D gainblock scaling ..................................... ...................... ................ 77 36. Simulation analysis indicating percentage timing error based on binary multiplication scaling and A /D gainblock scaling ..................................... ...................... ................ 78 37. Generic architecture of a system controlled by digital synthetic ripple modulator ............79 38. Generic synthetic ripple modulation showing the hysteretic thresholds, command variable and P W M signal .. ............................................................................ ............... 79 39. Architecture of digital SRM controlled synchronous buck DCDC converter. ....................80 310. Inductor current waveform during load current stepup and steadydown transient........... 81 311. Simulation analysis of percentage error for various scaling factor approximations ........... 81 312. Transfer characteristic of the A/D converter sampling the error voltage between output and com m and voltage .......................................... .......................... ................ 82 313. Sim ulink m odel of the PW M sw itch ........................................ ...................... ............... 82 314. Sim ulink m odel of buck L C filter......................................... ....................... ................ 83 315. Simulink model of the A/D converter ......................................................... 83 316. Sim ulink m odel of digital tim ing generator ................................................... ................ 84 317. Block diagram depicting the Simulink model of digital SRM controlled buck co n v erter .......................................................................................................... ........ .. 8 5 318. Simulation outputs of the synchronous buck converter using MATLAB/Simulink for V cm d= l1.3V ..................................................................................................... ........ .. 86 319. Simulation outputs indicating the step value, integer value and VPWM signal of the digital timing generator...................... ............ ............................. 87 320. Comparison between ontime/offtime generated based on theoretical equations and sim ulated synthetic ripple m odulator ............................................................ ................ 88 321. Percentage error between digital timing generator and theoretical expression using sim u latio n an aly sis ............................................................................................................. 8 9 322. Voltage change across the output capacitor during a stepdown load transient...............90 323. Integer value, modified hysteretic count, VPWM, and Error binary for AVP im plem entation in digital SR M ........................................................................ ................ 9 1 324. Integer value, modified hysteretic count, VPWM, and Error binary for AVP im plem entation in digital SR M ........................................................................ ................ 92 325. Inductor current and AVP of the output voltage based on optimal AVP design for the load step u p tran sent .................................................. .............................................. 93 326. Inductor current and AVP of the output voltage based on optimal AVP design for load step d ow n tran sent ............................................................................................................ 94 327. Inductor current and AVP of the output voltage Vcmd reaches higher level before the peaking of V out (V out m ax) ........................................ ....................... ............... 95 328. Inductor current and AVP of the output voltage Vcmd reaches higher level before the peaking of V out (V out m ax) ........................................ ....................... ................ 96 329. Inductor current, VPWM, and AVP of the output voltage Vcmd reaches higher level after the peaking of V out (V out m ax).......................................................... ................ 97 330. Modulator output, Error binary, and AVP of the output voltage Vcmd reaches higher level after the peaking of V out .......................................................... ................ 98 331. Dynamic system model of the digital SRM controlled synchronous buck converter .........99 332. Magnitude and phase of command (vcmd) to duty ratio (d) transfer function................100 333. Magnitude and phase of duty ratio (d) to output voltage (vout) transfer function ..........101 334. Magnitude and phase of command (vcmd) to output voltage (vout) transfer function..... 102 335. Plot indicating the linear control of output voltage with command voltage based on M A TLAB /Sim ulink sim ulation..................................... ....................... ................ 103 336. Simulation plot indicating the effect of component variations on the performance of th e d ig ital S R M ............................................................................................................... 10 4 337. Simulation of openloop load transient response of digital SRM controlled buck converter with Vcmd=1.5 V and load step of 5A to 10A in 100 ns (50 A/as) ................105 41. Schematic of synchronous buck DCDC converter...... .... ..................................... 119 42. Current through the UFET in a switching cycle............... ........................ 119 43. Schematic of signal conditioning circuit for the A/D converter with inclusion of the sc a lin g fa cto r ................................................................................................................. ... 12 0 44. Block diagram of the experimental digital synthetic ripple modulator indicating the register enable and tim ing signals......................................................... ............... 121 45. Frequency response of the signal conditioning circuit amplifier ..................................122 46. Phase voltage, converter output voltage, and signal conditioning circuit scaled voltages fo r V cm 1 .5 V ............................................................................................................... ... 12 3 47. Inductor voltages at the input of the A/D converter for a duty cycle of D=0.325 and Vcm, l.5V ........................................................................ ...... 124 48. Buck converter output voltages, error voltage and output A/D input voltage for Vcm l .5V ........................................................................ ...... 125 49. Gerber file indicating the top layer of the PCB board...............................................126 410. Gerber file indicating the bottom layer of the PCB board...................... ...................127 411. Photograph of the manufactured PCB board indicating the buck converter and the signal conditioning circuit. .................................................................... ............... 128 412. Timing signals and A/D converter input voltages for the signal conditioning circuit ......129 413. ALTERA board based digital synthetic ripple modulator outputs indicating VPWM outputs for step values (100)o0 and (42)0o................................... 130 414. Experimental implementation of DSRM controlled buck converter system.......... 131 51. Experimental testbed setup used for characterizing the DCDC synchronous buck co n v erter ........................................................................................................ ........ .. 14 1 52. Phase node voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3.............141 53. Output voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3..............................142 54. PWM Input (CH2) and highside gate drive (CH1) for Vin=5V and D=0.3 .....................142 55. PWM input (CH2) and Vphase (CH1) for Vin=5V and D=0.3 ............... ................143 56. PWM input (CH2) and lowside gate drive (CH1) for Vin=5V and D=0.3 ......................143 57. Phase node voltage (CH1) and lowside gate drive (CH4) for Vin=5V and D=0.3..........144 58. Phase node voltage (CH1), output voltage (CH2) and inductor voltage (Math2) for Vin=5V and D=0.3 ........................ .. .......... ............................... 144 59. Vphase_posl (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25 ......145 510. Vout negl (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25........145 511. VLpos_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.25 ....................146 512. VLneg_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.25....................146 513. Verr_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.3 .........................147 514. VLpos_adc_input (CH3), registerenable blnk_pos (CH4) and VPWM from digital modulator (CH1) for Vin=5V and Vcmd=1.38 ....... ... ...................................... 147 515. VLneg_adc_input (CH3), registerenable blnk neg (CH4) and VPWM from digital modulator (CH 1) for Vin=5V and Vcmd=1.38 ....... .......... ..................................... 148 516. A/D converter output for inductor voltage during ontimeVLPOS [70] (CH3), register enableblnk_pos (CH4), and VPWM (CH1). A) VLPOSO (LSB). B) VLPOS1. C) VLPOS2. D) VLPOS3. E) VLPOS4. F) VLPOS5. G) VLPOS6. H) V L P O S 7 (M S B ) ............................................................................................................... 14 9 517. A/D converter output for inductor voltage during offtimeVLNEG [70] (CH3), register enableblnk neg (CH4), and VPWM (CH1). A) VLNEGO (LSB). B) VLNEG1. C) VLNEG2. D) VLNEG3. E) VLNEG4. sF) VLNEG5. G) VLNEG6. H) V L N E G 7 (M S B ) .............................................................................................................. 15 0 518. A/D output for error voltage between Vcmd and Vout VERRAD [70] (CH3), register enableblnk neg (CH4), and VPWM (CH1). A) VERRADO (LSB). B) VERRAD1. C) VERRAD2. D) VERRAD3. E) VERRAD4. F) VERRAD5. G) V ER R A D 6. H ) V ER R A D 7 (M SB ). ................................................................................151 519. Verr_adc_input (CH1) and VPWM from digital modulator (CH4) for Vin=5V and V c m d = 1 .3 8 ................................................................................................................... ... 1 5 2 520. Timing generation comparison based on simulation, theory and experimental digital tim ing generation approach....................................... .......................... ............... 152 521. Percentage timing error based on experimental digital timing generation approach ........ 153 522. Linear plot of Vout Vs Vcmd for Vin=4.5V and load resistance RL=1 ........................ 153 523. Linear plot of Vout Vs Vcmd for Vin=4.96V and load resistance RL=1Q ...................... 154 524. Linear plot of Vout Vs Vcmd for Vin=4.17V and load resistance RL=1 ...................... 154 525. Linear plot of Vout Vs Vcmd for Vin=5V and load resistance RL=0.67Q ....................155 526. Linear plot of Vout Vs Vcmd for Vin=4.17V and load resistance RL=0.67Q ...............155 527. Load transient response of the digital SRM Vout (CH2), inductor current (CH4) and load current step (CH3)................................ ............................. 156 528. Variation of switching frequency with respect to load current for Vin=3.75V, 4.00V an d 4 .3 5V ...................................................................................................... ......... 157 LIST OF SYMBOLS AND ACRONYMNS A/D Analog to Digital D Steadystate duty ratio of the converter DLL Delaylocked loop DPWM Digital Pulse Width Modulator DSRM Digital synthetic ripple modulator FPGA Fieldprogrammable gate array Nc Number of bits for the hysteretic count resolution NL Number of bits for the sampled inductor voltage NQ(,I) Sampled converter/inverter parameter Nsc Scaling factor used in inverse timing generation Nsc AD Ratio of scaling factor used in the signal conditioning circuit PCB Printed circuit board PFC Power factor correction q(V,I) Control input for the inverse timing generator qsTEP Step value used in the accumulator tCLK Time period of the clock used for successive accumulation tOFF Offtime of the upper MOSFET switch toN Ontime of the upper MOSFET switch Ts Switching time period VCDL Voltagecontrolled delay line Verrq LSB equivalent of the quantized error voltage between output and command voltage VLbin Binary equivalent of the quantized inductor voltage VLq LSB equivalent of the quantized inductor voltage VRM Voltage regulator module VOUT Output voltage of the buck converter Error Percentage timing error metric for the timing generator AIL Peakpeak inductor current ripple Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DIGITAL SYNTHETIC RIPPLE MODULATOR FOR A DCDC CONVERTER By Bharath Balaji Kannan December 2006 Chair: Khai D.T. Ngo Cochair: John G. Harris Major Department: Electrical and Computer Engineering Voltage regulator modules (VRMs) powering the future microprocessors are required to meet the stringent specifications on the core voltage ripple and voltage regulation. These specifications are driven by the microprocessor's higher di/dt requirements and the need to operate at a lower supply voltage for reduced power consumption. The conventional VRMs resort to multiphase pulse width modulation (PWM) control schemes to cater to the high current demands and provide balanced load current sharing. The control schemes also involve a combination of voltagemode and currentmode or currentmode and hystereticmode control. Thus, these schemes add to the cost and complexity of the VRM. Synthetic ripple modulation (SRM) involves the generation of an artificial ripple, synthesized from a converter parameter which is then bonded to the output voltage of the VRM. This artificial scheme of carrier signal generation for PWM control enables voltagehysteretic modulation to be achieved in the lowvoltage VRM modules for microprocessors. With the inherent lowvoltage ripple exhibited by a lowvoltage VRM that is insufficient for conventional hysteretic operation, the SRM scheme on the other hand provides sufficient ripple for the PWM carrier signal. The SRM scheme blends in the advantages of currentmode control and hysteretic control providing superior transient performance. The introduction of digital control to the PWM control of switching power converters has gained popularity owing to its benefits of lower sensitivity to process and mismatch variations, programmability, and the reduction of passive components used in tuning. The digital control based SRM generates the duty ratio with inverse relation to a sampled converter parameter. The ontime and offtime duration of the switches forming the duty ratio is generated by successively accumulating the sampled inductor voltage. The accumulated output forming the synthetic ripple is added to the error between output voltage and reference voltage. The carrier signal thus generated is modulated between the higher and lower hysteretic thresholds, thus generating the duty ratio. A unique scaling process also allows the implementation of programmable switching frequency for converters. The major contributions of the dissertation in the field of engineering are given below. * Digital synthetic ripple modulator architecture for applications in power electronics. * Digital inverse timing generator with wide dynamic range and programmable frequency. The digital SRM scheme is verified experimentally in the control of a synchronous buck DCDC converter. Experimental data are provided to delineate the potential advantages such as inverse timing generation, programmable switching frequency, linear control of output variable with reference variable under openloop conditions, natural feedforward control, and superior transient performance. CHAPTER 1 INTRODUCTION Lowvoltage power supplies powering future microprocessors are under constant pressure to provide higher di/dt requirement. The corevoltages of current and future microprocessors are on the order of 0.81.0V, enabling lower power consumption. The trend towards lowvoltage operation increases the burden on the switching regulators which are required to maintain a tight tolerance on the core voltage. The allowed tolerance on the core voltage remains at a fixed percentage of the supply voltage instead of an absolute value in volts. This indicates that as the core voltages go down, the tolerance that the processors can handle also scales down proportionately. It is also predicted that the load current requirements of these microprocessor cores will increase up to 200A with dynamic current slewrates on the order of 120A/ns [12]. These dynamic loads are tackled with pointofload power supplies which derive their output voltage from power conversion of existing 12V supply systems. The dynamic loads also present stricter transient regulation requirements, thereby creating the need for the design of efficient and enhanced power supply operation and control. The dissertation focuses on the generation of carrier signals utilized in pulse width modulation (PWM) control of converters/inverters with hysteretic mode of operation. The carrier signals are derived from converter/inverter parameters such as inductor voltage, drainsource voltage of power MOSFET, inductor current, and stator winding current. The carrier signal is composed of the ripple associated with the variable to be controlled and a synthetic ripple derived by filtering (analog approach integration or digital approach accumulation) a converter parameter. Since the PWM control involves artificial carrier signal generation, the term synthetic ripple modulation promptly applies. The superimposing of the controlled variable with that of the synthetic ripple creates a significant amount of ripple similar to that exhibited in conventional current mode control. The modulation strategy is theoretically validated with an application involving the control of a DCDC synchronous buck converter used as a switching regulator for powering microprocessors. The tight tolerance required on the output voltage of the switching regulator and the higher di/dt (120A/ns) requirement can be achieved with the synthetic ripple modulation (SRM) technique. Since the SRM based control is a form of hysteretic control modulating the controlled variable directly within a hysteretic band, superior dynamic performance is inherently attained. The fact that the output voltage is bonded to a synthetic ripple, resulting in a carrier signal with sufficient ripple for PWM operation, allows the output voltage to be controlled directly and with the required tight tolerance. The digital SRM (DSRM) scheme employed in the control of the buck converter also involves a novel method for deriving the duty ratio, with the generated timeintervals inversely related to a sampled converter parameter. The duty ratio generation scheme is based on a unique scaling process and eliminates the need for a high clock frequency. The modulation scheme utilizes the sampled inductor voltage, which is scaled and successively accumulated to generate the synthetic ripple. The error in the output voltage when compared to a reference or command voltage is added to the synthetic ripple resulting in the carrier signal for PWM operation. The carrier signal is modulated between hysteretic limits, resulting in the required duty ratio. Since the carrier signal involved in the PWM signal generation is derived from the converter parameters in the SRM scheme, natural input feedforward control is also attained. This enables better rejection of line input disturbances. 1.1 Conventional Carrier Signal Generation Conventional PWM control relies on three main control schemes, namely, voltagemode control, currentmode control and hysteretic control [3]. In voltagemode control, the carrier signal required for PWM signal generation is based on an external oscillator. The oscillator providing the carrier signal is conventionally realized by charging or discharging a capacitor using a constant current source. It suffers from the serious drawback of external component variations and requires better matching between an onchip current source and an external capacitor. The transient performance of voltagemode control is limited by the delays involved in the compensation circuit forming the feedback loop. The currentmode control counterpart utilizes the inductor current ripple for the carrier signal. The commutation instants of the MOSFET switches are based on the type of currentmode control, namely peak currentmode control, average currentmode control, and valley currentmode control. Currentmode control offers better transient performance when compared to voltagemode control. This tradeoff is made possible only with accurate current sensing employing a current sense resistor or a current transformer. The advantage thus gained over the voltagemode control is offset by the additional loss in the resistor for higher load currents or by the cost and space requirements of the current sense transformer. In hysteretic control, the carrier signal is implicitly generated by regulating the desired output variable within a hysteretic band centered about a reference. The hysteretic mode of control provides fast load transient response, requires no feedback loop compensation, and no input filter interaction problems when compared to voltagemode or currentmode control. In applications requiring the controlled parameter to be within a marginal hysteresis band, the PWM comparator used in power switch commutation is required to exhibit high resolution and fast response. One of the major drawbacks involved in the hysteretic mode of control is the variation of the switching frequency, increasing the complexity involved in output filter design. The artificial ripple superimposed onto the controlled variable in the discussed synthetic ripple modulator is significant enough to eliminate the need for a high resolution PWM comparator. The synthetic ripple modulator also blends in the advantages of hysteretic modulation by virtue of the control variable being directly tracked by the PWM comparator. 1.2 Carrier Signals in Digitally Controlled DCDC Converters The conventional voltage/currentmode control based on analog approaches involves more realestate to accommodate for the external components like resistors, capacitors, current transformer, currentsense resistor, etc. The introduction of digital control for DCDC converters/inverters offers a multitude of benefits like insensitivity to component and parameter variations, better noise immunity, ease of programmability, reduced size and cost. An application involving the digital control of microprocessor power supplies also offers the benefits of easier VID code (Voltage Identification Code) integration, fault protection, programmed softstart, the inevitable features of modernday voltageregulator modules (VRM) [2]. Carrier signals for digital control of DCDC systems are generated using a specific module, namely the Digital Pulse Width Modulator (DPWM). The DPWMs are based on current starved inverters, fastclocked counter, tapped delaylines, hybrid approach involving multiplexer and delaylines, and binaryweighted delay lines. The architectural realization and implementation issues associated with the DPWM architectures are dealt with in chapter 2. The list of symbols and acronyms used in the dissertation are outlined in Table 11. CHAPTER 2 DIGITAL PULSE WIDTH MODULATOR The digital pulse width modulator (DPWM) block in a digitally controlled power converter/inverter generates the PWM pulse signal controlling the commutation instants of the switches. A typical application involving a DCDC converter relies on the control and regulation of output voltage or the line/input current of the converter. Similarly a DCAC inverter application involves the control/regulation of stator current or inverter output voltage for the speed control of motordrives. 2.1 DPWM Modules in Digitally Controlled DCDC Converter The DPWM module in a DC/DC converter generates a discrete set of duty ratio values based on a digital command input word from a discretetime compensator. The carrier signal involved in the PWM pulse signal generation is implicitly created by the DPWM module. The DPWM module quantizes the switching time period into a number of discrete time slots. A particular time slot is selected based on the digital duty command input (d[n]) [45]. The selection of a particular time slot and the time duration elapsed during the slot selection determines the commutation instant of the switch and the duty ratio respectively. The carrier signal information is embedded in the architecture forming the DPWM module. The generic architecture of a digitally controlled switching DCDC converter is outlined in Figure 21. The discrete set of duty ratio values involved in a digitally controlled DC/DC converter imposes restrictions on the set of steadystate values taken by the output voltage. The resolution of the DPWM module should be higher than that of the output voltage A/D resolution to avoid limit cycle oscillations [6]. The DPWM module serves as a D/A converter interfacing the digital control block with that of the switching converter. Several realizations of the DPWM module based on linearity, highfrequency capability, area, complexity and power consumption are outlined in literature [7 11]. A summary of the DPWM realizations are shown in Table 21. Due to the profound developments in Fieldprogrammable gatearray (FPGA) and the DSP processors sector of the semiconductor industry, the realization of such DPWM modules is becoming much easier. A comparative listing of the current approaches for the realization of DPWM modules in DCDC converters based on FPGA/IClevel and DSP implementation is indicated in Table 22 and Table 23 respectively. The approaches are also distinguished based on voltagemode, currentmode and hysteretic control of DCDC converters. The set of duty ratio generated from a hybrid DPWM [8] involving multiplexers and counters is shown in Figure 22. Based on the characteristic in Figure 22, a linear relation between the digital command word and the output duty ratio is sought in the digital control schemes which are based on Figure 21. The realizations based on IClevel/FPGA implementation are tailored to a particular application resulting in restricted programmability of the switching frequency. The linearity between the dutyratio command input and the PWM pulse signal exhibited by siliconbased DPWM modules relies on careful layout techniques and better matching between the delay cells [7]. The DPWMs based on tapped delaylines are susceptible to drifts in the switching frequency, due to process and temperature variations in individual delay cells. The power supply ripple rejection performance necessitates differential delay cell designs [11]. The DPWMs realized from the counter/comparator scheme suffers from the serious drawback of higher power consumption. The need for higher resolution in lowvoltage VRMs, leads to higher clock frequency requirement in the range of 200800MHz attributing to higher power consumption [12]. DCDC converters employed in lowvoltage VRM's are tied with stricter static and transient specifications with regulation tolerance less than 5%. This demands a higher resolution for the A/D converter sampling the output voltage. It also necessitates a lesser conversion time for the A/D converter when switching frequencies on the order of MHz are targeted in digitally controlled power supplies. This has become an inevitable requirement since higher switching frequencies allow smaller values for output filter components, reducing their size dramatically. DSP processor based realization of VRMs switched at higher frequency [1316] results in the requirement of lesser computation time for the dutyratio to achieve near onecycle control [17]. This proves to be an expensive solution when DSPs with higher processing power are targeted. The VRMs utilizing DSPs and based on the architecture of Figure 21 cannot accurately track component variations in the buck output LC filter. 2.2 DPWM Modules in Digitally Controlled DCAC Inverter The closedloop regulated DCAC PWM inverters are widely employed in programmable ac power sources, uninterruptible power supplies and induction motor drives [1821]. The architecture of a typical motor drive application is illustrated in Figure 23. In a typical motor drive application, the control strategy relies on comparing the stator current or the inverter output voltage with a desired reference to maintain regulation and thereby control the speed of the drive. In hysteretic control, the controlled variable is regulated within a hysteretic band [2227]. The comparative listing of the implementation of PWM inverter control, utilizing FPGA and DSP processors are outlined in Table 24 and Table 25 respectively. The DSP processor based current hysteretic control of PWM inverter in [22] and [24], relies on continuous stator current sensing and sampling. The sampled current value is compared with predefined upper and lower limits stored in registers. The digitized stator current value is updated at every sampling instant of the A/D converter. If the sampling frequency is too low, it can lead to current overshoot or undershoot, deviating from the hysteretic band. This necessitates a higher sampling frequency, thereby increasing the cost and power consumption. The various control and implementation strategy of DCDC converters and DCAC inverters discussed above determine the static and dynamic performance. The static performance is mostly met by the aforementioned methods, while the transient performance is limited by the delays involved in sampling and processing. The computation time involved in the various digital blocks restrict the maximum switching frequency [2830], since a portion of the switching time period is to be used for the housekeeping operations. The dynamic characteristics of hystereticmode of control are superior when compared to voltage/currentmode control [31], while it is dependent on the hysteresis band employed. A wider hystereis band for the modulation can alleviate the expensive requirements of faster and higher resolution of digital comparators. On the other hand a wider hysteresis band based modulation may not be a viable solution for lowvoltage VRMs (DCDC converter), where output voltage ripple requirements on the order of 1020mV are desired. Hence a modulation strategy that can offer the dynamic performance of hysteretic mode of operation while employing significant ripple as that of currentmode control and without the need for current sensing is desired. A good linearity between the controlled variable and a command reference under openloop operation can prove to be desirable characteristic with respect to control strategy implementation. These requirements paved the way for synthetic ripple modulation, wherein the controlled variable is bonded to any ac waveform derived from the converter or the inverter, to create a significant amount of ripple. This allows the controlled variable to be regulated with very less ripple. The synthetic ripple composed of the controlled variable and the ac waveform is favorable for hysteretic mode of control to reap the benefit of superior dynamic performance. The design, modeling, simulation, and implementation of the synthetic ripple modulator establish the focus of the remaining chapters. Table 21 DPWM architecture realizations DPWM architecture Parameters Complexity Linearity Area Fastclock counter approach Requires fast Good 1 mm x 1 mm [12] clock flk 2NDPWM f Tapped delayline PWM [11] Externally imposed clockOpen External Poor 0.75 mm x 1.2 mm loop oscillator, delay cell variations Delay cell based closed loop 2N : 1 MUX Poor Hybrid counter /Tapped delay Tradeoff power Good 0.25 mm x 1 mm line [8] for better THD Binaryweighted delay line Requires better Poor matching of delay between cells Segmented DPWM architecture Requires 2N : 1 Moderate 0.0675mm2 MUX and thermometer coding Table 22. Hardware/FPGA realization of DPWM module in DCDC converters Digital control Hardware/ Hardware Application DCDC converters FPGA Implementation Comparison Voltagemode control Hysteretic control Parameters Reference [Chandraksan98 [Maksimovic [Rinne04] [Sanders01] [Yau04] ] 02] Silicon area 3.2mm*2.8mm lmm2 <2.7k gates 3.2mm*2.8mm N/A Power consumption 10_W Clock speed 2.5MHz 8MHz 35MHz145MHz 5MHz 8MHz Obit Hybrid 8bit Hybrid Architecture MXCounter delay 612bit VCDL/DLL 8bit Ring Osc/MUX ALTERA Architecture MUX/Counter line/counter DPWM DPWM EPM7064SLC44 DPWMDPWM Application Buck VRM Buck converter Buck converter Buck VRM Forward converter MultiPhase MultiPhase N/A N/A 4PWM signals 4phase VRM N/A control Programmable switching 330kHz 1MHz 100kHz15MHz 100kHz 180kHz200kHz frequency Features Lowpower Novel delay Programmable Passive current Ultrafast transient response line A/D DPWM sharing Table 23. DSP/Microcontroller realization of DPWM module in DCDC converters DSP/Micro controller Application DCDC converters Implementation Comparison Voltage/Currentmode control Hysteretic control Parameters Reference [Zhang04] [Maksimovic01] [Erickson03] [Batarseh02] Processor engine 16bit fixed point 16bit ADSP2171 ADMC401 TMS320LF2407 DSP Instruction cycle 40MHz 38.5ns 26MIPS 26MHz 33ns parameters 8 channel ADS807 ADC 10bit ADC 8 channel 8channel 12bit ADS807 12bit 12bit 53MHz Hysteretic N/A N/A N/A + 10mV(steadystate) window +20mV(transient) Predictive current control Predictive PFC (CCM/DCM) Multiphase interleaved Features 8bit DPWM module control Constant ON time currentsharing Line current THD = 2.8% MultiPhase MultiPhase N/A N/A N/A 4phase control Switching 160kHz 1MHz 120kHz 190kHz frequency _________ Table 24. Hardware/FPGA realization of DCAC PWM inverter control Digital control Hardware Hardware Application DCAC inverters FPGA Implementation Comparison Voltage/Currentmode control Hysteretic control Parameters Reference [Yokoyama04] [Tzou99] [Guinjoan03] [Betz99] ALTERA ALTERA FPGA/Hardware atix Xilinx XC4005 Xilinx XC4010E3PC84 LEX K Stratix 1S25 FLEX10K50 245 CLB(Config.Logic Silicon area/ 500k gates 5000 logic gates,196 CLB, 112 Blocks) <500k gates 1204 Logic cells Number of gates IOB 30 IOB( I/O blocks) 84 Flipflops Clock speed 80MHz 8MHz 6MHz 10MHz Deadbeat control law based Counter/Comparator Architecture on multiplication and Counter/Comparator/Timer 8b DPWM /Timer PWM additions PWM generator Counter/Comparator generator MultiPhase 3phase control PWM 3phase PWM inverter control N/A 3phase PWM control inverter control inverter control Programmable switching 20kHz 31.25kHz 20kHz40kHz 2.9kHz frequency Table 25. DSP/Microcontroller realization of DCAC PWM inverter control DSP/Micro controller Application DCAC inverters Implementation Comparison Voltage/Currentmode control Hysteretic control Parameters Reference [Tzou95] [Toliyat04] [Mattavelli04] [Mattavelli00] [Round97] Processor engine TMS320C14 TMS320C50/FLEX6000 TMS320F2812 TMS320F240 TMS320C30 Instruction cycle 160ns 50ns 6.67ns 50ns parameters 12bit ADC 16 12bit serial ADC 16bit ADC 16bit ADC c Dual 10bit ADC ADC channel ADC Hysteretic N/A N/A Uses inductor Adaptive Current feature Current slope hysteretic band hysteretic band Switchingtime Adaptive Dead Switchingtime b hseti Multiloop digital Predictive stator current prediction control beat hysteretic control control Features control control Switching ..nr (Current, Voltage and Voltagesource inverter frequency Utilizes onboard Feedforward control) soon PWM modules stabilization for gate signals 1.5kW induction motor Active power Application 1 q! PWM inverter r drive filter Switching 30.72kHz 6.7kHz 10kHz 20kHz frequency V inJ VOWo  Y/ Load d(t) Gain = H d(t)\ T~, ___ d[n] Digital e[n] V[n] AID DPWM < +< 41 DPWM Compensator Figure 21. Generic architecture of digitally controlled DCDC swit[n]hing converter Figure 21. Generic architecture of digitally controlled DCDC switching converter Output duty rath [%] 80 70 60 .0 50  40 30 20 . 0 32 64 96 128 160 DPWM input (decimal) 224 255 Figure 22. Duty ratio based on hybrid DPWM (NDPWM=8bits) [8] Figure 23. Architecture of PWM inverter based 3(D induction motor drive CHAPTER 3 DIGITAL SYNTHETIC RIPPLE MODULATOR Digital Synthetic Ripple modulator (DSRM) functions as a digital to analog converter in producing the PWM pulse signal based on sampled converter waveforms. The DSRM utilizes sampled version of converter parameters like inductor voltage, inductor current, or drainsource voltage of MOSFETS to synthesize an artificial ripple used as carrier signal in pulse width modulation. The modulation strategy is based on bonding the controlled variable to the synthetic ripple generated by the DSRM. The resulting carrier signal is bound between hysteretic limits which dictate the commutation instants of the power MOSFET switches. The modulation strategy can be applied to the control of DCDC and DCAC power converters. 3.1 Design Concept of DSRM In DCDC converters or DCAC inverters employing currentmode control [3234], the ontime and offtime of the power MOSFET switches are inversely proportional to the inductor voltage under steadystate conditions as given in Eq. 31. tON or tOFF L x AL (31) VL where L is the value of the inductor and AIL indicates the peakpeak inductor current ripple. In the generic case, the time duration to be generated can be inversely proportional to a control input (q(V, I)) as given in Eq. 32. K theoretical q K 32) q(V,I) where q(V,I) is a function of voltage or current and K is a constant depending on the application. Similar duty ratio or time duration requirements are exhibited in hysteretic PWM control [3539] having variable switching frequency. The conventional analog approach based duty ratio/timing generators involve current sources and onchip/offchip capacitors. These approaches generally exhibit poor noise sensitivity and offer limited programmability. Timing generators [4043] and duty ratio generators based on digital schemes involve digital pulse width modulators (DPWMs) [4452] that are characterized by a linear relation between the time duration generated and the control input. The DPWMs are based on delaylines [8] [11], propagationdelay of basic gates or the time period of a fast running clock [12]. Synthetic Ripple Modulation based control of power converters involve carrier signal generation from converter based parameters. This modulation strategy, when applied to the control of a DCDC buck converter, utilizes the inductor voltage for its carrier signal generation. Hence, this modulation also involves generation of ontime and offtime duration for power MOSFET switches with inverse relation to a control voltage. In the analog domain, the inverse relation between the on/offtime of the power MOSFET switches and the inductor voltage as in Eq. 31 can be realized by employing a GmC circuit [53] [54]. An alldigital realization to generate timing inversely related to a voltage would involve areaintensive digital division hardware or a costintensive DSP processor based solution. The need for the inverse relation based duty ratio generation as in Eq. 32 led to the development of the digital inverse timing generator. 3.1.1 Digital Inverse Timing Generator The conceptual implementation of the digital duty ratio generation is shown in Figure 3 1. In the developed duty ratio generation scheme, output of an A/D converter sampling a converter parameter is scaled by Nsc to generate a step value (qstep), which is interpreted as a floating point binary number. The step value is successively accumulated at each clock instant (tCLK) until the hysteretic count (2Nc ) is reached, thereby generating a time duration that is inversely proportional to the binary input. The integer portion of the accumulator output is compared to the hysteretic count using a digital comparator. The timing signal is set at the beginning of the accumulation process and reset at the onset of the comparison hit. The number of clock counts required to reach the hysteretic count (2Nc ) and the slope of the staircaseshaped accumulator output are determined by the step value. Hence, a larger step value results in a steeper slope or fewer clock counts, generating shorter time duration and vice versa. The assumption of the step value as a floating point binary number enables the realization of inverse timing generation. The timing generation scheme is based on digital time quantization and accumulation. The digital timing expression embodying the design concept is given to be 2Nc tDltal = xN X tCLK (33) Nsc x NQ(V,I) 2Nc tDigital = x tCLK (34) step where 2N^ denotes the hysteretic count, Nc is the number of bits used for count resolution, N,(v,,) denotes the sampled value of the converter parameter (q(vL,iL, ... VDs)), Nsc indicates the scaling factor, and tCLK is the time period of the clock used for timing quantization of the switching period. The sampled value (A/D output) is related to the converter parameter as NQ(v,=) = G(A) x e s (35) where "A" is the amplitude of the converter parameter used as input in the describing function G(A), "t'" models the phase delay due to the sampling process. The quantization process involved in sampling the converter parameter is modeled using describing function analysis [55]. The describing function for the A/D quantization is expressed by the following relation [56]. 0 A < L 2 G(A) 4qs ( 1 2n1 2n (36)  S1 qLSB qLsB < A < qLSB ;rA2A 1 2 2 where qLSB is the LSB equivalent of the sampled analog input, "A" is the amplitude of the analog input, and "n" is the quantization bin number in the sampling process. The LSB equivalent is obtained from the maximum analog input amplitude (q(V,I)max), the number of bits (NL) allocated for the step value, and the control input. qLSB (I)max (37) 2LSB N 1 _ Based on the static characteristic of the A/D converter, the binary equivalent of the A/D output is equal to the bin number for which the describing function G(A) in Eq. 36 is satisfied. NQ(,) =n (38) The quantized analog output can be determined using Eq. 38 as Q(V, I)quant hardware = nx qLSB (39) 3.1.2 Extraction of Digital Timing Generator Parameters The key parameters involved in the design of digital timing generator are the clock frequency (fCLK), the count resolution (Nc), and the scaling factor (Nsc). The determination of the design parameters follows an iterative procedure supplemented with simulation analysis as a direct consequence of the nonlinear relation described in (32). The parameter extraction procedure begins with an initial assumption for the control input A/D resolution namely NL 10. The digital timing generator can be evaluated with reference to the generated time duration by determining how closely it approximates the time duration obtained from the theoretical expression of Eq. 31. The performance metric for the digital inverse timing generator, namely percentage timing error (Aerror), can be defined as Error ttheorehcal Digital hardware (310) ttheoretcal The selection of the number of bits for step value (NL) and count resolution (Nc) influences the timing accuracy between the digital and the theoretical expression for time duration. The total hysteretic count in the digital SRM is mapped to a hysteretic voltage (Vhys). The hysteretic voltage is selected to be much larger than the ripple on the output voltage of the DCDC buck converter as given in Eq. 311 Vhys > Vout ripple (311) The voltage mapping between the hysteretic voltage and the digital hysteretic count is given as 2Nc X qLs = Vhy, (312) Using Eq. 37 in Eq. 312 the relation governing the number of bits for the sampled converter parameter and the hysteretic count can be obtained. 2Ncx q(V)m < Vh (313) I NL Nc > log2 q(V'/)max' (314) In the limit of the step value approaching unity, the minimum time period of the clock to guarantee a specified timing accuracy can be derived by using Eq. 32 and Eq. 34. t t theorehtcalmm K ; fCLK 1 (315) CLK 2 2 x q(V, I. )max tCLK C The current through an inductor in a power converter under continuous conduction mode is shown in Figure 32 [31]. Also indicated in figure is the DCDC buck converter inductor voltage. The slope of the inductor current during the ontime (toN) and offtime (toFF) intervals as shown in Figure 32 is given by mi = VLro" and m2 = LTff (316) L L where L is the inductor value, vLron and vLroff are the voltages across the inductor during ontime and offtime respectively. The on/offtime of the power MOSFET switch from the Figure 32 can be inferred to be M Mx L M MxL tON ~ ~ ; tOFF = ~ Ix (317) i1 VLTon M2 VLToff The time duration expression involving the inductor voltage is equated with that of the digital duty ratio generation expression to obtain the scaling factor. The digital timing generator utilizes the inductor voltage of the converter to generate the duty ratio for the switches. By equating Eq. 31 to Eq. 33 and utilizing the sampled inductor voltage (vLbn) as the converter parameter, the scaling factor can be determined. tDgtal XCLK L L (318) Nsc X vLbn L where VLbn is determined using Eq. 36 for the given inductor voltage (Amplitude A VL), the quantization level qLs = v = Lmax indicates the LSB equivalent of the sampled inductor voltage and NL is the number of bits allocated for the sampled inductor voltage. The scaling factor reduces to 2Nc V, Nsc LxAL X tCLK (319) 3.1.3. Scaling Approaches The scaling of the sampled inductor voltage with Nsc can be carried out either by binary multiplication or by utilizing the gain of the inductor voltage A/D signal conditioning block. The two approaches are outlined in Figure 33 and their effectiveness is compared by evaluating the timing error performance metric A ...ror.. The scaling of the sampled inductor voltage results in a floating point binary number in both cases. In binary multiplication based scaling, the binary point of the floating point number is dictated by the input and the scaling factor. Hence the feasibility of this approach is affected by the need for additional logic to keep track of the floating point location in the step value and the overhead of binary multiplication. The alternative scaling approach efficiently separates the scaling factor as two ratios, one of which is incorporated into the A/D converter gain block and the other ratio is used for binary shifting. The ratios are indicated in the following equation. NR NR 2N Nsc Nsc hardware DR 2B x (320) The ratios are based on the following set of conditions that ensures maximum number of bits for the fractional portion of the step value to aid in timing accuracy. DR= power of 2; NR < 1 and N, = ceil log2 (NR) (321) The ratio formed using "NR" and 2NB is incorporated into the A/D signal conditioning circuit gain. On the other hand the ratio formed between 2NB and "DR" forms the binary shifting ratio. Hence, this approach eliminates the need for binary multiplication and additional logic required for tracking the initial floating point location. The sequential steps involved in the step value generation for the two approaches are illustrated in Table 31 for a given input. The parameter values used for illustration are NL=10, tCLK 40ns, q(V,J)max=12, andK = 6.2 x 10 6. The scaling factor obtained from Eq. 319 is Nsc = 1.21x10 3 and it is approximated as 5/ (212) to aid in binary operations. The various approximations for the scaling factor are determined from Eq. 321 and the optimum value is chosen by evaluating the timing error performance metric. In Figure 34 various scaling factor approximations are considered and the optimum value (5/212) is determined based on the criteria of minimum timing error (less than 2% over most of the input range). Considering the data in Table 31, in binary multiplication scaling, the A/D output is multiplied with the numerator (NR) of Nsc. The multiplied result (i.e. 882X5=4410) is construed as a floating point binary number with the virtual binary point dictated by the denominator of Nsc. The step value is truncated to NL =10 bits, resulting in 1.076= 1 X 20+0 X 21+0 X 22+0 X 23+1 X 24+0 X 25+0 X 26+1 X 27+1 X 2 +1 X 29. In the A/D gain scaling approach, the ratio of (5/23) is included in the A/D block. The scaling factor inclusion modifies the A/D gain as (A/D Gain) x (5 / 23) and results in the output of (55 1)10o for the given input. The output is considered as a floating point binary number with the binary point location determined by the binary shifting ratio, namely (23/212). Thus the step values are similar in both the cases while the latter approach eliminates the need for binary multiplication. It also avoids the need for additional logic to keep track of the initial floating point location in the step value. It allows for a constant initial floating point location over the entire input range. The parameter Aerror is determined for the two approaches and indicated in Figure 35. From Figure 35 it is evident that A/D gain scaling can yield the minimum percentage error over the entire input range. Hence A/D gain scaling is used in the experimental implementation of the digital timing generator. The difference in time duration from the theoretical expression of Eq. 32 arises from the fact that the scaling factor is approximated using Equations 320 and 321. This timing error is modeled along with the timing error resulting from the successive accumulation and described in the following section. 3.1.4. Successive Accumulation The successive accumulation is carried out by proper alignment of the integer and fractional portion of the step value with that of the accumulator output. The control logic in Figure 31 ensures the alignment of the integer/fractional portion based on the carry output from the accumulator. A carry output of "1" from the accumulator indicates an increment in the integer portion requiring an additional bit for its representation. The step value is logically shifted to the right by one bit with an insertion of a "0" bit at the MSB location. Similarly the accumulator output is shifted to the right by one bit with an insertion of "1" bit at the MSB location. The LSB bit is discarded in the above set of operations to truncate the result to NL bits of precision. A barrel shifter is used to extract the integer portion of the accumulator output and a digital comparator is used to compare with 2N The above set of operations involved in the successive accumulation is explained with the snapshot of the accumulator and input registers shown below. Considering an inductor voltage input of vL=5V and using the derived scaling factor of Ns = (5 / 2) x (2 / 212) the step value can be determined to be 5x 23 L = 5V==> qep = round ( = (266) x = (0,100001010)2 (322) Let ACC[k] and qstep[k] represent the accumulator output and the step value at the "kth" clock instant. A snapshot of the sequence of operations occurring in the accumulator is indicated below. (266)10 = (0,10000 10 10A ==> qtep = (0.51953)10 ACC[1] ==> (0,100001010)2 ==> (0.51953)10 q,tep[1]==> (0,100001010)2 ==> (0.51953)10 + ACC[2]==> (1,000010100)2 ==> (1.0390625)10 q,tep[2]==> (0,100001010)2 ==> (0.51953)10 + ACC[3] ==> (1,100011110)2 ==>(1.55859)10 q,tep[3]==> (0,100001010)2 ==> (0.51953)10 + ACC[4]==> (0,000101000)2 and CY=1 ACC[4 ]==> (10,00010100)2 ==> (2.078125)10 q,tep[4]==> (00,10000101)2 ==> (0.51953)10 The ACC[4+] and qstep[4+] indicate the accumulator output and step values that are modified to account for the carry generated at k=4 clock instant. The timing error due to the various quantizations can be modeled as the increase in the quantized amplitude produced at the A/D output. The difference in time duration (tDigital diff) from the theoretical expression is indicated in Figure 36. The change in the quantized amplitude of the inductor voltage can be modeled by the following equation. K VLquant amp hardware (323) theoretical Digital diff The resulting amplitude modeling the quantization error can be determined from Equations 36, 37 and 38. The digital timing expression including the various truncation and quantization errors is indicated in Eq. 324. 2NC tDigital _hardware X tCLK (3 24) NSC hardware X Lbin hardware where VLbin hardware= n for which the amplitude vLquant amp_hardware satisfies Eq. 36. The MATLAB function modeling the quantization is given in Appendix A. 3.2 Architecture of Digital Synthetic Ripple Modulator In conventional PWM control, the output variable is regulated by comparing a modulating function with that of a carrier signal. The comparison process effectively modulates the time duration of a pulse controlling the on/off position of a switch which in turn determines the duty ratio. In synthetic ripple modulation, the carrier signal utilized in the comparison process is derived from a system parameter unlike the traditional approach of using external oscillators. The modulation strategy is based on bonding the error between the controlled variable and a command variable to a synthetic ripple derived by filtering any ac waveform of the system. The combination of the error and the synthetic ripple forms the carrier signal (modulator output) which is bounded between hysteretic limits. The hysteretic limits dictate the on/off time duration of the switches in the system. Synthetic ripple modulation also allows openloop linear control of an output variable with reference to a command input. Since the modulation scheme derives the carrier signal from the system parameter, it enables natural feedforward control. This modulation scheme when applied to the control of DCDC converter or DCAC inverters, the output voltage of a voltage regulator or the rotor speed in a motor drive can be controlled. In such applications the on/offtime or the duty ratio of the power MOSFET switches can be inversely related to a control voltage input as given in Eq. 31 or Eq. 32. Thus, the above mentioned digital timing generator can be used for generating the duty ratio. The generic architecture of a digital synthetic ripple modulator controlling a desired output variable in a system is illustrated in Figure 37. As indicated in Figure 37, the system parameter related to the duty ratio is sampled and given as input to the digital timing generator. The digital timing generator scales the sampled input and generates the step value. The step value is successively accumulated between the hysteretic limits and the required duty ratio is generated. The PWM output is set to logic high or "1" when the modulator output exceeds the upper hysteretic threshold (2Nc1). The PWM output is set to logic low or "0" when the modulator output is lesser than the lower hysteretic threshold (2N1). f 1 Modulator Output < (2N 1) PWM= = (325) 0 Modulator Output > (+2 1) The PWM signal is retained in logic 1 or logic 0 when the modulator output is outside the hysteresis band. The PWM signal is set to the appropriate logic level once the modulator output is within the hysteresis band based on Eq. 325 and normal SRM operation is resumed. The generic expression modeling the synthetic ripple modulator in the analog domain is given in Eq. 326. ModulatorOutput Analog = Output Variable + Synthetic Ripple (326) The modulator output forming the carrier signal is modulated between the hysteretic limits given as Modulator = Command variable + (Hys/2) (327) Modulator = Command variable (Hys/2) where Modulator+ and Modulator are the higher and lower hysteretic thresholds in the analog domain and Hys indicates the hysteresis band. The schematic representation of Equations 326 and 327 is shown in Figure 38. The subtraction of the command variable from the modulator output expression of Eq. 326 modifies the hysteretic thresholds to (+Hys/2) and (Hys/2). The modulator output expression is changed accordingly as ModulatorOutput Analog Command = (Output Command) + SyntheticRipple In the digital SRM implementation, the error resulting from the difference between the command variable and the output variable is sampled by an A/D converter. The sampled error value (Error binary) indicated in Figure 37 and the synthetic ripple information from integer value of the accumulator are used in the formulation of digital SRM modulator expression. The digital SRM modulator output is given as Modulator Output = (Error binary) + Integer Value (329) In the digital SRM, the sampling of the error value between the command and output variable instead of the actual output variable provides the benefit of allocating higher number of bits for the error. It also offers the benefit of controlling the output variable with better precision. The dynamics of the SRM is also enhanced by the fact that when the sampled value of the error between output and command variable exceeds its higher or lower quantization levels [saturation limits of the A/D (e.g. 0 or 255 with 8 bits of precision)], the PWM signal can be immediately set to logic "1" or logic "0" depending on the saturation limits. The subtraction of the command variable from Eq. 326 as explained earlier modifies the digital SRM hysteretic thresholds as (2N1) and(2N1) with the "Hys" level in analog SRM mapped to 2Nc in the digital SRM. The integer value from the accumulator spans from 0 to 2Nc during both the ontime and off time durations. Thus, to account for the modified hysteretic thresholds, the terms (2N 1) and 2N 1) are added to the digital SRM modulator expression during the offtime and ontime duration respectively. This ensures that with the integer value spanning from 0 to 2 N the modulator output is always modulated with a hysteretic level of 2Nc The resulting digital SRM modulator expression is given in Eq. 330. Modulator Output= ( 2Nc 1 Error _binary [n] ) Integer Value[n] ;PWM = 0 Modulator Output = \ (330) (2N1 Error _binary [ n] ) +Integer Value[n] ;PWM = 1 In the expression describing the digital SRM modulator, Error binary[n] indicates the sampled error voltage of the output A/D and Integer Value[n] is the integer output extracted from the accumulator at tCLK instant "n". Considering the modulator expression Eq. 330, Error binary is negative when the output voltage is above Vcmd. Thus when PWM =1, the higher hysteretic threshold will be attained earlier and Integer Value will span to less than 2Nc resulting in reduced ontime. Similarly when Vout is less than Vcmd, Error binary is positive causing Integer Value to span to 2Nc resulting in increased on time. Similar argument can be applied for the factor of (2Nc1 Error binary) during PWM=0. A lowpass filtering effect similar to integration is obtained in the digital timing generator's accumulator during floating point addition by discarding the least significant bits. Thus the Integer Value[n] qualitatively represents the lowpass filtered output of the sampled converter parameter. 3.3 Application Illustration of the Digital Synthetic Ripple Modulator The DSRM architecture is illustrated below with reference to an application. The modulation strategy is used in the output voltage control of a synchronous buck DCDC converter. The architecture of the digital SRM controlled synchronous buck DCDC converter is shown in Figure 39. The specifications of the DCDC converter are outlined in Table 32. The DCDC buck converter controlled by the digital SRM operates in three distinct modes. * Mode 1: When the error between the output voltage (controlled variable) and command voltage exceeds the upper hysteretic limit (2N 1), the VPWM signal is set to logic "0" or the UFET switch is turned OFF. The switch is retained in this position until the error reduces to within the hysteretic band. * Mode 2: When the error is within the hysteretic band, the digital synthetic ripple modulator controls the converter output voltage. * Mode 3: When the error falls below the lower hysteretic limit(2Nc 1 ), the VPWM signal is set to high or the UFET switch is turned ON. The switch is retained in this position until the error returns to the hysteretic band. The digital SRM employs hysteretic mode of control with switching frequency variations, the ontime and offtime of the highside MOSFET (UFET) is given in Eq. 317 and repeated here for clarity ON = AILxL ; tOFF L xL (331) VLTON VLo FF where AIL is the peaktopeak inductor current ripple under steadystate conditions, VLTo, and vLTof are the inductor voltages during the ontime and offtime respectively. From this the duty ratio can be derived as d = tN (332) toN + tOFF From Eq. 331 it can be inferred that the on/off time duration can be generated using the digital timing generator with the inductor voltage as the system input parameter for the DSRM. The output voltage of the synchronous buck converter is the variable to be controlled by the digital SRM. The output voltage of the buck converter is related to the generated duty ratio as given in Eq. 333. The output voltage is controlled by modulating the duty ratio of the DCDC buck converter. VoU, (t) = d(t) x v(t) (333) The design of the complete system involves the design of LC output filter and the digital SRM controller. 3.3.1 Design of Buck ConverterOutput LC filter The buck converter is designed with an input voltage of 5V and an output voltage of 1.5 V. 1 The LC filter design assumes a switching frequency for the converter to be fs =300 kHz. S The converter output current is assumed to have a nominal value of 4 A. Using steadystate analysis for a buck converter, I, & Lou = 4 A The peakpeak inductor current ripple, AL = Ih, = 16%(IL) = 0.64A out .nom.al = 1.5 V, nominal = 5 V, Road = 0.375 Q, r = 10 mQ (334) The steadystate duty ratio based on the averaged PWMswitch model [57] can be derived from Eq. 335. Vot = RLoad x (DVn D'Vdode) (335) RLoad + rL Thus, the steadystate duty ratio can be determined to be D=0.39. The design of the output filter parameters is based on current ripple requirements and transient regulation requirements. The output filter inductor is determined from the inductor current ripple [58]. L = x( D)x Ts (336) 'hys 1.5x(10.39)x3.33x10 6 L 0.64 4.76kH (337) 0.64 The design of output filter capacitor is based on transient and output voltage ripple requirements. Considering the change in the inductor current for a buck converter during a load stepup and stepdown transient as shown in Figure 310, the inductor current slope can be derived. diL =V" : During stepup transient (338) dt L diL Vo.u dL O : During stepdown transient (339) dt L From Equations 338 and 339 it can be concluded that the outputvoltage overshoot during a loadstep down transient sets the limit on the transient performance of the converter [58]. In order to keep the output voltage Vout within regulation range AVoOu during a load transient ofAloutmax, the minimum required output filter capacitance [58] can be obtained as 1 A!2max _LF 1 "_ Cm = x Lmax x  (340) min 2 AV Vo di dt For a voltage deviation of AVout = 60mV and Alomax = 4A, the minimum output capacitance is determined. Cmin = 415/,F (341) 3.3.2 Design of Digital Synthetic Ripple Modulator The digital SRM controller involves the design of digital timing generator and the resolution of the output variable A/D converter. 3.3.2.1 Digital timing generator The design of the digital timing generator involves the determination of key parameters, namely the input clock frequency (fCLK), count resolution (Nc), scaling factor (Nsc) and the step value resolution (NL). The resolution for the A/D converter is assumed to be NL =8 bits. The count resolution can be determined from Eq. 314. NL Nc > log2 VLmax (342) Vhys VLmax V ...nmax =(1+ (5%)) x = 5.25 V (343) Assuming Vhy, (= 320 mV) > vo_ ppe (= 60 mV) NL Nc> log2 525 V, = 320 mV (344) \320 mV) NLNc log 525 (345) \320 mVJ NL Nc >4 > N = 8 > Nc = 4 (346) By comparing Equations 32 and 318 the parameter K can be determined to be K = AL xL = 0.64A x 4.76kuH = 3.046x106 (347) In a buck converter the maximum voltage across the inductor can occur during startup or during an output short circuit. The inductor voltage under these conditions can be derived using Table 32 to be VL = vou, (348) VLmax = VmaxVo = 5.25 V (349) The minimum time period of the clock required to guarantee minimum time duration accuracy as determined from Eq. 315. K 3.046 x 106 tC= 2=4 36.26 ns (350) CLK Nc V 24x5.25 2 Lmax 5.25 The experimental implementation of the digital timing generator utilizes the onboard oscillator from the ALTERA UP2 board [59]. The time period of the clock used for the digital timing generator fosc ALTERA = 25.175 MHz : tCLK= 39.72 ns (351) fOSC ALTERA The scaling factor can be determined from Eq. 319 to be 24 ( 5.25" 2NC XVLq 28 1 Ns = 3.046 =10 x 39.72 x109 = 4.2955 x 10 (352) sc K c 3.046 x106 Due to restricted availability of the hardware resources, values of NL 8 and Nc 4 results in percentage timing error less than 8%. The buck converter application can tolerate this percentage of timing error due to the delays involved in gate driver and the power MOSFETs. As discussed earlier the experimental implementation utilizes A/D gain block scaling to minimize the Aerror parameter. The scaling factor of Eq. 352 can be approximated based on the conditions stated in Equations 320 and 321. 9 9 24 N = x (353) s 211 16 211 In the above scaling factor, the ratio (9/16) is incorporated into A/D gain and the ratio (24/211) is used to interpret the A/D output as being binary shifted to the left by 4 bits followed by a binary shift to the right by 11 bits. This effectively provides a binary shift to the right by 7 bits. Hence, the 8 bit A/D output is construed as a floating point binary number with 1 bit for the integer portion and 7 bits for the fractional portion. The approximation of the scaling factor indicated in Eq. 353 also influences the timing accuracy between the theoretical and the digital timing generation approach. The possible scaling factors which closely approximate the estimated value are indicated in Table 33. Similarly the binary shifting ratios determining the initial binary point location for the step value are also indicated in Table 33. The optimum approximation for the scaling factor can be deduced by evaluating the timing error performance metric as indicated in Figure 311. The final count value to which the respective step values are accumulated in each case is modified to reduce the percentage timing error. The plot of Figure 311 indicate that timing errors less than 6% can be obtained for the parameter Aerror with Nsc=(9/211), thereby yielding the factor for the experimental implementation. 3.3.2.2 Output voltage A/D resolution The output voltage of the buck converter during the interval when the upper MOSFET (UFET) is ON is given to be Vout = vn vL (354) Avou = Av,, AvL (355) If the input voltage of the buck converter is assumed to be a constant value Avot =Av, (356) The above equation can be interpreted in the digital domain to be the change in output voltage caused by a single LSB change in the inductor voltage. The above equation can be used to derive the limitcycle oscillation constraint [6] [56]. The duty ratio change caused by a single LSB change in the inductor voltage must be less than the output errorvoltage A/D LSB change. The error between the output voltage and the command voltage is given by error = vcmd ot (357) The maximum value of the error voltage can be determined based on the dynamic response requirement. Considering the modulator expression of Eq. 330 the maximum value of Error binary determines how fast the modulator reacts to a transient condition (load stepup or stepdown). The error voltage between the command and the output voltage is sampled based on the A/D transfer characteristic shown in Figure 312. Under a load stepup or stepdown transient condition, the maximum value for the A/D output (Error binary ) in either direction is (2NE 1 or (2NE ). The magnitude of this maximum value should be such that the term 2Nc1 Error_ binary) in Eq. 330 attains the higher or lower hysteretic threshold to trigger the PWM comparator. Thus, the maximum allowable error voltage is given to be Vrrmax. hys (358) Using Vhys value of Eq. 344 in Eq. 358 Vema < 320 mV (359) The LSB of the inductor voltage is given asvLq m, and the LSB of the error voltage is given to be v rmax Lq errq (360) _Lmax errmax (361) 2NL 2NE NL N > int log, V ma. (362) 1 errmax where VL max is the maximum inductor voltage, NE is the resolution of the output error voltage A/D converter and NL is the number of bits used for the step value in the digital timing generator. Hence in a digital synthetic ripple modulator, to avoid limitcycle oscillation, the above conditions need to be satisfied. The above equations when applied to buck converter specifications from Table 32 would yield the following results. VL = 5.25 V and Ve = 320 mV (363) NL NE > 4 (364) The number of bits required for the output error voltage A/D is determined from static regulation requirements. The error voltage resolution must be greater than that of the inductor voltage resolution to ensure that the change in output voltage is tracked by the digital timing generator. Thus, the number of bits to be allocated for the error voltage A/D converter in order to provide a resolution of Verrq 30 mV(verrq > VjLq (= 20.588 mV)) is determined to be NE = int log2 ermax (365) 1 \30 mV NE = 4 (366) Using Equations 364 and 366, the NL can be determined to be NL= 8. 3.4 Modeling and Simulation of Digital SRM Based Buck Converter The buck converter controlled by the Digital Synthetic Ripple modulator involves both digital and analog blocks, which are modeled using MATLAB and Simulink [58] [6062]. The choice of MATLAB/Simulink allows easier systemlevel implementation of the digital SRM, integrating the continuoustime output filter, switching PWM action, and the digital controller. The buck converter shown in Figure 37 comprises of three major components namely the PWM switch, the output LC filter, and the digital SRM controller. The modeling of each of these components is explained in the following sections. 3.4.1 Modeling of PWM Switch For a Buck converter, based on the PWM gate drive, the input to the LC filter is either the input voltage (Vn) or the voltage drop across the synchronous rectifier (catch diode voltage (Vdiode) can be used if a catch diode is used instead of the synchronous rectifier) neglecting the drop across the UFET MOSFET. Hence the converter is modeled as a switch driving the output filter, with the switch outputs decided based on PWM signal (Vn when switch is ON and Vsync rct when switch is OFF). The ontime and offtime of the PWM switch is determined from the timing signal VPWM, the output of the digital SRM controller. The Simulink model is indicated in Figure 313. 3.4.2 Modeling of Output LC filter The output LC filter network with input voltage vphase input current iL and output voltage vou, is described by the following set of equations. L = vphase v it rL (367) dv Cdv= iL iot (368) dt Vout = Vc +rc (iL iot) (369) where rc and rL are the equivalent series resistance of the output capacitor and DC resistance of the inductor respectively. The above set of equations is incorporated into the Simulink model of the Buck filter shown in Figure 314. 3.4.3 Modeling of Digital SRM Controller The modeling of the digital SRM controller involves the A/D converter modeling, digital timing generator modeling. It also includes the generation of the modulator output which combines the output error voltage and the digital timing generator output. The A/D converter or the quantizer model [6165] is based on the LSB equivalent of the A/D converter. The A/D converter model is shown in Figure 315. The zero order hold is used for sampling, the quantizer is used for rounding to the nearest integer, and the saturation block limits the lower and higher digital output levels as specified. The A/D gain used for sampling the inductor voltage is based on the scaling factor. AID Gain Num(N) x= 27.32 (370) v 2B 5.25 16 VLq .281) where vLq is the LSB equivalent of the inductor voltage, VLq = 2Lm The lower and higher digital output levels of inductor voltage A/D are 0 and 255. The A/D gain used in the sampling of the error voltage between output voltage and command reference is given as A/D Gain= 2E = 16.756 (371) v v errq errmax The lower and higher digital output levels of the error voltage A/D are 16 and +15 based on whether the output voltage is higher or lesser than the command voltage. The digital timing generator as described earlier utilizes the sampled inductor voltage to generate the ontime/offtime. The timing generator is modeled with Level 2 Mfile S function utility in Simulink [66]. The block accepts the sampled inductor voltage, timing generator enable signal and the initial binary point location. The accumulated value, integer value, the current step value, and the carry output are fed back as inputs to the timing generator block. The carry output indicates the number of bits currently used for the integer portion of the accumulator output. The Simulink model is indicated in Figure 316. The modulator output is derived from the generic architecture expression of Eq. 330, op (+8) VerrAD[n] ] Integer val[n] ; PWM=0 (372) mod op= (372) [(8) VerrAD[n] ] + Integer val[n] ; PWM=1 The system implementation of the synchronous buck converter controlled by the digital SRM modeled in MATLAB/Simulink is shown in Figure 317. The buck converter waveforms are depicted in Figure 318. The waveforms indicate the inductor voltage (VL), inductor current (iL), output voltage (vout) and the phase voltage phases) for a command input of Vcmd=1.3 V. As seen from the waveforms, the inductor voltage during the UFET ontime is VLTo = 3.66 V and that during the offtime is VLToFF = 1.54 V The output voltage under the steadystate condition can be determined to be v0,t = 1.34 V. The ontime and offtime duration corresponding to these voltages based on the theoretical expression of Eq. 317 are 1.027[ts and 2.44[ts. The step value for accumulation, the accumulator output, and the PWM signal are indicated in Figure 319. The ontime and offtime duration from the simulation waveforms can be determined to be 1.1 [s and 2.6 as. The parameter A ..... can be determined to be less than 7% when comparing the generated time duration with that of the theoretical expression. The step value obtained in the waveforms during the ontime and offtime can be derived as given in Equations 373 and 374. 3.66 x  VLN STEPVAL =round 25 = (100)1 = (0,1100100)2 :> 0.78125 (373) 2'1 1.54x  VLOFF STEPVAL = round 5.25 =(42)1 = (0,0101010)2 :0.328 (374) The actual step values without A/D gain block scaling while based on multiplication can be determined to be A/D output= round L .5 =(178) (375) 2 T =(178) 4.2955 0.7645 (376)1) VLON STEPVAL IILT =(178)1 x 4.2955 x 10 = 0.7645 (376) A/D output = round =(75) (377) 5.25 10 ,(2'1)l VLOFF STEPVAL _UL = (75)10 x 4.2955 x 103 = 0.322 (378) By comparing Equations 373 and 374 with Equations 376 and 378 respectively, it is evident that the A/D scaling closely approximates the required step value. The time duration generated using the digital timing generator is compared with the theoretical expression and plotted in Figure 320. The percentage error is compared in Figure 3 21. 3.4.4 Simulation of Adaptive Voltage Position for Digital SRM based Buck Converter Adaptive voltage position (AVP) is an essential function of lowvoltage VRM designs. The AVP concept utilizes the entire voltage tolerance window during a stepdown or stepup load transient [67]. In AVP, the output voltage is positioned at a voltage level slightly higher than the minimum value (Vout min) at full load. Similarly the output voltage is positioned at a voltage level slightly lower than the maximum value (Vout max) under light load conditions. The AVP design was simulated in MATLAB/Simulink and needs to be experimentally verified in future. The AVP specs are Vin=5 V, Vout=1.55 V, and Alout=5 A. The stepdown load transient is considered with a load current slew rate of 50 A/Us. The maximum load current change is specified as AI,, = 5 A and the assumed Rdroop=16 mQ. The output voltage change under a step down transient is illustrated in Figure 322 indicating the inductor current, load current, capacitor current and the allowed voltage tolerance window. For AVP, it is evident from Figure 322 that the output voltage resonates to the maximum value when the load current reaches zero. This is due to the fact that once the load current is zero, the inductor current flows into the output capacitor to charge it to Vout max. In the digital SRM, the AVP can be easily implemented by turning off the UFET during the stepdown load transient and turning on the UFET once the inductor current reaches zero. The required voltage tolerance window can be determined as, AV re_ = Aut XR +VR = 5 Ax16 mQ+20 mV = 100 mV (379) The L and C are designed such that the output voltage resonates within the tolerance window. The inductor design is based on the ripple spec and given to be L Tffx (1 D)Ts Vout x (1 D) Ts (380) ~L ~L Vout = 1.55 V; D = Vout Vn = 1.55/5 = 0.31; AIL = 0.4 A; fs = 600 kHz L = 55 D)Ts 4.7 pH (381) AL During the loadstep transient the output voltage change occurring across the capacitor is given by AV =AV AAV (382) out C out max out ESR (382) where AVout ESR is the change in Vout due to the ESR of the output capacitor (C) and AVout c is the voltage change across the capacitor due to the load current change of Alout. AV c = AV (Aou, x esr C) = 100 (5 A x 5 mQ) = 75 m (383) out c out max ( ou= 100mV(5Ax5 Q 75(3 The charging time for the output capacitor can be determined from the load current change and the slope of the inductor current during offtime for a buck converter. The AVP design utilizes a load step of 5A at a slew rate of 50 A/as. Thus Alout=5 A. VLToffbuck = V =L A0u (384) tCHG Lx Aout 4.7pH x 5A tCHG Vou 15.1612ps (385) out 1.55 Thus, the net charge in the capacitor due to the load current change is given as 1 AQ= x tCHG xAout (386) The capacitor value can be determined from Equations 383 and 386 as AQ 1 (Alo )2 xL 1 (5)2 x4.7 C= = x ( = x = 400/F (387) AVout c + tolerance 2 Vo x (A c +tolerne) 2 1.55x95mV The capacitor used is 425[aF. The capacitor current is shown in Figure 322 and can be derived as ic (t) = Io t (388) vo (t) = ic(t) + (esr C x ic (t)) (389) At the instant when Vout peaks, dVout/dt=0. Thus, the instant at which Vout peaks can be determined from Equations 388 and 389. tVout peak =tcHG (esr_CxC)= 15.1612 js(5 mQx425 pF) =13.0362 js (390) Using the time duration determined from Equation 390, the slew rate for the command signal can be determined as shown in Equation 391. AVout max 100m V Slew rate cmd outpeak 2 7.67mV/us (391) tVout_ peak 13.0362ts The UFET need to be turned on after 13.0362 ats based on the time duration from Eq. 3.90. This can be accomplished by modifying the original hysteretic count of 2Nc = 16 under the load transient condition. The change in the hysteretic count to turn on the UFET at the instant when Vout peaks is determined from Eq. 396. The inverse timing generator expression in the digital SRM timing is given as 2Nc x, tDgtal CLK (392) STEP Under the stepdown load transient condition, the voltage across the inductor is the output voltage, VLff = Vot = 1.55 V. The step value used for the successive accumulation under the given load condition is given to be SVLJ 1.55/(5.25/255) qSTEP 2 1285 = 0.58816 0.6 (393) qslhf 2N[1 128 Hence to turn on the MOSFET after the time duration determined from Eq. 390, the modification in the hysteretic count can be determined as Hys CountxtCLKtoutek (394) E =t Voutpeak (394) STEP 13.0362/as x 0.6 Hys Count =336 x = 196 ; tCLK = 40 ns (395) 40ns Thus, the increment in the hysteretic count is determined to be Modified Hysteretic count Hyscount =13 (396) 2 N  16 In the digital SRM implementation the hysteretic count of 2Nc = 16 is carried out for 13 additional cycles to determine the turn on instant of the UFET. A counter increments the modified hysteretic count each time the digital timing generator output, namely, Integer value, reaches 2Nc = 16. The error voltage between the command signal and the output voltage is sampled by an A/D converter with NE=4 bits of precision and one additional bit for sign representation (error voltage (+ve) when Vcmd>Vout and (ve) when Vout > Vcmd ). The maximum error voltage is determined from Eq. 359. The error voltage A/D resolution is sufficient enough to track the output voltage change under the load transient. The error binary signal can have oscillations due to the output voltage not exactly coinciding with the peaking of the command signal (caused due to overshoot or undershoot). Because of the flexibility of digital control, the digital SRM compares the current error binary signal to a range of error binary (+1, 0, 1) values based on the error voltage resolution of Verrq=30 mV. Thus to determine the turn on instant of the UFET, the modulator compares the modified hysteretic count to the required value of 13 and also compares the error binary signal to the allowed digital tolerance band. When the required hysteretic count and the range of error values coincide, the UFET is turned on. The simulation outputs for the modified hysteretic count based AVP implementation of the digital SRM is shown in Figure 323 and Figure 324. In Figure 323, the inverse timing generator output (integer value), the modified hysteretic count, and the error binary signal are shown. As evident from Figure 323, integer value spans to the count of 32 for 6 cycles and an additional count of 16 resulting in 13 cycles of the original hysteretic count (2Nc = 16 ). From the figure it is also evident that the error binary signal at the vicinity of turning on the UFET lies within the allowed digital tolerance band. In Figure 324, the output voltage, inductor current, modulator output and the command signal are indicated. The overshoot evident in the output voltage is within the allowed tolerance band of 20 mV. The modified hysteretic count changes the lower hysteretic threshold as 208 (= 2N x 13 ). The resulting modulator output is also indicated in Figure 324. The inductor current, output voltage, modulator output are indicated in Figure 325 for a load stepup condition. A load current step of 5 A is used and the resulting AVP of the output voltage is indicated. Similar to a loadstep down transient the hysteretic count is modified to 208 (=16X13) during the load transient. The upper MOSFET is turned off when the modified hysteretic count is reached and when the error binary signal is within the tolerance band. In the transient AVP design methodology for digital SRM, three difference cases are considered for ramping up the command signal. The three cases are outlined below: Case 1: The command signal is ramped up once the UFET is turned "OFF" and the slew rate is designed such that the peaking of output voltage coincides with the higher level of Vcmd (Vout max). This is the optimum case of transient AVP design. Since Vcmd exactly coincides with the peaking of output voltage, by virtue of SRM the output voltage follows Vcmd without any overshoot or undershoots. The command signal is ramped up with a slew rate of 6.59mV/ats. The AVP of the output voltage is indicated in Figure 326. Case 2: The command signal is ramped up once the UFET is turned "OFF" and the slew rate is designed such that Vcmd reaches Vout_max before the peaking of output voltage. In this case the output voltage slightly overshoots and the follows Vcmd. The command signal is ramped up with a slew rate of 11.9mV/[ts. The AVP of the output voltage, inductor current, modulator output, VPWM, and Error binary for this case are indicated in Figure 327 and Figure 328. Case 3: The command signal is ramped up once the UFET is turned "OFF" and the slew rate is designed such that Vcmd reaches Vout_max after the peaking of the output voltage. In this case the output voltage slightly undershoots due to the fact that it tries to follow Vcmd. The command signal is ramped up with a slew rate of 5.43 mV/[ts. The AVP of the output voltage, inductor current, modulator output, VPWM, and Error_binary for this case are indicated in Figure 329 and Figure 330. The slew rate of the command signal in each of the above cases is designed to be less than the modulator output slew rate. The determination of modulator output slew rate is shown below dmod 2N Lq 16 (5.25 / 255) 658 mV/us (397) dt tON 500 ns Since the ontime modulator output has a steeper slope when compared to offtime the on time slope was used above. The digital SRM provides the significant advantage of programmable slew rate for the modulator to meet the required transient and steadystate specifications. 3.4.5 Modeling of Dynamics involved in the Digital SRM Controller for a Buck Converter The dynamics involved in the digital SRM can be obtained from the command to duty ratio and duty ratio to output voltage transfer functions. The dynamic system model of the digital SRM is indicated in Figure 331. The duty ratio to output transfer function can be obtained from converter system dynamics [31]. The command to output voltage transfer function can be obtained by deriving the command to duty ratio transfer function. The command to output voltage transfer function is thus given to be v =v x d (398) vcmd d vcmd From the digital SRM modulator expression of Eq. 330, the Error binary and Integer value can be derived based on Equations 35, 36, 37, 38, and 39. Error binary = verror x G (vcmd vou) x GE Nerr (399) Integer Value = v x Nsc x G (3100) where GL and GE are the describing function of the A/D quantizer based on Eq. 36 for sampling the inductor voltage and error voltage respectively. Thus the A/D converter model for sampling the inductor voltage is given by G, = G, (A) xe St 3101) The est' term models the phase delay due to the sampling process. The delay tl is given as t + = Ls +Processing delays (3102) 2 where Ts is the switching frequency and processing delays are on the order of 4050 ns. Similarly the A/D converter for the error voltage is modeled as T GE = GNE (A) x et2 t = + Processing delays (3103) 2 The ontime of the power MOSFET switch in a buck converter whose output voltage is controlled by the digital SRM can be derived using Equations 317 and 329 as, 2N Nerr) x tCLK (Vhys V error) x 'CLK n (Ns x VLon x GL) (vn vo ) x Ns x 3104) Similarly the offtime of the power MOSFET can be derived as tof (2Nc + Nerr) x tCLK (Vhys + Vrror) tCLK (3105) o (Nsc x VLTOff xGL) (v,) x Nsc x GL The resulting duty ratio is given by Eq. 331 and can be derived as d= tn (hys error ) Vo x(Ns xGL) (3106) ton +toff rrr (v NscG) (2voutNscG)] + (vhysnNscGL) The time varying duty ratio can be given as the sum of the DC operating point (quiescent point) and the small signal ac component. VD + Vs [Vmd c Vu + x V +out + x (Nsc (3107) \D+d = ^ ^  J^  (3107) Vc+md +Nmd Vout + OUt ( vNSCGL) ou t +v scG, + (Vhys nNSCGL j By crossmultiplying and grouping similar terms the following relation can be determined. The nonlinear terms involving the multiplication of 2 ac quantities are neglected. {Vhy (,GL)] + [(,nGL) ((Vmd VoU )G,)] [2 (VoGL) ((,.d Vot)GE )] d + {[2D((V Vmd)GE)] [D(GL)] [(VhysGL)] (3108) +[((Vcmd Vou )GE)] (VoutG)]} vut = {[2D(VouJL )] (D(GL))][(VouGL )]} cmd The duty ratio to output transfer function is given as v oudo V 1 C Gvd (s) t G2 ; Gdo o = ; Q = R (3109) d s s iD L The above expression can be modified as Gvd() o _ Gd ) Gd (3110) d s2 + s+o2 S2 +Vs+W where W = 02 Gd =Gdo x o 2and V = . Using Eq. 3110 in 3108, the command to Q duty ratio transfer can be derived as d_ [(2D1)(VutGj)] D(VGj]L)] (3111) Vd {Vhys (nG )] + [(GL) (( md u)GE )] [2(VuGL)((Vcmd ,u)GE)] [ Gvd (S)(D(GL))][ Gvd(s)D (2md4Jt)GE] Gvd(S) (VhysGL)] Gd (S)(Td O t)G] Gvd)(S )]} Defining the terms in the numerator and denominator of Eq. 3103 as NumA= [(2D 1)(VoGL,)] [D (V,,GL)] DenA =[Vs (VGL)] DenB =[(,,GL) ((Vcmd Vt)GE,)] [2 (V,,GL)((Vd ut)G)] (3112) DenC = [G (s) (D ( LGL))]+ [Vd (s)D (2V, d ) GE ] [Gvd (S)(VhysGL )]+[Gvd (S)(Vcmd ut)GE,][ Gvd(s)(VutGL)]} T_ d Numxe 2 (3113) vcmd DenAxe 2 DenBxe 2e 2 +DenCx G xe 2 s T y )+T xe +xs2 +VS+W x Using the first order Pade approximation for e "1 in Equations 393 and 395, est (sw / 4) Ts +delays = Tsw (3114) 1 +(Tsw /4) 2 Thus, the command to duty ratio transfer function can be obtained with numerator and denominator coefficients in the "s" domain as (NumA x,)s3 +(NumA(1+VT ))s2 +(NumA(V+W w))s d +(NumAW) (3115) V' {[(DenAx ) (DenBx T)]s3 + +[DenA + DenB + (DenA x V, )(DenBx VT, )]s2 +[(DenAx V) + (DenB x V) + (DenA x WTw) (DenB x WT ) + (DenC x GJT,, )] s +[(DenA xW)+(DenB xW)+(DenC xGd)]} The digital SRM controlled buck converter is simulated in MATLAB/Simulink and the steadystate parameters were derived from the converter outputs. The inputs to digital SRM controlled converter are Vin=5 V, Vcmd=1.3 V, and Rload=0.5 Q. The parameters of the digital timing generator used in simulation are Nc=4, NL=8, tCLK=40 ns, NE=5, and Ts=3.33 [as. The MATLAB function used to determine the coefficients of the command to duty ratio expression is given in Appendix A. The steadystate outputs determined from the simulation are D=0.27 and Vout=1.34 V. The resulting command to duty ratio expression based on Eq. 3115 is given as d 3.27x10 6s +1.9972 +2.312x104s+2.09x109 2.255 x10 6s +1.952S2 +4.225 x 104s + 1.44 x 1010 Vcmd The above expression can be expressed in the polezero gain form as d 1.4504(s + 6.006 x10)(s2 +x04s+1.064 x 109) (3117) S (+8.525105)(s2 +1.319x104S+7.491x109) The magnitude and phase of the command to duty ratio transfer function, duty ratio to output transfer function, and command to output voltage transfer function are plotted in Figures 332, 333, and 334 respectively. These functions need to be verified experimentally. 3.4.6 Design Methodology for Digital SRM Controlling the Synchronous Buck Converter A summary of the design methodology involved in the design of the digital SRM controlling the buck converter is outlined in this section. The digital SRM design process assumes that the parameters of the buck converter, namely, output filter inductor (L=4.7 tH), output capacitor (C=425 tF), input voltage (Vin=5 V; +5%/8%), output voltage (Vout=1.5 V), and peakpeak inductor ripple current (AIL=0.65 A) are known beforehand. The next step of the design process involves determination of the parameters in the digital inverse timing generator. The number of bits for the step value (NL) and the hysteretic count resolution (Nc) are determined from the maximum inductor voltage (VLmax=5.25 V) and the hysteretic voltage (Vhys=320 mV) selected. The equation relating NL and Nc is given from Eq. 314 as NL Nc >og j2 Vmax (3118) NL Nc > 4 (3119) Based on an initial assumption of NL=8 for the inductor voltage resolution, the hysteretic count resolution is determined from Eq. 3118 as Nc=4. The time period of the clock (tCLK =(/fcLK)) required for successive accumulation and timing generation is then determined. tCLK _3 LxL 36.26 ns; fC 1 27.58MHz (3120) CLK required 2Nc xV 3K requrd Lmax CLK Based on the availability of resources, the clock used in the experimental implementation is fCLK=25.175 MHz (tCLK=39.72 ns). The next step involves the determination of the scaling factor based on parameters determined above. Ns = AIL xt =4.2955 x103 (3121) The following step involves the approximation of the scaling factor based on Equations 3 20 and 321 to aid in binary operations. 9 9 24 N = 9 = x2 (3122) sc 211 16 211 (3122) Nsc AD = (3123) 16 The ratio Nsc A/D from Eq. 3123 is incorporated into the A/D signal conditioning circuit utilized for sampling the inductor voltage while the ratio (24/211) is utilized for virtual binary shifting in the step value generation. The final step of the design process involves the determination of number of bits for quantizing the error between the command and the output voltage. The inductor voltage and the error voltage resolution are related by the following equation. NL NE > int log Lmax (3124) V\ Ve max The error voltage resolution and the maximum error voltage are based on transient requirements. Based on the modulator expression of Eq. 330, the maximum error voltage (Verrmax) is selected to be less than or equal to the hysteretic voltage (Vhys) for the PWM comparator to respond instantaneously under a stepup or stepdown load transient. Thus, the relation between the number of bits for the inductor voltage and the error voltage is obtained as (5.25 V 3 NL NE > int log, 25V (3125) 1 E 320 mV NL NE > 4 (3126) The LSB equivalent of the error voltage (Verrq=30 mV) is chosen to be greater than the LSB of the inductor voltage (VLq=20.58 mV) resulting in NE = int log, ermax = 4 (3127) S30mV The AVP requirement of Vout_min=1.5V and Vout_max=1.6V indicates a voltage change of 100 mV. Thus, the number of bits determined for the error voltage and its resolution (Verrq=30 mV) can track this voltage change under a transient load stepup or stepdown condition and satisfy the transient AVP requirement. Based on the parameters determined, the timing generation accuracy is evaluated by comparing the time duration from digital timing generator with that of the theoretical expression as shown in Eq. 3128. LxMAIL 2N^ X tCLK Aerror ...= \l V, (3128) In order to improve the timing generation accuracy, the number of bits for NL can be increased or the time period of the clock (tCLK) used for accumulation can be reduced. The parameter determination procedure is reiterated to reflect the changes. 3.5 Performance Analysis of Digital Synthetic Ripple Modulator 3.5.1 Openloop Linear Control of Controlled Variable with Command Signal The digital SRM allows open loop linear control of the output variable as stated earlier. The command signal Vmd is varied from 1.2 V to 1.8 V and the resulting output voltages are shown in Figure 335. It is evident from Figure 335 that the output voltage follows Vcmd in a linear fashion even under openloop conditions. The openloop operation of the modulator results in an error voltage between the actual output voltage and the command voltage. This arises from the fact that the term VerrAD in Eq. 372 is not adequately compensated. Hence an offset results between the desired output voltage and the actual output voltage in the openloop control of the converter. On the otherhand, the openloop control still provides a linear control of the output voltage with respect to the command voltage. 3.5.2 Influence of Component Variations on the Digital SRM Performance The digital SRM involving generation of carrier signal from converter waveforms allows natural feedforward control. The SRM scheme also enables the carrier signal to better track the component variations. This is shown in Figure 336, which indicates the variation in output voltage for a command signal Vcmd=1.36 V due to variations in converter components values (e.g. L, C, esr_C, rL ) over aging. A variation of +15% is included in the output filter component values of the buck converter. The nominal inductor value used in simulation is L=4.7 tH ( Lmax var = 1.15X4.7 tH=5.4[gH and Lmin var=0.85X4.7 tH=3.99 pH) and the nominal output capacitor value is 4.11 mF ( Cmax var=4.73 mF and Cmin var=3.87 mF ). As evident from Figure 3 36, the output voltage remains within an allowable tolerance level over the 4 combinations of component variations. 3.5.3 Openloop Dynamic Response of the Digital SRM Controlled Buck Converter The openloop load transient response of the digital SRM controlled buck converter is indicated in Figure 337. A stepup load transient is presented to the buck converter with its command voltage held constant at Vcmd=1.5 V. As evident from the figure, the sudden change in load current is immediately supplied by the converter with the help of the digital SRM triggering the UFET VPWM signal to logic high or "1". Also evident from the figure is the droop in the output voltage. The droop in the output voltage results in the increase of the error voltage between command and output voltage. The increased error voltage causes the A/D converter sampling the error voltage to saturate to the higher limit based on Figure 312. Thus the lower hysteretic threshold is reached in Eq. 325 instantaneously, causing the VPWM signal to go to logic high or "1". The current implementation of the digital SRM is based on openloop control with no regulation for the output voltage, causing a droop in the output voltage for the given load transient. 3.6 Advantages of Digital Synthetic Ripple Modulator Digital Synthetic Ripple modulator generates the carrier signal from converter parameter allowing for natural feedforward characteristic. Linear control of the controlled variable can be obtained in openloop configuration and transient performance is better because the controlled variable is directly bonded to synthetic ripple. The principle of digital SRM when applied to speed control of motor drives can eliminate the need for stator current sensing, while providing superior transient performance due to hysteretic operation. Table 31. Sequential steps involved in Step Value generation Parameter Binary Multiplication Scaling A/D Gainblock scaling 1 Analog Input 10.35 10.35 2 A/D Output round(10.35/(12/1023)) round((10.35X5)/((12/1023)X8)) (N()) =(882)10=(1101110010)2 =(551)1o=(1000100111)2 3 Scaled output (882X5)/212=(1,000100111)2 (551)X(23/212)=(1,000100111)2 =1.0762 =1.0762 4 Step Value qstep=(1,000100111)2 qstep=(1,000100111)2 Table 32. DCDC converter specifications S.No Parameter Specification 1 Input Voltage 5V +5%,8% 2 Output Voltage 1.1 1.85V 3 Output current slew rate 50A/[ts 4 Output current selected 4A 5 Output voltage resolution 30mV Table 33. Scaling factor Approximations Actual Scaling Factor Nsc = 4.2955 x 10 Nsc approximation Virtual binary point factor 5/210 =4.88x10 3 23/210 9/211 = 4.3945 x103 24/211 8/211 = 3.90625 x 103 24/211 Figure 31. Conceptual implementation of digital duty ratio generation m VL=O m VLTOff iL L 2 L Figure 32. Inductor current indicating the current ripple and time intervals along with the buck converter inductor voltage Binary Multiplication Scaling AID  ,1OT7 NA r NNfr____ q(V,I..) Ns q _LSB step S bz1 b b, bl b . Integer  Integer Fractional Portion portion Virtual Decimal Pt Virtual Decimal Pt AI/D Gain Block Scaling r1 /AID bNl1 b, b, b0 Integer  2 I pion Fractional Portion 2 I portion Virtual Decimal Pt Den(Ns,) Figure 33. Scaling approaches for step value generation 6  SNSC= 5/212; Count = 16 NL =10 ; tLK= 40ns so L 'L ILK * Nsc= 9/213 Count = 14  Nc= 8/213 ;Count = 13 : 4 . 0 2 Sg 4 6 Control Input Voltage (V) Figure 34. Timing error performance for various scaling factor approximations used in step value generation 12   e A/D Gain block scaling N =5 /212 ;N =4 Binary multiplication scaling a N 10 ;tLK= 4Qns .0 10 L , 0 1 2 3 4 5 6 7 8 9 10 11 12 Control Input Voltage (V) Figure 35. Simulation analysis indicating percentage timing error based on binary multiplication scaling and A/D gainblock scaling 120   120 SNL 10 tCL = 40n Nsc =(5/23)X(23/12) S100 1L, CL 100I I I  LIIL__ _ .2 80 S60 E 40   100 200 300 400 500 600 700 800 900 100C Sampled Inductor voltage in binary It 0  100 200 300 400 500 600 700 800 900 100C Sampled Inductor voltage in binary Figure 36. Simulation analysis indicating percentage timing error based on binary multiplication scaling and A/D gainblock scaling System Parameter Error f (Digital Timing SI ADC Generator Input) S  Digital Timing Generator I fcI Scaling & Successive I N Accumulation I ___ Integer Value PWM SPWM A+BAB P WM I sV ", , Digital SRM 2c '1 ,/ i 2 to Modulator Output I Figure 37. Generic architecture of a system controlled by digital synthetic ripple modulator PWM Modulator Output to tON StOFF Modulator' = Command + Hys / / <  Synthetic Ripple Hys SModulator = Command Hys 2Output Variable Output Variable Figure 38. Generic synthetic ripple modulation showing the hysteretic thresholds, command variable and PWM signal Digital Timing Generator f Scaling & Successive to  I CLK Accumulation 4* Integer Value B PWM PWM A+B/AB I PWM  S  i Digital SRM 2 < ": y ! Digital S I Modulator Output Figure 39. Architecture of digital SRM controlled synchronous buck DCDC converter. V V in m out 1[ 1, A M ~u _L \ L 'hys" \/ \  V  \\A  //,   Outmt t Figure 310. Inductor current waveform during load current stepup and steadydown transient 20 1 _7 E~ F r Wa a)CC U 0~ 6N~ =5/2 3 ;N =2 3I2~ 10Count 16 N~ =9/2 4 ;N =24/211 ;Count 15 Ns =8/24 N B = 24/211 ;Count 15 01 1 1 1 1.5 2 2.5 3 3.5 Inductor Voltage (V) 4 4.5 5 5.5 Figure 311. Simulation analysis of percentage error for various scaling factor approximations +(2N 1 ........... + 3 + 2 + 1  1  2 3 Vcmd .................._...b Figure 312. Transfer characteristic of the A/D converter sampling the error voltage between output and command voltage. VP WM Figure 313. Simulink model of the PWM switch Figure 314. Simulink model of buck LC filter N Digital Output Zero order Quantizer Hold LSB 2N 1 Figure 315. Simulink model of the A/D converter VLbmary Timgen en Init cy digital _timing_ Sample delay Figure 316. Simulink model of digital timing generator Acc _val Integer val Async rect 0.2V 8 ..7 MOD OPf e rr A DC ADC Figure 317. Block diagram depicting the Simulink model of digiterrAl SRM controlled buck Timing converter R Generator + Integer 8 B<0..7> A<0..7> VPWM A+BIAB MOD OP ADDISUB  8 Figure 317. Block diagram depicting the Simulink model of digital SRM controlled buck converter Inductor Current(i 42 ................. ..... ............... ......  2.6tis 3 .  .. ............   ......... ... ..... .. ... ...... ........ ....... ............ .............. ........... 3 ....... ........ ... .. ...... ........ ........ ............ ................. 2 ....... ...... .................... ......... ..... ...... .. ..... ......... ...... ........................... .............. ............ ... ....... 2  1.3415 1.34 1,3395 1.339 2.838 2.84 2.842 2.844 2.846 2.84B Figure 318. Simulation outputs of the synchronous buck converter using MATLAB/Simulink for Vcmd=1.3V L      ............ . . . . . ........ .......... ....... ...... .. O lf V91(og "9 !Wt) ..... ............... ......... .... .. ....... ........ ........         2 1is Id iv   I II 5                 Integer _val .......... ......... .... ... ...... .......... ... .. ... ... .......... ... ......... .. .. .... ....... ........... .......  ....... ..  ............ .... .. ........... . ............ . VPWM .2.6 .s 1.1ps I i 5          . . . . . . 2.838 2.842 2844 2846 284W Figure 319. Simulation outputs indicating the step value, integer value and VPWM signal of the digital timing generator 2.85    .............................. ........... I ........... ............... I    . ...........  . . . ..........    ......................... Yqlue ............ ........................... .............. ...........    ..........  .............    ............   3 34  . ;; .  \ E~ Digital timing Generator Simulation data \Theoretical expression data 'I 1 L =1.5 ,L i , E 0.5 0.5 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Inductor Voltage (V) Figure 320. Comparison between ontime/offtime generated based on theoretical equations and simulated synthetic ripple modulator. 125  so a i L,. o S     0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.E Inductor Voltage (V) Figure 321. Percentage error between digital timing generator and theoretical expression using simulation analysis Alo9 IOUT Slope LTroff L iz (t) Seance 'CHG irv(t) Figure 322. Voltage change across the output capacitor during a stepdown load transient Integer value ..AAAA 14 I I I "12 .  .. . . . . .... . . . . . .. . ... . . . ... .. . . . . '. ..1. . . . . .. . . . S   o i ce hi tc i  4  . . . . ........ .. .... ..... .... ... ...... ..... S :Error binary 1 2 .    * ......  4 .. .. ..... .. ... .. .. .. .. .. ........... .. ......... .. ................ ..  .. ... .                 1.3 1.305 1.31 1.315 1.32 Figure 323. Integer value, modified hysteretic count, VPWM, and Error binary for AVP implementation in digital SRM .... II I I I I I 82 ..... ...... ............ ...... .. ... ....... .... .. ....... .... ..... ............. ..... ....... ................... .... ... .. ... .... ....... ..... 6 6 ............. ... ............ .. ... ... ... ... ... ......... .. .... ..... ... .... .... .. .......       54          InCommnand Signal rd (V)  .  . . I . . . . . . .. . .. .i    i .. . i   . . i . . 1 31 1 32 1 33 1 34 1 35 Figure 324. Integer value, modified hysteretic count, VPWM, and Error_binary for AVP implementation in digital SRM 1 29 1 36 I I I I I I I Inductor Cu:rrent i (A) 1 .4 .. . .. ..... .. ..... .. .. .. .. .... ...... ..... ... .. .. .... ..... ........ 05        4 I I I 250 5  I I Modulator Output 50       1.295 1.3 1.305 1.31 1315 1.32 1.325 1 33 Figure 325. Inductor current and AVP of the output voltage based on optimal AVP design for the load stepup transient ~f SI I I 1 I I I I 62 1.55 d 2.5  ...  .  .. .. .. .......^ ag ^ y         2   F    *  *I . . . . I   . .. ... .I. ... . . .. .. ..I .. .. . .. ... .. ... ... . .. . . .. .. . .. .. . . . . .  1.6       ....       1 5 ........................... ...I 4  ....... 2. Load .urr..t Step I 1)1 Se te =5 ) .... .. ... .... ... .. .. .. ... .... .... .... ..... .... .. .... ... ... .....'"^.. ... .. .... .. ... .. ... .. .... .... .. "..... .. .. .. .. ..... t           1.19 1.2 1.21 1.22 1.23 1.24 1.25 1.26 1.27 Figure 326. Inductor current and AVP of the output voltage based on optimal AVP design for load stepdown transient S ..... .. .. ... .... .. .. .. .. ........ ... ... ... ..... ... .... ........ .. ... .. .. .. .. .. ... .. .. .... ... .... .. .. ...... ......... .. ... ... .... .. .. .    ........    1       ..   16   1.55 .... ........ .... .. .. ... .. I .o.d Sign .L. .... .. .. ... .. ..... ............  ':. .....1 5  1 r  . 1.5 15    w e _ O  2 .  . ... . . . "    . . .    L i oad C rrent SIt'pRi0i(A) (SlewRate = 5OAI s) 1O0s div 1.19 1.2 1.21 1.22 123 1.24 1.25 1.26 1.27 Figure 327. Inductor current and AVP of the output voltage Vcmd reaches higher level before the peaking of Vout (Vout_max) . . .I I 4.  . . . .... . . . . .. 4 . . . . L .. . . . . . .... . . .. . . . ... . . . . t Idicto r Crrent i(A) . . . . . . . . . .: .... . : . . . .. i . . . . . . ....... i............. i... ... ........ i.................. i .. ............. i............... ...................'. ........... ..... 1 5    . . . . .. . . . . I . . . . J.. . . . .. . ... ] . . .. ( .. . .. . .. .. . output ol qgeyv IIIIII I I I 2 0  . ... . .... . . .... . .... . ... . ... .. . .... ..L. .. . . .. . ... .. ... 10 0 1 0     .       . . .. .  W2   0 M  N  WI ....  VjIIII)'IIII l' 10  ........ .. ..      L U.OU  . Moii o irn . . . ... .. . . . .... . ... .. . . ..... .. ... ... ...... ... ... ... ...... .... ... .... .... .... ....... ...... ...... .... ...... .. . b n a r. .... . o L2 : .:.. . . ....... ..... ......... !.................. M c d ik t ...0 111 1i ............. ...,.... : _ 2   I                   . . .. . . . . . . .. . . . .  . i" ~~~..... ... ........:, ................. i ................. i...... . ,. . .J. . .i. . II I 4 4       2 .......  T s ... ...... Load Curyrent Step i (A) (SleirRate = 50AI 1ps) 2        :    .. . .. .  :  . .. ..   1 / y o r   o ~~~~ ~ ~ ........  0 ......... ................. : ; II I I I I I I 1.19 1.2 1.21 1.22 1.23 1.24 1.25 126 1.27 Figure 328. Inductor current and AVP of the output voltage Vcmd reaches higher level before the peaking of Vout (Vout_max) I I I I I I I 1o6 .........       .................... . .. ".... 1       Output Volitge' V (): I I I I 1 .5 .. .. .. .... .. .... .. .. .. ... .. .. .. ... ... ....... ..... .. .... ... .. ...... ... . ... .. ...... .. .... .. .... .. .. .. 1 5 . . . .._. . . .. .. . .. .. .. : .. .. ... .. .. .. .. . .. ... .. .. .. .. . .. .. . : .. .. .. . .. .. . 6     I       I I      I I      I . . .. . .. . I .I .. . . .. . . . .I . .. . . .. . .I . . .   J .I. .    I . S.. ..............................................................  1.19 1.2 1.21 1_22 1.23 1.24 1.25 1_26 1.27 Figure 329. Inductor current, VPWM, and AVP of the output voltage Vcmd reaches higher level after the peaking of Vout (Vout_max)   . . .. . . ...... . . . II I I I I I   1Indue tor Curre nt i (A) 1.55  Output Voll IIIIIII r i l 1 1 1 i i i i i i i i i i i . . . .. . .. . ... . .. ... .. ..,. .. .... .. ..,. .i i l l i i i i f l l i l f l I2       1 0. . ,. . . . . ..:, . 5 .i . . ..  . . . . . .. . ...... ..... . . . . . . . . .. .. . . . . .. . . 2'   .   ..... . .. '.  . . . . . . . . . ,   .  .     10 ,0 1 .. . ... ... i . . . .. . ... . . . . . . ... ... . . . . .. .. . ... . _. . . . . . .  O            2 _...... Load C,.'rent Step .o()SlewRate = 50A,,! tzs) 1.OPzs,, .. i J....... "...................  0 iError i inary 1.19 1.2 1_21 122 1.23 1.24 1.25 1.26 1_27 Figure 330. Modulator output, Errorbinary, and AVP of the output voltage Vcmd reaches higher level after the peaking of Vout Figure 331. Dynamic system model of the digital SRM controlled synchronous buck converter Command to Dutyratio Magnitude(dB) 10 I 0 I  l II I I I lII I I I I I III I I I Il lI l l l l I I II I I l 1 + l L = 4I TiHI = 200 1,", I = 050 II I)=02,.r =51 =1 34I 1. =1.3r . 0  I I 0 4 4 30 1001001 102 103 104 1 0 Command to Dutyratio Phase(degrees) 200 0 100 103 Frequency (Hz) Figure 332. Magnitude and phase of command (vcmd) to duty ratio (d) transfer function 