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Digital Synthetic Ripple Modulator for a DC-DC Converter

HIDE
 Title Page
 Dedication
 Acknowledgement
 Table of Contents
 List of Tables
 List of Figures
 List of symbols and acronyms
 Abstract
 Introduction
 Digital pulse width modulator
 Digital synthetic ripple modul...
 Design and experimental implementation...
 Testing and analysis of digital...
 Conclusion
 Appendix A: Matlab functions
 References
 Biographical sketch
 

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1 DIGITAL SYNTHETIC RIPPLE MODULATOR FOR A DC-DC CONVERTER By BHARATH BALAJI KANNAN A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006

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2 Copyright 2006 by Bharath Balaji Kannan

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3 To the Almighty God.

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4 ACKNOWLEDGMENTS I would like to sincerely expre ss my gratitude and appreciati on for my advisor, Dr. Khai D.T. Ngo, for his constant enc ouragement and thought-provoking id eas that helped me in the development of this dissertati on. I would also like to thank th e Department of Electrical and Computer Engineering at the University of Fl orida, for providing me the necessary financial support. I would like to thank Dr. John G. Harris a nd Dr. William R. Eisenstadt for their valuable suggestions and for being on my dissertation comm ittee. I would also like to thank Dr. Jih-Kwon Peir for serving as my external committee member. I would also like to take this opportunity to thank Dr. Robert M. Fox, who helped me to acquire the skills in the field of integrated circu it design. I am also grateful to Dr. Jacob Hammer for helping me to secure the departmental financ ial assistance towards my research. I would also like to express my gratitude a nd appreciation to the College of Engineering, Anna University, India, for providing an ambient environment to study and learn. Last but not least, I would like to thank my parents, si ster, brother-in-law, and my resourceful friends who gave me the necessary impetus towards the development of this dissertation.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................4 LIST OF TABLES................................................................................................................. ..........8 LIST OF FIGURES................................................................................................................ .........9 LIST OF SYMBOL S AND ACR ONYMNS.................................................................................14 ABSTRACT....................................................................................................................... ............16 CHAPTER 1 INTRODUCTION................................................................................................................. .18 1.1 Conventional Carrier Signal Generation..........................................................................19 1.2 Carrier Signals in Digitally Controlled DC-DC Converters.............................................21 2 DIGITAL PULSE WIDTH MODULATOR..........................................................................22 2.1 DPWM Modules in Digitally Controlled DC-DC Converter...........................................22 2.2 DPWM Modules in Digitally Controlled DC-AC Inverter..............................................24 3 DIGITAL SYNTHETIC RIPPLE MODULATOR................................................................34 3.1 Design Concept of DSRM................................................................................................34 3.1.1 Digital Inverse Timing Generator..........................................................................35 3.1.2 Extraction of Digital Timing Generator Parameters..............................................37 3.1.3. Scaling Approaches...............................................................................................39 3.1.4. Successive Accumulation......................................................................................42 3.2 Architecture of Digital S ynthetic Ripple Modulator........................................................44 3.3 Application Illustration of the Digital Synthetic Ripple Modulator.................................47 3.3.1 Design of Buck Converter-Output LC filter...........................................................49 3.3.2 Design of Digital Synthetic Ripple Modulator.......................................................50 3.3.2.1 Digital timing generator...............................................................................50 3.3.2.2 Output voltage A/D resolution.....................................................................53 3.4 Modeling and Simulation of Digital SRM Based Buck Converter..................................55 3.4.1 Modeling of PWM Switch......................................................................................55 3.4.2 Modeling of Output LC filter.................................................................................56 3.4.3 Modeling of Digital SRM Controller.....................................................................56 3.4.4 Simulation of Adaptive Voltage Position for Digital SRM based Buck Converter...................................................................................................................... 59 3.4.5 Modeling of Dynamics involved in th e Digital SRM Controller for a Buck Converter...................................................................................................................... 65

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6 3.4.6 Design Methodology for Digital SRM Controlling the Synchronous Buck Converter...................................................................................................................... 69 3.5 Performance Analysis of Dig ital Synthetic Ripple Modulator.........................................72 3.5.1 Open-loop Linear Control of Controll ed Variable with Command Signal............72 3.5.2 Influence of Component Variations on the Digital SRM Performance.................72 3.5.3 Open-loop Dynamic Response of th e Digital SRM Controlled Buck Converter...................................................................................................................... 73 3.6 Advantages of Digital S ynthetic Ripple Modulator.........................................................73 4 DESIGN AND EXPERIMENTAL IMPLEM ENTATION OF DIGITAL SYNTHETIC RIPPLE MODULATOR......................................................................................................106 4.1 Experimental Implementation of Synchronous Buck Converter....................................106 4.1.1 Power MOSFET Design and Selection................................................................107 4.1.2 Output Filter Inductor Selection...........................................................................108 4.1.3 Output Filter Capacitor Selection.........................................................................109 4.1.4 Synchronous Buck Gate driver.............................................................................109 4.2 Experimental Implementation of Signal Conditioning Circuit.......................................109 4.3 Hardware Implementation of DC-DC Buck Converter and A/D Signal Conditioning Circuit........................................................................................................................ ........114 4.4 Experimental Implementation of the Digital Timing Generator....................................114 4.5 Experimental Implementation of Digital S ynthetic Ripple Modulat or Controlling the DC-DC Buck Converter....................................................................................................115 5 TESTING AND ANALYSIS OF DIGITAL SRM CONTROLLED BUCK CONVERTER...................................................................................................................... 132 5.1 DC-DC Buck Converter Testing and Measurement.......................................................132 5.2 Signal Conditioning Circuit Testing and Measurement.................................................134 5.3 Digital Synthetic Ripple Modulator C ontrolled Buck Converter Testing and Measurement.................................................................................................................... .135 5.3.1 Digital Inverse Timing Generator Testing...........................................................137 5.3.2 Command to Output Transfer Charact eristic of Digita l Synthetic Ripple Modulator Controlled Buck Converter......................................................................138 5.3.3 Load transient response Step-Response of Digital Synthetic Ripple Modulator Controlled Buck Converter........................................................................................138 5.3.4 Variation of Switching Frequency Based on Load Conditions............................139 5.4 Future Directives for Research.......................................................................................139 6 CONCLUSION................................................................................................................... ..158 6.1 Summary.................................................................................................................... .....158 6.2 Future Work................................................................................................................ ....158 APPENDIX MATLAB FUNCTIONS.............................................................................................................16 0

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7 LIST OF REFERENCES............................................................................................................. 164 BIOGRAPHICAL SKETCH.......................................................................................................170

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8 LIST OF TABLES Table page 2-1 DPWM architecture realizations............................................................................................ 27 2-2. Hardware/FPGA realization of DPWM module in DC -DC converters................................28 2-3. DSP/Micro-controller realization of DPWM m odule in DC-DC converters........................29 2-4. Hardware/FPGA realization of DC-AC PWM inverter control............................................30 2-5. DSP/Micro-controller realization of DC-AC PWM inverter control....................................31 3-1. Sequential steps involved in Step Value generation..............................................................74 3-2. DC-DC converter specifications........................................................................................... .74 3-3. Scaling factor Approximations............................................................................................ ..74 4-1. Comparison of time duration from simulations...................................................................117 4-2 Bill of materials for the synchronous buck DC-DC converter.............................................117 4-3 Bill of materials for the A/D c onverter and signal conditioning circuit...............................117 4-4 Bill of materials for the FPGA based digital controller........................................................118 5-1 Equipment list and specifications......................................................................................... 140

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9 LIST OF FIGURES Figure page 2-1. Generic architecture of digitally controlled DC-DC switching converter.............................32 2-2. Duty ratio based on hybr id DPWM (NDPWM=8bits) .........................................................32 2-3. Architecture of PWM inverter based 3induction motor drive..........................................33 3-1. Conceptual implementation of digital duty ratio generation.................................................75 3-2. Inductor current indicati ng the current ripple and time in tervals along with the buck converter inductor voltage.................................................................................................75 3-3. Scaling approaches fo r step value generation........................................................................76 3-4. Timing error performance for various scalin g factor approximations used in step value generation..................................................................................................................... ......76 3-5. Simulation analysis indicating percentage timing error based on binary multiplication scaling and A/D gain-block scaling...................................................................................77 3-6. Simulation analysis indicating percentage timing error based on binary multiplication scaling and A/D gain-block scaling...................................................................................78 3-7. Generic architecture of a system contro lled by digital synthetic ripple modulator...............79 3-8. Generic synthetic ripple modulation s howing the hysteretic thresholds, command variable and PWM signal...................................................................................................79 3-9. Architecture of digital SRM cont rolled synchronous buck DC-DC converter.....................80 3-10. Inductor current waveform during load current step-up and steady-down transient...........81 3-11. Simulation analysis of percentage erro r for various scaling factor approximations...........81 3-12. Transfer characteristic of the A/D converter sampli ng the error voltage between output and command voltage.............................................................................................82 3-13. Simulink model of the PWM switch...................................................................................82 3-14. Simulink model of buck LC filter........................................................................................ 83 3-15. Simulink model of the A/D converter.................................................................................83 3-16. Simulink model of digital timing generator........................................................................84

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10 3-17. Block diagram depicting the Simuli nk model of digital SRM controlled buck converter...................................................................................................................... ......85 3-18. Simulation outputs of the synchronous buck converter using MATLAB/Simulink for Vcmd=1.3V...................................................................................................................... ..86 3-19. Simulation outputs indicating the step va lue, integer value and VPWM signal of the digital timing generator......................................................................................................8 7 3-20. Comparison between on-time/off-time gene rated based on theoretical equations and simulated synthetic ripple modulator.................................................................................88 3-21. Percentage error between digital timi ng generator and theoretical expression using simulation analysis............................................................................................................ .89 3-22. Voltage change across the output capac itor during a step-down load transient..................90 3-23. Integer_value, modified hysteretic count, VPWM, and Error_binary for AVP implementation in digital SRM..........................................................................................91 3-24. Integer_value, modified hysteretic count, VPWM, and Error_binary for AVP implementation in digital SRM..........................................................................................92 3-25. Inductor current and AVP of the output voltage based on optimal AVP design for the load step-up transient......................................................................................................... 93 3-26. Inductor current and AVP of the output voltage based on optimal AVP design for load step-down transient............................................................................................................ 94 3-27. Inductor current and AVP of the output voltage Vcmd reaches higher level before the peaking of Vout (Vout_max).......................................................................................95 3-28. Inductor current and AVP of the output voltage Vcmd reaches higher level before the peaking of Vout (Vout_max).......................................................................................96 3-29. Inductor current, VPWM, and AVP of the output voltage Vcmd reaches higher level after the peaking of Vout (Vout_max)...............................................................................97 3-30. Modulator output, Error_binary, and AVP of the output voltage Vcmd reaches higher level after the peaking of Vout...............................................................................98 3-31. Dynamic system model of the digital SRM controlled synchronous buck converter.........99 3-32. Magnitude and phase of command (vcm d) to duty ratio (d) transfer function..................100 3-33. Magnitude and phase of duty ratio (d) to output voltage (vout ) transfer function............101 3-34. Magnitude and phase of command (vcmd) to output voltage (vout) transfer function.....102

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11 3-35. Plot indicating the linea r control of output voltage with command voltage based on MATLAB/Simulink simulation.......................................................................................103 3-36. Simulation plot indicating the effect of component variations on the performance of the digital SRM................................................................................................................ 104 3-37. Simulation of open-loop load transien t response of digital SRM controlled buck converter with Vcmd=1.5 V and load step of 5A to 10A in 100 ns (50 A/s)..................105 4-1. Schematic of synchronous buck DC-DC converter.............................................................119 4-2. Current through the UFET in a switching cycle..................................................................119 4-3. Schematic of signal conditioning circuit for the A/D converter w ith inclusion of the scaling factor................................................................................................................. ...120 4-4. Block diagram of the experimental digi tal synthetic ripple m odulator indicating the register enable and timing signals....................................................................................121 4-5. Frequency response of the sign al conditioning circuit amplifier........................................122 4-6. Phase voltage, converter output voltage, and signal conditioning circuit scaled voltages for Vcmd=1.5V...................................................................................................................123 4-7. Inductor voltages at the input of the A/D converter for a duty cycle of D=0.325 and Vcmd=1.5V........................................................................................................................12 4 4-8. Buck converter output voltages, erro r voltage and output A/D input voltage for Vcmd=1.5V........................................................................................................................12 5 4-9. Gerber file indicating th e top layer of the PCB board.........................................................126 4-10. Gerber file indicating th e bottom layer of the PCB board.................................................127 4-11. Photograph of the manufactured PCB board indicating the buck converter and the signal conditioning circuit................................................................................................128 4-12. Timing signals and A/D c onverter input voltages for the signal conditioning circuit......129 4-13. ALTERA board based digital synthetic ripple modulator outputs indicating VPWM outputs for step values (100)10 and (42)10........................................................................130 4-14. Experimental implementation of DS RM controlled buck converter system.....................131 5-1. Experimental test-bed setup used fo r characterizing the DC-DC synchronous buck converter...................................................................................................................... ....141 5-2. Phase node voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3........................141

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12 5-3. Output voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3................................142 5-4. PWM Input (CH2) and high-side gate drive (CH1) for Vin=5V and D=0.3.......................142 5-5. PWM input (CH2) and Vphase (CH1) for Vin=5V and D=0.3..........................................143 5-6. PWM input (CH2) and low-side ga te drive (CH1) for Vin=5V and D=0.3........................143 5-7. Phase node voltage (CH1) and low-side gate drive (CH4) for Vin=5V and D=0.3............144 5-8. Phase node voltage (CH1), output volta ge (CH2) and inductor voltage (Math2) for Vin=5V and D=0.3..........................................................................................................144 5-9. Vphase_pos1 (CH1) and PWM input (C H4) for Vin=5V, Vcmd=1.38V, and D=0.25......145 5-10. Vout_neg1 (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25........145 5-11. VLpos_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.25......................146 5-12. VLneg_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.25......................146 5-13. Verr_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.3...........................147 5-14. VLpos_adc_input (CH3), register-enabl e blnk_pos (CH4) and VPWM from digital modulator (CH1) for Vin=5V and Vcmd=1.38...............................................................147 5-15. VLneg_adc_input (CH3), register-enabl e blnk_neg (CH4) and VPWM from digital modulator (CH1) for Vin=5V and Vcmd=1.38...............................................................148 5-16. A/D converter output for inductor vo ltage during on-time-VLPOS [7-0] (CH3), register enable-blnk_pos (CH4), and VP WM (CH1). A) VLPOS0 (LSB). B) VLPOS1. C) VLPOS2. D) VLPOS3. E) VLPOS4. F) VLPOS5. G) VLPOS6. H) VLPOS7 (MSB)...............................................................................................................149 5-17. A/D converter output for inductor vo ltage during off-time-VLNEG [7-0] (CH3), register enable-blnk_neg (CH4), and VPWM (CH1). A) VLNEG0 (LSB). B) VLNEG1. C) VLNEG2. D) VLNEG3. E) VLNEG4. sF) VLNEG5. G) VLNEG6. H) VLNEG7 (MSB)..............................................................................................................150 5-18. A/D output for error voltage between Vcmd and Vout – VERRAD [7-0] (CH3), register enable-blnk_neg (CH4), and VP WM (CH1). A) VERRAD0 (LSB). B) VERRAD1. C) VERRAD2. D) VERRAD 3. E) VERRAD4. F) VERRAD5. G) VERRAD6. H) VERRAD7 (MSB).................................................................................151 5-19. Verr_adc_input (CH1) and VPWM from digital modulator (CH4) for Vin=5V and Vcmd=1.38...................................................................................................................... 152 5-20. Timing generation comparison based on s imulation, theory and experimental digital timing generation approach..............................................................................................152

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13 5-21. Percentage timing error based on experi mental digital timing generation approach........153 5-22. Linear plot of Vout Vs Vcmd for Vin=4.5V and load resistance RL=1 ........................153 5-23. Linear plot of Vout Vs Vcmd for Vin=4.96V and load resistance RL=1 ......................154 5-24. Linear plot of Vout Vs Vcmd for Vin=4.17V and load resistance RL=1 ......................154 5-25. Linear plot of Vout Vs Vcmd for Vin=5V and load resistance RL=0.67 ......................155 5-26. Linear plot of Vout Vs Vcmd for Vin=4.17V and load resistance RL=0.67 .................155 5-27. Load transient response of the digital SRM Vout (CH2), inductor current (CH4) and load current step (CH3)....................................................................................................156 5-28. Variation of switching frequency with respect to load current for Vin=3.75V, 4.00V and 4.35V...................................................................................................................... ...157

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14 LIST OF SYMBOLS AND ACRONYMNS A/D Analog to Digital D Steady-state duty ratio of the converter DLL Delay-locked loop DPWM Digital Pulse Width Modulator DSRM Di gital synthetic ripple modulator FPGA Field-programmable gate array NC Number of bits for the hyste retic count resolution NL Number of bits for the sampled inductor voltage NQ(V,I) Sampled converter/inverter parameter NSC Scali ng factor used in i nverse timing generation NSC_A/D Ratio of scaling fa ctor used in the si gnal conditioning circuit PCB Printed circuit board PFC Power factor correction q(V,I) Control input for the inverse timing generator qSTEP Step value used in the accumulator tCLK Time period of the clock used for successive accumulation tOFF Off-time of the upper MOSFET switch tON On-time of the upper MOSFET switch TS Switching time period VCDL Voltage-controlled delay line verrq LSB equivalent of the quantized error voltage between output and command voltage

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15 vLbin Binary e quivalent of the quantized inductor voltage vLq LSB equivalent of the quantized inductor voltage VRM Voltage regulator module vOUT Output voltage of the buck converter error Percentage timing error metric for the timing generator IL Peak-peak inducto r current ripple

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16 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DIGITAL SYNTHETIC RIPPLE MODULATOR FOR A DC-DC CONVERTER By Bharath Balaji Kannan December 2006 Chair: Khai D.T. Ngo Cochair: John G. Harris Major Department: Electrical and Computer Engineering Voltage regulator modules (VRMs) powering th e future microprocessors are required to meet the stringent specifications on the core voltage ripple and vo ltage regulation. These specifications are driven by the microprocessor’s higher didt requirements and the need to operate at a lower supply voltage for redu ced power consumption. The conventional VRMs resort to multi-phase pulse width modulation (PWM ) control schemes to cater to the high current demands and provide balanced load current sharing. The cont rol schemes also involve a combination of voltage-mode and current-mode or current-mode and hysteretic-mode control. Thus, these schemes add to the co st and complexity of the VRM. Synthetic ripple modulation (SRM) involves the generation of an artificial ripple, synthesized from a converter parameter which is then bonded to the output voltage of the VRM. This artificial scheme of carrier signal generation for PWM c ontrol enables vol tage-hysteretic modulation to be achieved in the low-voltage VRM modules for microprocessors. With the inherent low-voltage ripple exhi bited by a low-voltage VRM that is insufficient for conventional hysteretic operation, the SRM scheme on the othe r hand provides sufficient ripple for the PWM carrier signal. The SRM scheme blends in the ad vantages of current-mode control and hysteretic control providing superior transient performance.

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17 The introduction of digital co ntrol to the PWM control of switching power converters has gained popularity owing to its benefits of lowe r sensitivity to process a nd mismatch variations, programmability, and the reduction of passive co mponents used in tuning. The digital control based SRM generates the duty ratio with inverse relation to a sa mpled converter parameter. The on-time and off-time duration of the switches form ing the duty ratio is generated by successively accumulating the sampled inductor voltage. The accumulated output forming the synthetic ripple is added to the error between output voltage and reference voltage. Th e carrier signal thus generated is modulated between the higher and lo wer hysteretic thresholds, thus generating the duty ratio. A unique scaling process also allows the implementation of programmable switching frequency for converters. The major contributions of the dissertation in th e field of engineering are given below. Digital synthetic ripple modul ator architecture for applicat ions in power electronics. Digital inverse timing genera tor with wide dynamic range and programmable frequency. The digital SRM scheme is veri fied experimentally in the control of a synchronous buck DC-DC converter. Experimental data are provided to delineate the potential advantages such as inverse timing generation, programmable switching frequency, linear control of output variable with reference variable under ope n-loop conditions, natu ral feed-forward cont rol, and superior transient performance.

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18 CHAPTER 1 INTRODUCTION Low-voltage power supplies powering future mi croprocessors are under constant pressure to provide higher didtrequirement. The core-voltages of curre nt and future microprocessors are on the order of 0.8-1.0V, enabli ng lower power consumption. Th e trend towards low-voltage operation increases the burden on the switching regul ators which are required to maintain a tight tolerance on the core voltage. The allowed tole rance on the core voltage remains at a fixed percentage of the supply voltage in stead of an absolute value in vo lts. This indicates that as the core voltages go down, the tole rance that the processors can handle also scales down proportionately. It is also predic ted that the load current requir ements of these microprocessor cores will increase up to 200A with dynamic current slew-rates on the order of 120A/ns [1-2]. These dynamic loads are tackled with point-of-l oad power supplies whic h derive their output voltage from power conversion of existing 12V supply systems. The dynamic loads also present stricter transient regulation requi rements, thereby creating the need for the design of efficient and enhanced power supply ope ration and control. The dissertation focuses on the generation of carrier signals utilized in pulse width modulation (PWM) control of conve rters/inverters with hysteretic mode of operation. The carrier signals are derived from convert er/inverter parameters such as inductor voltage, drain-source voltage of power MOSFET, inductor current, and stator winding current. The carrier signal is composed of the ripple associated with the variable to be cont rolled and a synthetic ripple derived by filtering (analog approach – integrat ion or digital appro ach – accumulation) a converter parameter. Since the PW M control involves artif icial carrier signal generation, the term synthetic ripple modulation promptly applies. The superimposing of the cont rolled variable with that of the synthetic ripple creates a significan t amount of ripple similar to that exhibited in

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19 conventional current mode control. The modulati on strategy is theoretica lly validated with an application involving the contro l of a DC-DC synchronous buck converter used as a switching regulator for powering microproce ssors. The tight tolerance require d on the output vo ltage of the switching regulator and the higher di/dt (120A/n s) requirement can be achieved with the synthetic ripple modulation (SRM) technique. Since the SRM based c ontrol is a form of hysteretic control modulating the co ntrolled variable dire ctly within a hyster etic band, superior dynamic performance is inherently attained. Th e fact that the output voltage is bonded to a synthetic ripple, resulting in a carrier signal with sufficient rippl e for PWM operation, allows the output voltage to be controlled directly and with the required tight tolerance. The digital SRM (DSRM) scheme employed in the control of the buck converter also involves a novel method for derivi ng the duty ratio, with the gene rated time-intervals inversely related to a sampled converter parameter. The du ty ratio generation scheme is based on a unique scaling process and eliminates the need for a high clock frequency. The modulation scheme utilizes the sampled inductor voltage, which is sc aled and successively ac cumulated to generate the synthetic ripple. The error in the output voltage when comp ared to a reference or command voltage is added to the synthe tic ripple resulting in the carri er signal for PWM operation. The carrier signal is modulated between hysteretic limits, resulting in the required duty ratio. Since the carrier signal involved in the PWM signal generation is derived from the converter parameters in the SRM scheme, natural input feed-f orward control is also attained. This enables better rejection of lin e input disturbances. 1.1 Conventional Carrier Signal Generation Conventional PWM control reli es on three main control sc hemes, namely, voltage-mode control, current-mode control and hysteretic control [3]. In vo ltage-mode control, the carrier signal required for PWM signal generation is base d on an external oscillator. The oscillator

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20 providing the carrier signal is conventionally realized by chargi ng or discharging a capacitor using a constant current source. It suffers from the serious drawback of external component variations and requires better ma tching between an on-chip curre nt source and an external capacitor. The transient performan ce of voltage-mode control is li mited by the delays involved in the compensation circuit forming the feed-back loop. The current-mode control counterpart utilizes the inductor current ri pple for the carrier signal. Th e commutation instants of the MOSFET switches are based on the type of curren t-mode control, namely peak current-mode control, average current-mode control, and va lley current-mode contro l. Current-mode control offers better transient performance when compared to voltage-mode control. This tradeoff is made possible only with accurate current sensing employing a current sense resistor or a current transformer. The a dvantage thus gained over the voltage-mode control is offset by the additional loss in the resistor for higher load cu rrents or by the cost and space requirements of the current sense transformer. In hysteretic control, the carri er signal is implicitly gene rated by regulating the desired output variable within a hystere tic band centered about a referen ce. The hysteretic mode of control provides fast load transient response, requires no feedback loop compensation, and no input filter interaction problems when compared to voltage-mode or current-mode control. In applications requiring the contro lled parameter to be within a marginal hysteresis band, the PWM comparator used in power switch commutati on is required to exhi bit high resolution and fast response. One of the major drawbacks involv ed in the hysteretic mode of control is the variation of the switch ing frequency, increasing the comple xity involved in output filter design. The artificial ripple superimposed onto the co ntrolled variable in th e discussed synthetic ripple modulator is significant enough to el iminate the need for a high resolution PWM

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21 comparator. The synthetic ripple modulator al so blends in the adva ntages of hysteretic modulation by virtue of the control variable being directly tracked by the PWM comparator. 1.2 Carrier Signals in Digitally Controlled DC-DC Converters The conventional voltage/current -mode control based on analog approaches involves more real-estate to accommodate for the external co mponents like resistors, capacitors, current transformer, current-sense resistor, etc. Th e introduction of dig ital control for DC-DC converters/inverters offers a multitude of benefits like insensitivity to component and parameter variations, better noise immunity, ease of progra mmability, reduced size and cost. An application involving the digital control of mi croprocessor power supplies also o ffers the benefits of easier VID code (Voltage Identification Code) integrat ion, fault protection, programmed soft-start, the inevitable features of modern-day voltage-regulator modules (VRM) [2]. Carrier signals for digital control of DC-DC systems are generated using a specific module, namely the Digital Pulse Width Modu lator (DPWM). The DPWMs are based on current starved inverters, fast-clocked counter, tapp ed delay-lines, hybrid approach involving multiplexer and delay-lines, and binary-weighted delay lines. The architectural realization and implementation issues associated with the DPWM architectures are dealt with in chapter 2. The list of symbols and acronyms used in th e dissertation are outlined in Table 1-1.

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22 CHAPTER 2 DIGITAL PULSE WIDTH MODULATOR The digital pulse width modulator (DPWM) block in a digitally controlled power converter/inverter generates the PWM pulse signal controlling the commutation instants of the switches. A typical application involving a DC-DC converter relies on the control and regulation of output voltage or the line/input current of the converter. Similarly a DC-AC inverter application involves the c ontrol/regulation of stator current or inverter output voltage for the speed control of motor-drives. 2.1 DPWM Modules in Digitall y Controlled DC-DC Converter The DPWM module in a DC/DC converter genera tes a discrete set of duty ratio values based on a digital command input word from a discrete-time compensator. The carrier signal involved in the PWM pulse signal generation is implicitly created by the DPWM module. The DPWM module quantizes the switching time period into a number of discrete time slots. A particular time slot is selected ba sed on the digital duty command input ( d[n] ) [4-5]. The selection of a particular time slot and the time duration elapsed dur ing the slot selection determines the commutation instant of the switch and the duty ratio respectively. The carrier signal information is embedded in the archit ecture forming the DPWM module. The generic architecture of a digitally controlled switching DC-DC converter is outlined in Figure 2-1. The discrete set of duty ratio valu es involved in a digitally cont rolled DC/DC converter imposes restrictions on the set of stea dy-state values taken by the output voltage. The resolution of the DPWM module should be higher th an that of the output voltag e A/D resolution to avoid limitcycle oscillations [6].

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23 The DPWM module serves as a D/A converter interfacing the digital control block with that of the switching converter. Several realizations of the DP WM module based on linearity, high-frequency capability, area, complexity and pow er consumption are outlined in literature [711]. A summary of the DPWM reali zations are shown in Table 2-1. Due to the profound developments in Field-pr ogrammable gate-array (FPGA) and the DSP processors sector of the semiconductor industr y, the realization of su ch DPWM modules is becoming much easier. A comparative listing of th e current approaches fo r the realization of DPWM modules in DC-DC conve rters based on FPGA/IC-level and DSP implementation is indicated in Table 2-2 and Table 2-3 respectively. The approaches are also distinguished based on voltage-mode, current-mode and hysteretic control of DC-DC converters. The set of duty ratio generated from a hybrid DPWM [8] involvi ng multiplexers and counters is shown in Figure 2-2. Based on the characteristic in Figure 22, a linear relation betw een the digital command word and the output duty ratio is sought in the digital control schemes which are based on Figure 2-1. The realizations based on IC-level/FPGA im plementation are tailor ed to a particular application resulting in restricted programmab ility of the switching frequency. The linearity between the duty-ratio command input and the PWM pulse signal exhibited by silicon-based DPWM modules relies on careful layout techniques and better matching between the delay cells [7]. The DPWMs based on tapped delay-lines are sus ceptible to drifts in the switching frequency, due to process and temperature variations in individual delay cells. The power supply ripplerejection performance necessitates differential delay cell designs [11] The DPWMs realized from the counter/comparator scheme suffers from the serious drawback of higher power consumption. The need for higher resolution in low-voltage VRMs, leads to higher clock

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24 frequency requirement in the range of 200-800M Hz attributing to higher power consumption [12]. DC-DC converters employed in low-voltage VR M’s are tied with st ricter static and transient specifications with regulation toleranc e less than 5%. This demands a higher resolution for the A/D converter sampling the output voltage It also necessitates a lesser conversion time for the A/D converter when switching frequencies on the order of MHz are targeted in digitally controlled power supplies. This has become an inevitable requirement since higher switching frequencies allow smaller values for output filter components, reducing th eir size dramatically. DSP processor based realization of VRMs switched at higher frequency [13-16] results in the requirement of lesser computation time for the duty -ratio to achieve near one-cycle control [17]. This proves to be an expensive solution when DS Ps with higher processing power are targeted. The VRMs utilizing DSPs and based on the archite cture of Figure 2-1 ca nnot accurately track component variations in th e buck output LC filter. 2.2 DPWM Modules in Digitall y Controlled DC-AC Inverter The closed-loop regulated DC-AC PWM invert ers are widely employed in programmable ac power sources, uninterruptible power supp lies and induction motor drives [18-21]. The architecture of a typical motor drive applicati on is illustrated in Figure 2-3. In a typical motor drive application, the control strategy relies on co mparing the stator curren t or the inverter output voltage with a desired reference to maintain regu lation and thereby control the speed of the drive. In hysteretic control, the contro lled variable is regulated with in a hysteretic band [22-27]. The comparative listing of the implementation of PW M inverter control, utilizing FPGA and DSP processors are outlined in Tabl e 2-4 and Table 2-5 respectively. The DSP processor based current hysteretic c ontrol of PWM inverter in [22] and [24], relies on continuous stator current sensing and sampling. The sampled current value is compared

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25 with predefined upper and lower limits stored in registers. The digitized stator current value is updated at every sampling instant of the A/D conve rter. If the sampling frequency is too low, it can lead to current overshoot or undershoot, deviating from the hysteretic band. This necessitates a higher sampling frequency, thereby incr easing the cost and power consumption. The various control and implementation strategy of DC-DC c onverters and DC-AC inverters discussed above determine the static and dynamic performance. The static performance is mostly met by the aforementioned methods, wh ile the transient performance is limited by the delays involved in sampling and processing. Th e computation time involved in the various digital blocks restrict the maximum switching frequency [2830], since a portion of the switching time period is to be used for the housekeepi ng operations. The dynami c characteristics of hysteretic-mode of control are superior when compared to voltage/current-mode control [31], while it is dependent on the hysteresis ba nd employed. A wider hystereis band for the modulation can alleviate the expe nsive requirements of faster a nd higher resolution of digital comparators. On the other hand a wider hystere sis band based modulation may not be a viable solution for low-voltage VRMs (DC-DC converter), where output voltage ripple requirements on the order of 10-20mV are desired. Hence a modulation strategy that can offer the dynamic performance of hysteretic mode of operation while employing significant ripple as that of current-mode control and without the need for current sensing is desired. A good linea rity between the cont rolled variable and a command reference under open-loop operation can pr ove to be desirable characteristic with respect to control strategy implementation. These requirements paved the way for synthe tic ripple modulation, wherein the controlled variable is bonded to any ac waveform derived fr om the converter or the inverter, to create a

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26 significant amount of ripple. This allows the contro lled variable to be regulated with very less ripple. The synthetic ripple composed of the controlled variable and the ac waveform is favorable for hysteretic mode of control to reap the benefit of superior dynamic performance. The design, modeling, simulation, and implementation of the synthetic ripple modulator establish the focus of the remaining chapters.

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27 Table 2-1 DPWM architecture realizations Parameters DPWM architecture Complexity Linearity Area Fast-clock counter approach [12] Requires fastclock DPWMN clkS f f 2 Good 1 mm 1 mm Tapped delay-line PWM [11] Externally imposed clock-Open loop External oscillator, delaycell variations Poor Delay cell based – closed loop 21N: MUX Poor 0.75 mm 1.2 mm Hybrid counter /Tapped delay line [8] Tradeoff power for better THD Good 0.25 mm 1 mm Binary-weighted delay line Requires bettermatching of delay between cells Poor Segmented DPWM architecture Requires 21N: MUX and thermometer coding Moderate 0.0675mm2

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28Table 2-2. Hardware/FPGA realization of DPWM module in DC-DC converters Digital control Hardware/ FPGA Implementation Application DC-DC converters Comparison Parameters Voltage-mode control Hysteretic control Reference [Chandraksan98 ] [Maksimovic 02] [Rinne04] [Sanders01] [Yau04] Silicon area 3.2mm*2.8mm 1mm2 <2.7k gates 3.2mm*2.8mm N/A Power consumption 10 W Clock speed 2.5MHz 8MHz 35MHz-145MHz 5MHz 8MHz Architecture 10bit -Hybrid MUX/Counter DPWM 8bit -Hybrid delayline/counter DPWM 6-12bit VCDL/DLL DPWM 8-bit Ring Osc/MUX DPWM ALTERA EPM7064SLC44 Application Buck VRM Buck converter Buck converter Buck VRM Forward converter Multi-Phase control N/A N/A 4-PWM signals 4-phase VRM N/A Programmable switching frequency 330kHz 1MHz 100kHz-15MHz 100kHz 180kHz-200kHz Features Low-power Novel delayline A/D Programmable DPWM Passive current sharing Ultra-fast transient response

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29Table 2-3. DSP/Micro-controll er realization of DPWM module in DC-DC converters DSP/Microcontroller Implementation Application DC-DC converters Comparison Parameters Voltage/Current-mode control Hysteretic control Reference [Zhang04] [Maksimovic 01] [Erickson03] [Batarseh02] Processor engine 16-bit fixed point DSP 16-bit ADSP-2171 ADMC401 TMS320LF2407 Instruction cycle parameters 40MHz 38.5ns 26MIPS 26MHz 33ns ADC 10-bit ADC 8 channel 12bit 8-channel 12bit ADS807 12-bit 53MHz Hysteretic window N/A N/A N/A 10mV(steady-state) 20mV(transient) Features Predictive PFC control 8-bit DPWM module Predictive current control (CCM/DCM) Constant ON time Line current THD = 2.8% Multi-phase interleaved current-sharing Multi-Phase control N/A N/A N/A 4-phase Switching frequency 160kHz 1MHz 120kHz-190kHz

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30Table 2-4. Hardware/FPGA realizati on of DC-AC PWM inverter control Digital control Hardware FPGA Implementation Application DC-AC inverters Comparison Parameters Voltage/Current-mode control Hysteretic control Reference [Yokoyama04] [Tzou99] [Guinjoan03] [Betz99] FPGA/Hardware ALTERA Stratix 1S25 Xilinx XC4005 Xilinx XC4010E-3-PC84 ALTERA FLEX10K50 Silicon area/ Number of gates <500k gates 5000 logic gates,196 CLB, 112 IOB 245 CLB(Config.Logic Blocks) 30 IOB( I/O blocks) 84 Flip-flops 1204 Logic cells Clock speed 80MHz 8MHz 6MHz 10MHz Architecture Dead-beat control law based on multiplication and additions Counter/Comparator/Timer PWM generator 8-b DPWM – Counter/Comparator Counter/Comparator /Timer PWM generator Multi-Phase control 3-phase control PWM inverter control 3-phase PWM inverter control N/A 3-phase PWM inverter control Programmable switching frequency 20kHz 31.25kHz 20kHz-40kHz 2.9kHz

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31Table 2-5. DSP/Micro-controller realiza tion of DC-AC PWM inverter control DSP/Microcontroller Implementation Application DC-AC inverters Comparison Parameters Voltage/Current-mode control Hysteretic control Reference [Tzou95] [Toliyat04] [M attavelli04] [Mattavelli00] [Round97] Processor engine TMS320C14 TMS320C50 /FLEX6000 TMS320F2812 TMS320F240 TMS320C30 Instruction cycle parameters 160ns 50ns 6.67ns 50ns ADC 16-bit ADC 16-bit ADC 12-bit ADC 16 channel Dual 10-bit ADC 12-bit serial ADC Hysteretic feature N/A N/A Uses inductor Current slope Adaptive hysteretic band Current hysteretic band Features Multi-loop digital control (Current, Voltage and Feed-forward control) Predictive stator current control Voltage-source inverter Switching-time prediction control Switching frequency stabilization Adaptive Deadbeat hysteretic control Utilizes on-board PWM modules for gate signals Application 1 PWM inverter 1.5kW induction motor drive Active power filter Switching frequency 30.72kHz 6.7kHz 10kHz 20kHz

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32 Switching Converter LoadoutV GainH / A D[]outVninV []refVn [] enDigital Compensator [] dn DPWM SDT STdt () Figure 2-1. Generic architect ure of digitally controlled DC-DC switching converter Figure 2-2. Duty ratio based on hybrid DPWM (NDPWM=8bits) [8]

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33 3 Induction motor inV A DCaibici / DSPFPGA R EFi P Q RS TU P Q RSTU Figure 2-3. Architecture of PWM inverter based 3induction motor drive

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34 CHAPTER 3 DIGITAL SYNTHETIC RIPPLE MODULATOR Digital Synthetic Ripple modulator (DSRM) functions as a digital to analog converter in producing the PWM pulse signal based on sampled converter waveforms. The DSRM utilizes sampled version of converter parameters like in ductor voltage, inductor current, or drain-source voltage of MOSFETS to synthesize an artificial ripple used as carrier signal in pulse width modulation. The modulation strate gy is based on bonding the controlle d variable to the synthetic ripple generated by the DSRM. The resulting ca rrier signal is bound between hysteretic limits which dictate the commutation instants of the power MOSFET switches. The modulation strategy can be applied to the control of DC-DC and DC-AC power converters. 3.1 Design Concept of DSRM In DC-DC converters or DC-AC inverters em ploying current-mode control [32-34], the on-time and off-time of the power MOSFET switches are inversely proportional to the inductor voltage under steady-state condi tions as given in Eq. 3-1. L ONOFF LLI tort v (3-1) where L is the value of the inductor and IL indicates the peak-peak inductor current ripple. In the generic case, the time duration to be generated can be invers ely proportional to a control input ((,) qVI) as given in Eq. 3-2. (,)theoreticalK t qVI 3-2) where q(V,I) is a function of voltage or current and K is a constant depending on the application. Similar duty ratio or time duration requireme nts are exhibited in hysteretic PWM control [35-39] having variable switching frequency. The conventional analog approach based dutyratio/timing generators involve current s ources and on-chip/off-ch ip capacitors. These

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35 approaches generally exhibit poor noise sensitivity and offer limited programmability. Timing generators [40-43] and duty ratio generators base d on digital schemes invol ve digital pulse width modulators (DPWMs) [44-52] th at are characterized by a linear relation between the time duration generated and the control input. Th e DPWMs are based on delay-lines [8] [11], propagation-delay of basic gates or the tim e period of a fast running clock [12]. Synthetic Ripple Modulation based control of power converters involve carrier signal generation from converter based parameters. Th is modulation strategy, when applied to the control of a DC-DC buck converter, utilizes the inductor voltage fo r its carrier signal generation. Hence, this modulation also involves genera tion of on-time and off-time duration for power MOSFET switches with inverse rela tion to a control voltage. In the analog domain, the inverse relation between the on/off-time of the power MO SFET switches and the i nductor voltage as in Eq. 3-1 can be realized by employing a Gm-C circ uit [53] [54]. An all-digital realization to generate timing inversely related to a voltage would involve area-inten sive digital division hardware or a cost-intensive DSP processor ba sed solution. The need for the inverse relation based duty ratio generation as in Eq. 3-2 led to the development of th e digital inverse timing generator. 3.1.1 Digital Inverse Timing Generator The conceptual implementation of the digita l duty ratio generation is shown in Figure 31. In the developed duty ratio generation sc heme, output of an A/D converter sampling a converter parameter is scaled by NSC to generate a step value ( qstep), which is interpreted as a floating point binary number. The step value is successively accumulated at each clock instant ( tCLK) until the hysteretic count (2CN) is reached, thereby genera ting a time duration that is inversely proportional to the binary input. The integer portion of the accumulator output is

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36 compared to the hysteretic count using a digita l comparator. The timing signal is set at the beginning of the accumulation process and reset at the onset of the comparison hit. The number of clock counts required to reach the hysteretic count (2CN) and the slope of the staircase-shaped accumulator output are determined by the step value. Hence, a larger step value results in a steeper slope or fewer clock counts, genera ting shorter time duration and vice versa. The assumption of the step value as a floating point binary number enables the realization of inverse timing generation. The timing generation scheme is based on digi tal time quantization and accumulation. The digital timing expression embodying th e design concept is given to be (,)2CN D igitalCLK SCQVItt NN (3-3) 2CN D igitalCLK steptt q (3-4) where 2CNdenotes the hysteretic count, CN is the number of bits used for count resolution, (,) QVINdenotes the sampled value of the converter parameter (q(vL,iL,…VDS)), SCN indicates the scaling factor, and CLKtis the time period of the clock used for timing quantization of the switching period. The sampled value (A/D output) is rela ted to the converter parameter as 1(,)() s t QVINGAe (3-5) where “A” is the amplitude of the converter paramete r used as input in the describing function G(A), “t1” models the phase delay due to the sa mpling process. The quantization process involved in sampling the converter parameter is modeled using desc ribing function analysis [55]. The describing function for the A/D quantizatio n is expressed by the following relation [56].

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37 2 1 0 2 () 4 212121 1 222LSB n LSB LSBLSBLSB iq A GA q inn qqAq AA (3-6) where qLSB is the LSB equivalent of the sampled analog input, “A” is the amplitude of the analog input, and “n” is the quantizati on bin number in the sampling process. The LSB equivalent is obtained from the maximum analog input amplitude (q(V,I)max), the number of bits (NL) allocated for the step va lue, and the control input. max(,) 21LLSB NqVI q (3-7) Based on the static charact eristic of the A/D converter, the bina ry equivalent of the A/D output is equal to the bin number for which the describing function G(A) in Eq. 3-6 is satisfied. (,) QVINn (3-8) The quantized analog output can be determined using Eq. 3-8 as _(,)quanthardwareLSBQVInq (3-9) 3.1.2 Extraction of Digital Ti ming Generator Parameters The key parameters involved in the design of digital timing gene rator are the clock frequency ( fCLK), the count resolution ( NC), and the scaling factor ( NSC). The determination of the design parameters follows an iterative procedur e supplemented with simulation analysis as a direct consequence of the non-lin ear relation descri bed in (3-2). The parameter extraction procedure begins with an initial assumption for the control input A/D resolution namely NL=10 The digital timing generator can be evaluated with reference to the generated time duration by determining how closely it approximates the time duration obtained from the theoretical expression of Eq. 3-1. The performance metric for the digital inverse timing generator, namely percentage timing error ( error), can be defined as

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38 _theoreticalDigitalhardware error theoreticaltt t (3-10) The selection of the number of bits for step value ( NL) and count resolution ( NC) influences the timing accuracy between the digital and the theoretical expression for time duration. The total hysteretic count in the digital SRM is mapped to a hysteretic voltage ( Vhys). The hysteretic voltage is selected to be much larger than the ripple on the output voltage of the DC-DC buck converter as given in Eq. 3-11 Vhys vout_ripple (3-11) The voltage mapping between the hysteretic vol tage and the digital hysteretic count is given as 2CN LSBhysqV (3-12) Using Eq. 3-7 in Eq. 3-12 the relation gove rning the number of bits for the sampled converter parameter and the hyste retic count can be obtained. max(,) 2 2C LN hys NqVI V (3-13) max 2(,)LC hysqVI NNlog V (3-14) In the limit of the step value approaching un ity, the minimum time period of the clock to guarantee a specified timing accuracy can be derived by using Eq. 3-2 and Eq. 3-4. min max1 ; 22(,..)CCtheoretical CLKCLK NN CLKt K tf qVIt (3-15) The current through an inductor in a power converter under continuous conduction mode is shown in Figure 3-2 [31]. Also indicated in figu re is the DC-DC buck conve rter inductor voltage.

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39 The slope of the inductor current during the on-time ( tON) and off-time ( tOFF) intervals as shown in Figure 3-2 is given by and LToff LTonv v mm LL 12 (3-16) where L is the inductor value, LTonv and LToffv are the voltages acro ss the inductor during on-time and off-time respectively. The on/off-time of the power MOSFET switch fr om the Figure 3-2 can be inferred to be ; LLLL ONOFF LTonLToff I ILIIL tt mvmv 12 (3-17) The time duration expression invo lving the inductor voltage is equated with that of the digital duty ratio generation expr ession to obtain the scaling fact or. The digital timing generator utilizes the inductor volt age of the converter to generate th e duty ratio for the switches. By equating Eq. 3-1 to Eq. 3-3 and utili zing the sampled inductor voltage (Lbinv ) as the converter parameter, the scaling factor can be determined. 2CN L DigitalCLK SCLbinL I L tt Nvv (3-18) where Lbinv is determined using Eq. 3-6 for the given inductor voltage (Amplitude A= vL), the quantization level max21LL LSBLq Nv qv indicates the LSB equivalent of the sampled inductor voltage and LN is the number of bits allocated for the sampled inductor voltage. The scaling factor reduces to 2CN Lq SCCLK Lv Nt LI (3-19) 3.1.3. Scaling Approaches The scaling of the sample d inductor voltage with SCN can be carried out either by binary multiplication or by utilizing the gain of the i nductor voltage A/D signal conditioning block. The

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40 two approaches are outlined in Figure 3-3 and th eir effectiveness is compared by evaluating the timing error performance metricerror The scaling of the sampled i nductor voltage results in a fl oating point binary number in both cases. In binary multiplication based scaling, the binary point of the floating point number is dictated by the input and the scaling factor. He nce the feasibility of this approach is affected by the need for additional logic to keep track of the floating point location in the step value and the overhead of binary multiplication. The alternative scaling approach efficiently separates the scaling factor as two ratios, one of which is incorporated into the A/D converter gain block and the other ratio is used for bina ry shifting. The ratios are indica ted in the following equation. _2 2 B BN SCSChardware NNRNR NN DRDR (3-20) The ratios are based on the following set of conditions that ensures maximum number of bits for the fractional portion of the step value to aid in timing accuracy. 2 2; 1 and log 2BB NNR DRpowerofNceilNR (3-21) The ratio formed using “ NR” and 2 B Nis incorporated into the A/D signal conditioning circuit gain. On the other hand the ratio formed between 2 B N and “ DR” forms the binary shifting ratio. Hence, this approach eliminates the need for binary multiplication and additional logic required for tracking the initial fl oating point location. The sequent ial steps involved in the step value generation for the two appr oaches are illustrated in Tabl e 3-1 for a given input. The parameter values used for illustration are NL=10 tCLK=40ns q(V,I)max=12, and66.210 K The scaling factor obtained from Eq. 3-19 is 31.2110SCN and it is approximated as 5/ (212) to aid in binary operations. The various approxi mations for the scaling factor are determined from Eq. 3-21 and the optimum value is chos en by evaluating the ti ming error performance

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41 metric. In Figure 3-4 various scaling factor a pproximations are considered and the optimum value (5/212) is determined based on the criteria of minimum timing error (less than 2% over most of the input range). Considering the data in Table 3-1, in bina ry multiplication scaling, the A/D output is multiplied with the numerator ( NR ) of NSC. The multiplied result (i.e. 882X5=4410) is construed as a floating point binary numb er with the virtual binary poin t dictated by the denominator of NSC. The step value is truncated to NL =10 bits, resulting in 1.076= 1 X 20+0 X 2-1+0 X 2-2+0 X 2-3+1 X 2-4+0 X 2-5+0 X 2-6+1 X 2-7+1 X 2-8+1 X 2-9. In the A/D gain scaling approach, the ratio of (5/23) is included in the A/D block. The scaling factor inclusion modifies the A/D gain as 3/ 5/2 ADGain and results in the output of (551)10 for the given input. The output is considered as a floating point binary number w ith the binary point location determined by the binary shifting ratio, namely (23/212). Thus the step values are sim ilar in both the cases while the latter approach eliminates the need for binary multiplication. It also avoids the need for additional logic to keep track of the initial floating point location in the step value. It allows for a constant initial floating point location over the entire input range. The parameter error is determined for the two approaches and indicated in Figure 3-5. From Figure 3-5 it is evident that A/D gain scaling can yield the minimum percentage error over the entire input range. Hence A/D gain scaling is used in the experimental impl ementation of the digital timing generator. The difference in time duration from the theoretical expression of Eq. 3-2 arises from the fact that the scaling factor is approximated using Equations 3-20 and 3-21. This timing error is modeled along with the timing error resulting from th e successive accumulation and described in the following section.

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42 3.1.4. Successive Accumulation The successive accumulation is carried out by proper alignment of the integer and fractional portion of the step value with that of the accumulator output. The control logic in Figure 3-1 ensures the alignment of the integer/fractional portion based on the carry output from the accumulator. A carry output of “1” from th e accumulator indicates an increment in the integer portion requiring an additional bit for its representation. The step value is logically shifted to the right by one bit with an inserti on of a “0” bit at the MS B location. Similarly the accumulator output is shifted to the right by one bit with an insertion of “1” bit at the MSB location. The LSB bit is discarded in the above set of operations to tr uncate the result to NL bits of precision. A barrel shifter is used to extract the integer portion of the accumulator output and a digital comparator is used to compare with 2CN. The above set of operations involved in the successive accumulation is explained with the sn apshot of the accumulator and input registers shown below. Considering an inductor voltage input of vL=5V and using the derived scaling factor of 33125/22/2SCN the step value can be determined to be 3 12 1025 5 2 8 5 2660,100001010 12/10232LstepvVqround (3-22) Let ACC[k] and qstep[k] represent the accumulator output and the step value at the “kth” clock instant. A snapshot of the sequence of oper ations occurring in the accumulator is indicated below.

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43 10210 210 210 210 22660,1000010100.51953 [1]0,1000010100.51953 [1]0,1000010100.51953 + [2]1,0000101001.0390625 [2]0,1000010100.step step stepq ACC q ACC q 10 210 210 2 251953 + [3]1,1000111101.55859 [3]0,1000010100.51953 + [4]0,000101000 and CY=1 [4]10,00010100 2.0781stepACC q ACC ACC 10 21025 [4]00,10000101 0.51953stepq The ACC[4+] and qstep[4+] indicate the accumulator output and step values that are modified to account for the carry generated at k=4 clock instant. The timing error due to the various quantizati ons can be modeled as the increase in the quantized amplitude produced at the A/D output. The difference in time duration ( tDigital_diff) from the theoretical expression is indicated in Figur e 3-6. The change in the quantized amplitude of the inductor voltage can be m odeled by the following equation. __ _Lquantamphardware theoreticalDigitaldiffK v tt (3-23) The resulting amplitude modeli ng the quantization error can be determined from Equations 3-6, 3-7 and 3-8. The digital ti ming expression including the vari ous truncation and quantization errors is indicated in Eq. 3-24.

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44 __2CN D igitalhardwareCLK SChardwareLbinhardwarett Nv (3-24) where Lbinhardwarevn for which the amplitude __ Lquantamphardwarev satisfies Eq. 3-6. The MATLAB function modeling the quanti zation is given in Appendix A. 3.2 Architecture of Digital Synthetic Ripple Modulator In conventional PWM control, the output variable is regu lated by comparing a modulating function with that of a carrier signal. The co mparison process effectively modulates the time duration of a pulse controlling th e on/off position of a switch which in turn determines the duty ratio. In synthetic ripple modul ation, the carrier signa l utilized in the comparison process is derived from a system parameter unlike the tradit ional approach of using external oscillators. The modulation strategy is based on bonding the e rror between the controlled variable and a command variable to a synthe tic ripple derived by filtering a ny ac waveform of the system. The combination of the error and the synthetic ripple forms the carrier signal (modulator output) which is bounded between hystereti c limits. The hysteretic limits dictate the on/off time duration of the switches in the system. S ynthetic ripple modulation also al lows open-loop linear control of an output variable with refere nce to a command input. Since the modulation scheme derives the carrier signal from the system parameter, it enables natural feed-forward control. This modulation scheme when applied to the control of DC-DC converter or DC-AC inverters, the output voltage of a voltage regulat or or the rotor speed in a moto r drive can be controlled. In such applications the on/off-time or the duty ratio of the power MO SFET switches can be inversely related to a control voltage input as given in Eq. 3-1 or Eq. 3-2. Thus, the above mentioned digital timing generator can be us ed for generating the duty ratio. The generic architecture of a digita l synthetic ripple modulator contro lling a desired output variable in a system is illustrated in Figure 3-7.

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45 As indicated in Figure 3-7, the system parame ter related to the duty ratio is sampled and given as input to the digital ti ming generator. The digital timi ng generator scales the sampled input and generates the step value. The step value is successively accumulated between the hysteretic limits and the required duty ratio is ge nerated. The PWM output is set to logic high or “1” when the modulator output exce eds the upper hysteretic threshold (12CN). The PWM output is set to logic low or “0” when the modulator out put is lesser than the lo wer hysteretic threshold (12CN ). 1 1 1 2 0 2C CN NModulatorOutput PWM ModulatorOutput (3-25) The PWM signal is retained in logic 1 or logi c 0 when the modulator output is outside the hysteresis band. The PWM signal is set to the a ppropriate logic level once the modulator output is within the hysteresis band based on E q. 3-25 and normal SRM operation is resumed. The generic expression modeli ng the synthetic ripple modulat or in the analog domain is given in Eq. 3-26. ModulatorOutputAnalogOutputVariableSyntheticRipple (3-26) The modulator output forming th e carrier signal is modulated between the hysteretic limits given as 2 2 M odulatorCommandvariableHys M odulatorCommandvariableHys (3-27) where M odulator and M odulator are the higher and lower hys teretic thresholds in the analog domain and Hys indicates the hysteresis band. The schematic representation of Equations 3-26 and 3-27 is shown in Figure 3-8. The subtraction of the command vari able from the modulator output expression of Eq. 3-26 modifies

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46 the hysteretic thresholds to (+Hys/2) and (-Hys/2 ). The modulator output expression is changed accordingly as ModulatorOutputAnalogCommandOutputCommand SyntheticRipple (3-28) In the digital SRM implementation, the error resulting from the difference between the command variable and the output variable is sampled by an A/ D converter. The sampled error value ( Error_binary ) indicated in Figure 3-7 and the synt hetic ripple information from integer value of the accumulator are used in the formul ation of digital SRM m odulator expression. The digital SRM modulator output is given as M odulatorOutputErrorbinaryIntegerValue (3-29) In the digital SRM, the sampling of the error value between th e command and output variable instead of the actual output variable pr ovides the benefit of a llocating higher number of bits for the error. It also offers the benefit of c ontrolling the output variab le with better precision. The dynamics of the SRM is also enhanced by the fact that when the sampled value of the error between output and command variable exceeds its higher or lower quantiza tion levels [saturation limits of the A/D (e.g. 0 or 255 with 8 bits of pr ecision)], the PWM signal can be immediately set to logic “1” or logic “0” depending on the sa turation limits. The subtraction of the command variable from Eq. 3-26 as explai ned earlier modifies the digita l SRM hysteretic thresholds as 12CN and12CN with the “Hys” level in analog SRM mapped to 2CN in the digital SRM. The integer value from the accumulator spans from 0 to 2CN during both the on-time and offtime durations. Thus, to account for the m odified hysteretic thresholds, the terms 12CN and 12CN are added to the digital SRM modulator expression dur ing the off-time and on-time

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47 duration respectively. This ensures that w ith the integer value spanning from 0 to2CN, the modulator output is al ways modulated with a hysteretic level of2CN. The resulting digital SRM modulator expression is given in Eq. 3-30. 1 1 2 [] [] ;0 2 [] [] ;1C CN NErrorbinarynIntegerValuenPWM ModulatorOutput ErrorbinarynIntegerValuenPWM (3-30) In the expression describing the digital SRM modulator, Error_binary[n] indicates the sampled error voltage of the output A/D and Integer Value[n] is the integer output extracted from the accumulator at tCLK instant “n”. Considering the modulator expression Eq. 3-30, Error_binary is negative when the output voltage is above Vcmd. Thus when PWM =1, the higher hysteretic threshold will be attained earlier and Integer Value will span to less than 2CN resulting in reduced on-time. Similarly when Vout is less than Vcmd, Error_binary is positive causing Integer Value to span to 2CN, resulting in increased ontime. Similar argument can be applied for the factor of 12_CNErrorbinary during PWM=0. A low-pass fi ltering effect similar to integration is obtained in the digital timing generator’s accumulator during floating point addition by discarding the least significant bits. Thus the Integer Value[n] qualitatively represents the low-pass fi ltered output of the sample d converter parameter. 3.3 Application Illustration of the Digital Synthetic Ripple Modulator The DSRM architecture is illustrated belo w with reference to an application. The modulation strategy is used in the output voltage contro l of a synchronous buck DC-DC converter. The architecture of th e digital SRM controlled synchr onous buck DC-DC converter is shown in Figure 3-9. The specifications of the DC-DC converter are out lined in Table 3-2. The DC-DC buck converter controll ed by the digital SRM operates in three distin ct modes.

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48 Mode 1: When the error betw een the output voltage (contro lled variable) and command voltage exceeds the upper hysteretic limit 12CN, the VPWM signal is set to logic “0” or the UFET switch is turned OFF. The switch is retained in this position until the error reduces to within the hysteretic band. Mode 2: When the error is within the hysteretic band, the digital synthetic ripple modulator controls the converter output voltage. Mode 3: When the error falls below the lower hysteretic limit 12CN the VPWM signal is set to high or the UFET switch is turned ON. The switch is retained in this position until the error returns to the hysteretic band. The digital SRM employs hystere tic mode of control with sw itching frequency variations, the on-time and off-time of the high-side MOSFET (UFET) is given in Eq. 3-17 and repeated here for clarity ; ONOFFLL ONOFF LTLT I LIL tt vv (3-31) where L I is the peak-to-peak inductor current ripple under steady-state conditions, vLTon and vLToff are the inductor volta ges during the on-time and off-time respectively. From this the duty ratio can be derived as ON ONOFFt d tt (3-32) From Eq. 3-31 it can be inferred that the on/o ff time duration can be generated using the digital timing generator with the inductor voltage as the system input parameter for the DSRM. The output voltage of the synchronous buck converte r is the variable to be controlled by the digital SRM. The output voltage of the buck converter is related to the generated duty ratio as given in Eq. 3-33. The output voltage is cont rolled by modulating the duty ratio of the DC-DC buck converter. ()()()outinvtdtvt (3-33)

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49 The design of the complete system involves th e design of L-C output f ilter and the digital SRM controller. 3.3.1 Design of Buck Converter-Output LC filter The buck converter is designed w ith an input voltage of 5V a nd an output voltage of 1.5 V. The L-C filter design assumes a switch ing frequency for the converter to be 1 300 S S f kHz T The converter output current is assumed to have a nominal value of 4 A. Using steady-state analysis for a buck converter, 4 Lout I IA The peak-peak inductor current ripple, 16%()0.64LhysL I IIA _min1.5 outnoalVV _min5 innoalVV 0.375 LoadR 10Lrm (3-34) The steady-state duty ratio based on the aver aged PWM-switch model [57] can be derived from Eq. 3-35. diode in L Load Load outV D DV r R R V (3-35) Thus, the steady-state duty ratio can be determined to be D=0.39. The design of the output filter parameters is based on current ripple requirements and transient regulation requirements The output filter inductor is determined from the inductor current ripple [58]. (1)outS hysVDT L I (3-36) 61.5(10.39)3.3310 4.76 0.64LH (3-37) The design of output filter capacitor is based on transien t and output voltage ripple requirements. Considering the change in the indu ctor current for a buck converter during a load

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50 step-up and step–down transient as shown in Figure 3-10, the inductor current slope can be derived. : During step-up transientinout Lvv di dtL (3-38) : During step-down transientout Lv di dtL (3-39) From Equations 3-38 and 3-39 it can be conc luded that the out put-voltage overshoot during a load-step down transient sets the limit on the transient performance of the converter [58]. In order to keep the output voltage outV within regulation range outV during a loadtransient ofmax outI the minimum required output filter capacitance [58] can be obtained as 2 max min11 2o F outoutoutI L C VVdidt (3-40) For a voltage deviation of 60outVmV and max4o I A the minimum output capacitance is determined. min415 CF (3-41) 3.3.2 Design of Digital Synthetic Ripple Modulator The digital SRM controller involves the de sign of digital timing generator and the resolution of the output va riable A/D converter. 3.3.2.1 Digital timing generator The design of the digital timing generator i nvolves the determination of key parameters, namely the input clock frequency ( fCLK), count resolution ( NC), scaling factor ( NSC) and the stepvalue resolution ( NL). The resolution for the A/D converter is assumed to be NL =8 bits. The count resolution can be determined from Eq. 3-14.

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51 max 2 L LC hysV NNlog V (3-42) maxmax15%5.25 LininVVVV (3-43) Assuming _320 >> 60 hysoutrippleVmVvmV 25.25 ; 320 320 LChysNNlogVmV mV (3-44) 25.25 320 LCNNlog mV (3-45) 4 8 4LCLCNNNN (3-46) By comparing Equations 3-2 and 3-18 the parameter K can be determined to be 60.644.763.04610LKILAH (3-47) In a buck converter the maximum voltage acros s the inductor can o ccur during startup or during an output short circuit. The inductor voltage under these conditions can be derived using Table 3-2 to be LinoutvVv (3-48) maxmax 05.25 outLin VVVV (3-49) The minimum time period of the clock re quired to guarantee minimum time duration accuracy as determined from Eq. 3-15. 6 4 max3.04610 36.26 225.25CCLK N LK tns V (3-50) The experimental implementation of the di gital timing generator utilizes the onboard oscillator from the ALTERA UP2 board [59]. The time period of the clock used for the digital timing generator

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52 _1 25.175 39.72 OSCALTERACLK OSCALTERA f MHztns f (3-51) The scaling factor can be dete rmined from Eq. 3-19 to be 4 8 93 65.25 2 2 21 39.72104.295510 3.04610CN Lq SCCLKv Nt K (3-52) Due to restricted availability of the hardware resources, values of NL=8 and NC=4 results in percentage timing error less than 8%. The buck converter applicati on can tolerate this percentage of timing error due to the delays involved in gate driver and the power MOSFETs. As discussed earlier the experi mental implementation utilizes A/D gain block scaling to minimize the error parameter. The scaling factor of Eq. 3-52 can be approximated based on the conditions stated in Equations 3-20 and 3-21. 4 1111992 2162SCN (3-53) In the above scaling factor, the ratio (9/16) is incorporated into A/D gain and the ratio (24/211) is used to interpret the A/D output as being binary shifted to the left by 4 bits followed by a binary shift to the right by 11 bits. This eff ectively provides a binary shift to the right by 7 bits. Hence, the 8 bit A/D output is construed as a floating point bi nary number with 1 bit for the integer portion and 7 bits for the fractional portion. The approximation of the scaling factor indica ted in Eq. 3-53 also influences the timing accuracy between the theoretical and the digital timing generation approach. The possible scaling factors which closely approximate the estimated va lue are indicated in Table 3-3. Similarly the binary shifting ratios determining the initial bi nary point location for the step value are also indicated in Table 3-3. The optimum approxima tion for the scaling fact or can be deduced by evaluating the timing error performance metric as indicated in Figure 3-11 The final count value

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53 to which the respective step values are accumula ted in each case is modified to reduce the percentage timing error. The plot of Figure 3-11 indicate that timing errors less than 6% can be obtained for the parameter error with NSC=(9/211), thereby yielding the factor for the experimental implementation. 3.3.2.2 Output volt age A/D resolution The output voltage of the buck converter during the interval when the upper MOSFET (UFET) is ON is given to be outinLvvv (3-54) outinLvvv (3-55) If the input voltage of th e buck converter is assumed to be a constant value outLvv (3-56) The above equation can be inte rpreted in the digital domain to be the change in output voltage caused by a single LSB change in the in ductor voltage. The above equation can be used to derive the limit-cycle oscillat ion constraint [6] [56]. The duty ratio change caused by a single LSB change in the inductor voltage must be less than the output error-voltage A/D LSB change. The error between the out put voltage and the command voltage is given by errorcmdoutvvv (3-57) The maximum value of the error voltage can be determined based on the dynamic response requirement. Considering the modulator expr ession of Eq. 3-30 the maximum value of Error_binary determines how fast the modulator reacts to a transient condition (load step-up or step-down). The error voltage between the command and the output voltage is sampled based on the A/D transfer characteristic shown in Figure 312. Under a load step-up or step-down transient condition, the maximum va lue for the A/D output (Error_binary ) in either direction is 21EN

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54 or2EN The magnitude of this maximum valu e should be such that the term 12_CN E rrorbinary in Eq. 3-30 attains the higher or lowe r hysteretic threshold to trigger the PWM comparator. Thus, the maximum allo wable error voltage is given to be max errhysVV (3-58) Using Vhys value of Eq. 3-44 in Eq. 3-58 max 320 errVmV (3-59) The LSB of the inducto r voltage is given as max2LL Lq NV v and the LSB of the error voltage is given to be max2Eerr errq NV v Lqerrqvv (3-60) maxmax22LELerr NNVV (3-61) max 2 max intlogL LE errV NN V (3-62) where maxLVis the maximum inductor voltage, NE is the resolution of the output error voltage A/D converter and NL is the number of bits used for the step value in the digital timing generator. Hence in a digital synthetic ripple modulator, to avoid limitcycle oscillation, the above conditions need to be satisfied. The above equations when applied to buck converter specifications from Table 3-2 w ould yield the following results. 525 and V320 LmaxerrmaxV.VmV (3-63) 4LENN (3-64)

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55 The number of bits required for the output e rror voltage A/D is determined from static regulation requirements. The error voltage resolution must be great er than that of the inductor voltage resolution to ensure that the change in output voltage is tracked by the digital timing generator. Thus, the number of b its to be allocated for the error voltage A/D converter in order to provide a resolution of verrq=30 mV ( 20.588 errqLqvvmV ) is determined to be max 2intlog 30 err Ev N mV (3-65) 4EN (3-66) Using Equations 3-64 and 3-66, the NL can be determined to be NL = 8. 3.4 Modeling and Simulation of Digital SRM Based Buck Converter The buck converter controlled by the Digita l Synthetic Ripple m odulator involves both digital and analog blocks, whic h are modeled using MATLAB a nd Simulink [58] [60-62]. The choice of MATLAB/Simulink allows easier system -level implementation of the digital SRM, integrating the continuous-time output filter, sw itching PWM action, and the digital controller. The buck converter shown in Figure 3-7 comprise s of three major components namely the PWM switch, the output L-C filter, and the digital SRM controller. The modeling of each of these components is explained in the following sections. 3.4.1 Modeling of PWM Switch For a Buck converter, based on the PWM gate driv e, the input to the LC filter is either the input voltage (Vin) or the voltage drop across the sync hronous rectifier (cat ch diode voltage (Vdiode) can be used if a catch diode is used inst ead of the synchronous re ctifier) neglecting the drop across the UFET MOSFET. Hence the converter is modeled as a switch driving the output filter, with the switch outputs decided based on PWM signal (Vin when switch is ON and Vsync_rect

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56 when switch is OFF). The on-time and off-time of the PWM switch is determined from the timing signal VPWM, the output of the digital SR M controller. The Simulink model is indicated in Figure 3-13. 3.4.2 Modeling of Output LC filter The output LC filter network with input voltagephasev, input current Li and output voltage outv is described by the following set of equations. in phaseoutLLdi Lvvir dt (3-67) c Loutdv Cii dt (3-68) ()outCCLoutvvrii (3-69) where Cr and Lrare the equivalent series resistance of the output capacitor and DC resistance of the inductor respectively. The above set of equations is incorporat ed into the Simulink model of the Buck filter shown in Figure 3-14. 3.4.3 Modeling of Digital SRM Controller The modeling of the digital SRM controller involves the A/D converter modeling, digital timing generator modeling. It also includes the generation of the modulator output which combines the output error voltage and the digital timing generator output. The A/D converter or the quanti zer model [61-65] is based on the LSB equivalent of the A/D converter. The A/D converter model is shown in Figure 3-15. The zero order hold is used for sampling, the quantizer is used for rounding to the nearest integer, and the saturation block limits the lower and higher digital output levels as specified. The A/D gain used for sampling the inducto r voltage is based on the scaling factor.

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57 8() 119 / 27.32 5.25 216 21Bsc N LqNumN ADGain v (3-70) where Lqv is the LSB equivalent of the inductor voltage, max21LL Lq Nv v The lower and higher digital output levels of i nductor voltage A/D are 0 and 255. The A/D gain used in the sampling of th e error voltage between output voltage and command reference is given as max121 / 16.756EN errqerrADGain vv (3-71) The lower and higher digital output levels of the error voltage A/D are -16 and +15 based on whether the output voltage is higher or lesser than the command voltage. The digital timing generator as described earl ier utilizes the sampled inductor voltage to generate the on-time/off-time. The timing generato r is modeled with Level 2 M-file S function utility in Simulink [66]. The bl ock accepts the sampled inductor voltage, timing generator enable signal and the initial bina ry point location. The accumulated value, integer value, the current step value, and the carry output are fed back as inputs to the timing generator block. The carry output indicates the number of bits cu rrently used for the integer portion of the accumulator output. The Simulink model is indicated in Figure 3-16. The modulator output is derive d from the generic architectur e expression of Eq. 3-30, +8 VerrAD[n] Integer_val[n] ; PWM=0 mod_op = -8 VerrAD[n] + Integer_val[n] ; PWM=1 (3-72) The system implementation of the synchronous buck converter controlled by the digital SRM modeled in MATLAB/Simulink is shown in Figure 3-17. The buck converter waveforms are depicted in Figure 3-18. The waveforms indicate the inductor voltage ( vL), inductor current ( iL), output voltage ( vout) and the phase voltage ( vphase) for

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58 a command input of vcmd=1.3 V. As seen from the waveforms, the inductor voltage during the UFET on-time is 3.66 ONLTvV and that during the off-time is 1.54 OFFLTvV The output voltage under the steady-state conditi on can be determined to be 1.34 outvV The on-time and off-time duration corresponding to th ese voltages based on the theoretical expression of Eq. 3-17 are 1.027s and 2.44s. The step value for accu mulation, the accumulator output, and the PWM signal are indicated in Figure 3-19. The on-time and off-time duration from the simulation waveforms can be determined to be 1.1 s and 2.6 s. The parameter error can be determined to be less than 7% when comparing the generated time duration with that of the theore tical expression. The step value obtained in the waveforms during the on-time and off-time can be derived as given in Equations 3-73 and 3-74. 102 89 3.66 16 1000,11001000.78125 5.25 21LONSTEPVALvround (3-73) 102 89 1.54 16 420,01010100.328 5.25 21LOFFSTEPVALvround (3-74) The actual step values without A/D gain bl ock scaling while based on multiplication can be determined to be 10 83.66 / 178 5.25 21ADoutputround (3-75) 3 __ 101784.2955100.7645LONSTEPVALMULTv (3-76)

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59 10 81.54 / 75 5.25 21 ADoutputround (3-77) 3 __ 10754.2955100.322LOFFSTEPVALMULTv (3-78) By comparing Equations 3-73 and 3-74 with Eq uations 3-76 and 3-78 respectively, it is evident that the A/D scaling closely a pproximates the required step value. The time duration generated using the digita l timing generator is compared with the theoretical expressi on and plotted in Figure 320. The percentage error is compared in Figure 321. 3.4.4 Simulation of Adaptive Voltage Positi on for Digital SRM based Buck Converter Adaptive voltage position (AVP) is an essent ial function of low-voltage VRM designs. The AVP concept utilizes the entire voltage tolerance window during a step-down or step-up load transient [67]. In AVP, the output vo ltage is positioned at a voltage level slightly higher than the minimum value (Vout_min) at full load. Similarly the output voltage is posi tioned at a voltage level slightly lower than the maximum value (Vout_max) under light load conditions. The AVP design was simulated in MATLAB/Simulink and needs to be experimentally verified in future. The AVP specs are Vin=5 V, Vout=1.55 V, and Iout=5 A. The step-down load transient is considered with a load current slew rate of 50 A/s. The maximum load current change is specified as 5 out I A and the assumed Rdroop=16 m The output voltage change under a stepdown transient is illustrated in Figure 3-22 indica ting the inductor current load current, capacitor current and the allowed voltage tolerance window For AVP, it is evident from Figure 3-22 that the output voltage resonates to the maximum value when the load current reaches zero. This is due to the fact that once the load current is zero, the inductor current flows into the output

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60 capacitor to charge it to Vout_max. In the digital SRM, the AVP can be easily implemented by turning off the UFET during the step-down load transient and turning on the UFET once the inductor current reaches zero. The required voltage tolerance wi ndow can be determined as, max_51620100 outrequiredoutdrooptoleranceVIRVAmmVmV (3-79) The L and C are designed such that the output voltage resonates within the tolerance window. The inductor design is based on the ripple spec and given to be 1 1LToffS outS LLvDT VDT L II (3-80) 1.55;/1.55/50.31;0.4;600 outoutinLSVVDVVIAfkHz 1.551 4.7 S LDT LH I (3-81) During the load-step transient the output vol tage change occurring across the capacitor is given by __max_ outCoutoutESRVVV (3-82) where Vout_ESR is the change in Vout due to th e ESR of the output capacitor (C) and Vout_C is the voltage change across the capacito r due to the load current change of Iout. __max_100(55)75 outCoutoutVVIesrCmVAmmV (3-83) The charging time for the output capacitor can be determined from the load current change and the slope of the inductor current during off-time for a buck converter. The AVP design utilizes a load step of 5A at a slew rate of 50 A/s. Thus Iout=5 A. out LToffbuckout CHG I vVL t (3-84) 4.75 15.1612 1.55out CHG outLI HA ts V (3-85)

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61 Thus, the net charge in the capacitor due to the load current change is given as 1 2CHGoutQtI (3-86) The capacitor value can be determined from Equations 3-83 and 3-86 as 22 _54.7 11 400 221.5595out outCtolerance outoutCtoleranceIL Q CF VVmV VVV (3-87) The capacitor used is 425F. The capacitor current is shown in Figure 3-22 and can be derived as ()out Cout CHGI itIt t (3-88) 1 ()()_() OUTCCvtitesrCit C (3-89) At the instant when Vout peaks, dVout/dt=0. Thus, the instant at which Vout peaks can be determined from Equations 3-88 and 3-89. __15.1612542513.0362 VoutpeakCHGttesrCCsmFs (3-90) Using the time duration determined from Equa tion 3-90, the slew rate for the command signal can be determined as shown in Equation 3-91. _max _100 __7.67 13.0362out cmd VoutpeakV mV SlewratevmVs ts (3-91) The UFET need to be turned on after 13.0362 s based on the time duration from Eq. 3.90. This can be accomplished by modifying th e original hysteretic count of 216CN under the load transient condition. The change in the hysteretic count to turn on the UFET at the instant when Vout peaks is determined from Eq. 3-96. The inverse timing generator expression in the digital SRM timing is given as

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62 2CN CLK Digital STEPt t q (3-92) Under the step-down load transi ent condition, the voltage across the inductor is the output voltage, 1.55 LToffoutvVV The step value used for the successive accumulation under the given load condition is given to be 11.55/5.25/255 0.588160.6 2128Lout Lq STEP NV v q (3-93) Hence to turn on the MOSFET after the time duration determined from Eq. 3-90, the modification in the hysteretic count can be determined as CLK Vout_peak STEPHys_Countt =t q (3-94) 13.03620.6 Hys_Count196 ; 40 40CLKs tns ns (3-95) Thus, the increment in the hysteretic count is determined to be CNHys_count196 Modified Hysteretic count===13 216 (3-96) In the digital SRM implementati on the hysteretic count of 216CN is carried out for 13 additional cycles to determine the turn on in stant of the UFET. A counter increments the modified hysteretic count each tim e the digital timing generator output, namely, Integer_value, reaches 216CN. The error voltage between the comm and signal and the output voltage is sampled by an A/D converter with NE=4 bits of precision and one additional bit for sign representation (error voltage (+ ve) when Vcmd>Vout and (-ve) when Vout > Vcmd ). The maximum error voltage is determined from Eq 3-59. The error voltage A/D resolution is sufficient enough to track the outpu t voltage change under the load transient. The error_binary

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63 signal can have oscillations due to the output voltage not exactly coinciding with the peaking of the command signal (caused due to overshoot or unde rshoot). Because of the flexibility of digital control, the digital SRM compares the current erro r_binary signal to a rang e of error_binary (+1, 0, -1) values based on the e rror voltage re solution of verrq=30 mV. Thus to determine the turn on instant of the UFET, the modulator compares the modified hyste retic count to th e required value of 13 and also compares the error_binary signal to the allowed digital to lerance band. When the required hysteretic count and the range of error values coincide, the UFET is turned on. The simulation outputs for the modified hysteretic count based AVP implementation of the digital SRM is shown in Figure 3-23 and Figure 3-24. In Figure 3-23, the inverse timing generator output (integer_value), the modifi ed hysteretic count, and the erro r_binary signal are shown. As evident from Figure 3-23, integer_ value spans to the count of 32 for 6 cycles and an additional count of 16 resulting in 13 cycles of the original hys teretic count (216CN ). From the figure it is also evident that the error_bina ry signal at the vicinity of turning on the UFET lies within the allowed digital tolerance band. In Figure 3-24, the output voltage, induc tor current, modulator output and the command signal ar e indicated. The overshoot evid ent in the output voltage is within the allowed tolerance band of 20 mV. Th e modified hysteretic c ount changes the lower hysteretic threshold as -208 (213CN ). The resulting modulator output is also indicated in Figure 3-24. The inductor current, output voltage, modulat or output are indicated in Figure 3-25 for a load step-up condition. A load current step of 5 A is used and the resulting AVP of the output voltage is indicated. Similar to a load-ste p down transient the hysteretic count is modified to 208 (=16X13) during the load transient. The upper MOSFET is turned off when the modified hysteretic count is reached and when the error_ binary signal is within the tolerance band.

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64 In the transient AVP design methodology for digital SRM, three difference cases are considered for ramping up the command signal. The three cases are outlined below: Case 1: The command signal is ramped up once the UFET is turned “OFF” and the slew rate is designed such that the peaking of out put voltage coincides with the higher level of Vcmd (Vout_max). This is the optimum case of transient AVP design. Since Vcmd exactly coincides with the peaking of output voltage, by virtue of SR M the output voltage follows Vcmd without any overshoot or undershoots. The command signal is ramp ed up with a slew rate of 6.59mV/s. The AVP of the output voltage is indicated in Figure 3-26. Case 2: The command signal is ramped up once the UFET is turned “OFF” and the slew rate is designed such that Vcmd reaches Vout_m ax before the peaking of output voltage. In this case the output voltage slightly overshoots a nd the follows Vcmd. The command signal is ramped up with a slew rate of 11.9mV/s. Th e AVP of the output vol tage, inductor current, modulator output, VPWM, and Error _binary for this case are indi cated in Figure 3-27 and Figure 3-28. Case 3: The command signal is ramped up once the UFET is turned “OFF” and the slew rate is designed such that Vcmd reaches Vout _max after the peaking of the output voltage. In this case the output voltage slig htly undershoots due to the fact that it tries to follow Vcmd. The command signal is ramped up with a slew rate of 5.43 mV/s. The AVP of the output voltage, inductor current, modulator output, VPWM, and E rror_binary for this case are indicated in Figure 3-29 and Figure 3-30. The slew rate of the command signal in each of the above cases is designed to be less than the modulator output slew rate. The determination of modulator output slew rate is shown below mod2 165.25/255 658 500 CN Lq ONv dV mVs dttns (3-97)

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65 Since the on-time modulator output has a stee per slope when compared to off-time the ontime slope was used above. The digital SRM provi des the significant advantage of programmable slew rate for the modulator to meet the requi red transient and steadystate specifications. 3.4.5 Modeling of Dynamics involved in th e Digital SRM Controller for a Buck Converter The dynamics involved in the digital SRM can be obtained from the command to duty ratio and duty ratio to output voltage transfer functions. The dynamic system model of the digital SRM is indicated in Figure 3-31. The duty ratio to output transfer function can be obtained from converter system dynamics [31]. The command to output voltage transfer function can be obtained by deriving the command to duty ratio transfer function. The command to output voltage transfer function is thus given to be ^^ ^ ^^^outout cmdcmdvv d vdv (3-98) From the digital SRM modulator expression of Eq. 3-30, the Error_binary and Integer value can be derived based on Equations 3-5, 3-6, 3-7, 3-8, and 3-9. _errorEcmdoutEerrErrorbinaryvGvvGN (3-99) LSCL I ntegerValuevNG (3-100) where GL and GE are the describing function of the A/D quantizer based on Eq. 3-6 for sampling the inductor voltage and e rror voltage re spectively. Thus the A/D converter model for samp ling the inductor voltage is given by 1() s t LNLGGAe 3-101) The e-st1 term models the phase delay due to the sampling process. The delay t1 is given as 1 2ST tProcessingdelays (3-102) where TS is the switching frequency and processi ng delays are on the order of 40-50 ns.

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66 Similarly the A/D converter for th e error voltage is modeled as 22() : 2st S ENET GGAetProcessingdelays (3-103) The on-time of the power MOSFET switch in a buck converter whose output voltage is controlled by the digital SRM can be derived using Equations 3-17 and 3-29 as, 2CN errCLK hyserrorCLK on SCLTonLinoutSCLNt vvt t NvGvvNG (3-104) Similarly the off-time of the pow er MOSFET can be derived as 2CN errCLK hyserrorCLK off outSCL SCLToffLNt vvt t vNG NvG (3-105) The resulting duty ratio is given by Eq. 3-31 and can be derived as 2hyserroroutSCL on onoff errorinSCLoutSCLhysinSCLvvvNG t d tt vvNGvNGvvNG (3-106) The time varying duty ratio can be given as the sum of the DC operating point (quiescent point) and the small signal ac component. ^^^ ^ ^^^2hyscmdcmdoutoutoutoutSCL cmdcmdoutoutinSCLoutoutSCL hysinSCLVVvVvVvNG Dd VvVvVNGVvNG VVNG (3-107) By cross-multiplying and grouping similar terms the following relation can be determined. The non-linear terms involving the multiplica tion of 2 ac quantities are neglected.

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67 ^ ^ ^2 2 2hysinLinLcmdoutEoutLcmdoutE outcmdEinLhysL cmdoutEoutLout outLinLoutLcmdVVGVGVVGVGVVGd DVVGDVGVG VVGVGv DVGDVGVGv (3-108) The duty ratio to output tran sfer function is given as ^ ^21 () ; ; ; 1outdoout vddoo oovGV C GsGQR DL LC ss d Q (3-109) The above expression can be modified as ^ 2 0 ^ 2 22 0()outdo vd ovG Gd Gs sVsW d ss Q (3-110) where 2 0W 2 0 doGdG and 0V Q Using Eq. 3-110 in 3-108, the command to duty ratio transfer can be derived as ^ ^21 2 ()()24() ()()outLinL hysinLinLcmdoutEoutLcmdoutE cmd vdinLvdcmdoutEvdhysL vdcmdoutEvdoutLDVGDVG d VVGVGVVGVGVVG v GsDVGGsDVVGGsVG GsVVGGsVG (3-111) Defining the terms in the numerato r and denominator of Eq. 3-103 as

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68 21 2 ()()2 -()()(outLinL hysinL inLcmdoutEoutLcmdoutE vdinLvdoutcmdE vdhysLvdcmdoutEvdNumADVGDVG DenAVVG DenBVGVVGVGVVG DenCGsDVGGsDVVG GsVGGsVVGG )outLsVG (3-112) ^ 2 ^ 2222 2SW SWSWSWSWT s TTTT ssss cmddNume Gd v DenAeDenBeeDenCe sVsW (3-113) Using the first order Pad approximation for 1 s te in Equations 3-93 and 3-95, 111/4 ; 1/42SW st S SW SWsT T etdelaysT sT (3-114) Thus, the command to duty ratio transfer f unction can be obtained with numerator and denominator coefficients in the “s” domain as 32 ^ ^ 3 21 SWSWSW SWSW cmd SWSWNumATsNumAVTsNumAVWTs NumAW d DenATDenBTs v DenADenBDenAVTDenBVTs DenAVDenBVD SWSWSWenAWTDenBWTDenCGdTs DenAWDenBWDenCGd (3-115) The digital SRM controlled buc k converter is simulated in MATLAB/Simulink and the steady-state parameters were derived from th e converter outputs. The inputs to digital SRM controlled converter are Vin=5 V, Vcmd=1.3 V, and Rload=0.5 The parameters of the digital timing generator used in simulation are NC=4, NL=8, tCLK=40 ns, NE=5, and TS=3.33 s. The MATLAB function used to determine the coefficien ts of the command to dut y ratio expression is

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69 given in Appendix A. The steady-state outputs determined from the simulation are D=0.27 and Vout=1.34 V. The resulting command to duty ratio expression based on Eq. 3-115 is given as ^ 63249 ^ 6324103.27101.9972.312102.0910 2.255101.9524.225101.4410cmddsss sss v (3-116) The above expression can be expressed in the pole-zero gain form as ^ 5249 ^ 52491.45046.006101101.06410 8.525101.319107.49110cmdsss d sss v (3-117) The magnitude and phase of the command to duty ratio transfer f unction, duty ratio to output transfer function, and comm and to output voltage transfer function are plotted in Figures 3-32, 3-33, and 3-34 respectively. These functions need to be verified experimentally. 3.4.6 Design Methodology for Digital SRM Cont rolling the Synchronous Buck Converter A summary of the design me thodology involved in the de sign of the digital SRM controlling the buck converter is outlined in this section. The digital SRM design process assumes that the parameters of the buck convert er, namely, output filter inductor (L=4.7 H), output capacitor (C=425 F ), input voltage (Vin=5 V; +5%/-8%), output voltage (Vout=1.5 V), and peak-peak inductor ripple current ( IL=0.65 A) are known beforehan d. The next step of the design process involves determinatio n of the parameters in the di gital inverse timing generator. The number of bits fo r the step value (NL) and the hysteretic count resolution (NC) are determined from the maximum inductor voltage (VLmax=5.25 V) and the hysteretic voltage (Vhys=320 mV) selected. The equation relating NL and NC is given from Eq. 3-14 as max 2 L LC hysV NNlog V (3-118) 4LCNN (3-119)

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70 Based on an initial assumption of NL=8 for the inductor voltage resolution, the hysteretic count resolution is determ ined from Eq. 3-118 as NC=4. The time period of the clock (tCLK=(1/fCLK)) required for successive accumulation and timing generation is then determined. __ max1 36.26 ;27.58 2CL CLKrequiredCLKrequired N LCLKLI tnsfMHz Vt (3-120) Based on the availability of resources, the cl ock used in the experimental implementation is fCLK=25.175 MHz (tCLK=39.72 ns). The next step involves the determination of the scaling factor based on parameters determined above. 32 4.295510CN Lq SCCLK Lv Nt LI (3-121) The following step involves the approximation of the scaling factor based on Equations 320 and 3-21 to aid in binary operations. 4 1111992 2162SCN (3-122) _/9 16SCADN (3-123) The ratio NSC_A/D from Eq. 3-123 is incorporated in to the A/D signal conditioning circuit utilized for sampling the inductor voltage while the ratio (24/211) is utilized for virtual binary shifting in the step value ge neration. The final step of the design process involves the determination of number of bits for quantiz ing the error between the command and the output voltage. The inductor voltage and the error vo ltage resolution are re lated by the following equation. max 2 max intlogL LE errV NN V (3-124)

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71 The error voltage resolution and the maximum error voltage are based on transient requirements. Based on the modulator expressi on of Eq. 3-30, the maximum error voltage (Verrmax) is selected to be less than or equal to the hysteretic voltage (Vhys) for the PWM comparator to respond instantaneously under a step -up or step-down load transient. Thus, the relation between the number of b its for the inductor voltage and th e error voltage is obtained as 25.25 intlog 320 LEV NN mV (3-125) 4LENN (3-126) The LSB equivalent of the error voltage ( verrq=30 mV) is chosen to be greater than the LSB of the inductor voltage ( vLq=20.58 mV) resulting in max 2intlog4 30err EV N mV (3-127) The AVP requirement of Vout_min=1.5V and Vout_max=1.6V indicates a voltage change of 100 mV. Thus, the number of bits determined for the erro r voltage and its resolution ( verrq=30 mV) can track this voltage change under a tran sient load step-up or step-down condition and satisfy the transient AVP requirement. Based on the parameters determined, the timing generation accuracy is evaluated by comparing the time duration from digital timing generator with that of the theoretical expression as shown in Eq. 3-128. 2CN L CLK L L SC Lq error L LLI t v v N v LI v (3-128)

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72 In order to improve the timing generati on accuracy, the number of bits for NL can be increased or the time period of the clock (tCLK) used for accumulation can be reduced. The parameter determination procedure is re iterated to reflect the changes. 3.5 Performance Analysis of Di gital Synthetic Ripple Modulator 3.5.1 Open-loop Linear Control of Co ntrolled Variable with Command Signal The digital SRM allows open loop linear control of the output variable as stated earlier. The command signal cmdV is varied from 1.2 V to 1.8 V a nd the resulting output voltages are shown in Figure 3-35. It is evident from Figure 3-35 that the output voltage follows cmdV in a linear fashion even under open-loop conditions. The open-loop operation of the modulator results in an error voltage between the actua l output voltage and the command voltage. This arises from the fact that the term VerrAD in Eq 3-72 is not adequately compensated. Hence an offset results between the desired output voltage and the actual output voltage in the open-loop control of the converter. On the other-hand, th e open-loop control still provides a linear control of the output voltage with re spect to the command voltage. 3.5.2 Influence of Component Variatio ns on the Digital SRM Performance The digital SRM involving genera tion of carrier signal from converter waveforms allows natural feed-forward control. The SRM scheme also enables the carrier signal to better track the component variations. This is shown in Figure 3-36, which indicates the variation in output voltage for a command signal Vcmd=1.36 V due to variations in converter components values (e.g. L, C, esr_C, rL ) over aging. A variation of 15% is included in the output filter component values of the buck converter. The nominal induc tor value used in simulation is L=4.7 H ( Lmax_var = 1.15X4.7 H=5.4H and Lmin_var=0.85X4.7 H=3.99 H) and the nominal output capacitor value is 4.11 mF ( Cmax_var=4.73 mF and Cmin_var=3.87 mF ). As evident from Figure 3-

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73 36, the output voltage remains within an allowable tolerance level over the 4 combinations of component variations. 3.5.3 Open-loop Dynamic Response of th e Digital SRM Controlled Buck Converter The open-loop load transient re sponse of the digital SRM c ontrolled buck converter is indicated in Figure 3-37. A stepup load transient is presented to the buck converter with its command voltage held constant at Vcmd=1.5 V. As evident from the figure, the sudden change in load current is immediately suppl ied by the converter with the help of the digital SRM triggering the UFET VPWM signal to logic high or “1”. Also evident from the figure is the droop in the output voltage. The droop in the output voltage results in the increase of the error voltage between command and output volta ge. The increased error volta ge causes the A/D converter sampling the error voltage to saturate to the hi gher limit based on Figure 3-12. Thus the lower hysteretic threshold is reached in Eq. 3-25 instantaneously, causing the VPWM signal to go to logic high or “1”. The current implementation of the digital SRM is based on open-loop control with no regulation for the output vo ltage, causing a droop in the out put voltage for the given load transient. 3.6 Advantages of Digital Synthetic Ripple Modulator Digital Synthetic Ripple modul ator generates the carrier si gnal from converter parameter allowing for natural feed-forward characteristic. Li near control of the controlled variable can be obtained in open-loop configuratio n and transient performance is better because the controlled variable is directly bonded to synthetic ripple. The principle of digital SRM when applied to speed control of motor drives can eliminate the need for stator current sensing, while providing superior transient performance due to hysteretic operation.

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74 Table 3-1. Sequential steps invol ved in Step Value generation Parameter Binary Multiplication Scaling A/D Gain-block scaling 1 Analog Input 10.35 10.35 2 A/D Output ( NQ(V)) round(10.35/(12/1023)) =(882)10=(1101110010)2 round((10.35X5)/((12/1023)X8)) =(551)10=(1000100111)2 3 Scaled output (882X5)/212=(1,000100111)2 =1.0762 (551)X(23/212)=(1,000100111)2 =1.0762 4 Step Value qstep=(1,000100111)2 qstep=(1,000100111)2 Table 3-2. DC-DC converter specifications S.No Parameter Specification 1 Input Voltage 5V +5%,-8% 2 Output Voltage 1.1 – 1.85V 3 Output current slew rate 50A/s 4 Output current selected 4A 5 Output voltage resolution 30mV Table 3-3. Scaling factor Approximations Actual Scaling Factor 34.295510SCN NSC approximation Virtual binary point factor 1035/24.8810 23/210 1139/24.394510 24/211 1138/23.9062510 24/211

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75 s tepq ,,..LLDSqviV Scaling SCN L N ControlLogic Shiftenable L N L N Carry R egister DigitalComparator 2CN s tepq D igitaltCLKt 2CNOFFtONt A ccumulatorTiming Output CLK f B arrelShifter I ntegerValue 1CLK CLKf t / A D (,) QVIN Figure 3-1. Conceptual implementati on of digital duty ratio generation ONt ()Lit 1 L Tonv m L 2 L Toffv m L OFFt L I ()Lvtinoutvv outv (sec) t Figure 3-2. Inductor current indi cating the current ripple and time intervals along with the buck converter inductor voltage

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76 1 NLb0b1b2b VirtualDecimalPt F ractionalPortion s tepq (,..) qVI F ractionalPortionInteger portion SCN 1LSBq LN/ A D 1NLb 0b1b2b VirtualDecimalPt F ractionalPortion s tepq (,..) qVI F ractionalPortionInteger portion () 2BSC N LSBNumeratorN q LN/ A D LN 2 ()BN SCDenN / BinaryMultiplicationScalingADGainBlockScaling 1 2 3 4 1 2 3 Figure 3-3. Scaling approaches for step value generation 0 2 4 6 8 10 12 0 1 2 3 4 5 6 Control Input Voltage (V)Percentage error between digital timing generator and theoretical expression (%) NSC = 5/212 ; Count = 16 NSC = 9/213 ; Count = 14 NSC = 8/213 ; Count = 13 NL =10 ; tCLK = 40ns Figure 3-4. Timing error performance for various scaling factor approximations used in step value generation

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77 1 2 3 4 5 6 7 8 9 10 11 12 0 2 4 6 8 10 12 Control Input Voltage (V)Percentage error between digital timing generator and theoretical expression (%) A/D Gain block scaling Binary multiplication scaling NSC = 5/212 ; NC = 4 NL = 10 ; tCLK = 40ns Figure 3-5. Simulation analysis indicating percen tage timing error based on binary multiplication scaling and A/D gain-block scaling

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78 100 200 300 400 500 600 700 800 900 100 0 -40 -20 0 20 40 60 80 100 120 140 Sampled Inductor voltage in binaryTime duration difference from the theoretical expression (ns) NL =10 ; tCLK = 40ns ; NSC = (5/23)X(23/212) Figure 3-6. Simulation analysis indicating percen tage timing error based on binary multiplication scaling and A/D gain-block scaling

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79 / ConverterInverter A DC 12CN 12CN R S Q Q I nput Output ( ) SystemParameter DigitalTiming GeneratorInput D igitalTimingGenerator & ScalingSuccessive Accumulation A DC CommandInput Errorbinary CLK f onToffT1 0PWM PWM E rror 2CN I ntegerValue M odulatorOutput Digital SRMLN EN 12CN 12CN PWM B A / A BAB 0 1 ONtOFFtOFFtONt Figure 3-7. Generic architecture of a system controlled by digi tal synthetic ripple modulator 2 H ys ModulatorCommand PWM H ys ONt 2 Hys ModulatorCommandSyntheticRipple OFFt OutputVariable M odulatorOutput Figure 3-8. Generic synthetic ripple modulation showing the hysteretic thresholds, command variable and PWM signal

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80 / A D 12CN 12CN R S Q Q D igitalTimingGenerator & ScalingSuccessive Accumulation / A D cmdv CLK f PWM PWMerrorv PWM 2CN I ntegerValue M odulatorOutput D igital SRMLN EN ONtOFFt L v inV,LLrC p hasev Cr PWM ()outvt ONtOFFt1 0 B A / A BAB 0 1 12CN 12CN Errorbinary OFFtONt Figure 3-9. Architecture of digital SRM c ontrolled synchronous buck DC-DC converter.

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81 Li 1 inoutVV m L 2 outV m L hys I outit max outI Figure 3-10. Inductor current waveform during lo ad current step-up and steady-down transient 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 2 4 6 8 10 12 14 16 18 20 Inductor Voltage (V)Percentage error between digital timing generator and theoretical expression (%) NSC = 5/23 ; NB = 23/210 ; Count = 16 NSC = 9/24 ; NB = 24/211 ; Count = 15 NSC = 8/24 ; NB = 24/211 ; Count = 15 Figure 3-11. Simulation analysis of percentage error for various scaling factor approximations

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82 errv3 2 1 0 1 2 3 21EN 2EN cmdvoutv Figure 3-12. Transfer characteri stic of the A/D converter samp ling the error voltage between output and command voltage. inV_ s yncrectVphaseV VPWM Figure 3-13. Simulink model of the PWM switch

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83 phasev 1 L 1 s L i Lr 1 C 1 s outV Cr 1 L oadR outi Figure 3-14. Simulink model of buck LC filter / A DGain A nalogInput N D igitalOutput Z eroorder Hold QuantizerSaturation _max21analog LSB NV V Figure 3-15. Simulink mode l of the A/D converter

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84 __ digitaltiminggen L binaryV Timgenen_ Initcy Sampledelay A ccval Integerval_ Carr y out_ Stepvalue_ A ccval Figure 3-16. Simulink model of digital timing generator

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85 B uckLCFilter 5inVV outv errADV8 I nteger Value M ODOP 8 8 R S Q Q VPWM phasev PWM Switch L v __ digitaltiminggen Sampledelay 8LN _0.2syncrectVV cmdv errV A DC A DC/5ADN 10 8 0..7 A0..7 B / ADDSUB VPWM/ A BAB onToffTDigital Timing Generator Figure 3-17. Block diagram depicting the Simu link model of digital SRM controlled buck converter

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86 ()L I nductorCurrenti()L I nductorVoltagev()phasePhaseVoltageV()outOutputVolta g ev 1.1 s 2.6 s2/ sdiv Figure 3-18. Simulation outputs of the synchronous buck converter using MATLAB/Simulink for Vcmd=1.3V

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87 S tepValue_ Inte g ervalVPWMModulatorOutput 1.1 s 2.6 s2/ s div Figure 3-19. Simulation outputs indicating th e step value, integer value and VPWM signal of the digital timing generator

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88 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0.5 1 1.5 2 2.5 3 3.5 Inductor Voltage (V)Time duration from digital timing generator (us) Digital Timing Generator Simulation data Theoretical expression data Figure 3-20. Comparison between on-time/off-time generated based on theoretical equations and simulated synthetic ripple modulator.

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89 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5. 5 0 2 4 6 8 10 12 14 Inductor Voltage (V)Percentage error between digital timing generator and theoretical expression (%) Figure 3-21. Percentage error be tween digital timing generator a nd theoretical expression using simulation analysis

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90 Figure 3-22. Voltage change across the output capacitor during a step-down load transient

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91 Figure 3-23. Integer_value, modified hys teretic count, VPWM, and Error_binary for AVP implementation in digital SRM

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92 Figure 3-24. Integer_value, modified hys teretic count, VPWM, and Error_binary for AVP implementation in digital SRM

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93 Figure 3-25. Inductor current a nd AVP of the output voltage based on optimal AVP design for the load step-up transient

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94 Figure 3-26. Inductor current a nd AVP of the output voltage based on optimal AVP design for load step-down transient

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95 Figure 3-27. Inductor current and AVP of the output voltage Vcmd reaches higher leve l before the peaking of Vout (Vout_max)

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96 Figure 3-28. Inductor current and AVP of the output voltage Vcmd reaches higher leve l before the peaking of Vout (Vout_max)

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97 Figure 3-29. Inductor current, VPWM, and AVP of the output voltage Vcmd reaches higher level after the peaking of Vout (Vout_max)

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98 Figure 3-30. Modulator output, Erro r_binary, and AVP of the output voltage Vcmd reaches higher level after the peaking of Vou t

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99 ^ ^ () out vdBuckConverter v Gs d D utyratiotoOutput voltage ()outvtd ()cmdvt 2() s t ENEGGAe()errorvt 1() s t LNLGGAe ()phasevt ^ ^ () dvcmd cmdd Gs v CommandtoDutyratio SCN Figure 3-31. Dynamic system model of the di gital SRM controlled synchronous buck converter

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100 100 101 102 103 104 105 106 -30 -20 -10 0 10 20 100 101 102 103 104 105 106 0 50 100 150 200 Frequency (Hz) () CommandtoDutyratioMagnitudedB 4.7;200;0.5 0.27;5;1.34;1.3oload inoutcmdLHCFR D VVVVVV () CommandtoDutyratioPhasedegrees Figure 3-32. Magnitude and phase of command (v cmd) to duty ratio (d) transfer function

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101 100 101 102 103 104 105 106 -60 -40 -20 0 20 40 100 101 102 103 104 105 106 -200 -150 -100 -50 0 Frequency(Hz) () D utyratiotoOutputvoltageMagnitudedB () D utyratiotoOutputvoltagePhasedegrees 4.7; 15;200;10 0.5;0.27;5;1.34LoC loadinout L HrmCFrm RDVVV Figure 3-33. Magnitude and phase of duty ratio (d ) to output voltage (vou t) transfer function

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102 100 101 102 103 104 105 106 -50 -40 -30 -20 -10 0 10 20 100 101 102 103 104 105 106 -200 -150 -100 -50 0 Frequency (Hz)^^() () ()cmdoutCommandvtoOut p utvolta g evMa g nitudedB^^() () ()cmdoutCommandvtoOutputvoltagevPhasedegrees 4.7; 15;200;10 0.5;0.27;5;1.34LoC loadinout L HrmCFrm RDVVV Figure 3-34. Magnitude and phase of command (vcm d) to output voltage (vout) transfer function

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103 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Command or Reference voltage Vcmd (V)Buck Converter Output Voltage Vout (V) Output Voltage (Simulation data) Linear Fit Figure 3-35. Plot indicating the linear control of output voltage with command voltage based on MATLAB/Simulink simulation

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104 3.478 3.48 3.482 3.484 3.486 3.488 3.49 x 10-3 1.371 1.372 1.373 1.374 1.375 1.376 1.377 1.378 time (sec)Output Voltage (Vout (V))Effect of Output Filter Variations on Output voltage L-5.44uH C=4.73mF L=3.99uH C=3.87mF L=3.99uH C=4.73mF L=5.44uH C=3.87mF Figure 3-36. Simulation plot indicating the effect of component variations on the performance of the digital SRM

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105 2.495 2.5 2.505 2.51 2.515 2.52 2.525 2.53 2.535 2.54 2.545 x 10-3 4 6 8 10 12 14 2.495 2.5 2.505 2.51 2.515 2.52 2.525 2.53 2.535 2.54 2.545 x 10-3 1.4 1.5 1.6 2.495 2.5 2.505 2.51 2.515 2.52 2.525 2.53 2.535 2.54 2.545 x 10-3 -5 0 5 2.495 2.5 2.505 2.51 2.515 2.52 2.525 2.53 2.535 2.54 2.545 x 10-3 -0.5 0 0.5 1 Load current Inductor current (sec) time_ (A/D output of sampled error voltage) VerrAD(V) (OutputVoltage)outV () () L L oadCurrentstepandInductorcurrentiA(UFET PWM Signal) VPWM Figure 3-37. Simulation of open-loop load transi ent response of digital SRM controlled buck converter with Vcmd=1.5 V and load step of 5A to 10A in 100 ns (50 A/s)

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106 CHAPTER 4 DESIGN AND EXPERIMENTAL IMPLEMENTA TION OF DIGITAL SYNTHETIC RIPPLE MODULATOR The hardware implementation of the digita l SRM controlled sync hronous buck converter involves the implementation of digital timing ge nerator, synchronous buc k converter, and signal conditioning blocks. The digi tal timing generator is implemented using the ALTERA UP2 FPGA/CPLD board and utilizes Quartus II soft ware for timing analysis simulation. The signal conditioning block and the synchronous buck converter are implemen ted using discrete components based on simulation anal ysis from LTSpice/SwitcherCAD™. 4.1 Experimental Implementation of Synchronous Buck Converter The synchronous buck DC-DC converter impl ementation involves the design of power MOSFETs, inductor selection and ou tput capacitor selection. The converter shown in Figure 4-1 also requires synchronous buck gate drivers for driving th e power MOSFETs. The various component selections are based on the specificati ons outlined in Table 3-2 and the allocated loss budget. For a nominal output voltage of 1.5 V and load current of 4 A, the output power can be calculated as 1.5 4 6 outoutoutPVIVAW (4-1) Assuming an efficiency of =85% for the synchronous buck converter, the total loss budget can be determined to be _out LosstotalinoutoutP PPPP (4-2) _6 61.06 0.85LosstotalinoutW PPPWW (4-3) The stead-state duty ratio based on the specifications listed in Ta ble 3-2 is determined to be

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107 1.5 0.3 5out inV D V (4-4) 4.1.1 Power MOSFET Design and Selection The selection of the power MOSFET (UFET and LFET) is based on the switch blocking voltage and the on-resistance ( D Sonr ) of the device. The voltage across the UFET switch during the OFF-state (VPWM=0) is _maxDSUFETinVV (4-5) Hence the blocking voltage consider ing a safety factor of 2 is _max225.2510.5BlockUFETinVVV (4-6) Similarly the blocking voltage across the lowe r FET (LFET) is 10.5 V when the UFET is ON (VPWM=1). The current through the UFET MOSFET during a switching cycle is shown in Figure 4-2. In a buck converter the average value of the i nductor current is equal to that of the load current and given by LLoutiII (4-7) The power loss in the FETs can be determined based on the rms current. 2 _'0UFETrmsoutIDID (4-8) _2.2UFETrmsout I IDA (4-9) Assuming a 30% loss in the power MOSFETs, _0.3 159 2Losstotal LossUFETP PmW (4-10) The require on-resistance of the UFET can be determined to be

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108 2 _@150 _33 LossUFET DSONHOTC UFETrmsP rm I (4-11) _(@150) _@2513.2 2.5DSONUFETHOTC DSONUFETCr rm (4-12) Based on Equations 4-6 and 4-12, the power MOSFET chosen for the UFET and LFET is IRF7455 [68]. The IRF7455 N-channel power MOSF ET is specifically designed for use in high frequency DC-DC converters with synchronous r ectification. The power MOSFET can withstand a maximum drain-source voltage of VDSS=30V and exhibits low on-resistance (rDSON=7.5 m ) for VGS=4.5 V. Thus the actual pow er loss can be estimated. 2 __37 LossUFETUFETrmsDSONPIrmW (4-13) Thus the remaining loss budget can be recalculated as __237 0.986 LossremLosstotalPPmWW (4-14) 4.1.2 Output Filter Inductor Selection The component selection for the inductor is based on ESR (rL) of the inductor and the value of the inductor. The copper lo ss occurring in an inductor for a given current is estimated as 2 _CuLossLLrmsLPIr (4-15) Assigning 25% of the remaining loss for th e inductor loss budget, the ESR can be determined as 2 __0.25 ; CuLossLLossremLrmsLLrmsoutPPIrII (4-16) 15 Lrm (4-17) The inductor value determined from Eq. 3-36 is given to be L=4.76H. Based on the above calculations, an axial type inductor from Coilcraft was used for the experimental implementation. The inductor part number from the website is PCV-1-472-10L. The DC

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109 resistance or ESR of the chosen inductor is 12 m (i.e.12 Lrm ) with a variation in the inductor value of 15%. 4.1.3 Output Filter Capacitor Selection The output capacitor based on voltage regula tion specifications as determined from Equation 3-40 is 425F. The output capacitance is realized by a capacitor bank consisting of 5 capacitors each of 100F. The part-numbe r for the 100 F is 293D107X9020E from Vishay electronics. Each capacitor has an ESR (equivalent series resistance) of 10 m 4.1.4 Synchronous Buck Gate driver The experimental implementation utilizes the TPS2830 [69] synchronous buck MOSFET driver from Texas Instruments™. The driver ha s an in-built bootstrap diode which helps to reduce noise due to switching transitions. The dr iver also incorporates an adaptive dead time control to prevent shoot-th rough currents through the UFET and LFET during the switching transitions. The adaptive dead-time control al so provides higher e fficiency for the buck converter. 4.2 Experimental Implementation of Signal Conditioning Circuit The signal conditioning circuit incorporates the scaling factor used in scaling and successive accumulation process. It is also used to interface the DC-DC buck converter signals to the input of the A/D converter. The scaling factor to be included in the A/D signal conditioning circuit as determined from Eq. 3-52 is 4 1111992 2162SCN (4-18) _/9 16SCADN (4-19)

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110 The inductor voltage is sampled by the A/D c onverter for generating the synthetic ripple used for carrier signal. The polarity of the inductor voltage is positive during the on-time (VPWM=1) and negative during the off-time (VPWM= 0). The negative polarity is an indication of the discharge phase of the output capacitor. The digital timing gene rator requires only the absolute value of the inductor voltage to generate the step value. Thus the polarity of the inductor voltage needs to be reversed during the off-time or the discharge phase. An 8-bit A/D converter is used for sampling the inductor voltage based on the step value resolution requirement of NL=8 The A/D converter selected fo r the current application is ADS930 [70] from Texas Instruments™. The ADS 930 is an 8-bit, 30 MHz converter with a single ended full-scale range spa nning from 1 V to 2 V (1Vp-p) and a common-mode voltage of 1.5 V. The choice of ADS930 is influenced by the availability of the 25. 175 MHz oscillator from the ALTERA UP2 board and the range of output vol tages (1.2-1.85 V) of the buck converter. The inductor voltage of the buck converter is obtained from the difference between the phase voltage (Vphase) and the output voltage ( Vout). The range of voltages from the converter at the phase node and output voltage node need to be mapped to the allowabl e range of voltages at the input of the A/D converter. If KSC is the voltage scaling ratio for the inductor voltage, then the buck converter voltage can be mapped into the A/D input range by max /maxLN AD SCVA V K (4-20) where VLmax is the maximum inductor voltage (= Vinmax), VA/Dmax is the maximum voltage swing of the A/D converter, and AN is the gain of the operational amplifier used for buffering the scaled voltages. The scaling factor can be included in the volta ge scaling ratio to yield the resistive voltage division ratio as _11SCAD RSCN KK (4-21)

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111 Assuming an opamp gain of 3 and using the sp ecifications of the buck converter and the A/D converter the scaling is determined to be max /max5.253 15.75 1LN SC ADVA K V (4-22) _11191 15.751628SCAD RSCN KK (4-23) For the voltage division at the phase node and output voltage node, assuming one of the resistances as 18 k the resistive divider ca n be determined to be _1 18phaseposphasephase RR VVV KRk (4-24) 11 2818RR KRk (4-25) 660 R (4-26) The schematic representation of the voltage scaling to map the buc k converter voltages into the A/D input voltage range is shown in Figure 4-3. The simulation of the schematic in Figure 4-3 using LT Spice invol ved the actual components us ed in the experimental implementation. From Figure 4-3, the voltages at th e output of the operational amplifier A1 (Gain=3) and A2 (Gain=3), namely Vphase_pos1 and Vout_neg1 are the scaled phase node and output voltages respectively. The inductor voltage duri ng the on-time is obtained by applying Vphase_pos1 to the non-inverting input and Vout_neg1 to the inverting input of the operational amplifier A3. Thus, VLpos_adc_input, the amplifier A3 output represents the inductor voltage during on-time. It is connected to the A/D converter which generates the sampled binary value VLPOS [7...0]. The inductor voltage during the offtime is obtained by applying Vphase_pos1 to the inverting input and Vout_neg1 to the non-inverting input of the operational amplifier A4. Thus, the polarity is

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112 switched during the off-time resulting in the output VLneg_adc_input. This output is connected to A/D converter which yields the sampled output name ly, VLNEG [7…0]. The out put of the difference amplifiers are level sh ifted to account for the A/D convert er input range. The error voltage between command ( Vcmd) and output voltages ( Vout) is obtained using the difference amplifier A5. The output of the difference amplifier A5, namely Verr_adc_input, is connected to the A/D converter which produces the sampled error voltage VERRADC [7…0]. ___1_11.0VLposadcinputphaseposoutnegVVV (4-27) ___1_11.0VLnegadcinputoutnegphaseposVVV (4-28) The A/D converter outputs form the input to the digital synthetic ri pple modulator shown in Figure 4-4. The A/D outputs VL POS [7..0] and VLNEG[7 ..0] are given as i nput to the 8-bit 2to-1 multiplexer. The signals blnk_pos and blnk_neg are used to enable the 8-bit registers during on-time and off-time respectively. In a given switc hing cycle, when the m odulator output reaches the higher hysteretic threshold, the signal vh_set is set to logic 1. Sim ilarly when the modulator output reaches the lower hysteretic threshold, vl_set is set to logic 1. A set of combinational logic employing counters and latches are used to generate the ADC register enable signals. As stated earlier, once vl_set is set to logic 1, th e counters are enabled and blnk_pos signal is generated. The signal blnk_pos is delayed by 840 ns (determined fr om experimental signal conditioning circuit delays) with reference to vl_set Similarly blnk_neg is delayed by 1.5 s with reference to vh_set Thus the blnk_pos and blnk_neg signals ensure that the output from the A/D corresponds to the sampled inductor voltage during on-time and off-time respectively. The 8-bit 2-to-1 multiplexer receiving the inputs from the ADC registers carries out the polarity switching process by providing the on-time and off-time step va lues to the digital in verse timing generator based on VPWM signal. The timing signals vh_set vl_set blnk_pos blnk_neg and VPWM are

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113 indicated in Figure 4-4. The timing signals and the generatio n of the A/D outputs are also indicated in Figure 4-12 with re ference to the analog input volt ages to the A/D converter. The operational amplifier used in the expe rimental implementation is LT1022 [71] from Linear Technology™. LT1022 is a JFET input, pr ecision operational amplifier specifically designed for instrumentation applications. The se lection of the operational amplifier is greatly influenced by the slew-rate of the opamp. Th e phase node voltage has steep rising edges with slopes in the range of 50 V/s. The slew-rate of LT1022 is 26 V/s and sufficient enough to sample the inductor voltage at a particular swit ching cycle and generate the duty ratio based on it in the subsequent switching cy cle. The digital SRM implementa tion allows a slower slewing opamp to be used due to the fact that the ge nerated duty ratio is base d on the sampled inductor voltage at the previous switching cycle. Thus, the digital implementation allows additional cost savings. The asymmetry of the signa l swing (3.5 V and -1.5 V) n ecessitates the need for the twostage scaling and difference implementation. Th e schematic representation of Figure 4-3 was implemented in LTSpice/Switcher CAD and the a ssociated waveforms are indicated in Figures 4-5, 4-6, 4-7, and 4-8. The small-signal ac analysis (fre quency response) of the amplif ier indicating the loop gain and phase margin is shown in Figure 4-5. In or der to simulate the functionality of the signal conditioning circuit, the DC -DC buck converter was driven under open-loop condition by providing an external high-side gate drive for the UFET, namely the VPWM signal. The duty ratio of the VPWM signal is 0.325 at a switching frequency of 300 kHz. The LFET is driven by the complement of the VPWM signal. The command reference Vcmd was ramped up from 0V to 1.5V in 800 s. The phase node voltage and its sc aled value are plotted in Figure 4-6. The A/D input voltages derived from the s caled phase voltage and output vol tage are indicated in Figure

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114 4-7.The reference voltage, output voltage, error between the out put and reference voltage, and the error input to the A/D conve rter are shown in Figure 4-8. 4.3 Hardware Implementation of DC-DC Bu ck Converter and A/D Signal Conditioning Circuit The synchronous buck converter and the signal conditioning circuit are implemented on hardware using a printed circuit board (PCB). Th e PCB layout for the board was developed using Protel 99 SE software. The PCB board was milled on a 0.059” (59 mil) 0.5 oz. two layer copper board using Quick Circuit™ milling machine from T-Tech. The layout of the buck converter and the signal conditioning circuit from the gerb er file are shown below. The top layer and bottom layer of the PCB are indicated in Figure 4-9 and Figure 4-10 resp ectively. The layout of the synchronous buck converter [72] is carefully designed to avoid unnecessary parasitics. The traces between the outputs of the gate driver and the gate of the MOSFETs are kept short and wide. The bypass capacitors are kept closer to the power supply (PVDD) and power ground (PGND) pins of the gate driver. The source of the high-side MOSFET (UFET) and the drain of the low-side MOSFET (LFET) are kept as clos e as possible since the phase node connecting them exhibits a high dv/dt characteristic. DC -DC converters involve high switching currents which can cause perturbations to the sensit ive analog ground of signal conditioning circuits. Hence proper care is taken to isolate the power ground (sw itching converter ground), signal conditioning circuit ground, a nd the digital timing generato r ground. The manufactured PCB board with all the components is shown in Figure 4-11. 4.4 Experimental Implementation of the Digital Timing Generator The digital timing generator was implem ented using ALTERA UP2 board. The ALTERA board has a configurable CPLD device from the FLEX10K™ family, namely FLEX10K70. The on-board oscillator of 25.175 MHz was used as the clock input for the timing generator. In

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115 Figure 4-12, the voltages at the i nput of the A/D converter are indicated with respect to the phase node voltage ( Vphase). As evident from the figure, there is a finite delay between the rising or falling edge of Vphase to that of the A/D inputs. This delay arises due to the pha se shift from the opamps in the signal conditioning circuit. The finite delays are determined from the experimental circuit and implemented using th e counters described in section 4.2 in the ALTERA board. In order to account for these dela ys, the ADC enable signals bl nk_pos and blnk_neg in Figure 4-12 are delayed by 840 ns and 1.5 s (determined from the experimental signal conditioning circuit) respectively to sample the corr ect value of the scaled inducto r voltage. The internal timing signals vl_set and vh_set in Figure 4-12 determ ine the reference point from which the blnk_pos and blnk_neg signals are delayed re spectively. The Quartus II si mulation outputs of the digital timing generator implemented in ALTERA board are shown in Figure 4-13. The VPWM signal indicating the on-time (965 ns) and the off-time (2 .68 s) is shown in th e figure for the step values derived from Equations 3-73 and 3-74. The time duration for th e corresponding inductor voltages are compared in Table 4-1 based on theoretical expression, Simulink, and ALTERA board simulation. 4.5 Experimental Implementation of Digita l Synthetic Ripple Modulator Controlling the DC-DC Buck Converter The hardware implementation of the system architecture involving the buck converter, signal conditioning circuit, A/D converters, and the ALTERA dig ital timing generator is shown in Figure 4-14. The A/D outputs are interfaced to the digital contro ller through the 60-pin through-hole connector. The output of the digital controller (VPW M) forming the input to the synchronous buck gate driver is given thr ough a Schmitt trigger (SN74AHC1G14DBVRG4). The Schmitt trigger eliminates any high frequency noi se due to the clock of the timing generator.

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116 The testing and analysis of the digital SRM controlled buck converter is explained in chapter 5 of the dissertation. The experimental implementation of the digital SRM controlled buck converter involves the implementation of synchronous buck converter, signal conditioning circuit, and the digital controller. The bill of ma terials for the experimental implementation of the buck converter, signal conditioning circuit and the di gital controller are i ndicated in Table 4-2, Table 4-3, and Table 4-4 respectively.

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117 Table 4-1. Comparison of time duration from simulations Parameter Theoretical Expressi on MATLAB/Simulink ALTERA board VLTon=3.66V 1.027s 1.1s 0.965s VLToff= -1.54V 2.44s 2.6s 2.68s Table 4-2 Bill of materials for th e synchronous buck DC-DC converter Synchronous buck DC-DC converter S.No Component or Symbol name Part Number Specifications Qty 1 UFET and LFET IRF7455 (International Rectifier) 30V,rDSon=7.5m 2 2 Inductor (L) PCV-1-472-10L (Coilcraft) 4.7 H 15%, DCRmax=0.021 1 3 Output Capacitor (C) 293D107X9020E (Vishay Electronics) 100 F, esr=10m 5 4 MOSFET Gate driver TPS2830 (Texas Instruments) 4.5V-15V, 2.4A peak output current, 50ns rise/fall times-3.3nF load 1 Table 4-3 Bill of materials for the A/D converter and signal conditioning circuit A/D Signal conditioning circuit S.No Component or Symbol name Part Number(s) Specifications Qty 1 Opamps(A1,A2,A3, A4,A5) LT1022 (Linear Techonology) Slew rate 23V/ s; GBW=8.5MHz 5 2 A/D converter (ADC) ADS930 (Texas Instruments) 8-bit, 30MHz, 1Vp-p Full Scale 3 3 Resistors (660 ,18k ,2.2k 1k ,2k ,150 ) P18KECT-ND P2.2KECT-ND P1.0KECT-ND (Digi-key) 1/8W 5% 1206 SMD 10 4 Capacitors ( 220pF, 82pF) PCC221CGCT-ND 478-1479-1-1ND (Digi-key) 5% 50V 1206 SMD 5 5 Receptacle connector 4-1734005-0 (Tyco Electronics) AMPMODU receptacle 40 positions, Dual rows 2

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118 Table 4-4 Bill of materials for the FPGA based digital controller Digital SRM controller S.No Component or Symbol name Part Number(s) Specifications Qty 1 Digital controller FPGA board ALTERA UP-2 Evaluation board (Altera) FLEX10k70 and MAX7000S CPLDs, 25.175MHz onboard oscillator 1

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119 VinPWM switchOutput L-C filter,LLrCoutV VPWM L i phasev outi Cr Cv DigitalSRM L v UFETLFET L oadR outV cmdVSYNC B UCK DRIVER Figure 4-1. Schematic of s ynchronous buck DC-DC converter L i SDT'SDTSDT L iUFETi() ts Figure 4-2. Current through th e UFET in a switching cycle

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120 Vin 4.7,12LLHrm 500 C FoutV p haseV Cr Cv L v VPWM VPWM p haseV p haseposV 1 k2 k 66018 k _1 p haseposV cmdV 1.25LevelVV 2.2 koutV__ erradcinputV2.2 k 2.2 k 2.2 k 150220 p F82 pF1501 A 5AIRF7455IRF7455PCV-1-472-10LLT1022 LT1022 930 ADS 0 D 7 D CLK f outV outnegV 1k2 k 15066018k _1 outnegV220 p F2ALT1022 _1 p haseposV 82 pF_1 outnegV__ L posadcinputVonInductorVoltageduringT 2.2 k 2.2 k 2.2 k 2.2 k1503A1.0LevelVV LT1022 _1 p haseposV _1 outnegV__ L negadcinputVoffInductorVoltageduringT 2.2 k2.2 k2.2 k 2.2 k15082 pF4A1.0LevelVV LT1022[7..0] VERR930ADS 0 D 7 D CLK f [7..0] VLPOS930ADS 0 D 7 D CLK f [7..0] VLNEG Figure 4-3. Schematic of signal conditioning circu it for the A/D converter with inclusion of the scaling factor

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121 Figure 4-4. Block diagram of th e experimental digital synthetic ripple modulator indicating the register enable and timing signals

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122 105 54 DCgaindB PhaseMargin ---------: Gain : Phase Figure 4-5. Frequency response of th e signal conditioning circuit amplifier

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123 phaseposV_ outne g V p haseVoutV800/ nsdiv Figure 4-6. Phase voltage, converter output voltage, and signal conditi oning circuit scal ed voltages for Vcmd=1.5V

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124 _1 p hase p osV 1 outne g V__ LposadcinputV__ LnegadcinputV Figure 4-7. Inductor voltages at the input of the A/D converter for a duty cycle of D=0.325 and Vcmd=1.5V

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125 __ erradcinputVcmdVoutV Figure 4-8. Buck converter out put voltages, error voltage a nd output A/D input voltage for Vcmd=1.5V

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126 Figure 4-9. Gerber file indicati ng the top layer of the PCB board

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127 Figure 4-10. Gerber file indicating the bottom layer of the PCB board

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128 S YNCBUCK CONVERTER S IGNALCONDTG CIRCUIT / AD CONVERTER Figure 4-11. Photograph of the manufactured PCB board indicating the buck converter and the signal conditioning circuit

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129 ONTOFFT10(100) LposbinVphaseV ONT __ L posadcinputV blnkpos __ L negadcinputV blnkneg 10(100) LposbinV10(42) LnegbinV 10(42) LnegbinV 5inVV _0.2syncrectVV 0.3881.0()1.388 VLevelShiftV 0.1631.0()1.163 VLevelShiftV 840 ns 1.5 s Figure 4-12. Timing signals and A/ D converter input voltages for the signal conditioning circuit

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130 Figure 4-13. ALTERA board based digital sy nthetic ripple modulator outpu ts indicating VPWM outputs for step values (100)10 and (42)10

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131 Figure 4-14. Experimental implementation of DSRM controlled buck converter system

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132 CHAPTER 5 TESTING AND ANALYSIS OF DIGITAL SRM CONTROLLED BUCK CONVERTER The DC-DC buck converter contro lled by the digital synthetic ripple modulator consists of three main components, namely the synchr onous buck DC-DC convert er; ALTERA FPGA based digital timing generator, and th e A/D signal conditioning circuit. Each of the major blocks was tested at the module level to verify the functionality and extr act key parameters used for characterization. The system level testing was ca rried out to characterize the digital synthetic ripple modulation technique when applied to the control of power converters. 5.1 DC-DC Buck Converter Testing and Measurement The experimental test-bed used for measuring the various parameters of the buck-converter is shown in Figure 5-1. The list of equipments us ed in the measurement of various parameters is indicated in Table 5-1. The synchronous buck co nverter was driven by an externally generated PWM signal with a specified duty ratio in the following test procedure. This test was used to characterize the functionality of the buck convert er and determine the various propagation delays involved in the system. The test procedure is outlined below: 1. The current-limits of the voltage source (A gilent E3631A) supplying the gate driver and voltage source (HP6024A) supplying the input vo ltage of the buck converter was set to 5A and 4A respectively. 2 A power resistor of 1 (2 5W || 2 5W – part number DALE RH-5 5W 2 1%) is connected across the output capacitor for setting the load current to 1.5A. 3 The PVDD pin of the TPS2830 gate driver was set to 5V by gra dually increasing the voltage supply (Agilent E3631A ) from 0 to 5V. The cooling fan can be turned on for higher load conditions to c ool down the power MOSFETs. 4 A square wave with 5V amplitude, duty ra tio of 30%, and a frequency of 300 kHz was applied to the PWM input of the TPS2830 gate driver. 5 The input voltage of the buck converter (Vin ) was gradually increased from 0V to 5V by monitoring the output voltage and the input current.

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133 6 The gate drive (vGS2) for the lower MOSFET (LFET) and the gate voltage at the upper MOSFET (UFET) were measured. 7 The phase or the switch node voltage (Vphase) was measured. 8 The output voltage (Vout) of the buck converter was measured. 9 The inductor current was measured using a current loop. The measured waveforms from the buck converter are illustrated in Figures 5-2 to 5-8. Figure 5-2 indicates that during the on-tim e when PWM input is high (VPWM=5V), the UFET is turned ON and the switch node voltage is approximately equal to Vin. During the offtime the LFET is ON and the switch node voltage is pulled to ground. During the turn ON of the LFET, the body-diode of LFET conducts for a short duration to provide a continuous path for the inductor current and to avoid DCM (Discontinuous Conduction M ode). Figure 5-3 indicates the output voltage of the buck converter satisfy ing the steady-state dut y ratio expression Vout=DVin=0.3 X 5 = 1.5V. Figure 5-4 and 5-5 indicates th e sequential events of the hi gh-side gate drive going high followed by the phase-node voltage going high with the turn ON of UFET. The propagation delay between the rising of the PWM input with that of the high-side drive and phase node voltages are indicated in the respective figures. In Figure 5-6, the PWM input and the low-si de gate drive are indicated. Figure 5-7 indicates the dead-time between the falling of Vphase and the turn ON of the lower FET (LFET). The dead-time ensures that both the FETs are not ON at the same time and prevents any shootthrough currents between the MOSFETs. The inductor voltage obtained from the differe nce between the phase node voltage and the output voltage is shown in Figure 5-8.

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134 5.2 Signal Conditioning Circuit Testing and Measurement The functionality of the signa l conditioning circuit was tested and the propagation delays involved in the circuit were measured. The de termination of these delays enables accurate sampling of the scaled inducto r voltages. The testing is ca rried out by operating the buck converter in an open-loop condi tion and applying an external PWM input signal with duty ratio D=0.25. The following waveforms were measured from the signal conditioning circuit shown in Figure 4-3. Amplified phase and buck converter output voltages at the opamp outputs Vphase_pos1 and Vout_neg1. A/D input voltages for sampling the inductor voltage VLpos_adc_input and VLneg_adc_input. A/D input voltages for sampling the error vo ltage between the co mmand reference and output voltage – Verr_adc_input. Figures 5-9 to 5-12 depict the voltages associ ated with the signal conditioning circuit. These voltages are obtained for an input voltage of Vin=5V with command reference at Vcmd=1.38V. The measured buck converter output vol tage was 1.28 V. In Fig 5-9, the scaled phase voltage at the output of the opamp A1 in Fi g 4-3 is plotted. The pl otted outputs are verified with Equations 5-1 and 5-2. _1660660 3530.531 6601800066018000phaseposphaseVVV (5-1) In Figure 5-10, the scaled output voltage is pl otted which satisfies the following relation, _1660660 31.2830.136 6601800066018000outnegoutVVV (5-2) In Figure 5-11, the scaled inductor voltage during the on-time (PWM=1) forming the A/D input is shown which satisfies Eq. 5-3. ___1_11.0 V=0.5310.1361.0=1.395 VLposadcinputphaseposoutnegVVV (5-3)

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135 In Figure 5-12, the scaled inductor voltage during the off-time (PWM=0) forming the A/D input is shown which satisfies Eq. 5-4. ___1_11.0 V=0.136(0.1)1.01.235 LnegadcinputoutnegphaseposVVVV (5-4) Figure 5-13 indicates the level shifted error between the outp ut voltage and the command reference satisfying the following relation. __11.281.381.51.4 VerradcinputoutcmdVVV (5-5) As evident from Figures 5-9 to 5-13, the delay between the rising edge of Vphase and the instant at which VLpos_adc_input settles to the required scaled inductor voltage (during PWM=1) is 840 ns. Similarly the delay between the falling edge of Vphase and the instant at which VLneg_adc_input settles to the required scaled induct or voltage (during PWM=0) is 1.5 s. 5.3 Digital Synthetic Ripple Modulator Controlled Buck Converter Testing and Measurement Digital synthetic ripple modul ator utilizes the A/D outputs from the signal conditioning circuit to determine the on-time or off-time of the power MOSFET switches and controls the synchronous buck converter using the generated VPWM signal. T hus the output of the signal conditioning circuit forms the feedback input to the digita l modulator. The digital timing generator in the digital modulator utilizes the prop agation delay data from the open-loop tests to generate input register enable si gnals. The register-enable signals blnk_pos and blnk_neg are delayed by 840 ns and 1.5 s from the rising and falling edges of Vphase respectively. The active high enable signals are kept in logic high condition for 320 ns (8 clock counts) to accommodate the A/D converter latency of 5 clock cycles. The clock frequency used in the A/D converter is 25.175 MHz (tCLK=40 ns). The closed loop operation of the digital modulator, buck converter and the signal conditioning circ uit is tested uti lizing the test procedure outlined below:

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136 1 The PVDD pin of the gate driver was set to 5V by gradually increasing the voltage supply from 0 to 5V. 2 The ALTERA board is powered and the powe r-on-reset and clk_en signals are enabled appropriately. 3 The signal conditioning circu it is powered by setting the VDD and VEE to 15V and -15V respectively 4 The input voltage of the buck converter (Vin) was gradually in creased from 0V to 5V and the command reference (Vcmd) was simulta neously increased from 0V to 1.4V by monitoring the output voltage. 5 The Vcmd is adjusted until the output voltage settles to the required value and digital modulator outputs a PWM signal w ith constant switching frequency. 6 A power resistor of 1 (2 5W || 2 5W part number DALE RH-5 5W 2 1%) is connected across the output capacitor for setting the load current. 7 The phase or the switch node voltage (Vphase) was measured. 8 The gate drive (2 GSv ) for the lower MOSFET (LFET) a nd the gate voltage at the upper MOSFET (UFET) was measured. 9 The output voltage (OUTv ) of the buck converter was measured. 10 The inductor current is meas ured using the current loop. The input of the A/D converters, the digita l modulator inputs and the VPWM signal are measured and plotted in the following figures. Th e scaled inductor voltage at the input of the A/D converter during on-time and off-time are shown in Figure 5-14 and 5-15 respectively. From Figure 5-14 and 5-15 the A/D input voltages can be determined to be ____(1)1.65 (0)1.2LposadcinputLnegadcinputVVPWMVandVVPWMV (5-6) The LSB equivalent of the A/ D converters is given as _930 81V 3.92 2121LSBADS NFullScale VmV (5-7) The theoretical A/D output in ea ch case can be derived as

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137 102 9301.651 16610100110IDEAL LSBADSVLPOS V (5-8) 2 10 _930(1.21) 51(00110011)IDEAL LSBADSVLNEG V (5-9) The measured A/D outputs as determined fr om Figures 5-16 and 5-17 for the inductor voltage during the on-time and off-time are given as, 210[70](10100001)(161)measuredVLPOS (5-10) 210[70](00111100)(60)measuredVLNEG (5-11) Thus the measured A/D outputs closely a pproximate the outputs predicted from the theoretical expression. The A/D outputs, VLPOS [7-0] and VLNEG [7-0] forms the step value for the successive accumulation proce ss in the digital timing generator. From figure 5-19, the error vol tage A/D input can be dete rmined to be 1.4 V. The theoretical A/D output can be derived as, 10 _9301.41 (102)ideal LSBADSVERRAD V (5-12) 10 2[70]01101110(110)measuredVERRAD (5-13) The measured output approximately equals the theoretical output. 5.3.1 Digital Inverse Timing Generator Testing The synthetic ripple modulator based on hyste retic control involves generation of on-time and off-time duration for the power MOSFETs with inverse relation to th e inductor voltage. The inverse timing generator was implemented on the ALTERA UP2 board and tested over the entire input range of 0.25 V to 5.25 V. The measur ed time duration from the ALTERA board is compared with the time duration obtained from si mulation and theoretical expression. The time duration comparison plot is indicated in Figure 5-20.

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138 The time duration comparison plot utilizes th e following theoretical expression to compare the measured digital timing generator output with that of the simulation and theory. L ONOFF LLLI K tort VV (5-14) The percentage timing error between the digital and the theoretical approaches is plotted in Figure 5-21. As evident from Figure 5-21, the erro r is less than 4% over the entire input range. 5.3.2 Command to Output Transfer Characterist ic of Digital Synthe tic Ripple Modulator Controlled Buck Converter The property of the synthetic ri pple modulator to lin early control the out put variable with the command reference was verified with the following test. The command voltage Vcmd is varied from 1.25 V to 1.85 V and the correspon ding buck converter output voltage is measured. The linear plot of Vout vs Vcmd is obtained fo r various input voltages and load currents. The linearity plots are indicated in Figures 5-22 to 5-26. As evident from these figures, the linear control of the output variable, namely the outpu t voltage using the synt hetic ripple modulation technique is proved with the experimental implementation. 5.3.3 Load transient response Step-Respo nse of Digital Synthetic Ripple Modulator Controlled Buck Converter The open-loop load transient res ponse of the converter is test ed by providing a load step of 1.5 A at the rate of 50 A/s with a constant command voltage of 1.3 V. The load-step, inductor current and the output voltage are indicated in Figure 5-27. The load transient is created by including a load of 0.5 to an already existing load of 1 It is evident from figure 5-27 that the digital SRM responds instan taneously to the load transi ent even under open-loop condition with a droop in output voltage. In Figure 5-28, with Vcmd=1.5 V a similar load transient is applied. The figure depicts the fast response of the digital SRM wherein the upper MOSFET is turned ON instantaneously, indicated by the VPWM signal.

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139 5.3.4 Variation of Switching Fre quency Based on Load Conditions The variation of the switch ing frequency in hysteretic mode of control can be advantageous under light load condition. Due to reduced switching frequency under light load conditions, the associated switching losses are al so reduced. The varia tion of the switching frequency for the digital SRM control buck converter was investigated and associated results are shown in Figure 5-28. As evident from the figure, the converter switches at a lower frequency for load currents less than 1 A, thereby reducing the switching loss in the power MOSFETs and the gate driver. The variations in the switching freq uency can lead to a potential drawback caused by the introduction of undesirable harmonics into th e system. This complicates the design of the buck converter output filter. 5.4 Future Directives for Research The synthetic ripple modulation technique can be used in the c ontrol of motor drive controllers requiring time duration in versely proportional to a contro l input. The synthetic ripple modulation based on hysteretic c ontrol can provide efficient ope ration by operating at a lower switching frequency under light loads. The synthetic ripple modulation tec hnique can be applied to the control of low-voltage VRM (Volta ge Regulation Module) powering the modern microprocessors.

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140 Table 5-1 Equipment list and specifications S.No Equipment number Specifications 1 HP6263 Triple output power supply 0-6V,0-2.5A / 020V,0-0.5A 2 HPE3617A DC power supply 0-60V,0-1A 3 Agilent E3631A Triple Output power Supply 0-6V,5A / 0-25V, 1A 4 Tektronix AM503 current probe amplifier TM502A 20A (dc + peak ac) for current probe AM6302 5 Tektronix TDS460A 4-channel digitizing oscilloscope 400MHz, 100 MSa/s 6 PM 5192 programmable synthesizer, function generator 0.1mHz – 20MHz 7 HP6024A DC power supply 0-60V,0-10A, 200W

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141 VPWM L iphasev outi Cv L v AM503 Current-probe Amplifier TEKTRONIX P5200 High-Voltage Differential-probe 1 D Si PAPST MOTOREN 4600X 106 CFM Fan 460 4 TEKTRONIXTDSA channel DigitizingStorageOscilloscope 2 GSvTEKTRONIX TM502A L L rCCrinVoutVUFETLFET460 TEKTRONIX TDSA Figure 5-1. Experimental test -bed setup used for characterizing the DC-DC synchronous buck converter Figure 5-2. Phase node voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3

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142 Figure 5-3. Output voltage (C H1) and PWM input (CH2) for Vin=5V and D=0.3 Figure 5-4. PWM Input (CH2) and hi gh-side gate drive (CH1) for Vin=5V and D=0.3

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143 Figure 5-5. PWM input (CH2) and V phase (CH1) for Vin=5V and D=0.3 Figure 5-6. PWM input (CH2) and low-side gate drive (CH1) for Vin=5V and D=0.3

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144 Figure 5-7. Phase node voltage (CH1) and low-side gate drive (CH4) for Vin=5V and D=0.3 Figure 5-8. Phase node voltage (CH1), output voltage (CH2) a nd inductor voltage (Math2) for Vin=5V and D=0.3

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145 Figure 5-9. Vphase_pos1 (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25 Figure 5-10. Vout_neg1 (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25

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146 Figure 5-11. VLpos_adc_input (CH1) and PW M input (CH4) for Vin=5V and D=0.25 Figure 5-12. VLneg_adc_input (CH1) and PW M input (CH4) for Vin=5V and D=0.25

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147 Figure 5-13. Verr_adc_input (CH1) and PW M input (CH4) for Vin=5V and D=0.3 Figure 5-14. VLpos_adc_input (CH3), register-e nable blnk_pos (CH4) and VPWM from digital modulator (CH1) for Vin=5V and Vcmd=1.38

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148 Figure 5-15. VLneg_adc_input (CH3), regist er-enable blnk_neg (CH4) and VPWM from digital modulator (CH1) for Vin=5V and Vcmd=1.38

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149 A B C D E F G H Figure 5-16. A/D converter out put for inductor voltage during on-time-VLPOS [7-0] (CH3), register enable-blnk_pos (CH4), and VP WM (CH1). A) VLPOS0 (LSB). B) VLPOS1. C) VLPOS2. D) VLPOS3. E) VLPOS4. F) VLPOS5. G) VLPOS6. H) VLPOS7 (MSB).

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150 A B C D E F G H Figure 5-17. A/D converter out put for inductor voltage during off-time-VLNEG [7-0] (CH3), register enable-blnk_neg (CH4), and VP WM (CH1). A) VLNEG0 (LSB). B) VLNEG1. C) VLNEG2. D) VLNEG3. E) VLNEG4. sF) VLNEG5. G) VLNEG6. H) VLNEG7 (MSB).

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151 A B C D E F G H Figure 5-18. A/D output for error voltage be tween Vcmd and Vout – VERRAD [7-0] (CH3), register enable-blnk_neg (CH4), and VP WM (CH1). A) VERRAD0 (LSB). B) VERRAD1. C) VERRAD2. D) VERRAD3. E) VERRAD4. F) VERRAD5. G) VERRAD6. H) VERRAD7 (MSB).

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152 Figure 5-19. Verr_adc_input (CH1) and VPWM fr om digital modulator (CH4) for Vin=5V and Vcmd=1.38 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 2 4 6 8 10 12 14 16 18 20 Inductor Voltage VL (V)Time duration generated from digital inverse timing generator (us) Measured data Simulation data Theoretical Expression Figure 5-20. Timing generation comparison based on simulation, theory and experimental digital timing generation approach

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153 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.5 1 1.5 2 2.5 3 3.5 4 Inductor voltage VL (V)Percentage error between digital timing generator and theoretical approach (%) Figure 5-21. Percentage timing error based on ex perimental digital timi ng generation approach 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Command Input Vcmd (V)Output Voltage Vout (V) Vout Linear Fit inV = 4.5V Figure 5-22. Linear pl ot of Vout Vs Vcmd for Vin= 4.5V and load resistance RL=1

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154 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 Command Input Vcmd(V)Output Voltage (V) Vin=4.96V RL=1ohm linear Figure 5-23. Linear pl ot of Vout Vs Vcmd for Vin= 4.96V and load resistance RL=1 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 Command Input Vcmd (V)Output Voltage Vout (V) Vin = 4.17V RL=1ohm linear Figure 5-24. Linear pl ot of Vout Vs Vcmd for Vin= 4.17V and load resistance RL=1

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155 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Command Input Voltage (Vcmd (V) )Output Voltage Vout (V) VIn=5V RL=0.67ohm linear Figure 5-25. Linear pl ot of Vout Vs Vcmd for Vin=5V and load resistance RL=0.67 1.25 1.3 1.35 1.4 1.45 1.5 1.55 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 Command Input Voltage(Vcmd) (V)Output Voltage (Vout (V)) Vin=4.17V RL=0.67ohm linear Figure 5-26. Linear pl ot of Vout Vs Vcmd for Vin=4. 17V and load resistance RL=0.67

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156 2() outCHVOut p utVolta g e 4(1/) CHInductorCurrentAdiv 3(50/) CHLoadtransientstepAs Figure 5-27. Load transient respon se of the digital SRM Vout (C H2), inductor current (CH4) and load current step (CH3)

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157 0.5 1 1.5 2 2.5 3 3.5 4 640 650 660 670 680 690 700 Load Current Iout (A)Switching frequency (kHz) Vin = 4.35V Vin = 4.00V Vin = 3.75V Figure 5-28. Variation of switchi ng frequency with respect to load current for Vin=3.75V, 4.00V and 4.35V

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158 CHAPTER 6 CONCLUSION 6.1 Summary Synthetic ripple modulation technique enable s carrier signal generation from system parameters. The SRM facilitates the controlled vari able to be regulated with a tight tolerance while providing sufficien t ripple for PWM control. The modulation strategy superimposes the controlled variable with the synthetic ripple a nd thereby allows direct control of the output variable. The SRM scheme also provides the significant advantage of linear control of the output variable with a command signal even under ope n-loop conditions. Sin ce the synthetic ripple modulation derives its principle from hysteretic mode of contro l, superior dynamic performance is guaranteed. Thus the potential benefits of current mode cont rol and hysteretic mode control are achieved without the need for current sensing or a fast resolution PWM comparator. The digital SRM based on the synthetic ripple modulation scheme generates duty ratio with inverse relation to a sample d converter parameter. The digita l duty ratio generation involves a unique scaling process to eliminate the need for higher clock freque ncy and reduces power consumption. The programmable scaling factor allows realization of various switching frequencies and utilization of similar hardware fo r different applications. Since the carrier signal is derived from the converter parameter, the modulation scheme offers natural input feedforward control. The principle of the digi tal SRM was validated with simulation and experimental results. The appli cation of the digital SRM to th e control of a DC-DC synchronous buck converter was tested a nd verified experimentally. 6.2 Future Work The DC-DC buck converter application require s the design of a digital compensator to account for the error between the output voltage and the command voltage. The design of digital

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159 compensator ensures closed-loop operation and guaran tees the regulation of the output voltage to load transient conditions. The digital SRM stra tegy can be extended to the control of DC-AC inverters and speed control of induction motor drives. These applicatio ns generally involve hysteretic operation and require duty ratio generation with invers e relation to a given control input.

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160 APPENDIX A MATLAB FUNCTIONS A.1 Inductor Voltage Quantization function MATLAB function to generate the quantized am plitude for a given inductor voltage using NL=8, VLmax=5.25V. function [GNL_cmplx]=GNL_amp(sg_in) NL=8; LF=4.7e-6; Ihys=0.64; a_max= 5.25; qsg_bin=dfn_quant_bin(sg_in,NL,a_max); % % Quantized Amplitude based delays if qsg_bin <= 44 t_NL=2; elseif qsg_bin >= 45 && qsg_bin <= 56 t_NL= 87.19 + 35.831 ( qsg_bin 46 ) ; elseif qsg_bin >= 57 && qsg_bin <= 70 t_NL= 50.41 + 17.25 ( qsg_bin 57 ) ; elseif qsg_bin >= 71 && qsg_bin <= 84 t_NL= 9.829 + 15.572 ( qsg_bin 71 ) ; elseif qsg_bin >= 85 && qsg_bin <= 91 t_NL= -5.043 + 20.143 ( qsg_bin 85 ) ; elseif qsg_bin >= 92 && qsg_bin <= 99 t_NL= 47.26 + 17.248 ( qsg_bin 92 ) ; elseif qsg_bin >= 100 && qsg_bin <= 105 t_NL= 1.349 + 18.655 ( qsg_bin 100 ) ; elseif qsg_bin >= 106 && qsg_bin <= 111 t_NL= 59.49 + 14.7367 ( qsg_bin 106 ) ; elseif qsg_bin >= 112 && qsg_bin <= 120 t_NL= -13.71 + 11.516 ( qsg_bin 112 ) ; elseif qsg_bin >= 121 && qsg_bin <= 127 t_NL= 22.13 + 10.212 ( qsg_bin 121 ) ; elseif qsg_bin >= 128 && qsg_bin <= 134 t_NL= 9.871 + 9.1318 ( qsg_bin 128 ) ; elseif qsg_bin >= 135 && qsg_bin <= 141 t_NL= 30.25 + 8.212 ( qsg_bin 135 ) ; elseif qsg_bin >= 142 && qsg_bin <= 148 t_NL= 4.914 + 7.4272 ( qsg_bin 142 ) ; elseif qsg_bin >= 149 && qsg_bin <= 155 t_NL= 14.13 + 6.748 ( qsg_bin 149 ) ; elseif qsg_bin >= 156 && qsg_bin <= 162 t_NL= 18.9 + 6.158 ( qsg_bin 156 ) ; elseif qsg_bin >= 163 && qsg_bin <= 170 t_NL= 19.81 + 4.702 ( qsg_bin 163 ) ; elseif qsg_bin >= 171 && qsg_bin <= 177 t_NL= 17.33 + 5.188 ( qsg_bin 171 ) ; elseif qsg_bin >= 178 && qsg_bin <= 184 t_NL= 11.87 + 4.788 ( qsg_bin 178 ) ; elseif qsg_bin >= 185 && qsg_bin <= 198

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161 t_NL= 3.787 + 4.1525 ( qsg_bin 185 ) ; elseif qsg_bin >= 199 && qsg_bin <= 205 t_NL= 20.52 + 3.83 ( qsg_bin 199 ) ; elseif qsg_bin >= 206 && qsg_bin <= 216 t_NL= 6.127 + 3.252 ( qsg_bin 206 ) ; elseif qsg_bin >= 217 && qsg_bin <= 227 t_NL= 1.27 + 2.947 ( qsg_bin 217 ) ; elseif qsg_bin >= 228 && qsg_bin <= 245 t_NL= -6.854 + 2.6365 ( qsg_bin 228 ) ; elseif qsg_bin >= 246 && qsg_bin <= 255 t_NL= -0.02795 + 3.5935 ( qsg_bin 246 ) ; end t_NL=t_NL*1e-9; t_ana=(LF*Ihys) / sg_in ; % Determination of ideal analog time duration due to the quantized value amp_tdiff= (LF*Ihys) / ( t_ana + t_NL ) ; % Incrementing the quantized amplitude with the amplitude due % to timing error GNL_cmplx = amp_tdiff ; A.2 Error Voltage Quantization function MATLAB function to generate the quantized amplitude for the error voltage between the output voltage and command signal. function [GNE_cmplx]=GNE_amp(sg_in) NE=5; a_max=300e-3; topamp=1000e-9; tclk=40e-9; GNE_amp=dfn_quant(sg_in,NE,a_max); % Input signal quantized amp and phase GNE_cmplx=abs(GNE_amp); A.3 Dynamic system model transfer function MATLAB code for generating the command to out put transfer function, command to duty ratio transfer function, and duty ratio to output voltage transfer function. The code utilizes the inductor voltage A/D converter qua ntization function, namely, GNL_a mp(). It also utilizes the error voltage A/D converter quantization function, namely GNE_amp(). The functional description for the quantization functions are indicated above. % Frequency response of Digital SRM

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162 clear clc NL=8; NC=4; NAD=3; Verrmax=1.5; Vinmax=5.25; Ihys=0.64; tclk=40e-9; topamp=840e-9; low_freq=1; high_freq=500e3; freq_values=linspace(low_freq,high_freq,10000); len_freq=length(freq_values); Vin=5; Vcmd=1.5; R=0.2; D=0.306; rL=15e-3; rC=10e-3; L=4.7e-6; Co=500e-6; Vout=1.51; NSC= ((2^NC)*(Vinmax/2^NL)*tclk)/(L*Ihys); Vhys=(2^NC)*(Vinmax/2^NL); Tsw=3.33e-6; for j=1:len_freq % Vcmd to Duty ratio function wf(j)=2*pi*freq_values(j); Num= GNL_amp(Vout)*(1-(2*D)) + D*(GNL_amp(Vin)) ; D_A1=Vhys*(GNL_amp(Vin)); D_B1=((GNL_amp(Vin))*(GNE_amp(Vout-Vcm d))) + (2*GNL_amp(Vout )*(GNE_amp(Vcmd-Vout))); D_C1= D*(GNL_amp(Vin)) + ( D*(GNE_amp((2*Vcmd)-(4*Vout))) ) (GNL_amp(Vhys)) (GNE_amp(Vcmd-Vout)) + GNL_amp(Vout) ; PDV = (L*Co)*( 1 + (rC/R) ); QDV = (rC*Co) + (L/R); GDV = (Vin (rC*Co)) / PDV ; pl_1 = (-QDV/(2* PDV)) + (0 .5*((((QDV/PDV)^2)-(4/PDV))^0.5)); po_1 = complex(real(pl_1),imag(pl_1)); pl_2 = (-QDV/(2* PDV)) (0 .5*((((QDV/PDV)^2)-(4/PDV))^0.5)); po_2 = complex(real(pl_2),imag(pl_2)); zr_1 = (-1)/(rC*Co); Num_b3(j) = Num complex(0,(-1)*((wf(j))^3)); Num_b2(j) = Num ( (4/Tsw) (po_1+po_2) ) (-1) (((wf(j))^2)); Num_b1(j) = Num ((po_1 po_2)-(( 4/Tsw)*(po_1+po_2))) complex(0,wf(j)); Num_b0(j) = Num (4/Tsw) (po_1 po_2); Den_a3(j) = (D_A1 D_B1)* complex(0,(-1)*((wf(j))^3)); Den_a2(j) = ((D_A1*((4/Tsw)-(po_1+po_2))) + (D_C1 GDV) + (D_B1*(( 4/Tsw)+(po_1+po_2))))*((1)*((wf(j))^2)); Den_a1(j) = ( (D_A1 ((po_1 po_2)-((4/Tsw)* (po_1+po_2))))+ ((D_C1 GDV)*((4/Tsw)+zr_1)) (D_B1 ((po_1 po_2)+((4/Tsw)*( po_1+po_2)))) ) complex(0,wf(j));

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163 Den_a0(j) = (D_A1*((4/Tsw)*(po_1*po_2))) + ((D_C1 GDV)*((4/Tsw)*zr_1)) + (D_B1*((4/Tsw)*(po_1*po_2))) ; d_vcmd_num(j) = Num_b3(j) + Num_b2(j) + Num_b1(j) + Num_b0(j) ; d_vcmd_den(j) = Den_a3(j) + Den_a2(j) + Den_a1(j) + Den_a0(j) ; samp_hold1(j) = complex(1,((-1)*wf(j )*(Tsw/4))) /complex(1,(wf(j)*(Tsw/4))); d_vcmd_trfn(j) = ( d_vcmd_num(j) / d_vcmd_den(j) ) ; d_vcmd_mag(j) = 20*log10(d_vcmd_trfn(j)) ; d_vcmd_phase(j) = ( ((angle(d_vcmd_trfn(j))) (180/pi)) ) ; % Duty ratio to output function gvd_num(j) = complex(Vin,(wf(j)*rC*Co)); gvd_den(j) = complex((1-(((wf(j))^2)*PDV)),(wf(j)*QDV)); gvd_trfn(j) = gvd_num(j) / gvd_den(j); gvd_mag(j)=20*log10(gvd_trfn(j)); gvd_phase(j)=angle(gvd_trfn(j)) *(180/pi); % Command to Output transfer function vo_vcmd_mag(j) = gvd_mag(j) + d_vcmd_mag(j); vo_vcmd_phase(j) = gvd_phase(j) + d_vcmd_phase(j) ; end

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164 LIST OF REFERENCES [1] K.Yao, Y. Ren, F.C. Lee, “Critical bandwid th for the load transient response of voltage regulator modules,” IEEE Trans. Power Electron., vol. 19, pp 1454-1461, November 2004. [2] Intel document, “VRM9.1 DC-DC convert er design guidelines,” Order number: 298645001, January 2002. [3] P.T. Krein, Elements of Power Electronics. New York: Oxford University Press, 1998. [4] A. Prodic, D. Maksimovic, R.W. Ericson, “Design and Implementation of a digital PWM controller for a high-frequency switc hing DC-DC power converter,” in Proc. IEEE IECON, 2001, vol. 2, pp. 893-898. [5] A.M. Wu, J.X. Xiao, D. Markovic, S.R. Sanders, “Digital PWM c ontrol: Application in Voltage Regulation Modules,” in Proc. IEEE PESC, 1999, vol.1, 1999, pp. 77-83. [6] A.V. Peterchev, S.R. Sanders, “Quantiza tion resolution and limit cycling in digitally controlled PWM converters,” IEEE Trans. Power Electron. vol. 18, pp 301-308, January 2003. [7] A. Syed, E. Ahmed, D. Maksimovic, E. Alarcon, “Digital pulse width modulator architectures,” in Proc. IEEE PESC, 2004, vol. 6, pp. 4689-4695. [8] B.J Patella, A. Prodic, A. Zirger, D. Maksim ovic, “High frequency digital controller IC for DC/DC converters,” in Proc. IEEE APEC, 2002, vol. 1, pp. 374-380. [9] A. Prodic, D. Maksimovic, R.W. Erickson, “D igital controller chip set for isolated DC power supplies,” in Proc. IEEE APEC, 2003, vol. 2, pp. 866-872. [10] A. Dancy, A. Chandrakasan, “A reconfi gurable dual output low power digital PWM power converter,” in Proc. IEEE Int. Symp. on Low Power Elect. and Design, 1998, pp. 191-196. [11] J.X. Xiao, A.V. Peterchev, S.R. Sanders, “Architecture and IC impl ementation of a digital VRM controller,” in Proc. IEEE PESC, 2001, vol. 1, pp. 38-47. [12] G. Y. Wei, M. Horowitz, “ A low pow er switching power supply for self-clocked systems,” in Proc. IEEE Intl Symposium on Low Power Elect. and Design, 1996, pp 313317. [13] W. Gu, W. Qiu, W. Wu, I. Batarseh, “A multiphase DC/DC conve rter with hysteretic voltage control and cu rrent sharing,” in Proc. IEEE APEC, 2002, vol. 2, pp. 670-674. [14] W. Zhang, G. Feng, Y.F. Liu, B. Wu, “DSP implementation of predictive control strategy for power factor correction (PFC),” in Proc. IEEE APEC, 2004, vol. 1, pp. 67-73.

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PAGE 170

170 BIOGRAPHICAL SKETCH Bharath Balaji Kannan was born on February 18 1980, in Chennai, India. He did his schooling in SBOA School and J unior College and D.A.V Matr iculation Higher Secondary School. He received his bachelor’s degree in elect rical and electronics engineering from College of Engineering, Anna University, Guindy. He comp leted his master’s in el ectrical and computer engineering at the University of Florida during the summer of 2003. He has been pursuing his doctoral research in digi tal control of power converters at th e University of Florida since August 2003. His research interests in clude mixed signal IC design w ith focus on analog/digital PWM control of power converters. He is also interest ed in the field of dig ital signal processing and computer networks. His hobbies include listening to music, drawing and painting.


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Title: Digital Synthetic Ripple Modulator for a DC-DC Converter
Physical Description: Mixed Material
Copyright Date: 2008

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Table of Contents
    Title Page
        Page 1
        Page 2
    Dedication
        Page 3
    Acknowledgement
        Page 4
    Table of Contents
        Page 5
        Page 6
        Page 7
    List of Tables
        Page 8
    List of Figures
        Page 9
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        Page 12
        Page 13
    List of symbols and acronyms
        Page 14
        Page 15
    Abstract
        Page 16
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    Introduction
        Page 18
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    Digital pulse width modulator
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    Digital synthetic ripple modulator
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    Design and experimental implementation of digital synthetic ripple modulator
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    Testing and analysis of digital SRM controlled buck converter
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    Conclusion
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    Appendix A: Matlab functions
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    References
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    Biographical sketch
        Page 170
Full Text





DIGITAL SYNTHETIC RIPPLE MODULATOR FOR A DC-DC CONVERTER


By

BHARATH BALAJI KANNAN
















A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2006
































Copyright 2006

by

Bharath Balaji Kannan

































To the Almighty God.









ACKNOWLEDGMENTS

I would like to sincerely express my gratitude and appreciation for my advisor, Dr. Khai

D.T. Ngo, for his constant encouragement and thought-provoking ideas that helped me in the

development of this dissertation. I would also like to thank the Department of Electrical and

Computer Engineering at the University of Florida, for providing me the necessary financial

support. I would like to thank Dr. John G. Harris and Dr. William R. Eisenstadt for their valuable

suggestions and for being on my dissertation committee. I would also like to thank Dr. Jih-Kwon

Peir for serving as my external committee member.

I would also like to take this opportunity to thank Dr. Robert M. Fox, who helped me to

acquire the skills in the field of integrated circuit design. I am also grateful to Dr. Jacob Hammer

for helping me to secure the departmental financial assistance towards my research. I would also

like to express my gratitude and appreciation to the College of Engineering, Anna University,

India, for providing an ambient environment to study and learn.

Last but not least, I would like to thank my parents, sister, brother-in-law, and my

resourceful friends who gave me the necessary impetus towards the development of this

dissertation.









TABLE OF CONTENTS



A C K N O W L E D G M E N T S ..............................................................................................................4

L IST O F T A B L E S ......................................................................................................... ........ .. 8

LIST OF FIGURES ............................................. ............ ...........................9

LIST OF SYM BOLS AND ACRONYM N S............................................................ ................ 14

A B S T R A C T .......................................................................................................... ..................... 16

CHAPTER

1 INTRODUCTION .................................. .. ........... ............................. 18

1.1 Conventional Carrier Signal G generation ............................................. ..... ................ 19
1.2 Carrier Signals in Digitally Controlled DC-DC Converters.......................................21

2 DIGITAL PULSE W IDTH M ODULATOR ..................................................... ................ 22

2.1 DPWM Modules in Digitally Controlled DC-DC Converter....................22
2.2 DPWM Modules in Digitally Controlled DC-AC Inverter ..... ................24

3 DIGITAL SYNTHETIC RIPPLE MODULATOR...........................................................34

3.1 D esign C concept of D SR M ............................................. ........................... ................ 34
3.1.1 Digital Inverse Tim ing Generator ........................ .... ................ 35
3.1.2 Extraction of Digital Timing Generator Parameters ........................................37
3.1.3. Scaling Approaches .................................................................. 39
3.1.4 Successive A ccum ulation .................................................................... ............... 42
3.2 Architecture of Digital Synthetic Ripple Modulator ...................................................44
3.3 Application Illustration of the Digital Synthetic Ripple Modulator...............................47
3.3.1 Design of Buck Converter-Output LC filter............... ..................................... 49
3.3.2 Design of Digital Synthetic Ripple M odulator.................................. ................ 50
3.3.2.1 D igital tim ing generator ....................... ............................................... 50
3.3.2.2 O utput voltage A /D resolution .............................................. .................. 53
3.4 Modeling and Simulation of Digital SRM Based Buck Converter ................55
3.4.1 M odeling of PW M Sw itch .......................................... ....................... ............... 55
3.4.2 M modeling of Output LC filter ......................................................... 56
3.4.3 M odeling of D igital SRM C ontroller ................................................... ............... 56
3.4.4 Simulation of Adaptive Voltage Position for Digital SRM based Buck
C o n v e rte r ............... ....... ..... .................................................................................... 5 9
3.4.5 Modeling of Dynamics involved in the Digital SRM Controller for a Buck
C o n v erter..................................................................................................... ........ .. 6 5









3.4.6 Design Methodology for Digital SRM Controlling the Synchronous Buck
C o n v e rte r.......................................... ....... .... ................................................. ......... 6 9
3.5 Performance Analysis of Digital Synthetic Ripple Modulator .........................................72
3.5.1 Open-loop Linear Control of Controlled Variable with Command Signal ............72
3.5.2 Influence of Component Variations on the Digital SRM Performance ............ 72
3.5.3 Open-loop Dynamic Response of the Digital SRM Controlled Buck
C o n v erter.......................... ....... .... ............................................................... ......... 7 3
3.6 Advantages of Digital Synthetic Ripple M odulator .................................... ................ 73

4 DESIGN AND EXPERIMENTAL IMPLEMENTATION OF DIGITAL SYNTHETIC
R IPPL E M O D U L A T O R ................................................... ............................................. 106

4.1 Experimental Implementation of Synchronous Buck Converter.............................. 106
4.1.1 Power M OSFET Design and Selection....... .......... ...................................... 107
4.1.2 Output Filter Inductor Selection...... .......... ........ ..................... 108
4.1.3 Output Filter Capacitor Selection...... .... ...... ..................... 109
4.1.4 Synchronous Buck G ate driver................... ................................................. 109
4.2 Experimental Implementation of Signal Conditioning Circuit.................................... 109
4.3 Hardware Implementation of DC-DC Buck Converter and A/D Signal Conditioning
C ircu it................................................... .... ........................................................... ........ 1 14
4.4 Experimental Implementation of the Digital Timing Generator ..................................114
4.5 Experimental Implementation of Digital Synthetic Ripple Modulator Controlling the
D C -D C B uck C onverter.................................................. ............................................ 115

5 TESTING AND ANALYSIS OF DIGITAL SRM CONTROLLED BUCK
CONVERTER ...................................... ............ ............................. 132

5.1 DC-DC Buck Converter Testing and Measurement..............................................132
5.2 Signal Conditioning Circuit Testing and Measurement ............................................134
5.3 Digital Synthetic Ripple Modulator Controlled Buck Converter Testing and
M easurem ent .............................................. ... ... ......................... 135
5.3.1 D igital Inverse Tim ing G enerator Testing ................................... ..................... 137
5.3.2 Command to Output Transfer Characteristic of Digital Synthetic Ripple
M odulator Controlled Buck Converter............................................. ................... 138
5.3.3 Load transient response Step-Response of Digital Synthetic Ripple Modulator
C controlled B uck C onverter.............................................. .................... ............... 138
5.3.4 Variation of Switching Frequency Based on Load Conditions......................... 139
5.4 Future D irectives for R research ................. .......................................................... 139

6 C O N CLU SIO N ........................... ... ................................... ...... 158

6 .1 Su m m ary ...................................................................................................... ......... 158
6 .2 F future W ork .................................................................................................. .......... 158

APPENDIX

M A T L A B F U N C T IO N S ....................................................... ................................................ 160









L IST O F R E F E R E N C E S ....................................................... ................................................ 164

B IO G R A PH IC A L SK E T C H .................................................... ............................................. 170









LIST OF TABLES


Table page

2-1 D PW M architecture realizations .................. ............................................................... 27

2-2. Hardware/FPGA realization of DPWM module in DC-DC converters ..............................28

2-3. DSP/Micro-controller realization of DPWM module in DC-DC converters ........................29

2-4. Hardware/FPGA realization of DC-AC PWM inverter control ....................30

2-5. DSP/Micro-controller realization of DC-AC PWM inverter control................ 31

3-1. Sequential steps involved in Step Value generation......................................... ................ 74

3-2. D C -D C converter specifications........................................... ......................... ................ 74

3-3. Scaling factor A pproxim nations ...................................................................... ................ 74

4-1. Comparison of time duration from simulations....................................... 117

4-2 Bill of materials for the synchronous buck DC-DC converter.................. ...................117

4-3 Bill of materials for the A/D converter and signal conditioning circuit .............................117

4-4 Bill of materials for the FPGA based digital controller...... ......................................... 118

5-1 Equipm ent list and specifications ...................................... ........................ ................ 140









LIST OF FIGURES


Figure page

2-1. Generic architecture of digitally controlled DC-DC switching converter..........................32

2-2. Duty ratio based on hybrid DPWM (NDPWM=8bits) ...................................................... 32

2-3. Architecture of PWM inverter based 3-0 induction motor drive...................33

3-1. Conceptual implementation of digital duty ratio generation...........................................75

3-2. Inductor current indicating the current ripple and time intervals along with the buck
converter inductor voltage ..................... ................................................................. 75

3-3. Scaling approaches for step value generation................................................... ................ 76

3-4. Timing error performance for various scaling factor approximations used in step value
g en eratio n ......................................................................................................... ....... .. 7 6

3-5. Simulation analysis indicating percentage timing error based on binary multiplication
scaling and A /D gain-block scaling ..................................... ...................... ................ 77

3-6. Simulation analysis indicating percentage timing error based on binary multiplication
scaling and A /D gain-block scaling ..................................... ...................... ................ 78

3-7. Generic architecture of a system controlled by digital synthetic ripple modulator ............79

3-8. Generic synthetic ripple modulation showing the hysteretic thresholds, command
variable and P W M signal .. ............................................................................ ............... 79

3-9. Architecture of digital SRM controlled synchronous buck DC-DC converter. ....................80

3-10. Inductor current waveform during load current step-up and steady-down transient........... 81

3-11. Simulation analysis of percentage error for various scaling factor approximations ........... 81

3-12. Transfer characteristic of the A/D converter sampling the error voltage between
output and com m and voltage .......................................... .......................... ................ 82

3-13. Sim ulink m odel of the PW M sw itch ........................................ ...................... ............... 82

3-14. Sim ulink m odel of buck L C filter......................................... ....................... ................ 83

3-15. Simulink model of the A/D converter ......................................................... 83

3-16. Sim ulink m odel of digital tim ing generator ................................................... ................ 84









3-17. Block diagram depicting the Simulink model of digital SRM controlled buck
co n v erter .......................................................................................................... ........ .. 8 5

3-18. Simulation outputs of the synchronous buck converter using MATLAB/Simulink for
V cm d= l1.3V ..................................................................................................... ........ .. 86

3-19. Simulation outputs indicating the step value, integer value and VPWM signal of the
digital timing generator...................... ............ ............................. 87

3-20. Comparison between on-time/off-time generated based on theoretical equations and
sim ulated synthetic ripple m odulator ............................................................ ................ 88

3-21. Percentage error between digital timing generator and theoretical expression using
sim u latio n an aly sis ............................................................................................................. 8 9

3-22. Voltage change across the output capacitor during a step-down load transient...............90

3-23. Integer value, modified hysteretic count, VPWM, and Error binary for AVP
im plem entation in digital SR M ........................................................................ ................ 9 1

3-24. Integer value, modified hysteretic count, VPWM, and Error binary for AVP
im plem entation in digital SR M ........................................................................ ................ 92

3-25. Inductor current and AVP of the output voltage based on optimal AVP design for the
load step -u p tran sent .................................................. .............................................. 93

3-26. Inductor current and AVP of the output voltage based on optimal AVP design for load
step -d ow n tran sent ............................................................................................................ 94

3-27. Inductor current and AVP of the output voltage Vcmd reaches higher level before
the peaking of V out (V out m ax) ........................................ ....................... ............... 95

3-28. Inductor current and AVP of the output voltage Vcmd reaches higher level before
the peaking of V out (V out m ax) ........................................ ....................... ................ 96

3-29. Inductor current, VPWM, and AVP of the output voltage Vcmd reaches higher level
after the peaking of V out (V out m ax).......................................................... ................ 97

3-30. Modulator output, Error binary, and AVP of the output voltage Vcmd reaches
higher level after the peaking of V out .......................................................... ................ 98

3-31. Dynamic system model of the digital SRM controlled synchronous buck converter .........99

3-32. Magnitude and phase of command (vcmd) to duty ratio (d) transfer function................100

3-33. Magnitude and phase of duty ratio (d) to output voltage (vout) transfer function ..........101

3-34. Magnitude and phase of command (vcmd) to output voltage (vout) transfer function..... 102









3-35. Plot indicating the linear control of output voltage with command voltage based on
M A TLAB /Sim ulink sim ulation..................................... ....................... ................ 103

3-36. Simulation plot indicating the effect of component variations on the performance of
th e d ig ital S R M ............................................................................................................... 10 4

3-37. Simulation of open-loop load transient response of digital SRM controlled buck
converter with Vcmd=1.5 V and load step of 5A to 10A in 100 ns (50 A/as) ................105

4-1. Schematic of synchronous buck DC-DC converter...... .... ..................................... 119

4-2. Current through the UFET in a switching cycle............... ........................ 119

4-3. Schematic of signal conditioning circuit for the A/D converter with inclusion of the
sc a lin g fa cto r ................................................................................................................. ... 12 0

4-4. Block diagram of the experimental digital synthetic ripple modulator indicating the
register enable and tim ing signals......................................................... ............... 121

4-5. Frequency response of the signal conditioning circuit amplifier ..................................122

4-6. Phase voltage, converter output voltage, and signal conditioning circuit scaled voltages
fo r V cm 1 .5 V ............................................................................................................... ... 12 3

4-7. Inductor voltages at the input of the A/D converter for a duty cycle of D=0.325 and
Vcm, l.5V ........................................................................ ...... 124

4-8. Buck converter output voltages, error voltage and output A/D input voltage for
Vcm l .5V ........................................................................ ...... 125

4-9. Gerber file indicating the top layer of the PCB board...............................................126

4-10. Gerber file indicating the bottom layer of the PCB board...................... ...................127

4-11. Photograph of the manufactured PCB board indicating the buck converter and the
signal conditioning circuit. .................................................................... ............... 128

4-12. Timing signals and A/D converter input voltages for the signal conditioning circuit ......129

4-13. ALTERA board based digital synthetic ripple modulator outputs indicating VPWM
outputs for step values (100)o0 and (42)0o................................... 130

4-14. Experimental implementation of DSRM controlled buck converter system.......... 131

5-1. Experimental test-bed setup used for characterizing the DC-DC synchronous buck
co n v erter ........................................................................................................ ........ .. 14 1

5-2. Phase node voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3.............141









5-3. Output voltage (CH1) and PWM input (CH2) for Vin=5V and D=0.3..............................142

5-4. PWM Input (CH2) and high-side gate drive (CH1) for Vin=5V and D=0.3 .....................142

5-5. PWM input (CH2) and Vphase (CH1) for Vin=5V and D=0.3 ............... ................143

5-6. PWM input (CH2) and low-side gate drive (CH1) for Vin=5V and D=0.3 ......................143

5-7. Phase node voltage (CH1) and low-side gate drive (CH4) for Vin=5V and D=0.3..........144

5-8. Phase node voltage (CH1), output voltage (CH2) and inductor voltage (Math2) for
Vin=5V and D=0.3 ........................ .. .......... ............................... 144

5-9. Vphase_posl (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25 ......145

5-10. Vout negl (CH1) and PWM input (CH4) for Vin=5V, Vcmd=1.38V, and D=0.25........145

5-11. VLpos_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.25 ....................146

5-12. VLneg_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.25....................146

5-13. Verr_adc_input (CH1) and PWM input (CH4) for Vin=5V and D=0.3 .........................147

5-14. VLpos_adc_input (CH3), register-enable blnk_pos (CH4) and VPWM from digital
modulator (CH1) for Vin=5V and Vcmd=1.38 ....... ... ...................................... 147

5-15. VLneg_adc_input (CH3), register-enable blnk neg (CH4) and VPWM from digital
modulator (CH 1) for Vin=5V and Vcmd=1.38 ....... .......... ..................................... 148

5-16. A/D converter output for inductor voltage during on-time-VLPOS [7-0] (CH3),
register enable-blnk_pos (CH4), and VPWM (CH1). A) VLPOSO (LSB). B)
VLPOS1. C) VLPOS2. D) VLPOS3. E) VLPOS4. F) VLPOS5. G) VLPOS6. H)
V L P O S 7 (M S B ) ............................................................................................................... 14 9

5-17. A/D converter output for inductor voltage during off-time-VLNEG [7-0] (CH3),
register enable-blnk neg (CH4), and VPWM (CH1). A) VLNEGO (LSB). B)
VLNEG1. C) VLNEG2. D) VLNEG3. E) VLNEG4. sF) VLNEG5. G) VLNEG6. H)
V L N E G 7 (M S B ) .............................................................................................................. 15 0

5-18. A/D output for error voltage between Vcmd and Vout VERRAD [7-0] (CH3),
register enable-blnk neg (CH4), and VPWM (CH1). A) VERRADO (LSB). B)
VERRAD1. C) VERRAD2. D) VERRAD3. E) VERRAD4. F) VERRAD5. G)
V ER R A D 6. H ) V ER R A D 7 (M SB ). ................................................................................151

5-19. Verr_adc_input (CH1) and VPWM from digital modulator (CH4) for Vin=5V and
V c m d = 1 .3 8 ................................................................................................................... ... 1 5 2

5-20. Timing generation comparison based on simulation, theory and experimental digital
tim ing generation approach....................................... .......................... ............... 152









5-21. Percentage timing error based on experimental digital timing generation approach ........ 153

5-22. Linear plot of Vout Vs Vcmd for Vin=4.5V and load resistance RL=1 ........................ 153

5-23. Linear plot of Vout Vs Vcmd for Vin=4.96V and load resistance RL=1Q ...................... 154

5-24. Linear plot of Vout Vs Vcmd for Vin=4.17V and load resistance RL=1 ...................... 154

5-25. Linear plot of Vout Vs Vcmd for Vin=5V and load resistance RL=0.67Q ....................155

5-26. Linear plot of Vout Vs Vcmd for Vin=4.17V and load resistance RL=0.67Q ...............155

5-27. Load transient response of the digital SRM Vout (CH2), inductor current (CH4) and
load current step (CH3)................................ ............................. 156

5-28. Variation of switching frequency with respect to load current for Vin=3.75V, 4.00V
an d 4 .3 5V ...................................................................................................... ......... 157









LIST OF SYMBOLS AND ACRONYMNS

A/D Analog to Digital

D Steady-state duty ratio of the converter

DLL Delay-locked loop

DPWM Digital Pulse Width Modulator

DSRM Digital synthetic ripple modulator

FPGA Field-programmable gate array

Nc Number of bits for the hysteretic count resolution

NL Number of bits for the sampled inductor voltage

NQ(,I) Sampled converter/inverter parameter

Nsc Scaling factor used in inverse timing generation

Nsc AD Ratio of scaling factor used in the signal conditioning circuit

PCB Printed circuit board

PFC Power factor correction

q(V,I) Control input for the inverse timing generator

qsTEP Step value used in the accumulator

tCLK Time period of the clock used for successive accumulation

tOFF Off-time of the upper MOSFET switch

toN On-time of the upper MOSFET switch

Ts Switching time period

VCDL Voltage-controlled delay line

Verrq LSB equivalent of the quantized error voltage between output and
command voltage









VLbin Binary equivalent of the quantized inductor voltage

VLq LSB equivalent of the quantized inductor voltage

VRM Voltage regulator module

VOUT Output voltage of the buck converter

Error Percentage timing error metric for the timing generator

AIL Peak-peak inductor current ripple









Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

DIGITAL SYNTHETIC RIPPLE MODULATOR FOR A DC-DC CONVERTER

By

Bharath Balaji Kannan

December 2006

Chair: Khai D.T. Ngo
Cochair: John G. Harris
Major Department: Electrical and Computer Engineering

Voltage regulator modules (VRMs) powering the future microprocessors are required to

meet the stringent specifications on the core voltage ripple and voltage regulation. These

specifications are driven by the microprocessor's higher di/dt requirements and the need to

operate at a lower supply voltage for reduced power consumption. The conventional VRMs

resort to multi-phase pulse width modulation (PWM) control schemes to cater to the high current

demands and provide balanced load current sharing. The control schemes also involve a

combination of voltage-mode and current-mode or current-mode and hysteretic-mode control.

Thus, these schemes add to the cost and complexity of the VRM.

Synthetic ripple modulation (SRM) involves the generation of an artificial ripple,

synthesized from a converter parameter which is then bonded to the output voltage of the VRM.

This artificial scheme of carrier signal generation for PWM control enables voltage-hysteretic

modulation to be achieved in the low-voltage VRM modules for microprocessors. With the

inherent low-voltage ripple exhibited by a low-voltage VRM that is insufficient for conventional

hysteretic operation, the SRM scheme on the other hand provides sufficient ripple for the PWM

carrier signal. The SRM scheme blends in the advantages of current-mode control and hysteretic

control providing superior transient performance.









The introduction of digital control to the PWM control of switching power converters has

gained popularity owing to its benefits of lower sensitivity to process and mismatch variations,

programmability, and the reduction of passive components used in tuning. The digital control

based SRM generates the duty ratio with inverse relation to a sampled converter parameter. The

on-time and off-time duration of the switches forming the duty ratio is generated by successively

accumulating the sampled inductor voltage. The accumulated output forming the synthetic ripple

is added to the error between output voltage and reference voltage. The carrier signal thus

generated is modulated between the higher and lower hysteretic thresholds, thus generating the

duty ratio. A unique scaling process also allows the implementation of programmable switching

frequency for converters. The major contributions of the dissertation in the field of engineering

are given below.

* Digital synthetic ripple modulator architecture for applications in power electronics.
* Digital inverse timing generator with wide dynamic range and programmable frequency.

The digital SRM scheme is verified experimentally in the control of a synchronous buck

DC-DC converter. Experimental data are provided to delineate the potential advantages such as

inverse timing generation, programmable switching frequency, linear control of output variable

with reference variable under open-loop conditions, natural feed-forward control, and superior

transient performance.









CHAPTER 1
INTRODUCTION

Low-voltage power supplies powering future microprocessors are under constant pressure

to provide higher di/dt requirement. The core-voltages of current and future microprocessors are

on the order of 0.8-1.0V, enabling lower power consumption. The trend towards low-voltage

operation increases the burden on the switching regulators which are required to maintain a tight

tolerance on the core voltage. The allowed tolerance on the core voltage remains at a fixed

percentage of the supply voltage instead of an absolute value in volts. This indicates that as the

core voltages go down, the tolerance that the processors can handle also scales down

proportionately. It is also predicted that the load current requirements of these microprocessor

cores will increase up to 200A with dynamic current slew-rates on the order of 120A/ns [1-2].

These dynamic loads are tackled with point-of-load power supplies which derive their output

voltage from power conversion of existing 12V supply systems. The dynamic loads also present

stricter transient regulation requirements, thereby creating the need for the design of efficient and

enhanced power supply operation and control.

The dissertation focuses on the generation of carrier signals utilized in pulse width

modulation (PWM) control of converters/inverters with hysteretic mode of operation. The carrier

signals are derived from converter/inverter parameters such as inductor voltage, drain-source

voltage of power MOSFET, inductor current, and stator winding current. The carrier signal is

composed of the ripple associated with the variable to be controlled and a synthetic ripple

derived by filtering (analog approach integration or digital approach accumulation) a

converter parameter. Since the PWM control involves artificial carrier signal generation, the term

synthetic ripple modulation promptly applies. The superimposing of the controlled variable with

that of the synthetic ripple creates a significant amount of ripple similar to that exhibited in









conventional current mode control. The modulation strategy is theoretically validated with an

application involving the control of a DC-DC synchronous buck converter used as a switching

regulator for powering microprocessors. The tight tolerance required on the output voltage of the

switching regulator and the higher di/dt (120A/ns) requirement can be achieved with the

synthetic ripple modulation (SRM) technique. Since the SRM based control is a form of

hysteretic control modulating the controlled variable directly within a hysteretic band, superior

dynamic performance is inherently attained. The fact that the output voltage is bonded to a

synthetic ripple, resulting in a carrier signal with sufficient ripple for PWM operation, allows the

output voltage to be controlled directly and with the required tight tolerance.

The digital SRM (DSRM) scheme employed in the control of the buck converter also

involves a novel method for deriving the duty ratio, with the generated time-intervals inversely

related to a sampled converter parameter. The duty ratio generation scheme is based on a unique

scaling process and eliminates the need for a high clock frequency. The modulation scheme

utilizes the sampled inductor voltage, which is scaled and successively accumulated to generate

the synthetic ripple. The error in the output voltage when compared to a reference or command

voltage is added to the synthetic ripple resulting in the carrier signal for PWM operation. The

carrier signal is modulated between hysteretic limits, resulting in the required duty ratio. Since

the carrier signal involved in the PWM signal generation is derived from the converter

parameters in the SRM scheme, natural input feed-forward control is also attained. This enables

better rejection of line input disturbances.

1.1 Conventional Carrier Signal Generation

Conventional PWM control relies on three main control schemes, namely, voltage-mode

control, current-mode control and hysteretic control [3]. In voltage-mode control, the carrier

signal required for PWM signal generation is based on an external oscillator. The oscillator









providing the carrier signal is conventionally realized by charging or discharging a capacitor

using a constant current source. It suffers from the serious drawback of external component

variations and requires better matching between an on-chip current source and an external

capacitor. The transient performance of voltage-mode control is limited by the delays involved in

the compensation circuit forming the feed-back loop. The current-mode control counterpart

utilizes the inductor current ripple for the carrier signal. The commutation instants of the

MOSFET switches are based on the type of current-mode control, namely peak current-mode

control, average current-mode control, and valley current-mode control. Current-mode control

offers better transient performance when compared to voltage-mode control.

This tradeoff is made possible only with accurate current sensing employing a current

sense resistor or a current transformer. The advantage thus gained over the voltage-mode control

is offset by the additional loss in the resistor for higher load currents or by the cost and space

requirements of the current sense transformer.

In hysteretic control, the carrier signal is implicitly generated by regulating the desired

output variable within a hysteretic band centered about a reference. The hysteretic mode of

control provides fast load transient response, requires no feedback loop compensation, and no

input filter interaction problems when compared to voltage-mode or current-mode control. In

applications requiring the controlled parameter to be within a marginal hysteresis band, the

PWM comparator used in power switch commutation is required to exhibit high resolution and

fast response. One of the major drawbacks involved in the hysteretic mode of control is the

variation of the switching frequency, increasing the complexity involved in output filter design.

The artificial ripple superimposed onto the controlled variable in the discussed synthetic

ripple modulator is significant enough to eliminate the need for a high resolution PWM









comparator. The synthetic ripple modulator also blends in the advantages of hysteretic

modulation by virtue of the control variable being directly tracked by the PWM comparator.

1.2 Carrier Signals in Digitally Controlled DC-DC Converters

The conventional voltage/current-mode control based on analog approaches involves more

real-estate to accommodate for the external components like resistors, capacitors, current

transformer, current-sense resistor, etc. The introduction of digital control for DC-DC

converters/inverters offers a multitude of benefits like insensitivity to component and parameter

variations, better noise immunity, ease of programmability, reduced size and cost. An application

involving the digital control of microprocessor power supplies also offers the benefits of easier

VID code (Voltage Identification Code) integration, fault protection, programmed soft-start, the

inevitable features of modern-day voltage-regulator modules (VRM) [2].

Carrier signals for digital control of DC-DC systems are generated using a specific

module, namely the Digital Pulse Width Modulator (DPWM). The DPWMs are based on current

starved inverters, fast-clocked counter, tapped delay-lines, hybrid approach involving

multiplexer and delay-lines, and binary-weighted delay lines. The architectural realization and

implementation issues associated with the DPWM architectures are dealt with in chapter 2. The

list of symbols and acronyms used in the dissertation are outlined in Table 1-1.









CHAPTER 2
DIGITAL PULSE WIDTH MODULATOR

The digital pulse width modulator (DPWM) block in a digitally controlled power

converter/inverter generates the PWM pulse signal controlling the commutation instants of the

switches. A typical application involving a DC-DC converter relies on the control and regulation

of output voltage or the line/input current of the converter. Similarly a DC-AC inverter

application involves the control/regulation of stator current or inverter output voltage for the

speed control of motor-drives.

2.1 DPWM Modules in Digitally Controlled DC-DC Converter

The DPWM module in a DC/DC converter generates a discrete set of duty ratio values

based on a digital command input word from a discrete-time compensator. The carrier signal

involved in the PWM pulse signal generation is implicitly created by the DPWM module. The

DPWM module quantizes the switching time period into a number of discrete time slots. A

particular time slot is selected based on the digital duty command input (d[n]) [4-5]. The

selection of a particular time slot and the time duration elapsed during the slot selection

determines the commutation instant of the switch and the duty ratio respectively. The carrier

signal information is embedded in the architecture forming the DPWM module. The generic

architecture of a digitally controlled switching DC-DC converter is outlined in Figure 2-1. The

discrete set of duty ratio values involved in a digitally controlled DC/DC converter imposes

restrictions on the set of steady-state values taken by the output voltage. The resolution of the

DPWM module should be higher than that of the output voltage A/D resolution to avoid limit-

cycle oscillations [6].









The DPWM module serves as a D/A converter interfacing the digital control block with

that of the switching converter. Several realizations of the DPWM module based on linearity,

high-frequency capability, area, complexity and power consumption are outlined in literature [7-

11]. A summary of the DPWM realizations are shown in Table 2-1.

Due to the profound developments in Field-programmable gate-array (FPGA) and the DSP

processors sector of the semiconductor industry, the realization of such DPWM modules is

becoming much easier. A comparative listing of the current approaches for the realization of

DPWM modules in DC-DC converters based on FPGA/IC-level and DSP implementation is

indicated in Table 2-2 and Table 2-3 respectively. The approaches are also distinguished based

on voltage-mode, current-mode and hysteretic control of DC-DC converters. The set of duty

ratio generated from a hybrid DPWM [8] involving multiplexers and counters is shown in Figure

2-2. Based on the characteristic in Figure 2-2, a linear relation between the digital command

word and the output duty ratio is sought in the digital control schemes which are based on Figure

2-1.

The realizations based on IC-level/FPGA implementation are tailored to a particular

application resulting in restricted programmability of the switching frequency. The linearity

between the duty-ratio command input and the PWM pulse signal exhibited by silicon-based

DPWM modules relies on careful layout techniques and better matching between the delay cells

[7]. The DPWMs based on tapped delay-lines are susceptible to drifts in the switching frequency,

due to process and temperature variations in individual delay cells. The power supply ripple-

rejection performance necessitates differential delay cell designs [11]. The DPWMs realized

from the counter/comparator scheme suffers from the serious drawback of higher power

consumption. The need for higher resolution in low-voltage VRMs, leads to higher clock









frequency requirement in the range of 200-800MHz attributing to higher power consumption

[12].

DC-DC converters employed in low-voltage VRM's are tied with stricter static and

transient specifications with regulation tolerance less than 5%. This demands a higher resolution

for the A/D converter sampling the output voltage. It also necessitates a lesser conversion time

for the A/D converter when switching frequencies on the order of MHz are targeted in digitally

controlled power supplies. This has become an inevitable requirement since higher switching

frequencies allow smaller values for output filter components, reducing their size dramatically.

DSP processor based realization of VRMs switched at higher frequency [13-16] results in the

requirement of lesser computation time for the duty-ratio to achieve near one-cycle control [17].

This proves to be an expensive solution when DSPs with higher processing power are targeted.

The VRMs utilizing DSPs and based on the architecture of Figure 2-1 cannot accurately track

component variations in the buck output LC filter.

2.2 DPWM Modules in Digitally Controlled DC-AC Inverter

The closed-loop regulated DC-AC PWM inverters are widely employed in programmable

ac power sources, uninterruptible power supplies and induction motor drives [18-21]. The

architecture of a typical motor drive application is illustrated in Figure 2-3. In a typical motor

drive application, the control strategy relies on comparing the stator current or the inverter output

voltage with a desired reference to maintain regulation and thereby control the speed of the drive.

In hysteretic control, the controlled variable is regulated within a hysteretic band [22-27]. The

comparative listing of the implementation of PWM inverter control, utilizing FPGA and DSP

processors are outlined in Table 2-4 and Table 2-5 respectively.

The DSP processor based current hysteretic control of PWM inverter in [22] and [24],

relies on continuous stator current sensing and sampling. The sampled current value is compared









with predefined upper and lower limits stored in registers. The digitized stator current value is

updated at every sampling instant of the A/D converter. If the sampling frequency is too low, it

can lead to current overshoot or undershoot, deviating from the hysteretic band. This necessitates

a higher sampling frequency, thereby increasing the cost and power consumption.

The various control and implementation strategy of DC-DC converters and DC-AC

inverters discussed above determine the static and dynamic performance. The static performance

is mostly met by the aforementioned methods, while the transient performance is limited by the

delays involved in sampling and processing. The computation time involved in the various

digital blocks restrict the maximum switching frequency [28-30], since a portion of the switching

time period is to be used for the housekeeping operations. The dynamic characteristics of

hysteretic-mode of control are superior when compared to voltage/current-mode control [31],

while it is dependent on the hysteresis band employed. A wider hystereis band for the

modulation can alleviate the expensive requirements of faster and higher resolution of digital

comparators. On the other hand a wider hysteresis band based modulation may not be a viable

solution for low-voltage VRMs (DC-DC converter), where output voltage ripple requirements on

the order of 10-20mV are desired.

Hence a modulation strategy that can offer the dynamic performance of hysteretic mode of

operation while employing significant ripple as that of current-mode control and without the

need for current sensing is desired. A good linearity between the controlled variable and a

command reference under open-loop operation can prove to be desirable characteristic with

respect to control strategy implementation.

These requirements paved the way for synthetic ripple modulation, wherein the controlled

variable is bonded to any ac waveform derived from the converter or the inverter, to create a









significant amount of ripple. This allows the controlled variable to be regulated with very less

ripple. The synthetic ripple composed of the controlled variable and the ac waveform is

favorable for hysteretic mode of control to reap the benefit of superior dynamic performance.

The design, modeling, simulation, and implementation of the synthetic ripple modulator establish

the focus of the remaining chapters.









Table 2-1 DPWM architecture realizations
DPWM architecture Parameters
Complexity Linearity Area
Fast-clock counter approach Requires fast- Good 1 mm x 1 mm
[12] clock
flk 2NDPWM f
Tapped delay-line PWM [11]
Externally imposed clock-Open External Poor 0.75 mm x 1.2 mm
loop oscillator, delay-
cell variations
Delay cell based closed loop 2N : 1 MUX Poor
Hybrid counter /Tapped delay Tradeoff power Good 0.25 mm x 1 mm
line [8] for better THD
Binary-weighted delay line Requires better- Poor
matching of
delay between
cells
Segmented DPWM architecture Requires 2N : 1 Moderate 0.0675mm2
MUX and
thermometer
coding









Table 2-2. Hardware/FPGA realization of DPWM module in DC-DC converters
Digital control
Hardware/
Hardware Application DC-DC converters
FPGA
Implementation
Comparison Voltage-mode control Hysteretic control
Parameters
Reference [Chandraksan98 [Maksimovic [Rinne04] [Sanders01] [Yau04]
] 02]
Silicon area 3.2mm*2.8mm lmm2 <2.7k gates 3.2mm*2.8mm N/A
Power
consumption 10_W
Clock speed 2.5MHz 8MHz 35MHz-145MHz 5MHz 8MHz
Obit -Hybrid 8bit -Hybrid
Architecture MXCounter delay- 6-12bit VCDL/DLL 8-bit Ring Osc/MUX ALTERA
Architecture MUX/Counter
line/counter DPWM DPWM EPM7064SLC44
DPWMDPWM
Application Buck VRM Buck converter Buck converter Buck VRM Forward converter
Multi-Phase
Multi-Phase N/A N/A 4-PWM signals 4-phase VRM N/A
control
Programmable
switching 330kHz 1MHz 100kHz-15MHz 100kHz 180kHz-200kHz
frequency
Features Low-power Novel delay- Programmable Passive current Ultra-fast transient response
line A/D DPWM sharing









Table 2-3. DSP/Micro-controller realization of DPWM module in DC-DC converters
DSP/Micro-
controller Application DC-DC converters
Implementation
Comparison Voltage/Current-mode control Hysteretic control
Parameters
Reference [Zhang04] [Maksimovic01] [Erickson03] [Batarseh02]
Processor engine 16-bit fixed point 16-bit ADSP-2171 ADMC401 TMS320LF2407
DSP
Instruction cycle 40MHz 38.5ns 26MIPS 26MHz 33ns
parameters
8 channel ADS807
ADC 10-bit ADC 8 channel 8-channel 12bit ADS807
12bit 12-bit 53MHz
Hysteretic N/A N/A N/A + 10mV(steady-state)
window +20mV(transient)
Predictive current control
Predictive PFC (CCM/DCM) Multi-phase interleaved
Features 8-bit DPWM module
control Constant ON time current-sharing
Line current THD = 2.8%
Multi-Phase
Multi-Phase N/A N/A N/A 4-phase
control
Switching 160kHz 1MHz 120kHz- 190kHz
frequency _________









Table 2-4. Hardware/FPGA realization of DC-AC PWM inverter control
Digital control
Hardware
Hardware Application DC-AC inverters
FPGA
Implementation
Comparison Voltage/Current-mode control Hysteretic control
Parameters
Reference [Yokoyama04] [Tzou99] [Guinjoan03] [Betz99]
ALTERA ALTERA
FPGA/Hardware atix Xilinx XC4005 Xilinx XC4010E-3-PC84 LEX K
Stratix 1S25 FLEX10K50
245 CLB(Config.Logic
Silicon area/ 500k gates 5000 logic gates,196 CLB, 112 Blocks)
<500k gates 1204 Logic cells
Number of gates IOB 30 IOB( I/O blocks)
84 Flip-flops
Clock speed 80MHz 8MHz 6MHz 10MHz
Dead-beat control law based Counter/Comparator
Architecture on multiplication and Counter/Comparator/Timer 8-b DPWM /Timer PWM
additions PWM generator Counter/Comparator generator
Multi-Phase 3-phase control PWM 3-phase PWM inverter control N/A 3-phase PWM
control inverter control inverter control
Programmable
switching 20kHz 31.25kHz 20kHz-40kHz 2.9kHz
frequency









Table 2-5. DSP/Micro-controller realization of DC-AC PWM inverter control
DSP/Micro-
controller Application DC-AC inverters
Implementation
Comparison Voltage/Current-mode control Hysteretic control
Parameters
Reference [Tzou95] [Toliyat04] [Mattavelli04] [Mattavelli00] [Round97]
Processor engine TMS320C14 TMS320C50/FLEX6000 TMS320F2812 TMS320F240 TMS320C30
Instruction cycle 160ns 50ns 6.67ns 50ns
parameters
12-bit ADC 16 12-bit serial
ADC 16-bit ADC 16-bit ADC c Dual 10-bit ADC ADC
channel ADC
Hysteretic N/A N/A Uses inductor Adaptive Current
feature Current slope hysteretic band hysteretic band
Switching-time Adaptive Dead-
Switching-time b hseti
Multi-loop digital Predictive stator current prediction control beat hysteretic
control control
Features control control Switching ..nr
(Current, Voltage and Voltage-source inverter frequency Utilizes on-board
Feed-forward control) soon PWM modules
stabilization
for gate signals
1.5kW induction motor Active power
Application 1- q! PWM inverter r
drive filter
Switching 30.72kHz 6.7kHz 10kHz 20kHz
frequency















V inJ VOW--o-- -- Y/ Load




-d(t) Gain = H
d(t)\ T~, ___

d[n] Digital e[n] V[n] AID
DPWM <--- --+<- 41
DPWM Compensator

Figure 2-1. Generic architecture of digitally controlled DC-DC swit[n]hing converter

Figure 2-1. Generic architecture of digitally controlled DC-DC switching converter


Output duty rath [%]


80--

70-

60-- .0

50 ----

40-

30-

20 .


0


32 64 96 128 160
DPWM input (decimal)


224 255


Figure 2-2. Duty ratio based on hybrid DPWM (NDPWM=8bits) [8]

























Figure 2-3. Architecture of PWM inverter based 3-(D induction motor drive









CHAPTER 3
DIGITAL SYNTHETIC RIPPLE MODULATOR

Digital Synthetic Ripple modulator (DSRM) functions as a digital to analog converter in

producing the PWM pulse signal based on sampled converter waveforms. The DSRM utilizes

sampled version of converter parameters like inductor voltage, inductor current, or drain-source

voltage of MOSFETS to synthesize an artificial ripple used as carrier signal in pulse width

modulation. The modulation strategy is based on bonding the controlled variable to the synthetic

ripple generated by the DSRM. The resulting carrier signal is bound between hysteretic limits

which dictate the commutation instants of the power MOSFET switches. The modulation

strategy can be applied to the control of DC-DC and DC-AC power converters.

3.1 Design Concept of DSRM

In DC-DC converters or DC-AC inverters employing current-mode control [32-34], the

on-time and off-time of the power MOSFET switches are inversely proportional to the inductor

voltage under steady-state conditions as given in Eq. 3-1.


tON or tOFF L x AL (3-1)
VL
where L is the value of the inductor and AIL indicates the peak-peak inductor current
ripple.

In the generic case, the time duration to be generated can be inversely proportional to a

control input (q(V, I)) as given in Eq. 3-2.

K
theoretical q K 3-2)
q(V,I)
where q(V,I) is a function of voltage or current and K is a constant depending on the
application.

Similar duty ratio or time duration requirements are exhibited in hysteretic PWM control

[35-39] having variable switching frequency. The conventional analog approach based duty-

ratio/timing generators involve current sources and on-chip/off-chip capacitors. These









approaches generally exhibit poor noise sensitivity and offer limited programmability. Timing

generators [40-43] and duty ratio generators based on digital schemes involve digital pulse width

modulators (DPWMs) [44-52] that are characterized by a linear relation between the time

duration generated and the control input. The DPWMs are based on delay-lines [8] [11],

propagation-delay of basic gates or the time period of a fast running clock [12].

Synthetic Ripple Modulation based control of power converters involve carrier signal

generation from converter based parameters. This modulation strategy, when applied to the

control of a DC-DC buck converter, utilizes the inductor voltage for its carrier signal generation.

Hence, this modulation also involves generation of on-time and off-time duration for power

MOSFET switches with inverse relation to a control voltage. In the analog domain, the inverse

relation between the on/off-time of the power MOSFET switches and the inductor voltage as in

Eq. 3-1 can be realized by employing a Gm-C circuit [53] [54]. An all-digital realization to

generate timing inversely related to a voltage would involve area-intensive digital division

hardware or a cost-intensive DSP processor based solution. The need for the inverse relation

based duty ratio generation as in Eq. 3-2 led to the development of the digital inverse timing

generator.

3.1.1 Digital Inverse Timing Generator

The conceptual implementation of the digital duty ratio generation is shown in Figure 3-

1. In the developed duty ratio generation scheme, output of an A/D converter sampling a

converter parameter is scaled by Nsc to generate a step value (qstep), which is interpreted as a

floating point binary number. The step value is successively accumulated at each clock instant

(tCLK) until the hysteretic count (2Nc ) is reached, thereby generating a time duration that is

inversely proportional to the binary input. The integer portion of the accumulator output is









compared to the hysteretic count using a digital comparator. The timing signal is set at the

beginning of the accumulation process and reset at the onset of the comparison hit. The number

of clock counts required to reach the hysteretic count (2Nc ) and the slope of the staircase-shaped

accumulator output are determined by the step value. Hence, a larger step value results in a

steeper slope or fewer clock counts, generating shorter time duration and vice versa. The

assumption of the step value as a floating point binary number enables the realization of inverse

timing generation.

The timing generation scheme is based on digital time quantization and accumulation. The

digital timing expression embodying the design concept is given to be

2Nc
tDltal = xN X tCLK (3-3)
Nsc x NQ(V,I)

2Nc
tDigital = x tCLK (3-4)
step
where 2N^ denotes the hysteretic count, Nc is the number of bits used for count resolution,
N,(v,,) denotes the sampled value of the converter parameter (q(vL,iL, ... VDs)), Nsc
indicates the scaling factor, and tCLK is the time period of the clock used for timing
quantization of the switching period.

The sampled value (A/D output) is related to the converter parameter as

NQ(v,=) = G(A) x e s (3-5)

where "A" is the amplitude of the converter parameter used as input in the describing function

G(A), "t'" models the phase delay due to the sampling process. The quantization process

involved in sampling the converter parameter is modeled using describing function analysis [55].

The describing function for the A/D quantization is expressed by the following relation [56].









0 A < L
2
G(A) 4qs ( 1 2n1 2n (3-6)
-- S1- qLSB qLsB < A < qLSB
;rA2A 1 2 2
where qLSB is the LSB equivalent of the sampled analog input, "A" is the amplitude of the
analog input, and "n" is the quantization bin number in the sampling process.

The LSB equivalent is obtained from the maximum analog input amplitude (q(V,I)max), the

number of bits (NL) allocated for the step value, and the control input.

qLSB (I)max (3-7)
2LSB N 1 _

Based on the static characteristic of the A/D converter, the binary equivalent of the A/D output is

equal to the bin number for which the describing function G(A) in Eq. 3-6 is satisfied.

NQ(,) =n (3-8)

The quantized analog output can be determined using Eq. 3-8 as

Q(V, I)quant hardware = nx qLSB (3-9)

3.1.2 Extraction of Digital Timing Generator Parameters

The key parameters involved in the design of digital timing generator are the clock

frequency (fCLK), the count resolution (Nc), and the scaling factor (Nsc). The determination of the

design parameters follows an iterative procedure supplemented with simulation analysis as a

direct consequence of the non-linear relation described in (3-2).

The parameter extraction procedure begins with an initial assumption for the control input

A/D resolution namely NL 10. The digital timing generator can be evaluated with reference to

the generated time duration by determining how closely it approximates the time duration

obtained from the theoretical expression of Eq. 3-1. The performance metric for the digital

inverse timing generator, namely percentage timing error (Aerror), can be defined as










Error ttheorehcal Digital hardware (3-10)
ttheoretcal

The selection of the number of bits for step value (NL) and count resolution (Nc) influences

the timing accuracy between the digital and the theoretical expression for time duration. The

total hysteretic count in the digital SRM is mapped to a hysteretic voltage (Vhys). The hysteretic

voltage is selected to be much larger than the ripple on the output voltage of the DC-DC buck

converter as given in Eq. 3-11

Vhys > Vout ripple (3-11)

The voltage mapping between the hysteretic voltage and the digital hysteretic count is

given as

2Nc X qLs = Vhy, (3-12)

Using Eq. 3-7 in Eq. 3-12 the relation governing the number of bits for the sampled

converter parameter and the hysteretic count can be obtained.


2Ncx q(V)m < Vh (3-13)




I
NL Nc > log2 q(V'/)max' (3-14)


In the limit of the step value approaching unity, the minimum time period of the clock to

guarantee a specified timing accuracy can be derived by using Eq. 3-2 and Eq. 3-4.

t t theorehtcalmm K ; fCLK 1 (3-15)
CLK 2 2 x q(V, I. )max tCLK C


The current through an inductor in a power converter under continuous conduction mode is

shown in Figure 3-2 [31]. Also indicated in figure is the DC-DC buck converter inductor voltage.









The slope of the inductor current during the on-time (toN) and off-time (toFF) intervals as shown

in Figure 3-2 is given by


mi = VLro" and m2 = -LTff (3-16)
L L
where L is the inductor value, vLron and vLroff are the voltages across the inductor during
on-time and off-time respectively.

The on/off-time of the power MOSFET switch from the Figure 3-2 can be inferred to be

M Mx L M MxL
tON ~ ~ ; tOFF = ~ Ix (3-17)
i1 VLTon -M2 VLToff

The time duration expression involving the inductor voltage is equated with that of the

digital duty ratio generation expression to obtain the scaling factor. The digital timing generator

utilizes the inductor voltage of the converter to generate the duty ratio for the switches. By

equating Eq. 3-1 to Eq. 3-3 and utilizing the sampled inductor voltage (vLbn) as the converter

parameter, the scaling factor can be determined.


tDgtal XCLK L L (3-18)
Nsc X vLbn L
where VLbn is determined using Eq. 3-6 for the given inductor voltage (Amplitude A VL),

the quantization level qLs = v = Lmax indicates the LSB equivalent of the sampled

inductor voltage and NL is the number of bits allocated for the sampled inductor voltage.

The scaling factor reduces to

2Nc V,
Nsc- L--xAL X tCLK (3-19)


3.1.3. Scaling Approaches

The scaling of the sampled inductor voltage with Nsc can be carried out either by binary

multiplication or by utilizing the gain of the inductor voltage A/D signal conditioning block. The









two approaches are outlined in Figure 3-3 and their effectiveness is compared by evaluating the

timing error performance metric A ...ror..

The scaling of the sampled inductor voltage results in a floating point binary number in

both cases. In binary multiplication based scaling, the binary point of the floating point number

is dictated by the input and the scaling factor. Hence the feasibility of this approach is affected

by the need for additional logic to keep track of the floating point location in the step value and

the overhead of binary multiplication. The alternative scaling approach efficiently separates the

scaling factor as two ratios, one of which is incorporated into the A/D converter gain block and

the other ratio is used for binary shifting. The ratios are indicated in the following equation.

NR NR 2N
Nsc Nsc hardware DR 2-B x (3-20)

The ratios are based on the following set of conditions that ensures maximum number of

bits for the fractional portion of the step value to aid in timing accuracy.

DR= power of 2; NR- < 1 and N, = ceil log2 (NR) (3-21)


The ratio formed using "NR" and 2NB is incorporated into the A/D signal conditioning

circuit gain. On the other hand the ratio formed between 2NB and "DR" forms the binary shifting

ratio. Hence, this approach eliminates the need for binary multiplication and additional logic

required for tracking the initial floating point location. The sequential steps involved in the step

value generation for the two approaches are illustrated in Table 3-1 for a given input. The

parameter values used for illustration are NL=10, tCLK 40ns, q(V,J)max=12, andK = 6.2 x 10 6.

The scaling factor obtained from Eq. 3-19 is Nsc = 1.21x10 3 and it is approximated as 5/ (212)

to aid in binary operations. The various approximations for the scaling factor are determined

from Eq. 3-21 and the optimum value is chosen by evaluating the timing error performance









metric. In Figure 3-4 various scaling factor approximations are considered and the optimum

value (5/212) is determined based on the criteria of minimum timing error (less than 2% over

most of the input range).

Considering the data in Table 3-1, in binary multiplication scaling, the A/D output is

multiplied with the numerator (NR) of Nsc. The multiplied result (i.e. 882X5=4410) is construed

as a floating point binary number with the virtual binary point dictated by the denominator of

Nsc. The step value is truncated to NL =10 bits, resulting in 1.076= 1 X 20+0 X 2-1+0 X 2-2+0 X

2-3+1 X 2-4+0 X 2-5+0 X 2-6+1 X 2-7+1 X 2- +1 X 2-9. In the A/D gain scaling approach, the ratio

of (5/23) is included in the A/D block. The scaling factor inclusion modifies the A/D gain as

(A/D Gain) x (5 / 23) and results in the output of (55 1)10o for the given input. The output is

considered as a floating point binary number with the binary point location determined by the

binary shifting ratio, namely (23/212). Thus the step values are similar in both the cases while the

latter approach eliminates the need for binary multiplication. It also avoids the need for

additional logic to keep track of the initial floating point location in the step value. It allows for a

constant initial floating point location over the entire input range. The parameter Aerror is

determined for the two approaches and indicated in Figure 3-5. From Figure 3-5 it is evident that

A/D gain scaling can yield the minimum percentage error over the entire input range. Hence A/D

gain scaling is used in the experimental implementation of the digital timing generator. The

difference in time duration from the theoretical expression of Eq. 3-2 arises from the fact that the

scaling factor is approximated using Equations 3-20 and 3-21. This timing error is modeled

along with the timing error resulting from the successive accumulation and described in the

following section.









3.1.4. Successive Accumulation

The successive accumulation is carried out by proper alignment of the integer and

fractional portion of the step value with that of the accumulator output. The control logic in

Figure 3-1 ensures the alignment of the integer/fractional portion based on the carry output from

the accumulator. A carry output of "1" from the accumulator indicates an increment in the

integer portion requiring an additional bit for its representation. The step value is logically

shifted to the right by one bit with an insertion of a "0" bit at the MSB location. Similarly the

accumulator output is shifted to the right by one bit with an insertion of "1" bit at the MSB

location. The LSB bit is discarded in the above set of operations to truncate the result to NL bits

of precision. A barrel shifter is used to extract the integer portion of the accumulator output and a

digital comparator is used to compare with 2N The above set of operations involved in the

successive accumulation is explained with the snapshot of the accumulator and input registers

shown below.

Considering an inductor voltage input of vL=5V and using the derived scaling factor of

Ns = (5 / 2) x (2 / 212) the step value can be determined to be


5x- 23
L = 5V==> qep = round ( = (266) x = (0,100001010)2 (3-22)



Let ACC[k] and qstep[k] represent the accumulator output and the step value at the "kth"

clock instant. A snapshot of the sequence of operations occurring in the accumulator is indicated

below.








(266)10 = (0,10000 10 10A ==> qtep = (0.51953)10


ACC[1] ==> (0,100001010)2 ==> (0.51953)10
q,tep[1]==> (0,100001010)2 ==> (0.51953)10 +

ACC[2]==> (1,000010100)2 ==> (1.0390625)10
q,tep[2]==> (0,100001010)2 ==> (0.51953)10 +

ACC[3] ==> (1,100011110)2 ==>(1.55859)10
q,tep[3]==> (0,100001010)2 ==> (0.51953)10 +

ACC[4]==> (0,000101000)2 and CY=1

ACC[4 ]==> (10,00010100)2 ==> (2.078125)10
q,tep[4]==> (00,10000101)2 ==> (0.51953)10

The ACC[4+] and qstep[4+] indicate the accumulator output and step values that are

modified to account for the carry generated at k=4 clock instant.

The timing error due to the various quantizations can be modeled as the increase in the

quantized amplitude produced at the A/D output. The difference in time duration (tDigital diff) from

the theoretical expression is indicated in Figure 3-6. The change in the quantized amplitude of

the inductor voltage can be modeled by the following equation.
K
VLquant amp hardware (3-23)
theoretical Digital diff

The resulting amplitude modeling the quantization error can be determined from Equations

3-6, 3-7 and 3-8. The digital timing expression including the various truncation and quantization

errors is indicated in Eq. 3-24.









2NC
tDigital _hardware X tCLK (3 -24)
NSC hardware X Lbin hardware
where VLbin hardware= n for which the amplitude vLquant amp_hardware satisfies Eq. 3-6. The
MATLAB function modeling the quantization is given in Appendix A.

3.2 Architecture of Digital Synthetic Ripple Modulator

In conventional PWM control, the output variable is regulated by comparing a modulating

function with that of a carrier signal. The comparison process effectively modulates the time

duration of a pulse controlling the on/off position of a switch which in turn determines the duty

ratio. In synthetic ripple modulation, the carrier signal utilized in the comparison process is

derived from a system parameter unlike the traditional approach of using external oscillators.

The modulation strategy is based on bonding the error between the controlled variable and

a command variable to a synthetic ripple derived by filtering any ac waveform of the system.

The combination of the error and the synthetic ripple forms the carrier signal (modulator output)

which is bounded between hysteretic limits. The hysteretic limits dictate the on/off time duration

of the switches in the system. Synthetic ripple modulation also allows open-loop linear control of

an output variable with reference to a command input. Since the modulation scheme derives the

carrier signal from the system parameter, it enables natural feed-forward control. This

modulation scheme when applied to the control of DC-DC converter or DC-AC inverters, the

output voltage of a voltage regulator or the rotor speed in a motor drive can be controlled. In

such applications the on/off-time or the duty ratio of the power MOSFET switches can be

inversely related to a control voltage input as given in Eq. 3-1 or Eq. 3-2. Thus, the above

mentioned digital timing generator can be used for generating the duty ratio. The generic

architecture of a digital synthetic ripple modulator controlling a desired output variable in a

system is illustrated in Figure 3-7.









As indicated in Figure 3-7, the system parameter related to the duty ratio is sampled and

given as input to the digital timing generator. The digital timing generator scales the sampled

input and generates the step value. The step value is successively accumulated between the

hysteretic limits and the required duty ratio is generated. The PWM output is set to logic high or

"1" when the modulator output exceeds the upper hysteretic threshold (2Nc-1). The PWM output

is set to logic low or "0" when the modulator output is lesser than the lower hysteretic threshold

(-2N1).

f 1 Modulator Output < (-2N 1)
PWM= = (3-25)
0 Modulator Output > (+2 1)

The PWM signal is retained in logic 1 or logic 0 when the modulator output is outside the

hysteresis band. The PWM signal is set to the appropriate logic level once the modulator output

is within the hysteresis band based on Eq. 3-25 and normal SRM operation is resumed.

The generic expression modeling the synthetic ripple modulator in the analog domain is

given in Eq. 3-26.

ModulatorOutput Analog = Output Variable + Synthetic Ripple (3-26)

The modulator output forming the carrier signal is modulated between the hysteretic limits

given as

Modulator = Command variable + (Hys/2) (3-27)
Modulator = Command variable (Hys/2)
where Modulator+ and Modulator are the higher and lower hysteretic thresholds in the
analog domain and Hys indicates the hysteresis band.

The schematic representation of Equations 3-26 and 3-27 is shown in Figure 3-8. The

subtraction of the command variable from the modulator output expression of Eq. 3-26 modifies








the hysteretic thresholds to (+Hys/2) and (-Hys/2). The modulator output expression is changed

accordingly as

ModulatorOutput Analog Command = (Output Command) +
SyntheticRipple

In the digital SRM implementation, the error resulting from the difference between the

command variable and the output variable is sampled by an A/D converter. The sampled error

value (Error binary) indicated in Figure 3-7 and the synthetic ripple information from integer

value of the accumulator are used in the formulation of digital SRM modulator expression. The

digital SRM modulator output is given as

Modulator Output = (Error binary) + Integer Value (3-29)

In the digital SRM, the sampling of the error value between the command and output

variable instead of the actual output variable provides the benefit of allocating higher number of

bits for the error. It also offers the benefit of controlling the output variable with better precision.

The dynamics of the SRM is also enhanced by the fact that when the sampled value of the error

between output and command variable exceeds its higher or lower quantization levels [saturation

limits of the A/D (e.g. 0 or 255 with 8 bits of precision)], the PWM signal can be immediately set

to logic "1" or logic "0" depending on the saturation limits. The subtraction of the command

variable from Eq. 3-26 as explained earlier modifies the digital SRM hysteretic thresholds as

(2N-1) and(2N-1) with the "Hys" level in analog SRM mapped to 2Nc in the digital SRM.

The integer value from the accumulator spans from 0 to 2Nc during both the on-time and off-

time durations. Thus, to account for the modified hysteretic thresholds, the terms (2N -1) and

-2N -1) are added to the digital SRM modulator expression during the off-time and on-time









duration respectively. This ensures that with the integer value spanning from 0 to 2 N the

modulator output is always modulated with a hysteretic level of 2Nc The resulting digital SRM

modulator expression is given in Eq. 3-30.

Modulator Output= ( 2Nc- 1 Error _binary [n] )- Integer Value[n] ;PWM = 0
Modulator Output = \ (3-30)
(-2N1 Error _binary [ n] ) +Integer Value[n] ;PWM = 1

In the expression describing the digital SRM modulator, Error binary[n] indicates the

sampled error voltage of the output A/D and Integer Value[n] is the integer output extracted from

the accumulator at tCLK instant "n". Considering the modulator expression Eq. 3-30,

Error binary is negative when the output voltage is above Vcmd. Thus when PWM =1, the higher

hysteretic threshold will be attained earlier and Integer Value will span to less than 2Nc resulting

in reduced on-time. Similarly when Vout is less than Vcmd, Error binary is positive causing

Integer Value to span to 2Nc resulting in increased on- time. Similar argument can be applied

for the factor of (2Nc-1 Error binary) during PWM=0. A low-pass filtering effect similar to

integration is obtained in the digital timing generator's accumulator during floating point

addition by discarding the least significant bits. Thus the Integer Value[n] qualitatively

represents the low-pass filtered output of the sampled converter parameter.

3.3 Application Illustration of the Digital Synthetic Ripple Modulator

The DSRM architecture is illustrated below with reference to an application. The

modulation strategy is used in the output voltage control of a synchronous buck DC-DC

converter. The architecture of the digital SRM controlled synchronous buck DC-DC converter is

shown in Figure 3-9. The specifications of the DC-DC converter are outlined in Table 3-2.

The DC-DC buck converter controlled by the digital SRM operates in three distinct modes.









* Mode 1: When the error between the output voltage (controlled variable) and command
voltage exceeds the upper hysteretic limit (2N 1), the VPWM signal is set to logic "0" or
the UFET switch is turned OFF. The switch is retained in this position until the error
reduces to within the hysteretic band.
* Mode 2: When the error is within the hysteretic band, the digital synthetic ripple
modulator controls the converter output voltage.
* Mode 3: When the error falls below the lower hysteretic limit(-2Nc 1 ), the VPWM signal
is set to high or the UFET switch is turned ON. The switch is retained in this position until
the error returns to the hysteretic band.


The digital SRM employs hysteretic mode of control with switching frequency variations,

the on-time and off-time of the high-side MOSFET (UFET) is given in Eq. 3-17 and repeated

here for clarity


ON = AILxL ; tOFF L xL (3-31)
VLTON VLo FF

where AIL is the peak-to-peak inductor current ripple under steady-state conditions, VLTo, and

vLTof are the inductor voltages during the on-time and off-time respectively. From this the duty

ratio can be derived as

d = tN (3-32)
toN + tOFF

From Eq. 3-31 it can be inferred that the on/off time duration can be generated using the

digital timing generator with the inductor voltage as the system input parameter for the DSRM.

The output voltage of the synchronous buck converter is the variable to be controlled by the

digital SRM. The output voltage of the buck converter is related to the generated duty ratio as

given in Eq. 3-33. The output voltage is controlled by modulating the duty ratio of the DC-DC

buck converter.

VoU, (t) = d(t) x v(t) (3-33)









The design of the complete system involves the design of L-C output filter and the digital

SRM controller.

3.3.1 Design of Buck Converter-Output LC filter

The buck converter is designed with an input voltage of 5V and an output voltage of 1.5 V.

1
The L-C filter design assumes a switching frequency for the converter to be fs =300 kHz.
S

The converter output current is assumed to have a nominal value of 4 A. Using steady-state

analysis for a buck converter, I, & Lou = 4 A

The peak-peak inductor current ripple, AL = Ih, = 16%(IL) = 0.64A


out .nom.al = 1.5 V, nominal = 5 V, Road = 0.375 Q, r = 10 mQ (3-34)

The steady-state duty ratio based on the averaged PWM-switch model [57] can be derived

from Eq. 3-35.


Vot = RLoad x (DVn D'Vdode) (3-35)
RLoad + rL

Thus, the steady-state duty ratio can be determined to be D=0.39.

The design of the output filter parameters is based on current ripple requirements and

transient regulation requirements. The output filter inductor is determined from the inductor

current ripple [58].

L = x(- D)x Ts (3-36)
'hys

1.5x(1-0.39)x3.33x10- 6
L 0.64 4.76kH (3-37)
0.64

The design of output filter capacitor is based on transient and output voltage ripple

requirements. Considering the change in the inductor current for a buck converter during a load









step-up and step-down transient as shown in Figure 3-10, the inductor current slope can be

derived.

diL =--V" : During step-up transient (3-38)
dt L

diL -Vo.u
-dL O : During step-down transient (3-39)
dt L

From Equations 3-38 and 3-39 it can be concluded that the output-voltage overshoot

during a load-step down transient sets the limit on the transient performance of the converter

[58].

In order to keep the output voltage Vout within regulation range AVoOu during a load-

transient ofAloutmax, the minimum required output filter capacitance [58] can be obtained as
1 A!2max _LF 1 "_
Cm = -x Lmax x -- (3-40)
min 2 AV Vo di dt

For a voltage deviation of AVout = 60mV and Alomax = 4A, the minimum output

capacitance is determined.

Cmin = 415/,F (3-41)

3.3.2 Design of Digital Synthetic Ripple Modulator

The digital SRM controller involves the design of digital timing generator and the

resolution of the output variable A/D converter.

3.3.2.1 Digital timing generator

The design of the digital timing generator involves the determination of key parameters,

namely the input clock frequency (fCLK), count resolution (Nc), scaling factor (Nsc) and the step-

value resolution (NL). The resolution for the A/D converter is assumed to be NL =8 bits. The

count resolution can be determined from Eq. 3-14.










NL Nc > log2 VLmax (3-42)
Vhys

VLmax V ...nmax =(1+ (5%)) x = 5.25 V (3-43)

Assuming Vhy, (= 320 mV) > vo_ ppe (= 60 mV)

NL -Nc> log2 525 V, = 320 mV (3-44)

\320 mV)


NLNc log- 525 (3-45)
\320 mVJ

NL -Nc >4 -> N = 8 > Nc = 4 (3-46)

By comparing Equations 3-2 and 3-18 the parameter K can be determined to be

K = AL xL = 0.64A x 4.76kuH = 3.046x10-6 (3-47)

In a buck converter the maximum voltage across the inductor can occur during startup or

during an output short circuit. The inductor voltage under these conditions can be derived using

Table 3-2 to be

VL = vou, (3-48)

VLmax = VmaxVo = 5.25 V (3-49)

The minimum time period of the clock required to guarantee minimum time duration

accuracy as determined from Eq. 3-15.

K 3.046 x 10-6
tC=- 2=4 36.26 ns (3-50)
CLK Nc V 24x5.25
2 Lmax 5.25

The experimental implementation of the digital timing generator utilizes the onboard

oscillator from the ALTERA UP2 board [59]. The time period of the clock used for the digital

timing generator










fosc ALTERA = 25.175 MHz : tCLK= 39.72 ns (3-51)
fOSC ALTERA

The scaling factor can be determined from Eq. 3-19 to be

24 ( 5.25"
2NC XVLq 28 1
Ns = 3.046 =10 x 39.72 x109 = 4.2955 x 10 (3-52)
sc K c 3.046 x10-6

Due to restricted availability of the hardware resources, values of NL 8 and Nc 4 results

in percentage timing error less than 8%. The buck converter application can tolerate this

percentage of timing error due to the delays involved in gate driver and the power MOSFETs.

As discussed earlier the experimental implementation utilizes A/D gain block scaling to

minimize the Aerror parameter. The scaling factor of Eq. 3-52 can be approximated based on the

conditions stated in Equations 3-20 and 3-21.

9 9 24
N = x (3-53)
s 211 16 211

In the above scaling factor, the ratio (9/16) is incorporated into A/D gain and the ratio

(24/211) is used to interpret the A/D output as being binary shifted to the left by 4 bits followed

by a binary shift to the right by 11 bits. This effectively provides a binary shift to the right by 7

bits. Hence, the 8 bit A/D output is construed as a floating point binary number with 1 bit for the

integer portion and 7 bits for the fractional portion.

The approximation of the scaling factor indicated in Eq. 3-53 also influences the timing

accuracy between the theoretical and the digital timing generation approach. The possible scaling

factors which closely approximate the estimated value are indicated in Table 3-3. Similarly the

binary shifting ratios determining the initial binary point location for the step value are also

indicated in Table 3-3. The optimum approximation for the scaling factor can be deduced by

evaluating the timing error performance metric as indicated in Figure 3-11. The final count value









to which the respective step values are accumulated in each case is modified to reduce the

percentage timing error. The plot of Figure 3-11 indicate that timing errors less than 6% can be

obtained for the parameter Aerror with Nsc=(9/211), thereby yielding the factor for the

experimental implementation.

3.3.2.2 Output voltage A/D resolution

The output voltage of the buck converter during the interval when the upper MOSFET

(UFET) is ON is given to be

Vout = -vn vL (3-54)

Avou = Av,, AvL (3-55)

If the input voltage of the buck converter is assumed to be a constant value

Avot =-Av, (3-56)

The above equation can be interpreted in the digital domain to be the change in output

voltage caused by a single LSB change in the inductor voltage. The above equation can be used

to derive the limit-cycle oscillation constraint [6] [56]. The duty ratio change caused by a single

LSB change in the inductor voltage must be less than the output error-voltage A/D LSB change.

The error between the output voltage and the command voltage is given by

error = vcmd ot (3-57)

The maximum value of the error voltage can be determined based on the dynamic response

requirement. Considering the modulator expression of Eq. 3-30 the maximum value of

Error binary determines how fast the modulator reacts to a transient condition (load step-up or

step-down). The error voltage between the command and the output voltage is sampled based on

the A/D transfer characteristic shown in Figure 3-12. Under a load step-up or step-down transient

condition, the maximum value for the A/D output (Error binary ) in either direction is (2N-E 1









or- (2NE ). The magnitude of this maximum value should be such that the term

2Nc-1 Error_ binary) in Eq. 3-30 attains the higher or lower hysteretic threshold to trigger the


PWM comparator. Thus, the maximum allowable error voltage is given to be

Vrrmax. hys (3-58)

Using Vhys value of Eq. 3-44 in Eq. 3-58

Vema < 320 mV (3-59)


The LSB of the inductor voltage is given asvLq m, and the LSB of the error voltage is


given to be v rmax


Lq errq (3-60)

_Lmax errmax (3-61)
2NL 2NE


NL N > int log, V ma.- (3-62)
1 errmax

where VL max is the maximum inductor voltage, NE is the resolution of the output error voltage

A/D converter and NL is the number of bits used for the step value in the digital timing generator.

Hence in a digital synthetic ripple modulator, to avoid limit-cycle oscillation, the above

conditions need to be satisfied. The above equations when applied to buck converter

specifications from Table 3-2 would yield the following results.

VL = 5.25 V and Ve = 320 mV (3-63)

NL -NE > 4 (3-64)









The number of bits required for the output error voltage A/D is determined from static

regulation requirements. The error voltage resolution must be greater than that of the inductor

voltage resolution to ensure that the change in output voltage is tracked by the digital timing

generator. Thus, the number of bits to be allocated for the error voltage A/D converter in order to

provide a resolution of Verrq 30 mV(verrq > VjLq (= 20.588 mV)) is determined to be


NE = int log2 ermax (3-65)
1 \30 mV

NE = 4 (3-66)

Using Equations 3-64 and 3-66, the NL can be determined to be NL= 8.

3.4 Modeling and Simulation of Digital SRM Based Buck Converter

The buck converter controlled by the Digital Synthetic Ripple modulator involves both

digital and analog blocks, which are modeled using MATLAB and Simulink [58] [60-62]. The

choice of MATLAB/Simulink allows easier system-level implementation of the digital SRM,

integrating the continuous-time output filter, switching PWM action, and the digital controller.

The buck converter shown in Figure 3-7 comprises of three major components namely the PWM

switch, the output L-C filter, and the digital SRM controller. The modeling of each of these

components is explained in the following sections.

3.4.1 Modeling of PWM Switch

For a Buck converter, based on the PWM gate drive, the input to the LC filter is either the

input voltage (Vn) or the voltage drop across the synchronous rectifier (catch diode voltage

(Vdiode) can be used if a catch diode is used instead of the synchronous rectifier) neglecting the

drop across the UFET MOSFET. Hence the converter is modeled as a switch driving the output

filter, with the switch outputs decided based on PWM signal (Vn when switch is ON and Vsync rct









when switch is OFF). The on-time and off-time of the PWM switch is determined from the

timing signal VPWM, the output of the digital SRM controller. The Simulink model is indicated

in Figure 3-13.

3.4.2 Modeling of Output LC filter

The output LC filter network with input voltage vphase input current iL and output voltage

vou, is described by the following set of equations.


L- = vphase v it rL (3-67)


dv
Cdv= iL -iot (3-68)
dt

Vout = Vc +rc (iL -iot) (3-69)

where rc and rL are the equivalent series resistance of the output capacitor and DC resistance of

the inductor respectively. The above set of equations is incorporated into the Simulink model of

the Buck filter shown in Figure 3-14.

3.4.3 Modeling of Digital SRM Controller

The modeling of the digital SRM controller involves the A/D converter modeling, digital

timing generator modeling. It also includes the generation of the modulator output which

combines the output error voltage and the digital timing generator output.

The A/D converter or the quantizer model [61-65] is based on the LSB equivalent of the

A/D converter. The A/D converter model is shown in Figure 3-15. The zero order hold is used

for sampling, the quantizer is used for rounding to the nearest integer, and the saturation block

limits the lower and higher digital output levels as specified.

The A/D gain used for sampling the inductor voltage is based on the scaling factor.










AID Gain Num(N) x-= 27.32 (3-70)
v 2B 5.25 16
VLq
.28-1)

where vLq is the LSB equivalent of the inductor voltage, VLq = 2Lm The lower and

higher digital output levels of inductor voltage A/D are 0 and 255.

The A/D gain used in the sampling of the error voltage between output voltage and

command reference is given as


A/D Gain= 2E = 16.756 (3-71)
v v
errq errmax

The lower and higher digital output levels of the error voltage A/D are -16 and +15 based

on whether the output voltage is higher or lesser than the command voltage.

The digital timing generator as described earlier utilizes the sampled inductor voltage to

generate the on-time/off-time. The timing generator is modeled with Level 2 M-file S function

utility in Simulink [66]. The block accepts the sampled inductor voltage, timing generator enable

signal and the initial binary point location. The accumulated value, integer value, the current step

value, and the carry output are fed back as inputs to the timing generator block. The carry output

indicates the number of bits currently used for the integer portion of the accumulator output. The

Simulink model is indicated in Figure 3-16.

The modulator output is derived from the generic architecture expression of Eq. 3-30,

op (+8) VerrAD[n] ] Integer val[n] ; PWM=0 (3-72)
mod op= (3-72)
[(-8) VerrAD[n] ] + Integer val[n] ; PWM=1

The system implementation of the synchronous buck converter controlled by the digital

SRM modeled in MATLAB/Simulink is shown in Figure 3-17.

The buck converter waveforms are depicted in Figure 3-18. The waveforms indicate the

inductor voltage (VL), inductor current (iL), output voltage (vout) and the phase voltage phases) for









a command input of Vcmd=1.3 V. As seen from the waveforms, the inductor voltage during the

UFET on-time is VLTo = 3.66 V and that during the off-time is VLToFF = -1.54 V The output

voltage under the steady-state condition can be determined to be v0,t = 1.34 V. The on-time and

off-time duration corresponding to these voltages based on the theoretical expression of Eq. 3-17

are 1.027[ts and 2.44[ts. The step value for accumulation, the accumulator output, and the PWM

signal are indicated in Figure 3-19.

The on-time and off-time duration from the simulation waveforms can be determined to be

1.1 [s and 2.6 as. The parameter A ..... can be determined to be less than 7% when comparing

the generated time duration with that of the theoretical expression. The step value obtained in the

waveforms during the on-time and off-time can be derived as given in Equations 3-73 and 3-74.


3.66 x -
VLN STEPVAL =round 25 = (100)1 = (0,1100100)2 :> 0.78125 (3-73)
2'-1


1.54x -
VLOFF STEPVAL = round 5.25 =(42)1 = (0,0101010)2 :0.328 (3-74)



The actual step values without A/D gain block scaling while based on multiplication can

be determined to be



A/D output= round L .5 =(178) (3-75)

2 T =(178) 4.2955 0.7645 (3-76)1)

VLON STEPVAL IILT =(178)1 x 4.2955 x 10 = 0.7645 (3-76)











A/D output = round =(75) (3-77)
5.25 10
,(2'-1)l


VLOFF STEPVAL _UL = (75)10 x 4.2955 x 10-3 = 0.322 (3-78)

By comparing Equations 3-73 and 3-74 with Equations 3-76 and 3-78 respectively, it is

evident that the A/D scaling closely approximates the required step value.

The time duration generated using the digital timing generator is compared with the

theoretical expression and plotted in Figure 3-20. The percentage error is compared in Figure 3-

21.

3.4.4 Simulation of Adaptive Voltage Position for Digital SRM based Buck Converter

Adaptive voltage position (AVP) is an essential function of low-voltage VRM designs. The

AVP concept utilizes the entire voltage tolerance window during a step-down or step-up load

transient [67]. In AVP, the output voltage is positioned at a voltage level slightly higher than the

minimum value (Vout min) at full load. Similarly the output voltage is positioned at a voltage level

slightly lower than the maximum value (Vout max) under light load conditions. The AVP design

was simulated in MATLAB/Simulink and needs to be experimentally verified in future.

The AVP specs are Vin=5 V, Vout=1.55 V, and Alout=5 A. The step-down load transient is

considered with a load current slew rate of 50 A/Us. The maximum load current change is

specified as AI,, = 5 A and the assumed Rdroop=16 mQ. The output voltage change under a step-

down transient is illustrated in Figure 3-22 indicating the inductor current, load current, capacitor

current and the allowed voltage tolerance window. For AVP, it is evident from Figure 3-22 that

the output voltage resonates to the maximum value when the load current reaches zero. This is

due to the fact that once the load current is zero, the inductor current flows into the output









capacitor to charge it to Vout max. In the digital SRM, the AVP can be easily implemented by

turning off the UFET during the step-down load transient and turning on the UFET once the

inductor current reaches zero.

The required voltage tolerance window can be determined as,
AV re_ = Aut XR +VR = 5 Ax16 mQ+20 mV = 100 mV (3-79)


The L and C are designed such that the output voltage resonates within the tolerance

window. The inductor design is based on the ripple spec and given to be

L Tffx (1- D)Ts Vout x (1- D) Ts (3-80)
~L ~L


Vout = 1.55 V; D = Vout Vn = 1.55/5 = 0.31; AIL = 0.4 A; fs = 600 kHz


L = 55 -D)Ts 4.7 pH (3-81)
AL

During the load-step transient the output voltage change occurring across the capacitor is

given by
AV =AV -AAV (3-82)
out C out max out ESR (3-82)
where AVout ESR is the change in Vout due to the ESR of the output capacitor (C) and
AVout c is the voltage change across the capacitor due to the load current change of Alout.
AV c = AV (Aou, x esr C) = 100 (5 A x 5 mQ) = 75 m (3-83)
out c out max ( ou= 100mV(5Ax5 Q 75(3

The charging time for the output capacitor can be determined from the load current change

and the slope of the inductor current during off-time for a buck converter. The AVP design

utilizes a load step of 5A at a slew rate of 50 A/as. Thus Alout=5 A.


VLToffbuck = -V =-L A0u (3-84)
tCHG

Lx Aout 4.7pH x 5A
tCHG Vou 15.1612ps (3-85)
out 1.55









Thus, the net charge in the capacitor due to the load current change is given as

1
AQ= x tCHG xAout (3-86)


The capacitor value can be determined from Equations 3-83 and 3-86 as

AQ 1 (Alo )2 xL 1 (5)2 x4.7
C= = x ( = -x = 400/F (3-87)
AVout c + tolerance 2 Vo x (A c +tolerne) 2 1.55x95mV

The capacitor used is 425[aF. The capacitor current is shown in Figure 3-22 and can be

derived as


ic (t) = Io t (3-88)


vo (t) = ic(t) + (esr C x ic (t)) (3-89)

At the instant when Vout peaks, dVout/dt=0. Thus, the instant at which Vout peaks can be

determined from Equations 3-88 and 3-89.

tVout peak =tcHG -(esr_CxC)= 15.1612 js-(5 mQx425 pF) =13.0362 js (3-90)

Using the time duration determined from Equation 3-90, the slew rate for the command

signal can be determined as shown in Equation 3-91.

AVout max 100m V
Slew rate cmd outpeak 2 7.67mV/us (3-91)
tVout_ peak 13.0362ts

The UFET need to be turned on after 13.0362 ats based on the time duration from Eq. 3.90.

This can be accomplished by modifying the original hysteretic count of 2Nc = 16 under the load

transient condition. The change in the hysteretic count to turn on the UFET at the instant when

Vout peaks is determined from Eq. 3-96.

The inverse timing generator expression in the digital SRM timing is given as









2Nc x,
tDgtal CLK (3-92)
STEP

Under the step-down load transient condition, the voltage across the inductor is the output

voltage, VLff = -Vot = -1.55 V. The step value used for the successive accumulation under the

given load condition is given to be



SVLJ 1.55/(5.25/255)
qSTEP- 2 1285 = 0.58816 0.6 (3-93)
qslhf 2N[-1 128

Hence to turn on the MOSFET after the time duration determined from Eq. 3-90, the

modification in the hysteretic count can be determined as

Hys CountxtCLKtoutek (394)
E =t Voutpeak (3-94)
STEP

13.0362/as x 0.6
Hys Count =336 x = 196 ; tCLK = 40 ns (3-95)
40ns

Thus, the increment in the hysteretic count is determined to be


Modified Hysteretic count- Hyscount =13 (3-96)
2 N | 16

In the digital SRM implementation the hysteretic count of 2Nc = 16 is carried out for 13

additional cycles to determine the turn on instant of the UFET. A counter increments the

modified hysteretic count each time the digital timing generator output, namely, Integer value,

reaches 2Nc = 16. The error voltage between the command signal and the output voltage is

sampled by an A/D converter with NE=4 bits of precision and one additional bit for sign

representation (error voltage (+ve) when Vcmd>Vout and (-ve) when Vout > Vcmd ). The

maximum error voltage is determined from Eq. 3-59. The error voltage A/D resolution is

sufficient enough to track the output voltage change under the load transient. The error binary









signal can have oscillations due to the output voltage not exactly coinciding with the peaking of

the command signal (caused due to overshoot or undershoot). Because of the flexibility of digital

control, the digital SRM compares the current error binary signal to a range of error binary (+1,

0, -1) values based on the error voltage resolution of Verrq=30 mV. Thus to determine the turn on

instant of the UFET, the modulator compares the modified hysteretic count to the required value

of 13 and also compares the error binary signal to the allowed digital tolerance band. When the

required hysteretic count and the range of error values coincide, the UFET is turned on. The

simulation outputs for the modified hysteretic count based AVP implementation of the digital

SRM is shown in Figure 3-23 and Figure 3-24. In Figure 3-23, the inverse timing generator

output (integer value), the modified hysteretic count, and the error binary signal are shown. As

evident from Figure 3-23, integer value spans to the count of 32 for 6 cycles and an additional

count of 16 resulting in 13 cycles of the original hysteretic count (2Nc = 16 ). From the figure it is

also evident that the error binary signal at the vicinity of turning on the UFET lies within the

allowed digital tolerance band. In Figure 3-24, the output voltage, inductor current, modulator

output and the command signal are indicated. The overshoot evident in the output voltage is

within the allowed tolerance band of 20 mV. The modified hysteretic count changes the lower

hysteretic threshold as -208 (= -2N x 13 ). The resulting modulator output is also indicated in

Figure 3-24. The inductor current, output voltage, modulator output are indicated in Figure 3-25

for a load step-up condition. A load current step of 5 A is used and the resulting AVP of the

output voltage is indicated. Similar to a load-step down transient the hysteretic count is modified

to 208 (=16X13) during the load transient. The upper MOSFET is turned off when the modified

hysteretic count is reached and when the error binary signal is within the tolerance band.









In the transient AVP design methodology for digital SRM, three difference cases are

considered for ramping up the command signal. The three cases are outlined below:

Case 1: The command signal is ramped up once the UFET is turned "OFF" and the slew

rate is designed such that the peaking of output voltage coincides with the higher level of Vcmd

(Vout max). This is the optimum case of transient AVP design. Since Vcmd exactly coincides with

the peaking of output voltage, by virtue of SRM the output voltage follows Vcmd without any

overshoot or undershoots. The command signal is ramped up with a slew rate of 6.59mV/ats. The

AVP of the output voltage is indicated in Figure 3-26.

Case 2: The command signal is ramped up once the UFET is turned "OFF" and the slew

rate is designed such that Vcmd reaches Vout_max before the peaking of output voltage. In this

case the output voltage slightly overshoots and the follows Vcmd. The command signal is

ramped up with a slew rate of 11.9mV/[ts. The AVP of the output voltage, inductor current,

modulator output, VPWM, and Error binary for this case are indicated in Figure 3-27 and Figure

3-28.

Case 3: The command signal is ramped up once the UFET is turned "OFF" and the slew

rate is designed such that Vcmd reaches Vout_max after the peaking of the output voltage. In

this case the output voltage slightly undershoots due to the fact that it tries to follow Vcmd. The

command signal is ramped up with a slew rate of 5.43 mV/[ts. The AVP of the output voltage,

inductor current, modulator output, VPWM, and Error_binary for this case are indicated in

Figure 3-29 and Figure 3-30.

The slew rate of the command signal in each of the above cases is designed to be less than

the modulator output slew rate. The determination of modulator output slew rate is shown below

dmod 2N Lq 16 (5.25 / 255) 658 mV/us (3-97)
dt tON 500 ns









Since the on-time modulator output has a steeper slope when compared to off-time the on-

time slope was used above. The digital SRM provides the significant advantage of programmable

slew rate for the modulator to meet the required transient and steady-state specifications.

3.4.5 Modeling of Dynamics involved in the Digital SRM Controller for a Buck Converter

The dynamics involved in the digital SRM can be obtained from the command to duty ratio

and duty ratio to output voltage transfer functions. The dynamic system model of the digital

SRM is indicated in Figure 3-31. The duty ratio to output transfer function can be obtained from

converter system dynamics [31]. The command to output voltage transfer function can be

obtained by deriving the command to duty ratio transfer function. The command to output

voltage transfer function is thus given to be


v =v x -d (3-98)
vcmd d vcmd

From the digital SRM modulator expression of Eq. 3-30, the Error binary and Integer

value can be derived based on Equations 3-5, 3-6, 3-7, 3-8, and 3-9.

Error binary = verror x G (vcmd vou) x GE Nerr (3-99)

Integer Value = v x Nsc x G (3-100)

where GL and GE are the describing function of the A/D quantizer based on Eq. 3-6 for sampling

the inductor voltage and error voltage respectively.

Thus the A/D converter model for sampling the inductor voltage is given by

G, = G, (A) xe St 3-101)

The e-st' term models the phase delay due to the sampling process. The delay tl is given as


t + = Ls +Processing delays (3-102)
2
where Ts is the switching frequency and processing delays are on the order of 40-50 ns.








Similarly the A/D converter for the error voltage is modeled as

T
GE = GNE (A) x et2 t = + Processing delays (3-103)
2

The on-time of the power MOSFET switch in a buck converter whose output voltage is
controlled by the digital SRM can be derived using Equations 3-17 and 3-29 as,

2N Nerr) x tCLK (Vhys V error) x 'CLK
n (Ns x VLon x GL) (vn -vo ) x Ns x 3-104)

Similarly the off-time of the power MOSFET can be derived as

tof (2Nc + Nerr) x tCLK (Vhys + Vrror) tCLK (3-105)
o (Nsc x VLTOff xGL) (-v,) x Nsc x GL

The resulting duty ratio is given by Eq. 3-31 and can be derived as

d= tn (hys error ) Vo x(Ns xGL) (3-106)
ton +toff rrr (v NscG) -(2voutNscG)] + (vhysnNscGL)

The time varying duty ratio can be given as the sum of the DC operating point (quiescent
point) and the small signal ac component.

VD + Vs [Vmd c -Vu + x V +out + x (Nsc (3-107)
\D+d = ^ -^ --- ---J^ --- ----(3-107)
Vc+md +Nm-d -Vout + OUt ( vNSCGL) ou t +v scG,

+ (Vhys nNSCGL j

By cross-multiplying and grouping similar terms the following relation can be determined.
The non-linear terms involving the multiplication of 2 ac quantities are neglected.








{Vhy (,GL)] + [(,nGL) ((Vmd VoU )G,)] [2 (VoGL) ((,.d- Vot)GE )] d
+ {[2D((V Vmd)GE)] [D(GL)] [(VhysGL)]
(3-108)
+[((Vcmd Vou )GE)] (VoutG)]} vut
= {[2D(VouJL )] -(D(GL))]-[(VouGL )]} cmd



The duty ratio to output transfer function is given as

v oudo V 1 C
Gvd (s) --t G2 ; Gdo o = ; Q = R (3-109)
d s s iD L


The above expression can be modified as

Gvd() o _- Gd ) Gd (3-110)
d s2 + s+o2 S2 +Vs+W


where W = 02 Gd =Gdo x o 2and V = -. Using Eq. 3-110 in 3-108, the command to
Q
duty ratio transfer can be derived as

d_ [(2D-1)(VutGj)] D(VGj]L)] (3-111)
Vd {Vhys (nG )] + [(GL) (( -md u)GE )] [2(VuGL)((Vcmd ,u)GE)]
[ Gvd (S)(D(GL))]-[ Gvd(s)D (2md-4Jt)GE] Gvd(S) (VhysGL)]
Gd (S)(Td -O t)G]- Gvd)(S )]}

Defining the terms in the numerator and denominator of Eq. 3-103 as








NumA= [(2D -1)(VoGL,)] [D (V,,GL)]
DenA =[Vs (VGL)]
DenB =[(,,GL) ((Vcmd -Vt)GE,)] [2 (V,,GL)((Vd ut)G)] (3-112)
DenC = [-G (s) (D ( LGL))]+ [Vd (s)D (2V, d ) GE ]

-[Gvd (S)(VhysGL )]+[Gvd (S)(Vcmd ut)GE,]-[ Gvd(s)(VutGL)]}

T_
d Numxe 2 (3-113)
vcmd DenAxe 2 DenBxe 2e 2 +DenCx G xe 2
s T y )+T xe +xs2 +VS+W x

Using the first order Pade approximation for e "1 in Equations 3-93 and 3-95,

e-st (sw / 4) Ts +delays = Tsw (3-114)
1 +(Tsw /4) 2

Thus, the command to duty ratio transfer function can be obtained with numerator and

denominator coefficients in the "s" domain as

(NumA x,)s3 +(NumA(1+VT ))s2 +(NumA(V+W w))s
d +(NumAW) (3-115)
V' {[(DenAx ) (DenBx T)]s3 +
+[DenA + DenB + (DenA x V, )-(DenBx VT, )]s2
+[(DenAx V) + (DenB x V) + (DenA x WTw) (DenB x WT ) + (DenC x GJT,, )] s
+[(DenA xW)+(DenB xW)+(DenC xGd)]}

The digital SRM controlled buck converter is simulated in MATLAB/Simulink and the

steady-state parameters were derived from the converter outputs. The inputs to digital SRM

controlled converter are Vin=5 V, Vcmd=1.3 V, and Rload=0.5 Q. The parameters of the digital

timing generator used in simulation are Nc=4, NL=8, tCLK=40 ns, NE=5, and Ts=3.33 [as. The

MATLAB function used to determine the coefficients of the command to duty ratio expression is









given in Appendix A. The steady-state outputs determined from the simulation are D=0.27 and

Vout=1.34 V. The resulting command to duty ratio expression based on Eq. 3-115 is given as

d 3.27x10- 6s +1.9972 +2.312x104s+2.09x109
2.255 x10- 6s +1.952S2 +4.225 x 104s + 1.44 x 1010
Vcmd

The above expression can be expressed in the pole-zero gain form as

d 1.4504(s + 6.006 x10)(s2 +x04s+1.064 x 109) (3-117)
S (+8.525105)(s2 +1.319x104S+7.491x109)


The magnitude and phase of the command to duty ratio transfer function, duty ratio to

output transfer function, and command to output voltage transfer function are plotted in Figures

3-32, 3-33, and 3-34 respectively. These functions need to be verified experimentally.

3.4.6 Design Methodology for Digital SRM Controlling the Synchronous Buck Converter

A summary of the design methodology involved in the design of the digital SRM

controlling the buck converter is outlined in this section. The digital SRM design process

assumes that the parameters of the buck converter, namely, output filter inductor (L=4.7 tH),

output capacitor (C=425 tF), input voltage (Vin=5 V; +5%/-8%), output voltage (Vout=1.5 V),

and peak-peak inductor ripple current (AIL=0.65 A) are known beforehand. The next step of the

design process involves determination of the parameters in the digital inverse timing generator.

The number of bits for the step value (NL) and the hysteretic count resolution (Nc) are

determined from the maximum inductor voltage (VLmax=5.25 V) and the hysteretic voltage

(Vhys=320 mV) selected. The equation relating NL and Nc is given from Eq. 3-14 as


NL Nc >og j2 Vmax- (3-118)


NL Nc > 4 (3-119)









Based on an initial assumption of NL=8 for the inductor voltage resolution, the hysteretic

count resolution is determined from Eq. 3-118 as Nc=4. The time period of the clock

(tCLK =(/fcLK)) required for successive accumulation and timing generation is then determined.

tCLK _3 LxL 36.26 ns; fC 1 27.58MHz (3-120)
CLK required 2Nc xV 3K requrd
Lmax CLK

Based on the availability of resources, the clock used in the experimental implementation

is fCLK=25.175 MHz (tCLK=39.72 ns). The next step involves the determination of the scaling

factor based on parameters determined above.

Ns = AIL xt =4.2955 x10-3 (3-121)


The following step involves the approximation of the scaling factor based on Equations 3-

20 and 3-21 to aid in binary operations.

9 9 24
N = 9 -= x2 (3-122)
sc 211 16 211 (3-122)


Nsc AD =- (3-123)
16

The ratio Nsc A/D from Eq. 3-123 is incorporated into the A/D signal conditioning circuit

utilized for sampling the inductor voltage while the ratio (24/211) is utilized for virtual binary

shifting in the step value generation. The final step of the design process involves the

determination of number of bits for quantizing the error between the command and the output

voltage. The inductor voltage and the error voltage resolution are related by the following

equation.


NL -NE > int log Lmax (3-124)
V\ Ve max









The error voltage resolution and the maximum error voltage are based on transient

requirements. Based on the modulator expression of Eq. 3-30, the maximum error voltage

(Verrmax) is selected to be less than or equal to the hysteretic voltage (Vhys) for the PWM

comparator to respond instantaneously under a step-up or step-down load transient. Thus, the

relation between the number of bits for the inductor voltage and the error voltage is obtained as

(5.25 V 3
NL NE > int log, 25--V (3-125)
1 E 320 mV

NL -NE > 4 (3-126)

The LSB equivalent of the error voltage (Verrq=30 mV) is chosen to be greater than the LSB

of the inductor voltage (VLq=20.58 mV) resulting in


NE = int log, ermax = 4 (3-127)
S30mV

The AVP requirement of Vout_min=1.5V and Vout_max=1.6V indicates a voltage change

of 100 mV. Thus, the number of bits determined for the error voltage and its resolution (Verrq=30

mV) can track this voltage change under a transient load step-up or step-down condition and

satisfy the transient AVP requirement. Based on the parameters determined, the timing

generation accuracy is evaluated by comparing the time duration from digital timing generator

with that of the theoretical expression as shown in Eq. 3-128.



LxMAIL 2N^ X tCLK


Aerror ...= -\l V, (3-128)









In order to improve the timing generation accuracy, the number of bits for NL can be

increased or the time period of the clock (tCLK) used for accumulation can be reduced. The

parameter determination procedure is reiterated to reflect the changes.

3.5 Performance Analysis of Digital Synthetic Ripple Modulator

3.5.1 Open-loop Linear Control of Controlled Variable with Command Signal

The digital SRM allows open loop linear control of the output variable as stated earlier.

The command signal Vmd is varied from 1.2 V to 1.8 V and the resulting output voltages are

shown in Figure 3-35. It is evident from Figure 3-35 that the output voltage follows Vcmd in a

linear fashion even under open-loop conditions. The open-loop operation of the modulator

results in an error voltage between the actual output voltage and the command voltage. This

arises from the fact that the term VerrAD in Eq. 3-72 is not adequately compensated. Hence an

offset results between the desired output voltage and the actual output voltage in the open-loop

control of the converter. On the other-hand, the open-loop control still provides a linear control

of the output voltage with respect to the command voltage.

3.5.2 Influence of Component Variations on the Digital SRM Performance

The digital SRM involving generation of carrier signal from converter waveforms allows

natural feed-forward control. The SRM scheme also enables the carrier signal to better track the

component variations. This is shown in Figure 3-36, which indicates the variation in output

voltage for a command signal Vcmd=1.36 V due to variations in converter components values

(e.g. L, C, esr_C, rL ) over aging. A variation of +15% is included in the output filter component

values of the buck converter. The nominal inductor value used in simulation is L=4.7 tH (

Lmax var = 1.15X4.7 tH=5.4[gH and Lmin var=0.85X4.7 tH=3.99 pH) and the nominal output

capacitor value is 4.11 mF ( Cmax var=4.73 mF and Cmin var=3.87 mF ). As evident from Figure 3-









36, the output voltage remains within an allowable tolerance level over the 4 combinations of

component variations.

3.5.3 Open-loop Dynamic Response of the Digital SRM Controlled Buck Converter

The open-loop load transient response of the digital SRM controlled buck converter is

indicated in Figure 3-37. A step-up load transient is presented to the buck converter with its

command voltage held constant at Vcmd=1.5 V. As evident from the figure, the sudden change in

load current is immediately supplied by the converter with the help of the digital SRM triggering

the UFET VPWM signal to logic high or "1". Also evident from the figure is the droop in the

output voltage. The droop in the output voltage results in the increase of the error voltage

between command and output voltage. The increased error voltage causes the A/D converter

sampling the error voltage to saturate to the higher limit based on Figure 3-12. Thus the lower

hysteretic threshold is reached in Eq. 3-25 instantaneously, causing the VPWM signal to go to

logic high or "1". The current implementation of the digital SRM is based on open-loop control

with no regulation for the output voltage, causing a droop in the output voltage for the given load

transient.

3.6 Advantages of Digital Synthetic Ripple Modulator

Digital Synthetic Ripple modulator generates the carrier signal from converter parameter

allowing for natural feed-forward characteristic. Linear control of the controlled variable can be

obtained in open-loop configuration and transient performance is better because the controlled

variable is directly bonded to synthetic ripple. The principle of digital SRM when applied to

speed control of motor drives can eliminate the need for stator current sensing, while providing

superior transient performance due to hysteretic operation.









Table 3-1. Sequential steps involved in Step Value generation
Parameter Binary Multiplication Scaling A/D Gain-block scaling
1 Analog Input 10.35 10.35
2 A/D Output round(10.35/(12/1023)) round((10.35X5)/((12/1023)X8))
(N()) =(882)10=(1101110010)2 =(551)1o=(1000100111)2
3 Scaled output (882X5)/212=(1,000100111)2 (551)X(23/212)=(1,000100111)2
=1.0762 =1.0762
4 Step Value qstep=(1,000100111)2 qstep=(1,000100111)2



Table 3-2. DC-DC converter specifications
S.No Parameter Specification
1 Input Voltage 5V +5%,-8%
2 Output Voltage 1.1 1.85V
3 Output current slew rate 50A/[ts
4 Output current selected 4A
5 Output voltage resolution 30mV


Table 3-3. Scaling factor Approximations
Actual Scaling Factor Nsc = 4.2955 x 10
Nsc approximation Virtual binary point factor
5/210 =4.88x10 3 23/210
9/211 = 4.3945 x10-3 24/211
8/211 = 3.90625 x 10-3 24/211


































Figure 3-1. Conceptual implementation of digital duty ratio generation




m VL=O m VLTOff

iL L 2 L


Figure 3-2. Inductor current indicating the current ripple and time intervals along with the buck
converter inductor voltage










Binary Multiplication Scaling
AID
--- ,1O---T--7 NA r---- N---Nfr____
q(V,I..) Ns q
_LSB step



S bz1 b b, bl b .


Integer -----
Integer Fractional Portion
portion Virtual Decimal Pt
Virtual Decimal Pt


AI/D Gain Block Scaling
r-1 /AID


bNl1 --b, b, b0


Integer ----- 2 I
pion Fractional Portion 2
I portion Virtual Decimal Pt Den(Ns,)


Figure 3-3. Scaling approaches for step value generation







6 -
SNSC= 5/212; Count = 16 NL =10 ; tLK= 40ns
so L 'L ILK


-*-- Nsc= 9/213 Count = 14
------- Nc= 8/213 ;Count = 13


: 4



. 0



2
S-g


4 6
Control Input Voltage (V)


Figure 3-4. Timing error performance for various scaling factor approximations used in step
value generation












12 --- -- e- A/D Gain block scaling
N =5 /212 ;N =4 Binary multiplication scaling
a N 10 ;tLK= 4Qns
.0 10 L

-,






0











1 2 3 4 5 6 7 8 9 10 11 12
Control Input Voltage (V)


Figure 3-5. Simulation analysis indicating percentage timing error based on binary multiplication
scaling and A/D gain-block scaling













120 -- ------------------
120
SNL 10 tCL = 40n Nsc =(5/23)X(23/12)
S100 1L,
CL 100I -I I------ ------ ------L-----I-----I------------------L__ _

.2 80

S60
E 40 ------------





-
100 200 300 400 500 600 700 800 900 100C










Sampled Inductor voltage in binary
I-t


-0 -






100 200 300 400 500 600 700 800 900 100C
Sampled Inductor voltage in binary

Figure 3-6. Simulation analysis indicating percentage timing error based on binary multiplication
scaling and A/D gain-block scaling













System Parameter Error
f (Digital Timing ADC 2N 1 2v 1
SI ADC Generator Input)

S- -------- o I
Digital Timing Generator I
fcI Scaling & Successive I N
Accumulation I
___ Integer Value PWM

SPWM A+BA-B

P WM- I sV ", ,

Digital SRM 2c '-1 ,/
i -2 to Modulator Output I

Figure 3-7. Generic architecture of a system controlled by digital synthetic ripple modulator


PWM





Modulator Output


to
tON



StOFF

Modulator' = Command + Hys
-/ /- <- -
Synthetic Ripple Hys

SModulator = Command Hys
2Output Variable
Output Variable


Figure 3-8. Generic synthetic ripple modulation showing the hysteretic thresholds, command
variable and PWM signal




















Digital Timing Generator
f Scaling & Successive to -
I CLK Accumulation
--4*----- Integer Value B PWM

PWM A+B/A-B
I PWM -- S -
i Digital SRM -2- < ": y !
Digital S I Modulator Output


Figure 3-9. Architecture of digital SRM controlled synchronous buck DC-DC converter.












V -V
in m out
1--[
1,


A M -~u


_L \ L


'hys" -\/ \- ------

V ---- \\A ----
//,
------ ----------------







Outmt




t


Figure 3-10. Inductor current waveform during load current step-up and steady-down transient



20 1 _-7


E~
F
r



Wa



a)CC
U
0~


-6-N~ =5/2 3 ;N =2 3I2~ 10Count 16

N~ =9/2 4 ;N =24/211 ;Count 15

---Ns =8/24 N B = 24/211 ;Count 15


01 1 1
1 1.5 2 2.5 3 3.5
Inductor Voltage (V)


4 4.5 5 5.5


Figure 3-11. Simulation analysis of percentage error for various scaling factor approximations











+(2N -1 ...........


+ 3
+ 2
+ 1

- 1
- 2
-3


Vcmd


.................._...b


Figure 3-12. Transfer characteristic of the A/D converter sampling the error voltage between
output and command voltage.


VP WM


Figure 3-13. Simulink model of the PWM switch




































Figure 3-14. Simulink model of buck LC filter


N Digital Output


Zero -order Quantizer
Hold
LSB 2N -1


Figure 3-15. Simulink model of the A/D converter










VLbmary
Timgen en
Init cy digital _timing_




Sample delay











Figure 3-16. Simulink model of digital timing generator


Acc _val
Integer val














Async rect -0.2V

8 ..7







MOD OPf e rr
A DC ADC


Figure 3-17. Block diagram depicting the Simulink model of digiterrAl SRM controlled buck
Timing converter

R Generator +-

Integer


8 B<0..7> A<0..7> VPWM
A+BIA-B
MOD OP ADDISUB ----



-8


Figure 3-17. Block diagram depicting the Simulink model of digital SRM controlled buck
converter












Inductor Current(i



4-2 ................. ..... ............... ......---------------------- --------------------







2.6tis
3 .- --- ---.. ............ ------------------ -------------------- ......... ... ..... .. ... ...... ........ ....... ............ .............. ...........-





3 ....... ........ ... .. ...... ........ ........ ............ .................


2 ....... ...... .................... ......... ..... ...... .. ..... ......... ...... ........................... .............. ............ ... .......




-2 -


1.3415



1.34
1,3395
1.339


2.838


2.84


2.842


2.844


2.846


2.84B


Figure 3-18. Simulation outputs of the synchronous buck converter using MATLAB/Simulink for Vcmd=1.3V


L --------------------------- ---------- -------------------------- --------------------------- -------------------------- ............


. . . . . ........ .......... .......



...... .. O lf V91(og "9 !Wt) ..... ............... ......... .... .. ....... ........ ........
- ---------- ---- --- ---------------- -------------------------- --- --------------------- 2 1is I-d iv ---------------------------------------- ------------








































I II

5 -- -- - -- - -- -- - ---- -- -- - - - -- --

Integer _val

















.......... ......... .... ... ...... .......... ... .. ... ... .......... ... ......... .. .. .... ....... ...........






----....... ---- ..--...-.. .-. --- .-........... .... ..--- ..--....-..... .---- ........--.-... .-
VPWM .2.6 .s



















1.1ps I i

5 - - --- - - - ---- --- -


. . . . . .


2.838


2.842


2844


2846


2-84W


Figure 3-19. Simulation outputs indicating the step value, integer value and VPWM signal of the digital timing generator


2.85


-----------------------


---------------------


-----------------------------


..............................


........... I ...........


...............


I
- ---------- -------

. ........... -------





. . .


..........


------------- ---------


---------------- .........................

Yqlue


............ ...........................


.............. ...........


----------


----------


----------


..........


-------------


.............


-------------


-----------





----------


............


----------





-----------



















3 3------4---- ----- ---.-- --------;------;----- -----. -----
-\ -E~- Digital timing Generator Simulation data
\Theoretical expression data





'I-



1-- L

=1.5 ,L i ,


E



0.5------------------------------------------------------

0.5
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Inductor Voltage (V)

Figure 3-20. Comparison between on-time/off-time generated based on theoretical equations and
simulated synthetic ripple modulator.
















125 ------


s-o a i



L,.


o









S------ ---- -- ----- -




0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.E
Inductor Voltage (V)


Figure 3-21. Percentage error between digital timing generator and theoretical expression using
simulation analysis













Alo9


IOUT


Slope LTroff
L
iz (t)


Seance


'CHG
irv(t)





--Figure 3-22. Voltage change across the output capacitor during a step-down load transient










Integer value


..AAAA


14 I I I
"12 --.

- -.. . . . . .... . . . . . .. . -... . . . ... .. . . . . '. ..1. . . . . .. . . .
S---------- ------------ ----------------------------------- --------------------o------ ----i-- ce hi tc i --
4- ---- .- .-- .---- .--- ........---- .. .... ..... .... ... ...... .....


S- :Error binary
-1
2 .---- -- -- ---------- --*- ......---- ----------------



-4 .. .. ..... .. ... .. .. .. .. .. ........... .. ......... .. ................ ..--- ---- -..---- -..-. .----- -- -- -- ---- -- ---- ----- ---- -- ---- -- -- --- -- -- --
1.3 1.305 1.31 1.315 1.32

Figure 3-23. Integer value, modified hysteretic count, VPWM, and Error binary for AVP implementation in digital SRM


....












II I I I I I
82 ..... ...... ............ ...... .. ... ....... .... .. ....... .... ..... ...-.......... ..... ....... ................... .... ... .. ... .... ....... .....

















6-
6 ............. ... ............ .. ... ... ... ... ... ......... .. .... ..... ... .... .... .. .......
------- --- ------ -- ------- ---------








54 --- --- --- --- -- --- -- --- --



















InCommnand Signal rd (V)
-- -.- -- -. .- -I












. . . . . . .. . .. .i-- -- - -- i .. . i - - . . i . .


1 31


1 32


1 33


1 34


1 35


Figure 3-24. Integer value, modified hysteretic count, VPWM, and Error_binary for AVP implementation in digital SRM


1 29


1 36











I I I I I I I


Inductor Cu:rrent i (A)









1 .4 .. . .. ..... .. ..... .. .. .. .. .... ...... ..... ... .. .. .... ..... ........
05 ------- ----- ----- ------------------- -- ----------- --------------








4 I I I
250








5---- ----------- I I



Modulator Output


-50 -------- ------------------- --- ---- ---------------------------- -------------------------------------------------------------------

1.295 1.3 1.305 1.31 1-315 1.32 1.325 1 33

Figure 3-25. Inductor current and AVP of the output voltage based on optimal AVP design for the load step-up transient


~f











SI I I 1 I I I I

6-2







1.55 d
2.5 ---- ---------------... --- -. --- .. .. .. .......^ -ag ^ y ---- -- -- -- ---- ---- ---- --


-2 - - F - - - -* - *I . . . . I --- - -. .-. .-.-. .I. .-.-. .-- -. .-.- -.-.- -.-.I .-.- -.-.-- -.- .-. .-.-. .-. .-.-. .-.-.- -.- -.-.- .- -.-- -.-. .-. -. .-.- .-.- .- .- .- -. -. -



1.6 ---- -- -- ---- -------------------- ----------- .... ------- -- ---- --- ----------------- -
1 5 ........................... ...I
4 --- .......










2. Load .urr..t Step I 1)1 Se te =5 ) ....
.. ... .... ... .. .. .. ... .... .... .... ..... .... .. .... ... ... .....'"-^.. ... .. .... .. ... .. ... .. .... .... .. "..... .. .. .. .. .....





t ---------- -------- ---- ---- ---------------------- ------------ --- -- ---- ---


1.19 1.2 1.21 1.22 1.23 1.24 1.25 1.26 1.27

Figure 3-26. Inductor current and AVP of the output voltage based on optimal AVP design for load step-down transient











S ..... .. .. ... .... .. .. .. .. ........ ... ... ... ..... ... .... ........ .. ... .. .. .. .. .. ... .. .. .... ... .... .. .. ...... ......... .. ... ... .... .. .. .




----- ------ - -...-....-.- --- -------- ----- -----------1---- --------------- ----- -- --- --------- ------ .. ----- --
16 -- ----

1.55 .... ........ .... .. .. ... .. I .o.d Sign .L. .... .. .. ... .. ..... ............ -

':. .....1 5 -- ----1----- -----r -- .
1.5








15----- ----- ------ ----




w e -_ O -----------
2 . - -. -.-.. . -. . -"- - - - . . .- - - -
L i oad C rrent SIt'p-Ri0i(A) (SlewRate = 5OAI s) 1O0s div



1.19 1.2 1.21 1.22 123 1.24 1.25 1.26 1.27


Figure 3-27. Inductor current and AVP of the output voltage Vcmd reaches higher level before the peaking of Vout (Vout_max)









. . .I -I



4. - . . . .... . . . . .. 4 . . . . L .. . . . . . .... . . .. . . . ... . . . .
t Idicto r C-rrent i-(A)

. . . . . . . . . .: .... . : . . . .. i . . . . . .
....... i............. i... ... ........ i.................. i .. ............. i............... ...................'. ........... .....



1 5 - - - . . . . .. . . . . I . . . . J.. . . . .. . ... ] . . .. ( .. . .. . .. .. .
output ol qge-yv

IIIIII I I I
2 0 - . ... . .... . . .... . .... . ... . ... .. . .... ..L. .. . . .. . ... .. ...
10
-0
-1 0 --- ------ - - -.- - - - - - - --. -. .-. .-- -


W2- -- -- 0 M -- N- -- WI .... ---- --VjIIII)'IIII- l'
-10 ---------- ........ .. .. -- -- -- -- -- -----L U.OU -- .
Moii o irn


. . . ... .. . . . .... . ... .. . . ..... .. ... ... ...... ... ... ... ...... .... ... .... .... .... ....... ...... ...... .... ...... .. . b n a r. .... .
o L--2 : .:.. . -. ....... ..... ......... !.................. M c d ik t ...0 111 1i ............. ...,.... : _


2 -- -- I - - - - - - - - - - - - - - - - - - -. --. .-. . . . . .- .- .-.- .- .- .- -. - .
---i" ~~~..... ... ........:, ................. i ................. i...... . ,. . .J. . .i. .
II I
-4
-4 --------- -- -- --- --- --


2 ....... -- T s ... ......
Load Curyrent Step -i (A) (SleirRate = 50AI 1ps)
2 - -- -- -- - - -- : ----- - --- .. . .. . - -: - -. .. ..-- - - -1 / y o r - -
o ~~~~ ~ ~---- -------........ ----------------------------------------------------
0 ......... ................. : ;
II I I I I I I
1.19 1.2 1.21 1.22 1.23 1.24 1.25 1-26 1.27

Figure 3-28. Inductor current and AVP of the output voltage Vcmd reaches higher level before the peaking of Vout (Vout_max)

















I I I I I I I
1o6 ........-. -- -- -- -- -- --- .................... . .. -------------"....
1- - - - - - -
Output Volitge' V (-):




I I I I
1 .5 .. .. .. .... .. .... .. .. .. ... .. .. .. ... ... ....... ..... .. .... ... .. ...... ... . ... .. ...... .. .... .. .... .. .. ..








1 5 . . . .._. . . .. .. . .. .. .. : .. .. ... .. .. .. .. . .. ... .. .. .. .. . .. .. . : .. .. .. . .. .. .

6 -- -- -- -- I- --- -- -- -- -- -- I I - - - - -- I I - - - - - I .- .- .-.- .- .-.- .- I- .I .-.- .- .- .-.- .- .- .- .I .- .-.- -.- -. .-.- .-- .I .-- -. .-- - - J .I. .-- - - - I .



S---.. ----.........----.....................................................------ -------
1.19 1.2 1.21 1_22 1.23 1.24 1.25 1_26 1.27

Figure 3-29. Inductor current, VPWM, and AVP of the output voltage Vcmd reaches higher level after the peaking of Vout
(Vout_max)











- - -. . .. . . ...... . . .

II I I I I I
---- -
1Indue tor Curre nt- i (A)





1.55 -


Output Voll 1.5-
IIIIIII
r i l 1 1 1 i i i i i i i i i i i . . . .. . .. . ... . .. ... .. ..,. .. .... .. ..,. .i i l l i i i i f l l i l f l
I2- - - --- - - -

-1 0. . ,. . . . . ..:,
-. 5 .i . . ..-- - . . . . . .. . ...... ..... . . . . . . . . .. .. . . . . .. . .
2' - - --. - - --..... . .. '. -- . . . . . . . . . -,-- - --- -. - -.-- - - - -
-10
-,0 1 .. . ... ... i . . . .. . ... . . . . . . ... ... . . . . .. .. . ... . _. . . . . . . -
--O ------- ---- --- ---------------------------- ----------- ---- -------- ---- -------------------- ---- --







2 _...... Load C,.'rent Step- .o()SlewRate = 50A,,! tzs) 1.OPzs,, .. i
J....... "................... -

0-------------------------------------------------------------------
iError i inary




1.19 1.2 1_21 1-22 1.23 1.24 1.25 1.26 1_27

Figure 3-30. Modulator output, Errorbinary, and AVP of the output voltage Vcmd reaches higher level after the peaking of Vout

































Figure 3-31. Dynamic system model of the digital SRM controlled synchronous buck converter










Command to Dutyratio Magnitude(dB)


10
I 0 I - l II-- -I I I -l-II I I I -I I III- -I I I Il lI-- l- -l -l l I I II I I-- l 1 + l


L = 4I TiHI = 200 1,", I = 050 II-
I)=02,.r =51 =1 34I 1. =1.3r .
-0 -- I I 0- ---4--- 4




-30
1001001 102 103 104 1 0


Command to Dutyratio Phase(degrees)


200


0
100


103
Frequency (Hz)


Figure 3-32. Magnitude and phase of command (vcmd) to duty ratio (d) transfer function