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Development of DRIE CMOS-MEMS Process and Integrated Accelerometers


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DEVELOPMENT OF DRIE CMOS-MEMS PROCESS AND INTEGRATED ACCELEROMETERS By HONGWEI QU A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006

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Copyright 2006 by Hongwei Qu

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This thesis is dedicated to my wife Ch en Chen, and my daughters Wendy and Angela.

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iv ACKNOWLEDGMENTS I would like first to thank my advisor, Dr. Huikai Xie, for his continuous encouragement, expert advice, guidance and support of my thesis research. His profound knowledge and expertise in MEMS and other engineering fields are sources I can always rely on. I would like also to express my appreciat ion to my Ph.D. committee members, Dr. Toshikazu Nishida, Dr. David Arnold a nd Dr. Mark Davidson, for their advice, suggestion and time on my research and thes is. I am grateful to Dr. Arnold for his comments and corrections of my thesis ma nuscript. I am also benefited from the discussions with Dr. Mark Sheplak on fabr ication process and characterization of the accelerometers developed in this thesis work. I would like to acknowledge Drs. David J ohnson and Chris Constantine at Unaxis in St. Petersburg for beneficial discu ssions on the plasma etch of thick SiO2; Dr. Rauf Shahid at Freescale for help on physical models in plasma etch. I appreciate the helps from my gr oup members at the Biophotonics and Microsystems Lab (BML). My special thanks go to my project mate, Dr. Deyou Fang, for his excellent circuit design a nd help in device tests. Th e days and nights we spent together in the labs are just memorable. I enjoy my time with Dr. Ankur Jain and Shane Todd at BML. Dr. Jain’s advices on my device fabrication are valuab le. He is also an export on optical instruments and is always a reliable support to all BML members. Shane’s work on the modeling of optical MEMS devices helps me in a better

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v understanding of these devices. Mingliang Wang, Lei Wu, Kemiao Jia and Xiaoxing Feng offer me many helps in device fa brication and characterization. My thanks also go to the fellow members at the Interdisciplinary Microsystems Group (IMG) of the University of Florida. I benefited from the good research environment in IMG and helps from many IMG members including, but not limited to, Jian Liu, Anurag Kasyap, Stephen Horowitz Robert Dieme, Yawei Li, David Martin, Benjamin Griffin and Chris Bohr. The fabrication of the devices was mostly carried out at the University of Florida Nano Fabrication facilities (UFNF). Thanks go to Al Ogdan, Bill Lewis and Dr. Ivan Kravchenko at UFNF for the maintenance of the facility and support in the fabrication. I also thank Shannon Chillingworth, the depa rtmental graduate coordinator, for her outstanding work in my graduate study. Th anks go to Joyce White and Kathy Thomson for their support in my research. Finally, I am grateful to my family a nd friends for their constant support and encouragement. I am indebted to my wife Chen Chen for her endless love and support. Without her support, this thesis work is im possible. My love to my daughters, Wendy and Angela, is the propellant in ach ieving this thesis research. I owe my parents and parentsin-law for their endless love a nd support for my study in USA. I am in debt to my sister, Hongpei Qu, who takes care of my parents when I study abroad. I woul d like to thank my friends James Zhang, Jiandi Zhang, Michael Li u and their families for their friendship and help. I want also thank Vicky Liu and Huanyu Yue for their valuable advices on my Ph.D. study.

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vi This research work was partially su pported by NASA UF/UCF Space Research Initiative and the device fa brication was supported by MO SIS through its Educational Program.

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vii TABLE OF CONTENTS page ACKNOWLEDGMENTS.................................................................................................iv LIST OF TABLES...............................................................................................................x LIST OF FIGURES...........................................................................................................xi ABSTRACT.....................................................................................................................xv i CHAPTER 1 INTRODUCTION........................................................................................................1 1.1 CMOS-MEMS Technology...............................................................................2 1.1.1 Preand Inter-CMOS MEMS Technology..............................................2 1.1.2 Post-CMOS MEMS Technologies...........................................................4 1.1.2.1 Additional MEMS structur es on CMOS substrate...............................4 1.1.2.2 Formation of MEMS in CMOS substrate............................................6 1.2 MEMS Accelerometers....................................................................................10 1.2.1 Sensing Mechanisms of MEMS Accelerometers..................................12 1.2.2 Capacitive MEMS Accelerometers........................................................13 1.3 3-Axis CMOS-MEMS Accelerometers...........................................................17 1.4 Thesis Goals and Organization........................................................................20 2 DRY POST-CMOS MICROFABRICATION AND TOOLS....................................22 2.1 Plasma Etch......................................................................................................22 2.2 Characterization Methodology.........................................................................30 2.3 SiO2 Etch..........................................................................................................32 2.2.1 Challenges in Anisotropic SiO2 RIE......................................................32 2.2.2 System Characterization........................................................................34 2.2.2.1 Etching rate...................................................................................35 2.2.2.2 Top metal layer milling.................................................................36 2.2.2.3 Sidewall profile of the SiO2 layers and CMOS stacks..................38 2.2.2.4 The inhibitor polymer redeposition on the sidewall......................39 2.4 Advanced Silicon Etch by STS ICP DRIE......................................................43 2.3.1 ICP Silicon DRIE Syst em Configuration..............................................44 2.3.2 Silicon Anisotropic Etch........................................................................45 2.3.3 Silicon DRIE Characterization..............................................................48

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viii 2.3.3.1 Etch rate and profile tuning...........................................................49 2.3.3.2 Microloading and ARDE effect....................................................53 2.5 Summary..........................................................................................................57 3 IMPROVED DRIE POST-CMOS MEMS TECHNOLOGY.....................................59 3.1 Dry Post-CMOS MEMS: Background............................................................60 3.1.1 Thin-film Post-CMOS MEMS Technology..........................................60 3.1.2 DRIE Post-CMOS MEMS Technology.................................................63 3.1.2.1 Example device I: electrothermal micromirror.............................66 3.1.2.2 Example device II: single axis accelerometer...............................68 3.2 Improved DRIE post-CMOS MEMS Technology..........................................70 3.3 Summary..........................................................................................................73 4 DESIGN OF THE INTEGRATED ACCELEROMETERS.......................................74 4.1 Applications of the Designed Devices.............................................................74 4.2 Single-axis Lateral Accelerometer...................................................................76 4.1.1 Device Design........................................................................................76 4.1.2 Device Simulation Using Finite Elements Method...............................80 4.3 Tri-axial Accelerometer...................................................................................82 4.2.1 Z-axis Sensing........................................................................................85 4.2.2 Analysis of the Cross-axis Coupling......................................................92 4.4 Summary..........................................................................................................96 5 SOME ISSUES IN THE DEVICE FABRICATION.................................................98 5.1 Top Aluminum La yer Removal.......................................................................98 5.2 Dry Etch Caused Device Contamination.......................................................102 5.2.1 The Sources of Contamination.............................................................103 5.2.1.1 Front surface contaminants.........................................................105 5.2.1.2 Isolation trench sidewall contamination......................................107 5.2.1.3 Back surface contamination........................................................109 5.2.2 Solutions to the Device Rel ease with Contamination..........................110 5.2.2.1 Surface debris prevention............................................................111 5.2.2.2 Sidewall contamination control...................................................111 5.2.2.3 Backside surface contaminant removal.......................................114 5.3 Thermal Effect in the Device Release...........................................................114 5.3.1 Mechanism of the Undercut Caused by Thermal Effect......................115 5.3.2 Fabrication Method for the Suspended MEMS Devices.....................122 5.4 Summary........................................................................................................127 6 DEVICE CHARACTERIZATION..........................................................................128 6.1 Device Package..............................................................................................128 6.2 Test Setups.....................................................................................................130 6.3 3-Axis Accelerometer Test Results...............................................................130 6.3.1. Mechanical Test Results......................................................................132

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ix 6.3.2. On-Chip Circuit Test............................................................................136 6.3.3. Quasi-Static Response.........................................................................137 6.3.4. Noise Measurement.............................................................................139 6.3.5. Dynamic Test.......................................................................................145 6.3.5.1 Waveforms..................................................................................146 6.3.5.2 Dynamic ranges...........................................................................146 6.3.5.3 Inter-axis coupling.......................................................................148 6.3.6. Stability and Temperature Performance..............................................150 6.3.6.1. Offset drift..................................................................................150 6.3.6.2. Temperature performance test....................................................151 6.3.7. 3-Axis Accelerometer Performance Summary....................................156 6.4 Test on The Single-Axis Accelerometer........................................................157 6.5 Summary........................................................................................................159 7 CONCLUSION AND FUTURE WORK.................................................................160 7.1 Summary and Conclusion..............................................................................160 7.2 Future Work...................................................................................................162 APPENDIX A LAYOUTS OF TEST STRUCTURES FOR PROCESS CHARACTERIZATION..........................................................................................164 B PIN-OUT OF ACCELEOM ETERS AND BONDING PAD CONFIGURATION.................................................................................................166 C PROPOSED WAFER-LEVEL FA BRICATRION PROCESSES...........................167 Wafer Level Process I...............................................................................................167 Wafer Level Process II.............................................................................................169 LIST OF REFERENCES.................................................................................................172 BIOGRAPHICAL SKETCH...........................................................................................184

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x LIST OF TABLES Table page 1-1 Summary of previous work on bulk mi cromachined capacitive accelerometers.....15 2-1 Comparison of plasma etch in IC and MEMS.........................................................23 2-2 Influences of etching parameters on RIE etch results..............................................34 2-3 Anisotropic SiO2 etch recipe on the Plasma Therm SLR770 ECR RIE system.......42 2-4 Input parameters in the sili con ASE on STS ICP DRIE system..............................48 2-5 CMOS-MEMS accelerometer design rules extracted from the experimental results.......................................................................................................................5 8 3-1 Dimensions of the microstructu res in the test accelerometer...................................68 4.1 The major specifications of the design ed single and 3-axis accelerometers............76 4-2 Dimensions of the lateral accelerometer..................................................................80 4-3 Predicted performance of the designed single axis accelerometer...........................82 4-4 Structural dimensions of th e designed 3-axis accelerometer...................................85 4-5 Predicted performance of the designed 3-axis accelerometer..................................92 5-1 Dimensions of the z element and th e parameters used in the analysis...................119 6.1 Instruments and setups for the charac terization of fabricated accelerometers.......132 6-2 Summary of the inter-axis coup ling of the 3-axis accelerometer...........................150 6-3 Performance summary of the fabricated 3-axis accelerometer and a comparison between the this device and the ADXL330 from Analog Device..........................156 6-4 Performance summary of th e single-axis accelerometer........................................158

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xi LIST OF FIGURES Figure page 1-1 A lateral accelerometer fabricated using the thin film CMOS-MEMS technology..................................................................................................................8 1-2 SEM images of some sensing comb fi ngers in an integrated accelerometer fabricated using the previous DRIE CMOS-MEMS process.....................................9 1-3 Typical applications and perfor mance requirements of accelerometers..................11 1-4 Achievable device performance versus device size with diffe rent technological approaches shows the advantage of the DRIE CMOS-MEMS technology.............16 2-1 Seven steps of the etch process in RIE.....................................................................24 2-2 Four basic etch mechanisms.....................................................................................25 2-3 Configurations of ECR and ICP system...................................................................29 2-4 System response of the input parameters in a SiO2 RIE system..............................34 2-5 SiO2 etch rate as functions of system parameters....................................................35 2-6 Impact of the SiO2 etch on the top Al layer.............................................................37 2-7 Profiles of the CMOS stack at different process stages...........................................38 2-8 Inhibitor polymer formation in SiO2 etch................................................................40 2-9 SiO2 etching rate as the function of oxygen concentration in the CHF3/O2 gas mix............................................................................................................................ 41 2-10 Inhibitor polymer formation as the function of oxygen c oncentration in the CHF3/O2 mixture......................................................................................................42 2-11 Configuration of the STS ICP ASE system.............................................................45 2-12 Alternate etching and pa ssivation in Bosch process................................................46 2-13 Scallops formed on the sidewall of the etched structures showing the alternate etching and passivation cycl es in Bosch process.....................................................47

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xii 2-14 Etch rate per cycle using the recipe in Table 2-4 with varying etch duration..........49 2-15 Smooth sidewall in Si DRIE ach ieved with a lower etch rate..................................50 2-16 The tuning of etch profile by ch anging the etch/passivation ratio...........................51 2-17 Sidewall profiles of the comb fingers......................................................................52 2-18 ARDE effect and its influence on th e trench profile and etching rate.....................55 2-19 Etching profile of the sensing comb fingers.............................................................57 3-1 Cross-sectional view of the thin-film CMOS-MEMS process................................62 3-2 Cross-sectional view of the pro cess flow of DRIE post-CMOS MEMS technology................................................................................................................65 3-3 LVD electrothermal micromirror fabr icated using DRIE post-CMOS MEMS technology. The inset shows the undercut on the mirror plate and actuation frame, which is caused by the undercut of bimorphs...............................................67 3-4 Fabricated lateral accelerometer usin g previous DRIE CMOS MEMS process......69 3-5 The improved process flow of new DRIE post CMOS MEMS technology............72 4-1 Lumped model and equivalent electri cal circuit of the single axis capacitive accelerometer...........................................................................................................77 4-2 Fully differential configurati on of the lateral accelerometer....................................78 4-3 Schematic 3D model and mechanical spring configuration of the single-axis accelerometer...........................................................................................................79 4-4 Schematic 3D model of the 3-axis accelerometer and layout of devices designed....................................................................................................................84 4-5 Differential connection of the sidewall capacitors in z-axis sensing element..........88 4-6 Capacitance change in the range of -50 g to +50 g in z direction shows a good linearity.....................................................................................................................9 0 4-7 Z capacitance coupling from the lateral motion.......................................................95 4-8 The relation between capacitance change and the number of volume elements in mesh shows a convergent trend, indicati ng the reliability of the simulation...........96 5-1 A cluster of the residual byproduct formed in the aluminum plasma etch using Cl2/Ar chemicals......................................................................................................99

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xiii 5-2 The mechanism and result of the sidewall protection in the aluminum wet etch..101 5-3 Formation of the Al sidewall protection spacers on the isolation beams...............102 5-4 SEM photographs of the etched-throu gh comb fingers. The narrow connections along the ends of the comb fingers are cau sed by the micromasking effect of the contaminant on the sidewall of isolation trenches.................................................104 5-5 Schematic of the contamination in the plasma etch...............................................104 5-6 Front side surface contamination cause d by the physical process in the plasma etch.........................................................................................................................10 6 5-7 Structure connection caused by the debris on the front surface generated in the plasma etch.............................................................................................................106 5-8 SEM image and EDS spectrum of part of an isolation trench and peripheral structures................................................................................................................108 5-9 SEM image and schematic profile of an isolation trench sidewall with rough surface....................................................................................................................109 5-10 Fabrication method using a dditional etch on backside..........................................113 5-11 Undercut caused by the ove rheating of the structure.............................................116 5-12 Model of the z sensing element for temperature rise estimation............................119 5-13 Calculated temperatur e rise on z proof mass.........................................................120 5-14 Lateral undercut on the ro tor sensing finger of z elem ent. The back surface of the z block is also deteriorated due the higher temperature on the block..............122 5-15 Modified accelerometer fabricati on process with photoresist coating on backside..................................................................................................................124 5-16 Etched-through structures observed th rough photoresist coated on the backside of the device...........................................................................................................125 5-17 Fabricated device with mo st structures released. The structure damage caused by the thermal effect is avoided by coat ing photoresist on the backside of the device.....................................................................................................................126 6-1 Photographs of the packaged device......................................................................129 6-2 3-axis accelerometer test PCB board.....................................................................129 6-3 Sensing comb fingers on a 3-axis accelerometer...................................................131

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xiv 6-4 Block diagram of the Scanning Laser Doppler Vibrometer setup for z-axis resonant frequency test...........................................................................................134 6-5 The scanning area on the z-axis proo f mass and the frequency response of the motion in the scanned area.....................................................................................135 6-6 The detected acceleration versus driving frequency around the z-axis accelerometer resonant frequency..........................................................................136 6-7 Quasi-static test setup.............................................................................................138 6-8 Responses of the 3-axis accelerometer to 1g acceleration...................................139 6-9 Electronic noise density of y-axis inte rface circuit which has an overall gain of 44.5 dB...................................................................................................................141 6-10 The output spectrum of y-axis a ccelerometer at 200 Hz under 0.05g of sinusoidal acceleration. The sensitivity was 560 mV/g.........................................142 6-11 The output spectrum of z-axis accele rometer at 200 Hz under 0.5g of sinusoidal acceleration. The sensitivity was 320 mV/g...........................................................143 6-12 The output spectrum of y-axis accelero meter at 200 Hz without acceleration input. The sensitivity tested was 260 mV/g...........................................................143 6-13 Mounting method of the test board and reference accelerometer on shaker table.146 6-14 Output waveform of a z-axis a ccelerometer under 1g acce leration at 160 Hz. One grid in the lateral axis stands for 2.5 ms.........................................................147 6-15 Dynamic response of z-axis to 50 Hz sinusoidal acceleration...............................148 6-16 Spectrums obtained in the cross-talk test...............................................................149 6-17 Y-axis offset drift observed in duration of 48 hours..............................................150 6-18 Experimental setup for the co mb drive curling calibration....................................152 6-19 Surface profiles of latera l sensing comb fingers....................................................154 6-20 Net curling displacements on latera l comb fingers as the function of temperature.............................................................................................................155 6-21 Quasi-static response of the single-axis accelerometer The output instrumental amplifier on the test boa rd has a gain of 2.............................................................157 6-22 Measured noise density of the si ngle-axis accelerometer with a small acceleration input at 50 Hz. A gain of 2 was used in the output INA....................158

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xv A-1 Layouts of on-chip test structures..........................................................................165 B-1 Pad configuration and PLCC pin-out.....................................................................166 C-1 Proposed wafer-level process fl ow for backside etch steps...................................168 C-2 Wafer level process with isolati on trench refilling and wafer-bonding.................171

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xvi Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DEVELOPMENT OF DRIE CMOS-MEMS PROCESS AND INTEGRATED ACCELEROMETERS By Hongwei Qu August 2006 Chair: Huikai Xie Major Department: Electrical and Computer Engineering Plasma etch based CMOS MEMS technologies have the advantage of monolithic integration of sensors and conditioning electr onics, which yields small size, low noise and low cost of the devices. In this thesis work, a new deep reactive-ion-etch (DRIE) based post-CMOS MEMS microfabrication technology was developed, and single-axis and 3-axis integrated accelerometers were fabricated using the new microfabrication technology. Compared to the previous CMOS -MEMS technological ap proaches, the new microfabrication technology features the capab ility of monolithic integration for high performance MEMS sensors. The integrated accelerometers demonstrate small size, high sensitivity and high resolution with low power consumption. They can be used in a large spectrum of applications incl uding human activity monitoring, engineering measurement, security, and portable electronics. Detailed post-CMOS microf abrication processes are pr esented. Reactive-ion-etch (RIE) and DRIE tools and pro cesses are tuned to satisfy the technological requirements

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xvii of the device fabrication. Some general desi gn rules are extracted based on the systematic characterization of the etching tools. Speci al techniques were de veloped for aluminum wet etch and electrical isolation etch. The th ermal issues in the device fabrication were identified and an alternate fabrication pro cess was developed to avoid the device damage due to the overheat in the plasma processes. Wafer-level fabrication processes are also proposed. Detailed design of 3-axis and single-ax is accelerometers is presented. Device performance is predicted based on the calcula tions and finite-element analysis (FEA) using Coventor, a commercial FEA tool. The Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 m technology is used for the CMOS fabrication. With power consumption of 1 mW in each ax is, the fabricated 3-axis accelerometer achieves sensitivities of 560 mV /g and 320 mV/g in the lateral and z axes, with noise floors of 12 g/ Hz and 110 g/ Hz, respectively. The single-axis accelerometer achieves a sensitivity of 90.1 mV /g with a noise floor of 60.7 g/ Hz. The non-linearity in all lateral axes is less than 0.35%.

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1 CHAPTER 1 INTRODUCTION The last couple of decades have been seeing the emergence and prevalence of Micro-Electro-Mechanical Systems (MEM S) technology. Many MEMS products, from the first generation of pressure sensor s to newly developed integrated MEMS accelerometers and gyroscopes[1-4] have been commercialized at a fraction of the cost and size of conventional de vices. Manufacturing technolog ies have been developed specifically for MEMS, and some MEMS foundry services such as MUMPS and MEMS-Exchange are now available comme rcially [5-7] to MEMS community. However, these fabrication technologies are more research oriented and often incompatible with mainstream Complementary Metal-Oxide Semiconductor (CMOS) technology. The requirement of separate si gnal-conditioning circuitry, which in turn requires multi-chip assembly, makes the packaging of MEMS devices complicated and expensive. Small size, multi-function and low cost are the ultimate goals of commodity MEMS devices. One way to achieve these goals is the monolithic integration of MEMS technology with the standard inte grated circuit (IC) technolo gy. In fact, the crossover of the conventional IC industry and the fast -growing MEMS technology has led to many newborn technologies in the past years. Much effort has been made and large capital has been invested into CMOScompatible MEMS technology, or CMOS-MEMS. With assorted approaches, MEMS

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2 devices have been directly integrated with CMOS circuits, allowing smaller device sizes and higher performance. In this thesis research, a new post-CMOS MEMS technology is developed, and two integrated devices a 3-axis and a single-axis accelerometer are demonstrated based on this deep reactive-ion etch (DRIE) CMOS -MEMS technology. Device microfabrication processes are investigated in detail. Device design is describe d and the characterization of the fabricated devices is presented. This chapter summarizes the related CMOS-MEMS technologies and previous work on MEMS accelerometers. The organization of the thesis is given at the end of the chapter. 1.1 CMOS-MEMS Technology The integration of MEMS technology w ith the mainstream CMOS technology is referred to as CMOS-MEMS technology. This approach can be classified in three categories: pre-CMOS, inter-CMOS and pos t-CMOS technology [8], determined by when the MEMS processing is perfor med relative to the CMOS processing. 1.1.1 Preand Inter-CMOS MEMS Technology In the pre-CMOS technology represented by iMEMS developed by Sandia National Laboratory, MEMS struct ures are pre-defined before CMOS processes [9]. PostCMOS release processes are still required in device fabrication. Analog Device, Inc (ADI) adapted Sandia’s approach and de veloped a MEMS technology based on its BiCMOS process. This iMEMS technology, originally dedicated to CMOS-MEMS accelerometer and gyroscope fabrication, is an intermediate-CMOS MEMS, or interCMOS MEMS technology, in which LPCVD po lysilicon deposition and annealing are inserted into CMOS process steps for the form ation of inertial sensor micor structures

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3 [10, 11]. Infinion’s pressure sensor is also fabricated using this type of inter-CMOS MEMS technology [12]. To reduce the residu al stress in structural polysilicon, high temperature annealing of polysilicon is nor mally required in inter-CMOS MEMS, which could pose a potential risk to previous CMOS layers. Contamination caused by the process switch between microfabrication of MEMS structure and normal CMOS steps would be another serious problem. Therefore, usually a dedicated foundry is required for inter-CMOS MEMS technology. Since most preand interCMOS MEMS technologies were developed for surface micromachining with polysilicon as the stru ctural material, they suffer from some limitations as the following [13]: Mechanical performance of polysilicon is not as good as that of single crystal silicon (SCS). The structure size is li mited by the residual stress of thin-film structures. The smaller mass will result in higher thermo-mechanical noise in devices such as accelerometers where a large proof mass is required for high resolution. The curling of thin-film structures due to residual stress will severely reduce both the mechanical and electrical performa nce of MEMS devices. The temperature dependence and robustness of the de vice will be degraded as well. In the electrical domain, the parasitics be tween the polysilicon structures and the substrate underneath will reduce the out put signal dramatically. In a surface micromachined polysilicon accelerometer, depending on the polysilicon wiring path, the parasitic capacitance can be as hi gh as the order of pF [14], which could be several times larger than the sensing capacitance. This will lower the resolution and sensitivity of the device. Many thin-film polysilicon MEMS structures are fabricated using wet release in which the sacrificial SiO2 layer is etched by HF. Although vapor phase etch can be employed, stiction problems become severe when the feature size of a device is reduced to a few microns. The processes need to meet very stringe nt criteria to elim inate the potential contamination to the following CMOS process steps. The limited foundry availability, especial ly for inter-CMOS MEMS foundries, makes the overall cost of MEMS devices relatively high.

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4 1.1.2 Post-CMOS MEMS Technologies Post-CMOS MEMS technology has a potenti al to overcome the above-mentioned drawbacks by providing robust and sensitive dete cting structures. In contrast to both preCMOS MEMS and inter-CMOS MEMS, in post-CMOS MEMS technology, the fabrication of the CMOS circuitry and MEMS structures are perf ormed independently. This makes it possible to integrate high perf ormance mechanical structures made of bulk materials with high performance electronics. There are mainly two integration methods for post-CMOS micromachining. The first one is to add MEMS structures on the CMOS substrate, leaving the CMOS layers un-etched during the structure microfabri cation. The second is to form the MEMS structures by performing micromachining direct ly in the CMOS thin film layers and/or substrate. These two processing met hods are addressed as the following. 1.1.2.1 Additional MEMS structu res on CMOS substrate By adding additional layers onto a CMOS substrate, both metal, dielectric and other semiconductor materials with desired mech anical properties can be used to form MEMS structures. Because of its low process temperature, electroplating is frequently employed in the formation of metal micro st ructure [15]. In Texas Instruments’ popular digital micromirror devices (DMDTM), a sputtered metal is used as the mirror structural material and deep-UV hardened photoresist is used as the sacrif icial layer [16]. A research group at UC-Berkeley develope d a modularly integrated MEMS technology (MOD-MEMS) in which both polysilicon and po ly-SiGe can be used as structural materials. However, when polysilicon was used as the structural material in this MODMEMS technology, the aluminum interconnection in standard CMOS technology must be replaced with refractory metals such as tungsten to satisfy the high temperature

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5 requirement for polysilicon ann ealing [17]. Moreover, a TiN4 barrier layer should also be added to prevent the reaction between silicon and tungsten. These metallization steps are non-standard CMOS processes and can introduc e further residual stresses in polysilicon structural layers. A low temperature proce ss in which SiGe is used as the MEMS structural material was deve loped recently by the same gr oup at Berkeley and a SiGe resonator was demonstrated [18] using this process. In this MOD-MEMS technology, insitu p-doped polycrystalline SiGe was de posited at approximately 450C using low pressure chemical vapor deposition (LPCVD) and etched with conve ntional reactive ion etch (RIE). Germanium was used as sacrificia l layer since it could be easily etched using H2O2, with a high selectivity over oxide, poly SiGe (if Ge concentration is less than 70%) and metal. Unfortunately, due to the low deposition temperature, the mechanical properties of poly SiGe were not as good as those of polysilicon. Moreover, the laser melting annealing (ablation) needed in this proc ess also introduces stress gradient in poly SiGe thin films. Therefore, currently this ma terial is not suitable for MEMS devices such as MEMS accelerometers. Accelerometers made of electroplated coppe r on silicon substrate have also been demonstrated [19]. Potentiall y, the integration of electropl ated MEMS structures with CMOS substrate is achievable, although the contamination of heavy metal ions to the CMOS circuit is possible. In addition to the formation of MEMS stru ctures on top of CMOS substrate by thin film deposition, wafer bonding provides another me thod to directly integrate the wafers containing MEMS structures on CMOS substrat e wafer. This approach is exemplified by the fabrication process of a polysilicon thin film accelerometer [20]. In this

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6 accelerometer, the prefabricated polysilicon cap acitive acceleration sensor was bonded to the substrate wafer on which electrodes and CMOS read-out electronics were also prefabricated separately. In another wa fer-bonded piezoresistive accelerometer, the micromachined bulk silicon proof mass was sa ndwiched by a bottom glass cap and a top CMOS chip in which the conditioning circuit was pre-fabricated [21]. 1.1.2.2 Formation of MEMS in CMOS substrate In the second type of post-CMOS MEMS the CMOS surface layers and silicon substrate can be used to create surface and bulk MEMS structures. A high-Q RF MEMS filter with inter-metal dielectric layer as the structural material was reported by IBM [22]. A medical tactile sensor array was also reported in which the aluminum sacrificial layer was etched from the backside of the wafer after the CMOS substrate was etched completely [23]. A research group at ETH in Switzerland processes bulk silicon substrate of CMOS wafer with anisotropic wet etch to obtain thin film and bulk MEMS devices [24]. For thermal sensors in which membranes consisting of dielectric layers are needed for thermal isolation, substrate silicon can be etched completely to obtain the suspended dielectric membranes [25]. The silicon dioxide membrane acts as an intrinsic etch stop layer in a backside silicon anisotropic we t etch using KOH or TMAH solution. Using this anisotropic wet etch based post-CMOS pro cess, 256-pixel thermal imager arrays and multifunctional chemical sensors have been developed [26, 27]. Recently, a monolithic CO gas sensor with an integrated hotplat e was reported from the same group [28]. By combining the electrochemical stop techni ques with KOH anisotropic etch, silicon membranes with n-well islands can be obt ained. In this auto-stop technique, the anisotropic etch stops at the pn junction [29]. This process ca n be specifically used in the fabrication of highly sensitive pressure and force sensors [30]. By combing silicon

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7 anisotropic wet etch with deep reactive i on etch (DRIE), some sophisticated surface and bulk MEMS structures such as bridges and cantilever arrays can be created. A multisensor system was demonstrated usi ng the combined etch processes [31]. The main challenge in the wet post-CMOS MEMS technology is the protection of the CMOS structures. When etch stop is re quired for silicon diaphragm formation, the preparation for electrochemical process also increases the complexity of the process. Also, in most cases, precise double-side alignm ent is required in the fabrication of silicon islands using wet etch. The technological approaches developed by Carnegie Mellon University differ from those described above in that only dry et ch steps are used to create both surface and bulk MEMS structures [32, 33]. Dielectric laye rs and bulk silicon substrate are etched by isotropic/anisotropic RIE and DRIE respectiv ely, avoiding the potenti al stiction problem that is common to wet release processes. Th is dry technology show s another particular advantage in that it is a maskless process, wh ere CMOS metal layers act as masks in the dry etch steps. The MEMS structures are pr e-defined by the proper arrangement of metal layers; thus no lithography is needed in this post-CMO S micromachining process. Moreover, multi metal layers (normally 3~6 layers from different CMOS technologies and foundries) make the wiring of the devices fl exible which in turn reduces the parasitic effects and improves the electrical performance. This approach was originally developed fo r thin film MEMS structures in which mainly surface micromachining was involved [34]. A device based on a copper CMOS technology was also reported [35]. The size of the MEMS structures fabricated using this post-CMOS surface micromachining was strictly limited due to the large curling of thin-

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8 film structures caused by re sidual stresses. The maximum device size achieved was about 400 m400 m. Meanwhile, the strong temperature dependence of the thin-film MEMS structures caused by the mismatch of the te mperature coefficient of expansion (TCE) of the materials in the thin film s also limited their reliable application. Figure 1-1 shows the SEM image of a single-axis accelerometer fa bricated using the thin film CMOS-MEMS technology [36]. Figure 1-1. A lateral accelerometer fabricated using the thin film CMOS-MEMS technology. Device size is limited due to th e large curling of the thin film structures. After Luo, with permission [36]. A DRIE CMOS-MEMS process was deve loped later based on the surface micromachining described above. In this DRIE CMOS-MEMS technology, single crystal silicon (SCS) was etched using DRIE to fo rm bulk MEMS structures [33]. This DRIE CMOS-MEMS technology has shown great advantag es in the fabrication of relatively large MEMS devices such as micromirrors [ 37]. A large flat mirror can be obtained with bulk silicon existing underneath the alumin um mirror surface. However, when fine structures such as comb drives are fabricat ed through this process, the isotropic undercut Proof mass Spring Sensing fingers Hinge

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9 needed for the formation of electrical isolati on structures will have some severe effects on MEMS structures. Figure 1-2 shows the SEM images of sensing comb fingers in a CMOS-MEMS integrated accelerometer fabricated using the previous DRIE CMOSMEM process [38]. The SCS unde rneath the comb fingers was severely undercut when isotropic etch was performed to undercut the end of the fingers where the isolation beams are located. Figure 1-2. SEM images of some sensing comb fingers in an integrated accelerometer fabricated using the previous DRIE CMOS-MEMS process. SCS underneath the fingers was severely undercut when isotropic etch was performed for isolation beam undercut. Images were taken at orthogonal angles. Isolation beams Severe undercut on SCS

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10 In this thesis work, a new process is de veloped to overcome the drawbacks of the previous DRIE post-CMOS technology. As a demonstration of the new process, an integrated 3-axis accelerometer and a si ngle-axis accelerometer are designed and fabricated using the developed new technology. 1.2 MEMS Accelerometers The accelerometer is one of the firs t devices demonstrated using MEMS technology. Since the early 1990’s, MEMS acce lerometers have been dominating the fast-growing market of inertial sensors. Analog Devices is one of the major MEMS accelerometer suppliers. After it shipped its fi rst iMEMS™ accelerometer in the year of 1994, it took about 10 years for the market to grow to 100 million units. As accelerometers have found enormous applicatio ns beyond its original business of air-bags in automotives, ADI will ship its second 100 million MEMS accelerometers in only two and half years [39]. The wide spectrum of applications for MEMS accelerometers is at tributed to their small size, high sensitivity and low cost due to the large product volume. The conventional applications for accelerometer s include automotive safety, inertial navigation and guidance, seismetic and engi neering monitoring, explosion measurement in oil drilling, etc. Newer applications of MEMS accelerometers relate to the intelligent data carrier systems, in which data l ogging/transfer is used between monitoring accelerometers and the data processing center. Wireless communication is essential in many of these data carrier sy stems. Other typical applicat ions include management of rental vehicles, monitoring and tracking of cargo or goods in logistics systems, working condition and health monitoring. Figure 1-3 illustrates the typical applications and performance requirements for accelerometers in these applications[40]. To date, the

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11 fastest growth of MEMS accelerometers is in the consumer electronics industry. The prevalence of portable electronics and pers onal communication tools have tremendously boosted the need for small-sized MEMS acceler ometers and gyroscopes. Several models of cellular phones and personal data assistan ts (PDA) have been reported to perform certain functions using just sp ecific hand motions in different directions [41]. Computer and game peripheral manufactures are increas ingly integrating MEMS accelerometers in their products. The handheld electronics market is expected to exceed 600 million units in 2005, in which MEMS inertial sensors are expect ed to play a major role by enabling new functionalities and ease of operation. Figure 1-3. Typical applications and perf ormance requirements of accelerometers. 10-6 10-4 10-2 1102 104 10-1 10 1 102 103 104 Bandwidth ( Hz ) Acceleration (g) Explosion monitoring Engineering monitoring and security Air bags Virtualization and portable electronics Logistic management Inertial navigation

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12 1.2.1 Sensing Mechanisms of MEMS Accelerometers In principle, many physical effects can be used for acceleration or position sensing. The first micromachined accelerometer commercialized by NovaSensor was piezoresistive [42]. The main advantages of piezoresistive accelerometers are the simplicity of their structures and fabrication processes as well as the read-out circuits. However, piezoresistive devices have some critical drawbacks such as low sensitivity and large temperature dependence. Complex temp erature compensation circuits are often needed and a very large proof mass is e ssential for an accep table sensitivity. The capacitive sensing mechanism is dominant in MEMS accelerometers for several reasons. Both surface and bulk micromach ining can be used to fabricate a variety of capacitive accelerometers with perfor mance ranging from the low-end automotive application grade to the high-precision inertial navigation grade. Compared to piezoresistive accelerometers, capacitive accelerometers have high sensitivity, low power consumption, low noise level, st able dc characteristics and less temperature dependence. Their simple structures and fabrication pr ocesses make the integration of conditioning circuits with sensing elements more straightforward. Due to these advantages, integrated capacitive accelerometers are the primary fo cus for the booming portable electronics industry. While capacitive and piezoresistive sensi ng are two of the most common sensing mechanisms, other physical mechanisms such as resonant frequency shift, thermal transfer and quantum electron tunneling have been exploited as well for the acceleration and motion sensing. A micromachined vibrating beam accelerometer and a vacuum packaged resonant accelerometer have been reported respectively [43, 44]. In both resonant accelerometers, the force generated by the external acceler ation on the specially

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13 designed proof mass changes its resonant frequency. Therefore, the acceleration is measured in terms of a shifted resonant fre quency of the resonant device. The apparent advantage of the resonant accelerometer is its direct digital output. Thermal accelerometers have also been developed ba sed on the principle of convection heat transfer [45, 46]. Since there are no movable elements in this thermal accelerometer and the manufacturing variations do not influen ce the thermal performance of the device, these thermal accelerometers demonstrate very good robustness and good batch reproducibility. To achieve high sensitivity, cu rrent tunneling effects have also been exploited for sensing acceleration. [4749]. These accelerometers measure the displacement operating on the principle of quantum electron tunneling, which has very high position sensitivity. A resolution of 20 / ngHz has been accomplished by the reported micromachined tunneling accelerometer [50]. This particular accelerometer requires very specific technologi cal processes. The complexity of the fabrication and strict conditioning circuit design make it very difficult for this tunneling accelerometer to be commercialized. Other accelerometers using optical, piezo electric and electromagnetic sensing mechanisms have been demonstrated [5154]. However, the integration of these accelerometers with CMOS technology is a challenge. 1.2.2 Capacitive MEMS Accelerometers Due to their prevalence, capacitive MEMS accelerometers are discussed in more detail in this section. Technologically, MEMS capacitive acceleromet ers can be categorized into three types: thin-film accelerometers fabricat ed using surface micromachining; bulk

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14 accelerometers fabricated using bulk microm achining and/or wafer bonding technology; and other accelerometers fabricated using mo re exotic processes. Surface micromachined accelerometers, e.g., polysilicon thin film capacitive accelerometers, have been commercialized for more than ten years. They are available in large volume at very low unit price [1]. However, due to their small proof mass, typically they can only achieve several tens to several hundreds of / gHz noise floor [55-57]. This constrains their applications to only middle and low end de vices and systems. Today, many high-end inertial sensors are st ill dominated by very expens ive non-MEMS or piezoelectric devices. In capacitive sensing, normally micro-g resolution can only be realized by bulk accelerometers with large proof masses. Many of the reported high-performance capacitive accelerometers use multi-wafer bondi ng or SOI technology to form a large, thick proof mass [58-61] Some special processes such as wafer dissolving, double-side process and thick Epi-SOI are also utilized in the fabrication of bulk micromachined capacitive accelerometers [6264]. Recently a high-sensitiv ity bulk silicon capacitive accelerometer with a mechanical noise floor of 0.18 / gHz was reported [65]. All these reported bulk micromachined capacitiv e accelerometers employed wet etches to form the large proof masses. The special t echniques such as wafer bonding and automatic stop in wet etching complicates the fabrication. If glass is used in wafer bonding to form silicon-on-glass (SOG) accelerometers [66], th e temperature performance of the devices could be degraded due to the mismatch of th e thermal expansion coefficients between the glass substrate and the sensing element. SO I technology makes the fabrication and further

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15 monolithic integration of the accelerometer very costly. The previous works on bulk micromachined capacitive accelerometers are summarized in Table 1-1. Table 1-1 Summary of previous work on bul k micromachined capac itive accelerometers. Contributors Published year Structure and/or process used Accelerometer performance (noise floor) Rudolf et al [58] 1990 Sa ndwiched silicon-glass 1.0 / gHz Henrion et al [59] 1990 Sa ndwiched silicon-glass, Multi-step wet etch 120 / dBgHz 260 Hz bandwidth Warren [60] 1994 SIMOX N/A Bernstein et al [61] 1999 Silicon-glass bonding Dual chips Combination of wet and dry etch Automatic wet etch stop 1.0 / gHz 1 kHz bandwidth Yazdi, et al [63] 2000 Combination of bulk and surface micromachining Wet release 0.23 / gHz Yazdi et al [65] 2003 Combination of bulk and surface micromachining Wet release 0.18 / gHz Chae et al [62] 2005 SOG structure Silicon-glass bonding Silicon thinning by CMP Dry release 79 / gHz Other non-mainstream technologies were reported for fabrication of specific capacitive accelerometers as well [67-69]. These technologies require some unique processes and equipments which are curren tly cost-prohibitive for commercialization. The DRIE post-CMOS MEMS technology can be used in bulk micromachining for in-plane or out-of-plane capacitive sensing devi ces. It has the capability of creating thick structures with pure dry etch which avoids the problems in wet release. An in-plane driving, out-of-plane Coriolis acceleration sensing gyroscope has been demonstrated using this bulk DRIE postCMOS MEMS technology [70].

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16 The achievable device performances ve rsus device sizes with different technological approaches men tioned above are further illust rated in Figure 1-4. DRIE CMOS-MEMS technology has advantages of monolithic integration of bulk MEMS structures and interface circ uits fabricated using mainstream CMOS technologies, allowing MEMS devices with overa ll higher system performance. In this work, 3-axis and single-axis singl e-crystal silicon (SCS) accelerometers are designed and fabricated using an improve d DRIE post-CMOS MEMS technology [71]. Figure 1-4. Achievable de vice performance versus device size with different technological approaches shows the advantage of the DRIE CMOS-MEMS technology. Qu et al IEEE Sensors, 2004 Qu et al HH, 2006. Lemkin, 1997 : 110 ADXL105: 225 STM: 50 Luo, 2000 : 1000 Wu, 2004 : 50 1 10 100 Hybrid bulk technology 103 102 1 10-1 Thin-film technology 10 Yazdi et al, 2000 : 0.18 (wafer bonding) Chae et al, : 0.23 (SOG) Bernstein et al : 1.0 Chae et al, 2004, 1.6 Chae et al, 2005 : 79 (SOG) Integrated DRIE CMOS-MEMS Noise floor (g/ Hz) Footprint (mm2)

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17 1.3 3-Axis CMOS-MEMS Accelerometers Millions of portable personal electronics re quire smaller inertial sensors for easier operation and more functional ity. Integrated dualor tr i-axis accelerometers are advantageous for these portable devices in terms of compact size and multi-axis sensing. The first monolithic single-axis accelerometer was industrialized by ADI [72]. Later on, dual-axis monolithic accelerometer s were also commercialized. Recently triaxis integrated accelerometers have been released by a few industrial companies [3, 4, 73, 74]. The majority of multi-ax is accelerometers in the ma rket are hybrid, where singleaxis sensing elements and conditioning circuits are assembled together and packaged in the same enclosure. There is a tradeoff between the monolithic integration and hybrid approaches. The advantages of monolithic integration are smaller device size and better signal conditioning. But these advantages are at tained at the cost of more complicated fabrication processes. The hybrid soluti on, on the other hand, allows optimized mechanical structures and signal processing ci rcuits to be realized by dedicated and wellestablished fabrication processes. The draw backs include the relatively large package sizes and large parasitics caused by the wi ring and bonding between the sensing elements and the signal processing a pplication-specific IC (ASIC). Some high performance hybrid capacitive accelerometers were reported from both industry and academic institutes [62, 66, 75, 76]. Multi-axis accelerometers employing other se nsing mechanisms are also available. With proper design of the suspending beam s and the configurati on of piezoresistive bridge, 3-axis piezoresistive accelerometer s with a single proof mass can be easily achieved using SCS or SOI [21, 77]. Some 3-axis piezoresistive accelerometers are already available as volume products [78, 79].

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18 However, in most of the reported monolithic dual-axis or tri-axis accelerometers, separated in-plane and out-of -plane proof masses are used. Or, at least the out-of-plane element for z-axis sensing is separated from the lateral element where x, y-axis sensing parts share the same proof mass [80]. The a dvantage of the separated proof masses is usually the reduced cross-talk between the se nsing axes. Yet it is self-evident that the electrical performance is degraded by the la rger parasitic effects. In addition, this approach is less economical due to the large device size, espe cially for middle to low end capacitive accelerometers used in consumer el ectronics where small size and low cost are the main concern. The lack of 3-axis monolithic capacitive a ccelerometers with a single proof mass is due to the difficulty in the realization of vertical out-of-plane and lateral in-plane sensing using a shared proof mass. Z-axis sensing has two primary challenges. The first is how to use horizontal electrodes to sense out-of-plane displacements with the presence of large parasitic capacitances to the substrate, especi ally when differential sensing is needed. The second is how to realize large capacitance changes in the z-ax is using verti cally-oriented electrodes. In most of the reported z-axis capacitive accele rometers where the z-axis proof mass moves vertically, po lysilicon is used as the lower electrode of a horizontallyoriented sensing parallel plate capacitor. A fixed reference capacitor is also typically fabricated on the substrate. Therefore, it is difficult to have a fully differential output from the sensor node [14, 81]. Recently a z-axis sensing torsional acceler ometer with horizontal capacitors and differential output was reported [82]. Due to the asymmetric arrangement of the sensing capacitors, the satisfactory linear ity of the accelerometer is only limited to 1g. Moreover,

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19 the sensitivity of the accelero meter is extremely constrained by the process performed on a costly SOI substrate. The process is less controllable in that the formation of the horizontal gap for vertical se nsing is greatly affected by the later processes. Only a minimum of 4m vertical gap can be achieved due to the influence of the damping hole etch on the pre-defined z-se nsing gap. In another tors ional z-axis accelerometer fabricated using dissolved wafer process (D WP), acceleration in z-axis is detected by vertically-oriented interdigitat ed capacitors [83]. The cha nge of the capacitance between stators and rotors are caused by the variation of their common area instead of the change of the gap between them. A linearity of 0.2% in an acceleration range of -4 ~ 3g and a mechanical noise of 0.28 / mgHz was achieved. No differential output can be realized from the sensor node due to its mechanism. Thus, this accelerometer can not detect the direction of the acceleration in z direction. If fully-differential z sensing can be pr operly realized, the cr oss-talk among three axes can be greatly eliminated and the sharing of the same proof mass for 3-axis sensing will be feasible with proper mechanical desi gn. More recently, fully differential z-axis accelerometers using sidewall capacitance form ed by CMOS metal layers were reported [84, 85]. Due to the th in film mechanical springs employe d in these accelerometers, these devices still suffer the constrains of thin film devices. This thesis work targets an integrated 3-axis capacitive accelerometer with a shared, bulk silicon proof mass scheme [86]. With a unique z-axis sensing mechanism, fully differential sensing will be achieved in all three axes. The developed DRIE postCMOS MEMS technology will be employed in th e fabrication of this compact tri-axis accelerometer.

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20 1.4 Thesis Goals and Organization In this thesis work, a nove l DRIE post-CMOS MEMS technology is developed, and two devices a 3-axis and a single-axis integrated accelerometer are designed and fabricated based on the ne w fabrication process. In the improved DRIE post-CMOS MEMS, details of dry etch based micromachining of the designed MEMS devices with fine structures are explored. In particular, some physical effects that arise from the plasma etching and affect both the mechanical and electrical performance of su spended MEMS structur es are investigated. These detailed fabrication st udies are directed towards cr eating general design rules and optimizing the design and fabrication of ME MS devices. An integrated 3-axis and a single-axis accelerometer are de signed and fabricated to dem onstrate the features of the improved DRIE post-CMOS MEMS technology. Device design details are presented. Chapter 1 introduces the background of CM OS MEMS technologies. Particularly, the evolution of post-CMOS MEMS technolog y is presented and the prior works on a variety of non-CMOS, CMOS-MEMS capaci tive accelerometers are reviewed. Chapter 2 is a technologi cal introduction of plasma etch processes. Basic processing tools used in the developed pos t-CMOS technology are introduced. Electron cyclotron resonance (ECR) and inductively-c oupled plasma (ICP) etchers for anisotropic SiO2 etch and silicon DRIE are introduced. Etch ing system configura tions are described, and the system characterizations are detail ed based on the particular microfabrication requirements for accelerometers. Chapter 3 illustrates the DRIE post-CM OS MEMS technology and its potential applications. For comparison, thin-film postCMOS MEMS process and other previously investigated DRIE CMOS-MEMS process are also addressed.

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21 Chapter 4 focuses on the device design of the accelerometers. The mechanism of fully differential z-axis sensing is detailed in addition to the latera l-axis accelerometer design. Mechanical design and modeling of the single and 3-axis accelerometer are given, and performance of the devices is predicted. Chapter 5 discusses some specific practical issues in the fabrication of the devices. Contaminations of the surface and sidewalls of the sample during plasma processes, and their impact on the successful device release are addresse d. Thermal effects on MEMS structures in the DRIE release step are investigated. To have a better control of the etch process, especially the release step, a simplified model is created to estimate the temperature rising on the susp ended MEMS structures duri ng the plasma etch. This model helps in understanding and eliminati ng of the structure damage caused by the thermal effect mentioned above. Based on th ese observations in the microfabrication, MEMS device design rules and optimizati on considerations are discussed. In Chapter 6, the characterizations of the fabricated devices are detailed. The experimental setups are in troduced followed by test re sults. Discussions on the performance of the devices are addressed. Chapter 7 concludes the thesis work and proposes some future work including the wafer-level microfabrication pr ocesses for CMOS-MEMS devices.

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22 CHAPTER 2 DRY POST-CMOS MICROFABRICATION AND TOOLS To improve the performance of MEMS devices, a new DRIE post-CMOS MEMS technology has been developed in this thes is work. This post-CMOS micromachining consists of multiple plasma etch steps of SiO2 layer and Si substrate. Therefore, in the development of the new tec hnology, individual plasma dr y etch process should be optimized. As part of this thesis work, thick SiO2 anisotropic RIE etch and Si DRIE used in the new technology were investigated and op timized. Test structures were designed for the purpose of individual pro cess calibration and the extr action of criti cal technologybased device design rules. In this chapter, plasma etch technologi es involved in the developed DRIE postCMOS technology are introduced and the releva nt etching systems are calibrated using the test structures. The choi ce of the processes for the new technology is based on the availability of the qualified equipments locally on campus at the University of Florida. 2.1 Plasma Etch In MEMS structure release, plasma dry etch method has advantages over wet etch in structure profile control, stiction prev ention and etch efficiency. The DRIE postCMOS MEMS technology developed in this work is completely based on the plasma dry etch of SiO2 and silicon. Therefore, the control of th ese plasma etch processes is a critical issue to the fabrication and the final performance of the MEMS devices. The dielectric etch is used to open the patte rns of MEMS structures, theref ore anisotropic profiles are needed. For silicon etch, both isotropic and anisotropic processing are used. Normally, in

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23 terms of the feature size and etching depth, plasma etch in MEMS microfabrication differs from that in VLSI and ULSI. Their differences can be summarized in Table 2-1. Table 2-1 Comparison of plasma etch in IC and MEMS Plasma Etching Parameters In ICs In MEMS Devices Feature size Small Relatively large Depth Small Large Aspect ratio Small to middle Middle to large Structure refill Yes Normally No Etching time Short Long Etch induced structure damage Less More Etched surface contamination Less More There are many kinds of plasma-based et ch technologies in which both chemical and physical processes are employed for the et ch [87]. Plasma can be described as an electrically neutral ga s that contains equal numbers of positive and negative charges in addition to neutral atoms, radicals or molecules and photons emitted from the excited species [88]. Positively charged carriers are mostly ionized atoms, radicals, or molecules created by the impact of particles with elec trons. The majority of negative charges are electrons. However, when some of positive carriers capture electrons from the plasma, they can also convert themselves into ne gative charges. Neutral atoms, radicals and molecules can be in their ground states or exc ited states. When species in an excited state lose their energy via spontaneous transitions to resume their lower energy levels, photons are emitted and a plasma glow is observed. Many external parameters, such as chamber pressure, reactor geometry and residence time in the reactor, affect the composition and relative concentration of indi vidual carriers. Radicals and neutrals are main reactive species in the plasma etch. Radicals are much more abundant in a glow discharge (plasma) than ions because of their lowe r excited energy state and longer life time. However, the relative fluxes of radicals and neutral atoms are compatible. This is due to

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24 the following two factors. On one hand, ions move faster than radicals as a result of kinetic energy gained from the applied electric field. On the other hand, heavier radicals move toward the substrate mainly by diffusion. Radicals have a larger tendency to be absorbed on the reacting su rface due to their unfilled outer electron shell. The etch process in plasma can be categorized into seven steps, as shown in Figure 2-1. Figure 2-1. Seven steps of the etch process. (a) Dissociation and ionization of the reactive species. (b) Diffusion of the reactive ra dicals. (c) Absorption of radicals on surface. (d) Radical surface diffusion. (e) Chemical reaction. (f) Desorption of the by-products. (g) By-product diffusion to the chamber. Reactive species (radicals, ions, etc.) ar e generated by excitation, dissociation or ionization in the glow discharg e. By diffusion or acceleration due to the external electric field, these particles reach the substrate. Ra dicals are absorbed on the substrate surface, while ions, with their momentum, may disi ntegrate upon impact to the substrate and penetrate into the surface for a certain dept h. With the help of surface diffusion, the reactions may happen locally on the landing site of the carriers, or somewhere in the (a) (b) (c) (d) (e) (f) (g)

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25 diffusion path of the carrier on the substrate surface. Finall y, the reaction products leave the substrate surface, either by desorption if the by-products are volatile, or by ionactivated processes, and diffuse back into the plasma [87]. There are four basic etching mechanisms which contribute une qually to the etch process. They are illustrated in Figure 2-2 and their impacts on the etched materials are summarized as the following. Figure 2-2. Four basic etch mechanisms. (a) Physical sputtering. (b) Chemical reaction by neutral radicals. (c) Ion enhanced ch emical reaction. (d) Ion enhanced inhibitors. Physical sputtering. The interaction of the impinging ions with substrate surface is a purely physical process in wh ich momentum transfer is i nvolved. The substrate atoms are mechanically ejected by i ons with kinetic energy typical ly higher than 200 eV. This results in very anisotropic profiles, rough surface morphology, trenching effect and poor selectivity. The high energy i on bombardment always causes damages to the substrate. inhibitor (a) (b) (c) (d) Ions Radicals

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26 Due to its physical nature, the etching rate of sputtering is very slow, lowing the efficiency of this etch method. Chemical reaction. This etch is dominated by the chemical reaction between the neutral reactive species and th e substrate, which results in volatile by-products. The chemical reactions rely on the formation of the reactive species and their absorption on the surface of the substrate. However, the main requirement for the chemical etch is the volatility of the by-product from the reaction. Good etch rate and high selectivity can be obtained from chemical etch, and the plasma induced damage can be minimized. With less physical enhancement, chemical etch de monstrates isotropy which is unwanted for the formation of vertical profile. Energetic ion-enhanced chemical reaction. The neutral radicals slightly interact with the surface of substrate. The impinging ions alter the substrate or product layer, so that chemical reactions can take place mo re efficiently at the interface and the byproducts can be delivered more easily into the plasma. This process offers highly anisotropic features since side walls receive minimal ion flux. Ion-enhanced inhibitor. The inhibitor species form a polymer like thin film on sidewalls, which excludes the impinging neut ral etchant. This process prevents the sidewall from being etched and thus leads to an increased an isotropy. It differs from the energetic ion-enhanced reaction in that the chemical etchi ng can take place without the presence of impinging ions. Neutral etchant species spontaneously gasify the substrate material, and ions play a role by interacting with another co mponent instead of substrate material and reaction by-product. That component is the protective inhibitor film. The ion flux breaks down the protective in hibitor film on the horizontal surface which is at a right

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27 angle to the flux, allows the chemical etch to proceed anisotropically. Meanwhile, the protective film is not removed from the ve rtical sidewalls becau se these surfaces only intercept few ions scattered from other dir ections. The protective inhibitor may originate both from the involatile etch by-product or from film-for ming precursors that absorbed on the surface of substrate during the etching process. The last two ion-assisted plasma etch mechanisms dominate in most dry etching techniques that are widely used in VLSI and MEMS manufacturing and microfabricating. Reactive ion etch (RIE) is widely used in di electric etch because of its high etch rate, high selectivity and easy cont rol of the etching profile. D eep RIE provides an effective method for deep trench etch in silicon substrate to ach ieve bulk MEMS devices. Several energy coupling methods have been developed in the configuration of plasma reactors [88]. Of them electron cycl otron resonance (ECR) and inductive coupled plasma (ICP) are most widely used due to th eir high plasma density thus effective etch. Both of them can work at lower pressure and provide higher aspect ratio etching. The long mean free path (MFP) of gas molecules a nd ions due to the low system pressure can reduce the scattering collision, enabling very directional etch al ong the direction of biasing electric field. More power can be coupled into plas ma due to the high ion density sources, resulting in greater di ssociation of etch species. The main difference between an ECR and ICP system lies in the method to shape and sustain the plasma. An ECR reactor employs an external magnetic field to shape and contain the plasma; while an IC P reactor uses an inductively coupled RF bias to sustain high density ions in the disc harge [88]. The configurations of these two systems are illustrated in Figure 2-3.

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28 In an ECR reactor, microwave energy is coupled to the natural resonant frequency of the electron in the presence of a static ma gnetic filed. The resona nce of electrons in plasma occurs when the microwave excita tion frequency reaches th e electron cyclotron frequency which is given by e eeB m (2.1) where e is the unit charge of an electron, B is the strength of the static magnetic field and me is the electron mass. In practice, this requ irement can be satisfied in a discharge by adjusting the strength of the magnetic field. By presenting an elec tric field that is perpendicular to the magnetic field, as shown in Figure 2-3, the elec trons are accelerated in the ECR volume to ionize and excite the neutral species. The result is a low pressure, low collision plasma that can be tuned from a weakly to a highly ionized discharge by changing pressure, gas flow and input mi crowave power. The advantage of the ECR setup is the easy and cheap microwave power coupling, non-electrode in the system and, low heating effect resulted from the electron collisions and, ultimately, the high density ions and radicals in the plasma. ECR has gained great attractions in many plasma processing applications. On the contrary, an ICP reactor uses a ra dio frequency (RF) current applying to three coils in opposite directions to generate and alternating magnetic field in the upward and downward directions. It is the change rate of this magnetic field that induces a RF electric field which confines and accelerates electrons in a circular path. This inductive coupling is very efficient and leads to a hi gh plasma density, normally one order higher than ECR coupling. Since the electrons are tra pped in a circular path they have little chance of reaching the sample chuc k to lower the dc self-bias.

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29 Figure 2-3. Configurations of ECR and ICP system. (a) ECR etcher, (b) ICP etcher. (a) Gas inlet Microwave power Chamber Plasma glow Upper magnet Collimating magnet Powered electrode Chuck bias RF source (b) Gas inlet ICP RF source Powered electrode Chuck bias RF source ICP coil

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30 Due to the well confined electrons, anothe r RF source, driven at 13.56 MHz, is applied to the chuck which can control the dc bias separately. This configuration allows nearly independent control of ion flux (ICP power to the co ils) and ion energy (RF power to the chuck), making the tuning of the etchi ng easier. The etch rate of ICP reactor is much larger than other plasma etching t ools due to the high concentration of the dissociated radicals and ions. In addition, since the electrons are relatively confined, fewer of them are lost to the chamber walls and electrodes compared to ECR, resulting in lower dc bias and less ion damage on the sample. High density plasma can operate at lower pressure, which increases the MFP of the radicals and ions and consequently increases the anisotropy of the etching profile. No matter what kind of etcher is used, th e basic requirements for the dielectric or silicon etching in MEMS technology remain the same. Relatively high etching rate, good uniformity and profile control, high aspect ra tio and high selectivity are the main criteria for a good etching. According to the availability of the reactors around, in this thesis work, an modified PlasmaTherm ECR etcher (SLR-770) was used for the SiO2 etch and an ICP reactor from STS was employed for deep silicon etch in the development of DRIE post-CMOS MEMS technology. The etching syst em characterization was c onducted before the device fabrication. 2.2 Characterization Methodology Test structures were included on the same chips of the designed MEMS devices for the purposes of in-situ process monitoring and etching characterization. They were designed for the system characteri zation on assorted effects in SiO2 RIE and silicon DRIE, which will be detailed in the follo wing sections. Some layouts of the test

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31 structures are given in Appendix A. In SiO2 etch characterization, rectangular bars (cantilever beams after being etched) with permuted metal layer(s) were designed to characterize the etch ra te and profiles. These cantilever beams were designed to have fixed length and width. This is to exclude the effects of pr ocess variations. In silicon DRIE characterization, similar cantilever beam s with different spacing were designed to characterize the aspect-ratio dependent etching (ARDE) effe ct and the etching ratio. A Dektak II step profilometer with accur acy of 10 nm was used in the depth measurement for etch system characteriza tion [89]. In the developed DRIE CMOSMEMS technology, the top alumi num layer acts as the etchin g mask in the etching steps of the front side process. Th erefore, aluminum etching (mai nly physical milling) rate was first characterized to define the reference plan e in the measurement of etching rate in both SiO2 and Si etch. After the glass passivation la yer is etched and fresh top aluminum layer is exposed, part of the spare region on th e chip surface is covered by photoresist or Kapton tape, which has very good thermal and chemical stability. As the SiO2 RIE or Si DRIE proceeds, the uncovered aluminum area will be milled with a small rate. After certain etching time duration, a small step will be formed between the covered and uncovered aluminum area. By measuring the heig ht of the step after the removal of the photoresist or Kapton tape, and dividing it by the etch ing time, aluminum milling rate ral is obtained. Then, after an etching time of t in the following SiO2 RIE or Si DRIE, the etching rate can be calculated as, alhrt r t (2.2)

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32 where h is the height of the measured step between the exposed top aluminum surface and the surface of etching front. Since normally aluminum milling rate is much smaller than SiO2 and Si etching rate, the second term from the Al milli ng in the numerator can be neglected. A Joel 6400 scanning electron microscope (SEM) and a FEI Strata DB 235 focused ion beam (FIB) SEM were used for the etch profile observation and measurement. 2.3 SiO2 Etch In the development of DRIE postCMOS MEMS technology, RIE SiO2 etch is used to open the patterns of microstructures. After the SiO2 etch, the top metal on the CMOS stacks with alternate metal and SiO2 layers acts as the mask in the following Si DRIE. Thus the SiO2 etch quality will directly affect the final microstructures. The SiO2 RIE is a complex system in which many process variab les have impacts on the etch results. In many cases, the influences of the process parameters are non-linear and co-related. Therefore, design on experiment (DOE) is needed for the device/process design and optimization. 2.2.1 Challenges in Anisotropic SiO2 RIE Figure 2-4 shows the multiple responses of a SiO2 RIE system as a function of multiple system input parameters. The output of the RIE has some specific influences on MEMS structures due to the essential di fference between the ME MS microfabrication and the standard IC processes. Compared to the requirements of the normal IC process, RIE used in MEMS technology ha s some special challenges. The survival of the top metal layer and its profile. The SiO2 layer that needs to be etched in a MEMS device is us ually much thicker than that in the standard IC devices. This is due to the use of CMOS stacks that are consisted of a lternate metal and SiO2

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33 layers. These CMOS stacks also act as mask s in Si DRIE. The de pth of the trench between the mask stacks measures from th e surface of top metal to the interface of SiO2/Si, ranging from a couple of m to as high as ~ 12 m depending on the different CMOS technologies employed. During the longer time SiO2 etch, the top metal layer is exposed to the radicals and accelerated ions all the time, being milled physically or etched very slightly. The edges of the pa tterned top metal will be rounded and the microstructures will lose their critical dimensions. The survival of interconnect vias and electrical connection of the MEMS device. The electrical connection failu re of MEMS devices, mostly the failure of interconnect vias, may result from the SiO2 RIE. There are two mechanisms of the electrical connection failure. The first is the milling of th e top metal layer at the corners of the vias, leaving an open circuit due to the broken vi a corner. This is a phys ical process in which the ion bombardment damages via edges. The second failure mechanism is the lateral etch of the barrier layer (normally TiN) above or underneath each Al layer. On the fine microstructures with stacked CM OS layers, after the long SiO2 RIE, the barrier layer could be chemically etched through in the la teral directions on each side of the thin structures, leaving the structur e lose their electric connecti on. This lateral etch of the barrier layer can also cause th e delamination of aluminum laye rs in the MEMS structures. To satisfy the above and other more general requirements of the SiO2 RIE, etching system should be very carefully characteri zed and design rules s hould be extracted from the characterization for the successful future designs.

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34 2.2.2 System Characterization A PlasmaTherm SLR 77 0 RIE reactor was used in the SiO2 etch with CHF3/O2 as the etching chemicals. The output etch results were characterized as the functions of the system variables in Figure 2-4. Since the outpu t parameters are correlated to more than one input variable, some tradeoffs should be ma de to have an optimal etch results. DOE experiments were performed by sweeping in dividual system parameter with other parameters fixed. Figure 2-4. System response of the input parameters in a SiO2 RIE system. The correlation of the etch results with input variables can be qualitatively summarized as in Table 2-2. Table 2-2. Influences of etchi ng parameters on RIE etch results Output Input Etch rate Top metal layer milling Sidewall profile Inhibitor polymers Microwave power Varies CHF3 gas flow rate Varies Varies Varies Chamber pressure O2/CHF3 ratio Varies Varies Varies Dc bias of the sample varies Temperature Gas flow rate Loading Electrode spacing Pressure Power CHF3/O2 ratio Etching profile Milling damage SiO2 etch rate Byproduct RIE System Selectivity

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35 2.2.2.1 Etching rate To reduce the total etch time, an appropria te etch rate should be attained. Higher chemical etch rate helps to eliminate the ion milling of the top metal layer caused by the long time physical bombardment. The etch rate and milling effect should be balanced by adjusting the microwave power, chamber pressu re and dc bias on the sample chuck (RF power applied on the chuck). Figur e 2-5(a) shows etch rate as the function of the coupled microwave power. There is a steep section in the plot showing a critical value of the coupled microwave power (abou t 700W) for sufficient conc entration of dissociated reactive radicals. Figure 2-5. SiO2 etch rate as functions of system para meters. (a) plot of the etch rate as the function of microwave power; (b) etch rate versus system pressure. The coupled microwave power was selected as to be around 850W for an effective etch. Too high microwave power can result in the top layer metal damage. The chamber pressure dependence of the etching rate, as shown in Figure 2-11( b), reflects the ion assistance in the chemical etch. Lower pre ssure allows longer M FP thus higher kinetic 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 300 System pressure (mT) 500 550 600 650 700 750 800 850 0 50 100 150 200 250 300 Microwave power (W)SiO2 etch rate (nm/min)(a) SiO2 etch rate (nm/min) (b) SiO2 etch rate (nm/min)

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36 energy of the ions, which benefit th e etching by bombar ding the surface SiO2 atoms, providing a fresh reaction front and easing the deli very of the byproduct. 2.2.2.2 Top metal layer milling For long-time RIE of thick SiO2 layers in CMOS stacks, th e etch selectivity of SiO2 over Al is critical for the survival of the t op Al layer and vias. It is observed that aluminum etch during the SiO2 etch is actually due to the physical ion milling effect on the aluminum layer. Therefore, the most si gnificant influence on Al damage is from the chuck bias at a given chamber pressure. Figure 2-6(a) shows part of a capacitive sensing finger with milled top Al layer after 80 minutes of SiO2 etch. The microwave power used in the etch was 700W at a system pressure of 5 mT. With a dc bias of 345V resulted from a 75W RF power, the top Al layer was milled to approximately 0.3 m, which is only half of its original thickness. If sidewall capacitance is used for vertical position sensing, as in the z-axis sensing of the 3-axis accelerometer, which will be addressed in Chapter 4, the milled Al layer will greatly reduce the sensing capacitance fo rmed by Al sidewalls. In extreme case, damage to the MEMS devices will arise in th e subsequent etch pro cesses if the top Al layer, which acts as the mask for other etch steps, is completely milled away in the SiO2 etch. Under a similar etch condition, the co rner of an intercon nection via on a bonding pad of a micromirror was etched away, resu lting in an open circuit of the actuation polysilicon heater, as shown in Figure 2-6(b). A lower chamber pressure increases the MFP of the ions, allowing higher kinetic ener gy of the ions, which in turn reduces the selectivity of SiO2/Al and deteriorates the damage on the top metal. This trend is shown in Figure 2-6(c).

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37 In practice, the microwave power was in creased to 850W and the dc bias was reduced to 140~150V. This results in a proper et ch rate between 0.25 m/min and 0.33 m/min with a low aluminum milling rate. A selectivity of SiO2/Al as high as 50 has been achieved. Figure 2-6. Impact of the SiO2 etch on the top Al layer. (a) over-milling of the top Al layer on a comb finger of the fabricat ed accelerometer, (b ) open via in an electrothermal micromirror. (c) SiO2 etch rate and etch selectivity as the function of system pressure. Over-milled top Al layer Open via due to the over-milling (a)(b) 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 SiO2 etch rate (nm/min) 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 System pressure (mT)SiO2/Al selectivity(c)

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38 2.2.2.3 Sidewall profile of the SiO2 layers and CMOS stacks The main system variable which a ffects the sidewall profile of SiO2 layer is the chamber pressure. With higher chamber pressu res, the MFP of the ions and radicals reduces, resulting in more random collisions among the radicals. The deflected ions and radicals attack and react with the SiO2 on the sidewall, consequently resulting in a more isotropic profile. For CMOS stacks with multiple layers of Al, it is prone to have an undercut on the SiO2 between metal layers at a high chamber pressure. After optimization, a 10 mT system pressure was se lected for an adequate etching rate and a reasonable SiO2 profile. Figure 2-7. Profiles of the CMOS stack at different process stages. (a) after the first SiO2 etch; (b) after the second SiO2 etch. SiO2 etch was performed with a system pressure of 10 mT. Note there are two SiO2 RIE steps in the develo ped DRIE post-CMOS MEMS process. The first SiO2 etch is to open the pattern of electrical isolation structures; while the second is for other structures. Figure 27(a) and (b) show th e sidewall profiles of CMOS stacks after the first and second SiO2 etch respectively. It can be seen that a vias (a) (b)

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39 straight vertical SiO2 profile has been obtained and the vias have been nicely kept in shape after the second SiO2 etch, as shown in Figure 2-7(b). 2.2.2.4 The inhibitor polymer redeposition on the sidewall As one of the RIE mechanisms, inhibitors generated in the SiO2 etch provide a protection layer to the sidewa ll, making the etch more anisotropic. However, if the feature size of the MEMS stru cture is small, or, if the inhibitors redeposited on the sidewall are too thick, they will affect the feature size. This is due to the micromask effect of the inhibitor film in the following SiO2 RIE and Si DRIE. In addition to the etching system variables (e.g. chamber pr essure, microwave power and biasing RF power), the oxygen concen tration in the CHF3/O2 etching chemical plays an important role in the formation of the inhibitor polymers. The SEM image in Figure 2-8(a) shows th e thick inhibitor film formed on the sidewall of the SiO2. The energy dispersive spectroscopy (EDS) compositional analysis result is also shown in Figur e 2-8(b). The analysis was obt ained by using the EDS system integrated in a Joel 6400 SEM system. The presence of elements F, C and O in the film indicates the polymer nature of the inhib itor. The existence of aluminum in the redeposition layer is the evidence of the ion milling of the top Al layer. The milled Al atoms collide with the downward ions from the plasma bulk and are swept to the CMOS stack trench. They are then scattered to the sidewall by the reflected ions from the bottom of the etched trench. The contamination of th e sidewall with inhibito r film containing Al will cause some problems in the silicon etch fo r the release of the MEMS structures. This particular issue is addressed in Chapter 5.

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40 Figure 2-8. Inhibitor polymer formation in SiO2 etch. (a) Thick polymer layer on the sidewall of isolation holes. (b) EDS spectrum of the inhibitor polymer. Experimental results show that not only does oxygen concentrat ion in the etching gas affect the etch rate, but it also has impact on the formation of the inhibitor polymer film in the etching. Figures 2-9 shows the SiO2 RIE etch rate as the function of the oxygen concentration in the CHF3/O2 etching chemicals. The et ching rate peaks at the O2 concentration of about 5% 10%. It is widely accepted th at in a certain concentration range, the additive oxygen helps in dissociating more F radicals which is the main etchant (a) (b) polymer Inhibitor

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41 in the SiO2 etch [90]. When the O2 concentration is higher than 15%, Teflon-like (CF2)x inhibitor will form, and the SiO2 etching rate reduces. On the other hand, if O2 ratio is too low, it does not help the dissociation of the CHF3. The plot agrees with the reported ECR RIE of SiO2 [91]. Figure 2-10 shows the polymer formed on the sidewall of CMOS stacks after the final Si etch is performed. In Figure 2-10(a), thick polymer is present with a higher oxygen concentration of 40%. In Figur e 2-10(b), the redeposi tion of the polymer is greatly reduced by lowering the oxygen concentration to 6.7%. The clean CMOS stack sidewall is highly desired in the subsequent Si etch, especially when alternate SiO2 and Si etch are required in the micromachining processes. Figure 2-9. SiO2 etching rate as the function of oxygen concentration in the CHF3/O2 gas mix. 0 5 10 15 20 25 30 35 40 45 0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 0.32 Percentage of O2 in the gas mix (%)SiO2 etch rate (um/min)

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42 The oxygen concentration in th e gas flow also has affect s the etch se lectivity of SiO2 over Si. A lower oxygen concentration increases the SiO2/Si etching ratio by reducing the Si etching rate. In our e xperiment, the etch selectivity of SiO2/Si increases from 1.67 at a 40% oxygen concentration to 4.1 at 3.3% of oxygen concentration. The final recipe for the SiO2 etch is listed in Table 2-3. Figure 2-10. Inhibitor polymer formation as the function of oxygen concentration in the CHF3/O2 mixture. (a) Thick in hibitor polymer with O2 concentration of 40% in the SiO2 etch. (b) Inhibitor polyme r is reduced by reducing O2 concentration to 6.7 %. Table 2-3. Anisotropic SiO2 etch recipe on the Plasma Therm SLR770 ECR RIE system Parameters Settings CHF3 flow 30 sccm O2 flow 3~5 sccm RF2 power 850W RF1 power (platen) 40W~50W (140~150V bias) Chamber pressure 10 mT Thick inhibitor polymer with O2 concentration of 40% in the SiO2 etch. Inhibitor polymer is eliminated by reducing O2 concentration to 6.7 %. (a) (b)

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43 2.4 Advanced Silicon Etch by STS ICP DRIE Silicon DRIE is now a standard process for both bulk and surface micromachining in MEMS fabrication due to its capability of high-aspect-ratio etch and high selectivity over photoresist and SiO2. It is common in an advanced silicon etch (ASE) system to achieve an aspect-ratio (AR) of over 30, with selectivities over PR and SiO2 being higher than 50 and 100 respectively [92]. In the fabrication of many MEMS devices, silicon DRIE is the final dry release step. Since the normal etch tim e of a silicon DRIE step is relatively long, especially when a thick ME MS structure is fabricated, a number of geometry-related effects also play very signifi cant roles in the final structure formation. These effects should be considered at both the device design and fa brication stages as additional design rules which are of equal im portance as the basic process requirements [93, 94]. According to the fa brication level, the geometry -depended effects and other process variations can be categorized into inte r-die effects and intradie effects. The interdie effects include spatial cross-wafer etch rate variations in duced by the chamber geometry, and the macroloading effect caused by a global variation of etching species. The intra-die effects consist of aspect ratio dependent etching (ARDE) and microloading effect. There is a difference between ARDE and micr oloading effect. ARDE is an effect in which the etch rate decreases as a result of the reduced transport of reactive species in deep and narrow structures. Whereas in micr oloading effect, the et ch rate reduction is caused by a local depletion of reactive species. In the improved DRIE post-CMOS MEMS technology, which is detailed in Chapter 3, three silicon DRIE steps are used in the fabrication of the accelerometers. The first is the backside etch by which the chip or wafer is thinned to the desired thickness.

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44 The second step is the etch-through of the isol ation trenches. The thir d is the etch-through of the structures to release the device. If necessary, more DRIE can be conducted in between the above two steps to form some pa rticular structures. For example, one more silicon DRIE and isotropic silic on undercut is needed to creat e the isolation structure in the developed capaci tive accelerometer. In this section, the characterization of the DRIE etcher and some geometrydepended effects in the silicon DRIE are addr essed. The silicon DRIE in the developed post-CMOS MEMS technology was conducted using an ICP etcher from Surface Technology Systems (STS), LLC. 2.3.1 ICP Silicon DRIE System Configuration The system configuration of the STS IC P etcher is shown in Figure 2-11. As described in the previous sect ions, the key feature of the IC P system is the separation of the two RF powers in the system, i.e., the RF power for the generation of etching radicals and the other RF power for the sample bias The RF coil at the top of the ceramic chamber supplies the power to dissociate the species and generate radicals; and the RF power applied to the bottom electrode provides power for directional etch. It is this power applied on the bottom electrode that generates a dc bias for the self-bias of the carrier wafer on which the sample to be etched s its. This configuratio n allows independent power tuning for species dissociation and samp le bias. More power can be delivered to the top coil without aff ecting the self dc bias. As desc ribed in the previous section, compared to a RIE system, the ions in an IC P system are more confined in the plasma bulk due to the alternate magne tic field generated by the RF power on the coil, resulting in more collisions of ions with molecules a nd consequently higher plasma density in the system. For a processing pressure somewh ere between 1 mT and 100 mT, the plasma

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45 density is between 11011/cm2 and 11012/cm2, which is two orders of magnitude higher than in a traditional RIE system. Because of the high density of ion flux onto the sample chunk, the wafer in the process has to be cooled by helium flow running underneath the backside of the sample chunk. An effectiv e vacuum system is required to reduce the residual time of numerous etch by-products in the chamber. Figure 2-11. Configuration of the STS ICP AS E system. (Adapted from STS webside.) 2.3.2 Silicon Anisotropic Etch ASE employs Bosch process to achieve anis otropic etch [95]. The essence of the Bosch Process is the alternate etch and passiva tion steps in the whole process duration, as shown in Figure 2-12. The etching cycle utilizes SF6/O2 mix gas flow to etch exposed silicon. C4F8 flow is used for the passivation of si dewalls of the etched stru ctures. The preference of SF6 to pure F2 as the reactive gas is due to its lower toxicity. SF6 is dissociated in to the reactive F radical and unsaturated fluorosulfur (SxFy) in the plasma. The added oxygen in the

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46 reactive gas SF6 has two functions in facilitating the silicon etch. The first is to oxidize the surface of silicon, making the passivated oxide layer on Si surface easier to be removed by the impinging ions, subsequen tly allowing more fresh silicon surface exposed to reactive atomic F. The second f unction of additional oxygen is to react with the unsaturated SxFy, enabling more reactive atomic F while depleting polymer-forming species. In the etching cycle of Bosch Process, three processes the passivation of silicon surface by O2, the passivation layer removal and the etching of silicon happen simultaneously. Therefore, the silicon etch by SF6 is isotropic. In a high-aspect-ratio structural etch, a relatively high dc bias on the sample chunk is necessary to completely remove the SiOx passivation layer, especially from the bottom of the structure. Figure 2-12. Alternate etching and passivati on in Bosch process. (a) Etch step. (b) Passivation step. (c) The next etch step. (a) (b) (c) F* SF* nCxFy*

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47 In order to achieve the anisotropic silicon etch, sidewall passivation of the etched structure must be performed to protect the sidewall from being etched in the etching cycle. C4F8 is used in STS ASE process as the pa ssivating chemical. It is dissociated in the plasma and forms ions and radical sp ecies. These species undergo polymerization reactions and result in th e deposition of a polymeric layer consisting of n(-C4-F2-) molecular chains. This polymer layer is deposited uniformly on the surface of mask, sidewall of the etched struct ures and the bottom of the etch ed trenches. In the following etching cycle, aided by the ion bomba rdment, radicals dissociated from SF6 preferentially remove the surface passivation layer, leaving the polymer on the sidewall of the etched structures unetched. The anisotropic silicon can be achieved by alternately performing the SF6 etch and C4F8 passivation continuously. As a resu lt of the periodic etching and passivation, scallops on the si dewall of etched structures are observed, as shown in Figure 2-13. Figure 2-13. Scallops formed on the sidewa ll of the etched stru ctures showing the alternate etching and passivati on cycles in Bosch process.

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48 By adjusting the etching and passivation dur ation and their ratio, different scallop depth and spacing can be achieved. More dire ctional etch and smoother sidewall can be obtained at the expense of smaller etch rate and longer process time duration. 2.3.3 Silicon DRIE Characterization Due to the alternate etching and passivation cycles, more input parameters are involved in the silicon DRIE than in a traditional RIE system. While the common multiple input parameters of DRIE have the similar effects on the etching outputs as in RIE, as shown in Figure 2-4, great attenti on should be paid to some other variables specifically existing in an ASE system. For example, the time duration and the ratio of etching and passivation cycles pl ay important roles in the et ching rate tuning and profile control. In order to control the silicon anisotropic etch mo re effectively, after some optimal experiments on the input parameters, we fixed most input parameters, only leaving the etching/passivation ratio and platen dc bias tuna ble for the etch of different structures. The basic silicon ASE r ecipe is shown in Table 2-4. Table 2-4. Input parameters in th e silicon ASE on STS ICP DRIE system. Parameters Settings Coil power 600W Platen power Tunable Etching pressure 40 mT (APC position: 84%) Passivation pressure ~20~25 mT SF6 flow 130 sccm O2 flow 30 sccm C4F8 flow 85 sccm Etching time/cycle Varies Passivation time/cycle Varies In the backside etch in the develope d DRIE CMOS MEMS technology, the main concern is the surface and thic kness uniformity in the etched cavity on the backside. In an open area as large as 2 mm by 2 mm, the intradie thickness uniformity can be controlled

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49 within 2.5% and the surface roughness is less than 0.2m [92]. This satisfies the thickness uniformity requirement for the accelerometers developed in this thesis work. 2.3.3.1 Etch rate and profile tuning With other process parameters fixed, the etching rate can also be tuned by etchpassivation duration and their ratio. The duration of the et ch period determines the general etch rate, and the passi vation duration controls the late ral etch on the sidewall of the structure. Figure 2-14 shows the etching ra te as the function of the time duration of the etching cycle. Other system parameters are fixed as in Table 2-4. Figure 2-14. Etch rate per cycle using the reci pe in Table 2-4 with varying etch duration. By reducing the etch time and balanci ng the passivation duration, very small scallops can be achieved and consequently smooth sidewall can be obtained. Figure 2-15 shows a side view of a test structure. Smooth sidewall with scallops of 189nm in depth

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50 and 620nm in spacing has been achieved. These achievements are similar to the typical results reported [96]. They are achieved with a lower etching rate of 2.5 m/min. In the process, we tune the etch cycl e duration from 7.0 seconds to 13.0 seconds according to the requirement of different etching rate and sidewall profile. For microstructures in the accelerometer s, a maximum etching rate of 4.5 m/min can be used with an etch/passivation ratio of 13/7 under the other conditions lis ted in Table 2-4. The tuning of the platen dc bias also influences the etching rate by changing the momentum of the impinging ions, which is extrem ely useful in the etch of structures with high aspect ratio. For deeper trenches, in a ddition to the above met hods, the etching rate can be increased further by increa sing the gas flow rate of SF6. Figure 2-15. Smooth sidewall in Si DRIE achieved with a lower etch rate. Obviously, by changing the et ch/passivation time ratio, the sidewall profile can be tuned. Higher etch/passivation ratio turns out a more negativ e trench angle; while lower ratio produces a positive one. Fi gure 2-16 shows schematically the trends of the sidewall 0.8 m notch 0.62 m 150~189n m

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51 angle evolution; and photographs of the actual comb fingers after the release etch with different etch/passivation rati os. The tuning effect is obviou s. In the fabricated CMOSMEMS accelerometers in this thes is work, the gap between the 4.5 m-wide comb fingers is 2.1 m. The aspect ratio of the gap trench ranges from 20 to 25 with the thickness of the structure being 40 ~ 50 m. A nearly 90 profile angle can be obtained by tuning the etch/passivation ra tio between 9/5 to 10/5. Fi gure 2-17 shows the sidewall profiles of test structures a nd the finished comb fingers. The SEM pictures of the test structures were taken after 15 cycles of et ching and passivation, as show in Figure 216(a). The thickness of the etched comb fi nger in Figure 2-17(b) is approximately 45 m. The undercut on each side of the finger sidewall is less than 0.4 m. Figure 2-16. The tuning of et ch profile by changing the etch/passivation ratio. (a) Schematic tuning effect. (b) image of th e comb fingers after the release etch with 7:5 E/P ratio, (c) after the releas e etch with 8:5 E/P ratio, (d) after the release etch with 13:7 E/P ratio. E/P E/P (a) (b) (c) (d)

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52 Figure 2-17. Sidewall profiles of the comb fingers (a) test comb fingers after 15 cycles of etching, (b) the actual comb fingers after device release. (a) (b)

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53 2.3.3.2 Microloading and ARDE effect As mentioned previously, the geometry-dependent effects in the ASE mainly include macroloading effect, microloading e ffect and aspect ra tio dependent etch (ARDE). Macroloading effect is characterized by the faster etching rates on the largest open area. It is also observed that in the w hole wafer etching, the patterns on the wafer edge experience larger etching rate than th e same patterns at the center of the wafer. Apparently this macroloading effect, or calle d isotropic loading effect, is ascribed to diffusion-limited chemical reacti ons in confined spaces [97]. For a through-wafer etch of a 500m thick silicon wafer with same patterns uniformly distributed through the whole wafer, after hours of etch, the difference of the depth of the etched patterns can be as high as tens of micr ons. This implies that extra measurements should be taken to prevent the effects caused by the over-etch on the fastetched patterns. For through-wafe r etch without carrier wafer, large features on the wafer edge are etched through first, causing helium gas, which is used to maintain the substrate temperature in the plasma etch, to leak th rough these features to the chamber and cause the system to shut down. Therefore, this m acroloading effect is one of the main obstacle in achieving the wafer level fabrication a nd package for MEMS devices. In the silicon ASE in this work, chips of ME MS devices are glued on a 4 inch silicon carrier wafer. To avoid the macroloading effect, chips are distri buted symmetrically in the center area of the carrier wafer. The rest area of the car rier wafer is covered by photoresist or Kapton tape which demonstrates good thermal and chem ical stability. With very small open area of silicon on the chips, this approach can re duce the depletion of the reactive radicals in

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54 the sheath region, resulting a relatively uniform etch in the center area where device are attached. Microloading effect and ARDE are more related to both RIE and DRIE of smaller patterns. In general, they re fer to the phenomenon that the et ching rate scales not only to the absolute feature size, but also to the aspect ratio of the structure being etched. Sometimes they are used in ambiguous ways si nce in both of them the etching rate is a function of the mask geometry. Although they are based on some similar physical and chemical principles in terms of affecting the etching rate and trench profile in different geometrical structures, they diffe r from each other subtly [98]. Microloading effect is related to the lowe r etching rate that occurs on high pattern density regions, which is mainly due to the local depletion of etchant as a result of excessive load of the etching surface. It can be considered as a micro scale isotropic loading effect that applies to both anisotro pic and isotropic etches. This means that similar features close together etch slower th an a single isolated feat ure of the same size. Meanwhile, this also means that when cons idering uniformly dist ributed features, big features etch slower than small ones, due to the higher local density of the exposed surface thus less supply of etchant. Ela borately designed experiments have been conducted to detail the effect s of microloading effect on th e etching rate for different pattern shape and pattern density [99]. In practice, microloadi ng effect is often considered together with the ARDE effect in the MEMS device pattern design. The ARDE effect is the most problematic effect in the fabrication of MEMS devices with fine mechanical structures. Thus, it is one of the most important parameters in MEMS design rules. In this effect, the et ching rate is purely de pendent geometrically

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55 on the aspect ratio of the trenches or holes be ing etched. Moreover, not only does it affect silicon etching rate in DRIE, but also causes specific sidewa ll profile defects like bowing, bottling and microtrenching [98]. Figure 2-18(a) shows the SEM photography of the etched trenches on a test structure. The width of the trenches varies from 0.3m to 30m. The experiment was carried out using the sa me etching recipe as in the actual device fabrication. Top metal layer of the CMOS co mposite layers acts as the mask in silicon ASE. The plot in Figure 2-18( b) shows the silicon etching rate as the function of the trench width. The sharp slope indicates the hi gher the aspect ratio, th e lower the etch rate. If the trench is too narrow, the etch process even can not proceed. Figure 2-18. ARDE effect and its influence on the trench profile and etching rate. (a) Sidewall profile of trenches with various gaps. (b) etch rate as a function of gap width. (a) 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Width of the gap (um)Etch rate (um/min)(b)

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56 A large quantity of research works show that the ARDE effect is ascribed to a variety of mechanisms in RIE and DRIE. These mechanisms include ion shadowing, differential charging, neutral sh adowing, and Knedsen transpor t of neutrals in which the diffusion of the neutrals is limited by th e geometry [100-102]. To describe these mechanisms in a simpler way, the conductance of the trench is reduced by the high aspect ratio, impeding both the transport of the etch ing species to the bottom of the trench, and the removal of the etching by-product from th e trench. Moreover, the induced charges on the extruding mask at the trench entrance wi ll also shield the etch-aiding ions from entering and arriving the bottom of the trench. Microloading and ARDE effect play ex tremely important roles in MEMS design rules. They directly determine the maximum thickness the MEMS device can achieve once the smallest feature of the device is set. Or, in other wo rds, for a MEMS device with certain thickness, there exists the limit of the minimum feature size. In capacitive accelerometers, high sensitivity can be achieve d by either reducing the gap between the sensing comb fingers, or incr easing the structure thickness wh ich consequently increase the proof mass. These two approaches are all limited by the ARDE effect that is intrinsically determined by th e configuration of the ASE sy stem. In practice, the ARDE effect can be reduced by lowering the chamber pr essure. Lower pressure is also helpful in reducing the bowing effect and the etching notch which happe ns to the trench sidewall just underneath the mask. However, lower pressure means the longer MFP and higher kinetic energy of the ions which is the main cause of the rough surface [103]. The thermal effect caused by the bombardment of high-energy ions can result in over etch on

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57 fine structures in the lateral direction, esp ecially when the structure is suspended. This thermal effect will be discussed in Chapter 5. In the accelerometer design, the gap betw een the comb fingers should be carefully chosen based on the ARDE characteristics of the available system for silicon DRIE. According to the sidewall profile of the te st comb fingers the ICP DRIE etcher can accomplish, as shown in Figure 2-18, we c hoose the gap of the comb finger as 2.1m to avoid the apparent bowing and other ARDE caused sidewall deterioration. For comb fingers of 50m thick, the final gap of 2.1m can be achieved with 901 sidewall, as shown in Figure 2-19 where only stat or comb drives are shown. Figure 2-19. Etching profile of the sensing comb fingers. (a) Stator co mb drives after the device is released. (b) Backside cl osed-up view of the comb fingers. 2.5 Summary In this chapter, basic plasma etch te chnologies are introduced with exemplified PlasmaTherm SLR770 ECR and STS ICP ASE system. Some physical and chemical effects in the plasma etches, which are critical to the MEMS device design and fabrication, are also addresse d with experimental results. The design rules for CMOS(a) (b)

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58 MEMS accelerometers with structure thickness of 50 m are extracted, which are tabulated in Table 2-5. Table 2-5. CMOS-MEMS accelerometer design rules extracted from the experimental results Structural/process Parameters Design rules Highest aspect ratio 30 Comb finger gap 2.0 m Undercut on suspended structures 0.2~0.3 m Width of dummy pattern for ARDE reduction 3.0 m Selectivity in SiO2 etch (SiO2/Si) 3.0~4.0 Selectivity in SiO2 etch (SiO2/Al) 50.0 Selectivity in Si DRIE (Si/SiO2) 150 Selectivity in Si DRIE (Si/Al) 500~600

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59 CHAPTER 3 IMPROVED DRIE POST-CMOS MEMS TECHNOLOGY This chapter details the new DRIE post -CMOS MEMS process developed for the fabrication of CMOS-MEMS inte grated accelerometers. As a technological background, the previous plasma etch based post-CMOS MEMS approaches, including the thin-film and DRIE approaches, are introduced first. As a practice, a single-ax is accelerometer and a thermally-actuated micromirror were fabric ated using the previous DRIE post-CMOS technology. When used in the fabrication of capacitive acceleromet ers, the critical drawback of the previous DRIE CMOS-M EMS process (compared to the improved process developed in this thesis work) is th e simultaneous undercut of the whole structure when the undercut on isolation beams are perf ormed. This universal undercut enlarges the comb finger gap and thins the mechanic al springs, lowering both the electrical and mechanical performance of the accelerometers. It is concluded that although the previous DRIE process is effective in the fabricati on of thermal micromirrors where the feature sizes are as large as 10m, it is not a good choice in the micromachining of MEMS devices with much smaller features. The new DRIE post-CMOS MEMS pro cess was developed to overcome the shortcomings of the previous technology. It is specifically designed for the fabrication of capacitive inertial MEMS sensors where th e sensing and driving comb fingers are required to be electrically isolated from each other and from the substrate. Using the new process, the electrical isolat ion structures and the functi onal MEMS structures can be processed independently, allo wing separate control of th e fabrication parameters.

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60 3.1 Dry Post-CMOS MEMS: Background There are two types of dry post-CMOS MEMS technologies: thin-film surface micromachining technology and DRIE bulk mi cromachining technology. Both of them are CMOS-compatible because the CMOS circ uitry can be completely protected by the top metal layer during the post-CMOS micromach ining, which consists of dielectric and silicon plasma etches. Meanwhile, the MEMS st ructures are defined by the pattern of the top metal layer, which acts as a mask in th e dry etch steps. Therefore, both approaches are maskless, and no photolithography is needed for front side process. This greatly simplifies the micromachining and makes the prototyping development cycle much shorter. In addition to the convenience of th e fabrication, the multiple interconnect metal layers make the wiring of MEMS structures and integrated circuits very flexible. The fully-integrated metal wiring also helps in reducing the parasitics, allowing high overall device performance. 3.1.1 Thin-film Post-CMOS MEMS Technology [32] The process flow of thin-film CMOS-MEM S process with 4 metal layers is shown in Figure 3-1. The CMOS circuit region is designed to be covered by the top metal layer. MEMS structures are pre-defi ned by the top metal layer or the other interconnect metal layers. Figure 3-1(a) shows the cross-section of the original chip after CMOS foundry fabrication, with a passiva tion layer on top. Two processi ng steps are performed only on the front side of the chip. First, the predefined MEMS structure is exposed by etching the SiO2 stack between the interconnect layers, as shown in Figure 3-1(b). This is done by an anisotropic SiO2 plasma etch using an ECR RIE system with CHF3/O2 gases, as detailed in Section 2.2. Next, a silicon DR IE is performed using an ASE technology,

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61 followed by an isotropic silicon etch, wh ich releases the MEMS structures by undercutting the silicon beneath th e MEMS structures. The dept h of the anisotropic etch into silicon controls the gap between the releas ed structure and the silicon substrate. This gap should be large enough to eliminate th e parasitic capacitan ce between the MEMS structures and the silicon substrate. In practice, it is norma lly on the order of 30m [104]. A lateral accelerometer with 1 /mgHznoise floor exemplifies the types of MEMS devices fabricated usi ng this technology [34, 84, 105] This simple fabrication process yields much smaller parasitic eff ects as compared to the MUMPs polysilicon process, and it provides flexible wiring by using the multiple metal layers. However, there are some drawbacks in this technol ogy, which limit the performance of the fabricated accelerometer. First, there is large vertical curling of the suspended MEMS structure caused by the residual stress gradient exis ting in the composite SiO2/Al layers, as shown in the example device in Figure 1-1. For both in-plane and out-of-plane sens ing or actuation, this large vertical curling will result in the reduction or complete loss of the engagement between comb fingers or other capacitive MEMS stru ctures. Additionally, due to different thermal expansion coefficients (TEC) of Al and SiO2, the curled MEMS de vices exhibit a strong temperature dependence, which limits thei r utility. Although part icular compensation technology was employed to redu ce the structure mismatch by using a specially designed frame, the device fabricated using this thin film process still has a stringent size limit [106, 107].

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62 Figure 3-1. Cross-sectional vi ew of the thin-film CMOS-MEMS process. (a) Before the micromachining. CMOS region is shielded by top metal layer. (b) SiO2 anisotropic etch. (c) Anisotropic of Si (DRIE). (d) Isotropic etch of Si for structure release. Second, for inertial sensors fabricated us ing this technology, the requirement of release holes on the proof mass reduces the ma ss of the proof mass, resulting in a lower mechanical sensitivity of the sensors. To achieve a capacitance change large enough for the conditioning circuit to detect, the dimens ion of the accelerometer may need to be considerably large, which is in conflict with the dimension limit by the structure curling. Third, in-plane curling of the thin film st ructures due to fabrication variations also limits the maximum size of the device. A lthough there are some specific processes designed for low residual stress thin films [108], normally CMOS foundries have very few, if any, considerations to meet the particular requirements for MEMS devices. The curling of the MEMS structur es can only be compensated to a limited degree by proper (b) (a) (c) (d) CMOS region MEMS region SiO2 Si substrate Metal 4 Metal 3 Metal 2 Metal 1 Polysilicon Movable MEMS structures

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63 design of both the MEMS and compensating stru ctures. In addition to the collection of technological data directly from the empl oyed CMOS foundries, systematic post-CMOS process calibration must be conducted to char acterize the process va riations and their effect on the MEMS devices. Lastly, since the last release step is an isotropic etch, it undercuts the silicon close to the circuit and structure anchors. The ratio of the vertical and lateral etching rate is approximately 2:1 [109]. To protect the silic on underneath the circu it region from being etched away during the structure release, th e CMOS circuitry must be placed far away from the microstructures, especially when a large separation between the microstructures and substrate is needed. As a result, significan t chip area is wasted due to the protection margin around the MEMS structures. Sin ce the silicon underneat h the mechanical anchors of the MEMS structures is also etched away, the suspension of the mechanical structures is softened, which results in a lower mechanical performance and less robustness of the device. 3.1.2 DRIE Post-CMOS MEMS Technology [33] To overcome the drawbacks of the above thin-film post-CMOS MEMS process, DRIE post-CMOS MEMS technology was devel oped to incorporate bulk, single-crystal silicon (SCS) into the MEMS structures. By taking advantage of the ASE technology, high aspect ratio CMOS-MEMS struct ures have been demonstrated. The maximum aspect-ratio a DRIE system can achieve is an important factor in the MEMS structure design. It dete rmines the dimensional limit of the structures fabricated using that DRIE system. Once a lateral feat ure to be etched is fixed, the maximum thickness is uniquely defined. Similarly, for a structure with certain thickness, the smallest gap that can be created between ad jacent structures is al so uniquely defined.

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64 The DRIE post-CMOS MEMS technology st ems from the thin film technology described in last section. By taking advantag e of both the flexible wiring with multiple metal layers in CMOS technology and the capab ility of high aspect ratio etching, DRIE CMOS-MEMS provides an approach to implemen t thick and flat MEMS structures with better mechanical performance and device robustness. Figure 3-2 shows the process flow of the DRIE post-CMOS MEMS technology. The process starts with a back side silicon DRIE to define th e MEMS structure thickness, as shown in Figure 3-2(a). As described above, the maximum thickness of this structure is limited by the smallest etching pattern on th e front side of the MEMS structure and the maximum etch aspect-ratio. Next, as in th e thin film process, an anisotropic SiO2 etch is performed on the front side of the wafer (chi p) to define the MEMS structures (Figure 32(b)). The following step differs from the thin film process in that an anisotropic DRIE, instead of isotropic Si etch, finalize the stru cture release by etching through the remaining SCS diaphragm, as shown in Figure 3-2(c). With SCS in corporated underneath the CMOS interconnect layers, large and flat ME MS structures can be obtained because the residual stresses in the SiO2/Al thin-films are mitigated by the thick SCS, leading to very little out-of-plane curling. If necessary, an optional time-controlled isotropic silicon etch can be added to create compliant mechanical structures which only consist of CMOS thin films (Figure 3-2(d)). In th e accelerometers developed in this thesis work, the fullyundercut CMOS thin-film layers are employed as the electrical is olation between the sensing fingers and si licon substrate.

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65 Figure 3-2. Cross-sectional view of the process flow of DRIE post-CMOS MEMS technology. (a) Backside silic on DRIE. (b) Anisotropic SiO2 etch. (c) Silicon DRIE for structure release. (d) Optional silicon isotropic etch to create thin film structures. (a) (b) (c) (d) SCS membrane CMOS region MEMS region SiO2 surface passivation metal 4 metal 3 metal 2 metal 1 CMOS layer SCS CMOS thin-film stack without SCS underneath

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66 It should be pointed out that in the backside DRIE step to define the thickness of the MEMS structures, double side alignment is required. However, since normally the remaining silicon for bulk MEMS structures is on the order of tens of microns, there is no apparent circuit performance degradation ca used by the substrate thinning. Therefore, there is no strict requirement for alignment in the backside etch. With the flat MEMS microstructure s enabled by the DRIE CMOS MEMS technology introduced above, reli able sensing and actuation ca n be achieved. A lateralaxis angular rate gyroscope with a noise floor of 0.02 // sHz has been fabricated using this technology [70]. In particul ar, this technology is very su itable for the fabrication of thermally actuated micromirrors where bimor phs are used to elevate the mirror plate. Several electrothermal micromirrors have b een demonstrated usi ng this technology [37, 110, 111]. 3.1.2.1 Example device I: electrothermal micromirror As a process practice and comparison, tw o MEMS devices were fabricated using the above mentioned DRIE post-MEMS tec hnology: a micromirror and a lateral-axis accelerometer. In the first device, the fabricat ed electrothermal micromirror can provide large vertical displacement (LVD) by empl oying a tilting-angle compensation between the mirror plate and the actuating frame where the mirror plate is attached. Figure 3-3 shows a fabricated electrothermal micromi rror with LVD actuation in which the flat mirror with a large area allows high resolution, easy alignment and reliable scanning in an optical system [111]. In fabrication, when isotropic silicon etching is performed to remove the SCS underneath th e bimorphs, the same amount of lateral

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67 undercut simultaneously applies to both the mi rror frame and mirror plate, as shown in the process flow of Figure 3-2(d). The undercut is shown in the in set of Figure 3-3. For large structures such as the mirror pl ate with a dimension of 1mm by 1mm, the undercut is on the order of seve ral microns, which has negligib le effect on the structure integrity. However, for fine microstructures, this undercut could be disastrous! Thus, because of this simultaneous undercut, ther e will be a minimum structure size limit in MEMS device design if this DRIE postCMOS MEMS technology is employed. Figure 3-3. LVD electrothermal micromirror fabricated using DRIE post-CMOS MEMS technology. The inset shows the underc ut on the mirror pl ate and actuation frame, which is caused by the undercut of bimorphs. Bimorph Undercut on the mirror plate and frame

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68 3.1.2.2 Example device II: single axis accelerometer The second device fabricated using th e previous DRIE CMOS-MEMS technology is a single-axis accelerometer Without densely distributed release holes, large proof masses have been realized for better overall pe rformance. The drawback of this process is revealed by the accelerometer fabrication, in which severe problems caused by the simultaneous undercut have been observed. Figure 3-4(a) shows the lateral acceleromet er fabricated using the previous DRIE post-CMOS MEMS technology. The CM OS technology used was the AMI Semiconductor (AMIS) 0.5m process. The electrical isolation between the silicon underneath the sensing fingers and the bulk silicon substrate was realized by a CMOS interconnect stack of 2.4m width, as shown in Figure 3-4(b). The designed critical dimensions of the fabricated acceler ometer are tabulated in Table 3-1. Table 3-1. Dimensions of the microstructures in the test accelerometer Structures Dimension (m) Overlapped sensing finger length (L) 100.0 Sensing finger width (w) 4.0 Gap between sensing fingers (g) 2.4 Width of the isolation beam (wi) 2.4 Length of the isolation beam (Li) 4.0 Width of the spring (ws) 3.2 Length of the spring (single fold) 240.0 Thickness of the structure (t) 50.0 When the isotropic etch was performe d to undercut the SCS underneath the isolation beam, at least 1.2 m on each side should be etched to completely remove the SCS. This amount of underc ut took place on the sensing fi ngers and the mechanical springs at the same time, resulting in an enlarged gap between the comb drives. As a result, compared with the actual dimensi ons in Table 3-1, the capacitance formed

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69 between a rotor finger and stator finger is reduced by half according to the following equation, 0Lh C g (3.1) where 0 is the dielectric constant of the air and other parameters are defined in Table 3-1. This reduction of the sensing capacitance caused a lower sensitivity of the accelerometer. The impendence at the input node of the circuit will increase. Figure 3-4. Fabricated latera l accelerometer using previous DRIE CMOS MEMS process. (a) Topology of the device. (b) Top view of the enla rged sensing fingers and the illustrated cross-secti onal view of the sensing finger seen from A-A’. A Mechanical spring Shuttle connecting rotors frame of stators (a) A' (b) bulk silicon SCS on sensing finger metal 1 metal 2 SiO2 vias and contacts electrical isolation L h

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70 Additionally, the mechanical performan ce of the accelerometer will also be affected dramatically by the silicon underc ut on the mechanical springs. The spring constant of one turn clamped spring in th e response direction is given by [112] 3()s y sw kEh L (3.2) where E is the Young’s modulus of SCS. By undercutting 1.2 m on each side of SCS spring, the actual spring width will reduce to 0.8 m, which is only 1/3 of its original design value. According to Equation 3-2, the spring of the accelerometer will be softened to only 3.7% of the designed value. 3.2 Improved DRIE post-CMOS MEMS Technology As can be seen from last section, the anis otropic etch of the last step in Figure 3-3 has a significant impact on both electrical a nd mechanical performance of MEMS device. For the fabrication of MEMS devices in which capacitive sensing and actuation is employed, the isotropic undercut for electri cal isolation increases the minimum gap of comb fingers. It can even completely damage the mechanical structures if the etching time is not well controlled. The main task of this thesis work is to develop a microfabrication process to overcome the drawbacks caused by the last isot ropic etch in the previous DRIE CMOS MEMS process. To avoid the unwanted undercut on other MEMS structures, the electrical isolation etch s hould be performed independently to the structure release process. To realize this idea, we perform the isolation structure etch prior to the device release step. Another metal layer is used as the mask for the isolation structure etch. The process flow of the new DRIE po st-CMOS MEMS technology developed in this thesis work is shown in Figure 3-5. A CMOS-MEMS accelerometer is exemplified in

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71 the fabrication. TSMC 0.35m technology with 4 metal layers was used for CMOS foundry fabrication. The process starts with th e backside etching to define the structure thickness (Figure 3-5(a)), which is same as the previous DRIE CMOS MEMS technology. Then, anisotropic SiO2 etching is performed to expose the regions for electrical isolation of silicon only (Figure 3-5(b)). Note here top metal layer M4 covers all other regions on the device except for the is olation structure. An aluminum etch is then performed to remove the top metal layer M4 (Figure 3-5(c)). Next, a deep anisotropic silicon etch, follo wed by an isotropic silicon et ch, is performed to undercut the silicon beneath the isolation beams (Figur e 3-5(d)). These beams isolate the sensing fingers from the silicon substrate. Next, the second anisotropic SiO2 etch is performed to open the patterns of comb fingers, mechanic al springs and other structures (Figure 35(e)). In this step, M3 is used to protect circuit region. Finally, a deep silicon etch is performed again to etch through and releas e the accelerometer (Figure 3-5(f)). For accelerometer fabrication, compared to the previous DRIE CMOS MEMS process shown in Figure 3-2, in which isol ation beams and comb fingers were undercut by the isotropic silicon etch at the same time, the new process performs the etch steps for isolation and other structures separately. Th erefore minimal undercut of comb fingers can be achieved, which will greatly increase the sense capacitance and device sensitivity. This is realized by simply sacrificing the top metal layer M4. It shoul d be pointed out that this process can be further adapted for th e fabrication of MEMS devices in which independent processes should be pe rformed for different structures. In this thesis work, two accelerometers have been designed and fabricated using the above improved DRIE CMOS MEMS technolog y. The device designs are detailed in

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72 Chapter 4. In the 3-axis accelerometer, with a z-axis accelerometer embedded in the proof mass of a dual axis lateral accelerom eter, small size and robust structures are achieved. Figure 3-5. The improved process flow of new DRIE post CMOS MEMS technology. (a) Backside etch. (b) Anisotropic SiO2 etch and deep Si etch followed by Si undercut. (c) Top Al etch. (d) Anisotropic SiO2 etch followed by deep Si etch and Si undercut. (e) SiO2 etch to open microstruc ture region. (f) DRIE to release the device. (a) (b) (c) (d) (f) (e) CMOS region MEMS region Metal 4 (M4) Thin-film for electrical isolation SiO2

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73 3.3 Summary In this chapter, thin-film and the previous DRIE post-CMOS MEMS technologies are introduced followed by two example ME MS devices showing the drawbacks and limitations of these two processes. A new DR IE CMOS-MEMS process is developed. It features the independent cont rol of the etch steps for isolation thin films and other mechanical structures. It is particularly suit able for the fabrication of capacitive inertial sensors in which sensing and driving comb fi ngers are isolated from each other and from the silicon substrate. In genera l, the new process is appli cable to other MEMS devices where independent processes are required for different functional structures.

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74 CHAPTER 4 DESIGN OF THE INTEGRATED ACCELEROMETERS Two CMOS MEMS devices have been de veloped to demonstrate the improved post-CMOS MEMS technology described in Chap ter 3. These devices are a 3-axis and a single-axis CMOS MEMS accelerometer. For these capacitive inertial sensors, the improvements of the new DRIE post-CMOS ME MS technology allows comb drives with larger engaged area and smaller ga p, enabling high sensitivities. In this chapter, the performance goals fo r the devices are outlined first. Then, the mechanical and electrical designs of th ese devices are addressed in detail. The dimensions of the mechanical structures are determined according to the device performances, which are predicted based on simulation results. The CMOS technology used in this work is the Taiwan Se miconductor Manufacturi ng Company (TSMC) 0.35 m 4-metal, 2-poly CMOS technology. Low-power, low-noise, open-loop, capacitive amplifiers are used as interf ace circuits for the lateral and 3-axis accelerometers. The interface circ uit design is a separate work and can be found in [113]. 4.1 Applications of the Designed Devices The features of the designed accelerometers are their small size and monolithic integration enabled by CMOS-MEMS technology. What is more important, the improved DRIE post-CMOS MEMS technology developed in this work allows thick and robust sensor structures by incorporating SCS in th e mechanical structures. These are essential for the fabrication of high pe rformance capacitive sensors.

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75 Monolithic accelerometers with small si ze and 3-axis sensing capability are focused on human body motion sensing for app lications in human activity/physiological monitoring, athletic/sports monitoring, and the motion-triggered functions in portable electronics. In these applicati ons, the typical acceler ation human can generate is less than 1.5 g [114, 115]. In sports, the highest accelerati on an athlete can generate is less than 5g, and the muscle frequency is less than 200 Hz [116]. The minimum acceleration the human body generates in normal activities is on the order of tens of milli-g. If an accelerometer with a 3 g full sensing range and 200 Hz bandwidth is used to sense a 30 mg motion, from the following relation, 2 min naaBW (4.1) where amin is the resolution of the detection, an is the noise floor of the accelerometer and BW is the bandwidth, the noise floor required from the accelerometer is 2.12 /mgHz. This is a noise floor that even the sec ond generation of commercial MEMS accelerometer can achieve. Therefore, the human physiol ogical and physical activity monitoring only requires very low end of MEMS accelerometers. Much higher performance can be achieved using the improved DRIE CMOS MEMS technology due to its capability of producing a sensing stru cture with a large proof mass. We are pushing the developed in tegrated CMOS MEMS accelerometers into higher end applications by targe ting a noise floor of tens of /gHz with a bandwidth of a few hundred Hertz. With this improved performance, as tabulated in Table 4.1, the applications of the designed CMOS-MEM S accelerometers can be expanded to engineering monitoring, seismic monitoring, instrumentation and robotics. By optimizing the structural design, iner tial navigation grade performance could be achievable.

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76 Table 4.1. The major specifications of the designed single and 3-axis accelerometers Parameters (unit) Notation Value Power supply (V) Vdd 3.3 Modulation signal (V) Vm 1.5 Power consumption per axis (W) P 110-3 Full scale of acceleration sensing (g) 2 Bandwidth of the accelerometer (Hz) BW 500 Overall sensitivity (mV/g) S 200 Noise floor for z-axis ( /gHz) Nz 200 Noise floor for lateral axes ( /gHz) Nl 50 Dynamic range of z-axis (dB) 60 Dynamic range of lateral axes (dB) 70 4.2 Single-axis Lateral Accelerometer In the single-axis accelerometer, the extern al acceleration is sensed by the vertically parallel electrodes attached to the proof mass, which is anchored to the silicon substrate through SCS springs. The springs suspending th e proof mass are designed in such a way that they are primarily compliant in one in-plane direction. Compared to the accelerometer fabricated with the thin film CMOS-MEMS technology [57], the performance and the robustness of the propos ed accelerometer are greatly improved by the virtue of the SCS incorporated on the proof mass and the sensing fingers and mechanical springs. 4.1.1 Device Design The single-axis accelerometer can be simplified as the lumped model shown in Figure 4-1[112]. The governing eq uation of the system is [117] 2 2extdxdx mbkxma dtdt (4.2) which results in the transfer function of

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77 222()11 () ()Xs Hs bk As ssss mmQ (4.3) where b is the damping coefficient of the proof mass, is the resonant frequency and Q is the quality factor defined by m Q b For accelerometers working at a frequency lower than the system resonant frequency, the mechanical sensitivity can be expressed by dropping the first two terms in the denomi nator in Equation (4.3), which gives 21inxm ak (4.4) This is the mechanical sensitivity of the accelerometer. It is inte resting to note that the mechanical sensitivity is inversely pr oportional to the square of the resonant frequency. Figure 4-1. Lumped model and eq uivalent electrical circuit of the single axis capacitive accelerometer. (a) schematic model, (b) lumped circuit model. (a) (b) k b Proof mass F C 1/k R b L mC

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78 A fully differential configuration of the cap acitive sensing is employed to reject the common mode noise. The sensing bridge is formed by wiring the comb fingers in a common-centroid way, as shown in Figure 4-2. The sensitivity in electrical domain can be derived as 2 04 1 2ssm inspVCV aCCx (4.5) where s outoutVVVis the differential output of the capacitive sensing bridge, x0 is the original gap between the sensing comb fingers. Cs and Cp are the sensing capacitance and parasitic capacitance in the system respectively. In Figure 4-2, Cs=C1=C2=C3=C4, and Cp is the parasitic capacitance from the sensing node to the ground. Figure 4-2. Fully differential configur ation of the lateral accelerometer. Vout+ VoutC1a C2a C4a C3a C4b C3b C1b C2b C1a C3b C1b C3a C2a C2b C4a C4b C1 C3 C2 C4 Cp Cp Vout+ VoutVm+ VmVmVm+ Vm+ Vm-

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79 Figure 4-3 shows the schematic 3-D mode l of the single-axis accelerometer. The configurations of mechanical spring and the sensing comb fing ers are also given. The 3-D model was created using CoventorWare [ 118], a commercial FEM simulator. The dimensions of the structures are tabulated in Table 4-2. Figure 4-3. Schematic 3D model and mechanic al spring configurati on of the single-axis accelerometer. (a) 3D model of the device, (b) spring configuration. Due to the large ratio of La/Wa in the configuration, the spring constant of half of the serpentine mechanical springs, as seen fr om AA’ in Figure 4-3(b), can be simplified as [119]: springs driving fingers sensing fingers (a) ( b ) A A’ Wb Lb Lf Wa La Leff Wf X0

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80 3 31 () (1)2b quat bW kEt nL (4.6) where n is the number of turns of the mechanical springs, E is the Young’s Modulus of silicon, t is the thickness of the springs. Since there are two sets of the springs on each end of the proof mass, th e overall spring constant k should be the double of what is in Equation 4.6. The mechanical resonant frequency of the sensor is then 1 2 k f m (4.7) where m is the mass of the proof mass. Table 4-2 Dimensions of the lateral accelerometer Parts (unit) Notation Dimensions Proof mass area (m2) A 300*600 Length of single turn spring (m) Lb 200 Width of single turn spring (m) Wb 4 Length of meander (m) La 13 Width of meander (m) Wa 10 Length of comb finger (m) Lf 85 Length of effective comb finger (m) Leff 80 Width of comb fingers (m) Wf 4.8 Gap of the fingers (m) x0 2.1 Thickness of all the structure (m) t 50 Number of sensing comb finger pairs N 56 4.1.2 Device Simulation Using Finite Elements Method (FEM) The mechanical performance of the accelerometer was simulated with CoventorWare. Folded mechanical springs ar e employed to reduce the device size. They suspend the proof mass symmetrically. The simulated resonant frequency of the la teral accelerometer is 6.05 kHz, which is within 10% of the value calcu lated using Equations 4.6 and 4.7. The calculated parasitic

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81 wiring capacitance is less than 60 fF, accord ing to the technical data of TSMC 0.35m process provided by TSMC and the actual layou t. While the mechanical thermal-elastic damping effects are neglected in this system squeeze-film damping must be considered for the designed structure with large number of lateral sensing comb fingers. The squeeze-film damping coefficient of a single pa ir of the comb fingers is given by [120] 3 07.2()effl bNt x (4.8) where N is the number of comb fingers; =1.5410-6 kg/m/s is the viscosity of the air under atmospheric pressure at 20C [112]. leff is the engaged length of the comb fingers. In the designed lateral-axis acceleromet er, 4 groups of comb finger arrays, each consisting of 14 pairs of fingers are used to achieve large sensing capacitance. There are also 4 groups of driving comb fingers, each cons isting of 2 pairs of fingers with the same dimension as the sensing comb fingers. Therefore, in Equation 4.8, N=(14+2)4=64.. The dimensions of the structures in the designe d accelerometer are listed in Table 3-1. The equivalent Brownian noise am can then be expressed as [121] 4 (/) 9.8B mkTb agHz m (4.9) where kB is the Boltzman’s constant (1.3810-23 J/K), T is the absolute temperature of the working ambiance and m=12.6 g, is the proof mass of the accelerometer. The snap-in voltage can be calculated ba sed on the electrosta tic spring softening effect by balancing the electrostatic spring c onstant and the mechan ical spring constant [117], this yields 2 0 08 27m snapkx V C (4.10)

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82 where the mechanical spring constant km is approximately 30Nm The designed accelerometer has 134 pairs of sensing fingers, wired in a commoncentroid configuration as in Figure 4-2. The modulating voltage is designed as 1.5 V. The proof mass is assumed as approximately 23 g, attributed to the incorporated SCS. The performance of the designed acceleromete r can be predicted based on the above equations, as tabulated in Table 4-3. Table 4-3. Predicted performance of the designed single axis accelerometer Parameters Units Calculated value Total sensing capacitance fF 440 Device sensitivity (without amplification) mV/g 2.3 Brownian noise of the sensor /gHz 38.9 Resonant frequency kHz 6.05 Snap-in voltage of the sensing comb drive Vsi 15.5 Quality factor 1.1 With a designed 40 dB on-chip amplificati on, the output sensit ivity of the device can be expected as high as 0.23/ Vg. The noise floor of the interface circuit is about 10 / nVHz [113]. This single-axis acceleromete r is integrated with the 3-axis accelerometer. Their layout will be shown in later section. 4.3 Tri-axial Accelerometer A unique 3-axis accelerometer is the primary device de veloped using the proposed post-CMOS MEMS technology [86]. The independe nt silicon DRIE steps for electrical isolation structure formation and device releas e allow a precise control of the structure dimensions and critical profile s. By incorporating SCS in th e mechanical spring, robust devices are accomplished. As introduced in Chapter 1, there are nor mally two topologies for dual or 3-axis accelerometers. The hybrid topology has the ad vantage of better mech anical performance

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83 due to the optimized mechanical structure. The monolithic integrated approach has much lower parasitics. In this thesis work, the m onolithic integration approach is used for the design of a 3-axis accelerometer. Moreover, in order to further reduce the device size and parasitic effects caused by the long wiring pa th, the z-axis sensing element is embedded in the proof mass of the lateral accelerometer as schematically shown in Figure 4-4(a). As a first-order approximation, the dual-axis lateral accelerometer can be considered as a regular lateral accelerometer with a solid proof mass. In each sensing di rection, i.e. x-axis and y-axis, it consists of four groups of symmetric sensing and actuation comb fingers along the two opposite sides of the proof mass. The sensing comb fingers are wired the same way as in the single-axis acceleromete r described in the last section for common mode rejection. The proof mass is anchored to the silicon subs trate through four symmetric crab-leg SCS springs. The crab-leg springs permit displacement in both lateral directions, enabling the lateral sensing by the comb fingers on the proof mass. This compact configuration can improve the circuit performance by reducing the parasitics at a slight cost of possible cr oss-axis mechanical coupling. The simulated results, as presented in the following secti on, show that the mechanical coupling is acceptable for this kind of small-sized device designed for portable electronics and engineering monitoring. Figur e 4-4(b) shows the layout of the single and 3-axis accelerometer, along with other te st structures. The dimensi ons of the designed 3-axis accelerometer are tabulated in Table 4-4.

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84 Figure 4-4. Schematic 3D model of the 3axis accelerometer and layout of devices designed. (a) Schematic 3D model show ing the configuration of the sensing elements. (b) Layout of the integrated single and 3-axis accelerometer chip with circuit blocks. z proof mass lateral proof mass Si substrate backside cavity x, y springs z sensing fingers (a) x, y sensing fingers z y x z torsional spring (b) Single axis accelerometer 3-axis

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85 Table 4-4. Structural dimensions of the designed 3-axis accelerometer. Structures Dimension Lateral proof mass (mm) 10001000 Torsional plate (mm) 700300 Structure Thickness (m) 50 Lateral sensing finger length (m) 90 (80 engaged) Z sensing fingers length (m) 80 All finger gaps (m) 2.1 Lateral springs ( lw ) (m m) 3205 Z torsional springs ( lw ) (mm) 4005 Number of lateral sensing fingers 184 Number of z-sensing comb fingers 254 4.2.1 Z-axis Sensing One of the main challenges for achieving monolithic 3-axis capacitive accelerometers is how to realize z-axis sensing. The difficulty of z-axis sensing lies in the fabrication of horizontal elec trodes to sense out-of-plane di splacement in the presence of large parasitic capacitance to the substrate, es pecially when differential sensing is needed. Z-axis capacitive sensing with an imbalanced proof mass and torsional springs have been demonstrated [83, 122], but they suffer from either non-differential sensing or complicated fabrication processes. In the to rsional structure described in [122], glasssilicon bonding, wet etching and chemical mechanical polishing (CMP) were required, which complicates the fabrication process. R ecently, a bulk-silicon, integrated, 3-axis CMOS-MEMS accelerometer was demonstrated [123]. However, it has two drawbacks. First, although most of the sens ing structure is made of singl e-crystal silicon (SCS), the zaxis sensing employs Al/SiO2 thin-film spring beams, which have large out-of-plane curling and poor temperature performance. Second, the silicon undercut for electrical isolation of substrate silicon also undercuts the silicon underneath comb fingers, which increases the comb-finger gap and in turn reduces the sensitivity.

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86 As described in Chapter 1, the purpose of the improved DRIE post-CMOS MEMS technology developed in this thesis work is to solve the problem of the simultaneous undercut on the isolation struct ure, comb fingers and mechan ical springs, thus overcome the drawback of the device in [123]. Torsiona l sensing is one method to achieve out-ofplane sensing in the z-axis wit hout sacrificing the r obustness of the device. In this 3-axis accelerometer design, a torsional z-axis se nsing element is employed that uses the sidewall capacitance of the embedded metal laye rs for differential capacitive sensing. The z-axis accelerometer is embedded in the dua l-axes sensing proof mass by suspending the imbalanced z-axis proof mass to the lateral sensing proof mass with a pair of SCS incorporated torsional springs as shown in Figure 4-4(a). The concept of the z-axis sensing is illu strated in Figure 4-5. The z-axis sensing element consists of an imbalanced proof ma ss, a torsional spring beam and comb fingers on both ends of the proof mass. If there exists an external acceleration in z-axis, a net torque is generated about the torsional spri ng due to the mass difference on two sides of the imbalanced proof mass. Thus, one end of the proof mass moves down and the other end moves up with the same displacement. Th is symmetry is due to the same distance ( L ) from the both ends of the imbalanced proof mass to the torsional spring, as shown in Figure 4-5(a). The out-of-plane displacement is capacitively sensed by the capacitors formed among the metal layers in the CMOS thin-film stacks. Note that the SCS underneath the metal/SiO2 multilayer stacks is not shown in Figure 4-5(b). SCS in the z-ax is sensing comb fingers is used only as a mechanical support to maintain the flatness of the comb fingers. It is grounded to the substrate

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87 through the SCS on the torsiona l springs in z-element and crab-leg springs on lateral proof mass. The wiring configuration is s hown in Figure 4-5(b), where all three metal layers in the stators are electrically connected, while the rotors have only two metal layers which are electrically isolated. Theref ore, four sidewall capacitors, C1a, C1b, C2a and C2b, are formed. The pair C1a/ C1b changes values oppositely when there is a z-axis acceleration induced rotation; so does the other pair C2a/ C2b. Note that Cia and Cib (i=1, 2) are not equal even at the rest position. This is due to two factors. First, the top metal layer M3 will be slightly thinner than the bottom metal layer M1 because of the ion-milling effect during the etching of SiO2 during the post-CMOS fabricati on. Second, there is a SiO2 layer and supporting SCS structure underneath M1 but nothing on top of M3. This results in an asymmetric electric field along the z axis. Therefore, there will be a large d.c. offset if a capacitive half bridge is formed by only one pair of Cia / Cib. However, note that C1a changes value the same way as C2b which is on the other side of proof mass; so does C1b with C2a. With this observation, the large d.c. offset can be compen sated by constructing a half capacitive bridge with the wiring as illustrated in Fi gure 4-5(b). This connection forms a differential capacitive bridge with two pairs of capacitors, i.e., C1a+C2b (=C2) and C2a+C1b (=C1). The equivalent circuit is shown in Figure 4-5(c). In this configuration, C1 = C2 at the rest position.

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88 Figure 4-5. Differential connecti on of the sidewall capacitors in z-axis sensing element. (a). Torsional block motion in z direc tion and the capacitor arrangement. (b). Common-centroid configuration of the capac itance. (c). Formation of the half sensing bridge. za (a) C1a, C1b C2a, C2b Torsional beams and anchors Stators C4a, C4b C3a, C3b L1 L L (c) (b) Z Rotor up Rotor downZ Rotor C1a C2a C2b C1b Stator Rotor Stator Stator Stator M3 M2 M1 A l Via SiO2 Vm+ VmC1a C2b C2a C1b Vm+ VmC1 C2 Vm+ VmVout

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89 For the half capacitive bridge in Figure 4-5(c), at the presence of a z-axis acceleration az, the output voltage Vout is given by [84] 121 12()() ()()zz outm tCzCzma d VV dzCzCzkLL (4.11) where mz is the net mass of the Z sensing block, L1 is the distance from the mass center of the z-axis proof mass to the torsional beam, L is the distance from the torsional beam to the end of the proof mass and Vm is the modulation voltage. A small-angle approximation is used for deriving the above equation and th e mass of the sensing fingers is neglected. kt is the torsional stiffn ess of the torsional beam, which is given by [124]: 32 3b t bGwt k l (4.12) where lb is the length of the torsional spring beams, t is the thickness of the beam, wb is the width of the torsional beam and G is the shear modulus of the beam (silicon). Then, the resonant frequency of the torsional z sensing element is then, 1 2t zk f I (4.13) where I is the overall moment of in ertia of the z proof mass a bout the torsional spring and is given by: 2 11 3nz n I ImL (4.14) where n stands for the different rectangular plate on the z-axis proof mass, and L1 is the distance from the mass center to the torsional springs. Due to the complexity of the fringe capacitance formation, only FEM simulation was performed to predict the capacitance ch ange versus the external acceleration.

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90 Figure 4-6 shows the CoventorWare simulation results of the capacitance change as a function of z acceleration ranging from -50g to +50g. Two stators and two rotors on each end of the sensing block are used in the simulation for simplicity. This simulation is based on the actual dimension of the designed de vice listed in Table 4-4. Due to the large difference in dielectric constant of the SiO2 thin film and the air, it is apparent that C1a differs from C1b in value at the rest position. In value, C1b is almost the double of C1a. However, after swapping the counterpart cap acitors in the opposite side of the proof mass, C1 and C2 are equal when the z sensing block is flat and they change their value oppositely under the external acceleration. Figure 4-6. Capacitance cha nge in the range of -50 g to +50 g in z direction shows a good linearity. -50 0 50 -1 0 1 2 3 4 5 6 7 8 9 Acceleration in z direction (g)Capacitance (fF) y = 0.0024*x 2.1e-018 C1b C1a C1 C2 12 12CC CC

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91 Due to both the small displacement in the z-axis and the rotational angle about the torsional spring, a good linear sensing output can be achieved because of the linearity of the term 12 12CC CC The fitted curve of this term is shown in the figure as well. A fully differential capacitive bridge can be formed when the other two groups, C3 and C4, are connected in the same configuration. With this fully differential topology, the sensor offset caused by the fabrication vari ations and the cross-axis coupling can be greatly reduced. In addition, bidirecti onal sensing in z axis is achieved. Based on the calculation above, the sensitivit y of the lateral and z elements can be expected as 4.5 mV/g and 2.4 mV/g with approximately a total capacitance of 600 fF and 86 fF, respectively. The noise floor of the lateral sensing element is 0.35 / VHz. Since the z sensing element has a Couette dampi ng instead of squeeze-film damping between comb fingers, which has a much lower dampi ng coefficient, as shown in Equation 4.15. z zzz zt bNl g (4.15) where Nz is the number of the z-axis sensing fingers, lz, tz, are the length, thickness of the z-axis sensing comb fingers and gz is the gap between z comb fingers. Compared to lateral axes, the damping co efficient in z-axis is much smaller according to Equation 4.15. However, due to the smaller z-axis proof mass, the noise floor of the z sensing element calculated usi ng Equation 4.9 is consid erably large. The z quality factor is larger than those in latera l axes due also to the smaller proof mass. The predicted performance of th e 3-axis accelerometer is summarized in Table 4-5.

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92 Table 4-5. Predicted performance of the designed 3-axis accelerometer Parameters Unit Value Total lateral sensing capacitance fF 400 Total z-axis sensing capacitance fF 86 Sensitivity in lateral axes mV/g 4.5 Sensitivity in z-axis mV/g 2.4 Quality factor in lateral axes 1.1 Quality factor in z-axis 3.6 Brownian noise of the lateral axes / gHz 5.5 Brownian noise of the z-axis / gHz 27.0 4.2.2 Analysis of the Cross-axis Coupling The simulated resonant frequencies of the first three modes of the 3-axis accelerometer are respectively 1.70 kHz 3.23 kHz and 3.51 kHz corresponding to the rotation about the torsional spring of the z sensing element, the in-plane transversal motion of the whole structur e along x direction and the in -plane longitudinal motion along y direction, respectively. The accelerometer is designed to work in a bandwidth of 0 ~ 500 Hz in frequency, as shown in Table 4-1. Therefore other modes at higher frequencies can be neglected. One of the most significant features of the designed 3-axis accelerometer is the fully differential configur ation in all the three sensing elements by a common-centroid wiring. It is capable of can celing most cross-talk caused by orthogonal mechanical coupling. Simulation results conclude that the cross-talk between x and y axis is negligible by the virtue of the symmet ric mechanical geometry and common-centroid electrical wiring in both dire ctions. Moreover, since the late ral crab-leg springs are rigid in z direction, the influence of the motion of embedded z proof mass on lateral structure can be neglected.

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93 In this analysis, only the coupling of z se nsing element from lateral motion will be addressed. By analyzing the force applie d on the torsional beam, starting from the equation lTGI (4.16) where T is the torque generated by the imbalanced proof mass. I is the moment of inertia, and l is the rotational angle pe r length along the torsional be am. The rotational angle on the proof mass can then be calculated as [124], 1 32b z bmll a Gtw (4.17) where is an adjusting constant defined by the ratio of bt w, l1 is the distance from the center of the z proof mass to the torsional beam, as the L1 in Equation 4.11. For our structure, the in (1.5) is 0.32~0. 33 for the ratio of 50 3bt w [124]. Even though an analytical model can be created to reveal the motion of the z element in the mechanical domain, it is comp lex to predict the fringe capacitance change in the presence of the external vertical accele ration, especially when a torsional structure is involved. Therefore, only FEM analysis is carried out using the CoSolver tool in CoventorWare by including iterations in the mechanical and electrical domains simultaneously. For the coupling evaluation, the z capacitance ch ange responding to z acceleration was swept in the presence of e ither x or y acceleration. The z acceleration was swept from negative 10 g (pointing down) to positive 10 g (pointing up), with a lateral acceleration of 1 g or 3 g applied to the device at same time. These values were then compared with the capaci tance values under pure z accel eration without any lateral coupling.

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94 Figure 4-7 shows both the capacitance cha nge in z acceleration with and without the coupled acceleration from la teral axes. Figure 4-7(a) is the capacitance response to zaxis acceleration with and without 1g coupled from lateral axes. The right figure, 4-7(b) shows the zoomed portion where the cross of C1 and C2 happens. Figure 4-7(c) is the same as Figure 4-7(a) except that the coupled lateral accelerations ar e changed to 3g both in x and y axis. Figure 4-7(d) is the zoomed portion of 4-7(c). It is observed that the larger coupling effect to z-axis comes from in y direction, as shown in Figure 4-7(a) and (c). However, th is kind of coupling is very small. From calculation based on the data in the both pl ots, the maximum capacitance change caused by y direction coupling is on the order of 10-4 of the original value without coupling. Therefore, the coupling effects from both latera l axes to z sensing element are negligible. It should be pointed out that the simulation conducted a bove is reliable. Under two randomly selected conditions, i.e., -5 g and -10 g acceleration in z axis, the simulation result as a function of the number of meshi ng elements is plotted as Figure 4-8. The number of elements in the mesh ranges from 1820 to 20312. After the number reaches 5600, the simulation results vary within 5.5%, which means a confidence of 89%. To simulate effectively for the z acceleration sweep, the z sensing element was meshed with 5600 volume elements.

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95 Figure 4-7. Z capacitance coupling from the late ral motion. (a) Z capac itance change with and without 1g coupling from both x and y direction. (b) Portion of zoomed (a). (c) Same as (a), lateral accelerat ion is 3g in both x and y direction. (d) Portion of zoomed (c). original C1 and C2 with lateral motion coupling C1 and C2 coupled by X motion Legend for all plots C1 and C2 coupled by Y motion (c) (d) -0.47 -0.46 -0.45 -0.44 -0.43 -0.42 -0.41 -0.4 10.2675 10.268 10.2685 10.269 10.2695 10.27 10.2705 10.271 Acceleration in z direction (g)Capacitance change (fF) -10 -8 -6 -4 -2 0 2 4 6 8 10 9.8 9.9 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 Acceleration in z direction (g)Capacitance change (fF) -10 -8 -6 -4 -2 0 2 4 6 8 10 9.8 9.9 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 Acceleration in z direction (g)Capacitance (fF) -0.7 -0.65 -0.6 -0.55 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 10.26 10.265 10.27 10.275 10.28 Acceleration in z direction (g)Capacitance (fF)(a) (b) C1 C2 C2 C1 C2 C1 C2 C1

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96 Figure 4-8. The relation between capacitance ch ange and the number of volume elements in mesh shows a convergent trend, indicat ing the reliability of the simulation. 4.4 Summary Two CMOS MEMS accelerometers, including one single-axis and one 3-axis integrated accelerometer, have been designed an d their performances ar e predicted in this chapter. These devices are designed to have applications in engi neering monitoring and human activity monitoring and sensing, in wh ich small size, robust structures and low noise floor are required. The devices are intended to be fa bricated using the proposed new post-CMOS MEMS technology. Due to th e SCS incorporated in the sensing comb fingers, large sensing capacitance and high sensiti vity can be achieved for in-plane lateral acceleration. The independent etching processe s for the electrical isolation and comb fingers and other mechanical structures enables less undercut on the comb fingers, which further increases the sensitivity by reducing the gap between the fingers. In the 3-axis accelerometer, the torsional z sensing elemen t is embedded in the proof mass of a dual0 0.5 1 1.5 2 2.5 x 104 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Meshing element numbersCapacitance change under z acceleration (fF)-10g -5g

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97 axis in-plane lateral accelerometer. Sidewa ll and fringe capacitance of the CMOS metal layers is employed in the zaxis sensing. By swapping th e symmetrically distributed sidewall capacitors, fully differential sensing is accomplished in z sensing as well as the lateral sensing.

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98 CHAPTER 5 SOME ISSUES IN THE DEVICE FABRICATION In the fabrication of the designed devi ces, especially that of the 3-axis accelerometer, which has over five hundred sensing and driving comb fingers, some issues particularly relating to the improve d DRIE CMOS-MEMS process were observed. These issues include: problems in the top metal layer removal, isolation trench contamination caused by subsequent etching steps, and comb finger undercut due to the thermal effects in the plasma processes. In this chapter, these specific practical issues observed in the device fabrication are addre ssed, and solutions to these issues are presented. Not only are these solutions valid to the fabricated accelerometers, but also to other MEMS devices with similar suspended structures fabricated using dry plasma etching. In particular, these fabricatio n methods can be used in the post-CMOS microfabrication of MEMS gyroscopes, in which both suspended driving and sensing structures exist [70]. In add ition to the general design rules generated from the ordinary etching system characterization, as describe d in Chapter 2, some other significant MEMS design rules can be extracted from these obs ervations for the design and optimization of the similar MEMS devices. 5.1 Top Aluminum Layer Removal When the improved DRIE post-CMOS MEMS technology is employed in the microfabrication of the designed CMOS-MEM S accelerometers, the top metal layer on the devices are only used to define the electr ical isolation structur es, which isolate the comb fingers from the substrates, as shown in Figure 3-4(b). After the formation of the

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99 electrical isolation structur es, the top metal layers are removed to expose the other mechanical structures on the accelerometers. In practice, this step is performed after the first SiO2 etch, as shown in Figure 3-5(c). Cl2-based plasma aluminum anisotropic etch can be used in the top metal layer removal. Normally Cl2 is mixed with BCl3, which plays an important role in removing the local native Al2O3 layer and scavenging water vapor absorbed on the Al surface [87]. Due to the unavailability of BCl3, the aluminum dry etch was only tested using Cl2/Ar gas mix. After experiments, it is shown that the residues on the chip surface after the Cl2/Ar plasma etch pose a severe risk to the later processes. Without BCl3, some big clusters of involatile by products remain on the device surface, forming micro masks in the later etching pro cesses. Figure 5-1 shows a cluster of these residues. The typical size of the i ndividual residue is approximately 4 m3 m. Figure 5-1. A cluster of the residual byproduct formed in the aluminum plasma etch using Cl2/Ar chemicals.

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100 A special low-cost and clean wet Al et ch process was developed to avoid the potential micromasking effect of the residues in the Cl2 plasma etch described above. In order to protect the sidewalls of the metal la yers other than top layer, which form the isolation beam, a polymer layer is deposited over the whole device using the passivation cycle of the Bosch process. Then, a regular deep silicon etch follows to remove the polymer on the top surface of the device and the bottom in the isolation trenches. Note the polymer layer remains on the sidewalls of th e isolation trenches in this etch step, as shown schematically in Figure 5-2(a). Next the standard Ashland aluminum etchant (Phosphoric acid: nitric acid: acet ic acid: de-ionized water = 16 :1:1:2) is used to etch the exposed top Al layer at 40C The top Al layer (about 0.8m in thickness) is etched away in approximately two minutes and ten seconds. No apparent aluminum undercut was observed on the sidewalls of the isolation b eams due to the protection of the remaining fluoride polymer. Figure 5-2(b) and (c) show the isolation beam wetly etched using the aluminum etchant with and without the passiva tion layer protection on the sidewall. It is clear that the sidewall of aluminum layers in the isolation beams has been greatly improved with the polymer layer protection. Although this polymer passivation method is effective for the aluminum sidewall protection, it introduces one more process step and increases the fabrication cost. One easier way to avoid this extra step is to prot ect the aluminum in the isolation beams with SiO2 layer. This can be easily realized in the design step. Figure 5-3 illustrates the cross section view of the designed isolation beam structure before and after the SiO2 etch. M2 and M3 beams are designed slightly narro wer than M4 beam. Thin vertical SiO2 spacers

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101 will be left on both sides of the stack after the SiO2 etch, which act as protection to the inner aluminum beams in the following wet Al etch. In practice, the first SiO2 etch can stop anywhere between M1 and M3 before the top M4 removal. This also can effectively reduce the chance of M2 and M3 exposure due to the undercut on SiO2 spacers in the long plasma etch. Figure 5-2. The mechanism and result of th e sidewall protection in the aluminum wet etch. (a) schematic of the polymer protect ion; (b) isolation beams after the wet etch of the top aluminum layer w ithout polymer protection; (c) same structures after the aluminum wet etch with polymer protection. (a) Deposited polymer for protection Si substrate Pattern of the isolation hole Al SiO2 (b) (c) Isolationholes Protected Al beam Comb drive

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102 Figure 5-3. Formation of the Al sidewall pr otection spacers on the isolation beams. (a) before SiO2 etch; (b) after SiO2 etch. 5.2 Dry Etch Caused Device Contamination Sidewall and surface contamination of the device during the process is a very common phenomenon in the dry plasma etches and has been investigated intensively [125-132]. The reported research efforts main ly focused on the physical and chemical principles of the contamination formation from a metallurgical point of view. The samples used in these research efforts had only simple patterns and the process time was relatively short. In MEMS de vices, the dry etch process caused device contamination is more severe because of the complexity of ME MS structures in all three dimensions and the longer etching time. If multiple plasma process steps are required in the microfabrication of a MEMS device, the microfabrication would be even more challenging due to the cross contamination. In the microfabrication of the designed 3-axis accelerometers using the improved DRIE pos t-CMOS MEMS technology, the cross contaminations caused by the alternate SiO2 RIE and Si DRIE plasma etch steps are identified as the major reason for the failure of device release. The main contamination M1 M4 Si substrate SiO2 spacer on both sides of the beam stack SiO2 (a) (b)

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103 occurs on the sidewalls of the isolation tren ches. In particular, the additional isolation trench etching specifically needed in the developed DR IE CMOS MEMS technology introduces more potential device contamina tion. The involatile contaminants on the sidewalls act as micro masks in the following plasma etch steps, leaving some tiny connections between the movabl e and fixed structures after all the etching processes are completed. Figure 5-4 shows the SEM photos of th e etched-through comb fingers in a fabricated 3-axis accelerometer. As observed from the backside of the device, all other regions on the comb fingers were etched th rough except for the narrow connections along the both ends of the fingers. In many case, th is connection line causes the failure of the device release. In this section, the sources of the contamination are investigated and corresponding methods to avoid or overcome the contaminations are presented. 5.2.1 The Sources of Contamination The contamination sources in the device fabrication include debris and residues generated in the dry etch steps which fell onto the front surface; the inhibitor and sputtered particles on the sidewall of the structures; and the additional contamination layer on the sidewalls of the isolation trench es and on the backside surface of the device which is caused by the backside scatteri ng of the ions. The mechanism of the contamination formation are schematically illu strated in Figure 5-5. The contaminants originate from a variety of sources and have particular impacts on the mechanical structure formation in the accelerometers They are detailed as the following.

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104 Figure 5-4. SEM photographs of the et ched-through comb fingers. The narrow connections along the ends of the comb fingers are caused by the micromasking effect of the contaminant on the sidewall of isolation trenches. (a) top view from the backside of devi ce, (b) side view by rotating the sample for 90. Figure 5-5. Schematic of the cont amination in the plasma etch. Micro connection Comb fingers Isolation trenches (b) (a) Carrier wafe r Isolation trenches Debris Inhibitor Photoresist or cool grease Photoresist degas Scatterin g Contaminant accumulation Ions

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105 5.2.1.1 Front surface contaminants The contaminants on the front side of the device include the debris generated physically during the etching process and the residues of the involat ile byproducts after a chemical etching process. Note that the involatile by-products he re differ from the inhibitors in SiO2 etch. By optimizing an etching r ecipe, the chemical byproducts can be controlled very well. The sources of the de bris, which consequently are mainly the physical contaminants, include the accumula ted polymers on the chamber walls of the etcher and the sputtered or milled movable particles from the neighboring materials. Figure 5-6 shows the contamination on the fr ont side of the device observed at the interval of etching processes. In Figure 5-6(a), the debr is found after the first SiO2 etch turned out to be a tiny piece of photoresist bom barded from the coating resist layer on the carrier wafer on which the chip being processe d was glued. Whereas in Figure 5-6(b), the source of the movable debris on the surface is believed to be a piece of polymer falling from the chamber walls of the etcher. Once these photoresist and/or polymer de bris fell onto the surface where the structure pattern is located, they would play a role of etching mask and the SiO2 or SCS underneath them would not be removed after the dry etch. The movable structure would remain electrically and/or mechanically connected to the substrate if these debris particles happen to be on the top of the corresponding patt erns. Figure 5-7 is a top view of a few z element sensing finger observed from the back side after the device release. Due to the existence of a piece of contaminant on the fr ont side during the processes, one spot connecting a rotor finger and its neighboring st ator comb finger was formed. This single connection just causes the failu re of the device release.

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106 Figure 5-6. Front side surface contamination caused by the physical process in the plasma etching. (a) a small piece of photoresist was sputtered from the carrier wafer. (b) a piece of polymer scattered to the backside of a device. Figure 5-7. Structure connecti on caused by the debris on the front surface generated in the plasma etch. Photoresist Debris scattered on backside (a) (b) Connection spot Rotor sensing finger Stator sensing finger Polymer

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107 5.2.1.2 Isolation trench sidewall contamination The most severe process contamination hindering the successful release of the accelerometers is the contamination of the sidewalls of the isolation trenches. The sources of this contamination come from th e plasma etching steps after the isolation trench etch. As illustrated in Figure 3-5 of the process flow the improved DRIE CMOSMEMS process, there are sti ll two plasma etching steps after the formation of the isolation trench, i.e. the SiO2 etch to open the pattern of other MEMS structures and the Si DRIE for the final device release. It has been proven that the second SiO2 etch after the trench etch contributes most of contamina tion on the sidewall of the isolation trenches. Figure 5-8 shows the SEM photograph of part of an isolation trench and the energy dispersive spectroscope (EDS) analysis of the composition on the sidewall of the isolation trench. The SEM image and EDS were taken after 10 cycles of Si DRIE in the last release step. The spectrum was obta ined by scanning the ci rcled region on the sidewall of the isolation trench. The compositional analysis clearly indicates that the contaminants on the trench sidewall mainly originate from the SiO2 etch in which the shown elements, F, O, and C (very small peak) were involved in the etching chemical of CHF3 and O2. These contaminants are actually the inhibitors formed in the SiO2 etch. Since both ends of the trenches between adjacent sensing fingers are open in the SiO2 etch, the inhibitors, mainly involatile oxide and fluoride, will fall into the isolation trenches and deposit on their rough sidewalls, as illustrated in Fi gure 5-5. Another possible source of the contaminants is the fluoride polymer generate d in the passivation cycle of Si DRIE. The passivation polymer can stay on the rough tren ch sidewall, hiding in the micro caves caused by the ion scattering during the isolation trench etch. Since aluminum is present in

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108 the compositional spectrum as well, it is believed that Al atoms are also sputtered directly from the device surface where the top aluminum layer covers everywhere. Figure 5-8. SEM image and EDS spectrum of pa rt of an isolation trench and peripheral structures. (a) SEM photograph, (b) EDS spectrum of the circled region on the trench sidewall. It was observed that the contaminants on the sidewalls of the isolation trenches described above tend to accumulate on the bot tom region which is close to the back surface of the structure, as show n in Figure 5-5. This is easy to be understood. During the anisotropic etch of SiO2 and SCS after the formation of the isolation trench, the impinging energetic ions hit the contaminants and eventually sweep them to the bottom region in the trench. It is from there that they act as a micromask in the following Si DRIE, leaving a connection line along the ends of the comb fingers next to the isolation trenches, as shown exactly in Figure 5-4. Since the isolation trenches were formed by performing an isotropic undercut after the anisotropic DRIE which etched through the isolation holes, the profile of the isolation trenches would not be straight on the sidewall due to the screening eff ect of the isolation beams in the silicon DRIE. Micromask resulted from th e co ntaminant s (a) (b)

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109 Figure 5-9(a) shows a broken structure w ith exposed sidewall of an isolation trench. The sidewall has a positive angle with respect to the plane of the back surface. This profile narrows down the isolation trenches in the bottom region, making the contaminants prone to accumulate there. A bow ed profile has the same trend to collect contaminants there at the trench bottom, as shown in Figure 5-9(b). Figure 5-9. SEM image and schematic profile of an isolation trench sidewall with rough surface. (a) SEM photograph, (b) schematic profiles of the positive and bowed isolation trench. 5.2.1.3 Back surface contamination Another type of contamination takes place on the backside of the thinned substrate diaphragm, as shown in Figure 5-5. The formation of this co ntamination can be classified into two categories with different mechanis ms. The first is the redeposition of the particles onto the back surface of the device by backside scattering of the impingent ions. Since the isolation trenches are already open during the second SiO2 and the last Si DRIE Trench sidewall with positive angle Isolation holes (a) (b) B owed s i dewa ll

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110 step, particles are sputtered from either the front surface or the trench sidewalls, falling onto the surface of the carrier wafer just bene ath the isolation trenches. Scattered by the impinging ions through isolation trenches, some of these micro particles can redeposit onto the back surface of the device diaphragm. The second mechanism is the degassing of the photoresist that is used to glue the device chip on the carrier wafer. During the soft bake of the photoresist at 95C, or, even during the anisotropic SiO2 etch and Si DRIE in which the chip temperature can be over 100C due to the energy radiation from the plasma and the ion bombardment, the photoresis t experiences a degassing process. In the enclosed backside cavity, organic compounds evaporate fr om the photoresist and deposit on the back surface of the diaphragm to form a thin resist layer. These contaminants on the backside of the device, although not as severe as that on the sidewall of the isolation tren ches, also play negative roles in the release of the device. After the SCS is etched through in the final re lease step, the contamin ant layer still keeps the movable part of the device connecting the stators mechanically, resulting in an unfunctional device. 5.2.2 Solutions to the Device Release with Contamination Some processes, especially physical pro cesses such as sputtering and sputteringinduced particle redeposition, are inevitable in plasma processes. Therefore, in the fabrication of the devices, in addition to the optimization of the etching recipe to have a better control over the physical and chemical reactions, the procedure of the processes should also be arranged appropriately. In this section, e fforts are made not only to tune the etching recipes for the reaction control, but also to create some additional processes to

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111 minimize or avoid the contaminations on th e device surfaces. These solutions to the contaminations are addressed in the sequence corresponding to that in the last section. 5.2.2.1 Surface debris prevention As described in the last section, the sour ces of debris on the front surface include the dirty chamber wall and the exotic materials around the device chip, mainly photoresist in this device fabrication. Th e polymer accumulated on the chamber wall not only affects the etching process by changing th e composition of the chemical gases, but also generates dusts in the etching that fall onto the front surface of the device, forming the debris mentioned above [133]. When the etcher has multiple users, the different chemicals used by each user just make the cont amination worse. Therefore, a clean etcher chamber must be maintained in any plasma et ch. Due to the heavy load of the facility usage in this research work, the chamber of the SiO2 etcher should be physically cleaned with acetone every two weeks. Moreover, before and afte r each etching run, additional oxygen plasma cleaning of the chamber helps to scavenge the micro polymer dusks in the chamber. Before the sample is loaded, running a dummy sample with th e actual recipe is an effective method to get some particles pi nned in their original positions. 5.2.2.2 Sidewall contamination control As described in last section, the main obstacle to the successful release of the device is the sidewall contamination of the is olation trenches. Both chemical and physical measurements have been taken to minimize or remove this type of contamination which mainly originate from the anisotropic SiO2 etch. As shown in Figure 2-8(a), the thick inhibitor film left from the SiO2 etch also acts as a mask in the final comb finger etch. It has a screening eff ect on the SCS underneath the film. The chemical method includes mainly the SiO2 etching recipe tuning to reduce

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112 the fluoride polymer inhibitor generated on the sidewall of is olation holes. By optimizing the flow rate ratio of CHF3 and O2, both acceptable etching rate and minimum inhibitor generation can be achieved. This effort has already been shown in Figure 2-8. It is difficult from the front side to chemically remove the contaminants accumulated on the sidewall at the bottom of de ep isolation trenches. An additional Si anisotropic etching step is added to remove the contaminated area from the backside. To do so, the silicon diaphragm should be left thic ker than the intended thickness in the first backside Si DRIE as shown in Figure 3-5. Since the accumulated contaminants normally exist at the lower part of the isolation trench with a few microns from the backside of the device, to keep the fina l structure thickness as 50m, approximately 60m diaphragm should be left after the first b ackside silicon etch. Right before the last DRIE step for the final release of the device, the chip is flippe d over and glued on a clean carrier wafer with tiny amount of photoresist. The surface of the substrate frame is protected with photoresist after the device backsi de is cleaned in an ashing oven. Normal Si DRIE using Bosch process is then performed on the back si de to etch a few microns of the diaphragm. During this additional etch step, most of the fluoride polymer accumulated close to the back side surface on the sidewall of isolation trenches is removed. The very small amount of remaining aluminum com pound is sputtered by the ions to distribute through the backside surface, losing the function as micr omask. In addition, due to the larger exposure area, the edges of the isolation trench es are cut and a V shape groove is formed at the entrance of an isolation trench from back side. This V shape profile is beneficial to the final release of the device from the front side. Figure 5-10 illustrates the additional Si DRIE process on the back side and the comb fi ngers after the final release etching step.

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113 Figure 5-10. Fabrication method using additional etch on backside. (a) schematic of the function of the additional backside Si DRIE, (b) comb fingers released without and with the additional backside etch. With the additional backside Si DRIE, the contaminants are removed and the chance of the successful device release is in creased greatly. This is achieved at an expense of the reduced electrode area of th e parallel capacitors due to the formation of the V shape isolation trench, which cuts the comb finger ends close to the back surface. According to the device dimensions, it is esti mated that the total capacitance will reduced Accumulated contaminants Connection caused by the contaminants (a) (b) Isolation beams Isolation trench with V shape entrance

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114 by 3% due to the corner cut. For the lateral sensing element in the 3-axis accelerometer, the total capacitance for each lateral axis is as high as 400 fF, a 3% reduction of the sensing capacitance only causes ve ry limited performance drop. 5.2.2.3 Backside surface contaminant removal As mentioned in the last section, the a dditional Si DRIE performed on the backside of the device right before the final release step also helps to provide a clean back surface. Before this Si DRIE, the back surface can be pre-cleaned in an oxygen plasmas asher to remove most of the organic compounds de gassed from photoresist. The following DRIE process removes the other micro particles. Si nce the particle cont aminants generated by the ion back scattering are relatively small, even though they can not be etched, they will lose the function as a mechanical conn ection after the final device release. 5.3 Thermal Effect in the Device Release With a different mechanism, there exists another physical effect – thermal effect, which frequently causes the release failure of the 3-axis accelerometer. It is observed that normally this severe effect takes place on the suspended MEMS structures during the silicon DRIE of the final device release, more exactly, during th e overetch period after the etch reaches the ‘ending point’. The result of the effect is the severe lateral undercut on narrow suspending structures, which conseque ntly results in devi ce failure. Through extensive experiments, it has been unveiled that this lateral undercut is different in mechanism from the one tuned by changing th e etching/passivati on ratio in regular silicon DRIE described in Chapter 2. Sin ce this thermally-caused failure mechanism on suspended MEMS devices is prevalent, great atte ntion must be paid to it in the creation of related MEMS design rules. In this section, the mechanism of this overheat caused lateral undercut on suspended MEMS devices is discus sed and an effective fabrication technique

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115 has been developed to avoid this damaging thermal effect. A simplified lumped model has been created to estimate the temperature rise on the suspended z-sensing block, which is the real reason for the larger undercut. 5.3.1 Mechanism of the Undercut Caused by Thermal Effect Figure 5-11(a) shows the severe undercut on a torsional spring of z sensing element after the device is released. The 3m-wide torsional spring of the z sensing element was undercut approximately by 0.85m on each side, leaving th e width of the SCS on the spring only less than 1/3 of the designed va lue. This undercut on the torsional springs changes the mechanical performance of the de vice dramatically. What is worse, in many cases with only seconds of more overetc h, the SCS on the springs was undercut completely, resulting in a broken thin-f ilm beam. A similar phenomenon was also observed on the electrically isolated rotor sens ing fingers of the lateral sensing elements. In another experiment, after an overetch pe riod of 30 seconds with the standard SCS DRIE recipe described in Chapter 2, the late ral rotor fingers connecting to the proof mass of the lateral sensing element are complete ly etched away, as in Figure 5-11(b). As mentioned above, this la teral undercut is different in mechanism from the normal undercut caused by the large etching/ passivation ratio in Bosch process. The evidence is that under the same etching conditi on, the right part in Figure 5-11(a), which is the proof mass of the lateral element where the z element is embedded, has no apparent undercut on the sidewalls. Similarly, the stat or fingers in Figure 5-11(b) keep in good shape after the overetch while the roto r fingers are completely etched.

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116 Figure 5-11. Undercut caused by the overheating of the structure. (a) undercut of part of a z-axis torsional spring, (b) rotor sensi ng fingers of a x-axis sensing element. SEM images were taken from the back side of the device. Stator fingers connected to the substrate Rotor fingers connected to the proof (b) (a) Torsional spring of z sensin g element Proof mass of the lateral element

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117 The direct reason for the large undercut ra te is the elevated temperature on the suspended MEMS device during the overetch period, which results in increased etching rate. Assuming that in the silicon DRIE of the device release step, the etching rate is determined by the surface reaction rate rather than the reactive radical flux to the etching surface. The general relationship between the reaction rate and surf ace temperature at the reaction spot is given by the Arrh enius Equation, which reads [134], exp()E rA R T (5-1) where r is the general reaction rate of a chemical process, E is the surface activation energy, R is the molar gas constant with positive value and A is the frequency constant in the reaction. Qualitatively, there is a positive feedback among the heat generated in the reaction, the temperature rise of the structure bei ng etched and the etching rate. Once the equilibrium in either step is broken, c onsequently the reaction rate will increase dramatically. The etching rate as a functi on of the substrate temperature has been investigated with other materials based on empirical results [135]. To estimate more quantitatively the unde rcut etch rate increase caused by the temperature rise, a plasma energy transfer m echanism should be investigated to bridge the etching process parameters and the etchi ng rate. To achieve this, it is necessary to have an estimation of the temperature diffe rence between the suspended structures and the substrate during the overetch time. In a ICP chamber where co llisonless Bohm sheath exists, the ion power density P, in the unit of W/m2, can be expressed as [136],

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118 1 2()e s biaseT PnqV M (5-2) where ns is the ion density, e is the electron charge, Te is the electron temperature measured in eV (2 ~ 3eV for normal ICP system), Vbias is the DC bias on the sheath and M is the mass of the reaction ion. Here the z sensing element, in which the undercut happens on the torsional springs frequently, is exemplified. Assuming all the ki netic energy of the impingent ions converts into heat which rises the temperature of th e z proof mass and the temperature on the proof mass is uniform. The structure is shown in Fi gure 5-12(a), with dimensions in Table 5-1. The simplified lumped model as shown in Fi gure 5-12(b) can be used to evaluate the temperature rise. Suppose T is the temperature on the proof mass, T0 is the temperature on lateral proof mass in which th e z proof mass is embedded. The heat capacitance of the z proof mass can be calculated as mCCV (5-3) where V is the total volume of the z element. and Cm are density and specific heat of silicon respectively and their values are given in Table 5-1. The thermal resistance of the torsional springs is, 1 2 L R kwt (5-4) where L t and w are the length, thickness and width of the torsional spring, respectively. k is the thermal conductivity of silicon and its va lue is listed in Table 5-1. The factor of 2 is due to the fact that there are two torsional spring on the z-axis sensing element. It is clear the two torsional springs contribute most of the thermal resistance. Plugging in the

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119 dimension of the z block, the thermal time constant of the system R C can be calculated as 0.183 second. Figure 5-12. Model of the z sensing element for temperature rise estimation. (a) 3D model of the z proof mass, (b) the simplified thermal model. Table 5-1. Dimensions of the z element a nd the parameters used in the analysis. Dimensions or parameters Values Thickness of the structure (t) 50 m Torsional spring (LsWs) 400 m 5 m Proof mass 1 (Lm1Wm1) 300 m 700 m Proof mass 2 (Lm2Wm2) 260 m 80 m Proof mass 3(Wm1Wm3) 300 m 40 m Thermal conductivity of s ilicon (k) 98.9 W/(K.m) Specific heat of silicon (Cm) 712 J/(kg.K) Density of silicon ( ) 2330 kg/m3 Torsional spring Proof mass L m 1 L m 2 W m 1 W m 2 W m 3 t T0T0T T0 T C R (a) (b)

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120 With this short time constant, the system will rapidly reach the steady state once the structure is released. The following equati on can be obtained for the thermal current running from the z proof mass to the lateral proof mass through the two torsional springs. 0 0() (())()TtT dQdd PACTtTt dtdtdtR (5-5) Then, the temperature on z proof mass can be expressed as, 0()(1exp())t TtTPAR R C (5-6) Figure 5-13 shows the plot of the temper ature change on the z proof mass with respective to the lateral proof mass, where the temperature is set to 50 C due to the backside helium cooling. After the system reaches its equilibrium state once the overetch starts, the temperature difference between th e z proof mass and the lateral proof mass can be as high as 148.3 C. This explains why the larg e undercut was observed on the z sensing block. Figure 5-13. Calculated temper ature rise on z proof mass. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 20 40 60 80 100 120 140 150 Time (s)Temperature rise (degree C)

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121 It should be noted that the abrupt temp erature rise on the suspended accelerometer structures only takes place in the overetch pe riod after the structures are released. Before the ‘ending point’ of etch-through, movable structures are stil l connected to the substrate through the remaining silicon at the bottom of the silicon diaphragm, which provides a good heat path to prevent the abrupt temper ature rising on the stru ctures being etched. Due to the microloading effect and ARDE, structures with different trenches have different etching rates, result ing in their different release points. Structures with wider trenches are etched through earlier than t hose with narrower trenches. After they reach the ending point first, these structures st art to experience an overetch during the remaining etch time for those with narrower tr enches. Since the heat path provided by the connecting SCS does not exist any more, the re leased structures are thermally isolated from the substrate. Therefore, it is in this overetch period that the temperature of the suspended structure rises rapidly, resulting in the fast lateral undercut on all the suspended z proof mass. Figure 5-14 shows a nother SEM image of the z sensing fingers after the overetch in the rel ease step. More undercut can be found on rotor sensing fingers than on the stators. The reason is that the la teral proof mass, where the stator fingers are connected, has larger thermal conductance to substrate and thus ha s lower temperature than the z proof mass connecting the rotor fi ngers. The higher temperature on the z proof mass also increases the etching caused by th e radicals back scatte red from the carrier wafer, deteriorating the back su rface of the suspended z block. Similarly, on the lateral sensing element in the 3-axis accelerometers fabricated using the proposed new DRIE CMOS MEMS tec hnology, the electrical isolation trenches are first etched. After the sens ing fingers are etched through in the final release step, the

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122 silicon on the comb fingers are only connected to the proof mass or substrate through the electrical isolation beams which consist of only thin films of CMOS stacks. The low thermal conductance of the narrow composite CMOS stack also causes the temperature rise on the lateral comb fingers, giving rise to the unique undercut on these fine fingers, as shown in Figure 5-11(b). Figure 5-14. Lateral undercut on the rotor sensing finger of z element. The back surface of the z block is also deteriorated du e the higher temperature on the block. 5.3.2 Fabrication Method for the Suspended MEMS Devices The key factor that causes the large underc ut on the fine structures of suspended devices is the reduced heat paths from the suspended MEMS structures to the substrate once the device is released. The ultimate solution for this overetch-caused structure damage includes two aspects. The first is the design issue. Mi croloading and ARDE effect should be very carefully considered in the design stage to a ssure a proper device release sequence for different types of structur es. The suspended fine structures should be Stator Rotor Z proof mass

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123 released lastly to avoid the temperature rise on them. The second aspect involves the process monitoring. In device fabrication, if the etching ‘ending point ’ in the release step could be precisely detected, the process coul d be terminated immedi ately after the final point was reached to avoid the thermal effect caused device damage. However, the in-situ detection of the ending point requires speci fic monitoring systems which are unavailable to this research. The alternate method to overcome the thermally caused device damage described above is to provide additional thermal path for the suspended struct ures during the short overetch period. A couple of materials can be used to provide the external thermal path. For instance, a thin layer of metal with good th ermal conductivity can be sputtered to the backside of the silicon diaphragm. During the final release step, the sputtered metal layer provides an extra heat path from the suspende d structures to the solid substrate. A layer of PECVD SiO2, even with lower thermal conductivity can also functio n as the heat path. However, these additional layers will introduce extra processes and must be removed finally, which complicates the rel ease of the device in another way. In practical fabrication, hard baked photoresist was employed to provide the external thermal path in the device releas e. To keep the back surface clean, the photoresist was applied to the backside of the silicon dia phragm right after the first backside DRIE. To withstand the temperat ure rise in the plasma processes, the photoresist should also be hard baked to avoi d any reflow during the processes. After all the fabrication processes are finished, the photoresist can be ashed away in an oxygen plasma asher and simultaneously, the device is released. Figure 5-15 shows the modified

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124 process flow of the 3-axis accelerometer fabric ation. It is the same as Figure 3-5 except for the photoresist application af ter the backside etch in Fi gure 3-5(a) and the photoresist ashing step in Figure 5-15(f). The photores ist used for backside coating was AZ9260. After the application, it was soft-baked at 90 C in oven for 30 minute and then hard baked at 120 C for 1 hour 30 minutes. Figure 5-15. Modified accelerometer fabri cation process with photoresist coating on backside. Figure 5-16 shows the backside image of the device after the final Si DRIE. The comb fingers and lateral mechanical springs ca n be seen through the co ated photoresist. It (a) (b) (c) (d) (e) (f) Photoresist for external thermal path

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125 can also be found that cracks were developed in some area of the photoresist layer. That is due to the relative large thickness of the resist re quired for enough conductance. Figure 5-16. Etched-through structures obs erved through photoresist coated on the backside of the device. Figure 5-17 is the top view of a fabricat ed device observed from the backside. The removal of the photoresist completes the fabrication process. Comb fingers and mechanical springs are etched through without apparent undercut, as shown in the insets. The good release result suggests that this fa brication method with backside photoresist coating is effective to avoid the severe undercut on the suspended MEMS structures during the overetch for device release. It is noted that due to the footing effect caused by the ion scattering at the interface of the coated photoresist and the silicon on the diaphragm, part of the SCS at the bottom of the structures is etched, leaving a slope d shape on the bottom of the structures. This Crack in photoresist Etched through comb fingers

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126 can be observed in the insets of Figure 5-17 as well. This effect is similar to the entrance enlargement described in section 5.2 to re move the contamination. Therefore, with backside photoresist coating, the profile of the electrical isolation trenches can also be tuned by ion scattering inside the trenches This makes the release even easier by redistributing, if not completely removi ng, the contaminants generated during the multiple etching steps. Figure 5-17. Fabricated device with most structures released. The structure damage caused by the thermal effect is a voided by coating photoresist on the backside of the device.

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127 Since photoresist itself is not a good therma l conductor, other materials with higher thermal conductivity are highly desired. To be used as an additional thermal path in the specific process for the suspended MEMS devi ce release, these materials should also be easily removed without any damage to the ME MS structures after the etch processes. Some thermal conducting polymers could meet this requirement. 5.4 Summary In this chapter, some practical issues in the fabrication of the accelerometers using the new DRIE CMOS-MEMS process are addressed. These issues include both the common phenomena in plasma etch and the specific problems caused by the particular process steps in the new DRIE CMOS MEMS technology developed. By arranging the process sequence or adding some easy process steps, the device release yield has been greatly increased. The proposed methods to overcome the contamination on the sidewall of the isolation trenches we re proven effective. The additional thermal path method is also valid for the fabrication of other suspended MEMS devi ces that are released by dry etch.

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128 CHAPTER 6 DEVICE CHARACTERIZATION Both the 3-axis and single-axis integrated CMOS-MEMS accelerometers have been fabricated successfully using the improve d DRIE post-CMOS MEMS microfabrication process described in previous chapters. These devices have been tested intensively. In this chapter, the experimental methods are introduced, followe d by detailed test results of the 3-axis and single-axis CMOS-MEMS acceler ometers. All the tests were conducted in open air. The dynamic tests were performed on a vibration-isolated optical table to eliminate the spurious environmental mechan ical vibrations. In total, nine 3-axis accelerometers were characterized. The test results reported in this thesis are from different devices. 6.1 Device Package To reduce the size of the test boards and minimize the mechanical modes of the boards, the fabricated devices are packaged in 52-pin ceramic leaded chip carriers (CLCC). Accelerometer chips are hand-aligned and glued in the carrier cavities using silver epoxy with minimal misalignment with rega rd to the package. In chip gluing, it is important to press the solid part of the die uniformly to ensure a flat assembly and help reduce the output offset. Figure 6-1 shows the photographs of one packaged 3-axis accelerometer and the bonded die in which the locations of the accelerometers and other structures are labeled. The die pin-outs and the bonding configur ation are given in Appendix B.

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129 Figure 6-1. Photographs of the packaged de vice. (a) Device packed in CLCC-52 carrier, (b) bonded die showing the locations of the devices. The packaged devices are mounted on a te st printed circuit board (PCB) through a 52-pin plastic leaded chip car rier (PLCC) socket. To further reduce the mechanical modes, the test PCB board is split into a mounting board and a supporting board. They are connected to each other by detachable soft parallel wires, as s hown in Figure 6-2. Figure 6-2. 3-axis accelerometer test PCB board. 3mm 3mm X circuit Z circuit Y circuit Single-axis acceleromete r ( a ) ( b ) Test structures Mounting b oar d Support board Connecting i 3-axis accelerometer

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130 6.2 Test Setups The facilities and instruments used in th e comprehensive tests of the fabricated CMOS-MEMS accelerometers include a rotary table, a vibratory shaker and their controllers; network spectrum analyzer for noise measurement; and other general benchtop instruments for electrical measurement. A Polytec laser vibrom eter is employed for the mechanical test (resonant frequency) of the z-axis accelerometer. Commercial reference accelerometers are used for th e purpose of device calibration. The motion generation devices and electrica l instruments used in the accelerometer characterization are tabulated in Table 6.1. 6.3 3-Axis Accelerometer Test Results The characterization of the fabricated devi ces can be categorized into quasi-static test, dynamic test, noise measurement, mechan ical test (resonant frequency), temperature test and process verification. In this section, the 3-axis accelerometers test results are presented separately before the summary of the device performance. Due to the process variations, the fabricated devi ces have slight dimensional va riations as compared to the designed values described in Chapter 3. The tested devices come from the same fabrication batch. There was approximately 0.2 m undercut on the sensing comb fingers and mechanical springs. The thickness of the sensor was about 37 2 m. These process variations were considered in the calculati on of theoretical device performance. Other microstructure dimensions ar e listed in Table 4-4. Figure 6-3 shows some microstructures on a released 3-axis accelerometer, with typical process variatio ns described above.

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131 Figure 6-3. Sensing comb fingers on a 3-axis accelerometer. (a ) and (b), Front side view of the lateral fingers with a 52 tilting angle; (c) and (d), Backside view of the lateral fingers with a 52 tilting angle; (e) and (f), Backside view of z-axis fingers with a 52 tilting angle. (a) (b) (c) (d) (e) (f)

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132 Table 6.1. Instruments and setups for the ch aracterization of fabric ated accelerometers. Item Name Maker and Model Specifications Rotary Table and Controller Klinger Scientific, CC1.1 Resolution: 0.002 Vibratory Table + Power Amplifier Ling Dynamic Systems, V408 + PE 100 Frequency range: 5 Hz ~ 9 kHz; Maximum acceleration: 50 g. Vibratory Table + Power Amplifier Bruel & Kjaer, Mini shaker Type 4801 + Amplifier Type 2718 Frequency range: DC ~ 18 kHz; Maximum acceleration: 550 m/s2 (~55g). Hand-held Shaker PCB Piezoelectronics, 394C06 1 g acceleration at 159.2 Hz. Network Spectrum Analyzer Stanford Research Systems, SR785 Dual-channel; Bandwidth: DC~102.4 kHz; Dynamic range: 90 dB. Oscilloscope Tektronics, TDS-2014 4-channel; Bandwidth: 100 MHz; Sampling rate: 1GHz/sec. Reference Accelerometers + coupler Kistler, Accelerometer: 8638B5; 8702B50; Coupler: Type 5118B2 8638B5 Acceleration range: 5g; Nominal Sensitivity: 979mV/g; Resonant frequency: 9.0 kHz, Accuracy: 1.0%. 8702B50 Acceleration range: 50g; Nominal Sensitivity: 100.4mV/g; Resonant frequency: 54.0 kHz, Accuracy: 1.7%. Laser Vibrometer Polytec, OFV3001 Scanner control: MSV-Z040 Displacement resolution (out-plane,) 8 nm. 6.3.1. Mechanical Test Results The mechanical test of the fabricated accelerometer was performed mainly to identify the resonant frequencies of the device in all three axes. Four methods can be used for the resonant frequency measurement. The first and most convenient one is to use the on-chip self-test unit in which comb drives are designed to drive the accelerometer structures electrostaticly by a pplying an external driving si gnal. The resonant frequency

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133 can be directly obtained by sweeping the fre quency of driving signal while monitoring the sensor output. In the second method, the st ructure is electrostaticly driven by external signal as in the first method. But the resona nt frequency is obtained by the displacement or velocity measurement, normally accomplis hed by optical interferometry measurement. The third one is to apply external accele ration directly on the accelerometer, normally by mounting the device on a shaker table, and by sweeping the frequency of the acceleration, resonant frequency can be obtai ned through the device output. The last one is to apply external acceleration on the microstructure and measure the velocity and displacement response using optical methods. Although driving comb fingers are designed on the proof mass for the self-test in all three axes, due to the complex and crowded global wiring on the integrated accelerometer chip, driving signal feed-through was observed in the sensor output, which resulted in unreliable frequency response. The mounting board in Figure 6-2 has some unidentified mechanical modes, which prevent method three in last paragraph from being used in the frequency test. We use met hod two and method four for the resonant frequency measurement. A Polytec OFV3001S scanning laser Doppler vibrometer is used to measure the velocity and acceleration respons e of the mechanically driven devices. This model of laser vibrometer is only capable of out-of-p lane velocity measurement. Therefore only the resonant frequency in the z-axis is obtained. Figure 6-4 is the block diagram of the setup for z-axis resonant frequency measurement. To remove the other mechanical modes in the system, a released device chip was directly glued on the end of the mini shaker shaft, as shown in the inset. The

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134 mini shaker (Bruel & Kjaer Type 4810), separa tely placed on the isolated optical table, was driven through the power amplifier (B&K Type 2718) by the signal generated by the scanner controller MSV-Z-040. A chirp driving signal with frequencies ranging from 100 Hz to 5 kHz was used to drive the mini shaker. The fi ber interferometer OFV-511 gene rates the input laser beam and receives the optical signal reflected fr om the sample surface, which contains the motion information of the detected area on the sample. The resulting optical signal is converted to an electrical si gnal by the laser diode in the interferometer and consequently decoded by the interferometer controller OFV3001S to obtain the velocity of the sample. With further computation based on the system configuration, other motion signals such as acceleration can be obtained. Figure 6-4. Block diagram of the Scanning La ser Doppler Vibrometer setup for z-axis resonant frequency test. Power Amplifier 2718 Scanner Controller MSV-Z-040 OFV-074 Microscope Adapter Fiber Interferometer OFV-511 Interferometer Controller OFV-3001S PolyScanDAQ PC Device Under Test Mini Shaker B&K 4810 Olympus BX61 Microscope

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135 Figure 6-5 shows the scanning area on th e z-axis proof mass and the detected acceleration of the proof mass ve rsus the driving frequency. The scanning area consists of totally 66 scanning spots. At each spot, 50 samplings were performed to obtain the average value. To obtain some more system information, part of the raw data from the above measurement is re-plotted in Figure 6-6, with the detected accelerat ion expressed in dB. With the resonant frequency of 1497 Hz, the qua lity factor of the z-axis sensing element is extracted as approximately 11, which indicates a low damping coefficient. This is exactly the case in the z-axis sensing stru cture where Couette damp ing of the vertical comb fingers has a smaller damping coefficien t compared to the squeeze-film damping in lateral sensing elements. Figure 6-5. The scanning area on the z-axis proof mass and th e frequency response of the motion in the scanned area. Scanned area

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136 Since no in-plane displacement measuremen t facility was available locally, the resonant frequencies in latera l axes were not performed. Figure 6-6. The detected acceleration vers us driving frequency around the z-axis accelerometer resonant frequency. 6.3.2. On-Chip Circuit Test[137] A replica of the two-stage, dual-chop per amplifier used for on-chip signal amplification was integrated on the same chip for the purpose of sole circuit characterization. This circuit was tested wit hout the sensor release. With a 3.3V power supply voltage of 3. 3V, it dissipates 300 A current, resulting in a power consumption of 1 mW. The measured gain of the on-chip am plifier is 44.5 dB, and a load capacitor of 1 nF is employed to form a low pass filter. The tested 3-dB bandwidth is 1.5 kHz. The noise performance of the circuit is addressed in Section 6.3.4. 400 600 800 1000 1200 1400 1600 1800 2000 -25 -20 -15 -10 -5 0 Driving frequency (Hz)Detected acceleration in dB (mm/s2)

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137 6.3.3. Quasi-Static Response By rotating the device under test (DUT) 180 about certain axis, 1g gravitational acceleration in the orthogonal axis will be applied to the DUT. For instance, suppose the DUT is rotated about the x-axis, if the rota tion starts from y-plane, by rotating the DUT 180 1 g acceleration in the y-axis can be a pplied to the device. The linearity and sensitivity of an accelerometer can be exam ined by performing the device rotation which generates 1 g gravitational acceleration. It is a qu asi-static process in which the sensor outputs are recorded at uniforml y distributed rotation angles. Figure 6-7 shows the diagram and photogra ph of the quasi-static test setup. The device mounting plate is perpendi cular to the rotation plate attached to the rotary table, which is vertically mounted on a rack perp endicular to the surface of the vibrationisolated optical table. The rotary ta ble has an angular resolution of 0.001 corresponding to approximately 17 g of acceleration resolution. The plots in Figure 6-8 show the quasi-stati c response of the tri-axis accelerometer in all three axes. With a 1.5V modulati on voltage, 560, 460 and 320 mV/g sensitivities are achieved in the y-, xand z-axis, respectively. Two versions of circuits were designed for the 3-axis accelerometer [137]. One was used for y-axis sensing and the other was fo r x-axis and z-axis. The gains of the two circuits are slightly different due to the different configur ations of the first and second stage amplifier. In addition to the gain difference between the two versions of interface circuits used for the xand y-axis, the different mechanical modes between the two sensing elements also contribute to the sensit ivity variation. The cr ab-leg xand y-axis springs in Figure 4-4 are co mpletely symmetric in both axes. However, due to the

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138 different modes of the embedded z-axis sensi ng element in lateral directions, which is caused by the imbalanced z proof mass, ther e is a slight difference in resonant frequencies for the xand y-axis, which also results in the different sensitivity in these two axes. Less than 0.35% of non-linearity is achieved in both lateral axes. Figure 6-7. Quasi-static test setup. (a) Block diagram of th e system, (b) photograph of the setup. Vi b ration-isolated tableAccelerometer Mounting board Mounting block Rotar y table Oscilloscope or multimete r (a) (b) Rotary stage controller Rotary stage Device mountin g p late Power supply Supporting test board

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139 Figure 6-8. Responses of the 3-axis accelerometer to 1g acceleration. The device demonstrates different non-linear ities in z-axis when rotated about xand y-axis, as shown in Figure 6-8. The non-li nearity is 2.1% when rotated about x axis and 4.7% about y-axis. This non-linearity in zaxis can also be considered as the crosstalk coupling from xand y-axis when the device is working in an acceleration range of 1g. Again, this is due to the asymmetry of the z sensing block. The larger value about yaxis is due to the fact that the z torsional spring can also be bent in y direction, which results in the non-linear capacitance change in the z-axis. This tre nd coincides with the simulated results shown in Figure 4-7. 6.3.4. Noise Measurement The noise floor of the accelerometer in unit of /gHzdetermines the minimum acceleration the device can detect. It consists of the thermo-mechanical noise of the sensor and the electrical noise from the interface circuit, as shown in Equation 6.1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 External acceleration generated by stage rotation (g)Accelerometer output (mV) z rotation about y-axis z rotation about x-axis x rotation about y-axis y rotation about x-axis

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140 2222()e nmemV aaaa S (6.1) where an, am, ae are the overall noise floor, thermo -mechanical noise and circuit noise respectively. S is the sensitivity of the accelerometer in unit of V/g and Ve is the inputreferred circuit noise measured in the unit of / VHz. With a dummy self-test circuit designed on chip, the circuit no ise and the overall noise can be measured independently. Then the thermo-mechanical noise (Bro wnian noise) can be calculated using Equation 6.1. The theoretical value of the mech anical noise is expre ssed in Equation 4.9. The noise performance of the device wa s characterized using a SR-785 network spectrum analyzer from Stanford Research Syst ems. First, the electronic noise from the interface circuit was identifie d. This was accomplished by measuring the noise floor of the dummy amplifier without a sensor c onnected. The performance of the 3-axis accelerometer in both x-axis and y-axis was characterized respectively. However, the xaxis and y-axis sensing element have different interface circuits, and only a replica of the y-axis sensing interface circuit was integrated on the chip for the purpose of pure circuit characterization. In the following sections only the characteristics of the y-axis accelerometer are presented to represent the device performance in both lateral axes. The noise density measured from the out put node of the dummy self-test circuit was 2.7 V/ Hz, as shown in Figure 6-9. With the measured 44.5 dB gain of the on-chip amplifier and a unit gain of an amplifier (AD623 from Analog Device, Inc., used as a buffer), the input-referred noise floor was 16.08 nV/ Hz. For a sensitivity of 560 mV/g, the input-referred electronic noise in y-axis is 4.82 g/ Hz. With the measured sensitivities in Section 6.3.2, the overall noise floor of the y-axis is 12 g/ Hz at 200 Hz.

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141 The z-axis sensing element has a noise floor of 110 g/ Hz at 200 Hz. Their spectra are shown in Figure 6-10 and Figure 6-11, respectiv ely. As a comparison, the spectrum of the noise floor measured without acceleration input is pres ented in Figure 6-12. The spectrum was obtained from the same device with a modified sens itivity of 260 mV/g. The same acceleration-referred noi se floor was observed compared to that in Figure 6-10. Figure 6-9. Electronic noise density of y-axis interface circuit whic h has an overall gain of 44.5 dB[137]. From Equation 6-1, the Brownian noise fo r the y-axis can be estimated as 10.98 g/ Hz. This noise level is larger th an the calculated value of 5.6 g/ Hz. The reason for the difference is that in th e practical accelerometer devices in addition to the squeeze damping of the comb fingers, material damping and joint damping in the micro structures, especially in the crab-leg mechan ical springs, also cont ribute to the overall damping coefficient, which consequently incr ease the Brownian noise floor of the device 2.7 V/ Hz

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142 [138]. Quantitative analysis of th ese two damping mechanisms is out of the scope of this thesis work. The dominant damping of z-sensing comb fingers is Couette damping which has much smaller damping coefficient, as describe d in Section 6.3.1. However, the sensor has much larger noise floor in z-axis. This is mainly due to the much smaller sensing capacitance and the larger electronic noise floor of the interface circuit used in the z-axis sensor. Figure 6-10. The output spectrum of y-axis accelerometer at 200 Hz under 0.05g of sinusoidal acceleration. Th e sensitivity was 560 mV/g. 0.05g 12 g/ Hz

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143 Figure 6-11. The output spectrum of z-ax is accelerometer at 200 Hz under 0.5g of sinusoidal acceleration. Th e sensitivity was 320 mV/g. Figure 6-12. The output spectrum of y-axis accelerometer at 200 Hz without acceleration input. The sensitivity tested was 260 mV/g. 0.5g Pk 110g/ Hz 11.9

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144 The minimum detectable acceleration can be readily derived once the noise floor and bandwidth of the device are determin ed, as expressed in Equation 6-2. min noiseaaBW (6.2) With a 1.5 kHz bandwidth, the minimum detect able accelerations in the lateral axis and z-axis are 0.46 mg and 4.26 mg, respectivel y. If the detectable range is limited by the circuit output swing of 1.65V, the maximum acceleration is about 3g. Thus, the theoretical dynamic ranges of the lateral and z-axis can be derived as 76.8 dB and 61.4 dB for a bandwidth of 1.5 kHz. With this noise performance, the 3-axis accelerometers developed in this thesis work can be readily used in physio logical monitoring, infrastructure monitoring in civil engineering and security monitoring. If narrower bandwidth is satisfactory, the devi ce can achieve higher resolution. It is also worthy to examine how sensitive th e designed accelerometer is if it is used for displacement detection. Take the lateral sensing element as an example. The lateral sensing element has a proof mass of approximately 86.2 g. With the simulated resonant frequency of 3.23 kHz, as in Section 4.3.2, the spring constant is derived as 35.5 N m from Equation 6.3. 2(2)rkmf (6.3) Then the minimum detectable displacement can be approximately estimated as Equation 6.4, which gives a value of 1.110-12 m. min minma x k (6.4)

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145 This means that the lateral sensing element can detect an extreme tiny displacement of 0.011 angstrom! With the sensing capacitanc e of 400 fF, from Equation 6.5, the sensor achieves a capacitance resolution of 1.7810-19 F. minmin 00 x C x C (6.5) With a modulation voltage of 1.5V, the minimum detectable charge will be 2.6810-19 Coulomb. This quantity is merely le ss than the charges of two electrons! The above explanation helps in und erstanding why capacitive sensing has extremely high sensitivity and is widely employed in the design of various sensors. 6.3.5. Dynamic Test The dynamic test of the 3-axis accelero meters was performed on a LDS shaker table. The tested items include waveform obser vation, linear response of the device to the swept sinusoidal input accel eration and the inter-axis coupling at 1g orthogonal acceleration. The accelerometer output was measured by a SRS-785 spectrum analyzer, Tektronics 2014 oscilloscope and/or multim eters. Two commercial accelerometers from Kistler, with full sensing range of 5 g and 50 g respectively, were used for reference. Before each test, the reference accelerometer was calibrated on-site by a Piezoelectronics 394C06 hand-held shaker, which generates 1g standard acceleration at frequency of 159.2 Hz. An aluminum mounting block was de signed to connect the mounting board in Figure 6-2 to the shaker. By mounting the te st board on different plane of the mounting block, the accelerometer can be characteri zed in different axis. Figure 6-13 is the photograph of the mounting block on which bot h a reference accelerometer and the test board with a 3-axis accelerometer are mounted for the x-axis test.

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146 Figure 6-13. Mounting method of the test boa rd and reference accelerometer on shaker table. 6.3.5.1 Waveforms A waveform is exemplified to show the typical dynamic output of the 3-axis accelerometer. Figure 6-14 shows a waveform of the z-axis response to 1g acceleration at 160 Hz. As a comparison, the waveform of a Kistler 8638B5 reference accelerometer is also included. Clean output waveforms were obtained from the test board. 6.3.5.2 Dynamic ranges The goal of the dynamic range test is to determine the upper limit of the linear response of the accelerometers. The dynamic range can be obtained once the highest acceleration and the minimum det ectable acceleration are known. It should be noted that the upper linear response of the device can ei ther be limited by the circuit or by the mechanical structures in the sensor. As described in Secti on 6.3.4, with power supply of 3.3V, the circuit has a swing limit of 1. 65V. With sensitivi ties of 560 mV/g and Test board with DUT Reference accelerometer Y-axis Mounting face Shaker X-axis Mounting face Z-axis Mounting face

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147 320 mV/g for lateral and z-axis the device has upper limit of detectable acceleration of about 3g and 5g. This does not mean that the m echanical structures of the sensor can not response to higher acceleration. In this experiment, by reducing the modulation signal, the sensitivity of the sensor is reduced to allow the sensing of hi gher acceleration. The upper detectable acceleration limit is determined when the total harmonic distortion reaches 5%. Figure 6-14. Output waveform of a z-axis accelerometer under 1g acceleration at 160 Hz. One grid in the lateral axis stands for 2.5 ms. Figure 6-15 shows the dynamic response of the accelerometer z-axis. The 50 Hz acceleration generated by shaker table was m easured by the reference accelerometer. Due to the stability of the test board mounting, the highest acceleration detected only reached to 34 g. The output still demonstrates an acceptable linearity of 2.1%, which indicates that the mechanical limit for the sensing should be at least 34 g. Reference (871mV/g) Z-axis output (320mV/g) mV 0 200 400 600 -200 -400 -600

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148 Figure 6-15. Dynamic response of z-ax is to 50 Hz sinusoidal acceleration. In a similar test, by reducing the sensitivity, the lateral axis achieved about 8 g of highest detectable acceleration, which is li mited by the amplifier saturation. From the above experiment, it is clear that with the de vice sensitivity in Sec tion 6.3.4, the upper detectable acceleration is limited by the circuit output swing. Normally 100 Hz bandwidth is used for the calculation of dynamic range. For the tested device with sensitiv ities of 560 mV/g and 320 mV/g for lateral and z-axis, the dynamic ranges are then 87.9 dB and 73.4 dB. 6.3.5.3 Inter-axis coupling Inter-axis coupling between two lateral axes was examined individually by observing the sensor output while a 1g orthogonal accelera tion was applied. This was carried out by monitoring the output of re ference accelerometer (with a sensitivity of 871 mV/g) and the sensor output simulta neously using the spectrum analyzer. 0 5 10 15 20 25 30 35 0 200 400 600 800 1000 1200 1400 Acceleration (g)Accelerometer output (mV)

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149 In Figure 6-16, Window A shows the spectrum of the sensor output in y-axis when 1 g acceleration of 160 Hz is applied to x-axis. The sensitivity in y-ax is was calibrated as 158 mV/g. Window B is the spectrum of the reference accelerometer showing the applied 1g acceleration in x-axis. The coupling from x-axis to y-axis can be readily calculated as 2.26%. The same measurement was conducted for the cross-talk from yto x-axis, resulting in a coupling of 2.38%. Figure 6-16. Spectrums obtained in the cros s-talk test. (a) shows the y-axis output responding to 1g acceleration from x-ax is; (b) is the spectrum of the reference accelerometer showing 1g accel eration at 160 Hz in the x-axis. As introduced in Section 6.3.3, in the sta tic test of z-axis re sponse, 1g acceleration from either lateral axis is coupled to z-ax is when the device is rotated about the other lateral axis. Therefore, the coupling of late ral axes to z-axis can be derived from Figure 6-8. They are 2.11% from x-axis and 4.73% from y-axis, respectively. 1 g (a) (b)

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150 The measured inter-axis coupling is summarized in Table 6-2. Table 6-2. Summary of the inter-axis coupling of the 3-axis accelerometer. x y z x 2.38% <0.35% y 2.26% <0.35% z 2.11% 4.73% 6.3.6. Stability and Temperature Performance 6.3.6.1. Offset drift Only offset stability in y-axis was observ ed to evaluate the device stability. The experiment was conducted at room temper ature for 48 hours. Figure 6-17 shows the recorded offset drift during the observation, indicating a la rge unidirectional drift of 54 mV. Figure 6-17. Y-axis offset drift observed in duration of 48 hours. 0 4 14 18 22 32 36 48 -60 -50 -40 -30 -20 -10 0 10 Time (hour)Sensor offset (mV)

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151 The reasons for the unidirectional drift incl ude the material rela xation in the sensor microstructures, circuit gain drift, power supply drift and en vironmental variations. Since the package of the device is non-hermetic, th e humidity in Florida could most likely be the main reason for the offset drift. To further identify the reasons for the offset drift, hermetic package and strict test environment ar e need, which is part of the future work on the accelerometers developed. 6.3.6.2. Temperature performance test A large overall temperature coefficient of sensitivity (TCS) in the lateral axis sensing element was observed. The accelerati on sensitivity experienced a 23% reduction when the device was heated from the room temperature (21C) to 96C, resulting in a TCS of 3.0710-3/C. Simulation of the temperature dependence of the interface circuit and temperature test on sensor structures we re performed independently to identify the source of the large TCS. In th e circuit simulation, a negative open-loop gain drift of over 10% was observed, which contributes most of the TCS reduction [137]. In addition to the examination of temperat ure drift of the circuit, the impact of temperature on the sensor microstructures was investigated separately. Due to the thermal expansion coefficient difference and the residua l stress, CMOS thin film structures curl up or down with temperature changes. As desc ribed in Chapter 3 and Chapter 5, the only thin film structures in the 3-axis acceleromet er are the electrical isolation beams in the lateral accelerometers, which conne ct the sensing comb fingers to the substrate or lateral proof mass, as shown in Figure 6-3(a). Thes e isolation beams have certain temperature coefficients. Once environmental temperature ch anges, the isolation beams will curl up or down, making the comb fingers that connect to the isolation beams change their positions

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152 in vertical direction. This will directly resu lt in the sensing capacitance change. This is one of the reasons that cause the temp erature sensitivity of the accelerometer. The comb finger curling caused by the temp erature variation was investigated by observing the vertical position change of th e comb fingers using a surface profilometer. The packaged device was heated to designated temperature points on an isolated stage. The profiles of the fingers were obtained by scanning the surface at these temperature points. Figure 6-18 shows the setup for this temperature experiment. Four sets of data were acquire d at four temperature points: 21C, 54C, 71C and 96C. Comb fingers from lateral-axes and zaxis sensing elements, including stator and rotor fingers and scanned. Figure 6-18 show th e surface profiles of lateral comb fingers on a working device, simultaneously obtained by using a Wyko NT-1000 surface profilometer when the device was heated to 71C. Figure 6-19(a) shows the curling of a rotor finger and Figure 6-19(b) gives the profile of a stator finger. Figure 6-18. Experimental setup for the comb drive curling calibration. Wyko object lens Thin-film heater Packaged accelerometer Heat sink Thermal insulator Spot thermometer

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153 Figure 6-20 shows the plots of curling displacements on lateral and z-axis comb fingers as the function of devi ce temperature. In total, 0.533 m and 0.065 m net curling was observed on lateral rotor and stator fingers, respectively. It is obvious that the rotor fingers have larger curling than the stator fingers. The reason for the difference can be explained as th e following. First, in design, the rotor and stator isolation thin films have different patt erns, as shown in Figur e 6-3(a), resulting in the different temperature dependence of the thin film bending. Second, there is possible large undercut at the end of the rotor co mb finger on the proof mass side during the device release. As described in Chapter 5, the undercut difference between the rotors and stators is due to the temperature rise on th e proof mass during the overetch in the release process. The temperature dependence of the comb finger curling causes the temperature dependence of the sensing capacitance, thus the TCS of the accelerometer. The comb finger curling changes the sensing capacita nce by changing the common area of the lateral sensing capacitors. By neglecting the temperature-cau sed curling of the stator finger, with the comb finger thickness of 37 m, as given early in this chapter, a positive temperature coefficient of sensing capacitance (TCC) of 9.7310-5/C can be derived. The following equations hold. 0 0() () ()(1)1s sCTCT T ST CTCTT (6.6) 2()(1) (1)dSTT dTT (6.7)

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154 Figure 6-19. Surface profiles of lateral sensi ng comb fingers. (a) rotor comb finger, (b) stator finger. The test temperature was 71C. (a) Surface profile of the la teral rotor comb finger. (b) Surface profile of the late ral stator comb finger. Proof mass Proof mass

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155 where S is the sensitivity of the accelerometer; Cs is the sensing capacitance; C0 is the sensing capacitance at room temperature; is the TCC of the sensing capacitance, 9.7310-5/C, as given above; and A is a normalized constant. The validation of Equation (6.7) is due to the very small quantity of in the given temperature range. Figure 6-20. Net curling displacements on la teral comb fingers as the function of temperature. From Equation (6.7), the TCS resulted from the sensing comb finger curling has a small value of -9.7310-5/C, which is two orders smaller than the simulated TCS that caused by the temperature-caused open-loop gain drift. Therefore, it can be concluded that the main reason for the large TCS is the large temperature dependence of the openloop gain in the first stage of the capacitive amplifier. Since no thin film structure exists in the z-sensing element, in the same experiment, no apparent temperature dependence of out -plane displacement was observed on the z20 30 40 50 60 70 80 90 100 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Temperature (degree C)Net curling displacement on the comb fingers (um) Lateral rotor finger Lateral stator finger

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156 axis rotor comb fingers. Therefore, the TCS of the z-axis acceleration is also mainly caused by the gain drift of the interface circuit. 6.3.7. 3-Axis Accelerometer Performance Summary The main performance of the fabricated 3-axis accelerometer is summarized in Table 6-3. The designed and tested paramete rs are listed, showing the good agreement between them. As a comparison, the corres ponding performance parameters of a mean stream commercial integrated 3-axis acce lerometer, ADXL330 from Analog Device, Inc, are also listed [139]. Table 6-3. Performance summary of the fabricated 3-axis accelerometer and a comparison between the this device and the ADXL330 from Analog Device. Parameter (Unit) Designed Value Tested Result ADXL330 Chip size (mmmm) 33 44 (with package) Power consumption (mW) 1.0 0.9~1.0 0.6 ~ 1.15 Lateral-axis mechanical sensitivity (mV/g) 4.5 3.54 Z-axis mechanical sensitivity (mV/g) 2.4 2.02 Lateral-axis overall sensitivity (mV/g) 450 560 270~330 Z-axis overall sensitivity (mV/g) 240 320 270~330 Lateral-axis noise floor (g/Hz) 7.97 12.0 280 Z-axis noise floor (g/Hz) 110.0 350 Linearity (%) 0.1 0.35 (lateral) 2.11~4.71 (z) 0.3 Bandwidth (kHz) 1.5 (lateral) 0.5 (z) 1.5 (lateral) 1.5(z) 1.6 (lateral) 0.6 (z) Dynamic range (dB) BW=100Hz 87.9(lateral) 73.4 (z) TCS (%/C) -0.307 0.01 TCO (mg/C) 7.03 1 Inter-axis coupling (% ) 2.26~2.38 (lateral) 2.11~4.71 (z) 1

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157 The designed and test value on sensitivity and noise floor in lateral axes have good agreement with each other. Except for th e temperature performance and inter-axis coupling, the 3-axis in this thesis work has higher sensitivity and resolution than the only monolithic integrated 3-axis MEMS accelerometer available on the market. The large temperature dependence of the fabricated CM OS-MEMS 3-axis accelerometer is mainly due to the high temperature sensitivity of th e open-loop gain in the first stage of the interface amplifier. 6.4 Test on The Single-Axis Accelerometer In addition to the above tests on the 3axis accelerometer, the single-axis accelerometer integrated on the same chip was tested using the same test setup and method. The quasi-static response and the noi se spectrum are shown in Figure 6-21 and Figure 6-22, respectively. Figure 6-21. Quasi-static response of the single-axi s accelerometer. The output instrumental amplifier (INA) on the test board has a gain of 2. -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -200 -150 -100 -50 0 50 100 150 200 Acceleration (g)Sensor output (mV)

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158 Figure 6-22. Measured noise density of th e single-axis accelerometer with a small acceleration input at 50 Hz. A gain of 2 was used in the output INA. The major parameters of device performa nce are listed in Table 6-4. The less sensitivity of the device is due to the larg er sensing capacitor gap caused by the backside release. Table 6-4. Performance summary of the single-axis accelerometer. Parameters Unit Designed Value Tested Value Sensitivity mV/g 210 90.1 Linearity % 0.22 Noise floor g/Hz 38.9 60.7 Linear range g 5 16 Dynamic range (BW=100Hz) dB 85.8 88.5 Power consumption mW 1 1

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159 6.5 Summary In this section, the experimental setups for the test of the fabricated 3-axis and single-axis accelerometers are introduced a nd the detailed test results of these two devices are presented. The main perform ance parameters of the devices have good agreement with the designed specifications. The monolithic integrated CMOS-MEMS 3axis accelerometer demonstrates small size, high sensitivity, high resolution and good linearity. It has advantages over the mainstream integrated MEMS 3-axis accelerometers in low noise floor, low power consumption a nd high sensitivity. These features make the 3-axis accelerometer developed in this work a highly desired device in the applications such as physiological/athletic monitoring, en gineering monitoring, security and portable electronics.

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160 CHAPTER 7 CONCLUSION AND FUTURE WORK 7.1 Summary and Conclusion A CMOS-MEMS microfabrication technology ha s been successfully demonstrated in this thesis work with the accomplishment of both monolithic integrated 3-axis and single-axis accelerometers. The silicon-DRIE based technological process developed in this work can be widely used in the fabr ication of sensors and actuators where comb drives are used for capacitive sensing or electrostatic actuation. The 3-axis and singleaxis CMOS-MEMS accelerometers fabricated using the developed technology have numerous applications in physical monito ring, engineering monitoring, and most significantly, in portable electronics where low-power and high resolution are required. Individual process steps in the fabrica tion technology were tu ned to achieve the optimal profile for the micro structures in the accelerometers. Process parameters were extracted as design rules for the design and fabrication of these a nd other MEMS devices. In the fabrication of CMOS-MEMS accelerom eters, by performing the dry etch of electrical isolation structur es and the etch-through step for other sensor structures separately, the undercut on comb drives and mechanical springs is minimized, allowing large capacitance for sensing and actuating. Th is is achieved by using the top metal layer on the device to define the isolation etch holes. Two device release processes were demonstrated to overcome the inter-process contamination and the over-heating problem to the suspended single-crystal silicon micro structures. In the first release method, the el ectrical isolation trench es are etched to a

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161 tapered shape from the backside right before the final structure rel ease step. This allows the removal of the contaminants on the sidewall of the isolation trenches for the complete device release. In the other method, a thick photo resist layer is applied to the backside of the structure right after the backside s ilicon etch. This photor esist layer provides additional thermal paths, allowing the heat generated on the micro structures in the plasma etch transferring to the substrate. The over-heat of the micr o structures in the overetch period of the device release step is largely reduced; and the device structure damage resulted from the uncontrollable rapid u ndercut at high temperature is eliminated. The CMOS-MEMS 3-axis accelerometer a nd single-axis accelerometer developed in this work have features of small size, r obust structure with singlecrystal silicon, high sensitivity and resolution. In the 3-axis acc elerometer, the z-sensing element is embedded in the lateral proof mass. Th is greatly reduces the overall sensor size. 560 mV/g and 320 mV/g sensitivities are achiev ed for lateral and z-axis axes, with noise floors of 12 g/Hz and 110 g/Hz, respectively. For a bandwidth of 100 Hz, dynamic ranges for lateral and z-axis are 87.9 dB and 73.4 dB. The single-ax is accelerometer achieves a sensitivity of 90.1 mV/g with noise floor of 60.7 g/Hz. The non-linearity in all lateral axes is less than 0.35%. A slightly large non-linearity ha s been observed due to the inevitable interaxis coupling in the z-axis response. The in terface circuit in each axis consumes 1 mW power. Most of the test results demons trate good agreement with the designed specifications. With these performances and a die size of 3 mm3 mm, the CMOSMEMS accelerometers in this work can be widely used in portable electronics and wireless applications for hu man activity monitoring, engineering monitoring and public

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162 security. An evaluation prototype is under te st by a commercial company for security applications. 7.2 Future Work The future work of this project involv es the sensor improvement and process development for large volume fabrication. The sensor improvement includes the circuit improvement, integration of advanced functi on blocks and mechanical structure design optimization. The current interface circuit has a draw back of large temperature dependence due to the different types of th e input transistors in the first stage of amplifier. The modification of the input stag e should be the first task to improve the temperature performance of the sensors. A new circuit has been proposed by the circuit designer [137]. For high performance standal one wireless applica tions of inertial measurement unit (IMU), analog-digital conver ter (ADC), control and wireless blocks should be integrated on the chip. The mechan ical structure design optimization includes mechanical spring optimizati on to reduce the inter-axis c oupling; creation of precise analytical models for the prediction of device performance in all three axes. No device optimization can be realized wit hout a proper fabrication process. In the current CMOS-MEMS process used for accelerom eter fabrication in this project, the separation of etch steps for isolation trench and device release causes the contamination and the overheating problem, which both hi nder the devices from being successfully released. Other materials with better electrical and ther mal conductivity than photoresist should be investigated for use as the thermal path on the backside in the device release. The isolation trench should be refilled with insulating materials for really robust sensor structures.

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163 In commercialization of any devices, cost is a dominant desi gn constraint. Based on the CMOS-MEMS DRIE process in this work, two wafer-level microfabrication processes are proposed as the future work fo r volume fabrication of the accelerometers. The process flows are presented in Appendi x C with brief descriptions. The main challenges in wafer-level plasma etch pro cesses for MEMS devices include the loading effect caused nonuniformity in etch; wafer handling in process transfer; and device separation after the processes. Wafer-level vacuum package for high performance devices is even more challenging. It requires some additional particular processes such as wafer bonding, through-wafer interconnect and doubleside precise alignment. Some steps should be finished in vacuum with remote handling. For successful device development, these issues must be solved in the future.

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164 APPENDIX A LAYOUTS OF TEST STRUCTURES FO R PROCESS CHARACTERIZATION The layouts of some on-chip test structur es are given in this appendix section. Other individual test stru ctures are not included.

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165 Figure A-1. Layouts of on-chip test structures. (a) ARDE te st structure #1, (b) etching rate test structure, (c) ARDE test stru cture #2, (d) comb fingers with different patterns, (e) UFECE logo. M3 M4 M1 M2 (a) (c) (e) (b) (d)

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166 APPENDIX B PIN-OUT OF ACCELEOMETERS AND BONDING PAD CONFIGURATION For convenience of test, the wire bon ding configuration for the 3-axis accelerometer is fixed. The die pin-out is gi ven in Figure B-1 with the label of PLCC-52 pin numbers. PCB test boards were ma de based on this configuration. Figure B-1. Pad configur ation and PLCC pin-out vdrvp_3y Gnd_A Tst_in1 Tst_in2 vcm_out von2_3z vop2_3z voutp_3z voutn_3z VDD_A selftest vop1_3zvon1_3z voutp_3x voutn_3x vop2_3x von2_3x von1_3x Gnd_Avop1_3xvcmin3x Iin_3x sen_os2 sen_os1 von1_3y vop1_3y VDD_A Iin_3y von2_3y vop2_3yvoutp_3y voutn_3y voutp_1x vcmin3yvoutn_1x vop2_1x von2_1x Iin_1x vcmin1x vop1_1x von1_1x vdrvn_3y vdrvn_3x vdrvp_3x vdrvp_1x vdrvn_1x vdrv _comm vdrv_3z Gnd_a Clk_in Gnd_d Clk_out VDD_D VDD_M gnd_M sel1 sel0 vrefn vrefp vop2_tst von2_tst Iin_tst Iin_3z vcmin3z von1_tstvop1_tstvcmintstvoutn_tstvoutp_tst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 41 40 39 38 37 36 35 34 33 44 43 42 46 45 47 48 49 50 51 52vdrvp_3y Gnd_A Tst_in1 Tst_in2 vcm_out von2_3z vop2_3z voutp_3z voutn_3z VDD_A selftest vop1_3zvon1_3z voutp_3x voutn_3x vop2_3x von2_3x von1_3x Gnd_Avop1_3xvcmin3x Iin_3x sen_os2 sen_os1 von1_3y vop1_3y VDD_A Iin_3y von2_3y vop2_3yvoutp_3y voutn_3y voutp_1x vcmin3yvoutn_1x vop2_1x von2_1x Iin_1x vcmin1x vop1_1x von1_1x vdrvn_3y vdrvn_3x vdrvp_3x vdrvp_1x vdrvn_1x vdrv _comm vdrv_3z Gnd_a Clk_in Gnd_d Clk_out VDD_D VDD_M gnd_M sel1 sel0 vrefn vrefp vop2_tst von2_tst Iin_tst Iin_3z vcmin3z von1_tstvop1_tstvcmintstvoutn_tstvoutp_tst vdrvp_3y Gnd_A Tst_in1 Tst_in2 vcm_out von2_3z vop2_3z voutp_3z voutn_3z VDD_A selftest vop1_3zvon1_3z voutp_3x voutn_3x vop2_3x von2_3x von1_3x Gnd_Avop1_3xvcmin3x Iin_3x sen_os2 sen_os1 von1_3y vop1_3y VDD_A Iin_3y von2_3y vop2_3yvoutp_3y voutn_3y voutp_1x vcmin3yvoutn_1x vop2_1x von2_1x Iin_1x vcmin1x vop1_1x von1_1x vdrvn_3y vdrvn_3x vdrvp_3x vdrvp_1x vdrvn_1x vdrv _comm vdrv_3z Gnd_a Clk_in Gnd_d Clk_out VDD_D VDD_M gnd_M sel1 sel0 vrefn vrefp vop2_tst von2_tst Iin_tst Iin_3z vcmin3z von1_tstvop1_tstvcmintstvoutn_tstvoutp_tst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 41 40 39 38 37 36 35 34 33 44 43 42 46 45 47 48 49 50 51 52 3-axis IMU Singleaxis IMU 3-axis Accelerometer Single-axis Accelerometer

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167 APPENDIX C PROPOSED WAFER-LEVEL FA BRICATRION PROCESSES Wafer Level Process I In this process, the isolation trenches are formed completely from the backside etch. Two masks are needed. One is used to pattern the isolati on trenches and device separation trenches. The other is to patte rn the MEMS structure region. The backside is first deposited with SiO2 using low-temperature PECVD. The SiO2 layer is patterned to define the MEMS st ructure region and devi ce separation lines, as shown in Figure C-1(a). Then another photoresist layer is patterned to define the isolation trenches, see Figure C-1(b). In this step, doubl e side alignment is need. Next, DRIE is performed to etch isolation trenches and se paration trenches to certain depth, Figure C1(c) before photoresist is removed to expose the SiO2 patterns that define the MEMS structure regions, as in Figure C-1(d). The last DRIE step continues the etch in isolation and separation trenches until the etch front reaches the first SiO2 layer on front side. In the meantime, the newly opened area is etched to define the structure thickness, as shown in Figure C-1(e). Finally, the wafer will be f lipped over to perform the front side etch. Only one step of SiO2 is needed before the final DRIE from front side to release the device. It can be predicted that the profile of th e isolation trenches will be tapered to the shape as shown in Figure C-1( e). As described in Chapter 5, this helps the complete release of the MEMS structures.

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168 Figure C-1. Proposed wafer-level proce ss flow for backside etch steps. (a) (b) (c) (d) (e) (a) SiO2 growth and pattern to define the MEMS structure region and device separation trenches (b) Photoresist coat and pattern to define the isolation and separation trenches. (c) DRIE of isolation and separation trenches. (d) Photoresist removal to open the previous patterns in SiO2. (e) 2n d DRIE to etch the isolation trenches to the SiO2 layer on front side. CMOS region Si SiO2 Photoresist Substrate CMOS stack

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169 In this proposed process, we can take a dvantage of microloading effect to get an optimal timing ratio of the two DRIE steps to balance the isolation trench profile and the device thickness. Another merit of this proc ess involves the comb drive design. Since no undercut etch from the front si de is required, the comb dr ive fingers have no limit in shape at the connecting ends. Wider and robust comb drives with normal shape can be employed to realize the ove rall device robustness. Wafer Level Process II As described in Chapter 5, the isolat ion trench sidewalls are prone to be contaminated with etch byproduct and part icles milled from sample surface. This complicates the device release due to the micro mask effect of the contaminants. Additionally, the existence of the thin film isolation beams makes the sensor structures less robust and more temperatur e dependent. For the above reason, it is highly desired to replace the isolation trenches with other soli d structures that stil l have the function of electrical isolation. Another wafer-level fabrication process is proposed as the following. It employs a trench-refilling technique in which SiO2 and poly silicon-germanium (Poly SiGe) low temperature deposition and CMP are involved. PECVD SiO2 and LPCVD poly SiGe can all be deposited at a temperature below 425C, which is proven safe to CMOS circuits [140]. Since the CMOS circuits are completely protected by metal layers, CMP should not affect the electrical performance of the circuits. To ease the trench etch, the CMOS fabricat ed wafers will be thinned approximately to 100 m. This thickness is constrained by the achievable aspect ratio for isolation trench etch, and more practically, the wafer thickness limit for safe handling. Double-side alignment is needed to define the isolation trench, followed by DRIE trench etch, as

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170 shown in Figure C-2(a). Low-temperature PECVD (~350C substrate temperature) is performed to deposit a 1~2 m SiO2 layer on trench bottom and sidewalls for isolation. LPCVD poly SiGe deposition at about 425C follows to refill the trench partially, see Figure C-2(b). RIE or surface polish is followed to remove the SiO2 and polysilicon on the surface, as shown in Figure C-2(c). In the meanwhile, a separate silicon bare wafer (substrate wafer) is prepared for lo w-temperature Si-Si wafer bonding. 1~2 m SiO2 layer is deposited and patterne d followed by silicon DRIE for cavity etch in the substrate wafer. Then, after alignment, the CMOS wa fer and substrate wafe r are bonded together, see Figure C-2(d). Before front side etch process on CMOS wafer, the bonded wafers are attached to another carrier wafer and diced into device elements, as in Figure C-2(e). Finally, anisotropic SiO2 etch and silicon DRIE finish the MEMS sensor release, which is followed by the chip separation by photor esist ashing, as in Figure C-2(f). It should be noted that between the carri er wafer and substrate wafer in Figure C2(e), a reliable adhesion should be form ed for physical attachment and thermal conduction. The sensor elements should also be easily removed from the carrier wafer after the final process. Photor esist can be used as this a dhesion layer. After the device release, it can be ashed away to allow th e separation of sensor element from carrier wafer.

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171 Figure C-2. Wafer level process with isol ation trench refilling and wafer-bonding. Si CMOS layer Poly SiGe SiO2 Prepared Substrate with cavity SiO2 Dicing trench PR Car rierwafer (a) CMP of foundry fabricated CMOS wafer. (b) Isolation trench DRIE followed by lowtemperature PECVD of SiO2 and LPCVD of Poly SiGe for trench refilling. (c) Backside planarization. (d) Low temperature wafer bonding. (e) Wafer transfer followed by chip dicing. (f) Front side etch for device release and chip separation. (a) (b) (c) (d) (e) (f)

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184 BIOGRAPHICAL SKETCH Hongwei Qu received his B.S. and M.S. de gree in electrical e ngineering both from Tianjin University, Tianjin, China, in 1988 and 1993 respectively. From 1993 to 2000, he was a faculty member at the Electrical Engineering Depart ment of Tianjin University, where he was involved in research on semic onductor sensors. Mr. Qu is now pursuing the PhD degree at the Department of Electrical and Computer Engineering of the University of Florida. Before he moved to the University of Florida, he had also obtained a M.S. degree in physics from Florida International University in 2002, with thesis research on ferroelectric thin films. His current research involves CMOS ME MS technology, focusing on the integrated CMOS inertial measurement units. Mr. Qu is also interested in electrostatic micromirror, pressure sensor, magnetic sensor s and other solid state devices.


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DEVELOPMENT OF DRIE CMOS-MEMS PROCESS AND INTEGRATED
ACCELEROMETERS
















By

HONGWEI QU


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


2006

































Copyright 2006

by

Hongwei Qu
































This thesis is dedicated to my wife Chen Chen, and my daughters Wendy and Angela.















ACKNOWLEDGMENTS

I would like first to thank my advisor, Dr. Huikai Xie, for his continuous

encouragement, expert advice, guidance and support of my thesis research. His profound

knowledge and expertise in MEMS and other engineering fields are sources I can always

rely on.

I would like also to express my appreciation to my Ph.D. committee members, Dr.

Toshikazu Nishida, Dr. David Arnold and Dr. Mark Davidson, for their advice,

suggestion and time on my research and thesis. I am grateful to Dr. Arnold for his

comments and corrections of my thesis manuscript. I am also benefited from the

discussions with Dr. Mark Sheplak on fabrication process and characterization of the

accelerometers developed in this thesis work.

I would like to acknowledge Drs. David Johnson and Chris Constantine at Unaxis

in St. Petersburg for beneficial discussions on the plasma etch of thick SiO2; Dr. Rauf

Shahid at Freescale for help on physical models in plasma etch.

I appreciate the helps from my group members at the Biophotonics and

Microsystems Lab (BML). My special thanks go to my project mate, Dr. Deyou Fang, for

his excellent circuit design and help in device tests. The days and nights we spent

together in the labs are just memorable. I enjoy my time with Dr. Ankur Jain and Shane

Todd at BML. Dr. Jain's advices on my device fabrication are valuable. He is also an

export on optical instruments and is always a reliable support to all BML members.

Shane's work on the modeling of optical MEMS devices helps me in a better









understanding of these devices. Mingliang Wang, Lei Wu, Kemiao Jia and Xiaoxing

Feng offer me many helps in device fabrication and characterization.

My thanks also go to the fellow members at the Interdisciplinary Microsystems

Group (IMG) of the University of Florida. I benefited from the good research

environment in IMG and helps from many IMG members including, but not limited to,

Jian Liu, Anurag Kasyap, Stephen Horowitz, Robert Dieme, Yawei Li, David Martin,

Benjamin Griffin and Chris Bohr.

The fabrication of the devices was mostly carried out at the University of Florida

Nano Fabrication facilities (UFNF). Thanks go to Al Ogdan, Bill Lewis and Dr. Ivan

Kravchenko at UFNF for the maintenance of the facility and support in the fabrication.

I also thank Shannon Chillingworth, the departmental graduate coordinator, for her

outstanding work in my graduate study. Thanks go to Joyce White and Kathy Thomson

for their support in my research.

Finally, I am grateful to my family and friends for their constant support and

encouragement. I am indebted to my wife Chen Chen for her endless love and support.

Without her support, this thesis work is impossible. My love to my daughters, Wendy and

Angela, is the propellant in achieving this thesis research. I owe my parents and parents-

in-law for their endless love and support for my study in USA. I am in debt to my sister,

Hongpei Qu, who takes care of my parents when I study abroad. I would like to thank my

friends James Zhang, Jiandi Zhang, Michael Liu and their families for their friendship

and help. I want also thank Vicky Liu and Huanyu Yue for their valuable advices on my

Ph.D. study.









This research work was partially supported by NASA UF/UCF Space Research

Initiative and the device fabrication was supported by MOSIS through its Educational

Program.
















TABLE OF CONTENTS



A C K N O W L E D G M E N T S ................................................................................................. iv

LIST OF TABLES ............................................................................. x

LIST OF FIGURES ......... ......................... ...... ........ ............ xi

ABSTRACT .............. .......................................... xvi

CHAPTER

1 IN TR OD U CTION ............................................... .. ......................... ..

1.1 CM O S-M EM S Technology ..................................... ........................ .. .......... 2
1.1.1 Pre- and Inter-CMOS MEMS Technology ............................................2
1.1.2 Post-CMOS MEMS Technologies...........................................4
1.1.2.1 Additional MEMS structures on CMOS substrate..............................4
1.1.2.2 Formation of MEMS in CMOS substrate................. ...............6
1.2 M EM S Accelerom eters................................... .. ...... ...................... 10
1.2.1 Sensing Mechanisms of MEMS Accelerometers .............................12
1.2.2 Capacitive MEMS Accelerometers....................... ............... 13
1.3 3-Axis CMOS-MEMS Accelerometers.........................................................17
1.4 Thesis Goals and Organization .............................................. .................. 20

2 DRY POST-CMOS MICROFABRICATION AND TOOLS.............. .....................22

2 .1 P la sm a E tch ................................................................................................ 2 2
2.2 Characterization M ethodology..................................... ......... ............... 30
2 .3 S iO 2 E tc h ............... ... .. ....... ......... ...... .......................... ............... 3 2
2.2.1 Challenges in Anisotropic Si02 RIE..................... ........................... 32
2.2.2 System Characterization ............................................. ............... 34
2 .2 .2 .1 E thing rate ........................................................ ....................35
2.2.2.2 Top m etal layer m killing .............................................................36
2.2.2.3 Sidewall profile of the Si02 layers and CMOS stacks..................38
2.2.2.4 The inhibitor polymer redeposition on the sidewall...................39
2.4 Advanced Silicon Etch by STS ICP DRIE ............................................... 43
2.3.1 ICP Silicon DRIE System Configuration ...........................................44
2.3.2 Silicon A nisotropic Etch .............................................. .................. 45
2.3.3 Silicon DRIE Characterization ................................... ............... ..48









2.3.3.1 Etch rate and profile tuning.........................................................49
2.3.3.2 Microloading and ARDE effect ......................................... 53
2.5 Sum m ary ..................................................................... .......... 57

3 IMPROVED DRIE POST-CMOS MEMS TECHNOLOGY.............................. 59

3.1 Dry Post-CM O S M EM S: Background ........................................ .................60
3.1.1 Thin-film Post-CMOS MEMS Technology .......................................60
3.1.2 DRIE Post-CMOS MEMS Technology.................. ....... .........63
3.1.2.1 Example device I: electrothermal micromirror ...........................66
3.1.2.2 Example device II: single axis accelerometer .............................68
3.2 Improved DRIE post-CMOS MEMS Technology ............... .................70
3.3 Sum m ary ..................................................................... .......... 73

4 DESIGN OF THE INTEGRATED ACCELEROMETERS ............... ................. 74

4.1 Applications of the Designed Devices ........ .. ....... ....... .....................74
4.2 Single-axis Lateral Accelerometer...... .................. .............76
4 .1.1 D evice D esign ........................................... .. .. ..... ... .. .......... ........... 76
4.1.2 Device Simulation Using Finite Elements Method ............................80
4 .3 T ri-axial A ccelerom eter ......................................................... .....................82
4.2.1 Z -axis Sensing............... ....... .... .............. ................ ............. 85
4.2.2 Analysis of the Cross-axis Coupling................... ................................92
4.4 Sum m ary ................................................................... ........... 96

5 SOME ISSUES IN THE DEVICE FABRICATION ...........................................98

5.1 Top A lum inum Layer R em oval ............................................ .....................98
5.2 Dry Etch Caused Device Contamination................................................... 102
5.2.1 The Sources of Contamination ............ ............................. ........ 103
5.2.1.1 Front surface contam inants ............................... ............... .105
5.2.1.2 Isolation trench sidewall contamination..........................107
5.2.1.3 Back surface contamination .................. ....................................109
5.2.2 Solutions to the Device Release with Contamination..........................110
5.2.2.1 Surface debris prevention................................................ 111
5.2.2.2 Sidew all contam nation control...................................................111
5.2.2.3 Backside surface contaminant removal................................... 114
5.3 Therm al Effect in the Device Release ................................... ... ..................114
5.3.1 Mechanism of the Undercut Caused by Thermal Effect......................115
5.3.2 Fabrication Method for the Suspended MEMS Devices ...................122
5 .4 S u m m a ry .................................................................................................. 12 7

6 DEVICE CHARACTERIZATION ....................................................................... 128

6.1 D vice Package .............................................. .... .... ... ........ .... 128
6.2 Test Setups ................................. ........................... .... ........ 130
6.3 3-Axis Accelerom eter Test Results .................................... ............... 130
6.3.1. M echanical Test Results ........... ............................... ............... 132









6.3.2. On-Chip Circuit Test.................................................. ............... 136
6.3.3. Q uasi-Static R response ........................................ ...... ............... 137
6.3.4. N oise M easurem ent ........................................ ......... ............... 139
6.3.5. Dynamic Test .................. ...................... .. ..........................145
6.3.5.1 W aveform s .............................. ......... .. .... .......... ....146
6.3.5.2 D ynam ic ranges ........... ....................................... ............... 146
6.3.5.3 Inter-axis coupling.................................... ........ ............... 148
6.3.6. Stability and Temperature Performance ........................................... 150
6 .3 .6 .1. O ffset drift ........................................................ ....... ... ... ... .. 150
6.3.6.2. Tem perature perform ance test ............................ .................... 151
6.3.7. 3-Axis Accelerometer Performance Summary ...................................156
6.4 Test on The Single-Axis Accelerom eter............................. .....................157
6.5 Summary ..................................................................... ................................. 159

7 CONCLUSION AND FUTURE WORK ................... ......... .................160

7.1 Sum m ary and C conclusion ......... .......................................... ............... 160
7.2 Future W ork .............................. .................... ... ...... .............. 162

APPENDIX

A LAYOUTS OF TEST STRUCTURES FOR PROCESS
CH A R A CTER IZA TION ......... .................. .................................... ............... 164

B PIN-OUT OF ACCELEOMETERS AND BONDING PAD
C O N F IG U R A T IO N ........................................................................ ...................166

C PROPOSED WAFER-LEVEL FABRICATRION PROCESSES ...........................167

W after L ev el P ro cess I.................................................................... .................... 16 7
W after Level Process II ........................................................................ .. 169

L IST O F R E FE R E N C E S ....................................................................... .................... 172

BIOGRAPHICAL SKETCH ............................................................. ............... 184
















LIST OF TABLES


Table page

1-1 Summary of previous work on bulk micromachined capacitive accelerometers .....15

2-1 Comparison of plasma etch in IC and M EM S ............................... ............... .23

2-2 Influences of etching parameters on RIE etch results....................... ...........34

2-3 Anisotropic SiO2 etch recipe on the PlasmaTherm SLR770 ECR RIE system .......42

2-4 Input parameters in the silicon ASE on STS ICP DRIE system ...........................48

2-5 CMOS-MEMS accelerometer design rules extracted from the experimental
re su lts ............................................................................ 5 8

3-1 Dimensions of the microstructures in the test accelerometer...............................68

4.1 The major specifications of the designed single and 3-axis accelerometers............76

4-2 Dim tensions of the lateral accelerom eter .................................... ......... ............... 80

4-3 Predicted performance of the designed single axis accelerometer ...........................82

4-4 Structural dimensions of the designed 3-axis accelerometer. ................................85

4-5 Predicted performance of the designed 3-axis accelerometer..............................92

5-1 Dimensions of the z element and the parameters used in the analysis.................19

6.1 Instruments and setups for the characterization of fabricated accelerometers .......132

6-2 Summary of the inter-axis coupling of the 3-axis accelerometer...........................150

6-3 Performance summary of the fabricated 3-axis accelerometer and a comparison
between the this device and the ADXL330 from Analog Device..........................156

6-4 Performance summary of the single-axis accelerometer ............ ................158
















LIST OF FIGURES


Figure page

1-1 A lateral accelerometer fabricated using the thin film CMOS-MEMS
tech n o lo g y ........ ........................................... .......................................... 8

1-2 SEM images of some sensing comb fingers in an integrated accelerometer
fabricated using the previous DRIE CMOS-MEMS process...................................9

1-3 Typical applications and performance requirements of accelerometers ................11

1-4 Achievable device performance versus device size with different technological
approaches shows the advantage of the DRIE CMOS-MEMS technology ............16

2-1 Seven steps of the etch process in RIE................................. ..............24

2-2 Four basic etch m mechanism s ..................... ......... ........................... ............... 25

2-3 Configurations of ECR and ICP system ...................................... ....................... 29

2-4 System response of the input parameters in a Si02 RIE system. ...........................34

2-5 Si02 etch rate as functions of system parameters........................................35

2-6 Impact of the SiO2 etch on the top Al layer. ............. ........................................... 37

2-7 Profiles of the CMOS stack at different process stages. ..........................................38

2-8 Inhibitor polym er form ation in SiO2 etch........................................................... 40

2-9 SiO2 etching rate as the function of oxygen concentration in the CHF3/02 gas
m ix ............... ........................... ............................................... 4 1

2-10 Inhibitor polymer formation as the function of oxygen concentration in the
CHF3/02 mixture. ................................. ..... ......... ..............42

2-11 Configuration of the STS ICP ASE system. ................................. ..................... 45

2-12 Alternate etching and passivation in Bosch process. .............................................46

2-13 Scallops formed on the sidewall of the etched structures showing the alternate
etching and passivation cycles in Bosch process. .................................................47









2-14 Etch rate per cycle using the recipe in Table 2-4 with varying etch duration..........49

2-15 Smooth sidewall in Si DRIE achieved with a lower etch rate...............................50

2-16 The tuning of etch profile by changing the etch/passivation ratio.........................51

2-17 Sidewall profiles of the comb fingers. ........................................ ............... 52

2-18 ARDE effect and its influence on the trench profile and etching rate. ..................55

2-19 Etching profile of the sensing comb fingers...................................... .............57

3-1 Cross-sectional view of the thin-film CMOS-MEMS process.............................62

3-2 Cross-sectional view of the process flow of DRIE post-CMOS MEMS
techn ology ........................................................ ................. 6 5

3-3 LVD electrothermal micromirror fabricated using DRIE post-CMOS MEMS
technology. The inset shows the undercut on the mirror plate and actuation
frame, which is caused by the undercut of bimorphs ..................... .............. 67

3-4 Fabricated lateral accelerometer using previous DRIE CMOS MEMS process......69

3-5 The improved process flow of new DRIE post CMOS MEMS technology............72

4-1 Lumped model and equivalent electrical circuit of the single axis capacitive
accelerom eter. ................................................................... ....................... .... .......77

4-2 Fully differential configuration of the lateral accelerometer...............................78

4-3 Schematic 3D model and mechanical spring configuration of the single-axis
accelerom eter. ................................................................... ....................... .... .......79

4-4 Schematic 3D model of the 3-axis accelerometer and layout of devices
designed....................................................... ................... .... ... ... .... 84

4-5 Differential connection of the sidewall capacitors in z-axis sensing element..........88

4-6 Capacitance change in the range of -50g to +50g in z direction shows a good
lin earity ................ ..................................... ........................... 9 0

4-7 Z capacitance coupling from the lateral motion....................................... .......... 95

4-8 The relation between capacitance change and the number of volume elements in
mesh shows a convergent trend, indicating the reliability of the simulation. .........96

5-1 A cluster of the residual byproduct formed in the aluminum plasma etch using
C 12/A r chem icals. .......................... ...... .................................... .. ..... 99









5-2 The mechanism and result of the sidewall protection in the aluminum wet etch. .101

5-3 Formation of the Al sidewall protection spacers on the isolation beams.............102

5-4 SEM photographs of the etched-through comb fingers. The narrow connections
along the ends of the comb fingers are caused by the micromasking effect of the
contaminant on the sidewall of isolation trenches. .............................................. 104

5-5 Schematic of the contamination in the plasma etch. ..............................................104

5-6 Front side surface contamination caused by the physical process in the plasma
etc h ................................ ............................................................ 1 0 6

5-7 Structure connection caused by the debris on the front surface generated in the
plasm a etch. ..........................................................................106

5-8 SEM image and EDS spectrum of part of an isolation trench and peripheral
structures. ..........................................................................108

5-9 SEM image and schematic profile of an isolation trench sidewall with rough
surface. ............................................................................ 109

5-10 Fabrication method using additional etch on backside. ........... ...............113

5-11 Undercut caused by the overheating of the structure.. ..................... ..............116

5-12 Model of the z sensing element for temperature rise estimation........................... 119

5-13 Calculated temperature rise on z proof mass. ................................................ 120

5-14 Lateral undercut on the rotor sensing finger of z element. The back surface of
the z block is also deteriorated due the higher temperature on the block. .............122

5-15 Modified accelerometer fabrication process with photoresist coating on
backside............................................................................................. 124

5-16 Etched-through structures observed through photoresist coated on the backside
of the device. ...................................................................... 12 5

5-17 Fabricated device with most structures released. The structure damage caused by
the thermal effect is avoided by coating photoresist on the backside of the
d ev ice .......................................................................... 12 6

6-1 Photographs of the packaged device. ..................................................................... 129

6-2 3-axis accelerometer test PCB board. ....................................... ............... 129

6-3 Sensing comb fingers on a 3-axis accelerometer. .............................................131









6-4 Block diagram of the Scanning Laser Doppler Vibrometer setup for z-axis
resonant frequency test ........................................................................... .... ..... 134

6-5 The scanning area on the z-axis proof mass and the frequency response of the
m otion in the scanned area. ............................................. ............................ 135

6-6 The detected acceleration versus driving frequency around the z-axis
accelerometer resonant frequency. ........................................ ....... ............... 136

6-7 Q uasi-static test setup ..................................... ....... ... .... ..... .. .......... 138

6-8 Responses of the 3-axis accelerometer to +lg acceleration.............................. 139

6-9 Electronic noise density of y-axis interface circuit which has an overall gain of
4 4 .5 dB ......................................................................... 14 1

6-10 The output spectrum of y-axis accelerometer at 200 Hz under 0.05g of
sinusoidal acceleration. The sensitivity was 560 mV/g. ........................................142

6-11 The output spectrum of z-axis accelerometer at 200 Hz under 0.5g of sinusoidal
acceleration. The sensitivity was 320 m V/g...................................... ..................143

6-12 The output spectrum of y-axis accelerometer at 200 Hz without acceleration
input. The sensitivity tested was 260 mV/g. .................................. ............... 143

6-13 Mounting method of the test board and reference accelerometer on shaker table. 146

6-14 Output waveform of a z-axis accelerometer under Ig acceleration at 160 Hz.
One grid in the lateral axis stands for 2.5 ms. .................. ....................... 147

6-15 Dynamic response of z-axis to 50 Hz sinusoidal acceleration............................148

6-16 Spectrums obtained in the cross-talk test. ................................... ............... 149

6-17 Y-axis offset drift observed in duration of 48 hours............ ........ ............... 150

6-18 Experimental setup for the comb drive curling calibration..................................152

6-19 Surface profiles of lateral sensing comb fingers. ................................................154

6-20 Net curling displacements on lateral comb fingers as the function of
tem perature........... ....................................................................... 155

6-21 Quasi-static response of the single-axis accelerometer. The output instrumental
amplifier on the test board has a gain of 2. ..................................... ...............157

6-22 Measured noise density of the single-axis accelerometer with a small
acceleration input at 50 Hz. A gain of 2 was used in the output INA.................... 158









A- Layouts of on-chip test structures. .............................................. ............... 165

B-1 Pad configuration and PLCC pin-out ............................................ ...............166

C-l Proposed wafer-level process flow for backside etch steps .................................168

C-2 Wafer level process with isolation trench refilling and wafer-bonding ...............171















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

DEVELOPMENT OF DRIE CMOS-MEMS PROCESS AND INTEGRATED
ACCELEROMETERS

By

Hongwei Qu

August 2006

Chair: Huikai Xie
Major Department: Electrical and Computer Engineering

Plasma etch based CMOS MEMS technologies have the advantage of monolithic

integration of sensors and conditioning electronics, which yields small size, low noise

and low cost of the devices. In this thesis work, a new deep reactive-ion-etch (DRIE)

based post-CMOS MEMS microfabrication technology was developed, and single-axis

and 3-axis integrated accelerometers were fabricated using the new microfabrication

technology. Compared to the previous CMOS-MEMS technological approaches, the new

microfabrication technology features the capability of monolithic integration for high

performance MEMS sensors. The integrated accelerometers demonstrate small size, high

sensitivity and high resolution with low power consumption. They can be used in a large

spectrum of applications including human activity monitoring, engineering measurement,

security, and portable electronics.

Detailed post-CMOS microfabrication processes are presented. Reactive-ion-etch

(RIE) and DRIE tools and processes are tuned to satisfy the technological requirements









of the device fabrication. Some general design rules are extracted based on the systematic

characterization of the etching tools. Special techniques were developed for aluminum

wet etch and electrical isolation etch. The thermal issues in the device fabrication were

identified and an alternate fabrication process was developed to avoid the device damage

due to the overheat in the plasma processes. Wafer-level fabrication processes are also

proposed.

Detailed design of 3-axis and single-axis accelerometers is presented. Device

performance is predicted based on the calculations and finite-element analysis (FEA)

using Coventor, a commercial FEA tool. The Taiwan Semiconductor Manufacturing

Company (TSMC) 0.35 |tm technology is used for the CMOS fabrication.

With power consumption of 1 mW in each axis, the fabricated 3-axis accelerometer

achieves sensitivities of 560 mV/g and 320 mV/g in the lateral and z axes, with noise

floors of 12 [tg/'/Hz and 110 [tg//Hz, respectively. The single-axis accelerometer

achieves a sensitivity of 90.1 mV/g with a noise floor of 60.7 [tg//Hz. The non-linearity

in all lateral axes is less than 0.35%.














CHAPTER 1
INTRODUCTION

The last couple of decades have been seeing the emergence and prevalence of

Micro-Electro-Mechanical Systems (MEMS) technology. Many MEMS products, from

the first generation of pressure sensors to newly developed integrated MEMS

accelerometers and gyroscopes[1-4] have been commercialized at a fraction of the cost

and size of conventional devices. Manufacturing technologies have been developed

specifically for MEMS, and some MEMS foundry services such as MUMPS and

MEMS-Exchange are now available commercially [5-7] to MEMS community.

However, these fabrication technologies are more research oriented and often

incompatible with mainstream Complementary Metal-Oxide Semiconductor (CMOS)

technology. The requirement of separate signal-conditioning circuitry, which in turn

requires multi-chip assembly, makes the packaging of MEMS devices complicated and

expensive.

Small size, multi-function and low cost are the ultimate goals of commodity

MEMS devices. One way to achieve these goals is the monolithic integration of MEMS

technology with the standard integrated circuit (IC) technology. In fact, the crossover of

the conventional IC industry and the fast-growing MEMS technology has led to many

newborn technologies in the past years.

Much effort has been made and large capital has been invested into CMOS-

compatible MEMS technology, or CMOS-MEMS. With assorted approaches, MEMS









devices have been directly integrated with CMOS circuits, allowing smaller device sizes

and higher performance.

In this thesis research, a new post-CMOS MEMS technology is developed, and two

integrated devices a 3-axis and a single-axis accelerometer are demonstrated based on

this deep reactive-ion etch (DRIE) CMOS-MEMS technology. Device microfabrication

processes are investigated in detail. Device design is described and the characterization of

the fabricated devices is presented.

This chapter summarizes the related CMOS-MEMS technologies and previous

work on MEMS accelerometers. The organization of the thesis is given at the end of the

chapter.

1.1 CMOS-MEMS Technology

The integration of MEMS technology with the mainstream CMOS technology is

referred to as CMOS-MEMS technology. This approach can be classified in three

categories: pre-CMOS, inter-CMOS and post-CMOS technology [8], determined by

when the MEMS processing is performed relative to the CMOS processing.

1.1.1 Pre- and Inter-CMOS MEMS Technology

In the pre-CMOS technology represented by iMEMS developed by Sandia

National Laboratory, MEMS structures are pre-defined before CMOS processes [9]. Post-

CMOS release processes are still required in device fabrication. Analog Device, Inc

(ADI) adapted Sandia's approach and developed a MEMS technology based on its

BiCMOS process. This iMEMS technology, originally dedicated to CMOS-MEMS

accelerometer and gyroscope fabrication, is an intermediate-CMOS MEMS, or inter-

CMOS MEMS technology, in which LPCVD polysilicon deposition and annealing are

inserted into CMOS process steps for the formation of inertial sensor micor structures









[10, 11]. Infinion's pressure sensor is also fabricated using this type of inter-CMOS

MEMS technology [12]. To reduce the residual stress in structural polysilicon, high

temperature annealing of polysilicon is normally required in inter-CMOS MEMS, which

could pose a potential risk to previous CMOS layers. Contamination caused by the

process switch between microfabrication of MEMS structure and normal CMOS steps

would be another serious problem. Therefore, usually a dedicated foundry is required for

inter-CMOS MEMS technology.

Since most pre- and inter- CMOS MEMS technologies were developed for surface

micromachining with polysilicon as the structural material, they suffer from some

limitations as the following [13]:

* Mechanical performance of polysilicon is not as good as that of single crystal
silicon (SCS). The structure size is limited by the residual stress of thin-film
structures. The smaller mass will result in higher thermo-mechanical noise in
devices such as accelerometers where a large proof mass is required for high
resolution.

* The curling of thin-film structures due to residual stress will severely reduce both
the mechanical and electrical performance of MEMS devices. The temperature
dependence and robustness of the device will be degraded as well.

* In the electrical domain, the parasitics between the polysilicon structures and the
substrate underneath will reduce the output signal dramatically. In a surface
micromachined polysilicon accelerometer, depending on the polysilicon wiring
path, the parasitic capacitance can be as high as the order of pF [14], which could
be several times larger than the sensing capacitance. This will lower the resolution
and sensitivity of the device.

* Many thin-film polysilicon MEMS structures are fabricated using wet release in
which the sacrificial Si02 layer is etched by HF. Although vapor phase etch can be
employed, stiction problems become severe when the feature size of a device is
reduced to a few microns.

* The processes need to meet very stringent criteria to eliminate the potential
contamination to the following CMOS process steps.

* The limited foundry availability, especially for inter-CMOS MEMS foundries,
makes the overall cost of MEMS devices relatively high.









1.1.2 Post-CMOS MEMS Technologies

Post-CMOS MEMS technology has a potential to overcome the above-mentioned

drawbacks by providing robust and sensitive detecting structures. In contrast to both pre-

CMOS MEMS and inter-CMOS MEMS, in post-CMOS MEMS technology, the

fabrication of the CMOS circuitry and MEMS structures are performed independently.

This makes it possible to integrate high performance mechanical structures made of bulk

materials with high performance electronics.

There are mainly two integration methods for post-CMOS micromachining. The

first one is to add MEMS structures on the CMOS substrate, leaving the CMOS layers

un-etched during the structure microfabrication. The second is to form the MEMS

structures by performing micromachining directly in the CMOS thin film layers and/or

substrate. These two processing methods are addressed as the following.

1.1.2.1 Additional MEMS structures on CMOS substrate

By adding additional layers onto a CMOS substrate, both metal, dielectric and

other semiconductor materials with desired mechanical properties can be used to form

MEMS structures. Because of its low process temperature, electroplating is frequently

employed in the formation of metal micro structure [15]. In Texas Instruments' popular

digital micromirror devices (DMDTM), a sputtered metal is used as the mirror structural

material and deep-UV hardened photoresist is used as the sacrificial layer [16]. A

research group at UC-Berkeley developed a modularly integrated MEMS technology

(MOD-MEMS) in which both polysilicon and poly-SiGe can be used as structural

materials. However, when polysilicon was used as the structural material in this MOD-

MEMS technology, the aluminum interconnection in standard CMOS technology must be

replaced with refractory metals such as tungsten to satisfy the high temperature









requirement for polysilicon annealing [17]. Moreover, a TiN4 barrier layer should also be

added to prevent the reaction between silicon and tungsten. These metallization steps are

non-standard CMOS processes and can introduce further residual stresses in polysilicon

structural layers. A low temperature process in which SiGe is used as the MEMS

structural material was developed recently by the same group at Berkeley and a SiGe

resonator was demonstrated [18] using this process. In this MOD-MEMS technology, in-

situ p-doped polycrystalline SiGe was deposited at approximately 4500C using low

pressure chemical vapor deposition (LPCVD) and etched with conventional reactive ion

etch (RIE). Germanium was used as sacrificial layer since it could be easily etched using

H202, with a high selectivity over oxide, poly SiGe (if Ge concentration is less than 70%)

and metal. Unfortunately, due to the low deposition temperature, the mechanical

properties of poly SiGe were not as good as those of polysilicon. Moreover, the laser

melting annealing (ablation) needed in this process also introduces stress gradient in poly

SiGe thin films. Therefore, currently this material is not suitable for MEMS devices such

as MEMS accelerometers.

Accelerometers made of electroplated copper on silicon substrate have also been

demonstrated [19]. Potentially, the integration of electroplated MEMS structures with

CMOS substrate is achievable, although the contamination of heavy metal ions to the

CMOS circuit is possible.

In addition to the formation of MEMS structures on top of CMOS substrate by thin

film deposition, wafer bonding provides another method to directly integrate the wafers

containing MEMS structures on CMOS substrate wafer. This approach is exemplified by

the fabrication process of a polysilicon thin film accelerometer [20]. In this









accelerometer, the prefabricated polysilicon capacitive acceleration sensor was bonded to

the substrate wafer on which electrodes and CMOS read-out electronics were also

prefabricated separately. In another wafer-bonded piezoresistive accelerometer, the

micromachined bulk silicon proof mass was sandwiched by a bottom glass cap and a top

CMOS chip in which the conditioning circuit was pre-fabricated [21].

1.1.2.2 Formation of MEMS in CMOS substrate

In the second type of post-CMOS MEMS, the CMOS surface layers and silicon

substrate can be used to create surface and bulk MEMS structures. A high-Q RF MEMS

filter with inter-metal dielectric layer as the structural material was reported by IBM [22].

A medical tactile sensor array was also reported in which the aluminum sacrificial layer

was etched from the backside of the wafer after the CMOS substrate was etched

completely [23]. A research group at ETH in Switzerland processes bulk silicon substrate

of CMOS wafer with anisotropic wet etch to obtain thin film and bulk MEMS devices

[24]. For thermal sensors in which membranes consisting of dielectric layers are needed

for thermal isolation, substrate silicon can be etched completely to obtain the suspended

dielectric membranes [25]. The silicon dioxide membrane acts as an intrinsic etch stop

layer in a backside silicon anisotropic wet etch using KOH or TMAH solution. Using this

anisotropic wet etch based post-CMOS process, 256-pixel thermal imager arrays and

multifunctional chemical sensors have been developed [26, 27]. Recently, a monolithic

CO gas sensor with an integrated hotplate was reported from the same group [28]. By

combining the electrochemical stop techniques with KOH anisotropic etch, silicon

membranes with n-well islands can be obtained. In this auto-stop technique, the

anisotropic etch stops at the pn junction [29]. This process can be specifically used in the

fabrication of highly sensitive pressure and force sensors [30]. By combing silicon









anisotropic wet etch with deep reactive ion etch (DRIE), some sophisticated surface and

bulk MEMS structures such as bridges and cantilever arrays can be created. A

multisensor system was demonstrated using the combined etch processes [31].

The main challenge in the wet post-CMOS MEMS technology is the protection of

the CMOS structures. When etch stop is required for silicon diaphragm formation, the

preparation for electrochemical process also increases the complexity of the process.

Also, in most cases, precise double-side alignment is required in the fabrication of silicon

islands using wet etch.

The technological approaches developed by Carnegie Mellon University differ

from those described above in that only dry etch steps are used to create both surface and

bulk MEMS structures [32, 33]. Dielectric layers and bulk silicon substrate are etched by

isotropic/anisotropic RIE and DRIE respectively, avoiding the potential stiction problem

that is common to wet release processes. This dry technology shows another particular

advantage in that it is a maskless process, where CMOS metal layers act as masks in the

dry etch steps. The MEMS structures are pre-defined by the proper arrangement of metal

layers; thus no lithography is needed in this post-CMOS micromachining process.

Moreover, multi metal layers (normally 3-6 layers from different CMOS technologies

and foundries) make the wiring of the devices flexible which in turn reduces the parasitic

effects and improves the electrical performance.

This approach was originally developed for thin film MEMS structures in which

mainly surface micromachining was involved [34]. A device based on a copper CMOS

technology was also reported [35]. The size of the MEMS structures fabricated using this

post-CMOS surface micromachining was strictly limited due to the large curling of thin-









film structures caused by residual stresses. The maximum device size achieved was about

400[tmx400[tm. Meanwhile, the strong temperature dependence of the thin-film MEMS

structures caused by the mismatch of the temperature coefficient of expansion (TCE) of

the materials in the thin films also limited their reliable application. Figure 1-1 shows the

SEM image of a single-axis accelerometer fabricated using the thin film CMOS-MEMS

technology [36].






Spri-iB '!,-, ...












Figure 1-1. A lateral accelerometer fabricated using the thin film CMOS-MEMS
technology. Device size is limited due to the large curling of the thin film
structures. After Luo, with permission [36].

A DRIE CMOS-MEMS process was developed later based on the surface

micromachining described above. In this DRIE CMOS-MEMS technology, single crystal

silicon (SCS) was etched using DRIE to form bulk MEMS structures [33]. This DRIE

CMOS-MEMS technology has shown great advantages in the fabrication of relatively

large MEMS devices such as micromirrors [37]. A large flat mirror can be obtained with

bulk silicon existing underneath the aluminum mirror surface. However, when fine

structures such as comb drives are fabricated through this process, the isotropic undercut









needed for the formation of electrical isolation structures will have some severe effects

on MEMS structures. Figure 1-2 shows the SEM images of sensing comb fingers in a

CMOS-MEMS integrated accelerometer fabricated using the previous DRIE CMOS-

MEM process [38]. The SCS underneath the comb fingers was severely undercut when

isotropic etch was performed to undercut the end of the fingers where the isolation beams

are located.















Isolation beams Severe undercut on SCS


,, -- ...





i i I







Figure 1-2. SEM images of some sensing comb fingers in an integrated accelerometer
fabricated using the previous DRIE CMOS-MEMS process. SCS underneath
the fingers was severely undercut when isotropic etch was performed for
isolation beam undercut. Images were taken at orthogonal angles.









In this thesis work, a new process is developed to overcome the drawbacks of the

previous DRIE post-CMOS technology. As a demonstration of the new process, an

integrated 3-axis accelerometer and a single-axis accelerometer are designed and

fabricated using the developed new technology.

1.2 MEMS Accelerometers

The accelerometer is one of the first devices demonstrated using MEMS

technology. Since the early 1990's, MEMS accelerometers have been dominating the

fast-growing market of inertial sensors. Analog Devices is one of the major MEMS

accelerometer suppliers. After it shipped its first iMEMSTM accelerometer in the year of

1994, it took about 10 years for the market to grow to 100 million units. As

accelerometers have found enormous applications beyond its original business of air-bags

in automotive, ADI will ship its second 100 million MEMS accelerometers in only two

and half years [39].

The wide spectrum of applications for MEMS accelerometers is attributed to their

small size, high sensitivity and low cost due to the large product volume. The

conventional applications for accelerometers include automotive safety, inertial

navigation and guidance, seismetic and engineering monitoring, explosion measurement

in oil drilling, etc. Newer applications of MEMS accelerometers relate to the intelligent

data carrier systems, in which data logging/transfer is used between monitoring

accelerometers and the data processing center. Wireless communication is essential in

many of these data carrier systems. Other typical applications include management of

rental vehicles, monitoring and tracking of cargo or goods in logistics systems, working

condition and health monitoring. Figure 1-3 illustrates the typical applications and

performance requirements for accelerometers in these applications[40]. To date, the







11


fastest growth of MEMS accelerometers is in the consumer electronics industry. The

prevalence of portable electronics and personal communication tools have tremendously

boosted the need for small-sized MEMS accelerometers and gyroscopes. Several models

of cellular phones and personal data assistants (PDA) have been reported to perform

certain functions using just specific hand motions in different directions [41]. Computer

and game peripheral manufactures are increasingly integrating MEMS accelerometers in

their products. The handheld electronics market is expected to exceed 600 million units in

2005, in which MEMS inertial sensors are expected to play a major role by enabling new

functionalities and ease of operation.


104

103


102


10

1


10-


Explosion monitoring


106 1
10.6 10.4


10-2 1
Acceleration (g)


Figure 1-3. Typical applications and performance requirements of accelerometers.


102


104









1.2.1 Sensing Mechanisms of MEMS Accelerometers

In principle, many physical effects can be used for acceleration or position sensing.

The first micromachined accelerometer commercialized by NovaSensor was

piezoresistive [42]. The main advantages of piezoresistive accelerometers are the

simplicity of their structures and fabrication processes as well as the read-out circuits.

However, piezoresistive devices have some critical drawbacks such as low sensitivity and

large temperature dependence. Complex temperature compensation circuits are often

needed and a very large proof mass is essential for an acceptable sensitivity.

The capacitive sensing mechanism is dominant in MEMS accelerometers for

several reasons. Both surface and bulk micromachining can be used to fabricate a variety

of capacitive accelerometers with performance ranging from the low-end automotive

application grade to the high-precision inertial navigation grade. Compared to

piezoresistive accelerometers, capacitive accelerometers have high sensitivity, low power

consumption, low noise level, stable dc characteristics and less temperature dependence.

Their simple structures and fabrication processes make the integration of conditioning

circuits with sensing elements more straightforward. Due to these advantages, integrated

capacitive accelerometers are the primary focus for the booming portable electronics

industry.

While capacitive and piezoresistive sensing are two of the most common sensing

mechanisms, other physical mechanisms such as resonant frequency shift, thermal

transfer and quantum electron tunneling have been exploited as well for the acceleration

and motion sensing. A micromachined vibrating beam accelerometer and a vacuum

packaged resonant accelerometer have been reported respectively [43, 44]. In both

resonant accelerometers, the force generated by the external acceleration on the specially









designed proof mass changes its resonant frequency. Therefore, the acceleration is

measured in terms of a shifted resonant frequency of the resonant device. The apparent

advantage of the resonant accelerometer is its direct digital output. Thermal

accelerometers have also been developed based on the principle of convection heat

transfer [45, 46]. Since there are no movable elements in this thermal accelerometer and

the manufacturing variations do not influence the thermal performance of the device,

these thermal accelerometers demonstrate very good robustness and good batch

reproducibility. To achieve high sensitivity, current tunneling effects have also been

exploited for sensing acceleration. [47-49]. These accelerometers measure the

displacement operating on the principle of quantum electron tunneling, which has very

high position sensitivity. A resolution of 20 ng/ Hzhas been accomplished by the

reported micromachined tunneling accelerometer [50]. This particular accelerometer

requires very specific technological processes. The complexity of the fabrication and

strict conditioning circuit design make it very difficult for this tunneling accelerometer to

be commercialized.

Other accelerometers using optical, piezoelectric and electromagnetic sensing

mechanisms have been demonstrated [51-54]. However, the integration of these

accelerometers with CMOS technology is a challenge.

1.2.2 Capacitive MEMS Accelerometers

Due to their prevalence, capacitive MEMS accelerometers are discussed in more

detail in this section.

Technologically, MEMS capacitive accelerometers can be categorized into three

types: thin-film accelerometers fabricated using surface micromachining; bulk









accelerometers fabricated using bulk micromachining and/or wafer bonding technology;

and other accelerometers fabricated using more exotic processes. Surface micromachined

accelerometers, e.g., polysilicon thin film capacitive accelerometers, have been

commercialized for more than ten years. They are available in large volume at very low

unit price [1]. However, due to their small proof mass, typically they can only achieve

several tens to several hundreds of/ug/ /Hz noise floor [55-57]. This constrains their

applications to only middle and low end devices and systems. Today, many high-end

inertial sensors are still dominated by very expensive non-MEMS or piezoelectric

devices.

In capacitive sensing, normally micro-g resolution can only be realized by bulk

accelerometers with large proof masses. Many of the reported high-performance

capacitive accelerometers use multi-wafer bonding or SOI technology to form a large,

thick proof mass [58-61]. Some special processes such as wafer dissolving, double-side

process and thick Epi-SOI are also utilized in the fabrication of bulk micromachined

capacitive accelerometers [62-64]. Recently a high-sensitivity bulk silicon capacitive

accelerometer with a mechanical noise floor of 0.18 jg / Hz was reported [65]. All

these reported bulk micromachined capacitive accelerometers employed wet etches to

form the large proof masses. The special techniques such as wafer bonding and automatic

stop in wet etching complicates the fabrication. If glass is used in wafer bonding to form

silicon-on-glass (SOG) accelerometers [66], the temperature performance of the devices

could be degraded due to the mismatch of the thermal expansion coefficients between the

glass substrate and the sensing element. SOI technology makes the fabrication and further









monolithic integration of the accelerometer very costly. The previous works on bulk

micromachined capacitive accelerometers are summarized in Table 1-1.

Table 1-1 Summary of previous work on bulk micromachined capacitive accelerometers.
Contributors Published Structure and/or Accelerometer
year process used performance (noise
floor)
Rudolf et al [58] 1990 Sandwiched silicon-glass 1.0 ug /Hz
Henrion et al [59] 1990 Sandwiched silicon-glass, 120 dBg/-Hz
Multi-step wet etch 260 Hz bandwidth
Warren [60] 1994 SIMOX N/A
Bernstein et al [61] 1999 Silicon-glass bonding 1.0 g g/ 4Hz
Dual chips 1 kHz bandwidth
Combination of wet and
dry etch
Automatic wet etch stop
Yazdi, et al [63] 2000 Combination of bulk and 0.23 ug / JHz
surface micromachining
Wet release
Yazdi et al [65] 2003 Combination of bulk and 0.18 l g//Hz
surface micromachining
Wet release
Chae et al [62] 2005 SOG structure 79 ug/f/Hz
Silicon-glass bonding
Silicon thinning by CMP
_Dry release


Other non-mainstream technologies were reported for fabrication of specific

capacitive accelerometers as well [67-69]. These technologies require some unique

processes and equipment which are currently cost-prohibitive for commercialization.

The DRIE post-CMOS MEMS technology can be used in bulk micromachining for

in-plane or out-of-plane capacitive sensing devices. It has the capability of creating thick

structures with pure dry etch, which avoids the problems in wet release. An in-plane

driving, out-of-plane Coriolis acceleration sensing gyroscope has been demonstrated

using this bulk DRIE post-CMOS MEMS technology [70].










The achievable device performances versus device sizes with different

technological approaches mentioned above are further illustrated in Figure 1-4. DRIE

CMOS-MEMS technology has advantages of monolithic integration of bulk MEMS

structures and interface circuits fabricated using mainstream CMOS technologies,

allowing MEMS devices with overall higher system performance.

In this work, 3-axis and single-axis single-crystal silicon (SCS) accelerometers are

designed and fabricated using an improved DRIE post-CMOS MEMS technology [71].


Thin-film
technology


Lemkin, 1997: 110
ADXL105: 225
STM: 50
Luo,2000: 1000
Wu, 2004: 50


Yazdi et al, 2000: 0.18
(wafer bonding)
Chae et al, : 0.23 (SOG)
Bernstein et al: 1.0
Chae et al, 2004, 1.6
Chae et al, 2005: 79 (SOG)


101 -


Qu et al, IEEE Sensors, 2004
Qu et al, HH, 2006.


1 10 100
Footprint (mm2)


Figure 1-4. Achievable device performance versus device size with different
technological approaches shows the advantage of the DRIE CMOS-MEMS
technology.


103 -


102
10 -



10



1 -









1.3 3-Axis CMOS-MEMS Accelerometers

Millions of portable personal electronics require smaller inertial sensors for easier

operation and more functionality. Integrated dual- or tri-axis accelerometers are

advantageous for these portable devices in terms of compact size and multi-axis sensing.

The first monolithic single-axis accelerometer was industrialized by ADI [72].

Later on, dual-axis monolithic accelerometers were also commercialized. Recently tri-

axis integrated accelerometers have been released by a few industrial companies [3, 4, 73,

74]. The majority of multi-axis accelerometers in the market are hybrid, where single-

axis sensing elements and conditioning circuits are assembled together and packaged in

the same enclosure. There is a tradeoff between the monolithic integration and hybrid

approaches. The advantages of monolithic integration are smaller device size and better

signal conditioning. But these advantages are attained at the cost of more complicated

fabrication processes. The hybrid solution, on the other hand, allows optimized

mechanical structures and signal processing circuits to be realized by dedicated and well-

established fabrication processes. The drawbacks include the relatively large package

sizes and large parasitics caused by the wiring and bonding between the sensing elements

and the signal processing application-specific IC (ASIC). Some high performance hybrid

capacitive accelerometers were reported from both industry and academic institutes [62,

66, 75, 76].

Multi-axis accelerometers employing other sensing mechanisms are also available.

With proper design of the suspending beams and the configuration of piezoresistive

bridge, 3-axis piezoresistive accelerometers with a single proof mass can be easily

achieved using SCS or SOI [21, 77]. Some 3-axis piezoresistive accelerometers are

already available as volume products [78, 79].









However, in most of the reported monolithic dual-axis or tri-axis accelerometers,

separated in-plane and out-of-plane proof masses are used. Or, at least the out-of-plane

element for z-axis sensing is separated from the lateral element where x, y-axis sensing

parts share the same proof mass [80]. The advantage of the separated proof masses is

usually the reduced cross-talk between the sensing axes. Yet it is self-evident that the

electrical performance is degraded by the larger parasitic effects. In addition, this

approach is less economical due to the large device size, especially for middle to low end

capacitive accelerometers used in consumer electronics where small size and low cost are

the main concern.

The lack of 3-axis monolithic capacitive accelerometers with a single proof mass is

due to the difficulty in the realization of vertical out-of-plane and lateral in-plane sensing

using a shared proof mass. Z-axis sensing has two primary challenges. The first is how to

use horizontal electrodes to sense out-of-plane displacements with the presence of large

parasitic capacitances to the substrate, especially when differential sensing is needed. The

second is how to realize large capacitance changes in the z-axis using vertically-oriented

electrodes. In most of the reported z-axis capacitive accelerometers where the z-axis

proof mass moves vertically, polysilicon is used as the lower electrode of a horizontally-

oriented sensing parallel plate capacitor. A fixed reference capacitor is also typically

fabricated on the substrate. Therefore, it is difficult to have a fully differential output

from the sensor node [14, 81].

Recently a z-axis sensing torsional accelerometer with horizontal capacitors and

differential output was reported [82]. Due to the asymmetric arrangement of the sensing

capacitors, the satisfactory linearity of the accelerometer is only limited to Ig. Moreover,









the sensitivity of the accelerometer is extremely constrained by the process performed on

a costly SOI substrate. The process is less controllable in that the formation of the

horizontal gap for vertical sensing is greatly affected by the later processes. Only a

minimum of 4tlm vertical gap can be achieved due to the influence of the damping hole

etch on the pre-defined z-sensing gap. In another torsional z-axis accelerometer

fabricated using dissolved wafer process (DWP), acceleration in z-axis is detected by

vertically-oriented interdigitated capacitors [83]. The change of the capacitance between

stators and rotors are caused by the variation of their common area instead of the change

of the gap between them. A linearity of 0.2% in an acceleration range of-4 3g and a

mechanical noise of 0.28 mg I/Hz was achieved. No differential output can be realized

from the sensor node due to its mechanism. Thus, this accelerometer can not detect the

direction of the acceleration in z direction.

If fully-differential z sensing can be properly realized, the cross-talk among three

axes can be greatly eliminated and the sharing of the same proof mass for 3-axis sensing

will be feasible with proper mechanical design. More recently, fully differential z-axis

accelerometers using sidewall capacitance formed by CMOS metal layers were reported

[84, 85]. Due to the thin film mechanical springs employed in these accelerometers, these

devices still suffer the constrains of thin film devices.

This thesis work targets an integrated 3-axis capacitive accelerometer with a

shared, bulk silicon proof mass scheme [86]. With a unique z-axis sensing mechanism,

fully differential sensing will be achieved in all three axes. The developed DRIE post-

CMOS MEMS technology will be employed in the fabrication of this compact tri-axis

accelerometer.









1.4 Thesis Goals and Organization

In this thesis work, a novel DRIE post-CMOS MEMS technology is developed, and

two devices a 3-axis and a single-axis integrated accelerometer are designed and

fabricated based on the new fabrication process.

In the improved DRIE post-CMOS MEMS, details of dry etch based

micromachining of the designed MEMS devices with fine structures are explored. In

particular, some physical effects that arise from the plasma etching and affect both the

mechanical and electrical performance of suspended MEMS structures are investigated.

These detailed fabrication studies are directed towards creating general design rules and

optimizing the design and fabrication of MEMS devices. An integrated 3-axis and a

single-axis accelerometer are designed and fabricated to demonstrate the features of the

improved DRIE post-CMOS MEMS technology. Device design details are presented.

Chapter 1 introduces the background of CMOS MEMS technologies. Particularly,

the evolution of post-CMOS MEMS technology is presented and the prior works on a

variety of non-CMOS, CMOS-MEMS capacitive accelerometers are reviewed.

Chapter 2 is a technological introduction of plasma etch processes. Basic

processing tools used in the developed post-CMOS technology are introduced. Electron

cyclotron resonance (ECR) and inductively-coupled plasma (ICP) etchers for anisotropic

Si02 etch and silicon DRIE are introduced. Etching system configurations are described,

and the system characterizations are detailed based on the particular microfabrication

requirements for accelerometers.

Chapter 3 illustrates the DRIE post-CMOS MEMS technology and its potential

applications. For comparison, thin-film post-CMOS MEMS process and other previously

investigated DRIE CMOS-MEMS process are also addressed.









Chapter 4 focuses on the device design of the accelerometers. The mechanism of

fully differential z-axis sensing is detailed in addition to the lateral-axis accelerometer

design. Mechanical design and modeling of the single and 3-axis accelerometer are given,

and performance of the devices is predicted.

Chapter 5 discusses some specific practical issues in the fabrication of the devices.

Contaminations of the surface and sidewalls of the sample during plasma processes, and

their impact on the successful device release are addressed. Thermal effects on MEMS

structures in the DRIE release step are investigated. To have a better control of the etch

process, especially the release step, a simplified model is created to estimate the

temperature rising on the suspended MEMS structures during the plasma etch. This

model helps in understanding and eliminating of the structure damage caused by the

thermal effect mentioned above. Based on these observations in the microfabrication,

MEMS device design rules and optimization considerations are discussed.

In Chapter 6, the characterizations of the fabricated devices are detailed. The

experimental setups are introduced followed by test results. Discussions on the

performance of the devices are addressed.

Chapter 7 concludes the thesis work and proposes some future work including the

wafer-level microfabrication processes for CMOS-MEMS devices.














CHAPTER 2
DRY POST-CMOS MICROFABRICATION AND TOOLS

To improve the performance of MEMS devices, a new DRIE post-CMOS MEMS

technology has been developed in this thesis work. This post-CMOS micromachining

consists of multiple plasma etch steps of Si02 layer and Si substrate. Therefore, in the

development of the new technology, individual plasma dry etch process should be

optimized. As part of this thesis work, thick Si02 anisotropic RIE etch and Si DRIE used

in the new technology were investigated and optimized. Test structures were designed for

the purpose of individual process calibration and the extraction of critical technology-

based device design rules.

In this chapter, plasma etch technologies involved in the developed DRIE post-

CMOS technology are introduced and the relevant etching systems are calibrated using

the test structures. The choice of the processes for the new technology is based on the

availability of the qualified equipment locally on campus at the University of Florida.

2.1 Plasma Etch

In MEMS structure release, plasma dry etch method has advantages over wet etch

in structure profile control, stiction prevention and etch efficiency. The DRIE post-

CMOS MEMS technology developed in this work is completely based on the plasma dry

etch of Si02 and silicon. Therefore, the control of these plasma etch processes is a critical

issue to the fabrication and the final performance of the MEMS devices. The dielectric

etch is used to open the patterns of MEMS structures, therefore anisotropic profiles are

needed. For silicon etch, both isotropic and anisotropic processing are used. Normally, in









terms of the feature size and etching depth, plasma etch in MEMS microfabrication

differs from that in VLSI and ULSI. Their differences can be summarized in Table 2-1.

Table 2-1 Comparison of plasma etch in IC and MEMS
Plasma Etching Parameters In ICs In MEMS Devices
Feature size Small Relatively large
Depth Small Large
Aspect ratio Small to middle Middle to large
Structure refill Yes Normally No
Etching time Short Long
Etch induced structure damage Less More
Etched surface contamination Less More


There are many kinds of plasma-based etch technologies in which both chemical

and physical processes are employed for the etch [87]. Plasma can be described as an

electrically neutral gas that contains equal numbers of positive and negative charges in

addition to neutral atoms, radicals or molecules and photons emitted from the excited

species [88]. Positively charged carriers are mostly ionized atoms, radicals, or molecules

created by the impact of particles with electrons. The majority of negative charges are

electrons. However, when some of positive carriers capture electrons from the plasma,

they can also convert themselves into negative charges. Neutral atoms, radicals and

molecules can be in their ground states or excited states. When species in an excited state

lose their energy via spontaneous transitions to resume their lower energy levels, photons

are emitted and a plasma glow is observed. Many external parameters, such as chamber

pressure, reactor geometry and residence time in the reactor, affect the composition and

relative concentration of individual carriers. Radicals and neutrals are main reactive

species in the plasma etch. Radicals are much more abundant in a glow discharge

(plasma) than ions because of their lower excited energy state and longer life time.

However, the relative fluxes of radicals and neutral atoms are compatible. This is due to









the following two factors. On one hand, ions move faster than radicals as a result of

kinetic energy gained from the applied electric field. On the other hand, heavier radicals

move toward the substrate mainly by diffusion. Radicals have a larger tendency to be

absorbed on the reacting surface due to their unfilled outer electron shell.

The etch process in plasma can be categorized into seven steps, as shown in

Figure 2-1.




(a)




(b) (g)




(c) (d) (e)




Figure 2-1. Seven steps of the etch process. (a) Dissociation and ionization of the reactive
species. (b) Diffusion of the reactive radicals. (c) Absorption of radicals on
surface. (d) Radical surface diffusion. (e) Chemical reaction. (f) Desorption of
the by-products. (g) By-product diffusion to the chamber.

Reactive species (radicals, ions, etc.) are generated by excitation, dissociation or

ionization in the glow discharge. By diffusion or acceleration due to the external electric

field, these particles reach the substrate. Radicals are absorbed on the substrate surface,

while ions, with their momentum, may disintegrate upon impact to the substrate and

penetrate into the surface for a certain depth. With the help of surface diffusion, the

reactions may happen locally on the landing site of the carriers, or somewhere in the









diffusion path of the carrier on the substrate surface. Finally, the reaction products leave

the substrate surface, either by desorption if the by-products are volatile, or by ion-

activated processes, and diffuse back into the plasma [87].

There are four basic etching mechanisms which contribute unequally to the etch

process. They are illustrated in Figure 2-2 and their impacts on the etched materials are

summarized as the following.


( Ions

0 Radicals





(a) (b)

ST inhibitor




(c) (d)

Figure 2-2. Four basic etch mechanisms. (a) Physical sputtering. (b) Chemical reaction by
neutral radicals. (c) Ion enhanced chemical reaction. (d) Ion enhanced
inhibitors.

Physical sputtering. The interaction of the impinging ions with substrate surface is

a purely physical process in which momentum transfer is involved. The substrate atoms

are mechanically ejected by ions with kinetic energy typically higher than 200 eV. This

results in very anisotropic profiles, rough surface morphology, trenching effect and poor

selectivity. The high energy ion bombardment always causes damages to the substrate.









Due to its physical nature, the etching rate of sputtering is very slow, lowing the

efficiency of this etch method.

Chemical reaction. This etch is dominated by the chemical reaction between the

neutral reactive species and the substrate, which results in volatile by-products. The

chemical reactions rely on the formation of the reactive species and their absorption on

the surface of the substrate. However, the main requirement for the chemical etch is the

volatility of the by-product from the reaction. Good etch rate and high selectivity can be

obtained from chemical etch, and the plasma induced damage can be minimized. With

less physical enhancement, chemical etch demonstrates isotropy which is unwanted for

the formation of vertical profile.

Energetic ion-enhanced chemical reaction. The neutral radicals slightly interact

with the surface of substrate. The impinging ions alter the substrate or product layer, so

that chemical reactions can take place more efficiently at the interface and the by-

products can be delivered more easily into the plasma. This process offers highly

anisotropic features since sidewalls receive minimal ion flux.

Ion-enhanced inhibitor. The inhibitor species form a polymer like thin film on

sidewalls, which excludes the impinging neutral etchant. This process prevents the

sidewall from being etched and thus leads to an increased anisotropy. It differs from the

energetic ion-enhanced reaction in that the chemical etching can take place without the

presence of impinging ions. Neutral etchant species spontaneously gasify the substrate

material, and ions play a role by interacting with another component instead of substrate

material and reaction by-product. That component is the protective inhibitor film. The ion

flux breaks down the protective inhibitor film on the horizontal surface which is at a right









angle to the flux, allows the chemical etch to proceed anisotropically. Meanwhile, the

protective film is not removed from the vertical sidewalls because these surfaces only

intercept few ions scattered from other directions. The protective inhibitor may originate

both from the involatile etch by-product or from film-forming precursors that absorbed

on the surface of substrate during the etching process.

The last two ion-assisted plasma etch mechanisms dominate in most dry etching

techniques that are widely used in VLSI and MEMS manufacturing and microfabricating.

Reactive ion etch (RIE) is widely used in dielectric etch because of its high etch rate,

high selectivity and easy control of the etching profile. Deep RIE provides an effective

method for deep trench etch in silicon substrate to achieve bulk MEMS devices.

Several energy coupling methods have been developed in the configuration of

plasma reactors [88]. Of them electron cyclotron resonance (ECR) and inductive coupled

plasma (ICP) are most widely used due to their high plasma density thus effective etch.

Both of them can work at lower pressure and provide higher aspect ratio etching. The

long mean free path (MFP) of gas molecules and ions due to the low system pressure can

reduce the scattering collision, enabling very directional etch along the direction of

biasing electric field. More power can be coupled into plasma due to the high ion density

sources, resulting in greater dissociation of etch species.

The main difference between an ECR and ICP system lies in the method to shape

and sustain the plasma. An ECR reactor employs an external magnetic field to shape and

contain the plasma; while an ICP reactor uses an inductively coupled RF bias to sustain

high density ions in the discharge [88]. The configurations of these two systems are

illustrated in Figure 2-3.









In an ECR reactor, microwave energy is coupled to the natural resonant frequency

of the electron in the presence of a static magnetic filed. The resonance of electrons in

plasma occurs when the microwave excitation frequency reaches the electron cyclotron

frequency which is given by

eB
) = e (2.1)
me
m

where e is the unit charge of an electron, B is the strength of the static magnetic field and

me is the electron mass. In practice, this requirement can be satisfied in a discharge by

adjusting the strength of the magnetic field. By presenting an electric field that is

perpendicular to the magnetic field, as shown in Figure 2-3, the electrons are accelerated

in the ECR volume to ionize and excite the neutral species. The result is a low pressure,

low collision plasma that can be tuned from a weakly to a highly ionized discharge by

changing pressure, gas flow and input microwave power. The advantage of the ECR

setup is the easy and cheap microwave power coupling, non-electrode in the system and,

low heating effect resulted from the electron collisions and, ultimately, the high density

ions and radicals in the plasma. ECR has gained great attractions in many plasma

processing applications.

On the contrary, an ICP reactor uses a radio frequency (RF) current applying to

three coils in opposite directions to generate and alternating magnetic field in the upward

and downward directions. It is the change rate of this magnetic field that induces a RF

electric field which confines and accelerates electrons in a circular path. This inductive

coupling is very efficient and leads to a high plasma density, normally one order higher

than ECR coupling. Since the electrons are trapped in a circular path, they have little

chance of reaching the sample chuck to lower the dc self-bias.














Upper magnet

Gas inlet r










Collimating
magnet









Gas inlet --


S Microwave
power



Plasma
glow

SChamber





Chuck bias
RF source


ICP coil


Figure 2-3. Configurations of ECR and ICP system. (a) ECR etcher, (b) ICP etcher.









Due to the well confined electrons, another RF source, driven at 13.56 MHz, is

applied to the chuck which can control the dc bias separately. This configuration allows

nearly independent control of ion flux (ICP power to the coils) and ion energy (RF power

to the chuck), making the tuning of the etching easier. The etch rate of ICP reactor is

much larger than other plasma etching tools due to the high concentration of the

dissociated radicals and ions. In addition, since the electrons are relatively confined,

fewer of them are lost to the chamber walls and electrodes compared to ECR, resulting in

lower dc bias and less ion damage on the sample. High density plasma can operate at

lower pressure, which increases the MFP of the radicals and ions and consequently

increases the anisotropy of the etching profile.

No matter what kind of etcher is used, the basic requirements for the dielectric or

silicon etching in MEMS technology remain the same. Relatively high etching rate, good

uniformity and profile control, high aspect ratio and high selectivity are the main criteria

for a good etching.

According to the availability of the reactors around, in this thesis work, an modified

PlasmaTherm ECR etcher (SLR-770) was used for the Si02 etch and an ICP reactor from

STS was employed for deep silicon etch in the development of DRIE post-CMOS MEMS

technology. The etching system characterization was conducted before the device

fabrication.

2.2 Characterization Methodology

Test structures were included on the same chips of the designed MEMS devices for

the purposes of in-situ process monitoring and etching characterization. They were

designed for the system characterization on assorted effects in SiO2 RIE and silicon

DRIE, which will be detailed in the following sections. Some layouts of the test









structures are given in Appendix A. In SiO2 etch characterization, rectangular bars

(cantilever beams after being etched) with permuted metal layer(s) were designed to

characterize the etch rate and profiles. These cantilever beams were designed to have

fixed length and width. This is to exclude the effects of process variations. In silicon

DRIE characterization, similar cantilever beams with different spacing were designed to

characterize the aspect-ratio dependent etching (ARDE) effect and the etching ratio.

A Dektak II step profilometer with accuracy of 10 nm was used in the depth

measurement for etch system characterization [89]. In the developed DRIE CMOS-

MEMS technology, the top aluminum layer acts as the etching mask in the etching steps

of the front side process. Therefore, aluminum etching (mainly physical milling) rate was

first characterized to define the reference plane in the measurement of etching rate in both

SiO2 and Si etch. After the glass passivation layer is etched and fresh top aluminum layer

is exposed, part of the spare region on the chip surface is covered by photoresist or

Kapton tape, which has very good thermal and chemical stability. As the Si02 RIE or Si

DRIE proceeds, the uncovered aluminum area will be milled with a small rate. After

certain etching time duration, a small step will be formed between the covered and

uncovered aluminum area. By measuring the height of the step after the removal of the

photoresist or Kapton tape, and dividing it by the etching time, aluminum milling rate

ral is obtained.

Then, after an etching time of t in the following SiO2 RIE or Si DRIE, the etching

rate can be calculated as,

r = h (2.2)
t









where h is the height of the measured step between the exposed top aluminum surface

and the surface of etching front.

Since normally aluminum milling rate is much smaller than SiO2 and Si etching

rate, the second term from the Al milling in the numerator can be neglected.

A Joel 6400 scanning electron microscope (SEM) and a FEI Strata DB 235 focused

ion beam (FIB) SEM were used for the etch profile observation and measurement.

2.3 SiO2 Etch

In the development of DRIE post-CMOS MEMS technology, RIE SiO2 etch is used

to open the patterns of microstructures. After the SiO2 etch, the top metal on the CMOS

stacks with alternate metal and Si02 layers acts as the mask in the following Si DRIE.

Thus the SiO2 etch quality will directly affect the final microstructures. The SiO2 RIE is a

complex system in which many process variables have impacts on the etch results. In

many cases, the influences of the process parameters are non-linear and co-related.

Therefore, design on experiment (DOE) is needed for the device/process design and

optimization.

2.2.1 Challenges in Anisotropic SiO2 RIE

Figure 2-4 shows the multiple responses of a SiO2 RIE system as a function of

multiple system input parameters. The output of the RIE has some specific influences on

MEMS structures due to the essential difference between the MEMS microfabrication

and the standard IC processes. Compared to the requirements of the normal IC process,

RIE used in MEMS technology has some special challenges.

The survival of the top metal layer and its profile. The Si02 layer that needs to be

etched in a MEMS device is usually much thicker than that in the standard IC devices.

This is due to the use of CMOS stacks that are consisted of alternate metal and Si02









layers. These CMOS stacks also act as masks in Si DRIE. The depth of the trench

between the mask stacks measures from the surface of top metal to the interface of

Si02/Si, ranging from a couple of |tm to as high as 12 |tm depending on the different

CMOS technologies employed. During the longer time SiO2 etch, the top metal layer is

exposed to the radicals and accelerated ions all the time, being milled physically or

etched very slightly. The edges of the patterned top metal will be rounded and the

microstructures will lose their critical dimensions.

The survival of interconnect vias and electrical connection of the MEMS device.

The electrical connection failure of MEMS devices, mostly the failure of interconnect

vias, may result from the SiO2 RIE. There are two mechanisms of the electrical

connection failure. The first is the milling of the top metal layer at the covers of the vias,

leaving an open circuit due to the broken via corner. This is a physical process in which

the ion bombardment damages via edges. The second failure mechanism is the lateral

etch of the barrier layer (normally TiN) above or underneath each Al layer. On the fine

microstructures with stacked CMOS layers, after the long Si02 RIE, the barrier layer

could be chemically etched through in the lateral directions on each side of the thin

structures, leaving the structure lose their electric connection. This lateral etch of the

barrier layer can also cause the delamination of aluminum layers in the MEMS structures.

To satisfy the above and other more general requirements of the Si02 RIE, etching

system should be very carefully characterized and design rules should be extracted from

the characterization for the successful future designs.









2.2.2 System Characterization

A PlasmaTherm SLR 770 RIE reactor was used in the SiO2 etch with CHF3/02 as

the etching chemicals. The output etch results were characterized as the functions of the

system variables in Figure 2-4. Since the output parameters are correlated to more than

one input variable, some tradeoffs should be made to have an optimal etch results. DOE

experiments were performed by sweeping individual system parameter with other

parameters fixed.


Temperature


Pressure -
Power --
CHF3/02 -
ratio


Loading


Gas flow rate


Etching profile

-- SiO2 etch rate
I- Selectivity

Milling damage

Byproduct


Electrode
spacing


Figure 2-4. System response of the input parameters in a Si02 RIE system.

The correlation of the etch results with input variables can be qualitatively

summarized as in Table 2-2.

Table 2-2. Influences of etching parameters on RIE etch results
Output Etch rate Top metal Sidewall Inhibitor
Input layer milling profile polymers
Microwave power T T T Varies
CHF3 gas flow rate T Varies Varies Varies
Chamber pressure T 1 1 "
02/CHF3 ratio Varies Varies Varies "
Dc bias of the sample TI T varies


RIE System


!











2.2.2.1 Etching rate

To reduce the total etch time, an appropriate etch rate should be attained. Higher


chemical etch rate helps to eliminate the ion milling of the top metal layer caused by the


long time physical bombardment. The etch rate and milling effect should be balanced by


adjusting the microwave power, chamber pressure and dc bias on the sample chuck (RF


power applied on the chuck). Figure 2-5(a) shows etch rate as the function of the coupled


microwave power. There is a steep section in the plot showing a critical value of the


coupled microwave power (about 700W) for sufficient concentration of dissociated


reactive radicals.


JUU

250

200

S150

" 100

C0 50


00 550 600 650 700 750 800 8
Microwave power (W)


300

250,

200

150

100[

50


2 4 6 8 10 12 14 16 18 20
System pressure (mT)

(b)


Figure 2-5. SiO2 etch rate as functions of system parameters. (a) plot of the etch rate as
the function of microwave power; (b) etch rate versus system pressure.

The coupled microwave power was selected as to be around 850W for an effective


etch. Too high microwave power can result in the top layer metal damage. The chamber


pressure dependence of the etching rate, as shown in Figure 2-1 l(b), reflects the ion


assistance in the chemical etch. Lower pressure allows longer MFP thus higher kinetic









energy of the ions, which benefit the etching by bombarding the surface SiO2 atoms,

providing a fresh reaction front and easing the delivery of the byproduct.

2.2.2.2 Top metal layer milling

For long-time RIE of thick SiO2 layers in CMOS stacks, the etch selectivity of SiO2

over Al is critical for the survival of the top Al layer and vias. It is observed that

aluminum etch during the SiO2 etch is actually due to the physical ion milling effect on

the aluminum layer. Therefore, the most significant influence on Al damage is from the

chuck bias at a given chamber pressure. Figure 2-6(a) shows part of a capacitive sensing

finger with milled top Al layer after 80 minutes of SiO2 etch. The microwave power used

in the etch was 700W at a system pressure of 5 mT. With a dc bias of 345V resulted from

a 75W RF power, the top Al layer was milled to approximately 0.3 rim, which is only

half of its original thickness.


If sidewall capacitance is used for vertical position sensing, as in the z-axis sensing

of the 3-axis accelerometer, which will be addressed in Chapter 4, the milled Al layer

will greatly reduce the sensing capacitance formed by Al sidewalls. In extreme case,

damage to the MEMS devices will arise in the subsequent etch processes if the top Al

layer, which acts as the mask for other etch steps, is completely milled away in the SiO2

etch. Under a similar etch condition, the corner of an interconnection via on a bonding

pad of a micromirror was etched away, resulting in an open circuit of the actuation

polysilicon heater, as shown in Figure 2-6(b). A lower chamber pressure increases the

MFP of the ions, allowing higher kinetic energy of the ions, which in turn reduces the

selectivity of SiO2/Al and deteriorates the damage on the top metal. This trend is shown

in Figure 2-6(c).










In practice, the microwave power was increased to 850W and the dc bias was

reduced to 140-150V. This results in a proper etch rate between 0.25 [tm/min and

0.33 [tm/min with a low aluminum milling rate. A selectivity of SiO2/Al as high as 50 has

been achieved.


Over-milled top Al layer


, 60
E

ci
g 40
ci
14
, 20
Mn 7n


Open via due to the over-milling

__ / __


8 10 12 14
System pressure (mT)


Figure 2-6. Impact of the SiO2 etch on the top Al layer. (a) over-milling of the top Al
layer on a comb finger of the fabricated accelerometer, (b) open via in an
electrothermal micromirror. (c) SiO2 etch rate and etch selectivity as the
function of system pressure.









2.2.2.3 Sidewall profile of the SiO2 layers and CMOS stacks

The main system variable which affects the sidewall profile of SiO2 layer is the

chamber pressure. With higher chamber pressures, the MFP of the ions and radicals

reduces, resulting in more random collisions among the radicals. The deflected ions and

radicals attack and react with the SiO2 on the sidewall, consequently resulting in a more

isotropic profile. For CMOS stacks with multiple layers of Al, it is prone to have an

undercut on the SiO2 between metal layers at a high chamber pressure. After

optimization, a 10 mT system pressure was selected for an adequate etching rate and a

reasonable SiO2 profile.

vias















(a) (b)

Figure 2-7. Profiles of the CMOS stack at different process stages. (a) after the first SiO2
etch; (b) after the second SiO2 etch. SiO2 etch was performed with a system
pressure of 10 mT.

Note there are two SiO2 RIE steps in the developed DRIE post-CMOS MEMS

process. The first SiO2 etch is to open the pattern of electrical isolation structures; while

the second is for other structures. Figure 2-7(a) and (b) show the sidewall profiles of

CMOS stacks after the first and second SiO2 etch respectively. It can be seen that a









straight vertical Si02 profile has been obtained and the vias have been nicely kept in

shape after the second Si02 etch, as shown in Figure 2-7(b).

2.2.2.4 The inhibitor polymer redeposition on the sidewall

As one of the RIE mechanisms, inhibitors generated in the SiO2 etch provide a

protection layer to the sidewall, making the etch more anisotropic. However, if the

feature size of the MEMS structure is small, or, if the inhibitors redeposited on the

sidewall are too thick, they will affect the feature size. This is due to the micromask

effect of the inhibitor film in the following Si02 RIE and Si DRIE. In addition to the

etching system variables (e.g. chamber pressure, microwave power and biasing RF

power), the oxygen concentration in the CHF3/02 etching chemical plays an important

role in the formation of the inhibitor polymers.

The SEM image in Figure 2-8(a) shows the thick inhibitor film formed on the

sidewall of the Si02. The energy dispersive spectroscopy (EDS) compositional analysis

result is also shown in Figure 2-8(b). The analysis was obtained by using the EDS system

integrated in a Joel 6400 SEM system. The presence of elements F, C and O in the film

indicates the polymer nature of the inhibitor. The existence of aluminum in the

redeposition layer is the evidence of the ion milling of the top Al layer. The milled Al

atoms collide with the downward ions from the plasma bulk and are swept to the CMOS

stack trench. They are then scattered to the sidewall by the reflected ions from the bottom

of the etched trench. The contamination of the sidewall with inhibitor film containing Al

will cause some problems in the silicon etch for the release of the MEMS structures. This

particular issue is addressed in Chapter 5.






































Counts
Al Si
2500-

2000-

1500-

1000- 0

500-

0-
0 1 2 3
(b) Energy (keV)



Figure 2-8. Inhibitor polymer formation in SiO2 etch. (a) Thick polymer layer on the
sidewall of isolation holes. (b) EDS spectrum of the inhibitor polymer.

Experimental results show that not only does oxygen concentration in the etching


gas affect the etch rate, but it also has impact on the formation of the inhibitor polymer


film in the etching. Figures 2-9 shows the SiO2 RIE etch rate as the function of the


oxygen concentration in the CHF3/02 etching chemicals. The etching rate peaks at the 02


concentration of about 5% 10%. It is widely accepted that in a certain concentration


range, the additive oxygen helps in dissociating more F radicals which is the main etchant










in the SiO2 etch [90]. When the 02 concentration is higher than 15%, Teflon-like (CF2)x

inhibitor will form, and the Si02 etching rate reduces. On the other hand, if 02 ratio is too

low, it does not help the dissociation of the CHF3. The plot agrees with the reported ECR

RIE of Si02 [91]. Figure 2-10 shows the polymer formed on the sidewall of CMOS

stacks after the final Si etch is performed. In Figure 2-10(a), thick polymer is present with

a higher oxygen concentration of 40%. In Figure 2-10(b), the redeposition of the polymer

is greatly reduced by lowering the oxygen concentration to 6.7%. The clean CMOS stack

sidewall is highly desired in the subsequent Si etch, especially when alternate SiO2 and Si

etch are required in the micromachining processes.


0.32

0.3

- 0.28
E
E 0.26

a 0.24

3 0.22

W 0.2

0.18

0.16L
0


5 10 15 20 25 30 35
Percentage of 02 in the gas mix (%)


40 45


Figure 2-9. Si02 etching rate as the function of oxygen concentration in the CHF3/02 gas
mix.












The oxygen concentration in the gas flow also has affects the etch selectivity of

SiO2 over Si. A lower oxygen concentration increases the SiO2/Si etching ratio by

reducing the Si etching rate. In our experiment, the etch selectivity of SiO2/Si increases

from 1.67 at a 40% oxygen concentration to 4.1 at 3.3% of oxygen concentration.

The final recipe for the SiO2 etch is listed in Table 2-3.


Thick inhibitor polymer with 02
concentration of 40% in the
SiO2 etch.


Inhibitor polymer is eliminated by
reducing 02 concentration to 6.7 %.
I


- -"lrM


I (bil
(b)


Figure 2-10. Inhibitor polymer formation as the function of oxygen concentration in the
CHF3/02 mixture. (a) Thick inhibitor polymer with 02 concentration of 40%
in the SiO2 etch. (b) Inhibitor polymer is reduced by reducing 02
concentration to 6.7 %.

Table 2-3. Anisotropic Si02 etch reci e on the PlasmaTherm SLR770 ECR RIE system
Parameters Settings
CHF3 flow 30 sccm
02 flow 3-5 sccm
RF2 power 850W
RF1 power (platen) 40W-50W (140-150V bias)
Chamber pressure 10 mT









2.4 Advanced Silicon Etch by STS ICP DRIE

Silicon DRIE is now a standard process for both bulk and surface micromachining

in MEMS fabrication due to its capability of high-aspect-ratio etch and high selectivity

over photoresist and Si02. It is common in an advanced silicon etch (ASE) system to

achieve an aspect-ratio (AR) of over 30, with selectivities over PR and Si02 being higher

than 50 and 100 respectively [92]. In the fabrication of many MEMS devices, silicon

DRIE is the final dry release step. Since the normal etch time of a silicon DRIE step is

relatively long, especially when a thick MEMS structure is fabricated, a number of

geometry-related effects also play very significant roles in the final structure formation.

These effects should be considered at both the device design and fabrication stages as

additional design rules which are of equal importance as the basic process requirements

[93, 94]. According to the fabrication level, the geometry-depended effects and other

process variations can be categorized into inter-die effects and intra-die effects. The inter-

die effects include spatial cross-wafer etch rate variations induced by the chamber

geometry, and the macroloading effect caused by a global variation of etching species.

The intra-die effects consist of aspect ratio dependent etching (ARDE) and microloading

effect.

There is a difference between ARDE and microloading effect. ARDE is an effect in

which the etch rate decreases as a result of the reduced transport of reactive species in

deep and narrow structures. Whereas in microloading effect, the etch rate reduction is

caused by a local depletion of reactive species.

In the improved DRIE post-CMOS MEMS technology, which is detailed in

Chapter 3, three silicon DRIE steps are used in the fabrication of the accelerometers. The

first is the backside etch by which the chip or wafer is thinned to the desired thickness.









The second step is the etch-through of the isolation trenches. The third is the etch-through

of the structures to release the device. If necessary, more DRIE can be conducted in

between the above two steps to form some particular structures. For example, one more

silicon DRIE and isotropic silicon undercut is needed to create the isolation structure in

the developed capacitive accelerometer.

In this section, the characterization of the DRIE etcher and some geometry-

depended effects in the silicon DRIE are addressed. The silicon DRIE in the developed

post-CMOS MEMS technology was conducted using an ICP etcher from Surface

Technology Systems (STS), LLC.

2.3.1 ICP Silicon DRIE System Configuration

The system configuration of the STS ICP etcher is shown in Figure 2-11. As

described in the previous sections, the key feature of the ICP system is the separation of

the two RF powers in the system, i.e., the RF power for the generation of etching radicals

and the other RF power for the sample bias. The RF coil at the top of the ceramic

chamber supplies the power to dissociate the species and generate radicals; and the RF

power applied to the bottom electrode provides power for directional etch. It is this power

applied on the bottom electrode that generates a dc bias for the self-bias of the carrier

wafer on which the sample to be etched sits. This configuration allows independent

power tuning for species dissociation and sample bias. More power can be delivered to

the top coil without affecting the self dc bias. As described in the previous section,

compared to a RIE system, the ions in an ICP system are more confined in the plasma

bulk due to the alternate magnetic field generated by the RF power on the coil, resulting

in more collisions of ions with molecules and consequently higher plasma density in the

system. For a processing pressure somewhere between 1 mT and 100 mT, the plasma










density is between 1 x 1011/cm2 and 1 x 1012/cm2, which is two orders of magnitude higher

than in a traditional RIE system. Because of the high density of ion flux onto the sample

chunk, the wafer in the process has to be cooled by helium flow running underneath the

backside of the sample chunk. An effective vacuum system is required to reduce the

residual time of numerous etch by-products in the chamber.



Gas Inlet M
Ceramic Process Chamber

-|Fw ate| Plasma Chambeti
SPice-, Height

Weighted Clamp-. ,,afe Sample
(Optional)

PuIampm PoIT II.MESC Compatible
Isolation Valve
Temperature Controlled
Bellows Sealed Electrode

Helium Cooling



Figure 2-11. Configuration of the STS ICP ASE system. (Adapted from STS webside.)

2.3.2 Silicon Anisotropic Etch

ASE employs Bosch process to achieve anisotropic etch [95]. The essence of the

Bosch Process is the alternate etch and passivation steps in the whole process duration, as

shown in Figure 2-12.

The etching cycle utilizes SF6/02 mix gas flow to etch exposed silicon. C4F8 flow is

used for the passivation of sidewalls of the etched structures. The preference of SF6 to

pure F2 as the reactive gas is due to its lower toxicity. SF6 is dissociated into the reactive

F radical and unsaturated fluorosulfur (SxFy) in the plasma. The added oxygen in the









reactive gas SF6 has two functions in facilitating the silicon etch. The first is to oxidize

the surface of silicon, making the passivated oxide layer on Si surface easier to be

removed by the impinging ions, subsequently allowing more fresh silicon surface

exposed to reactive atomic F. The second function of additional oxygen is to react with

the unsaturated SxFy, enabling more reactive atomic F while depleting polymer-forming

species. In the etching cycle of Bosch Process, three processes the passivation of silicon

surface by 02, the passivation layer removal and the etching of silicon happen

simultaneously. Therefore, the silicon etch by SF6 is isotropic. In a high-aspect-ratio

structural etch, a relatively high dc bias on the sample chunk is necessary to completely

remove the SiOx passivation layer, especially from the bottom of the structure.



F*
FSF*

(a)



nCxFy*



(b)







(c)



Figure 2-12. Alternate etching and passivation in Bosch process. (a) Etch step. (b)
Passivation step. (c) The next etch step.









In order to achieve the anisotropic silicon etch, sidewall passivation of the etched

structure must be performed to protect the sidewall from being etched in the etching

cycle. C4F8 is used in STS ASE process as the passivating chemical. It is dissociated in

the plasma and forms ions and radical species. These species undergo polymerization

reactions and result in the deposition of a polymeric layer consisting of n(-C4-F2-)

molecular chains. This polymer layer is deposited uniformly on the surface of mask,

sidewall of the etched structures and the bottom of the etched trenches. In the following

etching cycle, aided by the ion bombardment, radicals dissociated from SF6 preferentially

remove the surface passivation layer, leaving the polymer on the sidewall of the etched

structures unetched. The anisotropic silicon can be achieved by alternately performing the

SF6 etch and C4F8 passivation continuously. As a result of the periodic etching and

passivation, scallops on the sidewall of etched structures are observed, as shown in

Figure 2-13.




















Figure 2-13. Scallops formed on the sidewall of the etched structures showing the
alternate etching and passivation cycles in Bosch process.









By adjusting the etching and passivation duration and their ratio, different scallop

depth and spacing can be achieved. More directional etch and smoother sidewall can be

obtained at the expense of smaller etch rate and longer process time duration.

2.3.3 Silicon DRIE Characterization

Due to the alternate etching and passivation cycles, more input parameters are

involved in the silicon DRIE than in a traditional RIE system. While the common

multiple input parameters of DRIE have the similar effects on the etching outputs as in

RIE, as shown in Figure 2-4, great attention should be paid to some other variables

specifically existing in an ASE system. For example, the time duration and the ratio of

etching and passivation cycles play important roles in the etching rate tuning and profile

control. In order to control the silicon anisotropic etch more effectively, after some

optimal experiments on the input parameters, we fixed most input parameters, only

leaving the etching/passivation ratio and platen dc bias tunable for the etch of different

structures. The basic silicon ASE recipe is shown in Table 2-4.

Table 2-4. Input parameters in the silicon ASE on STS ICP DRIE system.
Parameters Settings
Coil power 600W
Platen power Tunable
Etching pressure 40 mT (APC position: 84%)
Passivation pressure -20-25 mT
SF6 flow 130 sccm
02 flow 30 sccm
C4F8 flow 85 sccm
Etching time/cycle Varies
Passivation time/cycle Varies


In the backside etch in the developed DRIE CMOS MEMS technology, the main

concern is the surface and thickness uniformity in the etched cavity on the backside. In an

open area as large as 2 mm by 2 mm, the intra-die thickness uniformity can be controlled









within 2.5% and the surface roughness is less than 0.2plm [92]. This satisfies the

thickness uniformity requirement for the accelerometers developed in this thesis work.

2.3.3.1 Etch rate and profile tuning

With other process parameters fixed, the etching rate can also be tuned by etch-

passivation duration and their ratio. The duration of the etch period determines the

general etch rate, and the passivation duration controls the lateral etch on the sidewall of

the structure. Figure 2-14 shows the etching rate as the function of the time duration of

the etching cycle. Other system parameters are fixed as in Table 2-4.


7 8 9 10 11
Etch cycle duration (s)


12 13 14


Figure 2-14. Etch rate per cycle using the recipe in Table 2-4 with varying etch duration.

By reducing the etch time and balancing the passivation duration, very small

scallops can be achieved and consequently smooth sidewall can be obtained. Figure 2-15

shows a side view of a test structure. Smooth sidewall with scallops of 189nm in depth


1.6

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7


.1 .1. .1 .1IIII ,,,,II I ,,,, I ..,,









and 620nm in spacing has been achieved. These achievements are similar to the typical

results reported [96]. They are achieved with a lower etching rate of 2.5 im/min.

In the process, we tune the etch cycle duration from 7.0 seconds to 13.0 seconds

according to the requirement of different etching rate and sidewall profile. For

microstructures in the accelerometers, a maximum etching rate of 4.5 m/min can be used

with an etch/passivation ratio of 13/7 under the other conditions listed in Table 2-4.

The tuning of the platen dc bias also influences the etching rate by changing the

momentum of the impinging ions, which is extremely useful in the etch of structures with

high aspect ratio. For deeper trenches, in addition to the above methods, the etching rate

can be increased further by increasing the gas flow rate of SF6.


0.8 um notch



















Figure 2-15. Smooth sidewall in Si DRIE achieved with a lower etch rate.

Obviously, by changing the etch/passivation time ratio, the sidewall profile can be

tuned. Higher etch/passivation ratio turns out a more negative trench angle; while lower

ratio produces a positive one. Figure 2-16 shows schematically the trends of the sidewall








angle evolution; and photographs of the actual comb fingers after the release etch with

different etch/passivation ratios. The tuning effect is obvious. In the fabricated CMOS-

MEMS accelerometers in this thesis work, the gap between the 4.5 [tm-wide comb

fingers is 2.1 |tm. The aspect ratio of the gap trench ranges from 20 to 25 with the

thickness of the structure being 40 50 |tm. A nearly 900 profile angle can be obtained

by tuning the etch/passivation ratio between 9/5 to 10/5. Figure 2-17 shows the sidewall

profiles of test structures and the finished comb fingers. The SEM pictures of the test

structures were taken after 15 cycles of etching and passivation, as show in Figure 2-

16(a). The thickness of the etched comb finger in Figure 2-17(b) is approximately 45 [tm.

The undercut on each side of the finger sidewall is less than 0.4 [tm.


EIP t(


(a)








(c)


'-ml '


Figure 2-16. The tuning of etch profile by changing the etch/passivation ratio. (a)
Schematic tuning effect. (b) image of the comb fingers after the release etch
with 7:5 E/P ratio, (c) after the release etch with 8:5 E/P ratio, (d) after the
release etch with 13:7 E/P ratio.
























































Figure 2-17. Sidewall profiles of the comb fingers. (a) test comb fingers after 15 cycles of
etching, (b) the actual comb fingers after device release.









2.3.3.2 Microloading and ARDE effect

As mentioned previously, the geometry-dependent effects in the ASE mainly

include macroloading effect, microloading effect and aspect ratio dependent etch

(ARDE). Macroloading effect is characterized by the faster etching rates on the largest

open area. It is also observed that in the whole wafer etching, the patterns on the wafer

edge experience larger etching rate than the same patterns at the center of the wafer.

Apparently this macroloading effect, or called isotropic loading effect, is ascribed to

diffusion-limited chemical reactions in confined spaces [97].

For a through-wafer etch of a 500[tm thick silicon wafer with same patterns

uniformly distributed through the whole wafer, after hours of etch, the difference of the

depth of the etched patterns can be as high as tens of microns. This implies that extra

measurements should be taken to prevent the effects caused by the over-etch on the fast-

etched patterns. For through-wafer etch without carrier wafer, large features on the wafer

edge are etched through first, causing helium gas, which is used to maintain the substrate

temperature in the plasma etch, to leak through these features to the chamber and cause

the system to shut down. Therefore, this macroloading effect is one of the main obstacle

in achieving the wafer level fabrication and package for MEMS devices. In the silicon

ASE in this work, chips of MEMS devices are glued on a 4 inch silicon carrier wafer. To

avoid the macroloading effect, chips are distributed symmetrically in the center area of

the carrier wafer. The rest area of the carrier wafer is covered by photoresist or Kapton

tape which demonstrates good thermal and chemical stability. With very small open area

of silicon on the chips, this approach can reduce the depletion of the reactive radicals in









the sheath region, resulting a relatively uniform etch in the center area where device are

attached.

Microloading effect and ARDE are more related to both RIE and DRIE of smaller

patterns. In general, they refer to the phenomenon that the etching rate scales not only to

the absolute feature size, but also to the aspect ratio of the structure being etched.

Sometimes they are used in ambiguous ways since in both of them the etching rate is a

function of the mask geometry. Although they are based on some similar physical and

chemical principles in terms of affecting the etching rate and trench profile in different

geometrical structures, they differ from each other subtly [98].

Microloading effect is related to the lower etching rate that occurs on high pattern

density regions, which is mainly due to the local depletion of etchant as a result of

excessive load of the etching surface. It can be considered as a micro scale isotropic

loading effect that applies to both anisotropic and isotropic etches. This means that

similar features close together etch slower than a single isolated feature of the same size.

Meanwhile, this also means that when considering uniformly distributed features, big

features etch slower than small ones, due to the higher local density of the exposed

surface thus less supply of etchant. Elaborately designed experiments have been

conducted to detail the effects of microloading effect on the etching rate for different

pattern shape and pattern density [99]. In practice, microloading effect is often considered

together with the ARDE effect in the MEMS device pattern design.

The ARDE effect is the most problematic effect in the fabrication of MEMS

devices with fine mechanical structures. Thus, it is one of the most important parameters

in MEMS design rules. In this effect, the etching rate is purely dependent geometrically










on the aspect ratio of the trenches or holes being etched. Moreover, not only does it affect

silicon etching rate in DRIE, but also causes specific sidewall profile defects like bowing,

bottling and microtrenching [98]. Figure 2-18(a) shows the SEM photography of the

etched trenches on a test structure. The width of the trenches varies from 0.3 jtm to 30jtm.

The experiment was carried out using the same etching recipe as in the actual device

fabrication. Top metal layer of the CMOS composite layers acts as the mask in silicon

ASE. The plot in Figure 2-18(b) shows the silicon etching rate as the function of the

trench width. The sharp slope indicates the higher the aspect ratio, the lower the etch rate.

If the trench is too narrow, the etch process even can not proceed.














(a)


4.5
4-


2 3.
2.5
2
S1.5
1
0.5 (b)

0 0.5 1 1.5 2 2.5 3 3.5
Width of the gap (urn)


Figure 2-18. ARDE effect and its influence on the trench profile and etching rate. (a)
Sidewall profile of trenches with various gaps. (b) etch rate as a function of
gap width.









A large quantity of research works show that the ARDE effect is ascribed to a

variety of mechanisms in RIE and DRIE. These mechanisms include ion shadowing,

differential charging, neutral shadowing, and Knedsen transport of neutrals in which the

diffusion of the neutrals is limited by the geometry [100-102]. To describe these

mechanisms in a simpler way, the conductance of the trench is reduced by the high aspect

ratio, impeding both the transport of the etching species to the bottom of the trench, and

the removal of the etching by-product from the trench. Moreover, the induced charges on

the extruding mask at the trench entrance will also shield the etch-aiding ions from

entering and arriving the bottom of the trench.

Microloading and ARDE effect play extremely important roles in MEMS design

rules. They directly determine the maximum thickness the MEMS device can achieve

once the smallest feature of the device is set. Or, in other words, for a MEMS device with

certain thickness, there exists the limit of the minimum feature size. In capacitive

accelerometers, high sensitivity can be achieved by either reducing the gap between the

sensing comb fingers, or increasing the structure thickness which consequently increase

the proof mass. These two approaches are all limited by the ARDE effect that is

intrinsically determined by the configuration of the ASE system. In practice, the ARDE

effect can be reduced by lowering the chamber pressure. Lower pressure is also helpful in

reducing the bowing effect and the etching notch which happens to the trench sidewall

just underneath the mask. However, lower pressure means the longer MFP and higher

kinetic energy of the ions which is the main cause of the rough surface [103]. The

thermal effect caused by the bombardment of high-energy ions can result in over etch on









fine structures in the lateral direction, especially when the structure is suspended. This

thermal effect will be discussed in Chapter 5.

In the accelerometer design, the gap between the comb fingers should be carefully

chosen based on the ARDE characteristics of the available system for silicon DRIE.

According to the sidewall profile of the test comb fingers the ICP DRIE etcher can

accomplish, as shown in Figure 2-18, we choose the gap of the comb finger as 2. 1 tm to

avoid the apparent bowing and other ARDE caused sidewall deterioration. For comb

fingers of 50tlm thick, the final gap of 2. 1ltm can be achieved with 9010 sidewall, as

shown in Figure 2-19 where only stator comb drives are shown.
















(a) (b)


Figure 2-19. Etching profile of the sensing comb fingers. (a) Stator comb drives after the
device is released. (b) Backside closed-up view of the comb fingers.

2.5 Summary

In this chapter, basic plasma etch technologies are introduced with exemplified

PlasmaTherm SLR770 ECR and STS ICP ASE system. Some physical and chemical

effects in the plasma etches, which are critical to the MEMS device design and

fabrication, are also addressed with experimental results. The design rules for CMOS-









MEMS accelerometers with structure thickness of 50 jtm are extracted, which are

tabulated in Table 2-5.

Table 2-5. CMOS-MEMS accelerometer design rules extracted from the experimental
results
Structural/process Parameters Design rules
Highest aspect ratio 30
Comb finger gap > 2.0 tm
Undercut on suspended structures 0.2-0.3 jtm
Width of dummy pattern for ARDE reduction 3.0 |jm
Selectivity in Si02 etch (Si02/Si) 3.0-4.0
Selectivity in SiO2 etch (SiO2/A1) > 50.0
Selectivity in Si DRIE (Si/SiO2) > 150
Selectivity in Si DRIE (Si/Al) 500-600














CHAPTER 3
IMPROVED DRIE POST-CMOS MEMS TECHNOLOGY

This chapter details the new DRIE post-CMOS MEMS process developed for the

fabrication of CMOS-MEMS integrated accelerometers. As a technological background,

the previous plasma etch based post-CMOS MEMS approaches, including the thin-film

and DRIE approaches, are introduced first. As a practice, a single-axis accelerometer and

a thermally-actuated micromirror were fabricated using the previous DRIE post-CMOS

technology. When used in the fabrication of capacitive accelerometers, the critical

drawback of the previous DRIE CMOS-MEMS process (compared to the improved

process developed in this thesis work) is the simultaneous undercut of the whole structure

when the undercut on isolation beams are performed. This universal undercut enlarges

the comb finger gap and thins the mechanical springs, lowering both the electrical and

mechanical performance of the accelerometers. It is concluded that although the previous

DRIE process is effective in the fabrication of thermal micromirrors where the feature

sizes are as large as 10tm, it is not a good choice in the micromachining of MEMS

devices with much smaller features.

The new DRIE post-CMOS MEMS process was developed to overcome the

shortcomings of the previous technology. It is specifically designed for the fabrication of

capacitive inertial MEMS sensors where the sensing and driving comb fingers are

required to be electrically isolated from each other and from the substrate. Using the new

process, the electrical isolation structures and the functional MEMS structures can be

processed independently, allowing separate control of the fabrication parameters.









3.1 Dry Post-CMOS MEMS: Background

There are two types of dry post-CMOS MEMS technologies: thin-film surface

micromachining technology and DRIE bulk micromachining technology. Both of them

are CMOS-compatible because the CMOS circuitry can be completely protected by the

top metal layer during the post-CMOS micromachining, which consists of dielectric and

silicon plasma etches. Meanwhile, the MEMS structures are defined by the pattern of the

top metal layer, which acts as a mask in the dry etch steps. Therefore, both approaches

are maskless, and no photolithography is needed for front side process. This greatly

simplifies the micromachining and makes the prototyping development cycle much

shorter. In addition to the convenience of the fabrication, the multiple interconnect metal

layers make the wiring of MEMS structures and integrated circuits very flexible. The

fully-integrated metal wiring also helps in reducing the parasitics, allowing high overall

device performance.

3.1.1 Thin-film Post-CMOS MEMS Technology [32]

The process flow of thin-film CMOS-MEMS process with 4 metal layers is shown

in Figure 3-1.

The CMOS circuit region is designed to be covered by the top metal layer. MEMS

structures are pre-defined by the top metal layer or the other interconnect metal layers.

Figure 3-1(a) shows the cross-section of the original chip after CMOS foundry

fabrication, with a passivation layer on top. Two processing steps are performed only on

the front side of the chip. First, the pre-defined MEMS structure is exposed by etching

the SiO2 stack between the interconnect layers, as shown in Figure 3-1(b). This is done

by an anisotropic Si02 plasma etch using an ECR RIE system with CHF3/02 gases, as

detailed in Section 2.2. Next, a silicon DRIE is performed using an ASE technology,









followed by an isotropic silicon etch, which releases the MEMS structures by

undercutting the silicon beneath the MEMS structures. The depth of the anisotropic etch

into silicon controls the gap between the released structure and the silicon substrate. This

gap should be large enough to eliminate the parasitic capacitance between the MEMS

structures and the silicon substrate. In practice, it is normally on the order of 30tlm [104].

A lateral accelerometer with 1 mg/ JHz noise floor exemplifies the types of

MEMS devices fabricated using this technology [34, 84, 105]. This simple fabrication

process yields much smaller parasitic effects as compared to the MUMPs polysilicon

process, and it provides flexible wiring by using the multiple metal layers. However,

there are some drawbacks in this technology, which limit the performance of the

fabricated accelerometer.

First, there is large vertical curling of the suspended MEMS structure caused by the

residual stress gradient existing in the composite SiO2/Al layers, as shown in the example

device in Figure 1-1. For both in-plane and out-of-plane sensing or actuation, this large

vertical curling will result in the reduction or complete loss of the engagement between

comb fingers or other capacitive MEMS structures. Additionally, due to different thermal

expansion coefficients (TEC) of Al and SiO2, the curled MEMS devices exhibit a strong

temperature dependence, which limits their utility. Although particular compensation

technology was employed to reduce the structure mismatch by using a specially designed

frame, the device fabricated using this thin film process still has a stringent size limit

[106, 107].






62





MEMS region
CMOS region
Si02
-- m



Si substrate Polysilicon


(a) (c)
Metal 4 Movable MEMS structures
--m Metal 3
--.- Metal 2 -
~ Metal 1




(b) (d)


Figure 3-1. Cross-sectional view of the thin-film CMOS-MEMS process. (a) Before the
micromachining. CMOS region is shielded by top metal layer. (b) Si02
anisotropic etch. (c) Anisotropic of Si (DRIE). (d) Isotropic etch of Si for
structure release.

Second, for inertial sensors fabricated using this technology, the requirement of

release holes on the proof mass reduces the mass of the proof mass, resulting in a lower

mechanical sensitivity of the sensors. To achieve a capacitance change large enough for

the conditioning circuit to detect, the dimension of the accelerometer may need to be

considerably large, which is in conflict with the dimension limit by the structure curling.

Third, in-plane curling of the thin film structures due to fabrication variations also

limits the maximum size of the device. Although there are some specific processes

designed for low residual stress thin films [108], normally CMOS foundries have very

few, if any, considerations to meet the particular requirements for MEMS devices. The

curling of the MEMS structures can only be compensated to a limited degree by proper









design of both the MEMS and compensating structures. In addition to the collection of

technological data directly from the employed CMOS foundries, systematic post-CMOS

process calibration must be conducted to characterize the process variations and their

effect on the MEMS devices.

Lastly, since the last release step is an isotropic etch, it undercuts the silicon close

to the circuit and structure anchors. The ratio of the vertical and lateral etching rate is

approximately 2:1 [109]. To protect the silicon underneath the circuit region from being

etched away during the structure release, the CMOS circuitry must be placed far away

from the microstructures, especially when a large separation between the microstructures

and substrate is needed. As a result, significant chip area is wasted due to the protection

margin around the MEMS structures. Since the silicon underneath the mechanical

anchors of the MEMS structures is also etched away, the suspension of the mechanical

structures is softened, which results in a lower mechanical performance and less

robustness of the device.

3.1.2 DRIE Post-CMOS MEMS Technology [33]

To overcome the drawbacks of the above thin-film post-CMOS MEMS process,

DRIE post-CMOS MEMS technology was developed to incorporate bulk, single-crystal

silicon (SCS) into the MEMS structures. By taking advantage of the ASE technology,

high aspect ratio CMOS-MEMS structures have been demonstrated.

The maximum aspect-ratio a DRIE system can achieve is an important factor in the

MEMS structure design. It determines the dimensional limit of the structures fabricated

using that DRIE system. Once a lateral feature to be etched is fixed, the maximum

thickness is uniquely defined. Similarly, for a structure with certain thickness, the

smallest gap that can be created between adjacent structures is also uniquely defined.









The DRIE post-CMOS MEMS technology stems from the thin film technology

described in last section. By taking advantage of both the flexible wiring with multiple

metal layers in CMOS technology and the capability of high aspect ratio etching, DRIE

CMOS-MEMS provides an approach to implement thick and flat MEMS structures with

better mechanical performance and device robustness.

Figure 3-2 shows the process flow of the DRIE post-CMOS MEMS technology.

The process starts with a backside silicon DRIE to define the MEMS structure thickness,

as shown in Figure 3-2(a). As described above, the maximum thickness of this structure

is limited by the smallest etching pattern on the front side of the MEMS structure and the

maximum etch aspect-ratio. Next, as in the thin film process, an anisotropic Si02 etch is

performed on the front side of the wafer (chip) to define the MEMS structures (Figure 3-

2(b)). The following step differs from the thin film process in that an anisotropic DRIE,

instead of isotropic Si etch, finalize the structure release by etching through the remaining

SCS diaphragm, as shown in Figure 3-2(c). With SCS incorporated underneath the

CMOS interconnect layers, large and flat MEMS structures can be obtained because the

residual stresses in the Si02/Al thin-films are mitigated by the thick SCS, leading to very

little out-of-plane curling. If necessary, an optional time-controlled isotropic silicon etch

can be added to create compliant mechanical structures which only consist of CMOS thin

films (Figure 3-2(d)). In the accelerometers developed in this thesis work, the fully-

undercut CMOS thin-film layers are employed as the electrical isolation between the

sensing fingers and silicon substrate.
















CMOS region


MIEMS region surface passivation


m-SiO2
-


SCS membrane


metal 4

metal 3

- metal 2
--metal 1










S- CMOS layer



SCS


- -
m -
m -


- -


CMOS thin-film
stack without SCS
underneath


Figure 3-2. Cross-sectional view of the process flow of DRIE post-CMOS MEMS
technology. (a) Backside silicon DRIE. (b) Anisotropic Si02 etch. (c) Silicon
DRIE for structure release. (d) Optional silicon isotropic etch to create thin
film structures.


- -


- -


I









It should be pointed out that in the backside DRIE step to define the thickness of

the MEMS structures, double side alignment is required. However, since normally the

remaining silicon for bulk MEMS structures is on the order of tens of microns, there is no

apparent circuit performance degradation caused by the substrate thinning. Therefore,

there is no strict requirement for alignment in the backside etch.

With the flat MEMS microstructures enabled by the DRIE CMOS MEMS

technology introduced above, reliable sensing and actuation can be achieved. A lateral-

axis angular rate gyroscope with a noise floor of 0.02 /s/I/z has been fabricated using

this technology [70]. In particular, this technology is very suitable for the fabrication of

thermally actuated micromirrors where bimorphs are used to elevate the mirror plate.

Several electrothermal micromirrors have been demonstrated using this technology [37,

110, 111].

3.1.2.1 Example device I: electrothermal micromirror

As a process practice and comparison, two MEMS devices were fabricated using

the above mentioned DRIE post-MEMS technology: a micromirror and a lateral-axis

accelerometer. In the first device, the fabricated electrothermal micromirror can provide

large vertical displacement (LVD) by employing a tilting-angle compensation between

the mirror plate and the actuating frame where the mirror plate is attached.

Figure 3-3 shows a fabricated electrothermal micromirror with LVD actuation in

which the flat mirror with a large area allows high resolution, easy alignment and reliable

scanning in an optical system [111]. In fabrication, when isotropic silicon etching is

performed to remove the SCS underneath the bimorphs, the same amount of lateral







undercut simultaneously applies to both the mirror frame and mirror plate, as shown in
the process flow of Figure 3-2(d). The undercut is shown in the inset of Figure 3-3.
For large structures such as the mirror plate with a dimension of 1mm by 1mm, the
undercut is on the order of several microns, which has negligible effect on the structure
integrity. However, for fine microstructures, this undercut could be disastrous! Thus,
because of this simultaneous undercut, there will be a minimum structure size limit in
MEMS device design if this DRIE post-CMOS MEMS technology is employed.


Undercut on the mirror plate
and frame


Bimorph




/.


V


Figure 3-3. LVD electrothermal micromirror fabricated using DRIE post-CMOS MEMS
technology. The inset shows the undercut on the mirror plate and actuation
frame, which is caused by the undercut of bimorphs.









3.1.2.2 Example device II: single axis accelerometer

The second device fabricated using the previous DRIE CMOS-MEMS technology

is a single-axis accelerometer. Without densely distributed release holes, large proof

masses have been realized for better overall performance. The drawback of this process is

revealed by the accelerometer fabrication, in which severe problems caused by the

simultaneous undercut have been observed.

Figure 3-4(a) shows the lateral accelerometer fabricated using the previous DRIE

post-CMOS MEMS technology. The CMOS technology used was the AMI

Semiconductor (AMIS) 0.5[tm process. The electrical isolation between the silicon

underneath the sensing fingers and the bulk silicon substrate was realized by a CMOS

interconnect stack of 2.4[tm width, as shown in Figure 3-4(b). The designed critical

dimensions of the fabricated accelerometer are tabulated in Table 3-1.

Table 3-1. Dimensions of the microstructures in the test accelerometer
Structures Dimension (m)
Overlapped sensing finger length (L) 100.0
Sensing finger width (w) 4.0
Gap between sensing fingers (g) 2.4
Width of the isolation beam (wi) 2.4
Length of the isolation beam (Li) 4.0
Width of the spring (ws) 3.2
Length of the spring (single fold) 240.0
Thickness of the structure (t) 50.0


When the isotropic etch was performed to undercut the SCS underneath the

isolation beam, at least 1.2 |tm on each side should be etched to completely remove the

SCS. This amount of undercut took place on the sensing fingers and the mechanical

springs at the same time, resulting in an enlarged gap between the comb drives. As a

result, compared with the actual dimensions in Table 3-1, the capacitance formed







69


between a rotor finger and stator finger is reduced by half according to the following

equation,


C =Lh


(3.1)


where so is the dielectric constant of the air and other parameters are defined in Table 3-1.

This reduction of the sensing capacitance caused a lower sensitivity of the accelerometer.

The impendence at the input node of the circuit will increase.


Mechanical spring


frame of stators


Shuttle connecting rotors


(a)


I ;-~-
I 4
I 4


electrical isola

\


bulk -
silicon


tion

' .
.J


vias and contacts

4


SCS on sensing
finger



I L r


Figure 3-4. Fabricated lateral accelerometer using previous DRIE CMOS MEMS process.
(a) Topology of the device. (b) Top view of the enlarged sensing fingers and
the illustrated cross-sectional view of the sensing finger seen from A-A'.


metal 2
-metal 1
SiO2









Additionally, the mechanical performance of the accelerometer will also be

affected dramatically by the silicon undercut on the mechanical springs. The spring

constant of one turn clamped spring in the response direction is given by [112]

k, = Eh(-) (3.2)
L

where E is the Young's modulus of SCS. By undercutting 1.2 |tm on each side of SCS

spring, the actual spring width will reduce to 0.8 |tm, which is only 1/3 of its original

design value. According to Equation 3-2, the spring of the accelerometer will be softened

to only 3.7% of the designed value.

3.2 Improved DRIE post-CMOS MEMS Technology

As can be seen from last section, the anisotropic etch of the last step in Figure 3-3

has a significant impact on both electrical and mechanical performance of MEMS device.

For the fabrication of MEMS devices in which capacitive sensing and actuation is

employed, the isotropic undercut for electrical isolation increases the minimum gap of

comb fingers. It can even completely damage the mechanical structures if the etching

time is not well controlled.

The main task of this thesis work is to develop a microfabrication process to

overcome the drawbacks caused by the last isotropic etch in the previous DRIE CMOS

MEMS process. To avoid the unwanted undercut on other MEMS structures, the

electrical isolation etch should be performed independently to the structure release

process. To realize this idea, we perform the isolation structure etch prior to the device

release step. Another metal layer is used as the mask for the isolation structure etch.

The process flow of the new DRIE post-CMOS MEMS technology developed in

this thesis work is shown in Figure 3-5. A CMOS-MEMS accelerometer is exemplified in









the fabrication. TSMC 0.35[tm technology with 4 metal layers was used for CMOS

foundry fabrication. The process starts with the backside etching to define the structure

thickness (Figure 3-5(a)), which is same as the previous DRIE CMOS MEMS

technology. Then, anisotropic SiO2 etching is performed to expose the regions for

electrical isolation of silicon only (Figure 3-5(b)). Note here top metal layer M4 covers

all other regions on the device except for the isolation structure. An aluminum etch is

then performed to remove the top metal layer M4 (Figure 3-5(c)). Next, a deep

anisotropic silicon etch, followed by an isotropic silicon etch, is performed to undercut

the silicon beneath the isolation beams (Figure 3-5(d)). These beams isolate the sensing

fingers from the silicon substrate. Next, the second anisotropic SiO2 etch is performed to

open the patterns of comb fingers, mechanical springs and other structures (Figure 3-

5(e)). In this step, M3 is used to protect circuit region. Finally, a deep silicon etch is

performed again to etch through and release the accelerometer (Figure 3-5(f)).

For accelerometer fabrication, compared to the previous DRIE CMOS MEMS

process shown in Figure 3-2, in which isolation beams and comb fingers were undercut

by the isotropic silicon etch at the same time, the new process performs the etch steps for

isolation and other structures separately. Therefore minimal undercut of comb fingers can

be achieved, which will greatly increase the sense capacitance and device sensitivity.

This is realized by simply sacrificing the top metal layer M4. It should be pointed out that

this process can be further adapted for the fabrication of MEMS devices in which

independent processes should be performed for different structures.

In this thesis work, two accelerometers have been designed and fabricated using the

above improved DRIE CMOS MEMS technology. The device designs are detailed in









72




Chapter 4. In the 3-axis accelerometer, with a z-axis accelerometer embedded in the



proof mass of a dual axis lateral accelerometer, small size and robust structures are



achieved.


CMOS region MEMS region

Metal 4 (M4)


SiO2

--


m -
- m
m m


m


Thin-film for electrical
isolation


m
m m
- m


mm m
m m


Figure 3-5. The improved process flow of new DRIE post CMOS MEMS technology. (a)

Backside etch. (b) Anisotropic Si02 etch and deep Si etch followed by Si

undercut. (c) Top Al etch. (d) Anisotropic SiO2 etch followed by deep Si etch

and Si undercut. (e) Si02 etch to open microstructure region. (f) DRIE to

release the device.


~
~


m


m


m
m


m m


m m


I I


m :I


m m


II


m m
m


m m









3.3 Summary

In this chapter, thin-film and the previous DRIE post-CMOS MEMS technologies

are introduced followed by two example MEMS devices showing the drawbacks and

limitations of these two processes. A new DRIE CMOS-MEMS process is developed. It

features the independent control of the etch steps for isolation thin films and other

mechanical structures. It is particularly suitable for the fabrication of capacitive inertial

sensors in which sensing and driving comb fingers are isolated from each other and from

the silicon substrate. In general, the new process is applicable to other MEMS devices

where independent processes are required for different functional structures.














CHAPTER 4
DESIGN OF THE INTEGRATED ACCELEROMETERS

Two CMOS MEMS devices have been developed to demonstrate the improved

post-CMOS MEMS technology described in Chapter 3. These devices are a 3-axis and a

single-axis CMOS MEMS accelerometer. For these capacitive inertial sensors, the

improvements of the new DRIE post-CMOS MEMS technology allows comb drives with

larger engaged area and smaller gap, enabling high sensitivities.

In this chapter, the performance goals for the devices are outlined first. Then, the

mechanical and electrical designs of these devices are addressed in detail. The

dimensions of the mechanical structures are determined according to the device

performances, which are predicted based on simulation results. The CMOS technology

used in this work is the Taiwan Semiconductor Manufacturing Company (TSMC)

0.35Otm 4-metal, 2-poly CMOS technology. Low-power, low-noise, open-loop,

capacitive amplifiers are used as interface circuits for the lateral and 3-axis

accelerometers. The interface circuit design is a separate work and can be found in [113].

4.1 Applications of the Designed Devices

The features of the designed accelerometers are their small size and monolithic

integration enabled by CMOS-MEMS technology. What is more important, the improved

DRIE post-CMOS MEMS technology developed in this work allows thick and robust

sensor structures by incorporating SCS in the mechanical structures. These are essential

for the fabrication of high performance capacitive sensors.









Monolithic accelerometers with small size and 3-axis sensing capability are

focused on human body motion sensing for applications in human activity/physiological

monitoring, athletic/sports monitoring, and the motion-triggered functions in portable

electronics. In these applications, the typical acceleration human can generate is less than

1.5 g [114, 115]. In sports, the highest acceleration an athlete can generate is less than 5g,

and the muscle frequency is less than 200 Hz [116]. The minimum acceleration the

human body generates in normal activities is on the order of tens of milli-g. If an

accelerometer with a 3 g full sensing range and 200 Hz bandwidth is used to sense a 30

mg motion, from the following relation,

amn= -JBW (4.1)

where amn, is the resolution of the detection, an is the noise floor of the accelerometer and

BW is the bandwidth, the noise floor required from the accelerometer is 2.12 mg/ I-Hz .

This is a noise floor that even the second generation of commercial MEMS accelerometer

can achieve. Therefore, the human physiological and physical activity monitoring only

requires very low end of MEMS accelerometers.

Much higher performance can be achieved using the improved DRIE CMOS

MEMS technology due to its capability of producing a sensing structure with a large

proof mass. We are pushing the developed integrated CMOS MEMS accelerometers into

higher end applications by targeting a noise floor of tens of ug / /Hz with a bandwidth

of a few hundred Hertz. With this improved performance, as tabulated in Table 4.1, the

applications of the designed CMOS-MEMS accelerometers can be expanded to

engineering monitoring, seismic monitoring, instrumentation and robotics. By optimizing

the structural design, inertial navigation grade performance could be achievable.









Table 4.1. The major specifications of the designed single and 3-axis accelerometers
Parameters (unit) Notation Value
Power supply (V) Vdd 3.3
Modulation signal (V) Vm 1.5
Power consumption per axis (W) P 1x10-3
Full scale of acceleration sensing (g) +2
Bandwidth of the accelerometer (Hz) BW 500
Overall sensitivity (mV/g) S 200
Noise floor for z-axis (ig / IHz) Nz 200
Noise floor for lateral axes (g/g / Hz) N1 50
Dynamic range of z-axis (dB) 60
Dynamic range of lateral axes (dB) __70


4.2 Single-axis Lateral Accelerometer

In the single-axis accelerometer, the external acceleration is sensed by the vertically

parallel electrodes attached to the proof mass, which is anchored to the silicon substrate

through SCS springs. The springs suspending the proof mass are designed in such a way

that they are primarily compliant in one in-plane direction. Compared to the

accelerometer fabricated with the thin film CMOS-MEMS technology [57], the

performance and the robustness of the proposed accelerometer are greatly improved by

the virtue of the SCS incorporated on the proof mass and the sensing fingers and

mechanical springs.

4.1.1 Device Design

The single-axis accelerometer can be simplified as the lumped model shown in

Figure 4-1[112]. The governing equation of the system is [117]

d2x -dx
+b d + kx = maext (4.2)
dt2 dt

which results in the transfer function of






77


X(s) 1 1
H(s) = 1 1 (4.3)
A(s) 2 b k S2 0
s +-s+- s +-s+)
mm Q

where b is the damping coefficient of the proof mass, o) is the resonant frequency and Q

mcO
is the quality factor defined by Q = b. For accelerometers working at a frequency
b

lower than the system resonant frequency, the mechanical sensitivity can be expressed by

dropping the first two terms in the denominator in Equation (4.3), which gives

x 1 m
=2 (4.4)
a,, co k

This is the mechanical sensitivity of the accelerometer. It is interesting to note that

the mechanical sensitivity is inversely proportional to the square of the resonant

frequency.




C
/ k
I //K
Proof mass F 1/k m L
b

AC R


(b)


(a)


Figure 4-1. Lumped model and equivalent electrical circuit of the single axis capacitive
accelerometer. (a) schematic model, (b) lumped circuit model.









A fully differential configuration of the capacitive sensing is employed to reject the

common mode noise. The sensing bridge is formed by wiring the comb fingers in a

common-centroid way, as shown in Figure 4-2. The sensitivity in electrical domain can

be derived as

V, 4C, Vm 1
=^ (4.5)
a, 2C, +C x0 c 2

where V V = Vo, Vo, is the differential output of the capacitive sensing bridge, xo is the

original gap between the sensing comb fingers. Cs and Cp are the sensing capacitance and

parasitic capacitance in the system respectively. In Figure 4-2, C= C1=C2 C3 C4, and

Cp is the parasitic capacitance from the sensing node to the ground.



Vout+ Vout- Vm-


Cia C1b
S C3a- C3b
CCb
C2a 1I- C2b C4b
/ C4a
Cla C4b

C2a --C3b Vm+
C4a Clb Vm-

C3a C2b
C1 -C3
Vout+ Vout-


C, C2 C4 C


Vm+ Vm-
Vm+


Figure 4-2. Fully differential configuration of the lateral accelerometer.






79


Figure 4-3 shows the schematic 3-D model of the single-axis accelerometer. The

configurations of mechanical spring and the sensing comb fingers are also given. The 3-D

model was created using CoventorWare [118], a commercial FEM simulator. The

dimensions of the structures are tabulated in Table 4-2.


sensing fingers
\


springs


driving
fingers


A -


Wa
4


Xo Wf


Figure 4-3. Schematic 3D model and mechanical spring configuration of the single-axis
accelerometer. (a) 3D model of the device, (b) spring configuration.

Due to the large ratio of L,/W, in the configuration, the spring constant of half of

the serpentine mechanical springs, as seen from AA' in Figure 4-3(b), can be simplified

as [119]:









k 1. E(Wb)3 (4.6)
S(n 1)3 2Lb

where n is the number of turns of the mechanical springs, E is the Young's Modulus of

silicon, t is the thickness of the springs. Since there are two sets of the springs on each

end of the proof mass, the overall spring constant k should be the double of what is in

Equation 4.6.

The mechanical resonant frequency of the sensor is then


f =- (4.7)


where m is the mass of the proof mass.

Table 4-2 Dimensions of the lateral accelerometer
Parts (unit) Notation Dimensions
Proof mass area (rn2) A 300*600
Length of single turn spring ([tm) Lb 200
Width of single turn spring ([tm) Wb 4
Length of meander (pm) La 13
Width of meander ([tm) Wa 10
Length of comb finger ([tm) Lf 85
Length of effective comb finger ([tm) Lff 80
Width of comb fingers ([tm) Wf 4.8
Gap of the fingers ([tm) xo 2.1
Thickness of all the structure ([tm) t 50
Number of sensing comb finger pairs N 56


4.1.2 Device Simulation Using Finite Elements Method (FEM)

The mechanical performance of the accelerometer was simulated with

CoventorWare. Folded mechanical springs are employed to reduce the device size. They

suspend the proof mass symmetrically.

The simulated resonant frequency of the lateral accelerometer is 6.05 kHz, which is

within 10% of the value calculated using Equations 4.6 and 4.7. The calculated parasitic









wiring capacitance is less than 60 fF, according to the technical data of TSMC 0.35ltm

process provided by TSMC and the actual layout. While the mechanical thermal-elastic

damping effects are neglected in this system, squeeze-film damping must be considered

for the designed structure with large number of lateral sensing comb fingers. The

squeeze-film damping coefficient of a single pair of the comb fingers is given by [120]


b = 7.2N/t(--)3 (4.8)
xo

where Nis the number of comb fingers; / =1.54x10-6 kg/m/s is the viscosity of the air

under atmospheric pressure at 200C [112]. leff is the engaged length of the comb fingers.

In the designed lateral-axis accelerometer, 4 groups of comb finger arrays, each

consisting of 14 pairs of fingers are used to achieve large sensing capacitance. There are

also 4 groups of driving comb fingers, each consisting of 2 pairs of fingers with the same

dimension as the sensing comb fingers. Therefore, in Equation 4.8, N=(14+2)x4=64.. The

dimensions of the structures in the designed accelerometer are listed in Table 3-1. The

equivalent Brownian noise am can then be expressed as [121]


am =49. (g / z) (4.9)
9.8m

where kB is the Boltzman's constant (1.38x 1023 J/K), Tis the absolute temperature of the

working ambiance and m 12.6 ag, is the proof mass of the accelerometer.

The snap-in voltage can be calculated based on the electrostatic spring softening

effect by balancing the electrostatic spring constant and the mechanical spring constant

[117], this yields


Va = 2 (4.10)
S27C0









where the mechanical spring constant km is approximately 30 N. m.

The designed accelerometer has 13x4 pairs of sensing fingers, wired in a common-

centroid configuration as in Figure 4-2. The modulating voltage is designed as 1.5 V. The

proof mass is assumed as approximately 23 |tg, attributed to the incorporated SCS. The

performance of the designed accelerometer can be predicted based on the above

equations, as tabulated in Table 4-3.

Table 4-3. Predicted performance of the designed single axis accelerometer
Parameters Units Calculated value
Total sensing capacitance fF 440
Device sensitivity (without amplification) mV/g 2.3
Brownian noise of the sensor u/g / Hz 38.9
Resonant frequency kHz 6.05
Snap-in voltage of the sensing comb drive Vsi 15.5
Quality factor__ 1.1


With a designed 40 dB on-chip amplification, the output sensitivity of the device

can be expected as high as 0.23 V / g. The noise floor of the interface circuit is about

10 nV Hz [113]. This single-axis accelerometer is integrated with the 3-axis

accelerometer. Their layout will be shown in later section.

4.3 Tri-axial Accelerometer

A unique 3-axis accelerometer is the primary device developed using the proposed

post-CMOS MEMS technology [86]. The independent silicon DRIE steps for electrical

isolation structure formation and device release allow a precise control of the structure

dimensions and critical profiles. By incorporating SCS in the mechanical spring, robust

devices are accomplished.

As introduced in Chapter 1, there are normally two topologies for dual or 3-axis

accelerometers. The hybrid topology has the advantage of better mechanical performance









due to the optimized mechanical structure. The monolithic integrated approach has much

lower parasitics. In this thesis work, the monolithic integration approach is used for the

design of a 3-axis accelerometer. Moreover, in order to further reduce the device size and

parasitic effects caused by the long wiring path, the z-axis sensing element is embedded

in the proof mass of the lateral accelerometer, as schematically shown in Figure 4-4(a).

As a first-order approximation, the dual-axis lateral accelerometer can be considered as a

regular lateral accelerometer with a solid proof mass. In each sensing direction, i.e. x-axis

and y-axis, it consists of four groups of symmetric sensing and actuation comb fingers

along the two opposite sides of the proof mass. The sensing comb fingers are wired the

same way as in the single-axis accelerometer described in the last section for common

mode rejection. The proof mass is anchored to the silicon substrate through four

symmetric crab-leg SCS springs. The crab-leg springs permit displacement in both lateral

directions, enabling the lateral sensing by the comb fingers on the proof mass.

This compact configuration can improve the circuit performance by reducing the

parasitics at a slight cost of possible cross-axis mechanical coupling. The simulated

results, as presented in the following section, show that the mechanical coupling is

acceptable for this kind of small-sized device designed for portable electronics and

engineering monitoring. Figure 4-4(b) shows the layout of the single and 3-axis

accelerometer, along with other test structures. The dimensions of the designed 3-axis

accelerometer are tabulated in Table 4-4.