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PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE DOUBLEGATE MOSFETS WITH GATESOURCE/DRAIN UNDERLAP By MURSHED M. CHOWDHURY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006 Copyright 2006 by Murshed M. Chowdhury To My parents and Rono ACKNOWLEDGMENTS It has been an honor to work for, and with, my supervisor, Professor Jerry Fossum. Without his patient and inspiring guidance, encouragement, and support, this work would not have been possible. I would like to take this opportunity to express my gratitude to him. I would also like to thank members of my supervisory committee, Professors Scott Thompson, Jing Guo, and Kevin Ingersent, for their guidance and interest in this work. I would like to acknowledge Semiconductor Research Corporation, Freescale Semiconductor, and the National Science Foundation for their financial support. I would also like to thank Freescale Semiconductor and AMD Inc. for measured data. I am grateful to BichYen Nguyen for giving me an opportunity to gain industry experience at Freescale Semiconductor. I have greatly benefited from the interactions with the Novel Device, CMOS and MICA group members. I was extremely lucky to have Leo Mathew and Chip Workman as my mentors there, both of whom patiently suffered my constant demand of data and modelingtips. Also, I am thankful to Aaron Thean and Ben Gu for numerous discussions. I was fortunate to work with fellow group mates, Lixin Ge, JiWoon Yang, Vishal Trivedi, Weimin Zhang, SeungHwan Kim, Zhichao Lu, Siddharth Chouksey, and Shishir Agarwal. I have had many illuminating discussions with them, especially with Vishal, working with whom was an intriguing and beneficial experience. I would like to thank my friend Saif Uz Zaman, and Khairul Alam for riveting conversations on many aspects of device physics. In addition, I would like to thank Saif, and Syed Hussain Rana for reading this manuscript. I acknowledge the unconditional help I received from Tipu bhai, Boro Dulabhai, and Sheuli khala. I was fortunate to have such relatives and friends who are always there when needed. Likewise, my stay here in Gainesville is made easier by the presence of an accommodating community, whose good fellowship helped me to keep my morale high all these years. In particular, I would like to thank Maksudur Rahman, Shahed Nejhum, Sayed Hasan, Avijit Kar, Ziad Saleh, Naheen Aden, Shahed Reza, Reza Nabi, Mustaque Ahmed, and Amas Khan for their camaraderie. Finally, I am indebted to my parents, and siblings, Appi, Rono, Shetu, Rana, Meru and Moury, for their constant encouragement and support. My deep gratitude goes to my parents for their many sacrifices for my education. This work is dedicated to them, and to my selfless brother. TABLE OF CONTENTS page ACKNOW LEDGM ENTS ........................................... iv LIST OF TABLES ......... ............................................ ix LIST OF FIGURES ........ ............................................ x KEY TO ABBREVIATIONS. .......................................... xiv ABSTRACT ........ ................................................. xv CHAPTER 1 INTRODUCTION .......... .......................................1 1.1 DoubleGate MOSFETs; FinFETs .............................. 1 1.2 Compact Model for the DG MOSFET ........................... .. 2 1.3 D issertation O utline ............................................ 5 2 PHYSICAL INSIGHTS ON DESIGN AND MODELING OF NANOSCALE FIN FETS......... ............................... 9 2.1 Introduction ..................................................9 2.2 UFDG Calibration Methodology ................. ............. 11 2.3 Calibration of UFDG to AMD nFinFETs .......................... 16 2.4 Calibration of UFDG to Freescale PolyGate nFinFETs ............... 20 2.5 Calibration of UFDG to Freescale MetalGate pFinFETs .............. 22 2.6 D evice D esign Im plications ................................... 26 2.7 Summary ......... ........ ................ ..... .......33 3 UFDG UPGRADES FOR NANOSCALE FINFETS WITH UNDERLAPS.... 35 3.1 Introduction ......... .. ...... .. ....... 35 3.2 Calculation of WeakInversion Current in UFDG .................... 36 3.2.1 Review of WeakInversion Current Model in UFDG ........... 36 3.2.2 Source/DrainBody Junction Potential ................. .... 40 3.2.3 WeakInversion Model Verification for DG MOSFET .......... 47 3.3 Upgrades in WeakInversion Model for FinFET with Underlaps ........ 49 3.3.1 Model Upgrades ..................................... 49 3.3.2 Verification and Utility .................................. 58 3.4 Upgrades in StrongInversion Model for FinFET with Underlaps ....... 64 3.4.1 Effective Channel Length. .............................. 64 3.4.2 Parasitic Resistance ................ .................. 65 3.6 Conclusion ........ ........................................75 4 CARRIER TRANSPORT IN NANOSCALE FINFETS ................... 79 4.1 Introduction ....... .............................. ......... 79 4.2 Carrier Mobility in the Channel .............................. 80 4.2.1 Electron M obility in nFinFET ............................. 80 4.2.2 Hole M obility in pFinFET ............................ 100 4.3 BallisticLimit Current ............... ..................... 107 4.4 Effects of Parasitics, and Design Implications ................... .. 109 4.4.1 Effects of Parasitic Resistance ............................ 111 4.4.2 Effects of Parasitic Capacitance ........................... 115 4.5 Summary ......... ........................................117 5 SENSITIVITY OF FINFET PERFORMANCE TO GATESOURCE/DRAIN UNDERLAP PROPERTIES .............. .................. 119 5.1 Introduction ............... .................. ........... 119 5.2 Reference FinFET ................ ....................... 123 5.3 Effects of Variation of Film Thickness ........................... 128 5.4 Effects of Variation of Gate Length. .......................... 130 5.5 Effects of Variation of Lateral Straggle ........................... 132 5.6 Effects of Random Doping ................ .................. 136 5.6.1 NSD(y) Randomness ................ ................. 135 5.6.2 NSD(x) Randomness ................ ................. 139 5.6.3 Random UTB/Channel Doping ......................... 143 5.7 WorstCase Scenario ................ ...................... 145 5.8 Summary ......... ........................................148 6 GATE TUNNELING CURRENT IN NANOSCALE FINFETS ............ 150 6.1 Introduction ........................... ......... ..... .. 150 6.2 Compact Model for Gate Tunneling Current in FinFET .............. 151 6.2.1 Tunneling Current Components ................. ........ 153 6.2.2 Tunneling Current Model ............................ 157 6.2.3 Tunneling in AsymmetricGate Devices ................. .. 174 6.2.4 Drain Bias Dependence of Tunneling Current .............. 178 6.3 Model Implementation and Verification ...................... 182 6.4 Effects of Gate Tunneling Current on FinFETCMOS Performance. .... 194 6.5 Sum m ary ......................................... ....... 199 7 CONCLUSIONS AND RECOMMENDATIONS ....................... 200 7.1 Summary and Conclusion. ................................... 200 7.2 Recommendations for Future Work ............................ 204 APPENDIX MISCELLANEOUS UFDG UPGRADES ............................ 207 A. 1 Refining the ModerateInversion Spline ....................... .. 207 A.2 Incorporating NBODY= 0 Option ............................ 212 A.3 Refining the Charge Modeling .............................. 215 A.3.1 Accumulation Charge ............................. 215 A.3.2 WeakInversion Charge ............................. 217 A.4 Refinement of the Velocity Overshoot Model .................. ... 219 A.5 WeakInversion QM Model ................ ................. 223 REFERENCES ........ .............................................. 227 BIOGRAPHICAL SKETCH .............. ..........................236 LIST OF TABLES Table p 2.1 Key UFDG model parameters with brief description .................... 12 3.1 UFDGpredicted ringoscillator delay for an 18nmFinFET ............... 76 4.1 Key UFDG model parameters extracted from the calibration .............. 82 4.2 SCHREDpredicted subband occupation properties ................... 99 4.3 Key UFPDB model parameters used in the study ................... .. 110 5.1 MEDICI and UFDGpredicted characteristics of FinFETs .............. 138 5.2 UFDGpredicted variation of performance of FinFETCMOS ............ 147 LIST OF FIGURES Figure page 1.1 DoubleGate M OSFET structures .................................. 3 2.1 Measured SCEs vs. Lg of CMOS FinFETs ........................... 10 2.2 Partial UFDG calibration to an Lg = 105nm nFinFET ................... 17 2.3 Partial UFDG calibration to an Lg = 17.5nm nFinFET ................. 18 2.4 Partial UFDG calibration to an Lg = 100nm nFinFET ................ 21 2.5 Calibration of UFDG to metalgate pFinFETs. ....................... 23 2.6 Calibration of UFDG to a 75nm metalgate pFinFET ................. .. 24 2.7 Variation of TiN gate workfunction (0M) with drawn length .............. 25 2.8 Schematic cross section (top view) of an undoped FinFET................ 27 2.9 Effects ofunderlaps on the subthreshold characteristics of FinFET ......... 29 2.10 MEDICIpredicted variation of ION and IOFF ......................... 31 2.11 MEDICIpredicted variation of FinFET performance .................. 32 3.1 Boundaries for the solution ofPoisson's equation in the DGMOSFET...... 37 3.2 Lateral potential profile in weak inversion in the channel ................. 41 3.3 Schematic of variation of lateral potential............................. 43 3.4 Comparison of the variation of boundary potential ................... .. 46 3.5 Comparison of UFDG predictions with that of MEDICI in weak inversion ... 48 3.6 MEDICIpredicted surface potential variation between S and D ........... 50 3.7 UFDG calibration to a MEDICIsimulated midgap FinFET. ............. 52 3.8 MEDICI and UFDGpredicted potential profile, 0(y) ................... 54 3.9 Recalibration of the 18nmFinFET ............................... 56 3.10 Calibration of UFDG to a MEDICIsimulated 15nmthick fin FinFET. ...... 60 3.11 MEDICIsimulated electric field vector in the xy plane .................. 61 3.12 Comparison of UFDG predicted LES + LED. ....................... 63 3.13 MEDICIpredicted electron velocity along the channel. .................. 68 3.14 Extracted linear resistance of an 18nmFinFET. ...................... 70 3.15 Comparison of MEDICI and UFDGpredicted IV characteristics ......... 72 3.16 UFDGpredicted variation of ringoscillator delay ................... .. 74 4.1 Calibration of UFDG to weakinversion characteristics .................. 83 4.2 Calibration of UFDG to measured gm/ID2 vs. VGS ................ . 84 4.3 UFDGpredicted stronginversion IDVGS characteristics ................. 86 4.4 MEDICIpredicted variation of gm/ID2 with polysilicon doping ............ 88 4.5 SCHREDpredicted average distribution of carriers ................... 94 4.6 Calibrated UFDGpredicted variation of effective electron mobility ........ 97 4.7 Results of calibrating UFDG to an Lg = 10mm pFinFET ................ 102 4.8 UFDG calibration to the IDVGS characteristics of the 10mmpFinFET..... 103 4.9 UFDGpredicted effective hole mobility ............................. 105 4.10 UFDGpredicted currentvoltage characteristics ...................... 108 4.11 Effects of parasitic resistance on the onsate current .................. 113 4.12 Predicted propagation delays versus parasitic source/drain resistance ...... 114 4.13 Predicted propagation delays versus parasitic capacitance ............... 116 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 6.1 Leakage current components in a CMOSinverter 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 . . . . . . 1 5 2 Tunneling current components in an nFinFET. .............. Dominant tunneling component in a metalgate ............. Tunneling from semiclassical picture ............... ..... SCHREDsimulated conduction band profile ............... Comparison of distance between classical turning points ...... Variation of groundstate electron velocity with bias ......... Schematic of variation of Ec(x) in weak inversion in a MIGFET Variation of IGs/IG with drain bias. ....................... Updated UFDG network diagram ...................... Significance of the higher subbands in FinFET .............. Comparison of UFDG gate leakage model's prediction ....... .......... 154 . . . 156 . . . 159 .......... 164 .......... 166 .......... 169 .......... 176 . . . 183 .......... 184 .......... 186 ........ 188 The lateral S/Dextension doping concentration, NSD(y) ................ 121 Partial calibration of UFDG to MEDICIpredicted characteristics ......... 125 FinFETCMOS circuits used in the sensitivity study ................... 127 Sensitivity of FinFET performanceparameters with the variation of tsi. .... 129 Sensitivity of FinFET performanceparameters with the variation of Lg .... 131 Effects of varying Lg, but keeping Lext constant ....................... 133 Effects of variation of lateral straggle on the sensitivity of FinFET ........ 134 Various lateral doping profiles. ................ ................. 137 Localization of lateral dopants, NSD(y) at different x ................... 141 Medicipredicted IDVGS characteristics ............... ............ 142 TaurusDevicepredicted effects of uncontrolled doping on IDVGS ........ 144 6.13 Effects of DREFF on gate leakage current. ......................... 191 6.14 UFDGpredicted tunneling current through the gates ............... 192 6.15 UFDGpredicted tunneling current in n and pchannel FinFETs .......... 193 6.16 UFDGsimulated transient response of an FinFETSRAM cell ........... 195 6.17 Gatecurrent density at three future ITRS nodes ................... .. 196 6.18 Comparison of UFDGpredicted leakage currents in nFinFET ............ 198 A. 1 Cartoon depicting a typical IDVG characteristics ................. 210 A.2 Effects of UFDG model parameter DG ........................ 211 A.3 UFDG2.4 simulated IDVG characteristics ......... .......... 214 A.4 High field region in the channel of a doublegate MOSFET .............. 220 A.5 Comparison of effective saturated velocity ........................... 222 A.6 Comparison of weakinversion quantummechanical model .............. 225 KEY TO ABBREVIATIONS MOSFET MetalOxideSemiconductor FieldEffect Transistor CMOS Complementary MOS SOI SilicononInsulator FD Fully depleted UTB Ultrathin body SG Single gate SDG Symmetrical double gate ADG Asymmetrical double gate IG Independent gate UFDG University of Florida Double Gate KE Kinetic energy PE Potential energy SCE Shortchannel effect DIBL Draininduced barrier lowering QM Quantum mechanical TEM Transmission Electron Microscopy MC Monte Carlo DOS Density of states SDE Source/Drain Extension Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE DOUBLEGATE MOSFETS WITH GATESOURCE/DRAIN UNDERLAP By Murshed M. Chowdhury August 2006 Chairman: Jerry G. Fossum Major Department: Electrical and Computer Engineering This dissertation focuses on the physics and modeling of nanoscale doublegate (DG) fieldeffect transistors (FETs). The modeling work is incorporated in the University of Florida DoubleGate (UFDG) metaloxidesemiconductor field effect transistor (MOSFET) model that enables predictive device/circuit simulations of complementary metaloxidesemiconductor (CMOS) circuits based on DG FETs. Physical insights on the electrostatics of the DG MOSFET, especially the quasiplanar FinFET, are gained from calibration of UFDG to data obtained from industry. The calibration results show that contemporary FinFETs have gatesource/ drain underlap that makes the effective channel length, and parasitic resistance, bias dependent. Insights from the calibrations, along with numerical simulation results, reveal that the noted underlaps could be used beneficially in scaled FinFET design. The study also pinpoints required UFDG upgrades for nanoscale FinFETs, which are subsequently done and implemented in UFDG. The upgraded model is then used to gain insights on the transport properties of scaled FinFETs by, again, calibrating UFDG to experimental data. The calibration results show mobilities in both p and n channel FinFET are dramatically high compared to those in bulkSi MOSFETs. The high mobilities portend, as shown by UFDG, ballisticlimit current in nanoscale FinFETs, which leads us to the conclusion that channel engineering, like straining the channel, to increase mobility in the FinFET is not needed. The viability of gatesource/drain underlap as a design parameter, in addition to typical device design parameters like gate length, fin thickness, etc., is investigated in terms of the sensitivity of FinFET performance to the variations of process parameters that influence underlap properties; numerical simulators with UFDG aid this investigation. It is found that while variation in the performance of inverterbased circuits, like the ring oscillator, is reasonable, stability of static random access memory (SRAM) shows wide variation in performance for shorter underlap lengths. Finally, a physicsbased compact model for gate tunneling current in DG MOSFETs is developed, verified, and implemented in UFDG to enable reliable prediction of static power consumption in nanoscale FinFET circuits. Model predictions corroborate earlier results that for thinner oxides, presentday silicon oxynitride has to be replaced with highk dielectrics to control static leakage. However, use of underlap can relax the oxide thickness requirement and hence delay the introduction of highk dielectrics in FinFET technology. CHAPTER 1 INTRODUCTION 1.1 DoubleGate MOSFETs; FinFETs In the past three decades, the number of transistors per chip has gone up to a few hundred million, from a few thousand in the early '70s [Boh03]. Such an astronomical increase of transistors per chip is facilitated by continuous scaling of the bulkSi MOSFET, the workhorse transistor of digital integrated circuits. However, as the feature size is approaching sub50nm, the scaling of the bulkSi MOSFET faces stiff challenges coming from increased sourcedrain leakage, increased gate tunneling current, and wide variations in device performance due to uncontrollable channel doping [ITR03]. Hence, researchers are searching for alternatives to the bulkSi MOSFET and its silicononinsulator (SOI) counterpart, the partially depleted (PD) SOI MOSFET. Among the alternative devices considered so far, the doublegate (DG) MOSFET [HisOO] is the most promising candidate to replace bulkSi devices down the roadmap [ITR03]. The DG MOSFET is of the same material as the bulk MOSFET, i.e., silicon, but has a different structure. It offers better control of shortchannel effects (SCE) control [Kim01b] arising from the use of two gates with an ultrathin body (UTB); and high drive current per device width resulting from high mobility due to low transverse electric field and higher inversion carrier density from the two channels. The DG MOSFET need not require drastic changes in the existing CMOS process technology. Figure 1.1(a) shows a schematic of such a MOSFET. The thin channel is sandwiched between the two gates, one of which is buried in the SOI island. When the properties of both gates (gate workfunction, gate oxide thickness, and bias) are identical, the device is called a symmetric doublegate (SDG) MOSFET; otherwise, it is an asymmetric doublegate (ADG) MOSFET. While the electrical characteristics of the channel of the DG MOSFET are promising, high source/drain resistance (Rs/D) due to the thin silicon and difficulty in aligning the two gates cloud this device's future. An alternate and currently a popular version of the DG device called a FinFET is shown in Figure 1.1(b), where the device of Figure 1.1(a) is basically rotated 900. In the FinFET, the gate is "wrapped" over the thin silicon fin that is extended to isolate the gate from the source and the drain. As the gate is one continuous piece, the gate misalignment issue is resolved and the extended fin can be thickened to reduce the high Rs/D as well. For SDG design, the two gates remain connected and a thicker oxide layer is used on top of the fin to electrically isolate the top gate from the channel (body). When this is not the case, the device is called a tri gate MOSFET [Doy03]. If ADG operation is intended, the top gate is etched off to isolate the two gates, and the device is called an Independent Gate (IG) FinFET, such as the MIGFET [Mat04]. 1.2 Compact Model for the DG MOSFET Whatever form of the DG MOSFET is considered (e.g., ADG, SDG, or IG), for successful advancement of the technology, an accompanying compact model is a prerequisite. A compact model will allow the circuit designers to examine and Gate / (b) DoubleGate MOSFET structures: (a) planar DG structure: body is sandwiched between the two gates [Den96]; (b) FinFET structure: the raised source/drain is isolated from the gate by the thin extension. Figure 1.1 exploit circuits employing DG MOSFETs. This requires the model to be fast enough to simulate large blocks of circuits in reasonable times. At the same time, the model should have sufficient physical basis to allow device engineers to faithfully predict device performance, as well as to obtain reliable insights on the devices fabricated, especially when the technology is still in its infancy. A balance between having a fast and physicsbased model is thus imperative; UFDG [Fos04a], a physics/process based compact model for DG MOSFETs from the SOI group at the University of Florida, eloquently maintains the balance. The model is generic in nature, and can be used for SDG, ADG, and IG MOSFETs, as well as for singlegate fully depleted (FD) SOI devices. In UFDG, the 2D Poisson equation (PE) is solved to get the weak inversion (WI) characteristics [Yeh96]. The ID PE is combined with the drift diffusion current equation to obtain the stronginversion (SI) characteristics [Chi01], and the moderateinversion (MI) characteristics are obtained using polynomial splines, the coefficients of which are defined by the physical WI and SI solutions at the MI boundaries. In SI, velocity saturation is accounted for by incorporating a simplified form of the Boltzman Transport Equation (BTE) [GeOl]. Quantum mechanical (QM) effects are incorporated by solving the ID PE and effectivemass Schrodinger equation (SE) selfconsistently [Ge02a]. The SE is solved using a variational method, and the surface orientation effects are included through properly defining the effective masses and valley degeneracies. The transport formalism has a mobility model [Tri05b] that addresses the different scattering mechanisms, and takes care of thermal injectionlimited, or ballisticlike transport. With the incorporation of all these physical phenomena, UFDG is evolving as an essential tool for understanding DG MOSFET technology, as well as for predicting circuit performance, and is now in use in industry and academia alike. 1.3 Dissertation Outline In this dissertation, we start with applications of UFDG where device characteristics obtained from industrial collaborators are used to understand and gain physical insights on UTB DG MOSFET operations by systematically calibrating UFDG to them, which then leads to necessary upgrades and enhancements of UFDG. The upgraded model is then used for further calibration, followed by prediction of circuit performances, and their sensitivity to different process parameters. Since UFDG is a physics/processbased compact model, its key model parameters relate directly to device structure and physics. Hence systematic calibration of UFDG requires knowledge of the DG SOI technology. The model calibration methodology, which is similar to that of UFPDB [Chi01], a physics/ processbased PD SOI MOSFET model, includes tuning of particular parameters based on only a few electrical measurements of devices. The methodology [ChiOl] is expanded and applied in Chapter 2 for preliminary calibration to contemporary FinFET data obtained from two industry collaborators, Freescale Semiconductor and AMD. The insights from the calibrations, along with numerical simulations, are then used in discussing design issues related to nanoscale FinFETs. The preliminary UFDG calibrations to FinFETs done in Chapter 2 reveal new insights into the operation of DG devices, such as different effects of gate source/drain underlap in weak and strong inversion that necessitate model refinements. In Chapter 3, the incorporation of the effects of underlaps in UFDG formalism is discussed. In WI, the underlaps elongate the effective channel length (Leff) that determines the SCEs, modeling of which hence becomes critical. After a brief description of UFDG WI formalism we thus present a simplified yet physical way of incorporating the effects of underlaps in the WI characteristics. In strong inversion, the underlap does not contribute to the Leff significantly, however it does introduce an additional biasdependent component to the parasitic source/drain resistance. So, modeling issues and minimizing the effects of such resistance are discussed as well. With proper accounting of the effects of underlaps, the refined version of UFDG, which also has an upgraded QMbased mobility model [Tri05b], is then used for further calibration to contemporary FinFETs in Chapter 4. The focus now, however, is on the carrier transport in the channel of the FinFET, rather than on the electrostatics (as in Chapter 2). Calibration of UFDG to undoped p and nchannel DG FinFETs shows very high mobilities in contemporary FinFETs, implying smooth {110} finsidewall surfaces, and giving new insights on electron and hole mobilities in DG MOSFETs with {110} versus {100} surfaces. The high mobility portends ballistic transport in nanoscale FinFETs, and indeed simulation of 17.5nm DG FinFETs by UFDG shows ballisticlike currents. The high mobility and ballisticlike current indicate low intrinsic channel resistance in FinFET, which indicates FinFET characteristics could be dominated by the parasitic resistances. The effect of parasitics on high intrinsic drive current of the FinFET is thus studied, and compared with that found in bulkSi devices. With the needed underlaps in nanoscale FinFETs with undoped UTBs, the sensitivity of device performance gets an added constraint: the source/drain dopants in the extension. In bulkSi technology, the source/drain dopants define virtually biasindependent gatesource/drain overlap length and parasitic resistance. But in FinFET, the biasdependent effects make the sensitivity of device characteristics to the variations of extension properties, like the lateral source/drain doping profile or the fin thickness, unique. In Chapter 5, the effects of such variations on circuit performances like RO delay and static noise margin (SNM) of SRAM are studied using MEDICI [Med04] and UFDG. In addition, effects of an unintentional dopant (acceptor/donor) in the channel of an extremely scaled device is studied using the 3D numerical simulator, TaurusMEDICI [Tau04]. While Chapters 25 are mainly concerned with the electrostatic and carriertransport properties in the channel of the DG MOSFET, another important factor, the gate tunneling current, deserves attention. Indeed, the continual increase of gate tunneling leakage with scaling is one of the main factors that initiated the search for a replacement of the bulkSi MOSFET. It is expected that due to the low electric field in the SDG MOSFET the gate tunneling current will be less than that in the bulkSi device. However, with continuous scaling of the oxide thickness, and the unclear direction that integration of highk dielectrics is taking in CMOS technology, the effects of gate leakage current in SDG MOSFETs requires examination. Besides, the electric field in the ADG MOSFET, unlike that in SDG devices, is not low, and hence gate leakage current in the ADG MOSFET can be a serious issue. In Chapter 6, we thus develop a physicsbased compact model for gate tunneling current in generic DG MOSFETs. While all the components of tunneling currents in the nanoscale FinFET are considered, only the most dominant component, which is the electron (hole) tunneling current from the conduction (valence) band in the Si of the nFinFET (pFinFET), is modeled physically. The model is verified with experimental data obtained from two different groups, and then is used to examine the effects of tunneling on the static power of scaled DG devices and circuits. The gate leakage model also necessitated a refinement in the UFDG QM model in weak inversion, which is described in the Appendix along with other UFDG upgrades that stemmed from the work of this dissertation. Finally, Chapter 7 provides a summary of the work done in the dissertation, along with recommendations for future work. CHAPTER 2 PHYSICAL INSIGHTS ON DESIGN AND MODELING OF NANOSCALE FINFETS 2.1 Introduction The attractive features of the FinFET, like better SCEs, higher ION, etc., prompted experimental study of this device and several groups published encouraging results. For example, we show FinFET SCEs as reported in [Yu02] in Figure 2.1, where for a gate length (Lg) of 20nm, and fin thickness (tsi) of 1726nm, draininduced barrier lowering (DIBL) as low as 40mV/V and subthreshold slope, S ~ 75mV/decade are observed. While the excellent SCEs observed with Lg/ tsi 1 are encouraging, from a devicephysics perspective the results are perplexing; mere solution of the PE shows that to have reasonable SCEs (DIBL < 100mV/V, S < 80mV/decade), effective channel length (Leff) has to be more than twice tsi [Kim01a]. The effective channel length is the length of the channel region, resistance of which is modulated by the gate, and hence, defines the gateinduced variation of MOSFET characteristics, i.e., its switching properties. Ideally, Leff should be equal to the physical gate length, Lg. However, from bulkSi experience we know that Leff < Lg due to overlaps or encroachment of the source/drain dopants inside the channel [Tau98]; hence the results in Figure 2.1 imply some novel features of the FinFET, including a possible, unique relation of Leff and Lg. In this chapter, we attempt to calibrate UFDG to the experimental FinFET data to gain insight into the operation of 10 160 .. 160 a ANMOS 0 .A PMOS > 120 120 E t =1726nm Si a) 80 80 E 0 4c 40 40  0 0 0 0 20 40 60 80 100 Gate Length (nm) Figure 2.1 Measured SCEs vs. Lg of CMOS FinFETs, reproduced from [Yu02]. Note the extraordinary S and DIBL obtained with Lg < 30nm and tsi = 26nm. these devices, and to explain the surprising experimental observations. Before discussing the calibration results, we briefly outline the calibration methodology for UFDG. 2.2 UFDG Calibration Methodology Because of UFDG's physical basis, UFDG model parameters are known from process technology, or can be reasonably estimated for initial guesses in the calibration process. The key UFDG model parameters are listed with their default values in Table 2.1. For a complete list of the parameters, please refer to the user guide [Fos05]. Throughout this document, we will show the model parameters in bold face to differentiate them from the corresponding device variables. The parameters not listed here are mostly used with their default values obtained from calibration of earliergeneration SOI technologies [Kris96a], [ChiOl] and have not changed with scaling. The evaluation of model parameters starts with setting a preliminary model card based on the technology information. Model parameters, TOXF, TOXB, TSI, NBODY, NSD, WKFG, WKBG, SO, along with gate length (L), and width (W), can be estimated from the process information. However, process variations can significantly change some of the parameters, like NBODY, TSI, etc. One confusion common in literature related to DG devices, especially for FinFETs, is the definition of W (Figure 1.1). In UFDG, the integrated channel charge that naturally includes bulk inversion [Kim04] is used in calculating the drain current. So, width here for a FinFET is simply the height of the FET (hsi). The more commonly used 2hsi [Yu02], which stems from calculating the current for each channel with the factor 2 taking Table 2.1 Key UFDG model parameters with brief description and default values. Model Description Unit Default Parameter TOXF Frontgate oxide thickness m 3.0x109 TOXB Backgate oxide thickness m 3.0x109 TSI Sifilm (body/channel) thickness m 10.0x109 LES Dynamic sourceextension length m 0 LED Dynamic drainextension length m 0 NBODY Sifilm (body/channel) doping density cm3 1.0x1015 NDS Source/drain doping density cm3 5.0x1019 WKFG Frontgate work function V 4.6 WKBG Backgate work function V 4.6 QMX ID effective mass parameter for QM 1 UO Lowfield mobility for thick TSI cm2*V^*s1 1100./190. (nmos/pmos) THETA Mobility (surfaceroughness model) 1.0 tuning parameter VSAT Carrier saturated drift velocity cmos1 7.0x106 VO Velocity overshoot parameter 0 RD Specific drain parasitic resistance ohm*m 0 RS Specific source parasitic resistance ohm*m 0 SO (n)channel surfaceorientation indicator 1 (1: <100>; 2: <110>) DG Tiedgates indicator 1 (1: Gf and Gb tied; 0: Gf and Gb untied) care of the two FinFET channels, inherently misses an appropriate accounting of the contribution of bulk inversion to the drain current. After setting the preliminary model card, the next step of UFDG calibration is to calibrate the weakinversion IDVG characteristics of the device. The shortchannel effects are defined by the effective channel length (Leff), fin thickness (tsi) and oxide thickness (tox), along with body doping. In nanoscale FinFETs, the body is usually undoped and in UFDG Leff is defined by Leff _LgAL (2.1) where AL is the adjustment, usually positive, due to the gatesource/drain overlap, represented by model parameter DL in Table 1. So, by matching SCEs like S and DIBL from the weakinversion IDVGS characteristics of nanoscale FinFETs, one can finetune the L, DL, TSI and TOXF/TOXB. Once DIBL and S are matched, the WKFG/WKBG can be evaluated by matching the offstate current, IOFF. After evaluating the structural/processrelated model parameters from the weakinversion calibration, calibration of the linearregion, stronginversion IDVGS characteristics should follow. At low drain bias there is no velocity overshoot or selfheating effect, so from the stronginversion, linearregion characteristics, effective mobility, !eff (defined solely by model parameter UO and THETA) and parasitic resistances, RS and RD, can be extracted precisely. However, as RS/RD can effect the extracted mobility, calibrating the IDVGS characteristics directly will not yield an accurate effective mobility, especially for a shortchannel device. To avoid this, we will calibrate gm/ID2, which is nearly independent of RS/RD [Ghi88], [Kri96]. The total onstate resistance, RON, in the linear region can be expressed as VDS RS + RD Leff R + (2.2) ON ID W 2WCof(VGS Vt).eff(UO, THETA) (2 where W, Cof, VGS, and Vt are width, gate capacitance, gate bias and threshold voltage, respectively. The equation is written for symmetric doublegate MOSFETs, but a similar equation can be used for asymmetric DG MOSFETs or bulk MOSFETs as well, by properly changing the gate capacitance value. Differentiating both sides of (2.2) with respect to gate bias, and assuming (VGS ID RS / W) = VGS, we observe that gm/ID2 is independent of RS/RD. So, by calibrating gm/ID2 in strong inversion at low VDS the model parameters UO and THETA can be evaluated uniquely. Evaluating RS and RD then becomes straightforward, and can be obtained by simply forcing the model prediction to match the linear region current. (Application of this calibration methodology is illustrated in Chapter 4.) The stronginversion, saturationregion calibration can be done by tuning VO, VSAT and SELFT in an iterative manner to match IDVD characteristics. Because of the complex interdependence of selfheating on channel current, it's difficult to separate out thermal resistance and capacitances (turned on by SELFT) from velocityovershoot effects (tuned by VO). However, experience with PDSOI devices show calibration in the above manner is usually effective and less time consuming [ChiOl]. The accounting for QM effects, which are gaining importance in short channel devices, classical or nonclassical CMOS alike, in UFDG usually does not need any tuning parameter even though to take care of the uncertainties in effective masses, two model parameters QMX and QMD are left as tunable. However, except for holes in {110} Si, the default values of these two parameters accurately predict the QM effects due to solving the PE and the SE in a self consistent manner [Ge02a]. As the effective masses of holes in {110}p Si are not conclusively known, the above two parameters require tuning for { 110}p Si. For this purpose, calibration of CV characteristics is required. The CV characteristics can also be used to extract TOXF/TOXB; however the advanced gate oxidation process can yield gate thickness with 10% accuracy. For example, if the designed gate oxide is Inm thick, the maximum variation observed in the thickness after fabrication is +A. As FinFETs are left undoped, such small variation in oxide thickness is not reflected in short channel characteristics (unlike bulkSi technology, where large depletion charge, QD, makes the threshold voltage sensitive to tox through QD/Cox). So, for FinFETs, getting the oxide thickness from the designed value is sufficient, and calibration to simple IDVG and IDVD characteristics are enough to evaluate most of the other UFDG model parameters. However, as UFDG does not model polysilicon depletion in the gate, the process is more accurate for metal gate technology, which is the only viable option for undopedUTB DG MOSFETs. With the calibration methodology outlined above, in the next few sections we will present some calibrations of UFDG to both n and pchannel FinFETs along with insights therefrom. 2.3 Calibration of UFDG to AMD nFinFETs We start our calibration with an AMD fabricated FinFET [Yu02] of Lg 105nm. The body of the device is left undoped and S/D fin extension is doped by 0 tilt ion implantation with gate sidewall spacers. The fin thickness varies from 17nm to 26nm, and the extension lengths are of 80nm each. The nitrided gate oxide is 17A thick with poly silicon used as gate material. The UFDG calibration results are shown in Figure 2.2. Even though a good match in weakinversion characteristics, subthreshold slope and offstate current, is obtained for Leff = 135nm, which is 30nm longer than Lg, the stronginversion characteristics are not predicted well. Thus, UFDG calibration is only 'partial'. In Figure 2.2(b), the stronginversion calibration result is shown. With extraordinarily high RS/RD, UFDG predicts the saturation region characteristics well but underestimates the linearregion current. Although the calibration result in Figure 2.2 is far from perfect, we get two valuable insights from the calibration effort; one is that the effective channel length in the fabricated device is longer than the physical gate length, and the other is that the source/drain resistance (Rs/D) is very high and may be biasdependent making it impossible to match both linear and saturationregion currents with a constant RS/RD. In Figure 2.3, we show UFDG calibration results for a shorterchannel length device. Again, we find it difficult to match ID(VGS) in all the regions with constant RS/RD; moreover, in the shorterchannellength device we observe strong inversion Leff, Leff(st) > Lg as well, but it is not equal to weakinversion Leff, Leff(wk) The observation is in contradiction to that typically observed in bulkSi technology where Leff < Lg due to the diffusion of source/drain dopants into the channel. The 108 109 o VDS=0.1V measured data VDS=1.2V measured data 1010 UFDG (Leff=135nm; RD=Rs=200 Qim) 1011 10 12 0.4 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VGS (V) (a) 1 0 4 ............ ..... ... .. . 105 ., ,nooooooooooooooooooooooooooo0 1 106 107 109 109 o VDS=0. 1V measured data VDS=1.2V measured data 1010 / UFDG (Leff=105nm; RD=Rs=675 Qnim) 1011 0o 10n y 0.4 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VGS (V) (b) Figure 2.2 Partial UFDG calibration to an Lg = 105nm nFinFET; tsi = 26nm. In (a) with Leff = Lg + 30nm, the measured weakinversion IDVGS characteristics are predicted well, but the stronginversion curves are not. In (b) with Lff = Lg, and very high, but constant S/D series resistance, the measured highVDs stronginversion IDVGS characteristic is predicted well, but the lowVDS and weakinversion curves are not. 106 10 o VDS=O.1V measured data VDs=1.2V measured data 1010o  UFDG (RD=100 nim, Rs=550 nim) 0.4 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VGS (V) Figure 2.3 Partial UFDG calibration to an Lg = 17.5nm nFinFET; tsi = 17nm. With Leff = Lg + 26.5nm, the measured weakinversion IDVGS characteristics are predicted well; with shorter Leff = Lg + 12.0nm (2)), and very high source series resistance but low drain resistance, the stronginversion curves are predicted reasonably well. explanation of Leff > Lg observed here lies also in the diffusion of source/drain dopants in the channel, however, this time it is due to the lack of it. In FinFET technology, as mentioned earlier, the extensions (Figure 1.1(b)) are not doped directly, rather the ion implanted source/drain dopants are annealed to diffuse them inside the extensions. Apparently, the diffusion is not controlled well enough and an insufficient number of source/drain dopants (NsD) reach the gate edges leaving the extensions near the gate edges practically undoped. Because of the undoped body and the lightly doped/undoped extensions, the Debye screening length (kD) in such FinFETs is long, and gate modulation extends beyond the channel in weak inversion, resulting an Leff, defined as the length over which the gate modulates the carrier, longer than Lg. As the channel carrier concentration increases with gate bias, kD decreases, and carriers beneath the gate screen the carriers in the extensions from the gateinduced electric field. Thus, the Leff shrinks in SI, and hence, even though Leff(st) > Lg, Leff(st) < Leff(wk) as found in Figure 2.3. In strong inversion, besides slightly elongating the effective channel length, the lightly doped portion of the extension also increases the series resistance as evident in the high RS/RD obtained in Figure 2.3. However, the uniqueness of this component of parasitic resistance comes from the variation of carrier concentration inside the extension by gate bias, which gives rise to bias dependence of the noted Rs/D and renders prediction of stronginversion current with constant RS/RD ineffective. 2.4 Calibration of UFDG to Freescale PolyGate nFinFETs To further corroborate and generalize our insights from AMD FinFET calibration we employed UFDG to calibrate FinFETs fabricated at Freescale Semiconductor. In these devices, the extensions are of 100nm each, physical gate length is 100nm, and from TEM measurements fin thickness is found to be 30nm. The calibration results are shown in Figure 2.4. The weakinversion characteristics are predicted well with DL = 18nm, i.e., Leff(wk) > Lg. The fin thickness is found to be 32nm, 2nm thicker than that is found in TEM measurement. The gate work function inferred from the calibration results in a poly doping density of 4 x 1018 cm3, which is significantly less than what is observed in bulkSi technology. Also the gateinduced drain leakage (GIDL), a common feature in devices with overlaps, is absent in the IV characteristics of Figure 2.4, which is consistent with the negative DL found from the calibration that indicates instead of overlaps these devices have underlaps. In strong inversion, this time around we tried to observe the evolution of RS/RD with gate and drain biases by incrementally matching the UFDG prediction with the data as shown in Figure 2.4(b). We find that with the increase of gate bias in the linear region, RS/RD gradually decreases due to the fact that an increase of gate bias increases carrier concentration in the underlap regions. At high drain bias, a constant RS/RD results in a good match, indicating a saturation of carriers in the underlap regions. Note that while RS reduces both the effective gate and drain bias, RD only reduces the effective drain bias, and as long as RD is not high enough to 1 0 3 ........ ,.................. .........,.. 104 105 106 107 r 108 109 1010 1011 1012 ........................... 0.5 0.3 0.1 109 1010 1011 1012 1L. 0.5 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 VGS (V) 0.3 0.1 0.1 0.3 0.5 VGS (V) 0.7 0.9 1.1 1.3 1.5 Figure 2.4 Partial UFDG calibration to an Lg = 100nm nFinFET; tsi = 32nm, and tox=2.47nm. (a) Good match in weak inversion is obtained with DL =  18nm, and (b) the stronginversion characteristics are predicted well with biasdependent parasitic resistance. drive the channel out of saturation, the saturation region current is independent of RD. The asymmetric RS and RD found from the calibration thus are not necessarily physical. Due to the process symmetry, it is more likely that RS = RD in all bias regions. Also, there is a bit of uncertainty in the magnitudes of RS/D as there might be polydepletioninduced degradation of the channel current. However, poly depletion effects do not undermine our RS/D(VGS) conclusions deduced here. Poly depletion effect reduces ID, and it gets worse with increasing VGS [Tau98]. Hence, replicating polydepletion effect with RS/D will require increasing Rs/D with gate bias, which is not the case observed in Figure 2.4(b). So, the trend of RS/D(VGS) observed here is due to the noted underlaps, and the polydepletion could only affect the quantitative interpretation of RS/D(VGS). 2.5 Calibration of UFDG to Freescale MetalGate pFinFETs In Figure 2.5 and Figure 2.6 calibration results of UFDG to Freescale's metal gate pchannel FinFETs are shown. The gate is TiN and SiON is used as gate oxide in the devices studied. The calibrations are done starting from longchannel devices from which transport parameters are obtained and used for the shorter channel one, where RS/RD needed tuning to get the stronginversion calibration. None of the devices have significant SCEs, and the only adjustment needed in weak inversion is for the threshold voltage, which is done by tuning the gate work function. Variation of the TiN gate work function (OM), obtained from the calibration with Lg, is shown in Figure 2.7. We find that with decreasing Lg, (M increases. For the shorterLg FET, we find OM 4.6eV, and for the longerLg ones, 106 '. 1.2V .Data 106 Data  UFDG V DS 0.1 UFDG VDS 0.1 L=10 tm, L=I tm, 108 DL=0, TSI=25 nm, 108 DL=0, TSI=25 nm, UO275 cm2/Vs, UO=275 cm2/Vs, 1010 101010 1012 1012 101 4 ....................... 1014 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 VGS (V) VGS (V) (a) (b) 104 104 S* 1.2 1.2 106 106 VDS =0.1 VDS 0.1V , 108 10  D. Data a 0 SData \ 1 UFDG 1000 UFDG 10\ UFDG L=0.105 gm, L=0.24 gm, DL=14nm, 102 DL=0, TSI=25 nm, 112 TSI=25 nm, UO=275 cm2/Vs, \ :: 107 UO=275 cm2/Vs, RS=RD=450 RS= RD=550 10 14 1..... .... ...... .. .... .. ..... ..... ...... 1014 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 VGS (V) VGS (V) (c) (d) Figure 2.5 Calibration of UFDG to metalgate pFinFETs with gate length of (a) 10pm, (b) 1pm, (c) 0.24pm, and (d) 0.105pm. All the FinFETs have hsi = 90mn, tox = 2nm. Key UFDG model parameters are shown in the figure. IIII 104 Rs=RD=950 S1.2V 106 VDS =0.1V 10  Data 10 UFDG: Leff 97nm tsi=25nm 1012 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 VGS (V) Figure 2.6 Calibration of UFDG to a 75nm metalgate pFinFET. Good match in both the weak and stronginversion characteristics is obtained with a high Rs/ D and UO = 275cm2/Vs. The nonzero ID for VGS > 0.0V is due to gate leakage current. 4.65 4.60 Midgap gate 4.55 4.50 4.45 4.40 .............I.. I I ........ 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 L_drawn (pm) Figure 2.7 Variation of TiN gate work function ( For this technology, Ldrawn = Lg + 10nm1. The midgap gate work function is shown in the dashed line. 1. L. Mathew, private communication, Freescale Semiconductor Inc, 2005. bM ~ 4.4eV. The findings are consistent with the observations in [Yag98], where it was found that the crystal orientation of TiN varies with the gate length, and for shorter channel length the sputtered TiN has a predominant (100) orientation, whereas for longer channel lengths both (111) and (100) orientations are present. The (100) TiN has a work function of 4.6eV. For the (111) TiN it is 4.3 4.4eV. So, in shorterLg devices, the TiN work function it will be 4.6eV and will be less in the longergatelength devices, as observed in Figure 2.7. Note that like the nFinFETs, the pFinFETs here also have negative DL as found from the calibrations to the shorterLg devices, and high RS/D. For example, the shortest gate length studied here, Lg = 75nm, (Figure 2.6) has DL = 22nm. However, the parasitic resistance is unusually high (RS = 950Qjpm) compared to that found in the AMD devices or the Freescale polygate nFinFETs. This could be due in part to the lower mobility of holes, and the lesser number of dopants in the extensions compared to that in nFinFETs, and/or due to the unoptimized contact formation process. 2.6 Device Design Implications Our calibration of FinFETs fabricated in two different plants shows the presence of underlap instead of overlap in these devices. As the channel is undoped, excessive extension doping measures have to be avoided to prevent 'punchthrough', thus underlap might be a common feature in nanoscale FinFETs. To explore the effects of underlaps on device design, we use the 2D numerical simulator MEDICI [MED04] to simulate the idealized structure in Figure 2.8. The structure is idealized in the sense that we assume there are no dopants in the GS/D underlap regions (Les/ toxf Source Front Gate Drain Exte ion Extension tSi Body oxb Back Gate Le ~ Lg Le Figure 2.8 Schematic cross section (top view) of the undoped FinFET used in the MEDICI simulations. The undoped portion of the source (drain) extension is defined as Les (LeD). The devices simulated in this section have mid gap gates with Lg = 18nm, tsi = 10nm, toxf = toxb = tox = Inm, unless stated otherwise. D), and NSD(y) goes abruptly to zero in the extension. Energy quantization effects were turned off during the simulation. The default structure is chosen following the ITRS 32nm node MOS structure [ITR03], with Lg = 18nm, toxf = toxb = Inm. Figure 2.9 shows the effects of increasing underlaps on (a) subthreshold swing, S, and (b) on gate work function, (M, when IOFF is fixed at 0. IpA/pm. As the underlap length increases, the effective channel length increases, which decreases SCEs, and hence S decreases. Also evident in Figure 2.9(a) is (i) that the introduction of underlaps can relax the fin thickness requirements and (ii) that the decrease of S ceases once Les/LeD > 5nm. For example, for S = 85mV/decade, the required tsi = 10nm, with Les/LeD = 0. However, if Les = LeD = 5nm, the same S can be obtained with a thicker fin, tsi = 15nm. Similar conclusions can be made for DIBL as well, as SCEs like S and DIBL vary with tSitox/Leff (to first order), for reasonable short channel effects [KimOla]. So, any increase in the effective channel length will allow relaxation oftsi or tox. As it is difficult to fabricate thin films reliably, underlaps will be a welcome addition to viable FinFET technology. For longer underlap lengths, SCEs are insensitive to Les/LeD (hence, Leff), as for such cases, the coupling of two gates defined by the fin thickness determines the control of SCEs. Hence we note in Figure 2.9(a) that for longer underlap lengths S is almost independent of Les. The variations of (M in Figure 2.9(b) also illustrate that another advantage of introducing underlap in FinFET is that it widens the acceptable range of (M. The prominent gate materials in consideration for FinFET technology are nitrides of Ti and Ta. The choice of nitrogen concentrations in both the gate [Wak01] and the underlying SiON determines the work function of the gate. The use of U LSi  IJIIIII 3 o 100 L= 18nm S9 toxf toxb = lnm nm 0.0 5.0 10.0 15.0 LeS = LeD (nm) (a) 4.70 1 4.65 OFF = 100nA/pm Lg= 18nm, tsi = lOnm 4.60 toxf = toxb nm 4.60  4.55 4.50 4.450.0 2.0 4.0 6.0 8.0 10.0 Les = LeD (nm) (b) Figure 2.9 Effects of underlaps on the subthreshold characteristics of a FinFET illustrated by the IMEDICIpredicted variation of (a) subthreshold swing, and (b) gate work function required to maintain a constant offstate current with varying underlap lengths. underlaps thus can add flexibility in the choice of needed nitrogen concentration in the gate or in the SiON. In Figure 2.10, the variation of ION and IOFF with Les/LeD is shown. Increasing the underlap lengths increases Leff, which reduces the SCEs and hence IOFF decreases exponentially. On the other hand, increasing the underlap lengths increases RS/D and ION decreases too. Note that for Les = LeD < 4nm, increase of IOFF is abrupt and such sensitivity will prevent reliable design with Les/LeD shorter than 4nm. On the other hand, longer underlap lengths increase the resistance, and have a diminishing effect on SCEs. Hence, from Figure 2.9(a) and Figure 2.10, we conclude that the range of useful underlap lengths for the FinFETs considered here is 4 6nm. Indeed, a pragmatic FinFET design, with a Gaussian source/drain doping profile, proposed in [Tri05a], shows that an optimum 18nm FinFET should have 4.5nm of underlap on each side of the gates. Further discussion on such pragmatic design will be presented in Chapter 5. Note that we refrain from taking any quantitative interpretation of ION(Les/LeD) in Figure 2.10. The transport models in MEDICI that are appropriate for bulkSi are not calibrated for thinbody FinFETs and hence, while the effects of parasitic resistances will be reflected properly in MEDICI predictions, uncertainty in the MEDICI channel mobility/velocity saturation model will introduce uncertainties in the predicted ION, thus IoN(LeS/LeD) in Figure 2.10 should only be interpreted in qualitative terms. Figure 2.11 shows the effects of asymmetric underlaps on device performance. In Figure 2.1 l(a) the variations of DIBL and S are shown for increasing 107 108 9 109 10 1010 1011 I 0.0 5.0 10.0 Les=LeD (nm) Figure 2.10 VMEDICIpredicted variation of ION and IOFF of tl Figure 2.8 with underlap lengths LS/D; VDD = 1.2V. 2.0 1.8 1.6 1.4 1.2 0 1.0 0.8 0.6 0.4 0.2 0.0 15.0 ie FinFET defined in 5 10 15 20 25 Les (nm) (a) 0 5 10 15 20 25 Les (nm) (b) Figure 2.11 MEDICIpredicted variation of FinFET performance, (a) SCEs, and (b) ION/IOFF, with the position of the gate in the extension. Simulation is done by keeping the total extension length, Les+LeD constant. Inset in (a) shows the variation of threshold voltage when the gate is moved away from the center (i.e, when Les = LeD = 13nm). 80 I 1 78 76 C & 74 72 70 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 Les for a constant Les+LeD = 26nm. For Les = LeD = 13nm, i.e., when the gate is in the middle with symmetric underlaps on both sides, DIBL and S are minimum. Subthreshold slope, which is defined by Leff, and does not depend on the gate position, except when the gate is very near the source/drain, and spilledover electrons from source/drain reduce gate control by creating an GS/D overlap region like that in the bulkSi devices (the difference between the overlap region in the bulk Si device and the FinFET in Figure 2.1 l(a) is that in the bulkSi MOSFET the overlap region is due to the encroachment of S/D dopants, where as for the FinFET is due to the spilledover mobile carriers from S/D). Similarly, the off state current in Figure 2.11(b) also remains relatively constant with the gate position. The onstate current, however, is maximum when the gate is near the source, understandably so, as the smaller Les, the less the reduction of effective gate bias by Res, the resistance due to Les. The optimum FinFETs, thus, should have Les > LeD. 2.7 Summary We have presented insights from calibrations of UFDG to FinFET data that explain the good shortchannel effects observed in data with Lg tsi. The calibration results show that the GS/D underlap in the nanoscale FinFETs elongates Leff and introduces a biasdependent component in the parasitic RS/D. We also found that due to the underlaps, GIDL is absent in the FinFET. Design issues with the underlaps were explored through numerical simulations, which show that longer LeS/D is needed to minimize IOFF sensitivity to LeS/D variations (consistent with the finding that to get good SCEs Leff > 2tsi [Yan05]). Conversely, to keep the resistance low, Les/LeD should be minimum. The advantage of underlaps in relaxing the fin thickness and the gate work function requirement was illustrated. Also, probable FinFET design with asymmetric underlaps was discussed, and it was concluded that having a longer underlap length in the drain side is optimum, as shorter underlap length in the source side reduces the reduction of effective gate bias due to the resistive drop across the underlap. The calibration results also pointed out some required upgrades in UFDG, namely modeling of biasdependent Leff and Rs/D due to underlaps. In the next chapter, we will deal with such modeling issues, as well as further applications of UFDG, with the effects of underlaps incorporated. CHAPTER 3 UFDG UPGRADES FOR NANOSCALE FINFETS WITH UNDERLAPS 3.1 Introduction As observed in the previous chapter, the presence of gatesource/drain underlap, with an undoped UTB, introduces variation of the gatecontrolled area with bias that gives rise to a biasdependent effective channel length, and adds a non ohmic component to the parasitic resistance of the FinFET. In this chapter, our focus will be on the analysis and UFDG modeling of such novel features and their effects on FinFET characteristics in both weak and strong inversion. The weakinversion discussion will be concerned with a modification of the weakinversion current formalism that is compatible with compact models, while the stronginversion discussion will center around the properties of the parasitic resistances. In a compact model for a MOSFET, the weakinversion current is calculated neglecting drift current, and the potential profile in the channel is obtained by solving the 2D Poisson equation (PE) using the depletion approximation. For the FinFET, the gatecontrolled region extends beyond the channel and presents different boundary conditions for the PE, which requires extension of the compact model developed for conventional DG MOSFETs. Hence, we first check the applicability of UFDG for predicting weakinversion characteristics of nanoscale FinFETs, and then the required model upgrades will be presented. Before delving into the FinFET weakinversion characteristics, we first briefly review the weak inversion current model in UFDG. 3.2 Calculation of WeakInversion Current in UFDG 3.2.1 Review of WeakInversion Current Model in UFDG UFDG solves the PE in weak inversion assuming negligible carriers in the channel [Yeh96]. The effective channel length Leff in the model is the length over which the solution of PE is sought. In DG MOSFETs, Leff is defined by (2.1), where the channel within Leff is completely covered by the gate. The 2D PE, a2 a2 qNA 2 (x, y) + 24(x, y) (3.1) dx dy s with the potential ) referenced to a hypothetical neutral body, is subjected to the boundary conditions shown in the schematic crosssection of a DG MOSFET in Figure 3.1(a). The channel is surrounded by the gate in the transverse direction, and by the highly doped source and drain in the lateral direction. With the gate over the entire effective channel length, the boundary conditions in the transverse direction are clearly defined by the gateinduced electric fields, Seox sf6y) (VGfJ V FBf) 0 = _E (y)= f ) FB) (3.2) xix =0 sf a t =s oxf SE ox (VGbS FBb) sb 0 I = E ,(y)=  = tsi s oxb where VGf/bS is the front/back gate bias, eox/s is the oxide/silicon dielectric constant, VFBf/b is the flatband voltage of the front/back gate, Esf/b is the front/back surface the electric field, and {sf/b is the front/back surface potential. In the lateral direction, the boundary conditions are defined by the source/drainchannel builtin potential. The inherent assumption here is that source/drain doping is infinite (i.e., the potential Front Gate Esf(y) Channel  AL/2 (O,Leff) y AL/2 (0,0) Ct . (tsiO) 1 V Front Gate Esf(y) Channel (ii) Esb(y) Back Gate LeD I I I I (O,LeffLeD) f (0Leff) y I 7 e + v < . '(iii) ] (tsi,Leff) Figure 3.1 Boundaries for the solution of Poisson's equation in the DG MOSFET. (a) In a conventional DG MOSFET the boundary conditions are well defined on all four sides by (3.2) and (3.3). (b) In an undopedUTB FinFET, with undoped extensions as part of the channel (of length LeS, and LeD), the boundary conditions are not well defined. From y = Les to Les+Lg, the electric fields are easily obtained from (3.2), but from y = 0 to Les, or y = (Leff LeD) to Leff, the electric fields come from the fringing effect of the gates that complicate the solutions of PE inside the box [(0,0);(tsi,Leff)]. Leff No Esb(y) S(tsi,Leff) Back Gate ( I  (0,Les) Kk7F (0,0) (t0i (tsiO)  ' Y I eSI drop across the quasineutral S/D region is neglected), which gives a bias independent potential at the boundary and defines the boundary values for the PE in the y direction as Y(x, 0)= b (3.3) Y(x, L)= b + VDS. A solution of (3.1) subject to the boundary conditions in (3.2) and (3.3) is [Yeh96], (x,y) sinh(yL )[(K + b + VDS)sinh(yy) + (K + b)sinh(y(Leffy))] K (3.4) eff Here, y is the constant (in y) inverse length scale, which indicates the severeness of the SCEs in the channel at any x, and is given as + C of+ C of 2yO Co C y(x) = 2 ; oo = (35) I +x of 2 2 o s ox Yb Cb Also in (3.4), K is the ID potential, found from the solution of the ID PE in the vertical direction and is related to the gate biases as K =y C(VFBb VGbS)B(VGS VFBbf 2+ (3.6) [C("Fb "O 2e where the structuredependent constants are defined as B = B +y2(x) Cf+ B x2; B0 BBs o C C Cof + Cof Cob Cb tb 1+ b C (1+(x)2); C tb21+2 1 C = Co(I + (Yx)2 c = tb2 1 +2COf (3.8) The minimum potential along y at any x, Om(x), is obtained by solving for y = ym such that the lateral electric field is zero. From (3.4) we find Ey andym as = sinh(Lff) [( b + VDS)cosh(yy) (K + )b)COsh(y(Leff ))] y atanh 1 K + b+VDS tanh(yL eff) m y cosh(yLeff) +b e (3.9) (3.10) We note that, when VDS = 0, ym = Leff/2. Once the minimum potential, Om is found, the diffusion length, Le in the channel is calculated by, with Le Leff LS LD L 2[1b m m L S y = 0 a = (3.11) (3.12) and and (3.7) 2[,b m + VDS] (3.13) y=L Iy= Leff In (3.12) and (3.13), the lengths Ls and LD refer to the depletion lengths inside the channel near the source and drain, respectively, as illustrated in Figure 3.2. The channel current is assumed to be due to diffusion only, and is approximated as Iwk qD 1exp DS (3.14) Here, Q(Ls) is the integrated carrier density at the virtual source and is exponentially dependent on om [Yeh96]; q, VT, Dn, are electron charge, thermal voltage and diffusion length, respectively. So, the current is mainly dependent on two variables, exponentially on (m and linearly on Le 1. In UFDG, the channel is separated into multiple strips along x, and (3.14) is used to calculate the current in each strip [Tri05b]. The total current is then obtained by summing up the contributions of all the strips. 3.2.2 Source/DrainBody Junction Potential There are few assumptions in the above model for the weakinversion current in DG MOSFET. One is the boundary condition (3.3), which says the potential at y = 0 is fixed at Ob, assumed to be the builtin potential Vbi and approximated as (for a ptype body), E U N b + kT n (3.15) b 2 q n Figure 3.2 Lateral potential profile in weak inversion in the channel of a typical DG MOSFET. The diffusion length Le is obtained by subtracting Ls and LD, which are calculated by extrapolating the electric fields at the source/ channel (y = 0) and drain/channel (y = Leff) boundaries, from Leff. i.e., the model assumes the Fermi level in the source is aligned with the source conduction band. In (3.15), Eg is the silicon band gap, ni is the intrinsic carrier concentration, and k is the Boltzman constant. For a typical doping density of 1x1020cm3, b can be 2kT/q higher than that predicted by (3.15) if FermiDirac (FD) statistics are used. Besides the inherent approximation of MaxwellBoltzman (MB) statistics, (3.15) also assumes that there is no spatial variation of carrier density inside the source/drain. In reality, however, there will always be some carriers spilling over into the undoped channel from the source, and the potential profile in the source will be a function of gate length, film thickness, and biases. A typical profile of )(y) across the sourcechannel boundary is plotted in Figure 3.3 showing the deviation of b from Vbi, the potential inside the source where the carrier density equals the doping density. The inaccuracy, if any, introduced by the assumption in (3.15) that b = Vbi needs examination before we incorporate the effects of GS/D underlap. To estimate the potential at the sourcebody junction accurately, one needs to solve the ID PE inside the source, 2 d2 (ns N) ,(3.16) dy s where ND is the source doping density and ns is electron concentration in the source. In nearequilibrium, for an undoped body, ns can be expressed assuming MB statistics as [Tau98], n iexp (3.17) O(y) y Figure 3.3 Schematic of variation of lateral potential (solid line) across the source channel boundary in a FinFET with abrupt doping profile (dashed line). Due to finite depletion layer inside the source, (b < Vbi. Using (3.17) in (3.16) we find, d2 qND( Vbi) 2 Iexp 1 (3.18) dy2 T where Vbi is the ) where n = ND. Integrating (3.18) once, and using = o at y = ys, dy we get d4 2 qV'ND ( i' b (d j xP V 1 bi (3.19) dy) s T ) VT ) At the boundary (y = 0), the electric field and potential are continuous, so solutions of (3.1) and (3.16) are nearly the same there. Thus equating (3.9) and (3.19) at y = 0 we can get a refined expression for Ob, but the solution requires numerical evaluation. A simpler way is to employ the depletion approximation inside the source and neglect ns in (3.16). Then the potential at the boundary, in terms of the electric field, is c E2 bb =bi 2qN (3.20) Eb is the electric field at y = 0 and can be approximated from (3.9) for low VDS as Eb y(K + b)tanh( (3.21) Replacing Eb in (3.20) by (3.21), and solving the resultant quadratic equation we get ab as b 2 [ (2aK + 1)+ J(4K + 4Cbi + 1)] (3.22) 22a where a = 2tanh f is a constant in y, and relates the dependence of b on the device parameters, i.e., ND, Leff, and tsi. Note that in (3.22), Ob depends on the gate bias through K, but the variation is negligible in the weakinversion region. Figure 3.4 shows the variation of Ob from (3.22) with tsi and Lg. As is evident, Ob is independent of Lg until the length becomes too small, and punch through increases the density of carriers in the channel (and at the boundary, increasing b). With decreasing tsi, Ob decreases as thinner tsi enhances gate control reducing SCEs. In other words, in the 2D PE, E = (+ ), the gradient of the electric field along x increases with decreasing tsi, and thus decreases n (so too does 0 through (3.17)), for a constant gate length and drain bias. The prediction of (3.22) is in good agreement with that of MEDICI, as shown in the figure, except for thin films, where in the middle of the film the assumed depletion approximation is inaccurate. Also in the figure, the variation of 0b with a is shown in the inset. As a goes to zero (which can happen when ND ) oo), 0b approaches Vbi as assumed in (3.3). Note that for a pragmatic FinFET having tsi > 8nm, undoped body, and Leff (= Lg here) > 2tsi, Ob is around 0.55 V in Figure 3.5, as will be predicted by (3.15), 0b SEg/2 = 0.55V. The prediction by (3.15) is close because the deviation of b from Vbi is compensated by the use of MB statistics (instead of FD statistics), which underestimates the actual potential for source doping 1x1020 cm3. So, use of (3.15) Lg (nm) 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 0.60 0.55 0.50 0.45 Q 0.40 e 0.35 0.30 0.25 0.20 I 0.0 5.0 10.0 tsi (nm) 15.0 Figure 3.4 Comparison of the variation of boundary potential as a function of film thickness (tsi), and gate length (Lg) as modeled by (3.22) with that of MEDICI. For the first case Lg is set to 18nm and for the latter tsi = 10 nm is used. VGfS = VGbS = 0, WKF = WKB = 0, VDS = 50mV, toxf = toxb = Inm, ND = 1x1020cm3, and NA=1.3x1010cm3 are used. Inset shows the variation of Ob with a in (3.22); as a  0, b  Vbi works fine for typical FinFETs, although it does not capture the dependence of Ob on structural parameters. (In the next section, introduction of a new parameter SCEB will be discussed, which will help in removing the uncertainties introduced by (3.15), particularly for undoped UTBs.) 3.2.3 WeakInversion Model Verification for DG MOSFET Figure 3.5(a) shows the calibration of the UFDG weakinversion model to MEDICIsimulated DGMOSFET characteristics. The excellent match corroborates the model validity for DG MOSFETs. Figure 3.5(b) shows the comparison of UFDG predicted 0(y) with that of MEDICI for the same device. Note that both the curves have identical (m and will yield identical Le. Because the weakinversion current is mainly dependent on these two parameters, ym, and Le, as long as the calculation of these two are correct in (3.14), UFDGpredicted channel currents, and hence SCEs, will be valid. For conventional DG MOSFETs such accuracy in determining (m and Le is obtainable by using the exact physical parameters directly in the model. But for the undopedUTB FinFET the model is not directly applicable since the boundary condition in solving the PE is different. Figure 3.1(b) shows the boundaries within which the solution of the PE is sought. While the boundaries in the y direction are still well defined, the boundaries along the x direction in the extensions are defined by the fringing fields from the gates, which invalidate the use of (3.2) there. An exact solution for such a system will involve solving PE in regions (i), (ii) and (iii) in Figure 3.1(b) and equating the solutions at the boundaries of region (i) and (ii), and (ii) and (iii). Such an exact approach is complex and not favorable for compact models. As an alternative, we employ our insight from UFDG 103 VDS=1.0V 105 50mV 107 H 109 1011n MEDICI  UFDG 1013 0.2 0.1 0.0 0.1 0.2 0.3 0.4 VGS (V) (a) 0.8 0.7 V DS = 50mV 0.6 o****oooo *,OO 0 0.5 S0.4 0.3 0.2 M MEDICI 0.1  UFDG 0 .0 . ... .... .. .... . 35 40 45 50 55 60 65 70 75 80 y (nm) (b) Figure 3.5 Comparison of UFDG predictions with that of MEDICI in weak inversion, (a) IDVGS characteristics, and (b) potential (0) along the channel at x = tsi/2. The device is an undoped, midgap DG MOSFET with Lg = 18nm, tsi = 7nm, and toxf toxb = Inm. The relevant UFDG model parameters are WKF = WKB = 0.007, NSD = 1x1020cm3, DL = 0.4nm, and NBODY = 1.3x1010cm3. For (b) the gate bias is fixed at OV Note that in (a) the DL needed is nonzero, due to the uncertainty in the mesh size of MEDICI; the difference of 7mV in the work function can be attributed to the slight discrepancy in the values of intrinsic device parameters, like ni, Eg and silicon affinity, X, used in UFDG and MEDICI. weakinversion calibration that if we can get the correct 0m and Le for this structure (Figure 3.1(b)) by using an equivalent structure like that of in Figure 3.1(a), we can still reliably predict the performance of FinFETs. In the next section, the UFDG model's validity for FinFETs is examined and required upgrades are described based on the insights gained from the MEDICIsimulated FinFET characteristics and UFDG calibrations to those. 3.3 Upgrades in WeakInversion Model for FinFET with Underlaps 3.3.1 Model Upgrades The nanoscale FinFET (Figure 3.1(b)) structure, from source to drain, is basically a gated nin structure where the undoped portion (undoped/moderately doped extensions plus the channel) is flooded with electrons spilled over from the highly doped source and drain. The application of gate bias in the weakinversion region modulates the carrier concentration over the entire channel in the process of establishing a driftdiffusion balance. Moreover, as the low carrier concentration in the weak inversion is not effective enough to screen the gateinduced electric field, the gate also modulates the carriers in the undoped extensions. Figure 3.6 shows the MEDICIpredicted variation of potential and electron concentrations between source and drain with gate bias in an undoped nanoscale FinFET for both low and high drain biases. As evident in the figure, in weak inversion gate modulates the carriers in the extensions as well as in the channel. The Debye screening length XD is given as, 50 06 0 VGS=1 2Vi l l s 1020 1020 'Ls L LeD 1020 05 OOv 0 10 02V 1018 0 10170 00 V1 E 101 0 80 0 1016 00 Ol 0 0 102 1 10 10 030 1 0 1 L L Le 102 102 0 10 y (Cm) y (Cm) (a) VDS = 0.3V (c) VDS = 0. V 04l 1 02 1020 1020 1020 16 0Les I Lg Le 1013 U 10 S101 10 01 2 Vs~ 210 107 10 10S D0 Lg 0810 10o0 Sl1 07 ,I 1e0 2 10 10 v 10/ 1012 o 05 10/ 02 loll 10/ VG2 05 005 008 011 014 017 020 023 005 008 011 014 017 020 023 y (vm) y (Vm) (b) VDS = 1.2 V (d) VDS = 1.2 V Figure 3.6 IVIEDICIpredicted surface potential variation between the S and D contact regions of an L = 105nm DG nFinFET (Vt 0) for VGS varying between weak and strong inversion, and for (a) low and (b) high VDS; tsi = 26nm. Electron density (at x = 0, tsi) variation corresponding to the potential variation in (a) and (b) is shown in (c) and (d), respectively. The entire S/D finextension regions (Les = LeD = 25m) were left undoped, as was the body/channel. The S/D doping profile is abrupt as shown by the dotted curve. dotted curve. VT7 nD = . (3.23) i qn In weak inversion, usually the carrier concentration n < 1x1016 cm3, which makes kD > 40nm. Such a long screening length allows the gate bias to alter the carrier concentration beyond the channel, inside the undoped part of the extensions. As the carrier concentration goes up near the source (or drain), the gateinduced carrier modulation ceases. If the effective channel length Leff is defined as the length over which the gate modulates the carriers, for nanoscale FinFETs it becomes Leff = LeS +L + LeD (3.24) where Les and LeD are the undoped parts of the extensions near the gate edges as shown in Figure 3.6 and Figure 3.1(b). Comparing (3.24) with (2.1) we find that AL = (LeS+ LeD) (3.25) if the UFDG model is applicable for such FinFETs. To check this conjecture, we calibrate UFDG to MEDICIsimulated FinFETs. The gate length of the device chosen for simulation is 18nm, toxf = toxb = Inm, and tsi = 10nm; it has a midgap gate and its body is left undoped. In Figure 3.7 the calibration results are shown. The parameter DL (corresponds to AL in (3.25)) in UFDG is tuned to match the short channel effects. For (Les+LeD) = 8nm structure, to get an excellent match in SCEs (DIBL and S), DL is tuned to 6.2nm (Figure 3.7(a)) and for (Les+LeD) = 10nm, the required DL = 10.4nm (Figure 3.7(b)). 105 VDS1 v MEDICI  UFDG 5 mV 109 1011 10 13 0.2 0.1 0.0 0.1 0.2 0.3 VGS (V) (a) 106 MEDICI VDS= 1.0  UFDG 50 mV 10 1010 1012 10 14 . ., . . . 0.2 0.1 0.0 0.1 0.2 0.3 VGS (V) (b) Figure 3.7 UFDG calibration to a MEDICIsimulated midgap FinFET with (a) Les = LeD = 4nm and (b) Les = LeD = 10nm. Other device/model parameters are Lg = 18nm, tsi = 10nm, toxf = toxb = Inm. UFDG model parameter DL is tuned to (a) 6.2nm, and (b) 10.2nm. Quantummechanical effects are turned off in both the simulators. Les (LeD), as defined in Figure 3.1(b) as well as in MEDICI simulations, is a rather technological definition, i.e., it is defined as the distance from the gate edge to the plane, where the source (drain) doping falls abruptly to zero. However, Les (LeD) in (3.24) defines the source (drain) extension length over which the gate effectively controls the carriers. From Figure 3.6 it is evident that near the source (drain), gate does not modulate the carriers due to the shorter screening length there. Thus, (3.24) can be modified as Leff = LeS + L + LeD 2D(nb), (3.26) where XD(nb) is the Debye length corresponding to the carrier concentration at the boundary, nb. The typical value of kD is lnm, corresponding to an average doping density of lxl019cm3 near the source/drain. Considering this, for shorter Les and LeD in Figure 3.7(a), (3.26) holds true. That is, when the undoped extensions are smaller (4nm), UFDG is applicable to FinFET structures with its DL indicating the amount of gate underlap. But for longer Les and LeD, the DL required for predicting similar SCEs is almost half of Les + LeD and does not correlate directly to the underlap lengths. Before drawing any further conclusion, we look into the calibration results again in Figure 3.7. It is clear that while UFDG is predicting the SCEs well, it is overestimating the magnitude of the channel current Iwk, which is more evident for the longer underlaps. To investigate further we look at the potential profile along y, predicted by both UFDG and MEDICI. Figure 3.8 shows the potential profile for the device in Figure 3.7(a) at low drain bias with VGfS = VGfS = VGS = OV. While the 0.8 SMEDICI 0.7 UFDG 0.3 0.2 VGS = OV 0.2  VDS = 0.05V 0.1 Les Lg LeD 35 40 45 50 55 60 65 70 75 80 y (nm) (a) I II ) / 0.65 Les Lg LeD 0.45 0.35 MEDICI 0.25 UFDG VGS = OV VDS = 0.05V 0.15 0 .0 5 . . . . .. .. . 35 40 45 50 55 60 65 70 75 80 y (nm) (b) Figure 3.8 MEDICI and UFDGpredicted potential profile, 4(y) (a) along the channel of the FinFET simulated in Figure 3.7(a), and (b) potential profile for the same device as in (a) with the boundary value Ob taken from the MEDICI simulation rather than that predicted by (3.15). Inset in (a) shows the zoomedin profile near the metallurgical boundary. UFDGpredicted profile closely follows that of MEDICI, the minimum potential predicted by UFDG is a few millivolts higher than that of MEDICI, which results in the overestimation of UFDGpredicted Iwk, as from (3.14) log(Iwk) ,m. This overestimation is independent of gate bias, which is evident from Figure 3.7, where a shift in the voltage axis towards the right for UFDGpredicted characteristics will yield an exact match of Iwk between MEDICI and UFDG simulations, for all the bias points in weak inversion. The expression (3.4) for om using ym = Leff/2 for low VDS (from (3.10)), after some algebraic manipulation becomes om = (K +b)sech(j ) K. (3.27) In (3.27) the bias dependence comes from K. Then, the only parameter that gives a biasindependent variation of Om is )b, as dm =sech Y (3.28) db 2 As shown in the inset of Figure 3.8(a), the boundary value of Ob for the UFDG simulation is higher than (as predicted by (3.15)) that of MEDICI simulation. If we use the MEDICIpredicted Ob in the UFDG model, and compare the two profiles of Figure 3.8(a), as shown in Figure 3.8(b), we find that the minimum potential is identical for the two cases. So, the mismatch in Iwk in Figure 3.7 is due to the use of inaccurate Ob. To check this conclusion further, the calibrations in Figure 3.7 are repeated in Figure 3.9, where Ob used in UFDG is extracted from the corresponding MEDICI simulation. Excellent matches in Iwk, S, and DIBL are obtained, implying 56 105 VDS=I.OV MEDICI Les = LeD = 4 10 UFDG DL= 6.2 5mV 107 109 1011 1013 0.2 0.1 0.0 0.1 0.2 0.3 VGS(V) (a) 106 MEDICI Les = LeD= 10 VDS=10V UFDG DL= 10.2 50mV 108 1010 1012 1 0 14 . . . . . . . . . . . 0.2 0.1 0.0 0.1 0.2 0.3 VGS(V) (b) Figure 3.9 Recalibration of the 18nmFinFET in Figure 3.7. The value of the boundary potential Ob used in UFDG is extracted from MEDICI for both (a) the shorterunderlap, and (b) the longerunderlap FinFET. that along with the tuned DL, Ob also has to be close to the physical value to predict the characteristics of FinFET reliably. In addition, to get a correct 0m, accuracy in (b also aids in getting the correct electric field at the boundary. As seen from Eqs. (3.11)(3.14), Le depends on the electric field at the boundary Eb, as well as on Om. From (3.21), dE dEb tan h ; (3.29) d~b (N2 i.e., overestimation of Pb will overestimate Eb, which in turn overestimates Le in (3.13), and so underestimates the current. For shortchannel devices such overestimation of Le in (3.14) is compensated by the overestimation of 0m. However, for longchannel devices, the minimum potential is mainly influenced by the vertical field and the variation of Ob has a negligible effect on (m (as evident from (3.28), sech(yL/2) 0 as L/tsi becomes large), so overestimation of Ob will mainly result in overestimating Le and thus underestimating Iwk. Modeling Ob for FinFETs with underlap, along the lines of (3.22) for non underlap devices, requires a numerical solution of the PE in the extension. Nonetheless, we can get a simple model for (b using our insights from (3.26). As defined earlier, Les (LeD) is the length from the gate edge to the source (drain) contact where the gateinduced modulation ceases. So the effective channel boundary in the xz plane is where the carrier density is high enough to give a negligible kD and is able to screen the source (drain) carriers from the gateinduced field. Looking at Figure 3.6, the carrier density in the extensions where gate bias dependent modulation is negligible is 1 x 1019cm3. So, the potential 4b at that point can be expressed as b = Vbi VTln (3.30) where nb = 1 x 1019cm3. The value of nb chosen here varies with the device structure; for example, for severe shortchannel effects (i.e., when Leff/tsi is smaller), the electron concentration at the boundary increases due to increased punchthrough, yielding an increase in Ob. Besides, the use of MB statistics also introduces some uncertainty in (3.30). So, we introduce a new userdefined model parameter in UFDG, SCEB such that ND b = Vb (SCEB)VTln (3.31) nb Values of SCEB are positive and usually lie between 0 and 1. Along with this parameter, we also introduce two more parameters, LES and LED corresponding to the lengths Les and LeD in (3.24). These two length parameters replace the parameter DL in UFDG, but unlike DL, the contribution of LES and LED in Leff is biasdependent, as we will show in the next section. 3.3.2 Verification and Utility With three new model parameters, LES and LED defining Leff in (3.24), and SCEB removing the uncertainties in Ob in (3.31), the description of weak inversion current Iwk in (3.14) is now complete for faithfully predicting the weak inversion characteristics of nanoscale FinFETs. In this section we present further calibration results to corroborate UFDG's validity in such predictions. To get the test data, we again use MEDICI. Along with the 10nmthickfilm device, we also simulate a device with thicker film, tsi = 15nm, to check the model's viability for devices with degraded SCEs. In our MEDICI simulations, we use a constantmobility model to avoid nonphysical variations of mobility in the weakinversion region, which is present in some of the mobility models in MEDICI. Earlier UFDG models, used in this section (a QMbased mobility model [Tri05b], incorporated in the recent UFDG versions, is discussed in Chapter 4), take care of the dependence of mobility on film thickness [Chi01], which is absent in MEDICI's constantmobility model. To have the similar mobility in both the simulations, UFDG lowfield mobility UO is set to 820cm2/V.s and 670cm2/V.s for tsi = 10nm and 15nm, respectively, whereas in MEDICI, the lowfield mobility is specified as 600cm2/V.s regardless of the film thickness. Also, quantummechanical effects are not included in either MEDICI or UFDG simulations. In Figure 3.10, UFDG calibration to MEDICIsimulated 15nmthickfilm FinFET is shown. UFDG's prediction of IOFF, S, and DIBL are precise for both devices with total underlap of (a) 8nm, and (b) 16nm. In Figure 3.10(a), values of LES and LED are close to those of Les and LeD in MEDICI, implying that for shorter Les and LeD, LES and LED tell us the amount of underlap in the device. For shorter underlaps, the carriers in the extensions are supported by both the longitudinal field and the vertical fringing field from the gate. As seen from Figure 3.11 near the gate 0.20 0.10 0.00 0.10 VGS (V) (a) 0.10 0.00 0.10 0.20 VGS (V) (b) Figure 3.10 Calibration of UFDG to a MEDICIsimulated 15nmthick fin FinFET with (a) smaller underlaps, and (b) longer underlaps. All other device parameters are the same as in Figure 3.7. 106 108 1010 1012 LI 0.30 1013 L, 0.20 . .*,r. S . ~ * . . ......... .. . ... ...... C 4. . I *' II . *   i i .n a .... ., 5 a J, 1.il' I :,l tl r'i li((I !rTni"jP  .Ii* ... .... . S ..... .. A. ...  *"i ".. * j.. i .l I *i r ..icrunrt ] 2 ~Gj s A  I . s"t* J1. j _ ~ii. ;D .*t...*  4.D "..C O:.t ?e 80 R sD QOt:; e (InLcron > 18012 (b) Figure 3.11 MEDICIsimulated electric field vector in the xy plane of the FinFETs of Figure 3.7 with VGfs = VGfS = VGS = 0.1V and VDS = 50mV. The gate is spanned from 50nm to 68nm. In (a) Les = LeD = 4nm and in (b) Les = LeD = 10nm. edges, in the extensions, the electric field is 2D in nature, thus (3.1), with its boundary conditions (3.2) and (3.3), holds true, as long as Les and LeD are 4nm or less. The physical nature of the UFDG model for such shorter lengths thus allows us, through LES and LED, to extract the amount of underlaps in the devices directly. Figure 3.11(b) shows the electric field vector for longer Les and LeD. The field is clearly ID in nature in most parts of the extensions. So, the UFDG model in such cases basically presents an equivalent structure of the device with underlap, where Leff (as in (3.24)) represents an effective length, which allows UFDG to predict the correct diffusion length Le and minimum potential Om. So, there is no direct correlation between LES and LED with actual underlap in the device where Les and LeD are longer. However, the LES and LED in UFDG can still be effectively used in gathering information regarding the amount of underlap in the device. In Figure 3.12, UFDGpredicted (LES + LED) vs. actual underlap length in the MEDICI (Les + LeD) simulation is plotted for two different film thicknesses. For both devices, UFDG predicts shorter underlaps quite correctly; for longer underlap cases, its prediction is around 50% of the actual underlaps. From this empirical observation, we thus conclude that for devices with long underlap lengths (> 4nm), UFDG parameters LES and LED roughly indicate half of the underlap lengths. Note that from Figure 3.12, for a particular underlap length, the UFDG predicted Leff (defined by LES and LED) is almost independent of tsi. It is expected, because if tsi is thin enough to have sufficient gatecontrol all over the film, then Leff, i.e., the gate control of carriers in the lateral direction, will be independent of tsi. However, if tsi is so thick that the drain has more control of the carriers in the middle 1 0.0 20.0 10.0 15.0 Total Underlap Length (nm) Figure 3.12 Comparison of UFDGpredicted LES + LED (closed symbols), obtained by calibrating to VMEDICIpredicted WI characteristics, with the total underlaps of test FinFETs for two different film thicknesses: 10nm (circles) and 15nm (squares). The tuned SCEB (open symbols) in UFDG for the respective underlaps are also shown. 10.0 + c) S5.0 0.0( C of the fin than the gate, we can expect for a particular underlap length, Leff to be smaller compared to that of a thinner film FinFET. In fact in the figure, the thicker film device has slightly smaller LES+LED (when Les+LeD < 3nm) compared to the thinner film one, consistent with our understanding of Leff(tsi). Also, in Figure 3.12 the SCEB required for corresponding underlap is plotted. With the increase of underlap lengths, the required values of SCEB increase. This is because for the longerunderlap devices, the shortchannel effects are reduced, thereby reducing the potential at the boundary, and thus necessitating an increase in SCEB in (3.31). Usually the value of SCEB will lie between 0 and 1, as in the figure. But, for long channel devices, or with longer underlaps, it may go beyond 1. 3.4 Upgrades in StrongInversion Model for FinFET with Underlaps 3.4.1 Effective Channel Length We observed with gate bias the carrier concentration in the channel (ns), as well as that in the GS/D extension (nes/D) increases. However, as ns reaches ~ 1019cm3 in strong inversion, it screens the gateinduced electric field, as kD decreases and prevents gateinduced modulation of carriers in the extension. The phenomena is depicted in Figure 3.6, where we find that gateinduced modulation of neS/D ceases after the gate bias drives the device into the stronginversion region. That is, in SI there is no contribution of LeS/LeD to Leff in (3.26), which in SI shrinks to L = L + 2X (ns)=L . eff g D s g (3.32) With ns 1019cm3, the contribution of XD(ns) in (3.32) is small compared to Lg, hence, Leff = Lg in SI is a reasonable approximation. Indeed in the calibrations in Chapter 2, we have found that Leff = Lg in SI for longer devices. (The discrepancy in SILeff and Lg in Figure 2.3 for the 17.5nm FinFET could be due to the high R/D, which reduces the effective gate bias, i.e., inversion charge, and hence, increases XD. Also, the longer Leff obtained might also be accounting for the decrease of ID due to the polydepletion effects.) The validity of (3.32) for shorter channel lengths will be shown later in this section, after discussing the parasitic resistances. Note the difference in the manner AL and Les/LeD contribute to the Leff. The overlap always reduces the effective channel length, regardless of the gate biases as evident in (2.1), whereas the underlaps lengthen Leff in weak inversion but do not affect Leff in strong inversion. Such bias dependence is incorporated in UFDG by modeling stronginversion Leff by (3.32) but ignoring the contribution of XD(ns). The shrinking of Leff from (3.24) to (3.32) in UFDG is implicit in the moderateinversion spline, which is defined by the weakinversion and stronginversion currents that are governed by the respective Leff. 3.4.2 Parasitic Resistance Even though in strong inversion, the extensions do not contribute to Leff, they add an additional component to the parasitic resistance. The concentration of carriers in the extensions that define the resistance is determined by the amount of injection from the source (drain), and the diffusion of electrons from the channel. To develop a firstorder model for the resistor we can approximate this carrier concentration in the extensions with an average carrier concentration, nes/, in the linear region of operation. Then the resistance of the extension, ReS/D, assuming driftdominated conduction, is LeS/D R eS/D es/D (3.33) eS/D qn eS/DWti where pL is the carrier mobility in the extension. The average carrier concentration, neS/D, is determined by the carrier concentration on both sides of the GS/D underlap, i.e., nb and ns (Figure 3.6). The complexity in (3.33) comes from ns, which is a function of the effective gate bias, which in turn depends on the resultant ReS/D that reduces the gate bias, VGS by VeS/D = IDReS/D. Hence, incorporation of ReS/D by (3.33) will require introducing an iterative solution scheme for ID(VGSeff = VGS  Ves, VDSeff = VDS 2VeD), where the initial solution of ID has to be obtained with ReS/D = 0, which will also give the initial value of ns, and hence ReS/D. Then the updated ReS/D has to be used to get ID; the loop has to continue until a convergence criterion is met. Thus the incorporation of the linear resistance will increase simulation time significantly. In addition to the dependence on VGS, ReS/D also depends on the drain bias VDS. With the increase of VDS, ID increases, which in turn increases VeS/D, thus the electric field in the underlap increases. As the carrier concentration in the extension neS/D < ns, to support the same ID, the velocity veS/D of the carriers in the extension has to be greater than the velocity vs of the carriers in the channel. With an increased electric field in the extension, veS/D thus increases, and becomes saturated (to a value vsat) before vs. As such, at high VDS, ReS/D saturates and becomes independent of the gate bias, as we have found from UFDG calibration to data in Chapter 2. The phenomenon is further illustrated in Figure 3.13(a) where MEDICIpredicted SIv(y) of a FinFET with long, 27nm of underlap on each side of the gate (the device studied in Figure 2.3), is shown for increasing VDS. At high VDS, both Ves and VeD are saturated and are higher than vs. As VeS/D Vsat, V. 0 in (3.33), and thus ReS/D saturates to a value higher than that in the linear region. With veS/D = vsat, (3.33) is not applicable for saturated ReS/D. Rather, using a quasi2D analysis, like that done for accounting the channellength modulation in bulkSi [Man77], we find the expression for the saturated Res/D as 2 R L eS/D (3.34) eS/D2Si WtSisat Using the dimension parameters (tsi = 32nm, LeS/D = DL/2 = 9nm) of the FinFET in Figure 2.4, and assuming vsat = 5x106 cm/s, the voltage drop across the S/D underlap is 0.28V, with ID = lxl14A. From the calibration results in Figure 2.4, Rs = 4250 pm, assuming 150Qtm of it is due to the contacts/sheet resistance, ReS/D ~ (425 150) or 275Qpm, or 3KQ, which gives a voltage drop across Les, Ves = IDReS 0.3V, close to the value that is implied by (3.34). A complete modeling of ReS/D(VGS,VDS) includes smoothing of the linear resistance defined by (3.33) to the saturation resistance defined by (3.34), and then including the model in an iterative scheme to solve for ID(RS/D), and RS/D(ID). For pragmatic FinFETs, however, Les/LeD should be short, ~ 4nm, as discussed in Chapter 2, and as demonstrated in [Tri05a]. For such FinFETs, the velocity does not saturate in the extensions as illustrated in Figure 3.13(b). In the figure MEDICI 68 1 .5 ............ ...... ......... Les Lg LeD g D 1.0 0.5 o 1.2V J I VGs=1.2V I VDs=0.4V i 0.0 I 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 0.16 y (pm) (a) 2.0  S00.4V .6 0.6V o1.6 0.8V AA1. 0V o 1.2V 1.2 s O I S 0.8  0.4 VGS=1.2V SLs L LeD 0.0 . . 0.022 0.030 0.038 0.046 0.054 y (Pm) (b) Figure 3.13 MEDICIpredicted electron velocity along the channel of a FinFET with (a) long extension length, Les/D = 27nm, and tsi =17nm, like that in Figure 2.4, and (b) Les/D = 4.5nm, tsi = 14nm, like the optimum FinFET [Tri05a] discussed in Chapter 5. (In (b) the reduction in velocity in the channel near the drainend with increasing VDS could be due to the spurious solution of MEDICI energybalance model.) predicted SIv(y) of FinFET with LeS/D = 4.5nm is shown for different drain biases. As the underlap length is not much longer than kD(ns), the gate bias can effectively control the carriers in the extensions. Consequently, at high VGS, when ns and ID increase, neS/D increases as well, and can support the increased ID. Also, shorter underlap length reduces VeS/D, hence the electric field is also low in the extension. Thus VeS/D (and hence neS/D) does not saturate at high VDS; instead the carriers in the channel near the drain experience velocity saturation, like that in the typical MOSFETs. Therefore for pragmatic FinFETs, accounting for the saturation of underlap resistance is not needed. The total parasitic resistance (Rs/D) in FinFET is the sum of the contribution of the contact resistance (Rco), sheet resistance (Rsh), and spreading resistance (Rsp) [Tau98], and an additional component ReS/D when underlap is present, i.e., RsD= Rco +Rsh +Rsp + ReSD. (3.35) While in the bulkSi MOSFET, Rsp is 2030% of RS/D, in the FinFET due to bulk inversion [Kim06], Rsp is small compared to Roo or Rsh (as evident from MEDICI simulations). For shorter underlap length, ReS/D will be low as well. Dependence of ReS/D on LeS/D is illustrated in Figure 3.14, where extracted linear resistance from MEDICIpredicted linear IDVG, is plotted for varying Les. The extraction is done following the 'channel resistance method' described in [Tau98]. As expected from (3.33), the resistance increases sharply with the increase of Les. Also note the increase of ReS/D for the thinner fin. We argued that for pragmatic FinFET LeS/D ~ 300 250 200 150 100 Les (nm) Figure 3.14 Extracted linear resistance of an 18nmFinFET with varying underlap lengths, for two different fin thicknesses. The resistances are extracted from IMEDICIpredicted linear IDVG. Also shown in the figure is the ITRS targeted Rs/D for an 18nmMOSFET [ITR05]. 4nm, and for such cases ReS/D is not that high, and the total RS/D will be dominated by Roo and Rsh. Hence bias dependence of ReS/D expected from (3.33), will not be reflected in RS/D. That is, for shorter Les/LeD neither the VGS nor the VDS dependence has a significant effect on the total resistance, and thus, allows us to avoid incorporating the iterative ReS/D model described by (3.33) and (3.34). In UFDG thus, the biasindependent model parameter RS/RD is retained to model the resistiveeffects of LeS/D. This will make UFDG predictions optimistic for FinFETs with longer underlaps, but for pragmatic, shorter LeS/DFinFETs, model predictions will remain acceptable. The validity of retaining the biasindependent RS/RD to account for the parasitic resistance, as well as that of (3.32) to account for SILeff, for shorter underlap length is illustrated in Figure 3.15. With RS = RD = 60Qpm, and bias dependent Leff captured by LES = LED = 3.2nm, UFDG predictions are well in agreement with that of MEDICI for an 18nmSDG FinFET with 4nm of underlaps on each side of the gate. Excellent match in both the weak and strong inversion exemplifies UFDG's applicability for performance projection of pragmatic nanoscaleUTB FinFETs. 3.5 Design Implications With the incorporation of effects of underlaps in UFDG, we now can extend the design study done in Chapter 2. In Chapter 2, we focused on the effects of underlaps on device performance, here we look into their effects on speed performance of CMOSFinFETs using a 9stage FinFET ringoscillator. The FinFET structure considered is like that shown in Figure 2.8, except for the fin thickness. We VDS=I.OV : 50mV / / MEDICI Ls = LD = 4nm UFDG LES = LED = 3.2nm RS = RD = 60Qgm SCEB = 0 102 103 104 105 106 107 108 109 1010 1011 0. 0.6 0.7 0.8 0.9 1.0 Figure 3.15 Comparison of MEDICI and UFDGpredicted IV characteristics of a midgap gate 18nmSDG FinFET with underlaps; tsi = 8nm, tox = Inm. In both the simulators, carriertemperaturedependent transport models and QM models are turned off. 0.1 0.2 0.3 0.4 0.5 VGS (V) 0 use a pragmatic, thicker (14nm) film [Tri05a]. Also, LeS/D is kept relatively short, 0 8nm, as UFDG predictions are more reliable for shorter underlap lengths, and we already concluded that longer underlap lengths are not useful due to high, bias dependent RS/D. Figure 3.16 shows UFDGpredicted variation of RO delay with underlap lengths. The FinFET has Lg = 18nm, tsi = 14nm, and a midgap gate. In the simulation, ReS/D is taken from Figure 3.14, and 100IpOm is assumed due to contact and sheet resistance. As we do not consider the biasdependence of ReS/D, the delay predicted for the longer underlap lengths, like for LeS/D = 8nm is optimistic, but will not affect our conclusion here. Values of the inner fringing parameter FIF shown in the figure are taken from [Kim06]. The effect of underlap lengths on td is twofold. With increasing LeS/D, ION decreases (Figure 2.10) due to high RS/D, as well as increased Vt, which tends to increase the delay time. On the hand, increasing LeS/D decreases the fringing capacitances [Kim06], and thus tends to decrease td. The former dominates for longer LeS/D, and thus we see td showing a positive slope for LeS/D > 6nm in Figure 3.16 (the increase in td is not that pronounced in the figure due to assumed constant, low ReS/D). The reduction of fringing capacitances dominates for shorter LeS/D, and gives an optimum range for LeS/D, 45nm. In Chapter 2, we reached a similar conclusion considering the devicelevel performances. Thus a pragmatic, and optimum ITRS 45nm node FinFET with Lg = 18nm, should have 4 to 5nm of GS/D underlap. In Chapter 2, we also found that, if asymmetric Les and LeD are feasible, it is advantageous to have Les < LeD, as such a case offers lower Res and hence less 2.6 2.5 C,) 2.4 o 2.3 2.2 Figure 3.16 2.0 4.0 6.0 LeS/D (nm) UFDGpredicted variation of ringoscillator delay (td) with underlap lengths (Les/D). Inset shows key UFDG model parameters used for different Les/D. 1000Qjm of RS/RD is assumed to be due to the contact and sheet resistance, and the contribution ofRes/D(LeS/D) is obtained from Figure 3.14. Values of the inner fringing parameter, FIF is due to [Kim06]. The devices are undoped { 110}FinFET with Lg = 18nm, tsi = 14nm, tox Inm, and (M = 4.6eV; VDD = IV. QM and ballisticlimit model in UFDG is turned on. reduction of effective gate bias. In Table 2.1, we show the improvement in RO delay when Les < LeD is adopted over a reference FinFET having Les = LeD = 4nm. For example, when Les = 0 and LeD = 8nm, the improvement in UFDGpredicted td is 20%. The substantive increase is due to two reasons, one is the noted reduction of Res, and the other is the reduction of gatetodrain capacitance, Cgd with increasing LeD. Increasing LeS/D increases the separation between the source/drain 'plane' and the gate, which reduces both the inner and outer fringing capacitances [Kim06]. So, when LeD (Les) is increased (decreased), Cgd (gatetosource capacitance, Cgs) decreases (increases). Due to the Miller effect, RO delay is more dependent on Cgd than Cgs [Rab03], and hence, even though having Les < LeD increases Cgs, td decreases due to the decreased Cgd, and enhances the speedperformance compared to the Les = LeD design. However, caution should be exerted in designing a device with asymmetric Les/LeD, as when the gate is too close to the source/drain the SCEs degrade (Figure 2.11) and IOFF increases. Moreover, having the source/drain close to the gate edge increases the sensitivity of device performance to the variation of source/drain dopants in the extension, an issue discussed in Chapter 5. 3.6 Conclusion Due to the presence of underlaps, the effective channel length in nanoscale undopedUTB FinFET is biasdependent and is greater than the metallurgical gate length in weak inversion. In this chapter, we have discussed complexities presented by underlaps in compact modeling of FinFETs, and upgraded UFDG to account for Table 3.1 UFDGpredicted ringoscillator delay for an 18nmFinFET underlaps. Values of RS/D (LeS/D) and FIFs/D(LeS/D) are from other device parameters are the same as in Figure 3.16. with asymmetric Figure 3.16, also Les LeD RS RD 1 td (nm) (nm) (Qtm) (Qm) FIFs FIFD (ps) 4 4 128 128 0.7 0.7 2.30 2 6 106 154 0.9 0.6 2.12 0 8 100 188 1.0 0.5 1.82 1. At present UFDG does not allow asymmetric FIF; the above values are hardwired in the code before each simulation. the bias dependence of Leff. Also, the modeling of the sourcechannel boundary potential was discussed for both underlap and conventional nonunderlap devices. In strong inversion, the noted underlap does not affect the Leff significantly, but introduces a component to the parasitic resistance. The resistance due to the underlap shows bias dependence as well; it decreases with gate bias in the linear region, but saturates in the saturation region. However, for pragmatic FinFETs having shorter underlap lengths, the biasdependence of parasitic resistance is negligible and does not warrant a change in the present UFDG formalism that accounts for the parasitic resistance with biasindependent model parameters. Hence, even though modeling of the bias dependence of the underlap resistance was discussed, they were not incorporated in UFDG. However, proper accounting of the bias dependence of Leff was incorporated by replacing the overlap parameter DL, with parameters LES and LED that account for the effective underlap lengths, and modulate Leff appropriately. Model upgrades were verified by comparing UFDG predictions with those of MEDICI's. For both weak and strong inversion, upgraded UFDG predictions were found to be in excellent agreement with MEDICI for pragmatic UTB FinFETs. The proper accounting for the effects of underlaps thus enhanced the reliability of UFDG performanceprojection capability for pragmatic FinFET circuits. The upgraded model was then used to extend the design study of Chapter 2 by performing circuitlevel simulation. Study of the speedperformance of FinFET CMOS revealed that the optimum underlap length for a pragmatic, 45nm ITRS node 78 FinFET is 45nm. Also, UFDGpredicted RO simulation showed that speed enhancement as high as 20% can be achieved if asymmetric underlaps are used. CHAPTER 4 CARRIER TRANSPORT IN NANOSCALE FINFETS 4.1 Introduction In Chapter 2, in the preliminary calibration of UFDG to contemporary FinFETs, we mainly focused on the electrostatics of UTB FinFETs. We found that due to the undoped UTB, the extensions are not doped directly, which in turn results in GS/D underlaps, resulting in biasdependent Leff. A more direct effect of leaving the body undoped is that it reduces the transverse electric field, which promises higher channel mobility. In this chapter, with the upgrades done in Chapter 3 (i.e., accounting for the effects of gatesource/drain underlap), and the recently incorporated QMbased mobility model [Tri05a], we present further calibration of UFDG to FinFETs, and insights thereby derived, especially regarding the carrier mobility and transport properties in the channel. Both electron mobility and hole mobility in n and pchannel FinFETs are studied. The transport parameters obtained from the calibrations are then used to project channel currents of sub20nm FinFETs, by using UFDG simulations, which involve both dissipative and ballistic transport. With highmobility/ballisticlimited transport, the FinFET channel resistance is expected to be low, which indicates that the FinFET will be more vulnerable to parasitic resistance. Effects of the parasitic resistance on drive current and ringoscillator delay are thus discussed by comparing a hypothetical bulkSi device with an SDG FinFET. 4.2 Carrier Mobility in the Channel 4.2.1 Electron Mobility in nFinFET For our nFinFET calibration work described here, we chose room temperature IDVGS characteristics of a 370nmgatelength FinFET with n+poly gate fabricated at AMD with {110} surface [Yu02]. Calibration of UFDG to the subthreshold characteristics, like subthreshold swing and DIBL, allows us to uniquely obtain two of the three dimensionrelated parameters, effective channel length Leff (defined by model parameter L, LES and LED, or DL), fin thickness tsi (defined by model parameter TSI) and oxide thickness tox (defined by model parameter TOXF/TOXB). Hence if the third parameter is known through some other method e.g., oxide thickness from the CV characteristics, or fin thickness from TEM pictures, etc., a valid calibration can be done. However, for the longchannel device here, with apparently no shortchannel effects (SCEs), it is not possible to get unique values for these parameters from UFDG calibration. We mainly thus rely on the manufacturersupplied information for the values of the device dimensions. The gate oxide thickness used is 17A, known from the process information [Yu02] and also verified with reasonable accuracy from calibration of shorterchannel devices, as well as CV characteristics for the same technology [Yu02]. The physical gate length is 370 nm, and with extensions not doped directly, there is no source/gate or drain/ gate overlap and hence DL is set to zero. Underlap length, LES/LED, is assumed to be zero also; however as discussed in Chapter 2, in this device they are actually non zero and may be 3% of the gate length but their effect is negligible in weak inversion. For the same reason, tsi is assumed to be 26 nm, though TEM pictures of the fabricated device suggest it can vary from 17 nm to 26 nm. 4.2.1.1 Calibration Results The weakinversion calibration results, with the model parameters listed in Table 4.1, are shown in Figure 4.1, where UFDG predictions are in good agreement with data except for gate bias, VGS < 0.2 V. In that region, the drain current, ID at high drain bias increases due to gatetodrain tunneling leakage. Throughout this work the UFDG gate leakage model will be turned off but the QM model will remain turned on. The mobility, on which the subthreshold current is linearly dependent, used in the calibration is extracted from the linearregion, stronginversion characteristics described later. The gate work function (WKFG/WKBG) obtained from the calibration is 4.073, which indicates a poly doping of 4.5 x 1019 cm3 (using FermiDirac statistics) in the gate. The high polydoping concentration is consistent with the degradation of capacitances observed in the CV characteristics in [Yu02], where the degradation of gate capacitance is observed only at very high gate bias, VGS > 1.2 V. Once the dimensional parameters are known through weakinversion calibration, the next step is to extract transport parameters from stronginversion calibration. As we have found in Chapter 2, UO and THETA can be obtained uniquely from calibration of gm/ID2VGS, which is independent of Rs/D [Ghi88]. In Figure 4.2, we showed the calibration result of UFDG to gm/ID2 characteristics of the AMD 370 nm FinFET. With UO = 565 cm2/V.s and THETA = 0.2, the UFDG prediction is in excellent agreement with data throughout the stronginversion region, which spans from VGS (Nnv) = 0.3V (5x1012cm2) to 1.2V (2.1x1013cm2). Table 4.1 Key UFDG model parameters extracted from the calibration to 370 nm AMD nFinFET. Model Parameter Description Value L Physical Gate Length 370 nm LES Sourcegate underlap length 0 nm LED Draingate underlap length 0 nm DL Source/draingate Overlap length 0 nm TSI Film Thickness 26 nm TOXF Front gate oxide thickness 1.7 nm TOXB Back gate oxide thickness 1.7 nm WKFG Front gate work function 4.073 eV WKBG Back gate work function 4.073 eV UO Lowfield mobility 565 cm2/V.s THETA Mobility tuning parameter 0.2 RS Parasitic source resistance 390 Qjam RD Parasitic drain resistance 390 Qjam W Width 50 nm 83 1 0 5 . . . . . . . . . . . . . . 106 107 108 o VD = 0.V, measured data o VD = 1.2V, measured data S UFDG 10910 1 0 1 0 1 . . . . . . I . . I . . I . . .. . 0.3 0.2 0.1 0.0 0.1 0.2 0.3 VGS (V) Figure 4.1 Calibration of UFDG to weakinversion characteristics, IDVGS of a 370 nm gate length FinFET. Model parameters are listed in Table 4.1 S.. ....... 0.9 0.8 Measured Data 8 UFDG 0.7 \o = 565cm2Ns < 0.0 = 0.20 0.6 0.5 0.4 E 0) 0 0.3 0.2 0.1 VDS = 0.1V 0 .0 . . . . . . . . . . . . . . . . 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 VGS (V) Figure 4.2 Calibration of UFDG to measured gm/ID2 vs. VGS at low drain bias. The range of VGS shown is all stronginversion, as Vt = 0.1V. 