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Physical Analysis, Modeling, and Design of Nanoscale Double-Gate MOSFETs with Gate-Source/Drain Underlap


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PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE DOUBLE-GATE MOSFETS WITH GATE-SOURCE/DRAIN UNDERLAP By MURSHED M. CHOWDHURY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006

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Copyright 2006 by Murshed M. Chowdhury

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-ToMy parents and Rono

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iv ACKNOWLEDGMENTS Ithasbeenanhonortoworkfor,andwith,mysupervisor,ProfessorJerry Fossum.Withouthispatientandinspiringguidance,encouragement,andsupport, thisworkwouldnothavebeenpossible.Iwouldliketotakethisopportunityto expressmygratitudetohim.Iwouldalsoliketothankmembersofmysupervisory committee,ProfessorsScottThompson,JingGuo,andKevinIngersent,fortheir guidance and interest in this work. IwouldliketoacknowledgeSemiconductorResearchCorporation, FreescaleSemiconductor,andtheNationalScienceFoundationfortheirfinancial support.IwouldalsoliketothankFreescaleSemiconductorandAMDInc.for measured data. IamgratefultoBich-YenNguyenforgivingmeanopportunitytogain industryexperienceatFreescaleSemiconductor.Ihavegreatlybenefitedfromthe interactionswiththeNovelDevice,CMOSandMICAgroupmembers.Iwas extremelyluckytohaveLeoMathewandChipWorkmanasmymentorsthere,both ofwhompatientlysufferedmyconstantdemandofdataandmodeling-tips.Also,I am thankful to Aaron Thean and Ben Gu for numerous discussions. Iwasfortunatetoworkwithfellowgroupmates,LixinGe,Ji-WoonYang, VishalTrivedi,WeiminZhang,Seung-HwanKim,ZhichaoLu,SiddharthChouksey, andShishirAgarwal.Ihavehadmanyilluminatingdiscussionswiththem,especially withVishal,workingwithwhomwasanintriguingandbeneficialexperience.I

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v wouldliketothankmyfriendSaifUzZaman,andKhairulAlamforriveting conversationsonmanyaspectsofdevicephysics.Inaddition,Iwouldliketothank Saif, and Syed Hussain Rana for reading this manuscript. IacknowledgetheunconditionalhelpIreceivedfromTipubhai,Boro Dulabhai,andSheulikhala.Iwasfortunatetohavesuchrelativesandfriendswho arealwaystherewhenneeded.Likewise,mystayhereinGainesvilleismadeeasier bythepresenceofanaccommodatingcommunity,whosegoodfellowshiphelpedme tokeepmymoralehighalltheseyears.Inparticular,IwouldliketothankMaksudur Rahman,ShahedNejhum,SayedHasan,AvijitKar,ZiadSaleh,NaheenAden, Shahed Reza, Reza Nabi, Mustaque Ahmed, and Amas Khan for their camaraderie. Finally,Iamindebtedtomyparents,andsiblings,Appi,Rono,Shetu, Rana,MeruandMoury,fortheirconstantencouragementandsupport.Mydeep gratitudegoestomyparentsfortheirmanysacrificesformyeducation.Thisworkis dedicated to them, and to my selfless brother.

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vi TABLE OF CONTENTS page ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . .iv LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . .ix LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . .x KEY TO ABBREVIATIONS. . . . . . . . . . . . . . . . . . . . . . .xiv ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .x v CHAPTER 1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1Double-Gate MOSFETs; FinFETs. . . . . . . . . . . . . . . . .1 1.2Compact Model for the DG MOSFET. . . . . . . . . . . . . . . .2 1.3Dissertation Outline . . . . . . . . . . . . . . . . . . . . . .5 2PHYSICAL INSIGHTS ON DESIGN AND MODELING OF NANOSCALE FINFETS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . .9 2.2UFDG Calibration Methodology . . . . . . . . . . . . . . . . .11 2.3Calibration of UFDG to AMD nFinFETs . . . . . . . . . . . . .16 2.4Calibration of UFDG to Freescale Poly-Gate nFinFETs. . . . . . . .20 2.5Calibration of UFDG to Freescale Metal-Gate pFinFETs. . . . . . . .22 2.6Device Design Implications. . . . . . . . . . . . . . . . . . .26 2.7Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .33 3UFDG UPGRADES FOR NANOSCALE FINFETS WITH UNDERLAPS. . .35 3.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . .35 3.2Calculation of Weak-Inversion Current in UFDG. . . . . . . . . . .36 3.2.1Review of Weak-Inversion Current Model in UFDG . . . . . .36 3.2.2Source/Drain-Body Junction Potential. . . . . . . . . . . .40 3.2.3Weak-Inversion Model Verification for DG MOSFET. . . . . .47

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vii 3.3Upgrades in Weak-Inversion Model for FinFET with Underlaps . . . .49 3.3.1Model Upgrades. . . . . . . . . . . . . . . . . . . . .49 3.3.2Verification and Utility. . . . . . . . . . . . . . . . . .58 3.4Upgrades in Strong-Inversion Model for FinFET with Underlaps . . . .64 3.4.1Effective Channel Length. . . . . . . . . . . . . . . . .64 3.4.2Parasitic Resistance . . . . . . . . . . . . . . . . . . .65 3.6Conclusion . . . . . . . . . . . . . . . . . . . . . . . . .75 4CARRIER TRANSPORT IN NANOSCALE FINFETS . . . . . . . . . .79 4.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . .79 4.2Carrier Mobility in the Channel. . . . . . . . . . . . . . . . . .80 4.2.1Electron Mobility in nFinFET . . . . . . . . . . . . . . .80 4.2.2Hole Mobility in pFinFET . . . . . . . . . . . . . . . .100 4.3Ballistic-Limit Current. . . . . . . . . . . . . . . . . . . . .107 4.4Effects of Parasitics, and Design Implications. . . . . . . . . . . .109 4.4.1Effects of Parasitic Resistance . . . . . . . . . . . . . .111 4.4.2Effects of Parasitic Capacitance. . . . . . . . . . . . . .115 4.5Summary. . . . . . . . . . . . . . . . . . . . . . . . . .117 5SENSITIVITY OF FINFET PERFORMANCE TO GATE-SOURCE/DRAIN UNDERLAP PROPERTIES. . . . . . . . . . . . . . . . . . . . .119 5.1Introduction . . . . . . . . . . . . . . . . . . . . . . . .119 5.2Reference FinFET . . . . . . . . . . . . . . . . . . . . . .123 5.3Effects of Variation of Film Thickness . . . . . . . . . . . . . .128 5.4Effects of Variation of Gate Length. . . . . . . . . . . . . . . .130 5.5Effects of Variation of Lateral Straggle. . . . . . . . . . . . . .132 5.6Effects of Random Doping. . . . . . . . . . . . . . . . . . .136 5.6.1NSD(y) Randomness. . . . . . . . . . . . . . . . . . .135 5.6.2NSD(x) Randomness. . . . . . . . . . . . . . . . . . .139 5.6.3Random UTB/Channel Doping . . . . . . . . . . . . . .143 5.7Worst-Case Scenario . . . . . . . . . . . . . . . . . . . . .145 5.8Summary. . . . . . . . . . . . . . . . . . . . . . . . . .148 6GATE TUNNELING CURRENT IN NANOSCALE FINFETS. . . . . . .150 6.1Introduction . . . . . . . . . . . . . . . . . . . . . . . .150 6.2Compact Model for Gate Tunneling Current in FinFET . . . . . . .151 6.2.1Tunneling Current Components. . . . . . . . . . . . . .153 6.2.2Tunneling Current Model. . . . . . . . . . . . . . . . .157 6.2.3Tunneling in Asymmetric-Gate Devices . . . . . . . . . .174 6.2.4Drain Bias Dependence of Tunneling Current. . . . . . . . .178 6.3Model Implementation and Verification . . . . . . . . . . . . .182 6.4Effects of Gate Tunneling Current on FinFET-CMOS Performance. . .194 6.5Summary. . . . . . . . . . . . . . . . . . . . . . . . . .199

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viii 7CONCLUSIONS AND RECOMMENDATIONS. . . . . . . . . . . .200 7.1Summary and Conclusion. . . . . . . . . . . . . . . . . . . .200 7.2Recommendations for Future Work. . . . . . . . . . . . . . . .204 APPENDIX MISCELLANEOUS UFDG UPGRADES. . . . . . . . . . . . . . .207 A.1Refining the Moderate-Inversion Spline . . . . . . . . . . . . .207 A.2Incorporating NBODY= 0 Option . . . . . . . . . . . . . . . .212 A.3Refining the Charge Modeling. . . . . . . . . . . . . . . . . .215 A.3.1Accumulation Charge. . . . . . . . . . . . . . . . . .215 A.3.2Weak-Inversion Charge . . . . . . . . . . . . . . . . .217 A.4Refinement of the Velocity Overshoot Model. . . . . . . . . . . .219 A.5Weak-Inversion QM Model. . . . . . . . . . . . . . . . . . .223 REFERENCES. . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 BIOGRAPHICAL SKETCH . . . . . . . . . . . . . . . . . . . . . . .236

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ix LIST OF TABLES Table page 2.1Key UFDG model parameters with brief description. . . . . . . . . . .12 3.1UFDG-predicted ring-oscillator delay for an 18nm-FinFET. . . . . . . .76 4.1Key UFDG model parameters extracted from the calibration. . . . . . . .82 4.2SCHRED-predicted subband occupation properties . . . . . . . . . . .99 4.3Key UFPDB model parameters used in the study. . . . . . . . . . . .110 5.1MEDICIand UFDG-predicted characteristics of FinFETs. . . . . . . .138 5.2UFDG-predicted variation of performance of FinFET-CMOS. . . . . . .147

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x LIST OF FIGURES Figure page 1.1Double-Gate MOSFET structures . . . . . . . . . . . . . . . . . .3 2.1Measured SCEs vs. Lg of CMOS FinFETs. . . . . . . . . . . . . . .10 2.2Partial UFDG calibration to an Lg = 105nm nFinFET . . . . . . . . . .17 2.3Partial UFDG calibration to an Lg = 17.5nm nFinFET . . . . . . . . . .18 2.4Partial UFDG calibration to an Lg = 100nm nFinFET. . . . . . . . . . .21 2.5Calibration of UFDG to metal-gate pFinFETs. . . . . . . . . . . . . .23 2.6Calibration of UFDG to a 75nm metal-gate pFinFET. . . . . . . . . . .24 2.7Variation of TiN gate workfunction ( FM) with drawn length. . . . . . . .25 2.8Schematic cross section (top view) of an undoped FinFET. . . . . . . . .27 2.9Effects of underlaps on the subthreshold characteristics of FinFET . . . . .29 2.10MEDICI-predicted variation of ION and IOFF . . . . . . . . . . . . .31 2.11MEDICI-predicted variation of FinFET performance. . . . . . . . . . .32 3.1Boundaries for the solution of Poissons equation in the DG-MOSFET. . . .37 3.2Lateral potential profile in weak inversion in the channel. . . . . . . . .41 3.3Schematic of variation of lateral potential.. . . . . . . . . . . . . . .43 3.4Comparison of the variation of boundary potential . . . . . . . . . . .46 3.5Comparison of UFDG predictions with that of MEDICI in weak inversion. .48 3.6MEDICI-predicted surface potential variation between S and D. . . . . . .50

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xi 3.7UFDG calibration to a MEDICI-simulated mid-gap FinFET. . . . . . . .52 3.8MEDICIand UFDG-predicted potential profile, f (y) . . . . . . . . . .54 3.9Recalibration of the 18nm-FinFET . . . . . . . . . . . . . . . . .56 3.10Calibration of UFDG to a MEDICI-simulated 15nm-thick fin FinFET. . . .60 3.11MEDICI-simulated electric field vector in the x-y plane. . . . . . . . . .61 3.12Comparison of UFDG predicted LES + LED.. . . . . . . . . . . . . .63 3.13MEDICI-predicted electron velocity along the channel. . . . . . . . . .68 3.14Extracted linear resistance of an 18nm-FinFET. . . . . . . . . . . . .70 3.15Comparison of MEDICIand UFDG-predicted I-V characteristics . . . . .72 3.16UFDG-predicted variation of ring-oscillator delay . . . . . . . . . . .74 4.1Calibration of UFDG to weak-inversion characteristics . . . . . . . . .83 4.2Calibration of UFDG to measured gm/ID 2 vs. VGS . . . . . . . . . . .84 4.3UFDG-predicted strong-inversion ID-VGS characteristics. . . . . . . . .86 4.4MEDICI-predicted variation of gm/ID 2 with polysilicon doping. . . . . . .88 4.5SCHRED-predicted average distribution of carriers . . . . . . . . . . .94 4.6Calibrated UFDG-predicted variation of effective electron mobility . . . .97 4.7Results of calibrating UFDG to an Lg = 10mm pFinFET . . . . . . . .102 4.8UFDG calibration to the ID-VGS characteristics of the 10mm-pFinFET. . .103 4.9UFDG-predicted effective hole mobility . . . . . . . . . . . . . . .105 4.10UFDG-predicted current-voltage characteristics . . . . . . . . . . . .108 4.11Effects of parasitic resistance on the on-sate current. . . . . . . . . . .113 4.12Predicted propagation delays versus parasitic source/drain resistance . . .114 4.13Predicted propagation delays versus parasitic capacitance . . . . . . . .116

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xii 5.1The lateral S/D-extension doping concentration, NSD(y) . . . . . . . .121 5.2Partial calibration of UFDG to MEDICI-predicted characteristics . . . . .125 5.3FinFET-CMOS circuits used in the sensitivity study . . . . . . . . . .127 5.4Sensitivity of FinFET performance-parameters with the variation of tSi. . .129 5.5Sensitivity of FinFET performance-parameters with the variation of Lg. . .131 5.6Effects of varying Lg, but keeping Lext constant . . . . . . . . . . . .133 5.7Effects of variation of lateral straggle on the sensitivity of FinFET . . . .134 5.8Various lateral doping profiles. . . . . . . . . . . . . . . . . . .137 5.9Localization of lateral dopants, NSD(y) at different x . . . . . . . . . .141 5.10Medici-predicted ID-VGS characteristics . . . . . . . . . . . . . . .142 5.11Taurus-Device-predicted effects of uncontrolled doping on ID-VGS. . . . .144 6.1Leakage current components in a CMOS-inverter. . . . . . . . . . . .152 6.2Tunneling current components in an nFinFET. . . . . . . . . . . . .154 6.3Dominant tunneling component in a metal-gate . . . . . . . . . . . .156 6.4Tunneling from semi-classical picture. . . . . . . . . . . . . . . .159 6.5SCHRED-simulated conduction band profile . . . . . . . . . . . . .164 6.6Comparison of distance between classical turning points . . . . . . . .166 6.7Variation of ground-state electron velocity with bias . . . . . . . . . .169 6.8Schematic of variation of Ec(x) in weak inversion in a MIGFET . . . . .176 6.9Variation of IGS/IG with drain bias. . . . . . . . . . . . . . . . . .183 6.10Updated UFDG network diagram . . . . . . . . . . . . . . . . .184 6.11Significance of the higher subbands in FinFET. . . . . . . . . . . . .186 6.12Comparison of UFDG gate leakage models prediction . . . . . . . . .188

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xiii 6.13Effects of DREFF on gate leakage current. .. . . . . . . . . . . . . .191 6.14UFDG-predicted tunneling current through the gates . . . . . . . . . .192 6.15UFDG-predicted tunneling current in nand p-channel FinFETs . . . . .193 6.16UFDG-simulated transient response of an FinFET-SRAM cell. . . . . . .195 6.17Gate-current density at three future ITRS nodes . . . . . . . . . . . .196 6.18Comparison of UFDG-predicted leakage currents in nFinFET. . . . . . .198 A.1Cartoon depicting a typical ID-VG characteristics . . . . . . . . . . .210 A.2Effects of UFDG model parameter DG . . . . . . . . . . . . . . .211 A.3UFDG2.4 simulated ID-VG characteristics. . . . . . . . . . . . . . .214 A.4High field region in the channel of a double-gate MOSFET. . . . . . . .220 A.5Comparison of effective saturated velocity . . . . . . . . . . . . . .222 A.6Comparison of weak-inversion quantum-mechanical model. . . . . . . .225

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xiv KEY TO ABBREVIATIONS MOSFETMetal-Oxide-Semiconductor Field-Effect Transistor CMOSComplementary MOS SOISilicon-on-Insulator FDFully depleted UTBUltra-thin body SGSingle gate SDGSymmetrical double gate ADGAsymmetrical double gate IGIndependent gate UFDGUniversity of Florida Double Gate KEKinetic energy PEPotential energy SCEShort-channel effect DIBLDrain-induced barrier lowering QMQuantum mechanical TEMTransmission Electron Microscopy MCMonte Carlo DOSDensity of states SDESource/Drain Extension

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xv AbstractofDissertationPresentedtotheGraduateSchoolofthe UniversityofFloridainPartialFulfillmentoftheRequirements for the Degree of Doctor of Philosophy PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE DOUBLE-GATE MOSFETS WITH GATE-SOURCE/DRAIN UNDERLAP By Murshed M. Chowdhury August 2006 Chairman: Jerry G. Fossum Major Department: Electrical and Computer Engineering Thisdissertationfocusesonthephysicsandmodelingofnanoscale double-gate(DG)field-effecttransistors(FETs).Themodelingworkisincorporated intheUniversityofFloridaDouble-Gate(UFDG)metal-oxide-semiconductorfieldeffecttransistor(MOSFET)modelthatenablespredictivedevice/circuitsimulations of complementary metal-oxide-semiconductor (CMOS) circuits based on DG FETs. PhysicalinsightsontheelectrostaticsoftheDGMOSFET,especiallythe quasi-planarFinFET,aregainedfromcalibrationofUFDGtodataobtainedfrom industry.ThecalibrationresultsshowthatcontemporaryFinFETshavegate-source/ drainunderlapthatmakestheeffectivechannellength,andparasiticresistance,biasdependent.Insightsfromthecalibrations,alongwithnumericalsimulationresults, revealthatthenotedunderlapscouldbeusedbeneficiallyinscaledFinFETdesign. ThestudyalsopinpointsrequiredUFDGupgradesfornanoscaleFinFETs,whichare subsequently done and implemented in UFDG.

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xvi Theupgradedmodelisthenusedtogaininsightsonthetransport propertiesofscaledFinFETsby,again,calibratingUFDGtoexperimentaldata.The calibrationresultsshowmobilitiesinbothp-andn-channelFinFETaredramatically highcomparedtothoseinbulk-SiMOSFETs.Thehighmobilitiesportend,asshown byUFDG,ballistic-limitcurrentinnanoscaleFinFETs,whichleadsustothe conclusionthatchannelengineering,likestrainingthechannel,toincreasemobility in the FinFET is not needed. Theviabilityofgate-source/drainunderlapasadesignparameter,in additiontotypicaldevicedesignparameterslikegatelength,finthickness,etc.,is investigatedintermsofthesensitivityofFinFETperformancetothevariationsof processparametersthatinfluenceunderlapproperties;numericalsimulatorswith UFDGaidthisinvestigation.Itisfoundthatwhilevariationintheperformanceof inverter-basedcircuits,liketheringoscillator,isreasonable,stabilityofstatic randomaccessmemory(SRAM)showswidevariationinperformanceforshorter underlap lengths. Finally,aphysics-basedcompactmodelforgatetunnelingcurrentinDG MOSFETsisdeveloped,verified,andimplementedinUFDGtoenablereliable predictionofstaticpowerconsumptioninnanoscaleFinFETcircuits.Model predictionscorroborateearlierresultsthatforthinneroxides,present-daysilicon oxynitridehastobereplacedwithhigh-kdielectricstocontrolstaticleakage. However,useofunderlapcanrelaxtheoxidethicknessrequirementandhencedelay the introduction of high-k dielectrics in FinFET technology.

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1 CHAPTER 1 INTRODUCTION 1.1 Double-Gate MOSFETs; FinFETs Inthepastthreedecades,thenumberoftransistorsperchiphasgoneup toafewhundredmillion,fromafewthousandintheearlys[Boh03].Suchan astronomicalincreaseoftransistorsperchipisfacilitatedbycontinuousscalingof thebulk-SiMOSFET,theworkhorsetransistorofdigitalintegratedcircuits. However,asthefeaturesizeisapproachingsub-50nm,thescalingofthebulk-Si MOSFETfacesstiffchallengescomingfromincreasedsource-drainleakage, increasedgatetunnelingcurrent,andwidevariationsindeviceperformancedueto uncontrollablechanneldoping[ITR03].Hence,researchersaresearchingfor alternativestothebulk-SiMOSFETanditssilicon-on-insulator(SOI)counterpart, thepartiallydepleted(PD)SOIMOSFET.Amongthealternativedevicesconsidered sofar,thedouble-gate(DG)MOSFET[His00]isthemostpromisingcandidateto replace bulk-Si devices down the roadmap [ITR03]. TheDGMOSFETisofthesamematerialasthebulkMOSFET,i.e., silicon,buthasadifferentstructure.Itoffersbettercontrolofshort-channeleffects (SCE)control[Kim01b]arisingfromtheuseoftwogateswithanultra-thinbody (UTB);andhighdrivecurrentperdevicewidthresultingfromhighmobilitydueto lowtransverseelectricfieldandhigherinversioncarrierdensityfromthetwo channels.TheDGMOSFETneednotrequiredrasticchangesintheexistingCMOS

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2 processtechnology.Figure1.1(a)showsaschematicofsuchaMOSFET.Thethin channelissandwichedbetweenthetwogates,oneofwhichisburiedintheSOI island.Whenthepropertiesofbothgates(gateworkfunction,gateoxidethickness, andbias)areidentical,thedeviceiscalledasymmetricdouble-gate(SDG) MOSFET;otherwise,itisanasymmetricdouble-gate(ADG)MOSFET.Whilethe electricalcharacteristicsofthechanneloftheDGMOSFETarepromising,high source/drainresistance(RS/D)duetothethinsiliconanddifficultyinaligningthe two gates cloud this devices future. AnalternateandcurrentlyapopularversionoftheDGdevicecalleda FinFETisshowninFigure1.1(b),wherethedeviceofFigure1.1(a)isbasically rotated90o.IntheFinFET,thegateis"wrapped"overthethinsiliconfinthatis extendedtoisolatethegatefromthesourceandthedrain.Asthegateisone continuouspiece,thegatemisalignmentissueisresolvedandtheextendedfincan bethickenedtoreducethehighRS/Daswell.ForSDGdesign,thetwogatesremain connectedandathickeroxidelayerisusedontopofthefintoelectricallyisolatethe topgatefromthechannel(body).Whenthisisnotthecase,thedeviceiscalledatrigateMOSFET[Doy03].IfADGoperationisintended,thetopgateisetchedoffto isolatethetwogates,andthedeviceiscalledanIndependentGate(IG)FinFET,such as the MIGFET [Mat04]. 1.2 Compact Model for the DG MOSFET WhateverformoftheDGMOSFETisconsidered(e.g.,ADG,SDG,or IG),forsuccessfuladvancementofthetechnology,anaccompanyingcompactmodel isaprerequisite.Acompactmodelwillallowthecircuitdesignerstoexamineand

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3 (b) Oxide Gate Drain Source W = hSi y x SiFin(a) Substrate Front Gate Back Gate Drain Source Oxide W z yFigure 1.1Double-GateMOSFETstructures:(a)planarDGstructure:body issandwichedbetweenthetwogates[Den96];(b)FinFET structure:theraisedsource/drainisisolatedfromthegatebythe thin extension.

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4 exploitcircuitsemployingDGMOSFETs.Thisrequiresthemodeltobefastenough tosimulatelargeblocksofcircuitsinreasonabletimes.Atthesametime,themodel shouldhavesufficientphysicalbasistoallowdeviceengineerstofaithfullypredict deviceperformance,aswellastoobtainreliableinsightsonthedevicesfabricated, especiallywhenthetechnologyisstillinitsinfancy.Abalancebetweenhavingafast andphysics-basedmodelisthusimperative;UFDG[Fos04a],aphysics/processbasedcompactmodelforDGMOSFETsfromtheSOIgroupattheUniversityof Florida,eloquentlymaintainsthebalance.Themodelisgenericinnature,andcanbe usedforSDG,ADG,andIGMOSFETs,aswellasforsingle-gatefullydepleted(FD) SOI devices. InUFDG,the2DPoissonequation(PE)issolvedtogettheweakinversion(WI)characteristics[Yeh96].The1DPEiscombinedwiththedriftdiffusioncurrentequationtoobtainthestrong-inversion(SI)characteristics[Chi01], andthemoderate-inversion(MI)characteristicsareobtainedusingpolynomial splines,thecoefficientsofwhicharedefinedbythephysicalWIandSIsolutionsat theMIboundaries.InSI,velocitysaturationisaccountedforbyincorporatinga simplifiedformoftheBoltzmanTransportEquation(BTE)[Ge01].Quantummechanical(QM)effectsareincorporatedbysolvingthe1DPEandeffective-mass Schrdingerequation(SE)self-consistently[Ge02a].TheSEissolvedusinga variationalmethod,andthesurfaceorientationeffectsareincludedthroughproperly definingtheeffectivemassesandvalleydegeneracies.Thetransportformalismhas amobilitymodel[Tri05b]thataddressesthedifferentscatteringmechanisms,and takescareofthermalinjection-limited,orballistic-liketransport.Withthe

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5 incorporationofallthesephysicalphenomena,UFDGisevolvingasanessentialtool forunderstandingDGMOSFETtechnology,aswellasforpredictingcircuit performance, and is now in use in industry and academia alike. 1.3 Dissertation Outline Inthisdissertation,westartwithapplicationsofUFDGwheredevice characteristicsobtainedfromindustrialcollaboratorsareusedtounderstandandgain physicalinsightsonUTBDGMOSFEToperationsbysystematicallycalibrating UFDGtothem,whichthenleadstonecessaryupgradesandenhancementsofUFDG. Theupgradedmodelisthenusedforfurthercalibration,followedbypredictionof circuit performances, and their sensitivity to different process parameters. SinceUFDGisaphysics/process-basedcompactmodel,itskeymodel parametersrelatedirectlytodevicestructureandphysics.Hencesystematic calibrationofUFDGrequiresknowledgeoftheDGSOItechnology.Themodelcalibrationmethodology,whichissimilartothatofUFPDB[Chi01],aphysics/ process-basedPDSOIMOSFETmodel,includestuningofparticularparameters basedononlyafewelectricalmeasurementsofdevices.Themethodology[Chi01] isexpandedandappliedinChapter2forpreliminarycalibrationtocontemporary FinFETdataobtainedfromtwoindustrycollaborators,FreescaleSemiconductorand AMD.Theinsightsfromthecalibrations,alongwithnumericalsimulations,arethen used in discussing design issues related to nanoscale FinFETs. ThepreliminaryUFDGcalibrationstoFinFETsdoneinChapter2reveal newinsightsintotheoperationofDGdevices,suchasdifferenteffectsofgatesource/drainunderlapinweakandstronginversionthatnecessitatemodel

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6 refinements.InChapter3,theincorporationoftheeffectsofunderlapsinUFDG formalismisdiscussed.InWI,theunderlapselongatetheeffectivechannellength (Leff)thatdeterminestheSCEs,modelingofwhichhencebecomescritical.Aftera briefdescriptionofUFDGWIformalismwethuspresentasimplifiedyetphysical wayofincorporatingtheeffectsofunderlapsintheWIcharacteristics.Instrong inversion,theunderlapdoesnotcontributetotheLeffsignificantly,howeveritdoes introduceanadditionalbias-dependentcomponenttotheparasiticsource/drain resistance.So,modelingissuesandminimizingtheeffectsofsuchresistanceare discussed as well. Withproperaccountingoftheeffectsofunderlaps,therefinedversionof UFDG,whichalsohasanupgradedQM-basedmobilitymodel[Tri05b],isthenused forfurthercalibrationtocontemporaryFinFETsinChapter4.Thefocusnow, however,isonthecarriertransportinthechanneloftheFinFET,ratherthanonthe electrostatics(asinChapter2).CalibrationofUFDGtoundopedp-andn-channel DGFinFETsshowsveryhighmobilitiesincontemporaryFinFETs,implyingsmooth {110}fin-sidewallsurfaces,andgivingnewinsightsonelectronandholemobilities inDGMOSFETswith{110}versus{100}surfaces.Thehighmobilityportends ballistictransportinnanoscaleFinFETs,andindeedsimulationof17.5nmDG FinFETsbyUFDGshowsballistic-likecurrents.Thehighmobilityandballistic-like currentindicatelowintrinsicchannelresistanceinFinFET,whichindicatesFinFET characteristicscouldbedominatedbytheparasiticresistances.Theeffectof parasiticsonhighintrinsicdrivecurrentoftheFinFETisthusstudied,andcompared with that found in bulk-Si devices.

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7 WiththeneededunderlapsinnanoscaleFinFETswithundopedUTBs,the sensitivityofdeviceperformancegetsanaddedconstraint:thesource/draindopants intheextension.Inbulk-Sitechnology,thesource/draindopantsdefinevirtually bias-independentgate-source/drainoverlaplengthandparasiticresistance.Butin FinFET,thebias-dependenteffectsmakethesensitivityofdevicecharacteristicsto thevariationsofextensionproperties,likethelateralsource/draindopingprofileor thefinthickness,unique.InChapter5,theeffectsofsuchvariationsoncircuit performanceslikeROdelayandstaticnoisemargin(SNM)ofSRAMarestudied usingMEDICI[Med04]andUFDG.Inaddition,effectsofanunintentionaldopant (acceptor/donor)inthechannelofanextremelyscaleddeviceisstudiedusingthe3D numerical simulator, Taurus-MEDICI [Tau04]. WhileChapters2-5aremainlyconcernedwiththeelectrostaticand carrier-transportpropertiesinthechanneloftheDGMOSFET,anotherimportant factor,thegatetunnelingcurrent,deservesattention.Indeed,thecontinualincrease ofgatetunnelingleakagewithscalingisoneofthemainfactorsthatinitiatedthe searchforareplacementofthebulk-SiMOSFET.Itisexpectedthatduetothelow electricfieldintheSDGMOSFETthegatetunnelingcurrentwillbelessthanthatin thebulk-Sidevice.However,withcontinuousscalingoftheoxidethickness,andthe uncleardirectionthatintegrationofhigh-kdielectricsistakinginCMOStechnology, theeffectsofgateleakagecurrentinSDGMOSFETsrequiresexamination.Besides, theelectricfieldintheADGMOSFET,unlikethatinSDGdevices,isnotlow,and hencegateleakagecurrentintheADGMOSFETcanbeaseriousissue.InChapter 6,wethusdevelopaphysics-basedcompactmodelforgatetunnelingcurrentin

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8 genericDGMOSFETs.Whileallthecomponentsoftunnelingcurrentsinthe nanoscaleFinFETareconsidered,onlythemostdominantcomponent,whichisthe electron(hole)tunnelingcurrentfromtheconduction(valence)bandintheSiofthe nFinFET(pFinFET),ismodeledphysically.Themodelisverifiedwithexperimental dataobtainedfromtwodifferentgroups,andthenisusedtoexaminetheeffectsof tunnelingonthestaticpowerofscaledDGdevicesandcircuits.Thegateleakage modelalsonecessitatedarefinementintheUFDGQMmodelinweakinversion, whichisdescribedintheAppendixalongwithotherUFDGupgradesthatstemmed from the work of this dissertation. Finally,Chapter7providesasummaryoftheworkdoneinthe dissertation, along with recommendations for future work.

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9 CHAPTER 2 PHYSICAL INSIGHTS ON DESIGN AND MODELING OF NANOSCALE FINFETS 2.1 Introduction TheattractivefeaturesoftheFinFET,likebetterSCEs,higherION,etc., promptedexperimentalstudyofthisdeviceandseveralgroupspublished encouragingresults.Forexample,weshowFinFETSCEsasreportedin[Yu02]in Figure2.1,whereforagatelength(Lg)of20nm,andfinthickness(tSi)of17-26nm, drain-inducedbarrierlowering(DIBL)aslowas40mV/Vandsubthresholdslope,S ~75mV/decadeareobserved.WhiletheexcellentSCEsobservedwithLg/tSi~1are encouraging,fromadevice-physicsperspectivetheresultsareperplexing;mere solutionofthePEshowsthattohavereasonableSCEs(DIBL<100mV/V,S< 80mV/decade),effectivechannellength(Leff)hastobemorethantwicetSi[Kim01a].Theeffectivechannellengthisthelengthofthechannelregion,resistance ofwhichismodulatedbythegate,andhence,definesthegate-inducedvariationof MOSFETcharacteristics,i.e.,itsswitchingproperties.Ideally,Leffshouldbeequal tothephysicalgatelength,Lg.However,frombulk-SiexperienceweknowthatLeff
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10 020406080100 0 40 80 120 160 0 40 80 120 160 NMOS PMOS Wfin=26nm DIBL (mV/V) Subthreshold Slope (mV/dec)Gate Length (nm) 020406080100 0 40 80 120 160 0 40 80 120 160 NMOS PMOS Wfin=26nm DIBL (mV/V) Subthreshold Slope (mV/dec)Gate Length (nm) t Si =17-26nm Figure 2.1MeasuredSCEsvs.LgofCMOSFinFETs,reproducedfrom[Yu02].Note the extraordinary S and DIBL obtained with Lg < 30nm and tSi = 26nm.

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11 thesedevices,andtoexplainthesurprisingexperimentalobservations.Before discussingthecalibrationresults,webrieflyoutlinethecalibrationmethodologyfor UFDG. 2.2 UFDG Calibration Methodology BecauseofUFDGsphysicalbasis,UFDGmodelparametersareknown fromprocesstechnology,orcanbereasonablyestimatedforinitialguessesinthe calibrationprocess.ThekeyUFDGmodelparametersarelistedwiththeirdefault valuesinTable2.1.Foracompletelistoftheparameters,pleaserefertotheuser guide[Fos05].Throughoutthisdocument,wewillshowthemodelparametersin boldfacetodifferentiatethemfromthecorrespondingdevicevariables.The parametersnotlistedherearemostlyusedwiththeirdefaultvaluesobtainedfrom calibrationofearlier-generationSOItechnologies[Kris96a],[Chi01]andhavenot changed with scaling. Theevaluationofmodelparametersstartswithsettingapreliminary modelcardbasedonthetechnologyinformation.Modelparameters, TOXF TOXB TSI NBODY NSD WKFG WKBG SO ,alongwithgatelength( L ),andwidth ( W ),canbeestimatedfromtheprocessinformation.However,processvariationscan significantlychangesomeoftheparameters,like NBODY TSI ,etc.Oneconfusion commoninliteraturerelatedtoDGdevices,especiallyforFinFETs,isthedefinition of W (Figure1.1).InUFDG,theintegratedchannelchargethatnaturallyincludes bulkinversion[Kim04]isusedincalculatingthedraincurrent.So,widthherefora FinFETissimplytheheightoftheFET(hSi).Themorecommonlyused2hSi[Yu02], whichstemsfromcalculatingthecurrentforeachchannelwiththefactor2taking

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12 Model Parameter DescriptionUnitDefault TOXF Front-gate oxide thicknessm3.0x10-9TOXB Back-gate oxide thicknessm3.0x10-9TSI Si-lm (body/channel) thicknessm10.0x10-9LES Dynamic source-extension lengthm0 LED Dynamic drain-extension lengthm0 NBODY Si-lm (body/channel) doping densitycm-31.0x1015NDS Source/drain doping densitycm-35.0x1019WKFG Front-gate work functionV4.6 WKBG Back-gate work functionV4.6 QMX 1D effective mass parameter for QM1 UO Low-eld mobility for thick TSI (nmos/pmos) cm2V-1s-11100./190. THETA Mobility (surface-roughness model) tuning parameter 1.0 VSAT Carrier saturated drift velocitycms-17.0x106VO Velocity overshoot parameter0 RD Specic drain parasitic resistanceohmm0 RS Specic source parasitic resistanceohmm0 SO (n-)channel surface-orientation indicator (1: <100>; 2: <110>) 1 DG Tied-gates indicator (1: Gf and Gb tied; 0: Gf and Gb untied) 1 Table 2.1 Key UFDG model parameters with brief description and default values.

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13 careofthetwoFinFETchannels,inherentlymissesanappropriateaccountingofthe contribution of bulk inversion to the drain current. Aftersettingthepreliminarymodelcard,thenextstepofUFDG calibrationistocalibratetheweak-inversionID-VGcharacteristicsofthedevice.The short-channeleffectsaredefinedbytheeffectivechannellength(Leff),finthickness (tSi)andoxidethickness(tox),alongwithbodydoping.InnanoscaleFinFETs,the body is usually undoped and in UFDG Leff is defined by (2.1) where D Listheadjustment,usuallypositive,duetothegate-source/drainoverlap, representedbymodelparameter DL inTable1.So,bymatchingSCEslikeSand DIBLfromtheweak-inversionID-VGScharacteristicsofnanoscaleFinFETs,onecan fine-tunethe L DL TSI and TOXF / TOXB .OnceDIBLandSarematched,the WKFG / WKBG canbeevaluatedbymatchingtheoff-statecurrent,IOFF.After evaluatingthestructural/process-relatedmodelparametersfromtheweak-inversion calibration,calibrationofthelinear-region,strong-inversionID-VGScharacteristics should follow. Atlowdrainbiasthereisnovelocityovershootorself-heatingeffect,so fromthestrong-inversion,linear-regioncharacteristics,effectivemobility, meff(definedsolelybymodelparameter UO and THETA )andparasiticresistances, RS and RD, canbeextractedprecisely.However,as RS / RD caneffecttheextracted mobility,calibratingtheID-VGScharacteristicsdirectlywillnotyieldanaccurate effectivemobility,especiallyforashort-channeldevice.Toavoidthis,wewill L effLgD L @

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14 calibrategm/ID 2,whichisnearlyindependentof RS / RD [Ghi88],[Kri96].Thetotal on-state resistance, RON, in the linear region can be expressed as (2.2) whereW,Cof,VGS,andVtarewidth,gatecapacitance,gatebiasandthreshold voltage,respectively.Theequationiswrittenforsymmetricdouble-gateMOSFETs, butasimilarequationcanbeusedforasymmetricDGMOSFETsorbulkMOSFETs aswell,byproperlychangingthegatecapacitancevalue.Differentiatingbothsides of(2.2)withrespecttogatebias,andassuming(VGS-IDRS / W ) @ VGS,weobserve thatgm/ID 2isindependentof RS / RD .So,bycalibratinggm/ID 2instronginversion atlowVDSthemodelparameters UO and THETA canbeevaluateduniquely. Evaluating RS and RD thenbecomesstraightforward,andcanbeobtainedbysimply forcingthemodelpredictiontomatchthelinearregioncurrent.(Applicationofthis calibration methodology is illustrated in Chapter 4.) Thestrong-inversion,saturation-regioncalibrationcanbedonebytuning VO VSAT and SELFT inaniterativemannertomatchID-VDcharacteristics. Becauseofthecomplexinter-dependenceofself-heatingonchannelcurrent,its difficulttoseparateoutthermalresistanceandcapacitances(turnedonby SELFT ) fromvelocity-overshooteffects(tunedby VO ).However,experiencewithPDSOI devicesshowcalibrationintheabovemannerisusuallyeffectiveandlesstime consuming [Chi01]. TheaccountingforQMeffects,whicharegainingimportanceinshortchanneldevices,classicalornon-classicalCMOSalike,inUFDGusuallydoesnot RONVDSID---------RSRD + W ---------------------Leff2WCofVGSVt ()meffUOTHETA () ---------------------------------------------------------------------------------------------+ @

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15 needanytuningparametereventhoughtotakecareoftheuncertaintiesineffective masses,twomodelparameters QMX and QMD areleftastunable.However,except forholesin{110}Si,thedefaultvaluesofthesetwoparametersaccuratelypredict theQMeffectsduetosolvingthePEandtheSEinaselfconsistentmanner[Ge02a]. Astheeffectivemassesofholesin{110}-pSiarenotconclusivelyknown,theabove twoparametersrequiretuningfor{110}-pSi.Forthispurpose,calibrationofC-V characteristicsisrequired.TheC-Vcharacteristicscanalsobeusedtoextract TOXF / TOXB ;howevertheadvancedgateoxidationprocesscanyieldgatethickness with10%accuracy.Forexample,ifthedesignedgateoxideis1nmthick,the maximumvariationobservedinthethicknessafterfabricationis 1.AsFinFETs areleftundoped,suchsmallvariationinoxidethicknessisnotreflectedinshortchannelcharacteristics(unlikebulk-Sitechnology,wherelargedepletioncharge, QD,makesthethresholdvoltagesensitivetotoxthroughQD/Cox).So,forFinFETs, gettingtheoxidethicknessfromthedesignedvalueissufficient,andcalibrationto simpleID-VGandID-VDcharacteristicsareenoughtoevaluatemostoftheother UFDGmodelparameters.However,asUFDGdoesnotmodelpolysilicondepletion inthegate,theprocessismoreaccurateformetalgatetechnology,whichistheonly viable option for undoped-UTB DG MOSFETs. Withthecalibrationmethodologyoutlinedabove,inthenextfewsections wewillpresentsomecalibrationsofUFDGtobothn-andp-channelFinFETsalong with insights therefrom.

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16 2.3 Calibration of UFDG to AMD nFinFETs WestartourcalibrationwithanAMDfabricatedFinFET[Yu02]ofLg= 105nm.ThebodyofthedeviceisleftundopedandS/Dfinextensionisdopedby0otiltionimplantationwithgatesidewallspacers.Thefinthicknessvariesfrom17nm to26nm,andtheextensionlengthsareof80nmeach.Thenitridedgateoxideis17 thickwithpolysiliconusedasgatematerial.TheUFDGcalibrationresultsareshown inFigure2.2.Eventhoughagoodmatchinweak-inversioncharacteristics, subthresholdslopeandoff-statecurrent,isobtainedforLeff=135nm,whichis30nm longerthanLg,thestrong-inversioncharacteristicsarenotpredictedwell.Thus, UFDGcalibrationisonlypartial.InFigure2.2(b),thestrong-inversioncalibration resultisshown.Withextraordinarilyhigh RS / RD ,UFDGpredictsthesaturationregioncharacteristicswellbutunderestimatesthelinear-regioncurrent.Althoughthe calibrationresultinFigure2.2isfarfromperfect,wegettwovaluableinsightsfrom thecalibrationeffort;oneisthattheeffectivechannellengthinthefabricateddevice islongerthanthephysicalgatelength,andtheotheristhatthesource/drain resistance(RS/D)isveryhighandmaybebias-dependentmakingitimpossibleto match both linear and saturation-region currents with a constant RS / RD InFigure2.3,weshowUFDGcalibrationresultsforashorter-channellengthdevice.Again,wefinditdifficulttomatchID(VGS)inalltheregionswith constant RS / RD ;moreover,intheshorter-channel-lengthdeviceweobservestronginversionLeff,Leff(st)>Lgaswell,butitisnotequaltoweak-inversionLeff,Leff(wk). Theobservationisincontradictiontothattypicallyobservedinbulk-Sitechnology whereLeff
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17 Figure 2.2PartialUFDGcalibrationtoanLg=105nmnFinFET;tSi=26nm.In(a) withLeff=Lg+30nm,themeasuredweak-inversionID-VGScharacteristicsarepredictedwell,butthestrong-inversioncurvesarenot. In(b)withLeff=Lg,andveryhigh,butconstantS/Dseriesresistance,the measuredhigh-VDSstrong-inversionID-VGScharacteristicispredicted well, but the low-VDS and weak-inversion curves are not. -0.4-0.20.00.20.40.60.81.0VGS (V) 10-1210-1110-1010-910-810-710-610-510-4ID(A) VDS=0.1V measured data VDS=1.2V measured data UFDG (Leff=135nm; RD=RS=200 W-m m) 1.2 -0.4-0.20.00.20.40.60.81.0VGS (V) 10-1210-1110-1010-910-810-710-610-510-4ID(A) VDS=0.1V measured data VDS=1.2V measured data UFDG (Leff=105nm; RD=RS=675 W-m m) 1.2(a) (b)

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18 Figure 2.3PartialUFDGcalibrationtoanLg=17.5nmnFinFET;tSi=17nm.With Leff=Lg+26.5nm,themeasuredweak-inversionID-VGScharacteristics arepredictedwell;withshorterLeff=Lg+12.0nm(~2 lD),andveryhigh sourceseriesresistancebutlowdrainresistance,thestrong-inversion curves are predicted reasonably well. VDS=0.1V measured data VDS=1.2V measured data UFDG (RD=100 W-m m, RS=550 W-m m) -0.4-0.20.00.20.40.60.81.0VGS (V) 10-1110-1010-910-810-710-610-510-4ID (A) Leff=44.0nm Leff = 29.5nm 1.2

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19 explanationofLeff>Lgobservedhereliesalsointhediffusionofsource/drain dopantsinthechannel,however,thistimeitisduetothelackofit.InFinFET technology,asmentionedearlier,theextensions(Figure1.1(b))arenotdoped directly,rathertheionimplantedsource/draindopantsareannealedtodiffusethem insidetheextensions.Apparently,thediffusionisnotcontrolledwellenoughandan insufficientnumberofsource/draindopants(NSD)reachthegateedgesleavingthe extensionsnearthegateedgespracticallyundoped.Becauseoftheundopedbodyand thelightlydoped/undopedextensions,theDebyescreeninglength( lD)insuch FinFETsislong,andgatemodulationextendsbeyondthechannelinweakinversion, resultinganLeff,definedasthelengthoverwhichthegatemodulatesthecarrier, longerthanLg.Asthechannelcarrierconcentrationincreaseswithgatebias, lDdecreases,andcarriersbeneaththegatescreenthecarriersintheextensionsfromthe gate-inducedelectricfield.Thus,theLeffshrinksinSI,andhence,eventhough Leff(st) > Lg, Leff(st) < Leff(wk) as found in Figure 2.3. Instronginversion,besidesslightlyelongatingtheeffectivechannel length,thelightlydopedportionoftheextensionalsoincreasestheseriesresistance asevidentinthehigh RS / RD obtainedinFigure2.3.However,theuniquenessofthis componentofparasiticresistancecomesfromthevariationofcarrierconcentration insidetheextensionbygatebias,whichgivesrisetobiasdependenceofthenoted RS/Dandrenderspredictionofstrong-inversioncurrentwithconstant RS / RD ineffective.

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20 2.4 Calibration of UFDG to Freescale Poly-Gate nFinFETs TofurthercorroborateandgeneralizeourinsightsfromAMDFinFET calibrationweemployedUFDGtocalibrateFinFETsfabricatedatFreescale Semiconductor.Inthesedevices,theextensionsareof100nmeach,physicalgate lengthis100nm,andfromTEMmeasurementsfinthicknessisfoundtobe~30nm. ThecalibrationresultsareshowninFigure2.4.Theweak-inversioncharacteristics arepredictedwellwith DL =-18nm,i.e.,Leff(wk)>Lg.Thefinthicknessisfoundto be32nm,2nmthickerthanthatisfoundinTEMmeasurement.Thegatework functioninferredfromthecalibrationresultsinapolydopingdensityof~4x1018cm-3,whichissignificantlylessthanwhatisobservedinbulk-Sitechnology.Also thegate-induceddrainleakage(GIDL),acommonfeatureindeviceswithoverlaps, isabsentintheI-VcharacteristicsofFigure2.4,whichisconsistentwiththenegative DL foundfromthecalibrationthatindicatesinsteadofoverlapsthesedeviceshave underlaps. Instronginversion,thistimearoundwetriedtoobservetheevolutionof RS / RD withgateanddrainbiasesbyincrementallymatchingtheUFDGprediction withthedataasshowninFigure2.4(b).Wefindthatwiththeincreaseofgatebias inthelinearregion, RS / RD graduallydecreasesduetothefactthatanincreaseof gatebiasincreasescarrierconcentrationintheunderlapregions.Athighdrainbias, aconstant RS / RD resultsinagoodmatch,indicatingasaturationofcarriersinthe underlapregions.Notethatwhile RS reducesboththeeffectivegateanddrainbias, RD onlyreducestheeffectivedrainbias,andaslongas RD isnothighenoughto

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21 Figure 2.4PartialUFDGcalibrationtoanLg=100nmnFinFET;tSi=32nm,and tox=2.47nm.(a)Goodmatchinweakinversionisobtainedwith DL =18nm,and(b)thestrong-inversioncharacteristicsarepredictedwellwith bias-dependent parasitic resistance. -0.5-0.3-0.1 0.1 0.30.50.70.91.11.3VGS (V) 10-910-810-710-610-510-4ID (A) Measured Data UFDG: Leff = 118nm VDS = 50mV 1.5V tSi = 32nm10-1210-1110-1010-31.5VGS (V)ID (A) Measured Data UFDG: Leff = 100nm -0.5-0.3-0.10.10.30.50.70.91.11.31.5 10-1210-1110-1010-910-810-710-610-510-410-3 VDS = 50mV 1.5V 330 280 250 220 200 180RS=RD=360 W m mRS=425, RD=180 (a) (b)

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22 drivethechanneloutofsaturation,thesaturationregioncurrentisindependentof RD .Theasymmetric RS and RD foundfromthecalibrationthusarenotnecessarily physical.Duetotheprocesssymmetry,itismorelikelythat RS = RD inallbias regions.Also,thereisabitofuncertaintyinthemagnitudesofRS/Dastheremight bepoly-depletion-induceddegradationofthechannelcurrent.However,polydepletioneffectsdonotundermineourRS/D(VGS)conclusionsdeducedhere.PolydepletioneffectreducesID,anditgetsworsewithincreasingVGS[Tau98].Hence, replicatingpoly-depletioneffectwithRS/DwillrequireincreasingRS/Dwithgate bias,whichisnotthecaseobservedinFigure2.4(b).So,thetrendofRS/D(VGS) observedhereisduetothenotedunderlaps,andthepoly-depletioncouldonlyaffect the quantitative interpretation of RS/D(VGS). 2.5 Calibration of UFDG to Freescale Metal-Gate pFinFETs InFigure2.5andFigure2.6calibrationresultsofUFDGtoFreescales metalgatep-channelFinFETsareshown.ThegateisTiNandSiONisusedasgate oxideinthedevicesstudied.Thecalibrationsaredonestartingfromlong-channel devicesfromwhichtransportparametersareobtainedandusedfortheshorterchannelone,where RS / RD neededtuningtogetthestrong-inversioncalibration. NoneofthedeviceshavesignificantSCEs,andtheonlyadjustmentneededinweak inversionisforthethresholdvoltage,whichisdonebytuningthegateworkfunction. VariationoftheTiNgateworkfunction( FM),obtainedfromthe calibrationwithLg,isshowninFigure2.7.WefindthatwithdecreasingLg, FMincreases.Fortheshorter-LgFET,wefind FM~4.6eV,andforthelonger-Lgones,

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23 Figure 2.5CalibrationofUFDGtometal-gatepFinFETswithgatelengthof(a)10 m m, (b)1 m m,(c)0.24 m m,and(d)0.105 m m.AlltheFinFETshavehSi=90mn, tox = 2nm. Key UFDG model parameters are shown in the gure. -1.2 -1.0-0.8-0.6-0.4-0.20.00.2 ID (A) ID (A) 10-1410-1210-1010-810-610-4ID (A) ID (A) -1.2 -1.0-0.8-0.6-0.4-0.20.00.2 -1.2 -1.0-0.8-0.6-0.4-0.20.00.2 -1.2 -1.0-0.8-0.6-0.4-0.20.00.2 10-1410-1210-1010-810-610-410-1410-1210-1010-810-610-1410-1210-1010-810-6VGS (V) VGS (V) VGS (V) VGS (V) Data UFDG L =10 m m, DL =0, TSI =25nm, UO =275 cm2/V.s, RS = RD =0 Data UFDG L =1 m m, DL =0, TSI =25nm, UO =275 cm2/V.s, RS = RD =0 Data UFDG L =0.24 m m, DL =0, TSI =25nm, UO =275 cm2/V.s, RS = RD =450 Data UFDG L =0.105 m m, DL =-14nm, TSI =25 nm, UO =275 cm2/V.s, RS = RD =550(a) (b) (c) (d)VDS = -0.1V VDS = -0.1V VDS = -0.1V VDS = -0.1V -1.2V -1.2V -1.2V -1.2V

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24 Figure 2.6CalibrationofUFDGtoa75nmmetal-gatepFinFET.Goodmatchinboth theweak-andstrong-inversioncharacteristicsisobtainedwithahighRS/ Dand UO =275cm2/V.s.ThenonzeroIDforVGS>0.0Visduetogate leakage current. -1.2-1.0-0.8-0.6-0.4-0.20.00.2VGS (V) 10-1410-1210-1010-810-610-4ID (A) DataUFDG: Leff = 97nm tSi=25nm RS=RD=950VDS = -0.1V -1.2V

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25 Figure 2.7VariationofTiNgateworkfunction(FM)withdrawnlength,(L_drawn)as evaluatedfromUFDGcalibrationdescribedinFigure2.5andFigure2.6. Forthistechnology,L_drawn=Lg+10nm1.Themid-gapgatework function is shown in the dashed line. 1. L. Mathew, private communication Freescale Semiconductor Inc, 2005. 0.01.02.03.04.05.06.07.08.09.010.0L_drawn ( m m) 4.40 4.45 4.50 4.55 4.60 4.65FM (eV) Mid-gap gate

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26 FM~4.4eV.Thefindingsareconsistentwiththeobservationsin[Yag98],whereit wasfoundthatthecrystalorientationofTiNvarieswiththegatelength,andfor shorterchannellengththesputteredTiNhasapredominant(100)orientation, whereasforlongerchannellengthsboth(111)and(100)orientationsarepresent.The (100)TiNhasaworkfunctionof4.6eV.Forthe(111)TiNitis4.3-4.4eV.So,in shorter-Lgdevices,theTiNworkfunctionitwillbe~4.6eVandwillbelessinthe longer-gate-length devices, as observed in Figure 2.7. NotethatlikethenFinFETs,thepFinFETsherealsohavenegative DL as foundfromthecalibrationstotheshorter-Lgdevices,andhighRS/D.Forexample, theshortestgatelengthstudiedhere,Lg=75nm,(Figure2.6)has DL =-22nm. However,theparasiticresistanceisunusuallyhigh( RS =950 W-m m)comparedto thatfoundintheAMDdevicesortheFreescalepoly-gatenFinFETs.Thiscouldbe dueinparttothelowermobilityofholes,andthelessernumberofdopantsinthe extensionscomparedtothatinnFinFETs,and/orduetotheunoptimizedcontact formation process. 2.6 Device Design Implications OurcalibrationofFinFETsfabricatedintwodifferentplantsshowsthe presenceofunderlapinsteadofoverlapinthesedevices.Asthechannelisundoped, excessiveextensiondopingmeasureshavetobeavoidedtopreventpunch-through, thusunderlapmightbeacommonfeatureinnanoscaleFinFETs.Toexplorethe effectsofunderlapsondevicedesign,weusethe2DnumericalsimulatorMEDICI [MED04]tosimulatetheidealizedstructureinFigure2.8.Thestructureisidealized inthesensethatweassumetherearenodopantsintheG-S/Dunderlapregions(LeS/

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27 Figure 2.8Schematiccrosssection(topview)oftheundopedFinFETusedinthe MEDICIsimulations.Theundopedportionofthesource(drain)extension isdenedasLeS(LeD).ThedevicessimulatedinthissectionhavemidgapgateswithLg=18nm,tSi=10nm,toxf=toxb=tox=1nm,unlessstated otherwise. LgLeDLeS tSi toxb Drain Source ExtensionExtension Front Gate Back Gate Body toxf y x

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28 D),andNSD(y)goesabruptlytozerointheextension.Energyquantizationeffects wereturnedoffduringthesimulation.Thedefaultstructureischosenfollowingthe ITRS 32nm node MOS structure [ITR03], with Lg = 18nm, toxf= toxb= 1nm. Figure2.9showstheeffectsofincreasingunderlapson(a)subthreshold swing,S,and(b)ongateworkfunction, FM,whenIOFFisfixedat0.1 m A/ m m.Asthe underlaplengthincreases,theeffectivechannellengthincreases,whichdecreases SCEs,andhenceSdecreases.AlsoevidentinFigure2.9(a)is(i)thattheintroduction ofunderlapscanrelaxthefinthicknessrequirementsand(ii)thatthedecreaseofS ceasesonceLeS/LeD>5nm.Forexample,fo rS=85mV/decade,therequiredtSi= 10nm,withLeS/LeD=0.However,ifLeS=LeD=5nm,thesameScanbeobtained withathickerfin,tSi=15nm.SimilarconclusionscanbemadeforDIBLaswell,as SCEslikeSandDIBLvarywithtSitox/Leff 2(tofirstorder),forreasonableshortchanneleffects[Kim01a].So,anyincreaseintheeffectivechannellengthwillallow relaxationoftSiortox.Asitisdifficulttofabricatethinfilmsreliably,underlapswill beawelcomeadditiontoviableFinFETtechnology.Forlongerunderlaplengths, SCEsareinsensitivetoLeS/LeD(hence,Leff),asforsuchcases,thecouplingoftwo gatesdefinedbythefinthicknessdeterminesthecontrolofSCEs.Hencewenotein Figure 2.9(a) that for longer underlap lengths S is almost independent of LeS. Thevariationsof FMinFigure2.9(b)alsoillustratethatanother advantageofintroducingunderlapinFinFETisthatitwidenstheacceptablerange of FM.TheprominentgatematerialsinconsiderationforFinFETtechnologyare nitridesofTiandTa.Thechoiceofnitrogenconcentrationsinboththegate[Wak01] andtheunderlyingSiONdeterminestheworkfunctionofthegate.Theuseof

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29 Figure 2.9EffectsofunderlapsonthesubthresholdcharacteristicsofaFinFET illustratedbytheMEDICI-predictedvariationof(a)subthresholdswing, and(b)gateworkfunctionrequiredtomaintainaconstantoff-statecurrent with varying underlap lengths. 0.05.010.015.0LeS = LeD (nm) 60 70 80 90 100 110 120S (mV/decade) tSi = 10nm tSi = 15nmLg= 18nm toxf = toxb = 1nm Lg= 18nm, tSi = 10nm toxf = toxb = 1nm 0.02.04.06.08.010.0 4.45 4.50 4.55 4.60 4.65 4.70FG (eV) IOFF = 100nA/ m mLeS = LeD (nm)(a) (b)

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30 underlapsthuscanaddflexibilityinthechoiceofneedednitrogenconcentrationin the gate or in the SiON. InFigure2.10,thevariationofIONandIOFFwithLeS/LeDisshown. IncreasingtheunderlaplengthsincreasesLeff,whichreducestheSCEsandhence IOFFdecreasesexponentially.Ontheotherhand,increasingtheunderlaplengths increasesRS/DandIONdecreasestoo.NotethatforLeS=LeD<4nm,increaseofIOFFisabruptandsuchsensitivitywillpreventreliabledesignwithLeS/LeDshorterthan 4nm.Ontheotherhand,longerunderlaplengthsincreasetheresistance,andhavea diminishingeffectonSCEs.Hence,fromFigure2.9(a)andFigure2.10,weconclude thattherangeofusefulunderlaplengthsfortheFinFETsconsideredhereis~4-6nm. Indeed,apragmaticFinFETdesign,withaGaussiansource/draindopingprofile, proposedin[Tri05a],showsthatanoptimum18nmFinFETshouldhave4.5nmof underlaponeachsideofthegates.Furtherdiscussiononsuchpragmaticdesignwill be presented in Chapter 5. Notethatwerefrainfromtakinganyquantitativeinterpretationof ION(LeS/LeD)inFigure2.10.ThetransportmodelsinMEDICIthatareappropriate forbulk-Siarenotcalibratedforthin-bodyFinFETsandhence,whiletheeffectsof parasiticresistanceswillbereflectedproperlyinMEDICIpredictions,uncertaintyin theMEDICIchannelmobility/velocitysaturationmodelwillintroduceuncertainties inthepredictedION,thusION(LeS/LeD)inFigure2.10shouldonlybeinterpretedin qualitative terms. Figure2.11showstheeffectsofasymmetricunderlapsondevice performance.InFigure2.11(a)thevariationsofDIBLandSareshownforincreasing

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31 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0ION (mA/ m m) ION 0.05.010.015.0LeS=LeD (nm) 10-1110-1010-910-810-7IOFF (A/ m m) IOFF F igure 2.10MEDICI-predictedvariationofIONandIOFFoftheFinFETdenedin Figure 2.8 with underlap lengths LeS/D; VDD = 1.2V.

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32 Figure 2.11MEDICI-predictedvariationofFinFETperformance,(a)SCEs,and(b) ION/IOFF,withthepositionofthegateintheextension.Simulationisdone bykeepingthetotalextensionlength,LeS+LeDconstant.Insetin(a)shows thevariationofthresholdvoltagewhenthegateismovedawayfromthe center (i.e, when LeS = LeD = 13nm). (a) (b) 70 72 74 76 78 80S (mV/decade) S 0510152025LeS (nm) 40 50 60 70 80 90 100 110 120DIBL (mV/V) DIBL LeS (nm)Vt (V)VDS=0.1V 0.05.010.015.020.025.0 -0.23 -0.22 -0.21 -0.20 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0ION (mA/ m m) 0510152025LeS (nm) 0 1 2 3 4 5 6 7 8 9 10IOFF (nA/ m m) VDD=1.2V

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33 LeSforaconstantLeS+LeD=26nm.ForLeS=LeD=13nm,i.e.,whenthegateisin themiddlewithsymmetricunderlapsonbothsides,DIBLandSareminimum. Subthresholdslope,whichisdefinedbyLeff,anddoesnotdependonthegate position,exceptwhenthegateisverynearthesource/drain,andspilled-over electronsfromsource/drainreducegatecontrolbycreatinganG-S/Doverlapregion likethatinthebulk-Sidevices(thedifferencebetweentheoverlapregioninthebulkSideviceandtheFinFETinFigure2.11(a)isthatinthebulk-SiMOSFETtheoverlap regionisduetotheencroachmentofS/Ddopants,whereasfortheFinFETisdueto thespilled-overmobilecarriersfromS/D).Similarly,theoffstatecurrentinFigure 2.11(b)alsoremainsrelativelyconstantwiththegateposition.Theon-statecurrent, however,ismaximumwhenthegateisnearthesource,understandablyso,asthe smallerLeS,thelessthereductionofeffectivegatebiasbyReS,theresistancedueto LeS. The optimum FinFETs, thus, should have LeS > LeD. 2.7 Summary WehavepresentedinsightsfromcalibrationsofUFDGtoFinFETdata thatexplainthegoodshort-channeleffectsobservedindatawithLg~tSi.The calibrationresultsshowthattheG-S/DunderlapinthenanoscaleFinFETselongates Leffandintroducesabias-dependentcomponentintheparasiticRS/D.Wealsofound that due to the underlaps, GIDL is absent in the FinFET. Designissueswiththeunderlapswereexploredthroughnumerical simulations,whichshowthatlongerLeS/DisneededtominimizeIOFFsensitivityto LeS/Dvariations(consistentwiththefindingthattogetgoodSCEsLeff>2tSi[Yan05]).Conversely,tokeeptheresistancelow,LeS/LeDshouldbeminimum.The

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34 advantageofunderlapsinrelaxingthefinthicknessandthegateworkfunction requirementwasillustrated.Also,probableFinFETdesignwithasymmetric underlapswasdiscussed,anditwasconcludedthathavingalongerunderlaplength inthedrainsideisoptimum,asshorterunderlaplengthinthesourcesidereducesthe reduction of effective gate bias due to the resistive drop across the underlap. ThecalibrationresultsalsopointedoutsomerequiredupgradesinUFDG, namelymodelingofbias-dependentLeffandRS/Dduetounderlaps.Inthenext chapter,wewilldealwithsuchmodelingissues,aswellasfurtherapplicationsof UFDG, with the effects of underlaps incorporated.

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35 CHAPTER 3 UFDG UPGRADES FOR NANOSCALE FINFETS WITH UNDERLAPS 3.1 Introduction Asobservedinthepreviouschapter,thepresenceofgate-source/drain underlap,withanundopedUTB,introducesvariationofthegate-controlledareawith biasthatgivesrisetoabias-dependenteffectivechannellength,andaddsanonohmiccomponenttotheparasiticresistanceoftheFinFET.Inthischapter,ourfocus willbeontheanalysisandUFDGmodelingofsuchnovelfeaturesandtheireffects onFinFETcharacteristicsinbothweakandstronginversion.Theweak-inversion discussionwillbeconcernedwithamodificationoftheweak-inversioncurrent formalismthatiscompatiblewithcompactmodels,whilethestrong-inversion discussion will center around the properties of the parasitic resistances. InacompactmodelforaMOSFET,theweak-inversioncurrentis calculatedneglectingdriftcurrent,andthepotentialprofileinthechannelisobtained bysolvingthe2DPoissonequation(PE)usingthedepletionapproximation.Forthe FinFET,thegate-controlledregionextendsbeyondthechannelandpresents differentboundaryconditionsforthePE,whichrequiresextensionofthecompact modeldevelopedforconventionalDGMOSFETs.Hence,wefirstcheckthe applicabilityofUFDGforpredictingweak-inversioncharacteristicsofnanoscale FinFETs,andthentherequiredmodelupgradeswillbepresented.Beforedelving intotheFinFETweak-inversioncharacteristics,wefirstbrieflyreviewtheweakinversion current model in UFDG.

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36 3.2 Calculation of Weak-Inversion Current in UFDG 3.2.1 Review of Weak-Inversion Current Model in UFDG UFDGsolvesthePEinweakinversionassumingnegligiblecarriersinthe channel[Yeh96].TheeffectivechannellengthLeffinthemodelisthelengthover whichthesolutionofPEissought.InDGMOSFETs,Leffisdefinedby(2.1),where the channel within Leff is completely covered by the gate. The 2D PE, (3.1) withthepotential f referencedtoahypotheticalneutralbody,issubjectedtothe boundaryconditionsshownintheschematiccross-sectionofaDGMOSFETin Figure3.1(a).Thechannelissurroundedbythegateinthetransversedirection,and bythehighlydopedsourceanddraininthelateraldirection.Withthegateoverthe entireeffectivechannellength,theboundaryconditionsinthetransversedirection are clearly defined by the gate-induced electric fields, (3.2) whereVGf/bSisthefront/backgatebias, eox/sistheoxide/silicondielectricconstant, VFBf/bistheflat-bandvoltageofthefront/backgate,Esf/bisthefront/backsurface theelectricfield,and fsf/bisthefront/backsurfacepotential.Inthelateraldirection, theboundaryconditionsaredefinedbythesource/drain-channelbuilt-inpotential. Theinherentassumptionhereisthatsource/draindopingisinfinite(i.e.,thepotentialx 2 2 fxy () y 2 2 fxy () qN A e s ----------@ + x fx 0 = E sf y () e ox e s --------fsf y () V GfS V FBf () t oxf -------------------------------------------------------------x fxtSi= E sb y () e ox e s -------V GbS V FBb ()f sb y () t oxb ---------------------------------------------------------------= = = =

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37 Figure 3.1BoundariesforthesolutionofPoissonsequationintheDGMOSFET.(a) InaconventionalDGMOSFETtheboundaryconditionsarewelldened onallfoursidesby(3.2)and(3.3).(b)Inanundoped-UTBFinFET,with undopedextensionsaspartofthechannel(oflengthLeS,andLeD),the boundaryconditionsarenotwelldened.Fromy=LeStoLeS+Lg,the electriceldsareeasilyobtainedfrom(3.2),butfromy=0toLeS,ory= (Leff-LeD)toLeff,theelectriceldscomefromthefringingeffectofthe gates that complicate the solutions of PE inside the box [(0,0);(tSi,Leff)]. Back Gate Front GateDrain x y (tSi,0) (0,0) (0,Leff) Channel Esb(y) Esf(y)fbfb+ VDSSource(tSi,Leff) Lg D L/2 D L/2 Leff Source Back Gate Front Gate y Channel (tSi,0) (0,0) (0,Leff) (0,LeS) (0,Leff-LeD) fbfb+ VDSEsf(y) Esb(y)Drainx (tSi,Leff) Lg LeSLeD(i)(ii) (iii)

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38 dropacrossthequasi-neutralS/Dregionisneglected),whichgivesabiasindependentpotentialattheboundaryanddefinestheboundaryvaluesforthePEin the y direction as (3.3) Asolutionof(3.1)subjecttotheboundaryconditionsin(3.2)and(3.3)is [Yeh96], .(3.4) Here, g istheconstant(in y )inverselengthscale,whichindicatestheseverenessof the SCEs in the channel at any x and is given as .(3.5) Alsoin(3.4),Kisthe1Dpotential,foundfromthesolutionofthe1DPEinthe vertical direction and is related to the gate biases as ,(3.6) where the structure-dependent constants are defined asY x 0 ()fb Y xL ()fb V DS.+ = =fxy () 1 sinh g L eff () -----------------------------Kfb V DS ++ () sinh g y () Kfb + () sinh g L eff y () () + [] K = g x () 2 g o 1 x C of e s --------x 2 g o + ----------------------------------------g o 1 C of C ob ---------C of C b --------++ t b 2 1 2 C of C b ------------+ -----------------------------------= ; = K g 2 CV FBb V GbS () BV GfS V FBbf () qN A 2 e s ----------+ =

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39 ,(3.7) and .(3.8) Theminimumpotentialalong y atany x fm(x),isobtainedbysolvingfor y = ym such that the lateral electric field is zero. From (3.4) we find Ey and ym as (3.9) (3.10) Wenotethat,whenVDS=0,ym=Leff/2.Oncetheminimumpotential, fmisfound, the diffusion length, Le in the channel is calculated by, ,(3.11) with ,(3.12) andBB o g + 2 x () C of e s --------B o x 2 + B o ; C of C ob ---------C of C b --------+ t b 2 1 2 C of C b ------------+ -----------------------------------== CC o 1 g x () 2 + () C o ; t b 2 1 2 C of C b ------------+ 1 == y fEy g sinh g L eff () -----------------------------Kfb V DS ++ () h cos g y () Kfb + () h cos g L eff y () () [] = = y m 1 g -1 g L eff () cosh -----------------------------Kfb V DS ++ Kfb + ----------------------------------g L eff () tanh .atanh = L e L eff L S L D @ L S 2fbfm [] y y y 0 = ----------------------------@

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40 .(3.13) In(3.12)and(3.13),thelengthsLSandLDrefertothedepletionlengthsinsidethe channelnearthesourceanddrain,respectively,asillustratedinFigure3.2.The channel current is assumed to be due to diffusion only, and is approximated as .(3.14) Here,Q(Ls)istheintegratedcarrierdensityatthevirtualsourceandisexponentially dependenton fm[Yeh96];q,VT,Dn,areelectroncharge,thermalvoltageand diffusionlength,respectively.So,thecurrentismainlydependentontwovariables, exponentiallyon fmandlinearlyonLe -1.InUFDG,thechannelisseparatedinto multiplestripsalong x, and(3.14)isusedtocalculatethecurrentineachstrip [Tri05b].Thetotalcurrentisthenobtainedbysummingupthecontributionsofall the strips. 3.2.2 Source/Drain-Body Junction Potential Therearefewassumptionsintheabovemodelfortheweak-inversion currentinDGMOSFET.Oneistheboundarycondition(3.3),whichsaysthe potentialat y=0is fixedat fb,assumedtobethebuilt-inpotentialVbiand approximated as (for a p-type body), ,(3.15)L D 2fbfm V DS + [] y fyL eff = ----------------------------------------------@ I wk qD n QLS() Le--------------1 V DS V T -------------exp @fb E g 2 -----kT q -----N A n i -------ln + @

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41 Figure 3.2LateralpotentialproleinweakinversioninthechannelofatypicalDG MOSFET.ThediffusionlengthLeisobtainedbysubtractingLSandLD, whicharecalculatedbyextrapolatingtheelectriceldsatthesource / channel (y = 0) and drain/channel (y = Leff) boundaries, from Leff. Lef( tSi/2,y) fm Leff0 LS/2 LD/2

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42 i.e.,themodelassumestheFermilevelinthesourceisalignedwiththesource conductionband.In(3.15),Egisthesiliconbandgap,niistheintrinsiccarrier concentration,andkistheBoltzmanconstant.Foratypicaldopingdensityof 1x1020cm-3, fbcanbe~2kT/qhigherthanthatpredictedby(3.15)ifFermi-Dirac (F-D)statisticsareused.BesidestheinherentapproximationofMaxwell-Boltzman (M-B)statistics,(3.15)alsoassumesthatthereisnospatialvariationofcarrier densityinsidethesource/drain.Inreality,however,therewillalwaysbesome carriersspillingoverintotheundopedchannelfromthesource,andthepotential profileinthesourcewillbeafunctionofgatelength,filmthickness,andbiases.A typicalprofileof f (y)acrossthesource-channelboundaryisplottedinFigure3.3 showingthedeviationof fbfromVbi,thepotentialinsidethesourcewherethecarrier densityequalsthedopingdensity.Theinaccuracy,ifany,introducedbythe assumptionin(3.15)that fb=Vbineedsexaminationbeforeweincorporatethe effects of G-S/D underlap. Toestimatethepotentialatthesource-bodyjunctionaccurately,oneneeds to solve the 1D PE inside the source, ,(3.16) whereNDisthesourcedopingdensityandnsiselectronconcentrationinthesource. Innear-equilibrium,foranundopedbody,nscanbeexpressedassumingM-B statistics as [Tau98], .(3.17)y 2 2 d dfq e s ---n s N D () @ n s n ifV T ------exp =

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43 Figure 3.3Schematicofvariationoflateralpotential(solidline)acrossthesourcechannelboundaryinaFinFETwithabruptdopingprole(dashedline). Due to nite depletion layer inside the source, fb < Vbi. SourceChannel f (y) yVbifb -ys0 ym NDNA

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44 Using (3.17) in (3.16) we find, ,(3.18) whereVbiisthe f wher en=ND.Integrating(3.18)once,andusingaty=-ys, we get .(3.19) Attheboundary(y=0),theelectricfieldandpotentialarecontinuous,so solutionsof(3.1)and(3.16)arenearlythesamethere.Thusequating(3.9)and(3.19) aty=0wecangeta refinedexpressionfor fb,butthesolutionrequiresnumerical evaluation.Asimplerwayistoemploythedepletionapproximationinsidethesource andneglectnsin(3.16).Thenthepotentialattheboundary,intermsoftheelectric field, is ;(3.20) Eb is the electric field at y = 0 and can be approximated from (3.9) for low VDS as .(3.21) ReplacingEbin(3.20)by(3.21),andsolvingtheresultantquadraticequationweget fb asy 2 2 d dfqN D e s -----------fV bi V T -----------------exp1 = y d d f 0 = y d df 2 qV T N D e s --------------------fV bi V T -----------------exp1 fV bi V T ------------------ = fbV bi e s E b 2 2 qN D --------------- = E b g Kfb + () g L eff 2 ------------tanh @

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45 ,(3.22) whereisaconstantin y ,andrelatesthedependenceof fbonthe deviceparameters,i.e.,ND,Leff,andtSi.Notethatin(3.22), fbdependsonthegate bias through K, but the variation is negligible in the weak-inversion region. Figure3.4showsthevariationof fbfrom(3.22)withtSiandLg.Asis evident, fbisindependentofLguntilthelengthbecomestoosmall,andpunchthroughincreasesthedensityofcarriersinthechannel(andattheboundary, increasing fb).WithdecreasingtSi, fbdecreasesasthinnertSienhancesgatecontrol reducingSCEs.Inotherwords,inthe2DPE,,thegradientofthe electricfieldalong x increaseswithdecreasingtSi,andthusdecreasesn(sotoodoes f through(3.17)),foraconstantgatelengthanddrainbias.Thepredictionof(3.22) isingoodagreementwiththatofMEDICI,asshowninthefigure,exceptforthin films,whereinthemiddleofthefilmtheassumeddepletionapproximationis inaccurate.Alsointhefigure,thevariationof fbwith a isshownintheinset.As a goestozero(whichcanhappenwhenND ), fbapproachesVbiasassumedin (3.3).NotethatforapragmaticFinFEThavingtSi>8nm,undopedbody,andLeff(= Lghere)>2tSi, fbisaround0.55VinFigure3.5,aswillbepredictedby(3.15), fb@ Eg/2 = 0.55V. Thepredictionby(3.15)isclosebecausethedeviationof fbfromVbiis compensatedbytheuseofM-Bstatistics(insteadofF-Dstatistics),which underestimatestheactualpotentialforsourcedoping~1x1020cm-3.So,useof(3.15) fb1 2 a -----2 a K 1 + () a K 4 a V bi 1 ++ () + [] @ a eg22 qND-------------h2g Leff2 -----------tan = y d dEqn e ----x d dE + =

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46 Figure 3.4Comparisonofthevariationofboundarypotentialasafunctionoflm thickness(tSi),andgatelength(Lg)asmodeledby(3.22)withthatof MEDICI.FortherstcaseLgissetto18nmandforthelattertSi=10nm isused.VGfS=VGbS=0, WKF = WKB =0,VDS=50mV,toxf=toxb= 1nm,ND=1x1020cm-3,andNA=1.3x1010cm-3areused.Insetshowsthe variation of fb with a in (3.22); as a 0, fb Vbi. 0.05.010.015.020.025.030.035.040.045.050.0Lg (nm) 0.05.010.015.0tSi (nm) 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60fb (V) fbvs. TSi fbvs. Lg Eq. (3.22) MEDICI fb Vbia(0,0)

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47 worksfinefortypicalFinFETs,althoughitdoesnotcapturethedependenceof fbon structuralparameters.(Inthenextsection,introductionofanewparameter SCEB willbediscussed,whichwillhelpinremovingtheuncertaintiesintroducedby(3.15), particularly for undoped UTBs.) 3.2.3 Weak-Inversion Model Verification for DG MOSFET Figure3.5(a)showsthecalibrationoftheUFDGweak-inversionmodelto MEDICI-simulatedDG-MOSFETcharacteristics.Theexcellentmatchcorroborates themodelvalidityforDGMOSFETs.Figure3.5(b)showsthecomparisonofUFDGpredicted f (y)withthatofMEDICIforthesamedevice.Notethatboththecurves haveidentical fmandwillyieldidenticalLe.Becausetheweak-inversioncurrentis mainlydependentonthesetwoparameters,ym,andLe,aslongasthecalculationof thesetwoarecorrectin(3.14),UFDG-predictedchannelcurrents,andhenceSCEs, willbevalid.ForconventionalDGMOSFETssuchaccuracyindetermining fmand Le is obtainable by using the exact physical parameters directly in the model. Butfortheundoped-UTBFinFETthemodelisnotdirectlyapplicable sincetheboundaryconditioninsolvingthePEisdifferent.Figure3.1(b)showsthe boundarieswithinwhichthesolutionofthePEissought.Whiletheboundariesinthe ydirectionarestillwelldefined,theboundariesalongthexdirectioninthe extensionsaredefinedbythefringingfieldsfromthegates,whichinvalidatetheuse of(3.2)there.AnexactsolutionforsuchasystemwillinvolvesolvingPEinregions (i),(ii)and(iii)inFigure3.1(b)andequatingthesolutionsattheboundariesof region(i)and(ii),and(ii)and(iii).Suchanexactapproachiscomplexandnot favorableforcompactmodels.Asanalternative,weemployourinsightfromUFDG

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48 Figure 3.5ComparisonofUFDGpredictionswiththatofMEDICIinweak inversion,(a)ID-VGScharacteristics,and(b)potential( f )alongthe channelatx=tSi/2.Thedeviceisanundoped,mid-gapDGMOSFET withLg=18nm,tSi=7nm,andtoxf=toxb=1nm.TherelevantUFDG modelparametersare WKF = WKB =-0.007, NSD =1x1020cm-3, DL = -0.4nm,and NBODY =1.3x1010cm-3.For(b)thegatebiasisxedat0V. Notethatin(a)the DL neededisnonzero,duetotheuncertaintyinthe meshsizeofMEDICI;thedifferenceof7mVintheworkfunctioncanbe attributedtotheslightdiscrepancyinthevaluesofintrinsicdevice parameters,likeni,Egandsiliconafnity, c ,usedinUFDGandMEDICI. -0.2-0.10.00.10.20.3VGS (V) 10-1310-1110-910-710-510-3ID (A) MEDICI UFDG 35404550556065707580y (nm) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8f (V) VDS=1.0V 50mV VDS = 50mV(a) (b)0.4 Lg MEDICI UFDG

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49 weak-inversioncalibrationthatifwecangetthecorrect fmandLeforthisstructure (Figure3.1(b))byusinganequivalentstructurelikethatofinFigure3.1(a),wecan stillreliablypredicttheperformanceofFinFETs.Inthenextsection,theUFDG modelsvalidityforFinFETsisexaminedandrequiredupgradesaredescribedbased ontheinsightsgainedfromtheMEDICI-simulatedFinFETcharacteristicsand UFDG calibrations to those. 3.3 Upgrades in Weak-Inversion Model for FinFET with Underlaps 3.3.1 Model Upgrades ThenanoscaleFinFET(Figure3.1(b))structure,fromsourcetodrain,is basicallyagated n-i-n structurewheretheundopedportion(undoped/moderately dopedextensionsplusthechannel)isfloodedwithelectronsspilledoverfromthe highlydopedsourceanddrain.Theapplicationofgatebiasintheweak-inversion regionmodulatesthecarrierconcentrationovertheentirechannelintheprocessof establishingadrift-diffusionbalance.Moreover,asthelowcarrierconcentrationin theweakinversionisnoteffectiveenoughtoscreenthegate-inducedelectricfield, thegatealsomodulatesthecarriersintheundopedextensions.Figure3.6showsthe MEDICI-predictedvariationofpotentialandelectronconcentrationsbetweensource anddrainwithgatebiasinanundopednanoscaleFinFETforbothlowandhighdrain biases.Asevidentinthefigure,inweakinversiongatemodulatesthecarriersinthe extensions as well as in the channel. The Debye screening length lD is given as,

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50 Figure 3.6MEDICI-predictedsurfacepotentialvariationbetweentheSandD contactregionsofanLg=105nmDGnFinFET(Vt~0)forVGSvarying betweenweakandstronginversion,andfor(a)lowand(b)highVDS;tSi=26nm.Electrondensity(atx=0,tSi)variationcorrespondingtothe potentialvariationin(a)and(b)isshownin(c)and(d),respectively.The entireS/Dn-extensionregions(LeS=LeD=25nm)wereleftundoped, aswasthebody/channel.TheS/Ddopingproleisabruptasshownbythe dotted curve. 1011101210131014101510161017101810191020Doping Concentration (cm-3) 0.050.080.110.140.170.200.23 y ( m m) 0.0 0.1 0.2 0.3 0.4 0.5 0.6Potential (V) LgLeDVGS=-0.5V -0.1V 0.0V 0.2V VGS=1.2V(a) VDS = 0.1VLeSS D(c) VDS = 0.1V 10101011101210131014101510161017101810191020Doping Concentration (cm3 ) 0.050.080.110.140.170.200.23 y ( m m) 10910101011101210131014101510161017101810191020Electron Density (cm-3) Lg LeDLeSVGS=-0.5V -0.1V 0.0V 0.2V VGS=1.2VS D(b) VDS = 1.2 V 0.050.080.110.140.170.200.23 y ( m m) -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8Potential (V) 1011101210131014101510161017101810191020Doping Concentration (cm-3) LgLeDLeSVGS=-0.5V -0.1V 0.0V 0.2V VGS=1.2VS D 0.050.080.110.140.170.200.23 y ( m m) 10810910101011101210131014101510161017101810191020Electron Density (cm-3) 10101011101210131014101510161017101810191020Doping Concentration (cm3 ) LgLeDLeSVGS=-0.5V -0.1V 0.0V 0.2V VGS=1.2V(d) VDS = 1.2 VS D

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51 .(3.23) Inweakinversion,usuallythecarrierconcentratio nn<1x1016cm-3,whichmakes lD>40nm.Suchalongscreeninglengthallowsthegatebiastoalterthecarrier concentrationbeyondthechannel,insidetheundopedpartoftheextensions.Asthe carrierconcentrationgoesupnearthesource(ordrain),thegate-inducedcarrier modulationceases.IftheeffectivechannellengthLeffisdefinedasthelengthover which the gate modulates the carriers, for nanoscale FinFETs it becomes ,(3.24) whereLeSandLeDaretheundopedpartsoftheextensionsnearthegateedgesas shown in Figure 3.6 and Figure 3.1(b). Comparing (3.24) with (2.1) we find that (3.25) iftheUFDGmodelisapplicableforsuchFinFETs.Tocheckthisconjecture,we calibrateUFDGtoMEDICI-simulatedFinFETs.Thegatelengthofthedevice chosenforsimulationis18nm,toxf=toxb=1nm,andtSi=10nm;ithasamid-gap gateanditsbodyisleftundoped.InFigure3.7thecalibrationresultsareshown.The parameter DL (correspondsto D Lin(3.25))inUFDGistunedtomatchtheshortchanneleffects.For(LeS+LeD)=8nmstructure,togetanexcellentmatchinSCEs (DIBLandS), DL istunedto-6.2nm(Figure3.7(a))andfor(LeS+LeD)=10nm,the required DL = -10.4nm (Figure 3.7(b)).l D e V T qn ---------= LeffLeSLgLeD++ =D LLeSLeD+ () =

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52 Figure 3.7UFDGcalibrationtoaMEDICI-simulatedmid-gapFinFETwith(a)LeS=LeD=4nmand(b)LeS=LeD=10nm.Otherdevice/modelparameters areLg=18nm,tSi=10nm,toxf=toxb=1nm.UFDGmodelparameter DL istunedto(a)-6.2nm,and(b)-10.2nm.Quantum-mechanicaleffectsare turned off in both the simulators. -0.2-0.10.00.10.20.3VGS (V) 10-1410-1210-1010-810-6ID (A/ m m) MEDICI UFDG (a)(b) -0.2-0.10.00.10.20.3VGS (V) 10-1310-1110-910-710-5ID (A/ m m) MEDICI UFDG VDS=1.0V 50mV VDS=1.0V 50mV

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53 LeS(LeD),asdefinedinFigure3.1(b)aswellasinMEDICIsimulations, isarathertechnologicaldefinition,i.e.,itisdefinedasthedistancefromthegate edgetotheplane,wherethesource(drain)dopingfallsabruptlytozero.However, LeS(LeD)in(3.24)definesthesource(drain)extensionlengthoverwhichthegate effectivelycontrolsthecarriers.FromFigure3.6itisevidentthatnearthesource (drain),gatedoesnotmodulatethecarriersduetotheshorterscreeninglengththere. Thus, (3.24) can be modified as ,(3.26) where lD(nb)istheDebyelengthcorrespondingtothecarrierconcentrationatthe boundary,nb.Thetypicalvalueof lDis~1nm,correspondingtoanaveragedoping densityof1x1019cm-3nearthesource/drain.Consideringthis,forshorterLeSand LeDinFigure3.7(a),(3.26)holdstrue.Thatis,whentheundopedextensionsare smaller(~4nm),UFDGisapplicabletoFinFETstructureswithits DL indicatingthe amountofgateunderlap.ButforlongerLeSandLeD,the DL requiredforpredicting similarSCEsisalmosthalfofLeS+LeDanddoesnotcorrelatedirectlytothe underlap lengths. Beforedrawinganyfurtherconclusion,welookintothecalibrationresults againinFigure3.7.ItisclearthatwhileUFDGispredictingtheSCEswell,itis overestimatingthemagnitudeofthechannelcurrentIwk,whichismoreevidentfor thelongerunderlaps.Toinvestigatefurtherwelookatthepotentialprofilealong y predictedbybothUFDGandMEDICI.Figure3.8showsthepotentialprofileforthe deviceinFigure3.7(a)atlowdrainbiaswithVGfS=VGfS=VGS=0V.Whilethe LeffLeSLgLeD 2lDnb () ++ =

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54 Figure 3.8MEDICI-andUFDG-predictedpotentialprole, f( y ) (a)alongthe channeloftheFinFETsimulatedinFigure3.7(a),and(b)potential proleforthesamedeviceasin(a)withtheboundaryvalue fbtaken fromtheMEDICIsimulationratherthanthatpredictedby(3.15).Inset in (a) shows the zoomed-in prole near the metallurgical boundary. 35404550556065707580y (nm) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8f (V) MEDICI UFDG 4647 48y (nm) 0.45 0.50 0.55 0.60 0.65f (V) LeDLeS 35404550556065707580y (nm) 0.05 0.15 0.25 0.35 0.45 0.05 0.65f (V) MEDICI UFDG Lg LeDLeS Lg(a)(b)VGS = 0V VDS = 0.05V VGS = 0V VDS = 0.05V

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55 UFDG-predictedprofilecloselyfollowsthatofMEDICI,theminimumpotential predictedbyUFDGisafewmillivoltshigherthanthatofMEDICI,whichresultsin theoverestimationofUFDG-predictedIwk,asfrom(3.14)log(Iwk) fm.This overestimationisindependentofgatebias,whichisevidentfromFigure3.7,where ashiftinthevoltageaxistowardstherightforUFDG-predictedcharacteristicswill yieldanexactmatchofIwkbetweenMEDICIandUFDGsimulations,forallthebias pointsinweakinversion.Theexpression(3.4)for fmusingym=Leff/2forlowVDS(from (3.10)), after some algebraic manipulation becomes .(3.27) In(3.27)thebiasdependencecomesfromK.Then,theonlyparameterthatgivesa bias-independent variation of fm is fb, as .(3.28) AsshownintheinsetofFigure3.8(a),theboundaryvalueof fbforthe UFDGsimulationishigherthan(aspredictedby(3.15))thatofMEDICIsimulation. IfweusetheMEDICI-predicted fbintheUFDGmodel,andcomparethetwoprofiles ofFigure3.8(a),asshowninFigure3.8(b),wefindthattheminimumpotentialis identicalforthetwocases.So,themismatchinIwkinFigure3.7isduetotheuseof inaccurate fb.Tocheckthisconclusionfurther,thecalibrationsinFigure3.7are repeatedinFigure3.9,where fbusedinUFDGisextractedfromthecorresponding MEDICIsimulation.ExcellentmatchesinIwk,S,andDIBLareobtained,implying fm Kfb+ () g Leff2 ------------K sech =fbd dfm g Leff2 ------------sech =

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56 Figure 3.9Recalibrationofthe18nm-FinFETinFigure3.7.Thevalueofthe boundarypotential fbusedinUFDGisextractedfromMEDICIfor both (a) the shorter-underlap, and (b) the longer-underlap FinFET. -0.2-0.10.00.10.20.3VGS(V) 10-1310-1110-910-710-5ID (A/ m m) MEDICI LeS = LeD = 4 UFDG DL = -6.2 -0.2-0.10.00.10.20.3VGS(V) 10-1410-1210-1010-810-6ID (A/ m m) MEDICI LeS = LeD = 10 UFDG DL = -10.2 (a) (b)VDS=1.0V 50mV 50mV VDS=1.0V

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57 thatalongwiththetuned DL fbalsohastobeclosetothephysicalvaluetopredict thecharacteristicsofFinFETreliably.Inaddition,togetacorrect fm,accuracyin fbalsoaidsingettingthecorrectelectricfieldattheboundary.AsseenfromEqs. (3.11)-(3.14),LedependsontheelectricfieldattheboundaryEb,aswellason fm. From (3.21), ;(3.29) i.e.,overestimationof fbwilloverestimateEb,whichinturnoverestimatesLein (3.13),andsounderestimatesthecurrent.Forshort-channeldevicessuch overestimationofLein(3.14)iscompensatedbytheoverestimationof fm.However, forlong-channeldevices,theminimumpotentialismainlyinfluencedbythevertical fieldandthevariationof fbhasanegligibleeffecton fm(asevidentfrom(3.28), sech( g L/2) 0asL/tSibecomeslarge),sooverestimationof fbwillmainlyresultin overestimating Le and thus underestimating Iwk. Modeling fbforFinFETswithunderlap,alongthelinesof(3.22)fornonunderlapdevices,requiresanumericalsolutionofthePEintheextension. Nonetheless,wecangetasimplemodelfor fbusingourinsightsfrom(3.26).As definedearlier,LeS(LeD)isthelengthfromthegateedgetothesource(drain) contactwherethegate-inducedmodulationceases.Sotheeffectivechannel boundaryinthe x-z planeiswherethecarrierdensityishighenoughtogivea negligible lDandisabletoscreenthesource(drain)carriersfromthegate-induced field.LookingatFigure3.6,thecarrierdensityintheextensionswheregatebiasfbd dE b g h g L 2 ----tan =

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58 dependentmodulationisnegligibleis~1x1019cm-3.So,thepotential fbatthat point can be expressed as ,(3.30) where nb = 1 x 1019cm-3. Thevalueofnbchosenherevarieswiththedevicestructure;forexample, forsevereshort-channeleffects(i.e.,whenLeff/tSiissmaller),theelectron concentrationattheboundaryincreasesduetoincreasedpunch-through,yieldingan increasein fb.Besides,theuseofM-Bstatisticsalsointroducessomeuncertaintyin (3.30).So,weintroduceanewuser-definedmodelparameterinUFDG, SCEB such that .(3.31) Valuesof SCEB arepositiveandusuallyliebetween0and1.Alongwith thisparameter,wealsointroducetwomoreparameters, LES and LED corresponding tothelengthsLeSandLeDin(3.24).Thesetwolengthparametersreplacethe parameter DL inUFDG,butunlike DL ,thecontributionof LES and LED inLeffis bias-dependent, as we will show in the next section. 3.3.2 Verification and Utility Withthreenewmodelparameters, LES and LED definingLeffin(3.24), and SCEB removingtheuncertaintiesin fbin(3.31),thedescriptionofweakfb V bi V T N D n b -------ln =fb V bi SCEB () V T N D n b -------ln =

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59 inversioncurrentIwkin(3.14)isnowcompleteforfaithfullypredictingtheweakinversioncharacteristicsofnanoscaleFinFETs.Inthissectionwepresentfurther calibrationresultstocorroborateUFDGsvalidityinsuchpredictions.Togetthetest data,weagainuseMEDICI.Alongwiththe10nm-thick-filmdevice,wealso simulateadevicewiththickerfilm,tSi=15nm,tocheckthemodelsviabilityfor deviceswithdegradedSCEs.InourMEDICIsimulations,weuseaconstant-mobility modeltoavoidnon-physicalvariationsofmobilityintheweak-inversionregion, whichispresentinsomeofthemobilitymodelsinMEDICI.EarlierUFDGmodels, usedinthissection(aQM-basedmobilitymodel[Tri05b],incorporatedintherecent UFDGversions,isdiscussedinChapter4),takecareofthedependenceofmobility onfilmthickness[Chi01],whichisabsentinMEDICIsconstant-mobilitymodel.To havethesimilarmobilityinboththesimulations,UFDGlow-fieldmobility UO is setto820cm2/V.sand670cm2/V.sfortSi=10nmand15nm,respectively,whereas inMEDICI,thelow-fieldmobilityisspecifiedas600cm2/V.sregardlessofthefilm thickness.Also,quantum-mechanicaleffectsarenotincludedineitherMEDICIor UFDG simulations. InFigure3.10,UFDGcalibrationtoMEDICI-simulated15nm-thick-film FinFETisshown.UFDGspredictionofIOFF,S,andDIBLarepreciseforboth deviceswithtotalunderlapof(a)8nm,and(b)16nm.InFigure3.10(a),valuesof LES and LED areclosetothoseofLeSandLeDinMEDICI,implyingthatforshorter LeSandLeD, LES and LED tellustheamountofunderlapinthedevice.Forshorter underlaps,thecarriersintheextensionsaresupportedbyboththelongitudinalfield andtheverticalfringingfieldfromthegate.AsseenfromFigure3.11nearthegate

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60 Figure 3.10CalibrationofUFDGtoaMEDICI-simulated15nm-thicknFinFETwith (a)smallerunderlaps,and(b)longerunderlaps.Allotherdevice parameters are the same as in Figure 3.7. -0.20-0.100.000.100.200.30 10-1310-1110-910-710-5 VGS (V)ID(A)(b) (a)VDS=1.0V 50mV MEDICI LeS= LeD = 10 UFDG LES = LED = 5.55, SCEB = 1.1 -0.30-0.20-0.100.000.100.20VGS (V) 10-1210-1010-810-6ID(A) MEDICI LeS= LeD = 4 UFDG LES = LED = 2.95, SCEB = 0.7 VDS=1.0V 50mV

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61 Figure 3.11MEDICI-simulatedelectriceldvectorinthex-yplaneoftheFinFETsof Figure3.7withVGfS=VGfS=VGS=0.1VandVDS=50mV.Thegateis spannedfrom50nmto68nm.In(a)LeS=LeD=4nmandin(b)LeS=LeD= 10nm. S D S D FG BG BG FG LgLg(a) (b)

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62 edges,intheextensions,theelectricfieldis2Dinnature,thus(3.1),withits boundaryconditions(3.2)and(3.3),holdstrue,aslongasLeSandLeDare~4nmor less.ThephysicalnatureoftheUFDGmodelforsuchshorterlengthsthusallowsus, through LES and LED to extract the amount of underlaps in the devices directly. Figure3.11(b)showstheelectricfieldvectorforlongerLeSandLeD.The fieldisclearly1Dinnatureinmostpartsoftheextensions.So,theUFDGmodelin suchcasesbasicallypresentsanequivalentstructureofthedevicewithunderlap, whereLeff(asin(3.24))representsaneffectivelength,whichallowsUFDGto predictthecorrectdiffusionlengthLeandminimumpotential fm.So,thereisno directcorrelationbetween LES and LED withactualunderlapinthedevicewhere LeSandLeDarelonger.However,the LES and LED inUFDGcanstillbeeffectively usedingatheringinformationregardingtheamountofunderlapinthedevice.In Figure3.12,UFDG-predicted( LES + LED )vs.actualunderlaplengthinthe MEDICI(LeS+LeD)simulationisplottedfortwodifferentfilmthicknesses.Forboth devices,UFDGpredictsshorterunderlapsquitecorrectly;forlongerunderlapcases, itspredictionisaround50%oftheactualunderlaps.Fromthisempiricalobservation, wethusconcludethatfordeviceswithlongunderlaplengths(>4nm),UFDG parameters LES and LED roughly indicate half of the underlap lengths. NotethatfromFigure3.12,foraparticularunderlaplength,theUFDGpredictedLeff(definedby LES and LED )isalmostindependentoftSi.Itisexpected, becauseiftSiisthinenoughtohavesufficientgate-controlalloverthefilm,thenLeff, i.e.,thegatecontrolofcarriersinthelateraldirection,willbeindependentoftSi. However,iftSiissothickthatthedrainhasmorecontrolofthecarriersinthemiddle

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63 Lg= 18nm toxf = toxb = 1nm Figure 3.12ComparisonofUFDG-predicted LES + LED (closedsymbols),obtained bycalibratingtoMEDICI-predictedWIcharacteristics,withthetotal underlapsoftestFinFETsfortwodifferentlmthicknesses:10nm (circles)and15nm(squares).Thetuned SCEB (opensymbols)inUFDG for the respective underlaps are also shown. 0.0 0.5 1.0SCEB 0.05.010.015.020.0Total Underlap Length (nm) 0.0 5.0 10.0 15.0LES + LED (nm) (square) tSi = 15nm (circle) tSi = 10nm

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64 ofthefinthanthegate,wecanexpectforaparticularunderlaplength,Lefftobe smallercomparedtothatofathinnerfilmFinFET.Infactinthefigure,thethickerfilmdevicehasslightlysmaller LES + LED (whenLeS+LeD<3nm)comparedtothe thinner film one, consistent with our understanding of Leff(tSi). Also,inFigure3.12the SCEB requiredforcorrespondingunderlapis plotted.Withtheincreaseofunderlaplengths,therequiredvaluesof SCEB increase. Thisisbecauseforthelonger-underlapdevices,theshort-channeleffectsare reduced,therebyreducingthepotentialattheboundary,andthusnecessitatingan increasein SCEB in(3.31).Usuallythevalueof SCEB willliebetween0and1,as inthefigure.But,forlongchanneldevices,orwithlongerunderlaps,itmaygo beyond 1. 3.4 Upgrades in Strong-Inversion Model for FinFET with Underlaps 3.4.1 Effective Channel Length Weobservedwithgatebiasthecarrierconcentrationinthechannel(ns), aswellasthatintheG-S/Dextension(neS/D)increases.However,asnsreaches~ 1019cm-3instronginversion,itscreensthegate-inducedelectricfield,as lDdecreasesandpreventsgate-inducedmodulationofcarriersintheextension.The phenomenaisdepictedinFigure3.6,wherewefindthatgate-inducedmodulationof neS/Dceasesafterthegatebiasdrivesthedeviceintothestrong-inversionregion. Thatis,inSIthereisnocontributionofLeS/LeDtoLeffin(3.26),whichinSIshrinks to .(3.32)L eff L g 2 l D ns() +L g@=

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65 Withns~1019cm-3,thecontributionof lD(ns)in(3.32)issmallcomparedtoLg, hence,Leff@ LginSIisareasonableapproximation.Indeedinthecalibrationsin Chapter2,wehavefoundthatLeff@ LginSIforlongerdevices.(Thediscrepancyin SI-LeffandLginFigure2.3forthe17.5nmFinFETcouldbeduetothehighRS/D, whichreducestheeffectivegatebias,i.e.,inversioncharge,andhence,increases lD. Also,thelongerLeffobtainedmightalsobeaccountingforthedecreaseofIDdueto thepoly-depletioneffects.)Thevalidityof(3.32)forshorterchannellengthswillbe shown later in this section, after discussing the parasitic resistances. Notethedifferenceinthemanner D LandLeS/LeDcontributetotheLeff. Theoverlapalwaysreducestheeffectivechannellength,regardlessofthegatebiases asevidentin(2.1),whereastheunderlapslengthenLeffinweakinversionbutdonot affectLeffinstronginversion.SuchbiasdependenceisincorporatedinUFDGby modelingstrong-inversionLeffby(3.32)butignoringthecontributionof lD(ns).The shrinkingofLefffrom(3.24)to(3.32)inUFDGisimplicitinthemoderate-inversion spline,whichisdefinedbytheweak-inversionandstrong-inversioncurrentsthatare governed by the respective Leff. 3.4.2 Parasitic Resistance Eventhoughinstronginversion,theextensionsdonotcontributetoLeff, theyaddanadditionalcomponenttotheparasiticresistance.Theconcentrationof carriersintheextensionsthatdefinetheresistanceisdeterminedbytheamountof injectionfromthesource(drain),andthediffusionofelectronsfromthechannel.To developafirst-ordermodelfortheresistorwecanapproximatethiscarrier concentrationintheextensionswithanaveragecarrierconcentration,neS/D,inthe

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66 linearregionofoperation.Thentheresistanceoftheextension,ReS/D,assuming drift-dominated conduction, is,(3.33) where m isthecarriermobilityintheextension.Theaveragecarrierconcentration, neS/D,isdeterminedbythecarrierconcentrationonbothsidesoftheG-S/Dunderlap, i.e.,nbandns(Figure3.6).Thecomplexityin(3.33)comesfromns,whichisa functionoftheeffectivegatebias,whichinturndependsontheresultantReS/Dthat reducesthegatebias,VGSbyVeS/D=IDReS/D.Hence,incorporationofReS/Dby (3.33)willrequireintroducinganiterativesolutionschemeforID(VGSeff=VGSVeS,VDSeff=VDS-2VeD),wheretheinitialsolutionofIDhastobeobtainedwith ReS/D=0,whichwillalsogivetheinitialvalueofns,andhenceReS/D.Thenthe updatedReS/DhastobeusedtogetID;theloophastocontinueuntilaconvergence criterionismet.Thustheincorporationofthelinearresistancewillincrease simulation time significantly. InadditiontothedependenceonVGS,ReS/Dalsodependsonthedrainbias VDS.WiththeincreaseofVDS,IDincreases,whichinturnincreasesVeS/D,thusthe electricfieldintheunderlapincreases.Asthecarrierconcentrationintheextension neS/D
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67 phenomenonisfurtherillustratedinFigure3.13(a)whereMEDICI-predictedSI-v(y) ofaFinFETwithlong,27nmofunderlaponeachsideofthegate(thedevicestudied inFigure2.3),isshownforincreasingVDS.AthighVDS,bothveSandveDare saturatedandarehigherthanvs.AsveS/D vsat, m 0in(3.33),andthusReS/Dsaturates to a value higher than that in the linear region. WithveS/D=vsat,(3.33)isnotapplicableforsaturatedReS/D.Rather, usingaquasi-2Danalysis,likethatdoneforaccountingthechannel-length modulation in bulk-Si [Man77], we find the expression for the saturated ReS/D as .(3.34) Usingthedimensionparameters(tSi=32nm,LeS/D= DL /2=9nm)oftheFinFETin Figure2.4,andassumingvsat=5x106cm/s,thevoltagedropacrosstheS/Dunderlap is0.28V,withID=1x10-4A.FromthecalibrationresultsinFigure2.4,RS=425 W m m,assuming150 W m mofitisduetothecontacts/sheetresistance,ReS/D~(425150)or275 W m m,or3K W, whichgivesavoltagedropacrossLeS,VeS=IDReS~ 0.3V, close to the value that is implied by (3.34). AcompletemodelingofReS/D(VGS,VDS)includessmoothingofthelinear resistancedefinedby(3.33)tothesaturationresistancedefinedby(3.34),andthen includingthemodelinaniterativeschemetosolveforID(RS/D),andRS/D(ID).For pragmaticFinFETs,however,LeS/LeDshouldbeshort,~4nm,asdiscussedin Chapter2,andasdemonstratedin[Tri05a].ForsuchFinFETs,thevelocitydoesnot saturateintheextensionsasillustratedinFigure3.13(b).InthefigureMEDICI-R eS /D L 2 eS /D 2 e Si Wt Si v sat ----------------------------------=

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68 Figure 3.13MEDICI-predictedelectronvelocityalongthechannelofaFinFETwith (a)longextensionlength,LeS/D=27nm,andtSi=17nm,likethatinFigure 2.4,and(b)LeS/D=4.5nm,tSi=14nm,liketheoptimumFinFET[Tri05a] discussedinChapter5.(In(b)the reductioninvelocityinthechannel nearthedrain-endwithincreasingVDScouldbeduetothespurious solution of MEDICI energy-balance model.) 0.060.070.080.090.100.110.120.130.140.150.16y ( m m) 0.0 0.5 1.0 1.5Electron Velocity (107 cm/s) 1.2V VDS=0.4V LeSLeDLg SDVGS=1.2V 0.0220.0300.0380.0460.054 0.0 0.4 0.8 1.2 1.6 2.0 0.4V LeS LgLeD SDVGS=1.2V 0.6V 0.8V 1.0V 1.2V VDS Electron Velocity (107 cm/s)y ( m m)(a) (b)

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69 predictedSI-v(y)ofFinFETwithLeS/D=4.5nmisshownfordifferentdrainbiases. Astheunderlaplengthisnotmuchlongerthan lD(ns),thegatebiascaneffectively controlthecarriersintheextensions.Consequently,athighVGS,whennsandIDincrease,neS/Dincreasesaswell,andcansupporttheincreasedID.Also,shorter underlaplengthreducesVeS/D,hencetheelectricfieldisalsolowintheextension. ThusveS/D(andhenceneS/D)doesnotsaturateathighVDS;insteadthecarriersinthe channelnearthedrainexperiencevelocitysaturation,likethatinthetypical MOSFETs.ThereforeforpragmaticFinFETs,accountingforthesaturationof underlap resistance is not needed. Thetotalparasiticresistance(RS/D)inFinFETisthesumofthe contributionofthecontactresistance(Rco),sheetresistance(Rsh),andspreading resistance(Rsp)[Tau98],andanadditionalcomponentReS/Dwhenunderlapis present, i.e., .(3.35) Whileinthebulk-SiMOSFET,Rspis~20-30%ofRS/D,intheFinFETduetobulk inversion[Kim06],RspissmallcomparedtoRcoorRsh(asevidentfromMEDICI simulations).Forshorterunderlaplength,ReS/Dwillbelowaswell.Dependenceof ReS/DonLeS/DisillustratedinFigure3.14,whereextractedlinearresistancefrom MEDICI-predictedlinearID-VG,isplottedforvaryingLeS.Theextractionisdone followingthechannelresistancemethoddescribedin[Tau98].Asexpectedfrom (3.33),theresistanceincreasessharplywiththeincreaseofLeS.Alsonotethe increaseofReS/Dforthethinnerfin.WearguedthatforpragmaticFinFETLeS/D~ RS /DRcoRshRspReS /D+++ =

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70 Figure 3.14Extractedlinearresistanceofan18nm-FinFETwithvaryingunderlap lengths,fortwodifferentnthicknesses.Theresistancesareextracted fromMEDICI-predictedlinearID-VG.Alsoshowninthegureisthe ITRS targeted RS/D for an 18nm-MOSFET [ITR05]. 024681012 LeS (nm) 0 50 100 150 200 250 300ReS ( W-m m) tSi=8nm VDS = 50mV, VGS-Vt = 0.85V14nm ITRS RS/D

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71 4nm,andforsuchcasesReS/Disnotthathigh,andthetotalRS/Dwillbedominated byRcoandRsh.HencebiasdependenceofReS/Dexpectedfrom(3.33),willnotbe reflectedinRS/D.Thatis,forshorterLeS/LeDneithertheVGSnortheVDSdependencehasasignificanteffectonthetotalresistance,andthus,allowsusto avoidincorporatingtheiterativeReS/Dmodeldescribedby(3.33)and(3.34).In UFDGthus,thebias-independentmodelparameter RS / RD isretainedtomodelthe resistive-effectsofLeS/D.ThiswillmakeUFDGpredictionsoptimisticforFinFETs withlongerunderlaps,butforpragmatic,shorterLeS/D-FinFETs,modelpredictions will remain acceptable. Thevalidityofretainingthebias-independent RS / RD toaccountforthe parasiticresistance,aswellasthatof(3.32)toaccountforSI-Leff,forshorter underlaplengthisillustratedinFigure3.15.With RS = RD =60 W-m m,andbiasdependentLeffcapturedby LES = LED =3.2nm,UFDGpredictionsarewellin agreementwiththatofMEDICIforan18nm-SDGFinFETwith4nmofunderlapson eachsideofthegate.Excellentmatchinboththeweakandstronginversion exemplifiesUFDGsapplicabilityforperformanceprojectionofpragmatic nanoscale-UTB FinFETs. 3.5 Design Implications WiththeincorporationofeffectsofunderlapsinUFDG,wenowcan extendthedesignstudydoneinChapter2.InChapter2,wefocusedontheeffects ofunderlapsondeviceperformance,herewelookintotheireffectsonspeedperformanceofCMOS-FinFETsusinga9-stageFinFETring-oscillator.TheFinFET structureconsideredislikethatshowninFigure2.8,exceptforthefinthickness.We

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72 Figure 3.15ComparisonofMEDICI-andUFDG-predictedI-Vcharacteristicsofa mid-gapgate18nm-SDGFinFETwithunderlaps;tSi=8nm,tox=1nm.In boththesimulators,carrier-temperature-dependenttransportmodelsand QM models are turned off. 0.00.10.20.30.40.50.60.70.80.91.0VGS (V) 10-1110-1010-910-810-710-610-510-410-310-2ID (A/ m m) MEDICI LeS = LeD = 4nm UFDG LES = LED = 3.2nm VDS=1.0V 50mV RS = RD = 60 W-m m SCEB = 0

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73 useapragmatic,thicker(14nm)film[Tri05a].Also,LeS/Diskeptrelativelyshort,08nm,asUFDGpredictionsaremorereliableforshorterunderlaplengths,andwe alreadyconcludedthatlongerunderlaplengthsarenotusefulduetohigh,biasdependent RS/D. Figure3.16showsUFDG-predictedvariationofROdelaywithunderlap lengths.TheFinFEThasLg=18nm,tSi=14nm,andamid-gapgate.Inthe simulation,ReS/DistakenfromFigure3.14,and100 W-m misassumedduetocontact andsheetresistance.Aswedonotconsiderthebias-dependenceofReS/D,thedelay predictedforthelongerunderlaplengths,likeforLeS/D=8nmisoptimistic,butwill notaffectourconclusionhere.Valuesoftheinnerfringingparameter FIF shownin the figure are taken from [Kim06]. Theeffectofunderlaplengthsontdistwo-fold.WithincreasingLeS/D, IONdecreases(Figure2.10)duetohighRS/D,aswellasincreasedVt,whichtendsto increasethedelaytime.Onthehand,increasingLeS/Ddecreasesthefringing capacitances[Kim06],andthustendstodecreasetd.Theformerdominatesforlonger LeS/D,andthusweseetdshowingapositiveslopeforLeS/D>6nminFigure3.16 (theincreaseintdisnotthatpronouncedinthefigureduetoassumedconstant,low ReS/D).ThereductionoffringingcapacitancesdominatesforshorterLeS/D,andgives anoptimumrangeforLeS/D,4-5nm.InChapter2,wereachedasimilarconclusion consideringthedevice-levelperformances.Thusapragmatic,andoptimumITRS 45nm node FinFET with Lg = 18nm, should have 4 to 5nm of G-S/D underlap. InChapter2,wealsofoundthat,ifasymmetricLeSandLeDarefeasible, itisadvantageoustohaveLeS
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74 Figure 3.16UFDG-predictedvariationofring-oscillatordelay(td)withunderlap lengths(LeS/D).InsetshowskeyUFDGmodelparametersusedfor differentLeS/D.100 W-m mof RS / RD isassumedtobeduetothecontact andsheetresistance,andthecontributionofReS/D(LeS/D)isobtainedfrom Figure3.14.Valuesoftheinnerfringingparameter, FIF isdueto[Kim06]. Thedevicesareundoped{110}-FinFETwithLg=18nm,tSi=14nm,tox= 1nm,and FM=4.6eV;VDD=1V.QMandballistic-limitmodelinUFDG is turned on. 0.02.04.06.08.0LeS/D (nm) 2.2 2.3 2.4 2.5 2.6td (ps) LeS/D(nm) RS/D ( W m m) FIF 01001.0 21060.9 41280.7 61540.6 81880.5

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75 reductionofeffectivegatebias.InTable2.1,weshowtheimprovementinROdelay whenLeS
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76 1. At present UFDG does not allow asymmetric FIF ; the above values are hard-wired in the code before each simulation.LeS(nm) LeD(nm) RS ( W-m m) RD ( W-m m) FIFS 1FIFD 1td(ps) 441281280.70.72.30 261061540.90.62.12 081001881.00.51.82 Table 3.1 UFDG-predictedring-oscillatordelayforan18nm-FinFETwithasymmetric underlaps.ValuesofRS/D(LeS/D)and FIFS/D(LeS/D)arefromFigure3.16,also other device parameters are the same as in Figure 3.16.

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77 thebiasdependenceofLeff.Also,themodelingofthesource-channelboundary potential was discussed for both underlap and conventional non-underlap devices. Instronginversion,thenotedunderlapdoesnotaffecttheLeffsignificantly,butintroducesacomponenttotheparasiticresistance.Theresistance duetotheunderlapshowsbiasdependenceaswell;itdecreaseswithgatebiasinthe linearregion,butsaturatesinthesaturationregion.However,forpragmaticFinFETs havingshorterunderlaplengths,thebias-dependenceofparasiticresistanceis negligibleanddoesnotwarrantachangeinthepresentUFDGformalismthat accountsfortheparasiticresistancewithbias-independentmodelparameters.Hence, eventhoughmodelingofthebiasdependenceoftheunderlapresistancewas discussed,theywerenotincorporatedinUFDG.However,properaccountingofthe biasdependenceofLeffwasincorporatedbyreplacingtheoverlapparameter DL withparameters LES and LED thataccountfortheeffectiveunderlaplengths,and modulateLeffappropriately.ModelupgradeswereverifiedbycomparingUFDG predictionswiththoseofMEDICIs.Forbothweakandstronginversion,upgraded UFDGpredictionswerefoundtobeinexcellentagreementwithMEDICIfor pragmaticUTBFinFETs.Theproperaccountingfortheeffectsofunderlapsthus enhancedthereliabilityofUFDGperformance-projectioncapabilityforpragmatic FinFET circuits. TheupgradedmodelwasthenusedtoextendthedesignstudyofChapter 2byperformingcircuit-levelsimulation.Studyofthespeed-performanceofFinFETCMOSrevealedthattheoptimumunderlaplengthforapragmatic,45nmITRSnode

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78 FinFETis4-5nm.Also,UFDG-predictedROsimulationshowedthatspeed enhancement as high as 20% can be achieved if asymmetric underlaps are used.

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79 CHAPTER 4 CARRIER TRANSPORT IN NANOSCALE FINFETS 4.1 Introduction InChapter2,inthepreliminarycalibrationofUFDGtocontemporary FinFETs,wemainlyfocusedontheelectrostaticsofUTBFinFETs.Wefoundthat duetotheundopedUTB,theextensionsarenotdopeddirectly,whichinturnresults inG-S/Dunderlaps,resultinginbias-dependentLeff.Amoredirecteffectofleaving thebodyundopedisthatitreducesthetransverseelectricfield,whichpromises higherchannelmobility.Inthischapter,withtheupgradesdoneinChapter3(i.e., accountingfortheeffectsofgate-source/drainunderlap),andtherecently incorporatedQM-basedmobilitymodel[Tri05a],wepresentfurthercalibrationof UFDGtoFinFETs,andinsightstherebyderived,especiallyregardingthecarrier mobilityandtransportpropertiesinthechannel.Bothelectronmobilityandhole mobilityinn-andp-channelFinFETsarestudied.Thetransportparametersobtained fromthecalibrationsarethenusedtoprojectchannelcurrentsofsub-20nmFinFETs, by using UFDG simulations, which involve both dissipative and ballistic transport. Withhigh-mobility/ballistic-limitedtransport,theFinFETchannel resistanceisexpectedtobelow,whichindicatesthattheFinFETwillbemore vulnerabletoparasiticresistance.Effectsoftheparasiticresistanceondrivecurrent andring-oscillatordelayarethusdiscussedbycomparingahypotheticalbulk-Si device with an SDG FinFET.

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80 4.2 Carrier Mobility in the Channel 4.2.1 Electron Mobility in nFinFET ForournFinFETcalibrationworkdescribedhere,wechoseroomtemperatureID-VGScharacteristicsofa370nm-gate-lengthFinFETwithn+-poly gatefabricatedatAMDwith{110}surface[Yu02].CalibrationofUFDGtothe subthresholdcharacteristics,likesubthresholdswingandDIBL,allowsusto uniquelyobtaintwoofthethreedimension-relatedparameters,effectivechannel lengthLeff(definedbymodelparameter L LES and LED ,or DL ),finthicknesstSi(definedbymodelparameter TSI )andoxidethicknesstox(definedbymodel parameter TOXF / TOXB ).Henceifthethirdparameterisknownthroughsomeother methode.g.,oxidethicknessfromtheC-Vcharacteristics,orfinthicknessfromTEM pictures,etc.,avalidcalibrationcanbedone.However,forthelong-channeldevice here,withapparentlynoshort-channeleffects(SCEs),itisnotpossibletogetunique valuesfortheseparametersfromUFDGcalibration.Wemainlythusrelyonthe manufacturer-suppliedinformationforthevaluesofthedevicedimensions.Thegate oxidethicknessusedis17,knownfromtheprocessinformation[Yu02]andalso verifiedwithreasonableaccuracyfromcalibrationofshorter-channeldevices,as wellasC-Vcharacteristicsforthesametechnology[Yu02].Thephysicalgatelength is370nm,andwithextensionsnotdopeddirectly,thereisnosource/gateordrain/ gateoverlapandhence DL issettozero.Underlaplength, LES / LED ,isassumedto bezeroalso;howeverasdiscussedinChapter2,inthisdevicetheyareactuallynonzeroandmaybe~3%ofthegatelengthbuttheireffectisnegligibleinweak inversion.Forthesamereason,tSiisassumedtobe26nm,thoughTEMpicturesof the fabricated device suggest it can vary from 17 nm to 26 nm.

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81 4.2.1.1 Calibration Results Theweak-inversioncalibrationresults,withthemodelparameterslisted inTable4.1,areshownin Figure4.1, whereUFDGpredictionsareingoodagreement withdataexceptforgatebias,VGS<-0.2V.Inthatregion,thedraincurrent,IDat highdrainbiasincreasesduetogate-to-draintunnelingleakage.Throughoutthis worktheUFDGgateleakagemodelwillbeturnedoffbuttheQMmodelwillremain turned on. Themobility,onwhichthesubthresholdcurrentislinearlydependent, usedinthecalibrationisextractedfromthelinear-region,strong-inversion characteristicsdescribedlater.Thegateworkfunction( WKFG / WKBG )obtained fromthecalibrationis4.073,whichindicatesapolydopingof4.5x1019cm-3(using Fermi-Diracstatistics)inthegate.Thehighpoly-dopingconcentrationisconsistent withthedegradationofcapacitancesobservedintheC-Vcharacteristicsin[Yu02], wherethedegradationofgatecapacitanceisobservedonlyatveryhighgatebias, VGS > 1.2 V. Oncethedimensionalparametersareknownthroughweak-inversion calibration,thenextstepistoextracttransportparametersfromstrong-inversion calibration.AswehavefoundinChapter2, UO and THETA canbeobtained uniquelyfromcalibrationofgm/ID 2-VGS,whichisindependentofRS/D[Ghi88].In Figure4.2,weshowedthecalibrationresultofUFDGtogm/ID 2characteristicsofthe AMD370nmFinFET.With UO =565cm2/V.sand THETA =0.2,theUFDG predictionisinexcellentagreementwithdatathroughoutthestrong-inversion region, which spans from VGS (Ninv) = 0.3V (5x1012cm-2) to 1.2V (2.1x1013cm-2).

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82 Model ParameterDescriptionValue L Physical Gate Length370 nm LES Source-gate underlap length0 nm LED Drain-gate underlap length0 nm DL Source/drain-gate Overlap length0 nm TSI Film Thickness26 nm TOXF Front gate oxide thickness1.7 nm TOXB Back gate oxide thickness1.7 nm WKFG Front gate work function4.073 eV WKBG Back gate work function4.073 eV UO Low-eld mobility565 cm2/V.s THETA Mobility tuning parameter0.2 RS Parasitic source resistance390 W m m RD Parasitic drain resistance390 W m m W Width50 nm Table 4.1 Key UFDG model parameters extracted from the calibration to 370 nm AMD nFinFET.

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83 -0.3-0.2-0.10.00.10.20.3VGS (V) 10-1010-910-810-710-610-5ID (A) VD= 0.1V, measured data VD = 1.2V, measured data UFDG Figure 4.1CalibrationofUFDGtoweak-inversioncharacteristics,ID-VGSofa370 nm gate length FinFET. Model parameters are listed in Table 4.1

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84 0.30.40.50.60.70.80.91.0 1.1 1.2VGS (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0gm/ID 2(106 /V-A) Measured Data UFDG VDS = 0.1V Figure 4.2CalibrationofUFDGtomeasuredgm/ID 2vs.VGSatlowdrainbias.The range of VGS shown is all strong-inversion, as Vt@ -0.1V.m0 = 565cm2/V-s q = 0.20

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85 Withthetransportparametersobtainedfromgm/Id 2calibration,theIDVGScalibrationisnowstraightforwardneedingonly RS / RD tobetuned.InFigure 4.3(a),thelinearregionID-VGScalibrationresultisshown.Anexcellentmatchwith dataisobtainedwithaconstant RS = RD =390 W-m m.Comparedtotheextension resistanceintheshorter-channeldevices,the RS / RD heredoesnotshowthe expectedbiasdependenceduetocarriermodulationintheunderlapsbygatebias [Fos03c].Thereasonis,inthislonger-channeldevicethechannelresistanceismuch higherandanyvariation,unlesssevere,in RS / RD isnotreflectedinRONin(2.2). Thevoltagedropdueto RS atVGS=1.2VwithVDS=0.1Vis0.029V,which justifiesourassumptionusedin(2.2)forgm/ID 2calibrationthat(VGS-IDRS / W ) @ VGS. InFigure4.3(b)weshowthecalibrationresultsathighdrainbias.The conspicuousmismatchisduetothefactthatUFDGdoesnotconsiderthevariation oftransversefield(Ex(y))alongthechannelanditseffectonthemobility.However, comparedtothematchobtainedfora10 m mpFinFET(shownlater,Figure4.8), UFDGpredictionsareheremuchbetter,andgetbetterwithincreasingVGS.Bothof theseobservationsjustifyourreasoningthatthemismatchisduetonotaccounting forEx(y)degradationalongthechannel,whichceaseswithdecreasingLgand increasing VGS. Beforedrawinginferencefromthevaluesoftheparameters,like UO and THETA ontheFinFETtechnology,wewilllookintotheuncertaintiesthatmay resultininaccuraciesinthegm/ID 2calibration.Thefirst,istheuncertaintyinthefilm thickness.Asmentionedintheweakinversioncalibration,fordeviceswithnoSCEs

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86 Figure 4.3UFDG-predictedstrong-inversionID-VGScharacteristicsofAMD370nm FinFET:in(a)linearregion,(b)saturationregion.UFDGmodel parameters are listed in Table 4.1 0.000 0.005 0.010ID (mA) VD=0.1V, measured data UFDG -0.3-0.10.10.30.50.70.91.1VGS (V) 10-710-610-510-410-310-2ID (mA) -0.3-0.10.10.30.50.70.91.1 10-1010-910-810-710-610-510-4 0.00 0.01 0.02 0.03 0.04 ID (A)VGS (V)(a) (b) VD=1.2V, measured data UFDG ID (mA)

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87 itisdifficulttoaccuratelyfindoutwhatistheactualthicknessofthefin,andthere isapossibilityoftSivaryingfrom17nm-26nm[Yu02].TheeffectoftSicomesin toplayindeterminingthethresholdvoltagethataffectsgm/ID 2,whichisnegligible forthislong-channeldeviceforthenotedrangeoffinthickness,andtheother possiblevariationmaycomefromthedependenceof meffontSiin(2.2),throughthe dependenceofphonon-limitedscatteringontSi,butforthenotedrangeoftSi, phonon-limitedmobilitydoesnotvarymuchwithtSi,especiallyforhighNinv[Tri05b].So,wecanassumethatuncertaintyintSidoesnotaffectthecalibration results here. Theseconduncertaintyisintheeffectsofpolysilicondoping.Poly depletioncanreducetheeffectivegatebias,andinturntheinversion-chargedensity. Ifthereisaseverepoly-depletioneffect,theinversionchargepredictedbynottaking careofitwillbeanoverestimate,whichwillgivelowereffectivemobility(to maintainthesameamountofdraincurrent).Thatis,ifthereissomepoly-depletion effect,theUFDGpredictionforeffectivemobilitywillbelowerthantheactual mobilityvaluesinthedevice.Asthemobilityvaluewegetfromthis{110}-FinFET ishigherthanthatisexpectedtheoretically(discussedlater),wedonotexpecta significanteffectofpolydepletiononourcalibrationresultsasthatwouldmeanthe mobilityvaluesareunrealisticallyhigh.Toconfirmthisinference,weuseMEDICI tochecktheeffectsofpolysilicondepletionongm/ID 2characteristicsforsimilar device,andtheresultsareshownin Figure4.4.The simulationclearlyshowsthatfor polysilicondopingof5x1019cm-3(whichisapproximatelythepoly-dopingobtained

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88 VGS (V)gm/ID 2 ( m m/VA) Npoly (1x1019, 5x1019, 1x1020) 0.30.40.50.60.70.80.91.01.1 0.0 10000.0 20000.0 30000.0 40000.0 50000.0 60000.0 70000.0 80000.0 90000.0 100000.0 1.2 Figure 4.4MEDICI-predictedvariationofgm/ID 2withpolysilicondoping.Energy balanceandthequantum-mechanicalmodelwereturnedoff.Thedevice dimensions are dened by the parameters in Table 4.1.VDS = 0.1V

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89 fromtheweak-inversioncalibration),polydepletionhasnosignificanteffectongm/ ID 2, especially at high gate bias. 4.2.1.2 Inference on the Electron Mobility Thelow-fieldmobilitym0obtainedfromthecalibrationinFigure4.2is low(comparedtothatofthebulkCMOS)forthisnFinFET,thatisthemobilityin weakinversionislower,whichisbeneficial,asitwillreducetheoff-statecurrent. Toidentifythemechanismthatrendersm0low,webrieflydescribethemobility modelinUFDG.Detaileddescription(withverification)ofthemobilitymodelis published in [Tri04]. ThemobilitymodelinUFDGconsistsofaphysicalmodelofdominant scatteringmechanismsthatareaddedusingMatthiessensruletogivetheeffective mobility ( meff), which is given as, ,(4.1) where, ,(4.2) and mph, msr, mco, mothers, mph(bulk)arethephonon-limitedmobility,surfaceroughness-limitedmobility,Coulomb-scattering(CS)-limitedmobility,mobility duetootherscatteringmechanisms(forexample,remoteCoulombscattering (RCS)),andphonon-limited-mobilityintheundopedbulkSi,respectively.The m eff m 0 1 m 0 m phbulk () -------------------------m phbulk () m ph --------------------------1 q m 0 m sr -------++ ------------------------------------------------------------------------------------------------= m01 m co --------1 m others ------------------1 m phbulk () -------------------------++ 1 =

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90 modelparameters, UO and THETA mentionedearlier,correspondtom0and q in (4.1)and(4.2).TheCoulomb-limitedmobility, mcoin(4.2)canbeduetothecarrier interaction with interface charge or with ionized impurities in the channel. Forultra-thinbody(UTB),undopedFinFETs(noimpurityatom),the dominantmobilitycomponentsare mphand msr,andtheyaremodeledphysicallyin UFDG.Therest, mcoand mothers,areincludedinthetunablemodelparameter UO Thethirdtermin(4.2), mph(bulk)isaddedtohaveafiniteupperlimitfor UO .IfCS orotherscatteringmechanismsarenegligible,m0shouldbethebulkphonon mobility,whichis1350cm2/V.sforelectron.However,fromourcalibrationresults here,m0=565cm2/V.s.Suchlowvalueindicatespresenceofotherscattering mechanisminadditiontothesurfaceroughnessandphononscattering,andtheusual suspectforpolygateisRCS.However,forthe17oxideandtheNinvrangein Figure4.2,RCSisnegligible[Ess03].CSduetointerfacestatesshouldnotbe importantasthereisnoevidenceofsignificantinterfacestatesintheID-VGScharacteristics.ButCSduetodonoratomsinthechannelresultingfromthetailof the source/drain doping profile NSD(y) might be non negligible. TheprocesstechnologytofabricatethisFinFETuseslow-temperature annealingofimplantedsource/draindopantstogetthemintothesource/drain extensions.Theprocessisnotwellunderstood(andhencenotwellcontrolled)in ultra-thinbody,andthetailofthesource/draindopingprofilecanextendinsidethe channel.So,eventhoughthechannelisundoped,itmightcontaindonordopants(for n-channel).Fromourcalibrationofshorter-channeldevices(describedinChapter2) ofthesametechnology,weknowthattheseFinFETshave~15nmofunderlap(out

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91 ofanextensionlengthof80nm)onbothsidesofthegate.Thelengthoftheunderlap isestimatedbymodelingtheeffectivechannellength(Leff),whichisdefinedasthe lengthoverwhichthegatecontrolsthemodulationofelectrons,andtypically,gate controlceasesoncethesource/draindopingconcentration,NSD,reaches ~5x1018cm-3.Forthelonger-channeldevice,thecalibrationresultsforLeffisnotunique,so underlaplengthscannotbeobtainedconclusively.However,asboththeshortchanneldeviceandthelonger-channelonearefabricatedusingthesametechnology, andtheextensionlengthisthesameforboththecases,wecanassumethelongerchannelonealsohas~15nmofunderlap.Thatis,here,inthisFinFET,NSD(y)can dropto~5x1018cm-3,15nmbeforethegateedge,anddecreasegraduallytowards thechannel,dependingonthestraggle.Forstragglenotsharpenough,thetailinthe extensioncanleadtodonordopingconcentrationnearthesource/drainendofthe channel as high as 1018 cm-3. Ifweassumescatteringduetoothermechanismsarenotpresent,thenthe lowm0canonlybeexplainedbythepresenceofimpurityscatteringduetothe presenceofthenoteddonorsinthechannel.Mobilityduetoimpurityscatteringby an impurity concentration N can be described as [Lun00], (4.3) where, mmin, mmax,Nref,and a areparametersthatcanbeobtainedbyfittinglow-field electronmobilitydata.From(4.1)andignoring mothers, mco=972form0=565, plugginginthisvaluein(4.3)andusingthevaluesofthefittingparametersgivenin m co m min m max m min 1 N N ref -----------a + --------------------------------+ =

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92 [Lun00]forelectroninSi,wefindtherequiredimpurityconcentrationtogivem0= 565ismerely5.27x1016cm-3.Duetotheundopedbodyandpolysilicongate,the VtoftheFinFETislow(~-0.15V),andtheinversioncarrierdensityNinvisquite highevenforlowgatebiases.ForVGS=0.3VinFigure4.2,Ninv~5x1012cm-2. Ifthedonorconcentrationinthechannelwereuniformandequalto5x1016cm-3, suchahighNinvwouldeffectivelyscreenthedonors.However,aspointedout earlier,duetoGaussianprofile,NSDnearthesource/drainendofthechannelcould behighenoughtoreducethecarriermobilityathighNinv.Withthegatebias increasing,theincreasedinversioncarrierdensityultimatelyscreenstheimpurity atoms, and mco increases and its contribution becomes negligible in (4.2). As UO isabias-independentmodelparameter,itdoesnotreflectthe screeningeffectontheionizedatoms,andmodelparameter THETA hastobe adjustedtocompensateforthelowm0instronginversion(refertothelasttermofthe denominatorinrighthandsideof(4.1)).Note,that THETA isintendedtobeusedin UFDGtoadjust msrandhighvalueof THETA reflectsseverityofsurfaceroughness scattering.Typicalvaluefor THETA isfoundtobe0.83(alongwith UO =1100) fromUFDGcalibrationto{100}-DGMOSFETdataaswellastoMonteCarlo simulationofthesame[Tri04],butinourcalibrationresulthere,itisfoundtobe0.2, whichispartiallyduetotheoverestimatingoftheeffectsofimpurityscatteringin stronginversionbyusingbiasindependent UO toreflectthebias-dependent mco.For example,inourcase,ifm0were1100atVGS=1.2V, THETA wouldbe0.35. However,thisisstilllowerthanthevalueof THETA calibratedfrom{100}DG MOSFETstructuresin[Tri04],andsuggeststhatthesurface-roughnessscatteringis

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93 lessseverein{110}FinFET.Thisisincontradictiontotheeffectsseeninbulk-Si MOSFET,where{110}-Siexhibitsseveresurfaceroughnessscatteringcomparedto {100}-Si [Tak94b]. Toexplainthedecreaseofsurfaceroughnesslimitedscatteringin{110}Siwewillgothroughthepossiblereasons,startingwiththepossibilityofeffectsof redistributionofcarriersin{110}-comparedto{100}-Si.Duetosubband modulation,chargecentroidmovesawayfromthesurfacein{110}-Sicomparedto thatin{100}-Si.Figure4.5showsSCHRED[Vas00]predictedaverageelectron distribution,| Y|avg 2inthechannelforboththesurfaceorientationsfortheFinFET definedbytheparametersinTable4.1.Theaveragedistributionisfoundby averagingtheprobabilitydistributionfunction| Y |2ofallthesubbands(bothin unprimed and primed valley) as, (4.4) whereNijistheinversiondensityofi-thvalley,j-thsubband.Onlyfirsttwosubbands areconsideredfromeachvalley.Comparedto{100}-Si,| Y|avg 2with{110}-Sishows thepeakofthedistributiontobefurtherawayfromthesurfaceduetolowereffective massofthe4-fold(unprimed)valleyin{110},suggestingSRscatteringmightbeless in{110}-Si.However,theincreasedDOSmassoftheunprimedvalley,whichhas higherpopulation,increasesthescatteringrate(throughFermiGoldenrule, scatteringratevarieswithDOS).Hence,thetwofacts,i.e.,(i)lowerconfinement Yavg 2Yij 2Nij ijNij ij------------------------=

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94 Figure 4.5SCHRED-predictedaveragedistributionofcarriersalongthenthickness nearfrontsurfaceinSDGnFinFETswith{100}and{110}surfacesat VGS = 1.2 V; tSi = 26nm, FM = 4.073eV. 0.05.010.0Along x (nm) 0.0 0.2 0.5 0.8 1.0Normalized | Y |avg 2 {100} {110}tSi/2

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95 massintheunprimedvalleyin{110}movescarriersfurtherawayfromthesurface comparedtothatin{100},(ii)higherDOSmassin{110}-Siincreasesthescattering ratecomparedto{100}-Si,haveoppositeeffectsonthemobility.InbulkSi,{110} electronmobilityislowerthanthatin{100}[Tak94b],indicatingthedominanceof thelatterphenomena.ForFinFETwithtSi~5nm,theformerportendspronounced volumeinversionin{110}FinFETresultingmuchhigher msrcomparedtothatof {100}[Tsu05].Forourcase,tSiisratherthick,~26nm,thusQMeffectsarenotthat pronouncedtobeginwith,andasshowninFigure4.5,themovementofcarriersaway fromsurfaceareminimalforboththesurfaces.Hence,thedecreaseinSRscattering hasprobablyduetothechangeofsurfacepropertiesthemselvesratherthandueto the change of carrier distribution. Comparedtothe{100}-FinFETs[Ess01],thetestFinFETs(boththenandp-channel)herehavesomeaddedprocesssteps,i.e.,usessacrificialoxides techniquetogrowgateoxide,andusesSiONasgatedielectricinsteadofSiO2.Both oftheseprocesschangeshelpinreducingthesurfaceroughness.Experimental observationofoxide/Sisurfaceroughnessthroughx-rayreflectometryshowsSiON/ SisurfaceissmoothercomparedtoSiO2/Sisurface[Gre94],andisfoundtoincrease msrinbulk-SiwithSIONaswell[Tak98].Wetherebyconcludethattheincreased msrobservedforboththeelectron(Figure4.6)andthehole(Figure4.9)inthecalibration resultsof{110}-Siisduetolowsurfaceroughnessscatteringstemmingfromthe addedprocessstepsthatresultedinsmoothersurfacesinthetestdevices.Infact, suchconclusioncanbedrawnfromFigure4.2directly,wheregoodmatchisobtained forallbiasrangefor q =0.2.Ifthelowvalue q wereduetosomebias-dependent

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96 effects(likethecarrierredistributionmentionedabove,neglectofSR-inducedintervalleyscatteringandignoringscatteringofcarriersinhighersubbandsintheUFDG msrmodel,etc.),wemighthaveneededtovary q withVGS,asdonefortheRS/Din Figure2.4(b).Thebias-independenteffectsin msr,tofirstorder,comesfromtheSi/ SiO2properties,andhenceconstant,low q (comparedtothe{100}-Sidevices) obtainedfromthecalibratingindicatessmoothersurfacesinthetest{110}-FinFETs. InFigure4.6UFDGpredicted mn(eff)with m0and q obtainedfrom calibration,alongwith mn(eff)ofothercontemporaryMOSstructureisshown.Forthe sameinversionchargetheeffectivemobilityofFinFETisalmost2xhigherthanthat ofthebulkSi-MOSFET[Tak94]forNinv=7x1012cm-2andwillbemuchhigher(~ 4x)atNinvatonstate,whichis~1x1013cm-2.Comparedto{100}FinFETmobility data,{110}-FinFETmobilityis25%lowerforNinv=1.9x1013cm-2.Alsoplotted inFigure4.6,isUFDGpredictedmobilityfor{110}SDGFinFETusing m0=1100 and q =0.83.Thesevaluesof m0and q areobtained[Tri05b]bymatchingarrayof {100}SDGMOSFETdata[Ess01]andfoundtobetypicalofundoped{100}DG MOSFET.Comparisonof{100}-Sidataandpredicted{110}-Simobility(open symbolinthefigure)showsthatchangingthesurfaceorientationto{100}might resultin40%reductionofmobility(atNinv=1.9x1013cm-2)duehigherconductivity massin{110}-Si,howeverthe{110}FinFEThereshowsthatthereductionisonly 25%,anencouragingimprovementduetohigher msr,discussedearlier.Forthesame reasondegradationofmobilityislessseverein{110}FinFETthanthatof{100} FinFETathighNinv.FordecreasingNinv,thedegradationof{110}FinFETmobility becomessevereduetolow m0,i.e.,donorimpurityscattering.Fromourcalibration

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97 mn(eff) (cm2/V.s)Ninv (1013cm-2){110}-DG FinFET (tSi = 26nm) {110}-DG MOSFET (tSi = 21nm) Bulk-Si MOSFET (NA = 4x1018cm-3) {100}-DG MOSFET (tSi = 21nm) VGS = 0.3V VGS = 1.2V 0.51.01.52.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 450.0 Figure 4.6CalibratedUFDG-predictedvariationofeffectiveelectronmobilitywith inversion-carrierdensity(withrangeofgatevoltageindicated)inthe{110}DGFinFET,comparedwithmeasuredmobilities(points)in{100}-planar contemporarybulk-silicon[Tak94]andDG[Ess01]nMOSFETs.Also plottedistheUFDG-predicted{110}-DGnMOSFETmobility(lightcurve) correspondingto m0and q obtained[Tri04]bymatchingmobility measurements of {100}-planar DG MOSFETs.

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98 results,itisthusevidentthatundopednFinFETwith{110}-Sisurfacecanhavequite highmobilityaton-stateconditionmainlyduetoabsenceofacceptordopantsinthe channelandlessseveresurfaceroughnessscatteringandbeneficiallowmobilityin off-stateconditionpossiblyduetopresenceofdonordopants(albeitalowaverage concentration) in the channel. Wenotethatthereductionof mn(eff)inthe{110}DGFinFETrelativeto thatinthe{100}DGMOSFET(0.65xatNinv=1013cm-2)inFigure4.6islessthan thatmeasuredin[Yan03]forbulk-SiMOSFETs(0.33x).ThisDGversusbulk nMOSFETdifference,analogoustothatnotedforpMOSFETsintheprevious section,stemsinpartfromtechnologydifferences,i.e.,thedifferentdielectrics (SiONandSiO2)oftheDGdevicescomparedand,possibly,finroundingwhich yieldsambiguouscrystalorientationofthesidewalls[Lan06].However,theDG versusbulkdifferencescouldalsobeaidedbythedifferentdistributionofcarriers amongtheunprimed(UP)andprimed(P)valleysin{100}-and{110}-Si.InTable 4.2weshowSCHRED-predictedsubbandoccupationfactor,PF(i.e.,Nij/ Nij)for bothbulk-SiandFinFETwith{100}and{110}surfaces.Fromthetable,thechange intheweightedaveragemc( mc)ismoreinbulk-SitheninFinFETwhensurfaceis changedfrom{100}to{110},leadingtomorechangein mn(eff)( mc -1)inbulk-Si thaninFinFET.Also,notethechangeinthedifferencebetweenthefirsttwo subbandsofUPandPvalleysforbulk-SiandFinFET.Forbulk-Si,theirseparation decreasesby55meVfrom{100}to{110},whereasforFinFET,itis38meV,which willincreasetheinter-valleyscatteringin{110}-FinFETmorethanthatin{110}bulk-Si, for changing the surface from {100}.

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99 DeviceSurfacemcOccupation(%) mc= (PFv/mcv)-1D E11_21UPP PFUPPFPBulk-Si {100}0.1900.31571300.21389 {110}0.2830.31581190.28834 DG {100}0.1900.31556440.23060 {110}0.2830.31577230.28922 Table 4.2 SCHRED-predictedsubbandoccupationpropertiesofalowdopedbulk-Si nMOSFETanda26nmthickfinnFinFETatNinv=1013cm-2.UPandPdenotes unprimedandprimedvalleyrespectively, D E11_21istheseparationbetweenthe lowestsubbandsofUPandPvalleys,andmc[Ste72]istheconductivityeffective massinfreeelectronmassunit. mciscalculatedbytakingweightedaverageofthe mcs of all the valleys (v).

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100 4.2.1.3 Inference on the SDE Doping FromthelinearID-VGScalibrationinFigure4.3wehavefoundRS/D= 390 W-m m.Assumingdriftdominatedconductionand150 W-m moftheresistanceare duetocontactandsheetresistance,theaveragedopingdensityin15nmunderlapof the80nmextensionrequiredtogettheaboveresistanceis~2x1018cm-3.Suchlevel ofNSDisconsistentwithourrealizationthatpartoftheextensionisnotdopedwell andalongwiththeinterpretationoftheextractedlow-fieldmobilityvalues,we concludethatthestraggleintheextensionislargethatleavesasignificantNSD(y) tailinthechannel.Forlong-channeldevices,averagedopingdensityinthechannel duetothistailmaynotbelarge(asfoundherefrom(4.3)),butforshort-channel devicestheaveragedonorconcentrationcanbehighenoughtoeliminatethe advantageofundopedbodyasfarasmobilityisconcerned.Assuch,togetthefull advantageofFinFETsperfectchannelinsmallergatelengths,extensiondoping procedureneedscarefulattentionnotonlytoavoidpunch-troughorhighparasitic resistant effects but also to avoid low mobility in the channel. 4.2.2 Hole Mobility in pFinFET Weusenear-midgapmetal-gatep-channelFinFETs,with{110}sidewall surfacesthatwerefabricatedatFreescaleSemiconductor[Mat06]tostudythehole mobilityinFinFET.TheFinFETswereprocessedon100nm-thickSOI,using50nm nitridetopatternthethinSifinswithtSi@ 30nmandaheight(hSi)of @ 100nm.After removalofa10nmsacrificialoxide,a2nm-thick(EOT=tox)contemporarygate oxide(i.e.,nitridedoxide,orSiON)wasthermallygrownonthefins,andthen15nm oftitaniumnitride(TiN)wasdepositedoverthegatedielectricusinganoptimized

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101 PVDprocess.Toimprovetheprocessconformality,amorphousSiwasdeposited overtheTiNgate,yielding,ultimately,apolysilicon/TiNgatestack.Theionimplanted(boron)source/drain(S/D)regionswereactivatedusingthermal annealing,whichalsodopedthe50nmfin-extensionvialateraldiffusion.ThefinUTBwasleftundoped.Theback-endcontact/interconnectprocessingusedcobalt silicide and copper. 4.2.2.1 Calibration Results Measureddevicegatecapacitance-voltagecharacteristics,with correspondingUFDGcalibrationresults,foranLg=10mmpFinFETareshownin Figure4.7(a).Withourfocusonholemobility,wechosethelong-channeldeviceto avoidconfusingeffectsofhighandbias-dependentRS/D,inadditiontoenable reliablecapacitancemeasurements.ThegoodmatchoftheUFDGpredictionswith themeasuredCG-VGScharacteristicsisobtained,withtox=2nm,bytuningthe confinementmass(mx),andthusmD,inthelight/heavy-holesubbands,allofwhich wefoundtobe11%heavierthanthoseatplanar-{100}Sisurfaces.Whilethe increaseofboththeheavy-andthelight-holemassbythesameamountcouldbe fortuitous,thefactthattheyareheavierisconsistentwithMonteCarlosimulation resultsin[Fis03].Commensurately,Ninvvs.VGSispredictedverywellasshownin Figure4.7(b).Then,thelinearregionID-VGScharacteristicsismatched,asshownin Figure4.8,evaluating m0=250cm2/V-sand q =0.10.Notethat q ,whichisfoundto be~1.0forholesinplanar-{100}devices[Tri05b],ismuchsmallerhere.Thegate workfunctioninferredfromthecalibration,whichisconsistentwiththe characteristicsinFigure4.7andFigure4.8,is4.47eV,about130mVsmallerthanthe midgapworkfunction.Theconspicuousmismatchinthehigh-VDScharacteristicsin

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102 Figure 4.7ResultsofcalibratingUFDGtoanLg=10 m mpFinFET:measuredand predicted(a)gatecapacitance-voltageand(b)integratedinversion-carrier density-voltagecharacteristics.ThemeasuredNinv(VGS)in(b)isderived from integration of the measured CG(VGS) in (a). -2.0-1.8-1.6-1.4-1.2-1.0-0.8-0.6-0.4-0.20.0VGS (V) 0.00 0.01 0.02 0.03CG (pF) Measured UFDG (a) (b)VDS = 50mV -2.0-1.8-1.6-1.4-1.2-1.0-0.8-0.6-0.4-0.20.0VGS (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2Ninv (1013cm-2) Measured UFDG VDS = 50mV

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103 -2.0-1.8-1.6-1.4-1.2-1.0-0.8-0.6-0.4-0.2VGS (V) 10-1410-1310-1210-1110-1010-910-810-710-610-5ID (A) VDS = 50mV 1.2V Measured Figure 4.8UFDGcalibrationtotheID-VGScharacteristicsofthe10 m m-pFinFET. Predictedlinearregioncurrent-voltagecharacteristics,alongwiththe results in Figure 4.7, imply the effective hole mobility.UFDG

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104 Figure4.8isduetothefactthatUFDGdoesnotaccountfortheincreasingmobility fromsourcetodrainalongthechannelduetothedecreasing eeff(along-channel peculiarity),whichisalsoevidentinthenFinFETcalibrationinFigure4.3.Itdoes not effect the results of this work. 4.2.2.2 Inference on the Hole Mobility Figure4.9showstheUFDG-predicted(low-VDS) mp(eff)vs.Ninvforthe pFinFET,definedby UO ( m0)and THETA ( q) obtainedfromthecalibration.Also showninthefigureisthedirectlymeasured(viathelinearID(VGS)withNinvinferred fromtheCG(VGS),i.e.,thesplit-CVmethod)holemobilityforthesamedevice,and holemobilityinaplanar-{100}undopedDGpMOSFET(tSi=18nm)basedon measureddatafrom[Ess00].Forcomparisonstoclassicaldevices,weincludeinthe figuremeasuredholemobilitiesinacontemporary-like{100}bulk-SipMOSFET [Tak94a]withchanneldopingdensityof6.6x1017cm-3,andinanuncommon{110} bulk-SipMOSFET[Yan03]withlowchanneldopingdensity.TheUFDGpredictions areingoodaccordwiththedirectmeasurementsforNinv>4x1012cm-2,butthey offer much more insight as we will show. ForlowNinv,themeasuredmobilityislower,whichcanbeattributedto inaccuracyinthesplit-CVmethodformoderateinversion.Thestrong-inversion resultsaredramatic.Forexample,atNinv=1013cm-2theFinFETholemobilityis morethan3x-higherthanthatofthecontemporarybulk-SiMOSFET,andabout1.5xhigherthanthatoftheplanar-{100}DGMOSFET.Thesuperiorityoverthebulk-Si deviceisdueinparttotheundopedfin-UTBandthelow eeff,butnotealsothatthe degradationofmobilitywithincreasingNinvislesssevereinthe{110}-surface

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105 Figure 4.9UFDG-predictedeffectiveholemobility(curvewith m0and q given) versusintegratedinversion-carrierdensityderivedfromtheDGpFinFET calibrationillustratedinFigure4.7andFigure4.8.Thedirectlymeasured mobility(squares)forthe{110}-surfacepFinFETisalsoshown,aswell asthose(symbolsasnoted)foraplanar-{100}DGpMOSFET(tSi= 18nm),basedon[Ess00],acontemporary-likebulk-SipMOSFET(ND= 6.6x1017cm-3)[Tak94],andanuncommon{110}bulk-SipMOSFETwith low channel doping density [Yan03].0.00.20.40.60.81.01.21.41.61.82.0 0.0 50.0 100.0 150.0 200.0 250.0mp(eff) [cm2/V.s]Ninv [1013cm-2] {110} DG pFinFET measured {100} DG pMOSFET measured {100} bulk pMOSFET measured {110} DG pFinFET UFDG {110} bulk pMOSFET measured m0 = 250cm2/V-s q = 0.10

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106 FinFETthaninboththe{100}bulkdeviceandtheplanar-{100}DGMOSFET. Further,theFinFET mp(eff)fall-offislessseverethanthatinthe{110}bulk-Si MOSFET,althoughforlowNinvthemobilitiesinthesetwodevicesarecomparable. Withthelowvalueof THETA inferred,theseresultsimplylesssurface-roughness scattering of holes, i.e., smoother {110} fin-surfaces, in the pFinFET we examined. Notethatliketheelectronmobility,thechangeintheholemobilityfrom {100}-to{110}-pFinFET( @ 1.5x)isalsolessthanwhatisobservedfromthat( @ 3x) inthebulkdevices[Yan03].Thereason,webelieve,isthesameaspresentedinthe discussionofelectronmobility,i.e.,presenceofdifferentdielectricsintheFinFETs andaffectsofsubbandmodulation.However,forthepMOSFETs,theSiO2-to-SiON changetendstoenhancethenoted{100}-to-{110} mp(eff)increase,suggesting thereforethatthemc-andEj-definedbenefitsof{110}surfacesarelessinDG devicesthaninbulkdevices.Thissuggestionisconsistentwithourfindingofheavier hole masses in the {110}-surface FinFETs. ThegoodmatchofUFDG-predicted mp(eff)withthatofdatainFigure4.9 attestsUFDGsutilityasacharacterizationtool.Infact,useofUFDGtogain informationonthecarriermobilityisbeneficialintwoway,(i)UFDGcalibrationis notrestrictedtoextremelylong-channeldevices,liketheexperimentalmethods: four-probemeasurementsorsplitC-Vtechniques,(ii)theextractedUFDG parametersthemselvesgiveinsightsaboutthescatteringmechanisminthedeviceas demonstrated here.

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107 4.3 Ballistic-Limit Current Whileexperimentaldataforthe17.5nmdeviceispublished[Yu02],due toexcessiveresistivedropintheextensionssuchdataisnotveryhelpfultoget insightsonthechannelproperties.Wefindthatthechannelofthe17.5nmgate lengthFinFETin[Yu02]getslessthan0.1Vofbiasacrossit,whenthedrainbiasis 1.2V,duetoveryhighRS/Dandhenceitisnotpossibletogetanyusefulinformation onthetransportpropertiesofthechannelfromthisdevice.So,weuseUFDGto examinetheshorterchannellengthdevice,usingthetransportparametersobtained fromthelong-channelcalibration.Ifthehighmobilityobservedinthelongerchannel deviceremainssameintheshorterchanneldevices,whichispossibleiftheNSD(y) inthechannelremainslowenoughnottoeffectthemobilityathighNinv,thenthe on-statecurrentintheshorterchanneldevicemaybenearballistic.Tocheckhow closetheon-statecurrentistotheballistic-limitedcurrentweusedUFDGtopredict theID-VDcharacteristicsfora17.5nmgatelengthn-channelFinFETandthe predictionisshowninFigure4.10.Thefinthicknessischosentobe14nmasdevice withsuchthinfinisalreadyfabricated[Yu02]andalsogivesreasonableshortchanneleffectsfor17.5nmofgatelength.Theunderlaplengthisassumedtobe4.5 nmonbothsidesofthegateasthisistheoptimumvalueofLeS/LeDthatcanbeused insuchnanoscaleFinFETs[Tri05a].Theresistance,RS/Dissetto100 W-m m,of which27 W-m misduetothe4.5nmlongunderlap(extractedfromMEDICI simulation).Thesimulationisdoneforaneffectivegatebias,(VGS-Vt)of0.8V,as ITRSroadmapfor45nmnode(wherethegatelengthissimilartothatoneweare

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108 Figure 4.10UFDG-predictedcurrent-voltagecharacteristics,withandwithoutthe ballistic-limitcurrentactivated,forundopedLg=17.5nmn-channeland p-channelDGFinFETs.Thekeymodelparameters(i.e., UO THETA QMX ,and QMD )wereobtainedfromthecalibrationsofUFDGtolongLg {110}-surface FinFETs as reected in Figure 4.7 and Figure 4.3. -1.2-0.8-0.40.00.40.81.2VDS(V) 0.00 0.50 1.00 1.50 2.00ID (mA/ m m) w/o Ilim w/ IlimpFinFETnFinFETVGS Vt = 0.8V

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109 studying)projectssupplybiastobe1.0V,andthedevicetohaveathresholdvoltage ~0.2V.Thesimulationshowsthattheon-statecurrent,withthemobilityextracted fromthelong-channeldeviceis~50%higherthantheballistic-limitcurrentfor nFinFET.Thatis,theshort-channelFinFETon-statecurrentwillbelimitedby thermalinjectiononlyandhence,channelengineeringlikeintroducingstraininthe channel is not needed to enhance the mobility. 4.4 Ef fects of P arasitics, and Design Implications Forsub-20nmFinFET,wehavefoundthatthetransportwillbeballistic, sothereisnotmuchroomforchannelengineeringtoincreasedeviceperformance. Rather,ourfocusshouldbeontheeffectsofparasitics.Inthissection,weillustrate theeffectsofparasitics,thesource/drainresistancesandextrinsiccapacitances,on FinFETsperformance.Inaddition,wealsopresentcomparisonoftheeffectsof parasiticson{100}-SiSDGFinFETwiththatonahypothetical{100}-Sibulk-Si device.Thebulk-SiMOSFETissimulatedusingUFPDB[Fos02]andthekeymodel parametersarelistedinT able4.3.Thebulk-SidevicehasLeff=25nm,andisdesignedto givethecorrespondingITRS65nmnode[ITR05]recommendedIONandIOFF,withVDD= 1.1V.TheFinFETthickness(tSi=13nm)andgateworkfunction( FM=4.58eV)aretuned togivethesameIOFFasthebulk-Si;thetransportparametersthatareobtainedfromthe calibrationof{100}-SiDGMOSFET[Tri04]areused.NotethatfortheSDG,athinnern canbeusedalsotoreducetheIOFFwithouthamperingtheION,asthetSi-dependenceof IONisnotsignicantintheSDGFinFET.Theoff-statecurrentforboththebulk-Siand FinFETisthesame,0.2 m A/ m m,andtheintrinsicIONis1.2mA/ m mand2.6mA/ m m respectively.Forthering-oscillatorsimulations,weassumethewidthofthenMOSFET

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110 Model ParameterDescriptionValue L Physical Gate Length25 nm DL Source/drain-gate Overlap length0 nm TF Film Thickness20 nm TB Body Thickness16 nm NBH Body Doping (High)8x1018cm-3NBL Body Doping (Low)2x1018cm-3TOXF Front gate oxide thickness1.2 nm TPS Substrate Poly Type-1.0 TP Gate Poly Type1.0 UO Low-eld mobility250 cm2/V.s THETA Mobility tuning parameter0.9 QM Quantum-Mechanical effects tuner0.5 Table 4.3 KeyUFPDBmodelparametersusedinthestudyofeffectofparasiticresistanceand capacitance in Section 4.4.

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111 (pMOSFET)is1 m m(2 m m),andthelengthofthesource/drainis0.39 m m(6xthe1/2-pitch length).ForthenFinFETs(pFinFETs),weassumethereareseven(fourteen)nsper m m of 70nm-height. 4.4.1 Effects of Parasitic Resistance ThesaturationcurrentinMOSFET,includingtheeffectofparasiticsource resistance RS, can be written as (assuming negligible gate leakage) ,(4.5) wherevsatisthesaturationvelocityandCofissomeeffectivecapacitance(the effectivecapacitanceofFinFETistwicethatinbulk-Si);IDRSrepresentsthe reductionofeffectivegatevoltageduethedropacrossparasiticsourceresistance, RS.AssumingnegligibledependenceofvsatonVDS,differentiating(4.5)with respect to RS gives .(4.6) Eq.(4.6)impliesthattheeffectsofparasiticsismoresevereonthedevicewith higherintrinsicID,i.e.,lowerchannelresistance.From(4.6),wecandeducethatto get the same ION as that in bulk, the RS needed in FinFET is ,(4.7) IDCofVGSVTIDRS () vsat RSd d IDI DRSCofvsat()1 + ----------------------------------------Rs ,fin1 x2----Rs bulkx 1 () Cofvsat()1 + () =

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112 where x istherationofIONoftheintrinsicdevices.Notethat(Cofvsat)-1isbasically thechannelresistanceofthebulkdevice(Rch,bulk),ifeffectivegatedriveis1V.Thus for x =2 we can re-write (4.8) as .(4.8) ForthecaseinFigure4.11,Rch,bulkis917 W-m m,thusfrom(4.8),theadditionalRSFinFET can withstand maintaining the same ION as that in bulk is 229 W-m m. InFigure4.11thedegradationofIONforbothbulk-SiandFinFETis shown.TheintrinsicFinFEThasmorethan2xIONthanthebulk.Withtheaddition ofRS/D,itsIONsuperiorityhoweverdecreases,butdueitshighintrinsicION,fora reasonablerangeofRS/D,FinFETalwaysmaintainsitsIONsuperiorityoverthebulkSicounterpart.TheRS,finneededtogetthesameIONasthatoftheintrinsicbulk-Si device is 225 W-m m from Figure 4.11, in good agreement that predicted by (4.8). EventhoughFinFETIONishigherthanthatinbulk-SiinFigure4.11,as FinFEThastwicethegatecapacitancecomparedtobulk-Si,theimmediatequestion thatfollowsiscanFinFETmaintainshorterlogic-delaycomparedtothatinbulk-Si. Toseektheanswer,wesimulatea9-stageringoscillatorwithUFDG,andcompared theperstagedelay(td)inFigure4.12.Boththedevicesareassumedtohavesome bias-independentextrinsiccapacitanceCextof0.2fF/ m m.Interestingly,FinFETin spiteoftwicethecapacitance,maintainsashorterdelaycomparedtothebulk-Si device,fortherangeofRS/Dconsidered.Theexplanationofsuchperformance advantageofFinFEToverbulk-Si,evenwiththedegradationofIONwithRS/D,lies inthefactthat,duetotheundopedbody,intrinsicFinFEThaslowercapacitancein Rs ,fin1 4 -Rs bulkRch bulk+ () =

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113 Figure 4.11Effectsofparasiticresistanceontheon-satecurrentof(dash-dotline)a bulk-SiMOSFET,and(solidline)FinFET;Lg=25nm,tox=1.2nm,and VDD=1.1V.Thebulk-SiMOSFETisdenedinTable4.3,andtheFinFET is an undoped, near mid-gap gate SDG with tSi = 13nm. 0.0100.0200.0300.0400.0500.0RS/D ( W-m m) 0.0 1.0 2.0 3.0ION (mA/ m m) Bulk-Si (UFPDB) DG (UFDG)

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114 Figure 4.12Predictedpropagationdelaysversusparasiticsource/drainresistancefrom UFPDB/UFDG-aidedsimulationsofunloadednine-stageCMOS-inverter ringoscillatorcomprisingbulk-SiMOSFET(dash-dotline)/SDGFinFET (solidlines);Lg=25nm,andVDD=1.1V.Inaddition,delayofanSDG FinFET-ROwithUFDGfringing-capacitancemodelturnedon( CFF =1) isshown(line+symbols).Forthebulk-SinMOSFET(pMOSFET)area of the source/drain is assumed to be 0.39pm2(0.78pm2). 0.0100.0200.0300.0400.0500.0RS/D ( W-m m) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0Delay/stage (ps) Bulk-Si Cext = 0.2fF/ m m (UFPDB) SDG FinFET Cext = 0.2fF/ m m (UFDG, CFF = 0) SDG FinFET Cext = 0 (UFDG, CFF = 1)

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115 weakinversioncomparedtothebulk-Si,whichhasasignificantdepletion capacitanceinweakinversion.ThustheFinFETintegratedCVisnottwiceofthatin bulk,butmuchless[Kim05],whichallowsFinFETtomaintaintheshorterdelay evenwiththedegradeddrivecurrent.InFigure4.12wealsoshowtheFinFET-RO td(RS/D)withUFDGfringing-capacitancemodelturnedon(line+symbols),instead ofusingCext=0.2fF/ m m,whichisthetypicaloverlap-Cfinpresent-daybulk-Si technology,toreplicatethefringingcapacitances.WiththephysicalmodelforCfUFDG-predictedtdissmallerthanthatusingCext,indicatinglessseverefringing capacitanceintheFinFET(canbereducedfurtherifG-S/Dunderlapisused,as discussedinChapter3)comparedtoBulk-SiMOSFETwhereG-S/Doverlap exacerbates fringing capacitances. 4.4.2 Effects of Parasitic Capacitance Withthescalingoffeaturesizes,theparasiticcapacitancesinCMOS technologyareincreasingasthesource/draintogatedistancearedecreasing.To assesstheeffectsofextrinsiccapacitances(Cext)ontheperformanceofFinFETCMOS,weplottheUFDG-predictedROdelayforincreasingCextinFigure4.12.The UFPDB-predictedROdelayforthebulk-SiCMOSconsideredinFigure4.11is includedinFigure4.12.TheCextincludeslayout-dependentextrinsiccapacitances, aswellasouterfringingandinnerfringingcapacitances(herewekeptUFDG fringing-capacitancemodelturnedoff).However,fringingcapacitancesarebiasdependent,andtheireffectdecreaseswithbias[Kim06].Hence,suchlumped,biasindependent,accountingoffringingcapacitancesmakeourpredictioninFigure4.12

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116 Figure 4.13PredictedpropagationdelaysversusparasiticcapacitancefromUFPDB/ UFDG-aidedsimulationsofunloadednine-stageCMOS-inverterring oscillatorcomprisingbulk-SiMOSFET(dash-dotline)/SDGFinFET (solidlines);Lg=25nm,VDD=1.1V,andRS/D=140W-m m.Insetdenes the parasitic capacitance Cext. FG D S CextCext CextCextBG FinFET G D S CextCextBulk-Si 0.000.100.200.300.400.500.60Cext (fF/ m m) 0.0 2.0 4.0 6.0 8.0 10.0 12.0Delay/stage (ps) Bulk-Si (UFPDB) SDG FinFET (UFDG)

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117 pessimistic.Buttheinsightsregardingthecomparisonwillremainvalid.Aswiththe RS/D,FinFET-CMOSmaintainsitsperformanceadvantageoverbulk-SiCMOSfora reasonable range of Cext, due to the noted low intrinsic weak-inversion capacitance. 4.5 Summary BycalibratingUFDG,withitsQM-basedmobilitymodel,tomeasured dataofcontemporaryDGFinFETswith{110}Sifin-sidewallsurfaces,wehave shownthatholeandelectroneffectivemobilitiesinundopedfin-UTB/channelscan bedramaticallyhigherthanthoseinbulk-Sicounterpartsatthesameintegrated inversion-carrierdensity.Thecalibrationsfurtherimpliedunusuallysmoothfin surfaces,relativetotheplanar-{110}and-{100}surfacesoftestdevicesin[Ess00], [Ess01],[Yan03],and[Tak94].Also,thepFinFETcalibrationrevealedheavier(by 11%)holeeffectivemassesthancommonlypresumedat{100}Sisurfaces.UFDG simulationsofnanoscalep-andn-channelDGFinFETsthenshowedthatthehigh mobilitiesyieldon-statecurrentsattheballisticlimitsforLg<@ 20nm.These interestingresultssuggestthatstrained-Sichannelsformobilityenhancementarenot needed for nanoscale FinFETs. Thehighmobility/ballistic-limitedcurrentindicateslowchannel resistanceoftheFinFET,whichmakesitmorevulnerabletoparasiticresistance. However,comparisonofdrivecurrentofaFinFETwiththatofahypotheticalbulkSicounterpartMOSFETshowedthatforreasonablerangeofRS/D,FinFETcan maintainadrive-currentsuperiorityoverbulkdevices,duetoitshighintrinsicION. Ring-oscillatorsimulationsfurtheredshowedthatDGFinFET-CMOScanmaintain

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118 aspeed-performanceadvantageoverbulk-SiCMOSevenwithaddedparasitic resistance and capacitance.

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119 CHAPTER 5 SENSITIVITY OF FINFET PERFORMANCE TO GATE-SOURCE/DRAIN UNDERLAP PROPERTIES 5.1 Introduction Inpreviouschapters,weobservedthatnanoscaleFinFETshavingultrathinbodies(UTB)canhaveunderlapsthatcanbeusedbeneficialinoptimizing performance.TheUTBisrequiredforbettercharge-couplingbetweenthetwogates [Kim01b],aswellasforcontrollingtheshort-channeleffects(SCEs).However,the UTB,alongwiththetechnologicallylimitedfinheight(hSi)-to-thickness(tSi)ratio (rf),makesthechannelvolumetootinytoallowfaithfulplacingofasufficient numberofdopantsinthechannel.Toavoidthisproblem,anundopedbodyanduse oftunedgateworkfunctionareprescribed[Fos04b].Theundoped/intrinsicUTB facilitateshighcarriermobility,butitportendsthepossibilityofS-Dpunch-through whentheSDEsareheavilydopedtominimizeextrinsicS/Dresistance(RS/D).To preventsuchpunch-through,theSDEsarenotdopeddirectly;ratherdiffusionis facilitatedthroughannealingoftheion-implantedsource/drain,whichwhen uncontrolled,leavealongunderlapregiononeithersideofthegate,asweobserved inChapter2.However,bycontrollingthediffusionintheextension,theunderlap lengthcanbecontrolledandbeusedasacriticaldevicedesignparameter,as discussed in Chapter 3. In[Tri05a]anoptimizedFinFETfortheITRS45nmnode[Fos04b]is presented,utilizingthebeneficialunderlapsthroughcontrollingthelateraldoping

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120 profile(NSD(y))inthesource/drainextension(SDE).Astheextensionssharethe samewidthandheightwiththechannel(unlessitisflaredout),thelogicalquestions thatfollow(notingthatinbulk-Si,controllingthedopantsinthechannelisgetting increasinglydifficult)arehowwellcanthedopinginSDEbecontrolledandhowwill thevariationinNSD(y)affectthedeviceperformance.Whiletheanswerofthefirst partisnotknownconclusively,theexpectationisthatnearthegateedges,forthe UTBdevices,thedopingwillbecomerandom,andinthischapterwelookintothe effectofsuchrandomnessontheperformanceofFinFETs.Inaddition,wewillalso lookatthesensitivityofperformanceofFinFETstothevariationofotherdevice parameters that affect the underlap properties. Forthepurposeofthissensitivitystudy,weusetheoptimumFinFETin [Tri05a]asthereferencedevice,whichisof18nmgatelength,requiresapragmatic, Gaussiandoping-densityprofileNSD(y)with9.5nmstraggle( sL),andhasa20nm longextension(Lext).Thefilmthickness(tSi)ofthedeviceis14nm.InFinFET technology,limitationinetchingprocessesandmechanicalstabilityrequirements limitthefinaspectratio,rf=hSi/tSi;andatypicalrfis4.Thesmalldimensionsin bothhSiandtSimeanthatthenumberofdopantsinanincrementalvolumeoftheSDE isalsolow.Forexample,forthedesignin[Tri05a],tohaveoneatominaoneSilatticeconstant(aSi)thickslice,therequireddopingdensityis2.3x1018cm-3.In Figure5.1,wehaveplottedthenumberofdopantsinthey-direction,fromsourceto drain,correspondingtothedopingprofileproposedin[Tri05a]fortheoptimized FinFET.Togetthenumberofdopants,weapproximatedtheGaussianNSD(y)with aseriesofstepfunctionsofwidthaSi.Thedopingdensityineachstep,Nstep,isthe averagevalueofthedopingconcentrationfromtheoriginalprofileforthatstep.The

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121 Figure 5.1ThelateralS/D-extensiondopingconcentrationNSD(y)proposedin [Tri05a]forthe optimumDGFinFETattheITRS45nm-node.The numberofdopantsarecalculatedwithinasliceofvolume hSitSiaSi, whereaSiisthesiliconlatticeconstant,andhSiisassumedtobe4tSi.The NSD(y)proleisapproximatedasthesumofstepfunctionstoobtainthe average dopants within each slice. 0.010.020.030.040.050.060.070.080.0Distance along y (nm) 10161017101810191020Doping Concentration (cm-3) Gaussian Profile Step function appr. 0 0 1 10 100Number of Dopants Lg Leff SourceDrain

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122 numberofdopantspersegmentthencomesfrom NstepxVslice,whereVsliceisthe volumeofasliceintheS/DextensionofwidthaSi.NoteinFigure5.1thatnearthe gatethenumberofdopantis~1atom/sliceorlessthanthat.Whentheactualnumber ofdopantsisthislow,thewholediffusionprocessbecomesarandomevent.Thatis, eventhoughthedopingprofileintheS/DextensioniscontinuousGaussianhere,in reality,nearthegateitwillbecomeadiscontinuousrandomfunction.Hence,there maybeasignificantvariationofS/Ddopingintheextensionfromdevicetodevice. Studyofsuchrandomnessofdopantsisusuallydoneusingatomistic simulation[Ase98]ofalargesampleofdeviceswiththeobjectiveofobtaining statisticalfluctuationparameters.However,ourfocushereistoassesstheviability ofintroducingunderlapasadesignparameter,ratherthanobtaininganaccurate quantitativepicture.Hence,welookattheextremecasesofvariationusinga2D numericalsimulator,MEDICI[MED04],inconjunctionwithourphysics/processbasedcompactmodel,UFDG[Fos04a].MEDICIsolvesthe2DPoissonequation accurately,howeveritstransportmodel,orthequantum-mechanicalmodel,isnot calibratednorverifiedfortheUTBdevices.Fortunately,thereferenceFinFEThas thickenoughfilm(oneoftheadvantagesofhavingunderlap,asusedin[Tri05a],is thatitrelaxesthefinthicknessrequirement;seeChapter2)soasnottohaveour conclusionsbeunderminedduetothenoteddeficienciesofthenumericalsimulator. WhenlookingatthesensitivityofION,IOFForVtonvariousprocess/device parameters,wethususeMEDICI,butwhenwearelookingintotheeffectofsuch variationofcircuitperformance,likering-oscillator(RO)delay(td)orstaticnoise margin(SNM)ofSRAM,weuseUFDGforbothprojectionaccuracyaswellastime-

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123 efficiency.UFDGtransportandQMmodelsareperfectedforUTBdevices,butbeing acompactmodel,itdoesnotcomprehensivelysolvePoissonsequationforarbitrary NSD(y).Hence,wefirstuseUFDGtocalibrateMEDICI-predictedweak-inversion characteristicsofdeviceswithdifferentNSD(y)toobtaintheequivalentdevice.Once theequivalentdeviceisfound,weturnontheQMmobilitymodelandballisticlimit model[Tri05b]inUFDGtoprojectthetdandSNM.ThevaluesforUFDGtransportmodelparametersareobtainedfromUFDGcalibrationtoexperimentalFinFETs fabricatedatFreescaleSemiconductor(seeChapter2andChapter4).Thesource/ drainresistanceduetotheG-S/Dunderlap,aswellastheextension,isextractedfrom MEDICIfollowing[Tau98].Inthenextfewsections,afterdefiningthereference device,variationsofitscharacteristics,anditsspeedandSRAMperformance,due tothevariationsinthecriticaldevicedimensionsliketSi,Lgandprocessparameters like straggle, and the effects of randomness of the NSD(x,y), are presented. 5.2 Reference FinFET Afterchoosingthepragmaticdevicepresentedin[Tri05a],whichis designedfortheITRS45nmnode(Lg=18nm)[ITR03],asthereferencedevice,the firstproblemistoknowtheLeffofthedevice.Theeffectivechannellengthfor FinFETwithunderlapisbias-dependent,asshowninChapter2,andismodeledby (3.24)and(3.32)inweakandstronginversionrespectively.Forcompletelyundoped, shorterextensions,LeS(LeD)in(3.24)isapproximatelyequaltothelengthofthe undopedpartoftheextension.However,fordeviceswithmoderatelydoped extensions(possiblewithNSD(y)similartothatinFigure5.1)therelationofLeS(or LeD)withextensionlength(Lext)and sLisnon-trivial(adiscussionontherelation

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124 ofLeS/LeDwith sLandLextispresentedin[Tri05b]).Forthiswork,wecircumvent theproblemofobtainingLeffin(3.24)fordeviceswithnon-abruptNSD(y)by employingUFDGtocalibratetheMEDICI-predictedcharacteristicsofthedevice represented by NSD(y) in Figure 5.1. InFigure5.2,thecalibrationresultfortheweak-inversioncharacteristics ofthereferencedeviceisshown.UFDGpredictionsareinexcellentagreementwith MEDICI-simulatedresultsforLeff=27nm,andusing(3.24)wegetLeS=LeD=4.5 nm.Notethattheunderlaplengthsarewithintherangeoftheoptimumunderlap lengthfoundinChapter3.Ourreferencedeviceisnowwelldefined,withLeff= 27nm,Lg=18nm,tSi=14nm,toxf=toxb=1nm,hSi=4tSi,undopedbody,mid-gap gate,andwiththeNSD(y)showninFigure5.1.ForthereferencedesignwithVDD= 1.0V,MEDICIpredictedIOFFis14nA/ m m,IONis1.16mA/ m m,andthethreshold voltage (Vt) is 215 mV. Oncetheequivalentdevicestructureisobtainedfromthecalibration,we turnonUFDGQMmodel,andusetransportparametersobtainedfromearlier calibrationresultstopredictcircuitperformance.InUFDGsimulation,MEDICIextractedRS/Dof98 W m misusedthatincludestheresistanceduetotheG-S/D underlap(ReS/D)andsheetresistanceofthehighlydopedextension;howeveritdoes notconsiderthecontactresistance.TheUFDG-predictedFinFETperformance parametersareVt=235mV,IOFF=6.3nA/ m m,ION=1.21mA/ m m.Thedifference betweenUFDGandMEDICIpredictedVt(andIOFF)isduetotheuseoflowerlowfieldmobilityvalueusedinUFDGandconsiderationoftheQMeffectsinUFDG. TheIOFFprojectediswellbelowtheITRStarget[ITR03],whichis100nA/ m mfor

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125 0.00.10.20.30.4VGS (V) 10-1010-910-810-710-610-510-410-310-2ID (A/ m m) MEDICI UFDG Figure 5.2PartialcalibrationofUFDGtoMEDICI-predictedcharacteristicsofthe referencedevice.Verygoodagreementofweak-inversioncharacteristics between UFDG and MEDICI are obtained for Leff = 27nm.VDS = 1.0V 50mV

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126 the45nmnodehighperformance(HP)devices,buttheIONdoesnotmeettheITRS target of 1.9mA/ m m. UFDGpredictedROdelayforthenoteddesignisanimpressive2.78ps andtheSRAMstaticnoisemargin(SNM)is178mV.ThedesignoftheSRAMcircuit cellfollowsthatof[Zha06],whichisfocusedonmaximizingSRAMcelldensity,not necessarilyoptimizingtheperformance.TheROcircuitdelaymightalsodiffer dependingonthechosenparasiticcapacitancevalue.Weusedapessimistic0.16fF/ m mcapacitancepergate-source(drain)toaccountfortheeffectsoffringing(both innerandouterfringing)andparasitics.Layout-dependent,back-endprocessrelated capacitances were not considered. Notethatinthissensitivitystudy,weallowalltheFETsintheRO(Figure 5.3(a))ortheSRAM(Figure5.3(b))tovaryinasimilarfashion,whichmightnotbe thecaseinreality.However,devicesincloseproximityinthewafertendtovaryin asimilarfashion.(Forexample,dopingconcentrationinthemiddleofthewafer tendstobehigherthanthatneartheedges,hencethedevicesinthemiddletendto havehighernumberofdopantsthanthemean.)Moreover,SRAMcellstability,to firstorder,dependsonthethresholdvoltageofthedriverFET(pull-down),VDD,and W/Lratioofaccessanddrivertransistor[See87].Asourfocusisontheeffectsof variationofextensionparametersthatdoesnotaffectVDDandW/L(theLhereisthe strong-inversionLeff,from(3.32),whichisindependentoftheunderlaps)ratios, such an en mass variation of FinFETs in the cell is reasonable.

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127 Figure 5.3FinFET-CMOScircuitsusedinthesensitivitystudy,(a)onestageofthe9stageRO,and(b)the6TSRAMcell[Zha06].FortheROcircuit,theW/L ratio,Mpd/Mpuisassumedtobe2,andfortheSRAM,M1/M5(orM3/M6) is assumed to be 1 (not necessarily optimized for stability). BLBL WL VDDM1M3 M2M4 M5 M6 VLVR MpdMpu VDDAccess Access Driver/ pull-down Driver/ pull-down(a) (b)

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128 5.3 Effects of Variation of Film Thickness Oneofthepragmaticfeaturesoftheoptimumdevicediscussedhere,as mentioned,isthatitemploysarelativelythickerSifilm,whichismucheasierto fabricate.However,thevariationintSiisunavoidableduringfabricationdueto systematicprocessvariations,likemaskdefects,globalvariations,likeprocess-tool bias,andlocalvariations,likeetchingmismatch.InUTBdevices,filmthickness determinestheseverityofSCEs,quantum-mechanical(QM)effects,phonon-limited mobility,bulkinversion,andthesource(anddrain)seriesresistance,RS(andRD). Forthethicknessweareconcernedhere,thethicknessdependenceofthebulk inversionissomewhatirrelevant[Ge02b],phonon-limitedmobilityisinsensitiveof thethickness[Tri05b]andQMeffectsarenegligibleforweak/moderateinversion [Ge02b].Hence,inweakinversionweexpecttheVtandtheIOFFtovarywiththetSiduetothevariationinSCEs,andinstronginversion,theIONtovarymainlydueto the variation of Vt and RS/D. InFigure5.4,MEDICI-predictedvariationof(a)Vt,(b)IOFFandIONdue tovariationoftSiareshown.For10%increaseintSi,increasedSCEsdecrease thresholdvoltageby~20%andincreaseIOFFbyafactoroffour.Eventhough variationofIOFFissharp,astheIOFFforthereferencedeviceisquitelow(forHP devices),theeffectofvariationoftSionIOFFistolerable.A10%increase(decrease) intSiincreases(decreases)IONby4%,whichisduetothedecreased(increased)Vtmainly, as the change of RS/D due to the change of tSi is minimal.

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129 -10.0-5.00.05.010.0 -24.0 -16.0 -8.0 0.0 8.0 16.0 24.0Variation of Vt (%) -10.0-5.00.05.010.0 0.0 1.0 2.0 3.0 4.0 5.0Ratio of IOFF to IOFF(ref) -10.0 -5.0 0.0 5.0 10.0Variation of ION (%) -10.0-5.00.05.010.0Variation of tSi (%) -10.0 -5.0 0.0 5.0 10.0Variation of td (%) -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0Variation of SNM (%) Figure 5.4SensitivityofFinFETperformance-parameterswiththevariationoftSi. (a)MEDICI-predictedvariationofthresholdvoltage,(b)variationofIOFFand IONand (c) UFDG-predicted variation of td and SNM with tSi. (a) (b) (c)

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130 Figure5.4(c)showstheUFDG-predictedvariationoftdandSNMwithtSi. TheeffectoftSivariationis,relatively,lesssevereontd,for10%variationintSi;the maximumvariationobservedis8%.TheSNM,whichfollowsthethreshold variation,showsamaximumof12%variationdueto10%changeinthetSi.The variationsinthedelaycomesfromthevariationofcurrentwithtSi,astSivariation hasinsignificanteffectonthegatecapacitance,CG(forthenotedtSirange).Notethat intheCV/Idelaymetric,thecurrentIisnotsimplytheION,ratheritissome averageoflinearandsaturationcurrent[Na02].Asthelinearcurrentismore sensitivetoRS/D(tSi)variation(comparedtoION),thevariationintd(tSi)inFigure 5.4(c) is more than that of ION(tSi) in Figure 5.4(b). 5.4 Effects of Variation of Gate Length Asthecasewithbulk-SiMOSFET,gateisstillthemajordeterminantof theSCEsinUTBdevices.Effectsofvariationofgatelengthcanbestudiedintwo ways,onebykeepingthedistancebetweenthesourcetodrain(2Lext+Lg),constant andvaryingthegatelength;andinthesecondcase,bykeepingtheextensionlengths constantwhilelettingLgvary.Thefirstkind,whichisabsentinthepresent-day technologies,isstudiedwithMEDICIinFigure5.5,whereweonlytakealookatthe deviceleveleffectsofvariationofgatelengthwhilekeepingdistancebetweensource anddrainfixed.Asexpected,increased(decreased)SCEswithdecreased(increased) Lgdecreases(increases)Vt,andincreases(decreases)IOFF.However,interestingly, theon-currentincreaseswiththeincreasinggatelength(contrarytothetypical Leff -1dependenceofION).IncreaseofgatelengthdecreasesLeS/Dandhencethe resistanceReS/Ddecreases,whichcausestheincreaseintheION.Amaximumof12%

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131 -10.0-5.00.05.010.0 -16.0 -12.0 -8.0 -4.0 0.0 4.0 8.0Variation of Vt(%) -10.0-5.00.05.010.0 0.0 1.0 2.0 3.0Ratio of IOFF to IOFF(ref) -15.0 -10.0 -5.0 0.0 5.0 10.0Variation of ION (%) Variation of Lg (%) Figure 5.5SensitivityofFinFETperformance-parameterswiththevariationofLg. MEDICI-predictedvariationof(a)thresholdvoltage,(b)IOFFandION(bottom)withgatelength.Thesourcetodrainlengthwaskeptconstant (Lg + 2Lext).(a) (b)

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132 variationinIONisobservedfora10%variationinLg,whereastheIOFFcanincrease by 3x for the same amount of change in Lg. Thesecondtypeofgatelengthvariation,wheretheextensionlengthsare insensitiveofthegatelengthvariation,ismorerealistic.Becauseinstate-of-the-art technologies,theextensionlengthsaredefinedbythespacers,lengthofwhichis independentofLg-variation.Forthistypeofvariation,thedopingprofileinthe extensionremainsunchanged,i.e.,LeS/LeDandRS/Dremainunchanged.So,wecan stillexpectvariationinIONandIOFF,howeverinlessermagnitude.InFigure5.6 MEDICI-predictedvariationofVt(Figure5.6(a)),IOFFandION(Figure5.6(b)),and tdandSNM(Figure5.6(c))withthevariationofLgisshownforthiscase.Fora10% variationinthegatelength,amaximumof20%variationinVtisobserved,whichin turnchangestheIOFFby4x.ThemaximumchangeinIONismerely0.5%.However, themaximumchangeintdis5%,reflectingmainlythevariationinCGduetothe variationinLg.For10%changeinLg,themaximumchangeobservedinSNMis 12%, (follows the change in Vt). 5.5 Effects of Variation of Lateral Straggle Likethedevicedimensions,thelateralstragglecanalsovaryfromdevice todevice,dietodie,andchiptochip.LateralstraggledefinestheLeff[Tri05a],and affectstheRS/D.Hence,boththestrong-andweak-inversionperformance parametersareexpectedtovarywith sL.Figure5.7(a)showsthevariationofUFDGpredictedLeffandMEDICI-predictedVtwiththevariationof sL.A10%increasein sLdecreasesVtby23%andincreasestheIOFFby~6x(Figure5.7(b)),whereasa 10%decreasein sLincreasesVtby15%anddecreasesIOFFby3x.Herethe

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133 -10-505.010.0 -20 -15 -10 -5 0 5 10 15 20 Variation of Vt (%) -10-50510 0.0 1.0 2.0 3.0 4.0 5.0Ratio of IOFF to IOFF(ref) -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6Variation of ION (%) -10 -8 -6 -4 -2 0 2 4 6 8 10Variation of SNM (%) -10-50510Variation of Lg (%) -12 -8 -4 0 4 8 12Variation of td (%) Figure 5.6EffectsofvaryingLg,butkeepingLextconstant,onthesensitivityof FinFETperformance.MEDICI-predictedvariationof(a)threshold voltage,(b)IOFFandION,and(c)UFDG-predictedtdandSNMvariations with the variation of gate length are shown in. (a) (b) (c)

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134 -25 -20 -15 -10 -5 0 5 10 15 20Variation of Vt (%) -10-50510 -10.0 -5.0 0.0 5.0 10.0Variation of Leff (%) -10-50510 0.0 1.0 2.0 3.0 4.0 5.0Ratio of IOFF to IOFF(ref) -20.0 -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0 20.0Variation of ION (%) -10.0-5.00.05.010.0DsL (%) -20.0 -10.0 0.0 10.0 20.0D RS/D (%) -10-50510Variation of sL(%) -10.0 -5.0 0.0 5.0 10.0Variation of td (%) -15.0 -10.0 -5.0 0.0 5.0Variation of SNM (%) Figure 5.7EffectsofvariationoflateralstraggleonthesensitivityofFinFET performance.Figureshowsvariationof(a)theeffectivechannellength (Leff)andthethresholdvoltage(Vt),(b)IOFFandION,(c)tdandSNM variationswithlateralstraggle( sL).ThevariationofRS/Disshowninthe insetof(b).Thereference sLis9.5nm.TheLeffin(a),tdandSNMin(c) arefromUFDGsimulations,whilerestoftheparametersarefrom MEDICI simulations. (a) (b) (a) (c)

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135 asymmetricvariationofVt(andIOFF)ismainlyduetothenonlinearvariationofLeffwith sL.ThevariationofUFDG-predictedLeffwith sLshows(Figure5.7(a))that theincreaseof sLchangesLeffmoreseverelythanthedecreaseof sLdoes.The reasonforsuchasymmetrycanbeexplainedby(3.23).TheextentofLeS(LeD)inthe source(drain)extensionaredefinedbyacertaincarrierconcentration,sayneS(cm-3),whichishighenoughtogiveasmallerDebyelengthandusuallyliesinthe vicinityof5x1018cm-3.When sLislarge,i.e.,NSD(y)isflatter,neSisdefinedbythe NSD(y)andincreaseof sLdecreasesLeS(LeD),andhenceLeffdecreasessharplywith theincreaseof sL.However,when sLisdecreasing,NSD(y)becomesmoreabrupt, andneSisdefinedbythespilledoverelectronsintheextensionfromthesource/ drain,andbecomeslessdependentontheNSD(y).Hence,Leffbecomeslesssensitive of sL, as the latter decreases after certain value. InFigure5.7(b)thevariationofIONwith sLisshown.With10%variation in sL,IONcouldvaryashighas18%.Suchvariationisduetothevariationofboth VtandRS/D(shownintheinset).Thevariationofextensionresistancecouldbequite significant,asshowninthefigure.For10%variationof sL,themaximumvariation inRS/Dis~20%.However,ifcontactresistanceisconsidered,percentagevariation oftotalRS/Dwillbeless,butwiththevariationof sL,themodulationofsheet resistance and ReS/D will remain significant. TheUFDG-predictedvariationoftdandSNMareshowninFigure5.7(c). Thevariationoftdfollowsthatof1/IONindicatingnosignificantchangeofgate capacitanceduetothevariationof sL.ThevariationofSNMfollowsthatof1/IOFF, astheleakierpull-downtransistorsreducethestabilityoftheSRAMcell.Fora10%

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136 changein sLamaximumof7%variationintdand13%variationinSNMisobtained for our design. 5.6 Effects of Random Doping 5.6.1 NSD (y) Randomness TostudytheeffectsofNSD(y)randomness,hereweonlyvarythedopants withinthatpartoftheextensionwhichcontributestotheeffectivechannellength, i.e.,withinLeS/LeD.TwoextremecasesofNSD(y)variationsareconsidered;thefirst case(profiley_ainFigure5.8)iswhenthenumberofdopants/slicewithinLeS(LeD) isconstantandequaltothenumberatthebeginningoftheLeff,whichis~3atoms/ slice(Figure5.1)foraFinFETwithhSi=56nm.Inthesecondcase(profiley_bin Figure5.8),weassumethenumberofdopants/sliceiszerowithinLeS/LeD.Inboth thecases,thenumberofatomsinthechannelunderthegateisassumedtobezero, asassumingthesameforthereferencecasedoesnotchangethedevice characteristics noticeably. MEDICI-predictedperformanceparametersofthedeviceshavingNSD(y) asinFigure5.8arelistedinTable5.1.Fortheprofiley_a,wherethenumberofntypedopantswithinLeffishigherthanthatofinthereferenceprofile,Vtdecreases by8%.TounderstandthevariationofVt,weusedUFDGtocalibratethedevice characteristicswithdifferentprofilesandfoundthattheLeffisdifferentforallthree cases.TheLeffchangesby5%fromthereferencedeviceforthetwoextremecases andasnootherparametersintheUFDGmodelcardarechanged,weconcludethat thechangeintheLeffissolelyresponsibleforthevariationofthesubthreshold

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137 Figure 5.8Variouslateraldopingprolesforstudyingtheeffectsofsource/drain dopingvariationintheextension.Table5.1showsthecorresponding variations in the performance parameters. 0.010.020.030.040.050.060.070.080.0Distance along y (nm) 10161017101810191020NSD(y) (cm-3) Reference Profile Profile y_a Profile y_b LgSourceDrain

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138 Prole Leff(nm) RS/D( W m m) S (mV/ decade) DIBL (mV/ V) Vt(V) IOFF(nA/ m m) ION(mA/ m m) td(ps) SNM (V) Ref27.196841070.215141.162.780.178 y_a26.386861210.195281.312.640.172 y_b28.610381920.2554.370.932.850.189 Table 5.1 MEDICI-andUFDG-predictedcharacteristicsofFinFETswithNSD(y)shownin Figure 5.8

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139 parametersinTable5.1.WhentherearemoredopantswithinLeS/D(profiley_a),the donordopantconcentrationtherebecomesquitehigh(~7x1018cm-3forprofiley_a), whichtranslatesintosmallerDebyelength(~1.5nminthiscase),andcaneffectively screenthegateinducedelectricfield,andthusreducestheLeff.Similarly,absence ofdopantatomsintheextensionextendsthegate-controlledregion,andLeffincreases for the second case. Notethat,asthechangeinthedonorconcentrationoccursoutsidethe physicalgatelength,theydonoteffecttheworkfunctiondifferencebetweenthegate andthechannel,andonlyvariestheLeffslightly.Incontrast,thevariationofbody dopinginthebulk-Si,wherethegate-bodyworkfunctiondifference,aswellasthe contributionofdepletionchargechangeswiththevariationofchanneldopants, variesVtsignificantly.Thus,thecontrolofVtbyintroducingunderlapismuchmore viablethanbycontrollingthedopantsinthechannel.(Nottomention,forthe referencedevice,itisimpossibletogetareasonablethresholdvoltagewith polysilicongateandhighlydopedbody.Oneneedstouseacombinationofhighly dopedbody,thintSi,andsomenearmid-gapgatetogetathresholdvoltage~0.2V). AlsoinTable5.1,theMEDICI-predictedIONislistedcorrespondingto differentprofilesinFigure5.8.MaximumvariationinIONobservedis~20%from thereferencedevice,andhappenswhentherearenodopantswithinLeS/LeD.The variationisduetothechangeinthethresholdvoltageandsource/drainresistance.A maximumof8%variationintdanda10%variationinSNMispredictedbyUFDG for these extreme cases of randomness of the dopants within LeS and LeD.

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140 5.6.2 NSD (x) Randomness Likeinthepreviouscase,thedopingintheextensioncanbedistributed randomlyinthex-directionalso.Hereaswellweconsidertwopossibleextreme casesonly,oneofwhichiswherealltheatomsineachslice(Figure5.9(a))are placedneartooneofthesurfaces(henceforthreferredasprofilex_a)andtheother iswherealltheatomsareinthemiddleofthechannel(Figure5.9(b),henceforth referredasprofilex_b).Inboththecases,thenumberofdopantatoms/sliceisthe sameasforthereferencecases,howeverthecarrierconcentrationischangedto reflectthelocalizationoftheatomsinthespecifiedpartofthechannel.Weexpect theplacementofthedonordopants(forn-channel)toinfluencethethresholdvoltage dependingontheirpositionrelativetotheleakagepath.InanundopedFinFET,the leakagepath(i.e.,wherethecarrierconcentrationisthelargest)isatthecenterofthe channel,sowhenthesource/draindopantsgatheraroundthemiddleofthefin (profilex_b),theyincreasetheconduction(provideapunch-throughpath)and decreasethresholdvoltage.InFigure10,MEDICIpredictedID-VGcharacteristics followourexpectation,andprofilex_bdoesgivetheworstshortchanneleffects.For thecaseofprofilex_a,whenallthedonordopantsareplacednearoneofthe surfaces,theireffectscomefromthereductionofthedonorsfromthemiddleofthe channel,comparedtothatofthereferencedevice,andVtincreasesslightly.Asthe donordopinglevelisnegligibleinthechannel,inquantitativeterms(insetofFigure 5.10)thechangeinIOFFandION,duetothedifferentplacementofthedonordopants, isnotalarming.Amaximumof3.5%changeintheIONispredictedbyMEDICIfor

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141 NSD (cm-3)Distance along y (nm)Distance along x (nm)Distance along y (nm)NSD (cm-3)Distance along x (nm) Figure 5.9Localizationoflateraldopants,NSD(y)atdifferentx,allthedopants withinLeffareassumedtobecrammednear(a)thefrontsurface(prole x_a), and (b) in the middle of the lm (prole x_b). (a) (b)

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142 0.00.10.20.30.40.50.60.70.80.91.0 10-1010-910-810-710-610-510-410-310-2 ID (A/ m m)VGS (V) Ref. prole Prole x_a Prole x_b Figure 5.10MEDICI-predictedID-VGScharacteristicsforthedevicewithNSD(x,y) showninFigure5.9.Insetshowsthepercentvariationofdifferent performance parameters with respect to that of the reference FinFET.Prole D Vt(%) IOFF/ IOFF(ref) D ION (%) x_a2.80.13-0.26 x_b-4.61.33.5 VDS = 0.05V 1.0V

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143 thevariationoftheplacementofNSD(x)studiedhere.Thechangesincorresponding RO delay were negligible as well, only 0.35%. 5.6.3 Random UTB/Channel Doping WenotethatforextremecasesofrandomdistributionofSDEdopantsin boththex-andthey-directionforthedeviceunderconsideration,thevariationinthe performanceparametersisbearable.However,forextremelyscaleddevices,where onesingleatominthechannelcanaltertheelectricfieldsignificantly,thevariations inperformancesmaybesignificant.Tochecksuchscalingeffects,weconsidera hypotheticaldevicewith5nmfilmthickness,25nmofheight,and10nmofgate length.(Notethatsuchdevice,withpresenttechnology,isnotpossibletorealize withoutacceptinglowyield.)Thedeviceissimulatedusingthe3DsimulatorTaurusDevice[Tau04],usingthedrift-diffusiontransportmodelwithoutconsidering quantizationeffects.The dopants(1acceptor/donor)aremimickedinTaurus-Deviceby introducingequivalentconcentration(4x1019cm-3)ina 1nmx1nmx25nm volumewithin thedevice.However,wehavefoundthatthechoiceofvolumedoesnotaffectthesimulation results signicantly. TheTaurus-predictedID-VGScharacteristicsofthe10nmn-channel FinFETwith1acceptor/donorisplottedinFigure5.11.Thepositionofthedonor/ acceptorischosensothatitseffectismaximized;i.e.,thedonorisplacedinthe middleofthefilm,ontheleakagepath,andtheacceptorisplacednearthesurface. Theplacementofthedonorintheleakagepathincreasesthepunch-througheffect thatdecreasesVtby23mVandincreasesIOFFby2xcomparedtotheundopedcase;

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144 Figure 5.11Taurus-Device-predictedeffectsofuncontrolleddopingonID-VGScharacteristicsofascaledundoped,mid-gapgateFinFET,withLg= 10nm,hSi=25nm,tSi=5nm,inbothlogarithmicscale(left)andlinear scale(right).Drift-diffusiontransportmodel,withoutquantumeffectsare considered. 0.00.10.20.30.40.50.60.70.80.91.0VGS (V) 10-1010-910-810-710-610-510-4ID (A) No dopants 1 acceptor 1 donor 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20ID (mA) VDS = 0.05V VDS = 1.0V

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145 howeverIONdoesnotchangesignificantly.Whentheacceptorisplacednearthe surface,itreducestheeffectivegatebiasavailableforchannelinversion,aspartof itisspentindepletingthedevice(someeffectiveQD/Cof),therebyincreasingthe threshold voltage by 30mV, and reducing ION by ~3%. Thedrift-diffusionsimulation,heredonotpredictanyalarmingissues withanadditionaldonordopantinthechannelforthisextremelyscaleddevice either.However,useofquantum-mechanicalmodeltoincorporatetheeffectof influenceofalocalized,deltapotentialintroducedbytheunintentionaldonoror acceptor,andmoreappropriateaccountingofimpurityscattering(likeusingMonteCarlomethod)mightaltertheconclusionsdrawnhere,especiallyinstronginversion [Dol04]. 5.7 Worst-Case Scenario Inthissection,welookattheeffectsofvariationofalltheparameters considered(exceptNSD(x)randomness)atthesametime.Asfoundearlier,the randomnessoftheNSD(x)doesnotaffectthereferenceFinFETperformance significantly,andhencehereweexcludestudyofeffectsofsuchvariation.Sofarwe havefoundthattheworstcasedependsontheapplication;forexample,whilehigher IONdecreasestheROdelay,theassociatedhigherIOFF(ordecreasedthreshold) degradestheSRAMSNM.Assuch,herewelookatthescenariowhereallthe parametersvaryinawayeithertogivethehighestIONorthelowestION.Thefirst case,termedasCaseA,occurswhentSiincreasesby10%,Lgdecreasesby10%, andtheextensiondopingprofileislikethatofProfiley_ainFigure5.8,i.e.,allthe parametersvaryassuchthattheSCEsaremaximum.Forthesecondcase,termedas

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146 'CaseB',alltheparametersarevariedassuchthattheSCEsareminimum.Notethat suchanextremevariationofalltheparameterstogiveworstperformanceisan unlikelyeventinreality.Howeversuchastudycanhelpustochecktheviabilityof ourdesignapproach,namelyuseoftheG-S/DunderlapinFinFETs,especiallyifthe study does no reveal any extreme variation of performance. Tomakeourpredictionsmorereliable,weslightlychangetheapproachof thisworst-casestudy.WegettheequivalentdevicestructurebycalibratingUFDGto MEDICIpredictions,andturnonUFDGQMandballistictransportmodels,justlike theapproachfollowedpreviously.However,herewetheusetransportparameters (fornFinFET, m0=565cm2/V.s, q =0.2,etc.)obtainedfromthecalibrationresults ofChapter4.Eventhoughthereisnotquantitativechangeintheconclusions,useof the updated mobility-model parameters increases the reliability of our predictions. Table5.2showsthecomparisonofUFDG-predicteddeviceandcircuit performancesforcasesAandB.Apparently,whenalltheparametersvarytogive theworseSCEs,theleakagecurrentcanincreasebythreeordersofmagnitude,two ordersofwhichcomefromthevariationoftSiandLgonly.Theworst-casedelay happensforcaseBwhendelayincreasesby11%.ForSNM,theworstcasehappens whenthedeviceisleakier(CaseA),whereSNMdecreasesby50%comparedtothe referencecase.FortheSRAMapplication,wefoundthatthevariationoftSiandLgalonecanworsenthereadstabilityby35%.Introductionofunderlapaddsanother 15%variation.Incontrast,theRO-delayvariationisnotaffectedmuchbythe underlap;neitherCnorIinthedelaymetric,CV/I,degradessignificantlywiththe dopants in the extension.

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147 Case A : D tSi = +10%, D Lg = -10%, and NSD(y) is like the prole y_a in the Figure5.8 with Dsl = +10%. Case B : D tSi = -10%, D Lg= +10%, and NSD(y) is like the prole y_b in the Figure5.8 with Dsl = -10%.Scenario Vt(V) IOFF(nA/ m m) ION(mA/ m m) td(ps) SNM (V) Case A0.0612841.40 1.940.083 Ref0.239.71.2 2.680.169 Case B0.220.171.12.990.202 Table 5.2 UFDG-predictedvariationofperformanceofFinFET-CMOSwithextremeanden masse variation of all the design parameters.

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148 AprobablewaytoreducethesensitivityofSRAMSNMistoincreasethe underlaplength.Forexample,inFigure2.9(a)weobservethatSCEsbecomeless sensitivetounderlaplengthswhenLeS/LeD>5nm.Also,longerunderlaplengthwill decreasethecarrierconcentrationneargate-edges,andeffectsoftheirfluctuation willbeless.However,longerunderlaplengthwilldecreaseaccesstimeashigh RS/DwillreduceION.Hence,furtherstudyisneededtochecktheviabilityof nanoscale FinFETs with underlaps for SRAM circuits. 5.8 Summary Effectsofvariationindevicedimensions,likeSi-filmthicknessand physicalgatelength,andprocessparameters,likelateraldopingstraggle,onthe performanceofnanoscaleFinFETsdesignedwithunderlapwerestudied.Forthe underlapdesign,thevariationinLgdoesnoteffectdevicecharacteristicsseverely, whereasvariationinstragglecouldeffectdeviceperformance,especiallyIONsignificantly,duetothestrongdependenceofLeffonNSD(y).Asforthevariationin circuitperformance,duetothenotedparametervariations,FinFET-CMOSspeedperformancesuffersless,comparedtoFinFET-SRAMreadstability.TheSNM,due toitssensitivenesstotheweak-inversioncharacteristics,showsmoredependenceon tSi,Lgor sLvariationthantheROdelay.Amaximumof~15%variationcanoccur inSNMfor10%variationinoneofthenotedprocess-dependentparameters.When alltheparametersvaryatthesametimetogiveworsedevicecharacteristics,the variationintheSNMcanbeashighas50%.Conversely,whenalltheparametersare variedtogivelongerdelay,theFinFET-CMOSspeed-performancesuffersby11% only.Hence,weconcludethattheintroductionofoptimumunderlap(4-5nmforthe

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149 ITRSnodeconsideredhere)tooptimizeFinFETwillnotintroducesignificant additionalvariationinitsspeed-performance,aslongasthe3 s variationsofthe deviceparametersdonotexceedtherangeofvariationconsideredhere(10%) considerably.However,furtherstudy,ofstatisticalnature,isneededtodeterminethe viability of FinFET with similar underlap lengths for SRAM application. WealsonotethateventhoughtheSDEdopantdistributionofnanoscale FinFETswillberandomnearthegateedgesduetoultra-smallvolume,ourstudy showedthattheirrandomnesswillnoteffectthesubthresholdcharacteristicsofthe deviceseverely,astheSDEdopantsdonoteffecttheflat-bandvoltageandcontribute littletothechanneldepletioncharge.Theirplacementinthechannelisalsoless critical,asforthewell-tempereddevicetoavoidsource-drainpunchthroughthe actualnumberofSDEdopantsinthechannelshouldbeminimal.Afurtherstudy,of statisticalnature,canbecarriedouttoquantifytheeffectsofpossiblevariations. However,qualitatively,wecanconcludeherethattheperformanceenhancementof nanoscaleFinFETprovidedbytuningtheunderlap,alongwiththetunedgatework function, is a viable design goal, especially for logic circuitry.

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150 CHAPTER 6 GATE TUNNELING CURRENT IN NANOSCALE FINFETS 6.1 Introduction Inpreviouschapterswelookedintotheelectrostaticsandexaminedthe transportpropertiesoftheFinFET.Weobservedthatelectricalintegrityofthe FinFETchannelisquitegoodduetothetwogatescomparedtobulk-Sidevices,and withtheuseofG-S/Dunderlapcanbebettered,furtherallowingscalingofFinFET towardstheendoftheroadmap.BesidesdegradedSCEs,scalingofthebulk-Si MOSFETalsosuffersfromincreasedgateleakageduetotunnelingcurrentthrough thegateoxidebarrierasitsthicknessisscaleddown.Intuitively,intheFinFET,due tolowertransverseelectricfieldinthechannelstemmingfromundopedbody,the gatetunnelingcurrentisexpectedtobelower.However,aquantitativeaccounting ofitisrequirednotonlytoassestheviabilityofFinFETtechnology,butalsoto analyze its impact on circuit performance. Unlikethegatetunnelingcurrentinbulk-Sidevices[Ran96],[Lo99], [Reg99],[Yan99],tunnelingcurrentinthedouble-gatestructurehasnotbeen analyzedmuch.Amongthefewpublishedworks,Chang[Cha02]gainedqualitative insightsonthegatetunnelingcurrentinDGdevicesusingnumericaltechniques,Hou etal. [Hou04]lookedatdifferentcomponentsoftunnelingcurrentinmetal-gateDG MOSFETs,andrecentlyMukhopadhyay etal. [Muk05]developedananalytical modelfortunnelingcurrentintheDGMOSFETtostudyitsimpactoncircuit performance.However,atunnelingcurrentmodelconsideringallthepossible

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151 tunnelingcomponentsinthepresent-dayDGtechnology,verifiedwithexperimental data,and,mostofall,compactenoughtobeusefulincircuitsimulationisstillabsent inliterature.Inthischapter,weattempttofillthevoidbydevelopingacompactyet physics-basedmodelforgatetunnelingcurrentforthegenericdouble-gate MOSFET,integratingitwithUFDG,andtheninvestigatingtheeffectsoftunneling leakage in nanoscale FinFET-CMOS performance. 6.2 Compact Model for Gate Tunneling Current in FinFET Ourapproachtowardsmodelingthegate-tunnelingcurrentisthatwe physicallymodelthemostimportanttunnelingcurrentcomponentinthebiasrange itisofconcern.Tolookatwhichbiasesthetunnelingcurrentneedscarefulattention inaCMOScircuit,inFigure6.1welookattheleakagecurrentcomponentsofan inverterwhenitslogicstatesare1atinputand0atoutput.Withthedrainnodeat zerobias,off-stateleakageofthepMOSFET(IOFF_p)isthedominantchannel currentanddefinesthecurrentflowingthroughthenMOSFETchannelaswell. Amongthecurrentflowingbetweenthegateandthesource/drain,thegateleakage currentofthenMOSFET(withVGS=VDD)isseveralordersofmagnitudehigher thanthatofthepMOSFET(withVGS=0).Hence,thetotalstaticpowerisduetothe IOFF(channelcurrentatVGS=0,andVDS=VDD)ofthepMOSFET,andtotalgateleakagecurrentIGatVGS=VDD,andVDS=0,ofthenMOSFET.Similarly,when thestatesare0attheinput,and1attheoutput,thetotalleakageismainlyduetothe IOFFofthenMOSFET,andIGatVGS=-VDD,andVDS=0ofthepMOSFET.That is,thegate-leakagecurrentthatimpactsthestaticleakagepowerforCMOScircuits isthehigh-VGS,low-VDSgate-tunnelingcurrent.Therefore,wemodelthegate-

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152 IGS_pIGD_pIOFF_n IG_p1 0Figure 6.1LeakagecurrentcomponentsinaCMOS-inverteratsteadystate.For logic1atinputand0atoutput,thetotalleakagecurrentisdefined bytheoff-stateleakageofthepMOSFETandgate-tunnelingcurrent ofthenMOSFET(thicklines).Forlogic0atinputand1atoutputthe totalleakagecurrentcomesfromtheoff-stateleakageofthe nMOSFET and gate-tunneling current of the pMOSFET (thin lines). MpdMpu VDDVGVDG G S S D IOFF_pIGD_nIGS_n IG_n0 1

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153 tunnelingleakageatVDS=0andVGS=VDDphysically,andfortheVDSdependence, whichisimportantfornumericalstability,adoptasemi-empirical/empirical approach.Also,asouremphasisisonVDS=0bias,wealsoassumeVBS=0,thusall thebiasesarereferencedtothesource.Inthenextsection,wefurtherminimizeour modelingcomplexitybyfindingoutthemostimportantcomponentofthegatetunneling current at high VGS, i.e., at inversion condition. 6.2.1 Tunneling Current Components Inatypicalbulk-Sidevice,thetunnelingcurrenthastwocomponents:the gate-channel/bodycurrent,andthegate-source/drainoverlap-regioncurrent.We alreadynoticedinChapter2thattheoverlapregionisnotpresentinnanoscale FinFETs;insteadtheyhavegate-source/drainunderlap.Hence,onlythegatechannel/bodytunnelingcurrentisimportantinFinFETs,andwewillfocusonthis componentoftunnelingcurrentinthischapter.FortheFDdevice,likeFinFET,the wordschannelandbodyhereareindicatingthesameSifilmbutintwodifferent operatingregion.Ininversionthefilmisreferredtoasthechannel,andin accumulationitisreferredtoasthebody.Thisisslightlydifferentfromthebulk-Si device,wherethechannelusuallyreferstotheinvertedpartoftheSibeneaththe gate-oxide,andbodyreferstothepartoftheSinearthesubstratewhichisnot depleted. Thegate-channel/bodytunnelingcurrentconsistsoftunnelingofcarriers toandfromtheconduction(Jc)andthevalence(Jv)bandsinSi.InFigure6.2,the tunnelingcurrent-densitycomponentsareshown:(i)conductionbandelectron

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154 qVGSEFSEFGECSEVS q fbc q fox ECOX |J1| |J2| |J3| |J4|Gate Oxide Channel q fbvEVOXJcJv Figure 6.2TunnelingcurrentcomponentsinannFinFETatinversion.Inthe figurethebarrierheights fbc, fbvandpotentialdropacrosstheoxide foxfarealsodefined.Emnistheenergybandwithmindicating conduction(C)valence(V),orFermi(F)levels,andnindicating siliconchannel(S),oxide(OX)orgate(G).Typicallythesilicon conductionbandtooxideconductionbandbarrierheight, fbc= 3.15V,andthesiliconvalencebandtooxidevalenceband, fbv= 4.5V [Hou02].

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155 tunnelingfromthechanneltothegate(J1),(ii)valencebandholetunnelingfromthe channeltothegate(J2),(iii)valencebandelectrontunnelingtothegate(J3),and(iv) electrontunnelingfromthegatetothechannel(J4).JcisthesumofJ1andJ4,while JvconsistsofJ2andJ3.Figure6.2isdrawnassumingametalgateelectrode,andour discussionthroughoutwillassumeametalgate.However,thedevelopedmodelcan beextendedforpolysilicongateaswell,eventhoughsuchgatemightnotbepartof theFinFETtechnology.Also,fortheoxidethicknessrangeweareconcernedwith (sub-2nm),allthetunnelingcurrentsareduetodirecttunneling,insteadofFowlerNordheim tunneling that is observed in MOS structures with thicker gate oxide. Thetunnelingcurrentdependsontheavailabilityofthecarrierstotunnel, availabilityofstatestotunnelto,andtheheightofthebarrierthatthetunneling carriersface.Basedonthat,andfollowingHoussimulations[Hou04],wecanfilter thelessdominantcomponentsoftunnelingindifferentoperatingregionsofthe metal-gateFinFETandsimplifythemodelingandcomputationaleffort.InFigure6.3 thedominantcomponentoftunnelingcurrentforbothn-andp-channelFinFETsin inversionandaccumulationisshown.Ininversion,thepositivegatebias,lowersthe gateFermilevelfromthechannelFermilevelbyqVGS,whichprohibitstunneling fromgatetoeitherthechannelconductionbandorvalenceband.Fortheformer,the gatedoesnothaveenoughelectronshavingenergyhighenoughtotunneltothe conductionband,andforthelatter,eventhoughithashighconcentrationofelectron availablefortunnelingtothevalenceband,therearenotenoughemptystatesinthe valencebandthatthoseelectronscantunnelto,orinotherwords,thereisnovalence bandholetunnelingtogate.Forsimilarreason,electronsfromtheSivalenceband

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156 J1 J2 J2 J1 EFGEFGEFGEFGEFSEFSEFSEFSECSEVSECSEVSECSECSECSEVS(a) (b) (i) Inversion (i) Accumulation (ii) Accumulation (i) Inversion Figure 6.3Dominanttunnelingcomponentinametal-gate,undoped(a) nFinFETand(b)pFinFETforbothinversionandaccumulation condition.

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157 cannottunneltothegateunlessthedeviceisdrivenbysuchbiasthattheEFGisbelow EVS,whichwillgivethevalencebandelectronemptystatesinthegatetotunnelto. Butfornormaloperatingconditions,wecanconcludethatforann-FinFETJ2,J3, and J4 are negligible in inversion, and the only dominant component is J1. Ataccumulation,thegateFermilevelispulledupbythegatebias, enablingholetunnelingfromthesiliconvalencebandtothefilledstatesinthegate (J2).IfthebiasishighenoughtopulltheEFGaboveECS,gatetobodyelectron tunnelingcanalsooccur;otherwiseJ4isnegligible.LackofelectronsintheSi conductionbandandlackofemptystatesinthemetallimitsJ1andJ3in accumulation. AsimilarreasoningwillshowthatforthepFinFETthedominant componentininversionisJ2,andinaccumulationitisJ1.Hence,wewillonlyfocus onmodelingofthecomponentsJ1andJ2only.InSIoneofthemisconsidered(J1for n-channel, J2 for p-channel), and in WI both of them are modeled. Atzerogateanddrainbiasallthefourcomponentscanceleachother,and theterminalcurrentbecomeszero.Thusconsiderationofonlytwocomponentswill leadtonon-zerocurrentsatzerogatebiasleadingtoconvergenceissues.Hence,the othertwocomponentsJ3,andJ4willalsobeaccountedforinthemodel,butina heuristic manner to avoid complexity. 6.2.2 Tunneling Current Model Thechannel-to-gatetunneling(J1orJ2)ismodeledbasedonsemiclassicaltheory,wheretheelectronisconsideredasawavepackettravelingwithin theclassicalturningpointsinthechannel,buttheeffectivemassapproximationis

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158 usedtosimplifytheelectroninteractionpicturewiththeenvironment.Thedeveloped modelis1Dandneglectsanyeffectofscatteringinsidetheoxide,aswellaspresence ofthetransitionlayerbetweentheoxideandsemiconductor[Kra01];i.e.,variation ofthepotentialenergyacrosstheSi/SiO2interfaceisassumedabrupt.Thecore formalismisthesameforboththeweakandstronginversion,butthecalculationof someparameters,likeeigenstate,isdifferent.FollowingthecoreUFDGformalism, moderateinversionismodeledusinga2Dspline[Tri05b].Thediscussionhereis aimedforn-channeldevices,howevertheformalismisvalidforp-channeldevices aswell,withneededchangesintheparametervaluesandsigns.Wedescribethe modelingforelectron(hole)tunnelingfromtheconduction(valence)bandtothegate forn-(p-)channelFinFETsatstronginversionfirst,andtheninweakinversion.Our discussionsinthissectionwillbeforsymmetricDGMOSFETsmainly.The additions/alterationsforasymmetricgateMOSFETswillbeaddressedinthe following section. 6.2.2.1 Channel-to-Gate Current in Strong Inversion Tomodeltheinversionlayer-to-gatetunnelingwewillutilizetheattempt toescapepictureoftunneling[Reg99].Theelectronwave-packetinthechannelcan beconsideredtobebouncingbackandforthbetweenthebarriers;underappliedfield theelectronmovesinthedirectionofthefielduntilitisreflectedbyonebarrier,then itmovesintheoppositedirectionandgetsreflectedbackagainbytheotherbarrier (Figure6.4).Everytimetheelectronimpingesonthebarrierithasaprobability,T, totunneloutofthechannel.Ifthetimebetweensuccessiveattemptstotunneloutis t then the tunneling current due to a sheet carrier density of N is

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159 etSitoxb+tSi-toxfEFGbEFGfEc(x) TijTij x 0 Ec(0)Figure 6.4T unnelingfromsemi-classicalpicture.Theelectronisbouncingbackand forthbetweenthebarriers.Ineverycollisionwithoneofthebarrierithas aprobability,Ttotunneloutofthechannel.Thetunnelingcurrentthus comesfromthemultiplicationofthenumberoftimesitimpingesonthe barrier,T,andtotalcarrierdensityinthechannel.The figurealsoshows thereferenceforpotentialanddistanceusedinthemodeldeveloped here.OriginisassumedtobeatSi/SiO2interfacenearthefrontgate. Also, all the potentials are measured with respect to Ec(0).

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160 .(6.1) Thesubscriptfisaddedtodenotefrontgate(thediscussionisvalidforthebackgate also),iandjareindexesforvalleysandsubbandsrespectively,andqisthecharge of an electron. The2DcarrierdensityNisobtainedbyintegrating2Ddensityofstates, withtheFermi-Diracdistributionoveralltransverseenergiesandisgivenas[Tau98] ,(6.2) wheregvisthevalleydegeneracy,mDisthedensity-of-stateeffectivemassof electron,hisPlanksconstant,kisBoltzmansconstant,Tisthetemperaturein Kelvin,Eistheeigenenergyofelectrons,andEFSistheFermilevelinthechannel (Figure6.2).Thelatterenergiesaremeasuredfromtheconductionbandedgeatthe Si/Si02 interface, i.e., from Ec(0). ThetunnelingprobabilityTcanbeexpressedbyusingtheWKBmethod [Sha94]: .(6.3) Here kxistheelectronwavevectorinsidetheoxidebarrierinthexdirectionandtoxfisthethicknessofthebarrier.Ifthedispersionrelationintheoxideisassumedtobe parabolic [Yan04], kx then becomesJ 1fqN ij t ij ----------T ij ij= Nij4 pkTh2-------------gvimDi1 EFSEij kT ----------------------exp + ln = Tij2kxij xd0 toxf exp =

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161 ,(6.4) withmoxbeingelectroneffectivemassinsidethebarrier,andEcoxistheoxide conductionbandenergyatanyx.Plugging(6.4)in(6.3)andperformingthe integration,wefindTasafunctionofpotentialdropintheoxide, foxf(Figure6.2),as,(6.5) wherewedefinedEcox(Figure6.2)relativetotheconductionbandedgeofthe channel at the Si/SiO2 interface: .(6.6) Notethatfrom(6.5),ifthecarriershaveheaviermassinsidethebarrier, orifthebarrieristhicker,orifitsheightishigher,thetunnelingprobabilityis exponentiallylower.Thegatebias(VGfS)dependenceofthetunnelingprobability comes from the foxfwhich depends on VGfS as ,(6.7) where fsfisthefrontsurfacepotentialand FMSisthemetal-Siworkfunction difference.In(6.7),weassumedoxidechargesarenegligible.TheUFDGcore formalismsolvesfor fsf[Chi01],andEij[Ge02a],andhencetogetthetunneling kxij ,8 p2moxh2-----------------EcoxEij () = Tij4 toxf3 q ----------8 moxp2h2------------------ q jbcEij ()3 2 --q jbcEij q joxf ()3 2 -- joxf----------------------------------------------------------------------------------------exp= Ecoxq jbcq joxftoxf------------x = joxfVGfSFMS jsf =

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162 probabilityinUFDGweonlyhavetosupplythebarrierproperties( fbcandmox)in (6.5). Exactcalculationoftheattemptfrequency(/ t in(6.1))thatmeasures howmanytimestheelectronisattemptingtoescapefromtheinversionlayeris nontrivial.However,withsomekeyassumptionswecanhaveasimplifiedexpression for1/ t fornanoscaleFinFETs.Thepathtime t [Pri92]itselfmeasuresthetimethe electronrequirestotraverseonceineachdirectionwithoutescaping.Foranelectron in a particular subband, t can be expressed as [Ran96] ,(6.8) wherev(x)isthevelocityofthecarriersinthatsubbandandxijisthedistance betweenthetwoclassicalturningpoints(withoneatx=0,theSi/SiO2interface)in thewellforastatejini-thvalley.(Note:classicalturningpointisdefinedasthe pointinxwhereEij=Ec(x)[Sha94].)FornanoscaleFinFETs,assumingelectronsare bouncingbackandforthbetweenthetwooxideboundariestSiapart,withanaverage velocity , we can approximate t as.(6.9) TheassumptionoftSiasthedistancebetweentwoclassicalturningpoints in(6.9)isexactforSDGFinFETsoperatingintheweakinversion.However,in stronginversionthepotentialinthechannelisparabolic,andcreatestwoseparate wellswiththetwooxidebarriers.Thusin(6.9),forsuchcases,andespeciallyforthetij2 1 vijx () ------------xd0 xij= tij2 tSiv ij----------=

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163 lower-energystates,separationoftheclassicalturningpointsisexaggerated.In Figure6.5,SCHRED[Vas00]-predictedconductionbandprofile,andlowest eigenenergyinthechannelareshown,aswellastheclassicalturningpointinthe channelforelectronwithenergyE11,illustratingthefactthatxijcouldbelessthan tSi.Propermodelingofxijisthusneeded,butitrequiresknowledgeofEc(x),exact calculation of which is impractical in a compact model. However,nearthebarrierwecanassumeEc( x )islinearin x (Figure6.5) and write as ,(6.10) where efsisthefrontsurfaceelectricfield,whichforSDGisrelatedtothetotal inversion charge Qias (Gausss law), .(6.11) Thefactorin(6.11)comesfromthesymmetryoftheSDGstructure,andthe electricfieldispositiveasQiisnegativeforthen-channeldevice.In(6.11),wehave neglectedthedepletioncharge,assumingthatcomparedtotheinversioncarrier concentration,theionizedimpurityconcentrationisnotthatsignificantasFinFETs arenotdopedintentionally.Forasymmetricdevices,thefactorshouldbe replacedby h ,thechargepartitioningfactorbetweenthetwogates,asdescribedin [Ge02a],valuesofwhichvaryas0 h 1.Using(6.11)in(6.10),andapplyingthe classical turning point condition Eij = Ec(x), we get E cx () Ec0 () q efs x = efsQi2 eSi--------- =

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164 -5.00.05.010.015.0 Depth in x-direction (nm) -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0Energy (eV) Ec(x) E11 model Ec(x) x11FGChannelBGFigure 6.5SCHRED-simulatedconductionbandprofileforamid-gapgate undopedsymmetricDGFETat1.2Vgatebias.Firstsubbandforthe lowervalley,aswellastheclassicalturningpointwhereE11=Ec(x) arealsoshown.ThemodeledEc(x),whichisapproximatedasalinear potential to facilitate xij calculation, is shown in dashed lines.

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165 .(6.12) NotethatfortheSDGFinFET,anypredictionofxijby(6.12)withintSi/2 xij tSishouldbesmoothedtotSi,asxij>tSi/2in(6.12)indicatesEijisgreaterthan themaximumofEc(x),whichisattSi/2forSDGdevices,andhencethetwoclassical turningpointsareatthetwobarriers.Tocapturethisphysicalpicture,inUFDG implementation,wesmoothxijobtainedfrom(6.12)suchthatforxij>tSi/2in(6.12), itissetequaltotSi.InFigure6.6,x11predictedbyabovemodelforanSDGFinFET iscomparedwiththatofSCHREDfortwodifferentfinthicknesses,tSi=10nmand 20nm.TheModelpredictionisreasonablyclosetothatofSCHRED.The underestimationofx11bythemodelisduetotheassumptionofthelinearpotential in(6.12),whichtendstoconfinetheelectronmoredoesaparabolic-likeEc(x)(the actual potential in the channel as in, Figure 6.5). Withxijmodeledby(6.12),forthedeviceoperatinginstronginversion, (6.8) can be written as .(6.13) The average velocity can be found from [Sha94] ,(6.14) xij2 eSiEijqQi---------------- =tij2 xijv ij----------=v y | v y | yy | -----------------=

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166 Figure 6.6Comparisonofdistancebetweenclassicalturningpointsinstrong inversionforelectronsinthegroundstateaspredictedbythemodel with that of SCHREDs for an SDG FinFET with toxf= toxb= 1nm. 0.800.901.001.101.20 VGS (V) 0.10 0.20 0.30 0.40 0.50X11/tSi SCHRED, tSi = 10nm SCHRED, tSi = 20nm UFDG, tSi = 10nm UFDG, tSi = 20nm

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167 where y istheelectronwavefunctioninsidethechannel.Replacingvwithp/mx, withpbeingthemomentumoperatorandmxistheconfinementmassofthecarriers, we get from the above equation, after applying, .(6.15) ForaFinFET,theelectronwavefunctioninsidethechannelboundedby two barriers is essentially a standing wave and can be expressed as [Ge02a] ,(6.16) whereaisthenormalizationconstantandbisthevariationalparameter. Neglectingwavefunctionpenetrationinsidetheoxideforasubbandj,aandbare found as [Ge02a] (6.17) and .(6.18) In(6.18),Qd=-qNAtSi,thedepletioncharge,and,thetotalinversionchargedensity.Notethatthroughb,thesecondpartofthe(6.16)(within pi h 2 p -----x d d = v i h 2 p mx------------y*x d d y x d y*y x d------------------------------------------= yijaij2 ----2 tSi----j 1 + ()p x tSi---------------------b ijx tSi----------exp bij () bijx tSi-------exp exp + sin = aij22 bj () j 1 + ()p []212 bj () exp () bjbj 2j 1 + ()p []2+ [] ------------------------------------------------------------------+ exp1 2 -----= bjtSiqmxip2Qd5 6 -Qi+ j 1 + ()eSih2-----------------------------------------------1 3 --@ QiqNij =

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168 parenthesis)isbias-dependentandmodulatesthefreeelectronstandingwave expressed by the first part. Thestandingwavein(6.16)canalsobeexpressedasthesumoftwo oppositelymovingwaves, y+an y-byfactoringthesinefunction;forexamplethe component traveling in the -x direction can be written as.(6.19) Component y-(or y+)travelswiththesame(butintheoppositedirection)velocity vthatrepresentsthevelocityofelectronintheconfinementdirectionatthatstate. So, to get , using either yor y+ in (6.15) we find.(6.20)Thelimitsoftheintegrationin(6.15)shouldbe(0,xij);howeverin deriving(6.20),weused(0,tSi).Theassumptionhereisthatthecontributionfrom thewavefunctioninsidethebarrierinthechannel(i.e.,whereEc(x)>Eij)in(6.15) isnegligiblecomparedtothatwithin(0,xij).InFigure6.7,theaveragevelocity predictedby(6.20)isplottedasafunctionofbiasforanelectroninthegroundstate ofanSDGFinFETfortwodifferentfinthicknesses.Forthethinnerfilm,thevelocity islesssensitivetobias,indicatingstrongerstructuralquantization(comparedtofield quantization).Indeedforthinfilm,bin(6.20) 0,andbecomesthevelocity of an electron in the respective state in an infinite potential well. yij -1 2 i ----aij2 ----2 tSi----i () j 1 + ()p x tSi-------------------------------exp b ijx tSi----------exp bij () bijx tSi-------exp exp + = v ijj 1 + () haij 232 mxitSi---------------------------1 bij----1 bij----2 bij () 22 bij () exp + exp =

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169 Figure 6.7Variationofground-stateelectronvelocitywithbiasinstrong inversionofanSDGFinFEThavingamid-gapgateandtoxf=toxb= 1nm.ForthinnertSi,thelowerbiaspointsareinthemoderate inversionregion,whereUFDGstronginversionsolutionmaynotbe accurate, and should be interpreted as such.VGS (V)Average Velocity (x107 cm/s) 0.70.80.91.01.11.2 1.0 1.5 2.0 2.5 3.0 3.5 tSi=5nm tSi=10nm

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170 Theexpressionforattemptfrequencyin(6.13),with(6.20),now becomes .(6.21) Thusallthecomponentsin(6.1)aredefinedby(6.2),(6.5),and(6.21),facilitating calculationofJ1instronginversion.ThederivationofthedominantcomponentJ1describedhereisphysics-basedbuthasonetuningparameter,i.e.,theeffectivemass ofcarriersintheoxide(orsimply,thetunnelmass),moxin(6.5).Before implementingthemodelinUFDG,inthenextfewsectionswewillsimplifythe modelforweakinversion,addaccountingofothernegligiblecomponentsthatare requiredfornumericalstability,anddiscussthemodelmodificationsforasymmetric structures. 6.2.2.2 Channel-to-Gate Current in Weak Inversion Eventhoughthestrong-inversionformalismdevelopedaboveisgeneric enoughtobeapplicableinweakinversion,wewillsimplifythemodelfurtherfor efficiency.Thetunnelingprobabilityisstillgovernedbythesame(6.4),butthe2D carrierdensityin(6.2)andattemptfrequencyin(6.21)canbesimplified.Toobtain theexpressionfor/ t ,weexpressthevelocityin(6.8)intermsofkineticenergy and re-write as.(6.22) 1tij---j 1 + () haij 264 mxixijtSi---------------------------1 bij----1 bij----2 bij () 22 bij () exp + exp = tij22 EijEcx () () mxi------------------------------1 2 -- xd0 xij=

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171 ForundopedsymmetricDGFinFETsorsingle-gateFDSOIdevices,theelectricfield inthechannelislow,andEc(x)=Ec(0).However,forasymmetric-gatedevicesa linearpotentialgradientduetothegateasymmetryisdevelopedinthechannel resultinginanelectricfieldEx1D,asshownin[Ge02a],and[Tri05b],andisgivenas ,(6.23) whereVGbSisthebackgatebiasandVFBf/bistheflatbandvoltageoffront/back gate.NotethatforthesymmetricFinFET(i.e.,VGfS=VGbS,VFBf=VFBb),Ex1D= 0;aswellasfortheFDSOIdeviceswhereusuallytoxbisthick,andEx1D@ 0. ReplacingEc(x)withEc(0)-qEx1Dxin(6.22),andperformingtheintegration,we find .(6.24) AsEx1D 0,thewellresemblesasquarepotentialwell,andxij tSi;in such case using the square-well eigenenergy expression [Sha94], ,(6.25) we find from (6.24) the expression of t for SDG FinFET or FDSOI devices as .(6.26) Ex 1 DVGfSVGbS () VFBfVFBb () eSieox () toxftoxb+ () tSi+ ---------------------------------------------------------------------------=tij8 mxiEijEijqEx 1 Dxij qEx 1 D-------------------------------------------------------= Eijj 1 + ()2h28 mxitSi 2-----------------= tijtSi2 mxiEij----------hj 1 + () 2 Eij-------------------==

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172 Equation(6.26)isusedin[Reg99],and[Yan99]asanapproximationforcarrier-path timeinbulk-SiMOSFETsinalloperatingregions;howeverweonlyuse(6.26)in weakinversion,whereitismoreappropriate.With t definedin(6.26),theweakinversiontunnelingcurrentiscalculatedby(6.1)alongwith(6.2),(6.5),and(6.26). 6.2.2.3 Gate-to-Conduction Band Tunneling Asmentionedearlier,eventhoughthedominantcomponentininversion isJ1,notconsideringtheothercomponentscanleadtononzerocurrentatzerogate biascausingnumericalinstability.Hence,inthissectionwedescribeasimple accounting of J4 (Figure 6.2), the inverse of J1. Inmetal,carriersare3Dandtunnelingfrommetalcouldbeexpressedas [Zeg04] ,(6.27) whereN3Disthecarrierconcentrationinthemetal,vRistheRichardsonvelocityat whichcarrierimpingesonthebarrier,andTisthetunnelingprobabilitygivenin (6.5).However,iftrap/phonon-assistedtunnelingisneglected,onlyafewofthese carriersthatcanconservethetransversemomentumwillparticipateinthetunneling [Gra65],whichintroducescomplexityinthemodeling.Here,weavoiddetail accountingofJ4,andinsteadwemodelJ4byusingalreadymodeledJ1,andassuming that the total conduction band tunneling (Jc) is zero when gate bias is zero; i.e., .(6.28) Thesignsofthecomponentsin(6.28)aredeterminedbytheconvention thatcurrententeringinanode(gate)ispositive.WhenthegatebiasVGSisnonzero, J4N3 DvRT = JcVGS() J1J4 ==

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173 itseparatesthetwoFermilevels,andweassumethedifferenceinJ1andJ4then comesonlyfromthedifferenceinthecarrierdensitiesgivenby(6.2),inthe respective materials. In terms of J1, J4 then can be expressed as ;(6.29) or Jc, using N, T, and t from (6.2), (6.5), and (6.21), respectively, is .(6.30) From(6.30),whenVGS=0,Jcisappropriatelyzero;whenVGS<0,Jc<0andfor VGS>0,Jc=J1>0.ThusasimpleaccountingofJ4allowsustoavoidnumerical instabilitieswithoutintroducingmuchcomplexitiesinthemodel.However,asJ4is negligibleinstronginversion,duringmodelimplementation,onlyJ1(asmodeledin Section6.2.2.1)isconsideredin(6.28),butinweakinversion,bothJ4andJ1is considered and (6.30) defines the weak-inversion Jc. 6.2.2.4 Tunneling in Weak Accumulation Intheaccumulationregion,tunnelingoftheminoritycarriersbecomes dominantasshowninFigure6.3.ThecalculationofcomponentJ2,andtotal tunnelingtoandfromthevalenceband,Jv,isthesameasJ1andJcdescribedabove, exceptforthevaluesofbarrierheightsandeffectivemasses;theunprimedand primed valleys for Jc becomes heavyand light-hole valleys for Jv. J4J1NijEFSqVGS () NijEFS() ----------------------------------------= Jc4 pkTh2-------------gvim iTijtij-----1EFSEij kT ---------------------exp + 1EFSqVGSEijkT --------------------------------------------exp + -------------------------------------------------------------lnij=

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174 InUFDGthereisnoexplicitsolutionforpotentialsandchargesinthe accumulationregion.Inweakaccumulation,theUFDGweak-inversionmodelis valid,andhencethegatetunnelingcurrent,describedabove,isapplicableinweak accumulationaswell.However,foradeviceoperatinginstrongaccumulation (unlikelyindigitalcircuits),thegatecurrentformalismpresentedhereisnot applicable. 6.2.3 Tunneling in Asymmetric-Gate Devices SofarweonlyconsideredSDGMOSFET,thetotaltunnelingcurrentof whichcomesequallyfromthetwogates.Thefront/backgate-tunnelingcurrent JGf/bofSDGFinFETisdefinedby(Jc+Jv)inweakinversion/accumulation(with Jc/vgivenby(6.30)withappropriatesignandvaluesoftheparameterforelectrons/ holes),andbyJc@ J1instronginversion.However,tomaintainthegenericnatureof UFDG,weneedtoconsiderallpragmaticvariationofFinFETs,i.e.,bothSDGand ADG FinFET. Aftertheearlyexploratorywork,theasymmetricdouble-gate(ADG) MOSFETsthatusetwodifferentgatematerials(n+-,p+-poly)losttheirappealdue tothelessreturnoninvestmentintermsoffabricationcomplexityandadvantages overSDGs.However,withtheadventoftheMIGFET[Leo04],whereasymmetryis introducedbyusingdifferentbiasesonthetwogatesratherthanbychangingthegate materialsthemselves,theADGMOSFETisincontentionagain,especiallyfor analogapplications.Hence,afewmodificationsaredoneinthepresentedgate currentformalismforMIGFETs,mainlyfortunnelingtothesecondgate(backgate),

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175 i.e.,JGb.Wewillassumethefrontgateisthepredominantgate,thetunnelingcurrent to which can be calculated using the formalism described in previous sections. InFigure6.8,the conductionbanddiagraminaMIGFETwherebothgatesare biasedinweakinversionisshown.ThetunnelingfromastatewithenergyEijthroughthe backgatecanbethoughtofasatwostepprocess.Firstthecarrierstunnelthroughthe triangularbarrierofheight Dc(=qEx1D(tSi-xij))withprobabilityTc,andthentunnel throughthesecondgateoxidebarrierwithaprobabilityTB.Thetotaltunnelingprobability isTcTB.Integrationof(6.3)forTc(within(xij,tSi-xij))willrevealtheFowler-Nordheim tunnelingprobability,andTBislikethatin(6.5)withthebarrierheightincreasedby DB. WithNijdenedin(6.22)and t in(6.25),thetunnelingcurrentthroughthebackgateoxide then can be calculated using (6.1). Whiletheaboveapproachisexact,ithassomeissuesregarding implementationinacompactmodel:(i)forEij>qEx1DtSi, Dcrequiresasmoothingfunction tolimititsvaluetoqEx1DtSi,(ii)forEx1D<0,i.e.,whenthebackgateisthepredominant gatetherespectivecalculationforthefrontandbackgateneedstobeswapped.Hence,we choseanalternative,simplerapproach,realizingthatthetunnelingcurrentdensity,J N, T,andexpressingtunnelingthroughthebackgateintermsofthetunnelingcurrentthrough the front gate, JGf (= Jc + Jv), ,(6.31) whereNb/fisthecarrierconcentrationinthefront/backchannel.Theimplicit assumptionin(6.31)isthechargesheetapproximationthatassumesallthecharges JGbJGfNbTbNfTf------------=

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176 Figure 6.8SchematicofvariationofEc(x)inweakinversioninaMIGFETwhere both the gates are biased independently. Ec(x) tSitoxb+tSi-toxf x 0 xij DBDcFG BG fbcEij TC Tb Tf

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177 arenearthesurfaces,whichisnotaccurateinUTBdevices,especiallyinweak inversion.However,asthecurrentthroughthebackgateisfewordersofmagnitude lowerthanthatthroughthefrontgate,errorintroducedby(6.31)doesnoteffect deviceperformanceprojections.UsingMaxwell-Boltzmanstatistics,wecanre-write (6.31) in weak inversion as ,(6.32) where fsf/bisthefront/backsurfacepotential.Instronginversion,(6.31)canbe written in terms of h [ Ge02a] as .(6.33) ForSDGFinFETs, fsf= fsb,and h =1,andhenceJGb=JGfinboth(6.32) and(6.33).With(6.32)and(6.33)definingthebackgatecurrentinasymmetric devices,ourmodelingoftunnelingcurrentinaFinFETiscompleteforboth symmetric and asymmetric devices. The total tunneling current density is, .(6.34) InasymmetricFinFET,theback-gatecurrentisequaltothefrontgatecurrent,and JG=2JGf.InFDSOIdevices,wheretoxbisthick,Tb 0in(6.5),andthusJGb 0, andtotalcurrentcomesfromthefront-gatetunneling.Fortypicalasymmetric devices, JGb << JGf (will be shown later) and JG ~ JGf. JGbJGfTbTf-----q jSbjSf () kT -----------------------------exp = JGbJGfh TbTf--------= JGJGfJ +Gb=

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178 6.2.4 Drain Bias Dependence of Tunneling Current 6.2.4.1 Drain-Induced Reduction of Gate Current The1DmodeldevelopedheresofarneglectsanyeffectofdrainbiasVDS, asmainlyIGatVDS=0contributestotheCMOSstaticpower(Figure6.1).However, asmentionedearlier,IG(VDS> 0)needsconsiderationincompactmodelsfor numericalstability.WiththeapplicationofVDS,thepotentialalongthechannel, fromthesourcetothedrain,increases,andhencethepotentialdifferencebetween thegateandsomepoint,yinthechanneldecreasesalongthechannel,whichreduces the tunneling current density, JG(y). The IG(VDS) is then found as [Gu04] ,(6.35) where W is the width of the device, Lg is the physical gate length, and (6.36) definesJG(y),with f (y)beingthepotentialinthechannelandisafunctionofVDS. Inweakinversion, f (y)couldbefoundfromUFDGcoreformalism,asdiscussedin Chapter3.Thevariationof f inthechannelwithVDS,variesQi(y)and foxf/b(y).The variationof foxf/bmodulatesTin(6.5).However,foratypicalrangeof foxf/b,Tis relativelylesssensitiveon foxf/bandthereductioninIGcomesfromthereductionof Qi along the channel from source to drain. Basedontheaboveinsight,insteadofcalculating(6.35)exactly,we developasimplemodeltoaccountforthereductionofIGwithdrainbias.We IGWJGVy () () y d0 Lg= Vy () VGSj y () =

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179 assume,thequantizationeffects(Eij,Qi, tij,etc.)arethesamealongthechannel, independentofthedrainbias.Suchassumptionmaynotbevalid,aswithVDS>0, electronenergyincreasesalongthechannel,andthusconfinementeffectsshould lessen.However,suchassumptionwillonlyoverpredictthetunnelingcurrent, increasingmarginofsafetyofourmodelpredictions.Thusacceptingthispessimistic assumption,alltheeffectsofdrainbiasarelumpedasmodulationofcarrier concentration in (6.30), which is re-written as .(6.37) Atthedrainend,theFermilevelisloweredbydrainbias; a VDSin(6.37)thus representsaverageloweringofFermilevelinthechannel.NowJcin(6.37) representstheaveragetunnelingcurrentfromthechannelthatgivestunneling current in inversion region as .(6.38) Theparameterain(6.37)iskeptasfittingparameter,thevalueofwhichshouldbe within 0 a 1. WhileJcin(6.37)isapplicableinstronginversion,theavailabilityofa detailedsolutionofchargesinlinearandsaturationregionsinSIinUFDG[Chi01] allowsustodevelopamorephysicalmodeltoaccountforthereductionofIG(VDS) inSI.Besides,forshort-channeldevices,velocitysaturationnearthedrainendwill Jc4 pkTh2-------------g vi m iTijtij-----1E FSqaVDSE ijkT ---------------------------------------------------exp + 1E FSqVGSE ijkT -----------------------------------------------exp + -------------------------------------------------------------------lnij= IGfWLgJc=

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180 complicateextractionofain(6.37)asauniquevalue,independentofVDS.Withthe applicationofdrainbias,thestrong-inversioncarrierdensitiessaturatesnearthe drainasvelocitysaturationoccurs[Tau98].Thereductionofgatecurrentthencan be accounted for as ,(6.39) whereistheaveragechargedensityinthelinearregion(FigureA.4),andis assumedtobeequaltotheinversion-chargedensityQiatvirtualsourceasin(6.18); Qsatisthesaturation-chargedensitygivenin[Chi01],Leisthelengthofthelinear regioninthechannel,andLg-Leisthelengthofthevelocity-saturatedregion [Chi01].TypicallyQsatVdsat)
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181 issharedbythesourceanddrain,andexpresseddrainandsourcecomponentofthe tunneling current as (6.40) and ,(6.41) respectively.Lackofknowledgeofexact f (y)instronginversionpreventsusfrom accountingthecurrentpartitioningbyperformingtheaboveintegrations,andhence weadoptanempiricalpartitioningschemebasedontheworkofGu etal. [Gu04]. The gate current is partitioned as, ,(6.42) ,(6.43) where b is defined by a smoothing function: ,(6.44) with b0 being IGDW Lg----yJGVy () () y d0 Lg= IGSW 1 y Lg----- JGVy () () y d0 Lg= IGSb IG= IGD1 b () IG= bb0b00.5 () 1 4 VDSVGSkT q -----+ -------------------------+ ----------------------------------- =

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182 .(6.45) For bmax=0.83and bmin=0.3,thepredictionof(6.44)iscomparedinFigure6.9 withthatofalongbulk-SiMOSFET,aspredictedin[Gu04].Whenthedrainbiasiszero, thegatecurrentissharedequallybyboththesourceandthedrain.However,asVDSincreases,mostofthegatecurrentgoesthroughthesourcenode.AthighVDS,inPDSOI technology, b isobservedtobe~0.71.Asgateleakagedataasafunctionofdrainbiasis lacking,wehard-wiredtheabovevaluesof bmax,and bmininUFDG,theygive b inthe same range as that for the bulk-Si or PD/SOI devices. 6.3 Model Implementation and Verification Withtheincorporationofdrainbiasdependence,thegatecurrentmodelis complete,andisimplementedinUFDGthroughsixcurrentsources,threefromeach gate:gatetosource(IGf/bS),gatetodrain(IGf/bD),andgatetobody(IGf/bB).The formertwoaredefinedin(6.42)and(6.43),respectively,withIGreplacedbyIGfor IGb,andIGf/bBissettozero.WhileinthePDSOItechnology,duetothefloatingbodyeffects,theusuallynegligibleIGbneedstobemodeled[Yan04],inFDdevices liketheFinFET,lackoffloating-bodyeffectsallowustoignorethiscomponent completely.ThenetworkrepresentationofUFDGafterincludingthegatecurrent model is shown in Figure 6.10. Akeyissueregardingtheimplementationofthemodelistodetermine howmanysubbandstoconsiderfortunnelingcurrentcalculationin(6.1).Forbulk1. Chip Workman, private communication Freescale Semiconductor, 2004.b0bmaxbmin12 VGS+ ------------------------- =

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183 Figure 6.9VariationofIGS/IGwithdrainbias,aspredictedbytheempirical relationin(6.44).AlsoshownIGS/IGofa10 m mlongbulk-Si MOSFET as predicted in [Gu04]. 0.00.20.40.60.81.01.2 0.50 0.60 0.70 b = IGS/IGVDS(V) VGS = 1.0V

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184 Figure 6.10UpdatedUFDGnetworkdiagramshowingthecurrentsources accountingforgateleakagecurrent.IGfS/IGbSisgivenby(6.42)and IGfS/IGbDby(6.43),whileIGbB=IGfB=0.(Foradescriptionofthe other current sources see [Fos05].) ICHIBJT -IRGt(VBD) IRGt(VBS) D S BGf GbBD SIGi RSRB dQGf/dt dQD/dt dQS/dt dQB/dt dQGb/dt RD IGfSIGfDIGbSIGbD IGfB IGbB (w/ IGIDL)

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185 SiMOSFETs,onlythelowestsubbandisusuallyconsidered.Toresolvethisissue wedidnumericalsimulationsoftunnelingcurrentinSDGFinFET.Thesolutionof potentialfromtheSchrdinger-PoissonsolverSCHRED[Vas00]wasfedtoapost processorthatsolvesSEwithopenboundarycondition[Ala02].Thusthewave functionpenetrationeffectsintotheoxideisincludedintheSEsolution,which broadenstheDOSfromadeltafunctiontoaLorentzian.ThewidthoftheLorentzian givesthecarrierlifetime( t /T),andcurrentisthencalculatedfollowing(6.1).In Figure6.11,we showboththepopulationfactor,i.e,carrierconcentrationfractionin eachsubband,andthecontributiontogatecurrentfromeachsubbandforvarying gatebias.Asevident,unlikeinthebulk-SiMOSFET,twosubbandsfromeach ladder/valleycontributesignificantlytowardsthetotalcarrierpopulation.The pictureismoreinterestingforthetotaltunnelingcurrent,wherethecontribution fromtheuppersubbandsthathavelesscarrierscomparedtothelowersubbandsis quitesignificant,andinfactcouldbemorethanthatoflowersubbands.The explanationliesinthecarrierlifetime,whichissmallerfortheuppersubbandsasthe carriers have higher energy and face a lower tunneling barrier. Whileinstronginversionconsiderationoftwolowestsubbandsfromeach valleyisaccurateenough,inweak-inversionthreesubbandsfrombothvalleysmake non-negligiblecontributiontothetotalcurrents.However,toreducecomplexityand UFDGcomputationaltime,weaccountforonlytwosubbandsfromeachvalleyin both the weakand strong-inversion regions. Theimplementationofthemodeladdsthreenewmodelparametersto UFDG: IGATE MOX ,and DREFF .Parameter IGATE issimplyaflagthatturns

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186 Figure 6.11SignificanceofthehighersubbandsinFinFETs.Figureshows variationoffractional(a)carrierpopulation(populationfactor)and (b)tunnelingcurrentfromthreelowestunprimed/primed(open/solid symbols)subbandswithgatebiasinanundoped{110}-Sisurface mid-gapgateSDGnFinFET;tox=1nm,andtSi=10nm.Thesimulator is developed following [Ala02]. Gate Voltage (V)Nij/ S Nij 0.00.10.20.30.40.50.6 0.70.80.91.01.11.2 0.0 0.1 0.2 0.3 0.4 0.5 0.6 11 12 13 0.00.10.20.30.40.50.60.70.80.91.01.11.2 0.0 0.1 0.2 0.3 0.4 Gate Voltage (V)Jij/ S Jij ij 21 22 23 11 12 13 ij 21 22 23 (a) (b)

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187 onthegateleakagemodel; MOX definesthemassofthetunnelingcarriersinthe oxide;itistheratioofmox(in(6.5))andmo(freeelectronmass),andcanbetuned. And, DREFF istheain(6.37)thatallowsfinetuningofthedrainbiasdependence ofgatetunnelingcurrentinweakinversion.NotethatinCMOScircuits,theworstcasescenarioregardingtheeffectsofgateleakageiswhenVDS=0andVGS=VDD. Forexample,inaNANDgate,thegateleakageishighestwhentheinputis(0,1) [Muk05],i.e,VGS=0forthetopnMOSFETandVGS=VDDforthebottomone.In suchcases,thegateleakageinthetopdevice,isfewordersofmagnitudelowerthan thatinthebottomone,whichisinstronginversionandhasVDS=0.ThusUFDG predictionsforworst-casegateleakageincircuitswillbeunaffectedbythechoiceof DREFF InFigure6.12 model-predictedgatetunnelingcurrentdensity(pergate area)iscomparedwiththatofexperimentaldatafortwodifferentoxidethickness. ThegateoxideinboththedevicesisSiON;forthethicker-oxide(17)device [Yu02],measurementsweredoneona10 m mx10 m mSDGFinFET,howeverforthe thinner-oxide(14)device[Fer06]measurementsarefroma165nmx60nmFinFET. Hence,thereissomeuncertaintyinthereportedoxidethicknessforthelatter,asit maynotbeextractedfromthesameshorter-channellengthdevice;asoxidethickness extractionisdonefromC-Vmeasurementsthatrequiresextremelylong-andwidechanneldevices.Also,17isthephysicaloxidethicknessoftheSiONdielectric [Yu02],andforthe14device,thethicknessisreportedastheequivalentoxide thickness,EOT[Fer06].EOTisdefinedas3.9tox/k,wherekisthedielectricconstant ofthedielectric,andtoxisthephysicaloxidethickness.ForFinFETtechnology,the

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188 Figure 6.12ComparisonofUFDGgateleakagemodelspredictionwith experimentaldata.The17dataistakenfrom[Yu02]andthe14one from [Fer06]. The oxide in both the devices is SiON. VGS(V) 17 14 toxf = toxb 0.00.20.40.60.81.01.21.4 10-610-510-410-310-210-1100101102103 Experimental Data UFDG (MOX = 0.7)JG (A/cm2)

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189 nitrogenconcentrationinSiONislow,usually<10%1,andthusk~3.9;hencein our simulation for both the cases we use EOT @ tox. Withmoxtunedto0.7mo,theUFDG-predictedgateleakageiswellin agreementwiththedata,exceptforverylowgatebiases.Theunderestimationofthe gatecurrentnearzerogatebiasmaypossiblybeduetotherathersimplistic accountingofJ4inJcin(6.37),and/orduetoneglectoftrap-assistedtunneling.The goodmatchobtained(forVGS>0.2),withouttuninganyothermodelparameter exceptmox,illustratesthereasonablephysicalbasisofthemodel.Inexisting tunnelingcurrentmodels,likethatin[Hou04],theagreementwithdataisusually goodforVGS>1V[Hou04];i.e.,fortypicalCMOSoperatingbiasrange(0-1.2V, [ITR03]),predictionsofthosemodelsarenotaccurate.Onthecontrary,thestrength ofourmodelliesinthefactthatitshowsgoodagreementwithdatafornormal operating biases. Whilethemoxobtainedlieswithintherangeoftunnelmassreportedinthe literature(0.25mo-0.9mo,[St]),theindependenceoftheextractedmoxontoxcontradictswithatomistictight-bindingcalculationsofSiO2,whereitisfoundthat moxincreaseswithdecreasingoxidethickness[St].Theconstantmoxextracted fromourmodelcouldwellbeduetotheassumptionsinthemodel(e.g.,usingthe effectivemassapproximation,neglectingreflectionfromboundaries,etc.)orthe uncertaintyinthemeasuredoxidethicknesses.However,useoftheextractedmoxin performancepredictionofFinFETswiththinneroxideswillbepessimisticratherthat optimistic, as use of lighter mox will over predict gate leakage current (see (6.5)). 1. L. Mathew, private communication Freescale Semiconductor Inc, 2005.

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190 Theeffectofvariationofmodelparameter DREFF isshownin Figure 6.13,fora short-channelFinFET(Lg=18nm,liketheFinFETstudiedinChapter5). Inweakinversion, DREFF modulatesgatecurrentsignificantly,butastheeffectof drainbiasistakencareofmorephysicallyinstronginversion,choiceof DREFF doesnotalterthemodelpredictionsthere.InUFDG,thedefaultvalueof DREFF is setto0.1,basedontheobservationofsomeleakagedatathroughstressedoxide, whereitisfoundthattheminimumpointofthe|IG|-VGcurveshifts~0.1Vathigh VDS.Uponavailabilityofgateleakagedataoffreshoxides,atdifferentdrainbiases, the value of DREFF could be further refined. InFigure6.14, model-predictedgatetunnelingcurrentforbothADGand SDGFinFETsareshown.Duetohighertransverseelectricfieldinthechannel,the front-gatetunnelingcurrentintheADGdeviceishigherthanthatintheSDG FinFET.However,lackofcarriersnearthebackgatereducesback-gatetunnelingin ADGdevices,andthustotaltunnelingcurrentishigherinSDGFinFETs,(unlessthe biasasymmetryinADGdevicesisexcessivelyhigh;inthefigure,fortheADGback gateisbiasedat0.1V).Also,notethatthecontributionofback-gatecurrenttothe totaltunnelingcurrentintheADGdeviceisnegligible,whichjustifiesthesimplified accounting of back gate tunneling in Section 6.2.3. Figure6.15, comparesthetunnelingcurrentinn-andp-channelFinFETs. Duetohigherbarrierheightfortheholes(Figure6.2),IGinpFinFETisalwayslower thanthatinnFinFET.Hence,inCMOScircuits,whentunnelingcurrentis significant,thestaticleakageisdominatedbytheleakagethroughnFinFETs.So,in

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191 Figure 6.13Effectsof DREFF onthegateleakagecurrent.ThelowVDScurrent isindependentof DREFF .TheFinFETismid-gapgateSDG,withLg=18nm,tSi=14nm,toxf=toxb=1nm,andLeff=26nm,and MOX = 0.7 is used in the simulation. -0.10.10.30.50.70.91.11.31. 5 VGS(V) 10-2010-1810-1610-1410-1210-1010-810-6|IG| (A/ m m) VDS = 0.1 VDS= 1.2, DREFF = 0.05 VDS = 1.2, DREFF = 0.10 VDS = 1.2, DREFF = 0.15

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192 Figure 6.14UFDG-predictedtunnelingcurrentthroughthegatesofSDG(line)and ADG(symbols)FinFETs.FortheSDGFinFETtunnelingtroughboth thefront(IGf)andthebackgate(IGb)arethesame,howeverforADG IGf>>IGb.RelevantUFDGmodelparametersare L =18nm, LES = LED =4nm, TSI =20nm, TOXF = TOXB =1.0nm,and MOX =0.65. For the ADG, the back gate is biased at 0.1V. 0.00.10.20.30.40.50.60.70.80.91.01.11.2Front Gate Bias, VGfS (V) 10-1710-1610-1510-1410-1310-1210-1110-1010-910-810-7IGf/b (A/ m m) IGf(ADG) IGb (ADG) IGf = IGb (SDG) VDS = 0V

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193 Figure 6.15UFDG-predictedtunnelingcurrentinn-andp-channelFinFETs. RelevantUFDGmodelparametersare L =18nm, LES = LED =4nm, TSI =20nm, TOXF = TOXB =1.0nm, WKFG = WKBG =4.6,and MOX =0.7. -1.5-1.1-0.7-0.30.10.50.91.3 VGS (V) 10-2010-1810-1610-1410-1210-1010-810-6IG (A/ m m) 14 12 10 12 14 10 nFinFET pFinFET toxtoxVDS = 0V

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194 thenextsection,wewillonlylookintotheeffectsofgatetunnelingcurrenton leakage in nFinFETs to ascertain the static leakage of FinFET-CMOS circuits. 6.4 Effects of Gate Tunneling Current on FinFET-CMOS Performance Withthedevelopedmodel,inthissectionwelookintotheeffectsofgate leakagecurrentonFinFET-CMOSintermsofstaticleakage.In Figure6.16the effect ofgateleakagecurrentontheSRAMcelloftheFigure5.3(b)isshown.Following theITRS45nmnode,weassumetox=6.5forthissimulation.Turningonthegate leakagecurrentincreasesthepowerconsumptionby~8%,from7.46 m Wto8.09 m W (calculatedfromtheaveragecurrentin Figure6.16(b)thatincreasesfrom7.46 mA to 8.09 m A).Theincreaseisduetoincreaseofleakageduringboththeactiveand inactiveperiodofthecellduetogatetunneling,However,asinanSRAMarrayonly onecellremainsactiveatacertaintimeandallothercellsremaininactive,thecell leakageduringinactiveperiodsisofmajorconcern.Forexample,forthetransient responseinthefigure,ifthecellisinactivefor0.35ns,thestaticleakageduetogate leakagecurrentincreasesby28%,from21nWto27nW,asignificantincrease consideringthefactthatinatypicalSRAMtherearemillionsofinactivecellsata certaintime.Notethatsuchincreaseinthestaticpowerwillbeabsentinpragmatic FinFET-SRAMsemployingthickergateoxide,asdiscussednext,wherewefurther lookintotheeffectofgateleakageonSiO2dielectricanddiscussadesignapproach that will help in reducing the gate leakage current. InFigure6.17,we lookintothescalabilityofSiO2(orSiON,withlow nitrogenconcentration)forFinFETs.ForthethreeITRSnodeconsidered,57nm, 45nmand36nm,onlythe57nmnodethathasa9-thickgateoxideisabletomeet

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195 Figure 6.16UFDG-simulatedtransientresponseofanFinFET-SRAMcell,(a) showswordandbitlinesignalsindicatingcellactivity,aswellasthe statusofthestoredbit,and(b)showstheUFDG-predictedcellcurrent, Icell(currentdrawnfromthepowersupply),withandwithoutthegate leakagemodelactivated.TheFinFETsinthecellhaveLg=18nm,tSi=9nm,andtox=6.5A,withVDD=1V.Pa/sin(b)differentiatesactive/ staticcurrentthatdefinestheactive/staticpower.Theoscillationsin thecellcurrentduringinactiveperiodisduetothetruncationerrorsin Spice. -0.1 0.1 0.3 0.5 0.7 0.9 1.1Voltage BL BL WL Stored Bit 0.00.10.2Time (ns) 10-310-210-1100101102Icell ( m A) IGATE = 0 IGATE = 1 MOX =0.7 (a) (b) Write Inactive PaPs

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196 Figure 6.17Gate-currentdensityatthreefutureITRSnodes[ITR05].Fora particularnode,thenodenumber,correspondinggatelength,oxide thickness,andsupplyvoltageareshownintheaxislabel.The acceptableJG,correspondstothemaximumgateleakagecurrent densityforITRShighperformancenodes.Insetshowsthevariationof JGwith MOX ,whichcouldbehigherthan0.7inthenodesconsidered here. 57nm, 22nmITRS Node 102103104105JG (A/cm2) 9, 1V 45nm, 18nm 6.5, 1V 36nm, 14nm 5.0, 0.9V UFDG, MOX = 0.7 Acceptable JG, [ITR05] 0.50 0.70 0.90MOX 101102103104JG (A/cm2)

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197 theITRSgateleakagelimitcriteria.Forthenexttwonodes,withgateoxidesonly 6.5and5thick,gateleakagecurrentisanorder-of-magnitudehigherthanthe ITRSrequirement.Notethatinthesimulationwehaveassumedthatthedeviceshave nounderlapswithtSi=Lg/2(whichistherequiredminimumtohavereasonable SCEs),andused MOX =0.7,whichwasobtainedfromourcalibrationtodatainthe previoussection.Theinsetin Figure6.17showsthevariationofJGwithmoxforthe 57nmnode.Increaseof MOX from0.7to0.9reducesJGby80%,andthusevenif MOX isincreasedforthethinneroxides(6.5and5),JGwouldnotmeetITRScriteria.For thosenodes(45nmand36nm)eitherthickerSiO2hastobeused(liketheoptimumdevice inChapter5thatuses1nmthickgateoxideforthe45nmnode)orhigh-kdielectricsare needed (as predicted in [ITR05]) if EOT = 6.5/5 needs to be maintained. Theseverityofgateleakageinthinneroxidesisfurtherillustratedin Figure6.18, whereacomparisonofsource/drainleakagewiththatofgatetunneling leakageispresentedforthethreeITRSnodesconsideredabove,andfortheoptimum device[Tri05a]studiedinChapter5.Source-drainleakageissimulatedwithVGS= 0andVDS=VDD,andforgatetunnelingleakage,thesimulationisdonewithVGS= VDDandVDS=0.Forthetwothinneroxides,thetotalleakagesolelycomesfrom thegatetunnelingcurrent.However,whenthedesignisoptimizedusingunderlap, allowingthickeroxideandthickerfilm,thegateleakagetosource-drainleakage ratiois~1.0,bothofwhichareinthenArange.Suchreductionofthegateleakage currentisencouraging,asitillustratesthatuseofunderlaps,whichallowsuseof thickerfilmandthickergateoxide(seethediscussioninChapter2),mightallowthe industry to delay the introduction of high-k dielectrics.

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198 Figure 6.18ComparisonofUFDG-predictedleakagecurrentsinnFinFETatthree ITRSnodes,57nmnode(A),45nmnode(B),36nmnode(D),and(C) depictsanoptimum45nm-nodenFinFET.Thevalueswithin parenthesisshowthecorrespondingLg,tSi,tox,VDD.Oxideisassumed tobeSiO2with MOX =0.7,andconfinementdirectionisassumedto be<100>.For(C),4.5nmofunderlapisusedoneachsideofthegate [Tri05a].(22nm, 11nm 9, 1V) (18nm, 9nm 6.5, 1V) (14nm, 7nm 5.0, 0.9V) 100102104Static Leakage Current (nA/ m m) IDS (VGS = 0, VDS = VDD) IG (VGS = VDD, VDS = 0) (18nm, 14nm 10, 1V) A B C D

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199 6.5 Summary WedevelopedagatetunnelingcurrentmodelforthegenericFinFET,in whichthemostdominantcomponentoftunnelingismodeledphysically,butless importantcomponents,neededmainlyfornumericalstability,areaccountedina heuristicmanner.Themodelwasverifiedagainstexperimentaldata,fromwhichthe tunneling-carriereffectivemassintheoxidewasfoundtobe0.7mo,andindependent of oxide thickness. Thedevelopedmodelwas,implementedinUFDG,andthenusedto ascertaineffectsofgateleakageatfutureITRSnodes.UFDGmodelpredictions corroborateearlierfindingsthatSiO2couldleadtounacceptablegateleakageeven inFinFET,ifscaleddowntoacoupleofatomiclayers(~6).However,ifthedevice isoptimizedbyusingunderlap,whichwillallowuseofthickergateoxides, introductionofhigh-kdielectriccouldbedelayedfurther,andperhapsavoided entirely in FinFET technology.

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200 CHAPTER 7 CONCLUSIONS AND RECOMMENDATIONS 7.1 Summary and Conclusion Inthiswork,throughUFDGcalibrationtonanoscaleFinFETdata,we havedetectedinsufficientsource/draindopantsintheextensionsofcontemporary FinFETsthatresultingate-source/drainunderlapsinsteadofoverlaps.Theeffectsof detectedunderlapsonFinFEToperationwerestudied,modeled,andshowntobe beneficialwhenoptimized;relateddevicedesigninsightswerediscussed.Further, studyofindustry-fabricatedFinFETdatarevealeddramaticallyhighmobilitiesin FinFETUTBs/channelscomparedtobulk-Sidevices.Extractedtransportparameters fromlongchanneldeviceswereusedtodeterminetransportmechanisminscaled FinFETsbyUFDGsimulation,whichisfoundtobeballistic-like.Furtherinsights ondesignofFinFETswithunderlapsweregainedthroughstudyofthesensitivityof FinFETperformancetovariationsofprocessparametersthataffectthesource-drain lateraldopingprofile.Wefoundthatwhilerelativelyshorterunderlapsaresuitable forlogiccircuits,formemory,likeSRAMs,longerunderlapsmightbeneeded. Additionaldesigninsightsweregainedthroughstudyofgate-leakagecurrentinDG MOSFETs,whichledtothedevelopmentofacompactmodelforthetunneling current.UFDGgateleakagesimulationshowedhigh-kdielectricswillbeneededif required EOT for a specific design reaches ~ 6. InChapter2,acalibrationmethodologyforUFDGwasoutlinedand exemplifiedbycalibratingnanoscaleFinFETdataobtainedfromindustry.The

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201 calibrationresultsrevealedabias-dependenteffectivechannellengthinFinFETs. Theeffectivechannellengthwasfoundtobelongerinweakinversionandshorterin stronginversion.Suchbias-dependencewasattributedtothepresenceofunderlaps inFinFETs,whichallowcarriermodulationtoextendbeyondthechannelregion.It wasalsoobservedthatduetolongunderlaplengths,contemporaryFinFETshave high,bias-dependentparasiticsource/drainresistance.Numericalsimulations(using MEDICI)weredonetoexaminetheuseofunderlapsinFinFETdesign.Theresults showeduseofunderlapsrelaxesfin-thicknessrequirements,andwidensthechoice ofacceptablegatematerials.Also,wefoundthatifsource-drainasymmetryis unavoidable,itisbettertohavethedrain-sideunderlaplongerthanthesource-side one. InChapter3,weupgradedtheUFDGformalismtoincorporatetheeffects ofunderlapsobservedinChapter2.Themodelwasupgradedtoaccountforthe modulationoftheeffectivechannellength.Themodelformalismwaskeptsimple, yetadequatelyphysicaltokeepUFDGpredictioncapabilitiesintact.Also,the definitionoftheUTBboundarypotentialwasupdatedtoincorporatetheeffectsof (i)depletioninsidethesource/drainand(ii)thelightlydopedunderlaps.The upgradedmodelwasverifiedwithnumericalsimulation.Possibleaccountingforbias dependenceofsource/drainresistancewasdiscussed.Howeveritwasfoundthatthe optimumFinFETwillrequireshorterunderlaplengthsthatwillmakethe(stronginversion)biasdependenceofparasiticresistancesnegligible.Hence,accountingfor parasiticresistancewiththeexistingbias-independentmodelparameterwas retained.

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202 Chapter4discussedtheapplicationoftheupgradedUFDGin understandingthetransportpropertiesoftheFinFET.Experimentaldatawere studied,anditwasfoundthatthemobilitiesinbothp-andn-channelFinFETsare dramaticallyhigh.Thehighmobilitywasfoundtobedueto(i)theundopedbodyand (ii)smoothersidewallsurfacesintheFinFETsstudied.Also,relativelylowerlowfieldmobilitywasobserved,whichwasshowntobeduetopossiblediffusionof source/draindopantsinthechannel,albeitataconcentrationnothighenoughto causeanydecreaseinthresholdvoltageofthedevice.Theextractedmobility parametersfromthestudywerethenusedtodeterminethetransportmechanismina 17.5nmFinFET.Forbothp-andn-channelFinFETsthetransportwasfoundtobe ballistic,i.e.,thermalinjection-limitedinsteadofbeingdissipative,whichimplies efforttoincreasethemobilityinFinFETs,likeusingstrain,isunnecessary.The effectsofparasiticsonthehighdrivecurrentofFinFETswerethenstudied.Dueto lowerchannelresistance,theFinFETsuffersmorethanthebulk-Sidevicesfrom parasiticresistance.However,comparisonwitha65nm-nodehypotheticalbulk-Si MOSFETrevealedthattheFinFET,duetomorethandoubleintrinsiccurrentand almostzerointrinsicweak-inversioncapacitance,canwithstandhigherparasitic resistanceandcapacitance,whilemaintainingaring-oscillatordelaythatisatleast equal to or higher than that of the bulk-Si technology. TheviabilityofFinFETdesignusingunderlapwasfurtherscrutinizedin Chapter5,wheresensitivityofFinFETperformance,tothevariationofparameters affectingtheunderlappropertieswasstudied.Duetothetinyvolume,thelateral dopingconcentrationintheextensioncouldberandom,andhencestudyof

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203 performancevariationwiththerandomnessofdopantsintheextensioniscritical. UsingMEDICIfordevice-levelsimulationandUFDGforcircuit-levelsimulation, effectsofrandomnessofdopantsintheextension,alongwitheffectsofvariationsin straggle,finthickness,andgatelengthwerestudied.Insteadofdoingastatistical studyoftheparametervariations,thestudylookedintotheextremecasestogauge thepeaksofperformancevariation.Thestudyconcludedthatrelativeshorter underlapswillnotintroducemuchvariationinring-oscillatordelay;however,for SRAM,longerunderlapsmightbeneededtomakethestaticnoisemarginless sensitive to the variation in underlap parameters. Finally,inChapter6,theeffectofgate-leakagecurrentinnanoscale FinFETswasstudied.Forthatpurposeacompactmodelfortunnelingcurrentwas developed.Carewastakentomodelthedominanttunnelingcomponentphysically, butsimplificationwasenforcedoncomponentsthatarenotdominant,butimportant fornumericalstability.Themodelwasverifiedagainsttunnelingcurrentdatafor sub-2nmgateoxidethicknesses.UFDG,updatedwiththegate-leakagemodel,was thenusedtostudystaticleakagesinFinFETswithfewatomiclayer-thickoxides.In spiteoflowelectricfieldintheFinFETchannel,itwasfoundthatthetunneling currentcanbeastronomical,andbecomesthedominantleakagecomponent,ifSiO2(orSiON)is~6A.Noevidenceofeffectsoftunnelingleakageontheperformanceof circuit is found, though. Basedontheworkonthisdissertation,weconcludethatviableFinFET technologywillrequireG-S/Dunderlaps,whichneedtobeoptimizedbasedon circuitapplications.Also,strainingthechannelisnotneededforFinFETs,asfaras

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204 mobilityenhancementisconcerned.Rather,moreeffortshouldbeputintoimproving theparasiticresistancesandcapacitances,which,duetolowresistanceoftheFinFET channelandlowintrinsiccapacitanceofscaledFinFETs,couldseverelydegrade FinFET-CMOS circuit performance. 7.2 Recommendations for Future Work TheUFDGstrong-inversionformalismdoesnotaccountfordrain-induced chargeenhancement(DICE)[Vee88].ItisreasonabletoneglectDICEinwelltempereddevicesoptimizedforSCEs,inwhichtheinversionchargeresidesatthe surfaces.However,intheFinFETstrongbulkinversioncanmakeitmoreproneto DICE,evenifSCEsinweakinversionarewellcontrolled.Whileitispossibleto circumventtheeffectsofDICEinUFDGbyextendingitsMIregionwellintotheSI, suchapproachisdiscouragedasitmakesmodelpredictionspronetopossible,nonphysicalvariationsinspline.Hence,modelingofDICEinUFDGisstrongly recommended to remove uncertainties in the qualitative predictions of UFDG. Inaddition,wealsorecommendaccountingforpunch-througheffectin weakinversion.Whileforawelldesigneddevice,punchthroughshouldnotbean issue,inasymmetricdesign,where,LeS
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205 ThecoreUFDGformalismthatderivesthesurfacepotentialinstrong inversionbysolvingPoissonsEquationrequiresNewton-Raphson(NR)iterationto obtainthesolutions.IthasbeenobservedinsomeADGsimulationsthattheNR methodleadstoconvergenceissues.Revisitingthesurfacepotentialmodelis suggestedtoremoveanypossible,non-physicalelementsintheformalism(like smoothingparametersthatmayleadtoinaccuratedescriptionofelectricfieldinthe channel). DuringthecalibrationtoFinFETdata,wenoticedthepresenceofvariable finthickness,aswellasvariableeffectivechannellengthalongtheheight,bothof whichpreventedusfromcalibratingUFDGtothem.Thusthereisaneedto understand,andifneededmodelsuchLeff(hSi)andtSi(hSi).Werecommendastudy devotedtounderstandingoftheoriginofsuchheightdependence,andtheireffects on circuit performance, and its sensitivity. Whilethevelocityovershootmodelwasrecentlyrefined,thechannellengthmodulationmodelthatwasoriginallydevelopedforclassicaldevicesisstill usedinUFDG,albeitwithaccountingforeffectsofthesecondgate.However, neglectofbulk-inversioninthevelocitysaturationmodelmightleadto overestimationofchannel-lengthmodulationandunderestimationofsaturation charges,andhencethechannel-lengthmodulationformalism,anditsimpactonboth the charge and current modeling, need refinement as well. Finally,aswehavefoundinChapter6,high-kdielectricsmightbeneeded forextremelyscaledFinFETs.Atthemoment,UFDGcanbeusedforhigh-k dielectricsbyconsideringthephysicaloxidethicknessparameterinUFDGasEOT,

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206 however,notaccountingfortheactualphysicalthicknessoftheoxidecouldleadto underestimationofSCEs.Also,therearereportsofmobilitydegradationduetohighkdielectrics,whicharenotaccountedforinUFDG.Hence,simplychangingthe physicaloxidethicknesstoEOTmaynotyieldaccuratepredictionfordeviceswith high-k dielectrics. So, accounting for such dielectrics is needed in UFDG.

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207 APPENDIX MISCELLANEOUS UFDG UPGRADES SeveraldiscreteUFDGupgradesthataccompaniedtheworksinthis dissertationaredescribedinthisappendix.Theupgrades/bugfixingdonecanbe categorizedintothreeparts:(i)improvingthespline,(ii)incorporating NBODY =0 case,and(iii)remodelingweakinversionandaccumulationcharge.Theworkdone onthesplineisobsoleteinUFDGversionshigherthan2.5,whichusethe2Dspline [Tri05b].However,itisdiscussedheretogivegeneralinsightontheefficacyof moderate-inversionspline.The NBODY =0optionfacilitatesuseofacontinuous model,butdoesnothaveaccountingforSCEsinweakinversion.Thechargemodel upgrades were done on an ad hoc basis, and may need further refinements. A.1 Refining the Moderate-Inversion Spline UFDGapproachesthetransportproblemindouble-gatestructuresby dividingtheregionofoperationintothreeparts:weak-,moderate-andstronginversionregion.Weak-andstrong-inversionregionaremodeledphysically,andfor themoderate-inversionregionaspline,whichgetstheboundaryvaluesfromthe physicalmodeloftheweak-andstrong-inversionregion,isused.Initiallyacubic splinewasimplemented[Chi01],whichisthenupgradedtoafourthorderspline [Ge02a]inUFDG2.1.Introducingfourthordersplinealongwiththemodel parameter SFACT and WFACT reducedthewigglesinsplinebutcouldnotremove itcompletely.Also,forparticulardevicestructure,especiallyforSDG,themodel

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208 showedalarmingconvergenceproblem.Beforelookingatthesolutionofthese wiggleorconvergenceissues,welookathowthesplinesareimplemented.For channel current Ich, the moderate-inversion current is defined as, (A.1) where, aiisconstantevaluatedatweak-inversionthresholdvoltage,VTW,andat strong-inversionthresholdvoltage,VTS.ThedefinitionofVTWandVTSevolves fromLimsdiscussionofthresholdvoltageofSOIdevices[Lim83],andgivenin [Ge02a] as (A.2) and (A.3) where,symbolsbearusualmeanings.NotethatbothVTWandVTSdependonVGbS, thebackgatebias.So,foraparticularVGfS,SpicecalculatesIchusing(A.1),after gettingthecoefficientsfromtheIch(VTW),Ich(VTS),etc.Foranotherbiaspointin themoderate-inversionregion,SpicecalculatestheVTSandVTWagainandthenIchfrom(A.1).Thethresholdvoltages(VTW,VTS)fromtwobiaspointcalculationsmay notbethesameduetotheirdependenceonthebackgatebias.EvenifthebackgateI ch () lnaiV GfS V TW ()i i 0 = 4= V TW V FBf r V FBb +1r + ()f wsf 1 C o x f -----------r C o x b ------------+ Q d 2 ------- r a w + () V GbS + 1 a w -------------------------------------------------------------------------------------------------------------------------------------------------------------------------= V TS C oxf V FBf f sf + () C oxb V FBb f sb + () + C f -------------------------------------------------------------------------------------------------------C b V GbS Q is Q d + () + C f -------------------------------------------------------- =

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209 biasisfixedinthecircuit,duringiterationsSpicesendsindifferentbiasvaluesbased ontheprevioussolution.Asthesolutionapproachesconvergence,theSpice generatedbiasvaluesalsoapproachestothatofcircuitbiasvalueswithinatolerance leveldefinedbyVNTOL.Notonlythat,thevaluesofIcharedependentonbothVGFSandVGbS.SofordifferentbiaspointevenifVTWandVTSremainidentical,butVGBSchanges(certainlyfortiedgates)theIchatVTW,andVTSwillbedifferent.These giverisetodifferentinitialvaluessoasdifferentsplinesfortwodifferentvaluesof VGFS.Thatis,inthemoderate-inversionregionthesolutionateachpointcomesfrom thecontributionofdifferentsplinesinsteadofasinglespline.This,eventhoughis notapparentintheactualvaluesofthenodecurrents/charges,iscertainlyreflected inthederivativesofthecurrents/charges,i.e.,thebumpsinthetransconductanceor capacitances.Notonlythat,inthestrong-inversionmodelUFDGusesNewtonRaphsoniterationmethodstogetthesurfacepotentialwhichfacesconvergence problemformoderate-inversionbiasvalues. FigureA.1 summarizesthesituation.To eliminatethismultiplesplineissueweneedbiasindependentVTHandVTWandneed to use consistent values of VGbS for calculating the boundary currents. Forsymmetricdouble-gateMOSFETsthegatesaretiedandthesolution issimple,redefinethethresholdvoltagesusingVGfS=VGbSanduseVGfS=VGbS= VTWandVGfS=VGbS=VTSfortheboundaryvalues.ThisisdoneinUFDG introducinganewmodelparameter DG DG =1assumesthegatesaretiedtogether, and0whentheyarenottied. FigureA.2 showstheeffectofparameter DG in transconductanceandcapacitancecharacteristicsoftheSDGMOSFET.The minimizationofbumpsinthetransconductanceandcapacitanceshelpsconvergence

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210 Figure A.1Cartoon depicting a typical ID-VG characteristic of an SDG MOSFET.Thedashedanddottedlinerepresentstwodifferentsplines used to get the Ich at two different VGfS, where as in reality they shouldcomefromthesinglespline(solidline)spanningfromVGfS= VTW to VGfS = VTS. log(Ich)VGFS VTWVTS Ich(VGfS1,VGbS1) Ich(VGfS2,VGbS2)Ich(VGfS=VTW,VGbS=VGbS) Ich(VGfS=VTW,VGbS=VGbS1)Ich(VGfS=VTW,VGbS=VTW) (VGfS=VTS,VGbS=VTS)Ich Ich(VGfS=VTS,VGbS=VGbS2) Ich(VGfS=VTS,VGbS=VGbS1) Weak Inv. Moderate Inv. Strong Inv.

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211 Figure A.2Effects of UFDG mode parameter DG on (a) gm-VGfS, (b) C-VGfScharacteristics of a symmetric DG MOSFET. -0.50.00.51.0VGfS (V) 0.0 2.0 4.0 DG = 1 DG = 0 -1.2-0.7-0.20.30.8VGfS (V) 0.0005 0.0010 0.0015 0.0020C (pF) DG = 1 DG = 0(b) (a)Normalized gm, IDgmID6.0

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212 andreducestheruntime.BytuningSFACTandWFACT,alongwithDG=1,one cangetalmostbumpfreecharacteristicsforsymmetricdevices.Forasymmetric devices,withtheaboveformalismofthresholdvoltagesand1Dsplinethereis nothingmuchtodo.However,Trivedi[Tri05b]hasredefinedthethresholdvoltage definitionsanddevelopeda2DsplinethateliminatesseparatedefinitionofVTS/VTWfor SDG and ADG MOSFETs, and reduces bumps in ADG characteristics. A.2 Incorporating NBODY = 0 Option Withscalingtheactualamountofdopantimpuritiesisgettingfewerin ultrathinbody(UTB)MOSFETs.Infactwithundopedbody,i.e.,wherethedoping densityisintheorderof1x1015cm-3duetointrinsicdefects,theactualdopantsin thechannelcanbezero.Forexampleadevicewith L =25nm, TSI =10nmand W = 100nmhas0.025dopantswithdopingdensityof1x1015cm-3,thatisthereisno dopantinthechannel.Thisphenomenagivesrisetosomeinterestingmodeling leeway. Conventionally,whilesolvingPoissonsequation,intheweakinversion itisassumedthattheinversionchargeisnegligiblecomparedtothedepletioncharge andinthestronginversionthedepletionchargeisconsiderednegligiblecomparedto theinversioncharge.Forzerodopantcaseinboththeregionsitcanbeassumedthat theinversionregionchargeisdominant,eliminatingtheuseofregionalanalysisdue todifferentassumptionsnecessarytosolvePoissonsequationinconventional modeling.So,forundoped-UTBMOSFETsthestrong-inversionmodelofUFDGis applicabletoallregions.InUFDGtheparameter NBODY definesthebodydoping concentration.Using NBODY =0,allowsusertousethestrong-inversionmodelfor

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213 allregionsofoperation,andthebodyisthenassumedtobeintrinsic.Butusing NBODY =0introducesnewissues.Oneofthemishowtodefinetheinversion condition?Conventional,beginningofinversionismarkedwhensurfacepotential reaches~2 fB( fB=(kT/q)ln( NBODY /ni)).Butfor NBODY =0case,i.e.,for intrinsicbody,thiswillleadto fB=0.Trivedi[Tri05b]observedthatinUTB devices,toreachinversionthesurfacepotentialhastoreachacertainconstant potential fc.Thefact,thatreaching fcindicatesthebeginningofinversionistrueas longasthedopingdensityislowenough,i.e.,aslongasthedepletionchargeis negligible.Thusfor NBODY =0beginningofstronginversionisdefinedby fcin UFDG. FigureA.3 showsanexampleof NBODY =0option.Thecharacteristics predictedwith NBODY =0isinexcellentagreementwiththatofwithfinitebody doping.With NBODY =0thereisnosplineandhencelessruntime.Thedrawback ofthisoptionisthatUFDGdoesnotmodelshort-channeleffectsinstronginversion, so NBODY =0optioncannotpredictSCEs.Also,UFDGusesNewton-Raphson iterationtogetthesurfacepotentialinstronginversion[Chi01],whichisproneto convergenceproblemwheneitherthefrontorbackgatebiasisnotinstronginversion.Oncethesetwoissuesareresolved, NBODY =0optioncaninitiateanew eraofSpicebasedcircuitsimulationasitwillbefreefromanysplineorsmoothing functions to take care of moderate inversion region.

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214 Figure A.3UFDG2.4 simulated ID-VG characteristics of a symmetric DG MOSFET illustrating the utility of NBODY = 0 option. The characteristics predicted with NBODY = 0 is almost identical with thatofwithfinite NBODY ,exceptforthemoderate-inversionregion, wherethelatterusessplinetogetthesolution.Alsonotetheabsence of short-channel effects with NBODY = 0. Values of key UFDG modelparametersare L =50nm, TSI =10nm,and TOXF = TOXB = 3nm. -0.5-0.3-0.10.10.30.50.70.91.1VGfS(V) 10-1210-1110-1010-910-810-710-610-510-4ID (A) NBODY = 0 NBODY = 1x1015 cm-3

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215 A.3 Refining the Charge Modeling TheUFDGchargemodelisdividedintofourregionsofoperation: accumulation,andweak,moderate,andstronginversion.Likechannelcurrent,the moderate-inversionchargemodelingisdoneusingsplinesthatuseboundary conditionscomingfromphysicalmodelinginweak-andstrong-inversionregions. Herewepresentarefinementdoneintheaccumulationandweak-inversionregion. Therefinementismainlyinthefrontgatecharge(QGf)formalism,whichalsoalters the back gate charge through the neutrality condition. A.3.1 Accumulation Charge TheoriginalUFDGaccumulationchargemodelstemsfrom[Cha97], wheretheaccumulationregionfrontgatecharge,QGfA,isdefinedwhenthedepletion region disappears, as (A.4) whereCofisthefrontgatecapacitance,Wisdevicewidth,Listheeffectivechannel length, Fms fisthefrontgate-siliconbodywork-functiondifference,andVBSisbody bias.AsmoothingfunctionthenusedforcontinuoustransitionofQGfbetween accumulationandweak-inversionregions.Theintrinsicassumptionin(A.4)isthat thesurfacepotentialispinnedatVBS,whichisreasonablewhenthebodydopingis high.ButforUTBdevices,wherebodyisintrinsicorlightlydoped,thepinning occursatfc+VBS,ala fcinstronginversion[Tri05b].Sothelinear,(strong) accumulation charge can be redefined asQ GfA C of WLV GfS F f ms V BS =

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216 (A.5) Betweenthestrongaccumulationandweakinversionthereistheweak-accumulation charge,i.e.,wheregatebiasissmallerthanflatbandvoltagebutlargerthatfc, modelingofwhichismoredemanding.Consideringthefactthatweakaccumulation chargeissmallcomparedtoothercharges,andhaslittleimpactonthedevice behaviorinnormaloperatingcondition,thistransitioniscapturedbyintroducinga smoothingfunctionthatapproaches(A.5)forthenegativeVGfSandzeroforvery positive VGfS. (A.6) wherethecoefficientAisahard-wiredparameterthatdefinesthestiffnessofthe transitionbetweenthestrongaccumulationandweakinversion/accumulationcharge. Thevalueo fA=4.0kT/qextractedfromexperimentalC-VdataoftypicalDG MOSFETs, is used in the code. Asimilarapproachistakentomodeltheback-gateaccumulationcharge QGbA.Earlier,QGfAwasaccountedforinthebodycharge,andtheback-gatecharge wasderivedfromneutrality.Thatis,oncethebodychargewascompletely compensatingthefront-gatecharge,theback-gatechargeinaccumulationwaszero, i.e.,theQGbAmodelwasinaccurate.So,wemodelbothfront-gateandback-gate accumulationchargesindependently,andthebodychargeinaccumulation,QBA, then comes fromQ GfA C of WLV GfS F f ms V BS fc+ = Q GfA C of WLA 1 V GfS F f ms V BS f c + exp A ---------------------------------------------------------------------------------------+ ln =

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217 (A.7) whereQDisthebodydepletioncharge.Thisformalismensuresthat(i)theback-gate chargeinaccumulationismodeledphysicallyandproperlyand(ii)thebodycharge, whichisactuallythereflectionofbothgatechargesplusthedepletioncharge,is modeled accurately. A.3.2 Weak-Inversion Charge The intrinsic quasi-static front gate charge comes from Gausss law as (A.8) where fsf(y)isthespatiallyvaryingsurfacepotentialdiscussedinChapter3.Inweak inversion, for negligible VDS dependence, (A.8) can be approximated as (A.9) where fsf is the average front surface potential given as (A.10) Theweak-inversionfront-gatechargemodeldescribedby(A.9)is reasonableexceptfortheuseofeffectivechannellengthL.AsshownintheFigure 3.2,thedistanceLeisthelengthoverwhichthedominantcurrentisdiffusioncurrent, andthelateralelectricfieldisnegligiblecomparedtothefieldclosertothesourceQ BA Q D Q GfA Q GbA + () = Q Gf WC of V GfS F f ms jsf y () yd0 L= Q Gf WLC of V GfS F f ms jsf = jsf 1 L --jsf y () yd0 L=

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218 anddrainjunctions,andLSandLDaretheweak-inversionchannellengthmodulation inthedrainandsourcesiderespectively[Yeh96],whichcanbemodeledasthe depletionwidthinthelightlydopedsideofap-njunction[Yeh96].Thegatecharge ismainlyimagedwithinLe,whereasLD(LS)modulatesthecontributionofbody chargeinthechargeassociatedwithdrain(source)node.Sowith(A.9)thegate chargeisoverestimatedwiththeuseofLinsteadofLe.Theproperformoffront-gate charge in weak inversion is then (A.11) with (A.12) and,(A.13) where fmin(x),LS(x)andLD(x)arederivedintheUFDGformalismvia[Yeh96].The chargemodelpresentedin(A.11)isstrictlyclassical.Toincludethequantumeffects weneedtosubtractacorrectionpotentialtothesurfacepotentialterm,andis discussed in Section A.5. Asmentionedbefore,thechargewithinLS(LD)issupportedbysource (drain),andtobeconsistent,itshouldbeaddedtotherespectivenodecharges.But becausetheinaccuracyinvolvedissmallcomparedtotheneedednonlinearityQ Gf WL e C of V GfS F f ms jsf = jsfjmin x 0 = () = L e x 0 = () L eff L S x 0 = () L D x 0 = () =

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219 involvedinaddingtheminthesourceandthedrainchargemodels,thesecomponents of the body charges are neglected all together. A.4 Refinement of the Velocity Overshoot Model InUFDG,theaccountingforvelocityovershootisdonebymodifyingthe saturationvelocity(vsat)torepresentaneffectivevelocity(vsat(eff))thatincorporates non-localeffectslikelaggingofcarriertemperature(Tc)behindthelocalelectric field. It is expressed as [Ge01] (A.14) where D LisLg-LeasdefinedinFigureA.4(b),vsatisUFDGmodelparameter VSAT andtypicallyis6x106cm2/s.While(A.14)hasproperfunctionaldependenceofTcthrough meff(Tc),it,inessence,isthevelocityaty=Lg(FigureA.4(b)),wherev(y) in the high-field region is deduced as [Ge02a] (A.15) Assumingv(Lg)astheeffectivevelocityinthehighfieldregion(within D LinFigure A.4(b))resultsinoverestimationofID(vsat(eff)),speciallyfornanoscaledevices where the electric field at y = L is much higher than that in y = Le. Tocorrectthisoverestimation,weredefinevsat(eff)astheaveragevelocity of an electron passing the high field region with a transit time ttr; i.e.,v sateff () v sat 1kT m eff qv sat l c -----------------D L l c -----tanh + = vy () v sat 1 KT m eff qv sat l c -----------------y L e l c --------------tanh + =

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220 Figure A.4Highfieldregioninthechannelofadouble-gateMOSFET,(a)Cross section of the MOSFET, and (b) the lateral electric field along the channel [Chi01]. From 0 to Le, the electric field varies linearly, and defines the linear region of the channel, beyond that velocity of the carriers saturate and Le to Lg defines the saturation region. Source Drain LgLeChannel -Eyy High-eld region (2-D) 0 x y Front Gate Back Gate Source Drain BODYOxide Oxide tb toxftoxb Lg(a) (b) D L

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221 (A.16) Plugging in v(y) from (A.16), we have (A.17) whereand.Theintegrationin(A.17)is analyticallysolvable,however,alogarithmictermwithargument(1D L/lc)may drivethesimulatornumericallyunstableduringSpiceiterations.Hence,wewill approximatetheintegralusinga4-steptrapezoidalintegration.Formostcases, where D Lis2or3timeslc(~3nmforITRS32nmnode),the4stepsarereasonable. Acomparisonofvsat(eff)from(A.17)and(A.14)isshowninFigureA.5. Notetheunusuallyhighvelocitypredictedby(A.14),infact,vsat(eff)from(A.14)is higherthanthepeakvelocity(VOP)predictedinthechannelofaDGMOSFETwith tSi=10nmbyMonteCarlosimulation(~1.9x107cm2/s,[Gam04]).Incontrast,even thoughitisnotpossibletoverifythepredictionof(A.17)withexperimentalorMC simulationdataduetolackofit,thevsat(eff)from(A.17)islessthanVOP,andis higher than typical v(Le) ~107cm/s, indicating an improvement over that of (A.14). TheUFDGmodelparameter VO thataccountsfortheuncertaintyinthevsat(eff)model is still used; it modulates lc by lc/ VO in (A.17).v sateff () D L t tr -----D L 1 vy () ---------ydL e Lg1 == v sateff () D L l c -----v sat fz () zd0 D L l c ------1 = A kT meffqvsatlc--------------= fz () 1 1 Az () tanh + ------------------------------=

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222 Figure A.5Comparison of effective saturated velocity (vsat(eff)) predicted by (A.14)and(A.17).ThetestdeviceisannFinFETwithLg=18nm,tSi=10nm,tox=1nm.UFDGmodelparameter VSAT =5x106cm/s,and VO = 1 is used. 0.000.250.500.751.001.251.501.752.00VDS(V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5vsat(eff) (107 cm/s) (A.14) (A.17) Ninv = 1013cm-2

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223 A.5 Weak-Inversion QM Model WhileforSDGMOSFETs,theUFDGweak-inversionQMmodel[Ge02a] isreasonablyaccurate,forMIGFETs,itoverestimatestheQMeffects.TheWIQM modelinUFDGonlyconsidersgroundstate,E11,andcalculatesthedecreaseof surfacepotential( fsf)bysubtractingE11/qfromclassical-potential.Inotherwords, theconductionband(Ec)isreplacedby(Ec+E11)forthepurposeofcalculating carrierconcentrationusingM-Bstatistics.Theassumptioninherenthereisthatmost ofthecarriersareinthegroundstate,whichisnotgenerallyaccurateforUTB MOSFETs.Also,forMIGFETs,Ec(x) Ec(0)(Figure6.8),andhenceassumingthat carriershaveenergyE11+Ec(0)(whereE11istheKEandEcisthePE)allalongthe channeloverestimatestheaverageenergyofthecarriersinthechannel,whichresults inthenotedoverestimationofQMeffects.RecentworkbyTrivedi[Tri05b] overcomesbothofthesetwoproblems,i.e.,itconsiderscontributionsofother subbandsandproperlyaccountsforEc(x)variationintheMIGFET,andviaarefined model for QM effects in WI based on a variational method. Trivedismodel,whichisverifiedagainstnumericalsimulations[Tri05b], isimplementedinUFDGVer.3.6.TheQMeffectisincorporatedasaperturbation of WI surface potential; given by (for the nMOSFET) as [Tri05b] (A.18) where Dfs QMisthereductionoftheclassicalpotential fCLobtainedfromsolutionof the2DPE[Yeh96],Ex1Disthetransverseelectricfieldinthechannel,expressedin (6.23),isthereducedPlancksconstant,Ncisthe3DeffectiveDOSforthe Djs QME0q ----kBT q --------gmDp h 2Nc---------------qEx 1 D1 qEx 1 DtSi kBT () exp ------------------------------------------------------------g ln = h

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224 conductionband,Ej(Ej)istheseparationbetweenthejthsubbandintheunprimed (primed)valleyandthebottomoftheconductionbandatthefrontsurface,g(g)and mD(mD)arethedegeneracyandDOSeffectivemassfortheunprimed(primed) valley, and g includes the effects of all other subbands as [Tri05b] (A.19) Thesubbandenergiesarefoundusingavariationalmethodanddependsonboththe structural and electrical confinement, (A.20) Theelectricalconfinementterm(secondtermontherighthandside)dependsonthe cubicrootofEx1D(throughthevariationalparameterbj,givenbyanexpression similarto(6.18)),whichforcesustouseasmoothingfunctionintheUFDG implementationofEx1Dsothatitdoesnotgonegativewhenthebackgatebecomes dominantin(6.23).TheformalismforthepMOSFETs,withtheheavy-andlighthole valence bands analogous to the conduction band valleys above, is the same. InFigureA.6,we presenttheimprovementsinthepredictionsofUFDG3.6overUFDG-3.5forIGFinFETs.FortheSDGMOSFETincluded,boththeold QMmodelinVer.3.5[Ge02a]andtherefinedmodelofVer.3.6arewellin agreement.However,fortheIGFET,theoldmodelnotonlyunderestimatesIDdue tooverestimationoftheQMeffects,italsointroduceswiggleintheID(VGS) g 1 E0Ej kBT ----------------expj 1 =g mD gmD-------------E0Ej kBT ------------------expj 0 =++ = Ejh 22 mx--------p j 1 ) + () tSi---------------------2bj 23 4 3 -1 bjp tSi ()21 + [] --------------------------------------- + @

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225 Figure A.6Comparisonofweak-inversionquantum-mechanicalmodelinUFDG 3.5withtherefinedmodelinUFDG3.6forbothSDGFinFETandIG FinFET. For SDG, VGfS = VGbS, and for IG VGbS = 0.2V. Mid-gap gate,Lg=18nm,tSi=10nm,andtox=1nmisusedforthesimulations. -1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0VGfS (V) 10-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-3IDS(A/ m m) IG, UFDG 3.6 IG, UFDG 3.5 SDG, UFDG 3.6 SDG, UFDG 3.5 VDS=1.0V VDS=0.05V

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226 characteristicsaroundVGfS=VGbS.Theincorporationofthisimprovedweakinversion QM model thus facilitates reliable simulation of MIGFETs.

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236 BIOGRAPHICAL SKETCH MurshedMahmudChowdhuryreceivedhisB.Sc.Eng.andM.Sc.Engin electricalandelectronicengineeringfromBangladeshUniversityofEngineering andTechnology,Dhaka,Bangladesh,in1998and2001respectively.Inthesummer of2002hejoinedtheSOIgroupattheUniversityofFloridaasaresearchassistant. Sincethenhehasbeenworkingonthephysics,modeling,anddesignofnanoscale ultra-thin-body(UTB)devices,includingFinFETs.Hisresearchinterestconcerns tunnelinginultra-thindielectric,transportinultra-thinchannels,andelectrostatics of multi-gate MOSFETs. In2004,heworkedasaco-opdeviceengineeratFreescale Semiconductor,Austin,TX,wherehewasengagedincharacterizationofmulti-gate devices,modelingofleakagecurrentsinFinFETs,andimplementationofUFDGin Freescalesinternalcircuitsimulator,MICA.HewentbacktoFreescaleinthe summerof2005todoacomparativestudyofdifferentapproachesofdesigning FinFETs.UpongraduationhewilljointheNovelDeviceGroupatFreescale SemiconductorasaDeviceEngineerworkingonfuture-generationCMOS technology development.


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Title: Physical Analysis, Modeling, and Design of Nanoscale Double-Gate MOSFETs with Gate-Source/Drain Underlap
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Copyright Date: 2008

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PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE
DOUBLE-GATE MOSFETS WITH GATE-SOURCE/DRAIN UNDERLAP













By

MURSHED M. CHOWDHURY


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY


UNIVERSITY OF FLORIDA


2006































Copyright 2006

by

Murshed M. Chowdhury






































-To-


My parents and Rono















ACKNOWLEDGMENTS

It has been an honor to work for, and with, my supervisor, Professor Jerry

Fossum. Without his patient and inspiring guidance, encouragement, and support,

this work would not have been possible. I would like to take this opportunity to

express my gratitude to him. I would also like to thank members of my supervisory

committee, Professors Scott Thompson, Jing Guo, and Kevin Ingersent, for their

guidance and interest in this work.

I would like to acknowledge Semiconductor Research Corporation,

Freescale Semiconductor, and the National Science Foundation for their financial

support. I would also like to thank Freescale Semiconductor and AMD Inc. for

measured data.

I am grateful to Bich-Yen Nguyen for giving me an opportunity to gain

industry experience at Freescale Semiconductor. I have greatly benefited from the

interactions with the Novel Device, CMOS and MICA group members. I was

extremely lucky to have Leo Mathew and Chip Workman as my mentors there, both

of whom patiently suffered my constant demand of data and modeling-tips. Also, I

am thankful to Aaron Thean and Ben Gu for numerous discussions.

I was fortunate to work with fellow group mates, Lixin Ge, Ji-Woon Yang,

Vishal Trivedi, Weimin Zhang, Seung-Hwan Kim, Zhichao Lu, Siddharth Chouksey,

and Shishir Agarwal. I have had many illuminating discussions with them, especially

with Vishal, working with whom was an intriguing and beneficial experience. I









would like to thank my friend Saif Uz Zaman, and Khairul Alam for riveting

conversations on many aspects of device physics. In addition, I would like to thank

Saif, and Syed Hussain Rana for reading this manuscript.

I acknowledge the unconditional help I received from Tipu bhai, Boro

Dulabhai, and Sheuli khala. I was fortunate to have such relatives and friends who

are always there when needed. Likewise, my stay here in Gainesville is made easier

by the presence of an accommodating community, whose good fellowship helped me

to keep my morale high all these years. In particular, I would like to thank Maksudur

Rahman, Shahed Nejhum, Sayed Hasan, Avijit Kar, Ziad Saleh, Naheen Aden,

Shahed Reza, Reza Nabi, Mustaque Ahmed, and Amas Khan for their camaraderie.

Finally, I am indebted to my parents, and siblings, Appi, Rono, Shetu,

Rana, Meru and Moury, for their constant encouragement and support. My deep

gratitude goes to my parents for their many sacrifices for my education. This work is

dedicated to them, and to my selfless brother.















TABLE OF CONTENTS


page

ACKNOW LEDGM ENTS ........................................... iv

LIST OF TABLES ......... ............................................ ix

LIST OF FIGURES ........ ............................................ x

KEY TO ABBREVIATIONS. .......................................... xiv

ABSTRACT ........ ................................................. xv

CHAPTER

1 INTRODUCTION .......... .......................................1

1.1 Double-Gate MOSFETs; FinFETs .............................. 1
1.2 Compact Model for the DG MOSFET ........................... .. 2
1.3 D issertation O utline ............................................ 5

2 PHYSICAL INSIGHTS ON DESIGN AND MODELING OF NANOSCALE
FIN FETS......... ............................... 9

2.1 Introduction ..................................................9
2.2 UFDG Calibration Methodology ................. ............. 11
2.3 Calibration of UFDG to AMD nFinFETs .......................... 16
2.4 Calibration of UFDG to Freescale Poly-Gate nFinFETs ............... 20
2.5 Calibration of UFDG to Freescale Metal-Gate pFinFETs .............. 22
2.6 D evice D esign Im plications ................................... 26
2.7 Summary ......... ........ ................ ..... .......33

3 UFDG UPGRADES FOR NANOSCALE FINFETS WITH UNDERLAPS.... 35

3.1 Introduction ......... .. ...... .. ....... 35
3.2 Calculation of Weak-Inversion Current in UFDG .................... 36
3.2.1 Review of Weak-Inversion Current Model in UFDG ........... 36
3.2.2 Source/Drain-Body Junction Potential ................. .... 40
3.2.3 Weak-Inversion Model Verification for DG MOSFET .......... 47









3.3 Upgrades in Weak-Inversion Model for FinFET with Underlaps ........ 49
3.3.1 Model Upgrades ..................................... 49
3.3.2 Verification and Utility .................................. 58
3.4 Upgrades in Strong-Inversion Model for FinFET with Underlaps ....... 64
3.4.1 Effective Channel Length. .............................. 64
3.4.2 Parasitic Resistance ................ .................. 65
3.6 Conclusion ........ ........................................75

4 CARRIER TRANSPORT IN NANOSCALE FINFETS ................... 79

4.1 Introduction ....... .............................. ......... 79
4.2 Carrier Mobility in the Channel .............................. 80
4.2.1 Electron M obility in nFinFET ............................. 80
4.2.2 Hole M obility in pFinFET ............................ 100
4.3 Ballistic-Limit Current ............... ..................... 107
4.4 Effects of Parasitics, and Design Implications ................... .. 109
4.4.1 Effects of Parasitic Resistance ............................ 111
4.4.2 Effects of Parasitic Capacitance ........................... 115
4.5 Summary ......... ........................................117

5 SENSITIVITY OF FINFET PERFORMANCE TO GATE-SOURCE/DRAIN
UNDERLAP PROPERTIES .............. .................. 119

5.1 Introduction ............... .................. ........... 119
5.2 Reference FinFET ................ ....................... 123
5.3 Effects of Variation of Film Thickness ........................... 128
5.4 Effects of Variation of Gate Length. .......................... 130
5.5 Effects of Variation of Lateral Straggle ........................... 132
5.6 Effects of Random Doping ................ .................. 136
5.6.1 NSD(y) Randomness ................ ................. 135
5.6.2 NSD(x) Randomness ................ ................. 139
5.6.3 Random UTB/Channel Doping ......................... 143
5.7 Worst-Case Scenario ................ ...................... 145
5.8 Summary ......... ........................................148

6 GATE TUNNELING CURRENT IN NANOSCALE FINFETS ............ 150

6.1 Introduction ........................... ......... ..... .. 150
6.2 Compact Model for Gate Tunneling Current in FinFET .............. 151
6.2.1 Tunneling Current Components ................. ........ 153
6.2.2 Tunneling Current Model ............................ 157
6.2.3 Tunneling in Asymmetric-Gate Devices ................. .. 174
6.2.4 Drain Bias Dependence of Tunneling Current .............. 178
6.3 Model Implementation and Verification ...................... 182
6.4 Effects of Gate Tunneling Current on FinFET-CMOS Performance. .... 194
6.5 Sum m ary ......................................... ....... 199









7 CONCLUSIONS AND RECOMMENDATIONS ....................... 200

7.1 Summary and Conclusion. ................................... 200
7.2 Recommendations for Future Work ............................ 204

APPENDIX

MISCELLANEOUS UFDG UPGRADES ............................ 207
A. 1 Refining the Moderate-Inversion Spline ....................... .. 207
A.2 Incorporating NBODY= 0 Option ............................ 212
A.3 Refining the Charge Modeling .............................. 215
A.3.1 Accumulation Charge ............................. 215
A.3.2 Weak-Inversion Charge ............................. 217
A.4 Refinement of the Velocity Overshoot Model .................. ... 219
A.5 Weak-Inversion QM Model ................ ................. 223

REFERENCES ........ .............................................. 227

BIOGRAPHICAL SKETCH .............. ..........................236















LIST OF TABLES


Table p

2.1 Key UFDG model parameters with brief description .................... 12

3.1 UFDG-predicted ring-oscillator delay for an 18nm-FinFET ............... 76

4.1 Key UFDG model parameters extracted from the calibration .............. 82

4.2 SCHRED-predicted subband occupation properties ................... 99

4.3 Key UFPDB model parameters used in the study ................... .. 110

5.1 MEDICI- and UFDG-predicted characteristics of FinFETs .............. 138

5.2 UFDG-predicted variation of performance of FinFET-CMOS ............ 147















LIST OF FIGURES


Figure page

1.1 Double-Gate M OSFET structures .................................. 3

2.1 Measured SCEs vs. Lg of CMOS FinFETs ........................... 10

2.2 Partial UFDG calibration to an Lg = 105nm nFinFET ................... 17

2.3 Partial UFDG calibration to an Lg = 17.5nm nFinFET ................. 18

2.4 Partial UFDG calibration to an Lg = 100nm nFinFET ................ 21

2.5 Calibration of UFDG to metal-gate pFinFETs. ....................... 23

2.6 Calibration of UFDG to a 75nm metal-gate pFinFET ................. .. 24

2.7 Variation of TiN gate workfunction (0M) with drawn length .............. 25

2.8 Schematic cross section (top view) of an undoped FinFET................ 27

2.9 Effects ofunderlaps on the subthreshold characteristics of FinFET ......... 29

2.10 MEDICI-predicted variation of ION and IOFF ......................... 31

2.11 MEDICI-predicted variation of FinFET performance .................. 32

3.1 Boundaries for the solution ofPoisson's equation in the DG-MOSFET...... 37

3.2 Lateral potential profile in weak inversion in the channel ................. 41

3.3 Schematic of variation of lateral potential............................. 43

3.4 Comparison of the variation of boundary potential ................... .. 46

3.5 Comparison of UFDG predictions with that of MEDICI in weak inversion ... 48

3.6 MEDICI-predicted surface potential variation between S and D ........... 50









3.7 UFDG calibration to a MEDICI-simulated mid-gap FinFET. ............. 52

3.8 MEDICI- and UFDG-predicted potential profile, 0(y) ................... 54

3.9 Recalibration of the 18nm-FinFET ............................... 56

3.10 Calibration of UFDG to a MEDICI-simulated 15nm-thick fin FinFET. ...... 60

3.11 MEDICI-simulated electric field vector in the x-y plane .................. 61

3.12 Comparison of UFDG predicted LES + LED. ....................... 63

3.13 MEDICI-predicted electron velocity along the channel. .................. 68

3.14 Extracted linear resistance of an 18nm-FinFET. ...................... 70

3.15 Comparison of MEDICI- and UFDG-predicted I-V characteristics ......... 72

3.16 UFDG-predicted variation of ring-oscillator delay ................... .. 74

4.1 Calibration of UFDG to weak-inversion characteristics .................. 83

4.2 Calibration of UFDG to measured gm/ID2 vs. VGS ................ . 84

4.3 UFDG-predicted strong-inversion ID-VGS characteristics ................. 86

4.4 MEDICI-predicted variation of gm/ID2 with polysilicon doping ............ 88

4.5 SCHRED-predicted average distribution of carriers ................... 94

4.6 Calibrated UFDG-predicted variation of effective electron mobility ........ 97

4.7 Results of calibrating UFDG to an Lg = 10mm pFinFET ................ 102

4.8 UFDG calibration to the ID-VGS characteristics of the 10mm-pFinFET..... 103

4.9 UFDG-predicted effective hole mobility ............................. 105

4.10 UFDG-predicted current-voltage characteristics ...................... 108

4.11 Effects of parasitic resistance on the on-sate current .................. 113

4.12 Predicted propagation delays versus parasitic source/drain resistance ...... 114

4.13 Predicted propagation delays versus parasitic capacitance ............... 116









5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10

5.11


6.1 Leakage current components in a CMOS-inverter


6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

6.12


. . . . . . 1 5 2


Tunneling current components in an nFinFET. ..............

Dominant tunneling component in a metal-gate .............

Tunneling from semi-classical picture ............... .....

SCHRED-simulated conduction band profile ...............

Comparison of distance between classical turning points ......

Variation of ground-state electron velocity with bias .........

Schematic of variation of Ec(x) in weak inversion in a MIGFET

Variation of IGs/IG with drain bias. .......................

Updated UFDG network diagram ......................

Significance of the higher subbands in FinFET ..............

Comparison of UFDG gate leakage model's prediction .......


.......... 154

. . . 156

. . . 159

.......... 164

.......... 166

.......... 169

.......... 176

. . . 183

.......... 184

.......... 186

........ 188


The lateral S/D-extension doping concentration, NSD(y) ................ 121

Partial calibration of UFDG to MEDICI-predicted characteristics ......... 125

FinFET-CMOS circuits used in the sensitivity study ................... 127

Sensitivity of FinFET performance-parameters with the variation of tsi. .... 129

Sensitivity of FinFET performance-parameters with the variation of Lg .... 131

Effects of varying Lg, but keeping Lext constant ....................... 133

Effects of variation of lateral straggle on the sensitivity of FinFET ........ 134

Various lateral doping profiles. ................ ................. 137

Localization of lateral dopants, NSD(y) at different x ................... 141

Medici-predicted ID-VGS characteristics ............... ............ 142

Taurus-Device-predicted effects of uncontrolled doping on ID-VGS ........ 144









6.13 Effects of DREFF on gate leakage current. ......................... 191

6.14 UFDG-predicted tunneling current through the gates ............... 192

6.15 UFDG-predicted tunneling current in n- and p-channel FinFETs .......... 193

6.16 UFDG-simulated transient response of an FinFET-SRAM cell ........... 195

6.17 Gate-current density at three future ITRS nodes ................... .. 196

6.18 Comparison of UFDG-predicted leakage currents in nFinFET ............ 198

A. 1 Cartoon depicting a typical ID-VG characteristics ................. 210

A.2 Effects of UFDG model parameter DG ........................ 211

A.3 UFDG2.4 simulated ID-VG characteristics ......... .......... 214

A.4 High field region in the channel of a double-gate MOSFET .............. 220

A.5 Comparison of effective saturated velocity ........................... 222

A.6 Comparison of weak-inversion quantum-mechanical model .............. 225















KEY TO ABBREVIATIONS


MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor

CMOS Complementary MOS

SOI Silicon-on-Insulator

FD Fully depleted

UTB Ultra-thin body

SG Single gate

SDG Symmetrical double gate

ADG Asymmetrical double gate

IG Independent gate

UFDG University of Florida Double Gate

KE Kinetic energy

PE Potential energy

SCE Short-channel effect

DIBL Drain-induced barrier lowering

QM Quantum mechanical

TEM Transmission Electron Microscopy

MC Monte Carlo

DOS Density of states

SDE Source/Drain Extension














Abstract of Dissertation Presented to the Graduate School of the
University of Florida in Partial Fulfillment of the Requirements
for the Degree of Doctor of Philosophy


PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE
DOUBLE-GATE MOSFETS WITH GATE-SOURCE/DRAIN UNDERLAP

By

Murshed M. Chowdhury

August 2006

Chairman: Jerry G. Fossum
Major Department: Electrical and Computer Engineering

This dissertation focuses on the physics and modeling of nanoscale

double-gate (DG) field-effect transistors (FETs). The modeling work is incorporated

in the University of Florida Double-Gate (UFDG) metal-oxide-semiconductor field-

effect transistor (MOSFET) model that enables predictive device/circuit simulations

of complementary metal-oxide-semiconductor (CMOS) circuits based on DG FETs.

Physical insights on the electrostatics of the DG MOSFET, especially the

quasi-planar FinFET, are gained from calibration of UFDG to data obtained from

industry. The calibration results show that contemporary FinFETs have gate-source/

drain underlap that makes the effective channel length, and parasitic resistance, bias-

dependent. Insights from the calibrations, along with numerical simulation results,

reveal that the noted underlaps could be used beneficially in scaled FinFET design.

The study also pinpoints required UFDG upgrades for nanoscale FinFETs, which are

subsequently done and implemented in UFDG.









The upgraded model is then used to gain insights on the transport

properties of scaled FinFETs by, again, calibrating UFDG to experimental data. The

calibration results show mobilities in both p- and n- channel FinFET are dramatically

high compared to those in bulk-Si MOSFETs. The high mobilities portend, as shown

by UFDG, ballistic-limit current in nanoscale FinFETs, which leads us to the

conclusion that channel engineering, like straining the channel, to increase mobility

in the FinFET is not needed.

The viability of gate-source/drain underlap as a design parameter, in

addition to typical device design parameters like gate length, fin thickness, etc., is

investigated in terms of the sensitivity of FinFET performance to the variations of

process parameters that influence underlap properties; numerical simulators with

UFDG aid this investigation. It is found that while variation in the performance of

inverter-based circuits, like the ring oscillator, is reasonable, stability of static

random access memory (SRAM) shows wide variation in performance for shorter

underlap lengths.

Finally, a physics-based compact model for gate tunneling current in DG

MOSFETs is developed, verified, and implemented in UFDG to enable reliable

prediction of static power consumption in nanoscale FinFET circuits. Model

predictions corroborate earlier results that for thinner oxides, present-day silicon

oxynitride has to be replaced with high-k dielectrics to control static leakage.

However, use of underlap can relax the oxide thickness requirement and hence delay

the introduction of high-k dielectrics in FinFET technology.














CHAPTER 1
INTRODUCTION

1.1 Double-Gate MOSFETs; FinFETs

In the past three decades, the number of transistors per chip has gone up

to a few hundred million, from a few thousand in the early '70s [Boh03]. Such an

astronomical increase of transistors per chip is facilitated by continuous scaling of

the bulk-Si MOSFET, the workhorse transistor of digital integrated circuits.

However, as the feature size is approaching sub-50nm, the scaling of the bulk-Si

MOSFET faces stiff challenges coming from increased source-drain leakage,

increased gate tunneling current, and wide variations in device performance due to

uncontrollable channel doping [ITR03]. Hence, researchers are searching for

alternatives to the bulk-Si MOSFET and its silicon-on-insulator (SOI) counterpart,

the partially depleted (PD) SOI MOSFET. Among the alternative devices considered

so far, the double-gate (DG) MOSFET [HisOO] is the most promising candidate to

replace bulk-Si devices down the roadmap [ITR03].

The DG MOSFET is of the same material as the bulk MOSFET, i.e.,

silicon, but has a different structure. It offers better control of short-channel effects

(SCE) control [Kim01b] arising from the use of two gates with an ultra-thin body

(UTB); and high drive current per device width resulting from high mobility due to

low transverse electric field and higher inversion carrier density from the two

channels. The DG MOSFET need not require drastic changes in the existing CMOS









process technology. Figure 1.1(a) shows a schematic of such a MOSFET. The thin

channel is sandwiched between the two gates, one of which is buried in the SOI

island. When the properties of both gates (gate workfunction, gate oxide thickness,

and bias) are identical, the device is called a symmetric double-gate (SDG)

MOSFET; otherwise, it is an asymmetric double-gate (ADG) MOSFET. While the

electrical characteristics of the channel of the DG MOSFET are promising, high

source/drain resistance (Rs/D) due to the thin silicon and difficulty in aligning the

two gates cloud this device's future.

An alternate and currently a popular version of the DG device called a

FinFET is shown in Figure 1.1(b), where the device of Figure 1.1(a) is basically

rotated 900. In the FinFET, the gate is "wrapped" over the thin silicon fin that is

extended to isolate the gate from the source and the drain. As the gate is one

continuous piece, the gate misalignment issue is resolved and the extended fin can

be thickened to reduce the high Rs/D as well. For SDG design, the two gates remain

connected and a thicker oxide layer is used on top of the fin to electrically isolate the

top gate from the channel (body). When this is not the case, the device is called a tri-

gate MOSFET [Doy03]. If ADG operation is intended, the top gate is etched off to

isolate the two gates, and the device is called an Independent Gate (IG) FinFET, such

as the MIGFET [Mat04].


1.2 Compact Model for the DG MOSFET

Whatever form of the DG MOSFET is considered (e.g., ADG, SDG, or

IG), for successful advancement of the technology, an accompanying compact model

is a prerequisite. A compact model will allow the circuit designers to examine and
































Gate
/


(b)
Double-Gate MOSFET structures: (a) planar DG structure: body
is sandwiched between the two gates [Den96]; (b) FinFET
structure: the raised source/drain is isolated from the gate by the
thin extension.


Figure 1.1









exploit circuits employing DG MOSFETs. This requires the model to be fast enough

to simulate large blocks of circuits in reasonable times. At the same time, the model

should have sufficient physical basis to allow device engineers to faithfully predict

device performance, as well as to obtain reliable insights on the devices fabricated,

especially when the technology is still in its infancy. A balance between having a fast

and physics-based model is thus imperative; UFDG [Fos04a], a physics/process-

based compact model for DG MOSFETs from the SOI group at the University of

Florida, eloquently maintains the balance. The model is generic in nature, and can be

used for SDG, ADG, and IG MOSFETs, as well as for single-gate fully depleted (FD)

SOI devices.

In UFDG, the 2D Poisson equation (PE) is solved to get the weak-

inversion (WI) characteristics [Yeh96]. The ID PE is combined with the drift-

diffusion current equation to obtain the strong-inversion (SI) characteristics [Chi01],

and the moderate-inversion (MI) characteristics are obtained using polynomial

splines, the coefficients of which are defined by the physical WI and SI solutions at

the MI boundaries. In SI, velocity saturation is accounted for by incorporating a

simplified form of the Boltzman Transport Equation (BTE) [GeOl]. Quantum-

mechanical (QM) effects are incorporated by solving the ID PE and effective-mass

Schrodinger equation (SE) self-consistently [Ge02a]. The SE is solved using a

variational method, and the surface orientation effects are included through properly

defining the effective masses and valley degeneracies. The transport formalism has

a mobility model [Tri05b] that addresses the different scattering mechanisms, and

takes care of thermal injection-limited, or ballistic-like transport. With the









incorporation of all these physical phenomena, UFDG is evolving as an essential tool

for understanding DG MOSFET technology, as well as for predicting circuit

performance, and is now in use in industry and academia alike.


1.3 Dissertation Outline

In this dissertation, we start with applications of UFDG where device

characteristics obtained from industrial collaborators are used to understand and gain

physical insights on UTB DG MOSFET operations by systematically calibrating

UFDG to them, which then leads to necessary upgrades and enhancements of UFDG.

The upgraded model is then used for further calibration, followed by prediction of

circuit performances, and their sensitivity to different process parameters.

Since UFDG is a physics/process-based compact model, its key model

parameters relate directly to device structure and physics. Hence systematic

calibration of UFDG requires knowledge of the DG SOI technology. The model-

calibration methodology, which is similar to that of UFPDB [Chi01], a physics/

process-based PD SOI MOSFET model, includes tuning of particular parameters

based on only a few electrical measurements of devices. The methodology [ChiOl]

is expanded and applied in Chapter 2 for preliminary calibration to contemporary

FinFET data obtained from two industry collaborators, Freescale Semiconductor and

AMD. The insights from the calibrations, along with numerical simulations, are then

used in discussing design issues related to nanoscale FinFETs.

The preliminary UFDG calibrations to FinFETs done in Chapter 2 reveal

new insights into the operation of DG devices, such as different effects of gate-

source/drain underlap in weak and strong inversion that necessitate model









refinements. In Chapter 3, the incorporation of the effects of underlaps in UFDG

formalism is discussed. In WI, the underlaps elongate the effective channel length

(Leff) that determines the SCEs, modeling of which hence becomes critical. After a

brief description of UFDG WI formalism we thus present a simplified yet physical

way of incorporating the effects of underlaps in the WI characteristics. In strong

inversion, the underlap does not contribute to the Leff significantly, however it does

introduce an additional bias-dependent component to the parasitic source/drain

resistance. So, modeling issues and minimizing the effects of such resistance are

discussed as well.

With proper accounting of the effects of underlaps, the refined version of

UFDG, which also has an upgraded QM-based mobility model [Tri05b], is then used

for further calibration to contemporary FinFETs in Chapter 4. The focus now,

however, is on the carrier transport in the channel of the FinFET, rather than on the

electrostatics (as in Chapter 2). Calibration of UFDG to undoped p- and n-channel

DG FinFETs shows very high mobilities in contemporary FinFETs, implying smooth

{110} fin-sidewall surfaces, and giving new insights on electron and hole mobilities

in DG MOSFETs with {110} versus {100} surfaces. The high mobility portends

ballistic transport in nanoscale FinFETs, and indeed simulation of 17.5nm DG

FinFETs by UFDG shows ballistic-like currents. The high mobility and ballistic-like

current indicate low intrinsic channel resistance in FinFET, which indicates FinFET

characteristics could be dominated by the parasitic resistances. The effect of

parasitics on high intrinsic drive current of the FinFET is thus studied, and compared

with that found in bulk-Si devices.









With the needed underlaps in nanoscale FinFETs with undoped UTBs, the

sensitivity of device performance gets an added constraint: the source/drain dopants

in the extension. In bulk-Si technology, the source/drain dopants define virtually

bias-independent gate-source/drain overlap length and parasitic resistance. But in

FinFET, the bias-dependent effects make the sensitivity of device characteristics to

the variations of extension properties, like the lateral source/drain doping profile or

the fin thickness, unique. In Chapter 5, the effects of such variations on circuit

performances like RO delay and static noise margin (SNM) of SRAM are studied

using MEDICI [Med04] and UFDG. In addition, effects of an unintentional dopant

(acceptor/donor) in the channel of an extremely scaled device is studied using the 3D

numerical simulator, Taurus-MEDICI [Tau04].

While Chapters 2-5 are mainly concerned with the electrostatic and

carrier-transport properties in the channel of the DG MOSFET, another important

factor, the gate tunneling current, deserves attention. Indeed, the continual increase

of gate tunneling leakage with scaling is one of the main factors that initiated the

search for a replacement of the bulk-Si MOSFET. It is expected that due to the low

electric field in the SDG MOSFET the gate tunneling current will be less than that in

the bulk-Si device. However, with continuous scaling of the oxide thickness, and the

unclear direction that integration of high-k dielectrics is taking in CMOS technology,

the effects of gate leakage current in SDG MOSFETs requires examination. Besides,

the electric field in the ADG MOSFET, unlike that in SDG devices, is not low, and

hence gate leakage current in the ADG MOSFET can be a serious issue. In Chapter

6, we thus develop a physics-based compact model for gate tunneling current in









generic DG MOSFETs. While all the components of tunneling currents in the

nanoscale FinFET are considered, only the most dominant component, which is the

electron (hole) tunneling current from the conduction (valence) band in the Si of the

nFinFET (pFinFET), is modeled physically. The model is verified with experimental

data obtained from two different groups, and then is used to examine the effects of

tunneling on the static power of scaled DG devices and circuits. The gate leakage

model also necessitated a refinement in the UFDG QM model in weak inversion,

which is described in the Appendix along with other UFDG upgrades that stemmed

from the work of this dissertation.

Finally, Chapter 7 provides a summary of the work done in the

dissertation, along with recommendations for future work.















CHAPTER 2
PHYSICAL INSIGHTS ON DESIGN AND MODELING OF NANOSCALE
FINFETS

2.1 Introduction

The attractive features of the FinFET, like better SCEs, higher ION, etc.,

prompted experimental study of this device and several groups published

encouraging results. For example, we show FinFET SCEs as reported in [Yu02] in

Figure 2.1, where for a gate length (Lg) of 20nm, and fin thickness (tsi) of 17-26nm,

drain-induced barrier lowering (DIBL) as low as 40mV/V and subthreshold slope, S

~ 75mV/decade are observed. While the excellent SCEs observed with Lg/ tsi 1 are

encouraging, from a device-physics perspective the results are perplexing; mere

solution of the PE shows that to have reasonable SCEs (DIBL < 100mV/V, S <

80mV/decade), effective channel length (Leff) has to be more than twice tsi

[Kim01a]. The effective channel length is the length of the channel region, resistance

of which is modulated by the gate, and hence, defines the gate-induced variation of

MOSFET characteristics, i.e., its switching properties. Ideally, Leff should be equal

to the physical gate length, Lg. However, from bulk-Si experience we know that Leff

< Lg due to overlaps or encroachment of the source/drain dopants inside the channel

[Tau98]; hence the results in Figure 2.1 imply some novel features of the FinFET,

including a possible, unique relation of Leff and Lg. In this chapter, we attempt to

calibrate UFDG to the experimental FinFET data to gain insight into the operation of





10









160 .. 160

a -A--NMOS
0 .--A-- PMOS
> 120 120
E t =17-26nm
Si
a)
80 80 E

0
4c 40 40

----
0 0 0
0 20 40 60 80 100

Gate Length (nm)


Figure 2.1 Measured SCEs vs. Lg of CMOS FinFETs, reproduced from [Yu02]. Note
the extraordinary S and DIBL obtained with Lg < 30nm and tsi = 26nm.









these devices, and to explain the surprising experimental observations. Before

discussing the calibration results, we briefly outline the calibration methodology for

UFDG.


2.2 UFDG Calibration Methodology

Because of UFDG's physical basis, UFDG model parameters are known

from process technology, or can be reasonably estimated for initial guesses in the

calibration process. The key UFDG model parameters are listed with their default

values in Table 2.1. For a complete list of the parameters, please refer to the user

guide [Fos05]. Throughout this document, we will show the model parameters in

bold face to differentiate them from the corresponding device variables. The

parameters not listed here are mostly used with their default values obtained from

calibration of earlier-generation SOI technologies [Kris96a], [ChiOl] and have not

changed with scaling.

The evaluation of model parameters starts with setting a preliminary

model card based on the technology information. Model parameters, TOXF, TOXB,

TSI, NBODY, NSD, WKFG, WKBG, SO, along with gate length (L), and width

(W), can be estimated from the process information. However, process variations can

significantly change some of the parameters, like NBODY, TSI, etc. One confusion

common in literature related to DG devices, especially for FinFETs, is the definition

of W (Figure 1.1). In UFDG, the integrated channel charge that naturally includes

bulk inversion [Kim04] is used in calculating the drain current. So, width here for a

FinFET is simply the height of the FET (hsi). The more commonly used 2hsi [Yu02],

which stems from calculating the current for each channel with the factor 2 taking









Table 2.1

Key UFDG model parameters with brief description and default values.

Model Description Unit Default
Parameter

TOXF Front-gate oxide thickness m 3.0x10-9

TOXB Back-gate oxide thickness m 3.0x10-9

TSI Si-film (body/channel) thickness m 10.0x10-9

LES Dynamic source-extension length m 0

LED Dynamic drain-extension length m 0

NBODY Si-film (body/channel) doping density cm-3 1.0x1015

NDS Source/drain doping density cm-3 5.0x1019

WKFG Front-gate work function V 4.6

WKBG Back-gate work function V 4.6

QMX ID effective mass parameter for QM 1

UO Low-field mobility for thick TSI cm2*V-^*s1 1100./190.
(nmos/pmos)

THETA Mobility (surface-roughness model) 1.0
tuning parameter

VSAT Carrier saturated drift velocity cmos-1 7.0x106

VO Velocity overshoot parameter 0

RD Specific drain parasitic resistance ohm*m 0

RS Specific source parasitic resistance ohm*m 0

SO (n-)channel surface-orientation indicator 1
(1: <100>; 2: <110>)

DG Tied-gates indicator 1
(1: Gf and Gb tied; 0: Gf and Gb untied)









care of the two FinFET channels, inherently misses an appropriate accounting of the

contribution of bulk inversion to the drain current.

After setting the preliminary model card, the next step of UFDG

calibration is to calibrate the weak-inversion ID-VG characteristics of the device. The

short-channel effects are defined by the effective channel length (Leff), fin thickness

(tsi) and oxide thickness (tox), along with body doping. In nanoscale FinFETs, the

body is usually undoped and in UFDG Leff is defined by


Leff _Lg-AL (2.1)


where AL is the adjustment, usually positive, due to the gate-source/drain overlap,

represented by model parameter DL in Table 1. So, by matching SCEs like S and

DIBL from the weak-inversion ID-VGS characteristics of nanoscale FinFETs, one can

fine-tune the L, DL, TSI and TOXF/TOXB. Once DIBL and S are matched, the

WKFG/WKBG can be evaluated by matching the off-state current, IOFF. After

evaluating the structural/process-related model parameters from the weak-inversion

calibration, calibration of the linear-region, strong-inversion ID-VGS characteristics

should follow.

At low drain bias there is no velocity overshoot or self-heating effect, so

from the strong-inversion, linear-region characteristics, effective mobility, !eff

(defined solely by model parameter UO and THETA) and parasitic resistances, RS

and RD, can be extracted precisely. However, as RS/RD can effect the extracted

mobility, calibrating the ID-VGS characteristics directly will not yield an accurate

effective mobility, especially for a short-channel device. To avoid this, we will









calibrate gm/ID2, which is nearly independent of RS/RD [Ghi88], [Kri96]. The total

on-state resistance, RON, in the linear region can be expressed as


VDS RS + RD Leff
R + (2.2)
ON ID W 2WCof(VGS Vt).eff(UO, THETA) (2


where W, Cof, VGS, and Vt are width, gate capacitance, gate bias and threshold

voltage, respectively. The equation is written for symmetric double-gate MOSFETs,

but a similar equation can be used for asymmetric DG MOSFETs or bulk MOSFETs

as well, by properly changing the gate capacitance value. Differentiating both sides

of (2.2) with respect to gate bias, and assuming (VGS ID RS / W) = VGS, we observe

that gm/ID2 is independent of RS/RD. So, by calibrating gm/ID2 in strong inversion

at low VDS the model parameters UO and THETA can be evaluated uniquely.

Evaluating RS and RD then becomes straightforward, and can be obtained by simply

forcing the model prediction to match the linear region current. (Application of this

calibration methodology is illustrated in Chapter 4.)

The strong-inversion, saturation-region calibration can be done by tuning

VO, VSAT and SELFT in an iterative manner to match ID-VD characteristics.

Because of the complex inter-dependence of self-heating on channel current, it's

difficult to separate out thermal resistance and capacitances (turned on by SELFT)

from velocity-overshoot effects (tuned by VO). However, experience with PDSOI

devices show calibration in the above manner is usually effective and less time

consuming [ChiOl].

The accounting for QM effects, which are gaining importance in short-

channel devices, classical or non-classical CMOS alike, in UFDG usually does not









need any tuning parameter even though to take care of the uncertainties in effective

masses, two model parameters QMX and QMD are left as tunable. However, except

for holes in {110} Si, the default values of these two parameters accurately predict

the QM effects due to solving the PE and the SE in a self consistent manner [Ge02a].

As the effective masses of holes in {110}-p Si are not conclusively known, the above

two parameters require tuning for { 110}-p Si. For this purpose, calibration of C-V

characteristics is required. The C-V characteristics can also be used to extract

TOXF/TOXB; however the advanced gate oxidation process can yield gate thickness

with 10% accuracy. For example, if the designed gate oxide is Inm thick, the

maximum variation observed in the thickness after fabrication is +A. As FinFETs

are left undoped, such small variation in oxide thickness is not reflected in short-

channel characteristics (unlike bulk-Si technology, where large depletion charge,

QD, makes the threshold voltage sensitive to tox through QD/Cox). So, for FinFETs,

getting the oxide thickness from the designed value is sufficient, and calibration to

simple ID-VG and ID-VD characteristics are enough to evaluate most of the other

UFDG model parameters. However, as UFDG does not model polysilicon depletion

in the gate, the process is more accurate for metal gate technology, which is the only

viable option for undoped-UTB DG MOSFETs.

With the calibration methodology outlined above, in the next few sections

we will present some calibrations of UFDG to both n- and p-channel FinFETs along

with insights therefrom.









2.3 Calibration of UFDG to AMD nFinFETs

We start our calibration with an AMD fabricated FinFET [Yu02] of Lg

105nm. The body of the device is left undoped and S/D fin extension is doped by 0-

tilt ion implantation with gate sidewall spacers. The fin thickness varies from 17nm

to 26nm, and the extension lengths are of 80nm each. The nitrided gate oxide is 17A

thick with poly silicon used as gate material. The UFDG calibration results are shown

in Figure 2.2. Even though a good match in weak-inversion characteristics,

subthreshold slope and off-state current, is obtained for Leff = 135nm, which is 30nm

longer than Lg, the strong-inversion characteristics are not predicted well. Thus,

UFDG calibration is only 'partial'. In Figure 2.2(b), the strong-inversion calibration

result is shown. With extraordinarily high RS/RD, UFDG predicts the saturation-

region characteristics well but underestimates the linear-region current. Although the

calibration result in Figure 2.2 is far from perfect, we get two valuable insights from

the calibration effort; one is that the effective channel length in the fabricated device

is longer than the physical gate length, and the other is that the source/drain

resistance (Rs/D) is very high and may be bias-dependent making it impossible to

match both linear and saturation-region currents with a constant RS/RD.

In Figure 2.3, we show UFDG calibration results for a shorter-channel-

length device. Again, we find it difficult to match ID(VGS) in all the regions with

constant RS/RD; moreover, in the shorter-channel-length device we observe strong-

inversion Leff, Leff(st) > Lg as well, but it is not equal to weak-inversion Leff, Leff(wk)-

The observation is in contradiction to that typically observed in bulk-Si technology

where Leff < Lg due to the diffusion of source/drain dopants into the channel. The




















10-8

10-9 o VDS=0.1V measured data
VDS=1.2V measured data
10-10 UFDG (Leff=135nm; RD=Rs=200 Q-im)

10-11

10 12
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2
VGS (V)
(a)
1 0 -4 ............ ..... ... .. .

10-5
.,- ,nooooooooooooooooooooooooooo0 1
10-6

10-7

10-9

10-9 o VDS=0. 1V measured data
VDS=1.2V measured data
10-10 / UFDG (Leff=105nm; RD=Rs=675 Qn-im)

10-11 0o
10-n y
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2
VGS (V)
(b)
Figure 2.2 Partial UFDG calibration to an Lg = 105nm nFinFET; tsi = 26nm. In (a)
with Leff = Lg + 30nm, the measured weak-inversion ID-VGS
characteristics are predicted well, but the strong-inversion curves are not.
In (b) with Lff = Lg, and very high, but constant S/D series resistance, the
measured high-VDs strong-inversion ID-VGS characteristic is predicted
well, but the low-VDS and weak-inversion curves are not.
























10-6








10 o VDS=O.1V measured data

VDs=1.2V measured data

10-10o -- UFDG (RD=100 n-im, Rs=550 n--im)


-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2

VGS (V)



Figure 2.3 Partial UFDG calibration to an Lg = 17.5nm nFinFET; tsi = 17nm. With
Leff = Lg + 26.5nm, the measured weak-inversion ID-VGS characteristics
are predicted well; with shorter Leff = Lg + 12.0nm (-2)), and very high
source series resistance but low drain resistance, the strong-inversion
curves are predicted reasonably well.









explanation of Leff > Lg observed here lies also in the diffusion of source/drain

dopants in the channel, however, this time it is due to the lack of it. In FinFET

technology, as mentioned earlier, the extensions (Figure 1.1(b)) are not doped

directly, rather the ion implanted source/drain dopants are annealed to diffuse them

inside the extensions. Apparently, the diffusion is not controlled well enough and an

insufficient number of source/drain dopants (NsD) reach the gate edges leaving the

extensions near the gate edges practically undoped. Because of the undoped body and

the lightly doped/undoped extensions, the Debye screening length (kD) in such

FinFETs is long, and gate modulation extends beyond the channel in weak inversion,

resulting an Leff, defined as the length over which the gate modulates the carrier,

longer than Lg. As the channel carrier concentration increases with gate bias, kD

decreases, and carriers beneath the gate screen the carriers in the extensions from the

gate-induced electric field. Thus, the Leff shrinks in SI, and hence, even though

Leff(st) > Lg, Leff(st) < Leff(wk) as found in Figure 2.3.

In strong inversion, besides slightly elongating the effective channel

length, the lightly doped portion of the extension also increases the series resistance

as evident in the high RS/RD obtained in Figure 2.3. However, the uniqueness of this

component of parasitic resistance comes from the variation of carrier concentration

inside the extension by gate bias, which gives rise to bias dependence of the noted

Rs/D and renders prediction of strong-inversion current with constant RS/RD

ineffective.









2.4 Calibration of UFDG to Freescale Poly-Gate nFinFETs

To further corroborate and generalize our insights from AMD FinFET

calibration we employed UFDG to calibrate FinFETs fabricated at Freescale

Semiconductor. In these devices, the extensions are of 100nm each, physical gate

length is 100nm, and from TEM measurements fin thickness is found to be 30nm.

The calibration results are shown in Figure 2.4. The weak-inversion characteristics

are predicted well with DL = -18nm, i.e., Leff(wk) > Lg. The fin thickness is found to

be 32nm, 2nm thicker than that is found in TEM measurement. The gate work

function inferred from the calibration results in a poly doping density of- 4 x 1018

cm3, which is significantly less than what is observed in bulk-Si technology. Also

the gate-induced drain leakage (GIDL), a common feature in devices with overlaps,

is absent in the I-V characteristics of Figure 2.4, which is consistent with the negative

DL found from the calibration that indicates instead of overlaps these devices have

underlaps.

In strong inversion, this time around we tried to observe the evolution of

RS/RD with gate and drain biases by incrementally matching the UFDG prediction

with the data as shown in Figure 2.4(b). We find that with the increase of gate bias

in the linear region, RS/RD gradually decreases due to the fact that an increase of

gate bias increases carrier concentration in the underlap regions. At high drain bias,

a constant RS/RD results in a good match, indicating a saturation of carriers in the

underlap regions. Note that while RS reduces both the effective gate and drain bias,

RD only reduces the effective drain bias, and as long as RD is not high enough to











1 0 -3 ........ ,.................. .........,..

10-4

10-5

10-6

10-7 r

10-8

10-9

10-10

10-11

10-12 ...........................
-0.5 -0.3 -0.1


10-9

10-10

10-11


10-12 1L.
-0.5


0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5
VGS (V)


-0.3 -0.1 0.1 0.3 0.5

VGS (V)


0.7 0.9 1.1 1.3 1.5


Figure 2.4 Partial UFDG calibration to an Lg = 100nm nFinFET; tsi = 32nm, and
tox=2.47nm. (a) Good match in weak inversion is obtained with DL = -
18nm, and (b) the strong-inversion characteristics are predicted well with
bias-dependent parasitic resistance.









drive the channel out of saturation, the saturation region current is independent of

RD. The asymmetric RS and RD found from the calibration thus are not necessarily

physical. Due to the process symmetry, it is more likely that RS = RD in all bias

regions. Also, there is a bit of uncertainty in the magnitudes of RS/D as there might

be poly-depletion-induced degradation of the channel current. However, poly-

depletion effects do not undermine our RS/D(VGS) conclusions deduced here. Poly-

depletion effect reduces ID, and it gets worse with increasing VGS [Tau98]. Hence,

replicating poly-depletion effect with RS/D will require increasing Rs/D with gate

bias, which is not the case observed in Figure 2.4(b). So, the trend of RS/D(VGS)

observed here is due to the noted underlaps, and the poly-depletion could only affect

the quantitative interpretation of RS/D(VGS).


2.5 Calibration of UFDG to Freescale Metal-Gate pFinFETs

In Figure 2.5 and Figure 2.6 calibration results of UFDG to Freescale's

metal gate p-channel FinFETs are shown. The gate is TiN and SiON is used as gate

oxide in the devices studied. The calibrations are done starting from long-channel

devices from which transport parameters are obtained and used for the shorter-

channel one, where RS/RD needed tuning to get the strong-inversion calibration.

None of the devices have significant SCEs, and the only adjustment needed in weak

inversion is for the threshold voltage, which is done by tuning the gate work function.

Variation of the TiN gate work function (OM), obtained from the

calibration with Lg, is shown in Figure 2.7. We find that with decreasing Lg, (M

increases. For the shorter-Lg FET, we find OM 4.6eV, and for the longer-Lg ones,


















10-6 '. -1.2V .Data 10-6 Data
-- UFDG V DS -0.1 UFDG
VDS -0.1 L=10 tm, L=I tm,
108 DL=0, TSI=25 nm, 108 DL=0, TSI=25 nm,
UO275 cm2/Vs, UO=275 cm2/Vs,

10-10 1-010-10


10-12 10-12


101 4 ....................... 1014
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2
VGS (V) VGS (V)

(a) (b)


10-4 10-4
S* -1.2 1.2
10-6 106 VDS =-0.1
VDS --0.1V

, 108 10
- D. Data
a 0
S-Data \ -1 UFDG
1000 UFDG 10\
UFDG L=0.105 gm,
L=0.24 gm, DL=-14nm,
102 DL=0, TSI=25 nm, 112 TSI=25 nm,
UO=275 cm2/Vs, \ :: 107 UO=275 cm2/Vs,
RS=RD=450 RS= RD=550
10 14 1..... .... ...... .. .... .. ..... ..... ...... 10-14
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2
VGS (V) VGS (V)

(c) (d)


Figure 2.5 Calibration of UFDG to metal-gate pFinFETs with gate length of (a) 10pm,
(b) 1pm, (c) 0.24pm, and (d) 0.105pm. All the FinFETs have hsi = 90mn,
tox = 2nm. Key UFDG model parameters are shown in the figure.


IIII





















10-4 Rs=RD=950
S-1.2V


10-6 VDS =-0.1V



10- -


Data
10 UFDG: Leff 97nm
tsi=25nm



10-12




-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2
VGS (V)


Figure 2.6 Calibration of UFDG to a 75nm metal-gate pFinFET. Good match in both
the weak- and strong-inversion characteristics is obtained with a high Rs/

D and UO = 275cm2/Vs. The nonzero ID for VGS > 0.0V is due to gate
leakage current.

























4.65



4.60 -Mid-gap gate



4.55



4.50



4.45



4.40 .............I.. I I ........
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
L_drawn (pm)


Figure 2.7 Variation of TiN gate work function ( evaluated from UFDG calibration described in Figure 2.5 and Figure 2.6.
For this technology, Ldrawn = Lg + 10nm1. The mid-gap gate work
function is shown in the dashed line.


1. L. Mathew, private communication, Freescale Semiconductor Inc, 2005.









bM ~ 4.4eV. The findings are consistent with the observations in [Yag98], where it

was found that the crystal orientation of TiN varies with the gate length, and for

shorter channel length the sputtered TiN has a predominant (100) orientation,

whereas for longer channel lengths both (111) and (100) orientations are present. The

(100) TiN has a work function of 4.6eV. For the (111) TiN it is 4.3 4.4eV. So, in

shorter-Lg devices, the TiN work function it will be -4.6eV and will be less in the

longer-gate-length devices, as observed in Figure 2.7.

Note that like the nFinFETs, the pFinFETs here also have negative DL as

found from the calibrations to the shorter-Lg devices, and high RS/D. For example,

the shortest gate length studied here, Lg = 75nm, (Figure 2.6) has DL = -22nm.

However, the parasitic resistance is unusually high (RS = 950Q-jpm) compared to

that found in the AMD devices or the Freescale poly-gate nFinFETs. This could be

due in part to the lower mobility of holes, and the lesser number of dopants in the

extensions compared to that in nFinFETs, and/or due to the unoptimized contact

formation process.


2.6 Device Design Implications

Our calibration of FinFETs fabricated in two different plants shows the

presence of underlap instead of overlap in these devices. As the channel is undoped,

excessive extension doping measures have to be avoided to prevent 'punch-through',

thus underlap might be a common feature in nanoscale FinFETs. To explore the

effects of underlaps on device design, we use the 2D numerical simulator MEDICI

[MED04] to simulate the idealized structure in Figure 2.8. The structure is idealized

in the sense that we assume there are no dopants in the G-S/D underlap regions (Les/





















toxf Source Front Gate Drain
Exte ion Extension

tSi Body


oxb Back Gate

Le ~ Lg Le



Figure 2.8 Schematic cross section (top view) of the undoped FinFET used in the
MEDICI simulations. The undoped portion of the source (drain) extension
is defined as Les (LeD). The devices simulated in this section have mid-
gap gates with Lg = 18nm, tsi = 10nm, toxf = toxb = tox = Inm, unless stated
otherwise.









D), and NSD(y) goes abruptly to zero in the extension. Energy quantization effects

were turned off during the simulation. The default structure is chosen following the

ITRS 32nm node MOS structure [ITR03], with Lg = 18nm, toxf = toxb = Inm.

Figure 2.9 shows the effects of increasing underlaps on (a) subthreshold

swing, S, and (b) on gate work function, (M, when IOFF is fixed at 0. IpA/pm. As the

underlap length increases, the effective channel length increases, which decreases

SCEs, and hence S decreases. Also evident in Figure 2.9(a) is (i) that the introduction

of underlaps can relax the fin thickness requirements and (ii) that the decrease of S

ceases once Les/LeD > 5nm. For example, for S = 85mV/decade, the required tsi =

10nm, with Les/LeD = 0. However, if Les = LeD = 5nm, the same S can be obtained

with a thicker fin, tsi = 15nm. Similar conclusions can be made for DIBL as well, as

SCEs like S and DIBL vary with tSitox/Leff (to first order), for reasonable short-

channel effects [KimOla]. So, any increase in the effective channel length will allow

relaxation oftsi or tox. As it is difficult to fabricate thin films reliably, underlaps will

be a welcome addition to viable FinFET technology. For longer underlap lengths,

SCEs are insensitive to Les/LeD (hence, Leff), as for such cases, the coupling of two

gates defined by the fin thickness determines the control of SCEs. Hence we note in

Figure 2.9(a) that for longer underlap lengths S is almost independent of Les.

The variations of (M in Figure 2.9(b) also illustrate that another

advantage of introducing underlap in FinFET is that it widens the acceptable range

of (M. The prominent gate materials in consideration for FinFET technology are

nitrides of Ti and Ta. The choice of nitrogen concentrations in both the gate [Wak01]

and the underlying SiON determines the work function of the gate. The use of

















U LSi -- IJIIIII
-3
o 100 L= 18nm
S9 toxf toxb = lnm nm









0.0 5.0 10.0 15.0
LeS = LeD (nm)

(a)
4.70 1


4.65 OFF = 100nA/pm

Lg= 18nm, tsi = lOnm
4.60 toxf = toxb nm
4.60 -


4.55


4.50


4.450.0 2.0 4.0 6.0 8.0 10.0

Les = LeD (nm)
(b)


Figure 2.9 Effects of underlaps on the subthreshold characteristics of a FinFET
illustrated by the IMEDICI-predicted variation of (a) subthreshold swing,
and (b) gate work function required to maintain a constant off-state current
with varying underlap lengths.









underlaps thus can add flexibility in the choice of needed nitrogen concentration in

the gate or in the SiON.

In Figure 2.10, the variation of ION and IOFF with Les/LeD is shown.

Increasing the underlap lengths increases Leff, which reduces the SCEs and hence

IOFF decreases exponentially. On the other hand, increasing the underlap lengths

increases RS/D and ION decreases too. Note that for Les = LeD < 4nm, increase of IOFF

is abrupt and such sensitivity will prevent reliable design with Les/LeD shorter than

4nm. On the other hand, longer underlap lengths increase the resistance, and have a

diminishing effect on SCEs. Hence, from Figure 2.9(a) and Figure 2.10, we conclude

that the range of useful underlap lengths for the FinFETs considered here is 4- 6nm.

Indeed, a pragmatic FinFET design, with a Gaussian source/drain doping profile,

proposed in [Tri05a], shows that an optimum 18nm FinFET should have 4.5nm of

underlap on each side of the gates. Further discussion on such pragmatic design will

be presented in Chapter 5.

Note that we refrain from taking any quantitative interpretation of

ION(Les/LeD) in Figure 2.10. The transport models in MEDICI that are appropriate

for bulk-Si are not calibrated for thin-body FinFETs and hence, while the effects of

parasitic resistances will be reflected properly in MEDICI predictions, uncertainty in

the MEDICI channel mobility/velocity saturation model will introduce uncertainties

in the predicted ION, thus IoN(LeS/LeD) in Figure 2.10 should only be interpreted in

qualitative terms.

Figure 2.11 shows the effects of asymmetric underlaps on device

performance. In Figure 2.1 l(a) the variations of DIBL and S are shown for increasing

























10-7





10-8





9 10-9

10


10-10





10-11 I
0.0 5.0 10.0
Les=LeD (nm)




Figure 2.10 VMEDICI-predicted variation of ION and IOFF of tl
Figure 2.8 with underlap lengths LS/D; VDD = 1.2V.


-2.0

1.8

1.6

1.4

1.2 0

1.0

0.8

0.6

0.4

0.2

0.0
15.0


ie FinFET defined in


































5 10 15 20 25
Les (nm)
(a)


0 5 10 15 20 25
Les (nm)
(b)


Figure 2.11


MEDICI-predicted variation of FinFET performance, (a) SCEs, and (b)
ION/IOFF, with the position of the gate in the extension. Simulation is done
by keeping the total extension length, Les+LeD constant. Inset in (a) shows
the variation of threshold voltage when the gate is moved away from the
center (i.e, when Les = LeD = 13nm).


80

I

1
78



76
C

&-
74



72



70




2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0









Les for a constant Les+LeD = 26nm. For Les = LeD = 13nm, i.e., when the gate is in

the middle with symmetric underlaps on both sides, DIBL and S are minimum.

Subthreshold slope, which is defined by Leff, and does not depend on the gate

position, except when the gate is very near the source/drain, and spilled-over

electrons from source/drain reduce gate control by creating an G-S/D overlap region

like that in the bulk-Si devices (the difference between the overlap region in the bulk-

Si device and the FinFET in Figure 2.1 l(a) is that in the bulk-Si MOSFET the overlap

region is due to the encroachment of S/D dopants, where as for the FinFET is due to

the spilled-over mobile carriers from S/D). Similarly, the off state current in Figure

2.11(b) also remains relatively constant with the gate position. The on-state current,

however, is maximum when the gate is near the source, understandably so, as the

smaller Les, the less the reduction of effective gate bias by Res, the resistance due to

Les. The optimum FinFETs, thus, should have Les > LeD.


2.7 Summary

We have presented insights from calibrations of UFDG to FinFET data

that explain the good short-channel effects observed in data with Lg tsi. The

calibration results show that the G-S/D underlap in the nanoscale FinFETs elongates

Leff and introduces a bias-dependent component in the parasitic RS/D. We also found

that due to the underlaps, GIDL is absent in the FinFET.

Design issues with the underlaps were explored through numerical

simulations, which show that longer LeS/D is needed to minimize IOFF sensitivity to

LeS/D variations (consistent with the finding that to get good SCEs Leff > 2tsi

[Yan05]). Conversely, to keep the resistance low, Les/LeD should be minimum. The









advantage of underlaps in relaxing the fin thickness and the gate work function

requirement was illustrated. Also, probable FinFET design with asymmetric

underlaps was discussed, and it was concluded that having a longer underlap length

in the drain side is optimum, as shorter underlap length in the source side reduces the

reduction of effective gate bias due to the resistive drop across the underlap.

The calibration results also pointed out some required upgrades in UFDG,

namely modeling of bias-dependent Leff and Rs/D due to underlaps. In the next

chapter, we will deal with such modeling issues, as well as further applications of

UFDG, with the effects of underlaps incorporated.















CHAPTER 3
UFDG UPGRADES FOR NANOSCALE FINFETS WITH UNDERLAPS

3.1 Introduction

As observed in the previous chapter, the presence of gate-source/drain

underlap, with an undoped UTB, introduces variation of the gate-controlled area with

bias that gives rise to a bias-dependent effective channel length, and adds a non-

ohmic component to the parasitic resistance of the FinFET. In this chapter, our focus

will be on the analysis and UFDG modeling of such novel features and their effects

on FinFET characteristics in both weak and strong inversion. The weak-inversion

discussion will be concerned with a modification of the weak-inversion current

formalism that is compatible with compact models, while the strong-inversion

discussion will center around the properties of the parasitic resistances.

In a compact model for a MOSFET, the weak-inversion current is

calculated neglecting drift current, and the potential profile in the channel is obtained

by solving the 2D Poisson equation (PE) using the depletion approximation. For the

FinFET, the gate-controlled region extends beyond the channel and presents

different boundary conditions for the PE, which requires extension of the compact

model developed for conventional DG MOSFETs. Hence, we first check the

applicability of UFDG for predicting weak-inversion characteristics of nanoscale

FinFETs, and then the required model upgrades will be presented. Before delving

into the FinFET weak-inversion characteristics, we first briefly review the weak-

inversion current model in UFDG.









3.2 Calculation of Weak-Inversion Current in UFDG

3.2.1 Review of Weak-Inversion Current Model in UFDG

UFDG solves the PE in weak inversion assuming negligible carriers in the

channel [Yeh96]. The effective channel length Leff in the model is the length over

which the solution of PE is sought. In DG MOSFETs, Leff is defined by (2.1), where

the channel within Leff is completely covered by the gate. The 2D PE,


a2 a2 qNA
2 (x, y) + 24(x, y) (3.1)
dx dy s


with the potential ) referenced to a hypothetical neutral body, is subjected to the

boundary conditions shown in the schematic cross-section of a DG MOSFET in

Figure 3.1(a). The channel is surrounded by the gate in the transverse direction, and

by the highly doped source and drain in the lateral direction. With the gate over the

entire effective channel length, the boundary conditions in the transverse direction

are clearly defined by the gate-induced electric fields,


Seox sf6y) (VGfJ- V FBf)
0 = _E (y)= f ) FB) (3.2)
xix =0 sf a t
=s oxf

SE ox (VGbS- FBb) sb
0 I = -E ,(y)=- --------
= tsi s oxb


where VGf/bS is the front/back gate bias, eox/s is the oxide/silicon dielectric constant,

VFBf/b is the flat-band voltage of the front/back gate, Esf/b is the front/back surface

the electric field, and {sf/b is the front/back surface potential. In the lateral direction,

the boundary conditions are defined by the source/drain-channel built-in potential.

The inherent assumption here is that source/drain doping is infinite (i.e., the potential
















Front Gate


Esf(y)



Channel


- AL/2


(O,Leff)

y


AL/2



(0,0)







Ct .

(tsiO)
1 V-


Front Gate


Esf(y)



Channel

(ii)
Esb(y)


Back Gate


LeD
I I


I I
(O,LeffLeD)
f (0Leff)
y
I 7
-e-
+ v
< .

'(iii)

] (tsi,Leff)


Figure 3.1 Boundaries for the solution of Poisson's equation in the DG MOSFET. (a)
In a conventional DG MOSFET the boundary conditions are well defined
on all four sides by (3.2) and (3.3). (b) In an undoped-UTB FinFET, with
undoped extensions as part of the channel (of length LeS, and LeD), the
boundary conditions are not well defined. From y = Les to Les+Lg, the
electric fields are easily obtained from (3.2), but from y = 0 to Les, or y =
(Leff LeD) to Leff, the electric fields come from the fringing effect of the
gates that complicate the solutions of PE inside the box [(0,0);(tsi,Leff)].


Leff No

Esb(y)
S(tsi,Leff)
Back Gate


( I -
(0,Les)
Kk7F


(0,0)







(t0i

(tsiO)


- --'- Y


I eSI








drop across the quasi-neutral S/D region is neglected), which gives a bias-

independent potential at the boundary and defines the boundary values for the PE in

the y direction as


Y(x, 0)= b (3.3)
Y(x, L)= b + VDS.


A solution of (3.1) subject to the boundary conditions in (3.2) and (3.3) is

[Yeh96],


(x,y) sinh(yL )[(K + b + VDS)sinh(yy) + (K + b)sinh(y(Leff-y))] -K (3.4)
eff


Here, y is the constant (in y) inverse length scale, which indicates the severeness of

the SCEs in the channel at any x, and is given as


+ C of+ C of
2yO Co C
y(x) = 2 ; oo = (35)
I +x of 2 2 o
s o-x Yb Cb


Also in (3.4), K is the ID potential, found from the solution of the ID PE in the

vertical direction and is related to the gate biases as



K =y C(VFBb VGbS)-B(VGS- VFBbf 2+ (3.6)
[C("Fb "O 2e


where the structure-dependent constants are defined as










B = B +y2(-x) Cf+ B x2; B0
BBs o


C C
Cof + Cof
Cob Cb

tb 1+ b


C (1+(x)2); C tb21+2 -1
C = Co(I + (Yx)2 c = tb2 1 +--2COf


(3.8)


The minimum potential along y at any x, Om(x), is obtained by solving for

y = ym such that the lateral electric field is zero. From (3.4) we find Ey andym as


= sinh(Lff) [( b + VDS)cosh(yy) -(K + )b)COsh(y(Leff- ))]



y atanh 1 K + b+VDS tanh(yL eff)
m y cosh(yLeff) +b e


(3.9)



(3.10)


We note that, when VDS = 0, ym = Leff/2. Once the minimum potential, Om is found,

the diffusion length, Le in the channel is calculated by,


with


Le Leff LS- LD





L 2[1b m- m
L S y = 0
a =


(3.11)






(3.12)


and


and


(3.7)









2[,b m + VDS] (3.13)

y=L
Iy= Leff


In (3.12) and (3.13), the lengths Ls and LD refer to the depletion lengths inside the

channel near the source and drain, respectively, as illustrated in Figure 3.2. The

channel current is assumed to be due to diffusion only, and is approximated as



Iwk qD 1-exp -DS (3.14)


Here, Q(Ls) is the integrated carrier density at the virtual source and is exponentially

dependent on om [Yeh96]; q, VT, Dn, are electron charge, thermal voltage and

diffusion length, respectively. So, the current is mainly dependent on two variables,

exponentially on (m and linearly on Le 1. In UFDG, the channel is separated into

multiple strips along x, and (3.14) is used to calculate the current in each strip

[Tri05b]. The total current is then obtained by summing up the contributions of all

the strips.


3.2.2 Source/Drain-Body Junction Potential

There are few assumptions in the above model for the weak-inversion

current in DG MOSFET. One is the boundary condition (3.3), which says the

potential at y = 0 is fixed at Ob, assumed to be the built-in potential Vbi and

approximated as (for a p-type body),


E U N
b + kT- n (3.15)
b- 2 q n



































Figure 3.2 Lateral potential profile in weak inversion in the channel of a typical DG
MOSFET. The diffusion length Le is obtained by subtracting Ls and LD,
which are calculated by extrapolating the electric fields at the source/
channel (y = 0) and drain/channel (y = Leff) boundaries, from Leff.









i.e., the model assumes the Fermi level in the source is aligned with the source

conduction band. In (3.15), Eg is the silicon band gap, ni is the intrinsic carrier

concentration, and k is the Boltzman constant. For a typical doping density of

1x1020cm-3, b can be 2kT/q higher than that predicted by (3.15) if Fermi-Dirac

(F-D) statistics are used. Besides the inherent approximation of Maxwell-Boltzman

(M-B) statistics, (3.15) also assumes that there is no spatial variation of carrier

density inside the source/drain. In reality, however, there will always be some

carriers spilling over into the undoped channel from the source, and the potential

profile in the source will be a function of gate length, film thickness, and biases. A

typical profile of )(y) across the source-channel boundary is plotted in Figure 3.3

showing the deviation of b from Vbi, the potential inside the source where the carrier

density equals the doping density. The inaccuracy, if any, introduced by the

assumption in (3.15) that b = Vbi needs examination before we incorporate the

effects of G-S/D underlap.

To estimate the potential at the source-body junction accurately, one needs

to solve the ID PE inside the source,


2
d2 (ns- N) ,(3.16)
dy s


where ND is the source doping density and ns is electron concentration in the source.

In near-equilibrium, for an undoped body, ns can be expressed assuming M-B

statistics as [Tau98],



n iexp (3.17)
























O(y)


y

Figure 3.3 Schematic of variation of lateral potential (solid line) across the source-
channel boundary in a FinFET with abrupt doping profile (dashed line).
Due to finite depletion layer inside the source, (b < Vbi.









Using (3.17) in (3.16) we find,


d2 qND( Vbi)
2- Iexp -1 (3.18)
dy2 T


where Vbi is the ) where n = ND. Integrating (3.18) once, and using = o at y = -ys,
dy
we get


d4 2 qV'ND ( i' b
(d j xP V 1 bi (3.19)
dy) s -T ) VT )



At the boundary (y = 0), the electric field and potential are continuous, so

solutions of (3.1) and (3.16) are nearly the same there. Thus equating (3.9) and (3.19)

at y = 0 we can get a refined expression for Ob, but the solution requires numerical

evaluation. A simpler way is to employ the depletion approximation inside the source

and neglect ns in (3.16). Then the potential at the boundary, in terms of the electric

field, is


c E2
bb =bi 2qN (3.20)


Eb is the electric field at y = 0 and can be approximated from (3.9) for low VDS as



Eb y(K + b)tanh( (3.21)


Replacing Eb in (3.20) by (3.21), and solving the resultant quadratic equation we get

ab as









b 2 [- (2aK + 1)+ J(4K + 4Cbi + 1)] (3.22)
22a


where a = 2-tanh -f is a constant in y, and relates the dependence of b on the

device parameters, i.e., ND, Leff, and tsi. Note that in (3.22), Ob depends on the gate

bias through K, but the variation is negligible in the weak-inversion region.

Figure 3.4 shows the variation of Ob from (3.22) with tsi and Lg. As is

evident, Ob is independent of Lg until the length becomes too small, and punch-

through increases the density of carriers in the channel (and at the boundary,

increasing b). With decreasing tsi, Ob decreases as thinner tsi enhances gate control

reducing SCEs. In other words, in the 2D PE, E = -(+ ), the gradient of the

electric field along x increases with decreasing tsi, and thus decreases n (so too does

0 through (3.17)), for a constant gate length and drain bias. The prediction of (3.22)

is in good agreement with that of MEDICI, as shown in the figure, except for thin

films, where in the middle of the film the assumed depletion approximation is

inaccurate. Also in the figure, the variation of 0b with a is shown in the inset. As a

goes to zero (which can happen when ND -) oo), 0b approaches Vbi as assumed in

(3.3). Note that for a pragmatic FinFET having tsi > 8nm, undoped body, and Leff (=

Lg here) > 2tsi, Ob is around 0.55 V in Figure 3.5, as will be predicted by (3.15), 0b

SEg/2 = 0.55V.

The prediction by (3.15) is close because the deviation of b from Vbi is

compensated by the use of M-B statistics (instead of F-D statistics), which

underestimates the actual potential for source doping 1x1020 cm-3. So, use of (3.15)


















Lg (nm)
0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0


0.60


0.55


0.50


0.45


Q 0.40
-e-

0.35


0.30


0.25


0.20 I
0.0


5.0 10.0
tsi (nm)


15.0


Figure 3.4 Comparison of the variation of boundary potential as a function of film
thickness (tsi), and gate length (Lg) as modeled by (3.22) with that of
MEDICI. For the first case Lg is set to 18nm and for the latter tsi = 10 nm
is used. VGfS = VGbS = 0, WKF = WKB = 0, VDS = 50mV, toxf = toxb =

Inm, ND = 1x1020cm-3, and NA=1.3x1010cm-3 are used. Inset shows the
variation of Ob with a in (3.22); as a -- 0, b --- Vbi-









works fine for typical FinFETs, although it does not capture the dependence of Ob on

structural parameters. (In the next section, introduction of a new parameter SCEB

will be discussed, which will help in removing the uncertainties introduced by (3.15),

particularly for undoped UTBs.)


3.2.3 Weak-Inversion Model Verification for DG MOSFET

Figure 3.5(a) shows the calibration of the UFDG weak-inversion model to

MEDICI-simulated DG-MOSFET characteristics. The excellent match corroborates

the model validity for DG MOSFETs. Figure 3.5(b) shows the comparison of UFDG-

predicted 0(y) with that of MEDICI for the same device. Note that both the curves

have identical (m and will yield identical Le. Because the weak-inversion current is

mainly dependent on these two parameters, ym, and Le, as long as the calculation of

these two are correct in (3.14), UFDG-predicted channel currents, and hence SCEs,

will be valid. For conventional DG MOSFETs such accuracy in determining (m and

Le is obtainable by using the exact physical parameters directly in the model.

But for the undoped-UTB FinFET the model is not directly applicable

since the boundary condition in solving the PE is different. Figure 3.1(b) shows the

boundaries within which the solution of the PE is sought. While the boundaries in the

y direction are still well defined, the boundaries along the x direction in the

extensions are defined by the fringing fields from the gates, which invalidate the use

of (3.2) there. An exact solution for such a system will involve solving PE in regions

(i), (ii) and (iii) in Figure 3.1(b) and equating the solutions at the boundaries of

region (i) and (ii), and (ii) and (iii). Such an exact approach is complex and not

favorable for compact models. As an alternative, we employ our insight from UFDG










10-3

VDS=1.0V
10-5

50mV
10-7


H 10-9



10-11n MEDICI
-- UFDG

10-13
-0.2 -0.1 0.0 0.1 0.2 0.3 0.4
VGS (V)
(a)
0.8

0.7 V DS = 50mV

0.6 o****oooo *,OO
0
0.5

S0.4

0.3

0.2
M MEDICI
0.1 -- UFDG

0 .0 . ... .... .. .... .
35 40 45 50 55 60 65 70 75 80
y (nm)
(b)
Figure 3.5 Comparison of UFDG predictions with that of MEDICI in weak
inversion, (a) ID-VGS characteristics, and (b) potential (0) along the
channel at x = tsi/2. The device is an undoped, mid-gap DG MOSFET
with Lg = 18nm, tsi = 7nm, and toxf toxb = Inm. The relevant UFDG
model parameters are WKF = WKB = -0.007, NSD = 1x1020cm-3, DL =
-0.4nm, and NBODY = 1.3x1010cm3. For (b) the gate bias is fixed at OV
Note that in (a) the DL needed is nonzero, due to the uncertainty in the
mesh size of MEDICI; the difference of 7mV in the work function can be
attributed to the slight discrepancy in the values of intrinsic device
parameters, like ni, Eg and silicon affinity, X, used in UFDG and MEDICI.









weak-inversion calibration that if we can get the correct 0m and Le for this structure

(Figure 3.1(b)) by using an equivalent structure like that of in Figure 3.1(a), we can

still reliably predict the performance of FinFETs. In the next section, the UFDG

model's validity for FinFETs is examined and required upgrades are described based

on the insights gained from the MEDICI-simulated FinFET characteristics and

UFDG calibrations to those.


3.3 Upgrades in Weak-Inversion Model for FinFET with Underlaps

3.3.1 Model Upgrades

The nanoscale FinFET (Figure 3.1(b)) structure, from source to drain, is

basically a gated n-i-n structure where the undoped portion (undoped/moderately

doped extensions plus the channel) is flooded with electrons spilled over from the

highly doped source and drain. The application of gate bias in the weak-inversion

region modulates the carrier concentration over the entire channel in the process of

establishing a drift-diffusion balance. Moreover, as the low carrier concentration in

the weak inversion is not effective enough to screen the gate-induced electric field,

the gate also modulates the carriers in the undoped extensions. Figure 3.6 shows the

MEDICI-predicted variation of potential and electron concentrations between source

and drain with gate bias in an undoped nanoscale FinFET for both low and high drain

biases. As evident in the figure, in weak inversion gate modulates the carriers in the

extensions as well as in the channel.

The Debye screening length XD is given as,








50












06 0 VGS=1 2Vi l l s 1020 1020 'Ls L LeD 1020

05 OOv 0 10 02V
1018 0 10170


00 V1 E 101
0 80 0 1016 00 Ol 0

0 102 1
10 10


030 1
0 1 L L Le 102 102


0 10

y (Cm) y (Cm)
(a) VDS = 0.3V (c) VDS = 0. V
04l 1








02 1020 1020 1020

16 0Les I Lg Le 1013 U 10


S101 10
01 2 Vs~ 210 107 10
10S D0 Lg












0810 10o0 Sl1
07 ,I 1e0 2 10 10
v 10/ 1012 o
05 10/
02 loll 10/ VG2 05


005 008 011 014 017 020 023 005 008 011 014 017 020 023
y (vm) y (Vm)









(b) VDS = 1.2 V (d) VDS = 1.2 V





Figure 3.6 IVIEDICI-predicted surface potential variation between the S and D
contact regions of an L = 105nm DG nFinFET (Vt 0) for VGS varying


between weak and strong inversion, and for (a) low and (b) high VDS; tsi

= 26nm. Electron density (at x = 0, tsi) variation corresponding to the

potential variation in (a) and (b) is shown in (c) and (d), respectively. The
entire S/D fin-extension regions (Les = LeD = 25m) were left undoped,


as was the body/channel. The S/D doping profile is abrupt as shown by the
dotted curve.
dotted curve.









VT7
nD = -. (3.23)
i qn


In weak inversion, usually the carrier concentration n < 1x1016 cm-3, which makes

kD > 40nm. Such a long screening length allows the gate bias to alter the carrier

concentration beyond the channel, inside the undoped part of the extensions. As the

carrier concentration goes up near the source (or drain), the gate-induced carrier

modulation ceases. If the effective channel length Leff is defined as the length over

which the gate modulates the carriers, for nanoscale FinFETs it becomes


Leff = LeS +L + LeD (3.24)


where Les and LeD are the undoped parts of the extensions near the gate edges as

shown in Figure 3.6 and Figure 3.1(b). Comparing (3.24) with (2.1) we find that


AL = -(LeS+ LeD) (3.25)


if the UFDG model is applicable for such FinFETs. To check this conjecture, we

calibrate UFDG to MEDICI-simulated FinFETs. The gate length of the device

chosen for simulation is 18nm, toxf = toxb = Inm, and tsi = 10nm; it has a mid-gap

gate and its body is left undoped. In Figure 3.7 the calibration results are shown. The

parameter DL (corresponds to AL in (3.25)) in UFDG is tuned to match the short-

channel effects. For (Les+LeD) = 8nm structure, to get an excellent match in SCEs

(DIBL and S), DL is tuned to -6.2nm (Figure 3.7(a)) and for (Les+LeD) = 10nm, the

required DL = -10.4nm (Figure 3.7(b)).












10-5 VDS-1 -v
MEDICI
-- UFDG 5 mV


10-9



10-11



10- 13
-0.2 -0.1 0.0 0.1 0.2 0.3
VGS (V)
(a)


106 MEDICI VDS= 1.0
-- UFDG
50 mV
10--

10-10





10-12


10 -14 . ., . . .
-0.2 -0.1 0.0 0.1 0.2 0.3
VGS (V)
(b)

Figure 3.7 UFDG calibration to a MEDICI-simulated mid-gap FinFET with (a) Les
= LeD = 4nm and (b) Les = LeD = 10nm. Other device/model parameters
are Lg = 18nm, tsi = 10nm, toxf = toxb = Inm. UFDG model parameter DL
is tuned to (a) -6.2nm, and (b) -10.2nm. Quantum-mechanical effects are
turned off in both the simulators.









Les (LeD), as defined in Figure 3.1(b) as well as in MEDICI simulations,

is a rather technological definition, i.e., it is defined as the distance from the gate

edge to the plane, where the source (drain) doping falls abruptly to zero. However,

Les (LeD) in (3.24) defines the source (drain) extension length over which the gate

effectively controls the carriers. From Figure 3.6 it is evident that near the source

(drain), gate does not modulate the carriers due to the shorter screening length there.

Thus, (3.24) can be modified as


Leff = LeS + L + LeD- 2D(nb), (3.26)


where XD(nb) is the Debye length corresponding to the carrier concentration at the

boundary, nb. The typical value of kD is -lnm, corresponding to an average doping

density of lxl019cm-3 near the source/drain. Considering this, for shorter Les and

LeD in Figure 3.7(a), (3.26) holds true. That is, when the undoped extensions are

smaller (-4nm), UFDG is applicable to FinFET structures with its DL indicating the

amount of gate underlap. But for longer Les and LeD, the DL required for predicting

similar SCEs is almost half of Les + LeD and does not correlate directly to the

underlap lengths.

Before drawing any further conclusion, we look into the calibration results

again in Figure 3.7. It is clear that while UFDG is predicting the SCEs well, it is

overestimating the magnitude of the channel current Iwk, which is more evident for

the longer underlaps. To investigate further we look at the potential profile along y,

predicted by both UFDG and MEDICI. Figure 3.8 shows the potential profile for the

device in Figure 3.7(a) at low drain bias with VGfS = VGfS = VGS = OV. While the











0.8
SMEDICI
0.7 UFDG









0.3

0.2 VGS = OV
0.2 -
VDS = 0.05V

0.1
Les Lg LeD

35 40 45 50 55 60 65 70 75 80
y (nm)

(a)
I II ) /
















0.65 Les Lg LeD



0.45




-0.35

-MEDICI
0.25 UFDG VGS = OV
VDS = 0.05V
0.15


0 .0 5 . . . . .. .. .
35 40 45 50 55 60 65 70 75 80
y (nm)
(b)

Figure 3.8 MEDICI- and UFDG-predicted potential profile, 4(y) (a) along the
channel of the FinFET simulated in Figure 3.7(a), and (b) potential
profile for the same device as in (a) with the boundary value Ob taken
from the MEDICI simulation rather than that predicted by (3.15). Inset
in (a) shows the zoomed-in profile near the metallurgical boundary.









UFDG-predicted profile closely follows that of MEDICI, the minimum potential

predicted by UFDG is a few millivolts higher than that of MEDICI, which results in

the overestimation of UFDG-predicted Iwk, as from (3.14) log(Iwk) ,m. This

overestimation is independent of gate bias, which is evident from Figure 3.7, where

a shift in the voltage axis towards the right for UFDG-predicted characteristics will

yield an exact match of Iwk between MEDICI and UFDG simulations, for all the bias

points in weak inversion. The expression (3.4) for om using ym = Leff/2 for low VDS

(from (3.10)), after some algebraic manipulation becomes



om = (K +b)sech(j )- K. (3.27)


In (3.27) the bias dependence comes from K. Then, the only parameter that gives a

bias-independent variation of Om is )b, as


dm- =sech Y (3.28)
db 2


As shown in the inset of Figure 3.8(a), the boundary value of Ob for the

UFDG simulation is higher than (as predicted by (3.15)) that of MEDICI simulation.

If we use the MEDICI-predicted Ob in the UFDG model, and compare the two profiles

of Figure 3.8(a), as shown in Figure 3.8(b), we find that the minimum potential is

identical for the two cases. So, the mismatch in Iwk in Figure 3.7 is due to the use of

inaccurate Ob. To check this conclusion further, the calibrations in Figure 3.7 are

repeated in Figure 3.9, where Ob used in UFDG is extracted from the corresponding

MEDICI simulation. Excellent matches in Iwk, S, and DIBL are obtained, implying






56




10-5 VDS=I.OV

MEDICI Les = LeD = 4
10- UFDG DL= -6.2 5mV
107



10-9



10-11



10-13
-0.2 -0.1 0.0 0.1 0.2 0.3
VGS(V)
(a)



10-6 MEDICI Les = LeD= 10 VDS=10V
UFDG DL= -10.2
50mV
10-8



10-10



10-12



1 0 -14 . . . . . . . . . . .
-0.2 -0.1 0.0 0.1 0.2 0.3
VGS(V)
(b)

Figure 3.9 Recalibration of the 18nm-FinFET in Figure 3.7. The value of the
boundary potential Ob used in UFDG is extracted from MEDICI for
both (a) the shorter-underlap, and (b) the longer-underlap FinFET.









that along with the tuned DL, Ob also has to be close to the physical value to predict

the characteristics of FinFET reliably. In addition, to get a correct 0m, accuracy in (b

also aids in getting the correct electric field at the boundary. As seen from Eqs.

(3.11)-(3.14), Le depends on the electric field at the boundary Eb, as well as on Om.

From (3.21),


dE
dEb tan h ; (3.29)
d~b (N2


i.e., overestimation of Pb will overestimate Eb, which in turn overestimates Le in

(3.13), and so underestimates the current. For short-channel devices such

overestimation of Le in (3.14) is compensated by the overestimation of 0m. However,

for long-channel devices, the minimum potential is mainly influenced by the vertical

field and the variation of Ob has a negligible effect on (m (as evident from (3.28),

sech(yL/2) 0 as L/tsi becomes large), so overestimation of Ob will mainly result in

overestimating Le and thus underestimating Iwk.

Modeling Ob for FinFETs with underlap, along the lines of (3.22) for non-

underlap devices, requires a numerical solution of the PE in the extension.

Nonetheless, we can get a simple model for (b using our insights from (3.26). As

defined earlier, Les (LeD) is the length from the gate edge to the source (drain)

contact where the gate-induced modulation ceases. So the effective channel

boundary in the x-z plane is where the carrier density is high enough to give a

negligible kD and is able to screen the source (drain) carriers from the gate-induced

field. Looking at Figure 3.6, the carrier density in the extensions where gate bias-









dependent modulation is negligible is 1 x 1019cm-3. So, the potential 4b at that

point can be expressed as



b = Vbi- VTln (3.30)


where nb = 1 x 1019cm-3.

The value of nb chosen here varies with the device structure; for example,

for severe short-channel effects (i.e., when Leff/tsi is smaller), the electron

concentration at the boundary increases due to increased punch-through, yielding an

increase in Ob. Besides, the use of M-B statistics also introduces some uncertainty in

(3.30). So, we introduce a new user-defined model parameter in UFDG, SCEB such

that


ND
b = Vb -(SCEB)VTln- (3.31)
nb


Values of SCEB are positive and usually lie between 0 and 1. Along with

this parameter, we also introduce two more parameters, LES and LED corresponding

to the lengths Les and LeD in (3.24). These two length parameters replace the

parameter DL in UFDG, but unlike DL, the contribution of LES and LED in Leff is

bias-dependent, as we will show in the next section.


3.3.2 Verification and Utility

With three new model parameters, LES and LED defining Leff in (3.24),

and SCEB removing the uncertainties in Ob in (3.31), the description of weak-









inversion current Iwk in (3.14) is now complete for faithfully predicting the weak-

inversion characteristics of nanoscale FinFETs. In this section we present further

calibration results to corroborate UFDG's validity in such predictions. To get the test

data, we again use MEDICI. Along with the 10nm-thick-film device, we also

simulate a device with thicker film, tsi = 15nm, to check the model's viability for

devices with degraded SCEs. In our MEDICI simulations, we use a constant-mobility

model to avoid non-physical variations of mobility in the weak-inversion region,

which is present in some of the mobility models in MEDICI. Earlier UFDG models,

used in this section (a QM-based mobility model [Tri05b], incorporated in the recent

UFDG versions, is discussed in Chapter 4), take care of the dependence of mobility

on film thickness [Chi01], which is absent in MEDICI's constant-mobility model. To

have the similar mobility in both the simulations, UFDG low-field mobility UO is

set to 820cm2/V.s and 670cm2/V.s for tsi = 10nm and 15nm, respectively, whereas

in MEDICI, the low-field mobility is specified as 600cm2/V.s regardless of the film

thickness. Also, quantum-mechanical effects are not included in either MEDICI or

UFDG simulations.

In Figure 3.10, UFDG calibration to MEDICI-simulated 15nm-thick-film

FinFET is shown. UFDG's prediction of IOFF, S, and DIBL are precise for both

devices with total underlap of (a) 8nm, and (b) 16nm. In Figure 3.10(a), values of

LES and LED are close to those of Les and LeD in MEDICI, implying that for shorter

Les and LeD, LES and LED tell us the amount of underlap in the device. For shorter

underlaps, the carriers in the extensions are supported by both the longitudinal field

and the vertical fringing field from the gate. As seen from Figure 3.11 near the gate

































-0.20 -0.10 0.00 0.10
VGS (V)
(a)


-0.10 0.00 0.10 0.20
VGS (V)
(b)


Figure 3.10


Calibration of UFDG to a MEDICI-simulated 15nm-thick fin FinFET with
(a) smaller underlaps, and (b) longer underlaps. All other device
parameters are the same as in Figure 3.7.


10-6





10-8



1010


10-12 LI
-0.30


10-13 L,
-0.20





















.-- .*,r.

S- -.
~----- *




. -.-- ....-.....
.. .- ... ......
C 4.
-.






-I-- *'- II .
--* ----- -----



i--- i .n
a ----.-... .,

5 a J,
1.il' I :,l tl r'i


li((I -!rTni"jP -

.Ii* ... .... .


S ..... ..-




A-. .-.---.- --
*"i ".. *





j..









i .l I *i- r
..icrunrt ] -2


~-Gj-


s A-- -


I- .



s"t*




J1.- j _


----~ii.- -;-D

.*t...-*------- -


4.D "..C O:.t ?e 80 R sD
QOt:; e (InLcro-n > 1801-2

(b)

Figure 3.11 MEDICI-simulated electric field vector in the x-y plane of the FinFETs of

Figure 3.7 with VGfs = VGfS = VGS = 0.1V and VDS = 50mV. The gate is

spanned from 50nm to 68nm. In (a) Les = LeD = 4nm and in (b) Les = LeD

= 10nm.









edges, in the extensions, the electric field is 2D in nature, thus (3.1), with its

boundary conditions (3.2) and (3.3), holds true, as long as Les and LeD are 4nm or

less. The physical nature of the UFDG model for such shorter lengths thus allows us,

through LES and LED, to extract the amount of underlaps in the devices directly.

Figure 3.11(b) shows the electric field vector for longer Les and LeD. The

field is clearly ID in nature in most parts of the extensions. So, the UFDG model in

such cases basically presents an equivalent structure of the device with underlap,

where Leff (as in (3.24)) represents an effective length, which allows UFDG to

predict the correct diffusion length Le and minimum potential Om. So, there is no

direct correlation between LES and LED with actual underlap in the device where

Les and LeD are longer. However, the LES and LED in UFDG can still be effectively

used in gathering information regarding the amount of underlap in the device. In

Figure 3.12, UFDG-predicted (LES + LED) vs. actual underlap length in the

MEDICI (Les + LeD) simulation is plotted for two different film thicknesses. For both

devices, UFDG predicts shorter underlaps quite correctly; for longer underlap cases,

its prediction is around 50% of the actual underlaps. From this empirical observation,

we thus conclude that for devices with long underlap lengths (> 4nm), UFDG

parameters LES and LED roughly indicate half of the underlap lengths.

Note that from Figure 3.12, for a particular underlap length, the UFDG-

predicted Leff (defined by LES and LED) is almost independent of tsi. It is expected,

because if tsi is thin enough to have sufficient gate-control all over the film, then Leff,

i.e., the gate control of carriers in the lateral direction, will be independent of tsi.

However, if tsi is so thick that the drain has more control of the carriers in the middle














































1 0.0
20.0


10.0 15.0
Total Underlap Length (nm)


Figure 3.12


Comparison of UFDG-predicted LES + LED (closed symbols), obtained
by calibrating to VMEDICI-predicted WI characteristics, with the total
underlaps of test FinFETs for two different film thicknesses: 10nm
(circles) and 15nm (squares). The tuned SCEB (open symbols) in UFDG
for the respective underlaps are also shown.


10.0




+
c)

S5.0







0.0(
C









of the fin than the gate, we can expect for a particular underlap length, Leff to be

smaller compared to that of a thinner film FinFET. In fact in the figure, the thicker-

film device has slightly smaller LES+LED (when Les+LeD < 3nm) compared to the

thinner film one, consistent with our understanding of Leff(tsi).

Also, in Figure 3.12 the SCEB required for corresponding underlap is

plotted. With the increase of underlap lengths, the required values of SCEB increase.

This is because for the longer-underlap devices, the short-channel effects are

reduced, thereby reducing the potential at the boundary, and thus necessitating an

increase in SCEB in (3.31). Usually the value of SCEB will lie between 0 and 1, as

in the figure. But, for long channel devices, or with longer underlaps, it may go

beyond 1.


3.4 Upgrades in Strong-Inversion Model for FinFET with Underlaps

3.4.1 Effective Channel Length

We observed with gate bias the carrier concentration in the channel (ns),

as well as that in the G-S/D extension (nes/D) increases. However, as ns reaches ~

1019cm-3 in strong inversion, it screens the gate-induced electric field, as kD

decreases and prevents gate-induced modulation of carriers in the extension. The

phenomena is depicted in Figure 3.6, where we find that gate-induced modulation of

neS/D ceases after the gate bias drives the device into the strong-inversion region.

That is, in SI there is no contribution of LeS/LeD to Leff in (3.26), which in SI shrinks

to


L = L + 2X (ns)=L .
eff g D s g


(3.32)









With ns 1019cm3, the contribution of XD(ns) in (3.32) is small compared to Lg,

hence, Leff = Lg in SI is a reasonable approximation. Indeed in the calibrations in

Chapter 2, we have found that Leff = Lg in SI for longer devices. (The discrepancy in

SI-Leff and Lg in Figure 2.3 for the 17.5nm FinFET could be due to the high R/D,

which reduces the effective gate bias, i.e., inversion charge, and hence, increases XD.

Also, the longer Leff obtained might also be accounting for the decrease of ID due to

the poly-depletion effects.) The validity of (3.32) for shorter channel lengths will be

shown later in this section, after discussing the parasitic resistances.

Note the difference in the manner AL and Les/LeD contribute to the Leff.

The overlap always reduces the effective channel length, regardless of the gate biases

as evident in (2.1), whereas the underlaps lengthen Leff in weak inversion but do not

affect Leff in strong inversion. Such bias dependence is incorporated in UFDG by

modeling strong-inversion Leff by (3.32) but ignoring the contribution of XD(ns). The

shrinking of Leff from (3.24) to (3.32) in UFDG is implicit in the moderate-inversion

spline, which is defined by the weak-inversion and strong-inversion currents that are

governed by the respective Leff.


3.4.2 Parasitic Resistance

Even though in strong inversion, the extensions do not contribute to Leff,

they add an additional component to the parasitic resistance. The concentration of

carriers in the extensions that define the resistance is determined by the amount of

injection from the source (drain), and the diffusion of electrons from the channel. To

develop a first-order model for the resistor we can approximate this carrier

concentration in the extensions with an average carrier concentration, nes/, in the









linear region of operation. Then the resistance of the extension, ReS/D, assuming

drift-dominated conduction, is


LeS/D
R eS/D es/D (3.33)
eS/D qn eS/DWti


where pL is the carrier mobility in the extension. The average carrier concentration,

neS/D, is determined by the carrier concentration on both sides of the G-S/D underlap,

i.e., nb and ns (Figure 3.6). The complexity in (3.33) comes from ns, which is a

function of the effective gate bias, which in turn depends on the resultant ReS/D that

reduces the gate bias, VGS by VeS/D = IDReS/D. Hence, incorporation of ReS/D by

(3.33) will require introducing an iterative solution scheme for ID(VGSeff = VGS -

Ves, VDSeff = VDS -2VeD), where the initial solution of ID has to be obtained with

ReS/D = 0, which will also give the initial value of ns, and hence ReS/D. Then the

updated ReS/D has to be used to get ID; the loop has to continue until a convergence

criterion is met. Thus the incorporation of the linear resistance will increase

simulation time significantly.

In addition to the dependence on VGS, ReS/D also depends on the drain bias

VDS. With the increase of VDS, ID increases, which in turn increases VeS/D, thus the

electric field in the underlap increases. As the carrier concentration in the extension

neS/D < ns, to support the same ID, the velocity veS/D of the carriers in the extension

has to be greater than the velocity vs of the carriers in the channel. With an increased

electric field in the extension, veS/D thus increases, and becomes saturated (to a value

vsat) before vs. As such, at high VDS, ReS/D saturates and becomes independent of the

gate bias, as we have found from UFDG calibration to data in Chapter 2. The









phenomenon is further illustrated in Figure 3.13(a) where MEDICI-predicted SI-v(y)

of a FinFET with long, 27nm of underlap on each side of the gate (the device studied

in Figure 2.3), is shown for increasing VDS. At high VDS, both Ves and VeD are

saturated and are higher than vs. As VeS/D Vsat, V. 0 in (3.33), and thus ReS/D

saturates to a value higher than that in the linear region.

With veS/D = vsat, (3.33) is not applicable for saturated ReS/D. Rather,

using a quasi-2D analysis, like that done for accounting the channel-length

modulation in bulk-Si [Man77], we find the expression for the saturated Res/D as


2
R L eS/D (3.34)
eS/D2Si WtSisat


Using the dimension parameters (tsi = 32nm, LeS/D = DL/2 = 9nm) of the FinFET in

Figure 2.4, and assuming vsat = 5x106 cm/s, the voltage drop across the S/D underlap

is 0.28V, with ID = lxl1-4A. From the calibration results in Figure 2.4, Rs = 4250-

pm, assuming 150Q-tm of it is due to the contacts/sheet resistance, ReS/D ~ (425-

150) or 275Q-pm, or 3KQ, which gives a voltage drop across Les, Ves = IDReS

0.3V, close to the value that is implied by (3.34).

A complete modeling of ReS/D(VGS,VDS) includes smoothing of the linear

resistance defined by (3.33) to the saturation resistance defined by (3.34), and then

including the model in an iterative scheme to solve for ID(RS/D), and RS/D(ID). For

pragmatic FinFETs, however, Les/LeD should be short, ~ 4nm, as discussed in

Chapter 2, and as demonstrated in [Tri05a]. For such FinFETs, the velocity does not

saturate in the extensions as illustrated in Figure 3.13(b). In the figure MEDICI-






68





1 .5 ............ ...... .........


Les Lg LeD

g D
1.0




0.5
o 1.2V

J I VGs=1.2V
I VDs=0.4V i
0.0 I
0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 0.16
y (pm)
(a)



2.0 -
S00.4V
.6 0.6V
o1.6 -0.8V
A--A1. 0V
o 1.2V
-1.2 s

O I
S 0.8 -


0.4 VGS=1.2V
SLs L LeD

0.0 . .
0.022 0.030 0.038 0.046 0.054
y (Pm)
(b)

Figure 3.13 MEDICI-predicted electron velocity along the channel of a FinFET with
(a) long extension length, Les/D = 27nm, and tsi =17nm, like that in Figure
2.4, and (b) Les/D = 4.5nm, tsi = 14nm, like the optimum FinFET [Tri05a]
discussed in Chapter 5. (In (b) the reduction in velocity in the channel
near the drain-end with increasing VDS could be due to the spurious
solution of MEDICI energy-balance model.)









predicted SI-v(y) of FinFET with LeS/D = 4.5nm is shown for different drain biases.

As the underlap length is not much longer than kD(ns), the gate bias can effectively

control the carriers in the extensions. Consequently, at high VGS, when ns and ID

increase, neS/D increases as well, and can support the increased ID. Also, shorter

underlap length reduces VeS/D, hence the electric field is also low in the extension.

Thus VeS/D (and hence neS/D) does not saturate at high VDS; instead the carriers in the

channel near the drain experience velocity saturation, like that in the typical

MOSFETs. Therefore for pragmatic FinFETs, accounting for the saturation of

underlap resistance is not needed.

The total parasitic resistance (Rs/D) in FinFET is the sum of the

contribution of the contact resistance (Rco), sheet resistance (Rsh), and spreading

resistance (Rsp) [Tau98], and an additional component ReS/D when underlap is

present, i.e.,


RsD= Rco +Rsh +Rsp + ReSD. (3.35)


While in the bulk-Si MOSFET, Rsp is 20-30% of RS/D, in the FinFET due to bulk

inversion [Kim06], Rsp is small compared to Roo or Rsh (as evident from MEDICI

simulations). For shorter underlap length, ReS/D will be low as well. Dependence of

ReS/D on LeS/D is illustrated in Figure 3.14, where extracted linear resistance from

MEDICI-predicted linear ID-VG, is plotted for varying Les. The extraction is done

following the 'channel resistance method' described in [Tau98]. As expected from

(3.33), the resistance increases sharply with the increase of Les. Also note the

increase of ReS/D for the thinner fin. We argued that for pragmatic FinFET LeS/D ~



















300


250


200


150


100


Les (nm)


Figure 3.14


Extracted linear resistance of an 18nm-FinFET with varying underlap
lengths, for two different fin thicknesses. The resistances are extracted
from IMEDICI-predicted linear ID-VG. Also shown in the figure is the
ITRS targeted Rs/D for an 18nm-MOSFET [ITR05].









4nm, and for such cases ReS/D is not that high, and the total RS/D will be dominated

by Roo and Rsh. Hence bias dependence of ReS/D expected from (3.33), will not be

reflected in RS/D. That is, for shorter Les/LeD neither the VGS nor the VDS

dependence has a significant effect on the total resistance, and thus, allows us to

avoid incorporating the iterative ReS/D model described by (3.33) and (3.34). In

UFDG thus, the bias-independent model parameter RS/RD is retained to model the

resistive-effects of LeS/D. This will make UFDG predictions optimistic for FinFETs

with longer underlaps, but for pragmatic, shorter LeS/D-FinFETs, model predictions

will remain acceptable.

The validity of retaining the bias-independent RS/RD to account for the

parasitic resistance, as well as that of (3.32) to account for SI-Leff, for shorter

underlap length is illustrated in Figure 3.15. With RS = RD = 60Q-pm, and bias-

dependent Leff captured by LES = LED = 3.2nm, UFDG predictions are well in

agreement with that of MEDICI for an 18nm-SDG FinFET with 4nm of underlaps on

each side of the gate. Excellent match in both the weak and strong inversion

exemplifies UFDG's applicability for performance projection of pragmatic

nanoscale-UTB FinFETs.


3.5 Design Implications

With the incorporation of effects of underlaps in UFDG, we now can

extend the design study done in Chapter 2. In Chapter 2, we focused on the effects

of underlaps on device performance, here we look into their effects on speed-

performance of CMOS-FinFETs using a 9-stage FinFET ring-oscillator. The FinFET

structure considered is like that shown in Figure 2.8, except for the fin thickness. We






















VDS=I.OV :


50mV












/ / MEDICI Ls = LD = 4nm
UFDG LES = LED = 3.2nm
RS = RD = 60Q-gm SCEB = 0


10-2

10-3

10-4

10-5

10-6


10-7

10-8


10-9

10-10

10-11
0.


0.6 0.7 0.8 0.9 1.0


Figure 3.15


Comparison of MEDICI- and UFDG-predicted I-V characteristics of a
mid-gap gate 18nm-SDG FinFET with underlaps; tsi = 8nm, tox = Inm. In
both the simulators, carrier-temperature-dependent transport models and
QM models are turned off.


0.1 0.2 0.3 0.4 0.5
VGS (V)


0









use a pragmatic, thicker (14nm) film [Tri05a]. Also, LeS/D is kept relatively short, 0-

8nm, as UFDG predictions are more reliable for shorter underlap lengths, and we

already concluded that longer underlap lengths are not useful due to high, bias-

dependent RS/D.

Figure 3.16 shows UFDG-predicted variation of RO delay with underlap

lengths. The FinFET has Lg = 18nm, tsi = 14nm, and a mid-gap gate. In the

simulation, ReS/D is taken from Figure 3.14, and 100I-pOm is assumed due to contact

and sheet resistance. As we do not consider the bias-dependence of ReS/D, the delay

predicted for the longer underlap lengths, like for LeS/D = 8nm is optimistic, but will

not affect our conclusion here. Values of the inner fringing parameter FIF shown in

the figure are taken from [Kim06].

The effect of underlap lengths on td is two-fold. With increasing LeS/D,

ION decreases (Figure 2.10) due to high RS/D, as well as increased Vt, which tends to

increase the delay time. On the hand, increasing LeS/D decreases the fringing

capacitances [Kim06], and thus tends to decrease td. The former dominates for longer

LeS/D, and thus we see td showing a positive slope for LeS/D > 6nm in Figure 3.16

(the increase in td is not that pronounced in the figure due to assumed constant, low

ReS/D). The reduction of fringing capacitances dominates for shorter LeS/D, and gives

an optimum range for LeS/D, 4-5nm. In Chapter 2, we reached a similar conclusion

considering the device-level performances. Thus a pragmatic, and optimum ITRS

45nm node FinFET with Lg = 18nm, should have 4 to 5nm of G-S/D underlap.

In Chapter 2, we also found that, if asymmetric Les and LeD are feasible,

it is advantageous to have Les < LeD, as such a case offers lower Res and hence less




















2.6




2.5



C,)
-2.4
-o




2.3




2.2



Figure 3.16


2.0 4.0 6.0
LeS/D (nm)


UFDG-predicted variation of ring-oscillator delay (td) with underlap
lengths (Les/D). Inset shows key UFDG model parameters used for
different Les/D. 1000Q-jm of RS/RD is assumed to be due to the contact
and sheet resistance, and the contribution ofRes/D(LeS/D) is obtained from
Figure 3.14. Values of the inner fringing parameter, FIF is due to [Kim06].
The devices are undoped { 110}-FinFET with Lg = 18nm, tsi = 14nm, tox
Inm, and (M = 4.6eV; VDD = IV. QM and ballistic-limit model in UFDG
is turned on.









reduction of effective gate bias. In Table 2.1, we show the improvement in RO delay

when Les < LeD is adopted over a reference FinFET having Les = LeD = 4nm. For

example, when Les = 0 and LeD = 8nm, the improvement in UFDG-predicted td is

20%. The substantive increase is due to two reasons, one is the noted reduction of

Res, and the other is the reduction of gate-to-drain capacitance, Cgd with increasing

LeD. Increasing LeS/D increases the separation between the source/drain 'plane' and

the gate, which reduces both the inner and outer fringing capacitances [Kim06]. So,

when LeD (Les) is increased (decreased), Cgd (gate-to-source capacitance, Cgs)

decreases (increases). Due to the Miller effect, RO delay is more dependent on Cgd

than Cgs [Rab03], and hence, even though having Les < LeD increases Cgs, td

decreases due to the decreased Cgd, and enhances the speed-performance compared

to the Les = LeD design. However, caution should be exerted in designing a device

with asymmetric Les/LeD, as when the gate is too close to the source/drain the SCEs

degrade (Figure 2.11) and IOFF increases. Moreover, having the source/drain close to

the gate edge increases the sensitivity of device performance to the variation of

source/drain dopants in the extension, an issue discussed in Chapter 5.


3.6 Conclusion

Due to the presence of underlaps, the effective channel length in nanoscale

undoped-UTB FinFET is bias-dependent and is greater than the metallurgical gate

length in weak inversion. In this chapter, we have discussed complexities presented

by underlaps in compact modeling of FinFETs, and upgraded UFDG to account for






















Table 3.1


UFDG-predicted ring-oscillator delay for an 18nm-FinFET
underlaps. Values of RS/D (LeS/D) and FIFs/D(LeS/D) are from
other device parameters are the same as in Figure 3.16.


with asymmetric
Figure 3.16, also


Les LeD RS RD 1 td
(nm) (nm) (Q-tm) (Q-m) FIFs FIFD (ps)
4 4 128 128 0.7 0.7 2.30
2 6 106 154 0.9 0.6 2.12
0 8 100 188 1.0 0.5 1.82

1. At present UFDG does not allow asymmetric FIF; the above values are hard-wired in the code
before each simulation.









the bias dependence of Leff. Also, the modeling of the source-channel boundary

potential was discussed for both underlap and conventional non-underlap devices.

In strong inversion, the noted underlap does not affect the Leff

significantly, but introduces a component to the parasitic resistance. The resistance

due to the underlap shows bias dependence as well; it decreases with gate bias in the

linear region, but saturates in the saturation region. However, for pragmatic FinFETs

having shorter underlap lengths, the bias-dependence of parasitic resistance is

negligible and does not warrant a change in the present UFDG formalism that

accounts for the parasitic resistance with bias-independent model parameters. Hence,

even though modeling of the bias dependence of the underlap resistance was

discussed, they were not incorporated in UFDG. However, proper accounting of the

bias dependence of Leff was incorporated by replacing the overlap parameter DL,

with parameters LES and LED that account for the effective underlap lengths, and

modulate Leff appropriately. Model upgrades were verified by comparing UFDG

predictions with those of MEDICI's. For both weak and strong inversion, upgraded

UFDG predictions were found to be in excellent agreement with MEDICI for

pragmatic UTB FinFETs. The proper accounting for the effects of underlaps thus

enhanced the reliability of UFDG performance-projection capability for pragmatic

FinFET circuits.

The upgraded model was then used to extend the design study of Chapter

2 by performing circuit-level simulation. Study of the speed-performance of FinFET-

CMOS revealed that the optimum underlap length for a pragmatic, 45nm ITRS node






78


FinFET is 4-5nm. Also, UFDG-predicted RO simulation showed that speed

enhancement as high as 20% can be achieved if asymmetric underlaps are used.















CHAPTER 4
CARRIER TRANSPORT IN NANOSCALE FINFETS

4.1 Introduction

In Chapter 2, in the preliminary calibration of UFDG to contemporary

FinFETs, we mainly focused on the electrostatics of UTB FinFETs. We found that

due to the undoped UTB, the extensions are not doped directly, which in turn results

in G-S/D underlaps, resulting in bias-dependent Leff. A more direct effect of leaving

the body undoped is that it reduces the transverse electric field, which promises

higher channel mobility. In this chapter, with the upgrades done in Chapter 3 (i.e.,

accounting for the effects of gate-source/drain underlap), and the recently

incorporated QM-based mobility model [Tri05a], we present further calibration of

UFDG to FinFETs, and insights thereby derived, especially regarding the carrier

mobility and transport properties in the channel. Both electron mobility and hole

mobility in n- and p-channel FinFETs are studied. The transport parameters obtained

from the calibrations are then used to project channel currents of sub-20nm FinFETs,

by using UFDG simulations, which involve both dissipative and ballistic transport.

With high-mobility/ballistic-limited transport, the FinFET channel

resistance is expected to be low, which indicates that the FinFET will be more

vulnerable to parasitic resistance. Effects of the parasitic resistance on drive current

and ring-oscillator delay are thus discussed by comparing a hypothetical bulk-Si

device with an SDG FinFET.









4.2 Carrier Mobility in the Channel

4.2.1 Electron Mobility in nFinFET

For our nFinFET calibration work described here, we chose room-

temperature ID-VGS characteristics of a 370nm-gate-length FinFET with n+-poly

gate fabricated at AMD with {110} surface [Yu02]. Calibration of UFDG to the

subthreshold characteristics, like subthreshold swing and DIBL, allows us to

uniquely obtain two of the three dimension-related parameters, effective channel

length Leff (defined by model parameter L, LES and LED, or DL), fin thickness tsi

(defined by model parameter TSI) and oxide thickness tox (defined by model

parameter TOXF/TOXB). Hence if the third parameter is known through some other

method e.g., oxide thickness from the C-V characteristics, or fin thickness from TEM

pictures, etc., a valid calibration can be done. However, for the long-channel device

here, with apparently no short-channel effects (SCEs), it is not possible to get unique

values for these parameters from UFDG calibration. We mainly thus rely on the

manufacturer-supplied information for the values of the device dimensions. The gate

oxide thickness used is 17A, known from the process information [Yu02] and also

verified with reasonable accuracy from calibration of shorter-channel devices, as

well as C-V characteristics for the same technology [Yu02]. The physical gate length

is 370 nm, and with extensions not doped directly, there is no source/gate or drain/

gate overlap and hence DL is set to zero. Underlap length, LES/LED, is assumed to

be zero also; however as discussed in Chapter 2, in this device they are actually non-

zero and may be 3% of the gate length but their effect is negligible in weak

inversion. For the same reason, tsi is assumed to be 26 nm, though TEM pictures of

the fabricated device suggest it can vary from 17 nm to 26 nm.









4.2.1.1 Calibration Results

The weak-inversion calibration results, with the model parameters listed

in Table 4.1, are shown in Figure 4.1, where UFDG predictions are in good agreement

with data except for gate bias, VGS < 0.2 V. In that region, the drain current, ID at

high drain bias increases due to gate-to-drain tunneling leakage. Throughout this

work the UFDG gate leakage model will be turned off but the QM model will remain

turned on.

The mobility, on which the subthreshold current is linearly dependent,

used in the calibration is extracted from the linear-region, strong-inversion

characteristics described later. The gate work function (WKFG/WKBG) obtained

from the calibration is 4.073, which indicates a poly doping of 4.5 x 1019 cm-3 (using

Fermi-Dirac statistics) in the gate. The high poly-doping concentration is consistent

with the degradation of capacitances observed in the C-V characteristics in [Yu02],

where the degradation of gate capacitance is observed only at very high gate bias,

VGS > 1.2 V.

Once the dimensional parameters are known through weak-inversion

calibration, the next step is to extract transport parameters from strong-inversion

calibration. As we have found in Chapter 2, UO and THETA can be obtained

uniquely from calibration of gm/ID2-VGS, which is independent of Rs/D [Ghi88]. In

Figure 4.2, we showed the calibration result of UFDG to gm/ID2 characteristics of the

AMD 370 nm FinFET. With UO = 565 cm2/V.s and THETA = 0.2, the UFDG

prediction is in excellent agreement with data throughout the strong-inversion

region, which spans from VGS (Nnv) = 0.3V (5x1012cm-2) to 1.2V (2.1x1013cm-2).

















Table 4.1

Key UFDG model parameters extracted from the calibration to 370 nm AMD nFinFET.



Model
Parameter Description Value
L Physical Gate Length 370 nm
LES Source-gate underlap length 0 nm
LED Drain-gate underlap length 0 nm
DL Source/drain-gate Overlap length 0 nm
TSI Film Thickness 26 nm
TOXF Front gate oxide thickness 1.7 nm
TOXB Back gate oxide thickness 1.7 nm
WKFG Front gate work function 4.073 eV
WKBG Back gate work function 4.073 eV
UO Low-field mobility 565 cm2/V.s
THETA Mobility tuning parameter 0.2
RS Parasitic source resistance 390 Q-jam
RD Parasitic drain resistance 390 Q-jam
W Width 50 nm






83











1 0 -5 . . . . . . . . . . . . . .




10-6




10-7




10-8
o VD = 0.V, measured data
o VD = 1.2V, measured data
S-- UFDG
10-910




1 0 -1 0 1 . . . . . . I . . I . . I . . .. .
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3
VGS (V)


Figure 4.1 Calibration of UFDG to weak-inversion characteristics, ID-VGS of a 370
nm gate length FinFET. Model parameters are listed in Table 4.1




















S.. .......

0.9

0.8 Measured Data
8 UFDG

0.7 \o = 565cm2N-s
< 0.0 = 0.20
0.6

0.5

0.4
E
0) 0
0.3

0.2

0.1 VDS = 0.1V

0 .0 . . . . . . . . . . . . . . . .
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VGS (V)


Figure 4.2 Calibration of UFDG to measured gm/ID2 vs. VGS at low drain bias. The
range of VGS shown is all strong-inversion, as Vt = -0.1V.