<%BANNER%>

Embedded Test Circuit and Method for Radio Frequency (RF) Systems-on-a-Chip (SOCs)

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INGEST IEID E20110217_AAAAAQ INGEST_TIME 2011-02-17T11:47:51Z PACKAGE UFE0015657_00001
AGREEMENT_INFO ACCOUNT UF PROJECT UFDC
FILES
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EMBEDDED TEST CIRCUIT AND METH OD FOR RADIO FREQUENCY (RF) SYSTEMS-ON-A-CHIP (SOCS) By JANG-SUP YOON A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006

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Copyright 2006 by JANG-SUP YOON

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This document is dedicated to my parents, my son, and my wife.

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iv ACKNOWLEDGMENTS I would like to express my sincere gratit ude to my advisor, Professor William R. Eisenstadt, for his devoted support and enc ouragement throughout my work. Without his invaluable support and encourag ement, my exploration in th e research could not have come to fruition. It has been a great pleasure to have been his stude nt. I also would like to thank Professors Robert M. Fox, Kenneth K. O and Loc Vu-Quoc for their advice on this work and their willing service on my co mmittee. I appreciate their interest in my work and their valuable suggestions and co mments from the research proposal to its realization. I would like to especially thank Professor Robert M. Fox for his invaluable and timely advice and encouragement to continue my work every time I eagerly look for a breakthrough. I would like to thank the Semiconducto r Research Corporation (SRC) and National Science Foundation (NSF) for the sponsorsh ip of this work. I also would like to thank IBM for the chip fabrication. I would like to thank my colleague s Hyeopgoo Yoo, Sanghoon Choi, Kooho Jung, Jongsik Ahn, Ming He, Qizhang Yin, Tao Zhang, Choongeol Cho, Yuseok Ko, Xiaoqing Zhou, Xueqing Wang, Jiwoon Yang, Dongjun Ya ng, Inchang Seo, Okjune Jeon, and Youngki Kim for their helpfu l discussions, advice, and friendship. Their support and advice have contributed immensel y to my work. Also, I thank all of the friends who made my years at the University of Florida such an enjoyable chapter of my life

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v Finally, I am grateful to my parent s, Hoyoung Yoon and Jungja Kwon, my sister, Sunghee Yoon, and brother, Wonsup Yoon, fo r their love and en couragement throughout the years. I would like to express my profound thanks to my wife, Youngsim Kim, for her unconditional and never-ending love and suppor t, and my dearest son, Sungroa. Without them, it would not have been possibl e to pursue my graduate studies.

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vi TABLE OF CONTENTS Page ACKNOWLEDGMENTS.................................................................................................ivLIST OF TABLES...........................................................................................................viiiLIST OF FIGURES.............................................................................................................xABSTRACT.....................................................................................................................xv i CHAPTER 1 INTRODUCTION........................................................................................................11.1 Reason for Embedded RF Test...............................................................................11.2 Research Goals.......................................................................................................21.3 Outline of the Dissertation......................................................................................3 2 LUMPED PASSIVE CIRCUITS FOR EMBEDDED TEST OF RF SoCs.................52.1 Introduction.............................................................................................................52.2 Design of Lumped Passive Directional Coupler..................................................102.3 Design of Lumped Passive Balun and Divider.....................................................212.4 Simulation of Lump ed Passive Devices...............................................................272.5 Fabrication Results of Lumped Passive Devices..................................................382.6 Conclusion............................................................................................................43 3 EMBEDDED LOOPBACK FOR RF ICs TEST........................................................463.1 Introduction...........................................................................................................463.2 Embedded IC Test for WLAN SoCs....................................................................473.3 Design of Loopback Circuit..................................................................................493.4 Simulation of Loopback Sub-circuits and System................................................583.5 Measured Results of Loopback Sub-circuits and Test System.............................673.6 Conclusions...........................................................................................................73

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vii 4 ANOTHER EMBEDDED LOOPBACK FOR RF ICs TEST....................................754.1 Introduction...........................................................................................................754.2 Design of Loopback Circuit Type 2.....................................................................774.3 Simulation of Loopback Sub-circuits and System Type 2...................................794.4 Measured Results of Loopback Test Type 2 System............................................864.5 Conclusions...........................................................................................................88 5 EMBEDDED S-PARAMETER MEASUREMENT Module....................................895.1 Introduction...........................................................................................................895.2 Introduction of Scattering Parameters..................................................................925.3 Introduction of Mixed Mode Scattering Parameter..............................................965.4 Design for On-Chip Scattering Parameter Measurement.....................................995.5 Simulation for On-Chip Scattering Parameter Measurement.............................1105.6 Measured Results................................................................................................1155.7 S-parameter Application.....................................................................................1195.8 Conclusions.........................................................................................................122 6 SUMMARY AND CONCLUSION.........................................................................1256.1 Summary.............................................................................................................1256.2 Conclusion..........................................................................................................126 APPENDIX SPIRAL INDUCTOR MODELING USING HFSS........................................................130A.1 Overview............................................................................................................130A.2 Definition of Quality Factor..............................................................................131A.3 Inductance Calculation Using Y-parameter.......................................................132A.4 Another Calculation Me thod for Spiral Inductor...............................................134A.5 Material Assignment for Spiral Inductor Modeling..........................................136A.6 Simulation and Measurem ent of Spiral Inductor...............................................137A.7 De-embedding Method for Spiral Inductor.......................................................140A.8 Another De-embedding Method for Spiral Inductor.........................................143A.9 Conclusion.........................................................................................................145 LIST OF REFERENCES.................................................................................................146BIOGRAPHICAL SKETCH...........................................................................................151

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viii LIST OF TABLES Table page 2-1 Specification for the comme rcial directional coupler....................................................62-2 Specification for the lumped passive directional coupler..............................................72-3 Specification for the commercial divider......................................................................82-4 Specification for the lumped passive divider................................................................82-5 Specification for the commercial balun.........................................................................92-6 Specification for the lumped passive balun...................................................................92-7 Calculation and simulation value for the directional coupler......................................282-8 Calculated value of the equivalent circuit for the directional coupler.........................302-9 Calculation and simulation value for divider..............................................................322-10 Calculated value of the equi valent circuit for the divider.........................................342-11 Calculation and simulation value for the hybrid.......................................................373-1. The resistor values of various attenuators..................................................................533-2. Calculated value of the equivalent circuit for LNA...................................................643-3. Calculated value of the equiva lent circuit for embedded loopback............................664-1. Calculated value of the equiva lent circuit for LNA of Type 2...................................814-2. Calculated value of the equivalent ci rcuit for directional coupler of Type 2.............834-3. Calculated value of the equivalent circuit for the embedded loopback Type 2.........855-1. Specification of the commercial network analyzer and on-chip s-parameter module915-2. Calculation and simulation valu e of 10 GHz directional coupler............................1105-3. Calculated value of the phase detector circuit (Type I)............................................113

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ix 5-4. Calculated value of the HBT Cherry-Hooper amplifier...........................................1135-5. Calculated value of the peak detector.......................................................................1156-1. Design summary.......................................................................................................128

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x LIST OF FIGURES Figure page 2-1. RF&IF block diagram...................................................................................................52-2. Directional coupl er and detector...................................................................................72-3. The basic concept of directional coupler....................................................................102-4. Equivalent capacitance network.................................................................................112-5. Even mode and odd mode of transmission line..........................................................122-6. Transmission line model.............................................................................................132-7. Even mode analysis of coupler and equivalent lumped model..................................142-8. Open case of center symmetric line in even-mode and equivalent circuit.................152-9. Short case of center symmetric line in even-mode and equivalent circuit.................162-10. Odd mode analysis of coupler and equivalent lumped model..................................172-11. Short case of center symmetric line in odd-mode and equivalent circuit.................182-12. Open case of center symmetric line in odd-mode and equivalent circuit.................192-13. Directional coupler and equivalent lumped model...................................................202-14. Symbol for a balun...................................................................................................212-15. Symbol for a divider.................................................................................................212-16. model....................................................................................................................222-17. T-model.................................................................................................................. ..252-18. Schematic of lumped passive directional coupler....................................................272-19. The layout of the lumped-passive directional coupler..............................................292-20. The model of interconnection line............................................................................29

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xi 2-21. The equivalent circuit of metal line..........................................................................302-22. Simulation results of lumped -passive-directional coupler.......................................312-23. Schematic of lumped passive divider.......................................................................322-24. The layout of the lumped-passive the divider..........................................................332-25. The model of interconnection line............................................................................342-26. Simulation results of a lumped-passive divider........................................................352-27. A ring hybrid (rat-race).............................................................................................362-28. Schematic of a lumped passive hybrid.....................................................................362-29. Simulation results of th e lumped-passive balun.......................................................372-30. Die micrograph (1.0mm x 1.2mm) of the lumped-passive-directional coupler.......382-31. Simulated and measured results of the lumped-passive-directional coupler............392-32. Die micrograph (1.0mm x 0.8mm) of the lumped-passive divider..........................402-33. Simulated and measured results of the lumped-passive-divider..............................402-34. Die micrograph (1.0mm x 1.2mm ) of the lumped-passive hybrid...........................412-35. Simulated and measured results of the lumped-passive-divider..............................423-1. WLAN block diagram................................................................................................473-2. Block diagram of embedded loopback RFIC test.......................................................483-3. The resistor type attenuator........................................................................................493-4. The SPDT (single pole double throw) switches.........................................................543-5. N-channel MOSFET model........................................................................................553-6. The schematic of RF switch.......................................................................................553-7. The parasitic model of nMOS with control resistance..............................................573-8. The simulated results of the RF switch with and w ithout control resistance.............573-9. The schematic of the casc ode low noise amplifier (LNA).........................................583-10. Simulation result of pi-type attenuator.....................................................................59

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xii 3-11. The gate model for optimum insertion loss of RF switch........................................603-12. Simulated results of gate width (fi nger number) sweep from 60 to 120 at 5.2 GHz613-13. Simulated results of gate length sweep from 400 nM to 1300 nM at 5.2 GHz........623-14. Simulated results of the RF switch...........................................................................623-15. The schematic of the cascode lo w noise amplifier with parasitics...........................633-16. Simulated results of the low noise amplifier with parasitics....................................643-17. The block diagram of the embedded loopback test model.......................................653-18. The block diagram of the embedded loopback test model with parasitics...............653-19. Simulated results of the loopback with para sitics circuit output power level at port 2663-20. Die micrograph (1.0mm x 1.2mm) of the RF attenuator and RF switch..................673-21. Measured results of various pi-type attenuators.......................................................683-22. Model of the RF attenuator and substrate.................................................................693-23. Layout of the RF attenuator with and without substrate contact..............................703-24. Die micrograph (1.6mm x 1.1mm) of the RF attenuator and RF switch..................713-25. Measured results of the 30 dB attenuator.................................................................713-26. Measured results of the RF switch...........................................................................723-27. Die micrograph (1.85mm x 0.87mm) of the embedded loopback test model..........733-28. Measured results of the embedded loopback test model..........................................734-1. Block diagram of another embedded loopback RFIC test..........................................754-2. The block diagram of embedde d loopback test model Type 2...................................774-3. The schematic of cascode low noise amplifier (LNA)...............................................784-4. The schematic of 10 dB directional coupler...............................................................794-5. Simulated results of the RF switch.............................................................................804-6. The schematic of cascode low noise am plifier with paras itics for Type 2.................804-7. S-parameter simulation result of the low noi se amplifier with parasitics for Type 282

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xiii 4-8. Gain simulation result of the low noise amplifier with parasitics for Type 2............824-9. The schematic of lumped passive directio nal coupler with parasitics for Type 2......834-10. S-parameter simulation result of the dire ctional coupler with parasitics for Type 2844-11. The block diagram of embedded loopback test model Type 2 with parasitics.........854-12. Simulated results of the l oopback Type 2 with parasitics........................................864-13. Die micrograph (1.6mm x 1.2mm) of the embedded loopback test model..............874-14. Measured results of the embedd ed loopback test Type 2 model..............................875-1. Transmission line and equivalent circuit....................................................................925-2. Function diagram of s-parameter................................................................................955-3. Signal diagram of mixe d mode two-port network......................................................965-4. Conceptual diagram of mixed-mode two-port............................................................985-5. Traditional block diagram for s-parameter measurement.........................................1005-6. Receiver block diagram of trad itional s-parameter measurement............................1005-7. Conceptual block diagram for on-chip s-parameter measurement...........................1015-8. The schematic of 10 dB directional coupler for 10 GHz..........................................1025-9. The schematic of DPST switch for 10 GHz.............................................................1035-10. Flip-flop phase detector as a phase detector (type I)..............................................1055-11. The schematic of phase detector type I..................................................................1065-12. Exclusive-OR gate as a phase detector (type II).....................................................1065-13. The schematic of phase detector type II.................................................................1075-14. The schematic of Ch erry-Hooper amplifier............................................................1085-15. The concept of strong impedance mismatch..........................................................1095-16. The schematic of voltage-divid er enhanced RF power detector............................1095-17. Simulation results of 10 GHz directional coupler..................................................1105-18. Schematic of the 10 GHz RF switch......................................................................111

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xiv 5-19. Simulated results of the 10 GHz RF switch...........................................................1125-20. The simulated results of the ph ase detector type I at 10 GHz................................1125-21. The simulation of HBT Cherry-Hooper amplifier..................................................1135-22. Structure of the type II phase detector....................................................................1145-23. Simulated results of the pha se detector type II at 10 GHz.....................................1145-24. Simulated results of the peak detector....................................................................1155-25. Die micrograph (1.0mm x 1.2mm) of the phase detector type I and DPDT switch1165-26. The measured results of the DPDT switch.............................................................1165-27. The measured results of the DPDT switch.............................................................1175-28. Die micrograph (2.2mm x 1.2mm) of the pha se detector type II and phase detector1185-29. The measured results of the phase detector type II wi th Cherry-Hooper amplifier1185-30. The measured results of the peak detector..............................................................1195-31. Block diagram for verificati on of s-parameter measurement.................................1195-32. Peak detection of s-pa rameter measurement module.............................................1205-33. Phase detection of s-pa rameter measurement module............................................1215-34. Example of s-parameter measurement application.................................................1225-35. Phase error calculation with calibration to 0 dBm reference of s-parameter measurement module..............................................................................................124A-1. Spiral inductor modeli ng for 3D-EM simulation.....................................................132A-2. The equivalent circu it of spiral inductor..................................................................132A-3. Two port -model...................................................................................................133A-4. 2-port network of spiral inductor.............................................................................134A-5. Excitation for spiral inductor with GSG pad...........................................................138A-6. Simulation and measurement result of spiral inductor............................................139A-7. Open and short structure for de-embedding............................................................141A-8. The simulation and measured resu lts of open and short structure...........................142

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xv A-9. Simulated and measured result of de-embedding spiral inductor............................143A-10. Another de-embedding stru cture for spiral inductor.............................................144A-11. Simulated and measured result of de-embedding spiral inductor..........................144

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xvi Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy EMBEDDED TEST CIRCUIT AND METHODS FOR RADIO FREQUENCY (RF) SYSTEMS-ON-A-CHIP (SOCS) By Jang-Sup Yoon August 2006 Chair: William Eisenstadt Major Department: Electrical and Computer Engineering This proposal mainly focuses on research in embedded test circuit and methods for RF SoCs. First, lumped passive circuits fo r embedded test of RF SoCs are discussed. Many companies have been trying to integrate an entire WLAN system on a SoC. Such a high level integration calls for research in embedded tests for the SoC. The 802-11a WLAN embedded IC test requires 5 GHz di rectional couplers, baluns, and dividers, which are presented in this proposal. Lump ed passive 5 GHz ICs were developed to realize these compact test devices. Second, an embedded loop back for RF ICs te st is described. The loopback test is one of the lowest cost methods for verifyi ng functionality in a communication circuit. Thus, the loopback test is employed in mature product lines where cost is an over-riding concern or as a final test after other circuit tests. On-chip or on-waf er loopback circuits are designed for verifying performance of 5 GHz wireless WLAN IC circuits.

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xvii Finally, an embedded s-parameter measur ement method is discussed. Testing and verification of the RF and microwave components are major parts of the total testing cost. This is so because very expensive RF and microwave test equipment (for example, A vector network analyzer) should be used for this test. Over the years, various methods have been considered to re duce testing costs. A new met hod is an on-wafer s-parameter measurement which is a very economical method for keeping high level accuracy.

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1 CHAPTER 1 INTRODUCTION 1.1 Reason for Embedded RF Test. A recent design trend in RF/analog technologies is to design Systems-on-a-Chip (SoCs), which include mixed-signal/RF circ uit designs. Due to advanced process technologies, more advanced analog circui ts, RF, and microwave circuits can all be integrated. As chips become more integr ated with mixed-signal/RF circuits, more complex, higher frequency and more accurate test equipment is needed to verify SoC performance. In this highly competitive industry, both chip performance and chip costs are considered important factors for industry success. Testing in this commercial market, especially mixed-signal/RF circ uits, is becoming a major cost factor in overall IC manufacturing costs, and is the primary ma in reason that most IC manufacturers have sought to research and develop new, more economically viable, test methods for mixedsignal/RF circuits. Furthermore, newly developed process t echnologies will make for more complex chips. For this reason, high performance test equipment is needed to verify SoC performance in today’s IC production tests. However, mixed-mode ATE systems with 10 GHz test capability add signifi cant test costs to manufactured part costs, and complicated test procedures require increased testing ti me. Therefore, traditional ATE tests are no longer low cost, and chip designers and test en gineers want to find more advanced testing methods for more highly in tegrated chips.

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2 A proposed solution for the high cost of test s is embedded RF test. To verify chip performance, some of the parameters, for example s-parameters, may be extracted from the IC for RF testing. A method of RF micr owave component on-chip or on-wafer test has potentially huge t echnical advantages compared to traditional measurement methods. One advantage of on-wafer measurements is the elimination of pa ckage effects, and another advantage is that there are fewer comp lex RF test fixture e ffects than traditional measurement methods. Due to these advantag es, embedded RF test methods may support more accurate component characterization. The important test trade off in this on-chip test research is test accuracy vers us required area and power on the IC. 1.2 Research Goals The first goal of this research is to generate lumped passive circuits for 5 GHz embedded test of RF SoCs. Many companies have been trying to integrate the whole WLAN system on a SoC. Such a high level of integration calls for research to embedded test for the WLAN SoC. A WLAN embedded IC test can require 5 GHz directional couplers, baluns, and dividers, which are pres ented in this work. Lumped passive 5 GHz ICs were developed to realize these compact test devices. Measurement results show excellent agreement with simulation for the integrated 5 GHz coupl er, balun and divider designs. The second goal of this research is to r ealize embedded loop back for RF IC test. This research explores the use of on-chip or on-wafer loopback for verifying performance of 5 GHz wireless LAN IC circ uits. The loopback measurement is made for a simplified transceiver circuit. This resear ch is exploratory in nature, an d is the first attempt at a new on-chip RF test technique.

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3 Finally, this research develops a new embedded s-parameter measurement method. At RF microwave frequencies, embedded s-pa rameter measurements are considered an essential measurement method. The s-paramete rs of a DUT (DeviceUnder-Test) provide a clear interpretation of the small signal transmission and reflection performance of the DUT. The detection and measurement of leve l and phase difference between two signals are key points of s-pa rameter measurements. 1.3 Outline of the Dissertation This dissertation has been organized in to six chapters and an appendix. An overview of this research is given in the current chapter, including the importance of embedded RF test, the research goals, and the scope of this work. An appendix presents a spiral inductor modeling method using HFSS. In this appendix, more accurate modeling methods and faster simulation methods are reviewed. Chapter 2 presents some lumped passive circuits for embedded test of RF SoCs. In this chapter, a lumped passive directiona l coupler, lumped pass ive divider, lumped passive balun, and lumped passive hybrid for embedded test and differential measurement of RF ICs are reviewed. In chapters 3 and 4, a met hod for embedded loop back of RF ICs Test is presented. RF switches, and loopback test circuits have been designed and characterized for embedded test of RF ICs. Simplified transcei ver on-chip loopback ci rcuits were built and tested, and the performance is shown as well as the design and probing difficulties. An embedded s-parameter measurement me thod is introduced in chapter 5. This chapter discusses basic concep ts and shows a block diagra m to implement the proposed idea, and also discusses the weak point s and design bottlenecks of the embedded sparameter measurement method. To realize th e proposed idea, a di rectional coupler,

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4 DPDT (Double-Pole Double-Th row) switch, peak detector and phase detector are designed and a possible implementation method is briefly presented. Chapter 6 summarizes the dissertation and presents future work for after the dissertation.

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5 CHAPTER 2 LUMPED PASSIVE CIRCUITS FOR EMBEDDED TEST OF RF SOCS 2.1 Introduction Recent design trends in RF/analog tec hnologies show integration Systems-on-aChip (SoCs) and include mixed-signal/RF ci rcuit design. In today’s production tests, expensive equipment is needed to verify SoC performance. For example, mixed-mode ATE systems with 3 GHz test capability can add significant test costs to a manufactured part cost. BPF ANT ANT SW SW LNA BPF MIXER HPA BPFAMP MIXER LO SYNTH Receiver TransmitterDeMOD MOD AMP BPF ANT ANT SW SW LNA BPF MIXER HPA BPFAMP MIXER LO SYNTH Receiver TransmitterDeMOD MOD AMP Fig. 2-1. RF&IF block diagram To realize RF/analog signal test on the So C, each part (RF and IF block and digital control block) should be tested simultaneousl y. As shown in Figure 2-1, the RF and IF blocks consist of three function units (receiv er, transmitter, and synthesizer). Testing the

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6 functional unit (receiver, transmitter, and synthesizer), instead of testing each small subcircuit, is considered to be a reasonable tr adeoff between test efficiency and completeness for a mature and well understood IC part. Care must be taken so a part with a strong transmitter does not make a weak receiver look like it meets a test specification. To test the transmitter, the output signal at the high power amplifier (HPA) should be monitored. Therefore, monitoring the si gnal power level of each subcircuit without affecting the signal path is a key in realiz ing the embedded test of an RF/analog SoC signal. A noninvasive power monitoring circuit may consist of a dire ctional coupler and a power detector as shown in Figure 2-2. The DC output values of the detector correspond to the power level. In this way, an onchip test can monitor DUT power without disturbing circuit operation. Theref ore, a directional coupler is the key component for this embedded test. A working sampler (directiona l coupler) is designed for 5 GHz wireless LAN IC test. There are two major specificati ons to characterize th e performance of the directional coupler. One is the coupling and another is the insertion loss. In this research, a 10-dB directional coupler wa s designed for 5 GHz. The specification of the commercial directional coupler (Anaran 10610-10 ) is shown in Table 2-1. Table 2-1 Specification for the co mmercial directional coupler 50 ohm Impedance 1 dB max Insertion loss 10 0.5 dB Coupling 50 ohm Impedance 1 dB max Insertion loss 10 0.5 dB Coupling The coupling ratio at coupling port is 10 0.5 dB and th e insertion loss is lower than 1 dB. The dimension of this directi onal coupler is bigger than 30mm x 50 mm.

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7 Table 2-2 Specification for the lump ed passive directional coupler 50 ohm Impedance 2 dB max Insertion loss 10 0.5 dB Coupling 50 ohm Impedance 2 dB max Insertion loss 10 0.5 dB Coupling The proposed directional coupl er is designed using the lu mped passive circuits to realize it on the silicon wafer. So the target area for this directional coupler is less than 1 mm2. Even though dramatically less area is employed compared with a commercial directional coupler, the proposed specification for the lumped directional coupler has the same coupling and less than 2 dB insert ion loss as shown in the Table 2-2. Coupler DetectorInputThrough IsolatedCoupled OutputCoupler DetectorInputThrough IsolatedCoupled Output Fig. 2-2. Directional coupler and detector Other proposed lumped passive circuits are the lumped passive balun and the lumped passive divider. Most of RF app lications adopt single-ended (common-mode) analyses. But in balanced circuits, common-mo de analysis and differe ntial-mode analysis must be considered [Bok97] [Bok95]. Similar to the directional coupler case, the working sample is designed for a 5 GHz wireless LAN IC test. There are three major specifications to characterize th e performance of the divider. One is the phase difference

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8 between two dividing ports and th e second is the insertion loss The third is the amplitude difference between two ports. The lumped pa ssive divider was de signed for 5 GHz. The specification of the commercial divider (M eca 802-2-6.000) is shown in Table 2-3. The phase difference betwee n two ports are 0 4 and the insertion loss is low than 1 dB. The amplitude difference between two ports is within 1.5 dB and the dimension of this divider is bigger than 25mm x 20 mm. Table 2-3 Specification for the commercial divider 50 ohm Impedance 1.5 dB max Amplitude difference 0 4 Phase difference 1.0 dB max Insertion loss 50 ohm Impedance 1.5 dB max Amplitude difference 0 4 Phase difference 1.0 dB max Insertion loss The proposed divider is designed using the lumped passive circuits to realize it on the silicon wafer. Similar to th e lumped passive direction c oupler, the target area for the lumped passive divider is less than 1 mm2. The proposed specifica tion for the lumped passive divider is shown in the Table 2-4. Table 2-4 Specification for the lumped passive divider 50 ohm Impedance 1.5 dB max Amplitude difference 0 4 Phase difference 1.5 dB max Insertion loss 50 ohm Impedance 1.5 dB max Amplitude difference 0 4 Phase difference 1.5 dB max Insertion loss On the other hand, analyzing the differen tial-mode [Bok00] requires a device (a balun) that divides signals into two branch es with equal magnitude and opposite polarity (180 out of phase). This working sample also is designed for 5 GHz wireless LAN IC test. Similar to the divider, there are thr ee major specifications to characterize the performance of the balun. One is the phase difference between two dividing ports and the

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9 second is the insertion loss. The third is the amplitude difference between two dividing ports. The lumped passive balun was designe d for 5 GHz operation. The specification of the commercial balun (Johanson Technology 5250BL14B100) is shown in Table 2-5. The phase difference between two ports are 180 15 and the insertion loss is lower than 1 dB. The amplitude difference between the two ports is within 1.5 dB and the dimension of this divider is roughly 1.6mm x 0.8 mm. Table 2-5 Specification for the commercial balun 50 ohm Impedance 1.5 dB max Amplitude difference 180 15 Phase difference 1.0 dB max Insertion loss 50 ohm Impedance 1.5 dB max Amplitude difference 180 15 Phase difference 1.0 dB max Insertion loss The proposed balun is designed using the lump ed passive circuits to realize it on the silicon wafer. Similar to the lumped passive di rectional coupler, th e target area for lumped passive divider is less than 1 mm2. The proposed specifica tion for the lumped passive balun is shown in Table 2-6. Table 2-6 Specification for the lumped passive balun 50 ohm Impedance 1.5 dB max Amplitude difference 180 15 Phase difference 1.5 dB max Insertion loss 50 ohm Impedance 1.5 dB max Amplitude difference 180 15 Phase difference 1.5 dB max Insertion loss As mentioned already, for embedded IC test, a directional coupler, a balun and divider are needed. The traditional method to realize these pass ive circuits uses microstrip lines or lumped passive compone nts [Par89]. Unfortunately, the quarter-wave length at 5 GHz is almost 8 mm and is too big for on-chip realization. Therefore making the lumped-passive circuits is the only practical option.

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10 2.2 Design of Lumped Passive Directional Coupler The lumped passive circuit design style is as follows. First, a distributed microstrip circuit is designed with a larg e area, and then a compact lu mped equivalent circuit is extracted from the distributed circuit. Second, the design of the coupled line directional coupler for 5 GHz is presented. The main functi on of this directional coupler is to sample power from sources. Directional couplers[ Bah03] are also used for measuring unknown impedances, detecting antenna faults, and combining and or splitting power. There are various types of direc tional couplers in cluding branch line coupler s, wave guide couplers, Lange couplers [Lan69], Wilkinson divide rs [Wil60] and coupled line directional couplers [Mon55]. The coupled line directional coupler [Poz 97][Mal88][Mal79] is one of the most popular directional couplers at microwave frequency bands. When the transmission lines are located close to each othe r, power will be coupled as shown in Figure 2-3. The coupler consists of a pair of transmission lin es and is modeled as a 4-port network. Most of the launched power at port 1 will be delive red to port 4. Due to the interaction of the electromagnetic fields, some power will be coupled to port 2. As shown in Figure 2-2, if port 1 and port 4 are considered the input port and output port, respectively, port 2 becomes the coupling port and por t 3 becomes an isolation port. Fig. 2-3. The basic concept of directional coupler

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11 Typically the coupled transmission lines operate in TEM mode, and the electrical characteristics of the coupled lines can be modeled as a function of the effective capacitances between th e lines. As shown in Figure 24, the coupled transmission lines parameters C11, C22, and C12. C12 are defined as the capacitance between the two transmission lines, while, C11 and C22 are defined as the capacitance between the transmission lines and the ground. If the widt hs of the two transmission lines and the distance of the transmission lines from ground are the same, then C11 will equal C22. 12C12C11C22 12C12C11C22 Fig.2-4. Equivalent capacitance network In analyzing the coupled line directional coupler, one should consider the even and odd modes. As shown in Figure 2-5-(a), in the even mode, the current flows in the same direction with the same magnitude, and the electric flux is symmetric with respect to the H-wall. Conversely, in the odd mode, as shown in Figure 2-5-(b), the current flows in the opposite direction with the same magnitude, and the electric flux is also symmetric with respect to the E-wall. In this case, conducto r 1 is emitting electric flux while conductor 2 is sinking flux thus making the E-wall an e quipotential surface with V=0, and the E-wall acting as the ground plane.

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12 12 H-wall +V +V 12 H-wall +V +V (a) Even-mode 12 E-wall +V -V 12 E-wall +V -V (b) Odd-mode Fig. 2-5. Even mode and odd mode of transmission line As shown Figure 2-5, the coupled line directional coupler consists of two transmission lines. For analysis, each tran smission line can be modeled as shown in Figure 2-6. The voltage at the s ource (x=-l) and the load (x=0 ) can be equated as follows: l j L se V V (2.1) l j O l j se e V l V V (2.2) O LV V V 1 0 where O L O L OZ Z Z Z (2.3)

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13 The input impedance of the transmission lin e with the characteristic impedance of Z0, and the termination load of ZL, can be expressed as, (2.4) Also the voltage at the source can be expressed as the function of the voltage of the load (VL), the load impedance (ZL), the characteristic impedance (ZO), and the electrical lengthl (2.5) Fig. 2-6. Transmission line model If V1=VS, V4=VL, l= Z1=1/y1=ZO/ZL, then sin cos sin cos 11 1 1 1 4j y y jZ V V (2.6) The coupling factor is (2.7) (2.8) OO Oe OO OeZ Z Z Z C C C ZO Oe 1 1 Z l jZ Z l jZ ZL L tan tan Z Z0 0 0 in l Z Z j lL sin cos V V0 L S

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14 (2.9) To design a 10 dB coupled direc tional coupler, one calculates Zoe and Zoo. To realize the coupled line direc tional coupler, the line width (W) value and the line spacing (S) between two lines should be calculated first. This complex manipulation is beyond the dissertation focus. To convert a coupledline-directional coupler to a lumped-passivedirectional-coupler [Par 89] [Son02], first the even-mode is handled. Yin Yoe Yin Yoe (a) Coupled-line coupler CeCe 2 Le Yin CeCe 2 Le Yin (b) Equivalent lumped model Fig. 2-7. Even mode analysis of coupler and equivalent lumped model The directional coupler has horizontal symmetry (with respect to the two parallel lines) due to the H-field wall a nd vertical symmetry (symmetr y axis with respect to the center of transmission lines) due to its symmet rical structure. Therefore, the analysis for half of one transmission line can be used for the whole directional coupler as shown in C C ZO OO 1 1 Z

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15 Figure 2-7. If the center symmetric line is open as shown in Figure 2-8, the input impedance of the coupler is e insC Z 1 2 cot jZ 0e (2.10) 2 tan jZ 0o esC (2.11) 2 tan Z 0o eC (2.12) /2 Zin Zoe /2 Zin Zoe (a) Even-mode open case Ce Le Zin Ce Le Zin (b) Equivalent Circuit Fig. 2-8. Open case of center symmetric line in even-mode and equivalent circuit

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16 Now, consider the shorted case of the cen ter symmetric line in the even-mode as shown in Figure 2-9. This is similar to the ope n case, the input admittances of coupler are 2 tan jZ 0e inZ (2.13) 2 cot Z j 1 0o inY (2.14) e esL 1 C s Yin (2.15) /2 Yin Zoo /2 Yin Zoo (a) Even-mode short case Ce Le Yin Ce Le Yin (b) Equivalent Circuit Fig. 2-9. Short case of center symmetric li ne in even-mode and equivalent circuit The value of Le is delivered from,

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17 e e 0osL 1 C 2 cot jZ s (2.16) sin 2 Z oeeL (2.17) The next step is solving for the oddmode case. The odd-mode, with the E-wall located horizontally, acts as a ground plan e at the center as shown in Figure 2-10. Zin Zoo Zin Zoo (a) Coupled-line coupler Zin Ce Ce LeLe 2C o Lo Lo Zin Ce Ce LeLe 2C o Lo Lo (b) Equivalent lumped model Fig. 2-10. Odd mode analysis of c oupler and equivalent lumped model For a vertically symmetric shorted line, th e equivalent circuit is shown in Figure 211.

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18 / 2 Yin Yoo / 2 Yin Yoo (a) Odd-mode short case Yin Le Ce Lo Yin Le Ce Lo (b) Equivalent Circuit Fig. 2-11. Short case of center symmetric line in odd-mode and equivalent circuit The input impedance of transmission lin e as shown in Figure 2-11-(a) becomes (2.18) (2.19) And the input admittance of the equivalent circuit in Figure 2-11-(b) is (2.20) The even-mode equivalent parameters are derived (Ce, Le, Zoo and Zoe); Lo is formed by using a simple manipulation. sin 1 2 2 tan 2 cot 1 oo oo oe oZ Z Z L (2.21) Since =90, Lo simplifies as 2 cot oo injY Y 2 tan jZ 0 inZ o eL j 1 L j 1 e inC j Y

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19 oo oe oZ Z L 1 (2.22) Given that the vertical symmetric line is open, the equivalent circuit as shown in Figure 2-12-(b). / 2 Yin Yoo Open / 2 Yin Yoo Open (a) Odd-mode short case Yin Le Ce Lo Co Yin Le Ce Lo Co (b) Equivalent Circuit Fig. 2-12. Open case of center symmetric line in odd-mode and equivalent circuit The input impedance of transmissi on line in Figure 2-12-(a) becomes (2.23) (2.24) And the input admittance of the equiva lent circuit in Figure 2-12-(b) is (2.25) 2 tan oo injY Y 2 cot jZ 0 inZ o e e inC j L C j Y 1 j 1 L j 1 o

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20 The even-mode and odd-mode equivalent parameters (Ce, Le, Lo, Zoo and Zoe) are already found. Co is formed by using a simple manipulation. oo oe oe oo oe oZ Z Z Z Z C 1 sin 2 (2.26) Since =90, simplified Co is oo oe oe oo oe oZ Z Z Z Z C 1 2 (2.27) Finally, the equivalent lumped model of a directional coupler with every element is shown in Figure 2-13. Zoe, Zoo S y mmetric plane Zoe, Zoo S y mmetric plane (a) Coupled-line coup ler Port 1Port 3 Port 2 Port 4 Ce Ce CeCe LeLe Le Le 2Lo Co 2Lo Port 1Port 3 Port 2 Port 4 Ce Ce CeCe LeLe Le Le 2Lo Co 2Lo (b) Equivalent lumped model Fig. 2-13. Directional coupler and equivalent lumped model

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21 2.3 Design of Lumped Passive Balun and Divider Two other important on-chip te st circuits are the balun a nd the divider. The balun is a three-port network with a 180 phase diffe rence between the two output ports. With reference to the balun shown in Figure 2-14, a signal launched into port 1 will be evenly split into two components with a 180 pha se difference at port 2 and port 3. Fig. 2-14. Symbol for a balun The divider, is also a thr ee-port network, but with the same phase between the two output ports. As shown in Figu re 2-15, a signal launched into port 1 will be evenly split into two in-phase components forwards 2 and port 3. Fig. 2-15. Symbol for a divider The balun is created by combining a 90 pha se delay branch and a 270 phase delay branch. The divider is created by comb ining two 90 phase delay branches. The

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22 scattering matrix of a 90 phase delay branch is labeled as [S1] and the scattering matrix of a 270 phase delay branch is labeled as [S2]. 0 j j 0 0 90 1 90 1 0 S1 (2.28) 0 j j 0 0 270 1 270 1 0 S2 (2.29) This phase delay branch of the scattering matrix [S1] can be modeled as a model as shown in Figure 2-16. All series and s hunt components are given as admittances Y1, Y2 and Y3. Fig. 2-16. model The ABCD parameters for Figure 2-16 are; (2.30) (2.31) (2.32) 31 Y B 3 21 Y Y A 3 2 1 2 1Y Y Y Y Y C

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23 (2.33) If Y1=Y2, then the ABCD parameters reduce into; (2.34) (2.35) (2.36) (2.37) Using a table of conversions for two-port network parameters, th e s-parameters of this model are obtained. (2.38) (2.39) (2.40) (2.41) D CZ Z B A D CZ Z B A S 0 0 0 0 11 1 2 1 2 1 20 3 0 0 3 1 2 0 2 1 2 0 3 1 2 0 2 1 Z Y Z Z Y Y Z Y Z Y Y Z Y D CZ Z B A D CZ Z B A S 0 0 0 0 22 1 2 1 2 1 20 3 0 0 3 1 2 0 2 1 2 0 3 1 2 0 2 1 Z Y Z Z Y Y Z Y Z Y Y Z Y D CZ Z B A BC AD S 0 0 122 1 2 1 2 20 3 0 0 3 1 2 0 2 1 0 3 Z Y Z Z Y Y Z Y Z Y D CZ Z B A S 0 0 212 1 2 1 2 20 3 0 0 3 1 2 0 2 1 0 3 Z Y Z Z Y Y Z Y Z Y 3 2 1 12 Y Y Y C 3 11 Y Y A 3 11 Y Y D 31 Y B 3 11 Y Y D

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24 (2.42) Since S11 = S22 = 0, (2.43) (2.44) (2.45) (2.46) Substituting Y3 to equation “S12 = -j”, (2.47) 0 1Z j Y (2.48) 0 11 Z C (2.49) 0 2 0 1 2 0 2 1 32 1 Z j Z Y Z Y Y (2.50) 0 3Z L (2.51) The other phase delay branch of the scattering matrix [S2] can be modeled as a T model as shown in Figure 2-17. All series a nd shunt components are given as impedances Z1, Z2 and Z3. 1 2 1 2 20 3 0 0 3 1 2 0 2 1 0 3 12 Z Y Z Z Y Y Z Y Z Y S j Z Y Z Y 1 10 1 0 1 2 0 1 2 0 2 1 32 1 Z Y Z Y Y 1 23 1 2 0 1 Y Y Z Y 1 22 0 3 1 2 0 2 1 Z Y Y Z Y 0 1 2 1 2 1 20 3 0 0 3 1 2 0 2 1 2 0 3 1 2 0 2 1 11 Z Y Z Z Y Y Z Y Z Y Y Z Y S 0 j j 0 S 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 2 1 2 1 2 1 20 3 0 0 3 1 2 0 2 1 2 0 3 1 2 0 2 1 0 3 0 0 3 1 2 0 2 1 0 3 0 3 0 0 3 1 2 0 2 1 0 3 0 3 0 0 3 1 2 0 2 1 2 0 3 1 2 0 2 1Z Y Z Z Y Y Z Y Z Y Y Z Y Z Y Z Z Y Y Z Y Z Y Z Y Z Z Y Y Z Y Z Y Z Y Z Z Y Y Z Y Z Y Y Z Y

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25 Fig. 2-17. T-model The ABCD parameters for Figure 2-17 are; (2.52) (2.53) (2.54) (2.55) If Z1=Z2, then the ABCD parameters reduce into, (2.56) (2.57) (2.58) 31 Z C 3 11 Z Z A 31 Z C 3 11 Z Z A 3 2 1 2 1Z Z Z Z Z B 3 21 Z Z D 3 2 1 12 Z Z Z B

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26 (2.59) Using table of Conversions for Two-Port Network Parameters, the S-parameters of this T model are obtained. (2.60) (2.61) (2.62) (2.63) (2.64) Since S11 = S22 = 0, (2.65) (2.66) (2.67) Substituting Z3 to equation “S12 = j”, 0 23 1 1 2 0 Z Z Z Z 1 2 1 2 0 32 Z Z Z Z 0 2 2 23 1 1 3 1 0 2 0 3 1 1 2 0 11 Z Z Z Z Z Z Z Z Z Z Z S 3 11 Z Z D D CZ Z B A D CZ Z B A S 0 0 0 0 11 3 1 1 3 1 0 2 0 3 1 1 2 02 2 2 Z Z Z Z Z Z Z Z Z Z Z D CZ Z B A D CZ Z B A S 0 0 0 0 22 3 1 1 3 1 0 2 0 3 1 1 2 02 2 2 Z Z Z Z Z Z Z Z Z Z Z 3 1 1 3 1 0 2 0 3 02 2 2 Z Z Z Z Z Z Z Z Z D CZ Z B A BC AD S 0 0 122 D CZ Z B A S 0 0 212 3 1 1 3 1 0 2 0 3 02 2 2 Z Z Z Z Z Z Z Z Z 0 j j 0 S 3 1 1 3 1 0 2 0 3 1 1 2 0 3 1 1 3 1 0 2 0 3 0 3 1 1 3 1 0 2 0 3 0 3 1 1 3 1 0 2 0 3 1 1 2 02 2 2 2 2 2 2 2 2 2 2 2 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z

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27 (2.68) jZ Z 1 (2.69) 0 11 Z C (2.70) 0 1 2 1 2 0 32 jZ Z Z Z Z (2.71) 0 3Z L (2.72) 2.4 Simulation of Lumped Passive Devices The Directional Coupler is composed of six spiral induct ors and five MIM capacitors as shown in Figure 2-18. Fig. 2-18. Schematic of lumped passive directional coupler 3 1 1 3 1 0 2 0 3 0 122 2 2 Z Z Z Z Z Z Z Z Z S j Z Z Z Z 1 0 1 0

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28 Most of the signal launched in to port 1 (Input Port) will ar rive at port 3 (Transmit Port). The rest of the signal launched into port 1 will be coupled by port 2 (Coupling Port) with its own sampling ratio. A 10 dB Lumped passive Dire ctional Coupler is designed as an example. Every passive compone nt of the lumped-passive coupler circuits are calculated using values as shown in Table 2-7. Table 2-7 Calculation and simulation value for the directional coupler The following procedure is used to layout of each of the lumped-passive circuits. The layout of the directional coupler is shown in Figure 2-19. As shown in Figure 2-19, the lumped-passive direction coupler is fu lly symmetric so each bond path is connected to two spiral inductors a nd a MIM capacitor. Six spiral inductors and five MIM capacitors are located with symmetric st ructures and each passive component is connected with a metal line as shown in Figure 2-19. Ideally, these inner metal lines are used for connection between each passive co mponent and are considered short lines. Unfortunately, these metal lines have resistance and parasitics that create critical circuit side effects. To predict unwanted side effects, ever y connection metal line was modeled and considered in simulation.

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29 Fig. 2-19. The layout of the lump ed-passive directional coupler Fig. 2-20. The model of interconnection line For example, one of the bond pad branches located inside dotted circle in Figure 219 is modeled as shown in Figure 2-20. One single metal structure can be modeled as a

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30 combination of six metal segments. A single metal line on silicon wafers can be modeled as shown in Figure 2-21 [Nik00]. Each meta l line has a series inductance L and series resistance rx and parasitic capacitance C1 and C2 that exist between the metal structure and substrate. Also, there exists substrate resistances R1 and R2. L rxC1R1C2R2 L rxC1R1C2R2 Fig. 2-21. The equivalent circuit of metal line All the parasitics in the single metal st ructure shown in Figure 2-20 are calculated by the EM simulator ASITIC which is develope d by Berkeley and each value is shown in Table 2-8 Table 2-8 Calculated value of the equiva lent circuit for the directional coupler Finally, a 10 dB lumped-passive-directional coupler was designed with all the side effects of the connecting metal lines. Two si mulation results are shown in Figure 2-22.

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31 The original simulation result does not consid er parasitics of metal connection lines and the complete simulation result includes all pa rasitics of metal line connections. As shown in Figure 2-22, at 5 GHz the original simulati on result for the signal magnitude at port3 is approximately -0.9 dB, and about 80 % of the power will be delivered to port3 (transmit port). Also, at 5 GHz the original simulation result for the magnitude at port2 is approximately -12 dB, and about 6 % of th e power will be coupled to port2 (coupling port). The complete simulation results for the magnitude at port3 and port2 are -1.7 dB and -9.0 dB respectively. The insertion loss (S31) is increased and coupling (S21) is decreased due to inter-connection loss and pa rasitics. These unwanted parasitics change the frequency response of the lump ed passive directional coupler. -30 -25 -20 -15 -10 -5 0 12345678FrequencydB Sim_original s21(dB) Sim_original s31(dB) Sim_complete s21(dB) Sim_complete s31(dB) Fig. 2-22. Simulation results of lumped-passive-directional coupler A divider has two 90 phase shift branches as shown in Figure 2-23-(a). The signal launched into the input port will arrive at the out put ports with the same magnitude and phase. A divider is composed of two spiral inductors, four MIM cap acitors and one polyresistor as shown in Figure 2-23-(b).

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32 (a) (b) Fig. 2-23. Schematic of lumped passive divider The passive components of lumped-passive circuits are calculated using introduced equation as shown in Table 2-9. Table 2-9 Calculation and si mulation value for divider

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33 The layout of the following directional c oupler is shown in Figure 2-24. Passive components are used for circuit function. Two spiral inductors, a poly resister and four MIM capacitors are located with symmetric structures and each passive component is connected with metal lines as shown in Figur e 2-24. These metal lines have resistances and parasitics. These unwanted resistances and pa rasitics give rise to critical circuit side effects. Fig. 2-24. The layout of the lumped-passive the divider To predict unwanted side effects, connecting metal lines are modeled for a complete simulation. For example, one of th e bond pad branches located inside the dotted circle in Figure 2-24 is modeled as shown in Figure 2-25. One single metal structure can be modeled as a combination of these six metal segments. Each metal line has a series inductance L and seri es resistance rx. And parasitic capacitance C1 and C2 can model each metal structure and substrate. Also, there exists substrate resistance in R1 and R2.

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34 Therefore the single metal line on this silicon wafer can be modeled as shown in Figure 2-21 [Nik00]. Fig. 2-25. The model of interconnection line All parasitics in the single metal struct ure as shown in Figure 2-25 are calculated by EM simulator ASITIC developed by Berkeley and each value is shown in Table 2-10 Table 2-10 Calculated value of the equivalent circu it for the divider Two simulation results are shown in Figur e 2-26. The original simulation result does not consider any metal line parasitics a nd the complete simulation result includes all the metal line parasitics. As shown in Figure 2-26, at 5 GHz the original simulation result for the magnitude at the output ports is approximately -3 .8 dB. The phase balance

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35 between output ports is almost 0 throughout the frequency ba nd of 1 to 10 GHz. Further, up to 5 GHz, the complete simulation result for the magnitude at the output ports is approximately the same as the original simu lation result. At high frequency, frequency response is altered due in part to parasitic effects especially parasitic capacitances between the metal structure and the substrate. The phase balance between output ports is not changed significantly and stays almost 0 throughout the frequency band of 1 to 10 GHz. -16 -14 -12 -10 -8 -6 -4 -2 12345678910frequency(GHz)(dB) Sim_original S31(dB) Sim_original S32(dB) Sim_complete S31(dB) Sim_complete S32(dB) (a) -250 -200 -150 -100 -50 0 12345678910 frquency(GHz)(deg) Sim_original S31(deg) Sim_original S32(deg) Sim_complete S31(deg) Sim_complete S32(deg) (b) Fig. 2-26. Simulation results of a lumped-passive divider

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36 A 180 hybrid is composed of three 90 pha se shift branches and a 270 phase shift branch as shown in Figure 2-27. Fig. 2-27. A ring hybrid (rat-race) A 90 phase shift branch is composed of a spiral inductor and two MIM capacitors; while a 270 phase shift branch is com posed of a spiral inductor and two MIM capacitors. So the hybrid is com posed of four spiral inductor s and six MIM capacitors as shown in Figure 2.28. C1C1C2C2C2C2L L L L C1C1C2C2C2C2L L L L Fig. 2-28. Schematic of a lumped passive hybrid

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37 A hybrid is designed utilizing lumped pa ssive components is calculated using values Table 2-11. Table 2-11 Calculation and si mulation value for the hybrid As shown Figure 2-29, at 5.1 0.7 GHz, the original simulation and complete simulation results show that the magnitude si mulation in output por ts is approximately equal to -4.3 dB. The phase balance between these output ports is almost 180 at 5.1 0.7 GHz in the original simulation. At high frequency, especially above 6 GHz, transfer characteristics are degraded due to parallel parasitic capacitance between metal structures and the substrate. -25 -20 -15 -10 -5 0 12345678910 Frequency(GHz)(dB) Sim_original S12(dB) Sim_original S42(dB) Sim_complete S12(dB) Sim_complete S42(dB) (a) Fig. 2-29. Simulation results of the lumped-passive balun

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38 -450 -400 -350 -300 -250 -200 -150 -100 -50 0 12345678910frequency(GHz)(deg) Sim_original S31(deg) Sim_original S32(deg) Sim_complete S31(deg) Sim_complete S32(deg) (b) Fig. 2-29. Continued. 2.5 Fabrication Results of Lumped Passive Devices A lumped-passive-directional coupler wa s fabricated with the IBM 0.25 micron SiGe BiCMOS-6HP technology through MOSIS. The photomicrograph of the directional coupler is shown in Figure 2-30. The measurement of the directional coupler was performed by using an on-wafer Cascade Mi crotech Air Coplanar Probe (ACP) and a HP8510C Network Analyzer. The to tal chip size is about 1.2 mm2 (1.0 mm X 1.2 mm). Fig. 2-30. Die micrograph (1.0mm x 1.2mm) of the lumped-passive -directional coupler

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39 The measured results of the directiona l coupler are shown in Figure 2-31. The transmitted power at transmit port is -2.2 dB at 5.0 GHz including coupling loss of -1.1 dB. The coupling power at the c oupling port is -9.5 dB. As me ntioned before in Figure 231, the simulated transmit power at the tran smit port is -1.7 dB at 5.0 GHz and the simulated coupling power at th e coupling port is -9.0 dB. Compared to the previous simulation, the measurement results show good agreement. -30 -25 -20 -15 -10 -5 0 12345678Frequency(GHz)dB Measurement s31(dB) Measurement s21(dB) Simulation s21(dB) Simulation s31(dB) Fig. 2-31. Simulated and measured results of the lumped-passive -directional coupler The photomicrograph of the divider is s hown in Figure 2-32. A lumped-passivedivider was fabricated with the IBM 0.25 micron SiGe BiCM OS-6HP technology through MOSIS. The measurement of the dire ctional coupler was performed by using an on-wafer Cascade Microtech Air Coplanar Probe (A CP) and a HP8510C Network Analyzer. The total chip size is about 0.8 mm2 (1.0 mm x 0.8 mm).

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40 Fig. 2-32. Die micrograph (1.0mm x 0.8m m) of the lumped-passive divider The measured results of the divider are s hown in Figure 2-33. Th e insertion loss is 4.07 dB at 5 GHz including a signal split ter loss of 3 dB. Th e ripple is within 0.3 dB up to 6 GHz. The phase difference between the 2 output ports is within 0.5 throughout the frequency band of 1 to 10 GHz. Th e simulated insertion loss is -3.8 dB at 5 GHz and the phase difference between 2 output ports is 0. The measurement results show good agreement with the complete simulations. -16 -14 -12 -10 -8 -6 -4 -2 12345678910frequency(GHz)(dB) Measurement S31(dB) Measurement S32(dB) Simulation S31(dB) Simulation S32(dB) (a) Fig. 2-33. Simulated and measured re sults of the lumped-passive-divider

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41 -250 -200 -150 -100 -50 0 12345678910frquency(GHz)(deg) Measurement S31(deg) Measurement S32(deg) Simulation S31(deg) Simulation S32(deg) (b) Fig. 2-33. Continued. The photomicrograph of the balun is s hown in Figure 2-34. A lumped-passivebalun was fabricated with the IBM 0.25 micron SiGe BiCMOS-6HP technology through MOSIS. The measurement of the lumped-p assive-balun was performed by using an onwafer Cascade Microtech Air Coplanar Pr obe (ACP) and a HP8510C Network Analyzer. The total chip size is about 1.2 mm2 (1.0 mm x 1.2 mm). Fig. 2-34. Die micrograph (1.0mm x 1. 2mm) of the lumped-passive hybrid

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42 The measured results of the balun ar e shown in Figure 2-35. At 5 GHz, the insertion losses of the output ports, port1 and port4, ar e -4.41 dB and -4.47 dB respectively, including the 3 dB signal spli tter loss. The magnitude difference between the 2 output ports is only 0.06 dB at 5 GHz The phase balance be tween two output ports is approximately 183~186 at 5.1 0.7 GHz The simulated insert ion losses at 5 GHz are -3.81 dB at output port1 and -4.17 dB at output port4, and the phase difference between 2 output ports is 180~183 at 5. 1 0.7 GHz. Therefore, the measurement shows good agreement with the simulation. -25 -20 -15 -10 -5 0 12345678910Frequency(GHz)(dB) Measurement S12(dB) Measurement S42(dB) Simulation S12(dB) Simulation S42(dB) (a) -450 -400 -350 -300 -250 -200 -150 -100 -50 0 12345678910frequency(GHz)(deg) Measurement S31(deg) Measurement S32(deg) Simulation S31(deg) Simulation S32(deg) (b) Fig. 2-35. Simulated and measured re sults of the lumped-passive-divider

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43 2.6 Conclusion A lumped-passive directional coupler, lu mped-passive divider, and hybrid for embedded test and differential measurement of RF ICs have been designed and tested. As mentioned already, the traditional method to re alize these passive circuits uses microstrip line. Unfortunately, the quarter-w ave length of microstrip at 5 GHz is almost 8 mm and is too big for on-chip realization. Therefore making the lumped-p assive circuits is the only practical option to implement couplers, divi ders and baluns on the silicon wafer. 1) The chip size of a lumped-pa ssive directional coupler is 1 mm2 but only 0.45 mm2 core circuit area is required while th e commercial directi onal coupler needs 1500 mm2. To author’s knowledge, this is the fi rst attempt to design a miniature on-chip directional coupler design at 5 GHz. To provide more simu lation accuracy, the parasitics of metal lines for interconnection are mode led and considered for simulation. The transmitted power at transmit port is -2.2 dB at 5.0 GHz including coupling loss of 1.1 dB. Therefore the insertion loss of the lumped passive directional coupler is 1.1 dB. As shown in Table 2-2, the pr oposed insertion loss is lowe r than 2 dB. Another major specification is the coupling. The designed coupling ratio is 10 dB at 5 GHz and the proposed specification is 10 0.5 dB at 5 GHz. The measured coupling power at the coupling port is -9.5 dB. Therefore the de signed lumped passive directional coupler meets the proposed design specification. 2) Similar to the directional coupler, the chip size of a lumped-passive balun is 1 mm2 but only 0.4 mm2 core circuit area is required. Also this is the first attempt to design a miniaturized on-chip balun design at 5 GHz. To keep more accuracy in simulation, the parasitics of metal lines for interconnection are modeled and considered in simulation as

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44 in the directional coupler desi gn. At 5 GHz, the measured inse rtion losses of the output ports, port1 and port4, are 4.41 dB and 4.47 dB respectively, including the 3 dB divider loss. Therefore, the maximum measured in sertion loss is 1.47 dB when the proposed insertion loss specification maximum is 1.5 dB. The magnitude difference between the 2 output ports is only 0.06 dB at 5 GHz while the specification amplitude difference is lower than 1.5 dB. The phase balance betwee n the two output ports is approximately 183~186 at 5.1 0.7 GHz while the sp ecification phase difference is 180 15. Therefore the integrated lumped passive balun meets all of the proposed design specifications. 3) Similar to the directional coupler, the chip size of a lumped-passive balun is 0.8 mm2 but only 0.25 mm2 core circuit area is required. Also, this is the first attempt to design a miniaturized on-chip divider desi gn at 5 GHz. To keep more accuracy in simulation, the parasitics of metal lines fo r interconnection are modeled and considered for simulation similar to the di rectional coupler design. At 5 GHz, the measured insertion losses of the output ports are -4 .07 dB including the 3 dB di viding loss. Therefore, the maximum measured insertion loss is 1.07 dB while the specified maximum insertion loss is 1.5 dB. The magnitude difference between th e 2 output ports is lower than 0.02 dB at 5 GHz while the specified amplitude difference is lower than 1.5 dB. The phase balance between two output ports is approximately 0 up to 10 GHz while the specified phase difference is 0 4. Therefore the designed lu mped passive balun also meets all of the proposed design specifications. Through this research, the lumped passive directional coupler, divider and balun were designed for embedded RF IC test on-ch ip or on-wafer and these integrated lumped

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45 passive circuits meet all proposed specifica tion. These lumped pa ssive elements proved useful in a variety of on-c hip RF/microwave test system s including embedded loopback and on-chip s-parameter test system in future chapters.

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46 CHAPTER 3 EMBEDDED LOOPBACK FOR RF ICS TEST 3.1 Introduction Loopback test is one of the lo west cost test methods for verifying functionality in a communication circuit. This “go” or “no go” te st gives little insight into circuit failure mechanisms and is of little assistance in debugging a circuit ma nufacturing process. Thus, the loopback test is employed in mature product lines where cost is an over-riding concern [Heu99] [Lup03] or as a final test after other circuit tests. This work assesses the feasibility of on-chip loopback test for GHz wireless communication ICs. Industry uses off-chip loopback where transmit signals are r outed through a package I/O to a test board circuit and then back to the receiver of the IC under test. New, on-chip or on-wafer loopback circuits are designed for verifyi ng performance of 5 GHz wireless WLAN IC circuits in this research. Although loopb ack testing is common in mature network electronics, it has not been applied to on-chip RF systems because 1) there are potential signal path mismatches, crosstalk and signal leakage problems that adversely affect the RF/microwave circuit, 2) large amounts of area are consumed, and 3) new on-chip RF elements are required for implementation. In this dissertation, the author reports on the test block diagram, the test circuit design an d shows test data for loopback test; the key loopback sub-circuits are microwave attenuato rs and switches. Si mplified transceiver onchip loopback circuits have been built and te sted. In this dissertation, the performance and the design are presented. This research is exploratory in nature and is a first attempt at a new on-chip RF test technique.

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47 3.2 Embedded IC Test for WLAN SoCs Most wireless communications circuits (i ncluding WLAN) consist of three basic blocks (antenna, RF and IF block, and digi tal processing/control bl ocks) which are shown in Figure 3-1. In this figure, the RF and IF block contains a receiver, transmitter, local synthesizer, switch and band pass filter. RF & IF BLOCK Receiver Transmitter Switch & B.P.FLO SYNTHDIGITAL CONTROL BLOCK Demodulator Modulator Encoder MAC & PHY Controller LLC & Higher Layer Control RF & IF BLOCK Receiver Transmitter Switch & B.P.FLO SYNTHDIGITAL CONTROL BLOCK Demodulator Modulator Encoder MAC & PHY Controller LLC & Higher Layer Control Fig. 3-1. WLAN block diagram The receiver module communi cates to the digital pro cessing/control block through a demodulator and the transmitter module rece ives its input signal from a modulator connected to the digital block. Current i ndustry practices may utilize separate production tests for the transmitter and receiver RF and IF blocks and the digital processing/control block as well as a complete system test. Th is process can be costly. On-chip loopback methods potentially raise the test efficiency and lower test co st of the wireless LAN SoC in a mature design. Low cost tests will be critical for future low cost consumer parts. Figure 3-2 shows a WLAN bl ock diagram of the loopback test in which the transmitter signals test the receiver by conn ecting them to the receiver through RF switches with an attenuator in the signal path. In many commercial implementations, the

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48 High Power Amplifiers (HPA) are built us ing different technology (GaAs) and are separate from the silicon IC transceiver block. SYNTH RX BLOCK RF S/W S/W ANT 1 ANT 2 HPA LNA BPF AMP AMP AGC AMP AMPAMP BPFTX BLOCKMIXER MIXER ATT Test Circuit for Embedded testing Coupler RF S/W SYNTH RX BLOCK RF S/W S/W ANT 1 ANT 2 HPA LNA BPF AMP AMP AGC AMP AMPAMP BPFTX BLOCKMIXER MIXER ATT Test Circuit for Embedded testing Coupler RF S/W Fig. 3-2. Block diagram of embedded loopback RFIC test The HPA connects to the antenna (ANT) through the bandpass filter (BPF). In this loopback test example, test signals are amp lified via a preamplifier (AMP) and switched to either to the HPA input port or to the loopback attenuator and then the LNA via RF switches. The LNA requires a weak input si gnal to verify its performance which is created by the attenuator in the loopback signal path. For example, the minimum sensitivity of the wireless LAN is -65 dBm. If the amplifier output as shown in Figure 3-2 is -30 dBm, the input signal at LNA is -64 dBm. This signal is the low enough in strength to characterize the rece iver block: the loopback signal path is shown in the shaded region of Figure 3-2. In summary, Figure 3-2 shows the necessary circuits for demonstrating the transceiver RF embedded loopback test signal path; these consist of an AMP (preamplifier), a RF switch an attenuator, a second RF switch, and a LNA.

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49 3.3 Design of Loopback Circuit The key test circuits for implementing embedded loopback test are high-frequency attenuators which reduce the transmitted signal to sufficiently low test signal values and RF switches which are used to modify the signal path between te st operation and normal operation. There are various types of RF switches in communication circuits as like CMOS switches [Hua01], GaAs switches [G as78], MEMS switches [Pod00], PIN-diode switches [Cav92], and Ferrite switches [Cru89] Also, there are various types of attenuators such MOS active attenuators [Loh91], PIN-diode attenuators [Bae88], ferromagnetic attenuators [Tra98], thick film attenuators [Yaz91], and coaxial line attenuators [Cri79]. The resistor-based atte nuator [Poz97][Viz95] was selected as the most suitable for this embedded loopback RF IC test because it has a wideband circuit operation and compact implementation. Two ki nds of resistor-based attenuators are considered 1) -type and 2) T-type. Both attenuators are built from three on-chip resistors in two port networks as shown in Figure 3-3. (a) Pi-attenuator (b) T-attenuator Fig. 3-3. The resistor type attenuator

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50 The -type attenuator symmetric resistors R1 are the same value as shown in Figure 3-3-(a). If Zo is the port impedance and is defined as the attenuation value dB, K is defined as follows (3.1)(3.2). 2010 K (3.1) o oZ R Z R R V V K// //1 1 2 2 1 (3.2) As shown in Figure 3-3-(a), input impedance of the -type attenuator is matched at the port impedance Zo. ) // //(1 2 1o oZ R R R Z (3.3) From equation 3.2 o oZ R K Z R R // //1 1 2 (3.4) If “oZ R R //1 2 ” is “ oZ R K //1”, then oZ is o o o oZ R Z KR R Z R K R Z1 1 1 1 1// // // (3.5) With simple manipulation, oZ is o o o oZ KR Z R R Z KR Z1 1 2 1 2 1 (3.6) From equation 3.6, R1 is 1 11 K K Z Ro (3.7) K is the attenuation as shown in e quation 3.1, thus rewrite (3.7) as

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51 1 10 1 1010 10 1 oZ R (3.8) A parallel impedance of R1 and Zo is o o oZ R Z R Z R 1 1 1// (3.9) R1 is defined as equation (3.7), thus the equation 3.9 is K K Z K K K K Z Z K K Z Z K K Z Z Ro o o o o o o2 1 1 1 1 1 1 1 1 1 1 //1 (3.10) From equation (3.4) and equation (3.10), R2 is K K Z K Z R K Ro o2 1 1 // 11 2 (3.11) K K Z Ro2 12 2 (3.12) Finally, R2 is 20 10 210 ) 1 10 ( 2 oZ R (3.13) The T-type attenuator symmetric resistors R1 are also the same value as shown in Figure 3-3-(b). If Zo is the port impedance and is defined as the attenuation value dB, K is defined as same way as the -type attenuator. o o o oZ Z R Z R R Z R R R V V K 1 1 2 1 2 1 2 1// // (3.14) As shown in Figure 3-3-(b), input impedance of the T-type attenuator is matched at the port impedance Zo.

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52 ) //(1 2 1o oZ R R R Z (3.15) Rewrite the equation (3.15) as ) //(1 2 1o oZ R R R Z (3.16) From the equation (3.14) and (3.16), K is 1 1 1 1R Z Z R Z Z R R Z Z Ko o o o o o (3.17) Thus, R1 is 1 11 K K Z Ro (3.18) K is the attenuation as shown in e quation 3.1, thus rewrite (3.18) as 1 10 1 1010 10 1 oZ R (3.19) From the equation (3.16) o o oZ R R R R Z R R Z 1 2 1 2 2 1 (3.20) Rearrange the equation (3.20) as 1 2 1 22 R R R Zo (3.21) From the equation (3.18) and (3.21) 1 1 2 1 12 2K K Z R K K Z Zo o o (3.22) oZ K K R 1 22 2 (3.23) Finally, R2 is

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53 1 10 10 210 20 2 oZ R (3.24) For up to 30 dB attenuation, both -type and T-type can be realized on-chip but the T-type attenuator fails at greater than 40 dB attenuation. Table 3-1 shows R2 values of the T-type attenuator should be 1 or less for high attenuation values. Table 3-1. The resistor values of various attenuators 49.99 0.01 50.01 250k 80 49.97 0.03 50.03 79k 70 49.90 0.10 50.10 25k 60 49.68 0.32 50.32 7.9k 50 49.01 1.00 51.01 2.5k 40 46.93 3.17 53.27 789.78 30 40.91 10.10 61.11 247.50 20 25.97 35.14 96.25 71.15 10 R1 R2 R1 R2 Attenuation(dB) T-type Pi-type 49.99 0.01 50.01 250k 80 49.97 0.03 50.03 79k 70 49.90 0.10 50.10 25k 60 49.68 0.32 50.32 7.9k 50 49.01 1.00 51.01 2.5k 40 46.93 3.17 53.27 789.78 30 40.91 10.10 61.11 247.50 20 25.97 35.14 96.25 71.15 10 R1 R2 R1 R2 Attenuation(dB) T-type Pi-type These small resistors are difficult to integrate and easily altered by parasitic resistances. The -type topology is employed in 40 dB, 50 dB, and 60 dB on-chip attenuator designs. The attenuators are built with the IBM BiCMOS technology P+ polysilicon resistors, (good hi gh frequency response) with the same length and width, (minimize manufacturing variations). R1 is located symmetrically in the layout along the axis of R2. The second key component for the embedded loopback RFIC test is the RF switch: two SPDT (single-pole double-throw) switches are employed. As shown in Figure 3-4(a), the port1 is the input port, while port2 and port3 are the output ports. Figure 3-4-(b)

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54 shows that a SPDT (single-pole double-throw) switch can be realized by using two on-off switches. Port 1 Port 2 Port 3 Port 1 Port 2 Port 3 (a) Port 1 Port 2 Port 3 Port 1 Port 2 Port 3 (b) Fig. 3-4. The SPDT (single pole double throw) switches In good RF design, most of the launched power at switch port 1 will be delivered to one of the two output ports and a negligible am ount is delivered to th e other output port. In this paper, BiCMOS RF switches are c onstructed from MOSFETs because they prove useful in monolithic CMOS and BiCMOS SoC solutions, see Figure 3-5. The insertion loss, the most important specification of th e RF switch design, is controlled by the onresistance of the MOSFET. For this reason most RF switches, including these, employ only n-channel MOSFETs. As show n in Figure 3-5-(c), the parasitic capacitance between source and drain of the MOSFET is a dominant f actor in determining the isolation of the MOSFET. To realize the optimum RF switch, an equivalent ci rcuit is constructed and the optimum value of each equivalent component is found. To maintain a high frequency response, optimum length MOSFETs are used [Hua01].

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55 R SourceDrain Gate R SourceDrain Gate (a) R On-State SourceDrain R On-State R R On-State SourceDrain (b) C Off-State SourceDrain C Off-State C C Off-State SourceDrain (c) Fig. 3-5. N-channel MOSFET model Typical CMOS RF switches, according to the literature, are built from four nchannel MOSFET and four resistors as shown in Figure 3-6-a) [Hua01]. Port 2 Cont_Port2Cont_Port3 Port 3 Port 1 M1 M2 M3 M4 R1R3 R2 R4 Port 2 Cont_Port2Cont_Port3 Port 3 Port 1 M1 M2 M3 M4 R1R3 R2 R4 (a) Fig. 3-6. The schematic of RF switch

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56 Port 2 Cont_Port2Cont_Port3 Port 3 Port 1 M1M3 R1R3 Port 2 Cont_Port2Cont_Port3 Port 3 Port 1 M1M3 R1R3 (b) Fig 3-6. Continued. In these typical switches, the two MOSF ETs perform the switching functions and the additional two MOSFETs increase the isola tion. Isolation performance and test circuit area are traded off. In this application, this test circuit area is more important then its isolation performance because isolation can be compensated by other methods. For this reason, the RF switch is composed of two n-channel MOSFETs and two poly resistors as shown in Figure 3-6-b) in a compact area design. The parasitic model of M3 in Figure 3-6 is modeled as shown in Figure 3-7. To connect port1 to port2, Con_port2 is biased with high voltage and Con_port3 is biased with low voltage to disconnect port1 to port3. During this time, there is some power leakage through the pa rasitic capacitor Cgs3 of M3 as shown in Figure 3-7. Even though small amounts of power leaks th rough the parasitic capacitor Cgs3 of M3, the insertion loss may be decreased dramatica lly according to this leakage ratio because the gate of M3 is at low impedance ground. So all leakage signal flows into the low impedance. The other parasitics are not playing a critical role compared to Cgs3. Maintaining the high impedance at a gate of M3 is one good method to prevent leakage.

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57 M3 R3 Cgs3Cont_Port3 Substrate Csb3Cdb3Cgd3Cgb3 M3 R3 Cgs3Cont_Port3 Substrate Csb3Cdb3Cgd3Cgb3 Fig. 3-7. The parasitic model of n-MOS with control resistance A high resistance value (20 k ) is used to control resistor R3. By doing this, the gate impedance is changed from low impedan ce to high impedance and the effect of the parasitic capacitor is significantly decrease d. This in turn decreases the RF switch insertion loss by approximately 0.3 dB as show n in Figure 3-8. The CMOS gate length is the dominant RF switch insertion loss factor so the minimum length (250 nm device gate length, 400 nm drawn layout gate lengths) is used. -4.00 -3.50 -3.00 -2.50 -2.00 -1.50 -1.00 -0.50 0.00 1.02.03.04.05.06.07.08.09.010.0Frequency(GHz)Insertion loss (dB ) R=20k R=0 Fig. 3-8. The simulated results of the RF switch with and without control resistance

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58 As shown in Figure 3-2, the RF switch and RF attenuator are key components for the loopback test. To realize th is test, additional two amplifie rs are needed. One is a low noise amplifier (LNA) and the other is an amplifier (AMP) as s hown in Figure 3-2. A cascode low noise amplifier was designed as the low noise amplifier[Raz98]. The schematic diagram is shown in Figure 3-9. The transistor size is designed for optimum gain and noise figure. For input matching, two spiral inductors are used. One is 2.08 nH and another is 402 pH as shown in Figure 3-9. Similarly, for output matching, one spiral inductor and one MIM capacitor are used as shown in Figure 3-9. Fig. 3-9. The schematic of the cascode low noise amplifier (LNA) 3.4 Simulation of Loopback Sub-circuits and System Cadence SpectreS was used to design 5 GHz 30 dB, 40 dB, 50 dB, and 60 dB lumped passive -type attenuators. As shown in Fi gure 3-10, at 5 GHz the simulation

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59 results for the magnitude at port 2 for the 30 dB attenuator is approximately -30.1 dB. Similarly, the 40 dB attenuator has a -40.3 dB loss at 5 GHz, the 50 dB attenuator has a 50.1 dB loss at 5 GHz and the 60 dB attenuator has a -62.1 dB loss. This simulation includes parasitic parameters (capacitances) of the P+ Polysilicon resisters which degrade high frequency response. Fig. 3-10. Simulation result of pi-type attenuator In these typical switches, the two MOSF ETs perform the switching functions and the additional two MOSFETs increase the is olation. As shown in Figure 3-5-b), the resistance on on-state is the dominant RF switch insertion loss factor. The gate impedance can be modeled as shown in Figure 3-11.

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60 Fig. 3-11. The gate model for optimum insertion loss of RF switch The gate width can be modeled as a para llel resistor and parasitic capacitor as shown in Figure 3-11. As the width increa ses, the resistance becomes lower and the insertion loss of the RF switch decreases But simultaneously, the parasitic capacitor increases. The parasitic capacitors make the insertion loss of the RF switch worse. The simulation results which sweep the number of fingers in the MO SFET from 60 to 120 with a gate width of 900 nM is shown in Fi gure 3-12. When the number of finger is increased, the insertion loss becomes improves up to 84 fingers. If there are more than 84 fingers, the insertion loss becomes worse. So the 84 fingers are selected for the minimum insertion loss RF switch. In reality, it is difficult to layout an n-MOSFET with 84 fingers. For this layout, 84 metal lines are needed fo r every gate connection. This also causes unwanted parasitic capacitance. For practical realization of the MOSFET, the finger number is reduced from 84 to 8 and each ga te width is increased from 900 nM to 9400 nM. By doing this, the total gate width can be kept the same.

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61 Fig. 3-12. Simulated results of gate width (finger number) sweep from 60 to 120 at 5.2 GHz Similarly, the gate length can be modele d as the series resistance as shown in Figure 3-11. If the gate length is increase d, the resistance is increased also. The simulation results which sweep the gate le ngth from 400 nM to 1300 nM is shown in Figure 3-13. If the gate length is decreased, the insertion loss of the RF switch is also decreased. Finally, the insertion loss become s minimal when the gate length becomes 400 nM. The simulation results show up to a 400 nM gate length because IBM-6HP 0.25 technology can provide 400 nM as a minimum gate length. For this reason, a minimum length (250 nm device gate length, 400 nm draw n layout gate length) is used for the RF switch.

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62 Fig. 3-13. Simulated results of gate lengt h sweep from 400 nM to 1300 nM at 5.2 GHz Two simulations are performed to decide the optimum value of the RF switch. One is the sweeping gate length as shown in Figure 3-13 and another is the sweeping gate width as shown in Figure 3-12. -40 -35 -30 -25 -20 -15 -10 -5 0 12345678910 Frequency (GHz)( dB ) Simulaton (SW-on) Simulation (SW-off) Fig. 3-14. Simulated results of the RF switch Finally, the dimension of n-MOSFET RF switch is decided for optimum value according to various simulation results. As mentioned early, the minimum gate length is

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63 better for insertion loss and in creasing the gate width is not always good. The simulated optimum insertion loss of this n-channel MO SFET is 2 dB when the number of fingers is 8, the gate length is 400 nM, and the layout gate width is 9400 nM as shown in Figure 314. Fig. 3-15. The schematic of the cascode low noise amplifier with parasitics The schematic of cascode low noise amplifier with parasitics is shown in Figure 315. Every single metal line connection between transistors is modeled as an equivalent circuit as shown in Figure 3-22. All parasitics in the single metal plate as shown in Figure 3-15 are calculated by EM simulator ASITIC which was developed by Berkeley and each value is shown in Table 3-2.

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64 Table 3-2. Calculated value of the equivalent circuit for LNA 106.1 0.524 148.8 19.08 18 108.6 0.347 81.85 25.32 17 109.4 0.336 73.23 22.93 16 177.9 0.363 225.8 14.37 15 173.8 0.382 31.88 2.34 14 1307 0.053 98.26 3.87 13 1339 0.05 139.5 4.51 12 8.642 6.978 6237 141.4 11 308.7 0.222 222.5 10.93 10 0.13 3.845 203.9 9.68 9 308.9 0.221 203.9 9.68 8 4042 0.729 175.8 3.63 7 1930 0.356 175.8 3.63 6 1934 0.037 203.4 2.84 5 215.7 0.31 1323 20.62 4 53.69 1.33 350.5 28.38 3 307.5 0.22 96.4 9.17 2 307.3 0.21 17.37 6.79 1 R1,2(k) C1,2(fF) Rx(m) L(pH) 106.1 0.524 148.8 19.08 18 108.6 0.347 81.85 25.32 17 109.4 0.336 73.23 22.93 16 177.9 0.363 225.8 14.37 15 173.8 0.382 31.88 2.34 14 1307 0.053 98.26 3.87 13 1339 0.05 139.5 4.51 12 8.642 6.978 6237 141.4 11 308.7 0.222 222.5 10.93 10 0.13 3.845 203.9 9.68 9 308.9 0.221 203.9 9.68 8 4042 0.729 175.8 3.63 7 1930 0.356 175.8 3.63 6 1934 0.037 203.4 2.84 5 215.7 0.31 1323 20.62 4 53.69 1.33 350.5 28.38 3 307.5 0.22 96.4 9.17 2 307.3 0.21 17.37 6.79 1 R1,2(k) C1,2(fF) Rx(m) L(pH) Finally, the simulation result of the low noise amplifier with parasitics is shown in Figure 3-16. The simulated gain (S21) is 19 dB at 5.2 GHz and reflection at input and output ports are lower than -15 dB at 5.2 GHz. Fig. 3-16. Simulated results of the low noise amplifier with parasitics

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65 The embedded loopback circuit is modele d with the AMP (preamplifier), the two RF switches, the attenuator, and the LNA is shown in Figure 3-17. AMP ATT Port 1Port 2 LNA RF S/W RF S/W AMP ATT Port 1Port 2 LNA RF S/W RF S/W Fig. 3-17. The block diagram of the embedded loopback test model Similarly, every single metal line used fo r connection is modeled into equivalent circuits as shown in Figure 3-22. All parasiti cs in the single metal plate as shown in Figure 3-18 are calculated by EM simulator ASITIC, developed by Berkeley, and each value is shown in Table 3-3. Fig. 3-18. The block diagram of the embe dded loopback test model with parasitics

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66 Table 3-3. Calculated value of the eq uivalent circuit for embedded loopback 897 0.068 8.976 2.709 8 480.6m 10.98 96.49 66.03 7 34.03 1.263 64.8 39.34 6 1394 0.0518 127.7 3.481 5 901.9 0.0714 41.45 3.051 4 34.03 1.263 65.4 39.82 3 197.7 0.2749 24.9 11.08 2 910.2m 12.18 109.3 78.03 1 R1,2(k) C1,2(fF) Rx(m) L(pH) 897 0.068 8.976 2.709 8 480.6m 10.98 96.49 66.03 7 34.03 1.263 64.8 39.34 6 1394 0.0518 127.7 3.481 5 901.9 0.0714 41.45 3.051 4 34.03 1.263 65.4 39.82 3 197.7 0.2749 24.9 11.08 2 910.2m 12.18 109.3 78.03 1 R1,2(k) C1,2(fF) Rx(m) L(pH) As simulated earlier, the low noise amplifie r has approximately a 19 dB gain at 5.2 GHz. The initial RF switch has about a 2.0 dB insertion loss at 5.2 GHz. Due to this RF switch, the total power level gain is 17 dB above the input power. The 30 dB attenuator has 30 dB attenuation at 5 GHz so the power le vel lowers to -13 dB below input level at the attenuator output. This -13 dB signal pa sses through a second RF switch and another 2.0 dB loss occurs. Finally, th is signal is amplified by a bout by approximately 19 dB at the LNA so the output power level is a bout 4 dB loss as shown in Figure 3-19. Fig. 3-19. Simulated results of the loopback w ith parasitics circuit output power level at port 2

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67 3.5 Measured Results of Loopback Sub-circuits and Test System The 40 dB, 50 dB, and 60 dB RF attenuators were fabricated with the IBM 0.25 micron SiGe BiCMOS-6HP technology throug h the MOSIS fabrication service. The measurements of RF attenuators were performed by using an on-wafer Cascade Microtech Air Coplanar Probe (ACP) and a HP8510C Network Analyzer. The photomicrograph of the attenuators is shown in Figure 3-20. The total chip size is about 1.2 mm2 (1.2 mm x 1.0 mm). Fig. 3-20. Die micrograph (1.0mm x 1.2mm) of the RF attenuator and RF switch The measured results of the attenuators are shown in Figure 3-21. The transmitted power at port 2 in the 30 dB attenuator is -28. 6 dB, in the 40 dB attenuator is -39.7 dB, in 40 dB Attenuator 50 dB Attenuator 60 dB Attenuator RF switch

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68 the 50 dB attenuator is -49.2 dB, and in the 60 dB attenu ator is -57.5 dB at 100 MHz respectively and this agrees well with the simulated -30.1 dB, -40. 1 dB, -50.1 dB, and 60.1 dB responses. But at high frequency, the 50 dB and 60 dB attenuators are very ineffective and show poor ag reement with simulation indi cating significant substrate signal leakage that exceeds the 50 dB and 60 dB attenuator transmissions. As shown in Figure 3-21, the leakage power in creases at higher frequencies. Attenuator-70 -65 -60 -55 -50 -45 -40 -35 -30 12345678910 Frequency (GHz)( dB ) 40 dB ( Simulation ) 50 dB ( Simulation ) 60 dB ( Simulation ) 40 dB ( Measurement ) 50 dB ( Measurement ) 60 dB ( Measurement ) Fig. 3-21. Measured results of various pi-type attenuators As shown in Figure 3-21, RF attenuators ar e very ineffective at high frequency. The RF attenuator and silic on substrate can be modeled as shown in Figure 3-22. A coupling capacitor, Cc is modeled between sign al path and substrate. Coupling capacitors are distributed evenly through the dioxide laye r. And silicon substrate can be modeled as vertical components (Rsub1 and Csub1) and horizontal components (Rsub2 and Csub2). These

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69 vertical and horizontal compone nts are distributed evenly al so. A portion of the signal on the pads and attenuator is coupled through coupling capacitor Cc. This signal propagates to every direction. Some signals propagate to the bottom plate of a silicon substrate and others propagate to the side through the silicon subs trate. A portion of the signal launched at Pad1 propagates to Pad2 through the c oupling capacitor Cc, substrate resistor Rsub2, and substrate capacitor Csub2. If the leakage power through substrate exceeds the designed attenuation level, the attenuator becomes very ineffective at high frequency. SiO2 Si Cc Cc CcCc Csub1 Csub1 Rsub1 Rsub1 Rsub2 Csub2 Pad1 Pad2 Attenuator Sub-contact SiO2 Si Cc Cc CcCc Csub1 Csub1 Rsub1 Rsub1 Rsub2 Csub2 Pad1 Pad2 Attenuator Sub-contact Fig. 3-22. Model of the RF attenuator and substrate Two layouts are shown in Fi gure 3-23. Figure 3-23-a) s hows the layout of the RF attenuator without substrate contacts. This has -30 dB attenuation and its measurement results show in Figure 3-21. As mentioned ea rlier, there is some signal leakage through a substrate and this attenuator is very ineff ective at high frequency. To prevent the signal

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70 leakage through a substrate, many substrate cont acts are used as shown in Figure 3-23-b). The substrate contacts make a metal wall a nd block the signal leakage between two signal ports. (a) RF attenuator wit hout substrate contacts. Sub contactSub contact Sub contact Sub contactSub contact Sub contact (b) RF attenuator with substrate contacts. Fig. 3-23. Layout of the RF attenuato r with and without substrate contact The 30 dB RF attenuators w ithout substrate contacts an d the 30 dB RF attenuator with substrate contacts were fabricated with the IBM 0.18 micron SiGe BiCMOS-7WL technology through the MOSIS fa brication service. The meas urement of the 30 dB RF attenuator was performed by using an on-wa fer Cascade Microtech Air Coplanar Probe (ACP) and a HP8510C Network Analyzer. The photomicrograph of the attenuators is shown in Figure 3-24. The tota l chip size is about 1.7 mm2 (1.6 mm x 1.1 mm).

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71 Fig. 3-24. Die micrograph (1.6mm x 1.1mm) of the RF attenuator and RF switch 30 dB without sub-contact 30 dB with sub-contact 30 dB without sub-contact 30 dB with sub-contacts s 30 dB without sub-contact 30 dB with sub-contact 30 dB without sub-contact 30 dB with sub-contacts s Fig. 3-25. Measured results of the 30 dB attenuator The measured results of the attenuators are shown in Figure 3-25. The transmitted power at port 2 in the 30 dB attenuator with substrate contacts is -29.9 dB at 5 GHz. The attenuation is very constant and variation is within 0.3 dB up to 10 GHz. It is very effective and shows good agreement with the simulation when compared to the measurement result of 30 dB attenua tor without substrate contacts. Without subcontact With subcontact

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72 The RF switch was fabricated with the IBM 0.25 micron SiGe BiCMOS-6HP technology through the MOSIS fabrication servi ce. The measurement of the RF switch was performed by using an on-wafer Cascade Microtech Air Coplanar Probe (ACP) and a HP8510C Network Analyzer. The photomicrogra ph of the attenuators is shown in Figure 3-20. The total chip size is about 1.2 mm2 (1.2 mm X 1.0 mm). Switch-60 -50 -40 -30 -20 -10 0 12345678910 Frequency (GHz)( dB ) Simulaton (SW-on) Simulation (SW-off) Measurement (SW-on) Measurement (SW-off) Fig. 3-26. Measured re sults of the RF switch The measured results of the RF switch are shown in Figure 3-26. The transmitted power at port 2 is -2.4 dB at 5.2 GHz. Th e leakage power at port 3 is -16 dB. The simulated transmitted power at port 2 is -2.0 dB at 5.2 GHz and the simulated leakage power at port 3 is -32 dB. The measurements show good agreement with simulation. The leakage power at port 3 is higher than si mulation. The two MOSFETs and two resistors that were removed to save switch area result in this high leakage. The loopback test structure was fabric ated with the IBM 0.25 micron SiGe BiCMOS-6HP technology through the MOSIS fa brication service. The measurement of the loopback test structure was performed by using an on-wafer Cascade Microtech Air Coplanar Probe (ACP) and a HP8510C Netw ork Analyzer. The photomicrograph of the

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73 overall loopback test IC is shown in Figure 3-27. The total chip size is about 1.6 mm2 (1.85 mm x 0.87 mm). Fig. 3-27. Die micrograph (1.85mm x 0.87 mm) of the embedded loopback test model The measured results of the embedded l oopback test model are shown in Figure 328. The transmitted power at port 2 is 2 dB at 5 GHz. As mentioned before in Figure 319, the simulated transmitted power at port 2 is 4 dB at 5 GHz and the measurements show good agreement with simulation. Measurement Simulation Measurement Simulation Fig. 3-28. Measured results of the embedded loopback test model 3.6 Conclusions Attenuators, RF switches, Low Noise Amplif ier and loopback test circuits have been designed and characterized for embedde d testing of RF ICs. To realize high

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74 performance attenuation at high frequency, a method of reducing leakage through the substrate is investigated. Making a blocking wa ll using substrate contacts is shown to be a good method to reduce the substrate leakage. The measurement results of 30 dB RF attenuator with substrate co ntacts show better high frequency performance than the measurement results of an RF attenuator wi thout substrate contacts Using this method, RF attenuator is close to the design specification up to 10 GHz. Compared with a traditional RF switch, a ne w test RF switch is realized with half the area by reducing the design by two transi stors as shown in this chapter. The RF switch was designed for minimum insertion loss using the optimum gate dimension (the optimum gate width and the minimum gate length). The measurement results showed good agreement with simulation. For the experiments with the loopback test, the parasitics of metal lines for interconnection are modeled and considered in simulation to improve accuracy. There are closer agreements between the simulation a nd the measurement results when parasitics are considered. Through this research, th e loopback test method was proposed and verified for TDD (Time Division Dupl ex) communication methods up to 5 GHz. This is the first attempt for embedded loopback test of a wireless communication system. This proposed loopback was design ed with minimum area (0.02 mm2) and can extend the application frequency as high as the operating frequency of the on-chip RF attenuator and RF switch. The attenuation value for the l oopback signal can be decided according to each design application.

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75 CHAPTER 4 ANOTHER EMBEDDED LOOPBACK FOR RF ICS TEST 4.1 Introduction The loopback test, as proposed in an earlier chapter, is one of the least expensive test methods for verifying functionality in a communication circuit. However, this “go” or “no go” test gives little insight into circuit failure mechanisms and is of little assistance in debugging a circuit manufacturing proce ss. On-chip loopback techniques may prove attractive when doing bare die tests for ICs in system-in-a-package and when the chip package introduces parasitics that adversel y effect the off-chip short necessary for loopback test. This can occur with very hi gh frequency transceivers in the > 10 GHz range. SYNTH RX BLOCK RF S/W ANT HPA LNA BPF AMP AMP AGC AMP AMP BPFTX BLOCKMIXER MIXER ATT Coupler RF S/W Power Monitor Test Circuit for Embedded testing SYNTH RX BLOCK RF S/W ANT HPA LNA BPF AMP AMP AGC AMP AMP BPFTX BLOCKMIXER MIXER ATT Coupler RF S/W Power Monitor Test Circuit for Embedded testing Fig. 4-1. Block diagram of anot her embedded loopback RFIC test

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76 In a previous chapter, the loopback te st named Type 1 was proposed for High Power Amplifiers (HPA), that was built usi ng a different power amplifier technology (GaAs) that is separate from th e silicon IC transceiver block. In this chapter, a nother embedded loopback test name d Type 2 will be examined. As mentioned earlier, the Type 1 test is effective for separate d high power amplifier (HPA) designs using different materials fo r the HPA design. The biggest difference between Type 1 and Type 2 is that the later is for single chip design including the HPA in the same wafer. Designing the whole system function in a single ch ip is a new design trend. Figure 4-1 shows a WLAN block diagra m of the loopback Type 2 test in which transmitter signals test the receiver by conn ecting them to the receiver through RF switches with an attenuator in the signal path. The HPA connects to the antenna (ANT) through the RF switch (RF S/W). In this loopback test example, test signals are am plified via a high power amplifier (HPA) and most signals are delivered to the antenna i nput port though a direc tional coupler and RF switch. Further, some of the coupled signals are delivered to the loopback attenuator through a first RF switch and then an LNA via a second RF switch. The LNA requires a weak input signal created by the attenuator in the loopback signal path. Also, the HPA power can be monitored via a power detector The loopback signal path is shown in the shaded region of Figure 4-1. In summary, Fi gure 4-1 shows the necessary circuits for demonstrating the transceiver RF embedded loopback test signa l path: these consist of an HPA (high power amplifier), a directional coupl er, a RF switch, an attenuator, a second RF switch, peak detector, and a LNA.

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77 4.2 Design of Loopback Circuit Type 2 The embedded loopback circuit is modeled with an HPA (high power amplifier), a directional coupler, a RF switch, an attenuator, a second RF switch, peak detector, and a LNA as shown in Figure 4-2. HPA LNA ATT Coupler RF S/W 1 Power Detector Port 1 Port 2 Port 3 Port 4RF S/W 2 Port 5 HPA LNA ATT Coupler RF S/W 1 Power Detector Port 1 Port 2 Port 3 Port 4RF S/W 2 Port 5 Fig. 4-2. The block diagram of embedded loopback test model Type 2 The key test circuits for implementing em bedded loopback test Type 2 are highfrequency attenuators, which reduce the transm itted signal to sufficiently low test signal values, and RF switches, which are used to m odify the signal path between test operation and normal operation. The resistor-based atte nuator [Poz97][Viz95] was selected as the most suitable for embedded loopback RFIC te st because it has wideband circuit operation and compact implementation. The 30 dB atte nuator is designed according to the Table 41. The second key component for the embedded loopback RFIC test is the RF switch. Two n-MOSFET and two control re sistors are used for the RF switch as shown in Figure 4-6. For optimum size, the minimum gate le ngth 180 nM is used and the gate width is

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78 designed as 4.23 uM with 30 finge rs. To realize the loopback te st Type 2, two additional amplifiers, a directional coupl er and a power detector are needed. One is a low noise amplifier (LNA) and another is a high power am plifier (HPA) as show n in Figure 4-2. A cascode low noise amplifier is designed as a low noise amplifier. The schematic diagram is shown in Figure 4-3. The transistor size is designed for optimum gain and noise figure. For input matching, two spiral inductors are used: 1.08 nH and 220 pH as shown in Figure 4-3. Similarly, for output matching, tw o spiral inductors and three MIM capacitors are used as shown in Figure 4-3. Fig. 4-3. The schematic of cas code low noise amplifier (LNA) A 10-dB directional coupler [Yoo04] is de signed for 5 GHz operation as shown in Figure 4-4. This 10-dB directional couple r employs six spiral inductors and five capacitors. Each design value equa tion is derived in chapter 3.

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79 Port 1Port 3 Port 2 Port 4 445 fF 1.08 nH 4.71 nH 445 fF 445 fF 445 fF 420 fF 1.08 nH 1.08 nH 1.08 nH 4.71 nH Port 1Port 3 Port 2 Port 4 445 fF 1.08 nH 4.71 nH 445 fF 445 fF 445 fF 420 fF 1.08 nH 1.08 nH 1.08 nH 4.71 nH Fig. 4-4. The schematic of 10 dB directional coupler 4.3 Simulation of Loopback Sub-circuits and System Type 2 Cadence SpectreS was used to design 5 GHz 30 dB lumped passive -type attenuators. As shown in Figur e 4-5, at 5 GHz the simulation results for the magnitude at port 2 for the 30 dB attenuator is approximately -30.1 dB. This simulation includes parasitic parameters (capacitances) of the P+ Polysilicon resister s which degrade high frequency response. Finally, the dimension of the n-MOSFET RF switch is decided for optimum value according to various simulation results. As me ntioned earlier, the minimum gate length is better for insertion loss and in creasing the gate width is not always good. The simulated optimum insertion loss of this n-channel MOSF ET is 0.6 dB when the number of fingers is 30, the gate length is 180 nM, and the layout gate width is 4230 nM as shown in Figure 4-5.

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80 -0.6 dB -0.6 dB Fig. 4-5. Simulated results of the RF switch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2728 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 7 13 16 17 18 19 1316 17 18 19 13 16 17 18 19 13 16 17 18 19 13 16 17 18 19 16 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2728 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 7 13 16 17 18 19 1316 17 18 19 13 16 17 18 19 13 16 17 18 19 13 16 17 18 19 16 18 Fig. 4-6. The schematic of cascode low noi se amplifier with parasitics for Type 2

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81 The schematic of this cascode low noise amplifier with parasitics is shown in Figure 4-6. Every single metal line for connect ion between transistor s is modeled as an equivalent circuit as shown in Figure 3-22. All parasitics in the single metal line, as shown in Figure 4-6, are cal culated by the EM simulator ASITIC [Nik00] which was developed by Berkeley and each value is shown in Table 4-1. Table 4-1. Calculated value of the eq uivalent circuit for LNA of Type 2 748.7 32.5 28 15.26 231.4 12.08 2.91 27 33.41 867 126.7 50.07 26 0.565 1,223 74.3 28.42 25 538.8 86.2 29.67 8.30 24 32.9 432 23 36.7 416 22 1302 50.2 90.1 3.76 21 1327 51.8 52.25 2.80 20 1354 50.1 112.5 4.99 19 3705 18.5 71.39 2.20 18 1357 49.9 112.2 4.83 17 8422 8.1 73.44 1.35 16 0.842 13,540 15 1.153 10,590 14 2229 28.1 267 4.05 13 916 74.1 116.9 5.32 12 44.7 417 11 919.9 74.8 74.33 4.80 10 2066 32.8 152 4.32 9 2055 33.6 90.31 4.14 8 2169 30.8 71.12 2.20 7 132.5 220.5 61741 39.1 98.8 4.02 5 8422 8.1 71.46 1.334 4 536.6 83.8 48.29 11.49 3 510 117.9 23.03 11.23 2 512.5 102.2 15.59 5.564 1 R1,2(k) C1,2(aF) Rx(m) L(pH) 748.7 32.5 28 15.26 231.4 12.08 2.91 27 33.41 867 126.7 50.07 26 0.565 1,223 74.3 28.42 25 538.8 86.2 29.67 8.30 24 32.9 432 23 36.7 416 22 1302 50.2 90.1 3.76 21 1327 51.8 52.25 2.80 20 1354 50.1 112.5 4.99 19 3705 18.5 71.39 2.20 18 1357 49.9 112.2 4.83 17 8422 8.1 73.44 1.35 16 0.842 13,540 15 1.153 10,590 14 2229 28.1 267 4.05 13 916 74.1 116.9 5.32 12 44.7 417 11 919.9 74.8 74.33 4.80 10 2066 32.8 152 4.32 9 2055 33.6 90.31 4.14 8 2169 30.8 71.12 2.20 7 132.5 220.5 61741 39.1 98.8 4.02 5 8422 8.1 71.46 1.334 4 536.6 83.8 48.29 11.49 3 510 117.9 23.03 11.23 2 512.5 102.2 15.59 5.564 1 R1,2(k) C1,2(aF) Rx(m) L(pH)

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82 Finally, the simulation result of the low noise amplifier with parasitics is shown in Figure 4-7. The simulated gain (S21) is 16.3 dB at 5.0 GHz a nd reflection at input and output ports are lower than -10 dB at 5.0 GHz. S21(dB) S22(dB) S11(dB) S21(dB) S22(dB) S11(dB) Fig. 4-7. S-parameter simulation result of the low noise amplifier with parasitics for Type 2 5 8 11 14 17 20 -30-25-20-15-10-505 Pin (dBm)Gain (dB) Fig. 4-8. Gain simulation result of the low noise amplifier with parasitics for Type 2

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83 The schematic of the lumped passive directi onal coupler with para sitics is shown in Figure 4-9. Every single metal line for conn ection between lumped passive components is modeled into equivalent circuits as show n in Figure 3-22. All parasitics in the single metal line, as shown in Figure 4-9, are ca lculated by EM simulator ASITIC which was developed by Berkeley and each value is shown in Table 4-2. Fig. 4-9. The schematic of lumped passive di rectional coupler with parasitics for Type 2 Table 4-2. Calculated value of the equivalent circuit for directiona l coupler of Type 2 0.032 22.64 141.7 99.64 5 0.032 22.64 143.7 101.4 4 0.683 1.43 11.02 4.94 3 476 2.35 110.6 38.9 2 492.3 0.12 29.62 6.59 1 R1,2(k) C1,2(fF) Rx(m) L(pH) 0.032 22.64 141.7 99.64 5 0.032 22.64 143.7 101.4 4 0.683 1.43 11.02 4.94 3 476 2.35 110.6 38.9 2 492.3 0.12 29.62 6.59 1 R1,2(k) C1,2(fF) Rx(m) L(pH)

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84 Finally, the simulation results for the lump ed passive directional coupler is shown in Figure 4-10. The simulated coupling (S21) is -10.37 dB at 5.0 GHz and simulated through (S31) is -1.47 dB at 5.0 GHz. The simulated reflection ratios (S11,S22, and S33) of each port are lower than -20 dB at 5 GHz. Fig. 4-10. S-parameter simulation result of the directional coupler with parasitics for Type 2 As shown in Figure 4-2, the embedded l oopback circuit is m odeled with an HPA (high power amplifier), a directional coupler a RF switch, an a ttenuator, a second RF switch, a peak detector, and a LNA. Similarl y, every single metal line for connection is modeled into equivalent circuits as shown in Figure 3-22. All parasitics in single metal plates as shown in Figure 4-11 are calcu lated by EM simulator ASITIC which was developed by Berkeley and each value is shown in Table 4-3.

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85 Fig. 4-11. The block diagram of embedded loopb ack test model Type 2 with parasitics Table 4-3. Calculated value of the equivale nt circuit for the embedded loopback Type 2 43.56 0.88 37.96 22.65 V2-3 74.09 4.31 70.42 51.24 V2-2 1.052 25.23 203.8 199.9 V2-1 R1,2(k) C1,2(fF) Rx(m) L(pH) 43.56 0.88 37.96 22.65 V2-3 74.09 4.31 70.42 51.24 V2-2 1.052 25.23 203.8 199.9 V2-1 R1,2(k) C1,2(fF) Rx(m) L(pH) As simulated before, the low noise amplifie r has approximately 16.3 dB gain at 5.2 GHz. The through port of the directional coupler has about a 1.5 dB insertion loss at 5.2 GHz. Due to this directional c oupler, total power le vel gain at port 2 is 14.7 dB above the input power as shown in Figure 4-12-dB(S(21)). The coupling port of the directional coupler has about a 10.4 dB insertion loss at 5.2 GHz. The RF switch has about a 1.0 dB insertion loss at 5.2 GHz. The 30 dB atte nuator has a 30 dB attenuation at 5.2 GHz.

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86 Finally, simulation results of total loop back test Type 2 are shown in Figure 4-12. Total power level gain at port 3 is -15.2 dB below the input power as shown in Figure 4-12dB(S(31)). The reflection ratio of eac h port (port 1, port 2, and port 3) is lower than -10 dB at 5.2 GHz as shown in Figure 4-12. Fig. 4-12. Simulated results of th e loopback Type 2 with parasitics 4.4 Measured Results of Loo pback Test Type 2 System The loopback test Type 2 st ructure was fabricated with the IBM 0.18 micron SiGe BiCMOS-7WL technology through the MOSIS fa brication service. The measurement of the loopback test Type 2 was performed by using an on-wafer Cascade Microtech Air Coplanar Probe (ACP) and a HP8510C Netw ork Analyzer. The photomicrograph of the overall loopback test Type 2 IC is shown in Figure 4-13. Th e total chip size is about 1.9 mm2 (1.6 mm X 1.2 mm).

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87 Fig. 4-13. Die micrograph (1.6mm x 1.2mm) of the embedded loopback test model The measured results of the embedded l oopback test model are shown in Figure 414. The loopback power level gain at LNA i nput is -15 dB at 5.2 GHz. As mentioned before in Figure 4-12, the simulated loopback power level gain at LNA input is -15.2 dB at 5.2 GHz and shows good agreement with measurement. The transmitted power at port 2 is 12 dB at 5.2 GHz. As mentioned before in Figure 4-12, the simulated transmitted power at port 2 is 14.7 dB at 5.2 GHz a nd shows good agreement with measurement. Simulation-dB(S(2,1)) Simulation-dB(S(3,1)) X Measurement -dB(S(3,1)) Measurement -dB(S(2,1)) Simulation-dB(S(2,1)) Simulation-dB(S(3,1)) X Measurement -dB(S(3,1)) Measurement -dB(S(2,1)) Fig. 4-14. Measured results of the embedded loopback test Type 2 model

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88 4.5 Conclusions Attenuators, RF switches, dire ctional couplers, peak dete ctor, low noise amplifiers and loopback test Type 2 circuits have b een designed and characterized for embedded test of RF ICs. The loopback test Type 2 includes a directional coupler and a peak detector. Therefore, the Type 2 loopback test is effective for a single chip design including the HPA in the same IC. To the author’s best knowledge this is the first attempt for embedded loopback test of wire less communication system. As mentioned in a previous chapter, the parasitics of me tal lines for interconnection are modeled and considered for simulation. The measured resu lts of the loopback power level gain at LNA input are -15 dB at 5.2 GHz. As mentioned befo re in Figure 4-12, th e simulated loopback power level gain at LNA input is -15.2 dB at 5.2 GHz. There is closer agreement between the simulation and the measurement results wi th the metal line parasitics included than without parasitic consideration. The at tenuation value and coupling value of the directional coupler can be d ecided according to each tran sceiver test application.

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89 CHAPTER 5 EMBEDDED S-PARAMETER MEASUREMENT MODULE 5.1 Introduction Modern integrated systems include dense ICs containing diverse circuits such as microprocessors, memory, digital processing blocks, analog functi onal blocks, and RF functional blocks. As systems-on-a-chip (SoCs) become more advanced and complex, it is necessary to reduce manufacturing costs, es pecially testing costs. There are many types of test, including bench test for circuit verification and manuf acturing test for individual part verification. Manufacturing te st must be done efficiently to keep part cost low. The test goal is to remove bad parts. Test equi pment specifications can often be relaxed as compared to bench characterization equipment. To verify the performance of SoCs, mixed-signal and RF testing may be used. Among these test methods, RF test is a major pa rt of the entire test cost. RF measurement specifications often require the comparison of the amplitude and the phase difference between an unknown signal and a reference sign al. The magnitude and phase verification of an RF channel determines whet her a part can be sold or not. The s-parameters are considered a good me thod for the bench characterization of RF and microwave components because they pr ovide vector data fr om a controlled and easily achievable 50 impedance system. To perform this measurement, a direct and accurate measurement is needed and a de-emb edding procedure is adopted to remove the testing fixture characteristics from the overall measurement.

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90 As previously mentioned, testing and ve rification are a major part of the total production IC testing cost for RF and microwav e components. This is so because costly RF and microwave test equipment (vector netw ork analyzers or equivalent) are required. Other testing costs include the long time require d to set up and calibrate test equipment. Only the most expensive automated test eq uipment (ATE) has s-parameter capability and it is too costly to use for low cost consumer parts. Over the years, various methods have b een considered to reduce testing costs [Koo91][Pla95]. One of these methods is onchip measurement [C ow01]. Embedded test methods can mathematically subtract the eff ects of parasitics caused by the contact pads, the interconnections between the pads, RF probes and RF cables for connection to test equipment. At RF microwave frequencies, unmodeled parasitics cau se significant errors in parametric data. A complex calibration proc edure is needed to subtract the unwanted parasitic effects. Also, costly testing equipm ent is needed to measure RF performance. For this reason, an embedded test method for RF SoCs is potentially a very economical method for maintaining a high level test accuracy. The use of on-chip s-parameter techniques for IC production te st is limited by area and cost considerations. However, the design of single chip s-parameter test modules allows for extremely low cost s-parameter test probes and also low cost multi-channel RF test boards in automated test. Future applications of radio imagining array circui ts for automobiles at 77 GHz may require onchip sensor verification. In these systems, having an on-chip s-parameter measurement capability nearby may prove invaluable in circuit performance verification and calibration. In addition, on-chip s-parameter test ICs can be used on the load board of an ATE system.

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91 Table 5-1 is the summary of specifications of a traditional and the proposed on-chip network analyzer. As we know, network analyzer s that have been sold in the commercial market have a very high phase accuracy and high magnitude accuracy. For example, the Agilent PNA network analyzer E8363B m easurement accuracy is within 0.1 dB magnitude and 1 phase. To get this sensitivit y, the traditional network analyzer needs a large enclosure to add very accurate RF/microwave test blocks, thereby adding cost of the analyzer. Table 5-1. Specification of the commercial network analyzer and on-chip s-parameter module 2 or more 2 or 4 Number of test ports 4 1 Measurement uncertainty (Phase) 0.5 dB 0.1 dB Measurement uncertainty (Magnitude) On-chip sparameter module Traditional Network Analyzer (E8363B) 2 or more 2 or 4 Number of test ports 4 1 Measurement uncertainty (Phase) 0.5 dB 0.1 dB Measurement uncertainty (Magnitude) On-chip sparameter module Traditional Network Analyzer (E8363B) The on-chip s-parameter measurement met hod occupies a small area and measures s-parameters directly (without any probing) That is why the on-chip method provides major advantages in cost and time when the chip is embedded in probes and placed on multi-channel RF test boards. Again, there are cost trade offs in integrating these systems on every SoC. But sharing an on-wafer s-parame ter test system in the wafer scribe lanes may probe advantageous for production IC test There are huge difficulties in achieving the same performance on-chip as a commerc ial big network analyzer. Our measurement accuracy is within 0.5 dB with magnitude and 4 phase. Even though there is performance degradation for onchip s-parameter realizations, test time may be reduced

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92 which saves significant manufactured IC part cost. The goal is to make the test accurate enough for verification test of production ICs. 5.2 Introduction of Scattering Parameters For RF microwave measurements, using sparameters is adva ntageous over other parameters including y, z, and h-parameters. S-parameters are defined in terms of voltage traveling waves, which are relatively easy to measure in a microwave system while y, z, and h-parameters require ope n and short circuits which are often not feasible. i(x,t) v(x,t) + x x i(x,t) v(x,t) + x x (a) Transmission line for an incremental length i(x,t) v(x,t) + x R x L x G xC x i(x+ x,t) + v(x+ x,t) i(x,t) v(x,t) + x R x L x G xC x i(x+ x,t) + v(x+ x,t) (b) Lumped-element equivalent circuit Fig. 5-1. Transmission line and equivalent circuit

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93 Another strong advantage is that each parameter has a very similar meaning compared to other parameters; for example S11 is a reflection ratio at port 1. S22 is also a reflection ratio at port 2. S21 and S12 show gain or loss between two ports. The greatest advantage of using s-parameter for RF microwave measurement is that multiple devices can be cascaded and an overall system performance easily estimated. In addition, case of calibration and high accuracy are the main reas on why the s-parameters are so popular for RF and microwave measurement. For more accurate s-parameter descripti on, transmission line theory is adopted instead of circuit th eory [Poz97][Gon97]. As shown in Figure 5-1, a transmission lin e can be modeled with a lumped-element equivalent circuit. Voltage and current wa ves travel through a tr ansmission line so the magnitude and phase of voltage and current can vary according to their length. The voltage and current is given by V(z) = V+ e-j x + Vej x (5.1) I(z) = I+ e-j x Iej x (5.2) When x=0, at the n th port, the total voltage and current become Vn = Vn + + Vn (5.3) In = In + In (5.4) The scattering matrix is a ratio of the inci dent voltage wave to those reflected. In the n-port network, Vn+ is the amplitude of the incident voltage wave at port n, and Vnis the amplitude of the reflected voltage wave at port n. As previously stated, the sparameter is defined as a ratio of these inci dent and reflected voltage waves. So the sparameter can be defined as equation (5.5) and (5.6)

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94 n n nv v v S S S v v v . S . S . S . S S . S .2 1 nn n2 1 2n 22 21 1n 12 11 2 1 (5.5) j k for 0 j iV V kV ijS (5.6) Assume that the network has an n-port where Zon is the characteristic impedance of the nth port, and Vn+ and Vnare defined as incident and re flected voltage wave at port n respectively. A new set of wave equations is defined to explain a physically meaningful power relation in terms of wave amplitudes as shown in Figure (6-7) (6-8). I z v z 2 1 I z v n 0n n 0n 0n 0 n n nz a (5.7) n 0n n 0n 0n 0 nI z v z 2 1 I z v n nz b (5.8) So, equation (5.7) (5.8) become a z V V n 0n n n n nb V (5.9) a z 1 V V z 1 n 0n n n 0 n nb I (5.10) Rewrite equation (5.5) with equation (5.7)(5.8), a s b (5.11) where the i,j th element of the scattering matrix is given by j k for 0 j ia b ka ijS (5.12)

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95 This concept is described in Figure 5-2. In this figure, each traveling wave at the port has a direction where an represents an incident wa ve at the nth port, and bn represents a reflected wave from that port. When a power wave is launched at port 1, a portion of the wave energy will be reflected and the rest of the energy will be transmitted. The same is true with measuring energy at port 1. Wh en a power wave is launched at port 2, some of the wave energy will be transmitted to the port 1 and there rest of the wave energy will be reflected at port 2. Incident Transmitted Reflected Reflected Transmitted Incident DUT Port 1 Port 2 a1b1a2b2S21S12S22S11Incident Transmitted Reflected Reflected Transmitted Incident DUT Port 1 Port 2 a1b1a2b2S21S12S22S11 Fig. 5-2. Function diagram of s-parameter The s-parameter then becomes 1 port at power wave incident 1 port at power wave reflected 0 1 1 112 aa b S (5.13) 1 port at power wave incident 2 port at power wave d transmitte 0 1 2 212 aa b S (5.14) 2 port at power wave incident 1 port at power wave d transmitte 0 2 1 121 aa b S (5.15)

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96 2 port at power wave incident 2 port at power wave reflected 0 2 2 221 aa b S (5.16) 5.3 Introduction of Mixed Mode Scattering Parameter Differential circuits have performed critic al roles in an RF and microwave circuit design as well as in analog ci rcuit design. Mixed mode scat tering parameters have been investigated for mixed mode circuit analys is [Bok95]. The basic concept of mixed mode signals in a two-port networ k is shown in Figure 5-3. DUT V1 V2Port 1 Port 2 DUT V1 V2Port 1 Port 2 Fig. 5-3. Signal diagram of mixed mode two-port network As shown in Figure 5-3, the differential-m ode signal definition is that two voltage and current waves flow through the pair lines with different phases. So the voltage and current flow has a magnitude ( V1 0, V2 0). According to this definition, it is very difficult for the signal to be referenced to a ground potential. It is better that each two signals on both pairs of lines are referenced to each other. On the other hand, the common-mode signal definition is that two voltage and current waves flow through the pair of lines with the same magnitude and phase. So the voltage and current waves on bot h line pairs are equal in phase and in magnitude with respect to ground, so a differential voltage and current has no magnitude. ( V1= 0, V2= 0)

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97 For the mixed mode s-parameter, the diffe rential mode voltage and current and the common mode voltage and current should be de fined. The differential mode voltage is 2 1v v x vdm (5.17) The differential mode cu rrent can be defined 2 12 1i i x idm (5.18) The common mode voltage and current also can be defined same way 2 12 1v v x vcm (5.19) 2 1i i x icm (5.20) The characteristic impedance of the differe ntial and common mode at some point x also can be described 2 2o o pos o pos o pos dm pos dm dmZ Z x v x v x i x v Z (5.21) 2 2e e pos e pos e pos cm pos cm cmZ Z x v x v x i x v Z (5.22) The new mixed mode wave equation at port1 can be derived using the new definition of mixed mode voltage, current, an d characteristic impedance. (Assume the port 1 is located at x=o) 0 1 2 1 x dm dm dm dm dmR x i x v R a (5.23) 0 1 2 1 x dm dm dm dm dmR x i x v R b (5.24)

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98 0 1 2 1 x cm cm cm cm cmR x i x v R (5.25) 0 1 2 1 x cm cm cm cm cmR x i x v R b (5.26) The conceptual diagram of the mixed-m ode two-port is shown in Figure 5-4. Differential-mode ports Common-mode ports Physical port 1 Physical port 2 adm1bdm1acm1bcm1bdm2adm2bcm2acm2Mixed-mode 2-ports Differential-mode ports Common-mode ports Physical port 1 Physical port 2 adm1bdm1acm1bcm1bdm2adm2bcm2acm2Mixed-mode 2-ports Fig. 5-4. Conceptual diagram of mixed-mode two-port Rewrite (5.11) using equation (5. 23), (5.24), (5.25), and (5.26) 2 14 1 13 2 12 1 11 1 cm cm dm dm dma s a s a s a s b (5.27) 2 24 1 23 2 22 1 21 2 cm cm dm dm dma s a s a s a s b (5.28) 2 34 1 33 2 32 1 31 1 cm cm dm dm cma s a s a s a s b (5.29) 2 44 1 43 2 42 1 41 2 cm cm dm dm cma s a s a s a s b (5.30) 2 1 2 1 2 1 2 1 cm cm dm dm cc cd dc dd cm cm dm dma a a a s s s s b b b b (5.31)

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99 Where [Sdd] is the differential mode s-parameter, [Scc] is the common mode sparameter, and [Scd][Sdc] are the mode conversion or cross mode s-parameters. 5.4 Design for On-Chip Scattering Parameter Measurement A traditional block diagram for s-parameter measurements is shown in Figure 5-5. When a power wave is launched at port 1, most of the incident wave energy will be delivered to the DUT (Device-Under-Test) through the transmit port of the directional coupler 1. A small amount of the launched wave will be delivered to the receiver 2 through the coupling port of direct ional coupler 1. When incide nt power wave is traveling from the direction coupler 1 to the DUT, some energy is transmitted to the DUT and the rest is reflected. These reflected power waves from the DUT will travel through the directional coupler 1 again a nd be transferred to the rece iver 1. Power wave energy arriving at the DUT will be delivered to port 2 through the directional coupler 2. Minimal wave energy will be coupled through the coupling port of the directional coupler 2. That wave energy will be delivered to receiver 4. In addition, when the power wave energy is launched at port 2, some transmitted energy will be delivered to the receiver 1 and the rest of the reflected energy wave will be sampled at the receiver 4. Up to now, the discussion has focused on how power waves are delivered to the receiver. The receiver of a traditional radi o system is composed of an adjustable attenuator, mixer, LO (Loc al Oscillator), BPF (Ba nd Pass Filter), and ADC/DSP (Analog-to-Digital Converter / Di gital Signal Processor), as show n in Figure 5-6. It also includes RF switch blocks, such as an RF switch and a 50 terminator that share the local oscillator but these RF switch blocks ar e not examined in this phase. At first, traveling waves, which arrive at the receiver, have suitable levels of strength through the RF attenuator. These waves convert to base-band signals through the mixer.

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100 DUT Directional Coupler 1 Directional Coupler 2 RECEIVER1Port 1 Port 2a1b1a2b2 RECEIVER2 RECEIVER3 RECEIVER4 DUT Directional Coupler 1 Directional Coupler 2 RECEIVER1Port 1 Port 2a1b1a2b2 RECEIVER2 RECEIVER3 RECEIVER4 Fig. 5-5. Traditional block diagram for s-parameter measurement The local oscillator is set to the desi red frequency used for down-conversion of traveling waves at the mixer. The down-conve rted energy to be an alyzed as the signal arrives at the ADC/DPS through the BPF, and the other energy not useful for test is eliminated by the BPF. Finally, these desired waves will change to digital signals and analyzed by DSP. The DSP design is out of scope of this dissertation. Adjustable Attenuator ADC/DSP Mixer BPF LO From Coupler Adjustable Attenuator ADC/DSP Mixer BPF LO From Coupler Fig. 5-6. Receiver block diagram of traditional s-parameter measurement As shown in Figure 5-5 and Figure 5-6, a traditional s-parameter measurement method used a DSP at base-band that can support accurate characterization. A serious

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101 disadvantage is that the LO should have high de gree of phase noise and be stability. This requires a large, accurate and energy expensive LO. In this work, an embedded s-paramete r measurement method is proposed. As depicted in Figure 5-7, a directional coupler is located between each port and the DUT. The directional coupler passes some wave energy in a forw ard direction and some wave energy is coupled to a forward coupling port. If the power wave travels in the reverse direction, some wave energy is delivered in the reverse direction and wave energy is coupled to the reverse coupling port. The magn itude and phase of each delivered waves is measured directly at RF microwave frequenc ies. By doing this, the highly accurate LO can be removed from the block diagram of Fi gure 5-6. Additionally, the parasitic effects caused by both the probe pads and lines connecting the pa d and the DUT can also be ignored. Phase Detector 1 DUT Directional Coupler 1 SW(DPDT) 1 Peak Detector 1 Divider 1 50 Directional Coupler 2 Phase Detector 2 SW(DPDT) 2 Peak Detector 2 Divider 2 50 Port 1 Port 2 Phase Detector 1 DUT Directional Coupler 1 SW(DPDT) 1 Peak Detector 1 Divider 1 50 Directional Coupler 2 Phase Detector 2 SW(DPDT) 2 Peak Detector 2 Divider 2 50 Port 1 Port 2 Fig. 5-7. Conceptual block diagram for on-chip s-parameter measurement Network analyzers sold in the commercia l market have a very high degree of accuracy and dynamic range. For example, thei r dynamic range is over 120 dB and their

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102 measurement accuracy is within 0.1 dB or 1. To get this sensitivity, the network analyzer needs a large enclosure and complex circuitry to realize ex tremely accurate and high dynamic range functional blocks, thereb y greatly increasing the price of the analyzer. Calculation plays a vital role in measurement accuracy since microwave fixtures, connectors, cables, probes, and transmission lines can severely degrade the DUT measurement data. The proposed embedded sparameter measurement method occupies minimal chip space and directly measures s-pa rameters without probing. That is why the proposed method provides major advantages in cost and time when compared to the traditional method. Granted, it is difficult to achieve the same performance as big, commercial network analyzers. However, with minimal performance degradation, expensive test equipment can be eliminated and test time can be reduced. This is also useful for the verification test of production ICs. Port 1Port 3 Port 2 Port 4 Ce Ce CeCe LeLe Le Le 2Lo Co 2Lo Port 1Port 3 Port 2 Port 4 Ce Ce CeCe LeLe Le Le 2Lo Co 2Lo Fig. 5-8. The schematic of 10 dB directional coupler for 10 GHz As shown in Figure 5-5, the traditional ne twork analyzer has f our receiver blocks. Two of them analyze an incident power wave at each port and the other two analyze the reflected power wave at each port. But in this proposed embedded s-parameter measurement method, two receiver blocks can be reduced as shown in Figure 5-7. The

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103 key sub circuits for implementing embedded s-parameter measurement are directional couplers, double pole do uble throw (DPDT) switches, RF po wer dividers, peak detectors, and phase detectors as shown in Figure 5-7. A 10-dB directional coupler [Yoo04] is de signed for 10 GHz as shown in Figure 58. For the 10-dB directional coupler, six spir al inductors and five capacitors are used. Each equation used to decide the de sign value is derived in chapter 3. Input 1 M1M2 R1R2 Control Input 2 M4M3 R4R3 Output 1 Output 2 R5 _______ Control DC Bias 2 DC Bias 1 R6 Input 1 M1M2 R1R2 Control Input 2 M4M3 R4R3 Output 1 Output 2 R5 _______ Control DC Bias 2 DC Bias 1 R6 Fig. 5-9. The schematic of DPST switch for 10 GHz The DPDT (Double Pole Double Throw) sw itch is designed for 10 GHz as shown in Figure 5-9. For the DPDT switch, four nMOS transistors and seve n poly resistors are used. Each equation used to decide the design value is derived in ch apter 4. As mentioned earlier, the directional c oupler is bi-directional. First, th e forward direction is defined so

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104 that the signal is launched at port 1 as shown in Fig 6-8, the main signal is delivered to port 3 (forward through port). Second, the design ed coupling signal is delivered to port 2 (forward coupling port). Third, no power will be delivered to port 4 (forward isolation port). One the other hand, the reverse direction is defined such that the signal is launched at port 3 and then the main si gnal is delivered to the port 1 (reverse through port). Next, the sampled coupling signal is delivered to th e port 4 (reverse coupling port). Ideally, no signal will be delivered to the port 2 (reverse isolation port). The port 2 (forward coupling and reverse isolation) and port 4 (forward isolation an d reverse coupling) of the directional coupler as shown in Figure 5-8 are connected at input 1 and i nput 2 of DPDT (Double Pole Double Throw) switc hes respectively. Therefore, when a signal is launched with forward direction, the coupled signal is delivered to the input 1 of DPDT switch through the port 2 (forward coupling). The sign al is then forwarded to the output 1 of DPDT switch for s-parameter measurement. In this case, the control signal is high. Simultaneously, the other port, port 4 (forward isolation), is connected to the input 2 of DPDT switch and this port is terminated with 50 resistor through the output 2 of DPDT switch. On the other hand, during the reverse directional case, the signal is launched at the port 3 with reverse direction. The coupled signal is delivered to the input 2 of DPDT switch through the port 4 (reverse coupling). Th is signal is delivered to the output 1 of DPDT switch for s-parameter measurement. Here, the control signal is low. Simultaneously, the other port, port 2 (reverse is olation), is connected to the input 2 of DPDT switch and this port is terminated with 50 resistor also. By doing this, the 4 receiver blocks of traditiona l network analyzers can be reduc ed to 2 receiver blocks. That is a significant advantage of th is proposed s-parameter method.

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105 Two types of phase detector circuits are employed [Ega81][Mey01][Raz01]: an S-R flip-flop and a Gilbert cell. The phase detect or compares the phase difference between the reference input and the signal i nput. A flip-flop is used for phase detection as shown in Fig 6-10. The rising edge of A makes Q high and the rising edge of B makes Q low as shown in Fig 6-10-b). Therefore the average of the Vout is propor tional to the phase difference between A and B. The Vout has a ch aracteristic saw-tooth shape as shown in Fig 6-10-c). The output crosses zero at 180 degree out of phase between A and B and measured range is 180 degree around center. R SQ Q A B Vout R SQ Q A B Vout (a) A B Vout t A B Vout t (b) 02 4 Vout/ average 02 4 Vout/ average (c) Fig. 5-10. Flip-flop phase detector as a phase det ector (type I)

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106 VCCRCRCRBRBREVEEQ1Q2Q3Q4Q5Q6Out2 Out1 In 1 In 2 Rbi1Rbi2 Rb1Rb2 CB CB VCCRCRCRBRBREVEEQ1Q2Q3Q4Q5Q6Out2 Out1 In 1 In 2 Rbi1Rbi2 Rb1Rb2 CB CB Fig. 5-11. The schematic of phase detector type I The S-R flip flop is designed for single re ference input and single signal input as shown in Fig 6-11. A B Vout A B Vout (a) A B Vout t A B Vout t (b) 02 4 Vout/ average 02 4 Vout/ average (c) Fig. 5-12. Exclusive-OR gate as a phase detector (type II)

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107 An exclusive OR gate [Wes93] is used fo r phase detection as shown in Fig 6-12. As shown in Figure 5-12-b), the two square -wave inputs A and B make Vout. Therefore, the average of the Vout is proportional to the phase diffe rence between A and B. The variable Vout has a characteris tic triangular shape as shown in Figure 5-12-c). The output crosses zero at 90 degree out of phase between A and B and measured range is 90 degree around center. The Gilbert Cell phase detector is designed for differential signal input as shown in Figure 5-13. Vo IEE-VEE Vin1 Vin2 VCCRCRCQ1Q2Q3Q4Q5Q6 Vo IEE-VEE Vin1 Vin2 VCCRCRCQ1Q2Q3Q4Q5Q6 Fig. 5-13. The schematic of phase detector type II As shown in Figure 5-20, the phase detect or output is depende nt on input signal strength. When the signal at the input is larg er, the voltage output is also larger until the

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108 detector is saturated. The signal strength at i nput of this phase detector will change by an unknown value when the signal passes through th e DUT. That is a criti cal weak point of the phase detector. It is necessary to keep the phase detector input signals at the same voltage because phase detector output changes correspond to the input amplitude. For this reason, a limiting amplifier is employed in the circuits. A limiting amplifier takes a switching input signal of unknown small amplit ude and amplifiers it to the saturation level of the limiting amplifier. This output signa l is at the same level for all input signals switching. The HBT Cherry-H ooper amplifier [Chr04][Raz03] is employed as a wideband limiting amplifier as shown in Figure 5-14. The optimum bias [Wol94] is selected for linear operation. To bypass the current of IC11 from R1 and R2, transistor Q7 and Q8 are added in each parallel feedback stage. VCC Out1 R1 RfQ1 RfQ2 Out2 In1 In2 Q3Q4Q7Q8Q5Q6Q9Q10Q11Q12Q13Q14VEER1R2R2Bias1 Bias2 Rb Rb VCC Out1 R1 RfQ1 RfQ2 Out2 In1 In2 Q3Q4Q7Q8Q5Q6Q9Q10Q11Q12Q13Q14VEER1R2R2Bias1 Bias2 Rb Rb Fig. 5-14. The schematic of Cherry-Hooper amplifier The strong impedance mismatch and emitter-follow feedback help extend the bandwidth [Rei96][Chr04] as shown in Figure 5-15.

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109 low high very high very low low very high very low high RERFRLRERE EFs TAS TIS EFs TAS low high very high very low low very high very low high RERFRLRERE EFs TAS TIS EFs TAS Fig. 5-15. The concept of strong impedance mismatch As shown in Figure 5-7, peak detectors are used to detect the signal amplitude. Besides the large-signal-detection theory [Mey95][Mil96], the small-signal-detection theory is proposed for the large-dynamic -range signal detection [Zha04]. The Meyer power detector has limits in extending its dynamic-range. To increase the dynamic-range, the voltage-divider enhanced RF power detector was designed for peak detection as shown in Fig 6-16. The peak detector ci rcuit has a relatively high dynamic range compared to the phase detector. ACINVo1 Vo2 Vdd Q1 R1 Q2 R2 PD bias VdcC1 C2 C3 C4 Q3Q4 ACINVo1 Vo2 Vdd Q1 R1 Q2 R2 PD bias VdcC1 C2 C3 C4 Q3Q4 Fig. 5-16. The schematic of voltage-divider enhanced RF power detector

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110 5.5 Simulation for On-Chip Scattering Parameter Measurement. Cadence SpectreS was used to design th e 10 GHz 10-dB directional coupler. The Directional Coupler comprises six spiral inductors and five MIM capacitors as shown in Figure 5-8. Most of the signa l launched into port1 (Input Port) will arrive at port 3 (Transmit Port) with the designated sampling ratio. The rest of the signal launched into port 1 will be coupled by port 2 (Coupling Po rt) with the designated sampling ratio. Every single passive co mponent of lumped-passive circuits is calculated us ing values as shown in Table 5-2. Table 5-2. Calculation and simulation value of 10 GHz directional coupler 2.397 2.387 2Lo(nH)= 0.22 0.220 Co(pF)= 0.534 0.552 Le(nH)= 0.229 0.229 Ce(pF)= simulaiton calculation 2.397 2.387 2Lo(nH)= 0.22 0.220 Co(pF)= 0.534 0.552 Le(nH)= 0.229 0.229 Ce(pF)= simulaiton calculation Finally, a 10 dB lumped-passive-directi onal coupler was designed. As shown in Figure 5-17, at 10 GHz the simu lation results for the magnitude at port 3 and port 2 are 1.2 dB and -10.3 dB respectively. Fig. 5-17. Simulation results of 10 GHz directional coupler

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111 Next, the DPDT (Double Pole Double Thro w) switch was designed for 10 GHz as shown in Figure 5-18. The dimension of an n-MOSFET RF switch is chosen for optimum value according to various simulation results. As earlier mentioned, the minimum gate length is better for insertion loss and increasing the gate width is not always good. The simulated optimum insertion loss of this nchannel MOSFET is 1.7 dB when the number of fingers is 30, the gate length is 180 nM and the layout gate width is 4230 nM as shown in Figure 5-19. Each resist ance value at a control port (R1, R2, R3, and R4) is 33 krespectively. The re sistance value of R5 and R6 is chosen for optimum insertion loss as 40 k. The isolation between both inputs and outputs are about -29 dB at 10 GHz as shown in Figure 5-19. Port1 Port4 Port2 Port3 Port1 Port4 Port2 Port3 Port1 Port4 Port2 Port3 Port1 Port4 Port2 Port3 Fig. 5-18. Schematic of the 10 GHz RF switch

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112 Fig. 5-19. Simulated results of the 10 GHz RF switch The schematic of the S-R flip-flop type pha se detector, here named as Type I, is shown in Figure 5-11. Each component valu e of the phase detector is decided for optimum value according to various simulation results as shown in Table 5-3. Simulations of the phase detector are show n in Figure 5-20. When 0 dBm input signals are applied, the differential out put varies from -91 mV to 91 mV as the delay varies from 36 to 324 degrees. However, the output is highly amplitude-dependent. -150 -100 -50 0 50 100 150 010203040506070809010 0 degreemV -20 dBm(30mV) -10 dBm(100mV) 0 dBm(310mV) 10 dBm(1V) 13 dBm(1.1V) 180 0 360 36 72 108 144 216 252 288 324 -150 -100 -50 0 50 100 150 010203040506070809010 0 degreemV -20 dBm(30mV) -10 dBm(100mV) 0 dBm(310mV) 10 dBm(1V) 13 dBm(1.1V) 180 0 360 36 72 108 144 216 252 288 324 Fig. 5-20. The simulated results of the phase detector type I at 10 GHz

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113 Table 5-3. Calculated value of th e phase detector circuit (type I) 50 pF CB 1k RB 23k Rb2 9.9k Rb1 900 Rc 50 pF CB 1k RB 23k Rb2 9.9k Rb1 900 Rc In order to reduce the magnitude depe ndence of the phase detector, a limiting amplifier was added. Without a limiting amplif ier, the phase detector would have to be calibrated for input signal magnitude and would be very insensitive to low level signals. The limiting amplifier used in this design is a Cherry-Hooper amplifier. The schematic of the HBT Cherry-Hooper amplifier is shown in Figure. 6-14. Each component value of the HBT Cherry-Hooper amplifier is decided for optimum performance according to various simulation results as shown in Table 5-4. The gain of the amplifier can be scaled without affecting its basic band width by adjusting the R2 value and the bandwidth of amplifier can be controlled by adjusting the Rf value. [Chr04]. Simulations of the HBT CherryHooper are shown in Figure. 5-21. Table 5-4. Calculated value of the HBT Cherry-Hooper amplifier 450 R2 75 R1 90 Rf 450 R2 75 R1 90 Rf Fig. 5-21. The simulation of HBT Cherry-Hooper amplifier

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114 As stated early, the phase detector output is highly input-amplitude-dependent. To reduce this effect, a Type II phase detect or was designed combining the chain of differential Cherry-Hooper amplifiers with a Gilbert cell phase detector as shown in Figure 5-22. Gilbert Cell phase detector Cherry-Hooper Limiting Amp Gilbert Cell phase detector Cherry-Hooper Limiting Amp Fig. 5-22. Structure of th e type II phase detector The simulation results for this detector are shown in Figure 5-23. The differential output varies from -836 mV to +836 mV as the phase varies from 144 to 324 degrees. The amplitude dependence is greatly reduced and this circuit can be used over a wide range of input signal powers. -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0102030405060708090100 degreemV 14 dBm 0 dBm -16 dBm 180 0 360 36 72 108 144 216 252 288 324 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0102030405060708090100 degreemV 14 dBm 0 dBm -16 dBm 180 0 360 36 72 108 144 216 252 288 324 Fig. 5-23. Simulated results of the phase detector type II at 10 GHz

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115 The schematic of the peak detector is shown in Figure 5-16. Each component value of the peak detector is decided for its optimum value according to various simulation results as shown in Table 5-5. Simulations of the peak detector are shown in Figure 5-24. The DC output changes from 1 mV to 935 mV as the input sweeps from -29 dBm to 11 dBm. Table 5-5. Calculated value of the peak detector 3.079k R1, R2 93.44 fF C4 140.16 fF C3 93.44 fF C2 2.065 pF C1 3.079k R1, R2 93.44 fF C4 140.16 fF C3 93.44 fF C2 2.065 pF C1 Fig. 5-24. Simulated results of the peak detector 5.6 Measured Results The embedded s-parameter measurement st ructure was fabricated with the IBM 0.18 micron SiGe BiCMOS-7 WL technology through the MOSI S fabrication service. The measurement of the DPDT switch was performed by using an on-chip Cascade Microtech Air Coplanar Probe (ACP) and a HP8510C Network Analyzer. The photomicrograph of the phase detector type I and DPDT switch is shown in Figure 5-25. The total chip size is about 1.2 mm2 (1.0 mm X 1.2 mm).

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116 Fig. 5-25. Die micrograph (1.0mm x 1.2mm) of the phase detector type I and DPDT switch Measured results for the DPDT switch are shown in Figure 5-26. The insertion loss is -2.2 dB and the isolation is -19 dB at 10 GHz, agreeing well with simulations. Fig. 5-26. The measured results of the DPDT switch Phase Detector DPDT switch

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117 -200 -150 -100 -50 0 50 100 150 010203040506070809010 0 degreemV 3dBm 6dBm 0dBm -3dBm -6dBm -10dB 180 0 360 36 72 108 144 216 252 288 324 -200 -150 -100 -50 0 50 100 150 010203040506070809010 0 degreemV 3dBm 6dBm 0dBm -3dBm -6dBm -10dB 180 0 360 36 72 108 144 216 252 288 324 Fig. 5-27. The measured results of the DPDT switch The measurement of the the Type I phase detector (without the limiting amplifier) was performed by using an on-chip Cascad e Microtech Air Copl anar Probe (ACP), Agilient signal generator E8254A, an adjust able phase delay ARRA 9426A and Agilent oscilloscope 54622D. Measurement results fo r the Type I phase detector (without limiting amplifiers) are shown in Figure 5-27. With 0 dBm input, the DC output varies from -128 mV to 88 mV as phase varies fr om 36 to 324 degrees. In agreement with the simulations, the DC output varies si gnificantly with input amplitude. The peak detector and the Type II phase detector with 4-stage limiting amplifiers were fabricated on a second chip using the same technology. The measurement of the the Type II phase detector (w ith limiting amplifier) was perf ormed by using an on-chip Cascade Microtech Air Coplanar Probe (A CP), Agilient signal generator E8254A, an adjustable phase delay ARRA 9426A and Agilent oscilloscope 54622D. A photomicrograph is shown in Figure 5-28. The total size of this chip is about 2.64 mm2 (1.2 mm x 2.2 mm).

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118 Fig. 5-28. Die micrograph (2.2mm x 1.2mm) of the phase detector type II and phase detector Measured results for the Type II phase detector are shown in Figure 5-29. The results are very similar to the simulations. DC output vari es from -645 mV to 798 mV with 0 dBm input as phase varies from a bout 144 to 324 degrees. Further, the reduced amplitude dependence is consistent with simulation. -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0102030405060708090100 degreemV 0 dBm(Sim) 0 dBm 14 dBm 4 dBm -6 dBm -11 dBm -16 dBm 180 0 360 36 72 108 144 216 252 288 324 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0102030405060708090100 degreemV 0 dBm(Sim) 0 dBm 14 dBm 4 dBm -6 dBm -11 dBm -16 dBm 180 0 360 36 72 108 144 216 252 288 324 Fig. 5-29. The measured results of the pha se detector type II with Cherry-Hooper amplifier Peak detector Phase detector

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119 Measured results for the peak detector are shown in Figure 5-30. The DC output varies from 0 mV to 935 mV according to -29 dBm to 11 dBm i nput. The measurement results show good agreement with simulation results. Fig. 5-30. The measured results of the peak detector 5.7 S-parameter Application A series of simulations demonstrate how the proposed circuits can be used in measuring s-parameters. A DUT circuit was created using passive elements from the IBM design library; the DUT’s simulated S21 was (-0.54 dB, -90.0). Divider Divider Peak Detector Phase Detector DUT P1 P2 P3 90 Delay S/W1S/W2 S/W3 S/W4 Bypass1 Bypass2 Divider Divider Peak Detector Phase Detector DUT P1 P2 P3 90 Delay S/W1S/W2 S/W3 S/W4 Bypass1 Bypass2 Fig. 5-31. Block diagram for verifi cation of s-parameter measurement

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120 As shown in Figure 3-31, the s-paramete r setup uses two dividers, a 90 phase delay circuit, a peak detector and a phase detector. In an initial calibration step, the DUT and the 90 delay are both bypassed. The dc peak detector output at P2 is found to be 275 mV, corresponding to 0.96 dBm according to Figure 3-32. The phase detector output at P3 is -367 mV, corresponding to -291 from Figure 3-33. To measure the DUT’s sparameters, Bypass-Line1 is removed and the 90 phase delay is left bypassed. The peak detector output becomes 257 mV, correspondi ng to 0.44 dBm, and the phase detector output becomes 620 mV, correspo nding to -20.7 or -305. To resolve the ambiguity in the phase, Bypass-Line2 is removed and the phas e is measured again. The phase detector output with 90 phase delay becomes 325 mV, corresponding to -108.7 or -230.5. Only the first set of phase values is self-consistent, so the phase measurement with the DUT but without the 90 phase delay is interprete d as -20.7. By subtra cting the calibration values, the magnitude of the DUT’s S21 is found to be -0.52 dB, and the phase is -89.3, consistent with expectation. 150 170 190 210 230 250 270 290 -3-2-101dBmmV 275mV:0.96 dBm 257mV:0.44 dBm 150 170 190 210 230 250 270 290 -3-2-101dBmmV 275mV:0.96 dBm 257mV:0.44 dBm Fig. 5-32. Peak detection of s-parameter measurement module

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121 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0102030405060708090100 degreemV 14 dBm 0 dBm -16 dBm 180 0 360 36 72 108 144 216 252 288 324 -367mV:291 325mV:108 -620mV:21 -620mV:305 325mV:231 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0102030405060708090100 degreemV 14 dBm 0 dBm -16 dBm 180 0 360 36 72 108 144 216 252 288 324 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0102030405060708090100 degreemV 14 dBm 0 dBm -16 dBm 180 0 360 36 72 108 144 216 252 288 324 -367mV:291 325mV:108 -620mV:21 -620mV:305 325mV:231 Fig. 5-33. Phase detection of s-parameter measurement module As shown in Figure 5-34, another s-parame ter measurement application is shown. These proposed s-parameter modules which cons ist of directional c ouplers, RF switches, dividers, phase delays, peak detectors and phase detectors could be integrated in a microwave probe. As previously mentioned, very expensive RF and microwave test equipment (vector network analyzers) are requ ired with microwave probe for testing and verification for the RF and microwave compon ents. This traditional test method using microwave probe station and microwave test equipment includes a long time to set up and calibrate test equipment. The proposed application shows a built-in s-parameter measurement probe. If accurate calibrati on was done, this built-in s-parameter measurement probe can be used for many te sts without very expensive microwave test equipment and can be used without the long set up time for test equipment.

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122 DUT Coupler SW Peak Detector Divider Phase detector 90 SW SW 50 Coupler s-parameter measurement module Analog Connector Package RF DUT Connector PCB RF Probe RF Source Connector DUT Coupler SW Peak Detector Divider Phase detector 90 SW SW 50 Coupler s-parameter measurement module Analog Connector Package RF DUT Connector PCB RF Probe RF Source Connector Fig. 5-34. Example of s-parameter measurement application 5.8 Conclusions This chapter presents the design, simu lation and measurements of integrated BiCMOS s-parameter measurement circuits for low cost IC test. To verify the proposed s-parameter measurement idea, key subc ircuits are designed and fabricated. 1) One of these subcircuits is the DPDT switch which controls the signal path for measurement. Measured results for the DP DT switch are shown in Figure 5-26. The insertion loss is 2.2 dB and the isolation is -19 dB at 10 GHz, which agrees well with simulations. 2) The second key circuit for s-parameter module is the peak detector. The voltagedivider enhanced RF power detector [Zha04] was designed for peak detection. The DC output varies from 0 mV to 935 mV accordin g to -29 dBm to 11 dBm input which shows good agreement with simulation. 3) The measurement of a Type I phase detector (without limiting amplifier) was performed. Measurement results for the Type I phase detector (without limiting

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123 amplifiers) show good agreement with th e simulation but the DC output varies significantly with the RF input amplitude. That is the major weak point of the Type I phase detector (without limiting amplifier). For this reason, the Type II phase detector was designed. Measured results for the Type II phase detector are very similar to the simulations. Further, the reduced amplitude dependence is consistent with simulation. 4) Using the results of this research the author proposed an s-parameter measurement application to demonstrate how the dissertation circu its can be used in measuring s-parameters. A DUT circuit was created using passive elements from the IBM design library; the DUT’s simulated S21 was (-0.54 dB, -90.0). By using the proposed s-parameter measurement met hod, the magnitude of the DUT’s S21 is found to be -0.52 dB, and the phase is -89.3, cons istent with expectation. The measurement uncertainty of the magnitude is lower than 0. 5 dB and the measuremen t uncertainly of the phase is lower than 4 Therefore the s-parameter module meets the proposed specification and shows the potential to repla ce a very expensive network analyzer by an on-chip s-parameter measurement module. 5) The previously introduced s-parame ter measurement example was based on simulation data. Therefore, these results do not include process variations and mismatches. To overcome the errors caused by the process variation and mismatches, calibration is needed. Without th e calibration, the s-parameter te st circuits could not meet the specifications. This is the same situation as with the commercial network analyzer. Expensive commercial network analyzers also need a complex calibration step to achieve their specifications. The calibrated phase measurement precision of the on-chip solution is simulated to better than 3 as shown in Figure 5-35.

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124 Fig. 5-35. Phase error calculation with calib ration to 0 dBm reference of s-parameter measurement module 6) Another s-parameter measurement applic ation which could be integrated in a microwave probe is proposed. This built-in s-parameter measurement probe can be used for many tests without very expensive microwav e test equipment and can be used without the long test setup and equipment settling time. In summary, an on-chip s-parameter measurement system has been developed for IC manufacture test. The system can be integr ated on-chip, on-wafer or placed in probes and boards for low cost RF/microwave test.

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125 CHAPTER 6 SUMMARY AND CONCLUSION 6.1 Summary In this dissertation, many embedded test ci rcuits were designed and embedded test methods for RF SoCs were explored. All of these designs were simulated by simulation tools (Cadence and ADS) and fabricated by using the IBM SiGe process. The major research items are summarized as follows. In Chapter 2, lumped passive circuits for embedded test of RF SoCs were reported. These circuits included the lumped passive directional coupler, the lumped passive divider, the lumped passive balun, and the lu mped passive hybrid. This chapter presented a more detailed design procedure and introduc ed complex mathematical equations and simulation data. These circuits were designe d for 5 GHz and were fabricated using the IBM SiGe process. The simulation and measurement results were comparable. Chapter 3 and 4 explored the use of onchip or on-wafer loopback for verifying performance of 5 GHz wireless WLAN IC circuits. The test bo ck diagram, the test circuit design and characterization data are reported for sub-circuits (attenuators, and switches), loopback test type I and loopback test type II necessary to implement 5 GHz transceiver loopback. This research is exploratory in natu re, and is a first attempt at a new on-chip RF test technique. In Chapter 5, an embedded s-parameter measurement method was proposed. This method can reduce many parasitic effect s that cause significant problems for measurement. Also, it can eliminate the use of very expensive test equipment. For this

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126 reason, embedded s-parameter measurement methods can be considered a very economical measurement method which keeps a high level of measurement accuracy. Appendix A explored a method of spiral inductor modeling using HFSS for IBM 8HP BiCMOS SiGe process. The modeling me thod and simulation results are reported. These spiral inductors were designed and fa bricated using the IBM SiGe process. The simulation and measurement results were comparable. 6.2 Conclusion Many lumped passive circu its for embedded test were designed and fabricated using the IBM SiGe process. As shown in Table 6-1, lumped passive balun, divider, and directional couplers for 5 GHz band were designed. Using the IBM-6HP SiGe process, these devices were fabricated and measured As mentioned already, the traditional methods to realize these passive circuits use microstrip line. Unfortunately, the microstrip quarter-wave length at 5 GHz is almost 8 mm a nd is too big for on-chip realization. This makes the lumped-passive circuits the only practical option to implement baluns, couplers and dividers on the silicon wafer. Through this research, the lumped passive directional coupler, divider and balun were designed for the embedded RF IC test using the silicon wafer. The integrated lumped passive circuits meet all proposed sp ecifications. These lumped passive elements proved useful in a variety of on-chip RF /microwave test systems including embedded loopback and on-chip s-parameter test systems. These results are includ ed in a paper that was accepted for presentation at th e 2004 IEEE ISCAS conference [Yoo04]. In order to realize an embedded loopback fo r the RF ICs test, an RF switch, an RF attenuator, and a LNA for 5 GHz band were designed and fabricated using the IBM-6HP

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127 SiGe process. Measurements were made and testing data was gathered and analyzed. To realize high performance at tenuation at high frequency, a method of reducing leakage through the substrate is investigated. Using th is method, an RF attenuator can be used up to 10 GHz. Compared with a traditional RF switc h, a new test RF switch is realized with half the area by reducing two transistors. The RF switch was designed for minimum insertion loss using an optim um gate dimension (the optimum gate width and the minimum gate length). The measuremen t results showed good agreement with simulation. For the loopback test experime nts, the parasitics of metal lines for interconnection are modeled and considered in simulation to improve accuracy. There is closer agreement between the simulation and th e measurement results when parasitics are considered. Through this research, the loopback test method was proposed and verified for an example TDD (Time Division Duplex) communication circu it up to 5 GHz. This is the first attempt for embedded loopback test of a wireless communication system. This proposed loopback was designed w ith minimum area in creasing (0.02 mm2) and can extend application frequency as high as th e operating frequency of the on-chip RF attenuator and RF switch. The attenuation va lue for the loopback signal can be decided according to each design application. These data were summarized in a paper for a special IC test issue under th e IEEE Trans. of Inst and M easurement [Yoo05]. Table 6-1 summarizes the designs that have been examined. Finally, chapter 5 presents the design, simulation and measurements of integrated BiCMOS s-parameter measurement circuits for low cost IC test. To verify the proposed s-parameter measurement idea, key subcircuits are designed a nd fabricated. One of these

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128 subcircuits is the DPDT switch which controls the signal path for measurement. The insertion loss is 2.2 dB and the isolation is -19 dB at 10 GHz, which agrees well with simulations. The second key circuit for s-parameter module is the peak detector. The DC output varies from 0 mV to 935 mV accordin g to -29 dBm to 11 dBm input which shows good agreement with simulation. Table 6-1. Design summary Title Description Fabrication Measurement Balun/Hybrid 2-way 180 Phase @ 5 GHz IBM-6HP done Divider 2-way in Phase @ 5 GHz IBM-6HP done Device for Embedded test Directional Coupler 10 dB directional coupler @ 5 GHz IBM-6HP done Accepted in I SCAS paper RF Switch 2 dB loss @ 5 GHz IBM-6HP done Accepted in a journal paper RF attenuator 40/50/60 dB attenuation IBM-6HP done LNA 15 dB Gain @ 5 GHz IBM-6HP done Type I Loop back before Power Amp IBM-6HP/ IBM-7WL done Embedded Loopback Test System Type II Loop back after Power Amp through coupler IBM-6HP/ IBM-7WL done RF Switch (DPDT) 2 dB loss @ 10 GHz IBM-7WL done Peak Detector IBM-7WL done Cherry Hooper Amplifier 17 dB Gain @ 10 GHz IBM-7WL done Phase detector IBM-7WL done Embedded Sparameter Measurement Ver. 1.0 Peak detector and phase detector with limiting amp IBM-7WL done Accepted in BCTM paper

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129 The measurement of a Type I phase de tector (without lim iting amplifier) was performed. Measurement results for the Type I phase detector (without limiting amplifiers) shows good agreement with th e simulation but the DC output varies significantly according to the RF input amplit ude. That is the major weak point of the Type I phase detector (without limiting amp lifier). For this reason, the Type II phase detector was designed. Measured results for th e Type II phase detector are very similar to the simulations. Further, the re duced amplitude dependence is consistent with simulation. In summary, an on-chip s-parameter measur ement system has been developed for IC production test. The system can be integrated on-chip, on-wafer or placed in probes and boards for low cost RF/microwave test. These data were summarized in a paper accepted for a BCTM IEEE [Yoo06]. Table 6-1 summarizes the designs that have been examined.

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130 APPENDIX A SPIRAL INDUCTOR MOD ELING USING HFSS A.1 Overview In modern wireless communication system s, the system on chip (SoC) is a new design technique for integration of RF and digital function blocks into single chip. Compared to active components, passive com ponents such as resisters, capacitors, and inductors require more space. These passive components also play a critical role in improving the performance of the RF circuit bl ock. Various techniques to implement the passive components on the silicon substrate ha ve been developed. One implementation method for an RF capacitor is the MIM (metal-insulator-m etal) capacitor and the MOS capacitor is another implementation method. Sp iral inductors are considered to have good frequency performances despite their low Q. At low frequency, pa ssive components such as the MIM capacitor and spiral inductors with useful values could not be integrated on the silicon substrate because they occupy a relatively larg e chip size compared with active devices. Traditionally, designers used external pa ssive components off the chip instead of internal passive components to increase Q. Recent communication systems however have adopted higher-speed and wider-band commu nication methods. For this reason, the frequency for communication tends to keep incr easing for new wireless systems. At high frequency, a relatively low passive component value is n eeded for circuit functions because this passive component reactance scal es linearly with frequency. For example, 10 GHz band circuit uses ten times lower passi ve component values compared with other

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131 circuits in the 1 GHz band. At 10 GHz, there can be huge advantages in realizing the system on chip (SoC) with onchip passive components. So, many designers have tried to realize whole system functions on a si ngle chip at microwave frequency. Passive devices such as spiral inductors and MIM capacitors play a major role in circuit function blocks, especi ally at high frequencies. Sometimes, inaccurate modeling causes serious problems, such as gain drops, frequency shifts, etc. This is the primary reason a more accurate modeling method, in combination with a simulation method, is needed. In this chapter, the spiral induc tor modeling method will be described. To provide an accurate simulation, a three-dimension EM simula tor (Ansoft HFSS) is used. A.2 Definition of Quality Factor An important parameter describing the pe rformance of the passive components is the quality factor Q, which describes a co mponents ability to st ore energy [Lud00]. The quality factor is defined as (A.1) Also the quality factor is defined as (A.2) where Wmax and Pdissipation denote the maximum energies stored and the power dissipated per cycle [Tzy03]. The quality factor is also defined as (A.3) where Im(Z) and Re(Z) denote the imaginar y and real part of impedance [Tzy03]. n dissipatio maxP W Q loss energy stored energy average Q ) Re( ) Im( Z Z Q

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132 A.3 Inductance Calculation Using Y-parameter The spiral inductor can be characterize d by its inductance value and its quality factor Q. One key characteristic, “quality factor Q”, has already been defined and another, “the inductance,” can be calculated using y-parameters. As shown in Figure A-1, the spiral inductor is realized by winding a me tal line in a spiral a nd this spiral inductor can be modeled with the circ uit shown in Figure A-2. Fig. A-1. Spiral inductor modeling for 3D-EM simulation The inductance L shows the i nductance value of the windin g metal line. The series resistor rx is the resistance at the winding metal line. The capacitors C1 and C2 at both ends are the capacitance between the meta l line and substrate. The resistors R1 and R2 at both ends are the resistance to ground through substrate. Fig. A-2. The equivalent circuit of spiral inductor L r x C 1 R 1 C 2 R 2 Port1 Port2

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133 A two port model is shown in Figure A-3. The parallel impedance ZA and ZC at both ends is (A.4) And this admittance YA can be easily calculated as (A.5) The series impedance ZB is (A.6) And this admittance YB is (A.7) Fig. A-3. Two port -model The y-parameters can be calculated using a two port -model. This two port model is symmetric so Y21 and Y12 is the same as [Lud00] (A.8) (A.9) 21 11Y Y Y Y YA B A 2 1 2 1 2 2 1 2 1 2 1 2 1 2 1 1 2 1 2 1 2 2 1 21 1 R c c R j R c c c j R c c YA 2 2 2 2 1 1 1 11 1 c j R R c j Z c j R R c j ZC A x Br L j Z j L r L L r r L j r Yx x x x B 2 2 2 2 2 21 Port1 Port2 2 2 2 12 211 1 1x x x x x x x Br L r L j L j r L j r L j r L j r sL r Z Y Y

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134 If the series resistance of metal plate rx is very small compared with the inductance value L, the rx can be considered zero. Then Y21 is (A.10) The imaginary part of this equation is (A.11) Finally, the inductance of the spiral inductor can be calculated as [Ang04] (A.12) A.4 Another Calculation Method for Spiral Inductor In the previous section, an inductance calculation method for the spiral inductor was introduced. This method is very useful if a y-parameters are available. In this section, another inductance calculation me thod is introduced. The s-parameter is considered as a very popular parameter for RF design becau se this is the fundamental method of characterization compared with other parame ters for RF design. Figure A-4 shows a 2 port s-parameter network. The s-parameters of the spiral inductor are modeled with 50 characteristic impedance in the test system. Fig. A-4. 2-port networ k of spiral inductor L j L L j Y 2 2 21 L Y im 211 21 211 1 Y im Y im L Spiral [S]Z0=50 Zs ZL sL1 2 1Z2Z Spiral [S]Z0=50 Zs ZL sL1 2 1Z2Z

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135 As shown in Figure A-4, the re flection coefficient of source, S is the reflected wave to incident wave ratio from network toward the source [Poz97]. (A.13) The reflection coefficient of load, L is the reflected wave to incident wave ratio from network toward the load. (A.14) Then, the reflection coefficient of port 1 with load impedance ZL at port 2 is (A.15) And the reflection coefficient of port 2 with source impedance ZS at port 1 is (A.16) If | L| is 1 and ZL is 0 the reflection coefficient of port 1 is (A.17) If | S| is 1 and ZS is 0, the reflection coefficient of port 2 is (A.18) Finally, the port impedance of port 1 is (A.19) And the port impedance of port 2 is 11 21 12 22 21 S S S S 22 21 12 11 11 S S S S o s o s sZ Z Z Z o L o L LZ Z Z Z L LS S S S 22 21 12 11 11 s sS S S S 11 21 12 22 21 oZ Z1 1 11 1

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136 (A.20) The quality factor of spiral i nductor is repres ented by [Dan98] (A.21) A.5 Material Assignment for Spiral Inductor Modeling The spiral inductor is usually fabricated w ith the top metal laye r (the thickest) of the IC fabrication process. Thick metal redu ces resistance of the spiral inductance and increases quality factor Q. The resistance of the spiral inducto r is the most critical factor of quality factor Q. To determine the exact resistance of the metal line, conductivity should be calculated. Although top metal material is described in every design manual, the calculation of material conductivity is usually different from the bulk material resistivity. For example, a SiGe process has a layer which is fabr icated by copper with 0.55um thickness. The normal conductivity of copper is 58,000,000 S/ m and the measured metal layer’s sheet resistance RS is 0.0373 / If the sheet resistance RS is given, the conductivity of the metal layer is one over resistivity. So th e conductivity can be calculated using (A.22). (A.22) So each metal layer conductivity should be recalculated with the measured sheet resistance RS and the layer thickness. Like me tal line conductivity, via conductivity should also be recalculated with the given pr ocess information. In an example process, vias are fabricated with 0.4 um width, 0.4 um depth, and 0.65 um thickness. This via is filled with copper. According to the process sp ecification, the resistance of via is 0.25 oZ Z2 2 21 1 22 2 1 1Z re Z im Z re Z im Q S/m 48,744,821 1 1 t Rsheet

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137 /via. The resistance of a via metal bar is ea sily calculated by simp ly using (A.23). The calculated resistance of via is (A.23) The specification and the ca lculated resistances exhibit significant difference because of non-rectangular via. Even though the example depicts a via as rectangular, it is impossible to fabricate an ideal rectangular via. So the conductivity of vi a is derived from the via resistance. The new cal culated conductivity of a via is (A.24) As determined by equation 2.26, the c onductivity of a via represents a big difference from the conductivity of copper, even though the via is fabricated using copper. This calculated conductiv ity contributes to a decrease in quality factor Q of the spiral inductor compared with quality factor Q of the ideal spiral inductor, which uses bulk conductivity for calculation. A.6 Simulation and Measurement of Spiral Inductor As shown in Figure A-5, the spiral induc tor is modeled for simulation. Ansoft HFSS is used for 3-D EM simulation. The spiral inductor test chip includes the test spiral inductor, two GSG(groundsignal-ground) pads for probing, two metal lines for connection, and two ground planes, as shown in Figure A-1. Both ground pins of GSG type RF probe are normally tied, so ideally, both ground planes are connected with very low resistance. The ground resistance is another critical factor in deciding quality factor Q of the spiral inductor. A perfect E A L R 07 0 10 4 0 10 4 0 10 65 0 10 8 5 16 6 6 7 7 2 6 610 63 1 000 250 16 10 4 0 025 0 10 65 0 1 A R L

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138 bridge is used for inductor simulation as show n in Figure A-5. This helps provide a more accurate simulation for ground resistance. Lumped port Perfect E bridge S G G Lumped port Perfect E bridge S G G Fig. A-5. Excitation for spiral inductor with GSG pad To assign the port impedance, the lumped ports are used for simulation as shown in Figure A-5. The simulation and measurement re sults of spiral induc tor are presented in Figure A-6. The transfer ratio S21 and reflection ratio S11 are shown in Figure A-6 (a). The simulation and measurement of S11 at DC is lower than -30 dB because at DC, the impedance of the spiral inductor is very small. Two ports are connected without any impedance and almost all power can be delivere d, meaning very little power (lower than 0.1%) is reflected. At 30 GHz, the impedance of the spiral inductor increases sharply so port impedance (50 ) is connected to a very high im pedance. Therefore, almost all power will be reflected due to the impedance mismatch. For this reason, the simulation of

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139 |S11| is -2.0 dB and the measurement result s exhibit good agreement with the simulation results up to 40 GHz. + Simulation-S21 Measurement-S21 Simulation-S11 Measurement-S11 + Simulation-S21 Measurement-S21 Simulation-S11 Measurement-S11 (a) s-parameter magnitude L(nH) Q Simulation-Q + Measurement-Q Simulation-L Measurement-L L(nH) Q Simulation-Q + Measurement-Q Simulation-L Measurement-L (b) Inductance L and quality factor Q Fig. A-6. Simulation and measur ement result of spiral inductor S21 is the ratio of transfer port between 2 ports. As mentioned early, the impedance of spiral inductor at DC is close to zero, so the two ports are considered to be directly

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140 connected. All power is de livered without loss, so the simulation result of S21 at DC is 0 dB. At high frequency, the impedance of sp iral inductor reaches very high impedance. Almost power is reflected because the port im pedance is relatively low compared with the spiral inductor impedance. The simulation result of S21 at 20 GHz is lower than -13 dB. The measurement results show good ag reement with simulation up to 30 GHz. Figure A-6 (b) shows the inductance L(nH) a nd quality factor Q. Equation A.23 is used for inductance calculation of the spiral inductor series element. To calculate the quality factor of the spiral inductor, the equation A.22 is used. The simulated inductance of a spiral inductor at 1 GHz is 3 nH and this inductance varies within 10 % up to 20 GHz. The measured inductance of spiral induc tor shows excellent agreement within the simulation. The simulated quality factor is 13.2 at 3 GHz and the measured quality factor is 13.3 at 3 GHz. The peak Q is located at 3 GHz and the Q decreases when the frequency is increased. The simulated Q is 0 at 12.1 GHz and the measured Q is 0 at 12.8 GHz. A.7 De-embedding Method for Spiral Inductor Traditional calibration methods for s-pa rameters have been introduced though many studies [Hav02][Cho91][Van01]. The test st ructure for the spiral inductor always includes pads and the metal connection lines as shown in Figure A-7. However, the pads and metal connection lines are unwanted compone nts. To extract the s-parameter of the spiral inductor itself, a de-embedding met hod should be considered. Many de-embedding methods have been introduced [Tie03][Tor05 ][Tie05]. One such de-embedding method was introduced by M.C.A.M. Koolen at IEEE BCTM in 1991[Koo91].

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141 (a) (b) Fig. A-7. Open and short structure for de-embedding According to Koolen’s paper [Koo91], the open structure is made for a correction of the parallel parasitics as shown in Figure A-7 (a), and a short structure is employed for a correction of the series parasitics as show n in Figure A-7 (b). Simulation and measured results are used for de-embedding verificati on. The y-parameter of test structure, Ydut, which includes the pad and interconnection metal line can be calculated using sparameters. The simulated and measured sparameters are presented in Figure A-6.

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142 S21S11 Simulation-S11 Measurement-S11 + Simulation-S21 Measurement-S21 S21S11 Simulation-S11 Measurement-S11 + Simulation-S21 Measurement-S21 (a) open S21S11 Simulation-S11 Measurement-S11 + Simulation-S21 Measurement-S21 S21S11 Simulation-S11 Measurement-S11 + Simulation-S21 Measurement-S21 (b) short Fig. A-8. The simulation and measured results of open and short structure The y-parameter of open, Yopen, and short, Yshort, structures can be calculated using s-parameter as shown in Figure A-8 (a) and (b) respectively. Then the y-parameter of spiral inductor, Yind, is

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143 1 1 1) ) ( ) (( open short open dut indY Y Y Y Y (A.27) L(nH) Q + Simulation-Q 0 Measurement-Q Simulation-L Measurement-L L(nH) Q + Simulation-Q 0 Measurement-Q Simulation-L Measurement-L Fig. A-9. Simulated and measured re sult of de-embedding spiral inductor The simulated de-embedded inductance shows good agreement with measured deembedded inductance as shown in Figure A-9. Additionally, the simulated de-embedded quality factor Q of spiral inductor shows good agreement with measured de-embedded quality factor Q. A.8 Another De-embedding Method for Spiral Inductor The traditional de-embedding methods for sp iral inductor were introduced in the prior section. To verify this method, two additional structures were designed and fabricated. One is the open st ructure for parallel parasitics and the other is the short structure for series parasitics [Koo91]. As show n in Figure A-7 and Figure A-8, this is a very popular method for de-embedding, but thos e two additional test structures, open and short, are a major weak point of this met hod. Therefore, a substitute method is proposed.

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144 Fig. A-10. Another de-embedding structure for spiral inductor. L(nH) Q + Simulation-Q Measurement-Q O Simulation-L Measurement-L L(nH) Q + Simulation-Q Measurement-Q O Simulation-L Measurement-L Fig. A-11. Simulated and measured re sult of de-embedding spiral inductor

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145 With this method, the pad and interconnect ed line are removed and an ideal ground plane is utilized for the return path as shown in Figure A-10. Two additional test structures (open and short) can be removed, so a test chip and testing procedures can be removed. That is big advantage of this proposed method. The simulation results of inductance and quality factor Q are shown in Figure A-11. These results demonstrate excellent agreement with measured results in comparison to the previously introduced method (open-short stru cture using method). A.9 Conclusion The spiral inductor, open structure, a nd short structure have been designed for spiral inductor modeling. The traditional calcul ation method for the quality factor Q and the inductance L used y-parameters. The pr oposed equations for quality factor Q and inductance L of the spiral i nductor are driven by s-parame ter because s-parameter are more convenient compare with y-parameter for the RF industry. Also, a spiral inductor modeling methods and de-embedding methods are introduced. With additional open and short test structures, the spir al inductor is modeled. Finally, an alternative de-embedding method is proposed. Using this method, the open and short additional test structure can be eliminated. As shown in this appendix, the measurement shows good agreement with simulation results. Through this research, the accurate and fast sp iral inductor modeling method was proposed and verified.

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148 [Lup03] Lupea, D.; Pursche, U.; Jentschel, H.-J., “RF-BIST: loopback spectral signature analysis,” Design, Automation and Test in Europe Conference and Exhibition, pp 478-483, 2003 [Mal79] J.A.G. Malherbe, Microwave Transm ission Line Filters, Norwood, MA, Artech House Inc. 1979 [Mal88] J.A.G. Malherbe, Microwave Tr ansmission Line Couplers, Norwood, MA, Artech House Inc. 1988 [Mey95] R. Meyer, “Low-power monolithic RF peak detector analysis,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 65-67, Jan. 1995. [Mey01] Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, New York, NY, John Wiley & Sons, Inc., 2001 [Mil96] V. Milanovic, M. Gaitan, J.C. Marshall and M.E. Zaghloul, “CMOS foundry implementation of schottky diodes for RF detection,” IEEE Transactions on Electron Devices, Vol. 43, pp. 2210-2214, Dec. 1996. [Mon55] G.B. Monteath, “Coupled transmi ssion line as symmetrical directional couplers,” IEE Proc., Part B, pp. 383-392, May 1955. [Nik00] Niknejad, Ali M., Induc tors and Transformers for Si RF ICs., Norwell, MA, Kluwer Academic Publisher, 2000 [Par89] S.J. Parisi, "180 lumped el ement hybrid," IEEE MTT-S International Microwave Symposium Digest, Vo l. 3, pp. 1243-1246, June, 1989. [Pla95] Pla, J., Struble, W., Comomb, F., “On-wafe r calibration technique for measurement of microwave circuit and de vices on thin substrates,” IEEE MTTS International Microwave Symposiu m Digest, Vol. 3, pp. 1045-1048, May 1995. [Pod00] Poddar, A.K.; Pandey, K.N., “M icrowave switch using MEMS-technology,” IEEE International Symposium on Hi gh Performance Electron Devices for Microwave and Optoelectronic A pplications, pp134-139, Nov. 2000. [Poz97] D. M. Pozar, Mi crowave Engineering, 2nd edition, New York, NY, John Wiley & sons, Inc., 1997 [Raz98] Behzad Razavi, RF Microelectrone cs Upper Saddle River, NJ, Printice Hall PTR, 1998 [Raz01] Behzad Razavi, Design of Analog CM OS Integrated Circuits, New York, NY, McGraw-Hill Book Co., 2001

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149 [Raz03] Behzad Razavi, Design of Integrated Circuits for Optical Communication, New York, NY, McGraw-Hill Book Co. 2003 [Rei96] H.M. Rein, Moller, M., “Design cons iderations for very-h igh-speed Si-Bipolar IC’s operating up to 50 Gb/s,” IEEE Journal of Solid-State Circuits, Vol. 31, pp. 1076-1090, Aug. 1996. [Son02] T.Y Song, J.H. Kim, S.H. Kim, J.B. Lim, J. S. Park, “Design of a novel lumped element backward directi onal coupler based on parall el coupled-line theory” IEEE MTT-S International Microwave Symposium Digest, Vol. 1, pp. 213 216, June, 2002 [Tie03] Luuk F. Tiemeijer and Ramon J. Havens, “A calibrated lumped-element deembedding technique for on-wafer RF char acterization of high-quality inductor and high-speed transistors,” IEEE Trans. Electron Devices, Vol. 50, pp. 822829, March 2003. [Tie05] Luuk F. Tiemeijer, Ramon J. Havens, Andre B. M. Jansman and Yann bouttement, “Comparison of the “padopen-short” and “open-short-load” deembedding techniques for accurate onwafer RF characterization of highquality passives,” IEEE Trans on Microw ave Theory and Techniques, Vol. 53, pp. 723-729, Feb. 2005. [Tor05] Reydezel Torres-Torres, Roberto Murphy-Ateaga and J. Apolinar ReynosoHernandez, “Analytical model and para meter extraction to account for the pad parasitics in RF-CMOS,” IEEE Trans. on Electron Devices, Vol. 52, pp. 13351342, July 2005. [Tra98] Trask, C., “A wide-band low-di stortion ferrimagnetic attenuator,” IEEE MTT-S International Microwave Symposium Digest, Vol. 3, pp. 1847-1850, June 1998. [Tzy03] Tzyy-Sheng Horng, Kang-Chun Peng, Je-Kuan Jau, Yu-Shun Tsai, “Sparameter formulation of quality factor for a spiral inductor in generalized twoport configuration,” IEEE Trans. On Mi crowave Theory and Techniques, Vol. 51, pp. 2197-2202, Nov. 2003. [Van01] Ewout P. Vandamme, Dominique M. Schreurs a nd Cees van Dinther, “ Improved three-step de-embedding me thod to accurately account for the influence of pad parasitics in Silicon on-wafer RF test-structures,” IEEE Trans. Electron Devices, Vol. 48, pp. 737-742, April 2001. [Viz95] Peter Vizmuller, RF Design Guide System, Circuits, and Equations, Norwood, MA, Artech House Inc. 1995 [Wes93] Neil. E. Weste, Principles of CM OS VLSI Design A System Perspective, second edition, Santa Clara, CA, Addi son-Wesley Publishing Company, 1993.

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PAGE 168

151 BIOGRAPHICAL SKETCH Jang-sup Yoon was born in Kangwon, Korea, in 1967. He received the B.S. degree in electronic communication en gineering from Han Yang Univ ersity, Seoul, Korea, in 1994, and the M.S. degree from the University of Florida, Gainesville, in 2003, where he is currently working toward the Ph.D. degree under supervision of Dr. William R. Eisenstadt. Between 1994 and 2001, he wo rked as a research engineer at LG Electronics, Anyang, Korea. From 1994 to 1997, he was involved in the TRS sy stem repeater and handset RF part. Between 1998 and 1999, he developed the LMDS hub RF part and LMDS (24~27 GHz) hub/CPE PHEMT MMIC (LNA), LMDS hub RF part & LMDS (24~27 GHz) hub/CPE PHEMT MMIC (SSPA), and microstrip to waveguide transition for LMDS. Between 2000 and 2001, he develo ped the ITS’ (5.8 GHz) RSU (Road Side Unit) RF part. Since 2002, he has been as a research assistant at embedded test for mixed signal/RFIC group, department of electrical and computer engineering, university of florida, gainesville. During the summer of 2005, he worked at Ansoft (Boston, Massachusetts) as a summer intern. He mo deled the spiral i nductor for IBM-8HP BiCMOS SiGe process using Ansoft HFSS 3-D EM simulato r. His current research interests include the lumped passive devices, device for embedded self test, and sparameter measurement method using BiCMOS technologies.


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Title: Embedded Test Circuit and Method for Radio Frequency (RF) Systems-on-a-Chip (SOCs)
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EMBEDDED TEST CIRCUIT AND METHOD FOR RADIO FREQUENCY (RF)
SYSTEMS-ON-A-CHIP (SOCS)















By

JANG-SUP YOON


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


2006

































Copyright 2006

by

JANG-SUP YOON

































This document is dedicated to my parents, my son, and my wife.















ACKNOWLEDGMENTS

I would like to express my sincere gratitude to my advisor, Professor William R.

Eisenstadt, for his devoted support and encouragement throughout my work. Without his

invaluable support and encouragement, my exploration in the research could not have

come to fruition. It has been a great pleasure to have been his student. I also would like

to thank Professors Robert M. Fox, Kenneth K. O and Loc Vu-Quoc for their advice on

this work and their willing service on my committee. I appreciate their interest in my

work and their valuable suggestions and comments from the research proposal to its

realization. I would like to especially thank Professor Robert M. Fox for his invaluable

and timely advice and encouragement to continue my work every time I eagerly look for

a breakthrough.

I would like to thank the Semiconductor Research Corporation (SRC) and Na-

tional Science Foundation (NSF) for the sponsorship of this work. I also would like to

thank IBM for the chip fabrication.

I would like to thank my colleagues Hyeopgoo Yoo, Sanghoon Choi, Kooho Jung,

Jongsik Ahn, Ming He, Qizhang Yin, Tao Zhang, Choongeol Cho, Yuseok Ko, Xiaoqing

Zhou, Xueqing Wang, Jiwoon Yang, Dongjun Yang, Inchang Seo, Okjune Jeon, and

Youngki Kim for their helpful discussions, advice, and friendship. Their support and

advice have contributed immensely to my work. Also, I thank all of the friends who made

my years at the University of Florida such an enjoyable chapter of my life









Finally, I am grateful to my parents, Hoyoung Yoon and Jungja Kwon, my sister,

Sunghee Yoon, and brother, Wonsup Yoon, for their love and encouragement throughout

the years. I would like to express my profound thanks to my wife, Youngsim Kim, for her

unconditional and never-ending love and support, and my dearest son, Sungroa. Without

them, it would not have been possible to pursue my graduate studies.
















TABLE OF CONTENTS
Page

A C K N O W L E D G M E N T S ................................................................................................. iv

LIST OF TABLES .................................................... ....... .. .............. viii

LIST OF FIGURES ............................... ... ...... ... ................. .x

ABSTRACT .............. .................. .......... .............. xvi

CHAPTER

1 IN TR OD U CTION ............................................... .. ......................... ..

1.1 Reason for Embedded RF Test. ........................................ .......................... 1
1.2 R research G oals ............................................................... 2
1.3 O outline of the D issertation....................................................................... ....... 3


2 LUMPED PASSIVE CIRCUITS FOR EMBEDDED TEST OF RF SoCs .................5

2.1 Introduction ...................................................... ....... ..... ............ .5
2.2 Design of Lumped Passive Directional Coupler ............................................ 10
2.3 Design of Lumped Passive Balun and Divider ..............................................21
2.4 Simulation of Lumped Passive Devices ............. ...............................................27
2.5 Fabrication Results of Lumped Passive Devices............................................... 38
2.6 C conclusion ....................................................... ............ ......... 43


3 EMBEDDED LOOPBACK FOR RF ICs TEST.............................. ...............46

3.1 Introduction....................................................................... ....... ...... 46
3.2 Em bedded IC Test for W LAN SoCs ........................................ .....................47
3.3 D design of L oopback C circuit ................ .... .. ......................... .....................49
3.4 Simulation of Loopback Sub-circuits and System...............................................58
3.5 Measured Results of Loopback Sub-circuits and Test System.............................67
3 .6 C o n clu sio n s.................................................. ................ 7 3












4 ANOTHER EMBEDDED LOOPBACK FOR RF ICs TEST...................................75

4 .1 Intro du action .......... ......... .. .. .. ........ .. ....................... 7 5
4.2 Design of Loopback Circuit Type 2 ............... ............................................. 77
4.3 Simulation of Loopback Sub-circuits and System Type 2 .................................79
4.4 Measured Results of Loopback Test Type 2 System................ .............. ....86
4 .5 C o n clu sio n s.................................................. ................ 8 8


5 EMBEDDED S-PARAMETER MEASUREMENT Module .............................. 89

5.1 Introduction.............................. ...... ............. ........... .......... 89
5.2 Introduction of Scattering Param eters ...................................... ............... 92
5.3 Introduction of Mixed Mode Scattering Parameter............................................96
5.4 Design for On-Chip Scattering Parameter Measurement............................. 99
5.5 Simulation for On-Chip Scattering Parameter Measurement.............................110
5.6 M measured Results........ ...... ............................... .......... ................. 115
5.7 S-parameter Application ........... .. .............................. 19
5 .8 C o n c lu sio n s ................................................................................................... 12 2


6 SUMMARY AND CONCLUSION ..... ..................... ...............125

6.1 Summary ......... ...... ....... ... ............... .........125
6.2 Conclusion ............... ......... .......................126


APPENDIX

SPIRAL INDUCTOR MODELING USING HFSS................................ ..................1.30

A 1 O v erv iew .................. ................................................................................... 13 0
A.2 Definition of Quality Factor ....................................... 131
A.3 Inductance Calculation Using Y-parameter............................. ..............132
A.4 Another Calculation Method for Spiral Inductor............................134
A.5 Material Assignment for Spiral Inductor Modeling .......................................136
A.6 Simulation and Measurement of Spiral Inductor......................... ............137
A.7 De-embedding M ethod for Spiral Inductor .............................................140
A.8 Another De-embedding Method for Spiral Inductor ............. .................143
A .9 C conclusion ....................................................................................................... 145

LIST OF REFEREN CE S ......... .................................. ........................ ............... 146

B IO G R A PH ICA L SK ETCH ......... ................. ...................................... .....................151
















LIST OF TABLES


Table pge

2-1 Specification for the commercial directional coupler.................................................6

2-2 Specification for the lumped passive directional coupler..............................................7

2-3 Specification for the com m ercial divider ........................................... ............... 8

2-4 Specification for the lum ped passive divider ........................................ .....................8

2-5 Specification for the commercial balun......... .......................................... ............. 9

2-6 Specification for the lumped passive balun......... ............ ........... .............. 9

2-7 Calculation and simulation value for the directional coupler............................. 28

2-8 Calculated value of the equivalent circuit for the directional coupler......................30

2-9 Calculation and simulation value for divider ................................... .................32

2-10 Calculated value of the equivalent circuit for the divider .................. ...............34

2-11 Calculation and simulation value for the hybrid ....................................... .......... 37

3-1. The resistor values of various attenuators ................ ................. ............... 53

3-2. Calculated value of the equivalent circuit for LNA ................................................64

3-3. Calculated value of the equivalent circuit for embedded loopback..........................66

4-1. Calculated value of the equivalent circuit for LNA of Type 2...............................81

4-2. Calculated value of the equivalent circuit for directional coupler of Type 2 ............83

4-3. Calculated value of the equivalent circuit for the embedded loopback Type 2 .........85

5-1. Specification of the commercial network analyzer and on-chip s-parameter module91

5-2. Calculation and simulation value of 10 GHz directional coupler ..........................110

5-3. Calculated value of the phase detector circuit (Type I)...................................113









5-4. Calculated value of the HBT Cherry-Hooper amplifier............... .................13

5-5. Calculated value of the peak detector ................ ........................................... 115

6-1. D design sum m ary ................................... .............. ............... ......... .. 128
















LIST OF FIGURES


Figure page

2-1. RF& IF block diagram ........................................................... ........5..

2-2. Directional coupler and detector ........... ................................... 7

2-3. The basic concept of directional coupler ...................... ...............10

2-4. Equivalent capacitance network ........ ............................................ .. ............... 11

2-5. Even mode and odd mode of transmission line............ ...............................12

2-6. Transm mission line m odel........... ................. .. ....... ..................... ............... 13

2-7. Even mode analysis of coupler and equivalent lumped model .................................14

2-8. Open case of center symmetric line in even-mode and equivalent circuit ...............15

2-9. Short case of center symmetric line in even-mode and equivalent circuit ...............16

2-10. Odd mode analysis of coupler and equivalent lumped model..............................17

2-11. Short case of center symmetric line in odd-mode and equivalent circuit ...............18

2-12. Open case of center symmetric line in odd-mode and equivalent circuit ...............19

2-13. Directional coupler and equivalent lumped model............................................20

2 -14 Sy m b ol for a b alu n ......................................................................... ................ .. 2 1

2-15. Sym bol for a divider .......... ..... ........ ................................... .. ..... 21

2 -16 17 m o d el ................................................................2 2

2 -17 T -m o d el ................................................................2 5

2-18. Schematic of lumped passive directional coupler .....................................27

2-19. The layout of the lumped-passive directional coupler ........................... ..........29

2-20. The m odel of interconnection line....................................................... ............... 29









2-21. The equivalent circuit of m etal line................................. ........................ .. ......... 30

2-22. Simulation results of lumped-passive-directional coupler .............. ...................31

2-23. Schem atic of lumped passive divider.................................................................... 32

2-24. The layout of the lumped-passive the divider .................................................33

2-25. The m odel of interconnection line.................................................. .. ... .......... 34

2-26. Simulation results of a lumped-passive divider............................................ 35

2-27. A ring hybrid (rat-race).................................................. ............................... 36

2-28. Schem atic of a lum ped passive hybrid ........................................ .....................36

2-29. Simulation results of the lumped-passive balun ...................................................37

2-30. Die micrograph (1.0mm x 1.2mm) of the lumped-passive-directional coupler.......38

2-31. Simulated and measured results of the lumped-passive-directional coupler............39

2-32. Die micrograph (1.0mm x 0.8mm) of the lumped-passive divider ..........................40

2-33. Simulated and measured results of the lumped-passive-divider ............................40

2-34. Die micrograph (1.0mm x 1.2mm) of the lumped-passive hybrid...........................41

2-35. Simulated and measured results of the lumped-passive-divider ............. ..............42

3-1. W L A N block diagram ........................................................................ .................. 47

3-2. Block diagram of embedded loopback RFIC test.................... .............................. 48

3-3. The resistor type attenuator ............................................... ............................. 49

3-4. The SPDT (single pole double throw) switches ......................................................54

3-5. N -channel M O SFE T m odel.......................................................................... .... 55

3-6. The schem atic of R F sw itch ............................................... ............................ 55

3-7. The parasitic model of n-MOS with control resistance............... ........................57

3-8. The simulated results of the RF switch with and without control resistance ............57

3-9. The schematic of the cascode low noise amplifier (LNA).............. ..................58

3-10. Simulation result of pi-type attenuator .......................................... ...............59









3-11. The gate model for optimum insertion loss of RF switch .....................................60

3-12. Simulated results of gate width (finger number) sweep from 60 to 120 at 5.2 GHz61

3-13. Simulated results of gate length sweep from 400 nM to 1300 nM at 5.2 GHz ........62

3-14. Simulated results of the RF switch .................... ............... 62

3-15. The schematic of the cascode low noise amplifier with parasitics........................63

3-16. Simulated results of the low noise amplifier with parasitics...............................64

3-17. The block diagram of the embedded loopback test model ................. ................65

3-18. The block diagram of the embedded loopback test model with parasitics ..............65

3-19. Simulated results of the loopback with parasitics circuit output power level at port 266

3-20. Die micrograph (1.0mm x 1.2mm) of the RF attenuator and RF switch..................67

3-21. M measured results of various pi-type attenuators...................................................68

3-22. M odel of the RF attenuator and substrate ........................................................... 69

3-23. Layout of the RF attenuator with and without substrate contact.............................70

3-24. Die micrograph (1.6mm x 1.1mm) of the RF attenuator and RF switch..................71

3-25. M measured results of the 30 dB attenuator ......... ...... .... ............ ............... 71

3-26. Measured results of the RF switch ............... ....... ............ 72

3-27. Die micrograph (1.85mm x 0.87mm) of the embedded loopback test model..........73

3-28. Measured results of the embedded loopback test model ........................................73

4-1. Block diagram of another embedded loopback RFIC test.......................................75

4-2. The block diagram of embedded loopback test model Type 2.................................77

4-3. The schematic of cascode low noise amplifier (LNA).............................................78

4-4. The schematic of 10 dB directional coupler.................................... ............... 79

4-5. Sim ulated results of the RF sw itch ..................................... ............... ... ........... 80

4-6. The schematic of cascode low noise amplifier with parasitics for Type 2 ...............80

4-7. S-parameter simulation result of the low noise amplifier with parasitics for Type 2 82









4-8. Gain simulation result of the low noise amplifier with parasitics for Type 2 ............82

4-9. The schematic of lumped passive directional coupler with parasitics for Type 2......83

4-10. S-parameter simulation result of the directional coupler with parasitics for Type 284

4-11. The block diagram of embedded loopback test model Type 2 with parasitics.........85

4-12. Simulated results of the loopback Type 2 with parasitics ................ ................86

4-13. Die micrograph (1.6mm x 1.2mm) of the embedded loopback test model.............87

4-14. Measured results of the embedded loopback test Type 2 model............................87

5-1. Transmission line and equivalent circuit ............ ........... ............... 92

5-2. Function diagram of s-parameter................................. ...............95

5-3. Signal diagram of mixed mode two-port network..........................................96

5-4. Conceptual diagram of mixed-mode two-port ............... .................... ............... 98

5-5. Traditional block diagram for s-parameter measurement .............................100

5-6. Receiver block diagram of traditional s-parameter measurement..........................100

5-7. Conceptual block diagram for on-chip s-parameter measurement .........................101

5-8. The schematic of 10 dB directional coupler for 10 GHz............. ................102

5-9. The schematic of DPST switch for 10 GHz ................................. ...................103

5-10. Flip-flop phase detector as a phase detector (type I).............................................105

5-11. The schematic of phase detector type I .................. .............................106

5-12. Exclusive-OR gate as a phase detector (type II)................... ........... .................. 106

5-13. The schematic of phase detector type II ...................................... .............107

5-14. The schem atic of Cherry-Hooper amplifier..........................................................108

5-15. The concept of strong impedance mismatch .................................. ............... 109

5-16. The schematic of voltage-divider enhanced RF power detector ......................... 109

5-17. Simulation results of 10 GHz directional coupler ............................................ 110

5-18. Schematic of the 10 GHz RF switch .............. .... ....................... 111









5-19. Simulated results of the 10 GHz RF switch .............................. ..................112

5-20. The simulated results of the phase detector type I at 10 GHz ...........................12

5-21. The simulation ofHBT Cherry-Hooper amplifier ................................................. 113

5-22. Structure of the type II phase detector ........................................... ...............114

5-23. Simulated results of the phase detector type II at 10 GHz .............. ............... 114

5-24. Simulated results of the peak detector............................... ..............115

5-25. Die micrograph (1.0mm x 1.2mm) of the phase detector type I and DPDT switch 16

5-26. The measured results of the DPDT switch ................. ............ .................... 116

5-27. The measured results of the DPDT switch............. .........................................117

5-28. Die micrograph (2.2mm x 1.2mm) of the phase detector type II and phase detector 18

5-29. The measured results of the phase detector type II with Cherry-Hooper amplifier 18

5-30. The m measured results of the peak detector .................................... .................... 119

5-31. Block diagram for verification of s-parameter measurement ...........................119

5-32. Peak detection of s-parameter measurement module ..........................................120

5-33. Phase detection of s-parameter measurement module ................. .. ...................121

5-34. Example of s-parameter measurement application............................122

5-35. Phase error calculation with calibration to 0 dBm reference of s-parameter
m easurem ent m odule........................................... ....................................... 124

A-1. Spiral inductor modeling for 3D-EM simulation.......... ......................132

A-2. The equivalent circuit of spiral inductor...... ...................... ...........132

A -3. Tw o port H -m odel. ......................................................................... .....................133

A -4. 2-port netw ork of spiral inductor ...................... ..... ....................... ............... 134

A-5. Excitation for spiral inductor with GSG pad. ................... ........................ 138

A-6. Simulation and measurement result of spiral inductor. .........................................139

A-7. Open and short structure for de-embedding. ................................... ..................... 141

A-8. The simulation and measured results of open and short structure...........................142









A-9. Simulated and measured result of de-embedding spiral inductor............................143

A-10. Another de-embedding structure for spiral inductor. .........................................144

A-11. Simulated and measured result of de-embedding spiral inductor..........................144















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

EMBEDDED TEST CIRCUIT AND METHODS FOR RADIO
FREQUENCY (RF) SYSTEMS-ON-A-CHIP (SOCS)


By

Jang-Sup Yoon

August 2006

Chair: William Eisenstadt
Major Department: Electrical and Computer Engineering

This proposal mainly focuses on research in embedded test circuit and methods for

RF SoCs. First, lumped passive circuits for embedded test of RF SoCs are discussed.

Many companies have been trying to integrate an entire WLAN system on a SoC. Such a

high level integration calls for research in embedded tests for the SoC. The 802-1 la

WLAN embedded IC test requires 5 GHz directional couplers, baluns, and dividers,

which are presented in this proposal. Lumped passive 5 GHz ICs were developed to

realize these compact test devices.

Second, an embedded loop back for RF ICs test is described. The loopback test is

one of the lowest cost methods for verifying functionality in a communication circuit.

Thus, the loopback test is employed in mature product lines where cost is an over-riding

concern or as a final test after other circuit tests. On-chip or on-wafer loopback circuits

are designed for verifying performance of 5 GHz wireless WLAN IC circuits.









Finally, an embedded s-parameter measurement method is discussed. Testing and

verification of the RF and microwave components are major parts of the total testing cost.

This is so because very expensive RF and microwave test equipment (for example, A

vector network analyzer) should be used for this test. Over the years, various methods

have been considered to reduce testing costs. A new method is an on-wafer s-parameter

measurement which is a very economical method for keeping high level accuracy.














CHAPTER 1
INTRODUCTION

1.1 Reason for Embedded RF Test.

A recent design trend in RF/analog technologies is to design Systems-on-a-Chip

(SoCs), which include mixed-signal/RF circuit designs. Due to advanced process

technologies, more advanced analog circuits, RF, and microwave circuits can all be

integrated. As chips become more integrated with mixed-signal/RF circuits, more

complex, higher frequency and more accurate test equipment is needed to verify SoC

performance.

In this highly competitive industry, both chip performance and chip costs are

considered important factors for industry success. Testing in this commercial market,

especially mixed-signal/RF circuits, is becoming a major cost factor in overall IC

manufacturing costs, and is the primary main reason that most IC manufacturers have

sought to research and develop new, more economically viable, test methods for mixed-

signal/RF circuits.

Furthermore, newly developed process technologies will make for more complex

chips. For this reason, high performance test equipment is needed to verify SoC

performance in today's IC production tests. However, mixed-mode ATE systems with 10

GHz test capability add significant test costs to manufactured part costs, and complicated

test procedures require increased testing time. Therefore, traditional ATE tests are no

longer low cost, and chip designers and test engineers want to find more advanced testing

methods for more highly integrated chips.









A proposed solution for the high cost of tests is embedded RF test. To verify chip

performance, some of the parameters, for example s-parameters, may be extracted from

the IC for RF testing. A method of RF microwave component on-chip or on-wafer test

has potentially huge technical advantages compared to traditional measurement methods.

One advantage of on-wafer measurements is the elimination of package effects, and

another advantage is that there are fewer complex RF test fixture effects than traditional

measurement methods. Due to these advantages, embedded RF test methods may support

more accurate component characterization. The important test trade off in this on-chip

test research is test accuracy versus required area and power on the IC.

1.2 Research Goals

The first goal of this research is to generate lumped passive circuits for 5 GHz

embedded test of RF SoCs. Many companies have been trying to integrate the whole

WLAN system on a SoC. Such a high level of integration calls for research to embedded

test for the WLAN SoC. A WLAN embedded IC test can require 5 GHz directional

couplers, baluns, and dividers, which are presented in this work. Lumped passive 5 GHz

ICs were developed to realize these compact test devices. Measurement results show

excellent agreement with simulation for the integrated 5 GHz coupler, balun and divider

designs.

The second goal of this research is to realize embedded loop back for RF IC test.

This research explores the use of on-chip or on-wafer loopback for verifying performance

of 5 GHz wireless LAN IC circuits. The loopback measurement is made for a simplified

transceiver circuit. This research is exploratory in nature, and is the first attempt at a new

on-chip RF test technique.









Finally, this research develops a new embedded s-parameter measurement method.

At RF microwave frequencies, embedded s-parameter measurements are considered an

essential measurement method. The s-parameters of a DUT (Device-Under-Test) provide

a clear interpretation of the small signal transmission and reflection performance of the

DUT. The detection and measurement of level and phase difference between two signals

are key points of s-parameter measurements.

1.3 Outline of the Dissertation

This dissertation has been organized into six chapters and an appendix. An

overview of this research is given in the current chapter, including the importance of

embedded RF test, the research goals, and the scope of this work. An appendix presents a

spiral inductor modeling method using HFSS. In this appendix, more accurate modeling

methods and faster simulation methods are reviewed.

Chapter 2 presents some lumped passive circuits for embedded test of RF SoCs. In

this chapter, a lumped passive directional coupler, lumped passive divider, lumped

passive balun, and lumped passive hybrid for embedded test and differential

measurement of RF ICs are reviewed.

In chapters 3 and 4, a method for embedded loop back ofRF ICs Test is presented.

RF switches, and loopback test circuits have been designed and characterized for

embedded test ofRF ICs. Simplified transceiver on-chip loopback circuits were built and

tested, and the performance is shown as well as the design and probing difficulties.

An embedded s-parameter measurement method is introduced in chapter 5. This

chapter discusses basic concepts and shows a block diagram to implement the proposed

idea, and also discusses the weak points and design bottlenecks of the embedded s-

parameter measurement method. To realize the proposed idea, a directional coupler,






4


DPDT (Double-Pole Double-Throw) switch, peak detector, and phase detector are

designed and a possible implementation method is briefly presented.

Chapter 6 summarizes the dissertation and presents future work for after the

dissertation.
















CHAPTER 2
LUMPED PASSIVE CIRCUITS FOR EMBEDDED TEST OF RF SOCS

2.1 Introduction

Recent design trends in RF/analog technologies show integration Systems-on-a-

Chip (SoCs) and include mixed-signal/RF circuit design. In today's production tests,

expensive equipment is needed to verify SoC performance. For example, mixed-mode

ATE systems with 3 GHz test capability can add significant test costs to a manufactured

part cost.

Receiver

MIXER
1 > DeMOD

ANT LNA BPF AMP




SW \LO
S sw SYNTH

ANT Transmitter

HPA BPF AMP
IC MOD

MIXER


Fig. 2-1. RF&IF block diagram

To realize RF/analog signal test on the SoC, each part (RF and IF block and digital

control block) should be tested simultaneously. As shown in Figure 2-1, the RF and IF

blocks consist of three function units (receiver, transmitter, and synthesizer). Testing the









functional unit (receiver, transmitter, and synthesizer), instead of testing each small sub-

circuit, is considered to be a reasonable tradeoff between test efficiency and completeness

for a mature and well understood IC part. Care must be taken so a part with a strong

transmitter does not make a weak receiver look like it meets a test specification.

To test the transmitter, the output signal at the high power amplifier (HPA) should

be monitored. Therefore, monitoring the signal power level of each subcircuit without

affecting the signal path is a key in realizing the embedded test of an RF/analog SoC

signal. A noninvasive power monitoring circuit may consist of a directional coupler and a

power detector as shown in Figure 2-2. The DC output values of the detector correspond

to the power level. In this way, an on-chip test can monitor DUT power without

disturbing circuit operation. Therefore, a directional coupler is the key component for this

embedded test. A working sampler (directional coupler) is designed for 5 GHz wireless

LAN IC test. There are two major specifications to characterize the performance of the

directional coupler. One is the coupling and another is the insertion loss. In this research,

a 10-dB directional coupler was designed for 5 GHz. The specification of the commercial

directional coupler (Anaran 10610-10) is shown in Table 2-1.

Table 2-1 Specification for the commercial directional coupler
Coupling 10+0.5 dB
Insertion loss 1 dB max
Impedance 50 ohm

The coupling ratio at coupling port is 10 + 0.5 dB and the insertion loss is lower

than 1 dB. The dimension of this directional coupler is bigger than 30mm x 50 mm.









Table 2-2 S )ecification for the lumped passive directional coupler
Coupling 100.5 dB
Insertion loss 2 dB max

Impedance 50 ohm


The proposed directional coupler is designed using the lumped passive circuits to

realize it on the silicon wafer. So the target area for this directional coupler is less than 1

mm2. Even though dramatically less area is employed compared with a commercial

directional coupler, the proposed specification for the lumped directional coupler has the

same coupling and less than 2 dB insertion loss as shown in the Table 2-2.



Input Through



Isolated \ Coupled



Coupler
Output



Detector


Fig. 2-2. Directional coupler and detector

Other proposed lumped passive circuits are the lumped passive balun and the

lumped passive divider. Most of RF applications adopt single-ended (common-mode)

analyses. But in balanced circuits, common-mode analysis and differential-mode analysis

must be considered [Bok97] [Bok95]. Similar to the directional coupler case, the working

sample is designed for a 5 GHz wireless LAN IC test. There are three major

specifications to characterize the performance of the divider. One is the phase difference









between two dividing ports and the second is the insertion loss. The third is the amplitude

difference between two ports. The lumped passive divider was designed for 5 GHz. The

specification of the commercial divider (Meca 802-2-6.000) is shown in Table 2-3. The

phase difference between two ports are 0 + 4 and the insertion loss is low than 1 dB. The

amplitude difference between two ports is within 1.5 dB and the dimension of this divider

is bigger than 25mm x 20 mm.

Table 2-3 Specification for the commercial divider
Insertion loss 1.0 dB max
Phase difference 0 4'
Amplitude difference 1.5 dB max
Impedance 50 ohm

The proposed divider is designed using the lumped passive circuits to realize it on

the silicon wafer. Similar to the lumped passive direction coupler, the target area for the

lumped passive divider is less than 1 mm2. The proposed specification for the lumped

passive divider is shown in the Table 2-4.

Table 2-4 Specification for the lumped passive divider
Insertion loss 1.5 dB max
Phase difference 0 4'
Amplitude difference 1.5 dB max
Impedance 50 ohm

On the other hand, analyzing the differential-mode [BokOO] requires a device (a

balun) that divides signals into two branches with equal magnitude and opposite polarity

(1800 out of phase). This working sample also is designed for 5 GHz wireless LAN IC

test. Similar to the divider, there are three major specifications to characterize the

performance of the balun. One is the phase difference between two dividing ports and the









second is the insertion loss. The third is the amplitude difference between two dividing

ports. The lumped passive balun was designed for 5 GHz operation. The specification of

the commercial balun (Johanson Technology 5250BL14B100) is shown in Table 2-5. The

phase difference between two ports are 180 + 15 and the insertion loss is lower than 1

dB. The amplitude difference between the two ports is within 1.5 dB and the dimension

of this divider is roughly 1.6mm x 0.8 mm.

Table 2-5 Specification for the commercial balun
Insertion loss 1.0 dB max
Phase difference 180 15'
Amplitude difference 1.5 dB max
Impedance 50 ohm

The proposed balun is designed using the lumped passive circuits to realize it on

the silicon wafer. Similar to the lumped passive directional coupler, the target area for

lumped passive divider is less than 1 mm2. The proposed specification for the lumped

passive balun is shown in Table 2-6.

Table 2-6 Specification for the lumped passive balun
Insertion loss 1.5 dB max
Phase difference 180+ 15
Amplitude difference 1.5 dB max
Impedance 50 ohm

As mentioned already, for embedded IC test, a directional coupler, a balun and

divider are needed. The traditional method to realize these passive circuits uses

microstrip lines or lumped passive components [Par89]. Unfortunately, the quarter-wave

length at 5 GHz is almost 8 mm and is too big for on-chip realization. Therefore making

the lumped-passive circuits is the only practical option.









2.2 Design of Lumped Passive Directional Coupler

The lumped passive circuit design style is as follows. First, a distributed microstrip

circuit is designed with a large area, and then a compact lumped equivalent circuit is

extracted from the distributed circuit. Second, the design of the coupled line directional

coupler for 5 GHz is presented. The main function of this directional coupler is to sample

power from sources. Directional couplers[Bah03] are also used for measuring unknown

impedances, detecting antenna faults, and combining and or splitting power. There are

various types of directional couplers including branch line couplers, wave guide couplers,

Lange couplers [Lan69], Wilkinson dividers [Wil60] and coupled line directional

couplers [Mon55].

The coupled line directional coupler [Poz97][Mal88][Mal79] is one of the most

popular directional couplers at microwave frequency bands. When the transmission lines

are located close to each other, power will be coupled as shown in Figure 2-3. The

coupler consists of a pair of transmission lines and is modeled as a 4-port network. Most

of the launched power at port 1 will be delivered to port 4. Due to the interaction of the

electromagnetic fields, some power will be coupled to port 2. As shown in Figure 2-2, if

port 1 and port 4 are considered the input port and output port, respectively, port 2

becomes the coupling port and port 3 becomes an isolation port.

Port 2 Port 3
Coup Ihg N Iso atbn




Port1 Port4
Input Transm it


Fig. 2-3. The basic concept of directional coupler









Typically the coupled transmission lines operate in TEM mode, and the electrical

characteristics of the coupled lines can be modeled as a function of the effective

capacitances between the lines. As shown in Figure 2-4, the coupled transmission lines

parameters C11, C22, and C12. C12 are defined as the capacitance between the two

transmission lines, while, C1 and C22 are defined as the capacitance between the

transmission lines and the ground. If the widths of the two transmission lines and the

distance of the transmission lines from ground are the same, then C11 will equal C22.






C1 1 212 22








Fig.2-4. Equivalent capacitance network

In analyzing the coupled line directional coupler, one should consider the even and

odd modes. As shown in Figure 2-5-(a), in the even mode, the current flows in the same

direction with the same magnitude, and the electric flux is symmetric with respect to the

H-wall. Conversely, in the odd mode, as shown in Figure 2-5-(b), the current flows in the

opposite direction with the same magnitude, and the electric flux is also symmetric with

respect to the E-wall. In this case, conductor 1 is emitting electric flux while conductor 2

is sinking flux thus making the E-wall an equipotential surface with V=0, and the E-wall

acting as the ground plane.









+V +V




1 2






H-wall

(a) Even-mode

+V -V




1 2






E-wall

(b) Odd-mode

Fig. 2-5. Even mode and odd mode of transmission line

As shown Figure 2-5, the coupled line directional coupler consists of two

transmission lines. For analysis, each transmission line can be modeled as shown in

Figure 2-6. The voltage at the source (x=-l) and the load (x=0) can be equated as follows:

V, = VLe- I (2.1)

V = V(- /1)= V (e'# + Fo ) (2.2)


VL =V(O)= V (1+ ) ,where = ZL Zo (2.3)
ZL + Z









The input impedance of the transmission line with the characteristic impedance of

Zo, and the termination load of ZL, can be expressed as,

Z, + jZo tan fl
Zl = Z0
Zo + jZ tan/ l (2.4)

Also the voltage at the source can be expressed as the function of the voltage of the

load (VL), the load impedance (ZL), the characteristic impedance (Zo), and the electrical

length p .

Vs = VL (cos/ + jZo/Z sin/ /) (2.5)

Zu

zo
V+ ZL
Vs VL


x=-I x=o
/ T X= -I X=O



Fig. 2-6. Transmission line model

If Vi=Vs, V4=VL, P31=, ZI=I/yi=Zo/ZL, then

V4 1 y,
V4-4 = --- = l (2.6)
V, cosO+ jZ sin0 y cos+ jsinO

The coupling factor is

C = Ze Z00
Zoe + Zoo (2.7)


Zoe= Zo (C
o 1 -C (2.8)










zoo= zo (c
V1+C (2.9)

To design a 10 dB coupled directional coupler, one calculates Zoe and Zoo. To

realize the coupled line directional coupler, the line width (W) value and the line spacing

(S) between two lines should be calculated first. This complex manipulation is beyond

the dissertation focus. To convert a coupled-line-directional coupler to a lumped-passive-

directional-coupler [Par89] [Son02], first the even-mode is handled.




Yoe


Yin


(a) Coupled-line coupler


2 Le


CYin e I Ce




(b) Equivalent lumped model

Fig. 2-7. Even mode analysis of coupler and equivalent lumped model

The directional coupler has horizontal symmetry (with respect to the two parallel

lines) due to the H-field wall and vertical symmetry (symmetry axis with respect to the

center of transmission lines) due to its symmetrical structure. Therefore, the analysis for

half of one transmission line can be used for the whole directional coupler as shown in








Figure 2-7. If the center symmetric line is open as shown in Figure 2-8, the input

impedance of the coupler is

0 1
Z, = jZe cot- (2.10)
2 sCe

sCe =jZ0o tan (2.11)
2

Zoo 0
Ce oo tan (2.12)
a) 2


Y02


Zoe



Zin


(a) Even-mode open case



Le



Ce
Zin



(b) Equivalent Circuit

Fig. 2-8. Open case of center symmetric line in even-mode and equivalent circuit






16

Now, consider the shorted case of the center symmetric line in the even-mode as

shown in Figure 2-9. This is similar to the open case, the input admittances of coupler are


Z,n = jZoe tan


1 0
Y, = Z0o cot
j 2

1
Y = sCe +-
sLe



I 2


O Zoo



Yin


Yin


(2.13)


(2.14)


(2.15)


/77


(a) Even-mode short case


Le


, Ce


(b) Equivalent Circuit

Fig. 2-9. Short case of center symmetric line in even-mode and equivalent circuit

The value of Le is delivered from,








0
jZ0ocot -
2


Z
L oe sin 0
2ow


The next step is solving for the odd-mode case. The odd-mode, with the E-wall

located horizontally, acts as a ground plane at the center as shown in Figure 2-10.



................................. ................


Zoo I


Zin


(a) Coupled-line coupler


Ce Le
-F Le


Lo


Zin
Zin


Le


2C
O


Ce

Lo
Lo


(b) Equivalent lumped model
Fig. 2-10. Odd mode analysis of coupler and equivalent lumped model
For a vertically symmetric shorted line, the equivalent circuit is shown in Figure 2-


1
sCe + -
sLe


(2.16)


(2.17)









0/2
.............................................................................................. .

Yoo -


Yin


(a) Odd-mode short case



Yn Ce Lo Le
Yin



(b) Equivalent Circuit

Fig. 2-11. Short case of center symmetric line in odd-mode and equivalent circuit

The input impedance of transmission line as shown in Figure 2-1 l-(a) becomes

0
Z,, = jZ0 tan -
2 (2.18)

0
= jYo cot -
2 (2.19)

And the input admittance of the equivalent circuit in Figure 2-1 l-(b) is

1 1
Yn = J)C, + -+-
S joLe j )Lo (2.20)

The even-mode equivalent parameters are derived (Ce, Le, Zoo and Zoe); Lo is

formed by using a simple manipulation.

1
Lo = (2.21)
C Zo cot +Zootan 2Z sinO0


Since 8=900, Lo simplifies as






19


L,=- (Zo Z) (2.22)


Given that the vertical symmetric line is open, the equivalent circuit as shown in

Figure 2-12-(b).

S/2
Open
S..................................................................... O p e n
o- Yoo

Yin

(a) Odd-mode short case

Le


CYin Ce Lo Co


(b) Equivalent Circuit

Fig. 2-12. Open case of center symmetric line in odd-mode and equivalent circuit

The input impedance of transmission line in Figure 2-12-(a) becomes

Z =- jZo cot-
2 (2.23)


= jYoo tan -
2 (2.24)

And the input admittance of the equivalent circuit in Figure 2-12-(b) is

1 1
1
joL joL, + 1------
JC (2.25)jL
jcC0 (2.25)









The even-mode and odd-mode equivalent parameters (Ce, Le, Lo, Zoo and Zoe) are

already found. Co is formed by using a simple manipulation.


2 (Zo-Zo)
0 sinO (1+ Zoe(Zo-Zoo))

Since 8=900, simplified Co is

2 (Zo-Zoo)
o0 (1+Zo(Zo -Zoo))


(2.26)


(2.27)


Finally, the equivalent lumped model of a directional coupler with every element is

shown in Figure 2-13.


e
................................. .....


Symmetric
plane


Zoe, Zoo

(a) Coupled-line coupler


Cel


Ce x? Ce


(b) Equivalent lumped model


Fig. 2-13. Directional coupler and equivalent lumped model









2.3 Design of Lumped Passive Balun and Divider

Two other important on-chip test circuits are the balun and the divider. The balun is

a three-port network with a 1800 phase difference between the two output ports. With

reference to the balun shown in Figure 2-14, a signal launched into port 1 will be evenly

split into two components with a 1800 phase difference at port 2 and port 3.



90-





270


Fig. 2-14. Symbol for a balun

The divider, is also a three-port network, but with the same phase between the two

output ports. As shown in Figure 2-15, a signal launched into port 1 will be evenly split

into two in-phase components forwards 2 and port 3.


900 3





90"


Fig. 2-15. Symbol for a divider

The balun is created by combining a 900 phase delay branch and a 2700 phase delay

branch. The divider is created by combining two 900 phase delay branches. The









scattering matrix of a 900 phase delay branch is labeled as [Si] and the scattering matrix

of a 2700 phase delay branch is labeled as [S2].


(2.28)


0 1Z90 0 -j
21 = 1 90 0 -) lj O j



2 1Z270 0 j


This phase delay branch of the scattering matrix [Si] can be modeled as a n model

as shown in Figure 2-16. All series and shunt components are given as admittances Yi,

Y2 and Y3.


Fig. 2-16. H model

The ABCD parameters for Figure 2-16 are;

A=l+ 2


(2.30)


B=


(2.31)


YY
C=Y+Y,+1


(2.32)


(2.29)










D=1+


(2.33)


If Yi=Y2, then the ABCD parameters reduce into;


A=]+ l


(2.34)


B=
Y,


C = 2Y, + 1
Y,


(2.35)


(2.36)


D=1+


(2.37)


Using a table of conversions for two-port network parameters, the s-parameters of

this H model are obtained.


A+ B -CZ -D
A + BZ +CZo+D
0z

-A+B -CZ,+D

22 A+B +CZo+D
0z

2(AD BC)
S-,
12 A+B + CZo + D
/ Z

2
S -
21 A+B +CZ+D
AB


-(Y 2Z2 +2YY3Z2 _1)
y12ZO2+2Y,(Y3Zo +)Z +2YZo +1



-(2Zo +2Y,3Z2, -1)
2Zo2+2Y, (Y3Zo +)Zo +2Y3Z +1


2Y3Zo
2ZO+2Y, (Y3Zo +1)Zo + 2Y3Zo +1


2Y3Zo
2Zo2 + 2Y(Y3Zo +1)Zo+ 2Y3Zo +1


(2.38)




(2.39)



(2.40)


(2.41)









-(Y2Z2+ 2YY3Z2 -1)
I 2Zo2+2(Y3Zo + 1)Z + 2Y3Zo +1
2Y3ZO
2ZO2 + 2Y (Y3Zo + 1)Zo + 2Y3Zo +1


Since S11 = S22 = 0,


-(Y2Z2 +2YYZ2, -1)
112Z2 + 2Y(Y3Z + 1)Zo + 2Y3Zo + 1


(I -Y2Z )
2Y Z2
Y-,o20
2F72,


Substituting Y3 to equation "S12 -j",

S12 z +2YZ2 2 +Y Z +2o Z+
11Zo +2Y,1(Y3Zo +l)Zo +2Y3Zo +1


2Y3Zo
y2ZO2 + 2Y (Y3Z + 1)Z + 2Y3Zo+1
(2ZO2 +2YY3Z2 -1)
y12Z2 + 2Y,(Y3Zo +1)Zo +2Y3Zo +1


The other phase delay branch of the scattering matrix [S2] can be modeled as a T

model as shown in Figure 2-17. All series and shunt components are given as impedances


Zi, Z2 and Z3.


=[o -j1


(2.42)


Y2Zo, + 2Y,3Z2 = 1

YZ(Y2 1 +2Y3)=


(2.43)


(2.44)


(2.45)


(2.46)


(YIZO
YIzO +1


(2.47)

(2.48)


cZoZ


(I2Y 2Z
2Y1Z2
1Y, 70


(2.49)


(2.50)


(2.51)
























Fig. 2-17. T-model

The ABCD parameters for Figure 2-17 are;


A=l+ Z
Z,


B=Z1+ ZZ2
B = Z, + Z2 2


D =1+
Z,

If Z=Z2, then the ABCD parameters reduce into,

A=l+ Z
Z3


B = 2Z +
Z3


C=
Z3


(2.52)


(2.53)


(2.54)


(2.55)


(2.56)


(2.57)


(2.58)









D=1+


(2.59)


Using table of Conversions for Two-Port Network Parameters, the S-parameters of

this T model are obtained.


A+B -CZ, -D
A+ /Zo +CZo +D
ZA + B CZo + D
-A+B/ -CZ,+D
A+ BZ +CZo+D

2(AD- BC)
A + BZ +CZo+D

2
A+BZ +CZo+D
o o


2 (Z02- z1(z2z +23))
SZ Z, (Z,+2Z3,)
Z2 +2Z0(Z,+Z3)+Z,(Z +2Z3)


-(Z2-Z,(Z, +223))
Z,2+ 22(Z, +Z,3)+Z, (Z, +2Z3,)


2ZOZ3
ZO2 +22o(Z, + Z3)+ Z,(Z + 2Z3)



Z2 +220(Z, +Z3)+Z,(Z +223)


(2.60)



(2.61)



(2.62)



(2.63)


-(Z02 -Z1(+2Z3)) 2ZoZ3
Zo2 +2Zo(ZI +Z3)+ ZI(ZI +2Z3) Z2 +2Zo(Z +Z3)+ Z1(Z +2Z3)
2ZoZ3 -(Z2- Z(Z +2Z3))
Z2 +2Zo(ZI +Z3)+Z,(Z +2Z3) Z2 +2Zo(ZI +Z3)+Z1(Z +2Z3)


l = -(Z02 -Z(Z, +2Z3))
S o2+2Zo(Z, +Z3)+Z,(Z1 +2Z3)

Z02 Z, (Z1 + 2Z3)= 0

z2 _z2
Z3 0 1
2Z1

Substituting Z3 to equation "S12 =j",


(2.65)

(2.66)


(2.67)


0 j
S= ]
j 0.


(2.64)

Since S11 = S22 = 0,









2ZOZ3
Z2+ 2Z0(Z + Z3)+ Z (Z + 2Z3)


Z0 Z,
Zo + ZI


Z, = -jZ


1
co Z


z2 2
Z3 -
2Z,


(2.68)

(2.69)

(2.70)


(2.71)


(2.72)


2.4 Simulation of Lumped Passive Devices

The Directional Coupler is composed of six spiral inductors and five MIM

capacitors as shown in Figure 2-18.


.1


dFnd
. .v*A I I .




- - - Ti
*nur r I2


dIA A
.1 ,li


ab(p -'~'----.---"


I ..) . .
. . . .
',bl '^,', ,^ '


r-~9 T\ r T


L:E.J


.: . . .: 4.1 :64f -
. . . . .- .
- . . . *. .^ . .
- . .7 7 7 -
212 -t


Fig. 2-18. Schematic of lumped passive directional coupler


I rrnur-I









Most of the signal launched into port 1 (Input Port) will arrive at port 3 (Transmit

Port). The rest of the signal launched into port 1 will be coupled by port 2 (Coupling

Port) with its own sampling ratio. A 10 dB Lumped passive Directional Coupler is

designed as an example. Every passive component of the lumped-passive coupler circuits

are calculated using values as shown in Table 2-7.

Table 2-7 Calculation and simulation value for the directional coupler
calculation simulation

Ce(pF) 0.417135973 0.41664

Le(nH) 1.003707673 1.071

Co(pF) 0.400872798 0.41664

2Lo(nH) 4.340589357 4.256

The following procedure is used to layout of each of the lumped-passive circuits.

The layout of the directional coupler is shown in Figure 2-19. As shown in Figure 2-19,

the lumped-passive direction coupler is fully symmetric so each bond path is connected

to two spiral inductors and a MIM capacitor. Six spiral inductors and five MIM

capacitors are located with symmetric structures and each passive component is

connected with a metal line as shown in Figure 2-19. Ideally, these inner metal lines are

used for connection between each passive component and are considered short lines.

Unfortunately, these metal lines have resistance and parasitics that create critical circuit

side effects.

To predict unwanted side effects, every connection metal line was modeled and

considered in simulation.















FYI

iEf -- ---- -:i:
'A'







......... .
4. Mq4


rMIN


Fig. 2-19. The layout of the lumped-passive directional coupler


.I .. 12


'4 ,






N I I
116,


Fig. 2-20. The model of interconnection line

For example, one of the bond pad branches located inside dotted circle in Figure 2-

19 is modeled as shown in Figure 2-20. One single metal structure can be modeled as a










combination of six metal segments. A single metal line on silicon wafers can be modeled

as shown in Figure 2-21 [NikOO]. Each metal line has a series inductance L and series

resistance rx and parasitic capacitance Ci and C2 that exist between the metal structure

and substrate. Also, there exists substrate resistances R1 and R2.


L rx









Ri R2



Fig. 2-21. The equivalent circuit of metal line

All the parasitics in the single metal structure shown in Figure 2-20 are calculated

by the EM simulator ASITIC which is developed by Berkeley and each value is shown in

Table 2-8

Table 2-8 Calculated value of the equivalent circuit for the directional coupler
L R, C' R, C2 R2

1) 23.76p 38.03m 3.592f 4.184k 3.592f 4.184k
20X58.7
2) 33.03p 48.74m 4.261f 4.055k 4.261f 4.055k
20X74.1
@ 21.43p 62.24m 1.737f 4.438k 1.737f 4.438k
6.62X43.5
4 61.31p 78.07m 5.91f 3.791k 5.91f 3.791k
116.22X20
@ 13.31p 24.65m 2.695f 4.375k 2.695f 4.375k
20X39.38
6 20.54p 69.92m 1.703f 4.44k 1.703f 4.44k
40.28X5


Finally, a 10 dB lumped-passive-directional coupler was designed with all the side

effects of the connecting metal lines. Two simulation results are shown in Figure 2-22.










The original simulation result does not consider parasitics of metal connection lines and

the complete simulation result includes all parasitics of metal line connections. As shown

in Figure 2-22, at 5 GHz the original simulation result for the signal magnitude at port3 is

approximately -0.9 dB, and about 80 % of the power will be delivered to port3 (transmit

port). Also, at 5 GHz the original simulation result for the magnitude at port2 is

approximately -12 dB, and about 6 % of the power will be coupled to port2 (coupling

port). The complete simulation results for the magnitude at port3 and port2 are -1.7 dB

and -9.0 dB respectively. The insertion loss (S31) is increased and coupling (S21) is

decreased due to inter-connection loss and parasitics. These unwanted parasitics change

the frequency response of the lumped passive directional coupler.


-5

-10



-20

-25

_0


* Sim_original s21(dB)
S* Sim_originals31(dB)
__- Sim_complete s21(dB)
-- Sim_complete s31(dB)


-w
1 2 3 4 5 6 7 8
Frequency


Fig. 2-22. Simulation results of lumped-passive-directional coupler

A divider has two 900 phase shift branches as shown in Figure 2-23-(a). The signal

launched into the input port will arrive at the output ports with the same magnitude and

phase. A divider is composed of two spiral inductors, four MIM capacitors and one poly-

resistor as shown in Figure 2-23-(b).












o' ZO 90 -
Zo






2 ZO 90 --
Zo


zo


. ... .7 .. .
PCRT1 PRTJ
" A -n-1 7 num=3


: .:
nd :


Fig. 2-23. Schematic of lumped passive divider

The passive components of lumped-passive circuits are calculated using introduced

equation as shown in Table 2-9.


Table 2-9 Calculation and simulation value for divider

calculation simulation

L(nH) 2.2507 2.27

C(pF) 0.4502 0.4575

R(ohm) 100 100


. . . .









The layout of the following directional coupler is shown in Figure 2-24. Passive

components are used for circuit function. Two spiral inductors, a poly resister and four

MIM capacitors are located with symmetric structures and each passive component is

connected with metal lines as shown in Figure 2-24. These metal lines have resistances

and parasitics. These unwanted resistances and parasitics give rise to critical circuit side

effects.























Fig. 2-24. The layout of the lumped-passive the divider

To predict unwanted side effects, connecting metal lines are modeled for a

complete simulation. For example, one of the bond pad branches located inside the dotted

circle in Figure 2-24 is modeled as shown in Figure 2-25. One single metal structure can

be modeled as a combination of these six metal segments. Each metal line has a series

inductance L and series resistance rx. And parasitic capacitance Ci and C2 can model each

metal structure and substrate. Also, there exists substrate resistance in R1 and R2.










Therefore the single metal line on this silicon wafer can be modeled as shown in Figure

2-21 [NikOO].






i jo






=^





Fig. 2-25. The model of interconnection line

All parasitics in the single metal structure as shown in Figure 2-25 are calculated

by EM simulator ASITIC developed by Berkeley and each value is shown in Table 2-10

Table 2-10 Calculated value of the equivalent circuit for the divider
L Rx C, R, C2 R2
() 28.54p 28.37m 6.509f 3.852k 6.509f 3.852k
81.02X43.08
( 9.112p 21.66m 1.934f 4.517k 1.934f 4.517k
28.38X15
(3 62.6p 362.6m 5.674f 4.037k 5.674f 4.037k
101.48X15
(4) 8.571p 10.64m 4.742f 4.054k 4.742f 4.054k
55.13X39.48
5 3.788p 22.62m 787.1a 4.754k 787.1a 4.754k
12.02X4.28
(6 49.98p 45.25m 7.773f 3.699k 7.773f 3.699k
117.32X39.84


Two simulation results are shown in Figure 2-26. The original simulation result

does not consider any metal line parasitics and the complete simulation result includes all

the metal line parasitics. As shown in Figure 2-26, at 5 GHz the original simulation result

for the magnitude at the output ports is approximately -3.8 dB. The phase balance












between output ports is almost 00 throughout the frequency band of 1 to 10 GHz. Further,


up to 5 GHz, the complete simulation result for the magnitude at the output ports is


approximately the same as the original simulation result. At high frequency, frequency


response is altered due in part to parasitic effects especially parasitic capacitances


between the metal structure and the substrate. The phase balance between output ports is


not changed significantly and stays almost 0 throughout the frequency band of 1 to 10


GHz.


-2

-4

-6

--8
m
-10

-12

-14

-16


1 2 3 4 5 6
frequency(GHz)


7 8 9


-100

50 -E- Sim original S31(deg)
-150
-x- Sim_original S32(deg)
-e- Sim_complete S31 (deg)
-200
-4-Sim_complete S32(deg)

-250
1 2 3 4 5 6 7 8 9 10
frquency(GHz)


(b)


Fig. 2-26. Simulation results of a lumped-passive divider


- Sim_original S31(dB)
S -e-Sim_original S32(dB)
-B- Sim_complete S31(dB)
x- Sim_complete S32(dB)










A 1800 hybrid is composed of three 900 phase shift branches and a 2700 phase shift

branch as shown in Figure 2-27.



[(]
\ ( ) 9Zo 90 3

o oZ

rq l rs,
[A] I n)
N N


42 Zo 270 Zo
Z,0 Z0

Fig. 2-27. A ring hybrid (rat-race)

A 90 phase shift branch is composed of a spiral inductor and two MIM capacitors;

while a 2700 phase shift branch is composed of a spiral inductor and two MIM

capacitors. So the hybrid is composed of four spiral inductors and six MIM capacitors as

shown in Figure 2.28.


. . . .
: : ^ ^ ; ;


:tc :Z ::


Fig. 2-28. Schematic of a lumped passive hybrid










A hybrid is designed utilizing lumped passive components is calculated using

values Table 2-11.

Table 2-11 Calculation and simulation value for the hybrid

calculation simulation

L(nH) 2.2507 2.27

C1(pF) 0.904 0.905

C2(pF) 0.4502 0.4575


As shown Figure 2-29, at 5.1 0.7 GHz, the original simulation and complete

simulation results show that the magnitude simulation in output ports is approximately

equal to -4.3 dB. The phase balance between these output ports is almost 1800 at 5.1

0.7 GHz in the original simulation. At high frequency, especially above 6 GHz, transfer

characteristics are degraded due to parallel parasitic capacitance between metal structures

and the substrate.


0 _____________ ____________




-10


-15 -- Sim_original S12(dB)
Sim_original S42(dB)
-- Sim_complete S12(dB)
-20 cSim_complete S42(dB)


-25
1 2 3 4 5 6 7 8 9 10
Frequency(GHz)


(a)

Fig. 2-29. Simulation results of the lumped-passive balun













0





&-200 -_
'--250
-300 -- Sim_original S31(deg)
-350 --x-Sim_original S32(deg) __
-400 -e-Sim_complete S31(deg)
Sim_complete S32(deg)
-450
1 2 3 4 5 6 7 8 9 10
frequency(GHz)


(b)

Fig. 2-29. Continued.

2.5 Fabrication Results of Lumped Passive Devices

A lumped-passive-directional coupler was fabricated with the IBM 0.25 micron

SiGe BiCMOS-6HP technology through MOSIS. The photomicrograph of the directional

coupler is shown in Figure 2-30. The measurement of the directional coupler was

performed by using an on-wafer Cascade Microtech Air Coplanar Probe (ACP) and a

HP8510C Network Analyzer. The total chip size is about 1.2 mm2 (1.0 mm X 1.2 mm).


Fig. 2-30. Die micrograph (1.0mm x 1.2mm) of the lumped-passive-directional coupler









The measured results of the directional coupler are shown in Figure 2-31. The

transmitted power at transmit port is -2.2 dB at 5.0 GHz including coupling loss of -1.1

dB. The coupling power at the coupling port is -9.5 dB. As mentioned before in Figure 2-

31, the simulated transmit power at the transmit port is -1.7 dB at 5.0 GHz and the

simulated coupling power at the coupling port is -9.0 dB. Compared to the previous

simulation, the measurement results show good agreement.




-10




M-1 5
-20 -9- Measurement s31(d B)
2-X- Measurement s21(d B)
-25 -___- Simulation s21(d B)
+ Simulation s31(dB)
-30 I
1 2 3 4 5 6 7 8
Frequency(GHz)

Fig. 2-31. Simulated and measured results of the lumped-passive-directional coupler

The photomicrograph of the divider is shown in Figure 2-32. A lumped-passive-

divider was fabricated with the IBM 0.25 micron SiGe BiCMOS-6HP technology

through MOSIS. The measurement of the directional coupler was performed by using an

on-wafer Cascade Microtech Air Coplanar Probe (ACP) and a HP8510C Network

Analyzer. The total chip size is about 0.8 mm2 (1.0 mm x 0.8 mm).


























Fig. 2-32. Die micrograph (1.0mm x 0.8mm) of the lumped-passive divider

The measured results of the divider are shown in Figure 2-33. The insertion loss is -

4.07 dB at 5 GHz including a signal splitter loss of 3 dB. The ripple is within 0.3 dB up

to 6 GHz. The phase difference between the 2 output ports is within 0.50 throughout the

frequency band of 1 to 10 GHz. The simulated insertion loss is -3.8 dB at 5 GHz and the

phase difference between 2 output ports is 0. The measurement results show good

agreement with the complete simulations.


-2
-4
-6
- -8
-10
-12

-14
-16


5 6
frequency(GHz)


7 8 9


Fig. 2-33. Simulated and measured results of the lumped-passive-divider


-X- Measurement S31(dB)
-9- Measurement S32(dB)
-I- Simulation S31(dB)
-e- Simulation S32(dB)


1 2












0

-5 0 ---_ _ __----------------

S-100
-1 -- Measurement S31(deg) __
-x- Measurement S32(deg)
-200 -Simulation S31(deg) _
-x- Simulation S32(deg)
-250
1 2 3 4 5 6 7 8 9 10
frquency(GHz)


(b)

Fig. 2-33. Continued.

The photomicrograph of the balun is shown in Figure 2-34. A lumped-passive-

balun was fabricated with the IBM 0.25 micron SiGe BiCMOS-6HP technology through

MOSIS. The measurement of the lumped-passive-balun was performed by using an on-

wafer Cascade Microtech Air Coplanar Probe (ACP) and a HP8510C Network Analyzer.

The total chip size is about 1.2 mm2 (1.0 mm x 1.2 mm).


Fig. 2-34. Die micrograph (1.0mm x 1.2mm) of the lumped-passive hybrid










The measured results of the balun are shown in Figure 2-35. At 5 GHz, the

insertion losses of the output ports, port and port4, are -4.41 dB and -4.47 dB

respectively, including the 3 dB signal splitter loss. The magnitude difference between

the 2 output ports is only 0.06 dB at 5 GHz. The phase balance between two output ports

is approximately 1830-1860 at 5.1 0.7 GHz. The simulated insertion losses at 5 GHz

are -3.81 dB at output port and -4.17 dB at output port4, and the phase difference

between 2 output ports is 1800-1830 at 5.1 + 0.7 GHz. Therefore, the measurement

shows good agreement with the simulation.




-5
S0 __ -------------------------------


m
-15 -2- Measurement S12(dB)
-*- Measurement S42(dB)
-20 -e- Simulation S12(dB)
Simulation S42(dB)
-25 --
1 2 3 4 5 6 7 8 9 10
Frequency(GHz)
(a)
0


-100
-150
-200
S.-250
-300 Measurement S31(deg)
-350 ---- Measurement S32(deg) ---
-40 Simulation S31(deg)
--- Simulation S32(deg)
-450 I I i
1 2 3 4 5 6 7 8 9 10
frequency(GHz)
(b)
Fig. 2-35. Simulated and measured results of the lumped-passive-divider









2.6 Conclusion

A lumped-passive directional coupler, lumped-passive divider, and hybrid for

embedded test and differential measurement ofRF ICs have been designed and tested. As

mentioned already, the traditional method to realize these passive circuits uses microstrip

line. Unfortunately, the quarter-wave length of microstrip at 5 GHz is almost 8 mm and is

too big for on-chip realization. Therefore making the lumped-passive circuits is the only

practical option to implement couplers, dividers and baluns on the silicon wafer.

1) The chip size of a lumped-passive directional coupler is 1 mm2 but only 0.45

mm2 core circuit area is required while the commercial directional coupler needs 1500

mm2. To author's knowledge, this is the first attempt to design a miniature on-chip

directional coupler design at 5 GHz. To provide more simulation accuracy, the parasitics

of metal lines for interconnection are modeled and considered for simulation. The

transmitted power at transmit port is -2.2 dB at 5.0 GHz including coupling loss of 1.1

dB. Therefore the insertion loss of the lumped passive directional coupler is 1.1 dB. As

shown in Table 2-2, the proposed insertion loss is lower than 2 dB. Another major

specification is the coupling. The designed coupling ratio is 10 dB at 5 GHz and the

proposed specification is 10 0.5 dB at 5 GHz. The measured coupling power at the

coupling port is -9.5 dB. Therefore the designed lumped passive directional coupler

meets the proposed design specification.

2) Similar to the directional coupler, the chip size of a lumped-passive balun is 1

mm2 but only 0.4 mm2 core circuit area is required. Also this is the first attempt to design

a miniaturized on-chip balun design at 5 GHz. To keep more accuracy in simulation, the

parasitics of metal lines for interconnection are modeled and considered in simulation as









in the directional coupler design. At 5 GHz, the measured insertion losses of the output

ports, port and port4, are 4.41 dB and 4.47 dB respectively, including the 3 dB divider

loss. Therefore, the maximum measured insertion loss is 1.47 dB when the proposed

insertion loss specification maximum is 1.5 dB. The magnitude difference between the 2

output ports is only 0.06 dB at 5 GHz while the specification amplitude difference is

lower than 1.5 dB. The phase balance between the two output ports is approximately

1830-1860 at 5.1 0.7 GHz while the specification phase difference is 180 15.

Therefore the integrated lumped passive balun meets all of the proposed design

specifications.

3) Similar to the directional coupler, the chip size of a lumped-passive balun is 0.8

mm2 but only 0.25 mm2 core circuit area is required. Also, this is the first attempt to

design a miniaturized on-chip divider design at 5 GHz. To keep more accuracy in

simulation, the parasitics of metal lines for interconnection are modeled and considered

for simulation similar to the directional coupler design. At 5 GHz, the measured insertion

losses of the output ports are -4.07 dB including the 3 dB dividing loss. Therefore, the

maximum measured insertion loss is 1.07 dB while the specified maximum insertion loss

is 1.5 dB. The magnitude difference between the 2 output ports is lower than 0.02 dB at 5

GHz while the specified amplitude difference is lower than 1.5 dB. The phase balance

between two output ports is approximately 00 up to 10 GHz while the specified phase

difference is 0 40. Therefore the designed lumped passive balun also meets all of the

proposed design specifications.

Through this research, the lumped passive directional coupler, divider and balun

were designed for embedded RF IC test on-chip or on-wafer and these integrated lumped






45


passive circuits meet all proposed specification. These lumped passive elements proved

useful in a variety of on-chip RF/microwave test systems including embedded loopback

and on-chip s-parameter test system in future chapters.














CHAPTER 3
EMBEDDED LOOPBACK FOR RF ICS TEST

3.1 Introduction

Loopback test is one of the lowest cost test methods for verifying functionality in a

communication circuit. This "go" or "no go" test gives little insight into circuit failure

mechanisms and is of little assistance in debugging a circuit manufacturing process.

Thus, the loopback test is employed in mature product lines where cost is an over-riding

concern [Heu99] [Lup03] or as a final test after other circuit tests. This work assesses the

feasibility of on-chip loopback test for GHz wireless communication ICs. Industry uses

off-chip loopback where transmit signals are routed through a package I/O to a test board

circuit and then back to the receiver of the IC under test. New, on-chip or on-wafer

loopback circuits are designed for verifying performance of 5 GHz wireless WLAN IC

circuits in this research. Although loopback testing is common in mature network

electronics, it has not been applied to on-chip RF systems because 1) there are potential

signal path mismatches, crosstalk and signal leakage problems that adversely affect the

RF/microwave circuit, 2) large amounts of area are consumed, and 3) new on-chip RF

elements are required for implementation. In this dissertation, the author reports on the

test block diagram, the test circuit design and shows test data for loopback test; the key

loopback sub-circuits are microwave attenuators and switches. Simplified transceiver on-

chip loopback circuits have been built and tested. In this dissertation, the performance

and the design are presented. This research is exploratory in nature and is a first attempt

at a new on-chip RF test technique.









3.2 Embedded IC Test for WLAN SoCs

Most wireless communications circuits (including WLAN) consist of three basic

blocks (antenna, RF and IF block, and digital processing/control blocks) which are shown

in Figure 3-1. In this figure, the RF and IF block contains a receiver, transmitter, local

synthesizer, switch and band pass filter.

V RF & IF BLOCK DIGITAL CONTROL BLOCK






Controller Layer
ci- iMiodulator Control
Transmitter --Modulator -Encoder





Fig. 3-1. WLAN block diagram

The receiver module communicates to the digital processing/control block through

a demodulator and the transmitter module receives its input signal from a modulator

connected to the digital block. Current industry practices may utilize separate production

tests for the transmitter and receiver RF and IF blocks and the digital processing/control

block as well as a complete system test. This process can be costly. On-chip loopback

methods potentially raise the test efficiency and lower test cost of the wireless LAN SoC

in a mature design. Low cost tests will be critical for future low cost consumer parts.

Figure 3-2 shows a WLAN block diagram of the loopback test in which the

transmitter signals test the receiver by connecting them to the receiver through RF

switches with an attenuator in the signal path. In many commercial implementations, the









High Power Amplifiers (HPA) are built using different technology

separate from the silicon IC transceiver block.


ANT 1

ANT 2


(GaAs) and are




RX BLOCK






or -
Ting X



TX BLOCK


Fig. 3-2. Block diagram of embedded loopback RFIC test

The HPA connects to the antenna (ANT) through the bandpass filter (BPF). In this

loopback test example, test signals are amplified via a preamplifier (AMP) and switched

to either to the HPA input port or to the loopback attenuator and then the LNA via RF

switches. The LNA requires a weak input signal to verify its performance which is

created by the attenuator in the loopback signal path. For example, the minimum

sensitivity of the wireless LAN is -65 dBm. If the amplifier output as shown in Figure 3-2

is -30 dBm, the input signal at LNA is -64 dBm. This signal is the low enough in strength

to characterize the receiver block: the loopback signal path is shown in the shaded region

of Figure 3-2. In summary, Figure 3-2 shows the necessary circuits for demonstrating the

transceiver RF embedded loopback test signal path; these consist of an AMP

(preamplifier), a RF switch, an attenuator, a second RF switch, and a LNA.









3.3 Design of Loopback Circuit

The key test circuits for implementing embedded loopback test are high-frequency

attenuators which reduce the transmitted signal to sufficiently low test signal values and

RF switches which are used to modify the signal path between test operation and normal

operation. There are various types of RF switches in communication circuits as like

CMOS switches [Hua01], GaAs switches [Gas78], MEMS switches [PodOO], PIN-diode

switches [Cav92], and Ferrite switches [Cru89]. Also, there are various types of

attenuators such MOS active attenuators [Loh91], PIN-diode attenuators [Bae88],

ferromagnetic attenuators [Tra98], thick film attenuators [Yaz91], and coaxial line

attenuators [Cri79]. The resistor-based attenuator [Poz97][Viz95] was selected as the

most suitable for this embedded loopback RFIC test because it has a wideband circuit

operation and compact implementation. Two kinds of resistor-based attenuators are

considered 1) t-type and 2) T-type. Both attenuators are built from three on-chip resistors

in two port networks as shown in Figure 3-3.

R,
zo + --- o zo


V R1 V2


(a) Pi-attenuator
R1 R1
z 0 zo
+ +

Vi R2 V



(b) T-attenuator
Fig. 3-3. The resistor type attenuator









The 7T-type attenuator symmetric resistors R1 are the same value as shown in Figure

3-3-(a). If Zo is the port impedance and a is defined as the attenuation value dB, K is

defined as follows (3.1)(3.2).


K =1020 (3.1)

V R2 + R, // Z
K R2 + (3.2)
V2 R,//Z,

As shown in Figure 3-3-(a), input impedance of the 7t-type attenuator is matched at

the port impedance Zo.

Zo = R //(R2 + R, //Zo) (3.3)

From equation 3.2

R2 +R, //Z, =K(R // Z) (3.4)

If"R2 +R, I/Z" is "K(R //Zo)", then Z, is

1 KR1 Z
Zo =RI//K(RI//Zo)=R R, +// Zo (3.5)
(RI + Z0)

With simple manipulation, Zo is

KR, 2Z
Z = (3.6)
R,2 + R1Zo + KR1Zo

From equation 3.6, R1 is

Zo (K + 1)
R = 1) (3.7)
K is the attenuation as shown in equation 3.1, thus rewrite (3.7) as
K is the attenuation as shown in equation 3.1, thus rewrite (3.7) as









Zo 1010 +1
R1 = + (3.8)
1010 -1


A parallel impedance of R1 and Zo is

RZo
R,//Zo= o (3.9)
R, +Zo

R1 is defined as equation (3.7), thus the equation 3.9 is

(K + l) (K + 1)
RI O (K -1) o (K- 1) Zo(K + 1)
R, //Zo = (3.10)
(K ) (K+1 2K
Z '+Z +1
S(K 1) (K 1)

From equation (3.4) and equation (3.10), R2 is

R2 = (K -1)R//Zo)=(K -1)Z(K 1) (3.11)
2K

R2 z(K2-1) (3.12)
2K

Finally, R2 is

R2 = -(1010 -1)xl0 20 (3.13)
2

The T-type attenuator symmetric resistors R1 are also the same value as shown in

Figure 3-3-(b). IfZo is the port impedance and a is defined as the attenuation value dB, K

is defined as same way as the x-type attenuator.

K-V R, +RR2 //(R, +Zo) ( +3.14)
V2 R2//(R1 + Zo) Z

As shown in Figure 3-3-(b), input impedance of the T-type attenuator is matched at

the port impedance Zo.









Z, = R +R2//(R, + Z) (3.15)

Rewrite the equation (3.15) as

Zo R = R //(R + Zo) (3.16)

From the equation (3.14) and (3.16), K is

K = Z (RI + Z) (RI + Z) (3.17)
(z -R,) Zo (Zo R,)

Thus, R1 is

Zo(K 1)
R, = (K ) (3.18)
(K + 1)

K is the attenuation as shown in equation 3.1, thus rewrite (3.18) as


Zo 1010 -1
R,1 z= (3.19)
1010 +1


From the equation (3.16)

R2Z + R2R
Zo R (3.20)
R +R1 +Z0

Rearrange the equation (3.20) as

Zo2 = R,(2R2 +R1) (3.21)

From the equation (3.18) and (3.21)

Z2 = (K 2R2 +Z(K(3.22)
S(K + 1) a (K + 1)

2K
R2 2 o (3.23)


Finally, R2 is










2Z 1020
2Z 1020 (3.24)
R2 = (3.24)
1010 -1

For up to 30 dB attenuation, both 7-type and T-type can be realized on-chip but the

T-type attenuator fails at greater than 40 dB attenuation. Table 3-1 shows R2 values of the

T-type attenuator should be < 1 0 or less for high attenuation values.

Table 3-1. The resistor values of various attenuators
Pi-type T-type

Attenuation(dB) R2 R1 R2 R1

10 71.15 96.25 35.14 25.97

20 247.50 61.11 10.10 40.91

30 789.78 53.27 3.17 46.93

40 2.5k 51.01 1.00 49.01

50 7.9k 50.32 0.32 49.68

60 25k 50.10 0.10 49.90

70 79k 50.03 0.03 49.97

80 250k 50.01 0.01 49.99

These small resistors are difficult to integrate and easily altered by parasitic

resistances. The tr-type topology is employed in 40 dB, 50 dB, and 60 dB on-chip

attenuator designs. The attenuators are built with the IBM BiCMOS technology P+

polysilicon resistors, (good high frequency response) with the same length and width,

(minimize manufacturing variations). R1 is located symmetrically in the layout along the

axis of R2.

The second key component for the embedded loopback RFIC test is the RF switch:

two SPDT (single-pole double-throw) switches are employed. As shown in Figure 3-4-

(a), the port is the input port, while port2 and port3 are the output ports. Figure 3-4-(b)








shows that a SPDT (single-pole double-throw) switch can be realized by using two on-off

switches.


o Port 2
Port 1 o

SPort 3
(a)
0- --0 Port 2

Port 1

--0 Port 3
(b)
Fig. 3-4. The SPDT (single pole double throw) switches
In good RF design, most of the launched power at switch port 1 will be delivered to

one of the two output ports and a negligible amount is delivered to the other output port.

In this paper, BiCMOS RF switches are constructed from MOSFETs because they prove

useful in monolithic CMOS and BiCMOS SoC solutions, see Figure 3-5. The insertion

loss, the most important specification of the RF switch design, is controlled by the on-

resistance of the MOSFET. For this reason most RF switches, including these, employ

only n-channel MOSFETs. As shown in Figure 3-5-(c), the parasitic capacitance between

source and drain of the MOSFET is a dominant factor in determining the isolation of the

MOSFET. To realize the optimum RF switch, an equivalent circuit is constructed and the

optimum value of each equivalent component is found. To maintain a high frequency

response, optimum length MOSFETs are used [Hua01].









Source Drain

Gate



(a)

On-State
Source On-State Drain

R

(b)

Off-State
Source Drain
C

(c)

Fig. 3-5. N-channel MOSFET model

Typical CMOS RF switches, according to the literature, are built from four n-

channel MOSFET and four resistors as shown in Figure 3-6-a) [Hua01].

Port 1

Port 2 M1 M3 Port 3
0--"---- 40-- --- *--0

SR1 R3
M2 M -\ M4
R4
R2

Cont Port2 Cont Port3


(a)
Fig. 3-6. The schematic of RF switch











Port 1

Port 2 M1 M3 Port 3


R1 R3




0 0
Cont Port2 Cont Port3

(b)
Fig 3-6. Continued.

In these typical switches, the two MOSFETs perform the switching functions and

the additional two MOSFETs increase the isolation. Isolation performance and test circuit

area are traded off. In this application, this test circuit area is more important then its

isolation performance because isolation can be compensated by other methods. For this

reason, the RF switch is composed of two n-channel MOSFETs and two poly resistors as

shown in Figure 3-6-b) in a compact area design.

The parasitic model of M3 in Figure 3-6 is modeled as shown in Figure 3-7. To

connect port to port2, Con_port2 is biased with high voltage and Con_port3 is biased

with low voltage to disconnect port to port3. During this time, there is some power

leakage through the parasitic capacitor Cgs3 of M3 as shown in Figure 3-7. Even though

small amounts of power leaks through the parasitic capacitor Cgs3 of M3, the insertion

loss may be decreased dramatically according to this leakage ratio because the gate of M3

is at low impedance ground. So all leakage signal flows into the low impedance. The

other parasitics are not playing a critical role compared to Cgs3. Maintaining the high

impedance at a gate of M3 is one good method to prevent leakage.







57


M3



Csb3 Cgd3 Cdb3
C Ygd3
Cgs3


R3 C


Cont Port3
SSubstrate


Fig. 3-7. The parasitic model of n-MOS with control resistance

A high resistance value (20 kQ) is used to control resistor R3. By doing this, the

gate impedance is changed from low impedance to high impedance and the effect of the

parasitic capacitor is significantly decreased. This in turn decreases the RF switch

insertion loss by approximately 0.3 dB as shown in Figure 3-8. The CMOS gate length is

the dominant RF switch insertion loss factor so the minimum length (250 nm device gate

length, 400 nm drawn layout gate lengths) is used.

0.00

-0.50

-1.00

S -1.50 --

N -2.00

~ -2.50 -__ __-

-3.00 _
S-*- R=20k
-3.50 R=0

-4.00
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Frequency(GHz)
Fig. 3-8. The simulated results of the RF switch with and without control resistance











As shown in Figure 3-2, the RF switch and RF attenuator are key components for

the loopback test. To realize this test, additional two amplifiers are needed. One is a low

noise amplifier (LNA) and the other is an amplifier (AMP) as shown in Figure 3-2. A

cascode low noise amplifier was designed as the low noise amplifier[Raz98]. The

schematic diagram is shown in Figure 3-9. The transistor size is designed for optimum

gain and noise figure. For input matching, two spiral inductors are used. One is 2.08 nH

and another is 402 pH as shown in Figure 3-9. Similarly, for output matching, one spiral

inductor and one MIM capacitor are used as shown in Figure 3-9.
r--~~~~~~~----------------------
V Vdd
Vdd Output
Matching



121 fF
i --------- k--- ---------------
2k



6.6 pF



---- ---- -- 2 k
2.08 nH
8x
5.0 F


Input 402 pH
Matching




Fig. 3-9. The schematic of the cascode low noise amplifier (LNA)

3.4 Simulation of Loopback Sub-circuits and System

Cadence SpectreS was used to design 5 GHz 30 dB, 40 dB, 50 dB, and 60 dB

lumped passive tr-type attenuators. As shown in Figure 3-10, at 5 GHz the simulation






59


results for the magnitude at port 2 for the 30 dB attenuator is approximately -30.1 dB.

Similarly, the 40 dB attenuator has a -40.3 dB loss at 5 GHz, the 50 dB attenuator has a -

50.1 dB loss at 5 GHz and the 60 dB attenuator has a -62.1 dB loss. This simulation

includes parasitic parameters (capacitances) of the P+ Polysilicon resisters which degrade

high frequency response.

Forward Transmission, dB
-25

-30-

-35



05 u3 05 -45-

C CD CD-55-
-- 0-"


-65-


-70
1 2 3 4 5 6 7 8 9 10


freq, GHz

Fig. 3-10. Simulation result of pi-type attenuator

In these typical switches, the two MOSFETs perform the switching functions and

the additional two MOSFETs increase the isolation. As shown in Figure 3-5-b), the

resistance on on-state is the dominant RF switch insertion loss factor. The gate

impedance can be modeled as shown in Figure 3-11.
























Width


Fig. 3-11. The gate model for optimum insertion loss of RF switch

The gate width can be modeled as a parallel resistor and parasitic capacitor as

shown in Figure 3-11. As the width increases, the resistance becomes lower and the

insertion loss of the RF switch decreases. But simultaneously, the parasitic capacitor

increases. The parasitic capacitors make the insertion loss of the RF switch worse. The

simulation results which sweep the number of fingers in the MOSFET from 60 to 120

with a gate width of 900 nM is shown in Figure 3-12. When the number of finger is

increased, the insertion loss becomes improves up to 84 fingers. If there are more than 84

fingers, the insertion loss becomes worse. So, the 84 fingers are selected for the minimum

insertion loss RF switch. In reality, it is difficult to layout an n-MOSFET with 84 fingers.

For this layout, 84 metal lines are needed for every gate connection. This also causes

unwanted parasitic capacitance. For practical realization of the MOSFET, the finger

number is reduced from 84 to 8 and each gate width is increased from 900 nM to 9400

nM. By doing this, the total gate width can be kept the same.







-4.15
-4.2

-4.25

m -4.3

-4.35

-4.4

-4.45


60 80 100 120
Finger number
Fig. 3-12. Simulated results of gate width (finger number) sweep from 60 to 120 at 5.2
GHz
Similarly, the gate length can be modeled as the series resistance as shown in
Figure 3-11. If the gate length is increased, the resistance is increased also. The
simulation results which sweep the gate length from 400 nM to 1300 nM is shown in
Figure 3-13. If the gate length is decreased, the insertion loss of the RF switch is also
decreased. Finally, the insertion loss becomes minimal when the gate length becomes 400
nM. The simulation results show up to a 400 nM gate length because IBM-6HP 0.25
technology can provide 400 nM as a minimum gate length. For this reason, a minimum
length (250 nm device gate length, 400 nm drawn layout gate length) is used for the RF
switch.


; ` \


-











0

-1

-2

-3

-4

-5

-6
4C


500 600 700 800 900 1000 1100 1200 1300

Gate Length (nM)


Fig. 3-13. Simulated results of gate length sweep from 400 nM to 1300 nM at 5.2 GHz

Two simulations are performed to decide the optimum value of the RF switch. One

is the sweeping gate length as shown in Figure 3-13 and another is the sweeping gate

width as shown in Figure 3-12.


2 3 4 5 6
Frequency (GHz)


7 8 9


Fig. 3-14. Simulated results of the RF switch

Finally, the dimension of n-MOSFET RF switch is decided for optimum value

according to various simulation results. As mentioned early, the minimum gate length is


_ ----- ^ -- ---- ----- ----- ---- ----- ---- ~-- ---



Simulaton (SW-on)
Simulation (SW-off)


..............................


)0









better for insertion loss and increasing the gate width is not always good. The simulated

optimum insertion loss of this n-channel MOSFET is 2 dB when the number of fingers is

8, the gate length is 400 nM, and the layout gate width is 9400 nM as shown in Figure 3-

14.










13 __
1: 6 6' 6
















Fig. 3-15. The schematic of the cascode low noise amplifier with parasitics

The schematic of cascode low noise amplifier with parasitics is shown in Figure 3-

15. Every single metal line connection between transistors is modeled as an equivalent

circuit as shown in Figure 3-22. All parasitics in the single metal plate as shown in Figure

3-15 are calculated by EM simulator ASITIC which was developed by Berkeley and each

value is shown in Table 3-2.







64


Table 3-2. Calculated value of the equivalent circuit for LNA
L(pH) Rx(m) C1,2(fF) R1,2(k)
1 6.79 17.37 0.21 307.3
2 9.17 96.4 0.22 307.5
3 28.38 350.5 1.33 53.69
4 20.62 1323 0.31 215.7
5 2.84 203.4 0.037 1934
6 3.63 175.8 0.356 1930
7 3.63 175.8 0.729 4042
8 9.68 203.9 0.221 308.9
9 9.68 203.9 3.845 0.13
10 10.93 222.5 0.222 308.7
11 141.4 6237 6.978 8.642
12 4.51 139.5 0.05 1339
13 3.87 98.26 0.053 1307
14 2.34 31.88 0.382 173.8
15 14.37 225.8 0.363 177.9
16 22.93 73.23 0.336 109.4
17 25.32 81.85 0.347 108.6
18 19.08 148.8 0.524 106.1


Finally, the simulation result of the low noise amplifier with parasitics is shown in

Figure 3-16. The simulated gain (S21) is 19 dB at 5.2 GHz and reflection at input and

output ports are lower than -15 dB at 5.2 GHz.

20-
15-
10--





m 5
-15- ---






freq, GHz
Fig. 3-16. Simulated results of the low noise amplifier with parasitics










The embedded loopback circuit is modeled with the AMP (preamplifier), the two

RF switches, the attenuator, and the LNA is shown in Figure 3-17.




RF S/W RF S/W
Port1 I Port 2


ATT
AMP LNA

Fig. 3-17. The block diagram of the embedded loopback test model

Similarly, every single metal line used for connection is modeled into equivalent

circuits as shown in Figure 3-22. All parasitics in the single metal plate as shown in

Figure 3-18 are calculated by EM simulator ASITIC, developed by Berkeley, and each

value is shown in Table 3-3.

. . .... . . .. . . . . . . .. . .



LNA 'ATT [
: : : : .. ..........







.0 0 0. .

RF S/WFS/V:
- ---- -RF W..-. ... . .






Fig. 3-18. The block diagram of the embedded loopback test model with parasitics










Table 3-3. Calculated value of the equivalent circuit for embedded loopback


1 78.03 109.3 12.18 910.2m

2 11.08 24.9 0.2749 197.7

3 39.82 65.4 1.263 34.03

4 3.051 41.45 0.0714 901.9

5 3.481 127.7 0.0518 1394

6 39.34 64.8 1.263 34.03

7 66.03 96.49 10.98 480.6m

8 2.709 8.976 0.068 897


As simulated earlier, the low noise amplifier has approximately a 19 dB gain at 5.2

GHz. The initial RF switch has about a 2.0 dB insertion loss at 5.2 GHz. Due to this RF

switch, the total power level gain is 17 dB above the input power. The 30 dB attenuator

has 30 dB attenuation at 5 GHz so the power level lowers to -13 dB below input level at

the attenuator output. This -13 dB signal passes through a second RF switch and another

2.0 dB loss occurs. Finally, this signal is amplified by about by approximately 19 dB at

the LNA so the output power level is about 4 dB loss as shown in Figure 3-19.

Forward Transmission, dB
10
m1 ml
freq=5.200GHz
dB(S(2,1))=4.028


S-10-


-20-


-30- -


-40-1 1.. I 8
3 4 5 6 7 8
freq, GHz
Fig. 3-19. Simulated results of the loopback with parasitics circuit output power level at
port 2


L(pH)


Rx(m)


C1 ,2(fF)


R1,2(k)









3.5 Measured Results of Loopback Sub-circuits and Test System

The 40 dB, 50 dB, and 60 dB RF attenuators were fabricated with the IBM 0.25

micron SiGe BiCMOS-6HP technology through the MOSIS fabrication service. The

measurements of RF attenuators were performed by using an on-wafer Cascade

Microtech Air Coplanar Probe (ACP) and a HP8510C Network Analyzer. The

photomicrograph of the attenuators is shown in Figure 3-20. The total chip size is about

1.2 mm2 (1.2 mm x 1.0 mm).


Fig. 3-20. Die micrograph (1.0mm x 1.2mm) of the RF attenuator and RF switch

The measured results of the attenuators are shown in Figure 3-21. The transmitted

power at port 2 in the 30 dB attenuator is -28.6 dB, in the 40 dB attenuator is -39.7 dB, in










the 50 dB attenuator is -49.2 dB, and in the 60 dB attenuator is -57.5 dB at 100 MHz

respectively and this agrees well with the simulated -30.1 dB, -40.1 dB, -50.1 dB, and -

60.1 dB responses. But at high frequency, the 50 dB and 60 dB attenuators are very

ineffective and show poor agreement with simulation indicating significant substrate

signal leakage that exceeds the 50 dB and 60 dB attenuator transmissions. As shown in

Figure 3-21, the leakage power increases at higher frequencies.


Attenuator

-30

-35



-45 __ -*-40 dB ( Simulation )
S--50 dB ( Simulation )
m-5 --60 dB ( Simulation)
-50 '- .- -e-40 dB( Measurement)
---50 dB ( Measurement)
~60 dB ( Measurement)

-60 .

-65 ---*

-70
1 2 3 4 5 6 7 8 9 10
Frequency (GHz)


Fig. 3-21. Measured results of various pi-type attenuators

As shown in Figure 3-21, RF attenuators are very ineffective at high frequency.

The RF attenuator and silicon substrate can be modeled as shown in Figure 3-22. A

coupling capacitor, Cc is modeled between signal path and substrate. Coupling capacitors

are distributed evenly through the dioxide layer. And silicon substrate can be modeled as

vertical components (Rsub1 and Csubl) and horizontal components (Rsub2 and Csub2). These









vertical and horizontal components are distributed evenly also. A portion of the signal on

the pads and attenuator is coupled through coupling capacitor Cc. This signal propagates

to every direction. Some signals propagate to the bottom plate of a silicon substrate and

others propagate to the side through the silicon substrate. A portion of the signal launched

at Padl propagates to Pad2 through the coupling capacitor Cc, substrate resistor Rsub2,

and substrate capacitor Csub2. If the leakage power through substrate exceeds the

designed attenuation level, the attenuator becomes very ineffective at high frequency.

























Sub-contact

Fig. 3-22. Model of the RF attenuator and substrate

Two layouts are shown in Figure 3-23. Figure 3-23-a) shows the layout of the RF

attenuator without substrate contacts. This has -30 dB attenuation and its measurement

results show in Figure 3-21. As mentioned earlier, there is some signal leakage through a

substrate and this attenuator is very ineffective at high frequency. To prevent the signal









leakage through a substrate, many substrate contacts are used as shown in Figure 3-23-b).

The substrate contacts make a metal wall and block the signal leakage between two signal

ports.


(b) RF attenuator with substrate contacts.

Fig. 3-23. Layout of the RF attenuator with and without substrate contact

The 30 dB RF attenuators without substrate contacts and the 30 dB RF attenuator

with substrate contacts were fabricated with the IBM 0.18 micron SiGe BiCMOS-7WL

technology through the MOSIS fabrication service. The measurement of the 30 dB RF

attenuator was performed by using an on-wafer Cascade Microtech Air Coplanar Probe

(ACP) and a HP8510C Network Analyzer. The photomicrograph of the attenuators is

shown in Figure 3-24. The total chip size is about 1.7 mm2 (1.6 mm x 1.1 mm).




























Fig. 3-24. Die micrograph (1.6mm x 1.1mm) of the RF attenuator and RF switch


Forward Transmission, dB


0r

CrO
00

orr
In 7


0 1 2 3 4 5 6 7 8 9 10
freq. GHz


Fig. 3-25. Measured results of the 30 dB attenuator

The measured results of the attenuators are shown in Figure 3-25. The transmitted

power at port 2 in the 30 dB attenuator with substrate contacts is -29.9 dB at 5 GHz. The

attenuation is very constant and variation is within 0.3 dB up to 10 GHz. It is very

effective and shows good agreement with the simulation when compared to the

measurement result of 30 dB attenuator without substrate contacts.


-25-





-30-

A 30 dB without sub-contacts
o 30 dB with sub-contacts











The RF switch was fabricated with the IBM 0.25 micron SiGe BiCMOS-6HP


technology through the MOSIS fabrication service. The measurement of the RF switch


was performed by using an on-wafer Cascade Microtech Air Coplanar Probe (ACP) and a


HP8510C Network Analyzer. The photomicrograph of the attenuators is shown in Figure


3-20. The total chip size is about 1.2 mm2 (1.2 mm X 1.0 mm).


Switch


0

-10

-20

S-30

-40

-50

-60


-Simulaton (SW-on)
i- Simulation (SW-off)
-Measurement (SW-on)
- Measurement (SW-off)


1 2 3 4 5 6 7 8 9 10
Frequency (GHz)

Fig. 3-26. Measured results of the RF switch

The measured results of the RF switch are shown in Figure 3-26. The transmitted


power at port 2 is -2.4 dB at 5.2 GHz. The leakage power at port 3 is -16 dB. The


simulated transmitted power at port 2 is -2.0 dB at 5.2 GHz and the simulated leakage


power at port 3 is -32 dB. The measurements show good agreement with simulation. The


leakage power at port 3 is higher than simulation. The two MOSFETs and two resistors


that were removed to save switch area result in this high leakage.


The loopback test structure was fabricated with the IBM 0.25 micron SiGe


BiCMOS-6HP technology through the MOSIS fabrication service. The measurement of


the loopback test structure was performed by using an on-wafer Cascade Microtech Air


Coplanar Probe (ACP) and a HP8510C Network Analyzer. The photomicrograph of the







73


overall loopback test IC is shown in Figure 3-27. The total chip size is about 1.6 mm2

(1.85 mm x 0.87 mm).














Fig. 3-27. Die micrograph (1.85mm x 0.87mm) of the embedded loopback test model

The measured results of the embedded loopback test model are shown in Figure 3-

28. The transmitted power at port 2 is 2 dB at 5 GHz. As mentioned before in Figure 3-

19, the simulated transmitted power at port 2 is 4 dB at 5 GHz and the measurements

show good agreement with simulation.


20


-0
-20

-40-

-60 0 Measurement
-60-
V Simulation
-8 0 I 1 1 1 1 I 1 I I I
3 4 5 6 7 8

freq, GHz
Fig. 3-28. Measured results of the embedded loopback test model

3.6 Conclusions

Attenuators, RF switches, Low Noise Amplifier and loopback test circuits have

been designed and characterized for embedded testing of RF ICs. To realize high









performance attenuation at high frequency, a method of reducing leakage through the

substrate is investigated. Making a blocking wall using substrate contacts is shown to be

a good method to reduce the substrate leakage. The measurement results of 30 dB RF

attenuator with substrate contacts show better high frequency performance than the

measurement results of an RF attenuator without substrate contacts. Using this method,

RF attenuator is close to the design specification up to 10 GHz.

Compared with a traditional RF switch, a new test RF switch is realized with half

the area by reducing the design by two transistors as shown in this chapter. The RF

switch was designed for minimum insertion loss using the optimum gate dimension (the

optimum gate width and the minimum gate length). The measurement results showed

good agreement with simulation.

For the experiments with the loopback test, the parasitics of metal lines for

interconnection are modeled and considered in simulation to improve accuracy. There are

closer agreements between the simulation and the measurement results when parasitics

are considered. Through this research, the loopback test method was proposed and

verified for TDD (Time Division Duplex) communication methods up to 5 GHz.

This is the first attempt for embedded loopback test of a wireless communication system.

This proposed loopback was designed with minimum area (0.02 mm2) and can extend the

application frequency as high as the operating frequency of the on-chip RF attenuator and

RF switch. The attenuation value for the loopback signal can be decided according to

each design application.
















CHAPTER 4
ANOTHER EMBEDDED LOOPBACK FOR RF ICS TEST

4.1 Introduction

The loopback test, as proposed in an earlier chapter, is one of the least expensive

test methods for verifying functionality in a communication circuit. However, this "go"

or "no go" test gives little insight into circuit failure mechanisms and is of little assistance

in debugging a circuit manufacturing process. On-chip loopback techniques may prove

attractive when doing bare die tests for ICs in system-in-a-package and when the chip

package introduces parasitics that adversely effect the off-chip short necessary for

loopback test. This can occur with very high frequency transceivers in the > 10 GHz

range.

RX BLOCK

ANT / MIXER


II iAMP + MIXER

I _
S Coupler a
I HPA I BPF AMP



Fig. 4-1. Block diagram of another embedded loopback RFIC test









In a previous chapter, the loopback test named Type 1 was proposed for High

Power Amplifiers (HPA), that was built using a different power amplifier technology

(GaAs) that is separate from the silicon IC transceiver block.

In this chapter, another embedded loopback test named Type 2 will be examined.

As mentioned earlier, the Type 1 test is effective for separated high power amplifier

(HPA) designs using different materials for the HPA design. The biggest difference

between Type 1 and Type 2 is that the later is for single chip design including the HPA in

the same wafer. Designing the whole system function in a single chip is a new design

trend. Figure 4-1 shows a WLAN block diagram of the loopback Type 2 test in which

transmitter signals test the receiver by connecting them to the receiver through RF

switches with an attenuator in the signal path.

The HPA connects to the antenna (ANT) through the RF switch (RF S/W). In this

loopback test example, test signals are amplified via a high power amplifier (HPA) and

most signals are delivered to the antenna input port though a directional coupler and RF

switch. Further, some of the coupled signals are delivered to the loopback attenuator

through a first RF switch and then an LNA via a second RF switch. The LNA requires a

weak input signal created by the attenuator in the loopback signal path. Also, the HPA

power can be monitored via a power detector. The loopback signal path is shown in the

shaded region of Figure 4-1. In summary, Figure 4-1 shows the necessary circuits for

demonstrating the transceiver RF embedded loopback test signal path: these consist of an

HPA (high power amplifier), a directional coupler, a RF switch, an attenuator, a second

RF switch, peak detector, and a LNA.









4.2 Design of Loopback Circuit Type 2

The embedded loopback circuit is modeled with an HPA (high power amplifier), a

directional coupler, a RF switch, an attenuator, a second RF switch, peak detector, and a

LNA as shown in Figure 4-2.





Coupler
Port1 r Port 2


HPA



Power Detector ATT
Port 3 -RF S/W2
___ Port 4
RF SAN 1
LNA


Port 5

Fig. 4-2. The block diagram of embedded loopback test model Type 2

The key test circuits for implementing embedded loopback test Type 2 are high-

frequency attenuators, which reduce the transmitted signal to sufficiently low test signal

values, and RF switches, which are used to modify the signal path between test operation

and normal operation. The resistor-based attenuator [Poz97][Viz95] was selected as the

most suitable for embedded loopback RFIC test because it has wideband circuit operation

and compact implementation. The 30 dB attenuator is designed according to the Table 4-

1.

The second key component for the embedded loopback RFIC test is the RF switch.

Two n-MOSFET and two control resistors are used for the RF switch as shown in Figure

4-6. For optimum size, the minimum gate length 180 nM is used and the gate width is







78


designed as 4.23 uM with 30 fingers. To realize the loopback test Type 2, two additional

amplifiers, a directional coupler and a power detector are needed. One is a low noise

amplifier (LNA) and another is a high power amplifier (HPA) as shown in Figure 4-2. A

cascode low noise amplifier is designed as a low noise amplifier. The schematic diagram

is shown in Figure 4-3. The transistor size is designed for optimum gain and noise figure.

For input matching, two spiral inductors are used: 1.08 nH and 220 pH as shown in

Figure 4-3. Similarly, for output matching, two spiral inductors and three MIM capacitors

are used as shown in Figure 4-3.

Vdd Output
SMatching
1.94 nH
------ 2.40 nH
600 fF
3k 1 9

Bias Network T -99 fF 600 fF




4 Th s o 3.0 pF n a
3k -- --
1.08 nH
1 3x
5 .0 p F - ----------------

220 pH
Input
Matching __


Fig. 4-3. The schematic of cascode low noise amplifier (LNA)

A 10-dB directional coupler [Yoo04] is designed for 5 GHz operation as shown in

Figure 4-4. This 10-dB directional coupler employs six spiral inductors and five

capacitors. Each design value equation is derived in chapter 3.











445 fF 445fF

Port 1 1.08 nH 1.08 nH Port 3
DW_ 111Y7



4.71 nH 420 fF4.71 nH


Port 2 1.08 nH 1.08 nH Port 4
Port 2 Port 4




445 fF 445 fF


Fig. 4-4. The schematic of 10 dB directional coupler

4.3 Simulation of Loopback Sub-circuits and System Type 2

Cadence SpectreS was used to design 5 GHz 30 dB lumped passive 7t-type

attenuators. As shown in Figure 4-5, at 5 GHz the simulation results for the magnitude at

port 2 for the 30 dB attenuator is approximately -30.1 dB. This simulation includes

parasitic parameters (capacitances) of the P+ Polysilicon resisters which degrade high

frequency response.

Finally, the dimension of the n-MOSFET RF switch is decided for optimum value

according to various simulation results. As mentioned earlier, the minimum gate length is

better for insertion loss and increasing the gate width is not always good. The simulated

optimum insertion loss of this n-channel MOSFET is 0.6 dB when the number of fingers

is 30, the gate length is 180 nM, and the layout gate width is 4230 nM as shown in Figure

4-5.








80


Embedded test RFswitch schematic : Apr 5 15:08:46 2004
S-Parameter Response
4 ; $13 dB20
-4001


-500 -0.6 dB















1.000 3.00 5.00C 7 T0 9.00C 11.00
freq ( Hz )
B: (5.801290 632.72m) sope:-51.59880
Fig. 4-5. Simulated results of the R switch'-




'-1















.m .. .
Sam
632.72m sloe: 51.59









II I I


























Fig. 4-6. The schematic of cascode low noise amplifier with parasitics for Type 2











The schematic of this cascode low noise amplifier with parasitics is shown in

Figure 4-6. Every single metal line for connection between transistors is modeled as an

equivalent circuit as shown in Figure 3-22. All parasitics in the single metal line, as

shown in Figure 4-6, are calculated by the EM simulator ASITIC [NikOO] which was

developed by Berkeley and each value is shown in Table 4-1.


Table 4-1. Calculated value of the equivalent circuit for LNA of Type 2
L(pH) Rx(m) C1,2(aF) R1,2(k)
1 5.564 15.59 102.2 512.5
2 11.23 23.03 117.9 510
3 11.49 48.29 83.8 536.6
4 1.334 71.46 8.1 8422
5 4.02 98.8 39.1 1741
6 220.5 132.5
7 2.20 71.12 30.8 2169
8 4.14 90.31 33.6 2055
9 4.32 152 32.8 2066
10 4.80 74.33 74.8 919.9
11 417 44.7
12 5.32 116.9 74.1 916
13 4.05 267 28.1 2229
14 10,590 1.153
15 13,540 0.842
16 1.35 73.44 8.1 8422
17 4.83 112.2 49.9 1357
18 2.20 71.39 18.5 3705
19 4.99 112.5 50.1 1354
20 2.80 52.25 51.8 1327
21 3.76 90.1 50.2 1302
22 416 36.7
23 432 32.9
24 8.30 29.67 86.2 538.8
25 28.42 74.3 1,223 0.565
26 50.07 126.7 867 33.41
27 2.91 12.08 231.4 15.26
28 32.5 748.7






82


Finally, the simulation result of the low noise amplifier with parasitics is shown in

Figure 4-7. The simulated gain (S21) is 16.3 dB at 5.0 GHz and reflection at input and

output ports are lower than -10 dB at 5.0 GHz.

Forward Transmission, dB


3 4 5 6 7
freq, GHz


Fig. 4-7. S-parameter simulation result of the low noise amplifier with parasitics for Type


-30 -25 -20 -15 -10
Pin (dBm)


-5 0 5


Fig. 4-8. Gain simulation result of the low noise amplifier with parasitics for Type 2







83


The schematic of the lumped passive directional coupler with parasitics is shown in

Figure 4-9. Every single metal line for connection between lumped passive components

is modeled into equivalent circuits as shown in Figure 3-22. All parasitics in the single

metal line, as shown in Figure 4-9, are calculated by EM simulator ASITIC which was

developed by Berkeley and each value is shown in Table 4-2.


. .. . . . .... . . .. . . . .

T I
....-. : 1 : -. . T .. ..
....... :......................... . .























1 6.59 29.62 0.12 492.3
.... ... ..



.............

















2 38.9 110.6 2.35 476



4 101.4 143.7 22.64 0.032
Fig. 4-9. The schematic of lumped passive directional coupler with parasitic for Type 20.032
Table 4-2. Calculated value of the equivalent circuit for directional coupler of Type 2
L(pH) Rx(m) CI,2(fF) RI,2(k)

1 6.59 29.62 0.12 492.3

2 38.9 110.6 2.35 476

3 4.94 11.02 1.43 0.683

4 101.4 143.7 22.64 0.032

5 99.64 141.7 22.64 0.032