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A 24-GHz Fully-Integrated CMOS Transmitter with On-Chip Antenna

University of Florida Institutional Repository

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A 24-GHZ FULLY-INTEGRATED CMOS TRANSMITTER WITH ON-CHIP ANTENNA By CHANGHUA CAO A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006

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Copyright 2006 by Changhua Cao

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iii ACKNOWLEDGMENTS I would like to begin by thanking my advi sor, Professor Kenneth K. O, whose constant encouragement and patient guidance provided a clear path for my research. I would also like to thank Dr. Robert M. Fox, Dr. John G. Harris, and Dr. William L. Ditto for helpful suggestions and their time co mmitment in serving on my committee. Much appreciation goes to Defense Advan ced Research Projects Agency (DARPA), Space and Naval Warfare (SPAWAR) Systems Center at San Diego, and Semiconductor Research Corporation (SRC) for funding this work. My special thanks go to Albert Yen at UMC Inc. and Geoff Dawe at Bitwave Semiconductor Inc. for chip fabrication; Eric Schwartz at Agilent Technologies for the meas urement equipments. Thanks also go to Dr. Frederick Martin at Motorola Labs and Dr. Brian A. Floyd at IBM T. J. Watson Center for helpful technical discussions. I have been quite fortunate to have worked with my colleagues in the Node project: Yu Su, Yanping Ding, and Jau-Jr Lin, whose helpful recommendations, discussions and friendship have speeded up my research. I would also like to thank my other former and current colleagues at Univer sity of Florida for their helpful advice. Some of their names are listed here: SeongMo Yim, Dong-Jun Yang, Li Gao, Zhenbiao Li, Xiaoling Guo, Ran Li, Xiuge Yang, Ashok K. Verma, Haifeng Xu, and Chi-Kuang Yu. I am most pleased to acknowledge the love and encouragement of my parents, to whom I dedicate this work.

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iv TABLE OF CONTENTS page ACKNOWLEDGMENTS.................................................................................................iii LIST OF TABLES............................................................................................................vii LIST OF FIGURES.........................................................................................................viii ABSTRACT.....................................................................................................................xi v CHAPTER 1 INTRODUCTION......................................................................................................1 2 RADIO FREQUENCY TRAN SMITTER ARCHITECTURE..................................5 2.1 Introduction.........................................................................................................5 2.2 Two-Steps Transmitter........................................................................................5 2.3 Direction-Conversion Transmitter......................................................................6 2.4 Overview of the Node Transceiver...................................................................8 2.4.1 Radio Frequency Subsystem Specifications............................................8 2.4.2 Radio Frequency Transceiver Architecture..............................................8 3 KEY BLOCKS OF THE TRANSMITTER.............................................................12 3.1 Introduction.......................................................................................................12 3.2 Power Efficient 26-GHz 32:1 Static Frequency Divider..................................12 3.2.1 Circuit Architecture................................................................................12 3.2.2 Experiment Results................................................................................17 3.3 Low Power Wide Bandwidth Constant Envelope Modulator...........................20 3.3.1 Minimum Shift Key and Constant Envelope Modulation......................20 3.3.2 Implementation of Constant Envelope Modulator.................................23 3.3.3 Circuit Description.................................................................................25 3.4 Intermediate Fr equency Amplifier....................................................................27 3.5 Up-Conversion Mixer.......................................................................................27 3.6 High Efficiency Power Amplifier.....................................................................28 3.6.1 Introduction to CMOS Power Amplifier................................................28 3.6.2 Class A, B, AB, and C Power Amplifier................................................30 3.6.3 High Efficiency Class E Power Amplifier.............................................32 3.6.4 Circuit Description.................................................................................35 3.6.5 Mode Locking Technique......................................................................37

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v 3.6.6 Experiment Results................................................................................39 3.6.7 Summary and Conclusions.....................................................................45 3.7 Summary...........................................................................................................46 4 WIRELESS COMMUNICATIONS USING ON-CHIP ANTENNAS...................47 4.1 Review of On-Chip Antennas...........................................................................47 4.1.1 Introduction to On-Chip Antennas.........................................................47 4.1.2 Measured Performance of On-Chip Dipole Antenna.............................48 4.2 Test Transmitter with an On-Chip Antenna......................................................51 4.2.1 Circuit Architecture................................................................................51 4.2.2 Experiment Results................................................................................51 4.3 Fully Integrated Transmitt er with On-Chip Antenna........................................54 4.3.1 Transmitter Chain Overview..................................................................54 4.3.2 Experiment Results and Discussions......................................................56 4.3.3 Up-Link Demonstration Using an On-chip Antenna.............................62 4.4 Improved Transm itter Chain Design.................................................................63 4.4.1 Improved Modulation Scheme...............................................................63 4.4.2 Improved Transmitter Front-End with Notch Filters.............................64 4.5 Fully-Integrated Transceiver.............................................................................66 4.6 Summary...........................................................................................................68 5 MILLIMETER-WAVE VOLTAGE C ONTROLLED OSCILLATORS................69 5.1 Overview of the Millimeter-Wave Oscillators..................................................69 5.2 MOSFET Modeling for Millimeter-Wave Design............................................71 5.2.1 Gate Resistance and Non-Quasi Static Effect........................................71 5.2.2 Unity Gain Frequencies..........................................................................72 5.2.3 MOSFET Radio Frequency Model........................................................74 5.3 MOS Varactor...................................................................................................75 5.3.1 MOS Varactor Structure.........................................................................75 5.3.2 Equivalent Model...................................................................................77 5.3.3 Experiment Results and Discussions......................................................78 5.4 High Performance On-Chip Inductor................................................................81 5.5 Transistor Layout..............................................................................................83 5.6 Circuit Architecture...........................................................................................85 5.7 60-GHz Wide Tuning Oscillators.....................................................................86 5.7.1 Design Considerations............................................................................86 5.7.2 Experiment Results and Discussions......................................................87 5.8 100-GHz Oscillators in 0.13m CMOS..........................................................89 5.8.1 Design Considerations............................................................................89 5.8.2 Millimeter-Wave Spectrum Measurement Setup...................................90 5.8.3 99-GHz Voltage-Controlled Oscillator..................................................92 5.8.4 105-GHz Voltage-Controlled Oscillator................................................94 5.9 Oscillators Operating a bove 100 GHz in 90-nm CMOS..................................95 5.10 192-GHz Push-Push Oscillator........................................................................101 5.10.1 Circuit Design......................................................................................101

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vi 5.10.2 Experiment Results..............................................................................103 5.11 Summary and Discussions..............................................................................105 6 50-GHz CMOS PHASE-LOCKED LOOP............................................................107 6.1 Introduction.....................................................................................................107 6.2 Fundamental of Phase-Locked Loop..............................................................108 6.2.1 Basic Phase-Locked Loop....................................................................108 6.2.2 Phase Frequency Detector and Charge Pump......................................109 6.2.3 Linear Model........................................................................................111 6.2.4 Loop Filter and Frequency Response...................................................113 6.2.5 Phase Noise in the Loop.......................................................................114 6.3 High Frequency Injection-Locked Frequency Divider...................................115 6.4 50-GHz Phase-Locked Loop...........................................................................119 6.4.1 Loop Overview......................................................................................119 6.4.2 Measurement Results.............................................................................120 6.5 Summary.........................................................................................................124 7 SUMMARY AND FUTURE WORK....................................................................127 7.1 Summary.........................................................................................................127 7.2 Suggested Future Work...................................................................................128 APPENDIX A DEFINITION OF ERROR VECTOR MAGNITUDE...........................................130 B DERIVATION OF UNITY POWER GAIN FREQUENCY.................................132 LIST OF REFERENCES................................................................................................136 BIOGRAPHICAL SKETCH..........................................................................................145

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vii LIST OF TABLES Table page 2-1 Link budget of the Node system...........................................................................9 3-1 Power consumption and maximum operat ing frequency for several recently published 2:1 CMOS static frequency dividers....................................................19 3-2 Comparisons of power amplifie rs operating near 20 GHz...................................45 4-1 Summary of the 24-GHz transmitter performance...............................................61 5-1 Summary of the measured VCO performance....................................................100 5-2 Comparison with recently reported hi gh speed fundamental mode VCO’s in silicon technologies.............................................................................................106 6-1 Summary of the PLL Performance.....................................................................125 6-2 Comparison to the previously reported SiGe HBT PLL’s..................................125

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viii LIST OF FIGURES Figure page 1-1 Conceptual Node system.......................................................................................1 1-2 Typical Node device size.......................................................................................2 2-1 Two-step conversion transmitter..............................................................................6 2-2 Direct-conversion transmitter..................................................................................6 2-3 Disturbance of the local os cillator by PA leakage...................................................7 2-4 Direct-conversion transmitters with an offset LO...................................................7 2-5 Block diagram of simplified Node RF subsystem using two-step conversion architecture.............................................................................................................10 2-6 Direct-conversion architecture for Node.............................................................10 3-1 Block diagram of the 2:1 static frequency divider.................................................13 3-2 Schematic of the 2:1 static frequency divider........................................................14 3-3 Oscillation frequencies versus the width of the latch transistors with different PMOS load.............................................................................................................16 3-4 The operating frequencies and power cons umption versus the drive transistor width......................................................................................................................17 3-5 Micrograph of the 32:1 frequency divider.............................................................18 3-6 Measured input sensitivity at different supply voltages........................................18 3-7 Output waveform with 26GHz, 0-dBm input........................................................19 3-8 Block diagram of the MSK modulation.................................................................20 3-9 Signals in the MSK modulation.............................................................................21 3-10 An MSK modulation example and the m odulated signal’s constellation (a) MSK modulation is I-Q modulation with ha lf sinusoidal pulse shaping (b) The modulation generates a consta nt envelope constellation.......................................22

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ix 3-11 Ideal constellation of modulator output.................................................................23 3-12 Simulated power spectra of the modula tor output, standard MSK, and offset QPSK.....................................................................................................................24 3-13 Illustration of how a phasor can be generated from tw o phasors in quadrature....24 3-14 Conceptual schematic of a summing circuit..........................................................25 3-15 Block diagram of the constant envelope phase shift modulator............................26 3-16 Schematic of the phasor combining circuit............................................................27 3-17 Schematic of the IF amplifier................................................................................28 3-18 Schematic of the up conversion mixer...................................................................28 3-19 Simplified schematic of the power amplifier.........................................................30 3-20 Transistor currents for class A, B, and C power amplifiers...................................31 3-21 Class E power amplifier.........................................................................................33 3-22 Simplified class E stage model and its voltage and current waveform..................34 3-23 Class-E power amplifier with im pedance transformation network.......................35 3-24 Schematic of the fully-integra ted CMOS power amplifier....................................36 3-25 Schematic of output stage......................................................................................37 3-26 Small signal model of the common source amplifier............................................38 3-27 Die photograph of the chip containing two single-ended power amplifiers..........40 3-28 PA measurement setup...........................................................................................40 3-29 Output spectrum (a) unlocked, input:-42dBm (b) locked, input: -10dBm. (Losses from the cable and connector have been de-embedded)...........................41 3-30 Output power and current consumption as function of the input power for the 18 GHz power amplifier. (Supply voltage: 1.5 V).................................................42 3-31 PAE and drain efficiencies as a func tion of the input power of the 18-GHz power amplifier (Supply voltage: 1.5 V)...............................................................43 3-32 Output power and PAE as a function of the frequency of the 18-GHz power amplifier. (Supply voltage: 1.5 V).........................................................................43

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x 3-33 Output power and gain as function of the input power for the two power amplifiers...............................................................................................................44 4-1 Photograph of an on-chip antenna.........................................................................48 4-2 Input reflection coefficient of a 3-mm zigzag on-chip antenna.............................49 4-3 Antennas pair measurement environment (lobby).................................................50 4-4 Antenna pair gain vs. distance in th e lab for 3-mm zigzag antennas on a 20 .cm, 670m thick substrate with a 3-m oxide layer. The measurement frequency is 24 GHz [9].........................................................................................50 4-5 Block diagram of the test ch ip with an on-chip antenna........................................51 4-6 Micrograph of the test transmitter with an on-chip antenna..................................52 4-7 Input and output matching of the test transmitter..................................................52 4-8 Output power as function of input power..............................................................53 4-9 Measurement setup of the 5-m wirele ss communication using an on-chip antennas pair..........................................................................................................53 4-10 Received signal using an on-chip antenna located 5 m away................................54 4-11 Transmitter chain architecture...............................................................................55 4-12 Schematic of the RF drivers and power amplifier.................................................55 4-13 Photograph of the fully-integrated tr ansmitter and frequency synthesizer............57 4-14 Power consumption distribution in the transmitter chain......................................58 4-15 Transmitter output power versus frequency..........................................................58 4-16 Measured output power spectra of the transmitter around 24-GHz.......................59 4-17 Masured transmitter output constella tion with a 12-Mb/s data rate......................60 4-18 Measured output power spectrum with 24-GHz span............................................61 4-19 Reception of the signal from a transmitter IC with an on-chip antenna using a 20-dBi gain horn antenn a located 95m away.........................................................62 4-20 Modulator output spectra with di fferent modulation steps per bit.........................63 4-21 Second and third order notch filt ers and their characteristics................................64

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xi 4-22 Improved transmitter RF front-end with notch filters............................................65 4-23 Integrated transmitter and receiver RF front-end with distributed T/R switches..67 4-24 Integration of the frequency synt hesizer, transmitter and receiver........................68 5-1 Equivalent gate resistance model incl uding distributed ploy -silicon resistance and distributed channel resistance.........................................................................72 5-2 Equivalent MOS transistor mode l including the gate resistance...........................72 5-3 Unity current frequency, fT, and unit power gain frequency, fmax, versus gate length......................................................................................................................74 5-4 RF model of an NMOS transistor with intrinsic and extrinsic components..........75 5-5 Top view and cross section of the MOS varactor..................................................76 5-6 Simplified MOS varactor model............................................................................77 5-7 Measured MOS varactor capacitance, seri es resistance and quality factor at 24 GHz for a varactor with 0.64m width, 0.24m length and 20 fingers..............79 5-8 C-V and Q-V characteristics of the MO S varactors with different gate dimensions.............................................................................................................80 5-9 Minimum varactor Q and Cmax/Cmin ratio at 24 GHz as a function of gate length. ............................................................................................................................... .81 5-10 Differential inductor layout....................................................................................82 5-11 Lumped inductor model of differential inductor...................................................82 5-12 Cross-coupled transistor layout..............................................................................83 5-13 Capacitors in the VCO...........................................................................................84 5-14 Schematic of the proposed VCO............................................................................85 5-15 Micrograph of the 60-GHz VCO...........................................................................87 5-16 Output spectrum of the 59-GHz VCO (VDD = 1.5V, Vtune= 1.5V)........................88 5-17 Frequency range of two different VCO’s using different varactor structures.......88 5-18 Phase noise of the two different VCO’ s as function of the tuning voltage............89 5-19 100-GHz VCO measurement setup.......................................................................90

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xii 5-20 Simplified block diagram of measurement setup...................................................91 5-21 Output spectrum of the 99-GHz VCO...................................................................93 5-22 Measured phase noise plot of the 99-GHz VCO...................................................94 5-23 Frequency tuning, current consumption a nd phase noise of the 99-GHz VCO at 1.5 V VDD...............................................................................................................95 5-24 Micrograph of the 105-GHz VCO.........................................................................96 5-25 Output spectrum of the 105-GHz VCO.................................................................96 5-26 Photograph of the 140-GHz VCO..........................................................................97 5-27 Output spectrum of the 140-GHz VCO.................................................................97 5-28 Phase noise plot of the 140-GHz VCO..................................................................98 5-29 Output frequency versus the tuning voltage..........................................................99 5-30 Output frequency versus VDD for the 110-GHz VCO..........................................100 5-31 Schematic of the push-push VCO........................................................................101 5-32 Grounded coplanar waveguide transmission line................................................102 5-33 Micrograph of the 192-GHz push-push VCO......................................................103 5-34 Measured VCO output spectrum.........................................................................105 6-1 Basic phase-locked loop......................................................................................108 6-2 (a) Phase frequency detector block diag ram and PFD input/output waveform with (b) fA > fB, (c) A lagging B...........................................................................109 6-3 PFD transfer function...........................................................................................110 6-4 Charge pump with phase/frequency detector.......................................................110 6-5 Charge-pump PFD PLL block diagram...............................................................111 6-6 Linear model of charge-pump PFD PLL.............................................................112 6-7 Second-order passive loop filter..........................................................................113 6-8 Bode plot of third-order charge pump PLL.........................................................114 6-9 PLL block diagram with noise sources................................................................115

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xiii 6-10 Output phase noise plot of a third order charge pump PLL.................................115 6-11 Simplified model of the injectio n-locked frequency divider...............................116 6-12 Schematic of the ILFD with signal inj ected from the tail current transistor.......117 6-13 Schematic of the injection-locked fre quency divider with the input signal directly injected to the core transistor..................................................................118 6-14 Schematic of the VCO and ILFD in the 50-GHz PLL.........................................119 6-15 Block diagram of the 50-GHz phase-locked loop................................................119 6-16 Micrograph of the 50-GHz PLL..........................................................................120 6-17 Frequency range of VCO and locking range of ILFD.........................................121 6-18 Close-in output spectrum of the PLL...................................................................122 6-19 Phase noise plot of the PLL.................................................................................122 6-20 output spectrum of the PLL with 200-MHz span................................................123 6-21 The PLL settling time is around 40 s for a 4-MHz reference frequency step...123 6-22 The output spectrum of push-push node at 101 GHz..........................................124 A-1 Error vector magnitude and related quantities………………………..…...…..130 B-1 Simplified transistor model……………………………..………………………132 B-2 Calculation of the output im pedance of MOS transistor………………………..133 B-3 Maximum power delivery using complex conjugate termination........................134

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xiv ABSTRACT Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy A 24-GHZ FULLY-INTEGRATED CMOS TRANSMITTER WITH ON-CHIP ANTENNA By Changhua Cao August 2006 Chair: Kenneth K. O Major Department: Electrical and Computer Engineering The ever-increasing demand for low-cost portable devices has motivated the research on high frequency CM OS communication integrated circuits. We designed and implemented a transmitter chain that will be part of a single-chip 24-GHz CMOS radio for sensor network applications. The radio incl udes a RF transceiver, an on-chip antenna, a baseband processor, a sensor, and eventually a battery. The integration of an antenna on the same chip greatly simplifies the package, lowers the device cost to less than $1, and makes the radio easy to use. The transmitter includes a minimum shift key (MSK) modulator, IF amplifiers, an up-conversion mixer, drivers and a power amp lifier. A discrete a pproximation of the MSK using phase interpolati on simplifies the modulator design and lowers the power consumption. A mode locking technique usi ng positive feedback is also proposed to improve the power added efficiency (PAE) of power amplifier to 23.5%. The transmitter chain implemented in the UMC 0.13m CMOS provides 8-dBm output power to a 50

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xv load and 7.7% rms error vector magnitude (EVM) while dissipating 100 mW. The signal transmitted by the chain with an on-chip ante nna was picked up 5 meters away using an on-chip antenna, and 95 meters away usi ng a horn antenna with 20-dBi gain. These demonstrations prove that short-range wire less communications usi ng a single-chip radio with an on-chip antenna are possible. Frequency sources for future millimeter-wave applications are also demonstrated. The transistors, varactors, and inductors ar e optimized to reduce the parasiti c loss and capacitances. The components are used to realize wide tuning range 60-GHz voltagecontrolled oscillators (VCO’s) in UMC 0.13m CMOS and VCO’s around 140 GHz in UMC 90-nm CMOS processes. We also used push-push architecture obtain an operation frequency of 192 GHz in 0.13m CMOS. This is the highest operating frequency for any silicon-based circuit. Our study also showed that the lu mped element approach can be used even for circuits operating well above 100 GHz. A PLL tunable from 45.9 to 50.5 GHz was also implemented in 0.13m CMOS process. The power consumption was reduced to 57 mW by using an LC-oscillato r based injection locked frequency divider (ILFD) while the operating frequency range is increased by tracking the VCO and ILFD self oscillation frequencies. These results indicate the feasibility of implementing millimeter-wave applications using low-cost CMOS technology. With more advanced CMOS processes, it should be possible to extend the frequency to sub-millimeter or THz range.

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1 CHAPTER 1 INTRODUCTION Over the past 10 years, the wireless co mmunication industry ha s grown explosively and radio frequency integrated circuit (RFIC) research has received great attention. Everincreasing demand for monolithic, low-cost and low-power portable devices has motivated much research on a single-chip ra dio [1]. Since the baseband digital signal processors (DSP) are being implemented ex clusively using CMOS technologies, CMOS technology offers highest level of integra tion and lowest cost in volume product. Figure 1-1 Conceptual Node system A Node is a true single-chip radio incorpor ating an on-chip antenna, a transceiver, a digital baseband processor, a sensor, and pot entially even a batte ry. Including of small antennas in an integrated circuit keeps the Node size small, greatly simplifies their use, and eliminates the need for external tran smission line connections and sophisticated packaging, which can radically reduce cost of wireless systems operating above 10 GHz [2]-[4]. Figure 1-1 shows a conceptual diagram of a Node. The size of Node device is R X BATTERY T X PROCESSOR & SENSOR RFCHIP R X BATTERY T X PROCESSOR & SENSOR RFCHIP

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2 limited by the battery. Currently, a version with the size of an m&m (Figure 1-2) is being developed. Figure 1-2 Typical Node device size The version being developed using standa rd CMOS technology costs less than $1, and is capable of wireless transmission and reception at 24 GHz ISM band over short distances. The communication ra nge is typically 1 to 5 meters, and the range can be extended to around 30 meters at the cost of increased transmitted power and battery size. To keep the battery small and thus the over all form factor sma ll, power consumption must be low. This rugged system on a chip coul d be so small that it is practically difficult to be detected, and so inexpe nsive that it can be distribute d in large numbers. Groups of active Nodes can form self-organizing wi reless communication networks. The Node system can be viewed as a modifi ed Zigbee radio operated at 24 GHz. Our study focuses on design and character ization of a 24-GHz fully-integrated CMOS transmitter chain. The primary goal is to integrate all components including the antenna onto a single-chip while achieving low power consumption. The feasibility of implementing circuits for future millimeter-wave radios and sensor networks using CMOS technology are also studied. Size 5A and 10

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3 Chapter 2 reviews the architecture of integrated transmitter chain and discusses their advantages and drawbacks. The two st ep transmitter architecture is used in the Node system, to mitigate the VCO pulling issue in a fully integrated radio. Chapter 3 discusses the design and characte rization of the building blocks in the transmitter chain, including a static frequency divider, an MSK-like modulator, IF amplifiers, an up-conversion mixer, RF dr ivers and a power amplifier. A discrete approximation of the MSK using phase interp olation greatly simp lifies the modulator design. The efficiency of PA is crucial becau se it is the most power hungry block in the transceiver. Since a constant envelope modul ation scheme is used, a high efficiency nonlinear class-E PA is utilized. A mode locking technique using positive feedback is proposed to improve the efficiency of the PA. Chapter 4 presents wireless communi cations using on-chip antennas. The characteristics of on-chip antenna are review ed briefly and an up-converter with an onchip antenna is used to demonstrate the feas ibility of using on-chip antennas pair for 5 meters short range communications. Then, th e fully-integrated transmitter chain is described. The transmitter is first characterized using a 50load. It provides 8-dBm output power and 7.7% rms error vector magnitude (EVM, Appendix A ) while consuming 100-mW power. The signal tran smitted by the transmitter with on-chip antenna has been picked up 95 meters away us ing a horn antenna with 20-dBi gain. This uplink demonstration proves that communi cation between a base station and an integrated circuit with on-c hip antenna over a distance of 100 meters is possible. Chapter 5 describes the design of CMOS millimeter-wave vo ltage controlled oscillators. The high freque ncy characteristics of MOS transistor are discussed. The

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4 transistor, varactor and i nductor designs are optimized to reduce the parasitic capacitances and loss. An investigation of trade-off between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 m result in both good quality factor and tuning ratio in the 0.13m CMOS process. The components were utili zed to realize a wide tuning range 60-GHz VCO as well as oscillators operating above 140-GHz. A push-pus h architecture is utilized to obtain frequency close to 200-GHz. The lump ed element approach can be used even for oscillators operating above 100-GHz and it results in a smaller circuit area. Chapter 6 presents a 50-GHz phase-locke d loop design. This fully integrated PLL manufactured in the 0.13m logic CMOS process is tunable from 45.9 to 50.5 GHz. It consumes less than one-tenth of the power for the SiGe PLL’s us ing static frequency dividers, while achieving comparable phase noise performance. The power consumption is reduced using an LC-oscillator based inj ection locked frequency divider (ILFD). The operating frequency range is increased using a co mbination of an ILFD with an increased input frequency range, and tracking the VCO and ILFD self oscillation frequencies. Finally, this research work is briefly summarized and possible future works are suggested in Chapter 7.

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5 CHAPTER 2 RADIO FREQUENCY TRANSM ITTER ARCHITECTURE 2.1 Introduction Single chip radio implementation requires proper selection of ra dio architecture. A RF transmitter performs modulation, up-conve rsion, and power amplification, with the first two combined in some cases [5]-[7]. Th is chapter reviews the architectures of a RF transmitter with an emphasis on those issues particularly challenging when attempting to integrate all the functionalitie s onto a single chip. Sections 2.2 and 2.3 describe the twosteps and direct-conversion architecture and discuss their advantages and drawbacks. Chapter 2.4 presents the transceiver used in Node system. 2.2 Two-Steps Transmitter Figure 2-1 shows the block diagram of the two-steps transmitter architecture, which is similar to the heterodyne receiver archit ecture. First, the baseband I and Q channels undergo qudrature modulation at intermediate frequency of 1. Then, the result is upconverted to 12 by mixing and bandpass filtering. Th e first bandpass filter suppresses the harmonics of the IF signal, while th e second one removes the unwanted sideband, called image, centered around 12. In a two-step conversion architecture, sin ce quadrature modulation is performed at lower frequencies, I and Q matching is superi or, leading to less cross-talk between the two bit streams. Also, a channel filter may be used at IF to limit the transmitter noise and spurs in adjacent channels. The difficulty in two-steps transmitters is that the bandpass

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6 filter following the second upconversion mixe r must reject the unwanted image signal and LO leakage by a large factor, which could be more difficult when all the components are integrated on a single chip. Figure 2-1 Two-step conversion transmitter 2.3 Direction-Conversion Transmitter If the transmitted carrier fr equency is equal to the lo cal oscillator frequency, the architecture is called “dir ection conversion.” In this case, the modulation and upconversion occur in the same circuit. Figure 2-2 shows the block diagram of a directconversion transmitter. Figure 2-2 Direct-conversion transmitter The direct-conversion transmitter in Figur e 2-2 provides the highest integration level and lowest system cost, however it su ffers from an important drawback called injection pulling, that is, the transmitter local oscillat or is disturbed by the output of cos ct sin ct Baseband I Baseband Q PA Matching Network cos 1t sin 1t I Q PA BPF BPF cos 2t

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7 power amplifier (Figure 2-3). This issue arises because th e PA output is a modulated waveform with high power and a spectrum centered around the LO frequency [7]-[8]. Despite various shielding tec hnique employed to isolate th e VCO, the strong output of PA still corrupts the oscillator spectrum. In Nodes, a PA is integrated along with an antenna in the same chip as an oscillator a nd the PA is turned on and off periodically to save power. This problem is exp ected to be even more severe. Figure 2-3 Disturbance of the lo cal oscillator by PA leakage Figure 2-4 Direct-conversion tran smitters with an offset LO VCO PA N (N=2,4) I Q fVCO=N*fLO VCO PA 2 I Q Phase S p litte r fVCO=2/3*fLO (a) ( b ) BPF VCO I Q PA fLO f

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8 The phenomenon of LO pulling is alleviat ed if the PA output frequencies are sufficient higher or lower than the oscill ator frequency. For a quadrature modulation scheme in Figure 2-2, this can be accomplishe d by offsetting the LO frequency. In Figure 2-4 (a), the output of VCO is first divided by 2. Then, the VCO and divider output are mixed and the result is filtere d. Therefore, the VCO frequency is 2/3 of the LO frequency. In Figure 2-4 (b), the VCO output is divi ded by 2 or 4, and the frequency divider naturally generates quadrature LO signals. 2.4 Overview of the Node Transceiver 2.4.1 Radio Frequency Subsystem Specifications The Node system operates at in the ISM band between 24 and 24.25 GHz. The data rate is 100 kbps. Since a direct sequence spread spectrum (DSSS) technique is used, it leads to 50 or 100 Mega chips per second. To have a low bit e rrors rates (BER) and good tolerance to LO freque ncy drifting, the required Eb/No is larger than 18 dB. Assuming the receiver noise figure (NF) is around 8 dB, the received signal must be larger than -98 dBm. The power gain between a pair of on-chip 3-mm zigzag antennas with 5-meters separation is around -99 dB. To have sufficient link margin, the transmitter output power is required to be higher th an 10 dBm. Table 2-1 summarizes the key specifications of the RF subsystem. The link margin of the system is 9 dB. The antenna pair gain is expected to increase by about 10 dB when the substrate is thinned to ~100 m [9], thus, the link margin can be as high as 19 dB. 2.4.2 Radio Frequency Transceiver Architecture Both the two-steps and direct-conversion tran smitter architecture could be used for the Node system. Because the PA and antenna are integrated on the same chip as the

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9 local oscillator, the VCO pulling issue become s worse. Thus, the two-steps transmitter architecture is easier to implement and its performance requirements are relaxed. Table 2-1 Link budget of the Node system. Frequency Band 24 to 24.25 GHz ISM band TX Output Power 10 dBm Communication Range 5 m Antenna Pair Gain -99 dB Received Power -89 dBm Thermal Noise -174 dBm/Hz Date Rate (100 kb/s) 50 dB SNR 18 dB RX Noise Figure 8 dB Receiver Sensitivity -98 dBm Link Margin 9 dB Figure 2-5 shows the two-step or heterodyne architecture of the RF subsystem. The frequency synthesizer provides a 21.4-GHz LO signal. The intermediate frequency is 2.7 GHz, which is exactly 1/8 of the LO frequency, thus, IF signal could be generated using a frequency divider and only one synthesizer is required. The transmitter includes a multiphase generator (8:1 frequency divider), an MSK-like modulator, IF amplifiers, an upconversion mixer, drivers and a power amplif ier. The 8:1 frequenc y divider generates quadrature signals for the modulator. The seri al baseband digital da ta are directly upconverted to IF by the modulator and the IF I/Q mixers are not needed any more. The signal at IF is amplified and fed into a doubl e-balanced Gilbert cell up-conversion mixer. The RF signal is amplified by a 3-stage driver and fed to a class-E power amplifier (PA). Finally, the PA drives a 3-mm on-chip zigzag dipole antenna. The receiver includes a low noise amp lifier (LNA), a RF-to-IF down-conversion mixer, IF amplifiers, an IF-to-baseband mixe r, an automatic gain control (AGC) unit, a low pass filter (LPF), and an anal og to digital converter (ADC).

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10 Figure 2-5 Block diagram of simplified Node RF subsystem using two-step conversion architecture Figure 2-6 Direct-conversion architecture for Node TIMING RECOVERTY & DEMODULATOR 5 Bit A/D LNA AGC AGC LPF LPF MICROPROCESSOR BIT-TO-CHIP ENCODER PLL AMP PA N N RF I Q Q I TIMING RECOVERTY & DEMODULATOR 5 Bit A/D LNA AMP AGC AGC LPF LPF MICROPROCESSOR BIT-TO-CHIP ENCODER BUFFER PLL MODULATOR 8:1 divider & Muti-Phase BUFFER BUFFER AMP AMP PA TX I Q

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11 The direct conversion architectur e can also be used for the Node system. Both of the architectures in Figure 2-4 could be used. Because it is difficult to design a good phase shifter around 24 GHz, the architecture us ing a frequency divider in Figure 2-4(b) is easier to implement. Therefore, a synthe sizer running around 48 or 96 GHz is required. The feasibility of implementing oscillators a nd a synthesizer at this frequency band will be discussed in Chapter 5 and 6.

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12 CHAPTER 3 KEY BLOCKS OF THE TRANSMITTER 3.1 Introduction As described in Chapter 1, the key requirement for Node is the low power consumption. In the design, each block must c onsume as low current as possible. Another requirement for the transmitter is that the output power must be sufficient high and it must be power sufficient. In this chapter, the design and measurement results of each block of the transmitter are described. A power efficient 26-GHz static frequency divider is presented in Section 3.2. A low power wide bandwidth MSK-like modulator is discussed in Section 3.3. The IF amplifier a nd up conversion mixer ar e described briefly in Section 3.4 and 3.5. Section 3.6 proposes a high efficiency class E power amplifier using the mode locking technique. 3.2 Power Efficient 26-GHz 32:1 Static Frequency Divider 3.2.1 Circuit Architecture High speed frequency dividers are critical in a variety of applications from frequency syntheses in wi reless communications to broadband optical fiber communication systems. As shown in Figure 25, in the transmitter a 21.4 GHz frequency divided-by-8 circuit is require d for I/Q modulation. These app lications require high speed, low power, high sensitivity and monolithic integration. To date, the highest operating frequencies for frequency divider have been achieved with bipolar and III-V technol ogies, though their power consum ptions are high [10], [11].

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13 Compared to the bipolar and III-V divide rs, CMOS ones usually operate at lower frequencies. To increase the operating fre quency at given power consumption, several techniques are used, such as injection lo cking [12], dynamic circuit [13] and improved Miller divider [14]. Compare with them, a st atic one has a much wider operating range and moderate operating frequency and power consumption. CMOS static frequency dividers operating around 20 GHz have been re cently reported [15]-[ 19], but the power consumption is too high (usually hi gher than 25 mW for 25-GHz operation). Figure 3-1 Block diagram of the 2:1 static frequency divider Figure 3-1 shows the block diagram of 2:1 current mode logic (also known as source-coupled logic) static fr equency divider [20]. The divi der is based on the classical master-slave D-type flip-flop in which the i nverted slave outputs are connected to the master inputs. The differential nature reduces the switching noise and provides sufficient noise margin. The divider inputs (CK and CKb) are usually also terminated with 50resistors (not shown) to make the amplitude of input signals more predictable. As shown in Figure 3-2, each master-slave flip-flop is implemented using CML. The master and slave stages consist of an evaluate stage (M1,3,4) and a latch stage (M2,5,6). The current sources in conventional CML latches are omitted [15] for low voltage operation. This causes the total current flowing through the ev aluation and latch stag es to fluctuate in D Db Q Qb D Db Q Qb CK CKb OUT OUTb

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14 time, which may potentially generate la rger switching noise. However, at high frequencies, there is big overl ap when both the evaluation an d latch stages are turned on, which makes the supply current relatively co nstant. Therefore, th e switching noise is limited. That is also verified by the simulation. Figure 3-2 Schematic of the 2: 1 static frequency divider When CK and CKb are equal to the common mode va lue and there is no input clock signal, both the master and slave latches are semi-trans parent, allowing signals to propagate through both the latches. This makes th e circuit work as a ring oscillator. If the delay from the gate to drain of M3 is pd, then the oscillation period is equal to 4 pd. Thus, the circuit oscillates at 1/(4 pd) and the signal at the drain of M3 lags the signal at the gate of M3 by 90. In the small signal model, the propagation delay, pd, is proportional to the RLCL constant at the output node. However, the vo ltage swing in this circuit can be large and the operation of the oscillator becomes nonlinear [21]. This makes RLCL only an approximate estimate and large signal characteristic also need to be considered to estimate the real oscillation frequency. CK CK b CK CK b OUT OUTB M1 M2 M3 M4 M5 M6 M7 M8 Master Slave

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15 Usually, the higher self -oscillation frequency leads to higher operating frequency of divider. Meanwhile, the oscillation frequenc y strongly depends on th e transistors size. Figure 3-3 shows the simulated oscillation freq uency as function of the width of latch transistors (M5,6) for varying widths of PMOS loads (M7,8). In the simulation, the widths of M3,4 are fixed at 5 m and M1,2 are fixed at 8 m. As can be seen, smaller load transistors lead to lower osci llation frequency, because the RL increases with smaller loads. Though the capacitance CL also decreases a little, it decreases slower than the increase of RL. Furthermore, with given load transist ors, wider latch transistors lead to lower frequency. From the simulation, the output voltage swing (OUT, OUTB) increases as the latch transistor size increases, because of the larger negative resistance from the cross-coupled transistors. Meanwhile the ma ximum charge/discharge current is also limited by M1. This leads to the longer charging and discharging time, which in turn results in larger pd and smaller oscillation frequency [22]. Additionally, when the widths of PMOS loads are less than 1.8 m and latch transistors are less than 1 m, the circuit stops oscillating because the PM OS transistors are too small to pull-up sufficiently fast [23]. To lower power consumption, the PMOS loads and latch transistors should be small, while avoiding the regi on where the circuit fails to oscillate. Sufficient voltage swing is also required to drive the subsequent stage. In the final design, the widths of the drive transistors (M3, 4), PMOS loads (M7, 8) and latch transistors (M5, 6) are chosen as 5 m, 2.6 m and 1.6 m, respectiv ely. There is greater fl exibility for sizing input transistors (M1,2). It should be sufficiently larg e that the voltage drop across the transistors is not too high and the gate cap acitance is sufficiently low that the power

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16 consumption for driving their gates is not high. The widths of M1,2 are chosen to be 8 m. For the following four stages, the frequency is lower, thus, smaller transistors are used and the power consumption is much lower than that of the first stage. Figure 3-3 Oscillation frequencies versus the width of the latch transistors with different PMOS load Further, extracting from the layout of di vider, the interconnect capacitance does not change much with different sizes of the tran sistors. Therefore, as the sizes of all the transistors are scaled up, the impact of interconnect parasitic capacitance becomes less important and the self-oscilla tion frequency is increased. Th is, however, also increases the power consumption. Figure 3-4 show s the power consumption, maximum and minimum operating frequencies as f unction of the drive transistor (M1,2) width. In this simulation, for both the master and slave stages, the widths of M1,2, M5,6 and M7,8 are approximately 1.6 times, one third (1.6/5), a nd one half (2.6/5) of the width of M3,4 respectively. As expected, the power consum ption increases almost linearly with the transistor sizes, however, the operating frequenc y levels off when the drive transistor is larger than 5 m. This shows that the choice of 5 m for M3, 4 is almost optimal. 0 4 8 12 16 012345 Width of the latch transistor ( m)Oscillation Frequency (GHz) 1 2 3 4 5 6 7 8 1 Wp=1.2 m 2 Wp=1.5 m 3 Wp=1.8 m 4 Wp=2.2 m 5 Wp=2.6 m 5 Wp=3.0 m 7 Wp=3.5 m 8 Wp=4.0 m

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17 Figure 3-4 The operating frequencies a nd power consumption versus the drive transistor width 3.2.2 Experiment Results To make the measurements easier and more realistic, a 32:1 circ uit consisting of 5 stages of 2:1 divider is implemented. The circuit is fabricated in the UMC 0.13m CMOS logic process with eight-layer copper metallization. The die micrograph of circuit is shown in Figure 3-5. The chip size is 0.38 mm x 0.53 mm, which is mainly determined by the pad frame, while the active area is only about 20 m x 80 m. The divider starts to work at suppl y voltage of 0.53 V with 4.2 GHz maximum operating frequency and only 56 W power consum ption of the first 2:1 stage. This is only ~12 W higher than the divider architect ure specially designed for low voltage and power operation [24]. Figure 3-6 shows the input sensitivity measured at three different supply voltages of 0.7, 1.2 and 1.5 V. The ma ximum operating frequencies are 10, 22.5 and 26 GHz respectively and the power consum ption of the first 2:1 stage is 228 W, 1.86 mW and 3.88 mW, respectively. The power consumption of the whole 32:1 circuit 0 5 10 15 20 25 30 0246810 Width of the drive transistor ( m)Operating frequency (GHz)0 1 2 3 4 5 6Power consumption(mW) fmin fmax Power

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18 including buffers (with high impedance output load) is 551 W 4.68 mW and 8.97 mW, respectively. With 50 output load, the power consump tion is about 1/3 higher due to larger current in the buffers. As can be see n, the first stage consum es about 45% of total power. The output waveform is measured w ith Agilent Infiniium 86100B oscilloscope. Figure 3-7 shows the output waveform with 26 GHz input signal. Since the buffers work at low frequency, the out put is close to square. Figure 3-5 Micrograph of th e 32:1 frequency divider Figure 3-6 Measured input sensitiv ity at different supply voltages -35 -30 -25 -20 -15 -10 -5 0 051015202530 Frequeney (GHz)Input Power (dBm) Vdd=0.7V Vdd=1.2V Vdd=1.5V

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19 Figure 3-7 Output waveform with 26GHz 0-dBm input (Time 500ps/div, voltage 100mV/div, offset -5.1mV, AC coupled, 50 output load, Vdd=1.5V) Table 3-1 summaries the power consumption and the maximum operating frequency for several previously reported 2: 1 CMOS static frequency dividers above 20 GHz. The 3.88-mW power consumption at 26 GHz is much less than those of all the bulk CMOS dividers [16]-[18] and is close to th at of the SOI CMOS frequency divider [19]. Table 3-1 Power consumption and maximum op erating frequency for several recently published 2:1 CMOS static frequency dividers Ref Vdd [V] Power [mW] Input Power [dBm] Max. Freq. [GHz] Technology [16] 1.5 60.9* 9 25 120-nm CMOS [17] 1.5 45* 10 27 120-nm CMOS [18] 1.5 66* 0 18.5 120-nm CMOS 1.0 2.7 -7 25 [19] 1.5 7.66 -7 28.6 120-nm SOI CMOS 1.2 1.86 0 22.5 This work 1.5 3.88 0 26 0.13m CMOS Including the power consumption of output bu ffers, which is about 1/3 of the total power consumption Voltage time

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20 By optimizing the transistors sizes in D-flip-flops, a power efficient and high sensitivity 32:1 static frequency divider in a 0.13m CMOS process is demonstrated. The first 2:1 stage can work up to 26 GHz with only 3.88 mW power consumption at 1.5 V supply. This is the most power efficient bu lk CMOS static frequency divider operating above 20 GHz. 3.3 Low Power Wide Bandwidth Constant Envelope Modulator 3.3.1 Minimum Shift Key and Constant Envelope Modulation Minimum shift key (MSK) modulation can be considered as a special offset quadrature phase shift key (OQPSK), as s hows in Figure 3-8. Like other quadrature modulation schemes, every tw o consecutive bits are impre ssed on quadrature phase of a carrier. Suppose, we use half sinusoids, rather than rectangular pulse s (which is used in OQPSK), to represent the levels that are multip lied by the carrier. More specifically, as shown in Figure 3-9, let us multiply the levels in the upper arm by t1cos and those in the lower arm byt1sin where ) 2 /(1 bT and bT is the data period. Thus, the output of the modulator is t t a t t a t xc m c m sin sin cos cos ) (1 1 1 (3-1) Figure 3-8 Block diagram of the MSK modulation S/P Converter Binary data + T b x(t) cos 1t cos ct sin 1t sin ct + -A B 1 mama

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21 Figure 3-9 Signals in the MSK modulation The resulted output signal of a MSK modulation is cons tant envelope. As a matter of factor, MSK should eventually be viewed as a type of frequency shift key (FSK). The MSK modulation can also be seen in the cons tellation of a phase modulated signal. The signal vector, or phasor, changes its angle according to the transmitted bits while the magnitude of the vector is kept the same. Th is results in a point moving on a constant– radius circle and changing direction from time to time, as illustrated in Figure 3-10, which shows an MSK modulation and its constellation for 8 b it intervals. The baseband I/Q channel data bits are shap ed into sinusoidal pulses a nd respectively modulated onto two carriers with quadrature phases. Then th e resulting signals of the two channels are summed up, and the modulated signal becomes a constant envelope carrier with changing phases. It can be seen that on the resulting constellation the phasor moves on a circle and changes directions based on the I/Q bit patter n. It goes over a quadran t in a bit interval. t A B x(t) ma1 ma1 1 0 1 0 1 0 0 0

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22 In order to simplify the circuit architec ture without significantly compromising the performance of modulator, the possible output states are limited to 16 discrete steps. Therefore, the phase change over any bit inte rval, which corresponds to a quadrant on the constellation, was implemented in a limited num ber of 4 discrete steps. The output of modulator should generate a constellation as shown in Figure 3-11, where the modulated signal moves sequentially on the circle and changes direction only on the I or Q axis points. Theoretically, if infinite steps ar e used, i.e., these steps are continuous, it implements standard MSK modulation [25], [26]. The modulator implements an MSKbased constant envelope phase -shift scheme, so that a hi gh efficiency non-linear power amplifier can be used. Figure 3-10 An MSK modulati on example and the modulated signal’s constellation (a) MSK modulation is I-Q modulation with half sinusoidal pulse shaping (b) The modulation generates a c onstant envelope constellation In order to simplify the circuit architec ture without significantly compromising the performance of modulator, the possible output states are limited to 16 discrete steps. Therefore, the phase change over any bit inte rval, which corresponds to a quadrant on the constellation, was implemented in a limited num ber of 4 discrete steps. The output of modulator should generate a constellation as shown in Figure 3-11, where the modulated (a) (b)

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23 signal moves sequentially on the circle and changes direction only on the I or Q axis points. Theoretically, if infinite steps ar e used, i.e., these steps are continuous, it implements standard MSK modulation, and if one step per quadrant is used, its spectrum is the same as standard offset QPSK [25], [26]. Figure 3-11 Ideal constell ation of modulator output Figure 3-12 shows the simulated output spec trum of this modulator, as well as standard MSK and offset QPSK. Because of the limited steps is used, the modulation sidelobes are higher than those for MSK. In pa rticular, these are at frequency offset equal to multiples of four times the data rate are higher. They are about -26 dB lower than the mainlobe. However, compared to the offset QPSK, these peak sidelobes are lower and occur at higher frequencies. This make s the filtering of the sidelobe easier. 3.3.2 Implementation of Constant Envelope Modulator Figure 3-13 illustrates how, in a particular quadrant, constant envelope and different phases can be gene rated from two quadratures of a carrier. By maneuvering the values of a and b which can be seen as the weights of two quadratures, can be changed while maintaining the constant envelope, r By choosing pairs of quadratures of different phases according to the actual data, th e correct quadrant can be chosen. I Q

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24 Figure 3-12 Simulated power spectra of the modulator output, standard MSK, and offset QPSK Figure 3-13 Illustration of how a phasor can be gene rated from two phasors in quadrature The approach of generating an in-between phasor from two phasors in quadrature can be realized by a phasor combining circuit, or a summing circu it, whose conceptual schematic is presented in Figure 3-14 [25], [26]. In this circ uit, the two input LO signals, V1 and V2, are at carrier frequency and ha ve 90 degree difference in phase, while the a b sin t r cos t -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0123456Frequency offset from carrier (x data rate)Normalized power spectrum density (dB) This work Offset QPSK MSK

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25 values of I1 and I2 determine the weights of the two LO’s. Using the long channel small signal transistor model, V I V g am 1 12 where L W Cox/ (3-2) V I V g bm 2 22 (3-3) From Figure 3-13, V I I b a r ) ( 22 1 2 2 (3-4) To ensure the constant envelope, the summation of I1 and I2 should be constant. The input signal swing must be limited and the longer gate s need to be used, so that, the model is valid. However, to achieve ~2.7 GHz operating frequency, the gate le ngths should also be kept as short as possible. In the final design, the transist or length is chosen as 0.3 m. The input and output voltage swing must also be limited to valid the linear small signal transistor model. Figure 3-14 Conceptual sche matic of a summing circuit 3.3.3 Circuit Description Figure 3-15 shows the block diagram of the modulator. The circuit mainly consists of two 4:1 differential multiplexers, a phasor summing circuit, output buffers, and a logic V1 V2 I1 I2 I1+I2=constant

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26 circuit to control the two 4:1 multiplexers. The logic circuit is not in cluded in Figure 3-15, for the purpose of clarifying the modulator circ uit’s main architecture. The input I/Q data determine the control signals of the multiplexers. The four input quadrature signals are the outputs of an 8:1 sta tic divider similar to that described in Section 3.2 Figure 3-15 Block diagram of the cons tant envelope phase shift modulator Figure 3-16 shows the schematic of the pha sor combing circuit. The size of the summing transistors (M1-4) is 8 m/0.3 m and the load resistor is about 1.6 K The variable currents (I1 and I2 in Figure 3-14) are implemen ted by switching current source (M10-13) to left branch (M1, 2) or right branch (M3, 4). In each period, the value of I1 decreases as 4I0, 3I0, 2I0, and I0, while the value of I2 increases as 0, I0, 2I0, and 3I0. This topology ensures the total curren t of the two branches are always constant. The width of M8, 9 is twice of M5-7, so that they have the same vo ltage drop. The width of switches (M5-9) and current sources are made sufficient large, so the voltage drops across these transistors are not too high, which is important for the low voltage operation. 2:1 2:1 2:1 2:1 2:1 2:1 Buffer Buffer 0 o 90o 180o 270o Summing Circuit Output Buffer CLK DATA CLKd DATAd 4:1 Multi p lexe r 4:1 Multi p lexe r Next State Present State

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27 Figure 3-16 Schematic of th e phasor combining circuit 3.4 Intermediate Frequency Amplifier The IF amplifier is implemented using th e cascode topology. The schematic of the IF amplifier is shown in Figur e 3-17. Two cascode stages ar e used to provide sufficient power gain. The size of the tr ansistors in first stage (M1-4) is 60 m/0.12 m and that of the second stage (M6-9) is 180 m/0.12 m. From simulations, the two stages provide 20 dB power gain, while consum ing 4 mA from 1.5 V supply voltage. The simulated output P1dB is higher than 0 dBm. 3.5 Up-Conversion Mixer Figure 3-18 shows a circuit schematic of the up conversion mixer. A double balanced Gilbert cell active mixer is used to get higher gain and output power. From the measurement results of [27] the gain of mixer is a bout 1 dB and the output P1dB is about 11 dBm, while consuming 4.5 mA from 1.5-V supply voltage. In order to deliver 10 dBm to the antenna, the following RF amplifie rs must provide at 20 dB power gain. Present State Next State out outb A 0 A 0b A 1 A 1b Vdd I0 I0 I0 2I0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 R1 R2

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28 Figure 3-17 Schematic of the IF amplifier Figure 3-18 Schematic of the up conversion mixer 3.6 High Efficiency Power Amplifier 3.6.1 Introduction to CMOS Power Amplifier The power amplifier is the most difficult RF block in the transmitter. The PA is typically the most power-hungry building block, which makes th e PA efficiency crucial. Compared to the transistors in III-V tec hnology, the MOS transist or is slower, which makes it more difficult to get high efficiency especially around 20 GHz. The continuous IFIFLO+ LO+ LOVb RF+ RF Vin Vout Vb Vb Ld1 Ld1 Ld2 Ld2 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10

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29 scaling down of supply voltage due to the lower breakdown voltage of MOS transistors also limits the output power. The efficiency of power amplifier is de fined by two metrics [28], [29]. The drain efficiency, is equal to the power delivered to th e load (usually at the first harmonic) divided by the power drawn from the supply. The power-added efficiency (PAE) is the difference between the input and output power s divided by the supply power. If the PA has a relatively large power gain, the drain e fficiency is equal to PAE. In addition, the output spurs and harmonics of the PA in the Node system must also satisfy the wireless standards and FCC rules. Figure 3-19 shows a simplified schematic of a typical common-source PA. The RF chock (RFC) ideally has no voltage drop, thus, it will not affect the voltage swing at the drain node. The matching network provides bandpass filtering at the fundamental frequency. More importantly, it transforms the 50load to lower impedance. For the common-source configuration, the voltage at the drain node can only swing from 0 to 2VDD, thus the maximum power delivered is VDD2/2RL. By transform the load to a lower value, higher outp ut level can be achieved. It shoul d also be noted that the output stage of PA generally includes only one tran sistor instead of the cascode, because the large current would introduce more loss with more active devices in the signal path [29]. However, for the single-transist or amplifier in Figure 3-19, the gate and drain nodes have anti-phase voltage stresses to the gate oxi de. The gate to drain breakdown is becoming more and more severe limitation in CMOS, b ecause the thinner gate oxide thickness in shorter channel length device. Thus, some circuits [30], [31] have utilized the cascode structure instead of the classi cal topology in Figure 3-19.

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30 Figure 3-19 Simplified schema tic of the power amplifier 3.6.2 Class A, B, AB, and C Power Amplifier The power amplifiers are traditionally categoriz ed by classes: A, B, C, D, E, F, etc. In class A, B, and C power amplifiers, th e output transistor current and voltage waveforms are sinusoidal, and they are simila r to the standard small signal amplifier. However, the signal current in a PA is a subs tantial fraction of the bias level, and one would therefore expect potentially serious distortion. In narrowb and operation, the highQ matching and filtering network solve the di stortion problem, so that, overall linear operation prevails. These PAs are primarily di stinguished by bias c onditions. In a class A amplifier, the transistor opera tes linearly across the full input and output range; in a class B amplifier, the transistor conducts for half of the carrier period, while in a class C amplifier, the transistor is on for less than a ha lf of the cycle. They can also be classified using the conduction angle, Figure 3-20 shows the signal current in these three amplifiers. In a class A power amplifier, if the drain voltage in Figure 3-19 is a sinusoid having a peak-to-peak voltage of approximately 2VDD, then the maximum power delivered to the matching network is equal to VDD 2/( 2 Rin) For the drain voltage to reach 2VDD, the RFC must provide current of VDD/Rin. Since the RFC current is relatively constant, the power Vin Matching/ Filtering Network RFC Rin 50

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31 drawn from the supply equal to VDD 2/Rin. Therefore, the maximum drain efficiency is equal to 50%. Figure 3-20 Transistor currents for cl ass A, B, and C power amplifiers. In a class B power amplifier, since the transistor only c onducts half of the carrier period, the maximum power delivered to the load is only a half of class A amplifier, or VDD 2/( 4 Rin) The average current drawn from VDD is given by 2 / 0 ,) /( sin / 1T in DD in DD avg DDR V t R V T I (3-5) The maximum efficiency is therefore equal to /4 79%. In audio systems, class AB power amplifiers operating between class A a nd B are widely used. In these amplifiers, the transistors conduct slightly more than a half of period. A push-pull configuration makes sure that at least one transistor is on during an entire cycle. The class AB shows good efficiency, high output power as well as good linearity. In a class C stage, the conduction angle, is less than 180o. As decrease, the transistor is on for a smaller fraction of the period, thus dissipati ng less power. For the same reason, however, the power delivered to the load also decreases. If the current drawn by the transistor is assumed to be a pi ece of a sinusoid and the output voltage is a tSignal Current t 0 -1 0.5 2 Signal Current t 0 t Signal Current 0Bias Current ( a ) C la ss A (b) C la ss B (c) C la ss C

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32 sinusoid with a peak voltage equal to VDD, then the efficiency can be calculated as a function of As described in [28], [29], the efficiency is given by ) 2 / cos( 2 / ) 2 / sin( sin 4 1 (3-6) varying from 50% for = 360o (class A) to 79% for = 180o (class B) to 100% for = 0o. Though the class C stage could provide a ma ximum efficiency as high as 100%, the actual power delivered to the load is ) 2 / cos( 1 sin outP (3-7) The quantity drops to zero as the conduction an gle vanishes. For this reason, a true class C power amplifier is not suitable to some por table transceivers, where the output power is also a great concern. 3.6.3 High Efficiency Class E Power Amplifier The main premise in class A, B and C amp lifiers has been that output voltage and current waveforms are sinusoid (or a section of a sinusoid), thus limiting the efficiency of the class A and B and the output power of cl ass C [28]. In these amplifiers, the output matching network is designed with the assumpti on that the transistor operates as a current source. While in class D, E and F stages [32] [33], the transistor operates as an ideal switch, rather than a voltage-controlled curren t source. They are nonlin ear amplifiers that achieve efficiencies approaching 100% while delivering full power. Figure 3-21 shows a schematic of a class E pow er amplifier [32]. It consists of an output transistor M1, a grounded capacitor C1, and a series network C2 and L1. The RFC has high impedance at the frequency of operation and C1 includes the drain junction capacitance of M1. To ensure 100% power efficiency, the power consumption of the

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33 transistor M1 must be zero, i.e. the drain voltage VX and transistor current ID1 cannot be non-zero at the same time. Th erefore, the values of C1, C2, L1, and RL are chosen such that the drain voltage of M1, VX, satisfies three conditions [32]: (1) As the switch turns off, VX remains low long enough for the current to drop to zero. (2) VX reaches zero just before the switch turns on. (3) dVX/dt is also near zero when the switch turns on. Figure 3-21 Class E power amplifier Figure 3-22 shows the simplified model of th e class E stage. The transistor can be modeled as a switch with small resistance. When the switch is on, a near linearly increasing current is built up through the i nductor. As the turn-on resistance of the transistor is nearly zero, the voltage drop across the transistor is nearly zero and there is no power consumption. At the moment the switch is turned off, this current is steered into the capacitor, causing the voltage across the swit ch to rise. The tuned network is designed such that in steady state, VX returns to zero with a zero slope, immediately before the switch is turned on. The bandpass filter th en selectively passes the fundamental component to the load, creat ing a sinusoidal output. From [32], the value of the inductor a nd capacitors can be chosen as follows: Vin RFC RL M1 C1 L1 C2 VX

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34 QR L (3-8) R R C 447 5 1 ) 2 / )( 1 ( 12 1 (3-9) ) 08 2 42 1 1 ( 1 ) 08 2 42 1 1 )( 447 5 (1 2 Q QR Q Q C C (3-10) The Q should be as high as possible while satisfying the band width requirement. Once the Q is chosen, the PA can be designe d in a straightforward manner, using the equations given. Figure 3-22 Simplified class E stage mode l and its voltage and current waveform However, an ideal RFC and switch is not available in integrated circuits. A technique using the rela tive low Q on-chip inductors and sl ow transistor is described in [34]. A real class E power amp lifier also includes an impeda nce transferring network [32], as shown in Figure 3-23. The two series indu ctors are also usually merged as one. It should also be noted that 100% efficiency is never possible because the transistor and matching network always have loss. The non-zero turned-on resistance and non-zero switch time limits the efficiency. The transist or is further away from an ideal switch Vin RFC RL ron Vin Vd Ids t t t

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35 when the operating frequency is higher. In a practical circuit, PAE of 40-50% is usually expected. Figure 3-23 Class-E power amplifier w ith impedance transformation network A drawback of class E power amplifier is the large peak voltage that the switch sustains in the off state, which is about 3.56 VDD in an ideal case, which demands high transistor breakdown voltage. However, in real case, especially at hi gher frequencies, the transistor is not a perfect switch, thus th e maximum drain voltage is lower than the theoretical value. Compared with linear power amplifiers, which are usually optimized for maximum gain and linearity, the switching class-E power amplifiers provide much higher efficiency. They are particularly well suited for m odern communication systems using a constant envelope modulation, such as the Zigbee wi reless personal area networks (WPAN'S) and GSM cellular networks, as well as the constant envelope MSK-like modulation used in the Node. 3.6.4 Circuit Description Figure 3-24 shows the schematic of fu lly-integrated CMOS power amplifier designed using the UMC 0.13m process. It consists of a two-stage cascode amplifier, a common source driver, and an output stage. Due to the limited voltage headroom, Vin RFC 50 M1 C1 L1 C2 RL

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36 common-source amplifiers are used in the last two stages. The sizes of transistors in these four stages are 14, 24, 40, and 100 m, respectively. The cascode amplifiers are used to provide sufficient gain, good input matching and isolation from the last two stages which potentially could oscillate. Figure 3-24 Schematic of the fully -integrated CMOS power amplifier Figure 3-25 shows the schematic of th e output stage. The matching network components, L1, L2, C1, and C2, have to be properly selected as described above. The shunt capacitor at the drain of the transistor is omitted because the capacitance from the drain of the transistor is already large enough. To lower the matching network loss, the inductors L1 and L2 are formed with the top two copper layers, which results an effective thickness of 1.6 m. The metal traces are 3.6m wide and 4m above the polysilicon patterned ground shield. The effective series resistance of two inductors is about 5 The shunt capacitor C2 transfers the 50 load to around 40 at 20 GHz. In the layout, C2 is formed by absorbing the pad capacitance (~48 fF) and shunt parasitic of the C1 (~32 fF). A shunt inductor (Lg) is placed at the gate of output transistor to tune out the gate Vb2 Vb3 Vb4 M1 M2 M4 M3 M5 M6 IN 10pF 10pF Lg3 VDD1 VDD2 VDD3 Driver Stage Output Stage OUT

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37 capacitance, which reduces the value of the coupling capacitor, but as will be discussed below, also makes the circuit more potentially unstable. Figure 3-25 Schematic of output stage 3.6.5 Mode Locking Technique Near 20 GHz, the common source driver stag e is potentially unstable due to the feedback through Cgd, which is one of the reasons of the wide use of cascode amplifiers. Figure 3-26 shows the simplified small signa l model of the common-source amplifier, which includes a transconductor and two resonant networks connected by Cgd. Due to Cgd, the output of the amplifier is fed back to the input. The open loop gain of this circuit can be written as, ) /( 1 1 // ) (gd g g gd g d msC Z Z sC Z Z g s T (3-11) This expression consists of two parts: the gain from the gate to drain and voltage divider for the feedback path. To start oscillation, the loop gain s hould be larger than 1 and the phase change must be 360 degree. For the ne twork at the gate node, below its resonant Vb4 M6 IN 50 RL=40j 20 L1 0.55nH C1 125fF L2 0.6nH C2 80fF 100/0.12 Lg 0.24nH 100fF 10pF

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38 frequency, the network is inducti ve with an equivalent inductor Lg,equ and a series resistor Rg,Eq. The transfer function of voltage divider between Cgd and the network is equ g gd gd equ g equ g gd gd equ g gd equ g equ g equ g equ g gd g gR C j C L R C j C L C j R L j R L j sC Z Z, 2 , 2 , ,1 ) /( 1 ) /( 1 (3-12) When Lg,equ>>Rg,equ or Q is high, at frequencies below gd equ gC L,/ 1, this voltage divider provides a pha se shift close to 180o. Meanwhile, when Lg,equ<
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39 cascode amplifiers are used at the input. Th e gates of the common-gate transistors are connected to a bypass capacitor right beside the transistors to make the cascode stage stable. The instability is generally not desirable in power amplifiers. However, if the selfoscillation can be locked by the input, the in stability actually incr eases the gain of the circuit and reduces the drive requirement for switching the output transistor. This is called mode-locking (also known as injection-lo cking) and has been previously utilized in power amplifiers [35], [36] Usually, cross-coupled transi stors are used to provide the positive feedback (or negative resistance). Sinc e the driver in this work is unstable, additional positive feedback is not included. To study the benefits of mode-locking, a power amplifier without mode-locking is al so implemented. This is accomplished by removing the gate inductor of the driver stage (Lg3 in Figure 3-24). In addition, a 3-k resistor is added for dc biasing. 3.6.6 Experiment Results The power amplifier was fabricated in the UMC 0.13m logic CMOS process with eight copper layers and a substrate resistivity of 20 .cm. Another PA without using mode locking is fabricated for comparison. Figure 3-27 shows the die photograph of the two single-ended power amplifiers. The two am plifiers together occupy an area of 0.92 mm x 0.85 mm including bond pads. The large signal measurements were perf ormed using the setup shown in Figure 3-28. The output is connected to a powe r meter with an HP8485A 50MHz-26.5GHz power sensor. The losses of measuremen t setup are de-embedded using a thrumeasurement. The loss at the output end (from the probe and short SMA cable) of ~0.7

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40 dB at 18 GHz was measured with a network analyzer. An Agilent E4448A 50-GHz spectrum analyzer is also used to monitor the output spectrum of power amplifier. Figure 3-27 Die photograph of the chip contai ning two single-ended power amplifiers Figure 3-28 PA measurement setup With 1.5-V supply voltage and proper gate bias (0.5~0.7 V), the power amplifier shows self-oscillation with ~1-dBm peak pow er near 17.4 GHz. The self-oscillation is lower than designed frequency of 20 GHz proba bly because the gate to drain capacitance (Cgd) is larger than expected. As the input signal level applie d at the ‘IN’ node in Figure 3-24 is increased, the self-oscillation becomes weaker until finally the circuit is forced to VDD1 Vb2 GND VDD2 Vb3 VDD3 VDD1 Vb2 GND VDD2 Vb4 VDD3 GND GND IN IN GND GND OUT OUT Stable PA PA w/ mode locking Cascode Amplifiers Driver Output Stage Agilent E8254A Signal Generator 3 feet 3.5mm-cable DUT DC supply DC supply 3.5 inches SMA-cable HP 8485A HP 437B Power Sensor Power Meter RF Probe RF Probe

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41 oscillate at the same freque ncy as the input. Figure 3-29 shows the output spectrum with 17.6 GHz input. With -42-dBm input power leve l, the self-oscillati on cannot be locked, and the self-oscillation peak and inter-modulation products are shown beside the main peak. At -36-dBm input power, the circuit lock s to the input signal. Figure 3-29(b) shows that the output power is more than 10dBm wh en input power is -10dBm. When the input frequency is farther away from the self-osc illation frequency, the circuit becomes more Figure 3-29 Output spectrum (a) unlocke d, input:-42dBm (b) locked, input: -10dBm. (Losses from the cable and connector have been de-embedded) Ref 20dBm Norm Log 10 dB/ LgAv V1 S2 S3 FC A AA £ ( f ): FTun Swp Center 17.505 GHz Span 2 GHz #Res BW 3 MHz VBW 3 MHz #Sweep 100ms (601pts) Center 17.505 GHz Span 2 GHz #Res BW 3 MHz VBW 3 MHz #Swee p 100ms ( 601 p ts ) Ref 20dBm Norm Log 10 dB/ LgAv V1 S2 S3 FC A AA £ ( f ): FTun Swp (a) Input Frequency Self Oscillation Inter Modulation Inter Modulation (b) 10.67 dBm

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42 difficult to be locked. At -10dBm input power level, the circuit can be locked from 15.5 to 21.4 GHz. In addition, when a 20-GHz -10-dBm FM signal with 16-MHz maximum frequency deviation and 1 kbps to 1 Mbps data rate is used as input, the PA locked to the input, while preserving the shape of spectrum. A drawback of the circuit is that the minimum output power level is above 2 dBm wh en the PA is locked. If an output level below this is desired, the bias voltage can be lowered, maki ng the oscillator easier to lock or stop the oscillation. The self-oscillation di sappears when the gate bias of the driver stage is below 0.45 V. Figure 3-30 Output power and current consum ption as function of the input power for the 18 GHz power amplifier. (Supply voltage: 1.5 V) Figure 3-30 shows the output power and cu rrent consumption as function of the input power for the PA with mode-locking. At 18 GHz, with -5-dBm input power, a single-ended output power of 10.9 dBm is obt ained while drawing 35 mA from a 1.5-V supply. The maximum power added efficiency including all the amplif iers and driver is 23.5% (Figure 3-31). Because all the four stages are integrated together, the power at the 2 4 6 8 10 12-35-30-25-20-15-10-50 Input Power (dBm)Output Power (dBm)20 25 30 35 40 45Current Consumption (mA) Pout (dBm) I (mA)

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43 gate of the last stage cannot be measured. Here the current consumptions of all stages are included in the calculation of the PAE. Th e last stage consumes 22 mA and drain Figure 3-31 PAE and drain efficiencies as a function of the input power of the 18-GHz power amplifier (Suppl y voltage: 1.5 V) Figure 3-32 Output power and PAE as a func tion of the frequency of the 18-GHz power amplifier. (Supply voltage: 1.5 V) 4 5 6 7 8 9 10 11 12 1516171819202122 Frequency (GHz)Output Power (dBm)10% 15% 20% 25% 30%PAE (%) Output Power PAE (including drivers) 0% 5% 10% 15% 20% 25% 30% 35% 40% -35-30-25-20-15-10-50 Input Power (dBm)Efficiency (%) PAE(including drivers) Drain efficiency

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44 Figure 3-33 Output power and gain as func tion of the input power for the two power amplifiers. efficiency of the last stag e is about 38%. Further incr ease the input power leads to slightly higher output, but larger current consumption a nd lower efficiency. At 1.2 V supply, the PA provides 7.5-dBm saturate d output power and 18.6% maximum PAE, -25 -20 -15 -10 -5 0 5 10 15 -50-40-30-20-100 Input Power (dBm)Output Power (dBm) PA w/ mode locking (18 GHz) PA w/o mode locking (20 GHz) 10 15 20 25 30 35 40 -50-40-30-20-100 Input Power (dBm)Gain (dB) PA w/ mode locking (18 GHz) PA w/o mode locking (20 GHz) ( a ) ( b )

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45 while drawing 24.5 mA current. Figure 3-32 shows the saturated output power and PAE from 15.5 to 23 GHz at 1.5 V supply. The PA with mode-locking pr ovides more than 8dBm saturated output power over a 5-GHz band. The result for the PA without mode-locki ng is compared in Figure 3-33. This PA achieves 10.2 dBm peak output power and 20. 5% maximum PAE at 20 GHz. Because the gain is lower, it requires 6-8 dB higher input power to get th e same output level. The use of mode-locking technique leads to slightly la rger saturated output power and efficiency. More importantly, it reduces the input pow er requirement of class-E amplifier. 3.6.7 Summary and Conclusions An 18-GHz 10.9-dBm class-E power am plifier with 23.5% maximum PAE is demonstrated in the UMC 0.13m CMOS technology. The mode -locking technique is used to force the oscillating driver to follo w the input signal. The performance of power amplifier in this work is compared to that of the previously reported power amplifiers operating near 20 GHz in Table 3-2. The PA presented in this work shows significantly higher efficiency and lower input requirement than that for the previously reported CMOS PA operating near 20 GHz. This work suggests CMOS technology is a viable candidate for building a fully-integra ted transmitter operating near 20 GHz. Table 3-2 Comparisons of power am plifiers operating near 20 GHz Ref. Freq. [GHz] Vdd [V] Small Signal Gain [dB] Pout [dBm] Output PAE Technology 18 1.5 34 10.9 Single-ended 23.5% 0.13m CMOS This work 20 1.5 26 10.2 Single-ended 20.5% 0.13m CMOS [31] 24 2.8 7 14.5 Single-ended ~6% 0.18m CMOS [37] 24 N/A N/A 18 Differential 26% 0.13m GaAs

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46 3.7 Summary In this chapter, the key RF blocks of the transmitter implemented in the UMC 0.13m CMOS technology were presented. These blocks were a quardrature generator (frequency divider), a constant envelope m odulator, an IF amplif ier, an up-conversion mixer, and a high efficiency power amplifier. A complete transmitter chain could be built by integrating these blocks.

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47 CHAPTER 4 WIRELESS COMMUNICATIONS USING ON-CHIP ANTENNAS 4.1 Review of On-Chip Antennas 4.1.1 Introduction to On-Chip Antennas The research on antennas fabricated on se mi-conducting substrates dates back to late 1980’s [38]. An on-chip antenna integrated with a 95 -GHz IMPATT diode oscillator on a high resistively silicon substrate and an on-chip antenna integr ated with a 43.4-GHz IMPATT diode oscillator on a GaAs substrate [39] have been reported in 1986 and 1988, respectively. High resistivity silicon substrates have also been used to fabricate MEMS based antennas operating at 90 to 802 GHz [40] However, use of IMPATT diode circuits limits the types of radios that can be built. Furthermore, the substrates are not compatible with the low cost mainstream silicon process technologies. For on-chip antennas, the antenna size is limited by the size of th e chip. Therefore, to achieve usable antenna efficiency while limiting the physical size of the antenna requires operation at higher frequencies (e.g ., > 15 GHz), with corresponding to smaller wavelengths. As discussed in the preceding chapters, the speed im provement of silicon devices has made implementation of silicon integrated circuits operating at 20 GHz and higher feasible. At 24-GHz, a quarter wave di pole antenna needs to be only 3.2 and ~1.5 mm in free space and silicon, respectively, ma king integration of an antenna for wireless communication possible. An on-chip antenna could potentially be us ed to relieve the bottleneck associated with global signal distribution inside integrat ed circuits. The first proposed uses of on-

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48 chip antenna fabricated in conventional f oundry process are clock distribution [41] and data communication [41], [42]. Clock transmitter and receiver with on-chip antennas for intra-chip [42]-[45] and inte r-chip [46] wireless connecti on have been demonstrated. Using one of the clock receivers, a 14.3GHz 20-dBm signal from a 2-mm long zigzag dipole transmitting antenna 40 cm away has be en successfully picked up [44]. An 18GHz clock transceiver circuits with star t-up initialization and programmable delays successfully demonstrated the wireless clock distribution using an on-chip antenna pair [45]. A signal from a transmitter incorpor ating a 10-GHz VCO, buffer and antenna fabricated in a BiCMOS technology [47] has also been picked up by an external horn antenna. These suggest the potential to communicate over free space using CMOS and BiCMOS radios with on-chip antennas. 4.1.2 Measured Performance of On-Chip Dipole Antenna Figure 4-1 shows a micrograph of an on-ch ip antenna. The antenna is a 3-mm long zigzag dipole with a bend angle of 30 similar to that reported in [3], [9]. Compare to a linear dipole antenna, the zi gzag one possesses higher effi ciency [48]. The 3-mm length corresponds to around /4 in free space at 24 GHz. The antenna is formed by shunting all eight metal layers. The metal width is 24 m. Figure 4-2 shows the input refection coefficient, |S11|, of the on-chip antenna between 20 and 26 GHz. |S11| is below -10 dB over this frequency range. The measured input impedance is 23 75 j at 24 GHz. Figure 4-1 Photograph of an on-chip antenna 3 mm 120 m

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49 Figure 4-2 Input reflecti on coefficient of a 3-mm zigzag on-chip antenna The power gain of an on-chip antennas pair is measured in real environments using mobile probe stations [9]. Figure 4-3 s hows a measurement environment. A signal generator provides a 24-GHz signal to the tran smitting on-chip antenna and the signal is picked up using another on-chip antenna at different locatio ns. The received signal power level is measured using a spectrum analyzer By de-embedding the cable and probe loss, the power gain of an antenna pairs can be obtained. Figure 4-4 shows the measured antenna pair gain in the lobby as a function of the distance with diffe rent height to the ground. The antenna pair gain, Ga, for the 5 meters separa tion is between –93 and –104 dB, depending on the height to the ground. By using the Friis transmission eq uation, the free space path loss is r t t rG G R P P24 (4-1) where is the wavelength in free space, R is the distance between an antenna pair, and Gt and Gr are the transmitting and receiving antenna gains. If isotropic antennas with unity -20 -16 -12 -8 -4 0 20212223242526Frequency (GHz) |S11| (dB) Zin = 75 – j 23

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50 gain are used, the path loss at 24 GHz can be calculated as -74 dB with 5-m spacing. Therefore, the power gain of the on-chip antenna s pair is -30 to -20 dB lower, or each of the on-chip antenna’s gain is between -15 and -10 dBi in the lobby environment. This lower power gain is mainly due to the lossy silicon. Referring back to system link budget in Table 2-1, the on-chip antenna despite the loss associated with the conductive substrate should be sufficient for the Node applicati on with –98-dBm sensitivity [3], [9]. The antennas pair gain is increased by about 10 dB when the substrate is thinned to from 700 m to 100 m [9]. Figure 4-3 Antennas pair measurement environment (lobby) Figure 4-4 Antenna pair gain vs. distance in the lab for 3-mm zigzag antennas on a 20 .cm, 670m thick substrate with a 3-m oxide layer. The measurement frequency is 24 GHz [9]. 0.11.010.0100.0 Distance (m) -120.0 -100.0 -80.0 -60.0 -40.0Ga (dB) Therotical value 52 cm height 85 cm height 4.5 cm height

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51 4.2 Test Transmitter with an On-Chip Antenna 4.2.1 Circuit Architecture In order to demonstrate the feasibility of using an on-chip antenna for wireless communications, a test transmitter was fabric ated and tested. Figure 4-5 shows a block diagram of the chip. The circuit includes an IF amplifier, an up-conversion mixer, twostages RF amplifiers, and an on-chip ante nna. The IF and RF amplifiers utilize the cascade topology, and the mixer utilizes the dou ble balanced Gilbert cel l, as described in Chapter 3. Figure 4-5 Block diagram of the test chip with an on-chip antenna 4.2.2 Experiment Results The chip was fabricated in the UMC 0.13m logic CMOS process. Figure 4-6 shows the micrograph of test chip. The antenna occupies 3.0 mm x 0.12 mm and the other part occupies 1.1 mm x 0.85 mm in cluding bond pads. The zigzag antenna is formed using all 8 metal layers availabl e and the width of the metal trace is 24 m. The chip is first characterized on-wafer without the antenna. Figure 4-7 shows the input and output matching of the circuit. The |S11| is lower than -10 dB from 2.5 to 3 GHz and |S22| is lower than -10 dB from 22.5 to 25.5 GHz. Figure 4-8 shows the measured output power as function of input power. Th e LO signal power is about 3 dBm. The conversion gain from these four stages is about 20 dB. The circui t provides an output P1dB IF Amplifier Mixer RF Amplifiers 2.67 GHz 21.33 GHz 24 GHz IF LO

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52 of around -4 dBm and a saturated output pow er of around -1.5 dBm, while consuming 15 mA from a 1.2-V supply. The current consum ptions of IF amplifier, mixer, and RF amplifiers are 1.8 mA, 4.8 mA, and 8.4 mA respectively. With a 1.5-V supply, the saturated output power is about 0 dBm and the current consumption is 28 mA. Figure 4-6 Micrograph of the test transmitter with an on-chip antenna Figure 4-7 Input and output matching of the test transmitter -14 -12 -10 -8 -6 -4 -2 0 22.533.54 Frequency (GHz) -25 -20 -15 -10 -5 0 20212223242526 Frequency (GHz)|S11| (dB) |S22| (dB) RF Amplifiers Mixer IF Amplifier Antenna

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53 Figure 4-8 Output power as function of input power Figure 4-9 Measurement setup of the 5-m wireless communication using an on-chip antennas pair To demonstrate the feasibility of us ing an on-chip antenna for wireless communication, an amplitude modulation (A M) signal with 50% modulation depth was provided to the IF input of th e test transmitter chain, so th at, the transmitter delivered a Transmitter 5 m Receiving antenna -35 -30 -25 -20 -15 -10 -5 0 -55-50-45-40-35-30-25-20-15 Pin (dBm)Pout (dBm) P1dB

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54 24-GHz, 0-dBm AM signal to the on-chi p antenna. The measurement setup and environment are shown in Figure 4-9. The distance between the transmitter and the receiving antenna pair is 5 meters. The transm itter is located on a probe station while the receiving antenna is placed on a mobile probe station. The received signal is measured using an HP 8563E spectrum analyzer. The si gnal received at 5 m is about -102 dBm. Considering there is about 3 dB loss from th e probe and cable, the gain between the onchip antennas pair is estimated to be a bout -99 dB. Figure 4-10 shows the AM signal picked up by the on-chip receiving antenna. Figure 4-10 Received signal using an on-chip antenna located 5 m away 4.3 Fully Integrated Transmitter with On-Chip Antenna 4.3.1 Transmitter Chain Overview Figure 4-11 shows the transmitter chain. As mentioned before, the transmitter includes a frequency divider, a MSK-like m odulator, IF amplifiers, an up-conversion mixer, RF drivers, a power amplifier and an on-chip dipole ante nna. The 8:1 frequency divider generates quadrature si gnals for the modulator. The serial baseband digital data -160 -150 -140 -130 -120 -110 -100 -90 -80Center 24.0000011 GHz Span 10 kHz #RBW 3 Hz VBW 3 Hz -102.17 -114.3 -113.5

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55 are up-converted to IF by the modulator. The signal at IF is amplified and fed into a double-balanced Gilbert cell up -conversion mixer. The RF signal is amplified by a 3stage driver and fed to a class-E power amp lifier (PA). Finally, the PA drives a 3-mm long on-chip zigzag dipole antenna. To provi de sufficient LO power level, two buffers for LO signals are also included on the same chip. Figure 4-11 Transmitter chain architecture Figure 4-12 Schematic of the RF drivers and power amplifier The 1-dB compression point of the upconve rsion mixer is only -10 dBm [27], so that, more than 20 dB power gain must be provided by the following RF stages. Too V B2 To Antenna 6 pF VIN V B314 m 6 pF V B424 m 48 m 100 m 1.5 V 1.2 V V B1 1/8 PLL VCO MSKbased Serial Digital Data U p Mixe r Drivers IF AmpModulato r 0 90 180 270 Buffer Buffer 24GHz LO P A

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56 much gain at IF stage is just a waste. Meanwhile, to achieve a lower error vector magnitude (EVM, Appendix A ), the output voltage swing of the modulator is intentionally limited (Chapter 3.3) and a moderate IF stage gain is required. In this design, a two-stage IF amplifier provi des about 18 dB power gain. The four-stage RF amplifiers including PA provide about 25 dB small signal gain. It should also be noted the mixer output power level could be improved by usi ng alternate architectur e [49]. However, it provides lower gain and require s higher power consumption. Figure 4-12 shows the schematic of diffe rential RF drivers and power amplifier. All the circuits in the signal path are fully-differential, which should improve the rejection of common-mode noise from the di gital circuits which will eventually be integrated on the same chip. This also allows the connection to the dipole antenna to be made without a balun. To deliver sufficient power level to the an tenna, the widths of transistors are chosen as 14, 24, 48 and 100 m, respectively. Because the self-oscillation of drivers could be mistuned, to improve the chance for proper frequency tuning of the transmitter, the mode locking technique is not used in this version. Instead, all the three driver stages utilized the cascode topology. In the first two driver stages, the current sources at the common-mode nodes are replac ed by inductors to increase the voltage headroom. Shunt inductors are pl aced at the gates of transistor s in the last two stages, so that, the AC coupling capacitor can be smaller. Here, a lower supply voltage of 1.2 V is used for PA to have larger reliability margins. 4.3.2 Experiment Results and Discussions The chip was once again fabricated using the UMC 0.13m 1P8M CMOS process. Figure 4-13 shows the die micrograph. The ac tive area occupied by the transmitter is 1.8

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57 mm2 including the antenna and bond pads. An in teger-N frequency s ynthesizer is also integrated to study the VCO pulling issue. The size of the synthesizer is 0.7 mm2. Figure 4-13 Photograph of the fully-integrated transmitter and frequency synthesizer The transmitter is first ch aracterized on-wafer without the antenna. The output spectrum is measured using an Agilent E 4448A spectrum analyzer and the output power level is measured using a power meter. Th e transmitter including the divider and LO buffers consumes 100.2 mW. The supply voltage of the PA is 1.2 V and supply voltage of other circuits is 1.5 V to achieve highe r power gain. Figure 4-14 shows percentage of power dissipation in each block. As can be seen, the 24-GHz RF drivers and PA contribute more than 60% of the power cons umption, which is why the efficiency of drivers and power amplifier is so critical in the design. The transmitter can deliver 8-dBm output power to a 50load near 24 GHz. The 3-dB bandwidth is 3 GHz. The PA should be ab le to deliver saturated output power of 10 dBm at 1.2-V VDD if a larger voltage swing were provided by the driver. Figure 4-15 Integer-N Synthesizer IF Amplifiers Mixer RF Drivers PA Antenna 3 mm 1.52 mm LO Buffers Divider & Modulator

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58 shows the output power level between 21 and 26 GHz. The differential LO signal is provided using an external si gnal generator and the minimu m required power is -5 dBm. Figure 4-14 Power consumption dist ribution in the transmitter chain Figure 4-15 Transmitter output power versus frequency Figure 4-16 shows the measur ed output power spectrum density (PSD) for 100Mb/s pseudo random digital input. The random data are provided by an Agilent N4906 -2 0 2 4 6 8 10 20212223242526Output Power (dBm) Out p ut Fre q uenc y ( GHz ) LO Buffers 13.5% 8:1 Divider 7.5% Up Mixer 6.7% Modulator 3.7% IF Amplife r 7.5% PA (Last Stage) 25.2% RF Drivers 35.9%

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59 serial Bit Error Rate Test (BERT) instrument. The measured main lobe bandwidth is about 1.5 times the data rate and contains nearly all the output pow er as expected for MSK modulation. Outside the 24-24.25 GHz IS M band, the peak PSD is -36 dBm/MHz, or 5 dB higher than the equivalent isotr opic radiation power (EIRP) of -41.25 dBm (measured with 1-MHz resolution bandwidth) re quired by F.C.C. If the antenna gain of 10 to -8 dBi is included, the emission easily satisfies the requirement. However, the radio itself should satisfy the requirement, so that it can be used for a wider variety of applications. The higher sidelobes are partiall y due to the IF amplifiers being slightly mistuned to higher frequency. In addition, th e modulation steps should be increased to 8 (Chapter 4.4), so that, the peak sidelobe s are around 3 dB lower and occur at 800-MHz offset, so that, the IF amplifier could provide better suppression. Figure 4-16 Measured output power spectra of the transmitter around 24-GHz The output of transmitter for pseudo random input is down-converted to 1 GHz and the constellation is obtained using an Agilent 89600 vector spectrum analyzer (VSA). The measured rms and peak EVM’s are 7.7% and 16.8% (Figure 4-17). A lower data rate -50 -40 -30 -20 -10 0PSD ( dBm/MHz ) Center: 24.125 GHz SPAN: 1 GHz RBW: 1 MHz ISM band

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60 of 12 Mb/s is used due to the bandwidth limit of VSA. The measured rms magnitude error is 4.4% and the average phase error is 3.8 degrees. Figure 4-17 Measured transmitter output constellation with a 12-Mb/s data rate Figure 4-18 shows the measured spectrum with constant data input. The span is 24GHz, so most of the harmonic spurs can be observed. As mentioned, the F.C.C requires the EIRP of harmonic emission to be lower than -41.25 dBm/MHz. The image signal at 18.76 GHz is around -24 dBm or 32 dB lower than the in-band out put. When a random input is used, the power will spread to the entire frequency band and the power spectrum density will be no higher than -42 dBm/MHz. Therefore, the harmonic emission due to the image satisfies the F.C.C requirements. The LO leakage is about -27 dBm or 35 dB lower than the in-band carrier. The LO leakage is about 14 dB higher than the F.C. C requirement and its power level does not change when random data are used. To reduce this below the F.C.C. limit, notch filters

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61 must be added in the transmitter. More symmetric layout should also be used so that the LO leakage can be better rejected by the circuit. Figure 4-18 Measured output pow er spectrum with 24-GHz span Table 4-1 Summary of the 24-GHz transmitter performance Frequency band 24 24.25 GHz ISM band Modulation constant envelope MSK-like Data rate Up to 200 Mb/s Output power 8 dBm PA saturated output 10 dBm ( Vdd=1.2 V) Power dissipation 100.2 mW PA: 21 mA x 1.2 V Others: 50 mA x 1.5 V EVM 7.7% rms (data rate:12 Mb/s) LO leakage -35 dBc (req. -49 dBc) Chip area 1.8 mm2 The integer-N synthesizer beside the transmitter chain operates from 20.05 to 20.95 GHz, while consuming 24 mA from a 1.5-V s upply. However, due to the mis-tuning of buffers, the output power was not sufficiently. Ne vertheless, the transmitter is functional -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 121518212427303336Frequency (GHz) PSD (dBm/MHz) RF LO Image

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62 when driven from the synthesizer although the transmitted power is about 10 dB lower. The measured performance of the transmitter is summarized in Table 4-1. 4.3.3 Up-Link Demonstration Using an On-chip Antenna The communications between a transmitter with an on-chip antenna and a base station is demonstrated by transmitting a 24-GHz single tone (with constant digital input) and picking up the signal using a horn an tenna with 20 dBi nominal gain. The horn antenna was located at an entrance of a building and the transmitter is placed on a mobile probe station located at a pa rking lot 95 meters away in a humid morning (Figure 4-19). The horn could be considered as the antenna of a base station. The received signal is -97 dBm or the antenna pair gain is about -105 dB. These suggest that communication between a base station and an integrated ci rcuit with an on-chip antenna over a distance of 100 meters is possible. Figure 4-19 Reception of the signal from a transmitter IC with an on-chip antenna using a 20-dBi gain horn antenna located 95m away 95 m TX DC Bias LO Chip RX/horn antenna with 20 dBi gain -97 dBm

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63 4.4 Improved Transmitter Chain Design As discussed, it is required by F.C.C that the spurious emission must be less than 41.25 dBm when measured with 1-MHz re solution bandwidth. The transmitter chain however presently can not satisfy this. The probl ems come from two part s. First, the peak sidelobe power spectrum density is around 35 dBm/MHz. Secondly, the LO leakage is about -27 dBm, or 14 dB higher than require d. These two problems can be solved using improved modulator and amplifiers design. 4.4.1 Improved Modulation Scheme Figure 4-20 Modulator output spectra w ith different modulation steps per bit The sidelobes in Figure 4-16 come form th e modulator. To achieve higher level integration, no filters are used in the transm itter and IF amplifier is the only component which can suppress these sidelobe s. To provide better rejecti on to these sidelobes, more IF amplifier stages can be used, which howev er results in higher power consumption and -100 -80 -60 -40 -20 0 012345678910 Frequency offset from carrier (x data rate)Normalized power spectrum density (dB) 8 steps/bit 4 steps/pit MSK

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64 larger silicon area. A better way is to move these sidelobes to higher frequency offset. Because only 4 discrete steps per bit are used, the peak si delobes appear around 4 times of the data rate. If more steps per bit are used, the sidelobes will move to higher frequency offset. Figure 4-20 shows the modulat or output spectra with 4 and 8 steps per bit scheme. As a matter of f act, the MSK modulation has infi nite steps per bit. In the improved modulator, 8 steps per bit are used. This also requires the control circuit running at higher frequency and the control si gnals better matched to reduce the clock feed-through. The IF amplifiers is also re-tun ed, so that, its center frequency is around 2.7 GHz. 4.4.2 Improved Transmitter Front-End with Notch Filters Figure 4-21 Second and third order no tch filters and th eir characteristics C L Zin1 C1 C2 L Zin2 0 20 40 60 80 100 120 1820222426 0 200 400 600 800 1000 1200 1820222426 Frequency (GHz) Frequency (GHz) Impedance ( ) Impedance ( ) (a) (b)

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65 The LO leakage most likely comes from the active circuitry. Because the bandwidth of the RF amplifiers is wide due to low-Q passive components, the RF amplifiers cannot provide sufficient suppre ssion of LO leakage from the up-conversion mixer. To solve this, notch filters at LO frequency can be inserted. Two notch filters structures can be used. Figure 4-21 shows the schematic and the simulated characteristics of the second and third order notch filters. The Q of the inductor is assumed as 20 and that of the capacitor is 50 at 24-GHz. The i nductor value is limited to less than 1 nH, and the capacitance is less than 100 fF. The gain difference at RF and LO frequency can be estimated as the ratio of impedance at these tw o frequencies. Therefor e, both notch filters could provide about 10 dB suppression to the LO signal. In fact, the LO suppression only depends on the Q of the inductors and capaci tors, if the filters are tuned well. Figure 4-22 Improved transmitter RF front-end with notch filters To provide more than 14-dB rejection, two notch filters should be added to the circuit. From simulation, these notch filters also have nearly 2-dB in-band insertion loss. To compensate this, additional driver stag e is also included. Figure 4-22 shows the improved transmitter RF front-end. The impedance of second order filter is small, typically less than 100 thus, it cannot be added to a node where the impedance is high; otherwise the in-band gain will be significan tly degraded. On the other hand, the third Vtune1 Vtune2 Notch Filter 1 Notch Filter 2

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66 order notch filter cannot be added to a node where the impedance is low, because it almost has no effect on the gain at either th e LO or RF frequencies. Therefore, a third order notch filter is inserted between the second and third dr iver stages, while a secondorder filter is added to the output of the pow er amplifier. The capacitors in these filters are formed using a combination of a meta l capacitor and a MOS capacitor/varactor, so that the operating frequency of the filter can be tuned, while maintaining relatively high Q for the capacitor. 4.5 Fully-Integrated Transceiver Since the transceiver of a Node devi ce is time division duplex (TDD), which means only one chain is active at one time, one antenna can be used. This will make the design more flexible and decrease the silicon area. Generally, a T/R switch is required to control the connection between the receiver, transmitter and the antenna. However, it is difficult to implement single-po le double-throw (SPDT) switches with low insertion loss at 24-GHz using the 0.13m CMOS process. For example, switches implemented in the 0.13m CMOS process achieve 1.8-dB insertion loss at 15 GHz [50]. From simulations, insertion loss of a switch operating at 24 GHz can easily go higher than 2.5 dB. Therefore, at transmitting mode, nearly 50% of the tr ansmitted power will be dissipated in the switch. While in the receiving mode, the hi gh insertion loss will de grade the input SNR or increase the noise figure of receiver chain. For the Node transceiver, instead of us ing a T/R switch, the switching function is merged into the PA and receiver [51], as s hown in Figure 4-23. In the transmitting mode, RxEn is set to low voltage level (around 0.4 V in simulation). The series LswCsw-tank works as a notch filter for LO signal. At the same time, TxEn is set to VDD to turn on

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67 Figure 4-23 Integrated transmitter and rece iver RF front-end with distributed T/R switches transistor Msw. The gate of MRX1 is shorted to ground and this avoids high voltage swing at MRX1 gate. The impedance looking into the receiver will be j Lg which is around 150 j This high impedance assures the impeda nce matching between the antenna and PA output to deliver maximum power while protecting the LNA. While in the receiving mode, TxEn is ground to turn off Msw. RxEn is set to high voltage (VDD), so that Csw is tuned to its maximum capacitance valu e. The resonant frequency of the Lsw-Csw series tank moves to 13.5 GHz and it provides an inductive impedance of 100 j at 24 GHz. In simulation, this distributed switches scheme increase the noise figure for the receiver by 1.3 dB and decreases output power of the PA by 0.8 dB, which are much better than the SPDT T/R switch. The synthesizer provides th e 21.4-GHz LO signals to the receiver and the transmitter. To assure sufficient LO driv e, buffers have been inserted between the LswVg2 Csw MRX1 … TxEn …TX switch RX switch RXEn PA LNA MswMRX2 MTX Lg

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68 synthesizer and each mixer and divider in the receiver and the transmitter. Figure 4-24 shows the PLL output to different buffers. The PLL output buffer consumes 4-mA DC current from a 1.5-V supply. It provides ar ound 800-mV peak-to-peak voltage swing at the TX and RX buffer inputs. Figure 4-24 Integration of the frequenc y synthesizer, transmitter and receiver 4.6 Summary In this chapter, the design and measured results of a fully integrated 24-GHz transmitter chain are presented. The signal tr ansmitted by the circuit with an on-chip antenna can be picked up by an on-chip an tenna 5 meters away or a horn antenna 95 meters away. The communication between a transmitting antenna and a receiver with an on-chip antenna separated by 5 m was also demonstrated in [3]. These works demonstrated that it is feasible to build a wireless transceiver with on-chip antennas for short range communications. An integrated RF transceiver with a frequency synthesizer has been implemented. PLL Down-conversion mixer 1:8 frequency divider (receiver) GSSG pad (for test only) 1:8 frequency divider (transmitter) Up-conversion mixer RX TX

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69 CHAPTER 5 MILLIMETER-WAVE VOLTAGE C ONTROLLED OSCILLATORS 5.1 Overview of the Millimeter-Wave Oscillators For direct conversion architectur e, a voltage controlled osci llator operating at either 50 or 100 GHz is needed. With the rapid adva nce of high frequency capability for CMOS technology, it is becoming possible to make CMOS circuits operating in the millimeterwave frequencies [52]-[70], which once were onl y possible to be realized using GaAs and InP technologies. These millimeter wave CMOS in tegrated circuits can be used to satisfy the ever-increasing demand for bandwidth in communication (bro adband WLAN at 5964 GHz ISM band) as well as the emerging needs for RF sensor systems such as automotive cruise control at 76-77 GHz a nd imagers at 94 GHz. The MMIC solutions can provide the size, weight and performan ce advantages. Implementing millimeter-wave systems using the low cost CMOS technol ogy will lead to lower cost and higher integration levels, and help to turn the re latively small volume applications mentioned above as well as others into main stream high volume consumer applications. Over the past five years, the maximum ope rating frequency of VCO’s fabricated in silicon technology has almost quadrupled from 25.9 to 117.2 GHz [52]-[56], [60]-[64]. Push-push VCO’s using the second harm onic operating between 63 and 131 GHz [59], [65], [67] have also been demonstrated in silicon t echnology. However, among these, the bulk CMOS fundamental VCO’s operating around or above 50 GHz usually show poor phase noise, limited frequency range or large power consumption. In this chapter, the design trade-offs and optimization techni ques for high frequency LC-resonator based

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70 VCO’s are described. These techniques are utilized to realize a 59-GHz VCO with a tuning range of around 5.8 GHz, a 140-GHz fund amental mode VCO, as well as a 192GHz push-push VCO using CMOS technology. This work also shows that even at 100 GHz, lumped element approach can be used to implement VCO’s. As a matter of fact, the circuit sizes can be reduce d using the lumped elements instead of that based on transmission lines. A key to achieving oscillation in an LC os cillator is providing sufficient negative resistance to cancel the losses in the resonant LC tank. This is particularly difficult at high frequencies, because the core transistors cannot be large due to the capacitances they add to the tank. To accommodate core transist ors with a sufficient width, the parasitic capacitances connected to the tank, including th ose of transistors, must be minimized. At given operating frequency, the reduced parasi tic capacitances also allow inclusion of larger varactors for wider tuning range. Th e transistor size limitation can also be alleviated by increasing the quality factor (Q ) of tank to lower the loss. Therefore, low parasitic and high-Q resonator, as well as low parasitic and high gain transistor design is needed. Section 5.2 describes the transistor model in the millimeter-wave frequency range and discusses the operating frequency of the os cillators. Sections 5.3 and 5.4 discuss the performance of passive components (varacto r and inductor). The trade-off between the quality factor (Q) and tuning range of varactor is studied in detail Section 5.5 proposes a low parasitic and high gain transistor design, while section 5.6 desc ribes the architecture of these millimeter wave oscillators. The measured results of the fundamental VCO’s between 59 and 140 GHz are presented in Sectio ns 5.7 to 5.9. The performance of 192-

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71 GHz push-push VCO is discussed in Sec tion 5.10. Finally, the design method of millimeter wave VCO’s is summarized. 5.2 MOSFET Modeling for Millimeter-Wave Design 5.2.1 Gate Resistance and Non-Quasi Static Effect Two figures of merit for quantifyi ng the higher frequency performance of transistors are popular. These are fT (or T) and fmax (or max), which are the frequencies at which the extrapolated current and power ga in are unity. For a VCO, in order to sustain oscillation, the transistor must provide a power gain larger than one. Therefore, the unity power gain frequency, fmax, is closely related to the ma ximum operating frequency of an oscillator. It has been well known that th e gate resistance reduces fmax. The gate resistance is usually just considered as the ohmic sheet resistance of polysilicon. To reduce the gate resistance, the gate can be contacted on both ends and folded into multiple fingers. Therefore, the gate resistance can be expressed as, poly poly gR L W N R L N W N R, 2 ,1 12 1 / 3 1 1 4 1 (5-1) where, W and L are the width and length of the transistor, polyR, is the sheet resistance of the polysilicon, N is the number of fingers, 1/3 account s for the distributed gate resistance, and 1/4 accounts for the two-ends connection. This gate resistance is a bias-independen t component at DC and low frequencies. There is another gate resistance component with bias dependence at high frequency, which is due to the distributed transmission line effect of the gate. To reduce this, a multifinger device with a narrow finger width shoul d be used. The other effect is distributed

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72 channel resistance, arising from the non-quasi static (NQS) effect At frequencies NQS effects cannot be neglected, an additional re sistance is needed to account for the NQS effect. From [71], [72], the equivalent channel resistance can be expressed as 1/(5gm). Figure 5-1 Equivalent gate resistance model includi ng distributed ploy-silicon resistance and distribut ed channel resistance 5.2.2 Unity Gain Frequencies Figure 5-2 Equivalent MO S transistor model incl uding the gate resistance Using the equivalent transistor model in Figure 5-2, the unity current and power gain frequencies can be derive d. A transistor can be consid ered as a two-port network. The gate terminal is the input port, while the drain terminal is the output port. The source terminal is connected to ground. The expression for T assumes the drain is terminated as Rg Cgd Cgs 1/gds gmVgs S D G Cdb Vgs Rdb Ri=1/(5gm) S D distributed gate resistance distributed channel resistance W Ldistributed gate capacitance

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73 short while the gate is driven by an ideal cu rrent source. In additi on, the gate-to-drain capacitance is considered only in the computa tion of the input impedance, while its feedforward contribution to the out put current is neglected. With these assumptions, the ratio of drain current to gate current is ) ( ) (gd gs m gs gd gs gs m in dC C g V C C j V g i i (5-2) which has a value of unity at the frequency of ) ( 2gd gs m T TC C g f (5-3) Though the unity current gain of frequency, T is widely used, it dose not include the effects of several components. As a consequence of the shorted termination, T does not include the drain-bulk capacitance Cdb or output impedance 1/gds. The current source drive also takes out the series gate resistance term. Therefore, unity power gain frequency, max, which include these terms, is more rele vant for high frequenc y oscillator design. The computation of max is generally difficult, so se veral simplifying assumptions are used to make an approximate derivation possi ble (Appendix B) and it can be expressed as gd T ds m g TC g g R f ) 5 /( 1 2 2max max (5-4) Figure 5-3 shows the unity current gain frequency and unity power gain frequency, versus the transistor gate lengt h. For the transistor in 0.13m and 90-nm processes, fmax higher than 100 GHz has been reported. Therefor e, it should be possible to build a CMOS circuit running above 100 GHz. However, with device scaling, the contact/via area decreases and these resistances increase ve ry fast. For instance, the typical contact resistances are 7 15 and 45 in the 0.13m, 90-nm and 65-nm process,

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74 respectively. The higher contact resistance incr eases the gate resistance and slower the increase of fmax of the transistor with scaling. Figure 5-3 Unity current frequency, fT, and unit power gain frequency, fmax, versus gate length 5.2.3 MOSFET Radio Frequency Model Including the parasitic capacitors and re sistors at the drain, gate, source and substrate, a complete RF subcircuit model fo r a NMOS transistor is shown in as Figure 5-4 [71], [73], [74]. Rs and Rd are the source/drain resistan ces due to the resistive n+ active region. Cgsp and Cgdp are the parasitic gate-to-sour ce/drain capacitances, mostly from metal interconnections. Csb and Cdb are the source/drain junction capacitances while, Rsb and Rdb are the series resistances of juncti on capacitances. The parasitic capacitances at the gate and drain terminals will directly contribute to the LC-tank of the VCO and lower the oscillation frequency. The influence of substrate resistance, Rsub, is usually ignored for digital circuit simulation at low frequency. However, at hi gh frequencies, the signal at drain couples to the source and bulk terminals through source/drain junction ca pacitance and the substrate Gate Length (nm) Frequency (GHz) 10 100 1000 101001000 fmaxfT

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75 resistance. The substrate resistance influences mainly the output characteristics, and it can lower the output impedance as much as 30% in 0.13m CMOS process. The CgbRsub network also increases the noise figure of LNA. Figure 5-4 RF model of an NM OS transistor with intrin sic and extrinsic components 5.3 MOS Varactor Usually, at frequencies lower than 10 GHz the Q of LC resonator is limited by inductor loss. This is no longer the case at millimeter-wave frequencie s. Because the Q of capacitors (QC ~ 1/( RC)) decreases with frequency, while that of inductor (QL ~ L/R) increases with frequency, the tank Q is limited by the Q's of capacitors at the millimeterwave frequencies. The optimization of layout and an accurate model for the MOS capacitor/varactor are more critical at the millimeter-wave frequencies oscillators design. 5.3.1 MOS Varactor Structure Figure 5-5 shows the top-view and crosssection of a MOS varactor. The top and bottom plates are formed by silicided n+ polysilicon and n-well, which are separated by a gate oxide layer. The thickness of gate oxide is only about 3 nm, which leads to high G S D RdRs Cgsp Cgdp Rg Cdb Csb 0.5Rsub Rsb Rdb B B Intrinsic MOSFET 1/(5gm) 0.5Rsub

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76 capacitance density of 11 fF/ m2 in the accumulation region. The poly gate is connected at two ends to reduce the resistance. To increase the tuning range, the parasitic capacitance must be minimized. In advan ced CMOS technologies, where the minimum metal-to-metal and contact-to-polysilicon sp acing can be very small, the parasitic interconnect capacitance can be large. To d ecrease the parasitic cap acitance, the metal contacts for n-well are placed 0.4 m from the polysilicon ga te. Since the n-well is usually AC-grounded, the increased n-well to substrate junction capacitance can be tolerated. The metal interconnection of n-well is formed by only metal1 and 2 layers, and the gates are connected together using th e metal7 and 8 layers. For comparison, a varactor structure using the minimum sp acing and a ploy gate dimension of 0.12 m x 0.28 m was also fabricated. The metal conn ection for n-well was formed by stacking metal1 through metal6. The measured parasiti c capacitance, which is mainly due to the poly and metal interconnections, is about 3 times that of the gate oxide. This makes the tuning range of the vara ctor close to zero. Figure 5-5 Top view and cross section of the MOS varactor N-Well N+ STI N+ STI poly Metal1 Metal2 N+ N-well N-poly P-substrate

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77 5.3.2 Equivalent Model A simplified MOS varactor model including a series Ls-Rs-C network is shown in Figure 5-6. In the equivalent model, Cvar is the variable MOS capacitance and Cpar is the fixed parasitic capacitance due to the metal and polysilicon gate parasitic. Rgate is the resistances of poly gate, Rwell is the resistance associated with n-well/cha nnel under the gate, and Rmetal is those associated with the contac ts, vias and metal interconnects at the gate and n-well side, respectively. Other effect s, such as n-well to substrate capacitance, and substrate loss, are not included in the simplified model. More complete varactor models are discussed in [74]-[75]. Figure 5-6 Simplified MOS varactor model As described in [76], the series resistance is unit metal poly nw sR W R L R L W N R, 2 2 ,12 1 1 (5-5) where, W and L are the width and length of each finger, RP,nw and RP,poly are the sheet resistance of n-well and poly gate, N is the number of fingers. The factor of 12 in the denominator accounts for the double si ded n-well and poly gates contacts. Rmetal,unit is the resistance from contacts, vias and metal in terconnect in each finger. Because it decreases with more contacts and vias, their number s are increased to as many as allowed. As also described in [76], if only the capacitors from gate oxide and resistance from poly gate and channel are considered, the qual ity factor of this simplified model network is, Ls Rmetal Rgate Cva r Cpar Rwell

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78 ) ( 12 1, 2 2 ,WL R W R L R C C R Qunit metal poly nw ox s (5-6) where is the frequency and Cox is the gate-oxide capacitance per unit area. To increase Q, smaller W and L should be used. However, the penalty is larger parasitic capacitance due to more metal interconnections, wh ich decreases the tuning range. Since RP,nw is more than 50 times the RP,poly, L should be made smaller, while W of a finger can be made larger to reduce the parasitic capacitances With the continuing scaling in CMOS technology, the Q of varactor s hould increase with smaller gate length and lower n-well sheet resistance. However, this increase will be tempered by the increases in the contact and via resistances. 5.3.3 Experiment Results and Discussions To experimentally examine these, structures with varying gate lengths were fabricated in the UMC 0.13m CMOS process. The average capacitances of structures are kept approximately the same. The effects of pads are de-embedded using the open structure formed by disconnecting the gate conn ection from the pad as discussed in [76], [77]. One-port S-parameters of the test and open structures were collected using an HP8510C 26.5-GHz network analyzer. Figur e 5-7 shows the measured capacitance, series resistance, and quality factor of a MOS varactor. The finger length (L) is 0.24 m and width (W) is 0.64 m and there are 20 fingers. Figur e 5-8 shows the C-V and Q-V curves measured at 24 GHz for three varact ors with different di mensions. The minimum gate length of 0.12 m is used for structure (a), thus, it gives nearly the highest available Q. A minimum Q of 24 is achieved at 24 GHz, wh ich is close to the Q reported in [52]. When extrapolated using Q=1/( RC), Q is about 9 and 6 at 60 and 100 GHz, respectively.

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79 However, the tuning range is limited (Cmax/Cmin=1.75), though larger than 1.2 reported in [52]. In structure (c) w ith a gate length of 1 m, the tuning range (Cmax/Cmin) is ~7. As Figure 5-7 Measured MOS varactor capacitance, series resistance and quality factor at 24 GHz for a varactor with 0.64m width, 0.24m length and 20 fingers 0 20 40 60 80 -1.5-1-0.500.511.5 Vg (Volt)Capacitance (fF) 6 8 10 12 -1.5-1-0.500.511.5 Vg (Volt)Rs ( ) Rs C 0 10 20 30 40 -1.5-1-0.500.511.5 Vg (Volt)Quality Factor Q

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80 expected, the penalty is lower Q of ~2.5 in the accumulation region. A medium gate length of 0.24 m is used in structure (b), which has moderate Q at 24 GHz of 12.5 and an excellent Cmax/Cmin ratio of 3.5. Figure 5-8 C-V and Q-V characteristics of the MOS varactors with different gate dimensions Figure 5-9 shows the meas ured minimum Q and Cmax/Cmin ratio of varactors with varying gate lengths. The minimum Q decreases with the gate length, while the tuning 0 20 40 60 80 100 -1.5-1-0.500.511.5 Vg (Volt)Capacitance (fF) 0 10 20 30 40 -1.5-1-0.500.511.5 Vg (Volt)Quality Factor ( a ) 0.12x 0.64 x 25 (b) 0.24 x 1.00 x 24 (c) 1.00 x 6.00 x 1 ( L x W x N ) unit ( m) (a) (b)

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81 ratio increases. Depending on the operating fr equency, phase noise, power consumption and tuning range requirements for the VCO, a suitable varactor structure can be chosen using a plot like this. For the 0.13m CMOS process, the gate lengths between 0.18 to 0.24 m result good tuning and Q. Figure 5-9 Minimum varactor Q and Cmax/Cmin ratio at 24 GHz as a function of gate length 5.4 High Performance On-Chip Inductor Figure 5-10 shows the layout of differential circular inductor used in the 105-GHz VCO. To reduce the capacitance to substrat e, only the top metal 8 layer is used. The metal 8 layer is 0.8 m thick and ~5 m above the silicon substrate. The metal width is 3.6 m. Since the skin depth of copper at 105 GHz is ~0.20 m, the metal width of inductor can be as narrow as ~6 x 0.20 = ~1.2 m. The patterned ground shield is formed using the polysilicon layer and each finger is perpendicular to the metal trace. The spacing between polysilicon shields is set to ~4 m to reduce the pa rasitic capacitance 0 5 10 15 20 25 00.20.40.60.81 Gate Length ( m)Quality Factor0 1 2 3 4 5 6 7 8Tuning Ratio (Cmax/Cmin) Q Cmax/CminCmax/Cmin

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82 without degrading the quality factor [78]. A lumped inductor mode l [79], [80], including a series resistor, shunt capacitors, and substr ate resistors, is used for the design. The model parameters are extracted using Agilent Momentum, a 2.5-D EM field simulator. The simulations show the inductance of loop with a diameter of 57 m is ~ 90 pH and Qbw [81] is ~50 at 105 GHz. For the 59-GHz VCO, the inductor diameter is 89.6 m and the trace width is 4.8 m. The inductance is ~200 pH and Qbw is ~35 at 60 GHz. Lastly, the interconnections carrying signals at the millimeter-wave frequencies have also been modeled using the lump ed inductor model. Figure 5-10 Differen tial inductor layout Figure 5-11 Lumped inductor model of differential inductor 45 pH 0.7 0.7fF 0.7 45pH 1.4fF 0.7fF 7 Center Tap 2 1 Metal1 (Ground) Polysilicon (PGS) Metal8 (Inductor Trace) To Core transistors To Current Source

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83 5.5 Transistor Layout As mentioned, to increase the oscillati on frequency, the parasitic capacitance connected to the tank must be minimized. Fo r the VCO’s operating near 60 and 100 GHz, the capacitance of transistors in the 0.13m technology is comparable or larger than that from the varactors. Therefore, the parasitic capacitance of transistors must also be minimized. Figure 5-12 shows the top view of cross-coupled transistor s, which is similar to that used in [82]. It consists of a top part (M1) and a bottom part (M2) that are directly cross connected from the drain to gate. Th is makes the metal interconnect between the two transistors shorter which lowers the loss and parasitic capacitance of the interconnections. The drains of fingers are conne cted together by metal6 lines. The finger width of transistors needs to be kept small to lower the gate resistance. This however increases the gate to body/substrate capacitanc e. Because of these two competing effects, there should be an optimal finger wi dth. The final finger width of 0.64 m is chosen to maximize fmax [82]. From the measur ed results in [58], fmax is expected to be ~120 GHz. Figure 5-12 Cross-coupl ed transistor layout Metal1 Polysilicon Active Contact Source (GND) Source (GND) M1 M1 M2 M2 0.12 0.20 To metal6 To metal6 0.16 (unit: m)

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84 As was done for the varactor, the metal sp acing is intentiona lly increased. The spacing of source contact to gate is made 0.20 m, so that the parasitic gate and drain to source capacitances are reduced at the expense of slightly larger so urce series resistance. The increased source-to-body capacitance has ne gligible impact on VCO operation since the source nodes are virtual grounds. The drai n is usually made as small as allowed by design rules to reduce Cdb. However, in the VCO, the gate to drain capacitors (Cgd) of two core transistors are connected to the anti-pha se nodes. As shown in Figure 5-13, due to the Miller effect, the gate-to-drain overla p capacitance contribu tion to the tank is 2 (Cgd1+Cgd2) Thus, the effective transistor capac itance at the drain node is actually Cdb+ 4 Cgd. Figure 5-13 Capacitors in the VCO Increasing the spacing between drai n contact and gate decreases Cgd and increases Cdb. Simulations show that the drain contact to gate spacing of ~0.16 m minimizes the effective capacitance added to the tanks. As st ated earlier, the capacitance of transistors is comparable or larger than that from the varactor. Because of this, the Q of LC-tank strongly depends on the transi stor. For the 100-GHz VCO’s, since the capacitance of 2Cgd2 Cvar Cvar Cdb1 Cdb2 2Cgd2 2Cgd1 2Cgd1 Cgs2 Cgs2 M1 M2 M1 M2 Cequ=4Cgd+Cgs+Cdb+Cvar Cgd1 Cgd2 Cvar Cvar Cdb1 Cdb2 Cgs1 Cgs2

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85 transistors is much larger than that of the va ractors, the transistor capacitance is expected to determine the Q of the LC-tank. 5.6 Circuit Architecture The VCO employs the NMOS cross-coupled topology and is shown in Figure 5-14. The resonator consists of a single-loop circ ular inductor and an accumulation mode MOS capacitor. The bias current is injected in the middle of the inductor by a PMOS transistor, M7. This enables the modulation of Vdrain node by changing the Vbias voltage. As will be described, unlike other VCO’s, this is th e main mechanism used to tune the VCO frequency around 100 GHz. In addition, the buffer for driving the 50load utilizes two tapered stages to lower the capacitance added to the LC tanks. Figure 5-14 Schematic of the proposed VCO The PMOS current source is used to utili ze the full range of the varactor without requiring tuning voltages above Vdd or below zero. The varact or shows the best tuning around zero gate bias. For the VCO in Figur e 5-14, the top plate (gate) voltage of varactor is set to ~VDD/2 by using the PMOS current so urce on the top. When the bias M1 M2 M7 M3 M4 M5 M6 On-Chi p 50 50 VDDVDD B U FFVDD B U FF L1L2L 3 L4 L 5 L 6 Vbias Vdrain VTune

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86 voltage on the bottom plate of vara ctor is varied between 0 and VDD, the voltage across the varactor varies from -VDD/2 to VDD/2. Figure 5-8 also shows that the C-V curve is not monotonic due to the poly gate depletion when the gate bias is higher than 1 V. This may lead to a locking problem in th e phase-locked loop [52]. Since VDD is usually 1.2-1.5 V for the circuits built using this process, by limiting the gate to bulk voltage from -VDD/2 to VDD/ 2, the bias range affected by the pol y gate depletion region is avoided. 5.7 60-GHz Wide Tuning Oscillators 5.7.1 Design Considerations The 60-GHz WLAN band spans the fr equencies between 59 and 64 GHz. The VCO for this application must have a tuning range greate r than 5 GHz. However, the recently published CMOS VCO’s operati ng near 40-60 GHz ha ve tuning ranges significantly less than 5 GHz [53], [54], [62], except those fabricated using SOI processes due to lower parasitic capacitances in the SOI processes [55], [60] A wider tuning range in bulk CMOS is also possible when the parasitic capacitances from the varactor, transistor and inductor are minimized as disc ussed above. The varactor value should be maximized and varactors with a larger tuni ng ratio should be used. This however, can degrade phase noise because of an increase of VCO gain and a decrease of varactor Q. To evaluate this trade-off for VCO’s operating in the millimeter-wave frequency range, two VCO’s with different varactor structures are fabricated. In the first VCO, varactors with twenty 0.12 m (L) x 0.64 m (W) fingers are used. In the second one, varactors with ten 0.24 m (L) x 1 m (W) fingers are used. The two var actor structures have nearly the same capacitance value in accumulation region. Th e core transistor width is chosen to be 14.72 m. It is more than twice the minimum size required to sustain oscillation.

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87 5.7.2 Experiment Results and Discussions Figure 5-15 shows a micrograph of the 60-GHz VCO. Both VCO’s start to oscillate with about 3.5 mA current from a 0.9-V s upply when the varactor s are biased in the depletion region (Vtune = 1.5 V). To achieve good phase noise performance and output power greater than -10 dBm, the measurements are made at 6.5-mA bias current and 1.5V VDD. The output buffer consumes about 10 mA from a 0.8-V supply. Figure 5-16 shows the output spectrum of the VCO. Figure 5-17 shows the measured carrier frequency vs. the tuning voltage for th ese two VCO’s. For the VCO using 0.12m gate length varactors, the tuning range is 3. 8 GHz, while for the second VCO using the varactors with 0.24m gate length, the tuning range is 5.8 GHz. This difference is due to the larger tuning from the varactors with a longer cha nnel length. Figure 5-18 shows phase noise at 10 MHz offset vs. the tuni ng voltage for these two VCO’s. The phase noise peaks around 0.5~1.0-V tuning volta ge due to larger VCO gain resulting Figure 5-15 Microgra ph of the 60-GHz VCO VDD VBIAS VTUNE GND GND GND OUT+ OUTVDD,BUFF VDD,BUFF Inductor Core transistor L3 L4

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88 from a higher rate of change of varactor capaci tance. When the varactors are biased in the depletion region (Vtune = 1.5 V) and accumulation region (Vtune = 0 V), the VCO using varactors with a shorter finger length has phase noise of -89 dBc/Hz (not shown) and Figure 5-16 Output spectrum of the 59-GHz VCO (VDD = 1.5V, Vtune= 1.5V) Figure 5-17 Frequency range of two different VCO’s using di fferent varactor structures 53 54 55 56 57 58 59 60 00.511.5 Vtune (V)Frequency (GHz) VCO1 VCO2(0.12 m x 0.64 m x 20) (0.24 m x 1 m x 10) Ref 0dBm Norm Log 10 dB/ LgAv V1 S2 S3 FC A AA £ ( f ): FTun Swp Center 59.424 25 GHz Span 20 MHz #Res BW 180 kHz VBW 180 kHz #Swee p 1ms ( 601 p ts ) Mkr1 59.424 45 GHz Ext Mix -9.74 dBm

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89 -108 dBc/Hz at 1-MHz and 10-MH z offsets, respectively, which are ~ 1 dB lower than that of the second VCO. When the varactors are biased in the tran sition region, the VCO using the longer gates shows 2-3 dB higher phase noise. The differences are attributed to the 50% lower Q of the longer channel varactor as well as the larger VCO gain resulting from the ~60% larger tuning range. Figure 5-18 Phase noise of the two different VCO’s as function of the tuning voltage 5.8 100-GHz Oscillators in 0.13m CMOS 5.8.1 Design Considerations Since the fmax of NMOS transistors in the 0.13m CMOS process is higher than 100 GHz, so it should be possible to impl ement a VCO operating near 100 GHz. By applying the low parasitic, low loss design techniques discussed above, VCO’s operating between 90 to 105 GHz were designed. To explor e the frequency limit of this process, the core transistor sizes varying from 12.16 to 8.32 m are used to tune the center frequencies of VCO’s. For the varactors, th e minimum gate length is not used. Instead, -110 -108 -106 -104 -102 -100 -98 00.511.5 Vtune (V)Phase Noise at 10MHz offset (dBc/Hz) VCO1 VCO2(0.12 m x 0.64 m x 20) (0.24 m x 1 m x 10)

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90 one 0.24 m x 0.9 m finger with a larger tuning rati o is used. For the cross-coupled transistors, the finger width is 0.64 m. The number of fingers is changed from 19 to 13. Transmission lines have been used for ma tching and tuning in the circuits operating at frequencies from 60 to 100 GHz [56]-[58] However, a quarter-w avelength is still about 600 and 375 m at 60 and 100 GHz, respectively. The relatively long transmission line will increase the circuit si ze, as well as increasing the loss. The dimensions of components in the 105 GHz VCO are less than 90 m or ~6% of a wavelength. This makes the lumped element analysis still a pplicable for these components even at 105 GHz. In the design, the lumped model of vara ctor was extracted from the measurement at 24 GHz and the inductor model was cons tructed using Agilent Momentum. The simulated carrier frequencies and tuning ra nge are within 5% of the measurements. 5.8.2 Millimeter-Wave Spectrum Measurement Setup Figure 5-19 100-GHz VCO measurement setup Making spectrum measurements at millimeter-wave frequencies gets progressively more difficult as the frequencies get higher. Figure 5-19 shows the setup to measure a frequency source around 100 GHz. The VCO’s were measured on-wafer with an Agilent Agilent E4448A Spectrum Analyzer ( External Mix ) 75-120GHz Wave-guide probe Agilent 11970W 75-110GHz Harmonic Mixer LO IF

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91 E4448A spectrum analyzer and an Agilent 11970W 75-110 GHz harmonic mixer. The harmonic mixer down-converts the VCO output to 321.4 MHz [83] [84]. A 75-120 GHz W-band wave-guide probe is used to measure the VCO’ s operating near 100 GHz. Figure 5-20 Simplified block di agram of measurement setup The most common architecture for spectrum an alysis uses fundamental mixing, i.e. IF = (RF LO). However, this technique is less desirable for measurements at higher microwave and millimeter-wave frequencies due to the need for a high performance local oscillator with a very high and very wide frequency range Instead, using a harmonic of the local oscillator provides several benefits These benefits depend on whether the first mixer is located inside the spectrum analyz er (internal mixing) or outside (external mixing) of the analyzer. Figure 5-20 show s the simplified block diagram of the measurement setup. The frequency relationshi p can be expressed as IF = (RF – N x LO). The RF frequency can be obtained us ing RF = N x LO IF and the correct harmonic number can be automatically found us ing the signal identi fication function in spectrum analysis [83], [84]. The harmonic number N ranges from 6 to 54, and the LO frequency is around 3 to 6 GHz. Presently, th e harmonic mixers which can cover up to 325 GHz are commercially available. The main benefit of harmonic mixing is th e ability to analyze higher frequencies by using the same local oscillator and most of th e same IF structures that are also employed to analyze signals at lower frequencies. With harmonic mixing, the local oscillator need IF= (RF-N*LO) (IF < 1 GHz) RF LO (3 – 6 GHz) VCO Harmonic Mixer

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92 not have a signal source with frequency near the frequency of si gnals being measured. The LO only needs to have a harmonic (with su fficient energy to drive a mixer) at near the frequency of signal being measured. However, there are also drawbacks and performance limitations including reduced fr equency accuracy and stability, increased phase noise, undesired and unidentified mixer products, reduced amplitude sensitivity, and reduced amplitude accuracy. The VCO frequency can be obt ained using the signal identification function. This works well for the VCO measurements below 100 GHz. However, sometimes this function fails for oscillators operating around or above 100 GHz, most likely due to the signal not being sufficiently stable. Instead, to obtain the value of N, the LO frequency is changed by f, which changes IF by N x f. Then, the output frequency of VCO can be calculated using RF = N x LO IF. The sign depends on whether IF increases or decreases with the LO frequency change. Actually, this procedure is similar to that used by the built-in signal identification function, where the LO frequency is also changed by some amount depending on the harmonic number [84]. 5.8.3 99-GHz Voltage-Controlled Oscillator The 99-GHz VCO using 9.6m wide cross-coupled transist ors starts to oscillate at the bias current and supply voltage of 3.4 mA and 1.0 V. Once again, for more stable oscillation and larger output power, the measur ements are made at higher bias current of 6 mA and VDD of 1.5 V. An amplifier with 20-dB gain and 4.5-dB noise figure is added between the mixer output and spectrum anal yzer to reduce the impact of background noise from the analyzer. The measured out put spectrum is shown in Figure 5-21. The external amplifier gain, ~40-dB conversion loss of mixer and ~3-dB loss from probe and

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93 cable were de-embedded. The measured pha se noise is about 103 dBc/Hz at 10-MHz offset from the carrier. Figure 5-21 Output spectrum of the 99-GHz VCO Since the transistor capacitance is th e dominant contributor to the LC-tank capacitance and the transistor capacitance depends on the bias conditions, the transistor capacitance can be tuned to increase the t uning range. In fact, se veral authors have suggested changing supply voltage to increa se the tuning range of VCO’s [54], [56]. However, varying supply voltage is not practic al. A simple way to vary the DC bias of transistors is to change the gate bias of the tail transistor (M7 in Figure 5-14). By limiting the current range, it is possible to limit the variations of output power and phase noise over the tuning range. In this implementation, the Vbias is used for fine tuning and the varactors are used for coarse tuning. Since the varactors are bias ed in either strong accumulation or depletion, where the VCO gain du e to the varactors is smaller, this helps to keep the phase noise low. Figure 5-23 s hows the tuning characte ristics of VCO. By Mkr1 98.499 75 GHz Ext Mix -18.55 dBm Ref 0dBm Norm Log 10 dB/ LgAv V1 S2 S3 FC A AA £ ( f ): FTun Swp Center 98.499 70 GHz Span 50 MHz #Res BW 470 kHz VBW 470 kHz #Swee p 1ms ( 601 p ts )

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94 varying Vbias from 0 to 0.59 V when Vtune is 1.5 V, the bias cu rrent can be changed from 4.5 to 10 mA and the VCO can be tuned be tween 97.8 and 99.2 GHz. By biasing the MOS varactor in the accumulation region (Vtune = 0 V), the output frequency can be varied between 96.7 to 98 GHz. Over the tuning range, the ph ase noise at 10-MHz offset varies from -99.5 to -102.7 dBc/Hz and out put power varies from -22 to -18 dBm. The total tuning range is 2.5 GHz or ~ 2.5%. The be st phase noise is measured at 6-mA bias current instead of the largest current. If la rger output power level variations and higher phase noise can be tolerated, the tuni ng range can be increased to ~3 GHz. Figure 5-22 Measured phase noi se plot of the 99-GHz VCO 5.8.4 105-GHz Voltage-Controlled Oscillator By reducing the core transistor width to 8.32 m, a VCO operating from 105.1 to 105.3 GHz is demonstrated. Figure 5-24 s hows a micrograph of the VCO. The VCO consumes 6 mA from a 1.2-V supply. Figur e 5-25 shows the measured output spectrum. When it was reported, this was the highest fundamental frequency CMOS circuit up to Carrier Power -42.59 dBm Atten 10dB Mk1 10.0000 MHz Ref -50 dBc/Hz -102.74 dBc/Hz 10.00 dB / 200 kHz Frequency Offset 20 MHz

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95 that time. The tuning range is only 200 MHz. The circuit stops oscillation when the varactors are biased in the accumulation region or the bias current is reduced below 5 mA. This also suggests the oscillat ion frequency of 105 GHz is very close to the limit of 0.13m CMOS process. The VCO achieves phase no ise of -97.5 dBc/Hz at 10-MHz offset. Because the signal is week a nd unstable, the phase noise plot like Figure 5-22could not be obtained. Figure 5-23 Frequency tuning, current c onsumption and phase noise of the 99-GHz VCO at 1.5 V VDD. 5.9 Oscillators Operating above 100 GHz in 90-nm CMOS The 90-nm CMOS process offers a unity power gain frequency, fmax, of around 200 GHz [71], therefore, it should be feasible to build oscillators operating well above 100 GHz. In this section, F-band (90 140GHz) VCO’s fabricated in the UMC 90-nm CMOS [70] process is discussed. The arch itecture of the VCO’s is the same as the 100-GHz VCO’s 96 97 98 99 10000.10.20.30.40.50.60.7VBias (V)Frequency (GHz)-40 -30 -20 -10 0 10Output Power (dBm) Current (mA) I (mA) Pout (dBm) Vtune = 1.5 V Vtune = 0 V

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96 Figure 5-24 Microgra ph of the 105-GHz VCO Figure 5-25 Output spectrum of the 105-GHz VCO discussed above. Figure 5-26 shows the mi crograph of a 140-GHz VCO. Each VCO occupies 540 x 360 m2 including bond pads. The cross-coupled transistors are 8.36 m wide with the minimum gate length. They consist of 11 fingers, whose width is 0.76 m. The varactors are formed by two 0.5 m x 0.18 m fingers with contacts on both sides of Mkr1 105.224 5 GHz Ext Mix -25.04 dBm Ref 0dBm Norm Log 10 dB/ LgAv V1 S2 S3 FC A AA £ ( f ): FTun Swp Center 105.223 5 GHz Span 100 MHz #Res BW 910 kHz VBW 910 kHz #Swee p 1ms ( 601 p ts ) VDD VBIAS VTUNE GND GND GND OUT+ OUTVDD,BUFF VDD,BUFF

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97 the gate finger. The inductor trace was form ed using the top metal 9 (copper) layer with a thickness of 0.8 m. The trace width is chosen to be 2 m. To explore the frequency limit of this process, three VCO’s with varying inductor size are fabricat ed while keeping the transistors and varactors the same. The diamet ers of the circular inductors are 53, 40.8 and 31.6 m, respectively. The inductance is es timated to be between 80 and 50 pH. Figure 5-26 Photogra ph of the 140-GHz VCO Figure 5-27 Output spectrum of the 140-GHz VCO Mkr1 139.835 06 GHz Ext Mix -71.08 dBm Ref -40 dBm Norm Log 10 dB/ LgAv V1 S2 S3 FC A A A 1 Center 139.835 60 GHz Span 50 MHz Res BW 470 kHz VBW 470 kHz Sweep 1.04 ms (1201 pts) VDD GND GND GND GND VBIAS VTUNE VDD,BUFF OUT+ OUT-

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98 The 140-GHz VCO starts to oscillate at a bias current of 4.5 mA with VDD = 1 V. For more stable oscillation and larger output power, the measurements are made at a bias current of 8 mA and VDD = 1.2 V. Figure 5-27 shows the output spectrum. The conversion loss of harmonic mixer is about 50 dB and the insertion lo ss of probe is about 2 dB at 140 GHz. Thus, the outpu t is estimated to be somewhere around -19 dBm. Figure 5-28 shows the measured free running VCO pha se noise plot. The phase noise plot is noisy especially at low offset frequencies due to the frequency drif t. The phase noise is about -85 dBc/Hz at 2-MHz offset from the carrier. Figure 5-28 Phase noise pl ot of the 140-GHz VCO Figure 5-29 shows the output fre quency versus tuning voltage (Vtune) at 1.2-V VDD. At bias current of 8 mA, the output fre quency can be tuned from 139 to 139.8 GHz by changing the varactor voltage. As mentioned before, the operating frequency of VCO can also be tuned by the bias current. The output frequency can be tuned from 139 to 140.2 GHz if both the bias current and varactor ar e varied. In order to keep the output power Carrier Freq 139.8 GHz Signal Track off DANL off Trig Free Carrier Power -71.41 dBm Atten 10dB Mkr1 2.00000 MHz Ref -50 dBc/Hz -85.12 dBc/Hz 1 MHz Frequency Offset 10 MHz 5.00 dB / 1

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99 within 3 dB of the maximum, Vbias is kept lower than 0.56 V or the bias current is kept higher than 6.4 mA. If larger output power variation can be tolerated, the operating frequency can be increased to as high as 140.5 GHz. For this VCO, the bias current is used for coarse tuning and the varactor fo r fining tuning. The tuning curves for Vbias’s of 0 and 0.56 V overlap by ~ 500 MHz. Figure 5-29 Output frequenc y versus the tuning voltage The operating frequency decreases monotonica lly with the increas e of bias current or supply voltage for the oscillators in the 0.13m process (Figure 5-23). However, this is not the case for the VCO’s fabricated in this process. Figure 5-30 shows the output frequency versus supply voltage for the 140-GHz VCO when both Vbias and Vtune are grounded. The minimum operating frequency is achieved around 1.2 V. The VCO stops oscillation when the supply voltage is lower than 1.0 V or higher than 1.5 V. For the 110GHz and 123-GHz oscillators, the minimum ope rating frequencies ar e achieved at 1.5 V and 1.35 V, respectively. These minima are most likely due to the enhanced polysilicon gate depletion effect in the transistors with a thinner gate oxide (~ 2 nm) layer. The supply 139 139.5 140 140.5 141 00.30.60.91.21.5Output Frequency (GHz) V tune ( V ) Vbias = 0.0 V, I = 8 mA Vbias = 0.56 V, I = 6.4 mA Vbias = 0.62 V, I = 5 mA

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100 voltages for 90-nm processes are less than 1. 2 V, and this phenomenon should in general not matter. Figure 5-30 Output frequency versus VDD for the 110-GHz VCO Table 5-1 Summary of the measured VCO performance Version 109 123 140 VDD [V] 1.2 1.2 1.2 Current [mA] 8 8 8 Output Power [dBm] -10 -141 -191 Freq.Range[GHz] (varactor only) 108.3 – 109.2 122.1 – 122.95 139 – 139.8 Freq. Range2 [GHz] (varactor + current) 107.95 – 110.43 122 – 123.64 139 – 140.2 2-MHz offset -88.23 -86.44 -85.1 10-MHz offset -105.23 -100.24 -93 Technology UMC 90-nm logic CMOS Chip Area 540 m x 360 m 1 Accurate conversion loss of the harmonic mi xer is not available, and the output power estimation is only approximate. 2 Output power levels are kept within 3dB of the maximum. 3 VDD = 1.5 V. Phase noise is measured at 12 mA bias current. 4 VDD = 1.35 V. Phase noise is measured at 10 mA bias current. Table 5-1 summarizes the measured VCO pe rformance. With increasing oscillation frequency, output power dr ops and phase noise increases The phase noise for 109, 123 138.9 139.1 139.3 139.5 139.7 139.9 11.11.21.31.41.5Vdd (V)Frequency (GHz)4 6 8 10 12 14Current (mA) Frequency Current

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101 and 140-GHz VCO’s were measured at VDD of 1.5, 1.35, and 1.2 V, respectively. These are the points at which the output frequency versus VDD plots have the minima, and the supply pushing is minimized. At these bias conditions, the VCO’s become sufficiently stable to attempt the phase noise measurements An interesting possibility for exploration is reducing the supply pushing by making the flat portion in Figure 5-30 to be centered around VDD for the circuit. 5.10 192-GHz Push-Push Oscillator 5.10.1 Circuit Design Figure 5-31 Schematic of the push-push VCO Figure 5-31 shows the schematic of push-pus h VCO. It is based on the fundamental mode VCO discussed above. Cr oss-coupled transistors M1 and M2 form the VCO core. The width of the transistors is 12.16 m. Inductors, L1 and L2 (~45 pH), accumulation mode MOS capacitors, and the cap acitances associated with M1 and M2 form the LC resonant tank. At the virtual ground (or common mode) nodes, the anti-phase M1M2 VBIAS C1,a 2f0 (192 GHz) f0 (96 GHz) f0 (96 GHz) VBIAS VDD VDD VTUNE M3,a M3 bL1 L2 C1,b T1,a T1,b 12.16 / 0.12 60 / 0.3 60 / 0.3

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102 fundamental signals cancel out and the s econd harmonic signal can be extracted. The middle point of inductors L1 and L2 has the lowest parasitic capacitance to ground among the common-mode nodes. This makes the impe dance at resonant frequency the highest and the best port to extract the push-push output. A quarter wavelength transmission line tuned for the second harmonic frequency is us ually used to increase the amplitude of second harmonic while suppressing the funda mental signal. In this design, the transmission line and the current source transist or are broken into two parts to make the layout symmetric, which better suppresses th e fundamental signal at the common mode nodes. Figure 5-32 Grounded coplanar waveguide transmission line The transmission line structure is shown in Figure 5-32 and is formed using the grounded coplanar waveguide (C PW) structure [31], [85]. Compared to the conventional CPW, the ground plane isolates the line from the lossy silicon subs trate and reduces the insertion loss. The lines are formed using th e top metal 8 layer and the ground plane is formed by metal 1. The transmissi on line width and gap are 3 and 4 m, respectively. GND Signal GND PSi GND 15 m 4 m 3 m 4 m 15 m 0.8 m 4 m 150 m

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103 The characteristic impedan ce of the line is about 65 The length of lines is 150 m. This length is slightly shorter than /4, so that the impedance looking into the transmission line is inductive to resonate the capacitances from the pad and other metal interconnections. The 2-pF bypass capacitors (C1,a, C1,b in Figure 5-31) serve as short around 190 GHz. They are formed using the pa rasitic capacitance between adjacent metal layers [50]. The metal 8, 6, 4 and 2 layers form the top plate, and metal 7, 5, 3 and 1 layers form the bottom plate. The capacitance density is 0.55 fF/ m2. The transmission lines and bypass capacitors are simulated usi ng the Ansoft HFSS, a 3D EM simulator. 5.10.2 Experiment Results Figure 5-33 Micrograph of the 192-GHz push-push VCO Two VCO’s are implemented in the UMC 0.13m CMOS. In the first version, to achieve higher oscillatio n frequency, the output buffers and bond pads for the fundamental output were not incl uded. The chip occupies 450 m x 390 m including the bond pads. A micrograph is shown in Figure 533. The second VCO including the buffers GND GND VTUNE VDD VBIAS 2f0 M1, 2 L1 L2T1,a T1,b C1,a C1,b

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104 for the fundamental port was also fabricated Due to the capacitance from output buffers, the measured fundamental oscillation frequency is about 4 GHz lower. The chip was measured on-wafer as illustrated in Figure 5-19 using a GGB WR-5 (140 to 220 GHz) waveguide probe. The cut-off frequency of the TE10 mode in WR-5 waveguide is 115.7 GHz, which attenuates the fundamental signal entering the waveguide probe. The VCO output spectrum is measured using an OML M05HWD (140 to 220 GHz) harmonic mixer and an Agilent E4448A 50-GHz spectrum analyzer. An Agilent 11970W (75 to 110 GHz) harmonic mixer has also been used to evaluate the fundamental output. The circuit starts to oscillate at 3.2mA bias current. However, no signal was detected at the push-push port unt il the bias current is increase d to above 8 mA due to the detection limit of the measurement setup. To obtain higher output level, the circuit is measured with 11 mA bias current from a 1.5-V supply. Figure 5-34 shows the output spectrum and the measured signal level is -82 dBm. The conversion loss of harmonic mixer is around 60 dB at 190 GHz. The insertio n loss of probe is about 2 dB. Thus, the signal is estimated to be about -20 dBm. Th e oscillation frequency can be tuned from 191.4 to 192.7 GHz by changing Vtune from 0 to 1.8 V. 192-GHz is the highest operating frequency for any silicon based circuits. B ecause the output of harmonic mixer is weak, the phase noise could not be directly measur ed. The phase noise of fundamental output is -106 dBc/Hz at 10-MHz offset for the VCO with the output buffer. The phase noise at the push-push port is expected to be 6 dB highe r. Due to the coupling through the substrate and metal interconnection, the fundamental si gnal also appears at the push-push port. The measured fundamental signal is about -30 to -25 dBm at the push-push port after

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105 calibrating the losses. As expected, the fre quency tuning range of fundamental signal is exactly one half of the second harmonic. Figure 5-34 Measured VCO output spectrum 5.11 Summary and Discussions Millimeter-wave VCO’s operating betw een 60 and 192 GHz are presented. Reducing the metal parasitic capacitances of va ractors, inductor and tr ansistors is the key for achieving the wide tuning range at 60 GHz and operation close to 200 GHz using a 0.13m bulk CMOS process. The 192-GHz opera ting frequency is the highest for any silicon based circuits, while 140-GHz is th e highest fundamental frequency in silicon. Using push-push architecture, a 280-GHz VC O in 90-nm CMOS should be possible. Given that the state of art is 65-nm, gene ration of THz signals using CMOS technology cannot be far in the future. Table 5-2 compares the characteristics of recently published millimeter-wave fundamental VCO’s implemented using silicon technologies. The 59-GHz VCO Ref -50 dBm Norm Log 10 dB/ LgAv V1 S2 S3 FC A AA £ ( f ): FTun Swp Center 191.369 GHz Span 1 GHz #Res BW 1 MHz VBW 1 MH z #Sweep 2.53 ms (1025 pts) Mkr1 191.370 GHz 1

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106 implemented in the 0.13m bulk CMOS process has almost comparable phase noise and tuning range as that implemented in a 90-nm SOI CMOS process [60]. This work also shows that with optimized design, a mu ch higher VCO operating frequency can be attained. As a matter of f act, the 105-GHz VCO in 0.13m CMOS has a higher operating frequency than the one fabricated in a 90-nm technology [56]. This work has also shown that even at 100 GHz, lumped elements which should occupy a smaller area than the components based on tr ansmission lines can be used. Table 5-2 Comparison with recently reporte d high speed fundamental mode VCO’s in silicon technologies. Ref Freq. Phase Noise Vdd Pdc Tuning Technology 59 -89@1MHz 1.5 9.8 5.8 90 -104@10MHz 1.5 7.5~16 2.2a 98.5 -102.7@10MHz 1.5 7~15 2.5a 105.2 -97.5@10MHz 1.2 7.2 0.2 0.13m CMOS 110 -105.2@10MHz 1.5 18 2.4a 123 -100.2@10MHz 1.35 13.5 1.6a This work 140 -93@10MHz 1.2 9.6 1.2a 90-nm CMOS [53] 50 -100@1MHz 1.3 13 1.0 0.25m CMOS [54] 51 -85@1MHz 1.0 1 1.0a,b 0.12m CMOS [55] 40.7 -89@1MHz 1.8 11.3 6.0 0.13m SOI -85@10MHz 1.5 45 N/A [56] 103.9 -94@10MHz 1.5 180 N/A 90-nm CMOS [60] 60.6 -90@1MHz 1.5 21 8.3b 90-nm SOI [61] 85.8 -97.5@1MHz 3 25.8 2.3 0.12m SiGe [62] 43 -91@1MHz 1.0 7 1.7 0.13m CMOS 117.2 N/A 2.5 25-70 3.7a [63] 114.5 N/A 2.5 N/A 8.7 0.25m SiGe 80.6 -97@1MHz N/A 1200c 6.7 [64] 100.2 -90@1MHz N/A N/A 6.2 0.35m SiGe a The bias conditions of the transistor s are changed to increase tuning range. b The tuning voltage is higher than supply voltage. c Higher power consumption is due to the powerfu l output buffer and large output power level.

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107 CHAPTER 6 50-GHz CMOS PHASE-LOCKED LOOP 6.1 Introduction Millimeter-wave band VCO’s have been demonstrated in CMOS. However, no CMOS phase-locked loops (PLL’s) operating in the millimeter-wave band have been reported. The existing PLL’s operating at fr equencies above 50 GHz are based on III-V [86] or SiGe bipolar technol ogies [87]-[89]. Besides the VCO, the other challenging circuit block in the PLL is the high speed frequency divider. The dynamic frequency divider [13] could poten tially be faster than the static divider. However, dynamic divider usually consumes much more power, which ma kes it not attractive. To obtain high speed with low power consumption, an LC-resonato r based injection lock ed frequency divider (ILFD) is proposed [90], [ 91]. However, the ILFD us ually shows much narrower operating frequency range compared with other di viders. To utilize an ILFD in a PLL, the operating frequency range must be extended and the method to accomplish this is presented in this chapter. In addition, a 50-GHz phase-locked loop implemented in the UMC 0.13m CMOS process is presented. The PLL can be lock ed from 45.9 to 50.5 GHz and output power level is around -10 dBm. The circuit including buffers cons umes 57 mW from 1.5/0.8 V supplies. The phase noise at 50 kHz, 1 MHz a nd 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The P LL also outputs -22-dBm second order harmonic frequencies between 91.8 and 101 GHz. Section 6.2 describes the fundamental theory of

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108 the charge-pump PLL. Section 6.3 discu sses the high frequency ILFD design. The measured results of 50-GHz PLL are presented in Section 6.4. 6.2 Fundamental of Phase-Locked Loop 6.2.1 Basic Phase-Locked Loop A phase-locked loop is a feedback control system that operates on the excess phase instead of the voltage of the output signal. Shown in Figure 6-1 is a simple PLL, which consists of a phase detector (PD), a loopfilter, a VCO and a frequency divider (1/N) [92]-[94]. The PD detects the phase differen ce between feedback si gnal and input single, and the feedback loop minimizes this differen ce. The loop is considered “locked” if the phase difference is constant with time. Duri ng the locked condition, the phase detector produces an output proportio nal to phase difference The loop filter is a low-pass filter that suppresses high-frequency component in the PD output and allows the DC value to pass and control the VCO frequency. The i nput reference frequency and the divider output frequency are equal and the PLL output frequency is ex actly N times of the input frequency. Figure 6-1 Basic phase-locked loop The most popular phase-detector is a char ge-pump phase-frequency detector (PFD). The PFD can detect both phase and freque ncy differences. It provides a frequencysensitive signal to aid acquisition when the l oop is out of lock. The charge pump is so Phase Detector Loop Filter VCO Frequency Divider x ( t ) y(t)

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109 named because it delivers charge to the loop fi lter with the amount of charge proportional to the phase error. 6.2.2 Phase Frequency Detector and Charge Pump Figure 6-2 shows a block diagram of the PF D. The circuit consists of two D flipflops with reset control. Both the D inputs of flip-flops are conn ected to logic ONE. Signals A and B are two clock inputs. When0 B AQ Q, a rising edge on A causes1 AQ. A subsequent rising edge on A does not affectAQ, until a rising edge on B sets 1 BQ and resets both flip-flops through an AND gate. 1 B AQ Q for a short period of time which is the total delay of the AND gate and reset path. Figure 6-2 shows the input and output waveforms of the PFD. If the frequency of input A is higher than B, then the PFD generates positive pulses atAQ, and vice versa. If the frequencies are equal, PFD generates pulses at either AQ or BQ with a pulse width equa l to the phase difference of two inputs. Figure 6-3 shows the input-out put characteristic of the PFD. The linear operating range is 4 radians. Figure 6-2 (a) Phase frequency detector block diagram and PFD input/output waveform with (b) fA > fB, (c) A lagging B DFF D Q C K DFF D Q C K A B Reset ONE ONE QAQB A B QAQB ( b ) A B QA QB (c) (a)

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110 Figure 6-3 PFD transfer function Figure 6-4 Charge pump with phase/frequency detector The PFD outputs drive a three-state char ge pump as shown in Figure 6-4. The charge pump consists of two current s ources and two switche s. The switches are controlled by the two PFD outputs. If B A or A leads B, positive pulse on AQ turns on the UP switch to deliver charges to pC with the amount of charge equals to the charge pump current pI times the AQ pulse width. If B A or A lags B, the positive pulse on BQ turns on the DN switch to removes charges frompC. In the third state, when 0 B AQ Q, both UP and DN switch are open, th e charge pump output remains high impedance and the charges on the capacitance pC are kept constant. +2 -2 Vout PFD QAQBA B UP DN Cp IPIP

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111 6.2.3 Linear Model Figure 6-5 shows the block diagram of ch arge-pump PLL. Because of the switching operations of charge-pump, the PFD and charge -pump work as discrete-time circuits and the whole PLL is a time-varying system. A simple transfer function analysis is not directly applicable to this system. However, if the loop bandwidth is much smaller than the reference frequency, the VCO control vo ltage changes by a very small account during each cycle of the reference signal. The changes in a single cycle becomes unimportant, while the average behavior over many cycles is of relevance and the li near analysis using transfer functions can be applied as in the continuous-time systems. Figure 6-5 Charge-pump PFD PLL block diagram Figure 6-6 shows a block diagram of PLL with s-domain transfer functions for each block. For an ideal VCO, the output freque ncy is a linear function of control voltagectrlV, ctrl VCO FR outV K (6-1) whereVCOK is called the VCO gain. Treating a VCO as a linear time-invariant system, with the control voltage as input and excess phase dt V K tctrl VCO out) ( as output, the VCO transfer function is PFD Loop Filter VCO Frequency Divider x(t) y(t) Charge Pump

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112 s K s VVCO ctrl out (6-2) Using the continuous-time approximation, the charge pump average error current over a reference cycle is 2 / /e p p p dI T t I i (6-3) where pI is the charge pump current, pt is the charge pump curre nt pulse width due to a phase error e between reference and divider outpu t. The charge pump gain can be expressed as 2 / /p e dI i (6-4) ) ( s ZF is the transfer function of loop filter and it will be discussed in the next part. Since frequency divider divides the phase by N, its transfer function is 1/N, which can be considered as the feedback coefficient. Figure 6-6 Linear model of charge-pump PFD PLL From the linear model in Figure 6-6, the open-loop and close-loop transfer functions of PLL can be expressed as, s K s Z I s HVCO F p OL ) ( 2 ) ( (6-5) ZF(s) KVCO/s 1/N ref(s) + Ip/2 PFD and CP Loop Filter VCO Divider out(s) div(s)

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113 N s K s Z I s K s Z I s H N s H s HVCO F p VCO F p OL OL CL1 ) ( 2 1 ) ( 2 ) ( 1 1 ) ( ) ( (6-6) The loop transfer function is s K s Z I N s H N s TVCO F p OL ) ( 2 1 ) ( 1 ) ( (6-7) 6.2.4 Loop Filter and Frequency Response A passive second-order loop filter that can be used in a PLL is shown in Figure 6-7. The loop filter input is the charge pump current pI and the output voltage ctrlV is connected to VCO control voltage. For the second order loop filter in Figure 6-7, the transfer function is p z p z z z z z z p p ctrl FC C C C sR s C sR sC R sC s I s V s Z 1 1 // 1 (6-8) Figure 6-7 Second-order passive loop filter Inserting Equation (6-8) into Equation (6-7), the PLL loop transfer is p z p z z z z VCO pC C C C sR s C sR N s K I s T 1 1 2 ) ( (6-9) The open loop transfer function has two poles at the origin, which indicates the chargepump PLL with a second-order loop filter is a third-orde r type II loop [28]. Figure 6-8 Rz Cp Cz Ip Vctrl

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114 shows the bode plot of a th ird-order charge pump PLL loop transfer function. As an indicator for the stability of a negative feedb ack system, the phase margin is defined as the phase difference between -180 and the ac tual phase angle of the loop transfer function at unity gain frequency,t as shown in Figure 6-8. Like most feedback systems, phase margin of 60 or more is preferred. Figure 6-8 Bode plot of th ird-order charge pump PLL 6.2.5 Phase Noise in the Loop The phase noise at the PLL output comes from the reference, VCO, frequency divider, PFD, charge pump and loop filter, as shown in Figure 6-9. The PLL operates as a low-pass filter for the noises from PFD, CP a nd divider, a band-pass filter for the noise from loop filter, and a high-pass filter for th e noise from VCO. Therefore, for a thirdorder charge pump PLL, the phase noise spectrum has a sh ape similar to Figure 6-10. |T(s)| (dB) log -40dB/dec -40dB/dec -20dB/dec z p log Phase[T(s)] (degrees) -90 -180 Phase Margin t

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115 Within the loop bandwidth, the phase noises from reference and fr equency divider are dominant and outside the l oop bandwidth, the noise from VCO is dominant. More discussions on the noise cont ribution of the each component in a PLL can be found in [28], [94]. Figure 6-9 PLL block diagram with noise sources Figure 6-10 Output phase noise plot of a third order charge pump PLL 6.3 High Frequency Injectio n-Locked Frequency Divider The VCO output frequency will be pulled aw ay if a continuous wave signal at a different frequency is nearby. This ph enomenon is called VCO injection pulling. ZF(s) 1/N + Ip/2 PFD and CP Loop Filter Divider div(s) out(s) + n,div + KVCO/s n,LF + n,ref n,VCO + n,PFD,CP + ref(s) VCO VCO Reference (@ input) Reference Divider L( ) (dB) 20Log N Phase Noise of PLL Output

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116 Injection pulling is especially an undesired effect in direct conversion transceiver, where the PA is running at the same frequency as the VCO. Howeve r, it can be exploited to realize an ILFD. Figure 6-11 Simplified model of the injection-locked frequency divider An LC oscillator based injection-locked frequency divider can be modeled as shown in Figure 6-11. From the basic mixer theory,out in LO in outf f f f f so that, in outf f2 1 i.e. the input is divided by half. The ba ndpass filter is needed to reject all the undesired spurious outputs of the mixer. It should also be noted that by carefully controlling which harmonic is generated, hi gher divider ratio can be achieved. For instance, the mixer may genera te the third or higher orde r inter-modulation product, i.e. out in LO in outf f f f f3 3 so that out inf f4 This way a divided-by-4 operation is accomplished. The LC oscillator based ILFD was first proposed as that in Figure 6-12 and used in a 5-GHz frequency synthesizer [90], [91]. In this divider, the transistors, M1 and M2, serve as the mixer. The signal is injected to the mixer input node (sources of M1 and M2) from the tail current transistor. The LC tank serves as the bandpass filter. However, this topology is not suitable for high frequency operation beca use the sources of crosscoupled transistors and the drain of tail cu rrent transistor contribute relative large H( ) f in f ou t f ou t f LO=fout

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117 capacitance (Cp in Figure 6-12). Thus, at high frequenc ies, most of the AC current flows to this capacitor instead of the oscillator core. From [95], a 50 -GHz divider like this only achieves an 80-MHz input frequency range. Figure 6-12 Schematic of the ILFD with signal injected from the tail current transistor To obtain a wider frequency range, it should be better to inject the signal directly into the LC-tank. Figure 6-13 shows the topology of this kind of divider, where the signal is injected to the gate of M3, which is connected to the VCO core. This input signal is summed with the oscillating out puts of injection-locked divi der. The nonlinearities of M1 and M2 generate inter-modulation pr oducts which allow sustained oscillation at a fraction of the input frequency. The measured fre quency range of a 55-GHz ILFD is about 3.3 GHz [96], which is more than 40 times of the one in [95]. Compared to D-flip-flop based static fr equency dividers, the LC resonator based injection-locked frequency divider can opera te at much higher frequencies. However, even using the topology in Fi gure 6-13, an ILFD still ha s a much narrower operating frequency range compared to static frequenc y dividers, whose range could be more than 80% of the maximum operating frequency. In order to further extend the locking range, M1 M2 L1L2Vbias Vtune 2f0 f0 f0 Cp

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118 the ILFD is designed so that its tank resona nt frequency tracks that of the VCO. As shown in Figure 6-14, MOS va ractors are used to tune the ILFD’s self-oscillation frequency. Its control voltage (Vtune in Figure 6-14) is tied to the VCO control voltage. Thus, the self-oscillation frequency of ILFD tracks that of the VCO [91]. The selfoscillation frequency of ILFD should be around half of the VCO frequency. If for some values of Vtune, the self-oscillation frequency of ILFD were too far away from the half of VCO frequency, then the VCO will fail to lock the ILFD and the loop will fail to lock. Figure 6-13 Schematic of the injection-locked frequency di vider with the input signal directly injected to the core transistor The output frequency of injection-locked divider is around 25 GHz. At this frequency range, a static frequency divi der can be used. In addition to the much wider frequency range, it occupies a much smaller area. A 1/512 static frequency divider is built using the D-flip-flop architecture discusse d in Section 3.2. It consists of 9 divide-by-2 stages. To have sufficient margins, the transistors widths in the first dividedby-2 stage are increased by 50% and it consumes about 40% more power than that described in Section 3.2. M1 M2 M4 L1L2Vbias Vdrain VTune 2f0 f0 f0 M3

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119 Figure 6-14 Schematic of the VCO and ILFD in the 50-GHz PLL 6.4 50-GHz Phase-Locked Loop 6.4.1 Loop Overview Figure 6-15 Block diagram of the 50-GHz phase-locked loop Figure 6-15 shows the block diagram of a 50-GHz PLL. It includes a 50-GHz VCO, an ILFD, a 1/512 static frequency divider, a phase frequency detector (PFD), a charge pump (CP), and a low pass filter (LPF). The reference frequency for the PLL is between 45 and 49 MHz. To achieve even higher operating frequency, the 50-GHz VCO also provides a second harmonic around 100 GHz. The loop bandwidth is around 500 kHz. The resistor in the LPF is formed using non-silicided polysilicon and the capacitors are formed using MOS capacitors. To static frequency divider f0 2f0 Vtune Vb1 Vb2 V b3 T1 10pF 2 (ILFD) 512 PFD Charge Pump f0 2f0 fREF Loop Filter 24 pF 520 pF 8 k

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120 6.4.2 Measurement Results The chip was fabricated in the UMC 0.13m logic CMOS process with eight metal layers. Figure 6-16 shows the micrograph of the chip. The chip size is 1.16 x 0.75 mm2 including bond pads. The PLL was tested on-wafer and the output was measured using an Agilent E4448A 50-GHz spectrum analyzer. An Agilent E8254A signal generator is used to provide a -10-dBm si ne-wave frequency refe rence signal around 50 MHz. The second order harmonic near 100 GHz is measured using an Agilent 11970W harmonic mixer. Figure 6-16 Microgra ph of the 50-GHz PLL The VCO is biased at 1.5-V VDD and 12-mA bias current Figure 6-17 shows the output frequency range of VC O. The VCO can be tuned over 4.75 GHz from 45.85 to 50.6 GHz. The output power level is about -10 dBm and phase noise of free running VCO is about -90 and -109 dBc/Hz at 1MHz and 10-MHz offsets from the carrier, respectively. The ILFD is measured at 1.5-V VDD and 10-mA bias curren t. The self-oscillation frequency of ILFD varies from 23 to 25.1 GHz, which is slightly less than a half of the f0 2f0 VCO ILFD 512 PFD & Charge Pump Loop Filter fREF

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121 tuning range of VCO. If the tank is not tuned, the measured input lo cking range of ILFD is 1.8 GHz when driven by the VCO on the sa me chip. By tuning the ILFD along with the VCO, the ILFD can be made to operate over the entire tuning range of VCO. Figure 6-17 also shows the minimum and maximum input fre quencies to lock the ILFD. It should also be noted that the frequencies of VCO and ILFD are slightly affected by the bias current. The bias conditions mentioned above are chos en to maximize the i nput frequency range. The tuning range of ILFD should be increased to the half of VCO tuning range in future designs, in order to increase the margin. The static frequency divide r is powered by a 1.5V supply and all the buffers are powered using a 0.8-V supply. Figure 6-17 Frequency range of VCO and locking range of ILFD The PLL can be locked from 45.9 to 50.5 GHz while consuming 57 mW from 1.5/0.8 V supply. The frequency range can be extended to 51 GHz, if the supply voltage for charge pump is increased. Figure 6-18 shows the measured output spectrum at 46.2 GHz, after the cable and probe losses are de-embedded. The loop bandwidth is around 500 kHz. Figure 6-19 shows the phase noise plot of the PLL from 2 kHz to 20 MHz. The V tune ( V ) Frequency (GHz) 45 46 47 48 49 50 51 52 0.00.51.01.5 VCO output frequency Min. input frequency of ILFD Max. input frequency of ILFD

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122 Figure 6-18 Close-in out put spectrum of the PLL Figure 6-19 Phase noise plot of the PLL phase noise at 50-kHz, 1-MHz a nd 10-MHz offset from the carri er is about -63.5, -72 and -99 dBc/Hz, respectively. Th e output spectrum with 200-MHz span is also shown in Figure 6-20. The spurs are about 40 dB below the carrier. At 50.5-GHz output frequency, Carrier Freq 46.2 GHz Signal Track off DANL off Trig Free Carrier Power -23.21 dBm Atten 10dB Mkr1 50.000 kHz Ref -40 dBc/Hz -63.49 dBc/Hz 10 dB / 2 kHz Frequency Offset 20 MHz 1 Ref -10dBm Norm Log 5 dB/ LgAv V1 S2 S3 FC A AA £ ( f ): FTun Swp Mkr1 46.198 377 1 GHz Center 46.198 375 GHz Span 5 MHz #Res BW 51 kHz VBW 5 Hz #Sweep 15 s (2401pts) 1

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123 where the VCO gain is higher, the spurs b ecome stronger and they are only about 27 dB below the carrier. Figure 6-17 shows the cont rol voltage of VCO when the reference signal frequency is changed from 45 to 49 MHz, while the PLL output frequency is changed from 46 to 50 GHz. The measur ed settling time of PLL is about 40 s. Figure 6-20 output spectrum of the PLL with 200-MHz span Figure 6-21 The PLL settling time is around 40 s for a 4-MHz reference frequency step Time (us) Voltage (V) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -100-80-60-40-20020406080100 Center 46.192 400 GHz Span 200 MHz Res BW 1 MHz VBW 510 Hz #Sweep 3.12 s (1201pts) 39.39 dBc40.70 dBc Ref 0dBm Norm Log 10 dB/ LgAv V1 S2 S3 FC A AA £ ( f ): FTun

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124 The second order harmonic output freque ncy varies from 91.8 to 101 GHz. The measured output power is about -22 dBm at 101 GHz af ter all the losses in the measurement setup are de-embedded. Figur e 6-22 shows the spectrum of push-push output at 101 GHz. The cente r frequency is exactly 211 times of input reference frequency. The output power is about 5 dB lower at 92 GHz. This frequency dependence is probably due to the frequency response of transmissi on line matching network at the push-push node. Figure 6-22 The output spectrum of push-push node at 101 GHz. 6.5 Summary A 50-GHz phase-locked loop is demons trated using the UMC 0.13-m CMOS. The operating frequency range of injection locked divider is extended by tracking the VCO output frequency. The l oop can be locked from 45.9 to 50.5 GHz, and the power consumption is 57 mW. This PLL also outputs ~-22-dBm second order harmonic at frequencies between 91.8 and 101 GHz. Table 6-2 compares the performance of th is PLL with those of the previously reported SiGe PLL’s using static frequency dividers, as well as that using an ILFD [89]. Ref 0dBm Norm Log 10 dB/ LgAv V1 S2 S3 FC A AA £ ( f ): FTun Center 101.000 000 GHz Span 220 MHz Res BW 1 MHz VBW 1 kHz #Sweep 95.3 ms (601pts) Mkr1 101.000 000 1

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125 Table 6-1 Summary of the PLL Performance Locked frequencies 45.9 – 50.5 GHz (fundamental) 91.8 – 101 GHz (second harmonic) Phase noise -63.5 dBc/Hz @ 50 kHz offset -72 dBc/Hz @ 1 MHz offset -99 dBc/Hz @ 10 MHz offset Output Ppower -10 dBm (fundamental) -27 to -22 dBm (second harmonic) Settling time < 40 s Spurs -40 to -27 dBc Supply voltage 1.5/0.8 V Power dissipation 57 mW VCO 12 mA x 1.5 V ILFD 10 mA x 1.5 V Static divider 8 mA x 1.5 V PFD & CP < 1 mW Buffers 14 mA x 0.8 V Die area 1.16 x 0.75 mm2 Technology UMC 0.13m logic CMOS Table 6-2 Comparison to the previ ously reported SiGe HBT PLL’s This work [87]1 [88] [89] Technology 0.13m CMOS0.4m SiGe0.25m SiGe 0.12m SiGe Freq. [GHz] 45.9 – 50.5 36 – 45.5 54.5 – 57.8 51.4 – 54.5 Pout [dBm] -10 -16 to -12 > 0 N/A Power consumption 57 mW 650 mW 650 mW N/A Spurs [dBc] -27 to -40 N/A < -50 N/A Settling time 40 S < 300 S N/A N/A 50 kHz offset -63.5 N/A -58 -58 1MHz offset -72 -79.51 -722 -80 1 20-GHz fundamental frequency, not all parts integrated on-chip, phase noise is for a free running VCO with a frequency doubler. 2 750 kHz offset from the carrier. It achieves similar phase noise performance as the SiGe bipolar PLL’s. The SiGe PLL’s using static frequency dividers consume 650 mW [87], [88], wh ich is more than ten times that of the CMOS PLL. The SiGe PLL using an ILFD [89] also consumes significantly lower power than those using static fre quency dividers. Unfortunately, the accurate

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126 power consumption number is not available for compar ison. The maximum operating frequency of PLL proposed in this work is limited essentially by the maximum operating frequency of the oscillator that can be built. Given that a 192-GHz VCO can be built in the 0.13m CMOS, CMOS PLL’s operating in 100’s of GHz should be possible.

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127 CHAPTER 7 SUMMARY AND FUTURE WORK 7.1 Summary The ever increasing demand for low-cost portable devices has motivated the research on high frequency in tegrated CMOS communication circuits. This research work demonstrated a prototype of 24-GHz single chip radio for sensor network applications. The integration of an antenna on the same chip greatly simplifies the package, lowers the device cost, and makes the radio easy to use. Our work also has shown that it is possible to implement m illimeter-wave applications with reasonable performance and power consumption using CMOS technology. These millimeter-wave integrated circuits can be used for high data rate communications THz detection, and others. The transmitter chain includes an MSK-lik e modulator, an IF amplifier, an upconversion mixer, drivers and a power amplif ier. A discrete approximation of the MSK using phase interpolation simplifies the modulator design and lowers the power consumption. A mode locking technique using positive feedback is also proposed to improve the efficiency of power amplifier. The transmitter chain implemented in the UMC 0.13m CMOS provides 8-dBm output power to a 50load and 7.7% rms EVM at 12-Mb/s data rate, while dissipating 100 mW power. The signal transmitted by the chip with an on-chip antenna was picked up 5 meters away usi ng an on-chip antenna, and 95 meters away using a horn antenna. These demonstrations indicate that wireless communications over air using onchip antennas is possible.

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128 Frequency sources for future millimeter-wave applications are also studied in this dissertation. The transistors, varactors, and inductors are op timized to reduce the parasitic capacitances. The components were utilized to realize wide tuning range 60-GHz oscillators as well as VCO’s operating around 140-GHz in the UMC 90-nm process. Push-push architecture is util ized to obtain an operation frequency of 192 GHz in the UMC 0.13m CMOS. This is the highest opera ting frequency for any silicon based circuits. With more advanced CMOS processes, it should be easy to extend the operation frequency into the sub-millimeter or THz ra nge. A PLL tunable from 45.9 to 50.5 GHz is also implemented in the UMC 0.13m CMOS process. The power consumption is reduced to 57 mW by using an LC-oscillato r based injection lock ed frequency divider (ILFD). These results indicate the feasibility of implementing millimeter-wave systems using low cost CMOS technology. 7.2 Suggested Future Work A transmitter chain and millimeter wave circ uits have been implemented in this work. The main challenge beyond this is impr oving the circuit performance to meet real system requirements. Suggested futu re work includes the following. Evaluation of the improved transmitter chain and integrated transceiver. The biggest concern for the transmitter chain is th e harmonic emissions are higher than F.C.C requirements. An improved transmitter chai n with notch filters and better modulation scheme has been designed and submitted for fa brication. A frequency synthesizer is also integrated on the same chip. The VCO pulling issue due to the on-chip power amplifier also needs to be carefully investigated.

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129 Improving operating frequency of millimete r-wave circuits and building oscillators in THz range. In this work, a fundamental mode oscillator around 140-GHz and a pushpush oscillator close to 200GHz have been successfully demonstrated. The frequency limit of the oscillators has been studied. With the continuous MOS tran sistor scaling, as well as improved design, it should possible to build oscillators at higher operating frequencies. For instance, it should be possi ble to build a fundam ental oscillator above 200-GHz or a push-push VCO ope rating above 400-GHz using a 65-nm CMOS process. However, with device scaling, the contact/via area decreases and the resistance increases very fast. For instance, the t ypical contact resistances are 7 15 and 45 in 0.13m, 90-nm and 65-nm process, respectively. The hi gher contact resistance increases the gate resistance and lowers fmax of the transistor, thus li miting the maximum operating frequency of oscillators. Improve the performance of the millimeter-wave frequency sources. Millimeterwave oscillators and phase-locked loop have b een successfully demonstrated in this work. However, the performance may not be acceptabl e in real applicati ons. For instance, the output power of oscillators around 100-GHz is much lower than those implemented in III-V and SiGe bipolar processes. The phase noise of the oscillators and the phase-locked loop also should be improved.

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130 APPENDIX A DEFINITION OF ERROR VECTOR MAGNITUDE Error vector magnitude (EVM) is often used to specify the modulation accuracy of transmitted signals in the presence of impairment s. In the vector modulation, digital bits are transferred onto an RF carrier by varying the carrier’s magnitude and phase such that, at each data clock transition, the carrier occu pies any one of severa l specific locations on the I/Q plane. Each location encodes a specific data symbol, which consists of one or more data bits. The EVM is a measure of the difference between the ideal location and the measured results. Figure A-1 Error vector magnit ude and related quantities. Figure A-1 shows EVM and several relate d terms. The rms EVM, rms magnitude error and average phase error are defined as 2 1 2 11 1 N i i i i N i i iv v w N v e N EVM (A-1) Ideal symbol location Measured symbol location Error Vector Phase Error Magnitude Error v w e

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131 N i i i iv v w N Error Magnitude1 21 (A-2) N i i iv w N Error Phase11 (A-3) Where,iw,iv,andie are the measured vector, ideal v ector and error vector in the I/Q constellation plane. EVM is the scalar di stance between the end points of actual and intended phasor. The error vector, ie consists of anything that causes a displacement of the symbol from the intended state, thus it ca n also be treated like the noise. Since, SNR is the ratio of signal power and noise power, SNR can be approximated from EVM by EVM SNR log 20 (A-4)

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132 APPENDIX B DERIVATION OF UNITY POWER GAIN FREQUENCY The unity power gain frequency, fmax, was first explicitly defined by P. R. Drouilhet in 1955 as a figure of merit of transistor [97]. Later, Thornton and Glasser [99]-[102] proved that “no such network, regardless how cleverly constructed, can have pure sinusoidal natural frequenc ies of oscillation above fmax” [100]. The computation of the unity power gain frequency, fmax, is generally difficult, so several simplifying assumptions are used to make an approxima te derivation possible [29]. Figure B-1 shows the simplified transistor models using in the calculation of fmax. Figure B-1 Simplified transistor model The power delivered to the input is ) 5 /( 12m g in ing R i P (B-1) where the current consumption of 1/gds through Cgd is not included. As, Eq. 5-2, the magnitude of short circuit current can be obtained by the same expression used for the computation of T: T in di i (B-2) Rg Cgd Cgs 1/gds gmVgs S D G Cdb Vgs Rdb Ri=1/(5gm)

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133 The output impedance can be calcula ted by applying a voltage source (Vx) at the drain of the transistor, as shown in Figure B-2. Due the voltage divider network of Cgd and Cgs, the voltage across th e gate-to-source is x gd gs gd gsV C C C V (B-3) Here the gate resistor and channel resistor are not incl uded for simple expression. Therefore, the input current is x gd gs gd gs gs gd gs gd m gd gs x x ds gs m xV C C C C j g C C C g C j C j V V g C g I ) ( 1 ) /( 1 ) /( 1 (B-4) It is straight forward to s how that output impedance is ) ( 1gd gs gd gs gs gd gs gd m x x outC C C C j g C C C g V I g (B-5) and its resistive part of out put impedance is roughly ds gd T ds gs gd gd m outg C g C C C g g ) Re(. (B-6) Figure B-2 Calculation of the output impedance of MOS transistor Cgd Cgs 1/gds gmVx D G Vgs Vx + S Ix

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134 Here, the effects of gate resistance and the series resistance of Cdb are not included. In Figure B-3, if the conjugate termination ha s a conductance of this value then the power gain will be maximized, with half of the short circuit current goi ng into the conductance of the termination. Thus, the maximum power delivered is ds gd T in T out d in Lg C i g i P P 1 4 1 ) Re( 1 4 12 2. (B-7) Figure B-3 Maximum power delivery us ing complex conjugate termination Then, the maximum power gain is, ds gd T m g T m g in ds gd T in T m g in out d in Lg C g R g R i g C i g R i g i P P ) 5 /( 1 ( 4 ) 5 /( 1 ( 1 4 1 ) 5 /( 1 ( ) Re( 1 4 12 2 2 2 2 2. (B-8) This power gain has a value of unity at the frequency given by gd T ds m g TC g g R f ) 5 /( 1 2 2max max (B-9) It is clear that max depends on the gate resistance, so it is more comprehensive in this regard than T. Because a good layout can reduce ga te resistance to a small value, max can be considerably larger than T, especially in deep submicron CMOS processes. The Zin Re(gout) id D G S Im(gout) -Im(gout) Re(gout) transistor load 0.5 id

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135 output capacitance Cdb has no effect on max, because its series resistor Rdb is not included in our derivation, so that, Cdb can be tuned out with a lossless inductance. If Rdb is considered, the resistive part of the output impedance is 2 2 21 ) /( 1 1 Re ) Re(db db db db ds gd T db db ds gs gd gd m outC R C R g C C j R g C C C g g (B-10) and the maximum power gain becomes smaller, 2 2 2 2 2) ( 1 ) 5 /( 1 ( 4db db db db ds gd T m g T in LC R C R g C g R P P (B-11) As a consequence, the unity power gain frequency will be lower than Eq. B-9.

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145 BIOGRAPHICAL SKETCH Changhua Cao was born in Dongtai, Jiangs u Province, China, on November 26, 1980. He received the Bachelor of Engi neering degree with honor in Electronic Engineering from Tsinghua University, Beiji ng, China, on July 2002. He received the Master of Science degree in Electrical a nd Computer Engineering from University of Florida, Gainesville, Florida, on May 2004 and is currently a PhD degree candidate in the same department. Since 2002, He has been With Silicon Microwave Integrated Circuits and Systems (SiMICS) research group, ECE Department, University of Florida. His research focuses on CMOS transmitter and frequency source design at the high microwave and millimeter-wave frequencies. He received the Analog Device outstanding student designer award in 2006.


Permanent Link: http://ufdc.ufl.edu/UFE0015638/00001

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Title: A 24-GHz Fully-Integrated CMOS Transmitter with On-Chip Antenna
Physical Description: Mixed Material
Copyright Date: 2008

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Permanent Link: http://ufdc.ufl.edu/UFE0015638/00001

Material Information

Title: A 24-GHz Fully-Integrated CMOS Transmitter with On-Chip Antenna
Physical Description: Mixed Material
Copyright Date: 2008

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Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
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A 24-GHZ FULLY-INTEGRATED CMOS TRANSMITTER WITH
ON-CHIP ANTENNA











By

CHANGHUA CAO


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


2006




























Copyright 2006

by

Changhua Cao














ACKNOWLEDGMENTS

I would like to begin by thanking my advisor, Professor Kenneth K. O, whose

constant encouragement and patient guidance provided a clear path for my research. I

would also like to thank Dr. Robert M. Fox, Dr. John G. Harris, and Dr. William L. Ditto

for helpful suggestions and their time commitment in serving on my committee.

Much appreciation goes to Defense Advanced Research Projects Agency (DARPA),

Space and Naval Warfare (SPAWAR) Systems Center at San Diego, and Semiconductor

Research Corporation (SRC) for funding this work. My special thanks go to Albert Yen

at UMC Inc. and Geoff Dawe at Bitwave Semiconductor Inc. for chip fabrication; Eric

Schwartz at Agilent Technologies for the measurement equipment. Thanks also go to Dr.

Frederick Martin at Motorola Labs and Dr. Brian A. Floyd at IBM T. J. Watson Center

for helpful technical discussions.

I have been quite fortunate to have worked with my colleagues in the [tNode

project: Yu Su, Yanping Ding, and Jau-Jr Lin, whose helpful recommendations,

discussions and friendship have speeded up my research. I would also like to thank my

other former and current colleagues at University of Florida for their helpful advice.

Some of their names are listed here: Seong-Mo Yim, Dong-Jun Yang, Li Gao, Zhenbiao

Li, Xiaoling Guo, Ran Li, Xiuge Yang, Ashok K. Verma, Haifeng Xu, and Chi-Kuang

Yu.

I am most pleased to acknowledge the love and encouragement of my parents, to

whom I dedicate this work.















TABLE OF CONTENTS

page

A C K N O W L E D G M E N T S ................................................................................................. iii

LIST OF TABLES .................. .................. ................. ............ .............. .. vii

LIST OF FIGURES ................ .................. ............... ............. .... ...... viii

A BSTRA C T ..................... ................................................ ................ xiv

CHAPTER

1 IN T R O D U C T IO N ............................................................................ ................ .. 1

2 RADIO FREQUENCY TRANSMITTER ARCHITECTURE............................ 5

2 .1 In tro du ctio n ...................................... ............................................. .. 5
2.2 T w o-Steps T ransm itter............................................................. ..................... 5
2.3 Direction-Conversion Transmitter ................ ..............................................6
2.4 Overview of the [tNode Transceiver...............................8
2.4.1 Radio Frequency Subsystem Specifications ...........................................8
2.4.2 Radio Frequency Transceiver Architecture................... .....................8

3 KEY BLOCKS OF THE TRANSMITTER.......................................................... 12

3 .1 Intro du action ................... ....... ........ ......... ................. ................ 12
3.2 Power Efficient 26-GHz 32:1 Static Frequency Divider ..............................12
3.2.1 C ircuit A rchitecture..................................................... ...... ......... 12
3.2.2 E xperim ent R results ....................... ................. ............... .... 17
3.3 Low Power Wide Bandwidth Constant Envelope Modulator.........................20
3.3.1 Minimum Shift Key and Constant Envelope Modulation....................20
3.3.2 Implementation of Constant Envelope Modulator ..............................23
3.3.3 Circuit D description ..................................................................... 25
3.4 Intermediate Frequency Amplifier......................................... ............... 27
3.5 U p-C conversion M ixer ............................................... ............................ 27
3.6 High Efficiency Power Amplifier...................................... ......................... 28
3.6.1 Introduction to CMOS Power Amplifier....................................28
3.6.2 Class A, B, AB, and C Power Amplifier....................................30
3.6.3 High Efficiency Class E Power Amplifier .................. .... ........... 32
3.6.4 Circuit D description ................... ......... ......... .................... 35
3.6.5 M ode L rocking T technique ........................................... .....................37









3.6.6 Experim ent R results ........................................ .......................... 39
3.6.7 Sum m ary and Conclusions ............................................... ............... 45
3 .7 S u m m a ry ..................................................................................................... 4 6

4 WIRELESS COMMUNICATIONS USING ON-CHIP ANTENNAS ................. 47

4.1 R eview of O n-C hip A ntennas ................................................ .....................47
4.1.1 Introduction to On-Chip Antennas .....................................................47
4.1.2 Measured Performance of On-Chip Dipole Antenna.............................48
4.2 Test Transmitter with an On-Chip Antenna................................. ..............51
4.2.1 Circuit Architecture.....................................................51
4.2.2 Experiment Results ...................... ............ ...............51
4.3 Fully Integrated Transmitter with On-Chip Antenna.................... ........ 54
4.3.1 Transm itter Chain Overview ................................ ...................... 54
4.3.2 Experiment Results and Discussions....................... ............... 56
4.3.3 Up-Link Demonstration Using an On-chip Antenna ...........................62
4.4 Improved Transmitter Chain Design...................................... ............... 63
4.4.1 Im proved M odulation Schem e.......................................... ......... ......63
4.4.2 Improved Transmitter Front-End with Notch Filters ...........................64
4.5 Fully-Integrated Transceiver............................................ ............ ............... 66
4 .6 S u m m ary ...................................................... ................ 6 8

5 MILLIMETER-WAVE VOLTAGE CONTROLLED OSCILLATORS ................ 69

5.1 Overview of the Millimeter-Wave Oscillators ............ ... ......................69
5.2 MOSFET Modeling for Millimeter-Wave Design........................................71
5.2.1 Gate Resistance and Non-Quasi Static Effect................... .......... 71
5.2.2 Unity Gain Frequencies........................ .... ......................... 72
5.2.3 M OSFET Radio Frequency M odel ................................ ............... 74
5.3 M O S V aractor .......................................... ...... .. .... .. .. ........ .... 75
5.3.1 M O S V aractor Structure.............................................. ............... 75
5.3.2 Equivalent M odel ............................................................................77
5.3.3 Experiment Results and Discussions..........................................78
5.4 High Performance On-Chip Inductor ............... ......................................81
5.5 T ran sistor L ay out ............................................................ ........ ..... .... 83
5.6 C circuit A rchitecture......... ............................................... .......... ............. 85
5.7 60-GHz Wide Tuning Oscillators ............................ ..................... 86
5.7.1 Design Considerations..................... ...... .......................... 86
5.7.2 Experiment Results and Discussions..........................................87
5.8 100-GHz Oscillators in 0.13-[tm CM OS ........................ .. ....................... 89
5.8.1 Design Considerations.................. .............................. 89
5.8.2 Millimeter-Wave Spectrum Measurement Setup..............................90
5.8.3 99-GHz Voltage-Controlled Oscillator ............................................ 92
5.8.4 105-GHz Voltage-Controlled Oscillator ........................ ...............94
5.9 Oscillators Operating above 100 GHz in 90-nm CMOS .................................95
5.10 192-GHz Push-Push Oscillator................................................101
5.10.1 C ircuit D esign ........................... .............. .................. ............... 10 1









5.10.2 Experim ent R results ........................................ ......................... 103
5.11 Sum m ary and D discussions ........................................ ......................... 105

6 50-GHz CMOS PHASE-LOCKED LOOP .................................................... 107

6 .1 Intro du action ......... .......................... ...... ................................. ............... 10 7
6.2 Fundamental of Phase-Locked Loop ...................................................... 108
6.2.1 B asic Phase-L ocked L oop .............. ............. ............... ............... .108
6.2.2 Phase Frequency Detector and Charge Pump ......................................109
6.2 .3 L near M odel ............ ........ .. .............. .............. .................. 111
6.2.4 Loop Filter and Frequency Response ......... ................................... 113
6.2.5 Phase Noise in the Loop...................... ...................... 114
6.3 High Frequency Injection-Locked Frequency Divider................................1.15
6.4 50-GHz Phase-Locked Loop........................................... .......................... 119
6.4.1 Loop O overview ............................ ...... ........ ...... .......... .... 119
6.4.2 M easurement Results ....... .................. ...... ............... 120
6.5 Summary .................. ..... ................... 124

7 SUMMARY AND FUTURE WORK ..... .................... .............. 127

7.1 Summary ................ ......... .................. 127
7.2 Suggested Future Work ......... ............... ................... 128

APPENDIX

A DEFINITION OF ERROR VECTOR MAGNITUDE ........................... ........ 130

B DERIVATION OF UNITY POWER GAIN FREQUENCY............................ 132

L IST O F R E F E R E N C E S ......... .. ............................................................... .............. 136

BIOGRAPHICAL SKETCH ........... .......................................... 145















LIST OF TABLES


Table page

2-1 Link budget of the [[Node system ................................................ ....... ....... 9

3-1 Power consumption and maximum operating frequency for several recently
published 2:1 CM OS static frequency dividers. ............. .................................... 19

3-2 Comparisons of power amplifiers operating near 20 GHz ............................. 45

4-1 Summary of the 24-GHz transmitter performance ........................................... 61

5-1 Summary of the measured VCO performance ............ .................... 100

5-2 Comparison with recently reported high speed fundamental mode VCO's in
silicon technologies......................... .. .............. 106

6-1 Summary of the PLL Performance ......... ................................... ........... 125

6-2 Comparison to the previously reported SiGe HBT PLL's............................. 125















LIST OF FIGURES


Figure page

1-1 Conceptual Node system ..................................... ......... .................. 1

1-2 Typical N ode device size............................................................ ............... 2

2-1 Tw o-step conversion transm itter.................................................................. ...... 6

2-2 D irect-conversion transm itter ........................................... ........................... 6

2-3 Disturbance of the local oscillator by PA leakage ...............................................7

2-4 Direct-conversion transmitters with an offset LO .......................................7

2-5 Block diagram of simplified [[Node RF subsystem using two-step conversion
architecture .............. ...... ............. ................................. 10

2-6 Direct-conversion architecture for [[Node .....................................................10

3-1 Block diagram of the 2:1 static frequency divider.....................................13

3-2 Schematic of the 2:1 static frequency divider.......................................................14

3-3 Oscillation frequencies versus the width of the latch transistors with different
P M O S lo ad ........................................................................ 16

3-4 The operating frequencies and power consumption versus the drive transistor
w id th ........................................................... ................ 17

3-5 Micrograph of the 32:1 frequency divider........................................................18

3-6 Measured input sensitivity at different supply voltages .....................................18

3-7 Output waveform with 26GHz, 0-dBm input ................................ .................. 19

3-8 Block diagram of the MSK modulation..... ................................................. ...........20

3-9 Signals in the M SK m odulation....................................... .......................... 21

3-10 An MSK modulation example and the modulated signal's constellation (a)
MSK modulation is I-Q modulation with half sinusoidal pulse shaping (b) The
modulation generates a constant envelope constellation ....................................22

viii









3-11 Ideal constellation of modulator output. ...................................... ..................23

3-12 Simulated power spectra of the modulator output, standard MSK, and offset
Q P S K ........................................................................... 2 4

3-13 Illustration of how a phasor can be generated from two phasors in quadrature ....24

3-14 Conceptual schematic of a summing circuit ............ ................................ 25

3-15 Block diagram of the constant envelope phase shift modulator ............................26

3-16 Schematic of the phasor combining circuit........... ..... ..................27

3-17 Schematic of the IF amplifier ........... ..... .............................. 28

3-18 Schematic of the up conversion mixer...... ...................... ............28

3-19 Simplified schematic of the power amplifier ............. ..... ..................30

3-20 Transistor currents for class A, B, and C power amplifiers...............................31

3-21 C lass E pow er am plifier............................................... .............................. 33

3-22 Simplified class E stage model and its voltage and current waveform..................34

3-23 Class-E power amplifier with impedance transformation network .....................35

3-24 Schematic of the fully-integrated CMOS power amplifier...............................36

3-25 Schem atic of output stage ........................................................... .....................37

3-26 Small signal model of the common source amplifier ........................................38

3-27 Die photograph of the chip containing two single-ended power amplifiers..........40

3-28 PA m easurem ent setup................................................. .............................. 40

3-29 Output spectrum (a) unlocked, input:-42dBm (b) locked, input: -10dBm.
(Losses from the cable and connector have been de-embedded).........................41

3-30 Output power and current consumption as function of the input power for the
18 GHz pow er am plifier. (Supply voltage: 1.5 V).................................................42

3-31 PAE and drain efficiencies as a function of the input power of the 18-GHz
power amplifier (Supply voltage: 1.5 V) .................................... ............... 43

3-32 Output power and PAE as a function of the frequency of the 18-GHz power
amplifier. (Supply voltage: 1.5 V) ........................... ....... ................... 43









3-33 Output power and gain as function of the input power for the two power
am plifiers. .......................................... ............................ 44

4-1 Photograph of an on-chip antenna .............................................. ............... 48

4-2 Input reflection coefficient of a 3-mm zigzag on-chip antenna...........................49

4-3 Antennas pair measurement environment (lobby)............... ....... ............... 50

4-4 Antenna pair gain vs. distance in the lab for 3-mm zigzag antennas on a 20
f2cm, 670-[tm thick substrate with a 3-[tm oxide layer. The measurement
frequency is 24 G H z [9]............................................... .............................. 50

4-5 Block diagram of the test chip with an on-chip antenna.................... ........ 51

4-6 Micrograph of the test transmitter with an on-chip antenna..............................52

4-7 Input and output matching of the test transmitter ...............................................52

4-8 Output power as function of input power .................................. .................. ....53

4-9 Measurement setup of the 5-m wireless communication using an on-chip
antennas pair ........................................................................53

4-10 Received signal using an on-chip antenna located 5 m away .............................54

4-11 Transm itter chain architecture ........................................ .......................... 55

4-12 Schematic of the RF drivers and power amplifier ............. ................................. 55

4-13 Photograph of the fully-integrated transmitter and frequency synthesizer............57

4-14 Power consumption distribution in the transmitter chain ....................................58

4-15 Transmitter output power versus frequency .................................. ............... 58

4-16 Measured output power spectra of the transmitter around 24-GHz....................59

4-17 Masured transmitter output constellation with a 12-Mb/s data rate ......................60

4-18 Measured output power spectrum with 24-GHz span.........................................61

4-19 Reception of the signal from a transmitter IC with an on-chip antenna using a
20-dBi gain horn antenna located 95m away............ ......................................62

4-20 Modulator output spectra with different modulation steps per bit......................63

4-21 Second and third order notch filters and their characteristics.............................64









4-22 Improved transmitter RF front-end with notch filters.........................................65

4-23 Integrated transmitter and receiver RF front-end with distributed T/R switches ..67

4-24 Integration of the frequency synthesizer, transmitter and receiver...................68

5-1 Equivalent gate resistance model including distributed ploy-silicon resistance
and distributed channel resistance .............................................. ............... 72

5-2 Equivalent MOS transistor model including the gate resistance.........................72

5-3 Unity current frequency, f, and unit power gain frequency,fma, versus gate
le n g th ................................................... ................... ................ 7 4

5-4 RF model of an NMOS transistor with intrinsic and extrinsic components..........75

5-5 Top view and cross section of the MOS varactor..........................................76

5-6 Simplified M OS varactor model ................. ............................... ............... 77

5-7 Measured MOS varactor capacitance, series resistance and quality factor at 24
GHz for a varactor with 0.64-jtm width, 0.24-[tm length and 20 fingers.............79

5-8 C-V and Q-V characteristics of the MOS varactors with different gate
d im e n sio n s ....................................................... ................ 8 0

5-9 Minimum varactor Q and Cmax/Cmin ratio at 24 GHz as a function of gate length.
................................................................................................................................8 1

5-10 Differential inductor layout ............ ..... ................................. 82

5-11 Lumped inductor model of differential inductor ................................................82

5-12 Cross-coupled transistor layout............................. .... ...............83

5-13 C apacitors in the V C O .......... .................... ......... .................................. 84

5-14 Schematic of the proposed VCO....................... ............... .. ...............85

5-15 M icrograph of the 60-GH z V CO ................................................ ...... ............ ...87

5-16 Output spectrum of the 59-GHz VCO (VDD= 1.5V, Vtune= 1.5V) ........................88

5-17 Frequency range of two different VCO's using different varactor structures .......88

5-18 Phase noise of the two different VCO's as function of the tuning voltage............89

5-19 100-GHz VCO measurement setup .................................... ...............90









5-20 Simplified block diagram of measurement setup.................................... 91

5-21 Output spectrum of the 99-GHz VCO ......................................... ...... ............. 93

5-22 Measured phase noise plot of the 99-GHz VCO .............................. ...............94

5-23 Frequency tuning, current consumption and phase noise of the 99-GHz VCO at
1 .5 V V D D ............................................................................................................... 9 5

5-24 M icrograph of the 105-GHz VCO ........ ..................................................... 96

5-25 Output spectrum of the 105-GHz VCO ........................................ ... ............ 96

5-26 Photograph of the 140-GHz VCO.............. ... .......................97

5-27 Output spectrum of the 140-GHz VCO .................................................. ........... 97

5-28 Phase noise plot of the 140-GHz VCO ......................................... .. ............. 98

5-29 Output frequency versus the tuning voltage .................................. ............... 99

5-30 Output frequency versus VDD for the 110-GHz VCO......................................100

5-31 Schematic of the push-push VCO .................................................................. 101

5-32 Grounded coplanar waveguide transmission line ........................... .................102

5-33 Micrograph of the 192-GHz push-push VCO................... .............................. 103

5-34 M measured VCO output spectrum .............................................. ............... 105

6-1 B asic phase-locked loop ............................................. ............................. 108

6-2 (a) Phase frequency detector block diagram and PFD input/output waveform
with (b)fA >fB, (c) A lagging B .............. ...... ................... .............. 109

6-3 PFD transfer function..................................... ......... .................. ............... 110

6-4 Charge pump with phase/frequency detector...................................................110

6-5 Charge-pump PFD PLL block diagram....................... ......................111

6-6 Linear model of charge-pump PFD PLL ............. .................................112

6-7 Second-order passive loop filter ........... ....... ................... ............... 113

6-8 Bode plot of third-order charge pump PLL .................................... ............... 114

6-9 PLL block diagram with noise sources...................... .. ............... 115









6-10 Output phase noise plot of a third order charge pump PLL.............................115

6-11 Simplified model of the injection-locked frequency divider .............................1116

6-12 Schematic of the ILFD with signal injected from the tail current transistor ....... 117

6-13 Schematic of the injection-locked frequency divider with the input signal
directly injected to the core transistor....................................... ....... ............ 118

6-14 Schematic of the VCO and ILFD in the 50-GHz PLL..................................... 119

6-15 Block diagram of the 50-GHz phase-locked loop ......................... ............19

6-16 M icrograph of the 50-GHz PLL ......... ................................ ................... 120

6-17 Frequency range of VCO and locking range of ILFD..................................121

6-18 Close-in output spectrum of the PLL......... ............ ........... .............. 122

6-19 Phase noise plot of the PLL ........._....... ......... ................ .. ............. 122

6-20 output spectrum of the PLL with 200-MHz span ...........................123

6-21 The PLL settling time is around 40 |ts for a 4-MHz reference frequency step ...123

6-22 The output spectrum of push-push node at 101 GHz. .............. ..................124

A-1 Error vector magnitude and related quantities.................................. 130

B-l Simplified transistor m odel ........................... ..... .... .............. 132

B-2 Calculation of the output impedance of MOS transistor........... ...............133

B-3 Maximum power delivery using complex conjugate termination......................134















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

A 24-GHZ FULLY-INTEGRATED CMOS TRANSMITTER WITH
ON-CHIP ANTENNA

By

Changhua Cao

August 2006

Chair: Kenneth K. O
Major Department: Electrical and Computer Engineering

The ever-increasing demand for low-cost portable devices has motivated the

research on high frequency CMOS communication integrated circuits. We designed and

implemented a transmitter chain that will be part of a single-chip 24-GHz CMOS radio

for sensor network applications. The radio includes a RF transceiver, an on-chip antenna,

a baseband processor, a sensor, and eventually a battery. The integration of an antenna on

the same chip greatly simplifies the package, lowers the device cost to less than $1, and

makes the radio easy to use.

The transmitter includes a minimum shift key (MSK) modulator, IF amplifiers, an

up-conversion mixer, drivers and a power amplifier. A discrete approximation of the

MSK using phase interpolation simplifies the modulator design and lowers the power

consumption. A mode locking technique using positive feedback is also proposed to

improve the power added efficiency (PAE) of power amplifier to 23.5%. The transmitter

chain implemented in the UMC 0.13-[tm CMOS provides 8-dBm output power to a 50-Q









load and 7.7% rms error vector magnitude (EVM) while dissipating 100 mW. The signal

transmitted by the chain with an on-chip antenna was picked up 5 meters away using an

on-chip antenna, and 95 meters away using a horn antenna with 20-dBi gain. These

demonstrations prove that short-range wireless communications using a single-chip radio

with an on-chip antenna are possible.

Frequency sources for future millimeter-wave applications are also demonstrated.

The transistors, varactors, and inductors are optimized to reduce the parasitic loss and

capacitances. The components are used to realize wide tuning range 60-GHz voltage-

controlled oscillators (VCO's) in UMC 0.13-itm CMOS and VCO's around 140 GHz in

UMC 90-nm CMOS processes. We also used push-push architecture obtain an operation

frequency of 192 GHz in 0.13-[tm CMOS. This is the highest operating frequency for any

silicon-based circuit. Our study also showed that the lumped element approach can be

used even for circuits operating well above 100 GHz. A PLL tunable from 45.9 to 50.5

GHz was also implemented in 0.13-[tm CMOS process. The power consumption was

reduced to 57 mW by using an LC-oscillator based injection locked frequency divider

(ILFD) while the operating frequency range is increased by tracking the VCO and ILFD

self oscillation frequencies. These results indicate the feasibility of implementing

millimeter-wave applications using low-cost CMOS technology. With more advanced

CMOS processes, it should be possible to extend the frequency to sub-millimeter or THz

range.














CHAPTER 1
INTRODUCTION

Over the past 10 years, the wireless communication industry has grown explosively

and radio frequency integrated circuit (RFIC) research has received great attention. Ever-

increasing demand for monolithic, low-cost, and low-power portable devices has

motivated much research on a single-chip radio [1]. Since the baseband digital signal

processors (DSP) are being implemented exclusively using CMOS technologies, CMOS

technology offers highest level of integration and lowest cost in volume product.




OSESSOR




PROCESSOR
& SENSO


BATTERY
Figure 1-1 Conceptual [[Node system

A [[Node is a true single-chip radio incorporating an on-chip antenna, a transceiver,

a digital baseband processor, a sensor, and potentially even a battery. Including of small

antennas in an integrated circuit keeps the [[Node size small, greatly simplifies their use,

and eliminates the need for external transmission line connections and sophisticated

packaging, which can radically reduce cost of wireless systems operating above 10 GHz

[2]-[4]. Figure 1-1 shows a conceptual diagram of a [[Node. The size of [[Node device is









limited by the battery. Currently, a version with the size of an m&m (Figure 1-2) is

being developed.










Size 5A and 10


Figure 1-2 Typical |jNode device size

The version being developed using standard CMOS technology costs less than $1,

and is capable of wireless transmission and reception at 24 GHz ISM band over short

distances. The communication range is typically 1 to 5 meters, and the range can be

extended to around 30 meters at the cost of increased transmitted power and battery size.

To keep the battery small and thus the over all form factor small, power consumption

must be low. This rugged system on a chip could be so small that it is practically difficult

to be detected, and so inexpensive that it can be distributed in large numbers. Groups of

active gNodes can form self-organizing wireless communication networks. The [[Node

system can be viewed as a modified Zigbee radio operated at 24 GHz.

Our study focuses on design and characterization of a 24-GHz fully-integrated

CMOS transmitter chain. The primary goal is to integrate all components including the

antenna onto a single-chip while achieving low power consumption. The feasibility of

implementing circuits for future millimeter-wave radios and sensor networks using

CMOS technology are also studied.









Chapter 2 reviews the architecture of integrated transmitter chain and discusses

their advantages and drawbacks. The two step transmitter architecture is used in the

|jNode system, to mitigate the VCO pulling issue in a fully integrated radio.

Chapter 3 discusses the design and characterization of the building blocks in the

transmitter chain, including a static frequency divider, an MSK-like modulator, IF

amplifiers, an up-conversion mixer, RF drivers and a power amplifier. A discrete

approximation of the MSK using phase interpolation greatly simplifies the modulator

design. The efficiency of PA is crucial because it is the most power hungry block in the

transceiver. Since a constant envelope modulation scheme is used, a high efficiency non-

linear class-E PA is utilized. A mode locking technique using positive feedback is

proposed to improve the efficiency of the PA.

Chapter 4 presents wireless communications using on-chip antennas. The

characteristics of on-chip antenna are reviewed briefly and an up-converter with an on-

chip antenna is used to demonstrate the feasibility of using on-chip antennas pair for 5

meters short range communications. Then, the fully-integrated transmitter chain is

described. The transmitter is first characterized using a 50-Q load. It provides 8-dBm

output power and 7.7% rms error vector magnitude (EVM, Appendix A) while

consuming 100-mW power. The signal transmitted by the transmitter with on-chip

antenna has been picked up 95 meters away using a horn antenna with 20-dBi gain. This

uplink demonstration proves that communication between a base station and an

integrated circuit with on-chip antenna over a distance of 100 meters is possible.

Chapter 5 describes the design of CMOS millimeter-wave voltage controlled

oscillators. The high frequency characteristics of MOS transistor are discussed. The









transistor, varactor and inductor designs are optimized to reduce the parasitic

capacitances and loss. An investigation of trade-off between quality factor and tuning

range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between

0.18 and 0.24 |tm result in both good quality factor and tuning ratio in the 0.13-[tm

CMOS process. The components were utilized to realize a wide tuning range 60-GHz

VCO as well as oscillators operating above 140-GHz. A push-push architecture is utilized

to obtain frequency close to 200-GHz. The lumped element approach can be used even

for oscillators operating above 100-GHz and it results in a smaller circuit area.

Chapter 6 presents a 50-GHz phase-locked loop design. This fully integrated PLL

manufactured in the 0.13-[tm logic CMOS process is tunable from 45.9 to 50.5 GHz. It

consumes less than one-tenth of the power for the SiGe PLL's using static frequency

dividers, while achieving comparable phase noise performance. The power consumption

is reduced using an LC-oscillator based injection locked frequency divider (ILFD). The

operating frequency range is increased using a combination of an ILFD with an increased

input frequency range, and tracking the VCO and ILFD self oscillation frequencies.

Finally, this research work is briefly summarized and possible future works are

suggested in Chapter 7.














CHAPTER 2
RADIO FREQUENCY TRANSMITTER ARCHITECTURE

2.1 Introduction

Single chip radio implementation requires proper selection of radio architecture. A

RF transmitter performs modulation, up-conversion, and power amplification, with the

first two combined in some cases [5]-[7]. This chapter reviews the architectures of a RF

transmitter with an emphasis on those issues particularly challenging when attempting to

integrate all the functionalities onto a single chip. Sections 2.2 and 2.3 describe the two-

steps and direct-conversion architecture and discuss their advantages and drawbacks.

Chapter 2.4 presents the transceiver used in [tNode system.


2.2 Two-Steps Transmitter

Figure 2-1 shows the block diagram of the two-steps transmitter architecture, which

is similar to the heterodyne receiver architecture. First, the baseband I and Q channels

undergo qudrature modulation at intermediate frequency of o 1. Then, the result is up-

converted to co 1+02 by mixing and bandpass filtering. The first bandpass filter suppresses

the harmonics of the IF signal, while the second one removes the unwanted sideband,

called image, centered around 0o1-0o2.

In a two-step conversion architecture, since quadrature modulation is performed at

lower frequencies, I and Q matching is superior, leading to less cross-talk between the

two bit streams. Also, a channel filter may be used at IF to limit the transmitter noise and

spurs in adjacent channels. The difficulty in two-steps transmitters is that the bandpass








filter following the second upconversion mixer must reject the unwanted image signal

and LO leakage by a large factor, which could be more difficult when all the components

are integrated on a single chip.


WT

COSC t B P F -- P -

scosot2t

Q- j -- COSCQ2t
Figure 2-1 Two-step conversion transmitter

2.3 Direction-Conversion Transmitter

If the transmitted carrier frequency is equal to the local oscillator frequency, the

architecture is called "direction conversion." In this case, the modulation and

upconversion occur in the same circuit. Figure 2-2 shows the block diagram of a direct-

conversion transmitter.

Baseband 7

cosBct > Matching
sinc,-t Network
sinloc

Baseband
Q
Figure 2-2 Direct-conversion transmitter

The direct-conversion transmitter in Figure 2-2 provides the highest integration

level and lowest system cost, however it suffers from an important drawback called

injection pulling, that is, the transmitter local oscillator is disturbed by the output of









power amplifier (Figure 2-3). This issue arises because the PA output is a modulated

waveform with high power and a spectrum centered around the LO frequency [7]-[8].

Despite various shielding technique employed to isolate the VCO, the strong output of

PA still corrupts the oscillator spectrum. In [[Nodes, a PA is integrated along with an

antenna in the same chip as an oscillator and the PA is turned on and off periodically to

save power. This problem is expected to be even more severe.








fLO f
Q

Figure 2-3 Disturbance of the local oscillator by PA leakage


fvco=2/3*fLo


fvco=N*fLO


Figure 2-4 Direct-conversion transmitters with an offset LO









The phenomenon of LO pulling is alleviated if the PA output frequencies are

sufficient higher or lower than the oscillator frequency. For a quadrature modulation

scheme in Figure 2-2, this can be accomplished by offsetting the LO frequency. In Figure

2-4 (a), the output of VCO is first divided by 2. Then, the VCO and divider output are

mixed and the result is filtered. Therefore, the VCO frequency is 2/3 of the LO frequency.

In Figure 2-4 (b), the VCO output is divided by 2 or 4, and the frequency divider

naturally generates quadrature LO signals.


2.4 Overview of the iNode Transceiver

2.4.1 Radio Frequency Subsystem Specifications

The [[Node system operates at in the ISM band between 24 and 24.25 GHz. The

data rate is 100 kbps. Since a direct sequence spread spectrum (DSSS) technique is used,

it leads to 50 or 100 Mega chips per second. To have a low bit errors rates (BER) and

good tolerance to LO frequency drifting, the required Eb No is larger than 18 dB.

Assuming the receiver noise figure (NF) is around 8 dB, the received signal must be

larger than -98 dBm. The power gain between a pair of on-chip 3-mm zigzag antennas

with 5-meters separation is around -99 dB. To have sufficient link margin, the transmitter

output power is required to be higher than 10 dBm. Table 2-1 summarizes the key

specifications of the RF subsystem. The link margin of the system is 9 dB. The antenna

pair gain is expected to increase by about 10 dB when the substrate is thinned to -100 |tm

[9], thus, the link margin can be as high as 19 dB.

2.4.2 Radio Frequency Transceiver Architecture

Both the two-steps and direct-conversion transmitter architecture could be used for

the [[Node system. Because the PA and antenna are integrated on the same chip as the









local oscillator, the VCO pulling issue becomes worse. Thus, the two-steps transmitter

architecture is easier to implement and its performance requirements are relaxed.

Table 2-1 Link budget of the [tNode system.
Frequency Band 24 to 24.25 GHz ISM band
TX Output Power 10 dBm
Communication Range 5 m
Antenna Pair Gain -99 dB
Received Power -89 dBm
Thermal Noise -174 dBm/Hz
Date Rate (100 kb/s) 50 dB
SNR 18 dB
RX Noise Figure 8 dB
Receiver Sensitivity -98 dBm
Link Margin 9 dB


Figure 2-5 shows the two-step or heterodyne architecture of the RF subsystem. The

frequency synthesizer provides a 21.4-GHz LO signal. The intermediate frequency is 2.7

GHz, which is exactly 1/8 of the LO frequency, thus, IF signal could be generated using a

frequency divider and only one synthesizer is required. The transmitter includes a multi-

phase generator (8:1 frequency divider), an MSK-like modulator, IF amplifiers, an up-

conversion mixer, drivers and a power amplifier. The 8:1 frequency divider generates

quadrature signals for the modulator. The serial baseband digital data are directly up-

converted to IF by the modulator and the IF I/Q mixers are not needed any more. The

signal at IF is amplified and fed into a double-balanced Gilbert cell up-conversion mixer.

The RF signal is amplified by a 3-stage driver and fed to a class-E power amplifier (PA).

Finally, the PA drives a 3-mm on-chip zigzag dipole antenna.

The receiver includes a low noise amplifier (LNA), a RF-to-IF down-conversion

mixer, IF amplifiers, an IF-to-baseband mixer, an automatic gain control (AGC) unit, a

low pass filter (LPF), and an analog to digital converter (ADC).
































Figure 2-5 Block diagram of simplified [[Node RF subsystem using two-step conversion
architecture


Figure 2-6 Direct-conversion architecture for [[Node






11


The direct conversion architecture can also be used for the [[Node system. Both of

the architectures in Figure 2-4 could be used. Because it is difficult to design a good

phase shifter around 24 GHz, the architecture using a frequency divider in Figure 2-4(b)

is easier to implement. Therefore, a synthesizer running around 48 or 96 GHz is required.

The feasibility of implementing oscillators and a synthesizer at this frequency band will

be discussed in Chapter 5 and 6.














CHAPTER 3
KEY BLOCKS OF THE TRANSMITTER

3.1 Introduction

As described in Chapter 1, the key requirement for [tNode is the low power

consumption. In the design, each block must consume as low current as possible. Another

requirement for the transmitter is that the output power must be sufficient high and it

must be power sufficient. In this chapter, the design and measurement results of each

block of the transmitter are described. A power efficient 26-GHz static frequency divider

is presented in Section 3.2. A low power wide bandwidth MSK-like modulator is

discussed in Section 3.3. The IF amplifier and up conversion mixer are described briefly

in Section 3.4 and 3.5. Section 3.6 proposes a high efficiency class E power amplifier

using the mode locking technique.


3.2 Power Efficient 26-GHz 32:1 Static Frequency Divider

3.2.1 Circuit Architecture

High speed frequency dividers are critical in a variety of applications from

frequency syntheses in wireless communications to broadband optical fiber

communication systems. As shown in Figure 2-5, in the transmitter a 21.4 GHz frequency

divided-by-8 circuit is required for I/Q modulation. These applications require high speed,

low power, high sensitivity and monolithic integration.

To date, the highest operating frequencies for frequency divider have been achieved

with bipolar and III-V technologies, though their power consumption are high [10], [11].









Compared to the bipolar and III-V dividers, CMOS ones usually operate at lower

frequencies. To increase the operating frequency at given power consumption, several

techniques are used, such as injection locking [12], dynamic circuit [13] and improved

Miller divider [14]. Compare with them, a static one has a much wider operating range

and moderate operating frequency and power consumption. CMOS static frequency

dividers operating around 20 GHz have been recently reported [15]-[19], but the power

consumption is too high (usually higher than 25 mW for 25-GHz operation).




D Q D Q OUT

Db Qb- Db Qb OUTb


CK
CKb

Figure 3-1 Block diagram of the 2:1 static frequency divider

Figure 3-1 shows the block diagram of 2:1 current mode logic (also known as

source-coupled logic) static frequency divider [20]. The divider is based on the classical

master-slave D-type flip-flop in which the inverted slave outputs are connected to the

master inputs. The differential nature reduces the switching noise and provides sufficient

noise margin. The divider inputs (CK and CKb) are usually also terminated with 50-Q

resistors (not shown) to make the amplitude of input signals more predictable. As shown

in Figure 3-2, each master-slave flip-flop is implemented using CML. The master and

slave stages consist of an evaluate stage (M1,3,4) and a latch stage (M2,5,6). The current

sources in conventional CML latches are omitted [15] for low voltage operation. This

causes the total current flowing through the evaluation and latch stages to fluctuate in









time, which may potentially generate larger switching noise. However, at high

frequencies, there is big overlap when both the evaluation and latch stages are turned on,

which makes the supply current relatively constant. Therefore, the switching noise is

limited. That is also verified by the simulation.
r ---------------------------- r-----------------------------


(M7 M8

OUT



-1 M3 M M < M OUTB




CK -Mi CKb-- M2 CKb- CK-


Master Slave
Figure 3-2 Schematic of the 2:1 static frequency divider

When CK and CKb are equal to the common mode value and there is no input clock

signal, both the master and slave latches are semi-transparent, allowing signals to

propagate through both the latches. This makes the circuit work as a ring oscillator. If the

delay from the gate to drain of M3 is Cpd, then the oscillation period is equal to 4Cpd. Thus,

the circuit oscillates at 1/(4Cpd) and the signal at the drain of M3 lags the signal at the gate

of M3 by 900. In the small signal model, the propagation delay, cpd, is proportional to the

RLCL constant at the output node. However, the voltage swing in this circuit can be large

and the operation of the oscillator becomes nonlinear [21]. This makes RLCL only an

approximate estimate and large signal characteristic also need to be considered to

estimate the real oscillation frequency.









Usually, the higher self-oscillation frequency leads to higher operating frequency of

divider. Meanwhile, the oscillation frequency strongly depends on the transistors size.

Figure 3-3 shows the simulated oscillation frequency as function of the width of latch

transistors (M5,6) for varying widths of PMOS loads (M7,8). In the simulation, the widths

of M3,4 are fixed at 5 [tm and M1,2 are fixed at 8 tm. As can be seen, smaller load

transistors lead to lower oscillation frequency, because the RL increases with smaller

loads. Though the capacitance CL also decreases a little, it decreases slower than the

increase of RL. Furthermore, with given load transistors, wider latch transistors lead to

lower frequency. From the simulation, the output voltage swing (OUT, OUTB) increases

as the latch transistor size increases, because of the larger negative resistance from the

cross-coupled transistors. Meanwhile the maximum charge/discharge current is also

limited by M1. This leads to the longer charging and discharging time, which in turn

results in larger Tpd and smaller oscillation frequency [22]. Additionally, when the widths

of PMOS loads are less than 1.8 atm and latch transistors are less than 1 atm, the circuit

stops oscillating because the PMOS transistors are too small to pull-up sufficiently fast

[23].

To lower power consumption, the PMOS loads and latch transistors should be

small, while avoiding the region where the circuit fails to oscillate. Sufficient voltage

swing is also required to drive the subsequent stage. In the final design, the widths of the

drive transistors (M3, 4), PMOS loads (My, 8) and latch transistors (M5, 6) are chosen as 5

am, 2.6 am and 1.6 am, respectively. There is greater flexibility for sizing input

transistors (M1,2). It should be sufficiently large that the voltage drop across the

transistors is not too high and the gate capacitance is sufficiently low that the power










consumption for driving their gates is not high. The widths of M1,2 are chosen to be 8 tm.

For the following four stages, the frequency is lower, thus, smaller transistors are used

and the power consumption is much lower than that of the first stage.

16

3 7 1 Wp=1 .2Pm 2 Wp=1.5PLm
N 1 3 Wp=1.8jpm 4 Wp=2.2pLm
S12 5 Wp=2.6m 5 Wp=3.0m
S\ 7 Wp=3.54m 8 Wp=4.04m
2



8 ------- -- --- ---------- --------
U-



0

0
0 1 2 3 4 5
Width of the latch transistor (pim)

Figure 3-3 Oscillation frequencies versus the width of the latch transistors with
different PMOS load


Further, extracting from the layout of divider, the interconnect capacitance does not

change much with different sizes of the transistors. Therefore, as the sizes of all the

transistors are scaled up, the impact of interconnect parasitic capacitance becomes less

important and the self-oscillation frequency is increased. This, however, also increases

the power consumption. Figure 3-4 shows the power consumption, maximum and

minimum operating frequencies as function of the drive transistor (M1,2) width. In this

simulation, for both the master and slave stages, the widths of M1,2, M5,6 and M7,8 are

approximately 1.6 times, one third (1.6/5), and one half (2.6/5) of the width of M3,4

respectively. As expected, the power consumption increases almost linearly with the

transistor sizes, however, the operating frequency levels off when the drive transistor is

larger than 5[tm. This shows that the choice of 5 |tm for M3,4 is almost optimal.







17


30 6


25 -- -- 5
20 -,------------- -----------T----------------------------- 46









15 --r------------------ ------------------- 30
0 o
C 10 -
SnO



S15 3

5Po 1


0 0
0 2 4 6 8 10
Width of the drive transistor (Lrn)

Figure 3-4 The operating frequencies and power consumption versus the drive
transistor width


3.2.2 Experiment Results

To make the measurements easier and more realistic, a 32:1 circuit consisting of 5

stages of 2:1 divider is implemented. The circuit is fabricated in the UMC 0.13-[tm

CMOS logic process with eight-layer copper metallization. The die micrograph of circuit

is shown in Figure 3-5. The chip size is 0.38 mm x 0.53 mm, which is mainly determined

by the pad frame, while the active area is only about 20 ptm x 80 pm.

The divider starts to work at supply voltage of 0.53 V with 4.2 GHz maximum

operating frequency and only 56 MW power consumption of the first 2:1 stage. This is

only -12 MW higher than the divider architecture specially designed for low voltage and

power operation [24]. Figure 3-6 shows the input sensitivity measured at three different

supply voltages of 0.7, 1.2 and 1.5 V. The maximum operating frequencies are 10, 22.5

and 26 GHz respectively and the power consumption of the first 2:1 stage is 228 [aW,

1.86 mW and 3.88 mW, respectively. The power consumption of the whole 32:1 circuit










including buffers (with high impedance output load) is 551 aW, 4.68 mW and 8.97 mW,

respectively. With 50 Q output load, the power consumption is about 1/3 higher due to

larger current in the buffers. As can be seen, the first stage consumes about 45% of total

power. The output waveform is measured with Agilent Infiniium 86100B oscilloscope.

Figure 3-7 shows the output waveform with 26 GHz input signal. Since the buffers work

at low frequency, the output is close to square.


Figure 3-5 Micrograph of the 32:1 frequency divider


0

-5 -- --- ------ Vdd=0.7V
-A- Vdd=1.2V
-10 ---- -- --V = .
E Vdd=1.5V

-15

0 --20 ---

-25-

-30

-35
0 5 10 15 20 25
Frequeney (GHz)

Figure 3-6 Measured input sensitivity at different supply voltages


























time

Figure 3-7 Output waveform with 26GHz, 0-dBm input (Time 500ps/div, voltage
100mV/div, offset -5.1 mV, AC coupled, 50 output load, Vdd=1.5V)
.. .. ................. ......... .......... ............ .......|. ..................... ............. ...................... ......... .... ... ......+ ... ... ...|... ........ .................






time
Figure 3-7 Output waveform with 26GHz, 0-dBm input (Time 500ps/div, voltage
100mV/div, offset -5. mV, AC coupled, 50Q output load, Vdd=1.5V)

Table 3-1 summaries the power consumption and the maximum operating

frequency for several previously reported 2:1 CMOS static frequency dividers above 20

GHz. The 3.88-mW power consumption at 26 GHz is much less than those of all the bulk

CMOS dividers [16]-[18] and is close to that of the SOI CMOS frequency divider [19].

Table 3-1 Power consumption and maximum operating frequency for several recently
published 2:1 CMOS static frequency dividers
Ref Vdd Power Input Power Max. Freq. Te
Ref Technology
[V] [mW] [dBm] [GHz]
[16] 1.5 60.9* 9 25 120-nm CMOS

[17] 1.5 45* 10 27 120-nm CMOS

[18] 1.5 66* 0 18.5 120-nm CMOS
1.0 2.7 -7 25 120-nm SOI
[19]
1.5 7.66 -7 28.6 CMOS

1.2 1.86 0 22.5
This work 0.13-tim CMOS
1.5 3.88 0 26

* Including the power consumption of output buffers, which is about 1/3 of the total power
consumption









By optimizing the transistors sizes in D-flip-flops, a power efficient and high

sensitivity 32:1 static frequency divider in a 0.13-[tm CMOS process is demonstrated.

The first 2:1 stage can work up to 26 GHz with only 3.88 mW power consumption at 1.5

V supply. This is the most power efficient bulk CMOS static frequency divider operating

above 20 GHz.


3.3 Low Power Wide Bandwidth Constant Envelope Modulator

3.3.1 Minimum Shift Key and Constant Envelope Modulation

Minimum shift key (MSK) modulation can be considered as a special offset

quadrature phase shift key (OQPSK), as shows in Figure 3-8. Like other quadrature

modulation schemes, every two consecutive bits are impressed on quadrature phase of a

carrier. Suppose, we use half sinusoids, rather than rectangular pulses (which is used in

OQPSK), to represent the levels that are multiplied by the carrier. More specifically, as

shown in Figure 3-9, let us multiply the levels in the upper arm by cos o t and those in

the lower arm by sin 91t where o, = r r/(2Tb) and Tb is the data period. Thus, the output

of the modulator is

x(t) = am cos 09t cos (0Ot am, sin 01t sin (oct. (3-1)


am

A
C0S6)t COSO) ,o + -
Binary S/P


Figure 3-8 Block diagram of the MSK modulation











I I I I I
am
a 1 0 1 0
II I I I
I I I I II I I

S0 1














t
Figure 3-9 Signals in the MSK modulation


The resulted output signal of a MSK modulation is constant envelope. As a matter

of factor, MSK should eventually be viewed as a type of frequency shift key (FSK). The

MSK modulation can also be seen in the constellation of a phase modulated signal. The

signal vector, or phasor, changes its angle according to the transmitted bits while the

magnitude of the vector is kept the same. This results in a point moving on a constant-

radius circle and changing direction from time to time, as illustrated in Figure 3-10,

which shows an MSK modulation and its constellation for 8 bit intervals. The baseband

I/Q channel data bits are shaped into sinusoidal pulses and respectively modulated onto

two carriers with quadrature phases. Then the resulting signals of the two channels are

summed up, and the modulated signal becomes a constant envelope carrier with changing

phases. It can be seen that on the resulting constellation the phasor moves on a circle and

changes directions based on the I/Q bit pattern. It goes over a quadrant in a bit interval.









In order to simplify the circuit architecture without significantly compromising the

performance of modulator, the possible output states are limited to 16 discrete steps.

Therefore, the phase change over any bit interval, which corresponds to a quadrant on the

constellation, was implemented in a limited number of 4 discrete steps. The output of

modulator should generate a constellation as shown in Figure 3-11, where the modulated

signal moves sequentially on the circle and changes direction only on the I or Q axis

points. Theoretically, if infinite steps are used, i.e., these steps are continuous, it

implements standard MSK modulation [25], [26]. The modulator implements an MSK-

based constant envelope phase-shift scheme, so that a high efficiency non-linear power

amplifier can be used.








I I I I I I



Q i i
iI I I I I I
I 1 I I I I I




(a)

Figure 3-10 An MSK modulation example and the modulated signal's constellation
(a) MSK modulation is I-Q modulation with half sinusoidal pulse shaping
(b) The modulation generates a constant envelope constellation

In order to simplify the circuit architecture without significantly compromising the

performance of modulator, the possible output states are limited to 16 discrete steps.

Therefore, the phase change over any bit interval, which corresponds to a quadrant on the

constellation, was implemented in a limited number of 4 discrete steps. The output of

modulator should generate a constellation as shown in Figure 3-11, where the modulated









signal moves sequentially on the circle and changes direction only on the I or Q axis

points. Theoretically, if infinite steps are used, i.e., these steps are continuous, it

implements standard MSK modulation, and if one step per quadrant is used, its spectrum

is the same as standard offset QPSK [25], [26].

Q



x X

I I

k !




Figure 3-11 Ideal constellation of modulator output

Figure 3-12 shows the simulated output spectrum of this modulator, as well as

standard MSK and offset QPSK. Because of the limited steps is used, the modulation

sidelobes are higher than those for MSK. In particular, these are at frequency offset equal

to multiples of four times the data rate are higher. They are about -26 dB lower than the

mainlobe. However, compared to the offset QPSK, these peak sidelobes are lower and

occur at higher frequencies. This makes the filtering of the sidelobe easier.

3.3.2 Implementation of Constant Envelope Modulator

Figure 3-13 illustrates how, in a particular quadrant, constant envelope and

different phases can be generated from two quadratures of a carrier. By maneuvering the

values of a and b, which can be seen as the weights of two quadratures, 0 can be changed

while maintaining the constant envelope, r. By choosing pairs of quadratures of different

phases according to the actual data, the correct quadrant can be chosen.










0 -
-1-- This work
a -10 -
Offset QPSK


E -30





o. -60

-70

o -80
z
-90
0 1 2 3 4 5 6
Frequency offset from carrier (x data rate)

Figure 3-12 Simulated power spectra of the modulator output, standard MSK, and
offset QPSK


sincot








r \
b
"0 coso t
-, a

Figure 3-13 Illustration of how a phasor can be generated from two phasors in
quadrature


The approach of generating an in-between phasor from two phasors in quadrature

can be realized by a phasor combining circuit, or a summing circuit, whose conceptual

schematic is presented in Figure 3-14 [25], [26]. In this circuit, the two input LO signals,

V1 and V2, are at carrier frequency and have 90 degree difference in phase, while the









values of II and 12 determine the weights of the two LO's. Using the long channel small

signal transistor model,

a = gV = V2P, V, where / = CoxW/IL (3-2)

b = gm2V = 2 (3-3)

From Figure 3-13,

r = b2 = 2(I1 + 2)V. (3-4)

To ensure the constant envelope, the summation of I, and 12 should be constant. The input

signal swing must be limited and the longer gates need to be used, so that, the model is

valid. However, to achieve -2.7 GHz operating frequency, the gate lengths should also be

kept as short as possible. In the final design, the transistor length is chosen as 0.3 |tm.

The input and output voltage swing must also be limited to valid the linear small signal

transistor model.











4 11 11+12=constant T 12

Figure 3-14 Conceptual schematic of a summing circuit

3.3.3 Circuit Description

Figure 3-15 shows the block diagram of the modulator. The circuit mainly consists

of two 4:1 differential multiplexers, a phasor summing circuit, output buffers, and a logic










circuit to control the two 4:1 multiplexers. The logic circuit is not included in Figure 3-15,

for the purpose of clarifying the modulator circuit's main architecture. The input I/Q data

determine the control signals of the multiplexers. The four input quadrature signals are

the outputs of an 8:1 static divider similar to that described in Section 3.2


4:1 Multiplexer
I-----------------

ou 2:1
900 2:1 Buffer
1800 Next tate
2700 2:1

I--- -------- ----
CLK DATA + d Outp
Summing Buffer
4:1 Multiplexer Circuit Be
---------------- -----

S2:1
s m/ 2:1 Buffer
2:1
I--- 2: --- __--
CLKd DATAd
Figure 3-15 Block diagram of the constant envelope phase shift modulator


Figure 3-16 shows the schematic of the phasor combing circuit. The size of the

summing transistors (M1-4) is 8 lm/0.3 lm and the load resistor is about 1.6 KQ. The

variable currents (I1 and 12 in Figure 3-14) are implemented by switching current source

(M10-13) to left branch (Mi, 2) or right branch (M3, 4). In each period, the value of I1

decreases as 410, 310, 210, and Io, while the value of 12 increases as 0, Io, 210, and 310. This

topology ensures the total current of the two branches are always constant. The width of

Ms, 9 is twice of M5-7, so that they have the same voltage drop. The width of switches

(M5-9) and current sources are made sufficient large, so the voltage drops across these

transistors are not too high, which is important for the low voltage operation.















Present State N ext State



a M5 M6 [81b V-J My AA M8 Mg9 PAlb



lol l 1 ^10 lo 10 0210
SMio Ml lM12 lM13

Figure 3-16 Schematic of the phasor combining circuit

3.4 Intermediate Frequency Amplifier

The IF amplifier is implemented using the cascode topology. The schematic of the

IF amplifier is shown in Figure 3-17. Two cascode stages are used to provide sufficient

power gain. The size of the transistors in first stage (M-4) is 60 [tm/0.12 |tm and that of

the second stage (M6-9) is 180 [tm/0.12 |tm. From simulations, the two stages provide 20

dB power gain, while consuming 4 mA from 1.5 V supply voltage. The simulated output

P1dB is higher than 0 dBm.


3.5 Up-Conversion Mixer

Figure 3-18 shows a circuit schematic of the up conversion mixer. A double

balanced Gilbert cell active mixer is used to get higher gain and output power. From the

measurement results of [27], the gain of mixer is about 1 dB and the output P1dB is about -

11 dBm, while consuming 4.5 mA from 1.5-V supply voltage. In order to deliver 10 dBm

to the antenna, the following RF amplifiers must provide at 20 dB power gain.

























Figure 3-17 Schematic of the IF amplifier





RF+-

LO+-


Figure 3-18


Schematic of the up conversion mixer


3.6 High Efficiency Power Amplifier

3.6.1 Introduction to CMOS Power Amplifier

The power amplifier is the most difficult RF block in the transmitter. The PA is

typically the most power-hungry building block, which makes the PA efficiency crucial.

Compared to the transistors in III-V technology, the MOS transistor is slower, which

makes it more difficult to get high efficiency, especially around 20 GHz. The continuous


. Vout


-I- RF

--LO+









scaling down of supply voltage due to the lower breakdown voltage of MOS transistors

also limits the output power.

The efficiency of power amplifier is defined by two metrics [28], [29]. The drain

efficiency, r, is equal to the power delivered to the load (usually at the first harmonic)

divided by the power drawn from the supply. The power-added efficiency (PAE) is the

difference between the input and output powers divided by the supply power. If the PA

has a relatively large power gain, the drain efficiency is equal to PAE. In addition, the

output spurs and harmonics of the PA in the [[Node system must also satisfy the wireless

standards and FCC rules.

Figure 3-19 shows a simplified schematic of a typical common-source PA. The RF

chock (RFC) ideally has no voltage drop, thus, it will not affect the voltage swing at the

drain node. The matching network provides bandpass filtering at the fundamental

frequency. More importantly, it transforms the 50-Q load to lower impedance. For the

common-source configuration, the voltage at the drain node can only swing from 0 to

2VDD, thus the maximum power delivered is VDD2/2RL. By transform the load to a

lower value, higher output level can be achieved. It should also be noted that the output

stage of PA generally includes only one transistor instead of the cascode, because the

large current would introduce more loss with more active devices in the signal path [29].

However, for the single-transistor amplifier in Figure 3-19, the gate and drain nodes have

anti-phase voltage stresses to the gate oxide. The gate to drain breakdown is becoming

more and more severe limitation in CMOS, because the thinner gate oxide thickness in

shorter channel length device. Thus, some circuits [30], [31] have utilized the cascode

structure instead of the classical topology in Figure 3-19.











RFC
Matching/
Filtering
Vi, Network 50Q
Rin


Figure 3-19 Simplified schematic of the power amplifier

3.6.2 Class A, B, AB, and C Power Amplifier

The power amplifiers are traditionally categorized by classes: A, B, C, D, E, F, etc.

In class A, B, and C power amplifiers, the output transistor current and voltage

waveforms are sinusoidal, and they are similar to the standard small signal amplifier.

However, the signal current in a PA is a substantial fraction of the bias level, and one

would therefore expect potentially serious distortion. In narrowband operation, the high-

Q matching and filtering network solve the distortion problem, so that, overall linear

operation prevails. These PAs are primarily distinguished by bias conditions. In a class A

amplifier, the transistor operates linearly across the full input and output range; in a class

B amplifier, the transistor conducts for half of the carrier period, while in a class C

amplifier, the transistor is on for less than a half of the cycle. They can also be classified

using the conduction angle, 0. Figure 3-20 shows the signal current in these three

amplifiers.

In a class A power amplifier, if the drain voltage in Figure 3-19 is a sinusoid having

a peak-to-peak voltage of approximately 2VDD, then the maximum power delivered to the

matching network is equal to VDD2/(2R,1). For the drain voltage to reach 2VDD, the RFC

must provide current of VDD/R,,. Since the RFC current is relatively constant, the power









drawn from the supply equal to VDD2/Rn,. Therefore, the maximum drain efficiency is

equal to 50%.

Signal
Current
Signal
Bias--____- __ Current Signal
Current o Current

\.r

0*

,t
(a) Class A (b) Class B (c) Class C
Figure 3-20 Transistor currents for class A, B, and C power amplifiers.

In a class B power amplifier, since the transistor only conducts half of the carrier

period, the maximum power delivered to the load is only a half of class A amplifier, or

VDD2/(4Rn). The average current drawn from VDD is given by

1 T/2
IDD avg VDD /Rn sincot =VDD 1R) (3-5)


The maximum efficiency is therefore equal to 7T/4 z 79%. In audio systems, class AB

power amplifiers operating between class A and B are widely used. In these amplifiers,

the transistors conduct slightly more than a half of period. A push-pull configuration

makes sure that at least one transistor is on during an entire cycle. The class AB shows

good efficiency, high output power as well as good linearity.

In a class C stage, the conduction angle, 0, is less than 1800. As decrease, the

transistor is on for a smaller fraction of the period, thus dissipating less power. For the

same reason, however, the power delivered to the load also decreases. If the current

drawn by the transistor is assumed to be a piece of a sinusoid and the output voltage is a









sinusoid with a peak voltage equal to VDD, then the efficiency can be calculated as a

function of 0. As described in [28], [29], the efficiency is given by

1 0 sin O
r = (3-6)
4 sin( / 2) / 2 cos( / 2)

varying from 50% for 0= 3600 (class A) to 79% for 0= 1800 (class B) to 100% for 0= 0.

Though the class C stage could provide a maximum efficiency as high as 100%, the

actual power delivered to the load is

0 sin (
Pout O -c (3-7)
1 cos(0 / 2)

The quantity drops to zero as the conduction angle vanishes. For this reason, a true class

C power amplifier is not suitable to some portable transceivers, where the output power is

also a great concern.

3.6.3 High Efficiency Class E Power Amplifier

The main premise in class A, B and C amplifiers has been that output voltage and

current waveforms are sinusoid (or a section of a sinusoid), thus limiting the efficiency of

the class A and B and the output power of class C [28]. In these amplifiers, the output

matching network is designed with the assumption that the transistor operates as a current

source. While in class D, E and F stages [32], [33], the transistor operates as an ideal

switch, rather than a voltage-controlled current source. They are nonlinear amplifiers that

achieve efficiencies approaching 100% while delivering full power.

Figure 3-21 shows a schematic of a class E power amplifier [32]. It consists of an

output transistor M1, a grounded capacitor C1, and a series network C2 and L1. The RFC

has high impedance at the frequency of operation and C1 includes the drain junction

capacitance of Mi. To ensure 100% power efficiency, the power consumption of the









transistor M1 must be zero, i.e. the drain voltage Vx and transistor current ID1 cannot be

non-zero at the same time. Therefore, the values of Ci, C2, L1, and RL are chosen such

that the drain voltage of M1, Vx, satisfies three conditions [32]:

(1) As the switch turns off, Vx remains low long enough for the current to drop to

zero.

(2) Vx reaches zero just before the switch turns on.

(3) dVx/dt is also near zero when the switch turns on.



RFC

x L1 C2
M,
Vin, -1 XTC1 RL




Figure 3-21 Class E power amplifier

Figure 3-22 shows the simplified model of the class E stage. The transistor can be

modeled as a switch with small resistance. When the switch is on, a near linearly

increasing current is built up through the inductor. As the turn-on resistance of the

transistor is nearly zero, the voltage drop across the transistor is nearly zero and there is

no power consumption. At the moment the switch is turned off, this current is steered into

the capacitor, causing the voltage across the switch to rise. The tuned network is designed

such that in steady state, Vx returns to zero with a zero slope, immediately before the

switch is turned on. The bandpass filter then selectively passes the fundamental

component to the load, creating a sinusoidal output.

From [32], the value of the inductor and capacitors can be chosen as follows:









L QR (3-8)
0)

1 1
C, -I1 1 (3-9)
c1 R(;2 +1)(r/2) 5.447coR

5.447 1 42 1 1.42
C2 =C1( )(1+ ) (1+ )- (3-10)
Q Q 2.08 cQR Q 2.08

The Q should be as high as possible while satisfying the bandwidth requirement.

Once the Q is chosen, the PA can be designed in a straightforward manner, using the

equations given.



Vin

R F C t/



Vin





Figure 3-22 Simplified class E stage model and its voltage and current waveform

However, an ideal RFC and switch is not available in integrated circuits. A

technique using the relative low Q on-chip inductors and slow transistor is described in

[34]. A real class E power amplifier also includes an impedance transferring network [32],

as shown in Figure 3-23. The two series inductors are also usually merged as one. It

should also be noted that 100% efficiency is never possible because the transistor and

matching network always have loss. The non-zero turned-on resistance and non-zero

switch time limits the efficiency. The transistor is further away from an ideal switch









when the operating frequency is higher. In a practical circuit, PAE of 40-50% is usually

expected.



RFC



Vino R500




Figure 3-23 Class-E power amplifier with impedance transformation network

A drawback of class E power amplifier is the large peak voltage that the switch

sustains in the off state, which is about 3.56VDD in an ideal case, which demands high

transistor breakdown voltage. However, in real case, especially at higher frequencies, the

transistor is not a perfect switch, thus the maximum drain voltage is lower than the

theoretical value.

Compared with linear power amplifiers, which are usually optimized for maximum

gain and linearity, the switching class-E power amplifiers provide much higher efficiency.

They are particularly well suited for modem communication systems using a constant

envelope modulation, such as the Zigbee wireless personal area networks (WPAN'S) and

GSM cellular networks, as well as the constant envelope MSK-like modulation used in

the [[Node.

3.6.4 Circuit Description

Figure 3-24 shows the schematic of fully-integrated CMOS power amplifier

designed using the UMC 0.13-[tm process. It consists of a two-stage cascode amplifier, a

common source driver, and an output stage. Due to the limited voltage headroom,









common-source amplifiers are used in the last two stages. The sizes of transistors in these

four stages are 14, 24, 40, and 100 |tm, respectively. The cascode amplifiers are used to

provide sufficient gain, good input matching and isolation from the last two stages which

potentially could oscillate.

VDD1 I-
____ VDDI r------------ r------------
SDriver VDD2 Output VDD3
SStage | Stage


SOUT
I I
-1 M2 M 4:
]' ,l ,j ,tr 'Z


I'"sNM MHt3 rL M5: M6
Lg3

\Yb3 Vb4
Vb2 1 0pF 1 0pF
S I,
Figure 3-24 Schematic of the fully-integrated CMOS power amplifier

Figure 3-25 shows the schematic of the output stage. The matching network

components, L1, L2, C1, and C2, have to be properly selected as described above. The

shunt capacitor at the drain of the transistor is omitted because the capacitance from the

drain of the transistor is already large enough. To lower the matching network loss, the

inductors L1 and L2 are formed with the top two copper layers, which results an effective

thickness of 1.6 |tm. The metal traces are 3.6-[tm wide and 4-[tm above the polysilicon

patterned ground shield. The effective series resistance of two inductors is about 5 Q. The

shunt capacitor C2 transfers the 50 Q load to around 40 Q at 20 GHz. In the layout, C2 is

formed by absorbing the pad capacitance (-48 fF) and shunt parasitic of the Ci (-32 fF).

A shunt inductor (Lg) is placed at the gate of output transistor to tune out the gate









capacitance, which reduces the value of the coupling capacitor, but as will be discussed

below, also makes the circuit more potentially unstable.




0.6nH L RL=40-j20
0.55nH ,-----

100fF M6 C1
IN 100/0.12 15fF C2 505
N 100/0.12 |, _| 80fF
Lg
0.24nH
Vb4
10pF



Figure 3-25 Schematic of output stage

3.6.5 Mode Locking Technique

Near 20 GHz, the common source driver stage is potentially unstable due to the

feedback through Cgd, which is one of the reasons of the wide use of cascode amplifiers.

Figure 3-26 shows the simplified small signal model of the common-source amplifier,

which includes a transconductor and two resonant networks connected by Cgd.

Due to Cgd, the output of the amplifier is fed back to the input. The open loop gain

of this circuit can be written as,


T(s)= g, Zd+/ Zg +s- + (3-11)


This expression consists of two parts: the gain from the gate to drain and voltage divider

for the feedback path. To start oscillation, the loop gain should be larger than 1 and the

phase change must be 360 degree. For the network at the gate node, below its resonant









frequency, the network is inductive with an equivalent inductor Lg,equ and a series resistor

Rg,Eq. The transfer function of voltage divider between Cgd and the network is

Zg jCoLg,equ +Rg,equ
Zg +1/(SCgd) j oLg,equ +Rg,equ +1/(jCOCgd (
(3-12)
Lg,equ Cgd + jOC gdRgequ
1- ,2Legd + gdRgequ

When o)Lg,equ>Rg,equ or Q is high, at frequencies below 1/ Lg, Cgd this voltage


divider provides a phase shift close to 1800. Meanwhile, when o)Lg,equ
phase shift of 0 to 900. To satisfy the oscillation condition, the first term in Eq. (2.10)

needs to provide 1800 phase shift or the tank at drain node must resonate at the oscillation

frequency, and the second term must provide another 1800 phase shift. Therefore, the

resonant frequency of Lg,eq-Cgd circuit is set higher than the oscillation frequency and the

high Q inductive load at the gate node is used.


------------



Cgd Rd
-- -- --^ f^--d
V, --- --I




C,9


Figure 3-26 Small signal model of the common source amplifier

The output stage is designed to drive 50-Q load, so the voltage gain is not high. On

the other hand, the driver stage is designed to achieve high voltage gain. Because of this,

it is easier to make the driver stage oscillate. To provide good input matching, two stage









cascode amplifiers are used at the input. The gates of the common-gate transistors are

connected to a bypass capacitor right beside the transistors to make the cascode stage

stable.

The instability is generally not desirable in power amplifiers. However, if the self-

oscillation can be locked by the input, the instability actually increases the gain of the

circuit and reduces the drive requirement for switching the output transistor. This is

called mode-locking (also known as injection-locking) and has been previously utilized

in power amplifiers [35], [36]. Usually, cross-coupled transistors are used to provide the

positive feedback (or negative resistance). Since the driver in this work is unstable,

additional positive feedback is not included. To study the benefits of mode-locking, a

power amplifier without mode-locking is also implemented. This is accomplished by

removing the gate inductor of the driver stage (Lg3 in Figure 3-24). In addition, a 3-kQ

resistor is added for dc biasing.

3.6.6 Experiment Results

The power amplifier was fabricated in the UMC 0.13-[tm logic CMOS process with

eight copper layers and a substrate resistivity of 20 Q cm. Another PA without using

mode locking is fabricated for comparison. Figure 3-27 shows the die photograph of the

two single-ended power amplifiers. The two amplifiers together occupy an area of 0.92

mm x 0.85 mm including bond pads.

The large signal measurements were performed using the setup shown in Figure

3-28. The output is connected to a power meter with an HP8485A 50MHz-26.5GHz

power sensor. The losses of measurement setup are de-embedded using a thru-

measurement. The loss at the output end (from the probe and short SMA cable) of -0.7









dB at 18 GHz was measured with a network analyzer. An Agilent E4448A 50-GHz

spectrum analyzer is also used to monitor the output spectrum of power amplifier.


.... . .- ,,' "
Figure 3-27 Die photograph of the chip containing two single-ended power amplifiers


DC supply

3 feet 3.5 inches
3.5mm-cable SMA-cable
Agilent A -DUT HP HP
E8254A RF RF 8485A 437B
Probe Probe
Signal Power Power
Generator Sensor Meter
DC supply
Figure 3-28 PA measurement setup

With 1.5-V supply voltage and proper gate bias (0.5-0.7 V), the power amplifier

shows self-oscillation with -1-dBm peak power near 17.4 GHz. The self-oscillation is

lower than designed frequency of 20 GHz probably because the gate to drain capacitance

(Cgd) is larger than expected. As the input signal level applied at the 'IN' node in Figure

3-24 is increased, the self-oscillation becomes weaker until finally the circuit is forced to










oscillate at the same frequency as the input. Figure 3-29 shows the output spectrum with

17.6 GHz input. With -42-dBm input power level, the self-oscillation cannot be locked,

and the self-oscillation peak and inter-modulation products are shown beside the main

peak. At -36-dBm input power, the circuit locks to the input signal. Figure 3-29(b) shows

that the output power is more than 10dBm when input power is -10dBm. When the input

frequency is farther away from the self-oscillation frequency, the circuit becomes more

Ref 20dBm
Norm
Log
10 elf Input
dB/


LgAv

V1 S2 -
S3 FC
A AA
(f):
FTun
Swp

Center 17.505 GHz
#Res BW 3 MHz

Ref 20dBm
Norm
Log
10
dB/


LgAv

V1 S2
S3 FC
A AA
(f):
FTun
Swp

Center 17.505 GHz


--- sculation

Inter
VSCUI~fl~fl


iFrequency
Intei
Modulation
I I I


Span 2 GHz
VBW 3 MHz #Sweep 100ms (601pts)


1 1-0o67 dBrn


Span 2 GHz


#Res BW3 MHz VBW3 MHz (b) #Sweep 100ms (601 pts)


Figure 3-29 Output spectrum (a) unlocked, input:-42dBm (b) locked, input: -10dBm.
(Losses from the cable and connector have been de-embedded)







42


difficult to be locked. At -10-dBm input power level, the circuit can be locked from 15.5

to 21.4 GHz. In addition, when a 20-GHz -10-dBm FM signal with 16-MHz maximum

frequency deviation and 1 kbps to 1 Mbps data rate is used as input, the PA locked to the

input, while preserving the shape of spectrum. A drawback of the circuit is that the

minimum output power level is above 2 dBm when the PA is locked. If an output level

below this is desired, the bias voltage can be lowered, making the oscillator easier to lock

or stop the oscillation. The self-oscillation disappears when the gate bias of the driver

stage is below 0.45 V.


12 45


10 ------ --- 40

E
S8 ------------------------------------ ---35
o E
0


8 -.-Pout(dBm)
4 Iu --(mA) 25 5)
4 --------- 2------- -- I(mA) ------------ 250


2 I I 20
-35 -30 -25 -20 -15 -10 -5 0
Input Power (dBm)

Figure 3-30 Output power and current consumption as function of the input power for
the 18 GHz power amplifier. (Supply voltage: 1.5 V)


Figure 3-30 shows the output power and current consumption as function of the

input power for the PA with mode-locking. At 18 GHz, with -5-dBm input power, a

single-ended output power of 10.9 dBm is obtained while drawing 35 mA from a 1.5-V

supply. The maximum power added efficiency including all the amplifiers and driver is

23.5% (Figure 3-31). Because all the four stages are integrated together, the power at the







43


gate of the last stage cannot be measured. Here the current consumption of all stages are

included in the calculation of the PAE. The last stage consumes 22 mA and drain


40%

35%
30% -------------------------- .p------
30%

25%

20%

15%

10%
10% ------ ----------

5% ----------------

0%
-35 -30 -25 -20 -15
Input Power (dBm)


-5 0


Figure 3-31



12

11

10

9

8
0
S7

0 6

5

4


PAE and drain efficiencies as a function of the input power of the 18-GHz
power amplifier (Supply voltage: 1.5 V)


30%
- - - - - ------ - - - - - - -


------------- ------------- --^ -- ------------------- 25%



20%





------------ -1%-u-------------

I 110%


15 16 17 18 19 20 21 22
Frequency (GHz)

Figure 3-32 Output power and PAE as a function of the frequency of the 18-GHz power
amplifier. (Supply voltage: 1.5 V)











15

10

5

0

-5
-5 -

-10

-15

-20

1 C


-50 -40 -30 -20 -10
Input Power (dBm) (a)


35 -


30 -


15 -


-50 -40 -30 -20 -10 0
Input Power (dBm) (b)


Figure 3-33 Output power and gain as function of the input power for the two power
amplifiers.


efficiency of the last stage is about 38%. Further increase the input power leads to

slightly higher output, but larger current consumption and lower efficiency. At 1.2 V

supply, the PA provides 7.5-dBm saturated output power and 18.6% maximum PAE,


-- PA w/ mode locking
(18 GHz)
-A-PA w/o mode locking
(20 GHz)


---PA w/ mode locking
(18 GHz)
-A-PA w/o mode locking
(20 GHz)


-.L,









while drawing 24.5 mA current. Figure 3-32 shows the saturated output power and PAE

from 15.5 to 23 GHz at 1.5 V supply. The PA with mode-locking provides more than 8-

dBm saturated output power over a 5-GHz band.

The result for the PA without mode-locking is compared in Figure 3-33. This PA

achieves 10.2 dBm peak output power and 20.5% maximum PAE at 20 GHz. Because the

gain is lower, it requires 6-8 dB higher input power to get the same output level. The use

of mode-locking technique leads to slightly larger saturated output power and efficiency.

More importantly, it reduces the input power requirement of class-E amplifier.

3.6.7 Summary and Conclusions

An 18-GHz 10.9-dBm class-E power amplifier with 23.5% maximum PAE is

demonstrated in the UMC 0.13-[tm CMOS technology. The mode-locking technique is

used to force the oscillating driver to follow the input signal. The performance of power

amplifier in this work is compared to that of the previously reported power amplifiers

operating near 20 GHz in Table 3-2. The PA presented in this work shows significantly

higher efficiency and lower input requirement than that for the previously reported

CMOS PA operating near 20 GHz. This work suggests CMOS technology is a viable

candidate for building a fully-integrated transmitter operating near 20 GHz.

Table 3-2 Comparisons of power amplifiers operating near 20 GHz
Small
Ref. Freq. Vdd Signal Gain Pout
Ref.[GHz] [V] Signal Gain Output PAE Technology
[GHz] [V] [dB] [dBm]

s 18 1.5 34 10.9 Single-ended 23.5% 0.13-mnm CMOS
This
work
20 1.5 26 10.2 Single-ended 20.5% 0.13-.im CMOS

[31] 24 2.8 7 14.5 Single-ended -6% 0.18-.im CMOS

[37] 24 N/A N/A 18 Differential 26% 0.13-jim GaAs






46


3.7 Summary

In this chapter, the key RF blocks of the transmitter implemented in the UMC 0.13-

|tm CMOS technology were presented. These blocks were a quardrature generator

(frequency divider), a constant envelope modulator, an IF amplifier, an up-conversion

mixer, and a high efficiency power amplifier. A complete transmitter chain could be built

by integrating these blocks.














CHAPTER 4
WIRELESS COMMUNICATIONS USING ON-CHIP ANTENNAS

4.1 Review of On-Chip Antennas

4.1.1 Introduction to On-Chip Antennas

The research on antennas fabricated on semi-conducting substrates dates back to

late 1980's [38]. An on-chip antenna integrated with a 95-GHz IMPATT diode oscillator

on a high resistively silicon substrate and an on-chip antenna integrated with a 43.4-GHz

IMPATT diode oscillator on a GaAs substrate [39] have been reported in 1986 and 1988,

respectively. High resistivity silicon substrates have also been used to fabricate MEMS

based antennas operating at 90 to 802 GHz [40]. However, use of IMPATT diode circuits

limits the types of radios that can be built. Furthermore, the substrates are not compatible

with the low cost mainstream silicon process technologies.

For on-chip antennas, the antenna size is limited by the size of the chip. Therefore,

to achieve usable antenna efficiency while limiting the physical size of the antenna

requires operation at higher frequencies (e.g., > 15 GHz), with corresponding to smaller

wavelengths. As discussed in the preceding chapters, the speed improvement of silicon

devices has made implementation of silicon integrated circuits operating at 20 GHz and

higher feasible. At 24-GHz, a quarter wave dipole antenna needs to be only 3.2 and -1.5

mm in free space and silicon, respectively, making integration of an antenna for wireless

communication possible.

An on-chip antenna could potentially be used to relieve the bottleneck associated

with global signal distribution inside integrated circuits. The first proposed uses of on-

47









chip antenna fabricated in conventional foundry process are clock distribution [41] and

data communication [41], [42]. Clock transmitter and receiver with on-chip antennas for

intra-chip [42]-[45] and inter-chip [46] wireless connection have been demonstrated.

Using one of the clock receivers, a 14.3-GHz 20-dBm signal from a 2-mm long zigzag

dipole transmitting antenna 40 cm away has been successfully picked up [44]. An 18-

GHz clock transceiver circuits with start-up initialization and programmable delays

successfully demonstrated the wireless clock distribution using an on-chip antenna pair

[45]. A signal from a transmitter incorporating a 10-GHz VCO, buffer and antenna

fabricated in a BiCMOS technology [47] has also been picked up by an external horn

antenna. These suggest the potential to communicate over free space using CMOS and

BiCMOS radios with on-chip antennas.

4.1.2 Measured Performance of On-Chip Dipole Antenna

Figure 4-1 shows a micrograph of an on-chip antenna. The antenna is a 3-mm long

zigzag dipole with a bend angle of 300 similar to that reported in [3], [9]. Compare to a

linear dipole antenna, the zigzag one possesses higher efficiency [48]. The 3-mm length

corresponds to around X/4 in free space at 24 GHz. The antenna is formed by shunting all

eight metal layers. The metal width is 24 itm. Figure 4-2 shows the input refection

coefficient, ISn1, of the on-chip antenna between 20 and 26 GHz. IS11 is below -10 dB

over this frequency range. The measured input impedance is 75 j23Q at 24 GHz.



3mm
E
MK' CD


Figure 4-1 Photograph of an on-chip antenna






49


0


-4-



Z= 75 j 23 f2
Cf -12


-16


-20
20 21 22 23 24 25 26
Frequency (GHz)
Figure 4-2 Input reflection coefficient of a 3-mm zigzag on-chip antenna

The power gain of an on-chip antennas pair is measured in real environments using

mobile probe stations [9]. Figure 4-3 shows a measurement environment. A signal

generator provides a 24-GHz signal to the transmitting on-chip antenna and the signal is

picked up using another on-chip antenna at different locations. The received signal power

level is measured using a spectrum analyzer. By de-embedding the cable and probe loss,

the power gain of an antenna pairs can be obtained. Figure 4-4 shows the measured

antenna pair gain in the lobby as a function of the distance with different height to the

ground. The antenna pair gain, Ga, for the 5 meters separation is between -93 and -104

dB, depending on the height to the ground.

By using the Friis transmission equation, the free space path loss is


P- = 4 GtG (4-1)


where A is the wavelength in free space, R is the distance between an antenna pair, and Gt

and G, are the transmitting and receiving antenna gains. If isotropic antennas with unity










gain are used, the path loss at 24 GHz can be calculated as -74 dB with 5-m spacing.

Therefore, the power gain of the on-chip antennas pair is -30 to -20 dB lower, or each of

the on-chip antenna's gain is between -15 and -10 dBi in the lobby environment. This

lower power gain is mainly due to the lossy silicon. Referring back to system link budget

in Table 2-1, the on-chip antenna despite the loss associated with the conductive substrate

should be sufficient for the kNode application with -98-dBm sensitivity [3], [9]. The

antennas pair gain is increased by about 10 dB when the substrate is thinned to from 700

ltm to 100 |tm [9].


Figure 4-3 Antennas pair measurement environment (lobby)


-40.0


-60.0


-80.0


-100.0


.1 1.0 10.0 100.0
Distance (m)

Figure 4-4 Antenna pair gain vs. distance in the lab for 3-mm zigzag antennas on a 20
Q1cm, 670-tpm thick substrate with a 3-gm oxide layer. The measurement
frequency is 24 GHz [9].









4.2 Test Transmitter with an On-Chip Antenna

4.2.1 Circuit Architecture

In order to demonstrate the feasibility of using an on-chip antenna for wireless

communications, a test transmitter was fabricated and tested. Figure 4-5 shows a block

diagram of the chip. The circuit includes an IF amplifier, an up-conversion mixer, two-

stages RF amplifiers, and an on-chip antenna. The IF and RF amplifiers utilize the

cascade topology, and the mixer utilizes the double balanced Gilbert cell, as described in

Chapter 3.

21.33 GHz 24 GHz
LO



2.67 GHz -

IF Amplifier Mixer RF Amplifiers

Figure 4-5 Block diagram of the test chip with an on-chip antenna

4.2.2 Experiment Results

The chip was fabricated in the UMC 0.13-[tm logic CMOS process. Figure 4-6

shows the micrograph of test chip. The antenna occupies 3.0 mm x 0.12 mm and the

other part occupies 1.1 mm x 0.85 mm including bond pads. The zigzag antenna is

formed using all 8 metal layers available and the width of the metal trace is 24 |tm.

The chip is first characterized on-wafer without the antenna. Figure 4-7 shows the

input and output matching of the circuit. The |S11 is lower than -10 dB from 2.5 to 3 GHz

and |S22 is lower than -10 dB from 22.5 to 25.5 GHz. Figure 4-8 shows the measured

output power as function of input power. The LO signal power is about 3 dBm. The

conversion gain from these four stages is about 20 dB. The circuit provides an output P1dB









of around -4 dBm and a saturated output power of around -1.5 dBm, while consuming 15

mA from a 1.2-V supply. The current consumption of IF amplifier, mixer, and RF

amplifiers are 1.8 mA, 4.8 mA, and 8.4 mA, respectively. With a 1.5-V supply, the

saturated output power is about 0 dBm and the current consumption is 28 mA.


RF Amplifiers

Mixer


IF Amplifier


Antenna


Figure 4-6 Micrograph of the test transmitter with an on-chip antenna


2 2.5 3 3.5 4 20 21 22 23 24
Frequency (GHz) Frequency (GHz)


Figure 4-7 Input and output matching of the test transmitter


25 26










0
0 --

-5

-10

-15

-20

-25

-30

-35 C


-5 -5 -4 -4 -35,


-55 -50 -45 -40 -35
Pin (dBm)

Figure 4-8 Output power as function of input power


Figure 4-9


30 -25 -20


Measurement setup of the 5-m wireless communication using an on-chip
antennas pair


To demonstrate the feasibility of using an on-chip antenna for wireless

communication, an amplitude modulation (AM) signal with 50% modulation depth was

provided to the IF input of the test transmitter chain, so that, the transmitter delivered a









24-GHz, 0-dBm AM signal to the on-chip antenna. The measurement setup and

environment are shown in Figure 4-9. The distance between the transmitter and the

receiving antenna pair is 5 meters. The transmitter is located on a probe station while the

receiving antenna is placed on a mobile probe station. The received signal is measured

using an HP 8563E spectrum analyzer. The signal received at 5 m is about -102 dBm.

Considering there is about 3 dB loss from the probe and cable, the gain between the on-

chip antennas pair is estimated to be about -99 dB. Figure 4-10 shows the AM signal

picked up by the on-chip receiving antenna.

-80
-80 ------------------------------------------------------
-90

-100 --- -0T2.17 T-


-120 -----3 i -113-5




-140

-150

-160
Center 24.0000011 GHz Span 10 kHz
#RBW 3 Hz VBW 3 Hz
Figure 4-10 Received signal using an on-chip antenna located 5 m away

4.3 Fully Integrated Transmitter with On-Chip Antenna

4.3.1 Transmitter Chain Overview

Figure 4-11 shows the transmitter chain. As mentioned before, the transmitter

includes a frequency divider, a MSK-like modulator, IF amplifiers, an up-conversion

mixer, RF drivers, a power amplifier and an on-chip dipole antenna. The 8:1 frequency

divider generates quadrature signals for the modulator. The serial baseband digital data









are up-converted to IF by the modulator. The signal at IF is amplified and fed into a

double-balanced Gilbert cell up-conversion mixer. The RF signal is amplified by a 3-

stage driver and fed to a class-E power amplifier (PA). Finally, the PA drives a 3-mm

long on-chip zigzag dipole antenna. To provide sufficient LO power level, two buffers

for LO signals are also included on the same chip.


VCO


Buffer


PA Drivers Up Mixer
Figure 4-11 Transmitter chain architecture


IF Amp Modulator


1.5V 1.2V


VB1 v VB2 v VB3 6 pF

Figure 4-12 Schematic of the RF drivers and power amplifier


The 1-dB compression point of the upconversion mixer is only -10 dBm [27], so

that, more than 20 dB power gain must be provided by the following RF stages. Too


Serial
Digital
Data









much gain at IF stage is just a waste. Meanwhile, to achieve a lower error vector

magnitude (EVM, Appendix A), the output voltage swing of the modulator is

intentionally limited (Chapter 3.3) and a moderate IF stage gain is required. In this design,

a two-stage IF amplifier provides about 18 dB power gain. The four-stage RF amplifiers

including PA provide about 25 dB small signal gain. It should also be noted the mixer

output power level could be improved by using alternate architecture [49]. However, it

provides lower gain and requires higher power consumption.

Figure 4-12 shows the schematic of differential RF drivers and power amplifier.

All the circuits in the signal path are fully-differential, which should improve the

rejection of common-mode noise from the digital circuits which will eventually be

integrated on the same chip. This also allows the connection to the dipole antenna to be

made without a balun. To deliver sufficient power level to the antenna, the widths of

transistors are chosen as 14, 24, 48 and 100 |tm, respectively. Because the self-oscillation

of drivers could be mistuned, to improve the chance for proper frequency tuning of the

transmitter, the mode locking technique is not used in this version. Instead, all the three

driver stages utilized the cascode topology. In the first two driver stages, the current

sources at the common-mode nodes are replaced by inductors to increase the voltage

headroom. Shunt inductors are placed at the gates of transistors in the last two stages, so

that, the AC coupling capacitor can be smaller. Here, a lower supply voltage of 1.2 V is

used for PA to have larger reliability margins.

4.3.2 Experiment Results and Discussions

The chip was once again fabricated using the UMC 0.13-[tm 1P8M CMOS process.

Figure 4-13 shows the die micrograph. The active area occupied by the transmitter is 1.8









mm2 including the antenna and bond pads. An integer-N frequency synthesizer is also

integrated to study the VCO pulling issue. The size of the synthesizer is 0.7 mm2.

F- 3mm


Antennga

PA


SRF Drivers
1.52 mm
Mixer



LO Buffers IF Amplifiers

Divider & Modulator

Figure 4-13 Photograph of the fully-integrated transmitter and frequency synthesizer

The transmitter is first characterized on-wafer without the antenna. The output

spectrum is measured using an Agilent E4448A spectrum analyzer and the output power

level is measured using a power meter. The transmitter including the divider and LO

buffers consumes 100.2 mW. The supply voltage of the PA is 1.2 V and supply voltage

of other circuits is 1.5 V to achieve higher power gain. Figure 4-14 shows percentage of

power dissipation in each block. As can be seen, the 24-GHz RF drivers and PA

contribute more than 60% of the power consumption, which is why the efficiency of

drivers and power amplifier is so critical in the design.

The transmitter can deliver 8-dBm output power to a 50-Q load near 24 GHz. The

3-dB bandwidth is 3 GHz. The PA should be able to deliver saturated output power of 10

dBm at 1.2-V VDD if a larger voltage swing were provided by the driver. Figure 4-15









shows the output power level between 21 and 26 GHz. The differential LO signal is

provided using an external signal generator and the minimum required power is -5 dBm.


8:1 Divider Modulator


LO Buffers
13.5%




PA (Last --
Stage) i
25.2%


--


3.7%

IF Am plifer
7.5%

Up Mixer
6.7%






RF Drivers
35.9%


Power consumption distribution in the transmitter chain


8
E


O 60
4-

S2
C.
O 0

-2
-2 ----------------------

20 21 22 23 24 25 26
Output Frequency (GHz)
Figure 4-15 Transmitter output power versus frequency

Figure 4-16 shows the measured output power spectrum density (PSD) for 100-

Mb/s pseudo random digital input. The random data are provided by an Agilent N4906


Figure 4-14









serial Bit Error Rate Test (BERT) instrument. The measured main lobe bandwidth is

about 1.5 times the data rate and contains nearly all the output power as expected for

MSK modulation. Outside the 24-24.25 GHz ISM band, the peak PSD is -36 dBm/MHz,

or 5 dB higher than the equivalent isotropic radiation power (EIRP) of -41.25 dBm

(measured with 1-MHz resolution bandwidth) required by F.C.C. If the antenna gain of -

10 to -8 dBi is included, the emission easily satisfies the requirement. However, the radio

itself should satisfy the requirement, so that it can be used for a wider variety of

applications. The higher sidelobes are partially due to the IF amplifiers being slightly

mistuned to higher frequency. In addition, the modulation steps should be increased to 8

(Chapter 4.4), so that, the peak sidelobes are around 3 dB lower and occur at 800-MHz

offset, so that, the IF amplifier could provide better suppression.


0

Center: 24.125 GHz
-10 SPAN: IGHz -
RBW: 1 MHz

0 -20









-50

Figure 4-16 Measured output power spectra of the transmitter around 24-GHz

The output of transmitter for pseudo random input is down-converted to 1 GHz and

the constellation is obtained using an Agilent 89600 vector spectrum analyzer (VSA).

The measured rms and peak EVM's are 7.7% and 16.8% (Figure 4-17). A lower data rate











of 12 Mb/s is used due to the bandwidth limit of VSA. The measured rms magnitude

error is 4.4% and the average phase error is 3.8 degrees.


A: Chi QPSK Meas Time Range 3162278 V
1 5 CAL?
Trial License
6 Days Left


1-Q



300
m
/div



-1 5
-2.88062284 2.880622837
D: Chi QPSK Syms/Eris Range: 3.162278 V
EVM = 7.6629 %rms 16 814 % pk at sym 114
Mag Err = 4.3932 %rms -11.817 % pk at sym 148
Phase Err = 3.7949 deg 10.211 deg pk at sym 133
Freq Err = -29994 MHz SNR[MER) = 21 812 dB
IQ Offset = -46.895 dB Rho = 0.99341
Quad Err = -61.248 deg Gain Imb = 1.299 dB
CAL?

Figure 4-17 Measured transmitter output constellation with a 12-Mb/s data rate


Figure 4-18 shows the measured spectrum with constant data input. The span is 24-

GHz, so most of the harmonic spurs can be observed. As mentioned, the F.C.C requires

the EIRP of harmonic emission to be lower than -41.25 dBm/MHz. The image signal at

18.76 GHz is around -24 dBm or 32 dB lower than the in-band output. When a random

input is used, the power will spread to the entire frequency band and the power spectrum

density will be no higher than -42 dBm/MHz. Therefore, the harmonic emission due to

the image satisfies the F.C.C requirements.

The LO leakage is about -27 dBm or 35 dB lower than the in-band carrier. The LO

leakage is about 14 dB higher than the F.C.C requirement and its power level does not

change when random data are used. To reduce this below the F.C.C. limit, notch filters










must be added in the transmitter. More symmetric layout should also be used so that the

LO leakage can be better rejected by the circuit.


10
RF
0

-10

-o image LO
I -30

E -40
---50







-90


Figure 4-1


12 15 18 21 24 27 30
Frequency (GHz)
8 Measured output power spectrum with 24-GHz span


33 36


Table 4-1 Summary of the 24-GHz transmitter performance
Frequency band 24 24.25 GHz ISM band
Modulation constant envelope MSK-like
Data rate Up to 200 Mb/s
Output power 8 dBm
PA saturated output 10 dBm (Vdd=1.2 V)
Power dissipation 100.2 mW
PA: 21mAx 1.2V
Others: 50 mAx 1.5 V
EVM 7.7% rms (data rate: 12 Mb/s)
LO leakage -35 dBc (req. -49 dBc)
Chip area 1.8 mm2


The integer-N synthesizer beside the transmitter chain operates from 20.05 to 20.95

GHz, while consuming 24 mA from a 1.5-V supply. However, due to the mis-tuning of

buffers, the output power was not sufficiently. Nevertheless, the transmitter is functional









when driven from the synthesizer although the transmitted power is about 10 dB lower.

The measured performance of the transmitter is summarized in Table 4-1.

4.3.3 Up-Link Demonstration Using an On-chip Antenna

The communications between a transmitter with an on-chip antenna and a base

station is demonstrated by transmitting a 24-GHz single tone (with constant digital input)

and picking up the signal using a horn antenna with 20 dBi nominal gain. The horn

antenna was located at an entrance of a building and the transmitter is placed on a mobile

probe station located at a parking lot 95 meters away in a humid morning (Figure 4-19).

The horn could be considered as the antenna of a base station. The received signal is -97

dBm or the antenna pair gain is about -105 dB. These suggest that communication

between a base station and an integrated circuit with an on-chip antenna over a distance

of 100 meters is possible.








C-i












Figure 4-19 Reception of the signal from a transmitter IC with an on-chip antenna using
a 20-dBi gain horn antenna located 95m away







63


4.4 Improved Transmitter Chain Design

As discussed, it is required by F.C.C that the spurious emission must be less than -

41.25 dBm when measured with 1-MHz resolution bandwidth. The transmitter chain

however presently can not satisfy this. The problems come from two parts. First, the peak

sidelobe power spectrum density is around -35 dBm/MHz. Secondly, the LO leakage is

about -27 dBm, or 14 dB higher than required. These two problems can be solved using

improved modulator and amplifiers design.

4.4.1 Improved Modulation Scheme


0
a" 8 steps/bit
- 4 steps/pit
'- -20
20 -- MSK

E / '
-40 ,

t-




-80
0
z

-100
0 1 2 3 4 5 6 7 8 9 10
Frequency offset from carrier (x data rate)

Figure 4-20 Modulator output spectra with different modulation steps per bit


The sidelobes in Figure 4-16 come form the modulator. To achieve higher level

integration, no filters are used in the transmitter and IF amplifier is the only component

which can suppress these sidelobes. To provide better rejection to these sidelobes, more

IF amplifier stages can be used, which however results in higher power consumption and










larger silicon area. A better way is to move these sidelobes to higher frequency offset.

Because only 4 discrete steps per bit are used, the peak sidelobes appear around 4 times

of the data rate. If more steps per bit are used, the sidelobes will move to higher

frequency offset. Figure 4-20 shows the modulator output spectra with 4 and 8 steps per

bit scheme. As a matter of fact, the MSK modulation has infinite steps per bit. In the

improved modulator, 8 steps per bit are used. This also requires the control circuit

running at higher frequency and the control signals better matched to reduce the clock

feed-through. The IF amplifiers is also re-tuned, so that, its center frequency is around 2.7

GHz.

4.4.2 Improved Transmitter Front-End with Notch Filters





SL Zin2 LC2

(a) T (b)

120 1200

100- 1000

80 800 -- -

C 60 -- 600
CI I
E 40 ------- -- ---- --- --- C* 400 ------- --- ----- --- -
I I
20 I 200I
I I I I
I I I0 I
18 20 22 24 26 18 20 22 24 26
Frequency (GHz) Frequency (GHz)

Figure 4-21 Second and third order notch filters and their characteristics









The LO leakage most likely comes from the active circuitry. Because the

bandwidth of the RF amplifiers is wide due to low-Q passive components, the RF

amplifiers cannot provide sufficient suppression of LO leakage from the up-conversion

mixer. To solve this, notch filters at LO frequency can be inserted. Two notch filters

structures can be used. Figure 4-21 shows the schematic and the simulated characteristics

of the second and third order notch filters. The Q of the inductor is assumed as 20 and

that of the capacitor is 50 at 24-GHz. The inductor value is limited to less than 1 nH, and

the capacitance is less than 100 fF. The gain difference at RF and LO frequency can be

estimated as the ratio of impedance at these two frequencies. Therefore, both notch filters

could provide about 10 dB suppression to the LO signal. In fact, the LO suppression only

depends on the Q of the inductors and capacitors, if the filters are tuned well.






Vtunel Vtune2



Notch Filter 2
Notch Filter 1

Figure 4-22 Improved transmitter RF front-end with notch filters

To provide more than 14-dB rejection, two notch filters should be added to the

circuit. From simulation, these notch filters also have nearly 2-dB in-band insertion loss.

To compensate this, additional driver stage is also included. Figure 4-22 shows the

improved transmitter RF front-end. The impedance of second order filter is small,

typically less than 100 Q, thus, it cannot be added to a node where the impedance is high;

otherwise the in-band gain will be significantly degraded. On the other hand, the third









order notch filter cannot be added to a node where the impedance is low, because it

almost has no effect on the gain at either the LO or RF frequencies. Therefore, a third

order notch filter is inserted between the second and third driver stages, while a second-

order filter is added to the output of the power amplifier. The capacitors in these filters

are formed using a combination of a metal capacitor and a MOS capacitor/varactor, so

that the operating frequency of the filter can be tuned, while maintaining relatively high

Q for the capacitor.


4.5 Fully-Integrated Transceiver

Since the transceiver of a tNode device is time division duplex (TDD), which

means only one chain is active at one time, one antenna can be used. This will make the

design more flexible and decrease the silicon area. Generally, a T/R switch is required to

control the connection between the receiver, transmitter and the antenna. However, it is

difficult to implement single-pole double-throw (SPDT) switches with low insertion loss

at 24-GHz using the 0.13-[tm CMOS process. For example, switches implemented in the

0.13-[tm CMOS process achieve 1.8-dB insertion loss at 15 GHz [50]. From simulations,

insertion loss of a switch operating at 24 GHz can easily go higher than 2.5 dB. Therefore,

at transmitting mode, nearly 50% of the transmitted power will be dissipated in the

switch. While in the receiving mode, the high insertion loss will degrade the input SNR

or increase the noise figure of receiver chain.

For the tNode transceiver, instead of using a T/R switch, the switching function is

merged into the PA and receiver [51], as shown in Figure 4-23. In the transmitting mode,

RxEn is set to low voltage level (around 0.4 V in simulation). The series LswCsw-tank

works as a notch filter for LO signal. At the same time, TxEn is set to VDD to turn on














Vg2




Lg


RXEn Csw TxEn


TX switch RX switch


PA LNA

Figure 4-23 Integrated transmitter and receiver RF front-end with distributed T/R
switches

transistor Msw. The gate of Mx1 is shorted to ground and this avoids high voltage swing

at MRXI gate. The impedance looking into the receiver will bejcoLg which is around 150

jQ. This high impedance assures the impedance matching between the antenna and PA

output to deliver maximum power while protecting the LNA. While in the receiving

mode, TxEn is ground to turn off Mw. RxEn is set to high voltage (VDD), so that Csw is

tuned to its maximum capacitance value. The resonant frequency of the Lsw-Csw series

tank moves to 13.5 GHz and it provides an inductive impedance of 100jQG at 24 GHz. In

simulation, this distributed switches scheme increase the noise figure for the receiver by

1.3 dB and decreases output power of the PA by 0.8 dB, which are much better than the

SPDT T/R switch. The synthesizer provides the 21.4-GHz LO signals to the receiver and

the transmitter. To assure sufficient LO drive, buffers have been inserted between the


I _








synthesizer and each mixer and divider in the receiver and the transmitter. Figure 4-24

shows the PLL output to different buffers. The PLL output buffer consumes 4-mA DC

current from a 1.5-V supply. It provides around 800-mV peak-to-peak voltage swing at

the TX and RX buffer inputs.


RX Down-conversion mixer

| 1:8 frequency divider
(receiver)
m .--- - - -

PLL J GSSG pad
.... _._____ ([for test only_)______.
1:8 frequency divider
(transmitter)

TX Up-conversion mixer

Figure 4-24 Integration of the frequency synthesizer, transmitter and receiver

4.6 Summary

In this chapter, the design and measured results of a fully integrated 24-GHz

transmitter chain are presented. The signal transmitted by the circuit with an on-chip

antenna can be picked up by an on-chip antenna 5 meters away or a horn antenna 95

meters away. The communication between a transmitting antenna and a receiver with an

on-chip antenna separated by 5 m was also demonstrated in [3]. These works

demonstrated that it is feasible to build a wireless transceiver with on-chip antennas for

short range communications. An integrated RF transceiver with a frequency synthesizer

has been implemented.














CHAPTER 5
MILLIMETER-WAVE VOLTAGE CONTROLLED OSCILLATORS

5.1 Overview of the Millimeter-Wave Oscillators

For direct conversion architecture, a voltage controlled oscillator operating at either

50 or 100 GHz is needed. With the rapid advance of high frequency capability for CMOS

technology, it is becoming possible to make CMOS circuits operating in the millimeter-

wave frequencies [52]-[70], which once were only possible to be realized using GaAs and

InP technologies. These millimeter wave CMOS integrated circuits can be used to satisfy

the ever-increasing demand for bandwidth in communication (broadband WLAN at 59-

64 GHz ISM band) as well as the emerging needs for RF sensor systems such as

automotive cruise control at 76-77 GHz and imagers at 94 GHz. The MMIC solutions can

provide the size, weight and performance advantages. Implementing millimeter-wave

systems using the low cost CMOS technology will lead to lower cost and higher

integration levels, and help to turn the relatively small volume applications mentioned

above as well as others into main stream high volume consumer applications.

Over the past five years, the maximum operating frequency of VCO's fabricated in

silicon technology has almost quadrupled from 25.9 to 117.2 GHz [52]-[56], [60]-[64].

Push-push VCO's using the second harmonic operating between 63 and 131 GHz [59],

[65], [67] have also been demonstrated in silicon technology. However, among these, the

bulk CMOS fundamental VCO's operating around or above 50 GHz usually show poor

phase noise, limited frequency range or large power consumption. In this chapter, the

design trade-offs and optimization techniques for high frequency LC-resonator based

69









VCO's are described. These techniques are utilized to realize a 59-GHz VCO with a

tuning range of around 5.8 GHz, a 140-GHz fundamental mode VCO, as well as a 192-

GHz push-push VCO using CMOS technology. This work also shows that even at 100

GHz, lumped element approach can be used to implement VCO's. As a matter of fact, the

circuit sizes can be reduced using the lumped elements instead of that based on

transmission lines.

A key to achieving oscillation in an LC oscillator is providing sufficient negative

resistance to cancel the losses in the resonant LC tank. This is particularly difficult at

high frequencies, because the core transistors cannot be large due to the capacitances they

add to the tank. To accommodate core transistors with a sufficient width, the parasitic

capacitances connected to the tank, including those of transistors, must be minimized. At

given operating frequency, the reduced parasitic capacitances also allow inclusion of

larger varactors for wider tuning range. The transistor size limitation can also be

alleviated by increasing the quality factor (Q) of tank to lower the loss. Therefore, low

parasitic and high-Q resonator, as well as low parasitic and high gain transistor design is

needed.

Section 5.2 describes the transistor model in the millimeter-wave frequency range

and discusses the operating frequency of the oscillators. Sections 5.3 and 5.4 discuss the

performance of passive components (varactor and inductor). The trade-off between the

quality factor (Q) and tuning range of varactor is studied in detail. Section 5.5 proposes a

low parasitic and high gain transistor design, while section 5.6 describes the architecture

of these millimeter wave oscillators. The measured results of the fundamental VCO's

between 59 and 140 GHz are presented in Sections 5.7 to 5.9. The performance of 192-









GHz push-push VCO is discussed in Section 5.10. Finally, the design method of

millimeter wave VCO's is summarized.


5.2 MOSFET Modeling for Millimeter-Wave Design

5.2.1 Gate Resistance and Non-Quasi Static Effect

Two figures of merit for quantifying the higher frequency performance of

transistors are popular. These arefr (or oir) andfmax (or (Omax), which are the frequencies

at which the extrapolated current and power gain are unity. For a VCO, in order to sustain

oscillation, the transistor must provide a power gain larger than one. Therefore, the unity

power gain frequency, fmax, is closely related to the maximum operating frequency of an

oscillator.

It has been well known that the gate resistance reducesfmax. The gate resistance is

usually just considered as the ohmic sheet resistance of polysilicon. To reduce the gate

resistance, the gate can be contacted on both ends and folded into multiple fingers.

Therefore, the gate resistance can be expressed as,

1 1 1 W/N 1 1 W
Rg =I x I-WINR Ix 12Xx RoJ ply (5-1)
S4 N 3 L -12 N2 L (5-1)

where, W and L are the width and length of the transistor, R ,poly is the sheet resistance of

the polysilicon, Nis the number of fingers, 1/3 accounts for the distributed gate resistance,

and 1/4 accounts for the two-ends connection.

This gate resistance is a bias-independent component at DC and low frequencies.

There is another gate resistance component with bias dependence at high frequency,

which is due to the distributed transmission line effect of the gate. To reduce this, a multi-

finger device with a narrow finger width should be used. The other effect is distributed









channel resistance, arising from the non-quasi static (NQS) effect. At frequencies NQS

effects cannot be neglected, an additional resistance is needed to account for the NQS

effect. From [71], [72], the equivalent channel resistance can be expressed as 1/(5gm).


distributed
channel resistance

Figure 5-1 Equivalent gate resistance model including distributed ploy-silicon
resistance and distributed channel resistance


5.2.2 Unity Gain Frequencies


Rg ,, Cgd


Cgs

Ri=1/(5gm)


Figure 5-2 Equivalent MOS transistor model including the gate resistance

Using the equivalent transistor model in Figure 5-2, the unity current and power

gain frequencies can be derived. A transistor can be considered as a two-port network.

The gate terminal is the input port, while the drain terminal is the output port. The source

terminal is connected to ground. The expression for OmT assumes the drain is terminated as









short while the gate is driven by an ideal current source. In addition, the gate-to-drain

capacitance is considered only in the computation of the input impedance, while its feed-

forward contribution to the output current is neglected. With these assumptions, the ratio

of drain current to gate current is

id V (5-2)
jo)(Cg, +Cgd)Vg ) (C, + Cgd)

which has a value of unity at the frequency of

CoT = 2f g = gm/(Cg +Cgd) (5-3)


Though the unity current gain of frequency, omT, is widely used, it dose not include

the effects of several components. As a consequence of the shorted termination, OT does

not include the drain-bulk capacitance Cdb or output impedance 1/gds. The current source

drive also takes out the series gate resistance term. Therefore, unity power gain frequency,

cOmax, which include these terms, is more relevant for high frequency oscillator design.

The computation of (Omax is generally difficult, so several simplifying assumptions are

used to make an approximate derivation possible (Appendix B) and it can be expressed as


Ormax = 2fmax = (5-4)
2 ma + 1/(5gm))gds + COTCgd)


Figure 5-3 shows the unity current gain frequency and unity power gain frequency,

versus the transistor gate length. For the transistor in 0.13-[tm and 90-nm processes, fmax

higher than 100 GHz has been reported. Therefore, it should be possible to build a CMOS

circuit running above 100 GHz. However, with device scaling, the contact/via area

decreases and these resistances increase very fast. For instance, the typical contact

resistances are 7 Q, 15 Q, and 45 Q in the 0.13-[tm, 90-nm and 65-nm process,










respectively. The higher contact resistance increases the gate resistance and slower the

increase offmax of the transistor with scaling.


1000
0 fmax
SfT


I_0 0

100
o

U- 0


10
10 100 1000
Gate Length (nm)

Figure 5-3 Unity current frequency, f, and unit power gain frequency,fmax, versus
gate length

5.2.3 MOSFET Radio Frequency Model

Including the parasitic capacitors and resistors at the drain, gate, source and

substrate, a complete RF subcircuit model for a NMOS transistor is shown in as Figure

5-4 [71], [73], [74]. R, and Rd are the source/drain resistances due to the resistive n+

active region. Cgsp and Cgdp are the parasitic gate-to-source/drain capacitances, mostly

from metal interconnections. Csb and Cdb are the source/drain junction capacitances, while,

Rb and Rdb are the series resistances of junction capacitances. The parasitic capacitances

at the gate and drain terminals will directly contribute to the LC-tank of the VCO and

lower the oscillation frequency.

The influence of substrate resistance, Rsub, is usually ignored for digital circuit

simulation at low frequency. However, at high frequencies, the signal at drain couples to

the source and bulk terminals through source/drain junction capacitance and the substrate









resistance. The substrate resistance influences mainly the output characteristics, and it

can lower the output impedance as much as 30% in 0.13-[tm CMOS process. The Cgb-

Rsub network also increases the noise figure of LNA.

G


R9 / Intrinsic MOSFET



0----^ -----H~----------r-- -----O
S Rs gdp Rd


Csb Cdb
1/(5gm)


Rsb 0.5Rsub 0.5Rsub Rdb


B B

Figure 5-4 RF model of an NMOS transistor with intrinsic and extrinsic components

5.3 MOS Varactor

Usually, at frequencies lower than 10 GHz, the Q of LC resonator is limited by

inductor loss. This is no longer the case at millimeter-wave frequencies. Because the Q of

capacitors (Qc 1/(coRC)) decreases with frequency, while that of inductor (QL ~ coL/R)

increases with frequency, the tank Q is limited by the Q's of capacitors at the millimeter-

wave frequencies. The optimization of layout and an accurate model for the MOS

capacitor/varactor are more critical at the millimeter-wave frequencies oscillators design.

5.3.1 MOS Varactor Structure

Figure 5-5 shows the top-view and cross-section of a MOS varactor. The top and

bottom plates are formed by silicided n+ polysilicon and n-well, which are separated by a

gate oxide layer. The thickness of gate oxide is only about 3 nm, which leads to high









capacitance density of 11 fF/[tm2 in the accumulation region. The poly gate is connected

at two ends to reduce the resistance. To increase the tuning range, the parasitic

capacitance must be minimized. In advanced CMOS technologies, where the minimum

metal-to-metal and contact-to-polysilicon spacing can be very small, the parasitic

interconnect capacitance can be large. To decrease the parasitic capacitance, the metal

contacts for n-well are placed 0.4 |tm from the polysilicon gate. Since the n-well is

usually AC-grounded, the increased n-well to substrate junction capacitance can be

tolerated. The metal interconnection of n-well is formed by only metal 1 and 2 layers, and

the gates are connected together using the metal and 8 layers. For comparison, a

varactor structure using the minimum spacing and a ploy gate dimension of 0.12 |tm x

0.28 |tm was also fabricated. The metal connection for n-well was formed by stacking

metal through metal6. The measured parasitic capacitance, which is mainly due to the

poly and metal interconnections, is about 3 times that of the gate oxide. This makes the

tuning range of the varactor close to zero.



I N-poly
Metal


IN I I NMetail poly


STI N+ N+ STI
SN-Well
SP-substratN-well
aP-substrate


Figure 5-5 Top view and cross section of the MOS varactor









5.3.2 Equivalent Model

A simplified MOS varactor model including a series Ls-Rs-C network is shown in

Figure 5-6. In the equivalent model, Cvar is the variable MOS capacitance and Cpar is the

fixed parasitic capacitance due to the metal and polysilicon gate parasitic. Rgate is the

resistances of poly gate, Rwe,, is the resistance associated with n-well/channel under the

gate, and Rmetai is those associated with the contacts, vias and metal interconnects at the

gate and n-well side, respectively. Other effects, such as n-well to substrate capacitance,

and substrate loss, are not included in the simplified model. More complete varactor

models are discussed in [74]-[75].

Cvar
Ls Rmetal I1 Rwell

Rgate
Cpar
Figure 5-6 Simplified MOS varactor model

As described in [76], the series resistance is

R l(R w x L2 +R, poly xW2)+ Rmetal, (5-5)
R ~12xWxL

where, Wand L are the width and length of each finger, Renw and Rpoly are the sheet

resistance of n-well and poly gate, Nis the number of fingers. The factor of 12 in the

denominator accounts for the double sided n-well and poly gates contacts. Rmetalumt is the

resistance from contacts, vias and metal interconnect in each finger. Because it decreases

with more contacts and vias, their numbers are increased to as many as allowed.

As also described in [76], if only the capacitors from gate oxide and resistance from

poly gate and channel are considered, the quality factor of this simplified model network

is,









1 12
QO-- =-, 1(5-6)
SoR,C )mCox(R,.nwL2 + ROpoIW2 + Rm,,et,,,WL) (5-6)

where co is the frequency and Cox is the gate-oxide capacitance per unit area. To increase

Q, smaller Wand L should be used. However, the penalty is larger parasitic capacitance

due to more metal interconnections, which decreases the tuning range. Since Rew, is more

than 50 times the Repoy, L should be made smaller, while W of a finger can be made

larger to reduce the parasitic capacitances. With the continuing scaling in CMOS

technology, the Q of varactor should increase with smaller gate length and lower n-well

sheet resistance. However, this increase will be tempered by the increases in the contact

and via resistances.

5.3.3 Experiment Results and Discussions

To experimentally examine these, structures with varying gate lengths were

fabricated in the UMC 0.13-[tm CMOS process. The average capacitances of structures

are kept approximately the same. The effects of pads are de-embedded using the open

structure formed by disconnecting the gate connection from the pad as discussed in [76],

[77]. One-port S-parameters of the test and open structures were collected using an

HP8510C 26.5-GHz network analyzer. Figure 5-7 shows the measured capacitance,

series resistance, and quality factor of a MOS varactor. The finger length (L) is 0.24 |tm

and width (W) is 0.64 |tm and there are 20 fingers. Figure 5-8 shows the C-V and Q-V

curves measured at 24 GHz for three varactors with different dimensions. The minimum

gate length of 0.12 |tm is used for structure (a), thus, it gives nearly the highest available

Q. A minimum Q of 24 is achieved at 24 GHz, which is close to the Q reported in [52].

When extrapolated using Q=l/(oRC), Q is about 9 and 6 at 60 and 100 GHz, respectively.







79


However, the tuning range is limited (Cmax/Cmin=1.75), though larger than 1.2 reported in

[52]. In structure (c) with a gate length of 1 rtm, the tuning range (Cmax/Cmin) is ~7. As


80


l_ 60

0
C-)
e 40


8 20


0


-1 -0.5 0 0.5 1
Vg (Volt)


-1 -0.5 0 0.5 1
Vg (Volt)


LL 20- ------------------


0 10


0
-1.5 -1 -0.5 0 0.5 1
Vg (Volt)


Figure 5-7 Measured MOS varactor capacitance, series resistance and quality factor at
24 GHz for a varactor with 0.64-jtm width, 0.24-[tm length and 20 fingers







80


expected, the penalty is lower Q of -2.5 in the accumulation region. A medium gate

length of 0.24 |tm is used in structure (b), which has moderate Q at 24 GHz of 12.5 and

an excellent Cmax/Cmin ratio of 3.5.


015
-o.5


40



30

0

LL 20



10


-1 -0.5 0 0.5 1
Vg (Volt)


1.5

(a)


0
-1.5 -1 -0.5 0 0.5 1 1.5
Vg (Volt) (b)

Figure 5-8 C-V and Q-V characteristics of the MOS varactors with different gate
dimensions


Figure 5-9 shows the measured minimum Q and Cmax/Cmin ratio of varactors with

varying gate lengths. The minimum Q decreases with the gate length, while the tuning










ratio increases. Depending on the operating frequency, phase noise, power consumption

and tuning range requirements for the VCO, a suitable varactor structure can be chosen

using a plot like this. For the 0.13-[tm CMOS process, the gate lengths between 0.18 to

0.24 jpm result good tuning and Q.


25 8

7
20
6 E

S15 5
u_ 4 o
-0 I n \ ^

10 --C/Cn 3

2
5 --
I-

1

0 0
0 0.2 0.4 0.6 0.8 1
Gate Length (itm)

Figure 5-9 Minimum varactor Q and Cmax/Cmin ratio at 24 GHz as a function of gate
length

5.4 High Performance On-Chip Inductor

Figure 5-10 shows the layout of differential circular inductor used in the 105-GHz

VCO. To reduce the capacitance to substrate, only the top metal 8 layer is used. The

metal 8 layer is 0.8 jtm thick and -5 ptm above the silicon substrate. The metal width is

3.6 |tm. Since the skin depth of copper at 105 GHz is -0.20 |tm, the metal width of

inductor can be as narrow as -6 x 0.20 = -1.2 |tm. The patterned ground shield is formed

using the polysilicon layer and each finger is perpendicular to the metal trace. The

spacing between polysilicon shields is set to -4 jtm to reduce the parasitic capacitance









without degrading the quality factor [78]. A lumped inductor model [79], [80], including

a series resistor, shunt capacitors, and substrate resistors, is used for the design. The

model parameters are extracted using Agilent Momentum, a 2.5-D EM field simulator.

The simulations show the inductance of loop with a diameter of 57 |tm is 90 pH and

Qbw [81] is -50 at 105 GHz. For the 59-GHz VCO, the inductor diameter is 89.6 [tm and

the trace width is 4.8 itm. The inductance is -200 pH and Qbw is -35 at 60 GHz. Lastly,

the interconnections carrying signals at the millimeter-wave frequencies have also been

modeled using the lumped inductor model.

To Curr nt Source

MetalS -
(Inductor Trace) Metall
(Ground)




4 J- Polysilicon
(PGS)

To Core transistors
Figure 5-10 Differential inductor layout

Center Tap

45 pH 0.70 0.70 45pH
1 2

0.7fF 1.4fF 0.7fF
T T
701


Figure 5-11 Lumped inductor model of differential inductor









5.5 Transistor Layout

As mentioned, to increase the oscillation frequency, the parasitic capacitance

connected to the tank must be minimized. For the VCO's operating near 60 and 100 GHz,

the capacitance of transistors in the 0.13-tlm technology is comparable or larger than that

from the varactors. Therefore, the parasitic capacitance of transistors must also be

minimized. Figure 5-12 shows the top view of cross-coupled transistors, which is similar

to that used in [82]. It consists of a top part (Mi) and a bottom part (M2) that are directly

cross connected from the drain to gate. This makes the metal interconnect between the

two transistors shorter which lowers the loss and parasitic capacitance of the

interconnections. The drains of fingers are connected together by metal6 lines. The finger

width of transistors needs to be kept small to lower the gate resistance. This however

increases the gate to body/substrate capacitance. Because of these two competing effects,

there should be an optimal finger width. The final finger width of 0.64 |jm is chosen to

maximizefm, [82]. From the measured results in [58],fm, is expected to be -120 GHz.


,, Source (GNP),
Active
To metal
SPolysilicon

MN Metall

N Contact
To metal
(unit: pm)
C.2i ~0.1
Source (GND)

Figure 5-12 Cross-coupled transistor layout









As was done for the varactor, the metal spacing is intentionally increased. The

spacing of source contact to gate is made 0.20 jpm, so that the parasitic gate and drain to

source capacitances are reduced at the expense of slightly larger source series resistance.

The increased source-to-body capacitance has negligible impact on VCO operation since

the source nodes are virtual grounds. The drain is usually made as small as allowed by

design rules to reduce Cdb. However, in the VCO, the gate to drain capacitors (Cgd) of two

core transistors are connected to the anti-phase nodes. As shown in Figure 5-13, due to

the Miller effect, the gate-to-drain overlap capacitance contribution to the tank is

2(Cgd +Cgd). Thus, the effective transistor capacitance at the drain node is actually

Cdb+4Cgd.


G I Gi~ var i Cvar
I var Cvar
GId I- I II

I I VC VCgd1



Cdbl Mdb2 g .... ICdT TCOgs2


Cgsl Cgs2
SCequ=4Cgd+Cgs+Cdb+Cvar

Figure 5-13 Capacitors in the VCO

Increasing the spacing between drain contact and gate decreases Cgd and increases

Cdb. Simulations show that the drain contact to gate spacing of -0.16 jpm minimizes the

effective capacitance added to the tanks. As stated earlier, the capacitance of transistors is

comparable or larger than that from the varactor. Because of this, the Q of LC-tank

strongly depends on the transistor. For the 100-GHz VCO's, since the capacitance of









transistors is much larger than that of the varactors, the transistor capacitance is expected

to determine the Q of the LC-tank.


5.6 Circuit Architecture

The VCO employs the NMOS cross-coupled topology and is shown in Figure 5-14.

The resonator consists of a single-loop circular inductor and an accumulation mode MOS

capacitor. The bias current is injected in the middle of the inductor by a PMOS transistor,

M7. This enables the modulation of Vdrain node by changing the Vbias voltage. As will be

described, unlike other VCO's, this is the main mechanism used to tune the VCO

frequency around 100 GHz. In addition, the buffer for driving the 50-Q load utilizes two

tapered stages to lower the capacitance added to the LC tanks.

VDD
VDD.BUFF VDDBUFF
Vbas M7

L4 L3 V L5 L6




50L 50L
L1 VTune L2 I5i6




M4 M3 M5 M6
M1 M2

On-Chip
Figure 5-14 Schematic of the proposed VCO

The PMOS current source is used to utilize the full range of the varactor without

requiring tuning voltages above Vdd or below zero. The varactor shows the best tuning

around zero gate bias. For the VCO in Figure 5-14, the top plate (gate) voltage of

varactor is set to -VDD/2 by using the PMOS current source on the top. When the bias