|UFDC Home||myUFDC Home | Help|
This item has the following downloads:
SWITCHED-ACTIVE AND PASSIVE, HYBRID FILTER FOR RESONANCE-FREE
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
This document is dedicated to my daughter, Nirvana Ardra who, from birth, brought
heaven closer to earth.
I express my sincere gratitude to my advisor Prof. Khai Ngo for his guidance over
the years. His knowledge has been invaluable to me. I thank him for the tremendous
kindness he has shown me on so many occasions. I wish to also thank my other
committee members for investing their time in reviewing my work, offering new insights
and making constructive recommendations. Their words of encouragement from time to
time have meant a great deal to me.
In addition, I wish to thank my dear friend and co-worker, Xuelin Wu, for his
considerable understanding of my work. Discussions with him have always been
enj oyable and fruitful. He has shared references that have broadened my knowledge and
helped to keep me on track. I also acknowledge the help of my other friends Yus Ko,
Bharath Kannan, Shengwen Xu, Santanu Mishra, Alex Phipps, Ming He and C.G. Cho.
Most notably, they have assisted me in using various software and laboratory equipment,
finding parts, and loaning me tools. They have also been helpful in discussing ideas and
The funding for this research was provided by CPES under an NSF grant. I'm
grateful to these organizations' generous support. Furthermore, I owe Prof. Fred Lee
thanks for including me on the CPES research team and for funding my portion of the
proj ect. I thank Dr. Ming Xu for sharing key references with me and I thank Julu Sun for
allowing me the use of his VRM design in my simulations.
I also acknowledge the motivation, support and compassion of my family, most
especially, my wife Vanessa Vidya, my parents and my brother, Avinash.
Finally, I thank God Almighty for bringing me this far at least with such good
TABLE OF CONTENTS
ACKNOWLEDGMENT S .............. .................... iv
LI ST OF T ABLE S ................. ................. viii............
LI ST OF FIGURE S .............. .................... ix
AB STRAC T ................ .............. xiv
1 INTRODUCTION ................. ...............1.......... ......
1.1 Review of Relevant Research ................ ...............2............ ...
1.2 Research Goal and Contributions ................. ...............11........... ...
1.3 Practical Basis for the Experimental Setup ................. .......... ...............13
1.4 Content Organization ................. ...............15........... ....
2 DE SIGN THEORY AND ANALYSIS ................. ...............16........... ...
2.1 Equivalent Passive Filter Model and SAF Topology .............. ...................16
2.2 SAF Design for the Damped Passive Filter (EAVP) .............. .............. .21
2.3 SAF Design for the Lossless Passive Filter (non-EAVP) ............... ..............24
2.4 Loss Calculations ........._._.._......_.. ...............27....
2.5 Design M ethodology ........._....... .. ......._. ...............29....
2.6 Design Methodology Illustrated by Examples............... ...............33
2.6.1 Damped Passive Filter Example ........._._.._....._.. ........_.._......33
22.214.171.124 Design for unequal esr's ............._.._ ......._.._. ........_.._........3
126.96.36.199 Gate drive delay, capacitor es1 and load di/dt ............... ...............39
188.8.131.52 Overall design sensitivity ........._.._.. ......._ ........._.._......40
2.6.2 Lossless Passive Filter Example ........._._.._....._.. ........_.._......41
2.7 Design Synopsis............... ...............4
2.8 Variations on Circuit Topology .............. ...............46....
3 EXPERIMENTAL RESULTS AND PRACTICAL IMPLEMENTATION
IS SU E S .............. ...............49....
3.1 Low Speed Experiments .............. .. ...............53...
3.2 Step-Current Electronic Load, I-load............... ...............61.
3.3 Single Stage Hybrid Filter Experiment ................... .......... ................. ..69
3.4 Operation of the SAF with Multi-stage Passive Filters .............. ..................76
3.5 Feedback Control Feasibility ................. ...............81................
3.6 Applying the SAF to LAF Topologies ................. ...............83........... .
3.7 Pre-charging Mechanism .............. ...............85....
4 APPLICATIONS OF THE HYBRID FILTER ................. ................ ......... .89
4.1 System Architecture and Lumped Element Model ................ ............... ....90
4.2 SAF Design for Various Locations ................. ..... ........... .... .. .......... ......9
4.3 SAF Mounted On Package and Inj ecting into the Package Capacitor. ............94
4.4 SAF Inj ecting into the Socket .....___.. ..... .._... ....___.. ..........0
4.5 Applying the SAF to Multiple Stages ................. ............... ......... ...113
4.6 Alternative Inj section Points and Relative di/dt' s.........._..... ... ....._._.. ......1 15
4.7 Summary of SAF Application to Microprocessor Power Delivery Systems.118
4.8 Extension of EAVP to a Transmission Line Solution ................. ................119
4.9 Further Applications of the SAF ................. ...............120..............
4.9.1 Switched Coil Damping ................. ...............120...............
4.9.2 Retrofit Filters .................. ... ... ........ ....... ..... ...... .........12
4.9.3 Auxiliary Power Regulation to Complement EMI Filters ................... .122
5 CONCLUSION............... ...............12
A ACHIEVING EAVP WITHOUT AN ACTIVE FILTER ............... ............._..127
B LINEAR MODEL EXTRACTION OF BULK VOLTAGE REGULATOR ...........136
LIST OF REFERENCES ........._._.._......_.. ...............139....
BIOGRAPHICAL SKETCH ........._.._.. ...._... ...............142....
LIST OF TABLES
1.1. Sampled performance in the last seven years ................. ............... ......... ...4
1.2. Relative advantages of the SAF over other AF topologies. ................ ..................12
1.3. Power Delivery Path Model Parameters. ............. ...............14.....
2.1. Summary of design equations. ............. ...............30.....
2.2. Parameter and performance values for the circuit of Figure 2. 16. ................... ........43
3.1. List of Symbols. ............. ...............50.....
3.2. Hybrid filter parameters in low-speed experiments. ................ ..................5
3.3. I-load measured data and calculated performance parameters. .............. .... ............67
3.4. SAF and single stage passive, hybrid filter design and performance.............._..... ...72
3.5. Comparison of the passive filter in the experiment with the ideal EAVP filter.......78
4.1. Power Delivery Path Model Parameters .............. ...............92....
4.2. SAF design for inj section at the package. ...._._._.. .... .._.... ......__.. .......9
4.3. SAF design for inj section at the socket. ........._._._ ...._._. ......_._........10
4.4. Voltage deviation for the conditions given in Figure 4.25 ........._...... .................1 12
4.5. Multistage SAF design parameters for Figure 4.28 ................. ............ .........114
A.1. Design Values. ............. ...............133....
LIST OF FIGURES
1.1. Future Power Delivery Architecture. ............. ...............2.....
1.2. An example of a linear regulator ................. ...............4............ ..
1.3. Another example of a linear regulator ................. ...............5............ ..
1.4. Example of a linear active fi1ter ................. ......... ........ ...........
1.5. An example of a switched active fi1ter ................. ...............7..............
1.6. Another example of a switched active fi1ter ................. ...............9..............
1.7. Example of an auxiliary switching regulator used in fast transient regulation. .......10
1.8. Model of the microprocessor power delivery path ................. ................. .... 13
2.1. Multistage passive EAVP fi1ter model ................. ...............16...............
2.2. Typical waveforms of the passive EAVP filter. ....._____ ........._ ...............17
2.3. Equivalent single-stage passive fi1ter model. ............. ...............17.....
2.4. General multistage passive filter impedance and second order fit to dominant
resonance peak. ............. ...............19.....
2.5. Simplified diagram of the hybrid filter. The switched active filter is highlighted
in bold print. ............. ...............20.....
2.6. Comparison of LAF to SAF. ............. ...............28.....
2.7. Normalized SAF parameters: (a) log-log plot and (b) linear plot. ...........................31
2.8. Sample design specification of an SAF and damped passive, hybrid filter. ............33
2.9. SAF and passive, hybrid filter design for the example of Figure 2.8. ................... ..3 5
2.10. Hybrid filter response to 1 A step load. ............. ...............35.....
2. 11. Hybrid filter response for unequal esr's ................. ...............36...........
2.12. Corrected SAF design for Rc = 0 and R, = 0.1 02 ................ .................3
2.13. Corrected hybrid filter transient response. ............. ...............38.....
2. 14. Output voltage parameter sensitivity of circuit in Figure 2.9. ............. .................40
2. 15. Worst case, 20%, 128 run Monte Carlo simulation of circuit in Figure 2.9. ...........41
2.16. Example of SAF design for lossless passive filter. .............. ....................4
2.17. Output voltage response of the SAF designs for Figure 2.16. ............. .................43
2. 18. Relative improvement in regulation achieved by using SAF ................. ................44
2.19. Monte Carlo simulations showing hybrid filter performs as well as lossless
passive filter with 10 times the capacitance. .............. ...............45....
2.20. SAF response for 2Q = 1.4. ................. ...............46........ .
2.21. Variations of SAF: (a) original with grounded CAF, Switch near CAF; (b) floating
CAF, Switch near CAF; (C) grOunded CAF, Switch near load; (d) dual path SAF and
(e) SCAF, switched capacitor active filter. ............. ...............48.....
3.1. Experimental testbed. ............. ...............51.....
3.2. Hybrid filter circuit used in low-speed experiments. ............. .....................5
3.3. Low speed prototype: (a) plan view and (b) side view. ............. .....................5
3.4. Labeled section of a hybrid filter layout. ............. ...............56.....
3.5. Hybrid filter simulated response to 1-0 A, 50 A/ pu s, step-down response
showing usefulness in capacitor reduction for the same relative performance........ 58
3.6. Low-speed hybrid filter simulated response: (a) switched open, 1-0 A, 50 A/Cls
step-down, (b) switched 0.5 02, load pull-up. ......___ .... ... ._ ................58
3.7. Step-up output voltage response (a) without and (b) with the aid of the SAF.........58
3.8. Step-down output voltage response (a) without and (b) with the aid of the SAF. ...59
3.9. Step-down output voltage and VAF TOSponse (a) without and (b) with the aid of the
SAF ................. ...............59.................
3.10. Circuit schematic of 5 A, 5 A/ns electronic load with built-in sensing. ..................62
3.11. Internal and external I-load transient performance. ............. .....................6
3.12. Layout of I-load IC ................. ...............64..............
3.13. Bonding diagram for I-load IC ................. ...............65.............
3.14. Completed I-load circuit ................. ...............65...............
3.15. Load voltage waveform for 1 A step (a) at 20 ns/div and (b) 10 ns/div. ................67
3.16. Load voltage waveform for 2 A step (a) at 20 ns/div and (b) 10 ns/div. ........._......68
3.17. Load voltage waveform for 3 A. ............. ...............68.....
3.18. I-load circuit together with SAF and single stage passive filter. ............. ................70
3.19. Simplified circuit topology for SAF and single stage passive fi1ter test. ................71
3.20. SAF and single stage passive, hybrid filter tested using I-load at 0.5 A with (a)
VAF = OV and (b) VAF = 1.2 V ................. ...............73.............
3.21. SAF and single stage passive filter tested using I-load set at 1 A with (a) VAF = 0
V and (b) VAF = 2.3 V. ............. ...............74.....
3.22. Effect of delay error in hybrid filter response. ............. ...............75.....
3.23. Spike induced by es1 of point-of-load capacitor. ....._____ ... ......_ ..............76
3.24. Circuit used to test SAF with multi stage passive filter. ............. .....................7
3.25. Output voltage, volt), on a long time scale ................. ...............79...........
3.26. Waveforms of volt) showing the SAF working with multi-stage passive filter for
(a) VAF = OV and (b) VAF = 1 V at 0.5 A step load. ............. .....................7
3.27. SAF operation with the multistage passive filter at 1 A step load, and with VAF
= 2.3 V ......... ...............8 1......
3.28. Hybrid filter with feedback control on the SAF ................. ......... ................82
3.29. Output voltage of hybrid filter for various step loads. ................ ......................83
3.30. Linear active filter (left of iLOAD) operating with single-stage passive filter........84
3.31. Pre-charging mechanism: Resonant converter (a) open, rest position '0', (b)
charging position '2', (c) free-wheeling position '1', and (d) sample timing
diagram .......... ...............86......
3.32. Pre-charging waveforms. ............. ...............87.....
4.1. The 2004 Power delivery architecture system diagram. ............. .....................9
4.2. Lumped element model corresponding to Figure 4.1. ............. .....................9
4.3. Modeling the impedance seen by SAF inj ecting into package node...............__.. ....95
4.4. Magnified view of Figure 4.3 showing resonance peak approximation. .................95
4.5. Equivalent passive filter with respect to Vpkg inj section point. ............. ..... ........._.96
4.6. SAF design using the single stage model of Figure 4.5. ................ .............. .....97
4.7. Performance improvement with SAF; simulated with linear power path model.....98
4.8. Performance improvement with SAF; simulated with linear power path model;
magnified view. .............. ...............99....
4.9. Load current relative to currents associated with branches of the package node
with SAF operating. ............. ...............99.....
4.10. Schematic section showing the SAF injecting into package. Vmb is connected to
BVR output and Vup is connected to BVR sense. ......____ .... .. ..___............100
4. 11. Improvement in vpkg USing the SAF; simulated with switching regulator. .............101
4.12. Comparison of waveforms at package and die with SAF injecting at the
package. .......... ...............102......
4.13. Comparison of waveforms at package and die with SAF injecting at the
package; magnified view ................. ...............102................
4. 14. Effects of delay in the circuit of Figure 4. 10. ................ ............... ........ ...103
4. 15. SAF current and energy loss in the circuit of Figure 4. 10. ............. ...................103
4. 16. Graph of current in Lpkg, iLpkg, for the circuit of Figure 4. 10 with 20 A/ns di/dt at
the die (load) ................. ...............104................
4. 17. Allowable range of di/dt when inj ecting at package. ................ ............. .......105
4. 18. Adjustment of RAF to correct for low di/dt ................. ...............106...........
4.19. Circuit used to find equivalent passive filter with respect to Vsk. .........................107
4.20. Impedance with respect to Vskt of the multistage passive filter and its equivalent
single stage model. ............. ...............108....
4.21. Equivalent single stage model for the circuit of Figure 4. 19. ............. ..... .........._.108
4.22. Schematic section showing an SAF used for injection at the socket. ....................109
4.23. Performance of the SAF used for injection at the socket; simulated with 2004
linear model ................. ...............110........._ .....
4.24. Performance of the SAF used for injection at the socket; simulated with
switching regulator ................. ...............110................
4.25 Output voltage, VPKG, with SAF used for inj section at the socket. .........._..............11 1
4.26. Output voltage, VPKG, with Ins, 10 ns and 20 ns SAF switch delays. ................... .112
4.27. SAF current waveform and energy loss for the circuit in Figure 4.22. ..................1 13
4.28. Two-stage hybrid filter with an SAF on each stage. ................ ......................114
4.29. Performance improvement using two-stage hybrid filter. ...........__.................115
4.30. Alternative hybrid filter design to that in Figure 4.28.............__ ..........__ .....116
4.31. Relative performance of hybrid filter design given in Figure 4.30. .....................1 16
4.32. Comparison of node voltages. .........._._ ...._.... ...............117....
4.33. Current and voltage waveforms showing relative di/dt' s with respect to load
regulation performance. ................ ...............118......... ......
4.34. Extension of EAVP to transmission line ................. .....__ .........__ .....11
4.35. Damping a switched coil: (a) using single capacitor and (b) an SAF. ...................120
4.36. Effects of SAF on voltage across switch and circuit losses. ............. ..................121
A.1i. Transient response with and without AVP. ....._____ .... ... ._ ...........__.....2
A.2. Single stage model. ............. ...............128....
A.3. Design equations for single filter stage. ............. ...............129....
A.4. Example of a 4-stage Power Delivery Network ................_ ................_.......131
A.5. Equivalent circuits of decoupling stages starting from load to source. ..................1 31
A.6. Resultant passive filter design. ...._ ......_____ ......._ ............3
A.7. Output impedance of circuit in Figure A.6. ............. .....................134
A.8. Pull-up transient response of circuit in Figure A.6. ............. ......................134
B.1. BVR step-load response with known output filter capacitor. ............. .................136
B.2. Equivalent linear model of the BVR ................. ...............137........... ..
B.3. Linear model step-load response ................. ...............137........... ...
Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy
SWITCHED-ACTIVE AND PASSIVE, HYBRID FILTER FOR RESONANCE-FREE
Chair: Khai D.T. Ngo
Cochair: William R. Eisenstadt
Major Department: Electrical and Computer Engineering
Passive filters in the form of cascaded stages of filter capacitors along the power
supply path have thus far been used to keep the supply voltage at the point-of-load within
specification-typically 100-150 mV of allowable droop under step loads of about 100 A
at 1-10 A/ns. However, in faster, higher current, lower voltage microprocessors, for
example, an all passive solution may not be realizable.
This dissertation describes a switched-active filter used as an auxiliary circuit to a
passive filter in order to improve the dynamic load regulation of a power delivery system.
Useful, second-order models are derived for the multistage passive filter about the
resonant peaks in impedance. Techniques to design a Switched-Active Filter based on
this design-oriented model are described and the SAF is shown to complement the
passive filter in order to minimize ringing in the general multistage power delivery
system. Specific application of the resulting hybrid filter to a microprocessor power
delivery system is described.
The SAF design comprises a switched-capacitor, pre-charged to the right voltage
and energy to naturally inj ect or absorb the current needed to maintain regulation through
pre-determined parasitic inductance and resistance. Once the parasitic inductance in the
SAF path is determined from layout or loss constraints, analytic design equations yield
the other SAF parameters which depend only on the passive filter, the ripple specification
and the maximum load current. The design is flexible enough for the additional circuitry
to be placed some distance away from the point-of-load and is therefore not constrained
in the same way as the passive filter.
The design methodology is tested by means of scaled models of the microprocessor
power delivery path. SAF experiments demonstrate a factor of five improvement in load
regulation at acceptable losses, 0.1 p J and 5 pu J with 20 nH and 200 nH DC path
inductance respectively, per 1 A step load, even with 20% tolerance on the design
parameters. Normalized power loss is about 0.4 W/MHzA. Simulations show feedback
control is feasible while revealing some of the issues that need to be considered in
The dynamic load regulation specifications of power management systems are
becoming increasingly stringent as electronic systems target higher speeds. In principle,
passive filters may be designed to meet future requirements. However, in certain
applications such as microprocessor power delivery, insufficient space for capacitors near
the point-of-load (POL) and excessive series interconnect inductance will prevent an all-
passive filter solution causing transient-induced ringing to exceed specifications.
Described herein is a design methodology which uses a novel switched active filter to
augment transient performance of a passive filter in order to efficiently achieve an almost
resonance-free response. The analysis, design and experimental verification of the
switched-active filter shall be the focus of the dissertation.
Although most of the application discussion will be geared towards future
microprocessor power requirements, the techniques developed in this work can be
applied to other situations where
* Parasitic path inductances limit available current slew rate.
* Intermittent load current steps occur.
* Sufficient bypass capacitors cannot be placed near the point-of-load (POL).
* A power efficient method of actively suppressing transients is required.
Examples and discussion of a few of the other possible applications will be
mentioned later on in this work.
1.1 Review of Relevant Research
Given present layout and packaging technologies, future power delivery systems
may require some form of active filter, which results in the system architecture shown in
Figure 1.1. In addition to the main power path from the bulk voltage regulator (i.e., the
source) to the load, there is an active filter block with the associated feedback control,
power source and pre-charging mechanisms. Total loss will be the sum of the losses in
the individual circuit blocks, not counting the load. Hence, the most efficient design that
still meets load regulation specifications will be an optimization of all blocks taking into
consideration any design-impact by one block on another.
Circuit AF Control
Figure 1.1. Future Power Delivery Architecture.
The required voltage supply, and hence the losses, for the active filter or AF is
overwhelmingly a function of the parasitic path inductance, LAF fTOm the AF power
source to the inj section point near the load. For a largerLAF, a higher voltage is needed to
achieve a given load current slew-rate or di/dt. For the same LAF losses in switched AF
circuits may be lower than in linear AF's thanks to the switched-capacitors' voltage
decay while it operates in pull-up mode, and thanks to energy storage while it operates in
the pull-down mode. The energy savings gained by using a switched AF may unwittingly
be lost if the pre-charging circuit is poorly designed. In certain cases this may be
acceptable, for the same reason that increased losses in the BVR may be acceptable:
power dissipated further from the load (and hot-points in general) is less of a thermal
concern. Still, optimizing for efficiency, resonant or switching converter techniques may
be employed to make the loss in the AF supply and pre-charging circuit almost
negligible. Sensing and signal processing in the control block should also consume
In the first place, if a passive filter alone can meet load regulation specifications,
the three additional active circuit blocks are not needed. A design method for passive
filters to meet these specifications has been reported already [Wai01, ManO4].
Unfortunately, the required inductance and capacitor values for these designs are not
always realizable. Capacitors today have neither high enough capacitance density nor low
enough parasitic series inductance to be used ubiquitously. Since the BVR is relatively
slow to respond, the capacitors in the passive filter must be large (and hence may not fit
in the available space, or, if available in small packages, the associated equivalent series
inductance or es1 may then be too large). The required capacitance may of course be
reduced by increasing the bandwidth (and hence the switching frequency) of the BVR,
but in doing so the BVR losses increase and efficiency goes down [RenO4]. With the
trend towards higher load currents and lower supply voltages [Sta04], eventually it may
become necessary to include the active filter, AF, together with its own power source and
Active filters, AF's, have been reported and continue to be a topic of research.
Table 1.1 summarizes the key types of AF's.
Table 1.1. Sampled performance in the last seven years.
[Bar05] [Lim03] [Wu0 1] [Ang00] [Amo99] [Poo99]
Circuit Sw. Linear Regulators Switched Capacitors LAF
Output (V) 1 .5 2.5 1-2 1.6 2.5 5
Load (A) 32 0.4 9 10 13.5 20
Load di/dt < 0.1 A/ns 4A/ns ~0.15A/ns < 0.1A/ns
Output ripple 14% 0.4% 1% 4% 2.4% 0.6-1%
Event freq. 50 KHz < 10 < 1 MHz 50-70 < 50 KHz 100 Hz
Location Off chip On chip Off chip On chip Off chip
PAF Pload (%) ~10 32 >33 < 10 33 > 33
Input supply 5 3.3 4 1.6 5 12-18
GBW (MHz) ~-0.1 0.03 250 > 200 N/A 3
The use of Linear Regulator techniques to implement the AF [Lim03, Wu01i], is
very inefficient, and excessive heat loss becomes a problem as load currents and transient
event frequencies increase. An early topology (Figure 1.2) shows that the "active filter"
block is made up of transconductance amplifiers where the transistors operate in the
refI Low- I
+ ** Co
Figure 1.2. An example of a linear regulator, redrawn from: [Wu01i].
linear mode. This topology is very lossy as high current flows through these regulating
components across which there must be substantial voltage to maintain linear operation.
Although the offset threshold voltages, 3V at the inputs of the transconductance
amplifiers keep the circuit off when the point-of-load capacitor in the passive filter, Co, is
sufficient to maintain regulation, for fast response and proper regulation, 3V must be
much smaller than the allowed ripple and in effect the linear regulator circuit is activated
very easily for any sudden load change or transient event. As the rate of these transient
events or transient event frequency goes up, the energy savings gained by this offset
threshold technique is minimal and is merely an artifact of proper biasing of the two half-
circuits. Linear regulator circuits, such as the one in Figure 1.3, with a class-A output
stage avoid its use entirely. The linear regulator, in this case, is placed in series with the
main supply bus and not in parallel with it. So even at DC the losses are high.
Figure 1.3. Another example of a linear regulator, source: [Lim03].
As summarized in Table 1.1, although the regulation performance in these types of
circuits is very good, 0.4% [Lim03] to 1% [Wu01], they are inefficient. Power loss is
comparable to the actual power delivered: P,,/F oad is one third or more. In principle, the
transconductance amplifier regulator [Wu01] placed in parallel with the supply bus
would be more efficient but in experiments they appear just as lossy as the classical linear
regulator which operates all the time.
By using a filter in the feedback loop to limit the operational range of a Linear
Regulator, the resulting linear active filter [Poo99] can be made to operate only when
needed for a short time after a sudden load change or transient event. One such topology
is shown in Figure 1.4.
5 V output
Figure 1.4. Example of a linear active filter, redrawn from: [Poo99].
The 33 K 0 and 10 p F extracts the reference voltage. The voltage across Rs which
is proportional to the load current is fed to the opamp circuit. The opamp with the 1 pu F,
and 50 K 0Z potentiometer in a negative feedback connection is configured as a
differentiator to sense di/dt of the load current. (In reality this circuit forms the
compensation block seen in Figure 1.1 and is a bandpass filter due to the opamp gain roll-
off at the dominant and the 2nd most dominant poles.) For a load transient, the circuit
senses the di/dt and the driver operates the push-pull output stage to source or sink the
required current to maintain regulation. At DC the circuit is biased so that the driver sets
the output transistors to be just barely off. These linear active fi1ter circuits can handle
higher load current and higher transient event frequencies than the Linear Regulator
approach, but are still lossy. Furthermore, the response is unpredictable if driven into
saturation mode by high di/dt' s. Note that the additional power source, shown as one
block in Figure 1.1, is shown explicitly in Figure 1.4 as Vcc. It is also understood to be
present in Figure 1.3 as well although it is not shown.
Switched circuits can be used as active fi1ters. Figure 1.5 shows the topology of a
single-shot prototype [Amo99] which demonstrated improved load regulation on load
step-up but the design is cumbersome, using two separate branches for current inj section
and qualitatively derived design equations. The required injection current is first obtained
Figure 1.5. An example of a switched active filter, redrawn from: [Amo99].
through simulation for the worst case step load; then the resistor and capacitor networks
are chosen such that the discharge closely matches the required inj section current. No
explicit design equations are given. The capacitors and extra charging voltage are such
that there is sufficient energy to regulate the transient. For the slow network the idea of
matching time constants is used as a guide in choosing components. The design of the
fast network is mostly done by trial and error. The parasitic inductance in the network is
not considered in the design phase. Although it is a switching scheme, the data listed in
Table 1.1 indicate that the relative efficiency, 33%, at moderate current, 13.5 A, and
transient event frequency, less than 50 KHz, is no better than the linear regulator included
in the survey. This suggests that the experimental designs were not optimum.
An integrated switched-capacitor AF has been reported by Sun Microsystems Inc.
[Ang00]. Although high di/dt, 4 A/ns, and transient event frequency, 70 MHz, have been
achieved, this performance is largely due to the process technology which allowed for
total on-die capacitance greater than 1.6 uF and low-esl. The key features of the topology
(Figure 1.6) are the switched capacitor charge pump circuit controlled by an average
voltage tracking loop. On a pull-up load transient, Cl and C2 are connected in series,
ideally doubling the effective voltage which then quickly discharges its energy into the
load, thereby providing pull-up regulation. By the end of the discharge time, the voltage
across the series combination settles to Vdd-Vss. If a pull-down transient comes,
capacitors are switched into a parallel bank at half the total series voltage, ideally half of
Vdd, a l0WeT VOltage which helps pull-down regulation as the capacitors absorb the excess
energy. However, a close study of the experimental data revealed the switch-capacitor
circuit itself only afforded small improvement relative to a static 1.6 uF on-die capacitor.
V., Tracking Loop I Vinst 4lonitor and Charge Pump Loop I
I nchip Vddiec atV/ 2 cag
I2 chmg I
quiesce at I-
Vddaz quiesce ;at V,
quaiesce atI quiese at Veldl
onhi 4'uieSCe atd V4/ harge 01*
Figure 1.6. Another example of a switched active filter, source: [Ang00].
Furthermore, since parasitic inductances and resistances were ignored in the
analysis, the circuit concept fails if applied to more general situations off-chip. The IC
implementation did show that if care is taken, and if layout constraints allow, the active
filter may run off of the main supply bus but there is no guarantee of this in general.
Since the circuit merely switches capacitor bank configurations, there is never a stiff
voltage source inj ecting current from the AF directly into the load. This makes the system
naturally more stable and easier to control because there is less chance for excessive
energy to be injected into the system. Furthermore, P,,lF oad < 10%is very good.
On the other hand, for comparable relative efficiency, the use of an additional
switching DC-DC converter in parallel with the main VRM [Bar05] requires more careful
control (both linear and non-linear control must be used). The diagram of the topology is
shown in Figure 1.7. The lower switching regulator is designed to be the main power
supply, with linear feedback control and low ripple. Consequently it is slow. The output
voltage sense signal, however, not only goes to the linear feedback control circuit but also
to a digital threshold logic circuit block that switches very fast to control the upper buck
regulator. This regulator is designed to provide high di/dt's without regard for switching
ripple. The inductance in the output filter of the upper switching regulator is about 10
times lower than the equivalent component in the main regulator, 0.7 puH versus 7 pu H.
For an input voltage of 5 V and nominal output voltage of 1.5 V, maximum positive di/dt
available from the fast regulator is only (5 -1.5)/0.7 = 5 A/ pus and negative di/dt is even
lower. In principle a larger input voltage and a smaller inductance would give higher
di/dt' s. However, with this method, the designer runs into trouble trying to find
sufficiently fast components far sooner than if using any of the other approaches
previously discussed. This is because, in addition to precise switch-on, very fast and
precise switch-off is necessary. This method, therefore, is better suited for slower, off-
Pir L~Aux~liary Convete r""""""' ~
1VIN" 1 "1 j"------------- M
we ... MaiulnCovre
FigureI~~I 1..Exml onauiiryswitchigrgltrue in attasen euain
1.2 Research Goal and Contributions
Thus far, the problem that has been largely ignored is two-fold. The impact of the
passive filter on the design of the active filter and the impact the design of the active
Filter, in turn, has on power loss have not been considered in depth. Furthermore, open
loop or saturation mode performance has not been studied in detail even though high di/dt
transients usually drive the AF into this mode of operation initially.
Therefore, the goal of the dissertation is to show the coordinated design of a
wwitched-active and passive hybrid filter topology that achieves dynamic load regulation
when driven in the open loop mode. First the design equations for the switched-active
filter or SAF are derived based on the equivalent passive filter components. These
equations and the corresponding design methodology are then verified experimentally.
The open-loop SAF circuit topology is essentially the equivalent saturation mode
circuit in the other AF topologies previously described. So the SAF design equations lend
additional insight into the design and performance analysis of these other AF topologies.
More importantly, the SAF may be used with feedback control or advance warning
signals in place of the other AF topologies for dynamic load regulation of power supplies
with relative benefits as summarized in Table 1.2.
Despite the excellent line and load regulation performance associated with linear
regulators, they are very lossy- especially when designed for continuous operation. The
linear regulator response is unpredictable when driven into saturation- it may incur too
much overshoot or undershoot, and may even oscillate. The SAF offers the potential for
lower loss and is naturally designed for a stable open loop response. The SAF does share
some common design concerns with linear regulators that are off at steady state, namely,
the threshold triggering mechanism and the choice of sufficiently fast components.
Table 1.2. Relative advantages of the SAF over other AF topologies.
Topology Features Relative Advantages of the SAF
Linear Stiff extra supply, Less loss, works when driven into saturation,
regulator wideband pe-charged cpitor serves as a soft supl
Linear active Stiff extra supply, Slightly less loss, works when driven into
filter narrow bandwidth saturation, pre-charged capacitor serves as a soft
supply (which affords better stability)
Switched Pre-charges and Simpler design, parasitic inductance included in
capacitor AF switches capacitor- the analysis and design, well-defined design
bank configuration methodology, may be implemented on-chip as
well as off-chip
Switched Stiff extra supply, pre-charged capacitor serves as a soft supply,
regulator parallel buck sharp turn-off not needed, simple linear control
converter toooy feasible (usually), works with higher di/dt' s
Linear active filters can be low loss and are comparable to the SAF in this respect.
However, since it operates off of a stiff power source, instead of a pre-charged capacitor
with a smoothly decaying discharge curve, the SAF may be designed for slightly lower
loss. Also due to the "soft" supply formed by the pre-charge capacitor, the SAF is again
likely to be more stable.
The SAF and by extension, the hybrid fi1ter, is far simpler to design and apply
practically than the other switched capacitor techniques surveyed. This is expected to
remain true even with the inclusion of the feedback control and pre-charge circuits for the
SAF based on promising simulations of the envisioned schemes. However, it is not
expected that the SAF will be as efficient as some of the other switched capacitor
schemes that are designed to be ideally lossless. One should note however that any
practical implementation of such ideally lossless switching schemes is very likely to
suffer from excessive ringing and may prove even more difficult to control and stabilize.
This is particularly applicable to the switched regulator approach. While high
efficiencies are possible, the design criteria placed on the control circuit are very
demanding. Given present technology, it is doubtful that this approach is capable of
handling di/dt' s much greater than 25 A/ p s.
The SAF will be presented as a flexible auxiliary circuit that may function in a
hybrid fi1ter to provide dynamic load regulation for a short time after a sudden load
transient. Furthermore, the SAF will be discussed as a building block which may be used
in other power delivery applications such as EMI filtering and switched-coil damping.
1.3 Practical Basis for the Experimental Setup
Equipment availability and cost constraints aside, the fact that the development of
the SAF was primarily intended for application to future microprocessor power delivery
systems, which themselves are yet to be fully developed and disclosed, posed a peculiar
obstacle in doing the related experiments. Presently, only a passive fi1ter similar to the
ladder network of Figure 1.8 is used to provide the necessary load regulation. Parameter
values for realistic models are given in the first two data columns of Table 1.3.
VLmh Rmh Vnkt Lnkt Rnkt. Vnkn V,,
Figure 1.8. Model of the microprocessor power delivery path.
Table 1.3. Power Delivery Path Model Parameters.
Model Model 1998 2004 Model Magnitude Frequency
Element Parameters Model 775pin LGA (Impedance) Down-
[Luo02] Scaling shifting
478 pin 100x 10x
Cmb [uF] 5 600 6 700 67 670
Cmb Lamb [pH] 800 700 70 nH 700 nH
Rcmb [mQZ] 1 0.6 60 60
Lmb Lmb [pH] 21 100 10 nH 100 nH
R~mb [mQZ] 0.1 0.2 20 20
Cskt [uF] 240 850 8.5 85
Cskt Lesk [pH] 340 140 14 nH 140 nH
Roskt [mQZ] 0.17 0.2 20 20
Lskt Lskt [pH] 120 40 4 nH 40 nH
Riskt [mQZ] 1.1 0.6 60 60
Cpg[u] 26 23 0.23 2.3
Cpkg Lepkg [pH] 4.6 1 0.1 nH 1 nH
Rpg[mQZ] 0.54 ~0.02 2 2
Lpkg Lpkg [pH] 6 ~ 3 0.3 nH 3 nH
Rpg[mQZ] .03 ~0.015 1.5 1.5
Cdie [uF] 0.53 ~1 0.01 0.1
Micro- Rdie [mQZ] 0.1 ~0.7 10 10
processor Ldie Assumed to be negligible
I ~100 A, + 5-100 A/ns ~1 A, 0.05-1 A/ns
The 2004 Model data was obtained through private communications with the
Center for Power Electronics Systems, CPES, headquartered at Virginia Tech. It was
taken as the best available power delivery filter to date using only passive elements.
Maintaining a desired ripple specification of about 100 mV, the model was scaled down
in magnitude 100 times to allow for testing on the order of 1 A at 0.05-1 A/ns. This
effectively scales all impedances by 100. All resistances and inductances scaled by 100x
while the capacitors scaled 1/100x. In order to make measurements of inductance and
time with acceptable accuracy, using the available equipment, it was further necessary (in
some cases) to frequency shift the model 10x to a lower range. Keeping all resistances
fixed, all capacitors and inductors in the model were scaled up 10x.
As a side-note, the wide range in di/dt stemmed from the difference in values that
are merely desired or claimed to values that are experimentally verifiable. Currents slew-
rates of up to 100 N/ns have been predicted and are certainly desired. However, the best
certifiable electronic load (manufactured by Chroma Inc.) is only capable of 1 N/ns and
the most aggressive claim by any electronic load manufacturer is 3.5 N/ns. Hence 5 N/ns
was aggressively taken as the best di/dt that could be measured.
The scaled model parameters of the last two columns in Table 1.3 served as the
basis for the experimental work. The stages most frequently used were at the package
subscriptt "pkg") and the socket subscriptt "skt") levels.
1.4 Content Organization
The remaining chapters delve into design theory, experimental verification,
applications and a discussion of issues related to the SAF.
The SAF topology is described and the design methodology developed in Chapter
2. Design equations for the SAF are derived, normalized and then used to identify key
design tradeoffs in the same chapter. In Chapter 3 the SAF theory is verified
experimentally by means of scaled test circuits comprising printed circuit boards, discrete
devices and custom IC's. Other issues relevant to practical application such as pre-
charging and control are also discussed. Chapter 4 delves into applications of the SAF,
focusing on its use in microprocessor power delivery systems. Ideas for future work are
presented that offer viable solutions when final stage capacitor es1 becomes significant
and the lumped element models breakdown. Further applications to EMI filter systems,
and active damping of switched coils are suggested before concluding in Chapter 5.
DESIGN THEORY AND ANALYSIS
2.1 Equivalent Passive Filter Model and SAF Topology
Since the SAF discussed herein is intended to supplement an imperfect EAVP
passive filter, the latter is first reviewed so that the issues can be identified and the
approximations made. Later it will be shown that the equivalent single stage model that
shall be derived for the EAVP passive filter is also applicable to multistage passive filters
Ir~L3 ~V3 ~1L2 V2 L1 VI 1~LOV
L3 R3 L2 R2' 1 R~ La Ro
+ + + u~
VLC3 L3 VLC2 L2 VLC1 L1
Figure 2. 1. Multistage passive EAVP filter model.
Shown in Figure 2.1 is an EAVP passive filter connected between a well-regulated
low-frequency bus VSde and a microprocessor load represented by io, Co, and Rco.
Parasitic inductance associated with Co, is assumed to be zero, while io is assumed to be
an ideal step for simplicity. Real effects of non-zero es1 and finite di/dt are discussed later
on. If the filter components are designed appropriately [Wai0 1], Zout o and the impedance
seen into each filter section equal a real value Rout n. As the reactive components become
progressively smaller toward the high-speed end, they are more difficult to realize, i.e.,
the EAVP design constraints tend to be violated at or near the load, resulting in a
resonant spike in the impedance.
Let the filter section responsible for the resonance peak in the output impedance be
the section containing Cn, Ren, Len, Rn, Ln, Le n+l, Rc n+l, and Cn+1. (The reader could
assume n = 1 to facilitate understanding.) This section is excited by iL n-1 at node vn, and
by iL n+1 at node vn+1. To see how the section could be reduced to a simple circuit that
facilitates SAF design (Figure 2.3, eventually), the key voltages and currents on the
section are plotted in Figure 2.2.
0 /VC n+1
Figure 2.2. Typical waveforms of the passive EAVP filter.
Figure 2.3. Equivalent single-stage passive filter model.
Consider first the current waveforms. Since iL n-1 Tises to its steady state much
quicker than iLn, Lt n-1 can be approximated as a step current source in the analysis of itn-
Thus, the inductive current iL n-1 OXciting node vn in Figure 2.1 is represented as the
current source iLoAD exciting node v(t) in Figure 2.3. On the other hand, since iL n+1 TisCS
to its steady state much slower than iLn, it can be approximated as an open circuit while
the SAF operates. Thus, iL n+1 is not seen in Figure 2.3; the series combination of Ln and
Le n+l is represented as L, and the series combination of Rn and Rc n+1 by R. Consider
now vLCn and vc n+1 waveforms. Since vLCn ~ 0 (except for a very narrow initial spike)
while iL n-1 is approximated as a constant current, Len is approximated as a short, leaving
Cn as C and Ren as Rc in Figure 2.3. Chapter 4 will address design options to deal with
Len when the magnitude of the spike induced by it poses a problem.
Since vc n+1 is essentially constant, Cn+1 is represented as the stiff source Vs in
The model of Figure 2.3 is also applicable to the general multistage passive filter
which exhibits multiple resonances as in Figure 2.4 for example. After obtaining the
equivalent impedance at node n, Zout n, by simulation or impedance analyzer
measurement, each resonant peak in the impedance can be fitted with a second-order
impedance curve corresponding to the model of Figure 2.3.
I I I I
Figure 2.4. General multistage passive filter impedance and second order fit to dominant
Given the simplified, yet generalized, section model Figure 2.3, resonance-free Zout
(= Rout) and transient response are achieved when the EAVP design constraints Rc = R =
JWC= Rout( = AV/AI are satisfied [Wai01i], where AI is the step load current and AV the
step output voltage.
Power is normally supplied from source, Vs through the "DC" or low frequency
path modeled as L in series with R,. High frequency components of the power to the
load flow mainly from the point of load filter capacitance represented by C in series with
some effective esr, Rc Altogether, L R,, C and Rc form a passive filter.
When these passive filter parameters cannot be designed, practically, to meet the
load regulation specification, the SAF (highlighted in Figure 2.5) comprising a switch, a
capacitor CAF With initial voltage Vm,, an inductorLAF, and a resistor RAF may be used
to achieve the desired response by inj ecting some additional current iAF (t) for a short
period after a sudden transient.
The SAF is a narrow-band fi1ter that is activated by an event scheduler to
deliver/absorb a short current pulse, and then remains off. A simple pre-charger using
VEXT and a resistor is shown to establish VAF.
The value of V4F is set to overcome inductance L.4F to provide the initial high
di/dt. C.4F is chosen to store just the required amount of charge needed for the voltage to
settle to steady state with a time constant dependent on R4F after which the main DC
path takes over. The SAF parameters are dependent on the passive fi1ter parameters hence
the hybrid nature of the overall filter operation. If the timing of the transient event is
known in advance, as is often the case in digital signal processing applications, the SAF
may be programmed to switch in time with the transient edge. Otherwise fast sensing and
feedback with acceptable delay may be used to control the SAF. In this work, however,
open loop control is assumed. Methods to deal with significant esl, the design of more
efficient pre-charge topologies and feedback control feasibility for arbitrary load profie
are future topics to be addressed later.
ton at 0 LAF
CAF() RAF let iv(t)=
sVXVAF(t. VAF FO AF 1AF(t) Vo-+Av(t)=
RL L iL(t)Z
C AI u(t)
Figure 2.5. Simplified diagram of the hybrid filter. The switched active fi1ter is
highlighted in bold print.
Extremely detailed and rigorous analysis of a 4th order network may prove
unnecessarily tedious. Insights drawn from the analysis of two special cases shall yield
useful design equations, a general design methodology and a qualitative understanding of
the circuit behavior in all cases.
In the first analysis, the ability to damp the passive filter with precise series
resistors is assumed. This is the best case design situation. The EAVP [Wai01] or purely
resistive output impedance response is imposed as a specific condition on the design.
Next, the worst case analysis is done by assuming a lossless passive filter which exhibits
maximum ringing. Finally, it will be demonstrated that the design equations converge in
the most practical cases. Loss calculations are shown to be applicable in both cases. By
comparing the voltage responses for both EAVP and non-EAVP designs, general circuit
design and response of the passive and switched-active hybrid filter will be discussed
along with examples simulated in Synopsys Saber.
2.2 SAF Design for the Damped Passive Filter (EAVP)
Filter design for purely resistive Zou, = R, commonly termed EAVP [Wai01],
ensures that the response to a step load current, iLOAD (t) = Al u(t), is a step output
voltage: v(t) = Vo_ + AV-u(t), where
AV = -AI -R (2.1)
and Vm~ is the unit step function. Just after the step load, Vo, = Vo_ + AV
To generalize the design of the SAF, the following normalized variables are
JL'C~L, C, R V -
Q = ;K, A ; Kc A ; KR F; K,, F 0 (2.2)
2R L C` R AV
Imposing the desired step voltage response to the specified step in load current, in
the Laplace frequency domain, the required transient current that must be inj ected by the
active filter in order to achieve perfectly regulated response appears as
AF 5) = AF (VAF Vo ) LA
1+ sRAFC, AF S2LAF AF
+ + ( 2 3 )
s s R, + sL 1+ sRc C s s +sR 1+ sRc C
ar 1-R/Rn, + s (L/R, (R+RcRn, R:)CI)+ s2LCT(RcR',; -RRX, )
s 1 +s (Rc C + L/R, ) + s2LC Rc/R,
Note, the network is linear in each mode of the switch. Therefore, the DC components
can be set to zero in deriving (2.3) in order to extract just the transient response. By
matching the corresponding terms in (2.3), the design equations for the SAF can be
derived as follows:
Rc = R, = A V/M = R (2.4)
LAF AF = LC -> KL = 1/Kc (2.5)
RAF AF = L/R + RC -> KR = (4Q2 +1 )Kc (2.6)
CAF(VF-Vo) = M (L/R -RC) K,, = (4Q2' -1 K (2.7)
Note the corresponding quality-factor of the SAF network,
JLAF AFI 2R ILAF A~F 2Q
QAF Q~ e~ (2.8)
RAF RAF 1+4Q2'
is always less than 0.5, or non-resonant.
Equation (2.4) is a requirement already derived in [Wai01]. It states that, for the
desired ideal EAVP response, the esr values in the model of the damped passive filter
must be equal to the desired output resistance. However, it shall be shown that the rest of
the design equations are still useful in improving regulation even if (2.4) is not satisfied
The characteristic frequency of the SAF must equal that of the passive filter, (2.5).
The time constant of SAF is equal to the sum of the time constants in the "DC" and
"high-frequency" branches of the equivalent passive filter, (2.6). For Q > 2, K,, is
essentially KR, and RAF Scales with VAF Via (2.6) and (2.7). Note that (2.7) shows VAF is
proportional to MI and the level of deviation from the passive EAVP condition (which
requires the time constants in the "DC" and "high-frequency" branches to be equal).
Furthermore, (2.7) reveals the design dependence on Q, the quality factor of the passive
filter alone when (2.4) is satisfied. IfQ = 0.5, the EAVP design constraint is met and no
SAF is needed. If Q < 0.5 the passive filter keeps the output voltage excursion within
ripple specification, but exhibits an overdamped settling response. The SAF might be
used to take advantage of the quick settling of the resonance-free transient. The SAF is
most useful when Q > 0.5; without it, there may be excessive ringing.
Furthermore, for Q > 1.25, QAF < 0.35, RAF AF 0+, LAF << R4F AF
response is insensitive to LA,, and the SAF behaves as an RC circuit with the time
constant, zAF RAF AF = RC + L/R = (1+ 4Q2)RC The current peaks almost instantly,
then settles to zero within 5tAF Note that the settling time of the SAF depends only on
the passive filter parameters.
With four SAF variables in three equations, there is one degree of freedom in the
SAF design. The set of allowable designs depends on layout and loss constraints.
2.3 SAF Design for the Lossless Passive Filter (non-EAVP)
With R, = Rc = 0, Vo, = Vo_ = Vs and EAVP is no longer applicable. Instead, the
ripple is now a general function of time, Av(t) which is described in the Laplace domain
1+RFAF 0- AF-S+A F-S2
-M L M
AV(s) = (2.9)
1+ s2LC 1+ sRAFC, AF S2LC
Typically for large M, the expressions in terms of SAF parameters in the numerator and
the denominator approximately cancel leaving -Ml Ll( 1+s2LC), the inverse of a sum
of a constant and a square in s, which appears as prolonged sinusoidal oscillation in the
time domain. With care, however, the SAF can be designed to cancel this factor that is
primarily responsible for the ringing.
LAF AF = LC -> KL = 1/Kc (2.5)
RAF A VVF-o(2.10)
equation (2.9) simplifies to a standard second order expression:
AV(s) = (2.11)
1 +sRAF, AF S2 LC
Keeping (2.2) while further defining
coo = 1IJLC (2.12)
JL.4F AF ,
a= + -4 F
b= 1 -QF
Alv\t) = -Me L
for which the extremum occurs at
and is given by
M' = Ms ~L
For the highly overdamped SAF, eF << 0.5, (eF < 0.35 is better than 12%
Av(t)- = -Mo,7 I CF OXp(2 r-Q,~ t,
M -L KR ,ep KL tK R
-20, In e,
max F F
-2 L In O ,
R KR A
Using (2. 1) and (2.2) in (2. 19), the extremum is approximately given by
BM, -e,,F )~L -2004FMl -R
= 2QQ4F r = 4Q2 Ly r, 04 <0.35
The expression for M'max is put in terms of M' so that comparison can later be
made with the SAF design equations for the damped passive filter.
Approaching the critically damped case, Q4F ~ 0.5,
Av(t)~ -> -Mg 2Lte 2eA (2.22)
tmax -> 2eAF )" (2.23)
B, 2eQli4Fl )L -4QQ4FMI R/e = 0.35 < Q, < 0.5 (2.24)
Now, in terms of M' the peak ripple of the lossless passive filter alone is
M~pk ()L =M = M R = 2QMk~ (2.25)
Thus for a desired My (2 Q improvement), simply set M'max = M' ; and (2.21) implies
Q, e, < 0.35 or K = 4Q K, Q >1.5 (2.26)
It should be noted that, as implied by (2.24)
Q = --> M fe(2.27)
In other words, the use of the SAF automatically provides a factor of e or better
improvement in ripple.
For L, C, M' and Ml specified, the SAF design equations for the lossless passive
filter are (2.5), (2. 10), (2. 13) and either (2.26) or (2.27). For practical purposes, (2.27)
may be ignored since (2.26) yields a conservative design when QAF ~ 0.5 If this is done,
the SAF design equations can be summarized as
AV = -M R (2.1)
LCLA C, R V -
.=yl K, = F.K, AF KR = F K, AF 0+(2.2)
2R L c C R R g A
LAF AF = LC -> KL = 1/Kc (2.5)
RAF = KR =(2.28)
VAF VO+ = RAF~ M- KV = KR (2.29)
Now, high-Q passive filters are approximately lossless. Hence the SAF design of
the damped passive filter converges to the lossless case as the quality factor, Q, increases.
2.4 Loss Calculations
The energy lost in the SAF in Figure 2.5 is the same as that lost in a series RLC
circuit which discharges to zero from zero initial current and (VAF, Vo, ) initial voltage:
and is valid for both the damped and lossless cases. For the damped (EAVP) case,
C-AV2 24) L-M2 42_2 L M2 4Q2_2
E 4Q _A (2.31)
tos 2Kc 2Kc Q Q
whereas for the lossless passive filter case,
L -AI2 LA AI 2
E AF (2.32)
'"s 2KcO F 2QjF
Since QAF < 0.5 always, the minimum loss in the SAF for the lossless case is 2LAF ~2
As Q2 gets larger, there is more ringing in the passive fi1ter, QAF ~ 1/(2Q) and the loss in
the SAF increases quadratically.
The SAF may be placed close to the load, in which case LAF is Smaller at the cost
of larger CAF Via (2.5), or well removed from the load, but then the loss increases.
However, when the SAF is located close to the load, as is possible in IC applications, the
space that is already allocated to bypass capacitors may be shared with the SAF
capacitor. When the SAF is far removed from the load, which is typically a "hot-point",
the extra power loss incurred may be easier to dissipate.
out = v(t)~ Vo- + AVu(t)
In = VEX ~ Vo, t > 0
In= vAF(t) iFt
out =~ v(t)~ Vo- + AVu(t)
~ Vo+ t > 0
Figure 2.6. Comparison of LAF to SAF.
If the input power supply were used to power a linear regulator or a linear active
fi1ter, instead of the SAF (Figure 2.6) then, for comparison, the loss in the linear active
filter or LAF, could be calculated in terms of SAF design values using the knowledge
that, for perfect regulation, iAF is the same regardless of AF implementation. So, using
Not surprisingly, LAF loss increases linearly with V,, However, given there must
be some parasitic inductance, L.F, ,the lowest possible V, is bound to be close to the
yAF ValUe Set by (2.7), neglecting drop-out voltage. Therefore, for the worst case step-
load, loss in the SAF is about half that of the best-designed LAF. Furthermore, since the
design of the LAF for efficiency has not been essential in the past, supply voltages used
in previously reported LAF's are considerably larger than the minimum value indicated
by (2.7) and the resulting loss is also unnecessarily large.
However, energy saved by the SAF may easily be lost if the pre-charge circuit for
the SAF is poorly designed. Resonant, switching converter techniques should be used in
the design of the pre-charge circuit for optimum efficiency. These shall be discussed in
Another indirect advantage of the energy-efficient design of the SAF is improved
stability. Oscillations and instability are more likely to be fed by a stiff source with
unlimited energy available. Since the SAF has stored only just enough energy to provide
regulation of a single step, while it operates, it fades into a purely passive (an inherently
2.5 Design Methodology
For convenient reference, the key design equations are summarized in Table 2.1. If
it is possible to design the passive fi1ter such that its equivalent single stage model
satisfies the all-passive EAVP criteria given in Table 2.1, then no active fi1ter is
necessary and loss may be kept to a bare minimum given by ~CAV2 approximately. The
all-passive EAVP filter design is discussed in Appendix A. However, more often than
not, the values of the passive components required to ensure the EAVP criteria are met
are not practical. The equivalent "DC" inductance, L, may be too large or the equivalent
point-of-load capacitance, C, may be too small.
Table 2. 1. Summary of design equations.
AV = -AI -R ; Q = K, AF.K, AF KR = F K A 0
2R L c C > R 8 A
All-Passive Damped Passive and Lossless Passive and Lossless Passive
EAVP SAF SAF and SAF
QAF < 0.35 0.35 Rc = R, = R Rc = R, = R AVmax= 2QQAFAV AVma= 2QAV/e
L = RC or QA, 2Q) QAF = 1/(2Q)
R F1+ 4Q2 LAF, AF LC LAF AF = LC
L =R2C LA A =L LF FLAF AFc,
RAF AF = L/R + RC RAF AFRFF
0 L/R RC
VAF V I o+ VAF = RAFI V O+ VAF = RAF~ V O
A Vmx = 4() Q AV ax, aa/
K, =1/Kc a KR
KR = 4Q2 +1 Kc K, 1/Kc K, =1/Kc
K, = 4Q2 -1 Kc KR =4Q2/IKc KR =4Q2/Kc
O K, = KR K, = KR
~1 C V2 LAF' 2 4Q2 _2 LAF 2 I
2 2 4Q2i 2Q F
= L I2 (SAF loss only) (SAF loss only)
Inability to achieve the desired L and C mandates the use of an active filter. If it is
still possible to design precise damping resistors in the passive filter, then the "damped
passive and SAF" design equations may be used to obtain an SAF that would
complement the passive filter to achieve a specified EAVP response. As noted already,
there is one degree of freedom in the SAF design. Once an appropriate value of LAF is
chosen, the rest of the SAF design is generated by the equations. It is further possible to
state the SAF design equations in normalized form as shown in the second-to-last row of
Table 2. 1.
10: \KC KC K V
Q = 11 KR
100 ~ I I Q= 1
100.01 0.1 K 1 '10 00 0.5 1 KL1.5 2
Figure 2.7. Normalized SAF parameters: (a) log-log plot and (b) linear plot.
This enables the SAF design parameters to be plotted against the relative size of
LA,, K,, for various values ofQ (Figure 2.7). The relative size of CA,,,Kc, is inversely
proportional toK,. All other SAF parameters vary linearly withK,. For high Q, KR
and K,, coincide.
If precise damping in the passive filter is not possible, then the SAF may be
designed assuming the passive filter is lossless since this is the case that exhibits the
worst ringing. For variation of esr' s between the lossless and perfect EAVP damped
cases, only minor tweaking of the design would be necessary to achieve the desired
regulation. The shape of the step-load response would of course vary depending on the
esr' s but the output voltage transient can be maintained within the tolerance band using
design equations for either the damped or lossless case, Table 2.1.
The choice of the appropriate set of design equations, whether damped or lossless,
is determined by the actual esr values and tolerance specifications in the system.
However, either set of equations would yield improvement in regulation performance. In
fact, for high Q, when there is a lot of ringing in the passive filter by itself, both sets of
design equations are equivalent and can be represented by plots as in Figure 2.7(a). This
can be seen more clearly by comparing the columns of Table 2. 1. For Q less than 1.5,
QAF is sufficiently close to 0.5 that the SAF may automatically improve regulation
beyond the design specifications. However, it should also be noted that for low Q, ringing
in the passive filter by itself is also not that bad. In fact, for Q less than 1, the voltage
excursion exceeds the tolerance band by so little that it may be possible to not include
any SAF with the design, if reducing circuit complexity and losses is more important than
achieving perfect load regulation.
The design methodology may now be summarized as follows:
* Find impedance at "inj section node".
* Model each resonant peak with single stage equivalent.
* Design SAF to overcome resonance.
* Calculate Q.
o Q < 0.5 SAF not needed for regulation.
o (Q < 1, small tweaks in passive filter vs small loss with SAF).
o 0.5 < Q < 1.5, use EAVP design equations if branch esr's ~ R.
o Q > 1.5, EAVP and Non-EAVP design equations are equivalent.
* Choose LAF based on layout/loss considerations.
* Design SAF for dominant peak (or an SAF for each peak).
* Test and tweak design if necessary
0 If esr' s cause an additional droop of 6v outside specification, then design
for a new AV that is 6v less than the original value used in the design.
o If nonlinearities cause the output voltage to vary outside the limit,
iteratively tweaking the design as for a slightly different value of LAF
without actually changing LAF may improve the performance.
Usually however, tweaking is not necessary.
Loss incurred in the SAF is typically much larger than that incurred in the passive
filter as it goes with the square of2Q, which is approximately the desired factor of
improvement in regulation. The loss may be reduced by lowering LAF but there is no
evading the fact that there is a tradeoff between regulation performance and loss. Without
the SAF and its associated loss, regulation specifications will not be met.
2.6 Design Methodology Illustrated by Examples
2.6.1 Damped Passive Filter Example
Figure 2.8. Sample design specification of an SAF and damped passive, hybrid fi1ter.
Figure 2.8 shows an example of a design problem in which the numerical values
are typical of low-current high-quality PCB applications and which is also, roughly, a
scaled (~1/100x) high-frequency equivalent of a high-current microprocessor power
delivery system. [Luo02]. Typically, the model of the passive filter, along with an
estimate of the total inductance in the SAF path, will be known.
In the example of Figure 2.8, the DC bias from the equivalent voltage source is 1
V. Since initially load current is zero, Vo_ = 1 V The equivalent point-of-load
capacitance is 10 nF and the DC path inductance is 1 nH. The esr in both branches of the
passive filter is designed to be 0.1 0Z which meets the EAVP criterion (2.4) with
R = 0. 1 Z. With the load set to be a 1 A step, AV = -0. 1 V from (2. 1). LA, ,Which is
usually fixed by the layout, is 2 nH.
1 nH 10 nF
Using (2.5), CAF = LC/LAF = 5 nF Equation (2.6) yields
1 nH/0.1 0Z + 0. 1 0Z -10 nF
RAF AFII, )( (~LR + RC) = = 2.2 0
while (2.7) gives, VA AFC, ) (L/R -RC) + (V + AV) = 2.7 V
The completed design is shown in Figure 2.9 and the waveforms showing the
circuit response to a 1 A load step at t = 10 ns is given in Figure 2. 10.
2.2 O L,
CA Rr2 nH
vAF(t AF AF AF(t)
X5 nF 0.1 0 1nH v(t)
2.7 V RL L ileit) Zu
S, 01 ,tLOAD
C 1 A step
Figure 2.9. SAF and passive, hybrid filter design for the example of Figure 2.8.
Sv~t) with SAF
v it) with out SAF
i0.0 100 20nr 30n 400n 500r
Figure 2.10. Hybrid filter response to 1 A step load.
Without the SAF, the output voltage (i.e. the voltage across the current source load)
drops by almost 300 mV; more than twice the desired 100 mV deviation. With the hybrid
design, however, perfect EAVP response (i.e. exactly 100 mV droop) is achieved.
Initially all load current is drawn from the point-of-load capacitor C However, the SAF
quickly takes over thereby preventing the capacitor, C, from being discharged too much.
While the current iL (t) builds up in the main DC path inductance, the SAF provides just
the right current, i.4F (t), to maintain regulation. By the time that the full load current
builds up in the DC path, the voltage across the SAF capacitor, v.4F (t), decays to the
steady state output voltage, 0.9 V in this example.
Thus far it has been assumed that the designer has precise control over all
parameters in the circuit. However, usually parasitic elements cannot be tightly
controlled. A discussion of a few of the possible variations from the ideal EAVP design
184.108.40.206 Design for unequal esr's
Hybri d Filter Output Voltage, yvf) ve time
00 10ln 20n 5C~n 400 50ln
Figure 2. 11. Hybrid filter response for unequal esr' s.
Final steady state output voltage depends on RL, the resistance in the DC power
path. Furthermore, the maximum voltage deviation is set by the larger of R, or RL
Figure 2. 11 shows the effect of zero resistance in L and then in C for the example design
above. For zero RL, the output voltage initially drops by Al R, = 0. 1 V and then rises
back to Vs without significant overshoot. The original SAF design, therefore, is sufficient
to maintain regulation in this case. With R, set to zero instead, there is not an
instantaneous drop in output voltage and the initial di/dt provided by SAF is slightly
lower than ideal. This, combined with the fact that the actual Q of the passive filter is
now larger than the original value, causes a bit more voltage deviation which causes the
output voltage to drop out of specification. However, it should be noted that even in these
two extreme cases of esr imbalance, the SAF still improves the regulation significantly
(ABmax = 120 mV) over the passive filter alone (Aymax > 240 mV).
If low esr in the capacitor, Rc poses a problem, the extra deviation incurred by this
imbalance can be corrected by simply designing the SAF for a lower AV In this
example, since the worse case output voltage deviation, 120 mV, was 20 mV more than
the desired AV = 0. 1 V; redesigning the SAF for AV = 0.08 V (Figure 2. 12) corrected
the problem. The output voltage transient can be seen in Figure 2.13.
2.6,6 0ZY LA
Figure 2.12. Corrected SAF design for Rc = 0 and R, = 0.1 0 .
Hybrid Filter Output Voltage, v(t) vs time
Rc = 0 Ideal EAVP
0. 1n 20n 30n 40n 50n
Figure 2.13. Corrected hybrid filter transient response.
With slightly larger SAF precharge voltage, VA,, and total path resistance, RAF, the
output voltage response was improved by 20 mV to achieve the desired load regulation.
The shape of the response is not perfectly sharp and flat as in the ideal design but,
instead, exhibits a very small amount of ringing that quickly dies out. Using (2.30), the
corrected SAF design incurs 14 nJ of loss per step load compared to just 8 nJ of loss in
the original design. However, additional loss in the SAF is only natural since the passive
filter is less damped with Rc = 0 02.
In summary, the iterative SAF design rule for unequal esr's can be stated as
* Design the SAF for the greater of the esr' s (R = max(R,, Rc) = -AV/AI ) first and
simulate the circuit performance.
* Then if necessary redesign the SAF for lower AV (or alternatively, lower R ) to
correct for excess voltage deviation.
In most cases however redesign would not be necessary.
220.127.116.11 Gate drive delay, capacitor es1 and load di/dt
Negative gate drive delay or turning on the SAF in advance of the load step must
be avoided in order to prevent output voltage spikes outside the acceptable voltage range.
For instance, if the SAF is turned on in advance of a pull-up transient it will tend to cause
an overshoot equal to the anticipated voltage drop it is designed to compensate.
Therefore, any delay fault that turns on the SAF when it is not needed could effectively
double the original magnitude of the ripple. This however is usually not a problem in
causal systems but timing precautions must be taken when the system is non-causal. If,
for example, an additional 10% voltage deviation is allowed for the effects of delay, then
the allowable delay can be approximated as td = C AV/(10AI) = 0.1IRC which is the
approximate time it takes for the voltage across the capacitor C to drop by 0. 1 AV .
Somewhat larger delay is tolerable if R, is kept low and the SAF is designed for lower
than required AV as previously described.
In practical applications, infinite di/dt does not occur; nor is the es1 of the point-of-
load capacitor, Le, ever exactly zero. One may approximate a transition from one current
level to another by an ideal step change if the transition time is much smaller than one
quarter the resonant frequency of the equivalent passive fi1ter (i.e. tq-, <<0.57<&LC ).
However, even when this approximation is made, the relative effects of the esl-induced
voltage spike, Le di/dt, must be considered. In most cases Le di/dt < AV/2 is tolerable.
The difficulties in dealing with the negative effects of delay, es1 and transient edge di/dt
are well recognized in general. For example, some microprocessor manufacturers find it
necessary to allow for the power supply voltage to exceed the DC load regulation
specification for a short burst of time just after a load transient edge [Int05b].
On the other hand, if the transient di/dt is so low that the step load approximation is
no longer valid, then, instead of a switching function, the transistor in the SAF may
operate as a controlled variable resistance. In addition the SAF pre-charge voltage may be
adaptively varied in response to a slower transient. The issues of esl, delay and control
are left as future topics to be discussed in Chapter 4.
18.104.22.168 Overall design sensitivity
Keeping all else fixed, individual hybrid filter design parameters were increased to
obtain roughly 25% voltage deviation from ideal in order to investigate design sensitivity.
As summarized in Figure 2.14, the circuit is most sensitive to variations in VAF '
Fortunately, this parameter can be controlled tightly. All other parameters may be varied
by 20% to 50% without significant degradation in performance. Furthermore, the graphs
show that increases in LAF, RAF OrL cause additional voltage drops just after a transient
step-up in load current. These effects may be compensated by increases in C VAF Of CAF
respectively and are consistent with the design equations.
Output Voltage, v(t) Parameter Sensitivity
095 AFX1 1
2 IICAF X 1.4
0.es LAFX 1.5 RAFX1.2
0.0 20n 40n 60n
Figure 2.14. Output voltage parameter sensitivity of circuit in Figure 2.9.
Assuming 20% tolerance on all seven circuit elements in the hybrid fi1ter, a Monte
Carlo, worst case, 128 run simulation was performed. By comparing the results with the
output voltage waveform without the SAF (Figure 2.15) it was observed that even with
20% variation on all circuit elements the hybrid fi1ter performs better than the passive
Output Voltage, v(t)
0.8 .( 20% Worst Case Monte
0-75 o SAF Carlo simulation
I I I
0020 40n 60n
Figure 2.15. Worst case, 20%, 128 run Monte Carlo simulation of circuit in Figure 2.9.
2.6.2 Lossless Passive Filter Example
Given the example hybrid fi1ter circuit shown in Figure 2.16, in which the passive
filter is lossless (since there are no damping resistors), an SAF design to achieve
AV = -0. 1V for AI = lA is desired. With L.4F = 2 nH, the same as before, C.4F = 5 nF is
also unchanged, via (2.5).
Av (-0.1 V)
Nominally, R = =-= 0.1 0Z via (2.1). Hence, from the definitions
AI 1 A
1 LZ 1 1 nH
of (2.2), 20 = -, I- = -~ = 3.16 and the passive fi1ter would ring with an
SR VC 0.1 Z V10 nF
amplitude Aypk = 2QAY = 316 mV or roughly three times the load regulation ripple
specification. In this particular example a few possible design solutions present
vAF(t CA AF2i(t)
-5 nF 1 nH v(t)
C -- A step
Figure 2.16. Example of SAF design for lossless passive fi1ter.
Since the desired correction factor, -, one may design the SAF
2Q 3.16 3 e
for Q4F = 0.5 according to (2.27) if AV in the load regulation specification is somewhat
loose. The advantage of this design is that it offers the lowest loss. For eF = 0.5,
JL !C, J2 nH 5 nF
RAF .4 A 1.265 2, using (2.28), and
V4F = R,,F )+ = (1.265 V)(1 A)+1 V = 2.265 V, via (2.29).
Another option is to iteratively design for lower and lower values over the range
0.35 < eF < 0.5 until an exact value of eF is found to meet the AV requirement. If a
solution does exist over this range, then one may conservatively design for
eF = 0.35 and forego the iterative process.
Alternatively, one may simply find eF USing the conservative design equation
(2.26) already derived. For this example (2.26) yields e,,F 0.316.
Assuming LAF is given, then, after, QFis determined, CAF may be calculated from
(2.5); RAF fTOm (2.28) and VAF fTOm (2.29). SAF designs for the three values of
QAF Obtained are summarized in Table 2.2.
The design for QAF = 0.5 has the lowest loss but does not quite meet the
Since Q = 1.58 > 1.25, the most conservative design is approximately the same as
that derived for the damped passive filter of the same quality factor (Figure 2.9). Output
voltage plots for the three designs are shown in Figure 2.17.
Table 2.2. Parameter and pefrmance values for the circuit of Figure 2. 16.
AF VA [V] RAF[ 2 Vax,, [mV] Etoss [nJ]
0.5 2.265 1.265 111 4
0.35 2.8 1.8 87 8.2
0.316 3 2 81 10
QAF = 0.5 (35.242n, 1.0222)
QAF = 0.35 (35.529n, 1.0064)
~QAF = 0.3i6
1 2.559n, 0.91898)
Q,, =0.35(12.955n, 0.91298)
QAF = 0.5 (13.COIn, 0.88908)
Output voltage response of the SAF designs for Figure 2. 16.
For QAF = 0.5, the maximum voltage deviation is consistent with that predicted by
(2.27). For all designs, the voltage waveshape roughly follows the corresponding analytic
expressions derived from the form (2.16). However, there is a small exponentially
decaying sinusoid superimposed on the ideal waveshape that is due to very slight
numerical deviation from the exact design and is indicative of the fact that the SAF is
trying to damp an infinite-Q network. Even so, the unwanted "ringing" is much less than
AV (22 mV in the worst case), it decreases with lower QAF and it dies out within 1.5 to 3
cycles. It is insignificant when compared to the oscillation induced in the lossless passive
filter alone by the step-load (Figure 2. 18). A 32-run, 20%, worst case Monte Carlo
simulation shows that even with 20% variation on all hybrid fi1ter elements, the
regulation is much better than the lossless passive fi1ter alone and is comparable in
performance to a lossless passive fi1ter with 10 times the capacitance (Figure 2.19).
0.6 15.00~5n 0.688 73) (13.(Din 0.88908)
I I I I I
0.0 1n 20n 30n 40n 50n
Figure 2.18. Relative improvement in regulation achieved by using SAF.
No SAF; C = 10 nF
No SAF; C = 100 nF
Figure 2.19. Monte Carlo simulations showing hybrid filter performs as well as lossless
passive filter with 10 times the capacitance.
2.7 Design Synopsis
It is convenient to characterize SAF design by two key parameters- 2 Q and K,.
The former is a measure of the desired improvement in ripple over the lossless passive
filter: pk = 2Q, via (2.25); and governs the transient response. Figure 2.20 illustrates
the use of the SAF in EAVP and non-EAVP designs to improve transient voltage
response. The SAF designed for EAVP achieves a perfect step "ripple" in response to a
step in load current. Without the SAF, the output voltage overshoots the allowed AV and
may be almost as large as 2QAV The SAF designed for the loss-less (worst case)
passive filter virtually eliminates all ringing without ever exceeding the ripple
Output Voltage, v(t) vs time ; 2Q = 1.4
2QAV No SAF; RL = I = R
No SAF; RL = I = 0 n
Figure 2.20. SAF response for 2Q = 1.4.
Power loss is dependent not only on Q but also onKL Although the transient
response is somewhat insensitive to KL, it is directly related to power loss via (2.3 1),
(2.32) and (2.26).
2.8 Variations on Circuit Topology
The basic SAF circuit is depicted in Figure 2.21(a). It is a switched damped
resonant circuit topology. As shown, the energy storage element, C.4F, iS directly
referenced to ground and the switch is mounted at the same location as C,.4F.However, it
is conceivable that if C.4F WeTO allowed to float with respect to ground as in Figure
2.21(b), this will afford more flexibility in the design of the peripheral pre-charge and
control circuitry. The switch will still be physically mounted in the same location as C,,4F
away from the load. The fact that C.4F is mounted further from the load is a natural
consequence of the basic problem- there is not sufficient space at the load for extra
capacitors. However, it should be noted that it may be possible to share the available
space for package capacitors with C.4F in Order to achieve much better performance than
if no SAF were used and C.4F Simply formed a fraction of CPkg.
The switch, which typically is smaller than C.4F may be positioned near the load as
depicted in Figure 2.21(c). In fact, for microprocessor and similar IC applications, the
switch may even be integrated onto the load IC.
Figure 2.21(d) shows a topology variation that consists of dedicated capacitors and
SAF paths for pull-up and pull-down transients. Recall that the preset voltage depends on
the expected transient. For operation in mid-range, either pull-up or pull-down transients
may occur. When apriori transient information is unavailable (as typically is the case),
one SAF capacitor will be precharged for worst case pull-up and the other for worst case
pull-down. The feedback control circuit will be designed to activate the appropriate leg in
response to any transient. This topology allows for quick response to either rising or
falling edges at the cost of doubling the ancillary circuitry needed. It is envisioned that a
simple manifestation of this topology may include two additional pre-charging switches
as shown in Figure 2.21(e). While one half of the SAF is performing AF operation, the
other half quickly pre-charges and vice versa. At DC steady state, both the SAF switches
are off while the pre-charge switches are biased on.
T ,, (a) (b) (c)
R, LAFRA LAF
V II V
AF AMAFP AFMM
AF AM (d) (e)
Figure 2.21. Variations of SAF: (a) original with grounded CAF, Switch near CAF; (b)
floating CAF, Switch near CAF; (C) grOunded CAF, Switch near load; (d) dual
path SAF and (e) SCAF, switched capacitor active filter.
EXPERIMENTAL RESULTS AND PRACTICAL IMPLEMENTATION ISSUES
This chapter describes the experimental verification of the hybrid filter design
principles, measures improvement in performance over the passive filter alone, and
demonstrates the issues that arise in practical implementation. In one practical scenario,
the SAF inj section point may be on the motherboard close to the BVR. Inductance in the
DC path is relatively large while the es1 in the capacitance at the injection node is
negligible due to relatively low di/dt or slow speeds at that point. If, on the other hand,
the SAF inj section point is near a high-speed microprocessor load, for example, es1 of the
point-of-load capacitor should be considered even with the SAF assisting in regulation.
With a wide range of applications in mind, low speed experiments, in which the load
di/dt' s and the es1 of the filter capacitor can be ignored, are first described. These first
experiments use a switched resistive load which differs from the ideal current source used
to model the load on the pull-up edge. Thus it will be shown that the design methodology
is applicable even when the load is not an ideal current source. Next, a 50-200 A/~ ps di/dt
electronic load circuit which is used in the remaining experiments is presented. The use
of this high di/dt load circuit to test the SAF in conjunction with a single stage passive
filter shall demonstrate the negative effects of filter capacitor esl. Finally, the SAF is
shown to operate independently of additional stages in typical multistage filter
The key list of symbols used in this work is given in Table 3.1.
Table 3.1. List of Symbols.
AF Active filter
BVR Bulk voltae reuao, such as a Voltae Reuao Module (VRM)
C Equivalent POL capacitance in simplified model of passive filter; Figure 2.3
CAF Filter cpitor for the AF (LAF or SAF)
Cm, Capacitor associated with the microprocessor die
Cn Capacitor associated ivith the nth node of passive filter in Figure 2.1
Cok Package caaitors, illustrated in Fiure 1.8
CM Socket capacitors, illustrated in Figure 1.8
EAVP Extended Adatve Voltae Positionin
Eloss Energy loss in the SAF per step load
iAF CuTTCnt fTOH1 the AF (LAF or SAF)
ie Current through C
icme Current through Cm,
iCpk Current through Cok
iL CureTTC1111Ough L
ipk Current through Lp
iP Current drawlib the microprcesr die
A~I Transient change in load current
L Equivalent DC pahinductance in smlfed model of pasve filter; Figure 2.3
LAF Linear active filter
LAF Inductance between AF power source, VEXT, and AF injection point
Le Equivalent series inductance of C
Lepk Equivalent series inductance of Co
LCskt Equivalent series inductance of CsM
Lmb Inductor between the BVR and Cskt
Lpk Inductor between Zpk and Zm,
LM Inductor between ZCsM and Zepk
LVR Linear Voltage Regulator
Q Equivalent quality factor of dmepasve filter
QAF QUality f8CtOr of SAF network
RAF Resistance between AF power source, VEXT~I, and AF injection point
Re Equivalent series resistance of C
Rk Equivalent series resistance of Cok
RCskt Equivalent series resistance of Cskt
Rm, Equivalent series resistance of Cme
RL Equivalent series resistance of L
SAF Switched active filter
SAF Settling time-constant of SAF
Tn- Width of esl-induced spike in output voltage
tr Gate drive rise-time
VAF Voltage across CAF
VAF Initial VO tae CTOSS CAF
VEXT~I POWer supply voltage for the AF
vo Ouptvolte or volte across load
Vpk Voltage at the node where Coeis connected; see Figure 1.8
vM Voltage at the uP socket
VP Voltage across the microprocessor die (voltae across load)
AV Allowable transient variation riding on Vo, the average of vo
aVmax Peak transient variation riding on Vo, the average of vo
AVPk Worst case ringing in vo in lossless passive filter alone i.e. no SAF used
Zear Impedance of CAF. including equivalent series inductance & resistance
Z~oe Imeac of Ck, includn euivalent series inductance & resistance
ZCskt Impedance of Cs,~ including equivalent series inductance & resistance
Zm, Impedance of Cme, including equivalent series resistance
ZLAF Ouptipdneof the LAF
ZIpk Impedance of Lk
ZuP Impedance seen by is,
HP6236B & Passive Filter I-Loaa: Ivlubl lc;;
Power Supply hp6024ps;
CCserl360-103 ind. Or
discrete switch + resistor
Figure 3.1. Experimental testbed.
Figure 3.1 depicts the experimental testbed. The passive filter is formed from
discrete capacitors with Ln, Rn and Rcn all parasitic elements associated with the
components and interconnect layout. When necessary an HP6236 power supply is used as
the BVR. When testing the SAF at high frequencies, the BVR is not necessary and may
be replaced by a short circuit as shown by the bold dotted line. For low speed tests, the I-
load circuit block was implemented by means of an STS9NF30L switch and 1205 chip
resistors. The need to force high di/dt in the high-speed experiments was accomplished
by means of a custom designed I-load emulator circuit in which a 10 mHl inductor biased
with high current was switched fast enough by means of a gate driver and mosfet IC to
emulate a pulsed current source.
Various versions of the SAF were tested with open loop control. Function generator
timing signals were sent to trigger gate drivers synchronously with load switching
signals. Relative delays between load trigger and other gate signals were accomplished
by inserting RC delay networks at the appropriate signal line termination. Precharge was
accomplished via a separate HP6236 power supply charging CAF through a variable
resistor. The resistance setting was such that the precharging time constant was much
larger than the SAF time constant; thereby minimizing any effect of the precharging
network on the actual SAF performance measurements.
In all experiments, inductances and capacitances were measured using the HP4194
impedance analyzer through a semi-rigid, twisted pair extension or a manufacturer-
calibrated BNC extension cable where appropriate. Maximum measurement error was the
larger of 4 nH or 20%. However, typically error was less than 10%. When the layout
geometries were simple enough, inductance measurements were further cross-checked
using analytic formulas. Capacitor measurements, lying in the range 1 nF to 0.1 mF and
made between 100 KHz and 1 MHz, had less than 5% error.
Resistors were measured using hand-held multimeters. Small parasitic resistances
were estimated from known current and voltage drops which were measured, along with
time domain waveforms, on the Tek2440 (500 MS/s) or TAS455 (60 MHz)
oscilloscopes. Data was recorded by hand and a camera was used to take snapshots of
The bill of materials corresponding to the experimental testbed described above is
* PCB mill and soldering kit
* Dual power supply (HP6236B) Quantity: 2
* Power supply rated for over 3 A (HP6024A)
* 1-60 MHz Function Generator (PM5192/5132)
* 100 MHz Network/Impedance Analyzer (HP4194)
* 60/500 MHz Oscilloscopes (TAS455/TEK2440)
* Pulse-current probe (Isensortech 711-S)
* 10/30 mOhm, 10/30 nC QG Switching gate charge NMOS/PMOS switches
(IRF341 5, STS9NF3 0L/STS5PF20V)
* 3 A, 10 ns risetime Gate driver (IXDD408SI)
* 1-10 uH smt coilcraft inductor kit
* 1-100 K potentiometer kit
* 1-2200 uF electrolytic capacitor kit
* 0.0001-10 uF ceramic (NPO/XRF) 0805 cap. kit
* 0.1-100 Ohm 1206, 0.5 W, resistor kit
* BNC-SMA adaptor kit
* SMA connectors and 50 Ohm cables and termination kit
* Standard DMM and workshop tools
Specific setup along with parts and quantities used are described for each
3.1 Low Speed Experiments
An experimental PCB test circuit based on Figure 2.5 is given in Figure 3.2. The
design parameters are given in the upper rows of Table 3.2. For AI = 1 A, AV = 0. 1 V is
chosen yielding R = 100 maZ and Q = 7 via (2.1) and (2.2). However, it is understood
that due to non-idealities the resulting worst-case A~max will be larger than AV A plan
view, a side-view and a labeled section of the prototype are depicted in Figure 3.3 and
Figure 3.4. The load is formed by discrete design: an STS9NF30L n-channel MOSFET
switch, two 1210, 1 0Z resistors and an 0805, 1 pu F capacitor, which provides the "high
frequency" power path. The "DC" power path starts from the power supply (not shown),
reaches SMA-2 through roughly 180 nH of twisted pair lead inductance, goes through
another 16 nH of trace inductance between SMA-2 and SMA-1, and finally reaches the
load through approximately 4 nH in the loop around the Isensortech 711-S current sensor.
The parasitic resistances in the "DC" and "high frequency paths" were both determined
to be less than 100 m a Therefore, ideal EAVP is not to be expected. Separate SAF
paths, each having about 40 nH of trace inductance, for pull-up and pull-down (shown
without components) were laid out alongside the main power path for convenient testing.
Since Q 7, design values for an SAF can be calculated using the EAVP SAF design
equations (2.4) through (2.7) even though it is understood the ideal EAVP response will
not be obtained. Components that were already available in the lab were used to achieve
the closest approximation to the calculated SAF design and simulations were then done
based on the chosen component values. Table 3.2 lists values used in calculation,
simulation and experiment.
Figure 3.2. Hybrid filter circuit used in low-speed experiments.
Table 3.2. Hybrid filter parameters in low-speed experiments.
Symbol Calculated Simulated Experimental
| AV| 100 mV 100 mV 100 mV
| AI| 1 A 1 A 0.8-1 A
tr(switch) 0 20 ns >20 ns
C 0.1 p F 0.1 p F 0.1 p F
Rc 0.1 0Z 0.05 0Z <0.1 0Z
L 200 nH 200 nH 200 nH
RL 0.1 0Z 80 m Q 80 m Q
LAF 40 nH 40 nH ~40 nH
RAF 4 0 5 0 5 0
CAF 0.5 p F 0.5 p F 0.5 p F
VAF -3.4/4.5 V -3.8/4.8 V -3.8/4.8 V
A Vmax +/-100 mV +200/-270 mV +200/-450 mV
A Vpk-pk 2.8 V 2.5 V 2.5 V
Loss 4 p J 4.6 p J 4.6 p J
The plan of the full layout of the prototype is given in Figure 3.3(a). In order to
highlight the layout of traces, the photographs were taken before soldering the pull-down
SAF and the pre-charging circuit components. A side-view showing the relative positions
of the Isensortech 711l-S current sensor, which was used to measure the load transient,
and the oscilloscope voltage probe is given in Figure 3.3(b). The pull-up SAF and load
switches were implemented with STS9NF30L n-channel MOSFETS; the pull-down SAF
switch was implemented with the STS5PF20V p-channel MOSFET. Switches were
driven with IXDD408SI drivers. Using a single gate signal to trigger all the gate drivers,
the relative delay between switching signal edges was negligible. In place of an ideal
current source electronic load, a real switched 0.5 0Z load was used so that on pull-up the
load switches from open to 0.5 0Z On pull-down, the load switch action very closely
approximates an ideal current source since the switch suddenly opens and load current is
forced to zero. Pre-charging was accomplished via a voltage source and resistor network
such that the charging time-constant was much greater than the SAF time-constant in
order to minimize error due to the pre-charge network.
Figure 3.3. Low speed prototype: (a) plan view and (b) side view.
Power Supply SMAL-2 Current Sensor Load
CAF Arcz RF SL-
lead. ( in V,,) Fsic
Layout section~- 10 cm X 3 cm
Figure 3.4. Labeled section of a hybrid filter layout.
The section view of Figure 3.4 shows the STS9NF30L MOSFET switch and
parallel pair of resistors that formed the load. The wire loop around which the current
sensor is mounted is perpendicular to the PCB plane and is only about 2 cm outstretched
length. Underneath the current sensor, the point-of-load capacitor, C, is soldered
between SMA-1 signal and one of the ground pins. Due to the proximity of SMA-1 and
the load, the load voltage is practically given by the voltage probe measurement at SMA-
1. Since the expected di/dt's are much less than 50 A/us, the es1 of C, Le = 1 nH, is not
expected to induce greater than 50 mV spike. In fact, no noticeable spike was observed
which validated the assumption that Le could be neglected. The SAF network is formed
by C.4F, SAF-switch, and RF in that order from left to right. With RF about 4-5 Ohms as
listed in Table 3.2, the switch on-resistance of about 25 mOhm (found in datasheets), esr
of C.4F Of about 15 mOhm (extracted from impedance curves in datasheets) and parasitic
trace resistance of about 20 mOhm (measured by voltage-droop/forced-current) are
altogether negligible. The parasitic SAF path inductance, L.4F, iS dominated by pin and
trace interconnect inductance which is approximately 40 nH. The es1 of C.4F Which can
be extracted from the impedance curves in the component datasheet is about 0.8 nH and
can be neglected.
As can be seen from Table 3.2, the values used in the experiment are not exactly
equal to those generated by the design equations nor do the parasitic resistances in the
passive filter satisfy (2.4). Therefore, the ideal EAVP response was not expected.
However, although the RF ValUe is larger than the calculated value, this is somewhat
compensated by the larger V4F magnitude. Saber simulation showed that even a non-ideal
SAF design, (roughly 20% error on some parameters, and non-zero risetime, tr ), can
reduce by over twenty times the point-of-load capacitance, C, required for a purely
passive solution (Figure 3.5). Alternatively, the SAF assists the given passive filter by
reducing ripple by more than five times that of the passive filter alone as shown in Figure
3.6(a). Load current (not shown) for the pull-down case is the same with and without the
SAF and is simply a 1-0 A step down. Furthermore, recalling the SAF was derived using
an ideal current source as the load since this is the worst case scenario that leads to the
S04 ~1Output Voltage [V]
02 11vs Tirne [sec]
II i /Load Current [A] vs
05 Time [sec]
00 lu 2u 3u 4u 5u 6u 7u
most ringing, Figure 3.6(b) shows that the SAF works just as well with switched resistive
loads, in pulling up the response to achieve the required step load.
Output Voltage [V] vs
o 7 No SAF, C = 2 7 t&
SAF, C= 0 1
00 lu 2u 3u 4u 5u 6u 7u
Figure 3.5. Hybrid filter simulated response to 1-0 A, 50 A/ p s, step-down response
showing usefulness in capacitor reduction for the same relative performance.
1 0 .
0.0 lu 2u 3u 4u 5u 6u 7u
Figure 3.6. Low-speed hybrid filter simulated response: (a) switched open, 1-0 A, 50
A/Cls step-down, (b) switched 0.5 02, load pull-up.
Figure 3.7. Step-up output voltage response (a) without and (b) with the aid of the SAF.
Figure 3.8. Step-down output voltage response (a) without and (b) with the aid of the
Figure 3.9. Step-down output voltage and vAF response (a) without and (b) with the aid of
These simulation results were further corroborated in the actual experiments. The
output voltage was measured using the Tektronix TAS455 60 MHz oscilloscope; first
without the SAF connected and then with the SAF connected to the output node.
Performance values are listed in the last rows of Table 3.2.
The step-up response in Figure 3.7 shows that the SAF was able pull-up the output
voltage to within Aymax, = 200 mVpp of ripple (or 200% of the DC droop) thereby
allowing for an almost square step in load current from 0 to 1 A. This result is the same
as that predicted by simulations, as listed in Table 3.2. Note that the droop in the current
waveform with time is merely an artifact of "DC settling" in the passive current sensor.
The slight peaking in output voltage and corresponding dip in current at the start of the
transient are due to capacitive coupling of the gate-drive signal onto the output as well as
timing error in turning on the SAF switch.
On step-down, the SAF reduced the ripple to within A'maxDN = 450 mVpp (or
450% of DC droop); an improvement of almost a factor of 5 compared to the case of the
passive fi1ter by itself (Figure 3.8). Although simulations showed 270 mVpp of ripple,
this was largely due to waveshape deviation from the piecewise linear approximation and
component errors, which, in this case, had a greater impact since the equivalent circuit
quality factor is higher.
Without the SAF, the ringing frequency obtained from Figure 3.9(a) is about 1.2
IVHz (6 peaks in 5 pu s), and is consistent with the value predicted by model parameters
listed in Table 3.2, 1 (2nL7t = 1.121VI~z The SAF time-constant was verified to be
about 2.5 pus as the vAF waveform, given in Figure 3.9(b), covered 63% of maximum
change in this time and settled to 0.6 V in about 12 pu s.
As summarized in Table 3.2, the simulations and experiments agree fairly closely;
and both support the underlying theory. With the exception of AT'maxDN the measured
parameter values were within 20% of those calculated using the design equations. Since
I 4F and R4F Were larger in the actual experiment the energy loss was also a bit larger
than calculated: 4.6 pu J instead of 4 pu J. Even with significant variations from the ideal
EAVP design, the hybrid filter reduced the ringing of a high-Q passive filter by more
than a factor of five. The major sources of error were: R4F = 5 0Z instead of 4 0Z; timing
delay between SAF and load current switches; and R, being much less than 100 m Q .
3.2 Step-Current Electronic Load, I-load
Since the switched resistive load used in the previous section is incapable of
forcing a step-up in load current, an IC was designed to be used in a switched inductor
circuit to emulate a sharp current step-load for transient testing of the hybrid filter.
Initially, the IC proposed was designed to achieve a step of 1-5 A. The on-chip slew rate
specification was 1-5 A/ns on die and up to 1 A/ns off-chip through 0.5 nH equivalent
package inductance. A sense resistor measurement path was built in for wafer probing but
was never used since it was later decided that all the hybrid filter test circuits were to be
mounted on the PCB level. Eventually, the I-load was verified for up to 2 A at 0.2 A/ns
through an estimated 2 nH of package inductance. The I-load was still useful because,
although lower than originally intended, the achievable di/dt was more than sufficient to
reveal the effects of es1 in the filter capacitor.
The complete circuit schematic is shown in Figure 3.10. The IC components are
contained within the dashed box. The supplies, large (10 uH) inductance, LS, and current
limiting resistor, R4, are external to the IC. The output filter capacitor, modeled as
C2+R3+L8 is normally open-circuited. The IC consists of a two stage gate driver, a big
MOSFET used as current switch, and another big FET and current-sense resistor which
may be used to measure switching performance.
This circuit cannot be implemented on PCB due to inherently larger trace parasitic
inductances but, instead, needs to be implemented on an IC technology with high
frequency devices (ft in the multi-GHz region). The IBM7WL process was therefore
VDDi D L P
rddj[ TP33 *ddl fetD~ 68,N~ I=0
In TP3 2 ,-,
In ldrmid Yg ~ TN33 tL~ ~ I LbiSV
mliTN33 v4 TN33 Sr2 utut V
l=0n I=4.n ~pk~
nT= s L4, 50 R2, 50 -re
-0' C2~t L
L8 '=" 4,P
Figure 3.10. Circuit schematic of 5 A, 5 A/ns electronic load with built-in sensing.
The inductor is biased to carry up to 5 A which normally flows through the big
FET switch, TN330, with the gate drive signal, "in", normally high. The FET has been
designed to dissipate a maximum of 250 mW. A standard 50 Ohm function generator
with relatively slow (30-50 ns) rise-times will then cause TN330 to switch off very fast
(in 1 ns), the external inductor acts like a current source as it keeps the current flow
continuous, all the bias current must now switch to flow either through the C2+R3+L8
external load path OR the TN333 measurement path. If Vbias is set to zero and
C2+R3+L8 connected then the external load path is selected. If Vbias is set to 2.5 V and
C2+R3+L8 is disconnected then the measurement path is selected. Thus this circuit
provides for switching in a very fast, positive current step to either an internal or an
external load. Of course the internal load is fixed for a given IC but the external load can
Figure 3.11 shows the transient performance obtained in Cadence simulation with
C2, R3 and L8, 10 puF, 100 maZ and 100 pH respectively. On chip, with VB set to 2.5 V,
the preset current switched from the "DC" path to the sense path in 1 ns resulting in the
corresponding voltage step shown. Externally, with VB set to 0 V, a resulting current step
of 5 A at approximately 1 A/ns and the corresponding output voltage taken across the
capacitive load are given. Since the esr of the capacitor was 100 m a with small esl, the
transient voltage waveform closely resembles the current waveform on the initial ramp
only it is inverted.
The actual design and layout of the I-load IC was done as a parallel array of over
ten thousand smaller cells. The entire array was sectioned in a ratio of 1:3 in order to
allow for isolated or independent use of each of the sections. The layout diagram is given
in Figure 3.12. The smaller section can be seen to occupy the lower region of the layout.
8.a; -.: /L6/MINUS
a: VT("/fetD") VT("/D")
1.40 .,: / OP
19n 22n 25n 28n
time ( s)
Figure 3.11. Internal and external I-load transient performance.
Figure 3.12. Layout of I-load IC.
The bonding diagram is shown in Figure 3.13. The IC is packaged in a 44 pin
plastic quad flat-pack. Entering and exiting current paths were alternated in the pin-out to
help lower the overall package inductance. The average inductance for the 1 mil diameter
bondwire used in this package assembly is 1 nH/mm and the average bondwire length
was 6 mm. Eight pins were allocated to carry the high current of up to 5 A. The complete
I-load circuit, given in Figure 3.14, was modified from Figure 3.10 as follows:
* Bias resistor R4, 0.2 0Z, was implemented with a 1 W, 1% current sense resistor.
* Load capacitor, C2, was 2 pu F with lower esr and higher es1 relative to the 10 pu F
capacitor with 100 m a esr and 0. 1 nH.
* Lpkg was closer to 3 nH with PCB interconnect to L5 included and was much
greater than the desired 0.5 nH.
Vdd 0 8 8 8
Inl 1 lu\3 [10 3
CO II\ \ 12 1
S1 -1 3- 3 CD-
D1 DE; Emn ~ LBS
S1 1EX 5 L 0 D
D1 EX3 C2 S32~
S1 1m 7 E.3 D
D1 ET 1 0 ED~Y~sS
SO CI 9 252D//
DO DE 120 ~ 7S
I lI O/1 233
In0 8 88 8
OCP_LO1FPERP (2BB MIL So carry~)
Figure 3.13. Bonding diagram for I-load IC.
L5 =10 pH
Figure 3.14. Completed I-load circuit.
To prevent breakdown without impacting initial transient response, a 2200 pu F
capacitor with 30 nH of interconnect inductance was connected across the 2 pu F load
With the above modifications, VDD = 3 V and VB tied to GND, the I-load circuit
was given a 0-2.5 V square wave input and the voltage across the load capacitor, C2, was
measured with the Tek2440 oscilloscope via an SMA connector and appropriately
terminated 50 0Z coaxial cable. Note the 50 0Z termination on the coaxial probe cable is
much greater than the impedance seen looking into the output node "V" and therefore the
measurement apparatus does not impact circuit performance. Waveforms obtained for
steps 1 A and 2 A are given in Figure 3.15 and Figure 3.16 respectively. The magnitude
and the di/dt of the load current step were determined from the point-of-load capacitor
voltage waveform, v(t) .
Since in general, the current through a capacitor, ic = C c, where vc is the
voltage across the capacitor, then, referring to the waveforms of Figure 3.15 and Figure
3.16, the magnitude of the load current step, starting from zero and jumping up to M, is
M = C2 (3.1)
where -is the slope just after the transient step and is relatively constant for some time.
The minus sign in (3.1) indicates the load current is pulled out of the point-of-load
capacitor. In principle the value thus obtained should be equal to the DC bias current in
the inductor, LS.
As the current ramps up in the point-of-load capacitor, a downward, esl-induced
voltage spike occurs. This spike peaks when the di/dt reaches a maximum and goes away
when the current step transition is complete, i.e. when the di/dt returns to zero. Although
the es1 of the point-of-load capacitor, L6, may be unknown, a fairly accurate estimate of
the di/dt can be obtained just from knowing the width of the spike, T, and the
magnitude of the current transition:
di/dt M/4II, (3.2)
Really, this value is slightly lower than the maximum di/dt but as such it is still a
useful measure. It can in turn yield an estimate of the es1 of the point-of-load capacitor:
esl, L6 = L (3.3)
where VL is the magnitude of the inductive spike.
Table 3.3. I-load measured data and calculated performance parameters.
Nominal V(R4) (R4 = dv/dt Tw VL MJ [A] (C2 di/dt esl, L6
DC 0.2 02) [V/ pu s] [ns] [mV] = 2 pu F) [A/ns] [nH]
1 A 201 mV 0.5 8 105 1 0.125 0.84
2 A 409 mV 1.0 10 160 2 0.2 0.8
Figure 3.15. Load voltage waveform for 1 A step (a) at 20 ns/div and (b) 10 ns/div.
Figure 3.16. Load voltage waveform for 2 A step (a) at 20 ns/div and (b) 10 ns/div.
Data taken from Figure 3.15 and Figure 3.16, together with other relevant DC
measurements were used to calculate the magnitude and di/dt of the I-load circuit. The
results are summarized in Table 3.3. The values of M obtained from the oscilloscope
measurements were consistent with the DC measurements. It was observed that the I-load
switched in 8-10 ns which was more than twice as fast as the switched resistive load
circuit. The maximum di/dt obtained was 0.2 A/ns and the es1 values derived from both
sets of measurements were consistent.
Figure 3.17. Load voltage waveform for 3 A.
At greater than 2.5 A however, the start of the inductive spike became less well-
defined (Figure 3.17). This meant the switching of current flow from the IC to the point-
of-load capacitor started to be less sharp and indicates that the equivalent parasitic
inductance (estimated to be about 3 nH) between the source of TN333 and the top of L5
was pulling the source of TN333 sufficiently below ground to turn on TN333, draw
current through the substrate diode connection or both.
The decaying ringing that appears after the inductive spike is due to parasitics
associated with the measuring probe. This ringing gets noticeably worse if a longer cable
or a lower quality connector is used. It gets intolerably bad if the 50 0Z termination at the
oscilloscope is removed.
Finally, it was observed that reducing VDD resulted in longer switching times and
hence lower di/dt' s.
3.3 Single Stage Hybrid Filter Experiment
The I-load circuit of the previous section was used to test a hybrid filter comprising
a single stage passive filter and the complimentary SAF. The experimental setup is shown
in Figure 3.18. The simplified circuit topology, along with design values, is given in
Figure 3.19. The values for the passive filter in this experiment were chosen to match
those related to the microprocessor power delivery model as listed in Table 1.3. The
inductance in the SAF path was laid out to be twice that in the passive filter. The SAF
was designed using the non-EAVP design equations (2.5), (2.26), (2.28) and (2.29). The
design values are summarized in Table 3.4. It should be noted that once again the SAF
design using the EAVP equations yield approximately the same values.
At the time these experiments were performed, the smaller I-load section had been
disabled. Therefore as an added precaution against breakdown and bondwire fusing, for
this experiment, the I-load was set to a switching time of about 20 ns by adjusting VDD
(VDD = 2.4 V) and current was limited to a maximum of 1 A.
The 0.2 p F point-of-load capacitor was implemented by a parallel combination of
two radial 0. 1 pu F capacitors. Even with the leads of these capacitors cut to less than 3
mm the equivalent es1 of the soldered combination was about 3 nH, which dominates
over the esr for the time window of concern. Hence the point-of-load capacitor esr could
be ignored. Furthermore, this large value es1 was beneficial in retaining the inductive
spike at lower di/dt' s thereby allowing for easy measurement of the load di/dt. In real
application, however, the leaded capacitors would be replaced by low esl, surface mount
net o r
Figure 3.18. I-load circuit together with SAF and single stage passive filter.
The SAF switch was driven from the same input that went to trigger the I-load.
However, this signal was first inverted using an HCT 7414 inverter and sent to an
IXDD408 gate driver connected to the STS9NF30L switch in the SAF. (Use of the
complementary gate driver is also an option but parts were not available at the time.) The
25 ns relative delay incurred by the signal in going through the extra circuitry was
compensated by adding an RC delay on the input of the I-load circuit using 1 K 0Z and 67
pF in a lowpass configuration i.e. the input signal entered through the resistor and the
output, taken across the capacitor, went to trigger the I-load.
Note the 2200 pu F electrolytic capacitor was not used as shown in Figure 3.18. It
was removed and the leads were cut short to minimize es1 before it was re-soldered. The
es1 and esr of the 2200 pu F capacitor- about 4 nH and 60 m Q were lumped into L
and R, respectively. These values were obtained from measurement with the HP4194
2 O 40 nH
VAF RL L i (t)~ Le
80 mQZ 20 nH 3 nH
2200 pF ic(t) i
Figure 3.19. Simplified circuit topology for SAF and single stage passive filter test.
The SAF was never disconnected during testing as a safeguard against accidentally
destroying the circuit in the process of unsoldering and soldering. In order to show the
improvement in performance data was taken with the SAF precharge voltage, VAF, Set to
zero. The response measured under this condition differs only slightly from the passive
filter response by itself and therefore it serves as a good reference by which to judge
improvement. The value of VAF WaS adjusted to obtain good regulation and the
performance parameters noted. The results obtained for tests at 0.5 A and 1 A are shown
in Figure 3.20 and Figure 3.21 respectively. The key parameters are shown in Table 3.4.
Fortunately, components were readily available such that the calculated and actual
designs values were equal within tolerance. Ignoring the first inductive spike caused by
point-of load capacitor esl, it was possible to regulate the transient response to within 100
mV, the desired specification. For 0.5 A, Alax~, = 45 mV and for 1 A it was 60 mV.
However, the values of VAF measured in the experiment were slightly higher than those
calculated. These higher VAF ValUeS in turn caused larger losses than calculated in the
experiment- 44 nJ instead of 41 nJ at 0.5 A and 283 nJ instead of 162 nJ. The losses were
obtained by first measuring CAF, then, the initial and Einal steady state values of vAF t)
and substituting the measured values into equation (2.30).
Although the increase in loss seems high- more than 50% in the worse case- the
regulation is significantly better, 60 mV instead of 100 mV. Also it may be partially the
result of the parameter measurements being somewhat in error. For example the LAF
inductance measurements did not include the exact package inductance of the FET switch
but only an estimate. Also the es1 of the 2200 pu F capacitor may have been measured with
the leads close together and may have effectively been increased when the leads were
bent further apart in soldering the component.
Table 3.4. SAF and single stage passive, hybrid filter design and performance.
-AV/AI L C LA C, RA
0.102 20 nH 0.2 p F 40 nH 0.1 p F 202
tr R, R Le SAF-load delay Aipkl
20 ns 80 mQ ~Z10 m Q 3 nH +/-5 ns 2.2 V
AI lAlmax C al c. VAF Exp. VAF, Gl. Etoss Exp. EloSS
0.5 A 45 mV 0.96 V 1.0 V 41 nJ 44 nJ
1.0 A 60 mV 2.2 V 2.5 V 162 nJ 283 nJ
The 20 MHz ringing that can be seen on the vAF (t) waveforms in Figure 3.20(b)
and Figure 3.21(b) is caused by the measurement probe which had clip-leads and 1 M D
Figure 3.20. SAF and single stage passive, hybrid filter tested using I-load at 0.5 A with
(a) VAF = OV and (b) VAF = 1.2 V.
Figure 3.21. SAF and single stage passive filter tested using I-load set at 1 A with (a)
VAF = 0 V and (b) VAF = 2.3 V.
Figure 3.22. Effect of delay error in hybrid filter response.
In order to demonstrate the importance of proper timing in switching in the SAF,
the relative delay was adjusted such that the SAF was switched on 20 ns in advance of
the current step load. This resulted in a 40 mV overshoot spike which was immediately
followed by the 140 mV undershoot spike caused by the es1 of the point-of-load capacitor
and then increased ringing in the transient for a few hundred nanoseconds thereafter.
Note that switching in the SAF before the load transient edge did little to reduce the
magnitude of the inductive first spike- it merely shifted its relative position up by 40 mV.
Finally Figure 3.23 has been included to show that the switching time of the I-load
in these experiments was 18 ns and hence the maximum di/dt was about 50 A/ pus for a
step of 1 A.
Figure 3.23. Spike induced by es1 of point-of-load capacitor.
3.4 Operation of the SAF with Multi-stage Passive Filters
VAC T'LAF RAF
AF 40 nH 20
-= 1 V0
L, R1 Lo Ro
200 nH 80 ma 2 n 20 mR
~0.3 nH Leo
a R 1 3 nH
2200 pF ~8 ma, I oa
C, 0.2 CIF
3 0 1 FT
Figure 3.24. Circuit used to test SAF with multistage passive filter.
By extending the 2.2 mF electrolytic capacitor out an appropriate length of semi-
rigid, twisted wire and soldering 30 pu F in its place, the circuit of Figure 3.24 was
implemented and used to test the SAF of the previous section with a two stage passive
filter based on the scaled values of Table 1.3. Once it is shown that the SAF (designed for
an equivalent single stage) operates independently of the adj oining stage, it is a
straightforward inference that lower stages have even less impact. Two stages, therefore,
are sufficient to investigate SAF operation with multi-stage passive filters.
Note that designing the experimental two-stage circuit to exact specifications of a
perfectly scaled model (i.e. any given column of Table 1.3) was not practical since it
would be too time-consuming to design for exact capacitor esl. However the two-stage
circuit was still developed using the design methodology in Chapter 2, with the
impedance-scaled parameters of Table 1.3 as a guide, assuming SAF inj section at the
* Assume L, = 20 nH, R, = 20 mZ, L, = 200 nH andR, = 80 mQZ are given. This is
a justifiable assumption since, in full-scale application, these values are mainly set
by the choice of socket and location of the BVR respectively. Little can be done to
arbitrarily change these values. The 20 nH is consistent with (4 nH + 14 nH) of
Table 1.3. The value, 200 nH is larger than the corresponding (10 nH + 70 nH) in
Table 1.3 because it is assumed that fewer motherboard capacitors would be used
in order to make room for the SAF.
* At the output node vo, the DC path resistance, R = 20 + 80 = 100 mQ Designing
R = REn = Ra = R, + Rc, a Rc, = 100 mQZ 20 mQZ = 80 mnZ, REn = 100 mQZ;
L, + L, 20 nH
and C, = = 2 puF .
RAn (100 m2)2
* At the output node vl, the DC path resistance to the source (the 2.2 mF capacitor),
R = 80 mQ Designing for EAVP: R = Rc, = RL1 = R, = 80 mQZ;
L, 200 nH
and C, =--= 3 1 pF .
R (80 mn):
* Based on Table 1.3, C, is limited to 0.2 puF (the impedance-scaled value for C~ )
roughly. Furthermore, practical implementation however, esr's and esl's cannot be
controlled. In the experiment, significant es1 in the point-of-load (output) capacitor
was present, Len = 3 nH; REn was less than 15 m 0Z; and Rc, was about 8 m Q .
* The dominant peak in the impedance of this imperfect EAVP passive filter is
caused mainly by the small value of Co. Therefore, inj ecting the SAF at vo, the key
parameters in the equivalent single stage model of the passive filter were found:
L La = 20 nH and C Co = 0.2 uF .
* Hence, the SAF parameters were determined, given that LAF = 40 nH (a value
typical in PCB level
interconnects): CAF = LC/LAF =(20 nH)(0.2 p1F)/(40 nH)= 0.1 p1F,
RAF = (L/R + RC)/CAF = (20 nH/0.1 0Z + 0.1 0Z 0.2 prF) (0.1 pIF) a 2 02; and
VAF AF L/RRC) +Vo +ABV
S(0.5 A/0.1 puF) (20 nH/0.1 n) + 0.1 V -0.1 V = 1 V; for Mr = 0.5 A
S(1 A/0. 1 puF)(20 nH/0. 1 2) + 0.2 V 0. 1 V = 2. 1 V ; for MI = 1 A
* Note that the I-load circuit of Figure 3.10 was used not only to obtain a step current
but also to set the bias voltage, Vo_ = M R4.
Table 3.5. Comparison of the passive filter in the experiment with the ideal EAVP filter.
R, C, c La [ nH ] Ro Co
Ideal 200 nH 80 m Q 31 puF 80 m Q 19.7 20 m Q 2 puF 100 m Q
Expt. 200 nH 80 m Q 30 p F 8 m Q 20 20 m Q 0.2 pF <15 m Q
Table 3.5 allows for a comparison of the passive filter in the experiment with the
ideal EAVP passive filter derived above using the method described in Appendix A. The
lower stage of the passive filter is almost the same as the ideal EAVP design except that
the esr, E4,, is much lower than the desired 80 m a This of course will lead to a bit of
ripple at approximately the 65 KHz resonant frequency (or alternatively a 15 pus period)
in the transient response. This is indeed observed in Figure 3.25. The oscillation causes
an additional undershoot of 30%. However, the oscillation dies out in one cycle or 15 p s.
Figure 3.25. Output voltage, volt), on a long time scale
Figure 3.26. Waveforms of volt) showing the SAF working with multi-stage passive filter
for (a) VAF = OV and (b) VAF = 1 V at 0.5 A step load.
Figure 3.26. Continued
Riding on this low frequency decay is another decaying oscillation, seen in Figure
3.26(a), caused by the point-of-load capacitor, Co, which is much lower than desired
0.2 puF instead of 2 puF. This oscillation is made worse by the fact that the esrE40 is also
much lower than ideal- less than 15 maZ instead of 100 m Q .
However, Figure 3.26(b) shows that the SAF designed for the equivalent single
stage passive filter operates to regulate the output voltage to within 40 mV for the first
couple of microseconds after the transient edge (ignoring the very first inductive spike
caused by the 3 nH es1 of the leaded point-of-load capacitors). After the first couple
microseconds, the response follows almost exactly the trace of Figure 3.26(a). It droops
just a little bit less because the SAF effectively adds CAF in parallel with the lower
frequency filter capacitors. The results show that the SAF operation is unaffected by
lower frequency filter stages or by adj oining stages with interconnect inductance much
greater than the es1 of filter capacitor of that stage. Conversely, the SAF does not greatly
affect the performance of the adj oining filter stages.
Similar results were also obtained at the 1 A step load setting (Figure 3.27). With
VAF = 2.3 V (as in the single stage experiment), the SAF regulated the output voltage to
within 80 mV before falling into the lower frequency filter response. These Eindings
indicate that multiple SAF's may be used with a multistage passive fi1ter- a future topic
that is left for Chapter 4.
Figure 3.27. SAF operation with the multistage passive fi1ter at 1 A step load, and with
VAF = 2.3 V.
3.5 Feedback Control Feasibility
Feedback control may be used to achieve continuous regulation when the load
varies randomly provided the SAF is designed for the worst case step load that may occur
in the system. The envisioned configuration is given schematically in Figure 3.28. The
topology is similar to a linear active fi1ter except for the extra switches that control the
power supply feed to the circuit.
Ao = 60 dB
f = 1GHz
LAF 0.6 nH
0.2 mQZ 0.4 nH 0.8 mQ
Rise-time 5 ns
Figure 3.28. Hybrid filter with feedback control on the SAF.
The network comprising RF and CF may be a more sophisticated compensation
circuit but in the simplest case, it extracts the desired reference voltage which in turn is
maintained by the opamp in a negative feedback loop. The associated RFCF time
constant is chosen to be comparable with the risetime of the worst case step load. Bias
circuitry between opamp output and FET gates are not shown. In simulation, voltage
sources were used as level shifters to set the bias voltages such that both the SAF
switches are just off while the pre-charge switches are biased on at DC. For a rise in load
current, the VAFP supply is disconnected leaving the upper CAF, pre-charged to VAFP, to
provide the necessary energy through Qm1 in a controlled fashion (that is approximately
linear) by actively varying the channel-resistance, while VAnh pre-charges the lower CAF
to be ready for a fall in load current. In the event of a step load, the opamp saturates to the
appropriate rail and the circuit effectively functions as a switched active filter once again.
The passive filter design is loosely based on the 2004 microprocessor model. The
package capacitor, Co, is 10 pu F instead of 23 pu F as it is assumed some additional space
would be required for the pre-charge and control sections. The bulk capacitor has been
removed and the equivalent resistance in the socket Ro, esr Rel of the capacitor in the
socket cavity, and equivalent resistance in BVR model R1, have been tweaked to ensure 1
maZ total resistance in the DC and high frequency paths. The es1 of the socket cavity
capacitor Let is 20 pH, in anticipation of better component packaging in the future.
Output Voltage, v(t) vs time
|I|= 50 A |I|=o 100, Anl= u
0.0 1u 2u
Figure 3.29. Output voltage of hybrid filter for various step loads.
Simulation waveforms show for the use of an SAF at the output node of this two-
stage passive filter (the first stage of the passive filter is an EAVP design except for esl,
Let, which is larger than desired) the ripple can be maintained under 150 mV for a range
of step load magnitudes, from 25-100 A, and di/dt' s, from 5-20 A/ns (Figure 3.29).
Without the SAF, the voltage ripple exceeds 200 mV.
3.6 Applying the SAF to LAF Topologies
Figure 3.30 shows a hybrid filter comprising a single-stage passive filter and a
linear active filter topology. Normally, when this circuit is drawn, the capacitors and
inductors on the active filter supply are not shown- the supply is assumed to be ideal.
However, in reality, there is usually need for some filter capacitance near the circuit as
there is physically some inductance in between the power source and the circuit. These
components are shown explicitly in Figure 3.30.
i...TAF iAF 1)J v(t)
Figure 3.30. Linear active filter (left of iLOAD) operating with single-stage passive
For a short time immediately after a sudden load transient, the parasitic inductances
on the AF supply act like open circuits, the opamp saturates since the feedback loop is
generally too slow to respond and the active half of the AF topology in Figure 3.30
becomes topologically the same as an SAF (Figure 3.28).
If the LAF design parameters are chosen to match those obtained using the SAF
design equations, the output voltage would naturally be regulated over the time it takes
the feedback control loop to respond or "catch up". Applying the SAF design values to an
LAF may reduce the strain placed on the LAF control circuit design and operation.
Conversely, feedback control methods developed for LAF topologies may be
adapted to SAF and hybrid filter control.
Basing experiments on a microprocessor power delivery architecture, and
downscaling to inductances on the order of 10 nH, currents on the order of 1 A and
di/dt' s on the order of 0.05 A/ns; the hybrid filter theory and design methodology was
validated. Although the theoretically expected improvement was not achieved in every
case, up to a factor of five improvement in regulation performance was obtained in both
single stage and multistage passive filters. Deviations from ideal were consistent with the
underlying theory as they were explained by component tolerance and timing errors.
Remaining practical implementation issues have been investigated to some degree
3.7 Pre-charging Mechanism
In order to take advantage of the energy savings in the SAF, one must find a way to
efficiently pre-charge C,,F. One method is illustrated in Figure 3.31. By switching
between charging and free-wheeling positions, C.4F (also called CPS in the analysis) may
be charged up from arbitrary initial voltage, VPS to an arbitrary final voltage, VysAF
(which is also called V4F in the larger hybrid filter circuit) that is less than
2( -Pr ). The rest state is shown in Figure 3.31I(a). The source voltage, V,, across
a very large Cex is roughly constant. Zero current is in inductor LPS. When switched to
the circuit of Figure 3.31l(b), the current iPS, builds up inLPS While building up vPS across
CP. Solving for vPS andp i PS2,
"P2 IT PS, ~0 )+VS 1 I S ) COs0i, t (3.4)
IP KT PS, Sin ), t (3.5)
2 =LPS PSr
are obtained in terms of the known variables in the system. Energy in LPS is a function of
the current through it, iPS2 Whereas energy in CPS is a function of the voltage across it,