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Linearization Through Carrier Amplitude Modulation (lcam) Control of the Boost Converter

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LINEARIZATION THROUGH CARRIER AMPLITUDE MODULATION (LCAM) CONTROL OF THE BOOST CONVERTER By ALEX GEOFFREY PHIPPS A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE UNIVERSITY OF FLORIDA 2006

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Copyright 2006 by Alex Geoffrey Phipps

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iii TABLE OF CONTENTS page LIST OF TABLES...............................................................................................................v LIST OF FIGURES...........................................................................................................vi ABSTRACT.....................................................................................................................vi ii CHAPTER 1 INTRODUCTION........................................................................................................1 2 CONTROL METHODS...............................................................................................4 Standard Modulation....................................................................................................4 Non-Standard Modulation Control Methods................................................................5 One-Cycle Control.................................................................................................5 Feed Forward Control............................................................................................7 LCAM Control..............................................................................................................8 3 HYSTERETIC MODULATOR.................................................................................12 Ideal Hysteretic Modulator.........................................................................................12 Basic Operation...................................................................................................12 Operating Frequency...........................................................................................14 Current Sources............................................................................................14 Modulation Capacitor...................................................................................16 Physical Realization of the Hysteretic Modulator......................................................17 4 DESIGN ORIENTED MODELING..........................................................................19 Realizing the Modul ation Frequency..........................................................................19 Selection of CMOD................................................................................................20 Design of Idown.....................................................................................................21 Design of Iup........................................................................................................21 Switching Logic and Level Shifting...........................................................................22 Design of the Level Shifter..................................................................................24 Selection of the Inverter......................................................................................25 Comparators and SR Latch.........................................................................................25 Comparator and Latch Speed..............................................................................25

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iv Selection of the Offset Voltage...........................................................................27 Design Summary........................................................................................................28 5 SIMULATION AND VERIFICATION.....................................................................30 Verification Techniques..............................................................................................30 Boost Transfer Function with LCAM.................................................................30 Simulation Model................................................................................................32 Experimental Verification...................................................................................32 Results........................................................................................................................ .34 LIST OF REFERENCES...................................................................................................39 BIOGRAPHICAL SKETCH.............................................................................................40

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v LIST OF TABLES Table page 4-1 Design summary for the hysteretic m odulator needed to implement LCAM control on the boost converter..................................................................................29 5-1 Boost converter loss term values..............................................................................31 5-2 Hysteretic modulator simula tion parameters and components.................................32 5-3 Boost converter values used in simulation...............................................................32 5-4 Bias and offset voltages............................................................................................33 5-5 Bill of materials........................................................................................................38

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vi LIST OF FIGURES Figure page 1-1 Standard PWM boost converter topology..................................................................1 1-2 Boost transfer function /outinVV vs. D andD ..........................................................2 2-1 Waveforms used to generate the PWM signal for the standard modulation configuration..............................................................................................................4 2-2 One-Cycle controlled, co nstant-frequency switch.....................................................6 2-3 Waveforms for one-cycle contro lled, constant-frequency switch..............................7 2-4 Feed-Forward PWM controller for boost converter ..................................................7 2-5 Operational waveforms for Feed-Forward PWM controller......................................8 2-6 PWM waveforms with LCAM system.....................................................................10 2-7 Block diagram of the complete system used to realize LCAM control for the boost converter.........................................................................................................11 3-1 Ideal hysteretic modulator........................................................................................12 3-2 The voltage across M ODC ...........................................................................................13 3-3 Triangle shapes that can be ach ieved with a hysteretic modulator..........................14 3-4 Physical realization of the hysteretic modulator using non-ideal components........18 4-1 Schematic of the non-ideal hysteretic modulator.....................................................19 4-2 Current source topology...........................................................................................22 4-3 Level shifting implementation.................................................................................23 4-4 VCMOD for the ideal case without delays modulates between the two hysteretic thresholds.................................................................................................................26 4-5 Overshoot of the lower hysteretic limit requires the use of offsetV............................27

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vii 5-1 Boost converter with losses......................................................................................30 5-2 Saber schematic used for circuit simulations...........................................................33 5-3 Boost converter and LCAM syst em used to measured data.....................................34 5-4 Measured waveforms...............................................................................................35 5-5 outVvs. cmdVcurve with calculated, simu lated and measured data............................36 5-6 A family of outVvs. cmdVcurves for several values of out I ........................................36 5-7 A family of outVvs. cmdVcurves for several values of inV.........................................37

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viii Abstract of Thesis Presen ted to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Master of Science LINEARIZATION THROUGH CARRIER AMPLITUDE MODULATION (LCAM) CONTROL OF THE BOOST CONVERTER By Alex Geoffrey Phipps May 2006 Chair: Khai Ngo Major Department: Electrical and Computer Engineering In order to design a robust DC-DC converter it is essential that the system be controllable. The pulse width modulated (P WM) DC-DC boost convert er presents a nonlinear system with respect to the PWM duty cy cle, and standard lin ear control techniques cannot be applied. Typical control methods generate th e PWM waveform by comparing a fixed amplitude carrier to a variable magnitude DC reference. This thesis proposes a control method of L inearization through C arrier A mplitude M odulation (LCAM). In LCAM control, the PWM signal is generated by compar ing a variable amplitude carrier signal to a fixed DC reference. When this PWM signa l is applied to the boos t converter, it is shown that the output voltage of the converter is directly proportional to the amplitude of the carrier. The carrier signal is generated by a hysteretic modulator. The amplitude of the carrier from the hysteretic modulator is equal to a reference input signal, and the

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ix output voltage of the boost converter is therefor e directly proportional to the reference. Using the hysteretic modulator, the output will linearly track the reference signal. Operation and design of the hysteretic m odulator are examined for LCAM control of the boost converter, and a design metric fo r the hysteretic modulator is included for constant frequency operation. Sources of delays and hysteretic limit overshoot are examined and their effects on opera ting frequency are included. Models of the boost conver ter with LCAM control are given which predict the linear behavior. For an ideal boost converter the output voltage is independent of the output current and input voltage In a second order system with converter parasitics included, these other signals can superimpose sm all operating-point dependant loss terms. If losses can be minimized, however, the lin ear terms will dominate. Simulations and measured data are compared w ith the models in order to verify linear operation of the system. Input voltage and output current are varied to veri fy the second order effects.

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1 CHAPTER 1 INTRODUCTION For switching DC-DC converters, controll ability is essential for robust circuit design. In a Pulse Width Modulated (PWM) c onverter topology, the width of a constantfrequency pulse is modulated in order to contro l one or more of the c onverter’s variables. For a boost converter, th e transfer function,/outinVV, as a function of the PWM duty ratio, D, is nonlinear. Standard lin ear control processes, incl uding voltage feedback and current-mode control are more effective on linear systems. The standard Pulse Width Modulated (PWM) DC-DC boost converter can be seen in Figure 1-1. RL L1 CL Vin D1 M1 + VoutPWM input Duty cycle = D GD1 Figure 1-1: Standard PW M boost converter topology. A switching network comprising M1 and D1 is used to boost the input voltage,inV, up to the desired output voltage,outV. The output voltage that th e converter delivers to the load, RL, is controlled by a pulse-train signal sent to the gate of M1. Control of the output voltage is achieved by modulating the duty cycle,D, of the pulse-train. Using voltsecond-balance and amp-second-balance [1], it can be shown that th e transfer function for steady state operation of the boost converter is

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2 D D V Vin out 1 1 1 (1.1) where the compliment duty cycle1 DD If the duty cycle is the control variable, th e transfer function of (1.1) is non-linear with respect to bothDandD This non-linearity can be fu rther seen in Figure 1-2, which plots the relationships established in (1.1). Boost Transfer Function (Vout/Vin) vs. D and D`0 20 40 60 80 100 0.000.200.400.600.801.00D, D`TF TF vs. D TF vs. D` Figure 1-2: Boost transfer function /outinVV vs. D and D These functions are highly nonlinear. Classical linear control t echniques cannot be applied to non-linear systems, and stability of such systems is difficult to achie ve. The goal of this work is to present a method to linearize the dc relationship between the transfer function of the boost and its control variable. Chapter 2 examines the st andard control method us ed to generate the PWM signal for linear switching converters and shows why it will not work for the boost topology. Other complex methods used to control non-linear converters are also examined. Finally, a new control method, L inearization through C arrier A mplitude M odulation (LCAM) is presented for the boos t converter. Chapter 3 explores the

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3 operation of a hysteretic modul ator, which is the fundament al building block for the LCAM control system. Chapter 4 pr esents a detailed design methodology for implementation of the hysteretic modulato r. Chapter 5 verifies LCAM control by comparing theory, simulations and measured data.

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4 CHAPTER 2 CONTROL METHODS Standard Modulation A standard modulation scheme is often used to generate the PWM signal for switching converters. This method involves comparing a fixed amplitude carrier with a slowly varying, or dc, modulating signal. Making adjustments to the modulating signal controls the duty cycle of the PWM signal. An example of standard modulation with a triangular carrier signal ca n be seen in Figure 2-1. t t Ts DTsVpeakVcmd VcarrierVcmd 0 PWM Signal + Figure 2-1: Waveforms used to generate the PWM signal for the standard modulation configuration. Using the similar triangles formed in Figure 2-1 it can be seen that cmds peaksVDT D VT (2.1)

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5 Since peakV is fixed, the duty cycle, D is a linear function of the command voltage, cmdV However, from (1.1), the transfer function of the boost is non-linear with respect to the duty cycle. Therefore, the boost transfer function is non-line ar with respect tocmdV and linear feedback schemes cannot be applied control the output. Non-Standard Modulation Control Methods For any PWM converter topology, the goal of making a circuit lin ear is to force it to behave with the following characteristic: outcmdVkV (2.2) Here k is a constant and cmdV is a controllable command signal. The command signal varies slowly compared to the converter switc hing frequency and can be considered to be quasi-DC in the steady-state. There are two major benefits to achieving the behavior in (2.2). First, the output of the converter can be linearly controlled using only the command voltage. Second, in the ideal case, th e output signal is inde pendent of all other input parameters, includinginV This means that changes to the input of the converter will not greatly impact steadystate performance. Two common methods to achieve the lin ear behavior of (2.2) are One-Cycle Control [2], and Feed-Forward PWM Control [3 ]. These are non-linear methods used to achieve large-signal modulation control of switching converters. For each of these methods, however, certain drawbacks can ar ise due to complexity of the circuits. One-Cycle Control The schematic for a One-Cycle controlled, constant-frequency switch can be seen in Figure 2-2. In the One-Cycle scheme, opera tion of the circuit is initiated by the clock

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6 signal which closes the switch. With the switch closed, ()() ytxt and intV ramps up until it reaches cmdV in the following manner: 0()()onT cmd x tdtVt (2.3) Waveforms from this circuit can be seen in Figure 2-3. The average value of the switch output, () yt is found to be 0()()onTytxtdt (2.4) and therefore, ()()cmdytVt (2.5) For the boost converter ()()outytVt Substituting this into (2.5) yields the desired linear relationship between the co mmand voltage and the output. outcmdVV (2.6) + Controller Clock + VcmdVintINT x(t) y(t) Figure 2-2: One-Cycle controll ed, constant-frequency switch.

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7 Clock t y(t) vintTs x(t) vcmd Figure 2-3: Waveforms fo r one-cycle controlled, c onstant-frequency switch. The integrators needed for this circuit must have a reset, and the integration function can lead to cumbersome control equa tions. Complicated circuits may also be required to minimize errors due to delays in the reset process. Feed Forward Control The Feed-Forward PWM (FF-PWM) contro ller used for a boost converter with leading-edge modulation can be seen in Figur e 2-4. As in One-Cycle, the circuit is initiated by the clock, which resets the integrator. The command voltage, cmdV is integrated to create a ramp, which is compar ed to the converter input voltage. The PWM output created by this system can be seen in Figure 2-5. + INTINOUT R CLOCK Vin/k VcmdVPWM Figure 2-4: Feed-Forward PWM controller for boost converter with leading-edge modulation.

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8 Figure 2-5: Operational waveforms fo r Feed-Forward PWM controller. It can be shown that for boost converter s with PWM signals generated in this manner, the output voltage is pr oportional to the command voltage outcmdVkV (2.7) Like One-Cycle control, integrators w ith reset are central to FF-PWM control schemes [3]. The integrators are used to re alize complex equations necessary to achieve linear behavior. Several other elements are needed to achieve FF-PWM including, a comparator, a mono-stable pulse circuit and a clock signal. Time constants of the integrators and the clock must be closely matched, or a dependence on the input voltage may arise. LCAM Control The general linearization concept given in (2.2) can be specifically applied to the boost converter using the boost tran sfer function given in (1.1). Substituting the value of outV from (2.2) into (1.1), it can be shown that 1cmd inkV VD (2.8) Solving for D in cmdV D kV (2.9) VPWM Vcmd Vin/k

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9 This means that if the output voltage of the boost is to behave linearly as in (2.2), the switching MOSFET, M1, in Figure 1-1 must be driven with a PWM signal having a compliment duty cycle that obeys the relationship in (2.9). To achieve a PWM signal where D satisfies (2.9), the L inearization through C arrier A mplitude M odulation (LCAM) control system is used. The LCAM system is similar to the conventional PW M generator used for standard linear control. Again, a triangular carrier is compared to the modulating signal in order to generate the PWM signal. In this new scheme, however, the amp litude of the carrier is modulated also. The modulating signal, which must not be confus ed with the amplitude modulated carrier, should not change much within one carrier peri od. In order to real ize (2.9), the LCAM system uses configuration in Figure 2-6(a). The peak of the car rier signal is equal tocmdkV and inV acts as the modulating signal. Us ing the similar triangles seen in Figure 2-6(b), it can be seen that ins refsVDT D kVT (2.10) Therefore, the PWM signal generated by the LCAM system is that of (2.10). This signal satisfies the requirements of (2.9) and will therefore force the desired linear behavior for the boost converter spec ified in (2.2). It is important to realize that the goa ls and results of One-Cycle, FF-PWM and LCAM are the same. Namely, all of these me thods force switching converters to behave linearly as in (2.2). The differences between these concepts arise from their respective derivations and hardware implementations. LCAM does not propose a new concept of linearization, but rather a different method by which to implement it.

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10 Figure 2-6: PWM waveforms with LCAM syst em. (a) Generation of the PWM signals for the linearized boost conve rter using the LCAM system. (b) Comparator inputs and output for a amplitude modulated carrier. The constant k is used as a scaling factor forcmdV If1 k outcmdVV (2.11) For boost converters, the desired outV may be much larger than any available command voltage. By using the factork, a PWM signal with the desire d duty cycle can still be produced with a lower command voltage. It wi ll be assumed for the remainder of this paper that cmdV is a nominal voltage that can be easily obtained. For simplicity the scaling factork is assumed to be equal to one. A block diagram showing the complete LCAM system applied to the boost converter can be seen in Figure 2-7. The PWM signal is generated by comparing inV to the amplitude modulated triangular carrier. This triangular carrier is generated by a hysteretic modulator whose input is the control reference cmdV The upper hysteretic limit of the modulator determines the amplitude of the triangle wave and is set to cmdV The details of the modulator’s operation are covered thoroughly in Chapter 3. VcarrierVin PWM Signal + (a) t (b) Ts D’TskVcmdVin0

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11 Figure 2-7: Block diagram of the complete sy stem used to realize LCAM control for the boost converter. Boost Converter Hysteretic Modulator + Vin Vref Vout To PWM Switch Vcarrier

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12 CHAPTER 3 HYSTERETIC MODULATOR This chapter examines the operation of a hysteretic modulator, both in its ideal form and in a physical circuit realization. Ideal Hysteretic Modulator Basic Operation The hysteretic modulator is used to creat e a triangular volta ge waveform whose amplitude can be directly modulated with the quasi-DC command voltage,cmdV An ideal diagram of the hysteretic modulator is shown in Figure 3-1. CMOD + Q QSET CLRS R + Vcmd Switch Control IdownIup Vee+ VCMODCOMP1COMP2 VccICMOD Figure 3-1: Ideal hys teretic modulator.

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13 Operation of the modulator begins with the capacitor M ODC discharged and the current source up I switched off, so it does not conduct. The current source down I draws current from M ODC which lowers the voltage, CMODV slightly below zero. As this occurs, comparator 2COMP outputs a logic low and the SR latch is reset. The switch control logic causes up I to switch on. For proper circ uit operation it is assumed that updownII With this assumption, M ODC is now charged up with a constant current, CMODupdowniII The voltage CMODV ramps up at a constant rate as seen in Figure 3-2. Vcmd0 VCMOD t V+VFigure 3-2: The voltage across M ODC. CMODV ramps up and down between the two hysteretic limits V andV V is set to refV and V is grounded in this case. When the magnitude of CMODV grows slightly larger than cmdV, comparator 1COMP outputs a logic low and the SR latch is set. The switch control logic causes up I to turn off, and M ODC is discharged by the current sourcedown I The constant-current discharge of the capacitor causes CMODV to ramp back down. As CMODV again falls slightly below zero, the latch is reset and up I is turned back on. The two boundary voltages, cmdV and 0V, form the upper and lower hysteretic limits of the modulator. This process of charging and discharging M ODC continues, and a triangular waveform seen in Figure 3-2 is produced.

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14 Operating Frequency The operating frequency of the hysteretic modulator is determined by the speed at which the current sources charge an d discharge the modulation capacitor M ODC. With the desired operating frequency known, the rela tionships between the current sources and modulation capacitor can be derived to achie ve the leading edge, trailing edge and symmetrically modulated triangul ar waveforms in Figure 3-3. tfall trisetfall trise tfall triseLeading Edge (LE) Trailing Edge (TE) Symmetrical Figure 3-3: Triangle shapes that can be achieved w ith a hysteretic modulator. Current Sources From basic circuit theory, the relationsh ip between the current and voltage of a capacitor is cc cdvv iCC dtt (3.1) Using this approximation and the signals from Figure 3-1, (3.1) can be rearranged to

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15 CMODCMOD M ODvi tC (3.2) For a given modulator design, M ODC is fixed and CMODcmdvV which is the same for both charging and discharging events. This is due to the fact that the hysteretic thresholds are relatively fixed within each switching period as long as the carrier amplitude varies slowly compared to the switching period. Substituting CMODcmdvV into (3.2), it is seen that chargingcmdMODCMODriseVCIt (3.3) and discharging cmdMODCMODfallVCIt (3.4) for any of the waveforms in Figure 3-. Next, equating (3.3) and (3.4) it is shown that chargingdischarging CMODCMODII (3.5) where fall riset t. As M ODC is being discharged, up I is off, and therefore from Figure 3-1 discharging downCMODII (3.6) Similarly, as M ODC is charged up charging CMODupdown I II (3.7) Combining (3.6) and (3.7) chargingdischargingupCMODCMODIII (3.8) Finally, substituting (3.5) into (3.8) discharging(1)upCMODII (3.9)

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16 or (1)updown I I (3.10) The ratiodetermines which type of waveform from Figure 3-3 is produced. For a leading edge waveform, where f allrisett will be a small value. Conversely, for a trailing edgewill be large. In a symmetrical waveform, f allrisett and will be unity. Modulation Capacitor The value of the modulation capacitor, M ODC, needed to achieve a given frequency is derived from (3.1). Again assuming that CMODcmdvV CMOD MOD cmdit C V (3.11) When M ODC is discharging, (3.11) becomes down MOD cmd I t C V (3.12) For any of the waveforms in Figure 3-3, risefallTtt (3.13) which can be rearranged into 1 11falltT f (3.14) During the discharge of M ODC, falltt and (3.12) becomes 1down MOD CMDI C fV (3.15)

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17 While this derivation was done for a dischargi ng event, the same resu lt is achieved from a charging event. Any frequency waveform from Figure 3-3 can now be obtained by the proper choice of up I down I and M ODC. Physical Realization of the Hysteretic Modulator The previous model of the hysteretic modul ator provides the means to examine its operation under ideal conditions. Implementa tion of the circuit requires the use of nonideal parts and physical realiza tion of the hardware needed for logic control. Figure 3-4 shows the schematic of the modulator with nonideal components that is used to verify operation in Chapter 5. Operation of this circuit is similar to the ideal model. A symmetrical triangular waveform, with 1, is assumed to be used for the circuit of Figure 3-4. As before, M ODCbegins discharged, and up I is initially off. up I is realized with the trans-conductance amplifier consisting of Q1 and U1. CMODVis brought down as the current CMODdowniI is drawn from the capacitor, and when CMODVcrosses the lower hysteretic limit 2COMPresets the SR latch. The lower hysteretic limit is can be adjusted by the source offsetVto account for delays in the comparator and in the switching logic. The reset signal output from the SR latch is then sent to the switching logic that controlsup I This switching logic consists of an inverting gate-driver, and a level shifting zener diode. By controlling the voltage at the top of up I the current from this source can be switched on and off. Level shifting of the set and reset signals is necessary to ensure that the active components of up I remain in the correct operating modes.

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18 The reset signal from the SR latch is inverted and up I turns on similar to the ideal case. From (3.10), to achieve a symmetrical triangle wave, down upI I2 The capacitor voltage, CMODV, is charged up to th e upper hysteretic limit,cmdV, and COMP1 outputs a logic low to set the latch. The gate driver inverts the set signal from the SR latch causing up I to turn off and M ODC to discharge. As in the ideal case, modulation continues as M ODC is charged and discharged, and a symmetrical triangle is produced. The causes and effects of the various delays associated with non-ideal componen ts are covered in Chapter 4. CMOD + Q QSET CLRS R + Vcmd + VCMODCOMP1COMP2 Rup Vcc/2 Vcc Vee+ Rdown Vee/2 + Vcmd Vee Vcc+ Vee/2 Vcc GND INAINBOUTAOUTBICL7667 Vcc/2 + VcmdVcc/2 1k U2 U1 Q1 Q2 Rbias Vcc Voffset Vz+ Figure 3-4: Physical realization of the hys teretic modulator usi ng non-ideal components.

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19 CHAPTER 4 DESIGN ORIENTED MODELING This chapter provides a detailed explanat ion of the non-ideal hysteretic modulator seen in Figure 4-1. Guidelines for choos ing components and component values are also given. All derivations are made assu ming a symmetrical triangle waveform. CMOD + Q QSET CLRS R + Vcmd + VCMODCOMP1COMP2 Rup Vcc/2 Vcc Vee+ Rdown Vee/2 + Vcmd Vee Vcc+ Vee/2 Vcc GND INAINBOUTAOUTBICL7667 Vcc/2 + VcmdVcc/2 1k U2 U1 Q1 Q2 Rbias Vcc Voffset Vz+ Figure 4-1: Schematic of th e non-ideal hysteretic modulator. Realizing the Modulation Frequency Assuming the switching frequency is know n, the physical realization of the hysteretic modulator becomes an iterative process. First, the type of triangle waveform, leading-edge, trailing edge or symmetrical, must be chosen. For this circuit, a symmetrical waveform was used and the value of 1 Next, either the value of M ODCor down I must be selected. The other value is then calculated using (3.15). It is possible that this calculated value will exceed some design constraint and values for both

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20 must be redone. For instance, the value of down I calculated for a chosen capacitance value may be higher than component tolerances allow. In this case, lower capacitances values can be iterated until an acceptable down I is achieved. up I is always larger than down I and will most likely be unacceptable if down I is too large. The relationship between M ODC and down I was given in (3.15) a nd is repeated here for convenience. (1)down MOD cmdI C fV (4.1) cmdV is the control signal that modulates the am plitude of the carrier, and it is therefore assumed that cmdV will vary. If down I is assumed to be fixed, then for changes incmdV the capacitor M ODC must vary in order for frequency to remain the same. Variable capacitance is difficult to obtain in practice and is not a practi cal solution. On the other hand, if M ODC is assumed to be fixed, then for constant frequency operation down I must vary withcmdV Rearranging (4.1) shows a linear relationship between down I and cmdV 2CMODMODcmdifCV (4.2) A transconductance,mg found from (4.2) is defined as 2CMOD mMOD cmdi gfC V (4.3) Selection of CMOD The choice of M ODC must take several factors into account. In order to maintain a reliable modulation frequency, the capacita nce value must be stable over the entire voltage range of cmdV and all possible operating temperatures. Since the controller may be in close physical proximity to the boos t converter, there is the possibility of high temperatures generated by power de vices. For integrated designs, M ODC should be as

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21 small as possible, but must remain large e nough to overcome parasitic capacitances from the process. The active devices associated w ith the current sources can also cause stray capacitance in parallel with M ODC Small designs may require small components, which may put a limit on the capacitance. For non-in tegrated designs, mica capacitors make a good choice for temperature and voltage stability. Design of Idown With a chosen capacitance for M ODC the relationship between down I and cmdV in (4.3) can be realized using a transconductan ce current source. A schematic of the source down I can be seen in Figure 42(a). The current produced bydown I is a function of the voltage applied across the bias resistor, down R To set the transconductance of this source, the value of down R needed is 1down mR g (4.4) Combining (4.3) and (4.4), the resistance needed for the current source down I is 1 2down M ODR fC (4.5) Design of Iup The current source up I seen in Figure 4-2(b) is realized with the same circuit topology as down I There are two differences between these current sources. From (3.10), it can be shown that for a symmetrical triangle wave, where 1 that 2updown I I For a given value of cmdV the transconductance of up I must twice as large as that of down I to meet this specification. The bias resistor of up I is then given by 111 22(2)4up mMODMODR gfCfC (4.6)

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22 The other difference between the two current sources is that up I must be able to quickly switch on and off, while down I remains constant. The voltage across up R must therefore be switched quickly between cmdV in the on state, and zero in th e off. It should be noted that in the off state, the voltage across this resistor does not fall below zero. If the terminal s V in Figure 4-2(b) were switched to ground instead of 2ccV the biasing of the op-amp and BJT would change. When the cu rrent source switches back on, there would be a recovery time required to re-bias the circuit. During this recovery time there is no current flowing fromup I and the triangle wave experi ences overshoot and flat-spots. Rup Vcc/2 Vcc VeeVcmd + Vcc/2 2ICMOD Vcc/2 + -Current Source Iup Rdown Vcmd + Vee/2 Vcc Vee Vee/2 ICMOD + -Current Source IdownVs(a)(b) Figure 4-2: Current source t opology used to generate (a) Idown and (b) Iup in the hysteretic modulator. Switching Logic and Level Shifting Control circuitry is n eeded to realize the switching of the node s V in Figure 4-2(b), and also to make sure that the op-amp and BJ T remained biased in the active region. The sub-circuit seen in Figure 4-3 is used to achieve the switch signal that drives the current source up I The circuit consists of a zener diode, bias resistor and inverter.

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23 Vcc/2 + VrefVcc/2 Rbias Vcc Vz+ Vs TTL from SR Latch Level Shifted Signal t Vcc/2 0 Vcc/2 + VrefTTLhigh Figure 4-3: Level shifting implementa tion. Switching circuitry to drive Iup and the associated input and output waveforms. The input to the switching l ogic is a square wave output from the SR latch. This signal is a standard TTL signal and switche s between its power supply voltage and ground. The switching node of the current source, s V is directly controlled by the inverter, whose power and ground supply rails represent the on and off voltages of up I By biasing the supply rails in this manner, the inverter’s output will swing between the two desired levels and prevent the transistors in the current source from leaving the active region. The zener diode is n eeded to level shift the TTL latc h signal to a level that the inverter can use as an input. Figure 4-3 shows the result of the level shifting with the small delay caused by the inverter.

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24 Design of the Level Shifter Determining the correct amount of DC level shifting is necessary to ensure that the inverter can input the TTL logic levels from the SR latc h. Standard inverters do not respond properly when the input voltage is less than the value of their ground pin. Therefore, the zener voltage of the diode, zV should be such that it shifts the SR latch TTL signal by an amount equal to the valu e of the ground pin on the inverter. 2cc zV V (4.7) By doing this, a logic low from the latch will be at the voltage co rresponding to a logic low on the inverter. A bias resistor is required to provide current to the cat hode end of the zener diode. Using (4.7), when the input to the zener, inV is high the voltage across the resistor is given as 2cc RbaiscczininV VVVVV (4.8) When the input is low 2cc RbiascczV VVV (4.9) The resistance bias R must be chosen to provide ample bias current during a high input and still remain lower than the maximum cu rrent during a low input. This means 2cc in min biasV V I R (4.10) and max2cc biasV I R (4.11)

PAGE 34

25 Here min I is the minimum current required by the zener diode to function as a voltage level shifter, and max I is the largest curren t that the diode can safely conduct. Combining and rearranging (4.10) and (4.11) 2 2cc in cc bias maxminV V V R II (4.12) Selection of the Inverter The inverter must be capable of drivi ng the capacitive load of the current source up I without excessive delay. The amount of delay allowed depends on the modulating frequency of the circuit. The capacitive load of concern is a combination of the capacitances from the BJT emitter and the op-amp minus pin. To drive this capacitive load, an inverting gate driver can be used for the inverter in Figure 4-3. Gate drivers are designed to quickly charge and discharge the large gates of power MOSFETs, and many can do so in the MHz frequency range. Comparators and SR Latch Several issues arise in the choice of the comparators and SR latch for the hysteretic modulator. These include the comparator a nd latch speeds, offset voltage, and supply voltages needed for the latch and comparator. Comparator and Latch Speed Any delay between the signal CMODV and the current source up I can greatly influence the operating frequency of the modulator. Figure 4-4 illustrates two possibilities for the triangular waveform CMODV. The solid line represents an ideal system with no delays, while the dashed line show s a system where delays are present.

PAGE 35

26 Comparator delay and latch de lay both cause the operating fre quency to decrease because they slow the propagation of the switching signal to up I Tdelay = 1 fdelayT = 1 f Figure 4-4: VCMOD for the ideal case without delays (solid) modulates between the two hysteretic thresholds. Delays cause VCMOD to overshoot the thresholds (dashed) and change frequency. With ideal comparators, when the triangle wave crosses a hyster etic threshold the output of the comparator should switch. If no other delays are present in the latch and switching logic, the current source up I will immediately switch and the triangle wave will reverse direction. An ideal system such as this experiences no ove rshoot of the hysteretic limits. For non-ideal comparators, however, ther e is a small delay time after the triangle crosses the hysteretic limit, cdelayt. During this delay time, the signal telling up I to switch positions has not yet propagated past the comparator. The same current continues to charge or discharge M ODC, and CMODV continues past the hystere tic limit. The overshoot causes the frequency of the triangle to be less than the ideal case. Similarly, the delay of the SR latch can cause overshoot of the hysteretic limits. For an ideal comparator, the output switches as the triangle reaches a hysteretic limit. Delay in the latch, ldelayt, causes up I to remain in the same state, much in the same manner as comparator delay. The voltage wi ll continue in the same direction, either charging or discharging M ODC, and will overshoot.

PAGE 36

27 The delays of the comparator and latc h can be added to find the total delay encountered before the switching logic. delaycdelayldelayttt (4.13) In order to achieve the de sired operating frequency, th e total delay must be much less than the operating period, 1delaytT f (4.14) or 0.01delaytT (4.15) Selection of the Offset Voltage Depending on the comparator, there is a ch ance that there will be some overshoot of the lower hysteretic limit as seen in Figure 45. This is due to the fact that the lower limit is set to ground, the same as the lower supply voltage. This type of biasing can cause transistors in the comparator to en ter regions of operation that have slower performance. In this case, an offset voltage,offsetV, is used to correct the overshoot. The lower hysteretic limit is set tooffsetV, so that even if CMODV overshoots the threshold, the triangle modulates between cmdV and zero. 0 t t VCMODVoffsetVovershoot Figure 4-5: Overshoot of the lower hysteretic limit requires the use of offsetV.

PAGE 37

28 Choosing offsetV is done by assuming that the slope of the voltage waveform is constant and independent of th e hysteretic limit. In a timet the voltage will overshoot zero, which was the original th reshold, by an amount equal to overshootV. To remove this overshoot, the waveform must cr oss the new hysteretic limit,offsetV, at a time t before it crosses zero. For a constant slope, this means that offsetovershootVV (4.16) The exact amount of overshoot present may not be known in the design stage and may need to be empirically determined. It is therefore a good de sign practice to leave offsetV as an adjustable parameter. Design Summary This chapter has examined the design of a hysteretic modulator to be used in an LCAM system. The design procedure is summarized in Table 4-1. Parameters and components selected for the e xperimental circuit are include d in the table, with brief comments on why they were chosen. Those that do not have specific design equations associated with them should be chosen to accommodate the system to which they are being applied. Acceptable component delays depend upon the chosen frequency of operation, and the power supply rails are design-specific.

PAGE 38

29 Table 4-1: Design summary for the hysteretic modulator needed to implement LCAM control on the boos t converter. Design Specification Design Equation Value/ Component Comments/Selection Criteria Frequency Specified by converter ~500kHz T = 2000ns Vcc User Defined 12V Vee User Defined -12V Provides wide voltage range for testing purposes. CMOD User Defined 68pF, Mica temp/current independent Rdown (4.4) 5.1kohm Idown = 1mA, when Vcmd = Vcmdmax = 5V Rup (4.6) 2.4kohm Iup = 2mA, when Vcmd = Vcmdmax = 5V Zener (4.7) 1N4735 Vz = 6.2V, Imax = 146mA, Imin = 1mA Rbias (4.12) 620ohm 41ohm < 620ohm < 1kohm COMP1,2 (4.15) LT1720 tc-delay < 10ns << T = 2000ns SR Latch (4.15) DM74S00N tl-delay < 10ns << T = 2000ns Inverter User Defined ICL7667 tdelay < 60ns << T = 2000ns (for 1nF load) Op-Amp User Defined LM837A PNP User Defined 2907 NPN User Defined 2N2222 Voffset (4.16) 0.84V Experimentally determined.

PAGE 39

30 CHAPTER 5 SIMULATION AND VERIFICATION The purpose of this chapter is to verify the operation of the LCAM system applied to the boost converter. The firs t section includes expl anations of the ci rcuits and circuit models used for theoretical ca lculations, simulations and gathering measured data. The second section examines the measured result s of a working LCAM system, and compares them to data from the models and simulations. Verification Techniques This section begins with a derivation of the boost transfer function using LCAM from a simplified circuit model. The circu it used for simulations is presented next. Finally, a schematic of the system used to gather measured data is shown and measurement techniques are discussed. Boost Transfer Function with LCAM In the steady-state, the output voltage of the ideal boost converte r in Figure 1-1 is given in (1.1). A more physical model with lo sses included can be seen in Figure 5-1. RL L CL Vin D1 M1Vout GD1 Rind Vdiode Rdiode Rds Iout Figure 5-1: Boost c onverter with losses.

PAGE 40

31 The output voltage of the boost with losses [1] can be approximated by 2 21L outindiode inddsdiodeDR VVDV DDRRDRDR (5.1) If the output current,out I is constant, then the load L R in (5.1) can be replaced by out L outV R I (5.2) Substituting equation (5.2) into (5.1) and solving for outV yields 2 21outindiodeinddsdiode out outD IVDVRDRDR DI V D (5.3) Using the LCAM scheme, the compliment duty cycle produced is given by in cmdV D V (5.4) Combining (5.3) and (5.4), the new relationship between outVand cmdVis found to be 21cmdinin outcmddiodeoutinddsdiode incmdcmdVVV VVVIRRR VVV (5.5) The new output voltage can be split into three terms, cmdVand two loss terms. The first loss term is the forward voltage drop of the diode, diodeV, which is assumed to be constant to simplify these calculations. This simplification is justified by the previous assumption of a constant output current. The second loss term is depe ndant on the operating point of the modulator and the losses asso ciated with the converter. Th e converter losses for this model can be seen in Table 5-1. If the conve rter losses are removed, (5.5) reduces to the ideal LCAM relationship of (2.2). Table 5-1: Boost conve rter loss term values. Loss Term Value Rds 10mOhm Rind 8mOhm Vdiode 0.20V Rdiode 40mOhm

PAGE 41

32 Simulation Model The schematic seen in Figure 5-2 is used in Saber to simulate the operation of the boost converter with LCAM control. Compone nt values and operating parameters for the hysteretic modulator are given in Table 5-2. These values and components were chosen using the design methodology of Chapter 4. The values for the boost converter components are given in Table 5-3. Table 5-2: Hysteretic modulator simulation parameters and components. Component Value / Part # Vcc +12V Vee -12V R1 5.8kOhm R2 2.7kOhm Vos 0.048V CMOD 150pF LATCH ndlch_l4 Q1 mmbt2222_sl Q2 mmbt2907_sl U1,2 lm837_sl COMP1,2,3 comp_l4 Table 5-3: Boost converter va lues used in simulation. Component Value CL 20.1uF L 4.6uH Rind 8mOhm Rds 10mOhm Vdiode 0.20V Rdiode 40mOhm Experimental Verification Experimental data are gathered from an LC AM system whose schematic is seen in Figure 5-3. The bill of materials at the end of the chapter lists all of the components and component values used to construct this circ uit. In order to make the measurements more uniform, the boost converter was loaded with a constant-current active load.

PAGE 42

33 Figure 5-2: Saber schematic us ed for circuit simulations. Waveforms were measured with the Tektr onix TDS460A 4-channel oscilloscope. The value of out I was verified with a Tektronix TM502A current probe. The bias and offset voltage used to implement the design in Figure 5-3 can be found in Table 5-4. Table 5-4: Bias and offset voltages Design Specification Value/Component Vcc 12V Vee -12V Voffset 0.84V

PAGE 43

34 CMOD + Q QSET CLRS R + Vcmd + VCMODCOMP1COMP2 Rup Vcc/2 Vcc Vee+ Rdown Vee/2 + Vcmd Vee Vcc+ Vee/2 Vcc GND INAINBOUTAOUTBU3 Vcc/2 + VcmdVcc/2 1k U1bU1aQ1Q2 Rbias Vcc Voffset RL L1 CL Vin D1 M1 Vout GD1 Vz+ + COMP3DZ IoutU2 Figure 5-3: Boost convert er and LCAM system used to measured data. Results Figure 5-4 shows several of the key ope rational waveforms taken from the boost converter with the LCAM syst em. The triangular carrier, CMODV, ramps between the two hysteretic limits. These limits are set to zero andcmdV, which is 5V in this case. The square wave is the PWM signal output from COMP3 that drives M1. The output voltage,outV, is a DC signal with some switching noise. The average value of outVis approximately 5V, the same ascmdV.

PAGE 44

35 Figure 5-4: Measured waveforms. Figure 5-5 demonstrates the linearity of the output volta ge under LCAM control. The input voltage,inV, and output current,out I were kept constant while the reference voltage,cmdV, was swept. The close agreement be tween the calculated, simulated and experimental data suggests that the mode ls of the LCAM system are accurate. The ultimate goal of the LCAM system is to force the steady-state output voltage of the boost converter to be a linear function of only the command voltage. This ideal behavior can be accomplished in a lossless c onverter. However, as (5.5) suggests, the effects of the input voltage and output current cannot be ignored. VCMOD PWM Signal Vout

PAGE 45

36 Vout vs. Vcmd2.50 3.00 3.50 4.00 4.50 5.00 3.03.23.43.63.84.04.24.44.64.85.0Vcmd (V)Vout (V) Measured Calculated Simulated Iout = 1A, Vin = 3V Figure 5-5: outVvs. cmdVcurve with calculated, simu lated and measured data. In Figure 5-6, the measured outVvs. cmdVis plotted for a family of out I values. The value of inVis held constant at a nominal va lue. As suggested by (5.5), high out I values increase the losses produced by the operatingpoint dependant term and lead to smaller output voltages. V out vs. Vcmd with varying Iout 2.50 3.00 3.50 4.00 4.50 5.00 33.23.43.63.844.24.44.64.85 Vcmd (V)Vout (V) 1 Amp 2 Amp 3 Amp Vin = 3V Figure 5-6: A family of outVvs. cmdVcurves for several values of out I

PAGE 46

37 Figure 5-7 shows the effect that different inV values have onoutV. For each different value ofinV, out I is held constant while cmdVis swept. According (5.5) as inV gets larger the second loss term is reduced and outVis higher for a specific value of cmdV. V out vs. Vcmd with varying Vin 2.50 3.00 3.50 4.00 4.50 5.00 3.03.23.43.63.84.04.24.44.64.85.0 Vcmd (V)Vout (V) 2.7V 3.0V 3.3V Iout = 1A Figure 5-7: A family of outVvs. cmdVcurves for several values of inV. It should be noted that while inVand out I offset the outV vs. cmdV curves in Figure 5-6 and Figure 5-7, the linear rela tionship between the command and the output is preserved.

PAGE 47

38 Table 5-5: Bill of materials Item Quantity Reference Part Footprint Vendor Vendor Part # 1 1 L 4.6uH Axial Wilco LFB47G 2 1 CL 20.1uF Radial OSCON 20SP22M 3 1 M1 NMOS SO-8 Fairchild FDS6670 4 1 GD1 Gate Driver 8PDIP Texas Instruments UCC27324 5 1 D1 Diode TO220AB International Rectifier 40L15CT 6 1 RL Active Load N/A acd c electronics EL-300 7 3 COMP1, COMP2, COMP3 Comparator SO-8 Linear Technology LT1720 8 1 CMOD 68pF Radial Various Various 9 1 Rdown 5.1kOhm Axial Various Various 10 1 Rup 2.4kOhm Axial Various Various 11 1 DZ 6V Zener Diode Axial Axial 1N4735 12 1 Rbias 620Ohm Axial Various Various 13 1 U2 NAND Gate 14PDIP Fairchild Semiconductor DM74S00N 14 1 U3 Inverter 8PDIP MAXIM ICL7667 15 2 U1 Op-Amp 14PDIP National Semiconductor LM837N 16 1 Q1 PNP TO-92 Fairchild Se miconductor PN2907A 17 1 Q2 NPN TO-92 Fairchild Semiconductor PN2222A

PAGE 48

39 LIST OF REFERENCES [1] R.W. Erickson, Fundamentals of Power Electronics. Norw ell, MA: Kluwer Academic Publishers, 2001. [2] K. Smedley and S. uk, “One-cycle control of sw itching converters.” PESC ’91 Record. 22nd Annual IEEE Power Electronics Specialists Conference (Cat. No.91CH3008-0). Cambridge, MA, USA, 24-27 June 1991. p. 888-896. See also IEEE Transactions on Power Electronics, Nov. 1995 and US Patent 5,278,490 [3] B. Arbetter and D. Maksimovi “Feed-forward pulse -width modulators for switching power converters.” PESC ’95 Record. 26th Annual Power Electronics Specialists Conference. Atlanta, GA, USA, 18-22 June 1995. p.601-607.

PAGE 49

40 BIOGRAPHICAL SKETCH Alex Phipps obtained his BS degree in El ectrical Engineering fr om the University of Florida in 2004. He has been a research assistant for the Department of Electrical Engineering at UF since 2005 and is currently a Masters candidate. Hi s field of interest is the design of electronic circuits for power management.


Permanent Link: http://ufdc.ufl.edu/UFE0014374/00001

Material Information

Title: Linearization Through Carrier Amplitude Modulation (lcam) Control of the Boost Converter
Physical Description: Mixed Material
Copyright Date: 2008

Record Information

Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
System ID: UFE0014374:00001

Permanent Link: http://ufdc.ufl.edu/UFE0014374/00001

Material Information

Title: Linearization Through Carrier Amplitude Modulation (lcam) Control of the Boost Converter
Physical Description: Mixed Material
Copyright Date: 2008

Record Information

Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
System ID: UFE0014374:00001


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Full Text











LINEARIZATION THROUGH CARRIER AMPLITUDE MODULATION (LCAM)
CONTROL OF THE BOOST CONVERTER














By

ALEX GEOFFREY PHIPPS


A THESIS PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
MASTER OF SCIENCE

UNIVERSITY OF FLORIDA


2006































Copyright 2006

by

Alex Geoffrey Phipps





















TABLE OF CONTENTS


page

LIST OF TABLES ................ ...............v............ ....


LIST OF FIGURES .............. ....................vi


AB S TRAC T ......_ ................. ..........._..._ viii..


CHAPTER


1 INTRODUCTION ................. ...............1.......... ......


2 CONTROL METHODS .............. ...............4.....


Standard M odulation .................... ......... .. ............
Non-Standard Modulation Control Methods ................. ............. ......... .......5
One-Cycle Control............... ...............5.
Feed Forward Control ................. ...............7............ ....
LCAM Control............... ...............8.


3 HY STERETIC MODULATOR ............_......__....._ .............1


Ideal Hysteretic Modulator ........._.__....... .__. ...............12...
Basic Operation ........._.__........_. ...............12....
Operating Frequency .............. ...............14....
Current Sources ........._.___..... .__. ...............14....
M odulation Capacitor......................... ..........1
Physical Realization of the Hysteretic Modulator ....._.__._ ........___ ................17

4 DESIGN ORIENTED MODELING ................ ...............19................


Realizing the Modulation Frequency ................. ...............19................
S el section of C MlOD ........ ...............20

D esig n o f Idown .............. ...............21 2
Design of lup ................. ............. ................ ........ ......... ...._.21
Switching Logic and Level Shifting ................. ...............22........... ...
Design of the Level Shifter............... ...............24
Selection of the Inverter ................. ...............25.......... ....

Comparators and SR Latch ................. ...............25................
Comparator and Latch Speed .............. ...............25....












Selection of the Offset Voltage ................. ...............27........... ...
Design Summary .............. ...............28....


5 SIMULATION AND VERIFICATION ................. ...............30................


Verification Techniques................ ........... .........3
Boost Transfer Function with LCAM .............. ...............30....
Simulation M odel .............. ...............32....

Experimental Verification .............. ...............32....
Re sults ................ ...............34.................


LIST OF REFERENCES ................. ...............39........... ....


BIOGRAPHICAL SKETCH ............. ..............40.....



















LIST OF TABLES

Table pg


4-1 Design summary for the hysteretic modulator needed to implement LCAM
control on the boost converter. .............. ...............29....

5-1 Boost converter loss term values ................. ...............31...............

5-2 Hysteretic modulator simulation parameters and components............... ...............3

5-3 Boost converter values used in simulation. .............. ...............32....

5-4 Bias and offset voltages ............ ...... .___ ...............33...

5-5 Bill of materials ........._.___..... .___ ...............38....


















LIST OF FIGURES


Figure pg

1-1 Standard PWM boost converter topology. ............. ...............1.....

1-2 Boost transfer function Vout /Rn vs. D and D' ........... ...............2......


2-1 Waveforms used to generate the PWM signal for the standard modulation
configuration. ............. ...............4.....

2-2 One-Cycle controlled, constant-frequency switch. ............. ....................6

2-3 Waveforms for one-cycle controlled, constant-frequency switch. ................... ..........7

2-4 Feed-Forward PWM controller for boost converter .............. ....................7

2-5 Operational waveforms for Feed-Forward PWM controller ................. .................8

2-6 PWM waveforms with LCAM system ................. ...............10...............

2-7 Block diagram of the complete system used to realize LCAM control for the
boost converter. ................. ...............11.......... .....

3-1 Ideal hysteretic modulator ................. ...............12................

3-2 The voltage across CMO .............. ...............13....


3-3 Triangle shapes that can be achieved with a hysteretic modulator. .........................14

3-4 Physical realization of the hysteretic modulator using non-ideal components. .......18

4-1 Schematic of the non-ideal hysteretic modulator. ................ ......... ...............19

4-2 Current source topology ................. ...............22.......... ....

4-3 Level shifting implementation. ............. ...............23.....

4-4 VCMO for the ideal case without delays modulates between the two hysteretic
thresholds .............. ...............26....


4-5 Overshoot of the lower hysteretic limit requires the use of V4s, .. .. .. .. .. .. .. .. .. .. .. .. ..27











5-1 Boost converter with losses. .............. ...............30....

5-2 Saber schematic used for circuit simulations. ............. ...............33.....


5-3 Boost converter and LCAM system used to measured data ................. ................34

5-4 Measured waveforms. ............. ...............35.....


5-5 Vo,,,~ vs. Vci UTVe with calculated, simulated and measured data. ...........................36


5-6 A family of Vo,,.,~ vs.,, Vci CUVSFTSeVeral values of lo,,,. ............. ....................36


5-7 A family of Vo, vs. V cund CUTVC OTSeVeral values of F, ...37.................
















Abstract of Thesis Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Master of Science

LINEARIZATION THROUGH CARRIER AMPLITUDE MODULATION (LCAM)
CONTROL OF THE BOOST CONVERTER

By

Alex Geoffrey Phipps

May 2006

Chair: Khai Ngo
Major Department: Electrical and Computer Engineering

In order to design a robust DC-DC converter, it is essential that the system be

controllable. The pulse width modulated (PWM) DC-DC boost converter presents a non-

linear system with respect to the PWM duty cycle, and standard linear control techniques

cannot be applied.

Typical control methods generate the PWM waveform by comparing a fixed

amplitude carrier to a variable magnitude DC reference. This thesis proposes a control

method of Linearization through Carrier Amplitude Modulation (LCAM). In LCAM

control, the PWM signal is generated by comparing a variable amplitude carrier signal to

a fixed DC reference. When this PWM signal is applied to the boost converter, it is

shown that the output voltage of the converter is directly proportional to the amplitude of

the carrier. The carrier signal is generated by a hysteretic modulator. The amplitude of

the carrier from the hysteretic modulator is equal to a reference input signal, and the










output voltage of the boost converter is therefore directly proportional to the reference.

Using the hysteretic modulator, the output will linearly track the reference signal.

Operation and design of the hysteretic modulator are examined for LCAM control

of the boost converter, and a design metric for the hysteretic modulator is included for

constant frequency operation. Sources of delays and hysteretic limit overshoot are

examined and their effects on operating frequency are included.

Models of the boost converter with LCAM control are given which predict the

linear behavior. For an ideal boost converter, the output voltage is independent of the

output current and input voltage. In a second order system with converter parasitics

included, these other signals can superimpose small operating-point dependant loss terms.

If losses can be minimized, however, the linear terms will dominate. Simulations and

measured data are compared with the models in order to verify linear operation of the

system. Input voltage and output current are varied to verify the second order effects.















CHAPTER 1
INTTRODUCTION

For switching DC-DC converters, controllability is essential for robust circuit

design. In a Pulse Width Modulated (PWM) converter topology, the width of a constant-

frequency pulse is modulated in order to control one or more of the converter' s variables.

For a boost converter, the transfer function, Vo,, En as function of the PWM duty ratio,

D, is nonlinear. Standard linear control processes, including voltage feedback and

current-mode control are more effective on linear systems.

The standard Pulse Width Modulated (PWM) DC-DC boost converter can be seen

in Figure 1-1.



1 D +
Vin ~~PWM inputM1CRL Vu
(I~~~j GD1~" R2v~
Duty cycle = D



Figure 1-1: Standard PWM boost converter topology.

A switching network comprising M1 and D1 is used to boost the input voltage, V,,


up to the desired output voltage, Vou, The output voltage that the converter delivers to the

load, RL, iS controlled by a pulse-train signal sent to the gate of M1. Control of the output

voltage is achieved by modulating the duty cycle, D of the pulse-train. Using volt-

second-balance and amp-second-balance [1], it can be shown that the transfer function

for steady state operation of the boost converter is










V 11
o"' (1.1)
V1- D D'


where the compliment duty cycle D' = 1- D

If the duty cycle is the control variable, the transfer function of (1.1) is non-linear

with respect to both D and D'. This non-linearity can be further seen in Figure 1-2, which

plots the relationships established in (1.1).



Boost Transfer Function (Vout/Vin) vs. D and D'

100 -TF vs. D
TF vs. D'
80




20


0.00 0.20 0.40 0.60 0.80 1.00
D, D'



Figure 1-2: Boost transfer function Vout /En vs. D andD'. These functions are highly
nonlinear.

Classical linear control techniques cannot be applied to non-linear systems, and

stability of such systems is difficult to achieve. The goal of this work is to present a

method to linearize the dc relationship between the transfer function of the boost and its

control variable. Chapter 2 examines the standard control method used to generate the

PWM signal for linear switching converters and shows why it will not work for the boost

topology. Other complex methods used to control non-linear converters are also

examined. Finally a new control method, Linearization through Carrier Am litude

Modulation (LCAM) is presented for the boost converter. Chapter 3 explores the










operation of a hysteretic modulator, which is the fundamental building block for the

LCAM control system. Chapter 4 presents a detailed design methodology for

implementation of the hysteretic modulator. Chapter 5 verifies LCAM control by

comparing theory, simulations and measured data.
















CHAPTER 2
CONTROL METHODS

Standard Modulation

A standard modulation scheme is often used to generate the PWM signal for

switching converters. This method involves comparing a fixed amplitude carrier with a

slowly varying, or dc, modulating signal. Making adjustments to the modulating signal

controls the duty cycle of the PWM signal. An example of standard modulation with a

triangular carrier signal can be seen in Figure 2-1.


v ... ,P W M Sig nal






















Figure 2-1: Waveforms used to generate the PWM signal for the standard modulation
configuration.

Using the similar triangles formed in Figure 2-1 it can be seen that

Vcm D -T,
md= D (2.1)
Peak T












Since Vpeak is fixed, the duty cycle, D is a linear function of the command voltage, Icnid .

However, from (1.1), the transfer function of the boost is non-linear with respect to the

duty cycle. Therefore, the boost transfer function is non-linear with respect to Vcnid, and

linear feedback schemes cannot be applied control the output.

Non-Standard Modulation Control Methods

For any PWM converter topology, the goal of making a circuit linear is to force it

to behave with the following characteristic:

Yout k cnid (2.2)

Here k is a constant and Vcnid S a controllable command signal. The command signal

varies slowly compared to the converter switching frequency and can be considered to be

quasi-DC in the steady-state. There are two major benefits to achieving the behavior in

(2.2). First, the output of the converter can be linearly controlled using only the

command voltage. Second, in the ideal case, the output signal is independent of all other

input parameters, including ,, This means that changes to the input of the converter will

not greatly impact steady-state performance.

Two common methods to achieve the linear behavior of (2.2) are One-Cycle

Control [2], and Feed-Forward PWM Control [3]. These are non-linear methods used to

achieve large-signal modulation control of switching converters. For each of these

methods, however, certain drawbacks can arise due to complexity of the circuits.

One-Cycle Control

The schematic for a One-Cycle controlled, constant-frequency switch can be seen

in Figure 2-2. In the One-Cycle scheme, operation of the circuit is initiated by the clock








signal which closes the switch. With the switch closed, y(t) = x(t), and I, ramps up

until it reaches Vcnid in the following manner:


xr(t)dt = Vcni (t) (2.3)

Waveforms from this circuit can be seen in Figure 2-3. The average value of the switch
output, y(t) is found to be

y~t)= x~~dt(2.4)

and therefore,

y(t)= Vcni(t) (2.5)


For the boost converter y(t) = Vo,, (t) Substituting this into (2.5) yields the desired linear

relationship between the command voltage and the output.

Yout = cnd (2.6)


x(t) y(t)



Controller

Clock ~ +- IV~V, INT!


Figure 2-2: One-Cycle controlled, constant-frequency switch.


















.... .. x(t)





....J ..... ...Vcmd




Figure 2-3: Waveforms for one-cycle controlled, constant-frequency switch.

The integrators needed for this circuit must have a reset, and the integration

function can lead to cumbersome control equations. Complicated circuits may also be

required to minimize errors due to delays in the reset process.

Feed Forward Control

The Feed-Forward PWM (FF-PWM) controller used for a boost converter with

leading-edge modulation can be seen in Figure 2-4. As in One-Cycle, the circuit is

initiated by the clock, which resets the integrator. The command voltage, Vcind, iS


integrated to create a ramp, which is compared to the converter input voltage. The PWM

output created by this system can be seen in Figure 2-5.


CLOCK


Vcmd IN UT

Vin/k INT VPWM~



Figure 2-4: Feed-Forward PWM controller for boost converter with leading-edge
modulation.






















Figure 2-5: Operational waveforms for Feed-Forward PWM controller.

It can be shown that for boost converters with PWM signals generated in this

manner, the output voltage is proportional to the command voltage

Vou = k Vcm (2.7)
Like One-Cycle control, integrators with reset are central to FF-PWM control

schemes [3]. The integrators are used to realize complex equations necessary to achieve

linear behavior. Several other elements are needed to achieve FF-PWM including, a

comparator, a mono-stable pulse circuit and a clock signal. Time constants of the

integrators and the clock must be closely matched, or a dependence on the input voltage

may anise.

LCAM Control

The general linearization concept given in (2.2) can be specifically applied to the

boost converter using the boost transfer function given in (1.1). Substituting the value of

Vou, from (2.2) into (1.1), it can be shown that

k cd 1
md (2.8)
P D'
Solving for D',


D' = (2.9)
k cmd









This means that if the output voltage of the boost is to behave linearly as in (2.2), the

switching MOSFET, M1, in Figure 1-1 must be driven with a PWM signal having a

compliment duty cycle that obeys the relationship in (2.9).

To achieve a PWM si nal where D' satisfies (2.9) the Linearization thro gh

Carrier Amplitude Modulation (LCAM) control system is used. The LCAM system is

similar to the conventional PWM generator used for standard linear control. Again, a

triangular carrier is compared to the modulating signal in order to generate the PWM

signal. In this new scheme, however, the amplitude of the carrier is modulated also. The

modulating signal, which must not be confused with the amplitude modulated carrier,

should not change much within one carrier period. In order to realize (2.9), the LCAM

system uses configuration in Figure 2-6(a). The peak of the carrier signal is equal

tok Vcmd, and 6, acts as the modulating signal. Using the similar triangles seen in

Figure 2-6(b), it can be seen that

D'T~
"= D' (2.10)
k V ,

Therefore, the PWM signal generated by the LCAM system is that of (2. 10). This signal

satisfies the requirements of (2.9) and will therefore force the desired linear behavior for

the boost converter specified in (2.2).

It is important to realize that the goals and results of One-Cycle, FF-PWM and

LCAM are the same. Namely, all of these methods force switching converters to behave

linearly as in (2.2). The differences between these concepts arise from their respective

derivations and hardware implementations. LCAM does not propose a new concept of

linearization, but rather a different method by which to implement it.






10











t


Vcarrier
PWM Signal

Vn
I~ (a)


Figure 2-6: PWM waveforms with LCAM system. (a) Generation of the PWM signals
for the linearized boost converter using the LCAM system. (b) Comparator
inputs and output for a amplitude modulated carrier.

The constant k is used as a scaling factor for Vcmd. Ifk = 1,

Yout md Vc (2. 11)

For boost converters, the desired Vou, may be much larger than any available command

voltage. By using the factor a PWM signal with the desired duty cycle can still be

produced with a lower command voltage. It will be assumed for the remainder of this

paper that Vcmd iS nominal voltage that can be easily obtained. For simplicity the

scaling factor k is assumed to be equal to one.

A block diagram showing the complete LCAM system applied to the boost

converter can be seen in Figure 2-7. The PWM signal is generated by comparing V, to

the amplitude modulated triangular carrier. This triangular carrier is generated by a

hysteretic modulator whose input is the control reference Vcmd The upper hysteretic limit

of the modulator determines the amplitude of the triangle wave and is set to Vcmd The

details of the modulator' s operation are covered thoroughly in Chapter 3.










Vcarnler
Vret Hysteretic
Modulator +


To
PWM
Switch
Vin

Boost Vu
Converter


Figure 2-7: Block diagram of the complete system used to realize LCAM control for the
boost converter.












CHAPTER 3
HYSTERETIC MODULATOR

This chapter examines the operation of a hysteretic modulator, both in its ideal

form and in a physical circuit realization.

Ideal Hysteretic Modulator
Basic Operation
The hysteretic modulator is used to create a triangular voltage waveform whose

amplitude can be directly modulated with the quasi-DC command voltage, Vcmd. An ideal

diagram of the hysteretic modulator is shown in Figure 3-1.


Vee


SET
S Q


CMIOD~ -


Down


R CLR


SVee
Figure 3-1: Ideal hysteretic modulator.


Switch Control


COMPI


COMP2

































I~ \ / 1 I CMOD


Operation of the modulator begins with the capacitor IOD discharged and the

current source I,, switched off, so it does not conduct. The current source Istw,, draws

current from IOD, Which lowers the voltage, VCOD, Slightly below zero. As this occurs,

comparator COM~P, outputs a logic low and the SR latch is reset. The switch control


logic causes I~~ to switch on. For proper circuit operation it is assumed that I,,) > Ictom .

With this assumption, IOD is now charged up with a constant current,


icA, =IOD up Io,,_ i. The voltage VCMO ramps up at a constant rate as seen in Figure 3-2.


Vcmd


V.,' 's'L,'O

Figure 3-2: The voltage across IOD CIO ramps up and down between the two
hysteretic limits V, and V V+ is set to ,f and V is grounded in this case.

When the magnitude of VCMOD grOws slightly larger than V,2;c, comparaltor COME'~F

outputs a logic low and the SR latch is set. The switch control logic causes I,,, to turn off,

and IOD is discharged by the current sources tow; The constant-current discharge of the

capacitor causes VCMO to ramp back down. As VCMO again falls slightly below zero, the

latch is reset and I,,, is turned back on. The two boundary voltages, I0,,,< and OV, form

the upper and lower hysteretic limits of the modulator. This process of charging and

discharging IOD COntinues, and a triangular waveform seen in Figure 3-2 is produced.










Operating Frequency

The operating frequency of the hysteretic modulator is determined by the speed at

which the current sources charge and discharge the modulation capacitor COD With the

desired operating frequency known, the relationships between the current sources and

modulation capacitor can be derived to achieve the leading edge, trailing edge and

symmetrically modulated triangular waveforms in Figure 3-3.




Leading Edge (LE)






tnse tall
Trailing Edge (TE)





Symmetrical






Figure 3-3: Triangle shapes that can be achieved with a hysteretic modulator.

Current Sources

From basic circuit theory, the relationship between the current and voltage of a

capacitor is

dv Av
i, = C c C c (3.1)
Sdt At

Using this approximation and the signals from Figure 3-1, (3.1) can be rearranged to










CMOD~l I
(3.2)
At CMOD


For a given modulator design, CMO is fixed and lAvCO = Vcmd Which is the same

for both charging and discharging events. This is due to the fact that the hysteretic

thresholds are relatively fixed within each switching period as long as the carrier

amplitude varies slowly compared to the switching period. Substituting lAvCMOD = Vicmd

into (3.2), it is seen that

VcmdCMiOD = CMOD Icharging n'se (3.3)
and

Vcm'dCMOOD =CMOD discharging faull (3.4)

for any of the waveforms in Figure 3-.

Next, equating (3.3) and (3.4) it is shown that

CMrOD Icharging9= ICMIOD Idischargig (3.5)
tfall
where r
tnse

AsCMO is being discharged, Iup is off, and therefore from Figure 3-1


Idow~n ICMrOD Idischarging (3.6)
Similarly, as CMO is charged up


ICMrOD Icharging= u"p d.own (3.7)

Combining (3.6) and (3 .7)

u~p CMl~OD Icharging CMl-OD Idischarging (3.8)

Finally, substituting (3.5) into (3.8)

IP = (1+ r) ICMrOD dIscharging (3.9)









or

Iu = (1+ r)Idown (3.10)

The ratios determines which type of waveform from Figure 3-3 is produced. For a

leading edge waveform, where tfazz << t,,s, r will be a small value. Conversely, for a

trailing edge r will be large. In a symmetrical waveform, tf,,, = tns and r will be unity.

Modulation Capacitor

The value of the modulation capacitor, CMO needed to achieve a given frequency


is derived from (3.1). Again assuming that AvCMOD = Vcmd ,


CMO CO (3 11)
Vcmd

When CMO is discharging, (3.11) becomes


CMnOD __down (3.12)
Vcmd

For any of the waveforms in Figure 3-3,

T = tns + tfall (3.13)

which can be rearranged into


tfazz =iiK) T ~ +I (3.14)



During the discharge of CMO a fall and (3.12) becomes

cl
MO do" (3.15)
~ fVCMD+









While this derivation was done for a discharging event, the same result is achieved from a

charging event. Any frequency waveform from Figure 3-3 can now be obtained by the

proper choice of Iu Idown, and CMO

Physical Realization of the Hysteretic Modulator

The previous model of the hysteretic modulator provides the means to examine its

operation under ideal conditions. Implementation of the circuit requires the use of non-

ideal parts and physical realization of the hardware needed for logic control. Figure 3-4

shows the schematic of the modulator with non-ideal components that is used to verify

operation in Chapter 5.

Operation of this circuit is similar to the ideal model. A symmetrical triangular

waveform, with ic = 1, is assumed to be used for the circuit of Figure 3-4. As before,

CMO begins discharged, and Iu is initially off. Iu is realized with the trans-conductance

amplifier consisting of Q1 and U1. VCMO is brought down as the current iCMOD doIwn is

drawn from the capacitor, and when VCMO CTOsses the lower hysteretic limit

COM~P2 resets the SR latch. The lower hysteretic limit is can be adjusted by the source

V4~,, toaccount for delays in the comparator and in the switching logic. The reset signal

output from the SR latch is then sent to the switching logic that controls Ip This

switching logic consists of an inverting gate-driver, and a level shifting zener diode. By

controlling the voltage at the top of Iu the current from this source can be switched on

and off. Level shifting of the set and reset signals is necessary to ensure that the active

components of Iu remain in the correct operating modes.







18


The reset signal from the SR latch is inverted and Iu turns on similar to the ideal


case. From (3.10), to achieve a symmetrical triangle wave, I, = 2Id- The capacitor


voltage, VCMO, iS charged up to the upper hysteretic limit, Vcmd, and COMP1 outputs a


logic low to set the latch. The gate driver inverts the set signal from the SR latch causing

Iu to turn off and CMO to discharge. As in the ideal case, modulation continues as CMO

is charged and discharged, and a symmetrical triangle is produced. The causes and

effects of the various delays associated with non-ideal components are covered in

Chapter 4.

Vool +Vcmd V

OUTA INA ba
ICL7667 + Vz
SRup -UBI N
GND


V,/2 Vee V






Vee/2 + Vcmd() U2-V, Q2M
e R CLR 1k


~Rdown Vofe
Vee/2


Figure 3-4: Physical realization of the hysteretic modulator using non-ideal components.

















CHAPTER 4
DESIGN ORIENTED MODELING

This chapter provides a detailed explanation of the non-ideal hysteretic modulator


seen in Figure 4-1. Guidelines for choosing components and component values are also


given. All derivations are made assuming a symmetrical triangle waveform.

Vod2 + VcmdV

OUTVRba
ICL7667 + Vz-

GND

U1 Q1 Vd
Vod2 VeeVcmd


Vs SET

Vee/2 + Vcmd-2 Q2 C,,o VCMOD

V eet,, R CLR
COMP2 1
SRdown -
Vee/2


Figure 4-1: Schematic of the non-ideal hysteretic modulator.

Realizing the Modulation Frequency

Assuming the switching frequency is known, the physical realization of the


hysteretic modulator becomes an iterative process. First, the type of triangle waveform,

leading-edge, trailing edge or symmetrical, must be chosen. For this circuit, a


symmetrical waveform was used and the value of ic = 1. Next, either the value of


CMO Or I,w must be selected. The other value is then calculated using (3.15). It is


possible that this calculated value will exceed some design constraint and values for both










must be redone. For instance, the value of Idown calculated for a chosen capacitance value

may be higher than component tolerances allow. In this case, lower capacitances values

can be iterated until an acceptable I~w is achieved. Iu is always larger than Idown, and

will most likely be unacceptable if I~w is too large.

The relationship between CMO and Idown s WRiven in (3.15) and is repeated here

for convenience.


MnOD icl** (4.1)

Vcmd is the control signal that modulates the amplitude of the carrier, and it is therefore

assumed that Vcmd Will Vary. If Idown is assumed to be fixed, then for changes inVcmd,, the


capacitor CMO must vary in order for frequency to remain the same. Variable

capacitance is difficult to obtain in practice and is not a practical solution. On the other

hand, if CMO is assumed to be fixed, then for constant frequency operation Idown must

vary with Vcmd. Rearranging (4.1) shows a linear relationship between I,w, and Vcmd

iCMOD = 2 fCM~OD~cmd (4.2)
A transconductance, g,, found from (4.2) is defined as

gm __MD = 2 fCMO (4.3)
Vcmd
Selection of CMOD

The choice of CMO must take several factors into account. In order to maintain a

reliable modulation frequency, the capacitance value must be stable over the entire

voltage range of Vcmd and all possible operating temperatures. Since the controller may

be in close physical proximity to the boost converter, there is the possibility of high

temperatures generated by power devices. For integrated designs, CMO Should be as









small as possible, but must remain large enough to overcome parasitic capacitances from

the process. The active devices associated with the current sources can also cause stray

capacitance in parallel with CMOD. Small designs may require small components, which

may put a limit on the capacitance. For non-integrated designs, mica capacitors make a

good choice for temperature and voltage stability.

Design of loown

With a chosen capacitance forCMOD, the relationship between Idown and Vcmd i

(4.3) can be realized using a transconductance current source. A schematic of the source

Idown can be seen in Figure 4-2(a). The current produced by Idown is a function of the

voltage applied across the bias resistor, Rdown To set the transconductance of this source,

the value of Rdw needed is


Down =~(4.4)

Combining (4.3) and (4.4), the resistance needed for the current source Idown is


Rdown =(4.5)
2 fCMO
Design of I,,

The current source Iu seen in Figure 4-2(b) is realized with the same circuit

topology as Idown There are two differences between these current sources. From (3.10),

it can be shown that for a symmetrical triangle wave, where ic = 1, that Iu = 2Idown For


a given value of Vcmd the transconductance of Iu must twice as large as that of Idown to

meet this specification. The bias resistor of Iu is then given by

1 1 1
R= (4.6)
"2 g, 2(2 fCMO) 4 fCMO










The other difference between the two current sources is that I,,, must be able to quickly

switch on and off, while Idow,, remains constant. The voltage across R,,, must therefore

be switched quickly between Pcind in the on state, and zero in the off. It should be noted

that in the off state, the voltage across this resistor does not fall below zero. If the

terminal Ys in Figure 4-2(b) were switched to ground instead of Vc/2, the biasing of the

op-amp and BJT would change. When the current source switches back on, there would

be a recovery time required to re-bias the circuit. During this recovery time there is no

current flowing froml,,p and the triangle wave experiences overshoot and flat-spots.

V cd Ve/2

V,. 1 $Rup

Vcmd + Vee/2 fI


R= Voo/






Current Source Idown Current Source lup
(a) (b)

Figure 4-2: Current source topology used to generate (a) Iciown and (b) I,, in the hysteretic
modulator.

Switching Logic and Level Shifting

Control circuitry is needed to realize the switching of the node y, in Figure 4-2(b),

and also to make sure that the op-amp and BJT remained biased in the active region. The

sub-circuit seen in Figure 4-3 is used to achieve the switch signal that drives the current

source I,, The circuit consists of a zener diode, bias resistor and inverter.





Level Shifted
Signal


TTL from
SR Latch Voo Vod/2 + Vrer

Rbias

-Vz +

Ved/2


-
Vod/2 + Vree




TTLhigh

0


Figure 4-3: Level shifting implementation. Switching circuitry to drive l,, and the
associated input and output waveforms.

The input to the switching logic is a square wave output from the SR latch. This

signal is a standard TTL signal and switches between its power supply voltage and

ground. The switching node of the current source, y is directly controlled by the

inverter, whose power and ground supply rails represent the on and off voltages of I .

By biasing the supply rails in this manner, the inverter' s output will swing between the

two desired levels and prevent the transistors in the current source from leaving the active

region. The zener diode is needed to level shift the TTL latch signal to a level that the

inverter can use as an input. Figure 4-3 shows the result of the level shifting with the

small delay caused by the inverter.










Design of the Level Shifter

Determining the correct amount of DC level shifting is necessary to ensure that the

inverter can input the TTL logic levels from the SR latch. Standard inverters do not

respond properly when the input voltage is less than the value of their ground pin.

Therefore, the zener voltage of the diode, V should be such that it shifts the SR latch

TTL signal by an amount equal to the value of the ground pin on the inverter.


V~ = co(4.7)

By doing this, a logic low from the latch will be at the voltage corresponding to a logic

low on the inverter.

A bias resistor is required to provide current to the cathode end of the zener diode.

Using (4.7), when the input to the zener, I,, is high the voltage across the resistor is

given as


V~al = Ve V -V co V (4.8)

When the input is low


V~, = Ve Vz = co(4.9)

The resistance RI,, must be chosen to provide ample bias current during a high input and

still remain lower than the maximum current during a low input. This means



> I,,, (4.10)

and


co 2Rb,, max









Here Imm is the minimum current required by the zener diode to function as a voltage

level shifter, and Imax is the largest current that the diode can safely conduct.

Combining and rearranging (4. 10) and (4. 11)



co 2b "' (4.12)



Selection of the Inverter

The inverter must be capable of driving the capacitive load of the current source

I,,, without excessive delay. The amount of delay allowed depends on the modulating

frequency of the circuit. The capacitive load of concern is a combination of the

capacitances from the BJT emitter and the op-amp minus pin.

To drive this capacitive load, an inverting gate driver can be used for the inverter in

Figure 4-3. Gate drivers are designed to quickly charge and discharge the large gates of

power MOSFETs, and many can do so in the MHz frequency range.

Comparators and SR Latch

Several issues arise in the choice of the comparators and SR latch for the hysteretic

modulator. These include the comparator and latch speeds, offset voltage, and supply

voltages needed for the latch and comparator.

Comparator and Latch Speed

Any delay between the signal VCMO and the current source I,, can greatly

influence the operating frequency of the modulator. Figure 4-4 illustrates two

possibilities for the triangular waveform VCMO The solid line represents an ideal system

with no delays, while the dashed line shows a system where delays are present.









Comparator delay and latch delay both cause the operating frequency to decrease because

they slow the propagation of the switching signal to I .

Tdelay= delay








Figure 4-4: VhCMOD for the ideal case without delays (solid) modulates between the two
hysteretic thresholds. Delays cause VhCMOD to overshoot the thresholds
(dashed) and change frequency.

With ideal comparators, when the triangle wave crosses a hysteretic threshold the

output of the comparator should switch. If no other delays are present in the latch and

switching logic, the current source Iu will immediately switch and the triangle wave will

reverse direction. An ideal system such as this experiences no overshoot of the hysteretic

limits. For non-ideal comparators, however, there is a small delay time after the triangle

crosses the hysteretic limit, tc-Alay During this delay time, the signal telling Iu to switch

positions has not yet propagated past the comparator. The same current continues to

charge or dischargeCMOD, and VCMO COntinues past the hysteretic limit. The overshoot

causes the frequency of the triangle to be less than the ideal case.

Similarly, the delay of the SR latch can cause overshoot of the hysteretic limits.

For an ideal comparator, the output switches as the triangle reaches a hysteretic limit.

Delay in the latch, tl-Alay ,causes Iu to remain in the same state, much in the same

manner as comparator delay. The voltage will continue in the same direction, either

charging or discharging Cuoo, and will overshoot.










The delays of the comparator and latch can be added to find the total delay

encountered before the switching logic.

tdelay c-delay+ 1-delay (4.13)
In order to achieve the desired operating frequency, the total delay must be much

less than the operating period,


tdea << T = (4.14)

or

tdelay <0.01T (4.15)
Selection of the Offset Voltage

Depending on the comparator, there is a chance that there will be some overshoot

of the lower hysteretic limit as seen in Figure 4-5. This is due to the fact that the lower

limit is set to ground, the same as the lower supply voltage. This type of biasing can

cause transistors in the comparator to enter regions of operation that have slower

performance. In this case, an offset voltage, V4fs,,, is used to correct the overshoot. The

lower hysteretic limit is set toVy4f,,, so that even if VMO Overshoots the threshold, the

triangle modulates between Vcmd and zero.


~t At


Figure 4-5: Overshoot of the lower hysteretic limit requires the use of VO, .









Choosing V4,ss, is done by assuming that the slope of the voltage waveform is

constant and independent of the hysteretic limit. In a time At the voltage will overshoot

zero, which was the original threshold, by an amount equal to Vovershoot, To remove this

overshoot, the waveform must cross the new hysteretic limit, V4s,,, at a time At before it

crosses zero. For a constant slope, this means that

offset ers,,hoot V,(4.16)
The exact amount of overshoot present may not be known in the design stage and may

need to be empirically determined. It is therefore a good design practice to leave V ,,e

as an adjustable parameter.

Design Summary

This chapter has examined the design of a hysteretic modulator to be used in an

LCAM system. The design procedure is summarized in Table 4-1. Parameters and

components selected for the experimental circuit are included in the table, with brief

comments on why they were chosen. Those that do not have specific design equations

associated with them should be chosen to accommodate the system to which they are

being applied. Acceptable component delays depend upon the chosen frequency of

operation, and the power supply rails are design-specific.










Table 4-1: Design summary for the hysteretic modulator needed to implement LCAM
control on the boost converter.
Design Design Value/ Comments/Selection
Speification Eqation Compoent Criteria
Freqenc Speifiedby converter ~500k Vcc User Defined 12V Provides wide voltage range
for testing purposes.
Vee User Defined -12V

CMlOD User Defined 68pF, Mica temp/current indepedent
Rdown (4.4) 5.1kohm Idown = ImA,
when Vcmd = Vcmdmax = 5 V
Rup (4.6) 2.4kohm lup 2mA,
when Vcmd = Vcmdmax = 5 V
Zener (4.7) IN473 5 Vz = 6.2V, Imax = 146mA,
Imin = ImA
Rbias (4.12) 620ohm 410hm < 620ohm < 1kohm

COMP1,2 (4.15) LT 1720 tc-delay < 10ns << T = 2000ns
SR Latch (4.15) DM74S00N tl-dela < 10ns << T = 2000ns
Inverter User Defined ICL7667 tdelay < 60ns << T = 2000ns
(for InF load)
OpAmp User Defined LM837A
PNP User Defined 2907
NPN User Defined 2N2222
Voffset (4.16) 0.84V Experimentally determined.















CHAPTER 5
SIMULATION AND VERIFICATION

The purpose of this chapter is to verify the operation of the LCAM system applied

to the boost converter. The first section includes explanations of the circuits and circuit

models used for theoretical calculations, simulations and gathering measured data. The

second section examines the measured results of a working LCAM system, and compares

them to data from the models and simulations.

Verification Techniques

This section begins with a derivation of the boost transfer function using LCAM

from a simplified circuit model. The circuit used for simulations is presented next.

Finally, a schematic of the system used to gather measured data is shown and

measurement techniques are discussed.

Boost Transfer Function with LCAM

In the steady-state, the output voltage of the ideal boost converter in Figure 1-1 is

given in (1.1). A more physical model with losses included can be seen in Figure 5-1.

L Rind

D1 ld Rdlode
v,n cL L Vout


lou


Figure 5-1: Boost converter with losses.










The output voltage of the boost with losses [1] can be approximated by



V = ( -D' )_ r (5.1)

If the output current, lo,,,, is constant, then the load RL in (5.1) can be replaced by


RL out .(5.2)
lOut
Substituting equation (5.2) into (5.1) and solving for yo,, yields




Vot (5.3)

Using the LCAM scheme, the compliment duty cycle produced is given by


D' = (5.4)
cnid
Combining (5.3) and (5.4), the new relationship between Vo,,, and Ve,,, is found to be



ou cd-Ydod in ycnd cni

The new output voltage can be split into three terms, y ome and two loss terms. The first

loss term is the forward voltage drop of the diode, I cast, which is assumed to be constant

to simplify these calculations. This simplification is justified by the previous assumption

of a constant output current. The second loss term is dependant on the operating point of

the modulator and the losses associated with the converter. The converter losses for this

model can be seen in Table 5-1. If the converter losses are removed, (5.5) reduces to the

ideal LCAM relationship of (2.2).

Table 5-1: Boost converter loss term values.
Loss Term Value
Rds 10mOhm
Rind 8mOhm
Vdiode 0.20V
Rdiode 40mOhm










Simulation Model

The schematic seen in Figure 5-2 is used in Saber to simulate the operation of the

boost converter with LCAM control. Component values and operating parameters for the

hysteretic modulator are given in Table 5-2. These values and components were chosen

using the design methodology of Chapter 4. The values for the boost converter

components are given in Table 5-3.

Table 5-2: Hysteretic modulator simulation parameters and components.
Component Value / Part #
Vec +12V
Vee -12V
R1 5.8kOhm
R2 2.7kOhm
Vos 0.048V
ChlfOD 150pF
LATCH ndlch 14
Q1 mmbt2222 sl
Q2 mmbt2907 sl
U1,2 I~m837 sl
COMP1,2,3 COmp_14


Table 5-3: Boost converter values used in simulation.
Component Value
CL 20.1uF
L 4.6uH
Rind 8mOhm
Rds 10mOhm
Vdiode 0.20V
Rdiode 40mOhm

Experimental Verification

Experimental data are gathered from an LCAM system whose schematic is seen in

Figure 5-3. The bill of materials at the end of the chapter lists all of the components and

component values used to construct this circuit. In order to make the measurements

more uniform, the boost converter was loaded with a constant-current active load.



































gn gdgnd gnd L idRd de


I gnd gnd


Figure 5-2: Saber schematic used for circuit simulations.

Waveforms were measured with the Tektronix TDS460A 4-channel oscilloscope. The

value of Iou, was verified with a Tektronix TM502A current probe. The bias and offset

voltage used to implement the design in Figure 5-3 can be found in Table 5-4.



Table 5-4: Bias and offset voltages
Desin Spcfction Value/Component
Vcc 12V
Vee -12V
Voffset 0.84V




























Vee/2 + Vcmd (^):se 2~R

VofstCOMP2 1k


Vee/2




v~n CL RLotut




Figure 5-3: Boost converter and LCAM system used to measured data.

Results

Figure 5-4 shows several of the key operational waveforms taken from the boost

converter with the LCAM system. The triangular carrier, VCMO, ramps between the two


hysteretic limits. These limits are set to zero and Vcnd Which is 5V in this case. The

square wave is the PWM signal output from COMP3 that drives M1. The output

voltage, Vo,,,, is a DC signal with some switching noise. The average value of Vo,,, is


approximately 5V, the same as ynd *









Tek Run: 100MS/s Sample




1+ VCMOD




2+[ ,P ,;--- ,' PSignal



Vout




Ch 5.00 V Ch2 5.00 V M 500ns Chl I 2.5 V 30 Aug 2005
[ [H 5.00 V 12:16:13


Figure 5-4: Measured waveforms.

Figure 5-5 demonstrates the linearity of the output voltage under LCAM control.

The input voltage, V,, and output current, los,, were kept constant while the reference

voltage, Vcmd WaS swept. The close agreement between the calculated, simulated and

experimental data suggests that the models of the LCAM system are accurate.

The ultimate goal of the LCAM system is to force the steady-state output voltage of

the boost converter to be a linear function of only the command voltage. This ideal

behavior can be accomplished in a lossless converter. However, as (5.5) suggests, the

effects of the input voltage and output current cannot be ignored.












Vout vs. Vcmd
lout = 1A, Vin =3V


5.00 -/ + Measured
-Calculated
4.50
+ Simulated

4.00

3.50

3.00 t

2.50
3.0 3.2 3.4 3.6


3.8 4.0 4.2 4.4 4.6 4.8 5.0
Vcmd (V)


Figure 5-5: Vo,, vs. VcmCUT~e with calculated, simulated and measured data.


In Figure 5-6, the measured Vou, vs. Vcmd is plotted for a family of Iou, values. The


value of V, is held constant at a nominal value. As suggested by (5.5), high los, values


increase the losses produced by the operating-point dependant term and lead to smaller


output voltages.


Vout vs. Vcmd with varying lout

Vin = 3V


3 3.2 3.4 3.6 3.8 4 4.2
Vcmd (V)


4.4 4.6 4.8 5


Figure 5-6: A family of Vou vs. V cmd v CUTVC OTSeVeral values of lo











Figure 5-7 shows the effect that different values have on Vu For each different


value ofn lou, is held constant while Vcmd is swept. According (5.5) as ~,gets larger


the second loss term is reduced and Vou, is higher for a specific value of Vcmd



Vout vs. Vcmd with varying Vin
lout =1A


5.00 --2.7V

4.50 -m-3.0V -

S' 4.00 -A- 3.3V

o 3.50

3.00

2.50
3.0 3.2 3.4 3.6


3.8 4.0 4.2
Vcmd (V)


4.4 4.6 4.8 5.0


Figure 5-7: A family of Vo,,,uy, vs. Vcm CUTVC OTSeVeral values of ~n.


It should be noted that while and los, offset the Vou, vs. V cmCUTVCS in Figure 5-6


and Figure 5-7, the linear relationship between the command and the output is preserved.










Table 5-5: Bill of materials
Item Quantity Reference Part Footprnt Vendor Vendor Part #
1 1 L 4.6uH Axial Wilco LFB47G
2 1 CL 20.1luF Radial OSCON 20SP22M
3 1 M1 NMOS SO-8 Fairchild FDS6670
4 1 GDI Gate Driver 8PDIP Texas Instruments UCC27324
5 1 D1 Diode TO- International Rectifier 40L15CT
220AB
6 1 RL Active Load N/A acdc electronics EL-300
7 3 COMP1, Comparator SO-8 Linear Technology LT1720
COMPz
COMP3
8 1 ChK)D 68pF Radial Various Various
9 1 Rdown 5.1IkOhm Axial Various Various
10 1 R 2.4kOhm Axial Various Various
11 1 Dz 6V Zener Diode Axial Axial 1N4735
12 1 Rblas 6200hm Axial Various Various
13 1 U2 NAND Gate 14PDIP Fairchild Semiconductor DM74S00N
14 1 U3 Inverter 8PDIP MAXIM ICL7667
15 2 U1 Op-Amp 14PDIP National Semiconductor LM837N
16 1 Q1 PNP TO-92 Fairchild Semiconductor PN2907A
17 1 Q, NPN TO-92 Fairchild Semiconductor PN2222A
















LIST OF REFERENCES


[1] R.W. Erickson, Fundamentals of Power Electronics. Norwell, MA: Kluwer
Academic Publishers, 2001.

[2] K. Smedley and S. Cuk, "One-cycle control of switching converters." PESC '91
Record. 22nd Annual IEEE Power Electronics Specialists Conference (Cat.
No.91CH3008-0). Cambridge, MA, USA, 24-27 June 1991. p. 888-896. See also
IEEE Transactions on Power Electronics, Nov. 1995 and US Patent 5,278,490

[3] B. Arbetter and D. Maksimovic, "Feed-forward pulse-width modulators for
switching power converters." PESC '95 Record. 26th Annual Power Electronics
Specialists Conference. Atlanta, GA, USA, 18-22 June 1995. p.601-607.
















BIOGRAPHICAL SKETCH

Alex Phipps obtained his BS degree in Electrical Engineering from the University

of Florida in 2004. He has been a research assistant for the Department of Electrical

Engineering at UF since 2005 and is currently a Masters candidate. His field of interest

is the design of electronic circuits for power management.