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LINEARIZATION THROUGH CARRIER AMPLITUDE MODULATION (LCAM)
CONTROL OF THE BOOST CONVERTER
ALEX GEOFFREY PHIPPS
A THESIS PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
MASTER OF SCIENCE
UNIVERSITY OF FLORIDA
Alex Geoffrey Phipps
TABLE OF CONTENTS
LIST OF TABLES ................ ...............v............ ....
LIST OF FIGURES .............. ....................vi
AB S TRAC T ......_ ................. ..........._..._ viii..
1 INTRODUCTION ................. ...............1.......... ......
2 CONTROL METHODS .............. ...............4.....
Standard M odulation .................... ......... .. ............
Non-Standard Modulation Control Methods ................. ............. ......... .......5
One-Cycle Control............... ...............5.
Feed Forward Control ................. ...............7............ ....
LCAM Control............... ...............8.
3 HY STERETIC MODULATOR ............_......__....._ .............1
Ideal Hysteretic Modulator ........._.__....... .__. ...............12...
Basic Operation ........._.__........_. ...............12....
Operating Frequency .............. ...............14....
Current Sources ........._.___..... .__. ...............14....
M odulation Capacitor......................... ..........1
Physical Realization of the Hysteretic Modulator ....._.__._ ........___ ................17
4 DESIGN ORIENTED MODELING ................ ...............19................
Realizing the Modulation Frequency ................. ...............19................
S el section of C MlOD ........ ...............20
D esig n o f Idown .............. ...............21 2
Design of lup ................. ............. ................ ........ ......... ...._.21
Switching Logic and Level Shifting ................. ...............22........... ...
Design of the Level Shifter............... ...............24
Selection of the Inverter ................. ...............25.......... ....
Comparators and SR Latch ................. ...............25................
Comparator and Latch Speed .............. ...............25....
Selection of the Offset Voltage ................. ...............27........... ...
Design Summary .............. ...............28....
5 SIMULATION AND VERIFICATION ................. ...............30................
Verification Techniques................ ........... .........3
Boost Transfer Function with LCAM .............. ...............30....
Simulation M odel .............. ...............32....
Experimental Verification .............. ...............32....
Re sults ................ ...............34.................
LIST OF REFERENCES ................. ...............39........... ....
BIOGRAPHICAL SKETCH ............. ..............40.....
LIST OF TABLES
4-1 Design summary for the hysteretic modulator needed to implement LCAM
control on the boost converter. .............. ...............29....
5-1 Boost converter loss term values ................. ...............31...............
5-2 Hysteretic modulator simulation parameters and components............... ...............3
5-3 Boost converter values used in simulation. .............. ...............32....
5-4 Bias and offset voltages ............ ...... .___ ...............33...
5-5 Bill of materials ........._.___..... .___ ...............38....
LIST OF FIGURES
1-1 Standard PWM boost converter topology. ............. ...............1.....
1-2 Boost transfer function Vout /Rn vs. D and D' ........... ...............2......
2-1 Waveforms used to generate the PWM signal for the standard modulation
configuration. ............. ...............4.....
2-2 One-Cycle controlled, constant-frequency switch. ............. ....................6
2-3 Waveforms for one-cycle controlled, constant-frequency switch. ................... ..........7
2-4 Feed-Forward PWM controller for boost converter .............. ....................7
2-5 Operational waveforms for Feed-Forward PWM controller ................. .................8
2-6 PWM waveforms with LCAM system ................. ...............10...............
2-7 Block diagram of the complete system used to realize LCAM control for the
boost converter. ................. ...............11.......... .....
3-1 Ideal hysteretic modulator ................. ...............12................
3-2 The voltage across CMO .............. ...............13....
3-3 Triangle shapes that can be achieved with a hysteretic modulator. .........................14
3-4 Physical realization of the hysteretic modulator using non-ideal components. .......18
4-1 Schematic of the non-ideal hysteretic modulator. ................ ......... ...............19
4-2 Current source topology ................. ...............22.......... ....
4-3 Level shifting implementation. ............. ...............23.....
4-4 VCMO for the ideal case without delays modulates between the two hysteretic
thresholds .............. ...............26....
4-5 Overshoot of the lower hysteretic limit requires the use of V4s, .. .. .. .. .. .. .. .. .. .. .. .. ..27
5-1 Boost converter with losses. .............. ...............30....
5-2 Saber schematic used for circuit simulations. ............. ...............33.....
5-3 Boost converter and LCAM system used to measured data ................. ................34
5-4 Measured waveforms. ............. ...............35.....
5-5 Vo,,,~ vs. Vci UTVe with calculated, simulated and measured data. ...........................36
5-6 A family of Vo,,.,~ vs.,, Vci CUVSFTSeVeral values of lo,,,. ............. ....................36
5-7 A family of Vo, vs. V cund CUTVC OTSeVeral values of F, ...37.................
Abstract of Thesis Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Master of Science
LINEARIZATION THROUGH CARRIER AMPLITUDE MODULATION (LCAM)
CONTROL OF THE BOOST CONVERTER
Alex Geoffrey Phipps
Chair: Khai Ngo
Major Department: Electrical and Computer Engineering
In order to design a robust DC-DC converter, it is essential that the system be
controllable. The pulse width modulated (PWM) DC-DC boost converter presents a non-
linear system with respect to the PWM duty cycle, and standard linear control techniques
cannot be applied.
Typical control methods generate the PWM waveform by comparing a fixed
amplitude carrier to a variable magnitude DC reference. This thesis proposes a control
method of Linearization through Carrier Amplitude Modulation (LCAM). In LCAM
control, the PWM signal is generated by comparing a variable amplitude carrier signal to
a fixed DC reference. When this PWM signal is applied to the boost converter, it is
shown that the output voltage of the converter is directly proportional to the amplitude of
the carrier. The carrier signal is generated by a hysteretic modulator. The amplitude of
the carrier from the hysteretic modulator is equal to a reference input signal, and the
output voltage of the boost converter is therefore directly proportional to the reference.
Using the hysteretic modulator, the output will linearly track the reference signal.
Operation and design of the hysteretic modulator are examined for LCAM control
of the boost converter, and a design metric for the hysteretic modulator is included for
constant frequency operation. Sources of delays and hysteretic limit overshoot are
examined and their effects on operating frequency are included.
Models of the boost converter with LCAM control are given which predict the
linear behavior. For an ideal boost converter, the output voltage is independent of the
output current and input voltage. In a second order system with converter parasitics
included, these other signals can superimpose small operating-point dependant loss terms.
If losses can be minimized, however, the linear terms will dominate. Simulations and
measured data are compared with the models in order to verify linear operation of the
system. Input voltage and output current are varied to verify the second order effects.
For switching DC-DC converters, controllability is essential for robust circuit
design. In a Pulse Width Modulated (PWM) converter topology, the width of a constant-
frequency pulse is modulated in order to control one or more of the converter' s variables.
For a boost converter, the transfer function, Vo,, En as function of the PWM duty ratio,
D, is nonlinear. Standard linear control processes, including voltage feedback and
current-mode control are more effective on linear systems.
The standard Pulse Width Modulated (PWM) DC-DC boost converter can be seen
in Figure 1-1.
1 D +
Vin ~~PWM inputM1CRL Vu
(I~~~j GD1~" R2v~
Duty cycle = D
Figure 1-1: Standard PWM boost converter topology.
A switching network comprising M1 and D1 is used to boost the input voltage, V,,
up to the desired output voltage, Vou, The output voltage that the converter delivers to the
load, RL, iS controlled by a pulse-train signal sent to the gate of M1. Control of the output
voltage is achieved by modulating the duty cycle, D of the pulse-train. Using volt-
second-balance and amp-second-balance , it can be shown that the transfer function
for steady state operation of the boost converter is
V1- D D'
where the compliment duty cycle D' = 1- D
If the duty cycle is the control variable, the transfer function of (1.1) is non-linear
with respect to both D and D'. This non-linearity can be further seen in Figure 1-2, which
plots the relationships established in (1.1).
Boost Transfer Function (Vout/Vin) vs. D and D'
100 -TF vs. D
TF vs. D'
0.00 0.20 0.40 0.60 0.80 1.00
Figure 1-2: Boost transfer function Vout /En vs. D andD'. These functions are highly
Classical linear control techniques cannot be applied to non-linear systems, and
stability of such systems is difficult to achieve. The goal of this work is to present a
method to linearize the dc relationship between the transfer function of the boost and its
control variable. Chapter 2 examines the standard control method used to generate the
PWM signal for linear switching converters and shows why it will not work for the boost
topology. Other complex methods used to control non-linear converters are also
examined. Finally a new control method, Linearization through Carrier Am litude
Modulation (LCAM) is presented for the boost converter. Chapter 3 explores the
operation of a hysteretic modulator, which is the fundamental building block for the
LCAM control system. Chapter 4 presents a detailed design methodology for
implementation of the hysteretic modulator. Chapter 5 verifies LCAM control by
comparing theory, simulations and measured data.
A standard modulation scheme is often used to generate the PWM signal for
switching converters. This method involves comparing a fixed amplitude carrier with a
slowly varying, or dc, modulating signal. Making adjustments to the modulating signal
controls the duty cycle of the PWM signal. An example of standard modulation with a
triangular carrier signal can be seen in Figure 2-1.
v ... ,P W M Sig nal
Figure 2-1: Waveforms used to generate the PWM signal for the standard modulation
Using the similar triangles formed in Figure 2-1 it can be seen that
Vcm D -T,
md= D (2.1)
Since Vpeak is fixed, the duty cycle, D is a linear function of the command voltage, Icnid .
However, from (1.1), the transfer function of the boost is non-linear with respect to the
duty cycle. Therefore, the boost transfer function is non-linear with respect to Vcnid, and
linear feedback schemes cannot be applied control the output.
Non-Standard Modulation Control Methods
For any PWM converter topology, the goal of making a circuit linear is to force it
to behave with the following characteristic:
Yout k cnid (2.2)
Here k is a constant and Vcnid S a controllable command signal. The command signal
varies slowly compared to the converter switching frequency and can be considered to be
quasi-DC in the steady-state. There are two major benefits to achieving the behavior in
(2.2). First, the output of the converter can be linearly controlled using only the
command voltage. Second, in the ideal case, the output signal is independent of all other
input parameters, including ,, This means that changes to the input of the converter will
not greatly impact steady-state performance.
Two common methods to achieve the linear behavior of (2.2) are One-Cycle
Control , and Feed-Forward PWM Control . These are non-linear methods used to
achieve large-signal modulation control of switching converters. For each of these
methods, however, certain drawbacks can arise due to complexity of the circuits.
The schematic for a One-Cycle controlled, constant-frequency switch can be seen
in Figure 2-2. In the One-Cycle scheme, operation of the circuit is initiated by the clock
signal which closes the switch. With the switch closed, y(t) = x(t), and I, ramps up
until it reaches Vcnid in the following manner:
xr(t)dt = Vcni (t) (2.3)
Waveforms from this circuit can be seen in Figure 2-3. The average value of the switch
output, y(t) is found to be
y(t)= Vcni(t) (2.5)
For the boost converter y(t) = Vo,, (t) Substituting this into (2.5) yields the desired linear
relationship between the command voltage and the output.
Yout = cnd (2.6)
Clock ~ +- IV~V, INT!
Figure 2-2: One-Cycle controlled, constant-frequency switch.
.... .. x(t)
....J ..... ...Vcmd
Figure 2-3: Waveforms for one-cycle controlled, constant-frequency switch.
The integrators needed for this circuit must have a reset, and the integration
function can lead to cumbersome control equations. Complicated circuits may also be
required to minimize errors due to delays in the reset process.
Feed Forward Control
The Feed-Forward PWM (FF-PWM) controller used for a boost converter with
leading-edge modulation can be seen in Figure 2-4. As in One-Cycle, the circuit is
initiated by the clock, which resets the integrator. The command voltage, Vcind, iS
integrated to create a ramp, which is compared to the converter input voltage. The PWM
output created by this system can be seen in Figure 2-5.
Vcmd IN UT
Vin/k INT VPWM~
Figure 2-4: Feed-Forward PWM controller for boost converter with leading-edge
Figure 2-5: Operational waveforms for Feed-Forward PWM controller.
It can be shown that for boost converters with PWM signals generated in this
manner, the output voltage is proportional to the command voltage
Vou = k Vcm (2.7)
Like One-Cycle control, integrators with reset are central to FF-PWM control
schemes . The integrators are used to realize complex equations necessary to achieve
linear behavior. Several other elements are needed to achieve FF-PWM including, a
comparator, a mono-stable pulse circuit and a clock signal. Time constants of the
integrators and the clock must be closely matched, or a dependence on the input voltage
The general linearization concept given in (2.2) can be specifically applied to the
boost converter using the boost transfer function given in (1.1). Substituting the value of
Vou, from (2.2) into (1.1), it can be shown that
k cd 1
Solving for D',
D' = (2.9)
This means that if the output voltage of the boost is to behave linearly as in (2.2), the
switching MOSFET, M1, in Figure 1-1 must be driven with a PWM signal having a
compliment duty cycle that obeys the relationship in (2.9).
To achieve a PWM si nal where D' satisfies (2.9) the Linearization thro gh
Carrier Amplitude Modulation (LCAM) control system is used. The LCAM system is
similar to the conventional PWM generator used for standard linear control. Again, a
triangular carrier is compared to the modulating signal in order to generate the PWM
signal. In this new scheme, however, the amplitude of the carrier is modulated also. The
modulating signal, which must not be confused with the amplitude modulated carrier,
should not change much within one carrier period. In order to realize (2.9), the LCAM
system uses configuration in Figure 2-6(a). The peak of the carrier signal is equal
tok Vcmd, and 6, acts as the modulating signal. Using the similar triangles seen in
Figure 2-6(b), it can be seen that
"= D' (2.10)
k V ,
Therefore, the PWM signal generated by the LCAM system is that of (2. 10). This signal
satisfies the requirements of (2.9) and will therefore force the desired linear behavior for
the boost converter specified in (2.2).
It is important to realize that the goals and results of One-Cycle, FF-PWM and
LCAM are the same. Namely, all of these methods force switching converters to behave
linearly as in (2.2). The differences between these concepts arise from their respective
derivations and hardware implementations. LCAM does not propose a new concept of
linearization, but rather a different method by which to implement it.
Figure 2-6: PWM waveforms with LCAM system. (a) Generation of the PWM signals
for the linearized boost converter using the LCAM system. (b) Comparator
inputs and output for a amplitude modulated carrier.
The constant k is used as a scaling factor for Vcmd. Ifk = 1,
Yout md Vc (2. 11)
For boost converters, the desired Vou, may be much larger than any available command
voltage. By using the factor a PWM signal with the desired duty cycle can still be
produced with a lower command voltage. It will be assumed for the remainder of this
paper that Vcmd iS nominal voltage that can be easily obtained. For simplicity the
scaling factor k is assumed to be equal to one.
A block diagram showing the complete LCAM system applied to the boost
converter can be seen in Figure 2-7. The PWM signal is generated by comparing V, to
the amplitude modulated triangular carrier. This triangular carrier is generated by a
hysteretic modulator whose input is the control reference Vcmd The upper hysteretic limit
of the modulator determines the amplitude of the triangle wave and is set to Vcmd The
details of the modulator' s operation are covered thoroughly in Chapter 3.
Figure 2-7: Block diagram of the complete system used to realize LCAM control for the
This chapter examines the operation of a hysteretic modulator, both in its ideal
form and in a physical circuit realization.
Ideal Hysteretic Modulator
The hysteretic modulator is used to create a triangular voltage waveform whose
amplitude can be directly modulated with the quasi-DC command voltage, Vcmd. An ideal
diagram of the hysteretic modulator is shown in Figure 3-1.
Figure 3-1: Ideal hysteretic modulator.
I~ \ / 1 I CMOD
Operation of the modulator begins with the capacitor IOD discharged and the
current source I,, switched off, so it does not conduct. The current source Istw,, draws
current from IOD, Which lowers the voltage, VCOD, Slightly below zero. As this occurs,
comparator COM~P, outputs a logic low and the SR latch is reset. The switch control
logic causes I~~ to switch on. For proper circuit operation it is assumed that I,,) > Ictom .
With this assumption, IOD is now charged up with a constant current,
icA, =IOD up Io,,_ i. The voltage VCMO ramps up at a constant rate as seen in Figure 3-2.
Figure 3-2: The voltage across IOD CIO ramps up and down between the two
hysteretic limits V, and V V+ is set to ,f and V is grounded in this case.
When the magnitude of VCMOD grOws slightly larger than V,2;c, comparaltor COME'~F
outputs a logic low and the SR latch is set. The switch control logic causes I,,, to turn off,
and IOD is discharged by the current sources tow; The constant-current discharge of the
capacitor causes VCMO to ramp back down. As VCMO again falls slightly below zero, the
latch is reset and I,,, is turned back on. The two boundary voltages, I0,,,< and OV, form
the upper and lower hysteretic limits of the modulator. This process of charging and
discharging IOD COntinues, and a triangular waveform seen in Figure 3-2 is produced.
The operating frequency of the hysteretic modulator is determined by the speed at
which the current sources charge and discharge the modulation capacitor COD With the
desired operating frequency known, the relationships between the current sources and
modulation capacitor can be derived to achieve the leading edge, trailing edge and
symmetrically modulated triangular waveforms in Figure 3-3.
Leading Edge (LE)
Trailing Edge (TE)
Figure 3-3: Triangle shapes that can be achieved with a hysteretic modulator.
From basic circuit theory, the relationship between the current and voltage of a
i, = C c C c (3.1)
Using this approximation and the signals from Figure 3-1, (3.1) can be rearranged to
For a given modulator design, CMO is fixed and lAvCO = Vcmd Which is the same
for both charging and discharging events. This is due to the fact that the hysteretic
thresholds are relatively fixed within each switching period as long as the carrier
amplitude varies slowly compared to the switching period. Substituting lAvCMOD = Vicmd
into (3.2), it is seen that
VcmdCMiOD = CMOD Icharging n'se (3.3)
Vcm'dCMOOD =CMOD discharging faull (3.4)
for any of the waveforms in Figure 3-.
Next, equating (3.3) and (3.4) it is shown that
CMrOD Icharging9= ICMIOD Idischargig (3.5)
AsCMO is being discharged, Iup is off, and therefore from Figure 3-1
Idow~n ICMrOD Idischarging (3.6)
Similarly, as CMO is charged up
ICMrOD Icharging= u"p d.own (3.7)
Combining (3.6) and (3 .7)
u~p CMl~OD Icharging CMl-OD Idischarging (3.8)
Finally, substituting (3.5) into (3.8)
IP = (1+ r) ICMrOD dIscharging (3.9)
Iu = (1+ r)Idown (3.10)
The ratios determines which type of waveform from Figure 3-3 is produced. For a
leading edge waveform, where tfazz << t,,s, r will be a small value. Conversely, for a
trailing edge r will be large. In a symmetrical waveform, tf,,, = tns and r will be unity.
The value of the modulation capacitor, CMO needed to achieve a given frequency
is derived from (3.1). Again assuming that AvCMOD = Vcmd ,
CMO CO (3 11)
When CMO is discharging, (3.11) becomes
CMnOD __down (3.12)
For any of the waveforms in Figure 3-3,
T = tns + tfall (3.13)
which can be rearranged into
tfazz =iiK) T ~ +I (3.14)
During the discharge of CMO a fall and (3.12) becomes
MO do" (3.15)
While this derivation was done for a discharging event, the same result is achieved from a
charging event. Any frequency waveform from Figure 3-3 can now be obtained by the
proper choice of Iu Idown, and CMO
Physical Realization of the Hysteretic Modulator
The previous model of the hysteretic modulator provides the means to examine its
operation under ideal conditions. Implementation of the circuit requires the use of non-
ideal parts and physical realization of the hardware needed for logic control. Figure 3-4
shows the schematic of the modulator with non-ideal components that is used to verify
operation in Chapter 5.
Operation of this circuit is similar to the ideal model. A symmetrical triangular
waveform, with ic = 1, is assumed to be used for the circuit of Figure 3-4. As before,
CMO begins discharged, and Iu is initially off. Iu is realized with the trans-conductance
amplifier consisting of Q1 and U1. VCMO is brought down as the current iCMOD doIwn is
drawn from the capacitor, and when VCMO CTOsses the lower hysteretic limit
COM~P2 resets the SR latch. The lower hysteretic limit is can be adjusted by the source
V4~,, toaccount for delays in the comparator and in the switching logic. The reset signal
output from the SR latch is then sent to the switching logic that controls Ip This
switching logic consists of an inverting gate-driver, and a level shifting zener diode. By
controlling the voltage at the top of Iu the current from this source can be switched on
and off. Level shifting of the set and reset signals is necessary to ensure that the active
components of Iu remain in the correct operating modes.
The reset signal from the SR latch is inverted and Iu turns on similar to the ideal
case. From (3.10), to achieve a symmetrical triangle wave, I, = 2Id- The capacitor
voltage, VCMO, iS charged up to the upper hysteretic limit, Vcmd, and COMP1 outputs a
logic low to set the latch. The gate driver inverts the set signal from the SR latch causing
Iu to turn off and CMO to discharge. As in the ideal case, modulation continues as CMO
is charged and discharged, and a symmetrical triangle is produced. The causes and
effects of the various delays associated with non-ideal components are covered in
Vool +Vcmd V
OUTA INA ba
ICL7667 + Vz
SRup -UBI N
V,/2 Vee V
Vee/2 + Vcmd() U2-V, Q2M
e R CLR 1k
Figure 3-4: Physical realization of the hysteretic modulator using non-ideal components.
DESIGN ORIENTED MODELING
This chapter provides a detailed explanation of the non-ideal hysteretic modulator
seen in Figure 4-1. Guidelines for choosing components and component values are also
given. All derivations are made assuming a symmetrical triangle waveform.
Vod2 + VcmdV
ICL7667 + Vz-
U1 Q1 Vd
Vee/2 + Vcmd-2 Q2 C,,o VCMOD
V eet,, R CLR
Figure 4-1: Schematic of the non-ideal hysteretic modulator.
Realizing the Modulation Frequency
Assuming the switching frequency is known, the physical realization of the
hysteretic modulator becomes an iterative process. First, the type of triangle waveform,
leading-edge, trailing edge or symmetrical, must be chosen. For this circuit, a
symmetrical waveform was used and the value of ic = 1. Next, either the value of
CMO Or I,w must be selected. The other value is then calculated using (3.15). It is
possible that this calculated value will exceed some design constraint and values for both
must be redone. For instance, the value of Idown calculated for a chosen capacitance value
may be higher than component tolerances allow. In this case, lower capacitances values
can be iterated until an acceptable I~w is achieved. Iu is always larger than Idown, and
will most likely be unacceptable if I~w is too large.
The relationship between CMO and Idown s WRiven in (3.15) and is repeated here
MnOD icl** (4.1)
Vcmd is the control signal that modulates the amplitude of the carrier, and it is therefore
assumed that Vcmd Will Vary. If Idown is assumed to be fixed, then for changes inVcmd,, the
capacitor CMO must vary in order for frequency to remain the same. Variable
capacitance is difficult to obtain in practice and is not a practical solution. On the other
hand, if CMO is assumed to be fixed, then for constant frequency operation Idown must
vary with Vcmd. Rearranging (4.1) shows a linear relationship between I,w, and Vcmd
iCMOD = 2 fCM~OD~cmd (4.2)
A transconductance, g,, found from (4.2) is defined as
gm __MD = 2 fCMO (4.3)
Selection of CMOD
The choice of CMO must take several factors into account. In order to maintain a
reliable modulation frequency, the capacitance value must be stable over the entire
voltage range of Vcmd and all possible operating temperatures. Since the controller may
be in close physical proximity to the boost converter, there is the possibility of high
temperatures generated by power devices. For integrated designs, CMO Should be as
small as possible, but must remain large enough to overcome parasitic capacitances from
the process. The active devices associated with the current sources can also cause stray
capacitance in parallel with CMOD. Small designs may require small components, which
may put a limit on the capacitance. For non-integrated designs, mica capacitors make a
good choice for temperature and voltage stability.
Design of loown
With a chosen capacitance forCMOD, the relationship between Idown and Vcmd i
(4.3) can be realized using a transconductance current source. A schematic of the source
Idown can be seen in Figure 4-2(a). The current produced by Idown is a function of the
voltage applied across the bias resistor, Rdown To set the transconductance of this source,
the value of Rdw needed is
Combining (4.3) and (4.4), the resistance needed for the current source Idown is
Design of I,,
The current source Iu seen in Figure 4-2(b) is realized with the same circuit
topology as Idown There are two differences between these current sources. From (3.10),
it can be shown that for a symmetrical triangle wave, where ic = 1, that Iu = 2Idown For
a given value of Vcmd the transconductance of Iu must twice as large as that of Idown to
meet this specification. The bias resistor of Iu is then given by
1 1 1
"2 g, 2(2 fCMO) 4 fCMO
The other difference between the two current sources is that I,,, must be able to quickly
switch on and off, while Idow,, remains constant. The voltage across R,,, must therefore
be switched quickly between Pcind in the on state, and zero in the off. It should be noted
that in the off state, the voltage across this resistor does not fall below zero. If the
terminal Ys in Figure 4-2(b) were switched to ground instead of Vc/2, the biasing of the
op-amp and BJT would change. When the current source switches back on, there would
be a recovery time required to re-bias the circuit. During this recovery time there is no
current flowing froml,,p and the triangle wave experiences overshoot and flat-spots.
V cd Ve/2
V,. 1 $Rup
Vcmd + Vee/2 fI
Current Source Idown Current Source lup
Figure 4-2: Current source topology used to generate (a) Iciown and (b) I,, in the hysteretic
Switching Logic and Level Shifting
Control circuitry is needed to realize the switching of the node y, in Figure 4-2(b),
and also to make sure that the op-amp and BJT remained biased in the active region. The
sub-circuit seen in Figure 4-3 is used to achieve the switch signal that drives the current
source I,, The circuit consists of a zener diode, bias resistor and inverter.
SR Latch Voo Vod/2 + Vrer
Vod/2 + Vree
Figure 4-3: Level shifting implementation. Switching circuitry to drive l,, and the
associated input and output waveforms.
The input to the switching logic is a square wave output from the SR latch. This
signal is a standard TTL signal and switches between its power supply voltage and
ground. The switching node of the current source, y is directly controlled by the
inverter, whose power and ground supply rails represent the on and off voltages of I .
By biasing the supply rails in this manner, the inverter' s output will swing between the
two desired levels and prevent the transistors in the current source from leaving the active
region. The zener diode is needed to level shift the TTL latch signal to a level that the
inverter can use as an input. Figure 4-3 shows the result of the level shifting with the
small delay caused by the inverter.
Design of the Level Shifter
Determining the correct amount of DC level shifting is necessary to ensure that the
inverter can input the TTL logic levels from the SR latch. Standard inverters do not
respond properly when the input voltage is less than the value of their ground pin.
Therefore, the zener voltage of the diode, V should be such that it shifts the SR latch
TTL signal by an amount equal to the value of the ground pin on the inverter.
V~ = co(4.7)
By doing this, a logic low from the latch will be at the voltage corresponding to a logic
low on the inverter.
A bias resistor is required to provide current to the cathode end of the zener diode.
Using (4.7), when the input to the zener, I,, is high the voltage across the resistor is
V~al = Ve V -V co V (4.8)
When the input is low
V~, = Ve Vz = co(4.9)
The resistance RI,, must be chosen to provide ample bias current during a high input and
still remain lower than the maximum current during a low input. This means
> I,,, (4.10)
co 2Rb,, max
Here Imm is the minimum current required by the zener diode to function as a voltage
level shifter, and Imax is the largest current that the diode can safely conduct.
Combining and rearranging (4. 10) and (4. 11)
co 2b "' (4.12)
Selection of the Inverter
The inverter must be capable of driving the capacitive load of the current source
I,,, without excessive delay. The amount of delay allowed depends on the modulating
frequency of the circuit. The capacitive load of concern is a combination of the
capacitances from the BJT emitter and the op-amp minus pin.
To drive this capacitive load, an inverting gate driver can be used for the inverter in
Figure 4-3. Gate drivers are designed to quickly charge and discharge the large gates of
power MOSFETs, and many can do so in the MHz frequency range.
Comparators and SR Latch
Several issues arise in the choice of the comparators and SR latch for the hysteretic
modulator. These include the comparator and latch speeds, offset voltage, and supply
voltages needed for the latch and comparator.
Comparator and Latch Speed
Any delay between the signal VCMO and the current source I,, can greatly
influence the operating frequency of the modulator. Figure 4-4 illustrates two
possibilities for the triangular waveform VCMO The solid line represents an ideal system
with no delays, while the dashed line shows a system where delays are present.
Comparator delay and latch delay both cause the operating frequency to decrease because
they slow the propagation of the switching signal to I .
Figure 4-4: VhCMOD for the ideal case without delays (solid) modulates between the two
hysteretic thresholds. Delays cause VhCMOD to overshoot the thresholds
(dashed) and change frequency.
With ideal comparators, when the triangle wave crosses a hysteretic threshold the
output of the comparator should switch. If no other delays are present in the latch and
switching logic, the current source Iu will immediately switch and the triangle wave will
reverse direction. An ideal system such as this experiences no overshoot of the hysteretic
limits. For non-ideal comparators, however, there is a small delay time after the triangle
crosses the hysteretic limit, tc-Alay During this delay time, the signal telling Iu to switch
positions has not yet propagated past the comparator. The same current continues to
charge or dischargeCMOD, and VCMO COntinues past the hysteretic limit. The overshoot
causes the frequency of the triangle to be less than the ideal case.
Similarly, the delay of the SR latch can cause overshoot of the hysteretic limits.
For an ideal comparator, the output switches as the triangle reaches a hysteretic limit.
Delay in the latch, tl-Alay ,causes Iu to remain in the same state, much in the same
manner as comparator delay. The voltage will continue in the same direction, either
charging or discharging Cuoo, and will overshoot.
The delays of the comparator and latch can be added to find the total delay
encountered before the switching logic.
tdelay c-delay+ 1-delay (4.13)
In order to achieve the desired operating frequency, the total delay must be much
less than the operating period,
tdea << T = (4.14)
tdelay <0.01T (4.15)
Selection of the Offset Voltage
Depending on the comparator, there is a chance that there will be some overshoot
of the lower hysteretic limit as seen in Figure 4-5. This is due to the fact that the lower
limit is set to ground, the same as the lower supply voltage. This type of biasing can
cause transistors in the comparator to enter regions of operation that have slower
performance. In this case, an offset voltage, V4fs,,, is used to correct the overshoot. The
lower hysteretic limit is set toVy4f,,, so that even if VMO Overshoots the threshold, the
triangle modulates between Vcmd and zero.
Figure 4-5: Overshoot of the lower hysteretic limit requires the use of VO, .
Choosing V4,ss, is done by assuming that the slope of the voltage waveform is
constant and independent of the hysteretic limit. In a time At the voltage will overshoot
zero, which was the original threshold, by an amount equal to Vovershoot, To remove this
overshoot, the waveform must cross the new hysteretic limit, V4s,,, at a time At before it
crosses zero. For a constant slope, this means that
offset ers,,hoot V,(4.16)
The exact amount of overshoot present may not be known in the design stage and may
need to be empirically determined. It is therefore a good design practice to leave V ,,e
as an adjustable parameter.
This chapter has examined the design of a hysteretic modulator to be used in an
LCAM system. The design procedure is summarized in Table 4-1. Parameters and
components selected for the experimental circuit are included in the table, with brief
comments on why they were chosen. Those that do not have specific design equations
associated with them should be chosen to accommodate the system to which they are
being applied. Acceptable component delays depend upon the chosen frequency of
operation, and the power supply rails are design-specific.
Table 4-1: Design summary for the hysteretic modulator needed to implement LCAM
control on the boost converter.
Design Design Value/ Comments/Selection
Speification Eqation Compoent Criteria
Freqenc Speifiedby converter ~500k
for testing purposes.
Vee User Defined -12V
CMlOD User Defined 68pF, Mica temp/current indepedent
Rdown (4.4) 5.1kohm Idown = ImA,
when Vcmd = Vcmdmax = 5 V
Rup (4.6) 2.4kohm lup 2mA,
when Vcmd = Vcmdmax = 5 V
Zener (4.7) IN473 5 Vz = 6.2V, Imax = 146mA,
Imin = ImA
Rbias (4.12) 620ohm 410hm < 620ohm < 1kohm
COMP1,2 (4.15) LT 1720 tc-delay < 10ns << T = 2000ns
SR Latch (4.15) DM74S00N tl-dela < 10ns << T = 2000ns
Inverter User Defined ICL7667 tdelay < 60ns << T = 2000ns
(for InF load)
OpAmp User Defined LM837A
PNP User Defined 2907
NPN User Defined 2N2222
Voffset (4.16) 0.84V Experimentally determined.
SIMULATION AND VERIFICATION
The purpose of this chapter is to verify the operation of the LCAM system applied
to the boost converter. The first section includes explanations of the circuits and circuit
models used for theoretical calculations, simulations and gathering measured data. The
second section examines the measured results of a working LCAM system, and compares
them to data from the models and simulations.
This section begins with a derivation of the boost transfer function using LCAM
from a simplified circuit model. The circuit used for simulations is presented next.
Finally, a schematic of the system used to gather measured data is shown and
measurement techniques are discussed.
Boost Transfer Function with LCAM
In the steady-state, the output voltage of the ideal boost converter in Figure 1-1 is
given in (1.1). A more physical model with losses included can be seen in Figure 5-1.
D1 ld Rdlode
v,n cL L Vout
Figure 5-1: Boost converter with losses.
The output voltage of the boost with losses  can be approximated by
V = ( -D' )_ r (5.1)
If the output current, lo,,,, is constant, then the load RL in (5.1) can be replaced by
RL out .(5.2)
Substituting equation (5.2) into (5.1) and solving for yo,, yields
Using the LCAM scheme, the compliment duty cycle produced is given by
D' = (5.4)
Combining (5.3) and (5.4), the new relationship between Vo,,, and Ve,,, is found to be
ou cd-Ydod in ycnd cni
The new output voltage can be split into three terms, y ome and two loss terms. The first
loss term is the forward voltage drop of the diode, I cast, which is assumed to be constant
to simplify these calculations. This simplification is justified by the previous assumption
of a constant output current. The second loss term is dependant on the operating point of
the modulator and the losses associated with the converter. The converter losses for this
model can be seen in Table 5-1. If the converter losses are removed, (5.5) reduces to the
ideal LCAM relationship of (2.2).
Table 5-1: Boost converter loss term values.
Loss Term Value
The schematic seen in Figure 5-2 is used in Saber to simulate the operation of the
boost converter with LCAM control. Component values and operating parameters for the
hysteretic modulator are given in Table 5-2. These values and components were chosen
using the design methodology of Chapter 4. The values for the boost converter
components are given in Table 5-3.
Table 5-2: Hysteretic modulator simulation parameters and components.
Component Value / Part #
LATCH ndlch 14
Q1 mmbt2222 sl
Q2 mmbt2907 sl
U1,2 I~m837 sl
Table 5-3: Boost converter values used in simulation.
Experimental data are gathered from an LCAM system whose schematic is seen in
Figure 5-3. The bill of materials at the end of the chapter lists all of the components and
component values used to construct this circuit. In order to make the measurements
more uniform, the boost converter was loaded with a constant-current active load.
gn gdgnd gnd L idRd de
I gnd gnd
Figure 5-2: Saber schematic used for circuit simulations.
Waveforms were measured with the Tektronix TDS460A 4-channel oscilloscope. The
value of Iou, was verified with a Tektronix TM502A current probe. The bias and offset
voltage used to implement the design in Figure 5-3 can be found in Table 5-4.
Table 5-4: Bias and offset voltages
Desin Spcfction Value/Component
Vee/2 + Vcmd (^):se 2~R
v~n CL RLotut
Figure 5-3: Boost converter and LCAM system used to measured data.
Figure 5-4 shows several of the key operational waveforms taken from the boost
converter with the LCAM system. The triangular carrier, VCMO, ramps between the two
hysteretic limits. These limits are set to zero and Vcnd Which is 5V in this case. The
square wave is the PWM signal output from COMP3 that drives M1. The output
voltage, Vo,,,, is a DC signal with some switching noise. The average value of Vo,,, is
approximately 5V, the same as ynd *
Tek Run: 100MS/s Sample
2+[ ,P ,;--- ,' PSignal
Ch 5.00 V Ch2 5.00 V M 500ns Chl I 2.5 V 30 Aug 2005
[ [H 5.00 V 12:16:13
Figure 5-4: Measured waveforms.
Figure 5-5 demonstrates the linearity of the output voltage under LCAM control.
The input voltage, V,, and output current, los,, were kept constant while the reference
voltage, Vcmd WaS swept. The close agreement between the calculated, simulated and
experimental data suggests that the models of the LCAM system are accurate.
The ultimate goal of the LCAM system is to force the steady-state output voltage of
the boost converter to be a linear function of only the command voltage. This ideal
behavior can be accomplished in a lossless converter. However, as (5.5) suggests, the
effects of the input voltage and output current cannot be ignored.
Vout vs. Vcmd
lout = 1A, Vin =3V
5.00 -/ + Measured
3.0 3.2 3.4 3.6
3.8 4.0 4.2 4.4 4.6 4.8 5.0
Figure 5-5: Vo,, vs. VcmCUT~e with calculated, simulated and measured data.
In Figure 5-6, the measured Vou, vs. Vcmd is plotted for a family of Iou, values. The
value of V, is held constant at a nominal value. As suggested by (5.5), high los, values
increase the losses produced by the operating-point dependant term and lead to smaller
Vout vs. Vcmd with varying lout
Vin = 3V
3 3.2 3.4 3.6 3.8 4 4.2
4.4 4.6 4.8 5
Figure 5-6: A family of Vou vs. V cmd v CUTVC OTSeVeral values of lo
Figure 5-7 shows the effect that different values have on Vu For each different
value ofn lou, is held constant while Vcmd is swept. According (5.5) as ~,gets larger
the second loss term is reduced and Vou, is higher for a specific value of Vcmd
Vout vs. Vcmd with varying Vin
4.50 -m-3.0V -
S' 4.00 -A- 3.3V
3.0 3.2 3.4 3.6
3.8 4.0 4.2
4.4 4.6 4.8 5.0
Figure 5-7: A family of Vo,,,uy, vs. Vcm CUTVC OTSeVeral values of ~n.
It should be noted that while and los, offset the Vou, vs. V cmCUTVCS in Figure 5-6
and Figure 5-7, the linear relationship between the command and the output is preserved.
Table 5-5: Bill of materials
Item Quantity Reference Part Footprnt Vendor Vendor Part #
1 1 L 4.6uH Axial Wilco LFB47G
2 1 CL 20.1luF Radial OSCON 20SP22M
3 1 M1 NMOS SO-8 Fairchild FDS6670
4 1 GDI Gate Driver 8PDIP Texas Instruments UCC27324
5 1 D1 Diode TO- International Rectifier 40L15CT
6 1 RL Active Load N/A acdc electronics EL-300
7 3 COMP1, Comparator SO-8 Linear Technology LT1720
8 1 ChK)D 68pF Radial Various Various
9 1 Rdown 5.1IkOhm Axial Various Various
10 1 R 2.4kOhm Axial Various Various
11 1 Dz 6V Zener Diode Axial Axial 1N4735
12 1 Rblas 6200hm Axial Various Various
13 1 U2 NAND Gate 14PDIP Fairchild Semiconductor DM74S00N
14 1 U3 Inverter 8PDIP MAXIM ICL7667
15 2 U1 Op-Amp 14PDIP National Semiconductor LM837N
16 1 Q1 PNP TO-92 Fairchild Semiconductor PN2907A
17 1 Q, NPN TO-92 Fairchild Semiconductor PN2222A
LIST OF REFERENCES
 R.W. Erickson, Fundamentals of Power Electronics. Norwell, MA: Kluwer
Academic Publishers, 2001.
 K. Smedley and S. Cuk, "One-cycle control of switching converters." PESC '91
Record. 22nd Annual IEEE Power Electronics Specialists Conference (Cat.
No.91CH3008-0). Cambridge, MA, USA, 24-27 June 1991. p. 888-896. See also
IEEE Transactions on Power Electronics, Nov. 1995 and US Patent 5,278,490
 B. Arbetter and D. Maksimovic, "Feed-forward pulse-width modulators for
switching power converters." PESC '95 Record. 26th Annual Power Electronics
Specialists Conference. Atlanta, GA, USA, 18-22 June 1995. p.601-607.
Alex Phipps obtained his BS degree in Electrical Engineering from the University
of Florida in 2004. He has been a research assistant for the Department of Electrical
Engineering at UF since 2005 and is currently a Masters candidate. His field of interest
is the design of electronic circuits for power management.