<%BANNER%>

Low-Power Software Configurable Modulator for Wireless Communications

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Iwouldliketoexpressmysinceregratitudetomysupervisorycommitteechair,Dr.JenshanLin,whoprovidedthefree,creativeandfriendlyatmosphereneededforaninvaluableresearchexperience.Withouthisknowledge,experience,vision,andencouragingattitude,thisworkwouldbeimpossible.Ialsosincerelyappreciatethetimeandeortgivenbythemembersofmysupervisorycommittee(Dr.RizwanBashirullah,Dr.LiuqingYang,andDr.FanRen).Ithankthemfortheirinterestinmyworkandservingonmysupervisorycommittee.Iamalsothankfultomycolleagues(Tien-YuChang,LanceCovert,JerryJun,JaeseokKim,JaeShinKim,SangWonKo,ChangzhiLi,AshokVerma,YanmingXiao,andHyeopgooYeo)intheRadioFrequencySystemOnChip(RFSOC)Group,forallthehelptheyoered.MythanksalsogotomyothercolleaguesintheDepartmentofElectricalandComputerEngineering,especiallyeveryoneintheelectronicsarea,fortheirindispensableroleinmystudyandresearch.Idedicatethisworkandmydeepestlovetomyparentswhohavegivenmetheutmosttrustandsupporttoexploremylife.Lastbutnotleast,IthankDongmingXuforbeingmybestfriend. iv

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page ACKNOWLEDGMENTS ............................. iv LISTOFTABLES ................................. vii LISTOFFIGURES ................................ viii ABSTRACT .................................... xiv CHAPTER 1INTRODUCTION .............................. 1 1.1SoftwareDenedRadio ......................... 1 1.2DigitalModulationSchemes ...................... 3 1.2.1BinaryPhaseShiftKeying ................... 4 1.2.2QuadraturePhaseShiftKeying ................ 5 1.2.3OsetQuadraturePhaseShiftKeying ............. 7 1.2.4MinimumShiftKeying ..................... 8 1.2.5GaussianMinimumShiftKeying ................ 9 1.2.6AmplitudeModulation ..................... 10 1.3OverviewofDissertation ........................ 12 2SOFTWARECONFIGURABLEMODULATOR ............. 14 2.1ConventionalI/QModulators ..................... 14 2.2ProposedSoftwareCongurableModulator .............. 16 2.3ComparisonbetweenConventionalandProposedModulators .... 20 3DESIGNOFATESTMODULATORFORFIXEDPATTERNEDDATA 22 3.1ConstantEnvelopeModulation .................... 22 3.1.1PhaseChangePatternforMSKmodulation ......... 23 3.1.2PhaseChangePatternforGMSKModulation ........ 24 3.1.3DesignedConstantEnvelopePhaseShiftTestModulator .. 28 3.2DesignIssuesAssociatedWiththeConstantEnvelopePhaseShiftModulator ................................ 29 3.2.1TheoreticalPowerSpectralDensitywithrespecttotheNumberofPhaseShiftsperBitPeriod ............ 29 3.2.2ImpactofVariationsintheModulatedSignal'sAmplitudeandPhaseShiftStep ...................... 31 v

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........................... 34 3.3.1Divider .............................. 35 3.3.2Multiplexers ........................... 37 3.3.3PhasorCombiningCircuit ................... 39 3.3.4Buers .............................. 40 3.3.5DigitalCircuitSection ..................... 41 3.4ExperimentalResults .......................... 42 3.4.1ModulatorICFabricatedin0.18mCMOSProcess ..... 42 3.4.2ModulatorICFabricatedin0.13mCMOSProcess ..... 50 3.4.3PerformanceComparison .................... 54 4ADIGITALLYCONTROLLEDPHASESHIFTMODULATORFORARBITRARYDATAPATTERNS ..................... 57 4.1DesignDetails .............................. 57 4.2ExperimentalResults .......................... 61 5DESIGNOFADIRECTCONVERSIONTRANSMITTER ....... 73 5.1DirectConversionTransmitters .................... 73 5.2DesignofanInductor-Capacitor-BasedVoltageControlledOscillator 75 5.2.1SmallSignalModelofaCMOSVCO ............. 77 5.2.2NoiseIssueConsiderations ................... 79 5.3DesignofaPowerAmplier ...................... 82 5.3.1BasicCharactericsofaPowerAmplier ............ 82 5.3.2ClassesofPowerAmpliers ................... 84 5.3.3DesignofaNonlinearPowerAmplierfortheOutputoftheConstantEnvelopeModulatorCircuit ............. 88 5.4ExperimentalResultoftheDirectConversionTransmitterCircuit 92 5.5DirectConversionTransmitterusingaQuadratureVoltageControlledOscillator ................................ 100 5.5.1DesignofaQuadratureVoltageControlledOscillator .... 101 5.5.2ExperimentalResultoftheTransmitterCircuitusingQVCO 106 6DESIGNOFAnOQPSKMODULATOR ................. 110 6.1DesignoftheModulatorCircuitBoard ................ 110 6.2ExperimentalResults .......................... 117 7SUMMARYANDFUTUREWORK .................... 126 7.1Summary ................................ 126 7.2FutureWork ............................... 130 REFERENCES ................................... 134 BIOGRAPHICALSKETCH ............................ 138 vi

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Table page 3{1SummaryofthephasechangepatternofGMSKmodulation ....... 28 3{2Summingweightsforgeneratingdierentphasors ............. 34 3{3Summaryofmodulatorperformance(0.18mchip) ............ 50 3{4Summaryofmodulatorperformance(0.13mchip) ............ 54 3{5Comparisonofmodulatorperformance ................... 56 4{1Performancesummaryofthemodulatorforarbitrarydatapatterns ... 72 5{1Performancesummaryofthedirectconversiontransmitter ........ 100 5{2PerformancesummaryofthedirectconversiontransmitterusingaQVCO 107 vii

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Figure page 1{1TheQPSKmodulation.Theinputbitstreamisseparatedintotwostreamscontainingoddandevenbits. ................... 5 1{2AQPSKsignalwaveform .......................... 7 1{3OQPSKisobtainedfromQPSKbydelayingtheoddbitstreambyhalfabitintervalwithrespecttotheevenbitstream .............. 8 1{4AnOQPSKsignalwaveform ......................... 8 1{5PowerSpectralDensityofanMSKsignalascomparedtoaQPSKorOQPSKsignal ................................ 9 1{6ConstellationofaGMSKsignal.AnMSKsignalhasasimilarconstellationinthattheamplitude(envelope)doesnotvary. .............. 10 1{7PowerSpectralDensityofaGMSKsignalatdierentBTproduct .... 11 1{8Constellationofa16-QAMsignal ...................... 12 2{1BlockdiagramofagenericI/Qmodulator ................. 15 2{2Phasordiagramofamodulatedsignal ................... 17 2{3Howaphasorcanbegeneratedfromtwophasorsinquadrature ..... 18 2{4Conceptualschematicofasummingcircuit ................. 19 3{1AnMSKmodulationexampleandthemodulatedsignal'sconstellation(a)MSKmodulationisI-Qmodulationwithhalfsinusoidalpulseshaping(b)Themodulatedsignalpresentsaconstantenvelopeconstellation ... 23 3{2ADSsimulationforGSM ........................... 24 3{3ADSsimulatedGMSKwaveform(a)I-channel(b)Q-channel ....... 26 3{4ADSsimulationforGMSKspectrum .................... 27 3{5MATLABsimulationoftheconstellationofaGMSKsignal ....... 27 3{6BoundarypointsforonebitintervalonaGMSKconstellation ...... 28 viii

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30 3{8Idealconstellationofthemodulatoroutput ................. 31 3{9Normalizedsidelobelevel(referencedtomainlobelevel)versusvariationsinamplitudeandphaseshift(TheX-axishasaunitofradiansforphaseshiftvariation,anditindicatespercentageforamplitudevariation .... 33 3{10Howfourdiscretephasorswithinaquadrantcanbegeneratedfromtwophasorsinquadrature ............................ 34 3{11Constantenvelopephaseshiftmodulator .................. 35 3{12A2:1staticfrequencydivider(a)Blockdiagram(b)Adetaileddividerschematic ................................... 36 3{13A2:1dierentialcurrent-steeringmultiplexer ............... 38 3{14Phasorcombiningcircuit ........................... 39 3{15Schematicofthebuer ............................ 41 3{16Flip-oplatch ................................. 42 3{17DiemicrophotographofthemodulatorIC(0.18mchip) ......... 43 3{18Simulatedoutputpowerspectrumforthexedrepetitivedatapattern 45 3{19Measuredoutputpowerspectrum.Signals'sfrequencyis25MHz,oronefourthofthe100MHzbitrate,lowerthanthe2.5GHzcarrierfrequency. 45 3{20Measuredconstellation(0.18mchip)ofthemodulatedsignal(EVM=2.8%).Thesignalmovedsequentiallyandrepetitivelyinfullcircles ... 46 3{21MeasuredI/Qplanediagram(0.18mchip)ofthemodulatedsignal .. 46 3{22MeasuredEVMvs.carrierfrequency(0.18mchip).At100Mbpsbitrate,forEVMslowerthan5.5%,themodulatorcanoperateatacarrierfrequencybetween1.75GHzand3.5GHz ................. 47 3{23MeasuredEVMvs.bitrate(0.18mchip).At2.5GHzcarrierfrequency,forEVMslowerthan5%,thebitrateofthemodulatorrangesfromDCto500Mbps .................................. 48 3{24Constellation(EVM=6%)atbitrategreaterthan500Mbps(0.18mchip) ...................................... 49 3{25Whentheerrorvectorisperpendiculartotheidealphasor,thephasevariationisthebiggest ............................ 49 ix

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...................... 50 3{27Completemodulatortestchipcircuit(0.13mchip) ........... 51 3{28DiemicrophotographofthemodulatorIC(0.13mchip) ......... 52 3{29Measuredconstellation(0.13mchip)ofthemodulatedsignal(EVM=3.5%) ..................................... 53 3{30MeasuredI/Qplanediagram(0.13mchip)ofthemodulatedsignal .. 54 3{31MeasuredEVMvs.carrierfrequency(0.13mchip).At100Mbpsbitrate,forEVMslowerthan4%,themodulatorcanoperateatacarrierfrequencybetween1.5GHzand3.3GHz .................. 55 3{32MeasuredEVMvs.bitrate(0.13mchip).At2.5GHzcarrierfrequency,forEVMslowerthan5.5%,thebitrateofthemodulatorrangesfromDCto225Mbps .................................. 55 4{1Movementofthephasorwhenserialdatastream10110010isMSKmodulated ................................... 59 4{2Boundaryphasesontheconstellationforthe8bitintervals ........ 59 4{3HowastatestreamcanbegeneratedattheoutputofaMUX ...... 60 4{4Modulatorcircuitforarbitrarydatapatterns ................ 62 4{5IdealnormalizedoutputPSDforthemodiedmodulatorifpseudorandominputdataareapplied ............................ 62 4{6Idealconstellationforthemodiedmodulatorifpseudorandominputdataareapplied ................................ 63 4{7Diemicrophotographofthemodulatorcircuitforarbitrarydatapatterns 63 4{8Measurementsetupfortestingthemodulatorcircuitwithpesudorandominputdatabits ................................ 64 4{9Measuredconstellationat2.5GHzcarrierfrequencyand12Mbpsbitrate 65 4{10MeasuredI/Qdiagramat2.5GHzcarrierfrequencyand12Mbpsbitrate 66 4{11Measuredpowerspectrumat2.5GHzcarrierfrequencyand12Mbpsbitrate ...................................... 67 4{12Measuredpowerspectrumwithasmallerfrequencyspanat2.5GHzcarrierfrequencyand12Mbpsbitrate ................... 68 x

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................................ 68 4{14Measuredpowerspectrumat2.5GHzcarrierfrequencyand50Mbpsbitrate ...................................... 69 4{15Measuredpowerspectrumat2.5GHzcarrierfrequencyand100Mbpsbitrate ...................................... 69 4{16IEEE802.15.4andZigBeeworkingmodel ................. 70 4{17OutputspectrumoftheCC2420transmitter ................ 71 5{1GenericdirectconversiontransmitterutilizingtheconventionalI/Qmodulator ................................... 74 5{2Designeddirectconversiontransmittertobedesignedutilizingtheconstantenvelopephasemodulator ..................... 76 5{3DesignedCMOSLC-VCO .......................... 77 5{4EquivalentcircuitmodelofthedesignedCMOSLC-VCO ......... 78 5{5Symmetricspiralinductormodel ...................... 79 5{6LayoutoftheLC-VCOcircuit ........................ 81 5{7SimulatedresultoftheoutputofVCOplusdivider ............ 83 5{8Voltage-currentrelationshipsforvariousclassesofPA ........... 85 5{9Topologyofasingle-endedpoweramplier(classA,B,andC) ...... 88 5{10BuerstodrivethePA.(a)Buerfortherstthreestages(b)Buerforthelaststage ................................. 89 5{11LayoutofthePAanditsproceedingbuer/driver ............. 90 5{12SimulateddierentialoutputwaveformfromthePA ............ 91 5{13Diemicrophotographofthedirectconversiontransmittercircuit ..... 93 5{14Measurementsetupfortestingthetransmittercircuit ........... 94 5{15ObservedoutputsignalsthroughsubstratecouplingfromtheLC-VCOat5GHzandthedividerofthemodulatorat2.5GHz ............ 95 5{16Measuredpowerspectrumofthetransmittercircuitat2.5GHzcarrierfrequencyand12Mbpsbitrate ....................... 96 5{17Measuredpowerspectrumofthetransmittercircuitat2.5GHzcarrierfrequencyand25Mbpsbitrate ....................... 97 xi

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...................... 97 5{19Measuredpowerspectrumofthetransmittercircuitat2.5GHzcarrierfrequencyand50Mbpsbitrate ....................... 98 5{20Measuredpowerspectrumofthetransmittercircuitat2.5GHzcarrierfrequencyand100Mbpsbitrate ...................... 98 5{21OutputRFpowerlevelofthetransmittercircuitvs.carrierfrequency .. 99 5{22Directconversiontransmittertobedesigned ................ 101 5{23QuadratureVCO ............................... 102 5{24DesignedLC-QVCO ............................. 102 5{25LayoutoftheLC-QVCO ........................... 103 5{26SimulatedresultofthequadratureLOsignalsgeneratedbytheQVCO 105 5{27BlockdiagramofthedirectconversiontransmitterutilizinganLC-QVCO 105 5{28Diemicrophotographofthedirectconversiontransmittercircuit ..... 106 5{29MeasuredpowerspectrumofthetransmittercircuitusingaQVCOat2.56GHzcarrierfrequencyand12Mbpsbitrate ............. 108 5{30MeasuredpowerspectrumofthetransmittercircuitusingaQVCOat2.56GHzcarrierfrequencyand25Mbpsbitrate ............. 108 5{31MeasuredpowerspectrumofthetransmittercircuitusingaQVCOat2.56GHzcarrierfrequencyand37.5Mbpsbitrate ............ 109 6{1Phasorcombiningapproach ......................... 111 6{2ImplementationofsoftwarecontrolforMSKmodulation ......... 112 6{3ConstellationofanOQPSKsignal ..................... 112 6{4IllustrationofhowthecorrectquadrantscanbeselectedbythemultiplexersforOQPSK .................................. 113 6{5Modulatorcorecircuit ............................ 114 6{6Diemicrophotographofthemodulatorcorecircuit ............ 115 6{7UsingLinecalctocalculatethewidthofmicrostriptransmissionlineonanFR4board ................................. 116 6{8LayoutoftheprintedcircuitboarddesignedinProtel ........... 117 xii

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.................. 118 6{10PhotoofthebondedchiponthePCboard ................. 118 6{11PhotoofthecompletedPCboard ...................... 118 6{12Measurementsetupfortestingthemodulatorboard ............ 119 6{13Schematicoftheboard-levelcurrentsource ................. 119 6{14PhotoofthecurrentsourcetestboardforOQPSKmodulation ...... 119 6{15TheoreticalpowerspectrumofOQPSK .................. 121 6{16Consistentmeasurementresultwiththeoreticalspectrum ......... 121 6{17Measuredoutputspectrumat0.5GHzcarrierfrequencyand24Mbpsdatarate .................................... 122 6{18Measuredoutputspectrumat3GHzcarrierfrequencyand24Mbpsdatarate ...................................... 122 6{19Measuredoutputspectrumat3.7GHzcarrierfrequencyand24Mbpsdatarate .................................... 123 6{20Measuredoutputspectrumat2.4GHzcarrierfrequencyand40Mbpsdatarate .................................... 123 6{21Measuredoutputspectrumat2.4GHzcarrierfrequencyand80Mbpsdatarate .................................... 123 6{22Measuredoutputspectrumat2.4GHzcarrierfrequencyand100Mbpsdatarate .................................... 124 6{23Comparisonofthepowerspectrafordierentnumberofphasorsperquadrant .................................... 124 7{1SimpliedNodeRFsubsystemblockdiagram .............. 129 7{2Measuredoutputpowerspectrum(100Mbpsdatarate)andconstellation(12Mbpsdatarate)around24GHz .................... 129 7{3HowthecorrectvaluesofI1andI2canbeprovidedforaphasor ..... 132 7{4DiephotoofthemodulatorcorecircuitusingUMC90nmtechnology .. 133 xiii

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Weexaminedasoftwarecongurablemodulatorwiththepotentialtogeneratedierentmodulationschemes.Themodulatorusesa\digital"approachunlikethe\mixing"or\multiplying"approachusedbyconventionalanalogmodulators.Thedigitalapproachusesthephasorcombiningtechniquetogeneratethemodulatedsignalconstellation.Thephasorcombingmethodisessentiallytoweighandsumuptwophasors,ortwoLOsignalswithdierentphases(e.g,inquadrature)togenerateadesiredphasorthatrepresentsthemodulatedsignalontheconstellation. Wedesignedandtested2testmodulatorcircuitsrealizinganMSK-likemodulationschemebasedonthedesignapproach:onewithaxeddatapatternandtheotherforarbitrarydatapatterns.Experimentalresultsshowedthat,comparedtoaconventionalmodulatorwithsimilarfunctions,theproposedmodulatorhastheadvantagesoflowpowerconsumption(3.6mWexcludingoutputbuers),highdatarate(upto100Mbps),broadoperatingfrequency xiv

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Wealsopresentthedesignandexperimentalresultsofadirectconversiontransmitterthatusesthemodulator.Thetransmitterconsistsofavoltagecontrolledoscillator(VCO),themodulatorcircuitforarbitrarybitpatterns,andapoweramplier(PA).Thepowerconsumptionofthewholetransmitteris129mW,andtheoutputpowerlevelis3dBm.ThetransmittercanbeusedforaZigBee-readypersonalareanetwork,orothersimilarwirelessnetworks.Ithastheadvantagesofhigherdatarateandlowererrorvectormagnitude(EVM)thanthenormalspecicationsforsuchnetworks. Wealsodesignedandbuiltaboard-levelmodulatoracoremodulatorchipwiththesamearchitectureastheintegratedmodulatorcircuit.Controlsignalsandbiascurrentscanbeappliedo-chipbyon-boardcircuitcomponents.Theboardwastestedforosetquadraturephaseshiftkeying(OQPSK)modulation,andtheminimumshiftkeying(MSK)functioncanbedevelopedbyproperlydesignedon-boardcircuitry. ThephasorcombiningapproachcanpotentiallyallowamodulatortogeneratedierentmodulationschemessuchasQPSK,MSK,andevenquadratureamplitudemodulation(QAM).Thesemodulationschemesarewidelyusedintoday'swirelesscommunications.Therefore,theproposedmodulatormaybewellsuitedforasoftwaredenedradio. xv

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1 ].Thismakesitpossiblefortheradiotoprovidemoreservicesbysharingresourceswithneighboringdevicesandnetworks.amultimodehandsethasthepotentialformoreservicesandglobalroamingcapability. Softwaredenedradio(SDR)forum[www.sdrforum.org]denesSDRtechnologyas\radiosthatprovidesoftwarecontrolofavarietyofmodulationtechniques,wide-bandornarrow-bandoperation,communicationssecurityfunctions(suchashopping),andwaveformrequirementsofcurrentsandevolvingstandardsoverabroadfrequencyrange."Alsoknownassoftwareradio(SR),itcanbeseenaswirelesscommunicationinwhichthetransmittermodulationisgeneratedordenedbyacomputer,andthereceiverusesacomputertorecoverthesignal.SDRisarapidlyevolvingtechnologygeneratingmoreandmoreinterestinthetelecommunicationindustry.Manyanalogradiosystemsarebeingreplacedbydigitalradiosystemsforvariousradioapplications.Programmable 1

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hardwaremodulesareincreasinglybeingusedindigitalradiosystemsatdierentfunctionallevels.SDRtechnologyfacilitatesimplementationofsomeofthefunctionalmodulesinaradiosystemsuchasmodulation/demodulation,signalgeneration,coding,andlink-layerprotocolsinsoftware.Thishelpsinbuildingrecongurablesoftwareradiosystemswheredynamicselectionofparametersforeachofthemodulesispossible[ 2 ].Therefore,SDRtechnologygreatlybroadenstheapplicationprospectsofasystembyallowingthesamesystemtobecompatibleforapplicationsthatusedierentlink-layerprotocolsand/ormodulation/demodulationtechniques. SDRtechnologyaimstoimplementradiofunctionalityassoftwaremodulesrunningonagenerichardwareplatform.Multiplesoftwaremodulesimplementingdierentstandardscanbepresentintheradiosystem.Inotherwords,SDRisacollectionofhardwareandsoftwaretechnologiesthatenablerecongurablesystemarchitecturesforwirelessnetworksanduserterminals.Therefore,radiosbuiltusingSDRtechnologycanallow

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Todate,softwareradiobasestationshavebeenmorepopularandgottenmoreattentionthanhandsets,becausebasestationshavemuchmorerelaxedrequirementsforspecicationslikepowerandsiliconarea.However,softwareradiodesignsaremigratingtosmallhandsetsthatsupportmultimoderadios,althoughthetaskremainschallengingduetothemanyconstraints. ThemodulatorisakeycomponentforsoftwarecongurabilityofanSDR.Therefore,itisnecessarytolookatsomeofthebasicdigitalmodulationtechniquesforwirelesscommunications. Whatisdigitalmodulation?Totransportdatainadigitalcommunicationsystem,typicallyoneormorephysicalcharacteristicsofasinusoidalcarrier(such

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asfrequency,phase,oramplitude)isadjusted.Amodulatoratthetransmitterendimposesthephysicalchangeonthecarrier. Thechoiceofdigitalmodulationschemewillsignicantlyaectthecharacteristics,performance,andresultingphysicalrealizationofacommunicationsystem.Dependingonthephysicalcharacteristicsofthechannelandrequiredlevelsofperformance,somemodulationschemeswillhaveadvantagesoverothers.Otherfactorsthatcanaectthechoiceincluderequireddatarate,availablebandwidth,anticipatedlinkbudget,hardwarecostandcurrentconsumption.Nowletuslookatsomecommonlyuseddigitalmodulationschemesinvariouswirelesscommunicationsstandards. ForM-aryphaseshiftkeying(PSK),Mdierentphasesarerequired,andeveryn(whereM=2n)bitsofthebinarybitstreamarecodedasonesignalthatistransmittedasAcos(!t+j),wherej=1;:::;M.Whenimprovedspectraleciencyisrequired,higher-ordermodulationschemes,suchasquadraturephaseshiftkeying(QPSK),areoftenusedinpreferencetoBPSK.

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Figure1{1. TheQPSKmodulation.Theinputbitstreamisseparatedintotwostreamscontainingoddandevenbits. 1{1 showsthat,theinputbinarybitstream,dkwherek=0;1;2;:::,arrivesatthemodulatorinputatarate1=Tbits/secandisseparatedintotwodatastreamsdI(t)anddQ(t)containingoddandevenbitsrespectively,i.e.,

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AconvenientorthogonalrealizationofaQPSKwaveform,s(t),isachievedbyamplitudemodulatingthein-phaseandquadraturedatastreamsontothecosineandsinefunctionsofacarrierwaveas Usingtrigonometricidentitiesthiscanalsobewrittenas ThepulsestreamdI(t)modulatesthecosinefunctionwithanamplitudeof1.Thisisequivalenttoshiftingthephaseofthecosinefunctionby0or.ConsequentlythisproducesaBPSKwaveform.SimilarlythepulsestreamdQ(t)modulatesthesinefunction,yieldingaBPSKwaveformorthogonaltothecosinefunction.ThesummationofthesetwoorthogonalwaveformsistheQPSKwaveform.Thevaluesof(t)(0; InQPSK,thecarrierphasecanchangeonlyonceevery2Tseconds.IffromoneTintervaltothenextone,neitherbitstreamchangessign,thecarrierphaseremainsunchanged.IfonecomponentdI(t)ordQ(t)changessign,aphasechange

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Figure1{2. AQPSKsignalwaveform of90occurs.However,ifbothcomponentschangesign,thenaphaseshiftofoccurs(Figure 1{2 ).Infact,the180shiftinphasewillcausetheenvelopetogotozeromomentarily.Thepotentialfora180phaseshiftinQPSKresultsinmorelikelyspectralregrowthandrequiresbetterlinearityinthepoweramplier. 2bitinterval(Figure 1{3 ),thentheamplitudeuctuationsareminimizedsincethephaseneverchangesby180.Thismodulationscheme,osetquadraturephaseshiftkeying(OQPSK),isobtainedfromQPSKbydelayingtheoddbitstreambyhalfabitintervalwithrespecttotheevenbitstream.Figure 1{4 showsthat,therangeofphasetransitionsis0and90(thepossibilityofaphaseshiftof180iseliminated)andoccurstwiceasoften,butwithhalftheintensityoftheQPSK.Thephaseofthecarrierispotentiallymodulatedeverybit,noteveryotherbitasforQPSK.Hence,thephasetrajectoryneverapproachestheorigin.Whileamplitudeuctuationsmaystilloccurinthetransmitterandreceiver,theyhavesmallermagnitude.ThebiterrorrateforQPSKandOQPSKisthesameasforBPSK.

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Figure1{3. OQPSKisobtainedfromQPSKbydelayingtheoddbitstreambyhalfabitintervalwithrespecttotheevenbitstream Figure1{4. AnOQPSKsignalwaveform Itshouldbenotedthat,althoughOQPSKisobtainedfromQPSKbydelayingdQ(t)by1bitorTsecondswithrespecttodI(t),thisdelayhasnoeectonthebiterrorrateorbandwidth.Infact,becauseofthesimilaritiesbetweenQPSKandOQPSK,similarsignalspectraandbiterrorrateareachieved.OQPSKisusedintheNorthAmericaIS-95CDMAcellularsystemforthelinkfromthemobiletothebasestation.

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Figure1{5. PowerSpectralDensityofanMSKsignalascomparedtoaQPSKorOQPSKsignal providestherequiredlinearadvancementorrecedingofphasethatmakesMSKacontinuousphasemodulation.TheMSKmodulationmakesthephasechangelinearandlimitedto 1{5 [ 3 ]showsthePSDcomparisonbetweenMSKandQPSK/OQPSK.

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(GMSK).Therefore,GMSKisasimplebinarymodulationschemewhichmaybeviewedasaderivativeofMSK.Bothmodulationschemesareconstant-envelopmodulationsascanbeseenfromFigure 1{6 .Butinpractice,GMSKismoreattractiveforitsexcellentbandwidtheciency,althoughintersymbolinterference(ISI)isintroducedbecauseaGaussianpulseextendsintoadjacentbits.Therelationshipbetweenthepremodulationlterbandwidth,B,andthebitperiod,T,ortheproductofthetwo,determinesthebandwidthoftheGMSKsignal,whichisshowninFigure 1{7 [ 4 ]. Figure1{6. ConstellationofaGMSKsignal.AnMSKsignalhasasimilarconstellationinthattheamplitude(envelope)doesnotvary. BothMSKandGMSKhaveconstantamplitudewaveforms,whichallowsthepowerampliertobeoperatedfurtherintosaturationyieldingimprovedeciencyandincreasedoutputpower,withoutsignicantspectralre-growth.AsavariationofMSK,GMSKprovidesbetterspectralroll-oinexchangeforerrorrate.Theimprovedroll-oistocomplywithdemandingwirelessstandardsforadjacentchannelinterference. 5 ].

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Figure1{7. PowerSpectralDensityofaGMSKsignalatdierentBTproduct However,amplitudemodulationsarealsoaveryimportantclassofmodulationschemeandstillndtheirmanyapplicationsinwirelesscommunications.Oneofthemostcommonlyusedamplitudemodulationsisquadratureamplitudemodulation(QAM). QAMactuallyisamethodofcombiningtwoamplitude-modulatedsignalsintoasinglechannel,therebydoublingtheeectivebandwidth.Essentially,itisacombinationofamplitudemodulationandphaseshiftkeying.InQAM,data

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Figure1{8. Constellationofa16-QAMsignal informationisencodedintotwocarrierwaves,whosephasesareinquadrature,byvariationofthecarrieramplitude,inaccordancewithtwoinputsignals.Asanexample,Figure 1{8 showstheconstellationofa16-QAMsignal.QAManditsderivativesareusedinbothmobileradioandsatellitecommunicationsystems.

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directconversiontransmitterwhichintegratesaVCO,themodulatorcircuit,andaPA,demonstratingoneofthemanypossibleapplicationsofthemodulator.Aboard-levelmodulatordesignedandtestedforOQPSKmodulationisintroducedinChapter6.ThemodulatorcircuitboardhastheabilitytogenerateMSKaswell.Chapter7summarizesthedissertationandtalksaboutfuturework.

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Modulatorsareafundamentalcomponentinintegratedcircuitsforwirelesscommunicationsystems.ThemostcommonlyusedmodulatorsareI/Qmodulators,whichoperatebytakingtwobasebanddatasequences(IandQchannels)andvaryingtheamplitudeandphaseofasinusoidalcarriersignalinresponsetotheinstantaneousIandQchannelvoltages[ 6 ].TheconceptualblockdiagramofatgenericI/QmodulatorisshowninFigure 2{1 [ 7 ].ManymodulatorsdesignedbasedontheI/Qquadratureschemehavebeenreportedsuchasin[ 8 ],[ 9 ],and[ 10 ]. 14

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Figure2{1. BlockdiagramofagenericI/Qmodulator Themodulationschemesintroducedinthelastchapterareallquadraturemodulations(exceptforBPSK).Choiceofmodulationschemeisatradeobetweenthetransmitspectrum,simplicityofdetection,anderrorrateperformance.IfweconsiderQPSKasavarietyofQAM,or4-QAM,thenthesemodulationscanbedividedintotwocategories:linearandconstantenvelope.LinearmodulationssuchasQAMrequirelinearamplicationbecausethedatainformationiscarriedinthesignal'samplitudevariations,whereasconstantenvelopemodulationssuchasGMSKaremorerobusttothedistortioncausedbynonlinearampliers,whichoerhigherpowereciency.Thereisnooneprominentmodulationschemebetweenlinearandconstantenvelopemodulationmethods,becausewhenitcomestoparticularapplication,itisimportanttolookatthetradeosinvolved.Forexample,QPSK'simportanceinCDMAisevidentwithitsecientbandwidthuse,enablingmoreuserswithinalimitedchannelbandwidth.GMSKmakesitscontributiontocellularsystemsincommunicationsthatnecessitatepowerecientampliers.Becausedierentmodulationshavedierentfeaturesandareusedindierentapplicationsandstandards,amodulatorthatcanrealizemorethanonemodulationschemeswillbeofgreatsignicanceforasoftwaredenedradio(SDR).

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ForaconventionalI/QmodulatorstructureasinFigure 2{1 ,dierentquadraturemodulationschemesrequiredierentbasebandprocessing,includingpulseshapingorltering.Forexample,togenerateaQPSKsignal,thesystemconvertsabitstreamintoaNon-Return-to-Zero(NRZ)signalwhichismultipliedbyanin-phase(I)carrierandaquadrature(Q)carrier.WhileforGMSKmodulation,theNRZsignalneedstobepassedthroughaGaussianlter.Similarly,anMSKmodulatorwouldneedtoshapethedatastreamintosinusoidalpulses,whereasaQAMsignalneedstobegeneratedbyvaryingtheamplitudeoftheI/Qcarriers.Therefore,todesignamodulatorcircuitthatcanaccommodatemorethanoneschemesusingtheconventionalI/Qapproachposesconsiderablechallengesonthedigitalcircuitsectionforbasebandprocessing.

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Figure2{2. Phasordiagramofamodulatedsignal wewilltrytomakethemodulatorsoftwarerecongurableandthusapplicableforasoftwaredenedradio. Asimplywaytoviewamplitudeandphaseiswithaphasordiagram,whichisexempliedinFigure 2{2 ,wherethesignalisinterpretedrelativetothebefore-modulationcarrier.Themodulatedsignalisexpressedbythephasorasamagnitudeandaphase.Magnitudeisrepresentedasthedistancefromthecenterandphaseisrepresentedastheanglerelativeto0degree,orIaxis.Thephasor'sprojectionontotheIaxisisits\I"componentandtheprojectionontotheQaxisisits\Q"component.Amplitudemodulationchangesonlythemagnitudeofthephasor,whilephasemodulationchangesonlytheangleofthephasor.Themagnitudeandtheangleofaphasorcanbechangedtogether,asinthecaseofQAM.

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Figure2{3. Howaphasorcanbegeneratedfromtwophasorsinquadrature Dierentmodulationswillproducedierentphasormovementsontheconstellation.Aslongasthephaseandamplitudechangesalongtheconstellationcircle,correspondingtoactualdatabits,canbegeneratedinintegratedcircuits,bothlinearandconstant-envelopemodulationscanbeimplemented.Asanexample,Figure 2{3 illustrateshow,inanyparticularquadrant,constantenvelopeanddierentphases,'s,canbegeneratedfromtwoLOcarriersinquadrature.Bymaneuveringthevaluesofaandb,whichcanbeseenastheweightsofcos!tandsin!t,thetwoquadratureLOs,respectively,canbechangedwhilermaintainsconstant.Thiscanberealizedusingaphasorcombining,orsumming,circuitwheretwoquadratureLOsignalsareweightedandsummeduptogeneratethein-betweenphasor.BychoosingpairsofquadratureLOsofdierentphasesaccordingtotheactualdata,thecorrectquadrantontheconstellationcanbeguaranteed.

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Figure2{4. Conceptualschematicofasummingcircuit Theapproachofgeneratinganin-betweenphasorfromtwophasorsinquadraturecanberealizedbyaphasorcombiningcircuit,orasummingcircuit,whosesimpliedschematiccanbeseeninFigure 2{4 .Inthiscircuit,V1andV2,areatcarrierfrequencyandhavea90degreedierenceinphase.I1andI2weighV1andV2respectively,andthesumofthetwoweightedLOs,Vout,willbethegeneratedphasorthatfallsbetweenthetwoinputphasors.Inotherwords,Voutcanbeinterpretedasacarriersignalwhosephaseisbeingchanged.TheamplitudeofVout,orthemagnitudeofthegeneratedphasor,alsodependsonthevaluesofI1andI2.IfthesumofI1andI2remainsconstant,themodulatedsignalwillhaveaconstantenvelope.BychoosingpairsofquadratureLOsofdierentphasesaccordingtotheactualdata,thecorrectquadrantontheconstellationcanbeguaranteed. Thismethodcanbeappliedtonon-constantenvelopemodulationssuchasQAM,whichutilizeamplitudevariationsaswell.Inthatcase,boththemagnitudeandtheangleofthephasorneedtobechanged,althoughitwillmakenon-linear

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amplicationdicult.However,evenifonlynon-linearpowerampliersaretobeused,makinguseoftechniquessuchasLINC(LinearAmplicationwithNonlinearComponents)[ 11 ],non-constantenvelopemodulationsstillcanberealizedwiththecombinationoftwosetsofconstantenvelopemodulatorsandnonlinearpowerampliers.Thisbringsbroadapplicationprospectsformodulatorsdesignedbasedonthisprinciple,whichessentiallyisjustchangingthephase,andpossiblyamplitudeaswell,ofacarrieraccordingtothemodulation.Forexample,asoftwaredenedradio(SDR)canusesuchmodulatorstoaccommodatedierentmodulations. 12 13 ]. Thephasorcombiningapproach,onthecontrary,doesnotrequirebasebandprocessing.Inprinciple,itdirectlychangesthephaseand/oramplitudeofthecarrier,accordingtothedesignatedphasormovementontheconstellation.

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Dierentmodulationschemes,andhencethedierentbasebandprocessingstheyneed,resultindierentphasormovementsonthemodulatedsignal'sconstellation.Therefore,inasense,thephasorcombiningapproachskipsthebasebandprocessing,theanalogmixingormultiplication,andthesummation,andtriestocreatethenalvectorsignaldirectly.ThisisdonebyselectingthepairsofV1andV2(seeFigure 2{4 )forcorrectquadrantsandbycontrollingtheweighingcurrentsI1andI2forcorrectsignalphase/amplitude.Thecircuitrycanbemuchsimpliedinthisway. Anothermajordierencebetweenthetwotypesofmodulatorsliesinthattheproposedmodulatoris\linear"inthesensethatcarrierphaseand/oramplitudearechangedlinearlybythebiascurrents(I1andI2)ofthephasorcombiningcircuit,whereasconventionalI/Qmodulatorsusuallymakeuseofdevices'nonlinearitytorealize\mixing"or\multiplication".ThisdierencebringsforthanimportantadvantageofthephasorcombiningapproachovertheconventionalI/Qmodulators.Channelltering,whichisnecessaryforcleaningupanonlinearmodulator'soutputspectrum[ 14 15 16 ],wouldnotbenecessaryforthephasorcombiningmodulator,makingitmoresuitableforhigherlevelofintegration.

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Manywirelessmobileproductsusenonlinearsaturatedpowerampliersbecausetheyhavehighereciencythanlinearampliers.Anon-linearamplierchangesthesignalamplitudebydierentamountdependingontheinstantaneousamplitudeofthesignal.Themoretheamplitudeofasignalvaries,themorenon-linearamplicationoccurs,whichwillresultinadistortedsignal.Therefore,modulatedsignalswithconstantenvelopeareoftenpreferredinwirelesscommunications. Inconstantenvelopemodulations,onlyphaseinformationisemployedtocarrytheuserdata,withthecarrieramplitudebeingconstant.TwoexamplesofconstantenvelopemodulationsareMinimumShiftKeying(MSK)[ 17 ]andGaussianMinimumShiftKeying(GMSK)[ 18 ].ComparedtoMSK,GMSKhastheadvantageofamorecompactpowerspectrumduetobasebandltering[ 4 ],butMSKdoesnotgenerateIntersymbolInterference(ISI)becausethe 22

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shapingsinusoidalpulseisconnedinabitduration.Ineithermodulation,datainformationiscontainedonlyinthecarrier'sphase.Sothistypeofmodulationscanbeinterpretedasphasemodulation. (b) Figure3{1. AnMSKmodulationexampleandthemodulatedsignal'sconstellation(a)MSKmodulationisI-Qmodulationwithhalfsinusoidalpulseshaping(b)Themodulatedsignalpresentsaconstantenvelopeconstellation

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Figure3{2. ADSsimulationforGSM Ifseenfromtheconstellationofaphasemodulationsignal,thesignalvector,or,thephasor,changesangleaccordingtothetransmittedbitswiththemagnitudeofthevectormaintainingthesame,whichresultsinapointmovingonaconstant-radiuscircleandchangingdirectionfromtimetotime.ThisisexempliedinFigure 3{1 ,whichshowsanMSKmodulationanditsconstellationfor8bitintervals.ThebasebandI/Qchanneldatabitsareshapedintosinusoidalpulsesandrespectivelymodulatedontotwocarrierswithquadraturephases.Thentheresultingsignalsofthetwochannelsaresummedup,andthemodulatedsignalbecomesaconstantenvelopecarrierwithchangingphase.ItcanbeseenthatontheresultingconstellationthephasormovesonacircleandchangesdirectionbasedontheI/Qbitpattern.Itgoesoveraquadrantforaone-bitinterval.

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Gaussian.This,however,signicantlycomplexiestheresultingmodulatedsignal'sphasechangepattern. ToinvestigatethephasechangepatternofaGMSKsignal,weusedADSsimulation(Figure 3{2 ).ThisdesignisusedtodisplaytheGMSKmodulationwaveform(Figure 3{3 )andspectrum(Figure 3{4 ).TherandomsourceisGMSKmodulatedandthebasebandsignalisfedtoRFsectionwhichincludes:RFmixer,ButterworthFilterandRFgain.CentralFrequencyis935.2MHzasinGSMstandard.WeexportedthedataforthesimulationresultandprocesseditinMATLAB.BoththeI-channelandtheQ-channelwaveformdatawereplottedontoanI/Qdiagramtoseethesignalconstellation(Figure 3{5 ).ThesimulationwasdonedynamicallytogetherwiththedatabitsinordertoobservethephasechangepatternofaGMSKsignalaccordingtothedatabits. Itcanbeseenfromthesimulationresultsthat,likeMSK,GMSKisalsoaconstantenvelopemodulationwithincreasedspectraleciency,makingitdesirabletomaximizethenumberofavailablechannels.BasedonthedynamicsimulationfromMATLAB,unlikeMSK,theboundarypointsforaone-bitintervalinGSMK,asshowninFigure 3{6 ,arenotonlytheaxispointsanymore.Moreover,becauseaGaussianpulseextendsintoboththepreviousbitsandthenextbits,thephasechangedependsonmorethanjusttwoconsecutivebitsasinthecaseofMSK.ThephasechangepatternofGMSKcanbesummarizedasinTable 3{1

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(a) (b) Figure3{3. ADSsimulatedGMSKwaveform(a)I-channel(b)Q-channel

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Figure3{4. ADSsimulationforGMSKspectrum Figure3{5. MATLABsimulationoftheconstellationofaGMSKsignal

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Figure3{6. BoundarypointsforonebitintervalonaGMSKconstellation Table3{1. SummaryofthephasechangepatternofGMSKmodulation previoustwobits,currentbit,nextbit phasechange 0000or1111

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19 ]orothertypesoflowpowerwirelessnetworks.ThemodulatoradoptsanMSK-basedscheme,butthephasechangeoveranybitinterval,whichcorrespondstoaquadrantontheconstellation,wasimplementedinalimitednumberofdiscretesteps,fourinthisparticulardesign,inordertosimplifythecircuitarchitecturewithoutcompromisingtheperformanceofthemodulatorsignicantly.Thiswillbeexplainedinthefollowingtogetherwithsomeotherissueassociatedwiththemodulatordesign. 3{7 ,whichalsoshowsthedierentPSDsgeneratedfromthephaseshiftmodulationbyusingdierentnumbersofphaseshiftswithineveryquadrant,startingfromtheaxispoints.Itcanbeseenthat,withonephaseshiftperquadrant,thePSDisthesameasthatofanOQPSKmodulation.Andasthenumberofphaseshiftstepsperquadrantincreases,thediscretephaseshiftmodulationapproachesMSKandthespectrumeventuallybecomesanMSKspectrum.

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Figure3{7. Comparisonofpowerspectraldensity(PSD)withrespecttothenumberofphaseshiftsperbitperiod.Normalizedfrequencyisusedinthegure AsshownintoFigure 3{7 ,thehighestnormalizedsidelobelevelforthecasesof1step,2steps,4stepsperquadrantare-14dBc,-18dBcand-22dBc,respectively.Withfourphaseshiftsperquadrant,thediscretephaseshiftmodulatorhasaverysimilarspectrumastheMSKthathasa-23dBchighestsidelobelevel.Aquadrantontheconstellationcorrespondstoabitperiod.Therefore,wechosefourphaseshiftstepsforeverybitperiodforthedesigntosimplifythecircuitarchitecture. Withfourphaseshiftsperquadrant,theoutputofthemodulatorshouldgenerateaconstellationliketheoneinFigure 3{8 ,wherethemodulatedsignalmovessequentiallyonthecircleindiscretestepsandchangesdirectiononlyontheIorQaxispoints.

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Figure3{8. Idealconstellationofthemodulatoroutput 3{7 weresimulatedbyassuminganidealmodulatorthatproducesconstantamplitudeandconstantphaseshiftstepsize.However,duetoasummingcircuit'sgate-to-drainRFfeedthroughofthetwoquadratureinputsignals,whichexistsevenwhenoneofthetwosummingweightsissettozero,perfectconstantamplitudewithineachquadrantofthemodulatedsignal'sconstellationcannotbeachievedbyrealcircuit.Thesizeofthephaseshiftstepsalsovariesacrosstheconstellation.Thevariationinthemodulatedsignal'samplitudeandphaseshiftstepwillleadtodeviationofthesignalpointfromtheidealsymbolpointonaconstellation,whichwillincreasetheEVMofthemodulator.TheEVM(ErrorVectorMagnitude)isthedierencebetweentheidealvectorconvergencepointandthetransmittedpointonasignalconstellation.It

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isdenedasthermsvalueoftheerrorvectorsinrelationtothemagnitudeofanidealsymbol.Itisobviousthatthebiggertheamplitude/phaseshiftvariationsare,theworsethemodulatorwillperformintermsofEVM.Meanwhile,wealsoneedtoinvestigatetheimpactontheoutputspectrum. Inordertotakeintoaccountmoreanddierentvariationsofthemodulatedsignal,theeectofthevarianceofvariationsintheoutputsignal'samplitude,orinitsphaseshiftamongthefourstepswithineachquadrant,wasfurtherstudied.Thatis,wetreatedthevariationasarandomvariable,withameanofzeroandanapproximatedvariancebasedonthedatafromsimulationresults,andstudiedtherelationshipbetweenthemodulator'sperformance,intermsofsidelobelevel,andthevarianceofthevariation(VOV).WedenotedVOVas2V. Forexample,basedonprobabilitytheory,theVOVinphaseshiftcanbeapproximatedas 44Xi=1[(^ii) wherei=1:4=0;=8;=4;3=8and^i'sareactualvaluesofimplementedphases.Tosimulatetheeect,fournormallydistributedrandomvalueswithzeromeanandvarianceof2Vweregeneratedtorepresentthevariationsfromthefouridealphasepointsinaquadrant.Figure 3{9 plotstherstsidelobelevelnormalizedtomainlobelevel(dBc)versusthedierentvaluesofVinphaseshift.Forthemodulatordesign,maximumangledeviationfromtheidealphasorcanbelookedupinFigure 3{9 astheworstcasescenariointermsofphaseshiftvariationtoseehowtheperformancewillbeaected.TheresultsshowninFigure 3{9 indicate

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Figure3{9. Normalizedsidelobelevel(referencedtomainlobelevel)versusvariationsinamplitudeandphaseshift(TheX-axishasaunitofradiansforphaseshiftvariation,anditindicatespercentageforamplitudevariation that,ifVislessthan0.1radian(5.73),theincreaseofsidelobelevelfromtheidealcaseislessthan1dB. Figure 3{9 alsoplotstheeectofamplitudevariationonthePSD'ssidelobeincrease.Theeectappearstobesimilartothatofphaseshiftvariation.NotethattheX-axishasaunitofradiansforphaseshiftvariation,anditindicatespercentageforamplitudevariation.Therefore,whenVintheamplitudeofthemodulationislessthan10%,orwhenVinthephaseshiftstepislessthan0.1radian,themodulator'sperformancewillnotbedegradedsignicantly.Itshouldbepointedout,however,thatthevariationintheamplitudeofthemodulatedsignalislikelytodisappearafterthesignalisampliedbyanon-linearandsaturatedpower

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Figure3{10. Howfourdiscretephasorswithinaquadrantcanbegeneratedfromtwophasorsinquadrature amplier(PA).Therefore,itshouldnotbeacriticalfactorfortheperformanceofthemodulatorwhenintegratedinatransmitterwithanon-linearPA. 3{10 specicallyillustrateshowthefourdiscretephaseswithinaquadrant,orthefourphasors(P0,P1,P2,P3),canbegeneratedfromtwoquadraturephasorssin!tandcos!t.Table 3{2 liststhefourpairsofsummingweights(aandb)forgeneratingthefourphasors. Table3{2. Summingweightsforgeneratingdierentphasors P1 P2 P3 3

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Figure3{11. Constantenvelopephaseshiftmodulator AblockdiagramoftheconstantenvelopephaseshiftmodulatorcircuitisshowninFigure 3{11 .Thecircuitismainlycomposedofa2:1divider,two4:1dierentialmultiplexers,aphasorcombiningcircuit(summingcircuit),outputbuers,andadigitalcircuitsectiontocontroltheseblocks. 3{12 ,generatesfoursignalswithphasesthatareequallyseparatedover360degrees,asindicatedbythefourcrossesontheI/QaxesinFigure 3{8 .Thedividerhasadierentialmaster-slaveconguration.Theinvertedslaveoutputsareconnectedtothemasterinputs.Thecrossconnectionbetweentheslaveandthemastergeneratesanoutputfrequencyathalfoftheinput(CLKandCLKb)frequency.Thedierentialoutputfromthemaster(QiandQbi)isinquadraturewiththatoftheslave(QandQb).Therefore,

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(a) (b) Figure3{12. A2:1staticfrequencydivider(a)Blockdiagram(b)Adetaileddividerschematic withadierentialinputatafrequencytwicethedesignatedLOfrequencyforthemodulation,thedividerwillprovidefourLOsignalswhosephasesare90degreesapartfromoneanother.Boththemasterandtheslaveconsistoftwoinputtransistors(M1andM2),twodrivetransistors(M4andM5),twolatchtransistors(M3andM6),andtwoloadtransistors(M7andM8).Theself-oscillationfrequencyofadividerincreasesasthesizesofthetransistorsaredecreased,althoughdrivertransistorsizehaslesseectthatthesizesofothertransistors[ 20 ].Atagiven

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drivetransistorsize,thesmallerthelatchtransistors'sizeis,thelowertheoutputvoltageamplitudegets[ 20 ].However,increasingtransistors'sizewillalsoincreasepowerconsumption.Duetothesetradeos,andsincethedividermustbedesignedbasedontheacceptablepowerconsumptionandoutputsignallevel,thechosentransistorsizeswillsetalimitontheoperatingfrequencyofthedivider.Theoperatingfrequencyrangeofthedividerwilldeterminethemodulator'soperatingbandwidthtoagreatextent. 3{11 .Oneofthetwoclocks,Clock1inthisdesign,controlsthebitrate,andtheotherclockembedsthedigitaldatabits.Figure 3{13 showstheschematicofa2:1current-steeringMUX[ 14 ]usedinthedesign.Thisstructureallowsforareducedvoltageswing.Simulationsalsoindicatethatswitchingofthecurrentcanbeperformedataspeedhigherthanswitchingofthevoltage[ 14 ].ThereforethistypeofMUXcanincreasetheoperatingspeedofthecircuit,whichallowsfor

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Figure3{13. A2:1dierentialcurrent-steeringmultiplexer higherdatarates,especiallyifthesamecircuitryistobeusedforimplementingdierentmodulationschemes. Comparedtoaone-stage4:1MUX[ 15 ],thetwo-stageconguration,althoughmorecomplex,suerslessspeedpenaltyandmaintainsfully-dierentialsignalsbetter[ 16 ].Bothcongurationsrequireatleasttwoinputs,onefortheclocks,andtheotherfordata,whichwilldecidewhattoselectfromthefourLOsignals.Simulationresultalsoshowedthat,forthismodulatordesign,thepowerconsumptionofusingtwo-stageMUXeswasnotsignicantlyhigherthanusingone-stageones.

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Figure3{14. Phasorcombiningcircuit 3{14 .Thephasor-combiningcircuitsumstheinputsignalstoproduceasignalwithaphaseshiftingbetweenthoseofthetwoinputs.Dierentintermediatephasescanbegeneratedbyapplyingdierentbiascurrents(I1andI2)assummingweights,whichcanberealizedbyusingdigitallogiccircuitstoswitchthecurrentsources.AscanbeseenfromFigure 3{14 ,threeswitches,whichturnonorothethreebiascurrentsourcesIb1,Ib2,andIb3,arecontrolledbydigitalcircuittogeneratefourdierentcombinationsofI1andI2valueswithinabitinterval,inordertoimplementthefourintermediatephaseshiftswithinanyparticularquadrantperiod.Thedigitalcontrolsignalsforswitch1andswitch3aredierentialand

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thusneitherIb1norIb3willcontributetoI1orI2atthesametime,whileIb2alwayscontributestoI1only.ThecontrolsoftheswitchesaredesignedsuchthatthefourcombinationsofI1andI2areasfollows. 1)I1=Ib1+Ib2+Ib3/cos0;I2=0/sin0(togeneratea0phaseshiftrelativetothepresentstate); 2)I1=Ib2+Ib3/cos22:5;I2=Ib1/sin22:5(togeneratea22:5phaseshift); 3)I1=Ib1+Ib2/cos45;I2=Ib3/sin45(togeneratea45phaseshift); 4)I1=Ib2/cos67:5;I2=Ib1+Ib3/sin67:5(togeneratea67:5phaseshift). I1andI2weighthepresentstatesignalandthenextstatesignalrespectively,andVoutisthesumofthetwoweightedsignals,withanin-betweenphase.Inthemeantime,constantamplitudeofVoutcanbemaintainedbykeepingthesumofI1andI2constant(Ib1+Ib2+Ib3). 3{15 arecascadedtoserveasthedriver.Thebuersuseresistorloadstoachieveabroadbandresponse.ThereisalsoabuerstagebetweentheMUXesandthephasorcombiningcircuit.

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Figure3{15. Schematicofthebuer

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Figure3{16. Flip-oplatch showninFigure 3{16 [ 21 ].Latchesarealsousedtolineupthecorrectedgesofthegeneratedclocksandcontrols. 3.4.1ModulatorICFabricatedin0.18mCMOSProcess 3{17 Indesigningthisparticularmodulatortestingchip,repetitivedatapatternwasinternallygeneratedandtranslatedintothemultiplexers,creatingamodulatedsignalthatmovesclockwiseincirclesataconstantspeed,determinedbythedatarate,ontheconstellation.Thepurposewastwofold:1)toreducethespectrumbandwidthoftheoutputsignalsothatitcanbemeasuredbyequipmentwithlimitedbandwidth;2)tosimplifytestingtheICwithouttheneedforahigh-speed

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Figure3{17. DiemicrophotographofthemodulatorIC(0.18mchip) datapatterngeneratinginstrumentormultiplehighfrequencyclocksignalsources.Inthisdesign,onlyanRFsignalinput,forthedividertogeneratethefourphasedLOsignals,andasingleclockinput,forcontrollingtheMUXesandtimingtheinternaldigitalcircuits,areneeded. Toderivethemathematicaldescriptionofasignalmodulatedinsuchaway,assumethatthecarrierisintheformofAcos(2fct+0),whereAistheamplitudeofthecarrier,fcisthecarrierfrequency,and0istheinitialphaseofthecarrier.Withoutlossofgenerality,0canbeassumedtobezero.Amodulatedsignalmovingclockwiseontheconstellationcirclecontinuouslymeansthatthecarrier'sphasedecreasescontinuouslywithtime.DenotethebitrateasRandthereforethebitintervalT=1=R.SincethephasechangeofanMSKsignalwithinabit

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interval,T,is=2,themodulatedsignal,s(t),canbeexpressedas (3{2) =Acos(2fct (3{3) =Acos[2(fc1 4R)t]: Therefore,s(t)isstillasingletonesinusoidalsignal,butitsfrequencyis1 4Rlowerthantheoriginalcarrierfrequency.Becauseinthisdesignthecontinuousphasechangeisimplementedinfourdiscretesteps,themathematicalexpressionfortheactualsignal,sa(t),shouldinsteadbe T=4c);(3{5) wherebcistheooroperator,whichgivesthelargestintegerlessthanorequaltotheoperand.MATLABsimulationwasperformedtoestimatedtheoutputspectrumofsa(t),whichisshowninFigure 3{18 ThemodulatorICwastestedusinganAgilent89600seriesVectorSignalAnalyzer(VSA)withanexternalpoweramplierconnectedtotheoutputofthechip.TheVSAhasabandwidthof36MHz.Fromthemeasuredspectrumofthemodulator'soutputsignalinFigure 3{19 ,itcanbeseenthatitmatchesthetheoreticalestimation.Thebitratewassetto100Mbpsinthemeasurement,thecarrierfrequencywas2.5GHz,andthespectrumshowsasingletonewiththecenterfrequencyat2.475GHzwhichisexactly25MHzlowerthanthecarrierfrequency.Itshouldbepointedoutthat,althoughxeddatapatternwas

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Figure3{18. Simulatedoutputpowerspectrumforthexedrepetitivedatapattern Figure3{19. Measuredoutputpowerspectrum.Signals'sfrequencyis25MHz,oronefourthofthe100MHzbitrate,lowerthanthe2.5GHzcarrierfrequency.

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Figure3{20. Measuredconstellation(0.18mchip)ofthemodulatedsignal(EVM=2.8%).Thesignalmovedsequentiallyandrepetitivelyinfullcircles designedandusedtosimplifythemeasurement,attheendofeverybitintervalthemultiplexersalwaysre-selecttwoLOsinquadratureasthenew\present"and\next"states.Therefore,thedatarateofthexedpatterndatastillsigniesthebitratethatthemodulatorcanmanageforarbitrarydatapatterns.Asobservedinthemeasurement,asthedatarateincreased(thesignalvectorrotatedclockwisefaster),thefrequencyshiftinoutputspectrumalsoincreased. Figure3{21. MeasuredI/Qplanediagram(0.18mchip)ofthemodulatedsignal Figure 3{20 showsaconstellationmeasuredusingAgilent89600VectorSignalAnalyzer(VSA),withanexternalpoweramplierconnectedtothe0.18m

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Figure3{22. MeasuredEVMvs.carrierfrequency(0.18mchip).At100Mbpsbitrate,forEVMslowerthan5.5%,themodulatorcanoperateatacarrierfrequencybetween1.75GHzand3.5GHz chip'soutput.Thistestwasusedtoverifythecorrectnessofthephaseshifts.TheI/QplanediagraminFigure 3{21 demonstratestheconstantenvelopefeatureofthemodulator.Thebitratewassetto100Mbpsinthemeasurement.ThemeasurementresultshowedanaverageEVM(ErrorVectorMagnitude)of3%. Withoneofthedierentialoutputsterminatedby50,the0.18mtestchipdeliveredasignallevelof-2dBmtoa50load.Themodulatorwasdesignedforlowpowerapplications,andthemeasuredcurrentdissipationwas2mAwiththesupplyvoltagebeing1.8V.Itshouldbenotedthatthiscurrentdissipationdidnotincludethatofthethreecascadedoutputbuers,which,althoughconsumed10mAcurrent,arenotnecessarilyanintegralpartofthemodulator,ifthemodulatorisputintoatransmitterchainandonlyneedstodrivetheinputimpedanceofthenextstagecircuitsuchasanmixerorapoweramplier.

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Figure3{23. MeasuredEVMvs.bitrate(0.18mchip).At2.5GHzcarrierfrequency,forEVMslowerthan5%,thebitrateofthemodulatorrangesfromDCto500Mbps Thefrequencyrangeofthecarrierwasalsomeasured.Themeasurementwasdonebykeepingthebitratexedat100MbpsandmonitoringthesignalconstellationandEVMwhilechangingtheRFinputfrequencywhichistwicetheLOcarrierfrequency.AscanbeseenfromFigure 3{22 ,withinthecarrierfrequencyrangeof1.75GHzto3.5GHz,themodulatorworksnewithlowerthan5.5%EVMs(TheIEEE802.11astandard[ 22 ]speciesamaximumEVMof5.62%forthepeakdatarateof54Mbps.).Anothermeasurementwasdonetondoutthebitratethemodulatorcircuitcanhandlewitha2.5GHzcarrier.TheresultingEVMsatdierentbitratesareplottedinFigure 3{23 .Althougha500MbpsbitratecanturninadecentEVMof5%,measurementshowedthathigherbitratewouldresultinblurryconstellation(seeFigure 3{24 )anddegradedEVM(greaterthan6%),ifthecarrierfrequencyremainedthesame.

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Figure3{24. Constellation(EVM=6%)atbitrategreaterthan500Mbps(0.18mchip) Figure3{25. Whentheerrorvectorisperpendiculartotheidealphasor,thephasevariationisthebiggest EVMisadirectmeasureoftheaccuracyofamodulator.ThecontributorstothedegradationinEVMcouldincludevariationsinphaseandamplitude,phasenoise,poorfrequencyresponseatanystageofthesystem,poorreturnloss,andvirtuallyanyotherRFsystemrelatedproblems.AtacertainEVMvalue,themaximumpossiblephasevariation,,occursinthecaseofFigure 3{25 ,wheretheerrorvectorisperpendiculartotheidealphasor.ForEVM=6%,approximatelyequals0.085radian.AccordingtoFigure 3{9 ,thisvariationwillnotaectthePSDsignicantly.Sameanalysiscanbeappliedtotheamplitude

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Figure3{26. Whentheerrorvectorisinthesamedirectionastheidealphasor,theamplitudevariationisthebiggest variation,wheretheworstcasescenarioisasinFigure 3{26 .Again,ata6%EVM,thevariationinamplitudehaslittleimpactonthemodulator'soutputPSD,especiallyconsideringthatthesignalwillbeampliedthroughanamplierinsaturation. Abriefperformancesummaryfortheconstantenvelopephaseshiftmodulator(0.18mchip)islistedinTable 3{3 Table3{3. Summaryofmodulatorperformance(0.18mchip) 3{27 .Themicrophotographofthe0.13mchipisshowninFigure 3{28 .The0.83mm2chipsizeisconsiderablybiggerthanthe0.18mchip,becausemorepadsforDCbiaseswereplacedonthis

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Figure3{27. Completemodulatortestchipcircuit(0.13mchip)

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Figure3{28. DiemicrophotographofthemodulatorIC(0.13mchip) chipforthepurposeofseparatelycontrollingofthethreestagesofoutputbuersandadjustingtheamplicationgains.Thereasonformorecontrolsandbiasesisthatbigmetalcapacitors,whoseparasiticvaluesarehigh,wereusedinthelayoutasinter-stagecouplingcapacitorsbecausenoMIMCAPsareavailableinalogicprocess. Figures 3{29 and 3{30 arethemeasuredconstellationandtheI/Qplanediagram,respectively,ofthe0.13mchip'soutput.Themeasurementsetupwasalmostthesameasforthe0.18mchip,exceptthatmoreDCpowersupplieswereusedforoutputbuerbiascontrol.Atacarrierfrequencyof2.5GHzandabitrateof100Mbps,themeasuredEVMwas3.5%.

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Figure3{29. Measuredconstellation(0.13mchip)ofthemodulatedsignal(EVM=3.5%) The0.13mtestchipalsohasameasuredcurrentdissipationof2mA(excludingoutputbuers)withthesupplyvoltagebeing1.2V,sothepowerconsumptionwasevensmallerthanthe0.18mchip.Theoperatingcarrierfrequency(ata100Mbpsbitrate)rangesfrom1.5GHzto3.3GHz,withthemeasuredEVMsallequaltoorbelow4%(Figure 3{31 ).However,themaximumbitrateappearedtobemuchlowerthanthe0.18mchip,ascanbeseenfromFigure 3{32 .Ata250Mbpsdatarate,theEVMvalueisalready6.5%,withthecarrierfrequencymaintainingthesameat2.5GHz.Comparedtothepreviouschip,thesmalleroperatingfrequencyrangeandbitraterangeareprobablycausedbythecouplingcapacitorsusedinthelayout.BigmetalcapacitorswithconsiderablyhigherparasiticvalueswereusedinsteadofMIMCAPs,whichledtohigherinter-stagepowerlossinthecircuit.Therefore,theoutputsignalleveldecreased,degradingSNRandhenceEVM.Aperformancesummaryfor0.13mmodulatortestchipislistedinTable 3{4

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Figure3{30. MeasuredI/Qplanediagram(0.13mchip)ofthemodulatedsignal Table3{4. Summaryofmodulatorperformance(0.13mchip) (excludingoutputbuers) 3{5 comparesthisworktosomeofthereportedmodulatorsofsimilarfunctions.

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Figure3{31. MeasuredEVMvs.carrierfrequency(0.13mchip).At100Mbpsbitrate,forEVMslowerthan4%,themodulatorcanoperateatacarrierfrequencybetween1.5GHzand3.3GHz Figure3{32. MeasuredEVMvs.bitrate(0.13mchip).At2.5GHzcarrierfrequency,forEVMslowerthan5.5%,thebitrateofthemodulatorrangesfromDCto225Mbps

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Table3{5. Comparisonofmodulatorperformance Operating Reported consumption frequencyrange Bitratemodulators (mW) (GHz) (Mbps) AD8349 675 0.7-2.7 0-160 MITEQ SDM6474LCDQ 1800 6.4-7.4 0-100 CMOSI/Q modulator#1[ 23 ] 175 2.4 11 CMOSI/Q modulator#2[ 24 ] 187.8 1 3.75 thiswork 3.6 1.75-3.5 0-500

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Constantenvelopemodulations,suchasMSKandGMSK,allowthepoweramplier(PA)tobeoperatedinsaturation,andcanachievegreatereciencythanlinearmodulations.Thetestmodulatorintroducedinthepreviouschaptercangenerateaconstantenvelopemodulatedsignal,andthereforecanbeusedinalowpowertransmitterutilizinganon-linearPA,suchasaClassBoraClassCPA. Thestandalonetestmodulatorintroducedinthepreviouschapteronlyaccommodateaxeddatapattern,whichresultsinasignalpointmovingsequentiallyinthesamedirectioninfullcirclesontheconstellation.ThereasonsforthatdesignwerethatitcansimplifythedigitalcircuitrytosomeextentandthatmeasurementwillberelaxedintermsoftherequirementSforequipment,becausearandomorpseudorandomdatageneratorwouldnotbenecessary. Buttobeintegratedinatransmitter,themodulatorshouldbeabletotakearbitraryinputdataandmodifythemontothecarrier.Therefore,thepreviousmodulatorcircuitwasmodiedaccordingly,withnomajorchangesmadetothearchitecture. 57

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circlesontheconstellationasintroducedinthepreviouschapter,hasbeenprovedtohaveverygoodperformance.Therefore,thedesignofamodulatorforarbitrarydatashouldbeaimedtoinvolveminimalmodication.Hence,thefundamentalcircuitarchitectureofthismodulatorforarbitrarydatapatternsremainsthesameasthetestmodulator,exceptthattheclockgenerationanddigitalcontrolcircuitneedstobemodiedinordertotaketheinputofserialdigitaldatabits.However,theinternalclocksfortimingthemultiplexersandforcontrollingtheswitchesofthephasorcombiningcircuitarestillgeneratedfromoneexternalclockinput. LetustakealookbackattheexampleofanMSKsignalinthepreviouschapter.InFigure 3{1 (a),theserialdigitaldatabitsare10110010beforebeingconvertedtotwoparalleldatastreams(Istream1101andQstream0100).TheresultingphasormovementcanbeseeninFigure 3{1 (b)andisredrawnhereinFigure 4{1 forconvenienceofdiscussion.ItshouldbenotedthatA,B,C,andDinthisgurearethefourboundaryphasepointsforthebitintervals.Thesignalswiththesefourphasescanbegeneratedattheoutputofthedivider,ascanbeseeninFigure 3{27 Asexplainedinthepreviouschaptor,themodulatorcircuitneedstoselectthecorrectboundariesforeachbitinterval,whichistobedonebythetwo4:1MUXes.Becausethephasorwouldmovefromoneboundarypointtoanadjacentotheroneduringeachbitinterval,twoboundarypoints(startingpointandendingpoint)needtobeselectedbythetwoMUXesrespectively,whichiswhatismeantbythe\present"stateandthe\next"stateinthepreviousdescriptionofthemodulatorcircuit.Forthis8-bit-intervalMSKexample,Figure 4{2 showstheboundarypoints

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Figure4{1. Movementofthephasorwhenserialdatastream10110010isMSKmodulated Figure4{2. Boundaryphasesontheconstellationforthe8bitintervals

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Figure4{3. HowastatestreamcanbegeneratedattheoutputofaMUX atthe8bitintervals.Forthese8intervals,thestartingpoints,orthe\present"states,whicharetobeselectedbyoneofthetwoMUXes,areA,B,A,D,C,B,A,andB,whiletheendingpoints,orthe\next"states,whicharetobeselectedbytheotherMUX,areB,A,D,C,B,A,B,andC.Theendingpointofthe8thbitintervalCwillbethestartingpointofthe9thshouldtherebeone.Fordiscussionpurpose,theoutputofanMUXforaseriesofbitintervalsiscalledstatestream.Itcanbeseenthat,thephasestreamsatthetwoMUXes'outputarethesame,exceptthattheMUXforthe\present"statesgeneratesastatestreamthatisdelayedbyonebitinterval,comparedtothestatestreamgeneratedbytheMUXforthe\next"states. Figure 4{3 illustrateshowa4:1MUXisdesignedandcontrolledtoselectthecorrectphasestatesaccordingtotheinputserieldatabits.Notethatthe\clock"hereisnottheclockinputtotheentirechipbutratheronethatisgenerated

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therefrom.Asinthepreviousdesign,\clock"isinternallygeneratedbytheon-chipdigitalcircuitsectionanditsrateistwicetherateofserialdata.ThisMUXcanbeusedforthe\next"statestream,whileforthe\present"statestream,both\clock"and\data"aredelayedbyonebitintervalusingaip-oplatchasinFigure 3{16 .Eortsalsoneedtobemadetoensuretheedgesofthedigitaldatabitsandtheclocksarelinedup. TheblockdiagramofthemodiedmodulatorforarbitrarydatapatternsisshowninFigure 4{4 .Itcanbeseenthatthemainarchitectureofthemodiedmodulatorforarbitrarydatapatternsremainsthesameastheonewithaxeddatapattern.ThecontinuousphasechangeofMSKwithinanyquadrantisstillimplementedinfourdiscretesteps.Withpseudorandominputdatabits,theidealnormalizedoutputpowerspectraldensity(PSD)willbetheoneinFigure 3{7 forthecaseof4phaseshiftsperquadrant.WecantakeitoutandshowitinFigure 4{5 .TheidealconstellationforMSKmodulatedrandomdataisaconstantenvelopecircle,withfourdatapointseachinonequadrant,asinthecaseofQPSK/OQPSK.Figure 4{6 illustrateswhattheconstellationwilllooklike. 4{7 .Theareaofthechipis0.677mm2. Figure 4{8 showsthemeasurementsetupfortestingthemodulatorcircuitwithpesudorandominputdatabits.ThesignalgeneratorprovidesanACsignal

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Figure4{4. Modulatorcircuitforarbitrarydatapatterns Figure4{5. IdealnormalizedoutputPSDforthemodiedmodulatorifpseudorandominputdataareapplied

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Figure4{6. Idealconstellationforthemodiedmodulatorifpseudorandominputdataareapplied Figure4{7. Diemicrophotographofthemodulatorcircuitforarbitrarydatapatterns

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Figure4{8. Measurementsetupfortestingthemodulatorcircuitwithpesudorandominputdatabits whosefrequencyistwicethedesiredcarrierfrequency,orLOfrequency,forthemodulator.Theon-chip2:1frequencydividerwillgeneratefourLOswhosephasesareinquadraturewithoneanother.AgilentN4906Abiterrorratetester(BERT)isusedtoprovidethecircuitwithdataandclockinputs.ItshouldbenotedthattheBERTdataoutputhasthesamerateasitsclockoutput,whiletheactualmodulatorcircuitneedsaninputclockratethatisfourtimestheinputdataratebecausetheinputclockwillbeusedtogeneratealltheon-chipclockandcontrolsignals,includingthe\clock"signalinFigure 4{4 .However,themeasurementisfeasibleusingtheBERTdespiteitsseeminglywrongdatarate,becausetheinputdatabitstothemodulatorarebeinglatchedbyip-opsattherateofoneoftheinternallygeneratedclocks,whichisthedesireddatarate.Therefore,theip-opsactlikeasamplerwhichsamplesthehigher-ratedatainputatthedesireddataratewhichthecircuitneeds.TheBERTcangeneratehardwarebasedpesudorandom

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Figure4{9. Measuredconstellationat2.5GHzcarrierfrequencyand12Mbpsbitrate bitstreams(PRBS)upto2231,thereforetheactualsampleddataintothemodulatorcircuitareaPRBSof2211becausethedatarateaftersamplingisonefourththerateoftheBERT'sdataoutput.Themodulator'sdierentialoutputsignalismeasuredbyterminatingoneendwith50andexternallyamplifyingtheoutputoftheotherend.TheampliedsignalisconnectedtoaspectrumanalyzerandaVSAhardwareviaapowerspliter.TheVSAhardwareisconnectedtoaPCwheretheVSAsoftwareisinstalled.Themodulatedsignalwillbedown-convertedandsampledbytheVSAhardwareanddemodulatedbytheVSAsoftware.Thedemodulatedsignal'sconstellationandI/QdiagramcanbedisplayedonthePC'smonitor. TheAgilent89600SVSAislimitedtoabandwidthof36MHzbyitsdigitizer.Therefore,thedatarateofamodulatedsignalitcanmeasureisalsolimited.Toaccuratelydemodulateasignal,ideallyallthesidelobesinthespectrumshouldbe

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Figure4{10. MeasuredI/Qdiagramat2.5GHzcarrierfrequencyand12Mbpsbitrate includedinthefrequencyspanoftheVSA.Sincethelowestoutputclock/datarateoftheBERTis48MHz,themodulatorwasmeasuredat2.5GHzcarrierfrequencyand12Mbpsbitrate.Figure 4{9 andFigure 4{10 showthemeasuredconstellationandI/Qdiagramrespectively.Atthiscarrierfrequencyandbitrate,theaveragemeasuredEVMwas7%. Figure 4{11 showsthepowerspectrumofthemodulatedsignalmeasuredbyaspectrumanalyzer,anditcanbeseenthatthemeasuredresultisquitesimilartothesimulationresultinFigure 4{5 .Figure 4{12 allowsforacloserlookatthemainlobeanditsadjacentsidelobesofthemeasuredspectrum.Itcanbeseenthatthemeasuredmainlobewidthisapproximately18MHz,whichis1.5timesthebitrate,andtherstsidelobesareabout12MHz,whichisonebitrate,awayfromthecenterfrequency.TheseareconsistentwiththesimulationresultinFigure 4{13

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Figure4{11. Measuredpowerspectrumat2.5GHzcarrierfrequencyand12Mbpsbitrate ThemeasuredpowerspectraatsomehigherbitratescanbeseeninFigure 4{14 andFigure 4{15 ,wherethebitratesare50Mbpsand100Mbps,respectively,whilethecarrierfrequencyremainsthesameat2.5GHz.Theoutputsignal'spowerlevelisaround-3dBm.Notethatforthesemeasurementresultstheresolutionbandwidthofthespectrumanalyzerwassetto3MHz.Thepowerconsumptionofthismodiedmodulatoristhesameasthepreviousmodulatorwiththexeddatapattern.Thatis,themodulatorwithouttheoutputbuerstodrive50loadsdissipates2mAcurrent,whiletheoutputbuersneedatotalofnearly10mAbiascurrent. ThismodiedmodulatorcircuitforarbitrarydatapatternsisagreatcandidatetobeusedforpersonalareanetworkscomplyingwiththeZigBeetechnology.TheIEEE802.15.4standard[ 25 ],whichaZigBee-readytransceivershouldbecompliantto,isdesignedforlowcost,lowpowerconsumptionwireless

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Figure4{12. Measuredpowerspectrumwithasmallerfrequencyspanat2.5GHzcarrierfrequencyand12Mbpsbitrate Figure4{13. Simulatedpowerspectrumofthemodulatoroutputwithpesudorandominputdatabits

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Figure4{14. Measuredpowerspectrumat2.5GHzcarrierfrequencyand50Mbpsbitrate Figure4{15. Measuredpowerspectrumat2.5GHzcarrierfrequencyand100Mbpsbitrate

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Figure4{16. IEEE802.15.4andZigBeeworkingmodel applicationswithmoderatedatarates.ThestandardspeciesthePhysical(PHY)andMediaAccessControl(MAC)layersatthe868MHz,915MHzand2.4GHzISMbands,andthechipmodulationschemesareO-QPSKwithhalf-sinepulseshaping(MSK)for2.4GHzPHYandBPSKwithraisedconsinepulseshapingfor868/915MHzPHY,respecitvely.ThelayersoftheIEEE802.15.4standardandZigBeetechnologyareshowninFigure 4{16 [ 26 ].The2.4GHzPHYoftheIEEE802.15.4standardismoreattractivetothewirelessindustrybecausethe2.4GHzunlicensedISMbandisgloballyavailableandthereforeexibleinapplicationdesigns[ 26 ].Thechiprateforthe2.4GHzPHYis2Mchips/sfromadatarateof250kbps,andthespeciedEVMrequirementis35%.TheaverageEVMresultofthismodulatorat2.5GHzcarrierfrequencyand12Mbpsbitrateis7%,andtherecordedworst-caseEVMvalueisaround10%,whichisstillwellbelowtherequirementlimit.

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Figure4{17. OutputspectrumoftheCC2420transmitter Figure 4{17 showstheoutputpowerspectrumoftheCC2420transmitter[ 26 ].TheCC2420isalow-costtransceiverdesignedforlow-power,low-voltageRFapplicationsinthe2.4GHzISMband.ItisaZigBee-readyCMOSdeviceusingamainstream0.18mtechnology.Ascanbeseenfromitsoutputspectrum,themainlobeoccupiesabandwidthofapproximately3MHz,whichistwicethe2Mchip/schiprateintheIEEE802.15.4specication.ThemodulatedsignaltransmittedbytheCC2420hasaworst-caseEVMof20%[ 26 ].Therefore,themodulatorcircuitofthisworksurpassestheperformanceoftheCC2420intermsoftransmitmodulationaccuracy.ItalsosupportsmuchhigherdataratethantheCC2420.

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TheperformanceofthemodulatorcircuitforarbitrarydatapatternsissummarizedinTable 4{1 Table4{1. Performancesummaryofthemodulatorforarbitrarydatapatterns (excludingoutputbuers)

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Inthepreviouschapter,weintroducedadigitallycontrolledphaseshiftmodulatorcircuitforanMSK-likemodulationscheme,whichissuitableforZigBee-readyIEEE802.15.4-compliantdevices.Suchdevices,asthestandardisdesignedfor,areexpectedtobelowcostandlowcomplexity.Inaddition,thecompliantsystemimplementationswillenablelongbatterylifebyusingthepower-savingfeaturesatthePHY,MAC,andnetworklayersspeciedbythestandard[ 26 ]. Inadditiontothefunctionalityofthemodulator,wealsowantedtodemonstratethemodulator'ssuitabilityforhighlevelintegration.Therefore,weintegratedthemodulatorcircuitintoadirectconversiontransmitter,whichwillbeintroducedinthefollowingsections. Directconversiontransmittersappealtodesignersofwirelesssystemsfortheirsimplicityandlowcost.Thedirectconversionarchitectureeliminatesthe 73

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Figure5{1. GenericdirectconversiontransmitterutilizingtheconventionalI/Qmodulator intermediatefrequency(IF)stageanditsaccompanyingIFsurfaceacousticwave(SAW)lter,mixer,andvoltage-controlledoscillator(VCO)components.Fewerpartsmeanslowertotalcost,smallerdevicesandgreaterreliability.Italsomeanslessinsertionlossandlesspowerconsumption.Althoughasuperheterodynetransmitterisgenerallyconsideredahigher-performancetransmitter,ifthesystemrequirementscanbemetwiththedirectconversiontransmitter,whichismoresuitableforhighlevelsofintegration,thenamoreeconomicalradiocanberealized. Indirectconversiontransmitters,modulationisdonedirectlytothecarrieratthedesignatedoutputfrequencyandanupconversionisnotneeded.Asimpledirectconversiontransmittergenerallyconsistsofanoscillator,amodulator,andpowerampliers,whileacomplicatedonewouldincludeaphase-lockedoscillator.Figure 5{1 [ 27 ]showsasimpliedblockdiagramofagenericdirectconversiontransmitterutilizingtheconventionalI/Qmodulatorasweintroducedpreviously.

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Itcanbeseenthatthetransmitterincludesbasebandprocessingandanalogmixingthroughtwomixers.ThedigitallycontrolledconstantenvelopephasemodulatorofthisworkhasthefunctionofrealizingtheI/Qmodulationschemes.ItalsohasmanyadvantagesovertheconventionalI/Qmodulators.Therefore,weincorporatedthismodulatorintothedesignofthedirectconversiontransmitter,whoseblockdiagramisshowninFigure 5{2 .Inthisdesign,aVCOwillgenerateasignalattwicethedesignatedcarrierfrequency,whichwillbedivideddownbya2:1frequencydividertotheoutputRFfrequencyofthetransmitter.TheoutputsignalfromVCOwillbeconnectedtothemodulatorforarbitrarydatapatterns,wherefoursignalswhosephasesareinquadraturewithoneanotherwillbegeneratedfromtheVCO'soutputbythe2:1frequencydivider.TheoutputofthemodulatorwillbeanMSK-likemodulatedsignalwithaconstantenvelope,whichallowsfortheuseofasimplelow-costandrelativelynon-linearsucceedingpoweramplier(PA).Itshouldbepointedoutthatnobasebandprocessingisneededinthistransmitterarchitecture.WithaVCOprecedingthemodulator,andaPAfollowingit,themodulatorcanbeeasilyplacedintoadirectconversiontransmitterchain.TheblocksafterthePA,suchastheantenna,areomittedintheblockdiagramandinthedesignaswell.

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Figure5{2. Designeddirectconversiontransmittertobedesignedutilizingtheconstantenvelopephasemodulator narrowbandapplicationswithhighoutputlevelsatlowcost,whereasinductor-capacitor-basedVCOs(LC-VCOs)canprovidegoodperformanceatthelowcostsrequiredbymanyapplications.Inparticular,LC-VCOshavelowerphasenoisethanring-oscillatorVCOs,makingitanecessarydesignchoicewhengoodphase-noiseperformanceclosetothecarrierisrequired. AnLC-VCOisanoscillatorwheretheprincipalvariableortuningelementisavaractorcapacitor.TheVCOistunedacrossitsbandbyaDCvoltage,Vtune,appliedtothevaractortovarythenetcapacitanceappliedtothetunedcircuit.AnLC-VCOtypicallyconsistsofanLCtankandacircuitthatgeneratesanegativeconductanceforcompensatingthelossesintheLCtank.TheLC-VCOcorecircuitisbasedonacross-coupledMOStransistorpair,whichcreatestheeectivenegativeconductance.Thefollowingequationhastobefullledtoachieveoscillationstart-upconditions. whereGmisthenegativeconductance,andRpistheequivalentparallelresistanceoftheLCtank.

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Figure5{3. DesignedCMOSLC-VCO 5{3 .Ituseson-chipinductors(L1andL2)andvaractors(CV1andCV2).TheloadusuallyistheinputofCMOSbuersandhencecapacitive.Figure 5{4 isdrawnbasedontheequivalentcircuitmodelofanCMOSoscillatorin[ 28 ],wherethebrokenlineinthemiddlerepresentseitherthecommonmodeorground.ThesymmetricplanarspiralinductormodelofFigure 5{5 withidenticalRCloadingonbothterminalsisusedasapartofthetankmodel.TheparasiticcapacitanceofinductorsisrepresentedbyCL,whichisequaltoCs+Cp.RsistheparasiticresistanceinserieswithinductanceL.Rprepresentstheshuntresistance

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Figure5{4. EquivalentcircuitmodelofthedesignedCMOSLC-VCO acrosstheportandground.Thequalityfactor(QL)oftheL-RseriescombinationisthengivenbyQL=(!L)=Rs,where!istheoperationfrequency. VaractorsaremodeledwithacapacitorCVinserieswitharesistorRV.TheparasiticcapacitancesfromaMOStransistoraredescribedasCMOS,whichincludesCdb,Cgs,CgbandCgd.TheseriesresistanceRMOSmainlycomesfromthesubstrateresistancesassociatedwithsourceordraintosubstratejunctioncapacitor(CdborCsb)andgatetosubstratejunctioncapacitor(Cgb)[ 29 ].Thequalityfactorforacapacitor,QC,isgivenas1=(!RC),where!istheoperationfrequency,RistheparasiticresistanceinserieswithcapacitanceC.Therefore,largecontact

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Figure5{5. Symmetricspiralinductormodel arraysarenecessarytolowerRMOStoimprovethequalityfactorofCMOS.gmandgoaresmall-signaltransconductanceandoutputconductanceofthetransistors,respectively.

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noise.Moreover,sincethe1=fnoiseisinverselyproportionaltoatransistor'sgatearea,aPMOStransistor,M3,withlargewidthandlength(450m/500nm)isthereforeusedasthetailtransistortoreducetheclose-inphasenoise.Meanwhile,sincePMOStransistor'soverdrivevoltageislowthankstoitslargewidth,itleadstoasmallervoltagedropacrossthetransistor'ssourceanddrainwhenthetransistorisworkinginsaturation.ThisaddstotheadvantagesofusingaPMOStransistorforthetailcurrentsourceinthatitcanleavemoreheadroomfortheVCO'soutputvoltageswing,whichalsohelpsimprovephasenoiseperformance[ 30 ].However,itshouldbepointedoutthat,becauseNMOStransistorshavesmallersizethanPMOStransistorstoachievethesameGm,cross-coupledNMOStransistors(M1andM2)areusedforthenegativeconductancegenerationpartoftheCMOSLC-VCOcircuit,inordertoachievealargertuningrangethanitsPMOScounterpart. ForLC-VCOs,theoverallQoftheLCtankisalsoakeyfactorthatdeterminesthephasenoiseperformance.Normally,theQfactoroftheLCtankisdeterminedbytheinductor.Adierentialspiralinductorwithapolysiliconpatterned-groundshield(PGS)isusedinthisVCOdesigntoachieveahigherQ.ThisisalsoagoodmatchtothedierentialVCOtopology.AlargevalueoftheinductanceL,orasmallC=Lratio,canrelaxtherequirementforthevalueofGm,andhencereducepowerconsumption[ 31 ].Inthiswork,thevalueofLisdesignedtobe880pHfortheoscillatingfrequencyof5GHz.VaractorsareimplementedwithMOScapacitors.AMOStransistorwithitsdrain,source,andbulk(D,S,B)connectedtogethercanrealizeaMOScapacitor,andthevalueofthecapacitance

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Figure5{6. LayoutoftheLC-VCOcircuit

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isdependentonthevoltagebetweenbulk(B)andgate(G),VBG.MOSvaractorshaveanapproximatelysimilartuningrangeandbetterphasenoiseperformancethandiodevaractors[ 32 ].Thevalueforthevaractorswastargetedat800fFforanoscillatingfrequencyof5GHzwithanestimatedtuningrangefrom492fFto1.056pF.Avaractor'stunabilityisdenedtobeCmax=Cmin.Therefore,theestimatedtunabilityofthevaractoris2.15. ThelayoutoftheLC-VCOcircuitisshowninFigure 5{6 .TheVCOisdesignedtooscillateataround5GHz,whichistwicethedesiredLOfrequency.TheoutputoftheVCOwillbeconnectedtoa2:1frequencydivider,whichwasintroducedpreviouslyasoneofthecircuitblocksforthemodulator,togeneratefourLOsignalswithphasesinquadraturewithoneanother.ThesimulationresultofthegeneratedquadratureLOsignalscanbeseeninFigure 5{7 5.3.1BasicCharactericsofaPowerAmplier

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Figure5{7. SimulatedresultoftheoutputofVCOplusdivider amplierpreservesthedetailsofthesignalwaveform,thatistosay,[ 33 ] where,ViandVoaretheinputandoutputsignalsrespectively,andAisaconstantgain.ButifVicontainshigherpower,thentheampliercouldproducenonlineardistortion. Thedraineciencyofapoweramplier(PA)isameasureoftheamplier'sabilitytoconvertthedcpowerofthesupplyintothesignalpowerdeliveredtotheload.Thedenitionofdraineciencyisasfollows:[ 33 ] DCpower:(5{3)

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Ifanidealamplierexists,thepowerdeliveredtotheloadwouldequalthepowertakenfromtheDCsupply.Inreality,anampliereciencyofoneisnotpossible,especiallyinRFcircuits.Inmanyhighfrequencysystems,theoutputstageanddriverstageofanamplierconsumepowerintheamplicationprocess.However,somepowerampliersprovidehighereciencythanothers.Whatkindofpowerampliershouldbedesigneddependsontheapplicationrequirements.Generallyspeaking,linearmodulationsemployamplitudechangetocarrythedatainformation,andhencecanonlyallowforlinearbutnot-so-ecientpowerampliers.However,forconstantenvelopemodulations,powerecientnon-linearampliersisanappealingcandidatebecausesignaldistortionwillnotbeaconcern. 34 ]. However,atrade-obetweentheeciencyandlinearityexistsforPAsofanyclass.Thatis,highereciencymeanspoorerlinearityandviceversa.Forexample,letuscompareclassA,B,andCPAstoseethetrade-o.Amongthethree,the

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Figure5{8. Voltage-currentrelationshipsforvariousclassesofPA class-Aamplierhasthehighestlinearity.Theamplieroperatesinthedevice'slinearregionandisconductingcurrentconstantly,whichmeansmorepowerlossandlowerpowereciency.Anidealclass-Bamplieroperatesatzeroquiescentcurrent,becausetheoutputcurrentisoforhalfofaninputsinusoidalsignalcycle.Thislowersthepowerconsumptionandimprovestheeciency,butthelinearityofthedeviceisdegraded.Inapplicationswherelinearityisnotaconcern,aclass-Campliercanbeagoodchoice.Aclass-Camplierisbiasedsuchthattheoutputcurrentiszeroformorethanhalfoftheinputsignalcycle.Therefore,itseciencywillbeevenhigherthanaclass-Bamplier.ThetheoreticalvaluesforthehighestpossibleeciencyofclassA,B,andCampliersare50%,78%,and100%,respectively.Inpractice,however,aneciencyof100%isimprobablebecausethecurrentcannotbeswitchedocompletely. Thedierentclassesarefurtherdiscussedbelow. 5{8 [ 34 ],whereIpandVDDarethepeakcurrentand

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drainsupplyvoltage,respectively.Thelinearoutputpowercanbemaximizedbyproperloadmatching.DesigningaclassAPAis,inasense,thesameasdesigningasmall-signallinearamplierbecausetheoutputsignalisexpectedtoduplicativelyamplifytheinputsignal.ButaclassAPAoperatesathigherpowerlevelthansmall-signalampliers.Weknowthatmoreoutputpowercanbeobtainedwhenanamplierworksinthesaturationmode.However,theharmonicsanddistortionwillbelesssevereiftheamplierisnotoperatedfarintosaturation.Withtheactivedeviceworkinginthelinearregion,aclassAamplierprovidesthehighestlinearityandalmostexactlythesameoutputwaveformastheinputsignal,althoughitsmaximumdraineciencyislimitedto50%. 5{8 )andtheactivedeviceconductsonlyonehalfofacycle(180)oftheinputsinusoidalsignal.InsteadofobtainingmaximumlinearoutputpowerasinthecaseofclassA,theloadinclassBismatchedtoachievebestgainandmaximumeciencypossible.ClassBRFampliersoftenadoptapush-pullconguration,whichhastwosingle-endedstagesthatsharetheoutputload.Inapush-pullconguration,oneamplierstageonlyoperatesduringthepositivecycleofthesinusoidalwavewhenthetransistorpushescurrentintotheload,andtheotherstageonlythenegativecyclewhenthetransistorpullsthecurrentfromtheload.Thelinearityperformanceofsingle-endedclassBampliersisnotasgoodasclassA.However,theyhavehighereciencybecauseeachdeviceisturnedonforonly

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halfacycleoftheinputsignal.ThemaximumdraineciencyofclassBampliersis78%.

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Figure5{9. Topologyofasingle-endedpoweramplier(classA,B,andC) impedancematchingattheoutputtoterminateharmonicfrequencies,inordertoreducepowerdissipation.Ideally,theoutputcircuitofaclassFampliershouldbedesignedtopresentashortcircuittothesecondharmonicandanopencircuittothethirdharmonic.However,duetothedicultyindesigningmatchingcircuitsoveralargebandwidth,oftentimesonlytheshortatthesecondharmonicisaimedatinpractice.

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(a) (b) Figure5{10. BuerstodrivethePA.(a)Buerfortherstthreestages(b)Buerforthelaststage

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Figure5{11. LayoutofthePAanditsproceedingbuer/driver

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Figure5{12. SimulateddierentialoutputwaveformfromthePA Single-endedclassA,B,andCampliershavethesametopology(Figure 5{9 ),andaredierentiatedbytheirbiasconditions.Thepoweramplierdesignedinthisworkisbiasedbetweensingle-endedclassBandclassCcongurations.ItisnotexactlyaclassCamplierbecausethebiasconditionbordersonthatforaclassBamplier,althoughthegatevoltageisstilllowerthanthedevice'sthresholdvoltage.Thebiasconditionhastobesetinsuchawaythattheoutputsignallevelisacceptable.ThecongurationofthedesignedpoweramplieristhesameastheoneshowninFigure 5{9 .BiasingisdoneattheVbiasnode,andCcplisacouplingcapacitortoAC-couplethesignalfromthepreviousstageofthecircuitandfeeditintothepowerampliergatetogetherwiththebiasDCvoltage.Notethatatunedcircuitatf0oralterisnecessaryforaclassCampliertoreducethesignaldistortioncausedbythehighnon-linearityoftheamplier.

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Inthisdesign,thereareaseriesofbuers,asalsoshowninFigure 5{10 ,betweentheoutputofthemodulatorandtheinputofthepoweramplier,inordertodrivethesignallevelhighenoughfortheampliertosaturate.Thebuertopologyfortherstthreestagesissimilartothatusedinthemodulatordesign,andthelaststageusedtwosingleendedbuerswithinductorloadsinsteadofresistorstofurtherboostupthesignalswingbeforesendingitintothePA.ThelayoutofthePAanditsproceedingbuer/driverisshowninFigure 5{11 SimulationofthewholetransmitterchainshowedaresultofthePA'soutputwaveform,ascanbeseeninFigure 5{12 .Thesimulationwasdonebyapplyingthesamegatebiasvoltage,whichisalittlelowerthanthethresholdvoltageofbothdevices,tothePAanditsproceedingdriver.Thereasonforbiasingthedriverthiswayistoreduceitspowerconsumption. 5{13 .Theareaofthechipis1.094mm2. Thetransmittercircuitwastestedinasimilarwaytothetestingofthemodulatorcircuit,ascanbeseeninFigure 5{14 forthemeasurementsetup.Thesignalgeneratorthatwasusedfortestingthemodulatorcircuitisnotneeded,becausetheRFsignal,whichisatafrequencytwicethedesiredcarrierfrequency,canbegeneratedbytheon-chipLC-VCOcircuit.Thesupplyvoltage,bias

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Figure5{13. Diemicrophotographofthedirectconversiontransmittercircuit voltages,andcontrolvoltage(Vtune)fortheLC-VCOareprovidedbybatteriesinorderforamoresteadyVCOoutput. Therearenostand-alonetestingcircuitsfortwoofthebuildingblocksofthetransmittercircuit,theLC-VCO,andthePAwithitsdrivers.TheLC-VCOandthePAaretheprecedingandsucceedingblocks,respectively,ofthemodulatorcircuitwhichhasbeentestedandintroducedinthepreviouschapter.However,eachblockiscontrolledbyseparatesupplyvoltagesandbiases,andthereforethethreeblockscanbeturnedonsequentiallytoallowustoseethesignalstheygeneratefromthespectrumanalyzer,whichisconnectedthroughanRFprobe

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Figure5{14. Measurementsetupfortestingthetransmittercircuit totheon-chipoutputsignalpads.Itshouldbenotedthat,whenthePAisnotturnedon,thesignalswhichcanbeobservedonthespectrumanalyzer,fromeithertheLC-VCOaloneortheLC-VCOplusthemodulator,arecoupledtotheoutputsignalpadsthroughthesubstrate,becausetherearenorealsignalpathsfromtheLC-VCOorthemodulatortothepads.Figure 5{15 showsthesubstrate-coupledoutputoftheLC-VCOandthemodulator's2:1divider(withnodataorclockappliedtothemodulator). ThetuningrangeofaVCOcanbedenedas Withatuningvoltagebetween-1Vand2.8V,themeasuredtuningrangeoftheLC-VCOthroughsubstratecouplingisfrom4.5GHzto6.3GHz.Therefore,

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Figure5{15. ObservedoutputsignalsthroughsubstratecouplingfromtheLC-VCOat5GHzandthedividerofthemodulatorat2.5GHz wecanroughlyestimatethetuningrangeoftheLC-VCOtobe33.3%orlarger,whichisalittlebetterthanthe10-30%typicaltuningrangeforCMOSLC-VCOs[ 29 ].SincetheoscillatingfrequencyofanLC-VCOisinverselyproportionaltothesquarerootofthecapacitorvalueoftheLCtank,themeasuredoperatingfrequencyrangeoftheLC-VCOincursatunabilityof1.96forthevaractorusedintheLC-VCOdesign,whichisslightlylowerthantheestimatedvaluewhendesigningtheLC-VCO.Butconsideringthatthemeasuredfrequencyrangeisobtainedbasedonthesignaldetectedthroughsubstratecoupling,thistunabilityvalueisinlinewiththesimulationresult. WiththeLC-VCOtunedataround5GHz,thecarrierfrequencyis2.5GHzforthemodulatorandtheentiretransmitter.Applyingdataandclockatdierent

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Figure5{16. Measuredpowerspectrumofthetransmittercircuitat2.5GHzcarrierfrequencyand12Mbpsbitrate ratestothemodulator,andbiasingthePAatagate-to-sourcevoltageslightlyhigherthanthedevice'sthresholdvoltage,thetransmittercircuit'soutputsignalspectraatdierentdataratescanbeobservedandrecordedfromthespectrumanalyzer.Figures 5{16 5{17 5{18 5{19 ,and 5{20 showthepowerspectraoftheoutputsignalat12Mbps,25Mbps,37.5Mbps,50Mbps,and100Mbpsbitrate,respectively. Thecalibratedoutputsignalpowerlevelofthetransmittercircuitat2.5GHzcarrierfrequencyisaround3dBm.ThecurrentdissipationsoftheLC-VCO,themodulator,andthePAwithitsdriversare11mA,2mA,and59mArespectively.Thesupplyvoltagesforthecomposingblocksareall1.8V.Therefore,thepowerconsumptionoftheentiretransmittercircuitis129.6mW.Thetransmitter'soutputRFpowerlevelwithinthefrequencyrangeof2.3GHzto3GHzis

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Figure5{17. Measuredpowerspectrumofthetransmittercircuitat2.5GHzcarrierfrequencyand25Mbpsbitrate Figure5{18. Measuredpowerspectrumofthetransmittercircuitat2.5GHzcarrierfrequencyand37.5Mbpsbitrate

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Figure5{19. Measuredpowerspectrumofthetransmittercircuitat2.5GHzcarrierfrequencyand50Mbpsbitrate Figure5{20. Measuredpowerspectrumofthetransmittercircuitat2.5GHzcarrierfrequencyand100Mbpsbitrate

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Figure5{21. OutputRFpowerlevelofthetransmittercircuitvs.carrierfrequency plottedinFigure 5{21 .ThedraineciencyofthePAisnothigh,althoughahigheciencynonlinearPAwouldsuitthecircuitverywellthankstotheconstantenvelopemodulatoroutput.TheprobablereasonsforPA'sloweciencyincludehighbiasvoltageappliedatthegateofboththePAanditsdriverstoboostupthesignallevel,theunder-estimatedparasiticsofthecircuit,andtheover-estimatedoutputsignalpowerlevelfromtheVCOandthemodulator.AlthoughthePAdesignisnotoptimized,itservesthepurposeofamplifyingthemodulator'soutputsignallevelandpreservingthespectrum.Moreimportantly,wehavesuccessfullydemonstratedthatthemodulatorcanbeeasilyintegratedintoatransmittersystemandworksne. Table 5{2 brieysummarizestheperformanceofthedirectconversiontransmittercircuit.

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Table5{1. Performancesummaryofthedirectconversiontransmitter Itshouldbepointedoutthat,unlikethemeasurementofthemodulatorcircuit,thetransmitteroutput'sconstellationandI/Qdiagramwerenottested.Thereasonisthatthephaseofafree-runningVCOisnotxedbutratherconstantlychanging.Hence,thecorrectnessofthefourLOsignals'sphasecannotbeguaranteed.Thereforeacleanandnicesignalconstellationisveryunlikely.However,aswehaveshowninthepreviouschapters,iftheoutputoftheLC-VCOisreplacedbythesignalgeneratedbyasynthesizer,themodulatorcircuitisabletoproducefairlyaccuratelymodulatedsignals.Moreover,becauseoftheconstantenvelopefeatureofthemodulator'soutputsignal,thepoweramplierwillnotdegradethemodulation,whichisembodiedinthesignal'sphaseratherthanitsamplitude.Therefore,webelievethatthetransmittercanproduceanampliedsignalwithgoodmodulationaccuracywhenthephaseofthefree-runningLC-VCOislocked,whichisinpracticeoftentimesthecasewithapplicationstransceivers.

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Figure5{22. Directconversiontransmittertobedesigned designedtransmittersarethesameastheoneshownintheblockdiagraminFigure 5{22 .ThedierenceliesinthequadratureLOgeneratingcircuit. TwocommonlyusedmethodstogeneratequadratureLOsignalsfromvoltagecontrolledoscillatorsareVCOplusafrequencydividerandquadratureVCO.ComparativestudyhasshownthatthetopologyofaVCOplusadividerperformsbetterintermsofphasenoise[ 35 ],andisbetteratmitigatingtheproblemofLOpullinginadirectconversiontransmitter[ 36 ].Thersttransmitterwhichwasintroducedearlierinthischapterusedthismethod,i.e.,aVCOattwicethedesiredLOfrequencyplusa2:1frequencydivider. AnothertopologyforgeneratingquadratureLOsignalsisaquadratureVCO(QVCO)circuit.ThismethodreliesondirectquadraturegenerationattheoutputoftheQVCO,whichoperatesatthedesiredfrequencywithoutotheraccompanyingcircuitcomponents.Thesecondtransmitterusedthismethod.WewillnowintroducethedesignoftheQVCOrst,andthenpresenttheexperimentalresultsofthedirectconversiontransmitterusingtheQVCOcircuit. 5{23 .VCO2isconnectedtoVCO1

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Figure5{23. QuadratureVCO Figure5{24. DesignedLC-QVCO inanti-phase,whileVCO1isconnectedtoVCO2incommonphase.Thisyieldsa180-degreedelayinphasefromVCO2'soutputtoVCO1'sinput,forcingthetwoVCOstosynchronizesuchthatthephasedelayineachisexactly90degrees,assumingtheyareidentical.EachoscillatorcorehasbeendesignedasabasicfullydierentialLC-VCO,andtheoverallcircuittopologyfortheQVCOcanbeseeninFigure 5{24 TheQVCOisbasedonthecross-couplingoftwodierentialLC-VCOs.IneachLC-VCOcore,thecouplingtransistors(M3andM4)areplacedinparallelwiththeswitchtransistors(M1andM2).InsuchQVCOs,bothphasenoiseand

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Figure5{25. LayoutoftheLC-QVCO

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phaseerrorarestrongfunctionsof,denedastheratioofthewidthofthecouplingtransistorstothewidthoftheswitchtransistors[ 37 ].StudyhasshownthatthephaseerrorgetsquicklylargerwhenthecouplingbetweenthetwoVCOsisweakenedbydecreasing.Ontheotherhand,thephasenoisegreatlydecreaseswithadecreasing[ 37 ].Therefore,improvingthephasenoiseperformanceofaQVCOwillbeattheexpenseoftheQVCO'sphaseerrorperformance.InthisQVCOdesign,phaseerrorisalsoacriticalfactorwhichcanaectthemodulator'saccuracy.Besides,simulationshaveshownthattheQVCO'soutputvoltageswingisthebiggestwhenequals1/2.Withallthistakenintoaccount,thewidthsofthecouplingtransistorsandswitchtransistorsaredesignedtobe108mand216m,respectively. TheQVCOwasdesignedtooscillateataround2.5GHz.Accordingly,thevalueoftheinductorswaschosentobe3nH,andthevaractorsweredesignedtobe1.1pFwithanestimatedtuningrangefrom677fFto1.452pF.ThelayoutoftheLC-QVCOisshowninFigure 5{25 .ThesimulationresultofthegeneratedquadratureLOsignalscanbeseeninFigure 5{26 .TheblockdiagramofthedirectconversiontransmitterutilizingsuchaquadratureLOgenerationcircuittopologyisshowninFigure 5{27 .ItcanbeseenthatthearchitectureofthetwotransmittersarealmostthesameexceptforthataQVCOreplacedtheVCOplusdividertopologyinthesecondtransmitter.

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Figure5{26. SimulatedresultofthequadratureLOsignalsgeneratedbytheQVCO Figure5{27. BlockdiagramofthedirectconversiontransmitterutilizinganLC-QVCO

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Figure5{28. Diemicrophotographofthedirectconversiontransmittercircuit 5{28 showsthediemicrophotographofthetransmittercircuitusingaQVCO.Theareaofthechipis1.256mm2.ThemeasurementsetupisalmostthesameasillustratedinFigure 5{14 Withatuningvoltagebetween-1Vand2.8V,themeasuredfrequencyrangeoftheQVCOthroughsubstratecouplingisfrom2.33GHzto3.1GHz.Therefore,wecanroughlyestimatethetuningrangeoftheLC-VCOtobe28.36%orlarger,whichiswithinthe10-30%typicaltuningrangeforCMOSLC-VCOs[ 29 ].ThemeasuredoperatingfrequencyrangeoftheLC-VCOincursa1.77orhighertunabilityforthevaractorusedintheLC-VCOdesign.

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Thecalibratedoutputsignalpowerlevelofthetransmittercircuitat2.6GHzcarrierfrequencyis1dBm.ThecurrentdissipationattheLC-QVCO,themodulator,andthePAwithitsdriversare10mA,2mA,and58mArespectively.Thesupplyvoltagesforthecomposingblocksareall1.8V.Therefore,thepowerconsumptionoftheentiretransmittercircuitis126mW. Figures 5{29 5{30 ,and 5{31 showthepowerspectraoftheoutputsignalat12Mbps,25Mbps,and37.5Mbpsbitrate,respectively.ItcanbeseenthatthedirectconversiontransmitterusingaQVCOhasaLOleakageproblemwhichisquiteobviousatadatarateof37.5Mbpsorhigher.ThisisprobablybecausetheoperatingfrequencyoftheQVCOandthatofthePAareinthesamerange,whichisoneofthedrawbacksofsuchdirectconversiontransmitters.ThepreviouslyintroducedtransmittercircuitusesaVCOwhichoperatesattwicethecarrierfrequency,andhenceitcanalleviatetheLOdisturbancecausedbythePAtosomeextent. Table 5{2 brieysummarizestheperformanceofthedirectconversiontransmittercircuitusingaQVCO. Table5{2. PerformancesummaryofthedirectconversiontransmitterusingaQVCO

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Figure5{29. MeasuredpowerspectrumofthetransmittercircuitusingaQVCOat2.56GHzcarrierfrequencyand12Mbpsbitrate Figure5{30. MeasuredpowerspectrumofthetransmittercircuitusingaQVCOat2.56GHzcarrierfrequencyand25Mbpsbitrate

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Figure5{31. MeasuredpowerspectrumofthetransmittercircuitusingaQVCOat2.56GHzcarrierfrequencyand37.5Mbpsbitrate Thedigitallycontrolledphaseshiftmodulatorcanbeeasilyintegratedintobothtransmittersystems.ComparedtothetransmitterutilizingaQVCOtogeneratethefourquadratureLOsignalsthemodulatorneeds,thetopologyofaVCOplusafrequencydividerprovestomitigatetheLOleakageproblem.Butineithersystem,themodulatorcircuitfunctionswellandrequiresnobasebandprocessingfordata.

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Inthepreviouschapters,wedemonstratedtheconstantenvelopemodulationfunctionofthemodulatorcircuit,anditssuitabilityforaZigBeeradiocompliantwiththeIEEE802.15.4standard.Wealsopresentedthatthemodulatorcaneasilybeintegratedintoasimpledirectconversiontransmitter,whichcouldbeagoodchoiceforpersonalareanetworks.However,whetherinastand-alonetestchiporintegratedinadirectconversiontransmitter,themodulatorcircuitisdesignedtorealizeanMSK-likemodulationonly.Nowweaddressthesoftwarerecongurabilityofthemodulator.Thankstothephasorcombiningapproachandthecircuittopologydesignedbasedonthisapproach,amodulatorcircuitcore,whichcanbecontrolledbyperipheralsignalsonacircuitboard,canbesimilarlydesignedinaneorttogeneratesomedierentmodulationschemes.Thegoalofbuildingasoftwarecongurableboard-levelmodulatoristoroughlydemonstratetheapplicabilityoftheproposedmodulatorforasoftwaredenedradio. 6{1 retellstheprincipleoftheapproach,whichsimplysaysdierentphases()and/oramplitudesofVoutcanbegeneratedfrom 110

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Figure6{1. Phasorcombiningapproach twophasors(V1andV2)inquadraturebyapplyingdierentsummingweights(aandb). Recallthat,amongthebuildingblocksofthemodulatorcircuit(Figure 4{4 ),thetwo4:1multiplexersselectandprovidetwophasorsinquadratureinthecorrectquadrant,andthesummingcircuit(Figure 2{4 )usesthetwobiascurrents(I1andI2)toweighV1andV2respectivelyinordertoproducethedesiredoutputphasor(Vout).Therefore,theimplementationofsoftwarecontrolovertheoutputphasoraccordingtothedesiredmodulationtakesplacewiththebiascurrentsourcesforthesummingcircuit. IntheoriginalICdesignfortheMSK-likemodulator,fourphasors(P0,P1,P2,andP3)needtobegeneratedwithineachbitinterval,oreachquadrantontheI/Qplane.ItwasrealizedbydigitallygeneratingfourdierentcombinationsofcurrentsourcesasfourdierentsetsofweightsforV1andV2.AscanbeseenfromFigure 6{2 ,digitalcontrolsignalsareappliedtothethreeswitchesrepeatedly

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Figure6{2. ImplementationofsoftwarecontrolforMSKmodulation overthebitintervals.Eachbitintervalisdividedintofoursubintervals(t0,t1,t2,andt3),eachforonephasor(P0,P1,P2,andP3,respectively).Thetwobiascurrents(I1andI2)forthesummingcircuittakeondierentvaluesduringthefoursubintervals,thankstotheswitchesturningonorothecurrentsources(Ib1,Ib2,andIb3),andhencegeneratethefourdierentphasorsinVout. Figure6{3. ConstellationofanOQPSKsignal

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Asintroducedearlier,theMSKmodulationschemecanberegardedasthederivationofOQPSK,inthatthesquarepulseshapeinOQPSKisreplacedbythehalfsinepulseshapeinMSK.ThesquarepulseshapeinOQPSKresultsinnon-continuousphaseshiftwithineachbitinterval.Asamatteroffact,thephaseofthemodulatedsignalremainsconstantforonebitinterval,anditcouldeitherremainconstantorjumpby90forthenextbitinterval,dependingonthedatacombinationofthetwochannelsforthenextbitinterval.Thus,theconstellationofanOQPSKsignalshowsfoursignalpoints,oneineachquadrantand90apartfromoneanotherinphase.TheconstellationanditssymbolsforanOQPSKsignalisshowninFigure 6{3 Figure6{4. IllustrationofhowthecorrectquadrantscanbeselectedbythemultiplexersforOQPSK ItisstraightforwardtoimplementtheOQPSKmodulationschemeusingthesamearchitectureastheMSK-likemodulator.Themodicationwillmainlytakeplacewiththebiascurrentsforthesummingcircuitstoimplementsoftware

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Figure6{5. Modulatorcorecircuit control.Morespecically,insteadoffourdiscretephasorsperquadrant,onlyonephasorneedstobegeneratedforeachbitinterval.Therefore,thevaluesofthesummingcircuit'sbiascurrentsI1andI2canbexedandequalatalltimes.Thus,aslongasthecorrectquadrantisselectedbythetwomultiplexers,theresultingoutputsignalwillbethedesiredphasorinthequadrant.Figure 6{4 explainshowthemultiplexerscanguaranteethatthecorrectquadrantsbeselectedaccordingtothedatabits.Itcanbeseenthat,foreachbitinterval,thetwooutputsfromthemultiplexersaretwophasorsinquadratureconstitutingthecorrectquadrantontheconstellation.Itshouldbenotedthattheparallel2-bitdatasymbolsinparenthesisareonlyincurredbythe90bitstreamosetontheIchannel(withoutlossofgenerality),theydonotcontainrealdatainformation. Basedontheseconsiderations,amodulatorchiptobeusedasthecorecircuitonthecircuitboardwasdesignedandfabricatedintheTSMC0.18mCMOS

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Figure6{6. Diemicrophotographofthemodulatorcorecircuit process.Thedesignbasicallyconsistsofthetwo4:1multiplexers,thesummingcircuit,andsomedigitalcontrolcircuitfordataandclocks.However,thesummingcircuit'sbiascurrentswillbeprovidedbycurrentsourcesbuiltoncircuitboard,becauseitwillmakeiteasiertochangethecurrentsandhencetheoutputphasor.TheblockdiagramandthediephotoofthemodulatorcorecircuitisshowninFigure 6{5 andFigure 6{6 ,respectively. Ascanbeseenfromthediephoto,besidestheDCsuppliesandbiases,thecorecircuitneedsfourquadratureLOinputsignalsataround2.5GHz,fromwhichthetwo4:1on-chipMultiplexerswillselectthecorrectpairofquadraturephasorsV1andV2.Italsoneedsclockanddatainputtoperformmodulation.ThetwopadslabeledI1andI2arewhattheo-chipcontrolcurrentsforthesummingcircuitwillowthrough.Thedierentialoutputsignalwillbethegeneratedoutputphasor(Vout). Theprintedcircuit(PC)boardwasdesignedbasedonthespecicationsoftheFR4boardprovidedbyAdvancedCircuits.Specically,r=4.5,TanD=0.018

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Figure6{7. UsingLinecalctocalculatethewidthofmicrostriptransmissionlineonanFR4board (ataround2GHz),H=62mil(1.6mm),andT=2.1mil(0.053mm).TheinputsignalsthatthecorecircuitneedsincludethefourquadratureLOsignalsatthefrequencyofaround2.4GHz,anddataandclockfeed-insatuptoseveralhundredmegahertz.ThedierentialoutputsignalwillbeatthesamefrequencyastheLOsignals.Therefore,transmissionlinesareneededforthetransmissionoftheseinputandoutputsignals.UsingLinecalcinADS(Figure 6{7 ),thewidthofthemicrostriptransmissionlinewascalculatedtobearound2.9mmbasedonthespecicationsoftheFR4board.AsfortheDCsupplyandbiasvoltages,on-boardbypasscapacitorsneedtobeshuntedbetweenthemandground. ThePCboardwasdesignedusingProtel.Itisatwo-layerboard(topandbottom)withvias.thelayoutoftheboardisshowninFigure 6{8

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Figure6{8. LayoutoftheprintedcircuitboarddesignedinProtel Figure 6{9 showsthebondingdiagramofthecircuit.Ballbondingwasperformedtowirebondthecorecircuitchiptotheboard.Becausethetoplayermetaliscopper,whichcaneasilyoxidize,bondingwasdonebyplacinggoldbondballsontopofeachbondpadsontheboardwhilethecopperhasnotoxidizedyet.Thus,theballshaveabetterchancetostickonthepads.Then,goldbondwirescanbeplacedtoconnectthealuminumpadsonthecorecircuitchipandthegoldballsonthebondpadsoftheboard.Figure 6{10 showswhatthebondedchiplookslikeontheboard. 6{11 .Thedimensionoftheboardis2.58inchby2.36inch. Figure 6{12 showsthemeasurementsetupfortestingthemodulatorboard.ThesignalgeneratorprovidesanACsignalatthedesiredcarrierfrequency,orLOfrequencyforthemodulator.The90balunandthepairof180balunsare

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Figure6{9. Bondingdiagramforthecorecircuitchip Figure6{10. PhotoofthebondedchiponthePCboard Figure6{11. PhotoofthecompletedPCboard

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Figure6{12. Measurementsetupfortestingthemodulatorboard Figure6{13. Schematicoftheboard-levelcurrentsource Figure6{14. PhotoofthecurrentsourcetestboardforOQPSKmodulation

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connectedtogeneratefourLOsignalsinquadraturewithoneanother.ThesefoursignalsarefedintothemodulatorcircuitthoughthefourLOinputs.AgilentN4906Abiterrorratetester(BERT)isusedtoprovidethecircuitwithdataandclockinputs.Themodulator'sdierentialoutputsignalismeasuredbyterminatingoneendwith50andconnectingtheotherendtoaspectrumanalyzer. Theexternalcontrolcurrentsourcesarebuiltonabreadboardusingdiscretetransistorparts.Becausetheboard-levelmodulatormaintainsthesamecircuitarchitectureastheintegratedmodulatorcircuit,emphasiswasplacedongeneratingOQPSKmodulationintestingtheboard,becausetheMSKmodulationfunctionofthecircuithasbeendemonstratedearlieron.ForOQPSK,onlytwocurrentsourceswithequalcurrentvaluesareneededtobiasthesummingcircuit.KN2222/AepitaxialplanarNPNtransistorsand100kpotentiometerswereusedtobuildthecurrentsources.TheschematicofacurrentsourceisshowninFigure 6{13 ,andthephotoofthecurrentsourcetestboardsisshowninFigure 6{14 ThetheoreticalpowerspectrumofanOQPSKsignalisplottedinFigure 6{15 .Themeasuredoutputspectrashowedveryconsistentresults,ascanbeseenfromFigure 6{16 Figures 6{17 6{18 ,and 6{19 showthemeasuredoutputspectraatthecarrierfrequencyof0.5GHz,1GHz,and3GHz,respectively,withadatarateof24Mbps(minimumdatarateavailablefromtheBERT).Figures 6{20 6{21 ,and 6{22 arethemeasurementresultswhenthecarrierfrequencywassetto2.4GHz,whilethedataratewas40Mbps,80Mbps,and100Mbps,respectively.Theresolutionbandwidthofthespectrumanalyzerwassetto3MHzforallthemeasurement

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Figure6{15. TheoreticalpowerspectrumofOQPSK Figure6{16. Consistentmeasurementresultwiththeoreticalspectrum results.ForgeneratingOQPSK,thecurrentdissipationofthewholemodulatorcircuitboardis15mA,andthesupplyvoltageis1.8V. Themodulatorboardusesacorecircuitthathasthesamearchitectureexceptthattheon-chipimplementationofsoftwarecontroloverthecurrentsources,whichwasintroducedintheprevioussection,wasremovedfromthecorecircuit.Theexactsamecircuitrycanbebuiltonboardusingdiscretetransistorparts,andevenmorephasorsperquadrant,e.g.,8or16,canbepossiblycreatedby

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Figure6{17. Measuredoutputspectrumat0.5GHzcarrierfrequencyand24Mbpsdatarate Figure6{18. Measuredoutputspectrumat3GHzcarrierfrequencyand24Mbpsdatarate

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Figure6{19. Measuredoutputspectrumat3.7GHzcarrierfrequencyand24Mbpsdatarate Figure6{20. Measuredoutputspectrumat2.4GHzcarrierfrequencyand40Mbpsdatarate Figure6{21. Measuredoutputspectrumat2.4GHzcarrierfrequencyand80Mbpsdatarate

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Figure6{22. Measuredoutputspectrumat2.4GHzcarrierfrequencyand100Mbpsdatarate Figure6{23. Comparisonofthepowerspectrafordierentnumberofphasorsperquadrant

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generatingmorecombinationsofbiascurrentsources.Themorephasorsthereareperquadrant,theclosertheoutputspectrumwillbetothetheoreticalpowerspectrumofMSK(Figure 6{23 ).BecausetheMSKmodulationfunctionhasbeendemonstratedbytheintegratedcircuitpresentedearlier,itisreasonabletoinferthatthemodulatorcircuitboardiscapableofgeneratingMSKmodulationaswell.Hence,themodulatorcircuitboardcanbeusedtodemonstratethesoftwarerecongurabilityofthemodulator.

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TwotestmodulatorcircuitsrealizinganMSK-likemodulationschemebasedonthephasorcombiningapproacharedesignedandfabricatedusingtheTSMC0.18mmixed-modeCMOStechnology,onewithaxeddatapattern,theotherforarbitrarydatapatterns.Theexperimentalresultsshowthat,comparedtoconventionalmodulatorofthesimilarfunctions,modulatorcircuitsbuiltusingthephasorcombiningapproachhavetheadvantagesoflowpowerconsumption,highdatarate,broadoperatingfrequencyrange,andlesscircuitcomplexityintermsofnecessaryaccompanyingcircuitcomponentsforfunctionandperformancepurposes.Forexample,thesummingapproachreplacessignalmixingandhencerelaxestherequirementforimagerejectionandharmonicltering.Also,itreducestheburdenofbasebandprocessingonthedigitalcircuitsector.Thus,ifthemodulatoristo 126

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beusedinasoftwaredenedradio,inwhichitneedstobeabletogenerateseveraldierentmodulationschemes,thebasebandprocessingforthedierentschemescanbegreatlysimplied.Anotherpointworthmentioningisthat,themodulatorcircuitcanbecometailor-madeforaZigBeeradioorsomeotherdevicecompliantwithIEEE802.15.4,mainlythankstoitslowpowerconsumptionandMSKmodulationfunction.Itshouldbenotedthat,althoughonlyfourdiscretephasorsaregeneratedforeachbitintervalwhiletheidealMSKmodulationtakesaninnitenumberofthem,thepowerspectrumcanmatchthetheoreticalspectrumevenbettersimplybyincreasingthenumberofphasorsperquadrant,asshowninFigure 6{23 inthepreviouschapter. Themodulatorcircuithaslessneedforimagerejectionandltering,andhenceahigherlevelofintegrability.Itcaneasilybeintegratedintoatransmitterchain,wherethetransmitterarchitecturecanbeeitherdirectconversionorindirectupconversion.Asamatteroffact,themodulatordesignwasemployedinbotharchitecturesassummarizedinthefollowing,andthetestingresultsforbothtransmittersprovedthefunctionalityandintegrabilityofthemodulatorcircuit. ThedesignofadirectconversiontransmitterusingtheTSMC0.18mmixed-modetechnology,whichutilizesthemodulator,andtheexperimentalresultsarepresentedasoneoftheapplicationsofthemodulator.Becausethemodulatorrealizesaconstantenvelopephaseshiftmodulation,itallowsfortheuseofapower-ecientnonlinearpoweramplierinatransmitter,whichmakesthetransmitteragoodchoiceforsomelowpowerwirelesscommunicationapplications.Forexample,thetransmitterdesignintroducedinthedissertationcanbeapplied

PAGE 143

foraZigBee-readypersonalareanetwork,orsomeothersimilarwirelessnetworksorsensornetworks.IthastheadvantagesofhigherdatarateandlowerEVMthanthenormalspecicationsforsuchnetworks. ThemodulatordesignwasalsoappliedtotheNodesystemdevelopmentcarriedoutbytheSIMICSresearchgroupattheUniversityofFlorida.TheNodeisatruesinglechipradioincorporatingon-chipantennas,atransceiver,adigitalbasebandprocessor,asensor,andpotentiallyevenabattery.ItisbeingdevelopedusingstandardCMOStechnologyandintendedtobecapableofwirelesstransmissionandreceptionat24GHzovershortdistances.ItcanalsobeviewedasamodiedZigBeeradiooperatedat24GHz.Figure 7{1 showsthesimpliedNodeRFsubsystemblockdiagram,inwhichthehighlightedblockistheindirectup-conversiontransmitter.The24GHztransmitter,whichutilizestheconstantenvelopeMSK-likemodulatorattheIFfrequencyof2.7GHz,wasdesignedandfabricatedintheUMC0.13mLogicCMOSprocess.Themeasuredoutputpowerspectrumat100MbpsdatarateandI/Qplaneconstellationat12MbpsdatarateareshowninFigure 7{2 [ 38 ]. Inadditiontoitsapplicabilityforwirelesscommunicationtransmitters,themodulatorcircuit'srecongurabilitywasalsoaddressedanddemonstratedbythedesignandtestingofacircuitboardutilizingthecorecircuitofthemodulator,whichwasfabricatedintheTSMC0.18mprocess.Byslightlymodifyingthecongurationofthebiascurrentsforthesummingcircuit,anOQPSKmodulationwasimplemented,whichmakesthemodulatorsuitableformanymorewirelesscommunicationapplicationswhereconventionalI/Qmodulatorsarenormallyused.

PAGE 144

Figure7{1. SimpliedNodeRFsubsystemblockdiagram Figure7{2. Measuredoutputpowerspectrum(100Mbpsdatarate)andconstellation(12Mbpsdatarate)around24GHz

PAGE 145

Insummary,theconstantenvelopephaseshiftmodulatorusingthephasorcombiningapproachhasbeendemonstratedtoworkforanMSK-likemodulation.Itconsumesverylowpowerandhasgoodmodulationaccuracy.ComparedwithconventionalI/Qmodulators,theproposedmodulatorhastheadvantagesofrelaxedrequirementsforimagerejectionandltering,broaderoperatingfrequencyrange,andhigherdatarate.Themodulatorismostappealingandpromisinginthattheconceptbehindit,whichhasbeenveriedbyexperimentresults,canbeutilizedtogeneratedierentmodulationschemes.Forexample,GMSKmodulationgeneratesasignalwhosephasechangealsofollowsasimilarbutmorecomplicatedpatternthanMSK.Thus,itispossibletoimplementthephasechangepatternofGMSKsothattheconventionalbasebandcircuitforGaussianlteringorpulseshapingwillnolongerberequired.Moreover,foranyarbitrarymodulations,onlyanitenumberofstepsbetweenphasechangesisneeded,aslongastheoutputpowerspectrumcanmeettheapplication-specicrequirements.Therefore,asmentionedearlier,themodulatorhasabroadapplicationprospect.Itcanbeusedinlowpowertransmitters,especiallythoseintegratedwithwirelesssensors.Itisalsoagoodchoiceforapersonalareanetwork.Moreimportantly,duetoitsdigitalcontrolnatureandpotentialforimplementingdierentmodulationssuchasQAM,themodulatorwouldbewellsuitedforasoftwarecongurableradio.

PAGE 146

7{3 conceptuallyillustrateshow,ina4phasorsperquadrantcase,thecorrectvaluesofI1andI2canbeprovidedinordertogenerateaparticularphasor.Withoutlossofgenerality,inthisexample,IP0producesaweightthatisproportionaltocos0,IP1producesaweightproportionaltocos22.5,orsin67.5,IP2cos45,andIP3cos67.5.Therefore,peripheraldigitalcircuitneedstobebuilttorealizethisscheme,whilesynchronizationtobitintervalsisalsoakeyconsiderationtobeaccommodated.Additionalcircuitrycanbebuilttoequipthemodulatorboardwiththeabilityofswitchingbetweenthetwomodulationschemeswithease,forexample,atthepressingofabutton. Basedonthiswork,anewmodulatortestboardforthepurposeofgeneratingmoremodulationschemescanbedesignedandbuilt.TheimplementationofthesemodulationswillutilizethesamedesignprinciplebutrequiredierentphasechangepatternsanddierentmagnitudeofthephasoraswellforthecaseofQAM.AmodulatorcorecircuitchipforthispurposehasbeendesignedandfabricatedusingtheUMC90nmLogicCMOSprocess,andcanbeplacedonthenewtest

PAGE 147

Figure7{3. HowthecorrectvaluesofI1andI2canbeprovidedforaphasor board.Figure 7{4 showsthediephotoofthecorecircuitchip.Thearchitectureofthemodulatorcorecircuitisthesameaspreviouslyintroduced,andthemaindierenceliesinthatone-stage4:1multiplexersaspublishedin[ 15 ]areusedinsteadofthetwo-stageones.Thereasonforusingtheone-stage4:1multiplexersisthatitallowsforeasierselectionofthecorrectquadrantwhichthemodulatedsignalshouldfallsin,accordingtothedatabits. Controlswillmainlybeappliedovertheclockingofthemultiplexersandthegenerationofbiascurrentcombinationsforthesummingcircuit.Themultiplexersneedtobeclockedinordertoselectthecorrectquadrantsontheconstellation,andthephasorcombiningcircuitwillrelyonitstwobias/weightingcurrentsourcestoproducethecorrectphaseand/oramplitudeonthesignalconstellation.Itshouldbepointedoutthat,forthisnewcorecircuit,currentsourcesandtheirswitchesareallintegratedonthechip,butbiasingthecurrentsourcesandturningon/o

PAGE 148

Figure7{4. DiephotoofthemodulatorcorecircuitusingUMC90nmtechnology theswitchesarestilltoberealizedbyDCvoltagesandcontrolsignals,respectively.Again,thesecontrolsaretoberealizedochipbydigitalcircuitsorusinghighspeedmicroprocessorapplications.TheresultingmodulatorcircuitboardwillhopefullybeabletoaccommodatedierentmodulationssuchasQPSK/OQPSK,MSK,andQAM.

PAGE 149

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[12] M.Chongcheawchamnan,K.S.Ang,D.Kpogla,S.Nam,S.Lucyszyn,andI.D.Robertson,\Low-costmillimeter-wavetransmitterusingsoftwareradiotechniques,"inIEEEInternationalMicorwaveSymposiumDigest,June2000,pp.1949{1952. [13] S.Rajagopal,S.Rixner,andJ.R.Cavallaro,\Aprogrammablebasebandprocessordesignforsoftwaredenedradios,"inMidwestSymposiumonCircuitsandSystems,Aug.2002,pp.III{413{III426. [14] J.SavojandB.Razavi,High-SpeedCMOSCircuitsforOpticalReceivers,KluwerAcademicPublishers,2001. [15] D.KehrerandH.Wohlmuth,\20-Gb/s82mwone-stage4:1multiplexerin0.13mCMOS,"inEuropeanSolid-StateCircuitConferenceESSCIRC2003,2003,pp.385{388. [16] D.Kehrer,\Highspeedwirelessbuildingblocks,"inIEEERadioFrequencyIntegratedCircuitsSymposiumWorkshop,2004. [17] S.Pasupathy,\Minimumshiftkeying:aspectrallyecientmodulation,"IEEECommunicationsMagazine,vol.17,no.4,pp.14{22,July1979. [18] J.Proakis,DigitalCommunications,McGraw-HillScience/Engineering/Math,4thedition,Aug.2000. [19] E.H.Callaway,WirelessSensorNetworks:ArchitecturesandProtocols,AuerbachPublications,2002. [20] U.SinghandM.Green,\Dynamicsofhigh-frequencyCMOSdividers,"inProceedingsofInternationalSymposiumonCircuitsandSystems,2002,vol.5,pp.V{421{V{424. [21] G.Gerosa,S.Gary,C.Dietz,P.Dac,K.Hoover,J.Sanchez,P.Ippolito,N.Tai,S.Litch,J.Eno,J.Golab,N.Vanderschaaf,andJ.Kahle,\A2.2W,80MHzsuperscalarRISCmicroprocessor,"IEEEJ.Solid-StateCircuits,vol.29,no.12,pp.1440{1454,Dec.1994. [22] IEEE,SupplementtoIEEEstandardforInformationTechnology-TelecommunicationsandInformationExchangebetweenSustems-LocalandMetropolitanAreaNetworks-SpecicRequirementsPart11:WirelessLanMediumAccessControl(MAC)andPhysicalLayer(PHY)Specications:Higher-speedPhysicalLayerExtensioninthe2.4GHzBand,Piscataway,NewJersey,1999. [23] W.Kong,C.Ye,andH.C.Lin,\A2.4GHzfullyCMOSintegratedRFtransceiverfor802.11bwirelessLANapplication,"inProceedingsofIEEERadioandWirelessConference,Sept.2004,pp.475{478.

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[24] Y.ZhouandJ.Yuan,\A1GHzCMOScurrent-foldeddirectdigitalRFquadraturemodulator,"inIEEERadioFrequencyIntegratedCircuitsSympo-sium,June2005,pp.25{28. [25] IEEE,WirelessMediumAccessControl(MAC)andPhysicalLayer(PHY)SpecicationsforLow-RateWirelessPersonalAreaNetworks,NewYork,NewYork,2003. [26] K.T.Le,\Designingazigbee-readyieee802.15.4-compliantradiotransceiver,"Nov.2004,www.chipcon.com/les/411rfdf4.pdf. [27] B.Razavi,RFMicrolectronics,PrenticeHallPTR,1997. [28] D.HamandA.Hajimiri,\Conceptsandmethodsinoptimizationofintegratedlcvcos,"IEEEJ.Solid-StateCircuits,vol.36,pp.896{909,June2001. [29] Z.Li,RadioFrequencyCircuitsforTunableMulti-BandCMOSReceiversforWirelessLANApplications,Ph.D.dissertation,UniversityofFloirda,Gainesville,Florida,2004. [30] Z.Hua,J.Zhang,D.Zhou,J.Liu,L.Jiang,andY.Pan,\Aclosed-formphasenoisesolutionforanidealLCoscillator,"inProceedingsofISCAS'04,May2004,vol.4,pp.768{771. [31] C.-M.Hung,InvestigationofaMulti-GHzSingle-chipCMOSPLLFrequencySynthesizerforWirelessApplications,Ph.D.dissertation,UniversityofFlorida,Gainesville,FLorida,2000. [32] P.AndreaniandS.Mattisson,\OntheuseofMOSvaractorsinRFVCO's,"IEEEJ.Solid-StateCircuits,vol.35,no.6,pp.905{910,June2000. [33] S.Al-Shahrani,DesignofClass-ERadioFrequencyPowerAmplier,Ph.D.dissertation,VerginiaTech,Blacksburg,Virginia,2001. [34] K.Chang,I.Bahl,andV.Nair,RFandMicrowaveCircuitandComponentDesignforWirelessSystems,JohnWiley&Sons,2002. [35] H.Hegazy,K.Sharaf,andH.F.Ragai,\AcomparativestudyofCMOS-basedquadratureintegratedLCVCOtopologies,"inProceedingsofMWSCAS-20,Aug.2002,vol.1,pp.I{336{I{229. [36] D.Leenaerts,C.Dijkmans,andM.Thompson,\A0.18mCMOS2.45GHzlow-powerquadratureVCOwith15%tuningrange,"inProceedingsofIEEERFICSymposium,2002,pp.67{70. [37] P.Andreani,\A2GHz,17%tuningrangequadratureCMOSVCOwithhighgure-of-meritand0:6ophaseerror,"inEuropeanSolid-StateCircuitConferenceESSCIRC2002,2002,pp.818{818.

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[38] C.Cao,Y.Ding,X.Yang,J.Lin,A.K.Verma,J.Lin,F.Martin,andK.K.O,\A24-ghztransmitterwithanon-chipantennain130-nmcmos,"inIEEEsymposiaonVLSITechnologyandCircuits,June2006.

PAGE 153

XiugeYangwasborninBeijing,China.ShereceivedaBachelorofSciencedegreeinelectronicengineeringfromTsinghuaUniversityofChinain1999.ShereceivedaMasterofSciencedegreeinelectricalandcomputerengineeringandaMasterofSciencedegreeinmanagementfromtheUniversityofFloridain2001and2003,respectively.In2003,shejoinedtheRadioFrequencySystemOnChip(RFSOC)ResearchGroup,attheUniversityofFloridaDepartmentofElectricalandComputerEngineering.HerresearchinterestsincludeRFandmixedsignalintegratedcircuitdesigninCMOStechnology,wirelesscommunications,digitalmodulations,andsoftwaredenedradio. 138


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Title: Low-Power Software Configurable Modulator for Wireless Communications
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Copyright Date: 2008

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LOW-POWER SOFTWARE CONFIGURABLE MODULATOR FOR WIRELESS
COMMUNICATIONS
















By

XIUGE YANG


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


2006

































Copyright 2006

by

Xiuge Yang





































To my parents.















ACKNOWLEDGMENTS

I would like to express my sincere gratitude to my supervisory committee

chair, Dr. Jenshan Lin, who provided the free, creative and friendly atmosphere

needed for an invaluable research experience. Without his knowledge, experience,

vision, and encouraging attitude, this work would be impossible. I also sincerely

appreciate the time and effort given by the members of my supervisory committee

(Dr. Rizwan Bashirullah, Dr. Liuqing Yang, and Dr. Fan Ren). I thank them for

their interest in my work and serving on my supervisory committee.

I am also thankful to my colleagues (Tien-Yu C'!i 1,;, Lance Covert, Jerry Jun,

Jaeseok Kim, JaeShin Kim, SangWon Ko, C('i i;,. !hi Li, Ashok Verma, Yanming

Xiao, and Hyeopgoo Yeo) in the Radio Frequency System On Chip (RFSOC)

Group, for all the help they offered. My thanks also go to my other colleagues in

the Department of Electrical and Computer Engineering, especially everyone in the

electronics area, for their indispensable role in my study and research.

I dedicate this work and my deepest love to my parents who have given me the

utmost trust and support to explore my life. Last but not least, I thank Dongming

Xu for being my best friend.















TABLE OF CONTENTS
page

ACKNOWLEDGMENTS ................... ...... iv

LIST OF TABLES ...................... ......... vii

LIST OF FIGURES ................... ......... viii

ABSTRACT ................... .............. xiv

CHAPTER

1 INTRODUCTION .................... ....... 1

1.1 Software Defined Radio ........... .............. 1
1.2 Digital Modulation Schemes ......... ............ 3
1.2.1 Binary Phase Shift Keying ................... 4
1.2.2 Quadrature Phase Shift Keying ........ ......... 5
1.2.3 Offset Quadrature Phase Shift Keying . . 7
1.2.4 Minimum Shift Keying ................ ... 8
1.2.5 Gaussian Minimum Shift Keying .... . . 9
1.2.6 Amplitude Modulation ................ .... 10
1.3 Overview of Dissertation .................. ... .. 12

2 SOFTWARE CONFIGURABLE MODULATOR . . ..... 14

2.1 Conventional I/Q Modulators ................ .. .. 14
2.2 Proposed Software Configurable Modulator . . ... 16
2.3 Comparison between Conventional and Proposed Modulators . 20

3 DESIGN OF A TEST MODULATOR FOR FIXED PATTERNED DATA 22

3.1 Constant Envelope Modulation . . ...... .. 22
3.1.1 Phase C!i ,I,-,.' Pattern for MSK modulation . . 23
3.1.2 Phase C!i ,i,-,.! Pattern for GMSK Modulation . ... 24
3.1.3 Designed Constant Envelope Phase Shift Test Modulator .28
3.2 Design Issues Associated With the Constant Envelope Phase Shift
Modulator ....... .. ..... ......... 29
3.2.1 Theoretical Power Spectral Density with respect to the
Number of Phase Shifts per Bit Period . . ... 29
3.2.2 Impact of Variations in the Modulated Signal's Amplitude
and Phase Shift Step .................. ..... 31









3.3 Circuit Description ............... ....... .. 34
3.3.1 Divider ............... ......... .. 35
3.3.2 M ultiplexers .................. ........ .. 37
3.3.3 Phasor Combining Circuit .................. .. 39
3.3.4 Buffers .................. ........... .. 40
3.3.5 Digital Circuit Section ................ .. .. 41
3.4 Experimental Results ........ . . . ... 42
3.4.1 Modulator IC Fabricated in 0.18 pm C'\OS Process . 42
3.4.2 Modulator IC Fabricated in 0.13 pm C'\OS Process . 50
3.4.3 Performance Comparison .... . . 54

4 A DIGITALLY CONTROLLED PHASE SHIFT MODULATOR FOR
ARBITRARY DATA PATTERNS .................. .. 57

4.1 Design Details .................. ........... .. 57
4.2 Experimental Results .................. ....... .. 61

5 DESIGN OF A DIRECT CONVERSION TRANSMITTER . 73

5.1 Direct Conversion Transmitters ..... . . ..... ... 73
5.2 Design of an Inductor-Capacitor-Based Voltage Controlled Oscillator 75
5.2.1 Small Signal Model of a C'\OS VCO . . ..... 77
5.2.2 Noise Issue Considerations .................. .. 79
5.3 Design of a Power Amplifier .................. ..... 82
5.3.1 Basic ('! i i. terics of a Power Amplifier . . .... 82
5.3.2 Classes of Power Amplifiers . . . ..... 84
5.3.3 Design of a Nonlinear Power Amplifier for the Output of the
Constant Envelope Modulator Circuit . . ... 88
5.4 Experimental Result of the Direct Conversion Transmitter Circuit 92
5.5 Direct Conversion Transmitter using a Quadrature Voltage Controlled
Oscillator ......... .. .... .... .. ...... 100
5.5.1 Design of a Quadrature Voltage Controlled Oscillator . 101
5.5.2 Experimental Result of the Transmitter Circuit using QVCO 106

6 DESIGN OF An OQPSK MODULATOR ................ .. 110

6.1 Design of the Modulator Circuit Board . . ..... 110
6.2 Experimental Results .................. ..... .. 117

7 SUMMARY AND FUTURE WORK ........... .. ... 126

7.1 Summary ............... ........... 126
7.2 Future Work ...... .................... 130

REFERENCES .................. ........ . . .. .. 134

BIOGRAPHICAL SKETCH ............. . . .. 138















LIST OF TABLES


Table page

3-1 Summary of the phase change pattern of GMSK modulation ...... ..28

3-2 Summing weights for generating different phasors ............ ..34

3-3 Summary of modulator performance (0.18 pm chip) . . ... 50

3-4 Summary of modulator performance (0.13 pm chip) . . ... 54

3-5 Comparison of modulator performance .............. .. .. 56

4-1 Performance summary of the modulator for arbitrary data patterns .. 72

5-1 Performance summary of the direct conversion transmitter . ... 100

5-2 Performance summary of the direct conversion transmitter using a QVCO 107















LIST OF FIGURES
Figure page

1-1 The QPSK modulation. The input bit stream is separated into two
streams containing odd and even bits. ................. 5

1-2 A QPSK signal waveform .................. ... 7

1-3 OQPSK is obtained from QPSK by d 1 ,iing the odd bit stream by half a
bit interval with respect to the even bit stream ... . . 8

1-4 An OQPSK signal waveform .................. .... 8

1-5 Power Spectral Density of an MSK signal as compared to a QPSK or
O QPSK signal . . . . . . . .. 9

1-6 Constellation of a GMSK signal. An MSK signal has a similar constellation
in that the amplitude (envelope) does not vary. .. . . 10

1-7 Power Spectral Density of a GMSK signal at different BT product ... 11

1-8 Constellation of a 16-QAM signal .................. ..... 12

2-1 Block diagram of a generic I/Q modulator ............ .. 15

2-2 Phasor diagram of a modulated signal .............. .. .. 17

2-3 How a phasor can be generated from two phasors in quadrature ..... 18

2-4 Conceptual schematic of a summing circuit ................ .. 19

3-1 An MSK modulation example and the modulated signal's constellation
(a) MSK modulation is I-Q modulation with half sinusoidal pulse shaping
(b) The modulated signal presents a constant envelope constellation 23

3-2 ADS simulation for GSM .................. ........ .. 24

3-3 ADS simulated GMSK waveform (a) I-channel (b) Q-channel ..... ..26

3-4 ADS simulation for GMSK spectrum ............. .. 27

3-5 MATLAB simulation of the constellation of a GMSK signal ...... ..27

3-6 Boundary points for one bit interval on a GMSK constellation . 28









3-7 Comparison of power spectral density (PSD) with respect to the number
of phase shifts per bit period. Normalized frequency is used in the figure 30

3-8 Ideal constellation of the modulator output ................ .. 31

3-9 Normalized sidelobe level (referenced to mainlobe level) versus variations
in amplitude and phase shift (The X-axis has a unit of radians for phase
shift variation, and it indicates percentage for amplitude variation . 33

3-10 How four discrete phasors within a quadrant can be generated from two
phasors in quadrature .................. ....... .. .. 34

3-11 Constant envelope phase shift modulator ................. ..35

3-12 A 2:1 static frequency divider (a) Block diagram (b) A detailed divider
scheme atic .................. ................ .. 36

3-13 A 2:1 differential current-steering multiplexer .............. .. 38

3-14 Phasor combining circuit .................. ........ .. 39

3-15 Schematic of the buffer .................. .... .... 41

3-16 Flip-flop latch .................. .............. .. 42

3-17 Die microphotograph of the modulator IC (0.18 pm chip) . ... 43

3-18 Simulated output power spectrum for the fixed repetitive data pattern .45

3-19 Measured output power spectrum. Signals's frequency is 25 MHz, or one
fourth of the 100 MHz bit rate, lower than the 2.5 GHz carrier frequency. 45

3-20 Measured constellation (0.18 pm chip) of the modulated signal (EVM =
2 '- .). The signal moved sequentially and repetitively in full circles 46

3-21 Measured I/Q plane diagram (0.18 pm chip) of the modulated signal 46

3-22 Measured EVM vs. carrier frequency (0.18 pm chip). At 100 Mbps bit
rate, for EVMs lower than 5.5'. the modulator can operate at a carrier
frequency between 1.75 GHz and 3.5 GHz ................ 47

3-23 Measured EVM vs. bit rate (0.18 pm chip). At 2.5 GHz carrier frequency,
for EVMs lower than 5' the bit rate of the modulator ranges from DC
to 500 M bps .. .. .. ... .. .. .. ... .. .. .. .. ..... .. 48

3-24 Constellation (EVM -= i,) at bit rate greater than 500 Mbps (0.18 pm
chip) ...... .................... ........ .. 49

3-25 When the error vector is perpendicular to the ideal phasor, the phase
variation is the '1i-.-, -1 ............... ......... 49









3-26 When the error vector is in the same direction as the ideal phasor, the
amplitude variation is the 'Li-- -I1 ..... .......... ........ 50

3-27 Complete modulator test chip circuit (0.13 pm chip) .......... .51

3-28 Die microphotograph of the modulator IC (0.13 pm chip) . ... 52

3-29 Measured constellation (0.13 pm chip) of the modulated signal (EVM
3.5' ) . . .. . . . . . 53

3-30 Measured I/Q plane diagram (0.13 pm chip) of the modulated signal 54

3-31 Measured EVM vs. carrier frequency (0.13 pm chip). At 100 Mbps bit
rate, for EVMs lower than !' the modulator can operate at a carrier
frequency between 1.5 GHz and 3.3 GHz ................. .. 55

3-32 Measured EVM vs. bit rate (0.13 pm chip). At 2.5 GHz carrier frequency,
for EVMs lower than 5.5' the bit rate of the modulator ranges from DC
to 225 Mbps ............... ............. .. 55

4-1 Movement of the phasor when serial data stream 10110010 is MSK
modulated ............... ............ .. .. 59

4-2 Boundary phases on the constellation for the 8 bit intervals . ... 59

4-3 How a state stream can be generated at the output of a MUX . 60

4-4 Modulator circuit for arbitrary data patterns ............... ..62

4-5 Ideal normalized output PSD for the modified modulator if pseudo random
input data are applied .................. ......... .. 62

4-6 Ideal constellation for the modified modulator if pseudo random input
data are applied ...... .......... . . ..63

4-7 Die microphotograph of the modulator circuit for arbitrary data patterns 63

4-8 Measurement setup for testing the modulator circuit with pesudo random
input data bits .................. ............. .. 64

4-9 Measured constellation at 2.5 GHz carrier frequency and 12 Mbps bit rate 65

4-10 Measured I/Q diagram at 2.5 GHz carrier frequency and 12 Mbps bit rate 66

4-11 Measured power spectrum at 2.5 GHz carrier frequency and 12 Mbps bit
rate ..... .............. .................. .. 67

4-12 Measured power spectrum with a smaller frequency span at 2.5 GHz
carrier frequency and 12 Mbps bit rate .................. .. 68









4-13 Simulated power spectrum of the modulator output with pesudo random
input data bits ............... ............ .. 68

4-14 Measured power spectrum at 2.5 GHz carrier frequency and 50 Mbps bit
rate ..... .............. .................. .. 69

4-15 Measured power spectrum at 2.5 GHz carrier frequency and 100 Mbps bit
rate ..... .............. .................. .. 69

4-16 IEEE 802.15.4 and ZigBee working model ............ .. 70

4-17 Output spectrum of the CC2420 transmitter ............... .71

5-1 Generic direct conversion transmitter utilizing the conventional I/Q
modulator ............... ............... .. 74

5-2 Designed direct conversion transmitter to be designed utilizing the
constant envelope phase modulator .................. .. 76

5-3 Designed Ci\OS LC-VCO ............... ..... .. .. 77

5-4 Equivalent circuit model of the designed C'i\OS LC-VCO . ... 78

5-5 Symmetric spiral inductor model ................ . .79

5-6 Layout of the LC-VCO circuit ............... .... 81

5-7 Simulated result of the output of VCO plus divider ......... .83

5-8 Voltage-current relationships for various classes of PA . .... 85

5-9 Topology of a single-ended power amplifier (class A, B, and C) . 88

5-10 Buffers to drive the PA. (a) Buffer for the first three stages (b) Buffer for
the last stage .................. .............. .. 89

5-11 Layout of the PA and its proceeding buffer/driver ............ ..90

5-12 Simulated differential output waveform from the PA . ..... 91

5-13 Die microphotograph of the direct conversion transmitter circuit . 93

5-14 Measurement setup for testing the transmitter circuit . .... 94

5-15 Observed output signals through substrate coupling from the LC-VCO at
5 GHz and the divider of the modulator at 2.5 GHz . . ... 95

5-16 Measured power spectrum of the transmitter circuit at 2.5 GHz carrier
frequency and 12 Mbps bit rate .................. .. 96

5-17 Measured power spectrum of the transmitter circuit at 2.5 GHz carrier
frequency and 25 Mbps bit rate .................. .. 97









5-18 Measured power spectrum of the transmitter circuit at 2.5 GHz carrier
frequency and 37.5 Mbps bit rate .................. ..... 97

5-19 Measured power spectrum of the transmitter circuit at 2.5 GHz carrier
frequency and 50 Mbps bit rate .................. .. 98

5-20 Measured power spectrum of the transmitter circuit at 2.5 GHz carrier
frequency and 100 Mbps bit rate .................. ..... 98

5-21 Output RF power level of the transmitter circuit vs. carrier frequency 99

5-22 Direct conversion transmitter to be designed . . 101

5-23 Quadrature VCO .................. ............ 102

5-24 Designed LC-QVCO .................. .......... 102

5-25 Layout of the LC-QVCO .................. ........ .. 103

5-26 Simulated result of the quadrature LO signals generated by the QVCO 105

5-27 Block diagram of the direct conversion transmitter utilizing an LC-QVCO 105

5-28 Die microphotograph of the direct conversion transmitter circuit ..... 106

5-29 Measured power spectrum of the transmitter circuit using a QVCO at
2.56 GHz carrier frequency and 12 Mbps bit rate ............ ..108

5-30 Measured power spectrum of the transmitter circuit using a QVCO at
2.56 GHz carrier frequency and 25 Mbps bit rate ............ ..108

5-31 Measured power spectrum of the transmitter circuit using a QVCO at
2.56 GHz carrier frequency and 37.5 Mbps bit rate . ..... 109

6-1 Phasor combining approach .................. ..... .. 111

6-2 Implementation of software control for MSK modulation . ... 112

6-3 Constellation of an OQPSK signal ......... ..... 112

6-4 Illustration of how the correct quadrants can be selected by the multiplexers
for OQPSK ................... ..... ........ 113

6-5 Modulator core circuit .................. ......... .. 114

6-6 Die microphotograph of the modulator core circuit . . ... 115

6-7 Using Linecalc to calculate the width of microstrip transmission line on
an FR4 board ....... ......... .......... ..... 116

6-8 Layout of the printed circuit board designed in Protel . . ... 117









6-9 Bonding diagram for the core circuit chip ..... . . 118

6-10 Photo of the bonded chip on the PC board ..... . . 118

6-11 Photo of the completed PC board ................ . 118

6-12 Measurement setup for testing the modulator board . . ... 119

6-13 Schematic of the board-level current source ..... . . 119

6-14 Photo of the current source test board for OQPSK modulation ..... ..119

6-15 Theoretical power spectrum of OQPSK ............. .. 121

6-16 Consistent measurement result with theoretical spectrum . ... 121

6-17 Measured output spectrum at 0.5 GHz carrier frequency and 24 Mbps
data rate . . . . . .. . .... 122

6-18 Measured output spectrum at 3 GHz carrier frequency and 24 Mbps data
rate. .......................... ...... ...... 122

6-19 Measured output spectrum at 3.7 GHz carrier frequency and 24 Mbps
data rate . . . . . .. . .... 123

6-20 Measured output spectrum at 2.4 GHz carrier frequency and 40 Mbps
data rate . . . . . .. . .... 123

6-21 Measured output spectrum at 2.4 GHz carrier frequency and 80 Mbps
data rate . . . . . .. . .... 123

6-22 Measured output spectrum at 2.4 GHz carrier frequency and 100 Mbps
data rate . . . . . .. . .... 124

6-23 Comparison of the power spectra for different number of phasors per
quadrant ................ .............. .. 124

7-1 Simplified pNode RF -,il i-- i. block diagram . . 129

7-2 Measured output power spectrum (100 Mbps data rate) and constellation
(12 Mbps data rate) around 24 GHz ............. .. 129

7-3 How the correct values of II and 12 can be provided for a phasor ..... 132

7-4 Die photo of the modulator core circuit using UMC 90 nm technology 133















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

LOW-POWER SOFTWARE CONFIGURABLE MODULATOR FOR WIRELESS
COMMUNICATIONS

By

Xiuge Yang

i ,v 2006

C('! I,: Jenshan Lin
Major Department: Electrical and Computer Engineering

We examined a software configurable modulator with the potential to generate

different modulation schemes. The modulator uses a "digital" approach unlike the

uilxilg or "multiplyiing approach used by conventional analog modulators. The

digital approach uses the phasor combining technique to generate the modulated

signal constellation. The phasor combing method is essentially to weigh and sum

up two phasors, or two LO signals with different phases (e.g, in quadrature) to

generate a desired phasor that represents the modulated signal on the constellation.

We designed and tested 2 test modulator circuits realizing an MSK-like

modulation scheme based on the design approach: one with a fixed data pattern

and the other for arbitrary data patterns. Experimental results showed that,

compared to a conventional modulator with similar functions, the proposed

modulator has the advantages of low power consumption (~3.6 mW excluding

output buffers), high data rate (up to ~100 Mbps), broad operating frequency









range (up to -3 GHz), and less circuit complexity in terms of necessary a< 'iT'11 riling

circuit components for function and performance purposes.

We also present the design and experimental results of a direct conversion

transmitter that uses the modulator. The transmitter consists of a voltage

controlled oscillator (VCO), the modulator circuit for arbitrary bit patterns,

and a power amplifier (PA). The power consumption of the whole transmitter is

~129 mW, and the output power level is ~3 dBm. The transmitter can be used for

a ZigBee-ready personal area network, or other similar wireless networks. It has the

advantages of higher data rate and lower error vector magnitude (EVM) than the

normal specifications for such networks.

We also designed and built a board-level modulator a core modulator chip

with the same architecture as the integrated modulator circuit. Control signals and

bias currents can be applied off-chip by on-board circuit components. The board

was tested for offset quadrature phase shift keying (OQPSK) modulation, and

the minimum shift keying (\!SI() function can be developed by properly designed

on-board circuitry.

The phasor combining approach can potentially allow a modulator to generate

different modulation schemes such as QPSK, MSK, and even quadrature amplitude

modulation (QAM). These modulation schemes are widely used in today's wireless

communications. Therefore, the proposed modulator may be well suited for a

software defined radio.















CHAPTER 1
INTRODUCTION

1.1 Software Defined Radio

The concept of software defined radio is gaining more attention and acceptance,

thanks to the third-generation standards. The third-generation standards support

adaptive modulation and coding, user (or network) controlled quality of service

(QoS), and cooperative networking have necessitated the use of software radio

architectures for radio design [1]. This makes it possible for the radio to provide

more services by sharing resources with neighboring devices and networks. a

multimode handset has the potential for more services and global roaming

capability.

Software defined radio (SDR) forum [www.sdrforum.org] defines SDR

technology as I ., h1 that provide software control of a variety of modulation

techniques, wide-band or narrow-band operation, communications security

functions (such as hopping), and waveform requirements of currents and evolving

standards over a broad frequency range." Also known as software radio (SR), it

can be seen as wireless communication in which the transmitter modulation is

generated or defined by a computer, and the receiver uses a computer to recover

the signal. SDR is a rapidly evolving technology generating more and more

interest in the telecommunication industry. Many analog radio systems are being

replaced by digital radio systems for various radio applications. Programmable









hardware modules are increasingly being used in digital radio systems at different

functional levels. SDR technology facilitates implementation of some of the

functional modules in a radio system such as modulation/demodulation, signal

generation, coding, and linl k- 1 -r protocols in software. This helps in building

reconfigurable software radio systems where dynamic selection of parameters

for each of the modules is possible [2]. Therefore, SDR technology greatly

broadens the application prospects of a system by allowing the same system

to be compatible for applications that use different link-li i-r protocols and/or

modulation/demodulation techniques.

SDR technology aims to implement radio functionality as software modules

running on a generic hardware platform. Multiple software modules implementing

different standards can be present in the radio system. In other words, SDR is a

collection of hardware and software technologies that enable reconfigurable system

architectures for wireless networks and user terminals. Therefore, radios built using

SDR technology can allow

* Standard, open, and flexible architectures for a wide range of communications
products

* Enhanced wireless roaming for consumers by extending the capabilities of
current and emerging commercial air-interface standards

* Over-the-air downloads of new features and services as well as software patches

* Advanced networking capabilities to allow truly portable networks

* Unified communication across commercial, civil, federal, and military
organizations

* Significant life-cycle cost reductions









To date, software radio base stations have been more popular and gotten

more attention than handsets, because base stations have much more relaxed

requirements for specifications like power and silicon area. However, software radio

designs are migrating to small handsets that support multimode radios, although

the task remains challenging due to the many constraints.

1.2 Digital Modulation Schemes

Take as an example a voice SDR transmitter that might be used in a mobile

two-way radio or cellular telephone communications. Typically it consists of a

microphone, an audio amplifier, an analog-to-digital converter (ADC) that converts

the voice audio to ASCII data, a modulator that impresses the ASCII data onto a

radio-frequency (RF) carrier, a series of amplifiers that boosts the RF carrier to the

power level necessary for transmission, and a transmission antenna. Among these

modules, the ADC and the modulator are computer-controllable circuits whose

parameters are determined by computer programming (software). The service

type, the mode, and/or the modulation protocol can be changed by selecting and

launching the requisite computer program.

The modulator is a key component for software configurability of an SDR.

Therefore, it is necessary to look at some of the basic digital modulation techniques

for wireless communications.

What is digital modulation? To transport data in a digital communication

system, typically one or more physical characteristics of a sinusoidal carrier (such









as frequency, phase, or amplitude) is adjusted. A modulator at the transmitter end

imposes the physical change on the carrier.

The choice of digital modulation scheme will significantly affect the

characteristics, performance, and resulting physical realization of a communication

system. Depending on the physical characteristics of the channel and required

levels of performance, some modulation schemes will have advantages over others.

Other factors that can affect the choice include required data rate, available

bandwidth, anticipated link budget, hardware cost and current consumption. Now

let us look at some commonly used digital modulation schemes in various wireless

communications standards.

1.2.1 Binary Phase Shift Keying

Binary phase shift keying (BPSK) is the simplest form of digital phase

modulation. With theoretical BPSK, the carrier phase has only two states. For

example, So(t) A cos t represents binary "O", and S,(t) A cos(wt + 7r)

represents binary "1".

For M-ary phase shift keying (PSK), M different phases are required, and

every n (where M = 2' ) bits of the binary bit stream are coded as one signal

that is transmitted as A cos(wt + Oj), where j = 1,..., M. When improved spectral

efficiency is required, higher-order modulation schemes, such as quadrature phase

shift keying (QPSK), are often used in preference to BPSK.







5



dkIt)

do d1 d5 dt d7

d2 dg da
-1------
0 T 2T 3T 4T 5T 6T 7T 8T
la)

dl(t)
+1




-1
0 2T 4T 6T BT


doI!)
+1
d, dg dy

d3
-1-----
0 2T 4T BT 8T

Figure 1-1. The QPSK modulation. The input bit stream is separated into two
streams containing odd and even bits.



1.2.2 Quadrature Phase Shift Keying


If we define four signals, each with a phase shift differing by Tr/2, then we have


quadrature phase shift keying (QPSK). Figure 1 1 shows that, the input binary


bit stream, dk where k = 0, 1, 2,..., arrives at the modulator input at a rate 1/T


bits/sec and is separated into two data streams di(t) and dq(t) containing odd and


even bits respectively, i.e.,



di(t) do, d2, d4,...


dq(t) = d, d3, ,...









A convenient orthogonal realization of a QPSK waveform, s(t), is achieved by

amplitude modulating the in-phase and quadrature data streams onto the cosine

and sine functions of a carrier wave as


S(t) oc di(t) cos t + dQ(t) sin t (1-1)


Using trigonometric identities this can also be written as

7F
S(t) Acos(t + + ) (1-2)
4

The pulse stream di(t) modulates the cosine function with an amplitude

of 1. This is equivalent to shifting the phase of the cosine function by 0 or

7. Consequently this produces a BPSK waveform. Similarly the pulse stream

dq(t) modulates the sine function, yielding a BPSK waveform orthogonal to the

cosine function. The summation of these two orthogonal waveforms is the QPSK

waveform. The values of 0(t) (0, -, 7, 5) represent the four possible combinations

of di(t) and dq(t). Each of the four possible phases of carriers represents two bits

of data. Thus there are two bits per symbol. Since the symbol rate for QPSK is

half the bit rate, twice as much data can be carried in the same amount of channel

bandwidth as compared to BPSK. This is possible because the two signals I and Q

are orthogonal to each other and can be transmitted without interfering with each

other.

In QPSK, the carrier phase can change only once every 2T seconds. If from

one T interval to the next one, neither bit stream changes sign, the carrier phase

remains unchanged. If one component di(t) or dq(t) changes sign, a phase change









do ...... d- 1-- --d -1- d 1-- --d 1.

--d, = 1-- _--d1 = -1--l .--.... dg= ......--... + d7= = 7 -1
i E U I I d t I I -----1 I





0 2T 4T 6T BT

Figure 1-2. A QPSK signal waveform


of 900 occurs. However, if both components change sign, then a phase shift of

occurs (Figure 1-2). In fact, the 1800 shift in phase will cause the envelope to go

to zero momentarily. The potential for a 1800 phase shift in QPSK results in more

likely spectral regrowth and requires better linearity in the power amplifier.

1.2.3 Offset Quadrature Phase Shift Keying

If the two bit streams di(t) and dQ(t) are offset by a -bit interval (Figure

1-3), then the amplitude fluctuations are minimized since the phase never changes

by 1800. This modulation scheme, offset quadrature phase shift keying (OQPSK),

is obtained from QPSK by delaying the odd bit stream by half a bit interval

with respect to the even bit stream. Figure 1-4 shows that, the range of phase

transitions is 0 and 900 (the possibility of a phase shift of 1800 is eliminated) and

occurs twice as often, but with half the intensity of the QPSK. The phase of the

carrier is potentially modulated every bit, not every other bit as for QPSK. Hence,

the phase trajectory never approaches the origin. While amplitude fluctuations may

still occur in the transmitter and receiver, they have smaller magnitude. The bit

error rate for QPSK and OQPSK is the same as for BPSK.















0 T

d01(t)


3T 5T 7T


0 2T 4T 6T 8T

Figure 1-3. OQPSK is obtained from QPSK by delaying the odd bit stream by
half a bit interval with respect to the even bit stream

do =1-----d2= d ----. d4 -1 L( = t--
I
I IIl I



Wtt t
?t-'--d = 1-----'-'--- d3 = -I- ---"....... dg = 1- ...--..d7 = 1


Vr I v ; I t


0 T 2T 3T 4T 5T 6T 7T

Figure 1-4. An OQPSK signal waveform


It should be noted that, although OQPSK is obtained from QPSK by delaying

dq(t) by 1 bit or T seconds with respect to di(t), this delay has no effect on the

bit error rate or bandwidth. In fact, because of the similarities between QPSK and

OQPSK, similar signal spectra and bit error rate are achieved. OQPSK is used in

the North America IS-95 CDMA cellular system for the link from the mobile to the

base station.

1.2.4 Minimum Shift Keying

Minimum shift keying (\!lS\) is derived from OQPSK by replacing the

rectangular pulse in amplitude with a half-cycle sinusoidal pulse. This sinusoid
















9 X

-40

-50

-60
.701
fC, fOU5Rb f+R, f+lJRb fJ+2Rt fc+2.5Rb

Figure 1-5. Power Spectral Density of an MSK signal as compared to a QPSK or
OQPSK signal


provides the required linear advancement or receding of phase that makes MSK

a continuous phase modulation. The MSK modulation makes the phase change

linear and limited to 1 over a bit interval T. This enables MSK to provide a

significant improvement over QPSK. Because of the effect of the linear phase

change, the power spectral density (PSD) has low sidelobes that help to control

.,idi i.ent-channel interference. However the mainlobe becomes wider than the

quadrature shift keying. Figure 1 5 [3] shows the PSD comparison between MSK

and QPSK/OQPSK.

1.2.5 Gaussian Minimum Shift Keying

In MSK the rectangular pulse is replaced with a sinusoidal pulse. Other pulse

shapes are also possible. A Gaussian-shaped impulse response filter generates

a signal with low sidelobes and narrower mainlobe than the rectangular pulse.

The filter is approximated by a d, 1 -i, .1 and shaped impulse response that has a

Gaussian-like shape. This modulation is called Gaussian minimum shift keying









(GMSK). Therefore, GMSK is a simple binary modulation scheme which may be

viewed as a derivative of MSK. Both modulation schemes are constant-envelop

modulations as can be seen from Figure 1-6. But in practice, GMSK is more

attractive for its excellent bandwidth efficiency, although inter symbol interference

(ISI) is introduced because a Gaussian pulse extends into .,.i ,i:ent bits. The

relationship between the premodulation filter bandwidth, B, and the bit period, T,

or the product of the two, determines the bandwidth of the GMSK signal, which is

shown in Figure 1-7 [4].










Figure 1-6. Constellation of a GMSK signal. An MSK signal has a similar
constellation in that the amplitude (envelope) does not vary.


Both MSK and GMSK have constant amplitude waveforms, which allows the

power amplifier to be operated further into saturation yielding improved efficiency

and increased output power, without significant spectral re-growth. As a variation

of MSK, GMSK provides better spectral roll-off in exchange for error rate. The

improved roll-off is to comply with demanding wireless standards for .Ili ,i:ent

channel interference.

1.2.6 Amplitude Modulation

All the modulation schemes mentioned above are constant envelope modulations.

Constant envelope modulations have the following advantages [5].
















S40 ----


.-60 ...-... 0.2

a. 603 I
1 i 0.4

I ______I \


-12
0 0.5 1.0 1.5 2.0 2.5
NORILIZED FREENCY : (f-fc)T

Figure 1-7. Power Spectral Density of a GMSK signal at different BT product


* Power efficient nonlinear amplifiers can be used without introducing
degradation in the spectrum occupancy of the transmitted signal.

* Low out-of-band radiation of can be achieved.

* Limiter-discriminator detection can be used, which simplified receiver design
and provides high immunity against random FM noise and signal fluctuations
due to Rayleigh fading.

However, amplitude modulations are also a very important class of modulation

scheme and still find their many applications in wireless communications. One

of the most commonly used amplitude modulations is quadrature amplitude

modulation (QAM).

QAM actually is a method of combining two amplitude-modulated signals

into a single channel, thereby doubling the effective bandwidth. Essentially, it is

a combination of amplitude modulation and phase shift keying. In QAM, data










II
IIII
1011 1001 10001 10011
-,.--------,t--- ^-+-


I
I I I I
1010, 1000 10000 10010



1110 1100 0100 0110 I
II I I
I I I I
I I I I
II II
1111 1101 0101 0111
---4- -*-~- 4-- -4----
I I I I
II I I

Figure 1-8. Constellation of a 16-QAM signal


information is encoded into two carrier waves, whose phases are in quadrature,

by variation of the carrier amplitude, in accordance with two input signals. As an

example, Figure 1-8 shows the constellation of a 16-QAM signal. QAM and its

derivatives are used in both mobile radio and satellite communication systems.

1.3 Overview of Dissertation


A software configurable modulator that has the potential to generate different

modulation schemes is proposed. The modulator uses a "digital" approach

rather than conventional analog modulators using "mixiing or "multiplyiing

approaches. The digital approach uses the phasor combining technique to generate

the modulated signal constellation. The details of the phasor combing method will

be explained in C'! Ilpter 2. A test modulator with fixed data pattern based on the

design approach was built and tested, and is presented in ('!C Ipter 3. A modulator

for arbitrary data patterns based on the testing results of the test modulator is

introduced in C'! Ilpter 4. C'! Ilpter 5 presents a design and experimental results of a






13


direct conversion transmitter which integrates a VCO, the modulator circuit, and

a PA, demonstrating one of the many possible applications of the modulator. A

board-level modulator designed and tested for OQPSK modulation is introduced in

C'! lpter 6. The modulator circuit board has the ability to generate MSK as well.

C'! lpter 7 summarizes the dissertation and talks about future work.














CHAPTER 2
SOFTWARE CONFIGURABLE MODULATOR

2.1 Conventional I/Q Modulators

From the introduction to the different modulation schemes in the previous

chapter, it can be seen that, in quadrature schemes, two independent signals

("in-lph i- and"qu h ii i[i. ) are transmitted via a single carrier, making use of the

orthogonality of signal components. Cellular standards, such as the international

GSM standard, the US IS54, IS95, and IS136 standards, and the Japanese PHS,

all require I/Q demodulation in some form. Generally speaking, quadrature phase

modulation can be regarded as a special case of quadrature amplitude modulation,

where the amplitude of the modulated signal is constant, with only the phase

varying. For example, QAM and QPSK systems abound, in the sense that QPSK

can be viewed as a 4-QAM modulation. Applications for QAM or QPSK include

CATV set-top-box converters and hybrid fiber/coax video transmission.

Modulators are a fundamental component in integrated circuits for wireless

communication systems. The most commonly used modulators are I/Q modulators,

which operate by taking two baseband data sequences (I and Q channels) and

varying the amplitude and phase of a sinusoidal carrier signal in response to the

instantaneous I and Q channel voltages [6]. The conceptual block diagram of at

generic I/Q modulator is shown in Figure 2-1 [7].Many modulators designed based

on the I/Q quadrature scheme have been reported such as in [8], [9], and [10].










d (Q) ==,ano ,
Processing
cos &d-

Baseband
dQ ) Processing
sin &

Figure 2-1. Block diagram of a generic I/Q modulator


The modulation schemes introduced in the last chapter are all quadrature

modulations (except for BPSK). ('! i... of modulation scheme is a tradeoff between

the transmit spectrum, simplicity of detection, and error rate performance. If we

consider QPSK as a variety of QAM, or 4-QAM, then these modulations can be

divided into two categories: linear and constant envelope. Linear modulations

such as QAM require linear amplification because the data information is carried

in the signal's amplitude variations, whereas constant envelope modulations

such as GMSK are more robust to the distortion caused by nonlinear amplifiers,

which offer higher power efficiency. There is no one prominent modulation scheme

between linear and constant envelope modulation methods, because when it comes

to particular application, it is important to look at the tradeoffs involved. For

example, QPSK's importance in CDMA is evident with its efficient bandwidth

use, enabling more users within a limited channel bandwidth. GMSK makes its

contribution to cellular systems in communications that necessitate power efficient

amplifiers. Because different modulations have different features and are used in

different applications and standards, a modulator that can realize more than one

modulation schemes will be of great significance for a software defined radio (SDR).









For a conventional I/Q modulator structure as in Figure 2-1, different quadrature

modulation schemes require different baseband processing, including pulse shaping

or filtering. For example, to generate a QPSK signal, the system converts a bit

stream into a Non-Return-to-Zero (NRZ) signal which is multiplied by an in-phase

(I) carrier and a quadrature (Q) carrier. While for GMSK modulation, the NRZ

signal needs to be passed through a Gaussian filter. Similarly, an MSK modulator

would need to shape the data stream into sinusoidal pulses, whereas a QAM signal

needs to be generated by varying the amplitude of the I/Q carriers. Therefore, to

design a modulator circuit that can accommodate more than one schemes using

the conventional I/Q approach poses considerable challenges on the digital circuit

section for baseband processing.

2.2 Proposed Software Configurable Modulator

No matter what the modulation scheme is, the resulting modulated signal is

essentially a carrier waveform whose phase and/or amplitude will vary according

data information, pulse --i IlIr,.- and baseband filtering. Therefore, precise carrier

phase and amplitude control is crucial for the accuracy of any modulation. On

the other hand, realizing the correct carrier phase and/or amplitude change is an

alternate way of implementing a modulation. Hence, we propose such a modulator

that controls the phase and/or amplitude of the carrier in order to generate a

modulated signal. It will be also designed such that different controls can be

applied to the modulator to allow for differently modulated signals. In other words,




















Project signal r '
to "I" and "Q" axes 1-Value







Figure 2-2. Phasor diagram of a modulated signal


we will try to make the modulator software reconfigurable and thus applicable for a

software defined radio.

A simply way to view amplitude and phase is with a phasor diagram, which

is exemplified in Figure 2-2, where the signal is interpreted relative to the

before-modulation carrier. The modulated signal is expressed by the phasor as

a magnitude and a phase. Magnitude is represented as the distance from the center

and phase is represented as the angle relative to 0 degree, or I axis. The phasor's

projection onto the I axis is its "I" component and the projection onto the Q

axis is its "Q" component. Amplitude modulation changes only the magnitude

of the phasor, while phase modulation changes only the angle of the phasor. The

magnitude and the angle of a phasor can be changed together, as in the case of

QAM.










sincot




T ~--- - -
\
\
\






b r


a cost


Figure 2-3. How a phasor can be generated from two phasors in quadrature


Different modulations will produce different phasor movements on the

constellation. As long as the phase and amplitude changes along the constellation

circle, corresponding to actual data bits, can be generated in integrated circuits,

both linear and constant-envelope modulations can be implemented. As an

example, Figure 2-3 illustrates how, in any particular quadrant, constant envelope

and different phases, 0's, can be generated from two LO carriers in quadrature. By

maneuvering the values of a and b, which can be seen as the weights of cos ct and

sin ct, the two quadrature LOs, respectively, 0 can be changed while r maintains

constant. This can be realized using a phasor combining, or summing, circuit where

two quadrature LO signals are weighted and summed up to generate the in-between

phasor. By choosing pairs of quadrature LOs of different phases according to the

actual data, the correct quadrant on the constellation can be guaranteed.












Vout-


V T < 1: 62

11 12


Figure 2-4. Conceptual schematic of a summing circuit


The approach of generating an in-between phasor from two phasors in

quadrature can be realized by a phasor combining circuit, or a summing circuit,

whose simplified schematic can be seen in Figure 2-4. In this circuit, VI and V2,

are at carrier frequency and have a 90 degree difference in phase. Il and 12 weigh

V1 and V2 respectively, and the sum of the two weighted LOs, Vout, will be the

generated phasor that falls between the two input phasors. In other words, Vout

can be interpreted as a carrier signal whose phase is being changed. The amplitude

of Vout, or the magnitude of the generated phasor, also depends on the values

of Il and 12. If the sum of I1 and 12 remains constant, the modulated signal will

have a constant envelope. By choosing pairs of quadrature LOs of different phases

according to the actual data, the correct quadrant on the constellation can be

guaranteed.

This method can be applied to non-constant envelope modulations such as

QAM, which utilize amplitude variations as well. In that case, both the magnitude

and the angle of the phasor need to be changed, although it will make non-linear









amplification difficult. However, even if only non-linear power amplifiers are

to be used, making use of techniques such as LINC (Linear Amplification with

Nonlinear Components) [11], non-constant envelope modulations still can be

realized with the combination of two sets of constant envelope modulators and

nonlinear power amplifiers. This brings broad application prospects for modulators

designed based on this principle, which essentially is just changing the phase, and

possibly amplitude as well, of a carrier according to the modulation. For example,

a software defined radio (SDR) can use such modulators to accommodate different

modulations.

2.3 Comparison between Conventional and Proposed Modulators

As we have discussed, I/Q modulations, or quadrature modulations, are of

an important role in many telecommunication applications and wireless standards.

The modulator designed using the phasor combining approach is capable of

generating most of the widely used I/Q modulations such as QPSK, MSK, and

GMSK, but it is not exactly the same as a conventional I/Q modulator. However,

different quadrature modulation schemes require different baseband processing,

such as pulse shaping and filtering, which imposes challenges on the baseband

circuit, especially if multiple modulation schemes are to be generated, as for an

SDR [12,13].

The phasor combining approach, on the contrary, does not require baseband

processing. In principle, it directly changes the phase and/or amplitude of the

carrier, according to the designated phasor movement on the constellation.









Different modulation schemes, and hence the different baseband processing

they need, result in different phasor movements on the modulated signal's

constellation. Therefore, in a sense, the phasor combining approach skips the

baseband processing, the analog mixing or multiplication, and the summation, and

tries to create the final vector signal directly. This is done by selecting the pairs of

V1 and V2 (see Figure 2-4) for correct quadrants and by controlling the weighing

currents I1 and 12 for correct signal phase/amplitude. The circuitry can be much

simplified in this way.

Another 1i, i, ri difference between the two types of modulators lies in that the

proposed modulator is "linear" in the sense that carrier phase and/or amplitude

are changed linearly by the bias currents (I1 and 12) of the phasor combining

circuit, whereas conventional I/Q modulators usually make use of devices'

nonlinearity to realize "mixing or "multiplication". This difference brings forth

an important advantage of the phasor combining approach over the conventional

I/Q modulators. C'!i i ., I filtering, which is necessary for cleaning up a nonlinear

modulator's output spectrum [14, 15, 16], would not be necessary for the phasor

combining modulator, making it more suitable for higher level of integration.















CHAPTER 3
DESIGN OF A TEST MODULATOR FOR FIXED PATTERNED DATA

3.1 Constant Envelope Modulation

The proposed phasor combing circuit has the potential for generating different

modulation schemes by realizing different phasor change patterns in amplitude,

phase, or both. Since constant envelope modulations are an important class in low

power wireless communications, a constant envelope phase shift modulator circuit

was built to test how well the phasor combining approach works.

Many wireless mobile products use nonlinear saturated power amplifiers

because they have higher efficiency than linear amplifiers. A non-linear amplifier

changes the signal amplitude by different amount depending on the instantaneous

amplitude of the signal. The more the amplitude of a signal varies, the more

non-linear amplification occurs, which will result in a distorted signal. Therefore,

modulated signals with constant envelope are often preferred in wireless

communications.

In constant envelope modulations, only phase information is employ, -1 to

carry the user data, with the carrier amplitude being constant. Two examples

of constant envelope modulations are Minimum Shift Keying (\!SlK) [17] and

Gaussian Minimum Shift Keying (GMSK) [18]. Compared to MSK, GMSK has

the advantage of a more compact power spectrum due to baseband filtering

[4], but MSK does not generate Intersymbol Interference (ISI) because the








shaping sinusoidal pulse is confined in a bit duration. In either modulation, data

information is contained only in the carrier's phase. So this type of modulations

can be interpreted as phase modulation.

3.1.1 Phase Change Pattern for MSK modulation



S A11111 T '\


10 IIl:10 10 I1 I
0 11 0 0 1


1 1 1 Vi1i I I


(a)
Q









2 6
8 57


(b)
Figure 3-1. An MSK modulation example and the modulated signal's constellation
(a) MSK modulation is I-Q modulation with half sinusoidal pulse
shaping (b) The modulated signal presents a constant envelope
constellation

























-. ,., + N k4. M c rNSOLIUN U O ?? S
1= ==y ,..', Tm m+/ I n Ta
7 *.n I ,.













Nl.rO, r Jc1 7 NlI





Figure 3-2. ADS simulation for GSM


If seen from the constellation of a phase modulation signal, the signal


vector, or, the phasor, changes angle according to the transmitted bits with the


magnitude of the vector maintaining the same, which results in a point moving


on a constant-radius circle and changing direction from time to time. This is


exemplified in Figure 3-1, which shows an MSK modulation and its constellation


for 8 bit intervals. The baseband I/Q channel data bits are shaped into sinusoidal


pulses and respectively modulated onto two carriers with quadrature phases. Then


the resulting signals of the two channels are summed up, and the modulated signal


becomes a constant envelope carrier with changing phase. It can be seen that on


the resulting constellation the phasor moves on a circle and changes direction based


on the I/Q bit pattern. It goes over a quadrant for a one-bit interval.


3.1.2 Phase Change Pattern for GMSK Modulation


GMSK is also a constant envelope modulation scheme. It can be interpreted


as a derivation from MSK in that the sinusoidal pulse shape in MSK is changed to


Iiorn
"d
Bilr csu.cu)ru,~
ei YI
I 1~ .
)1-
IC-
LF)*~ i n i ( J( ~ 1~,









Gaussian. This, however, significantly complexities the resulting modulated signal's

phase change pattern.

To investigate the phase change pattern of a GMSK signal, we used ADS

simulation (Figure 3-2). This design is used to dipl iw the GMSK modulation

waveform (Figure 3-3) and spectrum (Figure 3-4). The random source is GMSK

modulated and the base band signal is fed to RF section which includes: RF

mixer, Butterworth Filter and RF gain. Central Frequency is 935.2MHz as in

GSM standard. We exported the data for the simulation result and processed it in

MATLAB. Both the I-channel and the Q-channel waveform data were plotted onto

an I/Q diagram to see the signal constellation (Figure 3-5). The simulation was

done dynamically together with the data bits in order to observe the phase change

pattern of a GMSK signal according to the data bits.

It can be seen from the simulation results that, like MSK, GMSK is also a

constant envelope modulation with increased spectral efficiency, making it desirable

to maximize the number of available channels. Based on the dynamic simulation

from MATLAB, unlike MSK, the boundary points for a one-bit interval in GSMK,

as shown in Figure 3-6, are not only the axis points anymore. Moreover, because

a Gaussian pulse extends into both the previous bits and the next bits, the phase

change depends on more than just two consecutive bits as in the case of MSK. The

phase change pattern of GMSK can be summarized as in Table 3-1.



























-om-

-0-04 V
-0_jOB- .


40a


sOO


8o0


1000


Index

(a)


0.06
0.04


AM


-002-



-006 200 400 600 00 10
0 200 400 600 8a0 1000


Index

(b)


Figure 3-3. ADS simulated GMSK waveform (a) I-channel (b) Q-channel

















-20-

-0- -- .---- ___

-60-
-h A t A A .

-100-

-120
933.0 933.5 934.0 934.5 935.0 935.5 936.0 936.5 937.0 937.5

Mega_Hertz


Figure 3-4. ADS simulation for GMSK spectrum








-,WOo +O O n


0
a





.00^^


Figure 3-5. MATLAB simulation of the constellation of a GMSK signal










A1




CI



A4 A2



C3 B2


C2
B3
A3


Figure 3-6. Boundary points for one bit interval on a GMSK constellation

Table 3-1. Summary of the phase change pattern of GMSK modulation

previous two bits, current bit, next bit phase change
0000 or 1111 Ai A,_
1000 or 0111 Ci Ai
0001 or 1110 Ai -- Bj1
1001 or 0110 Ci -C B
0010 or 1101 Bi Ai+
1010 or 0101 Ai Ai+
0011 or 1100 Bi -+ ,
1011 or 0100 Ai -+ C


3.1.3 Designed Constant Envelope Phase Shift Test Modulator

MSK and GMSK can both be interpreted as constant envelope phase

modulations. However, MSK has a much simpler phase change pattern, which

makes it a handy choice for designing a modulator circuit to test the phasor

combing approach. A test modulator circuit based on the MSK modulation was

designed and fabricated in both a 0.18 pm CM\OS process and a 0.13 pm process.









3.2 Design Issues Associated With the Constant Envelope Phase Shift
Modulator

The designed test modulator is one that follows the phasor combining

approach. It was designed for ZigBee [19] or other types of low power wireless

networks. The modulator adopts an MSK-based scheme, but the phase change

over any bit interval, which corresponds to a quadrant on the constellation, was

implemented in a limited number of discrete steps, four in this particular design, in

order to simplify the circuit architecture without compromising the performance of

the modulator significantly. This will be explained in the following together with

some other issue associated with the modulator design.

3.2.1 Theoretical Power Spectral Density with respect to the Number
of Phase Shifts per Bit Period

A good means for checking the performance of a modulator is the modulated

signal's power spectral density (PSD). Ideal MSK modulation with randomly

distributed input bits would give us a normalized PSD as shown by the solid

line in Figure 3-7, which also shows the different PSDs generated from the

phase shift modulation by using different numbers of phase shifts within every

quadrant, starting from the axis points. It can be seen that, with one phase shift

per quadrant, the PSD is the same as that of an OQPSK modulation. And as

the number of phase shift steps per quadrant increases, the discrete phase shift

modulation approaches MSK and the spectrum eventually becomes an MSK

spectrum.










0

-10


-30
-20 -r -




) -50


-50 ........ 1 step/quadrant
a- 2 steps/quadrant
-60- 4 steps/quadrant
-MSK
-3 -2 -1 0 1 2 3
(f-fc)/R

Figure 3-7. Comparison of power spectral density (PSD) with respect to the
number of phase shifts per bit period. Normalized frequency is used
in the figure


As shown in to Figure 3-7, the highest normalized side lobe level for the

cases of 1 step, 2 steps, 4 steps per quadrant are -14 dBc, -18 dBc and -22

dBc, respectively. With four phase shifts per quadrant, the discrete phase shift

modulator has a very similar spectrum as the MSK that has a -23 dBc highest side

lobe level. A quadrant on the constellation corresponds to a bit period. Therefore,

we chose four phase shift steps for every bit period for the design to simplify the

circuit architecture.

With four phase shifts per quadrant, the output of the modulator should

generate a constellation like the one in Figure 3-8, where the modulated signal

moves sequentially on the circle in discrete steps and changes direction only on the

I or Q axis points.






























Figure 3-8. Ideal constellation of the modulator output


3.2.2 Impact of Variations in the Modulated Signal's Amplitude and
Phase Shift Step

The results in Figure 3-7 were simulated by assuming an ideal modulator

that produces constant amplitude and constant phase shift step size. However,

due to a summing circuit's gate-to-drain RF feedthrough of the two quadrature

input signals, which exists even when one of the two summing weights is set to

zero, perfect constant amplitude within each quadrant of the modulated signal's

constellation cannot be achieved by real circuit. The size of the phase shift steps

also varies across the constellation. The variation in the modulated signal's

amplitude and phase shift step will lead to deviation of the signal point from

the ideal symbol point on a constellation, which will increase the EVM of the

modulator. The EVM (Error Vector Magnitude) is the difference between the ideal

vector convergence point and the transmitted point on a signal constellation. It









is defined as the rms value of the error vectors in relation to the magnitude of an

ideal symbol. It is obvious that the bigger the amplitude/phase shift variations are,

the worse the modulator will perform in terms of EVM. Meanwhile, we also need to

investigate the impact on the output spectrum.

In order to take into account more and different variations of the modulated

signal, the effect of the variance of variations in the output signal's amplitude, or

in its phase shift among the four steps within each quadrant, was further studied.

That is, we treated the variation as a random variable, with a mean of zero and an

approximated variance based on the data from simulation results, and studied the

relationship between the modulator's performance, in terms of sidelobe level, and

the variance of the variation (VOV). We denoted VOV as a$.

For example, based on probability theory, the VOV in phase shift can be

approximated as
4
V= 4iy f) (O p)]2 (3-1)
i=1

where i=1:4 0, 7/8, 7/4, 37/8 and ij's are actual values of implemented phases.

To simulate the effect, four normally distributed random values with zero mean

and variance of a$ were generated to represent the variations from the four ideal

phase points in a quadrant. Figure 3-9 plots the first sidelobe level normalized

to mainlobe level (dBc) versus the different values of av in phase shift. For the

modulator design, maximum angle deviation from the ideal phasor can be looked

up in Figure 3-9 as the worst case scenario in terms of phase shift variation to see

how the performance will be affected. The results shown in Figure 3-9 indicate











6
--Amplitude variation
'& -8 *-Phase shift variation
-D -10 ...
-10
a, -12

-14-






z -20 -
-22
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
G\1


Figure 3-9. NX in i, i. .1 sidelobe level (referenced to mainlobe level) versus
variations in amplitude and phase shift (The X-axis has a unit of
radians for phase shift variation, and it indicates percentage for
amplitude variation


that, if (-v is less than 0.1 radian (5.73), the increase of sidelobe level from the

ideal case is less than IdB.

Figure 3-9 also plots the effect of amplitude variation on the PSD's sidelobe

increase. The effect appears to be similar to that of phase shift variation. Note

that the X-axis has a unit of radians for phase shift variation, and it indicates

percentage for amplitude variation. Therefore, when av in the amplitude of the

modulation is less than 1C'. or when av in the phase shift step is less than 0.1

radian, the modulator's performance will not be degraded significantly. It should be

pointed out, however, that the variation in the amplitude of the modulated signal is

likely to disappear after the signal is amplified by a non-linear and saturated power









sincot


P2




T-- --- --------- P 1
P1

b r

-a coso t

Figure 3-10. How four discrete phasors within a quadrant can be generated from
two phasors in quadrature

amplifier (PA). Therefore, it should not be a critical factor for the performance of

the modulator when integrated in a transmitter with a non-linear PA.

3.3 Circuit Description

As discussed earlier, the modulator design is based on the MSK modulation

scheme, but MSK's continuous phase change over each bit interval is implemented

in four discrete steps. Figure 3-10 specifically illustrates how the four discrete

phases within a quadrant, or the four phasors (PO, P1, P2, P3), can be generated

from two quadrature phasors sin ut and cos ut. Table 3-2 lists the four pairs of

summing weights (a and b) for generating the four phasors.

Table 3-2. Summing weights for generating different phasors

Phasor PO P1 P2 P3
Phase (0) 0 8 L 3w
Summing Weight a ocos 0os cos oc cos oc cos 3
Summing Weight b oc sin 0 o sin oc sin oc sin-









4 LO output
signals with
phases equally
separated over 4:1 differential mux
separated over
2:1 Divider 360 degrees I
2:1
a(To 2: Buffer Present State
buffers L 2:1 chasee
//----t- ... I--
cK1 K2 Summing Output
4:1 differential mux
r----- ----- ----
Clock 7 2:1
generation d 2:1 -t Buffr Next S ate (Phase)
and digital t :1
control ] I __
circuit _ _
CK1 CK2
h h


Figure 3-11. Constant envelope phase shift modulator


A block diagram of the constant envelope phase shift modulator circuit is

shown in Figure 3-11. The circuit is mainly composed of a 2:1 divider, two 4:1

differential multiplexers, a phasor combining circuit (summing circuit), output

buffers, and a digital circuit section to control these blocks.

3.3.1 Divider

From a differential 2xLO (twice the LO frequency) input signal, a 2:1 current

mode logic static frequency divider, as shown in Figure 3-12, generates four signals

with phases that are equally separated over 360 degrees, as indicated by the four

crosses on the I/Q axes in Figure 3-8. The divider has a differential master-slave

configuration. The inverted slave outputs are connected to the master inputs. The

cross connection between the slave and the master generates an output frequency

at half of the input (CLK and CLKb) frequency. The differential output from the

master (Qi and Qbi) is in quadrature with that of the slave (Q and Qb). Therefore,











D Q

D Q

-f-ft-


Qbt
Qbi


D Q

D Q
I-A


(b)
Figure 3-12. A 2:1 static frequency divider (a) Block diagram (b) A detailed
divider schematic

with a differential input at a frequency twice the designated LO frequency for

the modulation, the divider will provide four LO signals whose phases are 90

degrees apart from one another. Both the master and the slave consist of two input

transistors (\I I and M2), two drive transistors (\! I and M5), two latch transistors

(\! I and M6), and two load transistors (\!7 and M8). The self-oscillation frequency

of a divider increases as the sizes of the transistors are decreased, although driver

transistor size has less effect that the sizes of other transistors [20]. At a given


L


Qb


CLK 0c
CLKb 0


mm-6


! I


I









drive transistor size, the smaller the latch transistors' size is, the lower the output

voltage amplitude gets [20]. However, increasing transistors' size will also increase

power consumption. Due to these tradeoffs, and since the divider must be designed

based on the acceptable power consumption and output signal level, the chosen

transistor sizes will set a limit on the operating frequency of the divider. The

operating frequency range of the divider will determine the modulator's operating

bandwidth to a great extent.

3.3.2 Multiplexers

From the four LO signals generated by the divider, two 4:1 differential

multiplexers (\ UXes) are used to select the present state and the next state.

The two states correspond to the two boundary points of a quadrant on the I/Q

plane, whereby the modulated signal phase would change by 90 degrees during

any bit interval. The selected pair of the two states holds for a bit interval before

being changed by the two 4:1 MUXes for the next bit interval. Each 4:1 MUX is

designed to consist of two stages of 2:1 differential MUXes. The two stages are

controlled by two clocks, Clockl and Clock2, respectively, as can be seen from

Figure 3-11. One of the two clocks, Clockl in this design, controls the bit rate,

and the other clock embeds the digital data bits. Figure 3-13 shows the schematic

of a 2:1 current-steering MUX [14] used in the design. This structure allows for

a reduced voltage swing. Simulations also indicate that switching of the current

can be performed at a speed higher than switching of the voltage [14]. Therefore

this type of MUX can increase the operating speed of the circuit, which allows for





















Vin2


Figure 3-13. A 2:1 differential current-steering multiplexer


higher data rates, especially if the same circuitry is to be used for implementing

different modulation schemes.

Compared to a one-stage 4:1 MUX [15], the two-stage configuration, although

more complex, suffers less speed penalty and maintains fully-differential signals

better [16]. Both configurations require at least two inputs, one for the clocks,

and the other for data, which will decide what to select from the four LO

signals. Simulation result also showed that, for this modulator design, the power

consumption of using two-stage MUXes was not significantly higher than using

one-stage ones.









VDD




Vout




111 12

0 sw.SWI H2 ,-
SWITCH11 I | 1 I SWITCH

-- .lblI 4b.]lb2 1_b3


Figure 3-14. Phasor combining circuit

3.3.3 Phasor Combining Circuit

After passing through buffers, the present state signal and the next stage

signal are fed into a phasor-combining circuit, which is shown in Figure 3-14.

The phasor-combining circuit sums the input signals to produce a signal with a

phase shifting between those of the two inputs. Different intermediate phases can

be generated by applying different bias currents (Ii and 12) as summing weights,

which can be realized by using digital logic circuits to switch the current sources.

As can be seen from Figure 3-14, three switches, which turn on or off the three

bias current sources bl1, Ib2, and Ib3, are controlled by digital circuit to generate

four different combinations of II and 12 values within a bit interval, in order to

implement the four intermediate phase shifts within any particular quadrant

period. The digital control signals for switch 1 and switch 3 are differential and









thus neither Ib1 nor Ib3 will contribute to I1 or 12 at the same time, while Ib2

alv--,i contributes to I1 only. The controls of the switches are designed such that

the four combinations of II and 12 are as follows.

1) I = Ib + 1b2 + 1b3 o cos 0, 12 = 0 oc sin 0 (to generate a 0 phase shift

relative to the present state);

2) I = 1b2 + 1b3 o cos 22.50, 12 = 1 x oc sin 22.50 (to generate a 22.50 phase

shift);

3) II = b + 1b2 oc cos 450, 12 = 13 oc sin 450 (to generate a 450 phase shift);

4) I = 1b2 oc cos 67.50, 12 = b1 + b3 o sin 67.50 (to generate a 67.50 phase

shift).

I1 and 12 weigh the present state signal and the next state signal respectively,

and Vout is the sum of the two weighted signals, with an in-between phase. In the

meantime, constant amplitude of Vout can be maintained by keeping the sum of II

and 12 constant (Ib + 1b2 + 13).

3.3.4 Buffers

The last stage of the modulator design is an output buffer/amplifier to drive

50 f single-ended loads for the purpose of testing with 50 f instruments. Three

buffers similar to the one in Figure 3-15 are cascaded to serve as the driver. The

buffers use resistor loads to achieve a broadband response. There is also a buffer

stage between the MUXes and the phasor combining circuit.










VDD





Vout













Figure 3-15. Schematic of the buffer


3.3.5 Digital Circuit Section

As introduced earlier, the modulator circuit needs many clock signals (e.g.,

for the MUXes) and control signals (e.g., for controlling the switches of the phasor

combining circuit). For testing purpose, the modulator chip is designed with only

one clock input, and all the clocks and controls are generated by digital circuitry

on the chip. Because these signals are of relatively lower frequencies, C'\ OS logic

digital circuit is used for lower power consumption. The digital circuit section

consists mainly of two sets of the combination of master-slave flip-flops and XOR

gates, with one set generating the control signals for the switches, and the other

generating the clocks for the MUXes. The two sets are separately configured

and connected according to the desired waveforms of the clocks and the controls.

In both sets, the masters and the slaves use the same type of flip-flop latch as









VDo VDD





rI r- I
CLK[ CLK -




CLKb CLK





Figure 3-16. Flip-flop latch


shown in Figure 3-16 [21]. Latches are also used to line up the correct edges of the

generated clocks and controls.

3.4 Experimental Results

3.4.1 Modulator IC Fabricated in 0.18 pm CMOS Process

The modulator IC was designed and fabricated in a 0.18 pm mixed signal

C'\OS process with a supply voltage of 1.8 V. The chip, which we will call the

0.18 pm chip for the convenience of discussion, occupies an area of 0.5 mm2. Its

microphotograph is shown in Figure 3-17.

In designing this particular modulator testing chip, repetitive data pattern

was internally generated and translated into the multiplexers, creating a modulated

signal that moves clockwise in circles at a constant speed, determined by the data

rate, on the constellation. The purpose was twofold: 1) to reduce the spectrum

bandwidth of the output signal so that it can be measured by equipment with

limited bandwidth; 2) to simplify testing the IC without the need for a high-speed

























Figure 3-17. Die microphotograph of the modulator IC (0.18 pm chip)


data pattern generating instrument or multiple high frequency clock signal sources.

In this design, only an RF signal input, for the divider to generate the four phased

LO signals, and a single clock input, for controlling the MUXes and timing the

internal digital circuits, are needed.

To derive the mathematical description of a signal modulated in such a way,

assume that the carrier is in the form of A cos(27r ft+o4), where A is the amplitude

of the carrier, f, is the carrier frequency, and 40 is the initial phase of the carrier.

Without loss of generality, 40 can be assumed to be zero. A modulated signal

moving clockwise on the constellation circle continuously means that the carrier's

phase decreases continuously with time. Denote the bit rate as R and therefore

the bit interval T = 1/R. Since the phase change of an MSK signal within a bit









interval, T, is r/2, the modulated signal, s(t), can be expressed as


j/2
s(t) A cos(2rf~t t) (3-2)

A cos(27ft Rt) (3-3)
2
1
= A.-[2-(f -R)t]. (3-4)
4

Therefore, s(t) is still a single tone sinusoidal signal, but its frequency is !R

lower than the original carrier frequency. Because in this design the continuous

phase change is implemented in four discrete steps, the mathematical expression for

the actual signal, s,(t), should instead be



ir t
sa(t) = A cos(2rft L- ), (3-5)
8 T/4

where [-L is the floor operator, which gives the largest integer less than or

equal to the operand. MATLAB simulation was performed to estimated the output

spectrum of s,(t), which is shown in Figure 3-18.

The modulator IC was tested using an Agilent 89600 series Vector Signal

Analyzer (VSA) with an external power amplifier connected to the output of the

chip. The VSA has a bandwidth of 36 MHz. From the measured spectrum of

the modulator's output signal in Figure 3-19, it can be seen that it matches the

theoretical estimation. The bit rate was set to 100 Mbps in the measurement,

the carrier frequency was 2.5 GHz, and the spectrum shows a single tone with

the center frequency at 2.475 GHz which is exactly 25 MHz lower than the

carrier frequency. It should be pointed out that, although fixed data pattern was
















-10


-2 -1 0
(f-fc)/R


1 2 3


Figure 3-18. Simulated output power spectrum for the fixed repetitive data pattern


Figure 3-19. Measured output power spectrum. Signals's frequency is 25 MHz, or
one fourth of the 100 MHz bit rate, lower than the 2.5 GHz carrier
frequency.


(f-fc)/R = -0.25
-f=fc R/4














C









Figure 3-20. Measured constellation (0.18 pm chip) of the modulated signal (EVM
= 2 .). The signal moved sequentially and repetitively in full circles


designed and used to simplify the measurement, at the end of every bit interval the

multiplexers ahv--, re-select two LOs in quadrature as the new p' -" 1n and"next"

states. Therefore, the data rate of the fixed pattern data still signifies the bit

rate that the modulator can manage for arbitrary data patterns. As observed in

the measurement, as the data rate increased (the signal vector rotated clockwise

faster), the frequency shift in output spectrum also increased.
















Figure 3-21. Measured I/Q plane diagram (0.18 pm chip) of the modulated signal


Figure 3-20 shows a constellation measured using Agilent 89600 Vector Signal

Analyzer (VSA), with an external power amplifier connected to the 0.18 pm


LIII

















4

3.5

3-

2.5
1.5 2 2.5 3 3.5
Carrier Frequency (GHz)

Figure 3 22. Measured EVM vs. carrier frequency (0.18 pm chip). At 100 Mbps
bit rate, for EVMs lower than 5.5' the modulator can operate at a
carrier frequency between 1.75 GHz and 3.5 GHz


chip's output. This test was used to verify the correctness of the phase shifts. The

I/Q plane diagram in Figure 3 21 demonstrates the constant envelope feature

of the modulator. The bit rate was set to 100 Mbps in the measurement. The

measurement result showed an average EVM (Error Vector Magnitude) of ;: -.

With one of the differential outputs terminated by 50 Q, the 0.18 pm test chip

delivered a signal level of -2 dBm to a 50 Q load. The modulator was designed for

low power applications, and the measured current dissipation was 2 mA with the

supply voltage being 1.8 V. It should be noted that this current dissipation did not

include that of the three cascaded output buffers, which, although consumed 10 mA

current, are not necessarily an integral part of the modulator, if the modulator is

put into a transmitter chain and only needs to drive the input impedance of the

next stage circuit such as an mixer or a power amplifier.


















3.5
LU
3

2.5


100 200 300 400 500
Bit Rate (Mbps)

Figure 3-23. Measured EVM vs. bit rate (0.18 pm chip). At 2.5 GHz carrier
frequency, for EVMs lower than 5'. the bit rate of the modulator
ranges from DC to 500 Mbps


The frequency range of the carrier was also measured. The measurement

was done by keeping the bit rate fixed at 100 Mbps and monitoring the signal

constellation and EVM while changing the RF input frequency which is twice

the LO carrier frequency. As can be seen from Figure 3-22, within the carrier

frequency range of 1.75 GHz to 3.5 GHz, the modulator works fine with lower than

5.5'. EVMs (The IEEE 802.11a standard [22] specifies a maximum EVM of 5.1'.-"

for the peak data rate of 54 Mbps.). Another measurement was done to find out

the bit rate the modulator circuit can handle with a 2.5 GHz carrier. The resulting

EVMs at different bit rates are plotted in Figure 3-23. Although a 500 Mbps bit

rate can turn in a decent EVM of 5'. measurement showed that higher bit rate

would result in blurry constellation (see Figure 3-24) and degraded EVM (greater

than i.'- ), if the carrier frequency remained the same.























Figure 3-24. Constellation (EVM = .',) at bit rate greater than 500 Mbps (0.18
pm chip)

Actual .
Phasor error (EVM)

m actua h a r
/ Ideal
ideal Phasor



Figure 3-25. When the error vector is perpendicular to the ideal phasor, the phase
variation is the 'li.--- -


EVM is a direct measure of the accuracy of a modulator. The contributors

to the degradation in EVM could include variations in phase and amplitude,

phase noise, poor frequency response at any stage of the system, poor return loss,

and virtually any other RF system related problems. At a certain EVM value,

the maximum possible phase variation, AK, occurs in the case of Figure 3-25,

where the error vector is perpendicular to the ideal phasor. For EVM = i'- AP

approximately equals 0.085 radian. According to Figure 3-9, this variation will

not affect the PSD significantly. Same analysis can be applied to the amplitude


DATAs



A
" lk










Smideal

Ideal Phasor error (EVM)

Figure 3-26. When the error vector is in the same direction as the ideal phasor, the
amplitude variation is the 'i--.: -1


variation, where the worst case scenario is as in Figure 3-26. Again, at a i'.

EVM, the variation in amplitude has little impact on the modulator's output PSD,

especially considering that the signal will be amplified through an amplifier in

saturation.

A brief performance summary for the constant envelope phase shift modulator

(0.18 pm chip) is listed in Table 3-3.

Table 3-3. Summary of modulator performance (0.18 pm chip)

Function Constant envelope phase modulation
Technology 0.18 pm C'\OS
Die size 0.5 mm2
Power supply voltage 1.8 V
Current dissipation 2 mA
(excluding output buffers)
EVM 2 ('. ((2.5 GHz and 100 Mbps)
Carrier frequency range 1.75 GHz to 3.5 GHz
Bit rate DC to 500 Mbps


3.4.2 Modulator IC Fabricated in 0.13 pm CMOS Process

The modulator design was also fabricated in a 0.13 pm logic C'\ OS process

with a supply voltage of 1.2 V. The schematic of the complete modulator test chip

circuit in the 0.13 pm process is shown in Figure 3-27. The microphotograph of

the 0.13 pm chip is shown in Figure 3-28. The 0.83 mm2 chip size is considerably

1i.~-- r than the 0.18 pm chip, because more pads for DC biases were placed on this


























To










F D
NOo








,, T [ I I <1 ,, T 1






I-- ------------------------------ ----L

o ,o
*l 0 a






0 r)












I Do al





Z3 -n T- I










------------------------ L --------------------.------ ---------------------------------------



Figure 3 27. Complete modulator test chip circuit (0.13 pm chip)
































Figure 3-28. Die microphotograph of the modulator IC (0.13 pm chip)


chip for the purpose of separately controlling of the three stages of output buffers

and adjusting the amplification gains. The reason for more controls and biases is

that big metal capacitors, whose parasitic values are high, were used in the layout

as inter-stage coupling capacitors because no MIMCAPs are available in a logic

process.

Figures 3-29 and 3-30 are the measured constellation and the I/Q plane

diagram, respectively, of the 0.13 pm chip's output. The measurement setup was

almost the same as for the 0.18 pm chip, except that more DC power supplies were

used for output buffer bias control. At a carrier frequency of 2.5 GHz and a bit rate

of 100 Mbps, the measured EVM was 3.5' .


























Figure 3-29. Measured constellation (0.13 pm chip) of the modulated signal (EVM
= 3.5' )


The 0.13 pm test chip also has a measured current dissipation of 2 mA

(excluding output buffers) with the supply voltage being 1.2 V, so the power

consumption was even smaller than the 0.18 pm chip. The operating carrier

frequency (at a 100 Mbps bit rate) ranges from 1.5 GHz to 3.3 GHz, with the

measured EVMs all equal to or below ,!'. (Figure 3-31). However, the maximum

bit rate appeared to be much lower than the 0.18 pm chip, as can be seen from

Figure 3-32. At a 250 Mbps data rate, the EVM value is already 6.5' with the

carrier frequency maintaining the same at 2.5 GHz. Compared to the previous chip,

the smaller operating frequency range and bit rate range are probably caused by

the coupling capacitors used in the layout. Big metal capacitors with considerably

higher parasitic values were used instead of MIMCAPs, which led to higher

inter-stage power loss in the circuit. Therefore, the output signal level decreased,

degrading SNR and hence EVM. A performance summary for 0.13 pm modulator

test chip is listed in Table 3-4.


1$


* *1


A U


9
9

























Figure 3-30. Measured I/Q plane diagram (0.13 pm chip) of the modulated signal

Table 3-4. Summary of modulator performance (0.13 pm chip)

Function Constant Envelope Phase Modulation
Technology 0.13 pm C'\OS
Die size 0.83 mm2
Power supply voltage 1.2 V
Current dissipation 2 mA
(excluding output buffers)
EVM 3.5'. ((2.5 GHz and 100 Mbps)
Carrier frequency range 1.5 GHz to 3.3 GHz
Bit rate DC to 225 Mbps


3.4.3 Performance Comparison

From the experiment results of both modulator test chips, it can be seen that,

in addition to the functionality and the low power consumption, the modulators of

this work work at a big range of operating frequency and high data rates. Table

3-5 compares this work to some of the reported modulators of similar functions.

















7


6-


LU 5


4


3-
1


1.5 2 2.5
Carrier Frequency (GHz)


3 3.5


Figure 3-31. Measured EVM vs. carrier frequency (0.13 pm chip). At 100 Mbps
bit rate, for EVMs lower than !'. the modulator can operate at a
carrier frequency between 1.5 GHz and 3.3 GHz


150
Bit Rate (Mbps)


Figure 3-32. Measured EVM vs. bit rate (0.13 pm
frequency, for EVMs lower than 5.5' .
ranges from DC to 225 Mbps


chip). At 2.5 GHz carrier
the bit rate of the modulator


























Table 3-5. Comparison of modulator performance


Reported Power Operating Bit rate
Reported Bit rate
modulators consumption frequency range (Mbps)
(mW) (GHz)
Analog Devices
A g D s 675 0.7-2.7 0-160
AD8349
MITEQ
MITE7Q 1800 6.4-7.4 0-100
SDM6474LCDQ
C\iOS I/Q 175 2.4 1
modulator #1 [23]
CM'OS I/Q 187.8 1 3.75
modulator #2 [24]
this work 3.6 1.75-3.5 0-500















CHAPTER 4
A DIGITALLY CONTROLLED PHASE SHIFT MODULATOR FOR
ARBITRARY DATA PATTERNS

Constant envelope modulations, such as MSK and GMSK, allow the power

amplifier (PA) to be operated in saturation, and can achieve greater efficiency than

linear modulations. The test modulator introduced in the previous chapter can

generate a constant envelope modulated signal, and therefore can be used in a low

power transmitter utilizing a non-linear PA, such as a Class B or a Class C PA.

The standalone test modulator introduced in the previous chapter only

accommodate a fixed data pattern, which results in a signal point moving

sequentially in the same direction in full circles on the constellation. The reasons

for that design were that it can simplify the digital circuitry to some extent and

that measurement will be relaxed in terms of the requirementS for equipment,

because a random or pseudo random data generator would not be necessary.

But to be integrated in a transmitter, the modulator should be able to take

arbitrary input data and modify them onto the carrier. Therefore, the previous

modulator circuit was modified accordingly, with no 1 i i" changes made to the

architecture.

4.1 Design Details

The test modulator for fixed patterned data, which was an internally generated

clock signal and translated into a phasor moving repetitively and sequentially in









circles on the constellation as introduced in the previous chapter, has been proved

to have very good performance. Therefore, the design of a modulator for arbitrary

data should be aimed to involve minimal modification. Hence, the fundamental

circuit architecture of this modulator for arbitrary data patterns remains the same

as the test modulator, except that the clock generation and digital control circuit

needs to be modified in order to take the input of serial digital data bits. However,

the internal clocks for timing the multiplexers and for controlling the switches of

the phasor combining circuit are still generated from one external clock input.

Let us take a look back at the example of an MSK signal in the previous

chapter. In Figure 3-1(a), the serial digital data bits are 10110010 before being

converted to two parallel data streams (I stream 1101 and Q stream 0100). The

resulting phasor movement can be seen in Figure 3-1(b) and is redrawn here in

Figure 4-1 for convenience of discussion. It should be noted that A, B, C, and D

in this figure are the four boundary phase points for the bit intervals. The signals

with these four phases can be generated at the output of the divider, as can be seen

in Figure 3-27.

As explained in the previous chapter, the modulator circuit needs to select the

correct boundaries for each bit interval, which is to be done by the two 4:1 MUXes.

Because the phasor would move from one boundary point to an .,l1i ient other one

during each bit interval, two boundary points (starting point and ending point)

need to be selected by the two MUXes respectively, which is what is meant by the

1p' -" ii state and the "ir :;: state in the previous description of the modulator

circuit. For this 8-bit-interval MSK example, Figure 4-2 shows the boundary points





59




Q


4B D


C A


5B 61


Figure 4-1. Movement of the phasor when serial data stream 10110010 is MSK
modulated









I 1: I 0 I I:0
I 11!

0 i 1 ii 01




A B A D C B A BC

Figure 4-2. Boundary phases on the constellation for the 8 bit intervals
Figure 4-2. Boundary phases on the constellation for the 8 bit intervals









A- 2:1
D MUX
2:1
clock MUX out
BC 2:1
B MUX !
Sdata
Clock

clock _F7 _- ] [- ] -F -

data m o 1 1 o o o

out A BA D C B A B -

Figure 4-3. How a state stream can be generated at the output of a MUX

at the 8 bit intervals. For these 8 intervals, the starting points, or the p -" : '

states, which are to be selected by one of the two MUXes, are A, B, A, D, C, B,

A, and B, while the ending points, or the i :;." states, which are to be selected by

the other MUX, are B, A, D, C, B, A, B, and C. The ending point of the 8th bit

interval C will be the starting point of the 9th should there be one. For discussion

purpose, the output of an MUX for a series of bit intervals is called state stream.

It can be seen that, the phase streams at the two MUXes' output are the same,

except that the MUX for the pI' -' i, states generates a state stream that is

d. 1 i,. ,1 by one bit interval, compared to the state stream generated by the MUX

for the "next" states.

Figure 4-3 illustrates how a 4:1 MUX is designed and controlled to select the

correct phase states according to the input seriel data bits. Note that the "clock"

here is not the clock input to the entire chip but rather one that is generated









therefrom. As in the previous design, "clock" is internally generated by the on-chip

digital circuit section and its rate is twice the rate of serial data. This MUX can be

used for the i., :;." state stream, while for the p,, ini state stream, both "clock"

and "data" are d. 1 iv .1 by one bit interval using a flip-flop latch as in Figure 3-16.

Efforts also need to be made to ensure the edges of the digital data bits and the

clocks are lined up.

The block diagram of the modified modulator for arbitrary data patterns is

shown in Figure 4-4. It can be seen that the main architecture of the modified

modulator for arbitrary data patterns remains the same as the one with a fixed

data pattern. The continuous phase change of MSK within any quadrant is still

implemented in four discrete steps. With pseudo random input data bits, the

ideal normalized output power spectral density (PSD) will be the one in Figure

3-7 for the case of 4 phase shifts per quadrant. We can take it out and show

it in Figure 4-5. The ideal constellation for MSK modulated random data is a

constant envelope circle, with four data points each in one quadrant, as in the case

of QPSK/OQPSK. Figure 4-6 illustrates what the constellation will look like.

4.2 Experimental Results

The modulator circuit for arbitrary data patterns was fabricated in a 0.18 pm

mixed signal C'\!OS process. The microphotograph of the chip is shown in Figure

4-7. The area of the chip is 0.677 mm2

Figure 4-8 shows the measurement setup for testing the modulator circuit

with pesudo random input data bits. The signal generator provides an AC signal











4 LO output
signals with


DATAin
CKin


Figure 4-4. Modulator circuit for arbitrary data patterns




10


-o
10------------------------------------------------------------

-10 ........................- ...------. ----
S-10\
-& 10 ------------------------ I1---- ---------

o')


S-30
(D

S.-40--- --


3_ -50


--10 -5 0 5 10
(f-fc)/BR

Figure 4-5. Ideal normalized output PSD for the modified modulator if pseudo
random input data are applied





























Figure 4-6. Ideal constellation for the modified modulator if pseudo random input
data are applied







GN xL Nias









Ki







Figure 4 7. Die microphotograph of the modulator circuit for arbitrary data
patterns










To DC sources
I -t-- t-t-


Ale500
S 500 HP 8563E
Agilent E8254A SMA .""""~. i. ASpectrum Analyzer
Signal Generator f t1hm o Iti
i2xLO+ RFout
o0 Balun I
2xLO- RFout- -- S
o DATAin CKin fr o rPA


/ I I I \. \ .- LPC

__ I Agilent 89600S
VSA
S Agilent N4906A
:Data Clock BERT

Figure 4-8. Measurement setup for testing the modulator circuit with pesudo
random input data bits


whose frequency is twice the desired carrier frequency, or LO frequency, for the

modulator. The on-chip 2:1 frequency divider will generate four LOs whose phases

are in quadrature with one another. Agilent N4906A bit error rate tester (BERT)

is used to provide the circuit with data and clock inputs. It should be noted that

the BERT data output has the same rate as its clock output, while the actual

modulator circuit needs an input clock rate that is four times the input data rate

because the input clock will be used to generate all the on-chip clock and control

signals, including the "clock" signal in Figure 4-4. However, the measurement is

feasible using the BERT despite its seemingly wrong data rate, because the input

data bits to the modulator are being latched by flip-flops at the rate of one of the

internally generated clocks, which is the desired data rate. Therefore, the flip-flops

act like a sampler which samples the higher-rate data input at the desired data rate

which the circuit needs. The BERT can generate hardware based pesudo random





























Figure 4-9. Measured constellation at 2.5 GHz carrier frequency and 12 Mbps bit
rate


bit streams (PRBS) up to 223 1, therefore the actual sampled data into the

modulator circuit are a PRBS of 221 1 because the data rate after sampling is

one fourth the rate of the BERT's data output. The modulator's differential output

signal is measured by terminating one end with 50 Q and externally amplifying the

output of the other end. The amplified signal is connected to a spectrum analyzer

and a VSA hardware via a power spliter. The VSA hardware is connected to a PC

where the VSA software is installed. The modulated signal will be down-converted

and sampled by the VSA hardware and demodulated by the VSA software. The

demodulated signal's constellation and I/Q diagram can be dip! i' '1 on the PC's

monitor.

The Agilent 89600S VSA is limited to a bandwidth of 36 MHz by its digitizer.

Therefore, the data rate of a modulated signal it can measure is also limited. To

accurately demodulate a signal, ideally all the sidelobes in the spectrum should be




























Figure 4-10. Measured I/Q diagram at 2.5 GHz carrier frequency and 12 Mbps bit
rate


included in the frequency span of the VSA. Since the lowest output clock/data rate

of the BERT is 48 MHz, the modulator was measured at 2.5 GHz carrier frequency

and 12 Mbps bit rate. Figure 4-9 and Figure 4-10 show the measured constellation

and I/Q diagram respectively. At this carrier frequency and bit rate, the average

measured EVM was 7'.

Figure 4-11 shows the power spectrum of the modulated signal measured by

a spectrum analyzer, and it can be seen that the measured result is quite similar

to the simulation result in Figure 4-5. Figure 4-12 allows for a closer look at the

mainlobe and its .,1i i,'ent sidelobes of the measured spectrum. It can be seen that

the measured mainlobe width is approximately 18 MHz, which is 1.5 times the bit

rate, and the first sidelobes are about 12 MHz, which is one bit rate, away from the

center frequency. These are consistent with the simulation result in Figure 4-13.









RL 100.dBm 10dBI 2.5017GHz
















CENTER 2.S000GHz SPAN 500.0MHz

Figure 4-11. Measured power spectrum at 2.5 GHz carrier frequency and 12 Mbps
bit rate


The measured power spectra at some higher bit rates can be seen in Figure

4-14 and Figure 4-15, where the bit rates are 50 Mbps and 100 Mbps, respectively,

while the carrier frequency remains the same at 2.5 GHz. The output signal's

power level is around -3 dBm. Note that for these measurement results the

resolution bandwidth of the spectrum analyzer was set to 3 MHz. The power

consumption of this modified modulator is the same as the previous modulator

with the fixed data pattern. That is, the modulator without the output buffers to

drive 50 Q loads dissipates 2 mA current, while the output buffers need a total of

nearly 10 mA bias current.

This modified modulator circuit for arbitrary data patterns is a great

candidate to be used for personal area networks complying with the ZigBee

technology. The IEEE 802.15.4 standard [25], which a ZigBee-ready transceiver

should be compliant to, is designed for low cost, low power consumption wireless


































Figure 4-12. Measured power spectrum with a smaller frequency span at 2.5 GHz
carrier frequency and 12 Mbps bit rate


10

o 0
m
-o

v,
-10

r -20

-30
i-)
-40
(l)
a -50

o -60

-70


-2 -1.5 -1 -0.5 0
(f-fc)/R


0.5 1 1.5 2


Figure 4-13. Simulated power spectrum of the modulator
random input data bits


output with pesudo





























Figure 4-14. Measured power spectrum at 2.5 GHz
bit rate


carrier frequency and 50 Mbps


1,1 1 11


Figure 4-15.


Measured power spectrum at 2.5 GHz
bit rate


carrier frequency and 100 Mbps


I I I I i I I I


I I











Applications
Zigbee or OEM
Application Profiles

- - - -



Alliance
Platform

IEEE 802.15.4
PHY Layer
2.4GHz 868/915 MHz


Silicon Application


Figure 4-16. IEEE 802.15.4 and ZigBee working model


applications with moderate data rates. The standard specifies the Physical (PHY)

and Media Access Control (\!AC) l1-.-rs at the 868 MHz, 915 MHz and 2.4 GHz

ISM bands, and the chip modulation schemes are O-QPSK with half-sine pulse

shaping (\!;SI) for 2.4 GHz PHY and BPSK with raised consine pulse shaping

for 868/915 MHz PHY, respecitvely. The lI--i,-~ of the IEEE 802.15.4 standard

and ZigBee technology are shown in Figure 4-16 [26]. The 2.4 GHz PHY of the

IEEE 802.15.4 standard is more attractive to the wireless industry because the 2.4

GHz unlicensed ISM band is globally available and therefore flexible in application

designs [26]. The chip rate for the 2.4 GHz PHY is 2 Mchips/s from a data rate

of 250 kbps, and the specified EVM requirement is ;:.'. The average EVM result

of this modulator at 2.5 GHz carrier frequency and 12 Mbps bit rate is 7'. and

the recorded worst-case EVM value is around 10' which is still well below the

requirement limit.











RBW 100 kHz RF Atr 30 dB
Ref Lvl VBW 100 kHz
O dBm SWT 5 ms Unit dBm




-3m





-40 _





-re
-60

-7







Center 2.45 GHz 1 MIHz/ Span 10 MHz


Figure 4 17. Output spectrum of the CC2420 transmitter



Figure 4 17 shows the output power spectrum of the CC2420 transmitter [26].


The CC2420 is a low-cost transceiver designed for low-power, low-voltage RF


applications in the 2.4 GHz ISM band. It is a ZigBee-ready C\ I OS device using


a mainstream 0.18 pm technology. As can be seen from its output spectrum,


the mainlobe occupies a bandwidth of approximately 3 MHz, which is twice the


2 Mchip/s chip rate in the IEEE 802.15.4 specification. The modulated signal


transmitted by the CC2420 has a worst-case EVM of 211'. [26]. Therefore, the


modulator circuit of this work surpasses the performance of the CC2420 in terms


of transmit modulation accuracy. It also supports much higher data rate than the


CC2420.






72


The performance of the modulator circuit for arbitrary data patterns is

summarized in Table 4-1.

Table 4-1. Performance summary of the modulator for arbitrary data patterns

Function Constant Envelope Phase Modulation (l\ Sli-like)
Technology 0.18 pm C'MOS
Die size 0.677 mm2
Power supply voltage 1.8 V
Current dissipation 2 mA
(excluding output buffers)
EVM 7'. ((2.5 GHz and 12 Mbps)















CHAPTER 5
DESIGN OF A DIRECT CONVERSION TRANSMITTER

In the previous chapter, we introduced a digitally controlled phase shift

modulator circuit for an MSK-like modulation scheme, which is suitable for

ZigBee-ready IEEE 802.15.4-compliant devices. Such devices, as the standard

is designed for, are expected to be low cost and low complexity. In addition,

the compliant system implementations will enable long battery life by using the

power-saving features at the PHY, MAC, and network 1. -ir specified by the

standard [26].

In addition to the functionality of the modulator, we also wanted to

demonstrate the modulator's suitability for high level integration. Therefore,

we integrated the modulator circuit into a direct conversion transmitter, which will

be introduced in the following sections.

5.1 Direct Conversion Transmitters

Many factors, such as function, power consumption, ease of integration, and

requirement of external components, can affect the choice of a specific transmitter

architecture for a specific standard and application. To comply with the low-cost

low-power nature of the IEEE 802.15.4 standard, the direct conversion transmitter

architecture is the best fit for efficient generation of the transmit signal.

Direct conversion transmitters appeal to designers of wireless systems for

their simplicity and low cost. The direct conversion architecture eliminates the










Baseband





VCO


Figure 5-1. Generic direct conversion transmitter utilizing the conventional I/Q
modulator


intermediate frequency (IF) stage and its accompanying IF surface acoustic wave

(SAW) filter, mixer, and voltage-controlled oscillator (VCO) components. Fewer

parts means lower total cost, smaller devices and greater reliability. It also means

less insertion loss and less power consumption. Although a superheterodyne

transmitter is generally considered a higher-performance transmitter, if the system

requirements can be met with the direct conversion transmitter, which is more

suitable for high levels of integration, then a more economical radio can be realized.

In direct conversion transmitters, modulation is done directly to the carrier

at the designated output frequency and an upconversion is not needed. A simple

direct conversion transmitter generally consists of an oscillator, a modulator, and

power amplifiers, while a complicated one would include a phase-locked oscillator.

Figure 5-1 [27] shows a simplified block diagram of a generic direct conversion

transmitter utilizing the conventional I/Q modulator as we introduced previously.









It can be seen that the transmitter includes baseband processing and analog

mixing through two mixers. The digitally controlled constant envelope phase

modulator of this work has the function of realizing the I/Q modulation schemes.

It also has many advantages over the conventional I/Q modulators. Therefore, we

incorporated this modulator into the design of the direct conversion transmitter,

whose block diagram is shown in Figure 5-2. In this design, a VCO will generate

a signal at twice the designated carrier frequency, which will be divided down

by a 2:1 frequency divider to the output RF frequency of the transmitter. The

output signal from VCO will be connected to the modulator for arbitrary data

patterns, where four signals whose phases are in quadrature with one another will

be generated from the VCO's output by the 2:1 frequency divider. The output of

the modulator will be an MSK-like modulated signal with a constant envelope,

which allows for the use of a simple low-cost and relatively non-linear succeeding

power amplifier (PA). It should be pointed out that no baseband processing is

needed in this transmitter architecture. With a VCO preceding the modulator,

and a PA following it, the modulator can be easily placed into a direct conversion

transmitter chain. The blocks after the PA, such as the antenna, are omitted in the

block diagram and in the design as well.

5.2 Design of an Inductor-Capacitor-Based Voltage Controlled
Oscillator

The VCO is an integral part of tod w-'s high speed or RF communication

circuits. Transmitters and receivers both require high-performance VCOs.

Ring-oscillator and relaxation-type VCOs are limited in their ability to support













VCO \ Envelope Phase PA
Modulator

Figure 5-2. Designed direct conversion transmitter to be designed utilizing the
constant envelope phase modulator


narrowband applications with high output levels at low cost, whereas inductor-

capacitor-based VCOs (LC-VCOs) can provide good performance at the low

costs required by many applications. In particular, LC-VCOs have lower phase

noise than ring-oscillator VCOs, making it a necessary design choice when good

phase-noise performance close to the carrier is required.

An LC-VCO is an oscillator where the principal variable or tuning element

is a varactor capacitor. The VCO is tuned across its band by a DC voltage,

Vt,,, applied to the varactor to vary the net capacitance applied to the tuned

circuit. An LC-VCO typically consists of an LC tank and a circuit that generates

a negative conductance for compensating the losses in the LC tank. The LC-VCO

core circuit is based on a cross-coupled MOS transistor pair, which creates the

effective negative conductance. The following equation has to be fulfilled to achieve

oscillation start-up conditions.
1
G, > (5-1)
Rp

where G, is the negative conductance, and Rp is the equivalent parallel resistance

of the LC tank.




















Cload- I Cvl Cv2l i [_Cload


M I M2.





Figure 5-3. Designed C'i\OS LC-VCO

5.2.1 Small Signal Model of a CMOS VCO

The topology of the designed LC-VCO for the direct conversion transmitter

is shown in Figure 5-3. It uses on-chip inductors (L1 and L2) and varactors (Cv1

and Cv2). The load usually is the input of C\ !OS buffers and hence capacitive.

Figure 5-4 is drawn based on the equivalent circuit model of an C'\ OS oscillator

in [28], where the broken line in the middle represents either the common mode or

ground. The symmetric planar spiral inductor model of Figure 5-5 with identical

RC loading on both terminals is used as a part of the tank model. The parasitic

capacitance of inductors is represented by CL, which is equal to C, + Cp. R8 is the

parasitic resistance in series with inductance L. Rp represents the shunt resistance








Cload Cload
I II
T------ Ulo~ ad -----------Ba

r- -- -------------
CL=Cs+Cp I CL=Cs+Cp
II II

Rp Rp Inductors
I
L Rs Rs L
-- ---------------Rv Cv -
V' M, Varactors
',---- I--- --- -- ------ ,

r -- - -I - -
CMOs RMOs RMOS CMOS

go I go
STransistors
-g I -gm
-------------


Figure 5-4. Equivalent circuit model of the designed C'\ OS LC-VCO

across the port and ground. The quality factor (QL) of the L-R series combination

is then given by QL = (L)/R,, where u is the operation frequency.

Varactors are modeled with a capacitor Cv in series with a resistor Rv.

The parasitic capacitances from a MOS transistor are described as CMos, which

includes Cdb, Cgs, Cgb and Cgd. The series resistance RMos mainly comes from the

substrate resistances associated with source or drain to substrate junction capacitor

(Cdb or Csb) and gate to substrate junction capacitor (Cgb) [29]. The quality factor
for a capacitor, Qc, is given as 1/(wRC), where u is the operation frequency, R

is the parasitic resistance in series with capacitance C. Therefore, large contact









Cs

II
L Rs




CP Rp Rp CP




Figure 5-5. Symmetric spiral inductor model

arrays are necessary to lower RMos to improve the quality factor of CMOS. gm and

go are small-signal transconductance and output conductance of the transistors,

respectively.

5.2.2 Noise Issue Considerations

The noise of the free-running VCO is a dominant noise contributor in an RF

communication circuit. In that respect, MOS LC-VCOs especially represent a

challenge for RF circuit design because of the high 1/f noise in the C'\ OS process.

Moreover, the scaling of C'\ IOS technology leads to lower supply voltage and

hence lower VCO tank voltage swing, which could degrade the VCO's phase noise

performance. Close-in phase noise is a i i i"r drawback for Ci\ OS VCOs because of

the high 1/f noise of the MOS transistors. A great deal of the close-in noise comes

from the up conversion of the 1/f noise through the tail transistor. Compared

to NMOS transistors, PMOS transistors contribute less thermal noise and 1/f









noise. Moreover, since the 1/f noise is inversely proportional to a transistor's gate

area, a PMOS transistor, M3, with large width and length (450 pm/500 nm) is

therefore used as the tail transistor to reduce the close-in phase noise. Meanwhile,

since PMOS transistor's overdrive voltage is low thanks to its large width, it

leads to a smaller voltage drop across the transistor's source and drain when the

transistor is working in saturation. This adds to the advantages of using a PMOS

transistor for the tail current source in that it can leave more headroom for the

VCO's output voltage swing, which also helps improve phase noise performance

[30]. However, it should be pointed out that, because NMOS transistors have

smaller size than PMOS transistors to achieve the same Gm, cross-coupled NMOS

transistors (\ I and M2) are used for the negative conductance generation part

of the C\ !OS LC-VCO circuit, in order to achieve a larger tuning range than its

PMOS counterpart.

For LC-VCOs, the overall Q of the LC tank is also a key factor that

determines the phase noise performance. Normally, the Q factor of the LC tank

is determined by the inductor. A differential spiral inductor with a polysilicon

patterned-ground shield (PGS) is used in this VCO design to achieve a higher Q.

This is also a good match to the differential VCO topology. A large value of the

inductance L, or a small C/L ratio, can relax the requirement for the value of Gm,

and hence reduce power consumption [31]. In this work, the value of L is designed

to be 880 pH for the oscillating frequency of 5 GHz. Varactors are implemented

with MOS capacitors. A MOS transistor with its drain, source, and bulk (D, S, B)

connected together can realize a MOS capacitor, and the value of the capacitance













ilin II
11111 I.
nun I
#1*211 ~ir


Figure 5-6. Layout of the LC-VCO circuit









is dependent on the voltage between bulk (B) and gate (G), VBG. MOS varactors

have an approximately similar tuning range and better phase noise performance

than diode varactors [32]. The value for the varactors was targeted at 800 fF for an

oscillating frequency of 5 GHz with an estimated tuning range from 492 fF to 1.056

pF. A varactor's tunability is defined to be Cma/Cmin. Therefore, the estimated

tunability of the varactor is 2.15.

The layout of the LC-VCO circuit is shown in Figure 5-6. The VCO is

designed to oscillate at around 5 GHz, which is twice the desired LO frequency.

The output of the VCO will be connected to a 2:1 frequency divider, which was

introduced previously as one of the circuit blocks for the modulator, to generate

four LO signals with phases in quadrature with one another. The simulation result

of the generated quadrature LO signals can be seen in Figure 5-7.

5.3 Design of a Power Amplifier

5.3.1 Basic Characterics of a Power Amplifier

RF/\ Ii rowave power amplifiers are an important circuit component used

in almost every communication system including cordless and cellular telephone,

base station equipment, satellite communications, wireless LANs, and so on.

However, they remain a challenging building block in RF circuit designs. Some

of the important characteristics of an amplifier include linearity, efficiency, and

output power. Usually there are tradeoffs between these characteristics. For

example, improving amplifier's linearity will degrade its efficiency. A linear










Tsi.. n iiFbr


Figure 5-7. Simulated result of the output of VCO plus divider


amplifier preserves the details of the signal waveform, that is to -i, [33]


Vo(t) A. (t)


(5-2)


where, Vi and Vo are the input and output signals respectively, and A is a constant

gain. But if Vi contains higher power, then the amplifier could produce nonlinear

distortion.

The drain efficiency of a power amplifier (PA) is a measure of the amplifier's

ability to convert the dc power of the supply into the signal power delivered to the

load. The definition of drain efficiency is as follows: [33]


I .:,',.i power delivered to load
DC power


i









If an ideal amplifier exists, the power delivered to the load would equal the

power taken from the DC supply. In reality, an amplifier efficiency of one is not

possible, especially in RF circuits. In many high frequency systems, the output

stage and driver stage of an amplifier consume power in the amplification process.

However, some power amplifiers provide higher efficiency than others. What kind

of power amplifier should be designed depends on the application requirements.

Generally -I' 1;.- linear modulations employ amplitude change to carry the

data information, and hence can only allow for linear but not-so-efficient power

amplifiers. However, for constant envelope modulations, power efficient non-linear

amplifiers is an appealing candidate because signal distortion will not be a concern.

5.3.2 Classes of Power Amplifiers

Depending on the relation between the input and output signals, circuit

configurations, and modes of operation, power amplifier circuits can be classified

into different classes. RF/microwave power amplifiers are generally defined to

operate in class A, B, AB, C, D, E, and F. These classes are implemented by

selecting bias conditions of the active device and by designing input and output

match, to meet system requirements in terms of output power, efficiency (or DC

power consumption), linearity conditions (modulation schemes), frequency range,

size, weight, and cost [34].

However, a trade-off between the efficiency and linearity exists for PAs of any

class. That is, higher efficiency means poorer linearity and vice versa. For example,

let us compare class A, B, and C PAs to see the trade-off. Among the three, the










Class A Class B Class F
Ip ..........................Ip ....p................ Ip .................
..............................
-.Q

I ""'
-I \Q Q
VDD VDD VDD

Figure 5-8. Voltage-current relationships for various classes of PA


class-A amplifier has the highest linearity. The amplifier operates in the device's

linear region and is conducting current constantly, which means more power loss

and lower power efficiency. An ideal class-B amplifier operates at zero quiescent

current, because the output current is off for half of an input sinusoidal signal

cycle. This lowers the power consumption and improves the efficiency, but the

linearity of the device is degraded. In applications where linearity is not a concern,

a class-C amplifier can be a good choice. A class-C amplifier is biased such that

the output current is zero for more than half of the input signal cycle. Therefore,

its efficiency will be even higher than a class-B amplifier. The theoretical values

for the highest possible efficiency of class A, B, and C amplifiers are 5(0'. 7''-

and 1(11' respectively. In practice, however, an efficiency of 101i' is improbable

because the current cannot be switched off completely.

The different classes are further discussed below.

Class A. The active Device in a class A PA is conducting at all times. In

other words, there is current for the full cycle (3600) of an input sinusoidal signal.

The quiescent point, Q, is set to approximately the center of the device current,

as can be seen in Figure 5-8 [34], where Ip and VDD are the peak current and