<%BANNER%>

Analog Baseband Processor for CMOS 5-GHz WLAN Receiver

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PAGE 1

ANALOG BASEBAND PROCESSOR FOR CMOS 5-GHZ WLAN RECEIVER By OKJUNE JEON A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2005

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ii ACKNOWLEDGMENTS I would like to express my deep appreciation to my supervisory committee chair (Robert M. Fox) for his guidance and support. His insight into circ uits and his patience and encouragement made my study possible. I also thank committee members William R. Eisenstadt, John G. Harris, and Oscar D. Crisalle for their helpful advice. Special thanks go to Dr. Brent A. Myers at Conexant Systems Incorporated for supporting my research project including tw o fabrications and giving me the summer internship experience. Hi s real-world comments throughout the research work and advice as a committee member are greatly appreciated. I thank my fellow graduate colleagues, Yus Ko, Choongeol Cho, Hyeopgoo Yeo, Jangsup Yoon, Kooho Jung, Jongsik Ahn, Ming He, Tao Zhang, Qizhang Yin, Xueqing Wang (Andy), Xiaoqing Zhou, and Su Dee p. Also, I thank Dr. Hyungjong Ko, Dr. Inchang Seo, Dr. Sanghoon Choi and Changjin Lee, who were former graduate students in the Analog Integrated Circuit Laboratory. My sincere thanks are given to my parents and parent-in-laws. I would like to offer my greatest appreciation to my lovely wife Sanghyun and dear children Yerin and Hohyun, who always stand by me with love a nd prayer. Finally, I would like to give thanks and glory to the lord God of Ebenezer.

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iii TABLE OF CONTENTS page ACKNOWLEDGMENTS..................................................................................................iiLIST OF TABLES...............................................................................................................vLIST OF FIGURES...........................................................................................................viABSTRACT....................................................................................................................... xi CHAPTER 1 INTRODUCTION........................................................................................................11.1 Motivation...............................................................................................................11.2 Research Goals.......................................................................................................21.3 Outline of the Dissertation......................................................................................32 BACKGROUND..........................................................................................................52.1 IEEE 802.11a Standard...........................................................................................52.2 System Specifications for WLAN Receiver...........................................................72.3 Receiver Architecture and Analog Baseband Signal Chain...................................92.4 AGC Fundamentals..............................................................................................123 OFDM SIGNAL AMPLITUDE ESTIMATION........................................................183.1 OFDM Signal Characteristics...............................................................................183.2 OFDM Signal Generation.....................................................................................203.3 Analog OFDM Signal Amplitude Estim ation with Statistical Simulation...........223.4 Accuracy Boundary for Received OFDM Short Trai ning Symbols.....................264 SEVENTH ORDER ELLIPTIC LOW-PASS GM-C FILTER..................................284.1 Introduction...........................................................................................................284.1.1 Specifications.............................................................................................284.1.2 Filter Topology...........................................................................................30

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iv 4.2 Filter Design I.......................................................................................................324.2.1 Gm-C Filter with Amplitude Scaling.........................................................324.2.2 Gm Cell Circuit Design..............................................................................344.2.3 Dealing with Para sitic Capacitance............................................................374.3 Filter Design II......................................................................................................394.3.1 Avoiding Floating Capacitor......................................................................394.3.2 Parasitic Capacitance Compensation..........................................................404.4 Simulation Results................................................................................................424.4.1 AC Response and Tuning Range................................................................424.4.2 Transient Response, Noise and Linearity...................................................435 AUTOMATIC GAIN CONTROL.............................................................................485.1 Introduction...........................................................................................................485.2 AGC Algorithm....................................................................................................505.3 Circuit Design.......................................................................................................555.3.1 Variable Gain Amplifier.............................................................................555.3.2 Differential Difference Amplifier...............................................................615.3.3 RMS Detector.............................................................................................625.3.4 Computation Block.....................................................................................645.3.5 Switched Gain Control 2............................................................................695.4 IC Implementation and Measurement..................................................................735.4.1 IC Implementation with Embedded Test Points.........................................735.4.2 Simulation Results......................................................................................775.4.3 IC Measurement and Analysis....................................................................866 SUMMARY AND FUTURE WORK......................................................................1026.1 Summary.............................................................................................................1026.2 Suggestions for Future Work..............................................................................105 APPENDIX SCHEMATIC OF TEST BOARD...........................................................107LIST OF REFERENCES.................................................................................................109BIOGRAPHICAL SKETCH...........................................................................................113

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v LIST OF TABLES Table page 2-1. Receiver performance requirements............................................................................83-1. Statistical simulation result for 5000 symbols (Max Peak = 0.607)..........................244-1. Spreadsheet to compute parasitic capac itance, number of dummy cells, and main capacitor value at each node.....................................................................................394-2. Summary of characteri stics of the two filters.............................................................475-1. Summary of the simulati on and measurement results..............................................101

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vi LIST OF FIGURES Figure page 2-1. Frequency band allocation in the IEEE 802.11a standard............................................52-2. PLCP Protocol Data Unit frame format.......................................................................72-3. Specifications of the minimum sensit ivity signal channel with adjacent and alternate adjacent channels for 6 and 54Mbps data rates...........................................92-4. Architecture for th e 5 GHz WLAN receiver..............................................................102-5. Baseband signal chain block diagram........................................................................112-6. Receiver gain distribution plots for 6Mbps data rate.................................................132-7. Receiver gain distribution plots for 54Mbps data rate...............................................142-8. AGC structure with (a) nonlinear feedback loop and (b) linearized loop representation...........................................................................................................153-1. A typical analog OFDM si gnal in the tim e domain....................................................183-2. OFDM modulator.......................................................................................................203-3. Short training symbols: (a) I channel one symbol (0.8s) and 7 symbols, and (b) Q channel one symbol (0.8s) and 7 symbols.........................................................213-4. Data symbol generation in the discrete time domain.................................................223-5. Data symbol generation in continuous time domain..................................................233-6. Data distribution plots for 6 detectors........................................................................253-7. Standard deviation plot for 6 detectors.......................................................................253-8. OFDM short training symbol generation with channel effect....................................274-1. Channel attenuation requirements for the baseband low-pass filter...........................294-2. Frequency response (magnit ude and group delay) for (a) 6th order elliptic, (b) 9th order Chebyshev II, (c) 3rd order elliptic, and (d) 4th order elliptic filters...............31

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vii 4-3. LC prototype filters for (a) 3rd order and (b) 4th order elliptic low-pass filters..........314-4. 3rd order Gm-C filter...................................................................................................324-5. Internal node voltage plot of the 3rd order Gm-C filter: (a) before scaling and (b) after scaling..............................................................................................................334-6. 3rd order Gm-C filter after voltage scaling for internal nodes....................................334-7. Schematics of (a) unit Gm cell and (b) FC with CMFB unit.....................................354-8. DC transfer characteristics of a unit Gm cell: (a) V-I plot, (b) Gm plot....................374-9. Fully differential 3rd order Gm-C filter.......................................................................384-10. Avoiding floating capacitor: (a) Gm -C filter with floa ting capacitor, (b) substitution of floating capacitor at node V1, (c) additional circuit for current source to node V1.....................................................................................................404-11. 3rd order Gm-C filter avoiding floating capacitor.....................................................414-12. Internal node voltage plot of the 3rd order Gm-C filter avoiding floating capacitor...................................................................................................................414-13. Internal node voltage plot of the 3rd order Gm-C filter avoiding floating capacitor...................................................................................................................424-14. AC response simula tion result for Filter 2................................................................434-15. AC response simulation resu lt for Filter 2 with tuning............................................444-16. Transient response of the Filte r 2 at (a) 8.3 MHz and (b) 12 MHz..........................444-17. Noise in dB vs. frequency plot.................................................................................454-18. Linearity of 1 % THD vs. input signal volta ge for (a) Filter 1 and (b) Filter 2 in nominal case.............................................................................................................465-1. Conventional AGC loop composed of VGA, Peak Detector and Loop Filter...........495-2. Architecture of the proposed AGC algorith m; (a) block diagram and (b) time line..505-3. Switched Gain Control 1 of the AGC algorithm........................................................525-4. Switched Gain Control 2 of the AGC algorithm........................................................525-5. AGC with One-step Correcti on: the fine gain-setting step.........................................535-6. Schematic of the proposed VGA................................................................................56

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viii 5-7. Schematic of the replica bias circuit for VGA...........................................................605-8. Simulation result for finding op erating point in the replica bias circuit. The result verifies that the bias circuit (for V = 0.6 V) can operate only at the single operating point of VA = 1.26 V and VB = 0.66 V.....................................................605-9. Schematic of the proposed Diff erential Difference Amplifier...................................625-10. Schematic of the proposed RMS detector................................................................645-11. DC simulation results of the RMS detector with VCM = 0.48 and vin = –0.25 ~ 0.25 V: (a) currents I1,2 after squarer and (b) currents I3,4 after rectifier..................645-12. V-to-I and I-to-V convert ers in (a) differential V to single-ended I (b) singleended V-to-I, and (c) single-end ed I to differential V modes..................................665-13. Schematic of the proposed analog computation block. The arrows indicate the VGS’s that form the translinear loop.........................................................................685-14. Switched gain control block implem entation using latched comparators and transmission gates....................................................................................................705-15. DC simulation result of the single-e nded V-to-I and I-to-differential V converters (single-ended VC1 versus differential V C1).............................................715-16. Reference voltage generator VINIT has six taps for preset voltages and is implemented as serial and parallel connections of a root component resistor.........725-17. Reference voltage generator VTH provides threshold voltages (V–20dBm, V–22dBm and V–30dBm) either for short training symbol signal or for sine wave signal...........735-18. Proposed AGC circuitry with 7 test points...............................................................755-19. Output voltage buffer................................................................................................765-20. Test switches; (a) voltage switch, and (b) current switch.........................................785-21. DC gain control simulation for the VGA with inverse gain loop.............................795-22. DC simulation for Vin ve rsus Vout of the VGA at (a) –4 dB gain and (b) 16 dB gain........................................................................................................................... 795-23. AC response of the VGA; (a) gain and (b) phase.....................................................805-24. VGA input and output noise versus gain..................................................................815-25. Linearity of the 2-stage VGA in THD (%) versus input signal vo ltage plots at (a) –8 dB, (b) 0 dB and (c) 32 dB gain settings.............................................................81

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ix 5-26. Input versus output characteristic of RM S detector; (a) for sine wave signal and (b) for short training symbol....................................................................................825-27. Characteristic of V-to-I converter; (a) input versus output linearity and (b) step response....................................................................................................................825-28. Input versus output charact eristic of I-to-V converter..............................................835-29. DC simulation results of the computati on block for sine wave signal with the switched gain of (a) –3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB...............................845-30. DC simulation results of the computa tion block for short tr aining symbol signal with the switched gain of (a) –3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB.................855-31. Transient simulation result (step response) of the computation block.....................855-32. Transient simulation results of the AGC circuit for sine wave signal with final gain of (a) –3 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB...................................................875-33. Transient simulation results of the AGC circuit for sine wave signal with final gain of (a) 15 dB, (b) 20 dB, (c) 23 dB and (d) 28 dB.............................................885-34. Transient simulation results of the AGC circuit for short training symbol signal with final gain of (a) –3 dB, (b ) 1 dB, (c) 4 dB and (d) 9 dB...................................895-35. Transient simulation results of the AGC circuit for short training symbol signal with final gain of (a) 15 dB, (b ) 20 dB, (c) 23 dB and (d) 28 dB.............................905-36. Full chip layout floor plan of the AGC circuit including ESD bonding pads and decoupling capacitor between positive supply and ground......................................915-37. Die photo of the fabricated AGC circuit..................................................................925-38. Test board design for the 40-pin AGC circuit package............................................935-39. Test board with a packaged AGC sample plugged in..............................................935-40. Bias circuit with external resistor connection: (a) can ca use oscillation and (b) can fix the problem...................................................................................................945-41. Measurement results on device characteri stics with various embedded test point selections: (a) diode-connected NM OS in RMS detector (W/L=5/10 m), (b) diode-connected NMOS in cascode current mirror (W/L=3/3 m), (c) threshold voltage extraction (diode-connected NMOS ), and (d) measurement plot on bias current versus external resistor.................................................................................955-42. Measurement of on-chip resistor variat ion: (a) resistors between input nodes and (b) measurement results for 20 samples...................................................................96

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x 5-43. Gain control curve for the 2-stage VGA..................................................................975-44. 2-stage VGA gain with supply voltage variation.....................................................975-45. Stability of VGA gain with (a) bias current and (b) temperature variations............985-46. 2-stage VGA characteristic at 12 dB ga in: (a) input-output linearity, (b) SFDR.....995-47. Frequency response of the 2-stag e VGA: (a) measurement result and (b) simulation result.......................................................................................................995-48. Measurement result for input-output characteristic of the RMS detector..............1005-49. Measurement result for input-output ch aracteristic of th e V-to-I converter..........1005-50. Measurement result for input-output characteristic of the current mode computation block..................................................................................................101

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xi Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy ANALOG BASEBAND PROCESSOR FOR CMOS 5-GHZ WLAN RECEIVER By Okjune Jeon December 2005 Chair: Robert M. Fox Major Department: Electrical and Computer Engineering This dissertation discusses the design of an analog baseband processor including channel-select filtering with automatic gain control (AGC) for a 5-GHz CMOS WLAN receiver. Basic concepts and specifications of the IEEE 802.11a standard are reviewed. Coded orthogonal frequency division multiple xing (OFDM), employed in this standard for high data rate capability in multipath envi ronments, degrades signal detection in the receiver due to the high peak-to-average pow er ratio (PAPR). Statistical simulation shows that RMS detection has the least error variance among se veral algorithms. Channel-select filters of the analog ba seband processor are implemented as 3rd and 4th order cascaded elliptic lowpass Gm-C filters The set of filters have been designed and fabricated in a 0.25 m CMOS process to meet all th e specifications under expected process variations. The AGC part of the analog baseband pro cessor has three variable gain amplifier (VGA) stages. One of them is placed before an d the rest after the cha nnel-select filter. A

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xii new gain-control algorithm for the OFDM ba seband signal is proposed based on analysis of conventional AGC loops. The new AGC algor ithm uses switched coarse gain-setting steps followed by an analog open-loop fine gain -setting step to set th e final gain of the VGAs. The AGC circuit is implemented in a 0.18 m CMOS process using newly designed circuits including linear VGAs, RMS detectors, and current-mode computation circuitry. Experimental results show that the new AGC circuit adjusts OFDM short training symbols to the desired leve l within settling-time requirements.

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1 CHAPTER 1 INTRODUCTION 1.1 Motivation Wireless technologies are progr essing rapidly, not only for voice, but also for data communications. The growing mobile com puting environment combined with the demand for network connectivity has made wi reless local area network (WLAN) popular. Since the Institute of Electrical & Elec tronics Engineers (IEEE) ratified two WLAN standards, 802.11a and 802.11b, in 1999, many WLAN system architectures have been developed to implement them. The IEEE 802.11b standard specifies op eration in the 2.4-GHz industrial-scientific-medical (ISM) ba nd using direct-seque nce spread-spectrum (DSSS) technology. On the other hand, the IE EE 802.11a standard specifies operation in the recently allocated 5-GHz unlicensed nati onal information infrastructure (UNII) band and uses the orthogonal frequency division multiplexing (OFDM) scheme instead of DSSS. The IEEE 802.11b standard, which suppor ts data rates of up to 11Mbps, was implemented before the IEEE 802.11a standar d, which supports data rates of up to 54Mbps, because the latter has more comp licated and strict transceiver design specifications than the former [Con01, Lee02]. In addition to the right performance requirement, implementation of the 5-GHz 802.11a RF transceiver with low cost and high power efficiency is another challenge. Along with several other sili con IC technologies, CMOS pr ocess technology can be a solution. It provides a low-cost advantage due to its compa tibility with high levels of integration. Many CMOS processes also offe r multiple metal layers, which enables the

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2 use of integrated inductors and linear capaci tors. However, characteristics of these passive devices can be poor, due to proce ss and temperature sens itivities. These drawbacks can be resolved by automatic fr equency and gain control (AFC and AGC) algorithms [Zar02]. A typical 5-GHz WLAN receiver with direct conversion consists of RF front end, analog and digital baseband blocks. In this ty pe of architecture, most gain is in the analog baseband except for the gain of a low noise amplifier (LNA) and mixer in the RF front end. An analog baseband processor covers from the mixer’s output to the analogto-digital (A/D) converter’s input, including baseband lowpass filters and AGC circuits. Therefore, the main function of an anal og baseband processor can be described as channel-select filtering with sufficient gain. OFDM signals have a large peak-to-average power ratio (PAPR), which requ ires wide dynamic range in the receiver [Och01]. In order to deal with the wide dynamic range of the OFDM signal in the analog baseband processor, we need to devise an efficient gain control algorithm. 1.2 Research Goals The first goal of this research is to design a baseband lowpass filter which meets the specifications of the I EEE 802.11a standard. The CMOS Gm -C elliptic filter can be a good candidate for its good on-chip integration properties. Also, by using a simple Gm tuning scheme, the filter can adjust the transfer function to compensate for process and temperature variations. The second goal is to propose a gain-control algorithm to provide a constant level of signal to the digital baseband processor. In order to achi eve this goal, the effect of PAPR characteristic of the OFDM data signa l on the signal amplitude estimation should be simulated statistically, by which one can determine the best detector type for the

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3 OFDM signal. Based on analysis of conventional AGC loops, a new gain-control technique can be obtained. Finally, the proposed AGC algorithm is to be implemented in the circuit level design. This research completes an an alog baseband processor for a CMOS WLAN receiver by making a whole signal chain with a filter and AGC circuits. To achieve experimental results, the AGC design is to be fabricated in TSMC 0.18 m CMOS technology. 1.3 Outline of the Dissertation This Ph.D. dissertation consists of six ch apters. An overview of the research is given in this current chapter (Chapter 1), including the motivation, research goals, and the scope of this work. Chapter 2 reviews some background knowledge on this research. Basic concepts and specifications of the IEEE 802.11a standard are described, and the overall system architecture and analog ba seband signal chain blocks are presented. Fundamentals of AGC operation are al so reviewed in that chapter. In Chapter 3, a statistical simulation of OFDM amplitude estimation is presented. An OFDM signal generator (transmitter) is si mulated, and signal detectors such as peak, average, RMS and pseudo-RMS detectors are compared based on 802.11a standard using Matlab/Simulink. The simulation results show that given random input OFDM-QAM signals, the RMS detector has the le ast error variance among detectors. Chapter 4 describes the design of 7th order elliptic lowpass filters for the baseband processor for a 5-GHz WLAN receiver. The fi lter employs a technique to avoid floating capacitors which allows setting peak values of all internal node voltages identical, thus improving the maximum input signal leve l. The circuit’s transconductors are

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4 implemented as sets of “unit gm” cells, by wh ich process-variation effects are reduced. The Gm cells provide reasonable linearity and tunability usin g degeneration. A spreadsheet to deal with the parasitic capacitance simplifies the design process. Simulation results in a 0.25 m CMOS process verify that the circuit meets all the specifications under expected process variations. Chapter 5 discusses the AGC part of the analog baseband processor. It has three stages of variable gain amplifiers (VGAs). One of them is placed in front of the lowpass filter to maximize the dynamic range of the si gnal. A new gain-control algorithm for the OFDM baseband signal is proposed based on an alysis of conventional AGC loops. After the switched coarse gain-setting, a fine gain-s etting scheme locks the final gain within the specification time. Circuit design for the proposed algorithm is implemented in a 0.18 m CMOS process. A summary of research work discussed in the dissertation and suggestions for the future work are presented in Chapter 6.

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5 CHAPTER 2 BACKGROUND 2.1 IEEE 802.11a Standard The 802.11a standard specifies operati on in the 5-GHz unlicensed national information infrastructure (UNII) band with available signal bandw idth of 300 MHz. The allocated frequency band is split in to two blocks (5.15 ~ 5.35 GHz and 5.725 ~ 5.825 GHz) with three different power-level work ing domains as illustrated in Figure 2-1. The bottom 100 MHz domain has a maximum po wer output restriction of 40 mW, while the next 100 MHz allows up to 200 mW. The top 100 MHz domain, intended for outdoor operation, allows power output up to 800 mW. Figure 2-1. Frequency band alloca tion in the IEEE 802.11a standard 5.15G 40mW 200mW 5.25G 800mW f (Hz)5.725G 5.825G 5.35G 20MHz 52 carriers per channel, each 312.5KHz wide

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6 The 802.11a standard employs an encodi ng technology called coded orthogonal frequency division multiplexing (OFDM). OF DM subdivides a high-speed data carrier into several lower-speed subcarriers, which ar e then transmitted in parallel. There are four 20 MHz-wide carriers in each 100 MHz domain. E ach 20 MHz-wide carrier is subdivided into 52 subchannels, each subcha nnel with 312.5 KHz bandwidth. 48 of these 52 subchannels are used for data, while the re maining 4 are used for error correction. By using this OFDM scheme with low data ra te subchannels, the signal channel is less susceptible to multipath effects during propaga tion. However, OFDM signals have large peak-to-average power ratio (PAPR) which requires a large power backoff in the transmitter and a wide dynamic range in the r eceiver. For example, suppose each of the 52 subcarriers of the OFDM signal is a single-to ne sine wave. Then the wave form of the composite OFDM signal in the time domain will have large peaks and valleys. In the worst case, if the peaks of all 52 sine waves co incide in time, the peak voltage will be 52 times larger than that of a single sine wave which results in a peak-to-average ratio of 17 dB ( 10log(52)). Although some signal clipping can be accepted with an insignificant performance degrade in practice, this PA PR characteristic of the OFDM signal can complicate transceiver design [Zar02]. The OFDM system uses binary / quadrat ure phase shift keying (BPSK/QPSK), 16-quadrature amplitude modulation (QAM) or 64-QAM for subcarrier modulation. When BPSK is used, each subchannel carrier en codes data of 125 Kbps, resulting in a 6 Mbps data rate. The data rate doubles to 12 Mbps, 250 Kbps per subchannel with QPSK. Using 16-QAM, the rate increases fu rther to 24 Mbps. It is mandatory for 802.11a systems to provide these data rates. Th e standard also allows data-rate extension

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7 beyond 24 Mbps. A data rate of up to 54 M bps in a 20 MHz channel can be achieved by using 64-QAM. The 802.11 wireless LAN data service is pr ovided by sending and receiving packet frames denoted as PLCP (physical layer convergence procedure) Protocol Data Unit frames. The packet frame format includes PLCP preamble, SIGNAL (header of the frame) and DATA parts as shown in Figure 2-2. The PLCP preamble is composed of 12 symbols: 10 repetitions of a “short tr aining sequence” (used for AGC convergence, diversity selection, timing acquisition, and co arse frequency acquisition in the receiver) and two repetitions of a “long training seque nce” (used for channel estimation and fine frequency acquisition in the receiver). The SIGNAL part constitutes a single BPSK coded OFDM symbol which includes the RATE and LENGTH fields required for decoding the DATA part of the packet. The DATA part, which includes the service data units, may consist of multiple OFDM symbols. The design considerations for an analog baseband processor deal with short traini ng symbols of the preamble in this OFDM packet frame format. Figure 2-2. PLCP Protocol Data Unit frame format 2.2 System Specifications for WLAN Receiver The receiver specifications for the 5 GHz WLAN system are described as receiver performance requirements in the 802.11a sta ndard. Table 2-1 speci fies the receiver PLCP Preamble 12 Symbols SIGNAL One OFDM Symbol DATA Variable Number of OFDM Symbols 10 short training symbols + 2 long training symbols RATE and LENGTH for DATA BPSK coded OFDMCoded OFDM

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8 performance requirements with data rates of 6 Mbps through 54 Mbps. The minimum sensitivity is -82 dBm for 6 Mbps data rate and -65 dBm for 54 Mbps data rate. For the baseband signal channel at DC, the adjacent channel (at 20 MHz) rejection should be no less than 16 dB (6 Mbps data ra te) or -1 dB (54 Mbps data rate). Similarly, alternate adjacent channel (at 40 MHz) re jection should be no less than 32 dB (6 Mbps data rate) or 15 dB (54 Mbps data rate). The relativ e constellation RMS error which is known as SIR (Signal-to-Interference Ratio) should not exceed -5 dB (6 Mbps data rate) or -25 dB (54 Mbps data rate). Figure 2-3 shows sp ecifications of the minimum sensitivity signal channel with adjacent and alte rnate adjacent channels for 6 and 54 Mbps data rates. Table 2-1. Receiver performance requirements Data rate (Mbps) Minimum sensitivity (dBm) Adjacent channel rejection (dB) Alternate adjacent channel rejection (dB) Relative constellation error (dB) 6 -82 16 32 -5 9 -81 15 31 -8 12 -79 13 29 -10 18 -77 11 27 -13 24 -74 8 24 -16 36 -70 4 20 -19 48 -66 0 16 -22 54 -65 -1 15 -25 From the specifications a bove, we can get the attenuation requirements for the analog baseband channel selection filter. With the minimum data rate, 6 Mbps, channel rejection should be 16/32 dB for adjacent/al ternate adjacent channels. Adding 6 dB for SIR and 5 dB for margin, total attenuation should be 27/43 dB fo r adjacent/alternate adjacent channels. Channel rejection with 54 Mbps data rate should be -1/15 dB for adjacent/alternate adjacent channels. This re sults in the total a ttenuation of 29/45 dB with 25 dB of SIR and 5 dB of margin. If we increase the margin to 10 dB, the filter

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9 attenuation requirements would be 34 dB fo r the adjacent channel and 50 dB for the alternate adjacent channel. Figure 2-3. Specifications of the minimum se nsitivity signal channel with adjacent and alternate adjacent channels for 6 and 54Mbps data rates 2.3 Receiver Architecture and Analog Baseband Signal Chain The two most common choices in receiver architecture are di rect conversion and low-IF dual conversion (superheterodyne). Di rect conversion is us ually preferred in a fully integrated design because it has a simple architecture. However, it has drawbacks such as 1/f noise sensitivity and DC-offset problems. Dual conversion can reduce the disadvantages of direct conversion, but it requires ex tra complexity [Raz01]. In this work, we assume that direct convers ion is used for the receiver architecture. As depicted in Figure 2-4, the receiver consists of a band-pass filter, low-noise amplifier (LNA), I/Q channel mixers and low-pass filt ers with automatic gain control (AGC) followed by analog-to-digital converters. The gi ven blocks have fixed gains; -3 dB for band-pass filter, 20/0 dB (selectable) for L NA and 10 dB for mixers. As we know the receiver specifications, we can get the gain budget distribution for the AGC with given RF block gains. 8.3 11.7 31.7 f (MHz) -82dBm -66dBm -50dBm (6 Mbps) +16dB +32dB 8.3 11.7 31.7 f (MHz) -65dBm -66dBm -50dBm (54 Mbps) +15dB -1dB

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10 Figure 2-4. Architecture for the 5 GHz WLAN receiver Input signal levels to the filter/AGC blocks can be computed by adding the gains of the BPF, LNA and mixer to the sensitivity. The minimum input signal level for 6 Mb/s data rate is: -82 dBm -3 dB + 20 dB + 10 dB = -55 dBm. For 54 Mb/s data rate, the minimum input signal level is: -65 dBm -3 dB + 20 dB + 10 dB = -38 dBm. The maximum input signal level of the adjacent a nd alternate adjacent channels at the AGC inputs are -39 dBm and -23 dBm, respectively. We assume that the input resistan ce of the A/D converter is 1 K and that its input signal level should be 1 Vpp in single ended mode. In differential mode, 1 Vpp equals to 0.5 Vpp (0.25 Vp) and to 0.178 Vrms for a sine wave. This corresponds to 0.032 mW in 1 k of input resistance, or -15 dBm. Fo r OFDM data signals, however, the ratio between the peak and the RMS voltage varies due to the randomness of data and the effects of the channel. For OFDM short tr aining symbols, which have fixed amplitudes specified in the 802.11a standar d, the RMS voltage of a short training symbol with 0.25 Vp is 0.105 Vrms. Its power level is computed as 0.1052 / 1K = 0.011 mW, or -20 dBm. In practice, the effects of a random channel can change this relationship. AGC1 AGC2 LNA BPF AGC1 AGC2 LPF LPF LO MixerI Mixer Q ANT A/D A/D I Q I Q

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11 Figure 2-5. Baseband signa l chain block diagram The proposed baseband signal chain is compos ed of three variab le gain amplifier (VGA) stages with two AGC blocks plus a 7th order Gm-C filter implemented as shown in Figure 2-5. It also includes DC-offset can celing blocks such as capacitive coupling, high-pass filter and/or feedback loop to rem ove dc offsets. One AGC block is placed before and one after the channel-selection filt er. Since the signals before and after the channel-select filter are diffe rent, we applied separate AGC blocks to provide optimum dynamic range (DR) for the filter. The prefilter AGC block with one selectable-gain VGA stage enables the desired channel to have the maximum gain in the presence of large adjacent channel signals by increasing th e gain until the composite (desired channel plus adjacent channels) signal reaches the inpu t saturation point of the filter. This prefilter AGC provides an approximately consta nt-level composite signal to the channelselection filter, thus reducing the input-signal dynamic-range requirement of the filter. The post-filter AGC with two VGA stages sets the gain so that th e signal level of the VGA 1 VGA 2,3 VGA 1 VGA 2,3 AGC 1 AGC 2 Gm tuning A/D A/D DSP RF I Q DC offset canceller Channel selection filter @ 8.3 MHz HPF @ 150 kHz DC offset canceller

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12 selected channel gets to the desired output leve l. If we had used a single post-filter AGC, a low-noise filter with high DR and a high ga in-range AGC would have been required in the worst case of low composite input signal. On the other hand, we would have needed an extra gain stage after the filter in the worst case of low desired signal level with high adjacent-channel signal level, if we had used a single pre-filter AGC. To ensure the operation of the baseband si gnal chain for all data rates with worstcase levels of adjacent channels, efficient gain distribution is needed for the two AGC blocks as illustrated in Figures 2-6 and 2-7. Given -16 dB as the input saturation point of the filter, the gain of the pre-filter AGC s hould be 7 dB or more. The gain of the postfilter AGC should be -4 dB (-16 to -20 dBm) for the maximum signal and 28 dB (-48 to -20 dBm) for the minimum signal, which specifi es the gain range of each VGA to -2 to 14 dB. The selectable gain of the pre-filter AGC can be set to 7 or 14 dB when all three VGA stages are identical. Adding 4 dB of gain margin, the VGA should be designed to have a gain range of -4 to 16 dB. 2.4 AGC Fundamentals In this section, a conventi onal closed-loop AGC is analyzed mathematically based on the AGC loop analysis given by [Kho98] to elucidate AGC function. For the operation of the AGC loop, we assume that the AGC circuit only operates on signal amplitude; hence the AGC input/output signals are represented only in terms of their amplitudes. Another assumption is that the p eak detector extracts the peak amplitude of Vout(t) linearly and instantly (much faster than the basic operation of the loop) so that peak voltage equals to the amplitude of Vout(t). This assumption enables omission of the peak detector function model in the analysis.

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13 Figure 2-6. Receiver gain distribution plots for 6 Mbps data rate. (a) Minimum signal 1. (b) Minimum signal 2. Figure 2-8 (a) shows a common structure of an AGC loop. The AGC loop consists of a VGA, a peak detector, a comparator, a nd a loop filter. The VGA amplifies the input signal Vin by the gain control signal Vc. The output of the VGA is extracted by the peak detector and then is compared with the reference voltage Vref. The error signal is filtered and fed back to the VGA to adjust the gain. The AGC loop is in general a nonlinear (a) LNA VGA Mixer VGA -3dB 0/20dB 10dB 3r d + 4 th AGC1 AGC2 (b) -4~28dB 7/14dB -50 -66 -82 -23 -39 -55 -16 -32 -48 -20 -42 -44 -66 -82 -74 -47 -55 -39 -33 -25 -41 -58 -52 -20

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14 Figure 2-7. Receiver gain distribution plots for 54 Mbps data rate. (a) Minimum signal. (b) Maximum signal. system because the VGA operates like a mixer: Vout = Vin f(Vc). (2-1) Thus, we need to linearize the loop to simp lify a mathematical analysis of the AGC loop. Figure 2-8 (b) shows a linearized structur e of the AGC loop. By taking the natural logarithm of Equation 2-1, we can change the multiplier expression of the VGA to an adder expression: ln(Vout) = ln{Vin f(Vc)} = ln(Vin) + ln(f(Vc)). (2-2) Mixer LNA VGA VGA -3dB 0/20dB 10dB -4~28dB 3r d + 4 th AGC1 7/14dB AGC2 (a) (b) -66 -50 -30 -59 -43 -23 -16 -36 -52 -20 -94 -96 -65 -50 -66 -38 -39 -31 -32 -23 -16 -59 -61 -20

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15 Figure 2-8. AGC structure with (a) nonlinea r feedback loop and (b) linearized loop representation To linearize the feedback l oop, two function blocks (the exponential block at the VGA output and the logarithm block at the c ontrol voltage input of the VGA) must be canceled. Hence, two shaded blocks (the logarithm block at the VGA output and the exponential block at the contro l voltage input of the VGA) ar e added in Figure 2-8 (b). We can write the control function to VGA as f(Vc) = exp(kVc), (2-3) and rewrite Equation 2-2 as ln(Vout) = ln(Vin) + ln(exp(kVc)) = ln(Vin) + kVc. (2-4) Let ln(Vin) = x and ln(Vout) = y, then the Equation 2-4 is y = x + kVc. (2-5) ln ex y VG A Vin k 1 sgm/C LF – + Vc Vout ln ez ln e ln Vref VG A Peak Detector – + VrefVoutVin Vc Loop Filter (a) (b)

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16 The control function from the l oop filter is expressed as t out ref m cd V V C g V0) ln(, and ln(Vout) = y, so t ref m cd y V C g V0) (. (2-6) Take derivative respect to time on Equations 2-5 and 2-6: ) ( ), ( y V C g k dt dx dt dy y V C g dt dV dt dV k dt dx dt dyref m ref m c c (2-7) And take the Laplace transfor mation to Equation (2-7): sy = sx k(gm/C)y, (s + kgm/C)y = sx. C g k s s s H x ym ) ( (2-8) Equation 2-8 is an input-output transfer function of the linearized VGA with AGC loop. The transfer function is a 1st order high-pass f unction and is stable since the pole is in the left half of the s-plane. This means that th e gain control voltage of the feedback loop is input signal independent. AGC settling time is inverse proportional to the constant loop bandwidth fc = k(gm/C). In many AGC systems, the logarithm amplif ier in shaded block in Figure 2-8 (b) can be omitted due to its complexity in real ization. With this omission, the above condition can still be met under certain smallsignal approximations. The assumption is that the AGC loop is operati ng with the condition that the output amplitude of VGA is near its fully converged state, that is, Vout Vref. In this case, the control voltage function can be written as t out ref m cd V V C g V0) (, and since Vout = exp(y), t y ref m cd e V C g V0) (. (2-9) Take the derivative respect to time on Equations 2-5 and 2-9:

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17 ) ( ), ( ,y ref m y ref m c ce V C g k dt dx dt dy e V C g dt dV dt dV k dt dx dt dy (2-10) Equation 2-10 is non-linear because of the exp(y) term. Let ln(Vref) = z; then Vref = exp(z). Under small-si gnal approximation of Vout Vref, we can get Vout Vref 0, and ln(Vout) ln(Vref) = y z 0. So, by Taylor series expansion, we can write ) 1 ( 1 ) 1 ( ,) (z y e e z y when z y e e e e e ez y z y z y z z y z z z y y (2-11) Combine Equations (2-10) and (2-11): y V V C g k dt dx dt dy z y V V C g k dt dx z y e V C g k dt dx dt dyref ref m ref ref m z ref m ) ln( ) 1 ( ) 1 ( (2-12) Take the Laplace transformation to Equation 2-12: sy = sx k(gm/C)Vrefy, (s + kgm/CVref)y = sx. ref mV C g k s s s H x y ) ( (2-13) Equation 2-13 is the input-output transf er function of the linearized VGA with AGC loop under small-signal approximation. The transfer function is a 1st order highpass function and is stable since the pole is in th e left half of the s-plane. However, since we assumed Vref Vout = Vinf(Vc), this system is fundament ally nonlinear and is input signal-dependent. Loop bandwidth fc = k(gm/C)Vref is not constant if the difference between Vout and Vref changes. Therefore, AGC sett ling time increases linearly with respect to the difference (input step size).

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18 CHAPTER 3 OFDM SIGNAL AMPLITUDE ESTIMATION 3.1 OFDM Signal Characteristics OFDM is a multi-carrier transmission technique, which divides the available spectrum into many carriers, each one being mo dulated by a low rate data stream. It is similar to Frequency Division Multiple Acce ss (FDMA) in that the multiple user access is achieved by subdividing the available bandwidth into mu ltiple channels, which are then allocated to users. However, OFDM uses the spectrum much more efficiently by spacing the channels much closer together. This is achieved by making all the carriers orthogonal to one another, preven ting interference between the closely spaced carriers. A key drawback of OFDM is its high peak-to-aver age power ratio (PAPR), that is, its signal in the time domain has noiselike amplitude with a very large dynamic-range [Och01]. Figure 3-1 shows a typical analog OFDM signal in the time domain. Figure 3-1. A typical analog OFDM signal in the time domain

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19 OFDM has gained considerable attenti on with the rapid gr owth of digital communication in recent years. It has been adopted for digital wireless broadcast and network standards, including IEEE802.11a wireless LAN standard. The 802.11a standard describes the specifi cations for 5 GHz wireless L AN transceivers using OFDM [IEE99]. As discussed in Chapter 2, it offers support for a combination of other modulation and coding alternatives such as phase shift keying (PSK) or quadrature amplitude modulation (QAM) with convolution encoding to generate data rates of 6 through 54 Mbps. A typical WLAN receiver consists of LNA, mixer, analog baseband processor and DSP blocks. An analog baseband processor includes AGC and channel-select filter blocks that deal with baseband signals in the time domain. The AGC sets the gain of variable gain amplifiers with respect to th e detected output signal strength, which keeps the output signal level to the digital block c onstant. AGC systems use peak detectors to detect the strength of the output signal assume that its peak amplitude is constant if the signal strength does not cha nge [Kho98]. However, peak detectors may not work properly with non-sinusoidal si gnals, that is, OFDM signal with high PAPR. Although RMS detectors have been widely used in nonsinusoidal signal amplitude estimation, no specific accuracy comparison among different type s of detectors has be en reported so far. In this chapter, an OFDM signal genera tor for the baseband frequency range is designed based on the 802.11a specifications to estimate amplitude of analog OFDM signal in time domain using Matlab/Simulink. OFDM data symbols are simulated using randomly generated 64-QAM sequences. Variou s detectors such as peak, average, and RMS detectors are tested by using the statis tical simulation method in order to find out

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20 which has less variance for the OFDM amplitude estimate. Signal detectors will show averages of detected symbol amplitudes and statistical variances from multiple simulations. 3.2 OFDM Signal Generation In an OFDM system, the data is split into a number of streams, which are independently modulated on parallel closelyspaced carrier freque ncies. An OFDM symbol is a sum of subcarriers that are indi vidually modulated by usi ng binary phase shift keying (BPSK), quadrature phase shift keyi ng (QPSK), 16-QAM, or 64-QAM. Figure 32 shows the basic OFDM signal ge nerator with the data symbols d(n) = a(n) + jb(n). The real and imaginary parts correspond to the in -phase and quadrature parts of the OFDM signal. They have to be multiplied by a co sine and sine of the desired frequency to produce the transmitted OFDM signal represented as [Cim85]: 1 0)} sin( ) ( ) cos( ) ( { ) (N n n nt n b t n a t D (3-1) Figure 3-2. OFDM modulator Serial to Parallel OFDM signal D(t) cos0t d(n)=a(n)+jb(n) sin0t cosN-1t sinN-1t MUX b(0) a(N-1) b(N-1) a(0)

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21 The IEEE 802.11a standard specifies th e physical layer convergence procedure (PLCP) which provides a framing format su itable for data exchange and information management. The PLCP preamble consists of 10 repetitions of a ‘short training symbol’ (10 x 0.8s), 2 guard intervals (2 x 0.8s), and 2 repetitions of a ‘long training symbol’ (2 x 3.2s). Seven out of ten short training symbols are used to allow time for signal detection, AGC convergence, and diversity se lection. A short tr aining symbol uses 12 subcarriers, which are modulated by the elements of the sequence S, given by: S-26,26 = (13/6) {0,0,1+j,0,0,0,-1-j,0,0,0,1+j,0,0,0,-1-j,0,0,0,-1-j,0,0,0,1+j,0,0,0,0, 0,0,0,-1-j,0,0,0,-1-j,0,0,0,1+j,0,0,0,1+j,0,0,0,1+j,0,0,0,1+j,0,0}. The multiplication factor of (13/6) normalizes the average power of the resulting OFDM symbol, which utilizes 12 out of 52 subcarriers. (a) (b) Figure 3-3. Short training symbols: (a) I cha nnel one symbol (0.8s) and 7 symbols, and (b) Q channel one symbol (0.8s) and 7 symbols A short training symbol can be generated by adding 6 signal sources for each I and Q channel using Simulink. The 12 subcarriers, 4(1.25MHz), 8(2.5MHz), 12(3.75MHz), 16 (5MHz), 20(6.25MHz), and 24(7.5MHz), are modulated by the

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22 BPSK sequence as given above. The generated short training symbol s (analog signal) for I and Q channels are illustrated in Figure 3-3. The 64-QAM OFDM data symbols are genera ted as follows: First, binary input data is encoded, interleaved, and converte d to QAM values. The 52 QAM values (48 data values and 4 pilot values) are then zer o padded and modulated onto 64 subcarriers by applying the Inverse Fast F ourier Transform (IFFT). Th e output is converted to a serial symbol in the next stage. The end pr ocessing of the digital baseband block adds cyclic extension and window functions. Fi gure 3-4 shows the block diagram for data symbol generation in th e discrete time domain. The OFDM data symbol signal in the con tinuous-time domain can be generated for I and Q channels by replacing the IFFT bloc k in Figure 3-4 with a new block that combines the QAM-modulated analog s ubcarriers as shown in Figure 3-5. Figure 3-4. Data symbol generati on in the discrete time domain 3.3 Analog OFDM Signal Amplitude Estima tion with Statistical Simulation The IEEE 802.11a standard reserves seve n short training symbols for signal detection, AGC convergence and diversity selec tion. Since seven id entical short training symbols are transmitted through an assumed unchanging channel, all of the available information about signal amplitude is availa ble during each symbol duration. Thus, the short training symbol duration (0.8 s) is the optimal amplitude-estimation time.

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23 However, due to its high PAPR, detecting th e OFDM signal within a time period as short as 0.8s can lead to high variance in the estimate. Moreover, th e received signal might have multi-path fading channel effects, which cause inaccurate amplitude estimation. Therefore, we can consider the variance of the estimated amplitude to compare the accuracy of estimation algorithms. We assume that the detector with lower variance is more accurate. In OFDM amplitude estimation, the accuracy of the estimate can be evaluated by statistical simulation; that is, th e smaller the standard deviation is, the better the accuracy of the detector is. Figure 3-5. Data symbol genera tion in continuous time domain In order to compare the variances of the al gorithms, we simulate the signal strength estimation using randomly generated data sy mbols. 64-QAM random data signals are generated and modulated with subcarriers to make OFDM data symbols. Three typical detectors such as peak (PK), average (AVR ) and RMS (RMS) detectors are considered for the accuracy analysis. Three pseudo-RMS (PRMS1.5, PRMS3 and PRMS4) detectors SC26

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24 are added to find out if they show variances si gnificantly different from that of the exact RMS detector. Six detectors are implemented as follows: 4 4 4 3 3 3 5 1 5 1 5 1 21 1 1 1 1 ) max( T T T T T Tdt S T PRMS dt S T PRMS dt S T PRMS dt S T RMS dt S T AVR S PK where S is the amplitude of the OFDM signal and T(=0.8s) is the estimation time Table 3-1. Statistical simulation re sult for 5000 symbols (Max Peak = 0.607) Detector PK AVR PRMS1.5RMS PRMS3 PRMS4 Arithmetic mean of 5000 results 0.318 0.118 0.129 0.140 0.160 0.176 Back-off (dB) 5.612 14.216 13.425 12.714 11.585 10.750 A total of 5000 random data symbols are simulated for statistical purposes. The arithmetic means of the 5000 simulated outputs for each detector are shown in Table 3-1. Back-off represents the ratio of the maximum pe ak value to the arithmetic mean value of each detector. The simulation results show that the back-off value for the peak detector is the smallest and that of the average detector is the largest, as expected. Back-off values for RMS and pseudo-RMS detectors decrease sl owly from the average detector to the high-order estimation. Data distribution plots and standard de viation for each detector are shown in Figures 3-6 and 3-7, respectively. The standard deviation of the peak detector is almost twice those of the others, which means th at it is not good for estimating OFDM signal strength. The RMS detector has the least stan dard deviation of all, but the differences between RMS detector and pseudo-RMS detector s are small. Standard deviations of pseudo-RMS detectors (PRMS1.5 and PRMS3) are only 4 to 6 % highe r than that of the

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25 true RMS detector (RMS). The simulation resu lts indicate that the RMS detector is the best one for OFDM amplitude estimation. However, a simple pseudo-RMS detector could also be used, because there is no bi g difference in standard deviation values between an RMS and pseudo-RMS detectors. Data Distribution Plots(5000 symbols for each detector)0 100 200 300 400 500 600 00.10.20.30.40.50.60.7valuesymbols peak average p.RMS(1.5) RMS(2) p.RMS(3) p.RMS(4) Figure 3-6. Data distribu tion plots for 6 detectors Standard Deviation0.06639 0.03407 0.02791 0.02682 0.02855 0.03164 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07peakaveragep.RMS(1.5)RMS(2)p.RMS(3)p.RMS(4) Figure 3-7. Standard deviat ion plot for 6 detectors

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26 3.4 Accuracy Boundary for Received OFDM Short Training Symbols In practice, OFDM symbol s are transmitted through a radio link that can be modeled as randomly scrambling the pha ses and possibly ch anging the relative amplitudes of the signal [Cho01]. When such a signal is received, the amplitude of the estimated signal can be different from the transmitted one even if all transceiver blocks are assumed ideal. By taking this multipath channel-effect into account, we can estimate the error variance of the r eceived OFDM signal. The RMS detector in the analog baseband processor is used for AGC, which mu st be performed with in the first 7 short training symbol period. The accuracy of AGC is bounded by the error variance in the RMS value of the received shor t training symbols. So we n eed to estimate the accuracy boundary for the short training symbols to consider gain margin of the AGC. Figure 3-8 shows how the OFDM short tr aining symbol gene ration and channel effect blocks were simulated in the discrete time domain. The shor t training symbols are generated by using the sequence given in Section 3.2 in the OFDM data symbol generation blocks. Multipath is implemen ted using Simulink library blocks. The Multipath Rayleigh Fading Channel block multiplies the input signal with samples of a Rayleigh distributed complex random process, while the additive wh ite Gaussian noise (AWGN) block adds noise. From 100 simulations for short training symbol with channel effects, the average of the estimated RMS amplitudes is 0.266, and its standard deviation is 0.1. These values translate to the accuracy boundary of 5.5dB. This margin should be considered when designing the AGC for an analog baseband processor in 802.11a WLAN receiver.

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27 Figure 3-8. OFDM short training symbol generati on with channel effect +26SCs Channel effect blocks

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28 CHAPTER 4 SEVENTH ORDER ELLIPTIC LOW-PASS GM-C FILTER 4.1 Introduction Channel-select filters for the analog ba seband processor in a WLAN receiver may be either off-chip passive filters or on-chip active filters. On-chip active filters are preferred for high integration and low cost, in spite of drawbacks such as limited receiver dynamic range, increased power consumption and chip area. Gm-C filters are well suited to high frequency applications as integrated continuous-time ac tive filters. In the Gm-C filter, parasitic capacitances of Gm cells can be merged into the grounded capacitors, thus minimizing their side effects [Kar92]. The channel-select filter must pass only th e desired channel to the analog-to-digital (A/D) converter, suppressing adj acent and all other channels. Specifications are given to realize the filter. Elliptic filters are used to meet the given specifications and implemented in a 0.25 m CMOS technology. This chapter describes the design of a CMOS fully differential 7th-order low-pass Gm-C filter for the baseband processor in 5 GHz WLAN receiver. The filter is implemented by cascading 3rd and 4th order elliptic filters. 4.1.1 Specifications Filter specifications were developed through discussions with the Intersil wireless group to be consistent with IEEE 802.11a st andard for a 5-GHz WLAN transceiver. The specifications of an active filter in a WLAN receiver usually include the following issues [Beh00].

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29 Frequency response: pass-band ripple, stopband attenuation, selectivity and group delay Input/output signal dynamic range, noise, linearity Power consumption or supply voltage with current drain Chip area and/or complexity The structure of the receiver uses I and Q channels for the baseband processing. The cutoff frequency of the low-pass filter can be set to half of the bandwidth. The occupied channel bandwidth is 16.6 MHz w ithin the allocated 20 MHz bandwidth and there is a 3.4 MHz spacing between channels Thus we can set the pass-band and stopband edge frequencies to 8.3 MHz and 11.7 MHz, respectively. Other specifications are minimum stop-band attenuation against adjacent channel and alternative adjacent channel, given as -34 dB @ 20 MHz and -49 dB @ 40 MHz, respectively. Figure 4-1 shows the channel magnitude attenuation requirements fo r the filter. Pass-band ripple should be less than 1dB. Settling time of the system, in cluding AGC settling, should be within 5.6 s (7 repetitions of the short training symbol ), which requires fast settling time of the filter. In addition, less group delay spread would ease the signal processing of the OFDM signals. Figure 4-1. Channel attenuation requiremen ts for the baseband low-pass filter f (Hz)

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30 4.1.2 Filter Topology In the light of the required stop-band a ttenuation and narrow transition-band, the specifications demand a relatively high-order filter. Elliptic filters have high selectivity (steep magnitude response), but require high-Q poles that tend to cause long settling times, large group delay spread, and high sens itivity to element e rrors. Chebyshev II (Inverse Chebyshev) filters ha ve less group delay variation, but need higher order (9th order) compared to elliptic type (6th order). Other filter types such as Bessel and Butterworth filters would require very hi gh filter orders to meet the selectivity requirements. Simulations indicated that a cascade of 3rd and 4th order elliptic lowpass sections provided superior trade-offs among delay, se ttling time and complexity. We can reduce the group delay variation of a high-order ellip tic filter by cascading lower-order ones. 3rdand 4th-order elliptic lowpass filters have 73 29 = 44 ns and 127 40 = 87 ns of maximum group delay variation in the passband, respectively [Men97]. Group delay variation of the cascaded f ilter is 44 + 87 = 131 ns, whereas that of the required 6th order elliptic filter is 403 79 = 324 ns. The cascad ed filter shows even better result in group delay than the 9th order Chebyshev II filter which has 142ns of the maximum group delay variation in the pass-band. Graphs of the magnitude and group delay responses for each filter type are shown in Figure 4-2. The Gm-C filters were designed based on LC passive filter prototypes, with element values provided by a filter data book [Hue80] and by software (Filter solutions v.8.0). Figure 4-3 illustrates prototype circuits of cascaded 3rd and 4th order low-pass elliptic LC passive filters which meet the gi ven specifications. Note that the input and output impedances are assumed to be 5 k

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31 (a) (b) (c) (d) Figure 4-2. Frequency response (ma gnitude and group delay) for (a) 6th order elliptic, (b) 9th order Chebyshev II, (c) 3rd order elliptic, and (d) 4th order elliptic filters (a) (b) Figure 4-3. LC prototype filters for (a) 3rd order and (b) 4th order elliptic low-pass filters 0 -20 -40 -60 -80 3r d order Elli p tic 80n 60n 40n 20n 0 Group delay (sec) 0 10M 20M 30M 40M Freq (Hz) 0 10M 20M 30M 40M Freq (Hz) 180n 150n 120n 90n 60n 30n 0 Group delay (sec) Magnitude (dB) Magnitude (dB) 0 -10 -20 -30 -40 -50 -60 4 th order Elli p tic 0 -20 -40 -60 -80 -100 -120 6 th order Elli p tic 540n 450n360n 270n 180n 90n 0 Group delay (sec) 0 10M 20M 30M 40M Freq 0 10M 20M 30M 40M Freq (Hz) 300n 250n 200n 150n 100n 50n 0 Group delay (sec) 9 th order Cheb y shev IIMagnitude (dB) Magnitude (dB) 0 -20 -40 -60 -80 -100 -120

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32 4.2 Filter Design I 4.2.1 Gm-C Filter with Amplitude Scaling The elliptic Gm-C filters are built from th e LC prototype by replacing both resistors and inductors with transconductors elements The input/output resistance of 5 k sets the transconductance gm to 200 A/V. The floating inductors are implemented using gyrator-C circuits with C = Lgm1gm2. In order to minimize mismatch, transconductors are composed of “unit gm (gmu)” cells. This also makes it convenien t for layout. All the transconductors in the filter are to be an in teger multiple of gmu. Transconductor of 200 A/V is represented by 4gmu with unit gm of 50 A/V. The transconductors connected to the input will be doubled to remove the 6 dB loss from implementation of equally terminated LC prototype. Figure 4-4 shows the implemented 3rd order Gm-C filter. Figure 4-4. 3rd order Gm-C filter However, in this filter, the amplitude of the signal at internal nodes may be higher than the filter input. These peak voltage s can drive internal transconductors into saturation, resulting in distortion of the output signal. This problem can be solved by applying amplitude scaling to the filter. That is, all node impedances are scaled so as to make their peak amplitudes remain near th e input signal’s level without changing the C1 = 4.45pF Vi C3 = 1.55pF V1 V2 V4 4gmu C2 = 4.45pF CL = 2.96pF 4gmu4gmu 4gmu 4gmu4gmu 8gmu

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33 transfer function of the filter. The 3rd order Gm-C filter has 3 nodes (two internal nodes and one output node). The second node n2 peak s at ~2.25 V in SPICE simulation, which is over twice the input voltage (1 V). This peak voltage can be reduced by half without changing the voltage at any other node of the filter. We can achieve this by halving the currents flowing into the capacitor’s node (4gmu 2gmu) and doubling the currents emitting from the capacitor’s node (4gmu 8gmu), simultaneously. The scaled internal node voltage plot and resulting Gm-C filter are given in Figures 4-5 and 4-6, respectively. (a) (b) Figure 4-5. Internal node voltage plot of the 3rd order Gm-C filter: (a ) before scaling and (b) after scaling Figure 4-6. 3rd order Gm-C filter after voltage scaling for internal nodes C1 = 4.45pF Vi C3 = 1.55pF V1 V2 V4 2gmu C2 = 4.45pF CL = 2.96pF 8gmu2gmu 8gmu 4gmu4gmu 8gmu

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34 4.2.2 Gm Cell Circuit Design The basic building block of the Gm-C filter is the integrator, which consists of a transconductor (Gm cell) and a capacitor. Th e characteristics of the filter such as frequency response, linearity, DC gain and tu ning range depend on the Gm circuit. Real Gm circuits have a finite output impedance that modifies the tran sfer function of the integrator, introducing a low fr equency pole p1. This low fr equency pole p1 limits the dc gain and varies the phase of the integrator, which may introduce distor tions in the transfer function of the Gm-C filters [San00]. One general approach to deal with the low frequency pole is to use a folded cascode (FC) output stage. The folded cascode structure increases the output impedance of the Gm circuit, which shifts the low frequency pole to a much lower frequency, reducing effects on the filter’s transfer function. Since the filter will operate in fully differential mode, we need to add common-mode feedback (CMFB) to the folded cascade output stage to stab ilize the common-mode output voltage. This circuit senses any change of the common mode output voltage and pushes it back to the reference point by controlling the bias cu rrent of the output stage through negative feedback. So the transconductor has two elem ents: a Gm unit and a FC with CMFB unit. The schematics of the Gm and FC with CM FB circuits are shown in Figure 4-7. The Gm cell has a p-channel differential pair as input stage. This can move the parasitic pole p2 to a higher frequency with smaller tr ansistor dimensions in the output stage compared to the n-channel input stage case. That is because the parasitic pole p2 is mostly determined by the parasitic capacitance of an n-channel transistor in the FC stage.

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35 (a) (b) Figure 4-7. Schematics of (a) unit Gm cell and (b) FC with CMFB unit The Gm cell uses source degeneration MO S resistors to improve linearity. One more voltage-controlled de generation transistor (M5) is added for tuning in parallel with the degeneration pair (M3,4) of the well-known four-transistor input stage. In the degeneration scheme, the linearity is increa sed by reducing the transconductance of the differential pair (gm1/2). The transconductance of th e linearized Gm cell can be found M1M2 M3 M4 M5 M6M7 M8M9 Vt Vp1Vp1 Vn1Vn1 VinpVinn I outI out+ I outI out+ I inI in+ Vp1 Vp1 Vp2 Vp2 Vn2 Vn2 Vp1Vp1 Vc Vc Vc Vcm CMFB

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36 with small signal analysis. Vx Vy for small input signals, which makes the degeneration transistors M3,4 and M5 operate in the triode region. The degeneration resistance is defined as R = R1 || R2 || R3, by which we get the following equation for AC current i. i R V Vy x (4-1) We can also write i V V gx inp m ) (1 (4-2) and i V V gy inn m ) (2 (4-3) for the input transistors M1 and M2, respectively, where gm1 = gm2 and Vinp Vinn = Vin From Equations 4-1 through 4-3 we get: i i R V gin m 2 ) (1 (4-4) in m mV R g g i 21 1 (4-5) mR m m m m m mg g R g R g R g g G || 2 1 2 1 2 21 1 1 1 1 (4-6) Equation 4-6 shows that the transconductance of the proposed Gm cell is the parallel sum of the transconductances of the differential i nput stage and the degene ration transistors. The unit Gm cell is designed and simulated to have 50 A/V of transconductance through 1 Vpp input signal range with 3 V supply voltage Figure 4-8 illustrates the linear range of the DC transfer characteristics and transconductance.

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37 (a) (b) Figure 4-8. DC transfer characteristics of a unit Gm cell: (a) V-I plot, (b) Gm plot 4.2.3 Dealing with Parasitic Capacitance The 3rd order filter in Figure 4-5 is redraw n in Figure 4-9 to show the fully differential structure with Gm cells, FC units and capacitors. In reality, active blocks such as these Gm cells and FC units have parasitic capacitances at their input/output ports. Hence, we need to compute all of the pa rasitic capacitances of the active blocks connected to each main capacitor nodes, and m odify the main capacitor value so that the total capacitance is the desired value. Also, to minimize process and temperature variations all nodes should have the same ratio of pa rasitic capacitance to main capacitance. An independent block compos ed of a FC output stage combined with CMFB is placed on capacitor node and used in common for all connected Gm cells. This is much simpler than including these functions in every Gm cell. The CMFB circuit in Figure 4-7 uses two matched differential pa irs for good linearity, and all nodes see low impedances to minimize high-frequency phase errors. The inputs remain linear for large 60 A 50 A 40 A 30 A 20 A Vin vs. Gm 0V 1V 2V 3V 40 A 20 A 0 A -20 A -40 A Vin vs. Iou t 0V 1V 2V 3V

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38 differential signals up to near 1 Vpp, which is consistent with the maximum input signal swing of the transconductors. In Figure 4-9, we can compute the number of FC units and Gm cells connected to each node. We keep track of the parasitic capacitances at each node for the output of each FC unit and the input of each Gm cell. The parasitic capacitan ces of each FC output port (Cout_FC) and Gm input port (Cin_Gm) are estimated from simulations [Kar92]. The parasitic capacitance at each node is calculated by the equation Cp = (number of FC) Cout_FC + (number of Gm) Cin_Gm. Let Ct be the total capacitan ce of each node. For each node, we set the ratio between ‘main’ and ‘paras itic’ capacitances as equal as possible to minimize the effects of process-parameter vari ations. Let x be the largest value of Cp/Ct for all nodes (x = 0.14 at node 5 of 4th order filter). The main capacitance to be placed at each node is C = Ct (1-x). The difference of the capacitance (Cd = Ct Cp C) should be realized by parasitic capacitance to provide pr ocess-parameter tracking. Therefore, we need to add dummy cells to all nodes with Cd except one. Finally, we can find the number of dummy cells (dummy#) and the main capacitor value (Ccap) for each node. A spreadsheet was developed to automate thes e calculations, as an example is shown in Table 4-1. Figure 4-9. Fully differential 3rd order Gm-C filter 8Gm + 2Gm + 3FC 8Gm + 1FC 4FC 4Gm + 4Gm + 8Gm + 2Gm + + + Vin Vout C1CLC2 C3

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39 Table 4-1. Spreadsheet to compute parasitic capacitance, number of dummy cells, and main capacitor value at each node filter order node FC# Gm# Cp Ct C Cd dummydummy# dum_diff Ccap 3 FC1 4 6 5.69E-13 4.45E-123.82E-126.24E -141.16E+001.00E+00 1.62E-01 3.83E-12 3 FC2 1 16 3.33E-13 2.96E-122.54E-128.61E -141.60E+002.00E+00 -3.96E-01 2.51E-12 3 FC3 3 6 4.47E-13 4.45E-123.82E-121.85E -133.45E+003.00E+00 4.45E-01 3.85E-12 4 FC1 4 12 6.48E-13 4 FC2 2 8 3.50E-13 4.55E-123.90E-122.94E -135.48E+005.00E+00 4.81E-01 3.93E-12 4 FC3 3 6 4.47E-13 4.84E-124.15E-122.40E -134.47E+004.00E+00 4.70E-01 4.18E-12 4 FC4 1 16 3.33E-13 3.44E-122.96E-121.55E -132.90E+003.00E+00 -1.04E-01 2.95E-12 4 FC5 3 6 4.47E-13 3.15E-122.70E-120.00E +000.00E+000.00E+00 0.00E+00 2.70E-12 FC#*Cout_FC + Gm#*Cin_Gm From Filter spec. Ct*(1-x)Ct-C-CpCd/Cin_dumint. of dummy remainder of Cd C + dum_diff*Cd Cout_FC 1.226E-13 Cin_Gm 1.3155E14 Cin_dum 5.3696E14 x 1.42E-01 4.3 Filter Design II 4.3.1 Avoiding Floating Capacitor The filter design in the previous section has embedded floating capacitors, which restricts node-voltage sca ling and thus limits the input dynamic range. Floating capacitors may also present a problem in the design due to their inaccuracy of the bottom-plate capacitance. Hence, in this se ction, we designed a nother version of the filter which avoids floating capacitors. This new filter design replaces floating capacitors with compatible circuit blocks and results in all scalable internal nodes. The improved dynamic range is obtained at the e xpense of some added complexity. Figure 4-10 describes the floating capacitor avoidance technique. The 3rd order Gm-C filter in Figure 4-4 is repeated here as 4-10 (a), where the floating capacitor is connected between node V1 and node V2. As shown in Figure 4-10 (b), the floating capacitor to the node V1 can be replaced w ith a grounded capacitor C3 and a current source of sC3V2 which flows into the node, because its current is sC3( V1 V2). The

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40 current source of sC3V2 can be implemented in the follo wing sequence; (i) duplicate all current sources at V2 (ii) drive thes e currents into R, (iii) ge t the desired current through scaled gm. This is illustra ted in Figure 4-10 (c). The voltage of the duplicated node Vx2 is s ( C2+ C3) V2/ gy2. Therefore, if we set the scaled gm as gx1 = gy2C3/( C2 + C3), then we get the desired current i = gx1 Vx2 = sC3V2. By applying the above technique to both nodes V1 and V2, the 3rd order Gm-C filter which avoids the floating capacitor is implemented, as shown in Figure 4-11. (a) (b) (c) Figure 4-10. Avoiding floating capacitor: (a) Gm-C filter with floating capacitor, (b) substitution of floating capacitor at node V1, (c) additional circuit for current source to node V1 4.3.2 Parasitic Capacitance Compensation All five internal nodes of the filter a voiding floating capacitors are scaled to maximize the input dynamic range of the filter The internal node voltage plot after scaling is shown in Figure 4-12, where peak vo ltages of all five in ternal nodes are equal to 1 V, which is the peak voltage of the input signal. gy2 VX2 V2V4s(C2+C3)V2g5’g7’ s C3 V1gX2’ gX1i C C V s(C3( V4Vi g1 g2 g4s C3 V1 C1 Vi C3 V1 V2 V4 C2 CL g4 g6 g2 g7 g1 s(C3((V1 g3 g5

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41 Figure 4-11. 3rd order Gm-C filter avoiding floating capacitor Figure 4-12. Internal node voltage plot of the 3rd order Gm-C filter avoiding floating capacitor Although the new filter presents scalabil ity for better dynamic range, the extra circuits introduce two new nodes that are not connected to grounded capacitors. These floating nodes, Vx1 and Vx2, depicted in Figure 4-13 (a) can add extra poles or zeros to the transfer function due to th eir parasitic capacitances. In order to solve this problem, C1Vi CL C2 V1V2g1 g2 g3g5g4g6g7 V X 1V X 2g1’ g2’ g5’ g4’ g7’ gy1 gy2 gX1’gX2’ gX2gX1 VL Internal Node Voltages 1.2V 0.8V 0.4V 0V V 2 V x1 V x2 V 1 V L 0Hz 5MHz 10MHz 15MHz

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42 we can add a ‘negative capacitor’ to the fl oating nodes of the filter. The negative capacitor circuit shown in Figure 4-13 (b) uses a cross-coupled diffe rential structure to compensate AC current due to th e parasitic capacitance by setting Cc = Cp. This circuit is applied to each floating node, by which the si de effects from the pa rasitic capacitance are cancelled out [Wak90]. (a) (b) Figure 4-13. Internal node voltage plot of the 3rd order Gm-C filter avoiding floating capacitor 4.4 Simulation Results 4.4.1 AC Response and Tuning Range The 3rd-4th order cascaded lowpass filter has been designed in two versions: namely, Filter 1 and Filter 2. Filter 1 includes floating capacitors whereas Filter 2 avoids the floating capacitors. The Cadence Spectre simula tion results show that the characteristics of both filters meet the specifications. The following data in the format of value1/value2/value3, which represents the sp ecifications, simulation results for Filter 1, and that of Filter 2, respectively. Pass-b and ripple is less than 1/0.75/0.86 dB. Pass-band and stop-band corner frequency attenuations ar e -1/-0.96/-0.78 dB and -28/-32/-40 dB, Vdd Gnd Cc Vp Vp Vn Vn Node_b Node_a Floating capacitor C1+C3 C2+C3Vi V1 V2VX1 VX2 Cpara Cpara-g2 -g7-gy2-gy1 g4g5g1 gX2’ gX2gX1’ gX1

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43 respectively. Stop-band attenuations for adj acent (at 20 MHz) and alternate adjacent (at 40 MHz) channels are -34/-47/-44 dB and -49/-58/-54 dB, respectively. Worst case simulations with temperature, process and mismatch variations showed that the pass-band cutoff frequency varied from 7.7 MHz to 8.7 MHz for both filters while maintaining the shape of the AC re sponse curve. Simulation results for AC response with tuning voltage of 0.1 ~ 1.9 V showed the pass-band cutoff frequency tuning range of 7.2 ~ 11.7 MHz for both filters This tuning range covers the worst case variation range. Therefore, these filters can tolerate temp erature, process and mismatch variations by using a simple automatic tuni ng circuitry. Figures 4-14 and 4-15 show the AC simulation results for Filter 2. Figure 4-14. AC response simulation result for Filter 2 4.4.2 Transient Response, Noise and Linearity Figure 4-16 (a) gives the result of the tr ansient simulation for pass-band signal at the edge frequency of 8.3 MHz. The output signal follows the input signal after initial settling period (~0.6 s). The plot shows the linear out put signal with approximately 90

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44 phase shift. Figure 4-16 (b) describes the a ttenuation for the stop-band signal at 12MHz, which suppresses out-of-ba nd signal after settling. Figure 4-15. AC response simulation result for Filter 2 with tuning (a) (b) Figure 4-16. Transient response of the F ilter 2 at (a) 8.3 MHz and (b) 12 MHz Noise performance of RF receivers is commonly characterized using the Noise Figure. Noise Figure is co mmonly defined as [Raz94], out inSNR SNR NF10log (4-7) Input Output Input Output

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45 where SNRin and SNRout are the signal-to-noise ratios meas ured at the input and the output, respectively. For a general calc ulation of the noise figure, th e NF is usually specified for a 1-Hz bandwidth at a given frequency. Th is is called as the “spot” noise figure to emphasize the very small bandwidth. This can be expressed as follows where A = Av and V2 n,out represents the total noise at the output. S out n S S n nkTR A V kTR R I V NF 4 1 log 4 ) ( 1 log2 2 10 2 10 (4-8) In this design, we set A=1 and RS=5k from which we get the noise figure from the simulation as NF = V2 n,out /(20.35n)2, as shown in Figure 4-17. The NF for the pass-band of the filter (156.25kHz ~ 8.3M Hz) is less than 16.8dB. Figure 4-17. Noise in dB vs. frequency plot The linearity of a filter can be specified by either single-tone total harmonic distortion (THD) or two-tone input IP3. In th is base-band filter design, the linearity of a filter is characterized by the signal voltage for 1 % THD. This figure of merit is used to quantify the non-linearity of the f ilter. Filter 1 shows 1 % T HD for an input signal of

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46 427 mVp while that of Filter 2 is 451 mVp in the nominal case (Figure 4-18). We can see that Filter 2 tolera tes higher input signals than Filter 1, under the same linearity condition. This is the result of a superior amplitude sc aling of Filter 2. The best/worst tuned case for the temperature, process and mismatch variation gives the maximum input signal range of 410 ~ 441 mVp and 424 ~ 503 mVp for Filter 1 and Filter 2, respectively. (a) (b) Figure 4-18. Linearity of 1 % THD vs. input sign al voltage for (a) Filter 1 and (b) Filter 2 in nominal case The comparison between Filter 1 and Filter 2 is summarized in Table 4-2. Filter 1 is superior in power consumption and comple xity, while Filter 2 shows better linearity. In conclusion, both 3rd-4th order cascaded elliptic lowpass Gm-C filters satisfy the specifications for the analog base-band filter in a 5 GHz WLAN receiver.

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47 Table 4-2. Summary of characteristics of the two filters Filter 1 Filter 2 Filter structure 3 rd +4 th elliptic with floating capacitor 3 rd +4 th elliptic avoiding floating capacitor Gm cells Unit Gm cells (50 A/V) Unit Gm cells + 10 extras number of MOS TRs 1364 2577 number of Caps 44 36 Itotal 21 mA 38 mA Max input V pp (worst/nominal/best) 820/854/882 mV 848/902/1006 mV In-band rms Noise 739.17 V/ Hz 870.22 V/ Hz DR (nominal input) 61 dB 60 dB

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48 CHAPTER 5 AUTOMATIC GAIN CONTROL 5.1 Introduction Automatic gain control (AGC) is an esse ntial function in a WLAN receiver because the power received through th e wireless channel is unpredictable. The AGC circuitry provides a known output voltage magnitude from an input signal with variable strength. In the IEEE 802.11a WLAN system, data pass through the channel in packet frames consisting of preamble, header and data segmen ts as discussed in Chapter 2. The receiver estimates corrections for the channel’s char acteristics during reception of the preamble. These characteristics are assumed to stay constant throughout the transmission of the whole packet frame, typically up to 1 ms. The preamble consists of 10 repetitions of a predefined data stream called a short training symbol (10 0.8 s) and two repetitions of a long training symbol (2 4 s). In the proposed receiver system, the time for seven of the repeated short training symbols (5.6 s) is allocated for signal detection, AGC convergence and diversity selection [IEE99]. While multipath can sign ificantly alter the waveform, we assume that the received signa l is essentially repeated during each short training symbol duration, and that its characteristics establish the amplitude and phase references for use during the entire packet frame. Conventional closed-loop anal og AGCs use feedback loops to adjust the gain of the variable-gain amplifiers (VGA) to set the de sired output signal stre ngth. In such AGC loops, as shown in Figure 5-1, input and output signals are typically represented by their peak amplitudes. This adequately represents signal levels for signals with constant PAPR

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49 such as sinusoids. For proper operation of closed-loop AGCs, the time required to determine peak amplitude must be much less than the time constant (settling time) of the loop filter [Kho98]. When the i nput amplitude changes, the detected output amplitude is compared to the desired amplitude and the diffe rence error is fed back to adjust the gain of the VGA to provide constant output amplitude. The negative feedback loop continuously responds to input amplitude variation. Figure 5-1. Conventional AGC loop composed of VGA, Peak Detector and Loop Filter However, in the 802.11a application, due to the high PAPR of the OFDM signal, input or output peak amplitude is not a relia ble measure of signal strength. The closedloop AGC with peak detector will not conve rge as the peak amplitude of the OFDM signal changes continuously. As discussed previously, the specif ications require AGC settling within the time for seven short trai ning symbols. Since seven identical short training symbols are transmitted through an assumed unchanged channel, all of the available information about signal amplitude is available during each symbol duration. So the short training symbol duration (0.8 s) is the optimal signal-averaging time. In the AGC loop, an average or RMS detector can replace the peak detector because signal strength can be estimated as an average or RMS over the symbol duration. The closedloop AGC with average or RMS detector will co nverge with the time constant of the loop VGA Peak Detector VrefVoutVin Vc Loop Filter

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50 filter much longer than the signal estimation time. The resulting AGC settling time is much longer than system specifications allo w. These issues preclude the use of a conventional closed-loop AGC in this applic ation. Based on these observations, a new open-loop AGC circuitry is propos ed in the following section. 5.2 AGC Algorithm Figure 5-2 illustrates the operation of th e proposed AGC circuitry. The analog baseband circuits include thr ee VGA stages plus a channel-selection filter. VGA stage VGA1, with gain selectable as 7 or 14 dB, precedes the filter. Two VGA stages, with combined gain variable continuously from a bout -8 dB to about 32 dB, follow the filter. Figure 5-2. Architecture of the proposed AGC algorithm; (a) block diagram and (b) time line Filter settling t1 t2 t3 t4 t5 t6 t7 Short Training Symbols t Set GLNA =20dB G1 = 7dB G2 = 6dB G3 = 6dB RD1,2 0.8 s 1.6 s2.4 s3.2 s4.0 s 4.8 s5.6 s RD3,4RD5 Coarse Gain Set 1 Coarse Gain Set 2 Fine Gain Set (b) VoutVin 3r d + 4 th order elliptic LPF RD1 Switched Gain Control 1 Gain = 7/14dB LNA Gain=0/20dB Iref VGA1 RD2 HPF Switched Gain Control 2 Gain = -3/7/17/27dB AGC with One-Step Correction Gain = -4~28dB HPF VGA2 VGA3 RD3 RD4 RMS Detector 5(a)

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51 Separate AGC loops are provided for the preand post-filter gain blocks, since they operate on different signals as discussed in Chapter 2. The AGC algorithm operates in three phase s: two switched coarse gain-setting phases, followed by an open-loop fine gain-set ting phase. The coarse gain-setting steps ensure that all of the gain and filter stages ope rate linearly and that the gain is within 5 dB of its optimal value. The fine step sets the gain for the entire packet to within 1 dB of its optimal value. Before the recep tion of each packet, gain s are initialized to 20 dB for the LNA, 7 dB for VGA1 and 6 dB for VGA2 and VGA3. During the first short training symbol time (t1: 0 ~ 0.8 s), RMS detectors RD1 and RD2, located before and after VGA1, estimate the signal amplitude. These values are sampled and held, and used by ‘Switched Gain Control 1’, a logic bl ock that selects the gains of the LNA and VGA1 as shown in Figure 5-3. The LNA gain is set to 0 dB if the output of RD1 is greater than -23 dBm. If the output of RD2 is less than -23 dBm, the gain of VGA 1 is set to 14 dB. Otherwise, they keep their initial gains. After the signals settle down through the filter (the second short training symb ol duration is allocated for filter settling), the post-filter AGC loop, ‘Switched Gain Cont rol 2’ (Figure 5-4), se lects the overall gain of the second and third VGAs (-3, 7, 17 or 27 dB) based on the signal amplitude detected during the third short training symbol (t3: 1.6 to 2.4 s) using RMS detectors RD3 and RD4 located before and after the cascade of VGAs. The overall gain of VGA 2 and 3 is set to -3 dB if the output of RD3 is greater than -30 dBm or to 7 / 17 dB if the output of RD4 is greater than -20 / -30 dBm. If the out put of RD4 is less than -30 dBm, the overall gain of VGA 2 and 3 is set to 27 dB.

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52 Figure 5-3. Switched Gain Cont rol 1 of the AGC algorithm Figure 5-4. Switched Gain Cont rol 2 of the AGC algorithm The final open-loop fine gain -setting phase, ‘AGC with One-Step Correction’, is applied to VGA2 and VGA3. The circuits include three main components: an RMS detector, an analog computation block and an inverse-gain block. As discussed in Chapter 3, an RMS detector should be used for the most accurate amplitude estimation of the OFDM signal. In this phase, the RMS det ector connected to the output of the third VGA (RD5) detects signal strength during the fift h short training symbol duration 20dB latched comparator RD1 RD2 -23dBm 0dB to LNA 14dB 7dB latched comparator -23dBm Vc to VGA1 Vc -3dB 7dB to VGA2 & 3 12dB 17dB 27dB RD3 RD4 -30dBm -20dBm -30dBm t=0s t=1.6 s latched comparator latched comparator latched comparator Vc

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53 (t5: 3.2 ~ 4.0 s). The output voltage of the RMS dete ctor is sampled and held, and the result, Vo1, is used in computing the final gain -control signal for VGA2 and VGA3. The analog computation circuitry comp utes the new control voltage (VC2) from Vo1, the desired reference voltage (Vref) and the initial control voltage (VC1). The new control voltage is applied to VGA2 and VGA3 th rough the inverse-gain block [Kho98], which adjusts VGA gain to get the desired level of the output signal. Note that the subscripts 1 and 2 represent previous and new time steps respectively. Figure 5-5. AGC with One-step Corr ection: the fine gain-setting step Designing a VGA with reasonable input-tooutput linearity is not too hard. However, accurately predicting the gain for a given gain-control input signal is quite difficult, especially in shor t-channel CMOS technologies. The inverse-gain block uses feedback to set the predicted switched gain accurately. Op-amp A in Figure 5-5 takes two positive DC voltage inputs, VC and VC and uses feedback to find the AGC gain-control voltage Vcp required to set the gain of VGA4 to Av = VC / Vdc. When Switch T is Vo Vref VC2Vin VC1 sqrt RMS detector + VCVcpVC Vdc x Vref / Vo Inverse Gain Block Computation Block VGA3 VGA2 VGA4 A VC1Sample & holdS/W T

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54 connected to VC1 (the switched-gain value set during co arse gain step 2), the gain of VGA4, as well as VGA2 and VGA3, are set to Av1 = VC1 / Vdc. (5-1) That is, the switched gain of the second coarse gain-setting phase (-3, 7, 17 or 27 dB for 2-stage VGAs) is set by the ratio of the selected voltage VC1 and the fixed voltage Vdc. Note that VGA4 in the inverse-gain bloc k must be matched to VGA2 and VGA3 in the main signal path. With the input voltage Vin applied during the fifth short training symbol time, the detected RMS output voltage is sampled and held: Vo1 = Av1 2Vin (5-2) The computation block computes the final control voltage: VC2 = VC1Vref / Vo1) (5-3) Then, VC2 is applied through Switch T to the inverse gain block, where the feedback loop of the op-amp A forces the gain of the VGA to Av2 = VC2 / Vdc. (5-4) From Equations 5-3 and 5-4: Av2 = VC2 / Vdc = VC1 / Vdc Vref / Vo1), and from Equation 5-1: Av2 = Av1 Vref / Vo1) (5-5) We can write the final output voltage as follows: Vo2 = Av2 2Vin = { Av1 Vref / Vo1)}2Vin = Av1 2Vin / Vo1Vref = Vref This equation shows that the final open -loop fine gain-setting AGC makes the output voltage Vo2 equal to the desired voltage Vref with one-step gain correction. Note that the final gain is held constant throughout the transmission of the packet frame. We also note that both I and Q channels can use one AGC loop for identical gain control, so the RMS detector can estimate the output amplitude from both I and Q channel signals. In summary, the proposed AGC algorithm us es a three-step iterative open-loop gain control method (two coarse gain-settings usi ng switches, followed by a final fine gain-

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55 setting using an open-loop computation circ uit). The algorithm c onverges within seven short-training-symbol times, and holds the fina l gain throughout the w hole packet frame. This avoids the settling-time lim its of a conventional closed-loop AGC. 5.3 Circuit Design 5.3.1 Variable Gain Amplifier The transconductance of a MOS differential pair may be varied either with bias current, or by an adjustable degeneration resistor. A Gilbert multiplier-type amplifier is well suited to implement a VGA with large gain and low noise, but its linearity is limited. A differential pair degenerated by a MOSFET resistor can handle large signals given a low power supply resulting in good linearity, because the degeneration does not degrade the voltage headroom in a simple differential pair. However, this degenerated differential pair has limited gain range and poor noise figure [Tad98]. High linearity in a transconductance cell requires the transconducta nce (Gm) to be independent of input signal. To cover the required gain range of -4 to 16 dB mentioned in Chapter 2, the VGA gain must be variable over a wide range Also, it should have good linearity and low noise. To ensure that the VGA can fulfill thes e requirements, it is designed as a linear transconductance cell combined w ith cross-coupled differential pairs as in a Gilbert cell for gain control. A source follower with shunt feedback, the so-called flipped voltage follower (FVF), provides a low-impedance out put node with a constant current through the input transistor [Car05]. A highly lin ear transconductance cell can be achieved by placing a fixed resistor RX between the low-impedance node s of the differential FVF to provide a constant tr ansconductance Gm = 2/RX. Feeding the output current of the transconductor to a fixed-resistor load RL would give a constant gain 2RL/RX. The

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56 differential pairs of Gilbert ce ll are used to steer the tune d portion of the transconductor’s output current to the load to make the gain adjustable. This type of VGA structure can provide -4 to 16 dB gain with good linearity. Figure 5-6. Schematic of the proposed VGA The proposed VGA consists of a linear transconductance cell (differential FVF with linear resistor), Gilbert cell-type differe ntial pairs and load resistors, as shown in Figure 5-6. In the differential FVF transconduc tance cell, due to the feedback loop, input signal applied to transistors M1a, b does not affect the transconductance Gm = 2/RX, that is, currents through M1a, b and M3a, b are constant. Instead, the input signal changes voltages at the low impedance nodes X1, 2 and current IX flows through resistor RX sourcing from M3a, b: IX = (I1 I2)/2 = GmVin where Gm = 2/RX. (5-6) The output currents (I1 and I2) of the transconductor are mirro red to the differential pairs with a 1:1 ratio: I1 = I3 and I2 = I4 (5-7) M2a M2b M1a M1b RX Vout+VinI1 M3a M3b M4a M6a M8b M8a M4b M5a M5b M7a M7b M6b RL1 RL2 RS1 RS2 RY1RY2 I3 I4 I2 Vout Vin+ VC2 VC1 VC1 VC2 Vn Vn VY VY I5 I6 I7 I8 I9 I10 I0 I0 IX IL X1 X2 Y1 Y2 IY IY Y3 Y4

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57 The cross-coupled structure of the Gilbert cell-type differential pairs yields I3 = I5 + I6 and I4 = I7 + I8. The control voltages (VC1 > VC2 > 0) are provided by a differential difference amplifier (DDA) and their differences adjust currents to the output stage: I5 = I3f(VC2 VC1), I6 = I3f(VC1 VC2), I7 = I4f(VC1 VC2), and I8 = I4f(VC2 VC1), (5-8) where 1 > f(VC1 VC2) > 1/2, and f(VC2 VC1) = 1 f(VC1 VC2). (5-9) The output stage consists of load resistors (RL1, 2) with common-mode feedback (CMFB), level-shift resistors (RS1, 2) and current sources (M8a, b). Since I9 = I10, I5 + I7 = I9 IL, and I6 + I8 = I10 IL, (5-10) we can get the output current IL = (I6 I7 +I8 I5)/2. (5-11) Using Equations 5-8 and 5-9, we can rewrite the output current IL = (I3 I4){2f(VC1 VC2) 1}/2, (5-12) and from Equations 5-6 and 5-7, IL = IX{2f(VC1 VC2) 1}. (5-13) The output voltage and voltage gain are Vout = ILRL = 2VinRL/RX{2f(VC1 VC2) 1}, (5-14) Av = Vout / Vin = 2RL/RX{2f(VC1 VC2) 1}. (5-15) The maximum gain is achieved when the difference of the control voltages is maximum (f(VC1 VC2) 1), that is, Av_max 2RL/RX. (5-16) Since DC biasing for the input stage is provided by output stage of an identical VGA stage, the output stage ha s level-shift resistors (RS1 and RS2) to match the input and output common-mode voltage ranges. Voltages in the VGA are highly constrai ned. For negative input swing M1 tends to go triode and M2 tends to go triode for positive input sw ing. To increase the usable input

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58 range, voltage level-shifter (IYRY) is added in the shunt feedb ack path of the FVF, which brings the drain voltages of M1 and M3 closer to the negative s upply rail. To optimize the voltage swing of the linear transconductance cell, the appropriate range of the voltage level-shifter is analyzed. If all transistor pairs are well matched and differential inputs are given as VCM vin, we can write: IX = 2 vin/RX, and vout vin, where vout represents voltage variation at node X1 (or X2) due to vin. For the worst case of applied maximum input + vin to the positive input port Vin+, transistors M2a, M1b and M3b should be in the active region. Conditions on M2a and M1b set the lower limit of the level-shift voltage, while M3b condition set the upper limit. At the edge of the active region, VGS1 = VT1 + V DSAT1, VGS2 = VT0 + V DSAT2 and VGS3 = VTN + V DSAT3, where VTN is NMOS threshold voltage without body effect, and VT0 and VT1 are PMOS threshold voltages without and with body effect, respectively. To keep M2a in the active region, the voltage at node X1 must be less than VDD VDSAT2, that is, VX1 < VDD VDSAT2. (5-17) Let the level-shift voltage V = IYRY, then VY1 = VDD VGS2a V and VX1 = VY1 + VDSAT1 + vout. From Equation 5-17, we can get V > VDSAT1 + vout VT0. (5-18) Simple calculation with maximum vout of 0.25 V and nominal values like VDSAT1 = 0.2 V and VT0 = 0.5 V shows -0.05 V as lower limit of V. This means that no voltage level-shifter is needed in this case to ensure M2 stage in the active region. To keep M1b in the active region, the voltage at node Y2 must be less than VG2 + VT1, that is, VY2 < VG2 + VT1. (5-19)

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59 Solving Equation 5-19 for V with VY2 = VDD VGS2b V and VG2 = VCM vin, we can get V > VDD VDSAT2 VT0 VT1 VCM + vin (5-20) With an input common-mode voltage VCM of about 0.5 V, 1.8 V supply voltage and other nominal values as above, this condition requires a voltage level-shift of more than 0.25 V. The final condition is for NMOS transistor M3b to be in the active region: VY2 > V DSAT3. (5-21) Solving this for V results in V < VDD VT0 VDSAT2 VDSAT3. (5-22) With similar rough calculation, this condition lim its the voltage levelshift value to less than 0.9 V. Thus, by considering all three conditions, the voltage level-shift value must be selected in the range of 0.25 V < V < 0.9 V. Since the two conditions for the voltage level-shift value reference the positive supply voltage, we must allow for supply volta ge variation of 10% (1.6 ~2.0 V). Although we can select the level-shif t value under the worst-case condition (0.25 + 0.2 V < V < 0.9 0.2 V), to optimize signal swing for all VDD values, V should be varied along with the variation of supply voltage. The level-shifters are implemented as linear resistors (RY1 and RY2) with current sources (M4a, b). The current sources are controlled by a voltage VY from a replica bias circuit (F igure 5-7). The replica bias circuit finds VY to make VD_M1 match VD_M12, referenced to ground rather than supply voltage. In this design, the voltage level-shift value V is set to 0.6 V and the voltages near the positive supp ly voltage nodes (Y3 and Y4) vary with VDD while the other nodes (Y1 and Y2) almost keep the same voltage. Inside the replica bias circuit, there are three feedback loops: two negative feedback loops (VY-M4-VA-M2-M1-VB-M11-M13 and VAM2-M1-VB-RY) and one positive feedback loop (VY-M4-VA-RY -VB-M11-M13). Due to the

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60 positive feedback loop, there can be multiple operating points [Fox99]. We need to make sure that only one operating point exists in the replica bias circuit design by using DC simulation for VA and VB as shown in Figure 5-8. Figure 5-7. Schematic of the replica bias circuit for VGA Figure 5-8. Simulation result for finding operati ng point in the replica bias circuit. The result verifies that the bias circuit (for V = 0.6 V) can operate only at the single operating point of VA = 1.26 V and VB = 0.66 V. The VGA structure shows good linearity with la rge gain range. However, there are tradeoffs among gain range, linearity, noise, frequency bandwidth and current consumption in circuit desi gn. Input transistors M1a and M1b have short channels to enhance gm, but increase flicker noise, so PMOS devices were used for this circuitry. M2 M1 M3 M4 M10 RY VinCM Vn M9 M12 M11 VY M13 Vp Vp VA VB 0.66 V 1.26 V VB VA IA = 0 IB = 0

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61 Using long-channel transistors fo r NMOS output current sources (M8a, b) also improves noise performance. Scaling up current along with channel widths reduces noise without changing circuit performance but current c onsumption had to be limited. Although longchannel devices reduce noise, they tend to degrade bandwidth due to large parasitic capacitances. Thus, short-channel transistors are used for Gilbert cell-type differential pairs and current mirrors to achieve adequate bandwidth. The current-mirror output of the VGA enables removing the PMOS tail current source, which saves voltage headroom. Constant current biasing is maintained by th e balanced control voltages from the DDA. 5.3.2 Differential Difference Amplifier A Differential Difference Amplifier (DDA) is used for the amplifier in the inverse gain-control loop because the loop operates in differential mode. A DDA has two differential input pairs and a differential output pair. When used in negative feedback connection with very large open loop gain the DDA forces the two differential input pairs identical [Hun97]. To ensure a wide output control volta ge range, the DDA is implemented as a folded cascade structure as sh own in Figure 5-9. It contains two simple differential pairs (M1, M2, M3 and M4) which compare the difference of the two differential input signal voltages (VC and Vdc). The differential cascode output stages, combined with a common-mode feedback (CMF B) circuit with level-shifters, provide differential output control voltages (Vcp1 and Vcp2) which change with the input difference. The CMFB circuit has a simple structure using source followers with levelshift resistors. Source followers M15 and M16 detect the output voltages of the DDA at their gates, and their corresponding source vol tage difference generates current through R1 and R2. This current shifts the common-mode voltage level VCM which is fed back to the gates of the cascode PMOS transistors M7 and M11. The differentia l control voltages

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62 are set by the feedback as the inverse gain loop forces the two input s to be identical. Since the DDA works with DC control voltages, two compensation capacitors (CC1 = CC2 = 10 pF), grounded in series with resistors, are added to the output nodes for stability. Figure 5-9. Schematic of the proposed Differential Difference Amplifier 5.3.3 RMS Detector The RMS detector estimates the RMS value of the output signal, integrated throughout one short training symbol duration. The RMS circuit is based on the approximately square-law charact eristics of long-channel (~ 2 m) MOSFETs in strong inversion [See87, Han98]. The dynamic range of this circuit is rath er narrow, which is acceptable because the coarse gain-setting step ensures the signals are not far from their optimal value. The RMS output voltage is stored as the difference of the VGS’s of a pair of diode-connected NMOS transistors (Vout+ Vout+). This signal is sampled and held on storage capacitors connected to th e gates of NMOS transistors. The RMS detector in Figure 5-10 uses NMOS transistors in strong inversion as the input squarer. The differential output vo ltages of the VGA with common-mode voltage M1 M2 M3M4M5 M6M7M8M9M10M11M12M13M14M15M16 M17M18 M19 R1R2 VCM CC1 VC+ VCVdcVdc+ Vcp1 Vcp2 CC2

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63 2 2 1 12 1 2 1T in CM n n T GS n nV v V L W K V V L W K I T CM in n nV V with v L W K 2 12are fed to the gates of the NMOS tr ansistors. Let the input signal VIN = VCM vin. The squarer transistor M1 converts input voltage vin to output current I1 as follows: (5-23) The resulting drai n current of M1 is almost proportional to the square of the input voltage if we set VCM VT. Similarly, the drain current of M2 is almost proportional to the square of the input voltage wh en the input signal is positiv e. Above the NMOS squarer are two cross-coupled NMOS differential pairs (M3 ~ M6). They operate like switches to rectify the currents in differential mode. For the differential pairs to work as switches, their gates must be triggered by large signals at the input signal frequency. Hence, the input signals vin+ and vinare boosted as Vn and Vp using amplifiers A and B, and supplied to the gates of the diffe rential pairs. The currents I1 and I2 are rectified to I8 when the input signal is positive and to I7 otherwise. Figure 5-11 plots DC simulation results for V-to-I converted currents (I1 and I2) and rectified currents (I7 and I8), which shows that current I8 is nearly proportiona l to the square of the input voltage. Currents I7 and I8 are averaged and square-rooted to complete the RMS detection. The averaging of the currents is performe d using a cascade of two first-order lowpass filters to meet the estimation time constr aint of a short training symbol (0.8 s). To provide an acceptable trade-off between smoothing and settling time, the on-chip capacitors are set to C1 = 4 pF and C2 = 10 pF, where C2 is bigger because it also used as a storage capacitor. The output current of the first PMOS lowpass filter is mirrored to the second NMOS lowpass filter. In this second filter, the NMOS implements a square-root function by converting the curr ent to a voltage proportional to the square-root of the

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64 current. The gate of the NMOS transistor a nd the storage capacitor are connected with a switch S (small geometry NMOS), which is opened after the symbol duration for the capacitor to hold the stored voltage. Figure 5-10. Schematic of the proposed RMS detector Figure 5-11. DC simulation result s of the RMS detector with VCM = 0.48 and vin = -0.25 ~ 0.25 V: (a) currents I1,2 after squarer and (b) currents I3,4 after rectifier 5.3.4 Computation Block The coarse gain-setting step provides us with a voltage VC1 that is applied to the inverse-gain block (along with Vdc) to set the VGA gains to a value within 5 dB of their 1s t LPF 2n d LPF Vout+ VoutVin+ VinI1rectifier squarer sqrt S S Vin+ VinVp Vn Vn Vn Vp A B M1 M2 M3 M4 M5 M6 M7 M9 M10 M8 M11 M12 I2 I7 I8C1 C2 I2 I1 I4 I3

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65 optimal values. The resulting RMS value Vo1 of the output is measured during t5 and is sampled and held. An analog computation block compares Vo1 to the desired value Vref, and computes the new value of VC2 = VC1 (Vref/Vo1) as discussed in the previous section. The final control voltage VC2 must be applied to the invers e-gain block to force the gain to its optimal value. For the optimal gain after the final control, we assume that the precision of 1 dB is acceptable for the syst em (approximately 0.5 dB is achieved by this computation block) as a de sign target. However, it is not easy to realize the analog computation block with multiplier, divider and square-root function blocks. The analog computation block is implemen ted using translinear circuits based on weak-inversion FETs [Mul99], which reduces power dissipation and complexity of the circuit. This requires that the input and output signals be represented as small (~1 A) single-ended currents. The single-ended cu rrent-mode operation of the computation block tends to be noisier than the different ial mode. This reduces the accuracy of the computation, but the noise does not couple in to the VGA signal path, since the gain is fixed during transmission of the data packet. Figure 5-12 shows V-to-I and I-to-V converters with single-ended and/or differential mode terminals. The differential voltage to single-ended current converter in Figure 5-12 (a) is placed between RMS dete ctor5 (RD5) and the computation block, which converts the output differe ntial voltage of RD5 to Io1 in the computation block. This V-to-I converter provides a linear out put current which is attenuated to around 1 A. The NMOS input transistors M1 and M2 have 5 times less transconductance compared to the output NMOS transistors of the RMS detector. PMOS transistors M5 and M6 are connected to the active loads (M3 and M4) of the input devices w ith shunt feedback, and

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66 Figure 5-12. V-to-I and I-to-V converters in (a) differentia l V to single-ended I (b) single-ended V-to-I, and (c) single-ended I to differential V modes work as source followers. The low impedan ce output nodes of the source followers are connected through a big li near resistor R (30 k ). The difference of the two input voltages creates a voltage between sources of M5 and M6, and thus a small amount of current IR across the resistor R. IR flows through M6, M8 and M9, and is mirrored to Io1 via the 4:1 attenuation cascode current mirror (M8, M9, M10 and M11). This differentialvoltage to single-ended current conv erter/attenuator provides around 1 A of single(a) (b) (c) M1 M2M3 M4M5M6M7R IR M8M9M11 M10 Io Io1 Vin+ VinVin Rd M1 I2 I1 Io Iin Io M2 M3 M5M4M6M7M1M2M4 M3 M5 M6R1 R2 VoVo+ ICM

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67 ended current output to the co mputation block for a voltage input of about 250 mV from RMS detector. The single-ended V-to-I converters in Figure 5-12 (b) convert single-ended voltages Vref and VC1 to single-ended currents Iref and IC1. A low gm NMOS transistor (M1) with degeneration resistor Rd (15 k ) converts input voltage Vin to current I1. This current is mirrored through a 4:1 attenuation cascode current mirror (M2, M3, M4 and M5) and is mirrored again through the 2:1 attenuation current mirror (M6 and M7) to achieve an output current Io of around 1 A for the computation block. Single-ended current to differential voltage converter in Figure 5-12 (c) converts the output current IC2 of the computation block to the input differential voltage VC2 of the inverse gain control block. This I-to-V c onverter amplifies its i nput current using a 1:4 cascode current mirror (M1, M2, M3 and M4), and the amplified output current Io creates two equal voltage drops in se ries-connected resistors R1 and R2. Differential output voltages are supplied at the top of R1 and at the bottom of R2. The gate of the M5 connects to the node between R1 and R2 to set the common-mode voltage. M6 delivers a common-mode current ICM to the drain of M5, which provides a common-mode voltage to the gate of M5 even when there is no input current applied. Single-ended voltages VC1 from the switched gain control block and Vdc are converted to differential input voltages of the inverse gain control block through a cascade of a single-ended V-to-I converter a nd a single-ended current to differential voltage converter to minimize mismatch with the other differential control voltage VC2 converted from the current mode computation block.

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68 Figure 5-13. Schematic of the proposed analog computation block. The arrows indicate the VGS’s that form the translinear loop. The schematic of the proposed analog computation block is shown in Figure 5-13. Applying the translinear characteristics in weak inversion, we get the desired computation as written in the following equations. VGS_C1 VGS_C1 + VGS_o1 VGS_ref + VGS_C2 + VGS_C2 = 0 (5-24) ln IC1 ln IC1 + ln Io1 ln Iref + ln IC2 + ln IC2 = 0 (5-25) ln IC2 2 ln IC1 2 = ln Iref ln Io1 (5-26) ln (IC2/IC1)2 = ln (Iref/Io1) (5-27) IC2 = IC1.Iref/Io1 (5-28) This circuit provides an output current IC2 with expected computation when the input currents IC1, Io1 and Iref are applied. To guarantee translinear ope ration in weak inversion w ith currents of about 1 A and lower, PMOS transistors are large sized: W/L = 200/1 m for M1, M2, M8 and M9. For the differential pair M3 and M4, longer channel with sma ller widths are used to provide good matching. M2, M3, M4 and M9 have separate n-wells to remove errors due IC2 IrefIo1IC1 M1 M2 M8 M9 M6M7M5M3M4

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69 to bulk effect. Also, fast and stable operati on is achieved by adjusting channel length for inner loop transistors M5, M6 and M7. 5.3.5 Switched Gain Control 2 The switched gain control block is im plemented using latched comparators, transmission gate switches, and tw o reference voltage generators (VINIT and VTH) as shown in Figure 5-14. A latched comparator which is a folded-cascode differential amplifier with a dynamic latch load compares two inputs, Vin (output from RMS detector) and Vth (threshold voltage from the reference voltage generator VTH), and yields differential outputs to activate transmission gate switches: either SA or SB. When the latch signal goes from 0 to 1, the crossconnected positive feedback loop forces the differential output voltages to be latched [Ock99]. The resu lt of the comparison of the two inputs decides the polarity of the output. The output of the latched comparator is connected to the gates of transmission gate switches (SA and SB) which select between two voltage inputs. The switc hing connection to select VC1 is completed when the transmission gate switch S1 is on. Three sets of latc hed comparators and transmission gates select gain-control voltage out of four initial voltages by comparing the outputs of the RMS detectors and the thre shold voltages, as described in the AGC algorithm section. The initial voltage and threshold voltag e generators provide reference voltages which are preset by resistor banks. The initial voltage generator VINIT provides six preset voltages V-3dB, V0dB, V7dB, V12dB, V17dB and V27dB. V-3dB, V7dB, V17dB and V27dB are selectable VC1 voltages, while V0dB and V12dB are VDC voltage and VC0 voltage for the initial VGA gain, respectively. As we men tioned before, the inverse gain control loop sets the two-stage VGA gain as Av = 40log(VC1/VDC) dB. So, VC1 can be found such that VC1 = VDC 10Av/40. (5-29)

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70 Figure 5-14. Switched gain control block im plementation using latc hed comparators and transmission gates With VDC = VCM 35 mV, the differences of the differential VC1 (including VDC and VC0) voltages for V-3dB, V0dB, V7dB, V12dB, V17dB and V27dB are 58.5, 70, 104.8, 139.6, 186.2 and 331.2 mV, respectively. Since single-ended VC1 is converted to a corresponding differential VC1 through V-to-I and I-to-V converter s, we can find the single-ended voltages for V-3dB, V0dB, V7dB, V12dB, V17dB and V27dB by DC simulation of those two converters. Figure 5-15 shows DC simulation result of the single-ended V-to-I and I-todifferential V conversion fo r gain control voltage VC1. V17dB VN2VN1latch VP1 VIN VTH VOPVONLatched Comparator 1 SW1 If V I N < VTH then VO = V B else VO = VAVA VB VO LC2 SW2 LC3 SW3 VORD3V-3dBV7dBV12dBV27dBV-20dBmV-30dBmVORD4 VTH VINIT V0dB VDC VC1 SASBS1 SW0 VC0 VC1

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71 V0dB single-ended VC1(V) differential VC1(V) V-3dB V7dB V17dB V27dB V12dB V0dB single-ended VC1(V) differential VC1(V) V-3dB V7dB V17dB V27dB V12dB Figure 5-15. DC simulation result of the single-ended V-to-I and I-to-differential V converters (single-ended VC1 versus differential V C1) The corresponding single-ended VC1 voltages for V-3dB, V0dB, V7dB, V12dB, V17dB and V27dB are 687, 716, 798, 871, 963 and 1279 mV. These preset control voltages for switched gain are implemented using resistor banks as shown in Figure 5-16. Applying an external 1.5 V supply voltage to a branch with total resistance of 15 k enables tapping out the desired voltages with correspond ing ratio of tapped resistors (Figure 5-16 (a)). In order to improve matching and to reduce process variations, each section of resistor is made of serial a nd parallel connections of a root component resistor as shown in Figure 5-16 (b) [Sai02]. For example, by choosing 2.32 k as the root resistor RR, the 0.29 k resistor between V-3dB and V0dB is realized as eight pa rallel connections of the root component. Another reference vo ltage generator VTH provides three threshold voltages (V-20dBm, V-22dBm and V-30dBm) for latched comparators. The reference voltage V-20dBm is preset to the positive output value of the RMS detector with 500 mVpp input signal (desired output

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72 Figure 5-16. Reference voltage generator VINIT has six taps for preset voltages and is implemented as serial and parallel connections of a root component resistor. signal level). Other reference voltages V-22dBm and V-30dBm are preset to the value of the RMS detector with 397.2 mVpp and 158.2 mVpp input signals which are 2 dB and 10 dB less than the desired one, respectively. These preset voltages are compared with actual output voltages of RMS detect ors by latched comparators during the switching gain control step. Applying the same method used for VINIT, the reference voltage generator VTH is implemented using a resistor bank (Figur e 5-17). Note that tw o different sets of threshold voltages are provided w ith signal type selection, si nce RMS values are different between sine wave signal (sine) and short training symbol (STS). V27dB V17dB V12dB V7dB V0dB V-3dB2.21k 3.16k 0.92k 0.73k 0.82k 0.29k 6.87k + -1.5 V(a) (b) RR = 2.32 k

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73 Figure 5-17. Reference voltage generator VTH provides threshold voltages (V-20dBm, V22dBm and V-30dBm) either for short training sym bol signal or for sine wave signal. 5.4 IC Implementation and Measurement 5.4.1 IC Implementation with Embedded Test Points The portion of the AGC circuits following th e channel-selection filter in Figure 5-2, including two VGAs, switched gain control 2 and AGC with one-step correction, was fabricated using a 0.18 m CMOS process av ailable through MOSIS. On-chip embedded test points are included in the design for test ability. Analog test buses provide access to V-20dBm sineV-22dBm sineV-30dBm sine V-20dBm STS V-22dBm STSV-30dBm STSSwitch for sine/STS selection RR = 4.8 k RR = 2.54 k

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74 internal nodes using switching structures [B ur01]. Figure 5-18 shows the AGC circuitry with 7 test points (SWT1 ~ SWT7). The main signal chain of the AGC circuit consists of two VGA stages as described in the previous section. Combined with external coupling capacitors (C 0.1 F), input bias voltages for VGA2 are prov ided by on-chip resistors (R 240 k ) in a negative feedback loop from the output nodes of VGA3 This feedback loop works as an RC lowpass filter which provides dc bias voltage to the input stage. Output signals can be measured through voltage buffers which reduce the output impedance of the AGC circuit. Simple PMOS source followers are used as voltage buffers as shown in Figure 5-19. Since these buffers are for test purpose, 3 V devices are used to accommodate level shifted DC bias voltage (0.48 V 1.48 V). The current source M2 provides 1 mA of DC bias current for good sourcing capability which enables this buffer to sink a large current from the load concerning large-signal behavior. The bulk of M1 is tied to the source using a separate n-well, which elim inates nonlinearity due to body effect. As designated in Figure 5-18, seven test po int switches are placed as follows: 1) at the output nodes of RD3, 2) between the output nodes of RD5 and the Vo input nodes of V-to-I converter, 3) between the Io output branch of V-to-I converter and the Io input branch of computation bl ock, 4) between the Iref output branch of V-to-I converter and the Iref input branch of computati on block, 5) between the IC2 output branch of computation block and the IC2 input branch of I-to-V c onverter, 6) between the output nodes of VC1/VC2 time switch and the Vc input nodes of DDA, and 7) between the Vdc output nodes of I-to-V converter and the Vdc input nodes of VGA4. Test switches 3), 4)

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75 and 5) are current switches implemented usi ng current mirrors with transmission gate switches while others are voltage switches (transmission gate switches). Figure 5-18. Proposed AGC circ uitry with 7 test points RD3 RD4 VGA2 VGA3 DDA buffer buffer LC1 LC2 LC3 SW1 SW2 SW3 Vinit SW0 Vth SWT1 VDC VC1 VGA4 SW SWT6 I-V V-I SWT7 I-V V-I I-V SWT5 V-I SWT2 RD5 Vref V-I SWT3 SWT4 Comp VDC VC1 IN OUT Test_IN Test_OUT One-step Gain Control Switched Gain Control VC2

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76 Figure 5-19. Output voltage buffer All test points are connected with differen tial in/out test buses through input/output test switches, and the test buses are connected to four pads (Test_in+, Test_in-, Test_out+ and Test_out-). From the test pads, we can access one out of seven test points, selectable using test switches. Internal signal paths ar e connected as normal when the test switches are off. However, one of the test switches is on, the internal signal path of the point is disconnected and the test point is externally accessible. For example, if we turn the test switches 7_IN and 7_OUT on, then the Vd c output nodes of the I-to-V converter are connected to Test_out+ and Test_outpads and the Vdc input nodes of DDA are connected to the Test_in+ and Test_inpads. In this switc h selection, we can monitor internal Vdc from Test_out pads and force an external Vdc value to Test_in pads during measurement. The voltage switch SWT7 in Figure 5-20 (a) has two selections, that is, SWTi for test input and SWTo for test output, and eight transmissi on gates for differential signal paths, where four of them (A, B, C and D) are used for positive signal paths. Two M1 M2

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77 internal nodes (Vip and Vop) are connected through transmission gates A and C when both switches are set to 0. Setting SWTo to 1 for ces transmission gate A to off and B to on, which changes connection from Vip-Vop to Vip-Top. Thus, internal voltage of node Vip can be monitored through the pos itive test output pad Top. Similarly, setting SWTi to 1 makes Vop connected to Tip, thus external input can be forced into Vop node through the positive test input pad Tip. Figure 5-20 (b) shows current switch SWT5, used for testing the Ic2 branch in the computation block. Two selec tions are SWTi for te st input and SWTo for test output. Voltage switch box SW_I connects Vn2 to VN node and ground (0) to VTi and VTo nodes when both switches are off. In this switch connection, the output current flows through the Ic2 branch via the M1-M2-M3-M4 current mirror. When SWTi is set to on, the gate of M4 is switched to ground; hen ce, the Ic2 branch is disconnected from the computation block. At the same time, the ga te voltages of M6 and M9 are switched from ground to Vn2, which enables connection fr om Tin to Ic2 via M6-M7-M8-M9 current mirror. For the test output, switch sw5To is se t to on. This makes transistor M4 off and transistor M5 on, thus the output current flows through Tout branch via M1-M2-M3-M5 current mirror. 5.4.2 Simulation Results The implemented AGC circuits were simu lated using Cadence Spectre with TSMC 0.18 mmodels. Figure 5-21 shows DC simulation results for the VGA in the inverse gain control loop. By applying control voltage Vc to the inverse gain loop, we can easily achieve a linear gain control charac teristic with desired gain of Av = Vc/Vdc.

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78 With Vdc = 35 mV, we can get the VGA gain of -4 dB by setting Vc = 22.1 mV, of 0 dB by setting Vc = 35 mV and of 16 dB by setting Vc = 221 mV. When Vin is set to 39.6 mV, the simulation result shows that Vout changes from 25 mV to 247 mV with Vc, a range of -4 to 16 dB. This is just a -0.1 dB gain e rror at the maximum gain (16 dB). Another DC simulation is for the inputoutput linearity of the VGA. Figure 5-20. Test switch es; (a) voltage switch, and (b) current switch (a) (b)M1 M2 M4 M3 M9 M8 M6 M7 M5 Tout Tin Ic2 SW_I VTi VTo V N VN VTi VTo SWTi SWTo Vn2 gnd SWTi SWTo To Ti A B C D Vi p Vi p Vo p Vo p Computation Block

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79 Figure 5-21. DC gain control simulati on for the VGA with inverse gain loop Figure 5-22 (a) shows Vin vs. Vout plot at the minimum gain (-4 dB), while Figure 5-22 (b) shows the plot at the maximum gain (16 dB). The simulation results show that the linearity error for the maximum input (250 mVp) at the minimum gain is 0.36 dB and the linearity error for the maximum output (250 mVp) at the maximum gain is -0.1 dB. AC response plots of the two-stage VGA shown in Figure 5-23 ensure the operation of the VGAs in the channel frequency range (156.25 KHz ~ 8.3 MHz). Figure 5-22. DC simulation for Vin versus Vout of the VGA at (a) -4 dB gain and (b) 16 dB gain (a) (b) Vout (-4 dB)(16 dB)

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80 Figure 5-23. AC response of the VGA; (a) gain and (b) phase Noise simulation indicates that the tota l output noise of the VGA for the signal bandwidth (156.25 KHz ~ 8.3 MHz) at 0 dB gain is 221 Vrms. Input referred noise can be derived as: 221e-6/ 8.14e6 = 77.5 nV/ Hz. Figure 5-24 shows noise versus gain plot of the VGA. Input referred noise at th e minimum gain (-4 dB) is about 120 nV/ Hz due to negative gain, but it goes down to 97 nV/ Hz at the actual minimum gain without margin (-2 dB). Moreover, as VGA1, located be fore channel-select f ilter, has 7 or 14 dB selectable gain, the input referred noise of the analog baseband processor would be below 40 nV/ Hz. The linearity of the 2-stage VGA is sp ecified by single-tone total harmonic distortion (THD) in -8, 0 and 32 dB gain m odes in Figure 5-25. The 2-stage VGA shows 0.99 % THD at the maximum gain (32 dB), while it shows 1.03 and 1.36 % THDs at 0 dB and minimum (-8 dB) gains, respectively. -3 dB @ 48 MHz -45 @ 9.6 MHz -135 @ 28 MHz ( a ) ( b ) Frequency

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81 Gain vs. Noise76 76.6 77.5 81 89.3 107.6 123.2 145.7 120.6 97 77.5 51.3 35.6 27 24.6 23.1 0 20 40 60 80 100 120 140 160 -4-20246810121416Gain (dB)Noise (nV/sqrt(Hz)) out noise in noise Figure 5-24. VGA input and out put noise versus gain Figure 5-25. Linearity of the 2-stage VGA in THD (%) versus input signal voltage plots at (a) -8 dB, (b) 0 dB and (c) 32 dB gain settings Figure 5-26 shows the input versus output ch aracteristic of the RMS detector. Plots (a) and (b) are drawn in dB range, where (a) is for a sine wave input and (b) is for a short training symbol. The input versus output char acteristics for sine waves and short training symbols have about 21 dB (-18 to 3 dB) of dynamic range with reasonable linearity. Vin (V) THD (%) Vin(V) (a) (b) (c)

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82 Figure 5-26. Input versus output characteristic of RMS detector ; (a) for sine wave signal and (b) for short training symbol The input voltage versus output current ch aracteristic of the V-to-I converter is shown in Figure 5-27 (a). The V-to-I convert er takes the differential voltage from the RMS detector as input and c onverts it to a single-ended outpu t current which flows into the computation block as Io1. To make sure the current m ode circuit operate fast enough for the settling time constraints, the V-to-I c onverter was designed with fast step response (Figure 5-27 (b)). Figure 5-28 shows the input versus output plot of the I-to-V converter. Figure 5-27. Characteristic of V-to-I converter; (a) input vers us output linearity and (b) step response (a) (b) Iout Iout

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83 Figure 5-28. Input versus output ch aracteristic of I-to-V converter The differential output voltage (0 ~ 500 mVpp) changes linearly along with the single-ended input current (0 ~ 1.5 A). The small increase (~20 mV) of the commonmode voltage over the range does not affect th e differential output voltage of the I-to-V converter. Simulation results of the proposed analog computation block for sine wave and short training symbol signals are shown in Figures 5-29 and 5-30, respectively. As discussed in the circuit desi gn section, the computation bl ock operates in current mode with three inputs (Io1, Iref and IC1) and generates one output (IC2). The plots show the output (IC2) versus input (Io1) characteristic, since the currents Iref and IC1 are fixed in the final gain setting step. The sw itched gain control current IC1 is set to one of the four preset values: 256 nA (-3 dB), 452 nA (7 dB), 794 nA (17 dB) and 1.397 A (27 dB). The reference current Iref is set to 1.025 A for sine wave or to 631 nA for the short training symbol signal. Agai n, this computation block co rrects the VGA gain, which was set to a switched gain with 5 dB error range, to the final ga in with 1 dB error. Figure 5-29 shows simulation results for sine wave signals, with Io1 swept from 500 nA (-6.2 dB from Iref) to 2 A (5.8 dB from Iref). The simulated control current IC2 is plotted in the Vout+Vout-VCM

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84 black curve while the ideal curve is drawn in gray. The largest error between the simulation and the ideal is -0.36 dB when Io1 is bigger (5.8 dB) than Iref with -3 dB switched gain. Figure 5-30 shows the simulation results for short training symbol signals, with Io1 swept from 300 nA (-6.5 dB from Iref) to 1.2 A (5.6 dB from Iref). In this simulation, the largest error is -0.4 dB when Io1 is smaller (-6.5 dB) than Iref with 27 dB switched gain. Figure 5-31 depicts the step response of the computation block, which demonstrates that the current-mode operation in weak inversion s hould meet the settling time constraints of the system. Figure 5-29. DC simulation results of the com putation block for sine wave signal with the switched gain of (a) -3 dB, (b ) 7 dB, (c) 17 dB, and (d) 17 dB Iref IC1(-3dB)IrefIC1(7dB) IrefIC1(27dB) Iref IC1(17dB) -0.36 dB error -0.17 dB error -0.27 dB error -0.26 dB error (a) (c) (b) (d)

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85 Figure 5-30. DC simulation results of the co mputation block for short training symbol signal with the switched gain of (a) -3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB Figure 5-31. Transient simulation result (s tep response) of the computation block The proposed AGC circuit in Figure 5-18 is simulated using transient response for both sine wave and short traini ng symbol signals. Given a se ttling time requirement of 7 Iref IC1 (-3dB)IrefIC1(7dB) IrefIC1(27dB) Iref IC1(17dB) -0.21 dB error -0.22 dB error -0.4 dB error -0.13 dB error (a) (b) (c) (d)

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86 short training symbol times, the implemented AGC circuit uses symbol time duration from t3 through t7 (50.8 = 4 s). The initial gain for two-stage VGA is set to 12 dB. The switched gain is selected du ring t4 and the final gain is adjusted during t6. Figure 532 shows output signals with the final gain of (a) -4 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB, where the switched gain of -3 dB for (a) and (b), and 7 dB for (c) and (d) are selected. Simulation results with small sine wave i nputs to get the final gain of (a) 15 dB, (b) 20 dB, (c) 23 dB and (d) 28 dB are shown in Figure 5-33. Similar simulations with short training symbol inputs are presented in Figures 5-34 and 5-35. From the simulation results, it can be observed that the AGC circ uit adjusts signals to the desired level with gain error less than 1 dB through th e actual gain range of -4 ~ 28 dB. 5.4.3 IC Measurement and Analysis The proposed AGC circuit in Figure 518 was laid out using the TSMC 0.18 m process with 6 metal layers. Figure 5-36 s hows the full chip layout floor plan including 40 bonding pads. The total chip area includ ing ESD (Electro-Stati c Discharge) bonding pads is 2850 2850 m, whereas the actual AGC circuit area is 750 750 m. The die photo of the fabricated AGC ci rcuit is shown in Figure 5-37. The fabricated parts are packaged in DIP40 (40-pin ceramic package). The package samples were measured us ing a test board to get access to the embedded test points. Figure 5-38 illustrates the test board design for the packaged AGC circuit. The test board includes DIP switc hes for embedded test point selection and input-output matching connectors. The selectable output buffe r stage is also included in the test board to provide matching with the 50 test equipments. The test board shown in Figure 5-39 was designed and built by the support of Conexant Systems. A detailed schematic of the test board is attached as an appendix.

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87 Figure 5-32. Transient simulation results of the AGC circuit for sine wave signal with final gain of (a) -3 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB 12 dB -3 dB -4 dB 12 dB -3 dB 1 dB 12 dB 7 dB 4 dB 12 dB 7 dB 9 dB Error = 0.49 dB Error = 0 dB Error = 0.32 dB Error = 0.29 dB t3 t4 t5 t6 t7 (a) (b) (c) (d)

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88 Figure 5-33. Transient simulation results of the AGC circuit for sine wave signal with final gain of (a) 15 dB, (b) 20 dB, (c) 23 dB and (d) 28 dB 12 dB 17 dB 15 dB 12 dB 17 dB 20 dB 12 dB 27 dB 23 dB 12 dB 27 dB 28 dB Error = -0.35 dB Error = 0.34 dB Error = -0.18 dB Error = -0.14 dB t3 t4 t5 t6 t7 (a) (b) (c) (d)

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89 Figure 5-34. Transient simulation results of the AGC circuit for short training symbol signal with final gain of (a) -3 dB (b) 1 dB, (c) 4 dB and (d) 9 dB 12 dB -3 dB -4 dB 12 dB -3 dB 1 dB 12 dB 7 dB 4 dB 12 dB 7 dB 9 dB Error = -0.99 dB Error = 0.47 dB Error = 0.14 dB Error = 0.12 dB t3 t4 t5 t6 t7 (a) (b) (c) (d)

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90 Figure 5-35. Transient simulation results of the AGC circuit for short training symbol signal with final gain of (a) 15 dB (b) 20 dB, (c) 23 dB and (d) 28 dB 12 dB 17 dB 15 dB 12 dB 17 dB 20 dB 12 dB 27 dB 23 dB 12 dB 27 dB 28 dB Error = -0.45 dB Error = 0.06 dB Error = 0.36 dB Error = -0.37 dB t3 t4 t5 t6 t7 (a) (b) (c) (d)

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91 Figure 5-36. Full chip layout floor plan of the AGC circuit including ESD bonding pads and decoupling capacitor between positive supply and ground With all prepared measurement setup including test board, some unexpected problems were found during basic DC measuremen ts. The first one is oscillation in DC bias voltages. The bias circuit, shown in Fi gure 5-40, consists of simple current mirrors providing gate voltages to cascode struct ures of PMOS and NMOS transistors. An external resistor is connected to allow the bias current to be vari ed. It is designed to provide 30 A with an external resistor of 7.8 k A grounded variable resistor (Rvar) on the test board is connected to the Rext pin of the package and its value can be adjusted to provide the desired bias current in spite of process variations. However, the positive AGC Cdecou p lin g S0T Swr1 S5To S5Ti Rext S3Ti S3To S2To S2Ti N/C Vinit Vth sine latch Sws Swt1 Swr2 Swt2 S1To S1Ti N/C Vip Vinvdd1vdd3vRext3VonVopvdd2 N/C S6To S6Ti gnd1gnd2TinTipTonTopS4To S4Ti

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92 feedback loop oscillates when the para sitic C reduces the impedance at the Rext port. This oscillation was eliminated by reducing the para sitic C. Instead of using the direct onboard connection of the variab le resistor which has high parasitic C, a fixed value of resistor (Rb) is added between Rext pin of the package and Rvar. In addition, a ferrite bead was inserted in the Rext pin connection. Figure 5-37. Die photo of the fabricated AGC circuit Another problem in the measurement is th at the input DC bias voltages in most chip samples were higher than expected. The input DC bias voltages are provided by output bias voltages created from diode-conne cted NMOS transistors using resistive negative feedbacks. The DC bias voltages we re designed to be about 0.48 V, but the measured values are in the range of 0.53~0. 56 V. Since this voltage corresponds to V V G G A A 3 3 V V G G A A 2 2 V V G G A A 4 4 D D D D A A C C o o m m p p u u t t a a t t i i o o n n b b l l o o c c k k R R M M S S d d e e t t e e c c t t o o r r 3 3 R R M M S S d d e e t t e e c c t t o o r r 4 4 R R M M S S d d e e t t e e c c t t o o r r 5 5 B B i i a a s s c c i i r r c c u u i i t t s s V V I I c c o o n n v v e e r r t t e e r r S S W W g g a a i i n n b b l l o o c c k k

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93 Figure 5-38. Test board design fo r the 40-pin AGC circuit package Figure 5-39. Test board with a packaged AGC sample plugged in S1Ti S1To S3Ti S3To S2Ti S2To S0T S4Ti S4To S5Ti S5To S6Ti S6To vdd3vRext3 vdd Rext VipVinVonVop gnd TinnTinpTonTopDIP SW sine Vinit Vth latch SWs SWr1 SWr2 SWt1 SWt2 Signal I/O, Bias Pulse signals Test I/O

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94 Figure 5-40. Bias circuit with external resistor connection: (a) can cause oscillation and (b) can fix the problem. VGS_M8 VRs of the output NMOS devices of the V GA in Figure 5-6, process variations in transistors’ size does not explain the volta ge difference. Instead, the variation of the model parameters such as th reshold voltage parameter VTH or transconductance parameter gm may explain the DC voltage differences. Measurements of singletransistor characteristics ar e possible using embedded test point connections. As shown in Figure 5-41, the measurement results in dicate that there exist transconductance differences between simulations and measur ements, while extracted threshold voltages VTH are almost identical to th e simulation value. Similar analysis can be done through bias current versus voltage measurements in the bias circuit. The measurement results show that a higher external resistor (~8.5 k ) than simulated (~7.8 k ) is needed to get the desired bias current (~30 A), consistent with the lower gm of the fabricated FETs. Ib = 30 A Loo p C p ara R va r C p ara R va r R b (a) (b) M1M2M3M4M5M7M8M9M10M6M11

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95 Figure 5-41. Measurement results on device characteristics with various embedded test point selections: (a) di ode-connected NMOS in RMS detector (W/L=5/10 m), (b) diode-connected NMOS in cascode current mirror (W/L=3/3 m), (c) threshold voltage extraction (diode-c onnected NMOS), and (d) measurement plot on bias current vers us external resistor. The third problem observed in the measurement of packaged samples is another device parameter shift: the measured resistor va lues are lower than the simulated values. Figure 5-42 shows the measurement of resistan ce between the two input nodes. The loop for measurement includes feedback resistors (Rfb = 240 k ), output load resistors (RL = 10 k ) and shift resistors (RS = 244 ) of the VGA. Although the designed and simulated resistance value of the two input nodes is ~500.5 k the measured values for 20 samples lie between 428 k and 437 k The measurement result shows shifted resistance value of -14 %. Diode-connected NMOS: Vth extraction0 500 1000 1500 2000 2500 3000 3500 4000 00.10.20.30.40.50.60.70.80.91 Vgs (V)sqrt(Id) (uA) measurement #18 VTH_Measured VTH_Simulation 440 mV Diode-connected NMOS I V0 10 20 30 40 50 60 70 80 90 100 00.61.21.8 Vgs (V)Id (uA) simulation measurement #18 gm 50 A/V gm 81.2 A/V Bias Circuit variability20 25 30 35 40 7.588.599.5 R (K Ohm)Ib (uA) measurement #12 sim sim (low gm) Cascode NMOS in CM0 2 4 6 8 10 12 14 16 18 00.10.20.30.40.50.60.70.8 Vgs (V)Id (uA) sim measurement #12 ( a ) ( c ) ( b ) ( d )

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96 Resistance between two input nodes (20 samples)0 1 2 3 4 5 6 428429430431432433434435436437Resistance (K Ohm)Frequency Figure 5-42. Measurement of on-chip resistor variation: (a) resist ors between input nodes and (b) measurement results for 20 samples After fixing these problems in the meas urement environment, the gain control function of the two-stage VGA is measured. As described before, VGA gain is set by the inverse-gain block using two dc voltages: Av = VC / Vdc. Sine wave signals from an Agilent 33120A were used for input signals. The amplitudes of the output signals are measured to compute gains using Agilent 54622D oscilloscope. Control voltages are applied to the inverse gain l oop through test points 6 and 7. Measurement results of the gain control function in Figure 5-43 match simu lation results closely. The replica bias circuit in Figure 5-7 minimizes the effects of supply voltage variations on VGA gain as shown in Figure 5-44. Rfb=240K RL=10K RS=244 Input nodes (a) (b)

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97 Gain vs. Vc/Vdc-8 -4 0 4 8 12 16 20 24 28 32 -8-4048121620242832 Vc/Vdc (dB)Gain (dB) meas Ideal sim Figure 5-43. Gain control curve for the 2-stage VGA VGA gain with Vdd sweep-10 0 10 20 30 40 1.61.71.81.92 Vdd (V)gain (dB) gain (-8dB) gain (12dB) gain (32dB) Figure 5-44. 2-stage VGA gain with supply voltage variation The stability of the VGA gain with bias cu rrent and temperature variations is also measured, as shown in Figure 5-45. The gain e rrors due to bias current variation are 0.7 dB at 28 A and -0.87 dB at 33 A. The temperature variation from 5 to 80 C

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98 generates gain errors from 0.4 to -1.1 dB. Figure 5-46 shows the i nput-output linearity and harmonic distortion plots of the chip at 12 dB gain. The VGA output signal was measured 37.5 dB of spurious-free dynami c range (SFDR), which showed only 3.4 dB reduction from 1 MHz sinusoidal input signal (4 0.9 dB of SFDR). Frequency responses of the 2-stage VGA at -8, 12 and 32 dB gain ar e shown in Figure 5-47. This verifies the operation of the VGA over the channel bandwidth of 156.25 KHz ~ 8.3 MHz. Figure 5-45. Stability of VGA gain with (a) bi as current and (b) temperature variations Ib VGA gain error-0.87 0.7 -1 -0.5 0 0.5 1 282930313233 Ib (uA)gain error (dB) Temp VGA gain error0.4 -1.1 -1.2 -0.8 -0.4 0 0.4 0.8 52035506580 Temp (C)gain error (dB) (a) (b)

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99 Linearity (Vin vs. Vout @ 12 dB)100 200 300 400 500 100200300400500 Vin 12dB (mV)Vout (mV) measurement Ideal Figure 5-46. 2-stage VGA characteristic at 12 dB gain: (a) inputoutput linearity, (b) SFDR Frequency Response (measurement)-20 -10 0 10 20 30 40 Frequency (Hz)Gain (dB) -8dB 12dB 32dB Frequency Response (simulation)-20 -10 0 10 20 30 40 Frequency (Hz)Gain (dB) -8dB 12dB 32dB (a) (b) Figure 5-47. Frequency response of the 2stage VGA: (a) measurement result and (b) simulation result Figure 5-48 shows input versus output plot of the RMS detector. The measurement result agrees well with the simulation result. The small deviation from ideal is reasonable for the simple square-law based RMS detector and is acceptable in meeting system gainaccuracy specification. Th e V-to-I converter between the RMS detector and the computation block was measured by applying in put voltages to test point 2 and detecting output current from test point 3. The resul ting linear conversion plot of the measurement (a) (b) 100 1K 10K 100K 1M 10M 100 1K 10K 100K 1M 10M

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100 is shown in Figure 5-49. The measured inpu t-output characteristic of the current-mode computation block is shown in Figure 5-50, which shows that the measurement results agree well with the simulation results. Table 5-1 summarizes the simulation and measurement results. Pseudo RMS detector0 0.1 0.2 0.3 0.4 0.5 0.6 00.10.20.30.40.50.60.70.8 Vin_pp (V)Vout (V) Vo (sine) Vrms (ideal sine) Vo (simulation) Figure 5-48. Measurement result for input-out put characteristic of the RMS detector V-I converter0 0.5 1 1.5 2 2.5 0100200300400500 Vin_pp (mV)Iout (uA) Figure 5-49. Measurement result for input-output characteristic of the V-to-I converter

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101 Computation block (Io1 vs. Ic2)0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0.20.40.60.811.21.41.61.82 Io1 (uA)Ic2 (uA) Ic2_measured lc2_simulation Ic2_ideal Figure 5-50. Measurement result for input-out put characteristic of the current mode computation block Table 5-1. Summary of the simulation and measurement results Simulation Measurement Process 0.18 m CMOS 1P6M0.18 m CMOS 1P6M Die size (with 40 pads) 2.85 2.85 mm2 2.85 2.85 mm2 Die size (AGC only) 0.75 0.75 mm2 0.75 0.75 mm2 Power supply 1.8 (1.6~2.0) V 1.8 (1.6~2.0) V Itotal 5.6 mA 5.8 mA AGC output voltage 500 mVpp_diff 500 mVpp_diff 2-stage VGA frequency response (1.5 dB) 1 kHz to 16 MHz 0.8 kHz to 18 MHz AGC gain range -8 to 32 dB -8 to 32 dB AGC gain accuracy 1 dB -AGC settling time 4.8 s -Input referred noise (@ 0 dB gain) 77.5 nV/ Hz -THD (1 MHz @ 0 dB gain) 1 % -

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102 CHAPTER 6 SUMMARY AND FUTURE WORK 6.1 Summary WLAN technologies are so popul ar these days that even casual PC users may have heard about 802.11a, b, or g. While impl ementing one-chip RF transceivers is a challenge, using CMOS process technology can be a solution due to its high integration capability and low cost. This research focuses on the design of an analog baseband processor for a CMOS 802.11a WLAN receiver. The main functions of an analog baseband processor are channel-select filt ering and AGC. Since 802.11a uses OFDM signals, which have a high PAPR, we need to analyze signal estimation for AGC and devise an efficient AGC algorithm for th e analog baseband processor design. The following summarizes the major research items. In Chapter 2, background knowledge and specifications for the IEEE 802.11a standard were described. The standard speci fies 20 MHz of channel bandwidth with 52 OFDM subcarriers in a 5-GHz RF frequency range. For data reception of each packet frame, seven short-training-symbol times (5.6 s) of preamble are allocated for AGC convergence. The standard details the rece iver performance requirements which guide attenuation specifications for channel-select filtering. Also, the system architecture for the analog baseband signal chain block was presented. As a sub-block of a direct conversion receiver, th e analog baseband signal chain consists of a pre-filter AGC, a channelselect filter and a pos t-filter AGC block. Design specification for the VGA gain range is obtained by estimating the receiver gain

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103 distribution. Analysis of a conventional closed loop AGC was given to introduce AGC fundamentals. In Chapter 3, the statistics of OFDM amplitude estimation were studied through simulation. OFDM signal generators w ith peak, average, RMS and pseudo-RMS detectors were simulated based on the 802.11a standard using Matlab/Simulink. Given random input OFDM-QAM signals, statistical si mulations show that a peak detector can degrade the accuracy of amplitude estimati on in OFDM analog baseband processor, leading to a high standard deviation in es timated amplitude. The RMS detector shows the least error variance, and thus the most accuracy among those detectors. However, a simple pseudo-RMS detector could also be used, because there is no big difference in standard deviation values between an RM S detector and pseudo-RMS detectors. In Chapter 4, a cascade of 3rdand 4th-order elliptic lowpass Gm-C filters for the baseband processor for a 5-GHz WLAN receiver was designed. Various techniques such as transconductors with unit Gm cells, intern al node amplitude scaling, and parasiticcapacitance compensation were implemente d to reduce mismatch, processand temperature-variation effects. Also, a s econd version of the filter was designed that avoids floating capacitors. The technique to avoid floating capacitors improved linearity by better internal node amplitude scaling, at the expense of increased complexity. Both versions of the filter circuits, designed in TSMC 0.25 m CMOS technology, were verified by Cadence Spectre. In Chapter 5, some issues on AGC with OFDM signal were discussed and a new analog baseband AGC algorithm for 802.11a WLAN receiver was proposed. As shown in Chapter 3, RMS detectors are recommended for OFDM amplitude estimation. Due to

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104 the stability condition that the system’s time constant be much longer than the estimation time, a conventional closed-loop AGC cannot co nverge within the required settling-time constraints. The new AGC algorithm uses a three-step iterative open-loop gain control method (two coarse gain-settings using switc hes, followed by a final fine gain-setting using an open-loop computation circuit). Th e algorithm converges within seven shorttraining-symbol times, and holds the final gain throughout the whole p acket frame. This avoids the settling-time limits of a conventional closed-loop AGC. The VGA circuit was designed with a linea r transconductance cell using a modified differential FVF with a linear transconductance-setting re sistor, Gilbert cell-type differential pairs and linear load resistors. An inverse-gain block uses feedback to achieve an accurate gain-control function. A Differe ntial Difference Amplifier (DDA) is used for the amplifier in the inverse gain control loop so that th e feedback loop operates in differential mode. The differential folded cascode output stage of the DDA, combined with a common-mode feedback circuit with level-shifters, provides differential output control voltages. A simple RMS detector circuit was intr oduced based on the approximately squarelaw characteristics of long-channel NMOS tran sistors in strong i nversion. The analog computation block was implemented using tr anslinear circuits based on weak-inversion FETs, which reduced the power dissipation and complexity of the circuit. New circuits such as V-to-I converters with current atte nuation and I-to-V converters with current amplification were designed for use with the current-mode computation block. The switched gain-control block was im plemented using latched comparators, transmission-gates, and two reference volta ge generators. The initial voltage and

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105 threshold voltage generators pr ovide reference voltages that ar e preset by resistor banks. The resistor banks were made of serial a nd parallel connections of a root component resistor to reduce the effect of process variations and mismatch. The proposed AGC circuit including embedde d test points was fabricated, and its performance was verified by simulations and measurements using TSMC 0.18 m CMOS process models available through MO SIS. The AGC circuit adjusts the VGA gain so that the RMS voltage of the output si gnal matches the desired level with less than 1 dB error through the actual gain range of -4 to 28 dB. 6.2 Suggestions for Future Work Embedded test points with selectable sw itches as well as a supporting test board provided direct and versatile measurement op tions. However, most measurements were done using a single function block with a sine -wave generator due to limit in the test environment. For example, an accurate multiple-clock generator would be required for testing the whole signal chain of the AGC circuit including switched gain control. Furthermore, verification of AGC performan ce with short training symbols was limited to simulation due to lack of a short training symbol generator. Also, fabrication was limited to the post-fi lter AGC section. Fabrication of the whole signal chain including filter is left for future work. Furthermore, an unexpected issue is that among 20 packaged samples, only two showed the measurement results consistent with simulation data. This ma y have been due to some unexpected device parameter shifts, as discussed in Section 5. 4.3. To fix unexpected measurement problems and to get better measurement results, fabricating a revised version of the test IC is recommended.

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106 Design of additional function blocks such as automatic Gm tuning and DC-offset cancellation circuits are not covered in this research. Including these implementations would supplement the research work on the design of analog baseband processor for CMOS 5-GHz WLAN receiver. Other applicati ons of the research can be found in gaincontrol circuits and current-mode circuit areas. The inverse-gain loop with linear VGA and DDA can also be used in conventional cl osed-loop AGC circuit wi th peak detectors to achieve a linear-in-dB gain control with a constant settling time. The translinear circuit in the analog computation block can be modified for other computation functions. Combined with the translinea r circuit, the new V-to-I and I-to-V converters can easily implement current mode circuits in us ually voltage-mode design environments.

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107 APPENDIX SCHEMATIC OF TEST BOARD

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108

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109 LIST OF REFERENCES [Beh00] F. Behbahani, W. Tan, A. Karimi-Sanjaani, A. Roithmeier, and A. Abidi, “A Broad-Band Tunable CMOS Channel-Sel ect Filter for a Low-IF Wireless Receiver”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 4, pp.476-489, Apr. 2000 [Bol01] G. Bollati, S. Marchese, M. Demi cheli, and R. Castello, “An Eighth-Order CMOS Low-pass Filter with 30-120 MH z Tuning Range and Programmable Boost”, IEEE Journal of Solid-State Ci rcuits, Vol. 36, Issue 7, pp. 1056-1066, Jul. 2001 [Bur01] M. Burns and G. W. Roberts, “An Introduction to Mixed-Si gnal IC Test and Measurement”, Oxford, 2001 [Che01] H. Y. Cheung, K. S. Cheung, and J. Lau, “A Low Power Monolithic AGC with Automatic DC Offset Cancellati on for Direct Conversion Hybrid CDMA Transceiver used in Telemetering”, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems, Vol. 4 6-9, pp. 390 -393, May 2001 [Cho01] Y. S. Choi, P. J. Volts, and F. A. Cassara, “On Channel Estimation and Detection for Multicarrier Signals in Fast and Selective Rayleigh Fading Channels”, IEEE Transactions on Communications, Vol. 49, No. 8, pp. 13751387, Aug. 2001 [Cim85] L. J. Cimini, “Analysis and simu lation of a digital m obile channel using orthogonal frequency division multi plexing”, IEEE Transactions on Communications, Vol. 33, pp. 665-675, Jul. 1985 [Con01] J. Conover. (2001, Jan.) 802.11a : Making space for speed. Tech Web. [Online]. Available at: http://www.planetit.com/techcenters/docs/net-worksnetwork_systems/technology_feature/PIT20010111S0019 accessed Feb. 2003 [Fox99] R. M. Fox and M. Nagarajan, “M ultiple operating points in a CMOS logdomain filter”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 46, Issue 6, pp. 705-710, Jun. 1999 [Gop99] V. Gopinathan, M. Tarsia, and D. Choi, “Design Considerations and Implementation of a Programmable High-Frequency Continuous-Time Filter and Variable-Gain Amplifier in Subm icrometer CMOS”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, pp. 1968-1707, Dec. 1999

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110 [Gra97] P. R. Gray and R. G. Meyer, “A nalysis and Design of Analog Integrated Circuits”, 3rd Edition, John Wiley & Sons, 1997 [Han98] G. Han and E. Sanchez-Sinencio, “CMOS Transconductance Multipliers: A Tutorial”, IEEE Transactions on Circuits and Systems II, Vol. 45, No. 12, pp. 1550-1563, Dec. 1998 [Hua98] P. C. Huang, L. Y. Chiou, a nd C. K. Wang, “A 3.3-V CMOS Wideband Exponential Control Variable-Gain-Amp lifier”, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 285-288, 1998 [Hue80] L. P. Huelsman and P. E. Allen, “Introduction to the Theory and Design of Active Filters”, McGraw-Hill, 1980 [IEE99] Wireless LAN medium access co ntrol (MAC) and physical layer (PHY) specifications: High-speed physical la yer in the 5-GHz band, IEEE Std. 802.11a, Part11, Sep. 1999 [Joh97] D. A. Johns and K. Martin, “Analog Integrated Circuit Design”, John Wiley & Sons, 1997 [Kar92] J. E. Kardontchik, “Introduction to the Design of Tr ansconductor-Capacitor Filters”, Kluwer Academic Publishers, 1992 [Kho98] J. M. Khoury, “On the Design of Constant Settling Ti me AGC Circuits”, IEEE Transactions on Circuits and Systems II, Vol. 45, No. 3, pp. 283-294, Mar. 1998 [Lee02] T. H. Lee, H. Samavati, and H. R. Rategh, “5-GHz CMOS Wireless LANs”, IEEE Transactions on Microwave Theory and Techniques, Vol. 50, No. 1, pp. 268-280, Jan. 2002 [Lin99] C. H. Lin, T. Pimenta, and M. Ismail, “Universal Exponential Function Implementation using Highly-Linear CMOS V-I Converters for dB-Linear (AGC) Applications”, Proceedings 1 998 Midwest Symposium on Circuits and Systems, pp. 360-363, 1999 [Lop01] A. J. Lopez-Martin and A. Carl osena, “A current-mode CMOS RMS-DC converter for very low-voltage appli cations”, The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001. ICECS 2001, Vol. 1, pp. 425-428, Sep. 2001 [Meh03] S. Mehta, M. Zargari, S. Jen, B. Kaczynski, M. Mack, S. Mendis, K. Onodera, H. Samavati, W. Si, K. Singh, M. Terrovi tis, D. Weber, and D. Su, “A CMOS Dual-band Tri-mode Chipset for IEEE 802.11a/b/g Wireless LAN”, 2003 IEEE Radio Frequency Integrated Circuits Symposium, pp. 427-430, 2003

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111 [Men97] C. Mensink, B. Nauta, and H. Wallinga, “A CMOS ‘Soft-Switched’ Transconductor and Its Application in Gain Control and Filters”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 989-998, Jul. 1997 [Mul99] J. Mulder, W. A. Serdijn, A. C. va n der Woerd, and A. H. M. van Roermund, “Dynamic Translinear and Log-Domain Circuits–Analysis and Synthesis”, Kluwer Academic Publishers, Boston, 1999 [Ock99] R. Ockey and M. Syrzycki, “Optim ization of a Latched Comparator for HighSpeed Analog-to-Digital Converters”, Proceedings of the 1999 IEEE Canadian Conference on Electrical a nd Computer Engineering, May 9-12, 1999 [Och01] H. Ochiai and H. Imai, “On the Distribution of the Peak-to-Average Power Ratio in OFDM Signals”, IEEE Trans actions on Communications, Vol. 49, No. 2, pp. 282-289, Feb. 2001 [Par99] A. Parssinen, J. Jussila, J. Ryynanen, L. Sumanen, and K. I. A. Halonen, “A 2GHz wide-band direct conversion recei ver for WCDMA applications”, IEEE Journal of Solid-State Circuits, Vo l. 34, Issue 12, pp. 1893-1903, Dec. 1999 [Raz94] B. Razavi, “RF Microe lectronics”, Prentice-Hall, 1994 [Raz01] B. Razavi, “A 5.2-GHz CMOS r eceiver with 62-dB image rejection”, IEEE Journal of Solid-State Circuits, Vo l. 36, Issue 5, pp. 810-815, May 2001 [Rij96] J. J. F. Rijns, “CMOS Low-Di stortion High-Freque ncy Variable-Gain Amplifier”, IEEE J. Solid-State Circu its, Vol. 31, No. 7, pp. 1029-1034, Jul. 1996 [Sai02] C. Saint and J. Saint, “IC Ma sk Design–Essential Layout Techniques”, Mc Graw Hill, New York, 2002 [San00] E. Sanchez-Sinencio and J. Silva-Martinez, “CMOS Transconductance Amplifiers, Architectures and Active Filte rs: a Tutorial”, IEE Proceedings of Circuits Devices Syst., Vol. 147, No. 1, pp. 3-12, Feb. 2000 [Str01] P. M. Stroet, R. Mohindra, S. Hahn, A. Schuur, and E. Riou, “A zero-IF single-chip transceiver for up to 22 Mb/s QPSK 802.11b wireless LAN”, ISSCC 2001. IEEE Int. Solid-State Circui ts Conference Digest of Technical Papers, pp. 204 -205, 447, 2001 [Tac93] E. J. Tacconi and C. F. Christians en, “A wide range and high speed automatic gain control”, Proceedings of the Partic le Accelerator Conference, Vol. 3, pp. 2139-2141, 1993

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112 [Tad98] S. Tadjpour, F. Behbahani, and A. A. Abidi, “A CMOS Variable Gain Amplifier for a Wideband Wireless Receiver”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 86-89, 1998 [Wak90] T. Wakimoto and Y. Akazawa, “A Low-Power Wide-Band Amplifier Using a New Parasitic Capacitance Compensation Technique”, IEEE Journal of SolidState Circuits, Vol. 25, No. 1, pp. 200-206, Feb. 1990 [Yam97] T. Yamawaki, M. Kokubo, K. Irie, H. Matsui, K. Hori, T. Endou, H. Hagisawa, T. Furuya, Y. Shimizu, M. Ka tagishi, and J. R. Hildersley, “A 2.7V GSM RF transceiver IC”, IEEE Journa l of Solid-State Circuits, Vol. 32, Issue 12, pp. 2089-2096, Dec. 1997 [Yod03] U. Yodprasit and C. C. Enz, “A 1.5-V 75-dB Dynamic Range Third-Order Gm-C Filter Integrated in a 0.18m Standard Digital CMOS Process”, IEEE Journal of Solid-State Circuits, Vo l. 38, No. 7, pp. 1189-1197, Jul. 2003 [Zar02] M. Zargari, D. K. Su, C. P. Yue, S. Rabii, D. Weber, B. J. Kaczynski, S. S. Mehta, K. Singh, S. Mendis, and B. A. Wooley, “A 5-GHz CMOS Transceiver for IEEE 802.11a Wireless L AN System”, IEEE Journal of SolidState Circuits, Vol. 37, No. 12, pp. 1688-1694, Dec. 2002 [Zha01] Z. Zhang, Z. Chen, L. Tsui, a nd J. Lau, “A 930MHz CMOS DC-Offset-Free Direct-Conversion 4-FSK Receiver”, I SSCC 2001. IEEE Int. Solid-State Circuits Conference, pp. 290-291, 456, 2001

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113 BIOGRAPHICAL SKETCH Okjune Jeon was born in Busan, Korea, in 1964. He received the B.S. degree in electronics engineering from Korea Military Academy, Seoul, Korea, in 1986, and the M.S. degree in electrical engi neering from Case Western Re serve University, Cleveland, Ohio, in 1990. He served in the Republic of Korea Army as a signal officer for 14 years, working on the operation of PCM cable, VHF, M/W a nd satellite communication systems. Through his military career as a company comma nder and as a staff officer, he gained his experience in group leadership and project management. From 1997 to 2000, he was a faculty member of the Department of Electronics Engineering, Korea Military Academy. Si nce 2001, he has been working on his Ph.D. degree in the analog IC design gr oup at the University of Flor ida as a graduate research assistant. During the summer of 2002, he was employe d at Intersil Corporation, Palm Bay, Florida, where he worked on the design of analog filters for a CMOS 802.11a WLAN receiver as an internship design engineer. He received an Outstanding Student Designer Award from Analog Devices Incorporated in 2004. His research interests involve analog a nd mixed-signal circuit design including CMOS integrated circuits, continuous-time filters, and AGC circuits.


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Title: Analog Baseband Processor for CMOS 5-GHz WLAN Receiver
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Copyright Date: 2008

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ANALOG BASEBAND PROCESSOR
FOR CMOS 5-GHZ WLAN RECEIVER
















By

OKJUNE JEON


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


2005
















ACKNOWLEDGMENTS

I would like to express my deep appreciation to my supervisory committee chair

(Robert M. Fox) for his guidance and support. His insight into circuits and his patience

and encouragement made my study possible. I also thank committee members William R.

Eisenstadt, John G. Harris, and Oscar D. Crisalle for their helpful advice.

Special thanks go to Dr. Brent A. Myers at Conexant Systems Incorporated for

supporting my research project including two fabrications and giving me the summer

internship experience. His real-world comments throughout the research work and

advice as a committee member are greatly appreciated.

I thank my fellow graduate colleagues, Yus Ko, Choongeol Cho, Hyeopgoo Yeo,

Jangsup Yoon, Kooho Jung, Jongsik Ahn, Ming He, Tao Zhang, Qizhang Yin, Xueqing

Wang (Andy), Xiaoqing Zhou, and Su Deep. Also, I thank Dr. Hyungjong Ko, Dr.

Inchang Seo, Dr. Sanghoon Choi and Changjin Lee, who were former graduate students

in the Analog Integrated Circuit Laboratory.

My sincere thanks are given to my parents and parent-in-laws. I would like to offer

my greatest appreciation to my lovely wife Sanghyun and dear children Yerin and

Hohyun, who always stand by me with love and prayer. Finally, I would like to give

thanks and glory to the lord God of Ebenezer.




















TABLE OF CONTENTS


IM Le

ACKNOWLEDGMENT S .............. .................... ii


LIST OF TABLES ............ ...... ._._ ...............v....


LIST OF FIGURES .............. ....................vi


AB STRAC T ................ .............. xi


CHAPTER


1 INTRODUCTION ................. ...............1.......... ......


1.1 Motivation............... ...............
1.2 Research Goals .............. ...............2.....
1.3 Outline of the Dissertation. ................ ................. ......... ..............3


2 BACKGROUND ................. ...............5.......... ......


2. 1 IEEE 802.11la Standard. ............... ... ...__ ...............5.
2.2 System Specifications for WLAN Receiver ................... .......... ................. .7
2.3 Receiver Architecture and Analog Baseband Signal Chain .............. ..................9
2.4 AGC Fundamentals .............. ...............12....


3 OFDM SIGNAL AMPLITUDE ESTIMATION ................. ......... ................18


3.1 OFDM Signal Characteristics............... ............1
3.2 OFDM Signal Generation................... .... .......... .. .......2
3.3 Analog OFDM Signal Amplitude Estimation with Statistical Simulation ...........22
3.4 Accuracy Boundary for Received OFDM Short Training Symbols.....................26

4 SEVENTH ORDER ELLIPTIC LOW-PASS GM-C FILTER ................ ...............28


4. 1 Introducti on ................. ...............28........... ...
4.1.1 Specifications .............. ...............28....
4. 1.2 Filter Topology ................. ...............30...............












4.2 Filter D esign I ................... ......... ..... ..... ...............32..
4.2.1 Gm-C Filter with Amplitude Scaling .............. ...............32....
4.2.2 Gm Cell Circuit Design ............ ......_ ...._ ..........3
4.2.3 Dealing with Parasitic Capacitance ......____ ........ ............_....3
4.3 Filter Design II............... ... .. ..............3
4.3.1 Avoiding Floating Capacitor .....__.....___ ..........._ ..........3
4.3.2 Parasitic Capacitance Compensation. ......____ ........__ ...............40
4.4 Simulation Results .............. ......_ ...............42..
4.4.1 AC Response and Tuning Range............... ...............42.
4.4.2 Transient Response, Noise and Linearity ......____ ..... ...__ ..............43

5 AUTOMATIC GAIN CONTROL .............. ...............48....


5 .1 Introducti on ................. ...............48........... ...
5.2 AGC Al gorithm .............. ...............50....
5.3 Circuit Design ................. ............ ...............55.....
5.3.1 Variable Gain Amplifier............... ...............5
5.3.2 Differential Difference Amplifier ................. ...............61........... ..
5.3.3 RM S Detector ................. ...............62...............
5.3.4 Computation Block............... ...............64.
5.3.5 Switched Gain Control 2 .............. ...............69....
5.4 IC Implementation and Measurement .............. ..... ...............73.
5.4. 1 IC Implementation with Embedded Test Points ................. ................ ...73
5.4.2 Simulation Results ................. ...............77................
5.4.3 IC Measurement and Analysis............... ...............86

6 SUMMARY AND FUTURE WORK .............. ...............102....


6. 1 Summary .................. .............. ...............102 .....
6.2 Suggestions for Future Work............... ...............105.



APPENDIX SCHEMATIC OF TEST BOARD ................ .............................107


LI ST OF REFERENCE S ................. ...............109................


BIOGRAPHICAL SKETCH ................. ...............113......... ......

















LIST OF TABLES


Table pg

2-1. Receiver performance requirements ................. ...............8...............

3-1. Statistical simulation result for 5000 symbols (Max Peak = 0.607)..........................24

4-1. Spreadsheet to compute parasitic capacitance, number of dummy cells, and main
capacitor value at each node .........._.__......._.._ ...............39.....

4-2. Summary of characteristics of the two filters ........ ................. .............. ....47

5-1. Summary of the simulation and measurement results.........._.._.. ........__. ........101


















LIST OF FIGURES


figure pg

2-1. Frequency band allocation in the IEEE 802.11la standard............._ ........._ ......5

2-2. PLCP Protocol Data Unit frame format .............. ...............7.....

2-3. Specifications of the minimum sensitivity signal channel with adj acent and
alternate adj acent channels for 6 and 54Mbps data rates ................ ............... .....9

2-4. Architecture for the 5 GHz WLAN receiver. ............. ...............10.....

2-5. Baseband signal chain block diagram ................. ...............11........... ..

2-6. Receiver gain distribution plots for 6Mbps data rate .............. .....................1

2-7. Receiver gain distribution plots for 54Mbps data rate .............. .....................1

2-8. AGC structure with (a) nonlinear feedback loop and (b) linearized loop
representation .............. ...............15....

3-1. A typical analog OFDM signal in the time domain............... ...............18.

3-2. OFDM modulator ................. ...............20................

3-3. Short training symbols: (a) I channel one symbol (0.8Cls) and 7 symbols, and (b)
Q channel one symbol (0.8Cls) and 7 symbols. ............. ...............21.....

3-4. Data symbol generation in the discrete time domain .............. .....................2

3-5. Data symbol generation in continuous time domain .............. ....................2

3-6. Data distribution plots for 6 detectors .............. ...............25....

3-7. Standard deviation plot for 6 detectors ................. ...............25........... ..

3-8. OFDM short training symbol generation with channel effect ................. ................27

4-1. Channel attenuation requirements for the baseband low-pass filter ................... ........29

4-2. Frequency response (magnitude and group delay) for (a) 6th order elliptic, (b) 9th
order Chebyshev II, (c) 3rd order elliptic, and (d) 4th order elliptic filters ...............31










4-3. LC prototype fi1ters for (a) 3rd order and (b) 4th order elliptic low-pass fi1ters..........31

4-4. 3rd order Gm-C Eilter............... ...............32.

4-5. Internal node voltage plot of the 3rd order Gm-C Eilter: (a) before scaling and (b)
after scaling .............. ...............33....

4-6. 3rd order Gm-C Eilter after voltage scaling for internal nodes .............. ..................33

4-7. Schematics of (a) unit Gm cell and (b) FC with CMFB unit .............. ...................35

4-8. DC transfer characteristics of a unit Gm cell: (a) V-I plot, (b) Gm plot ................... .37

4-9. Fully differential 3rd order Gm-C filter. ......___ ... ....._ ....__ ..........3

4-10. Avoiding floating capacitor: (a) Gm-C filter with floating capacitor, (b)
substitution of floating capacitor at node V1, (c) additional circuit for current
source to node V 1 .............. ...............40....

4-11. 3rd order Gm-C filter avoiding floating capacitor ................. ....___ ...............41

4-12. Internal node voltage plot of the 3rd order Gm-C filter avoiding floating
capacitor ........... ..... ._ ...............41...

4-13. Internal node voltage plot of the 3rd order Gm-C filter avoiding floating
capacitor ........... ..... ._ ...............42...

4-14. AC response simulation result for Filter 2............... ...............43...

4-15. AC response simulation result for Filter 2 with tuning .............. ....................4

4-16. Transient response of the Filter 2 at (a) 8.3 MHz and (b) 12 MHz ........................44

4-17. Noise in dB vs. frequency plot .............. ...............45....

4-18. Linearity of 1 % THD vs. input signal voltage for (a) Filter 1 and (b) Filter 2 in
nominal case ........._.__...... ..__ ...............46....

5-1. Conventional AGC loop composed of VGA, Peak Detector and Loop Filter ...........49

5-2. Architecture of the proposed AGC algorithm; (a) block diagram and (b) time line ..50

5-3. Switched Gain Control 1 of the AGC algorithm ................................... 5

5-4. Switched Gain Control 2 of the AGC algorithm ................................... 5

5-5. AGC with One-step Correction: the fine gain-setting step............._.._ ..........._..__...53

5-6. Schematic of the proposed VGA ................. ...............56...............










5-7. Schematic of the replica bias circuit for VGA ................. .............................60

5-8. Simulation result for finding operating point in the replica bias circuit. The result
verifies that the bias circuit (for AV = 0.6 V) can operate only at the single
operating point of VA = 1.26 V and VB = 0.66 V. ................ ......... ...............60

5-9. Schematic of the proposed Differential Difference Amplifier ................. ................62

5-10. Schematic of the proposed RMS detector ................. ............ ........ .........64

5-1 1. DC simulation results of the RMS detector with VCM = 0.48 and vin = -0.25 ~
0.25 V: (a) currents II,2 after squarer and (b) currents 13,4 after rectifier..................64

5-12. V-to-I and I-to-V converters in (a) differential V to single-ended I, (b) single-
ended V-to-I, and (c) single-ended I to differential V modes .............. .................66

5-13. Schematic of the proposed analog computation block. The arrows indicate the
VGS S that form the translinear loop ................. ...............68..............

5-14. Switched gain control block implementation using latched comparators and
transmission gates .............. ...............70....

5-15. DC simulation result of the single-ended V-to-I and I-to-differential V
converters (single-ended Vet versus differential Vo> cl)............... .....................71

5-16. Reference voltage generator VINIT has six taps for preset voltages and is
implemented as serial and parallel connections of a root component resistor .........72

5-17. Reference voltage generator VTH prOVides threshold voltages (V-20dBm, V-22dBm
and V-30dBm) either for short training symbol signal or for sine wave signal...........73

5-18. Proposed AGC circuitry with 7 test points ........._.._ ...... .___ .. ......_. .....7

5-19. Output voltage buffer. ............_. ...._... ...............76..

5-20. Test switches; (a) voltage switch, and (b) current switch............... .................7

5-21. DC gain control simulation for the VGA with inverse gain loop ................... ..........79

5-22. DC simulation for Vin versus Vout of the VGA at (a) -4 dB gain and (b) 16 dB
gain ................. ...............79.................

5-23. AC response of the VGA; (a) gain and (b) phase ........................... ...............80

5-24. VGA input and output noise versus gain ................. ...............81..............

5-25. Linearity of the 2-stage VGA in THD (%) versus input signal voltage plots at (a)
-8 dB, (b) 0 dB and (c) 32 dB gain settings ................. ...............81...........










5-26. Input versus output characteristic of RMS detector; (a) for sine wave signal and
(b) for short training symbol .............. ...............82....

5-27. Characteristic of V-to-I converter; (a) input versus output linearity and (b) step
response ................. ...............82.................

5-28. Input versus output characteristic of I-to-V converter ................. ............. .......83

5-29. DC simulation results of the computation block for sine wave signal with the
switched gain of (a) -3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB ............... .... ...........84

5-30. DC simulation results of the computation block for short training symbol signal
with the switched gain of (a) -3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB ...............85

5-3 1. Transient simulation result (step response) of the computation block ........._.._........85

5-32. Transient simulation results of the AGC circuit for sine wave signal with Einal
gain of (a) -3 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB ................. .................8

5-33. Transient simulation results of the AGC circuit for sine wave signal with Einal
gain of (a) 15 dB, (b) 20 dB, (c) 23 dB and (d) 28 dB .............. ....................8

5-34. Transient simulation results of the AGC circuit for short training symbol signal
with Einal gain of (a) -3 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB............... .................89

5-3 5. Transient simulation results of the AGC circuit for short training symbol signal
with Einal gain of (a) 15 dB, (b) 20 dB, (c) 23 dB and (d) 28 dB.............................90

5-36. Full chip layout floor plan of the AGC circuit including ESD bonding pads and
decoupling capacitor between positive supply and ground............... .................9

5-37. Die photo of the fabricated AGC circuit ........._._.......... .......__........9

5-3 8. Test board design for the 40-pin AGC circuit package..........._._... ......._._.......93

5-39. Test board with a packaged AGC sample plugged in .............. ....................9

5-40. Bias circuit with external resistor connection: (a) can cause oscillation and (b)
can Eix the problem............... ...............94

5-41. Measurement results on device characteristics with various embedded test point
selections: (a) diode-connected NMOS in RMS detector (W/L=5/10 Cpm), (b)
diode-connected NMOS in cascode current mirror (W/L=3/3 Cpm), (c) threshold
voltage extraction (diode-connected NMOS), and (d) measurement plot on bias
current versus external resistor............... ...............95

5-42. Measurement of on-chip resistor variation: (a) resistors between input nodes and
(b) measurement results for 20 samples ................. ...............96...............










5-43. Gain control curve for the 2-stage VGA ................. ................. ..............97

5-44. 2-stage VGA gain with supply voltage variation .............. ...............97....

5-45. Stability of VGA gain with (a) bias current and (b) temperature variations ............98

5-46. 2-stage VGA characteristic at 12 dB gain: (a) input-output linearity, (b) SFDR.....99

5-47. Frequency response of the 2-stage VGA: (a) measurement result and (b)
simul ation result ................. ...............99.......... .....

5-48. Measurement result for input-output characteristic of the RMS detector ..............100

5-49. Measurement result for input-output characteristic of the V-to-I converter ..........100

5-50. Measurement result for input-output characteristic of the current mode
computation block .........__._..... ..__. ...............101....
















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

ANALOG BASEBAND PROCESSOR
FOR CMOS 5-GHZ WLAN RECEIVER

By

Okjune Jeon

December 2005

Chair: Robert M. Fox
Major Department: Electrical and Computer Engineering

This dissertation discusses the design of an analog baseband processor including

channel-select filtering with automatic gain control (AGC) for a 5-GHz CMOS WLAN

receiver. Basic concepts and specifications of the IEEE 802. 11a standard are reviewed.

Coded orthogonal frequency division multiplexing (OFDM), employed in this standard

for high data rate capability in multipath environments, degrades signal detection in the

receiver due to the high peak-to-average power ratio (PAPR). Statistical simulation

shows that RMS detection has the least error variance among several algorithms.

Channel-select filters of the analog baseband processor are implemented as 3rd and

4th order cascaded elliptic lowpass Gm-C filters. The set of filters have been designed

and fabricated in a 0.25 Clm CMOS process to meet all the specifications under expected

process variations.

The AGC part of the analog baseband processor has three variable gain amplifier

(VGA) stages. One of them is placed before and the rest after the channel-select filter. A









new gain-control algorithm for the OFDM baseband signal is proposed based on analysis

of conventional AGC loops. The new AGC algorithm uses switched coarse gain-setting

steps followed by an analog open-loop fine gain-setting step to set the final gain of the

VGAs. The AGC circuit is implemented in a 0. 18 Clm CMOS process using newly

designed circuits including linear VGAs, RMS detectors, and current-mode computation

circuitry. Experimental results show that the new AGC circuit adjusts OFDM short

training symbols to the desired level within settling-time requirements.















CHAPTER 1
INTTRODUCTION

1.1 Motivation

Wireless technologies are progressing rapidly, not only for voice, but also for data

communications. The growing mobile computing environment combined with the

demand for network connectivity has made wireless local area network (WLAN) popular.

Since the Institute of Electrical & Electronics Engineers (IEEE) ratified two WLAN

standards, 802.11la and 802. 11b, in 1999, many WLAN system architectures have been

developed to implement them. The IEEE 802.11lb standard specifies operation in the

2.4-GHz industrial-scientific-medical (ISM) band using direct-sequence spread-spectrum

(DSSS) technology. On the other hand, the IEEE 802.11la standard specifies operation in

the recently allocated 5-GHz unlicensed national information infrastructure (UNII) band

and uses the orthogonal frequency division multiplexing (OFDM) scheme instead of

DSSS. The IEEE 802. 11b standard, which supports data rates of up to 1 1Mbps, was

implemented before the IEEE 802. 11a standard, which supports data rates of up to

54Mbps, because the latter has more complicated and strict transceiver design

specifications than the former [ConO1, Lee02].

In addition to the right performance requirement, implementation of the 5-GHz

802.11la RF transceiver with low cost and high power efficiency is another challenge.

Along with several other silicon IC technologies, CMOS process technology can be a

solution. It provides a low-cost advantage due to its compatibility with high levels of

integration. Many CMOS processes also offer multiple metal layers, which enables the









use of integrated inductors and linear capacitors. However, characteristics of these

passive devices can be poor, due to process and temperature sensitivities. These

drawbacks can be resolved by automatic frequency and gain control (AFC and AGC)

algorithms [Zar02].

A typical 5-GHz WLAN receiver with direct conversion consists of RF front end,

analog and digital baseband blocks. In this type of architecture, most gain is in the

analog baseband except for the gain of a low noise amplifier (LNA) and mixer in the RF

front end. An analog baseband processor covers from the mixer' s output to the analog-

to-digital (A/D) converter's input, including baseband lowpass filters and AGC circuits.

Therefore, the main function of an analog baseband processor can be described as

channel-select filtering with sufficient gain. OFDM signals have a large peak-to-average

power ratio (PAPR), which requires wide dynamic range in the receiver [Och01]. In

order to deal with the wide dynamic range of the OFDM signal in the analog baseband

processor, we need to devise an efficient gain control algorithm.

1.2 Research Goals

The first goal of this research is to design a baseband lowpass filter which meets

the specifications of the IEEE 802. 11a standard. The CMOS Gm-C elliptic filter can be a

good candidate for its good on-chip integration properties. Also, by using a simple Gm

tuning scheme, the filter can adjust the transfer function to compensate for process and

temperature variations.

The second goal is to propose a gain-control algorithm to provide a constant level

of signal to the digital baseband processor. In order to achieve this goal, the effect of

PAPR characteristic of the OFDM data signal on the signal amplitude estimation should

be simulated statistically, by which one can determine the best detector type for the









OFDM signal. Based on analysis of conventional AGC loops, a new gain-control

technique can be obtained.

Finally, the proposed AGC algorithm is to be implemented in the circuit level

design. This research completes an analog baseband processor for a CMOS WLAN

receiver by making a whole signal chain with a filter and AGC circuits. To achieve

experimental results, the AGC design is to be fabricated in TSMC 0.18Clm CMOS

technology.

1.3 Outline of the Dissertation

This Ph.D. dissertation consists of six chapters. An overview of the research is

given in this current chapter (Chapter 1), including the motivation, research goals, and the

scope of this work. Chapter 2 reviews some background knowledge on this research.

Basic concepts and specifications of the IEEE 802. 11a standard are described, and the

overall system architecture and analog baseband signal chain blocks are presented.

Fundamentals of AGC operation are also reviewed in that chapter.

In Chapter 3, a statistical simulation of OFDM amplitude estimation is presented.

An OFDM signal generator (transmitter) is simulated, and signal detectors such as peak,

average, RMS and pseudo-RMS detectors are compared based on 802.11la standard using

Matlab/Simulink. The simulation results show that given random input OFDM-QAM

signals, the RMS detector has the least error variance among detectors.

Chapter 4 describes the design of 7th order elliptic lowpass filters for the baseband

processor for a 5-GHz WLAN receiver. The filter employs a technique to avoid floating

capacitors which allows setting peak values of all internal node voltages identical, thus

improving the maximum input signal level. The circuit's transconductors are










implemented as sets of "unit gm" cells, by which process-variation effects are reduced.

The Gm cells provide reasonable linearity and tunability using degeneration. A

spreadsheet to deal with the parasitic capacitance simplifies the design process.

Simulation results in a 0.25Clm CMOS process verify that the circuit meets all the

specifications under expected process variations.

Chapter 5 discusses the AGC part of the analog baseband processor. It has three

stages of variable gain amplifiers (VGAs). One of them is placed in front of the lowpass

filter to maximize the dynamic range of the signal. A new gain-control algorithm for the

OFDM baseband signal is proposed based on analysis of conventional AGC loops. After

the switched coarse gain-setting, a fine gain-setting scheme locks the final gain within the

specification time. Circuit design for the proposed algorithm is implemented in a 0.18Clm

CMOS process.

A summary of research work discussed in the dissertation and suggestions for the

future work are presented in Chapter 6.















CHAPTER 2
BACKGROUND

2.1 IEEE 802.11a Standard

The 802.11la standard specifies operation in the 5-GHz unlicensed national

information infrastructure (UNII) band with available signal bandwidth of 300 1VHz.

The allocated frequency band is split into two blocks (5.15 ~ 5.35 GHz and 5.725 ~

5.825 GHz) with three different power-level working domains as illustrated in Figure 2-1.

The bottom 100 1VHz domain has a maximum power output restriction of 40 mW, while

the next 100 1VHz allows up to 200 mW. The top 100 1VHz domain, intended for outdoor

operation, allows power output up to 800 mW.

800mW
200mW
40mW





5.15G 5.25G 1 5.35G 5.725G 5.825G

**52 carriers per channel, '
each 312.5KHz wide






201VHz


Figure 2-1. Frequency band allocation in the IEEE 802.11la standard









The 802.11la standard employs an encoding technology called coded orthogonal

frequency division multiplexing (OFDM). OFDM subdivides a high-speed data carrier

into several lower-speed subcarriers, which are then transmitted in parallel. There are

four 20 MHz-wide carriers in each 100 MHz domain. Each 20 MHz-wide carrier is

subdivided into 52 subchannels, each subchannel with 312.5 KHz bandwidth. 48 of these

52 subchannels are used for data, while the remaining 4 are used for error correction. By

using this OFDM scheme with low data rate subchannels, the signal channel is less

susceptible to multipath effects during propagation. However, OFDM signals have large

peak-to-average power ratio (PAPR) which requires a large power backoff in the

transmitter and a wide dynamic range in the receiver. For example, suppose each of the

52 subcarriers of the OFDM signal is a single-tone sine wave. Then the wave form of the

composite OFDM signal in the time domain will have large peaks and valleys. In the

worst case, if the peaks of all 52 sine waves coincide in time, the peak voltage will be

52 times larger than that of a single sine wave, which results in a peak-to-average ratio of

17 dB (-101og(52)). Although some signal clipping can be accepted with an insignificant

performance degrade in practice, this PAPR characteristic of the OFDM signal can

complicate transceiver design [Zar02].

The OFDM system uses binary / quadrature phase shift keying (BPSK/QPSK),

16-quadrature amplitude modulation (QAM) or 64-QAM for subcarrier modulation.

When BPSK is used, each subchannel carrier encodes data of 125 Kbps, resulting in a

6 Mbps data rate. The data rate doubles to 12 Mbps, 250 Kbps per subchannel with

QPSK. Using 16-QAM, the rate increases further to 24 Mbps. It is mandatory for

802.11la systems to provide these data rates. The standard also allows data-rate extension










beyond 24 Mbps. A data rate of up to 54 Mbps in a 20 MHz channel can be achieved by

using 64-QAM.

The 802. 11 wireless LAN data service is provided by sending and receiving packet

frames denoted as PLCP (physical layer convergence procedure) Protocol Data Unit

frames. The packet frame format includes PLCP preamble, SIGNAL (header of the

frame) and DATA parts as shown in Figure 2-2. The PLCP preamble is composed of

12 symbols: 10 repetitions of a "short training sequence" (used for AGC convergence,

diversity selection, timing acquisition, and coarse frequency acquisition in the receiver)

and two repetitions of a "long training sequence" (used for channel estimation and Eine

frequency acquisition in the receiver). The SIGNAL part constitutes a single BPSK

coded OFDM symbol which includes the RATE and LENGTH Hields required for

decoding the DATA part of the packet. The DATA part, which includes the service data

units, may consist of multiple OFDM symbols. The design considerations for an analog

baseband processor deal with short training symbols of the preamble in this OFDM

packet frame format.

BPSK coded OFDM Coded OFDM

PLCP Preamble SIGNAL DATA
12 Symbols One OFDM Symbol Variable Number of OFDM Symbols

10 short training symbols RATE and LENGTH
+ 2 long training symbols for DATA


Figure 2-2. PLCP Protocol Data Unit frame format


2.2 System Specifications for WLAN Receiver

The receiver specifications for the 5 GHz WLAN system are described as receiver

performance requirements in the 802.11la standard. Table 2-1 specifies the receiver










performance requirements with data rates of 6 Mbps through 54 Mbps. The minimum

sensitivity is -82 dBm for 6 Mbps data rate and -65 dBm for 54 Mbps data rate. For the

baseband signal channel at DC, the adj acent channel (at 20 MHz) rej section should be no

less than 16 dB (6 Mbps data rate) or -1 dB (54 Mbps data rate). Similarly, alternate

adj acent channel (at 40 MHz) rej section should be no less than 32 dB (6 Mbps data rate)

or 15 dB (54 Mbps data rate). The relative constellation RMS error which is known as

SIR (Signal-to-Interference Ratio) should not exceed -5 dB (6 Mbps data rate) or -25 dB

(54 Mbps data rate). Figure 2-3 shows specifications of the minimum sensitivity signal

channel with adj acent and alternate adj acent channels for 6 and 54 Mbps data rates.

Table 2-1. Receiver pefrmance reuirements
Alternate
Mimimum Adj acent Relative
Data rate adjcen
~Mbp)sensitivity channel ~ a~~tconstellation
(Mbs)(dBm) rej section (dB) richaonnel error (dB)
6 -82 16 32 -5
9 -81 15 31 -8
12 -79 13 29 -10
18 -77 11 27 -13
24 -74 8 24 -16
36 -70 4 20 -19
48 -66 0 16 -22
54 -65 -1 15 -25


From the specifications above, we can get the attenuation requirements for the

analog baseband channel selection filter. With the minimum data rate, 6 Mbps, channel

rejection should be 16/32 dB for adjacent/altemnate adjacent channels. Adding 6 dB for

SIR and 5 dB for margin, total attenuation should be 27/43 dB for adj acent/altemate

adjacent channels. Channel rejection with 54 Mbps data rate should be -1/15 dB for

adjacent/altemnate adjacent channels. This results in the total attenuation of 29/45 dB

with 25 dB of SIR and 5 dB of margin. If we increase the margin to 10 dB, the filter










attenuation requirements would be 34 dB for the adj acent channel and 50 dB for the

alternate adj acent channel.



n (6 Mbps) (54 Mbps)
-50dBm -50dBm

-66dm I-65dBm ~~~-66dBm dBtd
-82ddm \


8.3 11.7 31.7 f (MHz) 8.3 11.7 31.7 f (MHz)


Figure 2-3. Specifieations of the minimum sensitivity signal channel with adj acent and
alternate adj acent channels for 6 and 54Mbps data rates

2.3 Receiver Architecture and Analog Baseband Signal Chain

The two most common choices in receiver architecture are direct conversion and

low-IF dual conversion superheterodynee). Direct conversion is usually preferred in a

fully integrated design because it has a simple architecture. However, it has drawbacks

such as 1/f noise sensitivity and DC-offset problems. Dual conversion can reduce the

disadvantages of direct conversion, but it requires extra complexity [Raz0 1].

In this work, we assume that direct conversion is used for the receiver architecture.

As depicted in Figure 2-4, the receiver consists of a band-pass filter, low-noise amplifier

(LNA), I/Q channel mixers and low-pass filters with automatic gain control (AGC)

followed by analog-to-digital converters. The given blocks have Eixed gains; -3 dB for

band-pass filter, 20/0 dB selectablee) for LNA and 10 dB for mixers. As we know the

receiver specifications, we can get the gain budget distribution for the AGC with given

RF block gains.










MixerI
ANT C I J ,
AGC1> I~~ AGC2> A/D CI

LPF




BPF I Q

GC1 Icl AGC2 A/D Q
Mixero P

Figure 2-4. Architecture for the 5 GHz WLAN receiver

Input signal levels to the filter/AGC blocks can be computed by adding the gains of

the BPF, LNA and mixer to the sensitivity. The minimum input signal level for 6 Mb/s

data rate is: -82 dBm -3 dB + 20 dB + 10 dB = -55 dBm. For 54 Mb/s data rate, the

minimum input signal level is: -65 dBm -3 dB + 20 dB + 10 dB = -38 dBm. The

maximum input signal level of the adj acent and alternate adj acent channels at the AGC

inputs are -39 dBm and -23 dBm, respectively.

We assume that the input resistance of the A/D converter is 1 KGZ and that its input

signal level should be 1 V,, in single ended mode. In differential mode, 1 V,, equals to

0.5 V,, (0.25 V,) and to 0.178 Vrms for a sine wave. This corresponds to 0.032 mW in

1 kGZ of input resistance, or -15 dBm. For OFDM data signals, however, the ratio

between the peak and the RMS voltage varies due to the randomness of data and the

effects of the channel. For OFDM short training symbols, which have fixed amplitudes

specified in the 802. 11a standard, the RMS voltage of a short training symbol with

0.25 V, is 0. 105 Vrms. Its power level is computed as 0. 1052 / 1K = 0.011 mW, or

-20 dBm. In practice, the effects of a random channel can change this relationship.








11 ________

|DC offset canceller
HPF aj 150 kHz Channel selection filter -:------
ja 8.3 MHz


I VGA 1 ~ CVGA23A/




Gm|
|RF AGC 1 tuning | AGC 2 DSP

I II



Q~ VGA 1 3 VGA 2, A/D |



|DC offset canceller
Figure 2-5. Baseband signal chain block diagram

The proposed baseband signal chain is composed of three variable gain amplifier

(VGA) stages with two AGC blocks plus a 7th order Gm-C Eilter implemented as shown

in Figure 2-5. It also includes DC-offset canceling blocks such as capacitive coupling,

high-pass filter and/or feedback loop to remove dc offsets. One AGC block is placed

before and one after the channel-selection filter. Since the signals before and after the

channel-select filter are different, we applied separate AGC blocks to provide optimum

dynamic range (DR) for the fi1ter. The pre-filter AGC block with one selectable-gain

VGA stage enables the desired channel to have the maximum gain in the presence of

large adj acent channel signals by increasing the gain until the composite (desired channel

plus adj acent channels) signal reaches the input saturation point of the filter. This pre-

filter AGC provides an approximately constant-level composite signal to the channel-

selection filter, thus reducing the input-signal dynamic-range requirement of the filter.

The post-filter AGC with two VGA stages sets the gain so that the signal level of the









selected channel gets to the desired output level. If we had used a single post-filter AGC,

a low-noise filter with high DR and a high gain-range AGC would have been required in

the worst case of low composite input signal. On the other hand, we would have needed

an extra gain stage after the filter in the worst case of low desired signal level with high

adj acent-channel signal level, if we had used a single pre-filter AGC.

To ensure the operation of the baseband signal chain for all data rates with worst-

case levels of adj acent channels, efficient gain distribution is needed for the two AGC

blocks as illustrated in Figures 2-6 and 2-7. Given -16 dB as the input saturation point of

the filter, the gain of the pre-filter AGC should be 7 dB or more. The gain of the post-

filter AGC should be -4 dB (-16 to -20 dBm) for the maximum signal and 28 dB (-48 to

-20 dBm) for the minimum signal, which specifies the gain range of each VGA to -2 to

14 dB. The selectable gain of the pre-filter AGC can be set to 7 or 14 dB when all three

VGA stages are identical. Adding 4 dB of gain margin, the VGA should be designed to

have a gain range of -4 to 16 dB.

2.4 AGC Fundamentals

In this section, a conventional closed-loop AGC is analyzed mathematically based

on the AGC loop analysis given by [Kho98] to elucidate AGC function. For the

operation of the AGC loop, we assume that the AGC circuit only operates on signal

amplitude; hence the AGC input/output signals are represented only in terms of their

amplitudes. Another assumption is that the peak detector extracts the peak amplitude of

Vout(t) linearly and instantly (much faster than the basic operation of the loop) so that

peak voltage equals to the amplitude of Vout(t). This assumption enables omission of the

peak detector function model in the analysis.








13




10
(a) 20
-20 61
-so ---- --- --- ---- ---2 3



E -48 ,'





-so C-82

-90

-100
7/14dB -4~28dB


0/20dB 10dB
-3dB Mixer 3rd + 4th
AGC1 AGC2


-20 (b 25 -202



--- -47



E 66
8 -70 -- --------- _---~
-74 *

-82
90

100
Receiver Stages

S V ig CHMnmm ~Y-Aj CH (+20MYz) -Alt.L~ Adj. CH (+40Mz



Figure 2-6. Receiver gain distribution plots for 6 Mbps data rate. (a) Minimum signal 1.
(b) Minimum signal 2.


Figure 2-8 (a) shows a common structure of an AGC loop. The AGC loop consists


of a VGA, a peak detector, a comparator, and a loop filter. The VGA amplifies the input


signal Vin by the gain control signal V,. The output of the VGA is extracted by the peak


detector and then is compared with the reference voltage Vrer. The error signal is filtered


and fed back to the VGA to adjust the gain. The AGC loop is in general a nonlinear


























































-96


Receiver Stages
--Sig CH i--Adj. CH (+20MHz) a -AILt Adj. CH (440MHz)


14





-10

-20 -----

~30

-4 0 -- -- --- - -



S-50 C---.j--50 '---~~~~~~~~~~



-80

-90

-100

rLNA
0/20dB 10~d
-3dBMie


-10

-2 ---- b )
-30

-40





o-66


-80


-9oo


-23 .. 7 -6
-31


6 .2O
-23


-36


Figure 2-7. Receiver gain distribution plots for 54 Mbps data rate. (a) Minimum signal.
(b) Maximum signal.


system because the VGA operates like a mixer: Vout = Vin x f(V,). (2-1)


Thus, we need to linearize the loop to simplify a mathematical analysis of the AGC loop.


Figure 2-8 (b) shows a linearized structure of the AGC loop. By taking the natural


logarithm of Equation 2-1, we can change the multiplier expression of the VGA to an


adder expression: In(Vout) = In {Vin X f(Vc)} = In(Vin) + In(f(V,)). (2-2)



















(a) V Detector


Loop
FilterI V
Vref




VGA



in | n out
(b)
In ,
I L
I

I+ z




Figure 2-8. AGC structure with (a) nonlinear feedback loop and (b) linearized loop
representation

To linearize the feedback loop, two function blocks (the exponential block at the

VGA output and the logarithm block at the control voltage input of the VGA) must be

canceled. Hence, two shaded blocks (the logarithm block at the VGA output and the

exponential block at the control voltage input of the VGA) are added in Figure 2-8 (b).

We can write the control function to VGA as f(V,) = exp(k-Ve,), (2-3)

and rewrite Equation 2-2 as

In(Vot) = In(Vin) + In(exp(k-Ve,)) = In(Vin) + k-V,. (2-4)

Let In(Vin) = x and In(Vout) = y, then the Equation 2-4 is y = x + k-V,. (2-5)










The control function from the loop filter is expressed as Vc = 3, nVu)



and In(Vout) = y, so Vc = (V,,, y)dv (2-6)

Take derivative respect to time on Equations 2-5 and 2-6:

dy dx~ dV, dVe g, dy dx~ g,
+k, -ye _V,- y), .- +k- m(V,,- y) (2-7)
dt dt dt dt C dt dt C

And take the Laplace transformation to Equation (2-7):

sy = sx k-(gm/C)-y, (s + k-gm/C)-y = sx.
-. =H(s)= s
x s k g (2-8)


Equation 2-8 is an input-output transfer function of the linearized VGA with AGC loop.

The transfer function is a 1st order high-pass function and is stable since the pole is in the

left half of the s-plane. This means that the gain control voltage of the feedback loop is

input signal independent. AGC settling time is inverse proportional to the constant loop

bandwidth f, = k-(gm/C).

In many AGC systems, the logarithm amplifier in shaded block in Figure 2-8 (b)

can be omitted due to its complexity in realization. With this omission, the above

condition can still be met under certain small-signal approximations. The assumption is

that the AGC loop is operating with the condition that the output amplitude of VGA is

near its fully converged state, that is, Vout Vrer. In this case, the control voltage function


can be writen as Vc = Km ~(Vrr i- Vo,)dr, and since Vout = exp(y),


VC = (V,, -eY)dv (2-9)

Take the derivative respect to time on Equations 2-5 and 2-9:










dy dx~ dVe dVe g, dy dx~ g,
+k- (~ ,- e ), +k- '(ye -eY ). (2-10)
dt dt dt dt C dt dt C

Equation 2-10 is non-linear because of the exp(y) term. Let In(Vrer) = z;

then Vrer = exp(z). Under small-signal approximation of Vout Vrer,

we can get Vout Vrer 0, and In(Vout) In(Vrer) = y z 0.

So, by Taylor series expansion, we can write

e~~Y =e e=ee e (1+ y -z) when z<<1
(2-11)
.. e = e (1+ y z)

Combine Equations (2-10) and (2-11):

=y +L k, "'- F 1 ) = +k-"-f (1 +y -z))

(2-12)
.dy i=+kX- ( ,In(P er) -)
dt dt C

Take the Laplace transformation to Equation 2-12:

sy = sx k-(gm/C)-Vree-y, (s + k-gm/C-Vrer)-y = sx.
y s
S =H(s)=
x g,, (2-13)
s+k-


Equation 2-13 is the input-output transfer function of the linearized VGA with

AGC loop under small-signal approximation. The transfer function is a 1st order high-

pass function and is stable since the pole is in the left half of the s-plane. However, since

we assumed Vrer = Vout = Vin-f(V,), this system is fundamentally nonlinear and is input

signal-dependent. Loop bandwidth f, = k-(gm/C)-Vrer is not constant if the difference

between Vout and Vrer changes. Therefore, AGC settling time increases linearly with

respect to the difference (input step size).















CHAPTER 3
OFDM SIGNAL AMPLITUDE ESTIMATION

3.1 OFDM Signal Characteristics

OFDM is a multi-carrier transmission technique, which divides the available

spectrum into many carriers, each one being modulated by a low rate data stream. It is

similar to Frequency Division Multiple Access (FDMA) in that the multiple user access

is achieved by subdividing the available bandwidth into multiple channels, which are

then allocated to users. However, OFDM uses the spectrum much more efficiently by

spacing the channels much closer together. This is achieved by making all the carriers

orthogonal to one another, preventing interference between the closely spaced carriers. A

key drawback of OFDM is its high peak-to-average power ratio (PAPR), that is, its signal

in the time domain has noise-like amplitude with a very large dynamic-range [Och01].

Figure 3-1 shows a typical analog OFDM signal in the time domain.

















Figure 3-1. A typical analog OFDM signal in the time domain









OFDM has gained considerable attention with the rapid growth of digital

communication in recent years. It has been adopted for digital wireless broadcast and

network standards, including IEEE802.11la wireless LAN standard. The 802.11la

standard describes the specifications for 5 GHz wireless LAN transceivers using OFDM

[IEE99]. As discussed in Chapter 2, it offers support for a combination of other

modulation and coding alternatives such as phase shift keying (PSK) or quadrature

amplitude modulation (QAM) with convolution encoding to generate data rates of 6

through 54 Mbps.

A typical WLAN receiver consists of LNA, mixer, analog baseband processor and

DSP blocks. An analog baseband processor includes AGC and channel-select filter

blocks that deal with baseband signals in the time domain. The AGC sets the gain of

variable gain amplifiers with respect to the detected output signal strength, which keeps

the output signal level to the digital block constant. AGC systems use peak detectors to

detect the strength of the output signal assume that its peak amplitude is constant if the

signal strength does not change [Kho98]. However, peak detectors may not work

properly with non-sinusoidal signals, that is, OFDM signal with high PAPR. Although

RMS detectors have been widely used in non-sinusoidal signal amplitude estimation, no

specific accuracy comparison among different types of detectors has been reported so far.

In this chapter, an OFDM signal generator for the baseband frequency range is

designed based on the 802. 11a specifications to estimate amplitude of analog OFDM

signal in time domain using Matlab/Simulink. OFDM data symbols are simulated using

randomly generated 64-QAM sequences. Various detectors such as peak, average, and

RMS detectors are tested by using the statistical simulation method in order to find out










which has less variance for the OFDM amplitude estimate. Signal detectors will show

averages of detected symbol amplitudes and statistical variances from multiple

simulations.

3.2 OFDM Signal Generation

In an OFDM system, the data is split into a number of streams, which are

independently modulated on parallel closely-spaced carrier frequencies. An OFDM

symbol is a sum of subcarriers that are individually modulated by using binary phase shift

keying (BPSK), quadrature phase shift keying (QPSK), 16-QAM, or 64-QAM. Figure 3-

2 shows the basic OFDM signal generator with the data symbols d(n) = a(n) + jb(n). The

real and imaginary parts correspond to the in-phase and quadrature parts of the OFDM

signal. They have to be multiplied by a cosine and sine of the desired frequency to

produce the transmitted OFDM signal represented as [Cim85]:

N-1
D(t) = {~a(n) cos(mst)+ b(n) sin(mst)) } (3-1)
n=0




o> sin mot
cosmot
SerialI
d(n)=a(n)+jb(n) b(0 OFDM signal D(t)
to :MUX
Parallel
a(-1) sinwN~t
cos ;v~t

b(-1)


Figure 3-2. OFDM modulator









The IEEE 802.11la standard specifies the physical layer convergence procedure

(PLCP) which provides a framing format suitable for data exchange and information

management. The PLCP preamble consists of 10 repetitions of a 'short training symbol'

(10 x 0.8Cls), 2 guard intervals (2 x 0.8Cls), and 2 repetitions of a 'long training symbol'

(2 x 3.2Cls). Seven out of ten short training symbols are used to allow time for signal

detection, AGC convergence, and diversity selection. A short training symbol uses 12

subcarriers, which are modulated by the elements of the sequence S, given by:

S-26,26 = x {0,0,1+j,0,0,0,-1-j,0,0,0,1+j,0,0,0,-1-j,0,0,0,-1-j,0,0,0,1+j,0,0,0,0,r; C~C~ C~ C
0,0,0,-1-j,0,0,0,-1-j,0,0,0,1+j,0,0,0,1l+j,0,0,0,1l+j,0,0,0,1l+j,0,0}.

The multiplication factor of -\~normalizes the average power of the resulting OFDM

symbol, which utilizes 12 out of 52 subcarriers.







(a)







(b)

Figure 3-3. Short training symbols: (a) I channel one symbol (0.8Cls) and 7 symbols, and
(b) Q channel one symbol (0.8Cls) and 7 symbols

A short training symbol can be generated by adding 6 signal sources for each I and

Q channel using Simulink. The 12 subcarriers, 14(1.25MHz), 18(2.5MHz),

12(3.75MHz), 16 (5MHz), 20(6.25MHz), and 24(7.5MHz), are modulated by the










BPSK sequence as given above. The generated short training symbols (analog signal) for

I and Q channels are illustrated in Figure 3-3.

The 64-QAM OFDM data symbols are generated as follows: First, binary input

data is encoded, interleaved, and converted to QAM values. The 52 QAM values (48

data values and 4 pilot values) are then zero padded and modulated onto 64 subcarriers

by applying the Inverse Fast Fourier Transform (IFFT). The output is converted to a

serial symbol in the next stage. The end processing of the digital baseband block adds

cyclic extension and window functions. Figure 3-4 shows the block diagram for data

symbol generation in the discrete time domain.

The OFDM data symbol signal in the continuous-time domain can be generated for

I and Q channels by replacing the IFFT block in Figure 3-4 with a new block that

combines the QAM-modulated analog subcarriers as shown in Figure 3-5.




zeroat DC
+26 C Vrt Ct _blackmnan
RadmitGnerl IFF In O
R dear nterger r ~fr 6 SG Conoa alinon Carrie soublion Pade t ei l nd Sgd aeoo
Baebn an[H pnal uin S90E
-26 SC


Figure 3-4. Data symbol generation in the discrete time domain


3.3 Analog OFDM Signal Amplitude Estimation with Statistical Simulation

The IEEE 802.11la standard reserves seven short training symbols for signal

detection, AGC convergence and diversity selection. Since seven identical short training

symbols are transmitted through an assumed unchanging channel, all of the available

information about signal amplitude is available during each symbol duration. Thus, the

short training symbol duration (0.8 Cls) is the optimal amplitude-estimation time.











However, due to its high PAPR, detecting the OFDM signal within a time period as short


as 0.8Cls can lead to high variance in the estimate. Moreover, the received signal might


have multi-path fading channel effects, which cause inaccurate amplitude estimation.


Therefore, we can consider the variance of the estimated amplitude to compare the


accuracy of estimation algorithms. We assume that the detector with lower variance is


more accurate. In OFDM amplitude estimation, the accuracy of the estimate can be


evaluated by statistical simulation; that is, the smaller the standard deviation is, the better


the accuracy of the detector is.



Unit oelay1l


+26SC S1 M n Age subC1 rdut PhaseDelay

t[,) hUnitDelay
angle to id1
Smtch


Randomly int GAenera -

R ndear nterg~er u4 r~ Signdl Deleclar
Baseband

SC26






-26 SC


Figure 3-5. Data symbol generation in continuous time domain


In order to compare the variances of the algorithms, we simulate the signal strength


estimation using randomly generated data symbols. 64-QAM random data signals are


generated and modulated with subcarriers to make OFDM data symbols. Three typical

detectors such as peak (PK), average (AVR) and RMS (RMS) detectors are considered


for the accuracy analysis. Three pseudo-RMS (PRMS ., PRMS3 and PRMS4) detectors









are added to find out if they show variances significantly different from that of the exact

RMS detector. Six detectors are implemented as follows:


PK = max(S) AVR = Sd

1 ~Sd RS =,1 Isl d
RM~S = Sd RS = -S d
TT TT

PRM~S3 =3 Sd RSS4d


where S is the amplitude of the OFDM signal and T(=0.8Cls) is the estimation time

Table 3-1. Statistical simulation result for 5000 symbols (Max Peak = 0.607)
Detector PK AVR PRMS'' RMS PRMS3 PRMS4
Arithmetic
mean of 5000 0.318 0.118 0.129 0.140 0.160 0.176
results
Back-off(dB) 5.612 14.216 13.425 12.714 11.585 10.750

A total of 5000 random data symbols are simulated for statistical purposes. The

arithmetic means of the 5000 simulated outputs for each detector are shown in Table 3-1.

Back-off represents the ratio of the maximum peak value to the arithmetic mean value of

each detector. The simulation results show that the back-off value for the peak detector is

the smallest and that of the average detector is the largest, as expected. Back-off values

for RMS and pseudo-RMS detectors decrease slowly from the average detector to the

high-order estimation.

Data distribution plots and standard deviation for each detector are shown in

Figures 3-6 and 3-7, respectively. The standard deviation of the peak detector is almost

twice those of the others, which means that it is not good for estimating OFDM signal

strength. The RMS detector has the least standard deviation of all, but the differences

between RMS detector and pseudo-RMS detectors are small. Standard deviations of

pseudo-RMS detectors (PRMS1. and PRMS3) are only 4 to 6 % higher than that of the


















































Standard Deviation






-0.034074
iiiiiii .027"1 _0.2682 .0328550.36


peak verae p.MS(1.) RM(2) .RMS() p.MS(4


true RMS detector (RMS). The simulation results indicate that the RMS detector is the

best one for OFDM amplitude estimation. However, a simple pseudo-RMS detector

could also be used, because there is no big difference in standard deviation values

between an RMS and pseudo-RMS detectors.


Data Distribution Plots
(5000 symbols for each detector)


-* peak
-=-average
- p.RMS(1.5)
-c RMS(2)
-p.RMS(3)
-- p.RMS(4)


0.1 0.2


0.3 0.4 0.5 0.6 0.7


value


Figure 3-6. Data distribution plots for 6 detectors


Figure 3-7. Standard deviation plot for 6 detectors









3.4 Accuracy Boundary for Received OFDM Short Training Symbols

In practice, OFDM symbols are transmitted through a radio link that can be

modeled as randomly scrambling the phases and possibly changing the relative

amplitudes of the signal [Cho01]. When such a signal is received, the amplitude of the

estimated signal can be different from the transmitted one even if all transceiver blocks

are assumed ideal. By taking this multipath channel-effect into account, we can estimate

the error variance of the received OFDM signal. The RMS detector in the analog

baseband processor is used for AGC, which must be performed within the first 7 short

training symbol period. The accuracy of AGC is bounded by the error variance in the

RMS value of the received short training symbols. So we need to estimate the accuracy

boundary for the short training symbols to consider gain margin of the AGC.

Figure 3-8 shows how the OFDM short training symbol generation and channel

effect blocks were simulated in the discrete time domain. The short training symbols are

generated by using the sequence given in Section 3.2 in the OFDM data symbol

generation blocks. Multipath is implemented using Simulink library blocks. The

Multipath Rayleigh Fading Channel block multiplies the input signal with samples of a

Rayleigh distributed complex random process, while the additive white Gaussian noise

(AWGN) block adds noise.

From 100 simulations for short training symbol with channel effects, the average of

the estimated RMS amplitudes is 0.266, and its standard deviation is 0.1. These values

translate to the accuracy boundary of 5.5dB. This margin should be considered when

designing the AGC for an analog baseband processor in 802.11la WLAN receiver.






























Figure 3-8. OFDM short training symbol generation with channel effect















CHAPTER 4
SEVENTH ORDER ELLIPTIC LOW-PASS GM-C FILTER

4.1 Introduction

Channel-select filters for the analog baseband processor in a WLAN receiver may

be either off-chip passive filters or on-chip active filters. On-chip active filters are

preferred for high integration and low cost, in spite of drawbacks such as limited receiver

dynamic range, increased power consumption and chip area. Gm-C filters are well suited

to high frequency applications as integrated continuous-time active filters. In the Gm-C

filter, parasitic capacitances of Gm cells can be merged into the grounded capacitors, thus

minimizing their side effects [Kar92].

The channel-select filter must pass only the desired channel to the analog-to-digital

(A/D) converter, suppressing adj acent and all other channels. Specifications are given to

realize the filter. Elliptic filters are used to meet the given specifications and

implemented in a 0.25Clm CMOS technology. This chapter describes the design of a

CMOS fully differential 7th-order low-pass Gm-C filter for the baseband processor in

5 GHz WLAN receiver. The filter is implemented by cascading 3rd and 4th order elliptic

filters.

4.1.1 Specifications

Filter specifications were developed through discussions with the Inrtersll' wireless

group to be consistent with IEEE 802.11la standard for a 5-GHz WLAN transceiver. The

specifications of an active filter in a WLAN receiver usually include the following issues

[Beh00] .










* Frequency response: pass-band ripple, stop-band attenuation, selectivity and group
delay

* Input/output signal dynamic range, noise, linearity

* Power consumption or supply voltage with current drain

* Chip area and/or complexity

The structure of the receiver uses I and Q channels for the baseband processing.

The cutoff frequency of the low-pass filter can be set to half of the bandwidth. The

occupied channel bandwidth is 16.6 MHz within the allocated 20 MHz bandwidth and

there is a 3.4 MHz spacing between channels. Thus we can set the pass-band and stop-

band edge frequencies to 8.3 MHz and 11.7 MHz, respectively. Other specifications are

minimum stop-band attenuation against adjacent channel and alternative adjacent channel,

given as -34 dB @ 20 MHz and -49 dB @ 40 MHz, respectively. Figure 4-1 shows the

channel magnitude attenuation requirements for the filter. Pass-band ripple should be

less than 1dB. Settling time of the system, including AGC settling, should be within

5.6 Cls (7 repetitions of the short training symbol), which requires fast settling time of the

filter. In addition, less group delay spread would ease the signal processing of the OFDM

signals.












Figure 4-1. Channel attenuation requirements for the baseband low-pass filter









4.1.2 Filter Topology

In the light of the required stop-band attenuation and narrow transition-band, the

specifications demand a relatively high-order filter. Elliptic filters have high selectivity

(steep magnitude response), but require high-Q poles that tend to cause long settling

times, large group delay spread, and high sensitivity to element errors. Chebyshev II

(Inverse Chebyshev) filters have less group delay variation, but need higher order (9th

order) compared to elliptic type (6th order). Other filter types such as Bessel and

Butterworth filters would require very high filter orders to meet the selectivity

requirements.

Simulations indicated that a cascade of 3rd and 4th order elliptic lowpass sections

provided superior trade-offs among delay, settling time and complexity. We can reduce

the group delay variation of a high-order elliptic filter by cascading lower-order ones.

3rd- and 4th-order elliptic lowpass filters have 73 29 = 44 ns and 127 40 = 87 ns of

maximum group delay variation in the pass-band, respectively [Men97]. Group delay

variation of the cascaded filter is 44 + 87 = 13 1 ns, whereas that of the required 6th order

elliptic filter is 403 79 = 324 ns. The cascaded filter shows even better result in group

delay than the 9th order Chebyshev II filter which has 142ns of the maximum group delay

variation in the pass-band. Graphs of the magnitude and group delay responses for each

filter type are shown in Figure 4-2.

The Gm-C filters were designed based on LC passive filter prototypes, with

element values provided by a filter data book [Hue80] and by software (Filter solutions

v.8.0). Figure 4-3 illustrates prototype circuits of cascaded 3rd and 4th order low-pass

elliptic LC passive filters which meet the given specifications. Note that the input and

output impedances are assumed to be 5 kGZ.































1ande(dB) 8n





40n

""' "" "
20n

---------- ------ r p delR s c O


Magni ide (dB)
150n

120






30n

(froup delBY (sec) 0


10M 20M 30M 40M Freq (Hz)
(d)


9th Order Chebyshev II


6th Order Elliptic


540n


Ide (dB)
-------r-- -450-----











10M 20M 30M 40M
(a)


L


-120





0


-20


-40


-60


-80


Freq 0


10M 20M 30M
(b)

4th Order Elliptic


40M Freq (Hz)



180n


3rd Order Elliptic


0 10M 20M 30M 40M Freq (Hz) 0
(c)


.


-60


Figure 4-2. Frequency response (magnitude and group delay) for (a) 6th order elliptic, (b)
9th order Chebyshev II, (c) 3rd order elliptic, and (d) 4th order elliptic filters


73.88 uH


BB.11 uH


ooo ~2


ooo ~2


Figure 4-3. LC prototype filters for (a) 3rd order and (b) 4th order elliptic low-pass filters










4.2 Filter Design I

4.2.1 Gm-C Filter with Amplitude Scaling

The elliptic Gm-C filters are built from the LC prototype by replacing both resistors

and inductors with transconductors elements. The input/output resistance of 5 kGZ sets

the transconductance gm to 200 CIA/V. The floating inductors are implemented using

gyrator-C circuits with C = L-gml-gm2. In order to minimize mismatch, transconductors

are composed of "unit gm (gmu)" cells. This also makes it convenient for layout. All the

transconductors in the filter are to be an integer multiple of gmu. Transconductor of

200 CIA/V is represented by 4gmu with unit gm of 50 CIA/V. The transconductors

connected to the input will be doubled to remove the 6 dB loss from implementation of

equally terminated LC prototype. Figure 4-4 shows the implemented 3rd order Gm-C

filter.

c3 =1.55pF

V gmu~ V44gmu V

8gmu

+) 4gmu 4gmui 4gmui 4gmu

V ~CI =4.45pl CL =2.96pF LC2=4.45pF


Figure 4-4. 3rd order Gm-C filter

However, in this filter, the amplitude of the signal at internal nodes may be higher

than the filter input. These peak voltages can drive internal transconductors into

saturation, resulting in distortion of the output signal. This problem can be solved by

applying amplitude scaling to the filter. That is, all node impedances are scaled so as to

make their peak amplitudes remain near the input signal's level without changing the









transfer function of the fi1ter. The 3rd order Gm-C Eilter has 3 nodes (two internal nodes

and one output node). The second node n2 peaks at ~2.25 V in SPICE simulation, which

is over twice the input voltage (1 V). This peak voltage can be reduced by half without

changing the voltage at any other node of the fi1ter. We can achieve this by halving the

currents flowing into the capacitor' s node (4gmu -2gmu) and doubling the currents

emitting from the capacitor's node (4gmu -8gmu), simultaneously. The scaled internal

node voltage plot and resulting Gm-C Eilter are given in Figures 4-5 and 4-6, respectively.


&: agVF(/nt014") : mag(VF("/120/net14 5"')) .:mgV( tl4) : mag(VF('VI28etl45"))



1.48









(a) (b)

Figure 4-5. Internal node voltage plot of the 3rd order Gm-C filter: (a) before scaling and
(b) after scaling


C1=4.45pII CL =2.96p F IC2=4.45pF


Figure 4-6. 3rd order Gm-C Eilter after voltage scaling for internal nodes









4.2.2 Gm Cell Circuit Design

The basic building block of the Gm-C filter is the integrator, which consists of a

transconductor (Gm cell) and a capacitor. The characteristics of the filter such as

frequency response, linearity, DC gain and tuning range depend on the Gm circuit. Real

Gm circuits have a finite output impedance that modifies the transfer function of the

integrator, introducing a low frequency pole pl. This low frequency pole pl limits the dc

gain and varies the phase of the integrator, which may introduce distortions in the transfer

function of the Gm-C filters [SanOO]. One general approach to deal with the low

frequency pole is to use a folded cascode (FC) output stage. The folded cascode structure

increases the output impedance of the Gm circuit, which shifts the low frequency pole to

a much lower frequency, reducing effects on the filter' s transfer function. Since the filter

will operate in fully differential mode, we need to add common-mode feedback (CMFB)

to the folded cascade output stage to stabilize the common-mode output voltage. This

circuit senses any change of the common mode output voltage and pushes it back to the

reference point by controlling the bias current of the output stage through negative

feedback. So the transconductor has two elements: a Gm unit and a FC with CMFB unit.

The schematics of the Gm and FC with CMFB circuits are shown in Figure 4-7.

The Gm cell has a p-channel differential pair as input stage. This can move the parasitic

pole p2 to a higher frequency with smaller transistor dimensions in the output stage

compared to the n-channel input stage case. That is because the parasitic pole p2 is

mostly determined by the parasitic capacitance of an n-channel transistor in the FC stage.












































(b)

Figure 4-7. Schematics of (a) unit Gm cell and (b) FC with CMFB unit

The Gm cell uses source degeneration MOS resistors to improve linearity. One

more voltage-controlled degeneration transistor (M5) is added for tuning in parallel with

the degeneration pair (M3,4) Of the well-known four-transistor input stage. In the

degeneration scheme, the linearity is increased by reducing the transconductance of the

differential pair (gm;/2). The transconductance of the linearized Gm cell can be found










with small signal analysis. Vx- y 7for small input signals, which makes the degeneration

transistors M3,4 and Mg operate in the triode region. The degeneration resistance is

defined as R = R1 || Rz || Rg, by which we get the following equation for AC current i.

V, V. = R i (4-1)

We can also write


g,,.,-(F,, Vx) =i (4-2)

and


g,z(,, (P,,,F)= -i (4-3)

for the input transistors M1 and M2, TOSpectively, where go,l = gaze and F n, y,,, = y n.

From Equations 4-1 through 4-3 we get:

g,,, -(F, -R-i)= 2-i (4-4)


i = "" -V(4-5)
g,,, -R +2 ""

g,,, 1

:. G,, = Kn; 2 R Kn;1 ,7R(4-6)
g,,, R +2 g,,, 1 2
+-
2R

Equation 4-6 shows that the transconductance of the proposed Gm cell is the parallel sum

of the transconductances of the differential input stage and the degeneration transistors.

The unit Gm cell is designed and simulated to have 50 CIA/V of transconductance through

1 V,, input signal range with 3 V supply voltage. Figure 4-8 illustrates the linear range

of the DC transfer characteristics and transconductance.










Vin vs. Iout Vin vs. Gm
401rA I ~ 601rA---------------









-20pA 301rA



OV IV 2V 3V OV IV 2V 3V
(a) (b)

Figure 4-8. DC transfer characteristics of a unit Gm cell: (a) V-I plot, (b) Gm plot

4.2.3 Dealing with Parasitic Capacitance

The 3rd order filter in Figure 4-5 is redrawn in Figure 4-9 to show the fully

differential structure with Gm cells, FC units, and capacitors. In reality, active blocks

such as these Gm cells and FC units have parasitic capacitances at their input/output ports.

Hence, we need to compute all of the parasitic capacitances of the active blocks

connected to each main capacitor nodes, and modify the main capacitor value so that the

total capacitance is the desired value. Also, to minimize process and temperature

variations all nodes should have the same ratio of parasitic capacitance to main

capacitance. An independent block composed of a FC output stage combined with

CMFB is placed on capacitor node and used in common for all connected Gm cells. This

is much simpler than including these functions in every Gm cell. The C1VFB circuit in

Figure 4-7 uses two matched differential pairs for good linearity, and all nodes see low

impedances to minimize high-frequency phase errors. The inputs remain linear for large









differential signals up to near 1 V,,, which is consistent with the maximum input signal

swing of the transconductors.

In Figure 4-9, we can compute the number of FC units and Gm cells connected to

each node. We keep track of the parasitic capacitances at each node for the output of

each FC unit and the input of each Gm cell. The parasitic capacitances of each FC output

port (Cout Fc) and Gm input port (Cin Gm) are eStimated from simulations [Kar92]. The

parasitic capacitance at each node is calculated by the equation C, = (number of FC) -

Cout FC + (number of Gm) Cin Gm. Let Ct be the total capacitance of each node. For each

node, we set the ratio between 'main' and 'parasitic' capacitances as equal as possible to

minimize the effects of process-parameter variations. Let x be the largest value of C,/Ct

for all nodes (x = 0. 14 at node 5 of 4th order filter). The main capacitance to be placed at

each node is C = Ct (1-x). The difference of the capacitance (Cd = t Cp C) Should be

realized by parasitic capacitance to provide process-parameter tracking. Therefore, we

need to add dummy cells to all nodes with Cd except one. Finally, we can find the

number of dummy cells (dummy#) and the main capacitor value (Ccap) for each node.

A spreadsheet was developed to automate these calculations, as an example is shown in

Table 4-1.


Figure 4-9. Fully differential 3rd order Gm-C filter











Table 4-1. Spreadsheet to compute parasitic capacitance, number of dummy cells, and
main capacitor vt lue at each node
filter
odrnode FC# IGm C, Ct C Cd dummy dummy# dum~diff Ccap
3 FC1 4 6 5.69E-13 4.45E-12 3.82E-12 6.24E-14 1.16E+()( 1.()(E+()( 1.62E-()1 3.83E-12
3 FC2 1 16 3.33E-13 2.96E-12 2.54E-12 8.61E-14 1.6)E+()( 12.()(E+()()-3.96E-()1 2.51E-12
3 FC3 3 6 4.47E-13 4.45E-12 3.82E-12 1.85E-13 3.45E+()( 13.()(E+()()4.45E-()1 3.85E-12
4 FC1 4 12 6.48E-13
4 FC2 2 8 3.5()E-13 4.55E-12 3.9()E-12 2.94E-13 5.48E+()( 15.()(E+()()4.81E-()1 3.93E-12
4 FC3 3 6 4.47E-13 4.84E-12 4.15E-12 2.4()E-13 4.47E+()( 4.()(E+()()4.7)E-()1 4.18E-12
4 FC4 1 16 3.33E-13 3.44E-12 2.96E-12 1.55E-13 2.9()E+()()3.()(E+)( -1.()4E-()1 2.95E-12
4 FC5 3 6 4.47E-13 3.15E-12 2.7()E-12 ().()(E+()( ().()(E+()( ().()()0 10E+())(.)(E ( 2.7()E-12
FC#*CoutFe From Ct(-)C-- dC int. of remainder C +
Filter spec. p mdmdummy of Cd dmdifP*Cd
Gm#*Cm, m
Cout Fe 1.226E-13
1.3155E-
Cm am 1
5.3696E-
Cm dum 1
x 1.42E-()1


4.3 Filter Design II

4.3.1 Avoiding Floating Capacitor

The filter design in the previous section has embedded floating capacitors, which

restricts node-voltage scaling and thus limits the input dynamic range. Floating


capacitors may also present a problem in the design due to their inaccuracy of the

bottom-plate capacitance. Hence, in this section, we designed another version of the

filter which avoids floating capacitors. This new filter design replaces floating capacitors

with compatible circuit blocks and results in all scalable internal nodes. The improved


dynamic range is obtained at the expense of some added complexity.

Figure 4-10 describes the floating capacitor avoidance technique. The 3rd order

Gm-C filter in Figure 4-4 is repeated here as 4-10 (a), where the floating capacitor is

connected between node Vt and node V2. As shown in Figure 4-10 (b), the floating


capacitor to the node Vt can be replaced with a grounded capacitor C3 and a current

source of sC3 2 which flows into the node, because its current is sC3 1, 2z). The









current source of sC3V2 can be implemented in the following sequence; (i) duplicate all

current sources at V2 (ii) drive these currents into R, (iii) get the desired current through

scaled gm. This is illustrated in Figure 4-10 (c). The voltage of the duplicated node Vx2

is s(C2 C3)V2 gy2. Therefore, if we set the scaled gm as gxi = gy2 3/C 2 C3), then we

get the desired current i = gxi-Vx2z= SC3Vy2. By applying the above technique to both

nodes V1 and V2, the 3rd order Gm-C filter which avoids the floating capacitor is

implemented, as shown in Figure 4-11.

s(C3(1V1 c3
V1 V V5
+ II+ +






(a)

91 V 94 V V4 95' VX2 97 V2
VV I sC2 03)V2 I
V, IIs-C3-V s.C3-V1

g2 9X1 9X21
CI C7 s(C31 9 D2
(b) (c)

Figure 4-10. Avoiding floating capacitor: (a) Gm-C filter with floating capacitor, (b)
substitution of floating capacitor at node V1, (c) additional circuit for current
source to node V1

4.3.2 Parasitic Capacitance Compensation

All five internal nodes of the filter avoiding floating capacitors are scaled to

maximize the input dynamic range of the filter. The internal node voltage plot after

scaling is shown in Figure 4-12, where peak voltages of all five internal nodes are equal

to 1 V, which is the peak voltage of the input signal.




























































OHz 51VHz 101VHz 151VHz


Figure 4-12. Internal node voltage plot of the 3rd order Gm-C filter avoiding floating
capacitor


Although the new filter presents scalability for better dynamic range, the extra


circuits introduce two new nodes that are not connected to grounded capacitors. These


floating nodes, Vxt and Vx2, depicted in Figure 4-13 (a) can add extra poles or zeros to


the transfer function due to their parasitic capacitances. In order to solve this problem,


_I ~C ,,I CL



Figure 4-11. 3rd order Gm-C filter avoiding floating capacitor


Internal Node Voltages


-----C-----E-----L-----L-----
: : : :
----:-----
-----C-----~----~
-----C-----~-----~-


----C-----


I I I ----


vL
Iv










we can add a 'negative capacitor' to the floating nodes of the filter. The negative

capacitor circuit shown in Figure 4-13 (b) uses a cross-coupled differential structure to

compensate AC current due to the parasitic capacitance by setting Co = C,. This circuit is

applied to each floating node, by which the side effects from the parasitic capacitance are

cancelled out [Wak90].

V1 V2Vd


Vp-C IIVp

Cl+C3 ; 9X2/ 9YX1 2 03
V Cpr xi g2 9X a





Floating capacitor --Node a 'nd Node b
(a) (b)

Figure 4-13. Internal node voltage plot of the 3rd order Gm-C filter avoiding floating
capacitor

4.4 Simulation Results

4.4.1 AC Response and Tuning Range

The 3rd-4th order cascaded lowpass filter has been designed in two versions: namely,

Filter 1 and Filter 2. Filter 1 includes floating capacitors whereas Filter 2 avoids the

floating capacitors. The Cadence Spectre simulation results show that the characteristics

of both filters meet the specifications. The following data in the format of

valuel1/value2/value3, which represents the specifications, simulation results for Filter 1,

and that of Filter 2, respectively. Pass-band ripple is less than 1/0.75/0.86 dB. Pass-band

and stop-band corner frequency attenuations are -1/-0.96/-0.78 dB and -28/-32/-40 dB,










respectively. Stop-band attenuations for adjacent (at 20 MHz) and alternate adjacent (at

40 MHz) channels are -34/-47/-44 dB and -49/-58/-54 dB, respectively.

Worst case simulations with temperature, process and mismatch variations showed

that the pass-band cutoff frequency varied from 7.7 MHz to 8.7 MHz for both filters

while maintaining the shape of the AC response curve. Simulation results for AC

response with tuning voltage of 0. 1 ~ 1.9 V showed the pass-band cutoff frequency

tuning range of 7.2 ~ 1 1.7 MHz for both filters. This tuning range covers the worst case

variation range. Therefore, these filters can tolerate temperature, process and mismatch

variations by using a simple automatic tuning circuitry. Figures 4-14 and 4-15 show the

AC simulation results for Filter 2.

AC Response











-70




B 10M 20M 30M 40M 50M 68M



Figure 4-14. AC response simulation result for Filter 2


4.4.2 Transient Response, Noise and Linearity

Figure 4-16 (a) gives the result of the transient simulation for pass-band signal at

the edge frequency of 8.3 MHz. The output signal follows the input signal after initial

settling period (~0.6 Cls). The plot shows the linear output signal with approximately 900












phase shift. Figure 4-16 (b) describes the attenuation for the stop-band signal at 12MHz,


which suppresses out-of-band signal after settling.

AC Response
+: vtune="1.9";/n x: vtune="l vtune="1.5";/n u, tune="l3j";/n o: .~- .--
10 7": vtune="900m"/v: viune="" *l*-; vtune="500m";/-: vtune="300m";/o:



0. aj

-10

-20


-40








-80
0.0 10M 20M 30M 40M 50M 60M

B 11.6786M -7181.B8ml slooe: -32.1245f


Figure 4-15. AC response simulation result for Filter 2 with tuning






I t~p







i : a econr 800n 10 0 0 22 40 r e on s















Figure. Noise Figure is commonly defined as [Raz94],




NF = logo (4-7)





































/ I


1 08z 100Hz 161K~z 1.OMI~z 100M~z 100Mz
10Lu~gvOG1fVONOISE*V(OINOISE) /20.35e-9/20.35e-9)
Freqguency

Figure 4-17. Noise in dB vs. frequency plot


The linearity of a filter can be specified by either single-tone total harmonic

distortion (THD) or two-tone input IP3. In this base-band filter design, the linearity of a

filter is characterized by the signal voltage for 1 % THD. This figure of merit is used to

quantify the non-linearity of the filter. Filter 1 shows 1 % THD for an input signal of


where SNRn and SNRour are the signal-to-noise ratios measured at the input and the output,

respectively. For a general calculation of the noise figure, the NF is usually specified for

a 1-Hz bandwidth at a given frequency. This is called as the "spot" noise figure to

emphasize the very small bandwidth. This can be expressed as follows where A = ocA,

and V2n,0ut TepreSents the total noise at the output.


NF =log,(V(, + I Rs)2 V1g 2n,out
4kTRs l A2 4kTRs 48


In this design, we set A=1 and Rs=5kaZ, from which we get the noise figure from the

simulation as NF = V2n,,ut/(20.35n)~2, as shown in Figure 4-17. The NF for the pass-band

of the filter (156.25k










































500m


~ .,..


427 mV, while that of Filter 2 is 45 1 mV, in the nominal case (Figure 4-18). We can see

that Filter 2 tolerates higher input signals than Filter 1, under the same linearity condition.

This is the result of a superior amplitude scaling of Filter 2. The best/worst tuned case

for the temperature, process and mismatch variation gives the maximum input signal


range of 410 ~ 441 mV, and 424 ~ 503 mV, for Filter 1 and Filter 2, respectively.

Transieni Response rni i egns
1.40 ,: thd(VT("/net99") Ze-06 4e-06 6i4) ~ ;a" hii(~lg~j 3-6eic 4


5011m

4sBm


.Xn 400Rm 420m- 4401m 420~m 440m 460m 480im
A: (4 ) Vln i A: (4btd88Srm 1)Vo
(a) (b)

Figure 4-18. Linearity of 1 % THD vs. input signal voltage for (a) Filter 1 and (b) Filter 2
in nominal case


The comparison between Filter 1 and Filter 2 is summarized in Table 4-2. Filter 1

is superior in power consumption and complexity, while Filter 2 shows better linearity.

In conclusion, both 3rd-4th order cascaded elliptic lowpass Gm-C filters satisfy the


specifications for the analog base-band filter in a 5 GHz WLAN receiver.






47


Table 4-2. Summary of characteristics of the two filters
Filter 1 Filter 2

Filter structure 3rd+4th elliptic with floating 3rd+4th elliptic avoiding floating
capacitor caacitor
Gm cells Unit Gm cells (50pAV Unit Gm cells + 10 extras
number of MOS TRs 1364 2577
number of Caps 44 36
Total 21 mA 38 mA

Max nputVpp820/854/882 mV 848/902/1006 mV
(worst/nominal/best)
In-band rms Noise 739.17 uV/9lHz 870.22 uV/9lHz
DR (nominal input) 61 dB 60 dB















CHAPTER 5
AUTOMATIC GAIN CONTROL

5.1 Introduction

Automatic gain control (AGC) is an essential function in a WLAN receiver because

the power received through the wireless channel is unpredictable. The AGC circuitry

provides a known output voltage magnitude from an input signal with variable strength.

In the IEEE 802.11la WLAN system, data pass through the channel in packet frames

consisting of preamble, header and data segments as discussed in Chapter 2. The receiver

estimates corrections for the channel's characteristics during reception of the preamble.

These characteristics are assumed to stay constant throughout the transmission of the

whole packet frame, typically up to 1 ms. The preamble consists of 10 repetitions of a

predefined data stream called a short training symbol (10 x 0.8 Cls) and two repetitions of

a long training symbol (2 x 4 Cls). In the proposed receiver system, the time for seven of

the repeated short training symbols (5.6 Cls) is allocated for signal detection, AGC

convergence and diversity selection [IEE99]. While multipath can significantly alter the

waveform, we assume that the received signal is essentially repeated during each short

training symbol duration, and that its characteristics establish the amplitude and phase

references for use during the entire packet frame.

Conventional closed-loop analog AGCs use feedback loops to adjust the gain of the

variable-gain amplifiers (VGA) to set the desired output signal strength. In such AGC

loops, as shown in Figure 5-1, input and output signals are typically represented by their

peak amplitudes. This adequately represents signal levels for signals with constant PAPR









such as sinusoids. For proper operation of closed-loop AGCs, the time required to

determine peak amplitude must be much less than the time constant (settling time) of the

loop filter [Kho98]. When the input amplitude changes, the detected output amplitude is

compared to the desired amplitude and the difference error is fed back to adjust the gain

of the VGA to provide constant output amplitude. The negative feedback loop

continuously responds to input amplitude variation.


GA


Peak
c, Detector


Loop 4
FilterI O
Vref

Figure 5-1. Conventional AGC loop composed of VGA, Peak Detector and Loop Filter

However, in the 802. 11a application, due to the high PAPR of the OFDM signal,

input or output peak amplitude is not a reliable measure of signal strength. The closed-

loop AGC with peak detector will not converge as the peak amplitude of the OFDM

signal changes continuously. As discussed previously, the specifications require AGC

settling within the time for seven short training symbols. Since seven identical short

training symbols are transmitted through an assumed unchanged channel, all of the

available information about signal amplitude is available during each symbol duration.

So the short training symbol duration (0.8 Cls) is the optimal signal-averaging time. In the

AGC loop, an average or RMS detector can replace the peak detector because signal

strength can be estimated as an average or RMS over the symbol duration. The closed-

loop AGC with average or RMS detector will converge with the time constant of the loop







50



filter much longer than the signal estimation time. The resulting AGC settling time is

much longer than system specifications allow. These issues preclude the use of a


conventional closed-loop AGC in this application. Based on these observations, a new


open-loop AGC circuitry is proposed in the following section.

5.2 AGC Algorithm

Figure 5-2 illustrates the operation of the proposed AGC circuitry. The analog

baseband circuits include three VGA stages plus a channel-selection filter. VGA stage


VGA1, with gain selectable as 7 or 14 dB, precedes the filter. Two VGA stages, with

combined gain variable continuously from about -8 dB to about 32 dB, follow the filter.




LNAI Switched Gain Control 1 I Switched Gain Control 2 I
Gain=0/20dB ,- ---------


(a) R D1 R D2 R D3 D
3d+ 4t
HPF VGA1 order elliptic HPF VGA2 VGA3
Vn LPF

I RMS
I Detector
I-
AGC with One-Step Correction
Iref Gain =-4~28dB

Short Training Symbols
(b) 0.8 ps 1.6 ps 2.4 ps 3.2 ps 4.0 ps 4.8 p
t1 t2 t3 t4 t5 t6 t7


Filter settling R

Set GLNA=20dB
G1 = 7dB
G2 = 6dB COarse Coarse Fine
G3 = 6dB Gain Set 1 Gain Set 2 Gain Set



Figure 5-2. Architecture of the proposed AGC algorithm; (a) block diagram and (b) time
line









Separate AGC loops are provided for the pre- and post-filter gain blocks, since they

operate on different signals as discussed in Chapter 2.

The AGC algorithm operates in three phases: two switched coarse gain-setting

phases, followed by an open-loop fine gain-setting phase. The coarse gain-setting steps

ensure that all of the gain and filter stages operate linearly and that the gain is within

+5 dB of its optimal value. The fine step sets the gain for the entire packet to within

+1 dB of its optimal value. Before the reception of each packet, gains are initialized to

20 dB for the LNA, 7 dB for VGAl and 6 dB for VGA2 and VGA3. During the first

short training symbol time (tt: 0 ~ 0.8 Cls), RMS detectors RD1 and RD2, located before

and after VGA1, estimate the signal amplitude. These values are sampled and held, and

used by 'Switched Gain Control 1', a logic block that selects the gains of the LNA and

VGAl as shown in Figure 5-3. The LNA gain is set to 0 dB if the output of RD1 is

greater than -23 dBm. If the output of RD2 is less than -23 dBm, the gain of VGA 1 is

set to 14 dB. Otherwise, they keep their initial gains. After the signals settle down

through the filter (the second short training symbol duration is allocated for filter settling),

the post-filter AGC loop, Switched Gain Control 2' (Figure 5-4), selects the overall gain

of the second and third VGAs (-3, 7, 17 or 27 dB) based on the signal amplitude detected

during the third short training symbol (t3: 1.6 to 2.4 Cls) using RMS detectors RD3 and

RD4 located before and after the cascade of VGAs. The overall gain of VGA 2 and 3 is

set to -3 dB if the output of RD3 is greater than -30 dBm or to 7 / 17 dB if the output of

RD4 is greater than -20 / -30 dBm. If the output of RD4 is less than -30 dBm, the overall

gain of VGA 2 and 3 is set to 27 dB.







52




Vc V
LNA 7` V2d 1d oc
VGA1


latched latched
Scomparator comparator


-23dBm -23dBm







Figure 5-3. Switched Gain Control 1 of the AGC algorithm




12dB 2d

t=0s t=1.6Cls




latched|
latched comparator
latched comparator
-30dBm
-20dBm

Vc

to VGA2 & 3 cmaao



Figure 5-4. Switched Gain Control 2 of the AGC algorithm

The final open-loop fine gain-setting phase, 'AGC with One-Step Correction', is


applied to VGA2 and VGA3. The circuits include three main components: an RMS

detector, an analog computation block and an inverse-gain block. As discussed in


Chapter 3, an RMS detector should be used for the most accurate amplitude estimation of

the OFDM signal. In this phase, the RMS detector connected to the output of the third


VGA (RD5) detects signal strength during the fifth short training symbol duration











(t5: 3.2 ~ 4.0 Cls). The output voltage of the RMS detector is sampled and held, and the

result, Vol, is used in computing the final gain-control signal for VGA2 and VGA3. The

analog computation circuitry computes the new control voltage (VC2) fTOm Vol, the

desired reference voltage (Vrer) and the initial control voltage (Vcl). The new control

voltage is applied to VGA2 and VGA3 through the inverse-gain block [Kho98], which

adjusts VGA gain to get the desired level of the output signal. Note that the subscripts

1 and 2 represent previous and new time steps respectively.


VGA2

V~~n RMS V
detector


Vcs A
Vc Sample & hold
VGA4 Vet
Vdc C


Inverse Gain Block

sqrt CIVref /Vo

V Computation Block Ve

Figure 5-5. AGC with One-step Correction: the fine gain-setting step

Designing a VGA with reasonable input-to-output linearity is not too hard.

However, accurately predicting the gain for a given gain-control input signal is quite

difficult, especially in short-channel CMOS technologies. The inverse-gain block uses

feedback to set the predicted switched gain accurately. Op-amp A in Figure 5-5 takes two


positive DC voltage inputs, Vc and Vc, and uses feedback to find the AGC gain-control

voltage Vep required to set the gain of VGA4 to A, = Vc / Vde. When Switch T is









connected to Vct (the switched-gain value set during coarse gain step 2), the gain of

VGA4, as well as VGA2 and VGA3, are set to A,1 = Vct / Vdc. (5-1)

That is, the switched gain of the second coarse gain-setting phase (-3, 7, 17 or 27 dB for

2-stage VGAs) is set by the ratio of the selected voltage Vct and the fixed voltage Vdc.

Note that VGA4 in the inverse-gain block must be matched to VGA2 and VGA3 in the

main signal path.

With the input voltage Vin applied during the fifth short training symbol time, the

detected RMS output voltage is sampled and held: Voi = A g2-Vin (5-2)

The computation block computes the final control voltage:

VC2 = Vcl-9(Vre /Vol) (5-3)

Then, VC2 is applied through Switch T to the inverse gain block, where the feedback loop

of the op-amp A forces the gain of the VGA to Av2 = VC2 / Vdc. (5-4)

From Equations 5-3 and 5-4: Av2 = VC2 / Vdc = Vc1/ Vdc -\IVre Vl, and from Equation

5-1: Av2 = Avy -\(Vrer / Vol) (5-5)

We can write the final output voltage as follows:

Vo2 = Av22-Vin = {Avl -\(Vre /Vol)}2-Vi = A g2-Vin / Vol .Vrer = Vref

This equation shows that the final open-loop fine gain-setting AGC makes the output

voltage Vo2 equal to the desired voltage Vrer with one-step gain correction. Note that the

final gain is held constant throughout the transmission of the packet frame. We also note

that both I and Q channels can use one AGC loop for identical gain control, so the RMS

detector can estimate the output amplitude from both I and Q channel signals.

In summary, the proposed AGC algorithm uses a three-step iterative open-loop gain

control method (two coarse gain-settings using switches, followed by a final fine gain-









setting using an open-loop computation circuit). The algorithm converges within seven

short-training-symbol times, and holds the final gain throughout the whole packet frame.

This avoids the settling-time limits of a conventional closed-loop AGC.

5.3 Circuit Design

5.3.1 Variable Gain Amplifier

The transconductance of a MOS differential pair may be varied either with bias

current, or by an adjustable degeneration resistor. A Gilbert multiplier-type amplifier is

well suited to implement a VGA with large gain and low noise, but its linearity is limited.

A differential pair degenerated by a MOSFET resistor can handle large signals given a

low power supply resulting in good linearity, because the degeneration does not degrade

the voltage headroom in a simple differential pair. However, this degenerated differential

pair has limited gain range and poor noise figure [Tad98]. High linearity in a

transconductance cell requires the transconductance (Gm) to be independent of input

signal.

To cover the required gain range of -4 to 16 dB mentioned in Chapter 2, the VGA

gain must be variable over a wide range. Also, it should have good linearity and low

noise. To ensure that the VGA can fulfill these requirements, it is designed as a linear

transconductance cell combined with cross-coupled differential pairs as in a Gilbert cell

for gain control. A source follower with shunt feedback, the so-called flipped voltage

follower (FVF), provides a low-impedance output node with a constant current through

the input transistor [Car05]. A highly linear transconductance cell can be achieved by

placing a fixed resistor Rx between the low-impedance nodes of the differential FVF to

provide a constant transconductance Gm = 2/Rx. Feeding the output current of the

transconductor to a fixed-resistor load RL WOuld give a constant gain 2-RL/Rx. The









differential pairs of Gilbert cell are used to steer the tuned portion of the transconductor' s

output current to the load to make the gain adjustable. This type of VGA structure can

provide -4 to 16 dB gain with good linearity.



V~- I~4aM
ML~I I ~ Ix In*21 V1 IJI

M~a Y3 M~aMlb Y4 M~

I3 I R X1 X~ X2RY
el~n- Mia M~tb

IIla


I I6 V V I I Ms






Figure 5-6. Schematic of the proposed VGA

The proposed VGA consists of a linear transconductance cell (differential FVF

with linear resistor), Gilbert cell-type differential pairs and load resistors, as shown in

Figure 5-6. In the differential FVF transconductance cell, due to the feedback loop, input

signal applied to transistors M1a, b does not affect the transconductance Gm = 2/Rx, that is,

currents through M1a, b and M3a, b arT COnstant. Instead, the input signal changes voltages

at the low impedance nodes X1, 2 and current Ix flows through resistor Rx sourcing from

M3a, b: IX (1 I2)/2 = Gm-Vin where Gm = 2/Rx. (5-6)

The output currents (lI and It) Of the transconductor are mirrored to the differential pairs

with a 1:1 ratio: li = IS and I2 14 (5-7)










The cross-coupled structure of the Gilbert cell-type differential pairs yields

IS = 5 16 and I4 = 7 + 8. The control voltages (Vcl > VC2 > 0) are provided by a

differential difference amplifier (DDA) and their differences adjust currents to the output

stage: Is = I3-f(VC2 Vc1), I6 = 3-f(Vc1 VC2), 17 = 4-f(Vc1 VC2),

and Is = I4-f(VC2 Vct), (5-8)

where 1 > f(Vcl VC2) > 1/2, and f(VC2 Vcl) = 1 f(Vcl VC2). (5-9)

The output stage consists of load resistors (RL1, 2) with common-mode feedback

(CMFB), level-shift resistors (RS1, 2) and current sources (Msa, b). Since 19 10Il,

Is + I, = 19 IL, and 16 8 10= l IL, (5-10)

we can get the output current IL (6 17 8I I5)/2. (5-11)

Using Equations 5-8 and 5-9, we can rewrite the output current

IL (3 I4)- {2-f(Vc1 VC2) 1}/2, (5-12)

and from Equations 5-6 and 5-7, IL = X- {2-f(Vc1 VC2) 1}. (5-13)

The output voltage and voltage gain are

Vout = IL.RL = 2-Vin-RL/Rxf {2f(VTI_ VC2)\ 1}, (5-14)


A, = Vout / Vin = 2-RL/Rx- {2-f(Vcl VC2) 1}. (5-15)

The maximum gain is achieved when the difference of the control voltages is maximum

(f(Vcl VC2) ~ 1), that is, Av, ma 2-RL/Rx. (5-16)

Since DC biasing for the input stage is provided by output stage of an identical VGA

stage, the output stage has level-shift resistors (Rsl and RS2) to match the input and output

common-mode voltage ranges.

Voltages in the VGA are highly constrained. For negative input swing M1 tends to

go triode and M2 tends to go triode for positive input swing. To increase the usable input










range, voltage level-shifter (Iv-Ry) is added in the shunt feedback path of the FVF, which

brings the drain voltages of M1 and M3 ClOser to the negative supply rail. To optimize the

voltage swing of the linear transconductance cell, the appropriate range of the voltage

level-shifter is analyzed. If all transistor pairs are well matched and differential inputs

are given as VCM f Avin, we can write: Ix = 2-Avin/Rx, and A~vout A~vin, where Avout

represents voltage variation at node X1 (or X2) due to Avin. For the worst case of applied

maximum input +Avin to the positive input port Vin+, transistors Mta, Mlb and Mgb should

be in the active region. Conditions on Mta and Mlb set the lower limit of the level-shift

voltage, while Mgb COndition set the upper limit. At the edge of the active region,

VGS1 = VT1 + V DSAT1, VGS2 = VTO + V DSAT2 and VGS3 = VTN + V DSAT3, where VTN is

NMOS threshold voltage without body effect, and VTO and VT1 are PMOS threshold

voltages without and with body effect, respectively.

To keep Mta in the active region, the voltage at node X1 must be less than VDD -

VDSAT2, that is, Vx1 < VDD VDSAT2. (5-17)

Let the level-shift voltage AV = ly-Ry, then Vyl = VDD VGS2a AV and

Vxl = Vyl + VDSAT1 + Vout. From Equation 5-17, we can get

AV > VDSAT1 + Vout VTO. (5-18)

Simple calculation with maximum Avout of 0.25 V and nominal values like

VDSAT1 = 0.2 V and VTO = 0.5 V shows -0.05 V as lower limit of AV. This means that no

voltage level-shifter is needed in this case to ensure M2 Stage in the active region.

To keep Mlb in the active region, the voltage at node Y2 must be less than

VG2 + VT1, that is, VY2 < VG2 + VT1. (5-19)










Solving Equation 5-19 for AV with VY2 = VDD VGS~b AV and VG2 = VcM Avin,

we can get AV > VDD VDSAT2 VTO VT1 VcM + Avin (5-20)

With an input common-mode voltage VcM of about 0.5 V, 1.8 V supply voltage and other

nominal values as above, this condition requires a voltage level-shift of more than 0.25 V.

The final condition is for NMOS transistor M3b to be in the active region:

VY2 >V DSAT3. (5-21)

Solving this for AV results in AV < VDD VTO VDSAT2 VDSAT3. (5-22)

With similar rough calculation, this condition limits the voltage level-shift value to less

than 0.9 V. Thus, by considering all three conditions, the voltage level-shift value must

be selected in the range of 0.25 V < AV < 0.9 V.

Since the two conditions for the voltage level-shift value reference the positive

supply voltage, we must allow for supply voltage variation of 10% (1.6 ~2.0 V).

Although we can select the level-shift value under the worst-case condition

(0.25 + 0.2 V < AV < 0.9 0.2 V), to optimize signal swing for all VDD ValUeS, AV should

be varied along with the variation of supply voltage. The level-shifters are implemented

as linear resistors (Ryl and RY2) with current sources (M4a, b). The current sources are

controlled by a voltage Vy from a replica bias circuit (Figure 5-7). The replica bias

circuit finds Vy to make VD M1 match VD M12, referenced to ground rather than supply

voltage. In this design, the voltage level-shift value AV is set to 0.6 V and the voltages

near the positive supply voltage nodes (Y3 and Y4) vary with VDD while the other nodes

(Y1 and Y2) almOst keep the same voltage. Inside the replica bias circuit, there are three

feedback loops: two negative feedback loops (VY-M4-VA-M2-M1-VB-M1 1-M13 and VA-

M2-M1-VB-RY) and one positive feedback loop (VY-M4-VA-RY -VB-M11-M13). Due to the












positive feedback loop, there can be multiple operating points [Fox99]. We need to make


sure that only one operating point exists in the replica bias circuit design by using DC


simulation for VA and VB aS shown in Figure 5-8.


Figure 5-7. Schematic of the replica bias circuit for VGA


I
I
IT
IIB
I
I
r


r


VB








0.66 V


IA = 0


Figure 5-8. Simulation result for finding operating point in the replica bias circuit. The
result verifies that the bias circuit (for AV = 0.6 V) can operate only at the
single operating point of VA = 1.26 V and VB = 0.66 V.


The VGA structure shows good linearity with large gain range. However, there are


tradeoffs among gain range, linearity, noise, frequency bandwidth and current


consumption in circuit design. Input transistors M1a and Mlb have short channels to


enhance gm, but increase flicker noise, so PMOS devices were used for this circuitry.









Using long-channel transistors for NMOS output current sources (Msa, b) alSO improves

noise performance. Scaling up current along with channel widths reduces noise without

changing circuit performance but current consumption had to be limited. Although long-

channel devices reduce noise, they tend to degrade bandwidth due to large parasitic

capacitances. Thus, short-channel transistors are used for Gilbert cell-type differential

pairs and current mirrors to achieve adequate bandwidth. The current-mirror output of

the VGA enables removing the PMOS tail current source, which saves voltage headroom.

Constant current biasing is maintained by the balanced control voltages from the DDA.

5.3.2 Differential Difference Amplifier

A Differential Difference Amplifier (DDA) is used for the amplifier in the inverse

gain-control loop because the loop operates in differential mode. A DDA has two

differential input pairs and a differential output pair. When used in negative feedback

connection with very large open loop gain, the DDA forces the two differential input

pairs identical [Hun97]. To ensure a wide output control voltage range, the DDA is

implemented as a folded cascade structure as shown in Figure 5-9. It contains two simple

differential pairs (M1, M2, M3 and M4) which compare the difference of the two

differential input signal voltages (Vc~ and Vdc+). The differential cascode output stages,

combined with a common-mode feedback (CMFB) circuit with level-shifters, provide

differential output control voltages (Vcpl and Vep2) which change with the input

difference. The CMFB circuit has a simple structure using source followers with level-

shift resistors. Source followers M15 and M16 detect the output voltages of the DDA at

their gates, and their corresponding source voltage difference generates current through

R1 and R2. This current shifts the common-mode voltage level VCM which is fed back to

the gates of the cascode PMOS transistors M7 and Mil. The differential control voltages










are set by the feedback as the inverse gain loop forces the two inputs to be identical.

Since the DDA works with DC control voltages, two compensation capacitors (Ccl = CC2

= 10 pF), grounded in series with resistors, are added to the output nodes for stability.





,M7 19 M11 I
edjpl nddl
s M6 VCM
pr 0 Mg M12

Vdc+ Vcpl, 4V
M1M2 3 M4 dc- M15 M16

M9 13


10 17 M18 M14



Figure 5-9. Schematic of the proposed Differential Difference Amplifier

5.3.3 RMS Detector

The RMS detector estimates the RMS value of the output signal, integrated

throughout one short training symbol duration. The RMS circuit is based on the

approximately square-law characteristics of long-channel (~ 2 Clm) MOSFETs in strong

inversion [See87, Han98]. The dynamic range of this circuit is rather narrow, which is

acceptable because the coarse gain-setting step ensures the signals are not far from their

optimal value. The RMS output voltage is stored as the difference of the VGSs Sof a pair

of diode-connected NMOS transistors (Vout+ Vout+). This signal is sampled and held on

storage capacitors connected to the gates of NMOS transistors.

The RMS detector in Figure 5-10 uses NMOS transistors in strong inversion as the

input squarer. The differential output voltages of the VGA with common-mode voltage









are fed to the gates of the NMOS transistors. Let the input signal VIN = VCM + vin. The

squarer transistor M1 converts input voltage vin to output current li as follows:

1 w W~ fw1 W
I, =-KI- (VGS1 -V,)~ = -KI-- (V,, +v, V,)
2 nLi\LI 1 2 nLu I

1 W\
K,, v,, V with VCM VT (5-23)
2 "Li
The resulting drain current of M1 is almost proportional to the square of the input voltage

if we set VcM ~ VT. Similarly, the drain current of M2 is almost proportional to the

square of the input voltage when the input signal is positive. Above the NMOS squarer

are two cross-coupled NMOS differential pairs (M3 ~ M6). They operate like switches to

rectify the currents in differential mode. For the differential pairs to work as switches,

their gates must be triggered by large signals at the input signal frequency. Hence, the

input signals vin+ and vin- are boosted as Vn and V, using amplifiers A and B, and

supplied to the gates of the differential pairs. The currents li and I2 are rectified to Is

when the input signal is positive and to I7 otherwise. Figure 5-11 plots DC simulation

results for V-to-I converted currents (lI and It) and rectified currents (I, and Is), which

shows that current Is is nearly proportional to the square of the input voltage.

Currents I7 and Is are averaged and square-rooted to complete the RMS detection.

The averaging of the currents is performed using a cascade of two first-order lowpass

filters to meet the estimation time constraint of a short training symbol (0.8 Cps). To

provide an acceptable trade-off between smoothing and settling time, the on-chip

capacitors are set to C1 = 4 pF and C2 = 10 pF, where C2 is bigger because it also used as

a storage capacitor. The output current of the first PMOS lowpass filter is mirrored to the

second NMOS lowpass filter. In this second filter, the NMOS implements a square-root

function by converting the current to a voltage proportional to the square-root of the











current. The gate of the NMOS transistor and the storage capacitor are connected with a


switch S (small geometry NMOS), which is opened after the symbol duration for the


capacitor to hold the stored voltage.


Figure 5-10. Schematic of the proposed RMS detector


DC Response
:: /1152/M2/D


'12 1


DC Response
.-: /Il52/M19/S
120u .; : /Il52/M1/S

100u

801.0u

6g.W

40,0Ru 1

20.0u


12u r: /

12.0u .

6100u

4800u

60,0Ru .

40,0u


230m 4-----8~nl~0m 730m 230m 480m 73
Vamp Vamp


Figure 5-11i. DC simulation results of the RMS detector with VCM = 0.48 and vin = -0.25
~ 0.25 V: (a) currents II,2 after squarer and (b) currents 13,4 after rectifier

5.3.4 Computation Block

The coarse gain-setting step provides us with a voltage Vct that is applied to the


inverse-gain block (along with Vde) to set the VGA gains to a value within +5 dB of their


Vm+ Vn

Vm- V,









optimal values. The resulting RMS value Vol of the output is measured during tS and is

sampled and held. An analog computation block compares Vol to the desired value Vrer,

and computes the new value of VC2 = Vcl(IVrer/Vol) as discussed in the previous section.

The final control voltage VC2 must be applied to the inverse-gain block to force the gain

to its optimal value. For the optimal gain after the final control, we assume that the

precision of 1 dB is acceptable for the system (approximately 10.5 dB is achieved by

this computation block) as a design target. However, it is not easy to realize the analog

computation block with multiplier, divider and square-root function blocks.

The analog computation block is implemented using translinear circuits based on

weak-inversion FETs [Mul99], which reduces power dissipation and complexity of the

circuit. This requires that the input and output signals be represented as small (~1 CIA)

single-ended currents. The single-ended current-mode operation of the computation

block tends to be noisier than the differential mode. This reduces the accuracy of the

computation, but the noise does not couple into the VGA signal path, since the gain is

fixed during transmission of the data packet.

Figure 5-12 shows V-to-I and I-to-V converters with single-ended and/or

differential mode terminals. The differential voltage to single-ended current converter in

Figure 5-12 (a) is placed between RMS detectors (RD5) and the computation block,

which converts the output differential voltage of RD5 to lot in the computation block.

This V-to-I converter provides a linear output current which is attenuated to around 1 LA.

The NMOS input transistors M1 and M2 have 5 times less transconductance compared to

the output NMOS transistors of the RMS detector. PMOS transistors Mg and M6 aef

connected to the active loads (M3 and M4) Of the input devices with shunt feedback, and




















M1 Io M2c V,




8s 11


(a)




oddlddd
M3 4 2 3g
widl ~~~rddl dlV2 dd






Van ICM


SRd 6~ M7
MS

(b) (c)


Figure 5-12. V-to-I and I-to-V converters in (a) differential V to single-ended I, (b)
single-ended V-to-I, and (c) single-ended I to differential V modes

work as source followers. The low impedance output nodes of the source followers are

connected through a big linear resistor R (30 kGZ). The difference of the two input

voltages creates a voltage between sources of Mg and M6, and thus a small amount of

current IR aCTOss the resistor R. IR flOws through M6, Ms and M9, and is mirrored to lot

via the 4: 1 attenuation cascode current mirror (Ms, M9, Mlo and Mil). This differential-

voltage to single-ended current converter/attenuator provides around 1 CLA of single-









ended current output to the computation block for a voltage input of about 250 mV from

RMS detector.

The single-ended V-to-I converters in Figure 5-12 (b) convert single-ended

voltages Vrer and Vet to single-ended currents herf and Ict. A low gm NMOS transistor

(M1) with degeneration resistor Rd (15 kGZ) converts input voltage Vin to current Il. This

current is mirrored through a 4: 1 attenuation cascode current mirror (M2, M3, M4 and Mg)

and is mirrored again through the 2:1 attenuation current mirror (M6 and M7) to achieve

an output current Io of around 1 CLA for the computation block.

Single-ended current to differential voltage converter in Figure 5-12 (c) converts

the output current IC2 Of the computation block to the input differential voltage VC2 Of the

inverse gain control block. This I-to-V converter amplifies its input current using a 1:4

cascode current mirror (M1, M2, M3 and M4), and the amplified output current Io creates

two equal voltage drops in series-connected resistors R1 and R2. Differential output

voltages are supplied at the top of R1 and at the bottom of R2. The gate of the M5

connects to the node between R1 and R2 to set the common-mode voltage. M6 delivers a

common-mode current IcM to the drain of Mg, which provides a common-mode voltage to

the gate of Mg even when there is no input current applied.

Single-ended voltages Vct from the switched gain control block and Vde are

converted to differential input voltages of the inverse gain control block through a

cascade of a single-ended V-to-I converter and a single-ended current to differential

voltage converter to minimize mismatch with the other differential control voltage VC2

converted from the current mode computation block.




















Ict 7~ lot~ Irer PIC2


Figure 5-13. Schematic of the proposed analog computation block. The arrows indicate
the VGS S that form the translinear loop.

The schematic of the proposed analog computation block is shown in Figure 5-13.

Applying the translinear characteristics in weak inversion, we get the desired

computation as written in the following equations.

- VGS C1 VGS C1 + VGS 01 VGS ref + VGS C2 + VGS C2 = 0 (5-24)

- InIcl InIcl + Inlot InIrer + InlC2 + InC2 = 0 (5-25)

lInC22 In C12 reIIf o I, (5-26)

In(ICzcl2 C1 2 ref ol) (5-27)

:. IC2 = C1.\IeT (5-28)

This circuit provides an output current IC2 with expected computation when the input

currents Ict, lot and herf are applied.

To guarantee translinear operation in weak inversion with currents of about 1 CLA

and lower, PMOS transistors are large sized: W/L = 200/1 Cpm for M1, M2, Ms and M9.

For the differential pair M3 and M4, lOnger channel with smaller widths are used to

provide good matching. M2, M3, M4 and M9 have separate n-wells to remove errors due









to bulk effect. Also, fast and stable operation is achieved by adjusting channel length for

inner loop transistors Mg, M6 and M7.

5.3.5 Switched Gain Control 2

The switched gain control block is implemented using latched comparators,

transmission gate switches, and two reference voltage generators (VINIT and VTH) aS

shown in Figure 5-14. A latched comparator which is a folded-cascode differential

amplifier with a dynamic latch load compares two inputs, Vin (output from RMS

detector) and Vth (threshold voltage from the reference voltage generator VTH), and yields

differential outputs to activate transmission gate switches: either SA Or SB. When the

latch signal goes from 0 to 1, the cross-connected positive feedback loop forces the

differential output voltages to be latched [Ock99]. The result of the comparison of the

two inputs decides the polarity of the output. The output of the latched comparator is

connected to the gates of transmission gate switches (SA and SB) which select between

two voltage inputs. The switching connection to select Vct is completed when the

transmission gate switch S1 is on. Three sets of latched comparators and transmission

gates select gain-control voltage out of four initial voltages by comparing the outputs of

the RMS detectors and the threshold voltages, as described in the AGC algorithm section.

The initial voltage and threshold voltage generators provide reference voltages

which are preset by resistor banks. The initial voltage generator VINIT prOVides six preset

voltages V-3dB, VodB, V7dB, V12dB, V17dB and V27dB. V-3dB, V7dB, V17dB and V27dB are

selectable Vct voltages, while VodB and V12dB are VDC VOltage and Vco voltage for the

initial VGA gain, respectively. As we mentioned before, the inverse gain control loop

sets the two-stage VGA gain as Av = 40-log(Vet/VDc) dB. So, Vet can be found such

that Vet = VDe -10Av/40. (5-29)







70


VDC


Vco V- I3dB



SWO~SW V, ITdO




Ifv V 777, then Vo Vg, else Vo VA
."Latched Comparator 1
LC2 SW3
V27d



I~ I oI LC3
~itch



V20dBm
V-30dBm

I~ I T I V URD4



4 V RD3


Figure 5-14. Switched gain control block implementation using latched comparators and
transmission gates

With VDe = VCM 0- 3 5 mV, the differences of the differential Vcl (including VDe and Vco)

voltages for V-3dB, VodB, V7dB, V12dB, V17dB and V27dB are 58.5, 70, 104.8, 139.6, 186.2

and 331.2 mV, respectively. Since single-ended Vct is converted to a corresponding

differential Vct through V-to-I and I-to-V converters, we can find the single-ended

voltages for V-3dB, VodB, V7dB, V12dB, V17dB and V27dB by DC simulation of those two

converters. Figure 5-15 shows DC simulation result of the single-ended V-to-I and I-to-

differential V conversion for gain control voltage Vet.







71


DC Response
.: /Il33/Il57/net23
700m _.: /1133/157/nett0171
VOdB V12dB









.V3dB V7dB V17dB V27dB
650m 950m 1.25
single-ended V,, (V)

Figure 5-15. DC simulation result of the single-ended V-to-I and I-to-differential V
converters (single-ended Vet versus differential V cl)

The corresponding single-ended Vet voltages for V-3dB, VodB, V7dB, V12dB, V17dB

and V27dB are 687, 716, 798, 871, 963 and 1279 mV. These preset control voltages for

switched gain are implemented using resistor banks as shown in Figure 5-16. Applying

an external 1.5 V supply voltage to a branch with total resistance of 15 kGZ enables

tapping out the desired voltages with corresponding ratio of tapped resistors (Figure 5-16

(a)). In order to improve matching and to reduce process variations, each section of

resistor is made of serial and parallel connections of a root component resistor as shown

in Figure 5-16 (b) [Sai02]. For example, by choosing 2.32 kGZ as the root resistor RR, the

0.29 kGZ resistor between V-3dB and VodB is realized as eight parallel connections of the

root component.

Another reference voltage generator VTH prOVides three threshold voltages (V-20dem,

V-22dem and V-30deng) for latched comparators. The reference voltage V-20denz is preset to

the positive output value of the RMS detector with 500 mV,, input signal (desired output






72


2.21k 3.16k 0.92k 0.73k 0. 82k 0.29k 6.87k<


V7dB


V~dB


V-3dB


V27dB V17dB V12dB
V


(b)


RR = 2.32 kGZ


Figure 5-16. Reference voltage generator VINIT has six taps for preset voltages and is
implemented as serial and parallel connections of a root component resistor.

signal level). Other reference voltages V-22dem and V-30dem are preSet to the value of the

RMS detector with 397.2 mV,, and 158.2 mV,, input signals which are 2 dB and 10 dB

less than the desired one, respectively. These preset voltages are compared with actual

output voltages of RMS detectors by latched comparators during the switching gain

control step. Applying the same method used for VINIT, the reference voltage generator

VTH is implemented using a resistor bank (Figure 5-17). Note that two different sets of

threshold voltages are provided with signal type selection, since RMS values are different

between sine wave signal (sine) and short training symbol (STS).










V-20dBm sine V-22dBm~sine V-30dBm sine









Switch for m w
ine/STS selection w -v -
W &RR 4.8 kGZ








RR = 2.54 kGZ








V-20bdm STs V-22dn~m STs~h, V-30dI~mSTS




Figure 5-17. Reference voltage generator VTH prOVides threshold voltages (V-20dem, V.
22dem and V-30dem) either for short training symbol signal or for sine wave
signal .

5.4 IC Implementation and Measurement

5.4.1 IC Implementation with Embedded Test Points

The portion of the AGC circuits following the channel-selection filter in Figure 5-2,

including two VGAs, switched gain control 2 and AGC with one-step correction, was

fabricated using a 0. 18 Clm CMOS process available through MOSIS. On-chip embedded

test points are included in the design for testability. Analog test buses provide access to









internal nodes using switching structures [Bur01]. Figure 5-18 shows the AGC circuitry

with 7 test points (SWT1 ~ SWT7).

The main signal chain of the AGC circuit consists of two VGA stages as described

in the previous section. Combined with external coupling capacitors (C 0.1 CLF), input

bias voltages for VGA2 are provided by on-chip resistors (R 240 ka) in a negative

feedback loop from the output nodes of VGA3. This feedback loop works as an RC

lowpass filter which provides dc bias voltage to the input stage. Output signals can be

measured through voltage buffers which reduce the output impedance of the AGC circuit.

Simple PMOS source followers are used as voltage buffers as shown in Figure 5-19.

Since these buffers are for test purpose, 3 V devices are used to accommodate level

shifted DC bias voltage (0.48 V 1.48 V). The current source M2 provides 1 mA of

DC bias current for good sourcing capability which enables this buffer to sink a large

current from the load concerning large-signal behavior. The bulk of Ml is tied to the

source using a separate n-well, which eliminates nonlinearity due to body effect.

As designated in Figure 5-18, seven test point switches are placed as follows: 1) at

the output nodes of RD3, 2) between the output nodes of RD5 and the Vo input nodes of

V-to-I converter, 3) between the Io output branch of V-to-I converter and the Io input

branch of computation block, 4) between the herf output branch of V-to-I converter and

the herf input branch of computation block, 5) between the IC2 Output branch of

computation block and the IC2 input branch of I-to-V converter, 6) between the output

nodes of Vcl/VC2 time switch and the V, input nodes of DDA, and 7) between the Vdc

output nodes of I-to-V converter and the Vdc input nodes of VGA4. Test switches 3), 4)










and 5) are current switches implemented using current mirrors with transmission gate

switches while others are voltage switches (transmission gate switches).


-VC2 Cm
I-V
sw
.DDA 1 -v v-1 v-1 yref



VGA4 1 H-v v-1 D

One-step Gain Control


Figure 5-18. Proposed AGC circuitry with 7 test points










VtddJv


Vp M2



out

pmoissv



n Md






Figure 5-19. Output voltage buffer

All test points are connected with differential in/out test buses through input/output

test switches, and the test buses are connected to four pads (Test~in+, Test~in-, Test~out+

and Test~out-). From the test pads, we can access one out of seven test points, selectable

using test switches. Internal signal paths are connected as normal when the test switches

are off. However, one of the test switches is on, the internal signal path of the point is

disconnected and the test point is externally accessible. For example, if we turn the test

switches 7_IN and 7_OUT on, then the Vdc output nodes of the I-to-V converter are

connected to Test~out+ and Test~out- pads, and the Vdc input nodes of DDA are

connected to the Test jn+ and Test~in- pads. In this switch selection, we can monitor

internal Vdc from Test~out pads and force an external Vdc value to Test~in pads during

measurement.

The voltage switch SWT7 in Figure 5-20 (a) has two selections, that is, SWTi for

test input and SWTo for test output, and eight transmission gates for differential signal

paths, where four of them (A, B, C and D) are used for positive signal paths. Two









internal nodes (Vip and Vop) are COnnected through transmission gates A and C when both

switches are set to 0. Setting SWTo to 1 forces transmission gate A to off and B to on,

which changes connection from Vip-Vop to Vip-Top. Thus, internal voltage of node Vip can

be monitored through the positive test output pad Top. Similarly, setting SWTi to 1

makes Vop COnnected to Tip, thus external input can be forced into Vop HOde through the

positive test input pad Tip.

Figure 5-20 (b) shows current switch SWT5, used for testing the Ic2 branch in the

computation block. Two selections are SWTi for test input and SWTo for test output.

Voltage switch box SWI connects Vn2 to VN node and ground (0) to VTi and VTo

nodes when both switches are off. In this switch connection, the output current flows

through the Ic2 branch via the M1-M2-M3-M4 current mirror. When SWTi is set to on,

the gate of M4 is switched to ground; hence, the Ic2 branch is disconnected from the

computation block. At the same time, the gate voltages of M6 and M9 are switched from

ground to Vn2, which enables connection from Tin to Ic2 via M6-M7-M8-M9 current

mirror. For the test output, switch sw5To is set to on. This makes transistor M4 off and

transistor MS on, thus the output current flows through Tout branch via M1-M2-M3-M5

current mirror.

5.4.2 Simulation Results

The implemented AGC circuits were simulated using Cadence Spectre with TSMC

0.18 Clm models. Figure 5-21 shows DC simulation results for the VGA in the inverse

gain control loop. By applying control voltage V, to the inverse gain loop, we can easily

achieve a linear gain control characteristic with desired gain of A, = V,/Vde.









With Vdc = 35 mV, we can get the VGA gain of -4 dB by setting V, = 22. 1 mV, of 0 dB

by setting V, = 35 mV and of 16 dB by setting V, = 221 mV. When Vin is set to 39.6 mV,

the simulation result shows that Vout changes from 25 mV to 247 mV with V,, a range of

-4 to 16 dB. This is just a -0.1 dB gain error at the maximum gain (16 dB). Another DC

simulation is for the input-output linearity of the VGA.


ISWTo


I~11n


(b)

Figure 5-20. Test switches; (a) voltage switch, and (b) current switch





79


J

i'


r


Vout


1G~T~m


221150 m 121 55m 221.00m
A: (22.1rn dla: (18-m 2 2m)
B: (21m -- I soupe: 1.11575

Figure 5-21. DC gain control simulation for the VGA with inverse gain loop

Figure 5-22 (a) shows Vin vs. Vout plot at the minimum gain (-4 dB), while Figure 5-22


(b) shows the plot at the maximum gain (16 dB). The simulation results show that the

linearity error for the maximum input (250 mV,) at the minimum gain is 0.36 dB and the


linearity error for the maximum output (250 mV,) at the maximum gain is -0.1 dB. AC


response plots of the two-stage VGA shown in Figure 5-23 ensure the operation of the

VGAs in the channel frequency range (156.25 KHz ~ 8.3 MHz).


-: /op1
800lm _: /on1









50Alm



25 m -40im


: fop1
700;m _: /on1


400;m


300jm ~
-250m

B: (25Dm -- 4


slope:


0l.0
Vamp
delta: (79,2m 493,6Mm)
slope: 6.23532


Figure 5-22. DC simulation for Vin versus Vout of the VGA at (a) -4 dB gain and (b) 16
dB gain






80



10.0 :"(a)


-30.0-3 dB @ 48 MHz

-70.0r




(b)

-200r -450 @ 9.6 MHz

-8 -1350 @ 28 MHz



1 100K 1M 10M 100M 1G
Frequency -

Figure 5-23. AC response of the VGA; (a) gain and (b) phase

Noise simulation indicates that the total output noise of the VGA for the signal

bandwidth (156.25 KHz ~ 8.3 MHz) at 0 dB gain is 221 LVrms. Input referred noise can

be derived as: 221e-6/-\81e = 77.5 nV/EH. Figure 5-24 shows noise versus gain plot

of the VGA. Input referred noise at the minimum gain (-4 dB) is about 120 nV/9\Hz due

to negative gain, but it goes down to 97 nV/E~H at the actual minimum gain without

margin (-2 dB). Moreover, as VGA1, located before channel-select filter, has 7 or 14 dB

selectable gain, the input referred noise of the analog baseband processor would be below

40 nV/EH.

The linearity of the 2-stage VGA is specified by single-tone total harmonic

distortion (THD) in -8, O and 32 dB gain modes in Figure 5-25. The 2-stage VGA shows

0.99 % THD at the maximum gain (32 dB), while it shows 1.03 and 1.36 % THDs at

0 dB and minimum (-8 dB) gains, respectively.





























































A; (2bdm 1.3b233) delta: (0 -328.971m) A: (t).2dm 994.2/bm)
B: (250m 1.03336) slope: undefined


Figure 5-25. Linearity of the 2-stage VGA in THD (%) versus input signal voltage plots
at (a) -8 dB, (b) 0 dB and (c) 32 dB gain settings

Figure 5-26 shows the input versus output characteristic of the RMS detector. Plots


(a) and (b) are drawn in dB range, where (a) is for a sine wave input and (b) is for a short


training symbol. The input versus output characteristics for sine waves and short training


symbols have about 21 dB (-18 to 3 dB) of dynamic range with reasonable linearity.


Transient Response

,. : thd(VT("/net0157") Ze-06 4e-06 64 10000~r



(C) M,



t 700m.
D (%)
600m.

500m
5.20m 5.601m 6.00m 6.401m
Vn (V)' Vamp


*- out noise
---a--- in noise


Gain vs. Noise


-4 -2 0 2 4 6 8 10 12 14 16

Gain (dB)


Figure 5-24. VGA input and output noise versus gain


Transient Response
:: thd(V("net0157) Ze-06 4e-06 64 10
1,0 .s: thd V("net0157 ) Ze-06 4e-06 64 10


1.20 (a)





THI
6001m t

4001m ....
150m 200m 250m
Vs, (V)' vamp






























Figure 5-26. Input versus output characteristic of RMS detector; (a) for sine wave signal
and (b) for short training symbol

The input voltage versus output current characteristic of the V-to-I converter is

shown in Figure 5-27 (a). The V-to-I converter takes the differential voltage from the

RMS detector as input and converts it to a single-ended output current which flows into

the computation block as lot. To make sure the current mode circuit operate fast enough

for the settling time constraints, the V-to-I converter was designed with fast step response


(Figure 5-27 (b)). Figure 5-28 shows the input versus output plot of the I-to-V converter.

DC Response Transient Response

1.40~u :. /1128/Iout R 700ln .a: /Il28/Iout

1.2u a600n 10Iut
1.00~u
I0ut 500~n
400




200n *~i ** *** *** ** r ,,,. ,, ,,, ,,, I 200~n
20.10m 70.10m 120m 170m 0.0 500n 1.0u
Vamp2 time ( s)
B: (164.9;8m 1.362510) slope: B.1i6609u

Figure 5-27. Characteristic of V-to-I converter; (a) input versus output linearity and (b)
step response


82



(a) RMS detector (sin) 12tl8 (b) RMS detector (STS) v uc


Vln(dB) Vm (dB










DC Response



700lm .

600m V ot+

V,,




Idc
A: r1_bu /bb.602m) deta: i0 -498._2t8m)
B: (1,5u 260.394m~slope: undefined

Figure 5-28. Input versus output characteristic of I-to-V converter

The differential output voltage (0 ~ 500 mV,,) changes linearly along with the

single-ended input current (0 ~ 1.5 CLA). The small increase (~20 mV) of the common-

mode voltage over the range does not affect the differential output voltage of the I-to-V

converter.

Simulation results of the proposed analog computation block for sine wave and

short training symbol signals are shown in Figures 5-29 and 5-30, respectively. As

discussed in the circuit design section, the computation block operates in current mode

with three inputs (lot, herf and Ict) and generates one output (IC2). The plots show the

output (IC2) VeTSus input (lor) characteristic, since the currents herf and Icl are fixed in the

final gain setting step. The switched gain control current Icl is set to one of the four

preset values: 256 nA (-3 dB), 452 nA (7 dB), 794 nA (17 dB) and 1.397 CLA (27 dB).

The reference current herf is set to 1.025 CLA for sine wave or to 631 nA for the short

training symbol signal. Again, this computation block corrects the VGA gain, which was

set to a switched gain with 5 dB error range, to the final gain with 1 dB error. Figure

5-29 shows simulation results for sine wave signals, with lot swept from 500 nA (-6.2 dB

from Irer) to 2 CLA (5.8 dB from Irer). The simulated control current IC2 is plotted in the







84



black curve while the ideal curve is drawn in gray. The largest error between the


simulation and the ideal is -0.36 dB when lot is bigger (5.8 dB) than herf with -3 dB


switched gain. Figure 5-30 shows the simulation results for short training symbol signals,


with lot swept from 300 nA (-6.5 dB from Irer) to 1.2 CLA (5.6 dB from Irer). In this


simulation, the largest error is -0.4 dB when lot is smaller (-6.5 dB) than herf with 27 dB


switched gain. Figure 5-3 1 depicts the step response of the computation block, which


demonstrates that the current-mode operation in weak inversion should meet the settling


time constraints of the system.

DC Response DC Response
(a) :(2.561e-07 sqrt((1.0246e-06 /' IS( (b) ::(4.5183e-07 sqrt((1.0246e-3 6 / IS
4001n : /150/102 700n .: /Il50/Ic2





Irr rrorn
100n .. I 3 0 . . .


500n 1.30u 2.10u
DC Response
(c) :(7 9359e-07 sqrt((1 0246e-06 / IS
1.20u ': /1150/102
1.1lu






500 n .... ...........~~...... I l . .' .'


500n 1.30u 2.10ru


500n i 1.30u 2.10u
I01
DC Response
(d) -: (1.397e-06 sqrt((1 0246e-06 / IS(
2.10~u 1: /Il50/Ic2
..0u 1-i0.27 dB error






5.00n13u .0
1.1R01


Figure 5-29. DC simulation results of the computation block for sine wave signal with the
switched gain of (a) -3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB












DC Response
(a) ;: (2.561e-07 sqrt((6.307e-07 / IS
400n an /Il50/Ic2


DC Response
(b) : (4.sise-07 sqrt((e.3B7e-07 7 / s(
700n `: /Il50/~Ic2


600n

500 nIref

400 ------------- *****C1(7dB)
-0.13 dB error


300[2n 800lln 1.30iu

DC Response
(d) ;: (1.397e-B6 sqrt((e.307e-ov / IS(



2.10u :/l5/2








300n 750n 1.2u
I01


...... c1 (-3dB)



-0.21 dB error


300 n



200~n



100ln


300In 800n 1.30iu

DC Response
(C) ;: (7.936e-07* sqrt((6 307e-07/ IS(
1.30u 1: /1150/Ic2
-0.22 dB error









300n 750n 1.2u
101


Figure 5-30. DC simulation results of the computation block for short training symbol
signal with the switched gain of (a) -3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB

Transient Response


-.; /Il50l/Ic2
.,: /V9/PLUS




." "


1.R0u

900n

800~n

700n

600n

500n

40~n

300n


0.01.0u 2.0Iu
time (s )


Figure 5-31i. Transient simulation result (step response) of the computation block


The proposed AGC circuit in Figure 5-18 is simulated using transient response for


both sine wave and short training symbol signals. Given a settling time requirement of 7









short training symbol times, the implemented AGC circuit uses symbol time duration

from t3 through t7 (5x0.8 = 4 Cps). The initial gain for two-stage VGA is set to 12 dB.

The switched gain is selected during t4 and the final gain is adjusted during t6. Figure 5-

32 shows output signals with the final gain of (a) -4 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB,

where the switched gain of -3 dB for (a) and (b), and 7 dB for (c) and (d) are selected.

Simulation results with small sine wave inputs to get the final gain of (a) 15 dB,

(b) 20 dB, (c) 23 dB and (d) 28 dB are shown in Figure 5-33. Similar simulations with

short training symbol inputs are presented in Figures 5-34 and 5-35. From the simulation

results, it can be observed that the AGC circuit adjusts signals to the desired level with

gain error less than +1 dB through the actual gain range of -4 ~ 28 dB.

5.4.3 IC Measurement and Analysis

The proposed AGC circuit in Figure 5-18 was laid out using the TSMC 0.18Cpm

process with 6 metal layers. Figure 5-36 shows the full chip layout floor plan including

40 bonding pads. The total chip area including ESD (Electro-Static Discharge) bonding

pads is 2850 x 2850 Cpm, whereas the actual AGC circuit area is 750 x 750 pm. The die

photo of the fabricated AGC circuit is shown in Figure 5-37. The fabricated parts are

packaged in DIP40 (40-pin ceramic package).

The package samples were measured using a test board to get access to the

embedded test points. Figure 5-38 illustrates the test board design for the packaged AGC

circuit. The test board includes DIP switches for embedded test point selection and

input-output matching connectors. The selectable output buffer stage is also included in

the test board to provide matching with the 50 R test equipment. The test board shown

in Figure 5-39 was designed and built by the support of Conexant" Systems. A detailed

schematic of the test board is attached as an appendix.





1 dB


" Error


...~ Error


1.0u 2.~u
t me ( s i)


i II


1.


...,, ,,.1,,, .,,,,1,


~YYYYYYYYYYYYY


1,,,,, ,,,1,,, ,,,,,1, ,,,,,


j r ;r


| | 11| IIl l

:I .,j. 11. | | | | | | |
a I, a .... ... ... .....1.1


A:i (j.18j48u 1 7006)~ delta : (2n -bli4.BQm)

t3 t4 t5 t6 t7
1.90 12 dB7 7 dB 9 dB .-
(d)

1.50 L F" |I I



O 0 1.0mu dm20us 3.01 4.0u


. -4 dB


0 dB


1.00


1 Ou


2.Iu
m~e ( s


3.0 ~


4 OIu


A: IS.isa5llu
B: (3.19686u


1 busuq)
1.20004)
-: /Vop
- :12 dB


deltl:
slope:


1(.en
-133.3


-3 dB


-4YS.YUrrn
7M


2.00


1.50


1.00


0.49 dB


1.Tu


2.5u
me ( s


3.0a


4 Ou


A: (0.lobitou I toI14)
B: (3.19006u 1.20265)


aelu
slop


b
e


: 4n -0 0t.a9
i: -132.2?3M


7 dB


-: /Voo
~:12 dB1


4 dB


1.90


1.50


0.32 dB


3.00


4 O~u


Error = 0.29 dB


A 3.18398u 1.74-029)
AB: (3.1B298u 1.22338)


delta: (-in -516.9077m)
slope: 516.907M


Figure 5-32. Transient simulation results of the AGC circuit for sine wave signal with
final gain of(a) -3 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB


-: /Vop
2.00~ "12 dB -


1.50 ~ bili


.-3 dB


i :.1..Eror





































~~ Error


1 Ou 2.0u
ti;me ( s i)


.,
( || | | | |
| I I

, , 1 1 ,


| | | |

| II I II I
....... .1... ..'. .. "..'. .I.


AB: (3.1B~44444u 1.22857) sl~ope -259.9 1p6M)
t3 t4 t5 t6 t7

()1.802 12 dBnj 27 dB 28 dl~n~'

1.50 /


0. 0 0 .0 3 0 4 0
,.,time2.u. (.C s ) ~


1R 90 12 dB n-


(a)


- 17 dB -


-0.14 dB


1.50

1.10


1 Ou


2.0lu 3.
mre ( s)
3: (1 --4Y 10/m)
e: undefined


17 dB


4 Olu


A 3. 18Bd9u 1./310/)
AB: (3. 1B309u 1.23998)


in 1.80 12 dBn


-0.18 dB


1.50

1.20Z


1 Ou 2.lu
t~ime ( s


3 0


4 Olu


A 3. 1821u 1 73222)
B: (3.1B31u 1 24255)


delt@;
slope:


(ln~ -489I668m)
-4B9.668M


~12 dBn


27 dB


1.90


0.34 dB


1.50 S

1.10


3.0


4 Ou


Error = -0.35 dB


A; (3.18326u 1.72815)
B: 3. 1B512u 1.24822)


delta; (1.86115n -479.942rn)
slope: -257.873M


Figure 5-33. Transient simulation results of the AGC circuit for sine wave signal with
final gain of (a) 15 dB, (b) 20 dB, (c) 23 dB and (d) 28 dB


1= 5 dB .


../Error


20 dB~


)Error


23 dB