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Stress Modeling of Nanoscale MOSFET

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PAGE 1

STRESS MODELING OF NANOSCALE MOSFET By NIRAV SHAH A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE UNIVERSITY OF FLORIDA 2005

PAGE 2

Copyright 2005 by Nirav Shah

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This work is dedicated to my parents for their unconditional love and support, and without whom, I could not have achieved what I have.

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ACKNOWLEDGMENTS First and foremost, I would like to thank my advisor, Dr. Scott E. Thompson, for all the support, encouragement and assistance he has given me throughout my graduate studies, and for the opportunity to work with him in the SWAMP group. Despite being really busy, he always found time for his students to discuss research and other technical deliberations. I will always adore his innovative thinking and diligent commitment to research, which I tried to imbibe during my work tenure. I am also very grateful to Dr. Mark E. Law and Dr. William R. Eisenstadt for supporting my research activities and for their guidance and support as my supervisory committee. This research could not have been completed without the financial support of the Semiconductor Research Corporation and Applied Materials Inc. I would like to thank the University of Florida and Department of Electrical and Computer Engineering for giving me an opportunity to explore the wide horizons of the technical arena. I would like to thank the SWAMP group and all its members for their warm support during my research. I appreciate the efforts of Teresa Stevens for being an excellent program assistant. I am grateful to Russ Robison for his assistance to get me acquainted with FLOOPS and his continuous support thereafter. I would like to thank Ljubo Radic for being a good friend and helping me solve problems during my research work. I am especially thankful to Heather Randell, for her help all throughout my research work and then after to compile my thesis. I would like to thank Sagar Suthram, iv

PAGE 5

Guangyu Sun, Nidhi Mohta and Kehuey Wu for their availability for research related discussions. I thank my loving parents and each member of my family, without whose support and motivation, my achievements would have been incomplete. Last but not least, I would specifically like to thank all my roommates, friends, colleagues and teachers in the United States, and back home, for their overwhelming love and trust in my efforts, and for standing by me whenever I needed them the most. v

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TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................iv LIST OF TABLES ...........................................................................................................viii LIST OF FIGURES ...........................................................................................................ix ABSTRACT .......................................................................................................................xi CHAPTER 1 INTRODUCTION........................................................................................................1 1.1 History and Motivation...........................................................................................1 1.2 Strained Silicon Physics.........................................................................................3 1.3 Modifications in Conventional MOSFET Equation due to Strain..........................5 1.4 Summary.................................................................................................................6 2 SIMULATION MECHANICS.....................................................................................7 2.1 Basics of Engineering Mechanics...........................................................................7 2.2 Relationship between Stress and Strain..................................................................8 2.3 Software Approach To Engineer Stress................................................................10 2.3.1 ISE-FLOOPS Background.........................................................................10 2.3.2 How to use ISE-FLOOPS...........................................................................11 2.3.3 Computation of Mechanical Stress using ISE-FLOOPS............................11 2.3.4 Finite Element Method (FEM)...................................................................12 2.3.5 Boundary Conditions..................................................................................15 2.4 Material Parameter Sensitivity.............................................................................15 2.5 Summary...............................................................................................................17 3 STRESS GENERATION TECHNIQUES IN ADVANCED CMOS........................18 3.1 Types of Process Induced Stresses.......................................................................18 3.1.1 Thermal Mismatch Stress...........................................................................18 3.1.2 Intrinsic Stress............................................................................................19 3.1.3 Dopant Induced Stress................................................................................20 3.2 Biaxial Stress Generation Technique....................................................................20 3.3 Uniaxial Stress Generation Technique.................................................................23 vi

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3.4 Effect of Varying Geometrical Parameters...........................................................24 3.4.1 Critical Dimension Scaling.........................................................................25 3.4.2 Polysilicon Gate Scaling.............................................................................26 3.4.3 Effect of Buffer Layer on NMOS Channel Stress......................................27 3.4.4 Effect of Salicide........................................................................................28 3.5 Summary...............................................................................................................29 4 CASES OF TECHNOLOGICAL IMPORTANCE AND RELATED ISSUES.........30 4.1 Strained-Silicon-On-Insulator (SSOI)..................................................................30 4.2 Uniaxially Strained Device Issues........................................................................32 4.2.1 Effect of Varying Silicon Nitride Thickness..............................................32 4.2.2 Multiple Gate Structure..............................................................................34 4.2.3 Stress Relaxation Due to the Presence of STI............................................35 4.2.4 Stress Relaxation due to Contact Etching..................................................37 4.2.5 Effect of Raised Source/Drain in PMOS Device.......................................39 4.2.6 SOI vs Bulk Technology............................................................................40 4.2.7 Effect on Stress by Boron Doping in p-channel Devices...........................42 4.3 Prospective Stress Generation Techniques...........................................................44 4.3.1 Stress Variation Along the Device Width..................................................45 4.3.2 Stress Engineering by STI Depth...............................................................46 4.3.3 Stress Engineering by STI Width...............................................................47 4.3.4 Stress Dependence on STI Topology.........................................................48 4.3.5 Stress Dependence on STI Densification...................................................49 4.4 Summary...............................................................................................................49 5 SUMMARY, CONCLUSIONS, AND RECOMMENDATIONS FOR FUTURE WORK........................................................................................................................51 5.1 Summary and Conclusions...................................................................................51 5.2 Recommendations for Future Work.....................................................................56 5.2.1 3D Modeling...............................................................................................57 5.2.2 Additivity Issue..........................................................................................57 5.2.3 Stress Generation due to Thermal Mismatch and Material Growth...........58 5.2.4 Better Understanding of Novel Stress Generation Techniques..................58 LIST OF REFERENCES...................................................................................................60 BIOGRAPHICAL SKETCH.............................................................................................65 vii

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LIST OF TABLES Table page 2-1 Material Parameter Sensitivity Results....................................................................16 2-2 Material Properties at Room Temperature...............................................................17 3-1 Longitudinal and Transverse Piezoresistance Coefficients Evaluated for Standard Layout and Wafer Orientation (Units of 10 -12 cm 2 dyne -1 ).......................21 3-2 Effect of Salicide on NMOS Channel Stress...........................................................29 viii

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LIST OF FIGURES Figure page 1-1 Prediction by Dr. Gordon E. Moore, also known as Moores Law............................1 1-2 Transistor size and technology trend..........................................................................2 1-3 Gate oxide scaling with the technology generations..................................................2 1-4 Supply voltage scaling with the technology generations...........................................3 2-1 Stress components acting on an infinitesimal cubic element.....................................8 2-2 Flowchart of FEM stress solving algorithm in a composite structure......................13 3-1 Lattice contraction due to boron atom and lattice expansion due to germanium atom..........................................................................................................................20 3-2 MOSFET schematic device cross-section (standard layout)....................................21 3-3 Steps in creating biaxially strained silicon film atop SiGe layer.............................22 3-4 Traditional approach to enhance device performance illustrating biaxial tensile stress in MOSFET channel.......................................................................................22 3-5 IBM technology to introduce uniaxial longitudinal stress in CMOS devices..........23 3-6 Intels strained silicon technology............................................................................24 3-7 Longitudinal channel stress component values for different critical dimensions for oxide, nitride and no spacers..............................................................................25 3-8 Effect of scaling polysilicon gate thickness on NMOS channel stress....................27 3-9 Effect of increasing buffer (liner) layer thickness on NMOS channel stress...........28 4-1 Stress relaxation in 200 A strained-silicon on insulator and on SiGe for different island sizes.................................................................................................31 4-2 Effect of increasing silicon nitride thickness on channel stress components...........33 ix

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4-3 Stacked gate structures generated by ISE-FLOOPS for different silicon nitride cap thicknesses.........................................................................................................34 4-4 Effect of varying space between adjacent gates for different Si 3 N 4 cap thicknesses for NMOS, and different spacer sizes for PMOS.................................35 4-5 Nested NMOS structure illustrating the stress relaxation due to the presence of STI............................................................................................................................36 4-6 Nested PMOS structure illustrating the stress relaxation due to the presence of STI............................................................................................................................37 4-7 Stress relaxation due to contact holes in NMOS strained silicon device with 45 nm L gate 140 nm gate thickness and 80 nm nitride cap thickness...........................38 4-8 Stress boosting in PMOS by increasing SiGe step height for 45 nm gate length devices......................................................................................................................39 4-9 Effect of varying SiGe depth in SOI vs bulk silicon devices...................................41 4-10 Effect of scaling boron concentration for different channel lengths, 0.5 m source/drain length and 0.12 m junction depth......................................................43 4-11 Stress variation along the device width in HARP STI stress engineering technique..................................................................................................................45 4-12 Effect of varying STI depth on channel stress: for free surface and for polysilicon on top.....................................................................................................46 4-13 Effect of varying STI width on channel stress for different transistor widths.........47 4-14 Stress dependence on STI topology.........................................................................48 4-15 Stress dependence on HARP STI intrinsic stress.....................................................49 x

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Abstract of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Master of Science STRESS MODELING OF NANOSCALE MOSFET By Nirav Shah December 2005 Chair: Scott E. Thompson Major Department: Electrical and Computer Engineering Process-induced strained silicon device technology is being adopted by the semiconductor industry to enhance the performance of the devices in the nanometer realm. A prime area of research is to explore different ways to maximize the desirable strain in the device channel. Difficulties also exist with scaling strain to future technology generations. The need of the hour is to simulate and understand the front-end process closely to attain the required strain in the channel and this can be done using Finite Element Method (FEM). ISE-FLOOPS uses StressSolve solver to calculate the stress by solving for Hookes Law. The stress is a function of different parameters like geometry of the structure, boundary conditions, material parameters, process flow, etc. A range of issues such as stress dependence on critical dimension scaling, stress relaxation due to STI and contact hole etching that restrict the scalability of device structures for uniaxial and biaxial process induced stress have been addressed and explained with the help of simulation results. The detrimental effects of dopant introduced tensile stress in the pxi

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channel devices have been highlighted. This work proposes some novel stress engineering techniques like using HARP STI to induce a transverse stress during the CMOS fabrication process. xii

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CHAPTER 1 INTRODUCTION In this thesis, the understanding and issues of MOSFET performance enhancement by using strained silicon devices will be discussed. This will be achieved by exploring the necessity of using mechanical strain as a vector for performance enhancement. 1.1 History and Motivation For the past four decades, geometrical scaling of the transistor dimensions-Moores Law [Moo65]-has dominated the semiconductor industry for greater transistor density and the corresponding transistor performance enhancement. The basic proposal by Dr. Gordon E. Moore was that transistor density on an integrated circuit will approximately double every two years. Figure 1-1: Prediction by Dr. Gordon E. Moore, also known as Moores Law [Moo65] 1

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2 Since then, much innovation in the areas of transistor scaling and usage of new materials to follow the Moores Law have been accomplished which has led to the present day MOSFETs. Figure 1-2: Transistor size and technology trend [Tho04c] With the scaling of the feature size, the supply voltage and gate oxide thickness also scaled to a certain extent, to fabricate low power high-speed circuits. Figure 1-3: Gate oxide scaling with the technology generations [Tho04c]

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3 Figure 1-4: Supply voltage scaling with the technology generations [Tho04c] The exponential progress predicted by Moores Law stayed firm on its path for over four decades, but it can not continue the trend forever [Moo03]. As the industry enters the nanometer regime, where the transistor gate length drops down to 35 nm and the gate oxide thickness to 1 nm, physical limitations such as off-state leakage current and power density pose a potential threat to enhance performance by simple geometrical scaling, and the industry needs a new scaling vector. Front-end process induced stress has thereby emerged as the new scaling vector for the current 90 nm node and the future technologies too [Tho04a, Tho04b]. Stress improves performance by the mobility enhancement, which fundamentally results from alteration of electronic band structure of silicon [Moh05]. 1.2 Strained Silicon Physics The switching speed of an ideal transistor can be increased primarily by two ways: physical gate length scaling and carrier mobility enhancement. Strained silicon is a technology, which increases the switching speed solely by enhancing the carrier mobility. The carrier mobility is given by [Moh05]:

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4 *mq where, 1/ = scattering rate, m* = conductivity effective mass (1-1) The carrier mobility is enhanced by strain by reducing the effective mass and/or the scattering rate. It is accepted now that the electron mobility is enhanced by both the phenomena [Yua01], while for holes, only mass change due to band warping is understood to play a significant role [Tho04d] at the current stress levels in production. The mobility is directly related to the carrier velocity and applied external electric field E by: = .E (1-2) It can be seen that increasing the carrier mobility increases the velocity, which is directly proportional to the switching speed of the device. For electron transport, the conduction band consists of six equal energy degenerate valleys at room temperature. Upon application of strain, two states occupy lower energy levels, while the remaining four occupy the higher one, thereby removing the degeneracy between the valleys. The difference in the energy levels causes repopulation of the electrons, thereby reducing their net effective mass [Moh05]. Due to band splitting, the backscattering of the electrons is reduced, thereby enhancing the velocity. The reduction of backscattering implies the increase in average lifetime of a carrier before it is knocked-off during its course. The combination of both these effects leads to a net increase of electron mobility improvement in strained silicon devices. For hole transport, the valence band structure of silicon is much more complex. The valence band comprises of three bands: heavy-hole, light-hole and split-orbit bands [Ran05]. Application of favorable strain along [110] direction causes high band warping. When the strain is applied, the degeneracy is removed between light-hole and heavy-hole

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5 bands, and holes fill-up the light-hole-like band [Moh05]. This reduces the effective mass, which is the prime contributor to hole mobility enhancement under strain. For the current stress levels (up to 1GPa), hole intervalley scattering is not significantly reduced since the bands splitting needs to be comparable to the optical phonon energy to considerably suppress the scattering effects. The main advantage of uniaxial compressive stress to the biaxial counterpart is that the hole mobility enhancement does not degrade at high vertical fields where commercial MOSFETs operate [Tho04b]. The methods of both uniaxial and biaxial state-of-the-art stress generation techniques are discussed at length in chapter 3 and chapter 4. Strained silicon technology comes with its own set of problems, which need to be addressed aptly. The main issues include the threshold voltage shifts [Lim04] and dislocation loops. The latter will have to be addressed by changing thermal cycles and controlling growth. 1.3 Modifications in Conventional MOSFET Equation due to Strain The classical MOSFET equations for a long-channel device operating in linear and saturation regions are given by: 22)(dsdsTgsoxlindVVVVLWCI (1-3) 2)(2TgsoxsatdVVLWCI (1-4) In the nanometer realm, the carrier transport in the device becomes ballistic and Equation (1-4) becomes dependent on the carrier velocity as [Tho04c]: TgsoxsatdVVWCI )0()( (1-5)

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6 Hence, it can be seen that the square-law relationship approaches linearity in a ballistic model. In the above equation, <(0)> is the average carrier velocity at source which is related to the mobility by Equation (1-2). As the channel length approaches zero, <(0)> is the unidirectional thermal velocity T which is given by [Tho04c]: *2mTkLBT (1-6) The drain current in the nanoscale limit can now be equated as: TgsLBoxsatdVVmTkWCI*)(2 (1-7) Therefore, it is obvious that improving the mobility by application of strain enhances the performance of the device. 1.4 Summary This chapter started with the brief introduction of MOSFET scaling trends and the motivation behind the work presented in this thesis. Moores Law was discussed along with the scaling trend of different device parameters such as the gate oxide and the supply voltage. This was followed by the understanding of the necessity of adopting strain as the new scaling vector and the basics of strain physics to assist performance enhancement. Finally, the implications of strain on the classical MOSFET equations in the nanotechnology devices were discussed. Chapter 2 will discuss of the simulation mechanics and strain engineering to generate the desirable strain in the device channel.

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CHAPTER 2 SIMULATION MECHANICS 2.1 Basics of Engineering Mechanics Since the thesis is primarily concentrated around stress and strain in MOSFETs, it is essential to understand the basics of engineering mechanics like stress, strain and mechanical properties. When a force is applied on a fixed body, it deforms in its shape. If the deformation is small enough, it returns to its original shape once the applied force is removed. This is described as the linear elastic behavior of the body and the deformation is considered to be within the elastic limit. Stress () is defined as force per unit area A acting on the surface of a solid. Its unit is Pascal (Pa). AFAlim0 (2-1) Stress is a vector which has two components: normal and shear component. Normal Stress: Force per unit area, acting normal to A is called the normal stress . Shear Stress: Force per unit area, acting tangential to A, i.e. along the plane of the surface, is called the shear stress . Shear stress has tearing effect on the plane of the body. Stress that acts to shorten an object is called compressive stress while the one that acts to lengthen an object is called tensile stress. As a rule of thumb, tensile stresses are considered positive and compressive stresses as negative. 7

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8 Strain is defined as change in length of an object under force, compared to its original length. It is unit less quantity. Again, corresponding to normal and shear stress, there are normal and shear strain components. To understand the stresses and strains in depth, consider an infinitesimal cube as shown in figure 2-1. The figure shows normal and shear stresses in x, y and z directions acting on different planes of the cube. + y zy zx zz yy yx yz xx xz xy +z +x Figure 2-1: Stress components acting on an infinitesimal cubic element [Ran05]. The first subscript identifies the face on which the stress is acting, and the second subscript identifies the direction. The ij components are the normal stresses while the ij components are the shear stresses. 2.2 Relationship between Stress and Strain Stress and strain are related to each other by the material property called Youngs Modulus E as E = /. Hence, it is obvious that Youngs modulus defines the stiffness of the material. Normal forces are resisted by the bodys bulk modulus and shear forces are resisted by the bodys shear modulus, which determines how much a solid will compress under external pressure.

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9 Poisson ratio , one more important property of the material, is the ratio of lateral contraction strain to longitudinal extension strain in the direction of the tensile stress. After the basic understanding of the mechanics concept, we can extrapolate our discussion to behavior of a body under force. Conceptually, any solid can be considered as a spring with certain stiffness. Consider a weightless spring suspended from ceiling and the other end is free to move. When a weight is suspended at the free end of the spring, it extends by a certain amount x depending the weight and stiffness of the spring. These quantities can be related to each other by mathematical expression of Hookes Law which states f = k.x, where f is the force applied (in our case, weight of object generates a force at the free end), k is the stiffness of the spring and x is the extension/displacement. Now, if the force applied is within the elastic limit, the spring reverts back to its original shape when the weight is removed. Also, in a system under equilibrium, the forces at all nodes are balanced, which means that summation of all forces in a system under equilibrium is zero. So when a force is applied on the spring, net forces acting on the spring are balanced when the spring displaces by a certain amount. Hookes Law also states that strain can exist without stress. To illustrate this phenomenon, consider an elastic band in relaxed position. When it is stretched along its length, stress is applied in y-direction whereas there is no externally applied stress along x and z-directions. The band not only extends along y direction, but also contracts along x and z-directions, which means there is strain in all the three directions when stress is applied in just one direction. After releasing the band, it comes back to its original shape if the applied forces are in elastic limit.

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10 The thesis work of Randell [Ran05] explains the concepts of shear and normal stresses and strains at length and their relationship in equilibrium condition. The stress matrix in static equilibrium is given by: zxyzxyzzyyxxtotal where, = normal stress component, = shear stress component (2-2) Similarly, the strain matrix in equilibrium is given by: zxyzxyzzyyxxtotal where, = normal strain component, = shear strain component (2-3) 2.3 Software Approach To Engineer Stress A software-based approach is adopted to engineer and maneuver the stress generated in the MOSFET channel, with an ultimate goal of enhancing the device performance. This is the common and most effective approach adopted in the semiconductor industry to model process-induced stress. 2.3.1 ISE-FLOOPS Background FLOOPS (Florida Object Oriented Process Simulator) is a 1D, 2D and 3D process simulator, which simulates all standard process simulation steps like diffusion, oxidation, etching etc. [ISE03]. FLOOPS is a C ++ based simulation program, which uses physical models to describe all the processing steps. There is a scripting capability called

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11 Alagator, which can be used to simulate all user-defined processing steps. The ISE version of FLOOPS, used to obtain all the results in this work, is based on the 2000 and 2002 releases of FLOOPS written by Dr. Mark Law and coworkers at University of Florida. 2.3.2 How to use ISE-FLOOPS ISE-FLOOPS accepts sequence of commands at the command prompt or composed in a command file. The process flow is simulated by issuing a sequence of commands that correspond to the individual process steps. The command file is first checked for syntax by a pre-compiler and then the commands are executed sequentially. The pre-compiler proves to be a great boost to enhance the execution speed since it checks for syntax at the beginning of execution. FLOOPS is written as an extension of tool command language (Tcl), so all Tcl commands and functionalities are supported by the software. A flexible way to use ISE-FLOOPS is to run the command file through the job-scheduler called GENESISe. The latter is added to ISE framework to make the usage of ISE TCAD tools easier and user-friendly. It simplifies and organizes the handling of complex projects by an intuitive Graphical User Interface (GUI) environment. The GENESISe scheduler forms Design of Experiments (DoE) for the jobs and allows monitoring the simulation jobs running in a project. The user can initiate a bunch of jobs for simulation and GENESISe enqueues the tasks to be executed sequentially. 2.3.3 Computation of Mechanical Stress using ISE-FLOOPS FLOOPS supports four mechanical models for the computation of mechanical stress: purely viscous, viscoelastic, elastic and plasticity. All simulations in this work are performed using elastic model. This is a valid approximation since the displacements

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12 caused due to the stresses are in the linear elastic limit. The approximation was asserted by setting the viscosity of the materials to a high value. The tensor equations can be split into two parts: deviatoric and dilatational [ISE03]. The dilatational trace describes the material behavior in the case of a pure volume change while the deviatoric part describes an arbitrary deformation but without changing the volume. In elastic model, the deviatoric part is calculated as jklkG''2 where, G = shear modulus (2-4) The dilatational part is calculated as kkkkkkpK33 where, p = hydrostatic pressure, K = bulk modulus (2-5) Traversing the mesh, at each step, the equation is solved for balance of forces given by [Cea04]: ,0ijijF (for i = x, y, z) (2-6) where, denotes the stress and F i denotes the total external forces generating the stress. These forces include the intrinsic film stress, thermal mismatch stress and stress induced due to material growth [Ran05]. 2.3.4 Finite Element Method (FEM) The physical interpretation of FEM is the breakdown of a structural system into components (elements) and reconstruction by the assembly process [Gud04]. This method is extremely useful for solving a complicated structure by dividing it into small elements by discretization process. The behavior of the overall structure can be estimated by solving the differential equations of individual elements. In 2D simulation, the z-direction is assumed to be infinite and the structure is sub-divided into triangles, while for 3D simulations, the element is a tetrahedron. A mesh is formed by the collection of all

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13 these 3-node triangles, and each node in the mesh is assigned a number along with a set of coordinates (x, y). For arbitrary structures, stresses are not in equilibrium when described externally. The stressSolve command solves for Hookes Law (f=k*x) at each element leading to global equilibrium condition. The solver traverses through all nodes in the mesh, calculating stiffness and displacement, which relates to strain and stress at each element. In a composite structure, like the one shown in figure 2-2, the normal force applied is calculated from intrinsic stress by integrating the defined stress over the area. The stiffness matrix at each node is calculated from two more matrices: B-matrix and D-matrix. B-matrix is a function of geometry of the element and the nodal coordinates of the given element, while D-matrix purely depends on the material properties. Create B T Create BCreate Dapplied force matrices matrices matrices Figure 2-2: Flowchart of FEM stress solving algorithm in a composite structure. In equilibrium condition, for an element triangle with area the elemental stiffness k e is calculated in discretized form as [Gud04]: k e = Area element .B T .D .B (2-7) The B-matix, which is a function of nodal coordinates, is given by [Zie89]: k 1 E 1 k 2 ,E 2 Calculate k 1 ,k 2 more nodes in mesh matrices Newtonian solver all nodes traversed Create global kmatrices for both ma t e r i a l s Calculate at Calculate x at Calculate at each node each node each node

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14 jiijikkikjjkijkijkjiikkjyyxxyyxxyyxxxxxxxxyyyyyyB000000.21 (2-8) The D-matrix, for plane strain, is given by: )1.(2)21(00011011)21).(1()1.(ED (2-9) The plane strain approximation for 2D simulations assumes that xz = yz = zz = 0, but stress in z-direction is not zero. Here, we assume an infinitely long structure along z-direction, hence the strain in z-direction approaches zero [Rue97] To compensate for the 3-D behavior in a 2-D domain, the 2-D strain must be multiplied by a factor of (1 + ) [Ran05]: 01zzyyxx (2-10) In equation (2-7), 2. represents elemental volume in 3D and area in 2D. After obtaining the stiffness values, displacement at each node is calculated by solving Hookes Law. Across the interface of the two materials, strain is constant and thereby, displacements at each node in adjoining material are calculated. The elemental strain is related to elemental displacement by: e = B x e (2-11)

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15 2.3.5 Boundary Conditions Understanding boundary conditions is imperative while using FEM. The reflecting boundary conditions were assumed in all the simulation cases. This is a valid approximation if the boundaries are defined considerably far from the channel area, to avoid any effect of the boundaries on the channel stress. In the actual environment, the boundaries of a semiconductor wafer are free, but to simulate using free boundary conditions for a single device, the source/drain diffusion regions need to be exceedingly large, i.e. boundaries must be too far from the channel. This unnecessarily increases the complexity and size of the mesh as well as the simulation time. The source/drain regions in the simulations were chosen large enough to have no effect of the boundary conditions on the channel stress. The grid setting in the mesh is an important aspect of any FEM based simulator. All simulations in this work are carried out using mgoals engine, which is an adaptive engine to set the grid as each processing step is simulated. Initially, the grid in the entire structure was set in a coarse fashion, which gave significant offset from the expected results. Then after, the grid density in the desired regions, viz. the channel and the source/drain, was increased till the stress became insensitive to the grid. Of course, the trade-off with increasing the grid density is the computation time. A more detailed explanation of the FEM is given by [Ran05]. The reader can refer to ISE TCAD Release 9.0 manual [ISE03] for a detailed working and description of all ISE-FLOOPS process models and other TCAD subsidiary tools. 2.4 Material Parameter Sensitivity In this work, the sensitivity of the channel stress to the material parameter variations was observed. Longitudinal tensile stress in NMOS is generated by

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16 densification of silicon nitride layer on NMOS [Tho04a]. Table 1 shows the summary of the results obtained by skewing various parameters. In all the results presented in this work, xx represents longitudinal component and yy represents out-of-plane component of stress. Also, the positive values denote tensile stress while negative ones denote compressive. We hereby start with the following parameters: E si = E poly = 180 GPa; E SiN = 300 GPa; Eoxide = 65.8 GPa; Si = Poly = 0.28; SiN = 0.1471; oxide = 0.2 The stress for the above stated parameters is: xx = 427 MPa, yy = -412 MPa The material parameters are highly process dependent and so are subject to change. The sensitivity of the channel stress on the parameters of each material was studied, and it was inferred that variations of material parameters do not alter the stress heavily. However, the silicon nitride parameters do affect the stress and changes the calculations significantly. The results obtained by the above mentioned sensitivity test are listed in Table 2-1. Each row suggests changing the listed parameter, while keeping all other parameters constant as above. The variations of the stress from the above mentioned results were studied. Table 2-1: Material Parameter Sensitivity Results (skewing the individual parameters, while keeping all others constant as stated above) Parameter xx (MPa) yy (MPa) Observation E si = E poly = 110 GPa 414 -412 No effect E si = 169 GPa, E poly = 164 GPa 431 -382 No effect Si = Poly = 0.222 419 -420 No effect E SiN = 160 GPa 160 -612 Significant effect, yy value unreasonably high SiN = 0.23 357 -352 Acceptable range oxide = 0.15 425 -408 No effect

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17 After significant research on the material parameters, the following values were found acceptable, which were used for most of the simulations in this work, unless specified. The mobility calculations from stress results obtained from the acceptable parameters were checked against the E-test published data and both the results matched within a small error margin. Table 2-2: Material Properties at Room Temperature [Mat88, FCG66, Yin03] Material Youngs Modulus E (GPa) Poisson ratio Silicon along [110] 169 0.222 Silicon along [111] 186 0.222 Polysilicon 164 0.222 Germanium 139 0.25 Oxide 72 0.15 Silicon Nitride 300 0.23 Tungsten 409 0.28 Si 0.83 Ge 0.17 163.7 (linearly interpolated between Si and Ge) 0.222 (same as that of Si) 2.5 Summary This chapter starts with the basics of engineering mechanics, the concept of stress and strain, and their components. The linear elastic property of solids is explained by an example of a spring. This is followed by the explanation of Hookes Law, and its mathematical interpretation. Next, the details of FLOOPS are discussed highlighting its key features and tools. The working of FEM, boundary conditions and approximations used for 2D simulations are explained. Finally, the preliminary simulations to observe the stress sensitivity to material properties are discussed along with observations. In Chapter 3, the stress generation techniques in leading edge advanced CMOS will be discussed in depth along with more simulation cases.

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CHAPTER 3 STRESS GENERATION TECHNIQUES IN ADVANCED CMOS In the nanometer regime, biaxial stress has been the conventional method to strain the MOSFET channel. Recent studies in the field of uniaxial process-induced strain have revealed significant advantages over its biaxial counterpart. In this chapter, the methods to induce both the types of strain in the MOSFET channel will be discussed. 3.1 Types of Process Induced Stresses The residual stresses present in thin films after deposition can be classified into two parts: 1) thermal mismatch stress and 2) intrinsic stress. Residual stresses will cause device failure due to instability and buckling if the deposition process is not controlled properly. 3.1.1 Thermal Mismatch Stress Thermal mismatch stress occurs when two materials with different coefficients of thermal expansion are heated and expand/contract at different rates. During thermal processing, thin film materials like polysilicon, SiO 2 silicon nitride expand and contract at different rates compared to the silicon substrate according to their thermal expansion coefficients. The thermal expansion coefficient, T is defined as the rate of change of strain with temperature. Its unit is microstrain/Kelvin (/K) [Sen01]. d T dT (3-1) The thermal mismatch strain generated into substrate upon skewing the temperature by T, is given by 18

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19 TsubT (3-2) The thermal mismatch strain in film is given by [Fre03]: TTsTfmismatchf., (3-3) where Tf and Ts are thermal expansion coefficients of film and substrate respectively. Finally, the thermal mismatch stress is related to strain by: mismatchffmismatchfE,,.1 (3-4) where is the Poissons ratio and E f is the Youngs modulus of the film. 3.1.2 Intrinsic Stress Intrinsic stress is a type of residual stress, generated due to factors such as deposition rate, thickness and temperature. During deposition, thin films are either stretched or compressed to fit the substrate on which they are deposited. After deposition, the film wants to be smaller if it was stretched earlier, thus creating tensile intrinsic stress, and similarly compressive intrinsic stress if it was compressed during deposition. The intrinsic stress generated due to this phenomenon can be quantified by Stoneys equation by relating the stress to the substrate curvature as [Fre03]: fSiSiSifhhRE..1.6 (3-5) where E Si and Si are Youngs modulus and Poissons ratio of Silicon, h Si and h f are substrate and film thickness, and R is the radius of curvature of the substrate.

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20 3.1.3 Dopant Induced Stress When a dopant atom is introduced in silicon substrate through ion implantation or diffusion, a local lattice expansion or contraction will occur depending on the varying atomic sizes and bond lengths of the atoms [Ran05]. Figure 3-1: Lattice contraction due to boron atom and lattice expansion due to germanium atom [Ran05]. Figure 3-1 illustrates the lattice contraction and expansion for boron and germanium atoms doped into silicon substrate. The stress generated due to boron doping is a case of technical importance, which will be studied with the understanding of simulation results in the next chapter, while the biaxial stress generated due to SiGe will be discussed in the following sections. 3.2 Biaxial Stress Generation Technique A widely adopted method to introduce wafer-based biaxial stress to enhance CMOS performance is practiced by growing a silicon film atop relaxed SiGe virtual

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21 substrate. Due to the lattice mismatch between Si and Ge atoms, tensile biaxial stress is generated in Si film, which enhances the performance of NMOS and PMOS, as can be seen from Table 3-1. It can be seen from the piezoresistance coefficients of Si for standard layout and wafer orientation, that NMOS performance (electron mobility) is enhanced by uniaxial longitudinal tensile and out-of-plane compressive stress (figure 3-2), while PMOS performance (hole mobility) is enhanced by uniaxial longitudinal compressive stress. Interestingly, both NMOS and PMOS performance is enhanced by biaxial tensile stress. Table 3-1: Longitudinal and Transverse Piezoresistance Coefficients Evaluated for Standard Layout and Wafer Orientation (Units of 10 -12 cm 2 dyne -1 ) [Tho04b] <100> <110> Polarity ll ll N or P 11 12 ( 11 + 12 + 44 )/2 ( 11 + 12 44 )/2 N-type -102 53.4 -31.6 -17.6 P-type 6.6 1.1 71.8 -66.3 Figure 3-2: MOSFET schematic device cross-section (standard layout) When a film is grown/deposited on a substrate, the mismatch strain between the two layers due to the difference in their lattice coefficients is given by [Jai96]: subfilmsubmismatchaaa (3-6)

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22 were a sub and a film are the lattice constants of the substrate and heteroepitaxy film. The stress in the layer is given by [Jai96]: mismatcho 112 (3-7) where is the shear modulus of elasticity and is the Poissons ratio. When a silicon film is deposited on SiGe buffer layer, the film is forced to adopt the greater lattice constant of the SiGe, hence the Si film is under biaxial (longitudinal and transverse) tension, whereas it exhibits an out-of-plane compressive component. This effect is well illustrated in figure 3-3 and figure 3-4. Figure 3-3: Steps in creating biaxially strained silicon film atop SiGe layer Figure 3-4: Traditional approach to enhance device performance illustrating biaxial tensile stress in MOSFET channel [Boh03]

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23 Figure 3-4 shows the traditional approach of generating biaxial tensile stress in MOSFET channel to enhance device performance. It illustrates the longitudinal and transverse tensile stress components in the silicon channel on graded SiGe layer. 3.3 Uniaxial Stress Generation Technique Uniaxial process strained silicon is being adopted in nearly all high-performance logic technologies [Tho04b]. Ito et al [Ito02] investigated channel stress by introducing a tensile nitride capping layer on the device structure. As a result, the channel stress dependent on the polysilicon gate and spacer dimensions. A predominant method of introducing uniaxial longitudinal tensile stress is by deposition of CVD silicon nitride film on the device structure. This enhances electron mobility, thereby improving NMOS performance. IBM incorporates compressive silicon nitride capping layer to generate uniaxial longitudinal compressive stress in PMOS channel. With the state-of-the-art processing technology, up to 1.4 GPa process induced tensile stress is generated inside SiN film for NMOS while up to 3.0 GPa compressive stress has been exhibited for PMOS [Bay05]. Figure 3-5: IBM technology to introduce uniaxial longitudinal stress in CMOS devices [Moh05]

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24 Figure 3-5 portrays dual stress liner process architecture with tensile and compressive silicon nitride capping layers over NMOS and PMOS respectively. Similarly, Intels technology also implements tensile Si 3 N 4 (silicon nitride) capping for nchannel devices. The p-channel device performance is enhanced by using selective SiGe layer as source/drain regions (figure 3-6). The lattice mismatch in the heterolayer compresses the silicon lattice, which consequently compresses the device channel. For 17% Ge concentration, a compressive stress of 1.4 GPa is generated inside the SiGe layer [Bay05]. All simulations in this work are carried out by modeling the lattice mismatch stress as the intrinsic stress and then balancing the forces to evaluate the channel stress. Figure 3-6: Intels strained silicon technology [Boh03] 3.4 Effect of Varying Geometrical Parameters The effect of varying geometrical parameters on channel stress and thereby on carrier mobility has been an interesting research topic in strained-silicon nanoscale devices. The work by Pidin et. al. [Pid04] highlights some of these effects by front-end

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25 process-simulations. An in depth review of these cases of technological importance are explained in this section. 3.4.1 Critical Dimension Scaling The most important parameter that scales with each technology generation is the critical dimension of the physical gate. The channel stress increases as the gate length is scaled since the channel is in closer proximity of the tensile capping Si 3 N 4 layer for smaller critical dimensions. For the current 90-nm node with the standard 140 nm gate thickness, 80 nm tensile SiN cap and nitride spacers, the simulated channel stress component values are xx =353 MPa, yy =276 MPa. The trend of future nodes can be seen from figure 3-7, assuming all other dimensions remain unchanged. Figure 3-7: Longitudinal channel stress component values for different critical dimensions for oxide, nitride and no spacers.

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26 It can be seen that for oxide spacers, the channel stress is lower than for the nitride spacers because tensile nitride cap relaxes as it pushes against the softer oxide spacers while balancing the forces. This causes lower stress to be transferred into the channel. The nitride film is able to transfer stress to the channel because an edge-force is developed as the film goes over the spacer and gate geometry [Cea04]. An important observation from the results is that it is difficult to strain long-channel devices compared to their short-channel counterparts using tensile nitride capping layer. This is an important consideration the circuit designer should take into account while designing for optimum circuit performance. 3.4.2 Polysilicon Gate Scaling With every technology node, the aspect ratio (ratio of length to height) of the polysilicon gate has increased since thicker gates yield higher channel stress for n-channel MOSFETs. An interesting trend observed while scaling the gate thickness is that beyond a certain value, increasing the aspect ratio is not beneficial. Figure 3-8 illustrates the issue. The graph shows that increasing the aspect ratio initially assists in boosting the stress transferred into the device channel from tensile nitride cap, but beyond 150 nm gate thickness, the stress rolls off and remains unchanged. It can be concluded that increasing gate thickness beyond this value only increases the process complexity and deteriorates device performance due to problems like fringing fields. The current 90-nm technology devices have a gate thickness of 100-140 nm. One more interesting observation from the graph is the effect of roll off point for devices without spacers. This case can be understood as a device with overall smaller gate length. The stress slope is steeper initially, but it rolls off at a prematured gate thickness of ~100 nm compared to

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27 the geometry with spacers In addition, the maximum stress extracted at this value is lower than the spacer case. Figure 3-8: Effect of scaling polysilicon gate thickness on NMOS channel stress 3.4.3 Effect of Buffer Layer on NMOS Channel Stress A common practice to reduce the font-end process generated defects is to use an unstressed thin silicon nitride buffer film over the structure. This buffer (liner) film, if not properly deposited, proves to be detrimental to the channel stress in NMOS. The tensile nitride capping layer needs to be in close proximity to the substrate (ideally directly onto the substrate) to stress the device channel. Figure 3-9 reveals the reduction in longitudinal stress upon increasing the liner thickness. Similarly, the out-of-plane compressive stress component, which is also significant in improving n-channel device performance, is reduced upon depositing thicker liner layers.

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28 Figure 3-9: Effect of increasing buffer (liner) layer thickness on NMOS channel stress 3.4.4 Effect of Salicide Salicides are essential for good contacts with the device terminals. Since salicides are of different material than silicon, it is worth exploring the effect of salicide on the channel stress. Modern process technologies have nickel salicide (NiSi) for the contacts whereas formerly, cobalt salicide (CoSi) was used. Both the salicides have the same material properties (Youngs modulus = 161 GPa, Poisson ratio = 0.33) [Lie03, Hsi92]. Salicide thickness can range from 50 A 200 A. The effect of salicides is shown in Table 3-2. Since the salicide has material properties almost same as that of silicon, its presence does not make any significant effect on the stress introduced into the channel.

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29 Table 3-2: Effect of Salicide on NMOS Channel Stress Salicide thickness (A) xx (MPa) yy (MPa) 0 349 -322 50 348 -332 100 349 -333 150 351 -330 200 352 -330 3.5 Summary In this chapter, the sources of strain in MOSFETs are discussed. This is followed by a brief understanding of different types of stresses, their physics and mathematical modeling. Next, the state-of-the-art stress generation techniques, for both wafer-based biaxial and locally-induced uniaxial stresses are discussed. Finally, the effects of scaling different geometrical parameters for n-channel devices are explained along with simulation cases. In next chapter, the cases of technical importance for leading edge CMOS technology will be studied.

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CHAPTER 4 CASES OF TECHNOLOGICAL IMPORTANCE AND RELATED ISSUES In this chapter, cases of technological importance in advanced strained silicon device technology will be investigated. After understanding the stress generation mechanisms, physics and mathematical modeling described in the previous chapters, we can expand our discussion to various issues that need to be addressed with due understanding to extract the desired CMOS performance enhancement. We initiate the cases by exploring the issues in both biaxial and uniaxial stress generation methods, and then continue with discussion of novel stress engineering mechanisms. 4.1 Strained-Silicon-On-Insulator (SSOI) A large amount of research is being conducted in exploring the possibility of including biaxial strained-Si in mainstream CMOS process to enhance device performance [Hoy02, Rim]. A novel approach in this direction is to fabricate ultra-thin strained-Si layer on SOI, called strained-silicon-on-insulator (SSOI) [Rim03], thereby complementing their individual advantages. At the future advanced process nodes of 65 nm and below, performance and power consumption issues arise due to bulk silicons higher leakage currents. SSOI technology has proven thus far to be a promising variation to deal with these issues. The process complexity of fabricating SSOI structure involves transferring a strained-Si/relaxed SiGe hetero-layer on a handle wafer, followed by selective etch-back of SiGe to leave SSOI structure [be04, Chr05]. A homogeneous stress of 1.5 GPa has been exhibited by Soitec Groups [Soi92] industrially manufactured SSOI wafers with a 200 A Si layer. 30

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31 Figure 4-1: Stress relaxation in 200 A strained-silicon on insulator and on SiGe for different island sizes. The curves in circle are for mentioned strained-silicon thicknesses for 1.0 m island The matter of concern in this technology is the stress relaxation due to generation of free surface while forming STI trenches, which leads to wasted active area along the channel width. Consequently, this increases the actual required transistor width than estimated, if the stress relaxation is not accounted for. Adding to this issue, it can be inferred from the simulations that there is a significant relaxation in the biaxial stress when the film is on oxide compared to atop a SiGe layer. The reason being that SiGe has a much higher Youngs modulus compared to oxide. Figure 4-1 shows the transverse stress profile along the island width from its center for both these cases: strained-silicon-on-oxide and on SiGe. The initial stress in the Si film was assumed to be 1.6 GPa and the

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32 relaxation after etching the islands was studied. The simulation results for three different island sizes: 0.25 m, 0.5 m, 1.0 m, reveal the center has maximum stress in all the cases. For 0.25 m island, there is a 21% stress relaxation, for 0.5 m, it is 10% and for 1.0 m, its only 3%. Hence, it can be noted that as the island size increases, the stress relaxation at the center drops, but this requires wider devices. It can be seen that there is a significant wastage of silicon before the channel stress approaches a desired value to give optimum performance enhancement. One more observation from the graph is that the island regains higher peak stress value quickly for thinner silicon compared to the thicker silicon layers. Therefore, a way out to minimize silicon wastage for optimum mobility enhancement is to fabricate devices on thinner strained-silicon membranes. 4.2 Uniaxially Strained Device Issues Uniaxial front-end process induced stress is being widely adopted in almost all logic technologies because of its edge over the biaxial counterpart [Tho04b]. A caveat that might invoke the attention of VLSI process and design engineers will be discussed in this section. 4.2.1 Effect of Varying Silicon Nitride Thickness Chapter 3 explains the concept of improving electron mobility in n-channel devices by depositing a tensile silicon nitride capping layer over the entire structure. It has been understood that increasing the Si 3 N 4 film thickness increases the stress in the channel [Pid04]. This holds true up to a certain thickness in a legged gate structure, which are widely used in logic technologies. The effect of increasing the nitride thickness, keeping a constant space between two NMOS devices in stacked gate structure, is presented in figure 4-2. The devices were laid apart at a distance of 110 nm and stress value in the

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33 center device channel is plotted in the figure. Initially, both the stress components, necessary to boost NMOS performance, increase with nitride thickness. Figure 4-2: Effect of increasing silicon nitride thickness on channel stress components At 45 nm nitride thickness, pinch-off occurs when nitride cap of two adjacent gates merge, which abruptly reduces the longitudinal component, whereas the out-of-plane component remains constant. Then after, the longitudinal component value increases again slowly as the nitride becomes thicker. This behavior hints that silicon nitride requires a certain overlap over the source/drain regions to strain the channel, denial of which proves detrimental to the stress in the channel. One more crucial outcome of the graph in figure 4-2 is that the longitudinal stress reaches a peak value for a very thick nitride cap. This property can be exploited in front-end processing by using silicon nitride as the first-layer dielectric, which is normally ~1000 A thick. By doing so, both the

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34 needs are sufficed, viz. extracting maximum channel stress and forming a first-layer dielectric. The structure, generated by ISE-FLOOPS, in the pinch-off condition and for different nitride thicknesses can be viewed from figure 4-3. Figure 4-3: Stacked gate structures generated by ISE-FLOOPS for different silicon nitride cap thicknesses 4.2.2 Multiple Gate Structure A case of technical importance, similar to the one discussed in section 4.2.1, is to examine the effect of varying the space between adjacent gates in a multiple/stacked gate structure. The simulation results for this case, are plotted in figure 4-4, for both n-channel and p-channel devices with 35 nm gate length and 140 nm polysilicon gate thickness. Again, the effect of pinch-of of nitride cap discussed in previous section can be viewed, where the stress for 30 nm nitride cap exceeds that for 100 nm cap until approximately 70 nm space. This behavior asserts the conclusion that the cap of a given thickness requires a

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35 minimum space to strain the device channel maximally. One more point to be noted is that beyond a certain space, the stress saturates in the channel; which means it is futile to have a bigger source/drain diffusion area than this roll-off point. The same effect can be seen for PMOS, where the stress boosts up initially as the SiGe volume (space) increases, and beyond a roll-off point, the stress saturates. Also, as expected, the stress values are higher for smaller spacers since the SiGe is in closer proximity of the channel. The junction depth for PMOS devices is assumed to be 0.12 m. Figure 4-4: Effect of varying space between adjacent gates for different Si 3 N 4 cap thicknesses for NMOS, and different spacer sizes for PMOS 4.2.3 Stress Relaxation Due to the Presence of STI Shallow Trench Isolation (STI) is primarily used in CMOS technology to isolate n-channel and p-channel devices. STI is formed by etching shallow trenches and filling

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36 them with oxide dielectric. In this section, the effect of stress relaxation in the devices adjacent to the STI is explained. Figure 4-5 and figure 4-6 depict the NMOS and PMOS multipleFigure 4-5: Nested NMOS structure illustrating the stress relaxation due to the presence of STI gate structures with three devices and STI at the ends. It shows that the center device has the maximum stress compared to the ones near STI. In the NMOS case, a portion of intrinsic nitride stress is lost due to the softer oxide in STI, which leads to lower stress introduced inside the device channels adjacent to STI. The same effect is seen in the PMOS case, where SiGe source/drain regions push against the channel to induce a compressive stress. In the devices adjacent to STI, the source/drain regions of these devices push against softer oxide on one end, which results in SiGe losing some stress,

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37 leading to lower stress in these devices. Both these effects are illustrated in figure 4-5 and figure 4-6, where the first value shows the longitudinal component and the second value is the out-of-plane component of the stress at that point. An interesting takeaway from figure 4-6 is the notably lower stress near source/drain surface. It is much lower than the initial intrinsic stress, which leads to lower point-defects during fabrication. Figure 4-6: Nested PMOS structure illustrating the stress relaxation due to the presence of STI 4.2.4 Stress Relaxation due to Contact Etching An interesting issue that arises in process-induced uniaxial strained silicon devices is the effect of etching contact holes in NMOS devices. This issue has been discussed by Cea et. al. [Cea04], where the effect of etching a portion of nitride cap to make contact holes is explained. When contact holes are etched, it removes a significant amount of

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38 nitride, which leads to channel stress relaxation in longitudinal and out-of-plane directions. This effect is corroborated by figure 4-7, where the relaxation is plotted against contact hole distance from the spacer edge. As discussed in previous chapters, the out-of-plane component of the channel stress primarily arises primarily due to the nitride overlap over the spacers. Hence, it is not affected much due to the holes. The channel regains peak stress when contacts are distant from the channel. Figure 4-7: Stress relaxation due to contact holes in NMOS strained silicon device with 45 nm L gate 140 nm gate thickness and 80 nm nitride cap thickness A better understanding of this effect will be obtained by simulating the case in a 3D simulator, where contacts are simulated as holes unlike of infinite depth in the 2D simulator.

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39 4.2.5 Effect of Raised Source/Drain in PMOS Device This section explores a strategy to increase compressive stress generated by embedded SiGe source/drain regions in a PMOS device. The topology of the source/drain regions can assist to increase the stress and this property is well exploited during the front-end processing. Raising the SiGe source/drain regions up to a certain extent transfers higher stress to the channel, thereby further improving the mobility of holes. Figure 4-8: Stress boosting in PMOS by increasing SiGe step height for 45 nm gate length devices. A general practice in forming spacers is to use prefer silicon nitride versus oxide as the spacer materials, since nitride has proven to act as a better shield to the gate oxide. The drawback of this technology is the reduction in potential transfer of compressive stress to the channel because nitride is a harder material compared to oxide. The effect is clearly

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40 depicted in figure 4-8, which also shows the increase in stress upon increasing the raised step height. Beyond approximately 300 A of step height, the raised SiGe source/drain regions do not increase the stress further, and therefore the curve saturates. The figure also reveals the higher stress induced upon increasing the Ge concentration. Higher Ge concentration in SiGe compresses the silicon lattice even greater, which is simulated by higher intrinsic stress inside SiGe regions. In sate-of-the-art nanodevice research, Ge concentration is increased up to 30%. 4.2.6 SOI vs Bulk Technology In this section, we shall investigate and compare the stress generated in SOI and bulk devices. Ghani et. al. [Gha03] have reported the PMOS drive current enhancement by epitaxially grown SiGe source/drain regions on bulk silicon substrates. The compressive stress generated in the device channel increases with increasing the SiGe volume in the source/drain regions. Cases along the same line have been discussed in sections 4.2.2 and 4.2.5, where the SiGe space was increased in former case while SiGe step height increase was studied in the latter. In this section, the effect of increasing SiGe depth, in both SOI and bulk silicon, is studied and the results are plotted in figure 4-9. In the SOI structure simulated, the 70 nm silicon membrane is bonded on an oxide box thickness of 1000 A. This is followed by selectively etching the source/drain regions to the required depth, and filled by epitaxially grown SiGe. The plot in figure 4-9 compares the stress generated in SOI vs bulk silicon devices for 45 nm gate length. The SOI case is simulated with two different Youngs modulus of oxide, viz. 44 GPa and 72 GPa. As can be seen, the Youngs modulus of oxide does not alter the stress significantly. Also, the stress in SOI and bulk cases is almost equal for a given source/drain depth.

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41 Figure 4-9: Effect of varying SiGe depth in SOI vs bulk silicon devices For the current 90 nm node, the standard source/drain depth in bulk silicon devices is 120 nm, which induces approximately 700 MPa compressive longitudinal channel stress, while the maximum stress extracted out of the standard SOI devices is only about 550 MPa. Thus, the bulk silicon technology yields considerably higher compressive channel stress for PMOS drive current enhancement. The recent research work published work by Freescale Semiconductor Inc. [Zha05] reports 40% higher channel stress of PDSOI devices compared to its bulk counterpart. This result is inconsistent with the simulated results presented above. A 3D simulation approach with closer process modeling might lead to consistent results.

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42 4.2.7 Effect on Stress by Boron Doping in p-channel Devices Boron doping in p-channel source/drain regions introduces a local tensile strain in the substrate due to its size mismatch with silicon. Boron is smaller in size than silicon and when it occupies a substitutional lattice site, a local lattice contraction occurs (figure 3-1) because the bond length for Si-B is shorter than for Si-Si [Ran05]. Horn et. al. [Hor55] reported that a single boron atom exerts 0.0141 A lattice contraction per atomic percentage of boron in silicon at room temperature. The stress induced in the channel due to boron doping was insignificant for long-channel devices, but for CMOS transistor channel lengths in the nanometer realm, this stress plays a significant role in determining the carrier mobility enhancement. Boron is widely chosen as the p-type dopant due to its high solubility limit in silicon; at 1100 C, boron has a solubility limit of 3.3X10 20 /cm -3 [Jae02]. The simulations are performed by defining the local boron induced lattice contraction by a tensile intrinsic stress in source/drain regions [Hol93]. BdNdaa00.1 (4-1) where, = lattice contraction coefficient = 5.19e -24 cm 3 N B = boron concentration, a 0 = lattice constant. Therefore, 00ada = -.N B = is the local strain generated inside the silicon lattice. This strain is compressive, thereby pulling the silicon atoms in the lattice and generating a tensile stress in the device channel. The tensile intrinsic stress defined in the simulations can now be calculated by = -(E Si x ). Figure 4-10 reveals the amount of tensile stress induced by boron doping at different concentrations for different channel lengths. For 0.5 m source/drain length and

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43 given boron concentration, as the channel length is varied from 25 nm to long-channel length of 1.0 m, the stress in the center of the channel reduces exponentially. The effects of scaling source/drain length and channel length are explained in depth by Randell [Ran05]. Longer source/drain regions imply higher number of boron atoms to pull the channel. Figure 4-10: Effect of scaling boron concentration for different channel lengths, 0.5 m source/drain length and 0.12 m junction depth As can be seen from the plot in figure 4-10, the problem of tensile stress due to boron doping is not significant in long-channel devices, where the stress is below 50 MPa for 2X10 20 /cm -3 boron concentration. The problem alleviates when channel lengths enter nanometer regime and the boron concentration reaches its solubility limit. The stress in 45 nm channel length and 3.5X10 20 /cm -3 boron concentration reaches approximately 200

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44 MPa. This tensile stress can be deleterious to the compressive stress induced by embedded SiGe source/drain and can result in carrier mobility much lower than expected. Also, the boron solubility in silicon germanium increases much beyond its limit in silicon. So the dopant stress generation problem proves to be even more significant in advanced CMOS devices where Ge concentration is expected to be close to 30%. Methods to counter and suppress the dopant induced stress are important issues under research. 4.3 Prospective Stress Generation Techniques Historically, STI stress has been considered detrimental to the device performance [Sco99, Nan05]. Simulation and experimental results have shown that High-Density Plasma (HDP) Shallow Trench Isolation (STI) generates a transverse compressive stress in the channel, which degrades NMOS performance while not affecting PMOS. Despite its compressive nature and degradation of NMOS mobility, HDP is the most commonly used gap-fill technology for STI because of processing ease. In 65 nm devices, where pitch is expected to be less than 200 nm, compressive stress and reduced mobility can prove to be a major obstacle. Hence, efforts have been made to eliminate this stress. In this work, use of the high aspect ratio process (HARP) STI [Bay05], which produces a moderate to high transverse tensile stress, to engineer the device performance is presented. CMOS performance does not improve with just one type of longitudinal uniaxial stress along [110] direction. HARP STI, if used for isolating the devices along their width, induces transverse tensile stress along [1-1 0] direction. From the calculations of piezoresistance coefficients (Table 3-1) of Si along different dominant directions, it is obvious that transverse tensile stress can improve CMOS performance. The novel technique for stress engineering comes along with its own complexities which need to be

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45 dealt with to attain the performance improvement. All issues pertaining to this technique will be discussed in the following sections. 4.3.1 Stress Variation Along the Device Width All simulations performed for HARP STI assume an initial intrinsic stress of 1 GPa in all directions in STI due to its densification. The densification effect of HARP STI generates an equal intrinsic stress in all directions. The simulations conducted with this assumption showed an interesting trend where the channel stress exceeded the intrinsically defined STI stress. This will be termed as Stress Magnification. Figure 4-11: Stress variation along the device width in HARP STI stress engineering technique The stress magnifies better if the island is smaller for given STI dimensions. A matter of concern in using STI for stress engineering is the variation of the channel stress along the

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46 width. This has been shown in figure 4-11. Bigger islands have a higher variation, which implies the mobility is enhanced differently along the width. 4.3.2 Stress Engineering by STI Depth Transverse channel stress by HARP STI can be engineered by varying STI depth. The stress is seen to be a strong function of trench depth up to 400 nm, beyond which it rolls off (figure 4-12). Here, the STI width and transistor width are held fixed at 300 nm and 500 nm respectively. The figure also shows the effect of polysilicon gate on top of the channel before balancing the forces. In this case, there is significantly low amount of stress generated compared to the former case, since the channel effectively becomes a buried layer bound from all sides when forces are balanced. Figure 4-12: Effect of varying STI depth on channel stress: for free surface and for polysilicon on top

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47 The case with polysilicon on top can be considered to be analogous to the stress generated by embedded SiGe source/drain in PMOS, except that SiGe induces a compressive stress. 4.3.3 Stress Engineering by STI Width One approach to engineer the transverse tensile channel stress is by modulating STI width. Higher STI width implies higher amount of STI to pull the channel. This case is analogous to the case discussed in section 4.2.2, where the SiGe space is scaled to extract higher channel stress. For the STI case, the results are plotted in figure 4-13. It can be inferred from the figure that the stress increases up to 500 nm STI depth, beyond which the stress is indifferent to STI depth. Figure 4-13: Effect of varying STI width on channel stress for different transistor widths

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48 The practical STI depth for current processing technology is approximately 500 nm, which suffices the need to maximize the channel stress. As expected, the figure shows lower stress for wider transistors. All results are obtained in the center of the device width and 100 A below the surface. 4.3.4 Stress Dependence on STI Topology The STI topology is another factor which can change the stress expected to be introduced by the HARP STI densification process. A recessed STI surface can undermine the stress in the channel. Figure 4-14 shows ~80 MPa stress reduction for a 500 A recess in the STI surface. Hence, due importance should be given to the STI topology while polishing the surface. Figure 4-14: Stress dependence on STI topology

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49 4.3.5 Stress Dependence on STI Densification The intrinsic stress in the STI can be increased by increasing the densification of atoms in the HARP STI gap-fill. Thereby, the densification is purely a function of process technology adopted for CVD deposition of oxide in the isolation trenches. For a given STI and channel dimension, the channel stress varies linearly with the STI intrinsic stress, which can be viewed from figure 4-15. Figure 4-15: Stress dependence on HARP STI intrinsic stress 4.4 Summary In this chapter, stress issues pertaining to strained silicon devices were discussed and the explanations were corroborated with the simulation results. The chapter commenced by explaining the major issues in the state-of-the-art biaxially wafer based strain technique, followed by a variety of issues in uniaxial strained silicon devices. The

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50 issues ranged from structural geometry, stress relaxation by STI, scalability and comparison between SOI and bulk technologies. This was followed by addressing the important issue of dopant-induced stress. Finally, the prospective stress engineering techniques were explored, and issues arising in the technique were discussed. In the next chapter, a summary of all chapters will be presented, along with recommendations for the future work.

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CHAPTER 5 SUMMARY, CONCLUSIONS, AND RECOMMENDATIONS FOR FUTURE WORK 5.1 Summary and Conclusions In this thesis, a wide range of issues related to strained silicon technology, a vector to extend Moores Law, has been investigated. A set of simulations targeted to study and maximize stress in CMOS devices was carried out, and the results were presented with explanations. In Chapter I, the history of CMOS devices was discussed, starting with Moores Law, its implications on the semiconductor industry, and its predicted pathway. This was followed by the discussion of the driving motivations to study desirable strain in MOSFETs to extend Moores Law. A survey of the existing literature on strained silicon devices was presented along with the explanation of the physics behind performance enhancement in the devices. The state-of-the-art techniques to induce uniaxial and biaxial strain in the devices were introduced along with their advantages and drawbacks. Chapter II introduced the basic concepts of engineering mechanics, stress, strain and their relationship. The governing law, called Hookes Law, which describes the motion of spring in elastic limit, was introduced and explained mathematically with an example of a spring. The concept of linear elasticity was introduced. This was followed by the introduction to the Finite Element Method (FEM), an approach to discretize and solve many complex mechanical engineering mechanics problems. To understand the limitations of a system, the boundary conditions and approximations used for 2D simulations were discussed. The 2D simulator, FLOOPS, used to carry out simulations in 51

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52 this thesis, was introduced highlighting its key features and tools. Finally, the preliminary simulations to observe the channel stress sensitivity to material properties were discussed along with their analysis. Chapter III deliberated on the sources of strain in MOSFET channel. This was followed by different types of stress, their physics and mathematical modeling. Next, the state-of-the-art stress generation techniques, for both wafer-based biaxial and locally-induced uniaxial stresses were discussed. The two different methods to strain the PMOS channel, by SiGe source/drain regions and by compressive nitride capping layer, were presented and explained pictorially. The physics behind strain generation in NMOS due to stressed silicon nitride capping layer and in PMOS by silicon germanium source/drain regions were explained. NMOS channel is stressed by tensile nitride cap since an edge force is developed as the film passes over the spacer and the structure geometry. The silicon lattice in PMOS source/drain is compressed by the introduction of Ge, a larger atom than Si, which in turn compresses the channel, thereby enhancing the mobility of hole carriers. The piezoresistance coefficient table for standard layout and wafer orientation corroborates the reasoning behind NMOS performance enhancement due to tensile longitudinal stress and PMOS performance enhancement due to the compressive stress. Finally, the effects of scaling different geometrical parameters for n-channel devices were explained along with simulation cases. The longitudinal component of channel stress increases along with the scaling of NMOS critical dimension. Nitride spacers are better acquainted to transfer the nitride capping stress to the channel compared to oxide spacers, since nitride is a harder material with a higher Youngs modulus. The polysilicon gate thickness also plays an important role in determining the

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53 n-channel device stress. Initially, as the gate aspect ratio is increased, the channel stress increases. However, beyond 150 nm gate thickness for spacer case, and 100 nm for no spacer case, the stress saturates and does not respond to increasing the gate thickness thereafter. The thickness of buffer nitride film, used to reduce the process-induced defects, is equally significant to engineer, to have the desired mobility enhancement. As the liner thickness increases, it becomes difficult for the tensile nitride cap to stress the channel. Chapter IV presented cases of technical importance in advanced strained silicon device technology and the related issues. The cases are important to design and process engineers. Historically, mobility of holes is considered to be approximately half that of electrons. Due to this reason, PMOS devices are considered to be slower than NMOS, and hence the former are designed to be twice as wide as NMOS to have symmetrical rise and fall times in CMOS technology. Front-end process induced stress has been reported to enhance stressed to unstressed hole and electron mobility ratios up to 4 and 1.7 respectively [Hoy02]. This implies that in future generations of CMOS strained silicon devices, for symmetrical rise and fall times, PMOS need not be twice as wide as NMOS. The process flow complexity to induce wafer-based biaxial stress in the state-of-the-art SmartCut technology [Soi92] was discussed and the issue of stress relaxation caused due to free surface generation while etching STI trenches was explained at length. The relaxation causes the stress to reduce near the edges of silicon membrane, and hence this relaxation should be accounted for when sizing the transistors. The advantages of using a thinner membrane to minimize stress relaxation were discussed along with simulation results.

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54 A set of cases pertaining to uniaxial locally-induced stress was discussed thereafter. The effect of scaling up the nitride capping layer thickness in legged-gate NMOS devices separated by a certain distance was seen. The channel stress increases up to a certain value, and reduces dramatically at pinch-off of nitride layer. Thereafter, increasing the nitride cap thickness slowly increases the channel stress. The use of stressed silicon nitride as the first layer dielectric, between device and first metal layer, was proposed to maximize the channel stress. This was followed by the discussion of a similar case, where the space between adjacent devices in a legged-gate structure was scaled in both types of MOSFETs, and it was inferred that the stress in both the devices increases with increasing the space. Again, the effect of silicon nitride pinch-off was observed in NMOS devices. These are some of the prime challenges to be faced at the smaller feature sizes, where source/drain regions will be made smaller to increase the packing density of the devices. Next, the stress variation in different devices in a legged-gate structure due to presence of STI was discussed. STI relaxes and absorbs some stress from the adjoining devices; thereby the carrier mobility enhancement will be different in different devices. This is another important consideration the design engineers should take into account during circuit design. Another issue that leads to stress reduction in NMOS device (and PMOS device in dual stress liner technique) channel is the effect of etching contact holes for the source and drain connection. The contact holes remove significant amount of nitride, which relaxes the channel stress. The effect has been discussed by Cea et. al. [Cea04] and the difference between 2D and 3D simulated results has been explained. A 2D simulator assumes the contacts are of infinite depth rather than the 3D case that takes

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55 all dimensions of the holes into account. The effect of raising the embedded SiGe source/drain regions to compress the channel higher, has been discussed in the following section. The raising is beneficial up to 300 A, beyond which the stress is indifferent to the step height. Due to processing conditions, nitride spacers are preferred over oxide spacers, but this hinders the SiGe source/drain regions to stress the channel. Further, increasing the Ge concentration increases the stress in the source/drain along with the longitudinal compressive channel stress. Modern processes have incorporated up to 30% Ge concentration in the source/drain to achieve ultra shallow junction depths for the minimal feature size transistors. Boron diffusivity has been reported to get retarded in presence of SiGe compared to single crystal silicon [Zan03]. The difference in the stress generated in p-channel devices in bulk and silicon-on-insulator (SOI) technology has been simulated. The presence of oxide box does not make significant differences in the stress transferred to the channel. The source/drain depth in PDSOI devices is restrained by the silicon thickness, and hence the maximum it can reach in modern processes is up to 70 nm. This limits the SiGe volume, and hence the current 90 nm technology devices on bulk silicon exhibit higher stress than the SOI devices. An important issue of dopant induced stress in p-channel MOSFET device is discussed in depth, and the detrimental longitudinal tensile stress generated due to B doping has been discussed for short-channel and long-channel devices. From the piezoresistance coefficient table, it can be seen that tensile longitudinal stress degrades PMOS hole mobility. The tensile stress is prominent in short-channel devices where the source/drain regions are in close proximity to the channel and the B dopant concentration is approximately 3 x 10 20 cm -3 The tensile stress offsets some of the compressive stress

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56 induced by the SiGe source/drain regions, and hence the hole mobility attained is lower than the expected value. Finally, the prospective stress generation techniques by engineering the transverse longitudinal stress by HARP STI have been discussed. Various issues pertaining to this technique have been explained and seconded with simulation results. The stress variation along the device width in long-channel devices can be of prime concern, since it gives different carrier mobility at different points along the width. It is equally important to engineer STI depth and width to maximize the stress for the given device dimensions. The effect of Stress Magnification in HARP STI stress generation technique has been explained, where the channel stress exceeds the intrinsically defined STI stress in absence of polysilicon on top during the process flow. The topology and densification of STI should be accounted for to attain the desired stress. 5.2 Recommendations for Future Work Strain generation techniques have been discussed and a wide range of issues affecting the strained silicon devices have been simulated as a part of this thesis work. The emphasis for this work was to highlight the issues which the industry needs to account for in developing the process and devices. At each technology node, smaller feature sizes will be incorporated, which will demand more precise modeling of the front-end process to predict the device behavior. As we deal with materials at the atomic levels in future technology nodes, many different processing techniques are being explored to meet the requirements of the International Roadmap for Semiconductors (ITRS). The following work describes some of the recommendations for the future work to achieve closer simulated results to the fabricated device data.

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57 5.2.1 3D Modeling A better understanding of issues like contact hole etching, stress relaxation in SSOI films etc. will be achieved by 3D modeling of the process and device. A good example illustrating the difference in the results is the 3D modeling of contact holes [Cea04] where the results obtained by 2D simulator are very conservative and depict a significant mobility loss compared to the actual loss. All simulation cases for PMOS devices need a 3D approach, where the width of the device is finite and the intrinsic stress defined in the source/drain regions should be in all three dimensions. The stress generation techniques using HARP STI should also be simulated by defining the intrinsic stress in all three dimensions, since the STI densifies equally in all dimensions. Some of the 3D simulation results might reveal that the stress generated in the channel is not purely uniaxial, and that there is also some biaxial component attached to it. Therefore, it is recommended to simulate all the cases in a 3D simulator with a very close modeling to the actual process flow. ISE-FLOOPS v10.0 supports 3D simulations, which is recommended to simulate all the future work. 5.2.2 Additivity Issue An interesting issue to explore, which was attempted during this thesis work, is the stress additivity when a compressive silicon nitride capping layer is deposited over a PMOS structure with embedded SiGe source/drain. It is worth exploring, if the compressive stress generated by the individual techniques, actually complement each other when incorporated together. This requires multiple balancing of forces during the simulations, first one after PMOS structure sans silicon nitride, and the second one after deposition of silicon nitride film. This effort should then be extended to simulate the effect of a nitride cap while raising the step height. It is predicted that initially the stress

PAGE 70

58 would be additive, but as the step height is increased, the impact of compressive nitride cap on the channel stress would decrease. This effect was attempted to be simulated during this thesis work, but since ISE-FLOOPS v9.5 does not support multiple StressSolve commands in a single script, it is left as a recommendation for the future work using ISE-FLOOPSv10.0. The effort to explore the additivity issue should also be extended to test if all the stress generation techniques, including the prospective ones, complement each other if implemented together in CMOS structures. 5.2.3 Stress Generation due to Thermal Mismatch and Material Growth In this thesis work, all stresses are modeled by approximating them to the intrinsic stress. It is hereby recommended that the thermal mismatch stress during diffusion be accounted for, since all materials have different thermal expansion coefficients and this can lead to variation in the stress induced in the channel. Also, the SiGe source/drain should be simulated with the natural growth profile, and the lattice mismatch stress due to the material growth should be simulated in its original form. The obtained results should then be compared against the intrinsic stress approximation results presented in this thesis work. 5.2.4 Better Understanding of Novel Stress Generation Techniques It is imperative to understand and closely model the novel stress generation techniques, like the HARP STI to engineer transverse longitudinal stress, which would suffice the needs of performance enhancements for future strained silicon devices. The next step should be to club the existing standard strained silicon techniques with the novel techniques, and explore the stress additivity in the composite structures. As can be seen from the discussion in this chapter, there is a wide scope for exploration in the field of simulating front-end process induced stress to enhance the

PAGE 71

59 carrier mobility and thereby extend the Moores Law. It is hereby recommended that all the simulation results should be backed with the experimental data to have a better understanding of strain generation mechanisms in the devices.

PAGE 72

LIST OF REFERENCES [be04] I. berg, O.O. Olubuyide, C. N Chlirigh, I. Lauer, D.A. Antoniadis, J. Li, R. Hull, and J.L. Hoyt, Electron and Hole Mobility Enhancements in Sub-10 nm-thick Strained Silicon Directly on Insulator Fabricated by a Bond and Etch-back Technique, IEEE Symposium on VLSI Technology, June 2004, pp. 52-53. [Bay05] A. Al-Bayati, L. Washington, L. Xia, M. Balseanu, Z. Yuan, M. Kawaguchi, F. Nouri, R. Arghavani, Production Processes for Inducing Strain in CMOS Channels, Semiconductor Fabtech, 26 th Edition, 2005. [Boh03] M. Bohr, Intels 90 nm Logic Technology Using Strained Silicon Transistors, Presentation, Dec. 2003. [Cea04] S. M. Cea, M. Armstrong, C. Auth, T. Ghani, M.D. Giles, T. Hoffman, R. Kotlyar, P. Matagne, K. Mistry, R. Nagisetty, B. Obra,dovic, R. Shaheed, L. Shifren, M. Stettler, S. Tyagi, X. Wang, C. Weber, K. Zawadzki, Front End Stress Modeling for Advanced Logic Technologies, IEDM, pp.963-966, San Francisco, CA, 2004. [Chr05] S.H. Christiansena, R. Singh, I. Radu, M. Reiche, U. Gosele, D. Webb, S. Bukalo, B. Dietrich, Strained Silicon on Insulator (SSOI) by Waferbonding, Materials Science in Semiconductor Processing, Vol. 8, 2005, pp. 197-202. [FCG66] Ferro-Ceramic Grinding Inc., Silicon Nitride Properties, last accessed July 2005, http://65.108.128.37/pub/prodsvc/silicon-nitride-properties.php [Fre03] L.B. Freund and S. Suresh Thin Film Materials: Stress,Defect Formation and Surface Evolution, Cambridge University Press, Cambridge, United Kingdom, 2003. [Gha03] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffiann, K. Johnson, C. Kenyon, J. Klaus, B. Mclntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, M. Bohr, A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors, IEDM 2003 Technical Digest, pp. 978-980 60

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62 [Moh05] N. Mohta and S.E. Thompson, Strained Si-The Next Vector to Extend Moores Law, To be published in IEEE Circuits and Devices Magazine, 2005. [Moo65] Gordon E. Moore, Cramming More Components onto Integrated Circuits, Electronics Magazine, Vol. 38, No. 8, April 19, 1965. [Moo03] Gordon E. Moore, No Exponential Forever: But Forever Can Be Delayed!, IEEE International Solid-State Circuits Conference, February 10, 2003. [Nan05] B. Wong, A. Mittal, Y. Cao, G. Starr Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, 2005. [Pid04] S. Pidin, T. Mori, R. Nakamura, T. Saiki, R. Tanabe, S. Satoh, M. Kase, K. Hashimoto, T. Sugii, MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology Node, Symposium on VLSI Technology, 2004. [Ran05] H. Randell, Applications Of Stress From Boron Doping And Other Challenges In Silicon Technology, Masters Thesis. University of Florida, 2005. [Rim] K. Rim, L. Shi, K. Chan, J. Ott J. Chu, D. Boyd, K. Jenkins, D. Lacey, P.M. Mooney, M. Cobb, N. Klymko, F. Jamin, S. Koester, B.H. Lee, M. Gribelyuk, and T. Kanarsky, Strained Si for Sub-100 nm MOSFETs, IBM SRDC, Research Division and Microelectronics Division. [Rim03] K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carmthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs, IEDM Technical Digest, Dec. 2003, pp. 3.1.1-3.1.4. [Rue97] H. Rueda, Modeling of Mechanical Stress in Silicon Isolation Technology and its Influence on Device Characteristics, Doctoral Dissertation. University of Florida, 1997. [Sco99] G. Scott, J. Lutze, M. Rubin, F. Nouri, M. Manley, NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress, IEDM, pp. 827-830, 1999. [Sen01] S. D. Senturia Microsystem Design, Kluwer Academic Publishers, Norwell, MA, 2001.

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63 [Soi92] Soitec Inc., last accessed July 2005, http://www.soitec.com/ [Tho04a] S.E. Thompson, N. Anand, M. Armstrong, C. Auth, B. Arcot, M. Alavi, P. Bai, J. Bielefield, R. Bigwood, J. Brandenburg, M. Buehler, S. Cea, V. Chikarmane, C. Choi, R. Frankovic, T. Ghani, G. Glass, W. Han, T. Hoffmann, M. Hussein, P. Jacob, A. Jain, C. Jan, S. Joshi, C. Kenyon, J Klaus, S. Klopcic, J. Luce, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, P. Nguyen, H. Pearson, T. Sandford, R. Schweinfurth, R. Shaheed, S. Sivakumar, M. Taylor, B. Tufts, C. Wallace, P. Wang, C. Weber, M. Bohr, A 90nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1 um 2 SRAM Cell, International Electron Device Meeting, 2002. [Tho04b] S.E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. McIntyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, A Logic Nanotechnology Featuring Strained-Silicon, IEEE Electron Device Letters, Vol. 25, No. 4, pp. 191-193, April 4, 2004. [Tho04c] S. E. Thompson, University of Florida. Course Notes, EEL 6935: From Leading-edge Advanced CMOS to Nanotechnology, Fall 2004. [Tho04d] S. E. Thompson, G. Sun, K. Wu, J. Lim, T. Nishida, Key Differences For Process-induced Uniaxial vs. Substrate-induced Biaxial Stressed Si and Ge Channel MOSFETs, pp. 221-224, Technical Digest of the IEEE International Electron Devices Meeting, 2004. [Yin03] H. Yin, R. Huang, K. D. Hobart, J. Liang, Z. Suo, S. R. Sheih, T. S. Duffy, F. J. Kub, J. C. Sturm, "Buckling Supression of SiGe Islands on Compliant Substrates," J. Appl. Physics, Vol. 94, No. 10, pp. 6875-6882, November 15, 2003. [Yua01] C. Zhi-Yuan, M. T. Currie, C. W. Leitz, G. Taraschi, E. A. Fitzgerald, J. L. Hoyt, D. A. Antoniadas, Electron Mobility Enhancement in Strained-Si n-MOSFETs Fabricated on SiGe-On-Insulator (SGOI) Substrates, IEEE Electron Device Letters, Vol. 22, No. 7, pp. 321-323, 2001. [Zan03] N. R. Zangenberg, J. Fage-Pedersen, J. Lundsgaard Hansen, and A. Nylandsted, Boron and Phosphorus Diffusion in Strained and Relaxed Si and SiGe, Journal of Applied Physics, Vol. 94, No. 6, pp. 3883-3890, September 15, 2003. [Zie89] O.C. Zienkiewicz, R.L. Taylor Silicon The Finite Element Method Fourth Edition, Volume 1, Basice Formulation and Linear Problems, McGraw-Hill Book Company, London, 1989.

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64 [Zha05] D. Zhang, B. Y. Nguyen, T. White, B. Goolsby, T. Nguyen, V. Dhandapani, J. Hildreth, M. Foisy, V. Adams, Y. Shiho, A. Thean, D. Theodore, M. Canonico, S. Zollner, S. Bagchi, S. Murphy, R. Rai, J. Jiang, M. Jahanbani, R. Noble, M. Zavala, R. Cotton, D. Eades, S. Parsons, P. Montgomery, A. Martinez, B. Winstead, M. Mendicino, J. Cheek, J. Liu, P. Grudowski, N. Ramani, P. Tomasini, C. Arena, C. Werkhowen, H. Kirby, C. H. Chang, C. T. Lin, H. C. Tuan, Y. C. See, S. Venkatesan, V. Kolagunta, N. Cave, J. Mogab, Embedded SiGe S/D PMOS on Thin Body SOI Substrate with Drive Current Enhancement, submitted to Symposium on VLSI Technology, 2005.

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BIOGRAPHICAL SKETCH Nirav Shah was born on November 3, 1981, in Maharashtra, India. He has loving parents, Darshana and Shailesh Shah. He received his Bachelor of Electronics and Communication Engineering in 2003 at S. P. University, Gujarat, India. His hobbies include traveling, sports and reading. Nirav Shah joined the Master of Science program in Electrical and Computer Engineering Department at University of Florida in 2003. He has been working as a research assistant with Dr. Scott Thompson since 2004. 65


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STRESS MODELING OF NANOSCALE MOSFET


By

NIRAV SHAH
















A THESIS PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
MASTER OF SCIENCE

UNIVERSITY OF FLORIDA


2005





























Copyright 2005

by

Nirav Shah
































This work is dedicated to my parents for their unconditional love and support, and
without whom, I could not have achieved what I have.















ACKNOWLEDGMENTS

First and foremost, I would like to thank my advisor, Dr. Scott E. Thompson, for all

the support, encouragement and assistance he has given me throughout my graduate

studies, and for the opportunity to work with him in the SWAMP group. Despite being

really busy, he always found time for his students to discuss research and other technical

deliberations. I will always adore his innovative thinking and diligent commitment to

research, which I tried to imbibe during my work tenure. I am also very grateful to Dr.

Mark E. Law and Dr. William R. Eisenstadt for supporting my research activities and for

their guidance and support as my supervisory committee.

This research could not have been completed without the financial support of the

Semiconductor Research Corporation and Applied Materials Inc. I would like to thank

the University of Florida and Department of Electrical and Computer Engineering for

giving me an opportunity to explore the wide horizons of the technical arena.

I would like to thank the SWAMP group and all its members for their warm

support during my research. I appreciate the efforts of Teresa Stevens for being an

excellent program assistant. I am grateful to Russ Robison for his assistance to get me

acquainted with FLOOPS and his continuous support thereafter. I would like to thank

Ljubo Radic for being a good friend and helping me solve problems during my research

work. I am especially thankful to Heather Randell, for her help all throughout my

research work and then after to compile my thesis. I would like to thank Sagar Suthram,









Guangyu Sun, Nidhi Mohta and Kehuey Wu for their availability for research related

discussions.

I thank my loving parents and each member of my family, without whose support

and motivation, my achievements would have been incomplete. Last but not least, I

would specifically like to thank all my roommates, friends, colleagues and teachers in the

United States, and back home, for their overwhelming love and trust in my efforts, and

for standing by me whenever I needed them the most.
















TABLE OF CONTENTS

page

A C K N O W L E D G M E N T S ......... .................................................................................... iv

LIST OF TABLES ............... .................... .. ......... ............ ............ viii

LIST OF FIGURES ......... ........................................... ............ ix

ABSTRACT ........ .............. ............. ...... ...................... xi

CHAPTER

1 IN TR OD U CTION ............................................... .. ......................... ..

1.1 H history and M motivation ............................................................................ .... .. 1
1.2 Strained Silicon Physics ................... .......... .. ....... ..... ...... ....
1.3 Modifications in Conventional MOSFET Equation due to Strain.........................5
1.4 Sum m ary ..................................... ................................. .......... 6

2 SIM ULATION M ECHANICS .......................................................... ............. 7

2.1 B asics of Engineering M echanics.................................... .................................... 7
2.2 Relationship betw een Stress and Strain.............................................................. 8
2.3 Software Approach To Engineer Stress...................................................... 10
2.3.1 ISE-FLO OPS B background ........................................ ...... ............... 10
2.3.2 H ow to use ISE -FLO O PS...................................................... ..................11
2.3.3 Computation of Mechanical Stress using ISE-FLOOPS............................11
2.3.4 Finite Elem ent M ethod (FEM ) .............................................. ...................12
2.3.5 B oundary C onditions........................................................ ............... 15
2.4 M material Param eter Sensitivity ........................................ ........................ 15
2.5 Sum m ary ............................................................... ... .... ......... 17

3 STRESS GENERATION TECHNIQUES IN ADVANCED CMOS ........................18

3.1 Types of Process Induced Stresses ............................................ .....................18
3.1.1 Therm al M ism atch Stress ................................................ ...... ......... 18
3.1.2 Intrinsic Stress ................................................................. ........... 19
3.1.3 D opant Induced Stress ...................................................... ..................20
3.2 Biaxial Stress Generation Technique......................................... ............... 20
3.3 Uniaxial Stress Generation Technique ...................................... ............... 23









3.4 Effect of Varying Geometrical Parameters ...... ...........................................24
3.4.1 Critical D im ension Scaling.................................... ......................... 25
3.4.2 Polysilicon Gate Scaling........................ ..... ......................26
3.4.3 Effect of Buffer Layer on NMOS Channel Stress............................... 27
3 .4 .4 E effect of S alicid e .............................................................. ................ .. 2 8
3 .5 S u m m a ry ...................................................................................................2 9

4 CASES OF TECHNOLOGICAL IMPORTANCE AND RELATED ISSUES.........30

4.1 Strained-Silicon-O n-Insulator (SSO I) ............................................. ................30
4.2 Uniaxially Strained Device Issues .............................. ...... .............................. 32
4.2.1 Effect of Varying Silicon Nitride Thickness............................................32
4.2.2 M multiple Gate Structure ....................................... ...... .................. 34
4.2.3 Stress Relaxation Due to the Presence of STI................ .............. ....35
4.2.4 Stress Relaxation due to Contact Etching ..............................................37
4.2.5 Effect of Raised Source/Drain in PMOS Device .................. ................39
4.2.6 SOI vs Bulk Technology ...........................................................40
4.2.7 Effect on Stress by Boron Doping in p-channel Devices...........................42
4.3 Prospective Stress Generation Techniques.............................. ............... 44
4.3.1 Stress Variation Along the Device Width ...............................................45
4.3.2 Stress Engineering by STI Depth .................................... ............... 46
4.3.3 Stress Engineering by STI W idth............................ .... .... .............. 47
4.3.4 Stress D ependence on STI Topology ............................... ............... .48
4.3.5 Stress Dependence on STI Densification ....................................... 49
4.4 Sum m ary .................................................................. ....... ........ 49

5 SUMMARY, CONCLUSIONS, AND RECOMMENDATIONS FOR FUTURE
W O R K ........................................... ..........................................................5 1

5.1 Sum m ary and Conclusions ............................................................................51
5.2 Recomm endations for Future W ork .......................................... ............... 56
5.2 .1 3D M odeling ............ .......................................................... .... .... ... ... 57
5.2.2 A dditivity Issue .................... ...... ................ ......... .......... ......... .. 57
5.2.3 Stress Generation due to Thermal Mismatch and Material Growth...........58
5.2.4 Better Understanding of Novel Stress Generation Techniques..................58

L IST O F R EFE R E N C E S ............................................................................. ............. 60

BIO GRAPH ICAL SK ETCH .................................................. ............................... 65
















LIST OF TABLES


Table page

2-1 M material Parameter Sensitivity Results ........................................ ............... 16

2-2 Material Properties at Room Temperature...... .............. ................................17

3-1 Longitudinal and Transverse Piezoresistance Coefficients Evaluated for
Standard Layout and Wafer Orientation (Units of 10-12 cm2 dyne-1).....................21

3-2 Effect of Salicide on NM OS Channel Stress ................................. ............... 29
















LIST OF FIGURES


Figure p

1-1 Prediction by Dr. Gordon E. Moore, also known as Moore's Law...........................1

1-2 Transistor size and technology trend................................... .................................... 2

1-3 Gate oxide scaling with the technology generations...............................................2

1-4 Supply voltage scaling with the technology generations ........................................3

2-1 Stress components acting on an infinitesimal cubic element.................................

2-2 Flowchart of FEM stress solving algorithm in a composite structure..................... 13

3-1 Lattice contraction due to boron atom and lattice expansion due to germanium
ato m ...............................................................................................2 0

3-2 MOSFET schematic device cross-section (standard layout).................................21

3-3 Steps in creating biaxially strained silicon film atop SiGe layer ...........................22

3-4 Traditional approach to enhance device performance illustrating biaxial tensile
stress in M OSFET channel ......... .................................... .... ..................... 22

3-5 IBM technology to introduce uniaxial longitudinal stress in CMOS devices..........23

3-6 Intel's strained silicon technology................................................. .....................24

3-7 Longitudinal channel stress component values for different critical dimensions
for oxide, nitride and no spacers. ........................................ ......................... 25

3-8 Effect of scaling polysilicon gate thickness on NMOS channel stress ....................27

3-9 Effect of increasing buffer (liner) layer thickness on NMOS channel stress...........28

4-1 Stress relaxation in 200 A strained-silicon on insulator and on SiGe for
different island sizes ..................................................... ... .. ............ 31

4-2 Effect of increasing silicon nitride thickness on channel stress components ..........33









4-3 Stacked gate structures generated by ISE-FLOOPS for different silicon nitride
cap th ick n esses ..................................................... ................ 3 4

4-4 Effect of varying space between adjacent gates for different Si3N4 cap
thicknesses for NMOS, and different spacer sizes for PMOS ..............................35

4-5 Nested NMOS structure illustrating the stress relaxation due to the presence of
S T I ................... ......................................................... ................ 3 6

4-6 Nested PMOS structure illustrating the stress relaxation due to the presence of
S T I ................... ......................................................... ................ 3 7

4-7 Stress relaxation due to contact holes in NMOS strained silicon device with 45
nm Lgate, 140 nm gate thickness and 80 nm nitride cap thickness .........................38

4-8 Stress boosting in PMOS by increasing SiGe step height for 45 nm gate length
d e v ic e s ........................................................................... 3 9

4-9 Effect of varying SiGe depth in SOI vs bulk silicon devices...............................41

4-10 Effect of scaling boron concentration for different channel lengths, 0.5 gm
source/drain length and 0.12 gm junction depth .............. ...................................43

4-11 Stress variation along the device width in HARP STI stress engineering
tech n iqu e ............................................................................ 4 5

4-12 Effect of varying STI depth on channel stress: for free surface and for
polysilicon on top ............................................................... .... ............ 46

4-13 Effect of varying STI width on channel stress for different transistor widths .........47

4-14 Stress dependence on STI topology .............................................. ............... 48

4-15 Stress dependence on HARP STI intrinsic stress.........................................49















Abstract of Thesis Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Master of Science

STRESS MODELING OF NANOSCALE MOSFET

By

Nirav Shah

December 2005

Chair: Scott E. Thompson
Major Department: Electrical and Computer Engineering

Process-induced strained silicon device technology is being adopted by the

semiconductor industry to enhance the performance of the devices in the nanometer

realm. A prime area of research is to explore different ways to maximize the desirable

strain in the device channel. Difficulties also exist with scaling strain to future technology

generations.

The need of the hour is to simulate and understand the front-end process closely to

attain the required strain in the channel and this can be done using Finite Element Method

(FEM). ISE-FLOOPS uses "StressSolve" solver to calculate the stress by solving for

Hooke's Law. The stress is a function of different parameters like geometry of the

structure, boundary conditions, material parameters, process flow, etc. A range of issues

such as stress dependence on critical dimension scaling, stress relaxation due to STI and

contact hole etching that restrict the scalability of device structures for uniaxial and

biaxial process induced stress have been addressed and explained with the help of

simulation results. The detrimental effects of dopant introduced tensile stress in the p-









channel devices have been highlighted. This work proposes some novel stress

engineering techniques like using HARP STI to induce a transverse stress during the

CMOS fabrication process.
















CHAPTER 1
INTRODUCTION

In this thesis, the understanding and issues of MOSFET performance enhancement

by using strained silicon devices will be discussed. This will be achieved by exploring the

necessity of using mechanical strain as a vector for performance enhancement.

1.1 History and Motivation

For the past four decades, geometrical scaling of the transistor dimensions-Moore's

Law [Moo65]-has dominated the semiconductor industry for greater transistor density

and the corresponding transistor performance enhancement. The basic proposal by Dr.

Gordon E. Moore was that transistor density on an integrated circuit will approximately

double every two years.


t15 1 G
14 -
S13' /

o- j





X 42
1-



VCL
F5 cDr. Gw More L





Figure 1-1: Prediction by Dr. Gordon E. Moore, also known as Moore's Law [Moo65]









Since then, much innovation in the areas of transistor scaling and usage of new

materials to follow the Moore's Law have been accomplished which has led to the

present day MOSFETs.

10pm
SEras of Transistor Scaling

N

Ta 1 npm Constant Voltage Scaling
I, Technology
M. Feature Size
a)130nm
LLnm Abrupt
fm 1Junctions
100nm .
o : Nanotechnology t Straned
Z Gate length Silicon



1 Onm
1970 1980 1990 2000 2010
Figure 1-2: Transistor size and technology trend [Tho04c]

With the scaling of the feature size, the supply voltage and gate oxide thickness also

scaled to a certain extent, to fabricate low power high-speed circuits.


100


E


Thickness vs Time
a Electrical
S10 0.325,

F_ 0.2 P


0 Physica 0O.aP
Source: Intel Technology
[Moore, 2003 ISSCC; Thompson 2002 IEDM]

'69 '72 '75 '78 '90 '93 '96 '99 '02 A

Figure 1-3: Gate oxide scaling with the technology generations [Tho04c]









100 -"
> I Technology Supply Voltage


0

S10 .7X Voltage
0 Scaling
0 Little
,- Voltage
I-
OI Scaling



1970 1980 1990 2000 2 t
Figure 1-4: Supply voltage scaling with the technology generations [Tho04c]

The exponential progress predicted by Moore's Law stayed firm on its path for

over four decades, but it can not continue the trend forever [Moo03]. As the industry

enters the nanometer regime, where the transistor gate length drops down to 35 nm and

the gate oxide thickness to 1 nm, physical limitations such as off-state leakage current

and power density pose a potential threat to enhance performance by simple geometrical

scaling, and the industry needs a new scaling vector. Front-end process induced stress has

thereby emerged as the new scaling vector for the current 90 nm node and the future

technologies too [Tho04a, Tho04b]. Stress improves performance by the mobility

enhancement, which fundamentally results from alteration of electronic band structure of

silicon [Moh05].

1.2 Strained Silicon Physics

The switching speed of an ideal transistor can be increased primarily by two ways:

physical gate length scaling and carrier mobility enhancement. Strained silicon is a

technology, which increases the switching speed solely by enhancing the carrier mobility.

The carrier mobility is given by [Moh05]:









/ = where, 1/T = scattering rate, m* = conductivity effective mass (1-1)
m

The carrier mobility is enhanced by strain by reducing the effective mass and/or the

scattering rate. It is accepted now that the electron mobility is enhanced by both the

phenomena [Yua01], while for holes, only mass change due to band warping is

understood to play a significant role [Tho04d] at the current stress levels in production.

The mobility is directly related to the carrier velocity 'u' and applied external

electric field 'E' by:

u = t.E (1-2)

It can be seen that increasing the carrier mobility increases the velocity, which is directly

proportional to the switching speed of the device.

For electron transport, the conduction band consists of six equal energy degenerate

valleys at room temperature. Upon application of strain, two states occupy lower energy

levels, while the remaining four occupy the higher one, thereby removing the degeneracy

between the valleys. The difference in the energy levels causes repopulation of the

electrons, thereby reducing their net effective mass [Moh05]. Due to band splitting, the

backscattering of the electrons is reduced, thereby enhancing the velocity. The reduction

of backscattering implies the increase in average lifetime of a carrier before it is knocked-

off during its course. The combination of both these effects leads to a net increase of

electron mobility improvement in strained silicon devices.

For hole transport, the valence band structure of silicon is much more complex. The

valence band comprises of three bands: heavy-hole, light-hole and split-orbit bands

[Ran05]. Application of favorable strain along [110] direction causes high band warping.

When the strain is applied, the degeneracy is removed between light-hole and heavy-hole









bands, and holes fill-up the "light-hole"-like band [Moh05]. This reduces the effective

mass, which is the prime contributor to hole mobility enhancement under strain. For the

current stress levels (up to 1GPa), hole intervalley scattering is not significantly reduced

since the bands splitting needs to be comparable to the optical phonon energy to

considerably suppress the scattering effects. The main advantage of uniaxial compressive

stress to the biaxial counterpart is that the hole mobility enhancement does not degrade at

high vertical fields where commercial MOSFETs operate [Tho04b]. The methods of both

uniaxial and biaxial state-of-the-art stress generation techniques are discussed at length in

chapter 3 and chapter 4.

Strained silicon technology comes with its own set of problems, which need to be

addressed aptly. The main issues include the threshold voltage shifts [Lim04] and

dislocation loops. The latter will have to be addressed by changing thermal cycles and

controlling growth.

1.3 Modifications in Conventional MOSFET Equation due to Strain

The classical MOSFET equations for a long-channel device operating in linear and

saturation regions are given by:

T uCW [ V17 \7 2 '1-3)
Id(hn)- c w VT ds (1-3)

_IUCJV W (1-4)

Id(sat)- gs )-4)

In the nanometer realm, the carrier transport in the device becomes ballistic and Equation

(1-4) becomes dependent on the carrier velocity as [Tho04c]:

Id(sat) =CoxW < u(O) > (VgS V) (1-5)









Hence, it can be seen that the square-law relationship approaches linearity in a ballistic

model. In the above equation, is the average carrier velocity at source which is

related to the mobility by Equation (1-2). As the channel length approaches zero,

is the unidirectional thermal velocity UT, which is given by [Tho04c]:

/2k T
UT = 2k (1-6)
V amn

The drain current in the nanoscale limit can now be equated as:


Id(sat) = oxW 2k gs (1-7)
V jn

Therefore, it is obvious that improving the mobility by application of strain enhances the

performance of the device.

1.4 Summary

This chapter started with the brief introduction of MOSFET scaling trends and the

motivation behind the work presented in this thesis. Moore's Law was discussed along

with the scaling trend of different device parameters such as the gate oxide and the

supply voltage. This was followed by the understanding of the necessity of adopting

strain as the new scaling vector and the basics of strain physics to assist performance

enhancement. Finally, the implications of strain on the classical MOSFET equations in

the nanotechnology devices were discussed. Chapter 2 will discuss of the simulation

mechanics and strain engineering to generate the desirable strain in the device channel.














CHAPTER 2
SIMULATION MECHANICS

2.1 Basics of Engineering Mechanics

Since the thesis is primarily concentrated around stress and strain in MOSFETs, it

is essential to understand the basics of engineering mechanics like stress, strain and

mechanical properties. When a force is applied on a fixed body, it deforms in its shape. If

the deformation is small enough, it returns to its original shape once the applied force is

removed. This is described as the linear elastic behavior of the body and the deformation

is considered to be within the elastic limit.

Stress (a) is defined as force per unit area AA acting on the surface of a solid. Its

unit is Pascal (Pa).

AF
Slim (2-1)
AA->O AA

Stress is a vector which has two components: normal and shear component.

Normal Stress: Force per unit area, acting normal to AA is called the normal stress 'a'.

Shear Stress: Force per unit area, acting tangential to AA, i.e. along the plane of the

surface, is called the shear stress 'T'. Shear stress has "tearing" effect on the plane of the

body.

Stress that acts to shorten an object is called compressive stress while the one that acts to

lengthen an object is called tensile stress. As a rule of thumb, tensile stresses are

considered positive and compressive stresses as negative.









Strain 'E' is defined as change in length of an object under force, compared to its

original length. It is unit less quantity. Again, corresponding to normal and shear stress,

there are normal and shear strain components.

To understand the stresses and strains in depth, consider an infinitesimal cube as

shown in figure 2-1. The figure shows normal and shear stresses in x, y and z directions

acting on different planes of the cube.



/ f"" ~1- T +Y
xz V Cxx 7

+z Tz Tv / -- 5yy
+z
S zy yx




+x

Figure 2-1: Stress components acting on an infinitesimal cubic element [Ran05].

The first subscript identifies the face on which the stress is acting, and the second

subscript identifies the direction. The 'o,' components are the normal stresses while the

'rz' components are the shear stresses.

2.2 Relationship between Stress and Strain

Stress and strain are related to each other by the material property called Young's

Modulus 'E' as E = o/e. Hence, it is obvious that Young's modulus defines the stiffness

of the material. Normal forces are resisted by the body's bulk modulus and shear forces

are resisted by the body's shear modulus, which determines how much a solid will

compress under external pressure.









Poisson ratio 'u', one more important property of the material, is the ratio of lateral

contraction strain to longitudinal extension strain in the direction of the tensile stress.

After the basic understanding of the mechanics concept, we can extrapolate our

discussion to behavior of a body under force. Conceptually, any solid can be considered

as a spring with certain stiffness. Consider a weightless spring suspended from ceiling

and the other end is free to move. When a weight is suspended at the free end of the

spring, it extends by a certain amount x depending the weight and stiffness of the spring.

These quantities can be related to each other by mathematical expression of Hooke's Law

which states k.x, wherefis the force applied (in our case, weight of object generates a

force at the free end), k is the stiffness of the spring and x is the extension/displacement.

Now, if the force applied is within the elastic limit, the spring reverts back to its original

shape when the weight is removed. Also, in a system under equilibrium, the forces at all

nodes are balanced, which means that summation of all forces in a system under

equilibrium is zero. So when a force is applied on the spring, net forces acting on the

spring are balanced when the spring displaces by a certain amount.

Hooke's Law also states that strain can exist without stress. To illustrate this

phenomenon, consider an elastic band in relaxed position. When it is stretched along its

length, stress is applied in y-direction whereas there is no externally applied stress along

x and z-directions. The band not only extends along y direction, but also contracts along

x and z-directions, which means there is strain in all the three directions when stress is

applied in just one direction. After releasing the band, it comes back to its original shape

if the applied forces are in elastic limit.










The thesis work of Randell [Ran05] explains the concepts of shear and normal

stresses and strains at length and their relationship in equilibrium condition. The stress

matrix in static equilibrium is given by:



Oyy

-tota = z where, a = normal stress component, T = shear stress component (2-2)

yz
7 zx


Similarly, the strain matrix in equilibrium is given by:


Eg w
gEy

Total -- where, F = normal strain component, y = shear strain component (2-3:
2/y
_Yx
Yz


2.3 Software Approach To Engineer Stress

A software-based approach is adopted to engineer and maneuver the stress

generated in the MOSFET channel, with an ultimate goal of enhancing the device

performance. This is the common and most effective approach adopted in the

semiconductor industry to model process-induced stress.

2.3.1 ISE-FLOOPS Background

FLOOPS (Florida Object Oriented Process Simulator) is a ID, 2D and 3D process

simulator, which simulates all standard process simulation steps like diffusion, oxidation,

etching etc. [ISE03]. FLOOPS is a C" based simulation program, which uses physical

models to describe all the processing steps. There is a scripting capability called


)


)









Alagator, which can be used to simulate all user-defined processing steps. The ISE

version of FLOOPS, used to obtain all the results in this work, is based on the 2000 and

2002 releases of FLOOPS written by Dr. Mark Law and coworkers at University of

Florida.

2.3.2 How to use ISE-FLOOPS

ISE-FLOOPS accepts sequence of commands at the command prompt or composed

in a command file. The process flow is simulated by issuing a sequence of commands

that correspond to the individual process steps. The command file is first checked for

syntax by a pre-compiler and then the commands are executed sequentially. The pre-

compiler proves to be a great boost to enhance the execution speed since it checks for

syntax at the beginning of execution. FLOOPS is written as an extension of tool

command language (Tcl), so all Tcl commands and functionalities are supported by the

software.

A flexible way to use ISE-FLOOPS is to run the command file through the job-

scheduler called GENESISe. The latter is added to ISE framework to make the usage of

ISE TCAD tools easier and user-friendly. It simplifies and organizes the handling of

complex projects by an intuitive Graphical User Interface (GUI) environment. The

GENESISe scheduler forms Design of Experiments (DoE) for the jobs and allows

monitoring the simulation jobs running in a project. The user can initiate a bunch of jobs

for simulation and GENESISe enqueues the tasks to be executed sequentially.

2.3.3 Computation of Mechanical Stress using ISE-FLOOPS

FLOOPS supports four mechanical models for the computation of mechanical

stress: purely viscous, viscoelastic, elastic and plasticity. All simulations in this work are

performed using elastic model. This is a valid approximation since the displacements









caused due to the stresses are in the linear elastic limit. The approximation was asserted

by setting the viscosity of the materials to a high value. The tensor equations can be split

into two parts: deviatoric and dilatational [ISE03]. The dilatational trace describes the

material behavior in the case of a pure volume change while the deviatoric part describes

an arbitrary deformation but without changing the volume.

In elastic model, the deviatoric part is calculated as

o Ik = 2GE'jk where, G = shear modulus (2-4)

The dilatational part is calculated as

C kk= 3K skk = -3p where, p = hydrostatic pressure, K = bulk modulus (2-5)
k k

Traversing the mesh, at each step, the equation is solved for balance of forces given by

[Cea04]:


S +F = 0, (fori =x, y,z) (2-6)

where, c denotes the stress and F, denotes the total external forces generating the stress.

These forces include the intrinsic film stress, thermal mismatch stress and stress induced

due to material growth [Ran05].

2.3.4 Finite Element Method (FEM)

The physical interpretation of FEM is the breakdown of a structural system into

components (elements) and reconstruction by the assembly process [Gud04]. This

method is extremely useful for solving a complicated structure by dividing it into small

elements by discretization process. The behavior of the overall structure can be estimated

by solving the differential equations of individual elements. In 2D simulation, the z-

direction is assumed to be infinite and the structure is sub-divided into triangles, while for

3D simulations, the element is a tetrahedron. A mesh is formed by the collection of all










these 3-node triangles, and each node in the mesh is assigned a number along with a set

of coordinates (x, y).

For arbitrary structures, stresses are not in equilibrium when described externally.

The stressSolve command solves for Hooke 's Law (f=k*x) at each element leading to

global equilibrium condition. The solver traverses through all nodes in the mesh,

calculating stiffness and displacement, which relates to strain and stress at each element.

In a composite structure, like the one shown in figure 2-2, the normal force applied is

calculated from intrinsic stress by integrating the defined stress over the area. The

stiffness matrix at each node is calculated from two more matrices: B-matrix and D-

matrix. B-matrix is a function of geometry of the element and the nodal coordinates of

the given element, while D-matrix purely depends on the material properties.


--------------------------------------------
applied force Create B- Create BT- Create D-
k2,E2matrices matrices matrices


more nodes in mesh Calculate kl,kz-
Newtonian __ matrices
solver
all nodes traversed


Calculate c at Calculate s at Calculate x at Create global k-
each node each node each node matrices for both
material s

Figure 2-2: Flowchart of FEM stress solving algorithm in a composite structure.

In equilibrium condition, for an element triangle with area A, the elemental stiffness ke is

calculated in discretized form as [Gud04]:

k Areaeement.BT .D .B (2-7)

The B-matix, which is a function of nodal coordinates, is given by [Zie89]:










SYJ-yk 0 k -y, 0 y, y 0
B = 2A 0 xk 0 x, xk 0 x, x, (2-8)
xk-xj yj yk x, Xk yk- Y xj -x y- yj



The D-matrix, for plane strain, is given by:


1 0
1-v
E.(1- v) v
D E v) 1 0 (2-9)
(1+ v).(1 2v) 1- v
0 0 (1- 2v)
2.(1-v)

The plane strain approximation for 2D simulations assumes that E = y, = z = 0, but

stress in z-direction is not zero. Here, we assume an infinitely long structure along z-

direction, hence the strain in z-direction approaches zero [Rue97] To compensate for the

3-D behavior in a 2-D domain, the 2-D strain must be multiplied by a factor of (1 + v)

[Ran05]:



s= sE = (l+ ) E (2-10)
e 0-

In equation (2-7), 2.A represents elemental volume in 3D and area in 2D. After

obtaining the stiffness values, displacement at each node is calculated by solving Hooke's

Law. Across the interface of the two materials, strain is constant and thereby,

displacements at each node in adjoining material are calculated. The elemental strain is

related to elemental displacement by:

8e =B. xe (2-11)









2.3.5 Boundary Conditions

Understanding boundary conditions is imperative while using FEM. The reflecting

boundary conditions were assumed in all the simulation cases. This is a valid

approximation if the boundaries are defined considerably far from the channel area, to

avoid any effect of the boundaries on the channel stress. In the actual environment, the

boundaries of a semiconductor wafer are free, but to simulate using free boundary

conditions for a single device, the source/drain diffusion regions need to be exceedingly

large, i.e. boundaries must be too far from the channel. This unnecessarily increases the

complexity and size of the mesh as well as the simulation time. The source/drain regions

in the simulations were chosen large enough to have no effect of the boundary conditions

on the channel stress.

The grid setting in the mesh is an important aspect of any FEM based simulator.

All simulations in this work are carried out using mgoals engine, which is an adaptive

engine to set the grid as each processing step is simulated. Initially, the grid in the entire

structure was set in a coarse fashion, which gave significant offset from the expected

results. Then after, the grid density in the desired regions, viz. the channel and the

source/drain, was increased till the stress became insensitive to the grid. Of course, the

trade-off with increasing the grid density is the computation time.

A more detailed explanation of the FEM is given by [Ran05]. The reader can refer

to ISE TCAD Release 9.0 manual [ISE03] for a detailed working and description of all

ISE-FLOOPS process models and other TCAD subsidiary tools.

2.4 Material Parameter Sensitivity

In this work, the sensitivity of the channel stress to the material parameter

variations was observed. Longitudinal tensile stress in NMOS is generated by









densification of silicon nitride layer on NMOS [Tho04a]. Table 1 shows the summary of

the results obtained by skewing various parameters. In all the results presented in this

work, oxx represents longitudinal component and yy represents out-of-plane component

of stress. Also, the positive values denote tensile stress while negative ones denote

compressive. We hereby start with the following parameters:

Esi = Epoly = 180 GPa; ESiN = 300 GPa; Eoxide = 65.8 GPa;

usi = UPoly = 0.28; UsiN = 0.1471; Doxide = 0.2

The stress for the above stated parameters is: oxx = 427 MPa, cyy = -412 MPa

The material parameters are highly process dependent and so are subject to change. The

sensitivity of the channel stress on the parameters of each material was studied, and it

was inferred that variations of material parameters do not alter the stress heavily.

However, the silicon nitride parameters do affect the stress and changes the calculations

significantly. The results obtained by the above mentioned sensitivity test are listed in

Table 2-1. Each row suggests changing the listed parameter, while keeping all other

parameters constant as above. The variations of the stress from the above mentioned

results were studied.


Table 2-1: Material Parameter Sensitivity Results (skewing the individual parameters,
while keeping all others constant as stated above)
Parameter xx (MPa) yy (MPa) Observation
Esi = Epo = 110 GPa 414 -412 No effect
Esi = 169 GPa, Epol = 164 GPa 431 -382 No effect
)si = Uoly = 0.222 419 -420 No effect
EsiN = 160 GPa 160 -612 Significant effect, cyy
value unreasonably high
USiN = 0.23 357 -352 Acceptable range
)oxide = 0.15 425 -408 No effect









After significant research on the material parameters, the following values were found

acceptable, which were used for most of the simulations in this work, unless specified.

The mobility calculations from stress results obtained from the acceptable parameters

were checked against the E-test published data and both the results matched within a

small error margin.

Table 2-2: Material Properties at Room Temperature [Mat88, FCG66, Yin03]
Material Young's Modulus 'E' (GPa) Poisson ratio 'u'
Silicon along [110] 169 0.222
Silicon along [111] 186 0.222
Polysilicon 164 0.222
Germanium 139 0.25
Oxide 72 0.15
Silicon Nitride 300 0.23
Tungsten 409 0.28
Si0.83Ge0.17 163.7 (linearly interpolated 0.222 (same as that of Si)
between Si and Ge)

2.5 Summary

This chapter starts with the basics of engineering mechanics, the concept of stress

and strain, and their components. The linear elastic property of solids is explained by an

example of a spring. This is followed by the explanation of Hooke's Law, and its

mathematical interpretation. Next, the details of FLOOPS are discussed highlighting its

key features and tools. The working of FEM, boundary conditions and approximations

used for 2D simulations are explained. Finally, the preliminary simulations to observe the

stress sensitivity to material properties are discussed along with observations. In Chapter

3, the stress generation techniques in leading edge advanced CMOS will be discussed in

depth along with more simulation cases.














CHAPTER 3
STRESS GENERATION TECHNIQUES IN ADVANCED CMOS

In the nanometer regime, biaxial stress has been the conventional method to strain

the MOSFET channel. Recent studies in the field of uniaxial process-induced strain have

revealed significant advantages over its biaxial counterpart. In this chapter, the methods

to induce both the types of strain in the MOSFET channel will be discussed.

3.1 Types of Process Induced Stresses

The residual stresses present in thin films after deposition can be classified into two

parts: 1) thermal mismatch stress and 2) intrinsic stress. Residual stresses will cause

device failure due to instability and buckling if the deposition process is not controlled

properly.

3.1.1 Thermal Mismatch Stress

Thermal mismatch stress occurs when two materials with different coefficients of

thermal expansion are heated and expand/contract at different rates. During thermal

processing, thin film materials like polysilicon, Si02, silicon nitride expand and contract

at different rates compared to the silicon substrate according to their thermal expansion

coefficients. The thermal expansion coefficient, aT, is defined as the rate of change of

strain with temperature. Its unit is microstrain/Kelvin (ge/K) [SenOl].

de
aT (3-1)
dT

The thermal mismatch strain generated into substrate upon skewing the temperature by

AT, is given by









ET = -asubAT (3-2)

The thermal mismatch strain in film is given by [Fre03]:

Ef,i .match = (cTf aTs )AT (3-3)

where aTf and aTs are thermal expansion coefficients of film and substrate respectively.

Finally, the thermal mismatch stress is related to strain by:


fs mismatch K f f,mismatch (3-4)
1-v

where v is the Poisson's ratio and Efis the Young's modulus of the film.

3.1.2 Intrinsic Stress

Intrinsic stress is a type of residual stress, generated due to factors such as

deposition rate, thickness and temperature. During deposition, thin films are either

"stretched" or "compressed" to fit the substrate on which they are deposited. After

deposition, the film wants to be "smaller" if it was "stretched" earlier, thus creating

tensile intrinsic stress, and similarly compressive intrinsic stress if it was "compressed"

during deposition. The intrinsic stress generated due to this phenomenon can be

quantified by Stoney's equation by relating the stress to the substrate curvature as

[Fre03]:


Ea = (3-5)
6.(1 us, ).R h

where Esi and usi are Young's modulus and Poisson's ratio of Silicon, hsi and hf are

substrate and film thickness, and R is the radius of curvature of the substrate.








3.1.3 Dopant Induced Stress
When a dopant atom is introduced in silicon substrate through ion implantation or

diffusion, a local lattice expansion or contraction will occur depending on the varying

atomic sizes and bond lengths of the atoms [Ran05].


Figure 3-1: Lattice contraction due to boron atom and lattice expansion due to
germanium atom [Ran05].
Figure 3-1 illustrates the lattice contraction and expansion for boron and

germanium atoms doped into silicon substrate. The stress generated due to boron doping

is a case of technical importance, which will be studied with the understanding of

simulation results in the next chapter, while the biaxial stress generated due to SiGe will

be discussed in the following sections.

3.2 Biaxial Stress Generation Technique
A widely adopted method to introduce wafer-based biaxial stress to enhance

CMOS performance is practiced by growing a silicon film atop relaxed SiGe virtual


00000 00000
00000 00000
00000 o oo 0
00000 00 0
00000 00000
Lattice Expansion from Germanium

00000 0OOO0
00000 00O00
00000 00o00
00000 00000
00000 00000
Lattice Contraction from Boron









substrate. Due to the lattice mismatch between Si and Ge atoms, tensile biaxial stress is

generated in Si film, which enhances the performance of NMOS and PMOS, as can be

seen from Table 3-1. It can be seen from the piezoresistance coefficients of Si for

standard layout and wafer orientation, that NMOS performance (electron mobility) is

enhanced by uniaxial longitudinal tensile and out-of-plane compressive stress (figure 3-

2), while PMOS performance (hole mobility) is enhanced by uniaxial longitudinal

compressive stress. Interestingly, both NMOS and PMOS performance is enhanced by

biaxial tensile stress.

Table 3-1: Longitudinal and Transverse Piezoresistance Coefficients Evaluated for
Standard Layout and Wafer Orientation (Units of 10-12 cm2 dyne-') [Tho04b]
<100> <110>
Polarity 7r1 T 711 __
N or P n11 R712 (711 + 71i2 + 744)/2 (7111 + 7112 744)/2
N-type -102 53.4 -31.6 -17.6
P-type 6.6 1.1 71.8 -66.3


Figure 3-2: MOSFET schematic device cross-section (standard layout)

When a film is grown/deposited on a substrate, the mismatch strain between the

two layers due to the difference in their lattice coefficients is given by [Jai96]:

asub afilm
Smismatch -lm (3-6)
asub










were asub and afilm are the lattice constants of the substrate and heteroepitaxy film. The

stress in the layer is given by [Jai96]:

v+l
So=-2Y mimsmatch (3-7)
v-1

where y is the shear modulus of elasticity and v is the Poisson's ratio.

When a silicon film is deposited on SiGe buffer layer, the film is forced to adopt

the greater lattice constant of the SiGe, hence the Si film is under biaxial (longitudinal

and transverse) tension, whereas it exhibits an out-of-plane compressive component. This

effect is well illustrated in figure 3-3 and figure 3-4.

Silicon "Strined' silicon











Silin Silion
gerrmanium germngirm
Figure 3-3: Steps in creating biaxially strained silicon film atop SiGe layer















Graded SiGe Layer

Figure 3-4: Traditional approach to enhance device performance illustrating biaxial
tensile stress in MOSFET channel [Boh03]









Figure 3-4 shows the traditional approach of generating biaxial tensile stress in

MOSFET channel to enhance device performance. It illustrates the longitudinal and

transverse tensile stress components in the silicon channel on graded SiGe layer.


3.3 Uniaxial Stress Generation Technique

Uniaxial process strained silicon is being adopted in nearly all high-performance

logic technologies [Tho04b]. Ito et al [Ito02] investigated channel stress by introducing a

tensile nitride capping layer on the device structure. As a result, the channel stress

dependent on the polysilicon gate and spacer dimensions. A predominant method of

introducing uniaxial longitudinal tensile stress is by deposition of CVD silicon nitride

film on the device structure. This enhances electron mobility, thereby improving NMOS

performance. IBM incorporates compressive silicon nitride capping layer to generate

uniaxial longitudinal compressive stress in PMOS channel. With the state-of-the-art

processing technology, up to 1.4 GPa process induced tensile stress is generated inside

SiN film for NMOS while up to 3.0 GPa compressive stress has been exhibited for

PMOS [Bay05].


Tensile Nitride Compressive Nitride


stress


Figure 3-5: IBM technology to introduce uniaxial longitudinal stress in CMOS devices
[Moh05]









Figure 3-5 portrays dual stress liner process architecture with tensile and

compressive silicon nitride capping layers over NMOS and PMOS respectively.

Similarly, Intel's technology also implements tensile Si3N4 (silicon nitride) capping for

n-channel devices. The p-channel device performance is enhanced by using selective

SiGe layer as source/drain regions (figure 3-6). The lattice mismatch in the heterolayer

compresses the silicon lattice, which consequently compresses the device channel. For

17% Ge concentration, a compressive stress of 1.4 GPa is generated inside the SiGe layer

[Bay05]. All simulations in this work are carried out by modeling the lattice mismatch

stress as the intrinsic stress and then balancing the forces to evaluate the channel stress.

I Intel's 90nm Technology






G






Selective SiGe S-D Tensile Si-N4 Cap

Figure 3-6: Intel's strained silicon technology [Boh03]

3.4 Effect of Varying Geometrical Parameters

The effect of varying geometrical parameters on channel stress and thereby on

carrier mobility has been an interesting research topic in strained-silicon nanoscale

devices. The work by Pidin et. al. [Pid04] highlights some of these effects by front-end









process-simulations. An in depth review of these cases of technological importance are

explained in this section.

3.4.1 Critical Dimension Scaling

The most important parameter that scales with each technology generation is the

critical dimension of the physical gate. The channel stress increases as the gate length is

scaled since the channel is in closer proximity of the tensile capping Si3N4layer for

smaller critical dimensions. For the current 90-nm node with the standard 140 nm gate

thickness, 80 nm tensile SiN cap and nitride spacers, the simulated channel stress

component values are 5xx=353 MPa, oyy=276 MPa. The trend of future nodes can be seen

from figure 3-7, assuming all other dimensions remain unchanged.


500 i i
450 -Tensile Nitride

400 140 nm
(\ -35 Poly gat I
350 ,
S- -" 11-30 nm
(r* Critical
S300 dimension

250 NMOS

S 200 1
,-
en 150
c no spacers
o0
100
with 30 nm
50 nitride spacers
with 30 nm
0 oxide spacers
0 50 100 150 200 250 300 350 400 450 500
Critical dimension (nm)
Figure 3-7: Longitudinal channel stress component values for different critical
dimensions for oxide, nitride and no spacers.









It can be seen that for oxide spacers, the channel stress is lower than for the nitride

spacers because tensile nitride cap relaxes as it pushes against the softer oxide spacers

while balancing the forces. This causes lower stress to be transferred into the channel.

The nitride film is able to transfer stress to the channel because an edge-force is

developed as the film goes over the spacer and gate geometry [Cea04]. An important

observation from the results is that it is difficult to strain long-channel devices compared

to their short-channel counterparts using tensile nitride capping layer. This is an

important consideration the circuit designer should take into account while designing for

optimum circuit performance.

3.4.2 Polysilicon Gate Scaling

With every technology node, the aspect ratio (ratio of length to height) of the polysilicon

gate has increased since thicker gates yield higher channel stress for n-channel

MOSFETs. An interesting trend observed while scaling the gate thickness is that beyond

a certain value, increasing the aspect ratio is not beneficial. Figure 3-8 illustrates the

issue. The graph shows that increasing the aspect ratio initially assists in boosting the

stress transferred into the device channel from tensile nitride cap, but beyond 150 nm

gate thickness, the stress rolls off and remains unchanged. It can be concluded that

increasing gate thickness beyond this value only increases the process complexity and

deteriorates device performance due to problems like fringing fields. The current 90-nm

technology devices have a gate thickness of 100-140 nm. One more interesting

observation from the graph is the effect of roll off point for devices without spacers. This

case can be understood as a device with overall smaller gate length. The stress slope is

steeper initially, but it rolls off at a prematured gate thickness of -100 nm compared to









the geometry with spacers In addition, the maximum stress extracted at this value is

lower than the spacer case.


400

350 no spacers

300 '

STensile Nitride




"o 1c I M--30 nm
3 150 /L =45 n1 *
S/ with spacers
-3 NMOS

50


0 50 100 150 200 250 300
Gate thickness (nm)
Figure 3-8: Effect of scaling polysilicon gate thickness on NMOS channel stress

3.4.3 Effect of Buffer Layer on NMOS Channel Stress

A common practice to reduce the font-end process generated defects is to use an

unstressed thin silicon nitride buffer film over the structure. This buffer (liner) film, if not

properly deposited, proves to be detrimental to the channel stress in NMOS.

The tensile nitride capping layer needs to be in close proximity to the substrate (ideally

directly onto the substrate) to stress the device channel. Figure 3-9 reveals the reduction

in longitudinal stress upon increasing the liner thickness. Similarly, the out-of-plane

compressive stress component, which is also significant in improving n-channel device

performance, is reduced upon depositing thicker liner layers.










350
Tensile Nitride

%Buffer (liner)
S Layer 140 n
? 300
S1 30 nm
Eg \c A Lgate

OT 250 N IVMOS
I-c



0 200 C /r
11 LU=70 "m

L,=110 nm

150
0 100 200 300 400
Buffer layer thickness (OA)
Figure 3-9: Effect of increasing buffer (liner) layer thickness on NMOS channel stress

3.4.4 Effect of Salicide

Salicides are essential for good contacts with the device terminals. Since salicides

are of different material than silicon, it is worth exploring the effect of salicide on the

channel stress. Modern process technologies have nickel salicide (NiSi) for the contacts

whereas formerly, cobalt salicide (CoSi) was used. Both the salicides have the same

material properties (Young's modulus = 161 GPa, Poisson ratio = 0.33) [Lie03, Hsi92].

Salicide thickness can range from 50 A 200 A. The effect of salicides is shown in

Table 3-2. Since the salicide has material properties almost same as that of silicon, its

presence does not make any significant effect on the stress introduced into the channel.









Table 3-2: Effect of Salicide on NMOS Channel Stress
Salicide thickness (oA) gxx (MPa) Gyy (MPa)
0 349 -322
50 348 -332
100 349 -333
150 351 -330
200 352 -330


3.5 Summary

In this chapter, the sources of strain in MOSFETs are discussed. This is followed

by a brief understanding of different types of stresses, their physics and mathematical

modeling. Next, the state-of-the-art stress generation techniques, for both wafer-based

biaxial and locally-induced uniaxial stresses are discussed. Finally, the effects of scaling

different geometrical parameters for n-channel devices are explained along with

simulation cases. In next chapter, the cases of technical importance for leading edge

CMOS technology will be studied.














CHAPTER 4
CASES OF TECHNOLOGICAL IMPORTANCE AND RELATED ISSUES

In this chapter, cases of technological importance in advanced strained silicon

device technology will be investigated. After understanding the stress generation

mechanisms, physics and mathematical modeling described in the previous chapters, we

can expand our discussion to various issues that need to be addressed with due

understanding to extract the desired CMOS performance enhancement. We initiate the

cases by exploring the issues in both biaxial and uniaxial stress generation methods, and

then continue with discussion of novel stress engineering mechanisms.

4.1 Strained-Silicon-On-Insulator (SSOI)

A large amount of research is being conducted in exploring the possibility of

including biaxial strained-Si in mainstream CMOS process to enhance device

performance [Hoy02, Rim]. A novel approach in this direction is to fabricate ultra-thin

strained-Si layer on SOI, called strained-silicon-on-insulator (SSOI) [Rim03], thereby

complementing their individual advantages. At the future advanced process nodes of 65

nm and below, performance and power consumption issues arise due to bulk silicon's

higher leakage currents. SSOI technology has proven thus far to be a promising variation

to deal with these issues. The process complexity of fabricating SSOI structure involves

transferring a strained-Si/relaxed SiGe hetero-layer on a handle wafer, followed by

selective etch-back of SiGe to leave SSOI structure [Abe04, Chr05]. A homogeneous

stress of 1.5 GPa has been exhibited by Soitec Group's [Soi92] industrially manufactured

SSOI wafers with a 200 OA Si layer.

















1600
S-W1.0 P


1200

a 1000 20 nm
S0 L Tnm
800

1 600
60 VfW=1.0 Pm
I 400 E E 1
CO LP LOI
2000

-500 -400 -300 -200 -100 0 100 200 300 400 500
Distance from center (nm)
Figure 4-1: Stress relaxation in 200 A strained-silicon on insulator and on SiGe for
different island sizes. The curves in circle are for mentioned strained-silicon
thicknesses for 1.0 ipm island

The matter of concern in this technology is the stress relaxation due to generation

of free surface while forming STI trenches, which leads to wasted active area along the

channel width. Consequently, this increases the actual required transistor width than

estimated, if the stress relaxation is not accounted for. Adding to this issue, it can be

inferred from the simulations that there is a significant relaxation in the biaxial stress

when the film is on oxide compared to atop a SiGe layer. The reason being that SiGe has

a much higher Young's modulus compared to oxide. Figure 4-1 shows the transverse

stress profile along the island width from its center for both these cases: strained-silicon-

on-oxide and on SiGe. The initial stress in the Si film was assumed to be 1.6 GPa and the









relaxation after etching the islands was studied. The simulation results for three different

island sizes: 0.25 gim, 0.5 gim, 1.0 gim, reveal the center has maximum stress in all the

cases. For 0.25 gtm island, there is a 21% stress relaxation, for 0.5 gim, it is 10% and for

1.0 gm, its only 3%. Hence, it can be noted that as the island size increases, the stress

relaxation at the center drops, but this requires wider devices. It can be seen that there is a

significant wastage of silicon before the channel stress approaches a desired value to give

optimum performance enhancement. One more observation from the graph is that the

island regains higher peak stress value quickly for thinner silicon compared to the thicker

silicon layers. Therefore, a way out to minimize silicon wastage for optimum mobility

enhancement is to fabricate devices on thinner strained-silicon membranes.

4.2 Uniaxially Strained Device Issues

Uniaxial front-end process induced stress is being widely adopted in almost all

logic technologies because of its edge over the biaxial counterpart [Tho04b]. A caveat

that might invoke the attention of VLSI process and design engineers will be discussed in

this section.

4.2.1 Effect of Varying Silicon Nitride Thickness

Chapter 3 explains the concept of improving electron mobility in n-channel devices

by depositing a tensile silicon nitride capping layer over the entire structure. It has been

understood that increasing the Si3N4 film thickness increases the stress in the channel

[Pid04]. This holds true up to a certain thickness in a legged gate structure, which are

widely used in logic technologies. The effect of increasing the nitride thickness, keeping

a constant space between two NMOS devices in stacked gate structure, is presented in

figure 4-2. The devices were laid apart at a distance of 110 nm and stress value in the









center device channel is plotted in the figure. Initially, both the stress components,

necessary to boost NMOS performance, increase with nitride thickness.


350 1 1 i i i i i i


300 Out-of-plane (Compressive) Long l
\ ,,..Longitudinal (Tensile)


250 1


200

150 *








Nitride thickness (nm)
Figure 4-2: Effect of increasing silicon nitride thickness on channel stress components

At 45 nm nitride thickness, "pinch-off' occurs when nitride cap of two adjacent gates

merge, which abruptly reduces the longitudinal component, whereas the out-of-plane

component remains constant. Then after, the longitudinal component value increases

again slowly as the nitride becomes thicker. This behavior hints that silicon nitride

requires a certain overlap over the source/drain regions to strain the channel, denial of

which proves detrimental to the stress in the channel. One more crucial outcome of the

graph in figure 4-2 is that the longitudinal stress reaches a peak value for a very thick

nitride cap. This property can be exploited in front-end processing by using silicon nitride

as the first-layer dielectric, which is normally -1000 'A thick. By doing so, both the
as the first-layer dielectric, which is normally -1000 A thick. By doing so, both the











needs are sufficed, viz. extracting maximum channel stress and forming a first-layer

dielectric. The structure, generated by ISE-FLOOPS, in the "pinch-off' condition and for

different nitride thicknesses can be viewed from figure 4-3.


SW nm 50 nm

o SiN SiN cap
110nm
I- 110 nm

*. TST1 STI STI STI
Si Bulk Si Bulk


,*. '04 i
-C I




E
-al -
S SiN cap "


110 nm
S TI STI
Si Bulk

0.5

Figure 4-3: Stacked gate structures generated by ISE-FLOOPS for different silicon
nitride cap thicknesses

4.2.2 Multiple Gate Structure

A case of technical importance, similar to the one discussed in section 4.2.1, is to

examine the effect of varying the space between adjacent gates in a multiple/stacked gate

structure. The simulation results for this case, are plotted in figure 4-4, for both n-channel

and p-channel devices with 35 nm gate length and 140 nm polysilicon gate thickness.

Again, the effect of "pinch-of' of nitride cap discussed in previous section can be viewed,

where the stress for 30 nm nitride cap exceeds that for 100 nm cap until approximately 70

nm space. This behavior asserts the conclusion that the cap of a given thickness requires a









minimum space to strain the device channel maximally. One more point to be noted is

that beyond a certain space, the stress saturates in the channel; which means it is futile to

have a bigger source/drain diffusion area than this roll-off point. The same effect can be

seen for PMOS, where the stress boosts up initially as the SiGe volume (space) increases,

and beyond a roll-off point, the stress saturates. Also, as expected, the stress values are

higher for smaller spacers since the SiGe is in closer proximity of the channel. The

junction depth for PMOS devices is assumed to be 0.12 nm.


300250200150 100 50
space (nm)


100 00- -
i200 300400 500 600
SiGe space (nm)


Figure 4-4: Effect of varying space between adjacent gates for different Si3N4 cap
thicknesses for NMOS, and different spacer sizes for PMOS

4.2.3 Stress Relaxation Due to the Presence of STI

Shallow Trench Isolation (STI) is primarily used in CMOS technology to isolate n-

channel and p-channel devices. STI is formed by etching shallow trenches and filling


900.

800"

700-

600-

500"

400-

300-

200"

100"

0










them with oxide dielectric. In this section, the effect of stress relaxation in the devices

adjacent to the STI is explained. Figure 4-5 and figure 4-6 depict the NMOS and PMOS

multiple-



0.2
45 nm


E T- a
c SiN cap

0 -5570 04 ,3821 3 047 -6510
-303 -381 -303


36-3 361-2 361-3
0.2





0.4 4.1E+08
2.8E408
1,5E+08
1.4E+07
0.6 0.8 1 1.2 1.4 -1.2E+08
X (Lm) -2.5E+08
Figure 4-5: Nested NMOS structure illustrating the stress relaxation due to the presence
of STI

gate structures with three devices and STI at the ends. It shows that the center device has

the maximum stress compared to the ones near STI. In the NMOS case, a portion of

intrinsic nitride stress is lost due to the softer oxide in STI, which leads to lower stress

introduced inside the device channels adjacent to STI. The same effect is seen in the

PMOS case, where SiGe source/drain regions push against the channel to induce a

compressive stress. In the devices adjacent to STI, the source/drain regions of these

devices push against softer oxide on one end, which results in SiGe losing some stress,










leading to lower stress in these devices. Both these effects are illustrated in figure 4-5 and

figure 4-6, where the first value shows the longitudinal component and the second value

is the out-of-plane component of the stress at that point. An interesting takeaway from

figure 4-6 is the notably lower stress near source/drain surface. It is much lower than the

initial intrinsic stress, which leads to lower point-defects during fabrication.


-0.2
45 nm
-E



-413 -461 -284 13
-458 Si.- Ge. ,- -574





91

0.4
StreXX

23
1,6E+08
0.6 -2A4E+08
-6,5Et08
I I I I I I I I .5 E + 0 8
0.4 0.8 1 1.2 1.4 1. -1,OE+09
X (pm) 1,4ED9
Figure 4-6: Nested PMOS structure illustrating the stress relaxation due to the presence
of STI

4.2.4 Stress Relaxation due to Contact Etching

An interesting issue that arises in process-induced uniaxial strained silicon devices

is the effect of etching contact holes in NMOS devices. This issue has been discussed by

Cea et. al. [Cea04], where the effect of etching a portion of nitride cap to make contact

holes is explained. When contact holes are etched, it removes a significant amount of









nitride, which leads to channel stress relaxation in longitudinal and out-of-plane

directions. This effect is corroborated by figure 4-7, where the relaxation is plotted

against contact hole distance from the spacer edge. As discussed in previous chapters, the

out-of-plane component of the channel stress primarily arises primarily due to the nitride

overlap over the spacers. Hence, it is not affected much due to the holes. The channel

regains peak stress when contacts are distant from the channel.


320



280 O ut-of-plane component (Compressive)

260 'Longitudinal component (Tensile)



S240 5 6 0 8

90Distance from spacer edge (nm)







S100 200 300 400 500 600 700 8itride
Distance from spacer edge (nm)
Figure 4-7: Stress relaxation due to contact holes in NMOS strained silicon device with
45 nm Lg,,t,, 140 nm gate thickness and 80 nm nitride cap thickness

A better understanding of this effect will be obtained by simulating the case in a 3D

simulator, where contacts are simulated as holes unlike of infinite depth in the 2D

simulator.









4.2.5 Effect of Raised Source/Drain in PMOS Device

This section explores a strategy to increase compressive stress generated by

embedded SiGe source/drain regions in a PMOS device. The topology of the source/drain

regions can assist to increase the stress and this property is well exploited during the

front-end processing. Raising the SiGe source/drain regions up to a certain extent

transfers higher stress to the channel, thereby further improving the mobility of holes.


1600

1500 Gate
3 height
140 Si1x-e0 Sil Ge 120 nm
o [Ge]=30% D Si Bulk
1300

1200
1200 [Ge]=25%

S1100

1000

S 900 Oxide spacers [Ge]=17%
a900 Nitride spacers /

S800 -

700
600 Nitride spacers
0 100 200 300 400 500 600 700 800 900 1000
Step height (OA)
Figure 4-8: Stress boosting in PMOS by increasing SiGe step height for 45 nm gate
length devices.

A general practice in forming spacers is to use prefer silicon nitride versus oxide as the

spacer materials, since nitride has proven to act as a better shield to the gate oxide. The

drawback of this technology is the reduction in potential transfer of compressive stress to

the channel because nitride is a harder material compared to oxide. The effect is clearly









depicted in figure 4-8, which also shows the increase in stress upon increasing the raised

step height. Beyond approximately 300 A of step height, the raised SiGe source/drain

regions do not increase the stress further, and therefore the curve saturates. The figure

also reveals the higher stress induced upon increasing the Ge concentration. Higher Ge

concentration in SiGe compresses the silicon lattice even greater, which is simulated by

higher intrinsic stress inside SiGe regions. In sate-of-the-art nanodevice research, Ge

concentration is increased up to 30%.

4.2.6 SOI vs Bulk Technology

In this section, we shall investigate and compare the stress generated in SOI and

bulk devices. Ghani et. al. [Gha03] have reported the PMOS drive current enhancement

by epitaxially grown SiGe source/drain regions on bulk silicon substrates. The

compressive stress generated in the device channel increases with increasing the SiGe

volume in the source/drain regions. Cases along the same line have been discussed in

sections 4.2.2 and 4.2.5, where the SiGe space was increased in former case while SiGe

step height increase was studied in the latter. In this section, the effect of increasing SiGe

depth, in both SOI and bulk silicon, is studied and the results are plotted in figure 4-9.

In the SOI structure simulated, the 70 nm silicon membrane is bonded on an oxide

box thickness of 1000 A. This is followed by selectively etching the source/drain

regions to the required depth, and filled by epitaxially grown SiGe. The plot in figure 4-9

compares the stress generated in SOI vs bulk silicon devices for 45 nm gate length. The

SOI case is simulated with two different Young's modulus of oxide, viz. 44 GPa and 72

GPa. As can be seen, the Young's modulus of oxide does not alter the stress significantly.

Also, the stress in SOI and bulk cases is almost equal for a given source/drain depth.











800


700 '-
7 0 Embedded SiGeqon bulk
E 90 nm
6 00 o production
M 600 1a
a-
SEmbedded SiGe on SOIate
S500 (ESi02=44,72 GPa)\ / SiGe SiG
S. Si bulk
U)
400 Nitride spacers
SGte

S300 iGe 7Onm SiGe
0
(-

200
Si bulk


100 '' '-* '''
0 20 40 60 80 100 120 140
Source/Drain depth (nm)
Figure 4-9: Effect of varying SiGe depth in SOI vs bulk silicon devices

For the current 90 nm node, the standard source/drain depth in bulk silicon devices is 120

nm, which induces approximately 700 MPa compressive longitudinal channel stress,

while the maximum stress extracted out of the standard SOI devices is only about 550

MPa. Thus, the bulk silicon technology yields considerably higher compressive channel

stress for PMOS drive current enhancement. The recent research work published work by

Freescale Semiconductor Inc. [Zha05] reports 40% higher channel stress of PDSOI

devices compared to its bulk counterpart. This result is inconsistent with the simulated

results presented above. A 3D simulation approach with closer process modeling might

lead to consistent results.









4.2.7 Effect on Stress by Boron Doping in p-channel Devices

Boron doping in p-channel source/drain regions introduces a local tensile strain in

the substrate due to its size mismatch with silicon. Boron is smaller in size than silicon

and when it occupies a substitutional lattice site, a local lattice contraction occurs (figure

3-1) because the bond length for Si-B is shorter than for Si-Si [Ran05]. Horn et. al.

[Hor55] reported that a single boron atom exerts 0.0141 A lattice contraction per atomic

percentage of boron in silicon at room temperature. The stress induced in the channel due

to boron doping was insignificant for long-channel devices, but for CMOS transistor

channel lengths in the nanometer realm, this stress plays a significant role in determining

the carrier mobility enhancement. Boron is widely chosen as the p-type dopant due to its

high solubility limit in silicon; at 1100 OC, boron has a solubility limit of 3.3X1020/cm-3

[Jae02]. The simulations are performed by defining the local boron induced lattice

contraction by a tensile intrinsic stress in source/drain regions [Hol93].

1 da(4-1)
ao dNB

where, p = lattice contraction coefficient = 5.19e-24 cm3, NB = boron concentration,

ao = lattice constant.


Therefore, da -3.NB = 8 is the local strain generated inside the silicon lattice. This
a0

strain is compressive, thereby pulling the silicon atoms in the lattice and generating a

tensile stress in the device channel. The tensile intrinsic stress defined in the simulations

can now be calculated by a = -(Esi x E).

Figure 4-10 reveals the amount of tensile stress induced by boron doping at

different concentrations for different channel lengths. For 0.5 am source/drain length and









given boron concentration, as the channel length is varied from 25 nm to long-channel

length of 1.0 jim, the stress in the center of the channel reduces exponentially. The effects

of scaling source/drain length and channel length are explained in depth by Randell

[Ran05]. Longer source/drain regions imply higher number of boron atoms to pull the

channel.


600 -* *

S25 nm
500 t
35 nm
M Gate
S400
Wr P+ P+
e.r $ Si bulk
300
._ 45 nm


S200 0.5 pm


100


0
1 2 3 4 5 6 7 8 9 10
Boron concentration 1020 (cm-3)
Figure 4-10: Effect of scaling boron concentration for different channel lengths, 0.5 .im
source/drain length and 0.12 rm junction depth

As can be seen from the plot in figure 4-10, the problem of tensile stress due to boron

doping is not significant in long-channel devices, where the stress is below 50 MPa for

2X1020/cm-3 boron concentration. The problem alleviates when channel lengths enter

nanometer regime and the boron concentration reaches its solubility limit. The stress in

45 nm channel length and 3.5X1020/cm-3 boron concentration reaches approximately 200









MPa. This tensile stress can be deleterious to the compressive stress induced by

embedded SiGe source/drain and can result in carrier mobility much lower than expected.

Also, the boron solubility in silicon germanium increases much beyond its limit in

silicon. So the dopant stress generation problem proves to be even more significant in

advanced CMOS devices where Ge concentration is expected to be close to 30%.

Methods to counter and suppress the dopant induced stress are important issues under

research.

4.3 Prospective Stress Generation Techniques

Historically, STI stress has been considered detrimental to the device performance

[Sco99, Nan05]. Simulation and experimental results have shown that High-Density

Plasma (HDP) Shallow Trench Isolation (STI) generates a transverse compressive stress

in the channel, which degrades NMOS performance while not affecting PMOS. Despite

its compressive nature and degradation of NMOS mobility, HDP is the most commonly

used gap-fill technology for STI because of processing ease. In 65 nm devices, where

pitch is expected to be less than 200 nm, compressive stress and reduced mobility can

prove to be a major obstacle. Hence, efforts have been made to eliminate this stress. In

this work, use of the high aspect ratio process (HARP) STI [Bay05], which produces a

moderate to high transverse tensile stress, to engineer the device performance is

presented. CMOS performance does not improve with just one type of longitudinal

uniaxial stress along [110] direction. HARP STI, if used for isolating the devices along

their width, induces transverse tensile stress along [1-1 0] direction. From the calculations

of piezoresistance coefficients (Table 3-1) of Si along different dominant directions, it is

obvious that transverse tensile stress can improve CMOS performance. The novel

technique for stress engineering comes along with its own complexities which need to be









dealt with to attain the performance improvement. All issues pertaining to this technique

will be discussed in the following sections.

4.3.1 Stress Variation Along the Device Width

All simulations performed for HARP STI assume an initial intrinsic stress of 1 GPa

in all directions in STI due to its densification. The densification effect of HARP STI

generates an equal intrinsic stress in all directions. The simulations conducted with this

assumption showed an interesting trend where the channel stress exceeded the

intrinsically defined STI stress. This will be termed as "Stress Magnification".


1500


1400


1300 1
Silicon substrate
v9
1200
0)
300 nm
| 1100
m 10 500 nm
^ 1000 *
1-


900
700 nm
800 ,i
-400 -300 -200 -100 0 100 200 300 400
Distance from center(nm)
Figure 4-11: Stress variation along the device width in HARP STI stress engineering
technique

The stress magnifies better if the island is smaller for given STI dimensions. A matter of

concern in using STI for stress engineering is the variation of the channel stress along the









width. This has been shown in figure 4-11. Bigger islands have a higher variation, which

implies the mobility is enhanced differently along the width.

4.3.2 Stress Engineering by STI Depth

Transverse channel stress by HARP STI can be engineered by varying STI depth.

The stress is seen to be a strong function of trench depth up to 400 nm, beyond which it

rolls off (figure 4-12). Here, the STI width and transistor width are held fixed at 300 nm

and 500 nm respectively. The figure also shows the effect of polysilicon gate on top of

the channel before balancing the forces. In this case, there is significantly low amount of

stress generated compared to the former case, since the channel effectively becomes a

buried layer bound from all sides when forces are balanced.


800


700 .1


600 Polysilicon

0 No Poly
2 500


S400C Poly on top
> Silicon substrate

300 '-...


'100 200 300 400 500 600 700 800 900 1000
STI depth (nm)
Figure 4-12: Effect of varying STI depth on channel stress: for free surface and for
polysilicon on top









The case with polysilicon on top can be considered to be analogous to the stress

generated by embedded SiGe source/drain in PMOS, except that SiGe induces a

compressive stress.

4.3.3 Stress Engineering by STI Width

One approach to engineer the transverse tensile channel stress is by modulating STI

width. Higher STI width implies higher amount of STI to pull the channel. This case is

analogous to the case discussed in section 4.2.2, where the SiGe space is scaled to extract

higher channel stress. For the STI case, the results are plotted in figure 4-13. It can be

inferred from the figure that the stress increases up to 500 nm STI depth, beyond which

the stress is indifferent to STI depth.


2500



2000 5
.-


1500
200 nm






500
1.0 pm


0 250 500 750 1000 1250 1500
STI Width (nm)
Figure 4-13: Effect of varying STI width on channel stress for different transistor widths









The practical STI depth for current processing technology is approximately 500 nm,

which suffices the need to maximize the channel stress. As expected, the figure shows

lower stress for wider transistors. All results are obtained in the center of the device width

and 100 A below the surface.

4.3.4 Stress Dependence on STI Topology

The STI topology is another factor which can change the stress expected to be

introduced by the HARP STI densification process. A recessed STI surface can

undermine the stress in the channel. Figure 4-14 shows -80 MPa stress reduction for a

500 A recess in the STI surface. Hence, due importance should be given to the STI

topology while polishing the surface.


780

770

760

L 750

10740

-0 730

e 720

6710
I--
700

690 Silicon substrate
680
-500 -400 -300 -200 -100 0 100 200 300 400 500
STI step height (OA) --
Figure 4-14: Stress dependence on STI topology









4.3.5 Stress Dependence on STI Densification

The intrinsic stress in the STI can be increased by increasing the densification of

atoms in the HARP STI gap-fill. Thereby, the densification is purely a function of

process technology adopted for CVD deposition of oxide in the isolation trenches. For a

given STI and channel dimension, the channel stress varies linearly with the STI intrinsic

stress, which can be viewed from figure 4-15.


800


700 2


600
CO
500


S400
CO
300


200


100
200 300 400 500 600 700 800 900 1000
STI Intrisic stress (nm)
Figure 4-15: Stress dependence on HARP STI intrinsic stress

4.4 Summary

In this chapter, stress issues pertaining to strained silicon devices were discussed

and the explanations were corroborated with the simulation results. The chapter

commenced by explaining the major issues in the state-of-the-art biaxially wafer based

strain technique, followed by a variety of issues in uniaxial strained silicon devices. The






50


issues ranged from structural geometry, stress relaxation by STI, scalability and

comparison between SOI and bulk technologies. This was followed by addressing the

important issue of dopant-induced stress. Finally, the prospective stress engineering

techniques were explored, and issues arising in the technique were discussed. In the next

chapter, a summary of all chapters will be presented, along with recommendations for the

future work.














CHAPTER 5
SUMMARY, CONCLUSIONS, AND RECOMMENDATIONS FOR FUTURE WORK

5.1 Summary and Conclusions

In this thesis, a wide range of issues related to strained silicon technology, a vector

to extend Moore's Law, has been investigated. A set of simulations targeted to study and

maximize stress in CMOS devices was carried out, and the results were presented with

explanations.

In Chapter I, the history of CMOS devices was discussed, starting with Moore's

Law, its implications on the semiconductor industry, and its predicted pathway. This was

followed by the discussion of the driving motivations to study desirable strain in

MOSFETs to extend Moore's Law. A survey of the existing literature on strained silicon

devices was presented along with the explanation of the physics behind performance

enhancement in the devices. The state-of-the-art techniques to induce uniaxial and

biaxial strain in the devices were introduced along with their advantages and drawbacks.

Chapter II introduced the basic concepts of engineering mechanics, stress, strain

and their relationship. The governing law, called Hooke's Law, which describes the

motion of spring in elastic limit, was introduced and explained mathematically with an

example of a spring. The concept of linear elasticity was introduced. This was followed

by the introduction to the Finite Element Method (FEM), an approach to discretize and

solve many complex mechanical engineering mechanics problems. To understand the

limitations of a system, the boundary conditions and approximations used for 2D

simulations were discussed. The 2D simulator, FLOOPS, used to carry out simulations in









this thesis, was introduced highlighting its key features and tools. Finally, the preliminary

simulations to observe the channel stress sensitivity to material properties were discussed

along with their analysis.

Chapter III deliberated on the sources of strain in MOSFET channel. This was

followed by different types of stress, their physics and mathematical modeling. Next, the

state-of-the-art stress generation techniques, for both wafer-based biaxial and locally-

induced uniaxial stresses were discussed. The two different methods to strain the PMOS

channel, by SiGe source/drain regions and by compressive nitride capping layer, were

presented and explained pictorially. The physics behind strain generation in NMOS due

to stressed silicon nitride capping layer and in PMOS by silicon germanium source/drain

regions were explained. NMOS channel is stressed by tensile nitride cap since an edge

force is developed as the film passes over the spacer and the structure geometry. The

silicon lattice in PMOS source/drain is compressed by the introduction of Ge, a larger

atom than Si, which in turn compresses the channel, thereby enhancing the mobility of

hole carriers. The piezoresistance coefficient table for standard layout and wafer

orientation corroborates the reasoning behind NMOS performance enhancement due to

tensile longitudinal stress and PMOS performance enhancement due to the compressive

stress. Finally, the effects of scaling different geometrical parameters for n-channel

devices were explained along with simulation cases. The longitudinal component of

channel stress increases along with the scaling of NMOS critical dimension. Nitride

spacers are better acquainted to transfer the nitride capping stress to the channel

compared to oxide spacers, since nitride is a harder material with a higher Young's

modulus. The polysilicon gate thickness also plays an important role in determining the









n-channel device stress. Initially, as the gate aspect ratio is increased, the channel stress

increases. However, beyond 150 nm gate thickness for spacer case, and 100 nm for no

spacer case, the stress saturates and does not respond to increasing the gate thickness

thereafter. The thickness of buffer nitride film, used to reduce the process-induced

defects, is equally significant to engineer, to have the desired mobility enhancement. As

the liner thickness increases, it becomes difficult for the tensile nitride cap to stress the

channel.

Chapter IV presented cases of technical importance in advanced strained silicon

device technology and the related issues. The cases are important to design and process

engineers. Historically, mobility of holes is considered to be approximately half that of

electrons. Due to this reason, PMOS devices are considered to be slower than NMOS,

and hence the former are designed to be twice as wide as NMOS to have symmetrical rise

and fall times in CMOS technology. Front-end process induced stress has been reported

to enhance stressed to unstressed hole and electron mobility ratios up to 4 and 1.7

respectively [Hoy02]. This implies that in future generations of CMOS strained silicon

devices, for symmetrical rise and fall times, PMOS need not be twice as wide as NMOS.

The process flow complexity to induce wafer-based biaxial stress in the state-of-the-art

SmartCut technology [Soi92] was discussed and the issue of stress relaxation caused due

to free surface generation while etching STI trenches was explained at length. The

relaxation causes the stress to reduce near the edges of silicon membrane, and hence this

relaxation should be accounted for when sizing the transistors. The advantages of using a

thinner membrane to minimize stress relaxation were discussed along with simulation

results.









A set of cases pertaining to uniaxial locally-induced stress was discussed thereafter.

The effect of scaling up the nitride capping layer thickness in legged-gate NMOS devices

separated by a certain distance was seen. The channel stress increases up to a certain

value, and reduces dramatically at "pinch-off' of nitride layer. Thereafter, increasing the

nitride cap thickness slowly increases the channel stress. The use of stressed silicon

nitride as the first layer dielectric, between device and first metal layer, was proposed to

maximize the channel stress. This was followed by the discussion of a similar case, where

the space between adjacent devices in a legged-gate structure was scaled in both types of

MOSFETs, and it was inferred that the stress in both the devices increases with

increasing the space. Again, the effect of silicon nitride "pinch-off' was observed in

NMOS devices. These are some of the prime challenges to be faced at the smaller feature

sizes, where source/drain regions will be made smaller to increase the packing density of

the devices.

Next, the stress variation in different devices in a legged-gate structure due to

presence of STI was discussed. STI relaxes and absorbs some stress from the adjoining

devices; thereby the carrier mobility enhancement will be different in different devices.

This is another important consideration the design engineers should take into account

during circuit design. Another issue that leads to stress reduction in NMOS device (and

PMOS device in dual stress liner technique) channel is the effect of etching contact holes

for the source and drain connection. The contact holes remove significant amount of

nitride, which relaxes the channel stress. The effect has been discussed by Cea et. al.

[Cea04] and the difference between 2D and 3D simulated results has been explained. A

2D simulator assumes the contacts are of infinite depth rather than the 3D case that takes









all dimensions of the holes into account. The effect of raising the embedded SiGe

source/drain regions to compress the channel higher, has been discussed in the following

section. The raising is beneficial up to 300 oA, beyond which the stress is indifferent to

the step height. Due to processing conditions, nitride spacers are preferred over oxide

spacers, but this hinders the SiGe source/drain regions to stress the channel. Further,

increasing the Ge concentration increases the stress in the source/drain along with the

longitudinal compressive channel stress. Modem processes have incorporated up to 30%

Ge concentration in the source/drain to achieve ultra shallow junction depths for the

minimal feature size transistors. Boron diffusivity has been reported to get retarded in

presence of SiGe compared to single crystal silicon [Zan03].

The difference in the stress generated in p-channel devices in bulk and silicon-on-

insulator (SOI) technology has been simulated. The presence of oxide box does not make

significant differences in the stress transferred to the channel. The source/drain depth in

PDSOI devices is restrained by the silicon thickness, and hence the maximum it can

reach in modern processes is up to 70 nm. This limits the SiGe volume, and hence the

current 90 nm technology devices on bulk silicon exhibit higher stress than the SOI

devices. An important issue of dopant induced stress in p-channel MOSFET device is

discussed in depth, and the detrimental longitudinal tensile stress generated due to B

doping has been discussed for short-channel and long-channel devices. From the

piezoresistance coefficient table, it can be seen that tensile longitudinal stress degrades

PMOS hole mobility. The tensile stress is prominent in short-channel devices where the

source/drain regions are in close proximity to the channel and the B dopant concentration

is approximately 3 x 1020 cm-3. The tensile stress offsets some of the compressive stress









induced by the SiGe source/drain regions, and hence the hole mobility attained is lower

than the expected value.

Finally, the prospective stress generation techniques by engineering the transverse

longitudinal stress by HARP STI have been discussed. Various issues pertaining to this

technique have been explained and seconded with simulation results. The stress variation

along the device width in long-channel devices can be of prime concern, since it gives

different carrier mobility at different points along the width. It is equally important to

engineer STI depth and width to maximize the stress for the given device dimensions.

The effect of "Stress Magnification" in HARP STI stress generation technique has been

explained, where the channel stress exceeds the intrinsically defined STI stress in absence

of polysilicon on top during the process flow. The topology and densification of STI

should be accounted for to attain the desired stress.

5.2 Recommendations for Future Work

Strain generation techniques have been discussed and a wide range of issues

affecting the strained silicon devices have been simulated as a part of this thesis work.

The emphasis for this work was to highlight the issues which the industry needs to

account for in developing the process and devices. At each technology node, smaller

feature sizes will be incorporated, which will demand more precise modeling of the front-

end process to predict the device behavior. As we deal with materials at the atomic levels

in future technology nodes, many different processing techniques are being explored to

meet the requirements of the International Roadmap for Semiconductors (ITRS). The

following work describes some of the recommendations for the future work to achieve

closer simulated results to the fabricated device data.









5.2.1 3D Modeling

A better understanding of issues like contact hole etching, stress relaxation in SSOI

films etc. will be achieved by 3D modeling of the process and device. A good example

illustrating the difference in the results is the 3D modeling of contact holes [Cea04]

where the results obtained by 2D simulator are very conservative and depict a significant

mobility loss compared to the actual loss. All simulation cases for PMOS devices need a

3D approach, where the width of the device is finite and the intrinsic stress defined in the

source/drain regions should be in all three dimensions. The stress generation techniques

using HARP STI should also be simulated by defining the intrinsic stress in all three

dimensions, since the STI densities equally in all dimensions. Some of the 3D simulation

results might reveal that the stress generated in the channel is not purely uniaxial, and that

there is also some biaxial component attached to it. Therefore, it is recommended to

simulate all the cases in a 3D simulator with a very close modeling to the actual process

flow. ISE-FLOOPS v10.0 supports 3D simulations, which is recommended to simulate

all the future work.

5.2.2 Additivity Issue

An interesting issue to explore, which was attempted during this thesis work, is the

stress additivity when a compressive silicon nitride capping layer is deposited over a

PMOS structure with embedded SiGe source/drain. It is worth exploring, if the

compressive stress generated by the individual techniques, actually complement each

other when incorporated together. This requires multiple balancing of forces during the

simulations, first one after PMOS structure sans silicon nitride, and the second one after

deposition of silicon nitride film. This effort should then be extended to simulate the

effect of a nitride cap while raising the step height. It is predicted that initially the stress









would be additive, but as the step height is increased, the impact of compressive nitride

cap on the channel stress would decrease. This effect was attempted to be simulated

during this thesis work, but since ISE-FLOOPS v9.5 does not support multiple

"StressSolve" commands in a single script, it is left as a recommendation for the future

work using ISE-FLOOPSv10.0. The effort to explore the additivity issue should also be

extended to test if all the stress generation techniques, including the prospective ones,

complement each other if implemented together in CMOS structures.

5.2.3 Stress Generation due to Thermal Mismatch and Material Growth

In this thesis work, all stresses are modeled by approximating them to the intrinsic

stress. It is hereby recommended that the thermal mismatch stress during diffusion be

accounted for, since all materials have different thermal expansion coefficients and this

can lead to variation in the stress induced in the channel. Also, the SiGe source/drain

should be simulated with the natural growth profile, and the lattice mismatch stress due to

the material growth should be simulated in its original form. The obtained results should

then be compared against the intrinsic stress approximation results presented in this thesis

work.

5.2.4 Better Understanding of Novel Stress Generation Techniques

It is imperative to understand and closely model the novel stress generation

techniques, like the HARP STI to engineer transverse longitudinal stress, which would

suffice the needs of performance enhancements for future strained silicon devices. The

next step should be to club the existing standard strained silicon techniques with the

novel techniques, and explore the stress additivity in the composite structures.

As can be seen from the discussion in this chapter, there is a wide scope for

exploration in the field of simulating front-end process induced stress to enhance the






59


carrier mobility and thereby extend the Moore's Law. It is hereby recommended that all

the simulation results should be backed with the experimental data to have a better

understanding of strain generation mechanisms in the devices.















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BIOGRAPHICAL SKETCH

Nirav Shah was born on November 3, 1981, in Maharashtra, India. He has loving

parents, Darshana and Shailesh Shah. He received his Bachelor of Electronics and

Communication Engineering in 2003 at S. P. University, Gujarat, India. His hobbies

include traveling, sports and reading.

Nirav Shah joined the Master of Science program in Electrical and Computer

Engineering Department at University of Florida in 2003. He has been working as a

research assistant with Dr. Scott Thompson since 2004.