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Time-Based Analog-to-Digital Converters

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TIME-BASEDANALOG-TO-DIGITALCONVERTERS By DAZHIWEI ADISSERTATIONPRESENTEDTOTHEGRADUATESCHOOL OFTHEUNIVERSITYOFFLORIDAINPARTIALFULFILLMENT OFTHEREQUIREMENTSFORTHEDEGREEOF DOCTOROFPHILOSOPHY UNIVERSITYOFFLORIDA 2005

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Copyright2005 by DazhiWei

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Tomyfamily.

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ACKNOWLEDGMENTS First,Iwishtoexpressmysinceregratitudetomyadvisor,Dr.JohnHarris, forthethingshetaughtmeovertheyears,hissupportandencouragement. Withouthispatienceandguidancethisworkwouldhavebeenimpossible.I wouldliketothankDr.JoseC.Principe,Dr.RobertM.Fox,andDr.Timothy Davisforbeingonmycommitteeandtheirfrequenthelpfuladvice.Iwouldalso liketothankDr.JoseA.B.Fortesforhissupportinthebio-nanocomputing project.IalsoappreciatethehelpfuldiscussionsfrompeopleintheComputational NeuroengineeringLab. Iamdeeplygratefultomyparents,brotherandsisterfortheirsupportand love.Thanksarealsoextendedtomydearson,Frank,forhiscomingtothisworld andmakingthisworkmoremeaningful.Last,Iwouldliketothankmydarling wife,XiaoyanZhang,forherloveandbeliefinme. iv

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TABLEOFCONTENTS page ACKNOWLEDGMENTS ............................. iv LISTOFTABLES ................................. viii LISTOFFIGURES ................................ ix ABSTRACT .................................... xii ChAPTER 1INTRODUCTION .............................. 1 1.1Background .............................. 1 1.2Motivation ............................... 2 1.3DissertationStructure ........................ 3 2TIME-BASEDANALOG-TO-DIGITALCONVERTERS ......... 5 2.1Introduction .............................. 5 2.2SignalRepresentation ......................... 5 2.3ConventionalAnalog-to-digitalConverters(C-ADCs) ....... 6 2.4Time-basedAnalog-to-digitalConverters(TB-ADCs) ....... 8 2.5ComparisonBetweentheC-ADCandtheTB-ADC ........ 9 3SPIKINGNEURONSIGNALREPRESENTATION ............ 12 3.1Introduction .............................. 12 3.2BiologicalNeuron ........................... 12 3.3Integrate-and-reNeuronModels .................. 14 3.3.1Integrate-and-reNeuronModel ............... 14 3.3.2LeakyIntegrate-and-reNeuronwithRefractoryPeriod Model ............................ 16 3.3.3Integrate-and-reNeuronwithThresholdAdaptation ... 17 3.4Summary ............................... 18 v

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4RECONSTRUCTIONFROMSPIKINGNEURONMODELS ...... 19 4.1Introduction .............................. 19 4.2DirectLow-passFilteringReconstructionMethod ......... 19 4.3WLPKReconstructionMethod ................... 20 4.3.1ReconstructionfromtheIFneuron .............. 21 4.3.2ReconstructionfromLIFneuronwithrefractoryperiod .. 24 4.3.3ReconstructionfromtheIFneuronwiththresholdadaptation .............................. 24 4.4DiscussionofOtherReconstructionMethods ............ 25 5PRACTICALISSUESRELATEDTOSPIKINGNEURONTB-ADC IMPLEMENTATION ........................... 26 5.1Introduction .............................. 26 5.2ImplementationofSpikingNeuronTB-ADC ............ 26 5.3PracticalIssuesRelatedtoSignalEncodinginSpikingNeuron Models ................................ 27 5.3.1FrequencyAliasingoftheInputSignal ........... 27 5.3.2LeakyIntegrationoftheIntegrator ............. 32 5.3.3ThermalNoiseoftheSpikingNeuron ............ 39 5.3.4SignalDependentReferenceVariationoftheComparator 46 5.4PracticalIssuesRelatedtoReconstructionfromSpikingNeuron Models ................................ 55 5.4.1TimingJitteroftheTimeQuantizer ............. 56 5.4.2KernelSelectionoftheDSPReconstructionAlgorithm ... 58 5.5Discussion ............................... 69 6IMPLEMENTATIONANDTESTOFANSPIKINGNEURONCHIP 71 6.1Introduction .............................. 71 6.2CircuitImplementationoftheTransconductor ........... 71 6.3CircuitImplementationoftheIFNeuron .............. 74 6.4Neuronchiplayout .......................... 78 6.5NeuronchipTestResults ....................... 79 6.5.14-parameterSineWaveFittingTest ............. 81 6.5.2SineWaveHistogramTest .................. 82 6.6Discussion ............................... 84 7IMPLEMENTATIONANDTESTOFANASYNCHRONOUSDELTA SIGMACONVERTER .......................... 86 vi

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7.1Introduction .............................. 86 7.2AsynchronousDeltaSigmaConverterArchitecture ......... 86 7.3SignalReconstructionAlgorithm ................... 87 7.4CircuitImplementation1 ....................... 90 7.4.1Integrator ........................... 90 7.4.2SchmittTriggerand1-bitDAC ................ 90 7.4.3ChipLayout .......................... 92 7.4.4ChipTestResults ....................... 93 7.5CircuitImplementation2 ....................... 96 7.5.1Integratorand1-bitDAC ................... 97 7.5.2SchmittTrigger ........................ 97 7.5.3ChipLayout .......................... 100 7.5.4ChipTestResults ....................... 100 8TIME-BASEDADCVARIATIONS ..................... 106 8.1Introduction .............................. 106 8.2ClockedNeuronModels ........................ 106 8.2.1GloballyClockedNeuron ................... 107 8.2.2LocallyClockedNeuron .................... 109 8.3Level-ModeTime-basedADCs .................... 110 8.3.1LevelCrossingSamplingTB-ADC .............. 112 8.3.2SawtoothWaveCrossingSamplingTB-ADC ........ 113 8.4Discussion ............................... 114 9CONCLUSIONS ............................... 115 REFERENCES ................................... 117 BIOGRAPHICALSKETCH ............................ 121 vii

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LISTOFTABLES Table page 2{1CharacteristicsoftheC-ADCandtheTB-ADC ............. 9 5{1PerformancecomparisonofthereconstructionusingtruncatedGaussiankernelandtruncatedSinckernel ................. 68 5{2PerformancecomparisonofthereconstructionusingtruncatedGaussiankernelandtruncatedSinckernelfor14kHzaverageringrate spiketrain ................................ 69 5{3Signaltonoiseratioduetodierentnoisesources ........... 70 6{1Thetransistorsizesforthetransconductanceamplier ......... 79 6{2ThetransistorsizesfortheIFneuron .................. 79 6{3Neuronchipperformancemetric ..................... 83 7{1Theasynchronousdeltasigmaconverterchip1performancemetric .. 96 7{2InputandoutputtransitiontableoftheSchmitttrigger( V in risesfrom below V rl toabove V rh ,andthendropsbelow V rl ) .......... 98 7{3Theasynchronousdeltasigmaconverterchip2performancemetric .. 105 viii

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LISTOFFIGURES Figure page 2{1Signalrepresentations.(a)Analogsignal.(b)Sampleandholdsignal.(c)Asynchronousdigitalsignal.(d)Digitalsignal ........ 6 2{2BlockdiagramoftheconventionalADC ................ 6 2{3Blockdiagramofthetime-basedADC ................. 8 3{1Structureofatypicalbiologicalneuron ................. 13 3{2StructureoftheIFneuron ........................ 14 3{3Shapesofthe V mem andthespikeoftheIFneuron ........... 15 3{4Shapesofthe V mem andthespikewaveformoftheLIFneuron .... 17 3{5Shapesofthe V mem S ( t )andthespikewaveformoftheIFneuron withthresholdadaptation ....................... 18 4{1SpectrumofthespiketrainfromtheIFneuron ............ 19 4{2ReconstructionresultsfromtheIFneuron.(a)Thespiketrain.(b) Theoriginalandreconstructedsignals.(c)Theerrorbetweenthe originalandthereconstructedsignals ................. 23 5{1BlockdiagramofthespikingneuronTB-ADC ............. 27 5{2PlotofSNRvs.aliasingfrequency .................... 31 5{3Schematicoftheleakyintegrator .................... 33 5{4SNRvs.outputresistance ........................ 37 5{5SNRvs.Sinewaveamplitude ...................... 38 5{6SNRvs.Sinewavefrequency ....................... 38 5{7Noisemodelofthespikingneuron .................... 39 5{8SNRvs.thermalnoisecurrentpowerspectraldensity ......... 46 5{9Signaldependentreferencevoltagevariationofthecomparator.High andlowslewrateareshownassolidordashedrespectively ..... 47 5{10PlotsofcoecientsC1andC2forsignaldependentthresholdvariation 52 ix

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5{11SNRvs.comparatortimeconstant ................... 54 5{12PlotofSNRvs.clockperiodusedinreconstruction .......... 59 5{13PlotofSinckernelvs.kernellength ................... 60 5{14PlotofSNRusingthetruncatedSinckernelvs.signallengthusedin thereconstruction ........................... 61 5{15PlotofGaussiankernelvs.kernellength ................ 62 5{16PlotofSNRusingthetruncatedGaussiankernelvs.signallength usedinthereconstruction ....................... 63 5{17PlotsoftherowvectorofthematrixCusingSincandGaussiankernels.(a)20throw.(b)80throw ................... 64 5{18WindowingschemeoftheDSPreconstructionalgorithm ....... 67 6{1Schematicofthetransconductanceamplier .............. 72 6{2Latcheswithapositivefeedback.(a)Capacitivefeedbacklatch.(b) Currentfeedbacklatch ......................... 75 6{3Schematicoftheneuroncircuit ..................... 76 6{4Layoutoftheneuronchip ........................ 78 6{5PlotoftheSNRvs.sinewaveamplitudeofthespikingneuronchip 81 6{6PlotoftheSNRvs.sinewavefrequencyofthespikingneuronchip 82 6{7PlotsoftheDNLandINLfromthesinewavehistogramtestofthe spikingneuronchip ........................... 83 7{1Architectureoftheasynchronousdeltasigmaconverter ........ 86 7{2CircuitimplementationoftheSchmitttrigger(M0-13)andthe1-bit DAC(M14-15) ............................. 91 7{3Layoutoftheasynchronousdeltasigmaconverterchip1 ....... 93 7{4PlotoftheSNRvs.sinewaveamplitudeoftheasynchronousdelta sigmaconverterchip1(thesinewavefrequencyis1kHz,theconvertersignalbandwidthis6kHz,and0dBFSrefersto0 : 2Vfull scaleamplitude) ............................ 94 7{5PlotoftheSNRvs.sinewavefrequencyoftheasynchronousdelta sigmaconverterchip1(thesinewaveamplitudeis-2.5dBFS) ... 95 x

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7{6PlotsoftheDNLandINLfromthesinewavehistogramtestofthe asynchronousdeltasigmaconverterchip1 .............. 96 7{7Integratorimplementationwith1-bitDAC ............... 98 7{8BlockdiagramoftheSchmitttrigger .................. 99 7{9Delayunitoftheschmidtttrigger .................... 100 7{10Layoutoftheasynchronousdeltasigmaconverterchip2 ....... 101 7{11PlotoftheSNRvs.sinewaveamplitudeoftheasynchronousdelta sigmaconverterchip2 ......................... 102 7{12PlotoftheSNRvs.sinewavefrequencyoftheasynchronousdelta sigmaconverterchip2 ......................... 103 7{13PlotoftheDNLandINLfromthesinewavehistogramtestofthe asynchronousdeltasigmaconverterchip2 .............. 104 8{1Referencevoltagewaveform,capacitorvoltagesandspikesforclocked neuronmodels. ............................. 107 8{2Reconstructionofthegloballyclockedneuron.(a)Spiketrainand Vrefwaveform.(b)Originalandreconstructedsignals ........ 108 8{3Reconstructionofthelocallyclockedneuron.(a)SpiketrainandVref waveform.(b)Originalandreconstructedsignals .......... 110 8{4ReconstructionofthelevelcrossingsamplingTB-ADC.(a)Spiketrain andVrefwaveform.(b)Originalandreconstructedsignals ..... 112 8{5ReconstructionofthesawtoothwavecrossingsamplingTB-ADC.(a) SpiketrainandVrefwaveform.(b)Originalandreconstructedsignals ................................... 113 xi

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AbstractofDissertationPresentedtotheGraduateSchool oftheUniversityofFloridainPartialFulllmentofthe RequirementsfortheDegreeofDoctorofPhilosophy TIME-BASEDANALOG-TO-DIGITALCONVERTERS By DazhiWei August2005 Chair:JohnG.Harris MajorDepartment:ElectricalandComputerEngineering Wepresenttheconceptandsomeimplementationsoftime-basedanalog-todigitalconverters(TB-ADCs).TheTB-ADCemploysafundamentallydierent architecturefromtheconventionalADCandachievesdataconversionbyrepresentingsignalsasaseriesofdiscretetimeevents.Thisnovelarchitecturetradeso simpleranalogcircuitryonthefrontendformorecomplexdigitalcircuitryonthe backend,andisverypromisingforlowpowerapplications. Weshowthattheoreticallywecanusetheweightedlow-passkernel(WLPK) methodtoperfectlyreconstructthesignalfortheTB-ADCs.Thismethodcanalso beextendedtosolvegeneralnonuniformsamplingproblems.Weinvestigatethe eectofdierentlow-passkernelssuchasSincandGaussianonthereconstruction performanceandcomputationcost.Wealsoextensivelyanalyzethefundamental performancelimitationofthespikingneuronTB-ADCduetononidealitiessuch asfrequencyaliasing,leakyintegration,thermalnoise,signal-dependentthreshold variation,andtimejitter.MuchofthisanalysiscanbeextendedtootherTBADCimplementations.WealsodiscusssomeotherTB-ADCvariationsincluding clockedneuronsandlevel-modeTB-ADCs.Testresultsofseveralprototypechips xii

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implementedin0 : 5umCMOStechnologyprocesssuggestthathighresolutionand lowpowerconsumptionTB-ADCsareachievableinpractice. xiii

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CHAPTER1 INTRODUCTION 1.1Background Thescalingtrendsofverylargescaleintegration(VLSI)CMOSprocesses havecontinuedtobringushigherspeedandlowerpowerdigitalcircuitryevery year.Theinternationaltechnologyroadmapforsemiconductors(2003edition) haspredictedthatthisscalingtrendwillcontinueuntilwellintothenextdecade. Forexample,thetransistorminimumgatelengthandthepowersupplyvoltage arepredictedtoreach7nmand0.5Vrespectivelyby2018[1].Sincethisscaling isoptimizedmostlyfortheperformanceimprovementofdigitalcircuitry,some analogdesignissuessuchasvoltageswing,intrinsicdevicegainandnoiseare severelycompromised,andhighperformanceanalogcircuitrywillbedicult todesign[2].Thereforethesignalprocessingtrendistocontinuetomovemore andmorefunctionalityfromanalogcircuitrytodigitalcircuitry.Thedesignof analog-to-digitalconverters(ADCs)alsofollowsthesametrend. Analog-to-digitalconvertersareemployedtoacquireanddigitizeanalogsignal sothatthesignalcanbeprocessedbydigitalprocessors.ConventionalADCsare realizedbasedonthedesignschemeofsample,holdandamplitudequantization. TheresolutionofconventionalADCsisdeterminedintheamplitude,orvoltage domain.BecausetheavailablevoltageswingcontinuestoshrinkduetotheVLSI processscaling,highresolutionADCdesignbasedonconventionaldesignschemes facesmoreandmorechallenges.Althoughsynchronousdeltasigmamodulation isasuccessfultechniquetoimprovetheADCperformance[3,4],itsoversampling naturedemandshighpowerconsumptionandlimitsitsapplication. 1

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2 NewADCimplementationsbasedontimequantizationhavebeeninvestigated toalleviatedrawbackssuchasthereducedvoltageswing,andtotakeadvantage ofthehighspeedcircuitrybroughtaboutbytheVLSIscaling[5{7].Onecommon featureintheseimplementationsisthatthesignalisrepresentedinthetime domainduringdataconversion.Theseimplementationsarecalledtime-based ADCssincetheirresolutionisdeterminedinthetimedomain,whichisamarked dierencefromconventionalADCs.Allier etal: havedesignedanewclassof asynchronousADCsbasedonlevel-crossingsamplingandtimequantization[5]. TheADCpowerconsumptionisobservedtobeoneorderofmagnitudeless thanconventionalADCsforsimilarperformance.Howeverareconstruction algorithmisnotdiscussedintheimplementationtoconvertthenonuniformly sampledsequencetotheuniformlysampledsequence.Rozapreviouslyproposed anADCimplementationusingasynchronousdelta-sigmamodulationandtime quantization[6].Theimplementationusesaninherentdirectlow-passltering methodtoreconstructthesignal.ToachievesomespecicADCperformance,a largeoversamplingratioisneededtosuppresshigherorderharmonicdistortions. LazarandTothhaverealizedaniterativealgorithmmethodbasedonnonuniform samplingtheorytotheoreticallyachieveperfectsignalreconstructionfromthe asynchronousdelta-sigmamodulation[7].Thismethodisnoteasytoapplyto othergeneraltime-basedADCimplementations,andtheeectsofnonidealitieson theADCperformancewerenotextensivelystudied. 1.2Motivation Therstmotivationofthisdissertationistoinvestigatepossibilitiesof time-basedADCimplementations.Thesignalreconstructionalgorithmisa keycomponenttodeterminetheperformanceoftheimplementations.Wewill developageneralalgorithmthatcanbeecientlyappliedtoalltime-basedADC architectures.

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3 Thesecondmotivationistocharacterizetheeectsofnonidealitiesonthe ADCperformance.EectsofnonidealitiesonconventionalADCperformancehave beenextensivelystudied.However,duetodierentsamplingandquantization scheme,thesenonidealitieshavedierenteectsontime-basedADCperformance andneedtobeinvestigatedtoguidepracticaldesigns. ThethirdmotivationistostriveforthehighresolutionandlowpowerTBADCcircuitimplementations.Novelarchitectureandcircuitdesigntechniques needtobestudiedtoachievebetterADCperformance. 1.3DissertationStructure Thisdissertationconsistsofninechaptersandisorganizedasfollows. InChapter1weintroducethebackgroundoftheADCimplementationsand presentsomemotivationsofthisdissertation. Chapter2reviewsthearchitectureoftheconventionalADCs,givesthe denitionandarchitectureofthetime-basedADC,andsummarizescomparison betweenthesetwotypesofADCs. InChapter3wewilltalkaboutthespikingneuronmodelswhichcanserveas theencoderinthetime-basedADCimplementations.Biologicalneuronmodelswill alsobebrieyreviewed. Chapter4introducesatheoreticallyperfectsignalreconstructionalgorithm whichcanbeappliedtogeneraltime-basedADCarchitectures.Theperformance ofthealgorithmisveriedthroughsignalreconstructionfromdierenttypesof spikingneuronmodels. InChapter5weinvestigateeectsofsomenonidealitiesontheperformance ofthetime-basedADC.Forthespikingneuronencodingcomponentweconsider thefrequencyaliasingoftheinputsignal,niteDCgainoftheintegrator,thermal noiseofthespikingneuron,andthesignaldependentthresholdofthecomparator.

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4 FortheDSPreconstructioncomponent,weconsiderthetimingjitterofthetime quantizer,thekernelselectionandthewindowingoftheDSPalgorithm. InChapter6wepresentthecircuitimplementationofthespikingneurontimebasedADC.Weconsidersomepracticalissuesandmakesometradeosduring theimplementation.Theperformanceoftheneuronchipismeasuredbasedonthe IEEEADCteststandard. Chapter7willpresentatime-basedADCimplementationbasedonthe asynchronousdelta-sigmamodulationwhichincludesthearchitecture,thedetailed circuitimplementation,thesignalreconstructionalgorithm,andthemeasuredchip performance. InChapter8wewilldiscussothertime-basedADCvariationsandgivesome simulationresultsoftheimplementations. Finally,theconclusionswillbegiveninChapter9.

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CHAPTER2 TIME-BASEDANALOG-TO-DIGITALCONVERTERS 2.1Introduction Inthischapterwerstreviewdierenttypesofsignalrepresentations.Based ondierenttransientsignalrepresentationsusedduringdataconversion,wegive denitionsoftheconventionalandthetime-basedADCs.Finallyweconcludethis chapterwithacomparisonbetweenthesetwotypesofADCs. 2.2SignalRepresentation ThesignalbeingprocessedbyADCsistypicallyaone-dimensionalsignal whichcanberepresentedbyavoltageorcurrentamplitudevaryingintime. Basedonwhethertheamplitudeandtimevariablesarecontinuousordiscrete, ADCsmaydealwith4typesofsignalsduringdataconversion,i.e.,analogsignals, sample-and-holdsignals,asynchronousdigitalsignalsanddigitalsignals,whichare showninFigure 2{1 (a),(b),(c)and(d),respectively.Theblackdotsinthegure representthesamplepointsofthesignal.ADCsareusedtoconverttheanalog signal,whichiscontinuousinbothamplitudeandtime,toadigitalsignal,whichis discreteinbothamplitudeandtime.Signalswithdiscreteamplitudecanbemore accuratelyrestoredthroughbueringinanoisyenvironment;thereforethedigital signalandtheasynchronousdigitalsignalaremorerobusttonoise.Thedigital signalandthesampleandholdsignalareusuallyuniformlysampledsequences, andcanbereconstructedbacktoananalogsignalthroughsimplelow-passltering basedonNyquistsamplingtheory.Therefore,thesampleandholdsignaliseasyto reconstructbutsensitivetothenoisewhiletheasynchronousdigitalsignalisrobust tonoisebutdiculttobereconstructedbecauseofthenonuniformsampling. Thesampleandholdsignalandtheasynchronousdigitalsignalaretwopossible 5

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6 Figure2{1: Signalrepresentations.(a)Analogsignal.(b)Sampleandholdsignal. (c)Asynchronousdigitalsignal.(d)Digitalsignal transientsignalrepresentationsthatcanbeusedduringdataconversion.The characteristicsofADCsaredeterminedbydierenttransientsignalrepresentations usedinimplementations. 2.3ConventionalAnalog-to-digitalConverters(C-ADCs) TheconventionalADC(C-ADC)realizesthedataconversionthroughthe schemeofclocksamplingandamplitudequantization.Figure 2{2 showsatypical architectureoftheconventionalADC[2].Thesamplingfrequency f s ,i.e.,theclock Figure2{2: BlockdiagramoftheconventionalADC

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7 frequency,mustbelargerthantwotimesthemaximumsignalfrequencytoavoid frequencyaliasingaccordingtoNyquistsamplingtheory.Thereforeanantialiasing lterisstrictlyrequiredtoremovefrequencycomponentshigherthan f s = 2fromthe inputanalogsignal.Thesamplingcircuitsamplesthelteroutputbyrecordingthe amplitudesatintegernumbersoftheclockperiod.Thissamplingmethodiscalled amplitudesampling.Theresultingsample-and-holdsignalperfectlyrepresents thelteroutputwithoutanyinformationlossbasedontheNyquistsampling theory.Laterthesignalamplitudeisapproximatedwithxedreferencelevelsby anamplitudequantizerandthenconvertedtoadigitalsignalbyanencoder.This approximationerror,whichisalsocalledquantizationnoise,determinesthatthe lteroutputcannotbeperfectlyreconstructedfromthedigitalsignal,resultingin theniteresolutionoftheADC.Inpracticebesidestheamplitudequantization noisetherearemanyothererrorsourcessuchasthermalnoiseandnonlinear distortionsduringthedataconversion.Thedierencebetweentheoriginallter outputandthereconstructedsignalfromthedigitalsignalisduetotheeectof alltheseerrorsources.Inthisdissertationwedonotdierentiatethedierence amongtheseerrorsourcesandusetheword\noise"torepresentallofthem.The resolutionoftheADCisrelatedtothesignaltonoiseratio(SNR)asdescribed below: SNR = P Signal P Noise =(6 : 02 N +1 : 76) dB (2.1) where N istheeectivenumberofbitsresolutionoftheADC.Thedenitionofthe SNRinthisdissertationisequivalenttodenitionssuchasthesignaltoerrorratio (SER),orthesignaltonoiseanddistortionratio(SINAD)inotherliteratures. ThereisanotherclassofconventionalADCcalledsynchronousdeltasigma ADCwhichisbasedonoversamplingandnoiseshapingtechniques.Itshares asimilarblockdiagramasshowninFigure 2{2 .Theanalogsignalissampled usingsuchahighsamplingfrequency f s thatonlyasmallpartoftheamplitude

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8 Figure2{3: Blockdiagramofthetime-basedADC quantizationnoisefallsintothesignalband,andthenthenoiseisshapedbya negativefeedbackinsuchawaythatmostofthenoiseispushedoutofthesignal bandwhilepreservingthein-bandsignal.Adecimationlter(theencoderin Figure 2{2 )isneededtolow-passanddownsamplethequantizeroutputtoobtain thedigitalsignalattheNyquistrate.Inthiswaytheconstraintsonthequantizer arerelaxedwhileachievinghighSNRatthecostofadditionalcomplexityonthe encoder. 2.4Time-basedAnalog-to-digitalConverters(TB-ADCs) FromaboveweseethatC-ADCsquantizeamplitudeatpredenedtimeintervals.Ontheotherhand,time-basedADCs(TB-ADCs)achievedataconversion throughaschemeofquantizingtimeatpredenedamplitudeintervals.TheTBADCblockdiagramisshowninFigure 2{3 .Anantialiasinglterworksinthe samewayasthatintheC-ADCtomakesurethelteroutputisabandlimited signal.Anencoderperformsthesamplingoperationandconvertsthelteroutput toaasynchronousdigitalsignal.Theencoderrecordsthetimestampswhenever theamplitudeofthelteroutput,ortheamplitudeofthetransformationofthe lteroutput,crossessomepredenedreferences.Thissamplingmethodiscalled timesampling.Examplesusingtimesamplingmethodarelevel-crossingsampling (amplitudeisthereferencelevelwhenthesamplinghappens),andpulseposition modulation(amplitudeisthesawtoothwavevalueatthesamplinginstant).The asynchronousdigitalsignalisthensynchronizedtoatimequantizer,i.e.,aclock,

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9 Table2{1: CharacteristicsoftheC-ADCandtheTB-ADC C-ADC TB-ADC Samplingmethod Amplitudesampling Timesampling Amplitude Quantized Exactlyknown Time Exactlyknown Quantized andthesampletimestampsareapproximatedtothenearestintegernumberof clockperiods T c .Thisapproximationerror,ortimequantizationnoise,determines theniteresolutionoftheADC.Sincethedigitalsignaltobeprocessedbycurrent DSPtechnologyisuniformlysampled,aDSPreconstructionalgorithmisrequired toconvertthenonuniformsampleswithtimequantizationtotheuniformlysampleddigitalsignal.ObviouslytheeciencyoftheDSPreconstructionalgorithm isexpectedtoaecttheresolutionoftheADC.SimilartoconventionalADCs althoughmaybeindierentways,othererrorsourcesduringdataconversionalso degradetheADCperformance.Againweusetheword\noise"torepresentthetotaleectduetothesenonidealities.Thesignal-to-noiseratioisdenedandrelated totheresolutionoftheADCinasimilarwayasinEquation 2.1 2.5ComparisonBetweentheC-ADCandtheTB-ADC Table 2{1 summarizesthedierentcharacteristicsoftheC-ADCandthe TB-ADCwehavediscussedinprevioussections.Thischaracteristicdierenceis mainlyduetothedierenttransientsignals(sampleandholdsignal,asynchronous digitalsignal)usedbytheC-ADCsandtheTB-ADCsduringdataconversion.For C-ADCsthesampletimeisexactlyknownandthesignalinformationisencodedin theunknownandquantizedamplitude.Onthecontrary,forTB-ADCsthesample amplitudeisexactlyknownandthesignalinformationisencodedintheunknown andquantizedtime.ThatisthereasonwhywemaycalltheTB-ADCadualcase oftheC-ADC[5].ClearlytheimplementationsoftheC-ADCsandTB-ADCshave dierentcharacteristics.

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10 TherstdierencebetweenC-ADCandTB-ADCisthepositionofthe quantizerintheADCimplementation.FromFigures 2{2 and 2{3 itisclearly seenthatquantizationofTB-ADCusesconventionaldigitalcircuitrywhileCADCisquantizedwithconventionalanalogcircuitry.Analogcircuitryfacesmore diculttradeosamongpower,noiseandresolutioncomparedtodigitalcircuitry. ThisdierencemeanstheTB-ADCcanbetterutilizethehighspeedandlow powerdigitalcircuitrytoobtainimprovedADCperformancewhilerelaxingthe requirementontheanalogcircuitry. TheseconddierenceisthatTB-ADCcanbesplitintoatransmitterside andareceiversidewhileC-ADCcanonlybeusedinthetransmitterside.The asynchronousdigitalsignalinTB-ADCisalreadydiscreteinamplitudeandrobust tonoiseandthussuitableforlongdistancetransmission,whilethesampleand holdsignalinC-ADCiscontinuousinamplitudeandnotsuitablefortransmission. ThismeansTB-ADCiscapableofsavingpoweronthetransmittersideandthusa bettercandidateforpowerlimitedapplications. ThethirddierenceisthatTB-ADCusesasignaldrivensamplingmethod whileC-ADCusesasignalindependentsamplingmethod.Thesamplingfrequency oftheC-ADCisaconstantandequalstotheclockfrequency.Evenwhenthe signalisnegligibletheC-ADCstilloutputsatthesamesamplingfrequency andconsumesunnecessarypower.SinceTB-ADCusesasignaldrivensampling method,theADCmaybeimplementedtooutputatalowsamplingfrequencyin regionsoflowinterest.Oneexampleofthesignaldrivensamplingmethodisthat strongersignalstriggermoresampleswhileweakersignalstriggerfewersamples. Thiscanfurtherreducepowerconsumptionwastedinsamplingnegligiblesignals. ThelastdierenceisthatthereconstructionpartoftheTB-ADCisanonuniformsamplingproblemwhilethatofC-ADCisauniformone.Goodreconstruction performancecanbeachievedbysimplelow-passlteringforC-ADC.Itwillbe

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11 seenthatfortheTB-ADCsimplelow-passlteringleadstopoorreconstruction performance,andamorecomplicatedreconstructionalgorithmshouldbecarefully implementedtoavoiddegradingtheperformanceoftheADC. Insummary,theTB-ADCtradesosimpleranalogcircuitryformorecomplex digitalcircuitry,whichisreasonablesincehighspeedandpowerfuldigitalcircuitry iseasilyrealized.Thistradeoisalsoagoodwaytodealwiththechallenges broughtaboutbyVLSIscaling.

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CHAPTER3 SPIKINGNEURONSIGNALREPRESENTATION 3.1Introduction Theneuronisafundamentalunitofbiologicalnervoussystems[8,9].Since thesesystemsarecharacterizedbyincrediblepatternrecognitionperformancewith ultralowpowerconsumption,itiswisetounderstandthesestrategiesinthedesign oflowpowerengineeringsystems.Thusthestudyinneuralencodingisexpected toprovidesomehintstobuildmoreecientman-madedevicessuchasADCs.In thischapterwerstintroducethestructureandtheencodingprocessingofthe biologicalneuron,andthenpresentseveralsimpliedspikingneuronmodelswhich canserveastheencodersinTB-ADCstructures. 3.2BiologicalNeuron MostinformationinthissectionisfromvanSchaik'sPhDdissertation[10]and Mead'sbook[11].Figure 3{1 showsthestructureofatypicalbiologicalneuron. Nearlyallneuronsusespikestocommunicatewithoneother.Thespike,oraction potential,isavoltagepulse.Allneuralspikesshareasimilarshapeandthusthe informationisbelievedtobeencodedinthespiketime.Theneuronreceivesspikes fromotherneurons'axonsbysynapsesonitsdendritesandcellbody,andthecell bodyprocessestheinformationandgeneratesitsownspikesattheaxonhillock whichthentravelalongitsaxontootherneurons. Spikegenerationisaveryimportantcomponentofneuralencoding.Hodgkin andHuxleydevelopedamodeltodescribethespikegenerationinthesquid axonin1952[12].Theinsideoftheneuronishighinpotassiumconcentration whiletheoutsideextracellularliquidishighinsodiumconcentration.Thecell membranecontainsmanypotassiumandsodiumchannels,andintheresting 12

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13 Figure3{1: Structureofatypicalbiologicalneuron statethepotentialoftheintercellularuidisaround 80mVwithrespecttothe groundpotentialoftheextracellularliquid.Thespikesfromotherneuronsrelease somechargeintotheneuronthroughthesynapsesandincreasesthemembrane potential.Experimentsshowifthemembranepotentialcanbeincreasedabove 40 m V,theneuroncangeneratespikes,otherwisethepotentialslowlydecays backtoitsrestingstate.Thisphenomenoniscausedbydependenceoftheopening andcloseofthepotassiumandsodiumchannelsonthethemembranepotential. Whenthepotentialisincreasingandabove 40mV,therapidopeningofthe sodiumchannelsbringspositivesodiumionsinsidetheneuronandfurtherincreases thepotential.Thepositivefeedbackloopquicklyraisesthepotentialto+40mV. Meanwhile,thesodiumchannelisinactivatedslowly,andmostimportantlya delayedopeningofpotassiumchannelscausesthepositivepotassiumchargeow outoftheneuron,whichresultsinthequickdecreaseofthepotentialbacktothe restingstate.Thetotaleectsofthesodiumandpotassiumchannelscausethe activepotential.Afteranactionpotentialthereisarefractoryperiodduringwhich nospikescanbegenerated.Thisisduetothefactthatthesodiumchannelsare inactivatedandthepotassiumchannelsareopenforsomeextratimeafterspiking.

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14 Figure3{2: StructureoftheIFneuron 3.3Integrate-and-reNeuronModels AlthoughtheHodgkin-Huxleymodelsuccessfullydescribesthespikegenerationofthebiologicalneuron,itistoocomplicatedforacompactcircuitimplementation.Spikingneuronmodelsbasedontheintegrate-and-remechanismalso capturetheessentialsofthespikegeneration,andareeasilyimplementedinsilicon. 3.3.1Integrate-and-reNeuronModel Thestructureoftheintegrate-and-re(IF)neuronmodelisshowninFigure 3{2 .Theeectofthechargereleasedbyotherneurons'spikesismodelledbya currentsource x ( t ).Themembraneismodelledbyapassivecapacitor C .The currentisintegratedoverthecapacitor C andincreasesthecapacitorvoltage V mem .Once V mem isabovethethresholdvoltage V ref ofthecomparator,aspike isgeneratedand V mem isthenresettogroundandanotherintegrationperiod begins.Theshapesof V mem andthespikeareshowninFigure 3{3 where t ib and t ie arethetimingsforthefallingandrisingedgesofthespike.Obviouslythe signalinformationisencodedintheintegrationperiod.Equations 3.1 3.2 and 3.3

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15 Figure3{3: Shapesofthe V mem andthespikeoftheIFneuron describethisencodingprocess. C dV mem dt = x ( t )(3.1) V mem ( t ib )=0(3.2) V mem ( t ie )= V ref (3.3) Wecanalsouseoneequationtodescribethisencodingprocess. Z t ie t ib x ( t ) dt = CV ref = ; 8 i (3.4) Ifweassumethespikewidthisinnitelysmall,weobtainspiketimings t i = t ib and t i +1 = t ( i +1) b = t ie ,andEquation 3.4 simpliesto Z t i +1 t i x ( t ) dt = ; 8 i (3.5)

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16 Ifwealsodenetheintegralofthesignalas f ( t )= R t t 0 x ( s ) ds where t 0 isthe beginningoftherstintegrationperiod,Equation 3.5 isequivalentto f ( t i )= i; 8 i (3.6) Thisshowsusanotherviewoftheencodingprocesswhichrecordsthetime whenevertheintegralofthesignalcrossesthelevelofintegernumberof .This interpretationplacestheintegrate-and-reneuronintheclassofTB-ADCsdened inChapter 2 3.3.2LeakyIntegrate-and-reNeuronwithRefractoryPeriodModel AsmentionedinSection 3.2 thespikegenerationofbiologicalneuronsshows somefeaturesofleakyintegrationandtherefractoryperiod.WhentheIFneuron inSection 3.3.1 isimplementedincircuitry,theniteoutputimpedanceofthe currentsourceandotherparasiticresistancesinparallelwiththecapacitorleadto aleakyintegration,andmeanwhiletheniteslopeofthespikefallingedgecauses somerefractoryperiod.Tomodeltheleakyconductancearesistor R isintroduced inparallelwiththecapacitor C .ThespikegenerationissimilartotheIFneuron case,andtheshapesof V mem andthespikeareshowninFigure 3{4 where T r representstherefractoryperiod.Similarlythisencodingprocesscanbedescribed byEquations 3.7 3.8 and 3.9 C dV mem dt + V mem R = x ( t )(3.7) V mem ( t ib + T r )=0(3.8) V mem ( t ie )= V ref (3.9) Wecanalsouseoneequationtodescribethisencodingprocess. Z t ie t ib + T r x ( t ) e t ie t RC dt = CV ref = ; 8 i (3.10)

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17 Figure3{4: Shapesofthe V mem andthespikewaveformoftheLIFneuron WecannoticethatEquation 3.10 isconsistentwithEquation 3.4 whentheleaky resistance R takesonaninnitevalue. 3.3.3Integrate-and-reNeuronwithThresholdAdaptation Biologicalneuronsalsoexhibitsomeadaptivepropertieswhengenerating spiketrains[9,13,14].Whenastrongstimulusisappliedtotheneuron,theneuron ringratewillinitiallybehighandthenadapttoalowervalue.Theadaptive mechanismmayservetosavepowerandimprovedynamicrange.Theseadaptive propertiescanbeutilizedinlowpowerADCapplications.Thresholdadaptationis onewaytointroduceadaptivepropertiesintotheneuronmodel[14].Thethreshold decaysexponentiallyandisincrementedafteranactionpotentialbyanamount determinedbypreviousringpatterns.TheEquationsbelowdescribetheencoding processing. C dV mem dt = x ( t ) ifV mem ( t )
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18 Figure3{5: Shapesofthe V mem S ( t )andthespikewaveformoftheIFneuronwith thresholdadaptation S ( t + ib )= S 0 + S ( t ib ) ifV mem ( t ib )= S ( t ib )(3.14) where s isthetimeconstantofthethreshold, S r isthesteadystatevalueof thethresholdintheabsenceofringand isapositivenumberlessthan1. Figure 3{5 showsthewaveformsofthecapacitorvoltage V mem ,thethreshold S ( t ), andthespiketrainfortheneuronwiththresholdadaptation.Wecanseethatif S r = S 0 = V ref and =0,theadaptiveneuronreducestheidealIFneuronwith constantthreshold. 3.4Summary Inthischapterweintroducedatypicalbiologicalneuronandsomeintegrateand-reneuronmodels.Theseneuronmodelsrepresentinformationinspike timingsandthereforecanserveastheencoderintheTB-ADCarchitecture.Inthe followingchapterwewillshowtheDSPalgorithmwhichcanbeusedtoreconstruct signalsfromthesespiketimings.

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CHAPTER4 RECONSTRUCTIONFROMSPIKINGNEURONMODELS 4.1Introduction AsmentionedinChapter 2 theperformanceoftheTB-ADCalsodepends onthereconstructionalgorithm.Poorreconstructionmethodscandegradethe ADCperformancedramaticallyevenwhenthesignalisaccuratelyencodedbythe encoder.Thischapterdescribesthemethodtoperfectlyreconstructthesignalfrom thespikingneuron. 4.2DirectLow-passFilteringReconstructionMethod Theeorttoreconstructsignalsfromtheneuronspiketraincanberecalled backtoasearlyas1968,whenBaylygaveaspectralanalysisofthespiketrain fromIFneuronwithsinglesinusoidalinput[15].Hisresultsshowthatinsome casesthesignalcanbereconstructedwithsometolerabledistortionfromthespike trainusingdirectlow-passltering.Weassumethethresholdvoltageis V ref = C andthespiketrainismodelledasanunit-areaimpulsetrainwith t i asthering times,Equations 3.1 3.2 and 3.3 thencanbesimpliedas = Z t i +1 t i x ( t ) dt (4.1) Figure4{1: SpectrumofthespiketrainfromtheIFneuron 19

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20 ConsideringthesimplecasewheretheinputtotheIFneuronisasinusoidalsignal x ( t )= m 0 + m 1 cos(2 f m t ),andoneofthespikeshappensat t =0,thespectral descriptionofthespiketrainfromBayly'sanalysisisgivenas: p ( t )= f 0 + m 1 cos(2 f m t ) +2 f 0 1 X k =1 1 X n = J n ( km 1 f m )(1+ nf m kf 0 )cos(2 ( kf 0 + nf m ) t ) (4.2) where f 0 = m 0 = isthefundamentalfrequencywhichisequivalenttotheaverage spikeringrate,and J n isaBesselfunctionoftherstkindoforder n .Therst twotermsinEquation 4.2 aredirectlyfromtheinputsignal x ( t )scaledby ,the otherterms kf 0 + nf m arethefrequencycomponentscrossmodulatedbetween f 0 and f m .ThespectrumcanbeseenmoreclearlyinFigure 4{1 .Forthespectrum ofthespiketraingeneratedfrommulti-toneinputsignal,theresultissimilarto Equation 4.2 exceptmorecomplicatedcrossmodulatedfrequencycomponents[16]. Thedirectlow-passlteringreconstructionmethodistopassthespiketrain throughalow-passlterwithcutofrequencyequaltothemaximumsignal frequencytoremovecrossmodulatedcomponents.Itcanbeclearlyseenfrom Equation 4.2 orFigure 4{1 thatnomatterhowlargetheaverageringrate f 0 is,therearealwayssomecrossmodulatedcomponents kf 0 + nf m fallingintothe signalband[ f m ;f m ]whichcannotbelteredoutevenusingideallow-passlter. Thismeansperfectsignalreconstructioncannotbeachievedusingthismethod.In practicalsignalreconstruction,thecrossmodulatedcomponentsinthesignalband usuallyhavenon-negligiblemagnitude,andthusthereconstructionperformanceof directlow-passlteringisnotacceptableformostapplications. 4.3WLPKReconstructionMethod ThesignalreconstructionfromTB-ADCisanon-uniformsamplingproblem. Developmentsinthenon-uniformsamplingtheoryhaveshownthatperfectsignal reconstructioncanbeachievedinsomecases[17,18].Wehavedevelopedthe

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21 weightedlow-passkernelmethod(WLPK)torealizeperfectsignalreconstruction [19].Themethodisdescribedbelow: Fromnon-uniformsamplingtheorywecanderivetheclaim:anybandlimited signalcanbeexpressedasalow-passlteredversionofanappropriatelyweighted sumofdelayedimpulsefunctions[17],[18].Assumingthat x ( t )isbandlimitedto [ s ; s ],and s j 'sarethetimingsoftheimpulsetrainandthemaximumadjacent sampletimingdistanceislessthantheNyquistperiod T = = s ,thenwehave x ( t )= h ( t ) X j w j ( t s j ) = X j w j h ( t s j ) (4.3) where w j arescalarweights, h ( t )istheimpulseresponseofthelow-passlterand denotestheconvolutionoperator.Theimpulseresponseoftheideallow-passlter isgivenbytheSincfunction: h ( t )=sin( s t ) = ( s t )(4.4) Nowthesignalreconstructionproblemissimpliedashowtocalculatethe appropriateweights.If s j = jT isauniformsamplingsequence,standardsampling theorycanbeusedtoshowthattheimpulseweightreducestothesampledvalueof signal x ( t )atthetiming s j ,i.e., w j = x ( s j ).Butgenerallytheweightsneedtobe calculatedusingtheencodinginformation. 4.3.1ReconstructionfromtheIFneuron Werstconsiderthereconstructionfromtheintegrate-and-reneuronwithout anyrefractoryperiod.Theringtimesmustsatisfy: Z t ie t ib x ( t ) dt = i ; 8 i (4.5) where i = forconstantthreshold,and t ib and t ie arethefallingedgeandthe risingedgeofthespike.Letusassumethat x ( t )isbandlimitedto[ s ; s ],and

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22 t ib ;i 2 Z and t ie ;i 2 Z aretimingsequenceswithmaximumadjacentinterval ( t ( i +1) b t ib )
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23 Figure4{2: ReconstructionresultsfromtheIFneuron.(a)Thespiketrain.(b) Theoriginalandreconstructedsignals.(c)Theerrorbetweentheoriginalandthe reconstructedsignals x ( t ): x ( t )=[ h ( t s j )][ c + ji ][ i ] =[ X j h ( t s j ) c + ji ][ i ] =[ h i ( t )][ i ] = X i h i ( t ) i (4.9) where c + ji isthe jth row ith columnelementoftheinversematrix C + ,[ ]denotesa matrixwithelement ,and h i ( t )= X j h ( t s j ) c + ji (4.10) Figure 4{2 showsareconstructedsignalusingtheWLPKmethodforanintegrateand-reneuron.TheinputsignalisaGaussianrandomnoisesignalbandlimitedto [ 3000 ; 3000 ]rad/s,andthecorrespondingNyquistperiod T =1 = 3ms.TheDC currentis800nA,thecapacitance C =18pF,thereferencevoltage V ref =3V,the

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24 spikewidthis6 : 6us.Sincethemaximumadjacentspikeinterval(0 : 15ms)isless than T ,thismethodcanbeusedtoreconstructtheinputsignal.Thesimulation resultsshowtheeectivesignaltonoiseratio(SNR)ofthereconstructionis107 : 6 dB.SNRiscomputedasthepoweroftheinputsignaldividedbythepowerofthe errorbetweentheoriginalandthereconstructedsignals. 4.3.2ReconstructionfromLIFneuronwithrefractoryperiod Equations 3.7 3.8 and 3.9 describetheencodingoperationoftheleaky integrate-and-reneuronwiththecurrentinput.Theyareusedtogeneratea linearsystemofequationinasimilarfashiontotheidealintegrate-and-reneuron discussedinSection 4.3.1 ,exceptthecoecientmatrixCelement c ij = Z t ie t ib + T r h ( t s j ) e ( t t ie ) = ( RC ) dt (4.11) whichistheleakyintegrationof h ( t s j )overthetimeperiod[ t ib + T r ;t ie ]. Equation 4.11 isconsistentwithEquation 4.7 whentheleakyresistance R takeson aninnitevalue.WecanuseEquation 4.8 tocalculatetheweightsforeachimpulse at s j ,thenuseEquation 4.3 toreconstructthesignal x ( t ). 4.3.3ReconstructionfromtheIFneuronwiththresholdadaptation ToreconstructthesignalfromtheIFneuronwiththresholdadaptationwe havetoknowtheintegrationoftheinputsignaloverthe i thintegrationperiod,i.e., thethresholdatthetime t ie .Assumingthethresholddoesnotchangefrom t ( i 1) e to t ib ,fromEquations 3.12 3.14 wecanobtainthethresholdvalueat t ie : i = S ( t ie )=( S 0 + S ( t ( i 1) e ) S r ) e t ib t ie s + S r = S ( t ( i 1) e ) e t ib t ie s + S r +( S 0 S r ) e t ib t ie s (4.12) whichcanbedeterminedifweknowthepreviousthresholdvalueat t ( i 1) e Thereforeiftheinitialthresholdvalueisgiven,wecancalculatetheexactfollowing thresholdvaluesusingEquation 4.12 ,andthenuseEquations 4.7 4.8 ,and 4.3 to

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25 reconstructthesignal.Iftheinitialthresholdvalueisnotgiven,someestimation errorwillbeintroducedintothereconstruction.However,itisbelievedthatthe estimationerrordecayswithtime.Thisisduetothefactthatthecoecient e t ib t ie s inEquation 4.12 isanumberlessthan1. 4.4DiscussionofOtherReconstructionMethods PrevioussimulationresultsshowthattheWLPKmethodachievesmuchbetter performancethanthedirectlowpasslteringmethod.Besidesthesetwomethods, therearealsoothermethodswhichcanbeusedforthesignalreconstructionfrom thespikingneuron. Noguchi etal: foundonemethodbasedontheintegralmechanismofthe neuronencodingandclaimedthereconstructionperformanceisbetterthansimple lowpassltering[23,24].TheirmethodusesB-splineinterpolationtoapproximate theintegrationfunctionoftheoriginalsignal x ( t )andthendierentiateitto obtaintheoriginalinput x ( t ).Thereconstructedsignalisnotperfectsincethe approximationerrorcannotbeavoided.Lazar etal: realizedaniterativealgorithm methodbasedonnonuniformsamplingtheorytotheoreticallyachieveperfect signalreconstructionfromtheasynchronousdelta-sigmamodulation[7].Since theIFneuronhasasimilarintegralmechanismoftheasynchronoussigma-delta converters,thismethodisalsoapplicabletotheIFneuron.Theproblemwith Noguchi'sandLazar'smethodsisthattheyarenoteasytobeappliedtomore complicatedmodelsuchastheleakyIFwithrefractoryperiodorthreshold adaptation,seeGerstner[13]formoreneuronmodels.Thisseriouslylimitstheir applicationsincepracticalIFneuroncircuitalwayshassomeleakyandrefractory periodfeatureswhichneedtobeconsideredinthereconstructionforbetter performance.TheWLPKmethodwediscussedisbetterinthatitcanbeapplied togeneraltime-basedADCarchitecture.

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CHAPTER5 PRACTICALISSUESRELATEDTOSPIKINGNEURONTB-ADC IMPLEMENTATION 5.1Introduction Inthischapter,werstintroduceaspikingneuronTB-ADCimplementation usingthespikingneuronmodeldiscussedinChapter 3 ,andtheDSPreconstruction algorithmblockdiscussedinChapter 4 .Sincetheactualbuildingcomponentsused arenotperfect,wetheninvestigateeectsofsomenonidealitiesontheperformance oftheanalogtodigitalconversion.Forthespikingneuronencodingcomponent weconsiderthefrequencyaliasingoftheinputsignal,leakyintegrationofthe integrator,thermalnoiseofthespikingneuron,andthesignaldependentthreshold ofthecomparator.FortheDSPreconstructioncomponent,weconsiderthetiming jitterofthetimequantizer,thekernelselection,andthewindowingoftheDSP algorithm. 5.2ImplementationofSpikingNeuronTB-ADC Figure 5{1 showsanimplementationofthespikingneuronTB-ADC.The detailedcircuitimplementationwillbediscussedinChapter 6 .Thecomponents insidethedashedboxformanintegrate-and-reneuronencoderwhichwas previouslydiscussedinChapter 3 .ComparedtothepreviousstructureinFigure 3{ 2 ,atransconductor G m blockisusedtoconvertavoltagesignal V ( t )toacurrent signal x ( t )= G m V ( t )sincetheinputsignalformanyanalogtodigitalapplications isinvoltageform.Iftheinputisacurrentsignal,the G m blockisobviouslynot neededandtheADCdesignissimplied.Theneuronencodestheanalogsignal waveforminthetransitiontimingsofthespikingsignal.Thetimequantizer quantizesthetransitiontimingsofthespikingsignalwithaclockperiod T c .The 26

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27 Figure5{1: BlockdiagramofthespikingneuronTB-ADC DSPreconstructionthenusestheWLPKmethoddiscussedinChapter 4 toconvert thenonuniformspikingsignaltoauniformlysampleddigitalsignal. 5.3PracticalIssuesRelatedtoSignalEncodinginSpikingNeuron Models TheencoderisthefundamentalpartoftheTB-ADCthatdeterminesits performance.Specialattentionshouldbepaidtotheimplementationsincethe encoderusesanalogcircuitry,whichissensitivetomanynonidealitiessuchas nonlinearity,niteamplierDCgain,niteamplierspeed,andnoise. 5.3.1FrequencyAliasingoftheInputSignal Forsimplicity,weneglectthetransconductanceamplier G m blockand considertheinputsignaltotheneuronasthecurrent x ( t ).Sinceitisassumedthat theinputsignalisbandlimited,ananti-aliasingpre-lterisstrictlyrequiredtobe placedbeforetheneurontolterouthigherfrequencies.Sincetheanti-aliasing pre-lterisnotperfectinpractice,somehigherfrequencycomponentswillstill existintheinputtotheneuron.Weshouldinvestigatetheeectofthesehigher frequencycomponentsontheADCperformance.Itiswellknownthatforstandard Nyquistratesampling,higherfrequenciesaresimplymappedtolowerfrequencies, preservingtheamountofpower[25].Aswillbeseen,thenatureofaliasingfor neuronencodingissignicantlydierent.Ourintuitionsaysthattheintegration

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28 causeshigherfrequenciestobeattenuatedmorethanlowerfrequencies.Nowletus mathematicallyexplainthisfrequencyaliasingeect. Assumethedesiredinputsignal V ( t )iscorruptedbyahighfrequencysine wave V a ( t )= A a cos(2 f a t )with f a muchhigherthanthesignalband s = (2 ).The actualinputsignaltotheintegrate-and-reneuronis V ( t )+ V a ( t )andwehavethe followingencodingequation: Z t ie t ib V ( t )+ V a ( t ) dt = CV ref = (5.1) where t ib and t ie arethebeginningandtheendof ith integrationperiod.Since thefrequency f a islargerthanthesignalbandwidth s = (2 )andthebandwidth requirementisnotsatised,wecannotexpress V ( t )+ V a ( t )inasimilarformto Equation 4.3 .Thereforewecannotperfectlyreconstruct V ( t )+ V a ( t ).However, whatwereallywanttoreconstructhereisthesignal V ( t ).Itcanstillbeexpressed usingEquation 4.3 ,ifthehighfrequencycomponent V a ( t )doesnotaectthespike timingsomuchthatthemaximuminterspikeintervalisstilllessthantheNyquist period.Theoreticallywecanstillperfectlyreconstruct V ( t )ifwecouldndthe actualintegration i = G m R t ie t ib V ( t ) dt .WerewriteEquation 4.9 asfollows: V ( t )= 1 G m X i h i ( t ) i (5.2) Sincewedonotknowtheexactfunctionof V a ( t )andcannotndtheexactvalueof i ,inpracticeweuse astheintegrationof V ( t )toobtainthereconstructedsignal ^ V ( t ): ^ V ( t )= 1 G m X i h i ( t ) (5.3) Thedierencebetweentheinputsignal V ( t )andthereconstructedsignal ^ V ( t ) representsthenoiseduetothefrequencyaliasingwhichobviouslydegradesthe

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29 reconstructionperformance.Wecancalculate( i ): i = G m Z t ie t ib V ( t )+ V a ( t ) dt G m Z t ie t ib V ( t ) dt = G m Z t ie t ib V a ( t ) dt = G m Z n i 0 A a cos(2 f a t ) dt = G m A a sin(2 f a n i ) = (2 f a ) (5.4) where n i isassumedtobeanindependentidenticalrandomvariableuniformly distributedin[ 1 = 2 f a ; 1 = 2 f a ].FromEquations 5.2 5.3 5.4 ,wecancalculatethe noisepowerduetothefrequencyaliasing: P noise;aliasing = E [( V ( t ) ^ V ( t )) 2 ] = 1 G 2 m E [( X i h i ( t )( i )) 2 ] = A 2 a (2 f a ) 2 E [( X i h i ( t )sin(2 f a n i )) 2 ] = A 2 a (2 f a ) 2 X i E [ h 2 i ( t )] E [(sin(2 f a n i )) 2 ] = A 2 a 2(2 f a ) 2 E [ X i h 2 i ( t )] (5.5) Thesignalpoweris: P signal = E [( V ( t )) 2 ] E [(^ x ( V )) 2 ] = 2 G 2 m E [( X i h i ( t )) 2 ] (5.6) wheretheapproximationismadewiththeassumptionthattheerrorbetween thereconstructedsignalandtheinputsignalisrelativelyverysmall.Finallythe correspondingsignaltonoiseratio(SNR)is: SNR aliasing = P signal P noise;aliasing

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30 = 8 2 f 2 a 2 E [( P i h i ( t )) 2 ] G 2 m A 2 a E [ P i h 2 i ( t )] 8 2 2 f 2 a G 2 m A 2 a (5.7) wheretheapproximationismadewiththeassumptionoflowoversampling ratio( 2 f avg s ). h i ( t )isaweighteddelayedlow-passkernel.Duetothekernel's time-decayingproperty,themeanoftheproductoftwokernelsfarapart,i.e., E [ h i ( t ) h j ( t )],ismuchsmallerthanthepowerofthekernel,i.e., E [ h 2 i ( t )].Sincethe oversamplingratioisnothighandmostkernelsarefarapart,theapproximation E [( P i h i ( t )) 2 ]= E [ P i h 2 i ( t )]+2 E [ P i 6= j h i ( t ) h j ( t )] E [ P i h 2 i ( t )]isvalid. Equation 5.7 showsthatincreasing ishelpfultosuppressthefrequencyaliasing eect.Thisreducestherelativevariationoftheintegration i whichisduetohigh frequencycomponents. Inpractice,theaverageringrate f avg = G m V dc CV ref isrelatedtothesignal bandwidthoftheADC,andisusuallyapredenednumber.Equation 5.7 canbe furthersimpliedas: SNR aliasing 8 2 2 f 2 a G 2 m A 2 a = 8 2 V 2 dc f 2 a A 2 a f 2 avg (5.8) where V dc istheDCcomponentoftheinputsignal.Increasing V dc isequivalent toincreasing CV ref withconstant f avg ,andishelpfultoreducetheperformance degradationduetothefrequencyaliasing. Equation 5.8 showsthattheSNRisproportionaltothefrequencyofthe aliasingsinusoidwithaslopeof20dB/decade,andinverselyproportionaltothe amplitudeofthealiasingsinusoidwithaslopeof20dB/decade.Thereforeour initialintuitionisveriedandthisanti-aliasingeectoftheneuronhastheeect ofarst-orderlow-passlter.Thecutofrequencyofthis\lowpasslter"is approximatelythesignalbandwidth.

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31 Figure5{2: PlotofSNRvs.aliasingfrequency SimulationshavebeenruninMatlabtovalidatethepreviousderivations. Figure 5{2 showsaplotofSNRvs.thefrequencyofanaddedhigh-frequency sinewave.Thesignalusedinthissimulationisthesameastheoneusedin Figure 4{2 .TheADCbandwidthisdenedas1 : 5kHz.Thesolidredlineand thedashedbluelinerepresenttheresultsfromthenumericalevaluationandthe Equation 5.8 ,respectively.Wecanclearlyseethatthedetrimentaleectofthe aliasingofthehighfrequencycomponentisreducedasthefrequencyoftheadded sinewaveincreases.Whenthefrequencyofthesinewaveishighenough,theSNR approaches107dB,avaluedeterminedbythenitenumberofspikesusedand thenitemachineprecision.Althoughthereisabout10dBdierencebetweenthe SNRsfromthenumericalevaluationandtheapproximateequation,theslopeofthe curvefromthesimulationis20dB/decadeaspredictedbyEquation 5.8 Nowletusdiscussthenonlinearityofthetransconductanceamplier G m block.Anideallinear G m blockonlyconvertsthevoltagesignal V ( t )intothe

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32 current x ( t ).Inpracticethe G m blockshowssomenonlinearcharacteristicsand distortsthecurrent x ( t )withsomehigher-orderharmonicswhichdonotexist inthevoltage V ( t ).Forexample,thespectrumof x ( t )mayhave2 f 1 ; 3 f 1 ; 4 f 1 ;::: frequencycomponentsalthoughonlyonefrequency f 1 existsinthespectrumof V ( t ).ThisnonlinearcharacteristicobviouslydegradestheADCperformanceand needstobeconsideredseriouslyinthecircuitimplementation.Ontheotherhand, theanti-aliasingeectoftheneuronmayattenuatesomeofthosehigher-order harmonicsthatarehigherthanthesignalband s = (2 ).Thismeansthatthe neuroncantoleratethenonlinearityofthe G m blocktosomedegree.Weshould alsobeawarethatinordertofairlycharacterizetheADCperformance,thetest frequencyappliedshouldbemuchlessthanthesignalband s = (2 )sothatthe eectofthenonlinearitiesofthe G m blockisconsideredinthemeasurement. 5.3.2LeakyIntegrationoftheIntegrator AsmentionedinSection 5.2 atransconductanceamplier G m blockisusedto convertthevoltageinputsignal V ( t )tothecurrentsignal x ( t )whichthencharges thecapacitortoimplementtheintegrationoperation.AsshowninFigure 5{3 ,the transconductanceamplierhasniteoutputresistance R whichresultsinaleaky integration.Wemustconsideritseectonthereconstruction.Theintegration operationisdescribedby C dV c dt = G m V ( t ) V c R = G m ( V ( t ) V c A DC ) (5.9) where A DC = G m R istheDCvoltagegainofthetransconductanceamplier.If weknowtheexactvalueof G m and R wecanusetheWLPKmethoddiscussed inSection 4.3.2 toperfectlyreconstructtheinputsignal V ( t )fromthisleaky integrate-and-reneuron.However,inpracticetheoutputresistance R isusuallya signal-andprocess-dependentterm r o =1 = ( I bias )andexhibitssomenonlinearity andunpredictability.Furthermore,sincethereconstructionperformanceissensitive

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33 Figure5{3: Schematicoftheleakyintegrator totheaccuracyoftheestimationoftheoutputresistance R ,itisdicultin practicetohavesatisfactoryreconstructionperformancebyapplyingtheWLPK methodtothisleakyneuron.Thereforewemayprefertotreatthisneuronas anidealintegrate-and-reneuronduringreconstructionandinvestigatethe performancelimitationduetotheleakyintegration. Ifwecancalculatetheexactvalueoftheleakedchargeovereachintegrationperiod,wecanobtaintheactualintegrationvalueoftheinputsignaland mathematicallyperfectreconstructionofthesignal.Itishelpfultoestimatethe reconstructionperformancebyinvestigatingtherelationshipbetweentheleaked chargevariationandtheinputsignal.Letusbeginfromthesimplecasethatthe inputsignal V ( t )hasonlyDCcomponent V dc .Assumingthatthe i thintegration period T i = t ie t ib ismuchlessthanthetimeconstant RC ,thevariationofthe voltage V c acrossthecapacitorcanbeapproximatedaslinearlyincreasingfrom0 to V ref ,andthustheleakedcharge i = V ref 2 R T i .Theeectoftheleakedcharge isequivalenttoaddingtotheinputsignalwithaconstantDCcomponentwhich equalsto i G m T i = V ref 2 G m R = V ref 2 A DC .ThisDCcomponentcanbeeasilyremovedthrough calibrationanddoesnotdegradethereconstructionperformance.Ourintuition saysthatitisthevariationof V ( t ),ortheACcomponentof V ( t ),thatdegrades thereconstructionperformance.

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34 Assumingthat V i and V i arethevaluesof V ( t )andthevalueoftherst-order derivative V ( t )= dV ( t ) dt at t = t ib respectively,and V ( t )doesnotvarymuchfrom t ib to t ie ,wecanapproximatetheinputsignalas V i + V i ( t t ib )forthe i thintegration period.Therefore,fromtheencodingequationoftheleakyneuronwecanobtain: = G m Z t ie t ib V ( t ) e t t ie RC dt G m Z t ie t ib ( V i + V i ( t t ib )) e t t ie RC dt = G m Z T i 0 ( V i + V i t ) e t T i RC dt = G m V i RC (1 e T i RC )+ G m V i RC ( T i RC (1 e T i RC )) G m V i ( T i T 2 i 2 RC )+ G m V i ( T 2 i 2 T 3 i 6 R 2 C 2 ) (5.10) wheretheTaylorseriesapproximationof e x isusedinthederivation.Sincewe treattheneuronasanidealintegrate-and-reneuron,theactualintegrationof V ( t )overthe i thintegrationperiodis: i = G m Z t ie t ib V ( t ) dt G m Z t ie t ib ( V i + V i ( t t ib )) dt = G m Z T i 0 ( V i + V i t ) dt = G m V i T i + G m V i T 2 i 2 (5.11) Thereforetheleakedchargeforthe i thintegrationperiodis: i = G m V i T 2 i 2 RC + G m V i T 3 i 6 RC G m ( V ref 2 A DC ) T i + G m V i T 3 i 6 RC (5.12) wheretheapproximationismadedueto CV ref G m V i T i .Again,therstitemin Equation 5.12 isequivalenttoaddingaDCcomponenttotheinputsignalwhich canberemovedthroughcalibration.TheseconditeminEquation 5.12 isdueto

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35 thevariationoftheinputsignalandistheonlysourcetoaectthereconstruction performance.Therefore,thenoisepowerduetotheleakyintegrationis: P noise;leaky = E [( V ( t ) ^ V ( t )) 2 ] = 1 G 2 m E [( x ( t ) ^ x ( t )) 2 ] = 1 G 2 m E [( X i h i ( t )( i G m ( V ref 2 A DC ) T i )) 2 ] = 1 G 2 m E [( X i h i ( t )( G m V i T 3 i 6 RC )) 2 ] = 1 G 2 m E [( X i h i ( t )( G m V i C 3 V 3 ref 6 RCG 3 m V 3 i )) 2 ] = ( CV ref ) 6 (6 RCG 3 m ) 2 X i E [ h 2 i ( t )] E [ V 2 i V 6 i ] ( CV ref ) 6 (6 RCG 3 m V 3 dc ) 2 E [ V 2 ( t )] E [ X i h 2 i ( t )] (5.13) where E [ V 2 ( t )]isthepoweroftherst-orderderivativeof V ( t ),andtheapproximationof E [ V 6 i ] V 6 dc ismadewiththeassumptionthattheDCcomponentis dominantintheinputsignal.Thesignalpoweris: P signal = E [( V ( t )) 2 ] = 1 G 2 m E [( X i h i ( t ) i ) 2 ] 1 G 2 m E [( X i h i ( t )) 2 ]( CV ref ) 2 (5.14) Finallythecorrespondingsignaltonoiseratio(SNR)duetotheleakyintegration is: SNR leaky = P signal P noise;leaky = (6 RV 3 dc G 2 m ) 2 C 2 V 4 ref E [ V 2 ( t )] E [( P i h i ( t )) 2 ] E [ P i h 2 i ( t )] (6 RV 3 dc G 2 m ) 2 C 2 V 4 ref E [ V 2 ( t )] (5.15)

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36 wheretheapproximationismadewiththeassumptionoflowoversamplingratio ( 2 f avg s ),aswediscussedinSection 5.3.1 Equation 5.15 showsthedependenceoftheSNRontheADCparameters andtheinputsignal.TheSNRcanbeincreasedbyaugmentingtheoutput resistanceRsincethecorrespondingleakycurrentisreduced.Smaller E [ V 2 ( t )], i.e.,smallersignalvariationduringtheintegrationperiodleadstolargerSNR. Equation 5.15 alsoimpliesthattheSNRisinverselyproportionaltothesignal amplitudeandfrequencysincetherst-orderderivativeoftheinputsignal V ( t )= A sin(2 ft )is V ( t )=2 fA cos(2 ft ).Equation 5.12 showsthatshorterintegration period T i leadstosmallerleakedchargevariation,andthereforelargerSNR. Sincetheintegrationperiod T i CV ref G m V i ,theSNRcanbeimprovedwithlarger transconductance G m andDCcomponent V dc orsmallercapacitance C and referencevoltage V ref ,whichisconsistentwithEquation 5.15 Inpractice,theaverageringrate f avg = G m V dc CV ref isrelatedtothesignal bandwidthoftheADCandisusuallyapredenednumber.Thisadditional constraintcomplicatesthechoicesoftheparameters G m V dc C and V ref .For example,increasinginsteadofdecreasing C isnowhelpfultoincreasetheSNR underthisconstraint.Tokeep f avg constant,either G m or V dc needtobeincreased, or V ref needstobedecreased,eachofwhichincreasestheSNRinawaythat outperformsthedecreasingoftheSNRduetotheincreasingofthe C .Thisshould notbeinterpretedcontrarytopreviousdiscussionssincetheconditionischanged duetotheadditionalconstraint. SeveralsimulationsareruninMatlabtovalidatethepreviousderivation. Withoutadditionaldeclarations,theparametersoftheADCare: C =10pF, V ref =2 : 5V, G m =6 : 2u 1 R =80M,andthesignalbandwidth s =2 10000 rad/s.Theinputsignalis V ( t )= V dc + A sin(2 ft )withaDCcomponent V dc = 0 : 234Vandasinewavewithanamplitude A =0 : 13Vandafrequency f =1kHz.

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37 Figure5{4: SNRvs.outputresistance Inthefollowingguresthesolidredlineandthedashedbluelinerepresentthe resultsfromthenumericalevaluationandtheEquation 5.15 ,respectively. Figure 5{4 showsthedependenceofSNRontheoutputresistance R .The equationmatchesthenumericalevaluationverywellwithaslopeof20dB/decade andamaximumSNRdierenceof3dB. Figure 5{5 showsthedependenceofSNRonthesinewaveamplitude A with thesignalfrequency f =8kHz.Theequationmatchesthenumericalevaluation verywellwithaslopeof 20dB/decadeandamaximumSNRdierenceof6dB. Figure 5{6 showsthedependenceofSNRonthesinewavefrequency f Theequationmatchesthenumericalevaluationverywellwithaslopeof 20 dB/decadeandamaximumSNRdierenceof3dB. Wemayalsoextendthepreviousderivationtothecaseoftreatingtheneuron asaleakyneuronduringreconstructionwiththeestimatedoutputresistance

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38 Figure5{5: SNRvs.Sinewaveamplitude Figure5{6: SNRvs.Sinewavefrequency

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39 R est =(1+ ) R .WecaneasilyobtaintheSNRduetotheestimationerror bysubstitutingthe R with(1+ 1 ) R inEquation 5.15 .Iftheestimationerror isaverysmallpositivenumber,theperformanceimprovementisveryobvious comparedtotreatingtheneuronasanidealIFneuronduringreconstruction. However,if isanegativenumberlessthan 0 : 5,theperformanceisevenworse comparedtotreatingtheneuronasanidealIFneuronduringreconstructionsince toomuchleakedchargeisestimated.Itiscleartoseethatthereconstruction performanceisverysensitivetotheaccuracyoftheestimatedoutputresistanceif wetreattheneuronasaleakyneuronduringreconstruction. 5.3.3ThermalNoiseoftheSpikingNeuron AnalogsignalsprocessedbyintegratedcircuitsincludingADCsarealways corruptedbynoise[26,27].TheeectofnoiseontheperformanceofanADCisso essentialthattheADCisusuallycharacterizedbythesignaltonoiseratio.The deviceelectronicnoisethatexistsinmostintegratedcircuitsincludesthermalnoise, shotnoiseandickernoise.Boththethermalnoiseandtheshotnoisearewhite bandnoise.Sincethethermalnoiseisatwo-sidedshotnoise[28],theireects shouldbesimilar.Inthefollowingdiscussionweonlyconsiderthethermalnoiseof thespikingneuron. Figure5{7: Noisemodelofthespikingneuron

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40 IntheblockdiagramofthespikingneuronTB-ADCinFigure 5{1 thereare threemajornoisesources:thetransconductanceamplier,thecomparator,andthe resettransistor.Comparedtothenoisefromthetransconductanceamplier,the noisefromthecomparatorisneglectedsincetheinput-referrednoiseisdividedby thelargevoltagegainofthecomparator.Thenoisemodelofthespikingneuron isshowninFigure 5{7 .Thethermalnoiseduetothetransconductanceamplier isreferredtoastheoutputcurrentnoisewithone-sidedpowerspectrumdensity (PSD)of i 2 n;amp =4 kTG m ,where k =1 : 38 10 23 J=K isBoltzmann'sconstant, T istheabsolutetemperatureinKelvin, istheexcessnoisefactor,and G m is thetransconductanceoftheamplier.Theoutputresistance R oftheamplieris avirtualresistanceduetothechannellengthmodulationoftheamplieroutput stageanddoesnotprovideanythermalnoisecontribution.TheNMOStransistor M 0 isinthetrioderegionmostofthetimeduringtheresetoperation,thereforethe thermalnoiseduetotheformedresistivechannelismodelledasthecurrentnoise withone-sidedPSDof i 2 n;reset =4 kT=R on duringtheresetoperation,where R on is thedrain-sourceresistancewith V DS =0. First,letustakealookatthethermalnoiseduetotheresettransistor M 0 Sinceduringtheresettime R ismuchlargerthan R on ,theformedRCnetworkcan beapproximatedbytheparallelconnectionof R on and C .Thenoisecurrentwith PSDof i 2 n;reset =4 kT=R on isappliedtotheRCnetworkandresultsinthenoise voltage.ThenoisebandwidthoftheRCnetworkisequalto 2 timesthecuto frequency,i.e., BW n;reset = 1 2 R on C 2 = 1 4 R on C (5.16) Thereforethenoisevoltagepowerduetotheresettransistor M 0 is V 2 n;reset = i 2 n;reset R 2 on BW n;reset = kT C (5.17)

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41 whichiscalled\kTCnoise"or\resetnoise",andisindependentonthevalueofthe R on oftheresettransistor. Wemaytrytoseeifwecanfollowasimilarideatocalculatethenoisevoltage powerduetotheamplier.Sinceduringtheintegrationperiod R off ismuchlarger than R ,theformedRCnetworkcanbeapproximatedbytheparallelconnectionof R and C .ThenoisecurrentwithPSDof i 2 n;amp =4 kTG m isappliedtotheRC network.Sincethenoisebandwidthis BW n;amp = 1 4 RC ,theresultednoisevoltage powerduetotheamplieris V 2 n;amp =4 kTG m R 2 1 4 RC = G m R kT C .Nowwehavea problemwiththisresult.Thesignalvoltage V c acrossthecapacitorisequalto V ref whentheneuronspikesandthusthesignalpowertakesonanitevalueof V 2 ref .If theamplierhasaninniteDCvoltagegain G m R ,basedontheabovederivation thenoisepowerwouldbeinnityandtheresultedSNRofthespikingneuron wouldbeequaltozero!Thisridiculousresultshowsthatsomethingiswrongwith thepreviousderivationofthenoisepowerduetotheamplier. Tofacilitatethefollowingdiscussion,typicalvaluesoftheparametersof interestaregivenbelow:theamplieroutputresistance R =80M,theamplier transconductance G m =6 : 2u 1 ,theintegrationperiod T i = t ie t ib =20us, thereferencevoltageofthecomparator V ref =2 : 5V,thechannelONresistance ofthetransistor R on =3 : 3k,theresettimeorequivalentlythespikewidth T reset = t ib t ( i 1) e =1 : 5us.Thereasonwhy R ismuchlargerthan R on isthat R istheoutputresistanceoftheampliercascodeoutputstagewhile R on isthe inverseofthetransconductanceoftheNMOStransistor M 0 withgateappliedwith thepositivepowersupplyvoltage V dd .DuringtheintegrationperiodtheNMOS M 0 isturnedoandthecorrespondingoresistance R off ismuchlargerthan R Actuallythenoisepowerduetowhitebandnoisesuchasthethermalnoise isafunctionoftime[29,30].Thecalculationofthenoisepowerusingprevious methodsisonlyvalidwiththeassumptionthatthesteadystateisachievedwithin

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42 theobservationtimeperiod.Fortheresetnoise,thisassumptionisvalidsince theresettime T reset =1 : 5usismuchlargerthantheRCnetworktimeconstant reset = R on C =33nsandthesteadystateisachieved.However,forthenoisedue totheamplier,thetransientresponseofthenoisepowerneedstobeconsidered sincetheintegrationperiod T i =20usisevenlessthantheRCnetworktime constant int = RC =800usandthecircuitisfarfromsettled.Thegoverning equationoftheRCnetworkwiththecurrentinput i n;amp ( t )andthevoltageoutput V n;amp ( t )is: i n;amp ( t )= C dV n;amp ( t ) dt + dV n;amp ( t ) R (5.18) Assumetheintegrationperiodbeginsat t =0.Thetransientresponseofthe voltage V n;amp ( t )is V n;amp ( t )= Z t 0 i n;amp ( ) C e t RC d (5.19) Thenthenoisepowerduetotheamplierintheendoftheintegrationperiod T i is V 2 n;amp = Z T i 0 R ( ) C 2 e 2( T i ) RC d = Z T i 0 2 kTG m C 2 e 2( T i ) RC d = kTG m R C (1 e 2 T i RC ) (5.20) where R ( )=2 kTG m isthetwo-sidedpowerspectraldensityoftheampliercurrentnoise.Iftheintegrationperiod T i goestoinnitythenoisepowerapproaches thesteadystate kTG m R C derivedearlier.Iftheintegrationperiod T i ismuchless thanthetimeconstant RC ,whichisthecasehere,thenoisepowerduetothe ampliercanbeapproximatedby V 2 n;amp = 2 kTG m T i C 2 (5.21) Notingthattheaverageintegrationperiod T i = CV ref V dc G m where V dc istheDC componentorthemeanoftheinputvoltagesignal V ( t ),wemayfurthersimplify

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43 Equation 5.21 as: V 2 n;amp = kT C ( 2 V ref V dc )(5.22) Thenoisesduetotheresettransistor M 0 andtheamplierareuncorrelated, thereforethetotalnoisepowerisequaltothesumofthesetwonoisepowers. AddingEquation 5.17 5.22 ,weobtain, V 2 n = V 2 n;reset + V 2 n;amp = kT C (1+ 2 V ref V dc ) kT C ( 2 V ref V dc ) (5.23) wheretheapproximationisvalidduetothefactthat ismuchlargerthan1and V dc isusuallylessthan V ref Thepowerofthereconstructionnoiseduetothethermalnoiseofthespiking neuronis: P noise;thermal = E [( V ( t ) ^ V ( t )) 2 ] = 1 G 2 m E [( x ( t ) ^ x ( t )) 2 ] = 1 G 2 m E [( X i h i ( t )( i )) 2 ] = 1 G 2 m E [( X i h i ( t )( CV n )) 2 ] = 1 G 2 m C 2 V 2 n X i E [ h 2 i ( t )] = 1 G 2 m 2 kT V dc E [ X i h 2 i ( t )] (5.24) Thesignalpoweris: P signal = E [( V ( t )) 2 ] = 1 G 2 m 2 E [( X i h i ( t )) 2 ] (5.25)

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44 Finallythecorrespondingsignaltonoiseratio(SNR)duetothethermalnoiseis: SNR noise = P signal P err;noise = V dc 2 kT E [( P i h i ( t )) 2 ] E [ P i h 2 i ( t )] V dc 2 kT (5.26) wheretheapproximationismadewiththeassumptionoflowoversamplingratio ( 2 f avg s )aswediscussedinSection 5.3.1 Equation 5.26 indicatesthatincreasingthethreshold = CV ref ortheDC component V dc oftheinputsignalordecreasingtheexcessnoisefactor arehelpful toalleviatetheADCperformancedegradationduetothethermalnoise.Special attentionshouldbepaidtothereasonwhyalarger V dc ishelpful.Assume and arethesame,larger V dc resultsinhigheraverageringrateorsmallerintegration periodwhichindicateslessthermalnoisepowerbasedonEquation 5.21 sothat theSNRisimproved.ItisinterestingtonotethattheSNRisnotdependenton thetransconductance G m ortheoutputresistance R .Astothe R ,if R islarger, theleakycurrentissmaller,thenetcurrentchargingthecapacitorislargerand theintegrationperiodissmaller.Again,thesetwoeectscanceleachotherand theresultingnoisepowerremainsthesame.Astothe G m ,if G m islarger,the noisecurrentislargerwhiletheintegrationperiodissmaller.Thesetwoeects canceleachotheranddonotaectthenoisepower.However,inpracticalcircuit implementationtheexcessnoisefactorisweaklydependentontheinverseof G m thereforealarger G m shouldprovidebetternoiseperformance. Inpractice,theaverageringrate f avg = G m V dc CV ref isrelatedtothesignal bandwidthoftheADC,andisusuallyapredenednumber.Equation 5.26 canbe furthersimpliedas: SNR noise V dc 2 kT = 2 f avg 2 kTG m (5.27)

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45 Withtheconstraintofconstant f avg ,theinputsignalpowerisproportionalto 1 =G 2 m whiletheinputreferrednoisepowerisproportionalto G m =G 2 m =1 =G m thereforeasmaller G m improvestheSNR.Thisshouldnotbeinterpretedcontrary topreviousdiscussionssincetheconditionischangedduetotheadditional constraint. SimulationsareruninMatlabtovalidatethepreviousderivation.Without additionaldeclarations,theparametersoftheADCare: C =10pF, V ref =2 : 5V, G m =6 : 2u 1 ,andthesignalbandwidth s =2 10000rad/s.Theinputsignal is V ( t )= V dc + A sin(2 ft )withaDCcomponent V dc =0 : 234Vandasinewave withanamplitude A =0 : 13Vandafrequency f =1kHz.Theoutputcurrent noisewithone-sidedPSDof i 2 n;amp isgeneratedusingthenormaldistribution noisefunction\ randn "inMatlab[31].Let Var ,and T n bethevarianceandthe samplingperiodofthenormaldistributionnoise,respectively.Thereforethenoise bandwidthis BW n = 1 2 T n ,andtheone-sidedpowerspectraldensityequalsto Var BW n =2 T n Var [32].Figure 5{8 showsthedependenceofSNRontheoutputnoise currentpowerspectraldensity(PSD).Sincethetransconductance G m isxed, varyingtheexcessnoisefactor isequivalenttovaryingthePSD.Inthegure theredsolidline,thegreendash-dottedline,andthebluedottedlinerepresent thenumericalevaluationresultswith R =80Mand R = 1 ,andtheresults fromEquation 5.27 ,respectively.Thetwosimulatedcurveswithdierentoutput resistancesmatchverywellexceptthattheSNRofthecurvewith R =80M saturatesataround78dBduetotheleakyintegrationeect.Thisveriesthat theSNRisindependentontheoutputresistance.Theequationresultsmatch thenumericalevaluationresultsverywellwithaslopeof10dB/decadeanda maximumSNRdierenceof7dB.

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46 Figure5{8: SNRvs.thermalnoisecurrentpowerspectraldensity 5.3.4SignalDependentReferenceVariationoftheComparator ThesamplingoperationofthespikingneuronTB-ADCisrealizedusinga comparatorinFigure 5{9 .Whenthevoltage V c acrossthecapacitorrisesabovethe referencevoltage V ref ofthecomparator,theoutputvoltage V o ofthecomparator goeshightoreachthelogicstate\1".Thisrisingtransitiontimeistheendtime t ie ofthe ith integrationperiod.Aftersometimedelay,thecapacitorisreset togroundandtheoutputofthecomparatorgoeslowtoreachthelogicstate \0".Thisfallingtransitiontimeisthebeginningtime t ( i +1) b ofthe( i +1) th integrationperiod.Thesetwotransitiontimingsandthecapacitorvoltagesat thesetwotransitiontimingstogetherdescribethesamplingoperation.Forthe idealcase,theoutput V o caninstantaneouslyreachthedigitallogicstatewhen V c reachesthenominalreferencevoltage V ref .Inpractice,thecomparatorhasa niteDCgainandanitebandwidthandneedssometimetoresolvetothelogic state.ForconventionalADCsthisresultsinthemetastablephenomenaduring

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47 Figure5{9: Signaldependentreferencevoltagevariationofthecomparator.High andlowslewrateareshownassolidordashedrespectively comparison[33,34].ForTB-ADCsthecomparatorshowssometimedelayor referencevariationcharacteristics.Figure 5{9 illustratesoutputsofthecomparator withinputswithdierentslewrates.Assumewhen t =0theinput V c = V ref and theoutput V o =0isatthesmallsignalground.Thecomparatorresolvestothe logicstatewhen V o reaches V d ,andthevalueof V c atthismomentisdenedasthe eectivereferencevoltageofthecomparator,andcorrespondinglythedelaytimeis denedasthetimethatthecomparatorneedstotakefrom V o =0to V o = V d .We canseethattheinputwithhigherslewrate(solidline)hasashortertimedelay ( t h V ref;l )thantheinput withlowerslewrate(dashedline).Thissignal-dependenttimedelayorreference variationdegradestheADCperformanceanditseectneedstobeinvestigated. Assumethecomparatorcanbemodelledasaone-polesystemwiththe transferfunction V o ( s ) V c ( s ) = A c 1+ s c (5.28) where A c istheDCvoltagegainand c isthetimeconstant.Assumetheinput V c = V ref andtheoutput V o =0when t =0,andtheinputsignal V ( t )= V ( t = t ie )= V i duringthecomparisonperiodwhichisusuallyveryshortcomparedtothe

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48 periodofthesignal.Thus V c canbeexpressedby V c ( t )= V ref + G m V i t C (5.29) where G m isthetransconductanceofthetransconductanceamplier.Actually theslewrateofthecomparatorinput V c isequalto G m V i C whichisproportional totheinputsignalvalue V i .Thereforeitisequivalenttosaylargerinputsignal value V i totheADCorhigherslewrateoftheinputtothecomparator.We alsoassumethatwhenthetimedelay t equalsto t d ,theoutput V o ( t )reaches V d andthecomparatorresolvestothelogicstate.Fromtheaboveassumptionsand Equations 5.28 5.29 ,wecanobtain V d = A c G m V i C ( t d c (1 e t d c ))(5.30) andthereforetheactualreferencevoltagevariationis V ref;act V ref = G m V i t d C (5.31) Equations 5.30 5.31 showthatthetimedelay t d andthereferencevariation V ref;act V ref aredependentonthesampledsignalvalue V i .Itisnecessaryforus todierentiatebetweentwoscenarios:lowerorhigherslewrateinput V c tothe comparator,orequivalentlysmallerorlargerinputsignal V i totheADC. Lowerslewratecomparatorinput V c ,orsmallerADCinputsignal V i Iftheinputsignal V i isverysmall,theslewrateoftheinputtothecomparatorissmall,orequivalentlythecomparatorisrelativelyveryfast,thecomparator canrespondquicklytotheinput.Inthisscenario,thetimedelay t d c andwe cancalculatethetimedelayandthereferencevariationfromEquations 5.30 5.31 as: t d;l = CV d A c G m V i + c (5.32)

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49 V ref;l V ref = V d A c + G m V i c C (5.33) Equation 5.33 showsthattheeectivereferencevoltageis V ref + V d A c + G m V i c C at theendtime t ie ofthe ith integrationperiod.Since V ref;l isdependentonthesignal value V i = V ( t = t ie )andcannotbeobtainedbeforereconstruction,wehavetouse aniterativemethodtoperfectlyreconstructthesignal V ( t ).Howeverifwetakea closerlookatEquation 5.32 5.33 ,wemayremovethesignaldependentterm G m V i c C fromEquation 5.33 and c fromEquation 5.32 ,andtreatthenewactualreference voltageas V ref + V d A c whiletheendtimeof ith integrationperiodis t ie c .Inthis way,ifweknowexactlytheparameterssuchas V ref ;V d ;C;G m ; c ,and A c ,wecould perfectlyreconstructtheinputsignal V ( t )usingtheWLPKmethoddiscussedin Section 4.3 .Howeverinpracticethecomparatorcannotbefullycharacterizedby Equation 5.28 withconstants A c and c .Theincorrectestimationof c unavoidably introducessomeerrorintothereconstructedsignal,althoughtheerrorispredicted tobereducedbyincreasingthecomparatorspeed.Withtheassumptionthat thetimedelayismuchlargerthanthetimeconstant,thecomparatorneedsvery highspeedandconsumesverylargepowerandisnotagoodchoiceforlowpower applications. Higherslewratecomparatorinput V c ,orlargerADCinputsignal V i Iftheinputsignal V i isverylarge,theslewrateoftheinputtothecomparatoris high,orequivalentlythecomparatorisrelativelyveryslow,thecomparatorcannot respondquicklytotheinput.Inthisscenario,sincethetimedelay t d c and e x 1+ x + x 2 2 for x 1,Equation 5.30 canbeapproximatedby: V d = A c G m V i C ( t d c (1 (1 t d c + t 2 d 2 2 c ))) = A c G m V i t 2 d 2 C c (5.34)

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50 Andthetimedelayisthen: t d;h = r 2 CV d c A c G m V i (5.35) FromEquation 5.31 5.35 ,weobtaintheactualreferencevoltagevariationas: V ref;h V ref = r 2 V d G m V i c A c C (5.36) Equation 5.36 showsthattheactualreferencevoltageis V ref + q 2 V d G m V i c A c C attheendtime t ie ofthe ith integrationperiod.TheADCperformanceislargely degradedduetothesignaldependentreferencevariation.InpracticetheDC componentoftheinputsignalcanbeeasilymeasured,andthetimedelayassociatedwiththeDCcomponentcanbeobtainedbeforesignalreconstructionas t d;dc = q 2 CV d c A c G m V dc .IfthetimedelayoftheDCcomponentisconsideredinthe reconstruction,betterreconstructionperformanceisexpected. WemayfollowthemethodinSection 5.3.1 tocalculatetheSNRduetothe signaldependentreferencevariation.Theactualintegrationoftheinputsignal V ( t )forthe i thintegrationperiodis: Z t ie t d;dc t ib G m V ( t ) dt = Z t ie t ib G m V ( t ) dt Z t ie t ie t d;dc G m V ( t ) dt i G m V i t d;dc (5.37) wheretheapproximationismadewiththeassumptionthat V ( t )doesnotvarytoo muchfortheshortperiodfrom t = t ie t d;dc to t = t ie .However,thenominal integration = CV ref isusedinthereconstructionandthisthresholderror accountsfortheperformancedegradation.Thethresholderrorduetothesignal dependentreferencevariationis: i G m V i t d;dc = CV ref;h G m V i t d;dc CV ref = r 2 V d CG m V i c A c G m V i r 2 CV d c A c G m V dc = p k ( p V i V i p V dc ) (5.38)

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51 where k = 2 V d CG m c A c forsimplication.Wecanseethatthethresholdvariation equalstozeroiftheADCinputsignal V ( t )= V dc .Thenoisepowerduetosignal dependentreferencevariationis: P noise;comp = E [( V ( t ) ^ V ( t )) 2 ] = 1 G 2 m E [( x ( t ) ^ x ( t )) 2 ] = 1 G 2 m E [( X i h i ( t )( i G m V i t d;dc )) 2 ] = k G 2 m X i E [ h 2 i ( t )] E [( p V i V i p V dc ) 2 ] +2 k G 2 m X i 6= j E [ h i ( t ) h j ( t )]( E [ p V i V i p V dc ]) 2 = k G 2 m ( X i E [ h 2 i ( t )] E [ V i ] k 1 +2 X i 6= j E [ h i ( t ) h j ( t )] E [ V i ] k 2 ) (5.39) wherethecoecients k 1 and k 2 willbecalculatedlater.Wemaytreat V i asan identicalindependentlydistributedrandomvariablewhichisuniformlydistributed insignalregion[ a;b ]where a and b aretheminimumandthemaximumofthe signal.Wecanobtainthefollowingexpectedvalues: E [ V i ]= a + b 2 = V dc E [ V 0 : 5 i ]= b 1 : 5 a 1 : 5 1 : 5( b a ) E [ V 1 : 5 i ]= b 2 : 5 a 2 : 5 2 : 5( b a ) E [ V 2 i ]= b 3 a 3 3( b a ) (5.40) Thereforethecoecients k 1 and k 2 inEquation 5.39 arecalculatedasbelow: k 1 = E [( p V i V i p V dc ) 2 ] E [ V i ] =1+ 4( m 3 1) 3( m 1)( m +1) 2 4 p 2( m 2 : 5 1) 2 : 5( m 1)( m +1) 1 : 5 k 2 = ( E [ p V i V i p V dc ]) 2 E [ V i ]

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52 Figure5{10: PlotsofcoecientsC1andC2forsignaldependentthresholdvariation = 2( m 1 : 5 1 1 : 5( m 1) q m +1 2 ) 2 m +1 (5.41) where m = b a isanumberlargerthan1.Figure 5{10 showstheplotsof k 1 and k 2 for m varyingfrom1 : 01to10. k 1 and k 2 quicklydecreaseas m approaches1, orequivalentlythevariationof V ( t )decreases. k 2 ismuchsmallerthan k 1 and thereforecanbeneglectedinEquation 5.39 .WecanfurthersimplifyEquation 5.39 as: P noise;comp kk 1 G 2 m E [ X i h 2 i ( t )] V dc (5.42) Thesignalpoweris: P signal = E [ V 2 ( t )] = 1 G 2 m E [( X i h i ( t ) ) 2 ] 2 G 2 m E [( X i h i ( t )) 2 ] (5.43)

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53 Therefore,thesignaltonoiseratio(SNR)duetothesignaldependentreference variationis: SNR comp = P signal P noise;comp = 2 kk 1 V dc E [( P i h i ( t )) 2 ] E [ P i h 2 i ( t )] CV 2 ref f u k 1 V d V dc G m = V ref f u k 1 V d f avg (5.44) wheretheapproximationismadewiththeassumptionoflowoversamplingratio ( 2 f avg s )aswediscussedinSection 5.3.1 f avg = G m V dc CV ref istheaverageringrateof theneuronencoder, f u = A c 2 c istheunitygainfrequencyofthecomparator,and k 1 isacoecientdeterminedbytheinputsignalrangeasshowninFigure 5{10 InordertoimproveSNR,wecaneitherincreasethereferencevoltageortheunit gainfrequencyofthecomparator,ordecreasethecomparatoroutputvoltageswing neededtoreachthelogicstateortheaverageringrate.Therearemanytradeos whenselectingtheseparameters.Larger V ref worsenstheSNRduetotheleaky integrationaswediscussedbefore.Larger f u meansthatthecomparatorneedsto consumemorepower.Smalleroutputvoltageswing v d ofthecomparatormeans thatthenoisemarginisreducedandthereforemoresensitivetonoise. SimulationsareruninMatlabtovalidatethepreviousderivation.Without additionaldeclarations,theparametersoftheADCare: C =10pF, V ref =2 : 5V, G m =6 : 2u 1 R =80M,thecomparatoroutputvoltageswing V d =0 : 7V, thecomparatorDCgain A c =109,andthesignalbandwidth s =2 10000rad/s. Theinputsignalis V ( t )= V dc + A sin(2 ft )withaDCcomponent V dc =0 : 234 Vandasinewavewithanamplitude A =0 : 13Vandafrequency f =1kHz. Fromthedistributionofthesignal V ( t )wecancalculatethecoecient k 1 =0 : 025. TheplotofSNRvs.thecomparatortimeconstantisshowninFigure 5{11 .The solidredlineandthedashedbluelinerepresenttheresultsfromthenumerical evaluationandtheEquation 5.44 ,respectively.Whenthetimeconstantislessthan 100ns,theSNRfromthenumericalevaluationdeviatesfromthepredictionof theequation.Thisisbecausethedelaytime t d isnotlessthanthetimeconstant

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54 Figure5{11: SNRvs.comparatortimeconstant andtheassumptionofEquation 5.44 isnolongervalid.Overall,thenumerical evaluationresultssupportthepredictionoftheequationverywell. Powerconsumptionlimitation. Itisalwaysofinteresttoinvestigatethe minimumpowerconsumptionneededforacceptableADCperformance.IftheADC inputisacurrentsignalandthetransconductanceamplierisnotneeded,most ADCpowerisconsumedbythecomparator.Wemayndthispowerlimitfromthe relationshipbetweenthecomparatorunitygainfrequencyandtheSNRasshownin Equation 5.44 IfweassumethattheinputstageofthecomparatorisrealizedwithadifferentialMOStransistorpairworkinginthesquare-lawregion,thecomparator transconductance g m;comp canbeexpressedas: g m;comp = p I bias (5.45)

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55 where I bias isthetotalbiascurrentofthedierentialpairand = C ox W L is onlydeterminedbythesizeofthetransistorandtheVLSItechnologyprocess parameters.Theunitygainfrequency f u ofthecomparatoris f u = g m;comp C o;comp (5.46) where C o;comp istheoutputcapacitanceofthecomparator.SubstitutingEquations 5.45 5.46 intoEquation 5.44 ,wecanobtain SNR comp = V ref p I bias k 1 V d C o;comp f avg (5.47) ThereforeweestablishtheconnectionbetweentheSNRandthebiascurrent,or equivalentlythepowerconsumptionofthecomparator,andmaytheoreticallyestimatetheminimumnecessarybiaspowerconsumptionforsomespecicSNR.We shouldalsobeawarethatthetotalpowerconsumptionoftheADCsalsoincludes thedynamicpowerconsumptionandtheshort-circuitpowerconsumption,which arenotconsideredinEquation 5.47 .Generallyspeaking,withtheassumptionthat thetimedelayismuchlessthanthetimeconstant,thecomparatordoesnotneed highspeedandthereforeconsumeslesspowermakingitsuitableforlowpower applications. 5.4PracticalIssuesRelatedtoReconstructionfromSpikingNeuron Models ForconventionalADCs,performanceisonlydeterminedbytheencodingand digitizationcircuitry.Howeverforthecaseoftime-basedADCs,theadditional DSPreconstructioncomponentalsoplaysaveryimportantroleindetermining theADCperformanceasshowninChapter 4 .Weneedtoconsidereectsof somenonidealitiesontheperformanceofthereconstruction.Inpracticethetime quantizercanbeputeitherintheADCfrontendwiththespikingneuronencoder together,orintheADCbackendwiththeDSPreconstructionalgorithm.To

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56 furtherreducethepowerconsumptioninthefrontendthelatterispreferredand thereforethediscussionoftimequantizationisincludedinthissection. 5.4.1TimingJitteroftheTimeQuantizer Thetimingoftheoutputspiketrainofthespikingneuronencoderisstill inanalogformandmustbedigitizedtobeprocessedbyaDSP.Thisisusually donebysynchronizingthespiketraintoafastclockandrecordingthequantized timestamp.Thissynchronizationwillintroducesometimejittertotherecorded arrivaltimings( t ib and t ie )ofeachspike.Theeectofthetimingjitterdegrades thereconstructionperformanceandneedstobeinvestigated. Weassumethatthetimingjittersassociatedwiththeoriginalspiketimings t ib and t ie are n ib and n ie respectively,whichareindependentidenticalrandom variablesuniformlydistributedin[ T c = 2 ;T c = 2]where T c istheclockperiodof thequantizationclock.Theactualrecordedbeginningandendingtimeofthe i th interspikeintervalare ^ t ib = t ib + n ib (5.48) ^ t ie = t ie + n ie (5.49) Ifweknowtheexactvalue i = G m R ^ t ie ^ t ib V ( t ) dt wecanrewriteEquation 4.9 as follows V ( t )= 1 G m X i h i ( t ) i (5.50) where h i ( t )iscalculatedbasedontherecordedspiketiming ^ t ib and ^ t ie .However, duetothenoisynatureoftherecordedspiketimingswecannotobtaintheexact valueof i ,butonlyusetheencodingequation = G m R t ie t ib V ( t ) dt toobtainthe reconstructedsignalas ^ V ( t )= 1 G m X i h i ( t ) (5.51) Thusthedierencebetweentheinputsignal V ( t )andthereconstructedsignal ^ V ( t )representstheerrorduetothetimingjitterswhichobviouslydegradesthe

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57 reconstructionperformance.Wecancalculate( i ): i = G m Z ^ t ie ^ t ib V ( t ) dt G m Z t ie t ib V ( t ) dt = G m Z ^ t ie t ie V ( t ) dt G m Z ^ t ib t ib V ( t ) dt = G m V ( ^ t ie )( ^ t ie t ie ) G m V ( ^ t ib )( ^ t ib t ib ) = G m V ( ^ t ie ) n ie G m V ( ^ t ib ) n ib (5.52) whereforthethirdequationweassumethetimerclockperiod T c ismuchlessthan theNyquistperiod T = = s ,andthesignal V ( t )isapproximatedbyaconstantin theverysmalltimeintervals[ t ie ; ^ t ie ]and[ t ib ; ^ t ib ]. Thepowerofthereconstructionnoiseduetothetimingjitterofthequantizationclockis: P noise;jitter = E [( V ( t ) ^ V ( t )) 2 ] = 1 G 2 m E [( X i h i ( t )( i )) 2 ] = E [( X i h i ( t )( V ( ^ t ie ) n ie V ( ^ t ib ) n ib )) 2 ] (5.53) Since n ib and n ie areindependentidenticalrandomvariables,wehave E [ n ib n jb ]= E [ n ie n je ]= 8 > < > : 0: 8 i 6= j T 2 c = 12: 8 i = j E [ n ib n je ]=0 8 i;j (5.54) AfterfurthersimplifyingEquation 5.53 wecanobtainthenoisepower: P noise;jitter = X i E [ h 2 i ( t )]( E [ V 2 ( ^ t ie )]+ E [ V 2 ( ^ t ib )]) T 2 c = 12 = E [ X i h 2 i ( t )] P signal T 2 c = 6 (5.55) Thereforethecorrespondingsignaltonoiseratio(SNR)duetotimingjitteris: SNR jitter = P signal P noise;jitter

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58 = 6 E [ P i h 2 i ( t )] T 2 c 6 2 E [( P i h 2 i ( t ) ) 2 ] T 2 c = 6 2 G 2 m P signal T 2 c 6 2 G 2 m V 2 dc T 2 c 6 f 2 avg T 2 c (5.56) wheretheapproximationismadewiththeassumptionoflowoversamplingratio ( 2 f avg s )aswediscussedinSection 5.3.1 ,theDCcomponent V dc isdominantinthe signal V ( t ),andtheaverageringrate f avg = G m V dc FromEquation 5.56 wecanseethattheSNRisinverselyproportionaltothe averageringrate f avg ,whichisreasonablesincethesameamountoftimingjitter disturbsthespiketimingswithsmallerinterspikeintervaltoamuchworsedegree. WecanalsoseethattheSNRisinverselyproportionaltotheclockperiodwith aslopeof20dB/decade,whichcangiveussomehintstodeterminehowfastthe digitalsynchronizationclockmustruninordertoachieveparticularlevelsofSNR. Figure 5{12 showsaplotofSNRvs.thesimulatedclockperiodforthesame randomnoiseinputusedinFigure 4{2 .Whentheclockperiodislessthan1ns, thetimingjitternoiseisnotthedominanterrorsourceandthereconstruction SNRsaturatestoavaluedeterminedbythecalculationroundoerrors.Whenthe clockperiodislargeenough,thetimingjitternoisedegradestheSNRwithaslope ofapproximate20dB/decadeclockperiod.Thethenumericalevaluationresults verifythepredictionmadebyEquation 5.56 5.4.2KernelSelectionoftheDSPReconstructionAlgorithm Thelow-passkernelplaysaveryimportantroleintheDSPreconstruction algorithm.InSection 4.3 theideallow-passkernel h ( t )=sin( s t ) = ( s t )isused tomathematicallyreconstructthesignal.Inpracticewecannotimplementperfect

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59 Figure5{12: PlotofSNRvs.clockperiodusedinreconstruction reconstructionduetononidealitiesandthereforedierentkernelsneedtobe investigated. OneassumptionoftheperfectreconstructionintheWLPKmethodisthat thekernel h ( t )andthesignal V ( t )areinnitelylongintimeandaninnite numberofspikesareavailable.However,duetostoragelimitations,computation complexitylimitation,andreal-timerequirements,awindow-basedreconstruction isneeded.Ineachtimewindow,onlyanitenumberofspikescanbeprocessed toreconstructanitelengthofthesignal.Correspondinglythelow-passkernel h ( t )usedistruncatedandhasonlynitelength,whichintroducessometruncation errorinthetimedomainandsomenon-ideallow-passlteringperformanceinthe frequencydomain.ThemagnitudeoftheSinckernelwiththelengthof60Nyquist periodsisshowninFigure 5{13 .Wecanseethatthemagnitudedecaysveryslowly intimeandthemaximumtruncationerrorcanbeaslargeas 40dBwhichis notnegligible.Sincethetruncationerrorisdependentonthesignallength,the

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60 Figure5{13: PlotofSinckernelvs.kernellength performanceofthereconstructionshouldalsobedependentonthesignallength usedinthereconstruction. Figure 5{14 showstheplotofSNRusingSinckernelvs.signallengthusedin thereconstruction.AGaussianrandomnoisesignalbandlimitedto[ 3000 ; 3000 ] isinputtoanintegrate-and-reneuron.Theaverageringrateis14kHz.Since themaximumadjacentspikeinterval(0 : 162ms)islessthantheNyquistperiod T =1 = 3ms,theWLPKmethodisusedtoreconstructtheinputsignalfromthe spiketrain.Wecanseethatthesignaltoerrorratio(SNR)isstronglydependent onthesignallength.Whenthesignalisabout20NyquistperiodslongtheSNR variesbetween80dBand100dB,whilewhenthesignalisabout120Nyquist periodslongtheSNRvariesbetween106dBand116dB.Itcanbeobservedthat themeanvalueoftheSNRincreasesandthevariationoftheSNRdecreasesas thesignallengthusedincreases.TheSNRvariationisverysensitivetothesignal

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61 Figure5{14: PlotofSNRusingthetruncatedSinckernelvs.signallengthusedin thereconstruction length.InordertohavealargeSNRwithsmallvariation,weneedtouseavery longsignallength. Gaussiankernel. Toreducethetruncationerrorandthedependenceof theSNRonthesignallength,weneedthekerneltohaveafasttimedecaying propertyandagoodlow-passlteringcharacteristics.TheGaussiankernelisa goodcandidateandisshownbelow: h g ( t )= e t 2 2 2 (5.57) AFouriertransformisneededtondtherelationshipbetweenthecutofrequency f c and .TheFouriertransformofEquation 5.57 is: H g ( f )= Z + 1 e t 2 2 2 e j 2 ft dt = p 2 e 2 2 f 2 2 Z + 1 1 p 2 e ( t + j 2 f 2 ) 2 2 2 dt = p 2 e 2 2 f 2 2 (5.58)

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62 Figure5{15: PlotofGaussiankernelvs.kernellength FromEquation 5.58 wecanndthe3-dBcutofrequency: f c = p 0 : 5ln2 = 0 : 1874 (5.59) Figure 5{15 showsthemagnitudeoftheGaussiankernelwiththelengthof4 Nyquistperiods.TheGaussiankernelonlyneeds1 : 25Nyquistperiodstodecay to 40dBlevelwhiletheSinckernelneeds30NyquistperiodsinFigure 5{13 TheGaussiankernelhasmuchfastertimedecayingpropertyandlesstruncation errorthantheSinckernel,andthereforethesignalreconstructionSNRshould belessdependentonthesignallength.Figure 5{16 showstheplotofSNRusing Gaussiankernelvs.signallengthusedinthereconstruction.Theinputsignaland theintegrated-and-reneuronarethesameasthoseinFigure 5{14 .Thecuto frequency f c =1500Hz,andtherefore =0 : 1874 =f c =12 : 5ms.Forthesignal lengthshorterthan26T,thevariationoftheSNRisverylarge.However,fora signallengthlongerthan26TtheSNRincreasesslowlyfrom114dBto120dB withverysmallvariation.ComparedtotheSinckernel,signalreconstructionusing

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63 Figure5{16: PlotofSNRusingthetruncatedGaussiankernelvs.signallength usedinthereconstruction thetruncatedGaussiankernelislessdependentonthesignallength,andtherefore shortersignallengthcanbeusedinthereconstruction. Computationcost. Asidefromthesignaltonoiseratioofthereconstructedsignal,anothercriteriatoevaluatetheperformanceofthespikingneuron TB-ADCisthecomputationcost.SincetheTB-ADCtradesosimpleranalog circuitryformorecomplexdigitalcircuitry,thecomputationburdenisputonthe DSPreconstructionalgorithm.Computationresourcesarenotfreeandshouldbe consideredinpractice.Onecomputationcostisthestorageneededforthecomputation.Toreducethecostofthememory,smallerstorageispreferable.Another computationcostistherequiredFLOPrateoftheDSPwhichisusuallyspecied bythenumberofoating-pointoperationspersecond(FLOPS).FLOPSisacommonbenchmarkmeasurementforratingthespeedofmicroprocessorsinDSPs.A lowerFLOPSnumberimpliesthatslowermicroprocessorscanbeusedwhichlowers thecost.Sincemultipliesanddividesaretypicallymoretimeconsumingthan

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64 (a)(b) Figure5{17: PlotsoftherowvectorofthematrixCusingSincandGaussiankernels.(a)20throw.(b)80throw additionandsubstractioninDSP,onlythemultipliesanddivisionareconsidered asoating-pointoperationsinthisanalysis. Sincemostcomputationisspentonsolvinglinearequationstocalculatethe weightsinEquation 4.8 ,onlythiscomputationcostisconsidered.Assumethe coecientmatrix C isa N N matrix,andtheweightvector W andthecharge vector are N 1vectors.Itisgoodtocheckiftheelementsofthematrix C have somespecialpropertiessothatthecomputationcanbesimplied.Figure 5{17 showstheelementsofthe20th(a)and80th(b)rowvectorsofthematrix C with N =100usingSincandGaussiankernels.Itisinterestingtonotethatthecurve shapeisnotexact,butsimilartotheshapeoftherespectivelow-passkernelused inthereconstruction.Thisisbecausetheelement c ij = R t ie t ib h ( t s j ) dt isthe integrationoftherespectivekerneloverthe ith integrationperiod.Thecurveshape ofdierentrowsaregenerallysimilarexceptthatthepeaklocatesindierent columnsthatareequaltotherespectiverownumbers.Forexample,thepeakof the20throwlocatesinthe20thcolumnwhilethepeakofthe80throwlocatesin the80thcolumn.Duetothefasttimedecayingofthecurveoftherowvectorof thematrix C usingGaussiankernel,mostelementsareverysmallandnegligible.

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65 Thereforethematrix C isapproximatelyabandedmatrixwithelementscentered aroundthemaindiagonal.Thebandwidth M ofthematrix C isdenedasthe numberofnon-zeroelementsineachrowofthematrix C .Thenumber M is determinedbytheproductoftheaverageringrate f avg andtheNyquistperiod T ,andisamuchsmallernumber,say15,thanthedimension N ofthematrix C if theoversamplingratioisnothigh.Thematrix C usingtheSinckernelisusually amatrixwithafullbandwidth,i.e., M = N ,duetotheslowtime-decayingofthe Sinckernel. ThereforethecomputationstorageofthereconstructionusingtheGaussian kernelis N M ,andismuchsmallerthanthatofthereconstructionusingtheSinc kernelwhichis N N .ThecomputationcomplexityisestimatedusingGaussian elimination[21,22].Thenumberofoating-pointoperationsofthecomputation ofthematrix C usingGaussiankernelis NM 2 = 4consideringitsbandedproperty, whilethatofthematrix C usingSinckernelis N 3 = 3.Assumethecomputation timeis t comp ,therequiredFLOPrateoftheDSPforthereconstructionusingthe Gaussiankernelis FLOPS Gaussian = NM 2 = 4 t comp (5.60) TherequiredFLOPrateoftheDSPforthereconstructionusingtheSinckernelis FLOPS Sinc = N 3 = 3 t comp (5.61) Sincethematrixbandwidth M ismuchsmallerthanthematrixdimension N therequiredFLOPrateoftheDSPofthereconstructionusingGaussiankernel ismuchlessthanthatofusingSinckernel.IftheSVD-basedpseudo-inverse conditioningtechniqueisusedinsolvingtheweights,thenumberofoating-point operationsforusingGaussiankernelorSinckernelisontheordersof N 2 M or N 3 respectively[35].

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66 Windowing. Inmanyapplicationssuchasremotesensing,theTB-ADC needstoperformreal-timeanalog-to-digitalconversion.ThereforetheDSP reconstructionalgorithmneedstobeimplementedinawindow-basedform. Thewholesignalisreconstructedbypiecingtogethersignalsrespectively reconstructedineachtimewindow.Figure 5{18 showsthiswindowingscheme. Sincethereconstructedsignalonthesideofeachwindowispronetothekernel truncationerrorandaccountsformostreconstructionerror,weusuallydiscard asmallpercentage,say10%,ofthesignalonthesideofeachwindow(theblank regioninthegure),andthereforeonlykeep80%ofthereconstructedsignal (theshadowedregioninthegure).Assumeat t = t 4 thebuerreceivesthe completespiketrainoftherstwindow WIN 1 whichspansfrom t 0 to t 4 andthe algorithmbeginstoperformthereconstruction.Meanwhile,thespiketrainforthe secondwindow WIN 2 beginstobestoredinthebuer.At t = t 7 thealgorithm nishesthereconstructionofthewindow WIN 1 andoutputsthereconstructed signalfrom t 1 to t 3 .Inthemeantime,thebuerreceivesthecompletespiketrain ofthewindow WIN 2 whichspansfrom t 2 to t 7 .Thealgorithmthenbeginsto performthereconstructionforthewindow WIN 2 ,andthebuerbeginstostore theincomingspiketrainforthethirdwindow WIN 3 .At t = t 10 thealgorithm nishesthereconstructionofthewindow WIN 2 andoutputsthereconstructed signalfrom t 3 to t 6 .Thealgorithmbeginstoreconstructthewindow WIN 3 and thebuerbeginstostorethespiketrainforthefourthwindow WIN 4 ,andsoon. Inthisway,thesignalcanbereconstructedinrealtimewithsomelatency. Wehavetwochoicesofthewindowdenition:constanttimewindowor constantnumberofspikeswindow.Iftheaverageringrate f avg ineachwindow issimilar,thedierencebetweenthesetwodenitionsaresmallandweusethe denitionoftheconstantnumberofspikeswindow.Assumethenumberofspikes ineachwindowis N ,andthenthetimeintervalforeachwindowis N=f avg .From

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67 Figure5{18: WindowingschemeoftheDSPreconstructionalgorithm Figure 5{18 wecanobtainthetimedelayofthereconstruction t delay = t 7 t 3 = 0 : 9 N f avg (5.62) Thecomputationtimeforthereconstructionofeachwindowis t comp = t 7 t 4 = 0 : 8 N=f avg .ThereforefromEquations 5.60 5.61 wecancalculatetherequired FLOPrateoftheDSPforthereconstructionusingGaussiankernel FLOPS Gaussian = NM 2 = 4 0 : 8 N=f avg = f avg M 2 3 : 2 (5.63) TherequiredFLOPrateoftheDSPforthereconstructionusingtheSinckernel FLOPS Sinc = N 3 = 3 0 : 8 N=f avg = f avg N 2 2 : 4 (5.64) Theselectionofthenumberofspikes N ineachwindowisatrade-oamong thesignaltonoiseratio(SNR),thetimedelay,andthecomputationcost.Larger N ,i.e.,longersignallengthusedforreconstruction,resultsinlargerSNRwith smallerSNRvariationaswediscussedinFigures 5{16 5{14 .Larger N increases thereconstructiondelayandworsensthereal-timeperformanceasshownin Equation 5.62 .Larger N increasestherequirementofthecomputationstorage, andalsoincreasestherequiredFLOPrateoftheDSPforreconstructionusingSinc

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68 Table5{1: PerformancecomparisonofthereconstructionusingtruncatedGaussian kernelandtruncatedSinckernel Kernels Gaussian Sinc SNR Figure 5{16 Figure 5{14 Timedelay 0 : 9 N=f avg 0 : 9 N=f avg Computationstorage(Bytes) 4 N M 4 N N RequiredFLOPrateoftheDSP(FLOPS) f avg M 2 = 3 : 2 f avg N 2 = 2 : 4 kernelasshowninEquation 5.64 howeverhasnoeectontherequiredFLOPrate oftheDSPforreconstructionusingGaussiankernelasshowninEquation 5.64 .In practicewechecktheFigures 5{16 5{14 tondtheminimum N whilestillhaving acceptableSNR.SincethereconstructionusingGaussiankernelislesssensitive tothesignallengththanthereconstructionusingSinckernel,wecanchoosea smaller N forthereconstructionusingGaussiankernel.Table 5{1 summarizesthe performancecomparisonofthereconstructionsusingthetruncatedGaussiankernel andthetruncatedSinckernel.Thedataareassumedtobestoredusingsingle oatingpointresolution(4Bytes). ItisofinteresttoputsomerealisticnumbersinTable 5{1 sothatwecan clearlyseetheperformanceimprovementforthereconstructionusingthetruncated Gaussiankernel.WeusethesamesimulationdataasthatusedinFigure 5{14 Theaverageringrate f avg =14kHz,theNyquistperiod T =1 = 3ms.Wewant tohavetheSNRofthereconstructionlargerthan100dB.Wecanestimatethat theminimumsignallengthforSinckernelis120T,orthenumberofspikesineach windowis N =120 Tf avg =560,toachieve101dBSNRfromFigure 5{14 .Wecan alsoestimatethattheminimumsignallengthforGaussiankernelis30T,orthe numberofspikesineachwindowis N =30 Tf avg =140,toachieve114dBSNR fromFigure 5{16 .ThebandwidthofthematrixCforGaussiankernelis M =15 fromFigure 5{15 .Thereforetheperformancecomparisonofthereconstructions usingthetruncatedGaussiankernelandthetruncatedSinckernelfor14kHz

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69 Table5{2: PerformancecomparisonofthereconstructionusingtruncatedGaussian kernelandtruncatedSinckernelfor14kHzaverageringratespiketrain Kernels Gaussian Sinc SNR(dB) 114 101 Numberofspikesperwindow 140 560 Matrixbandwidth 15 560 Timedelay(ms) 9 36 Computationstorage(Bytes) 8400 1254400 RequiredFLOPrateoftheDSP(FLOPS) 1 10 6 1 : 8 10 9 averageringrateisshowninTable 5{2 .TheGaussiankerneloutperformsthe Sinckernelineveryaspectinthetable. 5.5Discussion Inthischapterwediscussedeectsofsomenonidealitiesontheperformance ofthespikingneuronTB-ADC.Forthespikingneuronencodingcomponent weconsideredthefrequencyaliasingoftheinputsignal,leakyintegrationof theintegrator,thermalnoiseofthespikingneuron,andthesignaldependent referencevariationofthecomparator.FortheDSPreconstructioncomponent, weconsideredthetimingjitterofthetimequantizer,thekernelselectionandthe windowingoftheDSPalgorithm.Weestimatedthesignaltonoiseratiodueto somenonidealitiesinEquations 5.8 5.15 5.27 5.44 and 5.56 andsummarizedthem inTable 5{3 .ThereisanotherconstraintfortheADCparametersrelatedtothe averageringratewhichisshowninequationbelow: f avg = G m V dc CV ref (5.65) Theaverageringrate f avg isrelatedtothesignalbandwidthandisapredened numberduringADCdesign.Thisconstraintcomplicatesthechoicesof C V ref G m and V dc sinceincreasingoneofthemrequiresthecorrespondingchangesofthe others.TradeosduringADCimplementationsaremadebasedonTable 5{3 and Equation 5.65 together.

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70 Table5{3: Signaltonoiseratioduetodierentnoisesources Noisesource Signaltonoiseratio(SNR) Frequencyaliasing 8 2 V 2 dc f 2 a A 2 a f 2 avg Leakyintegration (6 RV 3 dc G 2 m ) 2 C 2 V 4 ref E [ k 2 ( t )] Thermalnoise C 2 V 2 ref f avg 2 kTG m Signaldependentreferencevariation V ref f u C 1 V d f avg Timingjitter 6 f 2 avg T 2 c Reducing f avg ishelpfultoreducetheeectoftheerrorsduetosignaldependentthresholdvariationofthecomparatorandthetimingjitterofthequantization clock,atthecostofperformancedegradationduetotheleakyintegrationandthe thermalnoiseofthetransconductanceamplier.Increasingthetransconductance amplieroutputresistance R ,thecapacitance C ,thereferencevoltage V ref ,the unitygainfrequencyofthecomparator f u aregenerallyhelpfultoreducetheeects duetodierenterrorsources,howeverthecostisthatmorepowerneedstobe consumedandmorechiplayoutareaisused.Decreasingthe G m ,orequivalently decreasingtheoutputreferrednoisecurrentpowerspectraldensity,canreduce theeectduetothermalnoiseofthetransconductanceamplier.Decreasing thetransconductance G m widensthelinearinputregionofthetransconductance amplierandreducesthenonlinearitydistortioniftheinputsignaliskeptthe same.However,itisnotthecaseheresincewiththeconstraintofconstant f avg we needtoapplyalargerinputsignal,andthereforethereductionofthenonlinear distortionisnotthatobvious.Smallercomparatoroutputvoltageswing V d ortime quantizerperiod T c canalsoobviouslyimprovetheADCperformance.

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CHAPTER6 IMPLEMENTATIONANDTESTOFANSPIKINGNEURONCHIP 6.1Introduction Inthischapterwepresentthecircuitimplementationofthespikingneuron TB-ADC.WeconsiderthepracticalissuesdiscussedinChapter 5 andmake sometradeosduringtheimplementation.Theperformanceoftheneuronchipis determinedusingthe4-parametersinewavettingmethodtestandthehistogram testmethod. 6.2CircuitImplementationoftheTransconductor AswementionedinChapter 5 thetransconductanceamplierinFigure 5{1 convertsthevoltagesignaltoacurrentsignal.Somenonidealitiesoftheamplier suchasthenonlinearity,theniteDCgainandthethermalnoiseaectthe signaltonoiseratiooftheADCandneedtobeconsideredduringtheADC implementation.Morespecically,weneedtowidenthelinearinputregion, increaseoutputresistanceandreducetheoutputreferrednoisecurrent. Figure 6{1 showstheimplementationofthetransconductanceamplier[36]. Theamplierusesthesourcedegenerationtechniquetowidenthelinearregionof thetransconductance G m .Thedegenerationresistorisrealizedusingtwocoupled PMOStransistorsM5andM6workinginthetrioderegion[37].Twonegative feedbacksformedbyM3andM7,M4andM8respectivelyimprovethelinearityby forcingthesourcesanddrainsofM5andM6tobevirtualground.Thedierential inputpairM1andM2providessomeattenuationsothatthelinearregionis furtherwidened.ADCosetcurrent I dc controlledbyaPMOStransistorM15is addedattheoutputtosettheaverageringrateoftheADC.Comparedtothe methodthatdirectlyappliesalargeDCosetvoltageattheinputs V i + and V i 71

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72 Figure6{1: Schematicofthetransconductanceamplier thismethodsavessomelinearregionfortheACvoltagesignal.Thecascodeoutput stageisusedtoincreasetheoutputresistance.Asarst-orderapproximation,the transconductance G m canbecalculatedas: G m =4 g m; 6 g m; 2 g m; 4 =4 6 s 2 I B 1 8 s n ( W=L ) 2 p ( W=L ) 4 =4( W=L ) 6 s 2 I B 1 n C ox ( W=L ) 2 ( W=L ) 8 ( W=L ) 4 (6.1) where g m isthetransconductanceofeachrespectivetransistor,( W=L )isthe transistorsizeratio, I B 1 isthebiascurrentthroughM9orM10, n istheelectron mobilityforNMOStransistors,and C ox istheoxidecapacitance.Itisalsoof interesttoestimatetheinputandoutputcommonmodevoltagerangessincewe

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73 needtomakesureallthetransistorsexceptM5andM6workinthesaturation region.Theinputcommonmodevoltagerangeis Inputrange =[ V dsat; 0 + V dsat; 2 + V TN ;V dd j V dsat; 4 jj V dsat; 8 j 2 j V TP j + V TN ](6.2) Theoutputcommonmodevoltagerangeis Outputrange =[ V dsat; 12 + V dsat; 14 ;V dd j V dsat; 4 jj V dsat; 8 jj V TP j ](6.3) where V dsat istheminimumdrainandsourcevoltagetokeepthetransistorin saturationregion, V TP isthethresholdvoltageforPMOStransistorsand V TN isthe thresholdvoltageforNMOStransistors.Duetothelevelshiftingprovidedbytwo bypassPMOStransistorsintheimplementationoftheneuroncircuit,theoutputof theamplierdoesnotneedtobepulledtogroundwhenthecapacitorisreset. Wemayalsoneedtoestimatetheoutputreferrednoisecurrentpowerspectral density(PSD) i 2 n;amp =4 kTG m sothatwecanknowhowtooptimizethenoise performancewithothertradeos.TheoutputreferrednoisecurrentPSDdueto M1,M2,M3andM4is: i 2 n;M 1 4 =4 kT 2 3 g m; 2 + g m; 4 g 2 m; 4 (4 g m; 6 ) 2 (6.4) TheoutputreferrednoisecurrentPSDduetoM5andM6: i 2 n;M 5 ; 6 =2 (2 i n;M 6 ) 2 =2 4 4 kTg m; 6 (6.5) TheoutputreferrednoisecurrentPSDduetoM9,M10,M13,M14andM15are simply4 kT 2 3 g m where g m isthetransconductanceofeachtransistor.Allother transistorsinFigure 6{1 contributenegligiblenoisepowerandthusareneglectedin thenoiseanalysis.Thereforethetotaloutputreferrednoisecurrentis: i 2 n;amp =4 kT ((8+ 64( g m; 2 + g m; 4 ) g m; 6 g 2 m; 4 ) g m; 6 + 4 3 g m; 10 + 4 3 g m; 14 + 2 3 g m; 15 )(6.6)

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74 Fortransistorsworkinginthesquare-lawabove-thresholdregion,thereisa tradeobetweenthetransconductance g m andthesaturationvoltage V dsat which followstheequation g m I B = 2 V dsat where I B isthedraincurrentintheequilibrium state.ItishelpfultoimprovetheADCnoiseperformancebyincreasing g m; 4 or reducinganyother g m inEquation 6.6 .However,reducingthese g m sindicates increasing V dsat andreducestheavailableoutputvoltageswingrangeasshownin Equation 6.3 .Reducingtheoutputvoltageswingrangewillreducethereference voltage V ref ofthecomparator,andthendegradetheADCperformance.Reducing g m; 2 increases V dsat; 2 andreducestheinputvoltageswingrangeasshownin Equation 6.2 .Reducing g m; 6 orincreasing g m; 4 decreasesthetransconductance G m oftheamplierasshowninEquation 6.1 .Tomaintainthesameaveragering rate f avg ,theinputvoltagesignalshouldbecorrespondinglyincreased.However theinputvoltagesignalshouldnotbelargerthan2 p 2 V dsat; 2 ,otherwiseoneofthe dierentialpairtransistorsM1andM2willenterthecutoregion. 6.3CircuitImplementationoftheIFNeuron Thespikingneuronencoderperformstheintegrate-and-reencodingoperation.Thecurrentisintegratedonthecapacitor.Iftheresultingcapacitorvoltage isabovethereferencevoltage,theoutputofthecomparatorgoeshigh,which indicatestheendofoneintegrationperiod.Thecapacitorisresetandaftersome timetheoutputofthecomparatorgoeslow,whichindicatesthebeginningof anotherintegrationperiod.AsmentionedinChapter 5 theADCperformanceis heavilydependentontheaccuracyoftherisingandthefallingtransitiontimings ofthespikes.Techniquesneedtobeemployedtoimprovetheaccuracy.Thepower consumptionisalsoanotherperformanceconcern.Besidesthebiascurrentconsumption,thepowerconsumptionduringswitchingtransitionsalsoneedstobe reduced.

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75 (a)(b) Figure6{2: Latcheswithapositivefeedback.(a)Capacitivefeedbacklatch.(b) Currentfeedbacklatch Thecircuitimplementationsofspikingneuronhasbeenthoroughlyinvestigatedintheliterature[11,38,39].Meadproposedaneuronformedbytwoinverters withacapacitivefeedbacklatch.ThecapacitivefeedbacklatchisshowninFigure 6{2 (a).Positivefeedbacksaretriggeredforbothrisingandfallingswitching transitions,andthereforethesignaldependentdelayandrefractoryperiodare reduced,whichisdesirableforADCapplications.However,thethresholdofthe neuronisonlydeterminedbytheVLSIprocessparametersandcannotbevaried afterfabrication.Alsoiftheinputsignalvariesslowlyduringtheswitching,both thePMOSandNMOSoftheinvertersareturnedonforalongtimeandalarge short-circuitpowerisconsumed.Vanschaikintroduceda5-Transistoropamp intotheneuronimplementationsothatthereferencevoltageisvariable[38].A positivefeedbackandadelayednegativefeedbackareutilizedtogeneratethepulse. However,thedelayunitisimplementedusingacurrentstarvedinverterwithacapacitiveload,andalargerefractoryperiodisintroducedandthereforethisneuron isnotsuitableforADCapplications.

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76 Figure6{3: Schematicoftheneuroncircuit Boaheninventedanewtechniquecalledthecurrentfeedbacklatch,which isshowninFigure 6{2 (b),toreducetheshort-circuitpowerconsumption[39]. ThecurrentthroughtheinverterformedbyM1andM2ismirroredtothecurrentthroughM5,whichformsapositivefeedback.When V in isapproachingthe thresholdvoltageofM1,thepositivefeedbackistriggeredandtheexponentially increasingcurrentthroughM5pulls V in upcloseto V dd quickly,andcorrespondinglythe V out ispulleddownclosetogroundquickly.Thepositivefeedbackis terminatedwhenthereisnocurrentthroughtheinverter.Thepositivefeedback canalsobetriggeredwhenwereset V in ,thereforethepull-downcurrentthrough theresettransistorM6mustbelargerthanthepull-upcurrentthroughM5sothat acompleteresetcanbeachieved. Figure 6{3 showsanspikingneuronimplementationusingcurrentfeedback latches.Theneuronimplementationconsistsofanopamp(M0-5)withacurrent feedbacklatch(M6-10),atimedelayunit(M15-21)usingcurrentfeedbacklatch, andsomeauxiliarycircuitryforresetorbypass(M22-26).Theneuronimplementationworksasfollows.Assumeinitiallyboththeoutput V out andthevoltage V mem acrossthecapacitor C mem arelow.M22ison,M26andM23iso,thecurrent

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77 I in fromtheprevioustransconductanceamplierbeginstochargethecapacitor C 1 andtheresultedvoltage V mem beginstorise.M1isalsoonandtheopamp (M0-5)worksasacomparator.When V mem risesabovethereferencevoltage V ref theoutputoftheopamprisesabovethethresholdofthecurrentfeedbacklatch (M6-11),thepositivefeedbackistriggeredand V 1 goeslowquicklyandtheoutput V out goeshighquickly.M22iso,M26ison,andtheinputcurrentisbypassed throughM26.M23isonandthecapacitor C mem isdischargedandthevoltage V mem ispulledtoground.SinceM1iso,theopampisdisabled, V out stayshigh andisnotaectedbythechangeof V mem .Meanwhile,since V 1 islow,M13ison, asmallcurrent I b 2 beginstochargeasmallcapacitor C d .Aftersometimedelay, thevoltageacross C d ishighenoughtotriggerthefollowingcurrentfeedbacklatch (M15-21), V 2 goesup,theopampoutputisreset, V 1 goesupandthus V out goes lowquickly.Thetimedelayisapproximatelyequaltothepulsewidthandisdeterminedby C d V TN I b 2 .Meanwhile,M23andM26areo,M22andM1areon,theopamp isenabledandthecurrentbeginstochargethecapacitor C mem again.Alsosince V 1 ishigh,thelargecurrentthroughM14quicklypullsdownthevoltageacrossthe capacitor C d V 2 islow,M10iso,andthecircuitisbacktotheinitialstate. Transistors(M22,M24-26)servesfortwopurposes.Onepurposeistobypass theinputcurrentwhen V out ishigh,otherwisetheoutputstageoftheprevious transconductanceamplierwouldenterthetrioderegionandthenexperiencelarge disturbancewhenbeingbacktochargethecapacitorafter V mem isreset.Theother purposeistoactasalevelshifterwhenthecapacitorvoltage V mem isresetto zero.Withthesetransistorstheoutputvoltageoftheprevioustransconductance amplieronlyneedstobepulleddownto j V TP j' 0 : 8 V ,whilewithoutthese transistorstheoutputvoltageoftheprevioustransconductanceamplierhastobe pulleddowntozeroandthecorrespondingdesigniscomplicated.

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78 Figure6{4: Layoutoftheneuronchip Wecanseethatpositivefeedbacksaretriggeredforbothrisingandfalling switchingtransitionssothatsignaldependentdelayorrefractoryperiodare reduced.Sincecurrentfeedbacklatchesareemployedtheshort-circuitpower consumptionoftheinvertersisminimized.Sincethedelaytimeisveryshort,the powerconsumptiondueto I b 2 isnegligible.Thepowerconsumptionofthisneuron implementationismainlythebiascurrent I b 1 consumptionoftheopamp.The thresholdvoltageofthisneuroncanbevariedfromgroundto V dd V tp 2 V dsat andthusitissuitablefortherealizationofthethresholdadaptation. 6.4Neuronchiplayout TheneuronchipwasimplementedintheAMI0.5umCMOStechnology processandpackagedinastandard40-pinDIP40throughMOSIS.Thetotal chipareaoccupiedbytheintegratorandtheneuronencoderis18000( m ) 2 .The

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79 Table6{1: Thetransistorsizesforthetransconductanceamplier Transistors W/L( m ) M 0 ; 11 ; 12 18 = 1 : 8 M 1 ; 2 1 : 5 = 45 M 3 ; 4 2 : 4 = 0 : 6 M 5 ; 6 4 : 8 = 6 : 6 M 7 ; 8 1 : 8 = 1 : 8 M 9 ; 10 ; 13 15 4 : 5 = 1 : 8 M 16 9 = 1 : 8 Table6{2: ThetransistorsizesfortheIFneuron Transistors W/L( m ) M 0 7 : 2 = 1 : 8 M 1 ; 11 ; 13 ; 19 ; 21 23 ; 25 ; 26 1.5/0.6 M 2 ; 3 9/1.8 M 4 ; 5 ; 12 1.8/1.8 M 6 9 ; 15 18 3/0.6 M 10 6/0.6 M 14 4.5/0.6 M 20 ; 24 1.5/1.5 capacitorisimplementedusingpoly1andpoly2layers.Chipareacanbereduced ifusingMOScapacitorswithhighercapacitancedensity.Thechiplayoutisshown inFigure 6{4 .Thedigitalcircuitryandtheanalogcircuitryareseparatedbyguard ringssothattheanalogcircuitryisnotaectedmuchbythelargetransientnoise producedbythedigitalcircuitry[40].Thepowersuppliesfortheanalogandthe digitalcircuitsarealsoseparated.Thetransistorsizesforthetransconductance amplierandtheIFneuronareillustratedinTable 6{1 6{2 ,respectively. 6.5NeuronchipTestResults Forthetransconductanceamplier,boththebiascurrents I b 0 and I b 1 are2 A,theDCosetcurrent I dc =1 A,thecommonmodeinputvoltageis2 : 5V. Fortheneuronencoder,thecapacitor C 1 =10pF,thecapacitor C d =100fF,the referencevoltage V ref is2 : 5V,thebiascurrent I b 1 oftheopampis2 A,thebias current I b 2 ofthedelayunitis0 : 05 A.

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80 Theinputvoltagesinewaveis x ( t )=2 : 5 V + A sin(2 ft )andisprovided throughafunctiongenerator.Becausethefunctiongeneratorweusedcanonly providesinewaveswithamplitudeslargerthan10mV,anattenuatorformedby tworesistors(50k,2k)isemployedforsignalswithamplitudelessthan10mV. Aswillbeseen,thethermalnoiseintroducedbythesetworesistorsisnegligible anddoesnotdegradetheADCperformance.Alogicanalyzerisusedtocapture transitiontimingsofthechipoutput.Theclockperiodofthelogicanalyzeris5ns. ThesignalisreconstructedinMatlabusingthealgorithmdiscussedinChapter 4 Weapplythesinewavewithdierentamplitudesandfromthereconstructed signalwecanestimatethetransconductanceofthetransconductanceamplier is G m =6 : 2 1 .Themeasuredpulsewidthis1 : 5 sandisconsistentwith C d V TN =I b 2 =1 : 4 sconsideringsomeparasiticcapacitance.Themeasuredaverage ringrateis f avg =58kHz.ThentheinputreferredDCosetvoltageis V dc = C 1 V ref f avg G m =234 mV (6.7) ThisDCosetvoltageconsistsoftheamplierbuilt-inosetvoltageandtheinput referredDCosetvoltageduetotheDCcurrent I dc addedattheoutput.ThisDC osetvoltageisalsocalledthefullscaleamplitude dBFS inlaterdiscussions. Thecurrentconsumptionofthechipexcludingpadsandbuersisaround9 A,andthereforethepowerconsumptionfora5Vpowersupplyis9 5=45 W. Sincetheactualtotalbiascurrentis I bias;tot = I b 0 ;amp +2 I b 1 ;amp + I dc;amp + I b 1 ;neuron = 1 : 941+1 : 966+1 : 966+1 : 001+1 : 992=8 : 866 A,theresulted0 : 134 Aisdueto thedynamiccurrentconsumptionofthedigitalcircuitry. Wehaveimplementedtwoteststocharacterizethechipperformancebased ontheIEEEstandard1241forADCtest[41].Oneisthe4-parametersinewave ttingtestandtheotheristhehistogramtest.

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81 Figure6{5: PlotoftheSNRvs.sinewaveamplitudeofthespikingneuronchip 6.5.14-parameterSineWaveFittingTest The4-parametersinewavettingmethodisatime-domaintestmethodto determinetheADCperformance.Themethodistoestimatetheinputsignalfrom theADCoutputsamplesbyndingthebest-ttingsinewave[41]: x ( t )= A cos( !t + )+ C (6.8) Wendthebest-ttingsinewavebyusingonlinematlabcode[42]whichisrealized basedontheIEEE1241standard.Thenoiseanddistortionaredenedasthe dierencebetweentheADCoutputsamplesandtheestimatedsignalsamples.The signalpowerisdenedasthepowerofthesinewavewithoutDCosetbasedon theIEEE1241standard.Thenwecancalculatethesignaltonoiseratio(SNR). TheresolutionoftheADC,i.e.,theeectivenumberofbits(ENOB),iscalculated viaEquation 2.1 .Fig 6{5 showsthemeasuredSNRvs.theamplitudeofthesine wavewith1 k Hzfrequency,wherethesignalbandwidthoftheconverteris10kHz

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82 Figure6{6: PlotoftheSNRvs.sinewavefrequencyofthespikingneuronchip ( s =2 10 k =20 k rad/sec),and0dBFSreferstoasinewavewith0 : 234 Vamplitude.Asthesinewaveamplitudeincreases,theSNRincreaseswitha slopeof1dB/1dBtoreachthepeakof59dBataround 5dBFS,i.e.,0 : 13V amplitude,andthenquicklydropsto0dB.TheSNRdropisduetotheincreased nonlinearitiescausedbythelargeramplitudesignalinputandthefrequency aliasingcausedwhenthemaximumintervalbetweenadjacenttransitiontimings growslargerthantheNyquistperiod = s .Weconcludethatthechipcanachieve 59dBSNR,orequivalently9 : 5bitresolution.Inordertoshowtheperformance isconsistentfordierentfrequencies,wealsoprovideaplotoftheSNRvs.the frequencyofthesinewavewitha 5 : 8dBFSamplitudeinFig 6{6 .TheSNRis above57dBforfrequenciesupto10kHzbandwidth. 6.5.2SineWaveHistogramTest Sinewavehistogramtestingisalsoperformedtomeasurethedierential nonlinearity(DNL)andintegralnonlinearity(INL).Thistestcomputesthecode

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83 Figure6{7: PlotsoftheDNLandINLfromthesinewavehistogramtestofthe spikingneuronchip Table6{3: Neuronchipperformancemetric Corediearea(( m ) 2 ) 18000 Powerconsumption( W) 45;10.5(w/otransamp) Signalbandwidth(kHz) 10 Eectiveresolution(Bit) 10 SNR(dB) 59 densityofthereconstructedsignal,andthencomparesittothecodedensityofan idealsinewavetoobtainthenonlinearities[43,44].Theinputsignaltothechip isasinewavewitha1kHzfrequencyanda 5 : 8dBFSamplitude.Thesampling frequencyofthereconstructedsignalisnotharmonicallyrelatedtothesinewave frequencyasrequiredbytheIEEEstandard1241.Withtheassumptionof10bit resolution,thenonlinearitiesarecalculatedandplottedinFig 6{7 .Wecansee bothDNLandINLarelessthan1leastsignicantbit(LSB),whichveriesthat thechipachievesan10-bitresolution.Theneuronchipperformancemetricis summarizedinTable 6{3 .

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84 6.6Discussion Inthischapterwehavediscussedadetailedcircuitimplementationofthe spikingneuronencoder.Thetestresultsshowthattheneuronchipcanachieve 59dBsignaltonoiseratio(SNR).Thenoiseisthetotaleectofallkindsoferror sourcesasdiscussedinChapter 5 .Itisofinteresttoverifytheeectoftheseerror sourcesontheperformanceoftheneuronchipandtoseeifitisconsistentwith thechipmeasurement.WeshouldbeawarethatthedenitionoftheSNRinthis chapterisnotexactlythesameasthatinChapter 5 .Neitherthesignalpower northenoisepowerarecalculatedwiththeDCosetusing4-parametersinewave ttingtest.However,inChapter 5 theDCcomponentisconsideredincalculations ofboththesignalpowerandthenoisepower. Weonlyconsidertheerrorsourcessuchastheleakyintegrationofthe integrator,thermalnoiseofthespikingneuron,thesignaldependentreference variationofthecomparator,andthetimingjitterofthetimequantizer.Without additionaldeclarations,theparametersoftheADCare: C =10pF, V ref =2 : 5V, G m =6 : 2u 1 R =80M,andthesignalbandwidth s =2 10000rad/s.The inputsignalis V ( t )= V dc + A sin(2 ft )withaDCcomponent V dc =0 : 234Vanda sinewavewithanamplitude A =0 : 13Vandafrequency f =1kHz. Thepoweroftherstderivationoftheinputsignal V ( t )is E [ V 2 ( t )]= 0 : 5 A 2 (2 f ) 2 .FromFigure 5{4 wecanobtaintheSNRduetotheleakyintegration oftheintegratoris76 : 5dBfromEquation 5.15 ,or78 : 5dBfromtheMatlab simulation.SinceEquation 5.15 suggeststheSNRisalsoinverselyproportional tothesinewavefrequency.Theworstcasehereiswhenthesignalfrequency equalstheADCbandwidth,i.e.,10kHz.Therefore,theworstcasefortheleaky integrationisthat SNR leaky =78 : 5 20=58 : 5dBfromEquation 5.15 WecanusethenoiseanalysistoolsinCadencetomeasuretheoutputreferred noisecurrentPSDofthetransconductanceamplier4 kTG m =1 : 2 10 24 A 2 =Hz .

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85 Inthechipmeasurementsetupanattenuatorformedbytworesistors( R 1 =50 k, R 2 =2k)isemployedforsignalswithamplitudelessthan10mV.We cancalculatetheadditionaloutputreferrednoisecurrentPSDduetothesetwo resistorsas4 kT ( R 1 jj R 2 ) G 2 m =1 : 22 10 27 A 2 =Hz ,whichisnegligibleanddoes notdegradetheADCperformance.FromFigure 5{8 wecanobtainthattheSNR duetothethermalnoiseis79dBfromEquation 5.27 ,or78dBfromtheMatlab simulation. IntheimplementationofthespikingneuroninSection 6.3 whentheoutputof the5-transistoropampreachesthethreshold( V TN )ofthecurrentfeedbacklatch, thepositivefeedbackistriggeredandittakesveryshorttimefortheoutputof theopamptoreachthepositivepowersupply.Thereforewemaytreatthedigital logicstate V d asthelatchthreshold,i.e.,thecomparatorresolvestothelogicstate whentheoutputoftheopampreaches V TN 0 : 7V.Simulationshavebeenrunin CadencetomeasuretheDCgainoftheopamp A c =109,theunitygainfrequency oftheopamp f u =62MHz,andthecorrespondingtimeconstant c =280ns.From Figure 5{11 wecanobtainthattheSNRduetothesignaldependentreference variationofthecomparatoris57dBfromEquation 5.44 ,or58dBfromtheMatlab simulation. Theclockperiodusedinthelogicanalyzeris T c =5ns.Theaveragering rateoftheADCis f avg =58kHz.FromEquation 5.56 wecanobtainthattheSNR duetothetimingjitteris78 : 5dB. Thechipmeasurementsareconsistentwiththeequationsandthesimulations discussedinChapter 5 .Frompreviousdiscussionswecanseethattheperformance limitationofthisneuronchipimplementationismainlyduetothesignaldependent referencevariationofthecomparator.Therefore,higherlevelsoftheothererror sourcescanbetoleratedduringtheADCdesignandthepowerconsumptionofthe transconductanceampliermaybefurtherreduced.

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CHAPTER7 IMPLEMENTATIONANDTESTOFANASYNCHRONOUSDELTASIGMA CONVERTER 7.1Introduction Inthischapterwerstintroduceatypicalasynchronousdeltasigmaconverter architectureandthenpresenttheDSPreconstructionalgorithm.Twocircuit implementationsoftheconverterareexplainedindetailandthecorrespondingchip performanceisdeterminedusingthe4-parametersinewavettingmethodtestand thehistogramtestmethod. 7.2AsynchronousDeltaSigmaConverterArchitecture Generallyspeaking,thespikingneuronTB-ADCpreviouslydiscussedcanonly receivepositivesignalinput,otherwisetheinterspikeintervalmaybetoolargeand thebandwidthconstraintisthusviolated.Theasynchronousdelta-sigmaconverter isanotherintegrate-and-retypeofTB-ADCwhichcanacceptpositiveornegative signalinput[6,45,46].Figure 7{1 showsthearchitectureofatypicalasynchronous Figure7{1: Architectureoftheasynchronousdeltasigmaconverter deltasigmaconverterbasedontheschemeproposedbyLazarandToth[7].This 86

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87 architecturedoesnotuseaclocktosampletheanalogsignal,andnoquantization operationisinvolvedduringthedataconversion.Thedierencebetweenthe inputsignal V ( t )andthefedbackanalogvaluecorrespondingtotheSchmitt triggeroutput y ( t i )iscontinuouslyintegrated.TheSchmitttriggercontrolsthe samplingoperationwithitshighreferencevoltage V rh andlowreferencevoltage V rl .TheSchmitttriggeroutput y ( t i )switchesfromlowtohighiftheintegrator outputrisesabovethehighreferencevoltage V rh ,switchesfromhightolowif theintegratoroutputdropsbelowthelowreferencevoltage V rl ,andotherwise remainsunchanged.Iftherearenononidealitiesduringthedataconversion,the informationintheanalogsignalislosslesslyencodedinthetransitiontimings t i oftheSchmitttriggeroutput.Thisisamarkeddierencefromsynchronousdelta sigmaconverterswherelosslesssamplingcanonlyoccurasymptoticallyinthe limitastheoversamplingratioincreasestoinnity.Theasynchronousconverter describedhererequiresnooversamplinginprinciple,howeverasmallamountof oversamplingincreasesthesignaltonoiseratio(SNR)inpractice. 7.3SignalReconstructionAlgorithm TheSchmitttriggeroutputisdiscreteinamplitudeandcontinuousintime andnecessitatestimequantizationtoobtaindigitaloutput.Moreover,sincemost currentdigitalsystemscanonlyprocessuniformlysampleddata,thenonuniform natureoftheSchmitttriggeroutputrequiresanothersignalprocessingblockto converttoauniformlysampledsequenceforsubsequentdigitalprocessing.The overallADCperformanceisnotonlydependentontheaccuracyoftheencoding circuit,butalsoontheeciencyofthesignalreconstructionblock.Directlow passlteringcannotachievesatisfactoryperformanceunlesstheaverageringrate isextremelyhigh[6],whichnecessarilyrequiresmorepowerconsumptiononthe converter.WecanusetheWLPKmethodintroducedinSection 4.3 toreconstruct thesignal.Similartothesignalreconstructionfromspikingneuronmodels,we

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88 mayneedtorstndtheencodingequationoftheasynchronousdeltasigma converter,andthensubstituteEquation 4.3 intotheencodingequationtocalculate theweightsandthereforethereconstructedsignal. Letusassumetheintegratorequationis G m C R dt ,the1-bitDACconvertslogic highandlogiclowto a and a .Withoutlossofgenerality,wealsoassume t 0 ;t 2 ;::: aretherisingedgetimingsfortheoutputswitchfromlowtohighand t 1 ;t 3 ;::: are thefallingedgetimingsfortheoutputswitchfromhightolow.Forthetimeperiod from t 0 to t 1 ,theSchmitttriggeroutputishigh,the1-bitDACoutputis a ,and theintegratoroutputdecreasesfrom V rh to V rl .Wecanobtain G m C Z t 1 t 0 ( V ( t ) a ) dt = V rl V rh (7.1) Similarlyforthetimeperiodfrom t 1 to t 2 ,wecanobtain G m C Z t 2 t 1 ( V ( t )+ a ) dt = V rh V rl (7.2) CombiningEquation 7.1 and 7.2 ,andaftersomesimplicationwecanobtainthe integralof V ( t )overtwoadjacentrisingedgetimings t 0 and t 2 : Z t 2 t 0 V ( t ) dt = a (2 t 1 t 2 t 0 )(7.3) Followingsimilarprocedureswecanobtaintheintegralof V ( t )overtwoadjacent fallingedgetimings t 1 and t 3 : Z t 3 t 1 V ( t ) dt = a (2 t 2 t 3 t 1 )(7.4) CombiningEquation 7.3 7.4 ,theencodingoperationoftheconvertercanbe summarizedas Z t i +2 t i V ( t ) dt =( 1) i a (2 t i +1 t i +2 t i )(7.5)

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89 WecansubstituteEquation 4.3 intoEquation 7.5 ,andobtainasystemoflinear equations X j w j c ij =( 1) i a (2 t i +1 t i +2 t i )(7.6) wherecoecients c ij = Z t i +2 t i sin( s ( t s j )) s ( t s j ) dt (7.7) areconstantsdependingonlyonthetransitiontimings t i ,and s j =( t j + t j +2 ) = 2. FinallywesolveEquation 7.6 toobtaintheweights w j ,andthenuseEquation 4.3 toreconstructthesignal x ( t ).FromEquation 7.6 wecanseethatthereconstructed signalisonlydependentontheDACoutput a andtheSchmitttriggeroutput transitiontimings t i andisimmunetoprocessvariationorotherdeviceparameters suchas G m C ,and( V rh V rl ). ThesucientconditiontomeetthebandwidthrequirementinEquation 4.3 is thatthemaximumintervalbetweenadjacenttimings s j and s j +1 ,orequivalently betweenadjacenttransitiontimings t i and t i +1 ,islessthan = s .Thusfrom Equation 7.1 7.2 wecanobtaintheconditionforallsignalswhichrequiresthatthe magnitudeofsignal V ( t )isboundedby j V ( t ) j a C ( V rh V rl ) s G m (7.8) Sincetheinformationisencodedinthetransitiontimings,theintervalsbetween adjacenttimingsaresignaldependent,andthereforethebandwidthrequirement canevenbesatisedforsomesignalswithmagnitudelargerthanthebound denedinEquation 7.8 Althoughmathematicallytheinformationislosslesslyencodedinthetransition timings,inpracticenonidealitiesintroducesomeerrorintothetimingsanddegrade theconverterperformance.Theeectsofthesenonidealitiesshouldbesimilarto

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90 thosediscussedinthecaseofspikingneuronTB-ADCinChapter 5 ,andtherefore thecorrespondinganalysisisneglected. 7.4CircuitImplementation1 7.4.1Integrator Theintegratorisimplementedusingatransconductanceamplier G m ,which isshowninSection 6.2 ,withacapacitiveload C .Thedeterminationofthe transconductance G m andsomeotherparameterscanbefoundinSection 6.2 .The inputvoltagesignalandthefeedbackvoltagesignalfromthe1-bitDACareapplied tothepositiveterminal V i + andthenegativeterminal V i oftheinputdierential pairoftheamplier,respectively. 7.4.2SchmittTriggerand1-bitDAC ThecircuitimplementationsoftheSchmitttriggerandthe1-bitDACare showninFigure 7{2 .TheSchmitttriggerisverysimpleanddoesnotrequireany resistors.Theseconddierentialinputpair(M0-3)isintroducedtoatransconductanceamplier(M4-13)toformthepositivefeedbackthatprovideshysteresis.The inverter(M12-13)isneededtoincreasetheloopgainandtoproducethedigital output.Itturnsout I b 1 hastobelargerthan I b 2 forproperoperation.TheSchmitt triggerworksasfollows.Assuminginitiallytheoutput V out islowandtheinput V in ismuchlowerthanthereference V ref ,transistorsM1andM5areoandtransistors M2andM4areon.Current I b 1 owsthroughM4andthecurrent I b 2 throughM2 andthus I b 1 + I b 2 owsthroughM6whilenocurrentowsthroughtransistorsM1, M5andM7,andtheoutput V out iskeptlow.If V in decreasesitwillnotchangethe currentowandthusnotaectthisstate.If V in increases,currentbeginstoswitch fromM4toM5,andthuscurrentthroughM6increasesandcurrentthroughM7 decreases.OncethecurrentsthroughM6andM7arebothequalto( I b 1 + I b 2 ) = 2, anincreasein V in willcausemorecurrenttoowthroughM7thanM6,andthus causetheoutput V out toincrease.Meanwhiletheincreaseof V out willalsoswitch

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91 Figure7{2: CircuitimplementationoftheSchmitttrigger(M0-13)andthe1-bit DAC(M14-15) morecurrentfromM2toM1,whichfurthercausesmorecurrenttoowthrough M7thanM6.Apositivefeedbackmechanismisactivatedand V out isexponentially increasedfromlowtohigh.Similaranalysiscanbeappliedtothecaseofswitching V out fromhightolow.Itturnsoutthatthehighandlowreferencevoltagesare theinputvoltageswhichcausethecurrentthroughM4toequal( I b 1 I b 2 ) = 2and ( I b 1 + I b 2 ) = 2respectively.Forabove-thresholdsquare-lawoperationwecanobtain thereferencevoltageswing v rh v rl as V rh V rl = 2( p I b 1 + I b 2 p I b 1 I b 2 ) p C ox ( W=L ) 4 (7.9) whichcanbetunedviabiascurrentsafterfabrication.Wecanalsoderivethe transconductanceoftheSchmitttriggerattheswitchingpointsas g m = 2 1 =g m 4 +1 =g m 5 = 2 1 p ( I b 1 I b 2 ) C ox ( W=L ) 4 + 1 p ( I b 1 + I b 2 ) C ox ( W=L ) 4

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92 = 2 p I 2 b 1 I 2 b 2 p I b 1 + I b 2 + p I b 1 I b 2 p C ox ( W=L ) 4 (7.10) TheSchmitttriggerisacriticalcomponenttoperformthesamplingoperationof theconverter.Alargerreferencevoltageswing V rh V rl isusuallypreferableas wediscussedinChapter 5 .Largertransconductance,orequivalentlylargerunity gainbandwidthwithconstantloadcapacitance,isalsopreferablebecausethe regenerationspeedofthepositivefeedbackisfaster[34,47]andthustheoutput requireslessdelaytoreachlogicalstates.Actuallyitisthevarianceofthedelay thataectsthereconstructionperformancesincethemeanofthedelaycanbe cancelledinthealgorithm.Thevarianceofthedelayarisesfromitsdependence ontheslewrateoftheinputvoltageoftheSchmitttrigger.Itisclearfrom Equation 7.9 7.10 thatatradeomustbemadebetweenthereferencevoltage swingandthetransconductancetochoosepropertransistor W=L ratioforgiven biascurrents. The1-bitDACisjustasimpleinverterwithsourcesconnectedtoappropriate analogvoltages V CM + a and V CM a V CM isthecommonmodevoltageand a is halfofthefullscaleanalogvoltage,whicharedeterminedbytheinputlinearregion oftheintegrator. 7.4.3ChipLayout TheasynchronousdeltasigmaconverterchipwasimplementedintheAMI0.5 umCMOStechnologyprocessandpackagedinastandard40-pinDIP40through MOSIS.ThetotalchipareaoccupiedbytheintegratorandtheSchmitttrigger is27600( m ) 2 .ThechiplayoutisshowninFigure 7{3 .Thedigitalcircuitryand theanalogcircuitryareseparatedbyguardringstoreducetheeectofthelarge transientnoiseproducedbythedigitalcircuitry[40].Thepowersuppliesforthe analogandthedigitalcircuitsarealsoseparated.

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93 Figure7{3: Layoutoftheasynchronousdeltasigmaconverterchip1 7.4.4ChipTestResults Fortheintegrator,thecapacitanceis10pF,andthebiascurrents I b 0 and I b 1 are5 Aand4 Arespectively,thecommonmodeinputvoltageis2 : 6Vand thecommonmodeoutputvoltageis1 : 8V.FortheSchmitttrigger,thereference voltage V ref is1 : 8V,thebiascurrents I b 1 and I b 2 are36 Aand26 A,andthe corresponding( v rh v rl )=0 : 5V.Forthe1-bitDAC,logichighandlogiclow correspondto2 : 7Vand2 : 3V,whichmeans a =0 : 2V.Theinputvoltagesine waveis x ( t )=2 : 5 V + A sin(2 ft ).Alogicanalyzerisusedtocapturetransition timingsofthechipoutput,andthenthesignalisreconstructedinMatlabtoa uniformlysampledsequenceusingthealgorithmdiscussedinSection 7.3 .Wehave implementedtwoteststocharacterizethechipperformancebasedontheIEEE standard1241forADCtest[41].

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94 Figure7{4: PlotoftheSNRvs.sinewaveamplitudeoftheasynchronousdelta sigmaconverterchip1(thesinewavefrequencyis1kHz,theconvertersignal bandwidthis6kHz,and0dBFSrefersto0 : 2Vfullscaleamplitude) 4-parametersinewavettingtest. Figure 7{4 showsthemeasured SNRvs.theamplitudeofthesinewavewith1kHzfrequency,wherethesignal bandwidthoftheconverteris6kHz( s =12000 rad/sec),and0dBFSrefers toasinewavewith0 : 2Vamplitude.Asthesinewaveamplitudeincreases,the SNRincreaseswithaslopeof1dB/1dBtoreachthepeakof51dBataround 2 : 5dBFS,andthenquicklydropsto0dB.TheSNRdropisduetotheincreased nonlinearitiescausedbythelargeramplitudesignalinputandthefrequency aliasingcausedwhenthemaximumintervalbetweenadjacenttransitiontimings growslargerthantheNyquistperiod = s .Weconcludethatthechipcanachieve 51dBSNR(morethan8-bitresolution).AsmentionedinSection 7.3 ,theaverage converterringrateissignaldependentanddecreasesfrom40kHzto20kHzas theamplitudeincreases.Thepowerconsumptionofthechipexcludingpadsand buersisaround715uW.Inordertoshowthattheperformanceisconsistentfor

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95 dierentfrequencies,wealsoprovideaplotoftheSNRvs.thefrequencyofthe sinewavewitha 2 : 5dBFSamplitudeinFigure 7{5 .TheSNRisabove50dBfor frequenciesupto6kHzbandwidth. Figure7{5: PlotoftheSNRvs.sinewavefrequencyoftheasynchronousdelta sigmaconverterchip1(thesinewaveamplitudeis-2.5dBFS) Sinewavehistogramtest. Sinewavehistogramtestingisalsoperformed tomeasurethedierentialnonlinearity(DNL)andintegralnonlinearity(INL). Thistestcomputesthecodedensityofthereconstructedsignal,andthencompares ittothecodedensityofanidealsinewavetoobtainthenonlinearities[43].The inputsignaltothechipisasinewavewitha1kHzfrequencyanda 2 : 5dBFS amplitude.Thesamplingfrequencyofthereconstructedsignalisnotharmonically relatedtothesinewavefrequencyasrequiredbytheIEEEstandard1241.With theassumptionof8bitresolution,thenonlinearitiesarecalculatedandplottedin Figure 7{6 .WecanseebothDNLandINLarelessthan1LSB,whichveriesthat thechipachievesan8-bitresolution.Theasynchronousdeltasigmaconverterchip 1performancemetricissummarizedinTable 7{1 .

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96 Figure7{6: PlotsoftheDNLandINLfromthesinewavehistogramtestofthe asynchronousdeltasigmaconverterchip1 Table7{1: Theasynchronousdeltasigmaconverterchip1performancemetric Corediearea(( m ) 2 ) 27600 Powerconsumption( W) 715 Signalbandwidth(kHz) 6 Eectiveresolution(Bit) 8 SNR(dB) 51 7.5CircuitImplementation2 ThecircuitimplementationinSection 7.4 hastwoproblems.Oneproblemis thattheusableinputlinearregionfortheACsignalisreducedduetotheaddition ofthelargeDCoutputvoltageofthe1-bitDACatthetransconductanceamplier input,furtherdegradingtheADCperformance.Theotherproblemisthelarge powerconsumptionoftheSchmitttriggerduetothediculttradeobetweenthe speedandthereferencevoltageswing.Thereforeotherconverterarchitecturesand Schmitttriggerimplementationsneedtobeinvestigated.

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97 7.5.1Integratorand1-bitDAC Ifthe1-bitDACconvertsadigitalsignaltoananalogcurrentsignal,we maydirectlyaddthiscurrentattheoutputofthetransconductanceamplier, andthereforetheinputlinearregionissavedonlyfortheACsignal.Figure 7{7 showstheimplementationoftheintegratorandthe1-bitDAC.Theintegrator isimplementedusingatransconductanceamplier G m ,whichwasdiscussedin Section 6.2 ,withacapacitiveload C .TheimplementationoftheDACisbased ontheideaofcurrentswitchingusingadierentialpair(M15-18).Ifthedigital signalishigh,i.e., V f + = V dd V f = Gnd ,theDCcurrent I dc issubtractedfrom theoutputoftheamplier,otherwisetheDCcurrentisaddedtotheoutputofthe amplier.Assumethetransconductanceoftheamplieris G m ,thisisequivalentto applyingapositiveornegativeDCosetvoltagewithanabsolutevalue a = I dc G m ThereforethesignalreconstructionalgorithminSection 7.3 canbeusedwithout anychange. 7.5.2SchmittTrigger Thelargerreferencevoltageswing V rh V rl oftheSchmitttriggerishelpfulto improvetheADCperformance.Thereferencevoltageswingcanbeoptimizedifit isnotdependentonthespeedorpowerconsumptionoftheSchmitttrigger. TwocomparatorsandaRSlatchcanbeusedtoimplementamultivibrator whichshowssomehysteresis[48].TheblockdiagramoftheSchmitttriggerusing thesimilarideaisshowninFigure 7{8 .Thereferencevoltageswingcanbesetto anyvalueaslongasitmeetstherequirementofthecommonmodeinputrangeof thetwoopamps.Twoinverterswithacurrentfeedbacklatchareemployedtoboost theswitchingtransitiontoreducethesignaldependentthresholdvariation.AnRS latchisusedtoguaranteetheproperfunctionoftheSchmitttrigger.Table 7{2 showsthechangingoftheoutput,i.e.,theQterminaloftheRSlatch,whenthe input V in risesfrombelow V rl toabove V rh andthendropsbelow V rl .Theoutput

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98 Figure7{7: Integratorimplementationwith1-bitDAC oftheRSlatchremainsunchangedwhenbothitsinputs R and S areswitchedto high.Itiscleartoseethattheoutputswitchesfromlowtohighwhentheinput risestocrossesthehighreferencevoltage V rh ,andswitchesfromhightolowwhen theinputdropstocrossesthelowreferencevoltage V rl .Thedelayunitisusedto generatethesignal Rst toresetthetwoinverterswiththecurrentfeedbacklatch. Table7{2: InputandoutputtransitiontableoftheSchmitttrigger( V in risesfrom below V rl toabove V rh ,andthendropsbelow V rl ) Region R S Q Q V in V rh 0 1 0 1 V rl
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99 Figure7{8: BlockdiagramoftheSchmitttrigger ThecircuitimplementationofOpamp1andOpamp2are5-transistor transampswithNMOSandPMOSinputdierentialpairs,respectively.Thereforethehighreferencevoltage V rh canbesetashighas V dd whilethelowreference voltage V rl canbesetaslowas Gnd .However,theactualreferencevoltagesare limitedbytheoutputvoltageswingrangeofthepreviousintegratorstageasshown inEquation 6.3 .Sinceeachtimeonlyonetransampneedstoperformthecomparison,thebiascurrentoftheothertransampisdisabledtosavepowerconsumption. Thetopinverterwithcurrentfeedbacklatch(Inv-cf1)isexactlythesameasthat inFigure 6{2 (b).Thebottominverterwithcurrentfeedbacklatch(Inv-cf2)isthe sameasthatinFigure 6{2 (b)ifallPMOSandNMOStransistorsareswitchedwith oneother.TheRSlatchisimplementedusingtwocoupledNANDgates.Thedelay unitisimplementedusingthecapacitivefeedbacklatchasshowninFigure 7{9 Biasvoltages V pu and V pd areusedtocontrolthecurrentthroughthecurrent starvedinverterandthereforethetimedelayoftheunit.Sincethecapacitanceof thefeedbackcapacitor C f isverysmall,thedelaytimeisveryshortandtherefore thepowerconsumedbythedelayunitisnegligible.

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100 Figure7{9: Delayunitoftheschmidtttrigger 7.5.3ChipLayout TheasynchronousdeltasigmaconverterchipwasimplementedintheAMI0.5 umCMOStechnologyprocessandpackagedinastandard40-pinDIP40through MOSIS.ThetotalchipareaoccupiedbytheintegratorandtheSchmitttriggeris 20500( m ) 2 .ThechiplayoutisshowninFigure 7{10 .Thedigitalcircuitryand theanalogcircuitryareseparatedbyguardringssothattheanalogcircuitryisnot aectedmuchbythelargetransientnoiseproducedbythedigitalcircuitry[40]. Thepowersuppliesfortheanalogandthedigitalcircuitsarealsoseparated. 7.5.4ChipTestResults Fortheintegrator,boththebiascurrents I b 0 and I b 1 are2 A,thecommon modeinputvoltageis2 : 5V,andthecapacitor C =10pF.The1-bitDACoutput current I dc =2 A.FortheSchmitttrigger,thehighreferencevoltage V rh is3 : 5 V,thelowreferencevoltage V rl is0 : 5V,thebiascurrentofthetransampis2 A, boththepull-downandthepull-upcurrentsofthedelayunitare10 A,andthe feedbackcapacitor C f =20fF. Theinputvoltagesinewaveis x ( t )=2 : 5 V + A sin(2 ft )andisprovided throughafunctiongenerator.Becausethefunctiongeneratorweusedcanonly

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101 Figure7{10: Layoutoftheasynchronousdeltasigmaconverterchip2

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102 Figure7{11: PlotoftheSNRvs.sinewaveamplitudeoftheasynchronousdelta sigmaconverterchip2 providesinewaveswithamplitudeslargerthan10mV,anattenuatorformedby tworesistors(50 k ,2 k )isemployedforsignalswithamplitudelessthan10mV. Alogicanalyzerisusedtocapturetransitiontimingsofthechipoutput.Theclock periodofthelogicanalyzeris5ns.ThesignalisreconstructedinMatlabusingthe algorithmdiscussedinSection 7.3 Weapplythesinewavewithdierentamplitudesandfromthereconstructed signalwecanestimatethetransconductanceofthetransconductanceamplier is G m =6 : 2 1 .Theoutputcurrentofthe1-bitDACcanbereferredtothe voltageatthetransconductanceamplierinputsas a = I dc G m =0 : 32V.The measuredaverageringrateis f avg =33kHz.Thecurrentconsumptionofthechip excludingpadsandbuersisaround10 : 4 A,andthereforethepowerconsumption fora5Vpowersupplyis10 : 4 5=52 W.Sincethetotalbiascurrentis I bias;tot = I b 0 ;amp +2 I b 1 ;amp + I dc;amp + I b 1 ;neuron =10 A,theremaining0 : 4 Aisdue tothedynamiccurrentconsumptionofthedigitalcircuitry.

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103 Wehaveimplementedtwoteststocharacterizethechipperformancebased ontheIEEEstandard1241forADCtest[41].Oneisthe4-parametersinewave ttingtestandtheotheristhehistogramtest. Figure7{12: PlotoftheSNRvs.sinewavefrequencyoftheasynchronousdelta sigmaconverterchip2 4-parametersinewavettingtest. The4-parametersinewavetting methodwasexplainedinChapter 6 .Figure 7{11 showsthemeasuredSNRvs. theamplitudeofthesinewavewith1 k Hzfrequency,wherethesignalbandwidth oftheconverteris10kHz( s =2 10 k =20 k rad/sec),and0dBFSrefers toasinewavewith0 : 32Vamplitude.Asthesinewaveamplitudeincreases,the SNRincreaseswithaslopeof1dB/1dBtoreachthepeakof51dBataround 6 : 5 dBFS,i.e.,150mVamplitude,andthenquicklydropsto0dB.TheSNRdrop isduetotheincreasednonlinearitiescausedbythelargeramplitudesignalinput andthefrequencyaliasingcausedwhenthemaximumintervalbetweenadjacent transitiontimingsgrowslargerthantheNyquistperiod = s .Weconcludethat thechipcanachieve51dBSNR,orequivalently8bitresolution.Inorderto

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104 Figure7{13: PlotoftheDNLandINLfromthesinewavehistogramtestofthe asynchronousdeltasigmaconverterchip2 showtheperformanceisconsistentfordierentfrequencies,wealsoprovideaplot oftheSNRvs.thefrequencyofthesinewavewitha 6 : 5dBFSamplitudein Figure 7{12 .TheSNRisabove50dBforfrequenciesupto10kHzbandwidth. Sinewavehistogramtest. Sinewavehistogramtestingisalsoperformed tomeasurethedierentialnonlinearity(DNL)andintegralnonlinearity(INL). Thistestcomputesthecodedensityofthereconstructedsignal,andthencompares ittothecodedensityofanidealsinewavetoobtainthenonlinearities[43].The inputsignaltothechipisasinewavewitha1kHzfrequencyanda 6 : 5dBFS amplitude.Thesamplingfrequencyofthereconstructedsignalisnotharmonically relatedtothesinewavefrequencyasrequiredbytheIEEEstandard1241.With theassumptionof8bitresolution,thenonlinearitiesarecalculatedandplottedin Figure 7{13 .WecanseebothDNLandINLarelessthan1LSB,whichveries thatthechipachievesan8-bitresolution.Theasynchronousdeltasigmaconverter chip2performancemetricissummarizedinTable 7{3 .

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105 Table7{3: Theasynchronousdeltasigmaconverterchip2performancemetric Corediearea(( m ) 2 ) 20500 Powerconsumption( W) 52 Signalbandwidth(kHz) 10 Eectiveresolution(Bit) 8 SNR(dB) 51

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CHAPTER8 TIME-BASEDADCVARIATIONS 8.1Introduction Chapters 3 4 ,and 6 havedescribedatime-basedADCimplementationbased ontheintegrate-and-reneuronmodel.TheIFneuronisonlysuitableforpositive signalinput,otherwisethespiketimingscanviolatethebandwidthconstraints. Someclockedneuronmodelsbesidestheasynchronousdelta-sigmaconverter canaddressthisproblem.TherearealsoothertypesofTB-ADCswhicharenot basedontheintegrate-and-remechanism.InthischapteralloftheseTB-ADC variationswillbediscussed. 8.2ClockedNeuronModels TheIFneuronmodelpresentedinChapter 3 usuallyhasaconstantreference voltage.Iftheinputsignal x ( t )isverysmall,theneuronmaytaketoomuch timetore.Sincethebandwidthrequirementisdeterminedbythemaximum interspikeinterval,theconstantreferencevoltagemethodlimitsthemaximum signalfrequencytobeencodedwithoutcausingaliasingeects.Therearegenerally twomethodstoaddressthisbandwidthlimitationproblem.Onemethodisto addaknownDCcomponenttotheoriginalsignal x ( t )whichforcestheneuron toreatsomespecicrateevenwhen x ( t )=0,and x ( t )caneasilyretrieved bysubtractingthatDCcomponentfromthereconstructedsignal.Thecircuit implementationbasedonthismethodwasshowninChapter 6 .Theothermethod istovarythereferencevoltagebasedonglobalorlocalclocks[49],andthe reconstructioncanbeachievedbyndingtheeectivereferencevoltagesfor eachspiketime.Itturnsoutthesetwomethodsareinfactequivalentforlinear 106

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107 Figure8{1: Referencevoltagewaveform,capacitorvoltagesandspikesforclocked neuronmodels. variationof V ref inthenoise-freecase.Theclockedneuronmodelswearegoingto discussarebasedonthelattermethod. 8.2.1GloballyClockedNeuron Thereferencevoltage V ref usedbygloballyclockedneuronsisaperiodic varyingwaveformcontrolledbyaglobalclock.Thereferencevoltagebeginswith someinitialvalue V 0 anddecreasestozeroinaclockperiod T ref .Thevariation canbelinearasshowninFigure 8{1 ornonlinear.Theintegrationofanysmall positiveinputsignalcancrossthereferencevoltagewaveformandreonceinone clockperiod.Ontheotherhand,theresetofthecapacitorvoltagehappensonly duringtheresetoftheclockandthereforetheneuroncannotremorethanonce inoneclockperiod.Inthiswaytheringrateoftheneuronisequaltotheinverse oftheglobalclockperiod T ref .Figure 8{1 showsthe V ref waveformandthespike generationfordierentinputcurrentsinoneclockperiod.Theintegrationofthe neuronbeginsattheresetofeachclockperiod,i.e., t =0,andendswhenthe capacitorvoltage V mem crossesthe V ref waveformandthenaspikeistriggered. Inthegure,theslopeof V mem isproportionaltotheinputcurrent,anditcan beclearlyseenthatanypositivecurrentinputcantriggeronespikeinoneclock periodandlargerinputs( I 1 >I 2 >I 3 )triggerearlierspikes( t 1
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108 Figure8{2: Reconstructionofthegloballyclockedneuron.(a)SpiketrainandVref waveform.(b)Originalandreconstructedsignals TheWLPKmethodpresentedinChapter 4 canalsobeappliedtotheglobally clockedneuronifappropriate t ib t ie ,and areused. t ib denotesthebeginningof the i thintegrationperiodwhichisinfactthebeginningofthe i thclockperiod. Thus t ib =( i 1) T ref where T ref istheclockperiod. t ie istheendingofthe i th integrationperiod,i.e.,therisingedgeofthe i thspike.Thethreshold isdened as CV ref ( t ie ),where V ref ( t ie )iscalculatedusingthe V ref waveformfunction,an exampleofwhichisshowninEquation 8.1 forthewaveforminFigure 8{1 V ref ( t ie )= V 0 (1 t ie t ib T ref )(8.1) Figure 8{2 showsthereconstructionofthegloballyclockedneuron.Theresulting SNRis96 : 7dB.Theparametersofthesimulationarelistedbelow:theinput currentis x ( t )=100(1+sin(2 600 t ))nA,thesignalbandwidth s =2 1000 rad/sec,thecapacitor C =5pF,theinitialreferencevoltage V 0 =5V,theclock

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109 period T ref =0 : 125ms,andthesignallengthprocessedis20mswithonly2ms lengthofwhichshowninFigure 8{2 forclarity. 8.2.2LocallyClockedNeuron Thereferencevoltage V ref usedbylocallyclockedneuronsisverysimilar totheoneshowninFigure 8{1 forgloballyclockedneurons,exceptthatthe resetofthewaveformiscontrolledbythespikeinsteadoftheglobalclock.The integrationoftheneuronbeginsatthefallingedgeofthepreviousspike,i.e., t =0 inFigure 8{1 ,andendswhenthecapacitorvoltage V mem crossesthe V ref waveform, andthenaspikeistriggeredand V ref isresettoitsinitialvalue V 0 .Theintegration ofanysmallpositiveinputsignalcancrossthereferencevoltagewaveformandre onceintheperiod T ref ,whichlimitstheminimumringrateastheinverseofthe clockperiod T ref .Ontheotherhand,sincetheintegrationbeginsjustafterthe previousspike,verylargeinputsignalcangenerateveryhighringratespiketrain, andthenthereisnolimitationonthemaximumringrate. TheWLPKmethodpresentedinChapter 4 canalsobeappliedtothelocally clockedneuronifappropriate t ib t ie ,and areused.Allotherparametersare sameasthoseingloballyclockedneuronsexcept t ib hereisthefallingedgeofthe ( i 1)thspike. Figure 8{3 showsthereconstructionofthelocallyclockedneuron.The resultingSNRis87 : 6dB.Theparametersofthesimulationarelistedbelow:the inputcurrentis x ( t )=100(1+sin(2 600 t ))nA,thesignalbandwidth s =2 1000 rad/s,thecapacitor C =5pF,theinitialreferencevoltage V 0 =5V,theclock period T ref =0 : 25ms,andthesignallengthprocessedis20mswithonly2ms lengthofwhichshowninFigure 8{3 forclarity.Wenowinvestigatetherelationship betweenvaryingthereferencevoltageandaddingaDCcomponentto x ( t ).We

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110 Figure8{3: Reconstructionofthelocallyclockedneuron.(a)SpiketrainandVref waveform.(b)Originalandreconstructedsignals knowtheencodingprocessoftheintegrate-and-reneuronisdescribedby 1 C Z t ie t i b x ( t ) dt = V ref ( t ie )(8.2) SubstitutingEquation 8.1 intoEquation 8.2 ,weobtain 1 C Z t ie t ib ( x ( t )+ CV 0 T ref ) dt = V 0 (8.3) Equation 8.3 showsthattheeectoflinearlyvaryingthereferencevoltageis mathematicallyequivalenttoaddingaDCcomponent CV 0 T ref totheoriginalsignal x ( t )whilexingtheconstantreferencevoltageat V 0 8.3Level-ModeTime-basedADCs TheTB-ADCspreviouslydiscussedsuchasneuronsandasynchronousdeltasigmaconvertersareinvolvedwiththeintegrationoftheoriginalsignalduring dataconversion.Thereareothertypesofsocalledlevel-modeTB-ADCsin

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111 whichacomparatordirectlycomparestheoriginalsignalwiththereferencesto implementthesamplingoperation.Theyincludeslevel-crossingsamplingTBADCandsawtoothwavecrossingsamplingTB-ADCbasedondierentreference waveforms.ThesamplesgeneratedbytheencodersoftheseTB-ADCsarepairsof ( t i V ref ( t i )),where V ref ( t i )isthereferencevalueatthesamplingtime t i .Thesignal reconstructionfromlevelmodeTB-ADCsaresimilartothereconstructionmethods showninpreviousTB-ADCs. Intheidealcasethevalueofsignal x ( t )atsamplingtime t i isequaltothe referencevalueatthattime,andweobtain x ( t i )= V ref ( t i ) ; 8 i (8.4) Theoriginalsignal x ( t )canbeexpressedas x ( t )= h ( t ) X j w j ( t t j ) = X j w j h ( t t j ) (8.5) TheonlydierencebetweenEquation 4.3 and 8.5 isthat s j inEquation 4.3 is changedto t j inEquation 8.5 .Inthiswaythelaterformulatedmatrix C haslarger elementvaluesatitsmaindiagonalwhichimprovesthereconstructioneciency. Substitutingequation 8.5 intoequation 8.4 ,weobtain V ref ( t i )= X j w j h ( t i t j ) = X j w j c ij (8.6) where c ij areconstantsthatcanbenumericallycomputedwith: c ij = h ( t i t j )(8.7)

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112 Figure8{4: ReconstructionofthelevelcrossingsamplingTB-ADC.(a)Spiketrain andVrefwaveform.(b)Originalandreconstructedsignals WecanuseEquation 8.6 tocalculatetheweightsandthenuseEquation 8.5 to calculate x ( t )towithinmachineprecision. 8.3.1LevelCrossingSamplingTB-ADC ThereferencesofthelevelcrossingsamplingTB-ADCareusuallyequally spacedlevels.Oncethesignal x ( t )crossesareferencelevel,asampleisgenerated andboththetimingandthereferencearerecorded[50].Figure 8{4 showsthe reconstructionoftheLevelcrossingsamplingTB-ADC.TheresultedSNRis 100dB.Theparametersofthesimulationarelistedbelow:theinputvoltagesignal is x ( t )=2(1 : 05+sin(2 600 t ))V,thesignalbandwidth s =2 1000rad/s,thestep ofthereferencelevelsare0 : 6V,andthesignallengthprocessedis20mswithonly 2mslengthofwhichshowninFigure 8{4 forclarity. Onesimplestlevel-crossingsamplingmethodisthezero-crossingsampling, whichissuitableforzeromeansignals.Oncethesignalcrossesthezerolevel

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113 Figure8{5: ReconstructionofthesawtoothwavecrossingsamplingTB-ADC.(a) SpiketrainandVrefwaveform.(b)Originalandreconstructedsignals thesampletimeisrecorded.InordertousetheWLPKreconstructionmethod, anonzeroamplitudesamplemustbeprovidedtogetherwiththezero-crossing timings.Althoughthemaximumtimeintervalbetweensamplesispossiblelarger thantheNyquistperiod,inpracticethereconstructionperformanceisacceptableif thesignalhaszeromeanandtheaveragesamplingrateisenoughhigh[51]. 8.3.2SawtoothWaveCrossingSamplingTB-ADC ThereferenceofthesawtoothwavecrossingsamplingTB-ADCisaperiodic variedsawtoothwaveformwhichisliketheoneinFigure 8{1 .Oncethesignal x ( t ) crossesthesawtoothwaveform,asampleisgenerated.Thiskindofmodulationis alsocalledpulsepositionmodulation(PPM)[52].Theeectivereferenceatthe samplingtimecanbecalculatedfromthesawtoothwaveformEquation. V ref ( t i )= V 0 (1 t i ( i 1) T ref T ref )(8.8)

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114 Figure 8{5 showsthereconstructionofthesawtoothwavecrossingsampling TB-ADC.TheresultedSNRis97 : 2dB.Theparametersofthesimulationare listedbelow:theinputvoltagesignalis x ( t )=2(1 : 05+sin(2 600 t ))V,thesignal bandwidth s =2 1000rad/s,theinitialreferencevoltage V 0 =5V,theclock period T ref =0 : 25ms,andthesignallengthprocessedis20mswithonly2mslength ofwhichshowninFigure 8{5 forclarity. 8.4Discussion InthischapterwediscussedsomeTB-ADCvariantsincludingclockedneurons andlevel-modeTB-ADCs.Theclockedneuronsalleviatetherequirementonthe inputsignalatthecostofmorecomplicatedencodingcircuitry.Thepreciseclock needstobeeithergeneratedonchiporappliedochip,whichincreasesthepower consumptionoftheencoder.Alsothewaveformofthereferencevoltageshould bekeptaccurate,otherwisethereferencevoltagevariationwilldegradetheADC performance.Thelevel-modeTB-ADCsdonotneedon-chipcapacitorsandcan savesomechiparea.Thecostisthatthereisnoanti-aliasingeectandtheADCis pronetohighfrequencyinterferences.Astothelevel-crossingTB-ADC,thedigital circuitryintheencodersideiscomplicatedsincethereferencevoltagesneedtobe adjustedupordownaccordingtheinputsignal.Astothesawtoothwavecrossing TB-ADC,morecomplicatedcircuitryisneededtogeneratetheaccuratesawtooth waveform.

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CHAPTER9 CONCLUSIONS Thisdissertationdescribesthetheory,implementationandtestingoftimebasedADCs.Thetime-basedADCemploysacompletelydierentarchitecture fromtheconventionalADCandquantizestimeatpredenedamplitudeintervals. Thisnovelarchitecturehaspromiseforlowpowerconsumptionbecauseofthe extremesimplicityoftherequiredanalogcircuitryandnorequirementforhigh oversampling. Theweightedlow-passkernel(WLPK)methodwediscussedcanachievetheoreticallyperfectsignalreconstructionperformance,andcanbegenerallyapplied tosolvemanykindsofnonuniformsamplingproblems.TheGaussiankernelwe proposedgreatlyreducesthecomputationcostofthesignalreconstruction.Since neithertheSinckernelnortheGaussiankernelisanalyticallyintegrable,higher computationcostisneededtoestimatethekernelintegrationwithinsomespecicaccuracyforintegrate-and-rebasedTB-ADCs.Thereforeitisworthwhile toinvestigateanalyticallyintegrablekernelswhichhaveacceptabletime-domain fast-decayingandfrequency-domainlow-passproperties.AmorescienticapplicationoftheWLPKmethodisthereconstructionofcontinuouswaveformsfrom actualbiologicalneurons.Inmanyapplications,suchasbrainmachineinterfaces, spiketrainsarebinnedtocreateacontinuouswaveformsuitableforprocessing. Thereconstructionmethoddescribedherecreateamoreaccurateinterpretationof thecontinuousinputintothesoma.Ofcourse,theaccuracyofthisinterpretation dependscriticallyonboththevalidityoftheassumedmodelandtheaccuracyof theneuronparameters. 115

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116 WeextensivelystudiedthefundamentalperformancelimitationduetononidealitiesforthespikingneuronTB-ADC,whichmaybeextendedtootherTB-ADC implementations.Testresultsofseveralprototypechipsimplementedina0 : 5um CMOStechnologyprocesssuggestthathighresolutionandlowpowerconsumption TB-ADCsareachievableinpractice.Onefundamentalperformancelimitationis relatedtotheunitygainfrequencyoftheopamp.SincemoreadvancedCMOS technologiescansupporthigherspeedcircuitry,itisworthwhiletoimplementTBADCsusingthesetechnologies(suchas0 : 13um)anddemonstratetheperformance improvement.However,betterdesigntechniquesneedtobeutilizedtoovercome dicultiesduetothelowersupplyvoltage.

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118 [13] W.GerstnerandW.Kistler, SpikingNeuronModels:SingleNeurons, Populations,Plasticity ,CambridgeUniversityPress,NewYork,2002. [14] M.Chacron,K.Pakdaman,andA.Longtin,\Interspikeintervalcorrelations, mempry,adaptation,andrefractorinessinaleakyintegrate-and-remodel withthresholdfatigue," NeuralComputation ,vol.14,no.2,pp.253-278, February2003. [15] E.Bayly,\Spectralanalysisofpulsefrequencymodulationinthenervous system," IEEETransactionsonBiomedicalEngineering ,vol.BME15,no.4, pp.257-365,October1968. [16] M.Nakao,M.Norimatsu,Y.Mizutani,andM.Yamamoto,\Spectral distortionpropertiesoftheintegralpulsefrequencymodulationmodel," IEEE TransactionsonBiomedicalEngineering ,vol.44,no.5,pp.419-426,May1997. [17] R.DunandA.Schaeer,\Aclassofnonharmonicfourierseries," TransactionsoftheAmericanMathematicalSociety ,vol.72,pp.341-366,1952. [18] H.FeichtingerandK.Grochenig,\Theoryandpracticeofirregularsampling," in Wavelets:MathematicsandApplications ,J.BenedettoandM.Frazier, Eds.,BocaRaton,FL,1994,pp.305-363. [19] D.WeiandJ.Harris,\Signalreconstructionfromspikingneuronmodels," in Proceedingsofthe2004InternationalSymposiumonCircuitsandSystems Vancouver,May2004,vol.5,pp.353-356. [20] T.Strohmer,\Irregularsampling,framesandpseudoinverse,"MSthesis, UniversityofVienna,Vienna,Austria,1993. [21] J.Thorson,\Gaussianeliminationonabandedmatrix," http://sepwww.stanford.edu/oldreports/sep20/20-11.pdf,December2004. [22] G.Stewart, IntroductiontoMatrixComputations ,AcademicPress,NewYork, 1973. [23] Y.Noguchi,H.Hataoka,S.Sugimoto,H.Kobayashi,andM.Kobayashi, \Integralfunctionmethod-anewanalyzingmethodforheartratevariability," in Proceedingsofthe9thAnnualInternationalConferenceoftheIEEE EngineeringinMedicineandBiologySociety ,Boston,November1987,vol.4, pp.1056-1057. [24] Y.Noguchi,T.Hamada,T.Kawamura,F.Matsumoto,andS.Sugimoto, \Highlyaccuratedemodulationmethodofanipfmmodelwithanabsolute refractoryperiod,"in Proceedingsofthe20thAnnualInternationalConference oftheIEEEEngineeringinMedicineandBiologySociety ,HongKong, October1998,vol.1,pp.345-348.

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119 [25] S.Mitra, DigitalSignalProcessing:AComputer-BasedApproach ,McGrawHill,NewYork,2001. [26] B.Razavi, DesignofAnalogCMOSIntegratedCircuits ,McGraw-Hill,New York,2000. [27] P.Gray,P.Hurst,S.Lewis,andR.Meyer, AnalysisandDesignofAnalog IntegratedCircuits ,JohnWileyandSons,NewYork,2001. [28] R.Sarpeskhar,T.Delbruck,andC.Mead,\Whitenoiseinmostransistors andresistors," IEEECircuitsandDevicesMagazine ,vol.9,pp.23-29, November1993. [29] F.Robinson, NoiseandFluctuationsinElectronicDevicesandCircuits ClarendonPress,Oxford,1974. [30] H.Tian,B.Fowler,andA.Gamal,\Analysisoftemporalnoiseincmos photodiodeactivepixelsensor," IEEEJournalofSolid-StateCircuits ,vol.36, no.1,pp.92-101,January2001. [31] MatlabStatisticsToolbox6.0Documents ,TheMathWorks,Inc.,Natick,MA. [32] A.Papoulis, SignalAnalysis ,McGraw-Hill,NewYork,1977. [33] T.Sakurai,\OptimizationofCMOSarbiterandsynchronizercircuitswith submicrometermosfets," IEEEJournalofSolid-StateCircuits ,vol.23,no.4, pp.901-906,August1988. [34] F.RosenbergerandT.Chaney,\Flip-opresolvingtimetestcircuit," IEEE JournalofSolid-StateCircuits ,vol.SC17,no.4,pp.731-738,August1982. [35] A.Papoulis, MatrixComputations ,TheJohnsHopskinsUniversityPress, Baltimore,Maryland,1996. [36] A.Lopez-Mietin,A.Carlosena,andJ.Ramirez-Angulo,\Versatilecmosand bicmoslineartransconductorcircuits,"August1999,vol.2,pp.1024-1027. [37] B.StefanellyandA.Kaiser,\Cmostriodetransconductorwithhighdynanmic range," ElectronicsLetters ,vol.26,no.13,pp.880-881,1990. [38] A.vanSchaik,\Buildingblocksforelectronicspikingneuralnetworks," Neural Networks ,vol.14,no.67,pp.617-628,July-September2001. [39] E.Culurciello,R.Etienne-Cummings,andK.Boahen,\Abiomorphicdigital imagesensor," IEEEJournalofSolid-StateCircuits ,vol.38,no.2,pp. 281-294,February2003. [40] A.HastingsandR.Hastings, TheArtofAnalogLayout ,PrenticeHall,Upper SaddleRiver,NewJersey,2000.

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120 [41] IEEEStandardforTerminologyandTestMethodsforAnalog-to-Digital Converters ,IEEE,NewYork,December2000. [42] J.Markus,\ADCtestdataevaluationprogramformatlab," http://www.mit.bme.hu/projects/adctest,May2004. [43] J.Doernberg,H.Lee,andD.Hodges,\Full-speedtestingofA/Dconverters," IEEEJournalofSolid-StateCircuits ,vol.SC19,no.6,pp.820-827,December 1984. [44] \Histogramtestingdeterminesdnlandinlerrors,"http://www.maximic.com/appnotes.cfm/appnote number/2085,December2004. [45] C.KikkertandD.Miller,\Asynchronousdeltasigmamodulation,"in ProceedingsofIREE ,April1975,vol.36,pp.83-88. [46] J.DasandP.Sharma,\Someasynchronouspulsemodulationsystems," ElectronicsLetters ,vol.3,no.6,pp.284-286,June1967. [47] T.KacprzakandA.Albicki,\AnalysisofmetastableoperationinRSCMOS ip-ops," IEEEJournalofSolid-StateCircuits ,vol.SC22,no.1,pp.57-64, February1987. [48] A.SedraandK.Smith, MicroelectronicCircuits ,OxfordUniversityPress, NewYork,1997. [49] X.Guo, ATime-BasedAsynchronousReadoutCMOSImageSensor ,Ph.D. dissertation,UniversityofFlorida,Gainesville,FL,2002. [50] F.Marvasti, UniedApproachtoZero-CrossingandNonuniformSamplingfor SingleandMultidimensionalSignalsandSystems ,NonUniform,1987. [51] S.Jaard,\Adensitycriterionforframesofcomplexexponentials," Michigan MathematicalJournal ,vol.38,no.3,pp.339-348,1991. [52] H.Black, ModulationTheory ,D.VanNostrandCompanyInc.,NewYork, 1953.

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BIOGRAPHICALSKETCH DazhiWeiwasborninLaiyang,Shandong,China.HereceivedhisBachelor ofSciencedegreesinautomationcontrolandtechnologicaleconomicsfromthe ShanghaiJiaoTongUniversity,Shanghai,China,in1995.Healsoreceivedhis MasterofSciencedegreeinelectricalandcomputerengineeringfromtheUniversity ofFloridain2003.From1995to2001hewasahardwareengineerintheSixth ResearchInstitute(Electronics)ofMII,Beijing,China.CurrentlyheisaPh.D. candidateintheComputationalNeuroEngineeringLaboratoryintheElectrical andComputerEngineeringDepartmentattheUniversityofFlorida.Hispresent researchinterestsareintheareasofbiologicallyinspiredsignalprocessingand mixed-signalintegratedcircuitdesign. 121


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TIME-BASED ANALOG-TO-DIGITAL CONVERTERS


By
DAZHI WEl















A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


2005

































Copyright 2005

by
Dazhi Wei
















To my family.
















ACKNOWLEDGMENTS

First, I wish to express my sincere gratitude to my advisor, Dr. .John Harris,

for the things he taught me over the years, his support and encouragement.

Without his patience and guidance this work would have been impossible. I

would like to thank Dr. .Josii C. Principe, Dr. Robert 31. Fox, and Dr. Timothy

Davis for being on my coninittee and their frequent helpful advice. I would also

like to thank Dr. .Josii A.B. Fortes for his support in the bio-nano computing

project. I also appreciate the helpful discussions front people in the Computational

Neuroengineering Lah.

I am deeply grateful to my parents, brother and sister for their support and

love. Thanks are also extended to my dear son, Frank, for his coming to this world

and making this work more meaningful. Last, I would like to thank my darling

wife, Xiaoi- Ilr Z1! In:- for her love and belief in me.


















TABLE OF CONTENTS
page

ACK(NOWLEDGMENTS ......... .. iv

LIST OF TABLES ......... .. .. viii

LIST OF FIGURES ......... .. .. ix

ABSTRACT ...... ...... .......... xii

ChAPTER

1 INTRODUJCTION . ...... ... .. 1

1.1 Background ......... . 1
1.2 Motivation ......... .. 2
1.3 Dissertation Structure . ...... .. :3




2 TIME-BASED ANALOG-TO-DIGITAL CONVERTERS .. .. .. .. 5

2.1 Introduction ......... ... 5
2.2 Signal Representation .. .. .. . . .. 5
2.3 Conventional Analog-to-digital Converters (C-ADCs) .. .. .. 6
2.4 Time-based Analog-to-digital Converters (TB-ADCs) .. .. .. 8
2.5 Comparison Between the C-ADC and the TB-ADC .. .. .. 9




:3 SPIK(ING NEURON SIGNAL REPRESENTATION .. . 12

:3.1 Introduction ......... ... 12
:3.2 Biological Neuron ....... .... 12
:3.3 Integrate-and-fire Neuron Models .... .. .. 14
:3.3.1 Integrate-and-fire Neuron Model .. .. ... .. 14
:3.3.2 Leaky Integrate-and-fire Neuron with Refractory Period
Model ........ .... ..... .. ..... 16
:3.:3.3 Integfrate-and-fire Neuron with Threshold Adaptation .. 17
:3.4 Summary ......... . 18











4 RECONSTRUCTION FROM SPIK(ING NEURON MODELS .. .. 19

4. 1 Introduction .... .... .. .. 19
4.2 Direct Low-pass Filtering Reconstruction Method .. .. .. .. 19
4.3 WLPK( Reconstruction Method ..... ... .. 20
4.3.1 Reconstruction front the IF neuron ... .. .. 21
4.3.2 Reconstruction from LIF neuron with refractory period 24
4.3.3 Reconstruction front the IF neuron with threshold adapta-
tion. ............ .... .... 24
4.4 Discussion of Other Reconstruction Methods .. .. .. .. 25




5 PRACTICAL ISSITES RELATED TO SPIK(ING NEURON TB-ADC
IMPLEMENTATION ......... ... 26

5.1 Introduction ....... . .. 26
5.2 Inmplenientation of Spiking Neuron TB-ADC .. .. .. .. 26
5.3 Practical Issues Related to Signal Encoding in Spiking Neuron
Models. ............ .. ..... 27
5.3.1 Fr-equency Aliasing of the Input Signal .. .. .. 27
5.3.2 Leaky Integration of the Integrator ... .. .. :32
5.:3.3 Thermal Noise of the Spiking Neuron .. .. .. :39
5.3.4 Signal Dependent Reference Variation of the Coniparator .46
5.4 Practical Issues Related to Reconstruction front Spiking Neuron
Models. ............ .. .... 55
5.4.1 Timing Jitter of the Time Quantizer .. .. .. .. .. 56
5.4.2 K~ernel Selection of the DSP Reconstruction Algorithm .. 58
5.5 Discussion .. ... . .. 69




6 IMPLEMENTATION AND TEST OF AN SPIK(ING NEURON CHIP .71

6.1 Introduction ........ .. .. .. 71
6.2 Circuit Inmplenientation of the Transconductor .. .. .. 71
6.3 Circuit Inmplenientation of the IF Neuron ... .. .. 74
6.4 Neuron chip layout ......... .. 78
6.5 Neuron chip Test Results . ... .. 79
6.5.1 4-paranieter Sine Wave Fitting Test ... .. .. 81
6.5.2 Sine Wave Histogram Test .... .. .. 82
6.6 Discussion ......... . 84




7 IMPLEMENTATION AND TEST OF AN ASYNCHRONOUS DELTA
SIGMA CONVERTER ......... .. 86










7. 1 Introduction.
7.2 Asynchronous Delta Sigma Converter Architecture
7.3 Signal Reconstruction Algorithm .
7.4 Circuit Implementation 1.
7.4.1 Integrator
7.4.2 Schmitt T1;_ -- 1 and 1-bit DAC.
7.4.3 Chip Layout.
7.4.4 Chip Test Results.
7.5 Circuit Implementation 2.
7.5.1 Integrator and 1-bit DAC.
7.5.2 Schmitt Til---- _
7.5.3 Chip Layout.
7.5.4 Chip Test Results.


8 TIME-BASED ADC VARIATIONS .. ..

8.1 Introduction ........
8.2 Clocked Neuron Models ......
8.2.1 Globally Clocked Neuron .. .
8.2.2 Locally Clocked Neuron ....
8.3 Level-Mode Time-based ADCs ....
8.3.1 Level Crossing Sampling TB-ADC
8.3.2 Sawtooth Wave Crossing Sampling
8.4 Discussion.


TB-ADC


9 CONCLUSIONS

REFERENCES ...............

BIOGRAPHICAL SKETCH ...........
















LIST OF TABLES
Table page

2-1 C'!I. .) .:teristics of the C-ADC and the TB-ADC .. .. .. 9

5-1 Performance comparison of the reconstruction using truncated Gaus-
sian kernel and truncated Sinc kernel .... .. 68

5-2 Performance comparison of the reconstruction using truncated Gaus-
sian kernel and truncated Sinc kernel for 14 kHz average firing rate
spike train ......... ... 69

5-3 Signal to noise ratio due to different noise sources .. .. .. 70

6-1 The transistor sizes for the transconductance amplifier .. .. .. .. 79

6-2 The transistor sizes for the IF neuron .... .. 79

6-3 Neuron chip performance metric ...... .. 83

7-1 The .I-i-itchronous delta sigma converter chip 1 performance metric 96

7-2 Input and output transition table of the Schmitt tri ~-r (1K, rises from
below VI to above Vrh, and then drops below VI) .. .. .. 98

7-3 The .l-i-itchronous delta sigma converter chip 2 performance metric 105
















LIST OF FIGURES
Figure page

2-1 Signal representations. (a) Analog signal. (b) Sample and hold sig-
nal. (c)Asynchronous digital signal. (d)Digital signal .. .. .. 6

2-2 Block diagram of the conventional ADC ... .. .. 6

2-3 Block diagram of the tinte-based ADC .... .. 8

:31 Structure of a typical biological neuron .... .. 1:3

:32 Structure of the IF neuron . ...... .. 14

:3-3 Shapes of the V nee and the spike of the IF neuron .. .. .. .. 15

:34 Shapes of the V nee and the spike waveform of the LIF neuron .. 17

:35 Shapes of the V nee, S(t) and the spike waveform of the IF neuron
with threshold adaptation . .. .. 18

4-1 Spectrum of the spike train front the IF neuron .. .. .. 19

4-2 Reconstruction results front the IF neuron. (a) The spike train. (b)
The original and reconstructed signals. (c) The error between the
original and the reconstructed signals ... ... .. 2:3

5-1 Block diagram of the spiking neuron TB-ADC ... .. .. 27

5-2 Plot of SNR vs. aliasing frequency .... .... :31

5-3 Schematic of the leaky integrator .... ... 3:3

5-4 SNR vs. output resistance . ..... .. :37

5-5 SNR vs. Sine wave amplitude . .... .. :38

5-6 SNR vs. Sine wave frequency . .... .. .. :38

5-7 Noise model of the spiking neuron .... .... :39

5-8 SNR vs. thermal noise current power spectral density .. .. .. .. 46

5-9 Signal dependent reference voltage variation of the comparator. Higfh
and low slew rate are shown as solid or dashed respectively .. .. 47

5-10 Plots of coefficients C1 and C2 for signal dependent threshold variation 52










5-11 SNR vs. comparator time constant .... .. .. 54

5-12 Plot of SNR vs. clock period used in reconstruction .. .. .. 59

5-13 Plot of Sinc kernel vs. kernel length .... .. 60

5-14 Plot of SNR using the truncated Sinc kernel vs. signal length used in
the reconstruction .. ... .. 61

5-15 Plot of Gaussian kernel vs. kernel length ... ... .. 62

5-16 Plot of SNR using the truncated Gaussian kernel vs. signal length
used in the reconstruction . .. .. 63

5-17 Plots of the row vector of the matrix C using Sinc and Gaussian ker-
nels. (a) 20th row. (b) 80th row .... .. .. 64

5-18 Windowing scheme of the DSP reconstruction algorithm .. .. .. 67

6-1 Schematic of the transconductance amplifier .. .. .. 72

6-2 Latches with a positive feedback. (a) Capacitive feedback latch. (b)
Current feedback latch ....... .. .. 75

6-3 Schematic of the neuron circuit ...... .. 76

6-4 Layout of the neuron chip . ...... .. 78

6-5 Plot of the SNR vs. sine wave amplitude of the spiking neuron chip 81

6-6 Plot of the SNR vs. sine wave frequency of the spiking neuron chip .82

6-7 Plots of the DNL and INL from the sine wave histogfram test of the
spiking neuron chip ......... .... 83

7-1 Architecture of the .I-i-itchronous delta sigma converter .. .. .. 86

7-2 Circuit implementation of the Schmitt trigger (j!11-13) and the 1-bit
DAC (il 14q-15) ......... .. 91

7-3 Layout of the .I-i-itchronous delta sigma converter chip 1 .. .. .. 93

7-4 Plot of the SNR vs. sine wave amplitude of the .I-i-itchronous delta
sigma converter chip 1 (the sine wave frequency is 1 kHz, the con-
verter signal bandwidth is 6 kHz, and 0 dBFS refers to 0.2 V full
scale amplitude) ......... ... 94

7-5 Plot of the SNR vs. sine wave frequency of the .I-i-nchronous delta
sigma converter chip 1 (the sine wave amplitude is -2.5 dBFS) .. 95










7-6 Plots of the DNL and INL from the sine wave histogram test of the
.I-i-nchronous delta sigma converter chip 1 .. .. .. 96

7-7 Integrator implementation with 1-bit DAC .. .. .. 98

7-8 Block diagram of the Schmitt trigger . . 99

7-9 Delay unit of the schmidtt trigger .... .. . 100

7-10 Layout of the .I-i-alchronous delta sigma converter chip 2 .. .. .. 101

7-11 Plot of the SNR vs. sine wave amplitude of the .I-i-alchronous delta
sigma converter chip 2 . ...... .. 102

7-12 Plot of the SNR vs. sine wave frequency of the .I-i-nchronous delta
sigma converter chip 2 . ...... .. 10:3

7-13 Plot of the DNL and INL from the sine wave histogram test of the
.I- inchronous delta sigma converter chip 2 ... .. .. 104

8-1 Reference voltage waveform, capacitor voltages and spikes for clocked
neuron models. ......... .. .. 107

8-2 Reconstruction of the globally clocked neuron. (a) Spike train and
Vref waveform. (b) Original and reconstructed signals .. .. .. 108

8-3 Reconstruction of the locally clocked neuron. (a) Spike train and Vref
waveform. (b) Original and reconstructed signals .. .. .. .. 110

8-4 Reconstruction of the level crossing sampling TB-ADC. (a) Spike train
and Vref waveform. (b) Original and reconstructed signals .. .. 112

8-5 Reconstruction of the sawtooth wave crossing sampling TB-ADC. (a)
Spike train and Vref waveform. (b) Original and reconstructed sig-
nals ........ .... ........... 11:3















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

TIME-BASED ANALOG-TO-DIGITAL CONVERTERS

By

Dazhi Wei

August 2005

C'I ny~: John G. Harris
31. ri ~ Department: Electrical and Computer Engineering

We present the concept and some intplenientations of tinte-based analog-to-

digital converters (TB-ADCs). The TB-ADC employs a fundamentally different

architecture front the conventional ADC and achieves data conversion by repre-

sentingf signals as a series of discrete time events. This novel architecture trades off

simpler analog circuitry on the front end for more complex digital circuitry on the

back end, and is very promising for low power applications.

We show that theoretically we can use the weighted low-pass kernel (WLPK()

method to perfectly reconstruct the signal for the TB-ADCs. This method can also

be extended to solve general nonunifornt sampling problems. We investigate the

effect of different low-pass kernels such as Sine and Gaussian on the reconstruction

performance and computation cost. We also extensively analyze the fundamental

performance limitation of the spiking neuron TB-ADC due to nonidealities such

as frequency aliasing, leaky integration, thermal noise, signal-dependent threshold

variation, and time jitter. Much of this analysis can he extended to other TB-

ADC intplenientations. We also discuss some other TB-ADC variations including

clocked neurons and level-niode TB-ADCs. Test results of several prototype chips










implemented in 0.5 um C110OS technology process -II---- -1 that high resolution and

low power consumption TB-ADCs are achievable in practice.















CHAPTER 1
INTRODUCTION

1.1 Background

The scaling trends of very large scale integration (VLSI) C110OS processes

have continued to bring us higher speed and lower power digital circuitry every

year. The international technology road map for semiconductors (2003 edition)

has predicted that this scaling trend will continue until well into the next decade.

For example, the transistor minimum gate length and the power supply voltage

are predicted to reach 7nm and 0.5V respectively by 2018 [1]. Since this scaling

is optimized mostly for the performance improvement of digital circuitry, some

analog design issues such as voltage swing, intrinsic device gain and noise are

severely compromised, and high performance analog circuitry will be difficult

to design [2]. Therefore the signal processing trend is to continue to move more

and more functionality from analog circuitry to digital circuitry. The design of

analog-to-digital converters (ADCs) also follows the same trend.

Analog-to-digital converters are emploi-v I to acquire and digfitize analog signal

so that the signal can he processed by digital processors. Conventional ADCs are

realized based on the design scheme of sample, hold and amplitude quantization.

The resolution of conventional ADCs is determined in the amplitude, or voltage

domain. Because the available voltage swing continues to shrink due to the VLSI

process scaling, high resolution ADC design based on conventional design schemes

faces more and more challenges. Although synchronous delta sigma modulation

is a successful technique to improve the ADC performance [3, 4], its oversampling

nature demands high power consumption and limits its application.










New ADC implementations based on time quantization have been investigated

to alleviate drawbacks such as the reduced voltage swing, and to take advantage

of the high speed circuitry brought about by the VLSI scaling [5-7]. One common

feature in these implementations is that the signal is represented in the time

domain during data conversion. These implementations are called time-based

ADCs since their r solution is determined in the time domain, which is a marked

difference from conventional ADCs. Allier et al. have designed a new class of

.I-i-itchronous ADCs based on level-crossing sampling and time quantization [5].

The ADC power consumption is observed to be one order of magnitude less

than conventional ADCs for similar performance. However a reconstruction

algorithm is not discussed in the implementation to convert the nonuniformly

sampled sequence to the uniformly sampled sequence. Roza previously proposed

an ADC implementation using .I-i-itchronous delta-sigma modulation and time

quantization [6]. The implementation uses an inherent direct low-pass filtering

method to reconstruct the signal. To achieve some specific ADC performance, a

large oversampling ratio is needed to suppress higher order harmonic distortions.

Lazar and Toth have realized an iterative algorithm method based on nonuniform

sampling theory to theoretically achieve perfect signal reconstruction from the

.I-i-itchronous delta-sigma modulation [7]. This method is not easy to apply to

other general time-based ADC implementations, and the effects of nonidealities on

the ADC performance were not extensively studied.

1.2 Motivation

The first motivation of this dissertation is to investigate possibilities of

time-based ADC implementations. The signal reconstruction algorithm is a

key component to determine the performance of the implementations. We will

develop a general algorithm that can he efficiently applied to all time-based ADC

architectures.










The second motivation is to characterize the effects of nonidealities on the

ADC performance. Effects of nonidealities on conventional ADC performance have

been extensively studied. However, due to different sampling and quantization

scheme, these nonidealities have different effects on time-based ADC performance

and need to be investigated to guide practical designs.

The third motivation is to strive for the high resolution and low power TB-

ADC circuit implementations. Novel architecture and circuit design techniques

need to be studied to achieve better ADC performance.

1.3 Dissertation Structure

This dissertation consists of nine chapters and is organized as follows.

In C'!s Ilter 1 we introduce the background of the ADC implementations and

present some motivations of this dissertation.

Chapter 2 reviews the architecture of the conventional ADCs, gives the

definition and architecture of the time-based ADC, and summarizes comparison

between these two types of ADCs.

In C'!s Ilter 3 we will talk about the spiking neuron models which can serve as

the encoder in the time-based ADC implementations. Biological neuron models will

also be briefly reviewed.

Chapter 4 introduces a theoretically perfect signal reconstruction algorithm

which can he applied to general time-based ADC architectures. The performance

of the algorithm is verified through signal reconstruction from different types of

spiking neuron models.

In C'!s Ilter 5 we investigate effects of some nonidealities on the performance

of the time-based ADC. For the spiking neuron encoding component we consider

the frequency aliasing of the input signal, finite DC gain of the integrator, thermal

noise of the spiking neuron, and the signal dependent threshold of the comparator.










For the DSP reconstruction component, we consider the timing jitter of the time

quantizer, the kernel selection and the windowing of the DSP algorithm.

In C'!s Ilter 6 we present the circuit intplenientation of the spiking neuron time-

hased ADC. We consider some practical issues and make some tradeoffs during

the intplenientation. The performance of the neuron chip is measured based on the

IEEE ADC test standard.

Chapter 7 will present a tinte-based ADC intplenientation based on the

.I-i-mlhronous delta-signia modulation which includes the architecture, the detailed

circuit intplenientation, the signal reconstruction algorithm, and the measured chip

performance.

In C'!s Ilter 8 we will discuss other tinte-based ADC variations and give some

simulation results of the intplenientations.

Finally, the conclusions will be given in ChI Ilpter 9.















CHAPTER 2
TIM\E-BASED ANALOG-TO-DIGITAL CONVERTERS

2.1 Introduction

In this chapter we first review different types of signal representations. Based

on different transient signal representations used during data conversion, we give

definitions of the conventional and the time-based ADCs. Finally we conclude this

chapter with a comparison between these two types of ADCs.

2.2 Signal Representation

The signal being processed by ADCs is typically a one-dimensional signal

which can he represented by a voltage or current amplitude varying in time.

Based on whether the amplitude and time variables are continuous or discrete,

ADCs may deal with 4 types of signals during data conversion, i.e., analog signals,

sample-and-hold signals, .I-i-alchronous digital signals and digital signals, which are

shown in Figure 2-1 (a), (b), (c) and (d), respectively. The black dots in the figure

represent the sample points of the signal. ADCs are used to convert the analog

signal, which is continuous in both amplitude and time, to a digital signal, which is

discrete in both amplitude and time. Signals with discrete amplitude can he more

accurately restored through buffering in a noisy environment; therefore the digital

signal and the .I-i-alchronous digital signal are more robust to noise. The digital

signal and the sample and hold signal are usually uniformly sampled sequences,

and can he reconstructed back to an analog signal through simple low-pass filteringf

hased on Nyquist sampling theory. Therefore, the sample and hold signal is easy to

reconstruct but sensitive to the noise while the .I-i-alchronous digital signal is robust

to noise but difficult to be reconstructed because of the nonuniform sampling.

The sample and hold signal and the .I-i-nchronous digital signal are two possible










Time


Continuous


Discrete


Time
(a)


Figure 2-1: Signal representations. (a) Analog signal.
(c)Asynchronous digital signal. (d)Digital signal


(b) Sample and hold signal.


transient signal representations that can he used during data conversion. The

characteristics of ADCs are determined by different transient signal representations

used in implementations.

2.3 Conventional Analog-to-digital Converters (C-ADCs)

The conventional ADC (C-ADC) realizes the data conversion through the

scheme of clock sampling and amplitude quantization. Figure 2-2 shows a typical

architecture of the conventional ADC [2]. The sampling frequency f,, i.e., the clock


Analog signal


S/H signal


Digital signal


Analog circuitry


Figure 2-2: Block diagram of the conventional ADC


Digital circuitry










frequency, must be larger than two times the maximum signal frequency to avoid

frequency aliasing according to Nyquist sampling theory. Therefore an antialiasing

filter is strictly required to remove frequency components higher than f,/2 from the

input analog signal. The sampling circuit samples the filter output by recording the

amplitudes at integer numbers of the clock period. This sampling method is called

amplitude sampling. The resulting sample-and-hold signal perfectly represents

the filter output without any information loss based on the Nyquist sampling

theory. Later the signal amplitude is approximated with fixed reference levels by

an amplitude quantizer and then converted to a digital signal by an encoder. This

approximation error, which is also called quantization noise, determines that the

filter output cannot be perfectly reconstructed from the digital signal, resulting in

the finite resolution of the ADC. In practice besides the amplitude quantization

noise there are many other error sources such as thermal noise and nonlinear

distortions during the data conversion. The difference between the original filter

output and the reconstructed signal from the digital signal is due to the effect of

all these error sources. In this dissertation we do not differentiate the difference

among these error sources and use the word in ~-a--" to represent all of them. The

resolution of the ADC is related to the signal to noise ratio (SNR) as described

below :

SNR Sign~al -(.2 1.76)dB (2.1)
PNoi.se
where NV is the effective number of bits resolution of the ADC. The definition of the

SNR in this dissertation is equivalent to definitions such as the signal to error ratio

(SER), or the signal to noise and distortion ratio (SINAD) in other literatures.

There is another class of conventional ADC called synchronous delta sigma

ADC which is based on oversampling and noise shaping techniques. It shares

a similar block diagram as shown in Figure 2-2. The analog signal is sampled

using such a high sampling frequency f, that only a small part of the amplitude



















Figure 2-3: Block diagram of the time-based ADC


quantization noise falls into the signal band, and then the noise is shaped by a

negative feedback in such a way that most of the noise is pushed out of the signal

band while preserving the in-band signal. A decimation filter (the encoder in

Figure 2-2) is needed to low-pass and downsample the quantizer output to obtain

the digital signal at the Nyquist rate. In this way the constraints on the quantizer

are relaxed while achieving high SNR at the cost of additional complexity on the

encoder.

2.4 Time-based Analog-to-digital Converters (TB-ADCs)

From above we see that C-ADCs quantize amplitude at predefined time in-

tervals. On the other hand, time-based ADCs (TB-ADCs) achieve data conversion

through a scheme of quantizingf time at predefined amplitude intervals. The TB-

ADC block diagram is shown in Figure 2-3. An antialiasingf filter works in the

same way as that in the C-ADC to make sure the filter output is a bandlimited

signal. An encoder performs the sampling operation and converts the filter output

to a .I-i-itchronous digital signal. The encoder records the time stamps whenever

the amplitude of the filter output, or the amplitude of the transformation of the

filter output, crosses some predefined references. This sampling method is called

time sampling. Examples using time sampling method are level-crossing sampling

(amplitude is the reference level when the sampling happens), and pulse position

modulation (amplitude is the sawtooth wave value at the sampling instant). The

.I-i-itchronous digital signal is then synchronized to a time quantizer, i.e., a clock,


Analog signal


Digital signal


I r
Analog circuitry Digital circuitry









Table 2-1: CI. .) :teristics of the C-ADC and the TB-ADC

C-ADC TB-ADC
Sampling method Amplitude sampling Time sampling
Amplitude Quantized Exactly known
Time Exactly known Quantized


and the sample time stamps are approximated to the nearest integer number of

clock periods Te. This approximation error, or time quantization noise, determines

the finite resolution of the ADC. Since the digital signal to be processed by current

DSP technology is uniformly sampled, a DSP reconstruction algorithm is required

to convert the nonuniform samples with time quantization to the uniformly sam-

pled digital signal. Obviously the efficiency of the DSP reconstruction algorithm

is expected to affect the resolution of the ADC. Similar to conventional ADCs

although maybe in different v- .--s, other error sources during data conversion also

degrade the ADC performance. Again we use the word in~~-a--" to represent the to-

tal effect due to these nonidealities. The signal-to-noise ratio is defined and related

to the resolution of the ADC in a similar way as in Equation 2.1.

2.5 Comparison Between the C-ADC and the TB-ADC

Table 2-1 summarizes the different characteristics of the C-ADC and the

TB-ADC we have discussed in previous sections. This characteristic difference is

mainly due to the different transient signals (sample and hold signal, .I- i-nchronous

digital signal) used by the C-ADCs and the TB-ADCs during data conversion. For

C-ADCs the sample time is exactly known and the signal information is encoded in

the unknown and quantized amplitude. On the contrary, for TB-ADCs the sample

amplitude is exactly known and the signal information is encoded in the unknown

and quantized time. That is the reason why we may call the TB-ADC a dual case

of the C-ADC [5]. Clearly the implementations of the C-ADCs and TB-ADCs have

different characteristics.










The first difference between C-ADC and TB-ADC is the position of the

quantizer in the ADC implementation. From Figures 2-2 and 2-3 it is clearly

seen that quantization of TB-ADC uses conventional digital circuitry while C-

ADC is quantized with conventional analog circuitry. Analog circuitry faces more

difficult tradeoffs among power, noise and resolution compared to digital circuitry.

This difference means the TB-ADC can better utilize the high speed and low

power digital circuitry to obtain improved ADC performance while relaxing the

requirement on the analog circuitry.

The second difference is that TB-ADC can be split into a transmitter side

and a receiver side while C-ADC can only be used in the transmitter side. The

.I-i-nchronous digital signal in TB-ADC is already discrete in amplitude and robust

to noise and thus suitable for long distance transmission, while the sample and

hold signal in C-ADC is continuous in amplitude and not suitable for transmission.

This means TB-ADC is capable of saving power on the transmitter side and thus a

better candidate for power limited applications.

The third difference is that TB-ADC uses a signal driven sampling method

while C-ADC uses a signal independent sampling method. The sampling frequency

of the C-ADC is a constant and equals to the clock frequency. Even when the

signal is negligible the C-ADC still outputs at the same sampling frequency

and consumes unnecessary power. Since TB-ADC uses a signal driven sampling

method, the ADC may be implemented to output at a low sampling frequency in

regions of low interest. One example of the signal driven sampling method is that

stronger signals tr~i c-;r more samples while weaker signals trigger fewer samples.

This can further reduce power consumption wasted in sampling negligible signals.

The last difference is that the reconstruction part of the TB-ADC is a nonuni-

form sampling problem while that of C-ADC is a uniform one. Good reconstruction

performance can be achieved by simple low-pass filtering for C-ADC. It will be









seen that for the TB-ADC simple low-pass filtering leads to poor reconstruction

performance, and a more complicated reconstruction algorithm should be carefully

implemented to avoid degrading the performance of the ADC.

In summary, the TB-ADC trades off simpler analog circuitry for more complex

digital circuitry, which is reasonable since high speed and powerful digital circuitry

is easily realized. This tradeoff is also a good way to deal with the challenges

brought about by VLSI scaling.















CHAPTER 3
SPIK(ING NEURON SIGNAL REPRESENTATION

3.1 Introduction

The neuron is a fundamental unit of biological nervous systems [8, 9]. Since

these systems are characterized by incredible pattern recognition performance with

ultra low power consumption, it is wise to understand these strategies in the design

of low power engineering systems. Thus the study in neural encoding is expected

to provide some hints to build more efficient nian-nmade devices such as ADCs. In

this chapter we first introduce the structure and the encoding processing of the

biological neuron, and then present several simplified spiking neuron models which

can serve as the encoders in TB-ADC structures.

3.2 Biological Neuron

Most information in this section is from van Schaik's PhD dissertation [10] and

Mead's book [11]. Figure 3-1 shows the structure of a typical biological neuron.

Nearly all neurons use spikes to coninunicate with one other. The spike, or action

potential, is a voltage pulse. All neural spikes share a similar shape and thus the

information is believed to be encoded in the spike time. The neuron receives spikes

front other neurons' axons by synapses on its dendrites and cell body, and the cell

body processes the information and generates its own spikes at the axon hillock

which then travel along its axon to other neurons.

Spike generation is a very important component of neural encoding. Hodgkin

and Huxley developed a model to describe the spike generation in the squid

axon in 1952 [12]. The inside of the neuron is high in potassium concentration

while the outside extracellular liquid is high in sodium concentration. The cell

nientrane contains many potassium and sodium channels, and in the resting

























Figure 3-1: Structure of a typical biological neuron

state the potential of the intercellular fluid is around -80 mV with respect to the

ground potential of the extracellular liquid. The spikes from other neurons release

some charge into the neuron through the synapses and increases the membrane

potential. Experiments show if the membrane potential can be increased above

-40mV, the neuron can generate spikes, otherwise the potential slowly decays

back to its resting state. This phenomenon is caused by dependence of the opening

and close of the potassium and sodium channels on the the membrane potential.

When the potential is increasing and above -40 mV, the rapid opening of the

sodium channels brings positive sodium ions inside the neuron and further increases

the potential. The positive feedback loop quickly raises the potential to +40 mV.

Meanwhile, the sodium channel is inactivated slowly, and most importantly a

d- 1 li- II opening of potassium channels causes the positive potassium charge flow

out of the neuron, which results in the quick decrease of the potential back to the

resting state. The total effects of the sodium and potassium channels cause the

active potential. After an action potential there is a refractory period during which

no spikes can be generated. This is due to the fact that the sodium channels are

inactivated and the potassium channels are open for some extra time after spiking.













x(t)


r~ef







Figure 3-2: Structure of the IF neuron

3.3 Integrate-and-fire Neuron Models

Although the Hodgkin-Huxley model successfully describes the spike gener-

ation of the biological neuron, it is too complicated for a compact circuit imple-

mentation. Spiking neuron models based on the integrate-and-fire mechanism also

capture the essentials of the spike generation, and are easily implemented in silicon.

3.3.1 Integrate-and-fire Neuron Model

The structure of the integrate-and-fire (IF) neuron model is shown in Figure

3-2. The effect of the charge released by other neurons' spikes is modelled by a

current source x(t). The membrane is modelled by a passive capacitor C. The

current is integrated over the capacitor C and increases the capacitor voltage

Vmem. Once Vmem is above the threshold voltage Ve,, of the comparator, a spike

is generated and Vmem is then reset to ground and another integration period

begins. The shapes of Vmem and the spike are shown in Figure 3-3 where tib and

tie are the timings for the falling and rising edges of the spike. Obviously the

signal information is encoded in the integration period. Equations 3.1, 3.2 and 3.3










Sp~ike"






tib tie t







tib ie t

Figure 3-3: Shapes of the Vmem and the spike of the IF neuron

describe this encoding process.

dVmem
C =x(t) (3.1)


Vmem(tib) = 0 (3.2)

Vmem(tie) = Vref (3.3)

We can also use one equation to describe this encoding process.


x$tdt CVey = 0 i (3.4)

If we assume the spike width is infinitely small, we obtain spike timings ti = tib

and tis = t(i+1)b = tie, and Equation 3.4 simplifies to


xr. d = 0, V (3.5)









If we also defin~e th~e integral of th~e sjignl as! f(t) = ff x~(s)dls where to is th~e

beginning of the first integration period, Equation 3.5 is equivalent to


f (ti) = ie Vi (3.6)


This shows us another view of the encoding process which records the time

whenever the integral of the signal crosses the level of integer number of 0. This

interpretation places the integfrate-and-fire neuron in the class of TB-ADCs defined



3.3.2 Leaky Integrate-and-fire Neuron with Refractory Period Model

As mentioned in Section 3.2 the spike generation of biological neurons shows

some features of leaky integration and the refractory period. When the IF neuron

in Section 3.3.1 is implemented in circuitry, the finite output impedance of the

current source and other parasitic resistances in parallel with the capacitor lead to

a leaky integration, and meanwhile the finite slope of the spike falling edge causes

some refractory period. To model the leaky conductance a resistor R is introduced

in parallel with the capacitor C. The spike generation is similar to the IF neuron

case, and the shapes of Vmem and the spike are shown in Figure 3-4 where T,

represents the refractory period. Similarly this encoding process can be described

by Equations 3.7, 3.8 and 3.9.


C/ + = x (t) (3.7)
dt R

Vmem(tib Tr) = 0 (3.8)

Vmem(tie) = Vref (3.9)

We can also use one equation to describe this encoding process.


x (t)e dt= CIre; = 0, i. (3.10)
t ib+Tr










Sp~ike"






tib tie







tib tibf Tr tie


Figure 3-4: Shapes of the Vmem and the spike waveform of the LIF neuron

We can notice that Equation 3.10 is consistent with Equation 3.4 when the leaky

resistance R takes on an infinite value.

3.3.3 Integrate-and-fire Neuron with Threshold Adaptation

Biological neurons also exhibit some adaptive properties when generating

spike trains [9, 13, 14]. When a strong stimulus is applied to the neuron, the neuron

firing rate will initially be high and then adapt to a lower value. The adaptive

mechanism may serve to save power and improve dynamic range. These adaptive

properties can be utilized in low power ADC applications. Threshold adaptation is

one way to introduce adaptive properties into the neuron model [14]. The threshold

decays exponentially and is incremented after an action potential by an amount

determined by previous firing patterns. The Equations below describe the encoding

processing.
dV,,
C em=x(t) if Vmem(t) < S(t) (3.11)

dS S S
if Vmem(t) < S(t) (3.12)

Vmem(tb) = 0 if Vmem(tib) = S(tib) (3-13)









Spike




I 1,
tib tie t

i\
\ S(t) I\





tib tie t

Figure 3-5: Shapes of the Vmem, S(t) and the spike waveform of the IF neuron with
threshold adaptation

S(t/b) = So + aS(tib) f Vmem(tib) = S(tib) (314

where 7r, is the time constant of the threshold, S, is the steady state value of

the threshold in the absence of firingf and a~ is a positive number less than 1.

Figure 3-5 shows the waveforms of the capacitor voltage Vmem, the threshold S(t),
and the spike train for the neuron with threshold adaptation. We can see that if

S, = So = Ve,, and a~ = 0, the adaptive neuron reduces the ideal IF neuron with
constant threshold.

3.4 Summary

In this chapter we introduced a typical biological neuron and some integrate-

and-fire neuron models. These neuron models represent information in spike

timings and therefore can serve as the encoder in the TB-ADC architecture. In the

following chapter we will show the DSP algorithm which can be used to reconstruct

signals from these spike timings.















CHAPTER 4
RECONSTRUCTION FROM SPIKING NEURON MODELS

4.1 Introduction

As mentioned in C'!s Ilter 2 the performance of the TB-ADC also depends

on the reconstruction algorithm. Poor reconstruction methods can degrade the

ADC performance dramatically even when the signal is accurately encoded by the

encoder. This chapter describes the method to perfectly reconstruct the signal from

the spiking neuron.

4.2 Direct Low-pass Filtering Reconstruction Method

The effort to reconstruct signals from the neuron spike train can be recalled

back to as early as 1968, when Bayly gave a spectral analysis of the spike train

from IF neuron with single sinusoidal input [15]. His results show that in some

cases the signal can be reconstructed with some tolerable distortion from the spike

train using direct low-pass filtering. We assume the threshold voltage is Vre;

and the spike train is modelled as an unit-area impulse train with ti as the firingf

times, Equations 3.1, 3.2 and 3.3 then can be simplified as


0 =~- xtd (4.1)







1 IOI.1 2 fo



Figure 4-1: Spectrum of the spike train from the IF neuron










Considering the simple case where the input to the IF neuron is a sinusoidal signal

x(t) = mo + mi cos(2x fmt), and one of the spikes happens at t = 0, the spectral

description of the spike train from Bayly's analysis is given as:

m1
p(t) = fo + cos(2x fmi)

+ 2 fo In()(1 + ) cos(2xr(k fo + n fm)t) (4.2)
k=1 n=-oo

where fo = mo/8 is the fundamental frequency which is equivalent to the average

spike firingf rate, and Jo is a Bessel function of the first kind of order n. The first

two terms in Equation 4.2 are directly from the input signal x(t) scaled by 8, the

other terms k fo + n fm are the frequency components cross modulated between fo

and fm. The spectrum can be seen more clearly in Figure 4-1. For the spectrum

of the spike train generated from multi-tone input signal, the result is similar to

Equation 4.2 except more complicated cross modulated frequency components [16].

The direct low-pass filteringf reconstruction method is to pass the spike train

through a low-pass filter with cutoff frequency equal to the maximum signal

frequency to remove cross modulated components. It can be clearly seen from

Equation 4.2 or Figure 4-1 that no matter how large the average firing rate fo

is, there are ah-li-w some cross modulated components k fo + n fm falling into the

signal band [- fm, fm] which can not be filtered out even using ideal low-pass filter.

This means perfect signal reconstruction can not be achieved using this method. In

practical signal reconstruction, the cross modulated components in the signal band

usually have non-negligible magnitude, and thus the reconstruction performance of

direct low-pass filteringf is not acceptable for most applications.

4.3 WLPK Reconstruction Method

The signal reconstruction from TB-ADC is a non-uniform sampling problem.

Developments in the non-uniform sampling theory have shown that perfect signal

reconstruction can be achieved in some cases [17, 18]. We have developed the










weighted low-pass kernel method (WLPK() to realize perfect signal reconstruction

[19]. The method is described below:

From non-uniform sampling theory we can derive the claim: any bandlimited

signal can be expressed as a low-pass filtered version of an appropriately weighted

sum of d-1 li-. I impulse functions [17], [18]. Assuming that x(t) is bandlimited to

[-R,, R,], and sj's are the timings of the impulse train and the maximum .Illi Il:ent

sample timing distance is less than the Nyquist period T = xr/R,, then we have







where my are scalar weights, h(t) is the impulse response of the low-pass filter and *

denotes the convolution operator. The impulse response of the ideal low-pass filter

is given by the Sine function:


h(t) = sin(Rst)/(Rst) (4.4)

Now the signal reconstruction problem is simplified as how to calculate the

appropriate weights. If sj = jT is a uniform sampling sequence, standard sampling

theory can be used to show that the impulse weight reduces to the sampled value of

signal x(t) at the timing sj, i.e., my = x(sj). But generally the weights need to be

calculated using the encoding information.

4.3.1 Reconstruction from the IF neuron

We first consider the reconstruction from the integfrate-and-fire neuron without

any refractory period. The firing times must satisfy:


x~t~d = Os, Vi(4.5)


where Os = 0 for constant threshold, and tib and tie are the falling edge and the

rising edge of the spike. Let us assume that x(t) is bandlimited to [-R,, R,], and










tib, i EZ and tie, i EZ are timing sequences with maximum .Illi Il:ent interval

(t(i+1)b tib) < ,((i+1)e tie) < T, Where the Nyquist period T = xr/R,.

We can create an impulse train with timing sj = (tjb + je)/2 with maximum

.Il1i Il:ent timing interval which is less than the Nyquist period T, and then x(t) can

be expressed as in Equation 4.3. Substituting Equation 4.3 into Equation 4.5, we

obtain







= wci (4.6)


where cs, are constants that can be numerically computed with:


cij = ih(t syld (4.7)
Itib

The resulting set of linear e nations is given by C W = 0 in matrix form where

W is a column vector with wj as the jth row element, C is a s uare matrix with

cj as the ith row ith column element, and 8 is a column vector with Os as the ith

row element. Unfortunately C is usually ill-conditioned necessitating the use of a

SVD-based pseudo-inverse conditioning technique [20] or other matrix regulation

techniques to calculate the weights. The computation cost is estimated assuming

the use of the Gaussian elimination method as discussed in later chapters [21, 22].

Thus we can obtain the weight vector W:


W = C' 0 (4.8)


Now we can substitute the weight vector to Equation 4.3 to numerically calculate

the reconstructed signal x(t) to within machine precision. In order to facilitate

later discussions we may further simplify the expression of the reconstructed signal













21


x 106 A
2 Original
Reconstructed



x 10 1A





3 4 5 6 7 8 9 10
Time (S) x 10-3


Figure 4-2: Reconstruction results from the IF neuron. (a) The spike train. (b)
The original and reconstructed signals. (c) The error between the original and the
reconstructed signals













As(t) = [h(t sj)lc,(4.10)






and-fre neurotn. The rrinputh signal~m isnn a asinC rando noise, signal~[ bandlmted to








[-3000xr, 3000xr] rad/s, and the corresponding Nyquist period T = 1/3 ms. The DC

current is 800 nA, the capacitance C = 18 pF, the reference voltage Vre; = 3 V, the










spike width is 6.6 us. Since the maximum .ll11 Il:ent spike interval (0.15 ms) is less

than T, this method can be used to reconstruct the input signal. The simulation

results show the effective signal to noise ratio (SNR) of the reconstruction is 107.6

dB. SNR is computed as the power of the input signal divided by the power of the

error between the original and the reconstructed signals.

4.3.2 Reconstruction from LIF neuron with refractory period

Equations 3.7, 3.8 and 3.9 describe the encoding operation of the leaky

integrate-and-fire neuron with the current input. They are used to generate a

linear system of equation in a similar fashion to the ideal integrate-and-fire neuron

discussed in Section 4.3.1, except the coefficient matrix C element


ce; =h(t sj) e(t-tie)/(nC)dt (4. 11)
~ 'tib+Tr

which is the leaky integration of h(t sj) over the time period [tib Tr, ie -

Equation 4.11 is consistent with Equation 4.7 when the leaky resistance R takes on

an infinite value. We can use Equation 4.8 to calculate the weights for each impulse

at sj, then use Equation 4.3 to reconstruct the signal x(t).

4.3.3 Reconstruction from the IF neuron with threshold adaptation

To reconstruct the signal from the IF neuron with threshold adaptation we

have to know the integration of the input signal over the ith integration period, i.e.,

the threshold at the time tie. Assuming the threshold does not change from t(i-1)e

to tib, from Equations 3.12, 3.14 we can obtain the threshold value at tie

tib-tie
04 = S(tie) = (So + a~S(t(i-1)e) S,)e vs + S,
tib-tie tib-tie
=S(t(i-1)e)a~e + S, + (So S,)e vs (4. 12)


which can be determined if we know the previous threshold value at t(i-1)e-

Therefore if the initial threshold value is given, we can calculate the exact following

threshold values using Equation 4.12, and then use Equations 4.7, 4.8, and 4.3 to










reconstruct the signal. If the initial threshold value is not given, some estimation

error will be introduced into the reconstruction. However, it is believed that the

estimation error decays with time. This is due to the fact that the coefficient
tib-tie
a~e 7 m Equation 4.12 is a number less than 1.

4.4 Discussion of Other Reconstruction Methods

Previous simulation results show that the WLPK( method achieves much better

performance than the direct low pass filtering method. Besides these two methods,

there are also other methods which can be used for the signal reconstruction from

the spiking neuron.

Nogfuchi et al. found one method based on the integral mechanism of the

neuron encoding and claimed the reconstruction performance is better than simple

low pass filtering [23, 24]. Their method uses B-spline interpolation to approximate

the integration function of the original signal x(t) and then differentiate it to

obtain the original input x(t). The reconstructed signal is not perfect since the

approximation error can not be avoided. Lazar et al. realized an iterative algorithm

method based on nonuniform sampling theory to theoretically achieve perfect

signal reconstruction from the .I-i-nchronous delta-sigma modulation [7]. Since

the IF neuron has a similar integral mechanism of the .I-i-nchronous sigma-delta

converters, this method is also applicable to the IF neuron. The problem with

Noguchi's and Lazar's methods is that they are not easy to be applied to more

complicated model such as the leaky IF with refractory period or threshold

adaptation, see Gerstner [13] for more neuron models. This seriously limits their

application since practical IF neuron circuit ahr-l- .- has some leaky and refractory

period features which need to be considered in the reconstruction for better

performance. The WLPK( method we discussed is better in that it can be applied

to general time-based ADC architecture.















CHAPTER 5
PRACTICAL ISSITES RELATED TO SPIK(ING NEURON TB-ADC
IMPLEMENTATION

5.1 Introduction

In this chapter, we first introduce a spiking neuron TB-ADC intplenientation

using the spiking neuron model discussed in OsI Ilpter :3, and the DSP reconstruction

algorithm block discussed in OsI Ilpter 4. Since the actual building components used

are not perfect, we then investigate effects of some nonidealities on the performance

of the analog to digital conversion. For the spiking neuron encoding component

we consider the frequency aliasing of the input signal, leaky integration of the

integrator, thermal noise of the spiking neuron, and the signal dependent threshold

of the comparator. For the DSP reconstruction component, we consider the timing

jitter of the time quantizer, the kernel selection, and the windowing of the DSP

algorithm.

5.2 Implementation of Spiking Neuron TB-ADC

Figure 5-1 shows an intplenientation of the spiking neuron TB-ADC. The

detailed circuit intplenientation will be discussed in OsI Ilpter 6. The components

inside the dashed box form an integrate-and-fire neuron encoder which was

previously discussed in C'!s Ilter :3. Compared to the previous structure in Figure :3

2, a transconductor Gen block is used to convert a voltage signal V(t) to a current

signal .r(t) = G,2V(t) since the input signal for many analog to digital applications

is in voltage form. If the input is a current signal, the Gen block is obviously not

needed and the ADC design is simplified. The neuron encodes the analog signal

waveform in the transition timings of the spiking signal. The time quantizer

quantizes the transition timings of the spiking signal with a clock period T,.. The











AnlgI V(t) X(t)
Anlg Gm : Spiking
Input .oP) signal

C Vre


IF Neuron


Figure 5-1: Block diagram of the spiking neuron TB-ADC


DSP reconstruction then uses the WLPK( method discussed in OsI Ilpter 4 to convert

the nonuniform spiking signal to a uniformly sampled digital signal.

5.3 Practical Issues Related to Signal Encoding in Spiking Neuron
Models

The encoder is the fundamental part of the TB-ADC that determines its

performance. Special attention should be paid to the implementation since the

encoder uses analog circuitry, which is sensitive to many nonidealities such as

nonlinearity, finite amplifier DC gain, finite amplifier speed, and noise.

5.3.1 Frequency Aliasing of the Input Signal

For simplicity, we neglect the transconductance amplifier Gm block and

consider the input signal to the neuron as the current x(t). Since it is assumed that

the input signal is bandlimited, an anti-aliasing pre-filter is strictly required to be

placed before the neuron to filter out higher frequencies. Since the anti-aliasing

pre-filter is not perfect in practice, some higher frequency components will still

exist in the input to the neuron. We should investigate the effect of these higher

frequency components on the ADC performance. It is well known that for standard

Nyquist rate sampling, higher frequencies are simply mapped to lower frequencies,

preserving the amount of power [25]. As will be seen, the nature of aliasing for

neuron encoding is significantly different. Our intuition ;7io that the integration









causes higher frequencies to be attenuated more than lower frequencies. Now let us

mathematically explain this frequency aliasing effect.

Assume the desired input signal V(t) is corrupted by a high frequency sine

wave V,(t) = A, cos(2x fat) with f, much higher than the signal band R,/(2xr). The

actual input signal to the integrate-and-fire neuron is V(t) + V,(t) and we have the

following encoding equation:


V~)+V,(t)dt = CVre; = 0 (5.1)

where tib and tie are the beginning and the end of ith integration period. Since

the frequency fa is larger than the signal bandwidth as/(2xr) and the bandwidth

requirement is not satisfied, we cannot express V(t) + V,(t) in a similar form to

Equation 4.3. Therefore we cannot perfectly reconstruct V(t) + V,(t). However,
what we really want to reconstruct here is the signal V(t). It can still be expressed

using Equation 4.3, if the high frequency component V,(t) does not affect the spike
timing so much that the maximum interspike interval is still less than the Nyquist

period. Theoretically we can still perfectly reconstruct V(t) if we could find the

actual integration Os = Gm, ft we V(t)dlt. We~ rewrite Eqcua~tion 4.91 a~s follows:


V~t) Ast)04(5.2)

Since we do not know the exact function of V,(t) and cannot find the exact value of

Os, in practice we use 8 as the integration of V(t) to obtain the reconstructed signal

V(t) :



The difference between the input signal V(t) and the reconstructed signal V(t)

represents the noise due to the frequency aliasing which obviously degrades the









reconstruction performance. We can calculate (8 Os):


/" e tie
Gm V(t) +V,(t)dt Gm V(t)dt
lib ib
Gm V,(t)dt
/"e
Gm As cos(2x faidt
JO
GmA, sin(2x fai)/(2x fe)


8 04


(5.4)


where ni is assumed to be an independent identical random variable uniformly

distributed in [-1/2 f,, 1/2 f,]. From Equations 5.2, 5.3, 5.4, we can calculate the
noise power due to the frequency aliasing:


E[(V(t) Vi(t))2]


(2 2E [(~ hi(t)( si(2 fai))2


(2K a)2 E [h(t)E [~:(sin(2xf,,ri))2

2(2 Tf,)2E ()]


Pnoise,aliasing


(5.5)


The signal power is:


Psignal = E[(V(t))2]
~ [(i(V))2]

E[( ~hi(t))2] (5.6)

where the approximation is made with the assumption that the error between

the reconstructed signal and the input signal is relatively very small. Finally the
corresponding signal to noise ratio (SNR) is:

Psignal
SNVRaliasing=
Pnoise,aliasing









8;,2 f2eE [(Ci A(t))2]
G AjE[Ci Af(t)]
~' A2 (5.7)

where the approximation is made with the assumption of low oversamplingf

ratio ( ). Aslt) is a weigh~ted delwedi~~ low-p~ass kernel. Due to th~e kernel's
time-decaying property, the mean of the product of two kernels far apart, i.e.,
E[hi(t)hj(t)], is much smaller than the power of the kernel, i.e., Elhf2t)]. Since the

oversamplingf ratio is not high and most kernels are far apart, the approximation
E[(EP hit))2] = [EA () +2[C hi.( t)hyi~t)] ~ E[E A (t)] s valid

Equation 5.7 shows that increasing 8 is helpful to suppress the frequency aliasing
effect. This reduces the relative variation of the integration Os which is due to high

frequency components.

In practice, thle average firing ratei few, = is related to the signal
bandwidth of the ADC, and is usually a predefined number. Equation 5.7 can be

further simplified as:

8K2 A22

(5.8)
Ag ff,

where cd is the DC component of the input signal. Increasing cd is equivalent

to increasing CVre; with constant f,,,, and is helpful to reduce the performance

degradation due to the frequency aliasing.

Equation 5.8 shows that the SNR is proportional to the frequency of the

aliasing sinusoid with a slope of 20 dB/decade, and inversely proportional to the

amplitude of the aliasing sinusoid with a slope of 20 dB/decade. Therefore our
initial intuition is verified and this anti-aliasingf effect of the neuron has the effect

of a first-order low-pass filter. The cutoff frequency of this "low pass filter" is

approximately the signal bandwidth.











140
SNumerical evaluation
---App roxi mate Eq uation 5.8
120 - -





S80 t-j-------
Z
60 -- -- *


4 0 ------


20 -


102 104 106 108 101
Aliasina freauency (Hz)


Figure 5-2: Plot of SNR vs. aliasing frequency


Simulations have been run in 1\atlah to validate the previous derivations.

Figure 5-2 shows a plot of SNR vs. the frequency of an added high-frequency

sine wave. The signal used in this simulation is the same as the one used in

Figure 4-2. The ADC bandwidth is defined as 1.5 kHz. The solid red line and

the dashed blue line represent the results from the numerical evaluation and the

Equation 5.8, respectively. We can clearly see that the detrimental effect of the

aliasing of the high frequency component is reduced as the frequency of the added

sine wave increases. When the frequency of the sine wave is high enough, the SNR

approaches 107 dB, a value determined hv the finite number of spikes used and

the finite machine precision. Although there is about 10 dB difference between the

SNRs from the numerical evaluation and the approximate equation, the slope of the

curve from the simulation is 20 dB/decade as predicted by Equation 5.8.

Now let us discuss the nonlinearity of the transconductance amplifier Gen

block. An ideal linear Gen block only converts the voltage signal V(t) into the










current x(t). In practice the Gm block shows some nonlinear characteristics and

distorts the current x(t) with some higher-order harmonics which do not exist

in the voltage V(t). For example, the spectrum of x(t) may have 2 fl, 3 fl, 4 fl,...

frequency components although only one frequency fl exists in the spectrum of

V(t). This nonlinear characteristic obviously degrades the ADC performance and

needs to be considered seriously in the circuit implementation. On the other hand,

the anti-aliasing effect of the neuron may attenuate some of those higher-order

harmonics that are higher than the signal band R,/(2xr). This means that the

neuron can tolerate the nonlinearity of the Gm block to some degree. We should

also be aware that in order to fairly characterize the ADC performance, the test

frequency applied should be much less than the signal band R,/(2xr) so that the

effect of the nonlinearities of the Gm block is considered in the measurement.

5.3.2 Leaky Integration of the Integrator

As mentioned in Section 5.2 a transconductance amplifier Gm block is used to

convert the voltage input signal V(t) to the current signal x(t) which then charges

the capacitor to implement the integration operation. As shown in Figure 5-3, the

transconductance amplifier has finite output resistance R which results in a leaky

integration. We must consider its effect on the reconstruction. The integration

operation is described by


C/ = GmV(t) -= Gm(V(t) )(5.9)
dt R ADC

where ADC = GmR is the DC voltage gain of the transconductance amplifier. If

we know the exact value of Gm and R we can use the WLPK( method discussed

in Section 4.3.2 to perfectly reconstruct the input signal V(t) from this leaky

integrate-and-fire neuron. However, in practice the output resistance R is usually a

signal- and process-dependent term ro = 1/(Xlbias) and exhibits some nonlinearity

and unpredictability. Furthermore, since the reconstruction performance is sensitive










) t(V


)t(X


G \L Vc



R -- C





Figure 5-3: Schematic of the leaky integrator

to the accuracy of the estimation of the output resistance R, it is difficult in

practice to have satisfactory reconstruction performance by applying the WLPK(

method to this leaky neuron. Therefore we may prefer to treat this neuron as

an ideal integrate-and-fire neuron during reconstruction and investigate the

performance limitation due to the leaky integration.

If we can calculate the exact value of the leaked charge over each integfra-

tion period, we can obtain the actual integration value of the input signal and

mathematically perfect reconstruction of the signal. It is helpful to estimate the

reconstruction performance by investigating the relationship between the leaked

charge variation and the input signal. Let us begin from the simple case that the

input signal V(t) has only DC component Vac. Assuming that the ith integration

period Ti = tie tib is much less than the time constant RC, the variation of the

voltage V, across the capacitor can be approximated as linearly increasing from 0

to Vrey, and thus the leaked charge 60s =R Ts. The,1,, effec of theleakedcharg

is equivalent to adding to the input signal with a constant DC component which

equals to =0 =" .:" This DC c~ompone~nt can be easily removed through

calibration and does not degrade the reconstruction performance. Our intuition

,a- that it is the variation of V(t), or the AC component of V(t), that degrades

the reconstruction performance.










Assuming that 1M and 1M are the values of V(t) and the value of the first-order

derivative V'(t) = at t =tib TOSpectively, and V/t)l does not vary much from tib

to tie, we can approximate the input signal as 1M + V4(t tib) for the ith integration

period. Therefore, from the encoding equation of the leaky neuron we can obtain:
/ iet-ti
Gm V Rt dt
tibl

/Ti RC _

Gm, (TH + Tt)e RCdt

=Gm%~RC(1 e e ) + Gm%~RC(Ti RC(1 e e ))

~- Gm( "---)+GK ) (5.10)
2RC 2 6R2C2

where the Taylor series approximation of e" is used in the derivation. Since we

treat the neuron as an ideal integrate-and-fire neuron, the actual integration of

V(t) over the ith integration period is:


04i = Gm V(t)dt
t ib
/tie
t ib

=' Gm (T +i't)dt

12


Therefore the leaked charge for the ith integration period is:


0i -0 =
2RC 6RC

~ Gm( )Ti +(5.12)
2ADc 6RC

where the approximation is made due to CVey ~ GmW~Ti. Again, the first item in

Equation 5.12 is equivalent to adding a DC component to the input signal which

can be removed through calibration. The second item in Equation 5.12 is due to









the variation of the input signal and is the only source to affect the reconstruction

performance. Therefore, the noise power due to the leaky integration is:

Poois,~leaky = E[(V(t) V(t))2]

G2E[(x(t) x(t))2]
-E [(~ h.L(t)(ei 8 Gm,( )Ti))



-EC~[(~ h (t)( 6 ))2]



(6jRCG ~)2 6 I2 CjL ~
(6ROC )2EV()E[ b() (5.13)


where E[V2 1)l is the power of the first-order derivative of V(t), and the approx-
imation of E[~6] V,6 is made with the assumption that the DC component is
dominant in the input signal. The signal power is:

Psignal = E[(V(t))2]
--E( i)i2

~ -E( A~t)) Vr;)2(5.14)

Finally the corresponding signal to noise ratio (SNR) due to the leaky integration



Psignal
SNVRleaky
Pnoise,leaky
(6RV,3G )2 E[(C As(t))2]
C'2 7~E[V2;(t)] E[C, Af"t)
(6RV,3G )2
(5.15)
c2 7fE[V2"(~









where the approximation is made with the assumption of low oversampling ratio

( -), as w-e discussed in Section 5.3.1.

Equation 5.15 shows the dependence of the SNR on the ADC parameters

and the input signal. The SNR can be increased by augmenting the output

resistance R since the corresponding leaky current is reduced. Smaller E[Vi2(t

i.e., smaller signal variation during the integration period leads to larger SNR.

Equation 5.15 also implies that the SNR is inversely proportional to the signal

amplitude and frequency since the first-order derivative of the input signal V(t) =

A sin(2x ft) is V(t) = 2x fA cos(2x ft). Equation 5.12 shows that shorter integration

period Ti leads to smaller leaked charge variation, and therefore larger SNR.

Since the integration period Ti tm2~" he SNR can be improved with larger

transconductance Gm and DC component Vdc or smaller capacitance C and

reference voltage Vef, which is consistent with Equation 5.15.

In practice, thle average firing ratei fe, = is related to the signald
bandwidth of the ADC and is usually a predefined number. This additional

constraint complicates the choices of the parameters Gm, Vde, C and Vey. For

example, increasing instead of decreasing C is now helpful to increase the SNR

under this constraint. To keep f,,, constant, either Gm or Vde need to be increased,

or Vey needs to be decreased, each of which increases the SNR in a way that

outperforms the decreasing of the SNR due to the increasing of the C. This should

not be interpreted contrary to previous discussions since the condition is changed

due to the additional constraint.

Several simulations are run in Matlab to validate the previous derivation.

Without additional declarations, the parameters of the ADC are: C = 10 pF,

Vey = 2.5 V, Gm = 6.2 uRl-, R = 80 MR, and the signal bandwidth as = 2xr10000

rad/s. The input signal is V(t) = Vdc + A sin(2x ~ft) with a DC component Ec =

0.234 V and a sine wave with an amplitude A = 0.13 V and a frequency f = 1 kHz.










110
105t r;--Numerical evaluation
105 ----- -- -*--Approximate Equation 5.15

100 ------- -- -- 4--4-

95 ::



80

75 ----



60
10~ 10 1

Ouou reitne Om





Figure 5-4: SNR vs. output resistance


In the following figures the solid red line and the dashed blue line represent the

results from the numerical evaluation and the Equation 5.15, respectively.

Figure 5-4 shows the dependence of SNR on the output resistance R. The

equation matches the numerical evaluation very well with a slope of 20 dB/decade

and a maximum SNR difference of 3 dB.

Figure 5-5 shows the dependence of SNR on the sine wave amplitude ,4 with

the signal frequency f = 8 kHz. The equation matches the numerical evaluation

very well with a slope of -20 dB/decade and a maximum SNR difference of 6 dB.

Figure 5-6 shows the dependence of SNR on the sine wave frequency f.

The equation matches the numerical evaluation very well with a slope of -20

dB/decade and a maximum SNR difference of 3 dB.

We may also extend the previous derivation to the case of treating the neuron

as a leaky neuron during reconstruction with the estimated output resistance











i Numerical evaluation
---Approximate Equation 5.15





- *-ri



11I g1 I


85


80


m`75


S70


55
10


102 101
Sine wave amo~litude (VI


Figure 5-5: SNR vs. Sine wave amplitude


Numerical evaluation
-* Approximate Equation 5.15


S75


S70


65


55 L
10


103
Sine wave freauency (Hz)


Figure 5-6: SNR vs. Sine wave frequency










R.,, = (1 + e)R. We can easily obtain the SNR due to the estimation error
by substituting the R with (1 + () R in Eqlua~tion 5 .1. If the estimation error e

is a very small positive number, the performance improvement is very obvious

compared to treating the neuron as an ideal IF neuron during reconstruction.

However, if e is a negative number less than -0.5, the performance is even worse

compared to treating the neuron as an ideal IF neuron during reconstruction since

too much leaked charge is estimated. It is clear to see that the reconstruction

performance is very sensitive to the accuracy of the estimated output resistance if

we treat the neuron as a leaky neuron during reconstruction.

5.3.3 Thermal Noise of the Spiking Neuron

Analog signals processed by integrated circuits including ADCs are ahr-7-1-

corrupted by noise [26, 27]. The effect of noise on the performance of an ADC is so

essential that the ADC is usually characterized by the signal to noise ratio. The

device electronic noise that exists in most integrated circuits includes thermal noise,

shot noise and flicker noise. Both the thermal noise and the shot noise are white

hand noise. Since the thermal noise is a two-sided shot noise [28], their effects

should be similar. In the following discussion we only consider the thermal noise of

the spiking neuron.





(d I I,amp =4kT 7G,,
V(t) X(t) Vc
Gm

-I) .2 = 4kT/R
,2 <-r oT In,reset 0


Figure 5-7: Noise model of the spiking neuron










In the block diagram of the spiking neuron TB-ADC in Figure 5-1 there are

three 1!! lb ~r noise sources: the transconductance amplifier, the comparator, and the

reset transistor. Compared to the noise from the transconductance amplifier, the

noise from the comparator is neglected since the input-referred noise is divided by

the large voltage gain of the comparator. The noise model of the spiking neuron

is shown in Figure 5-7. The thermal noise due to the transconductance amplifier

is referred to as the output current noise with one-sided power spectrum density

(PSD) of ii~,am = 4kTyGm, where k = 1.38 x 10-23J/K is Boltzmann's constant,

T is the absolute temperature in K~elvin, y is the excess noise factor, and Gm is

the transconductance of the amplifier. The output resistance R of the amplifier is

a virtual resistance due to the channel length modulation of the amplifier output

stage and does not provide any thermal noise contribution. The NMOS transistor

il6, is in the triode region most of the time during the reset operation, therefore the

thermal noise due to the formed resistive channel is modelled as the current noise

withone-idedPSD f i,reset = 4kT/R, during the reset operation, where R, is

the drain-source resistance with VDS = 0.

First, let us take a look at the thermal noise due to the reset transistor i E,

Since during the reset time R is much larger than Rm, the formed RC network can

be approximated by the parallel connection of R. and C. The noise current with

PSD of ii~,rese = 4kT/Rm is applied to the RC network and results in the noise

voltage. The noise bandwidth of the RC network is equal to times the cutoff

frequency, i.e.,

BAn,reset =(5.16)
2xrRonC 2 4RmC

Therefore the noise voltage power due to the reset transistor il6, is

kT
V ,?reSet = ii,resetR ,BA~j~ rese = (5.1'7)









which is called "kTC 1!s .s-- or "reset 1!s .s-- and is independent on the value of the

R, of the reset transistor.

We may try to see if we can follow a similar idea to calculate the noise voltage

power due to the amplifier. Since during the integration period Ro;; is much larger

than R, the formed RC network can be approximated by the parallel connection of

R and C. Th osecret ihPS fi,a = 4kTyGm is applied to the RC

network. Since the noise bandwidth is BWa,amp = ~, the resulted noise voltage

power due to the amplifier is V~,amp = 4kT-jGmR2- = T-mR Now we have a

problem with this result. The signal voltage Ve across the capacitor is equal to Vre;

when the neuron spikes and thus the signal power takes on a finite value of V,2, I

the amplifier has an infinite DC voltage gain GmR, based on the above derivation

the noise power would be infinity and the resulted SNR of the spiking neuron

would be equal to zero! This ridiculous result shows that something is wrong with

the previous derivation of the noise power due to the amplifier.

To facilitate the following discussion, typical values of the parameters of

interest are given below: the amplifier output resistance R = 80 MR, the amplifier

transconductance Gm = 6.2 ul-'l, the integration period Ti = tie tib = 20 us,

the reference voltage of the comparator Vre; = 2.5 V, the channel ON resistance

of the transistor Ron = 3.3 ka, the reset time or equivalently the spike width

Treset = tib t(i-1l)e = 1.5 us. The reason why R is much larger than R, is that

R is the output resistance of the amplifier cascode output stage while R, is the

inverse of the transconductance of the NMOS transistor il6, with gate applied with

the positive power supply voltage Vdd. During the integration period the NMOS i E,

is turned off and the corresponding off resistance Ro;; is much larger than R.

Actually the noise power due to white band noise such as the thermal noise

is a function of time [29, 30]. The calculation of the noise power using previous

methods is only valid with the assumption that the steady state is achieved within









the observation time period. For the reset noise, this assumption is valid since

the reset time Treset = 1.5 us is much larger than the RC network time constant

Treset = RonC = 33 ns and the steady state is achieved. However, for the noise due

to the amplifier, the transient response of the noise power needs to be considered

since the integration period Ti = 20 us is even less than the RC network time

constant unit = RC = 800 us and the circuit is far from settled. The governing

equation of the RC network with the current input in,amp(t) and the voltage output


in~amp dVn,amp (t) dVn,ampt) (.8
dt R

Assume the integration period begins at t = 0. The transient response of the

voltage Vu,amp 1) is

Vn,apnap7 eR d-r (5.19)

Then the noise power due to the amplifier in the end of the integration period Ti is


Vn,amp 0"R-rC 2(72


oC2
kTyGmR -2T
(1 -e no ) (5.20)


where R(-r) = 2kTyGm is the two-sided power spectral density of the amplifier cur-

rent noise. If the integration period Ti goes to infinity the noise power approaches

the steady state derived earlier. If th~e integration period Ti is mnuch~ less

than the time constant RC, which is the case here, the noise power due to the

amplifier can be approximated by

2 ~ 2k ITP',mTi
Vm? (5.21)


Noting that the average integration period T, = where Vac is the DC

component or the mean of the input voltage signal V(t), we may further simplify









Equation 5.21 as:
kT 2yVre;
V2 ( (5.22)
~n,amp Vac

The noises due to the reset transistor il1,, and the amplifier are uncorrelated,

therefore the total noise power is equal to the sum of these two noise powers.

Adding Equation 5.17, 5.22, we obtain,


Vn n2,reset n2,amp
kT 2yVre;
(1 + )
C Va 0
kT 2yVre;
( )(5.23)
C Va e

where the approximation is valid due to the fact that y is much larger than 1 and

Vac is usually less than Vrey.

The power of the reconstruction noise due to the thermal noise of the spiking
neuron is:


poseterm,, = E[(V(t) Vi(t))2]

G2 E[(x(t) x(t))2





G2 2VI~ Eh(t)(:)2]

1 2kTye :C h(.4
Gk~ VacE [ A t](.4

The signal power is:


Psignal = E[(V(t))2]

82E[(~ h,(t))2] (5.25)









Finally the corresponding signal to noise ratio (SNR) due to the thermal noise is:

SN~noisePsignal
Perr,noise
H0 0 E[(C As(t))2]
2kTy E[C Af(t)]
(5.26)
2kTy

where the approximation is made with the assumption of low oversamplingf ratio

( -) as we discussed in Section 5.3.1.

Equation 5.26 indicates that increasing the threshold 8 = CVe,, or the DC

component cd of the input signal or decreasing the excess noise factor y are helpful

to alleviate the ADC performance degradation due to the thermal noise. Special

attention should be paid to the reason why a larger Vdc is helpful. Assume 8 and y

are the same, larger cd results in higher average firingf rate or smaller integration

period which indicates less thermal noise power based on Equation 5.21 so that

the SNR is improved. It is interesting to note that the SNR is not dependent on

the t---ransondctance G~m or the output resistance R. As to the R, if R is larger,

the leaky current is smaller, the net current charging the capacitor is larger and

the integration period is smaller. Again, these two effects cancel each other and

the resulting noise power remains the same. As to the Gm, if Gm is larger, the

noise current is larger while the integration period is smaller. These two effects

cancel each other and do not affect the noise power. However, in practical circuit

implementation the excess noise factor is weakly dependent on the inverse of Gm,

therefore a larger Gm should provide better noise performance.

In practice, thle average firing ratei fe, = is related to the signald
bandwidth of the ADC, and is usually a predefined number. Equation 5.26 can be

further simplified as:


SNVRnoise 5.7
2kTy 2kTyGm 5.7









With the constraint of constant f,,,, the input signal power is proportional to

1/G' while the input referred noise power is proportional to Gm/G' = 1/Gm,

therefore a smaller Gm improves the SNR. This should not be interpreted contrary

to previous discussions since the condition is changed due to the additional
constraint.

Simulations are run in Matlab to validate the previous derivation. Without

additional declarations, the parameters of the ADC are: C = 10 pF, Vre; = 2.5 V,

Gm = 6.2 un-l, and the signal bandwidth as = 2xr10000 rad/s. The input signal

is V(t) = Vac + A sin(2x ft) with a DC component Vac = 0.234 V and a sine wave

with an amplitude A = 0.13 V and a frequency f = 1 kHz. The output current

noise with one-sided PSD of ii~,am is generated using the normal distribution

noise function I ,.,,,.1," in Matlab [31]. Let Var, and T, be the variance and the

sampling period of the normal distribution noise, respectively. Therefore the noise

bandwidth is BWI, =~ and the one-sided power spectral density equals to

=2T,Vanr [32]. Figure 5 8 shows the dependence of SN~R on the output noise

current power spectral density (PSD). Since the transconductance Gm is fixed,

varying the excess noise factor y is equivalent to varying the PSD. In the figure

the red solid line, the green dash-dotted line, and the blue dotted line represent

the numerical evaluation results with R = 80 MR and R = 00, and the results

from Equation 5.27, respectively. The two simulated curves with different output

resistances match very well except that the SNR of the curve with R = 80 MR

saturates at around 78 dB due to the leaky integration effect. This verifies that

the SNR is independent on the output resistance. The equation results match

the numerical evaluation results very well with a slope of 10 dB/decade and a

maximum SNR difference of 7 dB.











100
Numerical evaluation (R=80MOhm)
90 --- --- --- Numerical evaluation (R=i nf)
---Approximate Equation 5.27


70 t -

S60 -------- -

z 50 ~ -- -

40 -



20 ---------

10
1-26 1-24 1-22 1-20 1-18 1-16
Noise current PSD (A2/Hz)


Figure 5-8: SNR vs. thermal noise current power spectral density


5.3.4 Signal Dependent Reference Variation of the Comparator

The sampling operation of the spiking neuron TB-ADC is realized using a

comparator in Figure 5-9. When the voltage V, across the capacitor rises above the

reference voltage Vey of the comparator, the output voltage Vo of the comparator

goes high to reach the logic state "1". This rising transition time is the end time

tie of the ith integration period. After some time delay, the capacitor is reset

to ground and the output of the comparator goes low to reach the logic state

"O". This falling transition time is the beginning time t(i+1)b of the (i + 1)th

integration period. These two transition timings and the capacitor voltages at

these two transition timings together describe the sampling operation. For the

ideal case, the output Vo can instantaneously reach the digital logic state when

V, reaches the nominal reference voltage Vre y. In practice, the comparator has a

finite DC gain and a finite bandwidth and needs some time to resolve to the logic

state. For conventional ADCs this results in the metastable phenomena during














V~t)Comp Vo Vref t






th 1l t


Figure 5-9: Signal dependent reference voltage variation of the comparator. High
and low slew rate are shown as solid or dashed respectively


comparison [33, 34]. For TB-ADCs the comparator shows some time delay or

reference variation characteristics. Figure 5-9 illustrates outputs of the comparator

with inputs with different slew rates. Assume when t = 0 the input V, = Vey and

the output Vo = 0 is at the small signal ground. The comparator resolves to the

logic state when Vo reaches Vd, and the value of V, at this moment is defined as the

effective reference voltage of the comparator, and correspondingly the del li time is

defined as the time that the comparator needs to take from Vo = 0 to Vo = Vd. We

can see that the input with higher slew rate (solid line) has a shorter time delay

(th < tl) and a larger actual reference variation (Ve y~h > Vent) than the input

with lower slew rate (dashed line). This signal-dependent time delay or reference

variation degrades the ADC performance and its effect needs to be investigated.

Assume the comparator can be modelled as a one-pole system with the

transfer function
Vo ( s) Ae
(5.28)
Ve (s) 1 + a-re
where Ae is the DC voltage gain and -r, is the time constant. Assume the input

V, = Vey and the output Vo = 0 when t = 0, and the input signal V(t) = V(t=

tie) = 1K during the comparison period which is usually very short compared to the










period of the signal. Thus V, can be expressed by


Vc (t)= Key + (5. 29)


where Gm is the transconductance of the transconductance amplifier. Actually

the slew rate of the c~omparator input Vc is equal to which is proportional

to the input signal value 1M. Therefore it is equivalent to ;?-, larger input signal

value 1W to the ADC or higher slew rate of the input to the comparator. We

also assume that when the time delay t equals to td, the output Vo(t) reaches Vd

and the comparator resolves to the logic state. From the above assumptions and

Equations 5.28, 5.29, we can obtain

AcGmM t
Vd = td rc (1 e )) (5.30)


and therefore the actual reference voltage variation is


Vref,act Vrey = C(5.31)


Equations 5.30, 5.31 show that the time delay td and the reference variation

Kref~act Vref are dependent on the sampled signal value 1K. It is necessary for us

to differentiate between two scenarios: lower or higher slew rate input Vc to the

comparator, or equivalently smaller or larger input signal 1K to the ADC.

Lower slew rate comparator input Ve, or smaller ADC input signal

M.If the input signal 1K is very small, the slew rate of the input to the compara-

tor is small, or equivalently the comparator is relatively very fast, the comparator

can respond quickly to the input. In this scenario, the time delay ta > -r, and we

can calculate the time disi-i and the reference variation from Equations 5.30, 5.31

as:
C V,
ta,l = + e (5.32)
AcGm%~










Ket-Ky= + (5.33)
Ae C

Equation 5.33 shows that the effective refelrnc~e voltage is rKey + + ij atl

the end time tie of the ith integration period. Since Vent is dependent on the signal

value 1K = V(t = tie) and cannot be obtained before reconstruction, we have to use

an iterative method to perfectly reconstruct the signal V(t). However if we take a

closer look at Equation 5.32, 5.33, we mray: remove thle signal dependent termrl~

from Equation 5.33 and -r, from Equation 5.32, and treat the new actual reference

voltag~e as 1'ey + w zhile the end timne of ith integration period is iie 7e. In1 this

way, if we know exactly the parameters such as Vey, Vd, C, Gm, -re, and Ac, we could

perfectly reconstruct the input signal V(t) using the WLPK( method discussed in

Section 4.3. However in practice the comparator cannot be fully characterized by

Equation 5.28 with constants Ae and -re. The incorrect estimation of Tc, unavoidably

introduces some error into the reconstructed signal, although the error is predicted

to be reduced by increasing the comparator speed. With the assumption that

the time delay is much larger than the time constant, the comparator needs very

high speed and consumes very large power and is not a good choice for low power

applications .

Higher slew rate comparator input Ve, or larger ADC input signal 1M.

If the input signal 1K is very large, the slew rate of the input to the comparator is

high, or equivalently the comparator is relatively very slow, the comparator cannot

respond quickly to the input. In this scenario, since the time delay ta
ex ~1 +x + for x

C Tc 27c,

d (5.34)
2C-rc









And the time delay is then:
2CVa-re
td,h = (5.35)

From Equation 5.31, 5.35, we obtain the actual reference voltage variation as:


Vref,h Vrey = AC(5.36)


Equation? 5.36 shows thaRt the actual refereceC voltage is 1Key~ + 2V ~mCi
at the end time tie of the ith integration period. The ADC performance is largely

degraded due to the signal dependent reference variation. In practice the DC

component of the input signal can be easily measured, and the time delay asso-

ciated with the DC component can be obtained before signal reconstruction as

t aac = If the time delay of the DC component is considered in the

reconstruction, better reconstruction performance is expected.

We may follow the method in Section 5.3.1 to calculate the SNR due to the

signal dependent reference variation. The actual integration of the input signal

V(t) for the ith integration period is:


GmV(t)dt $; GmV(t)dt /tedd GmV(t~dt

~V 8i Gmlbia,ac (5.37)


where the approximation is made with the assumption that V(t) does not vary too

much for the short period from t = tie ta,dc to t = tie. However, the nominal

integration 8 = CVey is used in the reconstruction and this threshold error

accounts for the performance degradation. The threshold error due to the signal

dependent reference variation is:


8i Gml~ta,ac H = C~ref,h Gml~ta,ac Chref
2VdCGmM~-c 2CVa-re
Ae AcGmVac









where k = 2VaTm~ foT Simplification. Wlie can see that the threshold variation

equals to zero if the ADC input signal V(t) = Vac. The noise power due to signal

dependent reference variation is:


Pooise,comp = E[(V(t) V(t))2]

G2 E[(x(t) x())2]




Umii
whee te oeficint kiandk2Wil b cl ulae ae.W a ra sa
ideticl idepndetly distributed rado vralewi~~ch sunfrlydsriue
insgalrgon[,b]weea n aete iiu adte aiumo h
signl. W canobtin te folowig expect vaues


a+b
=Vac
2
b1.5 a1.5
1.5(b a)
b2.5 a2.5
2.5(b a)
b3 a3
3(b a)


(5.40)


Therefore the coefficients kl and k2 in Equation 5.39 are calculated as below:

E[(A ~)2

4(m3 1)4/(2.5 _1
=1+-
3(m 1) (m + 1)2 2.5(m 1) (m + 1)15


k2 "~


E [N]

E [Vo0.s

E [V .s"

E [ ~2]











- k


- 106


108


10-12


rn = bla


Figure 5-10:
tion


Plots of coefficients C1 and C2 for signal dependent threshold varia-


(5.41)
m+1

where mb = is a numberr largetr than 1. Figure 5-10 shows Ithe plots of kl and

k2 foT m Varying from 1.01 to 10. kl and k2 quickly decrease as m approaches 1,

or equivalently the variation of V(t) decreases. k2 is much smaller than kl and

therefore can be neglected in Equation 5.39. We can further simplify Equation 5.39

as:

nooise,comp- E G() Vc(.2

The signal power is:


= E[V2 (~


(5.43)









Therefore, the signal to noise ratio (SNR) due to the signal dependent reference

variation is:

Psignal e2 E [(Ci hi (t) )2] iTTCV2 fu iTVredsu
SR- ~~ U1 jlVdVeG ~vfv (5.44)

where the approximation is made with the assumption of low oversampling ratio

( "~~) asg we discussed in Section? 5.3.1,i f,,,, ="l is the~ ave1rage firing rate of

the neuron encoder, ~f, =~ is the unity: gain fr-equency of the comparator, and

kl is a coefficient determined by the input signal range as shown in Figure 5-10.

In order to improve SNR, we can either increase the reference voltage or the unit

gain frequency of the comparator, or decrease the comparator output voltage swing

needed to reach the logic state or the average firing rate. There are many tradeoffs

when selecting these parameters. Larger Vey worsens the SNR due to the leaky

integration as we discussed before. Larger f, means that the comparator needs to

consume more power. Smaller output voltage swing vd of the comparator means

that the noise margin is reduced and therefore more sensitive to noise.

Simulations are run in Matlab to validate the previous derivation. Without

additional declarations, the parameters of the ADC are: C = 10 pF, Vre; = 2.5 V,

Gm = 6.2 uRl-, R = 80 MR, the comparator output voltage swing Vd = 0.7 V,

the comparator DC gain Ae = 109, and the signal bandwidth as = 2xr10000 rad/s.

The input signal is V(t) = Vac + A sin(2x ~ft) with a DC component Vac = 0.234

V and a sine wave with an amplitude A = 0.13 V and a frequency f = 1 kHz.

Fr-om the distribution of the signal V(t) we can calculate the coefficient kl = 0.025.

The plot of SNR vs. the comparator time constant is shown in Figure 5-11. The

solid red line and the dashed blue line represent the results from the numerical

evaluation and the Equation 5.44, respectively. When the time constant is less than

100 ns, the SNR from the numerical evaluation deviates from the prediction of

the equation. This is because the delay time td is not less than the time constant










65
Numerical evaluation
--Approximate Equation 5.44
60 --- ----- ; i c i i ct c




55




45 -- -. ++.9-
II

r~rr llrr~r~rrI \llr



35 L
10 107 106 105 104
Comparator time constant (s)


Figure 5-11: SNR vs. comparator time constant


and the assumption of Equation 5.44 is no longer valid. Overall, the numerical

evaluation results support the prediction of the equation very well.

Power consumption limitation. It is ah-li-w of interest to investigate the

minimum power consumption needed for acceptable ADC performance. If the ADC

input is a current signal and the transconductance amplifier is not needed, most

ADC power is consumed by the comparator. We may find this power limit from the

relationship between the comparator unity gain frequency and the SNR as shown in

Equation 5.44.

If we assume that the input stage of the comparator is realized with a dif-

ferential MOS transistor pair working in the square-law region, the comparator

transconductance gm,comp can be expressed as:


gmLcom1pP = ~~lj


(5.45)










where Ibias iS the total bias current of the differe~ntial pair and i3 = pCom4 is

only determined by the size of the transistor and the VLSI technology process

parameters. The unity gain frequency f, of the comparator is


f, = (5.46)
o,comp

where Co,comp is the output capacitance of the comparator. Substituting Equa-

tions 5.45, 5.46 into Equation 5.44, we can obtain

iTVret0~L~
SNVReo (5.47)
mp kVdCo,comp avg

Therefore we establish the connection between the SNR and the bias current, or

equivalently the power consumption of the comparator, and may theoretically esti-

mate the minimum necessary bias power consumption for some specific SNR. We

should also be aware that the total power consumption of the ADCs also includes

the dynamic power consumption and the short-circuit power consumption, which

are not considered in Equation 5.47. Generally speaking, with the assumption that

the time delay is much less than the time constant, the comparator does not need

high speed and therefore consumes less power making it suitable for low power

applications .

5.4 Practical Issues Related to Reconstruction from Spiking Neuron
Models

For conventional ADCs, performance is only determined by the encoding and

digitization circuitry. However for the case of time-based ADCs, the additional

DSP reconstruction component also pil- a very important role in determining

the ADC performance as shown in ChI Ilpter 4. We need to consider effects of

some nonidealities on the performance of the reconstruction. In practice the time

quantizer can be put either in the ADC front end with the spiking neuron encoder

together, or in the ADC back end with the DSP reconstruction algorithm. To









further reduce the power consumption in the frontend the latter is preferred and

therefore the discussion of time quantization is included in this section.

5.4.1 Timing Jitter of the Time Quantizer

The timing of the output spike train of the spiking neuron encoder is still

in analog form and must be digitized to be processed by a DSP. This is usually

done by synchronizing the spike train to a fast clock and recording the quantized

time stamp. This synchronization will introduce some time jitter to the recorded

arrival timings (tib and tie) of each spike. The effect of the timing jitter degrades

the reconstruction performance and needs to be investigated.

We assume that the timing jitters associated with the original spike timings

tib and tie are nib and nie respectively, which are independent identical random

variables uniformly distributed in [-Te/2, Te/2] where T, is the clock period of

the quantization clock. The actual recorded beginning and ending time of the ith

interspike interval are

tib = ib + ib (5.48)

tie = tie + nie (5.49)

If we: knowz the: exact vanlue: O = Gmti fe (t)dtl we- can Irewirit Eqluaioiin 4.9 asq
follows

V~t) Ast)04(5.50)

where Aslt) is calculated based on the recorded spike timing tib and te. However,

due to the noisy nature of the recorded spike timings we cannot obtain the exact

value of Os, but only use the encoding eqluation B = Gm, f;e Vi(t)dt to obtain the
reconstructed signal as

V~t)= 1 ~ t)0(5.51)

Thus the difference between the input signal V(t) and the reconstructed signal

V(t) represents the error due to the timing jitters which obviously degrades the










reconstruction performance. We can calculate (8i 8):


04 8 =- G V(t)dlt Gm,, V(t)dtl
Lib ib



=GmV(te)(te tie) GmV(tAb) ib tib)

=GmV(te)nie GmV(tib)nib (5.52)


where for the third equation we assume the timer clock period T, is much less than

the Nyquist period T = xr/R,, and the signal V(t) is approximated by a constant in

the very small time intervals [tie, tfie] and [tib, tib -

The power of the reconstruction noise due to the timing jitter of the quantiza-
tion clock is:


poise, jitte = E [( V(t) V (t)) 2



= E[ h ()(Vtie~ie -V~tb)Ei 2](5.53)


Since nib and nie are independent identical random variables, we have



Tc2/12 :V


F [o, a ] 0 V, j(5.54)

After further simplifying Equation 5.53 we can obtain the noise power:


ploise, jitter = E [h, (t)] (E [V2 ie)]+ E [V2 ib,) ) 2 /12z

=L E[ Afi t)]P1signa c2/6 5.5


Therefore the corresponding signal to noise ratio (SNR) due to timing jitter is:


SNVRjitter = Psignal
Pooise,jitter












E [(E A(t)),2 c

602
GLPsignalff



(5.56)

where the approximation is made with the assumption of low oversamplingf ratio

( ~~P) als weC discussed in Section 5.3.1,l the D)C component Vac is dominant in the

signal V(t), and the average firing rate few,, = ~~
From Equation 5.56 we can see that the SNR is inversely proportional to the

average firing rate face, which is reasonable since the same amount of timing jitter

disturbs the spike timings with smaller interspike interval to a much worse degree.

We can also see that the SNR is inversely proportional to the clock period with

a slope of 20 dB/decade, which can give us some hints to determine how fast the

digital synchronization clock must run in order to achieve particular levels of SNR.

Figure 5-12 shows a plot of SNR vs. the simulated clock period for the same

random noise input used in Figure 4-2. When the clock period is less than 1 ns,

the timing jitter noise is not the dominant error source and the reconstruction

SNR saturates to a value determined by the calculation roundoff errors. When the

clock period is large enough, the timing jitter noise degrades the SNR with a slope

of approximate 20 dB/decade clock period. The the numerical evaluation results

verify the prediction made by Equation 5.56.

5.4.2 Kernel Selection of the DSP Reconstruction Algorithm

The low-pass kernel pha7i~ a very important role in the DSP reconstruction

algorithm. In Section 4.3 the ideal low-pass kernel h(t) = sin(Rst)/(aS2t) is used

to mathematically reconstruct the signal. In practice we cannot implement perfect










120r
d Numerical evaluation
110 Ap proxi mate Eq uati on 5.56




1060 --

50 -- --i -r~


40 -- L LU IIII IIIII
IILIILIIIIIII



30 I lllnlr rrrTT TIIII I IIII

20
10-10 10-9 10-8 107 10-6 10-s
Clock period (s)


Figure 5-12: Plot of SNR vs. clock period used in reconstruction


reconstruction due to nonidealities and therefore different kernels need to be

investigated.

One assumption of the perfect reconstruction in the WLPK( method is that

the kernel h(t) and the signal V(t) are infinitely long in time and an infinite

number of spikes are available. However, due to storage limitations, computation

complexity limitation, and real-time requirements, a window-based reconstruction

is needed. In each time window, only a finite number of spikes can be processed

to reconstruct a finite length of the signal. Correspondingly the low-pass kernel

h(t) used is truncated and has only finite length, which introduces some truncation

error in the time domain and some non-ideal low-pass filtering performance in the

frequency domain. The magnitude of the Sinc kernel with the length of 60 Nyquist

periods is shown in Figure 5-13. We can see that the magnitude decays very slowly

in time and the maximum truncation error can be as large as -40 dB which is

not negligible. Since the truncation error is dependent on the signal length, the












-0




-a -2 0 - -- -- -










-30 -20 -10 0 10 20 30
Kernel length (T)


Figure 5-13: Plot of Sinc kernel vs. kernel length


performance of the reconstruction should also be dependent on the signal length

used in the reconstruction.

Figure 5-14 shows the plot of SNR using Sinc kernel vs. signal length used in

the reconstruction. A Gaussian random noise signal bandlimited to [-3000xr, 3000xr]

is input to an integfrate-and-fire neuron. The average firingf rate is 14 kHz. Since

the maximum .Il11 Il:ent spike interval (0.162 ms) is less than the Nyquist period

T = 1/3 ms, the WLPK( method is used to reconstruct the input signal from the

spike train. We can see that the signal to error ratio (SNR) is strongly dependent

on the signal length. When the signal is about 20 Nyquist periods long the SNR

varies between 80 dB and 100 dB, while when the signal is about 120 Nyquist

periods long the SNR varies between 106 dB and 116 dB. It can be observed that

the mean value of the SNR increases and the variation of the SNR decreases as

the signal length used increases. The SNR variation is very sensitive to the signal











120


110-


100 ---


90 -0


Z 80


70-


60


50
0 20 40 60 80 100 120
Sianal lenath (T)


Figure 5-14: Plot of SNR using the truncated Sinc kernel vs. signal length used in
the reconstruction


length. In order to have a large SNR with small variation, we need to use a very

long signal length.

Gaussian kernel. To reduce the truncation error and the dependence of

the SNR on the signal length, we need the kernel to have a fast time decaying

property and a good low-pass filtering characteristics. The Gaussian kernel is a

good candidate and is shown below:


h, (t) = e- 20 (5.57)


A Fourier transform is needed to find the relationship between the cutoff frequency

fe and a. The Fourier transform of Equation 5.57 is:


Hg(f) = e- 22 2e-ja~rftd

/"~ 1 -

= Ave--"2x f" (5.58)













-20 -c i

-40 -







-12 -- -- -- --



-140

-102 -1.5 -1 -0.5 0 0.5 1 1.5 2
Kernel lenath (T)


Figure 5-15: Plot of Gaussian kernel vs. kernel length


Fr-om Equation 5.58 we can find the 3-dB cutoff frequency:


fe = 0.84(5.59)


Figure 5-15 shows the magnitude of the Gaussian kernel with the length of 4

Nyquist periods. The Gaussian kernel only needs 1.25 Nyquist periods to decay

to -40 dB level while the Sinc kernel needs 30 Nyquist periods in Figure 5-13.

The Gaussian kernel has much faster time decaying property and less truncation

error than the Sinc kernel, and therefore the signal reconstruction SNR should

be less dependent on the signal length. Figure 5-16 shows the plot of SNR using

Gaussian kernel vs. signal length used in the reconstruction. The input signal and

the integrated-and-fire neuron are the same as those in Figure 5-14. The cutoff

frequency f, = 1500 Hz, and therefore a = 0.1874/f, = 12.5 ms. For the signal

length shorter than 26T, the variation of the SNR is very large. However, for a

signal length longer than 26 T the SNR increases slowly from 114 dB to 120 dB

with very small variation. Compared to the Sinc kernel, signal reconstruction using











130


12 0 - - -


1 10 -- -- --


10 0 -- --


90


80 -


70
0 10 20 30 40 50 60
Signal length (T)


Figure 5-16: Plot of SNR using the truncated Gaussian kernel vs. signal length
used in the reconstruction


the truncated Gaussian kernel is less dependent on the signal length, and therefore

shorter signal length can be used in the reconstruction.

Computation cost. Aside from the signal to noise ratio of the recon-

structed signal, another criteria to evaluate the performance of the spiking neuron

TB-ADC is the computation cost. Since the TB-ADC trades off simpler analog

circuitry for more complex digital circuitry, the computation burden is put on the

DSP reconstruction algorithm. Computation resources are not free and should be

considered in practice. One computation cost is the storage needed for the compu-

tation. To reduce the cost of the memory, smaller storage is preferable. Another

computation cost is the required FLOP rate of the DSP which is usually specified

by the number of floating-point operations per second (FLOPS). FLOPS is a com-

mon benchmark measurement for rating the speed of microprocessors in DSPs. A

lower FLOPS number implies that slower microprocessors can be used which lowers

the cost. Since multiplies and divides are typically more time consuming than











Gaussian Gausslan
0.8 -- -n0. -- -S n


~0.4 -- 0.4 ----------- -



-0 .2 - - - --0 .2 -

-0.40 0 4 0 8 0 0 20 40 60 80 100
Index of the 20th row vector of the matrix G Index of the 80th row vector of the matrix G

(a) (b)

Figure 5-17: Plots of the row vector of the matrix C using Sinc and Gaussian ker-
nels. (a) 20th row. (b) 80th row


addition and substraction in DSP, only the multiplies and division are considered

as floating-point operations in this analysis.

Since most computation is spent on solving linear equations to calculate the

weights in Equation 4.8, only this computation cost is considered. Assume the

coefficient matrix C is a 1Vx NV matrix, and the weight vector W and the charge

vector 8 are NVx 1 vectors. It is good to check if the elements of the matrix C have

some special properties so that the computation can be simplified. Figure 5-17

shows the elements of the 20th (a) and 80th (b) row vectors of the matrix C with

NV = 100 using Sinc and Gaussian kernels. It is interesting to note that the curve

shape is not exact, but similar to the shape of the respective low-pass kernel used

in the reconstruction. This is because the element cy =J h.(t sj)dt is the

integration of the respective kernel over the ith integration period. The curve shape

of different rows are generally similar except that the peak locates in different

columns that are equal to the respective row numbers. For example, the peak of

the 20th row locates in the 20th column while the peak of the 80th row locates in

the 80th column. Due to the fast time decaying of the curve of the row vector of

the matrix C using Gaussian kernel, most elements are very small and negligible.










Therefore the matrix C is approximately a banded matrix with elements centered

around the main diagonal. The bandwidth M~ of the matrix C is defined as the

number of non-zero elements in each row of the matrix C. The number M~ is

determined by the product of the average firing rate f,,, and the Nyquist period

T, and is a much smaller number, wi 15, than the dimension NV of the matrix C if

the oversampling ratio is not high. The matrix C using the Sinc kernel is usually

a matrix with a full bandwidth, i.e., M~ = NV, due to the slow time-decaying of the

Since kernel.

Therefore the computation storage of the reconstruction using the Gaussian

kernel is NVx M~, and is much smaller than that of the reconstruction using the Sinc

kernel which is NVx NV. The computation complexity is estimated using Gaussian

elimination [21, 22]. The number of floating-point operations of the computation

of the matrix C using Gaussian kernel is NM12 4 COnSidering its banded property,

while that of the matrix C using Sinc kernel is N3"/3. Assume the computation

time is tcomp, the required FLOP rate of the DSP for the reconstruction using the

Gaussian kernel is
NM12/
FLOPSG,,,,e, = (5.60)
comp
The required FLOP rate of the DSP for the reconstruction using the Sinc kernel is

NV3/
FLOPSsie (5.61)
comp

Since the matrix bandwidth M~ is much smaller than the matrix dimension NV,

the required FLOP rate of the DSP of the reconstruction using Gaussian kernel

is much less than that of using Sinc kernel. If the SVD-based pseudo-inverse

conditioning technique is used in solving the weights, the number of floating-point

operations for using Gaussian kernel or Sinc kernel is on the orders of NV2M or NV3

respectively [35].










Windowing. In many applications such as remote ;1 ,01.r the TB-ADC

needs to perform real-time analog-to-digital conversion. Therefore the DSP

reconstruction algorithm needs to be implemented in a window-based form.

The whole signal is reconstructed by piecing together signals respectively

reconstructed in each time window. Figure 5-18 shows this windowing scheme.

Since the reconstructed signal on the side of each window is prone to the kernel

truncation error and accounts for most reconstruction error, we usually discard

a small percentage, ;?i 10'; of the signal on the side of each window (the blank

region in the figure), and therefore only keep H I' of the reconstructed signal

(the shadowed region in the figure). Assume at t = t4 the buffer receives the

complete spike train of the first window WINIV which spans from to to 4 and the

algorithm begins to perform the reconstruction. Meanwhile, the spike train for the

second window WIN2~ begins to be stored in the buffer. At t = t7 the algorithm

finishes the reconstruction of the window WINIV and outputs the reconstructed

signal from 1 to 3. In the meantime, the buffer receives the complete spike train

of the window WIN2~ Which spans from 2 tO t7. The algorithm then begins to

perform the reconstruction for the window WIN2~, and the buffer begins to store

the incoming spike train for the third window WINV3. At t = tlo the algorithm

finishes the reconstruction of the window WIN2~ and outputs the reconstructed

signal from 3 tO t6. The algorithm begins to reconstruct the window WINV3 and

the buffer begins to store the spike train for the fourth window WINV4, and so on.

In this way, the signal can be reconstructed in realtime with some latency.

We have two choices of the window definition: constant time window or

constant number of spikes window. If the average firing rate f,,, in each window

is similar, the difference between these two definitions are small and we use the

definition of the constant number of spikes window. Assume the number of spikes

in each window is NV, and then the time interval for each window is N/ f,,,. From







67


L. I KEPT

WIN1I DISCARDED





~t~-- WIN3


WIN4
to tl t2 t3 t4 ts t6 t7 ts t9 tlo t


Figure 5-18: Windowing scheme of the DSP reconstruction algorithm


Figure 5-18 we can obtain the time del li of the reconstruction

0.9NV
tdere, = t7 t3 = (5.62)


The computation time for the reconstruction of each window is tcomp =7 4

0.8N/ f,,,. Therefore from Equations 5.60, 5.61 we can calculate the required

FLOP rate of the DSP for the reconstruction using Gaussian kernel

NM1\2 3
FLOPScoussi, = (5.63)
0.8N/ f,,, 3.2

The required FLOP rate of the DSP for the reconstruction using the Sinc kernel

N3/ fat 2
FLOPSsine= (5.64)
0.8N/ f,,, 2.4

The selection of the number of spikes NV in each window is a trade-off among

the signal to noise ratio (SNR), the time delay, and the computation cost. Larger

NV, i.e., longer signal length used for reconstruction, results in larger SNR with

smaller SNR variation as we discussed in Figures 5-16, 5-14. Larger NV increases

the reconstruction delay and worsens the real-time performance as shown in

Equation 5.62. Larger NV increases the requirement of the computation storage,

and also increases the required FLOP rate of the DSP for reconstruction using Sinc









Table 5-1: Performance comparison of the reconstruction using truncated Gaussian
kernel and truncated Sinc kernel

Kernels Gaussian Sine
SNR Figure 5-16 Figure 5-14
Time del I\ 0.9N/l f,, 0.9N/ fa,,
Computation storage (Bytes) 4NV x M~ 4NV x NV
Required FLOP rate of the DSP (FLOPS) f,g:.1f2/3.2 f,,r N2/2.4


kernel as shown in Equation 5.64 however has no effect on the required FLOP rate

of the DSP for reconstruction using Gaussian kernel as shown in Equation 5.64. In

practice we check the Figures 5-16, 5-14 to find the minimum NV while still having

acceptable SNR. Since the reconstruction using Gaussian kernel is less sensitive

to the signal length than the reconstruction using Sinc kernel, we can choose a

smaller NV for the reconstruction using Gaussian kernel. Table 5-1 summarizes the

performance comparison of the reconstructions using the truncated Gaussian kernel

and the truncated Sinc kernel. The data are assumed to be stored using single

floating point resolution (4 Bytes).

It is of interest to put some realistic numbers in Table 5-1 so that we can

clearly see the performance improvement for the reconstruction using the truncated

Gaussian kernel. We use the same simulation data as that used in Figure 5-14.

The average firing rate f,,, = 14 kHz, the Nyquist period T = 1/3 ms. We want

to have the SNR of the reconstruction larger than 100 dB. We can estimate that

the minimum signal length for Sinc kernel is 120 T, or the number of spikes in each

window is NV = 120T f,, = 560, to achieve 101 dB SNR from Figure 5-14. We can

also estimate that the minimum signal length for Gaussian kernel is 30 T, or the

number of spikes in each window is NV = 30T f,,, = 140, to achieve 114 dB SNR

from Figure 5-16. The bandwidth of the matrix C for Gaussian kernel is M~ = 15

from Figure 5-15. Therefore the performance comparison of the reconstructions

using the truncated Gaussian kernel and the truncated Sinc kernel for 14 kHz









Table 5-2: Performance comparison of the reconstruction using truncated Gaussian
kernel and truncated Sinc kernel for 14 kHz average firingf rate spike train

Kernels Gaussian Sine
SNR (dB) 114 101
Number of spikes per window 140 560
Matrix bandwidth 15 560
Time delay (ms) 9 36
Computation storage (Bytes) 8400 1254400
Required FLOP rate of the DSP (FLOPS) 1 x 106 1.8 x 109


average firingf rate is shown in Table 5-2. The Gaussian kernel outperforms the

Since kernel in every aspect in the table.

5.5 Discussion

In this chapter we discussed effects of some nonidealities on the performance

of the spiking neuron TB-ADC. For the spiking neuron encoding component

we considered the frequency aliasing of the input signal, leaky integration of

the integfrator, thermal noise of the spiking neuron, and the signal dependent

reference variation of the comparator. For the DSP reconstruction component,

we considered the timing jitter of the time quantizer, the kernel selection and the

windowing of the DSP algorithm. We estimated the signal to noise ratio due to

some nonidealities in Equations 5.8, 5.15, 5.27, 5.44 and 5.56 and summarized them

in Table 5-3. There is another constraint for the ADC parameters related to the

average firingf rate which is shown in equation below:


favs (5.65)


The average firing rate f,,, is related to the signal bandwidth and is a predefined

number during ADC design. This constraint complicates the choices of C, Ve,,f

Gm and Vd, since increasing one of them requires the corresponding changes of the

others. Tradeoffs during ADC implementations are made based on Table 5-3 and

Equation 5.65 together.









Table 5-3: Signal to noise ratio due to different noise sources

Noise source Signal to noise ratio (SNR)

Fr-equenc~y aliasmg ff

Leaky integration (y Edk (t)]

Thermal noise c y ,fav

Signal dependent reference variation 11_
Timing jitter ~~


Reducing f,,, is helpful to reduce the effect of the errors due to signal depen-

dent threshold variation of the comparator and the timing jitter of the quantization

clock, at the cost of performance degradation due to the leaky integration and the

thermal noise of the transconductance amplifier. Increasing the transconductance

amplifier output resistance R, the capacitance C, the reference voltage Vre y, the

unity gain frequency of the comparator f, are generally helpful to reduce the effects

due to different error sources, however the cost is that more power needs to be

consumed and more chip layout area is used. Decreasing the yGm, or equivalently

decreasing the output referred noise current power spectral density, can reduce

the effect due to thermal noise of the transconductance amplifier. Decreasing

the transconductance Gm widens the linear input region of the transconductance

amplifier and reduces the nonlinearity distortion if the input signal is kept the

same. However, it is not the case here since with the constraint of constant f,,, we

need to apply a larger input signal, and therefore the reduction of the nonlinear

distortion is not that obvious. Smaller comparator output voltage swing Vd or time

quantizer period T, can also obviously improve the ADC performance.















CHAPTER 6
IMPLEMENTATION AND TEST OF AN SPIKING NEURON CHIP

6.1 Introduction

In this chapter we present the circuit implementation of the spiking neuron

TB-ADC. We consider the practical issues discussed in OsI Ilpter 5 and make

some tradeoffs during the implementation. The performance of the neuron chip is

determined using the 4-parameter sine wave fitting method test and the histogram

test method.

6.2 Circuit Implementation of the Transconductor

As we mentioned in OsI Ilpter 5 the transconductance amplifier in Figure 5-1

converts the voltage signal to a current signal. Some nonidealities of the amplifier

such as the nonlinearity, the finite DC gain and the thermal noise affect the

signal to noise ratio of the ADC and need to be considered during the ADC

implementation. More specifically, we need to widen the linear input region,

increase output resistance and reduce the output referred noise current.

Figure 6-1 shows the implementation of the transconductance amplifier [36].

The amplifier uses the source degeneration technique to widen the linear region of

the transconductance Gm. The degeneration resistor is realized using two coupled

PMOS transistors M5 and M6 working in the triode region [37]. Two negative

feedbacks formed by M3 and M7, M4 and M8 respectively improve the linearity by

forcingf the sources and drains of M5 and M6 to be virtual ground. The differential

input pair M1 and M2 provides some attenuation so that the linear region is

further widened. A DC offset current lac controlled by a PMOS transistor M15 is

added at the output to set the average firing rate of the ADC. Compared to the

method that directly applies a large DC offset voltage at the inputs 1M and 1M_,


































Gnd


Figure 6-1: Schematic of the transconductance amplifier

this method saves some linear region for the AC voltage signal. The cascode output

stage is used to increase the output resistance. As a first-order approximation, the

transconductance Gm can be calculated as:


Gm =4gm,6~
9m,4



2Is1p,Com(W/L)2
=4(W/L)6 (6.1)
(W/L),(W/L)4

where gm is the transconductance of each respective transistor, (W/L) is the

transistor size ratio, Im1 is the bias current through M9 or M10, p, is the electron

mobility for NMOS transistors, and Com is the oxide capacitance. It is also of

interest to estimate the input and output common mode voltage ranges since we









need to make sure all the transistors except M5 and M6 work in the saturation

region. The input common mode voltage range is


Input range = [Vasat,o + Vdsat,2 + VTN, Vdd | Vdsat,4 | | Vasat,s|I 2| VP p| + VTN] (6.2)

The output common mode voltage range is


OUtpUt range = [Vdsat,12 + Vdsat,14, Vdd | Vdsat,4 | | Vasat,s | | Vr P | (6.3)


where Vdase is the minimum drain and source voltage to keep the transistor in

saturation region, Vrp is the threshold voltage for PMOS transistors and VTN is the

threshold voltage for NMOS transistors. Due to the level shifting provided by two

bypass PMOS transistors in the implementation of the neuron circuit, the output of

the amplifier does not need to be pulled to ground when the capacitor is reset.

We may also need to estimate the output referred noise current power spectral

density (PSD) i ~,am = 4kTyGm so that we can know how to optimize the noise

performance with other tradeoffs. The output referred noise current PSD due to

M1, M2, M3 and M4 is:

.2 ~ k72 gm,2 9m,4 (J~1) 2 6l
nM--43 9m,4

The output referred noise current PSD due to M5 and M6:


i ,M,6: = 2(2i,,nM6 2 = 2 x 4 x 4kTgm,6. (6.5)

The output referred noise current PSD due to M9, M10, M13, M14 and M15 are
simply 4kT'2 gm where g i the transconductanceof each transistor Alote

transistors in Figure 6-1 contribute negligible noise power and thus are neglected in

the noise analysis. Therefore the total output referred noise current is:

." 64(m,~2 9m,4 9m,6 4,B 4 2
,,,am = kT((8 + 2% ).m,6f 9gm,10 g9m,14 f 915) (6i.6)










For transistors working in the square-law above-threshold region, there is a

tradeoff between the transconductance gm and the saturation voltage Vdase which

follows the equation "g = where Ig is the drain current in the equilibrium

state. It is helpful to improve the ADC noise performance by increasing gm,4 Or

reducing any other gm in Equation 6.6. However, reducing these gms indicates

increasing Vasat and reduces the available output voltage swing range as shown in

Equation 6.3. Reducing the output voltage swing range will reduce the reference

voltage Vre; of the comparator, and then degrade the ADC performance. Reducing

gm,2 inCTreSeS Vdsat,2 and reduces the input voltage swing range as shown in

Equation 6.2. Reducing gm,6 Or inCTreSing m,~4 decreases the transconductance Gm

of the amplifier as shown in Equation 6.1. To maintain the same average firing

rate face, the input voltage signal should be correspondingly increased. However

the input voltage signal should not be larger than 220Vdsat~,2 otherwise one of the

differential pair transistors M1 and M2 will enter the cutoff region.

6.3 Circuit Implementation of the IF Neuron

The spiking neuron encoder performs the integrate-and-fire encoding opera-

tion. The current is integrated on the capacitor. If the resulting capacitor voltage

is above the reference voltage, the output of the comparator goes high, which

indicates the end of one integration period. The capacitor is reset and after some

time the output of the comparator goes low, which indicates the beginning of

another integration period. As mentioned in (I Ilpter 5 the ADC performance is

heavily dependent on the accuracy of the rising and the falling transition timings

of the spikes. Techniques need to be emploi-v I to improve the accuracy. The power

consumption is also another performance concern. Besides the bias current con-

sumption, the power consumption during switching transitions also needs to be

reduced.















Vdd M5 Il~l M3


M2

Vin Vout Vi Vout

M1 5M Reset M~6 M1

Gnd
Gnd

(a) (b)

Figure 6-2: Latches with a positive feedback. (a) Capacitive feedback latch. (b)
Current feedback latch


The circuit implementations of spiking neuron has been thoroughly investi-

gated in the literature [11, 38, 39]. Mead proposed a neuron formed by two inverters

with a capacitive feedback latch. The capacitive feedback latch is shown in Figf-

ure 6-2(a). Positive feedbacks are t ri- v. 4I for both rising and falling switching

transitions, and therefore the signal dependent delay and refractory period are

reduced, which is desirable for ADC applications. However, the threshold of the

neuron is only determined by the VLSI process parameters and cannot be varied

after fabrication. Also if the input signal varies slowly during the switching, both

the PMOS and NMOS of the inverters are turned on for a long time and a large

short-circuit power is consumed. Van schaik introduced a 5-Transistor opamp

into the neuron implementation so that the reference voltage is variable [38]. A

positive feedback and a del wed I negative feedback are utilized to generate the pulse.

However, the delay unit is implemented using a current starved inverter with a ca-

pacitive load, and a large refractory period is introduced and therefore this neuron

is not suitable for ADC applications.



























Figure 6-3: Schematic of the neuron circuit


Boahen invented a new technique called the current feedback latch, which

is shown in Figure 6-2(b), to reduce the short-circuit power consumption [39].

The current through the inverter formed by M1 and M2 is mirrored to the cur-

rent through M5, which forms a positive feedback. When 1%, is approaching the

threshold voltage of M1, the positive feedback is t ri- v. 4I and the exponentially

increasing current through M5 pulls 1%, up close to Vdd quickly, and correspond-

ingly the Vout is pulled down close to ground quickly. The positive feedback is

terminated when there is no current through the inverter. The positive feedback

can also be t vi- re 4I when we reset 1%,, therefore the pull-down current through

the reset transistor M6 must be larger than the pull-up current through M5 so that

a complete reset can be achieved.

Figure 6-3 shows an spiking neuron implementation using current feedback

latches. The neuron implementation consists of an opamp (1\!11-5) with a current

feedback latch (111.-10), a time delay unit (11 15-21) using current feedback latch,

and some auxiliary circuitry for reset or bypass (\!jil-26). The neuron implementa-

tion works as follows. Assume initially both the output Vout and the voltage Vmem

across the capacitor Cmem are low. M22 is on, M26 and M23 is off, the current










Ii, from the previous transconductance amplifier begins to charge the capacitor

C1 and the resulted voltage Vmem begins to rise. M1 is also on and the opamp

(\!11-5) works as a comparator. When Vmem rises above the reference voltage Vrey,

the output of the opamp rises above the threshold of the current feedback latch

(110l-11), the positive feedback is t ri--- v. 4I and VI goes low quickly and the output

Vout goes high quickly. M22 is off, M26 is on, and the input current is bypassed

through M26. M23 is on and the capacitor Cmem is discharged and the voltage

Vmem is pulled to ground. Since M1 is off, the opamp is disabled, Vout stays high

and is not affected by the change of Vmem. Meanwhile, since VI is low, M13 is on,

a small current Ib2 begins to charge a small capacitor Cd. After some time delay,

the voltage across Cd is high enough to tr~i ;r the following current feedback latch

(\ll15-21), V2 gOeS up, the opamp output is reset, VI goes up and thus Vout goes

low quickly. The time delay is approximately equal to the pulse width and is deter-

mrined by .. Mleanwhlile, M23 anld ML26 ar~e off, M122 anld M11 ar~e on, thle opamrp

is enabled and the current begins to charge the capacitor Cmem again. Also since

VI is high, the large current through M14 quickly pulls down the voltage across the

capacitor Cd, V2 is l0W, M10 is off, and the circuit is back to the initial state.

Transistors (\!2, M24-26) serves for two purposes. One purpose is to bypass

the input current when Vout is high, otherwise the output stage of the previous

transconductance amplifier would enter the triode region and then experience large

disturbance when being back to charge the capacitor after Vmem is reset. The other

purpose is to act as a level shifter when the capacitor voltage Vmem is reset to

zero. With these transistors the output voltage of the previous transconductance

amplifier only needs to be pulled down to |VTP| ~ 0.8V, while without these

transistors the output voltage of the previous transconductance amplifier has to be

pulled down to zero and the corresponding design is complicated.





































Figure 6-4: Layout of the neuron chip


We can see that positive feedbacks are t ri- v. 4I for both rising and falling

switching transitions so that signal dependent delay or refractory period are

reduced. Since current feedback latches are emploi-. I the short-circuit power

consumption of the inverters is minimized. Since the del li- time is very short, the

power consumption due to Ib2 is negfligfible. The power consumption of this neuron

implementation is mainly the bias current Ib1 COnSumption of the opamp. The

threshold voltage of this neuron can be varied from ground to Vdd Vtp 2Vdase,

and thus it is suitable for the realization of the threshold adaptation.

6.4 Neuron chip layout

The neuron chip was implemented in the AMI 0.5 um C\!LOS technology

process and packaged in a standard 40-pin DIP40 through MOSIS. The total

chip area occupied by the integrator and the neuron encoder is 18000(pm)2. The









Table 6-1: The transistor sizes for the transconductance amplifier

Transistors W/L (pm)
M ,11,12 18 *
M1,2 1.5/45
if. 4 2.4/0.6
M5,6 4.8/6.6
M7,s 1.8/1.8
-17*10,1-15 4.5/1.8
M16 9/1.8

Table 6-2: The transistor sizes for the IF neuron

Transistors W/L (pm)
%, 7.2/1.8
M1,~11,13,19,21-23,25,26 1.5/0.6
M_ 1.; 9/1.8
M4,5,12 1-8 *.8
M, _., is--i 3/0.6
Ml,,, 6 0.6
M14 4.5/0.6
M_,, 1.5/1.5


capacitor is implemented using poly1 and poly2 1., r-is. Chip area can be reduced

if using MOS capacitors with higher capacitance density. The chip layout is shown

in Figure 6-4. The digital circuitry and the analog circuitry are separated by guard

rings so that the analog circuitry is not affected much by the large transient noise

produced by the digital circuitry [40]. The power supplies for the analog and the

digital circuits are also separated. The transistor sizes for the transconductance

amplifier and the IF neuron are illustrated in Table 6-1, 6-2, respectively.

6.5 Neuron chip Test Results

For the transconductance amplifier, both the bias currents Ib0 and Ib1 are 2

p-A, the DC offset current lac = 1 p-A, the common mode input voltage is 2.5 V.

For the neuron encoder, the capacitor C1 = 10 pF, the capacitor Cd = 100 fF, the

reference voltage Vre; is 2.5 V, the bias current Ib1 of the opamp is 2 pA, the bias

current Ib2 of the delay unit is 0.05 pA.









The input voltage sine wave is x(t) = 2.5V + A sin(2x ft) and is provided

through a function generator. Because the function generator we used can only

provide sine waves with amplitudes larger than 10 mV, an attenuator formed by

two resistors (50 kR, 2 kR) is emploi-v I for signals with amplitude less than 10 mV.

As will be seen, the thermal noise introduced by these two resistors is negligible

and does not degrade the ADC performance. A logic analyzer is used to capture

transition timings of the chip output. The clock period of the logic analyzer is 5 ns.

The signal is reconstructed in Matlab using the algorithm discussed in OsI Ilpter 4.

We apply the sine wave with different amplitudes and from the reconstructed

signal we can estimate the transconductance of the transconductance amplifier

is Gm = 6.2 pl-'l. The measured pulse width is 1.5 ps and is consistent with

CdVTw/Ib2 = l1. MS COnSidering some parasitic capacitance. The measured average

firing rate is f,,, = 58 kHz. Then the input referred DC offset voltage is


Vac Czr=' 234mV (6.7)
Gm

This DC offset voltage consists of the amplifier built-in offset voltage and the input

referred DC offset voltage due to the DC current lac added at the output. This DC

offset voltage is also called the full scale amplitude dBFS in later discussions.

The current consumption of the chip excluding pads and buffers is around 9

p-A, and therefore the power consumption for a 5V power supply is 9p x 5 = 45 pW.

Since the actual total bias current is Ibias,tot b IO,amp + 2b1,1amp d~c~amp b l,neuron

1.941 + 1.966 + 1.966 + 1.001 + 1.992 = 8.866 pA, the resulted 0.134 pA is due to

the dynamic current consumption of the digital circuitry.

We have implemented two tests to characterize the chip performance based

on the IEEE standard 1241 for ADC test [41]. One is the 4-parameter sine wave

fittingf test and the other is the histogfram test.



















60








-60 -50 -40 -30 -20 -10 0
Sine wave amplitude (dBFS)


Figure 6-5: Plot of the SNR vs. sine wave amplitude of the spiking neuron chip

6.5.1 4-parameter Sine wave Fitting Test

The 4-parameter sine wave fitting method is a time-domain test method to

determine the ADC performance. The method is to estimate the input signal from

the ADC output samples by finding the best-fitting sine wave [41]:


x(t) = A cos(cot + 8) + C (6.8)


We find the best-fitting sine wave by using online matlab code [42] which is realized

based on the IEEE 1241 standard. The noise and distortion are defined as the

difference between the ADC output samples and the estimated signal samples. The

signal power is defined as the power of the sine wave without DC offset based on

the IEEE 1241 standard. Then we can calculate the signal to noise ratio (SNR).

The resolution of the ADC, i.e., the effective number of bits (ENOB), is calculated

via Equation 2.1. Fig 6-5 shows the measured SNR vs. the amplitude of the sine

wave with 1kHz frequency, where the signal bandwidth of the converter is 10 kHz










65





60 -





55 -





50
0 2000 4000 6000 8000 10000
Sine wave frequency (Hz)


Figure 6-6: Plot of the SNR vs. sine wave frequency of the spiking neuron chip


(R, = 2xr x 10k = 20kxr rad/sec), and 0 dBFS refers to a sine wave with 0.234

V amplitude. As the sine wave amplitude increases, the SNR increases with a

slope of 1dB/1dB to reach the peak of 59 dB at around -5 dBFS, i.e., 0.13 V

amplitude, and then quickly drops to 0 dB. The SNR drop is due to the increased

nonlinearities caused by the larger amplitude signal input and the frequency

aliasingf caused when the maximum interval between .Illi Il-ent transition timings

grows larger than the Nyquist period WasR. We conclude that the chip can achieve

59 dB SNR, or equivalently 9.5 bit resolution. In order to show the performance

is consistent for different frequencies, we also provide a plot of the SNR vs. the

frequency of the sine wave with a -5.8 dBFS amplitude in Fig 6-6. The SNR is

above 57 dB for frequencies up to 10 kHz bandwidth.

6.5.2 Sine Wave Histogram Test

Sine wave histogfram testing is also performed to measure the differential

nonlinearity (DNL) and integral nonlinearity (INL). This test computes the code



















o 0 100 200 300 400 500 600 700 800 900 1000




0 -t---tt-


-0.5 -

~1


Table 6-3: Neuron chip performance metric

Core die area ((pm)2) 18000
Power consumption (pW) 45, 10.5 (w/o transamp)
Signal bandwidth (kHz) 10
Effective resolution (Bit) 10
SNR (dB) 59


0 100 200 300 400 500 600
Output Code


700 800 900 1000


Figure 6-7: Plots of the DNL and INL from the sine wave histogram test of the
spiking neuron chip


density of the reconstructed signal, and then compares it to the code density of an

ideal sine wave to obtain the nonlinearities [43, 44]. The input signal to the chip

is a sine wave with a 1 kHz frequency and a -5.8 dBFS amplitude. The sampling

frequency of the reconstructed signal is not harmonically related to the sine wave

frequency as required by the IEEE standard 1241. With the assumption of 10 bit

resolution, the nonlinearities are calculated and plotted in Fig 6-7. We can see

both DNL and INL are less than 1 least significant bit (LSB), which verifies that

the chip achieves an 10-bit resolution. The neuron chip performance metric is

summarized in Table 6-3.









6.6 Discussion

In this chapter we have discussed a detailed circuit implementation of the

spiking neuron encoder. The test results show that the neuron chip can achieve

59 dB signal to noise ratio (SNR). The noise is the total effect of all kinds of error

sources as discussed in Chapter 5. It is of interest to verify the effect of these error

sources on the performance of the neuron chip and to see if it is consistent with

the chip measurement. We should be aware that the definition of the SNR in this

chapter is not exactly the same as that in ChI Ilpter 5. Neither the signal power

nor the noise power are calculated with the DC offset using 4-parameter sine wave

fittingf test. However, in ChI Ilpter 5 the DC component is considered in calculations

of both the signal power and the noise power.

We only consider the error sources such as the leaky integration of the

integrator, thermal noise of the spiking neuron, the signal dependent reference

variation of the comparator, and the timing jitter of the time quantizer. Without

additional declarations, the parameters of the ADC are: C = 10 pF, Vre; = 2.5 V,

Gm = 6.2 uRl-, R = 80 MR, and the signal bandwidth as = 2xr10000 rad/s. The

input signal is V(t) = Vac + A sin(2x ~ft) with a DC component Vac = 0.234 V and a

sine wave with an amplitude A = 0.13 V and a frequency f = 1 kHz.

The power of the first derivation of the input signal V(t) is E[V2(l

0.5A2(2x f)2. From Figure 5-4 we can obtain the SNR due to the leaky integration

of the integrator is 76.5 dB from Equation 5.15, or 78.5 dB from the Matlab

simulation. Since Equation 5.15 -11---- -R- the SNR is also inversely proportional

to the sine wave frequency. The worst case here is when the signal frequency

equals the ADC bandwidth, i.e., 10 kHz. Therefore, the worst case for the leaky

integration is that SNVRleaky = 78.5 20 = 58.5 dB from Equation 5.15.

We can use the noise analysis tools in Cadence to measure the output referred

noise current PSD of the transconductance amplifier 4kTyGm = 1.2 x 10-24A2/Hz.










In the chip measurement setup an attenuator formed by two resistors (R1 = 50

kR, R2 = 2 kR) is emploi-. I for signals with amplitude less than 10 mV. We

can calculate the additional output referred noise current PSD due to these two

resistors as 4kT(RI||R2)G~ = 1.22 x 10-27A2/Hz, which is negligible and does

not degrade the ADC performance. From Figure 5-8 we can obtain that the SNR

due to the thermal noise is 79 dB from Equation 5.27, or 78 dB from the Matlab

simulation.

In the implementation of the spiking neuron in Section 6.3 when the output of

the 5-transistor opamp reaches the threshold (VTN) of the current feedback latch,

the positive feedback is t ri- v. 4I and it takes very short time for the output of

the opamp to reach the positive power supply. Therefore we may treat the digital

logic state Vd as the latch threshold, i.e., the comparator resolves to the logic state

when the output of the opamp reaches VTN ~ 0.7V. Simulations have been run in

Cadence to measure the DC gain of the opamp Ae = 109, the unity gain frequency

of the opamp f, = 62MHz, and the corresponding time constant Tc, = 280 ns. From

Figure 5-11 we can obtain that the SNR due to the signal dependent reference

variation of the comparator is 57 dB from Equation 5.44, or 58 dB from the Matlab

simulation.

The clock period used in the logic analyzer is T, = 5 ns. The average firing

rate of the ADC is f,,, = 58 kHz. From Equation 5.56 we can obtain that the SNR

due to the timing jitter is 78.5 dB.

The chip measurements are consistent with the equations and the simulations

discussed in OsI Ilpter 5. From previous discussions we can see that the performance

limitation of this neuron chip implementation is mainly due to the signal dependent

reference variation of the comparator. Therefore, higher levels of the other error

sources can be tolerated during the ADC design and the power consumption of the

transconductance amplifier maybe further reduced.















CHAPTER 7
IMPLEMENTATION AND TEST OF AN ASYNCHRONOUS DELTA SIGMA
CONVERTER

7.1 Introduction

In this chapter we first introduce a typical .I-i-alchronous delta sigma converter

architecture and then present the DSP reconstruction algorithm. Two circuit

implementations of the converter are explained in detail and the corresponding chip

performance is determined using the 4-parameter sine wave fitting method test and

the histogram test method.

7.2 Asynchronous Delta Sigma Converter Architecture

Generally p. .1:;11, the spiking neuron TB-ADC previously discussed can only

receive positive signal input, otherwise the interspike interval may be too large and

the bandwidth constraint is thus violated. The .I-i-nchronous delta-sigma converter

is another integrate-and-fire type of TB-ADC which can accept positive or negative

signal input [6, 45, 46]. Figure 7-1 shows the architecture of a typical .I-i-alchronous



x(t) Vd yv, v, (ti)
dt I"' o


I nteg rator
Schmidt trigger

a ++ high
-a ++ low

1-bit DAC


Figure 7-1: Architecture of the .I-i-nchronous delta sigma converter


delta sigma converter based on the scheme proposed by Lazar and Toth [7]. This










architecture does not use a clock to sample the analog signal, and no quantization

operation is involved during the data conversion. The difference between the

input signal V(t) and the fedback analog value corresponding to the Schmitt

trigger output y(ti) is continuously integrated. The Schmitt trigger controls the

sampling operation with its high reference voltage VKa and low reference voltage

VI. The Schmitt tri l'-;- output y(ti) switches from low to high if the integrator

output rises above the high reference voltage Vrh, switches from high to low if

the integrator output drops below the low reference voltage VI, and otherwise

remains unchanged. If there are no nonidealities during the data conversion, the

information in the analog signal is losslessly encoded in the transition timings ti

of the Schmitt trigger output. This is a marked difference from synchronous delta

sigma converters where lossless sampling can only occur .I-i-inphli'1 cally in the

limit as the oversampling ratio increases to infinity. The .I-i-nchronous converter

described here requires no oversamplingf in principle, however a small amount of

oversampling increases the signal to noise ratio (SNR) in practice.

7.3 Signal Reconstruction Algorithm

The Schmitt tri 1;- output is discrete in amplitude and continuous in time

and necessitates time quantization to obtain digital output. Moreover, since most

current digital systems can only process uniformly sampled data, the nonuniform

nature of the Schmitt tri 1;- output requires another signal processing block to

convert to a uniformly sampled sequence for subsequent digital processing. The

overall ADC performance is not only dependent on the accuracy of the encoding

circuit, but also on the efficiency of the signal reconstruction block. Direct low

pass filtering cannot achieve satisfactory performance unless the average firing rate

is extremely high [6], which necessarily requires more power consumption on the

converter. We can use the WLPK( method introduced in Section 4.3 to reconstruct

the signal. Similar to the signal reconstruction from spiking neuron models, we