<%BANNER%>

A Wireless clock distribution system using an external antenna

University of Florida Institutional Repository
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PAGE 1

A WIRELESS CLOCK DISTRIBUTION SYSTEM USING AN EXTERNAL ANTENNA By RAN LI A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2005

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ii ACKNOWLEDGMENTS I would like to thank my advisor, Pr ofessor Kenneth O, for giving me the opportunity to be part of the SiMICS research group a nd involved in the wireless clock distribution project. Hi s constant encouragement and guidance have been the main reason for the success of this work. I am deeply grat eful to him for what I have learned from him, which will benefit me in my whole life. I would like to thank Professors Jens han Lin, Rizwan Bashirullah, and Loc Lu-Quoc for their interest in this work a nd their time commitment in serving on my committee. I would like to thank the Semiconductor Re search Corporation (SRC) for sponsoring this work. I would like to thank UMC for the chip fabrication. I would like to thank the former SR C group member K. Kim, B. A. Floyd, J. Caserta, W. Bomstad, N. Trichy T. Dickson and J. Branch. Th e discussions with them and their advice were immens ely helpful for this work. Also, I would like to thank my research colleagues Dong-Jun Yang and Xi aoling Guo, for their teamwo rk and great help on this work. I am grateful to the current fellow me mbers of SiMICS research group for their continuoues support and friend ship on this project. I would like to thank my parents, my br other and sister. Their love and encouragement are the source of my stre ngth. Finally, I am grateful to Maojiao for her love and dedication behind this Ph.D. work.

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iii TABLE OF CONTENTS page ACKNOWLEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . .ii ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii CHAPTERS 1INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1Chanllenges of Conventional Interconnect Technology . . . . . . . .1 1.2Possible Solutions. . . . . . . . . . . . . . . . . . . . . . . .3 1.2.1Low-resistivity and LowMaterials. . . . . . . . . . . . .3 1.2.2Skew Compensation Using Feedbacks. . . . . . . . . . . . .4 1.2.3Distributed Oscillators or PLLs for Clock Distribution . . . . .5 1.2.4C oupled Standing-Wave for Clock Distribution. . . . . . . . .6 1.2.5Optical Clock Distribution Network. . . . . . . . . . . . . .7 1.3Inter/Intra-Chip Wireless Clock Distribut ion Using Microwaves . . . . . .8 1.3.1System Description. . . . . . . . . . . . . . . . . . . .8 1.3.2Challenges of Inter-chip Wireless Clock Distribution . . . . . .12 1.4Overview of the Dissertation . . . . . . . . . . . . . . . . . . .13 2THEORETICAL ANALYSIS OF LINEAR DIPOLE ANTENNAS . . . . .15 2.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2Dipole Antennas in Uniform Medium . . . . . . . . . . . . . . . .16 2.2.1Arbitrary-Length Dipole Antenna Characteristics. . . . . . . .16 2.2.2Performance of Dipole Antenna Pair in Uniform Medium . . . .24 2.3Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3INTER-CHIP WIRELESS INTERCONNECTION SYSTEM . . . . . . . .32 3.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.2Measurement Setup Improvement . . . . . . . . . . . . . . . . .34 3.2.1Measurement Setup and Its Shortcomings. . . . . . . . . . .34 3.2.2System Calibration. . . . . . . . . . . . . . . . . . . .36 3.3Measurement Results . . . . . . . . . . . . . . . . . . . . . .39 3.3.1Characteristics of Receiving Antennas. . . . . . . . . . . .39

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iv 3.3.2Gain and Phase Distributions from External Antenna . . . . . .44 3.3.3Wireless Interc onnect between Receiver and External Antenna . .46 3.4Heatsink Incorporation. . . . . . . . . . . . . . . . . . . . . .48 3.4.1Heatsink Evaluation . . . . . . . . . . . . . . . . . . .48 3.4.2Measurement Results With Heatsink . . . . . . . . . . . .51 3.5A Compact Inter-chip Clock Distribution System . . . . . . . . . . .55 3.6Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4CMOS CLOCK TRANSMITTER . . . . . . . . . . . . . . . . . . .60 4.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4.2Initialization and Start-up Scheme . . . . . . . . . . . . . . . . .61 4.3Transmitter Design. . . . . . . . . . . . . . . . . . . . . . . .63 4.3.1Voltage-Controlled Oscillator. . . . . . . . . . . . . . . .65 4.3.2 512:1 Divider and Logic Circuits. . . . . . . . . . . . . .66 4.3.3No-Signal-Transmission Period Generation Scheme. . . . . . .69 4.3.4Power Amplifier. . . . . . . . . . . . . . . . . . . . .70 4.4Measured Results of Transmitter . . . . . . . . . . . . . . . . . .72 4.4.1VCO Measured Results . . . . . . . . . . . . . . . . .72 4.4.2Transmitter Output Signal . . . . . . . . . . . . . . . .73 4.4.3Output Power . . . . . . . . . . . . . . . . . . . . .78 4.5A 20-GHz Clock Transmitter. . . . . . . . . . . . . . . . . . . .79 4.5.1VCO with New-designed Varactors. . . . . . . . . . . . .80 4.5.2Reduction of Q-Factor at Intermediate Node. . . . . . . . . .82 4.5.3Power Amplifier Redesign. . . . . . . . . . . . . . . . .83 4.5.4Measured Results . . . . . . . . . . . . . . . . . . . .85 4.6Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .88 5DEMONSTRATION OF INTER-CHIP CLOCK DISTRIBUTION . . . . .90 5.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .90 5.2Measurement Setup . . . . . . . . . . . . . . . . . . . . . . .91 5.3Inter-chip Clock Distribution System Demonstr ation . . . . . . . . . .95 5.3.1System Demonstration wit hout Heatsink. . . . . . . . . . .95 5.3.2System Demonstration with Heatsink . . . . . . . . . . .102 5.3.3Comparison am ong Clock Distribution Systems . . . . . . .106 5.4Summary . . . . . . . . . . . . . . . . . . . . . . . . . .107 6SUMMARY AND SUGGESTIONS FOR FUTURE WORK. . . . . . . .109 6.1Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .109 6.2Future Works. . . . . . . . . . . . . . . . . . . . . . . . . .110 6.2.1Demonstration of Compact Clock Distribution System. . . . .111 6.2.2Removal of the External PA. . . . . . . . . . . . . . . .111 6.2.3Higher Clock Frequency and Smaller On-chip Antenna . . . .111

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v APPENDIX AWAVE PROPAGATION BETWEEN ON-CHIP ANTENNA PAIR. . . . .113 A.1Multi-path Model for On-chip Antenna Pair . . . . . . . . . . . . .113 A.2Electric Field Due to Path A, C, D. . . . . . . . . . . . . . . . .116 LIST OF REFERENCES. . . . . . . . . . . . . . . . . . . . . . . . .123 LIST OF REFERENCES. . . . . . . . . . . . . . . . . . . . . . . . .123 BIOGRAPHICAL SKETCH128 APPENDIX WAVE PROPAGATION BETWEEN ON-CHIP ANTENNA PAIR. . . . . . .114 A.1Multi-path Model for On-chip Antenna Pair . . . . . . . . . . . . .114 A.2Electric Field Due to Path A, C, D. . . . . . . . . . . . . . . . .117 LIST OF REFERENCES. . . . . . . . . . . . . . . . . . . . . . . . .124 BIOGRAPHICAL SKETCH. . . . . . . . . . . . . . . . . . . . . . .129

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vi LIST OF TABLES 3-1Cut-off frequencies . . . . . . . . . . . . . . . . . . . . . . . . .49 4-1Transistors sizing for the first 4 stages SCL divi der . . . . . . . . . . . .68 5-1Comparison of high-performance clock di stribution networks recently reported. 106 Table Page

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vii LIST OF FIGURES 1-1H-tree clock distribution network . . . . . . . . . . . . . . . . . . . .2 1-2Diagram of skew compensation scheme (a ) two feedback paths (b) one feedback path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1-3Diagram of clock distributi on with (a) distributed ring os cillators (b) di stributed PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1-4Clock distribution network using coupled standing-wave (a) Clock distribution (b) Coupled standing-wave oscillators. . . . . . . . . . . . . . . . . 6 1-5Optical clock distribution with the propagation medium of (a) freespace (b) waveguides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1-6Conceptual diagrams of (a) intra-chip (b) inter-chip wireless cl ock distribution system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1-7Block diagram of clock tr ansmitter. . . . . . . . . . . . . . . . . . .11 1-8Block diagram of clock receiver . . . . . . . . . . . . . . . . . . . .11 2-1Linear dipole antenna . . . . . . . . . . . . . . . . . . . . . . . .16 2-2Directivity vs. frequency for a 2-mm antenna pair in free space, AlN and 20 -cm Si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2-3Radiation efficiency vs. frequency for a 2-mm antenna in fr ee space, AlN and 20 cm Si . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2-4Effective area vs. frequency for a 2mm antenna in free space, AlN and 20 -cm Si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2-5A dipole antenna pair in a uniform medium . . . . . . . . . . . . . . .23 Figure Page

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viii 2-6Power gain vs. frequency for a 2-mm antenna pair in fr ee space, AlN and 20 -cm Si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2-7Power gain vs. distance for a 2-mm antenna pair in different media at 24 GHz .25 2-8Power gain vs. frequency in 20 -cm Si for different antenna length . . . . .26 2-9Peak power gain vs. corres ponding frequency in Si with different resistivity . 27 2-10Power gain vs. antenna length at 20 and 100 GHz in 20 -cm and 100 -cm Si .28 2-11Optimal antenna length vs. corresponding fr equency in freespace, AlN and Si .28 2-12Power gain vs. resistivity of silicon, at optimal antenna length . . . . . . . .29 2-13Radiation pattern at the optimal antenna length at 20 GHz and 100 GHz . . . 30 2-14Radiation pattern at 0.5 x the optimal an tenna length at 20 GHz and 100 GHz. .30 3-1Clock distribution using an off-chip antenna . . . . . . . . . . . . . . .32 3-2Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . .34 3-3Balun and semi-rigid cables . . . . . . . . . . . . . . . . . . . . .35 3-4Antenna test chamber with absorber liners . . . . . . . . . . . . . 36 3-5Measured impedance of 2-mm zigzag dipole . . . . . . . . . . . . . . .37 3-6Two-port network composed of balun, semi-r igid cables and probe . . . . . .38 3-7Comparison of measured S11 and calculated S11 . . . . . . . . . . . . .38 3-8Layout of the test chip. . . . . . . . . . . . . . . . . . . . . . . .39 3-9Antenna gain on a 20-cm substrate. . . . . . . . . . . . . . . . 40 3-10Zigzag dipole antenna gain as a functio n of the separation between a wafer and an off-chip antenna. . . . . . . . . . . . . . . . . . . . . . . 40 3-11Zigzag dipole gain performance on different subs trates.. . . . . . . . . . .41 3-12Average gain (24 to 24.2 GHz) vs. separa tion for 2-mm zigzag dipole antenna. .41 3-13Average gain (24 to 24.2 GHz)vs. substrat e resistivity for zigzag dipole antennas42

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ix 3-14Inter-chip antenna pair gain for varying s ubstrate resistivity and thickness. . . .43 3-15Across a 2-inch-diameter opening with a 7.5-inch separation (a) relative gain (dB) distribution, (b) phase (degree) di stribution . . . . . . . . . . . . . 44 3-16Across a 4-inch-diameter opening with a 7.5-inch separation (a) relative gain (dB) distribution, (b) phase (degree) di stribution . . . . . . . . . . . . . 45 3-17A block diagram of a 0.18m clock receiver with a zigzag dipole antenna.. . 46 3-18Sensitivity vs. frequency plots for differ ent separation between the receiver and offchip transmitting antenna.. . . . . . . . . . . . . . . . . . . . 47 3-19Generic heatsink and modified heatsink. . . . . . . . . . . . . . . 48 3-20Waveguide models. . . . . . . . . . . . . . . . . . . . . . . . . .49 3-21Generic heatsink and modified heatsink . . . . . . . . . . . . . . . . .50 3-22Gain vs. frequency under different situations . . . . . . . . . . . . . . .51 3-23Gain vs. frequency for different antennas. . . . . . . . . . . . . . . . .51 3-24Gain and phase vs. location in each aperture at 23.25 GHz. . . . . . . . 53 3-25Relative gain and phase at center of each apertures at 24GHz. . . . . . . 54 3-26Proposed inter-chip clock distribution system. . . . . . . . . . . . . . .56 3-27Antenna test chamber . . . . . . . . . . . . . . . . . . . . . . . .56 3-28Across a 4-inch-diameter opening with a planar array antenna (a) relative gain (dB) distribution, (b) phase (degree) di stribution . . . . . . . . . . . . . 57 3-29Relative gain and phase at ce nter of each apertures at 24GHz . . . . . . . .58 4-1Initialization and start-up scheme.. . . . . . . . . . . . . . . . . 62 4-2Clock transmitter block diagram . . . . . . . . . . . . . . . . . 63 4-3Die photograph of clock transmitter . . . . . . . . . . . . . . . . . .64 4-4Circuit schematic of VCO and buffer . . . . . . . . . . . . . . . . . .65 4-5Block diagram of 512:1 frequency divider . . . . . . . . . . . . . . . .67

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x 4-6A block diagram of control-sign al-generation circuit. . . . . . . . . . . .69 4-7Circuit schematic of generating no-signal-transmission period.. . . . . . . 69 4-8Simulated output clock signal and control signal. . . . . . . . . . . . 70 4-9Circuit schematic of out put power amplifier. . . . . . . . . . . . . . . .71 4-10The simulated differential output waveform from PA. . . . . . . . . . . .71 4-11Output phase noise and spectrum of VCO.. . . . . . . . . . . . . . 72 4-12VCO tuning range . . . . . . . . . . . . . . . . . . . . . . 73 4-13Measurement setup of the transmitter. . . . . . . . . . . . . . . . . .74 4-14Waveforms of control signal and clock signa l (synthesizer as the clock source) .75 4-15Waveforms of control signal and clock signa l (VCO as the clock source). . . .75 4-16Transmitter output spectrum . . . . . . . . . . . . . . . . . . . . .76 4-17The measurement setup of using a transmitter on a PC-board. . . . . . . 76 4-18Waveforms of control signal and clock signal (Transmitter on board) . . . . 77 4-19RMS jitter of the output clock signal . . . . . . . . . . . . . . . . . .77 4-20Output power vs. clock frequency. . . . . . . . . . . . . . . . . . . .78 4-21Power amplifier output matching. . . . . . . . . . . . . . . . . 79 4-22Die photograph of the 20-GHz cl ock transmitter. . . . . . . . . . . . 80 4-23Layout of the newly designed MOS varactor . . . . . . . . . . . . . . .81 4-24Output phase noise and spectru m of the 20-GHz VCO. . . . . . . . . . . .82 4-25Tuning range of the 20-GHz VCO . . . . . . . . . . . . . . . . . . .82 4-26500-pH spiral inductor with a 200parallel resistor. . . . . . . . . . 83 4-27Output stage of clock transmitter in cluding PA and no-signal-transmission generation circuits. . . . . . . . . . . . . . . . . . . . . . . . . 83 4-28Simplified small-signal model of the common-source PA. . . . . . . . . 84

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xi 4-29Output clock waveform of the 20-GHz clock transmitter (on-chip). . . . . . .85 4-30Output clock waveform of the 20-GHz clock transmitter (on-board). . . . . .86 4-31RMS jitter of transmitted clock signal and triggering signal . . . . . . . 87 4-32Output power vs. clock frequency. . . . . . . . . . . . . . . . . . . .87 5-1Inter-chip clock distribution using a planar array antenna. . . . . . . . . 91 5-2A measurement setup of the wireless clock distribution syst em with an external antenna. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 5-3Photo of the measurement setup for the interchip clock distribution. . . . . .92 5-4Photograph of transmitter and receiver boards.. . . . . . . . . . . . . . .93 5-5Die photograph of the clock receiver . . . . . . . . . . . . . . . . . .94 5-6A measured waveform of the locked local clock signal (without heatsink) . . .96 5-7Local clock signal waveform over a shorter time period. . . . . . . . . 97 5-8Measured RMS jitter of the local clock si gnal and triggering signal . . . . 98 5-9Places in the cover opening to which the re ceiver chip can be moved . . . .100 5-10Local clock signal waveforms with receiver at 9 different places . . . . . 101 5-11Skew among the 9 places . . . . . . . . . . . . . . . . . . . 101 5-12Measurement setup with a heatsink . . . . . . . . . . . . . . . 103 5-13A measured waveform of the locked local clock signal (with a heatsink) . . .104 5-14Measured RMS jitter of the local clock signal and triggering si gnal (with a heatsink). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 A-1Power gain vs. frequency for different propa gation medium . . . . . . . .114 A-2Power gain vs. Frequency for AlN with differ ent thickness. . . . . . . . .115 A-3Measurement setup of on-chip antenna pair . . . . . . . . . . . . 116 A-4Wave paths of propagation . . . . . . . . . . . . . . . . . . 116

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xii A-5Lateral wave field . . . . . . . . . . . . . . . . . . . . . . . . .117 A-6Possible lateral wave path between an on-chip antenna pair . . . . . . . .118 A-7Calculated attenuation factor G when the distance is 5mm. . . . . . . . 120 A-8Wave transmission between SiO2 and Si . . . . . . . . . . . . . 121 A-9Calculated normalized E-field at the receiv ing antenna vs. frequency. . . . .122 A-10Measured power gain vs. frequency . . . . . . . . . . . . . . . . . .122 A-11Dip frequency vs. AlN thickness. . . . . . . . . . . . . . . . . . . .123

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xiii Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy A WIRELESS CLOCK DISTRIBUTION SYSTEM USING AN EXTERNAL ANTENNA By Ran Li August 2005 Chair: Kenneth K. O Major Department: Electrical and Computer Engineering With the increase of system operating fr equency and projected die size, distributing signals across the chip becomes challengi ng, due to the larger R-C delays, tighter skew and jitter tolerance and sign al dispersion along the metal interconnect paths. Some novel interconnection architectures ar e under investigation to tackle these problems, including optical interconnects, superc onducting interconnects and biol ogical interconnects. Previous works have demonstrated a wireless interconnect for cloc k distribution system utilizing microwaves, which is compatible wi th the conventional CMOS process. In such a system, clock signals propa gate at the speed of light of a propagating medium. An on-chip or off-chip tran smitting antenna transm its a global clock signa l. A grid of on-chip receivers with integrated antennas picks up th e signal, amplifies it and divides it down by 8 to provide the local clock si gnal. This work theoretically investigates the integrated antenna performance. Using the results from this, a wireless cloc k distribution system

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xiv using an external antenna (inter-chip wirele ss clock distribution) is constructed, and its characteristics are studied. First, the gain, directivity, efficiency and impedance of dipole antennas with arbitrary length, and the power tr ansmission gain between any two dipole antennas in a lossy medium have been calculated and used to de termine approaches to optimize antenna performance at a given frequency. Second, an inter-chip wireless interconnection is constructed and measured. The feasibility of an inter-chip clock distribution system is evaluated by measuring the power transmission gain be tween off-chip antennas and on-chip integrated antennas, and relative gain and phase distributions of signals picked up by the on-chip antennas. Also, a commercially available heatsink with fins and rectangular apertures is incorporated into this syst em. Third, a 17-GHz a nd a 20-GHz clock signal transmitter in a UMC 0.13 m logic CMOS process have b een designed, fabricated and measured. Periodic no-signal-t ransmission function is incor porated in the output clock signal, which is used by clock receivers for initiali zation and start-up. Fi nally, with a horn antenna as the external transm itting antenna, the operation of th e entire wireless clock distribution system is successfully demonstrated for the first time. Th e receiver initialization and start-up steps are working well and repeat able. The total clock skew and jitter are below 5% of a period at ~ 2.2GHz over a 4-cm diameter circular area. The results of this dissertation show the feasibili ty and have the potential for opening the doors for new clock distribution systems which can ope rate at higher frequency a nd synchronize a larger area.

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1 CHAPTER 1 INTRODUCTION 1.1 Challenges of Conventional Interconnect Technology The integrated circuit (IC) die size and clock signal frequenc y are being increased and feature size is being sc aled to accommodate faster a nd more complex functionality. According to the 2003 International Techno logy Roadmap for Semiconductors (ITRS), the chip areas for high pe rformance microprocessors are projected to be 310mm2, with the chip clock frequency of 9.29 and 12.4GHz at the 65 and 50 -nm technology nodes, respectively [SIA03]. The propagation delay of a signal on a metal li ne is approximately 0.35RCl2 [Wes92]. R and C are the resistance an d capacitance-per-unit-length of metal lines. Scaling down of the CMOS IC feature size increases the RC time constant [Boh95, Tau98]. With the increase of clock frequency, th is increases even faster due to the increase of resistance of metal lines re sulting from the skin effect. Al l these lead to a larger delay through the metal interconnection lines. With the increase of clock frequency and chip size, th e lengths of global interconnect metal lines become close to the wave length, and hence the global interconnects will function as transmission lines. The complex propagation constant is given by Eq. 1.1. and are the conductance and i nductance per unit lengt h of the metal lines. The attenuation constant which is the real part of complex propagation constant, increases with ++ + == (1.1)

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2 clock frequency. In addition, global interconnect lengths goes up with the increase of die size (). These two factors increase the vol tage attenuation (, i.e., the power loss) along the metal lines, which will require more drivers on the interconnection paths. On the other hand, because of the loss of transmission lines, clock dispersion also becomes a serious problem, which leads to an increase of the rise and fa ll times of th e clock signals [Deu98]. These issues pose great challenges for gl obal clock signal distribution. In a clock signal distribution system, lo w skew, low jitter and low power-dissipation are critical requirements. Skew is defined as the static phase mismatch among local cloc ks, while jitter is the time dependent random phase vari ation of clock signals caused by noise. Normally, the total skew and jitter tolerance in a microprocessor should be typically less than ~10% of a clock period. The c onventional global clock distribut ion often uses an H-tree to match the phases of local cloc k signals (Figure 1-1). The mi smatches of different signal paths and clock buffer s will generate clock skew. At lower clock signal frequencies, an CLK root leaf Figure 1-1. H-tree cloc k distribution network

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3 H-tree can be used to distribut e the clock signals with acceptable clock skew. With the improved performance of micropr ocessors, the clock frequency has become higher, resulting in a decrease of the clock period and hence making the skew tolera nce tighter in absolute time. Also, the propagation delay becomes larger with th e increase of clock frequency and chip size. It beco mes more and more difficult to match the larger propagation delays to a tighter skew tolerance. In an H-tree, jitter accumulates with the distance from a clock source, and clock repeat ers and buffers increase jitter because of the substrate and power supply noise. At higher clock fr equencies, the jitter tolera nce in absolute time also becomes tighter. In modern high-performan ce microprocessors, th e power dissipation could be larger than 100W. Driving the loads through the clock tree with the total length in the order of kilometers uses 30% or even 50% of this pow er [Kav00]. Because of these, the clock distribution using c onventional approach is becomi ng more difficult with each technology generation. 1.2 Possible Solutions The global wiring issue has been identif ied as a long-term “Grand Challenge” for semiconductor industry by th e 2001 International Technol ogy Roadmap for Semiconductors [SIA01]. To tackle this problem, many ideas and technique s have been investigated in the past decade. All the new techniques improve some aspects among the above mentioned problems. However, each of them has its own pros and cons. 1.2.1 Low-resistivity and LowMaterials Copper and low-k dielectrics were introdu ced to reduce the RC propagation delay in the global interconnect syst em. With lower resistivity and lower dielectric constant k, new materials can decrease the R and C by the same ratio as and k, and reduce the clock

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4 skew associated with the path length mismatch. However, with the increase of chip area, the RC propagation delay is still becoming la rger. Use of new materials will also soon encounter their fundamental l imits [Deu98]. It can only extend the lifetime of the conventional global interconnect system by several generations. New techniques have to be discovered to overcome the limitations. 1.2.2 Skew Compensation Using Feedbacks The use of feedback is a way to compensate the clock skews at different points in a clock network (Figure 1-2) A skew compensation scheme among three different local-clock-trees in an H-tree is shown in Fi gure 1-2 (a) [Hsi98]. Tw o feedback paths are connected to the root and one leaf in a local clock tree, respectively. The compensator measures the round-trip delays from the root s to leaves. Then, the phases are compared and the error is compensated. Figure 1-2.(b) shows an H-tree operating in a similar way. The comparator compares the phase difference between two leaves in two different local PLL Compensator ComparatorDelay Delay Global clock Diagram of skew compensation scheme with (a) two feedback paths (b) one feedback path Figure 1-2. (a) (b)

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5 clock trees. The phase error is compensate d by a DLL [Gut00]. The skew compensation scheme can significantly reduc e the clock skew. However, this scheme increases the power consumption. In addition, the jitter still accumulate s along the H-tree and actually is doubled because of the feedback. This sc heme leaves the jitter an unsolved problem. 1.2.3 Distributed Oscillators or PLLs for Clock Distribution Distributed oscillators and distributed phase locked loops (PLL’s) were implemented to reduce both jitter and skew. Figure 1-3 (a) shows a distributed three-phase ring oscillators for the clock di stribution [Hal97]. Figure 1-3 (b) shows distributed PLL’s which are kept synchronized [L au01]. In both schemes, an os cillator is used to provide clock signals to a small area. Because all the oscillators ar e in phase, the clock skew is only generated by the mismatch of the buffers a nd phase detectors, whic h is small. The jitter is attenuated because all th e oscillators or PLL’s are local and the jitter is not accumulated through the global distribut ion network. However, this scheme is too complex and Master PLL PLL Phase DetectorDiagram of clock distri bution with (a) distributed ring oscillators (b) distributed PLLs Figure 1-3. (a) (b)

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6 difficult to implement. In addition, because of the distributed osci llators or PLL’s, the power consumption is significantly increased. 1.2.4 Coupled Standing-Wave for Clock Distribution A recent paper discussed a global, standing-wave cl ock distribution network [Mah03], in which the propertie s of standing waves on a tran smission line are applied. A standing wave can be formed when two iden tical waves propagate in the opposite directions on a transmission line. Along a standing wa ve, the phase is the same at all points. The standing-wave clock distri bution network is shown in Figure 1-4. Transmission lines form the network. Standing waves are formed by the sum of the incident wave and the reflected wave from a short termination. Distributed standi ng-wave oscillators are coupled together and injection-locked onto the extern al clock source to compensate the loss on the transmission lines. Ideally, the clock skew in this clock distribution network should be zero. Clock distribution network using coupled standing-wave (a) Clock distribution (b) Coupl ed standing-wave oscillators Figure 1-4. global clock SWO Clock buffer Transmission line(a) (b)

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7 Compared to the conventional clock dist ributions, a standing-wave clock distribution network can operate at mu lti-GHz with very small skew A total skew of 3.3% of a period in a 10GHz standing-wa ve clock distribution networ k was achieved over a chip area of 3mm2 [Mah03]. However, this clock distribut ion system is difficult to implement because a grid of transmissi on lines has to be constructe d on chip. In addition, the power consumption increases because of the di stributed standing-wa ve oscillators. 1.2.5 Optical Clock Distri bution Network [Mul02] Optical clock distribution was proposed by Goodman in 1984. Using optical signal instead of electrical signal to distribute the clock signa l, the optical clock distribution bypasses the clock frequency limitation of conventional interconnect technology [Mil97]. An optical clock distributi on includes a photon source, a pr opagation medium, a diffractive optics device for light re direction, an optical -to-electrical converter and an on-chip receiver to amplify the photocur rents and generate the local clock signal. Presently, most of the published optical clock di stribution systems are inter-boa rd or inter-chip. There are two main types of optical clock distribution systems di stinguished by the propagation medium. Figure 1-5(a) shows the optical clock distributi on using focused free-space, where a diffractive optical device is used to focus the light beam fr om the optical source to a desired area. The photodetectors distributed over the area convert the optical signal to electrical signal. Figure 1-5(b) shows the optical clock distribut ion using on-board or on-chip fiber-optic waveguide s. An H-tree-like waveguide network is constructed on board or on chip to guide the light to the desired locations.

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8 In an optical clock distribution system, the maximum clock fr equency can be very high. Because the signal propagates at the spee d of light, the propagation delay is almost negligible, and the skew will be small. The interconnects are isolated from the power supply and substrate noise. Jitter only comes from th e noise of clock r eceivers, which is expected to be smaller. It seems like an id eal choice. However, the optical clock distribution network is difficult to implement. The in tegration level is low and the cost is high. Furthermore, the on-chip photodetectors and r eceivers are not easy to implement. These issues made the use of optical cl ock distribution systems challenging. 1.3 Inter/Intra-Chip Wireless Cl ock Distribution Using Microwaves 1.3.1 System Description With the increase of operation frequency, the wavelength decreases and the integration of small antenna s on chip to transmit and receiv e clock signals becomes possible. At 24 GHz, the wavelength in freespace is 12.5mm, and about 4mm in a silicon substrate. The length of a quarter-wave an tenna will be 3 and 1 mm in freespace and a silicon subPhoton Source Optical clock distribution with the propagation medium of (a) freespace (b) waveguides. Figure 1-5. (a) (b) Optical input Detector Si integrated Circuit Clock beam P

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9 strate, respectively. Based on th is, two wireless clock distri bution systems utilizing integrated antennas were proposed: intra-chip and inter-chip [O97, O99, Flo00]. Figure 1-6 shows the conceptual diagrams of the intra-ch ip and inter-chip clock distribution systems. In an intra-chip clock distribution, a near 24-GHz global clock si gnal is generated by an on-chip transmitter. Transmitted by an on-chip transmitting antenna at the center of the chip. The global clock signal is picked up by a grid of receivers with an on-chip antenna across the chip [Appendix]. The received sign al is then amplified and divided down by 8 to provide the local clock signals. The inter-ch ip clock distribution uses an external transmitting antenna instead of an on-chip antenna to distribute the global clock signal across the chip. This work focuses on the inter-chip wireless clock distribut ion system evaluation and demonstration. Integrate Circuits(PC Board/MCM) ZSReceiving Antenna Transmitting Antenna R T RRR RRRR RRRR RRRR Within an IC Heatsink Conceptual diagrams of (a) intrachip (b) inte-chip wireless clock distribution system Figure 1-6. (a) (b)

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10 A single-tone sine wave instea d of square wave is used in the wireless system for clock distribution, which eliminates the re quirement for a large number of repeaters to maintain the sharp clock edges. Therefore, the power dissipation could be lower [Flo99]. The inter-chip clock distribution is invest igated because it has several advantages over the intra-chip clock distribution. In an inter-chip clock distribution system (Figure 1-6(b)), there is almost no di fference in time of flight and amplitude of received signal, and the interference effects due to the planar metal structures on ch ip should be smaller. These lead to more uniform po wer amplitude and phase distribu tions of clock signals, and smaller skew. Furthermore, with a large external antenna to transmit the global clock signal, the size of integrated receiving antennas can be reduced, and the synchronization area can be significantly increased. The heatsink and packaging issues have to be taken into consideration in an inter-chip clock distribution system. This wo rk proposes a way for incorporating a heatsink with rectangular apertures and fins in the system on the backside of the chips, with BGA MCM packages and a board on the top side of the chips. The proposed transmitter block diagra m is shown in Figure 1-7 [Flo01a]. A 24-GHz clock signal is generate d by a voltage controlled osci llator (VCO) and locked by a phase-locked loop for small phase noise or jitter. A 24-GHz power ampl ifier amplifies the signal and delivers it to the transmitting antenna. The transm itter chip will be mounted on a PCB board, and SMA c onnectors are used to connect th e transmitter output and off-chip transmitting antenna. Figure 1-8 shows the block diagram of clock receiver [Flo01a]. In the system, on-chip receiving antennas pick up the global clock signal. The received signal is ampli-

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11 fied by a low-noise amplifie r and divided down by an 8: 1 frequency divider. The output buffer delivers the ~3GHz local clock signal. Compared to the optical clock distri bution system, microwave and integrated antennas are utilized in this work instead of light to distribute th e clock signals. Microwaves propagate at the speed of light, in the same way as the optical signal. Maximum clock frequency is significantly increased. Since the propagation delay is smaller, the clock skew will be mainly gi ven by the mismatch of receive rs. Jitter will not accumulate along the global signal path, but is only dependent on the performance of receivers and Receiving Analog LNA Frequency Divider Local Clock Output Output BuffersBuffers Antenna (~24 GHz) (~3 GHz) Block diagram of clock receiver Figure 1-8. Transmitting PA fREFAntenna (~24 GHz) Loop Freq. Divider Filter PFD Phase-Locked Loop VCO Block diagram of clock transmitter Figure 1-7.

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12 noise on the chips. Hence some of the sources which increas e jitters in the conventional global clock distribution system s are removed. Because the fr equency of global clock signal is much higher than the operating frequenc y of local circuits, the disturbance in the local circuits due to the transmitted micr owaves is reduced. More importantly, the inter-chip wireless clock distribution is comp atible with the conve ntional CMOS technology. All the integrated antennas can be fabricat ed in a standard CMOS process. In addition, a planar-array antenna is introduced in this work to construct a compact inter-chip clock distribution system, whic h has the same form factor as that in desktop systems. Without the fiber-optic waveguide s and the diffractiv e optical devices in the optical clock distribution, the proposed approach is comp atible with the pr esent CMOS technology trend. 1.3.2 Challenges of Inter-chip Wireless Clock Distribution First, a requirement for imple menting a wireless clock di stribution system is sufficient power transmission gain between th e transmitting and receiving antennas. The power gain is mainly limited by the perfor mance of on-chip ante nnas, which is a key parameter that determines the feasibility of the entire system. The external antenna performance determines the area that can be sync hronized and the system skew. A high-gain and wide-beamwidth antenna is desi rable. Second, the area cons umption of on-chip antennas is another big concern. Third, j itter and skew over an area that needs to be synchronized are fundamental performance pa rameters of a clock distri bution system, which must be studied. This work will focus on the analyses of on-chip antenna performance, and the implementation of an inter-chip wireless clock distribution system.

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13 1.4 Overview of the Dissertation Theoretical analyses of on-chip antennas ar e carried out in this work using fundamental electromagnetic formulas. The feasibility of inte grated antennas is analyzed from this point of view. A measurem ent setup for inter-chip wireless interconnect is constructed to measure the power transmi ssion gain and phase of S21 between an external antenna and on-chip antennas [Bom02]. Using this setup, onchip antennas, external antennas, and the impact of a heatsink are characterized. With the measured results, the feasibility of an inter-chip wireless clock distri bution system is evaluated. In the second part of this dissertation, an inter-chip wireless clock distributio n system with a heatsink is demonstrated. One difficulty is calculating the on-chip antenna parameters such as efficiency, directivity, and impedance in the presence of multiple di electric layers and a conductive silicon substrate. However, pa rameters of antennas in a uni form, linear isotropic medium such as freespace or silicon can be calculated to provide th e basis for a qualitative understanding of trends. The electro magnetic formulas and calculat ion results are presented in Chapter 2. Chapter 3 discusses an inter-chip wi reless interconnection system, including an antenna test chamber, external antenna, testchips and the measurement setup. Three testchips were designed and fabricated in the UF clean room. The feasibility of inter-chip wireless clock distribution wa s evaluated by characterizing a Gaussian optic horn antenna and a planar array antenna, by measuring the power trans mission gain between external antennas to on-chip antennas, and by characterizing the perf ormance of on-chip antennas with different structures and lengths. The advantages and drawbacks of the inter-chip clock distribution are discusse d. A heatsink is also introduced in Chapter 3. The effects of

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14 fins and rectangular apertures in the he atsink on wave propagati on are evaluated. The inter-chip wireless interconnection system wi th a heatsink is measured, and the feasibility of wireless clock distribution in the presence of a heatsink is discussed. To realize the inter-chip cl ock distribution, there must be a scheme to start all the receivers in the synchronization area at the same time, so th at all the local clock signals have the same phase. A system initialization and start-up scheme is presented in Chapter 4 [Yan04]. Two clock transmitters that meet the re quirement of this scheme are designed and fabricated in a UMC 0.13 m logic CMOS process. Th e design and measurement results of the transmitters are presented in Chapter 4. In Chapter 5, the measurement setup and m easured results of a wireless clock distribution system using an exte rnal antenna are presented. Th e clock transmitter presented in Chapter 4 and a clock receiver developed by X. Guo and D. J. Yang are used for the demonstration. With a horn an tenna as the external trans mitting antenna, an inter-chip wireless clock distribut ion system is successf ully demonstrated, in the presence of a heatsink. Lastly, in Chapter 6, the Ph.D dissertation work is summ arized and future work is suggested.

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15 CHAPTER 2 THEORETICAL ANALYSIS OF LINEAR DIPOLE ANTENNAS 2.1 Overview The performance of integrat ed antennas plays a key role determining the performance of an inter-chip wire less clock distribution system The power transmission gain between an external antenna and on-chip receiving ante nnas determines the power a receiver can pick up and the power a transmitter has to de liver. The power transmission gain depends on clock frequency, distance between an antenna pair, and individual antenna parameters such as efficiency a nd directivity. Although the power transmission gain between an antenna pair can be measured directly usin g a network analyzer [Kim00], some important individual antenna parameters such as efficien cy, directivity and radiation patterns are difficult to meas ure. Former works have demonstrated the wireless interconnection at 7.4 and 15 GHz using 0.25 and 0.18m CMOS technologies [Flo00, Flo01b]. In addition, the research on monolithically integrated true single chip radio ( Node) shows that integrated antennas are sufficie nt for wireless interconnection up to 5m or larger separations at 24 GHz [Lin04a, Lin04b]. Projecting from these, wireless interconnection at 100 GHz or higher sh ould be possible at the end of the current ITRS. Hence, the understanding of integrated an tenna performance at high fr equencies is critical. In an inter-chip wireless clock distribution system, integrated antennas operate in a multi-layer environment consisting of silicon substrate (500m), oxide layers with metal interconnects (< 10 m) and air, which makes the analytical studies of these antennas extremely

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16 difficult. However, antennas in a linear, is otropic dielectric medi um can be evaluated using the fundamental electroma gnetic formulas. This chapter presents the matlab simulation of dipole antennas with different lengths in free space, aluminum nitride (AlN) and silicon at different frequencies. The effect of silicon resistivity on power transmission gain between a dipole antenna pair is also investigated. 2.2 Dipole Antennas in Uniform Medium 2.2.1 Arbitrary-Length Dipole An tenna Characteristics [Ula01] Antenna performance is determined by an tenna gain efficiency directivity effective area impedance and so on. In a wireless clock dist ribution system, linear dipole antennas and zigzag dipole antenna s are mainly used as the receiving and on-chip transmitting antennas be cause of their reasonable di rectivity and antenna gain, besides being easy to implemented in an integr ated circuit. The parameters of an arbitrary-length dipole antenna in a uniform medium can be directly calculated. =0 I(t) RQ(R, ) a b Figure 2-1.Linear dipole antenna

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17 Figure 2-1 shows a linear dipo le antenna placed at the or igin of a spherical coordinate system [Ula01]. A sinusoida lly varying current I(t) is de livered into the antenna from the center point. I(t) is given by For a linear dipole antenna with arbitrary length with current fed from the center, the current distribution is sinusoidal and symmetric am ong its two halves. The current amplitude must go to zero at two ends. Theref ore, the current amplitude distribution along the dipole antenna I(z) can be derived as Here k is the wavenum ber which is given by The electric and magnetic fields at any poi nt in space due to the varying current I(t) on the antenna can be calculated through the reta rded vector potential A Any elemental length on the dipole antenna can be regarded as a shor t dipole antenna, and the differential electric field from this s hort dipole at point can be expressed using the short-di pole-antenna model. cos = (2.1) --– sin --+ sin = --– (2.2)-------== (2.3) ------------------–--------------cossin --– sin --– sin = --– (2.4)

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18 The total electric field at point ca n be derived by integration over the whole dipole antenna Power density from an antenna is a key pa rameter which reflects the radiation pattern, directivity, and radiated power, eff ective area. The time-av erage power density from an arbitrary-length dipole antenna can be calculated fr om the differential electric field, which is expressed by With input current I(t), th e total power radiated from an arbitrary-length dipole antenna can be derived through inte gration of the power density over and Antenna directivity and efficiency determ ine the antenna performance. The definition of antenna directivity is the ratio of the maximum radi ation intensity to the average values of the radiation intensity over space With the time-avera ge power density the directivity of an ar bitrary-length dipo le antenna can be obtained as – –------------------cos cos ----cos – sin ---------------------------------------------------------== (2.5) ----------------cos cos -----cos – sin --------------------------------------------------------------------== (2.6) sin -----------sin == (2.7) -------------------------------------sin ----------------------------------------------------cos – sin ---------------------------------------==== (2.8)

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19 In most cases, the highest directivity from an dipole an tenna is in the direction of However, when the antenna length is long, this is no longer the case. For instance, when the antenna length is two wavelengths, the directivity is zero in this direction. When an antenna is used in a receiver the intercepted power of the receiving antenna from an incident wave with power density is where is the antenna effective area, wh ich is directly dependent on directivity The antenna efficiency is defined as the ratio of the radiated power to the total power it consumes, which includes the radi ated power and di ssipated power The radiation resistance of an arbitrary-length ante nna can be derived from the time-average radiated power -= = (2.9) --------=(2.10) -----------+ ---------------------------------+ ---------------------------------===(2.11) --------------sin -------------------------------------------------------sin === (2.12)

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20 The loss resistance of an arbitrary-lengt h antenna at high frequencies is approximately where the skin effect is taken into account. In this equation, and are the magneti c permeability and co nductivity of the metal constructing the antenna. Normally, the transverse section of an on-chip dipole antenna is rectangular. In Eq. 2.13, and ar e the width and height of the dipole antenna (Figure 2-1). Eq. 2.13 shows that the lo ss resistance is frequency-dependent. Antenna gain can be expressed by where is the antenna efficiency and is the directivity. With the above formul as, the performance of an arbitrary-length dipole antenna in a uniform medium can be estimated. When a uniform medium has a relative di electric constant the expression for time-average power density changes because the wavelength decreases by a ratio of In this equation, The expressions for antenna di rectivity and efficiency are the same as those for the free space case except that the wavelength is expressed by Eq. 2.15. ---------+ -------------------= (2.13) = -----------------------cos cos -----cos – sin ---------------------------------------------------------------------------== (2.14) --------------------------=== (2.15)

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21 When a dipole antenna is in silicon, the si tuation will be differ ent because of the conductivity of silicon. In silicon, the wave vector which is a complex number. A complex dielectric constant replac es the previously used dielectric constant Us ing the same procedure for cal culating the electric and magnetic fields and the ti me-average power densit y, the power density ra diated from an arbitrary-length dipole antenna in silicon can be expressed as From here, the directivity in the direction of is To calculate the antenna efficiency in silicon, the radiation resistance and loss resistance have to be derived. The loss resi stance is kept the same as before, and the expression of the radiat ion resistance changes to The impedance of a dipole antenna can be expressed as The value of is a function of Howe ver, it is hard to obtain the exact value of through theoretical calculation. He nce, the reactance of integrated antennas is normally obtained from measurements. + == --+ = cos ------------------– ---------------' --------cos cos -----cos – sin -----------------------------------------------------------cos ------------------– ---------------' ---== (2.16) = ------------------------------cos – sin ---------------------------------------== (2.17) --------------sin -------------------------------------------------------== (2.18) + ++ == (2.19)

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22 2-mm linear or zigzag dipole antennas are us ed in this work for most of the cases. Hence the default value of the antenna lengt h for calculation is 2 mm. Figures 2-2 2-4 show the directivity, efficien cy and effective area of a 2mm dipole antenna versus frequency in free space, AlN and 20 -cm silicon with direct ion respectively. When the frequency is high, all three parameters vary periodically wi th frequency. At certain fre-= freespace AlN 20 W-cm Si 0 100 200 300 400 500 600 0 0.5 1 1.5 2 2.5 3 3.5 Frequency (GHz)Directivity free space AlN 20 -cm Si 0 100 200 300 400 500 600 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (GHz)Radiation Efficiency free space AlN 20 -cm Si Radiation efficiency vs. frequency for a 2-mm antenna in free space, AlN and 20 -cm Si Figure 2-3. Directivity vs. frequenc y for a 2-mm antenna pa ir in free space, AlN and 20 -cm Si Figure 2-2.

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23 quencies, antenna directivity and effective area become zero. This occurs when the antenna length is 2n where n is an integer. Clearly, operation near these frequencies must be avoided. At low frequencies, both the direct ivity and efficiency increase with frequency while the effective area decreases. These tw o opposing tendencies result in an optimal 0 100 200 300 400 500 600 10-20 10-18 10-16 10-14 10-12 10-10 10-8 10-6 10-4 Frequency (GHz)Effective Aperture (m2) free space AlN 20 -cm Si TX RX R PtPrfreespace/AlN/SiFigure 2-5. A dipole antenna pair in a uniform medium Effective area vs. frequency for a 2-mm antenna in free space, AlN and 20 -cm Si Figure 2-4.

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24 operating frequency for a given antenna le ngth. This phenomena will be discussed in detail in the next section. 2.2.2 Performance of Dipole Ante nna Pair in Uniform Medium For a dipole antenna pair in a uniform medium (air/AlN/Si), as shown in figure 2-5, the power transmission gain must be calculated, which is the ratio of the power picked up by receiving antenna and the power de livered to transmitting antenna. When the antenna pair is in free spac e or AlN, using the Friis tran smission formula, the received power delivered to the receiver is Hence, the power transmission gain is is defined in Eq. 2.15. R is the dist ance between transm itting and receiving antennas. For an antenna pair in silicon, there will be an attenuation factor in the power transmission gain expression. Figure 2-6 shows the power gain versus fr equency for a 2-mm antenna pair in free space, AlN and 20 -cm silicon (Figure 2-5). In this wo rk, the default va lues of distance between a linear antenna pair and operating frequency are 5 mm and 24 GHz respectively, ---------------------------------------------------------------------------------==== (2.20) -----------------------------------------== (2.21) -----------– ----------------------------------------------== (2.22)

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25 unless stated otherwise. The power transm ission gain does not increase monotonically with frequency. The maximum gain point occu rs at an optimal fr equency in free space, AlN and silicon, due to the interaction among the frequency dependencies of antenna effective area, directivity and efficiency. The optimal frequency decreases when the 0 100 200 300 400 500 600 -80 -70 -60 -50 -40 -30 -20 -10 Frequency (GHz)Power Gain (dB) free space AlN 20 -cm Si 4 8 12 16 20 24 -160 -140 -120 -100 -80 -60 -40 -20 0 Distance (mm) + + + * f a f a f aPower Gain (dB)f a + *f a + free space AlN 10 -cm Si 100 -cm Si 1000 -cm Si 20 -cm Si 50 -cm SiPower gain vs. frequency for a 2-mm antenna pair in free space, AlN and 20 -cm Si Figure 2-6. Power gain vs. distance for a 2-mm antenna pair in different media at 24 GHz Figure 2-7.

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26 dielectric constant in creases (Figure 2-6). At fre quencies when antenna length the transmission power gains become zero because directivity becomes zero. Figure 2-7 compares the transmission gain s for the same antenna pair at 24 GHz in free space, AlN and Si with resistivity of 10, 20, 50, 100 and 1000 -cm. With the increase of resistivity, the pow er gain is increased. When resistivity is decreased, power transmission gain decreases mo re rapidly with the antenna separation. At a 20-mm separation which is sufficiently large to cover the la rgest chip size projected in ITRS for wireless clock distribution, incr easing resistivity from 10 to 20 in creases gain by ~50 dB, 20 to 100 increases by ~ 40 dB, and 100 to 1000 increases by another ~ 10 dB. When the resistivity is 1000 -cm, the power gain is almost the same as that in AlN and free space. These suggest that increasing resistivity even to 100-cm can significantly improve the antenna power transmission gain. Figure 2-8 shows the performance of an tennas with varying lengths (0.25, 0.5, 1, and 2mm) in 20-cm Si. As the antenna length is decreased, the bandwidth of the antenna gain increases. It is possible to ac hieve a relatively flat gain over many 10’s of = 0 50 100 150 200 250 300 350 400 -300 -250 -200 -150 -100 -50 0 Frequency (GHz) + +Power Gain (dB) + + + 2mm dipole1mm dipole0.5mm dipole 0.25mm dipolePower gain vs. frequency in 20 -cm Si for different antenna length Figure 2-8.

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27 GHz. For each antenna length, there is a gi ven frequency where the peak gain can be achieved. However, this peak gain is not neces sarily the global peak gain point for a given frequency. For instance at 80 GHz, the gain for the 0.25-mm long antenna pair peaks, but clearly, it is possible to get larg er gains using longer antenna pairs. The peak transmission power gain is pl otted versus corres ponding frequency in Figures 2-9. As the peak gain frequency is increased, the peak gain decreases and to compensate for this, resistivity must be increased. Figure 2-10 shows power gain versus an tenna length at 20 an d 100 GHz. The optimal antenna lengths for 20 and 100 GHz are shown on the plots, which go up when the frequency is reduced. At 20 GHz, the gain ch anges by only ~ 5 dB from antenna length of 2 mm to the optimal an tenna length of 5 mm. This suggest s that the antenna length can be made smaller but with degradation in gai n. Figure 2-11 shows th e optimal antenna length versus corresponding frequency in free space, AlN and silicon with different resistivity. 20 40 60 80 100 120 140 160 180 200 -55 -45 -35 -25 -15 Power Gain (dB)Frequency (GHz)10 -cm 20 -cm 50 -cm 100 -cm 1000 -cm Peak power gain vs. corresponding fr equency in Si with different resistivity Figure 2-9.

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28 While the peak power transmission gain str ongly depends on substrate resistivity, the corresponding optimal antenna length is weakly dependent on it. On the other hand, the optimal length is strongly depends on the relative permittivi ty. At 100 GHz, the optimal antenna length is around 1 mm, which is large. Fortunately, the gain decreases by only ~ 8 dB at 100 GHz when the ante nna length is reduced to 250 m from the optimal antenna 0 1 2 3 4 5 6 7 8 9 10 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 Antenna length (mm)Power Gain (dB) 20 GHz, 20 -cm 20 GHz, 100 -cm 100 GHz, 20 -cm 100 GHz, 100 -cm 20 40 60 80 100 120 140 160 180 200 1 2 3 4 5 Frequency (GHz)Optimal Length (mm)10 -cm 20 -cm 50 -cm 100 -cm 1000 -cm 20406080100120140160180200 Frequency (GHz) 0 5 10 15 20Optimal Length (mm) Freespace AlNPower gain vs. antenna length at 20 and 100 GHz in 20 -cm and 100 -cm Si Figure 2-10. Optimal antenna length vs. corr esponding frequency in freespace, AlN and Si Figure 2-11.

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29 length of 1 mm (Figure 2-10) The antenna length of 250 m is sufficiently small to use them quite freely on-chip. These also suggest that antenna characteris tics such as impedance can be changed with rela tive small changes in the an tenna gain. Figure 2-12 shows the power gain versus substrate resistance at 20 and 100 GHz, when the antenna length is optimal, and 0.5 x and 0.25 x the optimal length. Figures 2-13 and 2-14 show th e radiation patterns when the antenna length is optimal and 0.5 x the optimal length for varying substrat e resistivity, at 20 and 100 GHz. The radiation patterns are in dependent of substrate resistivity and become more directed at the optimal antenna length, though the patterns are similar. These also imply that in area-constrained applications, it is preferable to use sub-optimal antenna lengths. Extrapolating to 200 GHz, it should be possible to achieve th e minimum acceptable ga ins (~ -60 dB) with an antenna length of ~ 100 m and an area of 3000 m2, which is much less than the area of a bond pad. 10 100 1000 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 Resistance (-cm)Power Gain (dB)20 GHz, Opt. len. 100 GHz, Opt. len. 20 GHz, 0.5 x Opt. len. 100 GHz, 0.5 x Opt. len. 20 GHz, 0.25 x Opt. len. 100 GHz, 0.25 x Opt. len. Power gain vs. resistivity of silicon, at optimal antenna length Figure 2-12.

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30 2.3 Summary The power transmission gain between an external antenna and integrated antennas is the key parameter in an inter-chip wirele ss clock distribution sy stem. The power gain is 0.2 0.4 0.6 0.8 1 30 210 60 240 90 270 120 300 150 330 180 0 0.2 0.4 0.6 0.8 1 30 210 60 240 90 270 120 300 150 330 180 0 Radiation pattern at the optimal antenna length at 20 GHz and 100 GHz Figure 2-13. Radiation pattern at 0.5 x the optim al antenna length at 20 GHz and 100 GHz Figure 2-14.

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31 determined mainly by the perfor mance of integrated antennas. In this chapter, a method to evaluate the performance of arbitrary-length dipole antennas (directivity, radiation efficiency and effective area) in a uniform medium such as free space, AlN and silicon at high frequency is described. This work examines how the performance a nd length of integrated dipole antennas will evolve as the operating frequency of the interconnects is increased. Though this work is more direct ly applicable to in tra-chip clock dist ribution, however the conclusions should also be a pplicable to the design of onchip antennas for inter-chip clock distribution systems. Ma tlab simulations show that there is an optimal antenna length at a given operating fre quency, and that th e optimal antenna length decreases with increase of frequency. At a given frequency, the optimal an tenna length is dependent on the dielectric constant of th e substrate, but weakly depende nt on substrat e resistivity. However, the peak power transmission gain is strongly dependent on substrate resistivity. Increasing the substrate re sistivity from 20 to 100-cm improves the antenna power transmission gain by ~40dB, whic h is significant. At 100 GHz, the optimal antenna length is around 1 mm. However, it is possibl e to reduce the antenna length to 250 m with ~8dB reduction on the power tr ansmission gain. The radiation pa tterns at optimal antenna length and 0.5 x the optimal antenna length are also presented in this chapter. When the operating frequency is high en ough so that the wave length is comparable to the antenna length, the radiation patt ern of dipole antennas will change. The power density in may not be the highest. This mu st be avoided in the inter-chip clock distribution system. However, this more comple x radiation pattern coul d be utilized in an intra-chip clock distribution system at very high operating frequencies. -=

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32 CHAPTER 3 INTER-CHIP WIRELESS IN TERCONNECTION SYSTEM 3.1 Overview An inter-chip wireless clock distribut ion system [O99, Ki m98, Kim00b, Bom02, Li03] shown in Figure 3-1 has been proposed in order to in crease the area and the number of circuits synchronized by a single clock. In such a system, a global clock signal at 24GHz is transmitted through an external antenna. On-chip r eceivers with an integrated antenna pick up the signal, amplify it and di vide it down by 8 to provide the local clock signal. To study the feasibilit y of implementing such a sy stem, a setup for measuring power amplitude and phase di stributions from an off-chip gaussian optics lens horn antenna (GOA) has been reported [Bom02]. The factors in the measurement setup which can introduce errors must be better understood and eliminat ed. The gain amplitude and phase distributions of received signal from an external antenna are critical in determining the synchronization area and skew of th e inter-chip clock distribution system. Integrated Circuits (PC Board/MCM) Transmitting Receiving AntennaHeatsink Antenna Figure 3-1. Clock distribution using an off-chip antenna ZS

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33 To investigate the integrated antenna pe rformance in the system, different antenna structures with different lengt hs on different types of subs trates are evaluated. Furthermore, a clock receiver fabricated in a 0.18 m CMOS process is used to receive the clock signal from an external antenna. The measurem ent results are compared with those for an intra-chip wireless clock di stribution system [Li03]. Since the power dissipation of micropro cessors could be over 100 W, thermal management is critical and a heatsink usually made with Alum inum is placed on the backside of a chip. However, in this arrangement, the heatsink shields integrated antennas from the electro-magnetic wave tran smitted from an off-chip antenna. A technique to incorporate a heatsink in the system is also discussed in this chapter [Li04]. This work also investigates the approach to make the system compact. This chapter includes 6 sections includi ng this overview section. Section 3.2 introduces the measurement setup used to evaluate the inter-chip wireless interconnection system. The factors in the setup that affect the power transmission ga in measurements are discussed. Section 3.3 presents the characteristics of antenna s shorter than 1 mm fabricated on commonly used 0.01-20 -cm silicon substrates. In addition, clock reception between a receiver with an integrated zigzag antenna [Flo01b, Flo02] and the off-chip antenna is demonstrated. S ection 3.4 introduces a heatsink which can be used in an inter-chip clock distribution system. The effect s of fins on a commerci ally available heatsink and apertures formed in a heatsink on wa ve propagation are evaluated. Wireless connection between an external an tenna and integrated antennas in the presence of a heatsink is demonstrated. Section 3.5 presents a cloc k distribution system using an off-chip pla-

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34 nar-array antenna, which essentia lly has the same form factor as commercial microprocessors. Last, this chapter is summarized in section 3.6. 3.2 Measurement Setup Improvement 3.2.1 Measurement Setup and Its Shortcomings To evaluate the feasibility of an interchip wireless clock distribution system, the power transmission gain between receiving an tennas and an off-chip transmitting antenna has been measured. For a wireless interconne ction system, the ante nna pair forms a two port network. The power transmission gain be tween the transmitti ng and receiving antennas can be defined as where S21, S11 and S22 are the S parameters of the two port network [Kim00a, Guo02]. The S-parameter measurement setup is shown in Figure 32, which includes an HP 8510C network analyzer, a balun, semi -rigid cables, signal-signal probe, and a chamber containing an off-chip antenna. The same kinds of balun and semi-rigid cables discussed in Figure 3-2. Measurement setup RF Probe 180deg.Coupler“Balun” Semi-Rigid Cables Wave guide Assembly 3.5 mm K Mode Launch Antenna TestHP8510C Network Analyzer chamber port 1 port 2G a S 21 2 1 S 11 2 – 1 S 22 2 – --------------------------------------------------------= (3.1)

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35 [Kim00a] are used to change the differential sign al to single-side signal. It has been shown that the balun can be used even with load impeda nce other than 50 [Kim00a]. Several pairs of semi-rigid cables are bent to a shap e that can be used to connect the signal-signal probe and the balun (Figure 33). To reduce the gain and phase mismatch among Path AC and Path AB, the gain and phas e difference between the two pa ths (Figure 3-3) for different pairs of semi-rigid cables are measured. The pairs wi th less than 1-dB gain mismatch and 5-degree phase mismatch over the meas urement frequency ra nge (23-25 GHz) are used for the following measurements. The S-S probe has ground shield s near the probe tips. As a matter of fact, the probe tips can also radiate or rece ive electro-magnetic waves. The error due to probe tips can be de-embedded in the measurement [Kim00a]. The probe tips can also be used as receiving antennas in the system to pick up the clock signa l from the off-chip antenna. This is particularly useful for generating am plitude and phase distribution. Figure 3-4 shows the antenna test chamber with an off-c hip 3.8-cm diameter gaussian optic lens horn antenna [Bom02]. A vac uum ring supports the wa fer and the radiation from the antenna illuminates the bottom surfac e of the wafer (Figur e 3-4). The separation between the transmitting antenna and wafer ca n be adjusted. The multi-reflection effects Balun semi-rigid cables A B C-3dB-3dBFigure 3-3. Balun and semi-rigid cables Connected to SS probe

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36 inside the chamber cause resona nces in the measurements. To reduce the multi-path effect, the inner walls of the chamber are lined with 10-mm-thick absorb ers [Bom02]. Measurements show that the reflections of the inner wall of the opening in the chamber cover can also produce dips in the gain versus frequenc y plots. Therefore, the inner wall of the opening is also covered with 4-mm-thick absorbers. In order to characterize the off-chip antennas, two chambe r covers were fabricated. One has a 2-inch-diameter ope ning and the other has a 4inch-diameter opening. The gain amplitude and phase distributions in these two openings will be compared. 3.2.2 System Calibration The 3.5-mm two-port calibration is carried out before each meas urement. The reference planes are the inputs to the balun and waveguide asse mbly. The power transmission gain obtained from the S-parameters usin g Eq. 3.1 is actually the power gain between AbsorberThin 1cm Wafer Cover Opening Separation absorber =7.5 InchInner wall of opening Figure 3-4. Antenna test chamber with absorber liners chamber cover opening screws

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37 the port of the balun and input port of the off-chip antenna. Beca use of the power loss in the balun, semi-rigid cables and S-S pr obe, the true power tr ansmission gain between the off-chip antenna and on-chip receiving antennas is ~4dB higher than In addition, which is determined by the impedance (E q. 3.2) of on-chip antennas is significantly affected by balun, semi-rigid cables and S-S probe. Figure 3-5 shows the measured impedance of a 2-mm zigzag dipole antenna using 3.5mm two-port calibration and using one-port on-chip calibration. Th e difference shows the eff ects of the balun, semi-rigid cables and probe. These effects can be de-embedded by manual calculation. Balun, semi-rigid cables and S-S probe form a tw o-port network. With one-port 3.5mm calibration, the S-parameters of this two-port network can be obtai ned by measuring the – + -----------------= (3.2) Figure 3-5. Measured impeda nce of 2-mm zigzag dipole

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38 with varying loads (short, open and 50 (Figure 3-6). This two port network is connected in series with the antenna pair. Using Matla b, the S-parameters of antenna pair can be extracted by de-embedding the S-parameters of balun, semi-rigid cables and probe from the total S-parameters. Figure 3-7 shows th e before and after de-embedding (Figure 3-7, (a)), and measured with one-port onchip calibration (Figure 3-7, (b)). The de-embedded still oscillates with frequency (Figure 3-7), but the radius of oscillations are greatly reduced. Th e after de-embedding are lo cated at almost the same places with the measured wi th one-port on-chip calibration. 2-mm zigzag dipole 1-mm zigzag dipole Before De-embedding Balun semi-rigid cables Load S11S-S Probe Figure 3-6. Two-port network composed of balun, semi-rigid cables and probe 2-mm zigzag dipole 1-mm zigzag dipole Figure 3-7. Comparison of measured S11 and calculated S11(b) Measured S11(a) S11 before and after de-embedding 0.5-mm zigzag dipole -8dB circle

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39 Despite this, still can be used as a re lative measure to characterize system performance, since there is constant differen ce of ~ 4dB between and the true power transmission gain between antenna pair. This difference wi ll be the same in all the measurements. In addition, even the before de-embedding are inside the -8dB reflection coefficient circle on the Smith chart (Figure 3-7), which are su fficiently small. Therefore, manual calculation to de-embed the effects of balun, semi-rig id cables and probe, which is inconvenient, are not used in the following work. 3.3 Measurement Results 3.3.1 Characteristics of Receiving Antennas In order to evaluate the characteristics of wireless interconne ction between integrated antennas and an offchip antenna, a test chip c ontaining 2-mm, 1-mm and 0.5-mm zigzag dipoles, folded dipoles and linear di poles, and a loop antenna (Figure 3-8) was fabricated using a single me tal process on 0.01 and 20-cm silicon substrat es, and on a sapphire wafer. Figure 3-9 compares the power transmission gains for the different antenna structures on a 20-cm silicon wafer with a 7.5-inch separation between the wafer and Figure 3-8. Layout of the test chip Zigzag dipole Folded Dipole Linear Dipole Loop antenna

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40 off-chip antenna. The measured frequenc y range is between 23 and 25 GHz. The 2-mm folded dipole and zigzag dipole have ~3 dB higher gain than the 2-mm linear dipole, ~5 dB higher than the 1-mm lin ear and zigzag dipole and ~8 dB higher than the loop antenna Figure 3-9. Antenna gain on a 20-cm substrate. 23.023.524.024.525.0 Frequency (GHz) -55.0 -50.0 -45.0 -40.0Gain (dB) zigzag dipole folded dipole linear dipole 1-mm zigzag dipole 1-mm linear dipole loop antenna 23.023.524.024.525.0Frequency (GHz) -42.0 -40.0 -38.0 -36.0 -34.0 -32.0 -30.0Gain (dB) 7.5 inches separation 6 inches separation 4.5 inches separation 3 inches separationZigzag dipole antenna ga in as a function of the separation between a wafer and an off-chip antenna. Figure 3-10.

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41 at 24 GHz. Since the zigzag di pole has comparable gain and o ccupies less area than the folded dipole, the 2-mm zigzag dipol e is mostly used for this work. The gain plots of a 2-mm zigzag dipole on a 20-cm wafer for the separations of 7.5, 6, 4.5 and 3 inches are shown in Figure 310. The gain at 24 GHz increases by ~7 dB Figure 3-11. Zigzag dipole gain pe rformance on differ ent substrates. 3.04.05.06.07.08.0 Separation (inch) -42.0 -40.0 -38.0 -36.0 -34.0Gain (dB) 2-mm zigzag dipole20--cm substrate 23.023.524.024.525.0 Frequency (GHz) -70.0 -60.0 -50.0 -40.0 -30.0Gain (dB) Sapphire substrate 20--cm substrate 0.01--cm substratezigzag dipole, 7.5 inches separationAverage gain (24 to 24.2 GHz) vs separation for 2-mm zigzag dipole antenna. Figure 3-12.

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42 as the separation is decreased from 7.5 to 3 inches, which is consistent with the Friis formula. The EM wave undergoes attenuat ion in Si wafer. Therefore, use of high resistivity substrates should be able to reduce the at tenuation and improve th e power gain. Figure 3-11 shows the power transmis sion gain of the 2-mm zigzag dipole on three different substrates when the separation is 7.5 inches. At 24 GHz, the gain increases by 22 dB and 6 dB when the substrate is changed from a 0.01-cm to a 20-cm silicon wafer, and from a 20-cm silicon wafer to a sapphire substrate, respectively. Figures 3-12 and 3-13 show the average pow er transmission gain of the 2-mm zigzag dipole antennas for different substrates a nd separations in the fr equency range of 24 to 24.2 GHz. It clearly shows that the power transmission gain increases monotonically with the resistivity of the substrate. However, the gain difference of ~6 dB between the antennas on the 20-cm and sapphire substrates indicates that integration of antennas with 0.0120.0Resistivity (-cm) -70.0 -60.0 -50.0 -40.0 -30.0Gain (dB) 1-mm zigzag dipole 2-mm zigzag dipole7.5 inches separationinfinityAverage gain (24 to 24.2 GHz) vs. substrate resistivity for zigzag dipole antennas. Figure 3-13.

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43 good performance on moderate resistivity substr ates typically used for IC processing is possible. Instead of using high-resist ivity-substrates, thinning the wafer should also be able to reduce the attenuation in Si and improve the power transmission gain. Figure 3-14 shows Ga between an off-chip horn antenna and 1-mm zigzag dipoles on thick and thin substrates with varying resistivities. Th e separation between the wafer and off-chip antenna is 7.5 inch. The antenna pair ga in with an 1-mm zigzag dipole on 20-cm silicon substrates improves by only 1-2 dB when the wafer is thinne d from 0.67mm to 0.1mm. However, for the 1-mm dipole on 0.01-cm substrates, the power gain increases by ~10dB when the wafer is thinne d. This is expected since th e EM wave is attenuated more significantly traveling through a 0.01-cm silicon substrate. This suggests that inter-chip wireless clock distribution s hould be possible even for circ uits fabricated on high-conductivity substrates. 23.023.524.024.525.0 Frequency (GHz) -70.0 -60.0 -50.0 -40.0 -30.0Ga (dB) 20--cm thick wafer 20--cm thin wafer 0.01--cm thick wafer 0.01--cm thin waferInter-chip antenna pair gain for varying substrate resistivity and thickness. Figure 3-14.

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44 3.3.2 Gain and Phase Distributions from External Antenna To measure the relative ga in amplitude and phase dist ributions at 24GHz, instead of using a test chip with a grid of zig zag dipole antennas [Bom 02], a signal-signal probe was used as receiving antenna to map the gain and phase distributions from the off-chip antenna. This avoids the variations due to the receiving antennas. Figure 3-15 shows the spatial distributions of relative gain amplit ude and phase between the off-chip antenna and S-S probe measured in a 2-inch diameter opening. The off-ch ip antenna is 7.5 inches away (a) (b) Across a 2-inch-diameter opening wi th a 7.5-inch separation (a) relative gain (dB) dist ribution, (b) phase (d egree) distribution Figure 3-15.

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45 from the wafer. The gains ra nge between -53 and -70 dB, and phases range between -2830 and -2870 degrees over a circular area with a diameter of 3cm. Increasing the opening diameter to 4 inches reduces the gains range to ~ 5 dB (-58 to -63 dB), and phase range to 60 degrees (-3290 and -3350 degrees) over a circul ar area with a diameter of 4cm (Figure 3-16). The phase vari ations would translate to clock skew of 1.4% and 2% of a period for 2-inch and 4-inch openings (E q. 3.3) when the signal is di vided down to 3 GHz by a clock receiver [O99],[Flo01b]. The gain and phase are affected by the proximity to opening. The (a) (b) Across a 4-inch-diamete r opening with a 7.5-inc h separation (a) relative gain (dB) distribution, (b ) phase (degree) distribution Figure 3-16.

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46 gain variations also introduce skew. In the measured area, ga in distribution in the 2-inch opening is symmetric and predictable. The gain variation could be compensated by adjusting the gain of LNAs in different clock rece ivers. In addition, recei ver simulations indicate that 10-dB gain variat ion induces skew less than 1.0% of a period [Yan04]. Therefore, the total skew due to the gain and phase variations should be less than 3% of a period for both cases, which is significantly less than the t ypical skew/jitter tolera nce of 10% of a period. 3.3.3 Wireless Interconnection betwee n Receiver and External Antenna To demonstrate that the system is comp atible with a convent ional CMOS process, a clock receiver fabricated for 15-GHz in tra-chip wireless inte rconnection [Flo01b, Flo02] Analog Buffers LNA Frequency Divider (8:1) Output Buffersoff-chip Antenna (~15 GHz) separation =3 7.5 inches A block diagram of a 0.18m clock receiver with a zigzag dipole antenna. Figure 3-17. Skew– 8 --------------------------------------------------------------1 360 0 ----------= (3.3)

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47 on a 20-cm substrate utilizing a 0.18m CMOS process is used to receive the clock signal from an off-chip antenn a [Li03]. Figure 3-17 shows th e measurement setup and the block diagram of clock receiv er. A 14~16GHz signal is gene rated by a synthesizer and transferred to an external transmitting ante nna through a waveguide. The receiver picks up the signal, amplifies it, and divides it down by 8. The recei ver output can be shown on an oscilloscope or a spectrum anal yzer. Figure 3-18 shows the sens itivity of the receiver with the external antenna 3 and 7.5 in ches away from the receiver. The sensitivity is defined as the minimum power needed at th e transmitting antenna for the r eceiver to be locked to the clock at a given frequency. Th is plot shows excellent syst em operation with the -10 dBm (100 W) or less at the transmitti ng antenna between 15 16.3 GHz. Compared to this, the intra-chip cloc k signal distribution requires transmitted power of more than 15 dBm to keep the re ceiver locked [Guo02]. This along with the 13.014.015.016.017.018.0 Transmitted Frequency (GHz) -40.0 -30.0 -20.0 -10.0 0.0 10.0 20.0Power Needed at External Antenna (dBm) external antenna, d=7.5 inches external antenna, d=3 inchesSensitivity vs. frequency plots fo r different separation between the receiver and off-chip transmitting antenna. Figure 3-18.

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48 short dipole measurements suggests that the an tenna size can be reduced to 1 mm or less at 15 GHz by increasing the transmitter power to 1 mW. If the operating frequency were to be increased and the receiver is tuned to 24 GHz, the antenna size can be further reduced. Finally, the excellent system performance at 7.5-inch sepa ration suggests that the integrated antennas could be used for genera l purpose wireless comm unication over a larger distance. 3.4 Heatsink Incorporation 3.4.1 Heatsink Evaluation To evaluate the impact of presence of a heatsink, a commercially available heatsink shown in Figure 3-19 was cut to a shape th at could be used in the measurement setup [Li04]. The fins are 30 mm l ong and separated by 1.5 mm. The base-plate thickness is 6 mm. In addition, seven rectangular apertures wi th the same height of 1.5 mm and different widths were opened in the h eatsink to allow wave propaga tion through the heatsink (FigFan Fins Base-plate 7mm 12mm 9mm 8mm (A) 8mm (B) 8mm (C)8mm (D) Figure 3-19. Generic heatsi nk and modified heatsink Fins 6mm 3cm

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49 ure 3-19). The fins form a pa rallel plate wave guide (Figure 3-20). TEM wave which is similar to an unbounded plane wave could exist be tween the parallel plates. TEM wave could have any frequenc y or wavelength and it propagates at the speed of light in vacuum. The rectangular apertures also act as rectangular wave guides (Figure 3-20). The minimum cut-off frequencies in th e apertures, which are the TE10 mode wave frequencies, are dependent on the aperture wi dth, (Eq. 3.4). The minimum cu t-off frequencies in the seven apertures are shown in Table 3-1. In or der for the cut-off frequency to be less thanTable 3-1Cut-off frequenciesWidth of aperturesfc107mm21.43GHz 8mm18.75GHz 9mm16.67GHz 12mm12.5GHz x y z a b 6mm Fins Fins Figure 3-20. Waveguide models

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50 24 GHz, the width must be greater th an 6.25 mm. The phase velocity of TE10 mode wave (Eq. 3.5) is also dependent on the width. Hence, the width variations affect the phases of signals picked up by the receiving antenna. As an example, for a 24-GHz signal transmitted through a 6-mm-thick wave guide, +/0.25 mm variation of the widths causes clock skew of ~ 0.2% of a period when divided down to 3 GHz, which is sm all. The TE10 mode wave has no E-field co mponent in the direction of aper ture width. This means antennas must be placed in parallel to the shorter edges (height) of apertures (Figure 3-20). f c 10 c 2 a ----= (3.4) v p -----c 1 c a -----2 – 0.5 ------------------------------------== (3.5) AbsorberThin 1mm Wafer Cover Opening Separation Heatsink absorber =7.5 InchInner wall of opening Figure 3-21. Generic heatsink and modified heatsink

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51 3.4.2 Measurement Results With Heatsink Figure 3-21 shows the measurement setup with a heatsink inserted between the off-chip antenna and the wafe r. Fins on the heatsink are put inside the opening of the chamber cover. Figure 3-22 compares the power transmis sion gains (Eq. 3.1) between the external antenna and a 1-mm zigzag dipole antenna, when the wave goes through a 9-mm width Figure 3-23. Gain vs. frequency for different antennasseparation=7.5 inch 23.023.524.024.525.0 Frequency (GHz) -90.0 -70.0 -50.0 -30.0Gain (dB) 2-mm zigzag 1-mm zigzag 0.5-mm zigzag 0.4-mm zigzag 0.2-mm zigzag Pad Substrate 1-mm zigzag, parallel 0.3-mm zigzag with longer edgeFigure 3-22. Gain vs. freque ncy under different situations -65.0 -60.0 -55.0 -50.0 -45.0 -40.0Gain (dB) 23.023.524.024.525.0Frequency (GHz) Through the heatsink with fins Through the heatsink without fins No heatsink separation=7.5 inch 1mm

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52 aperture in heatsinks with and without fins to when th ere is no heatsink. The off-chip antenna is 7.5 inches away from the wafer su rface. It shows that th e gain through a heatsink with/without fins is ~15dB higher than the case wit hout a heatsink. The presence of apertures and fins in a heatsink can actua lly improve gain by guiding the wave. This experiment demonstrated that a heatsink could be incorporated in a system using wireless clock distribution withou t degrading the gain. Figure 3-23 shows the power transmission gains of various antenna structures through the 9-mm width aperture (Figure 3-20) in the heatsink with fins. The gains of the 1-mm zigzag dipole antenna are ~ 8 dB worse than that of the 2-mm zigzag antenna. The 0.2-mm, 0.3-mm, 0.4-mm and 0.5-mm zigzag di pole antennas have similar gains which are only ~3dB worse than that of the 1-mm antenna, ~2dB hi gher than that of a pair of bond pads, and another 5dB higher than the ca se when the probe was directly landed on the oxide layer on a substrate. Even for a pair of bond pads, with tran smitted power of 20 dBm, the received power will be ~ -30 dBm whic h should be sufficient for system operation [Guo02]. This indicates that the receiving an tenna size could be extremel y small for clock distribution systems using an external an tenna. When the antenna lengt h is reduced to 0.2 mm and below, it should be possible to reduce the he ight of the aperture to ~ 0.3 mm and below. The bottom plot in Figure 3-23 is for a 1-mm zigzag dipole orie nted in parallel with the longer aperture edge. The gain was severely re duced, which is consistent with the fact that there should not be E-field along this edge. Figure 3-24 shows the re lative power gain and S21 phase distributions of a 1-mm zigzag dipole antenna in ap ertures with varying widths at 23.25 GHz. Higher gains and

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53 larger phase delays are measured in larger ap ertures. The gain dist ributions are symmetric and the highest gain occurs in the center. These indicate th at using apertures of the same size is preferable to reduce gain amplitude and phase variations thus skew. Figure 3-24 also suggests that more than on e antennas could be placed in one aperture with acceptable gain and phase variations. Am ong the four 8-mm apertures, power gain and phase vary -6.0-4.0-2.00.02.04.06.0Location in the aperture (mm) -80.0 -70.0 -60.0 -50.0Relative Gain (dB) through 7 mm aperture through 8 mm aperture (A) through 8 mm aperture (B) through 8 mm aperture (C) through 8 mm aperture (D) through 9 mm aperture through 12 mm apertureFigure 3-24. Gain and phase vs. lo cation in each aperture at 23.25 GHz -6.0-4.0-2.00.02.04.06.0Location in the aperture (mm) -260.0 -220.0 -180.0 -140.0 -100.0 -60.0 -20.0Relative Phase (degree) through 7 mm aperture through 8 mm aperture (A) through 8 mm aperture (B) through 8 mm aperture (C) through 8 mm aperture (D) through 9 mm aperture through 12 mm aperture

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54 due to the diffraction from ad jacent apertures and output power variation of the transmitting antenna. This indicates th at apertures should be distri buted with a regular pattern. 0246 Aperture Row Number -56 -54 -52 -50 -48 -46 -44 -42 -40Relative Gain (dB) Apertures in Column A Apertures in Column C Apertures in Column B1357 0246 Aperture Row Number -880 -860 -840 -820 -800 -780 -760Relative Phase (degree) Apertures in Column A Apertures in Column C Apertures in Column B1357 Figure 3-25. Relative gain and phase at center of each apertures at 24GHz 6mm 3cm A BC

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55 To evaluate the effect of heatsink on gain and phase distributions, a new heatsink in which rectangular apertures of the same size (7mm x 1.5mm) are distributed evenly is fabricated (Figure 3-25). Agai n, a signal-signal probe was used as the receiving antenna to measure the relative gain and phase in the center of each aperture. Figure 3-25 shows the relative gain and phase when th e S-S probe was placed in the center of the apertures. The relative gain varies from 50dB to -55dB, and the relative phase varies from -795 degree to -865 degree. The variation is almost the same as the case without a heatsink. This indicates that the area that can be synchronized will not change even when a heatsink is put into the system. Figure 3-25 also shows that the middle column apertures have higher gains and lower phase delays, which are cons istent with the case without a heatsink. A concern for having apertures in a heatsi nk is the potential for generation of hot spots. A preliminary simulatio n study suggests that the temp erature inside a 5 mm x 1.5 mm aperture of a 12 mm x 12 mm chip is ~2 degree higher after 60 seconds. This difference should decrease, if the ap erture height is reduced fr om 1.5 mm to 0.3 mm. Further studies of thermal issues are needed. Potential solutions to cope with the hot spots are under study. 3.5 A Compact Inter-chip Clock Distribution System To make the inter-chip clock distribu tion system compact, a system with a low-profile planar array antenna (Model: PLA 24-2, Dorado Intl. Co.) is proposed (Figure 3-26), which should have almost the same form factor as commercial microprocessors used in desktops. The planar array antenna operates in a freque ncy range of 24-24.25GHz with an antenna gain of 21dBi. In this setup, more than one chips ca n be placed on top of

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56 the heatsink and synchronized at the same time. A fan could be installed on one side of the heatsink (Figure 3-26). The same measurement setup (Figure 3-2) and antenna test chamber (Figure 3-27) are used to evaluate the planar-array antenn a. Relative gain amplitude and phase distributions were measured in the same way as befo re for the cases with and without a heatsink. Again, a signal-signal probe was used as th e receiving antenna. Fi gure 3-28 shows the relAntenna IC with Receiving Antennas Heatsink Low-profile Antenna Antenna Side View Front View Absorber Wafer Vacuum Ring Heatsink absorber planar-array antenna Inner wall of apertureFigure 3-26. Proposed inter-chip clock distribution system Figure 3-27. Antenna test chamber

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57 ative gain amplitude and phas e distributions measured in a 4-inch diameter opening at 24GHz. The heatsink is not included in the system. The gains range between -54dB to -61dB and phases range between -591 degree to -658 degree over a circular area with a diameter of 35mm. When the signal is divided down to 3 GHz, the phase variation will transl ate to a clock skew of 2.3% of a period (Eq. 3.3). Figure 3-29 shows the relative gain amplit ude and phase at the center of each rectangular apertures in the second he atsink when the planar array an tenna is used as the trans(a) (b) Across a 4-inch-diameter opening with a planar array antenna (a) relative gain (dB) distribution, (b) phase (degree) distribution Figure 3-28.

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58 mitting antenna. Phases range between -500 to -560 degree, which translates to a clock skew of 2% in a period when the signal is divided down to 3GHz (Eq. 3.3). The maximum gain variation is ~10 dB. The total clock skew due to both the gain and phase variations is ~ 3% of a period at 3 GHz, whic h is similar to the case when a Gaussian optics lens horn antenna is used. This indicates that the low-profile inter-ch ip clock distribution system is feasible. 01234567 Aperture Row Number -56 -52 -48 -44 -40 -36Gain (dB) Apertures in Column A Apertures in Column B Apertures in Column C 01234567Aperture Row Number -580 -560 -540 -520 -500 -480 -460 -440Relative Phase (degree) Apertures in Column A Apertures in Column B Apertures in Column CRelative gain and phase at cent er of each apertures at 24GHz Figure 3-29.

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59 3.6 Summary In this chapter, the characteristics of an tennas for inter-chip wireless clock distribution system are described. The relative gain amplitude and phase distributions in 2-inch and 4-inch diameter ope nings with an off-chip antenna 7.5 inches away from the wafer have been measured. It is shown that a 3-GHz clock signa l over a 4-cm-dia meter circular area with skew due to path mismatches le ss than 3% of a period can be provided by a 24-GHz wave incident from an off-chip gaussian optics lens horn antenna. A clock receiver fabricated in a 0.18m CMOS process is used to receive a 15-GHz clock signal from an external antenna. The measurements show that the system using an external antenna has 20-30 dB more margin over the in tra-chip wireless cl ock distribution system [Guo02]. This indicates that 0.5-mm or even shorter receiving antennas can be used in inter-chip clock distribution systems. Using fins and rectangular apertures in a heatsink as waveguides, wireless interconnection in the presence of a commercially available heat sink with the off-chip antenna over distances of 7.5-inches and less is demo nstrated. Use of a he atsink improves power transmission gain by guiding the EM waves. The measured result s also show that the heatsink with regularly distributed apertures does not change the gain and phase distributions. Based on this, an inter-chip wi reless clock distribut ion system using a planar array antenna was proposed and characterized. Th is system essentially has th e same form factor as commercial microprocessors. The measured results show the feasibility of a low-profile inter-chip clock distribution system.

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60 CHAPTER 4 CMOS CLOCK TRANSMITTER 4.1 Overview In an inter-chip wireless clock distribut ion system, the clock transmitter plays an important role. It generates the 24-GHz global cl ock signal and delivers it to an external antenna. To make the system feasible, the pow er level of the transm itted clock signal must be sufficient to be locked by the clock recei vers. In addition, to test the clock receiver locking, the clock signal should be able to be tuned over a larg e frequency range. When receivers lock onto the transmitted global cloc k signal, the global cl ock signal jitter will translate into the local clock signal jitter. Therefore, the global clock signal should also have small jitter or phase noise. In the system, the local clock signals at different receivers should be synchronized onto one unique global clock si gnal and in phase. However, when the system is powered up, the frequency dividers in different receivers start up wi th random phases. This causes skew. To eliminate this problem a technique to start up all the receivers in a synchronized state is proposed [Yan04]. Th e transmitter will generate a global clock signal with a no-signal-transmission period. The clock receivers should be ab le to recognize this no-signal-transmission period and genera te pulses to initialize and si multaneously start up all the 8:1 dividers. Two clock transmitters implementing this system are designed and fabricated in a UMC 0.13 m logic CMOS process. They share th e same circuit topology. The power sup-

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61 ply voltage of the transmitters is 1.2V. To stream line the task, an LC VCO without a PLL is fabricated. The frequency of VCO is direct ly controlled by a bias voltage. An LC VCO can achieve lower phase noise and higher oscill ating frequencies than ring oscillators. A symmetrical negative resistance structure is used in the VCO to lower power consumption. An on-chip Class-AB power amplifier is used to increase the power level of output clock signal. The clock frequenc y of the first clock transmitte r is designed to be 24GHz. Due to the improper modeling of the metalto-metal parasitic cap acitance of MOS varactors, the clock frequency is shifted down to 17GHz. To correct this problem and to make the operating frequency be tter suited for the 0.13 m process, a second 20-GHz clock transmitter is de signed and tested. This chapter is composed of 6 sections including this overview section. The second section introduces the init ialization and start-up methodol ogy of the inter-chip clock distribution system [Yan04]. Section 4.3 presents the desi gn and implementation of the clock transmitters, including the VCO, power amplifier, 512:1 frequency divider and no-signal-transmission period generation sche me. Section 4.4 shows the measurement setup and measured results of the 17-GHz clock transmitter. Both the on-chip measurement results and on-board m easurement results are presen ted. The problems associated with the 17-GHz clock transmitter are also di scussed. Section 4.5 presents the design and measured results of the 20GHz clock transmitte r. Finally, conclusions are presented in section 4.6. 4.2 Initialization and Start-up Scheme The receiver initializat ion and start-up scheme used in the inter-chip wireless clock distribution system is shown in Figure 4-1. The transmitter generates the 24-GHz global

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62 clock signal with a no-signal-tran smission period and delivers it to an external transmitting antenna. The clock receiver includes a detect or and an 8:1 frequency divider. The signal picked up by the receiving antenna is si multaneously fed into the clock divider and detector. The detector recogni zes the transition from the si gnal-transmission period to the no-signal-transmission period and generates one pulse (initializ ation pulse). This pulse is used to stop and initialize the 8:1 frequency di vider. Then the detector generates a second pulse (start-up pulse) using the transition from the no-signa l-transmission to the signal-transmission period. Th e divider is kept in the initialization st ate until the start-up pulse is received. After the star t-up pulse, the divider is placed into the divide mode and is started by the first clock tran sition from low to high (Figur e 4.1). The transition delay time from the initialization mode to the divide mode is de fined as latency. If the latency time is not zero and varies in different receivers, the variation will tr anslate to clock skew. A technique is incorporated to elim inate the latency in the receiv er [Yan04]. In addition, to make the system feasible, the 8:1 fr equency divider and detector must have small input amplitude and temperature sensitiv ity. Furthermore, they shoul d have a maximu m operating freDetector INI starting pointEnvelope LNA 1/8 Divider PA Buffer VCO 1/512 Divider Buffer TX RX /bufferFigure 4-1. Initializat ion and start-up scheme

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63 quency up to 24GHz. The design and measurement of divider and start-up circuits have been discussed in detail in anot her research dissertation [Yan04]. To improve testability, a clock signal with periodic no-signal-transmission periods is generated by the clock tran smitter. As shown in Figure 4-1, the 24-GHz clock signal generated by the VCO is divided down by 512 to create a low-fre quency control signal. This signal controls the output of transmitte r to generate the periodic no-signal-transmission periods. The design and meas ured performance of clock tr ansmitter that satisfy the proposed system requirements are disc ussed in the following sections. 4.3 Transmitter Design The block diagram of clock transmitter is shown in Figure 4-2. An on-chip VCO generates a 24-GHz clock signal and delivers it to the powe r amplifier (PA) and divider. To improve the flexibility for testing, an option to disable the VCO and input an external clock signal from a synthesizer through four GSSG pads at node A has been incorporated. Furthermore, the VCO and its si ngle-stage buffer can be separa tely characterized using the same four pads at node A, wi th the other parts of the transmitter circuit disabled. The on-chip VCOsynthesizer 512:1 divider buffer PA buffer on-chip antenna Go to oscilloscope as triggeringAVCO bufferBFigure 4-2. Clock transmitter block diagram

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64 24-GHz clock signal is divided down by 512 to genera te a digital clock signal. A logic circuit with a delay modul ates the duty cycle of the digital clock signal to generate periodic low-voltage state with duration of 1.2ns (Figure 4-2). This cont rol signal is used to control the PA to output the 1.2-ns nosignal-transmission pe riods in the transm itted clock signal. There are two options on the output side. The output clock signal from PA can be delivered to an on-chip zigzag transmitting antenna which can be used fo r intra-chip clock distribution [Flo02]. The antenna of the transmi tter can be diced off, and the transmitter can be placed on a PC board and connected to an external antenna usi ng SMA connectors. The control signal is taken out th rough an output pad (Figure 4-2), and used to trigger an oscilloscope. The transmitter is fabr icated using the UMC 0.13m logic CMOS process. Figure 4-3 shows the die photograph of the clock transmitter with a 2-mm zigzag antenna. The 780 m VCO 780m Figure 4-3. Die photograph of clock transmitter 2mm Vctrl VDD_VCO VDD inVbias VDD_VCO in+ VDD DCgen switch Trigger enb Gnd out+ Gnd Gnd outGnd

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65 chip area without the zi gzag antenna is 0.78x0.78 mm2, while the active area is 0.55x0.4 mm2. 4.3.1 Voltage-Controlled Oscillator As discussed, a voltage-controll ed oscillator is used to generate the clock signal. The VCO must have low phase noise to decr ease the local clock signal jitter. Figure 4-4 shows the circuit schematic of the VCO. A symmetrical nega tive resistance structure is utilized. For LC-VCO’s, the overa ll Q of LC-tank is the key factor that determines the phase noise performanc e [Hun00]. Normally, the Q factor of overall LC-tank is determined by the inductor. A differ ential spiral inductor with a polysilicon patterned-ground shield (PGS) is used in the VCO. The value of the inductor is chos en to be 400pH, with a Q-factor of 15 at 24-GHz. The varactors are chosen to be 50fF, and implemented with high-Q MOS capacitors [Hun00]. The measured Q factor of th e MOS varactors are ~ 30 at 24GHz. When the VCO is oscillati ng at the equation has to be satisfied, where is the effective tran sconductance and is the impedance of M4M3Vtune M2M1 Figure 4-4. Circuit schematic of VCO and buffer Buffer Buffer =

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66 LC-tank. Therefore, a larger L or a smaller C/L ratio in an LC VCO requires a smaller and reduces the power consumpt ion [Hun00]. In addition, the current-reuse topology (Figure 4-4) increases the total effective whic h reduces the current consumption. The sizes of cross-coupled PMOS and NMOS transistors in the VCO are 24 m/120nm and 12 m/ 120nm, respectively. The VCO current consumption is ~2mA. Close-in phase noise is a concern for CMOS VCO’s because of the high 1/f noise of MOS transistors. Most of the close-in noise is from the up convers ion of the 1/f noise of the tail transistor. Since 1/ f noise is inversel y proportional with the gate area, a PMOS with large width and length (160 m/240nm) is used as the tail transistor to reduce the close-in phase noise [Yan04]. Furthermore, compared to NMOS, PMOS transistors have lower thermal noise and 1/f noise Hence, use of PMOS tail tr ansistor can also improve the phase noise performance at larger offsets from the carrier [Yan04]. According to the LTI phase noise theory, the symmetrical negati ve resistance VCO structure can minimize the up-conversion of th e 1/f noise, thus redu ce the close-in phase noise. In addition, this structure will allow larger output signal swings at a given bias current level, which also improves the power effi ciency of the VCO at given phase noise performance [Lee00]. The VCO buffer is shown in Figure 4-4, which is an inductively-loaded common-source amplifier. The gate capacitances of the buf fer NMOS transistors (20 m/ 120nm) are included into the LC-tank design. 4.3.2 512:1 Divider and Logic Circuits Figure 4-5 shows the block diagram of the 512:1 frequenc y divider employing source-coupled logic ci rcuits (SCL). The SCL divide r achieves higher maximum operat

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67 ing frequency and better noi se performance compared to TSPC dividers [War89, Flo00, Flo01a]. The 512:1 divider is constructed by 9 cascaded SCL dividers A 2:1 SCL divider can operate in one of two modes. The first one is the la tched mode, which occurs when the input signal swing is large. In the latched m ode, the divider utilizes its latching property. The second is injection locked mode, which oc curs when the input signal swing is small QbQ CLK CLK b QbQ CLK CLK b (2:1) (2:1) M3 M1 M5 M2 M7 M6 M4 M8 VddVdd QbQCLKCLK b M13 M11 M15 M12 M9 M16 M14 M10 VddVdd Qbi CLK b CLK Qi ...7 stages... Figure 4-5. Block diagram of 512:1 frequency divider

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68 and its fundamental or one of the harmonics is close to th e frequencies of harmonics for self-oscillation of SCL divider. All the 9 stag es of the SCL divider operate in the latched mode, because the input voltage swing of each stage of the SCL divider is large. The performance of first stage SCL divider limits the maximum operating frequency of the 512:1 divider. Tabl e 4-1 shows the channel widths of the devices in the first 4 divider stages. The channel length of all th e devices are 120nm. To increase the maximum operating frequency, the gate s of the PMOS transistors M7,8,9,10 are grounded to operate them in the linear region. This re duces the RC time c onstants at nodes Q, Qb, Qiand Qbi. Simulations show that the maximum ope rating frequency of the 512:1 divider is ~30GHz. The current consumption of divider is ~7mA. The block diagram of the control-signa l-generation circuit following the 512:1 divider is shown in Figure 4-6. The output of the divider has a 50% duty cycle. For receiver initialization and st art-up, a no-signal-tran smission period of ~1 -ns is required in the transmitted global clock si gnal. Therefore, the contro l signal should have periodic low-voltage state with ~1ns duration. A 1.2-ns delay circuit and a NAND logic are used to modulate the duty cycle to meet this requirement (Figure 4-6). Table 4-1Transistors sizing for the first 4 stages SCL dividerFirst StageSecond StageThird StageFourth Stage M7, M8, M9, M102.6 m/ 120nm 1.4 m/ 120nm 1 m/ 120nm 0.9 m/ 120nm M3, M4, M13, M145 m/ 120nm 3.0 m/ 120nm 1.9 m/ 120nm 1.9 m/ 120nm M5, M6, M15, M161.6 m/ 120nm 1.4 m/ 120nm 1.7 m/ 120nm 1.7 m/ 120nm M1, M2, M11, M128 m/ 120nm 2.5 m/ 120nm 1.5 m/ 120nm 1.5 m/ 120nm

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69 4.3.3 No-Signal-Transmissi on Period Generation Scheme Figure 4-7 shows the scheme to generate the no-signaltransmission period using the control signal. Vin+ and Vinare the out put signals from the VCO buffer. They have the same amplitudes and 180o phase difference. The five PMOS transistors M1-M5 are controlled by the control signal Vcontrol. When Vcontrol is high, the five PMOS transistors are off; and the clock signal will go through to the output st age (PA) and be delivered to the transmitting antenna. When Vcontrol is low, the five PMOS tr ansistors are turned on. At nodes A and B, the two clock signals with 180o phase difference will cancel each other. In 512:1 SCL Divider 1.2ns Delay NAND buffer Output of VCO Vcontrol Figure 4-6. A block diagram of co ntrol-signal-generation circuit Clk1 Clk2 Vcontrol Clk1 Clk2 VcontrolVcontrolVcontrolVin+ VinVinVin+ Vout+ VoutA BM1M4M3M5M2Figure 4-7. Circuit schematic of ge nerating no-signal-tr ansmission period Power Amplifier

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70 addition, three PMOS transistor s M3, M4 and M5 at output nodes will short the output to AC ground. Therefore, a no-signal-transmission period is generated when the control signal is low. In order to redu ce the rippling time during the transition between signal-transmission to no-signal-transmission states, the Q of the output ne twork of PA must be small. The Q is chosen to be 1. Figure 4-8 shows th e simulated waveforms of the output clock signal and the control signal. A 1.2-ns no-signal-transmission period is successfully generated. The second edge of the no-signal-transmission period wh ich determines the receiver start-up is also shown in Figure 4-8. 4.3.4 Power Amplifier (PA) Figure 4-9 shows the circuit schematic of the power amplifier (PA). The gate bias of the active devices M1, M2 is connected to 1.2V which is well above the threshold voltage. Hence the PA works as a class A amplifier. L1, C1 constructs the output matching network. Due to the large size of transistors M1, M2, Ccouping may not be sufficiently large compared to the gate capacitance of M1, M2. To reduce the voltage drop across Ccouping, Figure 4-8. Simulated output clock signal and control signal

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71 Lg is used to tune out the gate cap acitance. The gate DC bias of M1, M2 are also provided through Lg. In an inter-chip wireless clock distribu tion system, when the receiver sensitivity is -40dBm [Flo01a, Flo02], with 40dB antenna pair power tran smission gain, the minimum transmitted power level should be 0dBm. In the system, the tran smitter has to be placed on a PC board and connected to an external an tenna through a balun. Therefore, the load on each side of output is 50 The power amplifier is tuned with a 50 load. The maximum output power is designed to be ~9dBm (the voltage ampl itude on each load is 0.6V). Figure 4-10. The simulated differen tial output waveform from PA Load Vin-Figure 4-9. Circuit schematic of output power amplifier C1M2L1 LgVin+M1 LoadC1L1 Lg Ccoupling

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72 Hence the current swing in the NMOS transistor s is at least 24mA. To support this large current swing, the NMOS transist or sizes are chosen to be 60 m/120nm. Figure 4-10 shows the simulated differen tial output waveform of the PA. The waveform is almost sinusoidal. 4.4 Measured Results of Transmitter 4.4.1 VCO The output spectrum and single-sideband phase noise of the VCO including its single stage buffer are obtaine d using a spectrum analyzer. Figure 4-11 shows the output spectrum and phase noise of the VCO. The os cillating frequency is 17.2GHz, with an output power level of -13.2dBm. The VCO core consumes 2mA currents from a 1.4V power supply. At 1-MHz and 3-MHz offsets, the phase noise are -106dBc/Hz and -116dBc/Hz, respectively, which are exce llent. The VCO oscillating frequency has shifted down by 7GHz from the designed value of 24GHz be cause of the improper modeling of the Figure 4-11. Output phase noise and spectrum of VCO -13.2dBm 17.2GHz

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73 metal-to-metal parasitic capac itance of MOS varactors [Ca o05a]. The parasitic capacitance of metal connections to the varactor increases the cap acitance by a factor of 2. Figure 4-12 shows the VCO tuning range, which is ~600MHz. The narrow tuning range is also due to the large metal-to-metal parasitic capacitanc e of MOS varactors. 4.4.2 Transmitter Output Signal With the 2-mm zigzag ante nna diced off, the transmi tter is measur ed on chip. An Agilent 86100B Oscilloscope is used to characterize the transmitter. Figure 4-13 shows the block diagram of the meas urement setup. The low frequenc y control signal is used as the triggering signal of the osci lloscope and is also connected to the channel 2 of scope. The output signal from PA is shown on channel 1. A GSSG pr obe, semi-rigid cables and a Figure 4-12. VCO tuning range 0.00.40.81.21.62.0 Control Voltage (Volt) 16.8 17.0 17.2 17.4 17.6Frequency (GHz) Vdd=1.4V Ic=2mA

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74 balun change the differential output signal to a single-side signal. As mentioned before, the source of clock signal coul d be either the on-chip VCO or an external synthesizer. Figures 4-14 and 4-15 show the waveforms of the control sign al and the transmitter output signal, with the on-chip VCO and an external synthesize r as the clock signal source, respectively. The periodic no-signal-tran smission with 1.2ns dur ation are successfully generated. The settling time for the transi tion between no-signaltransmission to signal-transmission states is ~ 50ps or ~ 1 period. Figure 4-16 shows the transmitter output spectrum when the VCO is used as the cloc k signal source. The 17.011GHz clock signal with a power level of -23.17dB m and the 33.2MHz harmonics due to the periodic no-signal-transmission periods are s hown. The output power level is low, even with the power loss in probe, semi-rigid cables, balun a nd cables de-embedded. This issue will be discussed shortly. The measurements showed th at the 512:1 divider works up to 24GHz, provided that the divider Vdd is increased to 2.2V. In an inter-chip wireless clock distributio n system, the transmitter has to be placed on a PC board and connected to an external antenna. Therefore, the performance of the transmitter on board has to be evaluated. A three-layer PC board for the transmitter is on-chip VCOsynthesizer 512:1 divider buffer PA buffer oscilloscope triC1 C2 VCO buffer balun Probe Figure 4-13. Measurement setup of the transmitter

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75 designed and fabricated using Protel DXP. The size of th e transmitter board is 30 x 30mm2. Figure 4-17 shows the transm itter board with a transmi tter chip mounted in the center. The measurement setup is the same as before except that an external PA is used to increase the output power leve l (Figure 4-17). Figure 4-18 shows the waveforms of control signal and transmit ter output signal with the VCO as the clock signal source. Like the Figure 4-15. Waveforms of control signal and clock signal (VCO as the clock source) Waveforms of control signal and clock signal (synthesizer as the clock source) Figure 4-14.

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76 on-chip measurements, periodi c no-signal-transmission with 1.2ns duration is observed in the transmitter output waveform. Transmitter board Balun trigger PA oscilloscope triC1 C2 Figure 4-17. The measurement setup of using a transmitter on a PC-board 17.011GHz -23.17dBm Transmitter Chip 30mm 30mm Figure 4-16. Transmitter output spectrum

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77 The transmitted clock signal ji tter is one of the key pa rameters in the inter-chip clock distribution system whic h determines the quality of the local clock signals. Figure 4-19 shows the RMS jitter of th e transmitter output signal, whic h is 2.4ps. This is the total jitter including the triggering si gnal jitter and the 1.2ps (1.5ps maximum) instrument characteristic RMS jitter of the oscilloscope. When the triggering signal jitter and instrument characteristic jitter are de-e mbedded, the RMS jitter of th e transmitter ou tput signal is between 0.42ps (best case) and 1.47ps (worst case), which is small. Figure 4-18. Waveforms of control signal and clock signal (Transmitter on board) Figure 4-19. RMS jitter of the output clock signal 0.01.02.03.04.05.0 t (ns) -0.1 -0.05 0.0 0.05 0.1Vout (V)

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78 4.4.3 Output Power As mentioned earlier, the tran smitter output power level is low. With a synthesizer as the clock signal source, the transmitte r output power versus clock frequency is measured and shown in Figure 4-20. The power loss in signal paths are de-embedded. It shows that the output power decreases rapidly from ~3dBm at 26 GHz to -15dBm at 16 GHz. A possible reason for the rapid drop of output power could be a higher Q factor at output node of the PA than expected. Figure 4-21 s hows the output matching of the PA, which indicates that the output matc hing is broadband and the output Q is low. Therefore, there must be some other nodes in the transmitter with a high Q-fa ctor. Review of the transmitter circuitry shows that the Q-factor at node B is too high (Figure 42). It can account for the rapid drop of output power as the frequency is decreased. In addition, the resonant frequency at node B was mistuned wh ich further reduces the output power level. Fortunately, in an inter-chip clock distri bution system, an external PA can be used to increase the 161820222426 Frequency (GHz) -15.0 -10.0 -5.0 0.0 5.0Output Power (dBm) Figure 4-20. Output power vs. clock frequency

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79 power lever of the clock signal delivered to the external ante nna. Therefore, this transmitter can still be used for the system demonstration. The input DC bias of the power amplifier is connected to Vdd, instead of having a separate pin. As a result, the current cons umption in the PA is above 80mA, which is unnecessarily high. In the sec ond version of the transmitter, as will be discussed, this problem has been corrected by adding a separate pin for the bias of PA. 4.5 A 20-GHz Clock Transmitter To correct the deficiencies mentioned a bove, a new clock transmitter is designed and fabricated, using the UMC 0.13 m logic CMOS process. Because the maximum operating frequency of the clock receiver is ar ound 20GHz, the new clock transmitter is tuned at ~20GHz. The same circuit topology is used to construct the transmitter. Figure 4-22 shows the die photograph of the new clock transmitte r with a 2-mm zigzag antenna. The chip area is the same as the 17-GHz clock transmitter. 141618202224 Frequency (GHz) -14.0 -12.0 -10.0 -8.0 -6.0S22 (dB) Vdd=1.8V Vdd=1.2VFigure 4-21. Power amplifier output matching

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80 4.5.1 VCO with Newly Designed Varactors The same circuit schematic is used to design the 20-GHz VC O (Figure 4-4). To avoid the frequency shift, a new varactor is designed to reduce the metal-to-metal parasitic capacitance, while keeping th e Q-factor high [Cao05a]. Fi gure 4-23 shows the layout of the new varactor. Minimum gate length is used to reduce the series resistance and achieve high Q-factor at the expens e of reduced tuning range. Fo r MOS varactors used in an LC-VCO, because the bottom plate (n-diffusi on/n-well) is AC ground, the parasitic capacitance between the metal connected to the di ffusion and ground is not a problem. Therefore, metal 2 is used to connect the n-diffusions. Metal 8 is us ed to connect the gates, and the areas of metals 1-7 are ve ry small, which significantly reduce the parasitic capacitance between metal connected to gates and the me tal connected to n-diffusion and ground. In Figure 4-22. Die photograph of th e 20-GHz clock transmitter 780 m 780 m 2mm VCO Vctrl VDD_VCO VDD_PA inVCObias Bias_div in+ VDD DCgen switch Trigger enb Gnd out+ Gnd Gnd outGnd PAbias

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81 addition, the metal spacings are made larger to further re duce the parasitic capacitance. The Q-factor is ~30 at 24GHz the same as before, and Cmax/Cmin ratio is ~1.75. The 20-GHz VCO is measured using a spec trum analyzer. Figure 4-24 shows the output spectrum and single-sideba nd phase noise of the VCO. The oscillating frequency is 20.11GHz, which is almost the same as the design target (20GHz). The VCO core consumes 2mA current from a 1.5 V power supply. At 1-MHz and 3-MHz offsets, the phase noise are -106dBc/Hz and -116dBc/Hz, respective ly, which is the same as before. Considering the 20GHz oscillating fr equency which is 3GHz higher, the phase noise performance is actually improved. Figure 4-25 shows the tuning range of the 20-GHz VCO. The tuning range is increased to ~3GHz, which is much larger than ~600MHz of the first version. 0.64m 0.4m Metal2 Metal 8 Metal 8Figure 4-23. Layout of the newly designed MOS varactor

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82 4.5.2 Reduction of Q-Factor at Intermediate Node In the first version of clock transmitter, the Q-factor at node-B is very high (Figure 4-2). Because of this, a small shift of resonant frequency at node-B due to the improperly modeled parasitics will lead to a rapid drop of the output pow er. The Q-factor at node-B is 100 kHz 10 MHz FREQUENCYOFFSET RL-50dBc/Hz 10dB/SPOTFRQ=100.0kHz FROM17.66GHzCARRIER -81.83dBC/Hz 0.00.51.01.52.0 Vtune (V) 20.0 21.0 22.0 23.0 24.0Oscillating frequency (GHz) -22.33dBm 20.11354GHz MKR RBW300kHzVBW300kHzSWP50.0ms STOP20.12320GHz START20.10320GHz RL0dBm ATTEN10dB 10dB/ MKR-22.17dBm 20.11320GHz K 20.11GHz-106dBc/Hz -116dBc/Hz Figure 4-24. Output phase noise and spectrum of the 20-GHz VCO Figure 4-25. Tuning range of the 20-GHz VCO

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83 mainly determined by the inductor in the buffe r (Figure 4-2). To re duce the inductor Q, a 200resistor is connected in parallel with the 500-pH inductor wi th Q-factor of 15 at 20GHz, as shown in Figure 4-26. The resistor reduces the tank Q to 2.6, while not affecting the voltage headroom. 4.5.3 Power Amplifier Redesign Figure 4-27 shows the updated circuit struct ure of the power amplifier, where a separate pin is used to provi de the DC bias of the input. The PA is tune d at 20GHz. By changing the DC bias voltage, th e power amplifier can be made to work as a class A or a 200500pH Q=15 at 20GHzFigure 4-26. 500-pH spiral inductor with a 200parallel resistor VcontrolVcontrolVcontrolVin+ VinVinVin+ Vout+ VoutA BM1M4M3M5M2 Vbias Vbias Power AmplifierOutput stage of clock transmitte r, including PA and no-signal-transmission generation circuits Figure 4-27.

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84 class B amplifier, with di fferent output power level and drain efficiency. When Vbias is well above the threshold voltage, the PA is a class A amplifier. The output power is higher with lower drain efficiency. When Vbias is near the threshold volta ge, the PA is a class B amplifier, with higher drain ef ficiency but lower output power. At high frequencies, the common-source PA could be unstable because of the feedback through Cgd [Cao05b]. The small-signa l model of the output st age is shown in Figure 4-28. Cgd forms a voltage-current (shunt-shunt) feedback between the input and output nodes. The loop gain of this circuit is For oscillation to start, the phase cha nge of loop gain must be 360 degrees, with the magnitude of larger than 1. To meet the phase ch ange requirement, the first part of Eq. 4.1 must give a phas e change of 180 degrees, i.e, the resonant frequency of the tank at drain node is near th e oscillation frequency. A nother 180-degree phase change Zg ZdCgdFigure 4-28. Simplified small-signa l model of the common-source PA -----------+ – -----------+ -----------------------= 4.1

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85 comes from the second part of Eq. 4, which re quires high Q of netw ork at an oscillation frequency below or and are the equivalent inductance and series re sistance of network [Cao05b]. In this design, to ensure the stability of the system, the Q-factor at th e gate node is set low. As a matter of fact, is smaller than at the resonant frequency (20GHz) of the tank at drain node. 4.5.4 Measured Results The same measurement setup shown in Fi gure 4-13 is used to characterize the 20-GHz clock transmitter. Figure 4-29 shows th e output waveform wh en the clock transmitter is measured on chip. It shows that al most a perfect periodic no-signal-transmission duration of 1-ns is generate d. The settling time during the no-signal-transmission to signal-transmission states is ~ 50ps or 1 period. The total curr ent consumption of the clock transmitter is ~50mA fr om a 1.5V power supply. The transmitter chip is mounted on the sa me transmitter board as before (Figure 4-17). The transmitter board is measured us ing the measurement se tup shown in Figure Z g 1 L gequ C gd L gequ R gequ L gequ R gequ Z g L gequ R g 0.00.51.01.52.0 t (ns) -0.3 -0.2 -0.1 0.0 0.1 0.2Vout (Volt) Figure 4-29. Output clock waveform of the 20-GHz clock transmitter (on-chip)

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86 4-17. Figure 4-30 shows the waveform of the transmitter output signal with the VCO as the clock signal source. One exte rnal PA is used here to increase the power level. Once again, the no-signal-transmissi on period is successfully gene rated. Figure 4-31 shows the RMS jitter of the tran smitter output signal. The 1.70ps RMS jitter c ontains the triggering signal jitter and the 1.2-ps inst rument-characteristi c RMS jitter. When the triggering signal jitter and instrument-characteristic jitter are de-embedded, the tr ansmitted clock signal RMS jitter is between 0.1ps (best case) and 0.87ps (worst case), which is much better than the first version clock transmitter. Figure 4-30. Output clock waveform of the 20-GHz clock transmitter (on-board) 0.01.02.03.04.05.0 t (ns) -40 -20 0.0 20 40 60Vout (mV)

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87 The output power of the clock transmitter is also measured with an external synthesizer as the clock signal source. Figure 4-32 shows the output pow er versus clock frequency when the PA works at the best op erating point (class A). At 17GHz, the PA generates 5.1dBm differential output power, while consum ing 30mA from a 1.5V power Figure 4-31. RMS jitter of transmitte d clock signal and triggering signal 16.018.020.022.0 Frequency (GHz) -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 10.0Out power (dBm) Figure 4-32. Output power vs. clock frequency

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88 supply. The drain efficiency is ~7.2%. The low efficiency is due to a few reasons. To pump more output power from the clock transmitter, higher DC bias voltage and larger bias current are used for the PA while the efficiency is sacrificed. The vol tage swing at drain node is not full swing from ground to and a fraction of DC bias current of the PA is wasted. Furthermore, the unacc ounted parasitic capacitance of the three switches at output nodes which are used to generate the no-si gnal-transmission peri od, could degrade the output power (Figure 4-27). The PA operating frequency is shifted down by 3GHz due to the unaccounted parasitic capac itances. However, at 20GHz the output power is above 0dBm, which is still much better than the first clock transmitter. 4.6 Summary A receiver initialization and st art-up scheme for an inter-ch ip wireless clock distribution system are introduced. A no-signal-transmission period in the transmitted global clock signal for the receive rs is utilized to generate a pulse to initialize and start up the frequency dividers. To support this, a clock tr ansmitter, including a VCO, 512:1 frequency divider, power amplifier and no-signal-trans mission period generation circuitry, is implemented in a 0.13 m logic CMOS process. The power level of transmit ted clock signal should be higher than 0dBm for the clock recei vers to lock. The jitter should be low. The VCO utilizes a large common-source PM OS tail transistor, symmetrical negative resistance structure and high-Q LC tanks to reduce the phase noise. The measured phase noise from a 20GHz carrier is -106dB c/Hz at 1MHz offs et and -116dBc/Hz at 3MHz offset, which are excellent. The tuning ra nge of the VCO is 3GHz, which is close to the design value. A periodic nosignal-transmission with 1ns duration is generated on the output signal.

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89 At 17GHz, the output power is 5.1dBm, wi th a drain efficiency of ~7.2%. The operating frequency of PA is dropped by 3GHz due to the unaccounted parasitic capacitance. However, at 20GHz, the output power is still higher than 0dBm. The RMS jitter of the transmitted clock signal is below 0.87ps.

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90 CHAPTER 5 DEMONSTRATION OF INTER-CHIP CLOCK DISTRIBUTION 5.1 Overview Based on the theoretical and experimental results presen ted in the previous chapters, a wireless clock distribut ion system using an external antenna is ready to be demonstrated. In a clock distribution syst em, clock jitter, skew, and synchronization area are the key parameters. As discussed in Chapter 3, in an inter-chip wireless clock distribution system, clock skew should be small over a large ar ea, which needs to be verified. Clock jitter in a wireless clock distribu tion system does not accumulate along the signal paths, but caused only by the transmitted clock signal noise and receiver noise. Therefore, jitter could be smaller, which also needs to be investigated by measurements. The goal of this work is to construct a compact inter-chip wireless clock distribution system using a planar-array antenna (Figure 5-1), which essentially has the same form factor as that of a system using a conventional clock distri bution system. The planar-array antenna has an operating frequency of 24 GHz with a narrow bandwidth of 0.25GHz. However, because the operating frequency of bo th the clock transmit ter and clock receiver are shifted down from 24GHz, a horn antenna with a larger bandwidth is used for the system demonstration. Using the cl ock transmitter, the receiver and the antenna test chamber with a horn antenna, the whole system is demonstrated.

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91 This chapter contains five sections including the overview section. Section 5.2 introduces the measurement set up for an inter-chip wirele ss clock distribution system. Section 5.3 discusses the problem s associated with the meas urements and presents the experimental results. A whole inter-chip wire less clock distribution system is successfully demonstrated, with a heatsink incorporated into the system. Clock jitter, skew and synchronization area of this system are evaluate d and compared with so me other clock distribution systems. Finally, conclusi ons are presented in Section 5.4. 5.2 Measurement Setup The measurement setup for an inter-chip wireless clock dist ribution system is shown in Figure 5-2. The setup includes an Agilent 86100B oscilloscope, clock transmitter, clock receiver, balun, semi -rigid cables, GSSG probes, and the antenna test chamber containing an external antenna and a heat sink. Figure 5-3 shows a photograph of the measurement setup. Both transm itter and receiver are mounted on PC boards, which are designed and fabricated using Protel DXP. Fi gure 5-4 shows the transmitter and receiver boards. The receiver board size is 38 x 35mm2. A global clock signal is generated by the Antenna IC with Receiving Antennas Heatsink Low-profile Antenna Antenna Side View Front ViewFigure 5-1. Inter-chip clock distri bution using a planar array antenna Fan

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92 transmitter chip and delivere d to the external antenna us ing an SMA cable. The external antenna is placed right beneat h the heatsink (Figure 5-2). The receiver board is placed on top of the heatsink with the receiver chip at the center of a rectangular aperture opened in r Transmitter board Balun Trigger Oscilloscope tri C1 C2 GSSG Probe PA Receiver Detector Envelope LNA 1/8 Divider Buffer 1-18GHz Balun Enable A measurement setup of the wirele ss clock distribution system with an external antenna. Figure 5-2. PA receiver transmitter offchip antenna insidePhoto of the measurement setup for the inter-chip clock distribution Figure 5-3.

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93 the heatsink. To increase the received power, the 2-mm on-chip zig zag antenna in the receiver is aligned parallel to the shorter edge of the apertures, as discussed in Chapter 3. The receiver picks up the clock signal transm itted by the external antenna, amplifies it, and divides it down by 8 to generate the local clock signal. Only DC power supplies are needed for the system. The clock receiver is fabr icated using the UMC 0.13m logic CMOS process [Yan04, Guo05]. Figure 5-5 shows the die photogr aph of the clock receiver, which contains a 2-mm zigzag antenna, a broadband LNA, an envelop detector and an 8:1 frequency divider [Yan04]. The chip area of the clock receiver wit hout zigzag antenna is 1.5 x 0.8mm2. It consumes ~ 40mA from a 1.4V power supply. Th e LNA has a maximum gain of 14dB at 19GHz, with a 4GHz 3-dB bandwidth [G uo05]. The amplitude-modulated transmitted clock signal (clock signal with periodic no-signa l-transmission) is amplified by the broadband LNA while keep ing the waveform for no-si gnal-transmission periods. The amplified clock signal is s imultaneously fed into an 8:1 clock divider and an envelop detector. The detector recognizes the no-signal-transmi ssion period and generates one INI pulse (two edges), as shown in Figure 4-1, which is used to initialize and start up the freFigure 5-4. Photograph of tran smitter and receiver boards. 38mm 35mm30mm 30mm

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94 quency divider. A balun is used to change the differential receiver output signal to a single-side signal. Because the local clock signa l is a square wave wi th a frequency of around 2.2GHz, a Krytar 180o hybrid coupler with 1-18GHz opera ting range is used as the output balun to avoid distortion. Th e output waveforms of the receiver are captured using the oscilloscope. The same low-fre quency control signal from th e transmitter board used to trigger the oscilloscope during th e transmitter measurements (Fi gure 5-2) is used to trigger the oscilloscope. With this tri ggering signal as reference, th e clock skew across the circular opening of the chamber cover can be char acterized. For test purpose, another low-frequency signal with 50% duty cycle generated by th e clock transmitter is used to enable the clock receiver, as shown in Figure 5-2. The clock transmitter and receiver operating fre quencies are shifted down from Figure 5-5. Die photograph of the clock receiver Wideband LNA Detector and 8:1 Frequency Divider 1.5mm 0.8mm 2mm

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95 24GHz. In particular, the best working frequency range for the clock receiver is below 19GHz. Because of this, the syst em is characterized using the first version clock transmitter (17GHz), while an external PA is used to increase the transm itted clock power level. Furthermore, as mentioned earli er, because the planar array antenna has greatly attenuated antenna gain (~ -1 dBi) at 17 GHz, a horn antenna with a larger bandwidth (8.5 GHz) is used instead of a planar array antenna for the system demonstration. The 18.5-dBi gain of the horn antenna at 17 GHz is 2.5 dB lower than that of the pl anar array antenna at 24 GHz (21dBi). This means the planar array antenna can be used in the system by properly frequency tuning the receiver and tran smitter, or the planar array antenna. The aperture of the horn antenna is 6.4 x 4.7 cm2. The horn antenna is placed in stead of the planar array antenna shown in Figure 5-1. 5.3 Inter-chip Clock Distri bution System Demonstration 5.3.1 System Demonstration without Heatsink The system is first measured at ~17GHz with the receiver boa rd placed directly above the horn antenna. The h eatsink is removed fr om the system. The distance between horn antenna and receiver board is ~30m m, which is the height of heatsink. The clock receiver is char acterized before the whole system measurement. It is shown that for the clock receiver to be locked, the power picked up by the receiving antenna must be higher than -26dBm, i.e., the receiver sens itivity is -26dBm. The receiver sensitivity is worse than that of the receiver used in Chapter 3, because this receiver has the function of initialization and start-up. In this receiver, an LNA with much broader band is needed to avoid signal distortion, wh ich reduces the LNA gain. Furthermore, the

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96 8:1 frequency divider operates in latched-mode instead of injection-locking mode, which degrades the divider sensitivity. In the setup, the antenna pair power gain between a horn ante nna and 2-mm zigzag antenna in the receiver is ~ -31dB at ~17 GHz. Therefore, the minimum power delivered to the horn antenna must be higher than 5dBm to lock the clock receiver. The clock power from the 17-GHz clock transmitter board is ~ -15dBm at 17GHz. Because of this, external amplifiers are used to drive the horn ante nna. The clock power delivered to the horn antenna is ~ 8dBm. Figure 5-6 shows the output waveform of the clock re ceiver on the oscilloscope. The waveform is clean and sharp indicating th e receiver has locked onto the transmitted clock signal. To double-check th at the clock receiver is lock ed onto the transmitted clock signal, the external amplifier is turned off, which severely reduces the power delivered to the horn antenna. Under this condition, the output waveforms from the clock receiver become disordered and all the clock edges di sappear. When the external amplifiers are turned back on, the clock recei ver again locked onto the tr ansmitted clock signal. When 0.01.02.03.04.05.0 t (ns) -0.2 0.0 0.2 0.4 0.6 0.8Vout (Volt) Initialization Point Start-up Point Figure 5-6. A measured waveform of the locked local clock si gnal (without heatsink)

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97 the first stage of LNA in the clock receiver is turned off, the receiver output waveform also become disordered. These results indicat e that the clock receiver is undoubtedly locking onto the transmitted clock signal. In Figure 5-6, the receiver is locked ont o the transmitted cl ock signal at 17.4GHz. The local clock frequency is 2.17GHz. The initialization period is bounded by two dashed lines. The locking frequency range is ~100MHz. With the DC bias of the clock receiver adjusted, the locking frequency range can be increased to over 600MHz, which is limited by the tuning range of first cl ock transmitter. Figure 5-7 shows the local clock signal waveform over a shorter time period. It illust rates the clock receiver output is nearly a square wave. The voltage swing is from -0.1V to 0.6V. As shown in Figure 5-6, The system is initialized approximately ev ery 30 ns. The jitter of the wireless clock distribution system using an ex ternal antenna has been meas ured (Figure 5-8), when the clock receiver is kept locking for five minut es, and the jitters shown on the oscilloscope do not change. The measured RMS jitter of the locked loca l clock signal and the triggering 0.00.51.01.52.0 t (ns) -0.2 0.0 0.2 0.4 0.6 0.8Vout (Volt) Figure 5-7. Local clock signal wave form over a shorter time period

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98 signal are 2.36ps and 2.35ps respectively. Both reflect the total jitter including the 1.2ps typical characteristic RMS jitt er of the oscilloscope. Due to the lack of necessary equipment, it is difficult to disti nguish the different jitters and to calculate the exact RMS jitter of the triggering signal and the local clock signa l. However, the jitters can be roughly estimated. The triggering signal jitter shown on th e oscilloscope counts the real low-frequency control signal jitter twice because the time delayed signal of this is used to trigger the signal. Therefore, assuming that the dela yed triggering signal is independent to the triggering signal, the triggeri ng signal jitter can be de-e mbedded using the square-law equation, Using the same method, the de-embedded RM S jitter of the local clock signal is Figure 5-8. Measured RMS jitter of the local clock signal and triggering signal – ----------------------------------------------------------– ------------------------------=== 5.1 – – – – === 5.2

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99 Therefore, the peak-to-peak jitter of the local clock signal is 8.64ps, which is ~1.88% of a period at 2.17GHz. This value is much lower than th e 10% limit typically required for a clock distribution system. The real local clock signal jitter shoul d be smaller than this value, because in the worst case th e jitters are added line arly instead of as a square root of sums of jitt ers. Furthermore, the maximum instrument RMS jitter of the oscilloscope is 1.5ps, instead of 1.2ps. For this case, the RMS ji tter of the triggering signal and local clock signal can be de-embedded as follows: In this case, the peak-to-peak jitter is 2.61ps, which is ~0.57% of a clock period at 2.17GHz. In conclusion, the peak -to-peak jitter of the locked local clock signal should be between 0.57% and 1.88% of a clock period. The peak-to-peak jitter includes that from the VCO. In this demonstration, the VCO in the transmitter is free-running. Once the VCO is locked, the peak-to-peak jitt er should be even smaller. One issue that deserves more attention is the effects of the receiver initialization and start-up scheme to the measurements of local clock signal jit ter. The 8:1 frequency divider in the clock rece iver is turned off for 1ns and st arted again in every 30ns. Once the divider is started up, it operates freely. The jitter is estimated by l ooking the distribution of a large number of a clock edge af ter the initialization. Despite th e fact that it is initialized every 30ns, it stil l reflects the variation of this clock edge due to the transmitted clock sig– ----------------------------------------------------------– ------------------------=== 5.3 – – – – ===5.4

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100 nal noise and the receiver noise Actually, the jitter also incl udes the variation due to the initialization step. The r easonable jitter also indicates that the initialization is working well and repeatable. Besides the jitter, the clock skew inside the synchronization area of the external antenna should be evaluated. To measure the system skew ca used by the displacement, a clock receiver is placed at cent er of the circular opening in the chamber cover and locked onto the 17.4GHz transmitted clock signal (Figur e 5-2). With all the DC bias voltages on, and the receiver kept locked, the receiver is moved inside the 4-inch diameter opening. During this, the triggering signal shown on the os cilloscope, which is from the clock transmitter, is not affected. With the triggering si gnal as the reference, the system skew due to displacement can be measure d. Figure 5-9 shows th e nine places in th e opening here the receiver is moved to. Due to the limitation of the probe st ation, the receiver could not be 0 2 1 3 4 5 6 7 8 18mm 10mm 10mm Figure 5-9. Places in the cover opening to which the receiver chip can be moved X Y Opening of Chamber Cover

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101 moved everywhere inside the opening. The displacement shown in Figure 5-9 is the maximum distance that the probe could be moved to. Figure 5-10 shows the local clock signal waveforms when the clock receiv er is at each of the nine places. The variations of local 0.00.20.40.60.81.0 t (ns) -0.2 0.0 0.2 0.4 0.6 0.8Vout (Volt) P0 P1 P2 P3 P4 P5 P6 P7 P8Figure 5-10. Local clock signal waveforms with receiver at 9 different places 0.600.620.640.66 t (ns) 0.0 0.2 0.4Vout (Volt) P0 P1 P2 P3 P4 P5 P6 P7 P8 0.6Figure 5-11. Skew among the 9 places

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102 clock signal amplitude is due to the variat ions of probe landing. The skew over the nine places with a displacement of 10mm in X direct ion and 28mm in Y direction is within 10ps, as shown in Figure 5-11. This is ~2.2% of a clock period at 2.17GHz. Although the measured area is limited by the movement in the probe station, the small measured clock skew indicates that the sim ilar clock skew projected over 4-cm diameter circular area based on antenna measurements in Chapter 3 is reasonable. When the clock jitter and skew are added together, the total uncertainty of ~ 4% of a clock period is still much smaller than the 10% limit. The clock skew measured he re is caused only by the receiver displacement. The process variation, which is another important factor causing skew, is not counted. Simulation using corner model parameters indicate s additional skew of 4ps (~0.8% of a period) on the local clock signal. Therefore, in th e worst case, the process variation should increase the clock skew to 3% of a period over a 4-cm diameter circular area, which is still small. 5.3.2 System Demonstration with Heatsink For a practical inter-chip wireless cloc k distribution system, a heatsink must be incorporated. To evaluate the system with a heatsink near 17GHz, a new heatsink with an array of 1.5mm x 9mm rectangular apertures is fabricated. The fins and rectangular apertures form wave guides with a minimum cutoff frequency of 16.6GHz (Eq. 3.4). As discussed in Chapter 3, the TE10 mode wave has no E-field co mponent in the direction of aperture width. Therefore, the receiving antennas should be aligned parallel to the shorter edges (height) of the apertures.

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103 With the heatsink incorporated into th e system, the antenna pair power gain between a horn antenna and 2mm zigzag antenna in the receiver, through a 1.5mm x 9mm aperture, is reduced to ~ 35dB at 17GHz. The gain degrad ation is caused by a dip near 17GHz, which may be caused by the multi-re flection on the bottom surfaces of heatsink and receiver board. At frequencies above 19GHz, the antenna pair gain is increased by the incorporation of a heatsink. As mentioned befo re, the receiver sensitivity is -26dBm. This suggests that the minimum pow er delivered into the horn antenna must be higher than 9dBm for the clock receive rs to lock. Because of this, the power gain of ex ternal amplifiers is increased by adding another stage so that the clock power delivered to the horn antenna is ~ 13 dBm. Using the same measurement setup as in Figure 5-2, th e system with a heatsink is measured. Figure 5-12 shows the receiver side of the measur ement setup, where the heatsink is placed underneath the receiver board, and above the horn antenna, which is inside the chamber. The receiver chip is positioned with the help of GSSG probe so that the receiving antenna is at the center and in paralle l to the shorter edge of the aperture (Figure 5-12). Figure 5-12. Measurement setup with a heatsink Receiver Detector Envelope LNA 1/8 Divider Buffer Aperture in Heatsink 9mm 1.5mmHeatsink

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104 The clock transmitter is t uned at 17GHz. Figure 5-13 show s the time delayed local clock signal from the clock receiver. The re ceiver is locked onto the global transmitted 0.01.02.03.04.05.0 t (ns) -0.2 0.0 0.2 0.4 0.6 0.8Vout (Volt) Initialization Point Start-up Point Figure 5-13. A measured waveform of the locked local clock signal (with a heatsink) Measured RMS jitter of the loca l clock signal and triggering signal (with a heatsink) Figure 5-14.

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105 clock signal, with a local cl ock signal frequency of 2.12GHz Again, the system initialization and start-up steps are demonstrated. The locking range is ~ 100M Hz, the same as the case without the heatsink. Figure 5-14 shows the total RM S jitter of the local clock signal and the triggering signal, which are 2.8ps and 2.6ps, respectivel y. Using the same method as before, the RMS jitter of the trigge ring signal and local clock signal can be estimated. When a root of the sum of squares is used, th e de-embedded RMS jitter of the triggering signal and local clock signal are When the simple addition is used, the de -embedded RMS jitter of the triggering signal and local clock signal are As a result, when a heatsink is in corporated, the maximum and minimum peak-to-peak local clock signa l jitters are 11.64ps and 4.56ps, re spectively. Therefore, the peak-to-peak jitter of the lo cal clock signal is between 1% and 2.47% of a clock period at – ----------------------------------------------------------– ------------------------------=== 5.5 – – – – === 5.6 – -----------------------------------------------------------– ------------------------=== 5.7 – – – – ===5.8

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106 2.12GHz, which is still much lower than the 10% limit. Compared to the case without a heatsink, the local clock signal jitter become s worse when a heatsink is incorporated. This is caused by the larger noise from the extern al PA. Like the case without a heatsink, once the free-running VCO in the clock transmitter is placed in a PLL, the local clock signal jitter should become even smaller. 5.3.3 Comparison among Cloc k Distribution Systems The proposed wireless clock di stribution system using an external antenna is successfully demonstrated in the presence of a heatsink. The local cl ock frequency is ~CL--Closed loop CLAC--Closed loop with active skew compensation Table 5-1Comparison of high-performance cloc k distribution networks recently reported.Microproces sor fc(GHz) L ( m) Synchronization Area (mm2) Technology Global Skew P-P Jitter Alpha 21364 [Xan01] 1.20.18397X-Tree, H-tree, Grid, Spine (CLAC) 10.8%N. A Pentium IV [Kur01] 2.0/4.00.18N. A.Binary Tree (CLAC) 3.2%7.0% Power PC [Hof00] 1.15N. A. N. A.H-Tree, Grid (CL) 1.72%4.9% Power 4 [Res02] 1.3N. A.N. A.H-Tree, Grid (CL) 3.25%3.9% RCD (Ryu02) 5board level N.AH-Tree with Junction Couplers 10%2.5% Itanium 2 (Tam04) 1.50.13374Diff. H-Tree, Zonal Clocks (CLAC) 3.6%N.A CSWO (Mah03) 100.1816Coupled Standing -wave Oscillators Grid 0.6%3% This Work2.170.131256/962Wireless<3%1%2.47%

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107 2.2GHz. The total timing uncertainty including sk ew, jitter, and variat ion of initialization are ~ 4% of a period. This resu lt indicates that the local cl ock frequency can be increased at least two times higher and synchronize over a ~4-cm diameter circular area, while keeping the timing uncertainty below the 10% li mit. Furthermore, once the free-running VCO in the clock transmitter is locked using a P LL, and a low noise cloc k receiver is designed and utilized, the total clock j itter and skew can be even sm aller, and the local clock frequency can be increased more. The performance of the wireless clock distribution system using an external antenna is compared with a few clock distribution systems recently reported. The comparison is shown in Table 5-1. The comparison shows that the wire less approach can be better in terms of the synchronizati on area, maximum clock freque ncy and the jitter and skew performance. 5.4 Summary Using the clock transmitter and receiver chips designed and fabricated in a UMC 0.13 m logic CMOS process, wireless clock distri bution using an external antenna is successfully demonstrated at ~17GHz, while in corporating a heatsink. Both the clock transmitter and receiver ar e mounted on PC boards. A broadba nd horn antenna is used instead of a 24GHz narrowband planar-array antenna in the system as the transmitting antenna, because the operating frequencies of both the clock transmitter and receiver are shifted down from 24GHz. For both ca ses with a heatsink and wi thout a heatsink, the clock receiver is successfully locked onto the ~17 GHz transmitted global clock signal from the external antenna. The system in itialization scheme is also su ccessfully demonstrated. The initialization and start-up steps are working we ll and repeatable. For both cases, the local

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108 clock signal is ~2.2GHz, with a peak-to-peak jitter of less th an 3% of a period. The measured clock skew over a 4-cm diameter circul ar area is less than 2.2% of a period. With process variation, the clock skew is still less than 3% of a period. The total uncertainty, including clock jitter and skew, is less than 5% of a period over a 4-cm diam eter circular area, which is significantly smaller than the 10% limit in a clock distribution system. The jitter and skew performance i ndicates that the local clock frequency can be increased to higher than 2.17GHz with acceptable jitter a nd skew using this technology. The results suggest that a wireless clock di stribution system using an exte rnal antenna is feasible, and also show the potential of a highe r maximum clock signal frequency. The antenna gain of the planar array ante nna at 24GHz is 2.5dB higher than that of the horn antenna at 17GHz. Th erefore, by properly freque ncy tuning the clock receiver and transmitter or the planar array antenna, it should be possible to construct a compact wireless clock di stribution system.

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109 CHAPTER 6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK 6.1 Summary In the first part of this di ssertation, the feasibility of an inter-chip wireless clock distribution system is evaluated. The power transmission gain between an external antenna and integrated receivi ng antennas is crucial for this system. Using the fundamental Electromagnetic formulas, th e performance of integrated antennas is analyzed. Next, a measurement setup is constructed to measur e the power transmission gain and phase of S21 between an external antenna and on-chip an tennas. Using this setup, external antennas, on-chip antennas, and the impact of a he atsink are characterized. It is shown that an external antenna can provide phase uniformity suitable for synchronizing at 3GHz over a circular area with a diameter of ~35mm which is 4-5 times larger than that previously thought possible. A heatsink with fins and an array of same-size r ectangular apertures can be incorporated into the system, without de grading the power gain and phase distribution from an external antenna. Based on the antenna measur ement data, the second part focuses on the design and demonstration of an inter-chip wireless clock distribution sy stem. A 17-GHz and a 20-GHz clock transmitter re quired for the system are demonstrated in a 0.13 m logic CMOS process. Periodic no-signal-transmission used for the receiver initialization are successfully generated with a small settling time (~50ps or 1 period). The measured RMS jitter of the transmitted clock signal is below 0.87ps.

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110 Using the 17-GHz clock tr ansmitter, and a clock re ceiver designed by others (Yan04, Guo05), a wireless clock distribution system using an external antenna is constructed. A horn antenna is used as the ex ternal transmitting antenna. The transmitted clock signal is picked up by the receiver and utilized to init ialize/synchronize the receiver and to generate a local clock signal in the presence of a heatsink. Th e receiver is successfully locked onto a 17GHz tran smitted clock signal with a local cloc k signal frequency of ~2.2GHz. The local clock signa l jitter is between 1% a nd 2.47% of a period. Clock skew over a circular area with diam eter of ~4cm is le ss than 2.2% of a peri od. With the process variation included, the maximum clock skew is expected to be still less than 3% of a period. The antenna gain comparison suggests that by properly frequency tuning the clock transmitter and receiver or planar array antenna, it shoul d be possible to implement a compact wireless clock distributi on system. This work has provi ded experimental results suggesting that inter-chip wireless clock dist ribution has the potenti al of enabling higher clock frequency and a larger synchronized area. 6.2 Future Work For the first time, this work has shown that a wireless clock distribution system using an external antenna can be a realistic option. To take this further, a few future works are suggested. 6.2.1 Demonstration of A Comp act Clock Distribution System The bandwidth of a planar array antenna is normally narrow. At frequencies outside of the planar array bandwidth, the ante nna gain is greatly attenuated and the power efficiency of the system is very low. As di scussed in Chapter 5, to utilize a planar array antenna in the system, the op erating frequency of the clock transmitter and clock receiver

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111 has to be tuned to match the planar array antenna operating frequency range (24-24.25GHz). Otherwise, a cust om planar array antenna s hould be designed to match the operating frequency of the clock transmitter and clock receiver. A compact wireless clock distribution system using a planar-array antenna has the same form factor as a conventional clock distribution syst em while having all the potenti al advantages of a wireless clock distribution system. 6.2.2 Removal of the External PA In this work, external PAs are used to increase the power level of the transmitted clock signal because the on-chip PA is mis-tuned. External PAs increases the system complexity and increases the cost. They should be replaced by an on-chip PA. In this system, the transmitted global clock signal is an am plitude-modulated sine wave with periodic no-signal-transmission, which is generated by switches at output nodes. A PA with high output power and power efficiency should be designed and fabricated. 6.2.3 Higher Clock Frequency a nd Smaller On-chip Antenna In the wireless clock distribution system described in Chapte r 5, the local clock signal frequency is ~ 2.2GHz, limited by the operatin g frequency of cloc k transmitter and receiver. There is much room for increasi ng the clock frequency using this technology. In an inter-chip wireless clock distribut ion system, microwaves propagate at the speed of light to di stribute the clock signals across a chip. The RC-delay and dispersion associated with conventional metal-line inte rconnections are almost eliminated. Using this technology, the maximum local clock signal fr equency is set by th e maximum operating frequency of clock transmitter and clock receiv er, and the clock skew and jitter at really high frequencies. According to recent publications, CMOS ICs using a UMC 0.13 m pro-

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112 cess can reach an oper ating frequency of ~ 100GHz [Ca o05a, Hua05]. Therefore, the maximum clock frequency will be limited only by the clock skew and jitter. As discussed earlier, the skew and jitter perf ormances have the potential of being excellent which could give more margin for the clock frequency in crease. To further reduc e the clock skew and jitter, the free-running VCO in the clock transmit ter should be replaced by a PLL, and a clock receiver with lower noise should be developed. With the increase of clock frequency, the on-chip receiving antenna size can be reduced, which will reduce the on-chip receiving antenna area, a major problem in the system. As a result of the sma ller receiving antenna size, the width and height of rectangular apertures in heatsinks can be reduced, whic h should improve the heatsink performance. 6.2.4 Evaluation of Wireless Clock Distribution in A Large IC In this work, only one clock receiver chip is used for the system demonstration. In a practical wireless cl ock distribution system using an ex ternal antenna, there are a grid of clock receivers across a large digital chip. The on-chip sw itching noise will affect the jitter performance. The noise coupling from nearby di gital circuits to the clock receivers should be evaluated. In terms of sk ew, the clock skew only caused by displacement of a clock receiver is measured in Chapter 5. Clock skew in a practical wirele ss clock distribution system should be investigated by measurements. Therefore, a la rge IC with a grid of clock receivers and switching noise source should be designed and fabricated. The receivers should be synchronized onto a tr ansmitted global clock signal from an external antenna. The clock jitter and skew of th e wireless clock distribution sy stem in a real environment should be evaluated.

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113 Finally, a compact inter-chip wireless cl ock distribution system with high integration level and high clock frequency will demonstrate the ul timate power of this technology.

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114 APPENDIX WAVE PROPAGATION BETWEEN ON-CHIP ANTENNA PAIR A.1 Multi-path Model for On-chip Antenna Pair [Li02] In an intra-chip wireless clock distri bution system, the pow er transmission gain between the on-chip antenna pa ir is the key parameter. Fo rmer works have shown that inserting a 0.76-mm Aluminum Nitride (AlN) layer between a sili con wafer containing integrated antennas and a meta l chuck emulating the role of a heat sink improves the antenna power transmission gain by ~ 8 dB at 15 GHz (Figur e A-1) [Guo02]. In this case the AlN layer is acting as a dielectric propagation medium which provides a low loss path for wave propagation. With the high thermal conductivity, the use of AlN should not significantly degrade the heat removal problem. When the AlN layer thickness increases, theGa (dB) 10.012.014.016.018.0 -65.0 -55.0 -45.0 with metal beneath 0.76mm AlN 1.0mm glass 1.0cm wood seperation=5mmFrequency(GHz) 5mm Power gain vs. frequency fo r different propagation medium Figure A-1.

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115 gain no longer increases monot onically with frequency in the measurement frequency range. Instead, dips are seen on the power gain plots. Figure A-2 show s that dips appear on the gain plots when the thic kness of AlN is above 3.8 mm. The dip frequency decreases with the AlN layer thickness. In an intra-ch ip clock distribution sy stem, the dips which greatly degrade th e power transmission gain must be avoided. Using the multi-wave-propagation-path model [Kim00], the cause for di ps and the thickness dependence of dip frequency can be explained. Figure A-3 shows the measurement setup where AlN la yer is inserted between silicon wafer and metal chuck. There are a 1.5m SiO2 layer, 600 m silicon layer, AlN layer and metal chuck layer beneath the inte grated antennas. The wave propagation model between an antenna pair is shown in Figure A-4 [Kim00, G uo02]. It contains four main wave paths, i.e. Path A (direct path), Path B (reflected wave at the Si/AlN interface), Path dip dipwith metal beneath 0.76mm AlN 3.80mm AlN 5.32mm AlN Ga (dB) Frequency (GHz)-85.0 -75.0 -65.0 -55.0 -45.0 10.012.014.0 16.0 18.0Power gain vs. Frequency for AlN with different thickness Figure A-2.

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116 C (lateral wave) and Path D (reflected wave at the AlN/ Metal interface). Among the paths, signal transmission through path B is negligible for substr ate resistivitie s less than ~ 20 cm because of the strong atte nuation in Si over the measur ement frequency range. Path A is in free space. In the final packaged solu tion, Path A could be bl ocked by the interfering metal structures. Therefore, Paths C and D are expected to be the dominant paths for power transmission between Tx and Rx antennas. Glass/Air Si Oxide TxRx Silicon Oxide Metal/HeatsinkAirr=1r=11.7r=3.9 AlNr=8.8 A D Si Oxide CMetalTx Rx AlN B RARc ld1ld2ld3Figure A-3. Measurement set up of on-chip antenna pair Figure A-4. Wave paths of propagation

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117 A.2 Electric Field Due to Path A, C, D Lateral wave propagates in the vicinity of an interf ace between two different media, and is associated with the total -reflection phenomena in electromagnetics. When an EM wave is transmitted from a denser medium onto a rarer me dium, total reflection happens when the incident angle is equal to or larger than the critical angle of reflection which is defined in Eq. A.1. In this equation, and are the refract ive indices of the denser medium and rarer medium, respectively. Th ere will be a lateral wave pr opagating below the interface when the incident wave hits the boundary at the critical angle (Figure A-5) [Tam82]. Lateral wave propagates at the speed of which is the speed of light in the rarer medium. For an on-chip antennas pair (Fi gure A-6), when there is no SiO2 top layer, signal transmission through Path C is possible for any propagating medium with relative permittivity value smaller than 11.7. The incident angle should be equal to the critical angle of reflection. When there is a SiO2 top layer, for signal tran smission through Path C to be ----= (A.1) n1 2=90o lateral waven2 c c Figure A-5. Lateral wave field

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118 possible, the permittivity of the propagating medium must be less than that of SiO2( r=3.9). These conditions are defined by Eqs. A .2-A.6. Hence, the la teral wave path does not exist when an AlN layer with the relative permit tivity of 8.8 is us ed as the propagating medium. When a sinusoidally varying cu rrent I(t) defined in Eq. 2.1 is delivered to the center of transmitting antenna, the electric field at receiving ante nna due to Path A and Path C can be estimated [Tam82]. To make it simple a line-source assumption is used here. A circular cylindrical wave is radi ated from the line source whic h generates electric field with two dimensional nature. The tr ansition from the two-dimensi onal to the three-dimensional Propagation Si (n2) Oxide (n1) Metal AntennaAntenna t12t23 t32t21 12 d2C 3=90o lateral wave Medium (n3) Possible lateral wave path be tween an on-chip antenna pair Figure A-6. n 1 1 3.91.97 === === = === n 3 n 1 < 3 1 <(A.2) (A.3) (A.4) (A.5) (A.6)

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119 can easily be carried out. In th is work only the components of electric field parallel to the dielectric boundary, i.e. perpendicular to the incident plane, are calculated. The electric field due to Path A can be expressed as [Tam82] In this equation, is a cons tant and is the amplitude of the current fed into the Tx antenna, which are independent of the paths. is the lengt h of dipole antenna. is the attenuation factor due to the si licon layer, which depends on the distance, frequency, and permittivity of a Si wafer, just like the surface wave radiated by a dipole above a ground plane with finite conductivity (the Earth) [Jor68]. The atte nuation factor G is calculated from Eqs. A.8-A.12, where and are the conduc tivity and relative permittivity of silicon, respectively. Maple is used to simulate the attenuation factor for the wave propaga-------------------------------------------------+ == (A.7) – – = – -----------------------------------– = – ------------------------= --------------= = (A.8) (A.9) (A.10) (A.11) (A.12)

PAGE 134

120 tion over a distance of 5mm. When the fr equency increases from 1 to 50 GHz, the attenuation changes from 0.75 to 0.35, as shown in Figure A-7. The electric field due to Path D is expr essed in Eq. A.13, where the wave vector is expressed in Eqs. A.14-A.16. is the length for wave propagation in each layer (Figure A-4). 0.010.020.030.040.050.0 Frequency (GHz) 0.30 0.40 0.50 0.60 0.70 0.80Magnitude of G 0.010.020.030.040.050.0 Frequency (GHz) 50.0 60.0 70.0 80.0 90.0Phase of G (degree) Calculated attenuation factor G when the distance is 5mm Figure A-7. (A.13) +++ – = ++ -– ----++ -– + = ---------+ + -= ---------+ – -= + = (A.14) (A.15) (A.16)

PAGE 135

121 Path D suffers two independe nt attenuation mechanisms. One is from the transmission coefficients t12, t21, t23, t32 between two different layers which are calculated from Eqs. A.17-A.21 (Figure A-8) [Kim00]. The ot her attenuation mechanism is due to the finite conductivity of silicon. + ------------------------------------------------= ˆ ˆ ˆ ˆ + ------------------------------------------------=ˆ ˆ + = -– – + + -= -– – – + + -= (A.18) (A.19) (A.20) (A.21) (A.17) Si SiO22 11r, Figure A-8. Wave tran smission between SiO2 and Si

PAGE 136

122 When the relative permittivity of the propagating medium is lower than that of SiO2, there will be Path C. The expression for the electric field due to Path C is where and are defined in Eqs. A.15-A.16. – -------------------------++ --------------------------------------------------------------------------------------– ==(A.22) ) = 6.010.014.018.022.026.0 Frequency (GHz) 20.0 60.0 100.0 140.0 180.0 220.0Normalized E-field at receiving antenna 2.28 mm AlN 3.8 mm AlN 5.32 mm AlN 10 12 14 16 18 20 22 24 26 -90 -80 -70 -60 -50 -40 -30 Frequency(GHz)Gain (dB) 2.28 mm AlN 3.8 mm AlN 5.32 mm AlN Dips DipsFigure A-10. Measured power gain vs. frequency Calculated normalized E -field at the receivin g antenna vs. frequency Figure A-9.

PAGE 137

123 With an AlN layer as the propagating medium, the tota l E-field at the receiving antenna is given by Eq. A.23 Figure A-9 shows the curves of calcula ted normalized E-field when the antenna separation is 5mm. Figure A-10 shows the meas ured power gain. With an AlN layer thickness of 2.28 mm, there is no dip on both plots. When the thickness of AlN increases to 3.8 mm and 5.32 mm, two dips occur in the freq uency range from 10 to 26 GHz and the dip frequency decreases wi th AlN thickness on both plots. It can be predicted from Figure A9 that a third dip will occur at higher fr equency for the 3.8-mm and 5.32-mm AlN cases. The measured and calculated first dip frequencies are compared in Figure A-11, where the AlN layer thickness is increased fr om 3mm to 7mm. The calculation results match the measured data. The comparison indi cates that the wave propagation model proposed in Figure A-4 is reasonable. These dips are caused by the destructive interference among different signal propagation paths. + == (A.23) 3.04.05.06.07.0AlN Thickness (mm) 6.0 8.0 10.0 12.0 14.0 16.0Dip Frequency (GHz) Measured Plot Calculated PlotFigure A-11. Dip frequency vs. AlN thickness

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124 LIST OF REFERENCES [Bal82]C. A. Balanis, Antenna Theory, New York: Harper & Row, 1982. [Boh95]M. T. Bohr, “Interconnect Scaling-The Real Limiter To High Performance ULSI,” IEDM Technical Digest pp. 241-244, Dec. 1995, Washington, DC [Bom02]W. Bomstad, and K. K. O, “Pha se and Amplitude Di stribution Measurement Using a Compact Antenna Test Ra nge Applicable To Wireless Clock Distribution,” 2002 IEEE AP-S Intl. Symp., Vol. 3, pp. 726-729, San Antonio, TX. [Cao05a]Changhua Cao and K. K. O, “A 90-GHz Voltage-Controlled Oscillator with a 2.2-GHz Tuning Range in a 130-nm CMOS Technology,” Accepted by Symp. VLSI Circuits Dig. Tech. Papers, 2005, Kyoto, Japan [Cao05b]Changhua Cao, Haife ng Hu, Yu Su and K. K. O, “An 18GHz, 10.9-dBm Fully-Integrated Power Amplifier with 23.5% PAE in 130-nm CMOS,” Accepted by 2005 Proceeding of the European Sol id-State Circuits Conference, Paris, France [Deu98]A. Deutsch, H. Harrer, C. W. Surovic, G. He llner, D. C. Edelstein, R. D. Goldblatt, G. A. Biery, N. A. Greco, D. M. Foster, E. Crabbe, L. T. Su, P. W. Coteus, “Functional High-speed Characterization and Modeling of a Six-layer Copper Wiring Structure a nd Performance Comparison with Al On-chip Interconnections,” IEDM Technical Digest pp. 295-298, Dec. 1998, San Francisco, Ca [Flo99]B. A. Floyd and K. K. O, “The Pr ojected Power Consumption of a Wireless Clock Distribution System and Comp arison to Conventional Distribution Systems,” Proc. International Intercon nect Technology Conference pp. 248-250, May 1999, San Francisco, Ca [Flo00]B. A. Floyd, K. Kim, and K. K. O, “Wireless Interconnection in a CMOS IC with Integrated Antennas,” ISSCC Digest Technical Papers pp. 328329 Feb. 2000, San Francisco, Ca [Flo01a]B. A. Floyd, “A CMOS Wireless Interconnect System for Multigigahertz Clock Distribution,” Ph.D. Dissertation, University of Florida, Gainesville, FL, 2001.

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125 [Flo01b]B. A. Floyd, C.-M. Hung, and K. K. O, “A 15GHz Wireless Interconnect Implemented in a 0.18m CMOS Technology Using Integrated Transmitters, Receivers, and Antennas,” Symp. VLSI Circuits Dig. Tech. Papers, June 2001, Kyoto, Japan [Flo02]B. A. Floyd, C.-M. Hung, and K. K. O, “Intra-chip Wi reless Interconnect for Clock Distribution Im plemented with Integrated Antennas, Receivers, and Transmitters,” IEEE Journal of Solid-State Circuits Vol. 37, Issue: 5, May 2002 [Guo01]X. Guo, J. Caserta, R. Li, B. A. Fl oyd and K. K. O, “Pr opagation Layers for Intra-chip Wireless Interconnection Compatible with Packaging and Heat Removal,” Dig. of Tech Papers, Symp. VLSI Tech. pp. 36-37, Honolulu, HI, 2002. [Guo05]X. Guo and K. K. O, “A Power Ef ficient Differential 20-GHz Low Noise Amplifier with 5-GHz 3-dB Bandwidth,” Accepted by IEEE Microwave and Wireless Components Letters [Gut00]V. Gutnik and A. P. Chandrak asan, “Active GHz Clock Network Using Distributed PLLs,” IEEE J. Solid-State Circuits vol. 35, no. 11, pp. 15531560, Nov. 2000. [Hal97]L. Hall, M. Clements, W. Liu, a nd G. Bilbro, “Clock Distribution Using Cooperative Ring Oscillators,” Conference on Advanced Research in VLSI 1997, pp. 62-75, Ann Arbor, Mi [Hof00]R. Hofstee, N. Aoki, D. Boerst ler, P. Coulman, S. Dhong, B. Flachs, N. Kojima, O. Kwon, K. Lee, D. Meltzer K. Nowka, J. Park, J. Peter, S. Posluszny, M. Shapiro, J. Silberman, O. Takahashi and B. Weinberger, “A 1GHz Single-Issue 64b PowerPC Processor,” ISSCC 2000 Session 5, Paper MP 5.4, San Francisco, Ca [Hsi98]H.-Y. Hsieh, W. Liu, M. Clements, and P. Franzon, “Sel f-Calibrating Clock Distribution With Scheduled Skews,” IEEE International Symposium on Circuits and Systems, 1998 pp. 470-473, Monterey, Ca [Hun00]C.-M. Hung, “Investigation of a Mu lti-GHz Single-chip CMOS PLL Frequency Synthesizer for Wireless App lications,” Ph.D. Dissertation, University of Florida, Gainesville, FL, 2000. [Hua05]P. Huang, M. Tsai, H. Wang, C. Chen and C. Chang, “A 114GHz VCO in 0.13m CMOS Technology,” ISSCC 2005 Session 21, 21.8, San Francisco, Ca

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126 [Jor68]Edward C. Jordan and Keith G. Balm ain, Electromagnetic Waves and Radiating Systems, Englewood Cliffs, NJ: Prentice-Hall, Inc. 1968, p648 [Kav00]A. Kavech, “The History of Power Dissipation,” Electron. Cool. 2000, 6 (1) [Kim98]K. Kim and K. K. O, “Character istics of Integrated Dipole Antennas on Bulk, SOI, and SOS Substrates for Wireless Communication,” Proc. of the IITC pp. 21-23, San Francisco, CA, 1998. [Kim00a]K. Kim, “Design a nd Characterization of RF Components for Inter and Intra-chip Wireless Communications,” Ph.D. Dissertation, University of Florida, Gainesville, FL, 2000. [Kim00b]K. Kim, H. Yoon, and K. K. O, “On-chip Wireless Interconnection with Integrated Antennas,” IEDM Technical Digest pp. 485-488, San Francisco, Ca, Dec. 2000. [Kim01]K. Kim, W. Bomstad, and K.K.O, “A Plane Wave Model Approach to Understanding Propagation in An In tra-chip Communication System,” IEEE APS Int. Symp pp. 166-169, Boston, MA, 2001 [Kur01]N. Kurd, J. Barkatullah, R. Dizon, T. Fletcher and P. Madland, “A Multigigahertz Clocking Sche me for the Pentium 4 Microprocessor,” IEEE Journal of Solid-State Circuits Vol. 36, No. 11, Nov. 2001 [Lau01]M. Saint-Laurent and M. Swamin athan, “A Multi-PLL Clock Distribution Architecture for Giga scale Integration,” Symp. VLSI Circuits Dig. Tech. Papers 2001, pp. 30-35, Kyoto, Japan [Lee00]T. H. Lee and Ali Hajimiri, “Oscillator Phase Noise: A Tutorial,” IEEE Journal of Solid-State Circuits Vol. 35, No. 3, Mar. 2000 [Li02]R. Li, K. K. O, “Signal Propagation for On-chip Clock Distribution,” Deliverable Report Pub004891, Oct. 29, 2002 [Li03]R. Li, W. Bomstad, J. Caserta, X. Guo and K. K. O, “Evaluation of Integrated Antennas for Wireless Connect ion between an Integrated Circuit and an Off-chip Antenna,” Proceedings of 2003 IITC pp. 120-122, San Francisco, CA, June 2003. [Li04]R. Li, X. Guo and K. K. O, “A Technique for Incorpor ation of a Heatsink for a System Utilizing In tegrated Circuits with Wireless Connections to An Off-chip Antenna,” Proceedings of 2004 IITC pp. 160-162, San Francisco, CA, June 2004.

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127 [Lin04a]J.-J. Lin, L. Gao, A. Sugavanam, X. Guo, Ran Li, J. E. Brewer and K. K. O, “Integrated Antennas on Silicon Subs trates for Communication Over Free Space,” IEEE Electron Device Letters Vol. 25, Num. 4, pp. 196-198 [Lin04b]J.-J. Lin, X. Guo, R. Li, J. Branch, J. E. Br ewer and K. K. O, “10x Improvement of Power Transmissi on over Free Space Using Integrated Antennas on Silicon Substrates,” Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, pp. 697-700, Orlando, Fl [Mah03]F. O’Mahony, C. P. Yue, M. A. Horowitz, and S. S. Wong, “10GHz Clock Distribution Using Coupled St anding-Wave Oscillators,” ISSCC 2003 Session 24, Paper 24.4, San Francisco, Ca [Mil97]D. A. B Miller, “O ptical Interconnect Tec hnologies for Si ULSI,” IEDM Technical Digest pp. 342-347, Washington, DC, Dec. 1997. [Mul02]A. V. Mule, E. N. Glytsis, T. K. Gaylord, and J. D. Meindl, “Electrical and Optical Clock Distribu tion Networks for Giga scale Microprocessors,” IEEE Transactions on VLSI Systems 2002 Vol. 10, No. 5, pp. 582-594, Honolulu, HI [O97]K. K. O, K. Kim, B. Floyd, and J. Mehta, “Inter and Intra-chip Clock Signal Distribution Using Microwaves,” 1997 IEEE Solid State Circuits and Technology Committee Workshop on Clock Distribution Oct. 1997, Atlanta, GA. [O99]K. K. O, K. Kim, B. A. Floyd, J. Mehta, and H. Yoon, “Inter and Intra-chip Wireless Clock Signal Distribution Usi ng Microwaves: A Status of an Initial Feasibility Study,” GOMAC pp. 306-309, Monterey, CA, 1999. [Res02]P. Restle, C. Carter, J. Eckhardt, B. Krauter, B. McCredie, K. Jenkins, A. Weger and A. Mule, “The Clock Dist ribution of the Power4 Microprocessor,” ISSCC 2002 Session8, 8.4, San Francisco, Ca [Ryu02]W. Ryu, A. Wai, F. Wei, W. La i and J. Kim, “Ove r GHz Low-Power RF Clock Distribution for a Mult iprocessor Digital System,” IEEE Transactions on Advanced Packaging, Vol. 25, No. 1, pp. 18-27, Feb. 2002, [SIA01]Semiconductor I ndustry Association, The International Technology Roadmap for Semiconductors San Jose, CA: SIA, 2001. [SIA02]Semiconductor I ndustry Association, The International Technology Roadmap for Semiconductors San Jose, CA: SIA, 2002. [SIA03]Semiconductor I ndustry Association, The International Technology Roadmap for Semiconductors San Jose, CA: SIA, 2003.

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128 [Tam82]T. Tamir, Electromagnetic Surf ace Modes, Chapter 13, Chichester, NY: John Wiley & Sons Ltd, 1982 [Tam04]S. Tam, R. D. Limaye and U. N. Desai, “Clock Generation and Distribution for the 130-nm Itanium 2 Processor With 6-MB On-Die L3 Cache,” IEEE Journal of Solid-State Circuits pp. 636-642, Vol. 39, No. 4, April 2004 [Tau98]Y. Taur and T. H. Ning, Fundame ntals of Modern VLSI Devices, 1st Edition, pp. 250-256, New York: Cambridge University Press, 1998. [Ula01]F. Ulaby, Applied Electromagneti cs, Upper Saddle Ri ver, New Jersey: Prentice Hall, 2001 [War89]K. Ware, H.-S. Lee, and C. G. Sodini, “A 200-MHz CMOS Phase-locked Loop with Dual Phase Detectors,” IEEE J. Solid-State Circuits vol. 24, no. 6, pp. 1560-1568, Dec. 1989. [Wes92]N. Weste and K. Eshraghian, Prin ciples of CMOS VL SI Design, a Systems Perspective, 2nd Edition, Reading, MA: Addison Wesley, 1992. [Xan01]T. Xanthopoulos, D. Bailey, A. Gangwar, M. Go wan, A. Jain and B. Prewitt, “The Design and Analysis of the Clock Distribution Network for a 1.2GHz Alpha Microprocessor,” ISSCC 2001 Session 25, 25.6, San Francisco, Ca [Yan04]Dongjun Yang, “Clock Generators for Frequenc y and Time Reference in Deep Submicron CMOS Technology,” Ph.D. Dissertation, University of Florida, Gainesville, FL, 2004.

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129 BIOGRAPHICAL SKETCH Ran Li was born in Lincheng, Hebei Pr ovince, China, on February 12, 1978. He received the B.S. in physics from Nankai University, Tianji n, China, in 1999. He received the M.S. degree in electrical and computer engineering from the University of Florida, Gainesville, in 2001. In 2000, he joined the Si licon Microwave Integrated Circuits and Systems (SiMICS) Research Group, University of Florida, as a Ph.D. candidate. His research interests include mi crowave integrated circuit de sign in CMOS technology, and wireless clock distributi on using integrated antennas. Ran Li is the first author of the paper which received the 2003 IEEE Internationa l Interconnect Technol ogy Conference (IITC) Best Student Paper award. He is also the firs t author of the best poster award in the 2004 External Advisory Meeting Best Poster Contest held by the De partment of Electrical and Computer Engineering, University of Florida.


Permanent Link: http://ufdc.ufl.edu/UFE0011385/00001

Material Information

Title: A Wireless clock distribution system using an external antenna
Physical Description: xiv, 129 p.
Language: English
Creator: Li, Ran ( Dissertant )
O, Kenneth K. ( Thesis advisor )
Lin, Jenshan ( Reviewer )
Bashirullah, Rizwan ( Reviewer )
Lu-Quoc, Loc ( Reviewer )
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2005
Copyright Date: 2005

Subjects

Subjects / Keywords: Electrical and Computer Engineering thesis, Ph. D.   ( local )
Dissertations, Academic -- UF -- Electrical and Computer Engineering   ( local )
Timing circuits -- Design and construction   ( lcsh )
Very high speed integrated circuits -- Design and construction   ( lcsh )
Wireless communication systems -- Design and construction   ( lcsh )

Notes

Abstract: With the increase of system operating frequency and projected die size, distributing signals across the chip becomes challenging, due to the larger R-C delays, tighter skew and jitter tolerance and signal dispersion along the metal interconnect paths. Some novel interconnection architectures are under investigation to tackle these problems, including optical interconnects, superconducting interconnects and biological interconnects. Previous works have demonstrated a wireless interconnect for clock distribution system utilizing microwaves, which is compatible with the conventional CMOS process. In such a system, clock signals propagate at the speed of light of a propagating medium. An on-chip or off-chip transmitting antenna transmits a global clock signal. A grid of on-chip receivers with integrated antennas picks up the signal, amplifies it and divides it down by 8 to provide the local clock signal. This work theoretically investigates the integrated antenna performance. Using the results from this, a wireless clock distribution system using an external antenna (inter-chip wireless clock distribution) is constructed, and characteristics are studied. First, the gain, directivity, efficiency and impedance of dipole antennas with arbitrary length, and the power transmission gain between any two dipole antennas in a lossy medium have been calculated and used to determine approaches to optimize antenna performance at a given frequency. Second, an inter-chip wireless interconnection is constructed and measured. The feasibility of an inter-chip clock distribution system is evaluated by measuring the power transmission gain between off-chip antennas and on-chip integrated antennas, and relative gain and phase distributions of signals picked up by the on-chip antennas. Also, a commercially available heatsink with fins and rectangular apertures is incorporated into this system. Third, a 17-GHz and a 20-GHz clock signal transmitter in a UMC 0.13 micron logic CMOS process have been designed, fabricated and measured. Periodic no-signal-transmission function is incorporated in the output clock signal, which is used by clock receivers for initialization and start-up. Finally, with a horn antenna as the external transmitting antenna, the operation of the entire wireless clock distribution system is successfully demonstrated for the first time. The receiver initialization and start-up steps are working well and repeatable. The total clock skew and jitter are below 5% of a period at ~ 2.2GHz over a 4-cm diameter circular area. The results of this dissertation show the feasibility and have the potential for opening the doors for new clock distribution systems which can operate at higher frequency and synchronize a larger area.
Subject: clock, distribution, initialization, integration, jitter, microwave, receiver, skew, synchronization, transmitter
General Note: Title from title page of source document.
General Note: Document formatted into pages; contains 143 pages.
General Note: Includes vita.
Thesis: Thesis (Ph. D.)--University of Florida, 2005.
Bibliography: Includes bibliographical references.
General Note: Text (Electronic thesis) in PDF format.

Record Information

Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
System ID: UFE0011385:00001

Permanent Link: http://ufdc.ufl.edu/UFE0011385/00001

Material Information

Title: A Wireless clock distribution system using an external antenna
Physical Description: xiv, 129 p.
Language: English
Creator: Li, Ran ( Dissertant )
O, Kenneth K. ( Thesis advisor )
Lin, Jenshan ( Reviewer )
Bashirullah, Rizwan ( Reviewer )
Lu-Quoc, Loc ( Reviewer )
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2005
Copyright Date: 2005

Subjects

Subjects / Keywords: Electrical and Computer Engineering thesis, Ph. D.   ( local )
Dissertations, Academic -- UF -- Electrical and Computer Engineering   ( local )
Timing circuits -- Design and construction   ( lcsh )
Very high speed integrated circuits -- Design and construction   ( lcsh )
Wireless communication systems -- Design and construction   ( lcsh )

Notes

Abstract: With the increase of system operating frequency and projected die size, distributing signals across the chip becomes challenging, due to the larger R-C delays, tighter skew and jitter tolerance and signal dispersion along the metal interconnect paths. Some novel interconnection architectures are under investigation to tackle these problems, including optical interconnects, superconducting interconnects and biological interconnects. Previous works have demonstrated a wireless interconnect for clock distribution system utilizing microwaves, which is compatible with the conventional CMOS process. In such a system, clock signals propagate at the speed of light of a propagating medium. An on-chip or off-chip transmitting antenna transmits a global clock signal. A grid of on-chip receivers with integrated antennas picks up the signal, amplifies it and divides it down by 8 to provide the local clock signal. This work theoretically investigates the integrated antenna performance. Using the results from this, a wireless clock distribution system using an external antenna (inter-chip wireless clock distribution) is constructed, and characteristics are studied. First, the gain, directivity, efficiency and impedance of dipole antennas with arbitrary length, and the power transmission gain between any two dipole antennas in a lossy medium have been calculated and used to determine approaches to optimize antenna performance at a given frequency. Second, an inter-chip wireless interconnection is constructed and measured. The feasibility of an inter-chip clock distribution system is evaluated by measuring the power transmission gain between off-chip antennas and on-chip integrated antennas, and relative gain and phase distributions of signals picked up by the on-chip antennas. Also, a commercially available heatsink with fins and rectangular apertures is incorporated into this system. Third, a 17-GHz and a 20-GHz clock signal transmitter in a UMC 0.13 micron logic CMOS process have been designed, fabricated and measured. Periodic no-signal-transmission function is incorporated in the output clock signal, which is used by clock receivers for initialization and start-up. Finally, with a horn antenna as the external transmitting antenna, the operation of the entire wireless clock distribution system is successfully demonstrated for the first time. The receiver initialization and start-up steps are working well and repeatable. The total clock skew and jitter are below 5% of a period at ~ 2.2GHz over a 4-cm diameter circular area. The results of this dissertation show the feasibility and have the potential for opening the doors for new clock distribution systems which can operate at higher frequency and synchronize a larger area.
Subject: clock, distribution, initialization, integration, jitter, microwave, receiver, skew, synchronization, transmitter
General Note: Title from title page of source document.
General Note: Document formatted into pages; contains 143 pages.
General Note: Includes vita.
Thesis: Thesis (Ph. D.)--University of Florida, 2005.
Bibliography: Includes bibliographical references.
General Note: Text (Electronic thesis) in PDF format.

Record Information

Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
System ID: UFE0011385:00001


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A WIRELESS CLOCK DISTRIBUTION SYSTEM
USING AN EXTERNAL ANTENNA















By


RAN LI














A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY


UNIVERSITY OF FLORIDA


2005















ACKNOWLEDGMENTS


I would like to thank my advisor, Professor Kenneth 0, for giving me the

opportunity to be part of the SiMICS research group and involved in the wireless

clock distribution project. His constant encouragement and guidance have been the

main reason for the success of this work. I am deeply grateful to him for what I have

learned from him, which will benefit me in my whole life.

I would like to thank Professors Jenshan Lin, Rizwan Bashirullah, and Loc

Lu-Quoc for their interest in this work and their time commitment in serving on my com-

mittee.

I would like to thank the Semiconductor Research Corporation (SRC) for sponsor-

ing this work. I would like to thank UMC for the chip fabrication.

I would like to thank the former SRC group member K. Kim, B. A. Floyd, J.

Caserta, W. Bomstad, N. Trichy, T. Dickson and J. Branch. The discussions with them and

their advice were immensely helpful for this work. Also, I would like to thank my research

colleagues Dong-Jun Yang and Xiaoling Guo, for their teamwork and great help on this

work. I am grateful to the current fellow members of SiMICS research group for their con-

tinuoues support and friendship on this project.

I would like to thank my parents, my brother and sister. Their love and encourage-

ment are the source of my strength. Finally, I am grateful to Maojiao for her love and ded-

ication behind this Ph.D. work.


















TABLE OF CONTENTS


page



A CKN OW LEGM EN TS ............................................... ii

ABSTRACT ........ ................................................. iii

CHAPTERS

1 INTRODUCTION...................................................1
1.1 Chanllenges of Conventional Interconnect Technology ............... 1
1.2 Possible Solutions................ .................... .........3
1.2.1 Low-resistivity and Low-K Materials. ..................... 3
1.2.2 Skew Compensation Using Feedbacks. ................... 4
1.2.3 Distributed Oscillators or PLLs for Clock Distribution ......... .5
1.2.4 Coupled Standing-Wave for Clock Distribution. .............. 6
1.2.5 Optical Clock Distribution Network. ....................... 7
1.3 Inter/Intra-Chip Wireless Clock Distribution Using Microwaves .......... 8
1.3.1 System Description...................................... 8
1.3.2 Challenges of Inter-chip Wireless Clock Distribution ......... 12
1.4 Overview of the Dissertation ................ ................... 13

2 THEORETICAL ANALYSIS OF LINEAR DIPOLE ANTENNAS .......... 15

2.1 O verview .................................... ..... .... .... 15
2.2 Dipole Antennas in Uniform Medium ............... ......... 16
2.2.1 Arbitrary-Length Dipole Antenna Characteristics .............. 16
2.2.2 Performance of Dipole Antenna Pair in Uniform Medium ....... 24
2.3 Summary ...............................................30

3 INTER-CHIP WIRELESS INTERCONNECTION SYSTEM .............. 32

3.1 Overview ....... ........ ........................ ............ 32
3.2 Measurement Setup Improvement ............... ............... 34
3.2.1 Measurement Setup and Its Shortcomings ................... .34
3.2.2 System Calibration .................................... 36
3.3 Measurement Results .......................................... 39
3.3.1 Characteristics of Receiving Antennas. ................... .. 39












3.3.2 Gain and Phase Distributions from External Antenna .......... 44
3.3.3 Wireless Interconnect between Receiver and External Antenna ... 46
3.4 Heatsink Incorporation .................................... ... .48
3.4.1 Heatsink Evaluation ................. ............... 48
3.4.2 Measurement Results With Heatsink ................. ... 51
3.5 A Compact Inter-chip Clock Distribution System ................. .. 55
3.6 Summary ................ ...............................59

4 CMOS CLOCK TRANSMITTER ............... ................... 60

4.1 Overview ................ ..................................60
4.2 Initialization and Start-up Scheme ...............................61
4.3 Transmitter Design ................................. ..........63
4.3.1 Voltage-Controlled Oscillator. ........................... 65
4.3.2 512:1 Divider and Logic Circuits .. ........................66
4.3.3 No-Signal-Transmission Period Generation Scheme ........... 69
4.3.4 Power Amplifier .....................................70
4.4 Measured Results of Transmitter ............... ................72
4.4.1 VCO M measured Results ............... ............... 72
4.4.2 Transmitter Output Signal ............................ 73
4.4.3 Output Power ..................................... ....78
4.5 A 20-GHz Clock Transmitter ............... ................... 79
4.5.1 VCO with New-designed Varactors ................... ..... 80
4.5.2 Reduction of Q-Factor at Intermediate Node .................. 82
4.5.3 Power Amplifier Redesign .............................. 83
4.5.4 Measured Results ..................................... 85
4.6 Summary ................................................88

5 DEMONSTRATION OF INTER-CHIP CLOCK DISTRIBUTION .......... 90

5.1 Overview ........................................... ......... 90
5.2 Measurement Setup ......................................... 91
5.3 Inter-chip Clock Distribution System Demonstration ................... 95
5.3.1 System Demonstration without Heatsink ..................... 95
5.3.2 System Demonstration with Heatsink ................... 102
5.3.3 Comparison among Clock Distribution Systems .............. 106
5.4 Summary ...............................................107

6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK ............... 109

6.1 Summary ............................................ ....... 109
6.2 Future Works. ............. ................................ 110
6.2.1 Demonstration of Compact Clock Distribution System ......... 111
6.2.2 Removal of the External PA ........................... 111
6.2.3 Higher Clock Frequency and Smaller On-chip Antenna ........ 111












APPENDIX

WAVE PROPAGATION BETWEEN ON-CHIP ANTENNA PAIR ............ 114

A. 1 Multi-path Model for On-chip Antenna Pair ........................ 114
A.2 Electric Field Due to Path A, C, D ............... .............. 117

LIST OF REFERENCES. ..... .......................................... 124

BIOGRAPHICAL SKETCH. ..........................................129

















LIST OF TABLES


Table Page

3-1 C ut-off frequencies ............................................... 49

4-1 Transistors sizing for the first 4 stages SCL divider ................... ...68

5-1 Comparison of high-performance clock distribution networks recently reported. 106


















LIST OF FIGURES



Figure Page

1-1 H-tree clock distribution network ...................................... 2

1-2 Diagram of skew compensation scheme (a) two feedback paths (b) one feedback path
................ ................... ................... .......... 4

1-3 Diagram of clock distribution with (a) distributed ring oscillators (b) distributed PLLs
................ ................... ................... .......... 5

1-4 Clock distribution network using coupled standing-wave (a) Clock distribution (b)
Coupled standing-wave oscillators. ................................. 6

1-5 Optical clock distribution with the propagation medium of(a) freespace (b) waveguides
. . . . . . . . . . . . . . . . 8

1-6 Conceptual diagrams of(a) intra-chip (b) inter-chip wireless clock distribution system
................ ................... ............................ 9

1-7 Block diagram of clock transmitter. .................................. 11

1-8 Block diagram of clock receiver ..................................... 11

2-1 Linear dipole antenna ............................................... 16

2-2 Directivity vs. frequency for a 2-mm antenna pair in free space, A1N and 20 Q-cm Si
...................................... .......................... 22

2-3 Radiation efficiency vs. frequency for a 2-mm antenna in free space, A1N and 20 Q-
cm Si ....... ... ..... .. ........................ ....... 22

2-4 Effective area vs. frequency for a 2-mm antenna in free space, A1N and 20 Q-cm Si
............................................. ............ ........ 23

2-5 A dipole antenna pair in a uniform medium ............... .............. 23











2-6 Power gain vs. frequency for a 2-mm antenna pair in free space, A1N and 20 Q-cm Si
......... .. ................. .............. ........ 25

2-7 Power gain vs. distance for a 2-mm antenna pair in different media at 24 GHz .25

2-8 Power gain vs. frequency in 20 Q-cm Si for different antenna length .......... 26

2-9 Peak power gain vs. corresponding frequency in Si with different resistivity 27

2-10 Power gain vs. antenna length at 20 and 100 GHz in 20 Q-cm and 100 Q-cm Si .28

2-11 Optimal antenna length vs. corresponding frequency in freespace, A1N and Si .28

2-12 Power gain vs. resistivity of silicon, at optimal antenna length ............. 29

2-13 Radiation pattern at the optimal antenna length at 20 GHz and 100 GHz ...... 30

2-14 Radiation pattern at 0.5 x the optimal antenna length at 20 GHz and 100 GHz... 30

3-1 Clock distribution using an off-chip antenna .......................... 32

3-2 Measurement setup ..................................... ............ 34

3-3 Balun and semi-rigid cables .......................................35

3-4 Antenna test chamber with absorber liners ........................... 36

3-5 Measured impedance of 2-mm zigzag dipole .......................... 37

3-6 Two-port network composed ofbalun, semi-rigid cables and probe .......... .38

3-7 Comparison of measured S11 and calculated S11 ......................... 38

3-8 Layout of the test chip .............................................39

3-9 Antenna gain on a 20-Q-cm substrate. .............................. 40

3-10 Zigzag dipole antenna gain as a function of the separation between a wafer and an
off-chip antenna. ........ ..... ................... ........ 40

3-11 Zigzag dipole gain performance on different substrates .................. 41

3-12 Average gain (24 to 24.2 GHz) vs. separation for 2-mm zigzag dipole antenna. ..41

3-13 Average gain (24 to 24.2 GHz)vs. substrate resistivity for zigzag dipole antennas 42












3-14 Inter-chip antenna pair gain for varying substrate resistivity and thickness. ..... 43

3-15 Across a 2-inch-diameter opening with a 7.5-inch separation (a) relative gain (dB)
distribution, (b) phase (degree) distribution .......................... 44

3-16 Across a 4-inch-diameter opening with a 7.5-inch separation (a) relative gain (dB)
distribution, (b) phase (degree) distribution .......................... 45

3-17 A block diagram of a 0.18-ptm clock receiver with a zigzag dipole antenna.. .. 46

3-18 Sensitivity vs. frequency plots for different separation between the receiver and off-


chip transmitting antenna.


. . . . . . . . . . 4 7


Generic heatsink and modified heatsink ............................. 48

Waveguide models.................. .........................49

Generic heatsink and modified heatsink ................. ............. 50

Gain vs. frequency under different situations .......................... 51

Gain vs. frequency for different antennas ............................ 51

Gain and phase vs. location in each aperture at 23.25 GHz. ............... 53

Relative gain and phase at center of each apertures at 24GHz .............. 54

Proposed inter-chip clock distribution system. ...........................56

Antenna test chamber .................. ........................ 56

Across a 4-inch-diameter opening with a planar array antenna (a) relative gain (dB)
distribution, (b) phase (degree) distribution .......................... 57

Relative gain and phase at center of each apertures at 24GHz ................ 58

Initialization and start-up scheme. ................. ............. 62

Clock transmitter block diagram ................................ 63

Die photograph of clock transmitter .................................64

Circuit schematic of VCO and buffer ............... ................65

Block diagram of 512:1 frequency divider ........................... 67


3-19

3-20

3-21

3-22

3-23

3-24

3-25

3-26

3-27

3-28


3-29

4-1

4-2

4-3

4-4

4-5











4-6 A block diagram of control-signal-generation circuit ................ ... .. 69

4-7 Circuit schematic of generating no-signal-transmission period ............. 69

4-8 Simulated output clock signal and control signal ....................... 70

4-9 Circuit schematic of output power amplifier. ......................... .71

4-10 The simulated differential output waveform from PA. ................... .71

4-11 Output phase noise and spectrum of VCO. ........................... 72

4-12 V C O tuning range ............................................ 73

4-13 Measurement setup of the transmitter ............... ................74

4-14 Waveforms of control signal and clock signal (synthesizer as the clock source) .75

4-15 Waveforms of control signal and clock signal (VCO as the clock source) ....... 75

4-16 Transmitter output spectrum .......................................76

4-17 The measurement setup of using a transmitter on a PC-board .............. 76

4-18 Waveforms of control signal and clock signal (Transmitter on board) ........ 77

4-19 RM S jitter of the output clock signal ............................... 77

4-20 Output power vs. clock frequency ............... ................... 78

4-21 Power amplifier output matching. ................................. 79

4-22 Die photograph of the 20-GHz clock transmitter ....................... 80

4-23 Layout of the newly designed MOS varactor ............................ 81

4-24 Output phase noise and spectrum of the 20-GHz VCO. ............. .. 82

4-25 Tuning range of the 20-GHz VCO ..................................... 82

4-26 500-pH spiral inductor with a 200-Q parallel resistor. ................... 83

4-27 Output stage of clock transmitter including PA and no-signal-transmission genera-
tion circuits. .................................... ........ 83

4-28 Simplified small-signal model of the common-source PA ............... 84











4-29 Output clock waveform of the 20-GHz clock transmitter (on-chip) ............ 85

4-30 Output clock waveform of the 20-GHz clock transmitter (on-board) .......... 86

4-31 RMS jitter of transmitted clock signal and triggering signal ............... 87

4-32 Output power vs. clock frequency ............... ................... 87

5-1 Inter-chip clock distribution using a planar array antenna. ................ 91

5-2 A measurement setup ofthe wireless clock distribution system with an external antenna.
.............. .................... ......................... .92

5-3 Photo of the measurement setup for the inter-chip clock distribution .......... 92

5-4 Photograph of transmitter and receiver boards ....................... 93

5-5 Die photograph of the clock receiver ............... ................ 94

5-6 A measured waveform of the locked local clock signal (without heatsink) ...... 96

5-7 Local clock signal waveform over a shorter time period. ................. 97

5-8 Measured RMS jitter of the local clock signal and triggering signal ......... 98

5-9 Places in the cover opening to which the receiver chip can be moved ........ 100

5-10 Local clock signal waveforms with receiver at 9 different places .......... 101

5-11 Skew am ong the 9 places ...................................... 101

5-12 M easurement setup with a heatsink ............................. 103

5-13 A measured waveform of the locked local clock signal (with a heatsink) ...... 104

5-14 Measured RMS jitter of the local clock signal and triggering signal (with a heatsink).
...................................................... ...... 104

A-i Power gain vs. frequency for different propagation medium ................ 114

A-2 Power gain vs. Frequency for A1N with different thickness ................. 115

A-3 Measurement setup of on-chip antenna pair ......................... 116

A-4 W ave paths of propagation ..................................... 116












A-5 Lateral wave field ........ .......................................117

A-6 Possible lateral wave path between an on-chip antenna pair ............... 118

A-7 Calculated attenuation factor G when the distance is 5mm ............... 120

A-8 Wave transmission between SiO2 and Si ........................... 121

A-9 Calculated normalized E-field at the receiving antenna vs. frequency ......... 122

A-10 Measured power gain vs. frequency ............... ................ 122

A-11Dip frequency vs. A1N thickness. ................................... 123
















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

A WIRELESS CLOCK DISTRIBUTION SYSTEM
USING AN EXTERNAL ANTENNA

By

Ran Li

August 2005

Chair: Kenneth K. O
Major Department: Electrical and Computer Engineering

With the increase of system operating frequency and projected die size, distribut-

ing signals across the chip becomes challenging, due to the larger R-C delays, tighter skew

and jitter tolerance and signal dispersion along the metal interconnect paths. Some novel

interconnection architectures are under investigation to tackle these problems, including

optical interconnects, superconducting interconnects and biological interconnects. Previ-

ous works have demonstrated a wireless interconnect for clock distribution system

utilizing microwaves, which is compatible with the conventional CMOS process. In such

a system, clock signals propagate at the speed of light of a propagating medium. An

on-chip or off-chip transmitting antenna transmits a global clock signal. A grid of on-chip

receivers with integrated antennas picks up the signal, amplifies it and divides it down by

8 to provide the local clock signal. This work theoretically investigates the integrated

antenna performance. Using the results from this, a wireless clock distribution system









using an external antenna (inter-chip wireless clock distribution) is constructed, and its

characteristics are studied.

First, the gain, directivity, efficiency and impedance of dipole antennas with arbi-

trary length, and the power transmission gain between any two dipole antennas in a lossy

medium have been calculated and used to determine approaches to optimize antenna per-

formance at a given frequency. Second, an inter-chip wireless interconnection is

constructed and measured. The feasibility of an inter-chip clock distribution system is

evaluated by measuring the power transmission gain between off-chip antennas and

on-chip integrated antennas, and relative gain and phase distributions of signals picked up

by the on-chip antennas. Also, a commercially available heatsink with fins and rectangular

apertures is incorporated into this system. Third, a 17-GHz and a 20-GHz clock signal

transmitter in a UMC 0.13jtm logic CMOS process have been designed, fabricated and

measured. Periodic no-signal-transmission function is incorporated in the output clock

signal, which is used by clock receivers for initialization and start-up. Finally, with a horn

antenna as the external transmitting antenna, the operation of the entire wireless clock dis-

tribution system is successfully demonstrated for the first time. The receiver initialization

and start-up steps are working well and repeatable. The total clock skew and jitter are

below 5% of a period at 2.2GHz over a 4-cm diameter circular area. The results of this

dissertation show the feasibility and have the potential for opening the doors for new clock

distribution systems which can operate at higher frequency and synchronize a larger area.















CHAPTER 1
INTRODUCTION

1.1 Challenges of Conventional Interconnect Technology

The integrated circuit (IC) die size and clock signal frequency are being increased

and feature size is being scaled to accommodate faster and more complex functionality.

According to the 2003 International Technology Roadmap for Semiconductors (ITRS),

the chip areas for high performance microprocessors are projected to be 310mm2, with the

chip clock frequency of 9.29 and 12.4GHz at the 65 and 50-nm technology nodes, respec-

tively [SIA03]. The propagation delay of a signal on a metal line is approximately

0.35RC12 [Wes92]. R and C are the resistance and capacitance-per-unit-length of metal

lines. Scaling down of the CMOS IC feature size increases the RC time constant [Boh95,

Tau98]. With the increase of clock frequency, this increases even faster due to the increase

of resistance of metal lines resulting from the skin effect. All these lead to a larger delay

through the metal interconnection lines.

With the increase of clock frequency and chip size, the lengths of global intercon-

nect metal lines become close to the wavelength, and hence the global interconnects will

function as transmission lines. The complex propagation constant y is given by Eq. 1.1. G


y = a +jp = ,(R+ jooL).(G+ jooC) (1.1)


and L are the conductance and inductance per unit length of the metal lines. The attenua-

tion constant ao, which is the real part of complex propagation constant, increases with







2

clock frequency. In addition, global interconnect lengths goes up with the increase of die

size (1). These two factors increase the voltage attenuation (e i.e., the power loss)

along the metal lines, which will require more drivers on the interconnection paths. On the

other hand, because of the loss of transmission lines, clock dispersion also becomes a seri-

ous problem, which leads to an increase of the rise and fall times of the clock signals

[Deu98].

These issues pose great challenges for global clock signal distribution. In a clock

signal distribution system, low skew, low jitter and low power-dissipation are critical

requirements. Skew is defined as the static phase mismatch among local clocks, while jit-

ter is the time dependent random phase variation of clock signals caused by noise. Nor-

mally, the total skew and jitter tolerance in a microprocessor should be typically less than

-10% of a clock period. The conventional global clock distribution often uses an H-tree to

match the phases of local clock signals (Figure 1-1). The mismatches of different signal

paths and clock buffers will generate clock skew. At lower clock signal frequencies, an


CLK


Figure 1-1. H-tree clock distribution network







3

H-tree can be used to distribute the clock signals with acceptable clock skew. With the

improved performance of microprocessors, the clock frequency has become higher, result-

ing in a decrease of the clock period and hence making the skew tolerance tighter in abso-

lute time. Also, the propagation delay becomes larger with the increase of clock frequency

and chip size. It becomes more and more difficult to match the larger propagation delays

to a tighter skew tolerance. In an H-tree, jitter accumulates with the distance from a clock

source, and clock repeaters and buffers increase jitter because of the substrate and power

supply noise. At higher clock frequencies, the jitter tolerance in absolute time also

becomes tighter. In modern high-performance microprocessors, the power dissipation

could be larger than 100W. Driving the loads through the clock tree with the total length in

the order of kilometers uses 30% or even 50% of this power [Kav00]. Because of these,

the clock distribution using conventional approach is becoming more difficult with each

technology generation.

1.2 Possible Solutions

The global wiring issue has been identified as a long-term "Grand Challenge" for

semiconductor industry by the 2001 International Technology Roadmap for Semiconduc-

tors [SIA01]. To tackle this problem, many ideas and techniques have been investigated in

the past decade. All the new techniques improve some aspects among the above men-

tioned problems. However, each of them has its own pros and cons.

1.2.1 Low-resistivity and Low-K Materials

Copper and low-k dielectrics were introduced to reduce the RC propagation delay

in the global interconnect system. With lower resistivity p and lower dielectric constant k,

new materials can decrease the R and C by the same ratio as p and k, and reduce the clock







4

skew associated with the path length mismatch. However, with the increase of chip area,

the RC propagation delay is still becoming larger. Use of new materials will also soon

encounter their fundamental limits [Deu98]. It can only extend the lifetime of the conven-

tional global interconnect system by several generations. New techniques have to be dis-

covered to overcome the limitations.

1.2.2 Skew Compensation Using Feedbacks

The use of feedback is a way to compensate the clock skews at different points in a

clock network (Figure 1-2). A skew compensation scheme among three different

local-clock-trees in an H-tree is shown in Figure 1-2 (a) [Hsi98]. Two feedback paths are

connected to the root and one leaf in a local clock tree, respectively. The compensator

measures the round-trip delays from the roots to leaves. Then, the phases are compared

and the error is compensated. Figure 1-2.(b) shows an H-tree operating in a similar way.

The comparator compares the phase difference between two leaves in two different local



LGlobal
clock
Delay ----- Delay


PLL Compensator N "m .I mratr







(a) (b)

Figure 1-2. Diagram of skew compensation scheme with (a) two feedback paths
(b) one feedback path







5

clock trees. The phase error is compensated by a DLL [GutOO]. The skew compensation

scheme can significantly reduce the clock skew. However, this scheme increases the

power consumption. In addition, the jitter still accumulates along the H-tree and actually

is doubled because of the feedback. This scheme leaves the jitter an unsolved problem.

1.2.3 Distributed Oscillators or PLLs for Clock Distribution

Distributed oscillators and distributed phase locked loops (PLL's) were imple-

mented to reduce both jitter and skew. Figure 1-3 (a) shows a distributed three-phase ring

oscillators for the clock distribution [Hal97]. Figure 1-3 (b) shows distributed PLL's

which are kept synchronized [Lau01]. In both schemes, an oscillator is used to provide

clock signals to a small area. Because all the oscillators are in phase, the clock skew is

only generated by the mismatch of the buffers and phase detectors, which is small. The jit-

ter is attenuated because all the oscillators or PLL's are local and the jitter is not accumu-

lated through the global distribution network. However, this scheme is too complex and



Master
PLL--D






o PLL
0 Phase Detector
(a) (b)
Figure 1-3. Diagram of clock distribution with (a) distributed ring oscillators
(b) distributed PLLs






6
difficult to implement. In addition, because of the distributed oscillators or PLL's, the

power consumption is significantly increased.
1.2.4 Coupled Standing-Wave for Clock Distribution

A recent paper discussed a global, standing-wave clock distribution network

[Mah03], in which the properties of standing waves on a transmission line are applied. A

standing wave can be formed when two identical waves propagate in the opposite direc-

tions on a transmission line. Along a standing wave, the phase is the same at all points.

The standing-wave clock distribution network is shown in Figure 1-4. Transmission lines
form the network. Standing waves are formed by the sum of the incident wave and the

reflected wave from a short termination. Distributed standing-wave oscillators are coupled

together and injection-locked onto the external clock source to compensate the loss on the
transmission lines. Ideally, the clock skew in this clock distribution network should be

zero.

Transmission line
\ B--WO


C


1 global
clock
m1= m m


r1 mm = 4.


Clock buffer
(a) (b)
Figure 1-4. Clock distribution network using coupled standing-wave
(a) Clock distribution (b) Coupled standing-wave oscillators







7

Compared to the conventional clock distributions, a standing-wave clock distribu-

tion network can operate at multi-GHz with very small skew. A total skew of 3.3% of a

period in a 10GHz standing-wave clock distribution network was achieved over a chip

area of 3mm2 [Mah03]. However, this clock distribution system is difficult to implement

because a grid of transmission lines has to be constructed on chip. In addition, the power

consumption increases because of the distributed standing-wave oscillators.

1.2.5 Optical Clock Distribution Network [Mul02]

Optical clock distribution was proposed by Goodman in 1984. Using optical signal

instead of electrical signal to distribute the clock signal, the optical clock distribution

bypasses the clock frequency limitation of conventional interconnect technology [Mil97].

An optical clock distribution includes a photon source, a propagation medium, a diffrac-

tive optics device for light redirection, an optical-to-electrical converter and an on-chip

receiver to amplify the photocurrents and generate the local clock signal. Presently, most

of the published optical clock distribution systems are inter-board or inter-chip. There are

two main types of optical clock distribution systems distinguished by the propagation

medium. Figure 1-5(a) shows the optical clock distribution using focused free-space,

where a diffractive optical device is used to focus the light beam from the optical source to

a desired area. The photodetectors distributed over the area convert the optical signal to

electrical signal. Figure 1-5(b) shows the optical clock distribution using on-board or

on-chip fiber-optic waveguides. An H-tree-like waveguide network is constructed on

board or on chip to guide the light to the desired locations.






















Si integrated
Circuit


Photon Source


(a) (b)

Figure 1-5. Optical clock distribution with the propagation medium of
(a) freespace (b) waveguides.

In an optical clock distribution system, the maximum clock frequency can be very

high. Because the signal propagates at the speed of light, the propagation delay is almost

negligible, and the skew will be small. The interconnects are isolated from the power sup-

ply and substrate noise. Jitter only comes from the noise of clock receivers, which is

expected to be smaller. It seems like an ideal choice. However, the optical clock distribu-

tion network is difficult to implement. The integration level is low and the cost is high.

Furthermore, the on-chip photodetectors and receivers are not easy to implement. These

issues made the use of optical clock distribution systems challenging.

1.3 Inter/Intra-Chip Wireless Clock Distribution Using Microwaves

1.3.1 System Description

With the increase of operation frequency, the wavelength decreases and the inte-

gration of small antennas on chip to transmit and receive clock signals becomes possible.

At 24 GHz, the wavelength in freespace is 12.5mm, and about 4mm in a silicon substrate.

The length of a quarter-wave antenna will be 3 and 1 mm in freespace and a silicon sub-













R1 TamIntegrate
R" R" R" R Transmitting Circuits
Antenna Heatsink-
RI R RI RF -\

ZU-


RR R 1 R R1 {--i-j

Receiving Antenna
Within an IC

(a) (b)

Figure 1-6. Conceptual diagrams of (a) intra-chip (b) inte-chip wireless clock
distribution system

state, respectively. Based on this, two wireless clock distribution systems utilizing inte-

grated antennas were proposed: intra-chip and inter-chip [097, 099, Flo00]. Figure 1-6

shows the conceptual diagrams of the intra-chip and inter-chip clock distribution systems.

In an intra-chip clock distribution, a near 24-GHz global clock signal is generated by an

on-chip transmitter. Transmitted by an on-chip transmitting antenna at the center of the

chip. The global clock signal is picked up by a grid of receivers with an on-chip antenna

across the chip [Appendix]. The received signal is then amplified and divided down by 8

to provide the local clock signals. The inter-chip clock distribution uses an external trans-

mitting antenna instead of an on-chip antenna to distribute the global clock signal across

the chip. This work focuses on the inter-chip wireless clock distribution system evaluation

and demonstration.







10

A single-tone sine wave instead of square wave is used in the wireless system for

clock distribution, which eliminates the requirement for a large number of repeaters to

maintain the sharp clock edges. Therefore, the power dissipation could be lower [Flo99].

The inter-chip clock distribution is investigated because it has several advantages

over the intra-chip clock distribution. In an inter-chip clock distribution system (Figure

1-6(b)), there is almost no difference in time of flight and amplitude of received signal,

and the interference effects due to the planar metal structures on chip should be smaller.

These lead to more uniform power amplitude and phase distributions of clock signals, and

smaller skew. Furthermore, with a large external antenna to transmit the global clock sig-

nal, the size of integrated receiving antennas can be reduced, and the synchronization area

can be significantly increased.

The heatsink and packaging issues have to be taken into consideration in an

inter-chip clock distribution system. This work proposes a way for incorporating a heat-

sink with rectangular apertures and fins in the system on the backside of the chips, with

BGA MCM packages and a board on the top side of the chips.

The proposed transmitter block diagram is shown in Figure 1-7 [FloOla]. A

24-GHz clock signal is generated by a voltage controlled oscillator (VCO) and locked by a

phase-locked loop for small phase noise or jitter. A 24-GHz power amplifier amplifies the

signal and delivers it to the transmitting antenna. The transmitter chip will be mounted on

a PCB board, and SMA connectors are used to connect the transmitter output and off-chip

transmitting antenna.

Figure 1-8 shows the block diagram of clock receiver [FloOla]. In the system,

on-chip receiving antennas pick up the global clock signal. The received signal is ampli-












........................................
Phase-Locked Loop

F
Loop -*
PFD LoopVCO
- PFD -- Filter vco



Freq. Divider --

........................................


Figure 1-7.






Receiving __
Antenna
(-24 GHz)


Transmitting
Antenna


Block diagram of clock transmitter


Local Clock
Output
(-3 GHz)


Figure 1-8. Block diagram of clock receiver

fled by a low-noise amplifier and divided down by an 8:1 frequency divider. The output

buffer delivers the -3GHz local clock signal.

Compared to the optical clock distribution system, microwave and integrated

antennas are utilized in this work instead of light to distribute the clock signals. Micro-

waves propagate at the speed of light, in the same way as the optical signal. Maximum

clock frequency is significantly increased. Since the propagation delay is smaller, the

clock skew will be mainly given by the mismatch of receivers. Jitter will not accumulate

along the global signal path, but is only dependent on the performance of receivers and


fREF







12

noise on the chips. Hence some of the sources which increase jitters in the conventional

global clock distribution systems are removed. Because the frequency of global clock sig-

nal is much higher than the operating frequency of local circuits, the disturbance in the

local circuits due to the transmitted microwaves is reduced. More importantly, the

inter-chip wireless clock distribution is compatible with the conventional CMOS technol-

ogy. All the integrated antennas can be fabricated in a standard CMOS process. In addi-

tion, a planar-array antenna is introduced in this work to construct a compact inter-chip

clock distribution system, which has the same form factor as that in desktop systems.

Without the fiber-optic waveguides and the diffractive optical devices in the optical clock

distribution, the proposed approach is compatible with the present CMOS technology

trend.

1.3.2 Challenges of Inter-chip Wireless Clock Distribution

First, a requirement for implementing a wireless clock distribution system is suffi-

cient power transmission gain between the transmitting and receiving antennas. The

power gain is mainly limited by the performance of on-chip antennas, which is a key

parameter that determines the feasibility of the entire system. The external antenna perfor-

mance determines the area that can be synchronized and the system skew. A high-gain and

wide-beamwidth antenna is desirable. Second, the area consumption of on-chip antennas

is another big concern. Third, jitter and skew over an area that needs to be synchronized

are fundamental performance parameters of a clock distribution system, which must be

studied. This work will focus on the analyses of on-chip antenna performance, and the

implementation of an inter-chip wireless clock distribution system.









1.4 Overview of the Dissertation

Theoretical analyses of on-chip antennas are carried out in this work using funda-

mental electromagnetic formulas. The feasibility of integrated antennas is analyzed from

this point of view. A measurement setup for inter-chip wireless interconnect is constructed

to measure the power transmission gain and phase of S21 between an external antenna and

on-chip antennas [Bom02]. Using this setup, on-chip antennas, external antennas, and the

impact of a heatsink are characterized. With the measured results, the feasibility of an

inter-chip wireless clock distribution system is evaluated. In the second part of this disser-

tation, an inter-chip wireless clock distribution system with a heatsink is demonstrated.

One difficulty is calculating the on-chip antenna parameters such as efficiency,

directivity, and impedance in the presence of multiple dielectric layers and a conductive

silicon substrate. However, parameters of antennas in a uniform, linear isotropic medium

such as freespace or silicon can be calculated to provide the basis for a qualitative under-

standing of trends. The electromagnetic formulas and calculation results are presented in

Chapter 2.

Chapter 3 discusses an inter-chip wireless interconnection system, including an

antenna test chamber, external antenna, testchips and the measurement setup. Three

testchips were designed and fabricated in the UF clean room. The feasibility of inter-chip

wireless clock distribution was evaluated by characterizing a Gaussian optic horn antenna

and a planar array antenna, by measuring the power transmission gain between external

antennas to on-chip antennas, and by characterizing the performance of on-chip antennas

with different structures and lengths. The advantages and drawbacks of the inter-chip

clock distribution are discussed. A heatsink is also introduced in Chapter 3. The effects of







14

fins and rectangular apertures in the heatsink on wave propagation are evaluated. The

inter-chip wireless interconnection system with a heatsink is measured, and the feasibility

of wireless clock distribution in the presence of a heatsink is discussed.

To realize the inter-chip clock distribution, there must be a scheme to start all the

receivers in the synchronization area at the same time, so that all the local clock signals

have the same phase. A system initialization and start-up scheme is presented in Chapter 4

[Yan04]. Two clock transmitters that meet the requirement of this scheme are designed

and fabricated in a UMC 0.13[tm logic CMOS process. The design and measurement

results of the transmitters are presented in Chapter 4.

In Chapter 5, the measurement setup and measured results of a wireless clock dis-

tribution system using an external antenna are presented. The clock transmitter presented

in Chapter 4 and a clock receiver developed by X. Guo and D. J. Yang are used for the

demonstration. With a horn antenna as the external transmitting antenna, an inter-chip

wireless clock distribution system is successfully demonstrated, in the presence of a heat-

sink.

Lastly, in Chapter 6, the Ph.D. dissertation work is summarized and future work is

suggested.















CHAPTER 2
THEORETICAL ANALYSIS OF LINEAR DIPOLE ANTENNAS

2.1 Overview

The performance of integrated antennas plays a key role determining the perfor-

mance of an inter-chip wireless clock distribution system. The power transmission gain

between an external antenna and on-chip receiving antennas determines the power a

receiver can pick up and the power a transmitter has to deliver. The power transmission

gain depends on clock frequency, distance between an antenna pair, and individual

antenna parameters such as efficiency and directivity. Although the power transmission

gain between an antenna pair can be measured directly using a network analyzer [KimOO],

some important individual antenna parameters such as efficiency, directivity and radiation

patterns are difficult to measure. Former works have demonstrated the wireless intercon-

nection at 7.4 and 15 GHz using 0.25 and 0.18-[im CMOS technologies [Flo00, FloOlb].

In addition, the research on monolithically integrated true single chip radio ([tNode)

shows that integrated antennas are sufficient for wireless interconnection up to 5m or

larger separations at 24 GHz [Lin04a, Lin04b]. Projecting from these, wireless intercon-

nection at 100 GHz or higher should be possible at the end of the current ITRS. Hence, the

understanding of integrated antenna performance at high frequencies is critical. In an

inter-chip wireless clock distribution system, integrated antennas operate in a multi-layer

environment consisting of silicon substrate (500-[tm), oxide layers with metal intercon-

nects (< 10 [tm) and air, which makes the analytical studies of these antennas extremely







16
difficult. However, antennas in a linear, isotropic dielectric medium can be evaluated

using the fundamental electromagnetic formulas. This chapter presents the matlab simula-

tion of dipole antennas with different lengths in free space, aluminum nitride (A1N) and

silicon at different frequencies. The effect of silicon resistivity on power transmission gain

between a dipole antenna pair is also investigated.

2.2 Dipole Antennas in Uniform Medium

2.2.1 Arbitrary-Length Dipole Antenna Characteristics [Ula0l]

Antenna performance is determined by antenna gain 6, efficiency ,, directivity

D, effective area A impedance Z and so on. In a wireless clock distribution system, lin-

ear dipole antennas and zigzag dipole antennas are mainly used as the receiving and

on-chip transmitting antennas because of their reasonable directivity and antenna gain,

besides being easy to implemented in an integrated circuit. The parameters of an arbi-

trary-length dipole antenna in a uniform medium can be directly calculated.



Q(R,, 4)



1(t)


Figure 2-1. Linear dipole antenna







17

Figure 2-1 shows a linear dipole antenna placed at the origin of a spherical coordi-

nate system [Ula01]. A sinusoidally varying current I(t) is delivered into the antenna from

the center point. I(t) is given by

I(t) = 0I coso t (2.1)


For a linear dipole antenna with arbitrary length 1 with current fed from the cen-

ter, the current distribution is sinusoidal and symmetric among its two halves. The current

amplitude must go to zero at two ends. Therefore, the current amplitude distribution along

the dipole antenna I(z) can be derived as


I sin 0 < Z <
SL\ Z1 ] 20
-2





Here k is the wavenumber which is given by

k = 2 7 (2.3)
c k


The electric and magnetic fields at any point in space due to the varying current

I(t) on the antenna can be calculated through the retarded vector potential A. Any elemen-

tal length dz on the dipole antenna can be regarded as a short dipole antenna, and the dif-

ferential electric field dEe from this short dipole at point 4(R, 0, 4) can be expressed

using the short-dipole-antenna model.
e- k ss dz. fosin Lkl--z 0 jkrl0O0 e jkzcos0 sL2 I 2
dE sine s dz (2.4)
6 47T r R osin 1 12
4 sin] < Z < 0
10 X2 2







18
The total electric field at point 0(R, )) can be derived by integration over the

whole dipole antenna

1/2 -jk cos 2 cos cos 2(
E0 = dE = j60 I 2 Cos in0 -- (2.5)
1/2 R


Power density from an antenna is a key parameter which reflects the radiation pat-

tern, directivity, and radiated power, effective area. The time-average power density S(0)

from an arbitrary-length dipole antenna can be calculated from the differential electric

field, which is expressed by

15 cos( cos) cos( 151
S(0) = cn =c- r(0) (2.6)



With input current I(t), the total power radiated from an arbitrary-length dipole

antenna can be derived through integration of the power density over 0 and )

1512
Prad= R S(R, 0,4) sin dd = rY() sinO O d4 (2.7)
4)0 4)0

Antenna directivity and efficiency determine the antenna performance. The defini-

tion of antenna directivity D is the ratio of the maximum radiation intensity to the average

values of the radiation intensity over space. With the time-average power density S(0),

the directivity of an arbitrary-length dipole antenna can be obtained as

Sj 4I5( 4 x 5(H 2 1 cos s 2
-. Pad = (2.8)
ave rad 2l S(O) Rsind0O Y(O)sin6oO
0 0







19

In most cases, the highest directivity from an dipole antenna is in the direction of

0 = However, when the antenna length is long, this is no longer the case. For instance,
2
when the antenna length is two wavelengths, the directivity is zero in this direction.

When an antenna is used in a receiver, the intercepted power Pin t of the receiv-

ing antenna from an incident wave with power density S. is


(2.9)


P = S .A
int 1 e '


where A is the antenna effective area, which is directly dependent on directivity
e/


2
A =
e 47r


(2.10)


The antenna efficiency 4 is defined as the ratio of the radiated power to the total

power it consumes, which includes the radiated power Prad and dissipated power P oss


P
P ra d
rad loss


Srad
R rad+ R loss


The radiation resistance of an arbitrary-length antenna can be derived from the

time-average radiated power


2P 7
rad 0
0


2. 27 S(O)'2 sin 0o
0

0
-0____
O


7r
60 Y(0) sin0 oO
0


P rad
Pt


(2.11)


(2.12)










The loss resistance of an arbitrary-length antenna at high frequencies is approxi-

mately

R /t[t 1 (2.13)
loss = 2(a+ b)


where the skin effect is taken into account.

In this equation, [t and o are the magnetic permeability and conductivity of the

metal constructing the antenna. Normally, the transverse section of an on-chip dipole

antenna is rectangular. In Eq. 2.13, a and b are the width and height of the dipole antenna

(Figure 2-1). Eq. 2.13 shows that the loss resistance is frequency-dependent.

Antenna gain can be expressed by G = D, where is the antenna efficiency and

D is the directivity. With the above formulas, the performance of an arbitrary-length

dipole antenna in a uniform medium can be estimated.

When a uniform medium has a relative dielectric constant sr, the expression for

time-average power density changes because the wavelength decreases by a ratio of /I

15L cos coso- cos 2 151
S(O) = 0 Y(O) (2.14)
2T I slno T sinI


In this equation,

S 0 0 (2.15)



The expressions for antenna directivity and efficiency are the same as those for the

free space case except that the wavelength is expressed by Eq. 2.15.







21

When a dipole antenna is in silicon, the situation will be different because of the

conductivity of silicon. In silicon, the wave vector k = 3 + ja = |A] e which is a

complex number. A complex dielectric constant s' = s + j- replaces the previously
0)
used dielectric constant 8. Using the same procedure for calculating the electric and mag-

netic fields and the time-average power density, the power density radiated from an arbi-

trary-length dipole antenna in silicon can be expressed as

cosQ -2a 2aR'2 cos lcos -cos 2 cosoQ -2aR
S(O) = 2L sine p Y(O) (2.16)


From here, the directivity in the direction of 0 = 7/2 is

4 (9 2[ -cos(P- 2
P- (2.17)
raod rc
JY(0)sin0 o
0

To calculate the antenna efficiency in silicon, the radiation resistance and loss

resistance have to be derived. The loss resistance Ross is kept the same as before, and

the expression of the radiation resistance changes to

2. 27f S(0) sin0 oO
R rad 0 (2.18)
rad
0 0

The impedance of a dipole antenna can be expressed as

Zn = R. + jXin = R d+ Ross+ jXin (2.19)
in in in rad loss in

The value of Xin is a function of 1/k. However, it is hard to obtain the exact

value of Xin through theoretical calculation. Hence, the reactance of integrated antennas

is normally obtained from measurements.








22

2-mm linear or zigzag dipole antennas are used in this work for most of the cases.

Hence the default value of the antenna length for calculation is 2 mm. Figures 2-2 2-4

show the directivity, efficiency and effective area of a 2-mm dipole antenna versus fre-

quency in free space, A1N and 20 Q-cm silicon with direction 0 = respectively. When
2'

the frequency is high, all three parameters vary periodically with frequency. At certain fre-

3.5
Free space
3 AIN
20 0-cm Si
2.5 -
25


o A


Figure 2-2.


Frequency (GHz)

Directivity vs. frequency for a 2-mm antenna pair in free space, A1N
and 20 Q-cm Si


free space
AIN
20 Q-cm Si


Figure 2-3.


Frequency (GHz)
Radiation efficiency vs. frequency for a 2-mm antenna in free space,
AIN and 20 Q-cm Si


M
1











- free space
E AIN
S20 Q-cm Si


Frequency (GHz)

Figure 2-4. Effective area vs. frequency for a 2-mm antenna in free space, AIN
and 20 Q-cm Si



freespace/AIN/Si


Pt


TX


Pr

RX


Figure 2-5. A dipole antenna pair in a uniform medium

quencies, antenna directivity and effective area become zero. This occurs when the

antenna length is 2nX, where n is an integer. Clearly, operation near these frequencies must

be avoided. At low frequencies, both the directivity and efficiency increase with frequency

while the effective area decreases. These two opposing tendencies result in an optimal







24

operating frequency for a given antenna length. This phenomena will be discussed in

detail in the next section.

2.2.2 Performance of Dipole Antenna Pair in Uniform Medium

For a dipole antenna pair in a uniform medium (air/AlN/Si), as shown in figure

2-5, the power transmission gain must be calculated, which is the ratio of the power

picked up by receiving antenna and the power delivered to transmitting antenna. When the

antenna pair is in free space or A1N, using the Friis transmission formula, the received

power delivered to the receiver is

CDtPt tDPt 1 Dr t rDtDr p t
2- 2
P =S A -A p t r P t A =(2.20)
rec r r r 2 r 4 2 r 47, 2 2
41R 41 lT (47) R


Hence, the power transmission gain is

a t r9 t2 r
eP t (47)2 (2.21)
a Pt (47)2 1


) is defined in Eq. 2.15. R is the distance between transmitting and receiving

antennas.

For an antenna pair in silicon, there will be an attenuation factor in the power

transmission gain expression.
P 2 -2tR
Srec trr
G (2.22)
a Pt (473)2 R2



Figure 2-6 shows the power gain versus frequency for a 2-mm antenna pair in free

space, A1N and 20 Q-cm silicon (Figure 2-5). In this work, the default values of distance

between a linear antenna pair and operating frequency are 5 mm and 24 GHz respectively,








25


-10
free space
-20 E AIN
S- 20 Q-cm Si
-30

-40
(D
3 -50
0
-60

-70

-80
0 100 200 300 400 500 600
Frequency (GHz)

Figure 2-6. Power gain vs. frequency for a 2-mm antenna pair in free space, AIN
and 20 Q-cm Si

0

-20

-40

S-60

s -80



120 Q





Distance (mm)


Figure 2-7. Power gain vs. distance for a 2-mm antenna pair in different media
-120 + 120 n-cm Si









at 24 GHz


unless stated otherwise. The power transmission gain does not increase monotonically

with frequency. The maximum gain point occurs at an optimal frequency in free space,

AIN and silicon, due to the interaction among the frequency dependencies of antenna

effective area, directivity and efficiency. The optimal frequency decreases when the
50 n-cm Si
-140 C l-OO n-cm Si
o-o 1000 n-cm Si
-160
4 8 12 16 20 24
Distance (mm)

Figure 2-7. Power gain vs. distance for a 2-mm antenna pair in different media
at 24 GHz


unless stated otherwise. The power transmission gain does not increase monotonically

with frequency. The maximum gain point occurs at an optimal frequency in free space,

A1N and silicon, due to the interaction among the frequency dependencies of antenna

effective area, directivity and efficiency. The optimal frequency decreases when the








26

dielectric constant increases (Figure 2-6). At frequencies when antenna length 1 = 2nk,

the transmission power gains become zero because directivity becomes zero.

Figure 2-7 compares the transmission gains for the same antenna pair at 24 GHz in

free space, A1N and Si with resistivity of 10, 20, 50, 100 and 1000 Q-cm. With the

increase of resistivity, the power gain is increased. When resistivity is decreased, power

transmission gain decreases more rapidly with the antenna separation. At a 20-mm separa-

tion which is sufficiently large to cover the largest chip size projected in ITRS for wireless

clock distribution, increasing resistivity from 10 to 20 increases gain by -50 dB, 20 to 100

increases by 40 dB, and 100 to 1000 increases by another 10 dB. When the resistivity

is 1000 Q-cm, the power gain is almost the same as that in A1N and free space. These sug-

gest that increasing resistivity even to 100-Q-cm can significantly improve the antenna

power transmission gain.

Figure 2-8 shows the performance of antennas with varying lengths (0.25, 0.5, 1,

and 2mm) in 20-Q-cm Si. As the antenna length is decreased, the bandwidth of the

antenna gain increases. It is possible to achieve a relatively flat gain over many 10's of

0

-50

-10 \0

S-150

o -200
A-A 2mm dipole
n 1mm dipole
-250 o-o .5mm dipoe
+-+ 0 25mm dip le
-300
0 50 100 150 200 250 300 350 400
Frequency (GHz)

Figure 2-8. Power gain vs. frequency in 20 Q-cm Si for different antenna length















-DL
Q ~000 E2-cm

.= -35 -^ 0_~_ _-m


a -45 -


-55

20 40 60 80 100 120 140 160 180 200
Frequency (GHz)

Figure 2-9. Peak power gain vs. corresponding frequency in Si with different
resistivity

GHz. For each antenna length, there is a given frequency where the peak gain can be

achieved. However, this peak gain is not necessarily the global peak gain point for a given

frequency. For instance at 80 GHz, the gain for the 0.25-mm long antenna pair peaks, but

clearly, it is possible to get larger gains using longer antenna pairs.

The peak transmission power gain is plotted versus corresponding frequency in

Figures 2-9. As the peak gain frequency is increased, the peak gain decreases and to com-

pensate for this, resistivity must be increased.

Figure 2-10 shows power gain versus antenna length at 20 and 100 GHz. The opti-

mal antenna lengths for 20 and 100 GHz are shown on the plots, which go up when the

frequency is reduced. At 20 GHz, the gain changes by only 5 dB from antenna length of

2 mm to the optimal antenna length of 5 mm. This suggests that the antenna length can be

made smaller but with degradation in gain. Figure 2-11 shows the optimal antenna length

versus corresponding frequency in free space, A1N and silicon with different resistivity.








28


0
-20
-40
E -60
c -80
I -100
~-120
-140
-1 20 GHz, 21 Q-cm
-160 20 GHz, 1 0 Q-cm
,100 GHz, DOQ-cm
-180- _100 GHz, 1 0 Q-cm
-200
-200 1 2 4 5 6 7 8 9 10

Antenna length (mm)

Figure 2-10. Power gain vs. antenna length at 20 and 100 GHz in 20 Q-cm and
100 Q-cm Si


20 5

E E \ 10 n-cm
E 15 e- Freespace E 20 -cm
-a AIN 50 \-cm
) \ r1000 Q-cm
D 10 3
j -j

E E 2
a-
0 0
o 2



20 40 60 80 100 120 140 160 180 200 20 40 60 80 100120 140 160 180 200
Frequency (GHz) Frequency (GHz)


Figure 2-11. Optimal antenna length vs. corresponding frequency in freespace,
A1N and Si


While the peak power transmission gain strongly depends on substrate resistivity, the cor-

responding optimal antenna length is weakly dependent on it. On the other hand, the opti-

mal length is strongly depends on the relative permittivity. At 100 GHz, the optimal

antenna length is around 1 mm, which is large. Fortunately, the gain decreases by only 8

dB at 100 GHz when the antenna length is reduced to 250 atm from the optimal antenna











-15
-20
-25
-o
-30
( -35
-4CT
0- Al


10 100 1000
Resistance (0-cm)


Figure 2-12. Power gain vs. resistivity of silicon, at optimal antenna length


length of 1 mm (Figure 2-10). The antenna length of 250 |tm is sufficiently small to use

them quite freely on-chip. These also suggest that antenna characteristics such as imped-

ance can be changed with relative small changes in the antenna gain. Figure 2-12 shows

the power gain versus substrate resistance at 20 and 100 GHz, when the antenna length is

optimal, and 0.5 x and 0.25 x the optimal length.

Figures 2-13 and 2-14 show the radiation patterns when the antenna length is opti-

mal and 0.5 x the optimal length for varying substrate resistivity, at 20 and 100 GHz. The

radiation patterns are independent of substrate resistivity and become more directed at the

optimal antenna length, though the patterns are similar. These also imply that in area-con-

strained applications, it is preferable to use sub-optimal antenna lengths. Extrapolating to

200 GHz, it should be possible to achieve the minimum acceptable gains (- -60 dB) with

an antenna length of- 100 |tm and an area of 3000 |jm2, which is much less than the area

of a bond pad.











90
1


270

Figure 2-13. Radiation pattern at the optimal antenna length at 20 GHz and 100
GHz


90
1


150,


270


Figure 2-14. Radiation pattern at 0.5 x the optimal antenna length at 20 GHz and
100 GHz


2.3 Summary

The power transmission gain between an external antenna and integrated antennas

is the key parameter in an inter-chip wireless clock distribution system. The power gain is







31

determined mainly by the performance of integrated antennas. In this chapter, a method to

evaluate the performance of arbitrary-length dipole antennas directivityy, radiation effi-

ciency and effective area) in a uniform medium such as free space, A1N and silicon at high

frequency is described. This work examines how the performance and length of integrated

dipole antennas will evolve as the operating frequency of the interconnects is increased.

Though this work is more directly applicable to intra-chip clock distribution, however the

conclusions should also be applicable to the design of on-chip antennas for inter-chip

clock distribution systems. Matlab simulations show that there is an optimal antenna

length at a given operating frequency, and that the optimal antenna length decreases with

increase of frequency. At a given frequency, the optimal antenna length is dependent on

the dielectric constant of the substrate, but weakly dependent on substrate resistivity.

However, the peak power transmission gain is strongly dependent on substrate resistivity.

Increasing the substrate resistivity from 20 to 100-Q-cm improves the antenna power

transmission gain by -40dB, which is significant. At 100 GHz, the optimal antenna length

is around 1 mm. However, it is possible to reduce the antenna length to 250[tm with -8dB

reduction on the power transmission gain. The radiation patterns at optimal antenna length

and 0.5 x the optimal antenna length are also presented in this chapter.

When the operating frequency is high enough so that the wavelength is compara-

ble to the antenna length, the radiation pattern of dipole antennas will change. The power

density in 0 = may not be the highest. This must be avoided in the inter-chip clock dis-
2
tribution system. However, this more complex radiation pattern could be utilized in an

intra-chip clock distribution system at very high operating frequencies.















CHAPTER 3
INTER-CHIP WIRELESS INTERCONNECTION SYSTEM

3.1 Overview

An inter-chip wireless clock distribution system [099, Kim98, KimOOb, Bom02,

Li03] shown in Figure 3-1 has been proposed in order to increase the area and the number

of circuits synchronized by a single clock. In such a system, a global clock signal at

24GHz is transmitted through an external antenna. On-chip receivers with an integrated

antenna pick up the signal, amplify it and divide it down by 8 to provide the local clock

signal. To study the feasibility of implementing such a system, a setup for measuring

power amplitude and phase distributions from an off-chip gaussian optics lens horn

antenna (GOA) has been reported [Bom02]. The factors in the measurement setup which

can introduce errors must be better understood and eliminated. The gain amplitude and

phase distributions of received signal from an external antenna are critical in determining

the synchronization area and skew of the inter-chip clock distribution system.

Transmitting Integrated
Antenna Circuits


Zs '



Heatsink Receiving
Antenna

Figure 3-1. Clock distribution using an off-chip antenna







33

To investigate the integrated antenna performance in the system, different antenna

structures with different lengths on different types of substrates are evaluated. Further-

more, a clock receiver fabricated in a 0.18[tm CMOS process is used to receive the clock

signal from an external antenna. The measurement results are compared with those for an

intra-chip wireless clock distribution system [Li03].

Since the power dissipation of microprocessors could be over 100 W, thermal

management is critical and a heatsink usually made with Aluminum is placed on the back-

side of a chip. However, in this arrangement, the heatsink shields integrated antennas from

the electro-magnetic wave transmitted from an off-chip antenna. A technique to incorpo-

rate a heatsink in the system is also discussed in this chapter [Li04]. This work also inves-

tigates the approach to make the system compact.

This chapter includes 6 sections including this overview section. Section 3.2 intro-

duces the measurement setup used to evaluate the inter-chip wireless interconnection sys-

tem. The factors in the setup that affect the power transmission gain measurements are

discussed. Section 3.3 presents the characteristics of antennas shorter than 1 mm fabri-

cated on commonly used 0.01-20 Q-cm silicon substrates. In addition, clock reception

between a receiver with an integrated zigzag antenna [FloOlb, Flo02] and the off-chip

antenna is demonstrated. Section 3.4 introduces a heatsink which can be used in an

inter-chip clock distribution system. The effects of fins on a commercially available heat-

sink and apertures formed in a heatsink on wave propagation are evaluated. Wireless con-

nection between an external antenna and integrated antennas in the presence of a heatsink

is demonstrated. Section 3.5 presents a clock distribution system using an off-chip pla-







34

nar-array antenna, which essentially has the same form factor as commercial microproces-

sors. Last, this chapter is summarized in section 3.6.

3.2 Measurement Setup Improvement

3.2.1 Measurement Setup and Its Shortcomings

To evaluate the feasibility of an inter-chip wireless clock distribution system, the

power transmission gain between receiving antennas and an off-chip transmitting antenna

has been measured. For a wireless interconnection system, the antenna pair forms a two

port network. The power transmission gain between the transmitting and receiving anten-

nas can be defined as

S21
G = 21 (3.1)
1 S11 2(1 s222)


where S21, S11 and S22 are the S parameters of the two port network [KimOOa, Guo02].

The S-parameter measurement setup is shown in Figure 3-2, which includes an HP 8510C

network analyzer, a balun, semi-rigid cables, signal-signal probe, and a chamber contain-

ing an off-chip antenna. The same kinds of balun and semi-rigid cables discussed in

Semi-Rigid
Cables


Figure 3-2. Measurement setup










semi-rigid cables



A A -3dB B
Balun o Connected to SS probe
Z= -3dB C


Figure 3-3. Balun and semi-rigid cables

[KimOOa] are used to change the differential signal to single-side signal. It has been shown

that the balun can be used even with load impedance other than 50 Q [KimOOa]. Several

pairs of semi-rigid cables are bent to a shape that can be used to connect the signal-signal

probe and the balun (Figure 3-3). To reduce the gain and phase mismatch among Path AC

and Path AB, the gain and phase difference between the two paths (Figure 3-3) for differ-

ent pairs of semi-rigid cables are measured. The pairs with less than 1-dB gain mismatch

and 5-degree phase mismatch over the measurement frequency range (23-25 GHz) are

used for the following measurements.

The S-S probe has ground shields near the probe tips. As a matter of fact, the probe

tips can also radiate or receive electro-magnetic waves. The error due to probe tips can be

de-embedded in the measurement [KimOOa]. The probe tips can also be used as receiving

antennas in the system to pick up the clock signal from the off-chip antenna. This is partic-

ularly useful for generating amplitude and phase distribution.

Figure 3-4 shows the antenna test chamber with an off-chip 3.8-cm diameter gaus-

sian optic lens horn antenna [Bom02]. A vacuum ring supports the wafer and the radiation

from the antenna illuminates the bottom surface of the wafer (Figure 3-4). The separation

between the transmitting antenna and wafer can be adjusted. The multi-reflection effects











Wafer
Inner wall
Cover Opening of opening
chamber
cover


Separation A A Thin 1cm.
=7.5 Inch absorber

se \ opening
screws






Figure 3-4. Antenna test chamber with absorber liners

inside the chamber cause resonances in the measurements. To reduce the multi-path effect,

the inner walls of the chamber are lined with 10-mm-thick absorbers [Bom02]. Measure-

ments show that the reflections of the inner wall of the opening in the chamber cover can

also produce dips in the gain versus frequency plots. Therefore, the inner wall of the open-

ing is also covered with 4-mm-thick absorbers.

In order to characterize the off-chip antennas, two chamber covers were fabricated.

One has a 2-inch-diameter opening and the other has a 4-inch-diameter opening. The gain

amplitude and phase distributions in these two openings will be compared.

3.2.2 System Calibration

The 3.5-mm two-port calibration is carried out before each measurement. The ref-

erence planes are the inputs to the balun and waveguide assembly. The power transmission

gain G obtained from the S-parameters using Eq. 3.1 is actually the power gain between









Z- 50
S Z- (3.2)
11 ZL+ 50

300.0
3--resistance of 2mm zigzag under 3.5mm cali.
reactancece of 2mm zigzag under 3.5mm cali.
9-resistance of 2mm zigzag under oneport cali.
200.0 I-reactance of 2mm zigzag under oneport cali.


0 100.0


0.0


-100.0 ..-- _*
23.0 23.5 24.0 24.5 25.0
Frequency (GHz)

Figure 3-5. Measured impedance of 2-mm zigzag dipole

the A port of the balun and input port of the off-chip antenna. Because of the power loss

in the balun, semi-rigid cables and S-S probe, the true power transmission gain between

the off-chip antenna and on-chip receiving antennas is -4dB higher than G In addition,

S11 which is determined by the impedance (Eq. 3.2) of on-chip antennas is significantly

affected by balun, semi-rigid cables and S-S probe. Figure 3-5 shows the measured imped-

ance of a 2-mm zigzag dipole antenna using 3.5mm two-port calibration and using

one-port on-chip calibration. The difference shows the effects of the balun, semi-rigid

cables and probe. These effects can be de-embedded by manual calculation. Balun,

semi-rigid cables and S-S probe form a two-port network. With one-port 3.5mm calibra-

tion, the S-parameters of this two-port network can be obtained by measuring the S51







38


semi-rigid cables




S11 Balun a Load



Figure 3-6. Two-port network composed of balun, semi-rigid cables and probe



2-mm zigzag dipole Before

2-mm zigzag dipole

I -8dBcircle



0.5-mm zigzag dipole 1-mm zigzag dipole
1-mm zigzag dipole

(a) S 1 before and after de-embedding (b) Measured S11

Figure 3-7. Comparison of measured S11 and calculated S11

with varying loads (short, open and 50Q) (Figure 3-6). This two port network is connected

in series with the antenna pair. Using Matlab, the S-parameters of antenna pair can be

extracted by de-embedding the S-parameters of balun, semi-rigid cables and probe from

the total S-parameters. Figure 3-7 shows the S11 before and after de-embedding (Figure

3-7, (a)), and measured S11 with one-port on-chip calibration (Figure 3-7, (b)). The

de-embedded S11 still oscillates with frequency (Figure 3-7), but the radius of oscilla-

tions are greatly reduced. The S11 after de-embedding are located at almost the same

places with the measured S11 with one-port on-chip calibration.







39

Despite this, G still can be used as a relative measure to characterize system per-

formance, since there is constant difference of 4dB between G and the true power

transmission gain between antenna pair. This difference will be the same in all the mea-

surements. In addition, even the S11 before de-embedding are inside the -8dB reflection

coefficient circle on the Smith chart (Figure 3-7), which are sufficiently small. Therefore,

manual calculation to de-embed the effects ofbalun, semi-rigid cables and probe, which is

inconvenient, are not used in the following work.

3.3 Measurement Results

3.3.1 Characteristics of Receiving Antennas

In order to evaluate the characteristics of wireless interconnection between inte-

grated antennas and an off-chip antenna, a test chip containing 2-mm, 1-mm and 0.5-mm

zigzag dipoles, folded dipoles and linear dipoles, and a loop antenna (Figure 3-8) was fab-

ricated using a single metal process on 0.01 and 20-Q-cm silicon substrates, and on a sap-

phire wafer.

Figure 3-9 compares the power transmission gains for the different antenna struc-

tures on a 20-Q-cm silicon wafer with a 7.5-inch separation between the wafer and

Loop antenna Zigzag dipole
Folded Dipole








Linear Dipole


Figure 3-8. Layout of the test chip











-40.0



m-45.0:



-50.0



-55.0


Frequency (GHz)


Figure 3-9. Antenna gain on a 20-Q-cm substrate.


-30.0


Figure 3-10. Zigzag dipole antenna gain as a function of the separation between a
wafer and an off-chip antenna.

off-chip antenna. The measured frequency range is between 23 and 25 GHz. The 2-mm

folded dipole and zigzag dipole have -3 dB higher gain than the 2-mm linear dipole, -5

dB higher than the 1-mm linear and zigzag dipole and -8 dB higher than the loop antenna







41

at 24 GHz. Since the zigzag dipole has comparable gain and occupies less area than the

folded dipole, the 2-mm zigzag dipole is mostly used for this work.

The gain plots of a 2-mm zigzag dipole on a 20-Q-cm wafer for the separations of

7.5, 6, 4.5 and 3 inches are shown in Figure 3-10. The gain at 24 GHz increases by -7 dB

-30.0
-30.0 zigzag dipole, 7.5 inches separation


-40.0


-50.0 o-oSapphire substrate
r m-Eo20-Q-cm substrate
30 o--0.01-Q-cm substrate
-60.0


-70.0 _
23.0 23.5 24.0 24.5 25.0
Frequency (GHz)

Figure 3-11. Zigzag dipole gain performance on different substrates.


-34.0


-36.0 20-Q-cm substrate


-38.0 -


-40.0 -e 2-mm zigzag dipole


-42.0
3.0 4.0 5.0 6.0 7.0 8.0
Separation (inch)

Figure 3-12. Average gain (24 to 24.2 GHz) vs. separation for 2-mm zigzag
dipole antenna.










-30.0
7.5 inches separation

-40.0-


-50.0 -
So-o 1-mm zigzag dipole
6a 2-mm zigzag dipole
-60.0


-70.0 1,,
0.01 20.0 itinfiiy
Resistivity (Q-cm)

Figure 3-13. Average gain (24 to 24.2 GHz) vs. substrate resistivity for zigzag
dipole antennas.

as the separation is decreased from 7.5 to 3 inches, which is consistent with the Friis for-

mula.

The EM wave undergoes attenuation in Si wafer. Therefore, use of high resistivity

substrates should be able to reduce the attenuation and improve the power gain. Figure

3-11 shows the power transmission gain of the 2-mm zigzag dipole on three different sub-

strates when the separation is 7.5 inches. At 24 GHz, the gain increases by 22 dB and 6 dB

when the substrate is changed from a 0.01-Q-cm to a 20-Q-cm silicon wafer, and from a

20-Q-cm silicon wafer to a sapphire substrate, respectively.

Figures 3-12 and 3-13 show the average power transmission gain of the 2-mm zig-

zag dipole antennas for different substrates and separations in the frequency range of 24 to

24.2 GHz. It clearly shows that the power transmission gain increases monotonically with

the resistivity of the substrate. However, the gain difference of 6 dB between the anten-

nas on the 20-Q-cm and sapphire substrates indicates that integration of antennas with










-30.0
G-e20-6-cm thick wafer
--a20-Q-cm thin wafer
---0.01 -Q-cm thick wafer
-40.0 A--O.01-Q-cm thin wafer


-50.0


-60.0


-70.0
23.0 23.5 24.0 24.5 25.0
Frequency (GHz)
Figure 3-14. Inter-chip antenna pair gain for varying substrate resistivity and
thickness.

good performance on moderate resistivity substrates typically used for IC processing is

possible.

Instead of using high-resistivity-substrates, thinning the wafer should also be able

to reduce the attenuation in Si and improve the power transmission gain. Figure 3-14

shows Ga between an off-chip horn antenna and 1-mm zigzag dipoles on thick and thin

substrates with varying resistivities. The separation between the wafer and off-chip

antenna is 7.5 inch. The antenna pair gain with an 1-mm zigzag dipole on 20-Q-cm silicon

substrates improves by only 1-2 dB when the wafer is thinned from 0.67mm to 0.lmm.

However, for the 1-mm dipole on 0.01-Q-cm substrates, the power gain increases by

-10dB when the wafer is thinned. This is expected since the EM wave is attenuated more

significantly traveling through a 0.01-Q-cm silicon substrate. This suggests that inter-chip

wireless clock distribution should be possible even for circuits fabricated on high-conduc-

tivity substrates.

















BEEN V I(a)






















Figure 3-15. Across a 2-inch-diameter opening with a 7.5-inch separation (a) rel-
ative gain (dB) distribution, (b) phase (degree) distribution

3.3.2 Gain and Phase Distributions from External Antenna

To measure the relative gain amplitude and phase distributions at 24GHz, instead

of using a test chip with a grid of zigzag dipole antennas [Bom02], a signal-signal probe

was used as receiving antenna to map the gain and phase distributions from the off-chip

antenna. This avoids the variations due to the receiving antennas. Figure 3-15 shows the

spatial distributions of relative gain amplitude and phase between the off-chip antenna and

S-S probe measured in a 2-inch diameter opening. The off-chip antenna is 7.5 inches away
















(a)








...U E E.. .(b)













Figure 3-16. Across a 4-inch-diameter opening with a 7.5-inch separation (a) rel-
ative gain (dB) distribution, (b) phase (degree) distribution

from the wafer. The gains range between -53 and -70 dB, and phases range between -2830

and -2870 degrees over a circular area with a diameter of 3cm. Increasing the opening

diameter to 4 inches reduces the gains range to 5 dB (-58 to -63 dB), and phase range to

60 degrees (-3290 and -3350 degrees) over a circular area with a diameter of 4cm (Figure

3-16). The phase variations would translate to clock skew of 1.4% and 2% of a period for

2-inch and 4-inch openings (Eq. 3.3) when the signal is divided down to 3 GHz by a clock

receiver [099],[Flo01b]. The gain and phase are affected by the proximity to opening. The







46

gain variations also introduce skew. In the measured area, gain distribution in the 2-inch

opening is symmetric and predictable. The gain variation could be compensated by adjust-

ing the gain of LNAs in different clock receivers. In addition, receiver simulations indicate

that 10-dB gain variation induces skew less than 1.0% of a period [Yan04]. Therefore, the

total skew due to the gain and phase variations should be less than 3% of a period for both

cases, which is significantly less than the typical skew/jitter tolerance of 10% of a period.

SPhasex Phase J 33
Skew =-ax ~83 60 0 (3.3)



3.3.3 Wireless Interconnection between Receiver and External Antenna

To demonstrate that the system is compatible with a conventional CMOS process,

a clock receiver fabricated for 15-GHz intra-chip wireless interconnection [FloOlb, Flo02]






separation
N =3 7.5 inches


o


Figure 3-17. A block diagram of a 0.18-[tm clock receiver with a zigzag dipole
antenna.











S20.0

1 10.0

S0.0






"2 --3external antenna, d=7.5 inches
4 -0 -external antenna, d=3 inches
S-0.0
S 13.0 14.0 15.0 16.0 17.0 18.0
o Transmitted Frequency (GHz)
a.

Figure 3-18. Sensitivity vs. frequency plots for different separation between the
receiver and off-chip transmitting antenna.

on a 20-m-cm substrate utilizing a 0.18-ttm CMOS process is used to receive the clock

signal from an off-chip antenna [Li03]. Figure 3-17 shows the measurement setup and the

block diagram of clock receiver. A 14-16GHz signal is generated by a synthesizer and

transferred to an external transmitting antenna through a waveguide. The receiver picks up

the signal, amplifies it, and divides it down by 8. The receiver opuput can be shown on an

oscilloscope or a spectrum analyzer. Figure 3-18 shows the sensitivity of the receiver with

the external antenna 3 and 7.5 inches away from the receiver. The sensitivity is defined as

the minimum power needed at the transmitting antenna for the receiver to be locked to the

clock at a given frequency. This plot shows excellent system operation with the -10 dBm

(100 |tW) or less at the transmitting antenna between 15 16.3 GHz.

Compared to this, the intra-chip clock signal distribution requires transmitted

power of more than 15 dBm to keep the receiver locked [Guo02]. This along with the







48

short dipole measurements suggests that the antenna size can be reduced to 1 mm or less at

15 GHz by increasing the transmitter power to 1 mW. If the operating frequency were to

be increased and the receiver is tuned to 24 GHz, the antenna size can be further reduced.

Finally, the excellent system performance at 7.5-inch separation suggests that the inte-

grated antennas could be used for general purpose wireless communication over a larger

distance.

3.4 Heatsink Incorporation

3.4.1 Heatsink Evaluation

To evaluate the impact of presence of a heatsink, a commercially available heat-

sink shown in Figure 3-19 was cut to a shape that could be used in the measurement setup

[Li04]. The fins are 30 mm long and separated by 1.5 mm. The base-plate thickness is 6

mm. In addition, seven rectangular apertures with the same height of 1.5 mm and different

widths were opened in the heatsink to allow wave propagation through the heatsink (Fig-

Fan


Fins


Base-plate


Figure 3-19. Generic heatsink and modified heatsink








Table 3-1 Cut-off frequencies
Width of apertures f10o
7mm 21.43GHz
8mm 18.75GHz
9mm 16.67GHz
12mm 12.5GHz


X


S


Fin %


, ins


tt t4


0# '- *
Ib
1%.a a



41+6mm


tt t4

a~


Figure 3-20. Waveguide models
ure 3-19). The fins form a parallel plate wave guide (Figure 3-20). TEM wave which is
similar to an unbounded plane wave could exist between the parallel plates. TEM wave
could have any frequency or wavelength and it propagates at the speed of light in vacuum.
The rectangular apertures also act as rectangular wave guides (Figure 3-20). The mini-
mum cut-off frequencies in the apertures, which are the TElo mode wave frequencies, are
dependent on the aperture width, a (Eq. 3.4). The minimum cut-off frequencies in the
seven apertures are shown in Table 3-1. In order for the cut-off frequency to be less than










10 2c
fclO 2a


(0 c
p, TE0 kg i (j 2.5 (35)





Wafer Heatsink Inner wall
Cover Opening of Opening




Separation A Thin 1mm
=7.5 Inch absorber







Figure 3-21. Generic heatsink and modified heatsink

24 GHz, the width must be greater than 6.25 mm. The phase velocity of TElo mode wave

(Eq. 3.5) is also dependent on the width. Hence, the width variations affect the phases of

signals picked up by the receiving antenna. As an example, for a 24-GHz signal transmit-

ted through a 6-mm-thick waveguide, +/- 0.25 mm variation of the widths causes clock

skew of- 0.2% of a period when divided down to 3 GHz, which is small. The TElo mode

wave has no E-field component in the direction of aperture width. This means antennas

must be placed in parallel to the shorter edges (height) of apertures (Figure 3-20).


(3.4)










3.4.2 Measurement Results With Heatsink

Figure 3-21 shows the measurement setup with a heatsink inserted between the

off-chip antenna and the wafer. Fins on the heatsink are put inside the opening of the

chamber cover.

Figure 3-22 compares the power transmission gains (Eq. 3.1) between the external

antenna and a 1-mm zigzag dipole antenna, when the wave goes through a 9-mm width

-40.0
Sseparation=7.5 inch
-45.0

a-50.0

-55.0 -
o-e Through the heatsink with fins
M- Through the heatsink without fins No -
-60.0 No heatsink 1mm

-65.0
23.0 23.5 24.0 24.5 25.0
Frequency (GHz)

Figure 3-22. Gain vs. frequency under different situations


E 2-mm zigzag 0.2-mm zigzag
1-mm zigzag Pad
-30.0 -- 0.5-mm zigzag x-x Substrate
0.4-mm zigzag 1-mm zigzag, parallel
0.3-mm zigzag with loa edge


S-50.0!



(D70.0 separation=7.5 inoh r \




-90.0
23.0 23.5 24.0 24.5 25.0
Frequency (GHz)

Figure 3-23. Gain vs. frequency for different antennas







52

aperture in heatsinks with and without fins to when there is no heatsink. The off-chip

antenna is 7.5 inches away from the wafer surface. It shows that the gain through a heat-

sink with/without fins is -1-5dB higher than the case without a heatsink. The presence of

apertures and fins in a heatsink can actually improve gain by guiding the wave. This

experiment demonstrated that a heatsink could be incorporated in a system using wireless

clock distribution without degrading the gain.

Figure 3-23 shows the power transmission gains of various antenna structures

through the 9-mm width aperture (Figure 3-20) in the heatsink with fins. The gains of the

1-mm zigzag dipole antenna are 8 dB worse than that of the 2-mm zigzag antenna. The

0.2-mm, 0.3-mm, 0.4-mm and 0.5-mm zigzag dipole antennas have similar gains which

are only ~3dB worse than that of the 1-mm antenna, ~2dB higher than that of a pair of

bond pads, and another 5dB higher than the case when the probe was directly landed on

the oxide layer on a substrate.

Even for a pair of bond pads, with transmitted power of 20 dBm, the received

power will be ~ -30 dBm which should be sufficient for system operation [Guo02]. This

indicates that the receiving antenna size could be extremely small for clock distribution

systems using an external antenna. When the antenna length is reduced to 0.2 mm and

below, it should be possible to reduce the height of the aperture to ~ 0.3 mm and below.

The bottom plot in Figure 3-23 is for a 1-mm zigzag dipole oriented in parallel with the

longer aperture edge. The gain was severely reduced, which is consistent with the fact that

there should not be E-field along this edge.

Figure 3-24 shows the relative power gain and S21 phase distributions of a 1-mm

zigzag dipole antenna in apertures with varying widths at 23.25 GHz. Higher gains and














-50.0



c -60.0

(C a-0 through 7 mm apert
( / through 8 mm apertu (A)
S-70.0 <- through 8 mm aperture E(B)
-70.0 through 8 mm apertur (C)
7a / through 8 mm aperture (D)
Q V---V through 8 mm aperture (D)
-- through 9 mm aperture
-80.0 n through 12 mm aperture
-6.0 -4.0 -2.0 0.0 2.0 4.0 6.0
Location in the aperture (mm)


-20.0

S-60.0

-100.0-

U-140.0 -
-4- through 7 mm apertur
3 / -- -E] through 8 mm aperture (A)
( -180.0 / -- through 8 mm aperture (B)-
~ through 8 mm aperture (C)
S-220.0 V- through 8 mm aperture (D)
S-- through 9 mm aperture
-260.0 -- through 12 mm aperture
-6.0 -4.0 -2.0 0.0 2.0 4.0 6.0
Location in the aperture (mm)

Figure 3-24. Gain and phase vs. location in each aperture at 23.25 GHz

larger phase delays are measured in larger apertures. The gain distributions are symmetric

and the highest gain occurs in the center. These indicate that using apertures of the same

size is preferable to reduce gain amplitude and phase variations thus skew. Figure 3-24

also suggests that more than one antennas could be placed in one aperture with acceptable

gain and phase variations. Among the four 8-mm apertures, power gain and phase vary







54

due to the diffraction from adjacent apertures and output power variation of the transmit-

ting antenna. This indicates that apertures should be distributed with a regular pattern.


I-,
r
CO

0



,(D
L-O
a)












Cn




rF


-40
-42
-44
-46
-48
-50
-52"
-54
-56
0


-760

-780

-800

-820

-840

-860

-880


1 2 3 4 5 6
Aperture Row Number


o-eApertures in Column A
- 3-Apertures in Column B
0-Apertures in Column C




01 2 4 6


0 1 2 3 4 5 6 7
Aperture Row Number

Figure 3-25. Relative gain and phase at center of each apertures at 24GHz







55

To evaluate the effect of heatsink on gain and phase distributions, a new heatsink

in which rectangular apertures of the same size (7mm x 1.5mm) are distributed evenly is

fabricated (Figure 3-25). Again, a signal-signal probe was used as the receiving antenna to

measure the relative gain and phase in the center of each aperture. Figure 3-25 shows the

relative gain and phase when the S-S probe was placed in the center of the apertures. The

relative gain varies from -50dB to -55dB, and the relative phase varies from -795 degree to

-865 degree. The variation is almost the same as the case without a heatsink. This indi-

cates that the area that can be synchronized will not change even when a heatsink is put

into the system. Figure 3-25 also shows that the middle column apertures have higher

gains and lower phase delays, which are consistent with the case without a heatsink.

A concern for having apertures in a heatsink is the potential for generation of hot

spots. A preliminary simulation study suggests that the temperature inside a 5 mm x 1.5

mm aperture of a 12 mm x 12 mm chip is -2 degree higher after 60 seconds. This differ-

ence should decrease, if the aperture height is reduced from 1.5 mm to 0.3 mm. Further

studies of thermal issues are needed. Potential solutions to cope with the hot spots are

under study.

3.5 A Compact Inter-chip Clock Distribution System

To make the inter-chip clock distribution system compact, a system with a

low-profile planar array antenna (Model: PLA24-2, Dorado Intl. Co.) is proposed (Figure

3-26), which should have almost the same form factor as commercial microprocessors

used in desktops. The planar array antenna operates in a frequency range of 24-24.25GHz

with an antenna gain of 21dBi. In this setup, more than one chips can be placed on top of










IC with







Antnn Anjenn

Front View Low-profile Side View
Antenna

Figure 3-26. Proposed inter-chip clock distribution system



Wafer Heatsink Inner wall
Vacuum Ring of aperture





planar-array absorber
antenna




Figure 3-27. Antenna test chamber

the heatsink and synchronized at the same time. A fan could be installed on one side of the

heatsink (Figure 3-26).

The same measurement setup (Figure 3-2) and antenna test chamber (Figure 3-27)

are used to evaluate the planar-array antenna. Relative gain amplitude and phase distribu-

tions were measured in the same way as before for the cases with and without a heatsink.

Again, a signal-signal probe was used as the receiving antenna. Figure 3-28 shows the rel-















Sm (a)

MmmIMmEm




















Figure 3-28. Across a 4-inch-diameter opening with a planar array antenna (a)
relative gain (dB) distribution, (b) phase (degree) distribution

ative gain amplitude and phase distributions measured in a 4-inch diameter opening at

24GHz. The heatsink is not included in the system.

The gains range between -54dB to -61dB, and phases range between -591 degree

to -658 degree over a circular area with a diameter of 35mm. When the signal is divided

down to 3 GHz, the phase variation will translate to a clock skew of 2.3% of a period (Eq.

3.3). Figure 3-29 shows the relative gain amplitude and phase at the center of each rectan-

gular apertures in the second heatsink when the planar array antenna is used as the trans-










-36-
e-eApertures in Column A
-40- --Apertures in Column B
*-Apertures in Column C

m -44
co -484 -
(3

-52 -

-56
0 1 2 3 4 5 6
Aperture Row Number


-440
-460 G-Apertures in Column A
"- --mApertures in Column B
S-480 .-Apertures in Column C
-4

0 -500 -

S-520 -

.> -540-

S-560

-580
Aperture Row Number

Figure 3-29. Relative gain and phase at center of each apertures at 24GHz

mitting antenna. Phases range between -500 to -560 degree, which translates to a clock

skew of 2% in a period when the signal is divided down to 3GHz (Eq. 3.3). The maximum

gain variation is -10 dB. The total clock skew due to both the gain and phase variations is

~ 3% of a period at 3 GHz, which is similar to the case when a Gaussian optics lens horn

antenna is used. This indicates that the low-profile inter-chip clock distribution system is

feasible.









3.6 Summary

In this chapter, the characteristics of antennas for inter-chip wireless clock distri-

bution system are described. The relative gain amplitude and phase distributions in 2-inch

and 4-inch diameter openings with an off-chip antenna 7.5 inches away from the wafer

have been measured. It is shown that a 3-GHz clock signal over a 4-cm-diameter circular

area with skew due to path mismatches less than 3% of a period can be provided by a

24-GHz wave incident from an off-chip gaussian optics lens horn antenna. A clock

receiver fabricated in a 0.18-[tm CMOS process is used to receive a 15-GHz clock signal

from an external antenna. The measurements show that the system using an external

antenna has 20-30 dB more margin over the intra-chip wireless clock distribution system

[Guo02]. This indicates that 0.5-mm or even shorter receiving antennas can be used in

inter-chip clock distribution systems.

Using fins and rectangular apertures in a heatsink as waveguides, wireless inter-

connection in the presence of a commercially available heatsink with the off-chip antenna

over distances of 7.5-inches and less is demonstrated. Use of a heatsink improves power

transmission gain by guiding the EM waves. The measured results also show that the heat-

sink with regularly distributed apertures does not change the gain and phase distributions.

Based on this, an inter-chip wireless clock distribution system using a planar array antenna

was proposed and characterized. This system essentially has the same form factor as com-

mercial microprocessors. The measured results show the feasibility of a low-profile

inter-chip clock distribution system.















CHAPTER 4
CMOS CLOCK TRANSMITTER

4.1 Overview

In an inter-chip wireless clock distribution system, the clock transmitter plays an

important role. It generates the 24-GHz global clock signal and delivers it to an external

antenna. To make the system feasible, the power level of the transmitted clock signal must

be sufficient to be locked by the clock receivers. In addition, to test the clock receiver

locking, the clock signal should be able to be tuned over a large frequency range. When

receivers lock onto the transmitted global clock signal, the global clock signal jitter will

translate into the local clock signal jitter. Therefore, the global clock signal should also

have small jitter or phase noise.

In the system, the local clock signals at different receivers should be synchronized

onto one unique global clock signal and in phase. However, when the system is powered

up, the frequency dividers in different receivers start up with random phases. This causes

skew. To eliminate this problem, a technique to start up all the receivers in a synchronized

state is proposed [Yan04]. The transmitter will generate a global clock signal with a

no-signal-transmission period. The clock receivers should be able to recognize this no-sig-

nal-transmission period and generate pulses to initialize and simultaneously start up all the

8:1 dividers.

Two clock transmitters implementing this system are designed and fabricated in a

UMC 0.13[tm logic CMOS process. They share the same circuit topology. The power sup-







61

ply voltage of the transmitters is 1.2V. To stream line the task, an LC VCO without a PLL

is fabricated. The frequency of VCO is directly controlled by a bias voltage. An LC VCO

can achieve lower phase noise and higher oscillating frequencies than ring oscillators. A

symmetrical negative resistance structure is used in the VCO to lower power consump-

tion. An on-chip Class-AB power amplifier is used to increase the power level of output

clock signal. The clock frequency of the first clock transmitter is designed to be 24GHz.

Due to the improper modeling of the metal-to-metal parasitic capacitance of MOS varac-

tors, the clock frequency is shifted down to 17GHz. To correct this problem and to make

the operating frequency better suited for the 0.13[tm process, a second 20-GHz clock

transmitter is designed and tested.

This chapter is composed of 6 sections including this overview section. The sec-

ond section introduces the initialization and start-up methodology of the inter-chip clock

distribution system [Yan04]. Section 4.3 presents the design and implementation of the

clock transmitters, including the VCO, power amplifier, 512:1 frequency divider and

no-signal-transmission period generation scheme. Section 4.4 shows the measurement

setup and measured results of the 17-GHz clock transmitter. Both the on-chip measure-

ment results and on-board measurement results are presented. The problems associated

with the 17-GHz clock transmitter are also discussed. Section 4.5 presents the design and

measured results of the 20GHz clock transmitter. Finally, conclusions are presented in sec-

tion 4.6.

4.2 Initialization and Start-up Scheme

The receiver initialization and start-up scheme used in the inter-chip wireless clock

distribution system is shown in Figure 4-1. The transmitter generates the 24-GHz global







62

clock signal with a no-signal-transmission period and delivers it to an external transmit-

ting antenna. The clock receiver includes a detector and an 8:1 frequency divider. The sig-

nal picked up by the receiving antenna is simultaneously fed into the clock divider and

detector. The detector recognizes the transition from the signal-transmission period to the

no-signal-transmission period and generates one pulse initializationn pulse). This pulse is

used to stop and initialize the 8:1 frequency divider. Then the detector generates a second

pulse (start-up pulse) using the transition from the no-signal-transmission to the sig-

nal-transmission period. The divider is kept in the initialization state until the start-up

pulse is received. After the start-up pulse, the divider is placed into the divide mode and is

started by the first clock transition from low to high (Figure 4.1). The transition delay time

from the initialization mode to the divide mode is defined as latency. If the latency time is

not zero and varies in different receivers, the variation will translate to clock skew. A tech-

nique is incorporated to eliminate the latency in the receiver [Yan04]. In addition, to make

the system feasible, the 8:1 frequency divider and detector must have small input ampli-

tude and temperature sensitivity. Furthermore, they should have a maximum operating fre-

----- ------ r --------------- -


starting point
VCO Buffe PAivier --
/buffer -
I LI_ IEnvelope
S1 2 Detector INI
Divider
TX RX
L.----... L -________________


Figure 4-1. Initialization and start-up scheme






63
quency up to 24GHz. The design and measurement of divider and start-up circuits have

been discussed in detail in another research dissertation [Yan04].

To improve testability, a clock signal with periodic no-signal-transmission periods

is generated by the clock transmitter. As shown in Figure 4-1, the 24-GHz clock signal

generated by the VCO is divided down by 512 to create a low-frequency control signal.

This signal controls the output of transmitter to generate the periodic no-signal-transmis-

sion periods. The design and measured performance of clock transmitter that satisfy the

proposed system requirements are discussed in the following sections.

4.3 Transmitter Design

The block diagram of clock transmitter is shown in Figure 4-2. An on-chip VCO

generates a 24-GHz clock signal and delivers it to the power amplifier (PA) and divider.

To improve the flexibility for testing, an option to disable the VCO and input an external

clock signal from a synthesizer through four GSSG pads at node A has been incorporated.

Furthermore, the VCO and its single-stage buffer can be separately characterized using the

same four pads at node A, with the other parts of the transmitter circuit disabled. The

i buffer PA on-chip
on.chipVCO I^_N d antenna
VCO buffer A ,B, ..



synthesizer 512:1 divider
Suffer Go to oscilloscope
as triggering


Figure 4-2. Clock transmitter block diagram







64

24-GHz clock signal is divided down by 512 to generate a digital clock signal. A logic cir-

cuit with a delay modulates the duty cycle of the digital clock signal to generate periodic

low-voltage state with duration of 1.2ns (Figure 4-2). This control signal is used to control

the PA to output the 1.2-ns no-signal-transmission periods in the transmitted clock signal.

There are two options on the output side. The output clock signal from PA can be deliv-

ered to an on-chip zigzag transmitting antenna, which can be used for intra-chip clock dis-

tribution [Flo02]. The antenna of the transmitter can be diced off, and the transmitter can

be placed on a PC board and connected to an external antenna using SMA connectors. The

control signal is taken out through an output pad (Figure 4-2), and used to trigger an oscil-

loscope.

The transmitter is fabricated using the UMC 0.13-[tm logic CMOS process. Figure

4-3 shows the die photograph of the clock transmitter with a 2-mm zigzag antenna. The

2mm



















780tm

Figure 4-3. Die photograph of clock transmitter







65

chip area without the zigzag antenna is 0.78x0.78 mm2, while the active area is 0.55x0.4

mm2.

4.3.1 Voltage-Controlled Oscillator

As discussed, a voltage-controlled oscillator is used to generate the clock signal.

The VCO must have low phase noise to decrease the local clock signal jitter. Figure 4-4

shows the circuit schematic of the VCO. A symmetrical negative resistance structure is

utilized. For LC-VCO's, the overall Q of LC-tank is the key factor that determines the

phase noise performance [HunOO]. Normally, the Q factor of overall LC-tank is deter-

mined by the inductor. A differential spiral inductor with a polysilicon patterned-ground

shield (PGS) is used in the VCO. The value of the inductor is chosen to be 400pH, with a

Q-factor of 15 at 24-GHz. The varactors are chosen to be 50fF, and implemented with

high-Q MOS capacitors [HunOO]. The measured Q factor of the MOS varactors are 30 at

24GHz. When the VCO is oscillating at 000, the equation GmRe(ZTANK) = 1 has to be

satisfied, where G is the effective transconductance and ZTANK is the impedance of





Buffer Buffer
r r- iy'
I I 4
I Vtune
I I I I
I I 'I I


SI I I I


Figure 4-4. Circuit schematic of VCO and buffer







66

LC-tank. Therefore, a larger L or a smaller C/L ratio in an LC VCO requires a smaller G

and reduces the power consumption [HunOO]. In addition, the current-reuse topology (Fig-

ure 4-4) increases the total effective Gm, which reduces the current consumption. The sizes

of cross-coupled PMOS and NMOS transistors in the VCO are 24[tm/120nm and 12[tm/

120nm, respectively. The VCO current consumption is -2mA.

Close-in phase noise is a concern for CMOS VCO's because of the high 1/f noise

of MOS transistors. Most of the close-in noise is from the up conversion of the 1/f noise of

the tail transistor. Since 1/f noise is inversely proportional with the gate area, a PMOS

with large width and length (160[tm/240nm) is used as the tail transistor to reduce the

close-in phase noise [Yan04]. Furthermore, compared to NMOS, PMOS transistors have

lower thermal noise and 1/f noise. Hence, use of PMOS tail transistor can also improve the

phase noise performance at larger offsets from the carrier [Yan04].

According to the LTI phase noise theory, the symmetrical negative resistance VCO

structure can minimize the up-conversion of the 1/f noise, thus reduce the close-in phase

noise. In addition, this structure will allow larger output signal swings at a given bias cur-

rent level, which also improves the power efficiency of the VCO at given phase noise per-

formance [LeeOO].

The VCO buffer is shown in Figure 4-4, which is an inductively-loaded com-

mon-source amplifier. The gate capacitances of the buffer NMOS transistors (20[tm/

120nm) are included into the LC-tank design.

4.3.2 512:1 Divider and Logic Circuits

Figure 4-5 shows the block diagram of the 512:1 frequency divider employing

source-coupled logic circuits (SCL). The SCL divider achieves higher maximum operat-






67
ing frequency and better noise performance compared to TSPC dividers [War89, Flo00,
FloOla]. The 512:1 divider is constructed by 9 cascaded SCL dividers. A 2:1 SCL divider
can operate in one of two modes. The first one is the latched mode, which occurs when the
input signal swing is large. In the latched mode, the divider utilizes its latching property.
The second is injection locked mode, which occurs when the input signal swing is small


i>-


Figure 4-5. Block diagram of 512:1 frequency divider







68

and its fundamental or one of the harmonics is close to the frequencies of harmonics for

self-oscillation of SCL divider. All the 9 stages of the SCL divider operate in the latched

mode, because the input voltage swing of each stage of the SCL divider is large.

The performance of first stage SCL divider limits the maximum operating fre-

quency of the 512:1 divider. Table 4-1 shows the channel widths of the devices in the first

4 divider stages. The channel length of all the devices are 120nm. To increase the maxi-

mum operating frequency, the gates of the PMOS transistors M7,8,9,10 are grounded to

operate them in the linear region. This reduces the RC time constants at nodes Q, Qb, Qi

and Qbi. Simulations show that the maximum operating frequency of the 512:1 divider is

-30GHz. The current consumption of divider is -7mA.

The block diagram of the control-signal-generation circuit following the 512:1

divider is shown in Figure 4-6. The output of the divider has a 50% duty cycle. For

receiver initialization and start-up, a no-signal-transmission period of -l-ns is required in

the transmitted global clock signal. Therefore, the control signal should have periodic

low-voltage state with -Ins duration. A 1.2-ns delay circuit and a NAND logic are used to

modulate the duty cycle to meet this requirement (Figure 4-6).


Table 4-1 Transistors sizing for the first 4 stages SCL divider

First Stage Second Stage Third Stage Fourth Stage

M7, M8, M9, Mo1 2.6[tm/ 1.4[tm/ lItm/ 0.9[tm/
120nm 120nm 120nm 120nm
M3, M4, M13, M14 5tm/ 3.Otm/ 1.9[tm/ 1.9[tm/
120nm 120nm 120nm 120nm
M5, M6, M15, M16 1.6[tm/ 1.4Ltm/ 1.7Ltm/ 1.7Ltm/
120nm 120nm 120nm 120nm
MI, M2, M11, M12 8[tm/ 2.5tm/ 1.55tm/ 1.55tm/
120nm 120nm 120nm 120nm










Control


Output
of VCO
Sm


Clk1 I- L

Clk2
Control


Figure 4-6. A block diagram of control-signal-generation circuit



Control
M M4
~ I 7Vout- Vout+
Vin+ M5 Vin-



L-n-- -- ---- ----J
Vin- M2 M, -LFGM- 'V in+
Tr Power Amplifier T


Figure 4-7. Circuit schematic of generating no-signal-transmission period

4.3.3 No-Signal-Transmission Period Generation Scheme

Figure 4-7 shows the scheme to generate the no-signal-transmission period using

the control signal. Vin+ and Vin- are the output signals from the VCO buffer. They have

the same amplitudes and 1800 phase difference. The five PMOS transistors M1-M5 are

controlled by the control signal Vontro1. When Vontro1 is high, the five PMOS transistors

are off; and the clock signal will go through to the output stage (PA) and be delivered to

the transmitting antenna. When Vcontro is low, the five PMOS transistors are turned on. At

nodes A and B, the two clock signals with 1800 phase difference will cancel each other. In


Clkl














7Wrn 1 U l i t


--1




Im I
12.30n 12-5in 12-,n 13.1an 1n-n



Figure 4-8. Simulated output clock signal and control signal

addition, three PMOS transistors M3, M4 and M5 at output nodes will short the output to

AC ground. Therefore, a no-signal-transmission period is generated when the control sig-

nal is low. In order to reduce the rippling time during the transition between signal-trans-

mission to no-signal-transmission states, the Q of the output network of PA must be small.

The Q is chosen to be 1. Figure 4-8 shows the simulated waveforms of the output clock

signal and the control signal. A 1.2-ns no-signal-transmission period is successfully gener-

ated. The second edge of the no-signal-transmission period which determines the receiver

start-up is also shown in Figure 4-8.

4.3.4 Power Amplifier (PA)

Figure 4-9 shows the circuit schematic of the power amplifier (PA). The gate bias

of the active devices MI, M2 is connected to 1.2V which is well above the threshold volt-

age. Hence the PA works as a class A amplifier. L1, C1 constructs the output matching net-

work. Due to the large size of transistors M1, M2, Ccouping may not be sufficiently large

compared to the gate capacitance of M1, M2. To reduce the voltage drop across Ccouping,













1 L, L1
C1 C1


M in+ Vin M2
Load M Load

Scoupling

Figure 4-9. Circuit schematic of output power amplifier


20 -: (vr(-vs lt-") V("rz' to'+ )










13.75n 1Wa7Pn l1M, n 13.87n 1.9ln 13-5n


Figure 4-10. The simulated differential output waveform from PA

Lg is used to tune out the gate capacitance. The gate DC bias of M, M2 are also provided

through Lg.

In an inter-chip wireless clock distribution system, when the receiver sensitivity is

-40dBm [FloOla, Flo02], with -40dB antenna pair power transmission gain, the minimum

transmitted power level should be OdBm. In the system, the transmitter has to be placed on

a PC board and connected to an external antenna through a balun. Therefore, the load on

each side of output is 500. The power amplifier is tuned with a 500 load. The maximum

output power is designed to be -9dBm (the voltage amplitude on each load is 0.6V).








72

Hence the current swing in the NMOS transistors is at least 24mA. To support this large

current swing, the NMOS transistor sizes are chosen to be 60tlm/120nm.

Figure 4-10 shows the simulated differential output waveform of the PA. The

waveform is almost sinusoidal.

4.4 Measured Results of Transmitter

4.4.1 VCO

The output spectrum and single-sideband phase noise of the VCO including its sin-

gle stage buffer are obtained using a spectrum analyzer. Figure 4-11 shows the output

spectrum and phase noise of the VCO. The oscillating frequency is 17.2GHz, with an out-

put power level of-13.2dBm. The VCO core consumes 2mA currents from a 1.4V power

supply. At 1-MHz and 3-MHz offsets, the phase noise are -106dBc/Hz and -116dBc/Hz,

respectively, which are excellent. The VCO oscillating frequency has shifted down by

7GHz from the designed value of 24GHz because of the improper modeling of the



-60 __ __ 17.2GHz -13.2dBm
dBc/Hz


-80


-100 -106dB_ .
dBc1Hz 16


-120 3 Hz I tk,
dBclHz r




100KHz 1MHz 10MHz
OFFSET

Figure 4-11. Output phase noise and spectrum of VCO










17.6



N 17.4
I


o 17.2

Vdd=1.4V
Ic=2mA
LL 17.0( c


16.8
0.0 0.4 0.8 1.2 1.6 2.0
Control Voltage (Volt)

Figure 4-12. VCO tuning range

metal-to-metal parasitic capacitance of MOS varactors [Cao05a]. The parasitic capaci-

tance of metal connections to the varactor increases the capacitance by a factor of 2. Fig-

ure 4-12 shows the VCO tuning range, which is -600MHz. The narrow tuning range is

also due to the large metal-to-metal parasitic capacitance of MOS varactors.

4.4.2 Transmitter Output Signal

With the 2-mm zigzag antenna diced off, the transmitter is measured on chip. An

Agilent 86100B Oscilloscope is used to characterize the transmitter. Figure 4-13 shows

the block diagram of the measurement setup. The low frequency control signal is used as

the triggering signal of the oscilloscope and is also connected to the channel 2 of scope.

The output signal from PA is shown on channel 1. A GSSG probe, semi-rigid cables and a























Figure 4-13. Measurement setup of the transmitter

balun change the differential output signal to a single-side signal. As mentioned before,

the source of clock signal could be either the on-chip VCO or an external synthesizer. Fig-

ures 4-14 and 4-15 show the waveforms of the control signal and the transmitter output

signal, with the on-chip VCO and an external synthesizer as the clock signal source,

respectively. The periodic no-signal-transmission with 1.2ns duration are successfully

generated. The settling time for the transition between no-signal-transmission to sig-

nal-transmission states is 50ps or 1 period. Figure 4-16 shows the transmitter output

spectrum when the VCO is used as the clock signal source. The 17.011GHz clock signal

with a power level of-23.17dBm and the 33.2MHz harmonics due to the periodic no-sig-

nal-transmission periods are shown. The output power level is low, even with the power

loss in probe, semi-rigid cables, balun and cables de-embedded. This issue will be dis-

cussed shortly. The measurements showed that the 512:1 divider works up to 24GHz, pro-

vided that the divider Vdd is increased to 2.2V

In an inter-chip wireless clock distribution system, the transmitter has to be placed

on a PC board and connected to an external antenna. Therefore, the performance of the

transmitter on board has to be evaluated. A three-layer PC board for the transmitter is






















........ ......... ....... ....... ...... ...... ....... .. . .
..* *" ..... .. .


... .. I -, , l, ... .

I-. I "


S . .. .. .. .. .


Figure 4-14. Waveforms of control signal and clock signal (synthesizer as the
clock source)


t. _


I


I
I


/


Figure 4-15. Waveforms of control signal and clock signal (VCO as the clock source)


designed and fabricated using Protel DXP. The size of the transmitter board is 30 x


30mm2. Figure 4-17 shows the transmitter board with a transmitter chip mounted in the


center. The measurement setup is the same as before except that an external PA is used to


increase the output power level (Figure 4-17). Figure 4-18 shows the waveforms of con-


trol signal and transmitter output signal with the VCO as the clock signal source. Like the


. . .. .


-3 ,*, '
- ,EJ:; i *- .i
I ia. ,..-*.'
: r'


''





~~b.~



' ' '






76
on-chip measurements, periodic no-signal-transmission with 1.2ns duration is observed in
the transmitter output waveform.


Figure 4-16. Transmitter output spectrum


30mm


oscilloscop(

otri *C2
L4oC


Figure 4-17. The measurement setup of using a transmitter on a PC-board










77


0.1 0.1


0.050.05



o o0

-0.05 -0.05


-0.1 -0.1
0.0 100 20.0 30.0 40.0 50.0 0.0 1.0 2.0 3.0 4.0 5.c
t (ns) t (ns)

Figure 4-18. Waveforms of control signal and clock signal (Transmitter on board)


S I r_-| .. 111,1h : H.-II .




i

.....1 9. -
"rwrI I ,
JPm l | '-,,, ,.




Figure 4-19. RMS jitter of the output clock signal

The transmitted clock signal jitter is one of the key parameters in the inter-chip

clock distribution system which determines the quality of the local clock signals. Figure

4-19 shows the RMS jitter of the transmitter output signal, which is 2.4ps. This is the total

jitter including the triggering signal jitter and the 1.2ps (1.5ps maximum) instrument char-

acteristic RMS jitter of the oscilloscope. When the triggering signal jitter and instrument

characteristic jitter are de-embedded, the RMS jitter of the transmitter output signal is

between 0.42ps (best case) and 1.47ps (worst case), which is small.









4.4.3 Output Power

As mentioned earlier, the transmitter output power level is low. With a synthesizer

as the clock signal source, the transmitter output power versus clock frequency is mea-

sured and shown in Figure 4-20. The power loss in signal paths are de-embedded. It shows

that the output power decreases rapidly from -3dBm at 26 GHz to -15dBm at 16 GHz. A

possible reason for the rapid drop of output power could be a higher Q factor at output

node of the PA than expected. Figure 4-21 shows the output matching of the PA, which

indicates that the output matching is broadband and the output Q is low. Therefore, there

must be some other nodes in the transmitter with a high Q-factor. Review of the transmit-

ter circuitry shows that the Q-factor at node B is too high (Figure 4-2). It can account for

the rapid drop of output power as the frequency is decreased. In addition, the resonant fre-

quency at node B was mistuned which further reduces the output power level. Fortunately,

in an inter-chip clock distribution system, an external PA can be used to increase the


5.0 .



E 0.0
m


I -5.0 -
0
a.


-10.0


-15.0


Frequency (GHz)


Figure 4-20. Output power vs. clock frequency










-6.0


mo
S-10.0
Co


Frequency (GHz)

Figure 4-21. Power amplifier output matching

power lever of the clock signal delivered to the external antenna. Therefore, this transmit-

ter can still be used for the system demonstration.

The input DC bias of the power amplifier is connected to Vdd, instead of having a

separate pin. As a result, the current consumption in the PA is above 80mA, which is

unnecessarily high. In the second version of the transmitter, as will be discussed, this

problem has been corrected by adding a separate pin for the bias of PA.

4.5 A 20-GHz Clock Transmitter

To correct the deficiencies mentioned above, a new clock transmitter is designed

and fabricated, using the UMC 0.13[tm logic CMOS process. Because the maximum oper-

ating frequency of the clock receiver is around 20GHz, the new clock transmitter is tuned

at -20GHz. The same circuit topology is used to construct the transmitter. Figure 4-22

shows the die photograph of the new clock transmitter with a 2-mm zigzag antenna. The

chip area is the same as the 17-GHz clock transmitter.










2mm









%If-----------^
Tie n u

Tri


i0 780pm
VD V

Bia d
trl
VCOi n in n


780tm

Figure 4-22. Die photograph of the 20-GHz clock transmitter


4.5.1 VCO with Newly Designed Varactors

The same circuit schematic is used to design the 20-GHz VCO (Figure 4-4). To

avoid the frequency shift, a new varactor is designed to reduce the metal-to-metal parasitic

capacitance, while keeping the Q-factor high [Cao05a]. Figure 4-23 shows the layout of

the new varactor. Minimum gate length is used to reduce the series resistance and achieve

high Q-factor at the expense of reduced tuning range. For MOS varactors used in an

LC-VCO, because the bottom plate (n-diffusion/n-well) is AC ground, the parasitic capac-

itance between the metal connected to the diffusion and ground is not a problem. There-

fore, metal 2 is used to connect the n-diffusions. Metal 8 is used to connect the gates, and

the areas of metals 1-7 are very small, which significantly reduce the parasitic capacitance

between metal connected to gates and the metal connected to n-diffusion and ground. In
















.4m
E m

CD0






Metal2


Figure 4-23. Layout of the newly designed MOS varactor

addition, the metal spacings are made larger to further reduce the parasitic capacitance.

The Q-factor is -30 at 24GHz, the same as before, and Cmax/Cmin ratio is -1.75.

The 20-GHz VCO is measured using a spectrum analyzer. Figure 4-24 shows the

output spectrum and single-sideband phase noise of the VCO. The oscillating frequency is

20.11GHz, which is almost the same as the design target (20GHz). The VCO core con-

sumes 2mA current from a 1.5V power supply. At 1-MHz and 3-MHz offsets, the phase

noise are -106dBc/Hz and -116dBc/Hz, respectively, which is the same as before. Consid-

ering the 20GHz oscillating frequency which is 3GHz higher, the phase noise performance

is actually improved. Figure 4-25 shows the tuning range of the 20-GHz VCO. The tuning

range is increased to -3GHz, which is much larger than -600MHz of the first version.













0u dB/ SOT FRQ .,
RL -50 dBc/Hz





L I cI
"11"f ld,, 6 3c/Hz


FREQUENCY
FROM 1766


OFFSET
GHz CARRIER


Figure 4-24. Output phase noise and spectrum of the 20-GHz VCO


24.0

N

23.0




22.0
4--
0)

I 21.0

O.

20.0
0.0 0.5 1.0 1.5 2.0
Vtune (V)

Figure 4-25. Tuning range of the 20-GHz VCO


4.5.2 Reduction of Q-Factor at Intermediate Node


In the first version of clock transmitter, the Q-factor at node-B is very high (Figure


4-2). Because of this, a small shift of resonant frequency at node-B due to the improperly


modeled parasitics will lead to a rapid drop of the output power. The Q-factor at node-B is


I


I


-- -


- inn n















500pH 200Q
Q=15
at 20GHz



Figure 4-26. 500-pH spiral inductor with a 200-Q parallel resistor

mainly determined by the inductor in the buffer (Figure 4-2). To reduce the inductor Q, a

200-Q resistor is connected in parallel with the 500-pH inductor with Q-factor of 15 at

20GHz, as shown in Figure 4-26. The resistor reduces the tank Q to 2.6, while not affect-

ing the voltage headroom.

4.5.3 Power Amplifier Redesign

Figure 4-27 shows the updated circuit structure of the power amplifier, where a

separate pin is used to provide the DC bias of the input. The PA is tuned at 20GHz. By

changing the DC bias voltage, the power amplifier can be made to work as a class A or a

Vbias Vbias
II Vcontrol H I,
M M4
-L ,-yo v utr-- V-t+-g 4L --


Vin- M I 1| AL M2 Vin+
VT o / Power Amplifier Vcontrol
Control I cnr



Figure 4-27. Output stage of clock transmitter, including PA and no-signal-trans-
mission generation circuits







84

class B amplifier, with different output power level and drain efficiency. When Vbias is

well above the threshold voltage, the PA is a class A amplifier. The output power is higher

with lower drain efficiency. When Vbias is near the threshold voltage, the PA is a class B

amplifier, with higher drain efficiency but lower output power.

At high frequencies, the common-source PA could be unstable because of the feed-

back through Cgd [Cao05b]. The small-signal model of the output stage is shown in Figure

4-28. Cgd forms a voltage-current (shunt-shunt) feedback between the input and output

nodes. The loop gain of this circuit is







For oscillation to start, the phase change of loop gain T(co) must be 360 degrees,

with the magnitude of T(co) larger than 1. To meet the phase change requirement, the first

part of Eq. 4.1 must give a phase change of 180 degrees, i.e, the resonant frequency of the

tank at drain node is near the oscillation frequency. Another 180-degree phase change



I I
T~s}= -g Z\\Z + --- *--- g--- 4









I I
I I
Cgd
I I
Z 9 r--



I I
I I ,
I I

L----- ---


Figure 4-28. Simplified small-signal model of the common-source PA







85

comes from the second part of Eq. 4, which requires high Q of network Z at an oscilla-
g
tion frequency below 1/ L, C or oL >> R L and R
Sg,equ gd g,equ g, equ g, equ g, equ
are the equivalent inductance and series resistance of network Z [Cao05b]. In this
g
design, to ensure the stability of the system, the Q-factor at the gate node is set low. As a

matter of fact, o)L is smaller than R at the resonant frequency (20GHz) of the tank
g, equ g
at drain node.

4.5.4 Measured Results

The same measurement setup shown in Figure 4-13 is used to characterize the

20-GHz clock transmitter. Figure 4-29 shows the output waveform when the clock trans-

mitter is measured on chip. It shows that almost a perfect periodic no-signal-transmission

duration of 1-ns is generated. The settling time during the no-signal-transmission to sig-

nal-transmission states is 50ps or 1 period. The total current consumption of the clock

transmitter is -50mA from a 1.5V power supply.

The transmitter chip is mounted on the same transmitter board as before (Figure

4-17). The transmitter board is measured using the measurement setup shown in Figure


o 1U0. 2U U.U 4.U0 5.0U 0.0 0.5 1.0 1.5
F 4ns9 t (ns)

Figure 4-29. Output clock waveform of the 20-GHz clock transmitter (on-chip)












60


40


20


0.0


-20


-40


0.0 1.0 2.0 3.0 4.0 5.0
t(ns)

Figure 4-30. Output clock waveform of the 20-GHz clock transmitter (on-board)

4-17. Figure 4-30 shows the waveform of the transmitter output signal with the VCO as

the clock signal source. One external PA is used here to increase the power level. Once

again, the no-signal-transmission period is successfully generated. Figure 4-31 shows the

RMS jitter of the transmitter output signal. The 1.70ps RMS jitter contains the triggering

signal jitter and the 1.2-ps instrument-characteristic RMS jitter. When the triggering signal

jitter and instrument-characteristic jitter are de-embedded, the transmitted clock signal

RMS jitter is between 0. Ips (best case) and 0.87ps (worst case), which is much better than

the first version clock transmitter.