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INVESTIGATION OF THEORETICAL LIMITATIONS OF RECOMBINATION DCIV METHODOLOGY FOR CHARACTERIZATION OF MOS TRANSISTORS By ZUHUI CHEN A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2005 Copyright 2005 by Zuhui Chen ACKNOWLEDGMENTS I am deeply indebted to Professor ChihTang Sah for his invaluable guidance, patience and teaching throughout my graduate study at the University of Florida. I would also like to thank Professors Kevin Jones, Sheng S. Li, Toshikazu Nishida, Scott Thompson and Bin Jie for serving on my Ph.D. supervisory committee. Special thanks go to Professors Xiuhua Lin and Binxi Jiang who led me into the field of solidstate physics when I was a graduate student at Xiamen University in China. I am grateful to the Chinese Church at Gainesville for giving my family much help before and after our baby Aden Chen was born on Jan., 27. 2005. Finally, I would like to thank my wife, Li Wu, for her love, support and encouragement, and our parents, Shuisheng Chen, Mudi Zeng, Huaxing Wu and Lijuan Huang, for their continuous support throughout my graduate education. TABLE OF CONTENTS page A C K N O W L E D G M E N T S .................................................................... ......... .............. iii L IST O F FIG U R E S .... ...................................................... .. ....... ............... vi ABSTRACT .............. .................. .......... .............. ix CHAPTER 1 INTRODUCTION ............... .................................. ................... 1 2 THEORETICAL CONFIDENT LEVEL OF BI APPROXIMATION COMPARED WITH THE EXACT FD SOLUTIONS .............................................5 2 .1 Intro du action ............................................................................................... .... 5 2.2 Configurations of the RDCIV method ............... ......................................8 2.3 Theory of R D CIV M ethodology .................................. .................................... 13 2.4 Theoretical Computations for Confident Level............................... ..................23 2.4.1 BI, BD and FI Approximations Compared with FD Exact Theory............29 2.4.2 Dopant Impurity Concentration Dependence...........................................34 2.4.3 Oxide Thickness Dependence ........................................... ............... 41 2.4.4 Injected Minority Carrier Concentration Dependence ..............................47 2.4.5 Energy Position of Discrete Energy Level Interface Traps........................53 2.4.6 Tem perature D ependence ................................ ................................... 59 2.5 Sum m ary ............................................................... ... .... ......... 65 3 RDCIV LINESHAPES FROM DISTRIBUTED ENERGY LEVELS OF INTERFACE TRAPS IN SILICON GAP............................................................... 66 3.1 Introduction ................ ...... ......... ..... ... ........... ........... .................. .....66 3.2 Effect of ratio of electron and hole capture rates at midgap trap ........................71 3.3 Effect of Distribution of Interface Trap Energy Level on RDCIV Lineshape....75 3.4 Temperature Dependence ..... ....................... .......................... .............. 97 3.4.1. Temperature Dependence of the Peak Current IBpeak..................... ........ 98 3.4.2. Temperature Dependence of the IBVGB lineshape ..............................107 2.4.3. Temperature Dependence of peak gate voltage VGBpeak .........................113 3.4.4. Reciprocal slope .................................................... ............ 118 3.5 Sum m ary ................................... .......................... ...... ..........120 4 IMPURITY DEIONIZATION ..........................................................................122 4.1 Introduction ...................................................................... ..... 122 4.2 Dopant Impurity Concentration Dependence.....................................................126 4.2 Oxide Thickness D ependence......................................... .......................... 130 4 .4 S u m m ary ...........................................................................................13 4 5 SUMMARY AND CONCLUSIONS ................................................135 APPENDIX ACCURACY OF ITERATIVE ANALYTICAL SOLUTIONS..............40 R E F E R E N C E S ........................................ ............................................................ 15 0 BIOGRAPHICAL SKETCH .............. ............................ .................................. 156 v LIST OF FIGURES Figure pge 2.1 Schematic device cross section of modern nchannel MOS transistor. .................9 2.2 Four DCIV bias configurations for a pMOS transistor: ............................ ........ 12 2.3 Energy band diagram and cross sectional view of a gated n+Si/SiO2/pSi structure in the basewell channel region along x direction. ....................................17 2.4 A transition energy band diagram showing the four fundamental transition processes between a conduction or valence band state and an electron trap state in the silicon energy gap............ ................................................ .... ............. 18 2.5 (a) Comparison of the theoretical RDCIV curves between BI, BD, FI, and FD solutions. (b) Normalized percentage deviation with respect to the exact or real FD theory Temperature T=296.15K. Metal gate MOS transistor...........................33 2.6 Effect of dopant impurity concentration on the DCIV on the normalized IB vs. VGB lineshape. M etal gate nM OS transistors. ................... ............... ......... 37 2.7 Effect of dopant impurity concentration on the DCIV on the normalized IB vs. VGB lineshape. Silicon gate nMOS transistors. .................. ....................... 39 2.8 Effect of oxide thickness on the DCIV on the normalized IB vs. VGB lineshape. M etal gate nM O S transistors ....................................................................... .......43 2.9 Effect of oxide thickness on the DCIV on the normalized IB vs. VGB lineshape. Silicon gate nM O S transistors ....................................................... ..................45 2.10 Effect of injection carrier concentration on the DCIV on the normalized IB vs. VGB lineshape. Metal gate nMOS transistors. .................. ....................... 50 2.11 Effect of injection carrier concentration on the DCIV on the normalized IB vs. VGB lineshape. Silicon gate nM OS transistors. ........................... .................. 52 2.12 Effect of energy position of discrete interface trap energy level on the DCIV on the normalized IB vs. VGB lineshape. Metal gate nMOS transistors....................55 2.13 Effect of energy position of discrete interface trap energy level on the DCIV on the normalized IB vs. VGB lineshape. Silicon gate nMOS transistors .................57 2.14 Effect of temperature on the DCIV on the normalized IB vs. VGB lineshape. Metal gate nMOS transistors ........... ..... ......... .................. 60 2.15 Effect of temperature on the DCIV on the normalized IB vs. VGB lineshape. Silicon gate nM OS transistors ..................................................................... 62 3.1 Energy distribution of Interface traps......................................... ......... ............... 70 3.2 Effect of ratio of electron and holecapture rates on normalized IBVGB lineshape: Interface trap level is at m idgap................................. ............... 73 3.3 Effect of ratio of electron and holecapture rates on normalized IBVGB lineshape. Density of interface traps is Ushaped and the ratio of cps/cns = CPN. .79 3.4 Effect of discrete and asymmetrical interface trap energy distribution on IB V G B lin esh ap e ..................................................... ................ 82 3.5 Effect of two discrete symmetrical interface traps at ETI =+0.05eV on IBVGB lin e sh a p e :................................................................................. ..8 6 3.6 Effect of two discrete and one midgap interface traps on IBVGB lineshape........91 3.7 Comparison for three distribution of density of interface traps in Sigap: a U shaped DOS, a constant DOS and a discrete interface trap energy level at mid g ap E T I= 0 ...................................................... ................ 9 3 3.8 Forward bias VPN dependence of recombination peak current IBpeak for an interface trap with discrete interface energy level.................................................100 3.9 Forward bias VPN dependence of recombination peak current IBpeak for continuous distribution of interface energy level in silicon gap. ...........................101 3.10 Temperature T dependence of recombination peak current IBpeak for .............102 3.11 Forward bias VPN dependence of thermal activation energy EA for an interface trap with discrete interface energy level ........... ........................... .............103 3.12 Temperature T dependence of recombination peak current IBpeak for a discrete interface energy ETI=0, 0.5eV, with NIT=f(ETI) or NITYf(ETI)....................104 3.13 Temperature T dependence of the IBVGB linewidth for interface trap energy level at midgap ETI=O.OeVK............. ...................... ..................... 109 3.14 Temperature T dependence of the IBVGB linewidth for a Ushaped distribution of interface trap energy level in silicon gap. ............ ............. .......................... 111 3.15 effect on peak gate voltage VGBpeak from oxide thickness, impurity concentration, trap level, and temperature .................. ............................... 115 3.16 Reciprocal slope depends on (a) ETI, and (b) Temperature ................................119 4.1 Impurity deionization effect at the SiO2/Si interface in noncompsated range......124 4.2 Impurity deionization effect at the SiO2/Si interface in compsated range. ............124 4.3 Deionization effect of dopant impurity concentration on the DCIV on the normalized IB vs. VGB lineshape.................................................. 128 4.4 Deionization effect of oxide thickness on the DCIV on the normalized IB vs. V G B lineshape.. ......................................................................132 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy INVESTIGATION OF THEORETICAL LIMITATIONS OF RECOMBINATION DCIV METHODOLOGY FOR CHARACTERIZATION OF MOS TRANSISTORS By Zuhui Chen August 2005 Chair: ChihTang Sah Major Department: Electrical and Computer Engineering This dissertation investigates the accuracy of using the recombination direct current current voltage (RDCIV) method to measure the interface traps and spatial variations or profiles of impurities and oxides in silicon MOS transistors. The Boltzmann electronhole distribution and ionized impurity approximations (Boltzmann ionization or BI) are much faster than the FermiDeionizated (FD) model. The accuracy of using the BI approximation to extract the device and material parameters of an MOS transistor is investigated by comparing with the timeconsuming and complicated FD model. The accuracies or confident levels on the extractable device and material parameters are analyzed, such as dopant impurity concentration PAA, oxide thickness Xox, interface trap concentration NIT, injected minority carrier concentration at SiO2/Si interface represented by the p/n junction VPN, energy level of interface traps distribution in silicon gap ETI and temperature T. From RDCIV lineshape analyses, it is shown that the BI approximation gives a small (1%5%) deviation when matching 90% of the experimental DCIV curve ix to theory. These results indicate that the simple and timesaving BI approximations are sufficiently accurate to extract from experimental data the spatial profiles of the dopant impurity concentration, and interface trap concentration at the SiO2/Si interface, and oxide thickness in modem MOS transistors. Effects of energy distribution of the interface traps on the RDCIV lineshape are also investigated. Comparison are made among three density of state (DOS) distributions of interface traps (1) a Ushaped DOS, (2) a constant DOS, and (3) a discrete interface trap energy level at midgap. These comparison shows that the experimental broadened RDCIV lineshapes may also be accounted partially for the spatial variation of surface dopant impurity concentration but also by the energy distribution of interface traps in silicon gap. Slater's perturbation theory is employed to suggest that a Ushaped DOS is the most probable distribution in silicon gap. Thus, the extractions of parameter spatial profiles, from experimental, should use a Ushaped density of interface traps, instead of the commonly assumed trap level at midgap ETI=0 in the silicon energy gap. For both the continuous energy distribution of interface traps and a discrete interface trap energy level at midgap, the peak RDCIV current has large temperature dependence. However, the thermal activation energy, the lineshape, reciprocal slope, and peak gate voltage all have negligible temperature dependence. The analyses of impurity deionization effect show that deionization has a negligible effect on the RDCIV lineshape when using Fermi ionization approximation (FI) to match experimental data from peak current down to 10% of the peak. The errors of FI approximation are nearly identical to the confident level of BI for all device and material parameters in practical range, for both metal gate and silicon gate MOS transistors. CHAPTER 1 INTRODUCTION Today, the metaloxidesemiconductor (MOS) transistor has become the most important building block of ultralargescaleintegrated (ULSI) circuits. The dimension of MOS transistors has narrowed from 25um in 1962 [1] to 90nm in 2002 [2]. The scaling trend, propelled by the rapid advancement of VLSI technology, is expected to continue [3] and the MOS transistor in production may shrink to 50nm in 2012 [4] as projected by the 1999 International Technology Roadmap for Semiconductors (ITRS). The success of today's semiconductor industry can be partially if not dominantly attributed to the extremely low density of electronhole recombination, generation and trapping centers or traps at the SiO2/Si interface (interface traps). Routine manufacturing processes have reduced the interface trap concentration NIT to 1010cm2 by slow cooling after the final high temperature oxidation step and by postoxidation annealing in hydrogen. The traditional smallsignal measurement techniques such as the MOS capacitance voltage method can only resolve interface trap density higher than about 101 cm2 and not its spatial variation and can not detect the very low density manufacturing residual interface traps in the stateofthe art MOS transistors. Recombination Direct Current CurrentVoltage (RDCIV) methodology is a simple and sensitive tool to extract spatial variation or profile of dopant impurity concentration and interface trap concentration profiles and oxide thickness. The high sensitivity is attained by forwardbiasing one or more p/n junctions (VpN) in a MOS transistor to exponentially raise the injected minority carrier concentration, exp(qVpN/kT). In this dissertation, the differences among BI, BD, FI, and FD solutions will be analyzed to determine the accuracy of the BI approximation which is computational the fastest. Here, BI stands for Boltzmann distribution of electrons and holes in energy and impurity full ionization. BD stands for Boltzmann distribution and impurity Deionization. FI stands for Fermi distribution of electrons and holes and impurity full ionization. FD stands for Fermi distribution and impurity deionization. We will evaluate the accuracy of simple and computational timesaving BI approximation solutions by comparison with the exact, complicated and timeconsuming FD theory. One of the novelties is that RDCIV lineshape is very sensitive to the device and material properties but rather insensitive to multidimensional effects inherent in the very small transistors. In chapter 2, the current in the base terminal of the MOS transistor IB, as a function of gate voltage VGB, due to electronhole recombination at the SiO2/Si interface traps in the basewell channel region, is analyzed theoretically using the ShockleyReadHall steady state recombination kinetics which has been applied by us [521]. Families of theoretical IB VGB curves are presented to illustrate their dependencies on the variations of dopant impurity concentration, oxide thickness, injected minority carrier concentration, interface trap energy level and temperature. The percentage deviation as a function of gate voltage and %RMS deviation over a range gate voltage covering the peak current are used to evaluate the accuracy of simple and timesaving BI approximation, by comparing with the exact, complicated and timeconsuming FD theory. According to these accuracy or confidence levels, it is shown that extracted value from experimental data would have only a small error from using BI approximation when matching 90% of the experimental RDCIV curve from peak current IBpeak down to 10% of the peak. The comparison of BI, BD, FI and FD solutions indicates that BI and FI solutions are respectively nearly as good as the BD and FD solutions, and the deionization only has effect on DCIV lineshape in accumulation region for nMOS transistors. This RDCIV lineshape analysis gives a comprehensive baseline that can be used to guide the analysis when extracting the spatial profiles of the impurity concentration, interface trap concentration and oxide thickness from the experimental data. This simple and nondestructive RDCIV methodology provides a powerful capability for routine monitoring and feedback during transistor fabrication. In chapter 3, the effect on RDCIV lineshape of electron and hole capture rates at midgap is analyzed. It shows that the ratio assumption with 0.01 gap has a small effect on the lineshape. Family of curves are computed to illustrate the effects on RDCIV lineshapes from the three distributed energy level of interface traps in silicon gap: (1) a Ushaped DOS, (2) a constant DOS, and (3) a discrete interface trap energy level at midgap. Comparisons among these distributions indicate that the broadened lineshape in experiments can also be accounted for partially by the energy distribution of interface traps in silicon gap, not just the spatial variation of surface dopant impurity concentration. Based on Slater's perturbation theory, we conclude that the most probable density distribution of the interface traps in the silicon energy gap is U Shaped. This is from the random variations of bond length and bond angle of the Si::04. Thus, the theory to extract impurity concentration and interface concentration profiles should be modified from the traditional assumption of interface energy level at midgap ETI=0, to a UShaped density distribution of interface traps throughout the energy silicon gap. The forward bias VPN dependence of peak gate voltage VGBpeak, thermal activation energy EA and peak current peak current IBpeak can provide a determination of the effective interface trap energy level ETI* for discrete interface trap levels. For both discrete and continuous interface trap level, EA, IBpeak, VGBpeak, n, and IBVGB lineshape have negligible temperature dependence, while IBpeak has large temperature dependence. In chapter 4, impurity deionization dependence of dopant concentration and oxide thickness on RDCIV lineshape will be analyzed. The percentage deviation and %RMS deviation of Fermi ionization approximation (FI) show that there is a negligible impurity deionization near the SiO2/Si interface in MOS transistors when matching 90% of experimental data from peak current down to 10% of the peak. We can expect that the errors of FI approximation are nearly identical to the confident level of BI for other device and material parameters in practical range, such as injected minority concentration, interface trap energy level and temperature, for both metal gate and silicon gate MOS transistors. The analyses of impurity deionization confirms that the time saving and simple BI is a good approximation to extract the spatial profiles from experiment data, such as the dopant impurity concentration, interface trap concentration, oxide thickness since it has a good physical basis at around the recombination peak current. Chapter 5 gives the summaries and concludes this dissertation. CHAPTER 2 THEORETICAL CONFIDENT LEVEL OF BI APPROXIMATION COMPARED WITH THE EXACT FD SOLUTIONS 2.1 Introduction RecombinationDCIV (RDCIV) methodology is a reliable and powerful tool for diagnosing interface properties as well as for characterizing transistor design. It is the only method which can extract profiles of the channel impurity concentration and oxide thickness with high resolutions in nanometer dimension range. However, its accuracy has not been evaluated. As we already know, the BI approximation solution is time saving and simple compared with the time consuming and complicated FD solution. There are some possible sources of errors using BI approximation in extracting parameters from experimental RDCIV data such as impurity and interface trap concentration profiles and oxide thickness profiles. In this chapter, we will evaluate these errors and present the confident level of BI approximation by comparing the BI and BD results with those of FD. The principle of RDCIV is the use of a surfacepotentialcontrolling gate terminal voltage, VGB, to modulate the baseterminal DC current, IB, from electronhole recombination at the SiO2/Si interface traps. The lineshape, linewidth, peak gate voltage and peak amplitude of the recombination currents from electronhole recombination at the interface traps in the channel space charge region are analyzed using ShockleyRead Hall steadystate recombination kinetics. The material physics used in this thesis are based on the textbook of Sah [5, 6] and references cited therein, including previous work on RDCIV [721] . Compared with the widely used differential CV profiling method, the RDCIV profiling technique provides several advantages: (1) low sensitivity to gate area variation; (2) no special test structures required to perform the test all production MOS transistors can be used with sufficient sensitivity and resolution; (3) directcurrent (DC) measurements allowing longtime average to reduce noise and increasing sensitivity using simple computercontrolled digital data collection; and (4) the test is nondestructive. Its high sensitivity is derived from forwardbiasing one of the p/n junctions to greatly increase the minority carrier concentration and recombination rate. In MOS transistor structures, it gains further sensitivity from the commonemitter and commonbase current gain of the BJT which is present in all MOS transistor structures. Sah [7, 8] measured the RDCIV characteristics of MOSgated silicon bipolar transistors in 1961 to investigate the effects of surface recombination and channel on p/n junction and transistor characteristics. The RDCIV method was reactivated 35 years later by Neugroschel et al. [9] in 1995 as a sensitive monitor for transistor reliability. They investigated the generation kinetics of the interface traps and the degradation kinetics of electrically stressed transistors from electricalstresscreated oxide and interface traps. In the past several years, many RDCIV applications were reported which included the delineation of interface trap generation/annealing kinetics on electricallystressed transistors by hot carriers and high current densities, and diagnosis and evaluation of transistor design and manufacturing processes on prestress transistors [1025]. In this chapter, the characteristics of the surface electronhole recombination current in the channel region are studied theoretically and the confident levels of Boltzmann Ionized approximation solutions are computed in order to provide a comprehensive baseline that can be used to guide the analyses of experimental data in the applications. These results can help quantify the applications of the simple and time saving BI solutions for the extraction of fundamental and applicationspecific properties of transistors and their materials, such as the physical (spatial location and density) and electronic (quantum density of states) properties of the residual and stressgenerated interface and oxide traps, and the dopant impurity concentration profiles. The formulation includes high injection level in the quasineutral basewell and electrical nonequilibrium from the forward applied p/n junction voltage which gives NP > ni2. Analytical solutions and their physical models are presented to illustrate the effects of material parameters on the IBVGB lineshape, the amplitude of peak current IBpeak, and peak gate voltage VGBpeak at the IBpeak. Families of base current versus gate/base voltage (IBVGB) are computed to illustrate the effects of the bulk impurity concentration and interface trap properties on the lineshape and the (IBpk, VGBpk) location and IB magnitude. The systematic computation begins with the ideal transistor structure in which there is no spatial variation of the basewell impurity concentration and a discrete energy distribution of interface traps is at midgap ETI=0. The simple ideal model can allow us to extrapolate the BI confident levels when extending to include spatial variations of dopant impurity interface trap concentrations, injected minority carrier concentration, and a Ushaped density distribution of interface traps in silicon gap. 2.2 Configurations of the RDCIV method One of the most important DCIV applications is to extract the surface dopant impurity profile at the interface of SiO2/Si. As the transistor dimensions decrease, the conventional optical and traditional electrical methods are increasingly inaccurate to monitor and measure the impurity profiles. The major difficulty lies in having as accurate a measurement to monitor impurity profiles in order to provide the feedback necessary for iterative fabrication processing to attain the optimum impurity profile and transistor characteristics to maintain or improve the highperformance electrical functions of the milliontransistor circuit chips. The discussion in this analytical theory chapter will follow the schematic cross sectional view of modern nchannel MOS transistor shown in Figure 2.1. The important physical features of the nMOS include the ntype heavily doped highconductivity ploysilicon gate (n++G), the refractory metal silicide gate on n++G and the heavily doped veryhighconductivity ntype drain and source extension (n++D and n++S), the medium highly doped highconductivity ntype drain and source extension regions (n+SER and n+DER), the ptype basewell channel region (pBCR), the drain and source oxide spacers, and the shallowtrench oxide isolation. Electronhole recombination can occur at the SiO2/Si interface traps located in the five regions along surface channel: (1) the basewellsurface channel region (BCR), (2) the sourcejunction spacecharge region (SJR), (3) the drainjunction spacecharge region (DJR), (4) source extension region (DER) and (5) drain extension region (DER). This study will focus on basewellsurface channel region and the results are also applicable to the other regions. Source S VsB=OmV .0 to 700mV Gate Drain Basewell G Vrn= 3.5V D Vn= OmV B IB versus VGB IB = BaseLine + IlnterfaceTrap(VGB) IIT(VGB) = ISE + ISJ + IBC + IDJ + IDE Figure 2.1 Schematic device cross section of modern nchannel MOS transistor. It is comprised of a gate dielectric, a doped polysilicon gate electrode and titanium silicide overlayer, frequently called a shunt. (adapted from ChihTang Sah[26]) Only the IB component from recombination at the interface space charge layer at interface traps will vary with VGB since the recombination rate at the interface is controlled by the interface or surface electron and hole concentration which are only modulated or varied by VGB under the gate electrode. Other IB components are from the injected minority carriers (such as electrons), which are from forward biased n++Drain/p Basewell (n+D/pB) or/and n++Source/pBasewell (n+S/pB). These injected minority carriers recombine with majority carriers (such as holes) at the bulktraps in the bulk p basewell and space charge regions of the n+D/pB and n+S/pB junctions, at the bulk traps in the psubstrate and at the interface traps at ohmic contact. These regions are not covered by the gateconductor. Thus, the recombination rate or current don't vary with the gate voltage. It is the IB baseline. Recombination DCIV measurement on MOS transistors can use four different bias configurations to inject minority carriers to the SiO2/Si interface [8, 1517, 26], as illustrated in Figure 2.2. These four configurations can be grouped in accordance with the two traditional BJT geometries, the vertical BJT (VBJT) and lateral BJT (LBJT). For the LBJT, given in Figures 2.2 (a) and (b), they are called the DrainEmitter configuration (DEDCIV) and SourceEmitter configuration (SEDCIV). For the VBJT, given in Figures 2.2 (c) and (d), the drain and source p/n or n/p junctions are simultaneously forward DC biased to the same terminal voltage, which is known as the Top Emitter configuration or TEDCIV. The other VBJT configuration is to forward bias the bottom p/n junction of the p/njunction basewell, which is known as the Bottom Emitter configuration or BEDCIV. The p/n junctions not forward biased are zerobiased, though they can also be reversebiased or even forwardbiased at a lower voltage in each of the bias configurations. These four DCbias configurations can provide high sensitivity and resolution to monitor the dopantimpurity and interface trap concentration profiles and as well as the electrical length of the five regions (SER, SJR, BCR, DJR and DER) and other transistor design parameters, such as the gate/source, gate/base, and gate/drain oxide thickness, and the series drain and source resistances [1517]. All of these are increasingly difficult to measure accurately and with confidence by traditional MOS transistor and metallurgical optical methods as the transistor shrinks due to the fundamental microscopic limitations. Each of the configurations, in Figures 2.2 (a)(d), provides a different and desired BJT injection pathway and spatial distribution of minority at the SiO2/Si interface to help further delineate the spatial distribution of the impurities and interface traps. The boron acceptor has a liquid/solid segregation coefficient of 0.8, which gives only about 20% variation of boronconcentration over the crystal length, while phosphorus donor segregation coefficient is 0.35 and phosphorus sources have very high vapor pressures to make the continuousdopant during growth difficult to control. Thus, all silicon integrated circuits start with a ptype highresistance, 50 to 100 Q cm ptype 8" or 12" diameter silicon wafer for highyield reason since 8" byseveralfoot silicon single crystals can be grown nearly defectfree, dopantimpurityfree and oxygenfree (using floatzone in vacuum chamber). Therefore, only the pMOST in digital circuits manufactured on highresistivity pSi wafers has an nbase/pcollectorsubstrate n/p junction basewell for transistor isolation which can be used in the BEDCIV methodology. The nB/pC (pcollector) junction well is formed by ionimplantation. It is not available for the digital nMOST which has a boron ionimplanted pB/pC high/low junction basewell. However, both nMOST and pMOST can be measured in the BEDCIV bias configuration on analog test transistor wafers since the highergain or hightransconductance nMOST requires a pB/nC junction basewell for electrical isolation. For the two lateral BJT or LBJT configurations, the DEDCIV is the most commonly used due to the ganged base pad and source pad. These ganged pads come from test transistor patterns with many channel lengths and widths. Due to large real estate requirements, few test transistors have isolated source, drain, gate and basewell contact pads. DrainEmitter (DE) (a) SourceEmitter (SE) (b) IB S 'B GBV I nL~ n I Pl I n I P p p I C. C' TopEmitter (TE) (c) BottomEmitter (BE) (d) IB VGB VPNVPN B GB B S D SB G D p p P n n SC C' Figure 2.2 Four DCIV bias configurations for a pMOS transistor: (a) DrainEmitter (DE), (b) SourceEmitter (SE), TopEmitter (TE), and (d) BottomEmitter (BE). (adapted from Yih Wang, PH.D thesis, December, 2000) Sah proposed this classification of the four DCIV bias configurations [1517, 26] in order to simpify and systemize the many possible DCIV measurements that are needed to give unique diagnostic solutions of test transistors for optimizing advanced manufacturing transistordesigns and processes development. In this thesis on the determination of the distribution of interface trap level, the TEDCIV is exploited to the fullest in order to provide reliable and accurate diagnoses. Future accuracy analysis will include the DEDCIV (and SEDCIV) and additional geometric effect. 2.3 Theory of RDCIV Methodology The dimensions of MetalOxideSilicon (MOS) fieldeffect transistors have continued to decrease, projected by SIA [4] in 1999 to drop below 100nm around the end of decade and has done so [2]. The width to length ration, W/L, could be unity or even smaller, making the width effect as important as the length effect on the transistor electrical characteristics. In this case, the transistor is threedimensional (3D). If a MOS transistor is much wider than its length, the structure is nearly twodimensional (2D) as indicated by the crosssectional view shown in Figure 2.1. The traditional industrial practice to design a transistor has been the use of super computers to obtain the DC steadystate numerical solutions of the threedimensional (3D) structure via the finitedifferent method. The 3D electrical characteristic solutions are tedious and complicated since they include the five simultaneous nonlinear partial Shockley equations, which govern the diffusion, drift and generationrecombination trapping of electrons and holes [6, pp. 268, Eqs (350.1)(350.6)]. As a diagnostic methodology, it is untenable to experimentally verify the transistor design during the engineering phase and manufacturing since the numerical solution takes a huge amount of time to reach an optimum transistor design. The dependence of the nonlinear coefficients (mobility, diffusivity, generationrecombinationtrapping rates) on the solutions (the electric field and potential, and the electron and hole concentrations) is not precisely known and can only be approximated by highly simplified quantum and statistical mechanical theory to give tractable analytical formulas. The further simplified empirical formulas have been used in common engineering practice for the fundamental parameters, which make the model and methodology inapplicable as an extrapolation scheme. Here, we use the partitioning methodology to divide the threedimensional (3D) transistor structure into onedimension (ID), disregarding the coupling effects of the other two dimensions (such as lateral diffusion and drift of the electrons and holes), because the salient feature of the DCIV methodology is that some of the ID features in the DCIV characteristics are strictly independent of the lateral (or yaxis) variation. Compared with the channel length (yaxis), the thickness of surface spacecharge layer and gate oxide is very thin. Thus, the variation of electric potential and field is small in the yaxis compared their xvariation, i.e., Ey(x,y) << Ex(x,y), which allows us to solve the ID xvariations exactly using ID MOS Capacitor (MOSC) and to sum these adjacent (in ydirection) to give the 2D solution such as the DC current of the basewell terminal. In the RDCIV measurements, excess minority carriers are injected by a forward biased p/n junction into the SiO2/Si interface which covers channel region between the source and drain of MOS transistors: the basewell channel region (BCR) and the drain and source junction and extension regions (DJR, SJR, DER and SER). The peaked components in a IBVGB plot arise from electronhole recombination at the SiO2/Si interface traps, NIT (No./cm2), in the five gatecovered regions along the interface channel. The surface recombination rate and current of each region reach their maximum when the gate voltage is varied to make the local surface concentration of electrons and holes nearly equal. When the bias configurations contain one or more forwardbiased p/n junctions, the device structure becomes a lateral or vertical bipolar junction transistor (LBJT and VBJT). Since LBJT is always available in a MOS transistor, the RDCIV measurement method can be applicable to actual small MOS transistors used in the integrated circuit [16]. Figure 2.3 is the energy band diagram of the metaloxidesilicon structure. The Ex energy band diagram is on a plane normal to the SiO2/Si interfacial plane and designated as the xdirection. It passes through the pbasewell underneath the gate oxide. It is labeled in detail to help describe the approximations of the analyses as follows. All voltages are normalized to the Boltzmann thermal voltage, kBT/q, where kB is the Boltzmann constant, T is the local lattice temperature and the q is the magnitude of the electron charge. The forward bias is UPN while the DC voltage applied to the gate relative to the pSi base is UGB. UN and Up are electron and hole quasiFermi potentials in pSi and their difference, known as the quasiFermipotential split, is UPN=UPUN. According to the charge neutrality condition and the electrical nonequilibrium from forward bias which gives N*P = ni2*exp(UpN) > ni2, the quasiFermipotentials in the quasineutral region of pSi base are Up =log, {NIM + 4n exp(UN)1/2 N, ]/2n,} (2.la) = log, {P, + 4n2 exp(Up )1/2 + P ] /2n,} (2. b) = log, {0.5 exp(UF){[(exp(2U) 1)2 + 4 exp(2UF + UN)]1/2 (exp(2U) 1)}} (2.1c) UN = log, {N + 4n2 exp(UPN)1/2 + N ]/2n,} (2.2a) = log, {P, +4n2 exp(UPN)1/2 PAA]/2n} (2.2b) = log {2exp(UF){[(exp(2U) 1)2 + 4exp(2UF + UpN)]1/2 + (1 exp(2UF))} 1( 2.2c) Here, NIM=NDDPAA is the net impurity concentration in base. Using UF = og,(PAA /nl) andUF = log,(NDD /nl), we get (2.1c) and (2.2c). The total energy band bending is denoted by the surface potential Us. The electron and hole concentrations at the SiO2/Si interface (Ns and Ps) are modulated by the gate voltage via bending the Si energy band: Ps = P(x = 0, y) = n, exp(Up Us) (2.3) Ns = N(x = 0, y) = n, exp(Us U,) (2.4) In our analysis, the surface potential normalized to the thermal voltage, kT/q, is the intrinsic position of the Fermi Potential Level at the surface or SiO2/Si interface. U,(x= 0,y) Us = qVs/kT (2.5) Four fundamental electronhole transition processes, between the continuous band states of silicon crystal and the localized trap states with an energy level ET in the silicon gap, can be illustrated using the energy band diagram as shown in figure 2.4. The rate (event/secondcm3) of the four processes can be conveniently described by: (a) electron capture from the conduction band at Cn(NTTnT), (b) electron emission to the conduction band at ennT, (c) hole capture from the valence band at CpnT, and (d) hole emission to the valence band at ep(NTTnT). Here, n and p are electron and hole concentrations in the conduction band and valence band respectively, NTT is the total density (#/cm3) and nT is the electronoccupied density of the trap states (#/cm3), and e's (sec) and c's (cm3sec1) are emission and capture rate coefficients of the four processes which depend on the energy levels of both the trap state and the band state. pBase\\ell ID Slice Ay Base BQNR N Space Charge Region Figure 2.3 Energy band diagram and cross sectional view of a gated n+Si/SiO2/pSi structure in the basewell channel region along x direction. UP and UN are respectively the electron and hole quasiFermi potential normalized to the thermal voltage (kT/q). (adapted from Yih Wang, PH.D thesis, December, 2000) Drain Gate Source Gate These four transition processes are mostly thermal involving emission and capture of phonons. The thermal capture and emission processes could involve about ten phonons for midgap trap levels since the maximum optical phonon energy is only about 62meV in silicon [27]. Huang and Rhys [28] did the first theoretical calculation of multiphonon process and Huang [29] refined it later. The firstprinciples calculation of the capture crosssections in a multiphonon process is rather laborious. For the purpose of developing a theory for the DCIV methodology, Shockley and Read, and Hall in 1952 [30] treated the fundamental capture and emission rates as constants independent of kinetic energies of band electrons and holes in order to develop the phenomenological kinetic theory. a b c d E nA Cnn(NTTnT) ennT ET nT A 1.12eV CppnT ep(NTTnT) Ev Figure 2.4 A transition energy band diagram showing the four fundamental transition processes between a conduction or valence band state and an electron trap state in the silicon energy gap: (a) capture of a conduction band electron by the trap, (b) emission a trapped electron to conduction band, (c) capture a valence hole by the trap, and (d) emission a trapped hole to valence band. The volume density of band electrons, band holes, electronoccupied traps and total traps are n, p, nT, and NTT respectively. The rates of the four processes are shown in terms of e's and c's. Purely thermal emission and capture processes involve multiple phonons. (adapted from ChihTang Sah [6,31]. In a RDCIV measurement, the base terminal current, IB, is measured as a function of gatebasewell voltage, VGB, which modulates the electronhole concentrations and recombination rate at the traps located at the gated Si02/Si interface. The excess minority carriers are injected into the MOSgated Si/Si02 interface by one or more forward biased p/n junctions in the MOS transistor structure, but also remote p/n junctions not part of the MOS transistor structure. The steadystate areal rate, Rss, of electronhole recombination at a discreteenergylevel of interface trap, with a interface trap density of NIT, is given by the ShockleyReadHall formula: Rss = Cp ps N,, Rss, x NT (2.6) CnsNs + ens + CpsPs + eps Here, Rssl is the steadystate recombination rate at NIT(y)dyW=l or the unit steady state recombination rate [26]. Cns, Cps, ens and eps are the electronhole captureemission rate coefficients at the interface traps, first introduced by Shockley and Read. From detailed balance near thermal equilibrium, c's and e's are related by ens=cnsniexp(UTI) and eps=cpsniexp(UTI). Using the Boltzmann representation for Ns and Ps given by (2.3) and (2.4), Rssl can be expressed by the more convenient forms as follow: Rs cnscpsNsPs enseps (2.7a) R S (2.7a) CnsNs + ens + csPs + eps (CnsCps)1 /2 n [exp(U ) 1] (2.7b) 2 exp(UpN /2)cosh(Us) + cosh(U ) Here, Us* and UTI* are the effective surface potential and interface trap energy, respectively. U: = Us +log,(cns /cs)1/2 (U + U,)/2 (2.8a) SUs +loge(Cns /c,)2 UF + U, /2 for p Si (2.8b) =Us +log,(cs /cs)1/2 UF Up /2 forn Si (2.8c) U, = ET /kBT = [(E,E,)/kBT+ Iln(cn, /c,)] (2.9) 2 Here, UTI is the interface trap energy level, measured from the intrinsic Fermi level El, defined by UTI = (ETEI)/q. Us(y) = Ui(x=0,y), commonly known as the surface energy band bending in the basewell channel region, is the total change of the electric potential along the xaxis at a particular yposition from the SiO2/Si interface (x=0) to the interior. Ui(x=infinity, y) = 0 is taken as the reference). The expression of (2.7) is exact with no approximations other than the thermal Boltzmann distribution with lattice temperature T. It immediately shows the presence of a peak at Us*=0 or cnsNs=cpsPs when the surface potential, Us, or the gate voltage VGB is varied. R p (Cnscps) /2n [exp(UN) 1] peak 2 exp(UpN /2)+ cosh(U ) (CnsCps)l/ n [ exp(Up, /2) 1] (2.10b) 2 For an interface trap energy level at around midgap with UTI*=O, we will have the classic IBo exp(qV/2kT) dependence, shown in (2.10b). This dependence suggests that many of the observed n=2 nonideal IV characteristics of p/n junctions [1, 7, 8, 31] could be due to interface traps at the surface perimeter of the p/n junction rather than residual bulk traps in the bulk spacechargelayer of the p/n junction. Rssl has a peak when the steadystate capture rate of electrons and holes are equal. It is expected from the equality of the four transitions, electron and hole capture and emission transitions at the trap. But more important, it is an immensely useful result that provides the simplest basis for qualitative interpretation and understanding of experimental data. The peak amplitude increases exponentially with forward bias, UpN, which gives the tremendous sensitivity and hence spatial resolution that are unique features of the DCIV method. The surface potential at the peak current (Us*=0) is USpeak loge(ns / Cps)1/2 +(Up + U.)/2 (2.1 la) loge(cns/cps)1/2+U Up /2 forpSi (2.11b) Sloge(cns/cps)1/2+UF+Up /2 fornSi (2.11c) The peak formula (2.1 la) was derived by SahNoyceShockley in 1957 [31] and used by Cai and Sah in 2000 for DCIV theory [20]. The basewell recombination current (IBBCR) [7, 8, 20, 26] is obtained by integrating the SRH steadystate electronhole recombination rate at the interface over the channel area dydz: IB(VGB) qj RssI (VGB, y)NIw (y)dydz (2.12a) q(cnsCps)12 nW [exp(Up, (y)) 1] (2.12b) 2 fJexp(UPN (y) / 2) cosh(U (y)) + cosh(U) N ()dy For low injection levels, traditionally defined as N < PAA/10 in pSi, we have UP=UF>O for pSi and UN UF potential. This is the common application range of the DCIV methodology. According to (2.1 Ib) and (2.1 lc), the RSS1peak lies in the flatband to the intrinsic gate voltage range (O Vs = VGB VFB 2*sign(Vs)*VAA{[l + (VGB VFB kTAD/q)VAA]1/2 1} (2.13) We have an approximation in this flatband/intrinsic range, VGB = VFB + Vs + 2(VAA) 1/2(V)1/2 ( 2.14a) = VFB + Vs + 0.053(Xox/lnm)(PAA/1017cm3)l/2 (2.14b) Then, the gate voltage at peak current IBpeak is VGBpeak 'VFB VSpeak + 0.053(X )( PAA 1/ 2( Speak )1/2 (2.15) Inm 101cm Here, VAA = EsqPAA/2Cox2 = 0.695*103*(Xox/ nm)(PAA/1017cm3)1/2. VFB is the flat band voltage which contains SiGate/SiO2/Si work function difference and the oxide charge from the charged electron and hole traps inside the thin oxide film, Q ,I Cox, where Cox= Es/Xox is the oxide capacitance per unite area. The last term in (2.13), (2.14) and (2.15) is the voltage drop across the oxide layer. The gate voltage at peak current VGBpeak is determined by the three terms: VFB, Vs peak and VAA, as indicated by (2.15) and (2.11). The dependencies on the transistor design parameters are (1) the substrate dopant concentration, (2) gate oxide thickness through VAA, (3) the ratio of electron and hole capture rates, (4) the flatband voltage VFB and (5) the emitter junction forward bias VpN. As a result, the IBpeak will shift toward a more positive VGB for a higher substrate impurity concentration or a thicker oxide thickness at a given forwardbiasvoltage VpN in an nMOS transistor. The theoretical variation of Rss1VGB lineshape due to device parameters is examined below, using the formula of halfwidth at half maximum (HWHM) at low injection levels [20]: AVGB+ = AVs + 2 VAA [V Vs peak AVs ] (flatband side) (2.16a) AVGB = AVs + 2VAA [V peak + AVs V ] (intrinsic side) (2.16b) As indicated in (2.16a) and (2.16b), the halfwidth on the flatband accumulation side of the peak is always larger and broader than that on the intrinsicinversion side of the peak. Thus, the recombination current lineshape is fundamentally asymmetric. A higher surface impurity concentration and thicker oxide will each give a larger HWHM or broader lineshape. For low injection levels, injected minority concentration has negligible effect on surface band bending, since VSVGB curve is mainly determined by the concentration of the majority carriers and ionized impurity atoms in the substrate. Therefore, effect of forward bias VpN at low injection level will have a negligible effect on DCIV lineshape. At high injection levels with N>10 X PAA, we have Up UN or the electron and hole concentrations in the channel region are nearly equal, and the maximum surface recombination rate is near the flatband. The exact result is Uspeak = loge(cps/cns)12 which can be derived from (2.1 la). As shown in (2.12b), the IB versus VGB lineshape is affected by Us* via the cosh(Us*) term in the denominator, assuming a singlelevel interface trap at the midgap, ETI*=0. Interface trap concentration NIT in the numerator of (2.12) only alters the peak amplitude but not the lineshape. Consequently, lineshape of IBVGB curve will be determined by the dopant impurity concentration and oxide thickness. 2.4 Theoretical Computations for Confident Level Before an attempt can be made to obtain the confident level of BI by comparing with the FD exact solutions when using the RDCIV methodology, a phenomenological model must be created and its analytical solutions derived. It is well known that the more exact the model is, the more accurate the derived solution will be. However, the solution will become complex with the advantage of model exactness, which will become quite clear in this thesis. In a semiconductor, temperature has an enormous influence on the electrical properties, especially the conductivity. The dielectric constants of silicon and silicon oxide have slight temperature dependence. A formula for SiO2/Si is not available since structural effects may begin to play an important role for thin oxides, and the formula would become a function of temperature and thickness. In this thesis, Esio2=3.90. For thin oxides transistors, the effective dielectric constant may be different due to interfacial layers. In fact, the concept of dielectric constants becomes debatable when only a few layers of atoms are involved. Increasing temperatures are associated with a narrowing of the energy gap. A secondorder polynomial by Bludau, Onton and Heinke [32] has been modeled to cover temperature range from 0 to 300K from the data on the absorption coefficient of highly pure ptype silicon. Sah, McNutt and Chan [33] gave the formula when temperature is above 300K and less than 500K. Since the intrinsic carrier concentration is an exponentiallike function of the energy gap, it is important to have an accurate value for the energy gap. Otherwise, the result will be substantially inaccurate. The calculated values of the energy gap and measures values of the intrinsic carrier concentration by Sah, McNutt and Chan [33], can use to compute the memh product. One remaining problem is the requirement of the individual effective masses to calculate Nc and Nv. Since there is no way to unequivocally separate the effective masses at temperatures significantly above 4.2K, this thesis uses the 4.2K data, obtained from cyclotron resonance measurements, which gave me/mo=1.065 and mh/mo=0.647, for an me/mh ratio of 1.646. The Boltzmann distribution (exponential) is a wellknown method used in the non degenerate case, i.e. low carrier concentration <108cm3, best approximating the Fermi statistics integral at low temperatures and/or low impurity doping, when (EcEF)/kT>4 or EF>Ec4kT. Degeneracy or Fermi statistics is used to deal with high carrier concentrations. Degeneracy is always important when the carrier concentration is high (and not just the dopant), such as in the presence of a highly forward biased p/n junction or under a bright light. In particular, degeneracy is important in the inversion and accumulation regions along the SiO2/Si interface channel of MOS transistors. Nevertheless, degeneracy is still generally not taken into account due to the complexity. There is no analytical solution for the Fermi statistics integral, so either fullrange analytical approximations must be used, such as those shown in Blackemore's paper on the subject of FD integrals [34], or iterative solutions must be employed, such as the rational Chebyshev approximations [35] used in this thesis. It is reasonably accurate to assume that all dopant impurities are ionized in most conditions. As long as shallowlevel dopants are used, which is equivalent to saying that the binding energy for electron (ntype) or hole (ptype) is small, so that almost complete ionization is expected. In ptype material, this can be easily rationalized by considering the Fermi level with respect to the dopant impurity level: as long as the Fermi level is above the acceptor level, the level should be filled with an electron and unoccupied by a hole, and hence the acceptors will be completely ionized. Similarly, as long as the Fermi level lies below the donor level in an ntype sample, the probability of the level being filled is low, and hence, the donor is likely ionized. When temperature is very low and the material is heavily doped, and/or the impurity level is deep, the impurity may not ionize completely, which is what is called deionization. This can be made sense physically at low temperatures: if there is not enough thermal energy to release the electrons or holes, then the impurities will not be ionized, or an electron will be trapped at the donor and hole will be trapped at the acceptor. For high doping concentrations, the Fermi level can go above donor level or below the acceptor level, and the fraction of ionized impurities will be consequently decrease. For electronhole recombination current at the SiO2/Si interface traps, gate voltage would attract electrons to interface and push holes away from interface in accumulation region. Thus, some donor impurities atoms near the SiO2/Si interface are occupied by the electrons and are deionized. The acceptor impurities are still ionized. In inversion region, gate voltage will push electrons away from interface and attract holes to interface. Thus, donor impurities are still ionized and acceptor impurities trap the holes at interface and are deionized. In this thesis, we only consider noncompensated materials, i.e. PAA=O in nBase and NDD=O in pBase. Thus deionization is entirely negligible except in the strong accumulation range. For modem ULSI technology, polysilicon gates are universally used on MOS devices. Gate depletion is possible and potentially nonnegligible for lowly doped gates (<5 x 102cm3). Polysilicon gates have some tremendous processing and transistor density benefits over metal gates, and can withstand high temperature steps that would cause most deposited metal gates to evaporate, particularly the source/drain drivein step. As oxide thickness continues to decrease, polysilicon depletion becomes a more important problem. The addition of the polysilicon depletion increases calculation complexity substantially since it introduces a second surface potential for the polysilicon gate. Yaron and FrohmanBentchkowsky [36], as well as Sah [5] have shown how to include the polysilicon depletion effect in CV theory. In this thesis, the confidence levels are computed for both metal and silicon gates. The most important effects are included in modeling RDCIV characteristics of a MOS transistor. However, there are many factors which are to be assumed negligible, but we should mention them for completeness. The transition layer between Si and Si02 is not abrupt an on the order of about one or two atomic layers (6A) in thin oxide [3739]. The transitional layer of SiOx has a different dielectric constant. The dielectric change in this very thin region should not be drastic enough to effect DCIV curves significantly, thus this effect was not included in this thesis. Energy gap narrowing was ignored for very high impurity concentrations. There is much debate about the modeling of the energy gap narrowing as a function of doping, and it is questionable whether the formulae are independent of deionization and especially impurity banding. Fringe field effects as well as frequency dependency of the dielectrics were not included. Series resistance, which is simple to include, was omitted since the RDCIV current density is low. Also, impurity banding was ignored in the analysis. The charge density in the semiconductor is given the equation p=q(N+PNA + PD n) (2.4.1) Here, N and P are electron and hole concentrations, respectively. The nT terms represents the contribution from trapped charge. NA and PD are respectively the ionized acceptors and donors [6,30]. N, = PA (2.4.2a) 1+ gexp([EA E ]/kT) ND = NDD (2.4.2b) 1+ g, exp([E, E] / kT) (2.4.2a) and (2.4.2b) take deionization into account. Generally, it is assumed that all of the impurities are completely ionized in doped silicon when shallow level impurities are used. This is a good approximation when T is large or EF >> EA. Incomplete impurity ionization occurs at low temperature and/or high doping (101cm3). For deep level impurities, deionization will become significant even at moderate doping and room temperature. In this thesis, we assume that MOS transistor has negligible trap charge. Using Poisson's equation, we can find the electric field Es in semiconductor. Starting from the d.c. steadystate equation in one dimension, we have EsdE/dx = p (2.4.3) Where, Es is the dielectric constant of silicon, E is the electric field in x direction, and p is the charge density given in (2.4.1). Since E=(dV/dx), we have EsdE / dx = Es (d / dx)(dV / dx) = Es [(dV / dx)(d / dV)](dV / dx) = (Ss /2)(d/dx)(dV/dx)2 = (s /2)(dE2 /dV) (2.4.4) Thus, from (2.4.3) and (2.4.4) dE2 = (2/ s)pdV = (2q/ s)(P+NNA +PD)dV (2.4.5) In (2.4.5), electric field can be integrated from Es(x=0) to E(x=oo)=0 and surface potential can be integrate from Us(x=0) to U(x=oo)=0 for charge density term. Then electric field is 2 2kT Es {NV[F3/2 (UU +UUF) F3/ (U + U)] Es +Nc[F3/2(Us +Uc UF)F3/2(U UF)] +N1+ gA lexp(UF U Us})] 1+ gA exp(U UA) +N], [US + log 1+ gD exp(UD U + Us)})]} (2.4.6) +NDD [Us + 1ge\ > D })] } (2.4.6) 1+ g exp(UD UF) The surface potential, Us, represents the amount of band bending of the silicon band at the SiO2/Si interface caused by the applied electric field or gate voltage. In this thesis, we only discuss the noncompensated region, i.e., either donor or acceptor is the dopant in substrate of MOS transistor. 2.4.1 BI, BD and FI Approximations Compared with FD Exact Theory Before finding the confident level of on % deviation the BI approximation, we first compare BI, BD and FI approximations with FD exact theory using RDCIV methodology. Here, BI stands for Boltzmann distribution of electrons and holes in energy and impurity full ionization. BD stands for Boltzmann distribution and impurity Deionization. FI stands for Fermi distribution of electrons and holes and impurity full ionization. FD stands for Fermi distribution and impurity deionization. For modeling RDCIV curves, the BI approximation is the fastest solution. There are two ways to derive the BI solution. One would be to build a BI model from the start using the Boltzmann (exponential) distribution for the carrier concentration while ignoring the effects of deionization completely. This is the typical textbook approach. A somewhat more instructive method is to present one complete derivation for the exact case (the degenerate and deionized model) and then reduce to a simper case. The later approach will be used in this thesis. The Boltzmann ionized solution is most useful just after the onset of accumulation or inversion at temperatures higher than 250K and doping less than 101cm 3. When in the strong accumulation or inversion ranges, Fermi statistical distribution are required. At low temperatures and/or high doping, the effect of deionization becomes nonnegligible and should be included. However, temperature at around 300K and impurity concentration lower thanl01cm3 are in the practical ranges. In addition, BI approximation solution is simple and timesaving. These were the right reasons we used BI approximation when using DCIV methodology to extrapolate the profile of impurity concentration, interface trap concentration and oxide thickness [26, 40]. The exact FD solution for a pdoped semiconductor is given by [5, pp.129]: VGB = VFB + Vs + sign(Vs)8sE, /Cox (2.4.7) According to (2.4.6), the electric field at the surface pSi, which includes the electrical nonequilibrium from the forward applied p/n junction voltage VpN, is given by 22kT Es = {Nv[F3/ (Us U +UF) F3/ (U +UU)] Es + N [F3/, (Us + Uc U, + UP) F3/2 (Uc UF + Up )] + P (Us + log exp(U ])} for FD (2.4.8) 1+ g, exp(UF U,) Once we assume that all the dopant impurities are fully ionized, the logarithmic tem of (2.4.8) is dropped, we have the electric field of FI 2kT Es = {N[F32 (Us UV + U) F32 (U + UF)] Es + NC [F3/2(Us + Uc UF+UPN) F3/ (Uc UF+UPN)] +PAAUs} for FI (2.4.9) Reducing this result to BD solution is straightforward. All the FD integrate are simply replaced by exponentials, which is valid when Fermi energy less than about 4 [69]. 2kT Es = {N,[exp(Us U,U) exp(U, + U,)] + N [exp(Us + Uc UF+UPN) exp(Uc UF+UP)] + PAA(Us + loge [1 A exp( A ])} for BD (2.4.10) 1+ gAexp(U UA) In order to remove the deionization effect, we assume the trap level is far away from the Fermi level exp(UFUA)< zero. Thus, the electric field of BI is Es 2kT {N,[exp(Us U U U) exp(U + U)] + Nc [exp(Us + Uc UF+ Up,) exp(Uc U+ Up )] + PAAUS forBI (2.4.11) The different electric field form (BI, BD, FI and FD) give different surface potential Us, which would affect the lineshape of DCIV curves. The four recombination DCIV curves are shown in Figure 2.5. The Lineshape of the three approximations are almost the same as the exact FermiDeionization solution, the difference between Fermi and Boltzmann statistics appears only when IB is around eight decades smaller than peak current IBpeak. The difference between using fully ionization and deionization models, such as BI and BD or FI and FD, is very small as shown in Figure 2.5(a). From Figure 2.5(a), the 90 percent of the peak current covers a gate voltage range from 0.10V to +0.10V. Figure 2.5(b) shows the % deviation is less than 0.1% for all three approximations in this gate voltage range for peak current IBpeak down to the 10% peak. As shown in Figure 2.5, the switch from full ionization to deionization generally results in very little gain by comparing with the increase in accuracy gained by switching from Boltzmann to Fermi statistics. However, in situations where the temperature is very low and/or the dopant concentration is quite high, deionization effects are nonnegligible. Also, if the dopant produces a deeplevel trap, deionization will become significant factor regardless of the doping concentration or temperature. According to Figure 2.5, we can conclude that BI and FI solutions are respectively nearly as good as BD and FD solutions, especially in accumulation region since deionization occurs only in this region. The nondegenerate, fullyionized solution is simplest when we assume that the minority carrier terms are negligible and the majority surface concentration is much larger than the bulk concentration, and the deionization term is dropped. This assumption would invalidate the Boltzmann assumption in some case, such as in strong accumulation region. But it allows us to find an analytical solution. For FermiDeionization case, the final solution will be iterative, which is the main disadvantage of including degeneracy. An exactly accurate numerical theoretical solution is impossible because of the approximation the formulae used for the normal and inverse Fermi integrals. The effects of deionization in the application range are generally so small that the error from using Boltzmann statistics instead of Fermi will swamp any gain from including deionization, except at the extremes, such as high doping and/or low temperature at the onset of inversion or accumulation, or for deep level traps. The inclusion of deionization also makes the Boltzmann case nonanalytical. More important, BI solution is simple and timesaving. For these reasons, we will compute the confident level or percentage deviation of the BI solution by comparing with the exact FD theory. 102 10 10 _T  10  102 nMOST S Xox=35A 10 V,=200mV 04 PAA=107cm3 10 105 1.5 1.0 0 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 VGBVGBPK/(V) 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 VGBVGBPK/( V) Figure 2.5 (a) Comparison of the theoretical RDCIV curves between BI, BD, FI, and FD solutions. (b) Normalized percentage deviation with respect to the exact or real FD theory. %Deviation = %[(IBBI/BD/FI/BBI/BD/FIpeak)/(IBFD/BFDpeak) 1]*100. The three points are for flatband (Us=0), subthreshold voltage (Us=UF), threshold voltage (Us=2UF). Temperature T=296.15K. Metal gate MOS transistor. Q 0 LI 0 tL 0e m ii M M m i 1 T 101 102 103 10 10 6 107 10 10 6 10 210 10 9 Five important factors that affect IBVGB lineshape are analyzed. These are expected to be dominant in conventional or production MOS transistors. They are: * Dopant Impurity Concentration Dependence * Oxide Thickness Dependence * Injected Minority Carrier Concentration Dependence * Energy Position of Discrete Energy Level Interface Traps * Temperature Dependence A midgap symmetrical interface trap is assumed ETEI=0with Cns=Cps=l10cm3/s, and NIT=101 cm3. The effect of ratio of electron and hole capture rates at the midgap on the DCIV lineshape is small, which will be discussed in the chapter 3. ni=101ocm3 corresponding to T=296.57K=23.42C=74.156F. The length and width of MOS transistors are 10um and lum, respectively. These results are the new applications that provide the feedbacks for optimization of the design and fabrication of increasing smaller transistor when using the simple and timesaving Boltzmann approximation with impurity full ionized solution of RDCIV methodology. 2.4.2 Dopant Impurity Concentration Dependence When the channel length of modem MOS transistor is scaled to 0.25um and below, a much higher dopant impurity concentration is necessary to reduce the thickness of the surface space charge region Xss and the reversebiased p/n junction spacecharge layer Ypn, as shown in Figure 2.1, in order to maintain the desired transistor characteristics. The high impurity concentration limit the worsening of the transistor characteristics from short channel and channel length modulated by the thickening of drain junction space charge region from the reverse voltage applied to the drain [4145]. If a spatially constant impurity concentration is used to limit the drain junction space charge thickness and thickness modulation by the drain voltage, the gate voltage required to turn on the MOS conduction channel would be excessive in order to overcome this high impurity concentration. In order to avoid this, twodimension impurity profile, such as the halo concentration contour by lowangle ion implantation or the "pocket", are designed into modern short channel transistors. The unavoidable impurity redistribution from diffusion and segregation disturbs the designed impurity profile during thermal oxidation [4647]. The impurity concentration profile is further complicated by defect annealing after ion implantation [4851] for a selfaligned source and drain to reduce overlap capacitances and shallow dopant at the Si/SiO2 interface for threshold voltage adjustment. In this section, constant dopant impurity profile is used to find the confident level ofBI solution using DCIV methodology, but it still allows us to extrapolate the confident level of Ushaped or inverted Ushaped impurity profiles since the confident level depends on the impurity concentration. The effect of impurity concentration 1016 to 1019 per cubic centimeters on the error analysis using BoltzmannIonization approximation is compared with the exact Fermi Deionization results. Figures 2.6 and 2.7 show a family of normalized theoretical recombination DCIV curves using BI approximation solution in dash line and the FD exact theory in solid line for metal gate case and silicon gate transistors, respectively. For short channel and small area transistors, the DCIV current is in the Femto ampere range. So only the current near the peak can be measured because of noise. Thus, the lineshape and error on percentage deviation are presented in the linear scale as shown in Figure 2.6(a) and 2.7(a). For large area and long channel transistors, the recombination DCIV current can be in the nanoampere range and the noise is three or more decades smaller. The lineshape and errors on percentage deviation are presented in semilog scale as shown in Figure 2.6 (b) and (c), and Figure 2.7(b) and (c), respectively. In both Figure 2.6(a) and 2.7(a), the 10% peak current, which means 100% IBpeak down to 10% IBpeak, is covered by a gate voltage range from 0.2V to +0.2V. We can see that the error or % deviation of the Boltzmann ionization approximation less than 8% for 1019 impurity concentration for both metal gate and silicon gate cases as shown in Figure 2.6(c) and 2.7 (c). When impurity concentration is 5 X 1017, which is in practical range, % deviation is less than 1% for metal gate case, while it is less than 2% for silicon gate devices. Figure 2.6(d) and 2.7(d) give the %RMS deviation when matching 10% to 90% of the theoretical curve to the experimental data. We can see that the Boltzmann approximation gives less than 4% RMS deviation at 1019 impurity concentration for both metal gate and silicon gate cases. For 1018 impurity concentration, the %RMS deviation is less than 1% for metal gate case and 2% for silicon gate case, when matching 90% of the theoretical curve to the experimental data. As already proved by Yih Wang and Sah [40], the distortion of IB vs. VGB lineshape is from the spatial variation of dopant impurity concentration which can be further distorted by the spatial variation of interface trap concentration NIT, but not by NIT alone at the interface of SiO2/Si with a constant impurity concentration. This allows us to extrapolate the percentage deviation and %RMS for nonconstant dopant impurity concentration at the interface of a MOS transistor. For Ushaped impurity concentration along channel with PAA =1017cm3 in the middle of the channel PAA =101cm3 at the end of the channel, the percentage deviation and %RMS error are all no more than 1% for 1.0 nMO Xox=3. 0.75 V 2C .IBBI 0.5 0.25 0.0 0.3 0.2 0.1 0.0 0.1 0.2 0.3 VGBVGBPK /(1V) 1 101 102 10 2 10 3 105 4 106 107 6 7 10 1081 1.0 0.5 0.0 0.5 VGBVGBPK /(1V) Figure 2.6 Effect of dopant impurity concentration on the DCIV on the normalized IB VS. VGB lineshape. (a) IB VS. VGB in linear scale, (b) IB VS. VGB in semilog scale. The substrate impurity. (c) percentage deviation and (d) %RMS deviation. RMS90, RMS75(FWQM), RMS50(FWHM), RMS25 and RMS 10 represent the lineshape for peak current IBpeak down to 90%, 75%, 50%, 25% and 10% of IBpeak, respectively. Metal gate nMOS transistors. m ii i 10 I I II i I I I I I I I nMOST S 1 Xo3.5nm m I Vp=200mV m 1 > RMS90 A o RMS75 "9 Y' a RMS50 I) 103 o RMS25 SRMS10 104 I V=200V (d) 10 16 1017 1018 1019 PAA/(cm3) 102 Increasing PA 111 S1 o 0 / , "> 3  05xl0 1 2 > 10 nMOST SXox=3.5nm 4 S"10 F VpN200mV (C) 5 I I I I I I I I I I I 1.0 0.5 0.0 0.5 1.0 VGBVGBPK /(1 V) Figure 2.6 Continued 1 1 102 10 04 105 104 106 5 10 6 1071 .7 8.. l1i 0.2 0.1 0.0 0.1 0.2 0.3 VGBVGBPK /(1V) Figure 2.7 Effect of dopant impurity concentration on the DCIV on the normalized IB VS. VGB lineshape. (a) IB VS. VGB in linear scale, (b) IB VS. VGB in semilog scale. (c) percentage deviation and (d) %RMS deviation. Silicon gate nMOS transistors. 0.5 0.0 0.5 VGBVGBPK /( V) 1.0 0.75 0.5 0e m m ii M M 0.25 0.0" 0.3 a. m 1I II 0 _0 () rr 1016 1017 1018 PAA/(cm3) Figure 2.7 Continued 1019 metal gate cases, and they are respective not more than 6% and 2% for silicon gate cases when matching 90% of the curve, since we can assume a constant PAA= 10cm3 along the channel, and the percentage deviation and %RMS are monotone increasing with impurity concentration as shown in Figure 2.6(c) and (d), Figure 2.7(c) and (d). Similarly, we can obtain the same results for inverted Ushaped impurity concentration along channel with PAA =1018cm3 in the middle of the channel PAA =1017cm3 at the end of the channel, since the distortion of DCIV lineshape is in accumulation region or negative VGB side for inverted Ushape PAA while the distortion is in inversion region or positive VGB side for a Ushape PAA in a nMOS transistor. 2.4.3 Oxide Thickness Dependence Boltzmann approximation solutions are reasonable for thick oxide MOS transistors. For thin oxides, neglecting degeneracy in inversion or accumulation is less accurate because accumulation and inversion give high carrier concentrations, which compromise the assumption of the Boltzmann distribution. Degeneracy can be included because there are several approximations which can be used [34, 35, 5255], although the Fermi integrals used in solidstate applications have no analytical solutions. In the last ten years, the more accurate FD approximations have been available by the highspeed computers, such those by Cody and Thacher [35], and Van Halen and Pulfrey [54]. Thus, degeneracy can be included for a more accurate solution. However, the error or percentage deviation is still so small enough for the simple and timesaving BI approximation solution in practical range, such as PAA=5 X 1017 cm3 for pSi and Xox=35A as shown in Figure 2.6 and 2.7, which is what we shall continue to use. Figures 2.8 and 2.9 respectively give one family of normalized IB VS. VGB to show the lineshape dependence on the one of the most basic MOS transistor design parameters, the oxide thickness (another is dopant impurity concentration), in the transistor spatial regions where the gate voltage is designed to control the electrical characteristics of the transistor, for metal gate and silicon gate case. Oxide thickness varies from 10A to 300A, which covers all practical range. The lineshape broadens, and the linewidth (AVGB+ andAVGB) increases as the oxide thickness and dopant impurity concentration increases as shown in Figure 2.6 and 2.7, and Figure 2.8 and 2.9, respectively. The peak gate voltage (VGBpeak) shifts toward the more positive gate voltage, i.e. towards increasing holeaccumulation range in the SiO2/Si interface for a p type doped substrate. These dependencies are anticipated by (2.15) and (2.16). They are also expected by simple device and material physics. For instance, a higher gate voltage or electric field is required to change the amount of surface potential or surface energy band bending in order to reach the peak recombination rate condition, CnsNs=cpsPs, as indicated by (2.6). It is evident that these curves are equally applicable to the pBase of nMOS transistor and the pDER and pSER of pMOS transistors. The linear DCIV curves in Figure 2.8(a) and Figure 2.9(a) are application to short channel application and semilog curves in Figure 2.8 (b) and Figure 2.9(b) are for application to long channel application of MOS transistors. The oxide thickness varies from 13 angstroms from 300 angstroms. 1.0r 0.75 0.5 0.25 0.0 0.5 0.5 0.0 0.5 VGBVGBPK /( V) Figure 2.8 Effect of oxide thickness on the DCIV on the normalized IB VS. VGB lineshape. (a) IB VS. VGB in linear scale, (b) IB VS. VGB in semilog scale (c) percentage deviation and (d) %RMS deviation. Metal gate nMOS transistors. 0.25 0.0 0.25 VGBVGBPK /( V) m 1=1 1 101 102 o6 10 105 106 4L 107 08 109 1.0 10 8 l1i 0.5 0.0 0.5 VGBVGBPK /( V) 50 100 150 200 250 300 Xox/(A) Figure 2.8 Continued m a m II 0 W > L.J Ql v 102 10 1 10 102 10 103 1.0 a m 4 0 o CO 1 10 2L 0 a_ t I VGBVGBPK /(1V) m M i mt i 1 101 102 3lO 10 105 10 5 10 6 109 7.0 107 1.0 0.5 0.0 0.5 VGBVGBPK /(1V) Figure 2.9 Effect of oxide thickness on the DCIV on the normalized IB VS. VGB lineshape. (a) IB VS. VGB in linear scale, (b) IB VS. VGB in semilog scale. (c) percentage deviation and (d) %RMS deviation. Silicon gate nMOS transistors. 0.5 0.0 0.5 VGBVGBPK /(1 V) 50 100 150 Xox/(A) 200 250 300 Figure 2.9 Continued For thin oxide MOS transistors, gate voltage covers from 0.1V to +0.1V for peak current down to 10 percent of the peak. While for metal and silicon gate thick oxide, gate voltage widen to the range of 0.4V to +0.4V for peak current down to 10 percent of peak. 102 10 1 101 102 2 10 a 0 W 10 1.0 m M 0 0 102 10 (d) SA A A A A RMS90 nMOST T o RMS75 VpN=200mV a RUSSO PAA=1018cm3 o RMS25 v RMS10 IIII 111111 IIII III 1111111111 0 Figure 2.8(c) and 2.9(c) show the %deviation using the Boltzmann approximation and full ionization of impurity for metal gate and silicon transistors. Again, it is compared with the exact Fermi distribution and impurity deionization. We see that the deviation is about 2% or less for metal gate devices and 4% for silicon gate MOS transistors covering the curve above 10% IBpeak. The %RMS deviation for 1018 impurity concentration is given in Figure 2.8(d). The error is less than 2% if we use only 90% of the measured DCIV curve down from IBpeak and it is less if we use less of the DCIV for both metal and silicon gate MOS transistors. In this section, constant oxide thickness profile is assumed to find the confident level of BI solution using DCIV methodology, but it still allows us to extrapolate the confident level of Ushaped or inverted Ushaped oxide thickness profiles at the interface of a MOS transistor since the confident level depends on oxide thickness. From the confidence levels of BI, we can conclude that the errors are small enough by using the BI model to extract oxide thickness from experiments over entire practical range. Thus, the simple and timesaving BI approximation solutions can used to extract the oxide thickness profile in MOS transistors. 2.4.4 Injected Minority Carrier Concentration Dependence At low injection levels in an pSi with PAA=1017cm3, defined as N effect on DCIV lineshape. In this case, we have Up=UF>O for pSi and UN=UF According to (2.11) and (2.15), VGBpeak 0 loge(Cns /cps)1/2 + U UpUN /2 O Vp, /2 for p Si VGBpeak c loge(cns /cps)1/2 + UF + UN /2 c Vp, /2 for n Si Thus, gate voltage at the peak current VGBpeak would increase with forward bias VpN in the nBase of pMOST and decrease with VpN in the pBase of nMOST. Low injection level is the common application range of the DCIV methodology. At high injection levels with VpN>800mV, the linewidth has the exp(UpN/4) dependence on forward bias VpN [20]. Thus, at low injection levels, the IBVGB linewidth can be large which is determined by the effective trap energy level, ETI*. The linewidth then decreases with increasing VPN until the onset of high injection level condition, beyond which it increases exponentially with VPN. The broadening of DCIV lineshape from high injection levels could occur at lower VPN in real transistors due to voltagedrop or VPN drop from high current density through the lateral base resistance and series drain and source resistances, and due to gate voltage lowering of the forward biased drain and source p/n junction barrier heights, and reduced majority carrier concentration at surface channel from surface band bending in the sub threshold region. Another important source of lineshape modification comes from the diffusion and drift current limitation on the emitter junction injection efficiency due to builtin electric field from graded vertical (xdirection) impurity concentration profile PAA(x,y), which is from the designed ion implantation in the bottomemitter configuration as shown in Figure 2.2(d). Since the diffusiondrift current is in series with the recombination current at the interface traps, the smaller one would dominate. The importance of the diffusiondrift limitation of the injection current has been demonstrated using experimental data [26]. The applications of short channel and long channel of MOS transistors are given in the linear Figure 2.10(a) and Figure 2.1 l(a), in the semilog curves in Figure 2.10(b) and 2.1 l(b). The figures for metal gate and silicon gate MOS transistors are respectively shown in Figure 2.10 and 2.11. The injected minority carrier concentration is increased from forward bias of 100mV from 800mV. For small injection minority carrier concentration, gate voltage covers from 0. 1V to +0. 1V for peak current down to 10 percent of the peak. While, gate voltage should change from 0.25V to +0.25V for peak current down to 10 percent of peak for high injection MOS transistors. Figure 2.10(c) and 2.11(c) show the %deviation using the Boltzmann approximation and full ionization of impurity for metal gate and silicon gate transistors. Again, it is compared with the exact Fermi distribution and impurity deionization. We see that the deviations are respectively about 6% and 10% for metal gate and silicon gate devices when matching 90% of experimental data from peak current IBpeak down to 10% of the peak using Boltzmann full ionization approximation solution. The %RMS deviation for 1018 impurity concentration is given in Figure 2.10(d) and 2.1 l(d). The error is around less than 3% for forward bias VPN smaller than 600mV and 6% for VPN smaller than 800mV if we use only 90% of the measured DCIV curve for metal gate transistors. While in silicon gate devices, these two values are respectively 4% and 8%.The %RMS deviation is less than 0.4% if we match only 10% of DCIV curves to experiments for both metal gate and silicon gate cases. These values of % deviation and %RMS deviation indicate that the Boltzmann full ionization approximation solution is good enough to extract the parameters of MOS transistors when forward bias VPN is in practical range. 1.0 0.75 0.5 Q. m II 0.25 ' ,,I \ 8Pm 'PN 700mV (100mV 2400mV 300m\ I I I ' I I nMOST / Xox=35A / PAA=10 cm" IBFD, IBDrt  .... IB.BI' IBir  ^ 0.0 0.25 u.u 0.25 N VGBVGBpk/(1 V) 101 m II VGBVGBpk/(1 V) Figure 2.10 Effect of injection carrier concentration on the DCIV on the normalized IB vs. VGB lineshape. (a) IB vs. VGB in linear scale, (b) IB vs. VGB in semilog scale. (c) percentage deviation and (d) %RMS deviation. Metal gate nMOS transistors. 1.0 0.5 0.0 0.5  I (1  I 4. 1 1 1 0.5 0.0 0.5 VGBVGBpk/(1 V) 200 300 400 500 600 700 800 VpN/(mV) Figure 2.10 Continued 102 10 1 101 101 2 10 3 10 m m 4 0 iLJ G 1041 1.0 a m II m 0 o (/) c^: 1 10 102 .LL 100 100 1.0 71 r nMOI Xox=3' 0.75 PAA=10 ~I IBI/ 0.5 0.25 0.0 0.3 0.2 0.1 0.0 0.1 0.2 0.3 VGBVGBPK /( V) 1 r 107 102 10 l3^ 104 105 4 10 95J 107 1.06 10 7 109 1.0 0.5 0.0 0.5 VGBVGBPK /(1V) Figure 2.11 Effect of injection carrier concentration on the DCIV on the normalized IB vs. VGB lineshape. (a) IB vs. VGB in linear scale, (b) IB vs. VGB in semilog scale. (c) percentage deviation and (d) %RMS deviation. Silicon gate nMOS transistors. 0.5 0.0 VGBVGBPK 0.5 /(1V) 200 300 400 500 600 700 800 VpN/(mV) Figure 2.11 Continued 2.4.5 Energy Position of Discrete Energy Level Interface Traps If a semiconductor is doped with a shallowlevel impurity, the impurity is expected to be fully ionized at room temperature. However, if the dopant produces a deeplevel 102 10 1 10 102 2 10 11 0 LJ Qt e 1031 1 10 1.0 aQ m m 4 0 o (V) Oc) IE 1 10 A RMS90 44  o RMS75 nMOST a RMS50 U  L 4  Xox=35A o RMS25 PAA=1o0cm3 v RMS10 , I , I I , I , I 10 100 trap, deionization will become a significant factor regardless of the doping concentration or temperature. According to (2.7) and (2.12), the interface trap energy level ETI determines the DCVI linewidth. As shown in Figure 2.10 and 2.11, the lineshape changes with increasing forward biases, VPN, applied to an n/p junction in pSi with an acceptor impurity concentration PAA=10cm3, an oxide thickness of 3.5nm, and a discrete interface trap at midgap (ETI=0). Figures 2.12(a) and 2.13(a) give the effect of the interface trap energy level position on the recombination DCIV lineshape for metal gate and silicon gate transistors, respectively. These figures are for 1discrete interface trap level. The reference of interface trap level is intrinsic Fermi level or midgap. If forward bias is less than interface trap energy, i.e., VPN peak current IBpeak and the lineshape is symmetrically broadened by shallower energy level traps, such as 0.2eV and 0.3eV traps. Note, the broad top is the distinct signature of a shallow interface trap energy level. The application on large area and long channel transistors is given in Figure 2.12(b) and 2.13(b) The %deviations for Boltzmann ionization approximation are given in Figure 2.12(c) and 2.13(c). Since gate voltage varies from 0.5V to +0.5V for peak current down to 10 percent of the peak for shallow trap levels, such as ETI=300mV. The %deviation is about 8% for metal gate devices and 15% for silicon gate transistors when matching 90% of experiment DCIV curve to theory using Boltzmann ionization approximation solutions. At midgap level, which is the commonest assumption for interface trap level during computations using DCIV mythology, the %deviation are less than 2% for metal gate devices and 5% for silicon gate transistors. Figure 2.12(d) and 2.13(d) show the %RMS deviation using 10% to 90% of the theoretical 1.0 0.75 0.5 0.25 0.0'L 0.5 m CL M M a m 1 101 102 12 10 10 10 10 10 5 6 7 10 108 1.0 0.25 0.0 0.25 VGBVGBPK /(1 V) 0.5 0.5 0.0 0.5 VGBVGBPK /(1 V) Figure 2.12 Effect of energy position of discrete interface trap energy level on the DCIV on the normalized IB vs. VGB lineshape. (a) IB vs. VGB in linear scale, (b) IB vs. VGB in semilog scale. (c) percentage deviation and (d) %RMS deviation. Metal gate nMOS transistors. 0e m IL  m 5 LJ. 10 1.0 0.5 0.0 0.5 VGBVGBPK/(V) 1U 10 50 100 150 200 250 300 ETI/(meV) Figure 2.12 Continued 1 0 LLI r' e 102 10 1 10 1072 102 103 10 4 10 a 4 (L IM 0 o (I)  a RMS90 RMS9 nMOST (d)  o RMS75 Xox=3.5nm RMS50 VpN=200mV o RMS25 P ,=10"crn3 o RMS 25  RUSIO _B 4 ^ ^ IIIIIIIIIII 11111111 111 IIIIIII I I I I I I I I I I I I I I I I I I I I I I I I I I i 3 1 2 10 0 1.0 r  V 0.75 0.5 0.25 0.0 0.5 0.5 0.5 0.0 0.5 VGBVGBPK /( V) Figure 2.13 Effect of energy position of discrete interface trap energy level on the DCIV on the normalized IB vs. VGB lineshape. (a) IB vs. VGB in linear scale, (b) IB vs. VGB in semilog scale. (c) percentage deviation and (d) %RMS deviation. Silicon gate nMOS transistors. 0.25 0.0 0.25 VGBVGBPK /( V) 1 101 102 12 10 3 10 4 105 5 106 16 10 7 10 10 1 1.0 102 10  1 1 10 2 10 3 10 4 10 1.05 1.0 0 . I II 0III I l 44 nMOST Xox=35A VpN=200meV PAA=10 cm"3 I ,I,,, I,, SRMS90 o RMS75 a RMS50 (d) o RMS25 v RMS10 ,,I,,,,,,,, I,,,,II 50 100 150 200 ETI/(meV) Figure 2.13 Continued curve to compare with experimental data. Again the error is less than 2% for metal gate case and 5% for silicon gate case even for the shallowest level. 0.5 0.0 0.5 VGBVGBPK/(V) m 4 0 > a ct a m m 4 0 o 1 101 250 300 ''''''''''''''''''' '''''''''' S21 10 0 The percentage deviation in accumulation region is greater than that in inversion region, as shown in the percentage curves from Figure 2.6 to 2.13, which is clearer by comparing the DCIV curves using BI approximation solutions with the exact FD theory in the semilog figures. In accumulation region, gate voltage attracts electrons to interface. Thus, electrons are trapped at the donor impurities near the SiO2/Si interface. While the donor impurities at interface are still ionized since gate voltage push electron away for ptype substrate. Therefore, deionization occurs only in accumulation region for pSi. The above discussion of energy position of discrete energy level interface traps has been based on the physicsbased assumptions that the ratio of electron and hole capture rates is a constant and the interface trap density is also a constant in the silicon gap. The detail discussion of interface trap energy profile on DCIV lineshape will be given in the next chapter. 2.4.6 Temperature Dependence When the interface of SiO2/Si of a MOS device is in the strong accumulation or inversion ranges, degeneracy comes into play with respect to device modeling. Thus, Fermi statistics are required. At low temperature and/or high doping, the effect of deionization becomes nonnegligible, and should be included. The Boltzmann ionized approximation solution is most useful around the onset of accumulation or inversion at temperatures higher than 250K and doping less than 1018cm3. The practical temperature varies from 293K to 333K for a MOS transistor. In this section, we will try to find the confident levels in this range of temperature of BI approximation solution by comparing the exact FD theory using DCIV methodology. 1.0 0.75 m i_ 0.25 F r. ,\ f I I I I MOST X,,=35A ',,=2immV P,=10 "mm"' T=293333K u.u 0.2 I I I I (a)  .l iBBi.pk  BBI 'BBipk Increasing T // SI I 0.1 0.0 0.1 0.2 0.0 0.1 0.2 VGBVGBpk/(1V) 1 10 102 10 10 3 10 4 106 1075 10 7 10 1 81 1.0 0.5 0.0 0.5 VGBVGBpk/( V) Figure 2.14 Effect of temperature on the DCIV on the normalized IB vs. VGB lineshape. (a) IB vs. VGB in linear scale, (b) IB vs. VGB in semilog scale. (c) percentage deviation and (d) %RMS deviation. Metal gate nMOS transistors. m II M _q 102 10 1 1 10 2 10 3 10 P.  T MOST Xox=35A (p=200mV A=101'cm3 =293~333K 0.5 0.0 0.5 VGBVGBpk/(1V) 303 313 T/(1K) 323 Figure 2.14 Continued ' I ' Q. m m II 0 O > tQ. a I I I I I I 04 1.0  MOST RMS90 Xox=35A (d a RMS75 VpN=200mV RMS50 PA=10lcm3 o RMS25  T=293333K v RMSO1 1 _ r m m 0 o V) y 8 101 9 102 293 333 (c) Decreasing T  I I I I I I I I I I nMOST X,,x=35.A Vp\,=200mV P =1O0"cm' T=293333K 0.1 1.0 0.75 0.0 (a) 0.2 VGBVGBpk/(1V) 0.5 0.0 0.5 VGBVGBpk/(1V) Figure 2.15 Effect of temperature on the DCIV on the normalized IB vs. VGB lineshape. (a) IB vs. VGB in linear scale, (b) IB vs. VGB in semilog scale. (c) percentage deviation and (d) %RMS deviation. Silicon gate nMOS transistors. I Ir FD 1e F0k S  IBBI IBBipk Increasing T // Q. m I 1""I 0.25 0.0 ' 0.2 1 10 102 10 10 3 10 4 106 107 6 7 10 rn m I i rn 1081 1.0 I I I I I I I I I ,I, ,I I I I, I , 101 1.0 10293 293 0.5 0.0 0.5 VGBVGBpk/(1 V) 303 313 T/(1K) 323 1 3 .0 33 Figure 2.15 Continued The temperature dependence of surface recombination current in the basewell channel region is mainly determined by the temperature dependence of intrinsic carrier concentration ni, in which, the effective density state in conduction band Nc and in 102 10 1 101 102 10 10 3 10 m m 0 > bi m ii 0 o (I M\ 1 101  I I I I (d) ?" D  a  ______ S0 > < ~  MOST a RMS90   Xox35A o RMS75  Vp=2OOmV a RMS50 PA,=lO'cm3 o RMS25 T=293~333K v RMS10 ,T =29i l 3K I I I , 91 ''''''''''''''''''' valence band Nv and silicon energy gap EG are functions of temperature. Thus, the transistor characteristics are temperature dependent. The linear DCIV curves in Figure 2.14(a) and 2.15(a) are for short channel application and semilog curves in Figure 2.14(b) and 2.15(b) for the application of long channel and large area MOS transistors. In this temperature range, gate voltage covers from 0.15V to +0.15V for peak current IBpeak down to 10 percent of the peak for both metal gate and silicon gate transistors. Figure 2.14(c) and 2.15(c) show the %deviation using the Boltzmann approximation and full ionization of impurity by comparing with the exact Fermi distribution and impurity deionization. We see that the deviation is about 2% or less for metal gate case and 5% for silicon gate case when marching peak current IBpeak down to 10% of the peak. The %RMS deviations are given in Figure 2.14(d) and 2.15(d). The error is less than 1% for metal gate transistors and 2% for silicon gate devices if we use only 90% of the measured DCIV curve and it is less if we use less of the DCIV. These confidence levels indicate that temperature fluctuation gives negligible errors when using BI approximation solutions to extract the parameters such as surface dopant impurity concentration and interface trap concentration profiles and oxide thickness profile in a MOS transistor. A detail discussion about temperature effect on DCIV lineshape, peak current amplitude IBpeak, peak gate voltage VGB and thermal active energy EA at different interface trap energy levels ETI will be described in the next chapter. 2.5 Summary Effects from variation at the SiO2/Si interface of the dopant impurity concentration PAA, oxide thickness Xox, the injected minority carriers VpN, energy position of interface trap level ETI and temperature T on the lineshape of the DCIV IBVGB curves are analyzed. The confident level or deviation from using the Boltzmann ionization approximation instead of the exact Fermi Deionization theory is computed. It is illustrated by a family curves that BI and FI solutions are respectively found to be nearly as good as BD and FD solutions, particularly in inversion region where deionization is less a factor. For a practical MOS transistor with VpN=200mV, Xox=35A, PAA=1018cm3, ETI=0.0eV and T=296.57K, the percentage deviation and %RMS deviation are respectively no more than 2% and 1% for metal gate devices, and 4% and 2% for silicon gate transistors when matching 90% of DCIV curves from peak current to experimental data using Boltzmann ionized approximation solutions. These results indicate that the simple and timesaving BI approximation solutions of RDCIV methodology are good enough to extract the spatial concentration profiles of the dopant impurity and interface trap at the SiO2/Si interface and the oxide thickness profile in modem MOS transistors. CHAPTER 3 RDCIV LINESHAPES FROM DISTRIBUTED ENERGY LEVELS OF INTERFACE TRAPS IN SILICON GAP 3.1 Introduction In this chapter, we analyze the effect of the energy level distribution of interface trap on the RDCIV lineshape. First, we give a review. Interface properties along the channel have dominated the electrical characteristics and performance, and reliability of MOS transistors. Due to the technological importance, extensive research efforts have been undertaken to study interfacial electronic traps at the SiO2/Si interface and to delineate their microscopic origin [56, 57]. First, we will review the history of interface traps or surface states at the interface of SiO2/Si in a MOS transistor. For a Schottly diode, the current formula is I(M/S)=I0*exp(qV/kT), where IO=A*exp(4B/kT) is dark current or saturation current. The reverse current is dependent on the work function difference between metal and semiconductor. It should be different values when using different metals. However, Mayerhof [58] in 1946 observed metal independent Schottly barrier height. In1947, John Bardeen [59] presented two models of interface trap level distribution to account for Mayerhof s results. One proposed distribution of density of interface state was UShaped that rises towards the two band edges. This is from random variations of SiO bond length and bond angles as explained by Sah [56, 57]. The second was the twolevel interface traps [59]. Twolevel interface traps are from periodic dangling silicon bond [57]. In 1948, ShockleyPearson [60] used thin film FET (Field Effect Transistor) to find a solidstate replacement of a vacuum tube. But they found no conductivity modulation in the FET. The null result was attributed to high density of interface states. High density of interface traps will pin or lock the position of the Fermi level at the surface of the thin Silicon film [56, 57, 59, 61] since band bending from the metal/semiconductor work function difference is negligible compared with that due to the high density of interface traps. So the voltage applied to the metal gate over airgap will not modulate the conductance or resistance of the thin silicon film on glass. The pinning or locking of the Fermi level to the neutral Fermi level position at the metal/semiconductor interface not only causes the experimental Schottky barrier height to differ from that calculated using the vacuum work function value of the metal but also makes the Si surface band bending or barrier height nearly independent of the type of metal or conductor used for the metal/Si Schottky diodes [61]. There was another experimental uncertainty of experimental level determined by the thermal activation (or temperature dependence) of a device current. In 1957, Sah NoyceShockey [31] used theory to fit experimental data in order to obtain the bulk trap energy level. What they found was that the trap energy levels were always near the mid gap over a small energy range for many different p/n junctions. These values are not unique since different matching points will give different energy level. In addition, what was measured was (2.9), ETI*=ETI+kTln(cns/cps), not ETI. Another historical example was reported on the uncertainty of the interface trap energy levels inl962. Sah [8] observed two discrete energy levels using recombination R DCIV methodology. However, the two levels may come from the same interface trap energy level because in a very thick oxide transistor, a nonuniform impurity concentration would shift peaked base current versus gate voltage from one into two locations. In 1971, Nishi [62] obtained discrete interface trap energy levels on large area and thick oxide using EPR (Electron Paramagnetic or Spin Resonance). The area is around one square centimeter and the oxide thickness is around one micrometer. For modem transistors, the area is much smaller than one square centimeter (lum2) and oxide thickness is much less than one micrometer (103 micrometer or Inm). Therefore, the discrete energy level obtained from EPR is not likely the interface trap in modern MOS transistors. One limitation using EPR is its lack of sensitivity, needing 10131014 spins per square centimeter to detect the signal. For modern MOS transistors with 1018cm3 impurity concentrations, 250nm of channel length and width, there are only 60 traps at 101 lcm2 or 6000 traps at 1013cm2. Therefore, it is impossible to observe the EPR signal even on the stateoftheart transistors. The RDCIV methodology has been proposed to extract device properties of deep submicron MOS transistor with spatial nanometer resolutions (or 10 atomic layers) which can not be obtained by conventional metallurgicaloptical techniques. In this novel method, the d.c. current voltage characteristics are measured and then analyzed by devicephysicsbased analytical theory to give the device and material properties. The novelty is the selection of the particular electrical characteristics which are very sensitive to the material properties in these devices, but also insensitive to multidimensional effects. The d.c. recombination current at basewell terminal, IB, is modulated by the applied gate/base voltage, VGB, in a MOS transistor. This method was used to monitor electric fieldstress generated interface traps as a transistor reliability monitor [11, 15, 26, 57] and to serve as prestress diagnostic monitor for transistor design and processing [26]. The IB modulated by gate voltage VGB arises from recombination of the majority carrier at the SiO2/Si interface traps under the gate oxide with the injected minority carriers by one or more forward biased p/n junctions (Drain/Base, Source/Base, and Substrate/Basewell) into the basewell. The RDCIV peak current IBpeak and its lineshape are highly sensitivity to the transistor design, such as channel L and width W, the spatially variation of the dopant impurity and interface trap concentrations along the SiO2/Si interface, and the profile of interface trap energy level over the silicon gap in MOS transistors. A detailed theoretical analysis on RDCIV methodology was presented in the chapter 2 for basewell channel region (BCR). The recombination at the interface traps in space charge region of source junction (SJR) and drain extension region (DER) becomes increasingly important in unstressed transistors as the channel length is scaled down and it is wellknown that recombination in SJR dominates in stressed transistors [15,10,21] regardless of the channel length [15,18]. In this chapter, Slater's perturbation theory [63] is used to explain the two models of interface trap energy distributions described by Sah [57] as shown in Figure 3.1. The energy band diagram in Fig 3.1(a) is for ideal case, zero traps at interface and in the bulk. The band diagrams in Fig 3.1(b) and Fig 3.1(c) are for bulk traps from perturbation in the silicon bulk. All the localized energy level with symmetry wave function will be pushed up when the localized perturbation from the trap potential A is positive (such as P type A=0 3.12eV Ec EG=1.12eV SiO2 Si 4 Ev 4.25eV Ev (a) Ideal zi) <0 SiO2 ^^  Ec Si ED Ev A(X2, Y2, Z2) >0 (b) Traps distributed in the Si bulk (A >0) SiO2 (c) Traps distributed in the Si bulk (A <0) A(x=0, y, zi) < A 0A S Ec(y SiO ED Si Ev(y A(x=0, Y2, Z2) >' Ev (d) 2 traps at 2 interface locations. N interface traps give UShaped DOS 0 1, Zi) 2, 2) 0 Figure 3.1 Energy distribution of Interface traps: (a) ideal case without traps, (b) traps distributed in the silicon bulk with trap potential A is positive, (c) traps distributed in the silicon bulk with trap potential A is negative, and (d) 2 traps at 2 interface locations. N traps at N interface locations give UShaped DOS. impurity). Similarly, all the localized energy level with symmetry wave function will be pushed down when the localized perturbation from the trap potential A is negative (such as N type impurity). The energy bands for antisymmetry wave function stay the same positions since the perturbation effect is cancelled after integration in space. The band diagram in Fig 3.1(d) is energy distribution for many traps at different interface locations. 2 traps at 2 interface locations give two discrete interface trap levels. N traps at N interface locations give UShaped DOS. In this model, the energy level below conduction band is acceptorlike and energy level above valence band is donorlike. The lineshape of RDCIV is primarily determined by the dopant impurity concentration and its areal profile at the SiO2/Si interface, and only secondarily determined by the areal variation of the interface trap concentration provided the impurity concentration is not a constant. The injected minority concentration at the interface gives only a small change of the lineshape for the usually encountered dopant impurity concentration profiles. However, energy distribution of interface traps is assumed at the midgap (ETI=0) in these cases. There is negligible lineshape change between the three distributions of density of interface traps: a discrete level at the midgap, a constant density of traps over the entire silicon gap, and a Ushape density of traps if we assume that the electron capture rates is equal to hole capture rate in silicon energy gap. A Ushaped density of traps in silicon gap with a Ushaped ratio of electron and holecapture rates for a constant impurity concentration profile over the channel can still broaden the lineshape, which will be shown in this chapter. Thus, lineshape, peak current IBpeak and peak gate voltage VGBpeak of RDCIV curves may give the energy distribution of interface traps. Families of base current versus gate/base voltage (IBVGB) are computed to illustrate the effects of energy level of interface traps which could extract a possible energy distribution in the silicon gap from experimental RDCIV lineshape. The potential applications from the analysis are proposed. 3.2 Effect of ratio of electron and hole capture rates at midgap trap The analytical formula were derived and described in chapter 2 for the Shockley ReadHall (SRH) steadystate recombination rate RSS at interface traps in the basewell channel region (BCR). We first examine the effect of the cns and cps on the RDCIV lineshape. In (2.7), the electron capture rate is assumed to equal to hole capture rate, i.e., cns=cps=108cm3/s, generally the capture cross section, effective mass and thermal velocity of electrons are different from those of holes. In addition, the capture cross section may vary with the velocity or kinetic energy. Thus, the cns value should be different from cps. According to (2.10) and (2.12), the peak position occurs at (2.11), ETI*=ETI+kT*ln(cns/cps). The ratio of cns/cps not only change peak current IBpeak but also shift the gate voltage at the peak VGBpeak. According to (2.11), VGBpeak is proportional to the log of the ratio of cns/cps by the term 0.5*ln(cns/cps). The VGB peak shifts 0.059V towards the accumulation region or negative VGB side and 0.059V towards the inversion region or positive VGB side when cns=100*cps and cns=0.01cps, respectively. The peak of recombination current is proportional to the product of cns and cps and inversely proportional to the ratio of cns and cps as shown in (3.1) IB peak C (CnsCps)1/2 [exp(UN) 1] 1 (3.1a) exp(UN /2) + cosh(U*, + n( s 2 cs oc (CsCps)1/2[exp(UP, /2) 1] for ET, = 0, and cs = cs (3.1b) As indicated by the formulas, the ratio of cns/cps can seriously affect the peak current IBpeak. However, this is not important because we always compare the normalized RDCIV curves with experimental data, i.e. the lineshape is what we need to care about when using RDCIV methodology. For a single interface energy level at midgap, the effect of Cns/cps ratio on the R DCIV lineshape is shown in Fig 3.1(a) and (b). The 90% peak current, which means 100% IBpeak down to 10% IBpeak, is covered by a gate voltage range from 0.1V to +0.1V in Figure 3.1(a). Using the RDCIV curve at Cns=Cps as reference, we can see in Figure 3.1(c) that the error or % deviation is less than 4% for CPN=10 or cns/cps=0.1, and 15% for 1.0 r 0.75 0.5 0.25 0.0 0.2 0.2 0.5 0.0 0.5 VGBVGBpk/(1V) Figure 3.2 Effect of ratio of electron and holecapture rates on normalized IBVGB lineshape: (a) IB vs. VGB in linear scale, (b) IB vs. VGB in semilog scale. CPN=cps/cns varies from 100 to 0.01. (c) percentage deviation and (d) %RMS deviation.Interface trap level is at midgap. 0.1 0.0 0.1 VGBVGBpk/(1V) 1 r 10 102  2 10 3 104 4 10 176 10 17" 10 1 18 10 m ii Y Q. m Mn m ii 74 103 ti.on l I  I I I I I I I I I LI boF 10 101   =CpN =CPN S10 II m 1 1 nMOST ' 10  0 Xox=35A > _2 VPN=200mV LlI 10 PAI=017ocm 3 En=0.0meV 1 0 (c)  10 1.0 0.5 0.0 0.5 1.0 VGBVGBpk/(lV) 10 I 10  >. nMOST . ) Xox=35A a RMS90 1~02 VpN=200mV o RMS75 S PA=1017cm3 RMS50 SEO.OmeV o RMS25 (d) v RMSD0 1 0 3 1 1 ,I I 1, ,I 1 1 102 10 1 10 102 Cps/Cns Figure 3.2 Continued CpN=0.01 or cns/cps=100. The %RMS deviation is around 8% for cns/Cps =100 as shown in Figure 3.1(d). While the percentage deviation and %RMS error are respectively smaller than 10% and 6% for CpN=0.1 or Cns/Cps =10. In practice, since the effective electron mass is smaller than the effective mass of hole, the Cns value may be greater than cps. Thus, the ratio of Cns/cps only gives a small change of lineshape for a single interface level at mid gap. The ratio of cns/cps at the midgap energy level could vary in a range from 0.01 to 100. According to this family figure, the ratio of cns/cps at the midgap has only a minor effect on RDCIV lineshape for a single interface energy level right at the midgap. 3.3 Effect of Distribution of Interface Trap Energy Level on RDCIV Lineshape In the preceding sections, we have already tested the effect of cns/cps ratio on R DCIV lineshape for single interface energy level at midgap. There are several possible combinations of energy dependence between density of interface traps and the ratio of cns/cps over the silicon gap: (1) a constant density of interface traps with a constant cns/cps, (2) a constant density of interface traps with a Ushaped cns/cps, (3) a Ushaped density of interface traps with a constant cns/cps, (4) a Ushaped density of interface traps with a Ushaped cns/cps. Since capture rate is a function of energy position in silicon gap, cns could be several orders greater than cps when interface energy level is close to conduction band. Similarly, cps could be several orders greater than cns when interface energy level is close to valence band. According to Slater's perturbation theory, interface trap levels are those localized energy levels with symmetry wave function in conduction and valence bands, shifted into silicon gap by localized perturbation potential. Thus, the density of interface traps near the conduction and valence bands should be greater than those at around midgap. Therefore, the combinations of energy level distribution of interface trap in (1), (2) and (3) may not be possible. The most probable combination is the last one, i.e., a Ushaped density of interface traps and a Ushaped ratio of cns/cps over the silicon gap. In this section, we then investigate the distribution of interface trap level ETI with a Ushaped cns/cps ratio in silicon gap on the RDCIV or IBVGB lineshape. Since the cns/cps ratio is a function of interface trap level, we will not study the case for a constant cns/cps ratio over the silicon gap. Before we look into the effect of energy position of interface traps, we should first give the definition of Ushaped distribution in silicon gap. For density of interface traps, a Ushape distribution has a minimum interface state density (NIT=1010cm2) at midgap (or ETI=0) and rises towards the two band edges (conduction and valence bands). Similarly, a Ushaped distribution for the ratio of electron and hole capture rates cns/cps has cns=cps=108cm3/s at midgap and rises towards the two band edges, and cns is several orders greater than cps at the edge of conduction band and cps is several orders greater than cns. Both density of interface trap states and cns/cps ratio are functions of energy position of interface traps, i.e., NIT=f(ETI) and cns/cps =f(ETI) For simplicity, we will not include the temperature effect on the two distributions in silicon gap and a normalized energy level of interface traps ETIN is introduced for this purpose. The formulae of density of interface traps, electron and hole capture rates are given N, = 1010 x cosh( ) ETIN c, = 10' x exp( ETI ), cs = 10 x exp( ET ETIN ETIN In our computations, the value of ETIN equals to 0.0625eV so that density of interface states at the two band edge is around NIT5.0*1013cm2 and the electron and hole capture rates are respectively 2.5*106 or around seven orders greater than hole and electron capture rates respectively at the edge of conduction and valence bands. In an RDCIV measurement, the contribution of each of interface trap energy level can be added to give the total contribution to recombination current IB. Computed examples are given to show the effects on the RDCIV lineshape using the following formula. q(CcnsCs)2 nW [exp(UpN) 1]N, (ET,) I2 exp(UpN / 2) cosh(Us) + cosh(U,) The interface traps are each characterized by its electron and hole capture rate coefficients, Cns and cps, and its energy level in the silicon energy gap, ETI, which is measured from the intrinsic Fermi position near the silicon midgap. These three properties define the star interface trap energy level, ETI*=ETI+kTln(cns/cps)1/2=UTI*(kT/q), at which the steadystate recombination rate peaks and begins to decrease due to the increase of the electron or hole surface concentration by the applied gate voltage, VGB. Since we don't know if the interface trap level in silicon gap is only 1 level at the midgap, it is necessary to investigate the effect of cns/cps ratio on the lineshape for multiinterface trap levels. The effect of cns/cps ratio on the RDCIV lineshape is shown in Fig 3.2(a) and (b) for a Ushaped density of interface traps and a Ushaped cns/cps ratio over the silicon gap. The ratio of CPN labeled in the figures 3.2(a) and (b) is for the midgap level. For instance, the formulas of cns and cps are changed into cns=10 10*exp(ETI/ETIN) and cps=108*exp(ETI/ETIN) for CPN=cps/cns=100, the CPN ratio at other trap levels are computed using these two formulas. The 10% peak current is covered by a gate voltage range from 0.15V to +0.15V in Figure 3.2(a). Again, using the RDCIV curve from the midgap level with cns=cps as reference, we can see in Figure 3.2(c) that percentage deviation is less than 30% for CPN=0.01 or cns/cps =100. The %RMS deviation is around 8% for cns/cps =100 as shown in Figure 3.2(d). The percentage deviation and %RMS error are respectively smaller than 10% and 4% for CPN=0.1 or cns/cps =10. Thus, the cns/cps ratio only gives a small change of lineshape for a Ushaped density of interface trap and a Ushaped cns/cps over the silicon energy gap. According to figures 3.1 and 3.2, the ratio of cns/cps has only a minor effect on R DCIV lineshape for both a single interface energy level right at the midgap and a U shaped distribution of density of interface trap with a Ushaped Cns/cps over the silicon gap. Thus, for the analysis convenience, we can assume the ratio of cns/cps equals to 1 or Cns=Cps at the midgap in the followings for the discussion of energy distribution of interface traps. For interface trap level at the edge of conduction band, electron capture and emission rates are respectively much greater than hole capture and emission rates. From (2.6), we have cn c, NsPs e seps Rss = N,, (2.6) nsNs + ens + ,sPs + eps CnsCps(NsPs ni) c=N P ) NI (3.3a) cs (N, + n,) + c,(Ps + P ) csn2 exp(UpN) Cps NIT, at the edge of CB (3.3b) Ns +n, RSSpeak epsNT exp(UpN), at the edge of CB (3.3c) RSSpeak ensNIT exp(UpN), at the edge of VB (3.3d) 1.0i 0.75 0.5 0.25 0.0 0.2 0.5 0.0 0.5 VGBVGBpk/( V) Figure 3.3 Effect of ratio of electron and holecapture rates on normalized IBVGB lineshape: (a) IB vs. VGB in linear scale, (b) IB vs. VGB in semilog scale.. (c) percentage deviation and (d) %RMS deviation. Density of interface traps is Ushaped and the ratio of cps/cns = CPN. 0.1 0.0 0.1 VGBVGBpk/(1 V) 102 10 104 10 4 10 M M O_ Q. m ii m 11 m M _ 5 LJ. o751 I 1.0 102 10 1 101 10 2 10 14 10 4 10 1 : 1 I I I I I I / .. ,s x K nMOST Xx=35A VpN=200mV PA=1017cm3 I I I I I I I I I .0 10 m s= 0 O" ) 10 2 I 10 " I "  CP oNO.L 10 50 En=Ushape NI=Ushape CO/Cp.=Ushape (c) I I I I I I I 0.5 0.0 0.5 VGBVGBpk/(1V) 10 1 1 10 Cps/Cns Figure 3.3 Continued In (3.3a) and (3.3b), nl and pi are respectively electron and hole concentrations when Fermi level EF coincides interface trap level ET. At the edge of conduction band, the product of surface electron and hole concentration is much greater than intrinsic m m 0 > iLi carrier concentration, i.e., NSPS=ni2exp(UPN)>>ni2, and cns>>cps, ens>>eps, and nl>>pl. Thus, we can ignore the term ni2 in numerator and cps(PS+pl) in denominator of in (3.3a), and equation (3.3a) can be simplified into (3.3b). Since nl is much greater than NS, NS can dropped in (3.3b) near the peak recombination current, Bpeak. Using eps=cpsnl, we have a formula of steadystate recombination rate near the peak at the edge of conduction band as shown in (3.3c). From this formula, it is obviously that the emission rate of holes dominates RSS recombination rate because it is the lowest among the four transitions as shown in Figure 2.4. Similarly, a formula RSS recombination rate near the peak at the edge of valence band can be obtained in (3.3d) using the same procedures. In this case, the emission rate of electrons dominates RSS since it is the lowest among the four transitions. According to (3.3c) and (3.3d), for a constant forward bias VPN, the contribution from a interface trap level above or below midgap may give a recombination current with sharp peak, which is dependent on the product of electron or hole emission rate (eps or ens) and density of interface states NIT at the level. Normally, the contribution from an interface level at the edge of conduction or valence bands give a RDCIV curve with a maximum flattop since the hole or electron emission rate is around seven orders smaller than that at the midgap, while the density of interface states is only three orders greater than that at the midgap. Thus, interface trap levels that can contribute a sharp peak R DCIV curve are those trap levels at around the silicon midgap. This result confirms that the most effective recombination centers are those interface traps with energy close to the midgap [31]. K m ii 1012 10 13 10 114 10 15 10 16 10 10 101 8 10 119 10 10 216 1017 101 10  1.0 0.5 0.0 0.5 VGB/(1 V) Figure 3.4 Effect of discrete and asymmetrical interface trap energy distribution on IB VGB lineshape: (a) Two interface trap energy levels ETI =0, 0.2eV. (b) Three interface trap energy levels ETI=0, 0.1, 0.2eV. (c) Eleven ETI varies from 0 to 0.5eV with a step of ETI =0.05eV. (d) Eleven ETI varies from 0 to 0.5eV with a step of ETI =0.05eV. NIT=f(ETI) and cns/cps=f(ETI). 0.5 0.0 0.5 VGB/(1V) K m II 1011 1012 I_ 4IBTOT (d) 10 nMOST NIT=f(ETI) 13 Xox35A C.,/C,=f(ET ) 1 Vp=200mV V=0.411V 1 0 P 1017cm 0.20 6 0.30 0.35 , 17 m 10 0.40 1018 " " 1019 ; /('' .. O.lO 0.50 0 4. 0 1620 0 E... 10 21 0 1.0 0.5 0.0 0.5 1.0 VGB/o(1V) 1 0 1 1 I I I I I I I I I I I I I I I I I I 1012 nMOST IBTo (c) NLT=f(ET) 13 Xox,=35A 1 3 V= ,200mV C0.1)C =f(E 14 VB=0.411V 10 Pa=10'7cm73 0.20 10150.25  10 < l r ^ 17 :   35 m 10. o  \ 21 8 0,5 10  0.40  \1 19  10   OA!9 10  e.50 1020_ ETI= 1 21 I, I, I 1.0 0.5 0.0 0.5 1.0 VGB/(1V) Figure 3.4 Continued Figures 3.3 (a) to (d) show the effect of many energy levels on the IBVGB lineshape. According to equations in (2.11) and (2.15), gate voltage at the peak current VGBpeak is proportional to the log of electron and hole capture rate ratio, cns/cps, i.e., VGBpeak loge(cns/cps). Since cns/cps ratio is a function of interface trap level, different energy position of interface traps can give different peak gate voltage as shown in Figures 3.3(a)(d). For those cns/cps ratio greater than 1 at the energy positions of interface traps above the midgap, the peak gate voltage VGBpeak will shift towards accumulation region or negative VGB side. Thus, the contribution from interface trap energy levels distributed above midgap broadens the shoulder of peak current Bpeak in accumulation side as shown in Figure 3.3(a), (b) and (c). Similarly, VGBpeak will shift towards inversion region or positive VGB side for those energy positions of interface traps below the midgap, and the contribution for each ETI broadens the shoulder of B peak in inversion side as shown in Figure 3.3(d). However, the shoulder broadening on both sides of peak current Bpeak is not exactly symmetrical as indicated by (2.16a) and (2.16b). RDCIV IBVGB lineshape is asymmetric and slightly wider on the accumulation side of the peak than on the inversion side. The difference is on the order of 0.5(VAAVSpeak)1/2(AVS/VSpeak)2, which is more pronounced in MOST with thick oxide and high surface impurity concentration since VAA = ESqPAA/(2COX2)=ESqPAAXOX2/(2sOX2). Figure 3.4 gives the effect of symmetrical interface trap energy distribution (without midgap level) on RDCIV lineshape. The effect from two discrete interface trap levels is shown in Figure 3.4(a), (b), (c) and (d), and the effect from four discrete trap levels is given in Figure 3.4(e) and (f). These symmetric interface trap energy levels symmetrically broaden the RDCIV lineshape. Once the value of normalized interface energy ETIN becomes half, or the density of interface trap NIT and Cns/cps ratio are functions of two times of interface trap level (i.e., Cns/cps =f(2ETI) and NIT=f(2ETI)), then there is a double peak IB VGB curve contributed from two interface trap levels ETI=0.05eV as shown in Figure 3.4(b). At ETI=0.05eV, the values of NIT, Cns and cps are given by NIT=1010*cosh(2*0.05/0.0625)=4.95*0100, and Cns= 10*exp(2*0.05/0.0625)=4.95*108, cps=108*exp(2*0.05/0.0625)=2.02*109. Thus, we have the ratio of cns/cps=24.53. Since the density of interface traps NIT is from the localized energy levels by the perturbation of localized potential, which is from the random variation of bond length and bond angle, NIT could be as much as five times of that at the midgap. For the cns/cps ratio, the electron and hole capture rates could have 20 times of difference at ETI=0.05eV. Therefore, it is possible to observe a double peak RDCIV curve during experimental measurements if two discrete interface trap levels are presented one above and one below the midgap as shown in Figure 3.4(b). If the density and ratio are large, of NIT=f(2ETI) and Cns/Cps=f(2ETI), for the two interface trap levels ETI=0. leV, we would have a flat top RDCIV curve as shown in Figure 3.4(d). If there are four discrete levels of interface traps in silicon energy gap, such as 0.05eV and +0. leV interface trap levels, the contribution from each trap will give a double peak RDCIV curve with symmetric broadening both in accumulation and inversion regions as shown in Figure 3.4(f). These two peaks and broadening of both shoulders signify discrete interface trap energy levels with different cns/cps ratio in silicon energy gap. However, we have not observed an RDCIV curve with a double peak in our comprehensive experimental measurements. Jin Cai [64] did observe a double peak R DCIV curve in a pMOS transistor using topemitter (TE) configuration. 101 1012 nMOST Nrr=f(ET) (a) 1013 Xox=35A/ Cn/Cp= f(En) S V,=200mV 1014 P AA=1017cm3 , 115 VFB=0.411V IBTOT S10/// 1I16 10 117 m 10 = 18 0.05 120 .05 1521 I I ,, I 1.0 0.5 0.0 0.5 1.0 VGB/( V) 12 TT 13 nMOST / /(b) X10oX=35A N=f(2ETI) 1 14 Cn/C, =f(2EI i 1 0 vm2oomV 15 PAA=1O17cm 10 VB,=0.411V S10 // \ 17 / / 119 10 20 10 2 1 I I I II 1.0 0.5 0.0 0.5 1.0 VGB/(1 V) Figure 3.5 Effect of two discrete symmetrical interface traps at ETI =+0.05eV on IB VGB lineshape: (a) NIT=f(ETI) and cns/cps =f(ETI), (b) NIT=f(2ETI) and cns/cps=f(2ETI). (c) NIT=f(ETI) and cns/cps=f(ETI), (d) NIT=f(2ETI) and cns/cps=f(2ETI). (e) NIT=f(ETI) and Cns/Cps=f(ETI), (f) NIT=f(2ETI) and Cns/Cps=f(2ETI). Temperature T=296.57K. 12 nMOST (c) 10 Xox=35A Nyrf(En) 1 0 r VN=200mV /'C f(ET) 014 PAA=10ocm' S015 VB=0.411V /IB C / i, &6 16 m 10 10 18  10 , 19.0 0.5 0.0 0.5 .0 10 0.1 vGB/(1V) 13 nMOST / / IBToT (d) 13 Xo0 x=35A NIT(2E.) 14 VPN=200mV / /n /C,,=f(2EM) 10 15 PA= 1017cm3 / \ 10 VEB=0.411V/ ' 10 I 10_ / 10198 10 1 20 " 10 1021 , I I I , 1.0 0.5 0.0 0.5 1.0 VGB/(1 V) Figure 3.5 Continued 1011 10 nMOST IBT Nrr=f(EI (e) 1013 Xox35A CJC^=/(EO 14 VpN200mV VpF=0.411V 10 \ PA=1017cm3 1 015 r / ",  16 M _ 1 l18 Ei  101 20 1021 9 I I I S1.0 0.5 0.0 0.5 1.0 VGB/(1V) 101 nMOST 0.eV  13 Xox=35A / Nf(2ETI 1 Vp=20OmV CnJCs=f(2ETI) 10 P=1on3 / VFB=0.411V ? 10 /1/ 5 SY10 ci (Y16 1 0 oo 0eV O0.05eV Y19 10 20 120 10 S1.0 0.5 0.0 0.5 1.0 VGB/(1V) Figure 3.5 Continued But the double peak curve can not indicate two discrete interface trap energy level in silicon gap since one of the peaks in the double peak curve is from increased interface trap concentration near the drain extension region (DER) of a stressed MOS transistor [26]. As indicated in (2.12b), the spatial interface trap concentration could greatly increase the shoulder amplitude to form a double peak curve for a MOS transistor with Ushaped dopant impurity concentration. Figure 3.5 shows the effect of discrete and midgap symmetrical interface trap energy distribution (with midgap) on RDCIV lineshape. As predicted by the theory in chapter 2, the peak current IBpeak occurs at the gate voltage VGBpeak or the interface or surface concentrations of electrons and holes, Ns and Ps, when cnsNs and cpsPs are equal. From the unit steadystate recombination rate (2.7a), it is evident that the lineshape is strongly affected by the emission rates of electrons and holes which in turn are dependent on the energy level position of the interface traps in the silicon gap. A more direct representations is given in (2.7b) which explicitly shows the effect of the energy level position as indicated by the term cosh(UTI*). Ii is not just the energy level position but also the electron and hole capture rate ratio as indicated by the definition of UTI*, E, = UTIkBT = [(E,E,)+ kBTln(cs /C,)] (3.4) From the base recombination current equation in (3.2), it is immediately obvious that there is a plateau in the IBVGB curves centered at the maximum whose width is proportional to ETI* as shown in Figure 3.5, such as the curves with interface trap energy level ETI=+0.45, 0.40, 0.35 and 0.30eV in Fig 3.5(c). Only when the surface energy band bending or the gate voltage is sufficiently large to make PS>(ens+eps)/cps or NS>(ens+eps)/cns that the unit steadystate recombination rate RSS1 or the basewell recombination current IB will start to decrease. For a interface trap level at midgap, (ens+eps)/(cps+cns) is about equal to intrinsic carrier concentration ni. Therefore, this corresponds to the sharp lineshape centered at the intrinsic surface condition or the subthreshold voltage. But for a shallow interface trap energy level, such as ETI=+0.4, 0.50eV, either ens or eps will be very large since they are assumed to be proportional to exp(ETI). Therefore, a much larger gate voltage VGB is necessary to increase electron or hole concentration at surface in order to reduce recombination current IB. In Figure 3.5 (a), the interface trap energy level ETI=+0.1eV symmetrically broadens the RDCIV lineshape. While ETI=+0.2eV give a broadening shoulder on both side of peak as shown in Figure 3.5(b). Figure 3.5(c) gives the contribution to total recombination recurrent IB from each interface trap energy level varying from 0.5eV to +0.5eV with a 0.05eV step. The effect of energy level number of interface traps NETIN is given in Figure 3.5(d). The contribution from less than about 11 levels of interface traps, except NETI=I at midgap ETI=0, gives an RDCIV lineshape with a hump on both shoulders as shown by these curves labeled NETI=7, 9 and 11 in Figure 3.5(d). Once NETIN is greater than 21 for the interface traps with symmetrically distributed density in Sigap, the humps disappear on the shoulders and the total contribution will give a smooth IBVGB curve, (curves labeled NETI=21, 101 and 999). Figure 3.6 shows the comparison among three distributions of interface traps in silicon gap: (1) a Ushaped DOS with NIT=1010*cosh(ETI/ETIN)Cm2, (2) a constant DOS NIT=1010cm2, and (3) a discrete interface trap energy level at midgap ETI=0. The normalized RDCIV curves are given in Figure 3.6(a) and (b) for linear scale and semilog scale. The percentage deviations using the curve with interface trap energy ETI=0as reference is shown in Figure 3.6(c), while %deviations using a constant density of interface traps as the reference is given in Figure 3.6(d). 