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A Time-base asynchronous readout CMOS image sensor

University of Florida Institutional Repository

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TABLEOFCONTENTS page ACKNOWLEDGEMENTS ::::::::::::::::::::::::::::: iii ABSTRACT ::::::::::::::::::::::::::::::::::::: vi CHAPTERS 1INTRODUCTION :::::::::::::::::::::::::::::::: 1 1.1Background.................................1 1.2Motivation..................................2 1.3Author'sContribution............................3 1.4DissertationStructure............................3 2SOLID-STATEIMAGERS ::::::::::::::::::::::::::: 5 2.1Introduction.................................5 2.2PrinciplesofSolid-StateImaging......................5 2.2.1GenerationofChargeCarriers...................5 2.2.2CollectionofGeneratedChargeCarriers..............6 2.2.3TransportationofCollectedChargeCarriers............7 2.3Charge-CoupledDevices(CCDs)......................8 2.4CMOSImageSensors............................9 2.5PerformanceLimitations..........................10 2.5.1QuantumEfciency........................10 2.5.2DarkCurrent............................11 2.5.3FixedPatternNoise(FPN).....................12 2.5.4TemporalNoise...........................12 2.5.5DynamicRange(DR).......................14 3TIME-BASEDASYNCHRONOUSREADOUTCMOSIMAGER ::::::: 15 3.1Introduction.................................15 3.2SNRandDRAnalysisofPhotodiodeCMOSAPS.............15 3.2.1SignalVoltage...........................17 3.2.2PhotonCurrentShotNoise.....................18 3.2.3DarkCurrentShotNoise......................18 3.2.4PhotodiodeResetNoise......................19 3.2.5ReadoutCircuitNoise.......................19 3.2.6Signal-Noise-Ratio(SNR).....................19 3.2.7AnExample............................19 3.3ExistingHighDynamicRangeImageSensors...............22 3.3.1NonlinearOpticalSignalCompression..............22 3.3.2Multisampling...........................23 iv

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3.3.3Time-basedHighDynamicRangeImagers............24 3.4PrinciplesofTBARCMOSImager.....................25 3.4.1HighDynamicRangeCapabilityofTBARImager........25 3.4.2AsynchronousReadout.......................32 3.5ArchitectureandOperationofTBARImagers...............34 3.5.1TBARwithon-chipMemory:TBAR MEM............34 3.5.2TBARwithouton-chipMemory:TBAR BASE..........38 3.6ErrorsAnalysisandSimulation.......................41 3.6.1ErrorsCausedbyLimitedThroughputofTBARArchitectures..42 3.6.2MATLABsimulationoferrors...................45 3.6.3TBAR BASEimagerwiththroughputcontrol...........54 3.7Summary..................................60 4TBARIMAGERCIRCUITDESIGNANDANALYSIS ::::::::::::: 62 4.1Introduction.................................62 4.2PixelDesign.................................62 4.2.1PixelOperationandDigitalControlCircuitry...........62 4.2.2PhotodiodeDesign.........................66 4.2.3ComparatorDesign.........................69 4.3AsynchronousReadoutCircuitDesign...................79 4.3.1DesignMethodology........................79 4.3.2AsynchronousCircuitDesign................... 80 4.4TimingAnalysis...............................87 4.4.1Reset................................87 4.4.2PixelsFiringSimultaneously....................88 4.4.3FiniteStateMachineModel....................92 4.5Summary..................................95 5TBARIMAGERTESTINGANDCHARACTERIZATION ::::::::::: 96 5.1Introduction.................................96 5.2TestingSetup................................97 5.3TestingandCharacterization........................99 5.3.1PowerConsumption........................99 5.3.2DarkCurrent............................100 5.3.3DynamicRange...........................101 5.3.4TemporalNoise...........................103 5.3.5ConversionGain..........................105 5.3.6FixedPatternNoise.........................109 5.4Summary..................................110 6CONCLUSION ::::::::::::::::::::::::::::::::: 113 6.1Summary..................................113 6.2FutureDirections..............................114 REFERENCES ::::::::::::::::::::::::::::::::::: 115 BIOGRAPHICALSKETCH :::::::::::::::::::::::::::: 119 v

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(2.1)whereEistheenergyofaphoton,hisPlanck'sconstant(6:631034Js),isfrequency,cisthespeedoflight(3:01010cm=s)andisthewavelengthofthephoton.Tobeabletogenerateelectron-holepairsinsemiconductors,theenergyofphotonsmustbegreaterthanthebandgapenergyofthesemiconductor.Forsilicon,thebandgap5

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=Eg(2.2)=hc Eg1120nm(2.3)whichisintheinfraredregion.Thewavelengthofvisiblelightrangesfromabout350nmto750nm[11].Thus,siliconisasemiconductorcapableofthevisiblelightimaging,althoughsometimesacolorcompensatinglterisusedtoeliminateinfraredwavelength(e.g.,seepage98ofBlanksby[12]).2.2.2CollectionofGeneratedChargeCarriersOnceelectron-holepairsaregenerated,anappliedelectriceldseparateselectronsandholes.Otherwise,electronsandholeswilleventuallyrecombine.Ontheotherhand,sinceitisverydifculttomeasureasingleelectronorhole,abetterwayistointegratechargecarriersintoachargepacketoveracertainperiodoftime.Bothseparationandintegrationofchargescanbedonewithacapacitor.Twotypesofcapacitorsarecommonlyused:MOScapacitorsandmetallurgicalp/njunctioncapaci-tors.MOScapacitorsareusedinCCDsandphotogateCMOSimagerswhilemetallurgicalcapacitorsareusedinphotodiodeCMOSimagers.Figure2.1(a)showsaMOScapaci-tor.Ifthegatevoltageishighenough,thereisadepletionregionunderthegate.Thephoton-generatedelectronswillbeswepttowardsandstoredattheSiSiO2interface.InFigure2.1(b),thep/njunctionisprechargedtosomepositivevoltagerelativetothesub-strate.Whenphoton-generatedelectronsareswepttowardsn-type-silicon,thep/njunctionisdischargedandVnbeginstodrop.Notetherearealsoelectron-holepairsgeneratedintheneutralbulkofthesemicon-ductormaterial.Someofthesecarrierscanbecollectedviadiffusion.Theefciencyofthisprocessdependsonthewavelengthoftheimpinginglightandthediffusionlengthofthe

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Figure2.1:Chargecarriersgenerationandintegrationinsilicon.semiconductormaterial.DetailedanalysisofchargegenerationcanbefoundinChapter5ofTheuwissen[1].2.2.3TransportationofCollectedChargeCarriersSincetheamountofchargeisproportionaltotheilluminancelevelforagivenchargecollectiontime,afterthechargecarriersarecollected,theilluminationinformationisstoredinachargepacket.Thenextstepistosendthisinformationoutformeasurementorprocessing.Sincethereareusuallymorethanthousandsofchargepackets(pixels)onanimagesensor,efcientlytransportingtheinformationinthesepacketsisasignicantissue.Therearetwoprimaryapproachestoreadingoffthemanychargepackets.Oneistosendthechargepacketsoutserially,asisdoneinashiftregister.Thisistheprincipleofcharge-coupleddevices(CCDs).CMOSimagesensorsadoptaquitedifferentapproach.Here,theinformationinthechargepacketsismultiplexedontoasensinglinethatissharedbymanypixels.ThedetailedoperationsofCCDsandCMOSimagerswillbediscussedinthenexttwosections.

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Figure2.2:ReadoutstructureofCCD.Sinceachargepackethastoundergohundredsoftransfersbeforeitcanreachtheoutputsite,thetransportationmustbenearlyperfectbetweentwoadjacentMOScapaci-tors.IfthechargetransportefciencyisdenedasthepartofachargepackettransportedthroughaCCDcell,normalizedtotheoriginalchargepacketthathadtobetransported,thechargetransportefciencyhastobeverycloseto1foraproperlyworkingCCD.Tounderstandwhythisistrue,ifthechargetransportationefciencyisonly99%andthereare500CCDcells,only0:66%oforiginalchargecarrierswillreachthereadoutsite.ThenearlyperfectchargetransportationrequirementmakesthetechnologyforCCDssomewhatmorecomplicated.Thecomplexityisaresultoftherelativelylargenumberoftechnologicalstepsandtheconsecutiverelativelylargethroughputtimeintheproductionfacilities[1].Asaresult,CCDtechnologyismorecostlythanCMOStechnol-ogy.Furthermore,toprovidenearlyperfectchargetransportation,propertimingiscrucial.ManyCCDsuseseveraldifferentsupplyvoltagefortimingclocks,whichaddsfurthersystemcomplexity.

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Select mishigh),theMOSswitchesassociatedwitheachpixelareturnedon.Allthepixelsintheselectedrowwillputtheirinformationonthecorrespondingcolumnline.Theinformationoneachcolumnlineisthenprocessedbysample-and-holdandothersignalprocessingcircuitsassociatedwitheachcolumn.Thecolumndecoderisusedtoselectwhichcolumntooutput. Figure2.3:ReadoutarchitectureofCMOSaddressableimagesensor.NoteinFigure2.3,acolumnlineissharedbymanypixelsinthesamecolumn.Theparasiticcapacitanceonthiscolumnlineismuchlargerthanthephoton-sensingcapacitorinsideeachpixel.Todealwiththisproblem,usuallyabufferisaddedintoeachpixel.Thesekindofsensorsarethereforecalledactivepixelsensors(APS).

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Figure2.4:PixelschematicofaphotodiodeAPS.OneofthecommonlyusedAPSarchitecturesisthephotodiodeAPS[5].TheschematicofapixelisshowninFigure2.4.ThereareaphotodiodeandthreeMOStran-sistorsinsideeachpixel.ResettransistorM1isusedtoprechargethephotodiode.M2isavoltagefollower,actingasabufferbetweenthesmallcapacitanceofthephotodiodeandthelargecapacitanceofthecolumnline.M3isaswitchtoselectthepixel.ArguablythebiggestadvantageofCMOSimagesensorsistheircapabilityofinte-gratingmanycircuitsontothesamechip.CCDimagersusuallyconsistofseveralchipsforreadoutamplication,timingcontrol,analog-to-digitalconversionandsignalprocessing.Asaresult,systemcomplexityandcostareincreased.Onthecontrary,itisquiteeasytointegrateallthesefunctionsontothesamechipforCMOSimagesensorsbyusingstandardCMOStechnology.2.5PerformanceLimitationsToproperlydesignasolid-stateimager,itisveryimportanttounderstandperfor-mancelimitations,whichprimarilyincludequantumefciency,darkcurrent,xedpatternnoise(FPN),temporalnoiseanddynamicrange.2.5.1QuantumEfciencyQuantumefciencyisdenedasthenumberofcollectedelectronsdividedbythenumberofphotonsimpingingonthedevice.Sincenoteveryphotoncangeneratean

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C=p C(2.7)

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q=p q(2.8)ReadoutCircuitNoise.Toconvertphotongeneratedchargecarriersintoameasurableelectricvoltageandcurrentandtobuffersignalstotheoutsideworld,bothCCDsandCMOSimagersneedreadoutcircuits.Readoutcircuitswillinevitablyintroducenoiseduetothethermalnoiseand1=fnoiseofMOStransistors.2.5.5DynamicRange(DR)Dynamicrange(DR)isanotherimportantperformancecriterion.Itisdenedastheratioofthemaximummeasurablesignal(saturationlevel)tothenoiseoor.ThesaturationlevelofCCDsisusuallylimitedbythechargewellcapacity,whilethesaturationlevelofCMOSimagersislimitedbythepowersupplyvoltage.Thenoiseooristhetotalnoisewhenthereisnosignal.Itconsistsofdarkcurrentshotnoise,resetKTCnoiseandreadoutcircuitnoise.Becausethesethreenoisesourcesareindependentinnature,thenoiseoorinnumberofelectronscanbeexpressedasnfloor=q

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Figure3.1:SchematicofPhotodiodeActivePixelSensor(APS).AsexplainedinChapter2,SNRcanbedenedasSNR=10logv2sig

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683 683 683 qL(3.6)

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Cph(3.11)=p Cph(3.12)3.2.3DarkCurrentShotNoiseThedarkcurrentofapixelIdark=JdarkA(3.13)FromEquation2.5,darkcurrentshotnoiseisvdark=p

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Cph(3.15)3.2.5ReadoutCircuitNoiseReadoutnoiseisthetotalthermaland1=fnoiseofM1,M2andM4,plusthenoisefromtheanalogsignalprocessingandADCcircuits[20].ThedetailedanalysisofreadoutnoisehasbeendonebyDegerlietal.[21].3.2.6Signal-Noise-Ratio(SNR)ThefullexpressionforSNRcannowbewrittenasSNR=10logv2sig C2ph+qJdarkATint Cph+v2read(3.17)3.2.7AnExampleInordertodemonstratetherelativeimportanceofvariousnoisesourcesandSNR,thedataofatypicalphotodiodeimagerareusedhereasanexample:ACMOSimagerimplementedusingAMI0.5mtechnologywith:Photosensitiveareaofphotodiode:A=14m2.Quantumefciency:=0:4,at=0:555m.MeandarkcurrentJdark=1nA=cm2.IntegrationtimeTint=30ms.TotalcapacitanceatthecathodeofthephotodiodeCph=5fF.Signalsaturationvoltage:vsig;max=1V.

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Figure3.2:Photocurrentanddarkcurrentasafunctionofilluminance.InFigure3.3,signal,varioussourcesofnoiseandtotalnoise(inVolts)areshown.Inthelowlightregion,KTCresetnoiseisthedominantnoisesource.Asilluminancelevel

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Figure3.3:Signalandtemporalnoiseasafunctionofilluminance.increases,photocurrentshotnoisebecomesmoreandmoreimportant.Alsothenoiseoorcanbeeasilycalculatedasvfloor=q

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Figure3.4:Relationshipofphotodiodevoltageandsignalvoltage.AsshowninFigure3.5,sincethephotodiodesinmostCMOSimagersoperateinintegrationmode,thesignallevelofeachphotodiodeincreaseswithtimeataratepropor-tionaltotheilluminanceonthatphotodiode.Afterapre-determinedexposuretime(whichisthesameforallpixels),theanalogsignallevelacrosseachphotodiodeisreadout.InFigure3.5,thesignalsaturationlevelis1Vandphotodiodenoiseooris0.97mV(seeEquation3.18).IfwextheexposuretimeforallpixelsandassumethattheminimumacceptableSNRis1(0dB),themaximumdynamicrangeisabout60dB(20log(1V=0:97mV)),nomatterwhichintegrationtimeischosen.Forexample,iftheintegrationtimeissettobe14s,informationforpixelswithilluminancebelow100luxandabove105luxislost.Whiletheintegrationtimecanbeincreasedto14mstocapturetheinformationofpixelswithilluminanceaslowas0:1lux,pixelswithilluminanceabove100luxareallsaturated,andtheopticalDRisstill60dB.AsanexampletoillustratehowtheTBARimagerachievesahighdynamicrange,considerthesituationinFigure3.6.InFigure3.6(a),fourpixelsarelocatedataddresses

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Figure3.5:Theresponseoftypicalphotodiodesundervariousilluminanceforconven-tionalCMOSimagers.(m1;n1);(m2;n2);(m3;n3)and(m4;n4),withilluminanceofL1;L2;L3andL0,respec-tively.Insteadofreadingouttheanalogvoltageacrosseachphotodiodeatapredeterminedexposuretime,thereisacomparatorinsideeachpixel.WhenthevoltageonaphotodiodeVphdropsbelowaglobalreferencevoltageVref(orequivalently,whensignalvoltagerisesaboveaglobalsignalreferenceVsig;ref),thecomparatorinverts,andthepixelgeneratesapulse(i.e.,ithasred),asshowninFig.3.6(b).Afterapixelhasred,itisdisabledfortherestoftheframe.Thetimeatwhichapixelresisuniquelydeterminedbytheilluminanceonthatpixel.Forexample,iftheilluminanceLkatapixelisktimeslargerthantheunitilluminanceL0,thesignalvoltageisproportionaltotheintegrationtimeandilluminanceuntilsaturation:

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Figure3.6:SchemeforTBARimager.Vsig=STintL(3.21)whereSisthesensitivity(V=(luxsecond))ofthephotodiodeopticalresponse.TheintegrationtimetkforpixelwithilluminanceLkistk=Vsig;ref

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C2ph+qJdarkATint Cph+v2read(3.28)Sincethephotocurrentshotnoise(innumberofelectrons)isproportionaltothesquarerootofthesignal(innumberofelectrons)asinEquation3.10,thephotocurrentshotnoiseisthedominantnoisesourceduringmoderateorhighlightsituations(whichisobviousfromFigure3.3).Equation3.28canbeapproximatedasSNR10log(min(v0sig;vsig;max))2 C2ph=10logCphVsig

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Figure3.7:Varyingreferencevoltageforawiderdynamicrangeinvideomode.Toillustratethisidea,considertheexampleinFigure3.7.IftheframetimeisTframeandthereferencesignalvoltageiskeptconstantatVsig;ref,anypixelwithillumi-nancebelowL3doesnotrewithinTframe,sotheimagercannotprocessandoutputvaliddataaboutthosepixels.However,ifthereferencevoltageissweptasshown,pixelswithilluminancebelowL3(suchasL4)willrebytheendoftheframe,sotheimagercanout-putdata(pixelringtimesandaddresses)that,alongwiththeknownreferencevoltageat

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MEMandTBAR BASE.Unlikemostdigitalcircuitsinusetoday,thereadoutcircuitofTBARimagersoperateasynchronously.Asynchronouscircuitshavethepotentialtoachievehigherspeed,lowerpower,improvednoiseandelectromagneticcompatibility(EMC),althoughthedesignofasynchronouscon-trolcircuitsisdifcultanderrorprone[41].Also,theprotocolofreadoutcircuitsaredata

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MEMandTBAR BASE,aredescribedatthesystemlevel.Detailedanalysisofeachcircuitcomponentwillbepresentedinthenextchapter.3.5.1TBARwithon-chipMemory:TBAR MEM MEM:ATBARimagerwithon-chipmemory.TheblockdiagramoftheTBAR MEMimagesensorisshowninFigure3.8.AnMNpixelarrayislocatedinthecenteroftheimager.Insideeachpixel,thereisaphotodiodewithresettransistor,acomparatorwithanautozerocircuittocanceltheoffset(notshown),andapixelcontrollogicblock.Onthelefthandsideoftheimager,thereis

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MEMisacolumn-wiseADC.AlthoughthethroughputofTBAR MEMisnotashighasthatofAndohetal.[40],thereisnoneedtoputadigitalcounterandmemoryinsideeachpixel,andasaresult,thenumberoftransistorsinsideeachpixelisdramaticallyreduced.TheTBAR MEMoperatesasfollows:1.Whenthevoltageacrossapixel'sphotodiodedropsbelowthecomparator'sreferencevoltage,thepixelmakesarowrequestbypullingdowntheRow request1line,whichissharedbyallpixelsinthesamerow.2.WhenthereisatleastoneactiveRow requestsignal,twothingshappen.First,thedigitalcounterdataareputintotheRowRequestMemoryatthepositionswhereRow requestareeffective.Thesearetherecordedringtimetobesavedintheframememory.Secondly,therowarbiterchoosesoneandonlyonerowbymakingthecorre-spondingRow selsignaleffective.3.Row selsignalplaystworoles.Inadditiontoselectingarowofpixels,therowarbiter'sRow selsignalalsoselectsthecorrespondingrowintheframememory.Then,thepixelsintheselectedrowthathaveredwillsendoutcolumnrequestsignals(inparallel)thatselectthecorrespondingcolumnsintheframememory.Nowthattheframememory'srowandcolumnaddresseshavebeenselected,thecountervalue(storedaftertherowrequest)isloadedtothoseaddresses.4.Afternishingon-chipmemorywriting,TBAR MEMcontrolcircuitsendsasignalMemoryWriteDonebacktothepixelarray.TogetherwiththeRow Selsignal,MemoryWriteDonedisablesthepixelswhichhasbeenwrittentotheon-chipframememory.Consequently,thesepixelswithdrawtheirRow requestsignal.Uptothispoint,TBAR MEMnishesareadoutcycle.Therowarbiterisallowedtoselectanewrowtocontinueanothercycle.ItisimportanttocalculatethethroughputoftheTBAR MEMimager.Thethrough-putisdenedhereasthenumberofpixelstheimagercanoutputpersecond.Fromthe

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MEMdescribedabove,thethroughputturnsouttobeimagedepen-dent.Todemonstratethispoint,assumewehaveanMNTBAR MEMimager.Ifallofthepixelsareringcloselyintime,duringoneframememorywritingoperation,Npixelscanbereadout.Throughputishighinthissituation.Onthecontrary,ifthepixelarrayressparsely,theremaybeonlyonepixelbeingreadoutduringoneframememorywritingoperation.Thiscorrespondstoalowthroughput.Thus,boththelowestandthehighestthroughputcasesneedtobeconsidered.FromtheoperationoftheTBAR MEMimager,thetimeofonereadoutcycleisTcycle=max(Trow memory;Trow arbiter+Tcol request)+Tframe memory+Tpixel disable(3.30)where:Trow memory:thetimedelayofwritingrowrequestmemory.Trow arbiter:thetimedelayofrowarbiterchoosingonerow.Tcol request:thetimedelayofpixelssendingcolumnrequestsignalstotheon-chipframememory.Tframe memory:thetimedelayofwritingon-chipframememory.Tpixel disable:thetimedelayofdisablingpixelswhichhavealreadybeenreadout.Sincerowmemorywritingoccursinparallelwithrowarbitrationandcolumnre-quest,theirdelaysdonotsum.Alsonotethattherowrequesttimeisnotincludedbecausethecyclestartsandendsatrowarbitration.Atthispoint,rowrequesthasalreadynished.ThethroughputofanMN(M=128andN=128inthisexample)TBAR MEMimagerusingAMI0.5mCMOStechnologycanbeestimatedfromCADENCESpectreSsimulations.SinceitisimpossibletosimulatesuchabigarrayinCADENCE,inordertoestimatetimedelays,simulationwasdoneona44arraywiththeparasiticcapacitance

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requestandTpixel disableare3nsand3.7ns,respectively.Theaccesstimeofstate-of-the-artembedded-SRAMislessthan2ns[42].Ifaconservativeaccesstimeof5nsisusedinEquation:3.30,thecycletimeofTBAR MEMisTcycle=max(5;2+3)+5+3:7=13:7nsThehighestandlowestthroughputcanthenbecalculatedusingthecycletime.ThehighestcycletimehappenswhenNpixelsarereadoutduringoneon-chipframememorywriting:Throughputmax=N Tcycle=128 13:7ns=9:34Gpixels=s(3.31)Thelowestthroughputhappenswhenonlyonepixelisreadoutduringoneon-chipframememorywriting:Throughputmin=1 13:7ns=73:0Mpixels=s(3.32)Itisalsointerestingtondouthowmuchtimeittakestoreadoutoneframeofa128128scene:Tmin=128128

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MEMisquitehigh(9.34Gpixels/sforanarraybuiltina0.5mCMOStechnology).However,thisisnotquitefeasibleforouruniversityresearchprojectbecauseitistobefabricatedthroughaneducationalMOSISprocess,whichlimitedustocertainprocessesandchipareas.Therefore,anotherTBARarchitecture,TBAR BASE,isproposedtogetridofon-chipmemory,althoughattheexpenseoflessthroughput.Thisarchitecturewillbediscussednext.3.5.2TBARwithouton-chipMemory:TBAR BASEInthissection,theoperationofaTBAR BASEimagerisdescribedatthesystemlevel.Thethroughputofthisarchitectureiscalculated.A3232versionofthisarchi-tecturehasbeensuccessfullyimplementedandtestedbytheauthor.Adetailedanalysisofeachcircuitcomponentwillbepresentedinthenextchapter. Figure3.9:TBAR BASEimagerblockdiagram.TheblockdiagramofaTBAR BASEimagerisshowninFigure3.9.AswiththeTBAR MEM,eachpixelcontainsaphotodiode,acomparator(withanautozerocircuitto

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BASEreadsoutpixels.Inordertoincreasethespeedatwhichtheimagercanoutputpulseeventsandthecorrespondingpixeladdresses,allcircuitsoperateasynchronouslywithoutaglobalclock.Alsothereisacounteroutputtingtimeinformation.TheTBAR BASEimageroperatesasfollows:1.Whenthevoltageacrossapixel'sphotodiodedropsbelowthecomparator'sreferencevoltage,thepixelmakesarowrequestbypullingdowntheRow requestline,whichissharedbyallpixelsinthesamerow.2.Therowarbiterrandomlyselectsarowthatismakingarowrequest.Thisrow'saddressisstoredbyarowaddressencoder.3.WhentherowarbiterselectsarowwiththeRow selectline,thepixelsthathaveredinthatrowareallowedtomakecolumnrequestsbypullingdowntheCol requestline,whichissharedbyallpixelsinthesamecolumn.4.Thepixelsintheselectedrowthataremakingcolumnrequestsputtheirringstatesintothelatchcells.5.Oncethecolumnrequestsarelatched,thepixelsintheselectedrowthathadbeenmakingcolumnrequestsaredisabledfromringagainfortherestoftheframebythesepixels'pixelcontrolblock.Asaresult,Row requestfromthisrowiswithdrawn.Afterthat,ifthereareothervalidRow requestsignals,newrowarbitrationisallowedtostarttakingplace.However,therowinterfacecircuitpreventsanewRow selectuntilallvaliddatainsidelatchcellshavebeenprocessed.Columnarbitrationbeginsontherequestsinthecolumnlatchcells.Notethatthethroughputcontrolcircuitcancontrolthecolumnarbitrationspeed.6.Duringcolumnarbitration,thecolumnarbiterrandomlyandsequentiallyselectsthelatchedcolumnrequests.Whenacolumnisselected,itsaddress,thelatchedrowaddress,andthetimearereadout.Thetimerepresentsinformationabouteachpixel'silluminance.7.Oncecolumnarbitrationiscomplete,i.e.,allvaliddatainsidethelatcheshavebeenprocessed,therowinterfacecircuitallowsanewRow selctsignalisvalid.Uptothispoint,areadoutcycleisnished.Afterareceiver(DSP,PC,orASIC)receiveseverypixel'sringtimeinformation(fromthecounter)andtheircorrespondingaddresses,thepixel'silluminancecanbefound

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MEMimager,wecanestimatethethroughputofa128128TBAR BASEimager.AssumeI/OcircuitsofaTBAR BASEimagerdonotputalimitonthroughput,foraMNTBAR BASEimager,thesmallestandlargestcycletimesareTmincycle=Trow arbiter+Tcol request+N(Tcol arbiter+Tcol encoder)+Trow interface arbiter+Tcol request+Tcol arbiter+Tcol encoder+Trow interface(3.36)whereTcol encoder:thetimedelayforcolumnaddressencoding.Trow interface:thetimedelayfromnishingdatainlatchestoallowinganewrow select.Trow arbiter,Tcol requestandTcol arbiter:sameasdenitionsappearedintheTB-AR MEMthroughputcalculation.Wecalculatedthethroughputofa128128TBAR BASEimagerusingthetimedelayinformationextractedfromCADENCESpectreSsimulations.Trow arbiter,Tcol request,Tcol encoderandTrow interface,are2ns,3ns,2nsand3.7ns,respectively.Thecolumnarbitertimeisdesignedtobecontrollable.Ifitisfreerunning(i.e.,thethrough-putcontrolcircuitdoesnotputalimitationonthroughput),theaverageTcol arbiteris2ns.Thesenumbersgivethefollowingcycletime:

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1284:07nsTmaxcycle=2:5+3+2+2+3:7=13:2nsThecorrespondingthroughputisThroughputmax=1 4:07ns=245:7Mpixels=s(3.37)Throughputmin=1 13:2ns=75:8Mpixels=s(3.38)ComparedwiththethroughputoftheTBAR MEMarchitecture,theminimumthroughputisslightlybetter,whilethemaximumthroughputismuchsmaller.Thisisbecausetheparallelwritingtoon-chipframememoryofTBAR MEMdoesnottakeextratime,whileinTBAR BASE,readingoutdatainlatchcellsmustgothroughalongse-quentialcolumnarbitrationprocess.Thetimeittakestoreadoutoneframeofa128128scenebytheTBAR BASEimager:Tmin=128128 MEMandTBAR BASE,areproposedandtheirthroughputiscalculated.Inthissection,errorscausedbylimited

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MEMandTBAR BASEimagers.Thesesimulatorsarequiteusefulbecausetheyquantifytheerrorsforreal-worldhighdynamicrangeimages.Simulationresultsoffourhighdynamicrangeimagesarepresented.3.6.1ErrorsCausedbyLimitedThroughputofTBARArchitecturesAsdiscussedinthelastsection,oneissuewiththeTBARarchitectureisthesit-uationwhenmanypixelsareringcloselyintime.Duetothelimitedthroughputofthereadoutcircuits,TBARimagersareunabletoreadoutpixelringsinrealtime.Therefore,thereadouttimemayhavesomedelayrelativetotherealringtime.Errorsareintroducedwhenpostprocessorsreconstructimagesusingthereadouttime,insteadofthetrueringtime.TheabovesituationcanbeshowninFigure3.10usingtheTBAR BASEarchi-tectureasanexample,wherea33pixelarrayisunderexactlythesameilluminanceL.AlthoughthosepixelsreatexactlythesametimeT(assumingnomismatchbetweenthesepixels),theircorrespondingoutputaddresspulsesoccuratdifferenttimes(fromt1tot9)duetothefactthataTBAR BASEimagercanonlyoutputonepixeladdressatatime.ThedifferenceintimedependsonhowfasttheTBAR BASEimagercanoutputthesepulses,i.e.thethroughputofTBAR BASEimager.InsteadofusingtimepositionTforallpixels,thereceiverwillhavetouset1;t2;:::;t9toreconstructtheoriginalimage.Sincethetemporalpositionoftheaddresspulsesrepresentsilluminance,someerrorsareintroduced.Thereconstructedimagewillobviouslybenonuniform.FromEquation:3.21,thetrueilluminanceforthesepixelsisL=Vsig;ref

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Figure3.10:Errorsintroducedbyuniformilluminanceona33pixelarrayofTBAR BASEimager.TherelativeerrorsintroducedareError=L^Lk tk=t T+t(3.43)wheret=tkTisdenedasthetimedelayoftheoutputpulses.FromEquation3.43,iftheTBARimagershaveahighthroughput,whichmeansasmallert,theerrorwouldbesmaller.Also,forthesametimedelayt,errorsaremoresevereforhighilluminancepixels,wheretheringtimeTissmall.FortheTBAR MEMimager,errorscausedbyuniformilluminationdonotexist.Thisisbecausetherowrequestmemorycanrecordtheringtimecorrectly.However,ifalotofpixelsareunderveryclose,butnotexactlysame,illumination,someerrorswillstillexistduetothelimitedthroughput.

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MEMarchitecture,forexample),oratthecircuitlevel.Generally,itisdifculttogivepreciseanalyticalresultsoftheamountoferrorsbecauseitisscenedependent.However,aworstcasesituationfortheTBAR BASEimagercanbeanalyzedhere.ForaTBAR BASEarchitectureshowninFigure3.9,theworstcaseoftimedelayforHDRimageswithasizeof128128canbecalculatedusingthefollowingassumptions:5%ofpixelsareunderexactlythesameilluminance.Afteranalyzingseven8-bit,grayscaleimagesinMATLAB,wefoundthattherewereatmost4%ofpixelsun-deruniformillumination.However,wemustrememberthattheseimagesare8-bitquantizedversionsoforiginalscenes.Itisreasonabletoassumethatquantizationer-rorsanddynamicrangelimitationsinthe8-bitimagesinatetheamountofuniformillumination.Thus,5%uniformilluminanceshouldbeasafeworstcaseforHDRimages.Thetimeinterval(t1inFigure3.10)oftwoadjacentoutputaddresseswhichbelongtotwopixelsinthesamerowunderuniformilluminanceis2.5ns.t1isduetothetimeneededforcolumnarbitration.Thetimeinterval(t2inFigure3.10)oftwoadjacentoutputaddresseswhichbelongtotwopixelsindifferentrowsunderuniformilluminanceisabout11ns.t2isduetothetimeneededfordisablingpixels,rowarbitrationandlatchingthecolumnrequest.ThisdelayinformationcomesfromaCADENCESpectreScircuitsimulationshowninFigure3.11.Onceagain,the

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BASEarchi-tecture.Ifweassumethelongestringtimeis20seconds(limitedbythedarkcurrent),thiswillgiveadynamicrangeof135dB.3.6.2MATLABsimulationoferrorsInthissubsection,MATLABsimulatorsarebuilttosimulateTBAR MEMandTBAR BASEatthesystemlevel.Thesesimulatorsturnouttobeveryusefulbecausetheycanpredicttheperformanceofimagersforagivencircuitarchitectureandspeed.Simulationsareperformedtoshowtheamountoferrorsforafewhighdynamicrange(HDR)imageswithdifferentsizes(160180and480720)usingbothTBAR MEMandTBAR BASEarchitectures.

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Figure3.12:ReferencevoltageofTBARimagersimulators.Aftereachpixel'sphotocurrentisdecided,itsringtimecanbecomputedas:t=8><>:2C Isecond:0
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MEMare:Timedelayfromapixelringtomakingarowrequest:1ns.Accesstimeofrowrequestmemoryandframememory:5ns.Averagetimedelayofarowarbitration:2ns.Timedelayfromrowselectiontocol request:3ns.Timedelayfromnishingthelatcheddatatothenextrow select:3.7ns.ThetimedelaysofTBAR BASE(freerunningmode)are:Timedelayfromapixelringtomakingarowrequest:1ns.Timedelayofarowarbitration2ns.Timedelayofacolumnarbitration2ns.Timedelayfromrowselectiontooutputapulse:3ns.Timedelayofcolumnencoder:2ns.Timedelayfromnishingthelatcheddatatothenextrow select:3.7ns.Beforeshowingsimulationresultsofrealhighdynamicrangeimages,itisinter-estingtolookateffectsoflimitedthroughputonimageswithlargeuniformilluminationareas.Figure3.13isascenewith4uniformlyilluminatedareas.Theyhavephotocurrentsequivalentto4,16,64and255timesthedarkcurrent.Figure3.14(a)(b)showthere-constructedimagesusingTBAR MEMsimulator.Thereisnoerrorinthiscase.ThisisbecausetherowrequestmemoryofTBAR MEMcanaccuratelyrecordtheringtimes.However,ifthesceneilluminationisveryclose,butnotperfectlyuniform,therearestill

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BASEsimu-lator.Wecanseethatduetothelimitedthroughput,thereconstructedimagehasrandomhorizontalbands. Figure3.13:A128128scene,`squares',withuniformilluminationarea.ThefollowingMATLABsimulationsareperformedtoshowtheamountoferrorsforfourhighdynamicrange(HDR)images.Theoriginalimageshaveasizeof480720pixels.TheseimagesaresubsampledtogetHDRimageswithsizeof160180,whichisslightlylargerthanthesizeofQCIF(144176)imageformat.QCIFisaboutthesizeoftheimagesusedforhand-heldPDAandvideophones.ThesefourHDRimagesusedintheMATLABsimulatorscomefromPaulDebevec'sgraphicsresearchgroupattheUniversityofSouthernCalifornia[43].Theyarenave,groveC,rosetteandvinesunset.Thesefourimagesareofoating-pointrepresentationandhaveadynamicrangefrom88dBto168dB.Aftersubsamplingtoasizeof160180,thereareslightchangestoDR.ThenumericalvaluesanddynamicrangesoftheseimagesareshowninTable3.1:ThesefourimagesarealsodisplayedinFigure3.15andFigure3.16.SinceMAT-LABcanonlydisplay8-bit(48dB)image,inordertodisplaythesehighdynamicrangeimages,twoguresareusedtodisplayoneimage.Themeanrelativeerrorsbetweentheoriginalimagesandthereconstructedimagesoffour160180andfour480720HDRimagesusingtheTBAR MEMarchitecture

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(a)(b) (c)(d)Figure3.14:Reconstructed`squares'.(a)UsingtheTBAR MEM(normaldisplay).(b)10Xbrightertoexaggerateerrors.(c)UsingtheTBAR BASE(normaldisplay).(d)10Xbrightertoexaggerateerrors.areshowninTable3.2.TheerrorsintroducedbyTBAR BASEarchitectureareshowninTable3.3.Tohaveanideaofhowsignicanttheseerrorsare,oneofthereconstructedim-ageswithhighestmeanrelativeerror(0.378%),rosetteofTBAR BASE,isdisplayedinFigure3.17.ThereisnorecognizabledifferencefromFigure3.16(a)(b).Also,tocomparewithothernoisesources,thenoise(error)causedbythephotocurrentshotnoisealoneofthelenaimage,showninFigure3.18(a),iscomputedusingEquation3.12.Itgivesameanrelativeerrorof0.9%.ThelenaimagewithphotocurrentshotnoiseisdisplayedinFigure3.18(b).

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Imageswithasizeof480720 nave groveC rosette vinesunset MinimumValue 168 124 130 88 Imageswithasizeof160180 nave groveC rosette vinesunset MinimumValue 164 115 129 86 Table3.2:ThemeanrelativeerrorsintroducedbyTBAR MEMoffourHDRimageswithsizesof160180and480720. Imageswithasizeof160180 ImageName nave groveC rosette vinesunset MeanRelativeError ImageName nave groveC rosette vinesunset MeanRelativeError MEMandTBAR BASEarenegligibleforthesefourHDRimages,comparedwiththephotocurrentshotnoiseandthexedpatternnoise(FPN).Thephotocurrentshotnoisealonewillcauseameanrelativeerrorof0.9%forthelenaimage.TheFPNistypically0.2%ofthesaturationlevel[16].ThemeanrelativeerrorcausedbytheFPNisevenhigherbecausenotallpixelshaveasignallevelclosetothesaturationlevel.Thelargertheimagesize,themoresignicanttheerrorsare.Thisisnotsurpris-ingbecausetheprobabilityofcollisionishigherforlargerimagesize.Fromthesimulationresults,however,theerrorsarenegligibleforimagesizesupto480720.

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(a)(b) (c)(d)Figure3.15:ImagesnaveandgroveC.(a)nave(brightpart).(b)nave(darkpart:100brighterfordisplay).(c)groveC(brightpart).(d)groveC(darkpart:20brighterfordisplay).TheerrorscausedbyTBARimagersareimagedependent.TheTBAR MEMarchitecturesuffersfewererrorsthantheTBAR BASE,thankstoitsparallelwritingon-chipframememory.Inthelastsection,wecomputedthethroughputoftheTBAR MEMandtheTBAR BASEarchitectures.ItisinterestingtolookattheringratesofthesefourHDRimagesandunderstandbetterhowthethroughputoftheTBARimagersaffectserrors.Theringratesarecomputedasthenumberofringspersecondinasmallperiod.Themax-imumandmeanringratesofthefourHDRimagesareshowninTable3.4.Thering

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(a)(b) (c)(d)Figure3.16:Imagesrosetteandvinesunset.(a)rosette(brightpart).(b)rosette(darkpart:100brighterfordisplay).(c)vinesunset(brightpart).(d)vinesunset(darkpart:10brighterfordisplay)ratesandtherelativeerrorsoftherosetteandvinesunsetimageswithsizesof160180and480720areshowninFigure3.19andFigure3.20,respectively.Thetimebinsizeofthesetwoguresis5s.FromFigure3.19andFigure3.20,wehavetwousefulobservations:Recallfromthethroughputestimationinthelastsection,theminimumthroughputofTBAR MEMandTBAR BASEare73.0and75.8MegaPixels/second.FromtheimageringrateplotinFigure3.19(b)andFigure3.20(b),rosettehasahighringrateofmorethan100MegaPixels/secondregionfrom27msto30ms.vinesunset

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BASEoffourHDRimageswithsizesof160180and480720. Imageswithsizeof160180 ImageName nave groveC rosette vinesunset MeanRelativeError ImageName nave groveC rosette vinesunset MeanRelativeError BASEimagerwith0.378%meanrelativeerror.(a)Brightpart.(b)Darkpart(x100brighterfordisplay).hasamaximumthroughputofonly73.8MegaPixels/second.Thisindicatesthatrosetteislikelytohavemoreerrorsthanvinesunset.ItisveriedbytheresultsinTable3.2andTable3.3.Imageswithdifferentsizehavedifferentringrate.Theimageswithasizeof160180haveringratesroughly10timeslowerthanthosewithasizeof480720.Sincetheringratesofimageswithsizeof160180aremuchlowerthanthethroughputofTBAR MEMandTBAR BASE,theerrorsarenegligible,whichismanifestedbylookingattheerrorsinTable3.2andTable3.3.3.6.3TBAR BASEimagerwiththroughputcontrolFromtheerrorcalculationsinthelastsubsection,theerrorsarenegligibleformoderatesizeimages(suchasQCIFimageformat)forboththeTBAR MEMand

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(a)(b)Figure3.18:Imagelena.(a)Originalimage.(b)Imagelenawith0.9%meanrelativeerrorduetophotocurrentshotnoise.Table3.4:ThemaximumandmeanringratesoffourHDRimageswithsizesof160180and480720. Imageswithsizeof160180 ImageName nave groveC rosette vinesunset MaxFiringRate(MPixels/second) 9.2 15.6 20.4 7.8 MeanFiringRate(MPixels/second) 0.96 0.96 0.96 0.96 Imageswithsizeof480720 ImageName nave groveC rosette vinesunset MaxFiringRate(MPixels/second) 89.6 105 190 73.8 MeanFiringRate(MPixels/second) 11.4 11.4 11.4 11.4 TBAR BASEarchitectures.However,onepracticalissuearisesashowtocapturetheaddresspulsesgeneratedbyafree-runningTBAR BASEimagershowninFigure3.11.Thisisnotatrivialissuebecausethedurationofapulseisonlyabout2ns.ThisputsaveryhighrequirementonI/Ocircuitdesign[44]andtesting.Onepossiblesolutionistouseanon-chipbuffer(registersorSRAM).Butthiswillmakethedesignmorecomplicatedandconsumemoresiliconarea.AlsoconsideringtheintendedtestinstrumentisaAgilent1693Alogicanalyzerwhichhasamaximumtransientclockspeedof200MHz,theoutputpulsesrateinFigure3.11arecontrolledbyanexternalclocktomaketestingeasier,.Thisbringstwoadvantages:

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(a)(b) (c)(d)Figure3.19:Theringratesofrosette(a)withthesizeof160180,(b)withthesizeof480720,andtherelativeerrorsofrosette(c)withthesizeof160180,(d)withthesizeof480720.1.Thethroughputoftheimageriscontrollable.Thedatageneratingrateoftheim-agercanbesloweddowniftheI/Oortestingequipmentcannotkeepupwithit.Althoughthisapproachmayreducethethroughput,butthetestabilityjustiesthisapproachforthisprototypedesign.2.Sincethethroughputiscontrolledbyanexternalclock,theoutputaddressesareactuallysynchronouswithaclock.Therefore,althoughtheinternalimagercircuitsareasynchronous,theoutputaddressesaresynchronous.Thissolutionincorporatestheasynchronouscircuitsinasynchronousenvironment[45].Thecurrentdesignhasbeensimulatedusingclockratesrangingfrom20MHzto66MHz.Ifa20MHzclockisused,ittakesoneclockperiodtooutputonepixel,nomatterwhereitislocated,asshowninFigure3.21,wherethec latchsignalisonephaseofa

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(a)(b) (c)(d)Figure3.20:Theringratesofvinesunset(a)withthesizeof160180,(b)withthesizeof480720,andtherelativeerrorsofvinesunset(c)withthesizeof160180,(d)withthesizeof480720.two-phaseclock.Ifa66MHzclockisused,ittakes1clockperiod(15ns)tooutputeachpixelringsimultaneouslyinthesamerow.Forpixelsringsimultaneouslyindifferentrows,ittakestwoperiods(30ns)tooutputeachofthem.ThisisshowninFigure3.22.Itisnotdifculttocalculatethethroughput.Witha20MHzclock,thethroughputisxedat:Throughput=1

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Figure3.21:Outputaddressesusinga20MHzclocktocontrolthroughputunderuniformillumination.Witha66MHzclock,throughputisdifferent.ForaMNarray,themaximumthroughputhappenswhenlatcheshaveNvaliddatainonecycle:Throughputmax=N NTcycle+Tcycle1

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Figure3.22:Outputaddressesusinga66MHzclocktocontrolthroughput.1 2Tcycle=33Mpixels=sErrorsintroducedby20MHzand66MHzthroughputcontrolareestimatedfromMATLABsimulationsonthefour160180HDRimages.TheyarelistedinTable3.5.ComparedwitherrorsinTable3.2andTable3.3,thereisaslightincreaseoferrors.How-ever,theyarestillnegligiblecomparedwithphotonshotnoiseandxedpatternnoise.Inthisresearchproject,a3232TBAR BASEimagerwiththroughputcontrolhasbeendesignedandtestedduetoitsfeasibilityandtestabilityintheuniversityenviron-ment.Theerrorsimulationsdiscussedinthelastseveralsubsectionsdemonstratethatthe

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TBAR BASEwith20MHzThroughputControl ImageName nave groveC rosette vinesunset MeanRelativeError BASEwith66MHzThroughputControl ImageName nave groveC rosette vinesunset MeanRelativeError MEMarchitecturesuffersfromfewererrorsforthesameimagesizecomparedtotheTBAR BASEarchitecture.Thedisadvantageofthisarchitectureisthelargeon-chipmemoryneeded.TheTBAR BASEimagerdoesnotneedon-chipmemoryattheexpenseofasmallerpeakthroughput.ThroughputcontrolcircuitsofTBAR BASEforcesthead-dresspulsestosynchronizewithanexternalclock.Thismakestestingmucheasier.SincebothTBAR MEMandTBAR BASEimagerssharethesameidea(time-basedimagerwithasynchronousreadout)andsamecircuitcomponents(pixel,arbiterandasynchronouscon-trolcircuits),aftera3232TBAR BASEimagerissuccessfullyfabricatedandtested,itcanbeeasilyextendedtomakealargerimageroraTBAR MEMimageriftheon-chipmemoryisavailable.3.7SummaryInthischapter,theDRofthephotodiodeCMOSAPSimagerisanalyzedtoshowthelimitationstoDRwiththeconventionalCMOSAPSimagerarchitecture.Theopera-tionsofanumberofexistingHDRimagersareinvestigated.Atime-basedasynchronousreadout(TBAR)imagerisintroducedtoachieveHDR,anditsprinciplesandoperationsaredescribed.Twodifferentarchitectures,TBAR BASEandTBAR MEM,areproposed.OneuniqueissuewithTBARimagers,errorsintroducedbylimitedthroughput,isdis-cussed.ThethroughputofTBAR BASEandTBAR MEMiscomputed.MATLABsimu-lationsdemonstratethattheerrorsintroducedbyTBARimagersarenegligibleforthefourmoderatesize(upto480720)HDRtestimages.Thereasonforaddingthethroughput

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BASEimagerwiththroughputcontrolwillbepresented.

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BASEimagerisdesignedusingaAMI0.5mCMOSprocess.Whilethesystemarchitecturehasbeendiscussedinthelastchapter,thischapterfocusesonthedesignatthecircuitlevel.Section4.2willdiscussthepixeldesignfortheTBARimagers,whichincludesaphotodiode,acomparatorandadigitalcontrolcircuit.TheasynchronousreadoutcircuitdesignispresentedinSection4.3.Sincetheimagerisoperatingasynchronously,thecorrecttimingiscrucial.ThetiminganalysisisdiscussedinSection4.4.ThischapterisconcludedinSection4.5.4.2PixelDesignTheblockdiagramofthefabricatedandtestedTBAR BASEimagerisshowninFigure4.1.Eachoftheblockswillbediscussedindetailinthischapter.ComparedwithFigure3.9,Figure4.1doesnothaveacountersincethetestequipments,anAgilent1693Alogicanalyzer,hasanintegratedcounter.Thereare3232pixelsforthisdesign.ThepixelschematicisshowninFigure4.2.Insideeachpixel,thereisaphotodiode,acomparatoranddigitalcontrolcircuitry.Thepixeloperationandthedigitalcontrolcircuitrywillbeexplainedrst,followedbythephotodiodeandcomparatordesign.4.2.1PixelOperationandDigitalControlCircuitryInthissection,theoperationofonepixeloftheTBAR BASEimagerwillbede-scribed.ThecircuitdiagramofonepixellocatedatrowmandcolumnnisshowninFigure4.2.D1isaphotodiode.Thecomparatorisimplementedusinganopamp(which62

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Figure4.1:TBAR BASEimagerblockdiagram.willbediscussedindetaillater).RESandRESareglobalresetsignals.JOINisan-otherglobalsignal,whichwillbeexplainedsoon.Therow requestsignalistherequestsignalgoingtotherowarbiter.row selistheselectionsignal,comingthroughtherowin-terfacecircuitfromtherowarbiter.latch rowisusedtopreventthepixelfromringagainafterthispixelhasputitsringstatusinsidethelatch.Thecoxsignalputsthepixelringstatusintothelatchaftertherowofthispixelisselectedbyrow sel.row request(m),row sel(m)andlatch row(m)signalsaresharedbyallpixelsinthesamerowm,whilecox(n)issharedbyallpixelsinthesamecolumnn.Thepixelwillalwaysbeinoneofthefouroperationstates:resetting,integrating,ringandlatching:

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Figure4.2:TBAR BASEpixelschematic.4.2.1.1ResettingDuringtheresetphase,RESishighandRESislow.Thecomparatorisinaunit-gainfeedbackcongurationtoresetthephotodiode.AssumingtheampliergainislargeenoughandthechargeinjectionofswitchM16isnegligible,thephotodiodeisresetatthevoltageofVreset+Voff,whereVoffistheoffsetvoltageofthecomparator.Also,duringtheresetphase,JOINislowandM17isoff.Asaresult,theoutputofthecomparatorisisolatedwithresetofthecircuit.M18isusedtospeeduptransitionduringring.Duringreset,thepixelshouldnotoutputarequestsignal.ThatmeansvoltageatnodeAshouldbelow(pixelisdisabled),ensuredbyM13.SinceM13isstrongerthanM18,Aislowduringresetphase.M30isusedtoresetthelatchformedbytwoinverters:INV3andINV4.Thislatchstoresinformationwhetherthepixelisinthelatchingstate.4.2.1.2IntegratingWhenRESgoeslow,thephotodiodeD1istobedischargedattheratepropor-tionaltophotocurrentandthepixelisintheintegrationphase.Thenon-invertingnodeof

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resettozero.Also,M13isdisabledandM17isturnedonduringtheintegrationphase.TheoutputofthecomparatorwillbeabletocontrolthevoltageatthenodeA.AttentionneedtobepaidforthetimingofJOIN.JOINisusedtoisolatethecomparatoroutputandnodeBduringtheResetphase.Itisnecessarybecausethecom-paratoroutputvoltageishigh(equaltoVreset)whilenodeBislowduringtheResetphase.IfM17isturnedonatthesametimeRESgoestolow,thevoltageatnodeBwillbede-cidedbythechargesharingbetweenthechargesstoredattheoutputofthecomparatorandnodeB.Thisvoltageisdigital`1'veriedbytheSPICEsimulation.However,pixelsshouldnotberingimmediatelyafterRESgoeslow.Therefore,M17needtobeturnedontlaterthanRESgoestolow,waitingfortheoutputoftheopampgoesbackto`0',whereitshouldbe.TheCADENCESpectreSsimulationshowstshouldbemorethan1s.4.2.1.3FiringDuringintegration,thephotodiodeisdischargedbythephotocurrent.WhenthevoltageatD1dropsbelowthereferencevoltageVref,thecomparatoroutputgoestohigh.Asaresult,Aishighandrow requestispulleddowntolow.Therefore,thispixelresandsendsarequestsignaltotherowarbiter.4.2.1.4LatchingIftherowarbiterselects(bymakingrow sel(m)high)thisrowafterreceivingtherow request(m)fromthispixel,thispixelwillsendcox(n)tothecolumnlatch.Afterthecorrespondinglatchmakessurethattheringstatus(either`1'or`0')isinsidethelatch,itsendsalatch row(m)signaltoletthepixelwithdrawrow request(m)signal.Meanwhile,thepixelisdisabledbythepull-downtransistorM32.ThispixelcannotreagainuntilthenextresetphaseturnsoffM32.

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imagerpixelsizecanbereducedtoabout9m9mifa0.18mtechnologyisused.Furthermore,sinceithasbeengenerallyacknowledgedthatfurtherdecreaseinthepixelsizemuchbeyond5m5misnotneededbecauseofthediffractionlimitofthecameralens[46].Therefore,theTBARimagerswillbenetfromfurtherscalingintermsofreducedpixelsize,whichisnotthecasefortheconventionalAPSimagesensorsbecausetheirpixelsizehasalreadyreachedtheirfundamentallimits.In[47],theauthorsestimatedthenumberoftransistorseachpixelcanllastheCMOStechnologyscalesassuminga5m5mpixelsizewithaconstantllfactorof30%.For0.10mtechnology,about20analogtransistorsor100digitaltransistorscanbeputintoonepixel.ThisismorethanenoughforTBARimagers.4.2.2PhotodiodeDesignThephotodiodedesignisnotatrivialissue.Theoptimaldesignshouldachievehighsensitivity,lowdarkcurrentandlowcross-talk.Oneeffectivewaytoincreasethephoto-sensitivityistodeepenthephoto-conversionregion[48].Toreducedarkcurrent,apinnedphotodiodeisusedtosuppressthesurfacestate[13,14,15].Cross-talkcanbereducedbycarefullayoutandadjustingthedopingprole[48].Notethatdevicesimulatorsarefrequentlyusedtodetermineoptimallayoutsanddopingprolesindesigningphotodiodes.Forthisresearchproject,wedonothavetheluxuryofadjustingthedopingprolestoachieveanoptimalphotodiode.Instead,nativeP/NdiodesofastandardAMI0.5mCMOSprocessareusedasphotodiodes.Thereareatleastthreetypesofphotodiodes

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Figure4.3:Thelayoutofonepixel.availableintheAMI0.5mCMOSprocess:P-substrate/N-diffusion,P-substrate/N-wellandP-diffusion/N-well.Inthisdesign,aP-substrate/N-welldiode,asshowninFigure4.4,isused.ThetotalcapacitanceatthecathodenodeofthephotodiodeisthesummationofthejunctioncapacitanceoftheP-substrate/N-well,thegatecapacitanceofaninputPMOStransistor(withawidthof1.5mandalengthof1.2m)ofthecomparatorandthedraincapacitanceoftheresetPMOStransistor(M16inFigure4.4,withawidthof1.5mandalengthof0.6m):Cpd=CNwell+Cgate+Cdrain(4.1)ThedrawnareaoftheN-wellis3:6m3:9m14m2,givingrisetoacapacitanceofCNwell=0:56fFfromtheMOSISN-wellcapacitancedata(40aF=m2between

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Figure4.4:N-well/P-subphotodiode.N-wellandsubstrate).TheinputPMOStransistorsofthecomparatorareintheweakinversionregion.ThegatecapacitorcanbemodeledastheseriescombinationofagateoxidecapacitorCoxandasubstratedepletioncapacitor[49].FromtheMOSISdata,thegateoxidecapacitanceofa1:5m(W)1:2m(L)PMOStransistoris4.3fF.Thedepletioncapacitancedependsonthesubstratedopingdensity,foratransistorinweakinversion[49]:Cb=As

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request.Thisamountoftimedelaymaybedifferentfordifferentilluminationlevels(i.e.,differentphotodiodedischargingrates).Whentheoriginalimage(illuminationinformation)isreconstructed

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Figure4.5:Usinganopamptoresetthephotodiode.AssumethegainoftheopampisA,fromthesmallsignalmodeloftheopamp,wehavevout=Avin(4.5)wherevoutandvinaresmalldeviationsfromtheopampDCoperatingpointsatoutputandinput,respectively.

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A0+1)Vreset+Vout;dcVreset A20(4.8)assumingAismuchsmallerthanA0andA0ismuchlargerthan1.Thus,theresetvoltagevariationisVph=(Vout;dcVreset)A=A20.ThisvariationdependsonthedifferencebetweentheopampoutputbiasvoltageVout;dcandthephotodioderesetvoltageVreset,theopampnominalgainA0,andtheopampgainvariationA=A0.Ifthephotodioderesetvoltageisequaltotheopampoutputbiasvoltage,theresetvoltagevariationiszerofromEquation:4.7.However,theremaybesomedifferencebe-tweenthedesiredphotodioderesetvoltageandtheopampoutputbiasvoltageinpractice.Toseehowmuchgainisrequired,assume:1.Thevariationofthephotodioderesetvoltageshouldbelimitedtolessthan1mV.2.Vout;dcVresetislessthan1volt.3.TheopampgainvariationA=A0is0.1.

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Figure4.6:Opampoffsetcancellationusingautozeroingcircuit.TheautozeroingoffsetcancellationcircuitisshowninFigure4.6.Duringtheresetphase,theopampisconnectedinaclosed-loopconguration.ItisnotdifculttondoutthevoltageatthephotodiodeisVph=Vreset+Voff+Vout;dcVreset

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2Qch 2WLCox(VGSVth)

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Figure4.7:Opampschematic.outputvoltageoftheopamp,Vout,goesfromtheresetvoltageVresettoabout0V.Becausethephotodiodeisoating,duetothegate-drainoverlapcapacitorCovofM1,thechangeinvoltageatthephotodiodeisgivenbyVph=Cov

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Figure4.8:5-transistorOpampchargeinjection.Gain.Tondthegainofthisopamp,noteatrstthatalltransistorsareworkingintheweakinversionregionsincethetotalbiascurrentislessthan100nA.Theweakinversiondraincurrent[52]ID=W LqXDnnp0expk2 LqXDnnp0expk2

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2=1 21 21

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TotalCurrent A PhaseMargin 64nA 39.6dB 48KHz 3.32s norm)hasperfectlymatchedinputtransistorsM1andM2inFigure4.7.Theothercomparator(comp mis)has25%lengthmismatchbetweenM1andM2.TheringtimesofpixelsatnodeAinFigure4.2arelistedinTable4.2forsituationswithandwithoutautozerocancellationatdifferentphotodiodecurrentlevels.For25%lengthmismatch,itshowstheerrors(inthetimedomain)havedecreasedfrom0.95%to0.21%andfrom0.87%to0.26%forphotocurrentsof200pAand2pA,respectively.Table4.2:Theringtimeofpixelswithandwithouttheautozeroingcircuit Ipd=2pA norm comp mis Error comp norm comp mis Error w/oautozero 52.41s 5.077ms 5.033ms 0.87% w/autozero 54.79s 5.302ms 5.288ms 0.26% WhentheTBAR BASEimagerwasdesignedandsubmitted,theauthordidnotrealizeahigh-gainamplierwasunnecessary.TheopampshowninFigure4.9wasused.Thisamplierachievedhighgain(79dB)attheexpenseofspeed.ThecadencesimulationresultsonAMI0.5mtechnologyarelistedbelowinTable4.3.TheoffsetcancellationeffectsareshowninTable4.4.Table4.3:Theopampperformance. TotalCurrent DCGain UnitGainBandwidth PhaseMargin 54nA 79dB 5.1MHz

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Figure4.9:OpampusedinthetestedTBARimager.Table4.4:TheringtimeofpixelswithandwithouttheautozeroingcircuitusingtheopampinFigure4.9 Ipd=2pA norm comp mis Error comp norm comp mis Error w/oautozero 54.41s 5.168ms 5.266ms 1.9% w/autozero 59.03s 5.629ms 5.617ms 0.2% BASEimagerisshowninFigure4.1.Firstnotethatthisisamixed-signalsystem,withtheanalogphotodiodeandcomparatorinsideeachpixelwhiletherestofthecircuitsaredigital.Secondly,thedigitalcircuitsoperateasyn-chronously.Thispreventsadoptingastandarddigitaldesignmethodology,whichusesahighdegreelanguage(VerilogorVHDL)todescribeandsimulatedigitalcircuits,andfromthatatransistorimplementationmaybeautomaticallysynthesizedusingalibraryofstan-dardcells.Partofthedifcultyliesonthatmostcommerciallyavailabletoolsandlibrariesaretargetingforsynchronoussystems.AlthoughtherearesomeCADtoolsavailablefrom

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80 theacademicresearchcommunity,majorEDAvendorshavenotyetincludedsuchtoolsin theirproductportfolios[41]. Forthis32 32TBAR BASE,thereareabout38ktransistors.FullSPICEsimulationwasproventobeimpossible.Ittakesmorethanonedaytosimulateabout20pixels. Forlargerarrayssuchas128 128,thecomputationwouldbeprohibitive. Someresearcherscalledforbehavioralmodellingofanalogandmixed-signalcircuits[54].Therearetworeasons,oneistheincreasingsizeofanalogsystems,theotheris theheterogeneityofwaveformtypesofinterest.Anexampleofthelattercaseisthephaselockloop(PLL),whichoperatesinthefrequencydomain.Forthemixed-signalsystem, theabilityofhierarchicalsimulationisimportant.Basically,inonesimulation,different blocksinasystemcanbesimulatedusingdifferentsimulationengines.Forexample,digitalpartsarerepresentedasabstractlogiccellsandsimulatedusingVHDL,whiletheanalog partsarerepresentedatthetransistorlevelandsimulatedusingSPICE. TheauthorhasnotbeenabletodesigntheTBARimagerusingtheaboveapproach. Onereasonisthetightschedule,andanotheristhatthemixed-signalsimulationtoolsdid notworkatthetime.Instead,aftercarefullysimulatingeachbuildingblock,wesimulated thewholeimagerforabouttwodozenpixelringsusingCADENCESpectreS.Circuits wereveriedwithextractedparasiticcapacitorsattheprocessandtemperaturecorners. Sincethisisahighspeeddigitaldesign,thepackageparasiticinductorsandcapacitors werealsoincludedinthesimulation. 4.3.2AsynchronousCircuitDesign 4.3.2.1Pixeldigitalcontrolcircuit ThepixeldigitalcontrolcircuithasbeendrawninFigure4.2anddescribedin Subsection4.2.1. 4.3.2.2Arbiter Rowandcolumnarbitersareusedtochooseonerow/columnwhenmanyrows/columnsmakesimultaneousrequests.ThearbitersusedinaTBARimagerarefromthe

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MEMarchitecture,asmentionedinChap-ter3. (a) (b)Figure4.10:Atwoinputarbitercellcircuit(a)schematicand(b)symbol.Theschematicandsymbolofatwo-inputarbitercellisshowninFigure4.10.Atwo-inputarbitercellhastwolowerportsandoneupperport.Eachlowerporthasonerequest in(LInintheschematic)inputpinandoneselect out(LOutintheschematic)outputpin.Theupperporthasonerequest out(ROutintheschematic)outputpinandoneselect in(RInintheschematic)inputpin.Whenatleastoneofthetwoactive-highrequestsignals,LIn

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Figure4.11:Timedelaysimulationofa2-inputarbitercell.Rowandcolumnarbitershavemanyinputs.Theyarebuiltfromtwo-inputarbitercellsusingthebinarytreearchitectureshowninFigure4.12.Therequestsarerelayedupthetree,whiletheselectionisrelayeddownthetree.Atanytime,onlyoneinputport(at

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Figure4.12:Aneightinputsarbitertree.4.3.2.3RowInterfaceTherowinterfaceisusedtocontrolwhetherarowcanbeselectedbytherowarbiter.Itislocatedbetweenthepixelarrayandtherowarbiter,asshowninFigure4.1.Thereisonerowinterfacecircuitforeachrow.ThecircuitisshowninFigure4.13.ItisimplementedusinganasymmetricC-elementdescribedbyMartin[55].Thisisastate-holdingoperatorwithtwoinputs.Oneoftheinputs,arbiter selistheselectionsignalcomingfromarbiter.Theotherinput,row sel enable,comesfromthelatchcontrolcircuit.Therearethreepossibilities:Ifarbiter selisinactive,row selisinactive,nomatterwhatstaterow sel enable.Ifbotharbiter selandrow sel enableareactive,theoutputrow selisactive.

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selisactiveandrow sel enableisinactive,therow selkeepsthepre-viousstate. Figure4.13:Rowinterfacecircuit.4.3.2.4LatchandLatchControlLatchandlatchcontrolcircuitshavebeendescribedbyK.Boahen[32].Thesecircuitsareusedtoincreasethethroughputofaddress-eventreadoutoriginallyproposedbyMahowald[56].ThelatchcellandlatchcontrolcircuitsschematicsareshowninFig-ure4.14[32].Thereisonelatchcellforeachcolumnandonelatchcontrolcircuitforthewholearray.Belowarefunctionsofsomeimportantcontrolsignals:bisusedtocontrolwhetherdataoncoxareallowedtocomeintothelatchcells.gindicateswhethertherearestillvaliddatainsidelatchcells.col request nisthecolumnarbiterrequestsignal;andcol sel nistheacknowledgesignalcomingthroughthethroughputcontrolcircuitfromcolumnarbiter.lpmonitorswhethertherearedataonthecoxlines.row sel enablegoestotherowinterfacecircuit(showninFigure4.13).Itenablesthenewrowselectionsignalgoesintopixelarray.

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(a) (b)Figure4.14:Latchcellandlatchcontrolcircuits.(a)Latchcell.(b)Latchcontrolcircuit.latch data readyisvalidafterdataoncoxlineshavealreadycomeintothelatch.Thissignal,togetherwithrow sel,disablethepixelswhichhaveredintheselectedrow.row address triggerletstherowaddressencoderupdateoutputrowaddress.Alsonotethat:1.coxcomesfromthepixel(Figure4.2)andissharedbyallpixelsinthesamecolumn.2.col request nandcol select naretherequestandselectforthecolumnarbitertree,respectively.

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Figure4.15:Throughputcontrolcircuit.bytwonon-overlappingclocks1and2,atanytime,atmostonetransmissiongateisopen.col arbiter selistheselectionsignalfromthecolumnarbiterandcol select ngoestothelatchcell.col encoder inistheinputtothecolumnaddressencoder.Byusingtwotransmissiongates,wecancontrolhowfasttheselectionsignalsfromcolumnarbitergointothelatchcellbysimplyadjustingtheclockspeed.

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BASEimagerareshowntogetabetterunderstandingoftheoperationoftheasyn-chronousreadoutcircuit.Thecircuitisanalyzedundertwosituations:imagerresetandforpixelsringsimultaneously.Wesummarizethetiminganalysisusinganitestatemachine(FSM)model.4.4.1ResetWhenRESisactive,theTBARimagerisreset.Belowaresomeimportantsignalstatesineachbuildingblock.4.4.1.1PixelandRowArbiterRES=0!A=0!row request=1!row sel=04.4.1.2LatchCellandLatchControlallcox=1!lp=0!latch data ready=0RES=0!col request n=0columnarbiter!col select n=0!g=1(lp=0)AND(g=1)!row sel enable;b=1Insummary,duringtheresetphase,row sel enable=1allowstherowinterfacetopasstherowselectionsignalfromtherowarbiter.b=1meanstheringstatescangointolatchcells.

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request(1,5,9,13,17,21,25,29)#row arbiter!rowarbiterpicksonerowarbitrarily.Inthisexample,the29throwisselected(i.e.row sel request sel request#torow sel sel sel enable=0)

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Figure4.16:Waveformsofrowarbitration.!latch data ready=1!disablefiredpixelsrow address trigger"!enablerowaddressoutputInsummary,whendata(coxsignals)arealreadyinsidethelatchcells(i.e.,gislow)andtherearevaliddataoncoxlines(i.e.,lpishigh),thelatchcontrolcircuitwillmakethreeactions:1.Makingb(row sel enable)low.Thiswillforbidnewrowselectionbydisablingtherowinterfacecircuit.2.Disablingtheredpixeloftheselectedrowbyenablinglatch data readysignal.3.Generatingarow address triggertriggersignaltooutputtherowaddress.TheabovetimgingisshowninFig.4.18.DisablingPixel.

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Figure4.17:Waveformsofcolumnarbitration.Whenthedataarealreadyinsidethelatch,pixelswhichhaveputdataintolatchcellsaredisabled,asshowninFigure4.19.Followingtheabovecase,row(29)hasbeenselectedanditisbeingdisablednow:latch data ready=1row sel row request(29)=1rowarbiter!row sel i=0allcox=1!lp=0Sincealltheredpixelsinthepreviouslyselectedrowhavebeendisabled,pixelrequestsignals,cox,arehigh.ThroughputControl

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Figure4.18:Waveformsoflatchcontrolcircuit.Byusingtwonon-overlappingclocksignalstocontroldatatransportbetweenthecolumnarbiterandlatchcells,throughputcontrolismadepossible.Thecolumnaddressisactuallysynchronouswiththecontrolclock,asshowninFigure4.20.Notethatci downandc latchinFigure4.20aretwonon-overlappingclocksignals1and2inFigure4.15,respectively.LatchControl(whenallthevaliddatainsidethelatchcellshaveoutputtheirad-dresses.)Whenthelastdatum(inthisexample,itisatcolumn29)inthelatchcellshasoutputitscolumnaddress,gxi select latchgoesdown.Thiswillcausegtoriseup.Asaresult,b(androw sel enable)goeshigh.Thus,therowinterfacecircuitisopenandnewrowselectionismade

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Figure4.19:Disablingpixels.possible.Uptothispoint,theTBARreadoutcircuitnishesoutputtingtheaddressesofredpixelsinoneselectedrow.ThisprocessisshowninFig.4.21.4.4.3FiniteStateMachineModelFromtheabovetiminganalysisandsimulationresults,wehaveseentheasyn-chronousreadoutcircuitisquitecomplicated.Moreinsightcanbeachievedbymodellingtheoperationofthereadoutcircuitasanitestatemachine(FSM),asshowninFigure4.22.TherearefourstatesforthisFSM:reset,standby,data-in-latch,andcolumn-ad-dress-output.1.Reset(StateI)WhenRES=1,theTBARimagerisreset.TheimportantsignalstateshavebeendescribedinSection:4.4.1.2.Standby(StateII)

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Figure4.20:ColumnAddressOutput.WhenRESgoesdown,theTBARimagerentersintothestandbystate,waitingforpixelring.Sincethereisnoring,theimportantsignalsstatesarethesameasintheStateI.3.Data-in-latch(StateIII)Afteroneofthepixelsrs,theTBARimagergoesfromtheStateIItotheStateIII.Inthisstate,redpixelsintherowselectedbytherowarbitersendtheirringstatestothelatchcells.Thecolumnarbiterbeginstoprocessdatainsidethelatchcells(i.e.,outputstheaddressesofthecellswithvaliddata).Asdescribedabove,threeactionsaretakenbythelatchcontrolcircuit:(a)Makingb(row sel enable)low.Thiswillforbidnewrowselectionbydis-ablingtherowinterfacecircuit.

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Figure4.21:Latchcontrolsignalsafteralldataareoutput.(b)Disablingtheredpixeloftheselectedrowbyenablingthelatch data readysignal.(c)Generatingarow address triggertriggersignaltooutputtherowaddress.4.Column-address-output(StateIV)Theactivelatch data readydisablestheredpixels,andallcoxsignalsarecleared.Columnarbiterandcolumnaddressencoderkeepoutputtingaddressesofthevaliddatainsidethelatchcellsataratecontrolledbythethroughputcontrolcir-cuit.Whenallvaliddatainthelatchcellsareprocessed(g=1),row sel enablebecomesvalidandnewrowselection(ifthereisany)canbestarted.TheTBARimagergoesbacktostandbystate(StateI).

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Figure4.22:Finitestatemachinemodelofasynchronousreadoutcircuit.4.5SummaryInthischapter,thedesignandanalysisoftheTBAR BASEimagerisdiscussed.AnN-wellphotodiodeisusedtoconvertphotonsintochargecarriers.Theonlyanalogpartintheimagerisacomparator.Thereasonsforusinganopampasacomparatorareexplained.Thegainrequirementofthisopampisanalyzedintermsofreductionofthexedpatternnoise(FPN).Thereadoutcircuitoperatesintheasynchronousmode.Eachpartoftheasynchronousreadoutcircuits(arbiters,rowinterface,latchcells,latchcontrolandthroughputcontrolcircuits)arediscussedandsimulationresultsarepresented.Thereadoutcircuitanalysisiscompletedbyanitestatemachine(FSM)model.

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Figure5.1:MicrographofTBAR BASEimager.ThemajortestingequipmentisanAgilentPC-hosted1693Alogicanalyzer.Ithasthreemeasurementmodes:astatemodewith200MHzclockrateand256Kmemory,an

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Figure5.2:PinconnectionoftheTBARimager.asynchronoustimingmodewith400MHz/800MHzsamplingrateand512K/1Mdeepmemory(full/halfchannel),andatransitionaltimingmodewith200MHzand256Kmemory.ThepowersupplyisanAgilent6651A8V/50ADCpowersupply.ReferencevoltageVrefandresetsignalRESaregeneratedfromanNationalInstruments8-channelNI-6713D/AcomputerhostedPCIcard.Itisa12-bitD/Awithmaximumupdaterateof1MS/second.TheFIFObuffercanhold16Ksamples.Thenominaloutputvoltagerangeisfrom-10Vto10V,whichgivesanLSBof5mV.TheRMSanalogoutputnoiseis200V.ThetestingsetupisshowninFigure5.3.Asmallprintedcircuitboard(PCB)isbuilttoputtogetherTBARimager,voltageregulator,biasgeneratorandconnectors.The1693AlogicanalyzercapturesaddressoutputsandpixelringtimesfromtheTBARimager.AsimpleMATLABprogramreconstructsimagesusingthecaptureddata.

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Figure5.3:ExperimentalsetupfortestingandcharacterizationofTBARimager.5.3TestingandCharacterizationInthissection,theperformanceoftheTBARimagerischaracterizedintermsofpower,darkcurrent,FPN,temporalnoise,conversiongain,anddynamicrange.Quantumefciencyandsensitivityarenotmeasuredbecausewedonothaveamonochromator.Withoutanintegratingspheretogeneratinguniformillumination,wearealsounabletoestimateFPN.5.3.1PowerConsumptionSinceTBARimagerhasaseparatepowersupplyforanalog,digital,andpadcircuit,powerconsumptionforthesethreecomponentscanbemeasuredseparately.ThecurrentismeasuredusingaKeithley617programmableelectrometer.At30frames/second,theanalogcurrentis0.24mAandthedigitalcircuit(withoutpads)consumes0.38mA.Thetotalcurrentis0.62mA(withoutpads).At5Vpowersupply,this3232TBARimagerconsumes3.1mWat30frames/sceonds.

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Figure5.4:Darkcurrentgenerationatthephotodiode.Wealsondmanypixelsdonotreatallunderthedarkcondition.Itwasquitesurprisingatrst.Aftercarefullylookingatthecircuitsaroundthephotodiode,webelieveitisbecauseoftheleakagecurrentofaPMOStransistor.AsshowninFigure4.2,PMOStransistorM16isusedtoresetphotodiodeD1duringresetphase.Afterreset,M16isturnedoffandthecathodeofD1isoating.FromFigure5.4,therearetwodiodesattheVphnode:oneisthen-well/p-substratephotodiodeD1,andtheotheristhep+/n-welldiffusiondiodeformingthesourceofPMOStransistorM16.ThedirectionofelectricaleldofthesetwodiodesarealsoshowninFigure5.4.WhilethethermalgeneratedchargecarriersfromphotodiodeD1dischargethecapacitoratthecathodeofthephotodiode,

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Figure5.5:DarkCurrentDistribution.ThedarkcurrentdistributioninthearrayisshowninFigure5.5.Notethatthedarkcurrentislinearlyscaledfrom0to255fordisplay.Aspatiallyrandomdistributionpatternisobservedfromthisgure.Itisnotsurprisingbecausethedarkcurrentislargelyduetothegenerationcenters(i.e.,traps),whichtendtodistributerandomly.5.3.3DynamicRangeGivenaxedreferencevoltage,thedynamicrangeoftheTBARimagerisdeter-minedbytheratioofthelongestintegrationtimetotheshortestintegrationtime,asfromEquation3.26.Thedarkcurrentdeterminesthelongestintegrationtime,whichismorethan20secondsfrommeasurements.Thedesignedshortestintegrationtimeis1s.This

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Figure5.6:AhighdynamicrangepicturetakenbyTBARimager(withoutpostprocessing).Sincewedonotagoodmounteddevicetoholdlens,wesimplyputalenssittingontopoftheTBARimager.Itturnsoutthisopticalsetupputsalimitonthedynamicrangewecanmeasure.Inordertotakeahighdynamicrangepicture,theremustbebothverybrightpixelsandverydarkpixelsinthesensorarray.However,sincethelensisnottightlymountedontheTBARimager,thereislightleakingintothepixelarraywhenaverybrightlightsourcepresented.Asaresult,weareunabletogetaverydarkpixelwhenastronglightsourceispresented.However,westillmanagetogeta104dBpicture,whichisfarbeyondthedynamicrangeofconventionalCCDandCMOSAPSimagesensors.Thispictureisanincandescentlampcoveredbyblacktapewithaholeinthemiddle,asshowninFigure5.6.Todisplaythedarkpartoftheimage,thedatainFigure5.6(B),(C),(D),(E),(F)are10,100,1000,10000,100000timeslargerthandatainFigure5.6(A),respectively.TheshapeandpositionofthelamentcanbeclearlyseenfromFigure5.6

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Figure5.7:HistogramequalizationofFigure5.6.(A).ThehistogramequalizedimageisdisplayedinFigure5.7.Alsonotethatthesmallestringtimeis1.61sandthelargestringtimeis255ms.Figure5.8showstwoimagesamplestakenbytheTBARimager.Thesetwoimageshaveadynamicrangeof57dBand58dB,respectively.5.3.4TemporalNoiseForconventionalCCDandCMOSAPSimagesensor,temporalnoiseisdenedastheoutputvoltageuctuationunderastableillumination.FortheTBARimager,sincetheilluminationisrepresentedinthetimedomain,theringtimeuctuationsaremeasuredtoestimatethetemporalnoise.Themajorlimitationtotheaccuracyofthemeasurementisthestabilityofthelightsource.Ifthelightsourceisunstable,wewillnotknowhowmuchtheringtimeuctuationiscontributedbythecircuittemporalnoiseandhowmuchiscontributedbythelightsourceuctuation.A3-voltDCbatterypoweredashlightisusedasalightsource.Thereisnoobservablebatteryvoltageuctuationfromtheoscilloscope.

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Figure5.8:Twoimagesamples`UF'and`Lamp'(withoutpostprocessing).Forapixel(m,n),themeanandvarianceoftheringtimeareestimatedasfollows:

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Figure5.9:Twohistogramequalizedimagesamples`UF'and`Lamp'.thisisthatthedominantnoisesourceisthephotocurrentshotnoise.Becausetherefer-encevoltageofthecomparatorsisconstant,allpixelshaveaccumulatedsamenumberofphotoelectrons.ThiswillgiverisetothesamenoiseassumingphotoelectrondistributionisaPoissondistribution(Equation2.6).Figure5.12showstheringtimeofonepixelatposition(5,5)inthedifferentframe.Thememorydepthofthelogicanalyzerlimitstheframenumberto45.Forthisparticularpixel,themeanringtimeis74.96msandthestandarddeviationis345.1s,whichgivesarelativetemporalnoiseof0.460%.5.3.5ConversionGainConversiongaincharacterizesthesignalgeneratedperphotoelectron.Itindicatesthesensitivityofthesensor.Anaccuratedeterminationoftheconversiongainalsoenablesadeterminationofthephotodiode'squantumefciency.Theconversiongainisdenedbyg=v n(5.4)wherevisthesignalvoltageatthephotodiodeandnisthenumberofphotoelectrons.AnexcellentreferenceofdeterminationoftheconversiongainusingastatisticalmodelisfromB.BeeckenandE.Fossum[61].Ifthedominantnoisesourceisthephotonshotnoise,conversiongaincanbedeterminedbyusingthefactthattheshotnoiseobeysthePoissondistribution.FromtheEquation5.4,themeanandthevarianceofthesignal

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Figure5.10:Thetemporalnoiseofdifferentpixelsintheimage`ashlight'.voltageatthephotodiode n(5.5)2v=g22n(5.6)ForaPoissondistribution,thevarianceissimplythemean.Thus,2n= n= 2n= 2v=g2=g2 2v(5.8)FromEquation5.8,theconversiongainisg=2v

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(a)(b)Figure5.11:Image'ashlight',(a)Brightpart.(b)Darkpart(1000timesbrighterfordisplay).startthederivation,notethattheconversiongainisalsodeterminedbythetotalcapacitanceatthecathodeofthephotodiode.IfnelectronscauseavoltageofvonacapacitanceofCph,theconversiongainisg=v n=1 nCph=q Cph(5.10)whereQnisthetotalchargesatthephotodiodeandqisthechargeofanelectron.Assumingthecomparatornoiseandthereadoutcircuitdelaycanbeneglected,theringtimeisthetimewhenthevoltageatthephotodiodereachesthereferencevoltageVref.Thisassumptionisvalidwhenthereareenoughphotonintroducedchargescarriersatthephotodiodeand,asaresult,thephoto-currentshotnoiseisthedominantnoisesource.Atthistime,thereareNphotoelectronsaccumulatedatthecathodeofphotodiode.WenotethatN=Q q=(VresetVref)Cph

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Figure5.12:Theringtimeofonepixel.resetinthiscase)tothetimetNwhentheNthelectronarriveshasanErlangdistribution:fN(t)=N (5.13)2t=N 2(5.14)Fromabovetwoequations,therelationshipbetweenthetemporalnoiset= tandthetotalnumberofchargecarriesNarefound:2t 2 tisthetemporalnoisedenedinthelastsection.SincethechargecapacityNissameforallpixelsassumingnomismatchbetweenpixels,Equation5.15impliesallpixelsshouldhavethesametemporalnoiseregardlessoftheirdifferentringtimes.

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(t (0:460%)2=47;260electrons(5.16)ThetotalcapacitanceatthecathodeofthephotodiodeisCph=Qch VresetVref=1:6101947;260 2=3:78fF(5.17)Wecalculatedthiscapacitancetobe4.0fFinChapter4.Themeasurementresultmatcheswellwithhandcalculations.FromEquation5.10,theconversiongainisg=q Cph=1:61019

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Figure5.13:Antemporallyaveragedimageunderroomlightconditionwithoutusingalens.ThisimageisscaleduptoexaggeratetheFPN.duetothelackofequipmenttocharacterizeFPN,quantumefciencyandsensitivity.TheperformanceoftheTBARimagerissummarizedinTable5.1.Table5.1:TheperformanceoftheTBARimager. Technology 0.5mAMIStandardCMOS SupplyVoltage 5Volt Transistorsperpixel 30 Arraysize 3232 Pixelsize 37.5m34.8m 4.8m5.1m 3.1mWwithoutpadpower Darkcurrent(roomtemperature) 42V/electron DynamicRange(onepixel,measured) 140dB DynamicRange(array,measured) 104dB(limitedbytheopticalequipment)

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Figure5.14:Awiresitabovesensorwithoutusingalens.

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BASEwithouton-chipmemoryandTBAR MEMwithhigherreadoutthroughputattheexpenseofon-chipmemory.TheTBARimagerperformanceisanalyzedandsimulatedatthesys-temleveltoproveitshighdynamicrangecapability.A3232TBAR BASEimagerwasdesignedina0.5mCMOStechnology.Thetimedomaintestingandcharacteriza-tiontechniquesaredevelopedbecausethecommonvoltagedomainbasedcharacterizationtechniquescannotbedirectlyapplied.Theimagerperformsasweexpected,achievinghighdynamicrangeandmoderatepower.Itistheauthor'sbeliefthattheTBAR BASEimagerispoisedtobeastrongcom-petitoramonghighdynamicrangeCMOSimagesensors,especiallyforsmalltomoderatesizeimagermarkets.TheauthorbelievesthattheTBAR BASEimagerhasoneofthemostoptimizedtrade-offsintermsofperformance,powerandmemoryrequirements.Forexam-ple,theFPNoflogarithm-basedhighdynamicrangeimagersisnotsatisfactoryevenwithFPNcancellationtechniques.Multi-samplingtechniquesusuallyneedalargeamountofmemoryandhasahighpowerconsumption.Manyothertime-basedhighdynamicrangeimagershavetoocomplicatedimagereconstructionprocedures.OurTBARimagersrepresentandreconstructimagesinanatureandsimpleway:thetimeintervalfrompixelresettingtoring.Formoderatesizeimages,theTBAR BASEarchitectureprovidesahighenoughthroughputtoaccuratelyreconstructimageswithout113

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BASEimager.TheauthorsincerelyhopethisworkcouldbecontinuedtomakeTBARimageraseriouscontenderfortheCMOSimagesensormarket.Thepossiblere-searchdirectionsare:1.ThethroughputoftheTBARimagerneedstobeimproved.ItisafundamentallimitingfactortoapplytheTBARimagerforlargeimages(e.g.,morethan1Mega-pixel).Thethroughputcanbeimprovedatboththearchitecturelevelandthecircuitlevel.2.Wehavebuilta3232TBAR BASEimagerusinga0.5mCMOStechnology.However,tobetterdemonstratethecapabilitiesoftheTBARimager,largerimager(e.g.,128128)needstobedesignedandfabricatedinamoreadvanced(e.g.,0.18mCMOStechnology).3.Oneofthecontributingfactorstothelargenumberoftransistorsinsideapixelistheautozeroingcircuit,whichisintendedtocancelFPN.Becausewedonothaveauniformlightsource,wewereunabletomeasurehoweffectivetheautozeroingcircuitisintermsofFPNcancellation.Thisissueneedstobefurtheraddressed.4.Intheauthor'sexperience,asynchronouscircuitdesignistediousanderror-prone.Itislargelybecausedesigntoolswehavearemainlyaimingatsynchronoussystemdesign.However,therearesomeasynchronouscircuitdesigntoolsfromacademicresearchcommunity.Itmaybecomeimperativetoincorporatesomeautomaticdesigntoolsastheimagersizeincreases.5.Becausewedonothavesomespecializedopticalequipmentinourlab,theauthorwasunabletomeasureFPN,quantumefciencyandsensitivity.Thisworkshouldbedoneinthefuturetomakethecharacterizationcomplete.6.TheoutputsofaTBARimageraredrasticallydifferentfromtheCCDsandCMOSAPS.Thepixelpositionsarereportedsequentiallyaccordingtotheirlightintensi-ties.Inotherwords,theimagearesortedinthelightintensity.Thisfeaturemakescertainsignalprocessingtasks,e.g.,histogramequalizationandtrackingobjects,easier.Thistopicmayneedtobefurtherinvestigated.

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117 [30]L.McIlrath.Alow-powerlow-noiseultrawide-dynamic-rangeCMOSimagerwith pixel-parallelA/Dconversion. IEEEJournalofSolid-StateCircuits ,36(5):846, May2001. [31]E.Culurciello,R.Etienne-Cummings,andK.Boahen.Arbitratedaddresseventrepresentationdigitalimagesensor.In ISSCCDigestofTechnicalPapers ,pages92, 2001. [32]K.Boahen.Athroughput-on-demandaddress-eventtransmitterforneuromorphic chips.In AdvancedResearchinVLSI ,pages72,1999. [33]V.BrajovicandT.Kanade.Asortingimagesensor.In Proc.ofthe1996IEEEInt. Conf.onRoboticsandAutomation ,pages1638,Minneapolis,Minnesota,April 1996. [34]Y.Ni,F.Devos,M.Boujrad,andJ.H.Guan.Histogram-equalization-basedadaptive imagesensorforreal-timevision. IEEEJournalofSolid-StateCircuits ,32(7):1027 1036,July1997. [35]X.Guo,M.Erwin,andJ.Harris.Ultra-widedyanmicrangeCMOSimagerusing pixel-thresholdring.In ProceedingsofWorldMulticonferenceonSystemics,CyberneticsandInformatics ,volume15,pages485,Orlando,Florida,July2001. [36]X.Guo,M.Erwin,andJ.Harris.Atime-basedasynchronousreadout(TBAR)CMOS imagerforhigh-dynamicrangeapplications.In ProceedingsofIEEESensors ,pages 712,Orlando,Florida,June2002. [37]S.Mendis,S.Kemeny,R.Gee,B.Pain,Q.KimC.Staller,andE.Fossum.CMOS activepixelimagesensorsforhighlyintegratedimagingsystems. IEEEJournalof Solid-StateCircuits ,32(2),Feburary1997. [38]R.Kummaraguntla. TimeDomainQuantizationCMOSImageSensorSystemDesign andArchitecture .Master'sthesis,UniversityofFlorida,Gainesville,FL,2001. [39]S.Kleinfelder,S.Lim,X.Liu,andA.ElGamal.A10000frames/sCMOSdigital pixelsensor. IEEEJournalofSolid-StateCircuits ,36(12):2049,December 2001. [40]F.Andoh,H.Shimamoto,andY.Fujita.Adigitalpixelimagesensorforreal-time readout. IEEETransactiononElectronDevices ,47(11):2123,November2000. [41]C.H.VanBerkel,M.B.Josephs,andS.M.Nowick.Applicationsofasynchronous circuits. ProceedingsoftheIEEE ,87(2):223,Feburary1999. [42]H.Shimizu,K.Ijitsu,H.Akiyoshi,K.Aoyama,H.Takatsuka,K.Watanabe, R.Nanjo,andY.Takao.A1.4-nsaccess700-MHz288-kbSRAMmacrowithexpandablearchitecture.In ISSCCDigestofTechnicalPapers ,pages190,1999. [43]P.Debevec. RecoveringHighDynamicRangeRadianceMapsfromPhotographs [Online.]http://www.debevec.org/Research/HDR/,accessed09/30/2002. [44]S.DabralandT.Maloney. BasicESDandI/Odesign .Wiley,NewYork,1998. [45]J.KesselsandP.Marston.Designingasynchronousstandbycircuitsforalow-power pager. ProceedingsoftheIEEE ,87(2):257,Feburary1999.

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118 [46]Hon-SumWong.TechnologyanddevicescalingconsiderationsforCMOSimagers. IEEETransactiononElectronDevices ,43(12):2131,December1996. [47]A.Gamal,D.Yang,andB.Fowler.Pixellevelprocessing-why,whatandhow?In ProceedingsoftheSPIEElectronicImagingConference ,volume3650,pages2, March1999. [48]M.Furumiya,H.Ohkubo,Y.Muramatsu,S.Kurosawa,andY.Nakashiba.High sensitivityandno-cross-talkpixeltechnologyforembeddedCMOSimagesensor.In IEDMTechnicalDigest ,pages701,2000. [49]Y.Tsividis. OperationandModelingoftheMOSTransistor .McGraw-Hill,New York,1999. [50]R.Yukawa.ACMOS8-bithigh-speedA/D. IEEEJournalofSolid-StateCircuits 20(3):775,June1985. [51]C.EnzandG.Temes.Circuittechniquesforreducingtheeffectsofop-ampimperfections:Autozeroing,correlateddoublesampling,andchopperstabilization. ProceedingsoftheIEEE ,84(11):1584,1996. [52]P.Gray,P.Hurst,S.Lewis,andR.Meyer. AnalysisandDesignofAnalogIntegrated Circuits .4thEd.JohnWiley&Sons,NewYork,2001. [53]J.Shieh,M.Patil,andB.Sheu.Measurementandanalysisofchargeinjectionin MOSanalogswitches. IEEEJournalofSolid-StateCircuits ,22(2):277,April 1987. [54]A.Abidi.Behavioralmodelingofanalogandmixedsignalic's.In Proceedingsof theIEEE2001CustomIntegratedCircuitsConference ,pages443,2001. [55]A.Martin.SynthesisofasynchronousVLSIcircuits. CaltechComputerScience TechnicalReportCS-TR-92-03 ,CaliforniaInstituteofTechnology,Pasadena,CA, 1991. [56]M.Mahowald. VLSIanalogsofneuronalvisualprocessing:Asynthesisofformand function .PhDthesis,CaliforniaInstituteofTechnology,Pasadena,CA,1992. [57]A.Martin.ProgramminginVLSI:Fromcommunicatingprocessestodelayinsensitivecircuits. CaltechComputerScienceTechnicalReportCS-TR-89-01 ,CaliforniaInstituteofTechnology,Pasadena,CA,1989. [58]A.Gamal,B.Fowler,H.Min,andX.Liu.ModelingandestimationofFPNcomponentsinCMOSimagesensors.In ProceedingsoftheSPIEElectronicImaging Conference ,volume3301,pages168,SanJose,California,January1998. [59]D.Yang,H.Tian,B.Fowler,X.Liu,andA.Gamal.CharacterizationofCMOSimage sensorswithnyquistratepixellevelADC.In ProceedingsoftheSPIEElectronic ImagingConference ,volume3650,pages52,SanJose,California,March1999. [60]R.SenthinathanandJ.Prince.ApplicationspecicCMOSoutputdrivercircuitdesigntechniquestoreducesimultaneousswitchingnoise. IEEEJournalofSolid-State Circuits ,28(12):1383,December1993. [61]B.BeeckenandE.Fossum.Determinationoftheconversiongainandtheaccuracyof itsmeasurementfordetectorelementsandarrays. AppliedOptics ,35(19):3471, July1996.


Permanent Link: http://ufdc.ufl.edu/UFE0000540/00001

Material Information

Title: A Time-base asynchronous readout CMOS image sensor
Physical Description: Mixed Material
Language: English
Creator: Guo, Xiaochuan ( Dissertant )
Harris, John G. ( Thesis advisor )
Principe, Jose C. ( Reviewer )
Fox, Robert M. ( Reviewer )
Wilson, Joseph N. ( Reviewer )
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2002
Copyright Date: 2002

Subjects

Subjects / Keywords: Electrical and Computer Engineering thesis, Ph. D.
Metal oxide semiconductors, Complementary   ( lcsh )
Dissertations, Academic -- UF -- Electrical and Computer Engineering
Image processing -- Digital techniques   ( lcsh )

Notes

Abstract: Charge-coupled devices (CCDs) have been the basis for solid-state imaging since the 1970s. However, during the last decade, interest in CMOS imagers has increased significantly since they are capable of offering System-on-Chip (SoC) functionality, lower cost and lower power consumption than CCDs. Furthermore, by integrating innovative circuits on the same chip, the performance of CMOS image sensors can be extended beyond the capabilities of CCDs. Dynamic Range is an important performance criterion for all image sensors. In this work, it is demonstrated that due to fundamental limitations of signal headroom and noise floor, the dynamic range of conventional CMOS imagers is limited to 60-70 dB. However, many scenes have a dynamic range of more than 100 dB. Instead of obtaining illumination information from the voltage domain, as is usually done, a time-based asynchronous readout (TBAR) CMOS imager, is proposed to obtain ultra-high (more than 120 dB) dynamic range. In this imager, the integration time is unique, depending on the illumination level of each pixel. Therefore, by reading out the integration time of each pixel, the illumination level can be recovered. In this dissertation, the signal-to-noise ratio (SNR) and dynamic range (DR) of the conventional photodiode CMOS active pixel sensor is first analyzed. Then, the TBAR imager is proposed to achieve ultra-high dynamic range. The operation of this imager is described to show the high dynamic range capability. Circuit design and analysis are presented. The fabricated TBAR imager is tested and characterized. The dissertation is concluded by a discussion of the future work.
Subject: asynchronous, circuit, CMOS, dynamic, image, imager, range, sensor
General Note: Title from title page of source document.
General Note: Includes vita.
Thesis: Thesis (Ph. D.)--University of Florida, 2002.
Bibliography: Includes bibliographical references.
General Note: Text (Electronic thesis) in PDF format.

Record Information

Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
System ID: UFE0000540:00001

Permanent Link: http://ufdc.ufl.edu/UFE0000540/00001

Material Information

Title: A Time-base asynchronous readout CMOS image sensor
Physical Description: Mixed Material
Language: English
Creator: Guo, Xiaochuan ( Dissertant )
Harris, John G. ( Thesis advisor )
Principe, Jose C. ( Reviewer )
Fox, Robert M. ( Reviewer )
Wilson, Joseph N. ( Reviewer )
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2002
Copyright Date: 2002

Subjects

Subjects / Keywords: Electrical and Computer Engineering thesis, Ph. D.
Metal oxide semiconductors, Complementary   ( lcsh )
Dissertations, Academic -- UF -- Electrical and Computer Engineering
Image processing -- Digital techniques   ( lcsh )

Notes

Abstract: Charge-coupled devices (CCDs) have been the basis for solid-state imaging since the 1970s. However, during the last decade, interest in CMOS imagers has increased significantly since they are capable of offering System-on-Chip (SoC) functionality, lower cost and lower power consumption than CCDs. Furthermore, by integrating innovative circuits on the same chip, the performance of CMOS image sensors can be extended beyond the capabilities of CCDs. Dynamic Range is an important performance criterion for all image sensors. In this work, it is demonstrated that due to fundamental limitations of signal headroom and noise floor, the dynamic range of conventional CMOS imagers is limited to 60-70 dB. However, many scenes have a dynamic range of more than 100 dB. Instead of obtaining illumination information from the voltage domain, as is usually done, a time-based asynchronous readout (TBAR) CMOS imager, is proposed to obtain ultra-high (more than 120 dB) dynamic range. In this imager, the integration time is unique, depending on the illumination level of each pixel. Therefore, by reading out the integration time of each pixel, the illumination level can be recovered. In this dissertation, the signal-to-noise ratio (SNR) and dynamic range (DR) of the conventional photodiode CMOS active pixel sensor is first analyzed. Then, the TBAR imager is proposed to achieve ultra-high dynamic range. The operation of this imager is described to show the high dynamic range capability. Circuit design and analysis are presented. The fabricated TBAR imager is tested and characterized. The dissertation is concluded by a discussion of the future work.
Subject: asynchronous, circuit, CMOS, dynamic, image, imager, range, sensor
General Note: Title from title page of source document.
General Note: Includes vita.
Thesis: Thesis (Ph. D.)--University of Florida, 2002.
Bibliography: Includes bibliographical references.
General Note: Text (Electronic thesis) in PDF format.

Record Information

Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
System ID: UFE0000540:00001


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Full Text











A TIME-BASED ASYNCHRONOUS READOUT CMOS IMAGE SENSOR


By

XIAOCHUAN GUO











A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY


UNIVERSITY OF FLORIDA


2002

















To my parents.















ACKNOWLEDGEMENTS


I would like to express my sincere gratitude to my advisor, Dr. John G. Harris, for

his continued guidance, support, and help throughout the past four years of Ph.D. graduate

studies. Without his patience and encouragement, this work would have been impossible.

He allowed me the freedom to explore by myself, but was always attentive and pertinent

in critical moments. Appreciation is also extended to Dr. Jose C. Principe, Dr. Robert

M. Fox, and Dr. Joseph N. Wilson for their interest and participation on my supervisory

committee. I would like to thank Julian Chen at Texas Instruments for the discussions and

suggestions. Also, many thanks go to Michael Erwin for his designing work in the early

stage of this project. I also would like to thank my colleagues in the analog group and the

Computational Neuroengineering Lab for their discussions of ideas and their friendships.

My wife, Liping Weng, has my deepest appreciation for all the suffering she had to

endure during the past two years, when she was working in San Diego and I was working

on this research project in Gainesville. Only a great love would be able to stand such a long

and involuntary separation, giving the support I needed at the same time. I am especially

grateful to my parents and to my sisters in China for their love and support.
















TABLE OF CONTENTS

page

ACKNOWLEDGEMENTS ................... ...... iii

AB STRACT . . . . . . . . .. vi

CHAPTERS

1 INTRODUCTION ................................ 1

1.1 B background . . . . . . . . 1
1.2 M otivation . .. . . . . . . 2
1.3 Author's Contribution . .. . . . . . 3
1.4 D issertation Structure . . . . . . . 3

2 SOLID-STATE IMAGERS .................. ... 5

2.1 Introduction . . . . . . . . 5
2.2 Principles of Solid-State Imaging .......... . ...... 5
2.2.1 Generation of Charge Carriers ....... . ...... 5
2.2.2 Collection of Generated Charge Carriers .... . 6
2.2.3 Transportation of Collected Charge Carriers . . . 7
2.3 Charge-Coupled Devices (CCDs) . . . . . 8
2.4 CM OS Image Sensors . . . . . . . 9
2.5 Performance Limitations . . . . . . 10
2.5.1 Quantum Efficiency . . . . . . 10
2.5.2 D ark Current . . . . . . . 11
2.5.3 Fixed Pattern Noise (FPN) . . . . . 12
2.5.4 Tem poral N oise . . . . . . 12
2.5.5 Dynamic Range (DR) . . . . . 14

3 TIME-BASED ASYNCHRONOUS READOUT CMOS IMAGER ....... 15

3.1 Introduction . . . . . . . . 15
3.2 SNR and DR Analysis of Photodiode CMOS APS . . 15
3.2.1 Signal Voltage . . 17
3.2.2 Photon Current Shot Noise . . . . . 18
3.2.3 Dark Current Shot Noise . . . . . 18
3.2.4 Photodiode Reset Noise . . . . . 19
3.2.5 Readout Circuit Noise . . . . . 19
3.2.6 Signal-Noise-Ratio(SNR) . . . . . 19
3.2.7 An Example . . . ... ... . 19
3.3 Existing High Dynamic Range Image Sensors . . . 22
3.3.1 Nonlinear Optical Signal Compression . . . 22
3.3.2 M ultisam pling . . . . . . 23









3.3.3 Time-based High Dynamic Range Imagers . . . 24
3.4 Principles of TBAR CMOS Imager . . . 25
3.4.1 High Dynamic Range Capability of TBAR Imager . . 25
3.4.2 Asynchronous Readout. . . . . . 32
3.5 Architecture and Operation of TBAR Imagers . . . 34
3.5.1 TBAR with on-chip Memory: TBARJVIEM . . 34
3.5.2 TBAR without on-chip Memory: TBARBASE . . 38
3.6 Errors Analysis and Simulation . . . . . .. 41
3.6.1 Errors Caused by Limited Throughput of TBAR Architectures 42
3.6.2 MATLAB simulation of errors . . . . 45
3.6.3 TBARBASE imager with throughput control . ..... 54
3.7 Sum m ary . . . . . . . . 60

4 TBAR IMAGER CIRCUIT DESIGN AND ANALYSIS . . 62

4.1 Introduction . . . . . . . . 62
4.2 Pixel D esign . . . . . ..... .. . 62
4.2.1 Pixel Operation and Digital Control Circuitry . ..... 62
4.2.2 Photodiode Design . . . . . . 66
4.2.3 Comparator Design . . . . . . 69
4.3 Asynchronous Readout Circuit Design . . . . 79
4.3.1 Design Methodology . . . . . . 79
4.3.2 Asynchronous Circuit Design . . . . 80
4.4 Timing Analysis . . . . . . . 87
4 .4 .1 R eset . . . . . . . . 87
4.4.2 Pixels Firing Simultaneously . . . . . 88
4.4.3 Finite State Machine Model . . . . . 92
4.5 Sum m ary . . . . . . . . 95

5 TBAR IMAGER TESTING AND CHARACTERIZATION . . 96

5.1 Introduction . . . . . . . . 96
5.2 Testing Setup . . . . . . . . 97
5.3 Testing and Characterization . . . . . . 99
5.3.1 Power Consumption . . . . . . 99
5.3.2 D ark Current . . . . . . . 100
5.3.3 Dynamic Range . . . . . . 101
5.3.4 Temporal Noise . . . . . . 103
5.3.5 Conversion Gain . . . . . . 105
5.3.6 Fixed Pattern Noise . . . . . . 109
5.4 Sum m ary . . . . . . . . 110

6 CONCLUSION .................. .............. .. 113

6.1 Sum m ary . . . . . . . . 113
6.2 Future Directions . . . . . . . 114

REFERENCES .................. ................ .. 115

BIOGRAPHICAL SKETCH .................. ......... .. 119















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy




A TIME-BASED ASYNCHRONOUS READOUT CMOS IMAGE SENSOR


By

Xiaochuan Guo

December 2002


Chairman: John G. Harris
Major Department: Electrical and Computer Engineering

Charge-coupled devices (CCDs) have been the basis for solid-state imaging since

the 1970s. However, during the last decade, interest in CMOS imagers has increased sig-

nificantly since they are capable of offering System-on-Chip (SoC) functionality, lower

cost and lower power consumption than CCDs. Furthermore, by integrating innovative cir-

cuits on the same chip, the performance of CMOS image sensors can be extended beyond

the capabilities of CCDs. Dynamic range is an important performance criterion for all im-

age sensors. In this work, it is demonstrated that due to fundamental limitations of signal

headroom and noise floor, the dynamic range of conventional CMOS imagers is limited to

60-70 dB. However, many scenes have a dynamic range of more than 100 dB.

Instead of obtaining illumination information from the voltage domain, as is usually

done, a time-based asynchronous readout (TBAR) CMOS imager, is proposed to obtain

ultra-high (more than 120 dB) dynamic range. In this imager, the integration time is unique,









depending on the illumination level of each pixel. Therefore, by reading out the integration

time of each pixel, the illumination level can be recovered.

In this dissertation, the signal-to-noise ratio (SNR) and dynamic range (DR) of the

conventional photodiode CMOS active pixel sensor is first analyzed. Then, the TBAR

imager is proposed to achieve ultra-high dynamic range. The operation of this imager

is described to show the high dynamic range capability. Circuit design and analysis are

presented. The fabricated TBAR imager is tested and characterized. The dissertation is

concluded by a discussion of the future work.















CHAPTER 1
INTRODUCTION

In this chapter, the background and motivation of this research project is discussed,

followed by a summary of the author's major contributions. The chapter is concluded with

an outline of the dissertation structure.

1.1 Background

In past decades, personal computer (PC) multimedia and Internet applications have

generated enormous demands for digital images and videos. As a result, there has been

significant research and development on electronic imaging devices.

Today, there are two competing technologies for solid state imaging: charge cou-

pled devices (CCDs) and CMOS imagers. CCDs were invented by W. Boyle and G. Smith

of Bell Labs in 1970. After about 30 years of evolution, CCDs have established a dom-

inant position as the basis for electronic imaging [1]. CCDs are a type of charge storage

and transport device. The basic architecture of CCDs is a closely coupled array of metal-

oxide-semiconductor (MOS) capacitors. The charge carriers are generated and collected

under MOS capacitors and transported. After years of study of CCD physics, technology

and applications, CCDs have found widespread application in the digital imaging area.

Before a resurgence in CMOS image sensors in the 1990s, Weckler [2] and Dyck

[3] introduced MOS image sensors as early as the 1960s. The NMOS, PMOS and bipolar

technologies have been exploited for imaging applications. However, the larger fixed-

pattern noise (FPN) [4] and pixel size made MOS and CMOS image sensors inferior to

CCDs. The resurgence of CMOS image sensors in the 1990s is largely due to the demands

to create highly functional single-chip imaging systems where low cost, not performance,

is the driving factor [5]. Since it is usually not feasible to integrate analog and digital









circuitry using CCD processes, CCD camera systems usually require multiple chips to

implement camera functionalities like analog-to-digital converters (ADCs), timing control

and signal processing. Therefore, system cost and power dissipation for CCDs are usually

higher than for CMOS imagers. After years of effort from both universities and industry,

CMOS imagers are gaining ground in the low-end digital imaging market. Camera-on-a-

chip solutions can be found in Smith et al. [6] and Loinaz et al. [7]. There are also CMOS

image sensors for digital still camera (DSC) applications from 800k-pixel [8] to several

mega-pixel [9].

1.2 Motivation

The motivation of this dissertation work is to present an architecture to improve

the dynamic range (DR) of CMOS image sensors. The DR can be defined as the ratio

of the highest illuminant level to the lowest illuminant level that an imager can measure

and process with acceptable output quality. The DR of conventional CMOS imagers is

usually limited to about 60-70 dB because the photodiode has a nearly linear response to

illuminance and all pixels have the same exposure time. However, many typical scenes

have a DR of more than 100 dB. As the standard CMOS technology keeps scaling, DR

tends to worsen because of the decreased signal headroom.

Since there is no single integration time that is satisfactory for all pixels, we found

dynamic range can be dramatically improved if each pixel has a unique integration time

depending on the illuminant level associated with each pixel. Therefore, time information,

not an electric voltage, is used to represent the illuminant level. To read out this time in-

formation effectively, an asynchronous readout circuit is applied. Compared with common

synchronous digital circuits, asynchronous readout circuits have the potential to achieve

higher speed, lower power, improved noise and electromagnetic compatibility (EMC), al-

though the design of asynchronous circuits is more involved.









1.3 Author's Contribution


The author's main contributions in this work are the following:

1. Analysis of the noise and dynamic range of photodiode CMOS imagers. The
analysis shows the fundamental limitations of dynamic range of the conventional CMOS
active pixel sensor (APS) architecture.

2. Development of a novel time-based asynchronous readout (TBAR) CMOS
imager architecture, which is capable of ultra-wide dynamic range. Some unique is-
sues associated with this architecture are discussed.

3. Design and analysis of this imager in the AMI 0.5 pm CMOS technology.
Some circuit design issues are discussed.

4. The test and characterization of this imager. The testing results prove the
high dynamic range capability of the TBAR imager. Characterization techniques specified
for time-domain image sensors are developed.

1.4 Dissertation Structure

This dissertation comprises six chapters whose contents are outlined below:

Chapter 1 introduces the background and motivation of this research project.

Chapter 2 introduces fundamentals of the solid-state imaging, followed by the dis-

cussion of the architectures and operations of the most important existing solid-state im-

agers.

Chapter 3 analyzes the DR and SNR of the conventional photodiode CMOS im-

agers. This analysis is used to show the fundamental limitations of the DR. Some existing

time-based CMOS imager architectures are then discussed. The principles of the TBAR

CMOS imager are then presented. One unique issue of this architecture, namely the limited

throughput introduced errors, is presented and its influences on image quality are discussed

in detail.

Chapter 4 discusses the design and analysis of the TBAR CMOS imager. There are

three parts in the TBAR CMOS imager: photodiode, analog and digital circuitry. The de-

sign and analysis of each part will be discussed. Detailed timing analysis is also presented.

Chapter 5 discusses the test and characterization of a 32 x 32 TBAR imager fabri-

cated using an AMI 0.5 pm process through MOSIS.






4


Chapter 6 concludes this research projects and discusses the possible directions of

future related research.















CHAPTER 2
SOLID-STATE IMAGERS
2.1 Introduction

This chapter introduces the physics of solid-state imaging. The architectures and

operations of the two most important solid-state imagers, CCD and CMOS active pixel

sensor (APS), are reviewed. The chapter is concluded by the descriptions of performance

limitations of CCD and CMOS imagers.

2.2 Principles of Solid-State Imaging

Solid-state imaging is based on the physical principles of converting quanta of light

energy (photons) into a measurable quantity (electric voltage, electric current) [1]. There-

fore, solid-state imaging is a physical process of generation, collection and transportation

of charge carriers.

2.2.1 Generation of Charge Carriers

If the energy of photons which are impinging on and penetrating into a semiconduc-

tor substrate (silicon for CCD and CMOS technology) is higher than the bandgap energy

of the semiconductor, it can generate electron-hole pairs. The electrons are released from

the valence band, leaving holes behind. We use Planck's relationship between energy and

photon frequency:
C
S= hv h (2.1)

where E is the energy of a photon, h is Planck's constant (6.63 x 10-34 J- s), v is frequency,

c is the speed of light (3.0 x 1010 cm/s) and A is the wavelength of the photon.

To be able to generate electron-hole pairs in semiconductors, the energy of photons

must be greater than the bandgap energy of the semiconductor. For silicon, the bandgap









energy E, is 1.11 eV [10]; therefore, the maximum photon wavelength to which silicon

can respond is as follows:
c
h = Eg (2.2)

he
A h 120nm (2.3)
Eg
which is in the infrared region. The wavelength of visible light ranges from about 350

nm to 750 nm [11]. Thus, silicon is a semiconductor capable of the visible light imaging,

although sometimes a color compensating filter is used to eliminate infrared wavelength

(e.g., see page 98 of Blanksby [12]).

2.2.2 Collection of Generated Charge Carriers

Once electron-hole pairs are generated, an applied electric field separates electrons

and holes. Otherwise, electrons and holes will eventually recombine. On the other hand,

since it is very difficult to measure a single electron or hole, a better way is to integrate

charge carriers into a charge packet over a certain period of time.

Both separation and integration of charges can be done with a capacitor. Two types

of capacitors are commonly used: MOS capacitors and metallurgical p/n junction capaci-

tors. MOS capacitors are used in CCDs and photogate CMOS imagers while metallurgical

capacitors are used in photodiode CMOS imagers. Figure 2.1(a) shows a MOS capaci-

tor. If the gate voltage is high enough, there is a depletion region under the gate. The

photon-generated electrons will be swept towards and stored at the Si SiO2 interface. In

Figure 2.1(b), the p/n junction is precharged to some positive voltage relative to the sub-

strate. When photon-generated electrons are swept towards n-type-silicon, the p/n junction

is discharged and V, begins to drop.

Note there are also electron-hole pairs generated in the neutral bulk of the semicon-

ductor material. Some of these carriers can be collected via diffusion. The efficiency of this

process depends on the wavelength of the impinging light and the diffusion length of the












SGate Vn


Oxide

N+
i \ A T



P Sub P Sub V


(a) MOS Capacitor (b) p/n junction

Figure 2.1: Charge carriers generation and integration in silicon.


semiconductor material. Detailed analysis of charge generation can be found in Chapter 5

of Theuwissen [1].

2.2.3 Transportation of Collected Charge Carriers

Since the amount of charge is proportional to the illuminance level for a given

charge collection time, after the charge carriers are collected, the illumination information

is stored in a charge packet. The next step is to send this information out for measurement

or processing. Since there are usually more than thousands of charge packets (pixels) on

an image sensor, efficiently transporting the information in these packets is a significant

issue.

There are two primary approaches to reading off the many charge packets. One is

to send the charge packets out serially, as is done in a shift register. This is the principle of

charge-coupled devices (CCDs). CMOS image sensors adopt a quite different approach.

Here, the information in the charge packets is multiplexed onto a sensing line that is shared

by many pixels. The detailed operations of CCDs and CMOS imagers will be discussed in

the next two sections.










2.3 Charge-Coupled Devices (CCDs)

As shown in Figure 2.2, CCDs consist of many closely coupled MOS capacitors.

By properly clocking the gates (1, 02, ..., ) of these MOS capacitors, charge can be

transported from the photon-collecting site to the readout site serially.

Light Shield
light 91 92 93 n q
light Readout





\ / \ -
n


P Substrate


Figure 2.2: Readout structure of CCD.


Since a charge packet has to undergo hundreds of transfers before it can reach the

output site, the transportation must be nearly perfect between two adjacent MOS capaci-

tors. If the charge transport efficiency is defined as the part of a charge packet transported

through a CCD cell, normalized to the original charge packet that had to be transported,

the charge transport efficiency has to be very close to 1 for a properly working CCD. To

understand why this is true, if the charge transportation efficiency is only 9' and there

are 500 CCD cells, only 0. -.1.'. of original charge carriers will reach the readout site.

The nearly perfect charge transportation requirement makes the technology for

CCDs somewhat more complicated. The complexity is a result of the relatively large

number of technological steps and the consecutive relatively large throughput time in the

production facilities [1]. As a result, CCD technology is more costly than CMOS technol-

ogy. Furthermore, to provide nearly perfect charge transportation, proper timing is crucial.

Many CCDs use several different supply voltage for timing clocks, which adds further

system complexity.










2.4 CMOS Image Sensors

Unlike CCDs, CMOS imager sensors are built upon standard CMOS technology.

Since it is not possible to get nearly perfect charge transport devices with standard CMOS

technology, most CMOS imagers use XY addressable architectures, as shown in Figure 2.3,

where a row/column address selects a particular pixel to read out. In Figure 2.3, the two-

dimensional spatial information in each pixel can be addressed by row and column de-

coders. When the row decoder selects one line (RowSelectm is high), the MOS switches

associated with each pixel are turned on. All the pixels in the selected row will put their

information on the corresponding column line. The information on each column line is

then processed by sample-and-hold and other signal processing circuits associated with

each column. The column decoder is used to select which column to output.

Column 1 Column 2 Column 3

Row Select 1
pixel pixel pixel


Row Select 2
pixel pixel pixel


Row Select 3
pixel pixel pixel


Sampling and Hold and Signal Processing


Column Decoder


Figure 2.3: Readout architecture of CMOS addressable image sensor.


Note in Figure 2.3, a column line is shared by many pixels in the same column. The

parasitic capacitance on this column line is much larger than the photon-sensing capacitor

inside each pixel. To deal with this problem, usually a buffer is added into each pixel.

These kind of sensors are therefore called active pixel sensors (APS).









Vdd Vdd

Rst
M1 M2



D1 Sel M3
SColumn
Output

Figure 2.4: Pixel schematic of a photodiode APS.

One of the commonly used APS architectures is the photodiode APS [5]. The

schematic of a pixel is shown in Figure 2.4. There are a photodiode and three MOS tran-

sistors inside each pixel. Reset transistor Ml is used to precharge the photodiode. M2 is

a voltage follower, acting as a buffer between the small capacitance of the photodiode and

the large capacitance of the column line. M3 is a switch to select the pixel.

Arguably the biggest advantage of CMOS image sensors is their capability of inte-

grating many circuits onto the same chip. CCD imagers usually consist of several chips for

readout amplification, timing control, analog-to-digital conversion and signal processing.

As a result, system complexity and cost are increased. On the contrary, it is quite easy to

integrate all these functions onto the same chip for CMOS image sensors by using standard

CMOS technology.

2.5 Performance Limitations

To properly design a solid-state imager, it is very important to understand perfor-

mance limitations, which primarily include quantum efficiency, dark current, fixed pattern

noise (FPN), temporal noise and dynamic range.

2.5.1 Quantum Efficiency

Quantum efficiency rT is defined as the number of collected electrons divided by

the number of photons impinging on the device. Since not every photon can generate an









electron which reaches the collecting region, quantum efficiency is always smaller than 1.

Quantum efficiency is also wavelength dependent. More detailed discussion of quantum

efficiency can be found in Theuwissen [1].

2.5.2 Dark Current

Even if image sensors are not illuminated at all, a small number of charge carriers

are still generated and collected by the pixels. This effect is called the dark current, Jdark,

in A/cm2.

The dark current is due to the thermal generation of charge carriers. It can happen

either at the SiO2 Si interface or in the bulk of the silicon; however due to the large

irregularity at the SiO2 Si interface, this interface is considered to be the principal

source of dark current. The dark current has two effects on image sensors. Because dark

currents vary from pixel to pixel, nonuniformities are introduced, which contribute to the

fixed pattern noise (FPN). On the other hand, like any other current, there is shot noise

associated with dark current. Dark current shot noise is part of the total temporal noise and

deteriorates the sensor's signal-to-noise-ratio (SNR) and dynamic range.

Since dark current is a thermal generation process, it is highly dependent on tem-

perature, doubling every 80C. In order to achieve an extremely small dark current in some

applications, the imager sensors are cooled down. Another way to achieve smaller dark

current is to isolate the photon-collection area from the SiO2 Si interface. It is called

pinned photodiode technology. Many CCDs use this technology to decrease the dark cur-

rent. Some CMOS imagers using this technology can be found in Guidash et al. [13],

Inoue et al. [14], and Yonemoto et al. [15]. However, extra implantation steps are usu-

ally needed. Depending on different technologies, dark currents vary over a wide range.

Dark currents range from 3 pA/cm2 to 100 pA/cm2 for CCDs, and from 206 pA/cm2 to

4 nA/cm2 [12] for photodiode CMOS imagers.









2.5.3 Fixed Pattern Noise (FPN)

Due to the device and circuit nonuniformity between pixels, there is a static pattern

even if the imager is under uniform illumination. This is called fixed pattern noise (FPN)

because this pattern is a spatial random process. The most important components of FPN

are the following:


Dark Current FPN

As explained in the last subsection, the dark current is a process of thermal gen-

eration of charge carriers. Because neither generation sites nor generation rates are

uniform, the dark current is also nonuniform. Dark current FPN is a dominant source

of FPN in low light conditions [16].

Pixel Response FPN

Due to the nonuniformity of geometry, layer thickness, doping levels or doping pro-

file, the photon response is different from pixel to pixel. This phenomenon is more

obvious in high light conditions.

Readout Circuit FPN

This problem is much less severe for CCDs because all the pixels share the same

readout circuit. For CMOS image sensors, each pixel experiences a different readout

path. Any nonuniformity of readout path will cause FPN. However, by applying a

double-delta-sampling (DDS) [17] circuit, it is reported [16] that the FPN of readout

circuit can be suppressed to a level negligible compared to dark current FPN and

pixel response FPN.

2.5.4 Temporal Noise

Like any electronic system, the solid-state imager is not immune to noise. Temporal

noise sets the lowest level of illuminance which sensors can detect. The major components

of the temporal noise are:









* Dark Current Shot Noise

The dark current is due to the collection of randomly generated charge carriers,

which can be described as a Poisson random distribution [1]. For Poisson distri-

butions, the variance is equal to the mean of the distribution [18]. If the dark current

charge is Qdark, then the dark current shot noise is (in number of electrons) dark:



dark = Qc k (2.4)

Dark current shot noise can also be expressed in voltage as

lndark q VQdark (
Udark = (2.5)
C C

where C is the total capacitance at the photodiode, which includes the photodiode ca-

pacitance, the drain capacitance of M1 and the gate capacitance of i /. in Figure 2.4.

* Photon Current Shot Noise

As is the case for dark current shot noise, the charge carrier distribution due to

photon-generated current is also a Poisson distribution. Therefore, the photon cur-

rent shot noise (in number of electrons) nphoton is


nphoton r hot (2.6)


* Photodiode Reset Noise

As shown in Figure 2.4, before the integration of charges, photodiode D1 is reset by

transistor M1. Due to the channel thermal noise of MI, there are voltage fluctuations

on the photodiode each time D1 is reset. Because of the nature of thermal noise, the

reset noise can be expressed (in voltage) [19] as


Vreset = (2.7)









where k is Boltzmann's constant (k = 1.38 x 10-23J/K) and T is the temperature

in Kelvin. If the reset noise is expressed in number of electrons:

Qreset -resetC VlTC (
reset = (2.8)
q q q

Readout Circuit Noise.

To convert photon generated charge carriers into a measurable electric voltage and

current and to buffer signals to the outside world, both CCDs and CMOS imagers

need readout circuits. Readout circuits will inevitably introduce noise due to the

thermal noise and 1/f noise ofMOS transistors.

2.5.5 Dynamic Range (DR)

Dynamic range (DR) is another important performance criterion. It is defined as the

ratio of the maximum measurable signal (saturation level) to the noise floor. The saturation

level of CCDs is usually limited by the charge well capacity, while the saturation level of

CMOS imagers is limited by the power supply voltage. The noise floor is the total noise

when there is no signal. It consists of dark current shot noise, reset KTC noise and readout

circuit noise. Because these three noise sources are independent in nature, the noise floor

in number of electrons can be expressed as

p 1.ark + Preset + Qread (2.9)

where nread is equivalent readout circuit noise in number of electrons. The noise floor can

also be expressed in volts:



Floor = Vark eset + ead (2.10)

where Vread is readout noise in voltage. If vsat is the signal saturation level of the photodi-

ode, DR (in dB) is
2
Vsat v2t
DR 20 log st 10 log v st (2.11)
Floor ark + Vreset + read
The DR of CMOS imager sensors will be discussed further in the next chapter.















CHAPTER 3
TIME-BASED ASYNCHRONOUS READOUT CMOS IMAGER
3.1 Introduction

In this chapter, a time-based asynchronous readout (TBAR) CMOS imager will

be presented at the system level. At first, the dynamic range of the standard photodiode

CMOS active pixel sensor (APS) is analyzed to show the dynamic range limitations of

this architecture, followed by a discussion of various existing approaches for improving

dynamic range. The center part of this chapter is the demonstration of the principles of

the TBAR CMOS imager. One unique issue of the readout architecture is that errors are

introduced when the throughput of the readout circuit is too low to accommodate the array

firing rate. This issue will be analyzed in detail. The simulation results show that the

introduced errors are negligible for moderate size high dynamic range scenes.

3.2 SNR and DR Analysis of Photodiode CMOS APS

The photodiode active pixel sensor (APS) is the most commonly used CMOS im-

ager architecture. In this section, the SNR and DR of the photodiode APS will be analyzed

in detail to show the limitations to DR of the APS architecture.

Figure 3.1 shows a schematic of a photodiode APS pixel and the associated readout

circuit. As explained in Chapter 2, Ml is used to precharge the photodiode Dl. After Ml

turns off, the cathode of the photodiode becomes floating. Photogenerated electrons will

begin to discharge the photodiode. M2 is used to buffer the photodiode voltage to the

column line, which is shared by all the pixels in the same column. M3 is a switch, and the

pixel will put its signal voltage on the column line when M3 is on. M4 is used to set a bias

current for the column line. The signal voltage on the column line then goes through other

analog signal processing and analog-to-digital converter (ADC) circuits.










Pixel Column
Vdd Vdd Lie


Reset
M2



D1 Sel M3
D, IDl M3


Analog Signal
Vout Processing and
ADC

Vbias M4



Figure 3.1: Schematic of Photodiode Active Pixel Sensor (APS).


As explained in Chapter 2, SNR can be defined as


2
SNR 10log 2 (3.1)
Uph U Udark r Ureset U Uread
The DR in Equation 2.11 is repeated here for convenience:


2
DR = 10 log 2 sat (3.2)
Dark + Vreset Uread
where


vsig: The photon introduced signal (in volts).


vph: Photon current shot noise (in volts).


Vdark: Dark current shot noise (in volts).


vreset: Photodiode reset noise (in volts).


Vread: Readout circuit noise (in volts).









vsat: The saturation (maximum) signal (in volts).

To calculate dynamic range, each of the components in Equation 3.2, Vsat, Vdark,

Vreset and Vread needs to be determined. To do this, some terms are defined:


L: Incoming light illuminance (in lux, 1 lux = 1/683 W/m2).

A: Photosensitive area of photodiode (in m2).

Tl: Quantum efficiency.


Jdark: Dark current per unit area (in A/m2).

A: Wavelength (in m).

Tint: Integration time (in s).

Cph: Total capacitance at the cathode of photodiode (in Farads).


Since the quantum efficiency is a function of wavelength, to simplify analysis, im-

pinging light is assumed to be monochromatic green light (A = 555 nm = 5.55 x 10-7 m).

3.2.1 Signal Voltage

The number of photons per unit time with light illuminance L is

LA
N = 683 (3.3)
hv

Photon current Iph is


Iph Nr]q (3.4)
LA 1
683 Tq (3.5)
hv
A1
A^-
S683 qL (3.6)
hA









where h is Planck's constant, v is photon frequency and c is the speed of light. If the

integration time is Tirt, the signal voltage at the photodiode is

SphTint
sg ph(3.7)

However, the readout architecture in Figure 3.1 limits the signal range. The maximum

signal range is roughly

Vsig,max = Vdd Vth,M1 Vth,M2 Vsat,M2 Vsat,M4 (3.8)

where Vdd is the power supply voltage. Vth,M1 and Vth,M2 are the threshold voltages of

Ml and M2, respectively. Due to the back gate effect, Vth,M1 and Vth,M2 are functions

of photodiode voltage. Vsat,M2 is the overdrive voltage of M2. Vsat,M4 is the necessary

voltage between drain and source to make sure M4 is working in the saturation region for

a given bias current. Thus, the true signal is the minimum of v'ig and Vsig,max:

Vsig = min(vig, vsig,ma,) (3.9)
3.2.2 Photon Current Shot Noise

As shown in Equation 2.6,the photon current shot noise (in number of electrons)

photon phint
nphoton P= = i hT(3.10)
q q
Photon current shot noise (in volts) can be expressed as

photon
Vph = (3.11)
cph

v/ph (3.12)
Cph
3.2.3 Dark Current Shot Noise

The dark current of a pixel

Idark JdarkA (3.13)

From Equation 2.5, dark current shot noise is

Vdark = Qdakt qdakA t (3.14)
Cph Cph Cph









3.2.4 Photodiode Reset Noise

The reset noise Equation 2.7 is repeated here:


reset kT= (3.15)
Cph
3.2.5 Readout Circuit Noise

Readout noise is the total thermal and 1/f noise of M1,M2 and M4, plus the noise

from the analog signal processing and ADC circuits [20]. The detailed analysis of readout

noise has been done by Degerli et al. [21].

3.2.6 Signal-Noise-Ratio(SNR)

The full expression for SNR can now be written as

2
SNR = 10 log 2 2 2 (3.16)
Vph + Vdark + Vreset + Vread
(min(v' ,Vsig,max})2
= 10 log (3.17)
l phTintq qJdarkATint kT 2
C2 + C 2 + +Vread
ph ph h
3.2.7 An Example

In order to demonstrate the relative importance of various noise sources and SNR,

the data of a typical photodiode imager are used here as an example:

A CMOS imager implemented using AMI 0.5 pm technology with:


Photosensitive area of photodiode: A = 14 pm2


Quantum efficiency: l = 0.4, at A = 0.555 pm.


Mean dark current Jdark = 1 nA/cm2.


Integration time Tit = 30 ms.


Total capacitance at the cathode of the photodiode Cph = 5 fF.


* Signal saturation voltage: vsig,max = 1 V.











* Readout circuit noise is assumed from [20]: ,,red = 300 pV.


From Equation 3.6 and Equation 3.13, photocurrent Iph


3.66 x 10-15 A/lux,


and dark current is 0.14 x 10-15 A/pixel. The photocurrent and dark current are shown

in Figure 3.2. While the mean dark current is constant, photocurrent is proportional to

illuminance in this model. Also note that scene illuminations range from 10-3 lux for

night vision, 102 to 103 lux for indoor lighting, to 105 lux for bright sunlight, to higher

levels for direct viewing of other light sources such as oncoming headlights [22].


2
Photocurrent and Dark Current vs Luminance (A=14 pL m2, QE=0.4, wavelength=555nm)




. .. .. . '. .. .. .. .... ... .. . .. . .. .. . ... . . .. ... .. ... . ....








Phkotocurrent








i ~ ~ ~ ~ ~ ~ . .ii l i i l i i l i i l i i i i l i i i i i l i i i i i l i i i i i


100 101 102
Luminance (lux)


10-8


10-9


10-10



10
10-11

E




3
10-12
0 10-13
s 10
0


10-14


10-15


10-16


10-17


Figure 3.2: Photocurrent and dark current as a function of illuminance.



In Figure 3.3, signal, various sources of noise and total noise (in Volts) are shown.

In the low light region, KTC reset noise is the dominant noise source. As illuminance level


103 104 105 106













Signal and Noise vs Luminance (Cph=5fF,Tint=30ms)
















-.:....: S.R . : : s




. .. .. . .. T o ta l N.is. . ... . . ..
: : :: ::i:i :i i i i i: :::: :::::::::: :::::::j \ : : : i : i : i :: :: : : :::: :::: : i :::::::i : :: K r s i : ::::: :::::: :::: :: ::: ::


.... ..:.: ...:...:..: : ::.:.:.. .. .:.. K T C ....: .
















.. .. .. ..Readout Noi .
S ': : :- : ': ':: ': : : h o 6 o oq u l re~n tl S h N O :: s e : ::: ': :::: : : : : : : : : :: : '* *: : : : :: : ::: : : :: : :::: ::





: :: : : :: : : : : : : : : : : : : : : : : : D ark current S:hot N oise : : : : : :









-210-1 10 10 102 103 1
Luminance (lux)
". . . . . . . ." "
. . . . . . . . . . .
. . . . . . . . . . .
'" "'' "' '' Total Noi s"
. . Noise' 'or
. . . . . . .
s s s s" "
.. .. .... ..... ... ... K T C m se t:N o is
: :: : :: ::: : :: .::: :::.P h : :tb / ::u rr en t:: :.::h. ::t Nb : :: I se:.
~ ~ ~ ~~~ ~ ....Readout Noise ..
~ ~-~-~~~-~-- -. -- -- ~ ~-~--~~- ~ ~ Darkc-- urrent S~-~--hot. N~-oi~-s~~e
. . . . . . . .
'""' "' "".... .......D~
. .. .. .. . . .. . .
" ~ " s ss"


-2 10- 1 10 0 10 1 10 2 10 3 1' '" "

'"" Sin~~l Luminance (lux)


Figure 3.3: Signal and temporal noise as a function of illuminance.



increases, photocurrent shot noise becomes more and more important. Also the noise floor


can be easily calculated as


Floor = vdark _+ reset + Vead 0.97V


(3.18)


The DR of the APS is the ratio of the photodiode saturation voltage to the noise floor:


2 1V2
DR 10 log vsigmax 10 log 60dB (3.19)
Vf2o 0.97mV2
floor

From Equation 3.19, in order to increase dynamic range, either the photodiode saturation


voltage needs to be increased or the noise floor to be decreased. As mentioned before, the


photodiode saturation voltage is limited by the power supply voltage, which is continually


scaling down for CMOS technology, driven by low-power and low-voltage requirements


0
> 10
0)
10
z
Vo


r)10
w,









for digital circuits. Also, from the expression of the noise floor in Equation 3.18, it is very

difficult to decrease any of the components. Therefore, it is very hard for the conventional

CMOS APS architecture to achieve high dynamic range (beyond 80 dB). Existing CCD

imagers have a dynamic range from 60 to 80 dB, while the dynamic range of CMOS

imagers is usually lower than 70 dB [12, 15].

3.3 Existing High Dynamic Range Image Sensors

From the dynamic range analysis of the last section, the DR of the conventional

CMOS imager is usually less than 70 dB. For consumer photography film, the dynamic

range is about 60 dB [23].

However, scene illuminations have a much higher dynamic range than 60 dB. A

typical scene encountered in an outdoor environment can easily have a dynamic range of

more than 100 dB. To deal with such a wide range of illuminance levels, researchers have

proposed a number of solid-state imagers intended for high dynamic range applications.

3.3.1 Nonlinear Optical Signal Compression

As shown in Figure 3.2, the photodiode photocurrent is a linear function of illumi-

nant level to the first order. Since signal voltage can only have a dynamic range of 60 dB as

explained in the last section, if there is a linear mapping between photocurrent and signal

voltage (as in conventional CMOS and CCD architectures), the dynamic range of the illu-

minant level is also limited to 60 dB. To extend the dynamic range, nonlinear compression

between photocurrent and signal voltage has been proposed by some researchers.

In Mead's photodiode [24], the photocurrent is fed into the source of a diode-

connected MOS transistor in the weak inversion region, where transistors have a loga-

rithmic current-voltage characteristic. The resulting voltage is logarithmically related to

the light intensity and a DR of more than 100 dB can be achieved. However, this archi-

tecture is very sensitive to device parameter variations and noise. Any small fixed pattern









noise (FPN) and temporal noise in the voltage domain results in much larger variations in

light intensity domain due to the nature of the signal compression.

To reduce FPN, some researchers proposed on-chip FPN cancellation. In Loose et

al. [25], the calibration information is stored on a capacitor inside each pixel. The FPN is

reduced to;: of a decade, which is about 1('. linearly. In Kavadias et al. [26], a simpler

on-chip calibration is used. Each pixel is readout twice: one is stimulated by photocurrent,

the other is stimulated by a reference current. The difference of the two readouts will

cancel the most important source of FPN: threshold voltage variations of MOS transistors.

The calibrated FPN is 2.5'. of saturation level. Since the authors claimed it is sensitive to

6 decades of light, the FPN is 15' of a decade, which corresponds to 14(1' error linearly.

Other signal compression methods besides logarithmic compression are possible.

In Decker et al. [27], the sensor's current versus charge response curve is compressed by

a lateral overflow gate, e.g., the reset transistor gate in a CMOS APS. The charge col-

lection well capacitor is adjusted by the overflow gate voltage. The imager achieved an

optical dynamic range of 96 dB. FPN is reduced to 0.2 !' of saturation level by applying

correlated-double-sampling (CDS) circuits.

3.3.2 Multisampling

The idea of multisampling is to capture the details of high light regions by using a

short integration time and the details of low light regions by using a long integration time.

A high dynamic range image can be achieved by combining two or more images captured

at different integration times. Yadid et al. achieved a dynamic range of 109 dB by dual

sampling [22]. In Yang et al. [28], 96 dB dynamic range is obtained by sampling nine

times, with integration time doubled each time.

One obvious requirement for multisampling methods is the scene must be still.

Another difficulty arises when combining different samples into a high dynamic range

image. The multisampling imagers in Yadid et al. [22] and Yang et al. [28] assume strict

linear response of signal voltage to illumination. However, in the actual photodiode APS,









the relationship between signal voltage and illumination is only approximately linear due

to the nonlinear nature of the photodiode capacitance and the gain of the readout circuits.

Therefore, some errors will inevitably be introduced when trying to recombine samples

linearly.

3.3.3 Time-based High Dynamic Range Imagers

Unlike the conventional CMOS APS imager, time-based imagers get optical illu-

mination information from the time domain. In Yang's work [29], the photodiode voltage

is compared with a fixed reference voltage. Once the reference voltage is reached, the pixel

outputs a pulse and is then reset. Basically, each pixel acts as a free-running continuous

oscillator. A brighter pixel outputs pulses more frequently than a darker pixel. The time

interval between pulses represents the illuminance level on that pixel. The pulses are read-

out column by column. An asynchronous counter on each row counts the output pulses

for a fixed time. The time interval between pulses can be calculated from the number of

pulses during this fixed time and the light illuminance can be recovered. A dynamic range

of 120 dB was achieved. One problem associated with this architecture is the very long

time needed to readout a frame.

Instead of reading out these pulses by a number of counters, these pulses can be

sampled out [30]. The sampling of a free-running oscillator is equivalent to a synchronous

first-order E A modulator. The author claims that acceptably low number of samples

(8k) are required to achieve a high dynamic range of 6k + 25 dB by sweeping through a set

of binary weighted frequencies. A dynamic range of 104 dB is achieved if the minimum

sampling frequency is 1 Hz.

In Culurciello et al. [31], a quite different readout scheme was used. When a pixel

output a pulse, the address of this pixel is readout using an address-event circuit [32].

This process is also continuous because, in contrast with conventional CMOS APS imager,

there is no global imager reset that signifies the start of a frame. Like Yang's work [29], by

measuring the time interval, the illuminant information can be reconstructed.









In Brajovic et al. [33] and Ni et al. [34], histogram equalization imagers were

implemented by storing a cumulative histogram information on a capacitor inside each

pixel. If a time stamp information is stored instead, it can be used as a high dynamic range

imager.

3.4 Principles of TBAR CMOS Imager

In this section, the principles of time-based imagers are first demonstrated to show

how high dynamic range is achieved [35]. Then, the motivations for the proposed asyn-

chronous readout architectures are presented [36].

3.4.1 High Dynamic Range Capability of TBAR Imager

To avoid ambiguity, all the signal voltages in the drawings and equations in this

chapter are the photocurrent introduced voltage drops across the photodiode. Let Vph de-

note the actual voltage at the photodiode in Figure 3.1, if the initial voltage (right after

resetting the photodiode) is Vrest, the signal voltage is


Vsig = Vreset Vph (3.20)

This relationship is clear from Figure 3.4. The photodiode is reset (precharged) to

V,,et initially. At To, the reset transistor is open and the photocurrent begins to discharge

the photodiode. The voltage at the photodiode begins to drop. If the signal voltage Vsig is

defined as shown in Figure 3.4, Vig is nearly proportional to the illuminance level and the

integration time, which is convenient for analysis.

From the SNR and DR analysis in Section 3.2, the fundamental factors limiting

the dynamic range (DR) of conventional CMOS imagers [37] are the photodiode's nearly

linear response and an exposure time that is the same for all pixels. To make this point

clearer, the data from the example in Section 3.2 are used here to show the response of a

photodiode under various illuminance levels.
















Vsig

TOTime

STint
Vsig 0







TO f Time

Figure 3.4: Relationship of photodiode voltage and signal voltage.


As shown in Figure 3.5, since the photodiodes in most CMOS imagers operate in

integration mode, the signal level of each photodiode increases with time at a rate propor-

tional to the illuminance on that photodiode. After a pre-determined exposure time (which

is the same for all pixels), the analog signal level across each photodiode is read out.

In Figure 3.5, the signal saturation level is 1 V and photodiode noise floor is 0.97

mV (see Equation 3.18). If we fix the exposure time for all pixels and assume that the

minimum acceptable SNR is 1 (0 dB), the maximum dynamic range is about 60 dB (

201og(1V/0.97mV) ), no matter which integration time is chosen. For example, if the

integration time is set to be 14 ps, information for pixels with illuminance below 100 lux

and above 105 lux is lost. While the integration time can be increased to 14 ms to capture

the information of pixels with illuminance as low as 0.1 lux, pixels with illuminance above

100 lux are all saturated, and the optical DR is still 60 dB.

As an example to illustrate how the TBAR imager achieves a high dynamic range,

consider the situation in Figure 3.6. In Figure 3.6 (a), four pixels are located at addresses











Signal Voltage at Photodiode vs Integration Time under Various Illuminance


Figure 3.5: The r
tional CMOS image


100






10-1


0
Ia

0-

10-2
c
0)

10-3





10-4
10-7


;e for conven-


(mT, ni), (Tm2, n2), (m3, r3) and (m4, n4), with illuminance of L1, L2, L3 and Lo, respec-

tively. Instead of reading out the analog voltage across each photodiode at a predetermined

exposure time, there is a comparator inside each pixel. When the voltage on a photodiode

Vph drops below a global reference voltage Vrf (or equivalently, when signal voltage rises

above a global signal reference Vsig,ref), the comparator inverts, and the pixel generates

a pulse (i.e., it has "fired"), as shown in Fig.3.6(b). After a pixel has fired, it is disabled

for the rest of the frame. The time at which a pixel fires is uniquely determined by the

illuminance on that pixel. For example, if the illuminance Lk at a pixel is k times larger

than the unit illuminance Lo, the signal voltage is proportional to the integration time and

illuminance until saturation:


10-6 10-5 10-4 10-3 10-2 10-1
Integration Time (s)

response of typical photodiodes under various illuminan(
gers.
















ti t2 (a) t3


t2 (b)
(m2 ,n2)


N


(m3 3) (m4 ,n4)


I N


Figure 3.6: Scheme for TBAR imager.


Vs, STintL


(3.21)


where S is the sensitivity (V/(lux second)) of the photodiode optical response. The
integration time tk for pixel with illuminance Lk is


k V sig,ref
SLk


(3.22)


Since the reference level is same for all pixels, from Figure 3.6(a),


Lktk = kLotk = LoTo


Vsig,ref
S


(3.23)


Thus, the relative illumination level k:


(3.24)


Output
Request


Address
Encoder
Output


Time(log)




Time(log)


ti

( )


Time(log)









So, for two pixels at addresses (mi, ni) and (m2, n2) with illuminance Li and L2 that fire

at times t1 and t2, respectively, they have the following relationship:


L1 t2
L '2 (3.25)
L2 tl

Thus, the illuminance is computed from the measured time domain information. In

this way, an analog-digital converter (ADC), which is required for conventional imagers to

output digital values, can be replaced with a digital counter that reports the time when each

pixel fires. As shown in Fig.3.6(c), the imager must also report the positions (addresses) of

the pixels as they fire to the receiver (PC or DSP processor) in order to reconstruct images.

Since each pixel has a unique integration time, which is determined by its illu-

minance level (as shown in Equation 3.22), DR is no longer limited in the same way as

are conventional images in Figure 3.5. As evident from Equation 3.25, in this time-based

scheme with fixed reference voltage, the dynamic range is the ratio of longest and shortest

firing time:


L longest
DRmax = 20 log Lmix 20 log ogest (3.26)
Lmmin shortest
To get a rough idea of how wide a dynamic range that a single pixel can achieve,

consider the following example. Suppose the pixel operates in still imaging mode, the

longest pixel integration (firing) time is limited by the dark current in this case, which is

usually a few tens of seconds. From our measurement results of a TBAR imager, this time

is no less than 20 seconds. On the other hand, the shortest integration time is designed to

be 1 ps in our TBAR imager implementation,. This will give a single pixel dynamic range

of more than 140 dB (20 log(20s/1ps) = 146 dB).

The dynamic range of an image array is more involved. If each pixel's light integra-

tion time can be accurately recorded, dynamic range of an array is same as that of a single

pixel. However, as we will see later, practical issues put limitations on readout circuits,

and as a result, readout circuits may introduce errors to the integration time. Therefore,









the dynamic range of an image array is determined by the readout circuit architecture, the

amount of acceptable errors, the size of the images and the nature of the scenes. This topic

will be further discussed.

Another advantage of the time-based imager operating in the still imaging mode is

the higher SNR than conventional APS CMOS imagers. To see why this is true, the SNR

expression in Equation 3.17 is repeated here:
2
SNR 10 log 2 2 ^2 V2 (3.27)
Vph + Vdark + Vreset + Vread
S(min(v, vsig,max))2
= 10 log (3.28)
IphTintq qJdarkATj.t kT 2
C^h2 + C2 + +Vread
Cph Cph Cph
Since the photocurrent shot noise (in number of electrons) is proportional to the square

root of the signal (in number of electrons) as in Equation 3.10, the photocurrent shot noise

is the dominant noise source during moderate or high light situations (which is obvious

from Figure 3.3). Equation 3.28 can be approximated as



SNR h 10 log s(m ( i )) 10 llog Cp (3.29)
IphTintq q
C2
ph
Thus SNR is proportional to the photodiode signal level Vsg. For the TBAR imager sce-

nario shown in Figure 3.6, the signal level of every pixel reaches the signal reference level

Vsig,ref when the pixel fires. Since Vsg,ref can be very close or equal to the maximum sig-

nal level, the SNR of each pixel is the same and is close or equal to the maximum possible

SNR. On the contrary, for the conventional CMOS APS imagers, as shown in Figure 3.5,

because the integration time is fixed for all pixels, the signal levels (which are always

smaller than maximum signal level) of pixels with different illuminance will be different.

For pixels with low light illuminance, the SNR is much smaller than the maximum possible

SNR (10 log(CphVig,max)/q) due to the small signal level.

For video applications, the achievable maximum integration time is limited by the

video frame time, which is a few tens of milliseconds (e.g., 30 ms). This may limit the










dynamic range if a constant reference voltage is used as in Figure 3.6. However,the dy-

namic range can be increased by varying the reference voltage appropriately. Also, under

room light conditions, the illuminance is often not strong enough to cause many pixels to

fire within a frame time with a constant, high reference voltage, and information of these

pixels would be lost. By varying the reference voltage [34], the imager can guarantee that

these pixels fire.

Photodiode
(Log) -Vref
Vsig,ref --------- --


L| L,


Time(log)
t t2 t3 t4 Tframe
(a)
Output
Request
Time(log)

ti t2 t3 t4
(b)

Address (mn ) (m2 ,2) (m3 ,n3) (m4 n4)
Encoder Tim
Output
Oupu Time(log)
ti t2 t3 t4
(C)

Figure 3.7: Varying reference voltage for a wider dynamic range in video mode.


To illustrate this idea, consider the example in Figure 3.7. If the frame time is

Tframe and the reference signal voltage is kept constant at Vig,ref, any pixel with illumi-

nance below L3 does not fire within Tframe, so the imager cannot process and output valid

data about those pixels. However, if the reference voltage is swept as shown, pixels with

illuminance below L3 (such as L4) will fire by the end of the frame, so the imager can out-

put data (pixel firing times and addresses) that, along with the known reference voltage at









that time, will allow those pixels' illuminance to be found. The disadvantage of perform-

ing this operation is that the pixels with an illuminance below L3 will now fire at a lower

signal level, so they will have a worse SNR than the pixels that fired when the reference

voltage was higher (as mentioned above). However, conventional APS imagers also suffer

from a degraded SNR for pixels at low illuminance levels, but without the advantage of an

increased dynamic range.

In the TBAR architecture, the analog photodiode voltage is converted into a digital

pulse inside each pixel. This approach brings several advantages. Firstly, in conventional

CMOS APS architectures, analog signals have to go through a voltage follower, sample-

and-hold, gain amplifier and ADC before being converted into digital values. During this

long analog signal path, various noises are inevitably introduced. Since the analog pho-

todiode voltage is converted into a digital value at a very early stage, this architecture is

much less sensitive to various noise sources. Another advantage comes from the power

consumption point of view. The power consumption of sampling and hold, gain ampli-

fier and ADC of the CMOS APS comprises most of the imager power budget [7]. On the

contrary, none of these power hungry components are needed in the TBAR architecture.

The most power hungry components are thousands of comparators, one inside each pixel.

However, by making the MOS transistors of the comparators work in the subthreshold

region of MOS transistors, low-power consumption can be achieved.

3.4.2 Asynchronous Readout

For a time-based image sensor, after digital pulses are generated inside each pixel,

the next step is to correctly record the firing time of each pixel. This is not a trivial task

considering there are tens of thousands pixels and image sensor pixel firings are massively

parallel. This time recording process can be considered as a time-domain analog-to-digital

conversion (ADC) because the continuous firing time has been converted to digital numbers

of a counter.









The recorded firing time information must be accurate, otherwise, errors will be

introduced when images are reconstructed using the recorded time. If the throughput of

the readout channels is not high enough, some fired pixels will have to wait to get their

firing time recorded. In this situation, some errors are introduced to their time records.

Researchers have proposed several approaches. In Yang [29], there is no global re-

set signals and pixels are reset right after firing. The temporal information is read out col-

umn by column by a counter at each row. Since it requires several seconds to readout low

light pixels in one column, it may take minutes to readout a whole frame. Basically, this

method is only suitable for still imaging application. McIlrath [30] and Kummaraguntla

[38] proposed multiple sampling of each pixel. Because pixels are digitized to either one

or zero, this method is similar to reading a memory. Because time-based imagers rely on

temporal information to reconstruct the original image, any difference between firing time

and sampling time will introduce errors. Thus there is a tradeoff between sampling rate and

errors. Higher sampling rate can reduce errors at the price of higher power consumption

and more memory (needed to store these samples).

Similar to the huge throughput of pixel-level voltage domain ADC CMOS imagers

in Yang et al. [28] and Kleinfelder et al. [39], a pixel-level time domain ADC CMOS

imager [40] also benefits from huge throughput. Inside each pixel, there is a 1-bit ADC and

8-bit counter. Except for time domain quantization errors, pixel firing times are recorded

accurately. However, the total number of transistors in a pixel is 214 and the pixel size is

an unacceptably large 50 x 50 p/m2 with a 0.35 pm technology.

To reduce the pixel area and, at the same time, keep adequate throughtput, this

author proposes two readout architectures: TBARJVIEM and TBARBASE. Unlike most

digital circuits in use today, the readout circuit of TBAR imagers operate asynchronously.

Asynchronous circuits have the potential to achieve higher speed, lower power, improved

noise and electromagnetic compatibility (EMC), although the design of asynchronous con-

trol circuits is difficult and error prone [41]. Also, the protocol of readout circuits are data











driven. Only pixels that have fired are transmitting their data. This is quite different from

sampling methods, where data is readout no matter whether the pixels have fired or not.

As a result, TBAR imagers will significantly reduce power and memory requirements. The

architectures and operations of TBAR imagers will be described in the next section.


3.5 Architecture and Operation of TBAR Imagers


In this section, the architecture and operation of two types of TBAR imagers,

TBARVIEM and TBARJBASE, are described at the system level. Detailed analysis of

each circuit component will be presented in the next chapter.

3.5.1 TBAR with on-chip Memory: TBARMEM


Pixel Array
Row Request~(l)

A
Row R
Pixel(m,n)
Request Rst B
Memory si_ "-.
Memoy Pixel T
SControl E
'- 7\ Ref T-
e- Logic R

Row sel(m)
Data Out Row Request (m)


Col Request(n)
Memory
Write Column Write Enable
Done
Counter
On-Chip
On / Row sel
Time Frame Memory
Time Data In





Figure 3.8: TBARJVIEM:A TBAR imager with on-chip memory.



The block diagram of the TBARJVIEM image sensor is shown in Figure 3.8. An

M x N pixel array is located in the center of the imager. Inside each pixel, there is a

photodiode with reset transistor, a comparator with an autozero circuit to cancel the offset

(not shown), and a pixel control logic block. On the left hand side of the imager, there is









an M x 1 word memory (one word each row), which is used to record firing time. At the

bottom of the pixel array, there is a frame memory that is the same size as the pixel array.

The reason for including an on-chip frame memory is to utilize its parallel writing and high

speed to increase readout throughput. On the right hand side, a row arbiter chooses one

and only one row when there are pixels at multiple rows firing simultaneously.

As mentioned earlier, writing the digital counter value into a memory can be con-

sidered as a time-domain analog-to-digital conversion process. If the architecture of Andoh

et al. [40] is considered as pixel-level time-domain ADC, TBARJMEM is a column-wise

ADC. Although the throughput of TBARJMEM is not as high as that of Andoh et al. [40],

there is no need to put a digital counter and memory inside each pixel, and as a result, the

number of transistors inside each pixel is dramatically reduced.

The TBARJVIEM operates as follows:

1. When the voltage across a pixel's photodiode drops below the comparator's
reference voltage, the pixel makes a row request by pulling down the Rowrequest 1
line, which is shared by all pixels in the same row.

2. When there is at least one active Row_request~ signal, two things happen.
First, the digital counter data are put into the Row Request Memory at the positions where
Rowrequest~ are effective. These are the recorded firing time to be saved in the frame
memory. Secondly, the row arbiter chooses one and only one row by making the corre-
sponding Rowsel signal effective.

3. Rowsel signal plays two roles. In addition to selecting a row of pixels, the
row arbiter's Rowsel signal also selects the corresponding row in the frame memory.
Then, the pixels in the selected row that have fired will send out column request signals (in
parallel) that select the corresponding columns in the frame memory. Now that the frame
memory's row and column addresses have been selected, the counter value (stored after
the row request) is loaded to those addresses.

4. After finishing on-chip memory writing, TBARJIEM control circuit sends a
signal MemoryWriteDone back to the pixel array. Together with the Row_Sel signal,
MemoryWriteDone disables the pixels which has been written to the on-chip frame
memory. Consequently, these pixels withdraw their Rowrequest" signal. Up to this
point, TBARMIEM finishes a readout cycle. The row arbiter is allowed to select a new
row to continue another cycle.

It is important to calculate the throughput of the TBARJVEM imager. The through-

put is defined here as the number of pixels the imager can output per second. From the
'A signal with ~ means it is an active-low signal through out this dissertation.









operation of TBARJMEM described above, the throughput turns out to be image depen-

dent. To demonstrate this point, assume we have an M x N TBARIEM imager. If all of

the pixels are firing closely in time, during one frame memory writing operation, N pixels

can be readout. Throughput is high in this situation. On the contrary, if the pixel array

fires sparsely, there may be only one pixel being readout during one frame memory writing

operation. This corresponds to a low throughput. Thus, both the lowest and the highest

throughput cases need to be considered.

From the operation of the TBARJVIEM imager, the time of one readout cycle is


Tcycle -= ax(Trowmemory Trow arbiter + Tcol request)

+ Tframememory + Tpixel disable (3.30)


where:


Trowmemory: the time delay of writing row request memory.

Trow_arbiter: the time delay of row arbiter choosing one row.


Tcolrequest: the time delay of pixels sending column request signals to the on-chip

frame memory.


Tframememory: the time delay of writing on-chip frame memory.


Tpixeldisable: the time delay of disabling pixels which have already been read out.

Since row memory writing occurs in parallel with row arbitration and column re-

quest, their delays do not sum. Also note that the row request time is not included because

the cycle starts and ends at row arbitration. At this point, row request has already finished.

The throughput of an M x N (M=128 and N=128 in this example) TBARJVIEM

imager using AMI 0.5 pm CMOS technology can be estimated from CADENCE SpectreS

simulations. Since it is impossible to simulate such a big array in CADENCE, in order to

estimate time delays, simulation was done on a 4 x 4 array with the parasitic capacitance









of a 128 x 128 array. From CADENCE SpectreS simulations, the average row arbitration

time is 0.5 x (K+1) x 0.5 ns for M = 2K rows. This gives an average row arbitration time

of 2 ns. Tcol_request and Tpixel_disable are 3 ns and 3.7 ns, respectively. The access time of

state-of-the-art embedded-SRAM is less than 2 ns [42]. If a conservative access time of 5

ns is used in Equation: 3.30, the cycle time of TBARJIEM is


Tcycie = max(5, 2 + 3) + 5 + 3.7= 13.7ns


The highest and lowest throughput can then be calculated using the cycle time. The

highest cycle time happens when N pixels are readout during one on-chip frame memory

writing:

N
Throiil-il ,N,
Tcycle
128
13.7ns
S9.34 Gpixels/s (3.31)


The lowest throughput happens when only one pixel is read out during one on-chip

frame memory writing:

1
T hrc.i,, li,,,I .
Cycle
1
13.7ns
S73.0 Mpixels/s (3.32)


It is also interesting to find out how much time it takes to readout one frame of a 128 x

128 scene:

128 x 128
Tmin Throiilipiil,

= 1.75 ps (3.33)
128 x 128
S Throiilpil,

= 224 ps (3.34)












From the above analysis, due to the massive parallel writing ability, the peak


throughput of TBAR_MEM is quite high (9.34 Gpixels/s for an array built in a 0.5 pm


CMOS technology). However, this is not quite feasible for our university research project


because it is to be fabricated through an educational MOSIS process, which limited us to


certain processes and chip areas. Therefore, another TBAR architecture, TBAR-BASE, is


proposed to get rid of on-chip memory, although at the expense of less throughput. This


architecture will be discussed next.


3.5.2 TBAR without on-chip Memory: TBARBASE


In this section, the operation of a TBARJ3ASE imager is described at the system


level. The throughput of this architecture is calculated. A 32 x 32 version of this archi-


tecture has been successfully implemented and tested by the author. A detailed analysis of


each circuit component will be presented in the next chapter.


Pixel Array


Pixel(m,n)

Pixel
Control
Ref
Ref Logic



Row request-(m)


R R
0
W A W
R A
I B D
N D R
R
T T E
E S
E S
R R E
:F N
C
A 0
C D
Row select(m) E R


Latching J v Col request-(n)
Done L A T C H E S
Pixel Selected
Counter THROUGHPUT CONTROL
COLUMN l
ADDRESS COLUMN ARBITER
ENCODER

Time Column Address Row Address


Figure 3.9: TBARJBASE imager block diagram.


Control
Circuit

__ _


Event Pulse


The block diagram of a TBARJBASE imager is shown in Figure 3.9. As with the


TBARJVIEM, each pixel contains a photodiode, a comparator (with an autozero circuit to









cancel the offset), and a pixel control logic block. Row and column arbiters, which were

previously implemented by Boahen [32], are needed in case there are conflicting pixel

firings. Row and column address encoders output the digital pixel addresses. Meantime,

control circuits output a pulse indicating the address is valid. The throughput control circuit

is used to control how fast TBARBASE reads out pixels. In order to increase the speed

at which the imager can output pulse events and the corresponding pixel addresses, all

circuits operate asynchronously without a global clock. Also there is a counter outputting

time information.

The TBARBASE imager operates as follows:

1. When the voltage across a pixel's photodiode drops below the comparator's
reference voltage, the pixel makes a row request by pulling down the Rowrequest" line,
which is shared by all pixels in the same row.

2. The row arbiter randomly selects a row that is making a row request. This row's
address is stored by a row address encoder.

3. When the row arbiter selects a row with the Rowselect line, the pixels that have
fired in that row are allowed to make column requests by pulling down the Colrequest~
line, which is shared by all pixels in the same column.

4. The pixels in the selected row that are making column requests put their firing
states into the latch cells.

5. Once the column requests are latched, the pixels in the selected row that had
been making column requests are disabled from firing again for the rest of the frame by
these pixels' pixel control block. As a result, Rowrequest~ from this row is withdrawn.
After that, if there are other valid Rowrequest" signals, new row arbitration is allowed to
start taking place. However, the row interface circuit prevents a new Rowselect until all
valid data inside latch cells have been processed. Column arbitration begins on the requests
in the column latch cells. Note that the throughput control circuit can control the column
arbitration speed.

6. During column arbitration, the column arbiter randomly and sequentially selects
the latched column requests. When a column is selected, its address, the latched row
address, and the time are read out. The time represents information about each pixel's
illuminance.

7. Once column arbitration is complete, i.e., all valid data inside the latches have
been processed, the row interface circuit allows a new Rowselct signal is valid. Up to this
point, a readout cycle is finished.

After a receiver (DSP, PC, or ASIC) receives every pixel's firing time information

(from the counter) and their corresponding addresses, the pixel's illuminance can be found









using Equation 3.24 (if the reference level is fixed) or other equations (depending on how

the reference voltage is varying in Figure 3.7).

Because the number of valid pixel firings put into latch cells simultaneously de-

pends on scenes, the readout throughput is also scene dependent. The highest throughput

occurs when all the pixels in the selected row have fired and are put into latches simul-

taneously, and the lowest throughput occurs when only one pixel is put into the latch.

Consequently, the cycle time is also different. Similar to the TBARJMEM imager, we can

estimate the throughput of a 128 x 128 TBARBASE imager.

Assume I/O circuits of a TBARBASE imager do not put a limit on throughput, for

a M x N TBARBASE imager, the smallest and largest cycle times are

rmin Trowarbiter + Tcolrequest + N X (Tcolarbiter + Tcolencoder) + Trow interface
cycle N

(3.35)

Tcyae Trowarbiter + Tcolrequest + Tcolarbiter + Tcolencoder + Trow interface (3.36)

where

Tcol_encoder: the time delay for column address encoding.

Trowinterface: the time delay from finishing data in latches to allowing a new

row_select.


Trow_arbiter, Tcolrequest and Tcol_arbiter: same as definitions appeared in the TB-

ARJVIEM throughput calculation.

We calculated the throughput of a 128 x 128 TBARJBASE imager using the

time delay information extracted from CADENCE SpectreS simulations. Trowarbiter,

Tcolrequest, Tcol_encoder and Trowinterface, are 2 ns, 3 ns, 2 ns and 3.7 ns, respectively. The

column arbiter time is designed to be controllable. If it is free running (i.e., the through-

put control circuit does not put a limitation on throughput), the average Tcol_arbiter is 2 ns.

These numbers give the following cycle time:












+ 2 + 3 + 128 x (2.0 + 2.0) + 3.7
Tmee t28 4.07 ns
cycle 128

T, = 2.5 + 3 + 2 + 2 + 3.7 13.2 ns

The corresponding throughput is

1
T hro -l/,.-,,,/ .
cycle
1
4.07ns
S245.7 Mpixels/s (3.37)
1
T hro, ,/-l, ,,,.

1
13.2ns
75.8 Mpixels/s (3.38)

Compared with the throughput of the TBARJVIEM architecture, the minimum

throughput is slightly better, while the maximum throughput is much smaller. This is

because the parallel writing to on-chip frame memory of TBARJMEM does not take extra

time, while in TBARJBASE, reading out data in latch cells must go through a long se-

quential column arbitration process. The time it takes to readout one frame of a 128 x 128

scene by the TBARJBASE imager:



128 x 128
Tmin Throiilpi,
Thron,,il, ,, ,/
S66.7ps (3.39)
128 x 128
Tmax
Thronil, i,, ,
S216ps (3.40)

3.6 Errors Analysis and Simulation

In the last section, two TBAR architectures, TBARJVIEM and TBARJBASE, are

proposed and their throughput is calculated. In this section, errors caused by limited









throughput of TBAR imagers are further investigated. MATLAB simulators have been

built for both TBARMIEM and TBARBASE imagers. These simulators are quite useful

because they quantify the errors for real-world high dynamic range images. Simulation

results of four high dynamic range images are presented.

3.6.1 Errors Caused by Limited Throughput of TBAR Architectures

As discussed in the last section, one issue with the TBAR architecture is the sit-

uation when many pixels are firing closely in time. Due to the limited throughput of the

readout circuits, TBAR imagers are unable to readout pixel firings in real time. Therefore,

the readout time may have some delay relative to the real firing time. Errors are introduced

when postprocessors reconstruct images using the readout time, instead of the true firing

time.

The above situation can be shown in Figure 3.10 using the TBARBASE archi-

tecture as an example, where a 3 x 3 pixel array is under exactly the same illuminance

L. Although those pixels fire at exactly the same time T (assuming no mismatch between

these pixels), their corresponding output address pulses occur at different times (from t1

to t9) due to the fact that a TBARBASE imager can only output one pixel address at a

time. The difference in time depends on how fast the TBARBASE imager can output

these pulses, i.e. the throughput of TBARBASE imager. Instead of using time position T

for all pixels the receiver will have to use tl, t2, t*, t9 to reconstruct the original image.

Since the temporal position of the address pulses represents illuminance, some errors are

introduced. The reconstructed image will obviously be nonuniform.

From Equation:3.21, the true illuminance for these pixels is

L -Vsig,ref (3.41)
ST

However, when the illuminance is reconstructed from the available time information tk,

the reconstructed illuminance is:

Lk ig,ref (3.42)
Stk










Signal at
Photodiode

Vref
Vsig,rel
L



Time
T (a)


OutputAt
Request

Time

ti t2 t3 t4 t5 t6 t7 t8 t9
(b)
Address
Encoder (m, n)
Output


Time
tl t2 t3 t4 t, t6 t7 t8 t9
(c)

Figure 3.10: Errors introduced by uniform illuminance on a 3 x 3 pixel array of
TBARJ3ASE imager.


The relative errors introduced are

L k tk -T At
Error = (3.43)
L tk T + At

where At = tk T is defined as the time delay of the output pulses. From Equation 3.43,

if the TBAR imagers have a high throughput, which means a smaller At, the error would

be smaller. Also, for the same time delay At, errors are more severe for high illuminance

pixels, where the firing time T is small.

For the TBARJVIEM imager, errors caused by uniform illumination do not exist.

This is because the row request memory can record the firing time correctly. However, if a

lot of pixels are under very close, but not exactly same, illumination, some errors will still

exist due to the limited throughput.









There are several factors which determine the amount of error (due to the time

delay). One important factor is the nature of the imaged scenes. The more uniform the

scene is, the more errors there will be. Also, since larger images have higher pixel firing

rate, errors are more likely to occur. In addition, the speed of the TBAR imagers also affects

errors. For a given image, the higher throughput a TBAR imager has, the fewer errors will

occur. The pulse output rate of a TBAR imager can be improved at the architecture level

(TBARJVIEM architecture, for example), or at the circuit level.

Generally, it is difficult to give precise analytical results of the amount of errors

because it is scene dependent. However, a worst case situation for the TBARBASE imager

can be analyzed here. For a TBARBASE architecture shown in Figure 3.9, the worst case

of time delay for HDR images with a size of 128 x 128 can be calculated using the following

assumptions:


5% of pixels are under exactly the same illuminance. After analyzing seven 8-bit,

grayscale images in MATLAB, we found that there were at most 4% of pixels un-

der uniform illumination. However, we must remember that these images are 8-bit

quantized versions of original scenes. It is reasonable to assume that quantization er-

rors and dynamic range limitations in the 8-bit images inflate the amount of uniform

illumination. Thus, 5% uniform illuminance should be a safe worst case for HDR

images.

The time interval (AtI in Figure 3.10) of two adjacent output addresses which belong

to two pixels in the same row under uniform illuminance is 2.5 ns. At, is due to the

time needed for column arbitration. The time interval (At2 in Figure 3.10) of two

adjacent output addresses which belong to two pixels in different rows under uniform

illuminance is about 11 ns. At2 is due to the time needed for disabling pixels, row

arbitration and latching the column request. This delay information comes from

a CADENCE SpectreS circuit simulation shown in Figure 3.11. Once again, the









simulation is carried out on a 4 x 4 array with load capacitance of a 128 x 128 array

using AMI 0.5 pm CMOS technology. Note that throughput control circuit is not

used in this simulation. Therefore, the asynchronous circuit is free running at the

maximum speed.

SEvery row contains at least one uniformly illuminated pixel. This assumption will

bring the worst delay because At2 is longer than At,.


Using the above assumptions, the worst case delay At is


At = At2M + AtlMNS (3.44)

11 ns x 128 + 2.5 ns x 128 x 128 x 5',

3.5/is


where M is number of rows and N is number of columns.

Note that the errors for the same amount of time delay vary depending on when

these pixels fire. As from Equation 3.43, if the firing time T is 10 /s, the worst relative

error is 3.5ps/13.5/s = 21.' If these pixels fire around 30 ms, the worst relative error is

3.5Ps/30.01 ;-,, = 0.01'"-. If we assume the lowest acceptable SNR is 0 dB, as in the

definition of DR, the smallest acceptable firing time is 3.5 ps for the TBARBASE archi-

tecture. If we assume the longest firing time is 20 seconds (limited by the dark current),

this will give a dynamic range of 135 dB.

3.6.2 MATLAB simulation of errors

In this subsection, MATLAB simulators are built to simulate TBARJVIEM and

TBARBASE at the system level. These simulators turn out to be very useful because

they can predict the performance of imagers for a given circuit architecture and speed.

Simulations are performed to show the amount of errors for a few high dynamic range

(HDR) images with different sizes (160 x 180 and 480 x 720) using both TBARJVIEM and

TBARJBASE architectures.


































- -D










C
4 C- --- --





% ^ y ----- ----------------------------.-

^ u > 11 f ^ ^ ^ - ^ --------_____-- - - -, C
--------




-r ) -- -


-- ; T I





-^ 8|^^ ---- ----------- -- -------------------------______
^' -t,------------------- -------------- "
- --- ---- - --- - - - I
;0 CNE




tA
r(I















Figure 3.11: Output pulses of a 4 x 4 pixel array under uniform illumination (CADENCE

SpectreS circuit simulation).
1 S?0
a *<; ___________________________________ ____ ^









In these two simulators, numerical values of testing imagers, which do not have

physical meanings, have to be mapped into photocurrents in the MATLAB simulation.

Two assumptions are made. The first assumption is that photocurrents are proportional to

the HDR images' numerical values. The second assumption is used to decide a reference

point. The dark current is assumed to correspond to the minimum non-zero numerical

value. Also, the imagers are assumed to be working in video mode (integration time is

30 ms) and the reference signal voltage drops linearly from 2 volts to 0 volts during time

interval from 15 ms to 30 ms. The reference voltage is shown in Figure 3.12.

Signal at
Photodiode I I
Vref

2V
3 Vref





Time

tt t2 (15ms) t3 t4 30ms

Figure 3.12: Reference voltage of TBAR imager simulators.


After each pixel's photocurrent is decided, its firing time can be computed as:


2C
second 0 < t < 5ms
t= 0.03 (3.45)
-10.00 second 15ms < t < 30ms
1 + 0.0075'
where C is the capacitance at photodiode and I is the photocurrent.

After having each pixel's firing time, the output time can be determined by TBAR

imager simulators. The delay times of 160 x 180 images used in MATLAB simulators

are again extrapolated from CADENCE SpectreS circuit simulations using AMI 0.5 pm

CMOS technology. For simplicity, the delay times of image size of 480 x 640 are the same

as those of image size of 160 x 180 assuming they are implemented in more advanced






48


(fast) technologies (e.g. 0.18 pm CMOS technology). The time delays of TBARJVIEM

are:


Time delay from a pixel firing to making a row request: 1 ns.

Access time of row request memory and frame memory: 5 ns.

Average time delay of a row arbitration: 2 ns.

Time delay from row selection to col_request: 3 ns.

Time delay from finishing the latched data to the next rowselect: 3.7 ns.


The time delays of TBARBASE (free running mode) are:

Time delay from a pixel firing to making a row request: 1 ns.

Time delay of a row arbitration 2 ns.

Time delay of a column arbitration 2 ns.

Time delay from row selection to output a pulse: 3 ns.

Time delay of column encoder: 2 ns.

Time delay from finishing the latched data to the next row_select: 3.7 ns.

Before showing simulation results of real high dynamic range images, it is inter-

esting to look at effects of limited throughput on images with large uniform illumination

areas. Figure 3.13 is a scene with 4 uniformly illuminated areas. They have photocurrents

equivalent to 4, 16, 64 and 255 times the dark current. Figure 3.14 (a) (b) show the re-

constructed images using TBARJVIEM simulator. There is no error in this case. This is

because the row request memory of TBARJVIEM can accurately record the firing times.

However, if the scene illumination is very close, but not perfectly uniform, there are still










errors. Figure 3.14 (c) (d) shows the reconstructed images using the TBARBASE simu-

lator. We can see that due to the limited throughput, the reconstructed image has random

horizontal bands.



20

40

60

80

100

120
20 40 60 80 100 120

Figure 3.13: A 128 x 128 scene, 'squares', with uniform illumination area.



The following MATLAB simulations are performed to show the amount of errors

for four high dynamic range (HDR) images. The original images have a size of 480 x 720

pixels. These images are subsampled to get HDR images with size of 160 x 180, which is

slightly larger than the size of QCIF (144 x 176) image format. QCIF is about the size of

the images used for hand-held PDA and videophones. These four HDR images used in the

MATLAB simulators come from Paul Debevec's graphics research group at the University

of Southern California [43]. They are nave, groveC, rosette and vinesunset. These four

images are of floating-point representation and have a dynamic range from 88 dB to 168

dB. After subsampling to a size of 160 x 180, there are slight changes to DR. The numerical

values and dynamic ranges of these images are shown in Table 3.1:

These four images are also displayed in Figure 3.15 and Figure 3.16. Since MAT-

LAB can only display 8-bit (48 dB) image, in order to display these high dynamic range

images, two figures are used to display one image.

The mean relative errors between the original images and the reconstructed images

of four 160 x 180 and four 480 x 720 HDR images using the TBARJVIEM architecture





















880

100 100

120 120
20 40 60 80 100 120 20 40 60 80 100 120

(a) (b)


20 20

40 40

60 60

80 80

100 100

120 120
20 40 60 80 100 120 20 40 60 80 100 120

(c) (d)

Figure 3.14: Reconstructed 'squares'. (a) Using the TBARJVIEM (normal display). (b)
10X brighter to exaggerate errors. (c) Using the TBARBASE (normal display). (d) 10X
brighter to exaggerate errors.


are shown in Table 3.2. The errors introduced by TBARBASE architecture are shown in

Table 3.3.

To have an idea of how significant these errors are, one of the reconstructed im-

ages with highest mean relative error (0.378%), rosette of TBARBASE, is displayed in

Figure 3.17. There is no recognizable difference from Figure3.16(a)(b). Also, to compare

with other noise sources, the noise (error) caused by the photocurrent shot noise alone

of the lena image, shown in Figure 3.18(a), is computed using Equation 3.12. It gives a

mean relative error of 0.9%. The lena image with photo current shot noise is displayed in

Figure 3.18(b).










Table 3.1: Four 480 x 720 and four 160 x 180 HDR images used in MATLAB simulation.
Images with a size of 480 x 720
Image Name nave groveC rosette vinesunset
Minimum Value 1.69 x 10-5 5.53 x 10-4 2.63 x 10-5 1.44 x 10-3
Maximum Value 4.27 x 103 8.80 x 102 8.28 x 101 3.61 x 101
Dynamic Range(dB) 168 124 130 88
Images with a size of 160 x 180
Image Name nave groveC rosette vinesunset
Minimum Value 1.69 x 10-5 9.13 x 10-4 2.63 x 10-5 1.58 x 10-3
Maximum Value 2.59 x 103 4.93 x 102 7.43 x 101 3.31 x 101
Dynamic Range(dB) 164 115 129 86


Table 3.2: The mean relative errors introduced by TBARJVIEM of four HDR images with
sizes of 160 x 180 and 480 x 720.
Images with a size of 160 x 180
Image Name nave groveC rosette vinesunset
Mean Relative Error 9.87 x 10-7 6.35 x 10-7 7.31 x 10-7 1.59 x 10-7
Images with a size of 480 x 720
Image Name nave groveC rosette vinesunset
Mean Relative Error 6.38 x 10-5 4.28 x 10-5 7.36 x 10-6 1.69 x 10-6


From the simulation results in Table 3.2, Table 3.3, Figure 3.17 and Figure 3.18,

we make the following observations:

The errors caused by the limited throughput of TBAR_MEM and TBARBASE are

negligible for these four HDR images, compared with the photocurrent shot noise

and the fixed pattern noise (FPN). The photocurrent shot noise alone will cause a

mean relative error of 0.9% for the lena image. The FPN is typically 0.2% of the

saturation level [16]. The mean relative error caused by the FPN is even higher

because not all pixels have a signal level close to the saturation level.

The larger the image size, the more significant the errors are. This is not surpris-

ing because the probability of collision is higher for larger image size. From the

simulation results, however, the errors are negligible for image sizes up to 480 x

720.























400 400 2 '4i i

100 200 300 400 500 600 700 100 200 300 400 500 600 700
(a) (b)

50
100
15,





350
400 *- ,. *


100 200 300 400 500 600 700 100 200 300 400 500 600 700

(c) (d)

Figure 3.15: Images nave and groveC. (a) nave (bright part). (b) nave (dark part: x 100
brighter for display). (c) groveC (bright part). (d) groveC (dark part: x20 brighter for
display).


The errors caused by TBAR imagers are image dependent.


The TBARJVIEM architecture suffers fewer errors than the TBARBASE, thanks to

its parallel writing on-chip frame memory.


In the last section, we computed the throughput of the TBARJVIEM and the

TBARJBASE architectures. It is interesting to look at the firing rates of these four HDR

images and understand better how the throughput of the TBAR imagers affects errors. The

firing rates are computed as the number of firings per second in a small period. The max-

imum and mean firing rates of the four HDR images are shown in Table 3.4. The firing

























400 10 5 0


100 200 300 400 500 600 700 100 200 300 400 500 600 700

(a) (b)

50 50

100 100

150 150

200 200
250 250

300 300

350 350

400 400

450 450
100 200 300 400 500 600 700 100 200 300 400 500 600 700

(c) (d)

Figure 3.16: Images rosette and vinesunset. (a) rosette (bright part). (b) rosette (dark
part: x 100 brighter for display). (c) vinesunset (bright part). (d) vinesunset (dark part:
x 10 brighter for display)


rates and the relative errors of the rosette and vinesunset images with sizes of 160 x 180

and 480 x 720 are shown in Figure 3.19 and Figure 3.20, respectively. The time bin size

of these two figures is 5 ps.

From Figure 3.19 and Figure 3.20, we have two useful observations:


Recall from the throughput estimation in the last section, the minimum throughput

of TBARJVIEM and TBARBASE are 73.0 and 75.8 MegaPixels/second. From the

image firing rate plot in Figure 3.19 (b) and Figure 3.20 (b), rosette has a high firing

rate of more than 100 MegaPixels/second region from 27 ms to 30 ms. vinesunset











Table 3.3: The mean relative errors introduced by TBARBASE of four HDR images with
sizes of 160 x 180 and 480 x 720.
Images with size of 160 x 180
Image Name nave groveC rosette vinesunset
Mean Relative Error 1.47 x 10-5 6.96 x 10-' 2.84 x 10-6 2.58 x 10-7
Images with size of 480 x 720
Image Name nave groveC rosette vinesunset
Mean Relative Error 2.39 x 10-4 1.93 x 10-4 3.78 x 10-3 6.71 x 10-6



100
150
200
250
300




100 200 300 400 500 600 700 100 200 300 400 500 600 700
(a) (b)

Figure 3.17: Reconstructed rosette by TBARBASE imager with 0.378% mean relative
error. (a) Bright part. (b) Dark part (xl00 brighter for display).


has a maximum throughput of only 73.8 MegaPixels/second. This indicates that

rosette is likely to have more errors than vinesunset. It is verified by the results in

Table 3.2 and Table 3.3.


Images with different size have different firing rate. The images with a size of 160

x 180 have firing rates roughly 10 times lower than those with a size of 480 x 720.

Since the firing rates of images with size of 160 x 180 are much lower than the

throughput of TBARJVEM and TBARBASE, the errors are negligible, which is

manifested by looking at the errors in Table 3.2 and Table 3.3.

3.6.3 TBAR_BASE imager with throughput control

From the error calculations in the last subsection, the errors are negligible for

moderate size images (such as QCIF image format) for both the TBARJIEM and























(a) (b)


Figure 3.18: Image lena. (a) Original image. (b) Image lena with 0.9% mean relative
error due to photo current shot noise.

Table 3.4: The maximum and mean firing rates of four HDR images with sizes of 160 x
180 and 480 x 720.
Images with size of 160 x 180
Image Name nave groveC rosette vinesunset
Max Firing Rate (MPixels/second) 9.2 15.6 20.4 7.8
Mean Firing Rate (MPixels/second) 0.96 0.96 0.96 0.96
Images with size of 480 x 720
Image Name nave groveC rosette vinesunset
Max Firing Rate (MPixels/second) 89.6 105 190 73.8
Mean Firing Rate (MPixels/second) 11.4 11.4 11.4 11.4


TBARBASE architectures. However, one practical issue arises as how to capture the

address pulses generated by a free-running TBARBASE imager shown in Figure 3.11.

This is not a trivial issue because the duration of a pulse is only about 2 ns. This puts a

very high requirement on I/O circuit design [44] and testing. One possible solution is to

use an on-chip buffer (registers or SRAM). But this will make the design more complicated

and consume more silicon area. Also considering the intended test instrument is a Agilent

1693A logic analyzer which has a maximum transient clock speed of 200 MHz, the output

pulses rate in Figure 3.11 are controlled by an external clock to make testing easier,. This

brings two advantages:











25x10
25


L b S. L _, ... L..I.. ..L ..
0005 001 0015 (
Time (second)


0 0005 001 0015 002
Time (second)


0025 003


_x 10


0
0 0005 001 0015 002
Time (second)


0031

0 025-

002-

0015-

0 01 -

0 005-

0 0005 001 0015 002 0025 01
Time (second)


Figure 3.19: The firing rates of rosette (a) with the size of 160 x 180, (b) with the size of
480 x 720, and the relative errors of rosette (c) with the size of 160 x 180, (d) with the
size of 480 x 720.


1. The throughput of the imager is controllable. The data generating rate of the im-
ager can be slowed down if the I/O or testing equipment cannot keep up with it. Although
this approach may reduce the throughput, but the testability justifies this approach for this
prototype design.

2. Since the throughput is controlled by an external clock, the output addresses
are actually synchronous with a clock. Therefore, although the internal imager circuits
are asynchronous, the output addresses are synchronous. This solution incorporates the
asynchronous circuits in a synchronous environment [45].

The current design has been simulated using clock rates ranging from 20 MHz to

66 MHz. If a 20 MHz clock is used, it takes one clock period to output one pixel, no matter

where it is located, as shown in Figure 3.21, where the catch signal is one phase of a


I I I I I












I I I I I


I I I I I




























Time (second) Time (second)

(a) (b)



25- .3-
8 8










25

2-
E E
1 1

0 0
0 0005 001 0015 002 0025 003 0 0005 001 0015 002 0025 003
Time (second) Time (second)

(a) (b)
St 10 o 0 x 104













two-phase clock. If a 66 MHz clock is used, it takes 1 clock period (15 ns) to output each
25 3

25
2-




























It is not difficult to calculate the throughput. With a 20 MHz clock, the throughput
2 2
w w


1




















T3 '1e = 20Mpixels/s
05 05


S 0005 001 0 015 002 0025 003 0 0 0005 001 0015 002 0025 003
Time (second) Time (second)
(c) (d)

Figure 3.20: The firing rates of vinesunset (a) with the size of 160 x 180, (b) with the
size of 480 x 720, and the relative errors of vinesunset (c) with the size of 160 x 180, (d)
with the size of 480 x 720.


two-phase clock. If a 66 MHz clock is used, it takes 1 clock period (15 ns) to output each

pixel firing simultaneously in the same row. For pixels firing simultaneously in different

rows, it takes two periods (30 ns) to output each of them. This is shown in Figure 3.22.

It is not difficult to calculate the throughput. With a 20 MHz clock, the throughput

is fixed at:

Throi,,,1i,,I O (3.46)
Ty,, 20Mpixels/s























-1.0
7.0 -: /Col_A2




7.0 o: /Col_A3




7.0 D: /Col_A4










t:me (/s_)
> 3.0 0













Figure 3.21: Output addresses using a 20MHz clock to control throughput under uniform
7,0 : /icye Tc ch











1
T ^J !i L J L J ^ i [- Ll ,1 [ 1_ i Lj Li
4.70u 4.90u 5.10u 5.30u 5.50u 5.70u
time ( s )




Figure 3.21: Output addresses using a 20MHz clock to control throughput under uniform
illumination.


With a 66 MHz clock, throughput is different. For a M x N array, the maximum throughput

happens when latches have N valid data in one cycle:



N x Tcycle + Tcycle











1

Cycle + Tcyci




















> 3 / ;
6 l l fi M I 0 o: Io AZ
01.
6.0 o: /Co _A3
-.+ *r +, -i ^ ^ < ^ '



6.0 P: /CoLA4

> 25 I
1 .0 i i

6,0 v: /'i0/c watchh
N n fi r i N i N n Sri n f n IN pi n n n r


4.80u 4.90u 5.00u 5.10u 5.20u
tIme ( s )




Figure 3.22: Output addresses using a 66MHz clock to control throughput.

1
2 x Tcycle
33Mpixels/s


Errors introduced by 20 MHz and 66 MHz throughput control are estimated from

MATLAB simulations on the four 160 x 180 HDR images. They are listed in Table 3.5.

Compared with errors in Table 3.2 and Table 3.3, there is a slight increase of errors. How-

ever, they are still negligible compared with photon shot noise and fixed pattern noise.

In this research project, a 32 x 32 TBARBASE imagery with throughput control

has been designed and tested due to its feasibility and testability in the university environ-

ment. The error simulations discussed in the last several subsections demonstrate that the










Table 3.5: The mean relative errors of four HDR images with size of 160 x 180 under
different throughput control clock.
TBARBASE with 20 MHz Throughput Control
Image Name nave groveC rosette vinesunset
Mean Relative Error 6.93 x 10-5 1.57 x 10-5 3.22 x 10-5 3.08 x 10-6
TBARBASE with 66 MHz Throughput Control
Image Name nave groveC rosette vinesunset
Mean Relative Error 3.64 x 10-5 4.17 x 10-6 9.67 x 10-6 1.10 x 10-6


TBARJVIEM architecture suffers from fewer errors for the same image size compared to

the TBARBASE architecture. The disadvantage of this architecture is the large on-chip

memory needed. The TBARBASE imager does not need on-chip memory at the expense

of a smaller peak throughput. Throughput control circuits of TBARBASE forces the ad-

dress pulses to synchronize with an external clock. This makes testing much easier. Since

both TBARJVIEM and TBARJBASE imagers share the same idea (time-based imager with

asynchronous readout) and same circuit components (pixel, arbiter and asynchronous con-

trol circuits), after a 32 x 32 TBARJBASE imager is successfully fabricated and tested,

it can be easily extended to make a larger imager or a TBARJVIEM imager if the on-chip

memory is available.

3.7 Summary

In this chapter, the DR of the photodiode CMOS APS imager is analyzed to show

the limitations to DR with the conventional CMOS APS imager architecture. The opera-

tions of a number of existing HDR imagers are investigated. A time-based asynchronous

readout (TBAR) imager is introduced to achieve HDR, and its principles and operations

are described. Two different architectures, TBARJBASE and TBARJVIEM, are proposed.

One unique issue with TBAR imagers, errors introduced by limited throughput, is dis-

cussed. The throughput of TBARBASE and TBARMEM is computed. MATLAB simu-

lations demonstrate that the errors introduced by TBAR imagers are negligible for the four

moderate size (up to 480 x 720) HDR test images. The reason for adding the throughput






61


control circuit is explained. In the next chapter, the design of a 32 x 32 TBARBASE

imager with throughput control will be presented.















CHAPTER 4
TBAR IMAGER CIRCUIT DESIGN AND ANALYSIS
4.1 Introduction

In this chapter, a 32 x 32 TBARBASE imager is designed using a AMI 0.5 pm

CMOS process. While the system architecture has been discussed in the last chapter, this

chapter focuses on the design at the circuit level. Section 4.2 will discuss the pixel design

for the TBAR imagers, which includes a photodiode, a comparator and a digital control

circuit. The asynchronous readout circuit design is presented in Section 4.3. Since the

imager is operating asynchronously, the correct timing is crucial. The timing analysis is

discussed in Section 4.4. This chapter is concluded in Section 4.5.

4.2 Pixel Design

The block diagram of the fabricated and tested TBARBASE imager is shown in

Figure 4.1. Each of the blocks will be discussed in detail in this chapter. Compared with

Figure 3.9, Figure 4.1 does not have a counter since the test equipment, an Agilent 1693A

logic analyzer, has an integrated counter.

There are 32 x 32 pixels for this design. The pixel schematic is shown in Figure 4.2.

Inside each pixel, there is a photodiode, a comparator and digital control circuitry. The

pixel operation and the digital control circuitry will be explained first, followed by the

photodiode and comparator design.

4.2.1 Pixel Operation and Digital Control Circuitry

In this section, the operation of one pixel of the TBARBASE imager will be de-

scribed. The circuit diagram of one pixel located at row m and column n is shown in

Figure 4.2. Dl is a photodiode. The comparator is implemented using an opamp (which















32x32
Pixel Array


Latching
Done


COLUMN
ADDRESS
ENCODER

SColumn


Pixel(m,n)


Pixel
Control
Ref Logic




Row request(m)


LATCHES


THROUGHPUT CONTROL
, V V V


COLUMN ARBITER


Address


R R
0 -0
W A
R A
I B D
ND
N R
T T E
E E S
R R E

A C
C D
E E
Rowselect(m) R



Colrequest(n)
Latch Control

2-phase Clock
9 j1, 2 lGenerator

T7 clock


Row Address
1


I/O Circuitry


Imager

Off-Chip


Power Supply, Bias Circuit and Test Equipment


Figure 4.1: TBARBASE imager block diagram.


will be discussed in detail later). RES and RES" are global reset signals. JOIN is an-


other global signal, which will be explained soon. The rowrequest" signal is the request


signal going to the row arbiter. rowsel is the selection signal, coming through the row in-


terface circuit from the row arbiter. latchrow is used to prevent the pixel from firing again


after this pixel has put its firing status inside the latch. The cox" signal puts the pixel firing


status into the latch after the row of this pixel is selected by rowsel. rowrequest (m),


rowsel(m) and latchrow(m) signals are shared by all pixels in the same row m, while


cox"(n) is shared by all pixels in the same column n.


The pixel will always be in one of the four operation states: resetting, integrating,


firing and latching:










To latcth

Vdd

SPixel(m,n) row rquest~(m) M 100
STo row arbiter
RES~ RES A
J OIN M25
I1 INV1 INV2
B Vdd

Dl-------N1 M30 S
Vdd INV13
M16 M18 achrow(m) co(n)
M NV4 M34
RES M13 M32
RES- M r5
1 ri ^M35





Figure 4.2: TBARBASE pixel schematic.


4.2.1.1 Resetting


During the reset phase, RES is high and RES~ is low. The comparator is in a unit-

gain feedback configuration to reset the photodiode. Assuming the amplifier gain is large

enough and the charge injection of switch M16 is negligible, the photodiode is reset at the

voltage of Vreset + V/ff, where Voff is the offset voltage of the comparator. Also, during

the reset phase, JOIN is low and M17 is off. As a result, the output of the comparator is

isolated with reset of the circuit.

M18 is used to speed up transition during firing. During reset, the pixel should not

output a request signal. That means voltage at node A should be low (pixel is disabled),

ensured by M13. Since M13 is stronger than M18, A is low during reset phase.

M30 is used to reset the latch formed by two inverters: INV3 and INV4. This

latch stores information whether the pixel is in the latching state.

4.2.1.2 Integrating


When RES goes low, the photodiode D1 is to be discharged at the rate propor-

tional to photocurrent and the pixel is in the integration phase. The non-inverting node of









the opamp is connected to the reference voltage V,,f. Since the initial voltage at D1 is ap-

proximately Veset, which is higher than V,,f, the output of comparator goes from V_reset

to zero. Also, M13 is disabled and M17 is turned on during the integration phase. The

output of the comparator will be able to control the voltage at the node A.

Attention need to be paid for the timing of JOIN. JOIN is used to isolate the

comparator output and node B during the Reset phase. It is necessary because the com-

parator output voltage is high (equal to Veset) while node B is low during the Reset phase.

If M17 is turned on at the same time RES goes to low, the voltage at node B will be de-

cided by the charge sharing between the charges stored at the output of the comparator

and node B. This voltage is digital '1' verified by the SPICE simulation. However, pixels

should not be firing immediately after RES goes low. Therefore, M17 need to be turned

on At later than RES goes to low, waiting for the output of the opamp goes back to '0',

where it should be. The CADENCE SpectreS simulation shows At should be more than

1 ps.

4.2.1.3 Firing

During integration, the photodiode is discharged by the photocurrent. When the

voltage at D1 drops below the reference voltage V,,f, the comparator output goes to high.

As a result, A is high and rowrequest" is pulled down to low. Therefore, this pixel fires

and sends a request signal to the row arbiter.

4.2.1.4 Latching

If the row arbiter selects (by making rowsel(m) high) this row after receiving the

rowrequest(m) from this pixel, this pixel will send cox~ (n) to the column latch. After

the corresponding latch makes sure that the firing status (either '1' or '0') is inside the

latch, it sends a latchrow(m) signal to let the pixel withdraw rowrequest" (m) signal.

Meanwhile, the pixel is disabled by the pull-down transistor M32. This pixel can not fire

again until the next reset phase turns off M32.









There are 30 transistors for each pixel. The layout of one pixel is shown in Fig-

ure 4.3. Note that the area that is not shaded is light-sensitive. The pixel area is 37.5 pm

x 34.8 pm. The photo-sensitive area is 4.8 pm x 5.1 pm. Compared with the pixel size

of about 5 pm x 5 pm for state of the art CMOS image sensors, this pixel size is much

larger. However, this design is implemented on a 0.5 pm CMOS technology. In [39],

there are 37 transistors in one pixel and the pixel size is 9.7 pm x 9.7 pm using a 0.18

pm CMOS technology. Thus, we expect that the TBAR_imager pixel size can be reduced

to about 9 pm x 9 pm if a 0.18 pm technology is used. Furthermore, since it has been

generally acknowledged that further decrease in the pixel size much beyond 5 pm x 5

pm is not needed because of the diffraction limit of the camera lens [46]. Therefore, the

TBAR imagers will benefit from further scaling in terms of reduced pixel size, which is

not the case for the conventional APS image sensors because their pixel size has already

reached their fundamental limits. In [47], the authors estimated the number of transistors

each pixel can fill as the CMOS technology scales assuming a 5 pm x 5 pm pixel size

with a constant fill factor of 30%. For 0.10 pm technology, about 20 analog transistors

or 100 digital transistors can be put into one pixel. This is more than enough for TBAR

imagers.

4.2.2 Photodiode Design

The photodiode design is not a trivial issue. The optimal design should achieve high

sensitivity, low dark current and low cross-talk. One effective way to increase the photo-

sensitivity is to deepen the photo-conversion region [48]. To reduce dark current, a pinned

photodiode is used to suppress the surface state [13, 14, 15]. Cross-talk can be reduced

by careful layout and adjusting the doping profile [48]. Note that device simulators are

frequently used to determine optimal layouts and doping profiles in designing photodiodes.

For this research project, we do not have the luxury of adjusting the doping profiles

to achieve an optimal photodiode. Instead, native P/N diodes of a standard AMI 0.5 pm

CMOS process are used as photodiodes. There are at least three types of photodiodes



































Figure 4.3: The layout of one pixel.


available in the AMI 0.5 pm CMOS process: P-substrate/N-diffusion, P-substrate/N-well

and P-diffusion/N-well. In this design, a P-substrate/N-well diode, as shown in Figure 4.4,

is used.

The total capacitance at the cathode node of the photodiode is the summation of

the junction capacitance of the P-substrate/N-well, the gate capacitance of an input PMOS

transistor (with a width of 1.5 pm and a length of 1.2 pm) of the comparator and the drain

capacitance of the reset PMOS transistor (M16 in Figure 4.4, with a width of 1.5 pm and

a length of 0.6 pm):



Cd = CN-well + Cgate + Cdrain (4.1)

The drawn area of the N-well is 3.6 pm x 3.9 pm w 14pm2, giving rise to a capacitance

of CN-wel = 0.56 fF from the MOSIS N-well capacitance data (40 aF//m2 between


'qZ, &:\ \\\'Z









To comparator/reset




N


N-Well


P Sub


Figure 4.4: N-well/P-sub photodiode.


N-well and substrate). The input PMOS transistors of the comparator are in the weak

inversion region. The gate capacitor can be modeled as the series combination of a gate

oxide capacitor Co and a substrate depletion capacitor [49]. From the MOSIS data, the

gate oxide capacitance of a 1.5 pm(W) x 1.2 pm(L) PMOS transistor is 4.3 fF. The

depletion capacitance depends on the substrate doping density, for a transistor in weak

inversion [49]:



Cb A (4.2)
V 2^
where A is the area of the gate, c, is the permittivity of silicon (1.04 x 10-12 F/cm),

Nh is the channel doping density (1.7 x 1017 cm-3 from MOSIS data) and bs is the

surface potential (about 0.7 V in weak inversion). From the above equation, the depletion

capacitance Cb is 3.2 fF. Thus, the gate capacitance is


Cgate = C C= 1.8 fF (4.3)
cox + Cb

Also from MOSIS data, the drain diffusion capacitance of the reset PMOS transistor is

about 1.6 fF. Thus the total capacitance:


Cpd N-well + Cgate + Cdrain = 4.0 fF


(4.4)









From the CADENCE SpectreS simulation, the total capacitance at the photodiode is about

4.6 fF, which matches well with the hand calculations.

4.2.3 Comparator Design

The operation of one pixel of the TBAR imager has been described in Section 4.2.1.

The only analog part of the TBAR imager is the comparator inside each pixel. The design

of the comparator will be discussed in this section.

As shown in the pixel diagram of Figure 4.2, the comparator output flips when the

voltage at the photodiode drops below the reference voltage. Modern high-speed com-

parators typically have one or two stages of preamplification followed by a track-and-latch

stage [50]. However, this architecture is not quite suitable for the TBAR imager. For a

track-and-latch type of comparator, the internal nodes are reset before entering the latch

(comparison) mode. That means, we need to decide when we want to make a comparison.

This is not a problem for synchronous systems, such as A/D converter applications, where

a clock can indicate when the comparison is to occur. For a TBAR imager, only one com-

parison is needed during one frame time for each pixel, but the time of the comparison is

unknown (in fact, this is the information the TBAR imager intends to capture). In other

words, we do not know when to switch the comparator from the track mode into the latch

mode. Another issue is that this architecture usually needs dozens of transistors, which

would make the pixel unacceptably large.

In this design, an opamp is used as a comparator. For conventional applications,

the main drawback of this approach is the slow response time since the opamp output has

to slew a large amount of output voltage and settles too slowly [19]. However, for TBAR

imager applications, it is not necessarily an issue. The slow response time of the opamp

will cause a delay from the time when the photodiode voltage reaches the reference volt-

age to the time when the pixel sends a row request signal rowrequest" This amount

of time delay may be different for different illumination levels (i.e., different photodiode

discharging rates). When the original image (illumination information) is reconstructed









using Equation 3.24, there will be some distortions from the (assumed) linear relationship

between illumination and image numerical value due to the additional opamp delay. Fortu-

nately, these nonlinear distortions are fundamentally different from the errors discussed in

Section 3.6, where pixels firing at the same time (i.e., pixels are under same illumination)

will have output pulses at different times. Assuming that there is no mismatch among these

comparators, the time delays introduced by the slow response of comparators are the same

for all pixels under the same illumination. Therefore, pixels with the same illuminance

still get the same reconstructed numerical values. Note that the nonlinear relationship be-

tween the illuminance and the output image numerical value exists even in conventional

CCD and CMOS APS imagers, because of the nonlinearities of the photodiode capacitance

and readout circuit gain with the signal level. Furthermore, some very nonlinear functions

(such as gamma correction [12]) are often applied to final digital output values from image

sensors to accommodate for human vision. In short, the slow response time of the opamp

will introduce nonlinear distortion, and unlike FPN, this nonlinear distortion is acceptable

for imaging applications.

The requirements for this opamp are low power, small area, high enough gain and

fast enough response time. Low power is essential because there are tens of thousands

of opamps in the imager array. To keep the power consumption of a TBAR imager with

100,000 pixels below 50 mW, the total current for one pixel must be less than 100 nA for

a 5 V power supply voltage. Therefore, the MOS transistors of the opamp operate in the

subthreshold region. Also, the opamp can not be too large due to the limited size of the

pixel. To reset the voltage of different photodiodes to a fixed value and to cancel effectively

the offset of opamps during autozeroing, enough gain is required. However, too much gain

will make the opamp too slow. Therefore, there is a trade-off between the opamp gain and

the response time.










4.2.3.1 Opamp Gain Requirement without Considering Offset

For most conventional APS CMOS image sensors, the reset ofphotodiode is simply

done by an NMOS transistor (shown in Figure 2.4). Fixed pattern noise is reduced by

the correlated double sampling (CDS) circuit. However, for TBAR imagers, once the

signal passes through the comparator, it is a digital voltage. It is not possible to apply an

analog voltage CDS circuit to cancel offsets. In contrast, an opamp working in unit-gain

feedback configuration is used to reset the photodiode during reset phase in this TBAR

imager design. In this way, the random offset of the comparator (an opamp in this design)

which gives rise to fixed pattern noise, as well as 1/f noise, can be greatly reduced. This

technique is also called antozeroing [51].

To see how much gain is needed for the opamp, a perfectly matched opamp is

considered at first, as shown in Figure 4.5.




Vph

Photodiode

Opamp

Vreset

Figure 4.5: Using an opamp to reset the photodiode.


Assume the gain of the opamp is A, from the small signal model of the opamp, we

have

Avo,, AA, (4.5)

where Av,,t and A, are small deviations from the opamp DC operating points at output

and input, respectively.









From Figure 4.5, the photodiode reset voltage Vph has to satisfy the following equa-

tion:

Vph Vout,dc = A(Vreset- Vph) (4.6)

where Vout,dc is the opamp output voltage when the differential input voltage is zero. From

this equation, the photodiode reset voltage can be expressed as


Vph Veset + t,- reset (4.7)

Without offset voltages, the desired photodiode reset voltage Vph should be the

same for all pixels. However, as from Equation: 4.7, Vph is a function of opamp gain A. If

there is a gain variation 6A from the nominal gain Ao (i.e., A = Ao + 6A), the photodiode

reset voltage is

Vout,dc Vreset
Ao + 6A + 1
Vh = Vreset Ao+SA+1
Voutdc Vreset 6A
Ao + 1 Ao + 1
r + Vout,dc Vreset (Vout,dc Vreset)6A
w Vreset (4.0;
Ao A (4.8)

assuming 6A is much smaller than Ao and Ao is much larger than 1. Thus, the reset voltage

variation is AVph = (Vout,dc Vreset)6A/A This variation depends on the difference

between the opamp output bias voltage Vout,dc and the photodiode reset voltage Vreset, the

opamp nominal gain Ao, and the opamp gain variation 6A/Ao.

If the photodiode reset voltage is equal to the opamp output bias voltage, the reset

voltage variation is zero from Equation: 4.7. However, there may be some difference be-

tween the desired photodiode reset voltage and the opamp output bias voltage in practice.

To see how much gain is required, assume:

1. The variation of the photodiode reset voltage should be limited to less than 1 mV.

2. Vout,dc Vreset is less than 1 volt.


3. The opamp gain variation 6A/Ao is 0.1.










This gives rise to an opamp gain of 100, which is not a difficult requirement to meet.

4.2.3.2 Opamp Gain Requirement with Considering Offset

The offset of the CMOS amplifier stems from the threshold voltage and device

W/L ratio mismatch of the source-coupled differential pair, as well as from the mismatch

of load elements [52]. The offset of the opamp might be on the order of 1 mV to 10 mV for

typical CMOS processes [51]. Random mismatches of pixels in an array introduce FPN

for a TBAR imager. An autozeroing circuit is used to effectively reduce the opamp offset

and 1/f noise [51].

RES

S1

Vph
V Voff
C A-


ES3 S2 Real Opamp
RES- RES \

V ref V reset

Figure 4.6: Opamp offset cancellation using autozeroing circuit.


The autozeroing offset cancellation circuit is shown in Figure 4.6. During the reset

phase, the opamp is connected in a closed-loop configuration. It is not difficult to find out

the voltage at the photodiode is

Vout,dc Vreset Voff
Vph = Vreset + Voff + A 1 A + (4.9)


When the opamp is used as a comparator, switches S1 and S2 are open, while switch S3 is

closed. The voltage at the photodiode right after switch S1 opens is

Vout,dc Vreset Voff Qinj
Vph = Vreset + Voff + + (4.10)
A+1 A+1 C

where Qij is the charge injection from switch S1, and C is the total capacitance at the

cathode of photodiode. From Equation 4.10, we can see the opamp offset has been stored









on the photodiode, in additional to a residual offset [51]


Voff,res Vff Q (4.11)

Considering that the Voff of the opamp is usually less than 50 mV, a gain of 100 should be

enough to reduce the the offset voltage below 1 mV. The charge injected into the photodi-

ode comes from the channel charge of switch MOS transistor S1:


Qch = WLCo,(VGS Vth) (4.12)

where W and L are the gate width and length of the MOS transitor switch S1, respectively.

When switch S1 turns off, Qch goes to both sides of the switch under capacitive coupling

and resistive conduction. However, in the fast switching-off conditions, the percentage of

charge injected into either side approaches 50 percent [53].

For a minimum size switch PMOS transistor with W = 1.5pm, L = 0.6/m,

Cox = 2.4f F/pm2, and Vs Vth = 1V, using the photodiode capacitance of 4.6fF, the

charge injection introduced voltage at the photodiode is

Tinj
Vph,inj
C
1 Qh
2C
1WLCo,(Vcs th)
2 C
= 0.23V

This is quite substantial. With an assumption of 2% mismatch of charge injection, it will

introduce about 5 mV photodiode reset voltage variance.

4.2.3.3 Opamp Design

From a gain requirement of about 100 and a total current of less than 100 nA,

the opamp in Figure 4.7 can be used. The reason why a simpler opamp is not used is

illustrated in Figure 4.8. Note that the photodiode is connected to the opamp inverting

input node. After the photodiode is reset and the pixel goes into the integrating phase, the









Vdd


M8 L M7
Vdd


Vb M9 Vout



a M2 Ml van




M6 M4 M3 M5




Figure 4.7: Opamp schematic.


output voltage of the opamp, Vout, goes from the reset voltage V.rest to about 0 V. Because

the photodiode is floating, due to the gate-drain overlap capacitor Co, of Ml, the change

in voltage at the photodiode is given by

Coy
AVPh C AVout (4.13)
Cph + Cov

Since the photodiode capacitance is only a few femto Farads, the overlap capacitance of

Co, is comparable to Cph. Therefore, AVph is quite significant because of the large swing

of AVout. Also, Co, is dependent on the transistor size. From CADENCE SpectreS simula-

tion, a few hundred mV have been observed. More importantly, any mismatch of transistor

size of Ml will introduce different charge injection. Cadence simulations show a firing

time difference of 10% if the Ml length has a mismatch of 25% given 200 pA photocurrent.

In contrast, the drain of inverting input transistor M2 in Figure 4.7 is at low impedance,

thanks to the diode connected transistor M4. Therefore, the drain of the opamp input tran-

sistor in Figure 4.7 node does not experience drastic voltage changes as in Figure 4.8.









Vdd
L J
M4 M3

M Vout

Cov
Vin+ Vin
M2 Ml -

Cph
Vb M5 Cph



Figure 4.8: 5-transistor Opamp charge injection.

Gain. To find the gain of this opamp, note at first that all transistors are working

in the weak inversion region since the total bias current is less than 100 nA. The weak

inversion drain current [52]
W k (Vos-Vt\ VD S
ID = qXDanpo exp ( exp 1VGS- Vt exp VDS (4.14)
L \VT} ) nVT ) (_ VT )I
where X is the thickness of the region in which ID flows, D, is the diffusion constant for

electrons, rpo is the equilibrium concentration of electrons in the substrate, k2 is a constant,

and n = (1 + Cjs/IC), in which Cjs is the depletion-region capacitance and Cox is the

oxide capacitance. Let

W k2 VT(4.15)
Is = -qXDnnpo exp exp (4.15)

Equation 4.14 is simplified to
(VoS s VDs 41
ID IS exp(VS 1 exp V ] (4.16)

Note that unlike in strong inversion, where VDS > Vo = VGS Vt is needed to enter into

saturation, the drain current is almost constant (saturated) when VDS is larger than a few

VT. Also, from Equation 4.16, the transconductance

aID I
g 91D ID (4.17)
8 =Vo s n^ V









The gain of the opamp in Figure 4.7

ID
A g nVT
gds,M5 + gds,M7 ID + ID
VA,M5 VA,M7
1
1 V (4.18)

VA,M5 VA,M7
given transistor pairs M3/M5, M4/M6, and M7/M8 are of the same size. From CADENCE

simulations, n = 1.75, VA,M5 = 9.5 and VA,M7 = 7.6. This gives a gain of 93.

To find out how much the gain variation is, simulations are done on design corners.

MOS transistor models with threshold voltage variances of 100mV are used. The sim-

ulations are also done at two different temperatures: 27C and 100C. The gain ranges

from 97 to 100, within 10% of the nominal value 93.

Speed. It is obvious that the first pole is decided by the time constance at the opamp

output. Note that the opamp is working open-loop during the comparison phase. Assuming

negligible influence from zeros and higher order poles, the -3dB frequency is

1 1
f-3dB 2= 1 (4.19)
27T 27 C,,,t
gds5 + gds7
where C,,t is the total capacitance at the opamp output, which includes the load capac-

itance and parasitic capacitance of transistors M5 and M7. The gain-bandwidth product

is:

1S1
GBW = Af_ 3dB -1 -n
gds,M5 + gds,M7 27 1 + Ct
gds5 + gds7
Sgm,M 1 (4.20)
27rC,,t
I dsM1 (4.21)
271 nVTCout

Table 4.1 shows the simulation results with a load capacitance CL = 10fF:

where r = 1/(2rf-_3dB) is the time constant of the open-loop opamp.










Table 4.1: The opamp performance.
Total Current A f-3dB T GBW Phase Margin
64 nA 39.6 dB 48 KHz 3.32 ps 3.3 MHz 45


The slew rate SL = IbiasCout. A Cout of 10 fF will give a slew rate of 3.6 V/ps.

Offset Cancellation. CADENCE simulations have been done to predict the per-

formance of the offset cancellation. Two comparators with different sizes are used in the

pixel schematic in Figure 4.2. One comparator (comp_norm) has perfectly matched input

transistors Ml and M2 in Figure 4.7. The other comparator (compmis) has 25% length

mismatch between Ml and M2. The firing times of pixels at node A in Figure 4.2 are listed

in Table 4.2 for situations with and without autozero cancellation at different photodiode

current levels. For 25% length mismatch, it shows the errors (in the time domain) have

decreased from 0.95% to 0.21% and from 0.87% to 0.26% for photocurrents of 200 pA

and 2 pA, respectively.


Table 4.2: The firing time of pixels with and without the autozeroing circuit
Ipd = 200 pA Ipd 2pA
comp_norm compmis Error comp_norm comp_mis Error
w/o autozero 52.41 ps 51.91 ps 0.95% 5.077 ms 5.033 ms 0.87%
w/ autozero 54.79 ps 54.67 ps 0.21% 5.302 ms 5.288 ms 0.26%


When the TBARBASE imager was designed and submitted, the author did not

realize a high-gain amplifier was unnecessary. The opamp shown in Figure 4.9 was used.

This amplifier achieved high gain (79 dB) at the expense of speed. The cadence simulation

results on AMI 0.5 pm technology are listed below in Table 4.3. The offset cancellation

effects are shown in Table 4.4.

Table 4.3: The opamp performance.
Total Current DC Gain Unit Gain Bandwidth Phase Margin
54 nA 79 dB 5.1 MHz 500









Vdd Vdd

Vpl Ml Vpl M9


Svp M8
in M2 M3 Vin+ Vout


Vn M7


M4 M5 M6




Figure 4.9: Opamp used in the tested TBAR imager.

Table 4.4: The firing time of pixels with and without the autozeroing circuit using the
opamp in Figure 4.9
pd =200 pA Ipd 2 pA
comp_norm compmis Error comp_norm comp_mis Error
w/o autozero 54.41 ps 55.39 ps 1.8% 5.168 ms 5.266 ms 1.9%
w/ autozero 59.03 ps 59.00 ps 0.05% 5.629 ms 5.617 ms 0.2%


4.3 Asynchronous Readout Circuit Design
4.3.1 Design Methodology

The system diagram of the TBARBASE imager is shown in Figure 4.1. First note

that this is a mixed-signal system, with the analog photodiode and comparator inside each

pixel while the rest of the circuits are digital. Secondly, the digital circuits operate asyn-

chronously. This prevents adopting a standard digital design methodology, which uses a

high degree language (Verilog or VHDL) to describe and simulate digital circuits, and from

that a transistor implementation may be automatically synthesized using a library of stan-

dard cells. Part of the difficulty lies on that most commercially available tools and libraries

are targeting for synchronous systems. Although there are some CAD tools available from









the academic research community, major EDA vendors have not yet included such tools in

their product portfolios [41].

For this 32 x 32 TBARJBASE, there are about 38k transistors. Full SPICE simu-

lation was proven to be impossible. It takes more than one day to simulate about 20 pixels.

For larger arrays such as 128 x 128, the computation would be prohibitive.

Some researchers called for behavioral modelling of analog and mixed-signal cir-

cuits [54]. There are two reasons, one is the increasing size of analog systems, the other is

the heterogeneity of waveform types of interest. An example of the latter case is the phase-

lock loop (PLL), which operates in the frequency domain. For the mixed-signal system,

the ability of hierarchical simulation is important. Basically, in one simulation, different

blocks in a system can be simulated using different simulation engines. For example, digi-

tal parts are represented as abstract logic cells and simulated using VHDL, while the analog

parts are represented at the transistor level and simulated using SPICE.

The author has not been able to design the TBAR imager using the above approach.

One reason is the tight schedule, and another is that the mixed-signal simulation tools did

not work at the time. Instead, after carefully simulating each building block, we simulated

the whole imager for about two dozen pixel firings using CADENCE SpectreS. Circuits

were verified with extracted parasitic capacitors at the process and temperature corners.

Since this is a high speed digital design, the package parasitic inductors and capacitors

were also included in the simulation.

4.3.2 Asynchronous Circuit Design
4.3.2.1 Pixel digital control circuit

The pixel digital control circuit has been drawn in Figure 4.2 and described in

Subsection 4.2.1.

4.3.2.2 Arbiter

Row and column arbiters are used to choose one row/column when many rows-

/columns make simultaneous requests. The arbiters used in a TBAR imager are from the










paper of Boahen [32]. Arbiters with many inputs are built from two-input arbiter cells.

Column arbiter is not necessary in the TBARMEM architecture, as mentioned in Chap-

ter 3.

LOut 2-

ROut

LIn 2 ROut






LIn2 2
L t
LIn l ROut n~ -

LOut 1~ In
I- -
LIn 1

(a)


requestin_2 (LIn_2)
selectout_2 (LOut_2-)
requestout (ROut)
selection (RIn~)
request in _1 (LInl)
select out 1 (LOut_ l)

(b)

Figure 4.10: A two input arbiter cell circuit (a) schematic and (b) symbol.


The schematic and symbol of a two-input arbiter cell is shown in Figure 4.10. A

two-input arbiter cell has two lower ports and one upper port. Each lower port has one

requesting (LIn in the schematic) input pin and one selectout (LOut~ in the schematic)

output pin. The upper port has one request_out (ROut in the schematic) output pin and

one selection (RIn" in the schematic) input pin.

When at least one of the two active-high request signals, LIn1_ and LIn_2, makes a

request, the arbiter cell relays the request to the upper level by making ROut high, through










a modified OR gate at the lower right of the schematic. When this arbiter cell is selected

(acknowledged) by RIn~ from the upper level, two situations might happen: if both LIn_l

and LIn_2 are making the request, one of the LOut~ pins is selected arbitrarily by the flip-

flop at the left of the schematic; if only one of the LIn pins is making a request, that port

is selected. The CADENCE SpectreS simulation using AMI 0.5 /m technology shows

the forward propagation delay (from LIn to ROut) is about 0.4 ns, and the downward

delay (from RIn~ to LOut ) is about 0.3 ns. The simulation results are also shown in

Figure 4.11.






Transient Response [
v: /Rin~ -: /LOut2
6.0 : /ROut ,: /Lin2



4.0 \

S3.


.800n 10.10r


10.70n
e ( s )


Figure 4.11: Time delay simulation of a 2-input arbiter cell.


Row and column arbiters have many inputs. They are built from two-input arbiter

cells using the binary tree architecture shown in Figure 4.12. The requests are relayed up

the tree, while the selection is relayed down the tree. At any time, only one input port (at











the left side of tree) is selected provided there is a request from this port. In situations that

there are requests from many input ports, only one port is selected arbitrarily.


request 1-


select 21
request 2
select 3-
request 3















select8~-
request8

Figure 4.12: An eight inputs arbiter tree.


4.3.2.3 Row Interface


The row interface is used to control whether a row can be selected by the row

arbiter. It is located between the pixel array and the row arbiter, as shown in Figure 4.1.

There is one row interface circuit for each row. The circuit is shown in Figure 4.13. It

is implemented using an asymmetric C-element described by Martin [55]. This is a state-

holding operator with two inputs. One of the inputs, arbiter sel~ is the selection signal

coming from arbiter. The other input, row_sel_enable, comes from the latch control circuit.

There are three possibilities:


If arbiter sel~ is inactive, rowsel is inactive, no matter what state rowselenable.


If both arbiter_sel~ and row_selenable are active, the output rowsel is active.










*If arbiter_sel~ is active and rowselenable is inactive, the rowsel keeps the pre-

vious state.


Vdd


arbiter sel


row sel


Srow sel enable



row request- arbiter request
>---- /x----


Figure 4.13: Row interface circuit.



4.3.2.4 Latch and Latch Control

Latch and latch control circuits have been described by K. Boahen [32]. These

circuits are used to increase the throughput of address-event readout originally proposed

by Mahowald [56]. The latch cell and latch control circuits schematics are shown in Fig-

ure 4.14 [32]. There is one latch cell for each column and one latch control circuit for the

whole array. Below are functions of some important control signals:


b is used to control whether data on cox~ are allowed to come into the latch cells.


g~ indicates whether there are still valid data inside latch cells.


colrequest_n is the column arbiter request signal; and colseln is the acknowledge

signal coming through the throughput control circuit from column arbiter.


Ip monitors whether there are data on the cox~ lines.


row_selenable goes to the row interface circuit (shown in Figure 4.13). It enables

the new row selection signal goes into pixel array.













Vdd
I col select n
Vdd /

RES

1p H bx col request n



COX~



(a)
Vdd
Vdd


ip










b









Figure 4.14: Latch cell and latch control circuits. (a) Latch cell. (b) Latch control circuit.



latchdatai..,.l is valid after data on cox~ lines have already come into the latch.

This signal, together with rowsel, disable the pixels which have fired in the selected

row.


row_address_trigger lets the row address encoder update output row address.


Also note that:

1. cox~ comes from the pixel (Figure 4.2) and is shared by all pixels in the same
column.

2. colrequestn and colselectn are the request and select for the column arbiter
tree, respectively.










3. lp, b and g~ are shared by all latch cells.

The operation of this asynchronous circuit has been described by Boahen [32] us-

ing the concurrent-hardware-processes (CHP) description language [57]. It will become

clearer after the timing analysis in Section 4.4.

4.3.2.5 Throughput Control

The throughput control circuit, shown in Figure 4.15, is used to control how fast the

readout circuit can be. TG1 and TG2 are two transmission gates. Since they are controlled

col arbiter sel


encoder in


Scolselect n

Figure 4.15: Throughput control circuit.


by two non-overlapping clocks O1 and 02, at any time, at most one transmission gate is

open. colarbitersel is the selection signal from the column arbiter and colselectn goes

to the latch cell. col_encoder_in is the input to the column address encoder. By using two

transmission gates, we can control how fast the selection signals from column arbiter go

into the latch cell by simply adjusting the clock speed.









4.3.2.6 Address Encoder and I/O

A standard digital address encoder and an I/O circuit are used in this design. Their

descriptions are omitted.

4.4 Timing Analysis

In this section, the CADENCE SpectreS simulation results of the 32 x 32

TBARBASE imager are shown to get a better understanding of the operation of the asyn-

chronous readout circuit. The circuit is analyzed under two situations: imager reset and for

pixels firing simultaneously. We summarize the timing analysis using a finite state machine

(FSM) model.

4.4.1 Reset

When RES is active, the TBAR imager is reset. Below are some important signal

states in each building block.

4.4.1.1 Pixel and Row Arbiter

RES = 0 A = 0 rowrequest~ = 1 rowsel = 0

4.4.1.2 Latch Cell and Latch Control

all cox = 1 lp = 0 -latchdata_-, ..li = 0

column arbiter
RES~ 0 col_request_n 0 col_select_n = 0 g = 1


(lp = 0)AND(g~ = 1) rowselenable, b 1


In summary, during the reset phase, rowsel_enable = 1 allows the row interface to pass

the row selection signal from the row arbiter. b = 1 means the firing states can go into

latch cells.









4.4.2 Pixels Firing Simultaneously

In this simulation, there is a 32 x 32 pixel array. Assuming all pixels at row(l,

5, 9, 13, 17, 21, 25, 29) and column(l, 5, 9, 13, 17, 21, 25, 29) have exactly the same

photocurrent, the following events will happen:


Row Arbitration.

Pixels located at row(l, 5, 9, 13, 17, 21, 25, 29) and column(l, 5, 9, 13, 17, 21, 25,
row arbiter
29) firing simultaneously rowrequest~ (1,5, 9, 13, 17, 21, 25, 29) 1

row arbiter picks one row arbitrarily. In this example, the 29th row is selected (i.e.

rowsel_29 1) ) fired pixels in row (29) sent their states to latch cells: cox~ (1,-

5,9,13,17,21,25,29) {.

Figure 4.16 shows this process: rowrequest_29~ -+ rowsel_29 T-- cox~(l,-

25) 1. From this figure, we can see the delay from rowrequest~ I to rowsel_29 T

is about 5.5 ns, and the delay from rowsel_29 T to cox~ (1, 5, 9, 13, 17, 21, 25, 29)1

is 0.5 ns.

Latch Cell and Column Arbitration.

at least one cox- is active
b 1 -gxo(1,5,9,13,17,21,25,29) 1

column arbiter
fx(1) = 1

where fx(1) is one of the column arbiter selection signals picked by the column

arbiter arbitrarily. It is shown in Figure 4.17.

Latch Control(when there is at least one valid data value inside latches).


cox" = 0b Ip = 1 eg =o0
Co 0 b = 0(row_sel -_enable = 0)
b 1







89








Transient Response [
6. x: /I0/row_request_29~
J.0


7.0 : /I0/row_sel_29


1.0 .. -..-. .....

6.0 : /I0/cox_25~





1 ^^ ^ ^ mra- ^
0.0

2.2250u 2.228u 2.2310u 2.2340u 2.2370u 2.2400u 2.2430u
time ( s )



Figure 4.16: Waveforms of row arbitration.


f latchdataready 1 disable fired pixels
rowaddresstrigger 1T- enable row address output

In summary, when data (cox" signals) are already inside the latch cells (i.e., g~ is

low) and there are valid data on cox" lines (i.e., lp is high), the latch control circuit

will make three actions:


1. Making b (rowselenable) low. This will forbid new row selection by disabling
the row interface circuit.


2. Disabling the fired pixel of the selected row by enabling latchdataready signal.


3. Generating a rowaddresstrigger trigger signal to output the row address.


The above timging is shown in Fig. 4.18.


* Disabling Pixel.

















7.0 x: ]/0o/b


> 3.0
6. : /10/cox_1l



7.0 : /10/gxo_5
> 3.0

7.0 A: /10/gxo_1


5.0 : /10/fx_ 1
> 2.0
2 F23ju ?.32u 2.2341u ? 26iu ? 238u 2.2


Figure 4.17: Waveforms of column arbitration.


When the data are already inside the latch, pixels which have put data into latch cells

are disabled, as shown in Figure 4.19. Following the above case, row(29) has been

selected and it is being disabled now:


latchdataready = 1


row_sel_29= 1
l latch row 29 = 1 29
Slatch_ n 2 1 ) pixel (29,j) is reset
if node A in pixel (29,j) = 1


( row arbiter
row-request (29) 1 row-seli = 0
all cox~ = 1 -+ p = 0

Since all the fired pixels in the previously selected row have been disabled, pixel

request signals, cox", are high.


* Throughput Control

























6.0 : !]/g


6.0 F: /10/4atch .dat : ready










1 and 2 in Figure 4.15, respectively.
d 6.0 : /0r/rowaddresstrigger

2.226u 2.230u 2.234u 2.238u 2.242u 2.246u
time ( s )



Figure 4.18: Waveforms of latch control circuit.


By using two non-overlapping clock signals to control data transport between the

column arbiter and latch cells, throughput control is made possible. The column

address is actually synchronous with the control clock, as shown in Figure 4.20.

Note that cidown and catch in Figure 4.20 are two non-overlapping clock signals

tl and 02 in Figure 4.15, respectively.


SLatch Control (when all the valid data inside the latch cells have output their ad-

dresses.)

When the last datum (in this example, it is at column 29) in the latch cells has output

its column address, gxi_29 (colselect_29 in Figure 4.14(a)) goes down right after

c_latch goes down. This will cause g~ to rise up. As a result, b (and rowselenable)

goes high. Thus, the row interface circuit is open and new row selection is made




















/: 10/ watch _row 29


x: /10/row_request_29~


a: /10/row_sel_29


,0: !/0/COX_ .1


: /I0/p

1240u 2.2280u 2.2520u 2.2560u 2.2400u 2.2z


Figure 4.19: Disabling pixels.


possible. Up to this point, the TBAR readout circuit finishes outputting the addresses

of fired pixels in one selected row. This process is shown in Fig. 4.21.

4.4.3 Finite State Machine Model

From the above timing analysis and simulation results, we have seen the asyn-

chronous readout circuit is quite complicated. More insight can be achieved by modelling

the operation of the readout circuit as a finite state machine (FSM), as shown in Figure 4.22.

There are four states for this FSM: reset, standby, data-in-latch, and column-ad-

dress-output.


1. Reset (State I)

When RES = 1, the TBAR imager is reset. The important signal states have been

described in Section: 4.4.1.


2. Standby (State II)
















7.0 t: /Col_A2
1.0 1. ....
7. 0 : /Col_A3


7.0 0: /Col_A4

3I D

> 3.0 F-- i-^ f- ?_ F r
-1. ,-- ,- ,Z q --, ^, L , -- ,-- L,=, ,
F V P N -I' F q r q F i"


4.7u 4 8u 4.9u 5.0u 5 lu 5.2u 5.3u
time ( s )



Figure 4.20: Column Address Output.


When RES goes down, the TBAR imager enters into the standby state, waiting for

pixel firing. Since there is no firing, the important signals states are the same as in

the State I.


3. Data-in-latch (State III)

After one of the pixels firs, the TBAR imager goes from the State II to the State III.

In this state, fired pixels in the row selected by the row arbiter send their firing states

to the latch cells. The column arbiter begins to process data inside the latch cells

(i.e., outputs the addresses of the cells with valid data). As described above, three

actions are taken by the latch control circuit:


(a) Making b (rowsel enable) low. This will forbid new row selection by dis-

abling the row interface circuit.