• TABLE OF CONTENTS
HIDE
 Title Page
 Acknowledgement
 Table of Contents
 Abstract
 Introduction
 Surface inversion carrier transport...
 BiMOST fabrication and operation...
 Oxide trap charging and discharging...
 Separation of interface traps and...
 Current-accelerated CHE stress...
 Conclusions
 References
 Biographical sketch














Title: Oxide charge degradation of MOS transistor current and mobility in the linear and saturation ranges /
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Permanent Link: http://ufdc.ufl.edu/UF00097376/00001
 Material Information
Title: Oxide charge degradation of MOS transistor current and mobility in the linear and saturation ranges /
Physical Description: vi, 154 leaves : ill. ; 29 cm.
Language: English
Creator: Kavalieros, Jack Theodore, 1967-
Publication Date: 1995
Copyright Date: 1995
 Subjects
Subject: Metal oxide semiconductor field-effect transistors   ( lcsh )
Electrical Engineering thesis, Ph. D
Dissertations, Academic -- Electrical Engineering -- UF
Genre: bibliography   ( marcgt )
non-fiction   ( marcgt )
 Notes
Thesis: Thesis (Ph. D.)--University of Florida, 1995.
Bibliography: Includes bibliographical references (leaves 148-153).
Additional Physical Form: Also available on World Wide Web
General Note: Typescript.
General Note: Vita.
Statement of Responsibility: by Jack Theodore Kavalieros.
 Record Information
Bibliographic ID: UF00097376
Volume ID: VID00001
Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
Resource Identifier: alephbibnum - 002056279
oclc - 33803987
notis - AKP4290

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Table of Contents
    Title Page
        Page i
        Page i-a
    Acknowledgement
        Page ii
    Table of Contents
        Page iii
        Page iv
    Abstract
        Page v
        Page vi
    Introduction
        Page 1
        Page 2
        Page 3
        Page 4
        Page 5
        Page 6
    Surface inversion carrier transport theory
        Page 7
        Page 8
        Page 9
        Page 10
        Page 11
        Page 12
        Page 13
        Page 14
        Page 15
        Page 16
        Page 17
        Page 18
        Page 19
        Page 20
        Page 21
        Page 22
    BiMOST fabrication and operation and effective mobility extraction
        Page 23
        Page 24
        Page 25
        Page 26
        Page 27
        Page 28
        Page 29
        Page 30
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        Page 33
        Page 34
        Page 35
        Page 36
        Page 37
        Page 38
        Page 39
        Page 40
    Oxide trap charging and discharging experiments
        Page 41
        Page 42
        Page 43
        Page 44
        Page 45
        Page 46
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        Page 84
        Page 85
        Page 86
        Page 87
        Page 88
    Separation of interface traps and areal oxide charge nonuniformity
        Page 89
        Page 90
        Page 91
        Page 92
        Page 93
        Page 94
        Page 95
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        Page 108
        Page 109
        Page 110
        Page 111
        Page 112
        Page 113
    Current-accelerated CHE stress for rapid time-to-failure extrapolation
        Page 114
        Page 115
        Page 116
        Page 117
        Page 118
        Page 119
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        Page 141
        Page 142
    Conclusions
        Page 143
        Page 144
        Page 145
        Page 146
        Page 147
    References
        Page 148
        Page 149
        Page 150
        Page 151
        Page 152
        Page 153
    Biographical sketch
        Page 154
        Page 155
        Page 156
Full Text









OXIDE CHARGE DEGRADATION OF MOS TRANSISTOR CURRENT
AND MOBILITY IN THE LINEAR AND SATURATION RANGES
















By

JACK THEODORE KAVALIEROS


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


1995










ACKNOWLEDGMENTS

I wish to thank Dr. Chih-Tang Sah for his time, support and guidance throughout

the course of my graduate career. I would also like to thank Drs. Toshikazu Nishida

and Arnost Neugroschel for all their technical assistance and supervision as well as

their participation on my supervisory committee. Additional thanks goes to Drs. Zory

and Kurzweg for their role as members of my supervisory committee.

I am also grateful to Dr. Scott Thompson, Dr. Yi Lu, Michael Han, Steve

Walstra, Mike Carroll, Derek Martin, Kurt Pfaff and Steve Hunsinger for their

friendship and many insightful talks.

Finally, I wish to thank my wife, Monica Kavalieros, and my family for all the

years of encouragement and support they have given me throughout this endeavor.










TABLE OF CONTENTS

Page

ACKNOWLEDGEMENTS...................................................................................... ii

A B STR A C T .................................................................. ................................... ..... v

CHAPTERS

INTRODUCTION............................................................................... 1

2 SURFACE INVERSION CARRIER TRANSPORT
TRANSPORT THEORY...........................................................7

Theoretical Calculation of ................................................................. 7
Surface Q uantization............................................................................ 8
Crystalographic A nisotropy..................................................................... 10
Screened Coulom bic Scattering............................................. ........ ..... 11
Phonon Scattering............................................. .................................. 15
Surface Roughness Scattering.............................................................. 18
Physical and Semi-empirical Models...............................................20

3 BiMOST FABRICATION AND OPERATION
AND EFFECTIVE MOBILITY.................................................... 23

BiMOST Fabrication and Operation................................. ........... ... 23
M easurem ent of l ................................................................................. 28

4 OXIDE TRAP CHARGING AND DISCHARGING
EX PERIM ENTS..........................................................................41

Net Negative Charge Build-Up Due to SHEi........................................ 42
Charging and Discharging the Deep
Oxygen Vacancy Center at Ec-7eV.......................... ............. 68
Charging and Discharging the Shallow
Oxygen Vacancy Center at Ec-leV............................................. 78

5 SEPARATION OF INTERFACE TRAPS AND
AREAL OXIDE CHARGE NONUNIFORMITY.................... 89

Nonuniform +QoT via FNTEi........................................... ............. 90
Room Temperature SHEi Stress........................................ .............. 96
Uniform Oxide and Interface Traps.................................................96








Nonuniform Oxide and Interface Traps...................................................99
Low Temperature SHEi Results.................................................................104

6 CURRENT ACCELERATED CHE STRESS FOR
RAPID TIME-TO-FAILURE EXTRAPOLATION.................... 114

Conventional Channel Hot Carrier Stress......................................... 114
Bottom-Emitter Current-Accelerated CHE............................................118
Top-Emitter Current-Accelerated CHE................................................. 134

7 CONCLUSIONS............................. ................ ...............................143

REFERENCES............................................................ ....................................... 148

B IO G RA PH ICA L SK ETCH ......................................................................................154












Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

OXIDE CHARGE DEGRADATION OF MOS TRANSISTOR CURRENT
AND MOBILITY IN THE LINEAR AND SATURATION RANGES

By

Jack Theodore Kavalieros

August 1995


Chairman: Chih-Tang Sah
Major Department: Electrical Engineering

The effects of charged oxide traps on the electron effective mobility (or

conductivity mobility) and the linear and saturation currents in the inversion surface

channel of the n-channel metal-oxide-semiconductor transistor (nMOST) are

investigated. The deep Ec-7eV and the shallow Ec-leV traps of the oxygen vacancy

center in the gate oxide are charged using substrate-hot-electron injection (SHEi) and

Fowler-Nordheim tunneling electron injection (FNTEi) methods and subsequently

neutralized by electric field-stimulated electron (EFSE) emission or low-field SHEi.

The effective mobility, teff, and saturation mobility, 1sat, of the electrons are monitored

during charging and discharging cycles and shown to decrease because of increased

Coulombic scattering in the surface channel during the charging stage, and to recover

during the discharging stage. In addition, changes of the drain saturation current,

AID-sat, and gate threshold voltage, AVGT, are also monitored and the effects of AVGT








and Asat, on AID.sat are separated. A linear dependence of the electron effective

mobility, Aneff, on the separated positive and negative charges stored in the oxide is

demonstrated for the first time.

The effects of really nonuniform oxide charges and interface traps in the gate

oxide are separated using a new procedure which combines two experimental d.c.

characteristics: the subthreshold drain-current swing and the d.c. base recombination

current, IB. Electrons are injected into the gate oxide by really uniform and

nonuniform methods to demonstrate this new technique.

Finally a new current-accelerated channel-hot-carrier (CHC) methodology is

demonstrated for rapid time-to-failure extrapolation of submicron MOSTs. This is

demonstrated using the n-channel bipolar MOST (nBiMOST) test structure with AIB as

the monitor for the degradation. This technique gives an acceleration, or stress time

reduction factor as high as 200 at the low operation drain and gate bias voltages (less

than 3.3V) required in future generations of deep sub-half-micron MOSTs. This is in

contrast to voltage-accelerated channel-hot-electron CHE which uses higher stress

voltages (6V, 8V or higher) to elevate the kinetic energy distribution of the channel

electrons and therefore changes the dominant failure mechanisms.













CHAPTER 1
INTRODUCTION



Since the initial theoretical work on the carrier mobility in the semiconductor

surface inversion layer by Schrieffer [1,2] and the channel conductance measurements

of Brown and Kingston [3,4], mobility studies have been made extensively using the

metal-oxide-semiconductor field-effect transistor (MOST or MOSFET).

Characterization of the carrier mobility is essential for advancing today's deep

submicron ULSI (Ultra large scale integrated) circuit technology to manufacture multi-

million-transistor chips since it is directly proportional to the MOST's output current to

charge up the load capacitance which limits the clock frequency of digital ULSI

circuits and since it is also directly proportional to the MOST's transconductance and

the cutoff frequency which limits the bandwidth of analog ULSI circuits. Accurate

wide-range characterization of the carrier mobility requires an in-depth quantitative

understanding of the physical scattering mechanisms which limit the mobility in the

MOST channel. The physics-based understanding is essential to the development of

accurate MOST device simulators that do not rely solely on calibrations using

experimental data that cannot assure accurate mobility extrapolation outside of the

mobility calibration range.

As the complementary-MOS (CMOS) and bipolar-CMOS (BiCMOS) integrated

circuit technologies continue to scale down the gate oxide thickness (below 50A), and








the channel lengths (below 0.1 pm) [5-8], the impurity dopant concentrations in the

CMOS wells and the MOST channels have to be increased accordingly to minimize the

various short-channel effects which give undesirable MOST characteristics. The

electric field also increases as the dimension decreases. The higher electric field and

dopant impurity concentration confine the inversion layer charge closer to the

interface, causing a higher carrier scattering rate due to the proximity of the carriers to

the atomically rough oxide/silicon interface and the charges in the gate oxide. The

higher electric field also increases the electric instability of the gate oxide via electron

and hole trapping at the existing and stress-generated oxide traps and at the stress-

generated oxide/silicon interface traps. Furthermore, the higher transistor density from

smaller transistor dimensions would raise the operation temperature of the transistors

and the ULSI circuit chips. Thus, the three major mobility reduction factors are the

higher longitudinal and transverse electric fields, the confinement of the charge carriers

(electrons or holes) near the oxide/silicon interface, and higher operation temperatures.

The effects of trapped charges in the silicon substrate, gate oxide layer, and

polysilicon (poly) gate, and at the poly-gate/SiO2 and SiO2/Si-substrate interfaces on

MOST characteristics have been studied by numerous investigators and reported in the

literature [9]. The magnitude, sign, and distribution of these trapped charges, in

relation to the conduction carriers (electrons or holes) in the surface channel, can alter

the threshold voltage, VGT, and the channel effective mobility, both of which govern

the shape of MOST's drain current-voltage (ID-VD) characteristics. So far, studies on

the effects of these charges on the carrier mobility have been limited to carrier

scattering by the charged Si/SiO2 interface traps and ionized impurity centers in the Si







substrate, and the Coulombic screening of the charged traps by the large carrier density

in the surface inversion channel.

In general, confinement of the inversion carriers closer to the interface will

increase surface (atomic) roughness scattering and convert phonon scattering from the

three-dimensional (3-d) to the more effective 2-d 'surfons' scattering as the quantum

energy states in the potential well of the surface channel become quantized [10, p.668].

Furthermore, there will be increased Coulombic scattering from the charges in the

poly-gate and the oxide and interfacial layers mentioned above because of the closer

proximity of these charges to the carriers in the conducting channel. Carrier

confinement will reduce scattering from ionized bulk impurities unless there is a

corresponding increase in the impurity concentration; higher impurity concentration is

frequently used to suppress short channel effects in recent generations of submicron

MOSTs. The higher MOST operation temperature from higher dc power density will

also increase phonon scattering and reduce the coulombic scattering.

There have been two effective mobilities measured and theorized for the surface

channel and the MOS transistors. The first effective mobility is obtained from the

MOST's channel conductance measurements in the linear channel current-voltage

range, given by the drain conductance, gd=IoD/VD with VG=constant, in the linear

MOST drain current-voltage (ID-VD) range. This will be denoted by et, linear or liin*

The second effective mobility is obtained from the MOST's transconductance

measurements, gm=IlD/aVG with VD=constant, which will be denoted by 'tgm. This

experimental mobility is highly dependent on the energy and spatial distribution of the








interface traps at the oxide/silicon interface. Thus, it is difficult to obtain reliable

results from an analysis of the experimental data.

The third effective mobility is obtained from least-squares-fit of the experimental

saturation drain current versus gate voltage data (ID-sat-VG) to the analytical equation

based on the simple bulk-charge theory. This mobility will be denoted by s.at-

Two effective mobilities are measured and compared with theory in this thesis:

the linear and saturation mobilities, Plin and 'sat. The linear mobility provides the most

direct experimental evaluation of the various scattering mechanisms which reduce the

mobility. The saturation mobility gives the transistor parameter that goes into the

transistor model used in the circuit analysis of MOS ULSI circuits.

In this thesis the effects of charge trapping and detrapping, in the gate oxide

layer, on the two effective mobilities are studied. Variation of the drain current due to

controlled changes of oxide charge density will be correlated individually to AVGT and

Ajpat. This gives the effects of Coulombic scattering of the channel electrons by the

positive and negative charges in the gate oxide on mobility. All measurements were

undertaken using the n-channel bipolar-MOST (n-BiMOST) test structure, therefore,

the scope of this thesis is limited to the study of electron effective mobilities in the

surface channel. Nevertheless, the new fundamental understanding and new

experimental methodologies are also applicable to hole mobilities in silicon p-channel

MOSTs.

Results of detailed studies are described in this thesis on the variation of the

mobilities (iun and ,sat), gate threshold voltage VGT, and drain saturation current, ID-sat,

caused by the three charge states (-1, 0, +1) of the bridging oxygen vacancy in the gate





5


oxide. The oxygen vacancy was also known as the E' center delineated prior to 1979

by electron paramagnetic resonance experiments. The oxygen vacancy was charged

and discharged or neutralized by Fowler-Nordheim tunneling electron injection

(FNTEi), substrate hot electron injection (SHEi), and Fowler-Nordheim tunnelling

electron emission (FNTEe) techniques, while the MOST's ID-VG and ID-VD

characteristics are monitored. Koomen's [11] split-CV method was used to measure

the carrier capacitance in the inversion surface channel, Cinv, which was then used to

calculate the inversion carrier charge density, QiNv. The linear mobility was then

computed from tlin = gd/(W/L)QINv where W/L is the channel width to length ratio or

the aspect ratio. The linear ID-VG (at three constant VD: VDI, VD2, and VD3) and the

saturation ID-sat-VD-sat (VD = VG = Vpower-supply VG VGT = VD-sat) were measured

before and after each electron injection-capture/emission cycle which gave the VGT,

ID-sat tsat and utlin as a function of the charged oxygen vacancy center.

The second part of this research concerned the effects of nonuniform charging of

the gate oxide using channel-hot-electron (CHE) and substrate-hot-electron (SHE)

injection to stress the n-channel MOS transistor. A new technique is demonstrated for

separating the effects of uniform or nonuniform interface traps and nonuniform oxide

traps along the length of the MOST channel. The technique makes use of the recently

developed direct-current current-voltage (DCIV) method [12] to monitor interface trap

generation, and the well-known change of the subthreshold drain-current swing, AS, to

monitor the spatial uniformity of the trapped oxide charge during the controlled oxide

trap (oxygen vacancy) charging and discharging cycles. In addition, the recently

demonstrated current-acceleration methodology for rapid time-to-failure measurement








in bipolar junction transistors (BJT), proposed by Neugroschel and Sah [13], is

extended for the first time to MOS transistors under CHE stress. This new MOST

acceleration stress technique makes use of the BiMOST's unique vertical BJT bottom-

emitter junction to accelerate the time-to-failure while maintaining the same drain and

gate voltages (VD, VG), which determine the kinetic energy and distribution of the

injected carriers. This new MOST acceleration stress technique is further extended to

regular MOSTs which do not have a substrate junction emitter by forward biasing the

source junction as proposed by Sah. The three failure parameters measured are the

increasing base current measured by the DCIV method, the change in the gate

threshold voltage, and the change in the drain saturation current.

Chapter 2 will review the scattering mechanisms affecting the carrier mobility in

the surface inversion layer of MOS transistors. The measurement setup and BiMOS

transistor fabrication and operation details will be described in chapter 3. The effects

of charged oxide traps on the mobility, saturation current, and threshold voltage are

discussed in chapter 4. Experiments demonstrating a new measurement technique for

the separation of interface traps and areal oxide charge nonuniformity will be presented

in chapter 5. Finally, the two new current-accelerated channel hot electron stress

methodologies are presented in chapter 6 which forward bias the substrate or source

n/p junction emitter to increase the channel hot electron current.













CHAPTER 2
SURFACE INVERSION CARRIER TRANSPORT THEORY



The three primary scattering mechanisms which contribute to the inversion

carrier mobility degradation as reviewed by Sah and his graduate students [14-16]

included the following: 1) lattice scattering due to acoustical and optical phonons, 2)

Coulombic scattering due to ions and dipoles in the oxide and at the SiO/Si interface,

and impurities in the silicon surface space-charge layer, and 3) surface roughness

scattering due to the interfacial atomic irregularities. One must also consider

Coulombic screening by the inversion-layer carriers and the effective mass anisotropy

in 2-d conduction due to 1-d quantization in the surface channel's quantum well from

the high transverse electric field. These scattering mechanisms will be reviewed in this

chapter based on the theoretical analyses given by the previous investigators as

reviewed by Sah [14-16].



2.1 Theoretical Calculation of u.



The general theory of inversion layer transport and carrier effective mobility was

first presented by Schrieffer [1] to account for the reduced conductivity due to diffuse

surface scattering. Diffuse scattering refers to the assumption that the probability of

scattering is equal in every direction. Schrieffer solves the Boltzmann transport








equation using the relaxation time approximation to obtain the inversion carrier

distribution function,

f = fo + f(v.z) (2.1)

where f, represents a small perturbation to the equilibrium Boltzmann distribution

function, fo. Using a random scattering boundary condition to eliminate f, at the

interface, (x=0), the current density is found by integrating f, in the velocity space,

i = qdvdvydvz vyfi (2.2)

Here vy and vz are the carrier velocities parallel to the interface and x is the normal (or

transverse direction) to the interface. By integrating the current density from the

interface to the edge of the inversion layer, xi, one finds the total d.c. current, Iy, due to

a constant longitudinal field Ey. The conductivity effective mobility or linear mobility

is then defined as,

Iy = qjpdinN vEy. (2.3)

The inversion carrier density, NLNy, is calculated for an assumed triangular potential

well (constant transverse field. Ex),

Ex = dcF/dx = constant (2.4)

V24 = p/es (2.5)

or by solving the Poisson equation for the potential well profile at the silicon surface.



2.2 Surface Ouantization



Schrieffer at the suggestion of Bardeen [2] also recognized the possibility of 1-d

or transverse quantization at high transverse fields Ex near the silicon surface. As the








applied d.c. gate voltage increases the surface energy band bending, the potential well

at the silicon surface becomes narrower and deeper; eventually quantizes the motion in

the x-direction giving quantized (discrete) energy subbands perpendicular to the

surface. This restricts inversion carrier motion to the two dimensions, y and z, parallel

to the interface within each 2-d energy subband. The two-dimensional transport in the

surface inversion layer was first observed by Fang and Fowler [17,18] using

magnetoconductance measurements on a <100> silicon surface at low temperatures.

Stern, Howard and Fang [17-20] performed selfconsistent calculations of the

Schroedinger and Poisson equations to illustrate the energy splitting between the

ground and the first excited 2-d energy subbands. Calculations were made using the

variational approach with the assumption that all the carriers occupy the lowest energy

subband and that the potential is a function of x only. The boundary conditions

assumed were as follows: (i) the potential vanishes at x=o, (ii) the transverse field,

dQ/dx, vanishes at the interface (x=0), and (iii) the electron wave function P vanishes

at the interface (infinite Si02/Si barrier height or zero penetration into the oxide) and

deep in the bulk silicon (x=oo). The envelope function, 4(z), of the electron wave

function

T = 4(z)exp(ikx + ik2y) (2.6)

is then

4(z) = (z)exp[-iz(W13k1 + W23k)/W33] (2.7)

where (z) are the eigenfunction solutions of the Schroedinger equation and Wij is the

reciprocal effective mass tensor (1-x, 2-y, 3-z). Solving the wave equation, they

compute the energy eigenvalues and an average distance from the interface for








inversion carriers in the channel. Their results illustrate the dependence of the

quantized energy splitting on well doping concentration, temperature, transverse field

in the silicon, Ex, and crystal orientation.

Subsequent theoretical work by Pierret and Sah [21] supported the strong

variation in effective mobility with well doping concentration in weak inversion near

VGT (when the surface potential, (s, equals twice the bulk potential (s=2F)). They

also noticed that the effective mobility approached a common value versus doping at

higher transverse fields or as the inversion charge density became degenerate.



2.3 Crystalographic Anisotropy



In the surface inversion layer the silicon crystal's cubic symmetry is disrupted by

the transition into the SiO2 layer and hence one must also refine the isotropic bulk

mobility theory to include the crystal orientation dependence. The first theoretical

treatments were presented by Ham and Mattis [22] assuming a constant surface field

and using a special set of spatial transforms to convert the ellipsoidal energy surfaces

to spherical ones. Their constant transverse field, Ex, (or triangular potential well)

assumption was removed by Pierret and Sah [21] who gave the solutions for the exact

electric field which used the Boltzmann transport equation and considered the

distribution function, f, for each of the six ellipsoidal conduction valleys in E-k space.

The analysis was then converted from k-space to velocity space (v-space) using the

spherical relation for the velocity,

vx = (l/h)dE/dk (2.8)








while the appropriate mass tensor is substituted for the spherical effective mass, m*.

Pierret and Sah also assumed that the surface inversion layer is nondegenerate, there is

no intervalley scattering, and a constant relaxation time may be used. The key

difference in this solution compared to the isotropic case is that the inversion carrier

velocity in the longitudinal direction, vy, is now dependent on the transverse velocity,

vx. Fortunately, however, if the normal to the interface is in the <100> direction, vx is

once again decoupled from the carrier velocity parallel to the interface and conduction

becomes isotropic. Since the samples tested in the present study are oriented in the

<100> direction, as is the case in most of today's and future MOST technologies, the

effects from anisotropic conduction will not be included in this thesis.



2.4 Screened Coulombic Scattering



As discussed earlier, the sources of Coulombic scattering include 1) ionized

impurities in the surface space charge layer of the silicon substrate and the polysilicon

gate, 2) charges in the gate oxide, and 3) isolated or dipole type charges located at the

polysilicon- gate/oxide and oxide/silicon-substrate interfaces. The key parameters

governing this form of scattering are 1) Coulombic screening by the mobile inversion

charge in the channel, 2) the distribution of these mobile charges within the surface

space-charge layer in the silicon, 3) the proximity or distribution of all the Coulombic

scattering sources with respect to the inversion layer, and 4) the position correlation of

the scatterers or the degree of randomness in their spatial distribution. The general

problem for calculating mobility involves finding the change in potential energy of the








inversion carriers in the presence of these scattering centers. For example, if a scatterer

lowers the potential energy, then the carrier density increases in the vicinity of this

scatterer while the reverse is true for a decreased potential. Hence the mobile charge

redistributes itself so that the scattering center's potential is screened.

Greene and O'Donnel [23] first considered the problem of scattering in the

presence of surface charges. They calculated the surface reflectivity in terms of the

differential scattering probability for a shielded Coulombic potential of N randomly

placed surface charges. Ster and Howard [19] also reformulated their analysis for the

lowest energy subband in the quantized surface to account for the additional screened

Coulombic potential due to ionized impurities in the silicon depletion layer as well as

any oxide and Si/SiO2 interface charges. Using first order perturbation theory, their

assumed potential, Z(r), which varies with r=(y2+Z2)1/2 and x, induces a change in the ith

eigenvalue 6Ei(r) of the mobile inversion charge,

8E,(r) = -q,(r) = -qf6D(r,x)gi(x) dx (2.9)

gi(x) = (1/2)b3x2exp(-bx) = Ili(x)12 (2.10)

b = { [487tq2m3/el][NDEP + (11/32)NNv] }13. (2.11)

where gi(x) and Ci(x) are the charge distribution function and the normalized

eigenfunction for the Stern and Howard 2-d ground state subband [19]. The induced

charge density in the inversion layer, pind, is expressed in terms of the reciprocal

screening length si,

Pind(r,x) = (ej27c)qi si Fi(r) gi(x). (2.12)

Ning and Sah [24] extend this single ion formulation by solving Poisson's equation for

65 due to a distribution of oxide charge at rn locations in a plane within the oxide,








V280(r,z) 2sD(r)g(z) = (47t/e,)qI5(r-r.)6(z) (2.13).

NoxA is the total number of oxide charges in a sheet of area A with an oxide charge

areal density Nox. Once the potential fluctuation Q(r) is known, the scattering

transition rate, Fk,, is found using the 'golden rule' and the Ster and Howard [19] 2-d

ground state plane wave, P,

rk, = 27ti/ 2 ave. (2.14)

The inversion layer mobility, p, may then be found numerically or by using the Born

approximation to calculate Fkk,,

S= (q/m,)Jy'T(fo l)dy/Jfody (2.15)

I= Erkk.(l cosO). (2.16)

Ster and Howard [19] illustrate the use of the Born approximation for a single ionized

impurity located at x=xo and discuss the validity of this approximation in great detail

by comparison with numerical phase-shift calculations. The approximation is

inaccurate at extremely low temperatures, or high doping impurity concentrations or

other scattering charge densities. This stems from the first order perturbation analysis

used in this approximation which assumes the 2-d wave function, T, is unchanged in

the presence of the charged scatterers. Other sources of error found in this analysis

include the assumptions of a spherical effective mass, the neglect of screening by

inversion carriers and the possibility of conduction in higher energy subbands at higher

transverse fields, temperatures and inversion carrier densities. Furthermore, the

average distance between the inversion layer and the surface charge scattering centers

was shown to have a pronounced effect on the mobility as would be expected from the

1/r dependent Coulombic potential.








The subject of the charged scatterer's spatial distribution and the effects of

position correlation of the scatterer were treated by Ning and Sah [24, 25]. These

authors reformulate the scattering problem into a simpler 2-d case where the potential

perturbation arises from the spatial variations in the local charge density. The charge

density fluctuations 5p are represented as,

5p(r) = p(r) po(x) (2.17)

p(x) = ave (2.18)

where po(x) represents the x spatial dependence of p(r) averaged over the y-z plane. If

the thermal wavelength of the inversion carriers, kth, is much larger than the inversion

layer thickness, xi, then the inversion layer can be treated as a 2-d gas. Under these

conditions the perturbation analysis proceeds as before to solve for the scattering

transition rate and mobility. Three sample oxide and inversion charge distributions,

with or without the effects of screening and correlation were analyzed [24] and used to

analyze the data [25, 26]. Their results indicate that increased correlation and/or

screening by the inversion charge would increase the channel mobility.

The carrier scattering by neutral dipoles formed by the hydrogen passivation of

ionized surface states at the Si/SiO2 interface as first suggested by Sah also falls under

the analysis discussed here. This dipole scattering rate was derived by Hess and Sah

[27] using the aforementioned Born approximation. Their results indicate a T1.5

dependence in the mobility for T>1000K,

Dp = ,oT15/(NDpLDp2) (2.19)

where NDP is the density of dipoles at the interface and LDP is the effective spatial

separation of the positive and negative charges in each dipole.










2.5 Phonon Scattering



As the temperature of the semiconductor increases, scattering due to quantized

lattice vibrations, or phonons, will naturally increase. These lattice vibrations are

commonly categorized as acoustical, for those with lower energies, and optical (or

intervalley) for higher energies. The first theoretical analysis for surface acoustical

phonon scattering by Kawaji [28] was essentially a 2-d version of the Bardeen-

Shockley deformation potential theory for bulk semiconductors. In this analysis a

change in potential (assumed to be an inverted triangular well) at the Si/SiO2 interface

originates from longitudinal phonons whose wave vectors are confined to the 2-d plane

parallel to the interface. Hence these phonons only interact with inversion carriers

moving parallel to the interface. The lattice displacement, 6R(R), in a direction 'k and

the corresponding dilation, A(r), due to a lattice wave in the 2-d surface plane are given

by,

6R(Rl) = N2-12 ik [akexp(ikRn) + akexp(-ikRn)] (2.20)

A(r) = V-5R(R%). (2.21)

There are N2 vibrating lattice points, and L represents the number of atomic layers in

the conducting surface. The semiconductor density, p, and the mass per unit area, M,

in the surface inversion layer of thickness 'd' are then related as p=MLN2. The 2-d

deformation potential is given by, A(r)E2, where E2 is the deformation potential

constant which was obtained by fitting the theory to experimental mobility data. This







potential may now be used to calculate the scattering transition matrix element, M .,

between the quantized 2-d inversion carrier momentum states p and p',

Mp = fj,(p)A(r)E2llp(p')da (2.22)

p=p' k (2.23)

T-1 = fM2(1 cosO)v2d, (2.24)

The relaxation time, t, refers to the electrons traveling parallel to the interface with

wave functions ',P and ~', where v2 is the 2-d density of states along a constant energy

curve, k, in E-k space. Assuming a constant velocity, c12, for the 2-d phonon wave and

an effective longitudinal mass, m,,, for the inversion carriers in the 2-d energy subband,

the mobility is calculated as,

L = (qh3pc2d)/(m E2kBT). (2.25)

Considering only the 2-d ground state eigenvalue Ex(0) for the triangular potential

well, and given the transverse field as,

Ex = Ex(0)/qd = (47/Es)(QDEP + QINv) (2.26)

it is easily shown that d (the average distance of the inversion layer charge from the

interface) has a (NDEP + N,)-1"3 dependence and hence the mobility is proportional to

T-'(NDEP +NV)-13.

The theory was later refined by Ezawa, Kawaji and Nakamura [29] who

introduced the term 'surfon' to describe acoustic phonons that satisfy the interface

boundary conditions, but have bulk and surface modes of vibration. Their analysis

included various vibrations modes for the surfons and their electron interactions, as

well as the effects of anisotropic conductivity tensors for different crystal orientations.

Inter-subband transitions and intervalley scattering were not considered. Some of the








remaining discrepancy in the theory, on the order of 6X larger mobility than that

measured, was attributed to optical phonon interactions and possible differences

between the assumed bulk values of the constants, such as polarizability, E, and their

actual values near the Si/SiO2 interface.

For temperatures below 100"K the measurements of Sah, Ning and Tschopp [25]

showed that the mobility due to lattice scattering, jL, varies as 7.4x105/T by using the

approximation by Debye and Conwell for pI [30],

1/L = l/Iexp l/I (2.27)

where exp and tI are the experimental and ionized impurity values of mobility. At

higher temperatures (>150K) Sah-Ning-Tschopp [25] reformulated the theory to

account for optical or intervalley phonon scattering and found

PL = 108/T2. (2.28)

This solution was obtained by replacing the deformation potential, the phonon energy,

and the occupation number for acoustical phonons with their optical counterparts

which was also employed by Luong and Shaw [31]. The two relaxation times for the

optical and acoustical cases are assumed independent,

-1 = AI + 1. (2.29)

The resulting expression for mobility is given in terms of the purely acoustical

dependence tA=7.4x10/T, the optical and acoustical ratio of the deformation potential

constants Zo/ZA, and the optical phonon energy, h0Oq. A good fit to their mobility data

was obtained for T=20-3000K and a range of oxide and interface trap densities when,

Zd/ZA = 2.3 (2.30)

hcOq/k = 65050 K (2.31)








2.6 Surface Roughness Scattering



The possibility of mobility reduction due to the atomic irregularity at the Si/SiO2

interface was analyzed by Cheng and Sullivan [32-34]. Under very controlled

processing conditions, they were able to fabricate transistors using a variety of

oxidation conditions to alter the quality of the Si/SiO2 interface and a range of interface

trapped charge densities, NIT. Measurements were performed at liquid helium

temperature (4.2K) to minimize the interference of phonon scattering. Mobility was

extracted at high transverse fields or high inversion carrier densities to emphasize the

effects of surface roughness by bringing the mobile carriers closer to the interface. The

observed strong Nav (-1 < a < -1.5) dependence of the surface mobility at high fields

was attributed by these authors to atomic surface inhomogeneity.

The analysis for modeling this scattering mechanism is similar to that of surface

charges with a random spatial distribution in the oxide. In an ideal situation the

Si/SiO2 interface would be treated as a perfect plane. Differences in the crystal

structure of the Si substrate and the amorphous nature SiO2, are immediately evident in

their energy bands as well as their electrical and thermal conductivity properties which

prevent the Si/SiO2 interface from being completely planar. To model the apparent

atomic irregularity in the direction perpendicular to the interface, a random spatial

displacement, Ax(R), is imposed upon the potential V(x) of an ideal planar surface.

The perturbed Hamiltonian is given by,

H = h2V2/2m* + V[x Ax(R)] (2.32)

5V = V[x Ax(R)] V(x) = Ax.(aV/ax) (2.33)







and 8V is the first order perturbation of the potential. Assuming the same form for the

ground state wave function, V, as Stern and Howard [19], though translating the

boundary condition of P(x=O)=0, the matrix element for 8V, and the

scattering rate, Fk,, may be calculated. The derived relaxation time, T(k), exhibits a

strong dependence on the inversion carrier concentration and two adjustable

parameters related to the Gaussian distribution assumed for Ax(R),

1/T= (144t2q 4LA2mi/ s2h3)[NDE + (11/32)NINV]2

*f(1 cosO)exp[- (1 cosO)k2L2/2] (2.34)

where A is the mean asperity of the perturbation to the ideal plane and L is the

correlation length of the Gaussian distribution (Figure 6 in [32]). Assuming

completely independent scattering mechanisms, the reciprocal relaxation times for

surface roughness and the Coulombic scattering are added and used to find the

mobility in the usual manner,

1/i = 1/Tsr + 1/Tcoou (2.35)

[ = (q/m) (2.36)

Since various surface preparations have been used in the industry and reported in the

literature, and since the thermal oxide growth conditions (dry, wet, with or without

HC1, TCA, and nitrogen, varying temperature, etc.) also vary from one process to the

next, large variations in the asperity and correlation would be expected. Hence it

would not be unusual to find significant process variation in Lsr and its dependence on

NINv. Matsumoto and Uemura [35] refined the work of Cheng et. al. [33] by including

the effects of screening by the inversion layer and by selfconsistent calculation of V(x)

using the variational approach and the Stern and Howard [19] ground state wave








function. They also defined an expression for the effective field in the semiconductor

as,

Eef = ((x)8VC*(x)dx = 47q2/e[(NlNv/2)+NDEP] (2.37)

where the first term (inversion charge) in the parentheses will dominate at high fields

as expected. The relaxation time can therefore be expressed as a function of Ef,.

Harstein, Ning, and Fowler [36] have also measured the effective mobility at very low

temperatures while varying the oxide charge in their samples and have experimentally

separated the effects of Coulombic and surface roughness scattering using the

Mathiesiens rule. More recent measurements by Takagi [37] at 77K have shown close

agreement to the theoretically predicted (Nmy)-2 dependence for electron mobility

due to surface roughness whereas the mobility for holes demonstrates a weaker

(NiNv)-' dependence. Agostinelli [38] speculates that this may be due to the difference

in the distribution of holes in the inversion layer further away from the interface as

suggested by Moglestue's [39] self-consistent calculations on <100> silicon.



2.7 Physical and Semi-empirical Models



It would appear that out of the three different scattering mechanisms affecting

the inversion layer mobility, surface roughness scattering is the most difficult to

accurately model without experimental parameter fitting because of surface processing

dependence. Yet it should be noted that some of the recent experimental work has

shown a universal behavior for surface roughness scattering in devices processed by







different groups [37, 40-42]. In providing a physically based mobility model, Sah [10,

14-16] summarized the various scattering mechanisms affecting mobility as follows:

Electrons

tOnLA = 7.4x105/T Surface acoustical phonons (2.38)

LOnLO = .0x1 08/T1.9 Surface optical phonons (2.39)

Ponox = 103(3x10 "/Nox)(T/80) Oxide charge (2.40)

OnDP = 102(NDpL -1(T/300)1.5 Surface dipoles (2.41)

JtonSR = 1.5x1029q2/(IQ B+IQINv)2 Surface roughness (2.42)

tonci = 8.5x108/(NIoN)l/ Ionized impurities (2.43)

where QB is the bulk charge density and Nox is the oxide charge density. The total

mobility, pot, is found by Mathiessen's rule by adding the mobility terms listed above

as ['1. The hole mobilities were approximated by scaling the electron mobility by the

hole/electron bulk mobility ratio (pip/in1=478/1423) [14-16]. The transverse and

longitudinal field dependence are also given [10] as follows:

t = o[1+(IEyI/EcL)Y-1/y Longitudinal Fields (2.43)

1 = Ljo[l +(IEzl/EcT)] Transverse Fields (2.44)

ECL= Osat/Io = 1.02x107/Ro Electrons

ECL= Osa/Ro = 0.75x107/R(o Holes

ECT= 100 kV/cm

where Ey and Ez are the longitudinal and peak transverse fields in the silicon surface

layer, EcL and ECT are the critical longitudinal and transverse fields and the constants, y

and 6, are empirical constants which vary slightly with temperature and both

longitudinal and transverse electric fields.








Various other semi-empirical mobility models have been developed for electrons

[43-49] and holes [38] but as the term semi-empirical suggests, these models require a

priori knowledge of the device characteristics to establish the various fitting parameters

in the model. The model developed by Schwarz and Russek [43] which showed

excellent agreement with the experimental data of various groups [25, 40, 42, 50] was

extended by Shin et al. [45, 46] using a novel modeling approach, to account for the

low-field and high-field mobility drop-off. The model by Shin et al. model extracts the

functional dependence of the inversion layer mobility on local transverse and

longitudinal electric fields, substrate doping concentration, fixed interface charge and

temperature from the experimentally measured effective mobility, leff. Their model,

which was implemented in the PISCES 2-d device simulator, was shown to have good

agreement with experimental ID-VG and ID-VD data. These models though do not

account for the Coulombic scattering due to trapped oxide charge build-up during

stress or the distribution of this charge which are the primary topics of this thesis.

The following chapter will the discuss the theory of operation and fabrication of

the BiMOST test structure and various techniques used to extract the saturation and the

conductivity effective mobilities.













CHAPTER 3
BiMOST FABRICATION AND OPERATION AND
EFFECTIVE MOBILITY EXTRACTION




In chapter 2 the work of previous authors on the scattering mechanisms affecting

the inversion carrier effective mobility was reviewed. This chapter consists of two

sections on: 1) the fabrication and operation of the BiMOST test structure and 2) a

detailed description of the mobility extraction procedures. The following chapter,

chapter 4, will describe their applications to the experiments on the effects of charging

and discharging oxide traps on the degradation of the mobility, drain saturation current,

and threshold voltage.



3.1 BiMOST Fabrication and Operation



The BiMOST test structure, shown in Fig. 3.1, was employed in this study

because of the versatility it provides for studying the gate oxide layer. The physical

aspects which make this structure unique are that it combines a vertical n/p/n or p/n/p

bipolar junction transistor (BJT) with an n- or p-channel MOST on the surface. This

allows one to stress the SiOz/Si interfacial layer, inject charges into the gate oxide and

characterize the resultant degradation by methods not available using the MOS or













S (base) (collector) I 0 SO (collector)


Inversion ayer Space charge la er
Diffused p-Well/Base

Diffused n-Well Emitter Electron Injection

p- epitaxial layer

p' substrate

























Figure 3.1 N-channel BiMOST test structure biased for substrate hot
electron injection (SHEi).







bipolar transistors or the MOS capacitor alone. These features will be discussed in the

following section.

The BiMOST structure is in fact present in all CMOS and BiCMOS technology

today. A typical CMOS wafer and chip fabrication process begins with a highly doped

p-type silicon wafer of 6-inch or 8-inch diameter and 500-micron thick (to be denoted

by p+Si where + signifies high dopant impurity concentration which is the boron

acceptor for p-type Si). On the atomically flat and polished wafer surface is epitaxially

grown a thin lowly doped p-type silicon layer (to be denoted by p-Si layer where the -

or minus sign signifies low dopant impurity concentration). Using thermally grown or

deposited silicon dioxide (SiO2), silicon nitride (Si3N4), and polycrystalline silicon

films as a penetration mask and photolithography for pattern definition, the epitaxial

surface is selectively implanted with n-type (phosphorus or arsenic) and p-type (boron)

impurities to form the n-well and p-well in which the p-channel and n-channel

IOST's, respectively, are then built respectively. To achieve a good interfacial layer

for oxide growth, improve the surface mobility and minimize short channel effects, the

impurity profile in the wells is highly retrograded in today's production MOSTs with

<(.5micron channel length and in future state-of-the-art 0.1 ltm channel length MOSTs

[7]. A typical retrograde profile will have a peak impurity concentration on the order

of 108cm-3 at about 500A from the Si/SiO2 interface in the ion implanted silicon well

\ while the impurity concentration at the Si/SiO, interface is 1-2 orders of magnitude

belo%\ this peak. If the inversion layer of the MOST surface channel is about 30-100A

thick. as discussed in chapter 2, then the highly retrograde profile of ionized impurity

centers in the well x% ill play an important role in determining the effective mobility.








Summarized briefly, the following steps in the CMOS (fabrication) process would first

thermally grow the very thin (3.5nm for next generation and 6nm for Pentium P-6

announced by Intel in December 1994) gate oxide on the epitaxial surface and then

deposit a polysilicon layer (poly-Si or just poly) over the entire surface. Next, using

the poly as the ion implantation mask by etching holes or patterns through the poly and

the gate oxide layers using photolithography (known as the self-aligned process)

shallow n-type and p-type impurity ion implantation through the holes is made to give

the n+ and p+ source and drain islands and to dope the polysilicon gate to high n+ or

p+ conductivity. On a p+Si or n+Si 6" or 8" wafer, both a p-channel BiMOST with a

vertical p/n/p BJT and an n-channel BiMOST with a vertical n/p/n BJT can be

fabricated. A cross-sectional view of the nBiMOST is shown in Fig.3.1 which is

fabricated on a n+Si wafer.

Some of the MOSTs and BiMOSTs measured in this thesis investigation were

obtained from industrial mentors. They were completely processed in their state of the

art production facilities, hence, represent the cleanest condition attainable. Large area

pBiMOSTs and nBiMOSTs were also fabricated by this candidate in our university

clean room fabrication laboratory, at high yields, and by other graduate students and

professors in our research group. These large area transistors were fabricated on I "xl"

wafers which were cut from 6" or 8" diameter wafers provided by industrial mentors

who first oxidized the n/p-epitaxy/p+substrate and p/n-epitaxy/n+substrate 6"-8"

wafers. All the remaining fabrication steps, except ion implant, were carried out by

this candidate in our own clean-room device fabrication laboratory, which included

self-aligned process to define the gate, implant the source, drain, and poly-gate regions








(by a California silicon chip foundry), and evaporate aluminum contacts on the front

and back of the wafers. The industrial mentor supplied MOSTs were rectangular with

L=W=100t.m to L and W less than 0.5ptm. Those fabricated by this candidate were

large concentric circles with L=150pm and a large gate area (3.89X103cm2). Gate

oxide thickness covered the range of 3.5nm to 30nm.

One of the key advantages of the BiMOST test structure is that the oxide electric

field, Eox, the reverse bias voltage, VCB, across the inversion layer or the collector/base

junction and the injection current through the gate, IG, can all be varied independently.

This allows one to stress the oxide using the substrate hot electron injection (SHEi)

technique at gate bias voltages as low as VG=VGT near the threshold and well below the

Fowler Nordheim tunneling voltage or tunneling electric field For SHEi the vertical

n/p/n bipolar transistor is operated in the forward active mode of the bottom emitter

configuration with the bottom emitter-base junction (VEB) forward biased and the n-

channel/p-well space charge layer reverse biased. The forward emitter-base bias (VEB)

injects the minority carriers (electrons) from n-emitter into the p-base of the vertical

n/p/n BJT. These minority carriers (electrons) diffuse through the p-base and, upon

entering the surface space charge layer beneath the n-inversion channel, are accelerated

towards the Si/SiO, interface by the electric field in the surface space-charge layer of

the reversed biased collector/base and channel/base junction. If the accelerated

electrons have enough kinetic energy at the interface to surmount the Si/SiO2 electron

energy barrier (3.13eV for electrons and 4.25eV for holes), they will be injected into

the oxide conduction band (or valence band for holes injected in the pBiMOST). In the

oxide layer the injected electrons, now labeled oxide electrons or electrons in the oxide








conduction band, are accelerated further by the oxide electric field, Eox, as they transit

toward the poly-Si gate electrode and exit the gate terminal to give the measured gate

current. Only a small fraction of the injected oxide electrons will be trapped or

expended via one of numerous trap charging-discharging, generation, neutralization,

and even annihilation mechanisms in the oxide or at the poly-gate/SiO2 and SiO2/Si

interfaces. During the stress or SHEi, the gate current is maintained at a constant value

by varying the d.c. forward bias on the emitter/base junction. In former reports,

verified in this thesis, SHEi is really uniform, across the length of the channel, in

contrast to the ac avalanche injection or the dc channel hot carrier (CHC) or channel

hot electron (CHE) stress techniques. Areal uniformity greatly simplifies the analysis

of the MOST IV and CV characteristics since any distortion of the IV and CV curves

due to nonuniform charge in the oxide can be misinterpreted as interface traps

generated during the stress. By maintaining the reverse bias voltage on the

collector/base junction below breakdown, SHE injection remains uniform and enables

us to evaluate the initial quality (or oxide and interface trap densities) of the oxide and

Si/SiO2 interface, and also the effects of post oxidation processing undertaken by us.



3.2 Measurement of lhin



The effective mobilities (linear and transconductance) of electrons and holes has

been measured extensively in the literature using the MOST. Leistiko, Grove and Sah

[51] measured the dc or differential conductance, gd, of the inversion layer at low drain

voltages or in the linear ID-VD range, which was defined as







gd = (W/L)qfa(x)dx (3.1)

where c(x) is the conductivity of the inversion layer at a depth x below the interface

defined by C(x)=qt(x)N(x) where t(x) and N(x) are the electron mobility and electron

concentration at a distance x from the SiO2/Si interface (x=O). Thus, o(x) is the

electron conductivity (siemen or mho/cm) at a depth x in the inversion channel. The

length and width of the channel are L and W. The integration covers the inversion layer

thickness (x=O to xi). The drain conductance, effective conductivity or linear mobility,

and inversion charge density (q/cm2) are then,

gd = (W/L)qfj(x)N(x)dx = (W/L)tflinQNv (3.2)

Plin = gd/[(W/L)QNv] = fp(x)N(x)dx / Niy (3.3)

NINV = fN(x)dx = Q1yv/q. (3.4)

Approximating L and W of the large area devices by their drawn length and width, one

needs only to measure the drain conductance, gd, and inversion charge, QINv, to extract

"lin.

In this investigation, the drain conductance is calculated from the experimental

dc Ir-VDs characteristics in the linear region (VDs = VD Vs < 100mV) at very small

longitudinal electric fields in the channel. The channel inversion charge density can

either be measured using the approximation

QINV = Cox(VG VGT) (3.5)

or by two ac capacitance techniques to be described. Although the value of Cox in (3.5)

can be accurately determined using large area capacitors, the threshold voltage, VGT, is

rather ill-defined in weak inversion near VGT, making (3.5) very inaccurate.








A more accurate method for extracting QINV, known as the 'Split-CV' method,

was introduced by Koomen [11]. He used it only to study interface states in the

inversion range. In this method the gate capacitance contributions of the

source/drain/inversion layer (Cd+Cs) are separated ('split') from those of the bulk, Cb,

shown the in Figure 3.2 and they can be easily measured using the standard 3-terminal

capacitance meter. The assumptions are that the small signal excess majority carrier

charge is supplied by the bulk current dIB, whereas the contributions from interface

state, AnIT, and excess minority carrier inversion charge, An, are supplied by dlD and

dis. Thus,

Cd + C, =(l/co)(dlD + dIs)/dVG (3.6)

Cb = (/co)dIB/dVG (3.7)

If the interface charge density is low, then Cd+Cs maybe integrated over VG to give

QINv from weak to strong inversion,

J(Cd + C) dVG = qN = QINV (3.8)

This Koomen method was first implemented by Sodini, Ekstedt and Moll [52] to

measure the effective conductivity or linear mobility, fin-

The exact method for measuring the conductivity mobility in a surface inversion

channel was suggested and demonstrated by Shiue and Sah [53]. They employed the

frequency dependencies of the ac conductance and capacitance of the channel treated

as a distributed one-dimensional transmission line. They demonstrated consistency in

the linear or effective conductivity mobilities calculated from the experimental input

admittance data of the MOS channel transmission line in the subthreshold and

inversion ranges. This exact method involved measuring the input admittance






drain



base



rce


) dlB ) di+ d
S) dIB f) dID+dIs


Figure 3.2 Split CV or low frequency Cinv-VG measurement setup [33].








(capacitance and conductance) of the surface channel and analyzing the data using a

distributed-transmission line model known as the circuit technique for semiconductor

analysis (CTSA) [54, pp. 160-164]. The CTSA equivalent circuit for an MOST, Fig.

3.3a [54, p.164], is synthesized using a small-signal expansion of the Shockley

equations. The Cdg-overlap and Csgoverlap are the drain and source overlap capacitances.

Cdep(y) is the distributed capacitance of the depleted layer of the surface space-charge

layer. The charge storage capacitance of the electrons in the inversion channel, C,(y),

is related to the electron concentration (number per unit volume), N(x), by

Cn = f(q2/kBT)N(x)dx = (q2/kBT)NI (F/cm2) (3.9)

where

N, = IN(x)dx (#/cm2) (3.10)

Similarly, the conductance element of the channel is defined by

Gn = fJqp(x)N(x)dx (Siemen or mho) (3.11)

-= pin*qNl,

Puin =- (x)N(x)dx / N1,v (3.12)

which provides the rigorous proof of the definition given by (3.3).

To find Cn and hence Niyv, the CTSA circuit was simplified by ac short-

circuiting the gate, source and substrate (Fig. 3.3b). The distributed capacitance

element C(y) and the transmission line equations relating the small-signal input (vd, id)

to the output (vs, is) are,

C = Cn(Cdep+Co)/[C+(Cdep+Cox)], (3.13)

vd = vcosh(yL) + Zoissinh(yL). (3.14)

id = (v/Zo)sinh(yL) + i,cosh(yL), (3.15)














G,B

(a)




D Vd id G/Ay Vs i

Cdg-overlap Cdj C, Ay


TT
G,B


(b)








Figure 3.3a and 3.3b Distributed Transmission Line or CTSA model [32].
(a) Gate and Substrate ac short- circuited and
(b) Gate, Source and Substrate ac short- circuited


m,


1








Zo = [1/joCZGZ]/2 = (q3/kBTW)NVlin, (3.16)

y = [joC/G,]12 = [jo(q/kBT)/linj1"2 = (jo/Dlin)1/2 (3.17)

where W is the channel width, L is the channel length, Zo is the characteristic

impedance, y is the propagation constant, Dlin=(kBT/q)Pin is the linear or effective

diffusivity, and o is the measurement frequency. The measured short circuit

capacitance, Cs, approaches a value of CLW/3 when the measurement frequency is

much smaller than the characteristic frequency given by,

f = (GW/L)/3rT(CLW/3) = (l/tL2)(G./C) -> Dlin/(TL2). (3.18)

where the asymptotic expression is for weak inversion when C, << Cdep + Co. If the

depletion and oxide capacitances, Cep and C,,, can be obtained from the CV curve of a

large area capacitor, then, the value of C, and N1Nv can be determined.

It is noted that by dc grounding the bulk of the transmission line and ac short-

circuiting the source and drain, the input capacitance between the gate and source/drain

is identical to Cd+C, in Koomen's analysis. This provides a rigorous theoretical proof

for Koomen's empirical assumptions.

A typical split-CV or Civ-VG measurement, between gate and the source/drain

(base and emitter are dc grounded) of an n-channel BiMOST device, is given in Figure

3.4. The integrated Equation (3.8) gives the inversion charge density versus the gate

bias VG which is also shown in Figure 3.4. Figures 3.5 and 3.6 illustrate the

corresponding prestress linear and saturation current-voltage characteristics of the n-

channel BiMOST. The drain current saturation condition is given by VD = VG > VD-sat

= VG VGT. By extracting the drain conductance from the linear ID-VGS for three







25 1.0


20 0.8
A Split- CV Capacitance; f= 10kHz
o Inversion Charge Density QINV
15 0.6 o


> 10 0.4
U
5 0.2


0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VG / (1V)














Figure 3.4 Initial prestress Split-CV measurement @10kHz for an
n-channel BiMOST with gate area= 1.0E-4 cm2 and an
oxide thickness Xox = 150 A Temperature = 295K.







10-4 30

10-5
25

S20
10-7 r o Linear ID 20

10-s 15 88
S tO near gLm i
a 10-9 10

10-10
5
10"11'

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VG /(1V)












Figure 3.5 Linear and logarithmic plot of the ID-VG and g m-VG characteristics
for an n-channel BiMOST with gate area = 1.0E-4 cm2 and an
oxide thickness Xox = 150A at Temperature = 295K.
















'I

II


0.3 0.4 0.5 0.6 0.7 0.8

VG-sat = VDsat / (1V)


20



15



10
0 C


I0.9. 1.0
0.9 1.0


Figure 3.6 Prestress satureation ID-sat versus VD-sat = VG-sat data
(triangle marker) and a corresponding 2-parameter fit
to the mobility and the threshold voltage using the
Sah-Pao [35] model to include bulk charge effects.








values of VDs (90, 100, 1 10mV) the prestress effective conductivity or linear mobility

(Fig. 3.7) can be calculated using equation 3.2.

The second effective mobility investigated in this thesis was the mobility in the

drain-current saturation range, ,sa,. It was extracted from the experimental ID-sat VS

VG-sat data by least-squares-fit (LSF) the data to the Sah-Pao MOST d.c. equation with

bulk charge [55]. The two LSF parameters were lsat and VGT and the Sah-Pao

equations are:

ID-sat = satCo "V/L) {(V2/2) + VBVDs[1+(VDS/20F)] 12

(40FVB/3)[(1+VDs/2Fp)3 1] } (3.19)

VDS = VG-sat-VGT+VB+(V /4F)-VB[ +B(V/I 6F)+(VG-VGT+VB)/2F]1/2 (3.20)

VB = [4qNAEsoF] 1/Cox (3.21)

OF = kBTloge(NAA/ni) (3.22)

where NAA is the acceptor concentration in the silicon and ni is the intrinsic carrier

concentration. The temperature dependence of ni is given by [54, p.52]

ni = 2.50939x 019(m*/m)3/2(T/300)3/2exp[-EG/(2kBT)] (3.23)

where the energy gap, EG, and the effective mass ratio, m*/m, are given by

EG = 1.1700 + (1.059X10-5)T- (6.05X10-7)T2 (T<1500K) (3.24)

EG = 1.1786 (9.025X10-)T (3.05X10-7)T2 (T>150K) (3.25)

m*/m = (mNmp/m2)1/2

= 0.81577+3.4353X10-3T[1-(T/437.6)+(T/814.2)2+(T/1356)3. (3.26)

mN/mp = 1.065/0.647 # f(T) (3.27)


























0 1 2 3 4


VG /(1V)


Drain (or channel) conductance, gd, and conductivity
effective electron or linear mobility, [tn, as a function of
the d.c. gate bias voltage, VG.


0


S,
0~
'I


400



300



200

bJl

100



0


Figure 3.7








Deionization of the dopant impurities at low temperatures is also taken into account by

solving the following quadratic for the majority carrier hole concentration, P of an n-

channel BiMOST,

P2 + PKA KNAA = 0 (3.28)

KD = (l/gA)Nvexp[-EA/kBT] (3.29)

Nv = 2.50X1019 (mp/m)lS(T/300)'5 (3.30)

where Nv is the effective density of states in the valence band, and mp is the density of

states effective mass in the valence band. The degeneracy factor, gA, is assumed equal

to 4 and the activation energy for boron is taken to be 45meV. Similar expressions are

used for phosphorus in the p-channel case with EA replaced by ED=44meV.

The shift in the gate threshold voltage, AVGT, as extracted from the

aforementioned two-parameter fit to the drain-saturation-current data will be plotted

unless otherwise noted since VGT can also be extracted from the linear ID-VD

characteristics.

As indicated above, plin was obtained at VDs -- 0 and Ey -- 0 so there was no

hot electron effect or mobility reduction with increasing longitudinal electric field.

However, tsat was obtained at VD = VG = power supply voltage, hence hot electron

effects may be important in very short channels. This was not included in the Pao-Sah

equation (3.19), but can be readily modified [10, pp.667-670] for short channels.













CHAPTER 4
OXIDE TRAP CHARGING AND DISCHARGING EXPERIMENTS



Chapter 3 reviewed the fabrication and operation of the very versatile BiMOST

test structure and mobility extraction methods for the two effective mobilities, tli and

Lsat. In this chapter the effects of charging and discharging traps in the gate oxide layer

on the two effective mobilities, the drain saturation current, and the threshold voltage

will be demonstrated by experiments. The injection mechanism and the nature of the

traps being charged and discharged during the stress cycles will also be discussed. The

results in this chapter are obtained on the n-channel BiMOST and are therefore related

to electron conduction in the surface channel. The results support the theory of

increased Coulombic scattering as the net trapped oxide charge density increases, and

decreased scattering as the net trapped oxide charge density decreases. Furthermore,

the changes in plin, ,sat' ID-sat, and VGT are shown to be consistent with the expected

sign of the charging and discharging mechanism. The linear proportionality of the

mobility change with positive and negative oxide charge density suggests a single

species of oxide trap with three charge states (+, 0, -) as anticipated from the bridging

oxygen vacancy or E' center.

Since the ID-sat measurement is taken at the condition of VD = VG > VG VGT, the

MOST may actually suffer CHEi stress during the poststress characterization. To limit

any such measurement stress, the measurement voltages were kept low and only a








small number of triplet data points, with a minimum number of samples for noise-

suppressing averaging, were measured at each of the predetermined voltages shown in

Figure 3.6. To insure that the device is not inadvertently stressed during

measurements, the linear- and saturation-IV and the split-CV were measured

repetitively at the intended measurement voltages on an unstressed MOST to detect

any shift in VGT during future poststress measurements. The results are shown in

Figure 4.1 where the shift in the gate voltage was measured at a constant drain current

of 1 pIA and plotted versus the measurement cycle to a total of 72 cycles. In the first 22

cycles only the linear IV and split-CV were measured while the remaining 50 cycles

included the saturation IV measurement. Figure 4.1 shows that AVGT is less than

0.2mV or the oxide charge changes by less than 3x108 q/cm2 (from AQOT = CoAVGT

where Co = 6o/Xox is the oxide capacitance) after 72 cycles at an experimental

resolution better than 50ltV (108 q/cm2). Thus, this test assures accuracy of the

degradation data since the test shows that the MOST was not stressed significantly

during the measurement part of the stress-and-measure (SAM) experiments on

nBiMOSTs and nMOSTs undertaken in this thesis and described in the following

sections and the next chapter.



4.1 Net Negative Charge Build-Up Due to SHEi



The first stress-and-measure or SAM experiment was to stress the BiMOST by

SHEi at a constant 5MV/cm gate oxide electric field. The gate current was kept

constant during the stress at IG=3nA and the reverse bias on the collector base junction







1.0


0.5


S


-0.5


-1.0 I I I I I I I I
0 3 6 9 12 15


-1.0







-0.5 H
0
O O



1.0


TIME /(103 sec)


Ths shift in the gate voltage, AVG, of an n-channel BiMOST due
to repetetive measurement of ID-VG, Split CV, and saturation.
ID-sat VG-sat (=VD-sat).


Figure 4.1








was kept constant at 4V (VCB-breakdown > 15V). The shift of the following MOST

characteristics and material parameters due to the SHEi stress were measured: linear

and saturation ID-VG, transconductance gm, split-CV, QIN, llin and psat, and gd- They

are plotted as a function of VG in Figures 4.2a-d at two stress fluences, NNj = 0, 1.3

and 2.7xl018cm-2. The injection stress fluence is defined as the integrated electron

current flowing through the gate oxide,

NINJ = (l/qA)fIG dt (electron/cm2-sec) (4.1)

where A is the gate area and IG is the d.c. gate current. In Figure 4.3a the effective

conductivity or linear mobility is replotted as a function of the inversion charge density

QINv, which is proportional to the effective field in the silicon surface, as derived in

chapter 2, thus. this figure illustrates the true mobility degradation by eliminating the

effect of AVGT. For comparison, the approximate linear mobility is also computed

from the approximated inversion charge density using (3.5). QJyv = Cox(VG VGT).

The approximate [lin versus the approximate Q1yw is plotted in Figure 4.3b. The value

of VGT used here was extracted from the linear ID-VG near the peak gm which is the

industry standard criteria. Comparing Figures 4.3a and 4.3b, it is evident that the

approximate QIN underestimates lin. due to overestimating Qyv from using (3.5),

nevertheless, the decreasing trend in the mobility with increasing stress fluence, Nj, is

still clearly evident in Figure 4.3b. These results are representative of the Xox=170A

BiMOST with a gate area of A=100xl00m2. The positive gate voltage shift indicates

a buildup of net negative charge trapped in the oxide. The extracted threshold voltage

shift, AVGT, is shown in Figure 4.4 versus the electron injection fluence through the

gate. The repeatability of these results is monitored versus fluence rather than stress








10

105

10-6


10o


'I

II


108

10-9


1-10 -

10-11
10-12
0.0


















Figure 4.2 a


0.5 1.0 1.5 2.0

VG /(1V)


20



-15



-10



5
-



-0
2.5


Shift in the linear IV of an n-channel BiMOST due to
SHEi stress at a constant Eox = 4MV/cm. The curves for
three different fluences are plotted.

















'C

cjr


10- 111 I I I I I
0.2 0.4 0.6 0.8 1.0

VG-sat = VD-sat / (1V)


Figure 4.2 b


Shift in the saturation IV of an n-channel BiMOST due to
SHEi stress at a constant Eox = 4MV/cm. The curves for
three different fluences are plotted.


15





10 <




5 i
d -














S15-
-i

> 10-


5


oLA
0
















Figure 4.2 c


4
Split CV Capacitance; f= lOkHz




20


SInversion Charge Density
A NINJ = 0.0 cm"2 1 Q4





VG /(1V)














Shift in the split-CV and QINv of an n-channel BiMOST
due to SHEi stress at a constant Eox = 4MV/cm. The
curves for three different fluences are plotted.













0

;>


o
0

c
*t-


0.5 1.0 1.5 2.0

VG /(V)


Figure 4.2 d


r-200



-150



100



50



L. 0
2.5


Shift in the effective mobility and gd of an n-channel BiMOST
due to SHEi stress at a constant Eox = 5MV/cm. The curves for
three different fluences are plotted.












f 500


G ~- A NINJ = 0.0 cm-2
400 NJ = 1.3X10'cm-2
400 13 NINJ = 2.7X1018cm-2




300
0 2 3 4

QINV /(10-7 C/cm2)













Figure 4.3a Shift in the effective mobility of an n-channel BiMOST due
to SHEi stress at a constant Eox = 4MV/cm. The curves for
three different fluences are plotted.












0
a)

S.-

0\
S.


0 1 2 3 4


COX(VG-VGT) QINV /(10-7


C/cm2)


Figure 4.3 b Shift in the effective mobility of an n-channel BiMOST due
to SHEi stress at a constant Eox = 4MV/cm. The curves for
three different fluences are plotted versus an approximated QNv.












>^
S



0

<3


0 0.5 1.0 1.5 2.0 2.5 3.0

NIN /(10"8 cm-2)


-20





--i

CN
-10

0


0


Threshold voltage shift of n-channel BiMOST during SHEi at
T=2950K, Eox= 4MV/cm, VcB = 4V and at a constant IG=3nA.


Figure 4.4








time since the gate current sometimes varies from device to device. In Figure 4.5a and

4.5b the degradation of the saturation current. AID-sat, is plotted versus the injection

fluence, NINJ. In Figure 4.5a the value of ID-sat is extracted at a constant value of VD =

VG > VD-sat = VG VGT whereas in Figure 4.5b ID-sat was extracted at VG VGT: which

includes the variation of VGT with NINJ. Thus, Figure 4.5a illustrates the contributions

to AID-sat from both the shift in the threshold voltage, AVGT, and the degradation or

change of the saturation mobility AIsat whereas Figure 4.5b AID-sat contains only the

contributions of Ajsat. The percent change in the effective saturation mobility, Pat, and

the effective conductivity or linear mobility, Plin' versus the injection fluence is plotted

in Figure 4.6. The value of tlin was monitored for a variety of constant QIv values to

maintain a constant surface field in the silicon. As clearly evident in Figures 4.3a and

4.3b, the mobility curves converge at large Q1Nv and hence the shift in fin is less as

shown in Figure 4.6. In Figure 4.6, the prestress values of |in range from 557cm2/V-

sec near the peak of the curve at QrNv=1.34x10-7C/cm2=8.4x10'1q/cm2, to 532cm2V-

sec at Qriv=2.51x10-7C/cm2=1.57x10'2q/cm2, while the prestress value of the effective

saturation mobility is 518cm2/V-sec. Figure 4.6 indicates that the saturation mobility

is more sensitive to the increasing charge in the oxide. To summarize the results,

Figure 4.7 plots the extracted AVGT, A1lin, APsat versus the total AIDsat ('D-sat extracted

VD = VG = IV = constant).

In order to quantify the effects of interface traps on the mobility, in addition to

the just-described effects from the oxide charge buildup during the stress, two methods

were employed to measure the increase in the interface trap's quantum density-of-state,

DIT. The first is the commonly used method of monitoring the change of the





















-80 VD-sat VG-sat = U.Y V, D-sat =-1U"1I
VDsat =VG-sat = 1.0V; D-sat =14.7pA

-100 1. 1.
0 0.5 1.0 1.5 2.0 2.5


NINJ /(1018cm2)


Figure 4.5 a


Shift in the saturation current of an n-channel BiMOST due
to SHEi stress at a constant Eox= 4MV/cm. The value of ID-sat
was extracted at a constant value of VD-sat = VG-sat.


-20


-40


-60


cdi


3.0








01


-20


-40


-60 I
A V
o V
-80-


-100 I I
0 0.5


1.0 1.5 2.0 2.5 3.0


NINJ/(1018cm-2


Figure 4.5 b


Shift in the saturation current of an n-channel BiMOST due
to SHEi stress at a constant Eox= 4MV/cm. The value of ID-sa
was extracted for a varying value of VDsat = VG-sat plus the
extracted value of VGT.















1. -10

-15sat
1 A nlnf @ QIN =1.34X10-7C/cm2
o A~lt, @ QIv =1.54X107C/cm2
-0 Ap L @ QIN =1.73X10-7C/cm2
-20 0 Ap~1i @ QINv =2.12X10-7C/cm2
v A~tln @ QjIN =2.51X10-7C/cm2
-25 I. I 1 I II I I I I
0 0.5 1.0 1.5 2.0


2.5 3.0


5

0

-5

-10


-15

-20

-25


NIN /(1018 cm-2


Figure 4.6


Percentage shift in the conductivity effective mobility, lin,
for varying values of QNv, and in the saturation effective
mobility, tsat plotted versus fluence for an n-channel BiMOST
during SHEi stress at constant Eox=4MV/cm and VCB = 4V.








-25


-20


o AVGT -15


-10




0
0 -10 -20 -30 -40 -50 -60

0 -10 -20 -30 -40 -50 -60


%AID-sat


The relative change in threshold voltage, VGT, the conductivity
effective mobility, plin and the saturation effective mobility, Psat,
versus the corresponding degradation in ID-sat for an n-channel.
BiMOST stressed at Eox = 4MV/cm.


S
'I


Figure 4.7







subthreshold voltage swing, AS, in which the inverse slope in the prestress

subthreshold portion of the ID-VGS data is measured and compared to that measured

after each stress. Although the ideal theoretical value at room temperature is

AVG=2.303kBT/q=60mV per decade of ID, a measured value of 80mV per decade is

more common due to thick oxide and high substrate doping variation [10, Fig.682.1 on

p.655]. The relation of the density of the generated interface trap to the subthreshold

swing, AS, is given by {See reference [10], Eqns.(683.10) and (683.11) on p.666.}

ADIT = DIT(tstes DIT(0) = (Cox/q)(q/2.303kBT)AS (#/eV-cm2). (4.2)

In our samples, the prestress density of interface traps is negligible and may be

assumed zero,

AS = S(DIT) S(DIT=0) = S(DIT). (4.3)

The second approach is a new method for measuring DIT buildup recently

proposed by Neugroschel and Sah, and demonstrated by them and their graduate

students [12]. This method takes advantage of the unique feature of the vertical bipolar

junction transistor (BJT) structure in the BiMOST and the fact that the buildup of the

BJT base recombination current, AIB, is directly and solely proportional to the buildup

of the interface trap density because the additional recombination of the minority

carriers (electrons in the p-base layer of n/p/n BJT of the nBiMOST) occurs at

generated interface traps. They demonstrated the extraction of the interface trap

density from the change of the stress-induced increase in the base current after each

stress cycle. This new method was coined and acronymed by Sah as the so-called

direct-current current-voltage measurement or DCIV.








The relationship between the change in the base current, AIl, the surface

recombination velocity, So, and the emitter base bias, VBE, is given by [12]

AIB = (qAniAS/2)exp(qVBE/kBT) (4.4)

ASo = (t/2)aothANIT (4.5)

where co is the cross-section of carrier capture at the interface traps, 0th is the carrier

thermal velocity, and ANIT is the stress-generated interface trap density (#/cm2). The

base current, Ig, versus the gate to base d.c. bias, VGB, measured during the SHEi stress

at Eox=5MV/cm is shown in Figure 4.8 for three stress fluences, NINJ = 0. 1.3 and

2.7xl018cm-2. A comparison of the two measurements, AS and %AI, is shown in

Figure 4.9 versus the injection fluence where %AIB/100 is calculated from,

%AIB/100 = [I,(tstre) IB(0)]/IB(0) (4.6)

where IB(0) is the prestress value and tst,,r is the stress time or the stress fluence.

The results of the two interface trap monitoring methods indeed track each other

quite well. The value for DIT plotted was calculated from AS assuming there are no

interface traps in the unstressed sample. A calculation of DIT from AIB would require

an assumption for the cross-section, oo. In the following chapter a more thorough

comparison of AS with AIg will be given to separate the effects of interface traps and

area (y-direction) nonuniformity of trapped oxide charge.

In order to investigate the effect of different charge distributions within the oxide

(x-direction) another device from the same 170A group was stressed at a lower gate

oxide electric field of 4MV/cm with all other stress and characterization parameters

remaining the same. Minority carriers traveling through the gate oxide during the

SHEi will now have a lower kinetic energies and will give a different oxide charge

















'I


-1.0 -0.8 -0.6 -0.4 -0.2


VGB /(1V)


Figure 4.8


Increase of the base current of an n-channel BiMOST due
to the build-up of interface states during SHEi stress at a
constant Eox=4MV/cm. IB is plotted for three different fluences.


0.0









0
0





0


C)1
t


Ut


0 0.5 1.0 1.5 2.0 2.5 3.0

NINJ /(108 cm-2)


Figure 4.9


-,


0

CD

CT
10 -




0-

0


Shift in the subthreshold slope, S, and the corresponding increase
in the base current, AIB, of an n-shannel BiMOST due to the
the build-up of interface states during SHEi stress at a constant
Eox=4MV/cm.








distribution in the thickness direction or x-direction of the thin gate oxide film, QoT =

Qo.(x). Furthermore, the lower electric oxide field of 4MV/cm will give a lower field-

aided and tunneling emission rates of electrons trapped in shallow energy levels in the

oxide. Figures 4.10-4.14 give an illustration of the oxide electric dependence of the

stress induced AVGT, A tIDsat, Alin, ALsat, AS and Al1 versus fluence for Eox=3MV/cm

and Eox=4MV/cm. The degradation of all these parameters indeed increases with

increasing gate oxide electric field. Furthermore the lower field stress appears to cause

a saturation of these parameters at a lower fluence, indicating that the oxide trap

charging or discharging rate may be lower and that the traps being filled by or emptied

of electrons have a larger capture or emission cross-section. In order to make a fair

comparison of the degradation in the extracted Aiin and A~sat at the two gate oxide

electric fields, Figure 4.12 should be replotted versus the trapped charge density, QOT.

Hence if the spatial distribution (in x-direction or the oxide-thickness direction) of the

stress built-up oxide traps at different Eox and stress conditions were the same, the

degradation in the two effective mobilities would be the same. However, the two

mobilities and drain current are also degraded and the gate threshold voltage is also

changed by the stress-generated interface traps which cannot be reversed during the

electronic neutralization of the oxide traps by electron thermal capture and tunnel

emission, because the generated interface traps cannot be removed or annealed

electronically. The two experiments described in the next two subsections will

demonstrate the reversibility of inl, Vsat, ID-sat, and VGT during the positive and negative

charging and neutralization cycles of the oxide traps.
























0 0.5 1.0 1.5 2.0 2.5 3.0

NINJ /(10" cm-2)


Figure 4.10


-20


0


-10

0



0


Threshold voltage shift of n-channel BiMOST during SHEi at
Eox=3MV/cm and Eox=4MV/cm; VcB=4V; T=2950K.


200


S


150



100



50























0 0.5 1.0 1.5 2.0 2.5 3.0


NINJ /(108 cm-2)














Figure 4.11a Shift in the saturation current of an n-channel BiMOST due
to SHEi stress at Eox=3MV/cm and Eox=4MV/cm. The value
of ID-sat was extracted at a constant value of VD-sat= VG-sa..

























0 0.5 1.0 1.5 2.0 2.5


NINJ /(10


Figure 4.11 b


3.0


18 cm-2)


Shift in the saturation current of an n-channel BiMOST due
to SHEi stress at Eox=3MV/cm and Eox=4MV/cm. The value
of ID-sat was extracted for a varying value of VD-sat= VG-sa. plus
the extracted value of VGT


0


-10


,-,


-20


-30


-40


-50







5

0

-5

-10

-15

-20


I-I1 II ll i 1 1 1111111. 11,1 I lIi1 1 1 -25
0 0.5 1.0 1.5 2.0 2.5 3.0


INJ /(1018 cm-2)


Figure 4.12


Percentage shift in the conductivity effective mobility, tllin and
saturation effective mobility, Psat of electrons plotted versus fluence
for an n-channel BiMOST during SHEi stress at Eox=3MV/cm and
Eox=4MV/cm and VcB=4V.


-10

-15

-20

-25
























NINJ /(108 cm-2)


Figure 4.13


Shift in the subthreshold slope, S, and the corresponding increase
in the base current, AIB, of an n-shannel BiMOST due to the
the build-up of interface states during SHEi stress at a constant
Eox=3MV/cm and Eox=4MV/cm and VCB=4V.


0




H


20




0

10 o



<3


3.0
3.0
















-10

-15 A Eox=3MV/cm
So Eox=4MV/cm
-20-


-25 I I i I i I
0 5 10 15 20


5

0

-5

-10

-15


-20


-25


NOT + NoT / (100 cm-2)















Figure 4.14 Percentage shift in the conductivity effective mobility, ,neff and
saturation effective mobility, ,sat of electrons plotted versus the
net trapped charge density for an n-channel BiMOST during SHEi
stress at Eox=3MV/cm and Eox=4MV/cm; VcB=4V.








4.2 Charging and discharging the deep oxygen vacancy center at Ec 7eV



One of the recently identified and studied defects in the SiO2 quartz, optical

fibers, and MOST's gate oxide is the E' center, commonly known as the bridging

oxygen vacancy center, pictured in Figure 4.15. The chemical symbol to be used in

this thesis will be Vo for the bridging oxygen vacancy center, and V', Vo, and Vo for

the center in the three charged states as proposed by Sah to account for the electronic

transitions between the multi-charge-states of the oxygen vacancy center [54, Fig.B3.4

on page 422.]. Thompson [56, 57] monitored the buildup kinetics of positive charge in

the oxide during FNTE or SHE injection stress at high oxide electric fields (Fig.

4.15c). His findings were attributed by Sah to the bridging oxygen vacancy [54,

Fig.B3.4 on page 422.]. The E' center has been well known in fiber and optical glass

investigations and its microscopic configuration indicated in Figure 4.15d was

delineated by electron paramagnetic resonance spectroscopy [58]. It is but only one of

the charge state configurations of the oxygen vacancy center, that is detectable by spin

resonance of an unpaired electron. The multi-charge-state and transition energy band

model proposed by Sah, as depicted in Figure 4.15c, suggests that positive oxide

charge is created when one of the bound electrons at an initially neutral oxygen

vacancy site [(Si-O)3-Si"Si-(O-Si)3], is impact emitted or released by an energetic

electron (kinetic energy > 7eV). In Thompson's experiment suggested by Sah,

electrons were injected into the gate oxide from the gate electrode during FNTEi or

from the substrate during SHEi. They were then accelerated to 7eV by the oxide

electric field to gain sufficient kinetic energy to impact release the bond electron at the











t
Cn+1


Ec-7eV


Sh+ eV
o =Ev+leV


Figure 4.15


Energy band diagram illustrating the various states of the E' center
otherwise known as the oxygen vacancy; (a) thermal or tunneling
emission from a shallow state, (b) thermal capture at a shallow state,
(c) generation of positive charge by impact emission of a bound
electron by an energetic electron injected from the substrate or poly-
gate, and (d) thermal capture at the deeper level (Ec-Et=7eV)
[51, Fig. B3.4]


n
en-1


t
Cf0





9-




0


9*-
9J-
.1 _


n
eno








neutral oxygen vacancy. These positively charged oxygen vacancy centers can then be

neutralized by capturing electrons (Fig. 4.15d) from low-field SHEi, at sufficiently low

oxide electric field such that the kinetic energy gained by injected electrons in the

oxide is less than about 7eV and impact emission of the newly captured electrons

would be avoided.

The results of charging and discharging the 7eV oxygen vacancy center under

high and low oxide electric fields and the effect of charge on the electron mobility and

ID-sat will now be discussed. An n-channel BiMOST (Xox=170A) was first subjected

to the low field Eox=1.5MV/cm SHEi stress to fill any already positively charged

states in the oxide. The positive threshold voltage shift, AVGT, is shown in Figure

4.16a and enlarged in Figure 4.16b at low fluence (N\,<4X1014/cm2). Next electrons

were Fowler-Nordheim tunnel injected from the poly-gate into the oxide to impact emit

the trapped electrons from the Ec 7eV level of the Vo center in the oxide giving Vo +

e-* V' + 2e-. The resulting negative threshold voltage shift is illustrated in Figure

4.16a. Finally the oxide was again SHE injected at Eox=1.5MV/cm to refill the

positively charged centers, V+ + e- Vo, as indicated in the enlargement of Figure

4.16c for (9x1015 < NINJ < 9.4xl015cm-2). Clearly VGT recovers almost completely, to

within 10mV of the initial value after low-field SHEi.

In Figures 4.17 and 4.18 the corresponding AIDsat are shown. The value of ID-sat

was extracted at a constant VD=VG in Figure 4.17 and at VD=VG adjusted by AVGT in

Figure 4.18 to separate the mobility and threshold voltage contributions to AID-sat

These two figures differ drastically due to the fact that the built-up oxide charge does

not seem to affect the value of tsat as much as VGT. Therefore the degradation























-100 a
S---- Eox = 8MV/cm ::

-125
0 25 50 75 100

NINJ /(1014 cm-2)

(c)


1 2
NNj /(1014 c-2 )


90.5 91.0 91.5 92.0 92.5 93.0 93.5
N,, /(1014 m-2 )


Figure 4.16


(a) Threshold voltage shift of n-channel BiMOST during SHEi at
Eox= 1.5MV/cm enlarged in (b) for NINj<4 xl014, followed by FNTEi
from the gate at Eox = 8MV/cm, for 4 x1014< NINJ< 9 xl015 ,and again
by SHEi at Eox=1.5MV/cm for 9 x1015< NINJ< 9.4 xl015 enlarged in (c).


S

'I

H$


-25

-50

-75


-5



0


5 H


10 o
CQ


15




























-20 I I I I I I I
0 25 50 75


100


NINJ /(1014 cm-2)

(c)
____. . . . . . . . . . .


60
Eox =1.5MV/cm
40

20

0

-20
-20 I I I I I I I I I I I I I I I I I I I I I I I I I I I
90.5 91.0 91.5 92.0 92.5 93.0 93.5
NINJ/(1014 cm-2)


Figure 4.17


Shift in the saturation current of an n-channel BiMOST during
SHEi at Eox=1.5MV/cm enlarged in (b) for NINj<4 x1014, followed
by FNTEi from the poly-gate at Eox=8MV/cm, for 4 x10 and again by SHEi at Eox=1.5MV/cm for 9 x1015

1 2 3
NNJ /(1014 cm-2 )




















cd~


-10 E--ox = 8MV/cm



-15
0 25 50 75

NINJ /(1014 cm-2)


) (c)


2 ,


S Eox = 1.5MV/cm


0


-1 -


-2 I I l, I i t i, I
0 1 2 3

NINJ /(104 cm-2)


Figure 4.18


60-
Eox = 1.5MV/cm
40

20-

0

-20
m-zlOIiiII.I itaII 11111II 1111111


90.5 91.0 91.5


92.0 92.5 93.0 93.5


NINJ /(1014 cm-2)


Shift in the saturation current of an n-channel BiMOST during
SHEi at Eox=1.5MV/cm enlarged in (b) for NINj<4 x1014, followed
by FNTEi from the poly-gate at Eox=8MV/cm, for 4 x0O and again by SHEi at Eox=1.5MV/cm for 9 x1015 The value of ID,,at was extracted at a constant VD-sat=VGsat plus AVGT.


100








in ID-sat appears negligible if the value of VD=VG+AVGT is used to extract the current as

in Figure 4.18. This figure essentially illustrates AIDsat due to the degradation in

mobility. This is also evident in the plot of the mobility degradation in Figure 4.19.

The three hollow marker curves in this plot give lin extracted at at three constant

values of QINV. These curves support my assumption that the positively charged

oxygen vacancy, Vo, are filled with electrons during the low field SHEi to neutralize

the centers, decrease the Coulombic scattering, and increase the mobility, as I

anticipated in designing this set of experiments. On the other hand during the high

field FNTEi the electrons are impact emitted from the 7eV level leaving behind a

positively charged center. This in turn increases the Coulombic scattering and

decreases tin. The solid triangle curve in Figure 4.19 represents the saturation

mobility, sat, which appears to be less sensitive to charging and discharging of this

oxide trap (oxygen vacancy) as suggested by the difference between Figures 4.17 and

4.18. Thompson showed [56] that the centroid for this positive charge, V', is

approximately 80-90A from the injecting interface or at about central plane of the

170A oxide layer investigated here. Nevertheless sat does degrade slightly during the

long FNTEi impact emission cycle and does recover immediately following the start of

the second low field SHEi cycle. By isolating the initial portion of the high-field

FNTEi and plotting the extracted positive oxide charge density, +QoT = -(Cox/q)AVGT

against the degradation of in (at a constant QlNv=1.5x10-7C/cm2=9.4x10"q/cm2) an

essentially linear dependence on the oxide charge, QoT, is revealed (Fig. 4.19d).

Finally it is noted that the generation of interface states as measured by AS and

AIB was negligible during the SHEi portions of the stress (Figs. 4.20b and 4.20c).
































0 25 50 75


NINJ /(1014 cm-2)


90.5


1 2 3

NINJ /(1014 cm-2)


91.0 91.5 92.0 92.5 93.5 94.0

INJ /(1014 cm-2)


Figure 4.19


Percent degradation of the mobility of an n-channel BiMOST during
SHEi at Eox=1.5MV/cm enlarged in (b) for NINJ <4x1014, followed
by FNTEi from the poly-gate at Eox=8MV/cm, for 4 x10 < NINJ < 9 x1015
and again by SHEi at Eox=1.5MV/cm for 9 x1015 < NIN < 9 x1015 in (c).
The value of IDsat was extracted at a constant VDsat=VG-sat plus AVGT.


100


0



2

E3
3 Eox = 1.5MV/cm
-4


. I I I II .... . . . . .


-3 L








-100



-75



S-50



S-25


-1 -2 -3

%Agliin/ (cm2 V'1sec-')


Figure 4.19 d Effective electron mobility shift versus the impact-emission generated
+QOT, trapped in the gate oxide during the high-field FNTEi.


1.2

1.0 c
0
0.8

0.6 -

0.4 H

0.2

0








(a)

0









O
PQ


-I I I I I I I I I I I I I I I I I 0
0 25 50 75 100

NIN /(104 cm-2)

(c)
1 60 ) 3.0 -' ' I' ' I ' ' I I ''.

Eox = 1.5MV/cm -40 2.5 Eox = 1.5MV/cm
20 2.0



-40 1.0
-40 0.5
m

2 3 4
NN, /(1014 c-2)


Figure 4.20


(a) Subtheshold slope and base current degradation of n-channel BiMOST
during SHEi at Eox= 1.5MV/cm enlarged in (b) for NINJ < 4 xl014, followed
by FNTEi from the gate at Eox = 8MV/cm, for 4 x1014< NINJ < 9 xl015 ,and
again by SHEi at Eox=1.5MV/cm for 9 x1015< NmI < 9.4 xl015 enlarged in (c).


c-i




'I
H


NINJ /(1014 cm-2 )








However, some DIT are generated during the FNTEi portion of the stress.

Interestingly though the subthreshold slope recovers to within 10% of its original value

during the second SHEi stage whereas the shift in Ig remains constant. This is most

likely due to the fact that the subthreshold swing is sensitive to the areal nonuniformity

of the oxide traps from charging and discharging in addition to the stress-generated

interface traps, whereas the peak value of IB depends only on the change or increase of

the recombination rate from the increasing density of the interface traps. Hence the

fact that AS recovers and AIB does not indicates that trap charging and discharging are

nearly really uniform in these experiments. And the experiments demonstrate again

that AS is not as sensitive and unambiguous as AIB in monitoring the interface traps.



4.3 Charging and discharging the shallow oxygen vacancy center at Ec leV



Thompson [57] in his doctoral thesis also investigated the shallow level

associated with the oxygen vacancy located at Ec leV below the oxide conduction

band. Since electrons trapped at this level are easily thermally emitted or detrapped at

room temperatures the leV level was filled at 77K using low field SHEi stress. Then

the electrons were tunneled out of the trap to the oxide conduction band using the

isochronal electric field-stimulated emission (EFSE) technique. In this measurement

the oxide electric field is incrementally increased by the applied gate bias with the

source, drain, well, and substrate grounded for a predetermined amount of time. As

Eox increases, the trap to band tunneling probability increases until the trapped

electrons are emitted from the shallow traps. In this section the effects of charging and







discharging this shallow leV center on the mobility and saturation current will be

illustrated.

In this SAM experiment, as in the previous ones, it is essential that the IV and

CV characterization measurements are limited to a range of gate bias voltages lower

than that applied during the stress in order that the trapped electrons are not field

emitted from the shallow leV level during the measurement. This cannot be attained

at room temperature because of rapid thermal emission of trapped electrons to the

oxide conduction band from the shallow level. Therefore, in order to obtain an

adequately long VG sweep for extracting tlin while keeping the oxide electric field

sufficiently low (<1MV/cm), an n-channel BiMOST with a thick gate oxide was used

with Xox=290A and a circular geometry of W/L=16.8. After immersing the packaged

BiMOST into liquid nitrogen in the computer-controlled dewar, a 5MV/cm field is

applied across the oxide for 5 minutes to ensure that all the shallow leV levels are

empty. Next the BiMOST is biased for SHEi at a low gate oxide electric field of

1MV/cm. Since the injection efficiency is rather poor at such a low field the

collector/base junction reverse bias was set to 7V and the emitter/base junction was

biased at 3V initially.

Figure 4.21 plots the shift in the threshold voltage versus the injection/emission

time, since the gate current is negligible during the emission portion of the stress and

does not contribute significantly to NINJ. The emission time for each VG increment of

0.3V was approximately 10 seconds. In Figure 4.22 the emission portion of the stress

is plotted versus the increasing gate oxide field illustrating the VGT recovery as the

trapped electrons are emitted. In Figures 4.23 and 4.24 the shift in ID-sat is plotted for














S


0 200 400 600 800

Stress Time /( sec)















Figure 4.21 Threshold voltage shift of an n-channel BiMOST during SHEi
stress at a constant Eox=1MV/cm and VCB=7V, followed by
isochronal EFSE for t>400sec.


-.5
-I


-2







0







400



300


S


200



100


1 2 3 4 5


-2 e
S
o

-I
-1
0



0


Eox /(1MV/cm)














Figure 4.22 Threshold voltage shift of an n-channel BiMOST during isochronal
EFSE versus the gate oxide electric field Eox.












-25


CIO
d -50



-75



-100



















Figure 4.23


tstress /(1sec)


Shift in the saturation current of an n-channel BiMOST due
to SHEi stress at a constant Eox= IMV/cm and VcB=7V,
followed by the isochronal EFSE for t>400sec. The value of
ID-sat was extracted at a constant value of VD-sat = VG-sat.











-25


-50


-17 -7


0 200 400 600 800

tstress /(lsec)














Figure 4.24 Shift in the saturation current of an n-channel BiMOST due
to SHEi stress at a constant Eox= 1MV/cm and VCB=7V,
followed by the isochronal EFSE for t>400sec. The value of
ID-sat was extracted at a value of VD-sat = VG-sat adjusted by AVGT.








the constant VD=VG and the VD=VG+AVGT cases as before. Though the value of ID-sat

decreases largely due to the shift in VGT there appears to be a significantly larger

decrease in sat seen in the VGT-adjusted plot (Fig. 4.24). The degradation and recovery in

pjin and psat are shown in Figure 4.25 where ljn is plotted for three different values of

constant QJNV. The magnitude of ApIun is significantly smaller than that of Aisat. This

may be due to the fact that the VD-sat=VG-sat values for extracting ID-sat remain constant

during the stress even though there is a large shift in VGT as shown in Figure 4.21.

This would cause a significant change of the voltage drop and longitudinal electric

field in the drain junction space-charge region from the carrier depletion point in the

channel to the drain junction, which would alter the buildup rate of the oxide charge

and interface traps. Therefore, the range of current used in the two-parameter (VGT,

jsat) least-squares-fit to the Sah-Pao model is changed after each stress. For example, a

large positive VGT shift would have shifted the data closer to the subthreshold range

where the Sah-Pao bulk-charge model does not apply. Nevertheless both mobilities

decrease as expected with the increasing trapped electron charge in the oxide due to the

corresponding increase in Coulombic scattering. The mobilities also recover as

expected when the electrons are tunnel emitted out of the shallow traps leaving them in

the neutral charge state and decreasing the Coulombic scattering. Plotting the

degradation of the effective mobility during the initial low-field -QOT charging stage

versus the negative oxide charge density extracted from the AVGT, a linear dependence

on -QOT is observed as shown in Fig. 4.26. This is similar to that shown in Fig.4.19d

for the +QoT and provides a second experimental proof of electron mobility reduction


























0 200 400 600


-0









-15
-a




-15



-20
800


tstress /(1sec)


Figure 4.25


Percentage shift in the conductivity effective mobility, imn,
for varying values of Qiyv, and in the saturation effective
mobility, isat plotted versus time for an n-channel BiMOST
during SHEi stress at constant Eox=lMV/cm and VcB = 7V,
followed by the isochronal EFSE for t > 400sec.











ct1
-2.0 E
O




-1.0


-2 -4 -6 -8 -10


%A.in / (cm2 .V-


'sec-')


Figure 4.26


Shift of the effective conductivity electron mobility during the
low-field SHEi filling of the shallow electron traps in the gate
oxide versus the negative oxide charge density.


400


S


H


300



200



100









A AS @ ID = 10.0nA; S(prestress)=28mV/dec 80
o AS @ IDS= 5.00nA; S(prestress)=27mV/dec
15
-60
60-
10o
40 4

5
-20


o o
0 200 400 600 800
Stress Time/(lsec)













Figure 4.27 Shift in the subthreshold slope, S, of an n-channel BiMOST due to
the build-up of interface states and/or nonuniform charging during
SHEi stress at a constant Eox=1MV/cm.and VcB=7V, followed by
isochronal EFSE for t > 400sec.







from Coulomb scattering of the channel electrons by positive and negative charge

states of oxide traps at the same location in the oxide.

Finally the subthreshold swing and the corresponding calculated DIT are shown

in Figure 4.27. The recovery shows that AS is most likely due to areal nonuniformity

in the oxide charge as discussed previously rather than true interface state generation

and annealing since such a large number (10lI/cm2) of interface states would not be

expected during low, IMV/cm, SHEi stress, and in addition, there is not a viable

physical mechanism to anneal out the interface states. This is collaborated with the AIl

change during the low field SHEi shown in Fig. 4.20 which shows no changes during

the "annealing" cycle when AS reduces to zero while AIg remains high.

This data will be expanded upon in the following chapter to illustrate the

separation of interface states and areal charge nonuniformity.













CHAPTER 5
SEPARATION OF INTERFACE TRAPS AND AREAL
OXIDE CHARGE NONUNIFORMITY



The interface-trap caused distortion of the gate capacitance-voltage (Cg-VG or

CV) characteristics of the MOSC [10, Fig.403.1 on p.324] and the d.c. ID-VG (IV)

characteristics of the MOST in both the subthreshold and the inversion ranges [10,

section 628 on pp.653-662] are well documented in the literature. However it is also

well-known that an really nonuniform distribution of charged oxide traps (Qor) will

distort the CV and IV characteristics. In addition, the IV characteristic is also distorted

by the channel mobility variation with VG as discussed in chapter 2 and illustrated in

chapter 4. In the last chapter it was shown that the MOST subthreshold swing, AS, and

base current change, AIB, could be used to monitor the increase in interface traps but

that they could also be affected by really (y-direction) nonuniform trapped oxide

charge. In this chapter a rapid and highly sensitive electrical measurement technique is

proposed and demonstrated [59] which is designed to separate the effects on the CV

and IV characteristics from stress-induced areal nonuniform interface and oxide traps.

This new technique combines the DCIV and AS methods to analyze samples

stressed by uniform and nonuniform SHEi, SHEi+CHEi, and FNTEi to uniformly and

nonuniformly charge and discharge the oxide traps via impact emission, low field

thermal capture, and EFSE emission transitions discussed in chapter 4. For example, it







was suggested that the constant Ig (unchanged during the low field SHEi stress) and the

changing distortion of the subthreshold swing in Figure 4.20c implied the presence of

really inhomogeneous oxide charge generated during the 8MV/cm FNTEi stress

(Fig.4.20a). The design of experiments in this chapter is based solely on the

assumption that interface traps generated during the high field (FNTEi or SHEi/CHE)

or low field (SHEi) phase-1 will not be removed or annihilated during the EFSE

emission or the low field SHEi neutralization of QOT during phase-2. Therefore any

stress-generated AIB increase, due to ADIT, during phase-1 will be preserved during

phase-2, while the stress-generated really nonuniform AQOT in phase-1 will be

neutralized during phase-2. The results presented in this chapter demonstrate: 1) the

separation of the generated interface traps, ADIr. from the really nonuniform charging

and uniform neutralization of the oxide traps, AQoT, 2) that charging +QoT by high

field SHEi with VDS=0 is really uniform whereas 3) charging +QoT by FNTEi is

really nonuniform, and 4) that low field (<1MV/cm) -QoT charging at 77K is also

really nonuniform.



5.1 Nonuniform +QoT via FNTEi



One possible explanation to describe the nonuniformity of the FNTEi in

MOST's is that the oxide voltage drop (Vox) in the gate/source and gate/drain overlap

regions differs from that in the channel or well region because of the difference in

doping impurity concentrations, n+ in the source and drain, and p or p- in the channel

or well. It is pointed out (chapter 3 of [10,54]) that the difference between the gate bias







(VG) and the oxide voltage drop (Vox) is due to three factors: 1) the total potential drop

in the polysilicon gate, Vs-gate, and silicon substrate, VS-subs, 2) the gate/substrate work

function difference, Gcx, and 3) the charged oxide and interface traps:

VOX = VG + VS-gate + VS-subs + (GX

= VG + VS-gate + VS-subs + VFB 5.1

where DGX is equal to the flatband voltage (VFB) if QOT and QIT are negligible ('X'

denotes the silicon substrate, G the gate, and S the gate/oxide and oxide/substrate

interface position). For example, VFB for a sample with an n-poly-gate concentration

of NcG = 1x1020 phosphorus/cm3 and a p-well concentration of Pxx = 3x1016

boron/cm3 is VFB VFgate VFchanne = (kbT/q)log,(NGGPxx/ni) = 0.93V whereas

VFB in the gate overlap regions of the self-aligned n+ source/drain is VFB =

(kBT/q)loge(N,/NDD) = OV. In addition to the difference in Vg, the silicon surface

energy band bending in the p-well, Vswe or VSchannel, will be greater than that in the

n+source/drain regions, Vs-source and VS-drain because of the lower dopant impurity

concentration in the well and channel and higher dopant impurity concentration in the

drain and source, in addition to their opposite conductivity type. The total potential

drop in the silicon gate and substrate, VS-gat, VS-channel, VS-drain and V-source, has two

contributions: 1) the potential drop in the accumulation or inversion layer (Vs-acc or

Vs-inv) and 2) the potential drop in the surface space charge layer when biased into

inversion. The second component is zero in accumulation and twice the bulk potential

(2VF) in inversion. Hence, given a particular gate bias condition, VG, and neglecting

any potential drop in the highly doped polysilicon gate, the oxide voltage drop in the

region over the p-well and the source/drain overlap regions is








Vox-well = VG VFB Vs-well 5.2

VOX-source/drain = VG VFB VS-source/drain = VG 5.3

Therefore during the accumulation stress of an n-BiMOST by FNTEi from the poly-

gate (VG = -13.6V), the voltage drop in the oxide, Vox, will be higher at the edge of the

channel and in the source and drain overlap regions than in the the channel over the p-

well since IVFBl>>IVs-weIl or IVoxl = IVGI-IVFBI. The higher Vox in the source/drain

regions would then give rise to significantly higher Fowler-Nordheim tunneling

injection current passing through the edge and source-drain regions of the oxide due to

the exponential dependence of IG on Eox=Vox/Xo. Furthermore, the higher Vox near

the source and drain will result in increased +QoT generation in these regions since

more carriers will gain the required kinetic energy (>7eV) to impact emit the trapped

electrons at the oxygen vacancy sites. The results of this case were presented in

Figures 4.16-4.20. Figure 4.20c (phase-2) illustrated the recovery in AS but not %AIB

during the low field SHEi which neutralized the nonuniform +QoT.

Conversely, under the inversion stress (VG > 0 in nMOST) the surface in the p-

well region is inverted, and electrons in the silicon substrate will tunnel through the

gate oxide layer into the poly-Si gate. The negative flatband voltage over the p-well

would increase Vox by approximately 0.93V in the center of the channel over the p-

well compared to the source and drain edge regions. However, the flatband voltage is

now compensated by the potential drop in the p-silicon well or substrate to invert the

surface to n-type and create the n-channel. This potential drop is Vs-channel-inv = 2VF-well

so the total voltage difference between VG and Vox is rather small, 2VFchannel +

VS-channel-inv =0.







Thus, a FNTEi/SHEi stress-and-measure or SAM experiment was conducted

with positive VG applied polarity to the poly-gate (inversion) in order to tunnel

electrons from the silicon substrate into the oxide and to impact emit the trapped

electrons at the neutral nonbridging oxygen vacancy centers in order to buildup

positive oxide charge. The source, drain, well and emitter of the BiMOST were all

grounded with respect to the gate electrode which was set to VG = +13.6V to determine

if the really nonuniform positive oxide charge distribution could be produced during

the inversion FNTEi stress of this nBiMOSTs. Figure 5.1 a illustrates the negative gate

voltage shift, AVG, during the high field FNTEi portion of the stress and the

subsequent recovery (Fig. 5.1b) during the low field thermal electron capture (SHEi) to

neutralize the +QoT. Figure 5.1c illustrates the corresponding increase of the

subthreshold swing, AS, (measured at ID=5nA and VDs=100mV) and the percent shift

in the peak base current, %AIg (measured at VBE=0.5V) during phase-1. Figure 5.1d

illustrates a recovery, by -60%, in AS towards its original value while the %AlB due to

ADIT remains constant during the phase-2 low field SHEi which neutralized the +QoT.

This is essentially the same result obtained under accumulation FNTEi stress discussed

in the previous chapter (Figs. 4.16 and 4.20). The recovery of AS indicates that an

really nonuniform distribution of positive oxide charge was generated during the high

field FNTEi which was then neutralized during the low field SHEi. The corresponding

increase in Ig during the high field FNTEi without the subsequent recovery during the

lo\\ -field SHEi is an indication of the expected +QIT generated by high-field FNTEi

stress. These results are consistent with the theory and demonstrate the separation of

QIl and the really nonuniform +QoT.




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