PHYSICSBASED THERMAL IMPEDANCE MODELS FOR THE SIMULATION OF
SELFHEATING IN SEMICONDUCTOR DEVICES AND CIRCUITS
By
JONATHAN SCOTT BRODSKY
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
1997
This work is dedicated to my parents,
Lawrence and Jeraldine,
my brother Matthew and sister Alexandra.
ACKNOWLEDGEMENTS
First, I wish to express my deepest gratitude to my advisor Dr. Robert M.
Fox. His constant support and patient guidance provided a clear path for my research.
It is both a pleasure and a privilege to have worked with Dr. Fox. I thank Drs. Mark
E. Law and Jerry G. Fossum for extending their expertise and help to my unending
questions. I would also like to thank Drs. William R. Eisenstadt, John G. Harris and
ChenChi Hsu for their willingness to serve on my supervisory committee. I am also
very grateful to Mary Turner for all of her help throughout my graduate career.
I would like to acknowledge and thank the Semiconductor Research
Corporation (SRC) for the financial support that made this research possible. I am
also grateful to Dr. Surya Veeraraghavan for his guidance and friendship during my
internship at Motorola.
I would like to thank the "TCAD elders", and now my friends, Keith
Green, Dongwook Suh, PingChin Yeh, Haeseok Cho, ChihChuan Lin, MingChang
Liang and Scott Miller, for helping me get comfortable in my new surroundings and
setting the standard of excellence.
I am also grateful to my good friends/workmates/"happy hour buddies"
Srinath Krishnan, Samir Chaudhry, David Zweidinger, Omer Dokumaci, MingYeh
Chuang, Dukhyun Chang, Susan Earles, Hernan Rueda, Glenn Workman and Meng
Hsueh Chiang, for all of the enlightening discussions, the Friday lunch tradition and
the weekend adventures.
There is a very special group of individuals who have my admiration and
love for the friendships they have given me. I would like to thank my best friends
Douglas Weiser, Martin Weiss, Stephen Cea, Edward Cometz and Peter Lynch.
I can not completely express the role my family has played in my life and
in the completion of this dissertation. For simple words seem to diminish their
unconditional and unending love and support. I owe everything I have, everything I
have done and everything I am, to my family. I give my deepest love to my parents,
Jeraldine and Lawrence Brodsky, my brother Matthew and my sister Alexandra.
Finally, I am grateful to all of the wonderful friends that I met in
Gainesville for making this period of my life truly enjoyable.
TABLE OF CONTENTS
ACKNOWLEDGEMENTS .................................
. . . . . . . iii
ABSTRACT ........................................................ viii
1 INTRODUCTION ................................................ 1
1.1 SelfHeating Effects in Semiconductor Devices
1.1.1 Bipolar Transistors ..................
1.1.2 FieldEffect Transistors ..............
1.2 SelfHeating Effects in Semiconductor Circuits
1.2.1 SmallSignal Circuit Performance ......
1.2.2 LargeSignal Circuit Performance ......
1.3 SelfHeating Effects in Parameter Extraction ..
1.4 The Simulation of SelfHeating Effects .......
1.5 Thermal Equivalent Circuits. ...............
. . . . . . . . . . . .
......................3
......................6
. . . . . . . . . . . 8
. . . . . . . . . . . 8
..................... 11
. . . . . . . . . . . 12
. . . . . . . . . . . 13
1.6 The Need for PhysicsBased Thermal Impedance Models ..
1.7 O organization ............... ......................
. . . . . . 16
........ .. 20
........... 25
2 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR
JUNCTIONISOLATED BIPOLAR TRANSISTORS. .................... 27
2.1 Introduction .......................................
..........27
2.2 Derivation of the SingleEmitter BJT/HBT Thermal Impedance Model... 28
2.2.1 Modification for Finite Wafer Thickness ................... .. 39
2.2.2 Effects of Interconnect Metallization on the Thermal Impedance ... 43
2.2.3 A Model for the Thermal Impedance of the Emitter Interconnect... 49
2.2.4 Effects of Isolation Structures on the Thermal Impedance ......... 52
2.3 Verification of the SingleEmitter Thermal Impedance Model .......... 61
2.4 Derivation of the MultipleEmitter BJT/HBT Thermal Impedance Model. 66
2.5 Verification of the MultipleEmitter Thermal Impedance Model ........ 72
2.6 Summary................... ............................... 76
3 A CIRCUIT MODEL FOR THERMAL COUPLING AND A LUMPED
ELECTROTHERMAL MODEL FOR BULK MULTIPLEEMITTER BIPOLAR
TRANSISTORS ............... .............................. 77
3.1 Introduction ................................................77
3.2 A Circuit Model for Thermal Coupling ............................ 80
3.3 A Lumped Electrothermal Model for MultipleEmitter BJT/HBT's ...... 86
3.3.1 A Review of BaseCurrent Thermometry. ................... .. 90
3.3.2 Generation of the Lumped Electrothermal Model ............... 91
3.4 Verification of the Lumped Electrothermal Model ................... 96
3.5 Summary ............ ....... ....... ........................ 101
4 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR
VERTICAL BIPOLAR TRANSISTORS FABRICATED WITH FULL
DIELECTRIC ISOLATION ....................................... 103
4.1 Introduction ........................ ........... ....... .. 103
4.2 Derivation of the DIBJT Thermal Impedance Model ................ 106
4.2.1 Derivation of the BuriedOxide HeatTransfer Coefficient ....... 116
4.2.2 Derivation of the Trench HeatTransfer Coefficient ........... 120
4.2.3 Effects of Interconnect Metallization on the Thermal Impedance . 126
4.2.4 A Model for the Thermal Impedance of the Emitter Interconnect. 129
4.3 Verification of the DIBJT Thermal Impedance Model ............... 132
4.4 Derivation of a Compact DIBJT Thermal Resistance Model .......... 134
4.5 Verification of the DIBJT Thermal Resistance Model ............... 146
4.6 Summary................................................... 149
5 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR BULK
METALOXIDESEMICONDUCTOR FIELDEFFECT TRANSISTORS .. 150
5.1 Introduction ........................... ..................... 150
5.2 Derivation of the Bulk MOSFET Thermal Impedance Model .......... 153
5.2.1 The Linear Source Thermal Impedance ................... .. 161
5.2.2 The Saturated Source Thermal Impedance ................. .. 164
5.2.3 Effects of the Device Interconnects on the Thermal Impedance ... 165
5.2.4 Effects of Isolation Structures on the Thermal Impedance ........ 171
5.3 Verification of the Bulk MOSFET Thermal Impedance Model ........ 176
5.4 Summary.................. ............................... 182
6 A QUASITHREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR
SILICONONINSULATOR METALOXIDESEMICONDUCTOR FIELD
EFFECT TRANSISTORS ........................................ 184
6.1 Introduction ................... ........................... 184
6.2 Derivation of the SOI MOSFET Thermal Resistance Model .......... 187
6.3 Verification of the SOI MOSFET Thermal Resistance Model ......... 202
6.4 Derivation of the SOI MOSFET Thermal Impedance Model .......... 204
6.5 Verification of the SOI MOSFET Thermal Impedance Model ......... 212
6.6 Summary................................................ 216
7 THE THERMAL IMPEDANCE PREPROCESSOR: TIPP .............. 219
7.1 Introduction ............................................... 219
7.2 A Description of TIPP ........................................ 220
7.3 Generation of Thermal Equivalent Circuits ........................ 225
7.3.1 Approximation of the Thermal Equivalent Poles/Time Constants. 226
7.3.2 Calculation of the Thermal Equivalent Components ............ 230
7.4 The Interface Between TIPP and Circuit Simulators ................. 232
7.5 Summary................................................... 234
8 CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK... 238
8.1 Conclusions ............................................... 238
8.2 Recommendations for Future Work. .......................... 240
8.2.1 The Temperature Dependence of the Thermal Conductivity ...... 240
8.2.2 Models for Thermal Effects Due to Advanced Isolation ......... 242
8.2.3 A Model for Thermal Coupling in SOI MOSFET Circuits ....... 243
REFERENCES ....................................................... 247
BIOGRAPHICAL SKETCH .......................................... . 257
Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy
PHYSICSBASED THERMAL IMPEDANCE MODELS FOR THE SIMULATION OF
SELFHEATING IN SEMICONDUCTOR DEVICES AND CIRCUITS
By
Jonathan Scott Brodsky
August 1997
Chairman: Robert M. Fox
Major Department: Electrical and Computer Engineering
Inherent in the operation of semiconductor devices is selfheating, an
increase in operating temperature due to a device's own power dissipation. The
magnitude of the selfheating effect can be quantified by the value of the thermal
impedance, which describes the dynamic response of the device temperature to
variations in device power. The thermal impedance is determined primarily by
material properties and device structure. The implication of the selfheating effect is
that the change in temperature can alter the operating characteristics of a device,
which in turn, can affect circuit performance.
The primary focus of this dissertation is the development of physicsbased
models for the thermal impedances of semiconductor devices. Models for the thermal
impedances of bipolar and fieldeffect transistors, on both bulk and siliconon
insulator (SOI) substrates, are presented. All of the thermal impedance models were
derived from the timedependent heat conduction equation, resulting in compact
analytic expressions for the thermal impedances. The physical nature of the thermal
impedance models allows them to scale with the device structure and material
properties, and they successfully reproduce results from both measurements and
threedimensional finiteelement simulations. A circuit model for thermal coupling
between transistors in a common substrate is also presented. The coupling model was
used in conjunction with the bulk bipolar thermal impedance model to extract a
lumped electrothermal model for multipleemitter bipolar transistors.
The secondary objective of this work is the provision of an approach for
incorporating these models into circuit simulators. It has been shown that the thermal
impedance models can be represented by thermal equivalent circuits made up of
resistors and capacitors, making them suitable for efficient circuit simulation. The
computer program TIPP (Thermal Impedance PreProcessor) is introduced. TIPP
was developed to provide circuit simulators with convenient algorithms for
generating thermal equivalent circuits. TIPP can calculate the component values for
thermal equivalent circuits from either physical models or measured data, and is
easily modified to interface with different circuit simulators.
CHAPTER I
INTRODUCTION
1.1 SelfHeating Effects in Semiconductor Devices
The physical properties of the materials used to fabricate semiconductor
transistors depend on temperature. Therefore, the operating characteristics of a
transistor (e.g. electrical currents and potentials), which are determined by the
material properties, are also temperature dependent. The temperature at which a
transistor operates is determined by the temperature of the surrounding environment
(referred to as the "local ambient temperature") and the power dissipated in the
device (referred to as the "selfheating effect"). Therefore, the timedependent
temperature of a transistor can be expressed as
t
T(t) = Tamb + P(t')hTH(tt')dt', (1.1)
0
where hTH is the thermal impulse response and P is the instantaneous power. The
second term on the righthand side of (1.1) represents the temperature rise in the
device
AT(t) = P hTH, (1.2)
where 0 is the convolution operator. The temperature rise can also be expressed in
the frequency domain as
AT(t) =  [ZTH(S) P(s)], (1.3)
where 1 represents the inverse Laplace transform and ZTH(s) is the thermal
impedance. The thermal impedance of a transistor describes the dynamic response of
the device temperature to variations in device power, and is determined primarily by
the material properties and the structure of the device. The transient thermal
impedance can be defined as
ZTH(t) = 1 ZTH(s), (1.4)
which represents the normalized thermal step response.
Since the power dissipation in (1.1) is determined by the operating
characteristics of a transistor, it depends on temperature such that
P = P(T) = Idev(T) Vdev(T), (1.5)
where Idev(T) and Vdev(T) represent general currents and potentials within a given
device, respectively. Consequently, there is feedback between the thermal and
electrical operation of the device. Whereas the transistor temperature is usually
assumed to be constant, the electrothermal coupling implied by (1.1) and (1.5) shows
that the temperature actually varies with the device operation. Thus, to fully
characterize the operation of semiconductor transistors, both the electrical and
thermal behavior should be determined.
1.1.1 Bipolar Transistors
In the forwardactive mode, the operating characteristics of bipolar
junction and heterojunction transistors (BJT's and HBT's) are controlled by the
injection and diffusion of minority carriers in the base region. For an npn transistor,
electrons are injected across the forwardbiased base/emitter junction, causing an
exponential increase in the minority carriers in the base. The electrons diffuse across
the base and are swept into the collector by the reversedbiased base/collector
junction. For a fixed base/emitter voltage, assuming negligible recombination in the
quasineutral base, the collector current can be expressed as
2 qVBE'
Ic(T) ni (T) exp EkT (1.6)
where ni is the intrinsic carrier concentration, q is the electron charge, k is
Boltzman's constant and T is temperature. The overall temperature dependence of
(1.6) is dominated by the relation between the intrinsic carrier concentration and
temperature, given by
2 "Eg
n (T) = N. N, exp.. ) (1.7)
where Eg is the semiconductor bandgap energy and Nc and Nv are the effective
density of states in the conduction and valence bands, respectively. The junction
voltage is always less than the bandgap and therefore, an increase in temperature
causes an exponential increase of minority carriers in the base, resulting in an
increase in collector current. Since the collector current is a significant component
of the power dissipation in a BJT, selfheating results in a regenerative feedback
between the collector current and the temperature of the device. This positive
feedback can lead to the destructive phenomenon of thermal runaway in BJT's
[Shu90].
For fixed base current, the collector current can be expressed as
Ic(T) = P(T) IB, (1.8)
where P(T) is the commonemitter current gain. For moderate injection levels, the
current gain can be approximated by the ratio of the electrons injected into the base
to the holes backinjected from the base to the emitter. This ratio, and hence p(T),
are typically high since the emitter usually has a higher doping level than the base.
Due to heavydoping effects in the emitter, the emitter bandgap is typically less than
that in the base so that
P(Y) NDE AEgN
(T) NB expAE ), (1.9)
NAB V k!T
where AEg is the bandgap difference between the emitter and base, and NDE and
NAB are the doping concentrations in the emitter and base, respectively. As shown
by (1.9), the current gain is greater at higher temperatures; consequently, the
collector current is, again, an increasing function of temperature. The rate of increase
with temperature in this case, however, is not as significant as that for a device biased
with a fixed base voltage. Therefore, the selfheating effect is not as substantial in
BJT's driven by a fixed base current.
HBT's are bipolar devices that use bandgap engineering in either the
emitter or base region to improve the current gain over homojunction BJT's. The
resulting bandgap in the emitter is wider than that in the base, so that the potential
barrier induced by the bandgap discontinuity effectively impedes the injection of
carriers from the base to the emitter. When biased with a fixed base voltage, the
temperature dependence of an HBT is similar to that of a standard BJT. However,
when an HBT is driven with a fixed base current, the temperature dependence of the
collector current is quite different than that of a BJT. While the collector current in
this case can still be determined from (1.8), the commonemitter current gain is now
expressed as
NDE (AEg'
P1(T) exp (1.10)
NAB kT
As a result of the bandgap being wider in the emitter than in the base, the sign of the
exponential argument is now positive. Therefore, as opposed to a standard BJT, the
current gain and the collector current decrease with increasing temperature. As a
result, selfheating in HBT's can lead to the noncatastrophic failure mechanism
known as current collapse [Sei93].
To reduce the effects of parasitic resistances and currentcrowding, large
bipolar devices are commonly fabricated using multiple devices connected in parallel
[Shu90]. Multipleemitter devices, both BJT's and HBT's, are capable of operating
at high frequencies under high power densities [Win67, Mar93, Liu95b]. However,
multipleemitter devices suffer from more complex selfheating effects due to the
thermal interactions among neighboring devices. The thermal coupling leads to
lateral temperature gradients across the device, resulting in the inner emitters
operating at higher temperatures. Due to the positive feedback between junction
temperature and junction current, the inner devices carry more current than those at
the outer extremes. As the current density in the inner emitters increases, the self
heating effect in these devices accelerates. The premature activation of thermal
runaway in BJT's and current collapse in HBT's is attributed to this thermal
instability inherent in multipleemitter devices [Win67, Liu93, Kag94, Lio94,
Lio96].
1.1.2 FieldEffect Transistors
For MetalOxideSemiconductor FieldEffect Transistors (MOSFET's)
operating in strong inversion, the current characteristics are determined by the drift
current of carriers in the inverted channel region. For small drain voltages, a
MOSFET operates in the linear region where the carrier velocity depends on the
longitudinal electric field in the channel. In the linear region, the drain current can
be approximated as
ID(T) oc (T). VGs Vt(T) DS, (.1)
where 1p(T) is the carrier mobility, Vt(T) is the threshold voltage, and VGS and VDS
are the applied voltages between the gate and source and drain and source,
respectively. At higher drain voltages, the electric field at the drain end of the
channel is large enough to cause the carrier velocity to saturate. In the saturation
region, the drain current can be expressed as
ID(T) Qc(VGs, VDS, st(T)) vsat(T), (1.12)
where Qc is the channel charge and vsat(T) is the saturated carrier velocity.
The overall temperature dependence of (1.11) and (1.12) are dominated
by the sensitivity of the carrier mobility to changes in temperature. Due to increased
lattice scattering at higher temperatures, mobility decreases as temperature increases.
The reduction in mobility leads to a decrease in drain current, which implies that the
drain current of a MOSFET is a decreasing function of temperature. At high power
dissipation levels, the selfheating effect can cause the drain current to drop below
the ambient temperature value. In such cases, the output conductance becomes
negative, and the device exhibits a negative dynamic resistance (NDR) [Sha83].
MOSFET's fabricated on silicononinsulator (SOI) substrates have
temperature dependence that are similar to those of their bulk counterparts, though
the effects of selfheating can be enhanced due to the low thermal conductivity of the
insulating layers. For nonfully depleted (NFD) SOI MOSFET's, however, floating
body effects further complicate the thermal effects [Wor97]. Impactionization
induced floatingbody effects are known to cause the kink, or increase in drain
current, in NFD SOI MOSFET's. The kink is affected by selfheating in two ways.
First, at elevated temperatures, the onset of the impactionization is retarded.
Second, an increase in recombination in the quasineutral body reduces the
thresholdvoltage shift caused by the impactionization. Therefore, in addition to a
reduction in drain current due to mobility effects, selfheating also reduces the
current in NFD SOI MOSFET's through temperaturedependent floatingbody
effects.
1.2 SelfHeating Effects in Semiconductor Circuits
Since the operating characteristics of transistors are affected by
temperature, the integrated circuits that depend on these transistors will also be
affected by changes in temperature. In modern digital circuits, the high switching
speeds of the transistors, the relatively slow time constants associated with the
temperature response and the low static power dissipation, all help reduce the
instantaneous temperature rise. Consequently, selfheating effects are typically
negligible in digital circuits. On the other hand, analog circuit applications
commonly have significant power dissipation and can operate at frequencies which
are comparable to the thermal timeconstants. Therefore, analog circuits are
generally more prone to selfheating effects.
1.2.1 SmallSignal Circuit Performance
The effect of selfheating on smallsignal BJT characteristics was derived
by Mueller and investigated in bipolar circuits by Fox et al. [Mue64, Fox93b]. The
twoport smallsignal admittance parameters, in the presence of selfheating, were
shown to be
YmnE + DmZTHImIn (1.13)
mn 1 DmZTHP
where ymnE are the admittance parameters neglecting selfheating, and Dm
represents the variation of the current Im with temperature. The denominator of
(1.13) establishes the sensitivity of the admittance parameters to power, and has a
significant impact as DmZTHP approaches unity. The effect of the denominator
generally becomes important only at high power dissipation. However, as the thermal
impedance increases (i.e. due to device scaling), the power level that defines the
threshold for selfheating effects will decrease. The second term in the numerator of
(1.13) shows that the effect of selfheating on the admittance parameters is also
proportional to the operating currents. For yll and y21 the selfheating term in the
numerator is small so that yll =YlE and y21 =Y21E. However, the effect of self
heating can be substantial in the numerators of yl2 and y22, even at moderate current
levels. The thermal effects on these parameters can result in a coupling between the
collector output admittance and the impedance of the basedriving source. Also, as
shown in Figure 1.1, there can be a significant reduction in the voltage gain of BJT
amplifiers.
The smallsignal performance of analog MOSFET circuits can also be
affected by selfheating. For moderate power levels, the thermal effects are similar
to those in bipolar circuits. However, as mentioned previously, the drain current of a
MOSFET decreases with increasing temperature, and significant selfheating can
induce NDR. The effect of a negative output conductance can be investigated by
examining the voltage gain of a MOSFET amplifier. As shown by Fox and Brodsky
[Fox93a], if the devices in the amplifier enter a region of negative output
conductance, the gain of the amplifier changes polarity. For an inverting amplifier,
102 104 106 108
Frequency, (Hz)
1010
The effect of selfheating on the smallsignal gain of a BJT differential
amplifier. The data was simulated using a version of SPICE, which was
modified to account for dynamic variations in temperature [Zwe97],
and the thermal impedance model for bipolar transistors presented in
Chapter Two.
300
200
100
0
Figure 1.1
selfheating effects can therefore cause the gain to become noninverting, resulting
in hysteresis in the amplifier's output characteristics.
1.2.2 LargeSignal Circuit Performance
The effects of selfheating on the largesignal operation of analog bipolar
circuits was investigated by Fox et al. [Fox93b]. The types of circuits that are
sensitive to thermal effects are typically those that depend on the precise control of
BJT characteristics. For example, the mismatch in the reference and output currents
of a current mirror can be increased due to selfheatinginduced differences in the
operating conditions of the transistors. Translinear circuits and bandgap voltage
references can also be affected by selfheating due to their strong dependence on the
thermal voltage. Thus, neglecting selfheating can result in significant discrepancies
between the ideal and actual operation of these types of circuits. The largesignal
transient operation of analog circuits is also affected by selfheating. The long time
constants of the thermal characteristics can effectively slow down the electrical
response of a circuit. Fox et al. showed that the fivepercent settling time of a Gilbert
multiplier increased by over an order of magnitude due to selfheating [Fox93b].
While the errors caused by selfheating can be reduced by careful circuit design, they
can not be completely eliminated.
1.3 SelfHeating Effects in Parameter Extraction
The extractions necessary to determine the behavioral characteristics of a
semiconductor transistor are often performed at bias levels that cause moderate to
highpower dissipation. Typically, the parameters that are extracted are assumed to
correspond to the ambient temperature at which the measurements are carried out.
However, at significant power levels, selfheating will cause a temperature rise in the
device. Neglecting the temperature rise that can occur during the measurements can
lead to erroneous results [Zwe97]. For example, the Early voltage, VA, of a BJT is
commonly extracted from the slope of the IC VCE characteristics in the linear region
of operation. If selfheating is significant, the slope of the output curves depends on
the source that is driving the base [Fox93b]. Therefore, the exact meaning of the
value extracted for VA would be ambiguous unless the thermal effects were taken
into account.
Various methods have been proposed for removing the effects of self
heating from parameter extraction. One approach augments a standard extraction
routine with measurements designed to determine the thermal characteristics of the
device. The full set of parameters can then be input to a global optimization routine
to generate electricalonly parameters that are independent of selfheating [Zwe97].
Other techniques attempt to directly remove the effects of selfheating from the
parameter extraction measurements by making the temperature rise in the given
device negligible. The temperature rise can be minimized by performing the
extractions in lowpower regions, or by using complex highspeed measurements
[Tu94, Jen95]. Since the device is not allowed to heat, the resulting device parameter
set would be approximately devoid of selfheating effects, and would essentially
correspond to the given device operating under isothermal conditions. Consequently,
the resulting electrical parameters would only pertain to device operation for low
power or highspeed circuit applications, and would not convey the proper device
characteristics for applications that experience substantial selfheating effects. Thus,
for a set of electricalonly parameters to correctly represent the characteristics of a
device, over a wide range of operating conditions and biases, it should be augmented
by additional parameters that describe the thermal attributes of the device.
1.4 The Simulation of SelfHeating Effects
As shown in the previous sections, the operating characteristics of both
individual transistors and circuits depend on temperature. Due to selfheating, the
effective operating temperature depends on power dissipation and can therefore vary
under different operating conditions.
By solving the timedependent heat conduction equation and energy
balance equations for electrons and holes, numerical device simulators can model
phenomena associated with dynamic selfheating in individual transistors [Lia94].
While this approach is invaluable for examining the detailed physics that govern the
operation of semiconductor devices, it is impractical for simulating all but the
simplest of circuits. Therefore, to investigate the effects of dynamic selfheating on
a broad range of circuits, a more efficient simulation approach is necessary.
The standard version of most circuit simulators such as Berkeley SPICE
[Nag75] and HSPICE [Hsp92], treat temperature as a static global parameter. This
has two significant implications. All of the semiconductor devices in a simulation
operate at the same temperature, and that temperature remains constant throughout
the simulation. Due to these constraints, a circuit simulator may not accurately
represent the physical operation of a circuit, where spatial and temporal variations of
the temperature can cause each device to operate at its own local temperature. To
account for the temperature dependence of a circuit's operation, circuit simulators
should be capable of independently tracking the dynamic temperature of each device
in the circuit.
A common approach for creating an electrothermal circuit simulator
(ETCS) uses the concept of the thermal impedance and the analogy between
electrodynamics and heat flow to account for dynamic temperature variations. This
approach allows temperature to be represented as an electrical potential and power
as an electrical current [Lee96, Zwe97]; therefore, the local operating temperature of
a device can be thought of as simply another "bias" condition. To facilitate the
temperature "bias" condition, an external node is added to a given compact device
model [McA92, Fos95, Lee96, Zwe97]; such a configuration is shown in Figure 1.2.
Attached to this node, internal to the device model, is a controlled current source that
represents the instantaneous power dissipation. The parameter set for the device
model should be modified to include the correct temperature dependence. When the
modified device model is used for a circuit simulation, a thermal impedance (and, in
some case, a voltage source to represent the reference ambient temperature) can be
T0p(t)
p(t)
I
Tamb
A generalized schematic showing a common method for modifying a
compact device model to include temperature as a variable. The dashed
box outlines the new model with the added temperature node; DEVICE
represents the original electricalonly model.
IL
I
Figure 1.2
____
attached to the new external node. Therefore, the voltage generated at this additional
node represents the local temperature of the device. The electricalonly device model
is first solved at the ambient temperature; this solution results in an initial guess for
the device power dissipation. This power is then used to calculate the temperature
rise in the device. Once the approximate local operating temperature is calculated, it
is used to update the temperaturedependent model parameters, which are used to
recalculate the electrical bias potentials and currents of the device model. This
procedure is repeated until selfconsistent solutions for the temperature and electrical
biases are reached. Thus, an effective operating temperature can be independently
calculated for each device in a simulation, and that temperature can now vary with
the operating point.
1.5 Thermal Equivalent Circuits
The data that quantify the thermal impedance of a transistor are typically
in the form of discrete data points for the temperature rise, normalized to a unitstep
increase in power dissipation, versus time or frequency. In such a format, the thermal
impedance data are not readily accessible by an ETCS. While data in a tabular format
can be used without much complexity for DC and AC simulations, an inefficient
convolution computation would be required to use the data for transient simulations.
Therefore, a representation for the thermal impedance is needed that both accurately
models the physical data and can be easily incorporated into an ETCS for efficient
DC, AC and transient simulations.
In an ETCS, when a current representing the power dissipation in a
transistor is applied to the thermal impedance, ZTH, the resulting voltage represents
the temperature rise in that transistor. By invoking the analogy between
electrodynamics and heat flow, the thermal impedance can be represented as an
electrical impedance. Common representations for the electrical impedance circuits
are shown in Figure 1.3. The resistances and capacitances that comprise the
impedance effectively represent the lumped threedimensional thermal resistance
and heat capacity of the semiconductor device structure. Therefore, the overall
electrical network can be referred to as a thermal equivalent circuit. The values for
the individual elements of a thermal equivalent circuit can easily be determined by
numerically fitting the circuit to existing thermal impedance data. Thermal
equivalent circuits are directly applicable for DC and AC electrothermal simulations
since, in such cases, the voltage drop across the network is simply equal to the
product of the current and the network resistance or impedance. In addition, such
networks inherently provide an efficient method for effecting the necessary transient
convolution.
As will be shown in the subsequent chapters of this dissertation, the
fundamental nature of heat flow is that of a distributed system. The dynamic
temperature rise in a device due to selfheating can occur over three or more decades
of time or frequency. A single time constant associated with a simple exponential
function can not represent the distributed behavior of selfheating. Consequently, the
network response of the singlepole thermal equivalent circuits which have been
proposed in previous works [McA92, Bau93, Lee93, Tu94], will not accurately
rth2
Cthl Cth2 Cth3
I I
(a)
rthl rth2 rth3
" I ......
I I IAA
Cthl
Cth2
Cth3
Thermal equivalent circuits used to represent a thermal impedance for
circuit simulation: a) Cauer network representation; b) Foster network
representation.
Figure 1.3
rthl
rth3
model the dynamic thermal impedance. Thermal equivalent circuits consisting of
cascaded resistor/capacitor stages, as exemplified in Figure 1.3, effectively provide
a distributed network response, and therefore allow a more accurate representation
of a dynamic thermal impedance [Bro93].
In the work by Szekely and Van Bien [Sze88], the Foster circuit
(Figure 1.3b) was shown to be an invalid representation of a discretized thermal
network. This point is valid in the context of numerical simulations (e.g. finite
difference or finite element) where the transistor structure is modeled by a
distributed thermal network. In that case, the nodetonode capacitances of the Foster
network do not have physical meaning and the Cauer network would be the proper
physical discretization of the given thermal domain. However, in this dissertation,
the thermal equivalent circuit is simply a numerical representation of a thermal
impedance, and the validity of its format is moot. Yet, for the purpose of representing
a lumped thermal impedance in an ETCS, the Foster network form offers an
important advantage over the Cauer form: the time constants associated with a given
Foster network are independent of any surrounding circuit elements. This
characteristic is beneficial when individual thermal equivalent circuits must be
connected to model different components of a transistor structure or the thermal
interactions between transistors. Therefore, the Foster network form will be assumed
for any thermal equivalent circuits within this dissertation.
1.6 The Need for PhysicsBased Thermal Impedance Models
In the previous two sections, the concept of the thermal impedance is
adopted to model the temperature rise in a transistor as a function of that device's
power dissipation. For the purpose of circuit simulation, the thermal impedance can
be represented by a network of resistances and capacitances that effectively represent
the lumped thermal characteristics of a transistor. To successfully synthesize a
thermal equivalent circuit, tangible data for the thermal impedance are necessary.
One approach to obtain the thermal impedance of a transistor is to extract
it from measurements [Lee95, Zwe96]. While this empirical approach provides
accurate temperature information, such measurements are somewhat difficult, for
several reasons. To begin with, thermal measurements are very timeconsuming. The
extraction procedure is generally divided into two steps, the first of which dominates
the total measurement time. This step is required to calibrate the relation between the
temperature and the physical characteristic that is being used to monitor the
temperature (e.g. the base current and drain current in bipolar and fieldeffect
transistors, respectively). The calibration is performed at multiple ambient
temperatures at DC and is thus limited by the long time constants associated with
steadystate heat flow. To make such thermal measurements requires special
measurement equipment such as a thermal wafer chuck or oven to accurately control
the temperature of the devices being measured. Finally, the results of any such
extraction are limited to the specific device being measured. Thus, the entire
procedure would have to be repeated for each transistor structure and transistor type
of interest.
Another approach, which avoids the inherent complexities of thermal
measurements, is to derive the thermal impedance of a transistor from the physical
equations that govern the temperature and heat flow in the device. Physical thermal
modeling is desirable because it can give the temperature behavior as a function of
the device structure and material properties alone; therefore, the effects of device
technology scaling on the thermal impedance can be predicted. The requirements of
accurate physical modeling (e.g. multidimensional numerical simulations) tend to
conflict with the needs for simplicity and efficiency in circuit simulation. However,
a thermal impedance model does not need to be absolutely accurate to provide
reasonable results within an ETCS. Therefore, by using certain heuristic
assumptions, compact physical models for the thermal impedance, suitable for
efficient simulation, can be derived. It is important, though, that the correlation
between the accuracy of the thermal impedance models and the accuracy of the
simulated electrical characteristics of a semiconductor device in the presence of self
heating be understood.
The sensitivity of a given electrical parameter, X, of a semiconductor
device to the thermal resistance can be defined as
RTH RTH aX
sx X T (1.14)
X X .RTH
As an example, since the output current of a device is very important for
characterizing performance, (1.14) can be used to determine the sensitivity of the
collector and drain currents of BJT's and MOSFET's, respectively. Using (1.1) in the
steadystate limit and (1.6) with (1.14), the sensitivity of the collector current of a
BJT is expressed as
RTH q. (Vg VBE) .RTH P
S (1.15)
c k (RTH P + T)2
where Vg is the semiconductor bandgap voltage. A similar expression for the
sensitivity of the drain current of a MOSFET can be determined using the current
equation given by Fox and Brodsky [Fox93a], which results in
SRT RTH. p P RTH. p
SI= a + 1 (1.16)
1 To To
where a is typically between 1.5 and 1.8 (assuming that the temperature dependence
of the drain current is dominated by the temperature sensitivity of the carrier
mobility). The expected level of error in simulated output currents can be
approximated by the product of the sensitivity and the anticipated error in the thermal
impedance model. Therefore, as shown by (1.15) and (1.16), the relation between the
accuracy of the thermal impedance models and the accuracy of the calculated
electrical parameters depends on the power dissipation and the sensitivity of the
electrical parameters to temperature. Consequently, the level of accuracy of a
thermal impedance model is more critical for devices with electrical characteristics
that are highly sensitive to temperature (e.g. BJT's as opposed to MOSFET's). At
low power dissipation levels, where the temperature rise is small compared to the
ambient temperature, the error in the thermal impedance model will not directly
correspond to the error in the calculated operating temperature. For a temperature
rise of twenty degrees, the sensitivities of the BJT collector current (VBE = 0.8) and
MOSFET drain current are 0.7 and 0.1, respectively. In such a case, the error in the
electrical characteristics will tend to be lower than the error in the thermal
impedance. Whereas at large power dissipation levels, the temperature rise can be
much larger than the ambient temperature, and the error in the thermal impedance
model will directly correspond to the error in the calculated operating temperature
(for a temperature rise of onehundred degrees, the respective BJT and MOSFET
current sensitivities are 2 and 0.4); in which case, large errors in the calculated
electrical characteristics can result. Figure 1.4 shows an example of BJT
characteristics simulated assuming a 20% error in the thermal resistance model; the
simulations were performed using the modified version of SPICE created by Lee
[Lee96]. The data clearly shows that for larger temperature rises, the error in the
calculated current (due to errors in the thermal impedance model) increases.
The motivation behind this dissertation is the development of compact
thermal impedance models for semiconductor transistors. These models can provide
a reasonably accurate representation of the dynamic temperature response within a
device; more importantly, since the models depend mainly on the physical structure
of a device, they can correctly anticipate the effects of technology scaling on the
thermal behavior. Physicsbased thermal impedance models allow an ETCS to
predict dynamic selfheating effects in circuits and can also provide more accurate
electrical parameter extraction. In addition, when the thermal impedance models are
coupled with physicsbased compact device models, the combination provides an
efficient tool for studying selfheating in semiconductor transistors.
40
S30
S20
o
U 10 
0
0Figure 1.4
Figure 1.4
1 2 3 4 5
CollectorEmitter Voltage, VCE (V)
Simulated output characteristics of a BJT, assuming that
RTH = 1000 C/W, for VBE = 0.80, 0.85, 0.90 and 0.95 V. The
simulations are repeated assuming a 20% error in the thermal
resistance model, so that RTH = 800 oC/W.
1.7 Organization
Chapter Two presents a physicsbased model for the thermal impedance of
bulk junctionisolated bipolar transistors. The model is derived by solving the three
dimensional timedependent heat conduction equation in the substrate. The ability of
the model to represent bulk BJT/HBT's with either LOCOS or trench isolation is
investigated. To account for multipleemitter bipolar transistors, the thermal
impedance model is extended to represent multiple heat sources. The accuracy of the
model is evaluated using measurements and threedimensional finiteelement
simulations.
Chapter Three describes a circuit network for modeling thermal
interactions between devices located in the same substrate. The network is developed
for the specific application of multipleemitter bipolar devices, but is shown to be
valid for general crosssubstrate thermal coupling in circuits. A method for
improving the simulation efficiency of a multipleemitter BJT/HBT electrothermal
model, using a lumped thermal impedance model, is presented. The validity of the
lumped modeling approach is supported with comparisons to the full electrothermal
model.
Chapter Four presents a predictive scalable model for the thermal
impedance of BJT's with full dielectric isolation. The model is derived by solving
the threedimensional timedependent heat conduction equation in the substrate
accounting for the buried oxide and trench isolation. In the limit of steadystate heat
conduction, the thermal impedance model is simplified, resulting in a closedform
model of the thermal resistance. The accuracy of both models is evaluated using
threedimensional finiteelement simulations and measurements.
Chapter Five describes a physicsbased model for the thermal impedance
of bulk MOSFET's. The model is derived by solving the threedimensional time
dependent heat conduction equation in the substrate. The effects of the device
interconnects and isolation structures, such as LOCOS and trenches, on the thermal
impedance are investigated. The accuracy of the model is evaluated using
measurements and threedimensional finiteelement simulations.
Chapter Six presents a predictive scalable model for the thermal
impedance of SOI MOSFET's. The model is initially derived for steadystate heat
conduction by coupling separate onedimensional heat conduction analyses in the
silicon film and interconnects. The derivation is then carried out for the case of time
dependent heat conduction, resulting in a model for the dynamic thermal impedance.
The accuracy of both models is evaluated using threedimensional finiteelement
simulations and measurements.
Chapter Seven describes a computer program developed to facilitate
thermal modeling in circuit simulation. The program, referred to as the Thermal
Impedance PreProcessor (TIPP), functions as a framework for obtaining the
component values of thermal equivalent circuits from the thermal impedance models
presented in Chapters Two through Six.
Chapter Eight concludes the dissertation with a summary of the
accomplishments of this work and suggestions for future modeling efforts.
CHAPTER 2
A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR JUNCTION
ISOLATED BIPOLAR TRANSISTORS
2.1 Introduction
The models derived in this chapter provide closedform physical solutions
for predicting the thermal impedances for single and multipleemitter bipolar
junction (BJT) and heterojunction bipolar (HBT) transistors, based solely on device
geometry and material properties. These models can predict both steadystate and
dynamic selfheating due to the semiconductor substrate. Previous works in this area
provided values for the thermal impedance of BJT's or HBT's, but were either
limited by assumptions or relied on nonpredictive measurement techniques. For
example, the thermal impedance model derived by Fox and Lee [Fox91a] is limited
to singleemitter devices. The analyses in other works only provide models for the
steadystate thermal resistance [Lio93, Bau94, Daw94, Lio94, Lio96]. Some authors
have used measurement techniques to extract either the steadystate thermal
resistance or simple onepole approximations for the thermal impedance [Bau93,
Liu93, Daw94, Liu95a, Liu95b]; in either case, the results do not provide a complete
picture of selfheating and are not predictive.
The thermal analysis by Joy and Schlig [Joy70] serves as the foundation
for deriving of thermal impedance model, and the first part of this chapter re
examines this work to provide a clear background for modifications made to the
model later in the chapter. The thermal impedance model developed by Joy and
Schlig was derived for singleemitter, junctionisolated BJT's operating in the
forwardactive region. A diagram of a typical junctionisolated npn BJT is shown in
Figure 2.1. In this chapter, the basic model is modified to account for variations in
substrate thickness. The effects of interconnect metallization and different isolation
technologies on the thermal impedance, and thus on the performance of the model for
advanced device structures, are investigated. The singleemitter thermal impedance
model is finally extended to account for BJT/HBT's with multiple emitter fingers.
2.2 Derivation of the SingleEmitter BJT/HBT Thermal Impedance Model
For the derivation of the singleemitter bulk BJT/HBT thermal impedance
model, the semiconductor substrate is represented by a homogeneous semiinfinite
halfspace with an adiabatic top surface (no heat transfer perpendicular to the
surface). The back side of the substrate is assumed to be held at a constant
temperature, To. Since the substrate material is assumed to be homogeneous, the
model most directly applies to junctionisolated transistors. The effects of other
types of isolation structures used in bulk technologies, such as recessed LOCOS
(local oxidation of silicon) or backfilled trenches, on the thermal response are not
taken into account. Figure 2.2 illustrates the simplified device geometry assumed for
the model derivation; the diagram focuses on the "electrically active" portion of the
device that lies directly beneath the emitter stripe, which has a width W and length
Collector
psubstrate
Crosssection of a typical junctionisolated bipolar junction transistor
(BJT).
Figure 2.1
Emitter
Base
(dT/dz) = 0
__  r_ 
The simplified device geometry used to define the solution domain for
the bulk, singleemitter BJT/HBT thermal impedance model. The
substrate is represented by a semiinfinite halfspace with an adiabatic
surface (the dotted lines). The emitter stripe has a width W and length
L. The heat source (the rectangular volume) is displaced a distance D
below the surface of the device, equivalent to the depth of the base/
collector junction. The heat source has a thickness H which
approximates the base/collector spacecharge region (SCR).
D
H
Figure 2.2
L. The imbedded heat source represents the base/collector spacecharge region
(SCR), which is further represented by a rectangular volume with a thickness, H. The
heat generated in this region is assumed to be due to uniform power dissipation. This
assumption is reasonable for devices in the forwardactive region of operation prior
to any high current effects, as the current distribution in the intrinsic device will be
approximately uniform. The electric field gradient in the base/collector SCR can also
be neglected since it does not greatly affect the thermal impedance model. The heat
source is displaced beneath the surface of the substrate by a distance D, assumed to
be the depth of the base/collector junction. Thus, any encroachment of the base/
collector SCR into the base region is neglected (which is reasonable since the base
typically has a higher doping than the collector).
Representing the substrate as a semiinfinite medium presumes that the
backside and the lateral edges do not influence the thermal response of the device.
Neglecting the effects of the back side of the substrate on the thermal response is
reasonable since a typical wafer is about 1000 times thicker than the heat source.
Neglecting the effects of the lateral boundaries requires that the device be located
sufficiently far from the substrate edges; the work by Fox et al. [Fox93b] suggests
that this assumption is valid for any device that is at least a distance 5/W L from
any lateral edge. The surface of the substrate is assumed to be the only boundary that
affects the thermal response of the device and it is considered to be adiabatic; thus,
conduction through the interconnects and conduction/convection from the surface
are neglected. Ignoring thermal energy transport from the substrate surface is
supported by the work of Berger and Chai and Goodson et al. [Ber91, Goo95];
however, they were mainly concerned with transport via convection to a surrounding
gas (namely air). Nonetheless, for the regions of the device covered by oxide, it is
unclear whether there is substantial heat conduction to this overlying oxide. From the
analysis of Goodson et al. [Goo95], the devicetooxide thermal conductance is of the
order of G = 4rk, which corresponds to an isothermal disk of radius r on the
boundary of a semiinfinite medium of thermal conductivity k. Approximating the
radius as J(WL)/7t and using the roomtemperature thermal conductivity of SiO2,
the devicetooxide thermal conductance for a typical device is on the order of
1 x 106 (W/OC). Comparably, the devicetosubstrate thermal conductance is on the
order of 1 x 103 (W/C), showing that the majority of heat will flow through the
substrate.
The temperature rise at any point within the device can be described by the
nonhomogeneous threedimensional heat conduction equation
V2AT(x, y, z, t) + g(x, y, z, t) I DAT(x, y, z, t) (2.1)
k a at
and the boundary conditions
AT( y, z, t) = 0 (2.2)
AT(x, +oo, z, t) = 0 (2.3)
aAT(x, y, z, t) 0 (2.4)
z=o
AT(x, y, o, t) = 0, (2.5)
where AT is the temperature rise above the local ambient (AT = TTo), g is the
internal energy generation density, k is the thermal conductivity, a is the thermal
diffusivity (a = k/(p cp) where p is the density and cp is the specific heat) and t
is time. Typical values for the material properties are given in Table 2.1.
Table 2.1 Semiconductor material properties
Source: [Mul77]
Equation (2.1) assumes that the thermal conductivity is independent of temperature
and position. Neglecting the temperature dependence of the thermal conductivity is
reasonable for a moderate temperature rise, where the temperature rise will vary
linearly with power dissipation. However, for large temperature excursions, the
value of the thermal conductivity can vary significantly; the thermal conductivities
of Si and GaAs will vary from their roomtemperature values by more than 20%
above 355 and 390 K, respectively [Gao89]. For such large temperature excursions,
the linear relation between temperature rise and power will not be valid. However,
the temperature dependence of the thermal conductivity can be accounted for by
Parameter Si GaAs
k (W cm K1) 1.412 0.455
p (g cm3) 2.328 5.316
Cp (J g1 K1) 0.70 0.35
using the Kirchoff transformation [Joy75], as discussed in Chapter Eight. Neglecting
the spatial dependence of the thermal conductivity implies that the effect of dopant
atoms is ignored. In the works by Weber and Gmelin and Goodson et al. [Web91,
Goo95], the thermal conductivity of doped silicon (up to lx1018 and 1.7x1019 dopant
atoms cm3) above 300 K is shown to differ only slightly from that of intrinsic
silicon. Since the majority of the substrate is typically lowdoped semiconductor
material, neglecting the doping effects on the thermal conductivity is reasonable.
With the initial thermal conditions within the substrate specified as
AT(x, y, z, 0) = 0, (2.6)
the solution to (2.1) can be expressed in the form
t
AT G(x, y, z, t) dt G(x, y, z, tx', y ,t')g(x', y, z, t')dv' (2.7)
t'=0 V
where
1 (x(x) (y)y)
G(x,y,z, tx',y',zz',t') = 1 __(exp  exp (
8[to(tt')]3/2 L4(t t )J 4(t t)
exp (z') + exp ( (2.8)
4a(t j t) 4(t t )(2
is the Green's function for the given boundaryvalue problem [Ozi93]. Equation (2.8)
is the solution to
V2G + gpi (x x')8(y y')8(z z')(t t) 1 G(2.9)
k a at
for the boundary and initial conditions given by (2.2) through (2.6), and physically
represents the temperature at point (x, y, z) at time t, due to an instantaneous point
source, gp (W s), of unit strength at point (x', y', z') at time t .
To account for the heatgeneration volume (V = W L H), (2.8) is
substituted into (2.7) and integrated over the base/collector SCR, resulting in
t
SP(t') ( L/2 + x ( L/2x x
AT(x, y, z, t)= P(t erf( L/2x +erf
S8pcV \,4ac(t t) 4c((t t')
t=0
r W/2+y W/2y
[erf( W/2+ + erfW/2
L V4a(t t') ,4a(t t')
S[erf z+D+H erf( Dz_
L erf)+erf
L 4a(t t4) a4(t t))
( zD D+Hz
+ef erf +erf( D+Hzdt' (2.10)
/4a(t t) J4c(t t )
where g(x', y', z', t') = g(t') = P(t')/V, since the power dissipation is assumed to be
uniform. Equation (2.10) represents the temperature response at any point in the
device at time t due to a change in continuous power dissipation in the base/collector
SCR. Assuming a step increase in power at t' = 0 (P(t') = P U(t) ) and expressing
the temperature rise as
AT(t) = ZTH(t) P (2.11)
yields the transient thermal impedance
r 1 r (L/2 +x+ erfL/2x)]
ZTH(x, z, t) = J8p erf2 + erf( 
/2+y y /2y y
S[erf (W/ + erf /2Y
[erf( z+D+H ) D z
erf + + erfy4
+erfz +erf(+Hz dt (2.12)
where the t value of the thermal impedance corresponds to the thermal
spreading resistance RTH.
Equation (2.12) represents the temperature rise at any point in the device
normalized to a unitstep increase in power dissipation. For circuit simulation, a
single temperature is needed to represent the effective operating temperature of the
device. Fox and Lee [Fox91b] showed that the thermal impedance model evaluated
at a surface corner of the emitter (x = L/2, y = W/2, z = 0) agreed well with
measurements of the thermal spreading resistance RTH; substituting these
coordinates into (2.12) gives the following expression for the thermal impedance
1 L (W (D+H D
ZTH e) = J4 rf er erf I erf(D I Idt (2.13)
t ,4pcV 4t 4at \F4at 4atJ
In this form, the thermal impedance model has four geometric input
parameters. Of the four, three (W, L and D) are determined directly by the device
layout. However, the fourth parameter, H, depends on the operating bias of the
device. The thickness of the base/collector SCR, H, can be estimated using the
depletion approximation; assuming a onesided step junction with uniform doping on
each side gives
2 Eg 0 (VR + bi)
H = R (2.14)
q Nepi
with
kB T N
Ybi n i (2.15)
where Esi is the dielectric constant of silicon, Eo is the permittivity of free space, VR
is the reverse bias voltage on the base/collector junction, q is electronic charge, Nepi
is the doping level in the epicollector, kB is Boltzman's constant, T is temperature,
Nb is the doping level in the base, and ni is the intrinsic carrier concentration in
silicon. fbi is the builtin potential of the base/collector junction. Equation (2.14)
shows that the thermal impedance depends on the bias of the base/collector junction,
and therefore can change during device operation. However, the squareroot
dependence of H on the base/collector voltage, is relatively weak. Figure 2.3
illustrates the variation of the modeled thermal resistance with changes in the
thickness of the base/collector SCR. The three data points plotted for each simulated
device correspond to reverse bias base/collector voltages of 5, 10 and 20 V. The
largest variation is observed for the smallest device, which shows a 25% change in
its thermal resistance going from VR = 0 V to 20 V. The larger devices show a
weaker dependence on H and have no more than a 15% change in thermal resistance
30
20
10
0
150
Figure 2.3
200 250 300 350 400
Variation of H (%)
Simulations showing the effect of variations in the thickness of the
base/collector spacecharge region on the thermal impedance model
(evaluated at steadystate) for different geometry BJTs. For each
device, D = 0.35 m, Nepi = 1 x 1016 cm3 and N = 1.5 x 1018 cm3.
The yaxis corresponds to the variation between the model evaluated
at VR = 0 V and the model evaluated at VR equal to 5, 10 and 20 V.
going from VR = 0 V to 20 V. However, at high base/collector biases, the maximum
value of H becomes effectively independent of bias. As shown in Figure 2.1, typical
bipolar technologies use a heavilydoped buried layer to reduce collector resistance.
At high base/collector biases, the lowdoped epicollector region depletes down to
the buried layer; consequently, the maximum value of H should be properly limited
to the thickness of the epicollector.
2.2.1 Modification for Finite Wafer Thickness
As previously derived, the thermal impedance model for singleemitter
bulk BJT/HBT's represents the substrate as a semiinfinite halfspace. This
representation assumes that the back side of the substrate does not affect the thermal
response of the device. In general, this is reasonable since the basecollector junction
is usually within 1 pim of the substrate surface, and a typical wafer is between 350 to
800 pim thick. However, wafers are commonly backlapped to improve thermal
performance, and substrate thicknesses of 75, 80 and 100 p.m have been reported by
a number of authors [Kag94, Mar93, Liu95a]. As the wafer thickness is reduced, the
substrate can no longer be approximated by a semiinfinite medium and the effects
of the backside boundary must be taken into account.
The threedimensional Green's function in the rectangular coordinate
system can be represented by the product of three onedimensional Green's functions
G(x, y, z, tx', y', z', t') = Gx(x, tx', t') Gy(y, ty', t') Gz(z, tz', t').
(2.16)
The lateral boundaries are still assumed to extend infinitely and their effects on the
thermal response are neglected; thus, the Green's function solutions in both the x and
y directions remain unchanged. In the zdirection, however, the substrate is now
assumed to have a finite thickness Dsub. The top surface of the substrate is still
assumed to be adiabatic. The bottom surface of the substrate is assumed to be at a
constant temperature, T(Dsub) = T0, so that the temperature rise at this surface is
defined by AT(Dsub) = T(Dsub) T = 0. These boundary conditions define the
new Green's function for the zdirection, which is given by
2 2
G,(z, tz', t') = exp[ac ip(tt')] Du cos(rpz) cos(7lpz) (2.17)
sub
p=l
where lp is the set of eigenvalues for the boundaryvalue problem and are given by
the positive roots of
cos(TipDsub) = 0. (2.18)
Equation (2.18) is solved when the argument of the cosine equates to odd multiples
of t/2. Using equations (2.17), (2.16), (2.11) and (2.7), and then integrating over the
base/collector SCR, assuming a unitstep increase in power at t = 0, gives the
following expression for the thermal impedance at any point in the device
Sdtr L/2+ x L/2x
ZTH(x, y, t) = ] erf  + erf
t 4pcV 4ot ) 4a t
F (W/2+y\ (W/2yi
erf W/2 + erf(/2 y
2cos(rOpz)exp(arpt)
= pf 71PDS~b
p=1 pDsub
{sin[qlp(D + H)] sin[T[pD]} (2.19)
where V = W L H and
(2p 1) (2.20)
4 = 2D (2.20)
2sub
Evaluating (2.19) at the coordinates (x = L/2, y = W/2, z = 0) to give a single
effective operating temperature, results in the following expression for the thermal
impedance
7 dt (4L W ( )
ZTH(t) = erf( L rf(W
TH M 4pcV F4 (t 4att
2
S2exp(a0rl t)
S p Dsub { sin [rp(D+ H)] sin [lpD]} (2.21)
p= sub
Since (2.21) is derived from the physical heat conduction equation, it can
be used to anticipate the effects of substrate scaling on the thermal impedance.
Figure 2.4 illustrates equation (2.21) evaluated at various values for Dsub. The
results show that the thermal resistance decreases as the substrate thickness is
reduced, which agrees with the trend predicted by Hattori et al. using a three
dimensional numerical simulator [Hat95]. Figure 2.4 also shows that (2.13) provides
675
650
625
600
575
550
525
500
400
500
Simulations showing the effect of substrate thickness on the thermal
impedance model (evaluated at steadystate). The model accounting
for finite substrate thickness is compared to the model assuming
infinite substrate thickness. The device specifications are L = 4 9m,
W = 1 jim, D = 0.35 pm, H = 0.35 im.
200 300
Substrate Thickness, Dsub (Pm)
Figure 2.4
0.
I 0G OModel w/finite Dsub
Model w/infinite Dsub
I I I
an accurate prediction of the thermal resistance over most of the range of substrate
thicknesses: only when the substrate thickness is significantly reduced (< 100 itm),
is there a large deviation between the two models.
2.2.2 Effects of Interconnect Metallization on the Thermal Impedance
For the derivation of the BJT/HBT thermal impedance model, the surface
of the substrate is assumed to be adiabatic. In actual devices, portions of the base,
collector and emitter regions are in direct contact with the metallization used to
electrically connect different devices on a chip. Since the metallization typically has
a high thermal conductivity, it is possible that the heat conduction via the
interconnects significantly influences the thermal response of a device. Therefore,
the validity of such an assumption should be investigated.
Threedimensional (3D) finiteelement (FE) thermal simulations of a
bipolar transistor, using the ANSYS software package [Ans96], were performed to
examine the effects of the interconnect metallization on the thermal impedance. To
simplify the FE model, the device was considered to be symmetric in both lateral
directions; therefore, only one quarter of the device was simulated. The bottom and
exterior sides of the substrate were assumed to be at a fixed ambient temperature. The
top and side surfaces of the interconnects, as well as the top surface of the interlayer
dielectric, were assumed to be adiabatic. The FE simulations tend to overpredict the
heat conduction through the interconnects since any contact resistances at the
material interfaces were neglected. The assumed symmetry of the device implies that
the base and collector metallization are equidistant from the emitter. In typical
devices, the collector contact is offset a greater distance from the emitter than the
base contact. Typical ranges for these offsets are 0.5 to 10 urn between the base and
emitter contacts, and 2.5 to 25 Lim between the collector and emitter contacts
[Gra93]. While the FE model does not exactly represent any actual device structure,
it can provide an estimate for the significance of the heat flow through the
interconnects as a function of their distance from the active device.
Figure 2.5a shows the FE model for bipolar devices with full
metallization. Steadystate thermal simulations were run for various interconnect
spacings; this spacing corresponds to the edgetoedge distance between the emitter
and base/collector interconnects. Simulations were also run of the same structure
with the base/collector interconnect removed. The results of the two groups of
simulations were compared to determine the effect of the base and collector
interconnects on the thermal resistance. Figure 2.5b shows the results of the
comparison between the FE simulations. The data clearly shows that the effect of the
base/collector interconnect metallization is small and decreases as the interconnects
are moved away from the active device area. The collector interconnect has less of
an effect on the thermal impedance than the base interconnect, due to the larger
distance between the collector contact and the active device. In any case, the effect
of either the base or collector interconnect should be negligible compared to the
influence of the emitter metallization.
To determine the extent of the effect of the emitter interconnect on the
thermal impedance, steadystate thermal simulations were run for different devices
with only the emitter metallization in contact with the device. Figure 2.6a shows the
2.5
2.0
r
c3
S1.5
E
 1.0
r
o
i 0.5
0.0
Interconnect Spacing (tm)
Figure 2.5
ANSYS simulations showing the effect of emitter, base and collector
interconnects on the thermal resistance. The device specifications are
D = 0.2 pim and H = 0.35 jIm, the interconnect width Wmet = 2 pmr
and thickness diet = 0.9 [tm, and the interlayer dielectric thickness
dox = 0.7 gim: a) The finiteelement model simulated with ANSYS; b)
the variation between the thermal resistance accounting for emitter,
base and collector interconnects and the thermal resistance accounting
for only the emitter interconnect, plotted as a function of the spacing
between emitter and base/collector interconnects.
50 100
50 100
Variation of Parameter (%)
(b)
200
250
ANSYS simulations showing the effect of the emitter interconnect on
the thermal resistance for variations in different technology
characteristics. The specifications for the nominal device are
L = 4 pm, W = 1 pm, D = 0.35 pm, H = 0.35 pm, dmet = 0.9 Im,
dox = 0.9 pm and Wmet = 2 [m: a) The finiteelement model
simulated with ANSYS; b) the variation between the thermal
resistance accounting for the emitter interconnect and the thermal
resistance neglecting the emitter interconnect. The variation plotted on
the xaxis corresponds to the deviation of each structure parameter
from its nominal value.
30
25
.)
U
S20
S15
.C
H
.E 10
c
5 5
0
0
Figure 2.6
nominal
SOdmet
a dox
OD
AL
Wmet
o0 A
AA
a/
^ ^
FE model for devices with only the emitter metallization. The same devices were also
simulated with the emitter interconnect removed. The simulations were performed by
independently varying each structure parameter of the FE device model. Reasonable
values were chosen for each parameter to represent a nominal device design; each
parameter was varied about the nominal value to represent a reasonable range of
technology scaling. Figure 2.6b shows the results of the FE simulations. The emitter
metallization becomes a more effective path for heat evacuation as the thickness,
dmet, and the width, Wmet, of the interconnect increase and as the thickness, dox, of
the dielectric layer between the substrate and the interconnect decreases. The data
also show that the effect of the emitter interconnect increases as the depth of the base/
collector junction is decreased (the heat source is moved closer to the surface) and
as the length of the emitter is decreased.
Transient thermal simulations of the FE model in Figure 2.6a were used to
examine the effect of the emitter interconnect on the transient thermal response.
ANSYS was used to simulate the structure with and without the emitter interconnect
in contact with the device; the results are shown in Figure 2.7. The thermal responses
for the device with and without the interconnect match until significant heat reaches
the surface of the device. The time for heat to reach the surface of the device can be
approximated as the square of the distance D divided by the thermal diffusivity of
the substrate material. The resulting time is approximately 0.44 nanoseconds, which
agrees with the FE simulations. The adiabatic boundary condition of the device
without the interconnect predicts a larger response since the heat is completely
reflected once it reaches the surface. The device with the emitter metallization, which
1.5
U
0

1.0
S0.5
[
0.0
1C
Figure 2.7
1010 108 106 104 102
Time (sec)
ANSYS simulations showing the effect of the emitter interconnect on
the transient thermal impedance. The specifications for the device
structure are L = 2 pm, W = 1 im, D = 0.2 jim, H = 0.35 gim,
dmet = 0.9 gm, dox = 0.7 gm and Wmet = 2 im.
acts as a separate heat sink path, has a reduced thermal impedance and an effectively
slower thermal response.
Based on the results of the 3D FE simulations, neglecting the base and
collector interconnect metallization in the model derivation is reasonable since it
only slightly affects the thermal impedance of a device. The emitter interconnect,
however, has a greater influence on both the steadystate and transient thermal
responses. The effect on the thermal resistance will be more significant for devices
with smallgeometry emitters and shallow base regions, where the transient thermal
response will mainly be affected for large devices with substantial contact structures.
In either case, equations (2.13) and (2.21) will tend to overpredict both the steady
state thermal resistance and the transient rise of the thermal impedance.
2.2.3 A Model for the Thermal Impedance of the Emitter Interconnect
As shown in the previous section, the assumption that the top surface of
the device is adiabatic neglects heat flow in the emitter interconnect and results in a
thermal impedance model that overestimates the transient temperature rise in a
bipolar device. To model the effects of the emitter interconnect on the overall
thermal impedance, both the thermal resistance and thermal capacitance of the
metallization need to be considered.
The thermal resistance of the emitter metallization is derived by assuming
that the interconnect can be represented by a onedimensional cooling fin, so that the
temperature rise at any point xmet along the interconnect,
ATmet(xmet) = Tmet(xmet) To, can be approximated by
m2ATmet 2
2 mmetATmet 0.
aXmet
(2.22)
The second term on the lefthand side of (2.22) accounts for heat conduction through
the underlying oxide as the heat travels along the interconnect, where
1 kmetdmet
mmet hmet
(2.23)
is the characteristic thermal length in the interconnect and
h = kox
met d
ox
(2.24)
is the heat transfer coefficient from the interconnect to the substrate. The material
properties for the emitter interconnect are given in Table 2.2.
Table 2.2 Emitter interconnect material properties
Source: [Ozi93]
* Assumed to be aluminum
Property Definition Value
kmet Thermal conductivity 2.39 (W cmI K)
Pmet Density 2.7 (g cm3)
Cpmet Specific Heat 0.9 (J g' K)
Approximating the temperature in the interconnect using a onedimensional equation
implies that the temperature gradients in the vertical and lateral directions within the
emitter interconnect are negligible. The validity of such an assumption can be
evaluated using the Biot number, which corresponds to the ratio of the internal and
external thermal resistances of a given object [Ozi93]. If the Biot number for the
interconnect is much less than unity, then the interconnect can be approximated as a
onedimensional thermal medium. The vertical and lateral Biot numbers for the
emitter interconnect are given by Bvmet = hmetdmet/kmet and
BLmet = hmetWmetetdmetmet), respectively. For most practical metallization
geometries, the Biot numbers are much less than one and the coolingfin model is an
accurate representation of the emitter interconnect.
Assuming that the temperature rise in the interconnect at the emitter
contact is equal to the effective operating temperature of the device, and that the
temperature rise approaches zero far from the contact, the thermal resistance of the
emitter interconnect can be expressed as
RTHmet [kmetmmetmtet]et (2.25)
The thermal capacitance of the emitter metallization can be approximated as
CTHmet PmetCpmetVmet. (2.26)
The volume of the metallization is Vmet = W L met, where 5met represents the
effective length of the interconnect structure. The parameter 5met should be
evaluated to include the volume of the contact and interconnect metallization but can
also be extracted from transient thermal measurements or numerical simulations.
Once the thermal resistance and thermal capacitance have been calculated, the
transient thermal impedance of the emitter interconnect can be approximated by
ZTHmet(t) = RTHmet[l exp t (2.27)
1 .Tmet '
where Tmet = RTHmetCTHmet. The overall thermal impedance of a bipolar device can
now be represented by the parallel combination of two thermal impedances, such that
effectively
ZTHdev(s) ZTHmet(S)
ZTH(S) = (2.28)
ZTHdev(s) + ZTHmet(S)'
where ZTHdev(s) is determined from the transient thermal impedance given by either
(2.13) or (2.21).
2.2.4 Effects of Isolation Structures on the Thermal Impedance
While junctionisolated technologies are still used, the drive to increase
packing density, improve lateral isolation and increase device operating speeds has
led to the development of newer isolation technologies for VLSI bipolar applications.
The advanced isolation technologies typically used in bulk bipolar fabrication are
recessed LOCOS (local oxidation of silicon) and Ugroove [Wol90, Gra93];
Figure 2.8 illustrates examples of bipolar devices fabricated with these isolation
techniques. Since advanced isolation structures typically use low conductivity
Collector
psubstrate
(a)
Base Emitter Collector
Oxide p \ Oxide
INE 1 N
N,
psubstrate
Crosssections of typical BJT's fabricated with advanced isolation
technologies: a) Recessed LOCOS; b) Ugroove isolation.
Figure 2.8
Emitter
Base
materials like SiO2, the thermal impedance of a device using such isolation tends to
be higher than that of its junctionisolated counterpart. The bulk BJT/HBT thermal
impedance model treats the substrate as a homogeneous material; therefore, it is
unclear whether the thermal impedance model is applicable to devices which are
fabricated with advanced isolation.
Threedimensional (3D) finiteelement (FE) thermal simulations, using
ANSYS, were performed to examine the effects of advanced isolation structures on
the thermal impedance of bipolar transistors. Two FE models were developed to
separately investigate the effects of recessed LOCOS and Ugroove isolation. To
simplify the FE models, the device was considered to be symmetric in both lateral
directions, so that only one quarter of the device was simulated. The bottom and
exterior sides of the substrate were assumed to be at a fixed ambient temperature. The
top surface of the device was assumed to be adiabatic. Due to the assumed symmetry,
the active device region was surrounded on all sides by the isolation structure, which
was at uniform distance from each side of the emitter. As shown by the illustrations
in Figure 2.8, the distance between the isolation structure and the intrinsic device is
not uniform on all sides of the device. Typical values for the distance between the
emitter and the isolationfor the portions of the isolation structure immediately
surrounding the emitterare in the range from 0.3 ptm to 0.8 p.m for advanced bipolar
devices [Del91, Klo93, Yam93, Pru94]. The distance between the emitter and the
portion of the isolation structure on the far side of the collector contact is generally
larger, typically two to four microns [Del91, Klo93]. For both FE models, the side
walls of the isolation structures were perpendicular to the top surface of the substrate.
For typical Ugroove isolation, the trench is created by anisotropic etching and the
sidewalls are nearly perpendicular to the surface. However, actual LOCOS
structures have tapered edges (see Figure 2.8) that get progressively thinner toward
the active device. To determine the implications of the model's nonphysicality, two
dimensional (2D) FE simulations were run for various angles (30 to 90 degrees)
between the substrate surface and the sidewall of the isolation. The simulations
showed that the temperature rise increased as the angle increased; thus, the 3D
LOCOS model should show a larger effect than that of an actual isolation structure.
While the finiteelement models do not truly represent the physical device layout,
they allow an orderofmagnitude estimate for the effects of the isolation structures
on the thermal impedance.
Steadystate thermal simulations were run for various deviceisolation
spacings, corresponding to the edgetoedge distance between the emitter and the
isolation structure. For the Ugroove isolation model, this spacing is the distance
between the emitter and the edge of the surface LOCOS; the actual trench is assumed
to be an additional 0.5 pm away from the edge of the LOCOS [Del91, Yam93].
Simulations were also run for the same devices with the isolation structures removed.
LOCOS isolation is formed by selectively oxidizing regions of the
semiconductor substrate in a dry or wet oxygenrich ambient. For bipolar
technologies, the resulting Si02 structures are typically no more than one micron
thick, since the growth of thicker oxides is impractical [Wol90, Gra93]. Figure 2.9a
illustrates the FE model for bipolar devices with recessed LOCOS isolation. The
oxide was assumed to be fully recessed beneath the top surface of the substrate and
0 0.5 1.0 1.5 2.0 2.5 3.0 3
DeviceOxide Spacing (Lim)
ANSYS simulations showing the effect of recessed LOCOS isolation
on the thermal resistance. The device specifications are L = 2 inm,
W = 1 rim, D = 0.35 jim and H = 0.35 jim: a) The finiteelement
model simulated with ANSYS; b) the variation between the thermal
resistance accounting for the isolation and the thermal resistance
assuming a homogeneous substrate, plotted as a function of the edge
toedge spacing between the emitter and the isolation.
Odfox = 1.0 lOm
30
20
C;
E
.2 10
O
.0
0
Figure 2.9
I 1 I 1 1 1 I I I
had a thickness, dfox, of one micron. Figure 2.9b compares the FE simulations with
and without the isolation. The effect of the LOCOS can be significant at small
deviceisolation spacings, but decreases as the isolation is moved away from the
active device region. In Figure 2.8a, the portions of the LOCOS structure close to the
emitter have the largest effect on the thermal response, since they directly restrict the
lateral heat flow away from the device. A number of manufacturers are using thinner
standard or semirecessed LOCOS (0.3 to 0.6 gim) combined with junction isolation
to reduce fabrication times and improve compatibility with existing MOS
technologies [Klo93], [Pru94]. The thinner oxides have a smaller effect on the
thermal resistance, and therefore, the FE simulations can be considered worstcase.
Ugroove isolation differs from LOCOS in that trenches are etched
directly into the substrate and then backfilled with oxide and polysilicon. The depth
of the trench, dtr, is typically on the order of 3 pim [Yam93, Ona95], but has been as
large as 5 ptm [Del91]; the width of the trench is generally in a range from 0.6 to
1.5 pim [Del91, Yam93, Ona95, Shi96]. Ugroove trenches will typically have a
surface LOCOS layer, but the thickness of this layer is usually no greater than 0.1 to
0.15 jim [Yam93], since the isolation is mainly achieved by the trench. Figure 2.10a
shows the FE model for devices with Ugroove isolation. The thickness of each fill
layer (dtrox for oxide and dpoly for polysilicon) in the Ugroove was assumed to be
uniform. Figure 2.10b compares the FE simulations with and without the isolation.
The effect of the Ugroove isolation on the thermal resistance is greater for small
deviceisolation spacings than in LOCOS due to the larger depth of the trench.
0.5 1.0 1.5 2.0 2.5
DeviceIsolation Spacing
3.0
(pm)
3.5 4.0 4.5
Figure 2.10
ANSYS simulations showing the effect of Ugroove isolation on the
thermal resistance. The device specifications are L = 2 tm,
W = 1 pm, D = 0.35 pim and H = 0.35 p.m. The Ugroove
specifications are dtr = 3.5 Jm, dtrox = 0.38 pm and dply = 0.75 pm:
a) The finiteelement model simulated with ANSYS; b) the variation
between the thermal resistance accounting for the isolation and the
thermal resistance assuming a homogeneous substrate, plotted as a
function of the edgetoedge spacing between the emitter and the U
groove isolation.
60
50
, 40
CZ
E 30
.
.5 20
0
' 10
c>
IIIIIIIII
However, these results represent the worst case, since in an actual device the active
region is not immediately flanked by the Ugroove on all sides.
Transient thermal simulations of the FE models shown in Figure 2.9a and
Figure 2.10a were used to examine the effects of both LOCOS and Ugroove
isolation on the transient thermal response. ANSYS was used to simulate the device
with and without the isolation structures; the results are shown in Figure 2.11. As the
heat travels laterally and reaches the edges of the isolation structure, the response
accounting for the isolation begins to deviate from the response without the isolation.
The time for the heat to reach the edges of the isolation structures can be
approximated as the square of the deviceoxide separation (1 jtm) divided by the
thermal diffusivity of the substrate material; the resulting time is on the order of ten
nanoseconds, which agrees with the simulations of both the LOCOS and Ugroove
isolation. The oxide used in the isolation structures restricts the lateral flow of heat
away from the device and in both cases results in a larger temperature rise.
Based on the results of the 3D FE simulations, advanced isolation
structures such as recessed LOCOS and Ugroove can considerably increase the
thermal impedance of bipolar devices. In most cases, the bulk bipolar model will tend
to underpredict both the steadystate and transient thermal response of devices
fabricated with oxidebased isolation structures. The error in the model will be the
greatest for advanced, highlyscaled devices fabricated with deep trench isolation.
102
Time (sec)
(a)
102
Time (sec)
Figure 2.11
ANSYS simulations showing the effect of advanced isolation
structures on the transient thermal impedance. The deviceisolation
spacing is one micron. The specifications for the device structure are
L = 2 rim, W = 1 rim, D = 0.35 ptm and H = 0.35 gim: a) Recessed
LOCOS or BOX isolation with dfox = 1.0 prm; b) Ugroove isolation
with dtr = 3.5 pLm, dtrox = 0.38 lim and dpoly = 0.75 pm.
2.3 Verification of the SingleEmitter Thermal Impedance Model
To verify the thermal impedance model, threedimensional (3D) finite
element (FE) simulations of a junctionisolated BJT were performed using ANSYS.
Interconnect metallization was neglected and the substrate was assumed to be
homogeneous silicon with the bulk properties given in Table 2.1. The FE simulations
were evaluated at the surface corner of the emitter and compared to the singleemitter
thermal impedance model given by equation (2.21); the results are shown in
Figure 2.12. The analytic model agrees closely, for both the steadystate and the
transient, with the 3D FE simulations for both device geometries. The predicted
values for the steadystate thermal resistance agree within twelve percent of the FE
simulations. The error can be partially attributed to numerical error associated with
the FE mesh.
The model was also compared to measured thermal impedances. The
measured data were extracted using the basethermometry technique developed by
Zweidinger et al. [Zwe96]. Figure 2.13, Figure 2.14 and Figure 2.15 compare the
measured and simulated data for the transient thermal impedance of Harris HBC bulk
BJTs. The thermal impedance model does a good job of predicting the steadystate
thermal resistance, with no more than a 20% error between the model and the
measurements. The model given by (2.13) tends to overpredict the transient
response. As shown with the ANSYS simulations in Figure 2.7, this discrepancy can
be attributed to the model's neglect of the emitter metallization. When the thermal
impedance of the emitter interconnect is accounted for, with 5met = 50 pim extracted
TEMPERATURE (C):
I I
27
27,431
27.863
28,294
28.725
29,157
29.588
30,019
30.451
30,882
Time (sec)
(b)
Figure 2.12 The transient thermal impedance simulated with ANSYS and
calculated with the bulk, singleemitter model: a) The finiteelement
model simulated with ANSYS for P = 1.8 mW; b) comparison of
thermal impedances simulated with ANSYS (symbols) and the thermal
impedance model (lines).
1150
950
750
550
350
150
50
1
10"
Time (sec)
~'50
U
0
E40
~30
 20
E
0
102
102
10u
Time (sec)
Figure 2.13
Measured and
Harris HBC
L = 100 tm.
simulated data for the transient thermal impedance of
bulk BJT's with W = 2 m: a) L = 30 m; b)
300
220
140
60
106
Time (sec)
20
102
Time (sec)
Figure 2.14
Measured and simulated data for the transient thermal impedance of
Harris HBC bulk BJT's with W = 3 4im: a) L = 10 itm; b) L = 30 pim.
260
220
180
140
100
60
20
102
Time (sec)
102
Time (sec)
Figure 2.15
Measured and simulated data for the transient thermal impedance of
Harris HBC bulk BJT's with W = 5 ptm: a) L = 10 pnm; b) L = 30 pm.
from the measurements, the model provides a more accurate representation of the
transient thermal response.
2.4 Derivation of the MultipleEmitter BJT/HBT Thermal Impedance Model
The thermal impedance model for bulk MEBJT/MEHBT's is an extension
of the singleemitter model. A multipleemitter device consists of singleemitter
devices placed adjacent to each other along their lengths. Since there are multiple
devices (referred to as "emitter fingers") that are thermally coupled through the
substrate operating in close proximity, the temperature rise in each emitter finger is
affected not only by its own power dissipation, but also by the power dissipated by
its neighbors. The heat conduction equation, (2.1), is linear, so superposition can be
used to calculate the total temperature rise in the device. The equation for the
temperature rise can then be manipulated to provide expressions for the effective
temperature rise in each individual finger.
Figure 2.16 illustrates the simplified multipleemitter device geometry
assumed for the model derivation. The substrate is represented by a homogeneous
semiinfinite halfspace with an adiabatic top surface with multiple imbedded heat
sources. The emitter fingers are assumed to be uniform in size and shape, with width
W and length L. Each finger has a corresponding heat source, due to an assumed
uniform power generation in the base/collector SCR; each heat source has a thickness
H and is displaced a distance D below the surface of the substrate. As with the
singleemitter model, D is assumed to equal the depth of the base/collector junction
W K"1
Figure 2.16
The simplified device geometry used to define the solution domain for
the bulk, multipleemitter BJT/HBT thermal impedance model. The
substrate is represented by a semiinfinite halfplane with an adiabatic
surface. Each emitter finger has a width W and length L and each heat
source (the rectangular volumes) is displaced a distance D below the
surface of the device and has a thickness H. The distance D is
equivalent to the depth of the base/collector junction and the thickness
H is approximated by the thickness of the base/collector SCR. The
emitter fingers are uniformly spaced with and edgetoedge separation
distance S.
and H can be calculated using equations (2.14) and (2.15). The edgetoedge
separation, S, between adjacent fingers is assumed to be uniform.
The Green's function technique can be employed to find the temperature
rise within the device. By applying superposition, the solution is expressed as the
sum of the Green's function solutions for the multiple heat sources
n t
AT(x, y, z, t) = J dt' G(x, y, z, tx', y', z', t')g(x', y', z, t')dv'. (2.29)
1 t =0 V
where G(x, y, z, tx', y', z', t') is given by equation (2.8). The summation accounts for
the integration over the different spatial coordinates of each heat source. To clarify
the derivation, certain conventions and definitions can be established. The origin for
the coordinate system is fixed at the center of the leftmost finger at the surface of
the device. A device is considered to have a total of n emitter fingers and a reference
order is established with the fingers numbered sequentially starting from the left
most finger. The character j, where j = 1 > n, is used to reference a specific emitter
finger. The ith neighbor (where i = i > n 1) of a given emitter finger, EFj, is
defined as a finger situated an edgetoedge distance [iS + (i 1)W] away on either
side. Using equations (2.8) and (2.29), the temperature rise at any point in the device
assuming a step increase in power at t = 0 for each fingeris given by
n ^P v dt .(L/2 + x erf(L/2 x
AT(x, y, z,t) = 8V[e[ () erf J
S[erf( (2j3)W/2 (j 1)S
+ erf(y+(2j1)W/2+(j 1)S']
/(xti
[r z+D+H Dz
erf +D+H + erf(z
(zD) D+Hzcl
+ erf +erf (2.30)
which accounts for n heat sources, one for each emitter finger EFj.
Equation (2.30) can be manipulated to provide the temperature rise in each
emitter finger. As with the singleemitter model, the temperature rise in each finger
is represented by a single effective value. To simplify the derivation, symmetry is
assumed such that the distance from the effectivetemperature point of finger EFj to
the heat source of its i th neighbor, is the same as the distance from the effective
temperature point of the ith neighbor to the heat source of EFj. This symmetry is
attained only for the coordinates (x, y = [j I ][S + L], z). When (2.30) is evaluated
at each of these points, the model is reciprocal and the effective temperature rise in
each emitter finger, ATEFj, can be expressed as
ATEFI ZS ZCI ... ZC(n 1) P
ATEF2 ZC Zs ... ZC(n 2) P2
ATEFn ZC(nl) ZC(n 2) S Pn (2.31)
where Zs is referred to as a self impedance and ZCi is the i th coupling impedance.
The system of equations given by (2.31) shows that the temperature rise
in each finger is determined by the power dissipation in its own heat source and by
the power dissipated in the (n 1) neighboring heat sources. The self impedance is
given by
v dt (L/2 + x. (L/2 x W/2
Zs(x, z, t) = erf + erf erf
I t 4pcV at at J t
j=It
z[erf(+D+H + Dz
+ erf + erf 
/4c4ct /4at 
erf + erf (D  (2.32)
and accounts for the portion of the temperature rise in a finger due to that finger's
own power dissipation. The ith coupling impedance can be expressed as
Sf dt r fL/2 +x erfL/2x
Zc(x, z, t) =  [erf, +erf 4
j=lt
cJ It 8pcV ( J4xt ) ( /4xt
rf (W/2 + i(W+S)) (W/2 i(W + S))+
e F4at /4 ct
erf ++H + erf( >z
( 14at ) \ /4Tt )
+ erf + e D+rHz (2.33)
,4(t^ J4axt )]
and accounts for the portion of the temperature rise in a finger due to the power
dissipated by its ith neighbor. Thus, for the assumed symmetry, the thermal
impedance of a device with n emitter fingers can be described with a single self
impedance and (n 1) coupling impedances.
Equations (2.32) and (2.33) should be evaluated at a single point to
represent the temperature rise of each finger by a single effective value. To keep the
MEBJT/MEHBT model as similar as possible to the singleemitter model, the points
x = L/2 and z = 0 are used, giving
r ( L ^ CW/2 > (D+ H> D 'Ni
(t = erf rf W2 erf erf dt (2.34)
Zs(t) = 2pcV 4t 4tA) 4(t y4 dt
t 24 pV At f4 (xat J4at /at
and
ZCi(t) = p erf i
Zc 4pcV t4t cv t
[erf (W/2 + i(W + S)) ef(W/2 i(W +S))
erf 4et (2.35)4t
erfD+Herf( D dt (2.35)
L 4at ) 14xt
as the final expressions for the self and coupling impedances. Therefore, the overall
selfheating on the scale of the entire device can be described by the selfheating and
thermal interactions on the smaller scale of each individual emitter finger.
Accounting for a finite wafer thickness can be important for multiple
emitter devices since the coupling impedances decrease as the wafer thickness is
reduced [Daw94], [Hat95]. The multipleemitter model can be modified in a similar
fashion as that for the singleemitter model; by simply using equations (2.17) and
(2.20) in place of the Gz(z, tlz', t') in equation (2.29), the expressions for Zs and Zci
will now account for a finite wafer thickness. Since the multipleemitter thermal
impedance model is simply an extension of the singleemitter model, the effects of
interconnect metallization and advanced isolation technologies are not taken into
account. Neglecting these portions of the overall device structure is assumed to affect
the multipleemitter model in the same manner, and to the same extent, as to which
it affects the singleemitter model.
2.5 Verification of the MultipleEmitter Thermal Impedance Model
Twodimensional (2D) finiteelement (FE) simulations of a junction
isolated, threefinger BJT were performed using ANSYS to verify the multiple
emitter thermal impedance model. Twodimensional FE simulations were used
instead of 3D simulations due to limitations of the available version of ANSYS. The
validity of comparing 2D FE simulations to a 3D analytic model is established by
evaluating the thermal impedance model derived for both two and three dimensions.
Figure 2.17a compares the results, which show that the 3D the 2D models converge
for long devices. The difference in the predicted thermal resistance values decreases
from 22% to less than 1% as the length of the device is increased from 50 pim to
800 ptm. Consequently, the 2D FE simulations can verify the 3D thermal
impedance model evaluated for devices with long emitters. The 2D FE simulations
do not verify the model for shorter devices where the heat flow becomes three
dimensional. However, the verification of the singleemitter thermal impedance
model for 3D heat flow can be assumed to also verify the MEBJT model. This
assumption is reasonable since the physics that describe the singleemitter model
also apply to the MEBJT thermal impedance model.
The physical device was assumed to be symmetric so that the FE model
represented only half of the device. Figure 2.17b shows an illustration of the FE
model simulated with ANSYS. Interconnect metallization was neglected and the
substrate was assumed to be homogeneous silicon with the bulk properties given in
Table 2.1. The bottom and exterior side of the substrate were held at a constant
ambient temperature while the top surface and the interior side were assumed to be
adiabatic. The FE simulations were compared to the multipleemitter thermal
impedance model given by equations (2.34) and (2.35), accounting for a finite
substrate thickness; the results are shown in Figure 2.18. The analytic model agrees
well, in both the steadystate and transient, with the 3D FE simulations of the self
and coupling impedances. The predicted values for the steadystate thermal
resistance agree within three percent of the FE results, which is within the expected
error of the model and the numerical simulations.
74
250
S GO2D Model: L = 50 pm
U 200 03D Model: L = 50 pm
0. 3 2D Model: L = 200 gm O 
S E 3D Model: L = 200 m
AA2D Model: L = 800 pm
150 A3D Model: L = 800 gm
S100 
E
I / ,^ B B
50 
0 3 ,,, ._ 
0f Qs .^ 'A""
1012 1010 108 106 104 102 100
Time (sec)
(a)
TEMPERATURE (oC):
27
i 29,072
31.145
33,217
35.289
S1I 37,361
39.434
41,506
43.578
45,651
(b)
Figure 2.17 Twodimensional heat flow in multipleemitter bipolar transistors: a)
A comparison of the threedimensional thermal impedance model to a
twodimensional model for W = 1 im, D = 0.5 pim and H = 0.5 grm;
b) the finiteelement model simulated with ANSYS for P = 500 pW.
15 r ,
OZs: 2D ANSYS Al A A AA
[ OZcl: 2D ANSYS
UA
o AZs+Zc2: 2D ANSYS 0 0 0 00
10  Zs: Model
S  ZCI: Model
a  Zs+Zc2: Model
E 5
0 /
1012 1010 108 106 104 102
Time (sec)
(a)
8
_ _0_ _A A_ A4a
OZs: 2D ANSYS O O O O GD
oZci: 2D ANSYS
o 6 AZs+Zc2: 2D ANSYS
S Zs: Model
T  Zci: Model
S ZS+Zc2: Model
Q 4
r/
0 ii
1012 10 0 10 106 104 102
Time (sec)
(b)
Figure 2.18 The transient thermal impedance simulated with ANSYS and
calculated with the bulk, multipleemitter model for L = 500 pm and
S = 1 (im: a) W= 1 (im, D =0.2 pLm, H =0.3 im; b) W = 3 pm,
D = 0.5 tim, H = 0.5 pm.
2.6 Summary
A thermal impedance model for bulk singleemitter BJT/HBT's was
presented and then extended for devices with multiple emitter fingers. The model
was shown to agree reasonably well with threedimensional finiteelement
simulations and measurements of junctionisolated devices. The effects of
interconnect metallization and advanced isolation technologies on the thermal
impedance were investigated; a simple model for the thermal impedance of the
emitter interconnect was demonstrated. The results suggest that the model can be
expected to provide reasonable predictions for the thermal impedance of junction
isolated devices. However, for highlyscaled devices, the effects of advanced
isolation can be significant and the accuracy of the model will decline. Methods for
modeling the effects of isolation structures are proposed in Chapter Eight.
CHAPTER 3
A CIRCUIT MODEL FOR THERMAL COUPLING AND A LUMPED
ELECTROTHERMAL MODEL FOR BULK MULTIPLEEMITTER BIPOLAR
TRANSISTORS
3.1 Introduction
Due to increased interest in the role of thermal effects in device and circuit
operation, especially for silicononinsulator (SOI) and heterojunction technologies,
circuit simulators and compact device models have been modified to account for the
dynamic temperature response within a device [McA92, Fox93b, Fos95]. Most of the
implementations have been applied to the case of selfheating, where a device's
effective operating temperature (EOT) depends on its power dissipation only. In
many circuits and some devices, such as multipleemitter bipolar transistors, a
number of devices can operate in close proximity. Under such conditions, the EOT
of a device is no longer determined solely by its own power dissipation but also
depends on the operation of its neighbors. Therefore, not only must circuit simulators
(and compact device models) be able to model dynamic selfheating, they must also
be able to model the dynamic thermal coupling between individual devices or
portions of one device.
An approach for modeling crosschip thermal coupling using a circuit
simulator was described by Fukahori and Gray [Fuk76]. The thermal coupling
between devices in an arbitrary circuit was modeled using a finite difference
technique. The semiconductor substrate was represented by a threedimensional
numerical mesh with equivalent thermal resistances and capacitances. The electrical
elements in the circuit (transistors, etc.) were represented by their standard compact
circuit models. The values for the lumped thermal components were calculated by
discretizing the heat conduction equation using a finite difference approximation. In
[Mar93], a similar approach was presented and applied to the simulation of multiple
emitter HBT's. In this case, twoport theory was used to generate a finite twodimensional
resistance network that represented steadystate heat conduction in the substrate. For both
applications, the resulting circuit admittance matrix contained elements corresponding to
the electrical circuit and also the thermal elements. The NewtonRaphsonlike iteration
scheme of the modified circuit simulators was then used to solve the coupled electrothermal
problem. To simulate both interdevice thermal coupling and selfheating using this
method, a large number of thermal nodes is required; therefore, this approach can
drastically increase simulation time.
Chapter One described a common method for using thermal impedances
to efficiently model selfheating in circuit simulators. A logical progression would
be to expand this method to account for thermal coupling between devices. Such an
approach can provide a more efficient alternative to the seminumerical methods
mentioned above. This technique was applied by Moinian et al. for modeling cross
substrate thermal coupling in bipolar circuits [Moi94], and by Baureis for modeling
multipleemitter HBT's [Bau94]. However, their circuit implementations did not
correctly represent the thermal interactions between (or within) the devices. The
shortcoming of the coupling model used in these works is discussed in this chapter.
A circuit model is then presented which correctly models thermal coupling and is
compatible with the selfheating circuit model described in Chapter One.
Once a valid circuit model for thermal coupling has been developed, it can
be used with the multipleemitter thermal impedance model to perform both steady
state and dynamic electrothermal simulations of multipleemitter BJT/HBT's. The
multipleemitter thermal impedance model expresses the selfheating of an entire
device as the sum of the thermal actions and interactions of the individual emitter
fingers. The thermal model structure requires that a single multipleemitter device be
represented by multiple compact device models. While this configuration allows for
the examination of the EOT of each finger in a device, for devices with a large
number of emitter fingers, the overall electrothermal network can become complex
enough to make moderate to largescale circuit simulations impractical. To make the
multipleemitter electrothermal model more suitable for circuit simulation, its
complexity can be reduced by representing the overall thermal response of the device
by a lumped thermal impedance. The lumped thermal impedance is generated by
applying the measurement approach developed by Zweidinger et al. to the simulation
of the complete electrothermal model [Zwe96]. The thermal impedance extraction
technique is briefly reviewed in this chapter. The lumped model generation
procedure is then described and the results are compared to the complete
electrothermal model.
3.2 A Circuit Model for Thermal Coupling
The EOT of any device in a system of n thermally coupled devices (e.g. a
multipleemitter bipolar transistor with n emitter fingers) can be expressed as
TDEV1(t) = [ATI(t) + AT2(t) + + ATin(t)] +Tamb
TDEV2(t) = [AT21(t) + AT2(t) + + AT2n(t)] +Tamb
TDEVn(t) = [ATnl(t) + ATn2(t) + + AT(t)] + Tamb (3.1)
where ATj(t) = 1 [Zsj P(s)] and ATji(t) = 1 [Zcji Pi(s)]. The impedance Zsj
is the self impedance of device j, and Zcji represents the coupling impedance
between device j and device i. (In general, it is not necessary for Zcji to equal Zcij .)
The modifications described in Chapter One allow circuit simulators to model self
heating; therefore, the EOT of each device in a simulation is calculated by
TDEVj(t) = ATj(t) + Tamb (3.2)
and is independent of its neighbors. The obvious way to expand this technique to
account for interdevice thermal coupling would be to simply tie together the
temperature nodes of individual devices using coupling impedances; this approach
was used by Baureis and Moinian et al. [Bau94, Moi94]. Figure 3.1 shows an
example of such a thermal coupling network for two devices, where
ZC = ZC12 = ZC21. Unfortunately, simple analysis of the circuit in Figure 3.1
shows that it does not correctly model the expression in (3.1). For example, analyzing
TDEV1(t)
? P2(t)
Tamb Tamb
A thermal coupling circuit model for two devices. The temperature
nodes of the two thermally coupled devices are connected using a
thermal coupling impedance.
Figure 3.1
TDEV2(t)
the circuit in the steadystate limit gives the following expression for the EOT of
device 1
Rs I(R + RS2) RslRs2T
TDEV P,+P + Ta m. (3.3)
TDEV (Rc + Rsi + RS2) (Rc + RsI + RS) 2 amb
A similar expression can be derived for the EOT of device 2. The problem with this
network formulation is that when individual temperature nodes are connected
through an impedance path, the entire network becomes distributed among the
coupled devices. The self impedances and coupling impedances, as derived, are not
defined to be distributed elements. In a more simplistic view, the network in
Figure 3.1 does not properly constrain the paths of the respective device power
currents. The powercurrent of a given device is divided between its own self
impedance and the rest of the network. The portion of that device's power flowing
through its neighbor's self impedance has no physical meaning. As a result, the
voltages generated at the temperature nodes do not correspond to the correct device
temperatures.
To develop a correct circuit representation of (3.1) and avoid the
shortcomings of the aforementioned coupling technique, control sources can be
utilized in a thermal coupling network group composed of two subnetworks. Each
device in a group of n thermally coupled devices has its own network group.
Figure 3.2 demonstrates how a thermal coupling network group works. Subnetwork
A attaches directly to the temperature node of device 1. The currentcontrolled
current source (F1) in subnetwork B has unity gain and is controlled by the current
UJ)
TDEV(t)
E12(t)
E13(t)
subnetwork A
Eln(t)
subnetwork B
A new circuit representation of thermal coupling which is compatible
with the selfheating circuit model. Subnetwork A is attached to the
temperature node of a device and represents the total temperature rise
in that device. Subnetwork B is used to calculate the thermal coupling
between devices. The voltagecontrolled voltage sources (E]j)
represent the individual portions of the temperature rise in device 1 due
to the other devices in the circuit. The currentcontrolled current
source (F,) models the power dissipation in device 1.
Fl(t).
Figure 3.2
flowing through the voltage source Vpl in subnetwork A. In this example, Vpl is
also used to set the reference ambient temperature. The voltage drop across each
coupling impedance (Zcil) in subnetwork B corresponds to the portion of the
temperature rise in each device i due to the power dissipation of device 1. The
voltagecontrolled voltage sources in subnetwork A each have unity gain and are
used to couple the voltage drops from each subnetwork B of the other devices, back
to device 1. For example, the value of the voltage source E12 is equivalently
EI2AT12(t), where ZC12 is part of subnetwork B of device 2. Therefore, the
voltage generated at the terminal of subnetwork A corresponds to the EOT of device
1, and is given by the following expression
TDEVI(t) = ATI(t) +ATI2(t) + + ATn(t) +Tamb. (3.4)
Similar expressions can be obtained for the EOT's of the other (n 1) devices in the
circuit since they each have similar thermal networks.
The thermal coupling model is demonstrated by simulating a fivefinger
HBT using a version of SPICE 2G.6 modified to model selfheating [Zwe97]. The
device characteristics are simulated with and without the thermal coupling between
emitter fingers. Figure 3.3 shows the results of the electrothermal simulations. When
accounting for the thermal coupling, the current collapse phenomenon commonly
observed in HBT's can be simulated [Liu93, Sei93, Liu95b]. Figure 3.3b illustrates
how the outer fingers shut down as the middle finger begins to carry all of the current.
The importance of modeling the thermal coupling is established by the fact that the
collapse phenomenon is not reproduced when the simulations only account for self
60
50
E
u 40
t 30
U
2 20
U
CollectorEmitter Voltage, VCE (V)
(a)
40
30
E
u
r
b 20
u
10
U
Figure 3.3
4 6
CollectorEmitter Voltage, VCE (V)
Simulated current characteristics of a fivefinger HBT with
AE = 20 x 2 tm2 for each emitter finger: a) The collector current as a
function of collectoremitter voltage for fixed base currents of 1.0, 2.0
and 3.0 mA; b) the collector current distribution in the device with full
thermal coupling for Ig = 3.0 mA.
  


Full Thermal Coupling
. SelfHeating Only
l ,I ,l iIl
I I I
heating. Multipleemitter devices provide just one application for the thermal
coupling model. It can be used on a larger scale for simulating thermal interactions
within circuits, and it can be used on a smaller scale. By dividing a single device (or
each finger of a device) into multiple subcells, the thermal coupling model could be
used to simulate the temperature distribution within a device and phenomena such as
current constriction [Koe94].
3.3 A Lumped Electrothermal Model for MultipleEmitter BJT/HBT's
Used together with a compact device model of either a BJT or HBT, the
multipleemitter thermal impedance model and the thermal coupling network form a
complete electrothermal model suitable for DC, AC and transient device/circuit
simulation. This type of electrothermal model is generally more efficient for circuit
simulation than either finite difference or finite element techniques; however, it can
be quite complex for devices with a large number of fingers and/or fingers with a
large number of subcells. In such a case, simulating moderate to largesize circuits
could become impractical. The complexity of the electrothermal device model can be
reduced by using a lumped modeling methodology. The measurement technique
described by Zweidinger et al., referred to in this work as basecurrent thermometry,
can extract the thermal impedance of a bipolar transistor using the temperature
dependence of the base current [Zwe96]. By applying this extraction technique to the
simulation of the complete electrothermal device model, a more compact lumped
electrothermal can be produced. The lumped model implicitly contains all the details
of the thermal actions and interactions described by the complete electrothermal
model, but with less complexity.
To present a clear discussion of the lumped electrothermal model
generation methodology, a few definitions and conventions will be established. Due
to the thermal interactions between fingers in a multipleemitter device a lateral
temperature gradient will exist across the device. Therefore, the current distribution
among the fingers may not be uniform since the hotter fingers will carry a larger
amount of current. As power dissipation increases, the lateral temperature gradient
also increases and eventually the device will become unstable and enter either
thermal runaway (BJT's) or current collapse (HBT's). Prior to the onset of thermal
instability, the lateral thermal gradient is small and the current distribution among
the fingers is approximately uniform. When the device reaches the point of thermal
instability, the fingers no longer operate under similar bias conditions and the current
no longer divides evenly among the fingers. Therefore, before a device becomes
thermally unstable, it is defined to be in the uniform operating regime; and, once the
device becomes unstable, it is defined to be in the nonuniform operating regime.
In the uniform operating regime, the EOT of the device varies linearly
with the power and the complete electrothermal model can be represented by a single
lumped device model and lumped thermal impedance, ZTHL. The circuit
representation for the uniform lumped model is shown in Figure 3.4a; the emitter
area of the lumped device model is equal to the total emitter area of the multiple
emitter device. As a device becomes thermally unstable the cooler fingers begin to
turn off, leaving the hottest finger to conduct all of the current; the temperature
Tamb
Tamb
Circuit representations of the lumped multipleemitter BJT/HBT
electrothermal model: a) For the uniform operating regime; b) for the
nonuniform operating regime.
Figure 3.4
power relation becomes nonlinear and the uniform lumped model will not accurately
model the device characteristics. To model this shutdown mechanism, the
nonuniform lumped model, which is shown in Figure 3.4b, uses two lumped device
models and four lumped thermal impedances to represent the entire device. Device
QIF is used to represent the hottest emitter finger. In a device with an odd number of
fingers, the hottest finger will be the middle finger. If a device has an even number
of emitter fingers, due to process variation, the hottest finger will be one of the inner
most fingers. For consistency, in either case the hottest finger will be referred to as
the middle finger. The other device model, QoF, represents the remaining outer
emitter fingers. The emitter area of QIF is equal to that of a single emitter finger and
the emitter area of QOF is equivalent to the sum of the emitter areas of the outer
fingers. The lumped thermal impedances ZSg and Zso model the self impedances of
the middle finger and the outer fingers, respectively. In the case of Zso, the
impedance represents the effective temperature rise in the lumped outer fingers due
only to their power dissipation. The lumped coupling impedance Zclo models the
temperature rise in the middle finger due to the power dissipation in the lumped outer
fingers. The reciprocal coupling impedance Zco1, corresponds to the effective
temperature rise in the lumped outer fingers due to the power generation of the
middle finger.
Thermally triggered instability in bipolar devices can lead to circuit
failure and even catastrophic device failure. Typically, this region of operation is
avoided in circuit design. Therefore, in most cases, the uniform lumped model should
be appropriate for most applications. However, if the effects of thermal instability on
device/circuit operation need to be investigated the nonuniform model should be
used.
3.3.1 A Review of BaseCurrent Thermometry
Basecurrent thermometry uses the base current as a thermometer to
extract the thermal impedance of a bipolar transistor [Zwe96]. The technique was
developed for measurementbased extraction but can be applied to the simulation of
compact device models as long as the models' temperature dependence are
physically valid.
The first step of the procedure is to determine the dependence of the base
current on temperature. The response of the base current to changes in temperature
is represented by the fractional temperature coefficient, defined as
TCF(I) I (3.5)
By biasing a device in the commonemitter configuration (avoiding impact
ionization), and separately varying the collector voltage and the ambient
temperature, the thermal resistance of the device can be extracted Since the base
collector conductance is typically negligible, any changes in the base current during
the measurements are due solely to the change in operating temperature. Therefore,
once the selfheating effects are accounted for, the fractional temperature coefficient
can be determined from the measured base current variations.
The second step of the procedure is to extract the transient thermal
impedance. The collector and base currents of the device are monitored for a step in
the collector voltage. The transient change in temperature can be expressed as
IB(t) IB(0)
AT(t) = (3.6)
IBTCF(IB)
where Ig is the median value of the base current for the transient. The temperature
change is then normalized by the magnitude of the power step, giving the following
equation for the thermal impedance
ZTH(t) AT(t) (3.7)
AP
3.3.2 Generation of the Lumped Electrothermal Model
The first step in the lumped model generation is to extract the temperature
coefficient of the base current by performing DC SPICE simulations at different
ambient temperatures. The .TEMP control card is used to set the ambient
temperature; temperature steps between 4 and 10 degrees are sufficient, where a
geometric mean can be used to average TCF(IB) over temperature to correct for
nonlinearities. The base voltage should be selected for the desired operating point
and for each temperature setting, the collector voltage should be swept over a range
in the forward active region. The range of collector voltages should be large enough
to produce a linear increase in base current. Examples of the resulting base current
characteristics are shown in Figure 3.5. The base and collector current values should
