Group Title: Department of Computer and Information Science and Engineering Technical Reports
Title: Planar topological routing
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Title: Planar topological routing
Series Title: Department of Computer and Information Science and Engineering Technical Reports
Physical Description: Book
Language: English
Creator: Thanvantri, Venkat
Lim, Andrew
Sahni, Sartaj
Affiliation: University of Florida
University of Florida
University of Florida
Publisher: Department of Computer and Information Science and Engineering, University of Florida
Place of Publication: Gainesville, Fla.
Copyright Date: 1996
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Planar Topological Routing *


Andrew Limt


Venkat Thanvantrit


Sartaj Sahnin


Abstract


We develop a simple linear time algorithm to determine if a collection of two-pin
nets can be routed, topologically, in a plane (i.e. single layer). Experiments indicate
that this algorithm is faster than the linear time algorithm of Marek-Sadowska and
Tarng [1]. Topological routability testing of a collection of multi-pin nets is shown to
be equivalent to planarity testing and a simple linear time algorithm is developed for
the case when the collection of modules remains connected following the deletion of all
nets with more than two pins.


Keywords and Phrases
single layer topological routing

















*This research was supported in part by the National Science Foundation under the grant MIP 91-03379
tInformation Technology Institute, National Computer Board, 71 Science Park Drive, Singapore 0511,
Republic of Singapore.
'Department of Computer and Information Sciences, University of Florida, Gainesville, FL 32611, U.S.A.

Department of Computer and Information Sciences, University of Florida, Gainesville, FL 32611, U.S.A.





















(a) Planar Routable (b) A non planar routable example


Figure 1: A planar routable and a non planar routable case



1 Introduction


The problem of routing two-pin nets on a single layer has been studied previous by several
researchers. The river routing and switch box routing problems are special cases of this.
Efficient algorithms for these can be found in [2, 3, 4, 5, 6, 7, 8, 9, 10, 11]. In this paper,
we are concerned with the problem of routing (topologically) a collection of two-pin nets
in a single layer or plane. We refer to this problem as the TPR problem. The input to
the problem is a two dimensional routing surface with a collection of modules placed in it
(Figure l(a)). We assume that no two modules touch. There are pins on the periphery of the
modules. Pins with the same number define a net and are to be joined by an interconnect
or wire. In topological routing, we are concerned with defining wire paths. However, no
underlying grid is assumed and there is no minimum wire separation requirement. Thus
wire paths can take any planar shape and may run arbitrarily close to each other. Wires
are not permitted to intersect or run over modules. In Figure l(a), the broken lines indicate
wire paths. The routing instance (RI) of Figure l(a) is topologically routable in a single
layer while that of Figure l(b) is not. The TPR problem for RIs in which all modules lie on
the boundary of the routing region (or more precisely all pins are on the boundary of the
region) was studied in [1, 2, 8]. A simple linear time algorithm for this version of the TPR
problem was developed in these papers For the case in which none of the modules are on
the boundary, Pinter [8] has -i--.-. -I.1 using the linear time planarity testing algorithm of
Hopcroft and Tarjan [12]. His algorithm is quite complex. Marek-Sadowska and Tarng [1]
have considered the TPR problem and several variants which include flippable modules


. . ... . .. .



. . ....
223 I


L1 T


2 - -- - -- ---- ----
3-.< . 4 "' *.
[-7 -
1 2 4 .. . .. ,









and multi-terminal nets. They develop a linear time algorithm for TPR which is based on
module merging. In this paper, we develop, in section 3, another linear time algorithm for
the general TPR problem that is almost as simple as the one of [1, 2, 8] for the restricted
TPR problem. Experimental results presented in section 5 indicate that our algorithm is
considerably faster than the TPR algorithm of [1] particularly if the routing instance is
not planar routable. For the case of multi-pin nets, we show, in section 4, that testing
for topological routability is equivalent to graph planarity testing and that finding the
maximum number of nets that is topologically routable is NP-Complete. We also extend
our two-pin algorithm to handle multi-pin instances in which the modules remain connected
following the deletion of all nets with more than two pins.



2 Preliminaries


To simplify matters, we shall assume that TPR RIs that have modules on the boundary
(Figure 2(a)) have been augmented by a set of nets that are required to be routed on the
boundary and that this routing together with the module boundaries enclose the routing re-
gion (Figure 2(b)). This augmentation may require the addition of corner modules (A, B, C
of Figure 2(b)). This assumption is needed so that our algorithm can account for the con-
straint that one cannot route around a boundary module but can route around all other
modules.

A pin -.,i.,' ,l P = pp2 ...pk, is a sequence of pins on the boundary of a module.
pi ... pk appear in this order when the module is traversed counter-clockwise beginning at pi.
Some of the pin segments of the modules of Figure 3 are: abcde and gjkH of module 1; MLK
and LKJGf of module 3; and AiF of module 2. Let last(P) and first(P), respectively,
denote the last and first pins of segment P. Let net(pi) denote the net associated with pin
pi. Note that two pins pi and pj are to be connected by a wire iff net(pi) = net(pj). A curve,
C = PIP2...P is a sequence of pin segments such that net(last(Pi)) = net(first(P+i+)),
1 < i < j. A curve, C = PIP2 ... Pj, is a closed curve iff net(last(Pj)) = net(first(P1)). In
Figure 3, net(pi) is the lowercase letter corresponding to pi. So, net(h) = net(H) = h. Some
of the curves of Figure 3 are Ih Habcdeg Gf FEDCBAi, j JGfM mlh, edcba ABCDE
and ABC cdeg GfM. IhHabcdeg Gf FEDCBAi and edcba ABCDE are closed curves.
With any curve C = PP2 ... Pj, we associate j 1 (j in case C is closed) wires. These, re-
spectively, connect the pins last(Pi) and first(Pi+l), 1 < i < j (and last(Pj) and first(P1)
in case of a closed curve). Note that the curves, closed curves, and wires associated with any















A 1 C



2





3 4
B


77 a


e e


(b) Augmented RI

Figure 2: Augmentation


Figure 3: An example to illustrate some terminology


(a) RI


a a


g g




















and b


Figure 4: Two possibilities to connect a and b


RI depend only on the modules and the net to pin assignments. These are not a function
of the layout of any of the wires.

For any closed curve C = PP2 ...Pj we define the following:


module(Pi)
pins(module(Pi))
pins(Pi)
pins(C)
ext pins(C)


... module corresponding to pin segment Pi
... set of all pins on module module(Pi)
... set of all pins on segment Pi
... set of all pins on curve C = U =l pins(Pi)
.. = pins(module(Pi)) pins(C)


Note, it is possible that module(Pi) = module(Pj), for i f j.

Lemma 1 : Let I be an RI that contains a closed curve C with respect to which there
are two pins a E pins(C) and b E ext_pins(C) such that net(a) = net(b). I is not planar
routable.

Proof : Figure 4 shows two possibilities. It should be clear that no matter how the wires



























Figure 5: Another not planar routable situation


of C and the wire (a, b) are laid out, there must be an intersection between two of these.
D

Lemma 2 : Let I be an RI that contains a closed curve C = P,P2,.. .,Pj and another
curve R = RR2 ... Rk such that module(Ri) = module(Pd) for some d, 1 < d < j and
first(Ri) E extpins(C) (see Figure 5). Assume that there exist two pins a and b such that
a E pins(C), b E extpins(C) Upins(R), and net(a) = net(b). I is not planar routable.

Proof : Follows from Lemma 1. D

Two modules are connected iff there is a curve C = P1P2 ... P such that both modules
are in Uj= n module(Pi). A connected component (or simply component) is a maximal set of
modules that are pairwise connected. It is easy to see that the connected components of an
RI are disjoint. A boundary component is a connected component that includes at least one
boundary module. Note that an RI with no boundary modules has no boundary component
while an RI with at least one boundary module has exactly one boundary component (this
is because RIs with boundary components have been augmented as in Figure 2(b)).

Lemma 3 : An RI is './'.,,1.'., .1ll.i routable iff its components are (independently) topolog-
ically routable.

Proof : It is easy to see that if the RI is topologically routable then each of its components
is topologically routable. Assume that each component is topologically routable. Order the












D O D

o o O

0 0 0 0 0
(a)O Module E Ka (b) Spanning tree
O Module ( Ka






(c) Envelope


Figure 6: Constructing the envelope of a component


components of the RI so that the boundary component is first. The remaining components
are in arbitrary order. Let the components in this order be K1 ,2, ., Kk. If k = 1, then
nothing is to be proved. So, assume K > 1. We shall show how to construct a topological
routing for K1, K2..., K, from a topological routing for K1,..., K,_1 and K,, 2 < a < k.
First since a > 1, K, is not a boundary component. So, it is possible to surround it by a
closed non self intersecting line such that the region enclosed by this line includes exactly
those modules that are in K, and no module touches the line. The region enclosed by
this closed line has the property that any two points in the enclosed region can be joined
by a line (not necessarily straight) that lies wholly within the region. We refer to the
surrounding line as the envelope of K,. One way to obtain an envelope of K, is to first
construct a set of IKa 1 (QKa, is the number of modules in K,) lines (not necessarily
straight) so that modules of K, together with these lines form a connected component in
the graph theoretic sense (see Figure 6). These lines do not touch or cross any of the
modules of RI. This construction can be done as every pair of modules of an RI can be
can be connected by such a line. The lines and modules define a spanning tree for K,.
By fattening the lines as in Figure 6(c), the envelope is obtained. It is easy to see that
























(a) Intersections (b) Re-routing


Figure 7: Re-routing to free independent component



if K, is topologically routable, then it is topologically routable with the defined envelope.
So, use such a topological routing for K,. When this routing is embedded into the routing
for K1,..., K, some of the topologically routed wires of Ki,..., K, may intersect (or
touch) the envelope of K,. However, none of these wires originate or terminate in the
envelope of K,. So, these can be rerouted following the contour of the envelope (Figure 7).


As a result of Lemma 3, we need concern ourselves only with the case when the RI has
a single component.



3 The Algorithm


Our algorithm to obtain a topological routing of a component uses Lemmas 1 and 2 to
detect infeasibility. The algorithm is given in Figure 8. As stated, it only produces an
ordering of the wires such that when the wires are topologically routed, one at a time, in
this order, then there is always a path between the two end points of the wire currently
being routed such that this path does not intersect previously routed wires or cross any of
the modules. This is sufficient to obtain the actual topological routing.

Our algorithm employs two stacks A and B. Stack A maintains a pin sequence that
defines a curve of the RI. Stack B is used to retain pins that define closed curves with



















Algorithm TestingPlanar_Routability

Step 1: Let m be any module of the component and let p be any pin of m.

Step 2: Examine the pins of m in counterclockwise order beginning at pin p. When a pin
q is being examined compare net(q) and net(r) where r is the pin (if any) at the top
of stack A. If stack A is empty or net(q) f net(r) then add q and the remaining pins
of m to the top of stack A. Otherwise output (q, r) and unstack r from A.

Step 3: If both stack A and B are empty, then terminate.

Step 4: Let r be the pin at the top of stack A. Let s be the pin such that net(r) = net(s).

(a) If s is at the top of the stack B, then [output (r, s); unstack r from A and s
from B; go to start of Step 3].

(b) If s is in stack B but not at the top, then [output("The RI is not planar
routable"). Terminate].

(c) If s is in stack A, then unstackk r from A; add r to stack B; go to the start of
Step 4].

(d) If s is in neither of the stacks then [ set p to s; let m be the module containing
s; go to Step 2].


Figure 8: Topological routing.



























(a)Example RI (b)A possible topological routing


Figure 9: Example RI



respect to a (sub) curve on stack A. We describe the working of the algorithm with the aid
of an example (Figure 9(a)). There are four modules 1 4 and 16 pins a h and A H.
net(p) = p if p is a lowercase letter and net(p) = lowercase(p) if p is an uppercase letter.
Suppose we begin in step 1 with m = 3 and p = B. Then in step 2, BAFEC get stacked, in
that order on to stack A. This corresponds to the curve of Figure 10(a). Pin c is in neither
of the stacks and in step 4(d), we set m = 1, p = c, and go to step 2. In this step, the
wires Cc, Ee and Ff are output for routing. The pins g and D are put on the top of stack
A. The curve traced so far is shown in Figure 10(b). The routed wires are also shown as a
curve. Note that these wires have to be routed using the procedure find_route, otherwise
they can enclose a non-empty region. The curve is extended to module 2 and stack A has
configuration BAghb. The wire Dd is output for routing. The curve has the form as shown
is Figure 10(c). The curve cannot be extended further as both end points of wire Bb are on
the stack. This means that we have detected a closed curve of the RI. The detected curve is
that of Figure 10(c). We defer the routing of Bb until we have verified Lemmas 1 and 2 for
this closed curve. The deferment also ensures that the current topological routing does not
contain a closed line. If Bb were routed now, then the wires Bb, Cc, and Dd together with
the boundaries of modules 1, 2, and 3 would define a closed line that encloses a non-empty
region. This could result in future routing problems as there would be no path between
a point in the region and one that is outside the region. For example, if the routing of


g e
Dc




I H
b -I --












B-A-F-E-C B-A-F-E-C-c-e-f-g-D



(a) (b)

B-A-F-E-C-c-e-f-g-D-d-h-b
B-A-F-E-C-c-e-f-g-D-d-h-b
\ H-- a

(c) (d)


Figure 10: Illustration of the routing sequence



Figure 11 is used, then there is no path between a and A as a is in the enclosed (shaded)
region while A is outside of it. The routing of Bb is deferred by saving b on stack B. The
curve of stack A is extended to module 4 via the wire hH. Wire hH is output for routing.
Also the wires gG and Aa are output for routing. Stack A contains the pin B and stack B
contains the pin b. The curve is shown in Figure 10(d). Finally, the wire Bb is output for
routing and the since both the stacks are empty, the algorithm terminates successfully in
step 3.

The routing order is Cc, Ee, Ff, Dd, hH, gG, Aa and Bb. Let us try this out on our
example. We see that no matter how Cc is routed there will remain a routing path for
the remaining wires. The routing of Dd and Hh cannot create any enclosed regions and
so cannot affect the feasibility of future routes. When Ee and Ff are routed, an enclosed
region can be formed. Hence these wires have to be routed using the procedure find_route
of Figure 13, otherwise they can enclose a non-empty region. The topological routed RI
can be found in figure Figure 9(b).


Lemma 4 : If 1/.c",'l11,i Testing_Planar_Routability terminates in step 3, then the input
instance is r',,,,,1.* '../ .11 routable.


Proof : We shall show that the algorithm Testing_Planar_Routability maintains the fol-
lowing invariant:

There is a topological routing of all wires output so far such that each remaining wire is








































Figure 11: Trapped terminal and module


Sx


m V--


-y ~ ~


Figure 12: To illustrate conflict


-y ~ ~










(individually) topologically routable.


This is true when we start as at this time, no wires have been output and for each wire,
there is a routing path between its two pins. Assume that the invariant holds just before
some wire (r, s) is output. We shall show the invariant holds after this wire is output for
routing. Wire (r, s) satisfies exactly one of the following:

(a) It is output in step 2, r is a pin that was on stack A, s is the first pin to be reached
on its module.

(b) It is output in step 2, r was on stack A, s is not the first pin to be reached on its
module.

(c) It is output in step 4(a). At the time of output, r was at the top of stack A and s at
the top of stack B.

If we are in case (a), then since module(s) is reached for the first time, no matter how
wire (r, s) is routed at this time no new enclosed regions are formed. Hence all remaining
wires remain routable.

The proofs for cases (b) and (c) are similar. We consider case (c) only. ,From the
algorithm it follows that at some time prior to the output of (r, s), both r and s were on
stack A, s was at the top of A and about to be moved to stack B. The pins on stack A
beginning with r and ending at s define a closed curve C (as net(r) = net(s)). Let these
pins be from modules module(r) = M1, M2,..., = module(s) (in this order moving up
stack A). Let p be any pin in pins(C) {r, s} and let q be such that net(p) = net(q).
We may assume that either q E pins(C) or module(q) is unvisited at the time s is moved
from stack A to stack B. Note that if this is not the case, then q is in stack A and below
r at this time. From the working of the algorithm it follows that when r reaches the top
of stack A (as it does by the assumption of (r, s) being output from step 4(a)), p must be
on stack B and above A. So, the algorithm should have terminated unsuccessfully in step
4(b), contradicting the assumption of termination in step 3.

Let U be the set of unvisited modules at the time s is transferred from stack A to stack
B. By extending our previous argument, we see that the set N of modules visited by the
algorithm between the time s is transferred from stack A to stack B and the time (r, s) is
output is such that

(1) N C U modules(C).









Algorithm find_route(r, s)
begin
currentpin := s; I := clockwisepin(currentpin);
while (1 r) do
begin
Step 1: Route clockwise from currentpin to I following the module boundary
Step 2: currentpin = q such that net(q) = net(1)
Step 3: Continue the route from I to currentpin following the existing route
closely
Step 4: 1 = clockwisepin(currentpin)
end
Complete the route from currentpin to I = r following the module boundary
end

Figure 13: Algorithm to find routing path between pins r and s


(2) All pins in (N n U) U (pins(C) {r, s}) have been output for routing.

(3) All pins reached from N n modules(C) are in pins(C) U pins(N n U).


We now claim that algorithm find_route(r, s) obtains a topological routing of the wire
(r, s) that preserves the invariant. To establish this, we need to show that

(A) The algorithm actually finds the route between r and s.

(B) The region enclosed by this route and the curve C contains no pins that have not
been routed to.


To prove (A), we need to show:


(Al) For each value of currentpin, clockwisepin(currentpin) (i.e., the pin clockwise from
currentpin) is defined and different from currentpin.

(A2) The net (1, currentpin) in step 3 of Figure 13 is already routed, so it is possible to
follow this route.

(A3) currentpin does not assume the same value twice.









For (Al), we simply assume that each module has atleast two pins. Modules with a single
pin may be ignored initially and routed to after the remaining routes have been made. For
(A2), let the value of the currentpin and I at the start of the i'th iteration of the while loop
be ci and 1i, respectively. We note that cl = s and 11 E pins(C). If li E pins(C) Upins(N n
U), then from conditions (2) and (3), it follows that ci+l E pins(C) U pins(N n U) and wire
(li, ci+l) has been routed. Suppose there is an li pins(C) U pins(N n U). Let lj be the
first such 1i. Since j > 1, lj_k and cj-k+1 are in pins(C) U pins(N n U) for k > 1. Since cj
and jl are on the same module, it follows that module(cj) N. So, Ij E ext_pins(C) and
cj E pins(C). From the way algorithm Testing_Planar_Routability works, it follows that
(I_1, cj) is a segment of the curve C and that curve C when oriented from r to s, first
reaches Iy_1 and then cy via wire (Ijy_,cy). Hence jly_ E pins(C). Since Ij2 E pins(C)
(by assumption on j), cj_l E pins(C) U pins(N n U). Further, since cj_l is a module of C,
cyl E pins(C). Now, since (lj_1, cj) is a segment of C and cyj_ is one pin clockwise from
ly_l and a pin of C, it follows that (j-2, Cj-1) is a segment of C oriented from lj-2 to Cj-1.
Continuing in this way, we conclude that (11, c2) is a segment of C oriented from 11 to c2.
However, we know that when C is oriented from r to s there is only one wire segment that
includes a pin of module(s) and this is oriented to module(s). That is, the orientation is c2
to 11, a contradiction. Hence, there is no li pins(C) U pins(N n U). Also, no li E {r, s}
at the start of a while loop iteration. ,From condition (2), it follows that all encountered
(li, ci+l) have been routed.

For (A3), suppose that ci = cy for some i and j, i < j. Since (li-1, ci) and (lyj_, cj) are
two-pin nets, it follows that li-1 = lyl. Now, since ci- and cy_l are, respectively, one pin
counterclockwise from 1i_1 and ly_1, it follows that ci- = cy_l. Continuing in this way,
we see that s = cl = c_-i+l. This implies that net (ly-i, cy_-i+) = (r, s) has already been
routed. But, it has not. So, no ci is repeated.

(B) follows from the fact that find_route reaches only pins in pins(C) U pins(N n U),
condition (3) and the fact that find_route follows existing routes without enclosing any new
pins. O

Lemma 5 : If the li,,"I'l1,i Testing_Planar_Routability (given in Figure 8) terminates in
step 4(b), the RI is not planar routable.

Proof : If the algorithm terminates in step 4(b), then let r and s be as in step 4. r is
at the top of stack A and s is in stack B but not at the top. Let x be at the top of stack
B and let y be the pin such that net(y) = net(x). y must currently be on stack A as x










can be put on stack B (see step 4(c)) only if y is on stack A. When one pin of a net is in
stack A and the other in stack B, the pins can leave the stacks together (step 4(a)) or not
at all. Since x is on stack B at termination, y must still be on stack A and hence must be
lower than r (as r is at the top). So, there is a curve y ... r in the RI. Furthermore, curves
y...r...s and y...r...x must exist as this is the only way s and x can get to stack A
and then to stack B. Figure 12(a) shows an example curve y... r... s. This figure assumes
that module(s) $ module(r). The proof for the case module(s) = module(r) is similar.
Let m be the module at which the curves y... r... s and y... r... x diverge (Figure 12(b)).
Note that m may be module(r) or a latermodule on the curve y... r... s. Let u be the pin
of m that is the last pin of m on curve y...r... s and let v be the corresponding pin for
y...r...x. Since all nets are two-pin nets, u f v. Since x is above s in stack B, v must
be on the curve y...r...s. The curve C = y...r...v...x is a closed curve. We see that
r E pins(C), and s E ext_pins(C), and net(s) = net(r). So, s and r satisfy the conditions
of Lemma 2 and the RI is not planar routable. O


Theorem 1 : The ., ,ii Testing_Planar_Routability (given in Figure 8) is correct.


Proof : Follows from Lemmas 4 and 5. O

The algorithm of Figure 8 is easily implemented to have complexity of O(n) where n
is the total number of pins. For this we need to use an array status[l..n] to maintain the
current status (i.e., on stack A, on stack B, on neither) of each pin.



4 Topological Routability of Multi-pin Nets


We shall refer to the extension of Testing_Planar_Routability or TPR to the case where some
or all nets may have more than two pins as MTPR. The MTPR problem may be solved in
linear time by mapping MTPR instances into graph planarity instances [3, 1]. However, the
known linear time algorithms [12] for graph planarity are complex and one is motivated to
explore the possibility that simpler algorithms exist for MTPR (just as they do for TPR).
Unfortunately, this is not the case. We show, in Theorem 2, that any algorithm for MTPR
can be used to test graph planarity with no increase in complexity. In Theorem 3, we show
that the problem of determining the maximum number of topologically routable nets of
an MTPR instance is NP-hard. Theorem 2 motivates the quest for a simple linear time
algorithm for a restricted version of MTPR. We show that the algorithm of Figure 8 may





























Figure 14: Realization of a planar net using one Steiner point



be extended to handle MTPR instances in which every pair of modules remains connected
(though not necessarily by a net) when all nets other than two-pin nets are eliminated.


Theorem 2 : Let I be an instance of graph planarity. I can be ti ,-f ,, ...i in linear time,
into an instance I' of MTPR such that I is planar iff I' is ',.,,,1,*..',. 11.1 routable.


Proof : ;From the constructions of [3, 1], it follows that the topological routability of
an MTPR instance does not depend on the specific placement of the modules. Hence,
in constructing I', we need not specify the module placement. I' is obtained from I by
replacing each edge (i,j), i < j of I by a module M ; with two pins I1' and 1I2. The nets
of I' are Ni = {1 i < j} U {MJ j < i}, 1 < i < n where n is the number of vertices in
I.

If I' is planar routable, then each net, NV, has a planar realization that does not contact
the realization of any other net. This realization connects the pins of N, together, possibly
using some Steiner points (see Figure 14(a)).

If N, is a two-pin net, then introduce vertex vi anywhere on the wire connecting the two
pins of N,. If N, has more than two pins, then by using the transformations of Figure 14(b),
we can reduce the number of Steiner points to one and also ensure that each pin of Ni
has exactly one wire connected to it. These transformations preserve the planarity of the
routing. The sole surviving Steiner point is replaced by the vertex vi.










Now each wire that connects to vi connects to module [ ; or Mji. This module has
another wire connecting to vertex j. Remove UI ; (or Mji) and join the ends of these two
wires together by a line joining the terminals of M ; (or Mji). We now have a planar
embedding of I.

If I is planar, then start with its planar embedding. Replace vi by a Steiner point;
place M ; anywhere on the embedding of edge (i,j), i < j; split the edge (i,j) at M ;
and connecting the two ends (at the split point) to the terminals of M ;. This yields a
topological routing of I'.

Hence, I is planar iff I' is topologically routable. O

Let MTPRmax be the problem of determining whether or not k of the nets of an MTPR
instance are topologically routable. To show that MTPRmax is NP-complete, we use the
following problem that is known to be NP-complete [13].

Planar Subgraph: Given Graph G = (V, E), and a positive integer k subset V' C V with I V' I> k such that the subgraph induced by the V' vertices is planar?


Theorem 3 : MTPRmax is NP-complete.


Proof : It is easy to see that MTPRmax is in NP. Also, from an instance I of the planar
subgraph problem, we can construct an instance I' of MTPRmax by replacing edges by
modules as in Theorem 2. It is easy to see that I' has k nets that are topologically routable
iff I has an induced subgraph with k vertices that is planar. O

Any instance I of MTPR may be transformed into an instance I' of TPR which includes
unordered modules (i.e., modules whose terminals may be rearranged at will). I' has the
property that there is an arrangement of terminals for each of the unordered modules which
results in I' being topologically routable iff I is topologically routable. To obtain I' from
I, for each multipin net Ni of size k, k > 2, we introduce an unordered module UMi with
k pins. The net Ni is replaced by k two-pin nets, one pin of each of these nets is an original
pin of Ni and the other a pin of UMi. Since planar routability is not affected by module
placement, UMi may be placed anywhere in the routing region. An example is given in
Figure 15.


Theorem 4 : The pins of each unordered module of I' can be ordered so that the resulting
instance of TPR is '/.i,,1,, "' .11 routable iff I is '/.,,1,, i/.' .11 routable.



























(a) A multipin net


(b) Two pin nets


Figure 15: Transformation from multipin to two-pin nets



Proof : If the pins of the UMi's can be so ordered, then a topological routing of I is easily
obtained from the topological routing of I' (simply replace each UMi by a Steiner point). If
I is topologically routable, then using transformations similar to those in Figure 15(b), we
may transform the topological routing into one in which each multipin net Ni of size k > 2
is routed using exactly one Steiner point. This Steiner point is replaced by module UMi
and the pin ordering is determined by the topological routing around the Steiner point. O

If we knew which terminal orderings of the UMi's to use, we could simply convert each
UMi to an ordered module and run the TPR algorithm. Unfortunately, we do not know
this. Therefore we need to modify algorithm Testing_Planar_Routability so as to properly
handle unordered modules. As in section 3, we may assume that I is a single component. For
our modification to work, we assume that I remains a single component when all multipin
nets Ni of size k > 2 are eliminated from I. The modified algorithm MTPR is given in
Figure 16.

The working of the MTPR algorithm is explained using the example in Figure 17. There
are five modules 1-5 and there are seven nets out of which six are two-pin nets. The seventh
is a four-pin net. The pins of the four-pin net are w, z, y and z. In step 1 of the algorithm of
Figure 16, we replace the multipin net of size four with a new unordered module UM1 which
has four pins. Suppose we begin in step 2 with m = 5 and p = A. Then in step 3, ACxB












Algorithm MTPR


Step 1: For each multipin net NT of size k > 2, introduce a new unordered module UMi
with k pins and replace NT by k two terminal nets as described earlier.

Step 2: Let m be any ordered module and let p be any pin of m which corresponds to an
original two-pin net.

Step 3: Examine the pins of m in counterclockwise order beginning at pin p. When a pin
q is being examined compare net(q) and net(r) where r is the pin (if any) at the top
of stack A. If stack A is empty or net(q) f net(r) then add q and the remaining pins
of m to the top of stack A. Otherwise output (q, r) and unstack r from A.

Step 4: If both stacks A and B are empty, then terminate.

Step 5: Let r be the pin at the top of stack A. Let s be the pin such that net(r) = net(s).
If module(s) is an unordered module then go to step 6.

(a) If s is at the top of the stack B, then [output (r, s); unstack r from A and s
from B; go to start of Step 4].
(b) If s is in stack B but not at the top, then [output("The RI is not planar
routable"). Terminate].
(c) If s is in stack A, then unstackk r from A; add r to stack B; go to the start of
Step 5].
(d) If s is in neither of the stacks then [ set p to s; let m be the module containing
s; go to Step 3].

Step 6:

(a) If module(s) is at the top of stack B, then [output (r, s); unstack r from A;
mark pin s as having been seen. If all pins of module(s) have been marked then
unstack module(s) from B; go to start of step 4]
(b) If modules) is on B but not at the top, then [output("The RI is not planar
routable"). Terminate].
(c) If module(s) is not in stack B, then unstackk r from A; mark pin s as having
been seen; add module(s) to the top of stack B; go to start of step 5].


Figure 16: Topological routing of multipin net for restricted version





























Figure 17: Example RI with a four pin net


get stacked, in that order, on to stack A. This corresponds to the curve of Figure 18(a).
The top of stack A now has pin B, and the curve on stack A is extended by adding pins
from module 1 to stack A. In this process, the wire Bb is output for routing. This situation
is depicted in Figure 18(b). Since pin a is at the top of stack A and its mate is below it in
the stack, pin a is moved from stack A to stack B. At the top of stack A, we have a pin of
a four-pin net and since this net is seen for the first time, we add the unordered module to
the top of stack B and mark y as having been seen. We route the wire from pin y to the
unordered module. The pin z, which is below pin y is next routed to the unordered module.
This is done using the procedure find_route of Figure 13. The curve on stack A is extended
by adding pins from module 4. At this time, wire Cc is output for routing. This scenario
is depicted in Figure 18(c). Now, pin z is at the top of stack A. This pin is routed to the
unordered module in step 6(a) of the algorithm. Next, in step 3 the wire dD is output for
routing. Also, pin E is put on the top of stack A. At this point stack A contains pins AfE,
bottom to top in that order. This situation is depicted in Figure 18(d). We set m = 2 and
p = e in step 3 of the algorithm and output wires Ee and fF for routing. The remaining
pin w is put at the top of stack A. In step 6(a) of the algorithm, we mark pin w as seen
and route a wire from this pin to the unordered module. Also, we remove the unordered
module from the top of stack B. This is shown in Figure 18(e). Now, stack A contains
pin A and stack B contains pin a and the wire Aa is output for routing in step 5(a) of the
algorithm. Both the stacks are empty and the algorithm terminates successfully in step 4.













A-C-x-B A-C-x-B-b-y-a

(a) (b)


A- C- B- B -b-y-a A-C- x-B-b -y- a
c f- d- z c-f- D- z
D -E



A- x -B- b --a
c -4- z
D -E- e- F- w


(e)


Figure 18: Illustration of the routing sequence with Multiterminal net



The topologically routed RI can be found in Figure 17.


Lemma 6 : If the .Jii ,ll', MTPR halts in step 4, then the wires are planar routable.


Proof : The proof is very similar to that of Lemma 4. The same invariant holds. When
we put an unordered module on stack B and mark a pin (if that is the first pin marked)
then we connect this pin to the unordered module. See that there is no enclosed region and
the invariant holds true. Now, if we are routing another pin (of multipin net) then the pin
it has to be connected is on the unordered module. So as soon as we reach the unordered
module, the next pin is chosen as the pin it has to be connected to (this also defines the
order of pins in the unordered module). The proofs apply in this case as we have made all
nets two-pin nets. O


Lemma 7 : Let I be an RI that contains a curve C = P1P2 ... Pj. Let R = RR2 ... .Rk and
S = S1S2...Si be two curves such that module(Ri) = module(Pd) for some d, 1 < d < j
and first(Ri) E ext_pins(C) and module(S1) = module(Pe) for some e, 1 < e < j and
first(Si) E pins(C).









Let C be such that first(Pi) and last(Pj) are part of the same net N. Assume that there
exist two pins a and b such that a E pins(C) U pins(S), b E ext_pins(C) U pins(R) and
net(a) = net(b) f N.

I is not planar routable.

Proof : Follows from Lemma 1. O

Lemma 8 : If 1/.,"a'll, MTPR terminates in steps 5(b) or 6(b), the RI is not planar
routable.

Proof : Suppose the algorithm terminates in step 5(b). Let r and s be as in step 5 and
let x be at the top of stack B. Note that r and s define a two-pin net. If x is a two-pin
net, then the RI is not planar routable (see proof of Lemma 4). So assume that x is an
unordered module (note that only pins of two-pin nets and unordered modules get on to
stack B). Module x must have atleast one marked and one unmarked pin. Let C be the
curve defined by the stack A segment from r to s when s was at the top of stack A just prior
to being transferred to stack B. From the working of MTPR, it follows that there is a pin
p E pins(C) from which a path was traced to the multipin net corresponding to module x.
Furthermore, there is atleast one pin a of the multipin net that is on a path from a pin that
is not in pins(C). A possible situation is shown in Figure 19. The conditions of Lemma 7
are satisfied and the RI is not planar routable.

If the algorithm terminates in step 6(b), then r is a pin of a multipin net and module(s)
is an unordered module. Let x be at the top of stack B at the time of termination. Let j
be one of the pins that have already been routed to module(s). Let C be the curve defined
by the stack A segment at the time pin j was output for routing. Let S be the curve or pin
in pins(C) that was used to reach pin x. Let y be such that net(x) = net(y). Since y must
be below r on stack A and r is a net of a multipin net, the path from y to r on stack A
must include a pin in ext_pins(C). By setting a and b of Lemma 7 to x and y respectively,
we see that the conditions of Lemma 7 are satisfied and the RI is unroutable. The proof
for the case x is an unordered module is similar. O



5 Implementation of Two-Pin Algorithm


While the correctness proof for our algorithm is somewhat involved, the algorithm itself is
quite simple and easy to implement. To get good performance we implemented stack A as

































Figure 19: A possible situation where the RI is unroutable


a stack of modules rather than one of pins as described in Section 3. So, when step 2 of
Figure 8 adds q and the remaining pins of m to stack A, we simply add a record of the
type (m, q, 1) where I is the last pin of m to the stack. Also, to get the top pin of stack A,
we look at the top record (m, q, 1). The top pin is 1. To delete this pin, the top record is
changed to (m, q,p(1)) where p(l) is the predecessor of pin I unless q = 1. In the latter case,
the record (m, q, 1) is deleted from the stack. The role of array status needs to be changed
to support this change in stack structure. We now keep a status for a module as well as for
a pin. A module's status reflects whether or not it is in stack A and a pin's status reflects
whether or not it is in stack B.

The algorithm of [1] is a two step algorithm:


Step 1:Merge modules together to obtain an equivalent routing problem in which all pins
are on the periphery of a routing region.

Step 2:Determine the feasibility of the equivalent problem using a single stack scheme.


To implement step 1, we performed a traversal of the modules. Each module was represented
as a singly linked circular list of pins. With this representation, modules can be merged
































Figure 20: Tree-like Connected Circuits



efficiently. By contrast, for the algorithm of Figure 8, modules were represented using
doubly linked circular lists.



6 Experimental Results


We implemented our algorithm for two-pin nets and that of [1] in C and obtained execution
times using both circuits that are routable and those that are not. The routable circuits used
are highly structured ones as shown in Figures 20 and 21 as well as randomly generated
ones. The nonroutable circuits used were obtained by modifying the tree-like circuits of
Figure 20.

The timing results for the routable circuits are shown in Tables 1, 2, and 3, respec-
tively. The times are in milliseconds and the programs were run on a SUN 4 workstation.
on tree-like circuits, the algorithm of [1] took i.".', more time than ours, on average; on
six-way circuits, it took approximately III, more time; and on random circuits, it took
approximately .''. more time.

Our algorithm has a distinct advantage over that of [1] when working with nonroutable

































Figure 21: Six-way Connected Circuits


NP 864 704 1440 6048 6944 2 I'lrs
NM 16 25 49 100 225 400
Our 3.40 2.91 5.53 22.90 27.40 93.30

[1] 5.45 4.36 9.10 37.80 44.90 162.80

NP = Number of pins in the circuit
NM = Number of modules in the circuit
Table 1: Tree-like Connected Circuits




NP 1792 1920 522 .,,2* "'-,., 17396
NM 25 49 100 100 225 400
Our 8.48 10.17 4.20 44.54 53.60 105.40
[1] 11.08 11.93 9.52 55.18 66.25 121.90


Table 2: Six-Way Connected Circuits











NP 92 1472 ~',ll 11776
NM 28 28 28 28
Our 0.91 6.54 12.76 49.95
[1] 0.98 9.18 18.17 78.20


Table 3: Random Circuit


NP ,8 6944 1i;-'
NM 25 225 225
Our 3.70 16.24 30.30
[1] 15.50 45.70 92.50


Table 4: Faster Termination for NonRoutable Circuits



circuits. The algorithm of [1] must complete its step 1 before it can detect infeasibility,
whereas our algorithm can detect infeasibility at any stage. Hence, it is possible for our
algorithm to take much less time than that of [1] when working on such circuits. The results
from three test circuits is given in Table 4. The algorithm of [1] is approximately 3 to 5
times slower than ours.



7 Conclusion


We have developed a relatively simple and fast linear time algorithm to test the planar
topological routability of a collection of two-pin nets. The algorithm is faster than the
linear time algorithm of [1]. We have also shown the equivalence of the multi-pin net
routability problem and the graph planarity problem. This implies that we cannot solve
the multi-pin problem by a simpler algorithm than used for graph planarity. Our simple
two-pin algorithm can be extended to work on routing instances that remain connected
following the elimination of all multi-pin nets. These are the same instances that can be
solved by the specialized algorithm of [1]. We also show that determining the maximum
number of routable nets is NP-hard when some or all of the nets have more than two pins.










References

[1] M. Marek-Sadowska and T. Tarng, "Single-Layer Routing for VLSI: Analysis and Al-
gorithms," IEEE transactions on Computer-Aided D.esign, vol. CAD-2, no. 4, 1',.;

[2] C. Hsu, "General River Routing Algorithm," in AC I\/IEEE De.siqn Automation Con-
ference, pp. 578-583, 1'i'.

[3] C. Leiserson and R. Pinter, "Optimal placement for river routing," SIAM Journal on
Computing, no. 12, pp. 447-462, 1I',.;

[4] A. Lim, S. Cheng, and S. Sahni, "Optimal Joining of Compacted Cells," IEEE Transac-
tions on Computer, accepted in 1991. Extended abstract in 1992 Brown/MIT Advanced
Research in VLSI and Parallel Systems.

[5] A. Mirzaian, I ,-! Routing in VLSI," Journal of Computer and System Sciences,
no. 34, pp. 43-54, 1'1 7.

[6] A. Mirzaian, "A Minimum Separation Algorithm for River Routing with Bounded
Number of Jogs," in International Conference in Computer-Aided D.esign, pp. 10-13,


[7] R. Pinter, "On routing two point nets across a channel," in AC I\/IEEE D.sign, Au-
tomation Conference, pp. .'*'I 'i11_' 1l'-1,

[8] R. Pinter, I!.- i-Routing: Methodology and Analysis," in Third Caltech Conference
on VLSI, March 1',-.;

[9] A. Siegel and D. Dolev, "The separation for general single layer wiring barriers," in
VLSI Systems and Computations, pp. 143-152, 1981.

[10] T. Tuan and S. Hakimi, 1UI-. Routing with Small Number of Jogs," SIAM J. Discrete
Math., vol. 3, no. 4, pp. 585-597, 1990.

[11] T. Tuan and K. Teo, "On River Routing with Minimum Number of Jogs," IEEE
transactions on Computer-Aided Deigqn, vol. 10, no. 2, pp. 270-273, 1991.

[12] John Hopcroft and Robert Tarjan, I.11 i ni Planarity Testing," J. AC I11 vol. 21, no. 4,
pp. 549-568, 1974.

[13] M. Garey and D. Johnson, Computers and Intractability: A Guide to the Theory of
NP- Completeness. W.H. Freeman and Company, 1979.




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