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Title: NP-hard module rotation problems
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Title: NP-hard module rotation problems
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NP-hard Module Rotation Problems


Keumog Ahn
University of Minnesota


Sartaj Sahni *
University of Florida


University of Florida TR 92-24

Abstract


Preplaced circuit modules may be rotated to improve performance and/or routability. We show

that several simple versions of the module rotation problem are NP-hard.


Keywords and Phrases


Module rotation, circuit performance, routability


























* Research supported, in part, by the National Science Foundation under grant MIP-9103379 and in part by an award
from AT&TBell Laboratories.










1 Introduction


The performance and routability of a circuit are affected by flipping and/or rotating the cir-

cuit modules while keeping the placement fixed. One may formulate several performance and/or

routability measures that are based on estimates of wire length. In these estimates, the length of a
wire is estimated either by the Euclidean distance between the wire end points or by the Manhat-

tan distance. The developments of this chapter use the Manhattan Metric. Let ETL denote the

estimated total wire length and let MEL denote the maximum estimated wire length (i.e., length

of the longest wire).


The problems of minimizing ETL and MEL by flipping modules have been studied by

Yamada and Lin [YAMA88], Libeskind-Hadas and Liu [LIBE89], and Chong and Sahni

[CHON91 and 92]. All of these start with a replaced circuit. It is assumed that modules may be

flipped about their horizontal and/or vertical axes. Hence, there are four possible orientations of a

module under flipping (Figure 1). The initial or reference orientation is denoted by 0, h, v, and b,

respectively, denote the orientation that results from flipping about the horizontal axis, vertical

axis, and both axes. For rotation, rotations of 0, 90, 180, and 270 degrees are permitted and it is

assumed that these rotations do not result in module overlaps.





vertical axis



v (x,y) (x,y)

(x -, ) _ horizontal axis


b(x,y) ( h (x,y)
IT


Figure 1 h, v, b










Let ETLF (ETLR) denote the problem of flipping (rotating) modules so as to minimize the
estimated total wire length. In both [YAMA88] and [LIBE89], the Euclidean distance between
wire end points is used to estimate wire length. Both ETLF and ETLR are shown to be NP-hard
in [LIBE89]. The proofs of [LIBE89] are easily modified for the case when wire length is
estimated using the Manhattan distance between the wire end points. Further, the proof for ETLF
holds even if flips are restricted to be made along only the vertical (horizontal) axis. Yamada and
Liu [YAMA88] propose an analytical method to obtain suboptimal solutions for ETLF. This
algorithm is shown (experimentally) to be competitive with hill-climbing and simulated anneal-
ing algorithms for ETLF. In [LIBE89], Libeskind-Hadas and Liu propose neural network formu-
lations for ETLF and ETLR.


Chong and Sahni [CHON92] show that ETLF is linearly solvable for the case when the
modules are arranged as a matrix in which wires connect only pairs of modules that are in adja-
cent columns. They also show that ETLF is polynomially solvable for standard cell designs in
which wires connect modules in adjacent columns and either the number of module columns is
two or the number of modules dependent on any other module is bounded by some constant.
Chong and Sahni [CHON92] also evaluate a simple greedy heuristic that attempts to minimize
ETL by flipping modules. Experimental results reported by them indicate this heuristic is supe-
rior to the neural network approach of [LIBE89].


The problem of minimizing the maximum estimated wire length was studied by Chong and
Sahni [CHON91]. They considered two versions of the problem MEL4 and MEL2. In MEL4
each module is permitted four orientations as in Figure 1. In MEL2, only two these four orienta-
tions are permitted. Chong and Sahni showed that MEL4 is NP-hard even for a single row or
column of modules. They developed polynomial time algorithms for restricted versions of MEL4
and obtained an O (nlogn) algorithm for MEL2.


In [AHN92], we obtained the following results for module orientation problems:

1. The MaxDelay problem is that of reorienting the modules so that the length of the longest sig-
nal flow path is minimized. We showed that MaxDelay is NP-hard when only horizontal flips,
only vertical flips, both horizontal and vertical flips, are permitted. This is so even for single
column or single row instances with equal size modules.










2. The ETLF problem is NP-hard for a single column of equal size modules even when only vert-
ical flips are permitted. Note that he ETLF proof of [LIBE89] uses modules of two different
sizes. While most of these are placed in a single row arrangement, two modules are stacked into a
column. So, their construction does not apply to the case of single row instances with equal size
modules and flips restricted to horizontal ones (this would be symmetric to single column, equal
size modules, vertical flips only). So, our ETLF proof applies to even simpler module layouts
than does the proof of [LIBE89].

3. Single column ETLF can be solved in linear time when only horizontal flips are permitted.

4. For the ETLF problem, algorithms to obtain optimal solutions for layouts that follow a module
matrix model as well as for standard cell layouts are developed.

5. A heuristic for the MaxDelay problem is proposed and evaluated experimentally.


In this paper we consider only module rotations. The following NP-hard results are
obtained:

1. The MaxDelay problem is NP-hard for single column and single row instances with equal size
modules even when only rotations are permitted.

2. The ETLR problem is NP-hard for a single column or row of equal size modules even when
only 00 and 900 rotations are permitted. Note that the ETLR proof of [LIBE89] comes close to
having three rows of modules. However, modules of different size are used. Our proof applies to
the simpler layout of equal size modules into a single row or single column.


2 NP-hard Results


To prove our NP-hard results, we use the following problem that is known to be NP-hard:

NE3SATproblem [GARE79]

Input: A Boolean function I= C1, C, ..., C, in n variables x1, x2,..., x,. Each clause C, is the
disjunction of exactly three literals.

Output: "Yes" iffthere is a truth assignment for the n variables such that in each clause C, at least
one literal evaluates to true and at least one to false (i.e., all three literals do not have
the same truth value). "No" otherwise.










Theorem 1: MaxDelay is NP-hard for a single column of equal sized modules when modules

may be rotated but not flipped.

Proof: Let I be an m clause n variable instance of NE3SAT. We shall construct a 2n module sigle

column instance, R, of MaxDelay such that R has an orientation with maximum delay at most d iff

I has answer 'yes'. Each module of R has dimensions s x s where s=2m +4n (Figure 2). Each

module has 2m +1 pins on each of its four covers. The 2m modules are labeled M11, M1, M2, 2,...

and are stacked one on top of the other as in Figure 3. There are 2n input pins to the circuit and 2n

output pins. The input pins are the top of the circuit and the output pins at the bottom. Some of

the 8m +4 pins on a module are input pins, some are output pins, and some are not used. No pin

will have more than one wire connected to it. The vertical distance between the circuit input and

output pins is L. We assume that the signal delay along a wire equals the Manhattan distance

between its two end points and the delay between an input and output pin of a module is s regard-

less of the distance between these two pins.





12 m 12 m
1' '
2' 2'
m m




1 C1
2- 2
m _- m

1'2' m' 1'2' m



Figure 2 A module for Theorem 1




Module A, denotes literal x, while A, denotes x,. As drawn in Figure 3, each module

represents the condition when its corresponding literal is true. If a module M, is rotated counter-

clockwise 900, then its corresponding literal is interpreted to be false. A counterclockwise rota-

tion of 1800 or 2700 corresponds to an invalid truth assignment for x,. Similarly, ifAI, is rotated

clockwise by 900, x, is false. If it is rotated 1800 or 2700, x, has an invalid truth assignment.















1 2 2n input pins

m+n+1/2 12n-11 m+n+1/2








L

M2

0
0

Mn



12 2n e output pins



Figure 3 Single column module stack



When the modules of Figure 3 and the circuit input/output pins are connected by wires,

paths between the input and output pins of the circuit will be defined. The signal delay along

these paths will depend on the orientation of the modules on the paths. An optimal orientation is

one which results in the maximum input pin to output pin delay being minimum. The wires we

shall now define will have the property that an optimal orientation of the modules will have max-

imum delay < L +3s -2n +2 iff the answer to I is 'yes'.



First, input pin 2i-1 is connected to the top right comer pin of A, and input pin 2i is con-

nected to the top left comer pin ofM ,, l
the output pin 2i -1 and the bottom right output pin of AI, connected to output pin 2i, l
4(a)). The wires are drawn as directed edges so as to define the direction of signal flow. Signal

enters a module through an input pin and leaves through an output pin. As remarked earlier, the

signal delay in going from a module input pin to a module output pin is s. We assume that each










input pin (defined so far) of a module is connected to each of its output pins. There are two cir-
cuit input-to-output paths in Figure 4(a). One is from input pin 2i-1 to output pin 2i-1; the other
between input and output pins 2i. The delay of the first is
L +(m +n +1/2+2n -(2i -1))+(m +n +1/2+(2i -2)) =L +s. The delay of the second path is also L +s.


2i-1 2i

(a)


2i-1 2i

(b) Consistency wires included


Figure 4 Input output pin connections




In Figure 4(b), we have added two wires between modules MA and M,. This has been done to

ensure a consistent truth assignment to x, and x, (i.e., one in which exactly one of x, and x, is true
and the other is false). As can be seen, these wires also use comer pins. In the module orientation
of Figure 4(b), both x, and x, are true. The path (2i-1), B, A, d, c, 2i has delay
L +(m +n +1/2+2n -(2i -1))+s +s +(m +n +1/2+2n-2i) = L +3s +2n-4i +2 2 L +3s-2n +2. One may
verify that the remaining paths in Figure 4(b) have a delay no more than that of this path.


The maximum delay can be reduced by rotating either MA counterclockwise 900 or M,

clockwise 900. In the first case (Figure 5(a)) we have x, false and x, true while in the second, we

have x, true and x, false. In Figure 5(a), the paths with maximum delay are (2i -1), B, C, b, c, 2i
and (2i -1), B, A, d, c, 2i. Both have delay L +(m +n +1/2+2i -2)+s +(m +n +1/2+2n -2i) = L +2s +1.










In Figure 5(b), the paths (2i -1), B, A, d, c, 2i and (2i -1), B, C, b, c, 2i have maximum delay. This
delay is also L +(m +n +/2+2n -(2i -1))+s +(m +n +1/2+2i -1) = L +2s +1. One may verify that any

other orientation ofJ, orA, results in a maximum delay 2 L +3s-2n +2. (Note that L +3s-2n +2 =
L +2s +1+(2m +4n -2n +1) >L +2s +1.)


(a) Mi rotated 900 counterclockwise


(b) Mi rotated 900 clockwise


Figure 5 Rotating a module




Next, we introduce three wires for each of the clauses of I. Consider clause C,. Suppose
that C, = (x,,+x,+x) and u broken lines show the wire from/to the input/output pins that were defined earlier. There are addi-
tional such wires that are not shown (e.g., a wire from the bottom left comer pin of Mu to the out-
put pin 2u -1; a wire from input pin 2v-1 to the top right comer pin of My; etc.). The pins used by
the three new wires are labeled i or i' in Figure 6. The clause wires for the remaining seven
clause types are shown in Figures 11(b) (h). These are obtained from Figure 6(a) by rotating the
complemented variable modules 900 counterclockwise from Figure 6(a).


We assume that there is no path internal to module M, that connects the output pins A and C
(see Figure 4(b)) to any of the pins of M, labeled 1, ..., m, 1', ..., m' (see Figure 2). Similarly, we

assume that there are no internal paths in M, between the input pins b and d and the pins labeled
1, ..., m, 1', ..., m'. These assumptions isolate the paths involving consistency wires from those


















/
/


(a) Ci=x +x, +x,


(b) Ci =x+x,+x~


(c) Ci =x +x, +x


(d) ci x, +x, x,


1-'
ll c t,-x


(e) Ci =x x, +x


(g) Ci =x, +x, x


(h) Ci =x, +x,+x


Figure 6


I
I










involving clause wires.


Because of the consistency wires, we need only consider orientations of M, (M,) which are
rotated 0 or 900 counterclockwise (clockwise). Consider Figure 6(a). When none of the modules
is rotated, the maximum delay along a path that involves clause wires is
L +(m +n +1/2+2n -(2u-1))+2s +(m +n +1/2+2w-2) = L +3s +2(w-u) 2 L +3s +2 L +3s-2n+2.
When all three modules are rotated 900 counterclockwise, the maximum delay is again 2
L +3s +2. These two orientations correspond to all three literals of C, being true or all three being
false. When exactly one or two of the modules of Figure 6(a) is rotated by 900 counterclockwise,
the maximum delay is L +2s +2n -2 < L +3s -2n +2.


One may verify that for each of the remaining seven configurations of Figure 6, the max-
imum delay is L +3s +2 when all three literals are true or all three are false and is < L +2s +2n -2
when at least one is true and one is false.


Now, it is easy to see that the optimal orientation for R has maximum delay < L +3s-2n +2
iffthe answer to I is 'yes'. 1

Theorem 2: MaxDelay is NP-hard for a single row of equal sized modules when modules may
be rotated but not flipped.

Proof: Similar to that of Theorem 1. O

Theorem 3: ETLR is NP-hard for a single column of equal size modules.

Proof: Let I be any n variable m clause instance ofNE3SAT. We show how to construct, in poly-
nomial time, a single column instance R of ETLR such that from an optimal orientation set of the
modules of R, one can determine in O (1) time the answer for the NE3SAT instance I. R consists of
a column of 5n modules. These 5n modules are partitioned into n blocks of five modules each and
each of these blocks represents one of the n variables of The block forx, is shown in Figure 7(a)
and the column arrangement of the n blocks is shown in Figure 7(b). B, represents the five module
block for x,. The five modules in the module block for variable x, are labeled M1, l module MA, denotes the literal x, and is also referred to as M(x,). The bottom module MA5 denotes

the literal x, and is referred to as M(x,). The distance between the bottom of one module and the

top of the module below it is one unit. In the orientation in which M(x,) (M(x,)) is drawn in Figure

7, we interpret the literal x, (x,) as being true. Since both x, and x, are interpreted as being true in









the drawn orientation, this represents an inconsistent truth assignment. By rotating M(x,) (M(x,))
by 900 counterclockwise, we get an orientation in which x, (x,) is false. Counterclockwise rota-
tions of 1800 and 2700 are interpreted to correspond to invalid truth assignments. Figure 8 shows
the possible rotations and their interpretations. We use the letters T, F, and N to denote the truth
values true, false, and invalid, respectively. The comers of M(x,) are labeled a, b, c, and d while
those ofM(x,) are labeled A, B, C, and D.


Mil X I

M,2 D_

M3 D_

M14 D-

Ml5 Xl I

Block Bi for x,


(b) Column with 5n modules
B2








(b) Column with 5n modules


Figure 7 A variable block and module column




Each module has dimension s x s where s 2G +d, d=m if m is even and m +1 if m is odd
(recall that m is the number of clauses in I), and G=(m + 1)2. Each module has a pin on each of its
four comers and d + pins at the center of each side (Figure 9). The d + center pins are one unit
apart. Since d is even, there is always a pin at the center of each side of a module. The four sides
are referred to as top (T), bottom (B), left (L), and right (R), respectively. This labeling is done
with the respect to the initial orientations of Figure 7. In Figure 9, only the center pins on sides B
and R are shown. Pins are numbered 1 through d + left to right on sides T and B and top to bot-
tom on sides L and R.














a d
M(x) x,=T
b c
(a) No rotation



x,=T
() C

(a) No rotation


d c


a b
(b) 900

D C
x,=F
A B
(b) 900


(c) 1800


(c) 1800


b a
x,=N
c d
(c) 2700

B A
x,=N
C D
(c) 2700


Figure 8 Module rotations and interpretation






T
-EE G d G-


1
R

d+1


Figure 9 A module


To ensure a consistent truth assignment, we define eight two pin nets between the modules
of a variable block. Two of these nets connect pairs of modules from {M2, M2 M34} and are
defined as in Figure 10(a). The first net connects the southwest and northwest comer pins ofMA2
and A,3 and the second connects the southwest and northwest comer pins of modules MI3 and


I I









J23- -dl
IIIIIII


L




S(










A4,.


In the module orientations of Figure 10(a) (which are the same as in Figure 7), these two nets
have a combined length of 2. In each of the remaining 63 possible orientations for the three
modules (note that each module has 4 possible orientations which correspond to rotations of 0,
900, 1800, and 2700), the combined length of these two nets is at least s +2. We refer to these two
nets as type A nets.





M2 a d A D
b Mi M3
b c B
M3
A D a
M3 M5
M4 B C b-

(a) type A (b) type B (c) type C



Figure 10 Intra block nets




There are two type B nets (Figure 10(b)). One of these connects the northwest comer pin of
MA, and the middle left pin of M 3. The other connects the southeast comer pin of Ml, and the
middle top pin of A3. In the orientation drawn, x, =T and the combined length of the type B nets
is 2s +2h where h s +2 is the distance between the bottom ofM and the top ofMf3. The 16 pos-
sible orientations of 1 and MA3 are shown in Figure 11. The combined length of the type B nets
is minimum in the orientations (a), (b), (m), and (o). However, if either orientation (m) or (o) is
used, the length of the type A nets is at least s +2 as in both of these orientations, MA3 has been
rotated from its initial orientation of Figure 11(a). So, only orientation (a) and (b) can yield a
combined length for type A and type B nets that is 2s +2h +2. These correspond to no rotation of
MA or a 900 counterclockwise rotation ofM 1.









There are two type C nets that connect AM3 and M5 (see Figure 18(c)). Type C nets have the
same properties as type B nets. Their minimum combined length is 2s +2h. However to get a com-
bined length for type A and C nets of 2s +2h +2 (which is the minimum possible), M, 3 should not
be rotated and M5 may be rotated by either 0 or 900 counterclockwise.


a d
T
b c
A D
D
B C
(a) 2s+2h

a d
T
b c

D C
A B

(e) 4s+2h


a d
T
b c
C
D

(i) 4s+2h


a d
T
b c
B
C D
(m) 2s+2h


(b) 2s+2h


(f) 4s+2h


(j) 4s+2h


(n) 2s+2h


c b

d a
"A D
B C
(c) 3s+2h


A D

B C
(d) 3s+2h


(g) 3s+2h (h) 3s+2h


c b
N
da
C B
D A

(k) 3s+2h


c
N
d a

B
C D
(o) 3s+2h


(1) 3s+2h


b a
N
c d
B
C D
(p) 3s+2h


Figure 11 Orientation of A, and A,3 (type B nets)










So, the minimum possible combined length for nets of type A, B, and C is 4s +4h +2 and the
orientations that have this length satisfy:

P1: M, is rotated by 0 or 900 counterclockwise. So, x, = true or false.

P2: MA5 is rotated by 0 or 900 counterclockwise. So, x, = true or false.
P3: Ajl2, Aj3, and f \ are not rotated.


In case the module orientations do not satisfy P1 P3, the net length is 2 5s +4h +2. There
are two more intrablock nets. These are type D nets and are shown in Figure 12(a). One of these
connects the middle left pin of MAh and the middle top pin of MA5 while the other connects the
middle bottom pin of Mi, and the middle right pin of M,5. Note that these pins are not used by
nets of type A, B, and C.


The orientation of Figure 12(a) corresponds to x,=x,= T. In this orientation, the type D nets
have length 2s +2h' where h'=3s +4 is the distance between the bottom of M, and the top ofM 5.
One may easily verify that the length of the type D nets cannot be less than s +2h'. Two of the
orientations that have this length are given in Figures 15(b) and (c). In each exactly one of M,
and MA5 is rotated 900 counterclockwise. Figures 15(a) and (d) show the result of no rotation and
900 rotation for both modules. Hence, we conclude that the combined length of the eight intra-
block nets achieves its minimum of 5s +4h +2h'+2 iffthe module orientations satisfy P1 P3 and
P4 below:

P4: Exactly one ofM and Al5 is rotated 900 counterclockwise.


P1-P4 may be condensed to obtain the following:

Q1: The length of the intra block nets of B, is 5s +4h +2h'+2 iff exactly one of M, and HM5 is
rotated counterclockwise by 900 and the remaining modules are not rotated at all. In all other
orientations, the net length is at least 6s +4h +2h'+2. Notice that there are exactly two minimum

length configurations for B,. In one, x, =T and x,=F and in the other x, =F and x, T.


To complete the construction we need to introduce interblock nets that correspond to the
clauses of I. Let C,=(lp+lq+l,) be a clause of I. Assume that the literals are ordered in the ascend-

ing order of the variable indices. So if C, =(x, +x,+x,), then u
nets for C,. These involve modules M(1l), M(lq), M(lr). In case C,=x,+ +x+x, then














a a --
Mn T F T F M(x,)
a a

A A
A 5 T T F F M(x,)
A A
(a) 2s +2h' (b) s +2h' (c) s +2h' (d) 2s +2h'



Figure 12 Type D nets


M(x) =Mu, M(x,) =M,, and M(x,)=M,1 are involved. The three nets are shown in Figure 13(a).


Letj= [m/2] + 1 and let d be as in the definition of a module (Figure 9). Let y=i if i # j and
lety d +1 otherwise. The first net connects pin y of the left side of M(lp) and pin y of the top of
M(lq). The second connects pin y of the left side of M(lq) and pin y of the top side of M(lr). The
third net connects pin y of the bottom side of M(1l) and pin y of the right side of M(lr). The
configuration of Figure 13(a) has each module in the orientation of Figure 7. In this orientation,
each literal is true. The length of the first net is s-(D +y-l)+h +(D +y-l)=s +h1 where h, is the
distance between the bottom ofM(lp) and the top ofM(lq). Net 2 has length s +h2 where h2 is the
distance between the bottom of M(1,) and the top of M(lr). The length of net 3 is
s-(D +y-1)+h +s +h2 +(D +y-l) = 2s +h+h2. So, the combined length of the three interblock
nets is 4s +2h1 +2h2. The eight orientations corresponding to the literals being either true or false
are shown in Figure 13. The combined length of the three nets is in the range [3s +2h +2h2-d,
3s+2h +2h2+d] (note that 1 orientations (a) and (h). One may verify that none of the remaining 56 orientations has a com-
bined net length less than 3s +2h +2h2-d. Let min (x,)=5s +4h +2h'+2 denote the minimum length
of the intrablock nets for B, and let min (C,)=3s +2h +2h2 +d. Notice that since s-d=2G 2(m +1)2,

4s +2hi +2h2=min (C,)+s-d=min (C,)+2(m +1)2. (1)

Also, 2dm < 2(m +)m
< 2(m +1)2






























(a) 4s+2hi+2h2


(b) 3s+2hi+2h2 (c) 3s+2hi+2h2 (d) 3s+2hi+2h2
(d-2y+2) +(d-2y+2) +(d-2y+2)


(e) 3s+2hi+2h2 (f) 3s+2hi+2h2
-(d-2y+2) +(d-2y+2)


(g) 3s+2hi+2h2 (f) 4s+2hi+2h2
-(d-2y+2)


Figure 13 Interblock nets and rotations




We claim that the 5n modules of R can be rotated to have total wire length _
n m
Imin (x,)+ min (C,) iff there is a truth assignment for I which results in each clause having at
1-i 1-i
=1 ==1
least one true and one false literal. To see this, first suppose that such a truth assignment exists.

For each x,, rotate M(x,) by 900 counterclockwise if x, is false. Otherwise, rotate M(x,) by this

amount. Now, the length of the intrablock wires in each B, is min (x,) as the orientations satisfy

condition Q. The orientations also fall into one of the cases (b) - (g) of Figure 13. So, the inter-

block wires for each clause have length � min (C,).


= 2G

< 2G +d


M(It)












n
Next, suppose there is an orientation of the 5n modules that has wire length < Imin (x,) +
1-i
m
,min (C,). If there is a block B, that does not satisfy condition Q, then the length of the intrablock
1-i

nets for this block is at least mmin (x,)+s. Hence, the total length, L, of all nets is at least


n m
^min (x,)+s + min (C,)-2dm (3)
1 1 1 =


(as the minimum length for the interblock nets of any clause C, is min (C,)-2d). From (3), we

obtain

n m
L _ ,min(x)in(x) in (C,)+s-2dm
-1 1-1

n m
> imin (x,)+min (C,) (from (2))
1-1 1-1



So, condition Q is satisfied by all blocks and none of the modules has an orientation with

truth value N or one in which both x, and x, have the same truth value. Now suppose that there is

a clause for which the orientations are either those of Figure 13(a) or (h). In this case,

n m
L _ inin (x,)+m in(C,)+2(m +1)2-2d(m-1) (see (1))
-1 1-i

n m
2 min (x,)+ min (C,)+2(m +1)2-2(m +)(m -1)
-1 1-i

n m
> min (x,) + min (C,)
-i1 1-i



n m
So, if the wire length is < nmin(x,)+ min (C), then the orientations of M(x,) and
-i1 =1-

M(x,), 1
true and one false literal. So, the answer to the NE3SAT instance I is "yes" iff R has a set of
n m
module orientations with wire length $ nmin (x,)+ min (C,). O
-1 1-1

Theorem 4: ETLR is NP-hard for a column of equal size modules even when each module is

permitted to be rotated by either 0� or 90�.

Proof: Follows from Theorem 3. O










Theorem 5: ETLR is NP-hard for a single row of equal size modules when rotations of 00, 90�,
1800, and 2700 are permitted and also when only 00 and 900 rotations are permitted.

Proof: Similar to Theorems 3 and 4. o


5 Conclusions


We have shown that following simplified versions of the module rotation problem are NP-
hard:


1. The MaxDelay problem for single column and single row instances with equal size modules.

2. The ETLR problem for a single column or row of equal size modules even when only 00 and
900 rotations are permitted.


6 References



[AHN92] K. Ahn and S. Sahni, 'Flipping modules to improve circuit performance and routabil-

ity', University of Florida, Technical Report, 1992.

[CHON91] K.R.Chong and S.Sahni, 'Flipping modules to minimize maximum wire length',
Proc. IEEE Intl' Conf. On Computer Design, ICCD'91, pp 528-531.

[CHON92] K.R.Chong and S.Sahni, 'Minimizing total wire length by flipping modules',
Proceedings VLSI Design'92, IEEE Press, pp 25-30.

[GARE79] M.R.Garey and D.S.Johnson, 'Computers and Intractability: A Guide to the theory of

NP-completeness', W.H.Freeman and Co., New York, 1979.

[HORO76}]E. Horowitz and S.Sahni, Fundamentals of computer algorithms, Computer Science

Press, Maryland, 1976.

[HORO90] E. Horowitz and S. Sahni, Fundamentals of data structures in Pascal, 3rd Edition,

Computer Science Press, Maryland, 1990.

[LIBE89] R.Libeskind-Hadas and C.L.Liu, 'Solutions to the modules orientation and rotation

problems by neural computation network', Proc. 26th Design Automation Confer-
ence, pp 400-405, 1989.







20


[YAMA88] M.Yamada and C.L.Liu, 'An analytical method for optimal module orientation',
Proc. 1988 International Symp. on Circuits and Systems, pp 1679-1682.




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