Group Title: Design and tradeoff analysis of JPEG2000 on hardware-reconfigurable systems
Title: Abstract
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Permanent Link: http://ufdc.ufl.edu/UF00094745/00001
 Material Information
Title: Abstract
Physical Description: Book
Language: English
Creator: DeVille, R.
Aggarwal, Vikas
Troxel, Ian
George, Alan D.
Publisher: DeVille et al.
Place of Publication: Gainesville, Fla.
Publication Date: 2005
Copyright Date: 2005
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Bibliographic ID: UF00094745
Volume ID: VID00001
Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.

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Design and Tradeoff Analysis of JPEG2000
on Hardware-Reconfigurable Systems


R. DeVille', V. _- i.- !. I. Troxel, and A. George
High-performance Computing and Simulation (HCS) Research Laboratory
Department of Electrical and Computer Engineering, University of Florida
Gainesville, FL 32611-(.2" 11

ABSTRACT

JPEG 2' ,i, is a relatively new image coding standard that uses state-of-the-art compression techniques based
on wavelet technology. Due to the standard's inherent flexibility, JPEG 21 "" lends itself to a variety of
military and aerospace applications and beyond, from satellite and medical imaging to digital cameras, but it
can be complex and demanding upon computational resources. While several initial software solutions have
been developed, they lack the level of performance that high-end imaging applications demand. Custom
VLSI solutions have also been developed, but these can be cost-prohibitive to employ. In recent years,
researchers have achieved success in porting various image-processing applications to reconfigurable
computing (RC) systems, where it is possible to provide efficient bit-level manipulation and true hardware
parallelism without incurring the high costs of ASICs. Hence, motivation exists for an RC design and
implementation of this computation-intensive encoding and decoding standard.

This presentation will showcase the acceleration of JPEG 2 ""'I encoding by identifying the most
computationally demanding parts of the algorithm and targeting them onto the FPGA, with less critical parts
provided by conventional processing as needed in a dual-paradigm computational setting. Our approach with
the FPGA focuses on the lossless encoder (which involves integer operations) from the gamut of options in
the standard, since all-integer arithmetic is more amenable to an FPGA implementation. Results and analyses
with JPEG 2, I 1 I will be provided by means of designs and experiments on two different RC platforms, an
SGI Altix 350 RASC system featuring one Xilinx Virtex-II device and two 64-bit microprocessors connected
to one another and main memory via its high-speed NUMAlink interconnect, and a dual-processor Linux
server equipped with a Nallatech BenNUEY card in a PCI slot coupled with a BenBLUE-II daughter card
together featuring three Virtex-II devices. Results from these two platforms will help identify and illustrate
tradeoffs in mapping of this application to two different styles of RC-enhanced system architecture. In
addition to contrasting the design for each of two system architectures, we will also highlight the performance
improvement obtained when compared to the software versions running completely on the host.


1 Corresponding author, email: deville@hcs.ufl.edu, telephone: 352-392-9046.




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