Title: Reconfigurable computing : the emerging paradigm for high-performance computing
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Title: Reconfigurable computing : the emerging paradigm for high-performance computing
Physical Description: Book
Language: English
Creator: George, Alan D.
Publisher: George, Alan D.
Place of Publication: Gainesville, Fla.
Publication Date: March 2008
Copyright Date: 2008
 Notes
General Note: Presented at the 13th SIAM Conference on Parallel Processing for Scientific Computing
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Bibliographic ID: UF00094688
Volume ID: VID00001
Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.

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Alan D. George, Ph.D.
Director, NSF CHREC Center
Professor of ECE, University of Florida
(on behalf of facultylstaff of CHREC at Florida, GWU, BYU, and VT)
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Computing Reformation
End of wave (Moore's Law) riding fclk + ILP (CPU)
a Explicit parallelism & multicore the new wave
Many promising technologies on new wave
a Fixed & reconfigurable multicore device architectures
Many R&D challenges lie on new wave
a Tried & true methods no longer sufficient; complexity abounds
a Semantic gap widening between applications & systems
e.g. App developers must now understand & exploit parallelism -7
Inherent traits of fixed device architectures "o
a App-specific: inflexible, expensive (e.g. ASIC)
a App-generic: power, cooling, & speed challenges (e.g. Opteron)
a Many niches between extremes (Cell, DSP, GPU, NP, etc.)
Reconfigurable architectures promise best of both worlds
a Speed, flexibility, low-power, adaptability, economy of scale, size
a Bridging embedded & general-purpose computing, superset of fixed
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What is a Reconfigurable Computer?


System capable of changing hardware structure to
address application demands
a Static or dynamic reconfiguration
U-
a Reconfigurable computing, configurable computing,
custom computing, adaptive computing, etc.
L Often a mix of conventional fixed & reconfigurable
devices (e.g. control-flow CPUs, data-flow FPLDs)

Enabling technology? FPGA
ECA
" Field-programmable multicore devices FPCA
FPOA
" FPGA et al. (broad & growing space) TILE
XPP
Applications? et al.
u Vast range computing and embedded worlds
a Faster, smaller, less power & heat, adaptable &
versatile, selectable precision, high comp. density


Performance


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Opportunities for RC?


10-100x speedups with
2-1 Ox energy savings
not uncommon


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When and Where to Apply RC?


Perfc
* When do we need?
a When performance & versatility are critical
Hardware gates targeted to application-specific requirements
System mission or applications change over time
a When the environment is restrictive
Limited power, weight, area, volume, etc.
Limited communications bandwidth for work offload
a When autonomy and adaptivity are paramount
* Where do we need?


romance j
Power I


a In conventional servers, clusters, and supercomputers (HPC)
Field-programmable hardware fits many demands
High DOP, finer grain, direct data-flow mapping, bit manipulation,
selectable precision, direct control over H/W (e.g. perf. vs. power)
a In space, air, sea, undersea, and ground systems (HPEC)
Embedded & deployable systems can reap many advantages w/ RC


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Multi-Core/Many-Core Taxonomy


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Multicore,
Many-Core
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Devices with
segregated RA &
FA resources; can
use either in stand-
alone mode


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Homogeneous
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Heterogeneous
I j


Heterogeneous
I ___ ,


Homogeneous
I_____


Heterogeneous


Spectrum of Granularity In Each Class


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Datapath De ory PEBloI I Precis I Interface Mode Power Interconnect

Datapath Device Memory PE/Block Precis on Interface Mode Power Interconnect


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Reconfigurability Factors


Datapath


Interface


RLDR SDR
PALCP. SDRI.- A


Device


Memory


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Mode


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Performance
Power


Precision


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RC Comes to Scientific Computing

Broad range of FPGA accelerator technologies
a Altera & Xilinx FPGA devices
a Tightly coupled subsystems KIEI XILINX
Processor socket (AMD, Intel)
Lj e.g. XDI, DRC/Cray, Nallatech 4Mmlm
System interconnect slot
a e.g. Celoxica (HTX), SGI (NUMAlink) !- Comter
Memory slot oer 4 W
L e.g. SRC (SNAP/MAP)
a Loosely coupled subsystems


Se.g. Nallatech, GiDEL, Alpha Data NALLATE
Variety of board configurations ANALLATECH


a Future?


* New devices, tighter integration
* Heterogeneous MC convergence


ALPHA DATA


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RC Comes to Scientific Computing


Broad range of FPGA application development tools

a Core libraries

Easily accessed as function calls from user apps I-

a Higher-level programming languages

Adaptations to common HLLs
L C, Matlab, Simulink, Fortran, etc. ....... .
hiSll wint" r eauing aft ralwrs deel
a Design productivity with some loss of efficiency
a Many vendors, tools, options \,
a Domain of app scientists with basic H/W insight

a Lower-level programming languages V-.

HDLs (hardware description languages) _
a VHDL, Verilog
Fortran -D! Carter Pro
a Design efficiency with some loss of productivity
a Domain of electrical/computer engineers
Implicitly Controled Device
F t Dense logic device
U Ug ,Higher lok rates
L Future? Typically fixed'ogic
Higher abstraction layers for app formulation
a Focus on alg/arch exploration, mapping, prediction
a Semi-automated bridge to code/core generation, libs


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ramming Environment C


Explicitly Cont lied Devie
Direct=ecu6- logic
:Loer clc rates
Typically w-figumble
FPGA, CPLD, OPLD, eic


Unified Executable


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What is CHREC? CHREC
NSF Center for High-Performance
Reconfigurable Computing
* NSF Center for High-Performance Reconfigurable Computing
a First national research center in this field, established Jan'07
a Leading research groups in RC/HPC/HPEC @ four major universities
Founding sites (2007-): Univ. of Florida (lead) and George Wash. Univ.
Expansion sites (2008-): Brigham Young Univ. and Virginia Tech

* Under auspices of I/UCRC Program at NSF
a Industry/University Cooperative Research Center
CHREC is supported by both CISE & Engineering Directorates @ NSF
O CHREC is both a National Center and a Research Consortium
University groups form the research base (faculty, students, staff)
Industry & government organizations are research partners, sponsors,
collaborators, advisory board, & technology-transfer recipients
UNivrnSITY Of
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CHREC Members


Honeywell


S--Arctic Region
Supercomputing Center


SOAK 0/SdIIl di
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Los Alamos
NATIONAL LABORATORY


Ij4RRIS


1h Rincr
SResarch
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communications


LUNAy-


AFRL Munitions Directorate
Altera
Arctic Region Supercomputing Center
Boeing [new]
Cadence
GE Aviation Systems
Harris Corp. [new]
Hewlett-Packard 27 members with
Honeywell 37 memberships
IBM Research in 2008
Intel
L-3 Communications [new]
Los Alamos National Laboratory [new]
Luna Innovations [new]
NASA Goddard Space Flight Center
NASA Langley Research Center
NASA Marshall Space Flight Center
National Instruments [new]
National Reconnaissance Office
National Security Agency
Network Appliance [new]
Oak Ridge National Laboratory
Office of Naval Research
Raytheon
Rincon Research Corp. [new]
Rockwell Collins
Sandia National Laboratories


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CHREC Faculty (17& growing) I
* University of Florida (lead)
a Dr. Alan D. George, Professor of ECE Center Director
a Dr. Herman Lam, Associate Professor of ECE
Dr. K. Clint Slatton, Assistant Professor of ECE and CCE
L Dr. Greg Stitt, Assistant Professor of ECE
u Dr. Ann Gordon-Ross, Assistant Professor of ECE
L Dr. Saumil Merchant, Research Scientist in ECE
* George Washington University (partner) CHREC features a
a Dr. Tarek EI-Ghazawi, Professor of ECE GWU Site Director strong team of -40
a Dr. Ivan Gonzalez, Research Scientist in ECE graduate students
a Dr. Sergio Lopez, Research Scientist in ECE spanning the four
* Brigham Young University (partner) university sites.
u Dr. Brent E. Nelson, Professor of ECE BYU Site Director
L Dr. Michael J. Wirthlin, Associate Professor of ECE
L Dr. Michael Rice, Professor of ECE
L Dr. Brad L. Hutchings, Professor of ECE
* Virginia Tech (partner)
a Dr. Shawn A. Bohner, Associate Professor of CS VT Site Director
L Dr. Peter Athanas, Professor of ECE
L Dr. Wu-Chun Feng, Associate Professor of CS and ECE
L Dr. Francis K.H. Quek, Professor of CS


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Elephant in Living Room

* Semantic gap between apps & architectures
a Multicore world one of explicit parallelism L
a Yet, architectures increasingly complex to target
* How do we bridge this gap? A r l
j Holistic concepts & tools for app development Di
j FDTE model: F abstraction bridges semantic gap
Formulation today is usually "seat of pants" within design
Poor method for algorithm, architecture, & mapping exploration
Lack of fundamental concepts & tools, complexity management
Common problem throughout multicore world (CPU, FPGA, Cell, etc.)
a Formulation is missing link & potential salvation
Strategic design playground, abstraction, prediction
a Irony: learning lesson prevalent in HPC science domains
With transitions from F to D (automation, design patterns, etc.)


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2008 CHREC Projects


Potential Bottlenecks


Florida Site /' (^}
a F1-08: System-Level Formulation % 216I
Abstraction layer, exploring complex alg. & arch. mappings
a F2-08: Application Performance Analysis
Run-time performance analysis for HLL-based RC apps
L F3-08: Case Studies in Multi-FPGA Application Design
Insight in multi-device apps, rapid prediction models, scalability
L F4-08: Reconfigurable Fault Tolerance & Partial Reconfig.
System-level FT, exploiting RTR and PR for dynamic response to
a F5-08: Device Characterization & Design Space Exploration
Quantitative analysis of broad device space (FPGA, FPOA, TILE,

George Washington Site
a G5-08: Library Portability for HLL Acceleration Cores
Provide HLL core portability via Portable Framework I/F (PFIF)
a G6-08: Intelligent Deployment of IP Cores
Identify HW tasks, deploy intelligently (grouping, IP interconnect)
L G7-08: Partial Run-Time Reconfiguration for HPRC
Explore PR for HPC, reduce reconfig. delay, HW virtualization


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2008 CHREC Projects


rHLL (Matlab/Fortran)
Tools *


HLL (C/C++/SysC)
"A


BYU Site
Libraries -
a B1-08: Core Library Framework for HPC/HPEC Coregen JHDL Vendorl OpenFPGA
XML framework for encapsulating details of reusable circuit cores
a B2-08: Heterogeneous Architectures for HPEC RC
Device characterizations with RC/Fixed hybrids (FPGA, Cell, GPU) F
u B3-08: High-Reliability RC Design Tools and Techniques
Device-level FT, auto. insertion of SEU mitigation, SEU estimation & detection
a B4-08: Reliable RC DSP/Comm Systems Computation
Independent
Application-specific techniques for DSP/communications system design Models


Virginia Tech Site Platform
Independent
a V1-08: Model-Based Engineering Framework for HPRC Applications Models
Explore concepts in MBE for HPRC, abstraction layer, app generation
Li V2-08: Process-to-Core Mapping for Advanced Architectures Platform
Study app hand-crafted mappings for new RC devices; decision framework SMpefs


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CHREC Studies with Science Apps

Variety of single-FPGA apps studies conducted @ UF Site of CHREC in 2007
La LIDAR processing, Molecular Dynamics simulation, PDF estimation, Multichannel DDC
First, start with high-level formulation ("back of envelope") & prediction
a Using RAT = RC Amenability Test, developed by CHREC
Enter basic parms. of parallel alg. plus general platform data into RAT table
Outcome is predicted speedup of that algorithm on that platform
Iterative process with algorithm, precision, platform changes until satisfied
Next, perform detailed design & coding of alg. in language of choice
a LIDAR & DDC coded in AccelDSP, MD in Impulse-C, PDF in VHDL
Translate & execute on platform of choice
a Suitable platform already determined with aid of RAT
Evaluate results (in wall-clock speedup vs. fast Xeon/Opteron on same platform)
a LIDAR:predicted = 11.2, actual = 13.1 [on Cray XD1]
a MD: predicted = 10.7, actual = 6.6 [on XDI XD1000]
a PDF: predicted = 13.0, actual = 20.6 [on Cray XD1]
a DDC: predicted = 26.1, actual = 22.6 [on Nallatech H101-PCIXM]
Optionally, analyze execution, find bottlenecks, improve
[] Using PPW, toolset with RC extension developed by CHREC
Li e.g. in MD: quickly found inefficient buffer-size setting, speedup increased 16%

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IDARPA Studies @ CHREC


* Research roadmaps for app
development on FPGA systems
Sa Bridging app/arch semantic gap
m Prevalent challenge of multi-core
a RC to revolutionize DoD missions
* 2 DARPA studies by CHREC
a One @ founding sites + Clemson
a One @ expansion sites
* Focus areas
a Study underlying tools limitations
Theory, practice, technologies
a Formulate strategic research paths
Revolutionary, impactful
a Craft research roadmaps
Highlight DARPA-hard challenges


* Exploration of a Research Roadmap for Application
Development & Execution on FPGA-based Systems
* Future FPGA Design Methodologies and Tool Flows
I. Formulation
(a) Algorithm design exploration
(b) Architecture design exploration
(c) Performance prediction (speed, area, etc.)
II. Design
(a) Linguistic design semantics and syntax
(b) Graphical design semantics and syntax
(c) Hardware/software codesign
III. Translation
(a) Compilation
(b) Libraries and linkage
(c) Technology mapping (synthesis, place & route)
IV. Execution
(a) Test, debug, and verification
(b) Performance analysis and optimization
(c) Run-time services


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Conclusions

* Growing impact of RC in scientific computing
a HPC and HPEC; from satellites to supercomputers!
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a Best of uotn worlds (speed &o power of ASIC, versatiiity or Grr)
* Broad range of acceleration platforms & tools
a Device, tool, and system technologies evolving to meet science needs
* Research & technology challenges abound li
a All phases of FDTE model, device/system archs., etc. Dign
Similar to challenges throughout multicore Moore's wave Tlat
a CHREC sites and partners leading key R&D projects Eet
* Industry/university collaboration is critical to meet challenges
a Incremental, evolutionary advances by vendors not sufficient
a CHREC research collaborations addressing tough problems
a Industry & government as partners, catalysts, tech-transfer recipients


CHREC LW FLORIDA
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Thanks for Listening! @


* For more info:



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* Questions?


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Under the auspices of the highly acclaimed
program for IndustrvUniversitv Cooperative
Research Centers (UUCRC) at the National
Science Foundation, CHREC
(pronounced "shreck") is a new national
center and consortium for fundamental
research in reconfigurable computing.
CHREC is comprised of more than 30
organizations from academia, industry, and
government with synergistic interests and
goals in this field. After completing a two-
year development and selection process at
NSF, CHREC became operational in January
2007. CHREC consists of four university
sites, where faculty and students conduct
the research for CHREC, and 27 industry
and government members, partners


collaborating on all research tasks and when completed applying technology
transfers.

A broad range of goals have been defined with NSF for CHREC, including: (1)
Establish the nation's first multidisciplinary research center in reconfigurable high-
performance computing as a basis for long-term partnership and collaboration
amongst industry, academe, and government; (2) Directly support the research
needs of industry and government partners in a cost-effective manner with pooled,
leveraged resources and maximized synergy; (3) Enhance the educational
experience for a diverse set of high-quality graduate and undergraduate students;
and (4) Advance the knowledge and technologies in this emerging field and ensure
relevance of the research with rapid and effective technology transfer.

Center Directors
Dr. Alan D. George (UF), Center Director
Dr. Tarek El-Ghazawi (GW), Center Co-Director
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.- National Sciencc Foundation


CHREC Sites
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