Title: Reformation and formulation : key challenges for reconfigurable supercomputing
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 Material Information
Title: Reformation and formulation : key challenges for reconfigurable supercomputing
Physical Description: Book
Language: English
Creator: George, Alan D.
Publisher: Alan D. George
Place of Publication: Gainesville, Fla.
Copyright Date: 2008
 Notes
General Note: Paper presented at Many-core and Reconfigurable Supercomuting Conference (MRSC), April 1-3, 2008
 Record Information
Bibliographic ID: UF00094686
Volume ID: VID00001
Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.

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NS Cete fo High-Performance


Alan D. George, Ph.D.

Director, NSF CHREC Center
Professor of ECE, University of Florida


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Outline


* What is CHREC?

* Architecture Reformation

* Application Reformation

* Formulation Examples (CHREC)

* Conclusions


CHREC
NSF Center for High-Performance
Reconfigurable Computing


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What is CHREC?


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NSF Center for High-Performance
Reconfigurable Computing


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UF FLORIDA
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What is CHREC? CHREC
NSF Center for High-Performance
Reconfigurable Computing
* NSF Center for High-Performance Reconfigurable Computing
a Unique US national research center in this field, established Jan'07
a Leading research groups in RC/HPC/HPEC @ four major universities
University of Florida (lead)
George Washington University
Brigham Young Universityn
Virgini Teexpansion sites (2008-) ,
Virginia Tech
* Under auspices of I/UCRC Program at NSF
J Industry/University Cooperative Research Center
CHREC is supported by CISE & Engineering Directorates @ NSF
O CHREC is both a National Center and a Research Consortium
University groups serve as research base (faculty, students, staff)
Industry & government organizations are research partners, sponsors,
collaborators, advisory board, & technology-transfer recipients
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Honeywell in 2008
IBM Research in
Intel
L-3 Communications [new]
Los Alamos National Laboratory [new]
Luna Innovations [new]
NASA Goddard Space Flight Center
NASA Langley Research Center
NASA Marshall Space Flight Center
National Instruments [new]
National Reconnaissance Office
National Security Agency
Network Appliance [new]
Oak Ridge National Laboratory
Office of Naval Research
Raytheon
Rincon Research Corp. [new]
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CHREC Faculty (17& growing) I
* University of Florida (lead)
a Dr. Alan D. George, Professor of ECE Center Director
a Dr. Herman Lam, Associate Professor of ECE
Dr. K. Clint Slatton, Assistant Professor of ECE and CCE
L Dr. Greg Stitt, Assistant Professor of ECE
u Dr. Ann Gordon-Ross, Assistant Professor of ECE
L Dr. Saumil Merchant, Research Scientist in ECE
* George Washington University (partner) CHREC features a
a Dr. Tarek EI-Ghazawi, Professor of ECE GWU Site Director strong team of -40
a Dr. Ivan Gonzalez, Research Scientist in ECE graduate students
a Dr. Sergio Lopez, Research Scientist in ECE spanning the four
* Brigham Young University (partner) university sites.
u Dr. Brent E. Nelson, Professor of ECE BYU Site Director
a Dr. Michael J. Wirthlin, Associate Professor of ECE
a Dr. Michael Rice, Professor of ECE
a Dr. Brad L. Hutchings, Professor of ECE
* Virginia Tech (partner)
a Dr. Shawn A. Bohner, Associate Professor of CS VT Site Director
L Dr. Peter Athanas, Professor of ECE
L Dr. Wu-Chun Feng, Associate Professor of CS and ECE
L Dr. Francis K.H. Quek, Professor of CS


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NSF Center for High-Performance
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Architecture


Reformation


CHREC
NSF Center for High-Performance
Reconfigurable Computing


UNIVERSITY of
UF FLORIDA
SBYU





Architecture Reformation

End of wave (Moore's Law) riding fIk + ILP (CPU)
a Explicit parallelism & multicore the new wave
Many promising technologies on new wave
a Fixed & reconfigurable multicore device architectures
Many R&D challenges lie on new wave
a Tried & true methods no longer sufficient; complexity abounds
a Semantic gap widening between applications & systems
e.g. App developers must now understand & exploit parallelism
Inherent traits of fixed device architectures
a App-specific: inflexible, expensive (e.g. ASIC)
a App-generic: power, cooling, & speed challenges (e.g. Opteron)
a Many niches between extremes (Cell, DSP, GPU, NP, etc.)
Reconfigurable architectures promise best of both worlds
a Speed, flexibility, low-power, adaptability, economy of scale, size
a Bridging embedded & general-purpose computing, superset of fixed
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What is a Reconfigurable Computer?


System capable of changing hardware structure to
address application demands
L Static or dynamic reconfiguration
L Reconfigurable computing, configurable computing,
custom computing, adaptive computing, etc.
L Often a mix of conventional fixed & reconfigurable
devices (e.g. control-flow CPUs, data-flow FPLDs)

Enabling technology? FPGA
ECA
L Field-programmable multicore devices FPCA
FPOA
MPPA
L FPGA is "King" (but space is broadening) TILE
XPP
Applications? eta.
a Vast range computing and embedded worlds
a Faster, smaller, less power & heat, adaptable &
versatile, selectable precision, high comp. density


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Opportunities for RC?


10-1OOx speedups with
2-1Ox energy savings
not uncommon





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When and Where to Apply RC?

Performance f
* When do we need? Perform
Power ,
a When performance & versatility are critical
Hardware gates targeted to application-specific requirements
System mission or applications change over time
a When the environment is restrictive
Limited power, weight, area, volume, etc.
Limited communications bandwidth for work offload
a When autonomy and adaptivity are paramount
* Where do we need?
a In conventional servers, clusters, and supercomputers (HPC)
Field-programmable hardware fits many demands
High DoP, finer grain, direct data-flow mapping, bit manipulation,
selectable precision, direct control over H/W (e.g. perf. vs. power)
a In space, air, sea, undersea, and ground systems (HPEC)
Embedded & deployable systems can reap many advantages w/ RC


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SMulticore/Many-Core Taxonomy


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Reconfigurability Factors


Datapath


Interface


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Power


Performance
Power


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Interconnect


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Future Convergence
3
SRising development costs & other 2
factors drive convergence
a 1.5
a As seen in many other technologies 1

* Device architecture convergence? o.

a Many-core driven by densities 0

a Heterogeneous?
Cell as initial example
Intel and AMD both cite heterogeneous
MC in their future
To extent complexity is manageable

a Reconfigurable
Multi-
Performance + versatility c<
Adaptive for many apps, missions
Avoid limitations of fixed architectures
Manage issues of heterogeneity


Mask set costs by process
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Application


Reformation


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NSF Center for High-Performance
Reconfigurable Computing


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UF FLORIDA
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Application Reformation

* Dawn of reformation in application development methods 1
L Driven by architecture reformation; complexity management
L Holistic concepts, methods, & tools must emerge
* Semantic gap widening between apps & archs
a MC world (fixed or RC), explicit parallelism
Architectures increasingly complex to target by apps
New to fixed MC world, familiar to RC/FPGA & HPC worlds
Optimizing compiler parallelizing compiler
Domain scientist involved in comp. structure of their app
. How do we bridge semantic gap? i
L Focus upon computational fundamentals
Formal models, complexity management via abstraction, encapsulation
L Learn lessons from other engineering fields (
e.g. aerospace engineers do not flight-test first, why must we?
L Build basis for an RC engineering discipline
Leverage where practical for fixed MC world


CHREC
NSF Center for High-Performance
Reconfigurable Computing


UNIVE RSITY I .
UF FLORIDA
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IReformation in App Development


* FDTE as formal model

I. Formulation
Strategic design playground,
abstraction, prediction

II. Design
Tactics, coding, details /


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III. Translation J>
Conversion to executable form

IV. Execution
Services, debug, optimization

* Applies throughout computing

J We focus on RC, which involves
hardware & software design


Spectrum of application development phases
I. Formulation
(a) Algorithm design exploration
(b) Architecture design exploration
(c) Performance prediction (speed, area, etc.)
II. Design
(a) Linguistic design semantics and syntax
(b) Graphical design semantics and syntax
(c) Hardware/software codesign
III. Translation
(a) Compilation
(b) Libraries and linkage
(c) Technology mapping (synthesis, place & route)
IV. Execution
(a) Test, debug, and verification
(b) Performance analysis and optimization
(c) Run-time services


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FDTE Model
Formu lation "We need a change in
Form Ula n mindset, not simply another
Strategic exploration I programming language.
u Not coding in traditional sense
Parallel algorithm exploration
a Control structures (wide, deep)
Data structures (elements, precision, layout)
Parallel architecture exploration
As mapping targets of parallel algorithm
Base characteristics (e.g. DoP, OPS, B/V)
High-level performance prediction
a Supports tradeoff analysis (alg, arch, both)
Memory hierarchy, data locality, bottlenecks
Analytical, simulative, or combo
Feeder to Design phase
a Patterns, templates, code generation, libraries
Theme: strategic design decisions


Formulation Tools
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FDTE Model (continued)

II. Design
Linguistic design semantics & syntax
Graphical design semantics & syntax
Hardware/software coding, co-design


IIl. T

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translation DTE phases traditionally
uiltion sed for "seat of pants"
Compilation formulation, but increasingly
Libraries & linkage inefficient and appropriate.


l ecnnology mapping (synthesis, rAr
IV. Execution
Test, debug, & verification
Performance analysis & optimization
Run-time services


Design Tools


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. Execution Services


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Benefits of Formulation

Management of increasing complexity
a Ideal level for exploring structures, mappings, tradeoffs
a Major (strategic) decisions prior to coding, manage complexity
Increasingly important in MC: fixed or heterogeneous or reconfigurable I
L Basis for achieving semi-automation
Major reduction in DTE costs
L Design
Reduction in Dfreq and Dtime and thus cost (D, = Dtime x Dfreq)
i Better strategies incoming means less design & re-design
a Transitions from F to D (automation, patterns, templates, code)
3 Translation & Execution
Reduction in Tfreq and thus cost (T = Time x freq)
Similarly for E,
Notional example (with & without Formulation)

Cd,, = (Fc + Dc + T + Ec)j = (0 + 202 hrs + 20 hrs + 5 hrs), = 402 hr- Without
+ (0 + 150 hrs + 20 hrs + 5 hrs)i=,
U
- C = .(F, + v, + Tc + Ev)t = 2 hrs + 18 hrs +3 hrs +2 hrs =25 hrs With (16x better)

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CHREC Examples



S^ Numerical Pattern
Architecture Mapping analysis library
x exploration options
Analytical

exploration ROa ll l 01A prediction

Simulative
Bridge to prediction
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I RAT: RC Amenability Test

* Variety of single-FPGA apps studies conducted @ UF Site of CHREC in 2007
L LIDAR processing, Molecular Dynamics simulation, PDF estimation, Multichannel DD
* First, start with high-level formulation ("back of envelope") & prediction
a Using RAT, developed by CHREC
Enter basic parms. of parallel alg. plus general platform data into RAT table
Outcome is predicted speedup of that algorithm on that platform
Iterative process with algorithm, precision, platform changes until satisfied
* Next, perform detailed design & coding of alg. in language of choice
a LIDAR & DDC coded in AccelDSP, MD in Impulse-C, PDF in VHDL
* Translate & execute on platform of choice
a Suitable platform already determined with aid of RAT, much fewer iterations in T&E
* Evaluate results (wall-clock speedup vs. fast CPU on same platform)
a LIDAR: predicted = 11.2, actual = 13.1 [on Cray XD1]
a MD: predicted = 10.7, actual = 6.6 [on XDI XD1000]
a PDF: predicted = 13.0, actual = 20.6 [on Cray XD1]
L DDC: predicted = 26.1, actual = 22.6 [on Nallatech H101-PCIXM]
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I RC Simulation Framework

* 6 key components of
framework depicted in figure -Hardware Core Simla
Characterization Domi
a Many key tasks can be --
completed independently
and in parallel s
T Application Script
A Characterization Generation
* Framework allows arbitrary RT
applications to be simulated
on any arbitrary systems
L Component models & Model Model
application scripts can be Development Calibration
reused for rapid simulative
analyses
RC Simulation Framework

System models driven by application scripts produce simulative
prediction results


Diagram


performance


L Systems modeled in 2007 include socket-based FPGA platform (XD1000), PCI-
based platform (Nallatech), and proprietary FPGA platform (SRC-6)


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NSF Center for High-Performance
Reconfigurable Computing


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RCML Abstraction Layer


Formulation Stage

Abstract RC Language Representation


Algorithm/Architecture
Exploration


Performance Prediction via F1
Simulation Framework



Code Template(s)
Design Stage


Primary goals and tasks
a Research concepts for RC abstraction layer in app formulation
Enable specification of algorithm and architecture via new
formulation language, called RCML (on top of AADL)
Define mapping from RCML to performance prediction
models (RAT, SIM) for exploration, tradeoff analysis
Demonstrate methods using proof-of-concept
case studies
a Extend RAT for multi-FPGA systems and more diverse apps
i=4
for each L Pixels in split DataCube
----_ ACSM Calculation


Conceptual flow of RC
formulation stage under study

Motivations
a Formulation is often neglected,
bypassed during RC development
a Provide user-friendly streamlined
interface to simulative analysis tools
under development in CHREC

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Formulation & Design Patterns

lining Loop Goal Investigate methods for strategic design
ttrne) Patron through pattern-based formulation and design
\-^ -- -[ Approach
/ gth) Datapath
mReplication Catalogue & classify patterns for use in a model-based
PDF b11+ k" Pattern RC design methodology
Application bpd -x; Computation patterns (exploit & express parallelism)
llty-kd,; \ Memory Communication patterns (regulate flow of data)
t- 1- (ty; Dependency
if(. tc1) Resolution Interface patterns (define pattern interface/boundary)
Pattern a Formulation:
m Explore algorithmic and architectural alternatives
Patterns (pattern-based preliminary design)
mappedto =i kemel Parameterize design patterns to efficiently exploit
hardware performance prediction tools (e.g., RAT) and
AI &W modeling languages (RCML)
|J= ernheil Mapping to detailed design patterns (tactical design)
Acum to automate generation of code/code templates


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DARPA Studies @ CHREC


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*rject DARPA

OA DA


* Research roadmaps for app
development on FPGA systems
Li Bridging app/arch semantic gap
m Prevalent challenge of multi-core
a RC to revolutionize DoD missions
* 2 DARPA studies by CHREC
a One @ founding sites + Clemson
a One @ expansion sites f
* Focus areas
i Study underlying tools limitations
Theory, practice, technologies
a Formulate strategic research paths
Revolutionary, impactful
a Craft proposed research roadmaps
Highlight DARPA-hard challenges


Titles of Two Studies for DARPA
* Exploration of a Research
Roadmap for Application
Development & Execution on
FPGA-based Systems
* Future FPGA Design
Methodologies and Tool Flows


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NSF Center for High-Performance
Reconfigurable Computing


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Conclusions


CHREC
NSF Center for High-Performance
Reconfigurable Computing


UNIVERSITY Iof
UF FLORIDA
SBYU






Conclusions

* Computing technologies undergoing reformation
a Architecture MC, HC, RC, convergence as costs escalate
L Application development expressing parallelism
* "Elephant in living room" 4
a Widening semantic gap between apps & architectures
L Traditional programming models & methods alone inadequate
* FDTE model l1
L Many good concepts & tools in DTE to leverage D
L Missing link & potential salvation is Formulation
Critically important for arch & app reformations E
Bridge across semantic gap; complexity management
L Formulation as strategic playground of computational structure
Algorithm & architecture exploration, prediction, tradeoff analysis
Transitions from F to D (F/D patterns, templates, code generation, libraries)
More time spent in F leads to much less time in D, T, and E
L D (coding), T (compile, PAR), and E (bugs & bottlenecks) increasingly expensive


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Conclusions

Many research challenges to enable Formulation
a Abstraction layer for strategic exploration (alg, arch, map)
Increasingly important for future: fixed, heterogeneous, or reconfigurable
New generation of theories, models, concepts & tools
Supportive of domain scientists, not merely EE/CS gurus
a Preliminary results in CHREC projects show potential for F
Emphasis upon FPGA-based systems, but may apply more broadly
L Simple & quick method to predict strategic performance (RAT)
L Simulation infrastructure for strategic performance prediction (F1)
a Abstraction layer to express & explore alg, arch, mappings (RCML)
a Algorithm patterns for F and as bridge between F & D stages (FRS))
a Research roadmap exploration for future R&D activities (DARPA)
Many educational challenges as well, for example:
a Formulation in computing curriculum
Common in most engineering fields, deficient in computing studies
a Numerical analysis in computing curriculum
Understanding issues with dynamic range, resource usage, error
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Under the auspices of the highly acclaimed
program for Industt/Universit' Cooperative
Research Centers (I/UCRC) at the National
Science Foundation, CHREC
(pronounced "shreck") is a new national
center and consortium for fundamental
research in reconfigurable computing,
CHREC is comprised of more than 30
organizations from academia, industry, and
government with synergistic interests and
goals in this field. After completing a two-
year development and selection process at
NSF, CHREC became operational in January
2007. CHREC consists of four university
sites, where faculty and students conduct
the research for CHREC, and 27 industry
and government members, partners


collaborating on all research tasks and when completed applying technology
transfers.

A broad range of goals have been defined with NSF for CHREC, including: (1)
Establish the nation's first multidisciplinary research center in reconfigurable high-
performance computing as a basis for long-term partnership and collaboration
amongst industry, academe, and government; (2) Directly support the research
needs of industry and government partners in a cost-effective manner with pooled,
leveraged resources and maximized synergy; (3) Enhance the educational
experience for a diverse set of high-quality graduate and undergraduate students;
and (4) Advance the knowledge and technologies in this emerging field and ensure
relevance of the research with rapid and effective technology transfer.

Center Directors
Dr. Alan D. George (UF), Center Director
Dr. Tarek El-Ghazawi (GW), Center Co-Director
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N at oional Sciccc Foundaricn

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