• TABLE OF CONTENTS
HIDE
 Title Page
 Dedication
 Acknowledgement
 Table of Contents
 List of Tables
 List of Figures
 Abstract
 Introdcution
 Emergency call processing
 A processing systems organizat...
 A street system model
 The search algorithm
 A search system architecture
 Evaluation of the proposed...
 Architectures for the other...
 Conclusion
 Appendix
 Reference
 Biographical sketch
 Copyright














Group Title: computer architecture for emergency call processing.
Title: A computer architecture for emergency call processing
CITATION THUMBNAILS PAGE IMAGE ZOOMABLE
Full Citation
STANDARD VIEW MARC VIEW
Permanent Link: http://ufdc.ufl.edu/UF00082482/00001
 Material Information
Title: A computer architecture for emergency call processing
Physical Description: xi, 131 leaves. : illus. ; 28 cm.
Language: English
Creator: Cyre, Walling Raymond, 1942-
Publication Date: 1973
 Subjects
Subject: Electrionic data processing -- Emergency communications systems   ( lcsh )
Assistance in emergencies   ( lcsh )
Electrical Engineering thesis Ph. D
Dissertations, Academic -- Electrical Engineering -- UF
Genre: bibliography   ( marcgt )
non-fiction   ( marcgt )
 Notes
Thesis: Thesis -- University of Florida.
Bibliography: Bibliography: leaves 130-131.
General Note: Typescript.
General Note: Vita.
 Record Information
Bibliographic ID: UF00082482
Volume ID: VID00001
Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
Resource Identifier: aleph - 000582334
oclc - 14101112
notis - ADB0708

Table of Contents
    Title Page
        Page i
    Dedication
        Page ii
    Acknowledgement
        Page iii
    Table of Contents
        Page iv
        Page v
    List of Tables
        Page vi
    List of Figures
        Page vii
        Page viii
    Abstract
        Page ix
        Page x
        Page xi
    Introdcution
        Page 1
        Page 2
        Page 3
        Page 4
    Emergency call processing
        Page 5
        Page 6
        Page 7
        Page 8
        Page 9
        Page 10
        Page 11
    A processing systems organization
        Page 12
        Page 13
        Page 14
        Page 15
        Page 16
        Page 17
        Page 18
        Page 19
        Page 20
    A street system model
        Page 21
        Page 22
        Page 23
        Page 24
    The search algorithm
        Page 25
        Page 26
        Page 27
        Page 28
        Page 29
        Page 30
        Page 31
        Page 32
        Page 33
        Page 34
        Page 35
        Page 36
        Page 37
        Page 38
        Page 39
        Page 40
        Page 41
        Page 42
        Page 43
        Page 44
        Page 45
        Page 46
    A search system architecture
        Page 47
        Page 48
        Page 49
        Page 50
        Page 51
        Page 52
        Page 53
        Page 54
        Page 55
        Page 56
        Page 57
        Page 58
        Page 59
        Page 60
        Page 61
        Page 62
        Page 63
        Page 64
        Page 65
        Page 66
        Page 67
        Page 68
        Page 69
        Page 70
        Page 71
        Page 72
        Page 73
        Page 74
        Page 75
        Page 76
        Page 77
        Page 78
        Page 79
        Page 80
        Page 81
        Page 82
        Page 83
        Page 84
        Page 85
        Page 86
        Page 87
    Evaluation of the proposed architecture
        Page 88
        Page 89
        Page 90
        Page 91
        Page 92
        Page 93
        Page 94
        Page 95
        Page 96
        Page 97
        Page 98
        Page 99
        Page 100
        Page 101
        Page 102
        Page 103
        Page 104
        Page 105
        Page 106
        Page 107
    Architectures for the other systems
        Page 108
        Page 109
        Page 110
    Conclusion
        Page 111
        Page 112
        Page 113
    Appendix
        Page 114
        Page 115
        Page 116
        Page 117
        Page 118
        Page 119
        Page 120
        Page 121
        Page 122
        Page 123
        Page 124
        Page 125
        Page 126
        Page 127
        Page 128
        Page 129
    Reference
        Page 130
        Page 131
    Biographical sketch
        Page 132
        Page 133
    Copyright
        Copyright
Full Text















A COMPUTER ARCHITECTURE
FOR .EIERCENrCY CALL PROCESSING





By



CALLING RAYMOND CYRE


A DISSERTATION PRESENTED TO THE GRADUATE COUNCIL OF
THE UNIVERSITY OF FLORIDA
IN PARTIAL FULFILLMENT OF THE REQUIP.FIENTS FOR THE
DEGREE OF DOCTOR OF PHILOSOPHY



UNIVERSITY OF FLORIDA


1973

































To Susan














ACKNOWLEDGEMENTS


The author wishes to express his sincere appreciation

to his advisors, Dr. Gerald J. Lipovski, Dr. Zoran R. Pop

Stojanovic, and Dr. John R. O'Malley, with particular

thanks to Dr. Lipovski for his guidance and encouragement.

The author also wishes to express appreciation to his

wife, Susan, for her help, encouragement, and patience.


iii















TABLE OF CONTENTS


Page
ACKNOWLEDGEMENTS . .. . iii

LIST OF TABLES . . . . .vi

LIST OF FIGURES . . . . vii

ABSTRACT . . . .. ix

INTRODUCTION . . . . .. 1

EMERGENCY CALL PROCESSING. . . .. 5

A PROCESSING SYSTEMS ORGANIZATION . ... 12

The Name File and Name System . .. 12
The Automatic Alarm File and Automatic
Alarm System . . . .15
The Street Index and Street Index System 15
The Street System Model and Search System 17
The Response File and Response System 17
The Inventory File and Inventory System 17
The Length File and Length System . 18
The Dispatch System . . ... 19
Additional Comments . . ... 19

A STREET SYSTEM MODEL . . ... 21

THE SEARCH ALGORITHM . . ... 25

A SEARCH SYSTEM ARCHITECTURE . .. 47

Storage of the Street System Model . 51
Messages . . . . 58
The Processing Cell Procedures . .. 65
The Processing Cell Architecture . 70
The Access Structure . . 80









TABLE OF CONTENTS (continued)


Page

EVALUATION OF THE PROPOSED ARCHITECTURE ... 88

Speed and Cost . . ... 88
Dependability . . . 101
Alternative Approaches . . ... .104

ARCHITECTURES FOR THE OTHER SYSTEMS . ... 108

CONCLUSION . . . . ... 111

APPENDIX

A NOTATIONAL CONVENTIONS . . 115

Statement Forms . . 115
Identifiers . . . 116
Operator Symbols . .... .117

B SIMULATION OF THE EXAMPLE MODULE . .. .124

LIST OF REFERENCES . . . ... 130

BIOGRAPHICAL SKETCH . . . ... 132














LIST OF TABLES


Table Page

1 Characteristics of the Selection
Criteria for Shortest Route Algorithms
on the Sample Street System of Figure 5. 41

2 Estimates of the Ranges of Street
System Parameters . . .. 57

3 The Search System Messages . .. 60

4 Examples of Interactions Between
Messages and Memory Words . ... 64

5 Example Module Description . .. 77

6 Connotations of Identifiers . 118

7 Operator Symbols . . . 122

8 Module Simulation Functions ...... 125

9 Module Input/Output Simulations . 128

10 Module Simulation Example . .. 129















LIST OF FIGURES


Figure Page

1 An emergency call processing system 8

2 An example of a desirable format for
the processor input and output . .. 10

3 A decomposition of the information
for emergency call processing . 13

4 An emergency call processor systems
organization . . . 14

5 An example of a street system model 27

6 The operation of the Moore algorithm
on the model of Figure 5 for the site
at node 38, showing the distances of
the nodes . . . . 30

7 The operation of the Dijkstra algorithm
on the model of Figure 5 for the site
at node 38 . .... . 31

8 The operation of the search algorithm
on the model of Figure 5 for the site
at node 38, and the control parameter,
R, incremented 5 units per iteration 39

9 The operation of the search algorithm
on the model of Figure 5 for the site
at node 38, and the control parameter,
R, incremented 5 units per iteration 40

10 The proposed search system architecture. 48

11 The storage organization of the street
system model elements in the cyclic
access memories . . . 52

12 The representation of the street system
of Figure 5 as a collection of fork
records . . . . 54


vii









LIST OF FIGURES (continued)


Figure Page

13 The serial storage of the fork records
of Figure 12 in a cyclic memory, showing
addresses and head node numbers .. 55

14 A section of the street system of
Gainesville, Florida . .. 59

15 The generations, lifetimes, and
deliveries of search messages for the
example of Figure 8 stored as in
Figure 13 . .. . . 63

16 The modular substructure of a
processing cell . . . 71

17 A submodule for Sequence 2 . ... 76

18 A unit of the search processor . .. 81

19 The structure of a channel . . 82

20 The dependence of the number of cycles
to complete a search over Figure 14 on
the control parameter increment ... 91

21 The dependence of the maximum required
storage modules on the control parameter
increment for searches over Figure 14 92

22 The distribution of arcs by arc length
for the street system of Figure 14 . 93

23 The potential increases in the number
of cycles to complete searches over
Figure 14 due to limiting storage
module requirement with the control
parameter, R . . . ... 94

24 Incidences of bus contention as a
percentage of the total messages
generated . . . . 96

25 Comparison of techniques for limiting
the required number of storage modules 98


viii









Abstract of Dissertation Presented to the Graduate Council
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy


A COMPUTER ARCHITECTURE
FOR EMERGENCY CALL PROCESSING


By

Walling Raymond Cyre

December, 1973


Chairman: Gerald J. Lipovski
Major Department: Electrical Engineering


This dissertation reports a computer architecture for

emergency call processing, and with this as an example,

examines an approach to designing special purpose computer

architectures. Computer architecture here includes consider-

ations of data organization, processing procedures, and

machine structure. The primary tasks to be performed by the

emergency call processor developed here are assignment,

routing, and dispatching of police, fire, ambulance, and

rescue vehicles in an urban area.

In a review of the emergency call processing problem,

system boundaries, necessary processing tasks, and requisite

information or data are identified. The problem is sub-

divided through a partition on the information base with

respect to the processing tasks. Each subproblem is identi-

fied with a processing system, and the system which assigns

and routes the vehicles closest to the site specified in a

call is found to merit further study. The remaining systems









are readily implemented by well-known techniques in avail-

able and previously proposed machines.

The real-time assignment and routing of vehicles becomes

the shortest route problem in graph theory when the street

system is modeled as a labeled, directed graph. From a

review of reported shortest route algorithms of the tree-

building class, it was observed that they operate by iter-

ated application of a minimizing procedure to elements of

the graph. The operations which must be performed in an

iteration may be executed in parallel, and an iteration can

be related to a scan of the graph elements. A generalized

statement of the algorithm is developed and a control param-

eter is introduced through which the number of operations

per iteration or cycle may be constrained to suit the machine

structure.

A machine structure based on the algorithm is proposed.

The machine employs segmented, cyclic access memory for

storage of the street system model such that an iteration of

the algorithm is identified with a memory cycle. A proces-

sing cell is associated with each memory segment to permit

parallel applications of the minimizing procedure to the

stored graph elements. Specific procedures realizing the

algorithm are developed, a data structure for the street

system model is designed, and a format for data transfer is

specified. An access structure for the machine is proposed

to meet the data transfer needs and to exploit the multi-

plicity in processing units for slow degradation in performance









with increasing component failures. Alternative architec-

tures are compared against the proposed architecture with

respect to speed, cost, and dependability.

In this study of a special purpose computer architec-

ture, it is evident that the aspects of processing proce-

dures,data organization, and machine structure must be

considered as they interact within the framework of the

application. Particular attention must be paid to avoid

unnecessarily constraining one of these aspects in describ-

ing one of the others. It is believed that the approach to

solving the emergency call processing problem followed here

has resulted in a sound architecture, well suited to the

problem. The approach should easily extend to the design of

computer architectures for other applications.














INTRODUCTION


The architecture of a special purpose computer is more

than the structure of a machine. It also includes the pro-

cessing procedures implemented in the machine and the organi-

zation of data in the storage. The design of a special

purpose computer, then, includes the specification of these

three architectural features such that the computational

requirements of the application are satisfied, while per-

formance and cost criteria of.the problem are observed.

This report describes an example in the design of a special

purpose computer from the analysis of the application to the

specification of the architecture. The application area is

emergency call processing.

The function of the computer proposed here for emer-

gency call processing is to improve fire, police, ambulance,

and rescue services in urban areas through reductions in

emergency vehicle response times. Response time is an im-

portant factor in servicing emergencies, and even small

improvements can result in the saving of human life or

valuable property [CARTG 70, CDPII* 69, LARSR 70]. It is

believed that delays arising in emergency service communi-

cation centers and the travel times of responding vehicles

can be reduced through automation in emergency call

1









processing with a moderate initial cost which should be

quickly recovered from savings in operating costs.

The primary tasks to be performed by the emergency call

processor are the calculation of the minimum travel times of

appropriate, available vehicles from their respective posi-
tions to the site of the emergency; the assignment of

vehicles based on the needs of the emergency and the travel

time estimates; and the determination of a quickest route

through the street system for each assigned vehicle. The

computation of travel times and the determination of routes

is based on a labeled, directed graph model of the street

system, and is performed for each emergency at the time the

call is received. The labels on the arcs of the street sys-

tem model represent the orientations of the corresponding

street segments and the estimated travel time along the seg-

ments. The orientations are included in order to assess

penalties on turns. Having the street system model stored

in the processor memory, the travel time labels are easily

altered with regular or anticipated changes in traffic con-

ditions, and with reported exceptions. The locations of

available emergency vehicles with respect to the street

system are represented in the model through labels on the

nodes and, again, are easily modified such that the current

positions of patrolling police cars or other cruising

vehicles may be accurately represented.

The travel times between emergency vehicle positions

or stations and the site of the emergency are calculated by








a shortest route algorithm representing a generalization of

the procedures of E. F. Moore [MOORE 59] and E. W. Dijkstra

[DIJKE 59]. As well as determining the travel times, the

algorithm places in labels of the nodes a shortest route

tree rooted at the node nearest the site of the emergency.

This tree facilitates the determination of quickest routes.

The structure of the proposed emergency call processor

has been heavily influenced by the size of street system

models for urban areas; the speed with which assignments

must be made and routes determined; and the characteristics

of shortest route algorithms. Cyclic access storage devices

such as magnetic discs or drums appear to be the most satis-

factory compromise in speed and cost for the repository of

the street system model. The shortest route algorithm

requires only simple arithmetic operations (addition, sub-

traction, and comparison), and has a high potential for

parallel computation. This potential is exploited to com-

pensate for the latency of the main memory by appending

suitable arithmetic and control modules to each cyclic seg-

ment of the memory. The result is a distributed-logic

machine structure. Both spatial and temporal relocationsof

partial results are provided for by buses and a small,

content-addressed memory. The costs of the segment modules

and the content-addressed memory are kept low by the use of

serial arithmetic and shift register memories wherever

possible.









In addition to the primary tasks of emergency call pro-

cessing, interface problems are considered. It is assumed

that the specifications of emergency sites and the descrip-

tions of the emergencies are presented to the processor as

character strings, and that the routes found by the processor

must be translated back into the names of streets. The

architectures of processor subsystems are proposed for these

tasks, but in less detail than for the primary tasks.
In the following section, the emergency call processing

problem is considered in detail in order to formulate the

desiderata. The next section deals with the street system

model, and subsequent sections treat the shortest route

algorithm and the processor architecture. In the final sec-

tions, elements of speed, cost, and dependability in the

proposed architecture are considered, and alternative archi-

tectures are reviewed.














EMERGENCY CALL PROCESSING


The purpose of this section is to examine the compo-

nents of vehicle response times and their relationships with

emergency call processing in some detail in order to develop

goals for the processor design. After analyzing response

times, the functions of an emergency call processor in an

urban-wide, emergency call processing system are considered.

The response time of an emergency vehicle is the dura-

tion from the time the informant initiates his call to the

time the vehicle arrives at the site of the emergency. The

two major components of response time are the communications

center response time and the travel time or field response

time [TFRPT 67]. The communications center response time

is the sum of the times for communication between the infor-

mant and a dispatcher, for the selection of vehicles by the

dispatcher, and for the communication between the dispatcher

and the vehicle operator. In police department operations

[LARSR 70] there are additional components because the calls

are filtered through a receptionist who encodes the informa-

tion and passes it to the dispatcher who may act on it or

place it in a queue depending on its urgency and the avail-

ability of vehicles.









The principal response time components of interest here

are those associated with the dispatcher and the field

response time. When the dispatcher is informed of an emer-

gency, he first decides on the types and numbers of vehicles

which should be sent. This decision is based on the descrip-

tion of the emergency, or its location and a standard re-

sponse. The dispatcher then selects the specific units to

respond from those available. Rapid and accurate decisions

by the dispatcher depend on his immediate knowledge of the

availability of specific units, their locations, the street

system, preplanned routes, and standard responses. Although

the dispatcher may be backed up by manual status boards,

street maps, street indices giving standard responses, and

possibly overlays for preplanned routes, reliance on these

measures can result in significant, additional delay [CARTG

70]. As an alternative to requiring the dispatcher to use

manual reference sources, the urban area is artificially

partitioned to limit the dispatcher's memory requirements.

The routes selected for responding vehicles are left

to the vehicle driver or his superior. When the vehicle is

located in its normal station, preplanned routes are used;

otherwise, the route decision is based on the vehicle

driver's knowledge of the street system and experience. So,

in brief, the important decisions in emergency call proces-

sing rely heavily on models and strategies stored in human

memories, and response times include these decision times

and depend on the accuracy of them.









An obvious goal for an emergency call processor is that

it make readily available an accurate model of the street

system including the locations and availabilities of all

emergency vehicles. A more ambitious goal, and the one

adopted here, is that the processor make the decisions on

which vehicles to send and how to route them. To accomplish

this, the processor needs a table of the standard responses

as well as a street system model.

Consider the emergency call processing system of Figure

1. This system is intended to cover and serve an entire

urban area for all types of emergency. As the informant

describes the emergency and its location, the receptionist

conveys the information to the processor through a keyboard.

Automatic alarms alert the processor directly as indicated.

In order to reduce the burden on the receptionist, it is

desirable that the site specification be entered as a string

of characters. Sites are specified as addresses (a number

and a street name), places (store, school, apartment house

names, etc.), and intersections (a pair of street names).

A further criterion is that the processor inform the recep-

tionist immediately when there is an error, and display a

number of acceptable character strings which are similar to

the one rejected. As indicated in the figure, the output is

transmitted directly to the vehicle operators through mobile

terminals in the vehicles [ELECM 73]. An output text should

contain the input information, the identification of the








8








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0r1 C! rri T rOy1 Cc-
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An emergency call processing system.


Figure 1.








vehicle, and the suggested route as an alternating string

of turns and street names. An example illustrating desirable

input and output formats appears in Figure 2.

As an additional design consideration, a primary ser-

vice rendered by ambulances is rapid transportation. There-

fore, the processor should also be capable of finding the

quickest route from the emergency site to the nearest emer-

gency treatment center.

With respect to the cost of the emergency call processor

and its terminals, observe that the dispatchers have been

eliminated and the training and skill required of the recep-

tionists is quite low. Thus, the final design goal is to

produce the processor at a price which can be recovered in a

few years through eliminated salaries. This is actually a

generous allowance when one considers that a number of dis-

patchers are required for each type of emergency service in

even a small urban area. It is not suggested, however, that

the training of vehicle operators be reduced, though some of

the training might be channeled towards emergency medical

and legal training.

In summary, the emergency call processor should be

designed to reduce vehicle response times to a minimum--the

sum of the communication time between informant and recep-

tionist plus the least time in which the vehicle can be

safely relocated from its current position to the emergency

site. This should be accomplished without the need for















(a serious automobile accident at an inter-
Input section involving injuries and a fire)



i nort & ocean
CONFIRM: NORTH AVENUE AND EAST OCEAN WAY
yes multiple vehicle,injuries,fire







Output (to hose truck 37 at station 4)



NORTH AVENUE AND EAST OCEAN WAY
MULTIPLE VEHICLE, INJURIES, FIRE
ENGINE 37
TURN N ONTO CARTER BOULEVARD
TURN NE ONTO SETIN STREET
TURN E ONTO EAST OCEAN WAY


Figure 2. An example of a desirable format for the
processor input and output.





11


highly trained receptionists and without a net increase in

long-term costs to the suppliers of emergency services.















A PROCESSING SYSTEMS ORGANIZATION


As indicated in the discussion of emergency call pro-

cessing in the previous section, a significant aggregation

of information is required. In this section, this body of

information is decomposed into a number of interrelated

files as indicated in Figure 3. Associated with each of

these files is a set of tasks required in emergency call

processing. Based on these files and tasks, a systems

organization for the emergency call processor is proposed.

This organization is illustrated in Figure 4.


The Name File and Name System


The name file is essentially a table of the names of

streets, the names of places, and the acceptable descrip-

tions of emergencies. Each entry of the table includes an

acceptable form of the name as a character string. Each

street name has one attribute in the table, a numerical code

unique to that name. This street name code is a pointer to

information in the street index file. Similarly, each emer-

gency description is associated with a response code point-

ing to the response file, but unlike the streets, many

descriptions may have the same response code. The names of
























































Figure 3. A decomposition of the information for
emergency call processing.



























































Figure 4. An emergency call processor systems organization.









places in the file have three attributes: a street name

code, an address number (house number), and a response code.

The response code alludes to the standard response for a

fire reported at that location. In addition to places such

as stores, schools, parks, and the like, names for some

remote alarm devices are included, e.g., "FIRE ALARM BOX #78."

The functions performed by the name system are primarily

the translation of character strings into one or more internal

codes, and the translation of internal codes into character

strings. As pointed out in the previous section, a secondary

function of the name system is to perform a threshold search

on names in the file if an exact match on the input string

is not found, returning those names exceeding the threshold

to the receptionist.


The Automatic Alarm File and
Automatic Alarm System


The automatic alarm file is directly accessed by-signals

from automatic alarms, translating the signals into name

codes and response codes. The name code refers to a place

name listed in the name file.


The Street Index and the Street Index System


The street index contains a set of lists representing

the streets of the urban area as chains of intersections

and other significant points. Each list represents a









continuous section of road under a single name code, and is

headed by a special record. This record contains pointers

to other sections of road under that name code (if there are

any), and the geographical direction corresponding with

travel along the street in the order in which the intersec-

tions are listed. Each element of a list contains an inter-

section identification number, an effective street address

for the intersection or point, the name of the transecting

street, and the response code for fires reported in that

area. The intersections are listed in the order of increas-

ing address numbers.

The primary function of the street index system is to

locate the site of an emergency in terms of one or more

intersection identification numbers. Since specification

of sites by place names are translated into street addresses

by the name system, the street index system has to deal only

with street addresses (number and name code) and intersec-

tions (a pair of name codes). In the case of street

addresses, both intersections whose address numbers bracket

the given number are considered to be sites. Ambiguity is

resolved by including the given street address in the output

text (see Figure 2). A second task of the street index

system is to determine the name codes for segments of emer-

gency vehicle routes found by the search system.








The Street System Model and Search System


The street system model is a directed graph representa-

tion of the structure of the street system, depicting inter-

sections and street segments. A number of parameters are

associated with the elements of the graph, formulating the

basis for the estimation of travel times for emergency

vehicles along paths through the street system. The primary

tasks of the search system are the calculation of the mini-

mal travel times of vehicles to the site of the emergency

and the determination of quickest routes. The street system

model and the search system are developed at length in fol-

lowing sections.



The Response File and Response System


The response file is a collection of standard responses,

where a standard response lists the quantity of each type of

emergency vehicle to be dispatched to service the emergency.

The function of the response system is to translate a

response code into a list of required equipment.


The Inventory File and Inventory System


The inventory file is a current list of the available

emergency vehicles housed at each emergency vehicle station.

The inventory file also contains the current position of

each cruising vehicle. The primary function of the inventory









system is the assignment of emergency vehicles to the cur-

rent emergency based on the required equipment list formu-

lated by the response system and on the relative distances

of vehicles determined by the search system. In addition,

the inventory system determines if the required equipment

list can possibly be satisfied from the total aggregation

of available equipment, and informs the receptionist appro-

priately. Another task performed by the inventory system

is to record the positions of cruising vehicles based on

input information. Although it has not been indicated, it

has been assumed that the current positions of cruising

emergency vehicles are determined by some form of automatic

locator system.


The Length File and Length System


The length file contains information from which the

values of the parameters of the street system model are

estimated. The primary values estimated by the length system

are the emergency vehicle travel times with respect to the

various road segments of the street system. Although it is

beyond this work to specify how these travel time estimates

are calculated, it is assumed that they are obtained through

time dependent functions of properties of the roadways and

intersections. Obvious arguments of such functions might

be the physical length of the segment, the number and widths

of lanes, the conditions of the road surface, the use of









adjacent land, the pattern of parking, the traffic density

statistics, and the existence of any traffic control devices

(signals and stop signs).


The Dispatch System


Unlike the other systems of the processor, the dispatch

system contains no file of information. The function of the

dispatch system is to assemble the input information together

with the results of the search and inventory systems into an

intelligible text for each responding vehicle.



Additional Comments


Throughout the preceding discussion, presuppositions

on the architecture of the processor have been avoided. Any

or all of the systems described could be implemented as sub-

routines in a conventional uniprocessor, or as individual

hardware units. In the following sections of this text,

possible architectures for each system are considered,

though only the search system is considered in detail.

With respect to intercommunication among units, it is

assumed that all information is transmitted between systems

in packets called messages, and that the links between

systems are those indicated in Figure 4. In a subroutine

implementation, the transmission of messages corresponds

with the passing of argument lists.


__






20


Because the functions performed by the search system

comprise the core of automated emergency call processing

and are the most complex to satisfy, the search system is

treated first, beginning with the development of the street

system model.














A STREET SYSTEM MODEL


In this section, a street system model in the form of

a labeled, directed graph [BERGC 62] is developed. In the

graph model, a node represents an intersection, a point at

which a street changes name or direction, the end-point of

a cul-de-sac, or the location of a fixed station for emer-

gency vehicles, e.g., a fire house. Each node is assigned

a unique identification number, J. This number was referred

to in the discussion of the street index as an intersection

identification number, which for brevity will be called the

node number hereafter. An arc of the graph corresponds with

one direction of traffic flow along a street segment between

nodes. The search algorithm in the following section bases

routes on paths from the emergency site to the emergency

vehicles, while the vehicles travel in the opposite direction.

To correct for this, a roadway from node H to node T is

denoted [T;H] and is considered an arc with tail node T and

head node H. Similarly, characteristics of the roadway from

node H to T are associated with the arc from node T to node H

in the model.

An essential requirement of the street system model is

that it be possible to define a function on the labels of









the arcs and nodes which, for a given path, returns a satis-

factory estimate of emergency vehicle travel time with

respect to the corresponding path in the street system.

Towards this, two labels, LET;H] and DET;H], whose ranges

are the non-negative integers, are defined on each arc of

the graph. The label LET;H] is referred to as the length

of the arc [T;H], and is a current estimate of the effective

travel time for that arc. The second label, D[T;H], defined

on an arc is the geographical orientation of the roadway

with respect to some reference, e.g., East.

In addition to the length label, a binary impassability

indicator, X[T;H], is associated with each arc. This label,

which can be altered by the receptionist, is used to note an

exception to the length label, and indicates a blockage of

the associated roadway, causing the travel time of the road-

way to be infinite. Examples of the sources of such block-

ages are traffic accidents, open draw bridges, floods, wash-

outs, and rock falls. Clearly, if a path includes an arc

for which X[T;H] is one, indicating a blockage, then the

length of the path is undefined.

It is contended here that a satisfactory estimate of

the travel time for a given path in a street system can be

obtained inductively as a sum of the lengths of the constitu-

ent arcs of the path in the street system model plus penal-

ties on the turns in the path. The turning penalty proposed

here is a constant times the absolute angle turned. With

the arc orientations, D[T;H], scaled over the range 0 to K-1,









the turning penalty between arcs ET;H] and [H;I1 is

I(DEH;I]-D[T;H]) if this absolute difference is less than

KX2, and is K minus this absolute difference, otherwise.

The notational conventions used here have been adapted from

APL [IVERK 62, IBMRM 70], and are summarized in Appendix A.

The inductive method for obtaining path travel time

estimates is expressed formally as Procedure 1. The variable

WE[I is the estimate of the travel time along the path from

the initial node to the node J in the path. P[J] is the

predecessor node of node J in the given path.

In applying Procedure 1, the nodes are treated as they

are encountered along the path from the initial node, A,

to the terminal node. If a node is encountered more than

once (due to a loop or circuit), the previous value of E[I]

is replaced.

A number of additional labels are associated with the

arcs and nodes of the street system model; however, they

will be introduced in the appropriate sections which follow.

The model as currently developed is sufficient to proceed

with the development of the search algorithm.






24


Procedure 1: Path Travel Time Estimation

Basis:

W[A] 0

Induction:

DD I((D[T;H] D[P[f];T]) if (T2A)

DD K DD if (TtA)A(DD>K)2)

W[H] LET;H] if (T=A)A(X[T;H]=0)

W[H] WET] + L[T;H] + DD if (T#A)A(X[T;H]=O)















THE SEARCH ALGORITHM


The calculation of minimal travel times and quickest

routes for emergency vehicles in the street system model is

essentially the shortest route problem in graph theory, a

problem which has received considerable attention in the

literature [PAPEU 69]. The algorithms reported for the

shortest route problem generally differ in assumptions on

the properties of the graph, specific constraints on the

solution obtained, and the architectures of the machines on

which they are implemented, if machine calculation is pro-

posed. Because no reported algorithm satisfying all the

requirements of emergency call processing has been found, a

search algorithm is developed in this section from concepts

of a number of reported algorithms.

The algorithm developed here is representative of the

class of tree-building algorithms [FARBB 67], which deter-

mine the minimum distances of every node of the graph with

respect to one, arbitrarily specified node, the reference

node. The distance of one node from another referred to a

particular path is defined to be the length of that path,

and for current purposes, that quantity is obtained by

Procedure 1 of the previous section. In addition, let the









reference node be the node of the graph nearest the site

of the current emergency.

Tree-building algorithms are iterative processes which

apply a distance minimizing procedure to distance labels of

the nodes of the graph. The minimizing procedure replaces

the value of a node distance label, W[J], when a smaller

value corresponding with a shorter path is found. The pro-

cedure proposed here is based on the path travel time esti-

mation procedure (Procedure 1), and is given as Procedure 2.

Minimization of node distance labels proceeds as follows.

If YET;H] is less than the current value in WEH] (based on

another path or initialized to +-), then the path including

arc [T;H] is clearly shorter, and the 3-tuple of labels for

node H is replaced. Thus, the execution of Procedure 2 for

an arc [I;J] has the tendency to reduce the distance label,

W[J], of node J.

A necessary part of a tree-building algorithm is a

method or criterion for selecting the arcs of the graph for

which Procedure 2 is to be executed in each iteration. In

discussing the selection criteria, it is helpful to consider

the street system model as a collection of "forks." A fork

consists of a node, T, together with every arc, [T;H], inci-

dent out of that node, and is referenced by the node number

T. An example of a simple street system as a collection of

forks appears in Figure 5. An "application" of Procedure 2

to a fork is defined to be its execution for every arc of

the fork except the arc [T;P[T]]. There are two popular

























a) A simple street system

S10 22
4 10 22
10
10
6 6 6 6 66
10 12 10

2 0 5 10 12 5 5 10
10 12
10 12
Orientations ss 5
\'5 i5
12 10
12 10

b) The model with arc lengths

15
1FP-^--- P --------
36
4 -19


23 38


28
12 c 43

47
33

c) The model as a collection of forks, showing
a numbering on the nodes


Figure 5. An example of a street system model.


I










Procedure 2: Path Travel Time Minimization

Basis:

W[1~N] + 1
WE1-N3 c

Q[1~N] 0

P[I~N] + 0

WE[A] 0

Induction:

DD + I(D[T;H] Q[T]) if (T;A)

DD + K DD if (TWA)A(DD>Ki2)

Y[T;H1] L[T;H] if (T=A)A(X[T;H]=0)

Y[T;H] W[T] + L[T;H] + DD if (TrA)A(X[T;H]=0)

(Q[H],WIH],PEHI) + (D[T;H],Y[T;H],T)
,if (Y[T;H] A(X[T;H]=0)A(P[T]H)






















NOTE: QEJ] is a simplified notation for D[P[J];J].









selection criteria, and these segregate the tree-building

algorithms into two major classes.

One class of tree-building algorithms, which includes

the algorithm by E. F. Moore [MOORE 59], applies Procedure 2

to every fork whose node distance label was reduced in the

previous iteration. In the first iteration, the distance

label of the reference or site node is reduced to zero. The

operation of a Moore type algorithm is illustrated in Figure

6 for the sample street system of Figure 5. In each sketch,

the results of an iteration are shown, with the nodes for

which Equation 2 was applied, shaded. The numbers by the

nodes indicate the values of their distance labels at the

end of the iteration. A turning penalty of 1 unit was

assessed on each turn. The arcs shown indicate the values

placed in P[J].

The second class of algorithms, including one by E. W.

Dijkstra [DIJKE 59], treat only one node in each iteration.

The node treated is the one which has the least value in

its distance label and which has not been treated previously.

The operation of an algorithm with this selection criterion

is illustrated in Figure 7.

It is appropriate to observe implications of these two

selection criteria on the structure of a processor in which

an algorithm is to be implemented. With the Moore criterion,

a number of applications are required in each iteration, and

these applications can be performed independently (and thus

simultaneously). This would suggest the appropriateness of




























(a) (b)



23 20 33 23 20

19 29 19

22 12 0 10 22 12 0 10
28 18 18

23 21 23
10 10 21


(c) (d)


33 23 20

29 19

2. 12 0 10

28 12
23 10 21


(e)














Figure 6. The operation of the Moore algorithm on the
model of Figure 5 for the site at node 38,
showing the distances of the nodes.











(a)


(d)


(e)


(h)


(g)




(j)
(j)


(k)


(1)


Figure 7. The operation of the Dijkstra algorithm on the
model of Figure 5 for the site at node 38.


(b)


0-


7e




































(0)


Figure 7.


(continued)


(p)









a parallel or multiprocessing machine. In a very large

graph, such as for a large city, the number of processing
units would have to be quite large to fully exploit this

parallel processing potential of the algorithm. Conversely,

the Dijkstra method requires only one application of Pro-

cedure 2 per iteration, each requiring very few executions.

This would tend to indicate a possible preference for a

conventional uniprocessor. In a very large graph, the total

processing time with a single processing unit could cause

this technique to be impractical.

In the following, a selection criterion is developed

through which the required number of applications of Procedure

2 per iteration may be controlled to suit the number of

parallel processing units of a given machine. This criterion

is developed from the Moore method, but is readily reduced to

either the Dijkstra or Moore criterion. As an introduction

to the development, a limitation of the Moore criterion with

respect to the emergency call processing problem is con-

sidered.

The Moore method has a rather serious drawback in that

the minimal distance of no node is known until all minimal

distances have been determined through an exhaustive search

of the graph. All distance labels contain the minimal dis-

tances with respect to the reference node when, for some

iteration, no further applications of Procedure 2 occur.

In a very large city, it is likely that a majority of

searches can be satisfied by the emergency vehicles stationed








in a relatively small radius, R (in travel time), about the

emergency site. Such cases would include police and pos-

sibly ambulance services. By adding a constraint deferring

applications of Procedure 2 whenever WC[T>R, a partial solu-

tion is obtained in which the distance labels of all nodes

whose minimal distances are within R of the site will con-

tain their minimal distances. The valid partial solution

is obtained when applications for W[TI
The preceding assertion may be restated as W[I]=Z[I],

if Z[I]3R. Z[I] is the true minimal distance of node I from

node A obtained by employing Procedure 1 along a shortest

route from A to I. This assertion is validated through con-

tradiction. Assume that Z[I]
were true, then Z[I] would not be the true minimal distance.

Now, consider that Z[I]Z[I]. Let PZ[I] be the

predecessor of node T in some shortest route from A to I.

Note that Z[I]>ZEPZ[I]] since all arc lengths of a street

system model are positive, and no turning penalty can be

negative. Thus, Z[PZ[I]]
W[PZ[I]]>Z[PZ[I]], for if they were equal, Procedure 2

would have been applied to node PZ[I], and Z[I] would be

equal to W[I]. This argument can be carried back along any

shortest route to node A, with the implication that W[A]>Z[A].

Clearly, this is absurd, since W[A] is zero by definition,

and necessarily Z[A]=W[A]. This contradiction requires that

W[I]=Z[I], provided Z[I]








In addition to having determined the minimal distances

of all nodes for which Z[I1
the predecessor labels, P, of the nodes may be used to trace

a shortest route from such a node to the reference node, A.

Clearly, the roadway [I;P[I]] is in a shortest route from

node I if Z[I]
Similarly, W[PCI]] was based on [PEPCIl];P[I]], and thus,

the roadway [PII];P[P[I]]] is in a shortest route to node

P[I] and subsequently to I. This argument can be carried

back until node A is reached.

An algorithm employing Procedure 2, and a constraint,

R, on applications of Procedure 2 is presented as Algorithm

1. An iteration is completed every time step CYCLE is

executed. In this algorithm, the label I[T], when set to

one, is used to indicate that an application of Procedure 2

has been deferred. The nodes of the graph are considered

for application of Procedure 2 in increasing order of their

identification numbers through the incrementing of T. The

head node numbers of the arcs incident out of a node are

represented in a successor array, S, which has a row for

every node and a number of columns equal to the greatest

number of arcs incident out of any node of the graph. The

head node numbers are left justified in the rows, with zeros

entered in any unused locations. The algorithm step DONE

is a trap which is entered when applications of Procedure 2

(counted by C) cease.








Algorithm 1: Shortest Route Algorithm


INITIALIZE: Initialization of all variable node labels.

C 0
T 0
Q[1N] + 0
P[l~N] + 0
W[1~N] + MX
I[1CN] 0

INITIATE: Setting of the labels for the site node.

WEA] + 0
I[A] + 1

ITERATION:

NODE: Selection of the next node for application
of the minimizing function.


T T+1
C CYCLE
+ NODE
IH <- 0


,if (T>N)
,if (I[T]=0)v(W[T]>R)


APPLY: Application of the minimizing function.


IH IH+1
H + S[T;IH]
- RESET
+ APPLY
DD + oD[T;H]-Q[T])
DD + K-DD
Y[T;H] + W[T]+L[T;H]+DD
Y[T;H] + LET;H]
(Q[H],W[H],I[H],P[H]) +

C + C+1
- APPLY


,if (H=0)
if (X[T;H]=1)v(P[T]=H)

,if (DD>K2)
if (W[T']0)
if (W[T]=0)
(DET;H],Y[T;H],1,T)
if (Y[T;H] if (Y[T;H]

RESET: Resetting of deferred status following
application.

I[T] 0
NODE









Algorithm 1 (cont.)


CYCLE: Testing for termination and preparing for the
next iteration.

DONE if (C=O)
C 0
T+ 0
-+ NODE

DONE: Termination trap.

DONE


NOTE: The value of MX must be greater than the
longest minimal distance from A to any node of the graph.
S[T;IH] is the IHth successor of node T.









Returning to the question of controlling the number of

applications of Procedure 2 per iteration, the parameter R,

introduced in Algorithm 1 for partial searches, has a much

broader interpretation. If R is varied during the processing

of the algorithm, it may be used to indirectly limit the

number of applications of Procedure 2 per iteration.

Examples of this property are illustrated in Figures 8 and 9

for the sample street system of Figure 5. In each of these

cases, R is initially zero, and is incremented by a fixed

amount, DELR, with each iteration. Table 1 summarizes the

results of the various selection criteria for the examples

of Figures 6 through 9. Note that if DELR is greater than

the longest arc, the selection criterion is-essentially the

Moore method. As DELR is reduced, the behavior of the

Dijkstra method is approximated, and if R is set to the

minimum of the WEll for the nodes not yet treated, the

Dijkstra method is obtained. Thus, the selection criterion

with a variable R is a generalization of the Moore and

Dijkstra criteria.

A necessary function of the search algorithm is that

it recognize the positions of emergency vehicles. Let a

binary flag, EEI] be associated with each node of the graph.

If an emergency vehicle of a type required for the current

emergency is stationed at the node I, or if cruising, will

encounter node I next, let the value of E[I] be set to one.

When the value of W[I] for a node with E[I]=1 falls below R,

it is known that a partial solution for R.will provide a
























a) R=O










d) R=15









g) R=30


b) R=5










e) R-20









h) R=35


c) R=10










f) R=25


Figure 8. The operation of the search algorithm on the
model of Figure 5 for the site at node 38, and
the control parameter, R, incremented 5 units
per iteration.
















b) R=4


d) R=12


g) R=24


e) R=16


h) R=28


f) R=20


i) R=32


j) R=36



Figure 9. The operation of the search algorithm on the
model of Figure 5 for the site at node 38, and
the control parameter, R, incremented 5 units
per iteration.


a) R=o


c) R=8


0 0--











Table 1

Characteristics of the Selection Criteria for Shortest
Route Algorithms on the Sample Street System of Figure 5


Criterion Moore DR=5 DR=4 Dijkstra

Figure 6 8 9 7


Iterations 5 8 10 16


Total applications of Procedure 2 17 16 16 16
Average applications per iteration 3 2 1.6 1
Maximum applications per iteration 6 4 4 1




Total executions of Procedure 2 29 28 29 28
Average executions per iteration 5.8 3.5 2.9 1.8
Maximum executions per iteration 10 6 7 4









shortest route for node I. Let the identification numbers

of the nodes for which E[I]=1 be stored in a variable length

vector, EV, as their WEI] fall below R. When all vehicles

represented by the nodes contained in EV are sufficient to

satisfy the current emergency, let the value of R be held

constant to terminate the search. This is accomplished by

setting a halt signal to one [HLT=11. The detection of

emergency vehicles and a variable R are included in Algorithm

2.

Throughout the development of the search algorithm, it

was assumed that a single reference node would suffice.

When an emergency occurs along a street segment, however, it

would be preferable to designate the two intersections adja-

cent to that segment as reference nodes. This is easily

accomplished with the algorithms described in this section,

by simply initializing the distance labels of both desired

reference nodes to zero at the beginning of the search. The

result of the search, then, will place in the distance label

of each node the least distance of that node with respect to

the closer of the two reference nodes.

This property of the algorithms is generally true in

that the results of a search will give the least distance

(and shortest route) of each node to the closest of any

reference nodes. This property is particularly useful in

providing ambulance services. Once an ambulance reaches the

site of an emergency, it may have to travel to the closest

emergency medical treatment center as quickly as possible.








Algorithm 2: The Search Algorithm


INITIALIZE: Initialization of all variable node labels.

W[1~N] + MX
Q[1-N] + 0
P[1~N] + 0
I[1~N] + 0
T 0
C+ 0
R 0
EV lO
HLT + 0

INITIATE: Setting of the labels for the site node.

WEA] + 0
I[EA] 1

ITERATION:

NODE: Selection of the next node for application
of the minimizing function.


T + T+1
- CYCLE
- NODE
IH +- 0
-+ APPLY


,if T>N
,if (I[T]=0)v(W[T]>R)


, if (E[T]=0)


UNION: Forming set union of T and EV.


- APPLY
EV EV,T


, if ((EViT)>pEV)


APPLY: Application of the minimizing function.

IH + IH+1
H + S[T;IH]
RESET if (H=0)
APPLY if (X[T;H]=1)v(P[T]=H)
DD + ID[T;H]-Q[T]
DD + K-DD if (DD>K-2)
Y[T;H] + W[T]+L[T;H]+DD if (W[T]O0)
Y[T;H L[T;H] if (W[T]=O)
(Q[H],W[H],IL[H],P[H]) + (D[T;H],Y[T;H],1,T)
if (Y[T;H] C -<- C+l if (Y[T;H] APPLY








Algorithm 2 (cont.)


RESET: Resetting of deferred status following
application.

I[T] + 0
NODE

CYCLE: Testing for termination and preparing for the
next iteration.


DONE
T 0
C 0
R + R FCN C
NODE

DONE: Termination trap.

DONE


, if (HLT=1)A(C=0)


NOTE: FCN is an-unspecified function of R and C
which determines the next value of R.









The emergency site cannot be used as the reference node

because the direction of the route will be wrong, and sym-

metry of the graph cannot be assumed. Instead, each medical

center is considered to be a reference node, and the emer-

gency site, A, is designated to be the sole emergency vehicle

station (E[A]+1). This will route the ambulance properly to

the nearest treatment center.

The development of Algorithm 2 concludes the analysis

of the emergency call processing problem, the identification

of the data base, and the adoption of a general processing

procedure. Before turning to the computer architecture, a

summary of the features of Algorithm 2 related to machine

structure is appropriate.

Algorithm 2 specifies a scan of the entire street system

model in each iteration, presupposing the inherent character-

istics of cyclic access storage for the model. Complete

scanning could be easily avoided by adopting one of the many

reported indexing or bookkeeping schemes developed for

random access storage, e.g., [BRAED 71, HITCL 68].

By generalizing on the selection criteria of Moore and

Dijkstra, the number of parallel processing units in the

machine can be determined on the bases of cost and perfor-

mance, rather than to suit peculiarities of an algorithm.

The control parameter, R, also provides a mechanism for

heuristic control of the search. Such control may be desir-

able when searches are conducted in sections of a street






46


system model having widely varying characteristics, or when

a processing unit fails in a parallel machine.














A SEARCH SYSTEM ARCHITECTURE


In this section, a special purpose processor architec-

ture specifically organized for application of the search

algorithm of the previous section to very large street system

models is proposed. The proposed architecture exploits the

characteristics of inexpensive, cyclic access storage devices,

and provides a high potential for dependable operation through

a highly repetitive structure. The architecture is character-

ized in Figure 10, and comprises a set of synchronized, cyclic

access memories, a set of identical processing cells in one

to one correspondence with the memories, a hierarchical

access structure, and a simple global controller. The basic

repetitive "unit" of the structure includes a commutator seg-

ment, a channel, and a group of associated processing cells

and cyclic memories. This structural repetition not only

permits the size of the processor to be matched to the street

system model for a given city, but more importantly, con-

tributes significantly to the dependable operation of the

machine. These and other questions of cost and dependability

are discussed in the next section in which the proposed

architecture is evaluated against the emergency call pro-

cessing problem and against some other possible approaches.










Cyclic Memories


Processing
Cells


Access Structure

Channels Commutator


System
Input/Output


Global
Controller


Figure 10. The proposed search system architecture.









The current section is devoted to the description of the

proposed search system architecture.

Each cyclic memory of the processor contains represen-

tations of a number of forks of the street system model, and

behaves as a long, cyclic shift register, a small part of

which is contained in the associated cell. The portion of

the cyclic memory in the processing cell is the only part

which is immediately accessible to the cell for operations

on or modification of the contents of the memory. The re-

mainder of the cell is essentially a hardware realization of

procedures through which the search algorithm and related

tasks are effected. The evocation of these procedures is

governed by major state signals broadcast to all cells by

the global controller. The global controller also determines

and broadcasts values of the algorithm control parameter, R.

In order to simplify the cells as much as possible, a

cell has no storage for retention of operands for periods

greater than the time required for a fork representation in

its cyclic memory to pass through it. The necessary tempo-

rary storage of operands and partial results is provided by

the access structure. A cell requiring temporary storage

forms a message which includes the data together with the

destination address of the data. This address alludes to

the representation of some fork of the street system model.

The major element of the access structure is the channel.

A channel consists primarily of content-addressed storage,

storing and delivering all messages destined to the cells









with which the channel is connected. Each channel is asso-

ciated with a group of cells, and both the delivery and

collection of messages are performed using a pair of buses:

one from the channel to all cells of the group, and one from

the cells to the channel. Messages which must traverse cell

group boundaries or are to or from other systems of the

emergency call processor are placed into the commutator by

the channels.

The commutator is merely a cyclicly connected set of

shift registers, one of which is associated with each channel

and one with the global controller. In addition to a shift

register, each commutator segment contains the logic required

to detect a message destined for a cell in the group served

by its associated channel. As may be noted in Figure 10,

the global controller serves as the input/output port of the

search system, as well as providing generalized control

signals.

In the remainder of this section, a number of the more

important aspects of the proposed architecture are considered

in some detail. Although the logical designs of the cell

and channel circuits are beyond the scope of the present

work, a partial example is included for illustration. The

first consideration in the proposed architecture is the

storage of the street system model in the cyclic access

memories.








Storage of the Street System Model


The contents of a cyclic access memory of the processor

may be viewed as a long string of words passing through its

associated cell as illustrated in Figure lla. Each word is

composed of a fixed number of bits, and is used to store all

labels of one arc or node of the street system model. All

cyclic memories of the processor have the same number of

words, and the Jth word of every memory passes into its

associated cell at the same instant. It is convenient to

define a "word time" as the lapse between the entries of two

successive words of a memory into a cell. The "cycle time"

of the memory is the time for every word of a memory to pass

through its cell precisely once.

The address, AD, of any word is given by three numbers,

AD[11, AD[2], and AD[3], where AD[3] is the least significant

part of the address. AD[11 is the number of the word in its

cyclic memory. AD[21 is the number of the memory (or cell)

in its unit, and AD[31 is the number of the unit in the

processor. (The global controller and its commutator segment

form the zeroth unit of the processor.)

The storage of the labels of the arcs and nodes of the

street system model in subfields of memory words is illus-

trated in Figure llb. The words containing node labels are

called node records, and those containing arc labels, arc

records. The identification number of a node is not stored

in the node record, but rather, the address of the word is


















a) Word organization of the cyclic memory storage


1JE Q W I P
Node Record
OX D L I H


Arc Record


emergency vehicle indicator
predecessor arc orientation
a distance to node T
deferred status indicator
predecessor node number
impassability indicator
arc orientation
arc length
deferred status indicator
head node number


b) The fields


of the memory words


SNode I Arc Arc I Arc J

c) The composition of a fork record as a node record and
a set of arc records.



Figure 11. The storage organization of the street system
model elements in the cyclic access memories.


E[T]
QET]
WET]
lIT]
PET]
X[T;H]
D[T;H]
L[T;H]
IET;H]









used for the node number. This is possible since all address

numbers are unique, and no particular number scheme is imposed

by either the modeling technique or the search algorithm.

It may be recalled from the previous section that the mini-

mizing function for the search algorithm is applied to forks

of the model, and that the execution of the function on an

arc of a fork requires as operands, values of labels on the

arc and labels of the node of the fork. Therefore, it is

appropriate to adopt the convention of a fork record as

illustrated in Figure llc. With the record format shown, the

tail node number of an arc need not be stored, since it is

the address of the last node record to pass into the cell.

The field F of the memory words is used to distinguish be-

tween node and arc records, and also serves to indicate the

first word of a fork record. To illustrate the representa-

tion of a street system model in a cyclic memory, the example

of Figure 5 is represented as a collection of fork records

in Figure 12, and the storage of the fork records in a

single cyclic memory is shown in Figure 13.

Each memory word has six fields. Though the fields have

differing lengths (numbers of bits) to conserve storage, the

respective fields in all words are equal. The lengths of

these fields are tailored to the ranges of the labels they

contain. The length of the fourth field need not be suffi-

cient for the greatest arc length, since long arcs can be

easily segmented by the introduction of artificial nodes.

The representation of W is, however, a problem. It is









L tI\ H IFIXID I L III H IFIXID I L I1 I H FIX D 1 L lII H


111 0I I0 10 15 10 3 4 4


S0I I 101 10 10 19 0 1 4 1 30 3 6 8
1 I I 0 0 10 23 0 1 6 1 0 3 5 12
1 0 I I 101 10 0 10 28 10 1 5 8 I
I1 10 I1o' 0 22 51 10 2 10 1 10 3 4 19
,1 1 i 0 1 1 4 15 10 2 10 4 10 1 3 6 23
S I I I i o o 1 121 138 o0 1 1 6 1 I1 9q l I1 I n I I P inl I I I i 01 i


ill


0lo I 12 -
!o Io I 121i


S43 jO


1 I 5 I
hllsl


23 I I


2 1-0 I 12 I vl 13 1 j 1 33o I
12 Ilo I 112 l I o 3 1 5 1 t33 1


8
12
15
19
23
28
33
36
38
43
47


t !o0 1o0
I I 10 I 12
-I 10 12


10 158 jO I
221 115 Io1


3 9


143101jn


154


51 111 I I
54 11
5 8 l


I I to I1 I
I I oi I1 I


9 151 0 o
111 154 10


12 110
12 o10


138 10
147 1


13 11 158 1


Figure 12. The representation of the
of fork records.


street system of Figure 5 as a collection


1
4


SI I01 0 12 47 10 1 5 28
F7 1 I10 I3 6 38!
i 1 I I0 lo1 1 1 10 1 5 t4 0 1 6 36 I0 2 12 23 lo0 3 5 I 143
1~ 1 i I I l 11 5 I 138 o0 l 2 1 121 128 10 I 3 I 5 I 147 I


1T


Fl


II 1 5 j


Z


f


Z


' I


I


I


z


133 |


I-- 1 I I- 1-- 1 1I 1


I


L --i I I


)


r I I I i I


I


1 10 1 1' 1 1 I I l


TIFIEIQ I W \Il P IFIXID I


I


!






















ad-Write
Head


15
54
51 54
1 \ 15
1
19 51



23
23 47 47
38 28
19 38:
8
23
2 443



33 36 38




Figure 13. The serial storage of the fork records of
Figure 12 in a cyclic memory, showing
addresses and head node numbers.









desirable to avoid having the fourth field of every word

long enough to represent the greatest travel time through

the city. Instead, the nature of the algorithm is exploited

such that a relatively small field will suffice. Consider

that a search is suspended when a tentative distance, Y[T;H],

computed for some arc would tend to overflow the field for

W[H]. The suspension of the search is effected by fixing R

at some value, say R', until applications of the minimizing

function cease. The search could be easily resumed by in-

creasing R again, but instead, all vehicles found in the

partial solution for R' are dispatched. Then, all node

labels having values not greater than R' are set to zero,

and R' is subtracted from all node labels greater than R',

but less than the initialized value in W. Finally, the

control parameter is reset to zero, and the search resumed.

Although the values found for nodes not contained in the

partial solution for R' will be in error by a factor of R',

only the relative distances of the remaining nodes are impor-

tant in selecting the additional required emergency vehicles.

Since the values in the field P are not affected by this

process for overflow avoidance, routes can be traced back to

the site for any vehicle. The procedure can be repeated any

number of times in an extensive search, so there is no limit

on the extent of searches due to limited field lengths.

In support of later discussions and examples, estimates

of the sizes of fields and the number of words for a city of

one million persons are listed in Table 2. The estimate of










Table 2


Estimates of the Ranges of Street System Parameters


Representation
Label Resolution Minimum Maximum (bits) Remarks

F 1 binary


X,E 1 binary


D,Q 0.7 degrees 0 deg degr3593 deees 2 sec. penalty
D for 900 turn

L,W 0.016 seconds 0.016 seconds 17 minutes 16


I 1 binary


H,P 1 1 262,143 18


Notes: A city with a population of one million persons would have about
25,000 nodes and 75,000 arcs. This would require about 4.6 million
bits of storage, where each word would have a length of 46 bits.









the number of arcs in a street system model was based on the

Address Coding Guides [USBCA 70] of seven large cities in

Florida. The estimate of the number of nodes was obtained

indirectly through the ratio of arcs to nodes for the section

of street system shown in Figure 14. Figure 14 corresponds

with about four square miles of Gainesville, Florida. The

remaining estimates should be self-explanatory.


Messages


In an execution of the search algorithm, each processing

cell essentially behaves as a subroutine with respect to each

fork record passing through it. Drawing on this analogy, the

information in the fork record is complemented by information

passed to the cell in an argument list or message. Similarly,

the results and partial results, such as tentative distances

Y[T;H], are embedded in messages by the cells and passed

back into the access structure.

For consistency, it is convenient to assume that as each

word of a memory passes through its associated cell, the cell

receives one message and generates one message, either or

both of which may be null or empty. In order to employ the

access structure for passing as much of the necessary infor-

mation to and from the cells, the concept of a message is

generalized. The generalized form of a message together

with the interpretations of a number of types of message are

given in Table 3.


























































Figure 14. A section of the street system of Gainesville,
Florida.









Table 3

The Search System Messages


Null: OP=0
Contents: MGE[ ;1~8]
Remarks: This is a null or empty message, and indicates
the absence of any other message.

Search: OP=1
Contents: MGE[ ;1~8] = (1,H,-,-,D,Y,-,T)
Source: The arc record [T;H], or the street index system.
Destination: The node record H.
Remarks: When received, this message may cause the
replacement of (Q[HI, W[HI, P[H]) by (D,Y,T)
of the message, with the subsequent generation
of search messages from the arc records of
fork H.

Station: OP=2
Contents: MGE[ ;1-8] = (2,P,-,-,Q,W,-,T)
Source: The node record T.
Destination: The inventory system.
Remarks: A station message is generated when (E[T]=1)
A(W[T]sR) and informs the inventory system
that the vehicles) at node T has been found.

Trace: OP=3
Contents: MGE[ ;1~8] = (3,P,-,-,Q,W,-,T)
Source: The node record T.
Destination: The node record P.
Remarks: These messages are used to trace routes from
station nodes or emergency vehicles to the
site node.

Route: OP=4
Contents: MGE[ ;1~88] = (4,P,-,-,Q,W,-,T)
Source: The channel serving the cell whose memory con-
tains the node record for P.
Destination: The dispatch system.
Remarks: These messages are copies of trace messages
made in the channels to provide the dispatch
system with the shortest routes.

Eset: OP=5
Contents: MGE[ ;1~8] = (5,T,-,E,-,-,-,-)
Source: The inventory system.
Destination: The node record T.
Remarks: These messages alter the emergency vehicle
indicators, E[T], in the node records.









Each message contains a code, OP, a destination address,

AD, and a block of data whose internal format is comparable

with that of a word of memory. The message codes govern the

interpretation of the message as indicated in Table 3. The

destination address specifies the unit and cell to which the

message is to be delivered, and the time or word number

during which it is to be delivered.

The messages of principal interest here are the search

messages (OP=1), for these are essential to the execution of

the search algorithm. Consider that a 3-tuple, (DET;H],

Y[T;H], T) is formed in a processing cell as the arc record

for [T;H] passes through it. The conditional replacement

of the 3-tuple of node labels (QEHI, WEH], P[H]) essential

to the minimization of node distance labels, must occur as

node record H passes through its respective cell. In fact,

the test YET;H]
tion of a search message is to carry the 3-tuple (D,Y,P)

from arc record [T;H] to node record H. It is possible,

however, that the generation of a search message may have to

be delayed or deferred. One possibility is that WET] exceeds

the value of the control parameter, R, during that particular

cycle of the memory. Another is that the bus to the channel

is busy, or the channel cannot accept another message at the

time. In either event, the deferred status flag, I, is set

to one in that arc record, such that the message will be

generated spontaneously in a later cycle as conditions permit.









The generations, lifetimes, and deliveries of search

messages are illustrated in Figure 15 for a search on the

sample street system of Figure 5. The search illustrated

is essentially the same as the one depicted in Figure 8.

Note that the search is initiated by an externally generated

search message.

The interactions between messages and memory words are

illustrated in Table 4. The examples refer to the search

illustrated in Figure 8. Example A shows the initiation of

the search by the externally generated message (1,38,-,-,0,

0,-,0) delivered to fork 38. In addition to reducing W[38]

from its initial value of 99, the message stimulates the

generation of further search messages from arcs stored in

words 39 through 42. One of these messages is delivered to

fork 43, but the generation of further search messages from

the arcs stored in words 45 and 46 is deferred because the

new value of W[43] at 5 is still greater than R at zero. The

appropriate messages are generated in the next cycle as shown

in Figure 15. Note that the deferred status flags are set in

the arcs (I[43;281 and I[43;471) rather than in the node flag

I[431. This permits the node flags to be used without ambi-

guity when the generation of a trace or search message must

be deferred.

Example B illustrates the reduction of W[1i in cycle 8

of the search from a greater value found in cycle 7. This

reduction is the result of the path including the arc [15;1]

being longer than the one with arc [4;1]. Example B also
























































O -Generation o -Delivery A -External Generation

Figure 15. The generations, lifetimes, and deliveries of
search messages for the example of Figure 8
stored as in Figure 13.











Tab le 4


Examples of Interactions Between
Messages and Memory Words


Information Ingressing the Information Egressing the
Processing Cell Processing Cell

-Delivered Message Memory Word Generated Mlessage Memory Word
3. 0 MGE[1;1~8] CM[1;1~6] MGE[2;1~8] CM[2;1~8]
So > F E Q W I P F E Q W I P
SlJ F X D L I H F X D L I H
A 0 1
38 (1,38,-,-,0, 0,-, 0) 1 0 0 99 0 0 (0, -,,-,-, -,-, -) 1 0 0 0 0 0
39 (0, , ,, -) 0 0 0 10 0 54 (1,54,-,-,0,10,-,38) 0 0 0 10 0 54
40 (0, -,-,-,-, -,-, -) 0 0 1 6 0 36 (1,36,-,-,1, 6,-,38) 0 0 1 6 0 36
41 (0, ,-,-,, -) 0 0 2 12 0 23 (1,23,-,-,2,12,-,38) 0 0 2 12 0 23
42 (0, ,-,-,, -) 0 0 3 5 0 43 (1,43,-,-,3, 5,-,38) 0 0 3 5 0 43
43 (1,43,-,-,3, 5,-,38) 1 0 0 99 0 0 (0, -, -) 1 0 3 5 0 38
44 (0, ,-,-,, -) 0 0 1 5 0 38 (0 --,-,-, ,-, -) 0 0 1 5 0 38
45 (0, -,-,-,-, -,-, -) 0 0 2 12 0 28 (0, -, , -) 0 0 2 12 0 28
46 (0, ,-,-,, -,, -) 0 0 3 5 0 47 (0, ,-,-,, -,-, -) 0 0 3 5 1 47


B 35 8
1 (1, 1,-,-,1,33,-, 4) 1 1 2 34 0 15 (2, 4,-,-,1,33,-, 1) 1 1 1 33 0 4
2 (0, -,-,-,-, -,-, -) 0 0 0 10 0 15 (1,15,-,-,0,44,-, 1) 0 0 0 10 0 15
3 (0, -,-,-,-, -,-, -) 0 0 3 4 1 4 (0, -,-,-,, -) 0 0 3 4 1 4
4 (0, -,-,-,-, -,, -) 1 0 1 29 0 8 (0, ,-,-,, -,, -) 1 0 1 29 0 8

C -
54 (3,54,-,-,1,20,-,51) 1 0 0 10 0 38 (3,38,-,-,0,10,-,54) 1 0 0 10 0 38









shows the generation of a station message, (2,4,-,-,1,33,-,1),

from node 1 as the value of R at 35 goes above the value of

WC1i at 33. (Note that E[1] was set to 1 for this example.)

Example C shows part of the tracing of the shortest route

from node 51 with trace messages following a search.


The Processing Cell Procedures


As mentioned earlier, the search algorithm is effected

through procedures applied by each cell to the fork records

and messages passing into the cell. Three procedures are

considered here. One, the search procedure, realizes the

minimizing function of the search algorithm, instruments the

tracing of shortest routes, and facilitates the alteration

of the emergency vehicle indicators of the node records.

The second procedure, the initialization procedure, causes

the initialization of the various fields of the node and arc

records employed in a search, and the third procedure, the

overflow avoidance procedure, resets the values in the node

distance fields in order to avoid overflow. These procedures

are stated below as Procedures 3, 4, and 5, respectively.

To help point out the roles of these procedures in

realizing the search algorithm, it may be noted that Procedure

4 corresponds with the step INITIALIZE of Algorithm 2. Step

INITIATE of the algorithm is performed by Procedure 3 when

a search message is received from the street index system








Procedure 3: Search Procedure (MS=1)

Note: This procedure is applied to every fork record
of the street system model in every cycle.


FORK: Test the current memory word as a node or arc record.


F + CME1;1]
CT + NC CT+1
CM2;11] + F
- NODE
- ARC


NODE: The current memory word is a node record.

T + CT,CLN

INPUT: Receive message and memory word.

(OP,AD,EX,QD,WL,PH) MGE[1;1,2,4-6,8]
(E,Q,W,I,P) + CM[1;2~6]
OP + 0 if (2+AD)#CLN

REPLACE: Conditionally replace node labels and test values.


, if (WL , if (OP=I)A(WW=I)
,if (OP=1)A(WW=1)
, if W , if W=0


, if (OP=5)


, if (F=l)
, if (F=0)


SENDN: Tests for generation or
and trace messages.

SND + 0
SND + 2

SND + 3

I + 1

I + 0


deferring of station



, if ((E=1)A(W A((I=I)v(OP=I)))
, if ((E=0)A((I=1)
v(OP=3)))
if ((SND~O)A(CH=1))
v((I=1)A(WR=0))
,if ((SND/ O)A(CH=O))


OUTPUTN: Send message and overwrite memory word.

MGE[2;1~8] + (SND,P,O,O,Q,W,O,T)
if ((SNDO)A(CH=O))
CM[2;2~6] <- (E,Q,W,I,P)
FORK


WW + 1
(Q,W,P) + (QD,WL,PH)
RPL 1
WR + 1
WZ 1


SETE:


E EX









Procedure 3 (continued)


ARC: The current memory word is an arc record.

INPUTA: Receive memory word and compute distance.

(X,D,L,I,H) + CM[1;2~6]
DD ID-Q
DD K-DD if (DD>K-2)
Y W+L+DD if WZ;1
Y L if WZ=1
OV Y2MX

OVFL: Test for overflow.

OFL + (OV=1)A(HiP)A((RPL=1)v(I=1))

SENDA: Test for generation or deferment of search message.

DNS (OV=1)v(H=P)v(X=1)
SND + 0
SND 1 if (DNS=O)A(WR=1)
A((RPL=1)v(I=1))
I + 1 if ((SND=1)A(CH=1))
V((I=I)A(WR=O))
I 0 if ((SND=1)A(CH=0))

OUTPUTA: Send message and overwrite memory word.

MGE[2;1~8] + (SND,H,O,O,Q,W,O,T)
if ((SND;0)A(CH=O))
CM[2;2~6] R (X,D,L,I,H)
-> FORK








Procedure 4: Initialization Procedure (MS=2)

Note: This procedure is applied to every fork record
through one processor cycle to initialize the
node labels for a search.





FORK: Test current memory word for node or arc record.

F CM[1;1]
CT +NCICT+1
CM[2;1] < F
NODE if (F=l)
ARC if (F=0)

NODE: The current memory word is a node record.

(E,Q,W,I,P) + CM[1;2~6]
(E,Q,I,P) + (0,0,0,0)
W + MX
CM[2;2~6] (E,Q,W,I,P)
-) FORK

ARC: The current memory word is an arc record.

(X,D,L,I,H) +- CM[1;2~6]
I F+ 0
CM[1;2-6] + (X,D,L,I,H)
FORK









Procedure 5: Overflow Avoidance Procedure (MS=3)

Note: This procedure is executed exactly once on every fork
record as soon as the searcn terminates by holding K
constant when overflow is detected during the search
procedure. After executing this procedure over one
cycle, R is reset to zero and the search resumed by
re-entering major state 1.



FORK: Test the current memory word for node or arc record.

F CM[1;1]
CT +NCI CT+1
CM[2;1] + F
NODE if (F=l)
ARC if (F=0)


NODE: The current memory word is a node record.


(E,Q,W,I,P) < CM[1;2~6]
WR + (W W W-R
W 0
CM[2;2~6] + (E,Q,W,I,P)
- FORK


, if (WR=O)A(WMX)
, if (WR=1)


ARC: The current memory word is an arc record.


- FORK








having the site node as its destination address, and the

field corresponding with Y set to zero. Procedure 3 also

performs the operations in the ITERATION step of the algo-

rithm. The steps CYCLE and DONE are performed by the global

controller. Procedure 5 has no analog in Algorithm 2, since

the range of the label W was not restricted in that section.

The procedures executed by the cells are mutually

exclusive in that no two are ever evoked simultaneously in

any cell for any record. In fact, exactly one of the pro-

cedures is executed in every cell of the processor at any

time, and this procedure is the same in all cells. There-

fore, it is convenient to associate with each procedure a

major state, MS, of the processor. The procedure evoked in

each cell is determined by the global controller which broad-

casts the major state of the processor.

The description of the activities of the cell by Pro-

cedures 3, 4, and 5 is sufficiently precise to permit the

consideration of the architecture of the cell next.


The Processing Cell Architecture


The architecture of the processing cell must, of course,

support Procedures 3, 4, and 5, but the cell does not need

to be programmable since neither the algorithm nor the

storage structure is likely to vary. To help define neces-

sary terminology, consider the general description of the

cell illustrated in Figure 16.







































MW -- ---


Processing Cell
-- j----------*---------------


Control
Module













"t"


Vt---


Arithmetic
Module








~!-


Priority
Module


1- 1


Figure 16. The modular substructure of a processing cell.


B- CH


--BO




















-BI


__ _~1_









The contents of the cyclic access memory associated with

the cell enter over the input MR, and the processed contents

to be rewritten exit over MW. BI is the input bus from the

channel over which messages are received, and BO is the bus

to the channel for messages generated by the cell. The

arithmetic module performs arithmetic operations and numeri-

cal comparisons on the fields of the records and messages,

and the control module performs combinational tests on the

binary variables, governs the arithmetic module, and assembles

output messages. The priority module controls the issue of

messages from the cell, and resolves bus contention among

cells of the group sharing the bus. The priority module

receives two external inputs: one, CH, from the channel to

signal that the channel cannot accept any further messages,

and the second, RI, a priority rail passing through the cells

of the group. The priority rail permits resolution of bus

contentions through a rotating priority scheme. The inputs

to the cell for timing and clock signals are not shown.

With respect to the arithmetic module, there are two

long sequences of operations which might occur in Procedure 3.

They are stated as Sequences 1 and 2 below.


Sequence 1: WW + WL W + WL if WW=1
WR + W WZ W=O

Sequence 2: DD + D-Q
DD + IDD
DD + K-DD if DD>k'2
Y + L+W+D
OV + Y>MX









Sequence 1 occurs in NODE of Procedure 3, and Sequence 2 in

ARC of Procedure 3. The arithmetic module must be capable

of executing either of these sequences in a word time.

Assuming that the cycle time of the memory and the number

of bits around it are fixed by practical considerations,

then there is a reciprocal relationship between the word

time and the width of the memory in bits. While a wide

memory can contain more words of the model, with a resulting

smaller number of cells, the word time is very short, and

high speed logic circuits are required. Because the unit

cost of logic generally decreases with increasing quantity,

and sharply increases with increasing speed, a minimal width

memory (one bit wide) would appear to afford an optimal solu-

tion. An additional and important advantage of a one bit

wide memory is that fewer input and output connections to

each cell are required, further reducing the unit cost.

With the words entering the cell as strings of serial

bits, serial arithmetic can be used if the sequences of

operations can be favorably scheduled. This also permits

the use of various length shift registers for storage.

Because the logic circuits for serial arithmetic operations

are simple and fairly inexpensive, it becomes practical for

many operations to be overlapped where precedence in the

procedure permits. In this manner, the last three statements

of Sequence 1 can be performed simultaneously, such that the

entire sequence can be performed in less than one word time,

e.g., 32 bit times of the 46 bit word time for the estimates








of Table 2. Thus, the speed of the logic can be commensurate

with the shift rate of the cyclic access memory.

Although compatibility in logic speeds and memory shift

rates has minor significance with head-per-track memories,

it may be quite significant if the integration of large

memories and logic circuits becomes economically competitive.

Such might become possible with the evolving technologies of

magnetic bubbles [MINNR 72] and charge coupled devices. For

this reason, a serial-by-bit, parallel-by-operation architec-

ture is recommended for the processing cell.

To help illustrate this approach, an implementation of

Sequence 2 is considered. Although the operations of the

first three statements appear formidable, they may be real-

ized in essentially two additions, one of which can occur

simultaneously with the execution of the fourth statement

(and fifth statement). Consider that the orientations D

and Q are represented by the integers from 0 through K-1,

where K corresponds with 3600, and is some power of two (2*9

here). Then, the addition of D to the K's complement (two's

complement) of Q can be stated

DD K\(D+Kl(-Q))

The most significant bit of the sum is

SDD +((2eK)p2)TDD

If SDD is zero, then the value of DD is the desired turning

penalty, but otherwise, the turning penalty can be found by

taking the K's complement of DD, e.g., DD -- *K(-DD). Thus,

the turning penalty is formed by a K's complement addition









followed by a possible complementation of the result. This

latter complementation can be formed as the turning penalty

is added to W. If it is assumed that the logic is moderately

fast, then the sum of the turning penalty W, and L can be

formed simultaneously. Note that the overflow indicator,

OV, is merely the carry out for the most significant bit of

this sum. Since the time to add D and the complement of Q

is 9 bit times, and the remaining operations are performed

in the length of W, of 16 bit times, the total bit times for

the execution of Sequence 2 is merely 25, considerably

shorter than a word time. A module for executing Sequence 2

based on the field lengths for F, X, D, L, I, and H of 1, 1,

9, 16, 1, and 18, respectively, is described in Table 5 and

illustrated in Figure 17. The variable T is used to indicate

the bit time with respect to the beginning of the arc record.

A simulation of the module in the APL programming language is

given in Appendix B.

Although this example for Sequence 2 realizes only a

small part of the total number of operations to be performed

by the cell, it does comprise the most complex sequence of

arithmetic operations, and is sufficient to indicate the

benefits of the proposed approach to the cell architecture.

First, there are relatively few connections with the module,

which can be of some importance in an integrated circuit

realization. Second, the relatively small amount of memory

required (13 bits here) can be realized by clocked shift

registers. In fact, no storage in the entire cell is









XE23
X[23






















X 3]


ZC13


Figure 17. A submodule for Sequence 2.


EN[2]








ENE 3]
EN[3]



















EN[4]


z[23


M.-






77


Table 5

Example Module Description


INPUTS:

X[13 is D if Te(2+19)
X[2] is L if Te(11+116)
X[3] is Q if TE(2+19)
X[4] is W if TE(11+116)

ENABLE INPUTS:

EN[11] T=2
EN[23 + T=11
EN[3] Te(l11+19)
EN[4] 1 (Te(11+1i6))A(WZ=1)

OUTPUTS:

Z[1] is Y if TE(11+116)
Z[21 is OV if T=27

FULL ADDER TERMINALS:

A,B are addends
CI is carry input
CO is carry output
S is sum output

Note: Only the memory input transfers are clocked. All
the transfers below are executed simultaneously.

FULL ADDER INPUTS:

FAA11] X[1]
FABE[] X[C2]
FACI[1] 1 MI
FAA[2] + X[3]
FAB[21] EN[3]A(M2eM3[9])
FACI[2] M4
FAA[3] X[11
FAB[3] FAS[2]
FACI[33 M5

MEMORY INPUTS:

M1 I FACO[1]vEN[1]
M2 (FAS[1]AEN[2])v(M2A-EN[2])
M3 + FAS[]3,M3[1~8]
M4 + (FAS[1CAEN[2])v(FACO[2]A^EN[2])
M5 + FACO[3]A-EN[2]





78


Table 5 (continued)


FULL ADDER OUTPUTS:

FAS + FAA#FABeFACI
FACO + 1<(FAA+FAB+FACI)

MODULE OUTPUTS:

Z[1] + (X[1]AEN[4])v(FAS[3]A-^N[4])
Z[2] + FACO[2]vFACO[3]






79


required to retain its information statically for more than

the duration of one fork record, and dynamic shift registers

can be employed. Although the multiplicity of operator

modules (such as the full adders) appears a disadvantage, it

does permit the use of a relatively low speed technology,

and simplifies control of the module. With the entire cell

designed after the style of Figure 17, the control signals

can be generated by a small read-only memory driven by a

counter whose modulus is the word length.

Before closing this discussion on the architecture of

the processing cells, a few comments on the mechanics of

receiving and transmitting messages are appropriate. The

total number of bits in a message exceeds the number for a

word of memory, and in order to avoid two data rates in the

cell, the input and output buses are each realized by a pair

of lines. One line carries the data, while the other, the

code and address of the message. As a message is broadcast

over a bus, BI, by a channel, each cell compares its number

against the cell number part of the destination address.

Only the cell whose number matches,interprets the message

as other than a null message.

The code and address parts of a message do not occupy

the entire word time on their lines of the buses. This

unused space on the input bus is employed by the channel to

inform each cell of its group of the major state of the

processor and the value of the control parameter R. On the

output bus, the unused time is employed by the cells to









transmit error signals and exception codes, such as overflow.

Concurrent signals are "OR-ed" into bus BO.

Having considered the general architectural features of

the processing cells, the nature of the access structure is

addressed next.


The Access Structure


Each group of processing cells with its channel and

commutator segment is an independent unit of the processor,

and is a useful basis for describing the access structure of

the search system processor. Such an aggregation of elements

is shown in Figure 18. The dominant element of the structure

is the channel and, therefore, its description and functions

are presented first.

The internal structure of a channel is illustrated in

Figure 19 as a set of modules. A channel contains one input

module, one output module, and a number of storage modules.

Each storage module comprises a shift register memory for one

message and a number of logic elements which implement asso-

ciative searches on fields of a stored message. The input

module accepts one message from the bus BO, and based on the

code and the unit part, AD[3], of the destination address of

the message, either stores the message or passes it to the

commutator segment associated with the channel. The input

module also extracts comparands from incoming messages for

some of the associative searches on the stored messages,






Cyclic Memory


co






'I-
)0





Commutator
Segment


Figure 18. A unit of the search processor.


























































C'0


Figure 19. The structure of a channel.









generates another comparand, and performs a few additional

functions as described shortly. The output module is pri-

marily used to reorganize messages such that the cell part,

AD[2], of the destination address precedes the remainder of

the message on the bus BI. In addition, the output module

injects the major state and control parameter information

broadcast from the global controller into an egressing

message line.

The functioning of the channel modules is perhaps most

easily described by following the activities attendant with

the entrance of a message on the bus BO. As the message

passes through shift registers of the input module, a number

of fields are examined. The code and destination address of

the entering message are checked, and if the message is a

station message (OP=2),or a trace (OP=3) or search (OP=1)

message whose address is not among the cells served by the

channel, the message is diverted to the commutator segment.

If the message is a trace message and the destination is in

the cell group, a copy of the message is made (with OP=4)

and the original is stored in the channel while the copy is

sent to the commutator for routing to the dispatch system.

As the code and destination address are scanned to

ascertain the disposition of a message, these values are

also employed as comparands for an associative search on the

respective fields of the messages in the storage modules.

By virtue of the procedures which generate the various mes-

sages, only search messages (0P=1) will satisfy this search,









and as will become clear, at most one match will occur.

While the matching messages have the same destination node,

they will differ in the tentative distance, Y, the tentative

predecessor node, P, or both. If the tentative distances

are equal, then only one message needs to be delivered since

only one shortest route for any vehicle is sought, and it is

immaterial which message is discarded. Here, the incoming

message is discarded while the stored message is preserved.

When the distances of the messages differ, however, the one

having the lesser value must be delivered, and the one with

the greater distance may be discarded since it represents a

poorer route. The message with the lesser distance is found

by performing an associative search with the distance of the

incoming message as comparand, and testing in each module

for the distance of the stored message being greater. This

operation will overlap the test on the code and address, so

both searches are performed independently. After both

searches are performed, a storage module satisfying both has

a message which can be replaced by the incoming message. If

a common match does not occur, but the code and address match,

then the incoming message is discarded. When a search or

trace message is to be stored, other than in replacement,

then the bottom-most storage module is selected by a simple

priority system.

The delivery of a message also involves an associative

search. There is a delay of two word times in placing a

message in a storage module onto the bus BI to the cells.









One word time is consumed in passing through the output

module, while the second is required in determining which

message is to be delivered. This latter operation is per-

formed by an associative search on the word number portion

of the destination address in every stored message against

the current word number (plus two) as comparand. It is

possible that more than one message will require delivery

during any particular word time because of the multiplicity

of cells served by the channel. In such an event, one

message is selected by a rotating priority system, and the

others will be delivered in later cycles.

In each word time, the channel obtains a count of the

number of messages contained in its storage modules. In the

input module, this count is compared against the count trans-

mitted on a control rail by the previous channel along the

commutator. The input module then transmits the greater of

these two counts to the next channel, such that the value

reaching the global controller on the rail is the number of

messages in the most densely filled channel. The global

controller employs this count in determining the value of

the control parameter, R, to be broadcast to the channels

for the next word time.

When any channel becomes filled to capacity, it inhibits

the generation of all messages by its associated cells, and

refuses acceptance of any messages from its commutator seg-

ment. In addition to providing message counts for control

purposes, the channels also monitor their input buses, BO,









for error and exception alarms, and retransmit them to the

global controller as they occur.

The remaining element of the access structure is the

commutator segment. This is essentially a single word time

delay line for messages, plus shift registers for storing

one message, and some logic. As a message passes through

the commutator segment, the unit part of its destination

address is checked to determine if the message is destined

to that unit. If such is the case, the message is diverted

from the commutator to the bus BO of the channel group. When

such a message is diverted, a null message is passed to the

next commutator segment. As illustrated in Figure 19, the

commutator shares the priority rail of the cells; however,

the segment always has highest priority whereas among the

cells, it is rotated. This assures that the commutator will

not be unnecessarily filled, as its capacity is relatively

small.

The commutator segment includes one shift register for

a message from the channel, and one for the message passing

from the previous segment. If the message entering from the

previous segment is not a null message, or if it is not

diverted to the channel, then a message entering from the

channel cannot be placed in the message stream of the com-

mutator. When this occurs, the message from the channel is

held in the segment until a vacancy in the stream occurs, at

which time it is entered into the stream. While a message

is being retained in the commutator segment, it is necessary





87


to defer the generation of all messages in that unit in

order that none are lost. This is realized through the

channel busy signal (CH=1).

This completes the description of the essential elements

of the architecture proposed for the search system processor.

In the next section, this architecture is evaluated with

respect to both the needs of emergency call processing, and

alternative approaches to the search system implementation.














EVALUATION OF THE PROPOSED ARCHITECTURE


The fundamental criterion for evaluation of the pro-

posed architecture for the search system is its suitability

to emergency call processing. This criterion can be factored

into four constituents: the ability to execute the searches,

the speed with which the searches are performed, dependability

of the system, and cost. From the preceding section, it

should be clear that the proposed processor can execute the

search algorithm, as it is specifically designed to do so.


Speed and Cost


As is generally the case in processor design, the speed

and cost of the proposed search system processor are antagon-

istically related. The first step towards speed and cost

estimates is the exposure of their interdependencies. A

fundamental speed-cost trade-off arises in the inverse rela-

tionship between the cycle time and the number of processing

cells.

In a particular city, the total quantity of cyclic

storage (in bits or words) is fixed by the street system, and

therefore, the number of words per memory is inversely re-

lated to the number of memories. Then, under the relatively









safe assumption that the data rate of the cyclic memory

storage medium is a primary constraint, the cycle time and

the number of words per memory are directly related. For

example, a head-per-track disc system having a data rate

limit of three million bits per second on each track, and

a synchronous drive motor, will yield a cycle time of 16.7

milliseconds, and each track will easily hold 1,024 words.

This system will then require 128 cells for a city of about

1.25 million persons based on the estimates of Table 2.

A second speed-cost trade-off occurs between the search

time and the capacity of the access structure for messages.

The search time (in memory cycles) is basically limited by

the topology of the street system model and the cyclic nature

of accession in its stored representation. This time is then

increased through deferment in the generation of search

messages. This effect can be seen to some extent even in

the simple example for Table 1, where the unconstrained

Moore criterion yields the basic search time. In order to

demonstrate the relationships between search time and access

structure capacity more accurately, simulations of a simple

processor have been performed with respect to the partial

street system of Figure 14.

The simulation programs were written in FORTRAN, and

treated the entire model as though stored in a single cyclic

access memory. The primary goal of the simulation was to

determine the relationship between the total number of




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