• TABLE OF CONTENTS
HIDE
 Title Page
 Dedication
 Acknowledgement
 Table of Contents
 List of Tables
 List of Figures
 List of Symbols
 Abstract
 Introduction
 The multiplication process and...
 Experimental procedure
 Experimental results
 Conlcusions and discussion
 Bibliography
 Biographical sketch
 Copyright














Group Title: investigation of some properties of carriers in field-effect devices
Title: An investigation of some properties of carriers in field-effect devices
CITATION THUMBNAILS PAGE IMAGE ZOOMABLE
Full Citation
STANDARD VIEW MARC VIEW
Permanent Link: http://ufdc.ufl.edu/UF00082467/00001
 Material Information
Title: An investigation of some properties of carriers in field-effect devices
Physical Description: xii, 73 leaves : ill. ; 28 cm.
Language: English
Creator: Rucker, Lucien Maurice, 1941-
Publication Date: 1977
 Subjects
Subject: Field-effect transistors   ( lcsh )
Electrical Engineering thesis Ph. D
Dissertations, Academic -- Electrical Engineering -- UF
Genre: bibliography   ( marcgt )
non-fiction   ( marcgt )
 Notes
Thesis: Thesis--University of Florida.
Bibliography: Bibliography: leaves 70-72.
Statement of Responsibility: by Lucien Maurice Rucker, III.
General Note: Typescript.
General Note: Vita.
 Record Information
Bibliographic ID: UF00082467
Volume ID: VID00001
Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
Resource Identifier: aleph - 000205830
oclc - 04022242
notis - AAX2619

Table of Contents
    Title Page
        Page i
    Dedication
        Page ii
    Acknowledgement
        Page iii
    Table of Contents
        Page iv
        Page v
    List of Tables
        Page vi
    List of Figures
        Page vii
        Page viii
    List of Symbols
        Page ix
        Page x
    Abstract
        Page xi
        Page xii
    Introduction
        Page 1
        Page 2
        Page 3
        Page 4
        Page 5
        Page 6
        Page 7
    The multiplication process and related behavior
        Page 8
        Page 9
        Page 10
        Page 11
        Page 12
        Page 13
        Page 14
        Page 15
        Page 16
        Page 17
    Experimental procedure
        Page 18
        Page 19
        Page 20
        Page 21
        Page 22
        Page 23
        Page 24
        Page 25
        Page 26
        Page 27
        Page 28
        Page 29
        Page 30
        Page 31
        Page 32
        Page 33
        Page 34
        Page 35
        Page 36
        Page 37
        Page 38
        Page 39
        Page 40
        Page 41
        Page 42
        Page 43
        Page 44
        Page 45
    Experimental results
        Page 46
        Page 47
        Page 48
        Page 49
        Page 50
        Page 51
        Page 52
        Page 53
        Page 54
        Page 55
        Page 56
        Page 57
        Page 58
        Page 59
        Page 60
        Page 61
        Page 62
        Page 63
        Page 64
        Page 65
    Conlcusions and discussion
        Page 66
        Page 67
        Page 68
        Page 69
    Bibliography
        Page 70
        Page 71
        Page 72
    Biographical sketch
        Page 73
        Page 74
        Page 75
    Copyright
        Copyright
Full Text













AN INVESTIGATION OF SOME PROPERTIES OF CARRIERS
IN FIELD-EFFECT DEVICES











By

LUCIEN MAURICE RUCKER, III


A DISSERTATION PRESENTED TO THE GRADUATE COUNCIL OF
THE UNIVERSITY OF FLORIDA
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE
DEGREE OF DOCTOR OF PHILOSOPHY





UNIVERSITY OF FLORIDA


1977



































To my wife, Barbara, who has helped me through three degrees,

and my son, Michael, who thinks Daddy's laboratory is a neat

place (Daddy agrees)

















ACKNOWLEDGMENTS


I would like to thank Dr. Eugene R. Chenette for the

opportunity and encouragement to pursue this research and

Dr. Alan D. Sutherland for his many helpful suggestions

during the experimental phase of my work. I also acknowl-

edge a special indebtedness to Dr. Aldert van der Ziel for

his most generous guidance and instruction. I thank Dr.

Jack R. Smith for review of this work and Dr. Zoran Pop-

Stojanovic for interesting discussions of Stochastic Equa-

tions over the last year.

The assistance of Mr. Walter Powers has proved in-

valuable on many occasions as has the support of many of

the faculty and staff through all of my graduate work. I

would especially like to note the work of undergraduate

assistants Dean McCormick and Kathy Harrer.

I want to express a special gratitude to my wife and

son. Without their help and understanding I could not have

returned to or continued in school.

This research was supported by National Science Founda-

tion grant ENG 75-17003.


iii














TABLE OF CONTENTS

Page

ACKNOWLEDGEMENTS . . ... . iii

LIST OF TABLES . . . . . vi

LIST OF FIGURES . . . . ... vii

LIST OF SYMBOLS . . . . ix

ABSTRACT . . . . . xi

CHAPTER

I INTRODUCTION . . . . 1

A. Purpose and Objectives . .. 1
B. Related Research . . . 4

II THE MULTIPLICATION PROCESS AND RELATED
BEHAVIOR . . .. . 8

A. The Multiplication Process in JFETs 8
1. Multiplication Factor and Current
Relations . . . 8
2. Input Conductance .. . 9
3. Multiplication as a Random Process 10
B. The Multiplication Process in MOSFETs .16

III EXPERIMENTAL PROCEDURE . . .. .18

A. DC Measurements . . ... 18
1. Drain-to-Gate Current Ratio ..... 18
2. Negative Gate Conductance of a JFET 26
B. Noise Measurement . .. 30
1. Equipment . . . 30
2. Measurement of Noise Associated with
JFET Gate Current . ... 38
3. Noise at the Substrate of a MOSFET .41
4. Noise at a FET Drain . ... .41
C. Stability of the DUT . . 44
D. Other Considerations . . 44













Chapter


Page


IV EXPERIMENTAL RESULTS . . ... 46

A. Region of Operation to Produce Channel
Avalanching . . . 46
B. Drain-to-Gate Current Ratio . .. 49
C. Gate Conductance of a JFET .. . .. 56
D. Conductance at a MOSFET Substrate . 58
E. Noise Associated with Channel Avalanche
Induced Gate Current in JFETs . .. .61
F. Source Current Enhancement . .. .61

V CONCLUSIONS AND DISCUSSION . .. . 66

BIBLIOGRAPHY . . . . .. .. 70

BIOGRAPHICAL SKETCH . . . ... 73


















LIST OF TABLES

Number Page

4.1 TEMPERATURE RISE CALCULATIONS AT LOW
DUTY CYCLE . . . . 48

4.2 LIST OF VALUES OF THE EXPONENT m IN
EQUATION 4.1 . . . 56

4.3 DATA USED TO VERIFY THE CALCULATION OF
GATE CONDUCTANCE OF JFETs EXHIBITING
CHANNEL AVALANCHING . .. 57

4.4 DATA USED TO VERIFY THE CALCULATION OF
SUBSTRATE CONDUCTANCE FOR MOSFETs AT
ROOM TEMPERATURE . . .. 59

















LIST OF FIGURES


Figure No.

2.1


3.1

3.2

3.3

3.4


3.5



3.6


3.7

3.8

3.9


3.10


3.11


3.12


4.2


Essential Details of a Simple Model of
JFET Geometry . . . .

High Voltage Power Supply . .

Tracking +15 Volt Supply . . .

Low Voltage Bipolar Supply . .

Block Diagram for Drain-to-Gate Current
Ratio Measurement at Low Duty Cycle

Oscillator used to Measure the Multipli-
cation Factor, M, at the Threshold of
Oscillation . . . .

A Simple Amplifier used to Measure Trans-
conductance, gm, of the DUT . .

Noise Measurement System Block Diagram

Circuit for a Low Noise Amplifier (LNA).

Amplifier Noise Voltage Referred to the
Amplifier Input . . .

Circuit of a Noise Standard using a
Vacuum Diode . . . .

Equipment for Measuring Noise Associated
with the Gate Current of the DUT .

Circuit used to Measure Noise at the
Drain of the DUT . . .

JFET Gate Current as a Function of
Temperature with VDS as a Parameter and
one percent Duty Cycle . . .

JFET Transconductance and Saturated Drain
Current with VG = 0 as Functions of
Temperature . . . .

vii


Page













List of Figures (Continued)


Figure No.

4.3 Device G Gate-to-Drain Current Relation .

4.4 Device AD Gate-to-Drain Current Relation .

4.5 Device AE Gate-to-Drain Current Relation .

4.6 Device C Gate-to-Drain Current Relation .

4.7 Device R Gate Noise as a Function of Gate
Current . . . . .

4.8 Device S Gate Noise as a Function of Gate
Current . . . . .

4.9 Device FH7 Gate Noise as a Function of Gate
Current . . . . .


viii


Page

51

52

53

54


62


63


64














LIST OF SYMBOLS


A Attenuation

a ionization rate


e2L RMS noise voltage of the low noise amplifier
LNA referred to the amplifier input

2
e 2 RMS noise voltage of the noise standard
NS
gin Input or gate conductance of a JFET

gp A conductance placed in parallel with a tank
circuit

gp p gt

gSUB Conductance of a MOSFET substrate terminal

gt The parallel equivalent conductance of a tank
circuit

IA DC anode current of the noise standard

ID DC drain current of a FET

I Noise at a FET drain in terms of equivalent
D eq saturated diode current

I Equivalent saturated diode current
eq
IG DC gate current of a FET

I Noise at a FET gate in terms of equivalent
G eq saturated diode current

I. Noise of the low noise amplifier referred to the
in amplifier input and expressed in terms of equiva-
lent saturated diode anode current

IS DC source current of a FET

I Noise at a FET source in terms of equivalent
S eq saturated diode current

ix













ISUB DC value of MOSFET substrate current

M Multiplication factor, the ratio of drain to
source current

M The mean or expected value of M

rd Incremental drain resistance of a FET

R 1/g

Sx(f) Spectral intensity of the quantity x

t time

VDG FET drain-to-gate potential

VDS FET drain-to-source potential

VGS FET gate-to-source potential











Abstract of Dissertation Presented to the Graduate Council
of the University of Florida in Partial Fulfillment of the Requirements
for the Degree of Doctor of Philosophy


AN INVESTIGATION OF SOME PROPERTIES OF CARRIERS
IN FIELD-EFFECT DEVICES

by

Lucien Maurice Rucker, III

December 1977

Chairman: Aldert van der Ziel
Co-Chairman: Alan D. Sutherland
Major Department: Electrical Engineering

The purpose of this work is to study the behavior of

several phenomena related to avalanching in the channel of

Field-Effect Transistors (FETs). For sufficiently high

drain-to-source potential in short channel FETs the majority

carriers can gain enough energy to cause ionization upon

impact with atoms in the crystal lattice. Such ionization

results in generation of a carrier pair with the majority

carrier continuing in the channel to enhance the drain

current and the minority carrier being collected rapidly by

the nearby depletion region to become part or all of the

gate or substrate current.

The results contained in this work show that the entire

gate current of Junction FETs (JFETs) is generated by the

channel avalanching process when the device is operated at

reduced temperature. This simplifies the remainder of the

study since it is not necessary to account for other gate

current-generating mechanisms.

xi











The relation for noise associated with the JFET gate

current generated by channel avalanching is adapted from

earlier work on MOSFETs and is verified. For low channel

avalanche levels found in JFETs the equivalent saturated

diode current is found to be equal to the JFET gate current.

The possibility of instabilities resulting from nega-

tive gate or substrate conductance and the noise associated

with the multiplication process are limitations on FET

performance of interest to both device and circuit designers.


xii

















CHAPTER I

INTRODUCTION

A. Purpose and Objectives

There are at least two reasons for studying noise

associated with electric circuits. The first, and most

familiar, is to be able to minimize the noise in a circuit.

The second is to study the noise characteristics of a

device in order to discover the mechanism that produces

the noise. This leads to a more complete understanding of

the physics which, hopefully, will lead to better devices

and circuit models. It is the second reason with which

this research is primarily concerned.

Field effect devices were discussed as early as the

1920's [1] with the first papers written on Field-Effect

Transistors (FETs) in the 1950's [2,3]. With only small

changes these works define FET behavior with reasonable

accuracy.

However, as FET fabrication and use became widespread

in the 1960's, effects were found for which earlier anal-

yses were incomplete. Important among such effects was the

generation of gate or substrate currents in Junction FETs

(JFETs) and Metal Oxide Semiconductor FETs (MOSFETs),

respectively, by avalanching in the channel. This can occur

when the electric field in the channel becomes high.

1











Majority carriers develop enough energy between collisions

with the lattice to ionize atoms upon impact. This process

generates carrier pairs. The new majority carrier continues

down the channel possibly contributing to additional ioniza-

tion and enhances the drain current. The minority carrier is

captured by the nearby depletion region before it can contrib-

ute to additional avalanching and becomes part of the gate

or substrate current. This mechanism is variously referred

to as avalanching, impact ionization and multiplication.

Some authors make a distinction between these terms but such

distinctions are not clearly defined and will not be made

here. The only exception will be the occasional use of the

terms channel avalanching or channel multiplication to sepa-

rate this mechanism from gate or substrate breakdown.

The channel multiplication process is different in one

important respect from the multiplication process found

earlier in avalanche diodes. The difference is that only

majority carriers take part in the channel process since

minority carriers are removed from the channel by the nearby

depletion region. Because of this property, studies can

be made of each type of carrier and its multiplication pro-

cess. This is still not possible in diodes where the carrier

types and their effects cannot be separated.

Since the 1960's the trend has been to design smaller

FETs with shorter channels resulting in higher transconduc-

tance and drain resistance. Because the channel is shorter,

the electric field in the channel is higher and avalanching














occurs more readily. In older devices gate or substrate

currents were largely the result of thermal generation of

carriers in the depletion region. In the newer shorter

channel devices, the gate or substrate current generated by

avalanching in the channel can easily become dominant.

This additional source of current leads to two poten-

tial difficulties, or at least conditions of which device

and circuit designers should be aware. First, the current

is in such a direction that a negative input conductance at

the gate or substrate results which can cause stability

problems. Second, the additional current has associated

with it a random component which can contribute significant

noise in many applications. Since JFETs are frequently

used in low noise applications and since the channel

avalanche generated gate current can be several orders of

magnitude higher than the usual thermal gate currents, the

avalanche-related noise can seriously degrade device noise

performance.

It is the purpose of this work to study some channel

avalanche-related effects in FETs. The JFET will be the

preferred device since it is widely used in low noise appli-

cations and because it is more susceptible in typical appli-

cations to stability difficulties. (The MOSFET substrate

is usually tied to the device source which prevents stability

problems related to the substrate current.) Objectives that

have been met are:

1. It is necessary to determine whether the JFET gate











current at low temperature and high VDS is entirely the

result of channel avalanche. If other mechanisms are

involved they must be taken into account.

2. The JFET gate conductance is measured in devices

showing channel avalanching and compared to theory.

3. The noise associated with channel avalanche-

generated gate current is measured and compared to theory.

4. The MOSFET substrate conductance is measured at

room temperature.

It is the intent in each of the above objectives to

develop practical theoretical relationships, to verify the

relationships with experiment and to demonstrate the

importance of the avalanche-related phenomenon.

The theory associated with channel avalanching and

related phenomena is developed in Chapter II. Chapter III

outlines the experimental method by which the theory is to

be verified and Chapter IV gives the results with some

discussion. A concise statement of conclusions and sugges-

tions for further work is contained in Chapter V.

B. Related Research

In May 1968 Fowler [4] reported finding an enhancement

of IG in n-channel JFETs with increasing VDS. The effect

was not found in p-channel devices or in "older transistor

types." The measurements were made at room temperature.

Fowler mentions earlier work by B. Newsam, but no publica-

tion of such work has been found. It was suggested,at the

time that the mechanism involved was emission of holes from











the drain contact. It was proposed that the holes were then

collected by the gate depletion region.

In 1968 Nakahara, Iwasawa and Yasutake [5], using

MOSFETs, found enhancement of ISUB in n- but not in p-channel

devices. These measurements were also performed at room

temperature where the ionization rate of holes is small in

silicon. In 1969 the same authors [6,7] found an exponen-

tial relation between IG and VDS in n-channel devices. A

major difference between this work and Fowler's is the pro-

posed mechanism. These authors suggested that the source

of minority carriers collected by the gate to form IG was

impact ionization in the channel, a theory now widely

accepted.

Also in 1969 Ryan [8], using JFETs cooled to 770K,

found p-channel behavior similar to that reported pre-

viously only for n-channel devices. The cooling "uncovered"

the p-channel behavior since avalanching increases with

decreasing temperature. The results for n-channel devices

were also enhanced at lower temperature. Later in 1969

Ryan [9] also published a letter containing similar find-

ings for the p-channel MOSFETs.

The first related noise measurements (i.e., involving

the multiplication process) were reported in December 1969

by Nakahara, Iwasawa and Yasutake [6]. The results still

indicated, as did their earlier work, that p-channel FETs

do not exhibit the multiplication mechanism. In 1970

Nakahara and Kobayeshi reported similar work including a

comment on variations in input conductance [10].












In 1970 Ambrozy [111 reported in more detail that both

p- and n-channel devices showed enhanced IG. He worked

with JFETs at varying temperatures. Arguments were offered

favoring avalanching as the mechanism producing IG and

added a new twist not previously suggested, that minority

carriers generated near the source end of the pinched-off

region of the channel might be collected by the source as

well as the gate. Thus, at high VDS an enhancement of IS

might be found.

In 1971 Klaassen [12] published noise measurements on

n-channel JFETs and both types of MOSFETs. The noise from

n-channel JFETs and MOSFETs were found to be comparable in

regions of operation where avalanching was considerable.

The JFET was much quieter in other regions (measurements

were at 1 KHz and 1/f noise was high in the MOSFET.) The

p-channel MOSFET was quieter at high VDS than either of the

n-channel devices as might be expected.

Also in 1971 Kim [13] wrote his Ph.D. Dissertation

which contained a much more detailed collection of data and

theory for the MOSFET. The impact ionization mechanism was

verified. Kim also verified earlier results for terminal

currents and related noise for both n- and p-channel MOSFETs.

One area left incomplete was the matter of source current

enhancement in which secondary minority carriers from

avalanching return to the source instead of the gate. This

was apparently observed in one device, doping unknown, but

was not pursued. Kim did not make JFET measurements.


__1













In all the reported work it was only slightly suggested

that the IG to ID ratio is important. For IG generated

entirely by channel avalanching, the ratio must be constant.

A changing ratio is evidence of another mechanism generating

gate current. Earlier work reported the ratio to be "con-

stant over most of the region" or to be "almost constant."

Since 1971 work on channel avalanching has included

modeling of MOSFET substrate currents [14], consideration of

substrate current as a process monitor in manufacturing [15]

and modeling of channel avalanching with computer-aided

design (CAD) in mind [16, 17]. There has been no mention

of stability difficulties, noise at gate or substrate or of

any examination of the invariance of the IG to ID ratio.

The latter has been assumed by some authors though it has

not been adequately demonstrated. Virtually all work since

1971 has been on MOSFETs.

















CHAPTER II

THE MULTIPLICATION PROCESS AND RELATED BEHAVIOR

A. The Multiplication Process in JFETs

1. Multiplication Factor and Current Relations

In the common explanations of JFET operation, the

source current equals the drain current except for a very

small difference attributed to the thermally generated gate

current. For purposes of this discussion, the thermal gate

current will be considered negligible and will be made

negligible in experiments by operation at low temperature.

There is another mechanism which generates gate cur-

rent, that of avalanching in the channel. When the E field

in the channel becomes large enough, majority carriers will

gain sufficient energy to ionize atoms of the crystal

lattice upon impact. Each ionization generates a carrier

pair. The newly generated majority carrier continues down

the channel, possibly contributing to further avalanching,

and enhances the drain current. The minority carrier is

collected by the gate depletion region before it can con-

tribute to the avalanching process.

A multiplication factor, M, is defined as the ratio

of DC drain current to DC source current.
iD
M =--- (2-1)
S

8











For M = 1 there is no avalanching in the channel and there

is no gate current. The negative sign occurs because the

convention of all currents into the device will be used and

M 1. The expected or mean value of M will be represented

by M. The gate current is:


G = -(ID + IS) (2-2a)

= -(I- -) (2-2b)
M


= I(-1) (2-2c)
D M

For constant M, IG must be proportional to ID. Significant

deviation would indicate the presence of another mechanism

generating gate current.

2. Input Conductance

Reducing Equation 2-2c to incremental currents:


i =-i d( 1) (2-3)
M

The transconductance of a FET is:

di
g dv (2-4)
gs vd =

This will give:


i = gm Vgs (2-5)


From Equations 2-3 and 2-5:


= (M (2-6a)
ig -gmVgs ( (2-6a)











Using the conventional definition, the gate conductance is:

i
in= = -g ( ) (2-6b)
gs

Neglecting thermal gate currents, this places the input

characteristic of the FET entirely in the third quadrant.

This negative input conductance can cause bias instabilities

and oscillation. In Equation 2-6b gm is also a function of

the multiplication process. It is practical to measure

this gm and the related M. However it is occasionally

desirable to work with transconductance not including

multiplication. Extrapolation of gm from data at low VDS

or calculation from device geometries are two such cases.

In this case gmo, transconductance without multiplication,

will be determined. For ido and gmo the drain current and

transconductance without multiplication

dio d
Sdo d (_-i ) (2-7a)
mo dgs vd=0 dgs vd=0

And using Equation 2-4 with id = M is

g
Sg m (2-7b)
M

and from Equation 2-6b

gin = -gmo 1) (2-8)

3. Multiplication as a Random Process

The current at the drain of a FET normally shows small

fluctuations or noise caused by a variety of mechanisms











including Johnson noise, hot electron noise and generation-

recombination noise. The multiplication process is random

and should increase the fluctuation in drain current. The

gate current is generated by the multiplication process and

will show the same fluctuation as induced in drain current

by the multiplication process [18].

a. Multiplication noise at the drain

To find the noise associated with avalanche-generated

gate current, first consider that M may be defined as the

ratio of the flux of majority carriers at the drain to the

flux of majority carriers at the source.


M =- (2-9)
nS

This is in agreement with Equation 2-1 since


IS = q; D = qD (2-10)

Now using the Burgess Variance Theorem


var nD = M var S + nS var M (2-11)

Changing this to currents

=-2
var iD = M var iS + qiS var M (2-12)

And since


S. (0) = 2 var is; S. (0) = 2 var iD (2-13)
Si D (2-1

S. (0) = M2S. (0) + 2qTi var M (2-14)
D 'S











b. Determination of var M

It is necessary to find a practical method for finding

var M in the second term of Equation 2-14. First consider

Figure 2-1. The increase in current through channel seg-

ment dy is dl(y). It would be expected that dl(y) is pro-

portional to the number of carriers in the channel volume

bounded in part by dy. dl(y) is then proportional to I(y).

The current increase should also be proportional to the

length of time carriers are in the region bounded by dy.

For a relatively constant velocity over the short distance

dy, dl(y) must be proportional to dy. Since minority

carriers are quickly removed from the channel by the nearby

depletion region, they do not contribute to the multiplica-

tion process and may be neglected. The increase in current

may be expressed by the simple relation


dl(y) = a(y)I(y)dy (2-15)


The coefficient a(y) is the majority carrier ionization

rate or probability that an ionization will occur in a unit

length of channel. This depends on the material and on the

E field which varies with y. A detailed knowledge of a(y)

is not needed for determining var M.

The solution of Equation 2-14 is

dI( = a(y) dy (2-16a)




















DRAIN


ID=1(d)


~ L-Depletion Region
Gate Diffusion








y=O

1S II=(0)


SOURCE


Figure 2.1.


Essential Details of a Simple Model
of JFET Geometry.


GATE








14

y y
In I(u) = In I(y) In 1(0) = a(u) du (2-16b)
0 0

With I(0) = IS this reduces to
y
M(0,y) = IY = exp a (u) du (2-16c)
S f
0

where the ratio I(y)/IS is a multiplication factor from the

source to some arbitrary distance y along the channel.

Expressing M as M(a,b) where a is the beginning and b the

end of the length of channel along which M is evaluated,

Equation 2-16c gives M(0,y) and Equation 2-1 gives M(0,d),

where y = d at the drain. The solution of Equation 2-16

from y to the drain gives
d
M(y,d) = exp a/ (u) du (2-17)
y

Since the ionization process is a Bernoulli trial, the

noise produced is shot noise and that added in segment dy is

dS i(y)(0) = 2qdl(y) (2-18a)

= 2 qa(y)I(y)dy (2-18b)

= 2qa(y)ISM(0,y)dy (2-18c)

= 2qa(y)IS[exp f a(u) du]dy (2-18d)


The noise due to multiplication in the dy segment that

appears at the drain is obtained by multiplying Equation

2-18d by [M(y,d)]2












dS. (0) = 2qa(y)IS[exp f
D '0


= 2qa(y)IS [exp f


rd
a(u)du][exp f a
y

a(w)dw]2[exp -f
2 0


(v)dv] dy (2-19a)



a(u)du]dy (2-19b)


where the first integral is M(0,d) 2 or simple M2.

total multiplication at the drain is


The


-2 y
2qa(y)IS 2[exp -
0


a(u)du]dy


To evaluate this double integration let


fa(u) du = f(y)


df(y) = a(u) du


(2-20)


(2-21a)


(2-21b)


and Equation 2-20 becomes


2qISM2f


exp(-f(y))df(y)


d
= 2qS M2[-exp f(y)]
0

S 2 1
= 2qIM (- + 1)
M


= 2qIsM(M 1)


(2-22a)



(2-22b)



(2-22c)



(2-22d)


Equation 2-22d must be equal to the last term in Equation

2-14. It is then necessary that


var M = M(M 1)


Si (0) =
I D f0d


S. (0) =
D


(2-23)











c. A practical calculation of gate noise

With Equation 2-23 it is possible to calculate magni-

tudes of noise resulting from the multiplication process.

The spectral intensity of drain current may be written

using Equations 2-14 and 2-23.


S. (0) = M2S. (0) + 2qI M(M 1) (2-24)
D S

The noise associated with the gate current may now be

found. Note that gate and source currents are related by

the factor (M 1). The spectral intensities which are

proportional to the squares of the related currents are

related by (M 1)2 so


S. (0) = (M 1)2S. (0) + 2qI M(M 1) (2-25a)
G S

or in terms of equivalent saturated diode current


IG eq= (M 1)2S e + M IG (2-25b)
G eq S eq G

The first term is small so to a very close approximation

S. (0) = 2qI M(M 1) (2-26a)
1 0

or

IG eq G I IG (2-26b)

This is convenient since S. (0) may not be known precisely,

B. The Multiplication Process in MOSFETs

The multiplication process described in section A

applies also to MOSFETs. The essential difference is that











minority carriers are collected by the substrate instead of

the gate. Therefore the substrate current is related to

source and drain currents as described in section A.1. The

input conductance at the substrate is given by Equation

2-6b or 2-8 where gm and gmo are defined from substrate to

drain for fixed VGS. The noise at the substrate is

described by Equations 2-25a and 2-25b. Equations 2-26a

and 2-26b are still good approximations of gate noise for

lower values of M, but MOSFETs exhibit higher values of

M than JFETs and the first terms of Equations 2-25a and

2-25b may become significant.

















CHAPTER III

EXPERIMENTAL PROCEDURE

There are essentially two types of measurements taken

in this research. First, some DC characteristics of the

device and second, the measurement of noise related to

those characteristics. The set-up and equipment used in

DC measurements are also used to bias the device-under-test

(DUT) in noise experiments.

A. DC Measurements

1. Drain-to-Gate Current Ratio

a. Equipment

As pointed out in Chapter II it is necessary to confirm

that gate current is generated only by current multiplica-

tion in the channel. Normal measurements at DC are inade-

quate because of self-heating in the DUT. Pulsed measure-

ments are required. Since the multiplication factor, M,

is a function of drain-source voltage, VDS, the drain supply

must be stable when the drain current is pulsed. Potentials

of up to 80 volts are required which preclude the use of

commercially available regulators such as the pA723. In

addition it is necessary to measure the average drain cur-

rent which is being pulsed at a relatively low duty cycle.

Any meter placed directly in series with the drain changes

VDS unacceptably. Figure 3-1 shows the high voltage (HV)













+84 %k R3 10
C5 10= 4=C6 .1
I R1 10
+15 1 -T-- +15VF
reg. l C1 10 __ C2
I R2 10 -5V R13
-15 o-.--~0 -15VF 2.2K
reg. C3 10- IC4 3W
C8 .001
'1 -4-


Q8 2N3440 R22 1K


.001


SIGNAL R4 1K J
INPUT -'--- | 1 Q4 6
T^ l R10 22K R19 10K
1R11 S- R18 5.6K
R 11


LEVEL --J 12K
R6 R9R 5.6K
o A741
-- 1K -15VF


SWEEP o i R7 100
RESET J,7<-- -----1| Q1 All resistor values in ohms and
iVR1I 0C7 capacitor values in jf except
15.6L-7470 --as noted. Transistors are
-15VF
E R8 2N5550 (npn) 0 2N5400 (pnp)
150K except as noted.

Figure 3.1. High Voltage Power Supply.


R23 1K











supply used to make measurements on n-channel FETs. For

p-channel FETs a similar supply has been constructed. For

stable operation the voltage level control requires a

regulated -15 volt supply. Since the stability of the

entire circuit is improved with all supplies regulated

(except the HV source), a regulated +15 volt supply using

the Fairchild 7815 and a tracking negative supply using

discrete components are used as shown in Figure 3-2.

One additional characteristic is required of the HV

supply. It must operate with a low noise level at its

output since it is used in noise measurements. The circuit

of Figure 3-1 produces approximately 1 nanovolt//Hz through

most of its useful range, which is acceptable.

The voltage regulator shown in Figure 3-1 is a conven-

tional regulator with a few minor modifications. Devices

Q7 and Q8 are series pass transistors. Devices Q4, 5 and 6

are the sense amplifier with a reference voltage at the Q4

base and the regulated voltage at the Q6 base. The load

current is measured by integrating the voltage across R21.

The base current of Q6 causes an error in measuring load

current and therefore must be small and stable. For a DUT

having ID = 0.1 milliampere and a 1% duty cycle, the average

current through R21 is only 1 microampere. A 1 microampere

base current to Q6 would cause a 100% error. Using the

emitter follower, Q5, this base current is reduced to

approximately 0.5 microampere and is relatively independent

of load current and so could be accounted for in measure-

ments.













































Figure 3.2. Tracking +15 Volt Supply.


12V








12V


-15V











The differential sense amplifier has another advan-

tage. Any voltmeter placed directly on the output would be

another source of error in measurement of load current.

This is overcome by measuring the reference voltage at Q4

base which is within, at most, a few tens of millivolts of

the regulated output potential which is sufficiently

accurate. The difference in base voltages is relatively

constant.

The reference voltage at Q4 base is established by an

operational amplifier consisting of Ul and Q2. The non-

inverting input of Ul is used as a current summing point.

Three signals are summed: 1) a DC level, 2) an external

input used to pulse the supply and 3) a sweep used for

plotting.

Other components contribute to the stability of the

circuit and to protection against output shorts.

In addition to the HV supply, a low voltage bipolar

supply shown in Figure 3-3 is required. This circuit is

used to drive either the gate or source of the DUT. It has

an output current capability of greater than 30 ma and an

output current measuring capability similar to the HV

supply. For measurements of very low output currents, an

LM 308 which requires very little input bias current is

substituted for the pA741 shown for U2. This circuit is

operated from the same +15 volt regulated supplies provided

for the HV supply.














-15VF

15VF


PULSE INPUT



DC LEVEL
5K


C2,4 25 Pf
C3,5 .001 pf


Resistor values in
ohms except as noted.


Figure 3.3. Low Voltage Bipolar Supply.


OUTPUT











b. Measurement method

The complete set-up for making pulsed measurements of

the ID to IG ratio is shown in Figure 3-4. The meter in

the gate of the DUT is an electrometer having relatively

low impedance so VG4 is essentially zero. This is verified

by measuring the Q point of the DUT with the electrometer

in the circuit and again with it removed (shorted).

Sufficiently low resistance is indicated by negligible

shift in the Q point. The electrometer is capable of

measuring IG accurately to less than 1 picoampere.

The DUT is operated in a Stratham chamber, model SD30,

with shielded leads to supplies outside the chamber. Liquid

nitrogen is used as a coolant.

The measurement of ID/IG is made in two steps. The

first step is to insure that the device operates in a

region for which IG is generated by channel avalanching.

The second step is to measure accurately the ID/IG ratio

while in the channel avalanche region.

To insure that gate current is generated by avalanching,

IG is measured at various temperatures for fixed VDS. This

is repeated for different values of VDS as a parameter. All

measurements are made by pulsing VGS from a quiescent point

in cutoff to VGS = 0. A 5 percent or less duty cycle is

used to prevent device heating. Thermal gate current has

a positive temperature coefficient, and channel avalanche

gate current has a negative temperature coefficient clearly

identifying the desired region of operation.
























DC High
Voltage VDD
Supply

(See Fig. 3.1) -Va"IDD







DUT

G I f




Pulsed
Bipolar
Pulse Supply
Generator Va--* -VQlS
(See Fig. 3.3)




Figure 3.4. Block Diagram for Drain-to-Gate Current
Ratio Measurement at Low Duty Cycle.











The device is then cooled sufficiently to insure channel

avalanching and the reduction of thermal gate current to a

negligible value. IG and ID are measured at 100 percent

duty cycle and using a least squares curve fit the exponent,

m, of


IG = K IDm (3-1)

is calculated. The value of m is generally found to be

less than unity for the higher values of current and near

unity for lower values. The same measurements are then

made while pulsing VGS at 5 percent duty cycle or less.

The duty cycle is chosen by determining what part of the

100 percent duty cycle curve has m = 1. If self heating is

the cause of curvature in the 100 percent duty cycle curve

and if the only mechanism generating IG is channel ava-

lanching, then m = 1 over the entire curve for the lower

duty cycle data.

2. Negative Gate Conductance of a JFET

As described in Chapter II, when a JFET is operated in

a region where avalanching occurs in the channel


gin = -g m( 1 mhos (3-2)


The circuit of Figure 3-5 will oscillate if Igin > gpl.

The conductance g' consists of the intrinsic parallel con-
p
ductance of the tank circuit, gt, and a discrete conduc-

tance, g in parallel. The discrete conductance is added

simply to vary g' for reasons that will be apparent.



























To Oscilloscope


Figure 3.5.


Oscillator used to Measure the Multiplication Factor,
M, at the Threshold of Oscillation.


.1 Pf














The DUT is placed directly in a small dewar flask con-

taining liquid nitrogen. This decreases the thermal com-

ponent of IG to near zero and increases the ionization

probability so that for increased VDD significant avalanching

occurs in the channel.

With g removed, VDD is increased while observing the

gate potential with an oscilloscope. At the threshold of

oscillation a sinewave of a few millivolts is observed and

the DUT gate is switched to the electrometer to measure IG.

ID is measured in the HV supply. The value of M is deter-

mined by

ID
M (3-3)
I I
D G

A low value of g is placed in the circuit and the proce-

dure is repeated. Higher values of gp are used until

oscillation fails to occur before gate junction breakdown.

The transconductance is measured for each of the

operating points found above using the circuit of Figure

3-6. This circuit simply determines the small signal

voltage gain of the DUT by setting vin at one millivolt RMS

and measuring output voltage. This method is sufficiently

accurate for values of RD less than a few thousand ohms.

Typical RD = 1 Kohm.

The value of gt is calculated from the first data point

taken with gp removed. Then for each succeeding point,

gp = ginis calculated using Equation 3-2. The value of g
is found from

























.1 V


.1 sPf


Figure 3.6. A Simple Amplifier used to Measure Trans-
conductance, gm, of the DUT.











p = gp g (3-4a)


= Igin -gt (3-4b)


= I-gm(H 1) gt mhos (3-4c)

Calculated values of g which compare favorably with

known values are convincing evidence that g is determined

by Equation 3-2.

B. Noise Measurement

1. Equipment

There are two difficulties in measuring electrical

noise. Both occur because of the small energies involved.

The first is to amplify the noise without contamination to

a usable level and the second is to find a standard to

which the noise can be compared.

a. Amplifier description

Figure 3-7 shows a block diagram of the noise measure-

ment system. The noise source will be described in the

next section and the DUT in connection with discussions of

particular experiments.

Immediately following the DUT is a low noise amplifier

(LNA) shown in Figure 3-8 which uses a high transconductance

JFET, type 2N6451, as the input of a cascode input stage.

The output is a bipolar transistor, type 2N3904. The cascode

is used to reduce Miller effect. The measured equivalent

noise voltage of the input stage as a function of source

resistance is shown in Figure 3-9 and agrees well with


















Device LOW NOISE AMPLIFIER Shall RF ATTENUATOR
Under < (LNA)
Test AV=30, 50 & 70 Db 0-110 Db in 0.1 Db Steps
(DUT) (See Figure 3.8) BW > 100 MHz





NOISE SOURCE IF Output
using a 500 KHz
5722 Vacuum Diode
(See Figure 3.10) Collins 51-SI RECEIVER VOLTMETER

AGC Disabled, AM Mode hp 3400
AV=1.3xI06, BW=3 KHz



Figure 3.7. Noise Measurement System Block Diagram.


















+20V


INPUT 0 Q1 -R7 A |
R7 11
R3 2N6451 00K _
F uOOeK L100K
100K

/77r r 7


Figure 3.8. Circuit for a Low Noise Amplifier (LNA).























4-




10--

I N
-t-




















10 10 10 10
0Figure 3.9. Amplifier Noise Voltage Referred to the Amplifier Input.
+-
"0
S-4
M--



Ln
L /
4- /













10 102 103 104

Source Resistance

Figure 3.9. Amplifier Noise Voltage Referred to the Amplifier Input.











theory. The input stage has an overall gain of 30 Db and

input resistance of 100 Kohms.

The second and third stages are identical 20 Db gain

cascodes using 2N4220A FET inputs and 2N3904 bipolar out-

puts. Because of the gain of the first stage, no special

effort was made to reduce noise in the later stages.

The final stage is a unity gain buffer having an

output impedance of approximately 50 ohms. A simple emitter

follower was found to operate more satisfactorily than

complex circuits having more precise gain and output

impedance.

The buffer is connected to one of the earlier stages

through a rotary switch having low capacitance between

contacts. The overall gain of the amplifier may then be

set to 30, 50 or 70 Db. The bandwidth depends on the gain

setting and is 3.5, 2.5, and 2.2 MHz, respectively.

Because of the high gain of the Collins receiver, only

30 Db of gain was necessary in the LNA. Higher gain in

the LNA is used in other related work.

Following the LNA is a Shall precision RF attenuator,

model 8841. The attenuation may be adjusted in 0.1 Db

steps from 0 to 110 Db. Input and output impedance is 50

ohms and the attenuator response is flat within less than

0.1 Db to over 100 MHz. The purpose of the attenuator is

to set the overall gain of the measurement system. This

is done by setting the noise voltage at the IF output of

the receiver to an acceptable value well above the receiver

noise.











The Collins 51-S1 receiver is used essentially as a

narrow band, high gain, tunable filter. It is used only in

the AM mode with a bandwidth of approximately 3 KHz. The

AGC is disabled so the gain is relatively constant near

1.3 x 10 from antenna input to IF output. Despite this,

the gain is found to vary slightly with signal level and

time apparentlyy because of temperature variations). For

this reason, all measurements are made with a constant IF

output voltage over a short time period (a few minutes is

adequate).

The IF output is measured with an hp 3400 true RMS

voltmeter. A true RMS reading is not necessary at this

point; it is only necessary to be able to set a repeatable

level. The 3400 is used here because of its frequency

response, range of scales, availability, ease of use in

this application (the hp 410 is usable but requires a

special AC probe) and because the 3400 was used in some of

the early calibration of the system.

b. Noise standard

The measurement method to be described in the next

section requires a noise source with a known level of

Gaussian white noise. The 5722 vacuum noise diode is such

a source and is used for this application because of avail-

ability and proven performance. The complete circuit is

shown in Figure 3-10. The use of the vacuum diode is well

documented elsewhere so only a brief description of the

noise source will be provided here [19, 20].



















.1 iif
Noise
572 Output

5722
Noise Z
Diode L
2A
.5 .5.5
270 2N4124 h ph 1 pf


10V 2N6474 P
NiCad --- V 180V
1N4151 L BB
Cel Is 8.2 .1 T .1
V VHH f





Figure 3.10. Circuit of a Noise Standard using a Vacuum Diode.











The noise diode produces shot noise at the anode when

operated in the temperature limited region. This noise is

easily shown to be


SI(f) = 2qleq amps2/Hz (3-5)


where I is the average anode current. The RMS noise
eq
current is the square root of SI(f) and the noise voltage

at the anode is simply calculated using the noise current

and the anode load impedance. This includes the anode

resistance, rp, of the diode which was found experimentally

on several tubes to be near

6 -1
r 1.2 x 106 I ohms (3-6)
p A

where IA is the average anode current in milliamps.

The tube is operated with a battery supplied anode

voltage of 170 to 200 volts. The anode current is adjusted

by varying the heater voltage, VHH, with a preregulator

type circuit and NiCad C or D cells to supply heater current.

The center tap of the heater is operated at AC ground and

small L-section filters are used in the other heater leads,

though they were generally found not to be necessary below

1 MHz. The anode load is a 1 Kohm resistor or a 25 milli-

henry commercial RF choke. The actual load is generally

the circuit in which noise is being measured.

Two noise sources were built. The first is in a

compact copper cabinet. This version uses a 1 Kohm load

and includes all batteries and metering necessary to be











self contained. The bandwidth is limited to approximately

5 MHz because of coaxial cable and other stray capacitances.

The second source is built into the LNA. This circuit uses

the supplies and metering of the first source. The band-

width is increased by the reduction of stray capacitance.

The real advantage of this circuit, however, is the reduc-

tion of stray noise. Supply leads are, of course, well

filtered.

2. Measurement of Noise Associated with JFET Gate Current

The circuit used to measure noise associated with FET

gate current is shown in Figure 3-11.

The circuit is first operated with the DUT gate dis-

connected and VHH = 0. The receiver is set to the desired

frequency, 450 KHz in this case. This frequency is chosen

to be above low frequency noise sources and still be low

enough that circuit layout is simple. Five hundred KHz was

not used because radio signals were usually evident, though

weak.

The tuned circuit is adjusted to give maximum noise

voltage at the received IF output, vIF. vIF is then

adjusted with the attenuator to some convenient level,

usually between 0.1 and 1.0 volts.

The attenuation is increased 3 Db and VHH on the noise

diode is increased until vIF is equal to the previous

reading. At this point, the noise at the input to the

attenuator and therefore to the input of the LNA has

increased 3 Db. The relation between the noise source and

LNA noises is found by:

























.1 pf


.I uf


VS



.1 If


5722
Noise
Diode


NOISE MEASURING SYSTEM


(See Figure 3.7)


V BB180V
BB


Figure 3.11.


Equipment for Measuring Noise Associated
with the Gate Current of the DUT.


DUT











2 2 2
eLNA + eNS 2eLNA (3-7a)


2q nR2 + 2qIAR2 =2(2qinR2) (3-7b)


in + IA = 21in (3-7c)


IA = 'in (3-7d)


where R is the unknown resistance at the input of the LNA

(essentially the equivalent parallel resistance of the tank

at resonance), q is electronic charge, IA is the average

anode current of the noise diode and I. is the equivalent

saturated diode current of the LNA referred to its input.

This can be related to the noise voltage plotted in Figure

3-9 by:


e2 = 2qinlZ 2 (3-8)


With Ii known, the DUT noise can be measured. The DUT is

connected and placed directly in liquid nitrogen. After

allowing a few seconds for cooling, the device is biased

to the proper Q point with VHH = 0. ID and IG of the DUT

are measured to determine M and the attenuator is set so

vIF is at a convenient level; usually the same as used in

the I. determination. The attenuation is increased 3 Db
in
and VHH is increased until vIF is the same as the previous

reading. At this point the noise at the input of the LNA

is given by:


e2 + e2 + e = 2(e2 + e2 (3-9a)
LNA DUT NS LNA DUT













A procedure similar to that used with Equation 3-7 gives


e e + eUT (3-9b)
NS eLNA DUT

Converting this to terms of equivalent saturated diode

current:


IG = IA I. (3-9c)
G eq A in

where I is measured as before, I. is known from previous
A in
measurements and IG eq' the equivalent saturated diode

current at the DUT gate, is then determined.

The procedure is repeated for various values of M

which is varied by changing VDD. IG eq versus IA is plotted

and compared to theory given in Chapter II.

3. Noise at the Substrate of a MOSFET

The method for measuring noise at the substrate of a

MOSFET is identical to that used for JFET gate noise out-

lined above except for those details necessary to provide

bias for the MOSFET.

4. Noise at a FET Drain

Two methods are used to measure DUT drain noise. The

general circuit applicable to each is.shown in Figure 3-12.

a. The first method is broad band and uses ZD =

1 Kohm. eLNA is measured with VHH 0 and the DUT dis-

connected. The attenuation is adjusted to set vIF at a

convenient level. VHH is used to set IA at a fixed level,

and the attenuator is adjusted until vIF equals its previous

level. A1 is the ratio of the first to the second attenuator
























.1 Ipf NOISE MEASUREMENT SYSTEM


5722
Noise
VS Diode


Figure 3.12. Circuit used to Measure Noise at the Drain of the DUT.


DD


(See Figure 3.7)


.1 wf


V B180V
BE











settings and the square of the noise voltage referred to

the LNA input is

e2
2 NS 2
eLNA eS (3-12)
LNA 2 NS
A -1
2

where A2 is the ratio of the new set of attenuator settings.

This assumes rd of the DUT is high (i.e., that the DUT is

operating in the saturation region).

It should be pointed out that this procedure is more

tedious than others described. It is outlined because some

of the early data were obtained with this method. It is

greatly simplified by setting A = 2 and adjusting IA with

3 Db increases in attenuator settings as for the gate

noise measurements. Equivalent currents can be used to

simplify the calculations and the equivalent current of

the DUT can be converted to a noise voltage if necessary.

b. The second method is similar to the.first except

the ZD is a parallel tuned circuit, Zp is a 25 mh commercial

RF choke, A = 2 and the method is identical to that used

for gate noise. Noise in terms of IG eq is easily found. To

convert to a noise voltage, ZT is measured with a vector

impedance meter or bridge at the appropriate frequency and

_- 21-
2 2
ed =d IZT (3-13)

The noise of the LNA presented in Figure 3-9 was

measured by this method with the DUT replaced with resistors











of various values. The resistor noise and that of the tuned

circuit was accounted for so the noise plotted is for the

amplifier only.

C. Stability of the DUT

As has been described it is possible for the JFET under

test to become unstable. Measurements made with an unstable

DUT, except those deliberately induced in the input conduc-

tance measurements, are not useful. The instability may

take two forms and may be detected in at least two ways.

If a tuned circuit is placed at the gate, oscillations

may occur. These are apparent when abrupt noise level of Q

point changes occur. Occasionally if the tuned circuit is

set within the received bandpass or its subharmonics, a

strong RF carrier is heard.

For resistive gate circuit, an abrupt Q point shift is

sometimes the only indication of instability. More often

the resistance with stray and device capacitance and the

diode action of the JFET gate form a relaxation oscillator

which is apparent in the receiver's speaker. For this

reason the speaker is always active. This form of insta-

bility occurs frequently when an electrometer is placed in

the gate circuit to measure IG.

D. Other Considerations

Time-of-day at which measurements are made is important.

During afternoon and early evening repeatable measurements

are difficult to obtain. This is in part due to atmospheric

noise, especially during the summer and fall months. It is








45


suspected, though not proven, that fluorescent lighting

used during the day throughout the building is a major

source of noise. In the evening most lights are off.

There is another white noise source that occasionally

switches on and off randomly at intervals from a fraction

of a second to thirty seconds during the day. The source

has not been located and measurements are not made when it

is apparent.

















CHAPTER IV

EXPERIMENTAL RESULTS

The procedures outlined in Chapter III were carried

out on a variety of devices. This chapter outlines the

results with some discussion of the conclusions to be drawn.

A more concise statement of conclusions is contained in

Chapter V as well as a summary of topics related to this

study which need additional attention.

Related research as outlined in Chapter I has laid

the groundwork for much of what is presented here, but in

no case have definitive statements been published. It is

suspected that one reason for this is the lack of DUT sta-

bility owing to the negative gate conductance.

A. Region of Operation to Produce Channel Avalanching

Before channel avalanching can be studied, two things

are necessary. The first is to identify the conditions

necessary to produce the avalanching and second, for the

gate current so generated to be at a usable level and

preferably free of currents from other sources. The pro-

cedure is outlined in Chapter III, section B.1, and the

results are shown in Figure 4-1 for two typical JFETs, one

n- and one p-channel. At low temperature and high drain

voltages both devices show clear negative slopes indicating

avalanche-generated gate currents. The negative slope is

46

















x U


\x


0o
^0


x n-channel

o p-channel


250
Temperature (OK)


Figure 4.1.


JFET Gate Current as a Function of Temperature
with VDS as a Parameter and One Percent Duty
Cycle.


104











103


10 -











1 -


300


350


_ T











the result of decreasing cross section of atoms in the

lattice with increasing temperature which results in lower

ionization rate [21]. The positive slopes at higher

temperature indicate thermally-generated gate currents which

are relatively independent of drain potential as would be

expected.

The results shown in Figure 4-1 were all obtained at

a one percent duty cycle. The average drain currents,

thermal resistance from manufacturer's specifications and

resulting maximum temperature rise are shown in Table 4-1.

All temperature rises are significantly less than 0.5 K.

The largest change in gate current is less than one percent

for a 0.50K rise in temperature at 150K and will be

neglected.



TABLE 4-1

TEMPERATURE RISE CALCULATIONS
AT LOW DUTY CYCLE


Average Thermal Maximum Maximum
Device ID Resistance VDS Temp. Rise

H(n-ch) 10 ua 5000K/W 40 0.20K

C(p-ch) 25 ua 3550K/W 40 0.360K



From Figure 4-1 it is determined that data taken at

150K will not show a significant thermal current in either

n- or p-channel devices and that for appropriate drain

voltages there will be measurable gate current.











Some measurements are taken at 770K with the DUT

immersed directly in liquid nitrogen. For this type of

operation the channel to case thermal resistances are

important. They are determined from thermocouple measure-

ments to be 3.6 x 102oK/W for the n-channel and 1.7 x 1020

K/W for the p-channel FETs. As expected these are somewhat

lower than the channel-to-ambient thermal resistances. The

only difficulty that might be expected at 77 K is carrier

freeze out in which the percentage of impurity atoms that

are ionized drops with temperature. This was observed below

100 K as evidenced by variations in transconductance and

IDSS. Data for one typical FET are shown in Figure 4-2 with

transconductance measured at 450 KHz. Freeze out is indi-

cated by the drop in both parameters at low temperature.

The studies involving channel avalanching may be run at

77 K since the relations involving generation of gate

currents are still valid. The only difficulty is that

slight changes in temperature cause considerable change in

some device parameters. Therefore care must be taken to

make related measurements under the same operating condi-

tions so the device temperature changes are minimal.

B. Drain-to-Gate Current Ratio

Figures 4-3 through 4-6 show gate current versus drain

current at duty cycles of 100 percent and 5 percent or

less. The 100 percent curves all show a clear downward

bend for high currents labeled Region B in the figures,and

at lower duty cycles the results appear linear. This





































x Drain Current

o Transconductance


. 6






4






-2
o




0
0
C)


- 2 I


3



i 0


3 75 100 125 150 175 200

Temperature (OK)


Figure 4.2.


JFET Transconductance and Saturated Drain Current with
VGS = 0 as Functions of Temperature.


2 +


1 +





























103 -.'









Sx 100% Duty Cycle

E0 o 1% Duty Cycle
o 10 -



-I-
4-

L O

+-



10
10 102 103

Drain Current (microamperes)

Figure 4.3. Device G Gate-to-Drain Current Relation.


















105-












104--










CD
L

o ( x 100% Duty Cycle

2 103.- o 2%0 Duty Cycle




+-



C(
0 O




102 II
10 102 103
Drain Current (microamperes)

Figure 4.4. Device AD Gate-to-Drain Current Relation.









































10

E
( c


M x
0

C

x 100% D
+ 10 o 2% Dut
L
L


t
4-

-I-Y
(D

.0




102I
10 102

Drain Current (microamperes)


uty Cycle

y Cycle


Figure 4.5. Device AE Gate-to-Drain Current Relation.


103











54































Ui)
L
104--












[ / x 100% Duty Cycle
o0103-- o 5% Duty Cycle
0


c-)



L O
o
c /
(-
CD_

102
102 103 104

Drain Current (microamperes)

Figure 4.6. Device C Gate-to-Drain Current Relation.










would indicate that self-heating is the cause of the non-

linearity in the 100 percent data.

A least squares power curve fit was done for the

entirety of each curve and for Region B of each curve. The

results are summarized in Table 4-2. For the entire low

duty cycle curves values of the exponent of Equation 3-1,

repeated here as Equation 4-1, are very near unity as would

be expected from the figures. The value of m near unity

indicated that the only source of gate current is channel

avalanching as is discussed in Chapter II.

m
I K I (4-1)
G D

A closer examination of the low duty cycle Region B

curve fit indicates that there is still some bend though it

may be small. As at least a partial explanation of this

curve, it is noted that the highest power dissipation in

the n-channel devices at low duty cycle will produce a

3.2 K temperature rise and for the p-channel device, a

9.30K rise will occur. These are sufficient to cause the

slight bending observed.

It can be concluded that the nonlinearity in Region B

of the data is strongly dominated by self heating and that

the slight bend remaining in the low duty cycle data is

due, at least in part, to self heating. The possibility

remains of other very small effects.

It is evident that minority carriers generated by

channel avalanching may be regarded for all practical














TABLE 4-2

LIST OF VALUES OF THE EXPONENT m
IN EQUATION 4-1


Entire Entire
Device Region B Curve Region B Curve

G number of points 3 8 5 16

m .52 .87 .94 .995


AD number of points 5 17 5 11

m .65 .93 .97 .994


AE number of points 8 20 6 14

m .62 .90 .96 .99


C number of points 5 10 7 14

m .52 .85 .91 .96



purposes in this study as the only source of gate current.

A note giving these results has been accepted for publica-

tion [22].

C. Gate Conductance of a JFET

The gate conductance of three JFETs was determined

using the method outlined in Chapter III, section B.2,and

the results are shown in Table 4-3. The fact that oscilla-

tions occur indicates that the input conductance is negative

as proposed.


__~













TABLE 4-3

DATA USED TO VERIFY THE CALCULATION OF GATE
CONDUCTANCE OF JFETs EXHIBITING
CHANNEL AVALANCHING


R ID IG M -gi Calculated
(Kohm) (ma) (pa) (jmho) Rp (Kohm)

DEVICE M---2N4220A---g =4.64 mmho

-- 3.81 33.5 1.0089 40.80
1000 3.82 34.5 1.0091 41.92 894
120 3.81 41.5 1.0110 50.66 102

DEVICE N---2N4220A---g =4.18 mmho

1.68 19.01 1.0114 47.87
1000 1.68 19.45 1.0117 48.96 913
120 1.70 22.27 1.0133 55.48 131
100 1.71 22.98 1.0136 56.94 110

DEVICE EH B-5 (U or F)--g =14.0 mmho

13.2 49.77 1.0039 52.95
1000 13.2 50.81 1.0039 54.16 900
120 13.2 57.40 1.0044 61.14 123
100 13.2 58.95 1.0045 62.80 102



The agreement between the known value of parallel

conductance (expressed as the resistance R ) and the value
p
calculated using Equation 3-4c indicates that the magnitude

of the input conductance is determined by the FET trans-

conductance and the multiplication factor as given in Equa-

tion 3-2 and shown here as Equation 4-2.


(4-2)


gin = -gmM 1)
M


A note giving these results has been accepted for

publication [23].











D. Conductance at a MOSFET Substrate

The experiment performed on JFETs to determine gate

conductance was repeated on MOSFETs with one change. The

devices were operated at room temperature. The frequency

of oscillation was set at 130 KHz.

The summary of results is shown in Table 4-4. There

appears to be a systematic error which could be explained

in part by a thermal component of substrate current. The

increasing error at lower values of Rp would indicate,

however, that the major cause of error must come from some

other cause as yet undetermined.

It is verified by the oscillations that the substrate

conductance is negative. The relation between known and

calculated conductances in Table 4-4 indicates that a major

part of the substrate input conductance is determined by

Equation 4-3 where the transconductance is from substrate

to drain with VG fixed.

An attempt was made to measure the substrate conduc-

tance of a p-channel MOSFET. Oscillations occurred readily

at room temperature indicating negative conductance, but

adequate data were not obtained. The difficulty was caused

by excessive temperature rise and drift. Because the

multiplication factor of p-channel FETs is much lower than

comparable n-channel devices, much higher drain voltage is

required to produce oscillation. The drain voltage in this

case exceeded the manufacturer's specification by a large

factor. Because of the excessive temperature rise and drift,

the value of M and therefore ISUB varied erratically.















TABLE 4-4


DATA USED TO VERIFY THE CALCULATION OF SUBSTRATE CONDUCTANCE
FOR MOSFETs AT ROOM TEMPERATURE


R ID IG g -g. Calculated
p D G m in R (Kohms)
(Kohms) Milliamps microamps millimhos micromhos Rp (Kohms)

DEVICE W (3N169)

m25.7 203 1.00796 8.94 71.2 ---
100 25.7 236 1.00927 8.98 83.3 83
68 25.7 257 1.0101 9.00 90.9 51
22 25.9 350 1.0137 9.00 123 19
10 26.1 518 1.0202 8.98 182 9.0
8.2 26.1 593 1.0232 8.96 208 7.3
5.6 26.3 768 1.0301 8.96 270 5.0


DEVICE X (2N4351)

1 14.2 150 1.0107 7.96 85.0 ----
100 14.5 170 1.0119 7.98 94.7 99
68 14.4 178 1.0125 7.96 99.7 68
22 14.3 242 1.0172 7.98 138 19
10 14.7 348 1.0242 8.06 196 9.0
8.2 14.7 398 1.0278 8.08 225 7.2
5.6 14.8 510 1.0357 8.16 291 4.8
4.7 14.8 585 1.0412 8.18 337 4.0
2.2 15.2 1.07x10 1.0757 8.41 637 1.8





















ID
milliamps


IG
microamps


TABLE 4-4 (continued)

M gm
millimhos


-gin
micromhos


Calculated
Rp (Kohms)


DEVICE Y (3N169)


1.00787
1.00919
1.00974
1.0133
1.0199
1.0219
1.0274
1.0328
1.0641
1.128
1.189
1.293


9.49
9.53
9.53
9.53
9.55
9.55
9.59
9.63
9.73
10.1
10.5
11.0


Rp
(Kohms)


00

100
68
22
10
8.2
5.6
4.7
2.2
1.0
.68
.47


22.8
22.4
22.5
22.5
22.8
22.8
22.7
22.8
22.4
24.0
25.0
26.1


178
204
217
295
445
488
605
725
1.35xl03
2.73xl03
3.98x103
5.92x103


74.7
87.6
92.8
127
190
209
263
316
624
1.29x103
1.98x103
3.24x103


77
55
19
8.7
7.4
5.3
4.1
1.8
.82
.52
.32











E. Noise Associated with Channel Avalanche-Induced
Gate Current in JFETs

Figures 4-7 through 4-9 show data for three devices

operated as outlined in Chapter III, section C.2, with the

DUT cooled to 770K by liquid nitrogen. At this temperature

the gate current is produced entirely by channel avalanching

and the equivalent saturated diode current associated with

the gate current should be given by Equation 2-26b shown

here as Equation 4-3.


IG eq G= IG : IG (4-3)


The figures show a linear relation between IG and IG eq

as would be expected for low values of M and the approxima-

tion in Equation 4-3 is verified. The more exact relation

including H cannot be verified until JFETs exhibiting higher

values of M are found.

The more complete Equation 2-25b which includes gate

current noise resulting from multiplied channel noise cannot

be verified without much higher values of M. It is doubtful

that such JFETs presently exist.

A note containing these results has been accepted for

publication [24].

F. Source Current Enhancement

The enhancement of source current by return of secondary

minority carriers from channel avalanching was mentioned

in Chapter I though it was not listed as an objective of

this research. Attempts were made while performing other

























100




IO
a)


E










r-
00
L












C

O

00
o
"o
+-

. o
-4-






-I-
> o
a)










r
a











1 10 100
Gate Current, IG (microamperes)



Figure 4.7. Device R Gate Noise as a Function of
Gate Current.
+-I-













Gate Current.
































U)
10C




L
0
CL
E
L0
a0


E



OlC
o1C


+-I-

L
c

L
3



0


0)


4-
co
a-
-L





.U


1 10 1(
Gate Current, IG (microamperes)


Figure 4.8. Device S Gate Noise as a Function of
Gate Current.












64













100.

0 o
0)
cn



L
O
(0
0

E

Cr
a-

10

C
S)
c0
L
LO


0



4-





L.
+--





a-





LU


1 10 100
Gate Current, IG (microamperes)


Figure 4.9. Device FH7 Gate Noise as a Function of
Gate Current.













experiments to observe such an enhancement. The reason for

the concern is that such a partitioning of the minority

carriers would alter the DC current and noise relation-

ships.

It was possible that source current enhancement was

observed in several devices, but it is more likely that the

behavior had some other cause such as temperature or voltage

variations. In any event the changes observed were so small

(one percent or less) that neglecting this effect would not

significantly change other results in this study.

















CHAPTER V

CONCLUSIONS AND DISCUSSION

This has been a study of some effects related to

avalanching in the channel of Field Effect Devices. JFETs

and MOSFETs were used though the JFET was the preferred

device in most work. Attempts were made to collect data on

both n- and p-channel devices. All devices studied are

available commercially with the exception of one fabricated

in the University of Florida Microelectronics Laboratory,

and that one was fabricated under contract for commercial

application.

The experimental results of Chapter IV agree with the

theory presented in Chapter II. The conclusions to be

drawn from the results are:

1. At low temperature the dominant source of gate

current in JFETs is the collection by the gate depletion

region of minority carriers generated by avalanching in the

channel.

2. The carriers generated by channel avalanching and

collected by the gate depletion region cause a negative

conductance at the gate of JFETs which can lead to insta-

bilities. The conductance at the gate can be calculated as


g. (M_)( (5-1)
gin m
M











provided the thermal component of gate current is negli-

gible.

3. The negative conductance of the JFET gate with

channel avalanching can occur at room temperatures and above

in some n-channel JFETs. In p-channel devices the ioniza-

tion rate is low at room temperature and reduced tempera-

ture is required to produce significant negative gate con-

ductance.

4. The noise associated with gate current in n-channel

JFETs as represented by an equivalent saturated diode

current may be represented by


G eq IG (5-2)


5. MOSFETs show a negative conductance at the sub-

strate similar to that of the JFET gate. This can be a

source of instability at room or lower temperature if an

impedance is placed in the substrate circuit. The insta-

bility can be a stable and possibly useful oscillation if

the impedance is a tuned circuit. This circuit appears to

operate reliably at room temperature. The substrate con-

ductance is given by Equation 5-1 for a fixed VGS.

These conclusions indicate that avalanching in the

channel of FETs may be a limiting factor in reducing the

size of this type of device. Size reduction has several

desirable features such as improvement of some device

parameters and use of less area on a silicon chip. However,











this is at the expense of increased noise and possible

instabilities, especially in n-channel FETs.

There are topics related to avalanching in FETs which

remain to be studied. Those evident from this work are:

1. The exponents in the ID/IG data are very close to

unity indicating the very strong dominance of avalanching

in generating gate current. However, the exponents in

several cases differ from unity sufficiently, with very high

correlation coefficients in the curve fitting to raise a

question concerning the existence of some very small effects.

It is suspected that this was the result of transients in

the pulsing techniques used, but more accurate data would

possibly detect other effects. One such possibility is that

the minority carriers may not be collected as fast as is

now postulated and that they do contribute to a very small

amount of avalanching in the channel before being collected

by the gate depletion region.

2. The multiplication factor in all JFETs studied

was relatively small. As a result only the approximate

relation of Equation 5-2 was verified. Devices with higher

multiplication factors could be used to verify the more

complete


IG eq M IG (5,3)

In addition with higher values of M the effect of S. (0)
-S
should become evident and the complete equation for gate

noise could be verified.











IG eq = (M 1) I eq + M IG (5-4)


3. The substrate input conductance for MOSFETs indi-

cated only partial agreement with theory at room tempera-

ture. A thermal component of substrate current will not

explain the anomaly completely. Measurements have not yet

been made at low temperature and perhaps this would be the

proper next step.

4. The drain resistance of a FET is reduced by channel

avalanching. A usable FET model incorporating this effect

needs to be developed and demonstrated, especially for

MOSFETs.

5. The possibility of source current enhancement due

to return of avalanche-generated minority carriers to the

source instead of the depletion region is still not settled.

















BIBLIOGRAPHY


1. Richard S. C. Cobbold, Theory and Applications of Field
Effect Transistors, Wiley-Interscience, 1970.

2. W. Shockley, "A Unipolar 'Field-Effect' Transistor,"
Proceedings of the I.R.E., Vol. 40, pp. 1365-76,
November 1952.

3. G. C. Dacey g I. M. Ross, "The Field Effect Transistor,"
Bell System Technical Journal, Vol. 34, pp. 1149-89,
November 1955.

4. E. P. Fowler, "Effect of Operating Conditions on Reverse
Gate Current of Junction F.E.T.'s," Electronics
Letters, Vol. 4, No. 11, May 31, 1968.

5. Masato Nakahara, Hiroshi Iwasawa, S Kazuyoski Yasutake,
"Anomalous Enhancement of Substrate Terminal Current
Beyond Pinch-Off in Silicon N-Channel MOS Transis-
tors and Its Related Phenomena," Proceedings of the
IEEE, Vol. 56, pp. 2088-20-90, November 1968.

6. M. Nakahara, H. Iwasawa, & K. Yasutake, "Anomalous
Low-Frequency Noise Enhancement Beyond Pinch-Off
in Silicon N-Channel MOS Transistors," Proceedings
of the IEEE, Vol. 57, pp. 2177-8, December 1969.

7. M. Nakahara, H. Iwasawa, S K. Yasutake, "Anomalous
Enhancement of Substrate Terminal Current Beyond
Pinch-Off in Silicon N-Channel MOS Transistor,"
Electronics and Communications in Japan, Vol. 52-C,
No. 3, 1969.

8. R. D. Ryan, "The Gate Currents of Junction Field Effect
Transistors at Low Temperatures," Proceedings of the
IEEE, pp. 1226, June 1969.

9. R. D. Ryan, "Substrate Current in Silicon p-Channel
MOS Transistors," Proceedings of the IEEE, pp.
1424-5, August 1969.

10. M. Nakahara & I. Kobayashi, "On the Gate Current and
Noise Behavior in Pinched Off Silicon JFETs," Pro-
ceedings of the IEEE, Vol. 58, pp. 1158-9, July
1970.











11. A. Ambrozy, "On the Gate Current of Junction Field
Effect Transistors," Periodica Polytechnica Elec-
trical Engineering, Vol. 14, pp. 355-61, 1970.

12. F. M. Klaassen, "On the Substrate Current Noise in
MOS Transistors Beyond Pinchoff," Proceedings of
the IEEE, Vol. 59, No. 2, pp. 331-2, February 1971.

13. Chang Soo Kim, Avalanche Multiplication and Related
Noise in Silicon MOSFET's, University of Florida,
Ph.D. Dissertation, 1971.

14. R. R. Troutman, "Low-Level Avalanche Multiplication
in IGFET's," IEDM Technical Digest, 1974.

15. S. A. Abbas, "Substrate Current-A Device Process
Monitor, IEDM Technical Digest, 1974.

16. Y. A. El-Mansy & A. R. Boothroyd, "A Simple Two Dimen-
sional Saturation Model of Short Channel IGFET's for
CAD Applications," IEDM Technical Digest, 1974.

17. Y. A. El-Mansy & D. M. Caughey, "Modelling Weak
Avalanche Multiplication Currents in IGFET's and
SOS Transistors for CAD," IEDM Technical Digest,
1975.

18. A. van der Ziel & E. R. Chenette, "Noise in Solid State
Devices," Advances in Electronics, accepted for
publication.

19. A. van der Ziel, Noise: Sources, Characterization,
Measurement, Prentice-Hall, 1970.

20. A. van der Ziel, Noise in Measurements, John Wiley and
Sons, 1976.

21. C. R. Crowell 9 S. M. Sze, "Temperature Dependence of
Avalanche Multiplication in Semiconductors,"
Applied Physics Letters, Vol. 9, No. 6, Sept. 15,
1966.

22. L. M. Rucker, E. R. Chenette, & A. Ambrozy, "On the
Gate-to-Drain Current Ratio in Junction FETs at
Low Temperature," Solid State Electronics, accepted
for publication.

23. A. van der Ziel & L. M. Rucker, "Oscillations in JFETs
Exhibiting Current Multiplication in the Channel,"
Solid State Electronics, accepted for publication.


_ _








72


24. L. M. Rucker & A. van der Ziel, "Noise Associated with
JFET Gate Current Resulting from Avalanching in
the Channel," Solid State Electronics, accepted for
publication.
















BIOGRAPHICAL SKETCH

Lucien Maurice Rucker, III, was born in Chicago,

Illinois, on January 18, 1941. In 1947 his family moved

to Montgomery, Alabama, where he graduated from Catholic

High School of Montgomery in 1959. He attended Auburn

University and received a Bachelor of Science degree in

Electrical Engineering and a Commission in the United

States Air Force in 1963. The next four years were spent

on active duty as an engineer at Eglin AFB, Florida,

working largely with the Electronic Countermeasures Test

Facility there.

In 1968 he entered the University of Florida and

received a Master of Science degree in Electrical Engineer-

ing in 1969. From 1969 to 1974 he worked as a Development

Engineer with Hewlett Packard Company in Colorado Springs,

Colorado. Returning to the University of Florida in 1974,

he has until present pursued the Doctor of Philosophy

degree.

In 1961 he married the former Barbara Bourne and is

the father of one son, Michael. He is a member of the

Institute of Electrical and Electronics Engineers and Eta

Kappa Nu.











I certify that I have read this study and that in my
opinion it conforms to acceptable standards of scholarly
presentation and is fully adequate, in scope and quality,
as a dissertation for the degree of Doctor of Philosophy.



Aldert van der Ziel, Chai man
Professor of Electrical Engineering

I certify that I have read this study and that in my
opinion it conforms to acceptable standards of scholarly
presentation and is fully adequate, in scope and quality,
as a dissertation for the degree of Doctor of Philosophy.



Alan D. Sutherland, Co-Chairman
Professor of Electrical Engineering

I certify that I have read this study and that in my
opinion it conforms to acceptable standards of scholarly
presentation and is fully adequate, in scope and quality,
as a dissertation for the degree of Doctor of Philosophy.



Eugene R. Chenette
Professor of Electrical Engineering

I certify that I have read this study and that in my
opinion it conforms to acceptable standards of scholarly
presentation and is fully adequate, in scope and quality,
as a dissertation for the degree of Doctor of Philosophy.

/'/ /'

Jac wR. Smith
P essor of Electrical Engineering

I certify that I have read this study and that in my
opinion it conforms to acceptable standards of scholarly
presentation and is fully adequate, in scope and quality,
as a dissertation for the degree of Doctor of Philosophy.



Zoran R. Pop Sto anovic
Professor of Mathematics










This dissertation was submitted to the Graduate
Faculty of the College of Engineering and to the Graduate
Council, and was accepted as partial fulfillment of the
requirements for the degree of Doctor of Philosophy.

December 1977



Dean, College of Engineering



Dean, Graduate School









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TITLE: Investigation of some Properties of Carriers in Field-Effect Devices
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