Study of the optimum charge-transfer image sensor

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Study of the optimum charge-transfer image sensor
Tseng, Hsin-Fu, 1940-
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vi, 168 leaves : ill. ; 28 cm.


Subjects / Keywords:
Capacitance ( jstor )
Charge transfer ( jstor )
Diodes ( jstor )
Drains ( jstor )
Electric potential ( jstor )
Sensors ( jstor )
Shift registers ( jstor )
Signals ( jstor )
Tetrodes ( jstor )
Transistors ( jstor )
Dissertations, Academic -- Electrical Engineering -- UF
Electrical Engineering thesis Ph. D
Optoelectronic devices ( lcsh )
bibliography ( marcgt )
non-fiction ( marcgt )


Thesis--University of Florida.
Bibliography: leaves 164-167.
General Note:
General Note:
Statement of Responsibility:
by Hsin-Fu Tseng.

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Hsin-Fu Tseng





I would like to express my deepest gratitude to Professor S.S. Li

for his guidance and encouragement throughout the research and prepara-

tion of this dissertation. Also, I give thanks to Professors E. R.

Chenette, F. A. Lindholm, D. R. MacQuigg, J. K. Watson, and K. Y. Chen

for their advice and support. In addition, I would like to acknowledge

the many helpful discussions with Mr. G. P. Weckler, and Dr. R. W. Bro-

densen at Reticon Corporation.

Thanks are also due to Mr. Ed Webb for carefully proofreading the

manuscript, and Reticon Corporation for financial support and fabrication

of the devices used in this study.



ACKNOWLEDGEMENTS. . ... ............... ii

ABSTRACT. . . .. . .................. v


1 INTRODUCTION . . .... . . . 1


2.1 Introduction. . . ... .. . .. 5
2.2 The Architecture of A Solid-State Image Sensor.. . 5
2.3 Device Structure to Realize the Optimum Architecture. 17

2.3.1 Device Structure . . . ... 18
2,3.2 Device Operation . . . .. 26


3.1 Introduction. ........... . . 31
3.2 Device Structure and Operation. . . ... 35

3.2.1 Device Structure . . . ... .35
3.2.2 Device Operation . . . ... .38
3.2.3 Input and Output Structures. .... . 43

3.3 Performance Limitations . . . ... .43
3.4 Tetrode Structure Bucket-Brigade Device . ... 46
3.5 Derivation of Transfer Inefficiency Model ...... 51

3.5.1 Intrinsic Transfer Rate. . . ... 52
3.5.2 Transfer Inefficiency Due to Subthreshold
Leakage of the IGFETS. . . ... 61
3.5.3 Transfer Inefficiency Due to Barrier-Height
Modulation . . .. . 73


4.1 Charge-Storage Operation of a Photodiode. . .. .84
4.2 Sensing Diode to BBD Analog Register Charge-Transfer
Mechanism . . . . .... 88


4.3 Anti-Blooming Mechanism . . . .. 96
4.4 Noise Analysis . . . . . 101

4.4.1 Noise Sources Associated with the Sensing
Diodes . . . . . 101
4.4.2 Noise Sources Associated with the Common
Video Lines . . . .. .. 103
4.4.3 Noise Sources Associated with the BBD Shift
Register .... . . . . 104


5.1 Device Fabrication . . . ... .108
5.2 Measurements . . . . . 109

5.2.1 Barrier-Height Modulation Measurement . 110
5.2.2 Bucket-Brigade Shift Register Transfer
Inefficiency Measurement. . . 110
5.2.3 Optical-to-Electrical Transfer Characteristics
Measurement . . . ... 115
5.2.4 Saturation Charge Measurement . ... .115


6.1 Introduction . . . . . 119
6.2 Experimental Results of the Bucket-Brigade Shift
Register . . . . . 119

6.2.1 Experimental Verification of the Barrier-Height
Modulation Model. . . . ... 120
6.2.2 Experimental Verification of the Intrinsic
Transfer Rate Model . . ... 129
6.2.3 Improvement of Transfer Efficiency by Using
Selective Ion Implantation. . . .131
6.2.4 A Proposed BBD Structure with Improved Perfor-
mance . . . . . 139

6.3 Experimental Results of the Image Sensor Performance 140

6.3.1 BBD Analog Shift Register . . ... .140
6.3.2 Image Test. . . . . ... 144
6.3.3 Transfer Characteristics. . . ... 149
6.3.4 Saturation Signal and Dark Current. . ... 151
6.3.5 Blooming Characteristic . . ... .154
6.3.6 Noise Performance and Dynamic Range . .. .157

7 CONCLUSIONS . . . . . . 162

REFERENCES. . . . . . . ... 164

BIOGRAPHICAL SKETCH . . . . ... .. 168

Abstract of Dissertation Presented to the Graduate Council
of the University of Florida in Partial Fulfillment of the Requirements
for the Degree of Doctor of Philosophy



Hsin-Fu Tseng

March 1979

Chairman: Sheng-San Li
Major Department: Electrical Engineering

This research deals with an investigation into the optimum structure

for a solid-state image sensor. This optimum structure consists of dif-

fused diodes for photosensing, and either a bucket-brigade or charge-coupled

transfer register for signal readout. The photodiode sensors offer the

advantages of full, smooth spectral response and high quantum efficiency,

while the charge-transfer register provides a low noise self-scanned video

output. A matrix array with two tetrode bucket-brigade readout registers

is fabricated and studied. This array consists of 10,000 photodiodes ar-

ranged in 100 columns and 100 rows. Each row of diodes is selected in

sequence by a digital scanning register, and the resulting signal charges

are transferred in parallel to two 50 stage odd and even bucket-brigade

registers by means of video lines and transfer gates common to all diodes

in a column. The outputs of the two 50 stage registers are then multi-

plexed to obtain a single 100 stage video signal.

Models describing the operating mechanisms of the bucket-brigade and

image sensor devices are developed. It is shown that for a tetrode bucket-

brigade device the high frequency operation is limited by the intrinsic

transfer rate of the tetrode gate, while the transfer inefficiency at low

frequencies is mainly determined by the barrier-height modulation of the

transfer gate. To improve the performance of the bucket-brigade, the re-

gions under the tetrode and transfer gates are implanted to increase the

effective substrate concentration; this reduces the barrier-height modu-

lation and significantly improves the bucket-brigade's performance. The

merits and disadvantages of the implanted device are discussed, which

leads to a proposed new bucket-brigade structure. It is shown that the

charge-transfer efficiency between the sensing diode and analog shift

register degrades sharply with decreasing light level due to the subthresh-

old leakage current of the transfer gates. By using a unique method to

provide a background or fat-zero charge, this transfer inefficiency is

eliminated, and the image sensor exhibits a linear photo-response with

a dynamic range of more than 600 to 1 at operating frequencies up to

10 MHz.



Electronic imaging devices perform the task of converting a pattern

of incident radiation falling upon the surface of the sensor into an

electrical signal which is an ordered, sequential reproduction of the ra-

diation pattern. The basic architecture of an image sensor, therefore,

can be reduced to two basic functions, namely, the detection of photo-

generated carriers and the readout of information gained thereby. For

some time the successful development of solid-state image sensors has

been regarded as a highly desirable goal, since solid-state sensors are

superior in performance and could be cheaper than electron beam scanned

camera tubes due to their small size, low power consumption, high reli-

ability, and long life. In addition, their expected ruggedness and

immunity to shock, vibration, and electromagnetic field provide attractive

features for such devices. However, until recently, the state of develop-

ment of solid-state image sensors was still far from satisfactory.

The development of solid-state image sensors began in the early 60's

and with the rapid advancement of semiconductor technology, several types

of image sensors were developed. They are referred to as self-scanned

photodiode arrays [1-3], charge injection image arrays [4-6], and charge-

coupled image arrays [7-17]. Each type of array uses a different

architecture to perform the photo-detection and the signal readout func-

tions. As a result, each type of device possesses certain advantages and

drawbacks which limit its performance.

Recently a new structure which combines the advantages of each of

these image sensors has been reported by Tseng and Weckler [18-20]. This

new structure employs photodiodes for signal detection and a low noise

charge-transfer analog shift register for readout. This combination to-

gether with a built-in anti-blooming structure results in an optimum

image sensor. The optimum sensor possesses all the desired characteris-

tics such as minimum fixed-pattern noise, high dynamic range, smooth and

broad spectral response, high quantum efficiency, uniform sensitivity,

immunity to overload blooming, and versatility of operation. It is im-

portant and highly desirable that such a solid-state image sensor be

developed and studied.

In this dissertation, the operating mechanism and performance limi-

tations of a matrix charge-transfer image sensor having optimal charac-

teristics are investigated. This image sensor consists of 10,000

photodiodes arranged in 100 columns and 100 rows. Each row of diodes

is selected in sequence by a scanning digital register, and the signal

charges are transferred in parallel into two tetrode bucket-brigade

analog registers [21-27] for readout. Since the analog shift register

constitutes a very important part of the imaging device, a large segment

of this research effort was devoted to the modeling and study of the BBD

analog register.

In Chapter 2, the building blocks of the common image sensors are

reviewed, and the new architecture which results in the optimal solid-

state image sensor is discussed in detail. The organization and operation

of the matrix array which realizes the optimal architecture is described.

In Chapter 3, the operation and performance limitations of the basic

and improved tetrode bucket-brigade devices are analyzed, and models


describing the mechanisms which govern the transfer efficiency and

operating speed of the BBD are developed. The barrier-height modulation

model developed to explain the low frequency transfer inefficiency of

the BBD is an improved version of Yau's [28] and Taylor's [29] short-

channel models. In this model, the effects of drain potential and the

gate-electrode fringing field in the drain depletion region [30] are

taken into account in deriving the threshold voltage of the MOS transis-

tor. This model is very useful for MOS circuit simulation, and can be

implemented easily into the simulation program.

Chapter 4 contains the analysis of the operating mechanisms and

design formulations for the optimal matrix array. A unique "fill and

spill" technique [31] used to eliminate the charge transfer inefficiency

between the sensing diode and the BBD register is discussed in detail.

The limitations of the anti-blooming structure for minimizing the signal

degradation due to saturation are also presented.

In Chapter 5, device fabrication and measurement procedures are

described. The fabrication process used was n-channel, double-layer

silicon-gate technology. The substrate concentrations used in this
14 15 -3
study were 6 x 10 and 1.7 x 10 cm

Chapter 6 presents the experimental results. It was concluded that

while high frequency operation of the BBD register is limited by its

intrinsic transfer rate, the transfer inefficiency at low frequencies is

mainly determined by the barrier-height modulation of the transfer gate.

To obtain a BBD register with good transfer efficiency and reasonable

speed, the substrate concentration must be much higher than 1.7 x 1015
cm However, if a low resistivity substrate is used for fabricating

the BBD register, the body effect [32] of the high substrate concentration

will make the peripheral circuits inoperable. To solve this dilemma, a

selective ion implant technique [33] was employed in which only the regions

under the BBD gates were implanted to minimize the barrier-height modula-

tion. This technique resulted in a high performance BBD register. The

limitations of the high performance BBD are discussed, which lead to a

proposed new BBD structure. Finally, the experimental results of the

optimal matrix array which incorporated the high performance BBD register

are reported. The optical-to-electrical transfer characteristics with

and without using the "fill and spill" technique are compared, and the

noise performance is presented.

Chapter 7 contains the conclusions of this work.



2.1 Introduction

Evolution has produced several solid-state image sensors, each pos-

sessing different architectures. Most of these can be broken down into

combinations of four basic building blocks. This chapter will present a

review of these building blocks and discuss in detail a new architecture

which results in the optimal solid-state image sensor.

2.2 The Architecture of A Solid-State Image Sensor

The solid-state image sensor takes advantage of the highly developed

silicon integrated circuit technology. The mechanism of detection is

based on the absorption by silicon of photons within an energy range of

1.1 eV to about 6 eV; this corresponds to a wavelength range of 1.1 pm

to 0.2 pm as shown in Figure 2.1 by a typical spectral response curve.

When a photon is absorbed, it generates an electron-hole pair. If we are

to detect this electron-hole pair, the components must be separated.

This is normally accomplished by the depletion region of a p-n junction

or the depletion region induced by applying the appropriate voltage to

an MOS capacitor. This is also referred to as a potential well. In

either case, the electron and hole are separated and the charge equiva-

lent to one electron will then appear on the depletion region capacitance.




) 0.4- /


200 300 400 500 600 700 800 900 1000 1100

Figure 2.1 Typical spectral response of a diffused diode.

Let us briefly compare these two basic detection mechanisms. The

internal quantum efficiencies can for all practical purposes be assumed

to be the same for both mechanisms, i.e., the efficiency of collecting

photo-generated electron-hole pairs. The main difference is in the ex-

ternal quantum efficiency of the two mechanisms. Figure 2.2 shows the

basic structure of these two detectors. The external quantum efficiency

of the diffused photodiode suffers minimum losses due to only two inter-

faces between materials of different refractive indices, i.e., Air-Si02

interface and Si02-Si interface. The thickness of the Si02 is such that

the modulation of the spectral response of the diffused photodiode is

negligible. It is apparent from Figure 2.2 that for the field induced

detector an additional two interfaces are present to introduce losses

[34]. Furthermore, the transparent electrode is not really transparent

since it is usually polysilicon. Because silicon is absorptive, some of

the incident photons are absorbed in this layer. This is particularly

true for the short wavelength or the blue end of the spectrum. The use

of exotic metallic materials [35] has resulted in field plates that are

more transparent over the spectral range of interest than is polysilicon;

however, these materials are foreign to standard integrated circuit tech-


Furthermore, the thickness of these films is subject to normal

processing variations. It is, therefore, difficult to insure reprodu-

cibility of sensitivity, uniformity, or spectral response. It is

apparent that the diffused photodiode is a far superior detector, pos-

sessing the following advantages:

(1) external quantum efficiency approximately three times that of

the quasi-transparent electrode employing polysilicon;


J hv




Figure 2.2 Two basic photodetector structures.


(2) full spectral response extending from 0.2 pm to 1.1 pm; and

(3) a relatively smooth spectral response not subject to process


Having now detected internally the absorption of a photon, it is

necessary that this information be made available at a terminal. Here

lies another of the principal differences in the design of solid-state

image sensors. Figure 2.3 shows schematically two approaches used to

interrogate and read out the individual picture elements of an image

sensor. Each approach uses a shift register to read out the information

stored on each individual photosensitive element or pixel. In the first

case a digital shift register is used to sequentially access a transfer

switch which connects individual pixels in turn to a common terminal.

This approach has the definite advantage that digital shift registers

and multiplex switches have been highly developed, use standard MOS pro-

cesses and are relatively easy to implement. The performance of this

readout technique is dependent on both the total number of multiplex

switches and on the uniformity of the multiplexing function, i.e., ideally

each multiplex switch and its drive should be identical. Non-uniform

multiplexing results in a fixed-pattern modulation which is superimposed

on the video information from the pixels. Differential signal processing

techniques have recently been incorporated which have reduced the fixed-

pattern component to a negligible level. The fixed pattern has been re-

duced to the point where the total number of multiplex switches is now

of practical significance. The random noise depends directly on the

size of the output capacitance which in turn is a function of the number

of multiplex switches connected to the output line. In the majority of

applications, particularly those for which the solid-state image sensor



i i 'T--l-T-


Figure 2.3 Techniques for interrogating and reading-out picture elements.


serves as an input to a machine, random noise does not appear to be a

practical problem. The level of the random noise, however, does set a

basic limit to the minimum detectable illumination level that can be


The second approach, shown in Figure 2.3, also employs a transfer

switch (really an adjustable barrier) for each pixel; however, all pixels

are sampled simultaneously, thus transferring all the information in

parallel into an analog shift register. This information is then clocked

to an output terminal at the end of the analog shift register. The ana-

log shift register has been highly developed over the past few years.

Charge-transfer devices, both bucket-brigade [33] and charge-coupled [36],

can now be made with transfer efficiencies exceeding 0.9999 at megahertz

clocking rates; therefore, the initial problems of shading and loss of

resolution are no longer a serious problem.

Figure 2.4 shows four architectures that may be implemented using

the building blocks described above. Let us begin by examining each

structure. The first structure to be discussed uses photodiodes as the

detectors and a digital shift register to sequentially interrogate these

diodes and is depicted in the figure as Combination A. This structure

operates in the charge-storage mode [1] and is commonly referred to as

a self-scanned photodiode array [2,3]. To obtain line storage requires

a single multiplex switch connected to each photodiode, thus making pos-

sible high density linear arrays which possess all the advantages of

the photodiode detector. To obtain frame storage in a matrix or two-

dimensional array requires that each photodiode have two multiplex

switches associated with it. As a result, the size is limited since

the minimum center-to-center spacing is about 75 pm [37]. For linear

/ /

h j




/ I I I


v /Peoly-Silicor
> r-'-_I- n-iii




Figure 2.4 Four basic architectures of a solid-state image sensor.



arrays, this architecture is perfectly adequate for realizing long, high

density arrays. Linear arrays approaching 2000 pixels in length with

pixels as close as 15 pm centers have been available for some time [38].

This architecture, however, has reportedly two serious shortcomings. The

one most often referred to is the output capacitance, which increases

directly with the number of pixels. Its effect is to increase directly

the thermodynamic or random noise of the system, thus limiting the mini-

mum number of photons/pixel that can be detected. The other is referred

to as fixed-pattern noise, which originates from the non-uniformity of

the shift register and multiplex switches. This noise is discernible

primarily at low levels of illumination. However, it can be eliminated

by using differential signal processing techniques and is, therefore,

much less of a problem now as compared to earlier arrays using this


The second architecture to be discussed is commonly referred as a

charge-coupled device which uses the field-induced photo-detector as the

pixel and the analog shift register to shift the information from the

pixel to the output terminal and is depicted by Combination B. Two

typical matrix structures are shown in Figure 2.5. These structures

permit very high density with pixel spacings of 20 to 30 pm not uncommon

[17]. Depending on the particular criteria employed, the performance of

these structures has ranged from adequate to excellent. As a result of

the very low output capacitance and the elimination of sequential sampl-

ing with multiplex switches, both the thermodynamic and the fixed-pattern

noise in the dark are exceptionally low. This, however, is offset by the

resulting non-uniformity that prevails under illumination. This non-

uniformity is a result of the variations in film thicknesses that occur




Figure 2.5 Readout organization of CCD matrix array.




I\\ \\\ \\


in fabricating the field-induced photo-detector added as well as those

non-uniformities that are always present in the bulk silicon. Since the

reflectivity as well as the absorption depends on the relative thicknesses

of several films, a compromise must be made between spectral response,

quantum efficiency, and the non-uniformity [34]. Normal process vari-

ations make reproduction of consistent parameters over a period of time

somewhat more difficult than for the simpler diffused diode structure.

This problem is further aggravated by both the complexity of the required

process and its developmental nature, i.e., most CCD processes are not

high volume production processes; therefore, they lack the stability of

a standard production process.

The third structure to be discussed, shown as C in the figure, com-

bines the field-induced photo-detector with the digital shift register

in an effort to obtain higher density with an existing technology. This

structure is employed in charge injection array as shown in Figure 2.6.

As initially conceived, this structure exhibited excessive uncontrolled

blooming, less sensitivity than the photodiode, spectral variations, ex-

cessive non-uniformity, fixed patterns in the dark resulting from digital

sampling, and an extremely large output capacitance. Most of these dif-

ficulties are now under control; however, the technology is no longer

standard requiring an exotic metal/silicon gate MOS process on an ex-

pitaxial substance [4-6,35]. Furthermore, a double sampling technique

must be used to process out the fixed-pattern noise resulting from the

sequential sampling of multiplex switches and the thermodynamic noise

associated with resetting the output capacitance. As a result of em-

ploying this more complicated signal processing technique, the inherent

forms of signal contamination are eliminated, and good low level perform-

ance is obtained.






Figure 2.6

Cross-section of X-Y addressable sensing
cell of a charge injection array showing
location of stored charge under (a)
Integration, (b) Readout enable, (c)
Injection conditions.


The final structure to be assembled from the set of building blocks

is shown in the figure as D. This structure uses photodiodes with all

their inherent advantages, i.e., spectral purity, high-external quantum

efficiency, combined with an analog shift register for readout. This

combination possesses all the advantages of the photodiode detector with

those of the analog shift register readout. In the following section we

will describe the practical realization of array employing this architec-

ture. For lack of a more descriptive acronym, let us refer to this

architecture as the optimum solid-state image sensor.

2.3 Device Structure to Realize the Optimum Architecture

Solid-state image sensors can be divided into two groups: linear

image sensors and area image sensors. Linear sensors consist of a single

row of photosensitive elements and thus can be used to monitor a one-

dimensional variable. In order to obtain a two-dimensional picture from

a line sensor, the other dimension has to be scanned mechanically. For

high speed scanning of a two-dimensional picture such as standard broad-

cast television, an electronically scanned area array which contains rows

and columns of photosensitive elements must be used. In the present

study, only a 100 by 100 area array image sensor will be fabricated and

investigated, since, in principle, the linear array is a simplified form

of a matrix array. Any results obtained from this study then will also

be applicable to the linear image sensor.


2.3.1 Device Structure

The 100 x 100 diode matrix array to be fabricated and studied con-

sists of six functional elements as shown in the schematic diagram of

Figure 2.7. These elements are:

(1) A 100 x 100 diode array matrix, schematically indicated by the

columns and rows of individual photodiodes. The diodes in each column

are connected one at a time through multiplex switches to a video line

which is common to all the diodes in that column. Parallel connection

of the multiplex switches simultaneously selects one diode from each

column. The diodes are operated in the charge storage mode [1]. When

a diode is selected by the multiplex switch, the potential of the diode

will be reset to a value of (V -V ), where V and V represent the
clock high voltage and threshold voltage of the multiplex switch, re-

spectively. The signal charge removed from the selected diode will be

transferred into an analog shift register through the common video line

for readout. After the multiplex switch is turned off, the diode starts

to integrate the photon-generated charge and its potential decays. The

total integration time of each diode is the time between two consecutive

readouts of the same diode. Figure 2.8 shows the potential diagram of

a diode before and after selection by the multiplex switch. This unique

structure makes possible a matrix array of photodiodes, each having only

a single multiplex switch, which provides frame storage. Furthermore,

the output capacitance is a single line and not the total number of pixels.

(2) A two-phase (2 0) dynamic shift register which controls the

multiplex switches. It turns on each row of diodes in sequence and

dumps the corresponding signal charge into the appropriate analog

shift register through each common video line, thus loading a complete


Figure 2.7 Schematic diagram of the 100 x 100 photodiode
charge-transfer array.








Figure 2.8 Potential diagram of a diode before and
after being selected.


line of information at one time. The dynamic shift register is driven

by a two-phase clock denoted by 0Y and 0Y2 in Figure 2.7. It can be

self-loaded for sequencing or controlled by an external start pulse.

These functions are performed by the "NOR" circuit. Tied to each output

of the shift register (except for the 100th position) are inputs to the

"NOR" circuit which control the loading of the shift register. When

there is an output from any of the 99 output positions, the "NOR" cir-

cuit keeps the shift register from loading. Once the bit occupies the

last position, the "NOR" circuit's output goes high and another bit is

loaded into the shift register. Note that YSTART is also connected to

the "NOR" gate. It can be used to inhibit the register from loading by

pulling YSTART to a high potential.

(3) Two tetrode gate bucket-brigade shift registers [26,27] with

a gated charge-integrator output. As shown in Figure 2.7, there are two

bucket-brigade analog shift registers located on either side of the de-

vice. These are the odd and even transport registers which accept the

pixel information in parallel from their respective odd and even video

diode columns, and shift the pixel information sequentially to the out-

put amplifier. Each shift register is driven by a two-phase clock

denoted by 0X1', X2 in Figure 2.7, and is also provided with a "fat zero"

input port to improve the transfer efficiency as well as to check the

performance of the register. The outputs from both shift registers are

multiplexed off-chip to obtain one line of combined video information.

The advantages of this multiplexing approach are manifold. It increases

the density of the array, especially for the linear array in which the

center-to-center distance of the sensing diodes is limited by the bit

length of the analog shift register; it increases the pixel rate to two


times the transport clock frequency, and generates a full-wave sample-

and-hold output; it also halves the number of charge transfers. This is

very important in realizing long arrays when the total amount of charge

loss and transfer noise limits the performance of the device.

As will be discussed in Chapter 3, the bucket-brigade device offers

certain advantages over the charge-coupled device, such as greater com-

patibility with standard MOS technology and ease of interfacing with

the peripheral circuitry. However, the bucket-brigade shift register

has received much less attention than the charge-coupled device. In an

attempt to remedy this, the BBD shift register instead of the CCD regis-

ter is discussed in this study. It is hoped that a better understanding

of the performance limitations of the BBD shift register can be obtained,

and a design formulation can be established.

(4) A video line reset switch LR, a transfer switch LT and a buffer

gate Vbuff. The reset switch LR provides a reference bias for all the
video lines while all the sensor diodes are integrating signal charges.

All the charges collected on stray capacitances along the video lines

and all the excess signal charges leaked from the sensor diodes are

drained into the sink voltage VDD through operation of the LR gate.

Therefore, LR functions as an anti-blooming and anti-crosstalk gate.

Prior to the moment when the dynamic register is to select another row

of diodes, the LR gate is turned off and the transfer gate is turned on

to the same reference level set by LR. This makes conditions ready for

the signal charge from the next row to be transferred into the BBD re-

gisters. The LR and LT control clocks are complements of one another.

Note also that, just prior to transfer, the BBD is empty of signal

charges, it contains only fat-zero reference charges so that the new


transfer is unaffected by prior data.

Ideally when the signal charge is transferred from the common video

line into the BBD shift register, the transfer gate LT should be turned

on to the same reference level set by LR. However, due to normal process

parameter variations at device fabrication, such as surface-state density,

gate-oxide thickness, and substrate concentration, there will be a thres-

hold voltage variation between transistors even though they are very close

together on the same integrated-circuit chip. This threshold voltage

variation will cause two problems in the operation of the device. Firstly,

with different threshold voltages, the level set by the LR and LT switches

will be different, even though they have the same gate voltage. If the

reference potential level set by the LR switch is higher than that of LT,

which corresponds to VTLR TLR TLT TLR TLT
voltages of the LR and LT switches respectively, then some of the signal

charge will be drained into the VDD sink and cause nonlinearity in the

optical-to-electrical transfer characteristics. This is illustrated in

Figure 2.9. In order to avoid this possible loss of signal charge, the

voltage applied to the LR switch should be lower than that of LT. The

effect of these different gate potentials on LR and LT results in adding

a fixed amount of charge Qf into the video signal at high light levels,


Qf = [(VLR VLT) (VTLR VLT) C (2.1)

= (AVG -AVT) Cs

VLR and VLT are the gate potentials of the LR and LT gates respectively,

and C is the capacitance of the video line. To prevent this fixed








Figure 2.9

Loss of signal charge due to threshold voltage difference of LT
and LR gates, VT > VTLR


charge Qf from saturating the analog shift register, it must be minimized

by either minimizing AVG or C .

The second problem caused by the threshold variation is the intro-

duction of fixed-pattern noise due to a different AVT for each video line.

As can be seen from equation (2.2), with a different AVT for each video

line, there will be a different Qf, which results in a fixed-pattern

noise on the output signal.

To minimize both the Qf and the fixed-pattern noise, a buffer gate

Vbuff is introduced in front of the LR and LT switches. This buffer

gate is biased at a DC potential below the LR and LT "high" potential.

The function of this buffer gate is to isolate the video line capacitance

C from being affected by the AVG and AVT shown in equation (2.2), and to
s G
minimize Qf as well as the fixed-pattern noise. Its effect is very simi-

lar to that of the tetrode gate in the BBD shift register to be discussed

in the following chapter. With the introduction of this buffer gate,

equation (2.2) is revised to

Qf = (AVG AVT) C (2.3)

where C. is the junction capacitance of the N diffusion between the LR

and LT switches. This C. is much smaller than C and results in a great
3 s
reduction of Qf and fixed-pattern noise.

(5) Interlacing switches denoted as LO and LE gates. These gates

allow the device to operate in an interlacing mode when driven by a set

of two-phase clocks running at the field rate. For the non-interlacing

mode, these gates are tied to a fixed voltage, and the rows are accessed

sequentially, with each odd line followed by an even line. For the


interlacing mode, odd rows are first all accessed to form an odd field,

followed by even rows to form an even field.

(6) Frame reset FR. This switch provides an access to the multi-

plex switches of all the diodes in the matrix and allows the entire

frame to be reset instantaneously. Since the diodes in each line are

automatically reset when the line is accessed, the frame reset switch

is normally not used and is held low. However, when a particular ex-

posure is desired, this control may be used to clear the diodes to start

a fresh integration cycle by taking FR terminal to VDD. When this mode

is used, a shutter or pulsed light input is required because the diodes

are sequentially accessed and will thus differ in exposure time if light

input is continued during the readout sequence.

2.3.2 Device Operation

Figure 2.10 shows the timing diagram for the array when operated in

the non-interlace mode. It consists of three sets of complementary

clocks for the dynamic shift register, the BBD analog register, and the

line reset and transfer gates. The rising edge of the LT pulse should

lead the rising (or falling) edge of the 0 clock by approximately 30 ns

or more to insure that no useful signal charge is drained into VDD. The

width of the LT pulse should be minimized to the time required for the

complete transfer of charge into the BBD register. During the transfer

gate "ON" time, the charge collected at the stray capacitance along the

video line and the excess signal charge leaked from other sensor diodes

not selected also go into the BBD shift register, with the possibility

of causing interline crosstalk and blooming. The theoretical considera-

tions of the anti-blooming mechanism, speed limitations of the charge

Y Y2 I ----
X2=^X1 Oxi IJJu Lfj' fnn

LT=i-R n n n [R

Figure 2.10 Timing diagram for continuous-scan mode.


transfer into the BBD register, as well as ways to speed up the charge

transfer process will be discussed in detail in Chapter 4.

During the time when the signal charge is being transferred into

the BBD register, the clock driving the register must stop with the clock

at high potential on the buckets receiving charge from the video line.

This will cause a deep potential well for the signal charge to flow into.

As evident from Figures 2.7 and 2.10, the buckets receiving charge for

both the odd and even transport registers are driven by 0X2, and the

charge transfer takes place simultaneously for both registers during the

time 0X2 is held high. However, on the readout, the odd BBD register

produces the first pixel, since it reads out on the first low-going 0X2

clock just after the transfer period. The second pixel is produced by

the even BBD register; and since this pixel must transfer through an

extra half-stage which is controlled by the 0 X clock, this even pixel

is produced when 0X1 goes low. This provides an easily multiplexed

signal by means of a simple external adder amplifier. The output charge

integrators of the shift registers are connected as a source follower

with an external load resistor tied between the video output terminal

and ground. The reset switch of the charge integrator VR1 and VR2 are

connected to the appropriate clocks driving the shift register to remove

the signal charges after they have been sensed. Because there are fifty

buckets of signal in each transport register, it requires at least 50

clocks to transfer all the signal charge into the output amplifier as

shown in Figure 2.10.

The timing diagram for the interlace mode is shown in Figure 2.11.

It generally is somewhat similar to that for the non-interlace mode;

however, the dynamic shift register clock 0 must run at twice the

vY1, --- ------ Y2- -- -}_
-- -- 1-----g
TRANSFER, LT --l ------ -- f __ -
LINE -- "---'--- --| --- --I_--
Y i YI i.

Figure 2.11 Timing diagram for interlace mode.


relative former rate, while the interlace gates LO, LE confine the row

selection to alternate lines, odd or even as appropriate for the field.

Thus, there is no change either in integration period or in overall

frame rate; the picture is merely assembled in two interlaced fields

instead of one sequential scan. Slight changes are required in the LT

and LR clocks to accommodate the new pattern.



3.1 Introduction

The basic structure of the bucket-brigade device (BBD) is shown in

Figure 3.1. This device in its integrated form was invented by Sangster

[21,22] in 1968. There was much interest [23-25] in this device since

it offered the first glimpse of a practical way of implementing an analog

delay. However, the initial device had many shortcomings, with the major

one being very poor transfer efficiency. Potential variations during the

charge-transfer period introduced excessive channel-length and barrier-

height modulation, and consequent transfer inefficiency. As a result,

the device was limited to a small number of stages and low-frequency


The first major advance made in improving the transfer efficiency

was also made by Sangster and his co-workers [26,27]. It came from the

introduction of an isolation or tetrode structure, with a DC biased

gate, separating each clocked element from its neighbor, as in Figure

3.2. Devices fabricated employing this tetrode structure were found to

perform reasonably well, but transfer efficiencies were still less than

one could wish; furthermore, stability was erratic and the devices were

sensitive to clock shapes, particularly the transition edges. Before

these problems could be solved, charge-coupled devices (CCD) [39] were





Figure 3.1 Basic bucket-brigade structure.



Figure 3.2 Improved bucket-brigade structure with tetrode


introduced which showed promise of improved transfer efficiency, higher

clocking frequencies and higher density; therefore, most of the work

switched from bucket-brigade devices to charge-coupled devices. The

charge-coupled device appeared to be a very simple structure, requiring

only simple processing. However, despite the theoretical improvement,

it produced devices with not much better performance than the bucket-

brigade. It took five years and a tremendous amount of effort to develop

the understanding and technology to the point which allowed the advantages

of CCD to be truly realized.

With the development of CCD and modern MOS technology, such as

multiple-layer silicon gates to increase the density, self-aligned struc-

tures to reduce the parasitic capacitance, and threshold voltage control

by selective ion implantation to minimize channel-length and barrier

modulation, it is now possible without any difficulty to fabricate a
bucket-brigade device with transfer inefficiency less than 104 and

operating frequency higher than 5 MHz [19,33]. The bucket-brigade de-

vice possesses certain advantages over the charge-coupled device, which

makes it very attractive in some signal processing and image sensing

applications. The most important advantage of the bucket-brigade device

is the simplicity [33] and flexibility [40] of tapping the signal along

the shift register. This is very desirable in correlator and transversal

filter applications, as well as in interfacing with peripheral circuitry.

Another advantage of the bucket-brigade device is its compatibility with

existing MOS processes; as a result, a wealth of circuitry used in making

digital memories and microprocessors can be integrated on the same chip.

In this chapter, the operation of the bucket-brigade device will be

presented, and its performance limitations will be discussed. Analytical


equations will be formulated to analyze the transfer efficiency quantita-

tively, which will allow one to see the effects of each device parameter

on its performance.

3.2 Device Structure and Operation

3.2.1 Device Structure

Figure 3.3a shows the integrated circuit version of an N-channel

IGFET bucket-brigade shift register. It can be fabricated using a stan-

dard two-layer polysilicon gate process. The substrate is p-type material

and the transfer channel is confined by channel-stop ion implantation and

field oxide. After the gate oxide is grown, the first poly layer is

deposited and defined to form the FET switch. The channel region under

the FET gate can be selectively implanted before the gate deposition to

increase the effective substrate concentration for minimization of

channel-length and barrier-height modulation. The oxide between the

switches is then etched away. An N island is then formed between the

switches either by a light diffusion or by ion implantation. A second

oxidation step regrows the gate oxide on top of the N island as well

as the insulation oxide on the first poly. A second layer of poly is

then deposited and defined on top of the N island to form the capacitor.

Figure 3.3b shows the equivalent circuit. C represents the gate capaci-

tance between the N island and the second poly. C. represents the

junction capacitance of the N island to the p-substrate.

Figure 3.3 (a) Integrated-circuit version of an N-channel IGFET
bucket-brigade shift register.

(b) Equivalent circuit and two output sensing schemes.

02 01

2nd Poly


N-^ '1st Poly


1 (2 #1 02 VOG r VDD
S---- "---1
Ci C C C
NODE I/. 10C -L- CJ DD B
NODE I/j i Ci() R
A -



3.2.2 Device Operation

The bucket-brigade device can be operated by either a two-phase

complementary, or non-overlapping clock. For simplicity, a two-phase

complementary clock changing from OV to VG will be used to describe the

charge transfer from stage to stage. To begin, it is assumed that sev-

eral cycles of the clock voltage have been applied. Referring to Figure

3.4, at t = tl when the clock transition has just finished, the 01 switch

will be turned off while the 02 switch will be turned on. Node B will

be bootstrapped by the 02 clock to a most positive reference potential

of V and become the drain of the 02 switch. Node A will be lowered to
c 2
a potential of V by the capacitive coupling of the 01 clock. The mag-

nitude of V will depend upon the amount of the signal charge. Node A
now becomes the source of the 02 switch and the signal electrons will

flow through the 02 channel into the drain node. As a result, the source

potential rises and the drain potential falls. Electron flow continues

until the source potential rises to (VG VT) where VG is the most pos-

itive voltage of the 02 clock and VT is the threshold voltage of the

IGFET devices. At this point, the potential of the source is no longer

negative enough to inject electrons into the surface inversion layer,

and charge transfer ceases. The drain will maintain a potential of

[Vc Q /(C + C.)] where Q is the signal charge. This is depicted in

Figure 3.4 as t = t2.

At t = t3, the potentials of the clock lines are now reversed, and

the sources and drains reverse their roles. The new potentials differ
from the old ones by (VG x + The factor (C + C) represents the
voltage division of the clock voltage by the two series capacitances.

Therefore, the reference voltage V can be expressed as

Figure 3.4 Operation of BBD shift register:

(a) Equivalent circuit of one-and-
one-half-stage shift register.

(b) Clocks to drive the shift register.

(c) Potential of each node at different
time cycles.


I -i- i c-i~



S! 1 Iov
i I I I

tl t2

t3 t4


C+Cj C

t = tj

t =t2

t= t3

t = t4



-(Vc -O
-Vc- c



C (3.1)
V =VG VT + VG C + C.

= 2VG VT (if C >> C.) (3.2)
rG T j

The potential V at the source when the clock transition has just finished

(t = t1 or t3) can be approximated by

s c C + C. VG x C +
J 3
= V VT (if C >> C) (3.4)

The charge that was previously transferred into a drain now finds itself

in another source, and so it again transfers one more stage toward the

output. If the input source island potential is held significantly posi-

tive (higher than "VG V "), there will be no new charge injected at the

input, and any internal charge is swept toward the output. When the

internal charge has all been removed, the N island potentials oscillate

between (VG VT) (source potential) and (2VG VT) (drain potential).

In the above analysis, the overlap capacitance of the IGFET gate to

the source island is assumed negligible. The formation of the N island

by light diffusion or ion implantation is intended to minimize this para-

sitic capacitance.

The largest quantity of charge that can be transferred in the chan-

nel is referred to as the charge handling capacity of the shift register.

The charge handling capacity can be obtained from equation (3.4) by

letting V = 0 which leads to

Qs (Max) = C (VG VT) (3.5)

A larger charge would make V negative and forward bias the N island

and p-substrate junction and inject the signal charge into the substrate.


3.2.3 Input and Output Structures

As shown in Figure 3.3b, the input structure consists of an N source

island which is the analog signal input terminal, a FET sampling switch

which is driven by one phase of the shift register clocks, and an input

capacitor C When the 02 switches are off and the 01 switches are on,

node I will be charged to the input potential V.. When the voltages on

the 01 and 02 switches are reversed, the charge at the input capacitance

will be transferred into the shift register, and node I will be discharged

to (VG VT) by the 02 switch. The charge injected into the shift reg-

ister is therefore

Qs = (VG VT Vi) C (3.6)

The signal charge in the shift register channel can be detected by atta-

ching the gate of a source follower to the channel, as depicted by output

A in Figure 3.3b, or by using a gated charge integrator [36] at the end

of the shift register as depicted by output B in Figure 3.3b. The dis-

advantage of the output A structure is that any noise on the driving

clock will appear on the output signal. However, this means of detection

is non-destructive which is an advantage over the charge integrator.

3.3 Performance Limitations

The most important aspect of a charge transfer device is its ability

to maintain the integrity of the charge packets as they are transferred

along the device. In the preceding section, it was assumed that the

charge transfer at each stage is perfect. However, in actual operation,

the transfer of charge from one stage to the next is neither instantaneous


nor complete. This puts some limitations on the speed of operation of

the bucket-brigade devices and the total number of transfers that can

be executed without objectional signal degradation. Incomplete transfer

means that in each transfer a small amount of signal charge is left be-

hind. This effect is cumulative and after many transfers the charge

packets become significantly smeared together. The parameter used to

describe the performance of the bucket-brigade device is called transfer

inefficiency c. This is defined as the fraction of signal charge left

behind after each transfer. This parameter multiplied by the number of

transfers in a device is the transfer inefficiency product N s, which
determines the overall transfer performance of the whole device.

The mechanisms that introduce the transfer inefficiency can be

classified according to the operating frequency of the bucket-brigade

device. At high frequencies, it is the intrinsic transfer rate of the

FET switch that limits the transfer efficiency. If not enough time is

allowed for the charge to transfer through the switch before the switch

is turned off, some of the signal charge will be trapped at the previous

stage. As will be discussed later, the transfer inefficiency is propor-

tional to the square of the clock frequency when the device is operated

in this frequency range. At low frequencies, there is enough time for

the charge to transfer through the FET switch, and therefore, the source

potential will be discharged to (VG VT) as discussed in the previous

section. However, the discharge current is not completely cut off due

to thermal diffusion of the charge carriers. There is still some leakage

current passing through the FET switch, which is referred to as the sub-

threshold leakage current, and the FET device is referred to as being

operated in the subthreshold or weak inversion region [41-43]. This


subthreshold leakage current will be affected by the channel-length

modulation [30,44] of the FET switch due to the different drain potential

accompanying the various amounts of signal charge. Moreover, the thresh-

old voltage of the FET switch is a function of the drain voltage due to

the ion-sharing effect at the drain junction [28,29,45]. This effect is

usually referred to as barrier-height modulation. As a result of these

channel-length and barrier-height modulations, there is a frequency-

independent component of transfer inefficiency which dominates at low


While the intrinsic transfer rate and the channel-length and barrier-

height modulations contribute to the transfer inefficiency and provide the

major limitations to shift register performance, there are other perform-

ance limiting effects which should be mentioned. Of these, perhaps the

most important one is that of interface states. With present day tech-

nology, interface-state densities are so small that they are not normally

considered to affect significantly IGFET operation. However, in the case

of the bucket-brigade shift register, we are talking about transfer in-

efficiency in the order of 10-4; therefore even a small density of interface

states can be important.

Only the interface states in the channel region of the IGFET can

affect bucket-brigade operation. Their effects are two-fold: one is

contributing generation current, and the other is trapping carriers dur-

ing transfer and emitting them at some later time. Interface-state

generation current, in combination with bulk generation current associated

with the N island, will add to the signal charge in the storage capaci-

tance. Given enough time, these generation currents will add enough

charge to overdrive the register. As a consequence, a low frequency or

minimum refresh time limitation will be introduced by the leakage current.


The trapping of carriers by interface states in the IGFET channel

and subsequent emission at a later time will result in charge left behind,

and will effectively introduce another contribution to the transfer in-

efficiency. This transfer inefficiency can be minimized by using a

certain amount of circulating charge, or "fat zero" in the device. The

effect of the fat zero is to keep the interface states under the gates

filled so that these states will not trap signal charge. As a result,

each charge packet will receive about the same number of electrons from

the preceding packets as it loses to the trailing packets. As will be

discussed later, this circulating charge will also speed up the intrinsic

transfer rate considerably, and improve the high-frequency performance of

the device.

Another limitation to bucket-brigade operation that needs to be men-

tioned is the dynamic drain conductance effect. It is well known that

drain potential modifies the current flow and gives rise to a non zero

output conductance in the saturation region of the IGFET characteristic

[30,44]. This effect is also caused by channel-length modulation as

mentioned before. This dynamic drain conductance effect will introduce

another component of transfer inefficiency in the high frequency opera-

tion range of the bucket-brigade device. However, this transfer

inefficiency component can be reduced to a negligible level by using

the tetrode gate structure.

3.4 Tetrode Structure Bucket-Brigade Device

The most important improvement in the development of the bucket-

brigade device, which makes the actual application of this device

possible, is the introduction of the tetrode gate structure [26,27].


The tetrode structure improves the performance of the device by reducing

the effects of channel-length and barrier-height modulation and meanwhile

does not increase the complexity of the fabrication process. There are

some other device structures which can improve the performance, such as

stepped electrode [46] and junction FET approaches [47]. However, these

approaches require special fabrication processes which are not compatible

with standard MOS processes. As a consequence, most of the modern bucket-

brigade devices use the tetrode structure.

Figure 3.5a shows the actual device structure, and Figure 3.5e shows

the equivalent circuit. C represents the junction capacitance of the

N island between the FET switch and tetrode gate. The function of the

tetrode gate is to isolate the storage capacitance C from being affected

by any channel-length and barrier-height modulations on the transfer

gates. Therefore, for optimum operation, the tetrode gate should be

biased near the higher clock driver voltage VG. In Figure 3.5b, the

bias level of the tetrode gate is shown at its optimum level which is

slightly below the phase driver voltage. The solid lines indicate the

surface potential without any introduced signal charge for the condition

of 02 high and 01 low. The shaded region is the bias charge always pre-

sent in the N regions. The double crosshatching indicates the introduction

of a half well of signal charge and the resultant barrier modulation. The

arrow points out the loss of charge from the signal packet due to the

barrier modulation. Since the capacitance of C is very small, this

loss is small. In Figure 3.5c, the tetrode gate is shown at a higher

voltage than that applied to the phase drivers. As seen by the double

crosshatching which extends across the tetrode gate, the loss due to the

barrier modulation is much larger since the capacitance which is affected

Figure 3.5 Tetrode bucket-brigade device:

(a) Actual device structure in integrated-circuit

(b) Tetrode gate correctly biased. The charge
loss due to barrier-height modulation is

(c) Tetrode gate biased too high, no effect in
suppressing the barrier-height modulation.

(d) Tetrode gate biased too low, reducing the
speed and charge handling capacity.

(e) Equivalent circuit.






VBB 01







by the modulation is much larger. The tetrode gate has no effect in

suppressing the barrier modulation with this bias level. In Figure 3.5d,

the tetrode gate is much lower than the phase driver voltage. This re-

sults in low signal-handling capacity and reduced operating speed.

When the tetrode gate bias VBB is lower than the clock voltage VG,

the charge-handling capacity becomes

Qs (Max) = C(VBB VT) (3.7)

with VBB too low, the charge-handling capacity is greatly reduced. Since

the capacitance C is very small, the node voltage V will quickly dis-

charge to a threshold below the gate voltage of 02. The limiting process

for speed of the transfer is the discharge of the large storage capaci-

tance C through the tetrode transistor Trt. Lowering of VBB bias will

effectively reduce the transconductance of the tetrode transistor and

consequently decrease the operating speed. It is also apparent that the

tetrode transistor will not suffer any barrier-height and channel-length

modulation, since the potential of V will never be much different from

a threshold below the 02 voltage when 02 clock is high. Therefore, the

high-frequency component of transfer inefficiency due to dynamic drain

conductance is negligible when the tetrode structure is used.

3.5 Derivation of Transfer Inefficiency Model

In this section, the three mechanisms, namely intrinsic transfer

rate, channel-length modulation, and barrier-height modulation; which

limit the performance of the bucket-brigade device, will be discussed

in detail. Analytical equations will be formulated to allow one to


examine the effects of each device parameter on its performance, and,

therefore, an optimum device can be designed for each specific applica-

tion. In the following derivation, emphasis will be on the physical

process involved as well as the simplification of the model, and, there-

fore, any model requiring two-dimensional numerical analysis will be


3.5.1 Intrinsic Transfer Rate

The intrinsic transfer rate of the basic bucket-brigade device will

be first derived, and the result will be then extended to the tetrode gate

structure. In Figure 3.6, a single IGFET is shown, which will serve as

the basis for the modeling of charge transfer efficiency in the bucket-

brigade device [23-25].

This FET is merely one-half of one stage of a BBD shift register.

The junction capacitance C. between the N island and the p-substrate

has been neglected. This makes the storage capacitance C linear which

is not completely true, but is a good enough approximation for most of

the practical devices.

In Section 3.2.2, it was pointed out that during charge transfer,

the source potential V rises to (VG VT) as the excess electronic charge

in the source transfer to the drain. At the same time, the rate of charge

transfer must go to near zero. However, this charge transfer process re-

quires a certain amount of time. If the bucket-brigade is to operate at

a clock frequency of f then the maximum time T allocated for each charge

transfer is

S= (3.8)


Vs -

Figure 3.6


C =

FET model for charge transfer efficiency
behavior of a bucket-brigade device.


If T is not long enough to allow the charge transfer process to complete,

there will be always a finite quantity of charge left behind in the source

due to this intrinsic transfer rate limitation.

As mentioned in Section 3.2.2, when the gate voltage is VG, the

drain voltage VD will be equal to (2VG VT) when there is no signal

charge. The drain voltage will decrease as the signal charge is trans-

ferred into the drain node. The minimum drain voltage occurs when there

is a saturation charge in the channel. This drain voltage equals

VD (in) = 2VG -T C

= 2VG VT -G V) (3.9)

= VG

From equation (3.9), it is clear that the IGFET is always operated in

the saturation region.

To derive the excess charge Q remaining in the source after time T,

we use the usual saturated current-voltage relation for the IGFET:

I = (V V V)2 (3.10)


n C W
=n ox (3.11)

where n = electronic mobility in the inversion layer
C = channel gate-oxide capacitance per cm
W = channel width

L = channel length


During the time the gate voltage is VG, the excess charge in the source

is defined as

Q(t) = C[Vs(t) (VG VT)] (3.12)

The source-to-drain current is

I= dQ(t) (3.13)

combining equations (3.10), (3.12), and (3.13) gives

dQ(t) Q(t)2 (3.14
dt 2 CC I

integrating (3.14) leads to

Q(t) = Q 1+ 2j (3.15)

where Qo is the initial charge in the source. Combining (3.15) with

(3.8) gives

Q(T) = Q 1+ 2 (3.16)
4f C

The transfer inefficiency e is defined by

( dQ(T) (3.17)

Differentiating equation (3.16) leads to
E(T) = f1+ 4 C2 (3.18)
4f C 2
It is convenient to perform a Taylor expansion in f of (3.18),

16C f 2
(T) = (3.19)


From (3.19) it is now obvious that the transfer inefficiency due to the

intrinsic transfer rate is not only proportional to the square of the

clock frequency, but also is inversely proportional to the square of the

signal charge Qo. As the signal charge decreases, the transfer ineffi-

ciency increases sharply. A circulating charge Qc or "fat zero" is

therefore needed not only to reduce the interface-state trapping, but

also to improve the transfer inefficiency due to this transfer rate


The physical meaning of the speeding up of the apparent transfer

rate by the circulating charge can be understood by examining equation

(3.16), which has been plotted in Figure 3.7 for the following represen-

tative values:

B = 3 x 10-5 A/V2

Qo = 0.8 and 2.4 picocoulomb (pc) (3.20)

C = 0.44 pF

Figure 3.7 shows that for a clock frequency of 0.5 MHz approximately

0.012 pc or 0.5% of charge remains in the source for Qo = 2.4 pc. This

0.5% transfer inefficiency is intolerable for any practical bucket-brigade

device. However, the charge remaining in the source for Qo = 0.8 pc is

very near to the value for the large initial charge. If this 0.8 pc is

the circulating charge Qc, and any change beyond this amount represents

the signal information, then the actual signal charge trapped at each

transfer will be the difference between the charges left behind for both

of the initial charges of 0.8 and 2.4 pc. Hence, the apparent transfer

efficiency is greatly improved. An accurate calculation of (3.16) using


E 0.1-


0.1 1.0 10 100
fc (MHz)

Figure 3.7 Charge left behind as a function of clock frequency
for two different initial charges, Q as described
by equation (3.16).


the condition of (3.20) for f = 0.5 MHz gives the signal charge left

behind of 0.0001 pc, which corresponds to 0.006% of the signal charge

which is now (2.4 0.8) = 1.6 pc.

Equation (3.19) now can be.modified to accommodate the introduction

of the circulating charge and actual transfer efficiency measurement

scheme which will be discussed in a later chapter. Equation (3.16) can

be expanded in a binominal series valid for most cases of practical in-

terest to get

2 24
4f C 16f C
Q(T) for BQ >> 4f C (3.21)
S2 Q c

With a circulating charge of Qc and a charge packet of Qo, the actual

signal charge left behind will be

16f 2C /
AQ 2 Qc (3.22)

The average transfer inefficiency is then

AQ 16f 2C
(T) = = c (3.23)
o Qc 2 QoQc

Comparing (3.23) with (3.19), it can be seen that (3.19) is the small

signal limit [24] of (3.23), which represents [AQ /(Q Q )] (Q -9 Q ).

From (3.23), it is also clear that the transfer inefficiency can be mini-

mized when both Qo and Qc are made as large as possible and that through

the clock frequency dependence of C(T) the intrinsic transfer rate will

provide an upper limitation to the operation of the bucket-brigade device.

To extend the result of the transfer inefficiency derived above for

the tetrode gate bucket-brigade structure, we use the model shown in

Figure 3.8, which represents one half stage of the tetrode BBD. As men-

tioned in Section 3.4, the junction capacitance C is much smaller than the



Tr t

-C y
_ I

Figure 3.8

FET model for charge transfer efficiency
behavior of a tetrode bucket-brigade device.



storage capacitance C, the limiting process for the speed of charge

transfer is the discharge of the large storage capacitance C through the

tetrode transistor Trt. This is because any small amount of charge ac-

cumulated in node y will lower V considerably and cause a sharp increase

of the current passing through the switch transistor T to discharge the

accumulated charge. Therefore, equation (3.23) has to be modified for

the tetrode BBD with the parameter B of the tetrode transistor Trt re-

placing that of the switch transistor T

In the derivation of equation (3.23), we assume that the switch

transistor Trs is always operated in the saturation region, which is al-

ways true as discussed previously. However, this is not exactly the case

for the tetrode Trt in the tetrode BBD. During and right after the clock

transition, the voltage at node y will be charged to a potential

V < (VBB VT), and then quickly discharged to near (VG VT). There-

fore, during the very early stage of the charge transfer process, the

tetrode transistor Trt is operated in the linear region instead of the

saturation region. However, a rigorous computer simulation using the

ASPEC transient program shows that with a capacitor ratio of C/C = 20-30,

and the same B parameter for both the switch transistor T and the te-

trode transistor Trt, the time that the tetrode transistor operated in

the linear region during the early stage of charge transfer process is

around 2-3% of the total charge transfer time. The total charge transfer

time here is defined as the time required for the transfer inefficiency

due to the charge transfer rate limitation to drop to the low frequency

limitation value due to channel-length and barrier-height modulation.

Therefore, the error introduced by assuming that the tetrode transistor

Trt is always operated in the saturation region is negligible.


3.5.2 Transfer Inefficiency Due to Subthreshold Leakage of the IGFETS

As discussed previously, at the end of a charge transfer the source

will rise to a potential of nearly (VG VT). However, due to thermal

diffusion of the charge carriers from the source region into the drain

region, the channel current of the IGFET does not suddenly drop to zero.

Rather, it diminishes exponentially with decreasing gate-to-source volt-

age. The effect of this subthreshold leakage current on the transfer

inefficiency of the BBD will be considered in this section.

Figure 3.9a shows the FET model to be used in the subthreshold leak-

age current analysis. Cs represents the capacitance at the source node.

In the basic BBD structure, this is the storage capacitance; however,in

the tetrode BBD, this is the junction capacitance of the N+ island between

the tetrode and switch gates which is depicted as C in Figure 3.8. CD

represents the capacitance at the drain node which is the storage capac-

itance for both the basic and tetrode structures. It is assumed that

enough time has elapsed to allow the charge at the source node to transfer

into the drain node and the source potential reaches (VG VT) as shown

in Figure 3.9b. Once this condition is reached,current enters the channel

barrier region only by diffusion.

The objective of this analysis will be to find the amount of charge

trapped on the left of the barrier at the end of the charge transfer

cycle. The amount of this charge Q1 will be found as a function of the

charge transferred, Qo. The charge transfer inefficiency due to this

subthreshold leakage current ED is then dQ1/dQo as before.

To find this relationship, consider Figure 3.9b. Assuming the

carrier concentration at the left edge of the barrier is no, then the

diffusion current across the barrier can be expressed [41] as

Figure 3.9 (a)

FET model for derivation of transfer
inefficiency due to subthreshold leakage

(b) Surface potential of an ideal FET with
no subthreshold leakage current. Also
shown are the trapped and transferred

(c) Actual surface potential and charge
transfer during the part of the cycle
devoted to subthreshold leakage current.



--Trs CD






(VG -VT)





S qDnoLBW exp (-V q/kT) (3.24)
st =L(VD) (3.2

/K e kT
L = s (3.25)
B 2

is the extrinsic Debye length

and q = electron charge

D = electron diffusion constant

NA = substrate concentration

k = Boltzmann's constant

T = temperature in degrees Kelvin

VDS = drain-to-source potential

K = dielectric constant of silicon
E = permitivity of free space
L(VD) = effective channel-length as a function of the
drain voltage due to channel-length modulation.

The equilibrium minority-carrier concentration n at the edge of

the source is a function of the surface potential at the source, and can

be expressed [41] as

exp[(b 1)U ] 1
n = 3 n. (3.26)
S [2(Usx + bUF 1)]2


U = source-to-substrate voltage normalized by kT/q
U = Zn the bulk Fermi potential normalized by kT/q
F n.
b = the band-bending parameter (b = 2 at strong
F inversion, b = 1 at weak inversion)


U = surface band-bending normalized by kT/q

n. = intrinsic carrier concentration of silicon.

If VDS >> kT/q which is the case in BBD operation, the term in the

brackets of equation (3.24) equals 1, and (3.24) reduces to

qDnoL W
I = (3.27)
st L(VD)

As the current diffuses over the barrier into the drain, the potential

energy level at the source node starts to drop below the (VG VT) level

as shown in Figure 3.9c. As a consequence, the carrier concentration at

the source edge also drops, as does also the diffusion current. From

equation (3.26), it can be seen that carrier concentration at the source

edge will decrease exponentially with reducing surface potential, there-


n (t) = n eVt)/kT (3.28)
o o


qDnoB -V(t)q/kT (3.29)
st L(VD)

The value of V gradually increases as current flows over the barrier ac-

cording to

dV(t) Ist(t) (3.30)
S= (3.30)
dt C

Eliminating Ist(t) from (3.29) and (3.30), we obtain an equation which

can be solved for V(t).

dV(t) qDnoLB -V(t)q/kT
edt (3.31)
dt L(VD s


Solving equation (3.31) with the initial condition V = 0 at t = 0, we


SkT q DnLBWt (3.32)
V(t) n 1 + kTL( c (3.32)
q kTL(VD) Cs

At the end of the charge transfer cycle, the charge trapped at the source

node is

kTC q Dn L
Q = -CV() = q An 1 + kTL (3.33)

s n B (3.34)
q kTL(VD)Cs

where T is defined by equation (3.8). The approximation of (3.34) from

(3.33) is always true when the BBD is operated in the low frequency

range. The minus sign in front of equation (3.33) indicates that in

reality the charge is depleted instead of trapped.

The transfer inefficiency is then obtained by taking the derivative

of Q1 with respect to the charge Qo transferred,

dQ1 dQ1 dL(VD)
E X (3.35)
dQo dL(VD) dQ

C kT 1 dL(VD)
s (3.36)
q L(VD) dQ

The transfer inefficiency in (3.36) depends only on how the channel length

is modulated by the charge Qo transferred into the drain node. The charge

Qo is related to the drain voltage VD by

V = 2V VT (3.37)


This gives

kT C dL(VD)
kT s 1 D
D q CD L(VD) dVD (38)

Thelast multiplier term in (3.38) represents the channel-length modula-

tion for different drain voltages.

As mentioned previously in this section, a circulating charge Qc is

always present in the channel, and the actual signal charge is (Qo Q )

The actual signal charge trapped at the source can be calculated from

(3.34) which leads to

C kT L(VD )
AQn (3.39)
sig q L(V D

L(V ) and L(V ) represent the effective channel lengths when a charge

packet of Q and Qe are respectively present at the drain node. The

transfer inefficiency then can be expressed by

AQ C kT L(VD )
= sig s n (3.40)
D Q 0- Qc q(Qo- Qc) L(V Dc
o c c D

To complete the calculation of transfer inefficiency, the multiplier

terms in (3.38) and (3.40) representing the channel-length modulation

have to be evaluated. The channel-length modulation is generally attrib-

uted to the spreading of the depletion region near the drain which

results in a reduction of the channel length. Ihantola [48], Reddi and

Sah [44] calculated the extent of this spreading by describing the elec-

tric field distribution using step p-n junction theory. However, it was

pointed out by Frohman-Bentchkowsky and Grove [30] that owing to the

presence of the gate electrode, the electric field in the drain depletion

region near the Si-Si02 interface is greatly increased. A simple physical

model was presented by them which takes into account this increase in the


electric field. Good agreement between the model and output conductance

measurements throughout a very wide range of device parameters was ob-

served; as a result, this model is widely adopted in many modern computer

circuit simulation programs.

Although this model is developed for the IGFET under strong inversion

to account for the dynamic drain conductance, it can be extended into the

weak inversion region with a slight modification of the definition of the

drain saturation voltage VDsat. According to conventional theory, an

IGFET device operates in the saturation region when the drain voltage is

increased to a value such that the inversion condition at the end of the

channel near the drain can no longer be maintained by the applied gate

voltage. The drain voltage at the onset of saturation is denoted by

VDst, and can be expressed in terms of device parameters and applied

gate voltage.

K qN [ / 2C 2(V V )
V =V V -F -20 + s 1 + ox G FB
Dsat G FB F C2 K e qN


VFB = "flat-band" voltage of the IGFET
0 = Fermi potential of the substrate.

Any further increase of drain voltage beyond this value is then pictured

to result in the formation of a depleted region of length Zdep between

drain and channel as shown in Figure 3.10. This is equivalent to assum-

ing that the voltage at the end of the channel which corresponds to the

edge of the depletion is VDsat. In weak inversion operation, there is


Cross-section of MOS transistor operating in saturation region.

Figure 3. 10


no drift component in the channel current; therefore, the variation of

surface potential along the channel is very small [42]. The current is

mainly from diffusion of minority carriers due to the concentration gra-

dient. Therefore, the end of the channel should be the point where the

minority-carrier concentration equals zero. For simplicity, we define

the end of the channel as the point where the semiconductor is intrinsic.

The potential at this point is denoted by V as distinguished from
conventional V By definition V can be expressed by
Dsat Dsat

V Ds = V V + s l l+ ox VG -VFB
Dsat G FB F 2 K e qN


Note that the only difference between (3.41) and (3.42) is the factor

"2" in front of the Fermi potential 0Fp

The extent of the depleted region depends on the difference between

the potential of the drain, VD, and that at the end of the channel,

VDt and on the average transverse electric field component near the
Si-Si02 interface, ET. Thus

V V '
VD Dsat
Ydep = E (3.43)

According to Frohman-Bentchkowsky and Grove's model [30], this average

transverse field is attributed to the superposition of three electric

fields as shown in Figure 3.11. E1 arises from acceptor ions within

the drain depletion layer, EX2 is the X-axis component of fringing field

E2 which arises from the drain-gate potential difference, and EX3 is the

X-axis component of fringing field E which arises from the gate to VDst

difference. Thus



Figure 3.11

The electric field distribution for MOS
device operation in saturation.


ET = E1 + EX2 + EX3 (3.44)

The field E1 can be obtained from the step junction approximation

E = / (V ) (3.45)
E1 2K e D Dsat

A rigorous calculation of the contributions of EX2 and EX3 requires a

solution of Poisson's equation in the depletion region near the Si-Si02

interface. However, they can be given by the approximations [30]

K (V V + V )
E a D FB (3.46)
X2 K t
s ox
K (V V V )
E G FB Dsat (3.47)
X3 K t
s ox

where K and t are the dielectric constant and thickness of the gate
o ox
oxide layer respectively, and a and B are the field-fringing factors

which represent the extent to which the normal oxide field fringes in

a transverse direction into the depleted region near the drain. Good

agreement between theory and experiment was obtained over a wide range

of device parameters and applied voltages for the values a = 0.2 and

S= 0.6.

Combining equations (3.43)-(3.47), we obtain

/ qN /K \ (V VG + VFB
Sdep = (V) V [) (V V^ + ) a V FB
D Dsat 2K D Dsat t
so s ox


+ (Ko (V V V -)(3.48)
(o (VG VFB Dsat1
+ V

In the limiting case of high substrate concentration, the first term in

the bracket of (3.48) will dominate, and the expression of Zdep reduces



2K E
idep = (V (3.49)
qNA (VD Dsa (349)

which corresponds to the results obtained by Ihantola [48] and by Reddi

and Sah [44]. The effective channel length now can be expressed as

L(VD) = 2X. idep (3.50)

where LM is channel length defined by the gate mask, and Xj represents

the lateral underdiffusion from the source and drain. Differentiating

(3.50) leads to

dL(VD) (/)(V VD t) + (K /K t )( a)(VG VF V
D D Dsat o s ox G FB Dsat
dV 1 92 kK1t-)(VD
dVD (-)(V V ) + (Ko/K t F2 + (2K/KKt (V Vst) F
K D Dsat o s ox o s ox D Dsat


where K = so (3.52)

F = a(V VG + V) + B(VG VB Vst) (3.53)

With equations (3.36), (3.40), (3.48) and (3.51), the transfer ineffi-

ciency ED due to the subthreshold current can be calculated. In Figure

3.12 the theoretical values of cD are plotted as a function of the

channel length L for different substrate concentrations NA.

3.5.3 Transfer Inefficiency Due to Barrier-Height Modulation

Another mechanism that affects the transfer inefficiency at low

frequencies is the barrier-height modulation due to variation of drain

voltage with different signal charges. To analyze this mechanism we

will not consider the effects of subthreshold leakage current which have

been treated in the previous subsection. In addition, we assume the

Cs =1,

r = 1.5im
tox = 0.11 m

=6 x 1014

1.7 x 1015

3 x 1016

51 I I I I




Figure 3.12

Theoretical transfer inefficiency due to subthreshold leakage current
as a function of channel length for different substrate concentrations.






frequency is so low that the surface potential on the left of the barrier

equals the potential of the barrier as shown in Figures 3.9a and 3.9b.

These assumptions simplify the calculation because the amount of un-

transferred charge is completely determined by the product of the barrier

potential and the capacitance of the region to the left of the barrier.

The objective then is to find the barrier potential as a function of

transferred charge. The transfer inefficiency can then be found from

dQ1 d(VG VT) dVT
S=-- = C = -C (3.54)
B dQ s dQ s dQ0

where Q1 is the untransferred charge at the end of transfer, Qo is the

transferred charge. C is the capacitance of the source node, and VT

is the threshold voltage of the switch transistor T
In conventional MOS theory, the threshold voltage of an IGFET is

simply obtained by applying the charge conservation principle to the

region bounded by the gate and bulk of the semiconductor and neglecting

any two-dimensional edge effects at the source and drain ends. This may

be written as [49]

S+ QF + N + B = 0 (3.55)

where Q is the charge on the gate, QF includes the fixed charge in the

Si02' QN is the charge due to the free carriers in the surface inversion

layer, and QB is the fixed charge due to the ionized impurities in the

depletion region. For an N-channel IGFET, equation (3.55) may be ex-

pressed in terms of voltages as [49]

VG = VFB + 0s (QB + QN)/Cox



where 0 is the surface potential with respect to the substrate. By
using the commonly used criterion for surface inversion, the expression

for the threshold voltage is [42,49]

VT = VFB + bF QB/Cox (3.57)

where 0F is the bulk Fermi potential and b is the band-bending parameter

which determines the degree of inversion. The effect of the bulk charge

QB in equation (3.57) is to increase the magnitude of the threshold volt-

age. However, due to the two-dimensional edge effect, the full effect

of QB on the threshold voltage is decreased when the channel length is

reduced and becomes comparable to the junction depth of the source and

drain. As the distance between the source and drain decreases, the in-

fluence of the source and drain on the electrostatic potential distribution

under the gate increases. In contrast to the conventional long-channel

theory, a large fraction of the field lines originating from the bulk

charge under the gate are terminated on the source and drain islands,

causing the threshold voltage to be lower than what is predicted by

equation (3.57). This ion-sharing effect near the ends of the channel

results in a dependence of threshold voltage on the channel length and

on the drain voltage [28,29,45].

To analyze the dependence of threshold voltage on the channel length

and drain voltage requires a two-dimensional numerical analysis of the

IGFET [50,51]. However, many one-dimensional models which take into

account the two-dimensional field distribution have been reported.

Cheney and Kotch [52] first modified the threshold voltage expression

for the case of a large substrate bias by including the effect of the

depth of the source and drain diffusion. This results in a correction


at high backgate bias. To include the short-channel effect for low back-

gate bias, Lee [45] refined the model of Cheney and Kotch, and after a

lengthy piecewise one-dimensional analysis, he obtained a very complicated

closed-form expression for the threshold voltage as a function of channel

length, drain voltage, and junction depth. By introducing two experimen-

tally determined weighting factors, his theory and experiments appear to

agree much better than that of Cheney and Kotch. Yau [28] used a simple

geometrical approximation in conjunction with a charge conservation analy-

sis to obtain a threshold voltage expression which has the advantage of

a simple form and, at the same time, retains the physical insight of the

original charge conservation approach. Although his theory is in ex-

cellent agreement with experiments, the expression is only applicable

for the case of zero drain-to-source voltage. To take into account the

effect of drain-to-source voltage, Taylor [29] modified Yau's model.

His theory was corroborated by experiments over a wide range of drain

and gate voltages. In the following discussion, a simple model which

is applicable to the operation of bucket-brigade devices will be pre-

sented. The approach taken is similar, in some respects, to the

derivations of Yau and Taylor.

To include the edge-effects of bulk charge QB in the expression of

VT, we assume a source and drain junction with a cylindrical edge of

radius, r., equal to the depth of the N islands as shown in Figure 3.13.

Directly under the middle of the gate, the width of the bulk space charge


W = VK(0 + V )


Figure 3.13

Model to calculate threshold voltage of
an MOS transistor.


where K is defined by equation (3.52). Without going through a two-

dimensional analysis, the field lines arising from the bulk charge can

be approximated as drawn in Figure 3.13. The field lines originating

from the fixed charge inside the trapezoidal region are terminated with-

in the effective channel length (L idep), whereas the field lines from

the fixed charge outside the trapezoidal region are terminated in the N

islands. Based on this geometrical approximation, the total bulk charge

inside the trapezoid is

QB(L kdep) = qN W L+ L de) (3.59)

(L + L dep) (3.60)
B A 2(L kdep)

where Q represents the average charge per unit area in the effective

channel length of (L dep), where Rdep is defined by equation (3.48).

The threshold voltage VT at weak inversion (b = 1) now can be ex-

pressed as

/2qN K e
VT = V + 0 + F x (VDsat + 0F) (3.61)
T FB F b C2 Dsat F

F (L + L dep) (3.62)
b 2(L kdep)

is the form factor for barrier modulation. In equation (3.61), the

source potential has been replaced by VD This is because at the end

of the charge transfer process, the subthreshold leakage current will de-

cay twoard zero, and the source potential will reach (VG VT) VDsat.

From Figure 3.13, the form factor can be calculated by straightfor-

ward geometrical analysis:


L = L L1 L2 2 dep

L = (r -W rj

L = (r2 2- 2 r. dep

r + YK(V + V
1 j+ Kbi Dsat

r2 = r. + K(Vbi + VD)

W = /K(V t + 0)
Dsat F







where Vbi is the build-in voltage of the N junction. Combining (3.62)-
(3.68) we obtain
(3.68) we obtain

F 1-
b L

L1 + L2
(L dep
2(L dep)


L1= r2 +

L2 [,
2 j

2r. /K(V + V ) + K(V .
j bi Dsat bi

- 0F] -rj

+ 2r. K(Vbi + V) + K(V + V Vs
3 bi D D bi Dsat


- F)]


- (rj + Rdep)

From equations (3.37), (3.54) and (3.61), the transfer inefficiency due

to barrier modulation eB now can be expressed as

C 2qNAK e V +
S = sA S 0 + -
B CD C 2 Dsat

x 1

+ F sN o
ox D+Fsat
ox Dsat F ^\



(L kdep)

d2 + dde
dV 2 dV
D (3.73)

2(L Zdep)



dL2 = i rj _____ .i1
2 1 V1 [ 2
d 2 ir + 2r. K (Vbi + VD) + K(VD + V -Dsa
dVD 2 D D bbibi Dsat F

Kr 1 de
x K+ K dVdep (3.74)
(Vbi + VD) dVD

where d de can be obtained from equation (3.50)-(3.51). The second
bracketed term in (3.72) represents the effect of the change of depletion

width under the gate due to the source potential being modulated. This

term is only important at high substrate concentration (CB > 1016Cm-3).

For the simplified case of source and drain junction with vertical sides

(or the equivalent condition r. >> /K(V + 0)), equations (3.70),
J Dsat F
(3.71), and (3.73) reduces to the forms

L = K(Vbi + V sa (3.75)
1 bi Dsat

L2 = K(Vb + VD) Adep (3.76)
dL2 =1 K dkdep
dVD 2 /K(Vbi + VD) dVD

Again for the case of a circulating charge Q and signal charge of

(Qo Qc) the transfer inefficiency also can be obtained by
=- (3.78)
B (Qo Qc)

where AVT is the threshold voltage variation of the switch transistor

when Qc and Qo are present at the drain node. This threshold voltage

variation AVT is obtained by calculating the variation of form factor

AFb for different drain potentials, and multiplying by the two bracketed

terms in (3.72).

For the model discussed in this section it is assumed that the


substrate concentration is uniform, the one-sided junction approximation

is valid, and that the channel length is long enough so that the source

and drain depletion regions do not meet under the gate. Any deviation

from these assumptions will cause errors and affect the accuracy of this

model. In Figure 3.14, the theoretical values of cB are plotted as a

function of channel length for different substrate concentrations NA.

In Chapter 6, the models discussed in this chapter will be compared with

experimental results.


rj = 1.5m -
tox= .111m

NA 6 x 1014

7 x 1015

3 x 1016



, (jm)

Figure 3.14 Theoretical transfer inefficiency due to barrier-
height modulation as a function of channel length
for different substrate concentrations.







1i -








4.1 Charge-Storage Operation of a Photodiode

The photodiode used in a solid-state image sensor is operated in

the charge-storage mode instead of the normal photoconductive or photo-

voltaic mode. In the normal photoconductive or photovoltaic mode, the

output from a photodiode depends on the rate of photon absorption;

however, as discussed in the previous chapter, the photodiodes in an

image sensor are sampled in a periodic manner. Therefore, the active

properties of the diode are used only during the time of sampling. To

fully utilize the sensing diode during the total sensing period, the

photon flux has to be integrated, which leads to the charge-storage mode

of operation.

In the charge-storage mode of operation the photodiode is precharged

first to a fixed reverse bias of a few volts, and the circuit is then

opened so that the junction behaves like a capacitor which discharges

smoothly under the influences of the illumination and the junction leak-

age current. While the photodiode integrates the light, it provides a

means to evaluate the total irradiation energy received. The charge

lost during the light integration period is proportional to the illumin-

ation energy received by the diode multiplied by the duration of light

integration. Thus, by monitoring the charge required periodically to



re-establish the initial-voltage condition, one may obtain a signal

proportional to the incident illumination. The advantages of this mode

of operation are the improvement of responsivity resulting from integra-

tion of the incident illumination and the capacity to control the

responsivity by varying the integration time.

The signal charge Qs obtained from the sensing diode at each sampling

time can be expressed as

Q = (I + I )T (4.1)
s p L i

where T. is the total integration time, and I and IL are the photocurrent
1 p L
and the leakage current respectively. The photocurrent I is related to
the incident power by

I = gAnAP (4.2)
p he
where A is the sensing diode area in cm

n is the quantum efficiency

X is the wavelength of the incident light

P is the incident power in watt/cm2

h is the Planck's constant

c is the velocity of the incident light

It is obvious from equation (4.1) that if I >>IL, the signal charge

Q will be proportional to the integration time T., and, therefore, the

sensitivity will increase by increasing T.. However, at low light level
the contribution of the leakage current is no longer negligible. This

leakage current not only introduces shot noise, but also results in a

fixed-pattern noise due to the dark current non-uniformity in each


sensing cell. In the very low light level limiting case where IL >Ip
L p
the sensing diode will be saturated by the dark current; therefore, the

dark current plays a very important role in the low light level applica-

tions of an image sensor. The leakage current is a strong function of

temperature and can be written as [49]

1 n.
IL q T- W.A (4.3)

where TO is the effective lifetime within the reverse-
biased depletion region

W. is the width of the depletion region

A. is the junction area.

The maximum amount of charge that a photodiode can store before it

spills over the anti-blooming control gate is also important. This is

commonly referred to as the saturation charge of photosensor. This

saturation charge determines the maximum output level and, therefore,

affects the useful dynamic range of the device. This saturation charge

can be obtained by integrating C(V)dV from the initial voltage V to the

final voltage VF which is determined by the anti-blooming gate voltage.

Assuming a one-sided step junction, the result can be given by

Qsat = (qKoNA) [(Vo + B) (VF + B) (4.4)

where 0B is the junction built-in potential. For a linearly graded junc-

tion, the result becomes

Q 2 2t 1/ 3 2/3
Q = V [~aK ] Vo + 0B)2/3 (V + 0)2/3] (4.5)

where "a" is the impurity gradient in cm and can be approximated by



a = X A n (4.6)
X. x 0.7 N

where X. is the junction depth and N is the surface concentration of
J o
the N diffusion which is usually around 10 cm .

The voltage drop across the photodiode is also proportional to the

total energy received. This voltage drop provides another way to sense

the total incident radiation by connecting a MOS sensing gate to each

diode. However, since the depletion layer capacitance varies with re-

verse bias, the relationship between irradiant energy and reverse bias

voltage is nonlinear. Assuming that the photocurrent is predominant,

the voltage across the junction as a function of time and photocurrent

can be obtained by solving the following equation [1]

C(V) = -I (4.7)
dt p

which leads to

V(T) = [V (22 t] (4.8)
SA sA 2 A

for the one-sided step junction, and

V(t) = 02/3 2 1 12 t (4.9)
s \qaK e _

for the linearly graded junction. As is the total sensing diode storage

area. Other than the nonlinearity of the optical-to-electrical transfer

characteristic, this voltage pick-up sensing method offers certain advan-

tages such a low reset noise, nondestructive readout, and higher



4.2 Sensing Diode to BBD Analog Register Charge-Transfer Mechanism

The charge transfer mechanism from the sensing diode into the BED

register, for the optimum area image sensor described in Chapter 2, is

very similar to that of the tetrode bucket-brigade device. Figure

shows the equivalent circuit of the charge transfer path. C represents
the storage capacitance of the sensing diode, 0 is the multiplex switch,

C is the video line capacitance, and C. is the junction capacitance of

the N diffusion between the LR and LT switches. The line reset LR

switch is not shown in the equivalent circuit since it is turned off

during the charge transfer process. Figure 4.1b shows the potential at

each node before the charge transfer. Since C is much larger than both

C and C., the charge transfer speed will be limited by the discharge of
s J
C through the Vbuff gate.

Ideally, during the charge transfer process, the MOS switches should

cut off when the potentials of each capacitor reach a value of (VG-VT),

where VG and VT are the gate potential and threshold of the MOS switches.

However, as discussed in Chapter 3, due to the subthreshold leakage be-

havior of the MOS switch, the current does not cut off sharply. Instead,

it decays exponentially, and as a consequence, the potential at each

capacitor will increase slowly beyond the (VG-VT) level with increasing

time. Theoretically this leakage current never ceases, and the potential

of the capacitor keeps increasing. However, in real applications, when

the current reaches a negligible level, the MOS switch is considered to

be in the off state.

To derive the equations for the charge transfer speed let us con-

sider the worst case transfer efficiency of the buffer gate at very low

light levels. Because the buffer gate is biased at a DC level of Vbuff

Figure 4.1

(a) Equivalent circuit for charge transfer between the sensing diode
and BBD shift register.

(b) Potential at each node before charge transfer.














H cX2







after each charge transfer the potential of the common video line will

increase with time which is depicted as V (t) in Figure From

Chapter 3, the subthreshold leakage current through the buffer gate can

be expressed as

qDn LBW -V(t)q/kT
I (t) = B e (4.10)
st Leff

where V(t) = V (t) (Vbuff VTbuff)

L eff is the effective channel length of the buffer gate

VTbuff is the threshold voltage of the buffer gate.

V(t) is the video line potential below the (Vbuff VTbff) level as

shown in Figure 4.1b. As the value of V(t) increases, the current de-

creases exponentially toward zero.

The small signal "ON" resistance of the buffer gate, operated in

this subthreshold region, now can be obtained by

dV LeffkT V(t)q/kT
R e e (4.11)
dI 2
st q DnoLW

From Chapter 3, the V(t) can be expressed by

q Dn L W
V(t) = n + t (4.12)

q kTL Ce
SkT In (4.13)
q LkTLeff v

where C is the video line capacitance. Substituting (4.13) into (4.11),

the small signal "ON" resistance now becomes

R = t (4.14)


It is clear from equation (4.14) that the subthreshold "ON" resis-

tance is independent of the geometry of the MOS switch. Therefore,

increasing the size of the MOS switch will not help the transfer speed.

Multiplying both sides of equation (4.14) by C results in a small signal

RC time constant of "t." The worst case time is the total integration

time. This worst case corresponds to the condition that only one diode

in the common video line is under illumination, and the rest are in the


In the above discussion, it is assumed that signal charge dumped

into the video line is so small that it does not change the video line

potential V significantly. Under this low light level, the charge

transfer time constant is so long that with a finite transfer time Tt

which corresponds to the pulse width of the LT clock, most of the signal

charge will be trapped on the video line. However, at high light levels,

the charge dumped into the video line is large enough to modulate the

video line potential considerably. As a result, the initial charge

transfer speed will increase greatly, and the percentage of signal charge

trapped on the video line will become less important.

To calculate the charge trapped on the video line after a finite

transfer time, Tt, at high light levels, let us assume that only one of

the diodes in the video line is illuminated, and a signal charge of Q

is dumped into the video line when this diode is selected. The signal

charge will lower the video line potential by an amount Qs/C Let us

further assume that the gm of buffer gate is large enough that the video

line potential will be discharged to (Vbuff VTbuff) in a time which

is negligible compared with the total transfer time Tt. At the end of

the transfer time, the video line potential will be


kT q DnLBW
V(T ) -= n + T (4.15)
t q kTL f t

where n is the equivalent carrier concentration at the source end of

the buffer gate when V = (Vbuff VTbuff). Before the illuminated diode

is selected again, the video line potential will reach V(Ti), where T.

is the integration time. The expression of V(T.) is identical to equation

(4.15) with T. replacing T The signal charge lost now can be determined
1 t

Q C = C [V(T.) V(T )] (4.16)

With a typical integration time of 4 ms and transfer time of 4 1s, the

charge loss calculated from equation (4.16) is about 30% even at a satur-

ation charge level of 1.5 pc. This results from the video line capaci-

tance, C being about ten times larger than the sensing diode storage

capacitance C
For the low light level case, let us assume that after the video

line potential has been lowered by a magnitude of Q /C its potential

is still "V below the (Vbuff VTbff) level. The video line potential
o buff Tbuff
then can be expressed by

/qp n WL V q/kT
V(t) = k n noC B t + eVok (4.17)
q \ Leff v

In equation (4.17), the electronic diffusion constant D has been replaced

by pn using Einstein's relationship, and the initial condition V = Vo at

t = 0 also has been incorporated. The worst case charge transfer inef-

ficiency now can be determined from

Cv [V(Tt) Vo]
E =-v (4.18)
C [V(Ti) V ]
V[VT -v


i no B t \
n + L efC x V q/kTI
S n eff v e o / (4.19)
qp n WL T. B T \
no B ___
n 1 eff+ v x eVoq/kT
\ eff v co

Examining equations (4.16) and (4.19) indicates that the ratio of

T /T. is important in determining the transfer inefficiency. To reduce

this ratio, the Vbuff gate can be clocked instead of DC biased. It can
be clocked with a pulse which is about the same width as the LT pulse.

However, in order to have the anti-blooming circuit function properly,

the rising edge of the Vbuff pulse should lead the rising edge of the

LT pulse by lhs or more to allow the video line to be reset through the

LR switch before charge transfer. Using this clocking scheme, T. in

equations (4.16) and (4.19) can be replaced by T which is the total

buffer gate "ON" time during the total integration time T.. In Figure

4.2, the transfer efficiency is plotted as a function of Q /C for a

T = 2ps and T = 300ps. It is clear that the transfer efficiency is
t on
still very poor.

To increase the charge transfer speed, a background charge of Qc

is needed. The function of this background charge is similar to the "fat

zero" in the BBD register. As discussed in Chapter 3, this background

charge will speed up the apparent transfer rate considerably, since the

charge lost will be the difference of the charges left behind when the

initial charges are Qc and (Q + Qs). Using the result of Chapter 3,

the low light level transfer inefficiency, which corresponds to Qs 0,

can be expressed as

e(Tt) 2 2 2 (4.20)
c t

Full Text
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