• TABLE OF CONTENTS
HIDE
 Title Page
 Dedication
 Acknowledgement
 Table of Contents
 Abstract
 Introduction
 Linear-region conductance of large-grain...
 Current-voltage characteristics...
 Anomalous leakage current of small-grain...
 Subthreshold behavior of thin-film...
 Summary, conlusions, and recom...
 Appendix
 Reference
 Biographical sketch
 Copyright














Title: Effects of grain boundaries in polysilicon-on-insulator (SOI) MOSFETS
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Permanent Link: http://ufdc.ufl.edu/UF00082438/00001
 Material Information
Title: Effects of grain boundaries in polysilicon-on-insulator (SOI) MOSFETS
Physical Description: vii, 155 leaves : ill. ; 28 cm.
Language: English
Creator: Ortiz-Conde, Adelmo, 1956-
Publication Date: 1985
 Subjects
Subject: Metal oxide semiconductor field-effect transistors   ( lcsh )
Grain boundaries   ( lcsh )
Electrical Engineering thesis Ph. D
Dissertations, Academic -- Electrical Engineering -- UF
Genre: bibliography   ( marcgt )
non-fiction   ( marcgt )
 Notes
Thesis: Thesis (Ph. D.)--University of Florida, 1985.
Bibliography: Bibliography: leaves 148-154.
Statement of Responsibility: by Adelmo Ortiz-Conde.
General Note: Typescript.
General Note: Vita.
 Record Information
Bibliographic ID: UF00082438
Volume ID: VID00001
Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
Resource Identifier: aleph - 000876113
oclc - 14706270
notis - AEH3691

Table of Contents
    Title Page
        Page i
    Dedication
        Page ii
    Acknowledgement
        Page iii
        Page iv
    Table of Contents
        Page v
        Page vi
    Abstract
        Page vii
        Page viii
    Introduction
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    Linear-region conductance of large-grain polysilicon MOSFETS
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    Current-voltage characteristics of large-grain polysilicon MOSFETS
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    Anomalous leakage current of small-grain polysilicon MOSFETS
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    Subthreshold behavior of thin-film small-grain polysilicon MOSFETS
        Page 97
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    Summary, conlusions, and recommendations
        Page 128
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    Appendix
        Page 134
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    Reference
        Page 148
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    Biographical sketch
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    Copyright
        Copyright
Full Text
















EFFECTS OF GRAIN BOUNDARIES IN
POLYSILICON-ON-INSULATOR (SOI) MOSFETS









By

ADELMO ORTIZ-CONDE


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN
PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA
1985



















TENGO EL INMENSO PLACER DE

DEDICAR ESTA TESIS A MIS PADRES



ALICIA CONDE-BRANDT DE ORTIZ

AnELMO ORTIZ PINERO



















ACKNOWLEDGMENTS

I would like to thank all those who helped me in one way or another

to make this work possible.

I wish to express my sincere gratitude to my guru, Dr. Jerry G.

Fossum, for his invaluable guidance, encouragement and assistance in all

phases of this dissertation. It has been my privilege and my pleasure

to have been his student. I am thankful to Professors Fredrik A.

Lindholm, Dorothea E. Burk, Sheng S. Li, and Arun K. Varma for their

participation on my supervisory committee. I also thank Professor

Arnost Neugroschel for his help during the experimental part of this

work and Professor Eugene R. Chenette for guiding my steps during the

beginning of my graduate work.

I want to express my appreciation to Drs. Hon Wai Lam, Ravishankar

Sundaresan, Hisashi Shichijo, and Sanjay Ranerjee of Texas Instruments,

Inc., for technological support.

I would especially like to thank my friends Drs. Hyung-Kiu Lim and

Ravishankar Sundaresan, former graduate students, for the many

insightful discussions. My interaction with them has been a very

gratifying learning experience. I would like to also thank my other

colleagues and friends, Dr. Franklin Gonzalez, Bruce Rushing, Dr. Hsing-

Liang Lu, Victor de la Torre, Tae-Wong Jung, Robert McDonald, Suy-Young

Yung, Surya Veeraraghavan, Dr. Jean Andrian, Dr. Ganesh Kousik, Arthur











Van Rheenen, Dr. Saeid Tehrani-Nikoo, and Juin-Jei Liou for helpful

comments and encouragements.

I am grateful to Ms. Carole Roone for her excellent work in editing

and typing this dissertation.

I cannot in words express my thanks to my former professors at the

Universidad Simdn Rolvar, Drs. Pierre Schmidt, Gustavo Roig, Paul

Esqueda, and Francisco Garcia, for all they have done in support of my

graduate work.

I am infinitely indebted to my parents and family for their

incredible support and encouragement throughout my graduate school

career.

The financial support of The Consejo Nacional de Investigaciones

Cientificas y Tecnologicas (CONICIT), Naval Research Laboratory (NRL),

and the University of Florida Center-of-Excellence Program is gratefully

acknowledged.



















TABLE OF CONTENTS



PAGE

ACKNOWLEDGMENTS ........................ ................... .iii

ABSTRACT... .......................................... ..............vi i

CHAPTER

ONE INTRODUCTION..... ............ ........................ ...... 1

TWO LINEAR-REGION CONDUCTANCE OF LARGE-GRAIN POLYSILICON MOSFETS..11

2.1 Introduction ...........................................11
2.2 Linear-Region Conductance in Strong Inversion...........14
2.2.1 Intragrain Electron Distribution in Channel.....14
2.2.2 Grain-Boundary Potential Barrier in Channel.....16
2.2.3 Channel Conductance... ......................... 24
2.3 Linear-Region Conductance in Moderate Inversion........31
2.4 The Significance of Grain Boundary Orientation..........35
2.5 Experimental Support and Discussion ....................38
2.5.1 Support for the Strong Inversion Analysis.......39
2.5.2 Support for the Moderate Inversion Analysis.....45
2.6 Summary.............. ...................................46

THREE CURRENT-VOLTAGE CHARACTERISTICS OF LARGE-GRAIN POLYSILICON
MOSFETS........................ ....................... .49

3.1 Introduction...........................................49
3.2 Analysis............................................... 51
3.2.1 Formalism .................... ............... 53
3.2.2 Numerical Solution ............................ ..59
3.3 Experimental Support and Discussion....................65
3.4 Summa ry................. .... .......... ... 67

FOUR ANOMALOUS LEAKAGE CURRENT OF SMALL-GRAIN POLYSILICON
MOSFETS ...................... ........... .... ....... 69

4.1 Introduction..........................................69
4.2 Leakage Current Model.................................73
4.3 Summary .................... ...... ........ .... ........94













FIVE SUBTHRESHOLD BEHAVIOR OF .THIN-FILM SMALL-GRAIN POLYSILICON
MOSFETS.............. ............................... ....... 97

5.1 Introduction................................. ...... 97
5.2 Analysis....................... ......... ............ .100
5.2.1 Formalism .................................... 102
5.2.2 Numerical Solution...................... .. 108
5.3 Experimental Results and Discussion...................121
5.4 Summary ...............................................125

SIX SUMMARY, CONCLUSIONS, AND RECOMMENDATIONS................ 128

6.1 Summary and Conclusions..............................128
6.2 Recommendations for Further Research..................131

APPENDICES

A THE CHARGE TRAPPED AT THE GRAIN BOUNDARY IN TERMS OF THE
OUASI-FERMI LEVEL. ...... .......................... ... ..... 134

B THE FOUNDATION OF A CHARGE-SHEET MODEL FOR THE THIN-FILM
MOSFET.................................................. ..136

C FORTRAN COMPUTER PROGRAM TO CALCULATE THE CHARGE DENSITY IN A
THIN-FILM SMALL-GRAIN POLYSILICON MOSFET ................ 140

REFERENCES.. ....... .... .................. ............ ... 148

BIOGRAPHICAL SKETCH.... ...........................................155


















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

EFFECTS OF GRAIN BOUNDARIES IN
POLYSILICON-ON-INSULATOR (SOI) MOSFETS

Ry

ADELMO ORTIZ-CONDE

August 1985

Chairman: Jerry G. Fossum
Major Department: Electrical Engineering

This dissertation presents physical models that describe the

effects of grain boundaries on the steady-state current-voltage

characteristics of large- and small-grain polysilicon (SOI: Si-on-Si02)

MOSFETs. These models, which are supported experimentally, reveal that

the grain boundaries can control the drain current and hence the

electrical properties of the MOSFET. Interpretations of measurements

based on single-crystal MOSFET theory can therefore result in erroneous

parameter evaluations and misconceptions regarding the underlying

physics. The models developed herein enable proper interpretations of

measurements and facilitate optimal design of the devices.

The models for the large-grain polysilicon SOI MOSFET predict:

(a) an effective turn-on characteristic in the linear-region, controlled

by the grain boundaries, that occurs beyond the strong-inversion

threshold voltage, and henceforth defines the "carrier mobility theshold












voltage" and the effective field effect carrier mobility; (b) a nearly

exponential dependence on the (front) gate voltage, defined by the

properties of the grain boundaries, for moderate-inversion conductance,

and (c) that a grain boundary near the drain can control the conduction

properties for all (weak-to-strong) inversion conditions in all (linear-

to-saturation) regions of operation.

The models for the small-grain polysilicon SOI MOSFET predict:

(a) the anomalous leakage current (OFF state), which is attributed to

field emission via grain-boundary traps in the (front) surface depletion

region at the drain; (b) that the gate-voltage swing for the

subthreshold drain current (ON state) depends strongly on the grain-

boundary properties and weakly on the charge coupling between the front

and back gates; (c) that the effective threshold voltage (ON state)

depends strongly on grain-boundary properties and on the charge coupling

between the front and back gates; and (d) the device design

modifications to control and reduce the leakage current, the gate-

voltage .swing, and the effective threshold voltage.


viii


















CHAPTER ONE
INTRODUCTION
Because of the advantages of dielectric isolation and three-

dimensional (3-D) integration [GI80; LA82; MA85], there is much interest

in SOI (silicon-on-insulator) MOSFETs. The advantages of these devices

compared with the single-crystal counterpart are [LA82]: (a) increased

circuit speed due to reduced parasitic capacitance; (b) superior

hardness to transient radiation; and (c) elimination of latch-up, which

is of fundamental importance when the feature sizes in CMOS

(complementary metal-oxide-semiconductor) technology are scaled to

smaller dimensions. Today, CMOS is the dominant technology for VLSI

(very large scale integration) because of low power consumption,

superior noise margins, better compatibility with analog circuits, and

reduced vulnerability to soft errors.

The most promising SOI technologies for VLSI are: SOI formed by

high-dose ion implantation [HE84], SOI using porous silicon [BA84],

silicon-on-sapphire (SOS) [SA84], beam recrystallization of polysilicon-

on-silicon dioxide [LA80], and as-deposited LPCVD (low-pressure chemical

vapor deposition) polysilicon-on-silicon dioxide [MA85]. The first two

of these technologies yield dielectrically isolated single-crystal

silicon, but they have disadvantages. The SOI formed by high-dose ion

implantation technology requires excessive capital costs for equipment,

and the SOI formed by the porous silicon technology is not compatible













with the subsequent process [LA82]. The SOS technology also produces

dielectrically isolated single-crystal silicon, but it has not been

widely accepted because of fundamental material limitations [LA82] that

impede the realization of high-quality silicon-on-sapphire. The beam-

recrystallization SOI technology, which yields large-grain polysilicon

(> 1 um), is of practical interest because of the relatively good

performance of the devices fabricated with it compared with that of the

single-crystal counterpart [LA80; TS81; C083,84]. The as-deposited

LPCVD SOI technology, which produces small-grain polysilicon (< 0.1 nm),

is also of practical interest because of the circuit applications

[MA84,85] that do not require stringent performance of all the devices,

e.g., CMOS memories, and because of the simplicity of the fabrication.

Because of the practicality of the last two technologies, it is of

primary importance to model the large- and small-grai.n polysilicon SOI

MOSFETs.

Most of the previous research and development of SOI has emphasized

either the technology, i.e., the recrystallization process [LA80; LE81;

NG81; TSA81; N1831 or the grain-boundary passivation [KA80; SH84; MA851,

or the recrystallized silicon [GE82; MA82; SC83], i.e., its

characteristic defects and grain boundaries. Little work [KA72;

DE80,82; LEV82; COV82,83,84] has been done on the characterization and

modeling of devices in large- and small-grain polysilicon SOI films,

which is essential if SOI integrated circuits are to be optimally

developed.













Such characterization of the large- and small-grain polysilicon SOI

MOSFET must include a description of the charge coupling between the

front and back gates [LI83b,84a,84b], and must account for the influence

of grain boundaries on the electrical characteristics, which is the

subject of this dissertation.

The inversion-mode large-grain polysilicon SOI MOSFET, illustrated

in Fig. 1.1, presents a relatively good performance compared with that

of the single-crystal counterpart [LA80; TS81; C083, 84], but it has the

disadvantage of requiring the additional recrystallization step. The

accumulation-mode small-grain (as deposited) polysilicon SOI MOSFET,

shown in Fig. 1.2, does not require the recrystallization step, but it

is inferior to the single-crystal counterpart, especially because of

anomalous high leakage current and exceptionally high gate-voltage swing

O[N82; SH841. To improve the performance of the small-grain SOI MOSFET,

for applications that do not require single-crystal silicon device

characteristics (e.g. load elements for a dense static RAM), grain-

boundary passivation (e.g., via hydrogenation [KA80; SH84]) has been

successfully used [MA84; MA85]. Unlike the large-grain polysilicon

device, the small-grain polysilicon device can be designed to be

operated in either the accumulation- or inversion-mode because the film

body (grains) is completely depleted of free carriers, facilitated by

grain-boundary trapping.

The purpose of this dissertation is to develop physical models for

the effects of grain boundaries in large- and small-grain polysilicon

SOI MOSFETs, which are useful for the prediction and optimization of













VG f Polysilicon or Metal
Li Si 02
I / Yfl


(V


SPolysilicon Film
/


li^^^^^^^^^^^^J;^;^^ 1


Si Substrate


VG b


Fig. 1.1 Cross-section of the four terminal n-channel inversion-mode
heam-recrystallized (large-grain) polysilicon SOI MOSFET.
The terminal voltages are .referenced to the source voltage
(Vs 0).


Vs =0

JTI


IiI.J11I1i11 1 1111111


77 r- II


--


i I












































VGb


Basic structure of the four-terminal p-channel accumulation-
mode LPCVD (small-grain) polysilicon SOI MOSFET.


Fig. 1.2













device performance in SOI integrated circuits. Chapters Two and Three

concern the large-grain polysilicon device, and Chapters Four and Five

concern the small-grain polysilicon device. The major contributions

made in this dissertation are:

(1) the modeling of the effects of grain boundaries for all

regions of operation in large-grain polysilicon SOI MOSFETs;

(2) the physical characterization of the anomalous leakage

current (OFF state) in small-grain polysilicon SOI MOSFETs;

(3) the numerical modeling of the subthreshold drain current and

the threshold voltage (ON state) of thin-film small-grain

polysilicon SOI MOSFETs;

(4) the development of the foundation of a charge-sheet model

[RR78,811 for the thin-film single-crystal SOI MOSFET;

(5) the experimental support for the developed models from

measurements of representative SOI MOSFETs.

We derive in Chapter Two a theoretical description of the linear-

region drain current of the large-grain polysilicon SOI MOSFET, which is

valid for all inversion levels and accounts for arbitrary orientation of

the grain boundaries. The corresponding channel conductance shows an

effective turn-on characteristic controlled by the grain boundaries that

occurs beyond the strong-inversion threshold. Henceforth the carrier

mobility threshold voltage, which exceeds the actual one, and the

effective carrier mobility, which is typically higher than the actual

(intragrain) one, are defined. For sufficiently high gate voltage, the

grain-boundary potential barrier is low enough that the channel












conductance is not significantly influenced by the boundaries. For gate

voltages lower than the carrier mobility threshold voltage, the

conductance varies nearly exponentially with the gate. voltage and

depends strongly on the grain-boundary properties. Grain boundaries

perpendicular to the carrier flow in the channel produce the strongest

effects on the conductance. To support this analysis and to stress its

practicality, we compare model, predictions with measured current-

voltage-temperature characteristics of laser-recrystallized SOI MOSFETs

fabricated at Texas Instruments [LA83]. The theoretical-experimental

agreement is good, and in addition to indicating properties of the grain

boundaries in these devices, it exemplifies how the mobility threshold

voltage and the effective carrier mobility can be easily misinterpreted

as the actual threshold voltage and mobility when conventional MOSFET

theory is used as the basis for interpreting electrical measurements of

SOI MOSFETs. Such misinterpretations can obscure essential criteria for

achieving optimal designs of SOI devices and integrated circutis. For

example, our physical analysis reveals that in particular cases grain

boundaries can actually benefit the SOI MOSFET performance by producing

an unusually high transconductance. This suggests, in contrast to the

general belief, that optimal designs may not require elimination of all

grain boundaries.

We describe in Chapter Three a physical model for the current-

voltage characteristics of the large-grain polysilicon SOI MOSFET in all

regions of operation. The essence of this model is an accounting for

sizable, position-dependent voltage drops across the grain boundaries













that-can occur when the device is. driven out of the linear-region. The

carrier transport through the grain boundaries (viz., over potential

barriers-created by carrier trapping) is .then nonlinear, and the'channeT

conduction depends -on how the grain boundaries are distributed between

the source and the drain. Although our model accounts for any number of

grain boundaries in the channel, we apply it herein to the most likely

case (in beam-recrystallized VLSI) of an SOI MOSFET with only one grain

boundary. We emphasize the importance of the position of the grain

boundary, as well as its electrical properties, in defining the current-

voltage characteristics. Model calculations, supported by limited

experimental results, show that grain boundaries tend to decrease the

drain current of large-grain polysilicon SOI MOSFETs, but can increase

the transconductance.

We develop in Chapter Four a physical model for the anomalous

leakage current (OFF state) in small-grain polysilicon SOI MOSFETs based

on field emission via grain-boundary traps. To support this model, we

compare its predictions with measured data from p-channel accumulation-

mode and n-channel inversion-mode devices FSU84; SH85]. Good

correlation is shown, and field emission at the back surface is

suggested as the mechanism underlying the minimization of the leakage

current at relatively low values of front gate voltage. Insight

regarding the physics underlying the anomalously strong drain and gate

voltage dependence is readily provided by the model, and implies design

criteria to control the leakage current in small-grain polysilicon

MOSFETs.












We .derive in Chapter. Five a theoretical description of the.

subthreshold drain current and the threshold voltage (ON state) in the

thin-film small-grain polysil icon SI. MOSFET,--which reveals-the' physical

influence of grain boundaries in the channel, and the charge coupling

between the front and back gates. The main results of this model,

supported by experimental results, are: the gate-voltage swing depends

strongly on grain-boundary properties and weakly on the charge-coupling

effects; the threshold voltage depends strongly on grain-boundary

properties and charge-coupling effects; the charge-coupling effects

decrease as the trap density, the thickness of the film, or the doping

concentration increases.

We summarize in Chapter Six the main conclusions and

accomplishments of this dissertation. We also suggest in this chapter

further related research.

We show in Appendix A that the electron charge trapped at a grain

boundary (in an n channel) can be expressed in terms of the electron

quasi-Fermi level for any grain-boundary voltage drop. This result,

which was used in Chapter Three, indicates that a previous assumption

rRA78a], which establishes that the charge trapped at the grain boundary

is independent of the grain-boundary voltage drop, is generally

invalid. In Chapter Three, we have also avoided the use of another

classical, but generally invalid assumption [MU61] that a (constant)

fraction of the thermionically emitted electrons are captured by the

grain-boundary traps.












As a first step towards the development of a practical model for

integrated circuit design with SOI MOSFETs, we present in Appendix R the

foundation of a-charge-sheet model -[RR78,81] for the thin-film single-

crystal silicon MOSFET.

In Appendix C we include the computer program used in Chapter Five

to calculate the subthreshold drain current and the threshold voltage

(ON state) in the thin-film small-grain polysilicon MOSFET. The program

is based on a "two-dimensional" bisection method [RU81] that we

developed. Although this method is not as fast computationally as

Newton-Raphson [RU81], we use it because it avoids the problems of

convergence that typically occur when Newton-Raphson [BU81] is applied

to complex problems.


















CHAPTER TWO
LINEAR-REGION CONDUCTANCE OF LARGE-GRAIN
POLYSILICON MOSFETs



2.1 Introduction

We derive in this chapter a theoretical description of the linear-

region drain current of the large-grain polysilicon SOI MOSFET, which

reveals the physical influence of grain boundaries in the channel. The

corresponding channel conductance is described in terms of the (front)

gate voltage, the device parameters, and the grain and grain-boundary

properties. We restrict our analysis to cases in which the polysilicon

film is not completely depleted between the front and back surfaces. We

initially assume in Section 2.2 strong inversion, and that the grain

boundaries in the channel are perpendicular to the carrier flow; but we

generalize the analysis in Sections 2.3 and 2.4 by removing these two

assumptions respectively.

The model comprises the following physics: (a) the quantum-

mechanical description [HS79] of the carrier distribution in the

inversion layer, which implies an average carrier density and its

dependence on the gate voltage that can be modeled based on the

classical solution [C070; SZR11; (b) the two-dimensional potential

variation near a grain boundary in the channel, which when approximated

by coupled one-dimensional solutions of Poisson's equation defines the












grain-boundary barrier height resulting from carrier trapping [BA78a,b];

and (c) the description of the carrier transport through the grain

boundary, assumed to be predominantly thermionic emission over the

potential barrier [PI79]. To obtain closed-form expressions for the

channel conductance, which give physical insight and facilitate the

development of SOI MOSFET models suitable for computer-aided circuit

analysis, simplifying assumptions are made and justified.

The resulting strong-inversion channel-conductance model of

Section 2.2 shows an effective turn-on characteristic controlled by the

grain boundaries that occurs beyond the strong-inversion threshold.

Henceforth the carrier mobility threshold voltage, which exceeds the

actual one, and the effective carrier mobility, which is typically

higher than the actual (intragrain) one, are defined. For sufficiently

high gate voltage, the grain-boundary potential barrier is low enough

that the channel conductance is not significantly influenced by the

boundaries. Thus the intragrain mobility, which can be affected by

surface scattering [SU801, controls the conductance at high gate

voltages.

In Section 2.3 we extend the analysis to account for moderate- and

weak-inversion levels. For gate voltages lower than the carrier

mobility threshold voltage, we find that the conductance varies nearly

exponentially with the gate voltage, and that the gate-voltage swing

needed to reduce the conductance by one order of magnitude is strongly

dependent on the properties of the grain boundaries.













We account in Section 2.4 for -arbitrary orientation of the grain

boundaries. This analysis is of interest because of the possibility of

controlling [MA82; :TSA82; N183; SC83] the predominant grain-boundary

orientation in devices fabricated in recrystallized polysilicon. We

find that grain boundaries perpendicular to the carrier flow in the

channel maximize the grain-boundary effects on the conductance. In

contrast, grain boundaries parallel to carrier flow in the channel do

not affect the conductance.

To support the analysis and to stress its practicality, we compare

in Section 2.5 model predictions with measured current-voltage-

temperature characteristics .of .laser-recrystallized SOI., MOSFETs

fabricated at Texas Instruments [LA83]. The theoretical-experimental

agreement is good, and in addition to indicating properties of the grain

boundaries in these devices, it exemplifies how the mobility threshold

voltage and theeffective carrier mobility can be easily misinterpreted

as the actual threshold voltage and mobility when conventional MOSFET

theory is used as the basis for interpreting electrical measurements of

SOI MOSFETs. Such misinterpretations can obscure essential criteria for

achieving optimal designs of SOI devices and integrated circuits. For

example, our physical analysis reveals that in particular cases grain

boundaries can actually benefit the SOI MOSFET performance by producing

an unusually high transconductance. This suggests, in contrast to the

general belief, that optimal designs may not require elimination of all

grain boundaries.













2.2 Linear-Region Conductance in Strong Inversion

We assume, based on studies [RA78a,h; PI79] of majority-carrier

transport through silicon grain boundaries at room temperature, that

thermionic emission of carriers over the grain-boundary potential

barrier YRo underlies the predominant influence of the boundary on the

channel conductance of SOI MOSFETs, and that VBo results from carrier

trapping at localized grain-boundary states. The trapping and VRo are

characterized by a two-dimensional solution of Poisson's equation in the

channel. Before we discuss this solution and the corresponding

thermionic-emission current, we must consider the intragrain carrier

distribution in the channel and its dependence on the gate bias, which

define YBo. We refer to the four-terminal n-channel inversion-mode

large-grain polysilicon SOI MOSFET illustrated in Fig. 1.1, and we

assume that the grain boundaries in the channel are perpendicular to the

electron flow.


2.2.1 Intragrain Electron Distribution in Channel

Because the inversion layer thickness xi is very narrow (on the

order of the electron de Rroglie wavelength), the true electron

distribution n(x) in the channel (away from grain boundaries) must be

described quantum-mechanically [HS791. This description follows from a

self-consistent solution of the Schrodinger equation and Poisson's

equation. The result differs markedly from the classical solution

[C070, SZ81] based on Poisson's equation and Maxwell-Boltzmann

statistics: xi is narrower and n(x) is more uniform [HS79]. However the

inversion-layer areal charge density,













X
-0 = qJ n(x)dx (2.1)
n 0


where x = 0 represents the Si-Si02 interface, is predicted well-by the

classical solution.

The analyses suggest a simplification in the description of n(x)

and its dependence on the (front) gate voltage VGf. We define an

average electron density R over the effective portion of the inversion

layer, O< x< xi(eff), as revealed by the quantum-mechanical solution,

but we use the classical solution, ncl(x), to convey the Vf

dependence.. We find that Xi(eff) is described well by


i(eff)cl cl
qf n (x)dx = -0.9 O01 (2.2)
0 n


where OCl (= On) is given by (2.1) with n(x) replaced by ncl(x); that

is, about 90% of the inversion-layer charge is contained within a region

in which n = and in which virtually all the channel current flows.

Then we define R by



qnxi(eff) = -0.9 01 n (2.3)


Numerical evaluations of xi(eff) reveal that it is not strongly

dependent on VGf, that it decreases with increasing film doping density

NA, and that typically it is quite narrow. For example, when NA
1016 cm-3, Xi(eff) = 120 A. Corresponding calculations of R defined by












(2.3) are plotted versus (VGf -. VTf) in Fig. 2.1 for-different values of
NA and for an oxide thickness tof of 600 A; VTf is the threshold voltage
S'-"-'- 3b:. .8h that corresponds to- the -onset of strong tnverstorn-~rC l(y

NAI.- As -implied by (2.3), Fig. 2.1 shows that n increases with

increasing VGf and with increasing NA. We find that Xi(eff) and 5 as

defined by (2.2) and (2.3) in terms of the classical solution [C070;

SZ81] are generally consistent with the actual electron distribution

given by the quantum-mechanical solution rHS79].


2.2.2 Grain-Roundary Potential Barrier in Channel

...For .strong-inversion_. conditions within the grains, .electron
trapping at localized grain-boundary states produces potential barriers

that -affect the electron transport along the channel. The barrier

formation is similar to that at grain boundaries in bulk polysilicon

S. A78b;: .F0821_ except in the channel 'To is influenced by IVf ..as
described by the two-dimensional form of Poisson's equation.

We consider the potential variation near a grain boundary in the

channel as shown in Fig. 2.2. We assume that away from the grain

boundary (y > yd) the electric field is vertical (in the x-direction),

and n(x) is, well approximated by n over the effective inversion layer,

n x Xi(eff), as discussed in the preceding subsection. In this

region (I), Poisson's equation simplifies to



-= + NA) (2.4)
ax 2 s

















4 x 1017




3.5 x 1017




3 x 1017




2.5 x 1017


t.. 5 x










0.5 x


VGf VT (V)


Fig. 2.1 Calculated average electron density in channel versus (front)
gate voltage for several film doping densities.





















.*....... ... .. :::: .... ........




. . .

x1
1 e 0111








nn+






Grain Boundaries



Fig. 2.2 Cross-section of effective inversion layer showing typical
grain and grain boundaries, which are assumed to he
perpendicular to the electron flow.













where' is the electrostatic potential. In the vicinity of the grain

boundary (y < yd), a horizontal (y-direction) component of the electric

field is produced by the electrons trapped at the grain boundary. We

assume that the trapping nearly depletes this region (II) of free

electrons; hence


+ = + NA (2.5)
ax y I s


We note that this depletion approximation [BA78b; PI79] is valid

provided VBo is sufficiently high: high enough in fact, we assume, that

the grain boundaries significantly affect the channel conductance. We

discuss the validity of this assumption in Subsection 2.2.3.

Assuring that, analogous to the gradual-channel approximation

FSZ81], the trapped electrons at the grain boundary typically create

only a small perturbation on the x-component of electric field, we can

write


< -< 2(2.6)
ax a x ay


where the partial derivatives are evaluated anywhere in the regions

indicated. We justify this assumption by noting that the subsequent

solution we obtain is consistent with it when (VGf VTf) > Y' which

is usually true for strong-inversion conditions. Hence (2.6) implies an

approximate solution to the two-dimensional problem defined by (2.4) and

(2.5), which is obtained by coupling two one-dimensional solutions.













The corresponding approximation for VBo derives

combination of (2.4)-(2.6), which yields



2 q -
2 = -. in
Iy s

with the boundary conditions


S(x,y = yd) =I (x)


from the




(2.7)


(2.8)


and


(2.9)


In (2.8) Yl(x) is the intragrain (region I) potential variation in the

channel, which is given by the one-dimensional solution of Poisson's

equation and the Schrodinger equation [HS79]. We now identify yd as the

grain-boundary depletion-region width, and we note that our analysis

applies only when the grains are not completely depleted. The solution

to (2.7)-(2.9) is


S(x,y) II (y-- _d + (x)


and hence

-2
qny.
Ro = TI(x) (x,0) 11 -4-
s


(2.10)


(2.11)


Tay Y=Yd















To complete the description of YBo, we must express yd in terms of

known parameters. This expression is implied by the conservation of

charge in the vicinity of the grain boundary:



OG = 2qnyd (2.12)


which equates the areal density of charge trapped at the grain boundary,

OGg, to the electron charge density removed to form the (two) adjacent
depletion regions. In writing (2.12) we have implicitly assumed that

the electrons are trapped within Xi(eff), which is commensurate with our

previous assumptions. The trapped charge density depends on the

distribution in the energy gap of localized grain-boundary states

(acceptor-type since QGB < 0) [PI79]. It is reasonable to approximate

this distribution by a delta function [BA78b; PI79; F082; tU81],

yielding NST states (traps) per unit area at an energy level ET. Then


-qNST
O = E- ES (2.13)
1 ET F-Y=O
1 + exp kT

where EF is the Fermi level and the factor of 1/2 reflects the (spin)

degeneracy of the localized states. The position of EF relative to ET

is defined by YRo and the electron density in region I, i.e., n:



[ET EFy ET E + Bo nn (2.14)
FT+ B q













where Ei is the intrinsic Fermi level (virtually at midgap) and ni is

the intrinsic carrier density in silicon.

Thus (2.11)-(2.14) implicitly describe ?Bo in terms of the grain-

boundary parameters NST and (ET Ei), and of R, which depends on VGf

and the MOSFET properties as described in Subsection 2.2.1. Numerical

calculations of TBo are plotted versus (VGf VTf) in Fig. 2.3 for NA =

1016 cm-3, tof = 600 A two representative values of NST, '1011 and

1012 cm-2, and three positions of ET in the energy gap. In all cases,

for VGf sufficiently high, 1Bo decreases with increasing Vgf. This can

be explained by noting that under these conditions virtually all the

grain-boundary ,states. (within Xi(eff)) ;are filled, ;and hence

OGR = -qNST is independent of VGf. Therefore since R increases with VGf
(see Fig. 2.1), yd concomitantly decreases as described by (2.12), which

implies through (2.11) that 'Ro also decreases:


qNST
TRo = (2.15)
Ssn

However when VGf is low,'Bo is nearly insensitive to Vgf. This is

because the grain-boundary states are not completely filled, and hence

EF is near ET, which virtually fixes YBo as described by (2.14).

We note in Fig. 2.3 that for NST = 1011 cm-2, Bo is less than

10 mV when (VGf VTf) exceeds about 0.1 V. Thus although our depletion

approximation is invalid for these conditions, we surmise that YRo is

low enough that the grain boundaries do not significantly affect the

channel conductance. However for NST = 1012 cm-3, so is high enough,




















































VcQ VT (V)


Calculated grain boundary potential barrier versus (front)
gate voltage for two representative grain-boundary trap
densities and three energy levels. We note that the low
values of 'YRo calculated for NST = 101 cm-2 are probably
inaccurate because of the invalidity of the depletion
approximation (2.5). Nevertheless the curve is useful
because it indicates when f3o is low enough that the grain-
boundary effect on channel conduction is insignificant.


Fig. 2.3












even when (VGf VTf) is relatively large, to validate the depletion

approximation and to strongly influence the channel conductance as we

describe in the next section.


2.2.3 Channel Conductance

The physical basis for the influence of grain boundaries on the

channel conductance is the interaction between electrons flowing from

source to drain and the potential barriers at the boundaries. Although

quantum-mechanical tunneling of electrons through the barrier may be

significant at low temperatures FLU81] and diffusion of electrons is

important when the barrier is low [C082, 83, 84], we assume (at room

temperature) that thermionic emission of electrons over the barrier

T o is the predominant grain boundary transport mechanism [PI791. Then
if the drain voltage VD is low enough (linear region) that the voltage

drop across a grain boundary Vgb is much smaller than 2kT/q, and if

YRo > kT/q, the emitted current density is [BA78b]


J qA*T exp( TRo n V (2.16)
gb kNC kT gb


where A* is the effective Richardson constant [SZ81] for electrons

(= 250 A/cm2/K2) and NC is the effective density of states in the

conduction band (= 2.9 x 1019 cm3 at 3000 K).

Since the current in the channel is continuous from source to

drain, the drain current ID can be expressed by the integral of (2.16)

over the (effective) cross-sectional area of the channel:














ID Z Xi(eff) gb (2.17)


where Z is the channel width. The combination of (2.16) and (2.17)

gives ID as a function of Vgb. To obtain ID as a function of VD, we
simply equate the sum of the voltage drops along the channel to Vn. If

we assume that the channel comprises Ng grains of equal length yg
separated by (Ng 1) identical grain boundaries (see Fig. 2.2), then


V = (Ng 1)Vgb + NV (2.18)


where Vg is the voltage drop across a grain, which assuming that the

carrier transport in the grain is by drift CSZ81] is


y 2y (2.19)
V -1- ng n I


in the linear region. In (2.19) ung is the intragrain electron

mobility, the dependence of which on VGf and on device parameters can be
given empirically [SU80].

Combining (2.3) and (2.16)-(2.19), we obtain In(VGf,VD) for the SOI
MOSFET in the linear region (VD < (Ng 1) 2kT/q). If we assume that

Yg >> d, which is valid in typical recrystallized SOn MOSFETs, then our
result simplifies to


~ "nI Ong V
D (N -) k n eRo(Vf) (2.20)
S0.9LA*T kT















where L = Ngg is the channel length. In (2.20) 0n is given by the
strong-inversion condition



-Qn Cf(VGf Tf) (2.21)


where Cof is the (front) gate oxide capacitance.

The influence of the grain boundaries on ID is reflected by the

second term in the denominator of (2.20), which depends of VGf through

Bo[(VGf- VTf)] as described in Subsections 2.2.1 (Fig. 2.1) and
2.2.2 (Fig. 2.3). If the number of grains Ng constituting the channel

is one, vis-a-vis, if there are no grain boundaries in the channel, then

(2.20) reduces to the corresponding result of conventional MOSFET theory

FSZ81I. Furthermore if Bo is sufficiently low, because of low NST
and/or high VGf (see Fig. 2.3), then the same result obtains. We note

that (2.20), which because of the model assumptions is strictly valid

only when RBo > kT/q, will correctly give the conventional current at

high VGf only if the pre-exponential coefficient is much less than

unity. With this insight then, (2.20) facilitates a self-consistency

check for our model assumptions (2.5) and (2.16). We find that when the

grain boundaries are influential, TBo is generally high enough that the

assumptions are valid.

In deriving (2.20) we have neglected thermionic field emission

(tunneling) through Yo, and we have ignored the possible existence of a

significant grain-boundary scattering potential barrier [LU81] through












which the electrons must tunnel to traverse the boundary. The tunneling

can be predominant at low temperatures, but at room temperature and
above it is generally insignificant [PI79; LU811. We also neglected

diffusion of electrons through iBo, which is important only when 'Ro is

low [C083]. When VBo is high enough that the grain boundaries

significantly affect ID, the diffusion can be ignored.

To illustrate the grain-boundary effects described by (2.20), we

plot in Figs. 2.4 and. 2.5 calculations of the linear-region channel
conductance (gA ID/VD) versus (VGf VTf) for several values of Ng and

NST. In Fig. 2.4 we let Ng vary from one to 200 grains, and we use
typical- values for the remaining -parameters: NST = 1012 cm2 ..at

ET = Ei; N = 116 cm-3, tof = 600A Z = L = 40 um; we also specify a
(front) fixed oxide charge density Off = q(1011 cm'2), which

defines ng and its dependence on VGf [SU80]. We see that as Ng
increases, g decreases and the plots become inflected, in general

accord with recent measurements of laser-annealed SOI MOSFETs
[LE81; C084]. The plots show apparent threshold voltages that are

higher than VTf and transconductances (gm A ID/VGf = VD9g/VGff) that

imply effective electron mobilities (via the conventional MOSFET theory

[SZ81]) which can differ from i The apparent threshold voltage is
actually a "carrier mobility threshold voltage" (V ) at which n becomes

high enough that TRo begins to diminish with increasing VGf (see

Fig. 2.3) as described by (2.15). For VGf > V, 1Ro is too low to
significantly affect ID; that is, the Ro term in (2.20) is negligible,

and gm is defined by vng. Note however in Fig. 2.4 that the plots for

















































.0 1.5
VGI Vf (V)


Fig. 2.4 Calculated linear-region channel conductance versus (front)
gate voltage for several numbers of grains constituting the
channel. The broken portions of the curves for N =20, 100,
and 200 are inaccurate because of the invalidity of (2.20) as
discussed in Subsection 2.2.3. The N = 1 curve is
inaccurate for VGf near VTf because of the invalidity of the
strong-inversion relationship (2.21).












9 x 10-5


8 x 10-5


7 x 10-5



6 x 10-5




5 x 10-5




4 x 10-5




3x 10-5




2 x 10-


10-5




0


VGf VTf(V)


Fig. 2.5 Calculated linear-region channel conductance versus (front)
gate voltage for several grain-houndary trap densities.













Ng very large become erroneous when VGf >> V because, as we discussed

previously, the pre-exponential coefficient in (2.20) is not much less

than unity. When Vf > V g is typically higher than that

corresponding to ng. We stress that the high effective electron

mobility implied by gm is defined predominantly by the properties of the

grain boundaries. Measured ID(VGf,VD) characteristics of SOI MOSFETs

can thus be misleading because of the nonlinear effects. of grain

boundaries as we discuss in the next section.

Additional calculations reveal that V depends on NA and tof; it

decreases with increasing NA and it increases with increasing tof.

These dependence reflect, for a given (VGf VTf), the dependence

of n, which controls ~Ro, on NA shown in Fig. 2.1 and on tof implied

by -0n Cof.

The plots of g versus (VGf VTf) in Fig. 2.5 for NST ranging from

1011 to 2 x 1012 cm"2 were calculated from (2.20) for the same device

parameter values used to derive the plots in Fig. 2.4. We let Ng = 2

(one grain boundary) to simplify the physical interpretation of the

results. The same type of inflection seen in Fig. 2.4 is noted in

Fig. 2.5 for NST > 1011 cm-2. For the device considered, if NST is much

lower than 1012 cm-2, the grain boundary is virtually ineffective;

whereas if NST is higher than 1012 cm-2, the grain boundary severely

affects (lowers) the channel conductance. Similar calculations have

been made for different values of ET. In this case of the n-channel

MOSFET, we find that as ET approaches the conduction-band

edge, RoO diminishes and the grain boundary becomes ineffective. As ET













moves toward midgap and below, the grain-boundary effect materializes as

indicated in Fig. 2.5. This dependence on ET reflects the electron

occupancy of the grain-boundary states, which has been described

elsewhere [F082]. These results for a monoenergetic trap density could

be used to infer corresponding results for different trap distributions

in the energy gap.



2.3 Linear-Region Conductance in Moderate Inversion

To extend the analysis described in Section 2.2 to the moderate

inversion region of operation, we must remove the strong-inversion

approximation. (2.21). If the polysilicon ..film is not completely

depleted between the front and back surfaces, we can neglect the charge-

coupling effects [BA80; LI83b]. Then for all inversion conditions

[TSIR2],



0n = 0s b (2.22)


where

Sn. 2 q 1/2
s sf n qsf
s r -kT + exp( kT (2.23)


is the (areal) charge density in the silicon and


f 1/2
b = -r -k- 11 (2.24)
b r ,KT












is the depletion-region charge density. In (2.23) and (2.24), *sf is

the front hand bending and Or = [2kTesNA 1/2 has been defined to make a

compact notation. The relationship between \sf and VGf is defined by


f 0s qNsf
Gf VFR sf C C sf (2.25)
of of

where VFR is the front-gate flatband voltage [NI82], which includes a

contribution from fast surface states at the Si-Si02 interface, the

density Nsf (cm-2eV-1) of which is assumed to be uniform in the energy

gap. The On(VGf) dependence in (2.20) is now defined by (2.22)-(2.25).

,.,To illustrate the grain-boundary effects in moderate inversion
described by (2.20) and (2.22)-(2.25), we plot in Fig. 2.6 and 2.7

calculations of the linear-region channel conductance versus VGf for

several values of ET and Nsf. To facilitate a later comparison between

experimental and theoretical results (see Section 2.5.2), we set

VTf = 0, which defines VFB through (2.25). In Fig. 2.6 we let (ET-Ei)
vary from 0 to 0.22 eV, and we use typical values for the remaining

parameters: NA = 2x1016cm-3, which implies Xi(eff) = 80 A, n =
380 cm2/v-sec, tof = 600A Z = L = 40 urm, NST = 012cm-2, and Ng = 50.

We see that the conductance presents a nearly exponential dependence on

VGf for the lower-VGf(
voltage swing S needed to reduce ID by one order-of-magnitude increases

as ET increases. This dependence is due primarily to the exp(-k -) term
in (2.20) which is dominant (>> 1).










10-4


0 .2 .4 .6 .8 1.0 12 1.4
V.f... (V) .. .....


Fig. 2.6 Measured (points) and calculated (curves) linear-region (Vr =
50 mV) conductance versus front-gate voltage of an n-channel
SOI MOSFET in laser-recrystallized polysilicon at room
temperature. The measurements were made with the hack gate
biased at -40 V. The calculations were done for different
grain-boundary trap energy levels as indicated and with the
fast surface-state density at the front Si-Si02 interface
equal to zero. Note that VTf = 0 V.

















































VGf(V)


Fig. 2.7


Measured (points) and calculated (curves) linear-region (VD =
50 mV) conductance versus front-gate voltage of an n-channel
SOI MOSFET in laser-recrystallized polysilicon at room
temperature. The measurements were made with the back gate
biased at -40 V. The calculations were done for different
fast surface-state densities at the front Si-Si02 interface
as indicated and with the grain-boundary trap energy level at
0.2 eV above midgap.













The plots of g versus VGf in Fig. 2.7 for Nsf ranging from 0 to

5 x 1011 cm-2eV-1 were calculated for (ET-Ei) = 0.2 eV and the same

remaining parameters values used to derive the plots in Fig. 2.6. 'We

see that S is nearly independent of Nsf although g decreases as Nsf

increases.

We conclude this subsection by stressing that the drain current in

the lower-VGf, or "submobility-threshold" (VGf < V ) regions of

operation, presents a nearly exponential dependence with respect to VGf,

and that the gate-voltage swing needed to reduce ID by one order-of-

magnitude is strongly dependent on the properties of the grain

boundaries.


2.4 The Significance of Grain Boundary Orientation

The studies in Section 2.3 and 2.4 have been based on the

assumption .that- the grain boundaries are perpendicular to the carrier

flow in the channel. In this Section, we generalize the analysis to

account for arbitrary orientation of the grain boundaries. This

generalization is of interest because of the possibility of controlling

[MA82; TSA82; NI83; SC831 the predominant grain-boundary orientation in

devices fabricated in recrystallized polysilicon.

We consider a (straight) grain boundary arbritrarily oriented in

the channel as shown in Fig. 2.8. The drain current can be expressed,

to first order, as


IF = Iff + IDb


(2.26)




















H ----L----)


grain boundary

n+ y n+ Ib




















Fig. 2.8 Illustration of arbitrary grain-boundary orientation in
channel.












where IDf is the component that flows in the grain-boundary-free portion

(Z-Zb) of the channel and IDb is the component that flows in the portion
(Zb) containing the grain boundary. Note in Fig. 2.8 that Zb is defined

by Z and L, and the angle between the grain boundary and the

z-direction. In the linear region (strong inversion),


(Z-Zb)
lOff L ngCof(VGf Tf)VD (2.27)


The characterization of IDb depends on a complicated two-

dimensional electron transport problem. To derive a crude

approximation, we assine that the electron current density Jgb through

the grain boundary (via thermionic emission) is perpendicular to it.

Then, analogous to (2.16),


:qA*T e p BO
Jgh exp( kT )V gbn (2.28)


where n = cos(O )y sin(e )z is the unit vector normal to the grain
boundary. We further assume that away from the grain boundary the

electrons flow predominantly in the y-direction. Then to ensure current

continuity from source to drain, we must have


Zb (2
Ob cost ) Xi(eff) n* gb (2.29)












Using (2.28) and (2.29) and following the derivation in Section 2.2, we

obtain

b
I ng Cof (VGf -VTf )V
Db kN qP (2.30)
1 0.9LA*T expkT) cos(O )
The combination of (2.26), (2.27) and (2.30) then describes

approximately, for strong-inversion conditions in the linear region, the

significance of the grain-boundary orientation illustrated in

Fig. 2.8. The cos( ) in (2.30), as well as the Zb(e) dependence, convey

this significance. If 0 > 00, then Zb < Z and the grain-houndary effect

is ameliorated. If e6 = 900 (grain boundary parallel to electron flow),
then Zh = 0 and the grain boundary does not affect the channel

conductance (although it may enhance source-drain leakage current via

other mechanisms).


2.5 Experimental Support and Discussion
To support the analysis in this chapter and to identify critical

aspects of it with regard to SOI device and integrated circuit design,

we measured linear-region In(VGf,VD,T) characteristics of four-terminal

SOI MOSFETs (n-channel) fabricated at Texas Instruments [LA83]. The

polysilicon film is 0.5 um thick and was laser-recrystallized after

being deposited via LPCVD on a 1-um-thick layer of silicon-dioxide,

which had been thermally grown on a silicon substrate. The film was

doped by ion implantation of boron that yielded NA= 2 x 1016 cm-3

near the front surface and NA~ 1015 cm-3 at the back surface [LAR31.













The front gate is n' polysilicon and Co = 5.8 x 10-8 F/cm2

(tof 600A). Large devices (Z = L = 40 um) were selected to preclude
small-geometry effects [AK82].

To avoid complications due to the charge coupling between the front

and hack gates [LI83b], a high negative voltage (- 40 V) was applied to

the back gate to ensure accumulation at the back Si-Si02 interface and

to fix VTf. The Io(VGf) dependence was measured with VD = 50 mV at

three temperatures (240 C, 70 C, and 1000 C).


2.5.1 Support for the Strong Inversion Analysis

The corresponding channel conductance characteristics g(VGf,T) of a

particular device, which typify the characteristics of identically

processed devices, are plotted in Fig. 2.9. The basic shape of these

plots is the same as that of the theoretical curves in Figs. 2.4

and 2.5, which implies qualitative support for our analysis. (The

experimental curves and Figs. 2.4 2.5 should not be compared

quantitatively because the parameter values used in the calculations are

not necessarily the actual values.)

The support for (2.20) is demonstrated by examination of the

measured g(VGf,T) characteristics within particular ranges of VGf. For
high VGf (> \ ), g is defined by the numerator of (2.20); the grain-

boundary effect is negligible. Thus as in the case of conventional

MOSFETs [SZ81, the carrier mobility (vng) follows from the slope of

g(VGf), i.e., from gm, and the threshold voltage (VTf) is given by the
























4 x 10-0 70C

100*C

3 x 10-5



2 x 10-5 0



10-5




0 0.5 1 1.5 2 2.5




Fig. 2.9 Measured linear-region channel conductance versus (front)
gate voltage of n-channel SOI MOSFET in laser-recrystallized
polysilicon [LA83] at three temperatures. The threshold
voltage is fixed by the back-gate voltage [LI83b], which was
set at -40V to ensure accumulation at the back Si-Si02
interface.













linear extrapolation of the characteristic to the VGf axis. From

Fig. 2.9 we thereby get VTf= 0.10 V and U =n 380 cm2/V-sec at 240 C.

This value of ng is low, and hence implies excessive scattering at the

polysilicon surface, due possibly to high Off [SU80]. The low Ung does

not reflect decreased transconductance due to a high surface electric

field [SU80], which we observed only at values of VGf higher than those

in Fig. 2.9. These interpretations are supported by the temperature

dependence of g in the high-VGf region. We see in Fig. 2.9 a weak

dependence of VTf on T and a negative temperature coefficient for png,

which are consistent with the g(T) characteristics of conventional

silicon MOSFETs [LE81; GA75].

We see from Fig. 2.9 that VTf is considerably less than the

electron mobility threshold voltage V Thus there is a significant

range of VGf (VTf < VGf < ) in which the grain boundaries suppress

Ip. In this case the YBo term in (2.20) is much greater than unity,

i.e., Vgb >> Vg, and hence g exp(-ctBo/kT). As long as VGf < VU, ?Bo

is high and does not vary significantly with VGf (see Fig. 2.3). The

positive temperature coefficient for g thus predicted is consistent with

the measured conductance plotted in Fig. 2.9 in this region.
When VGf > R, 'po decreases with increasing VGf (see Fig. 2.3),

and hence g increases. To analytically describe this increase and to

estimate V, we use the approximate YRo(n) dependence in (2.15) and the

strong-inversion relationship (2.21). The combination of (2.15),

(2.20), and (2.21) yields a g(VGf) characteristic that exhibits an

inflection point where gm is maximum. The theoretical and experimental












plots in Figs. 2.4, 2.5 and 2.9 imply that this maximum is broad.

Therefore we approximate the actual characteristic by the linear

function



9 n(eff)Cof(VGf V ) (2.31)


which is tangent to the actual g(VGf) curve at" the inflection point.

This function then analytically defines A and the effective field-

effect electron mobilitypin(eff) due to the grain boundaries.

The value of VGf at the inflection point is defined by equating to

zero the second derivative of (2.20) with respect to VGf, using (2.3),

(2.15), and (2.21). We find that at this value, the denominator of

(2.20) is two. Thus (2.31) describes the tangent to g(VGf) at the point

where the 'Ro term in the denominator of (2.20) is unity. This tangent
yields (for Ng >-1.) --1
3 2
q xi(eff)NST
8kTe C
V = Vf + s. ofTL (2.32)
2 + In f0.9A*TL
2 + ln
kNeng (N -1)

and


ng 2 + n 0.9A*TL (2.33)
n(eff) T {2 + n kNng(Ng-l) (2.33


We note that the weak dependence of xi(eff) on VGf has been ignored in
the derivation of (2.32) and (2.33). Thus Vu in (2.32) is evaluated by

assuming a representative value for xi(eff), which depends on NA as












discussed in Subsection 2.2.1. We stress that (2.32) and (2.33), which

are based on analytic simplifications of our more general analysis

described in Section 2.2, are merely estimates of V and un(eff)*

However they are useful in describing the functional dependence of g

and gm on device parameters and temperature, and hence will facilitate

SOI MOSFET design and computer-aided SOI circuit analysis.

We see from (2.33) that the effective electron mobility is

typically higher than Ung depending on L, Ng, and T. The measured

g(VGf) characteristics plotted in Fig. 2.9 when interpreted using (2.31)
yield n(eff) 530 cm2/V-sec at 240 C, which is considerably higher

than ung. The negative temperature coefficient for Un(eff) implied by

the data in Fig. 2.9 is consistent with (2.33), which shows that the

temperature dependence is defined primarily by that of upng Using the

measured value of n(eff) mentioned above and (2.33), we find that
N = 50 grains. Since L = 40 um, this implies a crude estimate of

about 1 um for the average grain size (yg), which is not unreasonable

for the laser-recrystallized polysilicon film [LA83]. We note finally
that the dependence of un(eff) on L suggested by (2.33) is consistent

with measurements [NG81] of (effective) electron mobility in laser-

recrystallized MOSFETs having different channel lengths. For a given

yg (=L/N with Ng > 1), un(eff) increases as L is reduced from many
times yg toward yg.

The electron mobility threshold voltage as described in (2.32) is

strongly dependent on NST and T, as well as on NA through VTf FLI83h]

and Xi(eff). The inverse dependence of Xi(eff) on NA described in













Subsection 2.2.1 implies that the difference between V and VTf

decreases as NA increases. The predicted direct dependence on NST is

consistent with observed decreases in.the (apparent) threshold voltage

of polysilicon MOSFETs resulting from hydrogenation [KA80], which is

known to reduce NST. The inverse dependence of V, on T suggested by

(2.32) is corroborated by the measured g(VGf,T) data plotted in

Fig. 2.9. At 240 C, the measurements when interpreted using (2.31)

imply V = 0.55 V, whereas VTf 0.10 V. The difference between Vp

and VTf, based on (2.32), indicates that NST 1 x 1012 cm2 (where the

traps are near midgap).

We conclude -this -subsection by -cstressing two significant

conclusions drawn from it. First, because (2.31), which is of the same

form as the linear-region conductance expression for the conventional

MOSFET [SZ81], empirically describes well an appreciable region of the

g(VGf) characteristic for the.SOI MOSFET, VI. and un(eff) can be easily

misinterpreted as VTf and ng. Such misinterpretations, which evidently

have been made in some previous work, can lead to misconceptions

regarding SOI and can impede the development of optimal SOI devices and

integrated circuits. Second, even though grain boundaries are effective

in defining the channel conductance of SOI MOSFETs, the transconductance

can be higher than that of the conventional counterpart; the grain

boundaries are actually beneficial in this regard. Thus perhaps optimal

designs of SOI MOSFETs may not require complete elimination of grain

boundaries.












?i5zt-ScQpport for the Moderate Inversion Analysis

S.In-subsection 2.5.1 we estimated, for a typical device, that the
thrIeShldt voTtage- defined by the linear extrapolation"of the measured

1g(VgY)'--wHdn the grain boundaries are insignificant (VGf >> V ) is

Vf = 0.1 V, and that the electron mobility defined by the slope of the
extrapolation is ng= 380 cm2/V-sec. From g(Vgf) that is affected by

theo grin boundaries (VGf > V ), we measured, based on our model,

V = 0.5 V, NST= 1012 cm-2 (for ET assumed to be at midgap), and
Ng -='50. Note that typically Vf = VTf + nkT/q with n = 3-5 depending

on NA and Cof [TS82b]. Thus our strong-inversion measurements imply
VTf=-9-, which is consistent with calculations based on (2.22),- (2.25).

We .stress-that the difference between VT and Vjf can be ignored for the

strnng-'inVersion analysis because (VGf VTf) >> kT/q.
"--T 4e~pTot in Fig. 2.6 the g(VGf) characteristic of a typical device

meIa.sured-:at. room temperature. Note especially the lower-VGf (<. V)
'...d- Ata, which show a nearly exponential dependence on VGf. For comparison

we also show in Fig. 2.6 theoretical g(VGf) curves that were numerically

derived from (2.20) and (2.22) (2.25) using the parameter values given
above and NA = 2 x 1016 cm"3. We varied ET and let Nsf = 0, which

-. f.rom.VTf =-) and (2.25) implies VFB = -1.9 V. The calculated g(VGf)

chaiaracteristics also are nearly exponential for low VGf, even though the

inversion level is not weak. (In weak inversion, the conductance of

single-crystal MOSFETs is exponentially dependent on the gate voltage

because 0n is [TS82b; SW72].) This dependence is due primarily to the

exp(qBo,/kT) term in (2.20) as implied by the strong dependence of S













(i.e.-, the inverse slope) on ET. As ET moves from midgap (= Ei) toward

the conduction band, S increases; when (ET-Ei) 0.2 eV, the measured S

is modeled Well. -Thus the energy level of the grain-boundary traps

significantly affects the channel conductance below the electron

mobility threshold (VGf < V )

We illustrate in Fig. 2.7 the effect of Nsf on the g(VGf)

characteristic. The theoretical curves plotted were derived using the

same parameter values for Fig. 2.6 and (ET-Ei) = 0.2 eV. For each value

of Nsf, VFB was calculated from (2.25) using VTf 0. Increasing Nsf

tends to suppress the conductance for intermediate values (~ V ) of VGf,

but does not significantly affect S. By comparing the calculated curves
11 2 1
with the measured data, we crudely estimate that Nsf 10 cm-eV .

Measurements at different temperatures (T = 24C, 700C, and 1000C)

indicate that, for intermediate VGf, both g(VGf) and S increase with

increasing T. As T increases from 24OC to 100oC, S increases from

0.25 V/decade to 0.34 V/decade and, at VG = V = 0.5 V, g increases
Gf V
from 1.3 x 10-6 u to 4.5 x 10-6 u These changes.are consistent with

(2.20) in which, for relatively low VGf, the exp(q~cB/kT) term defines

the predominant dependence on temperature.



2.6 Summary

A physical model that describes the effects of grain boundaries on

channel conductance in SOI MOSFETs has been developed and supported

experimentally. These effects originate when electrons (n-channel

MOSFET) are trapped at localized grain-boundary states, thereby creating













potential barriers that influence the flow of electrons from source to

drain. The electron trapping depends on the degree of inversion in the

channel and hence on the gate voltage. For sufficiently 'high VGf, "Bo

is low enough that the grain boundaries are inconsequential with regard

to g and gm. However for lower VGf, the grain boundaries can

predominantly control g and g, and can define: (a) an effective turn-on

(linear-region) characteristic that occurs well beyond the strong-

inversion threshold as illustrated in Figs. 2.4 and 2.5; and (b) a

nearly exponential dependence with gate voltage, as shown in Figs. 2.6

and 2.7, for moderate inversion conditions.

The effective turn-on characteristic, described generally by (2.20)

and approximated by (2.31), is actually a reflection of the "carrier

mobility turn-on", which is controlled by the grain boundaries. It

defines the electron mobility threshold voltage V which exceeds VTf,

and the effective electron mobility un(eff), which is-typically higher

than the actual (intragrain) mobility ung. Evidently measurements of V.

and "n(eff) have been previously misinterpreted as determinations of VTf.

and ng. Subsequent erroneous conclusions regarding SOI can inhibit the

development of optimal SOI devices and integrated circuits, which, based

on our analysis, possibly need not nor should not be completely void of

grain boundaries.

For moderate-inversion conditions, the drain current, which is

controlled by the grain boundaries, varies nearly exponentially with

gate voltage and the gate-voltage swing needed to reduce the drain

current by one order-of-magnitude depends strongly on the properties of













the grain boundaries, especially the grain-boundary trap level, and on

the properties of the Si-Si02 interface, i.e., the fast surface-state

density.

Grain boundaries perpendicular to the carrier flow in the channel

maximizes the grain-boundary effects on the conductance as described by

(2.30). In contrast, grain boundaries parallel to carrier flow in the

channel does not affect the conductance (although it may enhance source-

drain leakage current via other mechanisms).



















CHAPTER THREE
CURRENT-VOLTAGE CHARACTERISTICS OF
LARGE-GRAIN POLYSILICON MOSFETs



3.1 Introduction

In this. chapter, we describe extensions of our previous work that

yield a physical model for the steady-state current-voltage

characteristics of the large-grain polysilicon SOI MOSFETs in all

regions of operation. The essence of the extensions is an accounting

for sizable, position-dependent voltage drops across the grain

boundaries that can occur when the device is driven out of the linear

region. The carrier transport through the grain boundaries (viz., over

potential barriers created by carrier trapping) is then nonlinear, and

the channel conduction depends on how the grain boundaries are

distributed between the source and the drain. Although our model

accounts for any number of grain boundaries in the channel, we apply it

herein to the most likely case (in beam-recrystallized VLSI) of an SOI

MOSFET with only one grain boundary. We emphasize the importance of the

position of the grain boundary, as well as its electrical properties, in

defining the current-voltage characteristics.

As in the previous chapter, we assume that thermionic-emission

theory adequately describes the carrier transport over the grain-

boundary potential harriers. Unlike the previous chapter, the use of













the thermionic-emission theory is not well established because the

applied voltage to the grain boundary is much greater than 2kT/q. The

previous analyses [MU61; BA78b] of this problem for polysilicon

resistors are based on assumptions which are generally invalid, e.g.,

that a (constant) fraction of the thermionically emitted electrons are

captured by the grain boundary traps [MU61], or that the charge trapped

at the grain boundary is independent of the grain-boundary voltage drop

[RA78a]. The former assumption is invalid because the rate of the band-

to-trap recombination process is proportional [SZ81] to the

concentration of unoccupied traps and not to the current. The latter

assumption is -invalid because the charge trapped at the grain boundary

can be expressed (see Appendix A) in terms of the electron quasi-Fermi

level, and therefore, it depends on the grain-boundary voltage drop. We

avoid the use of these invalid assumptions by using the physically

reasonable approximation that the electron quasi-Fermi level is nearly

flat on the emitting side of the grain boundary.

These potential barriers, which result from trapped inversion-layer

charge, decrease with increasing inversion level, and hence are

modulated by the gate voltage and vary along the channel when the drain

voltage is high. Consequently grain boundaries near the drain, where

the inversion level is weakest, are most influential. To properly

account for the inversion-level dependence, we necessarily base our

analysis on a MOSFET model [RR78, 81] that is applicable for all

inversion levels.













Model calculations, supported by limited experimental results, show

that grain boundaries generally tend to decrease the conductance (drain

current) of SOI MOSFETs, but can increase the transconductance. Grain

boundaries having a trap density comparable to that (~1012 cm-2)

estimated for typical high-angle boundaries in beam-recrystallized SOI

can, when located near the drain, significantly affect the current-

voltage characteristics of the SOI MOSFET in all regions of operation.

The grain-boundary effect is enhanced as the channel length is

shortened.


S ,. 3.2 Analysis -- : .

We refer to the n-channel, enhancement-mode large-grain polysilicon

SOI MOSFET illustrated in Fig. 1.1. To emphasize the grain-boundary

effects, we assume that the polysilicon film' is not completely depleted

between the front and back surfaces so that charge-coupling effects

[LI83b] can be ignored (vis-a-vis, the back gate is inconsequential).

We initially assume that the (front) channel comprises Ng grains

separated by (Ng 1) identical grain boundaries (surfaces)

perpendicular to the carrier (electron) flow. Later we analyze the

likely case of a single grain boundary in the channel (Ng = 2),

emphasizing the importance of its position. The energy-band diagram at

the jth [1 < j < (N 1)] grain boundary, counted from source to drain,

is illustrated in Fig. 3.1 for the cases of zero drain voltage (VD) and

of VD > 0. When VD = 0, electrons trapped at localized grain-boundary

states produce the potential harrier ~Bo (at each grain boundary), which













q Bo
Ec-


E;-L --^







Sbj
Ec








E .
EFn 7


electron energy


JjL 4Bo


EFn


-jth grain
boundary


y
(a) VD=O


electron energy
~I ,


(b) VDO


Fig. 3.1 Energy-band diagram at jth grain boundary for drain voltage
equal to (a) and greater than (b) zero.







53




is determined by the inversion level, vis-a-vis, the. (front) gate

voltage VGf, as we described in the previous chapter. When VD > 0, a

voltage Vgbj is -dropped--across--the jth grain boundary, skewing the

energy-hand diagram as illustrated. If Vghj is large enough, it

produces significant changes in the (areal) density of charge OGRj

trapped at the grain boundary and in the inversion levels in the

adjacent grains.



3.2.1 Formalism

From Fig. 3.1, for VD > 0,


V 1 r .r 1 (3.1)
Vgbj =j Bj -B (3.1)


1 r
where' andi T are the potential barriers on the left and right sides

of the jth grain boundary, and and r are the electron quasi-Fermi
J J
potentials in the left and right adjacent grains. The average electron

densities in the adjacent inversion layers are



nj = n exp(qp /kT) (3.2)


-r = niexp(q /kT) (3.3)



where ni is the intrinsic carrier density in silicon. The densities in

(3.2) and (3.3) are related to the inversion layer (areal) charge

densities On on the left and right by (2.3).












The electron transport is controlled by the gate and drain voltages

through the dependence of On on VGf and VD. To characterize this

dependence, as well as the intragrain current, we use the charge-sheet

model [BR78, BR811, which is applicable for all levels of inversion. At

an arbitrary (intragrain) point y in the channel,


On(y) = Os(y) Ob(y) (3.4)


where


0(y) f + (-, )2exp -. sf(y) V(y)]]}1/2 (3.5)


is the charge density in the silicon and


f l (y) 1/2
S(y) -r- kT -1]/2 (3.6)


is the depletion-region charge density. In (3.5) and (3.6), sf is the
band bending (normal to the front surface), V is the difference between

the electron and hole quasi-Fermi potentials [V(O) = 0, V(L) = VD where

L is the channel length], and Or = [2kTEsNA11/2. The band bending is

related to VGf by


Os() = -CofVGf vB -V sf(y)] (3.7)













To complete the description of the energy-band diagram in Fig. 3.1,

we ensure that charge is conserved in the vicinity of the grain boundary



Gj -qs Bj 1/2 [2s rBj 1/2 (3.8)


which equates the charge trapped at the jth grain boundary to the

electron charge removed to form the adjacent depletion regions. (We

assume the regions are virtually depleted of free electrons.) Because

the inversion layer is void of holes, the electron capture and emission

rates for the grain-boundary traps must be equal in the steady state,

and hence OGj can be expressed in terms of the electron quasi-Fermi

level EFnj at the jth grain boundary (see Appendix A):


-qNST
GBj 1 e ET-EFnj (3.9)
1 + exp(- kT

In (3.9), (ET-EFnj) depends on Vgbj as suggested by Fig. 3.1. This

dependence is, in general, complicated and can be defined only when the

electron transport mechanisms) is specified. Although many theories

regarding carrier transport through grain boundaries have been purported

(e.g., thermionic emission, diffusion, thermionic field emission), none

can be verified unequivocally because of the complex, variable nature of

the grain boundaries. Thus to avoid undue model complexity, we assume,

as in the previous chapter, that the predominant transport mechanism is

thermionic emission over the potential barrier. This simplifying

assumption is physically reasonable at and above room temperature where













thermionic field emission is not probable, and for substantial

nontriviall) barrier heights, which render diffusion less significant.

The thermionic-emission model, which in fact has functional dependence

similar to the diffusion model, is further consistent with the depletion

approximation, and hence with it yields insightful results commensurate

with the uncertain nature of the grain boundaries.

Referring to Fig. 3.1, we note that if there is a net left-to-right

transport of electrons predominantly by thermionic emission, then EFn

can be assumed to be nearly flat on the left side of the grain boundary;

Vgbj is dropped predominantly on the right side where the (net) emitted

electrons drift away from the grain boundary. Thus in (3.9), ,



(ET nj) (E) + 1 (3.10)


where (ET-Ei) gives generally the position of the traps in the energy

gap. We stress that dEFn/dy at the grain boundary is not related to the

current because of the assumptions that the carrier transport is

described by thermionic emission theory and not by diffusion theory.

We have now described, in (3.1) (3.10), how the energy-band

diagram at a grain boundary changes to reflect the voltage drop Vgbj.

By using physically reasonable approximations, we have avoided the use

of a classical, but generally invalid assumption [MU61] that a

(constant) fraction of the thermionically emitted electrons are captured

by the grain-boundary traps. This commonly used assumption in fact

overly defines the grain-boundary transport problem because the rate of












the-b-and--to-trap recombination process is proportional [SZ81] to the

concentration of unoccupied traps and not to the current. We have

furthermore not used another common assumption [BA78a] that GBj, is

independent of Vgbj, which is also generally invalid as indicated by


Our model for the steady-state current-voltage characteristics of

the large-grain polysilicon MOSFET is completed by: (a) equating the

drain current ID to the net thermionic-emission current defined by the

perturbed energy-band diagram at each grain boundary; (b) equating In to

the current defined by the charge-sheet model [BR78] applied to each

orat-ecadr.c) summing all the grain-boundary and grain voltage drops to
VDP

The net thermionic-emission current density over the potential
barrier at the jth grain boundary (Fig. 3.1) is [BA78b]

1 r
*T2 1 q
-A*gbj exp(- 8-j) rexp(- -r ) (3.11)
gbj N [ kT kT


where A* is the effective Richardson constant for electrons in silicon

(. 250 A/cm2-K2) and NC is the effective density of states in the
----conduction-band (= 2.9 x 1019 cm3 at 3000K). Thus for all j,


II = ZXi(eff)Jgbj (3.12)


where Z is the channel width. We assume Xi(eff) (100 A) is constant,

independent of position and bias; n reflects changes in the local












channel conductivity. With (2.3) and (3.1) (3.10), (3.11) and (3.12)
relate ID to Vgbj for the (Ng 1) grain boundaries.
Using the charge-sheet model [BR78], we now express ID as a
function of the band bending at the left and right sides of each
grain. For the kth (1< k< N ) grain with length ygk (L = ygl +
-- + YgN9g)


I = n Co{ [ + -T(V V )](\r 1 q r 2
D Ygk q of kTGf FB sfk -sfk 2 kT sfk



1 2 2(q)3/2r sfk 3/2 1 sfk3 (3.13)
f k)- 777 (sfk)w (3.13)
of



+ ( q)1/2 [r 1/2 -2 )1/2
kT C sfk sfk
of

where ung is the electron mobility in the intragrain channel. The
combination of (3.5), (3.7), and (3.13) gives ID as a function of the
voltage drop Vk = Vr V (the variation in V) along the channel in the
gk k k
kth grain. Since V = Vr + Vg(jk) for 2 < k < N and V = 0 and
k k-i gh(j=k-1) f 1
Vr = VD, we have related ID to Vgk for all the Ng grains.
g
The final relationship needed to define ID(VD,VGf) is

(N -1) N
VDg Vj k (3.14)
Sj=1 gbj k=l gk (3.14)













3.2.2 Numerical Solution

The current-voltage characteristic is evaluated numerically by

solving simultaneously the nonlinear system of equations described by

(2.3) and (3.1) (3.14), for all j and k. Instead of solving directly

this nonlinear system of equations, we obtain the solutions by first

assigning values for ID and VGf, and then calculating the corresponding

value of VD. The advantage of this method is that we avoid the typical

convergence problems of the iterative methods [BU81] for. solving

nonlinear system of equations because we only solve many nonlinear

independent equations with one variable.

To illustrate the predictions of our model, we apply it to a

typical (but thick) SOI MOSFET for which N = 1016 cm3, Cof = 5.8 x

10-8 F/cm2 (the gate oxide thickness is 600 A), Z = L = 40 um, and ng =

700 cm2/V-sec. To emphasize the most likely case (in beam-

r.ecrystallized SOI VLSI), we let Ng = 2 (one grain boundary). We plot
in Fig. 3.2, for NST = 1012 cm-2, ET = Ei (traps at midgap), and ygl =

Yg2 = L/2 (grain boundary at middle of channel), the calculated Ir(VD)
characteristics for several values of (VGf VTf); the threshold voltage

VTf is the value of VGf yielded by (3.5) and (3.7) when Ysf(V = 0) is
f
twice the Fermi potential of the silicon film body. We note that VFB

does not need to be specified because it is related to VTf through (3.5)

and (3.7) evaluated at y=0. For comparison we also plot (dashed curves)

corresponding characteristics for Ng = 1 (no grain boundary). The grain

boundary reduces ID; as in the linear region (see Chapter Two), its

effect is most significant at low VGf. In the saturation region,







60








25
Ng=2 /
N92 L VG -VT = 1.5 V
Y91 2 2 /
NST=1012 -2 /
Z=L=40 .m /
20- I/ .- .






/


5 // /

10-
1.0 V





5- -
5 / ~75 V



.5 V
0 .5 1.0 1.5
VD (V)
Fig. 3.2 Calculated current-voltage characteristics (solid curves) for
typical large-grain polysilicon SOI MOSFET with one grain
boundary at middle of channel. Without the grain boundary,
the dashed curves derive.













ID(sat) can be substantially limited, although VD(sat) is virtually
unaffected since V(y=L) always equals the drain voltage.

The grain-boundary effect is strongly dependent on NST. To

illustrate this dependence, we plot in Fig. 3.3 the square-root of

ID(sat) versus (VGf VTf) for NST ranging from 0 (no grain boundary) to
2 x 1012 cm-2. As NST increases, the grain-boundary potential barrier

increases, and hence a larger part of VD(sat) must be dropped across the

boundary to enable ID(sat) to flow through it. For NST high, ID(sat) is

reduced considerably even for VGf high.

Because the grain-boundary potential barrier increases as the

adjacent intragrain inversion level decreases, the effect of the grain

boundary will, for VD > 0, be stronger if the boundary is closer to the

drain. To emphasize this important position dependence, we show in

Fig. 3.4 how the calculated ID(sat)(VGf) characteristic is altered as

the grain boundary, with NST = 1.2 x 1012 cm-2, is shifted toward the

drain. Since Qn ~ 0 near the saturated drain, a grain boundary there is

influential regardless of how high VGf is. A grain boundary near the

source however is significant only for VGf low. We also see in Fig. 3.4

that the position of the grain boundary is irrelevant for (VGf VTf)

< .6 V because the inversion level remains nearly constant along the

channel for this low VGf.

The grain-boundary effect illustrated in Figs. 3.2 3.4 is

enhanced as the channel length is shortened. This enhancement is

demonstrated in Fig. 3.5 where we plot the calculated In(sat)(VGf)

characteristic for different L with Z/L = 1 and yg2 = L/4. The






62








6

Ng=2

2Yg91 Y 2
Z=L=40in

4-




1.5x1012 -


2- 1012 cmr2
8x 1011 cmm2
N =0
ST /

12 -2
/ xO 2x10 cm

0
0 .5 1.0 1.5

VGf- VTf (V)






Fig. 3.3 Calculated dependence of drain saturation current, versus
gate voltage, on grain-boundary (at middle of channel) trap
density.






63







6 I /

Ng =2 /
NST=1.2 x 1012cm2
Z=L= 40j.m //


4




no grain / 20 jLm
boundary /
2 /1' .m

/ yg2=1 p.m





0 .5 1.0 1.5

VGf-VTf (V)






Fig. 3.4 Calculated dependence of drain saturation current, versus
gate voltage, on grain-boundary position along channel.






64











Ng=2
2 4 12 -2
Yg2 / /
NST=1.2 x 10 cm /

=1 //
S4- /





/ / 1001m
no grain // /
2 boundary / /40 J.m


S// L=10 pm


.lI I

O0 .5 1.0 1.5

VG-VTf (V)





Fig. 3.5 Calculated dependence of drain saturation current, versus
gate voltage, on channel length with grain boundary L/4 from
drain.













reduction in current with decreasing channel length results because the

constraint on ID defined by (3.11) and (3.12) is independent of L, and

hence Vgb must increase to support higher current densities in the

channel.

To further stress the significance of grain boundaries in large-

grain polysilicon SOI MOSFETs, we plot in Fig. 3.6 the calculated

transconductance in the saturation region, gm(sat) a ID(sat)/VGf, for

one grain boundary in the middle of the channel having different values

of NST. Depending on VGf, gm(sat) can be lower or higher than that for

the grain-boundary-free (NST = 0) counterpart. At low VGf, below the

"mobility threshold" (VY) the grain boundary virtually inhibits current;

thus gm(sat) ~ 0. As VGf increases, the grain-boundary effect is

diminished as the intragrain channel conductance is enhanced, thereby

producing unusually high transconductance (like in the linear region

analysis of Chapter Two). At high VGf, the grain-boundary effect tends

to subside, and gm(sat) approaches that corresponding to NST = 0.


3.3 Experimental Support and Discussion

To provide experimental support for the analysis, we measured

current-voltage characteristics of large-grain polysilicon SOI MOSFETs

described in Section 2.5.

We find that the measured ID(sat) is smaller than that of the

theoretical calculations of the corresponding single-crystal counterpart

(NG = 1), and that this relative difference increases as VGf
decreases. This result implies qualitative support for our analysis.




























E

20- 1.2x1012 cm2

10 cm
8x1011 cm-2 1.5x1012cm-y .

NS ,- 2 xl012 crr2
01 -- I I
0 .5 1.0 1.5
VGf-VTf (V)






Fig. 3.6 Calculated saturation-region transconductance versus gate
voltage and grain-boundary (at middle of channel) trap
density.













Unfortunately, quantitative support is not obtained because Ng is not

known exactly.

Additional support for our analyses has been presented by Colinge

et al. [C083], who developed a technique to control the location of the

grain boundaries in SOI MOSFETs. They fabricated two transistors with

the same geometry, one beside the other, one of them with a

perpendicular grain boundary at the middle of the channel, and the other

without grain boundary. They found that ID(sat) for the transistor with

a grain boundary is smaller than that of the transistor without a grain

boundary.

We conclude this section by stressing three significant;conclusions

drawn from this analysis. First, because the ID(VD) characteristics of

SOI MOSFETs resemble that of the single crystal counterpart, the device

parameters can be easily misinterpreted by using direct MOSFETs

theory. Such misinterpretations, which evidently have been made in some

previous work, can lead to misconceptions regarding SOI and can impede

the development of optimal SOI devices and integrated circuits. Second,

because of the variation in the degree of inversion along the channel

produced by VD, a grain boundary close to drain affects IDsat even at
sat
high VGf. Third, because part of V (sat) is dropped across the grain

boundaries, I (sat) is reduced.



3.4 Summary

Using simplifying, but physically reasonable assumptions, we have

modeled the effects of grain boundaries on the steady-state current-













voltage characteristics of large-grain polysilicon SOI MOSFETs. We have

assumed that the predominant transport mechanism is thermionic emission

over the potential barrier,and we have avoided the use of previous

generally invalid assumptions [MU61; BA78a]. The complexity of the

model is commensurate with the uncertain and variable nature of the

grain boundaries, but its predictions are in general accord with

experimental results. Basically the model shows that grain boundaries

tend to reduce the MOSFET conductance (ID), but can increase or decrease

the transconductance. Although the grain-boundary effects are most

apparent at low gate voltages, they can be quite significant at higher

gate voltages :when the drain voltage-is high, e.g., in the saturation

region. Grain boundaries close to the drain are most effective. The

effects are enhanced as the channel length is shortened.

We have measured current-voltage characteristics of both [LA83]

laser- (Ng >> 1) and graphite-strip-heater- (Ng 2) recrystallized SOI

MOSFETs, and have found general agreement with the model predictions.

Because Ng is not known exactly, it is difficult to make more

quantitative comparisons.

A main conclusion of our work is that a single grain boundary in

the channel can significantly affect the electrical properties of an SOI

MOSFET. Thus although the grain size of beam-recrystallized SOI is

large, the grain boundaries, with randomly varying properties, can pose

problems regarding yield, reproducibility, and reliability of SOI VLSI

that cannot be ignored.



















CHAPTER FOUR
ANOMALOUS LEAKAGE CURRENT OF SMALL-GRAIN
POLYSILICON MOSFETs


4.1 Introduction

Recent laboratory achievements [MA84; MA85] imply that the first

commercial adaptation of three-dimensional integration may be stacked

CMOS VLSI memory chips in which one of the complementary transistors

(usually p-channel) is fabricated in a- layer of LPCVD polysilicon on

silicon dioxide. Grain-boundary passivation (e.g., via hydrogenation

[SH84]) is required to render the polysilicon MOSFET performance

acceptable for the circuit application, although single-crystal silicon

device characteristics are not needed. The polysilicon transistor is

inferior to the single-crystal counterpart, especially because of

anomalous high leakage current and exceptionally high gate-voltage swing

[0N82; SH84].

In this chapter we model the OFF-state leakage current of the

small-grain polysilicon SOI MOSFET, which we theorize is controlled by

grain-boundary traps. By qualitative deduction, we identify a plausible

physical mechanism underlying the leakage current, and then show that it

is consistent with the anomalously strong dependence on the gate and

drain voltages that have been observed [0N82; SH84; MA85]. Such

physical insight can aid the design of polysilicon MOSFETs to control

and minimize the leakage.













A typical set of measured current-voltage characteristics of an

unpassivated LPCVD polysilicon MOSFET is shown in Fig. 4.1. The

particular device is p-channel and operates in the accumulation mode.

The back gate and the source are grounded. In the OFF state (front-gate

voltage VGf> 0), the film body (grains) is completely depleted of free

carriers, facilitated by grain-boundary trapping of holes. The front

surface is inverted for VGf sufficiently high (> ~0), facilitated by

positive charge at the interface. The leakage current (IL = ID in the

OFF region) increases exponentially with VGf and as a power (> 1) of the

drain voltage VD. The device characterized in Fig. 4.1 is long-channel

(32 1m), which means that the anomalous IL(Vf,VD) is not a short-

channel effect [AK82]. Other measurements [MA85] reveal that IL is

virtually independent of the (long) channel length, and that the same

anomalies obtain for other polysilicon MOSFET structures, e.g., the

n-channel inversion-mode device. Passivation of the grain boundaries in

hydrogen plasma [SH84] reduces IL by two or three orders of magnitude,

but does not remove the strong dependence on VGf and VD.

To physically model IL, we first deduce the most plausible

mechanism producing the leakage by qualitatively eliminating the

possibilities of other significant mechanisms. Although this deduction

is not rigorous, we support the model by demonstrating correlation

between its IL(VGf,VD) predictions and measured data. A rigorous

corroboration, which would require comprehensive analyses of all the

possible mechanisms and extensive measurements of special test

structures, is not feasible.












10701 T I i 1 1 I I I 1


10


Q


10-


-- V -,15-8. V05
8 VD











-0.05 V

12 ---


-5.0


5.0


VGf (V)

Fig. 4.1 Measured current-voltage characteristics of an unpassivated
LPCVD polysilicon MOSFET (p-channel, accumul ion-mode; Z =
128 pm, L = 32 im, tf = 500 A, NA = 101 cm- ). The
polysilicon film is 0.1% pm-thick and was deposited via LPCVD
on a 0.5 pm-thick layer of silicon-dioxide. The back gate
and the source are grounded.


10-













Possibly significant leakage mechanisms in the polysilicon MOSFET

are: (a) space-charge-limited flow [RI73; SC82] of holes from source to

drain through the (depleted) film body; (b) thermal emission of carriers

[SZ81], via grain-boundary traps, in the depletion region near the

drain; (c) field-enhanced (Poole-Frenkel [GR82]) thermal emission in the

drain depletion region; (d) impact ionization (avalanching) [DU78] in

the drain depletion region; (e) band-band field emission (tunneling)

[R173] in the drain depletion region; and (f) field emission via grain-

boundary traps [GR84], or possibly metal precipitates [LEF82], in the

drain depletion region. The measured independence of IL on (long)

channel length [MA85] rules out space-charge-limited flow.- The strong

observed dependence of IL on VGf and VD imply that thermal-emission

current, which depends only weakly on VD, is not significant. The

observed saturation of IL with increasing VGf in Fig. 4.1 is

inconsistent with predominant Poole-Frenkel emission or avalanching.

Furthermore the electric field in the drain depletion region, for the

values of VGf and VD used in the measurements (Fig. 4.1), is not high

enough to produce significant avalanching or band-band tunneling. We

are thus left with field emission through grain-boundary traps, or metal

precipitates, as the most plausible mechanism underlying the observed

IL(VGf,VD). The strong dependence on VGf further implies that the
predominant field emission occurs near the front surface, in fact

between the p+ drain and the n inversion layer where the electric field

is highest. If the hack surface is inverted, significant field emission

can occur there also.













Our analysis of the field emission emphasizes grain-boundary traps,

not metal precipitates, for two main reasons. First, neutron activation

analyses [SH85] of the LPCVD polysilicon reveal concentrations

(< 1013 cm-3) of metallic impurities comparable to those in bulk silicon

and much lower than the grain-boundary trap density. Second, the grain

boundaries getter metallic impurities, which tends to prevent the

formation of metal precipitates.

In the next section, we develop an analytic model for the trap-

assisted field-emission current in the LPCVD polysilicon MOSFET. To

support the model, we compare its predictions of IL(VGf,VD) with

measured data !from p-channel accumulation-mode and n-channel inversion-

mode devices. Good correlation is shown, and field emission at the back

surface is suggested as the mechanism underlying the minimization of the

leakage current at relatively low values of VGf like that illustrated in

Fig. 4.1. Insight regarding the physics underlying the anomalously

strong IL(VGf,VD) dependence is readily provided by the model, and

implies design criteria to control IL in polysilicon MOSFETs.



4.2 Leakage Current Model

To develop a physical model for the leakage current in the LPCVD

polysilicon MOSFET, we consider the p-channel accumulation-mode device,

the basic structure of which is illustrated in Fig. 1.2. The leakage

current in other polysilicon devices, e.g., the inversion-mode MOSFET

[0N82], can be described basically by the same model as we discuss

later. The accumulation-mode device is of interest because it can be













designed to have reasonably low threshold voltages [SH84; MA85]. Such

design depends on the complete depletion of the small (~ 1000 A) grains

in the body via carrier trapping at localized grain-boundary states

[BA78a; SH84]. The OFF state of the device then obtains in the absence

of an accumulation layer under the gate; the surface is either depleted

or inverted. Our model is based on the latter, more prevalent surface

condition, and hence describes the anomalous strong dependence of the

leakage current on the gate and drain voltages [0N82; SH84].

As discussed in Section 4.1, the leakage current is assumed to

originate via field emission through grain-boundary traps (bound states)

at the drain junction.. Because of: the complete depletion of the body,

this emission occurs predominantly at the surface under the gate in the

depletion region between the p+ drain and n inversion layer. This

conclusion is consistent with the observed strong dependence of the

leakage current on the gate voltage. Although band-band tunneling in

this surface region would occur only at very high electric fields

[RI73], substantial field emission can occur at low fields because of

the high density of grain boundary traps in the LPCVD polysilicon. To

enable an analytic description of this emission, we assume that the

traps are monoenergetic (at ET in the energy gap) and uniformly

distributed in space [KA72; DE80; DE84] (with trap density NT = 2NST/dG

where NST is the grain-boundary areal trap density and dG is the average

columnar grain size).

The critical region of the device described above is illustrated in

Fig. 4.2. It is the depletion region near the surface between the p+















Polysillcon Gate

-nr-^:


K

XFO


Fig. 4.2 Critical depletion region between the
layer with important electric field
(4.13) indicated.


drain and the inversion
components in (4.11)-













drain and the n inversion layer. Because of the lateral diffusion of

the drain under the gate, the inversion extends into the drain region

with complicated geometry. Thus the effective cross-sectional area of

the n-p+ junction is difficult to define. The electric field in this

region, which governs the field emission, is two-dimensional

[FR69; TE84] (for wide channels) depending on both the gate and drain

voltages, VGf and VD. Following a previous analysis [FR69] of the bulk

MOSFET in the saturation region, we will treat this complex two-

dimensional problem empirically, which enables us to model the field

emission processes as occurring predominantly parallel to the surface

(in the y-direction). This simplification is commensurate with device

ambiguities, yet yields a model that is consistent with experimental

results and hence is insightful.

The energy-band diagram in the region, including the grain-boundary

trap level, is sketched (versus y) in Fig. 4.3. Maintaining the degree

of complexity implied above, we assume that the electric field in the

y-direction, Fy = (dEi/dy)/q, is constant in the depletion (barrier)

region, and that the electrons (or holes) tunnel through the barrier via

the traps at constant energy [GA70; R077].

The leakage current derives then from the combined net field

emission of holes, ITV, from the traps to the valence band in the drain

region, and of electrons, ITC, from the traps to the conduction band in

the inversion region. For traps within an incremental width (dy) of the

depletion region (see Fig. 4.3) [GA70; R077; GR84],





















Electron
Energy


y


Ecp


ET



EV
EF


vii I W I
i I

y(Ecn) Y(Evp)





Fig. 4.3 Electron energy-band diagram along the surface between the
(n) inversion layer and the (p+) drain.













q(l fT)NTZx dy
dTV T TV4.1)


and


qfTNTZxe dy
d(-ITc) : (4.2)
TC T TC

the rates of the respective inverse processes are negligibly small for
the nonequilibrium conditions of interest (e.g., IVD >> kT/q). In

(4.1) and (4.2), Z is the channel width of the MOSFET, xe is an

effective depth of the junction region (see Fig. :4.2), fT is the

electron occupancy factor of the traps, and TTV and TTC are the time

constants for hole and electron tunneling respectively, which depend
on Fy and ET as we discuss later.
In the steady state, the number of trapped electrons is constant,

and hence in the absence of significant thermal emission, dlTV
d(-ITC). Equating (4.1) and (4.2) then, we have


TTC
f T TC (4.3)
T T TC TV

The incremetal field-emission current is given by the combination of

(4.1) or (4.2) with (4.3). The total (leakage) current is then

expressed by integrating the result over that portion of the depletion
region across which valence band-trap-conduction band carrier

transitions at constant energy are possible (see Fig. 4.3):













Y(Ev)
L = qZx N f y(E dy (4.4)
Sy(ECn) TC +TV


Since we assume that F is constant in the depletion region,


D EVp ECn
Fy W- qLy(EVp) Y(ECn) (4.5)


where D is the potential barrier height and. W is the width. The
tunneling time constants are thus independent of y also, and (4.4) can
be written as

S E E
IL- ZxeNT +T- F ) (4.6)
TC TV y

Because the leakage current is low, little voltage is dropped
across the inversion layer; VD is dropped across the drain depletion
region as indicated in Fig. 4.3:


EFp EFn qVDIv (4.7)


For JVDI greater than a few tenths of a volt then, we note that the
quasi-Fermi level separation in (4.7) equals approximately (Evp ECn)
in (4.6). Thus


L qZxeNT( ) (4.8)
TC TV y













The time constants TTC and TTV reflect the probability per unit

time that a trapped carrier will tunnel through a triangular barrier,

defined by ET as shown in Fig. 4.3, to its respective band. Based on

the WKB approximation [R077; SZ81; GR84],

1/2 3/2
4(2m )/2(ET E)
TTV OVexp[ 3qhFy ] (4.9)




and


4(2m ) (EC ET3/2
TTC= TOCexp[ 3qhF ] (4.10)


*
where mp and mn are the appropriate [LU72; GR841 effective masses for
*
the tunneling holes and electrons (m = mn = 0.2 m0 [GR84] where mo is

the free electron mass), and where TOV.and TOC are effective carrier

transit times in the valence and conduction bands, which we assume to be

constants [LU72]. For a parabolic barrier [R077; SZ81], the numerical

constant in the exponential argument is different (lower). The effect

of the barrier shape on IL can thus be studied by varying the effective

masses in (4.9) and (4.10), which in fact cannot be unequivocally

defined [LU72; GR84].

We stress that the field-emission current IL in (4.8) is

predominant because of the high density NT of traps that increase

substantially the tunneling probability, conveyed by (4.9) and (4.10),

over that for band-band tunneling [SZ81]. To complete the model for IL













defined by (4.8)-(4.10), we must describe F in terms of VGf and VD. As

discussed with reference to Fig. 4.2, the electric field in the

depletion region at the surface, and indeed the two-dimensional region

itself are virtually impossible to describe analytically. However an

empirical description, commensurate with our one-dimensional field-

emission model, can be given based on a previous analysis [FR69] of the

bulk MOSFET in the saturation region.

With reference to Fig. 4.2 three "components" of Fy can be

identified [FR69]:


Fy = F 1 F2 + F3 F (4.11)



In the empirical representation (4.11), F1 is the electric field that

exists in the absence of the gate; i.e., F1 is due to the depletion

charge in the reverse-biased drain junction. The presence of the gate

produces fringing electric fields F2 and F3: F2 is due to the gate-drain

potential drop and F3 is due to the potential difference between the

drain end of the inversion layer and the gate. Following [FR69], which

has been supported experimentally. [BR81], we assume that F2 and F3 are

proportional to the respective normal electric fields at the surface

(see Fig. 4.2):


F2 = aFD (4.12)
2 S













F3 = (4.13)


where and 8 are constant "field-fringing factors".

At the p+ drain side of the depletion region, the surface potential

is nearly zero, and


SCf +
FD = Gf -+D S + (4.14)
s of


where Cof is the .(front) gate oxide capacitance, Off is the fixed charge
+
density at the (front) Si-SiO2 interface, and MS is the gate-p

silicon work function difference. For an n+ polysilicon 'gate,
+
MpS = -E /q where Eg is the silicon energy gap. At the inversion-layer
side of the depletion region,


F 1s (VGf + off ) (4.15)
S s (VGf MS of q


since the potential drop between the end of the (strong) inversion layer

and the source region (VS = 0) is about Eg/q.

Using the one-dimensional analysis of the reverse-biased p-n

junction [SZ81], we express



F1 ] 1/2 (4.16)


as an average value of the y-dependent electric field in the depletion

region between the p+ drain and the n inversion layer. In (4.16), n is

defined by (2.3) and (2.21),














~ of i
n (VGf VTf) (4.17)
xi (eff)


where Xi(eff) is the inversion layer thickness (~ 100 A) defined in

Section 2.2.1 and VTf is the strong-inversion threshold voltage of the
MOS structure, the characterization of which depends not only on the

structural properties but also on the polysilicon film properties, e.g.,

NST, ET, and dG [KA72]. The potential barrier height is defined by VD and the surface potential in the inversion layer. For

strong inversion,


E
Sn q IVDI (4.18)


The combination of (4.8)-(4.18) gives an analytic description of IL
and its dependence on VGf and VD for the p-channel accumulation-mode

polysilicon MOSFET. The control of IL by the grain boundaries is

conveyed by NT (= 2NST/dG) and ET (relative to the band edges) in the
*i +
model. The parameters Cof, VTf, MS' Qff, and xi(eff) are defined by

the MOSFET structure, or can be estimated. The field-fringing factors a

and 8, and xe must be estimated or evaluated through comparisons of

model predictions and measured data; they control the relative

significance of VGf and VD in determining IL. The transit times TOV and
TOC associated with the field emission are in effect normalization

factors for the tunneling time constants; they have been characterized

from first principles [LU72], although not accurately. The model













therefore actually predicts the normalized IL(VGf,VD) dependence;

absolute measured values however could be matched by assigning proper

values to r OV andr OC.

The model does indeed predict the general IL(VGf,VD) dependence

exemplified in Fig. 4.1. To demonstrate this correlation and to

indicate the physical insight afforded, we plot in Fig. 4.4 the

calculated leakage current versus VGf and VD for a device similar to the

one measured. Quantitative comparisons of the theoretical and

experimental characteristics should not be made because actual values of

many of the model parameters are unknown. In the calculations, we used

Z = 128 um (L is irrelevant) and Cof = 6.9 x 10-8 F/cm2 (= Eof/tof with

tox = 500 A) corresponding to the device measured. We chose xe = 500 A,

greater than xi(eff) but less than the extent of the lateral drain

diffusion, and a = 0.2 and 8 = 0.6, crude values based on the bulk

MOSFET model [FR69]. We let TOV = TOC '0 = 10-12 sec, a crude

estimate derived experimentally [GR84], and NT = 2 x 1017 cm-3, which

corresponds to NST = 1012 cm"2 and dG = 1000 A. We put ET at midgap.
We characterized VTf = VTO Qff/Cof with ff/q = 1012 cm2 and VTO = 0
i 1
V, which yield VTf -2 V. [We stress that VTf is the strong-inversion

threshold voltage, in contrast to the turn-ON threshold voltage (for

strong accumulation), which is about -4 V as indicated in Fig. 4.1.]

From (4.6) we note that IL is directly proportional to the factor

ZxeNT/ O, and hence changes in these parameters simply alter the

magnitude of IL and not shape of the semi-logarithmic IL(VGf,VD)

characteristics in Fig. 4.4. Additional calculations show also that the



























101








-4-I
10-10



10 8 6 4 2 0
VG, (V)












Fig. 4.4 Calculated leakage current versus (front) gate and drain
voltages for a p-channel accumulation-mode LPCVD polysilicon
MOSFET.













shape of IL(VGf) is not strongly dependent on a and B. Variations in

the oxide capacitance Cof, however, produce significant changes in

IL(VGf), primarily because of its influence on F1 described by (4.16)
and (4.17). Similar changes are produced by variations in VTf, or VTO

as shown by the calculations plotted in Fig. 4.5. The leakage is most

sensitive to VGf just above threshold for strong inversion; well above

threshold (high VGf), Fy in (4.11) is high and the tunneling time

constants TTV and TTC in (4.9) and (4.10) tend toward minimum values

(TO), thereby causing IL to approach a value independent of VGf.

The calculated dependence of IL on the trap level ET is illustrated
in Fig. 4.6.- As-can be inferred from (4.9) and (4.10), traps near

midgap are most effective in the field-emission processes; shallow traps

do not facilitate carrier tunneling to the opposite band. We note that

ET could possibly be inferred from measurements of the slope of the

IL(VGf) characteristic.
Although the model predictions can be brought into close agreement

with the measured leakage current by altering parameter values, the

benefit of doing so is questionable because of the uncertainty in the

actual physical structure and parameters of the device. For example,

variations in the shape of the potential barrier in the drain depletion

region, and/or in the effective masses in (4.9) and (4.10) can result in

considerable changes in the predicted IL(VGf,VD) characteristics. Such

changes are illustrated in Fig. 4.7 where we plot the calculated
*
IL(VGf,VD) with mp = mn varying from 0.1 mo to 0.5 mo. We note
however from the calculations plotted in Figs. 4.4-4.7 that the measured


















i "


.--14


1U0
10
I I i q; ,. i r- n -a el


0


VGf (V)


Fig. 4.5 Calculated variation of IL(VGf) for different (strong-
inversion) threshold voltages Vf = VTO Off/Cof (with
Off/Cof = 2.3 V).


10-6


VO-3V






7Q.
3V
VD=-5V


I I i


-1010
10-1


0






88















10-6 (Ec-ET)= Eg/2


3 E9/3 or 2Eg/3

10
Eg/5 or 4Eg/5

VD=-5V

10-14 1 1 1 1 1 1 1 1 1
1 10 8 6 4 2 0

VGf (V)















Fig. 4.6 Calculated dependence of IL(VGf) on the grain-boundary trap
energy level ET.



































1o-14
1


VGf (V)


Fig. 4.7 Calculated dependence of
effective masses mp = mn


IL(VGf) on tunneling carrier


10-6





10-10


-J













IL(VGf,VD) characteristics in Fig. 4.1 could be simulated well by the
model with physically reasonable parameter values.

The plots in Figs. 4.4-4.7, as well as the data in Fig. 4.1 which

indeed reflect the general IL(VGf,VD) dependence seen in a variety of
LPCVD polysilicon MOSFETs, show that IL varies predominantly

exponentially with VGf (> VTf) for a given value of VD. This dependence

results from the exponential dependence of TTV and TTC on Fy expressed

in (4.9) and (4.10). The dependence- of IL on VD is also strong, as

emphasized by the calculations of Fig. 4.4 replotted in Fig. 4.8. For a

given value of VGf (> VT), IL varies as IVDIm where m ~- 1-10. This

dependence follows from (4.8) and the implicit dependence on VD of Fy

and TTC and TTV. Note that m decreases with increasing VGf and IVf).

The predicted m vs. VGf variation can be seen in the measured data in

Fig. 4.1, although the m vs. IVDI variation cannot. This discrepancy

appears to be due to (trap-assisted) avalanching in the drain depletion

region that causes the measured leakage current to increase abruptly as

IVDI approaches ~10 V. We note further that the measured m (1-5) for
all the devices is lower than that calculated, which could indicate that

the effective masses in (4.9) and (4.10) are lower than 0.2 mo as we

assumed, or that the potential barrier is more parabolic than linear.

Additional calculations reveal that the effective masses must be reduced

by about an order of magnitude to bring m down to the measured value.

Then to retain theoretical-experimental agreement for the absolute value

of IL, the effective carrier transit times in (4.9) and (4.10) must be

reduced by three to four orders of magnitude. Higher values of a and

lower values of a also weaken the dependence of IL on Vn.























10' -

VGf =10V


10-11
OV


-15 1
10 3
3I
-VD (V)














Fig. 4.8 Calculated I (VGf,Vn) characteristics
dependence on drain voltage Vh.


emphasizing


-J


10
















the













Additional support for the field-emission model for IL is obtained

from consideration of the influence of the back-gate bias VGb. This

influence is related to the minimization of the leakage current at low

VGf depicted in Fig. 4.1. As VGf is reduced to switch the device from

OFF to ON (accumulation), the measured leakage current reaches a minimum

value, whereas the calculated current continues to be reduced

monotonically. This simply indicates that the field emission in our

model is insignificant at this point, and the actual minimum leakage

current is produced by another mechanism, possibly field emission -via

grain-boundary traps near the back surface where positive interfacial

charge- could indeed cause inversion .with the back gate grounded

(VGb = 0). The minimum measured currents in Fig. 4.1 show a strong
dependence on VD like our model predicts, and hence we surmise that they

result from field emission near the hack surface. We note further that.

the value of VGf at which the minimum IL obtains decreases as VD

increases. This implies that the dependence on VD of the field-emission

current at the back surface is weaker than that of the front-surface

current, which, based on our model, is a result of the thicker back-gate

(underlying) oxide.

Measured ID(VGf,VGb) characteristics for a hydrogenated n-channel

inversion-mode LPCVD thin-film polysilicon MOSFET, with VD = 5V, are

plotted in Fig. 4.9. For VGf << 0 (OFF region), ID ( IL) is

independent of VGb and increases exponentially with IVGfI in accordance

with our model. For low VGf (near the minimum 1o), with VGb < 0 which

implies that the back surface is accumulated, I increases with IVGbI




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