• TABLE OF CONTENTS
HIDE
 Title Page
 Acknowledgement
 Table of Contents
 Abstract
 Introduction
 Background
 System design of the multi-loop...
 Synthesizer implementation
 Frequency summation mechanism
 Voltage-controlled oscillator and...
 The synthesizer output spectru...
 Measured synthesizer performan...
 Summary, closing comments...
 Appendix
 Reference
 Biographical sketch
 Copyright






Title: Design and analysis of an integrated circuit-based multi-loop frequency synthesizer
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Permanent Link: http://ufdc.ufl.edu/UF00082411/00001
 Material Information
Title: Design and analysis of an integrated circuit-based multi-loop frequency synthesizer
Physical Description: vi, 412 leaves : ill. ; 29 cm.
Language: English
Creator: Martin, Frederick Lee, 1957-
Publication Date: 1992
 Subjects
Subject: Frequency synthesizers -- design and construction   ( lcsh )
Electrical Engineering thesis Ph. D
Dissertations, Academic -- Electrical Engineering -- UF
Genre: bibliography   ( marcgt )
non-fiction   ( marcgt )
 Notes
Thesis: Thesis (Ph. D.)--University of Florida, 1992.
Bibliography: Includes bibliographical references (leaves 408-411).
Statement of Responsibility: by Frederick Lee Martin.
General Note: Typescript.
General Note: Vita.
 Record Information
Bibliographic ID: UF00082411
Volume ID: VID00001
Source Institution: University of Florida
Holding Location: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
Resource Identifier: aleph - 001801809
oclc - 27719624
notis - AJM5578

Table of Contents
    Title Page
        Page i
    Acknowledgement
        Page ii
    Table of Contents
        Page iii
        Page iv
    Abstract
        Page v
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    Introduction
        Page 1
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    Background
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    System design of the multi-loop synthesizer
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    Synthesizer implementation
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    Frequency summation mechanism
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    Voltage-controlled oscillator and shaping circuits
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    The synthesizer output spectrum
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    Measured synthesizer performance
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    Summary, closing comments and conclusion
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    Appendix
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    Reference
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    Biographical sketch
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    Copyright
        Copyright
Full Text












DESIGN AND ANALYSIS OF AN INTEGRATED CIRCUIT-BASED
MULTI-LOOP FREQUENCY SYNTHESIZER


















By

FREDERICK LEE MARTIN


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


1992















ACKNOWLEDGEMENTS

I am very grateful to the people and organizations who

helped and supported me in this endeavor. Special thanks go

to the members of my supervisory committee, especially the

chairman, Dr. Leon W. Couch, and cochairman, Dr. Robert M.

Fox. Their insight and encouragement did much to improve the

quality of this dissertation.

Special thanks go also to Motorola, Incorporated and to

Mr. William O'Connor, Director of IC Technology Center at

Motorola. This study was funded by Motorola through the

Distinguished Student/Employee Fellowship Program. Without

their generous support, the study could not have been

completed.

Finally, very special thanks go to my wife, Jennifer.

















TABLE OF CONTENTS


ACKNOWLEDGEMENTS


ABSTRACT . . .


CHAPTERS


1 INTRODUCTION .


Purpose and Scope of the Research . . .
Original Elements of the Dissertation . .
Organization of the Text . . . . .

2 BACKGROUND . . . . . . . .

The Portable Communications Environment .
Specifications for the Synthesizer Design
Survey of Existing Technology . . . .


3 SYSTEM DESIGN OF THE MULTI-LOOP SYNTHESIZER

Overview . . . . . . . . . .
The PLL Synthesizer as a Building Block . .
Sum-and-Divide Synthesizer as a Building Block
Multi-Loop Synthesizer Structure . . . .
System Specification . . . . . . .

4 SYNTHESIZER IMPLEMENTATION . . . . .

Overview . . . . . . . . . .
Structure of the Integrated Circuit . . .
Low-Frequency Loops . . . . . . .
Output Loop . . . . . .
Control and Test Functions . . . . .

5 FREQUENCY SUMMATION MECHANISM . . . .

Overview . . . . . . . . .
Frequency Summation of Sinusoidal Signals .
Symmetrical Clipping of Multiplier Inputs .
Image-Balanced Multiplier Implementation . .


6 VOLTAGE-CONTROLLED OSCILLATOR AND SHAPING
CIRCUITS . . . . . . .


Overview . . . . . .


ii


S v


4
5

7
. . 1


. . 4
. . 5

. . 7


30


67
68
73
96
106

112

112
113
118
140


. . 154


. . . . 154










Description and Analysis of the Ring-Oscillator
Circuit . . . . . . . . .
Bias Generator . . . . . . . .
Shaping Circuits . . . . . . . .
Design Considerations . . . . . .


7 THE SYNTHESIZER OUTPUT SPECTRUM . .

Overview . . . . . . . .
The Continuous Output Spectrum . . .
The Discrete Output Spectrum . . .

8 MEASURED SYNTHESIZER PERFORMANCE . .

Overview . . . . . . . .
Test Structures and Methods . . .
Characterization of the Ring-Oscillator
Noise Spectrum of the Low-Frequency Loop
Spur Spectrum of the Low-Frequency Loop
Spur Spectrum of the Synthesizer System


. . . 196


. 196
. 198
. 225

. 254


. 254
S. 255
. 260
S. 275
S. 277
. 279


9 SUMMARY, CLOSING COMMENTS AND CONCLUSION . .

Summary of Dissertation . . . . . .
Closing Comments . . . . . . . .
Conclusion . . . . . . . . . .

APPENDICES

A DETAILED SCHEMATIC DIAGRAMS FOR THE MULTI-LOOP
SYNTHESIZER INTEGRATED CIRCUIT . . .


B STRUCTURE AND OPERATION OF EMITTER-COUPLED LOGIC
USED IN THE SYNTHESIZER . . .. ....


Introduction . . . .
ECL Structures . . . .
Propagation Delay, Bias
Dissipation . . .


Current and Power


C PROGRAM LISTING -- MULTI-LOOP SYNTHESIZER DISCRETE
SPECTRUM ANALYSIS PROGRAM . . . . .


286


S 286
S 288
S 290


292


341

341
342


. . 358


367


D PROGRAM LISTING -- BASIC PROGRAM FOR MULTI-LOOP
SYNTHESIZER SERIAL LOADER . . . . .. 391


REFERENCES . . . . . . . . . . .

BIOGRAPHICAL SKETCH . . . . . . . . .


408

412


157
182
186
189















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

DESIGN AND ANALYSIS OF AN INTEGRATED CIRCUIT-BASED
MULTI-LOOP FREQUENCY SYNTHESIZER

By

Frederick Lee Martin

August, 1992

Chairman: Leon W. Couch, Ph.D.
Major Department: Electrical Engineering

A frequency synthesizer for generation of radio-frequency

signals in portable communications applications is designed,

analyzed and tested. The synthesizer features a unique multi-

loop system design and unique voltage-controlled oscillator

(VCO) and frequency summation blocks. Emphasis in the study

is on means of realizing wide synthesizer control bandwidth in

a synthesizer implemented on a single integrated circuit

substrate.

The synthesizer architecture presented in the study

includes elements of phase-locked loop (PLL) and direct sum-

and-divide frequency synthesis. The study includes a

description of the design and analyses of spur and noise

characteristics of the system output. Methods are discussed

for extending the design to improve output spur performance.

A tunable, monolithic ring-oscillator is utilized as the

VCO in some synthesizer loops. The design of this circuit is









described in the study. The FM spectra of the oscillator and

the tuning characteristics are analyzed.

Coupling between loops of the multi-loop synthesizer is

accomplished via a frequency summation structure based on an

image-balanced multiplier. A time-domain analysis is

performed to define limits on input wave shape for the

structure.

The study includes a description of measured results on

a version of the synthesizer on a BICMOS process. Measured

and predicted spectral characteristics of the VCO and the

synthesizer are compared.















CHAPTER 1
INTRODUCTION

Purpose and Scope of the Research

Generation of radio or microwave frequency carriers via

frequency synthesis is an area of research that has been

somewhat neglected during the past decade, with the result

that existing frequency synthesizers in commercial communica-

tions products are based on approaches developed ten to twenty

years ago. With the growth of commercial communications in

the land-mobile and cellular telephone bands, and with the

expected emergence of digital cellular telephone and personal

communications systems [1], [2], new frequency synthesis

requirements are evolving which cannot be met by existing

approaches. Thus, an environment is developing where new

research is needed in the area of frequency synthesis tech-

niques.

While size, cost, spectral purity and power dissipation

are all areas where improvement in frequency synthesizer

technology could be sought, the single most pressing perfor-

mance issue in frequency synthesis for commercial applications

is settling time. This is broadly defined as the time

required for a synthesizer to reach the correct steady state

frequency after a channel change or other external perturba-

tion. Settling time is an important system consideration in







2

time division multiple access (TDMA) and frequency-hopping

code division multiple access (CDMA) communications systems.

In frequency division multiple access (FDMA) systems, fast

settling time is desirable for minimizing susceptibility to

mechanical vibration and other environmental disturbances and

in facilitating implementation of features such as channel

scanning. Present synthesizer systems which are acceptable

for commercial communications units in terms of size, cost and

power dissipation generally have poor settling time perfor-

mance. The goal of this study is to explore a synthesizer

design which is comparable to existing designs in size, cost

and power dissipation but exhibits faster settling time.

While settling time is important to many synthesizer

applications, its definition and measurement criteria are

dependent on the application. To avoid the ambiguity associ-

ated with settling time, the related concept of controller

bandwidth is emphasized in this study as the benchmark for

comparing settling times of different synthesizers. The

concept of bandwidth is common to all synthesizers which

employ phase-locked loop (PLL) or filtering techniques. In

all such systems, settling time is limited by the bandwidth of

the synthesizer controller.

The synthesizer research performed in this dissertation

is in the form of a design. A unique synthesizer system with

the potential to satisfy commercial communications require-

ments while providing a wider controller bandwidth than is

found in previously reported systems is designed, analyzed,







3

constructed and tested. The design makes use of multiple PLL

frequency synthesizer blocks coupled in an arrangement which

minimizes discrete and continuous disturbances in the system

output spectrum. The inherently low level of coupling of

disturbances to the system output spectrum facilitates a wide

controller bandwidth. In previously reported synthesizers,

narrow filters are required to minimize disturbances in the

system output spectrum.

A key element of the dissertation is the exploration of

integrated circuit (IC) design techniques in the implementa-

tion of the multi-loop synthesizer. The study includes

fabrication of an IC containing most of the functions of the

synthesizer system. Key circuits in the system are designed

to take advantage of the high degree of device matching and

low parasitic capacitance that is characteristic of the

integrated circuit environment.

The work presented here represents a "first-pass" effort

in the design of the synthesizer system. The system as

designed exhibits undesired discrete output spectrum compo-

nents (spurs) at some frequencies which would be unacceptable

in most applications. Mechanisms which cause the spurs are

discussed in this report, as are possible design changes which

could minimize the problem. Suggestions for further research

on this topic are presented in the concluding chapter of this

dissertation.









Original Elements of the Dissertation

The dissertation contains elements of both design and

analysis which represent original contributions of the author.

Original aspects of material are noted in the text as part of

the presentation. An overview is presented here.

Among the original design elements in the study are the

overall system design, and in particular, the combination of

integrated circuit and synthesizer system designs which

facilitates implementation of the system on a single IC.

While many of the system design techniques applied here have

been previously reported, the use of the multi-loop configura-

tion in an integrated circuit environment to optimize the

performance of integrated circuit synthesizer elements is

unique.

Two synthesizer circuits also represent original design

contributions. The first is an integrated, tunable ring-

oscillator structure used as a voltage-controlled oscillator

(VCO). The second is an image-balanced multiplier circuit and

its associated driving circuitry. The circuits represent

essential blocks in the synthesizer system.

Many of the analyses produced in support of the synthe-

sizer design are original. Most significant among these are

the analyses of the ring-oscillator output spectrum and image-

balanced multiplier time-domain output. The analysis of the

ring-oscillator is part of a larger description of the circuit

which includes sections on tuning characteristics, output

amplitude and output noise spectrum. The multiplier analysis







5

features a time-domain derivation of conditions under which

the image-balanced multiplier acts as a frequency summation

operator. Additional analyses of some significance are the

calculations of the discrete and continuous output spectra of

the synthesizer system.

Organization of the Text

The remainder of this study is organized into separate

discussions, each addressing a major topic of the study:

In Chapter 2, background information for the study is

presented. The purpose of this chapter is to support the

technical detail presented later in the dissertation, and to

explain the factors which make the design unique and timely.

Topics include a description of the environment in which

synthesizers for commercial communications applications must

operate, a discussion of target specifications for the

synthesizer, and a review of the present state of the art in

frequency synthesis.

In Chapter 3, the synthesizer system design is presented.

The chapter includes a description and analysis of synthesizer

building blocks, a system analysis of the synthesizer design

that is the focus of this study, and a specification of the

design.

In Chapter 4, the implementation of the synthesizer

integrated circuit is described. Non-original circuits used

in the multi-loop synthesizer IC are also described.

In Chapter 5, the coupling mechanism used to inject

signals into PLL synthesis structures is described. The









coupling mechanism performs a frequency summation operation,

producing an output signal whose frequency is the sum of the

frequencies its input signals. The chapter features a time-

domain analysis of the block which results in a set of

conditions under which correct frequency summation occurs.

In Chapter 6, the ring oscillator is described. The

chapter includes sections on the design of the structure and

on analyses of amplitude, tuning and spectral characteristics.

In Chapter 7, continuous and discrete output spectra for

the synthesizer system are analyzed. The chapter includes a

description of a program used to predict the discrete output

spectrum of the synthesizer as a function of carrier frequen-

cy.

In Chapter 8, results of measurements on the working

synthesizer system are reported. Sections are included on the

ring oscillator and on all PLL blocks in the system.

In Chapter 9, a summary of the dissertation and closing

comments are presented.

Four appendices are included in the dissertation.

Appendix A contains the set of detailed schematics for the

synthesizer IC. Appendix B contains a description of the

differential emitter-coupled logic (ECL) used to implement

many of the circuits in the IC. Appendix C contains a listing

of the program used in the analysis of the discrete output

spectrum of the synthesizer. Appendix D contains a listing of

the program used to configure the synthesizer IC.















CHAPTER 2
BACKGROUND

The Portable Communications Environment

Many similarities exist among user equipment for existing

and proposed wireless commercial communications services.

This similarity is an outgrowth of similar physical and

performance characteristics which define the services. The

combination of physical and performance attributes is de-

scribed collectively in this paper as the "portable communi-

cations environment." The term "portable" reflects the

partial or complete dependence of most commercial wireless

communications on portable, handheld user equipment.

Physical attributes for user equipment in the portable

communications environment are defined by the requirement for

portability and by the commercial nature of the communications

services. The portability requirement implies strict limita-

tions on the size and power consumption of all components used

in the equipment. Cost, which can also be treated as a

physical attribute, is limited by the commercial nature of the

application. Most commercial wireless communications services

act as extensions or alternatives to wireline phone services.

Thus, the cost of the user unit must be sufficiently low to

compete on this basis.







8

In terms of performance, services are designed primarily

for transmission of voice information and for operation in

areas where frequency spectrum is crowded and difficult to

obtain. As a result, operating frequencies tend to be closely

spaced and spectral purity of transmitted signals is rela-

tively high.

Frequency synthesizers designed for user equipment in the

portable communications environment derive common attributes

from the equipment for which they are specified. As with the

complete user unit, the attributes can be grouped as either

physical or performance related. The two groups are discussed

qualitatively in the paragraphs below. Emphasis in the

discussion is on the impact of the different attributes on the

research presented in this dissertation.

Physical Attributes

Important physical attributes of frequency synthesizers

in the portable communications environment include size, power

consumption, cost and interface requirements. In all of these

areas, existing and reported synthesizers show considerable

similarity. A summary of current and reported practice with

regard to these physical attributes is presented here.

Collectively, the attributes serve as a benchmark. Whatever

the performance, new synthesizer designs must meet or exceed

the physical attribute benchmarks set by current designs.

Physical size. The physical size of existing and

reported synthesizer systems in the portable communications

environment varies widely in terms of spatial dimensions as







9
applications are compared. However, the number and type of

components varies little from system to system. The typical

synthesizer contains a single integrated circuit package, a

fixed reference frequency source and discrete component

implementations for a low-pass filter and a VCO. New synthe-

sizer systems in the portable environment would be limited to

similar numbers and types of components.

Cost. As with size, cost of comparable synthesizer

systems is difficult to compare directly. Variation in

packaging and performance specifications make accurate cost

comparisons difficult. However, the underlying cost-driving

factors are similar among most units in the portable communi-

cations environment. Integrated circuits are either commer-

cially available or are implemented with custom circuits built

on high-volume, standard IC processes. Discrete components

are largely standard, high volume items. Custom or exotic

components are rarely used. The reference frequency source is

simple, requiring no modulation and tuning only for frequency

setting. New approaches in frequency synthesis for this

environment would by limited to similar low cost techniques.

Power Consumption. Power for portable communications

equipment is supplied by battery, making minimization of power

consumption a desirable goal. Frequency synthesizer power

dissipation varies by application and operating frequency,

with typical values in the range 10 to 100 mW. For synthe-

sizers with fast settling time, an acceptable value could be







10

somewhat higher, since the synthesizer could be powered only

intermittently during times of no communications activity.

Interface requirements. In this category are grouped

supply, programming and output requirements. Typically in

portable communications equipment, DC power is available in

the form of a single regulated supply with value in the range

3 to 5 volts. Additional negative or high voltage supplies

must be generated using capacitive switching techniques [3].

A microcomputer is, almost universally, resident and available

to provide programming inputs to a synthesizer via a serial

bus. Synthesizer radio frequency (RF) outputs are generally

in the form of impedance-matched ports with output levels on

order of 0 dBm.

Performance Attributes

Key performance attributes of frequency synthesizers in

the portable communications environment include frequency

range and resolution, spectral purity and settling time.

While, to some degree, requirements for these attributes vary

with the application, many similarities exist in the require-

ments for most portable communications applications. Factors

which link and differentiate frequency synthesizers with

respect to these attributes are discussed below.

Frequency range. The required range of synthesizer

operating frequencies varies considerably depending on the

type of communications service under consideration. Land-

mobile radio systems alone utilize parts of the spectrum in

the range 35 to 950 MHz. Cordless telephone and personal







11

communications services have been proposed for frequencies as

high as 1900 MHz. It would be exceedingly difficult to design

a single frequency synthesizer to operate over this entire

range of frequencies. However, using the approach taken in

the design of most modern synthesizers, a common approach can

be used to cover the range.

Typically, a synthesizer consists of an oscillator which

produces a signal at or near the output frequency of the

system and a synthesizer network which acts either to control

or to modify the signal of that output oscillator. For any

synthesizer designed using this approach, a wide range of

frequency bands can be generated by designing the output

oscillator to operate in the correct band. Design of circuit-

ry used to modify or control the oscillator frequency is

essentially independent of the operating frequency of the

oscillator. This is the approach used in the synthesizer

designed for this study.

Frequency resolution. Frequency resolution refers to the

spacing between frequencies produced by the synthesizer. In

the personal communications environment, frequency resolution

is relatively fine, at least compared to communications

activities such as satellite communications or broadcast

television. Within the personal communications environment,

frequency resolution requirements can be classified by system

access method. FDMA systems such as land-mobile radio and

most existing cellular telephone require narrow channel

spacings in the range 12.5 to 30 kHz. TDMA and CDMA systems,







12

including the GSM digital cellular standard and proposed

personal communications systems, require channel spacings on

order of 200 kHz to 1.73 MHz [4].

Spectral purity. The output spectrum of the typical

synthesizer contains discrete and broadband disturbances. The

discrete disturbances, termed "spurs" in this paper, are

measured in units of dBc (decibels with respect to the carrier

power). The broadband noise is described by the sideband

noise ratio (SBNR) in units of dBc/Hz.

The required attenuation of noise and spurs with respect

to the synthesizer carrier is determined by the targeted

adjacent channel selectivity ratio of the communications

system. Typical values for this ratio are on order of -60 to

-90 dBc, depending on the system. For synthesizer design

purposes, discrete and continuous output spectra are specified

separately. Limits are assigned to each of the two distur-

bance types such that the total spectral energy within a

system receiver bandwidth satisfies adjacent channel require-

ments.

Settling time. Settling time refers to the time required

for the synthesizer output to the correct steady-state

frequency after a channel change or perturbation. The direct

importance of this specification to communication system

performance varies depending on the system access method. In

TDMA and CDMA systems, required settling time is small

(typically less than 1 mS) and critical to system performance.







13
For FDMA systems, settling time is of secondary importance to

system operation.

In all systems, performance of the user unit is greatly

affected by settling time. This is a result of the character-

istic of virtually all frequency synthesizers to produce

modulation of the output carrier in response to mechanical or

electrical disturbances to the physical environment about the

synthesizer. Systems with faster settling times tend to have

greater immunity to environmental disturbances. Additionally,

rapid settling times facilitate the design of user unit

features such as channel scanners and power consumption

reduction schemes.

While settling time is an important feature for frequency

synthesizers in the portable communications environment, it

tends to be difficult to apply as a benchmark. At present,

there is no standard definition of settling time. Settling

time measurement is further clouded by the use in some systems

of frequency steering or adaptive filter schemes to reduce

settling time at channel change. In this dissertation, the

benchmark used to evaluate settling time is synthesizer

control bandwidth. For feedback type synthesizers, this

refers to the bandwidth of the control loop. For synthesizers

which use bandpass filters, the control bandwidth is treated

as the equivalent low-pass filter bandwidth of the most narrow

bandpass filter in the system. In virtually all synthesizers,

control bandwidth limits settling time. Furthermore, the







14

bandwidth can be measured independently of adaptive filter of

steering operations.

For comparison, an estimate is provided of the settling

time for a PLL synthesizer. The settling time is estimated

from the transfer function of a type 2 loop (a loop in which

the loop filter contains a single pole at frequency 0) with a

second order filter. An expression can be derived from the

transfer function of the loop:

2 ( fFINAL '?_
tsettling In AfFIL (2-1)


In the expression, AfOFFSET is the magnitude of the change in

frequency induced by the channel change, AfFINAL is the accept-

able frequency error in the system and co is the unity gain

bandwidth of the PLL loop in radians/sec. The expression

provides an acceptable approximation for settling time for PLL

synthesizer with higher order filters. A rough approximation

for settling times of synthesizers whose settling time is

limited by bandpass filter bandwidth can be obtained using

the equivalent low-pass bandwidth in place of (0c.

Specifications for the Synthesizer Design

The synthesizer design explored in this dissertation is

intended to be compatible with the portable communications

environment. Design specifications, developed from the

environment description of the previous section and adhered to

in the design except where noted, are presented here in

tabular form. Information in the tables represents specifica-







15

tions for physical and performance attributes of the synthe-

sizer system.

Physical Attributes

The physical attributes of Table 2-1 form a general

description of the synthesizer system under study. Each of

the listed restrictions is based on an overriding goal of

designing a synthesizer which can be implemented with physical

attributes comparable to previously reported designs. The one

area where the design presented here is not equal to the best

reported system is in power consumption, where the 75 mW

specification is higher than power consumption in many

existing and reported systems. The additional power consump-

tion is partly the result of complex system structure (which

results in wide control bandwidth) and partly the result of a

circuit design not optimized for minimum power dissipation.

Additional effort and design risk required to reduce power

consumption could not be justified in this demonstration

study.

While the physical attributes define much of design

approach of the system presented in following chapters,

little explicit discussion of physical attributes appears in

the following chapters. It can be assumed that the design

meets all criteria described in Table 2-1.

Performance Attributes

Performance specifications are presented in Table 2-2.

In general, the collection of specifications represents

typical synthesizer requirements for an FDMA application.










Physical Attributes of Synthesizer System.


Attribute Specification

Size Synthesizer component listing:
one integrated circuit.
one fixed frequency reference
signal source.
one discrete loop filter.
one discrete VCO.
Cost Driving Integrated circuit:
Factors custom IC implemented on standard
BICMOS process.

Reference source:
fixed frequency.
no special tuning or modulation
requirements.

Discrete components:
no custom or high performance
components.
Power dissi- 75 mW at 3.0 volts supply.
pation
Interface DC supplies:
requirements main supply: 2.9 to 5.0 volts at
25 mA.
optional high voltage supply: 5.0
to 10.0 volts at 400 gA (could be
supplied by voltage multiplier).

Programming:
3 wire serial interface.

Outputs:
Outputs provided by discrete VCO.
No limitations due to system
design.


This focus on narrow channel spacing, FDMA compatible specifi-

cations was chosen because it offers a more comprehensive test

of the synthesizer. Performance of the synthesizer to wide

channel spacing (TDMA or CDMA) specifications can be regarded

as a subset of the narrowband results.


Table 2-1.







17
Table 2-2. Performance attributes of synthesizer system.

Specification Value
Frequency Range (MHz) 451.2 to 464.0
Channel Spacing (kHz) 12.5
Spurs (dBc/Hz) -70 max.
SBNR (dBc/Hz at offsets -120 max.
from the carrier 25 kHz or
greater)
Control Bandwidth 2n.25l103
(radians/sec)

From a research perspective, the most critical specifica-

tion in Table 2-2 is the control bandwidth of the synthesizer.

The target bandwidth of 2it25-103 radians/sec was chosen

somewhat arbitrarily as a value which could be achieved using

the system design presented in the next chapter. As noted in

the review of existing technology in the next section, the

figure exceeds the best previously reported control bandwidth

by a factor of 50.

A settling time can be estimated using the expression in

(2-1). For an initial offset of 10 MHz, a maximum error of

100 Hz and a unity gain frequency equal to the design band-

width value of 2n-25-103 radians/sec, the estimated settling

time is 146 gS.

As explained in the previous section, the choice of

operating frequency range is largely independent of the

synthesizer design approach. For this study, the test range

of 451.2 to 464.0 MHz was chosen. The values for the range

correspond to a portion of the UHF land-mobile band for which

test equipment and working user units are readily available.







18

The 12.8 MHz range extent was chosen in relation to the system

reference frequency of the designed synthesizer. The reason-

ing for this choice becomes apparent as design and test of the

synthesizer is presented.

It must be noted that the synthesizer as built and tested

in this dissertation does not meet output spectrum require-

ments of Table 2-2. System SBNR is limited by a fixable

design error which could not be corrected for this study due

to limitations on time and access to IC processing. Output

spur amplitudes are above design targets due to fundamental

mechanisms in the synthesizer system. These mechanisms, along

with design changes which could reduce or correct the problem,

are discussed in later chapters of this work.

Survey of Existing Technology

The justification for the research presented here is that

no existing approach to synthesizer implementation can

simultaneously satisfy the physical and performance require-

ments of Table 2-1 and Table 2-2. This is demonstrated in the

summary of existing synthesizer technology presented in this

section. The review includes current synthesizer approaches

which appear in textbooks, journals or existing portable

communications products. Discussion is limited synthesizer

system approaches. Present art in synthesizer functional

blocks is surveyed in the chapters where original blocks are

discussed.










Phase-locked Loop Frequency Synthesis

This approach to frequency synthesis has been dominant in

portable communications applications since frequency synthe-

sizers became prevalent in portable equipment in the 1970s.

The theory governing PLL frequency synthesis, understood since

the 1960s, is discussed in textbooks [5], [6]. New appli-

cations and implementations continue to appear.


-----------
I REF DIVIDE

(12.8 MHz) (R= 1024)
I I

I(12.5 kHz)
I OR LOOP FILTER I
PHASE LOOP FILTER VCO I
I DETECTOR LOPI
I I T


Figure 2-1.


Block diagram of PLL frequency synthesizer.


A typical PLL frequency synthesizer is shown in block

diagram form in Figure 2-1. The synthesizer consists of a

fixed reference frequency signal source, a VCO, a phase

detector, a loop filter and digital dividers at outputs of

both the reference signal source and the VCO. The circuit


SYNTHESIZER IC L
I.----------------.


programmable N







20
operates as a feedback control system, with the VCO output

frequency manipulated such that the phase error at the loop

phase detector output is maintained at a fixed value. The

steady state condition for operation can be described in terms

of the frequency of the reference source f, and the VCO f, by

fo = N (2-2)

where N and R are the modulus values for the loop divider and

reference divider, respectively.

While the basic operation of the PLL synthesizer has been

unchanged in recent years, implementations have improved as

integrated circuit technology has matured. Shown in

Figure 2-1 is the grouping of operations used for the more

recent commercially available and reported systems. In this

configuration, a single integrated circuit substrate contains

all divider and phase detector operations in addition to gain

stages for the reference source. Other circuitry, for a

number of reasons, cannot be integrated. The reference source

requires a non-integratable piezo-electric crystal. Spectral

purity issues force implementation of the VCO using a discrete

inductor or resonator structure. Loop filter capacitor values

preclude integration. Implementations of the single-chip

divider and phase detector units have been reported in CMOS

[7] and BICMOS [8] technologies.

In comparison to the targeted attributes of the synthe-

sizer designed for this study, PLL frequency synthesizers

compare well in physical attributes but not in performance








21

attributes. In terms of physical attributes, the size, cost,

power dissipation and interface descriptions of Table 2-1 were

formulated from comparison to existing and reported PLL

synthesizers. Performance of PLL systems is limited due to a

fundamentally low control bandwidth, on order of 2' 50

radians/sec for systems with spectral purity requirements

listed in Table 2-2. As seen in the table, this value is

several orders of magnitude less than the target value of

27C25-103 radians/sec.

The dynamics of the PLL synthesizer are discussed in

Chapter 3. For clarity, the mechanism responsible for low

control bandwidth in PLL synthesizers is demonstrated by

example, here, using Figure 2-1 and the expression in (2-2).

It can be seen from (2-2) that for integer R and N, the

frequency of the signal at the reference divider output must

be no greater than the frequency resolution of the channel

spacing. This results in a high value for loop divider

modulus N. For example values of 461.625 MHz for fo and 12.5

kHz for channel spacing (from Table 2-2), the resulting value

for N is 36930. If the PLL is treated as a linear system, the

DC gain from the reference divider output to the VCO output is

91 dB. This high gain is applied to noise generated in the

reference path and to discrete frequency components of the

reference signal which are conducted through the phase

detector by parasitic and mismatch mechanisms. To minimize

the effects of these undesired components on the VCO output

spectrum, a narrow control bandwidth must be applied.









Settling Time Improvement Techniques

Many schemes have been developed to overcome the slow

settling time of PLL frequency synthesizers. The schemes fall

into three basic categories depending on the approach. The

first category includes those schemes that steer or preset the

VCO frequency at the beginning of a channel change operation

[5, p. 242]. This reduces settling time by reducing the

magnitude of the frequency change required by the VCO. In

systems which use wide tuning range or phase detectors without

inherent steering, a steering circuit may be required for lock

acquisition. A second approach increases synthesizer band-

width at channel change or in the presence of an out-of-lock

condition, then returns the loop to its narrow bandwidth after

equilibrium has been restored [9]. The wider bandwidth

facilitates reduced settling time in environments where

additional noise and spurs generated at channel change are not

a concern. A third approach employs two complete synthesizers

such that a channel change in one synthesizer can be imple-

mented while another provides an output signal. This scheme

would be useful in frequency hopping environments.

All of these settling time reduction schemes share common

disadvantages of increased circuitry and poor response to non-

programmed perturbations to the loop. A synthesizer with

inherently wide bandwidth, such as the one studied in this

dissertation, overcomes these limitations. Also, any of the

schemes could be used with the wide-bandwidth synthesizer








23

presented here to achieve further improvements in settling

time.

Fractional Division Frequency Synthesis

An extension to the PLL synthesis approach is the

fractional division frequency synthesizer. In this approach,

a divider control block is added to the basic PLL frequency

synthesizer structure as shown in Figure 2-2. The purpose of

the divider control block is to manipulate over time the

integer loop divider modulus N, creating a time-averaged value

of N which is non-integer.

The advantage of fractional division can be shown by

revisiting the example shown for basic PLL operation. The

example is illustrated in Figure 2-2, where the reference

divider modulus R is set to unity and integer portion of loop

divider modulus N is set to 36. Reference frequency fR (12.8

MHz) and output frequency fo (461.625 MHz) are unchanged. The

effect of fractional division in the example is to manipulate

the instantaneous value of N such that the time-averaged value

has fractional part 66/1024. This results in the desired

synthesizer output frequency but a gain from reference divider

output to VCO output of 31 dB. An improvement of 60 dB is

realized compared to the simple PLL synthesizer. This example

demonstrates that the susceptibility of fractional division

systems to reference path disturbances can be lower than that

of equivalent PLL systems which employ integer division.

Fractional division synthesizers are limited in control

bandwidth due to the need to filter from the VCO output














(12.8


programmable N, num, den

Figure 2-2. Block diagram of fractional division synthe-
sizer.



spectrum spurious frequency components at integer multiples of

the system frequency resolution. These "subharmonic" spurs

result from periodic manipulation of the loop divider modulus,

an activity which generates phase perturbations in the PLL

which appear in the VCO output spectrum. Analog [10] and

digital [10], [11], [12] methods have been reported

which minimize low frequency components of the disturbance.








25

Of these, digital methods have proven to be the more effec-

tive.

Most research in the area of fractional division has been

conducted by private corporations whose reports are released

in the form of patent documents. As such, measured perfor-

mance of fractional division systems is generally not pub-

lished. The best comparison of fractional division synthe-

sizer performance to the target specifications can be found in

the performance of synthesizers in recently released portable

communications products. For narrowband systems (frequency

resolution on order of 12.5 kHz), the best known control

bandwidth is 27 500 radians/sec.1 Though information is

available for fractional division synthesizers for systems

with wider channel spacing, control bandwidths could be

expected to be wider for these systems. The improvement in

bandwidth with increased channel spacing is the result of

wider separation from the carrier of subharmonic spurs for

increased channel spacing.

Coherent Direct Synthesis

While coherent direct synthesis has not appeared in

recent literature or applications, its continued presence in

texts on frequency synthesis [6, p. 7] and spread spectrum

communications [13, p. 126] makes it worthy of discussion.

Also, the principles of operation for this method are used as

a building block in the system design presented in the next



IRadius GP300 Land-Mobile Transceiver, manufactured by
Motorola, Inc.







26

chapter. Synthesizers of this description are categorized by

output signals which are produced directly from a single

reference frequency via a combination of division, multiplica-

tion, mixing and filtering operations. Several approaches can

be included in this category, the most common of which is the

sum-and-divide approach.

An example of a double-mix sum-and-divide synthesizer is

shown in Figure 2-3. The example frequencies shown in the

figure depict a typical scheme for generating frequency

461.625 MHz. The scheme presented in the figure is simplified

compared to an actual circuit. Not shown are the bandpass

filters required at each mixer and divider output and the

fixed frequency section required to produce the 11 input

signals required for the system.

As seen in the example, direct synthesis requires

considerable circuitry, including multiple filter elements

which are difficult to integrate. The large amount of

circuitry makes systems of this type incompatible with

portable communications environment on the bases of cost and

size. In performance, coherent direct synthesis systems can

meet or exceed all specifications of Table 2-2.

Direct Digital Synthesis

A relatively recent development, the direct digital

synthesizer (DDS) is constructed entirely (except for a

frequency reference) of digital, integratable components. As

shown in the block diagram of Figure 2-4, the system comprises

a reference frequency source, a digital accumulator, a read-















461.625


36+0 36+1 36+2 ... 36+9


*ALL FREQUENCIES ARE IN UNITS OF MHz,


Figure 2-3.


Adjustable-frequency stage for a double-mix sum-and-divide
synthesizer.


frequency







28

only memory (ROM) and a digital-to-analog (D/A) converter. No

filtering or feedback is used.


programmable input

ACCUMU- LOOK-UP D/A
LATOR ROM ---
r (fixed -- --
capacity)


Figure 2-4. Block diagram of direct digital frequency
synthesizer.


In operation, the synthesizer produces an output frequen-

cy that is equal to the product of the reference frequency and

the accumulator capacity. The accumulator contents are

converted to a sinusoid or other output shape via the look-up

ROM. The ROM contents are converted to an analog output via

the D/A converter. While broadband noise produced in the

circuit is minimal, spurs are generated by the finite resolu-

tion of both the accumulator and the D/A converter contribute

significantly to the output spectrum of the system. Recent

papers have characterized these effects [14], [15].

While the direct digital synthesizer compares well to

many of the target attributes of Table 2-1 and Table 2-2,

power consumption for reported schemes exceeds acceptable

limits. This is a fundamental problem resulting from the

number of high-speed operations which must be performed in a

DDS. With improvements in IC technology, the DDS approach may

become viable for portable communications applications. To







29

date, best reported performance is 5.0 watts for a 500 MHz

synthesizer with -30 dBc spurs [16], and 1.6 watts for a

100 MHz synthesizer with -32 dBc spurs [17]. A commercial

venture was announced in which a 16 bit D/A converter for DDS

applications would be developed [18]. The part, described

as "low power," would operate to 1 GHz, provide spur perfor-

mance to the -90 dBc level, and require an estimated 2.0

watts. Clearly, power consumption for present DDS systems

exceeds requirements of the portable communications environ-

ment by an order of magnitude or more.

Hybrid Approaches

An obvious extension of synthesizer technology is to

combine existing approaches to take advantage of the best

features of each. Variations of this technique are discussed

in textbooks [5], [6] and used in test and measurement

equipment [19]. In all cases, the approaches are described

in the context of large systems implemented with discrete

components. Hybrid synthesizers optimized for IC implementa-

tion are described in recent papers [20], [21]. These

systems are based on the use of separate integrated circuits

for each synthesizer element. Problems associated with

combining all synthesizer elements on a single substrate are

not addressed. The multiple IC approach makes such systems

unsuitable for portable communications applications on the

bases of size and cost. Performance of the reported systems

could be expected to exceed the requirements of Table 2-2.















CHAPTER 3
SYSTEM DESIGN OF THE MULTI-LOOP SYNTHESIZER

Overview

In this chapter, the system design of the wide bandwidth

synthesizer is developed. Described in the remainder of this

paper as the "multi-loop synthesizer," the design is actually

a hybrid. Elements of sum-and-divide direct synthesis are

employed along with multiple PLL structures. To maintain

compatibility with the target physical attributes discussed in

Chapter 2, the system is designed such that all elements

except a single VCO, a loop filter and a reference signal

source can be implemented on a single integrated circuit

substrate. This restriction drives optimization of the design

for use with synthesizer components which can be integrated.

The design is presented here both in general form and as

a completely specified system. The latter represents one of

a family of systems which could be built from the general

design. The purpose of the specified system is to provide a

vehicle for demonstration of the system design and the

component designs presented in following chapters. It is not

necessarily the optimal application of the general multi-loop

system design.

The presentation of the system design is arranged in four

sections. In the first two sections, PLL and sum-and-divide








31
synthesis approaches are described and design equations are

derived. These building blocks are used in the third section

to develop the general structure of the multi-loop synth-

esizer. In the final section, assumptions about component and

block performance are applied to complete the specification of

a demonstration system.

The design of the multi-loop synthesizer for implementa-

tion on a single integrated circuit represents work original

to this dissertation. As discussed in the review of existing

technology in Chapter 2, other synthesizers have been reported

which combine PLL and sum-and-divide approaches [6], [19].

However, these designs require components which preclude

implementation on a single integrated circuit.

The PLL Synthesizer as a Building Block

The multi-loop synthesizer presented in this study

embodies the channel delineation and filter characteristics of

the PLL synthesizer. The characteristics are examined in this

section with the purpose of developing design equations for

application to the multi-loop design. The section is devel-

oped with separate discussions on the linear model of the PLL,

the physical interpretation of the model and the PLL synthe-

sizer output spectrum.

Much of the information in this section is adapted from

standard PLL analyses presented in textbooks [5], [6] on PLL

frequency synthesis. This section is included as a basis for

future work and for definition of terminology.









Linear Representation of the PLL Synthesizer

The PLL synthesizer can be treated as a feedback control

system which manipulates the frequency of a VCO by forcing a

fed-back version of the oscillator output to match in phase a

fixed-frequency reference signal. The feedback network

consists of a programmable counter which acts to divide the

phase (or frequency) of the VCO output signal. In closed loop

operation, it is the programmed modulus of the counter which

determines the output frequency of the VCO.


PHASE DETECTOR LOOP VCO
............ ................. na FILTER ne

R K 0
StransKDim F(s) v V g K
1+ ++

LOOP
DIVIDER




n2

Figure 3-1. Linear system representation of PLL synthesizer.


A block diagram of the linear system representation of

the synthesizer is shown in Figure 3-1. Loop parameters

include phase detector gain KD in amps/radian, loop filter

transimpedance F(s) in volts/amp, VCO gain K, in

radians/sec/volt, and unitless loop divider modulus N.

Several signal points are labeled in the figure, including

reference signal point R and output signal point O. Labeled







33
signal points nj, n2 and n3 designate summing inputs for signal

transfer or noise analyses.

The representation of the synthesizer as a linear control

system is valid for a system whose output is at or near its

steady state value, an assumption which applies to synthe-

sizers in normal operation. Under the linear system assump-

tion, the response of the synthesizer to a stimulus can be

expressed as a transfer function. The transfer function of

the system at point O to a perturbation at point R can be

described by the expression


oZ(s)_ KF(s)- K,F(s)K (3-1)
S (3-1)
Qg (s) Kv 1 KFl(s)s '
1 + KF(s) K +KF()K
sN N

where 4R(s) is the incremental phase of the signal at refer-

ence point R and Do(s) is the incremental phase of the signal

at output point O.

The response (3-1) is dependent on the loop filter

transfer function F(s). For this analysis, F(s) is assumed to

be of form


F(s) = KF(+) (3-2)
S(s+p,)...(s+pk)

where K, is a constant, filter zero z is far below the unity

gain frequency of the loop o, (to be defined below), and

filter poles p, through Pk are well above the unity gain

frequency of the loop. A filter design of this description is

commonly applied in PLL synthesizers to insure system stabil-

ity while minimizing steady state phase error and maximizing







34
attenuation of spurious outputs [22]. Applying the re-

strictions on pole and zero locations, the filter transimped-

ance F(s) in the region about unity gain frequency C, is flat.

The magnitude of the transimpedance can be approximated by


IF(S) KF Ri. (3-3)

The unity gain frequency of the loop is the frequency at

which the magnitude of the loop gain is identically equal to

unity. This can be found by setting the expression for loop

gain to unity and solving for frequency. Using the approxima-

tion from (3-3), the loop gain can be expressed:


'1 =iF(s) I KDK 1.s (3-4)
sN sN

By performing the substitution s = jc% and solving for ct, the

unity gain frequency of the loop can be found:

DR = KlK (3-5)
Nu

By substituting (3-2), (3-3) and (3-5) into the original

transfer relation of (3-1), the transfer function can be

expressed in terms of ci and R:

PlP2"..Pk
o_(s) u( ) (s+p1) (s+p2)...(s+pk)(3-6)
R (s ) PlP2"'Pk
s2 + (s+z)--
u (s+pl) (s+p2)...(s+Pk)

Recalling that z is limited to values less than cL, a real

number q (q > 1) can be defined describing the ratio of oL to

z. Then,










Nc +u) PlP2...Pk
so(s) u s (s+p,) (s+p2)...(s +pk)
=' (3-7)
R (s) S2 +( u PlP2"' Pk
q (s+pd) (s +p2)... (s+pk)

The factor representing the loop filter poles in the denomina-

tor of (3-7) can neglected. This follows from the previous

assumption that poles p, through Pk have values much greater

than c,. At frequencies where the factor containing loop

filter poles deviates significantly from unity, the denomina-

tor of (3-7) is dominated by the s2 term. With the factor

containing the loop filter poles neglected in the denominator

of (3-7), the transfer function can be expressed as the

product of a second order PLL transfer function and an

additional unity gain low-pass factor (containing the loop

filter poles):


No s+
00(s) C P1P2"'. P
0R(s) 0 2 (s+pl) (s+p2)...(s+pk)
S2 + SWu -
q

The effect of ratio q in (3-8) can be demonstrated by a

plot of the magnitude of the transfer function for several

values of q. This is shown in Figure 3-2. Curves are

generated with the low-pass factor neglected. As seen in the

figure, the value of q affects the transfer function only in

the region near cl. Low values of q promote peaking of the

response, while a more flat response is achieved for higher

values.











+5
q = 1.5








-5 ----- ------------------------ ---------.
q=1.5



















.01-0u .1u Mu 1 u10
o 0




7-5













Figure 3-2. PLL transfer curve variation versus q.


Using methods similar to those used to derive (3-8),

transfer relationships can be derived for other points in the

PLL. Input points are defined in Figure 3-1. For transfer

relationships between the divider input and the VCO output

(point n2 to point 0) and between the phase detector output

and the VCO output (point n3 to point 0), the transfer curve

of (3-8) can be modified by a constant. The transfer curve

from divider input to VCO output is


3o() q W P1P2.*Pk (3-9)
(s) 22 + u (s+p, ) (s+p2) ... (s+pk)
s2 + S+-
..







37
From the phase detector output to the VCO output, the

transfer curve is


o (s N sq PlP2"'Pk (3-10)
On3 (S) KD 22 (S+PI) (S+P2)...(S+pk)'
S + S~,+-
q

where the transfer expression has units of radians/amp. The

closed loop transfer function between point nj (summed to the

VCO output) and VCO output point O is

0o(s) s2
n3 (s) u2 (3-11)
S + S ,A+
q

Unlike responses in other points in the loop, this transfer

function represents a high-pass response. The response is

independent of loop filter poles pi through Pk,

Magnitudes of transfer curves for the PLL output with

respect to inputs R, nj and n2 are shown in Figure 3-3. Curves

are plotted for q assigned value 4.0 and loop divider modulus

N assigned value 10. Loop filter poles are neglected. The

response from n3 to 0, not shown, matches in shape the

response from R to O.

Physical Interpretation of the Control System Model

The PLL synthesizer possesses characteristics of a

frequency control mechanism, a frequency summation operator

and a bandpass filter. All of these characteristics can be

demonstrated by viewing the transfer analysis of the previous

section in the context of the physical signals present in the

synthesizer. In that context, physical signals for all










+15
+10 ........................--........---------------------------------




S + 5 -........- ........-.... .... .................. .......... .......... ... ....... ... .. ....................... .......
,,, o s]/ (S
cn

:D

C
-5 ......................................... ................. .... ...... ...... ..... ............. ...... .... ............................................


-10



-15 . .i .. .
.01u .1,u m 10ou 100&u


Figure 3-3. Typical PLL transfer function magnitudes.


labeled points in Figure 3-1 (except n3, which is a baseband

current) can be described in the time domain by sinusoidal

expressions with arguments consisting of a frequency term and

a generalized phase perturbation term. For the synthesizer

reference input signal at node R, the expression is

x,(t) = sin[oRt + )R(t)], (3-12)

where (o, is the carrier frequency of the output signal and

OR(t) is the time domain expression for an incremental

perturbation to the steady state condition of the loop. The

frequency domain incremental output phase DR(s) is the Laplace

transform of #R(t) :


QR(s) = f{)R(t)}.


(3-13)







39
Similar expressions can be derived for other nodes in

Figure 3-1.

The frequency control mechanism in the PLL can be

demonstrated through application of a perturbation to the loop

in the form of a step. For a perturbation of magnitude A0R

applied at point R at time t = 0, the time domain waveform can

be described

XR(t) = sin[W t + Aku(t)] (3-14)

The resulting incremental frequency-domain description of the

input is


IR(s) = f{AMRu(t)} = -. (3-15)

Substituting (3-15) into the transfer function of (3-8), an

expression for change in phase of the output as a result of

the step can be found:



o(s) A"R. sql) PlP.Pk (3-16)
s W2 (s+p1) (s+p2)...(s+pk)
S2 + SU+---
q

The steady state value for the phase change can be designated



A40o = o(t)I- = s (s)ls-.o = NAOR. (3-17)

Because the PLL can be treated as a linear system, (3-17) can

be extended to any set of inputs which can be expressed as a

summation of step inputs. This includes the case where OR(t)

is of the form of a frequency term (ot. Then, the frequency







40
at the PLL output c(b can be expressed as a function of the

frequency at reference node R:

Wo = NOR. (3-18)

For fixed ok, the synthesizer output frequency c4 is determined

by the value of the loop divider modulus N.

The frequency summation characteristic of the PLL

synthesizer follows from the superposition property exhibited

by the PLL as a linear system. If a step input in phase with

magnitude A4n2 is applied at node n2, the steady state change

at output node O can be found through analysis of (3-9):

Ao = 4o(t)It-. = so (s)s- = An2 (3-19)

For simultaneously applied steps in phase at nodes n2 and R,

the change in phase at node O can be found through superposi-

tion of the results of (3-17) and (3-19):

Ao = N-AR + A4n2. (3-20)

By again extending the results to include frequency expres-

sions, the frequency summation property of the PLL is demon-

strated:

CO = NgR + (n2. (3-21)

Bandpass and bandstop filter characteristics of the PLL

synthesizer occur because the phase manipulated by the loop is

actually modulation on a steady-state carrier signal. When

viewed as an operation on a modulated carrier, the low-pass

responses (3-8) through (3-10) are translated in frequency to

the carrier frequency of the signal. The result in each case

is a bandpass response centered at the carrier frequency.







41
Similarly, a bandstop response results from frequency transla-

tion of the high-pass response of (3-11).

Spectral Characteristics of the PLL Synthesizer

At steady state, the output of the PLL synthesizer

consists of a carrier term modulated with deterministic

disturbances (spurs) and noise from various sources. In

typical systems, minimization of these disturbances in the

synthesizer output spectrum results in the definition of the

PLL unity gain bandwidth o, and the loop filter characteris-

tics. The disturbance mechanisms can be characterized by the

nature of the source. Major disturbance mechanisms in the PLL

synthesizer are discussed below.

Reference spurs. Reference spurs appear as modulated

sub-carriers about the PLL output signal with separation from

the carrier equal to integer multiples of the reference

frequency. The amplitude of the actual reference spur is

limited by mismatch and parasitic coupling mechanisms in the

phase detector circuit. Modulation components result from

sampling of modulated phase detector input signals by the

phase detector. While not all phase detectors exhibit

sampling characteristics, the digital tri-state detectors used

in this study behave as samplers at a rate equal to the system

reference frequency.

Sub-harmonic reference Spurs [111. In systems which

employ a fractional loop divider, spurs can occur at sub-

harmonics of the system reference frequency. These spurs

result from perturbation produced in the loop by the periodic







42

time variation in the modulus of the divider. The amplitude

of the spur is dependent on the value of the fractional

divisor and on the pattern of modulus values used to produce

the average modulus. An upper bound for spur amplitude is

found by treating the spur as a disturbance of amplitude 2n

radians (1 cycle of the VCO output signal) applied to the loop

at the loop divider input (signal point n) The attenuation

of the spur from point n2 to output point O is described by

(3-9). The upper bound on amplitude comes about because a

change in the loop divider modulus of unity results in a

change in phase at the divider output of 1/N cycles. The same

change reflected to the divider input would have magnitude 1.0

cycles or 2n radians.

VCO noise. The noise spectrum for virtually any oscilla-

tor can be described by region. In the region far from the

carrier, the spectrum is dominated by noise whose distribution

is frequency independent. Closer to the carrier, distribution

of noise in a bandwidth is an inverse function of the frequen-

cy separation from the carrier. Very close to the carrier,

the distribution of noise becomes an inverse function of the

carrier to a power greater than unity. This region, which can

be described as the "1/f" region, is neglected in this study.

Noise in the regions closer to the carrier has the additional

property that the distributions at equal separations above and

below the carrier frequency are correlated; that is, the

noise is FM modulated onto the carrier [5, p. 81].







43

The effect of the PLL on VCO noise is described by

(3-11). Above the unity gain frequency of the loop, the PLL

has little effect on the spectrum of the VCO. Below the unity

gain frequency, the PLL acts as a filter to minimize noise in

the VCO output spectrum.

The limits of the regions for oscillator noise and the

noise density within those regions is dependent on the design

of the oscillator. In the multi-loop system, two types of

oscillator are applied. The oscillator used to generate the

system carrier frequency is implemented as a discrete second

order feedback oscillator or, as in the case of experiments

conducted on the constructed multi-loop synthesizer, with a

commercially available signal generator. In either case, the

oscillator satisfies system spectral purity requirements. A

second type of oscillator is used in other loops in the

system. This is a fully integrated tunable ring-oscillator.

Spectral purity of this circuit is not sufficient to meet

system spectral purity requirements. Therefore, the system

design must be arranged to minimize contributions of these

oscillators to the system output spectrum.

Reference source noise. The spectrum of the reference

oscillator can be treated as a special case of the more

general description of oscillator noise spectra presented

above. For the reference oscillator, non-flat regions of the

spectrum are assumed to reside at frequencies sufficiently

close to the carrier that they may be neglected. Thus, the







44
noise spectrum of the reference oscillator can be regarded as

flat.

The effect of reference noise on the output spectrum of

the PLL synthesizer is described by (3-8). The general shape

of the response is that of a low-pass filter with dominant

corner near unity gain frequency o0. The in-band gain of the

filter is N.

Phase detector and loop filter noise. Noise sources in

the phase detector output stages and the loop filter can be

major contributors to the PLL output spectrum. The sources

can be described as noise currents applied to the loop via

transfer function (3-10). For thermal noise generated in the

filter, shaping by the filter must be considered. Minimiza-

tion of this noise is achieved though selection of a system

reference frequency and scaling of phase detector gain values

and loop filter component values. In this chapter, contribu-

tions of these circuits to the system output spectrum are

neglected. The issue is addressed in the analysis of the

multi-loop system output spectrum in Chapter 7.

Noise in phase processing circuits. Circuits in the PLL

synthesizer which act directly on the phase of a signal

include the loop divider and portions of the phase detector.

In the multi-loop synthesizer design presented in this

chapter, the contributions of these circuits to the system

output spectrum is neglected. The issue is addressed further

in the analysis of the output spectrum in Chapter 7.









Sum-and-Divide Synthesizer as a Building Block

As discussed in Chapter 2, sum-and-divide direct frequen-

cy synthesis is difficult to implement using integrated

circuit techniques. The amount of circuitry and the number of

required bandpass filter operations make this approach better

suited to discrete implementations. However, the sum-and-

divide channel selection mechanism has some attractive

features which can be adapted to approaches more suited to

integrated circuit implementations. That channel selection

mechanism is described in this section. The discussion

presented in this section is a simplified version of the

discussions found in texts on frequency synthesis [5], [6].




k X. / ..- -X P X P2 -




-k fk-1 f3 f2 f1
Figure 3-4. Simplified block diagram of sum-and-divide
frequency synthesizer.


A much-simplified block diagram of a sum-and-divide

frequency synthesizer is shown in Figure 3-4. The diagram

includes only those elements which impact the frequency

selection mechanism. Filters and other hardware not directly

related to channel selection have been eliminated. As seen in

the figure, the synthesizer consists of a cascaded series of

frequency dividers and signal multipliers. The signal







46
multipliers are assumed to produce only the frequency summa-

tion term for the two input frequencies. (This operation is

described in detail in Chapter 5.) Inputs to the synthesizer

are provided by the set of k input signals, each of form

Si(t) = sin(2%fit) = sin[27(fiot + ciAft)], (3-22)

where ci represents a non-negative integer. Notation for

inputs in the figure indicates the frequency of the input

signal.

For the synthesizer of Figure 3-4 with inputs described

by (3-22), the output frequency fo can be described by

f, f, f,
fo = fl + 2 + + +
P2 P23 P23Pk (3-23)
(3-23)
= f10+cAf + f20+c2Af + f30+c3Af ... k
P2 P2P P2P "Pk

Combining terms and representing the combination of fixed

frequency terms fo1 through fko by a single frequency term fmin,

the output frequency can be expressed


fo = fmin + Af ci + 2 P 3 + ... Pk ). (3-24)
P2 2 3 P2 3 ... Pk)

The fundamental property on which sum-and-divide schemes

are based is that the frequency resolution of the synthesizer

output is finer than the resolution of inputs to the synthe-

sizer network. This is demonstrated in (3-24), where the

resolution of each input signal is Af, while the resolution of

the output waveform is Af divided by the product of divisors

P2 through Pk. The significance of this is realized in systems
where spurs associated with input signals are at frequency







47

separations from the carrier equal to the frequency resolu-

tions of the signals.

A related advantage of the sum-and-divide topology is the

noise reduction properties of the system with respect to

signals s2(t) through sk(t). Because the signals are divided

in the system output, noise modulated onto the carriers is

also divided. Thus, spectral purity requirements for signals

s2(t) through sk(t) are less stringent than the requirements

of the system output. Only s,(t), which contributes without

division to the system output, must meet the spectral purity

requirements of the system output signal.

A final issue to be considered in the sum-and-divide

synthesizer is the necessary range for each of the coeffi-

cients ci through ck. Assuming that all coefficients are

integers with minimum value 0, the tuning range of the

synthesizer is limited by cl. For a synthesizer range with

limits fin and f.ax, the required range for c, is


(C1)= int( fmax .min (3-25)


Maximum values for the remaining coefficients must be chosen

so that channel selection can be achieved throughout the

range. This can be achieved if the following condition is

met:


(ci)m = Pi 1.


(3-26)









Multi-Loop Synthesizer Structure

The multi-loop synthesizer design, the focus of this

dissertation, is a combination of the PLL and sum-and-divide

structures of the previous sections. Like the sum-and-divide

synthesizer, the structure presented here offers the advantage

of frequency resolution finer than the resolution of frequency

generators in the system. The multi-loop structure also takes

advantage of the filter characteristics of the PLL synthesiz-

er. The combination of approaches makes possible a synthesiz-

er with wider control loop bandwidth than conventional PLL

synthesizers with fewer components than sum-and-divide

systems.

Hybrid PLL and sum-and-divide approaches are discussed in

textbooks [6] and have been demonstrated in commercially

available test and measurement products [19]. However, these

approaches are predicated on discrete implementations and on

the use of bandpass filters in frequency summation mechanisms.

The design presented here is optimized for the integrated

circuit environment, and the use of bandpass filters is

avoided.

The description of the multi-loop synthesizer presented

in this section includes a discussion of the multi-loop

structure and derivations of expressions describing the

channel selection mechanism and the filter characteristics.

These topics are detailed in separate discussions below.









Structure Description

A block diagram of the multi-loop synthesizer is shown

Figure 3-5. The structure consists of k cascaded PLL synthe-

sizers linked with a common reference input at point R. Each

PLL unit i consists of a phase detector with gain KDi, a loop

filter with transfer function Fi(s) a VCO with gain constant

Kvi and a programmable loop divider with modulus Ni. All PLL

loops except loop 1 include a reference divider with modulus

Ri and an interstate divider at the loop output with modulus

Pi. The PLL synthesizers are cascaded such that the output of

each loop i is injected into the subsequent loop i-1 at the

loop divider input. The coupling mechanism is a frequency

summation operator, the characteristics of which are defined

in Chapter 5. Each PLL synthesizer output is divided in

frequency by the interstate divider modulus Pi before injec-

tion into the next stage. The system output at point O is the

output of loop 1.

In operation, each PLL performs the role of providing one

of the input signals of the sum-and-divide synthesizer of

Figure 3-4. The interstate dividers P2 through Pk function

identically to the interstate dividers of the sum-and-divide

synthesizer. Typically, frequency selection is controlled by

programming of the loop divider modulus values N1 through Nk.

Reference and interstate divider modulus values are normally

fixed for a given application.











PHASE
DETECTOR


LOOP
FILTER


VCO


REFERENCE
DIVIDER


PHASE


Block diagram of multi-loop synthesizer.


Figure 3-5.









Control of Output Frequency

In the multi-loop synthesizer, each PLL synthesizer unit

provides both frequency summation and frequency selection

functions. This role is described in the frequency summation

expression for a PLL in (3-21). Applying this relationship to

a loop i in the system of Figure 3-5, where the offset port

(port n2 in Figure 3-1) is driven by the divided down output

of loop i+l, the output frequency fi can be described:1


fi = f, i + f1 (3-27)
i Pi+1

In the expression, coarse channel selection is performed by

adjustment of loop divider modulus Ni. Additional adjustment

is provided by the fi+1 term which is combined with the fi term

in a frequency summing operation. This expression can be

applied recursively to define all loop output frequencies in

the system:


fo = f N + N-2 + .. k (3-28)
S R R2P P2 RkP1iP2".Pk)

The implied value for P, and R, in the expression is unity.

The frequency control expression of (3-28) is similar in

form to (3-24), the frequency control expression for the sum-

and-divide synthesizer. The expressions are made identical

when fmin in (3-24) is assigned value 0, Af is replaced with



1As convention in this paper, it is assumed that all
frequency summation operators perform subtraction. The output
of the interstate divider is subtracted from the VCO output.
This results in a positive summation term in expressions for
PLL output frequency in terms of reference and offset frequen-
cies.







52

fR, and the ci coefficients are replaced with the terms Ni/R,.

Thus, the sum-and-divide characteristic of the multi-loop

synthesizer is demonstrated. For the case where all Ri other

than R, are equal, and all loop divider values can be ex-

pressed as rational fractions with equal denominators, the

frequency resolution of the multi-loop synthesizer is less

than the resolution of any individual loop by the product of

interstate divider values P2 through P,.

As with the sum-and-divide system, care must be taken to

insure that the synthesizer tunes to all frequencies in the

band of interest. For the system of Figure 3-5, tunability

can be limited by tuning ranges of the VCO or loop divider

blocks in the system.

Attenuation of Spurs and Noise

A characteristic of the multi-loop synthesizer which is

critical to its implementation on a single integrated circuit

is the attenuation of undesired spectral components produced

in the system. This is especially important for noise and

spur sources located in loops other than loop 1 because all

components in these loops are integrated and tend to produce

high levels of noise and spurs. In this section, the impact

of the multi-loop design on spurs and noise generated at

various points in the system is analyzed.

The processes by which noise and spur energy are trans-

ferred to the system output spectrum are essentially linear

and can, therefore, be described by transfer functions. For

disturbances originating in loop 1, the transfers can be







53
described by expressions (3-8) through (3-11). For distur-

bances originating in loops other than loop 1, transfer

functions for loops between the source and system output can

be cascaded. For example, the transfer function for the

response of the loop 1 output o01(s) to a disturbance at the

loop i VCO
0o1(s) 1 of (s) i-1 oj (s) (3-29)
in0((s) H PJ 4n2jQs
neS (s) Pi A (s) J=1 n2 (\S)

where transfer function factors 4oi(s) /n,,i (s) and
can be expressed in the form of (3-8) and (3-9), respectively.

As shown in this expression, three separate mechanisms act to

attenuate noise produced at the loop i VCO. For disturbances

at frequencies below the unity gain frequency of loop i, the

high-pass action of the loop i PLL to disturbances applied at

the VCO acts on the disturbance. For disturbance frequencies

above the unity gain frequencies of loops 1 through i-1, the

low-pass action of these loops is effective. At all frequen-

cies, the disturbance is attenuated by the product of inter-

stage dividers P1 through Pi.

Expressions similar to (3-29) can be formulated for

disturbances from other sources. The effect on the system

output spectrum of disturbances to the loop i reference signal

can be described

0o0(s) 01 1 oj (S) ) (3-30)
S _(s) Pi .1 (s)j- Pj On2j(S)

For loop filter or phase detector noise currents, the expres-

sion is









oi((s) 1 0oi(s) ii 1 oJ (s) (3-31)
in3i(s) Pi n3i (s) j=1 Pj n2j(s)

In both of these expressions, all loops 1 to i contribute low-

pass characteristics to the total response. No high-pass

mechanism occurs. As in (3-29), disturbances are attenuated

by the product of interstate dividers P, through Pi.

System Specification

To completely specify the design of the multi-loop

synthesizer, it is necessary to select values for system

parameters including reference frequency, VCO ranges, loop

divider modulus ranges, interstate divider values and loop

filter characteristics. In this section, an example is

presented which demonstrates multi-loop system trade-offs to

meet performance objectives. The performance objectives are

those described in Chapter 2 and restated in Table 3-1. The

implementation and test of the example design presented here

are discussed in Chapters 4 through 8.

Table 3-1. Performance attributes of synthesizer system.

Specification Value

Frequency Range (MHz) 451.2 to 464.0
Channel Spacing (kHz) 12.5
Spurs (dBc/Hz) -70 max.
SBNR (dBc/Hz at offsets -120 max.
from the carrier 25 kHz or
greater)
Control Bandwidth 2-n25-10'
(radians/sec) _

Design values for the multi-loop synthesizer are deter-

mined largely by system spectral purity and tuning range







55
requirements and by performance capabilities of blocks which

comprise the system. While system performance requirements

have been discussed, block performance has not. This informa-

tion is presented here in the form of assertions to be

justified in later chapters. Both the design specification

and the assertions and limitations on which it is based are

presented below.

Assertions and Limitations

In this section are stated the assumptions on which the

design specification is based. The assumptions are classified

either as assertions or limitations. Assertions are defining

statements of performance of blocks in the system. Support

for assertions, where necessary, is stated directly or

referenced to the chapter of this dissertation where the topic

is presented. Limitations are constraints imposed on the

operation of elements in the system to simplify design or to

insure correct performance of the element in question.

Support for limitations is stated with the limitation.

Assertion 1: discrete loop 1 VCO. A VCO function can be

implemented using either a commercially available signal

generator or discrete tunable oscillator. In either case,

specifications for the VCO can be made to exceed the tuning

and spectral purity requirements of Table 3-1. Justification

for this statement can be found in published performance of

commercially available signal generators [23] and land-

mobile radio products which employ discrete VCO structures

[24].







56

Assertion 2: tunable integrated rinc-oscillators. VCO

structures for loops other than loop 1 can be implemented

using tunable ring-oscillator structures completely integrated

on an IC. The oscillators can be tuned over at least a 2:1

range in frequency with a maximum frequency of 60 MHz.

Spectral purity for frequencies below 60 MHz is -80 dBc/Hz or

better. The design and analysis of these structures is

presented in Chapter 6.

Assertion 3. frequency summation operator. Image-

balanced multiplier structures can be used to implement a

frequency summation operation on a class of periodic, symmet-

ric, non-sinusoidal waveforms. Analysis and design of these

circuits are discussed in Chapter 5.

Assertion 4: spurious frequency outputs. For any loop

in the system, the discrete output spectrum is dominated by

sub-harmonic spurs produced by fractional dividers or by

reference spurs. As shown in Chapter 7, this assumption is

not true for some frequencies in the test range. Extensions

to the system design to insure that this assumption can be

made true are also discussed in Chapter 7. In the design

presented below, this assumption is used as if true for all

frequencies of interest.

Assertion 5: reference signal spectrum. A reference

signal frequency of 12 MHz or greater is adequate to insure

that sideband noise from the reference source does not

dominate the system output spectrum. This statement is

supported by performance of existing land-mobile radio







57

equipment which produces transmit carriers and receiver local

oscillator signals through multiplication of the signals

produced by 12 to 19 MHz crystal oscillators [25]. The PLL

synthesizers used in the multi-loop system essentially perform

the same multiplication operation on the PLL reference signal.

Limitation 1: VCO quadrature outputs. Quadrature

signals must be available at the outputs all VCO circuits in

the system. This is the result of a requirement for quadra-

ture inputs to the frequency summation operator as stated in

Chapter 5. For the integrated VCO structures discussed in

Chapter 6, quadrature outputs are inherent to the design. For

the discrete oscillator used in loop 1, a separate phase-shift

circuit must be employed. This circuit is discussed in

Chapter 4.

Limitation 2: interstate dividers. Modulus values for

all interstate dividers must be integer powers of 2 greater

than or equal to 4. This is to facilitate generation of

quadrature outputs of the divider to drive the frequency

summation block inputs. Design of the dividers is discussed

in Chapter 4.

Limitation 3: loop dividers. The minimum divider

modulus is 4.0. For fractional loop dividers, the denominator

must be a power of 2. As discussed in Chapter 4, these

restrictions simplify design of the dividers.

Limitation 4: loop filters. All loop filter transfer

functions must be in the form of (3-2) where loop filter zero

z is at frequency no greater than 0.3 times the unity gain







58

frequency of the loop. For a loop filter with a single pole

pl, the pole must be at frequency at least 3.0 times the unity

gain frequency of the loop. For a loop filter with 2 poles,

the poles may be coincident at frequency 6.0 times the unity

gain frequency of the loop. The limitations on pole and zero

locations are imposed to insure loop stability. Resulting

phase margin for the loops as described is 50 degrees.

Synthesis of Values for System Variables

With the above assertions and limitations, specification

of system parameters can be accomplished using the algorithm

diagrammed in Figure 3-6. The method is applied below to the

system specified in Table 3-1.

Step 1: determination of f, and R, through Rk. Reference

frequency selection is governed by two constraints. First,

from Assertion 5, the frequency must be 12 MHz or greater.

The second constraint is determined by restrictions on channel

spacing and on divider modulus values. From (3-28) the system

frequency resolution Afo is equal to

Af = fR (3-32)
S DRk(PIP2"-Pk)

where Dk is the fractional denominator of loop divider Nk.

From Limitations 2 and 3, both the interstate divider modulus

values and the fractional denominator must be powers of 2.

Thus, reference frequency fR must be equal to the product of

system frequency resolution Afo, reference divider modulus Rk

and a power of 2. That is,














STEP 1 \
SELECT f, all R


Figure 3-6.


Flowchart describing the design procedure for
the multi-loop synthesizer.







60

f, = AfoRkR2, (3-33)

where I is a positive integer.

Some design choice is found in the selection of fR. The

choice is used here to limit the value for Rk and reference

divider modulus values to a power of 2. This, along with

(3-33), limits f, to the product of Afo and a power of 2. For

the 12.5 kHz requirement for Afo in Table 3-1, the minimum

allowed value for system reference fR is 12.8 MHz. This value

is chosen as the reference frequency.

Values for reference divider modulus values are chosen to

satisfy the trade-off of maximizing the reference frequency

for each loop (to minimize closed-loop gain) while insuring

that the loop divider modulus is at least 4.0 for the minimum

operating frequency for each loop (from Limitation 3). A

value of 4.0 for each modulus value satisfies the power of 2

requirement, maintains loop reference frequencies at rela-

tively high values and permits operation of each loop to a

minimum frequency of 12.8 MHz at the loop divider input.

Step 2, loop 1: definition of VCO range and P,. From

Table 3-1, the required range of the system output is 451.2 to

464.0 MHz. This is identically the required range of the loop

1 VCO. From the system block diagram in Figure 3-5, there is

no interstate divider at the loop 1 output. Therefore, no

value assignment is required for P1.

Step 3, loop 1: loop filter characteristics and A,. In

a typical design, loop 1 unity gain frequency oz would be

determined as a trade-off between settling time and VCO







61

spectral filtering requirements. For this design, O(i is

artificially specified in Table 3-1 as value 2n-25 103

radians/sec, making trade-offs unnecessary. From the discus-

sion in Chapter 2, the settling time of loop 1 is on order of

150 IS. From Assertion 1, the spectral purity of the loop 1

VCO is sufficient for system requirements without additional

filtering. As shown in (3-11), the filter action of loop 1

for the unity gain frequency as specified provides no attenua-

tion to the VCO spectrum in the region of interest (the region

where offset from the carrier is greater than 25 kHz).

The loop filter for loop 1 includes 2 poles of filtering

above the unity gain frequency. From Limitation 4, the poles

can be placed at location 6.0 times o,i. Two filter poles are

used in this application to provide maximum filtering of spurs

in the system. More than 2 poles are not feasible due to

constraints on loop stability and thermal noise in filter

components.

Step 4, loop 1: loop frequency resolution. From

Assertion 3, spurious output of a loop is limited by frac-

tional division spurs or reference spurs. From the discussion

on fractional division spur amplitude in this chapter, an

upper bound for fractional division spur amplitude in a loop

output spectrum can be approximated by the transfer function

gain of (3-9) at the spur frequency. A similar upper bound

can be set for reference spurs. From (3-21), it can be seen

that the loop frequency resolution, neglecting the offset term

from loop 2, is equal to the reference frequency divided by







62

the fractional denominator of the loop divider. From Limita-

tion 3, the fractional denominator is an integer power of 2.

Thus, the loop 1 frequency resolution is restricted to

products of the reference frequency fR and the inverse of a

power of 2. By calculating loop attenuation for each frequen-

cy choice using (3-9), it can be shown that a loop frequency

resolution of 3.2 MHz results a maximum spur value of -95 dB

and a frequency resolution of 1.6 MHz results in a maximum

spur value of -77 dB. The more conservative value of 3.2 MHz

is chosen.

Step 5, loop 1: system frequency resolution. This step

serves as a check to determine if a sufficient number of loops

has been specified for the system. For loop 1 in a single-

loop system, the loop frequency resolution and the system

frequency resolution are identical. The 3.2 MHz value for

resolution is much larger than the specified system resolution

of 12.5 kHz, implying that additional loops are needed.

Step 2, loop 2: definition of VCO range and P,. The

goal of this step is to maximize the interstate divider value

and to maximize the attenuation from the second loop to the

system output. At the same time, it is necessary to insure

continuous tuning of the system. Therefore, the frequency

range at the loop 2 interstate divider output must be greater

than or equal to the 3.2 MHz loop 1 frequency resolution.

From Assertion 2, the integrated loop 2 VCO is limited in

maximum frequency to 60 MHz and in ratio of maximum to minimum

frequency to 2:1. A range of 25.6 to 51.2 MHz satisfies the







63

maximum frequency range and tuning range requirements. The

interstate divider value P2 for this VCO range is 8, an

integer power of 2 as required from Limitation 2.

Step 3, loop 2: loop filter characteristics and ),. The

total attenuation required for spectral noise produced in the

loop 2 VCO is 40 dB, the difference between the VCO spectral

noise of -80 dBc/Hz and the system specification of -120

dBc/Hz. Applying (3-29), the transfer function from the loop

2 VCO to the system output, 42 dB attenuation can be achieved

for a unity gain frequency Ca2 with value 2'-200103

radians/sec. Because spurs produced in this loop are

attenuated by the interstate divider and the output loop in

addition to the loop 2 filter action, a single filter pole

above the unity gain frequency is sufficient. Per Limitation

4, the value of the pole is 3.0 times the unity gain

frequency.

Steps 4 and 5, loop 2: loop frequency resolution. Using

reasoning similar to that used in loop 1 but including the

effects of P2 and the loop 2 transfer function, a loop

frequency resolution of 800 kHz produces spurs at level -94

dBc at the system output. The 800 kHz loop spacing results in

a system resolution of 100 kHz. Because the system resolution

is higher than the required value of 12.5 kHz, a third loop is

needed.

Steps 1 through 6, loop 3. Because of the large amount

of attenuation provided by interstate dividers, design of loop

3 is not critical. For simplicity, VCO range, unity gain







64

frequency and filter requirements for the loop are specified

identically to loop 2. The loop 3 interstate divider value P3

can be assigned value 32 while maintaining continuous tuning.

The loop frequency resolution can be assigned value 3.2 MHz,

which results in the target system frequency resolution of

12.5 kHz. Because frequency resolution requirements are met,

the required number of loops in the system is 3.

Step 7: loop divider modulus ranges. The divider

modulus range can be found using the expression for the

frequency summing characteristic of a PLL with offset node in

(3-21). For loop 3, no offset value is present and the

divider range is determined solely by the reference frequency

and the VCO range. For reference frequency 3.2 MHz and VCO

range 25.6 MHz to 51.2 MHz, the required divider range is 8.0

to 16.0.

For loop 2, the offset produced by loop 1 must be

considered in addition to the reference frequency (3.2 MHz)

and VCO range (25.6 MHz to 51.2 MHz). The maximum magnitude

of the offset is the maximum loop 3 VCO frequency divided by

P3. This results in an offset with magnitude 1.6 MHz. A

maximum loop 2 divider modulus of 16.5 is required for maximum

loop 2 VCO frequency and positive offset. The minimum modulus

of 7.5 occurs for minimum VCO frequency and negative offset.

Using similar reasoning or the loop 1 divider, the offset

magnitude is 6.4 MHz. This results in a divider range of

34.75 to 36.75.









Design values for multi-loop synthesizer.


Design Parameter Minimum Actual
Requirement Design
Value
SYSTEM PARAMETERS
number of loops: 3 3
f, (MHz): 12.8 12.8
LOOP 1
VCO range (MHz): 451.2-464.0 451.2-464.0
unity gain freq. (rad/sec): 2n725000 27 25000
filter pole 1 (rad/sec): 2 -150000 2n-150000
filter pole 2 (rad/sec): 2n 150000 2 -150000
filter zero (rad/sec): 27-6000 2c 6000
loop divide range: 34.75-36.75 8.0-128.0
fractional denominator: 4 8
LOOP 2
VCO range (MHz): 25.6-51.2 25.6-51.2
unity gain freq. (rad/sec): 27-200-103 2X 200-103
filter pole 1 (rad/sec): 27c 600-103 27v 600- 10
filter zero (rad/sec): 27v 66- 10 27v 66- 10
loop divide range: 7.5-16.5 4.0-16.0
fractional denominator: 4 8
reference divide value: 4 4-5
interstate divide value: 8 4-64
LOOP 3
VCO range (MHz): 25.6-51.2 25.6-51.2
unity gain freq. (rad/sec): 27- 200-103 2n'200-103
filter pole 1 (rad/sec): 27f 600-103 2n7 600-103
filter zero (rad/sec): 27 66-103 27f 66-103
loop divide range: 8.0-16.0 4.0-16.0
fractional denominator: 4 8
reference divide value: 4 4-5
interstate divide value: 32 4-64


Design summary.


Design values for


the multi-loop


synthesizer are summarized in Table 3-2. The table contains

separate columns for the minimum required range of values for

each parameter and for actual design values implemented in the


circuit.


For many system parameters, actual ranges are


greater than minimum required ranges.


This results partly


from an attempt to design additional flexibility into the test


Table 3-2.







66

circuit and partly because the wider ranges are simpler to

implement in some cases.















CHAPTER 4
SYNTHESIZER IMPLEMENTATION

Overview

A single-chip, mixed bipolar-CMOS version of the multi-

loop synthesizer of Chapter 3 was designed and fabricated.

The goal of this exercise was to provide a vehicle for testing

the performance of the multi-loop system. In this chapter,

the implementation of the integrated circuit is described.

The uniqueness of the multi-loop synthesizer presented in

this dissertation is largely in the arrangement of elements

which comprise the system. Most of the circuits used in the

implementation of the system are known. Major exceptions to

this are the frequency summation block and the tunable ring

oscillator. These circuits are discussed in Chapters 5 and 6,

respectively. Other circuits which are original to this work

are identified in the course of the discussion.

Information in this chapter is presented in separate

discussions on the overall structure of the synthesizer IC,

the low-frequency loops (loops 2 and 3), the high-frequency

loop (loop 1), and the control and test functions. Circuits

common to all loops are discussed in the section on the low-

frequency loops.









Structure of the Integrated Circuit

Block Diagram Description

The synthesizer integrated circuit and the multi-loop

synthesizer system are shown in block diagram form in

Figure 4-1. The integrated circuit consists of five blocks:

three PLL frequency synthesizer units (loop 1, loop 2 and loop

3), the Serial-to-Parallel Interface (SPI), a test multiplexer

and buffer, and an input buffer for the reference signal. A

functional synthesizer system includes the integrated circuit,

an external loop filter and a voltage-controlled oscillator

(VCO). With the exception of supply and ground (not shown),

the only required inputs to the synthesizer system are the

serial programming bus and a reference clock input.

The circuit operates in accordance with the system

description in Chapter 3. Each PLL block in the figure

represents a single loop in the multi-loop synthesizer system.

Loops are cascaded via the offset input ports (OFFI and OFFQ

on loops 1 and 2). Programming for variable modulus dividers

is facilitated by the SPI, a serial-in, parallel-out shift

register.

Inputs and Outputs

Inputs and outputs of the chip are detailed in Table 4-1.

The table includes all signal ports shown in Figure 4-1 in

addition to the supply and ground ports. The order of the

ports in the table corresponds the physical arrangement of

bond pads on the integrated circuit substrate in counterclock-

wise order.











SERIAL BUS
MULTI-LOOP SYNTHESIZER IC

CEX DATA LATCH
A2
LOOP 3
REF PLL FREQ. SYNTHESIZER CTL(20:0) OUT(27:7)

RFOUTI RFOUTQ IOUT FLTR TUNE TSTA TSTE SERIAL-
iTO-
PARALLEL
JUMPER 1 INTERFACE
OFFI OFFQ
LOOP 2
< REF PLL FREW SYNTHESIZER CTL(22:0) OUT(50:28)

RFOUTI RFOUTQ IOUT FLTR TUNE TSTA TSTE


JUMPER B1 B2
OFFI OFFQ
LOOP 1
REF DIVIDER, PHASE DET. &OFFSET CKTS. CTL(15:0) /OUT(66:51)
FOR PLL FREQ. SYNTHESIZER W/ OFFSET \
IOUT INX IN TST

E Cl C2 B1 A2 E/ OUT(1

OUT EN C1 C2 B1 B2 A1 A2
CTL(4:0) OUT(6:2)
INPUT TEST TESTA AUX1 AUX2
BUFFER BUFFER/ TESTAX -
MUX TESTB --
IN TESTBX --


REF IN IN

RF OUT
OUT TUNE OUT
LOOP FILTER VCO



Figure 4-1. Block diagram of the multi-loop synthesizer
implementation.









Table 4-1.


70

Synthesizer integrated circuit interconnect
definitions.


Node Type Function Limits

GND1 ground ground -- Loop 1
IOUT1 output 200 1A charge pump 0.5 V min.
output -- Loop 1 VMULT 0.5 V max.
VMULT supply high voltage supply 10.0 V max.
for Loop 1 charge 5.0 V min.
pump
CLK input SPI clock input high: Vsup 0.5 V
low: 0.5 V
CEX input SPI active-low chip high: Vsup 0.5 V
enable low: 0.5 V
DATA input SPI data input high: Vsup 0.5 V
low: 0.5 V
TESTAX output negative polarity high-impedance
test output load only
TESTA output positive polarity high-impedance
test output load only
TESTBX output negative polarity high-impedance
test output load only
TESTB output positive polarity high-impedance
test output load only.
REF input input for system AC coupled:
reference 200 mVpp
DC coupled:
OV min., SUP3 max.
GND3 ground ground -- Loop 3,
ref. input buffer
SUP3 supply supply -- Loop 3, Vsp: 3.3 to 5.0 V
ref. input buffer
IOUT3 output switched 25, 50 gA 0.5 V min.
charge pump output Vsup 0.5 V max.
-- Loop 3
TUNE3 input VCO tuning port -- Vup 2.5 V min.
Loop 3 Vsup 0.5 V max.
FLTR3 input/ integrated loop
output filter -- Loop 3
VLN3 supply low-noise supply -- Vp: 3.3 to 5.0 V
__Loop 3









Table 4-1 -- continued.

Node Type Function Limits

GND2 ground ground -- Loop 2
SUP2 supply supply -- Loop 2 Vsup: 3.3 to 5.0 V
IOUT2 output switched 25, 50 1A 0.5 V min.
charge pump output Vsup 0.5 V max.
-- Loop 3
TUNE2 input VCO tuning port -- Vsup 2.5 V min.
Loop 2 V.P 0.5 V max.
FLTR2 input/ integrated loop
output filter -- Loop 2
VLN2 supply low-noise supply -- Vup: 3.3 to 5.0 V
Loop 2
SUP4 supply supply -- SPI Vsp: 3.3 to 5.0 V
AUX1 output SPI buffered output low: 0.0 V
high: Vsup
AUX2 output SPI buffered output low: 0.0 V
high: Vsu
GND4 ground ground -- SPI and
test buffer/mux
SUP1 supply supply -- SPI and Vsp: 3.3 to 5.0 V
test buffer/mux
IN1X input negative polarity AC coupled only.
input -- Loop 1 differential:
100 mVpp
unipolar:
bypass or leave
unconnected
IN1 input positive polarity AC coupled only.
input -- Loop 1 differential:
100 mVpp
unipolar:
200 mVpp


All voltages in the table are referenced to circuit

ground unless otherwise noted. Ground ports on the chip share

a common voltage (0.0 V). Supplies on the chip except high

voltage supply VMULT share a common voltage Vup. For inputs







72

and supplies, the listed values listed indicate the maximum

allowed range of values to be applied to the port. For

outputs, the limit values represent a guide for successful

usage of the component.

Circuit Design, Signal Routing and Layout Techniques

An attempt was made to be consistent in the use of

design, layout and routing techniques throughout the implemen-

tation. In the area of circuit design, digital signal-path

and test circuits are implemented using a low voltage (0.13 V

peak-to-peak), fully differential version of emitter-coupled

logic (ECL). Details of this type of design are discussed in

Appendix B. Control circuits are implemented using standard

CMOS logic.

Several techniques are used throughout the design to

minimize parasitic coupling of signals. Coupling though

supply and ground conduction is minimized through the use of

separate supply and ground ports for each loop. In addition,

the VCO and wave-shaping circuits in loops 2 and 3 are

connected to supplies separate from other circuits in the

loops (VLN2 and VLN3). Minimization of signal coupling is

accomplished by the use of the ECL techniques of Appendix B

and fully differential signal routing on virtually all non-

static signals on the chip.

To reconcile the incompatible goals of testability and

minimization of signal routing, critical signals in the system

are made available for test through the use of buffered multi-

plexers. A two-level system is employed, with the output







73

stage represented by the test buffer and multiplexer block in

Figure 4-1. A second level of buffered multiplexers is

resident in the loop circuits. Accessible circuit nodes and

multiplexer programming are described in the section on

control and test.

Schematic Conventions

Throughout this chapter, circuits are described using

simplified diagrams of the type shown in Figure 4-1. A list

of conventions used in interpreting the schematics is shown in

Figure 4-2. In addition to these conventions, simplifications

typically include the elimination of level-shift structures,

supplies, grounds and bias sources. Detailed circuit schem-

atics used in mask generation of the IC can be found in

Appendix A.

In the ECL circuits used in this chip, the technique of

gate merging is applied extensively to minimize propagation

delay, power dissipation and circuit area. Merged gates are

indicated in the simplified layout by suffixes on circuit

identifiers of the same name. For example, for a flip-flop

input merged with an AND gate, the flip-flop might be called

12 and the AND gate I2A. Merged gates are discussed in the

description of ECL circuit techniques in Appendix B.

Low-Frequency Loops

Block diagrams for the low-frequency synthesizer loops 3

and 2 are shown in Figure 4-3 and Figure 4-4, respectively.

Each circuit comprises a complete PLL frequency synthesizer,

including VCO, loop filter, loop divider, reference divider,











> SINGLE CONDUCTOR


DIFFERENTIAL-SIGNAL CONDUCTOR
PAIR

MULTI-CONDUCTOR BUS




O BOND PAD

-- MULTIPLEXER-ACCESSED TEST POINT



--/A A/ CONNECTOR

Figure 4-2. Key for schematic diagram conventions and
symbols.


phase detector and output circuit. The two structures are

identical expect for the image-balanced mixer used to provide

a frequency offset mechanism in loop 2. Loop 3 does not have

an offset mechanism.

The operation of the circuits is consistent with opera-

tion of PLL type frequency synthesizers. That is, the output

frequency is a function of the frequency applied to the

reference port and the divider modulus values in the system.

For loop 3, the output frequency can be described by

N3
fou3 = fref p R (4-1)

where fout3 is the output frequency of the system at nodes RF

OUTI and RF OUTQ in Figure 4-3, fref is the frequency of the

signal applied to node REF, and N3, P3 and R3 are the modulus



























































Figure 4-3.


Block diagram of Loop 3 PLL synthesizer.























CTL(O)


JUMPER


IF OUTI


INI INQ


INHI INHQ
WAVE-
TUNE SHAPING
BUFFER
OUTI OUTQ


Block diagram of Loop 2 PLL synthesizer.


Figure 4-4.







77

values for the loop divider, the output divider and the

reference divider, respectively. The loop 2 expression is

similar, but includes an offset term:


fout2 fref'-N ) + foffset2 (4-2)

Here, foffset2 is the frequency of the signal applied to the OFFI

and OFFQ ports of the circuit in Figure 4-4.

The diagrams in Figure 4-3 and Figure 4-4 have been

simplified to show only signal-path circuits. In addition to

the typical loop components, these include wave-shaping

circuits at the loop outputs and at the input to the image-

balanced mixer in loop 2. These circuits, necessary for

correct offset mechanism operation, are described in detail in

Chapters 5 and 6. Not shown in the diagrams are bias sources

and output multiplexers. These blocks, shown in the detailed

schematics in Appendix A, were omitted from Figure 4-3 and

Figure 4-4 so that the relationships among signal path

circuits could be shown more clearly. Points accessed by the

test multiplexers are shown in the simplified diagrams.

Access to the test points is described in the section on

control and test.

Control of the loop 2 and loop 3 synthesizers is accom-

plished via the SPI. Control inputs to the blocks in

Figure 4-3 and Figure 4-4 are identified by the node name CTL.

The index numbers following the CTL node names are local to

each loop structure and do not correspond to index numbers for

the SPI block in Figure 4-1. Not all control lines for loops







78

2 and 3 are shown in Figure 4-3 and Figure 4-4. Bias switches

and controls for the test multiplexers are not shown in the

diagrams, but are described in the section of this chapter on

the control and test.

In the remainder of this section, more detailed descrip-

tions are presented for some key blocks and concepts in the

low-frequency loops. These include the dividers, the phase

detector and the loop filter. The image-balanced multiplier

and the frequency offset operation are described in Chapter 5.

The VCO and wave-shaping circuits are described in Chapter 6.

Reference Divider

The reference divider, shown in Figure 4-5, is a synch-

ronous ECL counter with modulus selectable between integer

values 4 and 5 via the SPI. As shown in the diagram, the

circuit consists of three D flip-flops Ii through 13 and two

AND gates I1A and I3A. The arrangement shown in the figure is

commonly used as a first stage in high-speed prescaler

circuits for frequency synthesis applications [26].

In operation, a negative-to-positive polarity transition

is produced at node OUT for each R negative-to-positive of

transitions of the waveform applied to the input node CLK,

where R is the modulus value, selectable between 4 and 5 via

control input SEL5. For logic 0 applied to SEL5, the output

of gate I3A and, therefore, the output Q of flip-flop 13, are

held at logic 0 under all conditions. For this case, flip-

flops Il and 12 and gate IlA form a counter with modulus 4.

When SEL5 is assigned logic 1, the output of flip-flop 13

























Figure 4-5. Block diagram of reference divider.


tracks the output of flip-flop 12 with a delay of one cycle of

the input clock. Under this condition, a counter with modulus

5 is created.

The counter is implemented using ECL circuitry of the

type described in Appendix B. The approximate maximum

operating frequency is 80 MHz.

Output Divider

The design of the output divider is constrained by system

requirements for power of 2 programmability and for dual

outputs separated by 1/4 cycle time delay. The circuit used

to realize these requirements is shown in Figure 4-6. To the

author's knowledge, this circuit is original to the study

presented here.

The structure and operation of the circuit can be seen

from Figure 4-6. The circuit consists of six flip-flops and

three multiplexers, with the flip-flops arranged in three

cascaded, synchronous stages. Flip-flops Ii and 12 and


























CTL(2)

2:1 MUX
-SEL
I1A
IN1 OUT
INO


CTL(1>-


CTL(O)>---
CTL(1)>---
I


-F


D Q
11

CLK Q)


4:1 MUX
CTLO
CTL1


INO OU -OUTQ
IN1
IN2 7
IN3


__ __ 4


________.


D Q
12

CLK QX


D Q
13


e


D Q
14

CLK Q>


CTL(O) --
CTL(1) -

Y-

I


4:1 MUX
CTLO
CTL1


IND OUT- OUTI
IN1
IN2 18
IN3


CLK> I


Block diagram of the output divider.


n


D Q D Q -
15 16

CLK Q1 I CLK Qt


Figure 4-6.


SCLK I F







81

multiplexer I1A form the input stage of the counter, a

programmable stage with modulus selectable between 2 and 4

depending on the state of control bit CTL(2). The output Q of

flip-flop 12 provides the clock for the second stage, a fixed

modulus-four stage comprised of flip-flops 13 and 14.

Similarly, this stage clocks the final stage, a fixed modulus-

four stage comprised of flip-flops 15 and 16. Multiplexers 17

and 18, controlled by bits CTL(O) and CTL(1), provide power-

of-two scaling for the circuit outputs.



CLK ij--nj

OUTI

OUTQO

-> <- TOUT
4

Figure 4-7. Input and output waveforms versus time for the
output divider in divide by 4 mode.


The key features of the divider, power of 2 program-

mability and dual outputs with 1/4 period separation, are

produced by the combined actions of the cascaded divide by 4

stage configuration and the dual output multiplexers. The 1/4

period separation of the outputs is demonstrated in the timing

diagram of Figure 4-7 for the modulus 4 case. The time

separation is produced as a property of the divide by 4

structure. Power of 2 programmability is achieved by manipu-

lating the choice of stage outputs using the multiplexers.







82

For multiplexer I1A set for first divider stage divide by 2

operation, total divider values of either 8 and 32 are

achieved. If the second stage (13 and 14) outputs are

selected by the output multiplexers 17 and 18, a modulus of 8

results. Selection of third stage (15 and 16) outputs results

in a modulus of 32. In similar manner, modulus values of 4,

16 and 64 can be produced if the first stage modulus is set to

4.

The required maximum operating frequency for the output

divider is approximately 60 MHz. The estimated maximum

operating frequency, based on analog simulation of the

circuit, is on order of 150 MHz.

Loop Divider

The system requirement for the loop divider block is for

full programmability over a multi-octave range with fractional

step size. In addition, the circuit is required to operate at

relatively high frequencies and must be suitable for implemen-

tation using the ECL techniques described in Appendix B. An

approach uniquely suited to the loop divider requirements is

the asynchronous feedback counter [27]. The circuit is

shown in Figure 4-8.

Loop divider step size and range requirements. Step size

and range requirements for the loop divider are defined by

system requirements. For circuits in loops 2 and 3, the

minimum step size is 0.25. The maximum required range of 7.5

to 16.5 occurs for the loop 2 circuit in a three-loop system.











































Figure 4-8.


L(9)


Block diagram of the loop divider.







84

These requirements are exceeded in the design of Figure 4-8,

where the modulus range is 4 to 32 with a minimum of step size

of 0.125.

Loop divider structure and operation. The circuit can be

described from the simplified diagram of Figure 4-8. It is

comprised of a programmable input stage Il driving a cascaded

series of toggle-connected flip-flops (13, 15, 17, 19 and

Ill). A series of feedback gates (12, 14, 16, 18 and 110)

manipulate the signal at feedback port FBK of Il based on the

states of the flip-flops. Output multiplexer 116 facilitates

selection of the divider output from among several ports in

the flip-flop chain.

In operation, the toggle-connected flip-flop string

performs dual roles as a power of 2 counter and as a sequencer

for controlling Ii, the first stage of the divide by 4 to 8

block. The first stage can be programmed to produce a divider

modulus between 4 and 8 as a function of block programming

inputs CTLO 'and CTL1 and feedback input FBK as shown in

Table 4-2.1 As seen in the table, for a given set of values

for CTLO and CTL1, the Ii block can be treated as a dual-

modulus counter. In this interpretation, the role of FBK is

to modify the modulus by one count, either up or down depend-

ing on the initial modulus. In the divider of Figure 4-8, the



IControl line notation is complicated. Nodes CTLOX and
CTL1X in the table are inverted versions of lines CTLO and
CTL1 shown in Il. The inversion is necessary to demonstrate
the Grey code relationship in the table. Lines CTLO and CTL1
on Il correspond to control lines CTL(3) and CTL(2), respec-
tively, in the loop divider schematic.







85

value of FBK on Il at an instance in time is determined by the

states of flip-flops 13, 15, 17, 19 and Ill and by the states

of programming lines CTL(4) through CTL(9). An average

modulus for counter block Il and for the entire counter can be

found by integrating the instantaneous modulus over an integer

number of cycles of operation.

Table 4-2. Divide-by-four-to-eight programming.

CTLOX CTL1X FBK Modulus

0 0 0 4
0 0 1 5
0 1 1 5
0 1 0 6
1 1 0 6
1 1 1 7
1 0 1 7
1 0 0 8

Fractional division operation of the counter is facili-

tated by the inherent power of 2 relationship of the divider

chain (13, 15, 17, 19 and Ill) and by multiplexer 116. For a

counter output taken at the output of Ill, the counter modulus

is programmable over the range 128 to 256 with step size equal

to unity. If the output node is designated at a different

point in the divider chain, both the divider modulus value and

the step size are reduced by the factor 2', where I is the

number of flip flops in the chain between the designated

output node and the output if Ill. For example, an output

designated as the output of flip-flop I5 results in a modulus

range of 16 to 32 with a step size of 0.125. Multiplexer 116







86
facilitates selection of the output node from among outputs of

Il, 13 and 15. This allows adjustment of modulus range and

step size.

Three features of the circuit of Figure 4-8 make it well

suited to synthesizer applications. First, all gates in the

circuit have low fan-in, facilitating implementation using ECL

techniques. For comparison, the maximum fan-in in a synchro-

nous counter is equal to the number of flip-flops in the

circuit.

A second advantage of the counter architecture is that

while the circuit is asynchronous, the maximum clock frequency

for any flip-flop in the circuit approaches the toggle speed

of the flip-flop. This is a result of the design of the flip-

flop and feedback networks, where the output of each stage of

the feedback network is synchronized by its corresponding

flip-flop. This approach is advantageous for high-frequency

or low-power design, since only the high speed stage Il

requires low propagation delay circuits. The flip-flop and

feedback networks tolerate longer propagation delay and can

be implemented using structures with relatively high propaga-

tion delay and low power dissipation.

A third advantage of the asynchronous feedback counter is

built-in fractional division operation. Using this feature,

the fractional division requirement of Chapter 3 can' be

satisfied.

The divider of Figure 4-8 is somewhat simplified compared

to the actual circuit in Appendix A. In the actual circuit,







87

the flip-flops are configured as cascaded divide by 4 stages

instead of toggle stages as shown in Figure 4-8. The divide

by 4 stages in the actual circuit, configured so that logic

state progressions are identical to those of toggle stages,

were designed to minimize power dissipation through reduction

in the number of required level shifts. The toggle stages are

shown in Figure 4-8 to provide a clearer explanation of

circuit function.
r 1


Figure 4-9. Block diagram of divide by 4 to 8.


Divide by 4 to 8 structure and operation. The divide by

4 to 8 is shown in Figure 4-9. From the simplified diagram,

the circuit consists of three synchronously-connected flip-

flops (14, 15 and 17) and several gates. As in previous







88

discussions, gates with the same identifiers but different

suffixes are implemented as merged structures.

The circuit shown in Figure 4-9 evolved from a program-

mable divider with modulus selectable between 2 and 4 as a

function of CTL1 and a feedback node which enabled operation

with modulus 3. Flip-flops 14 and 15 and gates Il, I1A, 12,

13, I3A and I4A formed this structure. In the original

arrangement, the feedback node was at the outputs of I1B and

I3B in the circuit of Figure 4-9.

Operation with modulus values in the range 4 to 8 is

achieved with the addition of flip-flop 17 and gates IlB, IlC,

I3B, I3C, 16 and I6A. The additional blocks are arranged to

operate as a synchronous version of the toggle flip-flop and

feedback structure of the circuit in Figure 4-8. Programming

for the stage is described in Table 4-2.

Loop divider programming. Programming of the loop

divider is a two step process, requiring calculation of the

correct feedback coefficients (CTL(2) through CTL(9)) and

scaling factor (CTL(O) and CTL(1)). The scaling factor is the

value by which the desired modulus must be divided to place it

in range of the base modulus range of the divider. The base

range is defined here as the range of possible modulus values

if the output is taken from the final flip-flop in the chain

(Ill in Figure 4-8). For the divider of Figure 4-8, the base

range is 128 to 256. The scaling factor, reflecting the

action of the output multiplexer 116 in the circuit, is

programmed according to Table 4-3.









Table 4-3. Loop divider scaling factors -- loops 2, 3.

CTL(0) CTL(1) Scaling Factor

0 0 test mode
0 1 0.03125
1 0 0.0625
1 1 0.125


Feedback coefficients CTL(2) through CTL(9) assign

divider modulus according to a Grey code. A partial table of

feedback coefficients and their corresponding modulus values

is shown in Table 4-4. The modulus values in the table refer

to the base modulus of the counter, found by dividing the

desired modulus value by the scaling factor found in the first

part of the calculation. Because of the control line naming

convention in the circuit design, it is necessary to invert

bits CTL(2) and CTL(3) to maintain the Grey code. This

inversion is noted by an X suffix on those lines in the table.

Programming of the counter can be best understood through

an example. Consider the case where the desired modulus value

of a counter is 8.25. The scaling factor for this case is

.0625, resulting in a base modulus of 133. From Table 4-3,

values of 1 and 0 for scaling coefficients CTL(0) CTL(1),

respectively. The base modulus value corresponds to lines 9

and 10 of Table 4-4, resulting in feedback coefficient words

00001101 and 00001111 for bits CTL(2)X, CTL(3)X, CTL(4)

CTL(5), CTL(6), CTL(7), CTL(8) and CTL(9). Two correct

programming words result from each programming calculation, a

result of the design of the first stage of the counter.









Table 4-4.


Partial look-up table for


90

loop divider feed-


back coefficients -- Loops 2 and 3.

Line CTL CTL CTL CTL CTL CTL CTL CTL Base
(2) (3) (4) (5) (6) (7) (8) (9) Mod-
X X _______ulus

0 0 0 0 0 0 0 0 0 128
1 0 0 0 0 0 0 0 1 129
2 0 0 0 0 0 0 1 1 129
3 0 0 0 0 0 0 1 0 130
4 0 0 0 0 0 1 1 0 130
5 0 0 0 0 0 1 1 1 131
6 0 0 0 0 0 1 0 1 131
7 0 0 0 0 0 1 0 0 132
8 0 0 0 0 1 1 0 0 132
9 0 0 0 0 1 1 0 1 133
10 0 0 0 0 1 1 1 1 133
11 0 0 0 0 1 1 1 0 134

253 1 0 0 0 0 0 1 1 255
254 1 0 0 0 0 0 0 1 255
255 1 0 0 0 0 0 0 0 256

Cycle 512 256 128 64 32 16 8 4
Lngth


The complete


version of


Table 4-4 would be unwieldy,


containing 256 lines. A more practical approach to assignment

of feedback coefficients is through the use of an algorithm.

One such algorithm, based on the periodicity of the columns in

Table 4-4, is shown in flow chart form in Figure 4-10. For

the counter of Figure 4-8, the number of coefficients N is

equal to 8 (CTL(2) through CTL(9)). The minimum base modulus

MMIN is 128. The only other required input is the desired

base modulus M.

Phase Detector

The phase detector block combines the basic phase-

frequency detector logic described in [5, p. 115] with a high-

impedance charge pump. The approach is one of many which have










DEFINE
M := BASE MODULUS
MMIN:= MINIMUM BASE MODULUS
N := NUMBER OF COEFFICIENTS
C(N)...C(1) := COEFFICIENTS
L := LINE NUMBER
CL := CYCLE LENGTH
I:= INDEX NUMBER
FR() := OPERATOR -- FRACTIONAL PART OF ARG,
CTL(2)...CTL(N) := FEEDBACK COEFFICIENTS


ASSIGN
M, MMIN, N

L ->2*(M-MMIN)
I -> 0


NO
I
YES
I -> I + I
CL -> 2 1+1











CTL 21X -> CN)
CTL 3 X-> C(N-)
CTL(4) -> C(N-2) >


Flowchart of feedback coefficient algorithm.


Figure 4-10.







92

appeared in literature and in products in recent years. It

was chosen because it can be completely integrated, it has

inherent frequency steering, and the noise output is inher-

ently low. These advantages are demonstrated later in this

section.


Figure 4-11. Block diagram of phase detector.


The circuit, shown in Figure 4-11, includes a logic

section and a charge pump. The logic section is comprised of

two resetable D flip-flops Il and 12 and an AND gate 13. The

charge pump 14, shown in symbolic form in the figure, is a

switchable current source with separate enable and control

inputs.

In operation, the charge pump is controlled by the logic

circuit and by enable inputs ENH and EN (control lines CTL(1)


IOUT







93

and CTL(2) in Figure 4-3 and Figure 4-4). When the applicable

enables are at logic 1, a logic 1 at a flip-flop Q output

causes non-zero output current to flow from charge pump output

IOUT. A logic one at flip-flop Il causes the charge pump to

source current, while a logic 1 at 12 causes the circuit to

sink current. When flip-flop outputs are simultaneously high

or low, the net charge pump output is 0.

The enable lines in the charge pump allow the charge pump

current to be adjusted to either of two values, and contribute

to system testability. When EN is set high and ENH is set

low, the on state output current is 25 gA. Setting EN and ENH

high simultaneously produces an output current of 50 tA.

Output current is disabled for EN low. Two values of output

current are necessary to insure that stability is maintained

in the PLL over the entire operating frequency range.

The phase detection operation of the detector is accom-

plished in the logic portion of the circuit. The quantity

measured is actually not phase but the difference in time

between rising edges of signals applied to the UP and DOWN

inputs. Beginning with the condition where both flip-flop Q

outputs are at logic 0, a rising edge on the UP node sets

output Q of Il to logic 1 and enables the up, or source, side

of the charge pump. Conversely, a leading edge on node DOWN

sets Q of 12 to logic 1 and enables the down, or sink, side of

the charge pump. The condition where Q outputs of Il and 12

are simultaneously high is transient, leading to an asynchro-

nous reset of both flip-flops via gate 13.























I
Figure 4-12. Phase detector transfer curve.

A transfer curve of output current versus phase (or time)

error can be developed based on the amount of charge released

by the circuit in a cycle of the input. This curve is shown

in Figure 4-12. In the figure, the output current is the

average output current over a cycle, where a cycle is defined

on one of the periodic inputs applied to the phase detector

input ports, say the one at port UP. Linear phase detection

is demonstrated for a phase difference at port UP with

reference to port DOWN of between -2K and 2K radians. In this

region, the average current varies linearly between -I and I

with phase difference, where I is the magnitude of the charge

pump current. Outside of the -2n to 2n region, the relation-

ship between phase error and output current is not linear.

However, the sign of the phase error matches the sign of the

output current for all values of phase error. A phase

detector that exhibits this characteristic is said to exhibit

"frequency steering."


PHASE
ERROR
(RAD)


ZZ




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