• TABLE OF CONTENTS
HIDE
 Title Page
 Acknowledgement
 Table of Contents
 Abstract
 Introduction
 BICMOS design optimization for...
 Substrate PNP transistor model...
 MMSPICE benchmarking
 Statistical simulations and sensitivity...
 Summary and suggestions for future...
 Appendix
 Reference
 Biographical sketch
 Copyright






Title: Modeling and technology CAD for scaled BICMOS integrated circuits
CITATION THUMBNAILS PAGE IMAGE ZOOMABLE
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Permanent Link: http://ufdc.ufl.edu/UF00082209/00001
 Material Information
Title: Modeling and technology CAD for scaled BICMOS integrated circuits
Physical Description: vi, 190 leaves : ill. ; 29 cm.
Language: English
Creator: Cho, Hae-Seok, 1961-
Publication Date: 1993
 Subjects
Subject: Bipolar integrated circuits -- Design and construction   ( lcsh )
Semiconductors -- Design and construction -- Data processing   ( lcsh )
Electronic circuit design -- Data processing   ( lcsh )
Electrical Engineering thesis Ph.D
Dissertations, Academic -- Electrical Engineering -- UF
Genre: bibliography   ( marcgt )
non-fiction   ( marcgt )
 Notes
Thesis: Thesis (Ph. D.)--University of Florida, 1993.
Bibliography: Includes bibliographical references (leaves 186-189).
Statement of Responsibility: by Hae-Seok Cho.
General Note: Typescript.
General Note: Vita.
 Record Information
Bibliographic ID: UF00082209
Volume ID: VID00001
Source Institution: University of Florida
Rights Management: All rights reserved by the source institution and holding location.
Resource Identifier: aleph - 001922329
oclc - 30495386
notis - AJZ8141

Table of Contents
    Title Page
        Page i
    Acknowledgement
        Page ii
    Table of Contents
        Page iii
        Page iv
    Abstract
        Page v
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    Introduction
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    BICMOS design optimization for supply voltage scaling
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    Substrate PNP transistor modeling
        Page 51
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    MMSPICE benchmarking
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    Statistical simulations and sensitivity analysis using MMSPICE/SUMM
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    Summary and suggestions for future work
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    Appendix
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    Reference
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    Biographical sketch
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    Copyright
        Copyright
Full Text












MODELING AND TECHNOLOGY CAD FOR
SCALED BICMOS INTEGRATED CIRCUITS















By

HAE-SEOK CHO


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF DOCTOR OF PHILOSOPHY




UNIVERSITY OF FLORIDA


1993















ACKNOWLEDGEMENTS


I would like to express my sincere gratitude to my

advisor, Professor Jerry G. Fossum, for giving me an oppor-

tunity to work as one of his students on interesting

research topics. Without his guidance, encouragement, con-

cern, and support, this work could not have reached frui-

tion.

I also would like to thank the other members of my

supervisory committee, Professors Robert M. Fox, Mark E.

Law, Shakir A. Abbas, and Ulrich H. Kurzweg, for their

willingness to serve on my committee.

I am also indebted to many people I have interacted

with during my graduate study. I cannot mention all of

them, but I should mention Drs. H. Jeong, Y. Kim, J. Choi,

J. Jin, S.-G. Lee, H. Cho, Y. Eo and Messrs. G.-B. Hong,

Y. Chung, T. Kim, K. Green, D. Suh, H. Park, P. Yeh, S.

Krishnan, J. Brodsky. My deepest gratitude goes to my wife

Hyunjoo, son Daniel, and daughter Grace, whose endless

love, support, and encouragement were most valuable to me.

I thank my mother and parents-in-law for their encourage-

ment and prayers. My highest thank goes to my Lord Jesus

Christ whose overflowing blessings helped me through dif-

ficult times in my life. I also thank the Semiconductor

Research Corporation for the financial support.















TABLE OF CONTENTS


Page

ACKNOWLEDGEMENTS ....................................... ii

ABSTRACT ............................... ................ v

CHAPTERS

1 INTRODUCTION ..................................... 1

2 BICMOS DESIGN OPTIMIZATION FOR SUPPLY VOLTAGE
SCALING ......................................... 10

2.1 Introduction ................................... 10
2.2 Conventional BiCMOS Gate Operation ............. 13
2.3 Voltage Scaling ................................ 19
2.4 Design for "Near-Full-Swing" Operation at
Scaled VDD .................................. 24
2.5 Polysilicon Emitter Design for Voltage Scaling. 36
2.6 Scaled BiNMOS .................................. 44
2.7 Summary.................................... .. 49

3 SUBSTRATE PNP TRANSISTOR MODELING ................. 51

3.1 Introduction ................................... 51
3.2 Initial Model Development ...................... 53
3.3 PISCES Simulations ............................. 57
3.4 Semi-Empirical Modeling ........................ 73
3.5 MMSPICE Implementation/Application ............. 83
3.6 Summary ........................................ 86

4 MMSPICE BENCHMARKING .............................. 89

4.1 Introduction ................................... 89
4.2 Parameter Specification for Comparable Models.. 91
4.3 Parameter Tuning -for the MMSPICE BJT Model..... 92
4.3.1 dc Parameter Tuning ......................... 93
4.3.1.1Medium-Current Range ................... 93
4.3.1.2 High-Current Range .................... 94
4.3.1.3 Low-Current Range ..................... 96
4.3.2 ac and Transient Parameter Tuning .......... 96


iii









4.4 Model Scalability .............................. 105
4.5 Model Convergence and Accuracy ................. 111
4.6 Run-Time Comparison ............................ 115
4.7 Summary ........................................ 120

5 STATISTICAL SIMULATION AND SENSITIVITY ANALYSIS
USING MMSPICE/SUMM .............................. 122

5.1 Introduction.................................... 122
5.2 Statistical (Monte Carlo) Simulation........... 125
5.2.1 Selection of Input Variables and Correlation
among Model Parameters .................. 126
5.2.2 Methodology for the Statistical Simulation. 129
5.2.3 Statistical Simulation Results ............. 135
5.3 Sensitivity Analysis Using MMSPICE and SUMM.... 154
5.3.1 Device Performance Correlations ............ 155
5.3.2 Methodology for the Sensitivity Analysis ... 160
5.3.3 Circuit Sensitivity Simulation Results ..... 168
5.4 Summary ........................................ 175

6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK ........... 177

APPENDIX

APPENDIX A ........................................... 180

REFERENCES ............................................. 186

BIOGRAPHICAL SKETCH .................................... 190














Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy


MODELING AND TECHNOLOGY CAD FOR
SCALED BICMOS INTEGRATED CIRCUITS

By

HAE-SEOK CHO

August 1993




Chairman: Dr. J. G. Fossum
Major Department: Electrical Engineering


This dissertation describes development and assess-

ment of bipolar junction transistor (BJT) models and sim-

ulation tools for technology computer-aided design (CAD)

of scaled BiCMOS integrated circuits (ICs). Optimization of

the conventional BiCMOS design for supply voltage scaling is

analyzed using MMSPICE, a semi-numerical mixed-mode device/

circuit simulator. Device/circuit simulations give physical

insights concerning design optimization, and suggest optimal

design involving variations in gate layout and polysilicon

emitter process. The optimal design is shown by simulations

to be superior to the counterpart CMOS gate at low supply

voltage (3.3 V) in regard to propagation delay. A simple yet

accurate model for the parasitic substrate pnp BJT, which

can be activated by (quasi-) saturation of the npn tran-









sistor and hence can be problematic for reliable BiCMOS

gate operation, is developed. The semi-empirical model is

defined based on insights gained by purely numerical device

simulations (with PISCES) and is verified by measurements.

The physical MMSPICE BJT model is benchmarked by demon-

strating important advantages of it, which include model

scalability and ease of parameter tuning, and by qualifying

its disadvantages, which include inaccuracy in hard satu-

ration and increases in run-time. It seems that the advan-

tages of the MMSPICE BJT model outweigh the disadvantages

and hence it is possibly a viable alternative to the ubiq-

uitous SPICE Gummel-Poon model. A methodology for statis-

tical (Monte Carlo) simulation and sensitivity analysis is

developed by exploiting unique advantages of MMSPICE and

SUMM, its model parameter evaluator, applied to IC TCAD.

The novel methodology reliably and efficiently relates

device/circuit performance directly to measurable process

parameters since MMSPICE/SUMM implicitly accounts for

physical correlations among device model parameters. The

computational efficiency permits use of a simple Monte

Carlo technique involving random generation of process

parameters for the statistical simulation. The utility of

the TCAD methodology is demonstrated by predicting IC para-

metric yields and sensitivities of device/circuit perform-

ance to process parameters in an actual technology.














CHAPTER 1
INTRODUCTION


Recently BiCMOS or merged bipolar-CMOS technology has

been widely promoted for high-speed digital and mixed dig-

ital-analog VLSI integrated circuits (ICs) such as gate

arrays, static and dynamic RAMs, and microprocessors. The

bipolar ECL technology offers highest speed available in

today's silicon technology, but its use is limited to low

packing-density ICs due to high power consumption. On the

contrary, the CMOS technology consumes negligible stand-by

power, making it suitable for VLSI applications requiring

high packing density. However, its speed is restricted by

the low driving capability of MOSFETs. The conventional

BiCMOS gate, which is a clever combination of bipolar

(BJTs) and MOS (MOSFETs) transistors, provides high driv-

ing capability by the use of BJTs as active charging/dis-

charging devices and low-power consumption by the use of

MOSFETs as switching devices. As a result, BiCMOS technol-

ogy has gained widespread use in today's high-speed and

high packing-density applications. The high packing-den-

sity requirement, as demanded by the growing number of

devices to be integrated in an IC, dictates scaling of the

lateral and vertical dimensions of semiconductor devices.

Such structural scaling necessitates supply voltage scal-









ing to mitigate high electric-field effects, such as hot-

carrier-induced device degradation, which tend to degrade

circuit reliability as well as performance.

As the supply voltage is scaled from 5 V down to 3.3

V and below, the speed advantage of BiCMOS over CMOS for

VLSI digital applications appears tenuous for submicron

technologies [Mom87]. The conventional BiCMOS gate propa-

gation delay increases inordinately as the voltage is

reduced because of logic level offsets that decrease the

effective bias on the MOSFET gates and hence the channel

currents which drive the BJTs. The offsets which appear in

the transient logic levels (for cascaded gates) are defined

by the bipolar transistor charge dynamics coupled to the

load impedance. Their debilitating effects can possibly be

limited by optimal design and scaling of the technology and

the circuit. Such design optimization requires reliable

device/circuit simulation tools, such as MMSPICE [Jeo90],

to assess the tradeoffs involved.

MMSPICE simulation of the conventional BiCMOS gate for

the technology optimization revealed that the npn BJTs are

commonly driven into saturation or quasi-saturation modes

during transient operation of the gate. In Fig. 1.1, a two-

dimensional structural diagram of an advanced npnp BJT,

including the parasitic substrate pnp transistor, is

shown. The saturated or quasi-saturated npn BJT may acti-

vate the parasitic substrate pnp transistor, which may

cause excessive substrate current. The excessive substrate

current flowing during the transient response of a BiCMOS















Base


Collector


Fig. 1.1 Two-dimensional structural diagram of an
advanced npnp BJT, including the parasitic
pnp transistor created by the p-type
substrate.


Emitter








gate can cause substrate bias instability or latch-up, and

is a significant problem in integrated-circuit design

[Kaw89]. Since the substrate pnp transistor tends to be

activated by the npn BJT in a conventional BiCMOS gate, the

development of a physical substrate pnp model with linkage

to the npn model is crucial to assess a BiCMOS design in

terms of reliable circuit operation.

Since fabrication of semiconductor devices for exam-

ining technology optimization and scaling is costly and

time-consuming as technologies are scaled down to the deep-

submicron regime, reliable and efficient technology CAD

(TCAD) tools are necessary. An efficient TCAD system

requires integrated, physical tools for predictive pro-

cess, device, and circuit simulations. A conventional TCAD

system comprises purely numerical process and device sim-

ulators, and a circuit simulator with analytical device

models, e.g., the Gummel-Poon model, which are empirical

and erroneous in accounting for specific physical phenom-

ena and can miss physical correlations among parameters.

Although the numerical process/device simulators are

robust and predictive, the conventional TCAD system is not

well suited for manufacturing CAD involving statistical

simulation and sensitivity analysis due to the CPU-inten-

siveness of the numerical simulators in addition to the use

of empirical device models. A numerical mixed-mode device/

circuit simulator may circumvent the problem of the empir-

ical device models, but is very computationally ineffi-

cient and usually introduces severe convergence problems.








A new IC TCAD system, which consists of an existing

numerical process simulator and a semi-numerical mixed-

mode device/circuit simulator (MMSPICE/SUMM) linked to

process simulator, has been developed [Jeo90], [Gre92].
The semi-numerical BJT model in MMSPICE is physical and

predictive and has physical parameters that relate

directly to the device structure shown in Fig. 1.1. The

linking software SUMM extracts physically correlated

device model parameters from the one-dimensional intrinsic

doping profile obtained from process simulation. The new

TCAD system is advantageous compared to the conventional

one involving the Gummel-Poon model in that it can account

for physical correlation among device model parameters,

can directly relate device/circuit performance to doping

profiles, and can accurately predict device/circuit per-

formance in high-current regions of operation. In addition

to these advantages, the computational efficiency makes

the new semi-numerical TCAD approach amenable to IC manu-

facturing CAD involving statistical simulation and sensi-

tivity analysis.

Subsequent to the initial development [Jeo90], sig-

nificant expansions and refinements [Hon91], [Jin92] of

the MMSPICE (charge-based) BJT model (QBBJT) have been

done. Thus to assess the utility of the MMSPICE/SUMM sys-

tem, the model needed to be benchmarked with respect to the

SPICE/GP model, which has been the workhorse for BJT sim-

ulation for past two decades. The benchmarking must demon-









state important advantages and significant disadvantages

of MMSPICE/QBBJT relative to SPICE/GP.

Statistical and sensitivity analyses of scaled ICs

have become essential in the cost-effective manufacture of

them. Technology design for performance, reliability, and

yield must be done with minimum number of experiments in

short development time for cost effectiveness and compet-

itiveness. The new TCAD approach involving MMSPICE/SUMM

offers computationally efficient statistical simulation

and sensitivity analysis, retaining good accounting of

physical correlations among device model parameters and

properly relating device/circuit performance to process-

ing.

This dissertation addresses these issues; it expands,

demonstrates, and assesses the utility of the approach to

TCAD comprising MMSPICE/SUMM for BiCMOS ICs. The major con-

tributions made in this work are described as follows:

(1) optimization of BiCMOS design for supply voltage scal-

ing, based on insights gained by extensive use of the

mixed-mode device/circuit simulator MMSPICE;

(2) development of a simple yet accurate parasitic pnp

model needed for complete design optimization of BiCMOS

gates based on MMSPICE;

(3) MMSPICE/QBBJT benchmarking for demonstration of its

utility as a viable alternative to SPICE/GP;

(4) development of a new methodology for statistical

(Monte-Carlo) simulation and sensitivity analysis








using MMSPICE/SUMM, which also shows utility of the new

semi-numerical TCAD approach.

In Chapter 2, the optimization of the conventional

BiCMOS gate design for supply voltage scaling is analyzed

using MMSPICE. The analysis is focused on the inordinate speed

degradation of the BiCMOS driver circuit at low supply volt-

ages caused by reduction in pull-down MOSFET drive current due

to logic-level (VBE) offsets. Device/circuit simulations give

physical insight concerning the design optimization, and sug-

gest how the polysilicon emitter formation process as well as

gate layout parameters be varied to retain the BiCMOS speed

superiority over CMOS when the technology is scaled. Optimal

design for gate layout and polysilicon emitter process vari-

ations is derived and shown to be superior to the counterpart

CMOS gate at low supply voltage (3.3 V) in regard to propaga-

tion delay.

In Chapter 3, a simple yet accurate model for the par-

asitic substrate pnp BJT, which can easily be activated by

the (quasi-) saturation of an npn transistor and hence can

be problematic for reliable BiCMOS gate operation, is

developed. A physical model for the hole transport cannot

be based on the MMSPICE/QBBJT collector analysis of the

quasi-saturated npn transistor. Due to this problem, the

simple model is derived semi-empirically based on insights

gained by PISCES simulations. The model is verified by mea-

surements, and its usefulness for BiCMOS design optimiza-

tion is also demonstrated by predicting the transient

substrate current of a BiCMOS gate.








In Chapter 4, the MMSPICE/QBBJT model is benchmarked

by demonstrating its important advantages and significant

disadvantages relative to SPICE/GP. The MMSPICE/QBBJT

advantages, which include model scalability and ease of

parameter tuning compared to the intensive parameter opti-

mization needed for SPICE/GP model, are presented. The dis-

advantages, which include convergence problem for circuits

with large number of BJTs, inaccuracy in hard saturation,

and increases in run-time and memory-usage, are discussed.

It seems that the advantages of MMSPICE outweigh the dis-

,advantages and MMSPICE/QBBBJT is possibly a viable alter-

native to SPICE/GP.

In Chapter 5, a methodology for statistical (Monte-

Carlo) simulation and sensitivity analysis is developed by

exploiting unique advantages of the new TCAD approach con-

sisting of MMSPICE and SUMM. The methodology directly

relates the device/circuit performances to measurable pro-

cess parameters by using MMSPICE/SUMM and a unique way of

characterizing the needed one-dimensional doping profile

for a randomly given set of independent process parameters.

The methodology accounts for physical correlations among

model parameters by using SUMM. Since the methodology is

computationally efficient, unlike other approaches that

use pure numerical process and device simulators, a simple

Monte-Carlo analysis involving random generation of pro-

cess parameters can be used for statistical simulation. The

usefulness of our methodology is demonstrated by predict-

ing parametric yields and sensitivities of device/circuit






9


performance figures of merit to process parameters in an

actual IC technology.

In Chapter 6, the main accomplishments of this dis-

sertation are summarized, and future research areas are

suggested.














CHAPTER 2
BICMOS DESIGN OPTIMIZATION FOR SUPPLY VOLTAGE SCALING


2.1 Introduction


The speed advantage of BiCMOS over CMOS for VLSI dig-

ital applications appears tenuous for submicron technolo-

gies in which the supply voltage must be scaled from 5 V

down to 3.3 V and below [Mom87]. The conventional BiCMOS

gate propagation delay increases inordinately as the volt-

age is reduced because of base-emitter junction voltage

offsets that decrease the effective bias on the MOSFET

gates and hence the channel currents which drive the bipo-

lar transistors (BJTs). The offsets which appear in the

transient logic levels (for cascaded gates) are defined by

the bipolar transistor charge dynamics coupled to the load

impedance. Their debilitating effects can possibly be lim-

ited by optimal design and scaling of the technology and

the circuit. Such design optimization requires reliable

device/circuit simulation tools to assess the tradeoffs

involved.

Modifications, e.g., those in [Nis89], in the basic

BiCMOS driver circuit have been proposed to resolve the

voltage-scaling problem, some requiring a complementary

BiCMOS technology [Shi89], [Emb91]. Also, simple modifica-








tions in the transistor layouts [Raj90], or scaling rules

[Ros89a], [Bel90], based on device analyses, have been sug-

gested to alleviate the problem. However, due to the strong

link between BiCMOS technology and circuit design, and to

the implied problems in predictive simulation, no truly

comprehensive study of optimal design for scaled BiCMOS has

been done.

This Chapter addresses the voltage-scaling problem in

BiCMOS design using MMSPICE [Jeo90], an enhanced version

of SPICE2 containing our physical charge-based BJT model

[Jeo89] written into the source code. The model is semi-

numerical, requiring Newton-like iterative solutions of

the nonlinear model equations for each Newton-Raphson

iteration of the circuit nodal analysis. From the solution,

Ic, IBB QBE, and QBC, which include all components of cur-
rents and regional charges in the BJT, are characterized

for the specified VBE and VBc. The transconductances and

(nonreciprocal) transcapacitances needed in the nodal

analysis are evaluated using difference approximations

based on successive calls of the model routine. Since the

key model parameters are technological (i.e., they follow

directly from the device structure), MMSPICE is an appli-

cation-specific semi-numerical (multi-level Newton) mixed-

mode device/circuit simulator as well as a physical

replacement for SPICE/Gummel-Poon [Get78]. It can be quite

useful in BiCMOS TCAD, as we demonstrate herein.

In Section 2.2, the switching operation of the con-

ventional BiCMOS gate is reviewed briefly, and MMSPICE sim-









ulations revealing the dependence of propagation delay on

(npn) BJT physical/structural parameters are discussed.
This discussion demonstrates the utility of MMSPICE, and

provides physical insight into the voltage-scaling prob-

lem. In Section 2.3, this problem in general applications

is characterized, and a first-order design objective to

ameliorate the problem is defined. In Section 2.4,

approaches to this design objective are assessed by using

MMSPICE to predict the dependence of the transient logic

levels, including the VBE offsets, on the BiCMOS gate

structural and layout parameters. A first-order optimal

design, requiring only minor modifications in the nominal

gate structure and layout, is derived from the simulations

and insight attained. The suggested design effectively

increases the pull-down drive current, partly by minimiz-

ing the pull-up transient offset, to improve the worst-case

pull-down speed deterioration at low supply voltages. Cas-

caded-gate simulations are then done to show that the speed

advantage (shorter propagation delay) of BiCMOS over CMOS

at 3.3 V, and even at lower supply voltages, can be main-

tained without major changes in technology or circuit

design. The potential problematic transient substrate

(pnp) current is recognized as a tradeoff, and designs to

minimize it are stressed. In Section 2.5, possible improve-

ment of the first-order design afforded by optimization of

the polysilicon emitter-formation process, which involves

using interfacial oxide between the polysilicon and sili-

con emitter to satisfy the requirements of the first-order








design objective, is examined with some simulation

results.

For scaled technologies requiring supply voltages

well below 2.5 V, modified driver circuit configurations

designed for full-swing logic levels will be necessary. In

Section 2.6, the possible utility of the BiNMOS gate

[Wat89], which uses an n-channel MOSFET as the active dis-

charging device for pull-down, is assessed via MMSPICE sim-

ulations for these deep-submicron technologies.


2.2 Conventional BiCMOS Gate Operation


Fig. 2.1 shows the conventional BiCMOS driver circuit.

Explanation of its general operation is given in [San86]

and [Ros89b], but an adequate discussion of how the tran-

sient logic levels obtain, which is critical in the supply

voltage (VDD)-scaling problem, has not been given. Illus-

trative plots of node voltages in a cascaded circuit with

a capacitive load (CL) during the pull-up transient are

shown in Fig. 2.2. In this transient, the input to an

intermediate stage drops from high to low, pulling the out-

put up from Voo to (VDD-Vol). The voltage offsets Voo and

V01 are fractions of a nominal VBE drop, defined by the cou-

pled charge dynamics of the BJTs and the load in the pull-

down and pull-up transients respectively. In the pull-up

transient, the p-channel MOSFET M1 initially drives the BJT

Z1, which in turn charges CL; Z2 is virtually off. As the

output rises, the base node voltage (VB1) of Z1 reaches VDD,
















VDD


Fig. 2.1 Conventional BiCMOS driver
circuit.


VIN









6 --1




5




4


0 ...... Vout

S1 VB1
ccc
o

- 2-
a)




z



1








12 13 14 15 16
Time (ns)


Fig. 2.2 Illustrative plots of node voltages in a
cascaded BiCMOS circuit with a
capacitive load (CL) during the pull-up
transient; VDD = 5 V.








which is higher than the output because of the base-emitter

forward bias VBE1 on Z1, and M1 loses its drive (VDs = 0).

At this point, the base current of Z1 is negligible, yet

Zl continues to charge CL. The charge dynamics at this

point are crucial in setting Vol. For example, if CL is rel-

atively small, then the output will rise quickly relative

to the discharging of Z1, forcing VB1 significantly above

VDD as indicated in Fig. 2.2. This saturates Z1, but the
negative base current pulled by M1 in reverse mode facil-

itates the discharging of Z1, and the ultimate offset,

Vol=VBE1, tends to be small. However, if CL is relatively
large, then the output will not rise much as Z1 discharges,

and hence the base node drops below VDD again. The positive

base drive from M1 is returned, tending to keep Z1 charged,

and Vol large. The VBE1 offset, and the VBE2 (= Vo0) offset

for the pull-down transient, define the transient logic

levels, which in turn govern the MOSFET gate drives and

hence the propagation delay for cascaded stages in a BiCMOS

circuit.

The regions of device operation that obtain during the

transient switching of the circuit affect the delay

[Ros89b], and the VBE offsets significantly. For example,

when a bipolar transistor operates in quasi-saturation

[Jeo87], the added stored charge (in the collector region)

tends to reduce the current gain and speed of the device,

and hence increases the delay of the circuit. Thus BJT

structural designs to avoid quasi-saturation can enhance









circuit speed. Such designs can be assessed directly with

MMSPICE.

To exemplify the utility of MMSPICE, we show in Fig.

2.3 the predicted pull-up propagation delay, tdu, versus CL

for different epitaxial-collector doping densities, NEPI,

in a nominal advanced-technology (polysilicon-self-

aligned) n pnn+ BJT, with VDD = 5 V. NEPI is a parameter in

our BJT model [Jeo89]. For advanced BiCMOS, the same epi

is used for the BJT collector and for the PMOS n-well body.

Thus changes in NEPI will affect the p-channel MOSFET as

well as the BJT. In these simulations, we assumed that the

MOSFET threshold voltage was fixed, and concentrated on the

dependence of tdu on the BJT structure. Note in Fig. 2.3

that tdu tends to decrease with increasing NEPI. This is due

predominantly to the suppression of quasi-saturation

[Jeo87] in the BJT, a high-current mode of operation which

onsets when Ic is near

Io = qANEPIVsat (2.1)

where A is the BJT area and vsat is the electron saturated

drift velocity. Increasing NEPI can thus push o1 to higher

currents which are not reached during the switching tran-

sient due to limited MOSFET drive. Note, however, that the

speed enhancement would have to be traded-off with the con-

comitant reduction in breakdown voltage, which could also

be analyzed with MMSPICE [Jeo88].

In our BJT model [Jeo89], the saturation current den-

sity JEO for minority holes injected into the emitter and










5.0





4.0





3.0
o
CO


2.0





1.0





0.0
0.0


(Azl=4gm2, WM1=5gm, WEPI=0.37gm)


2.0 4.0 6.0 8.0
CL (pF)


Fig. 2.3 MMSPICE-predicted pull-up propagation
delay, tdu, versus CL for different
epitaxial-collector doping densities,
NEpI, in a nominal advanced-technology
n pnn+ BJT, with VDD = 5 V.


10.0








the related stored excess-charge control time TE' both of

which depend on the effective surface recombination veloc-

ity Sp(eff) as well as on the doping density profile, are

modeled based on a physical analysis of the hole transport

in the highly doped polysilicon/silicon emitter region.

Therefore by varying these parameters we can simulate with

MMSPICE effects of changing the polysilicon-emitter pro-

cess on the BiCMOS circuit. We plot in Fig. 2.4 simulated

pull-up propagation delay, tdu, versus TE for two different

values of JEO at VDD=3.3 V. Note that tdu tends to decrease

with decreasing TE and JEO, reflecting, respectively,

enhanced speed and current gain of Z1. For design optimi-

zation however, the physical correlation between JEO and tE

will have to be accounted for.


2.3 Voltage Scaling


Because of the VBE offsets, the BiCMOS gate delay

tends to increase abruptly as VDD is lowered toward 3 V,

which jeopardizes the BiCMOS superiority over CMOS for

scaled technologies [Mom87]. There are transient logic-

level offsets associated with both the high and low levels

for the conventional BiCMOS gate in Fig. 2.1. They are, as

implied in Section 2.2, different from dc offsets which are

defined by device leakage currents [San86]. The logic-

level offsets for pull-up and pull-down transients can be

expressed as









(Az1=12gm2, WM1=16pm, NEpI=2x1016 cm-3)


---O JEO=1.6x10-8 A/m2
c-- JEO=0.8x10-8 A/m2


5.0 10.0
TE(xl0~10 sec)


Fig. 2.4


MMSPICE-simulated tdu versus TE for two
different values of JEO, with VDD = 3.3 V
and CL = 6 pF.


3.0




2.5




2.0




c1.5




1.0




0.5


0.0L


3


15.0


1111)1(11))1)(









Vol VDD-Vout() (2.2)

and

Vo0 Vout0) (2.3)

where Vout(1) and Vout(0) are the high and low transient out-

put logic levels defined by the device/circuit charge

dynamics. The offsets limit gate-source voltage drive on a

cascaded stage, which defines the BJT base drive currents

and hence the speed. The effective gate-source drive pro-

vided in a cascaded circuit is (see Fig. 2.1)


-VGS1 = VDD-Voo (for pull-up) (2.4)

or


VGS2 = VDD-Vol-VBE2 (for pull-down) (2.5)

where VGS1 is the drive on Ml, limited by the pull-down off-

set Voo of the previous stage, and VGS2 is the drive on M2,

limited by the pull-up offset Vol of the previous stage and

by the needed forward bias VBE2 on Z2 during the pull-down

transient. As VDD is scaled, the effective gate drives in

(2.4) and (2.5) will approach zero faster than VDD since

Vo0, Vol, and VBE2 are virtually fixed and do not scale.

This in fact is the cause of the aforementioned abrupt

increase in the gate delay. At extremely low VDD (< Vol +

VBE2 + VT2, where VT2 is the threshold voltage of M2), the
BiCMOS gate will not function at all because of insuffi-

cient gate drive for the pull-down transient.









MMSPICE-simulated pull-up and pull-down propagation

delays versus VDD are plotted in Fig. 2.5 for a cascaded

circuit from a nominal BiCMOS technology. Note the signif-

icant deterioration in speed as VDD is lowered toward 3 V,

especially for the pull-down transient. The termination of

the curves near 2.7 V indicates the cessation of the pull-

down operation. These results illustrate the implication

of (2.4) and (2.5) that the VDD-scaling effect is most

severe on the pull-down transient. So the objective in our

design optimization is to increase the pull-down drive cur-

rent, partly by minimizing V1o in (2.5), which is the volt-

age offset defined by the pull-up transient as given in

(2.2). This optimization will also include consideration

of increasing the M2 width and/or the Z2 area, and decreas-

ing VT2. Such first-order optimization can possibly be

improved by designing the polysilicon emitter to lower Sp(eff),

which tends to decrease JEO and increase TE [Gre92]. Both of

these (correlated) parametric changes are favorable with

regard to reducing Vol and increasing the pull-down drive cur-

rent. Simulations done with MMSPICE reveal that Vol is

indeed influenced by these device and layout parameters.

These make the idea of a first-order design optimization

feasible, and in fact doable as outlined in the next sec-

tion.










30.0




25.0




20.0



(D
,15.0
"0



10.0




5.0




0.0 2
2.0


(Azl=4pm2, WMI=5gm, NEPI=2x1016cm3)


3.5
VDD (V)


Fig. 2.5


MMSPICE-simulated pull-up and pull-down
propagation delays versus VDD for a
cascaded circuit from a nominal BiCMOS
technology; CL = 6 pF.


5.0









2.4 Design for "Near-Full-Swina" Operation at Scaled VDD


The objective here is a first-order design optimiza-

tion to ensure conventional BiCMOS speed superiority over

CMOS at VDD = 3.3 V, the scaled supply voltage for the next

generation of VLSI CMOS, and perhaps even for lower VDD.

Circuit (and technology) modifications to effect full-

swing operation have been suggested [Shi89], [Emb91], but

with sacrifice of area and undue BJT saturation, which

drives the parasitic substrate pnp transistor and may cause

bias instability or latch-up in the BiCMOS integrated cir-

cuit. Alternatively we explore here the possibility of

achieving near-full-swing operation, without modifying the

circuits, but by increasing the pull-down drive current and

minimizing Vol (2.5) via optimization of gate layout param-

eters and polysilicon/silicon emitter structure, which

will be explained in detail in the next section. With

MMSPICE we can examine directly the dependence of Vol on

the BiCMOS technology, and can suggest a gate structure to

minimize the offset and increase the pull-down drive cur-

rent such that the pull-down delay does not limit perform-

ance.

To facilitate a systematic design optimization, how-

ever, we need some qualitative insight. As discussed in

Section 2.2, Vol is controlled by the charge dynamics near

the end of the pull-up transient. Here the rate of change

of VBE1 relative to that of Vout determines the ultimate
offset. If








dVBEI dVout
i< --- (2 .6)
dt dt

when VB1 = VDD, i.e., when M1 is not driving Z1 and VBC1 =

0, then a significant transient VB1 > VDD overshoot (see

Fig. 2.2) tends to occur, and the subsequent discharging

of Z1 is facilitated by negative base current, resulting

in small VBE1 = Vol in (2.2). We thus want to design the

gate to force (2.6), which we can express phenomenologi-

cally as

kT dQzi 1 dQcL 1i1 1 Qz
( )- (2.7)
qQz dt CL dt CL CL t (2

where Qzi represents the electron charge stored in Z1 and

It is an effective (non-constant) transit time for Z1. The
insight afforded by (2.7) is useful. It implies that a slow

BJT (small dQzi/dt) with large current (Ici = Qzi/ct) at

VB, = VDD tends to minimize Vol. Note the dependence on CL

in (2.7). In fact for low CL, the inequality is generally

valid, and V1o is small for typical technological parame-

ters. Only for moderate and high CL is the validity of (2.7)

ever threatened so that design optimization is needed.

Also, the direct effects of parametric changes on the BJT

current drive (Icl) and on propagation delay (as exemplified

in Figs. 2.3 and 2.4), as well as their influence on Vol,

must be considered in the optimization.

We stress that the desired transient VB1 overshoot

forces Zl into a transient saturation condition. Thus

excessive base-node voltage overshoots at the end of both

the pull-up and pull-down transients may significantly

activate the parasitic substrate pnp transistors of the BJT









structures [Kaw89]. The substrate pnp can inject excessive
currents into the substrate, which can cause bias insta-

bility in an integrated circuit and may trigger latch-up.

Therefore any viable design criteria for scaled VDD should

avoid excessive BJT saturation. This constraint on the

design optimization was overlooked in previous studies

[Emb91], [Raj90].

As VDD is lowered, Ici of Z1 for the pull-up transient

is diminished due to the reduced gate drive for M1 in

(2.4). This in turn means less quasi-saturation of Z1,

i.e., a faster device. These conditions are not compatible

with the criteria for V1o minimization; they threaten the

validity of (2.7). Therefore, we should increase the width

WM1 of Ml, relative to its acceptable value at VDD = 5 V,

to increase the Zl base drive and hence Icl. The increased

Icl can force the BJT into quasi-saturation, which tends to
make dQzl/dt smaller and hence ensure the validity of

(2.7). However, a design tradeoff is implied because the

quasi-saturation can directly lengthen the gate delay.

This tradeoff can perhaps be effected via changes in the

structural parameters of Zl, including the area AZ1 as

indicated by (2.1). However, we cannot clearly see how

effective such parametric changes are until we simulate the

actual circuits, varying additionally WM2 and AZ2 to fur-

ther increase the pull-down drive current. Note though that

if WMI is increased, Icl over the entire active charging

period will be larger, and this will directly reduce the

delay, independent of the afforded benefit of minimizing









Vol. Thus an extensive set of simulations with varying

parameters will have to be done to truly optimize the

speed-area tradeoff.

The insight derived can facilitate a systematic design

optimization based on simulations by using MMSPICE inte-

grated with SUMM [Gre92] for technology CAD. The program SUMM

evaluates the correlated MMSPICE BJT model parameters. The

BJT model parameters used represent a typical advanced device

with structure corresponding to the double-polysilicon self-

alignment technology. For the simulations, the SPICE Level-

2 MOSFET model was used. The model parameters were

extracted from a nominal submicron BiCMOS technology:

threshold voltages of 0.80 V and -1.12 V were used for the

n- and p-channel transistors respectively; channel lengths

of 1 jm were assumed. In Fig. 2.6, we plot the offset Vol

versus AZ1 (= Az2) derived from pull-up simulations of a

two-stage circuit using the basic gate in Fig. 2.1 with WM1

(= 2WM2) as a varying parameter. The supply VDD was 3.3 V

and the load CL was 6 pF. Consistent with our insight, the

simulation results show that Vol is reduced substantively

by increasing WM1. For example, with AZ1 = 12 um2, increas-

ing WMI from 4 um to 16 um decreases Vol by about 100 mV.

Note also the predicted dependence on AZ1. If AZ1 is too

small, the sensitivity to WM1 is diminished, and Vol is rel-

atively large. In this case, Z1 is driven into quasi-sat-

uration, and the degraded current gain (viz., increased Tt)

limits Icl, tending to invalidate (2.7) as well as directly

lengthening the gate delay.









(NEPI=21 016cm-3, WEPI=0.371m)


0.9




0.8




0.7




0.6




0.5


5.0


10.0


15.0 20.0 25.0 30.0
AZi (lm2)


Fig. 2.6 Pull-up offset Vol versus AZ1 (= AZ2)
derived from simulations of a two-stage
circuit using the basic gate in Fig. 2.1
with WMI (= 2WM2) as a varying parameter;
VDD = 3.3 V and CL = 6 pF.


* I I i I I -

e-e WMi=44m
o--e WM=8gm
e---- WM=12pm
-A WM1=16pm
v-vWM1=16gm, JEO=8x109 A/m2 -





"-"-


0.40
0.4


D


"""'""









Quasi-saturation effects are influenced by, via

(2.1), NEPI and by the BJT epi-collector width WEPI [Jeo87].

Therefore, the relatively large circuit area requirement

implied by Fig. 2.6 could possibly be relaxed by increasing

NEPI to prevent quasi-saturation, or by decreasing WEPI to
minimize its effects. However MMSPICE simulations show

that Vol is not sensitive to NEPI and that it actually

increases with decreasing WEPI. These results reflect the

complexity of the device physics obscured by (2.7), and the

fact that quasi-saturation can in some cases be beneficial

and in others detrimental to the overall BiCMOS gate per-

formance. Indeed the delay is directly dependent on NEPI

(see Fig. 2.3) and WEPI, and hence a comprehensive design

optimization for minimum delay at scaled VDD could involve

some change in these parameters, as well as in JEO and TE

as we discuss in Section 2.5. We include in Fig. 2.6 pre-

dicted Vol for JEO reduced by a factor of two from its nom-

inal value, which could possibly be achieved by perturbing

slightly the polysilicon emitter-formation process. Note

that Vol is reduced dramatically. This improvement is due

to the increased current gain of Z1 and the concomitant

higher Icl in (2.7). Note however that the predicted Vol

versus JEO variation in Fig. 2.6 does not account for the

correlated variation of TE and its effect on Vol.

As mentioned previously, we must be concerned with the

VBI overshoot and the degree of saturation of Z1 associated

with the reduction of Vol. We plot in Fig. 2.7 the maximum

transient VBc1 versus VDD for different WM1 obtained from










(Az1=12pm2, NEP=2X1016cm-3, WEPI=0.371m)


e---- WM=16m, CL=2pF
---WMI=8gm, CL=2pF
e--- WMl=16gm, CL=6pF
A---WMl=8pm, CL=6pF


I... I


2.5 3.0 3.5 4.0
VDD (V)


I . I .. -


4.5 5.0 5.5 6.0


Fig. 2.7 Maximum transient VBC1 versus VDD for
different WM1 obtained from the MMSPICE
simulations.


1.0





0.8


.0.6

X
E
V-"

>0.4





0.2


0.02
2.'


0


1. . .. .. . . . . . . . . . I ' .


I . . I . . I . . I


I . . I








the MMSPICE simulations. The near-optimal BJT area (AZ1 =

12 pm) suggested in Fig. 2.6 was used. Note that the max-

imum VBCI tends to increase with increasing WMi, but that
scaling VDD inherently decreases it. This indicates that

Icl in (2.7), which increases with increasing WM1 and
decreases with decreasing VDD, is the controlling factor in

establishing the validity of (2.7). For our design objec-

tive at VDD = 3.3 V, the VB1 overshoot is thus low enough

to avoid the substrate current problem while high enough

to effectively reduce Vol. However at lower VDD, the trade-

off cannot be effected. The small VB1 overshoot tends to

allow Vol to be large, preventing the achievement of near-

full-swing operation by varying structural parameters

only. Hence modification of the conventional circuit will

be needed for full-swing operation at very low VDD (scaled

for deep-submicron technologies) to maintain the speed

superiority of BiCMOS over CMOS.

Based on the MMSPICE simulations discussed previ-

ously, a first-order optimal gate structure for increasing

M2 drive current by minimizing Vol and hence ameliorating

the VDD-scaling problem can be suggested. The optimization
requires only minor modifications in the BJT design, which

would be compatible with a nominal advanced BiCMOS tech-

nology. To enhance Icl at the end of the pull-up transient,

and thereby minimize the Vol offset in (2.5) at low VDD, we

use a fairly large MOSFET: WM1 = 16um; and large BJT: AZl
= 12 um2. We use a nominal (relatively small) epi-collector

doping density: NEPI = 2x016 cm-3; with relatively thick









epi to exploit some advantage of quasi-saturation in slow-

ing the device: WEPI = 0.4 Jim. Indeed, this structure

approximates a typical advanced-technology bipolar tran-

sistor [Zde87].

The choices for NEPI and WEPI are based on additional

MMSPICE simulations which show that larger NEPI (as sug-

gested by Fig. 2.3) and/or smaller WEPI tend to push the

abrupt increase in the BiCMOS delay to higher VDD. These

predicted tendencies are evidence that some quasi-satura-

tion can be beneficial by slowing the BJT such that ade-

quate VB1 overshoot obtains and minimizes Vol.

The performance comparison of BiCMOS and CMOS gates

should be done under the conditions of equal gate areas and

equal input capacitances [Raj92]. Hence, we compare the delay

of the BiCMOS driver circuit in Fig. 2.1 with that of a CMOS

inverter-cascade circuit, in which the total MOS gate area of

the first inverter is adjusted to equal that of the MOSFETs

(Ml, M2, and M3) connected to Vin in the BiCMOS circuit, while

the second inverter gate area is adjusted to keep the total

circuit areas the same [San86]. To correctly account for the

speed deterioration caused by the voltage offsets, a two-stage

BiCMOS driver and the counterpart two-stage CMOS inverter-

cascade were simulated, with load capacitances (CL) added to

the output of each stage.

We show in Fig. 2.8 the MMSPICE-predicted speed of

BiCMOS and CMOS circuits using the optimized BJT and MOSFET

structures. A large load CL (= 6 pF in Fig. 2.8(a)) was

used, for which the supply voltage-scaling problem is










25.0





20.0





15.0

c,


10.0





5.0





0.0
2.0


Fig. 2.8


(CL=6pF, NEPI=2x016cm-3, WEPl=0.37gm)


2.5 3.0 3.5 4.0 4.5
VDD (V)


5.0


Simulated average propagation delay tD of
a BiCMOS cascade circuit using the
optimized BJT and MOSFET structures for (a)
CL = 6 pF and (b) CL = 2 pF. For comparison,
the delay of counterpart CMOS inverter
cascade and that of BiCMOS gate with
smaller AZ1 and WM1 are shown also.









severe [Mom87]. For comparison, the simulated speed for

small CL (= 2 pF in Fig. 2.8(b)) is shown as well. The prop-

agation delay tD, plotted versus VDD, is the average of the
pull-down and pull-up delays of the second stage in the

simulated cascaded circuit. Note that the critical volt-

age, Vcrit, for VDD, below which the BiCMOS tD is longer

than that of the CMOS, has been reduced to well under 3 V.

Also, note that Vcrit for the small CL (= 2 pF) is lower

than that for the large CL because the inequality (2.7)

defaults for low CL. To emphasize the dependence of Vcrit

on the BJT area and the MOSFET width, we include in Fig.

2.8 the same BiCMOS/CMOS comparison for smaller AZ1 and WM1

and corresponding gate area. In this case Vcrit is signif-

icantly higher.

Additional increase of the M2 drive current can be

effected by decreasing the threshold voltage. Such rede-

sign is indeed called for since M2, with its body tied to

ground, shows an increased threshold voltage due to the

body effect caused by the transient VBE2 of Z2. Hence,

designing M2 for lower VT2 can significantly increase the

transient pull-down drive current in line with our design

objective. To see the effect of a reduced VT on the circuit

speed, we include in Fig. 2.8(a) predicted tD-versus-VDD

plots of the BiCMOS and corresponding CMOS gates having

lower threshold voltages: VT2 = 0.4 V and VT1 = -0.7 V. Note

that Vcrit is lowered significantly more (to about 2.4 V),

mainly because of the 0.4 V reduction in VT2 although the











20.0
C
E
C
E


15.0







- 10.0 -
a






5.0 r







0.01
2.0


(CL=2pF, NEPl=2x1016cm3, WEPl=0.37gm)
* ' I ' i ' ' I ' i ' I ' '

--0 CMOS, Equi BiCMOS AZ1=4Jm2, WMi=51m
--- CMOS, Equi BiCMOS Azi=12(m2, WM1=16gm
>---- BiCMOS, Azi=4pm2, WM1=51m
.----a BiCMOS, Azi=12gm2, WM1=161m


0


" -----------------
E .... ----
"'El- .-........ ^.. ............................


2.5


3.0


3.5
VDD (V)


4.0


4.5


Fig. 2.8 --Continued


5.0









corresponding reduction in VT1 improved the pull-up delay

somewhat.

The simulations of Fig. 2.8 were done with WIM = 2WM2

and AZ1 = AZ2. Thus increasing WM1 to reduce Vol implies

additional pull-down drive current because of the corre-

sponding increase of WM2. To separate out the speed bene-

fits afforded by reducing Vol and by increasing WM2, we show

in Fig. 2.9 simulated pull-down delays versus VDD for four

variations on the gate design involving different values

of WMI, WM2, AZ1, and AZ2. We see that the optimal design
follows when both mentioned speed benefits are derived,

while using the larger AZ2 to limit quasi-saturation in Z2.


2.5 Polysilicon Emitter Design for Voltage Scaling


The first-order optimal design shown in Fig. 2.8 can

further be improved by considering the optimization of

polysilicon emitter in order to satisfy the insights for

improving BiCMOS delay performance at low VDD, which

includes increasing the pull-down drive current and mini-

mizing Vol in (2.5). To demonstrate the unique advantage of

optimizing the polysilicon emitter, the optimization

starts with the nominal structure and layout dimension,

i.e., AE = 4 m2, WM1 = 5im (WM2 = 2.5im), NEPI = 2x1016
-3 dmnin o h
cm WEPI = 0.4pm, without using the dimensions for the

first-order optimal design in Fig. 2.8.

Varying the polysilicon emitter-formation process for

the BJTs will change Sp(eff), and JEO and TE [Gre92]. A direct









(NEpI=2xl016cm-3, WEPl=0.37pm, TE=2.6x10-10)


10.0




5.0




0.0
2.0


5.0


2.5 3.0 3.5 4.0 4.5
VDD (V)


Fig. 2.9 Simulated pull-down delay versus VDD for
four variations on the values of WM, WM,
AZ1, and AZ2; CL = 6 pF, JEO=1.6x10 A/m.


25.0




20.0




15.0








benefit of lowering Sp(eff) is increased current gain 0, which

means enhanced collector current for a constant base drive

current, and hence increased pull-down (as well as pull-up)
drive current. Additionally, lowering Sp(eff) can increase the

excess carrier charge stored in the emitter, which slows down

the BJT but helps minimize the logic level offsets as implied

by (2.7). These two tendencies promote our design objective

of increasing the BiCMOS speed at low supply voltage.

We expect that the best results will be attained when

Sp(eff) is lowered as much as possible. The surface recombina-
tion velocity can be reduced drastically by introducing a thin

layer of interfacial silicon dioxide on the silicon emitter

prior to the polysilicon deposition [Yun88]. However the

interfacial oxide layer causes higher emitter resistance RE,

which degrades BiCMOS performance. Polysilicon contacts with

the RCA-clean interfacial oxide layer have orders of magni-

tude-lower Sp(eff) than those without the interfacial layer,

with the emitter specific resistance increased by an order of

magnitude [Yun88]. Recent work [Ham92] however showed that

when an intentionally grown interfacial oxide is broken up

just enough to create numerous small perforations, the high

p (i.e., low Sp(eff)) can be achieved with only a negligible

increase in RE. Based on these insights, a viable polysilicon

emitter design for BiCMOS speed improvement at low VDD can be

suggested, and demonstrated relative to CMOS with MMSPICE as

follows.

First, we will examine the effect of reducing Sp(eff) down

to that of the polysilicon/silicon emitter with the interfa-









cial oxide in terms of BiCMOS speed improvement at low VDD.

The concomitant effect of increasing RE by an order of magni-

tude will also be analyzed. Anticipating that the benefit

gained by the reduction of Speff is largely offset by the

increase of RE, we will then gauge the design tradeoff involv-

ing increased BJT emitter areas to limit RE. Note that

increasing the emitter area of Z2, as well as that of Z1 to

limit Vol, gives additional speed improvement at low VDD

because of the increased pull-down current, which tends to

offset the degradation due to quasi-saturation of the BJT.

Finally, we will assess the perforated emitter structure

[Ham92] which, with regard to BiCMOS performance (but not nec-

essarily technology), seems optimal.

The correlated JEO and TE variation as functions of

Sp(eff) and the emitter doping-density profile were simulated
by using SUMM. Same MOSFET and BJT structures as those in the

previous section were used for polysilicon emitter design

optimization. The conventional polysilicon emitter does not

include an interfacial oxide, and Sp(eff) g10 cm/sec. The max-

imum BJT gain (Pmax) is about 90 for a typical emitter area

AE of 4 pm2 with emitter width of 1 pm. A projected minimum

value for Sp(eff) of 100 cm/sec for the polysilicon emitter

structure with a thin (~ 2 nm) interfacial oxide layer [Yun88]

was used.

We show in Fig. 2.10 the MMSPICE-predicted BiCMOS and

CMOS propagation delays versus VDD. A large load (CL = 6 pF)

same as for the first-order optimal design in the previous

section was used. Curve (A2) in Fig. 2.10 characterizes the










25.0





20.0





15.0





10.0
0



10.0





5.0





0.0


Fig. 2.10


Fig. 2.10


2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)


MMSPICE-Predicted BiCMOS and CMOS tD-
versus-VDD characteristics for designs with
polysilicon emitter optimization. Same
circuits as for Fig. 2.12 are used for the
simulations.








speed of the nominal, non-optimized BiCMOS gate, for which JEO
(= 7.25x10-9 A/m2 with equivalent Pmax = 90) and TE (= 2.12x10-
10 sec), correlated and extracted by SUMM, correspond to

Sp(eff) = 105 cm/sec. Also RE = 20 2, which correlates with AE
= 4 im2 with emitter specific resistance of about 70 2.- m2

Note that Vcrit for this case, defined by the counterpart CMOS
curve (A), is less than 3 V, but the slope of the BiCMOS

tD(VDD) -curve for VDD in the vicinity of 3 V is high, indicat-
ing a tolerance problem for design at 3.3 V. (The non-opti-

mized design in Fig. 2.10 is better than that in Fig. 2.8

because the BJT current gain in Fig. 2.8 is too low (- 50) due

to large JEO value obtained directly from SUMM. The BJT gain
in Fig. 2.10 was adjusted to the nominal 0 (- 90) of MOSAIC

III by tuning JEO-) The predicted Vcrit is in accord with mea-

sured values reported in the literature [Yam89], [Mos91],

given variations in BJT structural parameters and the NMOS

threshold voltage. The BiCMOS pull-down delay at low VDD is

very sensitive to this threshold voltage due to the decreased

effective M2 gate drive as given by (2.5).

Curve (Al) in Fig. 2.10 represents the predicted BiCMOS

speed performance when the polysilicon-emitter structure
includes the interfacial oxide: Sp(eff) = 100 cm/sec but RE is

inherently large. Note that this value of Sp(eff) is about

three orders of magnitude lower than that for a nominal poly-

silicon emitter (105 cm/sec) without the interfacial oxide

[Yun88]. RE = 200 92 is 10-times higher than that of the con-

ventional polysilicon emitter without the interfacial oxide,

which is consistent with the increase in emitter specific








resistance corresponding to Sp(eff) decreasing from 105 to 102
cm/sec [Yun88]. The values of JEO (= 1.48x10-9 A/m2) and TE (=
4.92x10-10 sec) are correlated as evaluated by SUMM. Pmax
450 is five-times higher than that of the BJT with the nominal

polysilicon emitter without the interfacial oxide. Notice

however that the predicted Vcrit for this case is actually

higher than that for the non-optimized case (curve (A2)),

revealing that the large increase in RE negates the benefit

afforded by the decrease in Sp(eff)
If this large increase in the specific resistance result-

ing from the interfacial oxide were unavoidable, the BJT emit-

ter area AE would have to be enlarged to keep RE low enough

to realize the speed enhancement (i.e., the Vcrit reduction)

offered by the minimal Sp(eff). This design tradeoff is gauged

by curve (Bl) in Fig. 2.10. For these BiCMOS simulations, AE
of BJTs Zl and Z2 (see Fig. 2.1) was increased by four times

to lower RE from 200 (for curve (Al)) to 50 f. Note from the

comparison with the corresponding larger-area CMOS tD(VDD)

characteristic (B) that Vcrit is effectively reduced to less

than 2.7 V by this gate enlargement, in combination with the

low Sp(eff) afforded by the interfacial oxide.
Curve (A3) in Fig. 2.10 reflects the optimal polysilicon-

emitter design, predicting the BiCMOS speed performance when

the polysilicon emitter structure yields both low Sp(eff) and

low RE, for example as in the structure which includes the

perforated interfacial oxide [Ham92]. For this case, as for

curve (Al), the values of JEO and TE correspond to Sp(eff) =

100 cm/sec. RE = 20 0 is the same value used for curve (A2)








corresponding to an advanced BJT with the conventional poly-
silicon emitter (without the interfacial oxide). AE is not

increased from the nominal 4 m 2 value. Note that the pre-

dicted improvement in Vcrit, which is now 2.5 V, with respect

to that of the non-optimized case (curve (A2)) is about 250

mV, and the slope of the tD(VDD) curve at 3.0 V is low. These

results imply that even with 10% variation of VDD, which

might occur in actual circuits, this design is viable at 3.3

V and below, where the predicted BiCMOS tD is less than one-

third of that of the CMOS counterpart. Note also that tD is

reduced at higher VDD by the design optimization as well.

In summary, the simulation results in Fig. 2.10 suggest

that the dramatic reduction in Sp(eff), yielded by an interfa-

cial oxide in the polysilicon emitter structure, can render,

provided RE is not increased significantly, a substantial

reduction in Vcrit. Such an optimized polysilicon emitter is

perhaps that described in [Ham92], which could ensure the

speed superiority of BiCMOS over CMOS at VDD = 3.3 V and below
without additional changes in technology or circuit design.

However if the perforated polysilicon emitter is not techno-

logically feasible and an increase in emitter specific resis-

tance cannot be avoided as Sp(eff) is lowered, then decreasing

RE by increasing the emitter areas of the BJTs is a doable

design tradeoff. Note however that for further reduction in

VDD much below 3.3 V (e.g., to 2.2 V), the suggested optimal
polysilicon emitter design is probably not sufficient alone

to maintain the BiCMOS speed superiority.








2.6 Scaled BiNMOS


The simulation results of Figs. 2.8, 2.9, and 2.10

imply that BiCMOS design for VDD much below 3 V will require

modifications in the basic circuit. Even for our optimal

design shown in Fig. 2.8, the BiCMOS gate loses its advan-

tage over CMOS at VDD2.2 V for CL = 6 pF. The fundamental

reason for this limitation was discussed previously; Vol

cannot be reduced much at low VDD due to the inherent reduc-

tion in Icl*

BiCMOS circuit modifications to achieve the full-

swing operation needed for scaled deep-submicron technol-

ogies have been reported [Shi89], [Emb91]. Alternatively,

the BiNMOS gate [Wat89] is a candidate for the next-gener-

ation technology, which may not allow pnp transistors

needed for CBiCMOS. The circuit diagram of the BiNMOS gate

is shown in Fig. 2.11. An n-channel MOSFET M2' is used as

the pull-down device, avoiding the deterioration of the

BiCMOS M2 gate drive in (2.5) due to VBE2 and the offset

Vo0 in the M1 gate drive in (2.4). Thus use of BiNMOS is

compatible with our first-order design optimization aimed

at increasing M2 drive current by minimizing Vol in (2.5),

and could yield a virtual full-swing technique.

The pull-up delay of the BiNMOS gate is thus guaran-

teed to be superior to that of the CMOS gate even for VDD

less than 2 V. The pull-down delay comparison will be

defined by the efficacy of our first-order optimization.

It is estimated that Vcrit for an optimized BiNMOS gate,













VDD


Vout


Fig. 2.11 BiNMOS gate circuit.


VIN









which must exceed (VTn+Vol) where VTn is the M2' threshold

voltage, will be about 2 V. Hence, the voltage-scaling

effect of the BiNMOS gate is worse than that of CMOS, but

it is not as severe as that of the conventional BiCMOS

gate. Note however that the pull-down circuit of the BiNMOS

gate is the same as that of CMOS. Hence we cannot exploit

the current driving capability of the BJT for the pull-down

transient.

In Figs. 2.12(a) and (b), we plot the MMSPICE-simu-

lated BiNMOS, BiCMOS, and CMOS cascaded gate delays versus

VDD for the pull-up and the pull-down transients respec-
tively. The nominal threshold voltages were assumed. The

area of M2' in the BiNMOS gate was adjusted to equal the

total area of M2, M4, and Z2 in the conventional BiCMOS

gate (in Fig. 2.1), yielding Wn = 37 um. The pull-up circuit

was kept identical to that of the previously optimized

BiCMOS gate of Fig. 2.8. We can clearly see in Fig. 12(a)

that the pull-up delay of the BiNMOS gate is superior to

that of the BiCMOS gate because of the absence of the off-

set Vo0. In Fig. 12(b), we see that the pull-down delay of

the BiNMOS gate is superior to that of the BiCMOS gate as

well, but that the delay increases abruptly near VDD = 2 V

due to an unavoidable Vol, which tends to increase with

decreasing VDD (viz., decreasing Icl in (2.7). However, it

appears that the BiNMOS gate is a potentially useful deep-

submicron technology with VDD scaled down to 2.2 V.










(NEPI=2x1016cm-3, WEPI=0.37pm)
20.0 .... ... ........... .....


G--- CMOS, Eq. BiCMOS Az1=12pm2, WM1=16m
Q--a BiCMOS, Azi=4gm2, WMI=5im
0 BiCMOS, Azi=12p.m2, WM1=1 6pm
A- BiNMOS, Azi=12Im2, WM1=16p.m, Wn=37pm
15.0






1 10.0
4"-





5.0






0.0 .. *
2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

(a)


Fig. 2.12 MMSPICE-simulated BiNMOS, BiCMOS, and CMOS
gate delays versus VDD for (a) pull-up and
(b) pull-down transients; CL = 6 pF.









(NEPI=2x1016cm-3, WEPI=0.37gm)
40.0 .... .... .... ... .... ...
G--0 CMOS, Equi BiCMOS Azl=12pm2, WMI=
--- BiCMOS, Azl=4pim2, WMI=5gm
35.0 -- BiCMOS, AZ1=12pm2, WM =16pm
A--A BiNMOS, Azl=12pm2, WM1=16pm, Wn=3


30.0


25.0


: 20.0


15.0


10.0


5.0


0.0 ...
1.5 2.0 2.5 3.0 3.5 4.0
VDD (V)

(b)


Fig. 2.12 --Continued


5.0









2.7 Summary


A first-order design optimization of the conventional

BiCMOS gate at scaled supply voltage was derived from

MMSPICE device/circuit simulations. The design for near-

full-swing operation at VDD = 3.3 V is based on minimizing

the VBE offset voltage in the high logic level, and on

directly increasing the pull-down drive current to ease the

VDD-scaling-induced deterioration of the pull-down propa-
gation delay. It was found that the offset voltage depends

on the charge dynamics of the BJT coupled to the load

impedance near the end of the pull-up switching transient,

and can be minimized by increasing Ic at VBC(t) = 0 V while

slowing the BJT. The first-order optimal design exploits

this effect, and was defined by simulating gates with var-

ious layout dimensions of the BJT and the MOSFET in the

pull-up circuit. Appropriate changes in the MOSFET width

WM1, the BJT area AZ1 were found to be most effective in
reducing the offset. The substrate current problem that

accompanies the offset minimization, due to the BJT base-

node voltage overshoot, was investigated to ensure that it

is not a problem at VDD = 3.3 V. It was further shown by

simulations that the additional increase in pull-down

drive current afforded by increasing WM2 (= WM1/2) with WM1

and by reducing the MOSFET threshold voltages were needed

for complete optimization, as was the increased Az2 (= AZ1)

to limit quasi-saturation during the pull-down transient.

The superiority of the first-order optimal design over the









same gate-area CMOS for CL = 6 pF was demonstrated even for

VDD < 3 V by MMSPICE simulations of cascaded gates, which
are sensitive to the logic-level offsets. The possibility

of optimizing the polysilicon emitter-formation process to
further improve the first-order optimal design derived

from variations in layout dimension was also investigated.

The optimal polysilicon emitter design is perhaps that with

a perforated interfacial oxide [Ham92]; otherwise an area

(viz., AE) versus speed (viz., RE) design tradeoff can be

effected. The superiority of the optimal polysilicon emit-

ter design over the same gate-area CMOS for CL = 6 pF was

demonstrated for VDD scaled down to even 2.5 V.

For further reduction in supply voltage down to 2.2

V, the BiNMOS gate was shown to be of possible use when the

complementary pnp BJT is not available for CBiCMOS. MMSPICE

simulations predicted that the delay of an optimal BiNMOS

gate can be superior to that of BiCMOS for VDD scaled down

to near 2 V, suggesting its utility for deep-submicron

technologies.














CHAPTER 3
SUBSTRATE PNP TRANSISTOR MODELING


3.1 Introduction


In Chapter 2, it was shown by MMSPICE simulations that

during pull-up and pull-down transients of a conventional

BiCMOS gate, the npn BJTs may go into saturation or quasi-

saturation modes. The saturated or quasi-saturated npn BJT

will increase the internal forward bias of the emitter-base

junction of the parasitic substrate pnp transistor (see

Fig. 1.1) and may activate it. If the current gain of the

substrate pnp transistor is high enough, excessive sub-

strate current may flow. The substrate current flowing dur-

ing the transient operation of a BiCMOS gate can cause

substrate bias instability or latch-up, and is a problem

in integrated circuit design [Kaw89]. Since the substrate

pnp transistor tends to be activated by the npn BJT in a

conventional BiCMOS gate, a physical substrate pnp model

with linkage to npn model is crucial for assessment of a

BiCMOS design in terms of reliable circuit operation.

In Section 3.2, it is shown by measurements how the

substrate (pnp collector), current Ipc depends on VBE(npn)

and VBC(npn). We try to develop a physical model for Ipc

which properly accounts for the hole transport in the npn









collector region under the intrinsic base for saturated or

quasi-saturated modes of the npn transistor. However, the

model obtained by expanding the physical electron current

analysis of the MMSPICE BJT model becomes trivial due to

the assumption of flat minority-hole quasi-Fermi level in

the conductivity-modulated epi-collector region. Thus a

comprehensive study of the substrate pnp transistor based

on numerical device simulation is needed to understand the

hole current flow in the actual npnp device structure.
In Section 3.3, the physical mechanism underlying the

turning-on of the substrate pnp is investigated by using

PISCES simulations of an isolated pnp and a pnp in an

actual npn transistor structure. It is proved that the ter-

minated n* buried layer near the oxide-isolation increases

the current gain due to a reduced Gummel number and results

in easy turn-on of the substrate pnp at relatively low npn

VBE. The pertinent carrier transport is two-dimensional.

In Section 3.4, based on the insights gained by the

physical modeling and the PISCES simulations, a semi-

empirical substrate pnp model depending on an effective

Gummel number and the area of the interface region between

the oxide-isolation and the buried layer is defined with

emphasis on the linkage of the model to that of the npn.

The model is shown to be adequate for predicting the turn-

on VBE(npn) and estimating Ipc, and is thus useful for

assessing the significance of Ipc in the transient opera-

tion of the BiCMOS gate, for both forward and reverse

biases on the base-collector junction.









In Section 3.5, the network representation of the

model and the model implementation in the existing MMSPICE

BJT model are discussed. Then an application of the model

in predicting the transient substrate current of a BiCMOS

gate is described. The predicted Ipc is shown to be signif-

icant for VDD = 5 V but to be insignificant for VDD = 3.3 V.


3.2 Initial Model Development


In this development, the substrate pnp transistor con-

sisting of the npn base (p), the n-epi/n' buried layer, and

the p-substrate as shown in Fig. 1.1 is considered. Fig.

3.1 shows measured npn collector current Inc, npn base cur-

rent InB, and substrate (pnp collector) current Ipc versus

VBE(npn) for VBC(npn) = 0.4, 0, and -1 V. These curves indi-
cate that advanced npn BJTs, with oxide isolation, have

significant dc Ipc at high VBE(npn) (> 1.0 V), even for

VBC(npn) = -1 V. Note that Ipc depends on VBE(npn) and

VBC(npn); the larger the VBC(npn), the lower the turn-on

VBE(npn) above which Ipc becomes significant. Hence physical
Ipc modeling is necessary to account for these dependencies
on applied biases. In this section, we try to derive a

physical substrate pnp model by expanding the collector

regional analysis of the BJT model in MMSPICE. Insights on

the substrate current flow are attained from the physical

model development.

The model development is focused on the substrate cur-

rent that tends to be activated by an ohmic or non-ohmic













(Device name: PCTN2x8, Wafer number: W11


-1.0


-2.0


-3.0


-4.0


-5.0


-6.0


-7.0


-8.0


-9.0


-10.0


-11.0


-12.0
0.0


Fig. 3.1


Measured npn collector current Inc, npn
base current InB, and substrate current Ipc
versus VBE(npn) curves for VBC(npn) = 0.4, 0.
and -1 V.


0.2 0.4 0.6 0.8 1.0 1.2


VBE(,) (V)









quasi-saturation of the intrinsic npn transistor. The

intrinsic forward bias (VBco) of the base-collector (B-C)

junction caused by the quasi-saturation is usually larger

than the applied voltage (VBc'), excluding the voltage

drops across external Rc and RB. TAerefore, we reason ini-

tially that the substrate pnp transistor is driven by the

B-C junction intrinsic forward bias (VBco), especially when

the npn BJT is in quasi-saturation. Using VBco as a drive

for the substrate transistor facilitates the model linkage

to the existing npn model in MMSPICE in which VBco is eval-

uated by using numerical iteration for given VBE and VBC.

When the npn transistor goes into ohmic or non-ohmic

quasi-saturation, there may exist a conductivity-modulated

quasi-neutral region in the epi-collector. To support the

quasi-neutrality in this region, there also may exist hole
current flowing into the collector region, part of which

is the substrate current. The hole current transport in

this quasi-neutral region is affected by the electric field

set up by the electron distribution and the electron cur-

rent. The electric field E is found from the electron

transport equation by rearranging terms:

Jn Dn 1 dn
E = (3.1)
qnpn u n dx

where Jn is the electron current density in the npn

collector. By substituting the electric field into the hole

current equation and subsequently using the assumptions of

quasi-neutrality and negligible recombination in the









conductivity-modulated epi-collector region, we can
express the hole (substrate) current Ipc as follows:
[ (VBco) -exp(VBcI)
q2A2Dpnn i exp V-) exp( )]
Inc qAInWQNNepi V VT (32)
I =+ (3.2)
pC b bQn Qn

where b is the ratio between electron and hole mobilities,

Inc is the npn collector current, WQN is the width of the
conductivity-modulated epi-collector region, VBCo and VBcI
are the quasi-Fermi level separations at x = 0 and x = WQN,

respectively, and Qn is the electron charge density in the

conductivity-modulated epi-collector region:
WQN
Qn = qA ndx. (3.3)
0
The unknowns Inc, WQN, and Qn in (3.2) can be obtained

by using the results of the collector analysis of the

MMSPICE/QBBJT model, which uses a modified Kull [Kul85]

analysis [Jeo87] to solve for the majority-electron cur-

rent and the stored excess charge in the conductivity-mod-

ulated quasi-neutral epi-collector region. By substituting
into (3.2) the unknowns obtained from the MMSPICE/QBBJT

collector analysis, we get merely a trivial solution for

the substrate current. Since the Kull analysis assumes a

flat minority-hole quasi-Fermi level in the conductivity-

modulated epi region, we find that it is virtually impos-

sible to predict the Ipc; only the recombination current

defined by the stored excess charge can be modeled based

on the (modified) Kull analysis. These insights gained from









the physical modeling call for further investigation of the

substrate transistor using PISCES simulations.


3.3 PISCES Simulations


In this section, the actual mechanism of the substrate

current flow will be investigated by using PISCES simula-

tion of an isolated pnp and a pnp in an npn structure. The

objective of the simulation of an isolated pnp transistor

is to verify the anomaly in the actual current gain of the

pnp with very high base doping. The pnp in an npn structure

is simulated to verify the actual turn-on VBE(npn) and mag-

nitude of Ipc, which are crucial in predicting Ipc in the

transients of a conventional BiCMOS gate.

In Fig. 3.2, the measured collector current Ipc and

base current IpB versus VEB(pnp) of an isolated pnp transis-

tor of MOSAIC III technology [Zde87] are shown. The tran-

sistor consists of the npn external base (p+ emitter), the

npn collector (n/n' base), and the substrate (p collector).

The emitter peak doping concentration is ~ 7x1019 cm3 and

the junction depth is ~ 0.4 im. The base consists of an n-

epi with constant doping of 2x1016 cm-3 and width of 0.26

Lm, and an n' buried layer with peak doping of 2x1019 cm-3

and width of 1.4 im. The p-substrate has constant doping
of 2x1015 cm-3 and is contacted at p channel-stop region.

Note that even though the base doping is very high, which

results in high Gummel number, the peak current gain is

greater than one.













(Device name: PCTN2x8. Wafer number: W18, Vo.,)=2.0 V)
-1.0 *'


-2.0


-3.0- Ic
----.------. I.

-4.0


-5,0


o -6.0


-7.0
C3

-8.0


-9.0


-10.0


-11.0


-12.0 '
0.2 0.4 0.6 0.8 1.0

V v) (V)





Fig. 3.2 Measured Ipc and IpB versus VEB(pnp) curves
for the isolated substrate pnp transistor.









By simulating different isolated substrate pnp struc-

tures, agreements in order-of-magnitude between measured

and simulated peak current gain and Ipc magnitude will be

sought to gain needed physical insight. Two isolated pnp

structures with constant doping contour plots, used for

PISCES simulations, are shown in Figs. 3.3(a) and (b).

Structure (a) is basically a one-dimensional structure

with the n+ buried layer under all the p+ region. Structure

(b) resembles a real structure as shown in Fig. 1.1, which

has oxide-isolation and channel-stop implantation, but has

the buried layer terminated prematurely at one edge. This

structure thus includes a lightly doped region that could

result from excess spacing between the oxide-isolation and

the buried layer in layout design, or from compensation of

the n buried layer by the p+ channel stop under the oxide-

isolation. Doping levels and junction depths of the two

structures are chosen to approximate those for the struc-

ture used in measurements described above.

In Figs. 3.4 (a) and (b), the PISCES-simulated Ipc and

IpB versus VEB(pnp) plots are shown for structures (a) and

(b) in Fig. 3.3, respectively. For the one-dimensional

structure, Ipc is much smaller than IpB, which implies that

the current gain is much smaller than one. There may be

possible uncertainties in the structural parameters such

as the peak concentration and depth of the buried layer,

but varying these parameters does not affect the magnitude

of the collector current much. For the realistic structure,

the magnitude of Ipc and the peak current gain are compa-






60



o (a)




o '------------------ --- -----------' -----
o4 n+ B/L
0.-- ----- n-ep-____
o ..................-..... ...... `- .- -.--
0o:





p-sub


o:



b.-O "' 0 .20D i'sAt~ance vaMicrons)' 1'.20 1.40
S(b)









04 pu n+ B/L
O_'L-----.--------.~--~--L------.-- .------.------
2 r








-o0:







or
oi-
bisa O .0 i



o (b)





















o -s ......... ...-.,-.' ...0.- - .- .. .' .-. ^ -. r .. :- ^
Fig. 3.3 Structural diagrams with constant doping-epi






simulation, of an isolated substrate pnp
I.





Distance (Microns)




Fig. 3.3 Structural diagrams with constant doping
contour plots, used for the PISCES
simulation, of an isolated substrate pnp
transistor; (a) is for a one-dimensional
structure and (b) is for a realistic
structure.












-1.0


-2.0


-3.0


-4.0 ....-- .... IP


-5.0


O -6.0


? -7.0


) -8.0


-9,0


-10.0


-11.0


-12.0


-13.0 '
0.2 0.4 0.6 0.8 1.0 1.2



(a)



Fig. 3.4 PISCES-simulated Ipc (= IsUB) and IpB versus
VEB (pnp) plots. (a) is for the one-
dimensional structure shown in Fig.
3.3(a); (b) is for the realistic structure
shown in Fig. 3.3(b).













-1.0


-2.0


-3.0 Ic (=I
.......- (=I .........
---------- 14I

-4.0


-5.0


- -6.0

8 //

L *



-9.0


-10.0


-12.0


-12.0 .....""

-13.0
-13.0 I - ^ -- -- -- -- -- --
0.2 0.4 0.6 0.8 1.0 1.2



v(b)
(b)


Fig. 3.4 --Continued









rable to the measured values. In Fig. 3.5, the vector plot

for the hole current is shown for VEB(pnp) = 0.8 V at which

the current gain peaks. Note that most of the hole current

flows through the interface between the oxide-isolation

and the terminated buried layer, where the doping concen-

tration is decreased to 1018 cm-3. From other simulations,

it was found that the magnitude of Ipc is very sensitive to

the width of this interfacial region, which is determined

by the distance between the oxide-isolation and the buried

layer edge.

Next, the substrate pnp structure in an npn with ter-

minated buried layer is simulated to verify turning-on of

the linked substrate transistor while the npn transistor

is biased at high VBE (> 1 V) with VBC O V. The simulated

structure with constant doping contour plots is shown in

Fig. 3.6. The oxide isolation is removed from the structure

in Fig. 3.3(b) due to the limitation in the total number

of grid points for PISCES simulation. Doping densities and

thicknesses of the extrinsic base, the n-epi, the n+ buried

layer, and the substrate region are same as those of the

structures in Fig. 3.3. The intrinsic region of the npn

transistor represents that of MOSAIC III [Zde87]. Hence it

has the polysilicon emitter, the peak doping of the intrin-
sic base of 2x1018 cm-3 with thickness of 0.15 pm, and

the epi thickness of 0.46 gm. The external RE, RB, and Rc

used are 20, 20, and 100 f, respectively. In Fig. 3.7, the

PISCES-simulated and measured Inc, InB, and Ipc versus

VBE(npn) plots are shown for VBC(npn) = 0.4, 0, and -1 V. Note

























-1-14 -1-4 --4----
r C *
I


- ~ ~ ~ ~ ~ 1 4-
. . .


0.50


1.00


1.50 2.UU
Distance (Microns)


4 u;.j1 1"" '


Fig. 3.5


PISCES-simulated hole-current flow vectors
for VEB = 0.8 V, at which the current gain
peaks, for the structure in Fig. 3.3(b).


S.00


h


1


J .UU


z U





















Co ' ' I p- Base '
0 '------------,--------
* ^ -.. . . . . . -- ^


0)
r





U
o



I


p-sub


0.00


0.50


1.00


- I 1 I
1.50


I
2.00


Distance (Microns)












Fig. 3.6 Structural diagram, with constant doping
contour plot, of the pnp transistor
linked to npn with buried layer
terminated.


r--1---r--~--

'4


I ,


,


I I.,n .


I


I













1 .0 ,-- - -- -- --
--.-- II, Measured
A---- I,, Measured
-2.0 ~--- Ip, Measured
--- I, PISCES
SI, PISCES
-3.0 -------- .. PISCES


-4.0


-5.0




C
-7.0


-8.0


-9.0 1


-10.0


-11.0


-12.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2

VS(p) (V)

(a)



Fig. 3.7 PISCES-simulated and measured Inc, InB, and
Ipc versus VBE(npn) plots V and AE = 8.64
pm Rc=100 a; for VBC(npn) = 0.4, (b)
for VBC(npn) = 0.0, and (c) for VBC(npn) =
1V.













(Device name: PCTN2x8. Wafer number: W1


-1.0 -


-2.0


-3.0


-4.0


-5.0


-6.0


-7.0


-8.0


-9.0


-10.0


-11.0


-12.0
0.0


VE (V)


(b)


Fig. 3.7 --Continued


0.2 0.4 0.6 0.8 1.0 1.2

























































0.2 0.4 0.6 0.8 1.0 1.2 1.4


VK() (V)


(c)


Fig. 3.7 --Continued


-1.0



-2.0



-3.0


-4.0



-5.0



-6.0


-7.0



-8.0



-9.0


-10.0



-11.0


-12.0 L-
0.0









that good agreement between measured and simulated cur-

rents is obtained. In Fig. 3.8, the PISCES-simulated Ipc,

Inc, and InB versus VBE(npn) curves are plotted for different
RC values. When Rc is increased, significant decrease in

the turn-on VBE(npn) and increase in the slope of Ipc occur.

The decrease in the turn-on VBE(npn) with increasing Rc is

caused by the increase in the internal bias VBC' of the B-

C junction with increasing Rc. Since the substrate current

Ipc depends exponentially on the applied voltage VBC the
increase in VBC' with increasing Rc causes the increase in

the slope of Ipc with increasing Rc. Predicting the turn-

on VBE(npn) and the magnitude of the steady-state Ipc with

good accuracy is crucial for assessing the significance of

the transient Ipc in a conventional BiCMOS gate.

Since the modeling approach discussed in the previous

section, which assumes that the substrate pnp is driven by

VBCO, yields a trivial prediction for Ipc, the actual mech-
anism of the substrate current flow will be clarified by

analyzing the PISCES simulation results. In Figs. 3.9(a)

and (b), the PISCES-simulated quasi-Fermi potentials in y-

direction at x = 0.1 im and 2.0 im are plotted for low-Ipc

case and high-Ipc case, respectively, for VBC(npn) = 0 V.

For the low-Ipc case, VBE(npn) = 1 V and for the high-Ipc

case, VBE(npn) = 1.15 V. As we can see in the structural

diagram in Fig. 3.6, the region near x = 0.1 im represents

the terminated buried layer with lowered concentration

whereas the region at x = 2.0 im represents the intrinsic

base region with the buried layer concentration unchanged.













-1.0


-2.0


-3.0


-4.0


-5.0


-6.0


-7.0


-8.0


-9.0


-10.0


-11.0


-12.0


-13.0


-14.0 L
0.0


Fig. 3.8


0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

v,) (v)


PISCES-simulated Inc' InB, and Ipc versus
VBE(npn) curves for the same structure with
Fig. 3.8 but with Rc = 10, 50, and 100 9.


















io -- Poten-

o QFH-------------

0 C V
0 / \ \ QFE-----------



S.1-\ -o
O o_





0.00 1.00 2.00 3.00 4.00
Distance (Microns)




( x=2.0 ilm, in y-direct.)
o

(0c case ------) = 1.15\V)
-0
- o ..... .~---. \ Poten
o .- QFH ------------
> I QFE-- -----


-1 1



... ..\ ..... .......






0.00 1.00 2.00 3.00 4.00
Distance (Microns)


(a)


Fig. 3.9 PISCES-simulated quasi-Fermi potentials in y-
direction at x = 0.1 Im and 2.0 jLm. (a) is for
low Ipc case (VBE(npn) = 1 V); (b) is for high
Ipc case (VBE(npn) = 1.15 V).






















O
o


0


S*0
-I I
r0




-4









C
0
C









0



-'-40
MI-
'-l










& 0


2.00 3.00

Distance (Microns)


Fig. 3.9 --Continued


Distance (Microns)









The intrinsic base-collector junction is located near x =

2.0 pm and y = 0.25 pm. For low Ipc (~ pA) case, the intrin-

sic forward bias VBCO under the intrinsic base region (at
x = 2.0 pm) is high, while the internal bias VBC' (at x =

0.1 pm), excluding the voltage drops across Rc and RB, is

low. This confirms that Ipc is not driven by VBCo but by

VBC For high Ipc (- 2 gA) case, the internal bias VBC is

also high (~ 0.8 V) and further verifies that Ipc is driven

by VBC From hole current vector plots, it was shown that
the substrate current flows dominantly through the oxide-

isolation/buried layer interface region near x = 0 pm. The

importance of VBC' for activating Ipc supports the fact that

Rc and RB affect the turn-on VBE(npn) much because varia-

tions in Rc and RB directly affect VBC' on which Ipc depends

exponentially.
From these simulations, we conclude that Ipc is driven

by VBc' and the buried layer is effectively bypassed at one
edge; that is, the buried layer is ineffective in blocking

the substrate current. Some empiricism is necessary for

modeling the substrate current due to the two- or even

three-dimensional nature of the hole current flow in the

actual device structure.


3.4 Semi-Empirical Modeling


In this section, a semi-empirical Ipc model will be

derived based on insights gained by the physical modeling

and the PISCES simulations, and the model will be verified









by measurements. The nature of the substrate current is

two-dimensional because it flows through the interface

between the oxide-isolation and the terminated buried

layer region as shown in Fig. 3.5. This necessitates a

semi-empirical modeling approach since it is virtually

impossible to characterize the two-dimensional effect with

analytical expressions and physical parameters only. The

model will be used for predicting the characteristic of the

substrate pnp driven by the saturated or quasi-saturated

npn transistor, but not for the isolated parasitic pnp

transistor. This restriction simplifies the modeling since

we do not need to include the base current of the substrate

pnp transistor.

The fundamental Moll-Ross relation [Mol56] can be used

for modeling the collector current (Ipc) of the substrate

pnp transistor because the current gain is greater than

one; that is, recombination in the neutral base region of

the pnp can be neglected with minor error in Ipc. As was

explained in the previous section, Ipc is driven by VBC

which is given as:


VB = VBC +IncRc-InBR (3.4)

where RC is. the external collector resistance including the

contact and the buried layer resistance, and RB is the

external base resistance. The VBc' is already available

from the npn analysis in the QBCT routine, and hence the

model linkage to the npn model can easily be achieved. From

the PISCES simulations discussed in the previous section,









it can be argued that the substrate current does not depend
on the whole base area but on the area of the interface

region between the oxide-isolation and the buried layer.
Based on these insights, Ipc can be represented as


qADpn? exp VBc -
I = NG(3.5)
pc- NGeff

where Ap is an effective cross-sectional area for the
current flow. It can be defined as

Ap = P-AW (3.6)

where P and AW are the perimeter length and width of the

interface region through which Ipc flows. P can be

determined by measuring the total length of the oxide-

isolation/buried layer interface in the transistor layout.

For typical advanced BJT technology with double-

polysilicon, poly-emitter, and self alignment, P can be

estimated given as

AE
P = 2(WE+2 LBE) + ( +2-LBE) (3.7)
WE

where WE is the emitter width, LBE is the width of the

extrinsic base, and AE is the emitter area, all of which

are parameters of MMSPICE/QBBJT model and are known. NGeff

is the effective Gummel number of the pnp peripheral base
region, which is difficult to express with physical

parameters due to the two-dimensional current flow. To

reduce the number of model parameters needed, the pre-









exponential parameters in (3.5), including the empirical
parameters AW and NGeff, can be incorporated into one:



Ip = JcPP exp -) (3.8)



where the saturation current density per unit length (A/m)

JCop = qDpni2AW/NGeff and is the only empirical parameter
needed to account for the two-dimensional current flow.
For the verification of the semi-empirical model, Inc

and Ipc of the npn transistor structure with emitter area
AE of 8.64 pm2 (WE = 1.2 Lpm) in the MOSAIC III technology
[Zde87] was simulated. The model parameters were evaluated
by using SUMM [Gre92]. MMSPICE-simulated Inc and the semi-
empirical model-predicted IpC versus VBE(npn) are contrasted

to the corresponding measurements in Fig. 3.10 for differ-
ent VBc(npn) of 0.4, 0, and -1 V. RE, Rc, and RB affect the
high-VBE(npn) portion (> 1 V) of Inc much. Moreover, as shown
in (3.4), Inc, Rc, and RB influence the internal bias VBC'

of the npn B-C junction, which in turn determines the turn-
on VBE(npn). Hence matching the MMSPICE-simulated Inc to the
measurement at high VBE(npn) by adjusting RE, Rc, and Rg is
crucial to the accurate prediction of the turn-on VBE(npn).
The saturation current density Jcop, which is influenced by

the structural parameters NGeff and AW, affects Ipc for

given VBE(npn) and VBC(npn) because it determines the current
gain of the substrate pnp transistor. In tuning the model-

predicted Ipc to measurements, first, Rc, RB, and RE are









10-1

10-2

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10

10-11

10-12


VBE (V)


Fig. 3.10


MMSPICE-simulated Inc and the semi-
empirical model-predicted Ipc versus
VBE(npn) contrasted to measured Inc and Ipc.
AE = 8.64 gm, RE = 9 RB = 50 9, Rc =50
D, and Jcop = 2.5x10- A/m were used for
the model prediction; (a) for VBC(npn) Of
0.4 V, (b) for VBc(npn) of 0.0 V, and (c)
for VBC(npn) of -1.0 V.









10-1
S'--+ c, Measured
10-2 nnc, MMSPICE
-- p Ipc, Model with
10-3 C, Measured
------- Ipc, MMSPICE

10-4 r

10-5

S10-6
0
I6 10-7


10-8

10-9

10-10

10-11

10-12
0.2 0.4 0.6


(b)


Fig. 3.10 --Continued


VBE (V)









10-1 . .

+2-- nC, Measured
10-2 inc, MMSPICE-simulate
Ipc, Model with VBCO f m MMSPICE
10-3 pc, Measured
------- pc MMSPICE-sim ated

10-4

10-5

10-6
a-


10-
10-8 r

10-9


10-11
10-11

10 -12, , r . . ,
0.2 0.4 0.6 0.8 1.0 1.2
VBE (V)

(c)


Fig. 3.10 --Continued









adjusted to match the high-VBE(npn) portion of MMSPICE-sim-

ulated Inc and the model-predicted turn-on VBE(npn) to mea-

surements for three VBC(npn) values. Then the Jcop is
adjusted to fine-tune the predicted turn-on VBE(npn) and the

saturated Ipc at high VBE(npn). RE = 9 RB = 50 , Rc = 50

2, and JCOP = 2.5x10-15 A/m resulted from the fitting, and

were used for the model predictions in Fig. 3.10. Note that

the turn-on VBE(npn) is predicted with reasonable accuracy

especially for VBC(npn) = 0 and 0.4 V, which are likely to

be encountered at the end of the transient response of a

conventional BiCMOS gate, and that the turn-on VBE(npn)

becomes smaller as VBC(npn) becomes higher. The model pre-

diction for VBC(npn) = -1 V is not as accurate as for VBC(npn)

= 0 and 0.4 V due to perhaps more significant two-dimen-

sional transport effects at the collector-substrate junc-

tion. The inaccuracy is not crucial for predicting the

transient substrate current in a BiCMOS gate because for

negative VBc(npn) the turn-on VBE(npn) is usually higher than

the normally encountered values (< 1.1 V) in actual tran-

sients, as shown in Fig. 3.10(c). The measured substrate

current at very high VBE(npn) (> 1.2 V) becomes saturated

partly because VBc' becomes flat in this voltage range due

to flat Inc, and partly because quasi-saturation occurs due

to the high pnp-collector (substrate) resistance. The sub-

strate resistance is not accounted for in this model to

avoid the additional complexity in the implementation in

MMSPICE. As a result, the model prediction is not accurate

at very high VBE(npn), especially for higher VBC(npn), at









which Ipc saturation occurs at lower VBE(npn). Since we are

interested in the VBE(npn) range near the turn-on point,

which is most frequently encountered in BiCMOS gate tran-

sients, the model inaccuracy at very high VBE(npn) is not

important. To stress the extrinsic nature of Ipc as con-

cluded in Section 3.3, also included in Fig. 3.10 are model

predictions based on (3.8) but using VBCo instead of VBC

as the driving bias. Note that the predicted turn-on

VBE(npn) implied by VBCo is significantly lower than what
the measurements show. This discrepancy further confirms

that the substrate current in the advanced BJT structure

(with a buried layer) is not driven by the intrinsic bias

(VBco) at the base-collector junction.
The model's dependence of Ipc on the perimeter rather

than the area, as given in (3.8), can be verified more

directly by predicting substrate current of the npn tran-

sistor structure with smaller emitter area (effective AE =

1.2x3.2p m2). In Fig. 3.11, MMSPICE-predicted and measured

Inc and Ipc for the device with smaller emitter area are
shown. The scaling equations, given in Section 4.4, for

physical variations of area-dependent model parameters

were used to predict the scaled npn characteristics. To

fine-tune Inc in high-VBE(npn) region, which is crucial for

the accurate prediction of the substrate current, Rc was

adjusted from 84 to 80 9. Note that the predicted Ipc is

matched well with the measured one without tuning JcoP.

This would not have been achievable if an area-dependent

model were used.









10-1 . . . . . .

10-2 Inc Measured
10- Inc, MMSPICE-simulated
p--a I Measured
10-3 -""-- IpC, MMSPICE-simulat


10-4

10-5

10-6 .
10
oC 10-7
_.-





10-9 f I

10-10 "


10-11

10-12
0.2 0.4 0.6 0.8 1.0 1.2
VBE (V)


Fig. 3.11 MMSPICE-predicted and measured Inc and Ipc
for the device with smaller emitter area
(AE = 1.2x3.2 pm2) for VBC(n n) = OV with
RE = 20 1 RB =84 f, Rc = 80 and Jcop
= 2.5x10 A/m.









3.5 MMSPICE Implementation/Application


In this section, the network representation of the

model with explanation about simplification of the model

and the model implementation in MMSPICE are described. Then

an application of the model is demonstrated by simulating

the substrate current during the switching transient of a

conventional BiCMOS gate.

Fig. 3.12 shows the network representation of the sub-

strate pnp model linked to the npn model. IB, Ic, and dQ/

dt current sources pertain to the npn model. Ipc represents

the pnp collector current (3.8) determined by the internal

npn B-C junction voltage, excluding the voltage drops

across Rc and RB as defined in (3.4). The pnp base current

IpB (which we have not modeled) is shown partitioned into
two predominant components: IE, which represents the
injected hole recombination in the npn collector with elec-

trons from the npn emitter, and I which represents the

hole recombination with electrons from the npn collector.

The decomposition of IpB is similar to partitioning of the

stored excess charge in the npn collector [Jeo89] and is
E C
physical. As long as IB (< IC) >> IpB IB and pB can be

neglected in the network representation without signifi-

cant error in the substrate current. Another reason that

we can neglect the pnp base current is that the primary

purpose of the modeling is to predict only the substrate

current. This is also why pnp charging currents are not

included in the model, in addition to the fact that the






84




Collector



I- RC

IpC

pB


Base RB Substrate

dQBc dQsuB

S. dt dt
'B dQBE IpB
dt



RE


Emitter







Fig. 3.12 Network representation of the substrate pnp
model linked to the npn model.









charge dynamics of the substrate pnp will not affect the

speed of the npn transistor much. The primary purpose of

the model is to predict leakage current during BiCMOS tran-

sients. The substrate pnp model thus needs only one circuit

element, Ipc.

The substrate pnp model is implemented by modifying

the MMSPICE routines affected by the addition of the cur-

rent source Ipc, the new model parameter Jcop, and other

features discussed later. Because the substrate node

already exists in the MMSPICE npn model, no additional node

generation is necessary, which simplifies the model imple-

mentation. The substrate pnp model is implemented as an

optional feature of MMSPICE-2.1. If the new model parameter

Jcop is set to a value greater than zero on the model card,
the substrate pnp modeling is activated. The substrate pnp

analysis is skipped if Jcop is set to zero, which is the

default value. The dc substrate current Ipc is implemented

as an operating variable, which is printed out in the dc

operating-point information of a transistor appearing in

the MMSPICE output of the .OP analysis.

The model utility is demonstrated by simulating the

transient substrate current of a conventional BiCMOS gate.

As was discussed in Chapter 2, the base node voltage of a

bipolar transistor in the BiCMOS gate can overshoot the

collector node voltage, being governed by the magnitude of

the load capacitance and the BJT device parameters. The

higher the base voltage overshoot is, the larger the sub-

strate current will be. To exemplify how significant Ipc









might be, the BiCMOS design including the BJT with perfo-

rated emitter, which has the largest base voltage overshoot

as shown in Chapter 2, is simulated. Fig. 3.13 shows
MMSPICE-simulated transient substrate current Ipc and VBC

of Z1 of the BiCMOS circuit (Fig. 2.1) for three different

VDD values. Note that Ipc for VDD = 5V is greater than 10
.A and may be problematic for reliable circuit operation.

Note also that as VDD is decreased, Ipc decreases rapidly,

which implies that the substrate current for VDD less than

3.3 V is probably not a problem.


3.6 Summary


A simple yet accurate model for the parasitic sub-

strate pnp transistor in an advanced npn BJT structure,

which can easily be activated and is problematic for reli-

able BiCMOS circuit operation, was developed. A physical

model, derived by expanding the MMSPICE/QBBJT electron

current analysis in the collector region of the quasi-sat-

urated npn transistor, was found to be trivial due to the

assumption of flat hole quasi-Fermi level in the quasi-neu-
tral epi-collector region. Hence, PISCES simulations were

done to investigate the physical mechanism underlying the

turn-on of the substrate current. Based on insights gained

from the PISCES simulations, a semi-empirical substrate

pnp current (Ipc) model was defined with emphasis on the

linkage of the model to that of the primary npn BJT. Model

predictions were compared with measured data, showing the









10-4



10-5



10-6


10
10-8


10-9



10-10



10-11
0.Oe+00


5.0e-09 1.0e-08
Time (sec)


S. 1.0





SVDD=5.0V
SVDD=4.0V
SVDD=3.3V
0.5
)r VDD=5.0V
)r VDD=4.0V
)r VDD=3.3V o

N




0.0









S ' -0 5
1.5e-08 2.0e-08


Fig. 3.13


MMSPICE-simulated transient Ipc and VBC
of Z1 of the BiCMOS gate tor three
different VDD values. Note that
transient Ipc for VDD=5V is greater than
10 gA.






88


simple model to be sufficiently accurate for prediction of

the turn-on VBE(npn) and Ipc magnitude. An application of

the model to predict the transient substrate current of a

switching BiCMOS gate was also demonstrated. The result

shows that the substrate current is significant in opti-

mally designed circuits (including perforated polysilicon

emitter contacts defined in Chapter 2) operating at VDD =

5V, but is decreased to an insignificant level as the power

supply voltage is lowered to 3.3 V.















CHAPTER 4
MMSPICE BENCHMARKING


4.1 Introduction



To assess the utility of MMSPICE and the BJT model,

which has been improved considerably [Hon91], [Jin92]

after the development of the first version [Jeo90], the

model should be benchmarked with respect to the SPICE/Gum-

mel-Poon(GP) model, which has been the workhorse for BJT

simulation for past two decades. The benchmarking

described herein is intended to demonstrate important

advantages and noteworthy disadvantages of MMSPICE/QBBJT

relative to SPICE/GP. The possible key advantages of the

MMSPICE/QBBJT model are eased parameter extraction and

parametric correlation, which derive from the physical

nature of the model and which enable meaningful TCAD, man-

ufacturing-CAD, statistical analysis, and sensitivity

analysis at the circuit level. Also quick device/circuit

simulation based on technology and BJT structure informa-

tion is enabled. This capability can be a useful feature

for circuit designers even when test devices are not avail-

able at early stages of technology development. The inher-

ent accuracy in high-current regions of operation,

predictability, and scalability are other anticipated

l ,









advantages of the model. Possible disadvantages are model
inaccuracies in the hard-saturation region for low collec-

tor current, and increased run-time compared to SPICE/GP.
The advantages seem to outweigh the disadvantages, imply-

ing that the MMSPICE/QBBJT model is potentially a viable

replacement for SPICE/GP.

In this chapter, the MMSPICE benchmarking is done by

demonstrating some of the advantages and disadvantages

mentioned previously. In Section 4.2, parameter specifica-

tion for MMSPICE/QBBJT and SPICE/GP models is discussed.

Then in Section 4.3, parameter tuning for the MMSPICE/QBBJT

model is explained with emphasis on ease and physical

nature of tuning in contrast to the empirical nature and

numerical intensiveness of the parameter optimization

required for the SPICE/GP model. The model parameters tuned

are those which have uncertain values and which dominantly

affect device performances in specific regions and modes

of operation. In Section 4.4, MMSPICE/QBBJT model scal-

ability is demonstrated by predicting the device charac-

teristics for increased emitter area with physical

variation of parameters influenced by area scaling. This

model scalability cannot be achieved with the SPICE/GP

model due to its empirical accounting of device character-

istics for specific regions of operation. In Section 4.5,

MMSPICE convergence and inaccuracy in hard saturation are

discussed. Finally in Section 4.6, run-time and memory-

usage of the MMSPICE/QBBJT model are compared with those

of the SPICE/GP model. Usefulness of the physical paramet-









ric correlation mentioned above is demonstrated by devel-

oping new statistical-simulation and sensitivity-analysis

methods using MMSPICE/SUMM in Chapter 5.


4.2 Parameter Specification for Comparable Models


The model parameters used for the benchmarking are

based on MOSAIC III [Zde87], which was developed at Motor-

ola and is an advanced self-aligned BJT technology with

polysilicon emitter and oxide-isolation. The Gummel-Poon

model parameters extracted and optimized for a specific lot

by the Motorola technology development team were directly

used for the benchmarking. Also ac parameters were

extracted and optimized by them to fit the measured fT ver-

sus Ic characteristics. The model parameters for the

MMSPICE/QBBJT model were extracted by using SUMM [Gre92]

from the nominal one-dimensional (1-D) doping profile for

MOSAIC III obtained from SUPREM output. SUMM extracts a set

of MMSPICE/QBBJT model parameters, accounting for physical

correlations among them, from the l-D doping profile. Due

to inevitable uncertainties in some of the device parame-

ters, the prediction of device characteristics required

some tuning of a few parameters. The tuning however did not

involve any optimization, and thus the capability of link-

ing device model parameters to structural and process

parameters was maintained.









4.3 Parameter Tuning for the MMSPICE BJT Model


The objective of this work is to demonstrate that the

MMSPICE/QBBJT model parameters can be easily tuned by using

the physical nature of the model, without using intensive

parameter optimization as needed for the Gummel-Poon model

parameters. The tuned model parameters obtained from this

work will also be used for comparing MMSPICE/QBBJT with

SPICE/GP in Section 4.6.
Though most of the MMSPICE BJT model parameters are

physical and can be determined directly from the technol-

ogy, a few cannot be determined accurately due to uncer-
tainties in fundamental and process-dependent parameters

such as mobility and surface recombination velocity. Dis-

crepancies between the (SUMM-based) model-predicted and

measured device characteristics can hence be attributed to

uncertainties in these parameters. These discrepancies can

be easily removed by parameter tuning, by which the model

parameters that predominantly affect the device character-

istics in specific regions and modes of operation are var-

ied to fit the measured data.
Tuning of model parameters in each region, such as

small-, medium-, and high-current regions, and in each mode

of operation, such as dc, ac, and transient, is explained

with underlying physics. The test device used for the

parameter tuning has the effective emitter area of 0.95x3.2

1im2 (drawn: 1.75x4 Pmn2), the peak base doping of 1.4x1018
cm3, the epi thickness of 0.4 im, and the epi doping









density of 2x1016 cm-3. In the following explanations of

parameter tuning, all model parameters are expressed in

boldface type.


4.3.1 dc Parameter Tuning


4.3.1.1 Medium-Current Ranae


To match the medium collector current Ic, the average

minority-carrier diffusivity DNB in the base is increased

from 11.79, extracted from SUMM, to 25.3. DNB is an uncer-

tain parameter because it is an average quantity, and fur-

thermore it is a minority-carrier diffusivity, which SUMM

assumes to equal the majority-carrier diffusivity. Also,

it is possible that some bandgap narrowing occurs in the

highly doped base (peak doping is 1.4x1018 cm-3), which is

not modeled in the released version of MMSPICE. The band-

gap-narrowing effect can be taken into account by increas-

ing DNB, which directly affects the pre-exponential factor

of the expression for Ic as does the bandgap narrowing.

The emitter saturation current density JEO is adjusted

slightly from 1.48x10-8 A/m2, extracted from SUMM, to

1.70x10-8 A/m2 to obtain a good fit for medium base current

IB. The back-injection component of Ig into the emitter is
modeled by JEO, which is determined by doping density and

thickness of the emitter, as well as the properties of the

poly-/mono-silicon interface represented by the effective

surface recombination velocity Sp(eff). JEO should be tuned









for a specific technology due to the dependence of Sp(eff)

on processing technique for the emitter formation. SUMM

requests a value for Sp(eff) to represent a specific tech-

nology.

The equilibrium base-emitter space-charge region

(SCR) width WSEO is reduced from 3.13x10-8 m, extracted
from SUMM, to 2.0x10-8 m to match the P(VBE) characteris-

tic, which shows a mild decrease with increasing VBE in the

medium-VBE range. This is the so-called Late effect. The

slope of the Ic(VBE) curve at medium VBE is slightly non-

ideal due to this effect, which depends on the doping gra-

dient at the base side of the base-emitter SCR. In MMSPICE,

the base-doping profile is modeled as an exponential func-

tion, and WSEO extracted from the exponential function may

result in uncertainty in approximating the actual varia-

tion of the base-side edge of the SCR as a function of VBE.

Therefore, WSEO needs to be tuned to match the model pre-

diction to measured data. In the Gummel-Poon model, the

phenomenon is modeled by using the empirical inverse Early

voltage (VAR) and the forward-current emission coefficient

(NF).


4.3.1.2 High-Current Range


A semi-physical parameter AC, which is larger than AE,

is used in MMSPICE BJT model to account for the lateral

spreading of electrons at high current density in the col-

lector, which diminishes the one-dimensional quasi-satura-




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