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Page i Acknowledgement Page ii Table of Contents Page iii Page iv Page v Key to symbols Page vi Page vii Page viii Page ix Page x Page xi Page xii Page xiii Page xiv Page xv Page xvi Page xvii Page xviii Abstract Page xix Page xx Chapter 1. Introduction Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Chapter 2. Circuit topology and operation Page 7 Page 8 Page 9 Page 10 Page 11 Page 12 Page 13 Page 14 Page 15 Chapter 3. Modified statespaceaveraging Page 16 Page 17 Page 18 Page 19 Page 20 Page 21 Page 22 Page 23 Page 24 Page 25 Page 26 Page 27 Page 28 Page 29 Page 30 Page 31 Page 32 Chapter 4. Power dissipation and thermal analysis Page 33 Page 34 Page 35 Page 36 Page 37 Page 38 Page 39 Page 40 Page 41 Page 42 Page 43 Page 44 Page 45 Page 46 Page 47 Chapter 5. Dynamic analysis and compensation Page 48 Page 49 Page 50 Page 51 Page 52 Page 53 Page 54 Page 55 Page 56 Page 57 Page 58 Page 59 Page 60 Page 61 Page 62 Page 63 Page 64 Page 65 Page 66 Page 67 Page 68 Page 69 Page 70 Page 71 Chapter 6. Designing a switchedcapacitor DCDC converter Page 72 Page 73 Page 74 Page 75 Page 76 Page 77 Page 78 Page 79 Page 80 Page 81 Page 82 Page 83 Page 84 Page 85 Page 86 Page 87 Page 88 Page 89 Page 90 Page 91 Page 92 Chapter 7. Converter performance Page 93 Page 94 Page 95 Page 96 Page 97 Page 98 Page 99 Page 100 Page 101 Page 102 Page 103 Page 104 Page 105 Page 106 Page 107 Chapter 8. Verification of analysis results Page 108 Page 109 Page 110 Page 111 Page 112 Page 113 Page 114 Page 115 Page 116 Page 117 Page 118 Page 119 Page 120 Page 121 Page 122 Page 123 Page 124 Page 125 Page 126 Page 127 Page 128 Page 129 Page 130 Page 131 Page 132 Chapter 9. Summary and conclusions Page 133 Page 134 Page 135 Page 136 Appendix A. Derivation of the output ripple equation Page 137 Page 138 Page 139 Page 140 Page 141 Appendix B. Derivation of the system transfer functions Page 142 Page 143 Page 144 Page 145 Page 146 Page 147 Page 148 Appendix C. Derivation of the standard parameter models Page 149 Page 150 Page 151 Page 152 Page 153 Page 154 Page 155 Page 156 Page 157 Page 158 Appendix D. Design procedure source listing Page 159 Page 160 Page 161 Page 162 Page 163 Page 164 Page 165 Page 166 Page 167 Page 168 Page 169 References Page 170 Page 171 Page 172 Page 173 Page 174 Biographical sketch Page 175 Page 176 Page 177 Page 178 
Full Text 
ANALYSIS AND DESIGN OF A POWER SWITCHEDCAPACITOR DCDC VOLTAGE CONVERTER By WILLIAM SCOTT HARRIS A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 1997 ACKNOWLEDGEMENTS There are many individuals without whose help the work contained in this dissertation would not have been completed, and special thanks are extended to all. Dr. Khai Ngo holds a special place in my heart for taking me in as his student without even knowing me. His kindness and encouragement will not be forgotten. Dr. Robert M. Fox, Dr. Dennis P. Carroll, Dr. J. Kenneth Watson, Dr. Loc VuQuoc, and Dr. Kenneth 0 all graciously agreed to serve on my committee. Dr. Gijs Bosman gave me friendship and guidance during my time in Gainesville. Eddie and Lois Houk of Gainesville provided warm friendship and wonderful hospitality. Joe Taylor, Russ Schambeau, and Bill McBroom from Eglin Air Force Base allowed me to go to graduate school and to complete my dissertation. My wife, Betsy Harris, encouraged me to keep going during the many years it took to complete this dissertation. Words are inadequate to express my love and appreciation for her. My children, Meg, Alex and Abby Harris, showed me that the most important thing in life is not academic achievement, but the legacy I leave behind. Most importantly, I thank God for loving me, and for helping me make it through all of the difficult times in life. TABLE OF CONTENTS page ACKNOW LEDGEM ENTS ............................................................................................... ii KEY TO SYM BOLS ........................................................................................................vi ABSTRACT .................................................................................................................... xix CHAPTERS 1. INTRODUCTION ................................................................................................ 1 2. CIRCUIT TOPOLOGY AND OPERATION ....................................................... 7 2.1. Introduction ................................................................................................... 7 2.2. Switching Operation ..................................................................................... 8 2.3. Current Source Operation ............................................................................ 9 2.4. Switching Loss ............................................................................................ 11 3. MODIFIED STATESPACEAVERAGING ..................................................... 16 3.1. Introduction ................................................................................................ 16 3.2. M odified StateSpaceAveraging .............................................................. 17 3.3. Practical Approxim ations .......................................................................... 26 3.4. SteadyState Solution ................................................................................ 27 4. POWER DISSIPATION AND THERMAL ANALYSIS .................................... 33 4.1. Conduction Losses ...................................................................................... 34 4.2. Switching Losses ....................................................................................... 35 4.2.1. Switching M OSFET Energy Loss .............................................. 37 4.2.2. Current Source MOSFET Energy Loss ....................................... 39 4.2.3. Diode Energy Loss ..................................................................... 40 4.2.4. Switching Power Loss ................................................................. 41 4.3. Total Power Loss ....................................................................................... 43 4.4. Therm al Analysis ..................................................................................... 44 5. DYNAMIC ANALYSIS AND COMPENSATION ........................................... 48 5.1. OpenLoop Response ................................................................................ 49 5.1.1. Current Am plitude Control .......................................................... 49 5.1.2. Duty Cycle Control ................................................................... 51 5.1.3. Average StateSpace LargeSignal Circuit Model ...................... 53 5.1.4. Sm allSignal Circuit M odel ....................................................... 55 5.1.5. Impedances and Admittances ..................................................... 56 5.1.6. Audio Susceptibility Function ..................................................... 59 5.2. Compensation ............................................................................................ 60 5.3. ClosedLoop Response ............................................................................. 64 5.3.1. Voltage Gain ............................................................................. 65 5.3.2. Im pedances ................................................................................ 67 5.3.3. Audio Susceptibility Function ..................................................... 68 5.4. Design of a ClosedLoop Converter .......................................................... 69 6. DESIGNING A SWITCHEDCAPACITOR DCDC CONVERTER ................ 72 6.1. Com ponent Parameter M odels ................................................................. 73 6.1.1. Charging Capacitors ................................................................... 73 6.1.2. M OSFETs .................................................................................. 75 6.1.3. Diodes ....................................................................................... 78 6.2. Practical Considerations ........................................................................... 79 6.2.1. Selecting the Number of Stages .................................................. 79 6.2.2. Selecting the Switching Frequency ............................................. 80 6.2.3. GateDrive Requirements ......................................................... 81 6.3. Design Procedure ....................................................................................... 82 7. CONVERTER PERFORM ANCE ...................................................................... 93 7.1. Perform ance Lim its .................................................................................. 93 7.1.1. M inim um Input Voltage ............................................................ 93 7.1.2. M aximum Output Voltage .......................................................... 94 7.1.2. M aximum Efficiency ................................................................. 94 7.1.3. M aximum Output Power ............................................................ 97 7.2. Perform ance Parameters ........................................................................... 98 7.2.1. Total Capacitance ...................................................................... 98 7.2.2. Total Capacitance Volume ............................................................ 100 7.2.3. Efficiency ...................................................................................... 103 8. VERIFICATION OF ANALYSIS RESULTS ...................................................... 108 8.1. Verification of the DC Analysis ................................................................... 108 8.2. Verification of the Switching Loss Analysis ................................................ 111 8.3. Verification of the Dynamic Analysis .......................................................... 115 8.3.1. Converter Design .......................................................................... 115 8.3.2. Dynamic Measurement Setup Configuration ................................ 119 8.3.3. OpenLoop Response .................................................................... 121 8.3.4. ClosedLoop Response ................................................................. 124 9. SUMMARY AND CONCLUSIONS .................................................................... 133 APPENDIX A DERIVATION OF THE OUTPUT RIPPLE EQUATION .................. 137 APPENDIX B DERIVATION OF THE SYSTEM TRANSFER FUNCTIONS .......... 142 APPENDIX C DERIVATION OF THE STANDARD PARAMETER MODELS ...... 149 C 1. C apacitors .................................................................................................... 149 C .2. M O SFETs ................................................................................................... 151 C.2.1. Switching MOSFETs ................................................................... 151 C.2.2. Current Source MOSFET ............................................................. 154 C .3. D iodes ......................................................................................................... 156 APPENDIX D DESIGN PROCEDURE SOURCE LISTING ...................................... 159 REFERE N C ES ............................................................................................................... 170 BIOGRAPHICAL SKETCH .......................................................................................... 175 KEY TO SYMBOLS The unit system in this paper is SI (MKS). Unless otherwise specified, the convention used in this dissertation is as follows: x* Instantaneous value of the variable x x Lowfrequency component of x* iSmallsignal perturbation of x* X Average value of x The nomenclature used is as follows: a A constant a1 A firstorder coefficient matrix for the Taylor series expansion of the A matrix around the steadystate value of the duty cycle all A term in the a, matrix a12 A term in the a, matrix a2 A secondorder coefficient matrix for the Taylor series expansion of the A matrix around the steadystate value of the duty cycle a21 A term in the aI matrix a22 A term in the a, matrix A Averaged statespace matrix for the switching interval A0 The gain relating the output voltage to the reference voltage at dc A1 Statespace matrix for the charge interval A11 A term of the averaged statespace matrix A A12 A term of the averaged statespace matrix A A2 Statespace matrix for the discharge interval A21 A term of the averaged statespace matrix A A22 A term of the averaged statespace matrix A ACL The gain relating the output voltage to the reference voltage AaMW The openloop gain of the operational amplifier used in the compensation circuit Ad The drain area of a MOSFET Adnorm The drain area of a MOSFET normalized by the drain current AO Crosssectional area of a piece of material used for heat transfer b, A firstorder coefficient matrix for the Taylor series expansion of the B matrix around the steadystate value of the duty cycle bl, 1 A term in the b, matrix bl, A term in the b, matrix b2 A secondorder coefficient matrix for the Taylor series expansion of the B matrix around the steadystate value of the duty cycle b21 A term in the b, matrix b22 A term in the b, matrix B Averaged statespace matrix for the switching interval B1 Statespace matrix for the charge interval BI1 A term of the averaged statespace matrix B B12 A term of the averaged statespace matrix B B2 Statespace matrix for the discharge interval B21 A term of the averaged statespace matrix B B22 A term of the averaged statespace matrix B C Value of charging capacitors C2, C3.... Cn C1 Output capacitor Cdg The draingate capacitance of a MOSFET Cdgo The zerobias draingate capacitance of a MOSFET Cds The drainsource capacitance of a MOSFET Cfl A capacitor used in the compensation network Cf2 A capacitor used in the compensation network Cgs The gatesource capacitance of a MOSFET Cgso The zerobias gatesource capacitance of a MOSFET Ciss MOSFET input capacitance, as specified on the manufacturer's data sheets Cj Charging capacitors C2, C3,... Cn Cmin Minimum allowable value of C for a given design CO The gate oxide capacitance of a MOSFET COSS MOSFET output capacitance, as specified on the manufacturer's data sheets Cp Parasitic capacitance of a switching device Cross MOSFET reverse transfer capacitance, as specified on the manufacturer's data sheets CT The total capacitance in a converter, C, + C2 +...Cn CTmin The minimum total capacitance needed by a particular design Cx The sum of the gatesource and the drainsource capacitances of a MOSFET Cy The sum of the draingate and the drainsource capacitances of a MOSFET d Charging duty cycle d' 1d DiA Diodes that conduct during the charge interval DjB Diodes that conduct during the discharge interval E Energy Ecgd Energy lost by the draingate capacitor of Mc during a chargedischarge cycle Ecsd Energy lost by the drainsource capacitor of Mc during a chargedischarge cycle Ecsg Energy lost by the gatesource capacitor of MC during a chargedischarge cycle Ejmdg Energy lost by the draingate capacitor of Mj during a chargedischarge cycle Ejmds Energy lost by the drainsource capacitor of Mj during a chargedischarge cycle Ejmgs Energy lost by the gatesource capacitor of Mj during a chargedischarge cycle EjA Energy lost by the capacitance of DjA during a chargedischarge cycle EjB Energy lost by the capacitance of DjB during a chargedischarge cycle Es Total energy switching loss during a switching period f Frequency fA Switching frequency fsmx Maximum allowable switching frequency g An arbitrary function gm Transconductance of Mc Gc The openloop input current to output voltage transfer function Gd The openloop duty cycle to output voltage transfer function Ggate The transfer function from the input of the gatedrive circuit to the drain current of MC Hc The compensation network used to adjust the phase margin of the closedloop system Hgate The gain of the gatedrive circuit of Mc Hpwm The gain of the pulsewidth modulator in the feedback network i Integer index, i = 1, 2.... n iel The current through C icj The current through C2Cn ics The current source value in the statespace averaged equivalent circuit id Drain current of a MOSFET idiode The current through a diode tMc The current through Mc iMj The current through M2Mn to The output current through RL is Source current of a MOSFET I Identity matrix Idma Maximum diode current /gd The current capability of the gatedrive circuit of M2Mn loss Average charging current loss during the charge interval iMcmax The current rating of MC Imax The minimum of IMjmax and ldmax Ion The current through MC during the charge interval /rating The current rating of Mj j Integer index, j = 2, 3.... n k The value of C1 is kC kc A constant kT A constant K The ratio of o)c to Oz or the ratio of (op to 0 Km The conductance parameter of a MOSFET L The channel length of a MOSFET m An integer value M The voltage stepdown ratio, Vin / Vo MC MOSFET acting as a currentsource Mj Switching MOSFETs M2, M3.... Mn n Number of stages nmnax Maximum number of stages that can be used for a given converter design nmin Minimum number of stages that can be used for a given converter design p A constant P A transformation matrix relating the state variables from the beginning to the end of the charge interval PC Average conduction power dissipated by a component PcA Average conduction power dissipated by each charge diode D2ADnA PcB Average conduction power dissipated by each discharge diode D2BDnB Pccl Average conduction power dissipated by C, PcC Average conduction power dissipated by each C2Cn Pcm Average conduction power dissipated by each M2Mn Pcrm Average conduction power dissipated by MC Pin Average input power Pjsm Average switching power loss in each M2Mn PjtA Average total power loss in each charge diode D2ADnA PjtB Average total power loss in each discharge diode D2BDnB Pjtm Average total power loss in each M2Mn PO Average output power Pomax The maximum output power available from a converter PRi Average power dissipated by Ri, a resistor in the compensation circuit Ps Total average switching power loss Psm Average switching power loss of MC Pt Average total power dissipated by a component Ptc Average total power dissipated by each C2Cn Ptc1 Average total power dissipated by Mc Ptmax The maximum power a device can dissipate at a given temperature Ptm= Average total power dissipated by Mc q Integer index, q = 0, 1.... no Q The rate at which heat energy is transferred by conduction from a body at temperature T, to another body at temperature T2 Qg The charge needed to bring the gate of a MOSFET from zero to some voltage req The ac resistance value in the averaged statespace equivalent circuit R, Equivalent series resistance of C1 RD The drift resistance of the epidrain bulk region of a MOSFET RL Load resistance Rb One of the input resistors used in the compensation circuit Req The dc resistance value in the averaged statespace equivalent circuit Resr Equivalent series resistance of C2Cn Rf The feedback resistor used in the compensation circuit Ri One of the input resistors used in the compensation network Ron "On" resistance of M Ronmx Maximum allowable "on" resistance of M Ronmin Minimum allowable "on" resistance of Mi Ronp "On" resistance of the current source in the statespace averaged equivalent circuit Re Thermal resistance of a piece of material Rocs Thermal resistance of the case of a MOSFET or diode to a heat sink R~jC Thermal resistance of the junction of a MOSFET or diode to its case Rosa Thermal resistance of a heat sink to air s The Laplace variable S Capacitance per unit volume Sm The safety margin for Vblock and Vwk t Time tmax Time where peak output ripple occurs, referenced from the beginning of the discharge interval ts The time it takes for M2Mn to switch states from on to off or vice versa T Switching period, inverse of switching frequency T, A constant temperature T2 A constant temperature Ta Ambient temperature Ti The junction temperature of a MOSFET or diode Tjnm The maximum junction temperature rating of a MOSFET or diode TCL Loopgain u Input vector v Voltage VC1 Voltage of C1 vcj Voltage of C2, C3,...Cn VCjmx Maximum allowable voltage of C2, C3,... Cn for a given design vc The output voltage of the compensation circuit Hc vd Drain voltage of a MOSFET Vdg Draingate voltage of a MOSFET Vdrain The drain voltage of MC Vds Drainsource voltage of a MOSFET VF Diode "on" voltage Vg Gate voltage of a MOSFET Vgs Gatesource voltage of a MOSFET Vin Input voltage Vinv The voltage at the inverting terminal of the operational amplifier used in the compensation network Vo Output voltage Vref The reference voltage used to set the value of output voltage in the closedloop system vs Source voltage of a MOSFET Vsat The limiting velocity for electrons in silicon VT MOSFET threshold voltage Vblock MOSFET or diode blocking voltage VCT Volume of the total capacitance CT Vdmax The maximum allowable drain voltage on MC to keep it in saturation Vdsat Minimum voltage across a MOSFET to keep it in saturation Vgate The gate voltage of Mc needed for the drain current to equal Ion Vgsp The voltage where the VgsQg curve of a MOSFET plateaus Vinmin The minimum allowable input voltage to keep MC in saturation Vj B The cathode voltage of DjB at the end of the charge interval VjM The drain voltage of Mj at the end of the charge interval Viin The gatesource voltage of Mi necessary to assure operation in the linear region during the discharge interval Vomax The maximum allowable output voltage Vwk Working voltage rating of a capacitor W Channel width of a MOSFET x Statespace vector over the switching period Xm Sampled data points of x* at t = mT Xm+1 Sample data points of x* at t = (m+ 1)T Xm+d Sample data points of x* at t = (m+d)T Y1 A constant Y2 A constant Ygate The gate voltage to drain current transfer function of a pchannel MOSFET Zf The feedback impedance of the compensation network 4i The openloop, smallsignal input impedance of the converter Zic The closedloop, smallsignal input impedance of the converter Zo The openloop, smallsignal output impedance of the converter Zoc The closedloop, smallsignal output impedance of the converter ZPs Impedance of the converter power stage equivalent circuit cc Ratio of C1 to C1+C2+...Cn 10 The MOSFET transconductance parameter 5 The thickness of a piece of material used to conduct heat AVc The change in voltage of a charging capacitor during the charge interval AVo Output voltage ripple ASAo The percent maximum error in the gain equation relating vo and Vref Ar9 The difference between the maximum possible efficiency and the minimum acceptable efficiency &A The error term in the gain equation relating vo and Vref EAO The error term in the gain equation relating vo and Vref at dc m The phase margin of the loopgain TCL 4A constant 71 Converter efficiency Tlrlax The maximum possible efficiency available from a given converter Y A constant F A constant F1 A constant F2 A constant ?, I Eigenvalue of matrix A1 X2a Eigenvalue of matrix A2 X2b Eigenvalue of matrix A2 Ax A constant 9p The hole mobility in the inversion layer of a MOSFET Po Thermal resistivity of a material a A constant "t A time constant T1 A time constant, the inverse of X, 12a A time constant, the inverse of X2a T2b A time constant, the inverse of X2b 0 A constant (OC The zero in the openloop input current to output voltage transfer function 0Co The cutoff frequency where the magnitude of TCL equals one Od The zero in the openloop duty cycle to output voltage transfer function O)p The pole frequency of the compensation network 0)oz The zero frequency of the compensation network 'F Ratio of the average charging current through C1Cn to Ion during the charge interval xviii Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy ANALYSIS AND DESIGN OF A POWER SWITCHED CAPACITOR DCDC VOLTAGE CONVERTER By William Scott Harris May 1997 Chairman: Professor Khai D. T. Ngo Major Department: Electrical and Computer Engineering Switchedmode voltage converter circuits that utilize capacitors as the energy transfer element are called switchedcapacitor voltage converters. Switchedcapacitor voltage converters are attractive because they use no magnetic components and may one day be amenable to monolithic integration. Previous attempts at analyzing switchedcapacitor voltage converters have relied on a technique called StateSpaceAveraging. While this technique is acceptable for converters having natural frequencies much less than the switching frequency (linear ripple), its accuracy suffers when this assumption is not true. This dissertation focuses on a specific switchedcapacitor topology that has nonlinear ripple, and uses a new technique to aid in the analysis and design. This new technique, called Modified StateSpace Averaging, is generally suitable for analysis of voltage converters with nonlinear ripple. In this dissertation, Modified StateSpaceAveraging is used along with practical approximations to derive the steadystate operating conditions of the converter. The effect of switching losses on the steadystate output voltage is also accounted for, and a method of calculating these losses is given. Modified StateSpaceAveraging is also used to derive the openloop dynamic response of the converter, and a method of feedback compensation is presented to control the closedloop frequency response. The dynamic analysis also leads to the derivation of continuoustime equivalent circuits that model the transient and frequency responses of the converter, allowing much shorter simulation times. An optimized design procedure is presented that allows a converter to be designed for minimum volume for given values of input voltage, output voltage, efficiency, and output ripple. The performance limits of the converter, such as maximum output power, maximum efficiency, and minimum capacitance are presented in graphical form. Experimental circuits are used to show that a switchedcapacitor dcdc converter can process up to several tens of watts of output power at an efficiency exceeding 80%. Experimental and simulation verification of the steadystate and dynamic analysis is given. CHAPTER 1 INTRODUCTION Power supplies are an integral part of today's electronic systems. Their function is to provide a regulated dc voltage source to the various electronic components in the system. Initially, linear power supplies were used, but they suffered from low efficiency (30 to 60%) and required large 60 Hz transformers to step down the input line voltage. Large capacitors were necessary to filter the dc output voltage, and a transistor operated in the active region (low efficiency) was used to provide output regulation [34]. Today, high efficiency switchedmode supplies use magnetic energy transfer and solidstate switches to convert one dc voltage to another. Although much progress has been made in reducing the size of the magnetic components used in such supplies [1][18][35][37][54], these components remain a barrier to monolithic integration. On the other hand, it has been shown that capacitors have fewer physical barriers to monolithic integration than do magnetic components [8][24][26][451. As capacitor technology develops towards full integration, it is possible that they could be used in an integrated switchedmode supply as the energy transfer element. Switchedmode dcdc converter circuits that utilize capacitors as the energy transfer element are called Switched Capacitor DcDc Converters (SCDDCs). Commercially available SCDDCs include the ICL7660 [12] and the LT1054 [25]. However, these products offer a limited range of voltage conversion and operate at very low power levels. This dissertation focuses on a specific stepdown SCDDC topology, with a four stage converter shown in its simplified form in Fig. 11. As will be discussed in Chapter 2, the capacitors C2C4 are charged in series and discharged in parallel, while C, acts as a filter for the load resistor RL. During the charge interval, the switches labeled Sc are closed and the switches labeled Sd are open. During the discharge interval, the switches labeled Sd are closed and the switches labeled Sc are open. Previous attempts at analyzing SCDDCs [6][7][28][29][49][521 have relied on StateSpaceAveraging (SSA) [33], and have been limited to an output power of a few watts or less. It has been shown [52] that the efficiency of a SCDDC can exceed 80% by proper choice of the capacitive stepdown ratio. Thus, the power rating of a SCDDC does not have to be restricted to a "low" power rating of a few watts, and a "medium" power rating of several tens of watts is conceivable. In the practical case, however, the analysis and design results [52] are not directly applicable since, as shown in Fig. 12, the assumption of linear ripple [33] does not hold. Other analysis techniques derived from SSA can be found [9][53], but these techniques also rely on the assumption that the natural frequencies of the system are much less than the switching frequency. Therefore, general analysis and design methods for the SCDDC need to be revisited. This dissertation presents a new technique for analyzing a switchedcapacitor dcdc converter. This technique, called Modified StateSpaceAveraging (MSSA) [17], is generally suitable for analysis of converters with nonlinear ripple. Like SSA, the results from MSSA are used to derive the steadystate operation and the dynamic response of the C4 F SdH Sc: C3 Sd Sd I Iii + Sa C, RL Figure 11. Fourstage switchedcapacitor dcdc converter. converter. Results from the steadystate analysis lead to expressions for output voltage, output ripple, charging capacitor voltage, and efficiency. Results from the dynamic analysis can be used to design a method for optimizing the response of the closedloop system and to derive a nonswitching equivalent circuit that models the transient and frequency responses of the converter. The remainder of the dissertation is as follows. Chapter 2 presents the circuit topology and discusses the switching operation of a SCDDC. Two methods of control, input current and duty ratio, are given. Equivalent circuits for both the charge and discharge intervals are presented, along with justification for the inclusion of the switching losses in the statespace equations. 12.04 12.02 V0 12 o 11.98 11.96 11 .94 rtmax 11.924 .2 2.2 2. 2.6 2.8 3 seconds X 10 Figure 12. Output voltage ripple for a fourstage, 48 W SCDDC withfs = 100 KHz, PSPICE simulation. Chapter 3 introduces the analysis problem by giving the background for State SpaceAveraging, and provides the justification for Modified StateSpaceAveraging. A numerical example is given to give a comparision between the two. Practical approximations are made, allowing the analysis results to be simplified into a usable format. These approximations allow the derivation of the steadystate operating conditions, and calculation of the values of steadystate output voltage, output ripple, charging capacitor voltage, and efficiency. Chapter 4 analyzes the power dissipation (conduction and switching) in the SCDDC and uses basic thermal analysis to determine if a device is operating within its maximum ratings. Chapter 5 uses the averaged statespace equation derived from MSSA to obtain the openloop transfer functions and impedances, along with the largesignal and smallsignal continuoustime equivalent circuits for the converter [33]. These equivalent circuits provide a reduction in the time needed to simulate a converter circuit. Because its switching operation, PSPICE simulation [32] of a SCDDC can take several minutes to several hours, depending on the number of stages and the speed of the computer. This chapter also looks at the effect of the feedback loop on the transfer functions, impedances, and output voltage of the converter. Analysis and modification of the closedloop gain allows the designer to set the frequency response of the system. An example is given to show how to implement the feedback loop in a closedloop converter. Chapter 6 presents a design procedure based on analysis results derived from Modified StateSpaceAveraging. The procedure gives the smallest total capacitance (and size) for the set of input parameters of output voltage, output power, output voltage ripple and efficiency. Standard parameter models of currently available MOSFETs, diodes, and capacitors used in the procedure are given. These models calculate the device parameters that would be found in a datasheet, all as functions of input voltage and output power. Chapter 7 presents the performance limits of the SCDDC in graphical form using the component models given in Chapter 6. In this chapter, the minimum possible input voltage, the maximum possible efficiency, and the maximum possible output power are all plotted as a functions of the input design parameters. The design procedure in Chapter 6 is then used to obtain curves for the minimum total capacitance used and the total capacitance volume of the SCDDC as a function of the input design parameters. Chapter 8 presents design examples, and compares analytical, simulation and experimental results. In this chapter, the analysis results of the preceding chapters are verified using simulation and experimental data. Design examples are presented for three mediumpower converters, and experimental circuits similar to the design examples are fabricated to show that highefficiency, mediumpower converters are feasible. Experimental data is shown to closely agree with analysis and simulation results. Simulation data showing the effect of switching losses on the output voltage at switching frequencies of 100 KHz and 1 MHz is given. Good agreement between calculated and simulated values is shown, excepted as noted. Chapter 9 summarizes the main contributions and accomplishments of this dissertation, and suggests topics for further research. CHAPTER 2 CIRCUIT TOPOLOGY AND OPERATION This chapter introduces the topology for the switchedcapacitor stepdown dcdc converter, and discusses switching operation. Equivalent circuits are given to simplify the analysis presented in the next chapter. Section 2.1 introduces the function of the circuit components in a switchedcapacitor stepdown dcdc converter. Section 2.2 discusses the switching operation of the converter, and presents equivalent circuits for the charge and discharge intervals. Section 2.3 discusses the necessary conditions for the current source to remain in the saturation region of operation. Section 2.4 justifies the inclusion of the switching losses in the statespace equations. 2.1. Introduction As shown in Figs. 11 and 21, a SCDDC generally consists of n stages. The first stage consists of capacitor C1, which acts as a filter for the load resistor RL. Each of the other stages consists of a capacitor Ci, diodes DjAand DjB, and a MOSFET Mj. MOSFET Mc operates as a current source that controls the output voltage. It is shown as a pchannel device because they can be driven with simpler gatedrive circuitry, as compared to an nchannel device. The other MOSFETs and the diodes are used as switches. As will be shown later in Chapter 3, the output voltage can also be controlled by the duty ratio of the input current. 2.2. Switching Operation Each switching period T consists of a charge interval dT (mT < t < (m+d)7), and a discharge interval d'T ((m+d)T < t < (m+ 1)7). At the beginning of the charge interval, M2M4 and D2BD4B are off, and MC and D2AD4A are turned on, charging the capacitors C1C4. The charge circuit is shown in Fig. 22(a). During the discharge interval MC and D2AD4A are off, and M2M4 and D2BD4B are turned on, discharging C2C4 into C1 and RL. The discharge circuit is shown in Fig. 22(b). Figures 12 and 23 show the typical waveforms of an SCDDC switched at 100 KHz and 0.25 duty ratio. It can be seen from Figs. 22(a), 23(a), and 23(b) that during the charge interval, the current Ion flows through MC, C1C4, and D2AD4A and establishes a voltage at the drain of Mc which is the sum of the voltages across C1C4 and D2AD4A. During the discharge interval (Fig. 22(b)), C2C4 discharges into C1 and RL through M2M4. Note that in the discharge interval the current through M4 (Fig. 23(c)) is exponential, not linear. The voltage ripple (Fig. 12) is also obviously nonlinear. These nonlinear waveforms necessitate the use of Modified StateSpaceAveraging discussed in the next chapter. The output voltage ripple shown in Fig. 12 is for d = l/n, which corresponds to a zero slope for vo during the charge interval. When d < l/n, the slope of vo during the charge interval is positive because Ion > vO/RL. When d > l/n, the slope of v. is negative during the charge interval because Ion < vo/RL. + IT RL V Figure 21. A fourstage stepdown converter. 2.3. Current Source Operation During the charge interval, MC must remain in the saturation region; which means that the voltage across it must be greater than or equal to Vdsat, the saturation voltage. This gives rise to the condition Vin>Vdsat+VClI[(m+d)T]+(nI)(VF+IonResr +VCj[(m+d)T) (21) where the equivalentseriesresistance (ESR) of C, has been neglected. The relationship between drain current and gatesource voltage for a pchannel power MOSFET is given by id = Km(Vgs+ VT) (22) where the threshold voltage VT is a negative number. For most applications the power MOSFET will be operating in a region where there is a linear relationship between the drain current and the gatesource voltage, and the value for Km is given by [2] Km = CoWvsat (23) where vsat ; 8 x I06 cm / second [10]. If the MOSFET is operating in the region where there is a quadratic relationship between the drain current and the gatesource voltage, the value of Km is given by [15] Km = WjCop(Vgs + VT) = 0(Vgs + VT) (24) The manufacturer's data sheets usually contain a drain current vs. gatesource voltage plot that will allow a designer to determine which equation is valid for a specific application. Therefore, for a power MOSFET operating in the linear region of drain current vs. gatesource voltage ,on 'on (25) Vdsat Km gm where the transconductance gm of MC can be found in the manufacturer's data sheets. For a power MOSFET operating in the nonlinear region of drain current vs. gatesource voltage Vdsat = 2Ion (26) 11O11 I II V. /o i I (nl)Re (Ron + Res)I(n1) (nI)VF + c(n1) (n1) vcj R, + + ~ +n1) RL V, R, + RLv.VF kC C kC VC R V (a) (b) Figure 22. Equivalent circuits for the charge (a) and discharge (b) intervals. It appears from (21) that to keep Mc in saturation, the righthand side of (21) should be made as small as possible, e.g., by making n or Vcj[(m+d)TJ small. It will be shown later, however, that n is directly proportional to the efficiency and Vcj[(m+d)7T inversely proportional to the size of the semiconductor devices and the capacitors. Thus, it is desirable to keep the righthand side of (21) as close to Vin as possible. 2.4. Switching Loss In a real circuit the MOSFETs and diodes have parasitic capacitances that must be charged and discharged during switching. The charging and discharging of these capacitors results in switching losses [42][431, reducing the output power and thus the output voltage. It will be shown later that this is equivalent to having a net reduction of charging 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 seconds x 1 0,6 2.2 2 .4 216 2.8 3 seconds x 10 seconds x 10 Figure 23. Current through Mc (a); the voltage at the drain of Mc (b); and current through M4 (c); foran SCDDC with Po = 48 W, Vi, = 55 V, Vo = 12 V, n = 4,f, = 100 KHz, I,, = 4 A, RL = 3 , C = 9.6 pF, Resr = 3 mfn, k = 9, Ron( 25*C ) = 0.3 f), VF = 0.3 V, PSPICE simulation. current through CICn. In Fig. 2(a), this reduction in current is shown as loss, which represents the average charging current loss over the charge interval. The average charging current during the charge interval is then given by Ion /ls =1S Ton (27) where TP will be determined later from the switching power loss Ps and the output power Po, or T+, (28) Figure 24 shows the charging currents through MC and C2C4 at the beginning of the charge interval for a fourstage converter. The successive reduction in current is due to the switching currents flowing into the parasitic capacitances of the MOSFETs and diodes, as shown in Fig. 2.5. 14 0.1 0.08 ion 0.06 C4 0.04 E 0 Op  0.02 0.04' 2 2.01 2.02 2.03 2.04 2.05 2.06 seconds x 106 Figure 24. Charging currents through Mc and C2C4 at the beginning of the charge interval for an SCDDC with P =1 W, Vi =55 V, V, = 12 V, n = 4, I0 = 83 mA, RL = 144 0, C= 80 nF, Resr 3 rmQ, k = 60, Ron = 0.3 fl, VF = 0.3 V, PSPICE simulation. 0.06 0.05 0.04 0.03 0.02 0.01 0 0.01  2 2 2.01 2.02 2.03 seconds 2.04 2.05 2.06 x 10s 2.04 2.05 2.06 5 x10 Figure 25. Switching currents through the drain of M4 (a) and through D4B (b) at the beginning of the charge interval for the circuit of Fig. 24, PSPICE simulation. 2.01 2.02 2.03 seconds CHAPTER 3 MODIFIED STATESPACEAVERAGING This chapter presents the derivation of Modified StateSpaceAveraging (MSSA), which is generally suited for the analysis of converters with nonlinear ripple. Section 3.1 introduces the analysis problem and discusses StateSpaceAveraging, a previous method of analysis. Section 3.2 derives the statespace equations and gives justification for the use of Modified StateSpaceAveraging. The averaged statespace equation over the switching period is derived from averaging the statespace equations of the charge and discharge intervals. Section 3.3 justifies the use of practical approximations, and simplifies the averaged statespace equation to a usable form. Section 3.4 uses the averaged statespace equation to analyze the SCDDC during steadystate operation. Expressions are given for the steadystate output voltage, output voltage ripple, and efficiency. 3.1. Introduction In any switching power supply with a dc output voltage the instantaneous output voltage will vary with the switching frequency, a term normally called the output ripple. A designer is interested in being able to model the average value of the output voltage, which normally changes at a much lower frequency than the switching frequency. Figure 31 illustrates this problem by showing the output voltage for the circuit of Fig. 21 at startup. Previous work [33][52] has relied on StateSpaceAveraging to model this low frequency, average output voltage. StateSpaceAveraging is a technique which is based on the assumption that the natural frequencies of the circuit are much less than the switching frequency, which means that the instantaneous output voltage is linear over a switching interval (linear ripple). Mathematically, this means that the exponential terms in the solution for the instantaneous output voltage can be approximated as t e t1 t T (31) However, it will be shown that when the circuit of Fig. 21 is designed using typical, commercially available components that (31) is not always valid. Therefore, a new technique had to be developed to account for the case where (31) is not true. This new technique, called Modified StateSpaceAveraging, can generally be used for converters where the output ripple is nonlinear. 3.2. Modified StateSpaceAveraging This section presents the derivation of Modified StateSpaceAveraging. Modified StateSpaceAveraging seeks to model the slowlyvarying "envelope" constructed from the regularly sampled points xm derived from the instantaneous state vector x*(t). The frequent choices for xm are x*(mT), the value of x*(t) at the beginning of each switching period [9], and are related to each other by transformations. Since the ripple in an SCDDC is generally nonlinear, it is convenient to let the MSSA state variable be 14 Vo 12 10 8 0 > 6 4 2 01 2 3 4 5 seconds X 104 Figure 31. Output voltage at startup for the circuit of Fig. 23, PSPICE simulation. xm = x* (mT) (32) where *= (33) VC I It is assumed that the voltages of C2, C3,...Cn are equal, thus allowing the simplification of an nstate system down to a 2state system [52]. Modified StateSpaceAveraging starts with the statespace equations of the equivalent circuits shown in Figs. 22(a) and 22(b). It is assumed that the circuit switches states in a time much shorter than the switching period, or tso T For the charge interval shown in Fig. 22(a): =Aix*+Blu* where A= kCRL 0 BI= kC B*=[k ] U*=ic] (34) (35) (36) (37) (38) For a constant input U where (39) the solution to (35) is [22] S = nFJ ei(t T) (m7)+X ( (t ) (on Vc (rT) 11 e 1)kC Vcj*(t) = VCj(mT) + TI(t mT) 1 1 1 kCRL For the discharge interval shown in Fig 22(b): I* = A2x* + B2u* (311) (312) (313) (n 1) kC((Ron + Resr) 1 RL) I C(Ron + Resr) B2 = [ kC(Ron C(Ron' (n 1) kC(Ron + Res) 1 C(Ron + Resr) For a constant input U, the solution of (313) is where where (314) (315) vcl*(t) = (310) A2t(mn+d)T +A1(eA2[t(m +d)T] I)B2U (6 x* (t) = e Xm+d +A2 (e (316) where the exponential term involving A2 has two natural time constants (secondorder system) which will be designated as T2a and T2b. Using (310), (311), and (316), the discrete derivative of the state can be approximated by the Euler approximation [20][22] = ~ Xm +1 Xm (7 tm = .t(mT) T (317) From (310) and (311), the boundary condition at t = (m+d)T is dT dT v~[m dT Vlm~ kCR I k')L vC,[(m+d)TJ = vcl(ml)e + PIonRL I e (318) Vcj[(m+d)T] = vCj(mT)+ C (319) C From (316), the boundary condition at t = (m+ l)T is A2d'T m+A21 (eA2d'T Xm 1= A2e Xm +A (e )B2U (320) Use of (318), (319), and (320) in (317) allows the expression Of xm+i in terms of xm. Up to this point the procedure deriving Modified StateSpaceAveraging is the same as that for StateSpaceAveraging. In StateSpaceAveraging the exponential terms in (318) and (320) are approximated as dT kCRL I dT e 1 (321) kCRL A2d' T e A TI+A2d'T (322) The result is that (317) can be cast in the following continuous statespace form: = Ax+BU (323) where A = dA1 + d'A2 (324) B = dB1 + d'B2 (325) However, in some cases (322) is not valid, and thus the need for Modified StateSpaceAveraging. A "low" power converter has '2b << T and T2a >> T. For these conditions, the exponential functions in (320) can be approximated as d'T e 12b ;0 (326) d' T e2a d'T (327) e .1  37 "t2a As the power increases to a "medium" level, T2b can become very close to T, because C must also increase. The condition that 't2a >> T is still valid, and (327) still holds. The exponential function in (326) can no longer be approximated by zero, nor the first two or three terms in the series as in other forms of StateSpaceAveraging [9][33]. Therefore, in Modified StateSpaceAveraging, the exponential term containing T2b is carried along as a constant I, where I is defined as d' T "2b ei = e (328) Since T1 >> T, the exponential term in (318) can be approximated as dT e dT (329) kCRL This allows (310) and (311) to be rewritten in matrix form as Xm+d = (I+dTAI)Xm+dTB1U (330) Xm+d =NX m+PU where d 0 P kC dT 0 Thus, with Modified StateSpaceAveraging (317) can be cast in the following continuous statespace form: .x: = Ax+BU (333) (332) where A and B are functions of I, and are given by A OyO(n )C(RL + Ron+Resr)1 yakCRL 0 diY[ (n 1 )C(RL+ Rn+ Resr+ 1 )CR Bd= +T n+(n 1)CRL dT (0 ykC(RL + RI)+ yCRL) where y(n I)CRL 1 ykC(RL + RI)FJ yF(n 1)CRL T 1 r(O kC(RL + (1 d)T T2a 8 = t2ae It2b (334) (335) (336) (331) N: o (1 d)T yt2a y'=e (337) 1 F= t2a "t2b 't2a = C[RL(n I +k) +Ron +Resr+kR1] "t2b = (338) (339) (340) kC[RI(Ron + Resr) + RL(Ron + Resr) + (n I)RIRLI [RL(n I + k) + Ron + Resr + kR1 ] Table 31 shows the analysis results for the circuit of Fig. 23 for both SSA and MSSA. Notice that the output ripple is much greater using SSA as compared to MSSA. Because of this overestimation of the output ripple, the design procedure presented in Chapter 6 will calculate more total capacitance than is actually needed for a specific design. Table 31: A comparision of SSA and MSSA for the circuit of Fig. 23, PSPICE simulation. Parameter SSA MSSA PSPICE Vcl(mT) 12.01 V 12.01 V 12.02 V Vcj(mT) 12.71 V 12.45 V 12.38 AVo 144 mV 95.7 mV 93.4 mV 3.3. Practical Approximations Because of the availability of MOSFETs with Ron less than 0.1 ohm [36], and multilayer ceramic capacitors with Resr ranging from a few milliohms to a few tenths of a milliohm [4] [40], practical constraints were invoked to simplify the exact analytical results. *RL >> (Ron+Resr) >> R *For low ripple, C1 >> (C2+C3+...Cn) As stated previously, the nonlinear ripple is due to an exponential current spike sent to the output during the discharge interval, meaning that one of the eigenvalues of A2 is on the order of the switching frequency. Under the stated assumptions, these eigenvalues are given by 1 (341) T2a (k + n 1)RLC I1 zt 1 ( 2 2b = (Ron + Resr)C (342) where k X k (343) The state matrices of (334)(335) can also be rewritten as A[All A12 [T +(1a)(1c)G1 (1p)(1L)]1 (344) IA21 A22 C 1t t 22] [ (I~)c lp) B 1 12= FckT (345) [B21 B22 d'J4p (3.45 C T 3.4. SteadyState Solution The steadystate capacitor voltages at the beginning of the charge interval can be found by setting the derivative in (333) equal to zero, which results in X = A1BU (346) Using (344)(345), the steadystate capacitor voltages can be given as VC I (mT) ndTlonRL (347) Vcj(mT) .VcI(mT) + VF + pJdTIon(Ron + Resr + (348) e sr fC(I (3 I) In the limit as C goes to infinity, the results in (347) and (348) can be shown to reduce to the statespace results [52]. A designer usually does not have much control over the VcI(mT) and VF terms in (348) because, as shown later, VCI (mT) _ Vo and VF is the ondrop of the diodes. Therefore, if Vcj[(m+d)T] is to be kept small as dictated by (21) to keep MC in saturation, the capacitive reactance llfsC and the parasitic resistances (Ron+Resr) need to be made small. In particular, since Ion could be several amperes at medium power levels (e.g., 50 W), (Ron+Resr) needs to be on the order of 1 0 or less. Consequently, r2b defined in (342) is comparable to T, making the output waveform (Fig. 12) nonlinear and necessitating Modified StateSpaceAveraging. One may argue that (Ron+Resr) should be made as small as practically allowed so that the same Vcj[(m+d)TJ can be achieved with a small value of C. However, there are several problems with this argument. First, practical capacitors are made such that a lower Resr corresponds to a larger C. Secondly, a MOSFET with too small an Ron would be difficult to drive because of the large gate capacitance. Thirdly, if (Ron+Resr) is so small that t2b << T, C2Cn would discharge into C1 in the form of exponential current spikes with high peak value, causing electromagnetic interference problems. Thus, it is recommended that if possible, Ron and C be selected such that 0.25d'T< "t2b < d'T (349) From (331), the voltage of Cl at the beginning of the discharge interval is given by dTW I n . VcI[(m+d)T] = aVc l(mT) + kC %VcI(m7)(+ T (350) Under the assumption that t1 >> T, (350) reduces to Vc, [(m + d)T] VcI(mT) (351) The voltage of C at the beginning of the discharge interval is where Vcj[(m+d)T] = Vcj(m7T)+AVC dTlon AVc= C (352) (353) Assuming that C1 can be chosen so that R, is small enough to be neglected, the output voltage can be approximated as Vo* VCI* (354) This gives the steadystate average output voltage as Vo VCi (mro) l nd IOnRL (355) The output voltage ripple is calculated from AV = max(vo*)min(vo*) (356) There are two cases that must be considered in evaluating (356). For d > l1n, (356) becomes AVo = vo*[(m+d)T+tmax]vo*[(m+d)7] (357) where tma is shown in Fig. 12. For d < 1 In, (356) becomes AVo = vo*[(m+d)T+tmax 1Vo*(mT) (358) If (357) and (358) are plotted as a function of d, they will intersect at a minimum point where d 1 In. Figure 32 shows a MATLAB [30] plot of (357) and (358) for the circuit of Fig. 12, where n = 4. The two equations intersect at a minimum ripple of AVo = 0.097 V at d = 0.25. In Chapter 7 the estimated value for AVo will be shown to be 0.095 V. For the minimumripple condition (d = l/n), the value of AVo is given by (358), which can be written using (354) as AVo = vCl*[(m+d)T+tmax]vCl*(m7) (359) Expansion of (316) gives vcl* during the discharge interval, and the value of tm can be found from where the derivative of Vcl equals zero. Substitution of (316), (347)(348), and (350)(355) into (359) will result in the simplified equation: dTVlon( 1 ao) AVo C I ,(DO lnF)j (360) where t2b fl 2b Tn (361) T n I 0.16 AV0 0.14 d!l/n 0.12 d> lln 0 > 0.1 0.08 0.06 0.04 0 0.1 0.2 0.3 0.4 0.5 d Figure 32. The output ripple as a function of duty cycle for d > lln and d < l/n for the circuit of Figure 23. A more complete derivation of (360) can be found in Appendix A. Figure 33 shows the variation of Ron and C with fixed AV. for a typical fourstage converter. The efficiency is calculated from PO 0o2 1 ( 2 1 = RL dlonVin (362) which can be rewritten using (355) as 1 Vn 100% (363) VIn x 104 2 C 1.5 S1 Av,= o.i% 0.5 Av o 0.5% AVo =1% 0 0.1 0.2 0.3 0.4 0.5 ohms R. Figure 33. Charging capacitance vs. R,, for a converter with n =4, Vi. = 50 V, V, 10 V, P, = 50 W, C = 1.9 F, k = 2, andfs = 100 KHz. The maximum possible efficiency obtainable from a given converter is when switching losses are negligible, or TP = 1. This gives the maximum efficiency as nV Tlmax Vn 100% (364) which is equal to the previously derived expression for efficiency [52]. CHAPTER 4 POWER DISSIPATION AND THERMAL ANALYSIS Calculating the power dissipation in a device is necessary so that the proper heat sinking and mounting procedures can be used to keep the device operating well within its maximum ratings. Power dissipation in the SCDDC is due mainly to conduction losses. However, switching losses can also have significant effect on the performance of a SCDDC. As the switching frequency moves up into the 100 KHz range and beyond, switching losses can begin to cause a noticeable reduction in the output voltage. Switching losses occur when energy is lost in the parasitic capacitors of the MOSFETs and diodes as they charge and discharge [42]. This chapter analyzes the power loss in the SCDDC. Section 4.1 calculates the conduction loss of each component in the converter. Section 4.2 presents an analysis of the effects of switching losses on the output voltage of an SCDDC. An expression to calculate the energy lost during a chargedischarge cycle of a capacitor is derived, along with the power lost due to switching. Section 4.3 calculates the total power dissipated per component using the results from the previous two sections. Section 4.4 discusses heat flow in a material. The concept of thermal resistance is used to calculate the junction temperature of a device. This junction temperature is used in the design procedure to determine the size of the heat sink needed to keep the device operating within its rated conditions. 4.1. Conduction Losses Conduction losses occur in an active device while the device is conducting current, as opposed to switching losses where power is lost as the device is switching from "on" to "off' or vice versa. In a passive component such as a resistor, losses occur when the component is conducting current. During the charge interval, conduction losses occur in Mc, D2ADnA, and CICn. During the discharge interval, conduction losses occur in M2Mn, D2BDnB, and CICn. The conduction loss over a switching period can be calculated from the familiar m+ 1)T PC = v(t mT)i(t mT)dt (41) mT where v and i describe the time dependence of the voltage and current across the device. Using (41), the loss in the current source MC is given by P cmc dI on[Vin Vo (n 1)(VF +Vcj(mT) + 'C)] (42) The loss in each charge diode D2ADnA is given by PcA 'dlon VF (43) The loss in each discharge diode D2BDnB is given by d'Io n VF cB n (44) The loss in each switching MOSFET M2Mn is given by d'on+ AVC Vo) cm n (45) The loss in each capacitor C2Cn is given by PCC,(Ion)2 Resrd d + 2) (46) (n  Finally, the loss in capacitor C1 is given by C I 1jd(l V + 2d'(kC j V2 (47) PcC1 R1 n Rif .,max) where tmax is given in (A14). Figure 41 shows the typical conduction loss of each component (as modeled in Chapter 6) for an eightstage converter. 4.2. Switching Losses As previously stated in Chapter 2, switching losses occur when the parasitic capacitors of the MOSFETs and diodes charge and discharge. The switching losses take away from the available output power, reducing the output voltage. In (355), this effect is shown to be equivalent to reducing the charging current from Ion to TIon, as shown in Fig 22(a). The MOSFET and diode capacitance model used is found in [43], and is given by 1.4 1.2 1 (0. ..Q8. G6. G4. 02 0.ii , Mc IjCJA EJB Figure 41. Conduction power loss in each component for a converter with n =8, Vin = 100 V, V,0= 10 V, P,= 10W, C= 1.91.tF, k=5,fs=207KHz, AVo= 1%. Cp(v) = Co(1 + m (48) where v is the voltage across Cp, CO is the zerobias capacitance, + is the pn potential and m is a constant. The energy lost during a chargedischarge cycle of a voltagedependent capacitor as it charges from a voltage of zero to a voltage of V is E = 2 VCp(V)dv (49) which, for m = 0.5, simplifies to E = 4co P + 0(V + 2 (410) For a capacitor whose value remains constant with voltage (Cp(v) = Co), (49) simplifies to E = Co(V)2 (411) 4.2.1. Switching MOSFET Energy Loss The capacitance model of a power MOSFET is made up of three capacitors, the voltagedependent draingate and drainsource, and the constant gatesource [43]. During a switching cycle, the drain voltage of Mj goes from V. to VjM and back, the gate voltage goes from zero to Vo+Vlin and back, while the source voltage remains constant at Vo, where for j=2,3,... n, VjM= Vo+4j1)VF+(J1)Vjf(m+d)TI (412) Thus, the energy absorbed by the draingate capacitor of Mj can be calculated as Ej = 4Cdgo( j + (VjM 24') + 2(I) + CdgO(Vlin)2 (413) jmdg = L ,o [ The subscriptj represents the jth MOSFET, while the subscripts d and g represent the drain and gate terminals. A similar designation s applies to the source terminal. The first term represents energy lost as vdg goes from zero to VjM, while the second term represents the energy lost when Vdg goes from Viin to zero. The draingate capacitance is a constant Cdgo when Vdg < 0. Using (411), the energy absorbed by the constant gatesource capacitor of Mj is given by Ejmgs = Cgso[(Vo)2 + (Vlin)2 (414) When the gate voltage rises from zero to Vo + Viin, the energy lost to the draingate and gatesource capacitors is supplied by the gatedrive circuit. When the gate voltage falls to zero from Vo + Vlin, the energy lost to the draingate and gatesource capacitors is donated by the converter power stage. Therefore, in calculating the net energy lost by the power stage of the converter, only one half of the values given in (413) and (414) are used. The energy lost to the drainsource capacitor of Mj is given by Ejmds = 3Cdso ( + jM 05+ 2 (415) The values for Cdgo, Cgso, and CdsO can be calculated using the capacitances specified in a MOSFET data book: the input capacitance Ciss, the output capacitance Coss, and the reversetransfer capacitance Crss. The relationships between these capacitances, which are usually specified at Vds = 25 V and Vgs = 0 V, are given as Cis =Co + C +16) Ciss =Cso+ CdgoQI+ + (416 Coss = Cdso(l + Vds M + Cdgo(l + d)m (417) Crss= Cdgo(1 + V dgM (418) For = 0.75 and m = 0.5, these relationships simplify to CdgO = 5.86Crss (419) Cdso = 5.86(Coss Crss) (420) Cgso = Ciss Crss (421) 4.2.2. Current Source MOSFET Energy Loss In this analysis it is assumed that MC is a pchannel MOSFET. Therefore, the source voltage remains constant at Vin, the gate voltage goes from Vin down to Vgate and back, and the drain voltage goes from [VnM (n I)(AVc)I up to VnM and back. The energy lost to the draingate capacitance is then given by Ed (Vin Vn2)o +Cdo(VnV ate)2 (422) where Vgate Vin + VT ; VT < 0 (423) gm Only onehalf of this energy is used in calculating the net power loss by the converter. The energy lost to the gatesource capacitance is given by Ecsg = Cgso(Vin Vgate)2 (424) The energy lost to the gatesource capacitance of Mc is not used in calculating the net energy lost by the power stage of the converter because the current that flows is between Vn and the gate drive circuit of MC. The energy lost to the drainsource capacitance is given by Ecsd= 3Cdso0 [+ 0 ) (viaVnm2 )+2 1 +Cdgo(VinVM(nl)AVC) (425) As with the draingate capacitance, only onehalf of this energy is used in calculating the net power loss by the converter. 4.2.3. Diode Energy Loss The power diode circuit model [27] consists of a contact resistance in series with a diode having a junction capacitance. As previously stated, this junction capacitance is modeled using (48). In the circuit of Fig. 21, it can be seen that there are two types of diodes, charge and discharge. The charge diodes (type "A" diodes) are forwardbiased during the charge interval. The discharge diodes (type "B" diodes) are forwardbiased during the discharge interval. During the charge interval, thejth Bdiode voltage goes from VF to VjB, where VjB = Vo +(J)VF+(2)VCj[(m+d)T] (426) During the discharge interval, the/h Adiode voltage goes from VF to (Vcj[(m+d)TI + VF). Neglecting the contact resistance of the diode and VF, the energy lost to DjA is then given by EA=04 [l R~( )l (VciI(m +d)1 24)+24] (427) Neglecting the contact resistance of the diode, the energy lost to DjB is 4 rrV B \O EjB = cjo +) +(VjB2 )+ 2 ] (428) 4.2.4. Switching Power Loss The total energy lost per switching cycle by the power stage of the SCDDC E. is the sum of the energy lost from each parasitic capacitor of the switching devices, or n E=Ecdg +Ecds + ('E + md 5E + EA+ E 49 jm2d2s 2 jjB j=2 The total power lost due to switching is then given by Ps = fsEs (430) The value for T is obtained from (28), or 111= (431) P+ To obtain the desired output voltage Vo the current through Mc during the charge interval must be increased by the factor I/T or IMc = o ; mT< t <(m+d)T (432) The total power lost due to switching by each MOSFET and diode can also be calculated as Psmc = (Ecdg + Ecds + Ecgs)fs (433) Pjsm = (Ejmdg + Ejmds + Ejmgs)fs (434) PjsA = Ej As (435) PjsB = Ejfs (436) Upon examination of (412)(436) it should be obvious that for a given circuit the switching power loss is the same value in each of D2ADnA, while variable in D2BDnBand the switching MOSFETs M2Mn. From (412) and (426) it can be seen that the magnitude of the charge interval voltages across DnB and Mn are greater than DjB and M (j < n). 0.8 0,7 0 6 0 5 0.4 0 3 0.2 0.1 Figure 42. Switching power loss in each component for a converter with n =8, V, = 100 V, V,= 10 V, P = 10 W, C= 1.9pF, k=5,f,=207KHz, AVo= 1%. Therefore, the greatest switching loss in DnB and Mn is greater than for DjB and M. (I< n). Conversely, the switching loss in D2B and M2 is less any DjB and M where (> 2). Figure 42 shows the typical switching loss of each component (as modeled in Chapter 6) for the eightstage converter of Fig. 41. 4.3. Total Power Loss Using the results of the previous two sections, the total power per device can be calculated by summing the conduction and switching power losses, or Ptmc =cmc + smc (437) PjtA PcA + PjsA (438) PjtB = PcB + PjsB (439) Pjtm = Pcm + Pjsm (440) Ptc = PcC (441) PtC I = PcC1 (442) 4.4. Thermal Analysis There is a massive amount of literature on the subject of heat transfer, and this dissertation does not intend to present any new material. However, the subject of heat sinking and thermal management must be addressed for a SCDDC, especially for medium output power. In order to simplify the analysis, several assumptions will be made. Heat flows by conduction only (convection and radiation are not discussed). The thermal model is static (transient heat flow is ignored). The heat dissipated by a component and its heat sink is uniform, i.e. there are no "hot" spots. The rate at which heat energy is transferred by conduction from a junction at temperature 7 to the air at temperature Ta is defined as Q [23]. It is linearly proportional to the temperature difference between the two interfaces and inversely proportional to the thermal resistance between them, R0, or T._ _Ta Ro (443) For analysis purposes, it is necessary to define the thermal resistances between three boundaries: the resistance between the junction and the case of the device ROjc, the resistance between the case and the heat sink Rocs, and the resistance between the heat sink and the air (ambient) Rosa. The value for Rojc can be found in the MOSFET (or diode) data books. It is a function of the die junction area, the substrate material, attachment method, and package material. The value for Rocs is a function of the mounting procedures and can be kept down between 0.1 to 0.2 CIW if proper procedures are used [3]. The thermal resistance of a heat sink to air of thickness 6 (incm), crosssectional area Ao (incm2), and thermal resistivity Po is defined as 6 90 Rosa = A0 (444) Because of reliability concerns, it is very important that the junction temperature T of the MOSFETs and diodes not exceed the maximum junction temperature rating 7max. It has been found that a lower junction temperature corresponds to a lower failure rate. For example, a junction operating at temperature of 175C will have a failure rate three times that of one operating at 125C. In a MOSFET, calculating the junction temperature is also important for two other reasons. First, the value for Ron is temperature dependent. For example, for a MTM8N40 having a drain current of 6 A, Ron = 0.45 (1 at 25C and Ron = 0.80 fl at 1000C [36]. Such a large increase in Ron can prevent Mc from remaining in saturation during the entire charge interval. Second, T7 determines the maximum power P.. that can be dissipated by a device. For example, for the MTM8N40 (TO204 case) the value for P.. is 150 W at Tj = 250C. However, this value for Ptmax must be derated for temperature by the factor 1/Rojc = 1.2 W/C for temperatures above 250C. This means that for 7= 1250C, Ptma = 30 W. Typical values for Ptmax and Rojc are shown in Table 41. Table 41: Typical Maximum Power and Thermal Resistance Values Ptrnax Rojc (watts) (C / watt) 50 2.5 75 1.67 125 1 150 0.83 250 0.5 The junction temperature can be calculated using (443) as Tj = Ta + Pt(Rojc + Rocs + Rosa) (445) where Pt is the total power dissipated by the device. The size of the heat sink needed can be calculated using (444) and (445). To find the necessary value for Rosa, the junction temperature should be set to some value well below Tmax. For a MOSFET, a typical value for/jmax is 150'C for TO220 and TO204 packages. Ambient temperature is normally set at 25C, but may be different depending on environmental conditions. As previously stated, the value for Roes is approximately 0.1 to 0.2 C /W, and the value for Rojc can be found from the device data books. The thermal resistivity for a variety of materials is shown in Table 42 [231. Table 42: Thermal Resistivities of Materials Used in Electronic Equipment Material Resistivity MC cm/watt Still Air 3050 Mylar 635 Silicone Grease 520 Mica 150 Filled silicone grease 130 Alumina 6.0 Silicon 1.2 Beryllia 1.0 Aluminum Nitride 0.64 Aluminum 0.48 Copper 0.25 CHAPTER 5 DYNAMIC ANALYSIS AND COMPENSATION Knowledge of the openloop dynamic response of the converter is needed so that a feedback network can be designed to keep the output voltage constant in the presence of changes in input or output parameters such as the input voltage or the output load. Analyzing the dynamics of the converter is also important in the development of large and smallsignal equivalent circuits, whose use greatly reduces the time necessary to simulate the converter circuit in PSPICE. In this chapter, the open and closedloop dynamic response of the converter is analyzed using the results of Modified StateSpaceAveraging derived in Chapter 3. Section 5.1 derives the openloop input current to output voltage and duty cycle to output voltage transfer functions by perturbing the averaged statespace equation derived in Chapter 3. The averaged statespace equation is also used to derive the large and small signal equivalent circuits. From the smallsignal circuit, several different impedances are calculated, along with the audio susceptibility function. Section 5.2 closes the loop and discusses a method of compensation to optimize the transient response of the closedloop converter by manipulation of the phase margin of the loopgain. Section 5.3 calculates the voltage gain of the closedloop circuit and discusses the effects of feedback on the input and output impedances and other functions of interest. Section 54 gives an example of how to implement a closedloop converter. 5.1. OpenLoop Response The openloop transfer functions are now derived [33]. The input vector to state vector transfer function is derived first, followed by the duty cycle to state vector transfer function. 5.1.1. Current Amolitude Control Assume that a small variation in the input vector U = U+ai (51) causes a similar variation in the state vector x = X+! (52) The duty cycle is assumed to remain constant, or d = D. Substitution into (333) gives X+X = A(X+i)+B(U+i) (53) The dynamic model can be extracted from (53), and neglecting secondorder terms, is given by x = A.c+Bfi (54) Using Laplace transforms, the input vector to state vector transfer function can be shown to be .1 z = (slA) B (55) U Although (55) contains four separate transfer functions, the only one that will be considered is the one that relates the input current to the output voltage. Using (354), the input current to output voltage transfer function is given by nDT % k (s + o~) = GC(s) = (56) 1 c(n I + k)CRL + 1")+ kCRL where C = (I p)2tfs (57) For medium output power or when k >> n, a good approximation to (56) is given by nDTF kC (58) kS+TCRL) Equation (58) has a single pole, which means that the overall phase of Gc(s) will never be more than 90 degrees at the crossover frequency, and may be much less negative for large values of C1 = kC (medium output power). See Appendix B for a more complete derivation. 5.1.2. Duty Cycle Control To derive the duty cycle to state vector transfer function it is assumed that a small perturbation occurs d = D+d (59) while the input vector remains constant. Because matrices A and B are complicated functions of d, there is no way to easily factor out d. Instead, the A and B matrices are expanded in a Taylor series [41] about the steadystate value of the duty cycle D. This allows A and B to be written in the form: A(dD) = A(D)+a1(D)(dD)+(a2(D)(dD)2+...) (510) B(dD) = B(D)+bl(D)(dD)+(b2(D)(dD)2 +...) (511) Neglecting all terms higher than firstorder, evaluation of (510) and (511) using (59) and substitution of (52) and (510)(511) into (333) gives ,+ i (A + ald)(X + .c) + (B + bl21)U (512) where the firstorder coefficient matrices, a, and b1, are Ilp.t(n1) (I a(l aI = a, IF go _+(I_ ) W I CL(Ron "+"Resr) + (n I + k)RL] [ I 1) rDT(n 1) b= Rn aC(Ron + Resr)] bI[ +=D C[+ ctC(RD + Resr] p(n 1) kC(Ron + Resr) C(Ron + Resr) p(n 1) kaC(Ron + Resr) p+ CRn+ Resr)j where pi and a evaluated at d = D. The dynamic model can be extracted from (512) and, neglecting secondorder terms, is given by x _A + d(a1X + b I U) (515) Using Laplace transforms, the duty cycle to state vector transfer function can be shown to be dc (slA)(al d (516) Again, the only transfer function of interest is the one relating the duty cycle to the output voltage. Assuming that (354) holds, for medium output power or when k >> n this transfer function can be approximated as (513) (514) iVo 1 nIonT z = Gd(S)r':S kLI kC (517) Equation (517) is similar to (58) in that it is a singlepole function, with the overall phase contribution never more than 90 degrees at the crossover frequency. See Appendix B for a more complete derivation. 5.1.3. Averaged StateSpace LargeSignal Circuit Model The averaged statespace equation ((333)) is now used to derive the averaged state space circuit model [33]. Expansion of the averaged statespace equation gives d v C I i c I1 ( 8 dt kC AllvCl +Al2Vcj+BIon +B12VF (518) dvcj i C= A21VcI +A22vcj + B2IOn + B22VF (519) where A,1, A 12, A21, A22, B,1, B12, B21, and B22 are defined in (344) and (345). Using (3 54), and solving for the currents ic, and icj, (518) and (519) simplify to Cl (I T )n ) (520) iC1 ;I+ d Iol (vC vo Rn)( (521) iCj~t pIxd on (Vcj Vo VF)(1 OaC (1 T ( 1 A circuit representation of (520) and (521) is shown in Fig. 51 where + VF Figure 51. Statespace averaged circuit model. Req (5 1 eq (1I) (nl)fsC (522) The circuit in Fig. 51 is a largesignal dc circuit model. The steadystate dc output voltage can be calculated directly as Vo = ndTIonRL (523) which is identical to (355). The current source in Fig. 51 is actually a pchannel power MOSFET, where the channellength modulation is neglected and the drain current is given using (22) as ics= nd'lon = ndTI" Km(Vgs + VT) (524) Figure 52 shows the statespace averaged circuit model with the current source replaced by the largesignal MOSFET model, including the terminal capacitances and drain resistance [44]. The labels in the MOSFET model of d, g, and s stand for the drain, gate and source, respectively. 5.1.4. SmallSignal Circuit Model The smallsignal circuit model is derived by perturbing the averaged circuit model of Fig. 52, which results in the circuit of Fig. 53. Neglecting VF and the secondorder terms, the ac resistance term is derived as eReq (525) eq Ron + Resr The perturbed current of the current source is given by ics nTKm[d( Vgs + VT) Digs] (526) The smallsignal circuit model can be found from Fig. 53 and is shown in Fig. 5 4. The drain resistance RD is assumed to be constant, which means that there is no quasi saturation region in the epidrain [44]. For medium and high voltage MOSFETs with maximum Vds ratings greater than 300 V, RD = Ronp. Otherwise, RD is measured using another method [44]. Vi. + CS _J_. Cdg I(n1)C kC KL Cgs g + VF Figure 52. Statespace averaged circuit model with the MOSFET model in place of the current source. 5.1.5. Impedances and Admittances The circuit of Fig. 54 can be used to derive the openloop input and output impedances. Using (526) and assuming that d = D, 's = n and D = 1'd = 0, the input impedance is given by I 1 in +Cds(RD + Gc) Cx Zi(s) = n+(527) ts Is +C nD gm +s Cxq+nDPgmCy(Req +Gc) (+ C x + gmCy(R eq + Gc) + CxCy(Req + Gc) where Cx = Cgs + Cds (528) Cy = Cds + Cdg (529) RD d Vi.+ in 10+ 2o RL Figure 53. Circuit resulting from perturbation of the statespace averaged circuit model. The poles and zero of (527) are at relatively high frequencies as compared to the poles and zero of (56) and to the practical values of switching frequencies. Therefore, for the frequencies of interest (which are less than some submultiple of the switching frequency), (527) can be approximated as 1 Zi~) nD P gm (530) where the transconductance gm is given by W gmL= 2Km = "Copp(Vgs + VT) for (23) and (24), respectively. gm = Km = CoWvsat (531) (532) Vo+ o Cds RD S RD d 0 R q + r q n + Ics Cdg Rn+req kC 'in( PCs _._ 1(~)C CR cgs g Figure 54. Smallsignal circuit model for the SCDDC. Assuming that the impedance looking into the drain of a MOSFET is large at the frequencies of interest, the output impedance is given by 1 S+ Vo (n l)C(Req + req) I Z0(s) I = skC (533) Io S + kC(Req+req) 1 a Another function of interest is the gate admittance, which relates the gate voltage to the drain current. The gate admittance will be used in the next section to calculate the loop gain for currentamplitude control. Using the circuit in Fig. 54, for a pchannel MOSFET the gate admittance is given by (s nDPgm Ygate(S) = cs Cdg Cdg4) V (Cdg + Cds)(RD + Zps) (Cd + Cds)(RD+Zps) Again, as in (527), the pole and zero frequencies of (534) are relatively high as compared to the pole of (58) and the frequencies of interest. Therefore, (534) can be approximated as Ygate(S) t nD'Pgm (535) 5.1.6. Audio Susceptibility Function The audio susceptibility function (input voltage to output voltage transfer function) is derived from the input current to output voltage transfer function given by (58) and the input impedance given by (530). It is assumed that the duty cycle is constant, or d = D. The drain and source currents of the current source are assumed to be equal, and are given by Ics = Id = ndion s (536) The audio susceptibility function can now be found using (58), (530) and (536) as nD'gm o kC(537) Din (S + I The dc value of this function is gm" RLI which means that any lowfrequency change in Vin can have significant effect on Vo. 5.2. Compensation The output voltage of the converter is to be regulated by controlling the amplitude of or the duty cycle of the current through MC. This is done by feeding back the output voltage to a compensation and control circuit, forming a closedloop system, as shown in Fig. 55. If the current amplitude is used to regulate the output, the control circuit would supply Mc with a gate voltage that could vary in amplitude while maintaining a constant duty cycle. If the duty cycle is used to regulate the output, the control circuit would supply MC with a gate voltage that could vary in duty cycle while maintaining a constant amplitude. Because the SCDDC would very often be connected to integrated circuits, the desired output response would have the fastest possible rise time with minimal overshoot, which corresponds to a loopgain phase margin between 45 and 60 degrees. To obtain the desired transient response, a feedback compensation network He(s) found in [50] is used to supply the necessary phase at the crossover frequency. For current amplitude control, the loopgain TCL is given by Fig. 55(a) as TCL = Ggate(s)Gc(s)Hc(s) (538) where Ggate(S) is given by Ggate(S) = YgateHgate (539) 61 (a) (b) Figure 55. Closedloop system for a SCDDC using current amplitude (a) and duty cycle (b) control. and Hgate is the gain of the gate drive circuit of the current source (in this case it is negative). For duty cycle control TCL is given by Fig. 55(b) as TCL = HpwmGd(S)Hc(S) (540) where Hpwm is the gain of the PulseWidthModulation circuit. The expression for Hc(s), shown in Fig. 56, is given by V R C z R I z c Rf Cfl 1 + Rf 1 + HR (s s Cf2 << Cf1 (541) Vo Ri CfH+Cf2 1+s Ri l+ 0 ) p ( 0 p where the openloop gain of the amplifier Aamp is neglected and 1 o = 1 (542) z RfCfl 1 0p = (543) P Rf Cf2 62 cf2 7f I 4 I I I I IQ I fCf1 I I I L    Ri VCAmp Vinv V vc Figure 56. Operational amplifier implementation of the compensation network He(s). Figure 57 shows the gain and phase characteristics of He(s) for an experimental 1 W, four stage converter. The frequency response of the closedloop systems in Fig. 55 can be determined by examination of the phase of the loop gain TCL at the crossover frequency (oco, or the frequency where the magnitude of TCL equals one. Without the added phase from the pole and zero of Hc(s), the maximum phase of TCL is only 270 degrees at cOco. This means that although the system is stable, the response of the system is very slow. Therefore, to obtain the desired response the pole and zero of Hc(s) must supply between 30 and 45 degrees of phase at the crossover frequency. It is assumed that the crossover frequency is to be set to some fraction of the switching frequency, where the fraction is less than one half [39]. It is further assumed that the lowfrequency pole of TCL is much less than coco, or 63 70 (a) 60 S 0 calculated measured 40 30 20 102 03 104 1o Hz 200 (b) 2 20 U 240 260 measured 280 10 10 10' 10s Hz Figure 57. The gain (a) and phase (b) for the compensation circuit for a duty cycle controlled SCDDC with P. = 1 W, Vi. = 25 V, Vo = 5 V, n=4, k= 19.l,f = 100 KHz, C= 0.68 p1F, Vref 2 V, +M = 60 degrees, Ri = 91!Q, Rb = 62 f, Rf= 1.1 KO, Cf, =.016 gF, Cf= 1180 pF, Pl= 0.1 W. 1 I o (0 (544) C tRL co If the following are defined as: 0co OzO)p (545) (CO (0p 0) COco (546) then it can be shown that the phase of H,(s) is given by ZHc(s) = 180' 2arctan(K1) = 3601 + 2arctan(K) (547) Using (547), the phase of TCL is now given by ZTCL = 900 + ZHc(s) = 450' + 2arctan(K) (548) The phase margin (4m > 0) is then given by 4m = 3600 + ZTCL = 900 + 2arctan(K) (549) The value for K can be found from (549), and is given by K= tan(m+90) (550) 5.3. ClosedLoop Response This section looks at the performance of the closedloop system, especially the output voltage as related to some reference voltage, and the effect of feedback on the output impedance and the input impedances looking into the gate and source of Mc. 5.3.1. Voltage Gain In the closedloop system the value of the output voltage of the SCDDC is to be directly related to the value of some reference voltage Vref, or Vo = ACLVref (551) The compensation circuit, shown in Fig. 56, can be used to calculate the value of ACL by summing the currents at the inverting terminal of the opamp, or vc Vinv +Vo Vinv Vinv ( 2 Rb= (552) Zf Ri Rb where Zf sfII(f+ (553) Vinv =Vref Aamp (554) and Aamp is the openloop gain of the operational amplifier. A more accurate expression than (541) for the gain of the compensation circuit can be shown to be ( aampRi vc Zf/ Ri + Zf H (s) =V= R.I A ampRi (555) 0 R1 + Zf) 66 For a goodquality highfrequency amplifier, Aamp is very large for the frequencies of interest [48], and (555) can be approximated as Vc Zf HV(S) = Vo ;z' (556) He~s)v0 R. Using (552)(556), the equation for ACL can be shown to be vo ( R . ACL = = 1 +!+ 2_&.sA (557) Vref Rb f TCL Zf +1 1 (8 TCL I AampTCLRi(?Ri,+ (558) where TCL is the loopgain given by (538) or (540). The dc (s = 0) gain error term SA0 can now be calculated using (538)(539), (5 53), (556) and (558) as SA0 = (559) The percent gain error is then given by ASAO = (1 SAO) 100% = 0 (560) From (557)(558), the dc voltage gain is given by A0 = 1 + (561) 67 To find the component values for the compensation circuit, choose some value PRi as the power dissipation of Ri. Using (56 1), the input component values can be calculated using Ri Vre,), (562) PRi R. Rb (563) Using (541)(543) and (546) the feedback components can be calculated using Rf = Vnc(co)iR (564) 1 Cf1 = R1z (565) I Cf2 = 1 (566) Rf(O 5.3.2. Impedances Since the output voltage is sampled by the feedback circuit, the output is said to have shunt feedback. Shunt feedback lowers the output impedance, which is now given by [111 (Zo 11 R)( Z0c I TCL (7 Lowering the output impedance is advantageous because the effect of a large increase in output current will have a much smaller effect on the output voltage, as compared to the openloop circuit. Examination of (533) shows that Zo goes to infinity as the frequency goes to zero, but (567) goes to zero at dc. Since the amplitude of the gate voltage is controlled by the feedback circuit, the input is said to have series feedback. Series feedback increases the input impedance, which is now given by Zic = Zi(l TCL) (568) Increasing the input impedance is advantageous because the effect of a large increase in input voltage will have a much smaller effect on the output voltage, as compared to the openloop circuit. Examination of (527) shows that Zi is fairly small, which means that even a small variation in input voltage can have a significant effect on the input current, and thus the output voltage. However, (568) goes to infinity as the frequency goes to zero which means that even a relatively large variation in input voltage will have a very small effect on the input current and the output voltage. 5.3.3. Audio Susceptibility Function The closedloop audio susceptibility function can be calculated using (58), (537) and (568) as nD'gm V o k C 1 ( 9 21i (s+ "1_TCL (569) in +______ ( L) Again, it is assumed that the duty cycle is constant, or d = D. As previously mentioned, the effect of feedback is to reduce the effect of a variation in input voltage on the output voltage. At dc (569) goes to zero, which means that even a relatively large variation in input voltage will have a very small effect on the output voltage. 5.4. Design of a ClosedLoop Converter An example will now be given to illustrate how to design a closedloop converter. The input parameters are Vin = 24 V, Vo = 10 V, and Po = 25 W. The complete results of the design procedure for this example are presented in Chapter 7. In this example, a Micro Linear ML48 11 High Frequency Power Supply Controller [31] is used as the main component of the feedback loop. The ML4811 uses pulsewidth modulation (PWM) to control the output voltage (duty cycle control). Figure 58 shows the circuit blockdiagram of a twostage experimental converter with a ML48 11 as the control device. Although the ML4811 has many features such as soft start reset, cyclebycycle current limit, and under voltage lockout, for simplicity only the input, PWM and output sections are shown. The switching frequency is chosen to be 100 KHz and the crossover frequency is set to be fs/3. The reference voltage was chosen to be Vref = 5.1 V since the ML4811 has Figure 58. Simplified circuit diagram of an experimental 25 W converter. this voltage as an output on pin 19. An estimate of Hpwm can be calculated from the data sheets of the ML4811 by dividing the duty cycle range by the ramp valley to peak voltage. For the ML48 11, this value is Hpwm = 0.28. If the phase margin is set to 60 degrees, the component values compute to be Ri = 240 Rb = 250 al, Rf = 4 Kf, Cf1 = 4500 pF, and Cf2 = 323 pF. Figure 56 shows the gain and phase plots of the resulting compensation network and Fig. 59 shows the gain and phase of the closedloop gain TCL. It can be seen from Fig. 59 that the crossover frequency is approximately 33 KHz, and the phase is approximately 300 degrees at the crossover frequency. This gives a phase margin of 60 degrees. 80 60 40 20 calculated simulated 0 20 3 . 10 10 10 10 Hz (b) 280 290 simulated 300 0 310 32 0 calculated 330 340 102 103 104 10 s Hz Figure 59. The gain (a) and phase (b) of the closedloop gain TCL for a dutycycle controlled SCD DC with P. = 25 W, Vi, = 24 V, V, = 10 V, n = 2,f,= 100 KHz, C= 6.8 gF, Vref= 5.1 V, m = 60 degrees, Ri = 240 n, Rb = 250 n, Rf = 4 K, Crf = 4.5 nF, Ct2 = 323 pF, PSPICE simula tion. CHAPTER 6 DESIGNING A SWITCHEDCAPACITOR DCDC CONVERTER As stated in Chapter 1, SCDDCs have been analyzed many times using StateSpaceAveraging, and in the previous chapters using Modified StateSpaceAveraging. However, there has been little written on how to design a practical SCDDC for a specific application, especially for medium output power. In designing a SCDDC, there is a tradeoff between total capacitance used (which translates into size) and efficiency. For a given application, there are many different solutions that will satisfy the set of input and output specifications, where each different solution may have a different total capacitance. It is the objective of this chapter to present a method of design that will enable the reader to design a SCDDC that has the minimum total capacitance volume for a given input voltage, output voltage, output ripple and minimum efficiency. This chapter also gives the designer an idea of the component parameters that will be encountered for particular values of input voltage, output voltage and output ripple. The component parameter models are used to calculate such things as Ron and the parasitic capacitances that the designer would see in a datasheet. In Chapter 7 these models are used to calculate the limits of converter performance using available components. Section 6.1 presents the parameter models for the power MOSFETs, power diodes and capacitors. These models give empirical relationships between the parameters needed in the design procedure and the current and blocking voltage. Section 6.2 discusses the rationale behind how to select the number of stages and the switching frequency, along with the requirements of the gatedrive circuit. Section 6.3 presents the optimized design procedure. 6.1. Component Parameter Models This section presents the component parameter models empirically derived from manufacturer's data sheets. These models are used in the design procedure in calculating the minimum total capacitance volume for the given converter requirements. 6.1.1. Charging Capacitors In choosing the type of capacitor to use in a SCDDC, the designer has to take into account such parameters as maximum working voltage, maximum available capacitance, equivalent series inductance (ESL), equivalent series resistance (ESR), size and cost. Based on these criteria, this dissertation recommends using the SupraCapTM, a multilayer ceramic capacitor made by the AVX Corporation [4]. These capacitors, made especially for use in switching power supplies, feature extremely low ESR and ESL. They can be obtained with working voltages up to 500 V and capacitance values up to 1300 p.F. They also come with leadframes for either thruhole or surface mount assembly. In using multilayer ceramic capacitors, the designer must decide which type of dielectric to use, as each one has its own distinct advantage. The COG (NPO) dielectric has the most stable capacitance with age and frequency. The X7R dielectric has the most stable capacitance with temperature. The Z5U dielectric provides the highest capacitance for a given size. Since one of the goals of the design procedure is to find the minimum size of the total capacitance, the Z5U dielectric will be used in this dissertation. In order to compute the volume of the total capacitance, a standard capacitance per unit volume S(Vwk) as a function of working voltage will be defined. Using the SupraCapTM capacitance data, this relationship is found to be (24000 .F3 V) S(Vwk)' in (61) Vwk where Vwk is the capacitor working voltage rating. In the design procedure Vwk will be set to the maximum voltage across the capacitor times a safety margin, or Vwk Sm Vcj[(m + d)T] (62) The maximum value for Vwk is 200 V for the Z5U dielectric. It will also be assumed that Resr and C are inversely proportional to each other. Using the SupraCapTM capacitance curves and specifications, this relationship is found to be 24mflpitF Resr C (63) where C is given in microfarads. A more complete derivation of the capacitor parameter relationships can be found in Appendix C. 6.1.2. MOSFETs As with the charging capacitance, a standard power MOSFET model for M2Mn will be defined using current power MOSFET data books [34][36]. The relationship between blocking voltage VbIock, average drain current IMj, and Ron for this standard power MOSFET will be given as Ronmax(25C) = 0.1132 An VbiO~k (64) 7 0 rating d 'W on5 IMj n 1 (65) VbIock = SmVin (66) where Ronmax(250C) is the value of Ronma when the junction temperature is Ti = 25C and rating is the minimum current rating of a power MOSFET for a given value of blocking voltage. This value for Ron is the maximum allowable value that will fit the data [36]. The minimum allowable value is given as [36] Ronmin(250C) = 5.8(Vblock)2 + 0.026 (67) where the maximum value for VbIock is 1000 V. The value for!rating as a function of lMj and Vbock is given as the maximum of [36] /rating 40 A 05 (68) JVblock /rating = IMj (69) In choosing M2Mn from a data book, the designer needs to know the value of Ron(25 C). However, the value of Ron used in the design procedure to minimize the total capacitance is the value of Ron at the operating junction temperature, or Ron(!]). This relationship between Ron(/]) and Ron(25"C) is given by Ron(T.) = Ron(25C)" [0009. T + 0.775] (610) For reliability reasons, in the design procedure the junction temperature will be set to one half of max, which for most power MOSFETs is Tmax = 150'C. Using (610), the value for Ron(25 C) becomes Ron(75C) T.= 75'C (611) R0n(25C) 1.45 ; where Ron(75C) is defined as the value for Ron that gives the minimum capacitance volume for a given design. The zerobias capacitances of the power MOSFET in picofarads are found from 0.85p Vbock + 810pF Cdgo = Ro(25c) (612) 1.17f)pF 1 Vblock + 147KIpF Cdso = Ron(25oc) (613) 1.1f!QpF V Vblock + 33f)pF Cgso Ron(250C) (614) In a power MOSFET data book the input, output and reverse transfer capacitances are specified at Vds = 25 V and Vgs = 0 V. These capacitances can be calculated using (416)(418). The relationship between g. and Ion for a pchannel power MOSFET is given by 0.53 mhos gm = Ion A Ion> 0.94 A (615) gm = 0.5 mhos ; Ion < 0.94 A (616) The threshold voltage is given by VT = 3.5 V, and the value for Viin is set to 10 V. The maximum value for lMc is given by 'Mcmax = 3000 AV (617) VbIock A more complete derivation of the power MOSFET parameter relationships can be found in Appendix C. Again, as with the charging capacitors and power MOSFETs, a standard diode model will be defined using data from current data books [ 131[211. The blocking voltage is assumed to be between 50 and 1000 V, and pn junction power diodes are used. To increase efficiency, Schottky diodes could be used for blocking voltages less than 100 V, but they will not used in this particular model. The forward voltage of the diode is given as VF = kT[ln((ofn) + ln(10)(0.0206 Vblock + 7.22))] (618) where kT = 0.0259 at T = 25C and kT = 0.0302 at = 750C. The junction capacitance Co in picofarads is related to the diode current by Cjo = 65286.28Vblock (619) Finally, the maximum diode current Idmax is given by ldmax = 49.6 0.046Vbiock (620) A more complete derivation of the power diode parameter relationships can be found in Appendix C. 6.2. Practical Considerations In this section, advice is given on how to determine the number of stages and the switching frequency for a specific converter. The gatedrive circuit current requirements are also discussed. 6.2.1. Selecting the Number of Stages The first thing to decide when designing a SCDDC is how many stages to use for a given value for M, where M = V (621) Vo In previous work [17][52] the number of stages was computed by rounding M down to the nearest integer, which will be defined as nmax (if M is an integer value then subtract one to get nmax). This gives the maximum possible efficiency, but not necessarily the minimum capacitance volume VCT, given using (61) as CT VCT S(V (622) S(VWk) where CT is the total capacitance given by CT = (n1+k)C (623) In the design procedure the designer selects a minimum value of efficiency 1lmin. It can be shown that any converter can be designed to use less than nmx stages (assuming that n..x > 2), and that the minimum value for CT occurs when n = 2. However, because of the increase in working voltage as n is reduced the minimum value for VCT does not necessarily occur at n = 2. To determine the value for n, the value of ilmax as given by (364) is calculated for n = 2 to nmax, and these values compared to imin. The minimum value for n, nmin, is given where the function Ail has the smallest positive value, where Ail = 1lmax71min (624) The converter is then designed for all integer values of n from nmin to nmax. The value of n is chosen as that where VCT is minimum. 6.2.2. Selecting the Switching Frequency Maximizing the switching frequency is important when trying to minimize the size of the converter because, as shown in Chapter 3, the charging capacitance is inversely proportional to switching frequency. It has been reported [14] that a switching frequency of 10 MHz has been used in a 50 W resonant converter. The problem in switching at 10 MHz is that the effects of the packaging parasitics (such as lead inductance) start to become noticeable. The effects of these parasitics have not been modeled in Modified StateSpaceAveraging and will not be considered in this dissertation. Therefore, the maximum switching frequency is limited tofsmx = 1 MHz. 