A characterization of buried oxide layers formed by oxygen implantation

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Title:
A characterization of buried oxide layers formed by oxygen implantation
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vi, 141 leaves : ill. ; 28 cm.
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English
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Brady, Frederick T., 1963-
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Subjects / Keywords:
Metal oxide semiconductors   ( lcsh )
Thin films -- Electric properties   ( lcsh )
Silicon-on-insulator technology   ( lcsh )
Electrical Engineering thesis Ph. D
Dissertations, Academic -- Electrical Engineering -- UF
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bibliography   ( marcgt )
non-fiction   ( marcgt )

Notes

Thesis:
Thesis (Ph. D.)--University of Florida, 1991.
Bibliography:
Includes bibliographical references (leaves 136-140).
General Note:
Typescript.
General Note:
Vita.
Statement of Responsibility:
by Frederick T. Brady.

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University of Florida
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Table of Contents
    Title Page
        Page i
    Acknowledgement
        Page ii
    Table of Contents
        Page iii
        Page iv
    Abstract
        Page v
        Page vi
    Chapter 1. Introduction
        Page 1
        Page 2
        Page 3
        Page 4
        Page 5
        Page 6
        Page 7
        Page 8
    Chapter 2. Capacitance-voltage theory for silicon/insulator/silicon capacitors
        Page 9
        Page 10
        Page 11
        Page 12
        Page 13
        Page 14
        Page 15
        Page 16
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        Page 19
        Page 20
        Page 21
        Page 22
    Chapter 3. The effects of processing on the pre-irradiation defect densities
        Page 23
        Page 24
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    Chapter 4. The effects of total-dose irradiation on the charge trapping of the buried oxide layer
        Page 46
        Page 47
        Page 48
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        Page 50
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        Page 81
        Page 82
        Page 83
        Page 84
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    Chapter 5. High electric field stressing of the buried oxide layer
        Page 87
        Page 88
        Page 89
        Page 90
        Page 91
        Page 92
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        Page 112
        Page 113
        Page 114
        Page 115
    Chapter 6. The dual-beam optical modulation technique
        Page 116
        Page 117
        Page 118
        Page 119
        Page 120
        Page 121
        Page 122
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    Chapter 7. Conclusions
        Page 134
        Page 135
    References
        Page 136
        Page 137
        Page 138
        Page 139
        Page 140
    Biographical sketch
        Page 141
        Page 142
        Page 143
Full Text











A CHARACTERIZATION OF BURIED OXIDE LAYERS FORMED BY
OXYGEN IMPLANTATION










By
FREDERICK T. BRADY


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA
1991














ACKNOWLEDGEMENTS


Working towards a Ph.D degree is much like a quest although it is essentially

a solitary project, one is pushed on by his teacher and assisted by those he meets on
the way. And so, I would like to thank some of those who have helped me.

First and foremost, I would like to thank my advisor, Dr. Li, for giving me
the opportunity to pursue graduate research, and for being very supportive of my

research efforts. I am also indebted to Wade Krull of Ibis Technology, for whom I

worked as an Associate Engineer for two summers, and who particularly assisted on
the radiation study portion of this work. In addition, I gratefully acknowledge the

financial support of Harris Corporation, the Rome Air Force Development Center,

and the Florida High Technology and Industry Council.

Furthermore, I would like to thank Professors Dorothea Burk, Robert Fox, Arnost

Neugroshel, and Kevin Jones for serving on my doctoral committee.

Finally, I would like to thank the various students in the lab through the years
for many interesting conversations, and for putting up with me during the times I

was heavily using the equipment. I would especially like to thank Hung Shen Chen

for many valuable discussions.













TABLE OF CONTENTS

page

ACKNOWLEDGEMENTS ................................................... ii

A B ST R A C T ................................................................. v

CHAPTERS

1. INTRODUCTION .................................................... 1

1.1 Methods of Forming the SOI Materials .................................... 2
1.2 Characterization of Defects in SIMOX Materials and Devices .............. 4
1.3 Objective and Approach .................................................. 6

2. CAPACITANCE-VOLTAGE THEORY FOR
SILICON/INSULATOR/SILICON CAPACITORS ................ 9

2.1 The Si/Si0 2 Interface ..................................................... 9
2.2 Derivation of SIS C-V Theory ............................................ 11
2.3 Application of SIS C-V Theory to Fitting Experimental Curves ........... 15

3. THE EFFECTS OF PROCESSING ON THE PRE-IRRADIATION
DEFECT DENSITIES .......................................... 23

3.1 Low-Temperature Annealed Samples ..................................... 23
3.2 Samples Annealed at 1285C ............................................. 27
3.3 Quick-Turnaround Devices ............................................... 29
3.4 Sum m ary ................................................................ 32

4. THE EFFECTS OF TOTAL-DOSE IRRADIATION ON THE
CHARGE TRAPPING OF THE BURIED OXIDE LAYER ........... 46

4.1 The Interaction Between Ionizing Radiation and the Si/SiO2 System ...... 47
4.2 Experim ental Details .................................................... 48
4.3 Basic Radiation Response ................................................ 49








4.4 The Effects of Processing ................................................ 52
4.5 Sum m ary ................................................................ 58

5. HIGH ELECTRIC FIELD STRESSING OF THE BURIED
OXIDE LAYER .................................. ............... 87

5.1 Fowler-Nordheim Tunneling .............................................. 87
5.2 Experim ental Details .................................................... 89
5.3 R results .................................................................. 90
5.4 D iscu ssion ............................................................... 95
5.5 Sum m ary ................................................................ 97

6. THE DUAL-BEAM OPTICAL MODULATION TECHNIQUE ...... 116

6.1 Nondestructive Evaluation Techniques ................................... 117
6.2 Theory of the DBOM Technique ........................................ 119
6.3 Experim mental Details ................................................... 125
6.4 R esu lts ................................................................. 125
6.5 Sum m ary ............................................................... 127


7. CONCLUSIONS ................................................... 134

R EFER EN CES ............................................................ 136


BIOGRAPHICAL SKETCH ................................................ 142














Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

A CHARACTERIZATION OF BURIED OXIDE LAYERS FORMED BY
OXYGEN IMPLANTATION

By

Frederick T. Brady

May 1991

Chairman: Prof. Sheng S. Li
Major Department: Electrical Engineering


A thin semiconductor film on an insulating layer presents a device structure with
a small active volume and greatly reduced junction capacitances. Thus, much research
effort has been spent on SOI (silicon-on-insulator) technology in order to facilitate the

development of integrated circuits with superior speed, improved radiation hardness,
and freedom from latch-up.

Of the many techniques for forming SOI structures, the most advanced is the
oxygen implantation technique, known as SIMOX (Separation by IMplantation of

OXygen). In this dissertation, the buried oxide layer formed by the SIMOX technique
is studied. The charges of the buried oxide are investigated as the parameters of the
SIMOX processing are changed, and as the buried oxide is irradiated or stressed with
high voltages. In addition, a technique for the nondestructive evaluation of SIMOX
material is presented.

Since the buried oxide capacitor includes two silicon/silicon dioxide interfaces,
conventional metal-oxide-semiconductor (MOS) capacitance-voltage theory cannot be








used. Instead, MOS theory is modified to extend to two interfaces. The approach

developed consists of fitting theoretical high frequency C-V curves to the measured

curves.

The results show that the best quality material is obtained with an oxygen im-

plant dose of 1.8 x 1018 cm-2, and a high anneal temperature. Choosing the anneal

time involves a tradeoff, as longer anneals reduce the post-irradiation charge trap-

ping, but increase the pre-irradiation fixed oxide charge density. Some interesting

results were obtained in the radiation study. An increase in the film donor density

with X-ray dose was discovered. In addition, it was shown that very few interface

states were generated by irradiation.

The high electric field stress studies showed that multiple oxygen implant samples

were more resistant to stress than were single implant samples. All of the samples

were seen to have low threshold fields for electron injection.

Finally, a contactless technique was developed to measure the recombination
lifetime of SOI substrates. The transmission of infrared light through the test wafer

is measured as it is modulated by free carriers generated by a short wavelength light

source. The lifetime is calculated from the magnitude of the modulation.














CHAPTER 1
INTRODUCTION


This dissertation is the result of a research project whose objective was to develop
techniques suitable for characterizing the oxide charge and interface traps of buried

oxide layers, and to analyze buried oxide layers using these techniques. A second
objective was to develop techniques for the rapid evaluation of SOI material.

The idea of fabricating semiconductor devices in a thin Si film on an insulating
substrate is attractive for several reasons. First of all, since the source and drain
can be fully bottomed, the area of the p-n junctions is greatly reduced, thus greatly

reducing the junction leakage. Decreasing the junction area also minimizes the junc-
tion capacitances. This results in faster devices. The smaller device volume also
has several benefits. The most important of these is a decrease in the sensitivity of
devices to single event and transient upset phenomena. Most of the electron-hole
pairs generated by ionizing radiation will be generated in the substrate. Since the

devices in the active layer are separated from the substrate by an insulating layer,
these excess carriers will not be able to upset the logic states of devices in the film.
Another benefit of the smaller volume is a reduced diffusion current, which allows op-

eration at high temperatures. An additional benefit of the SOI device structure is the
elimination of latch-up. Latch-up is the formation of parasitic transistors or silicon-
controlled rectifiers between neighboring devices. In bulk Si technology, neighboring
devices are isolated by p-n junctions. Under certain conditions, such as radiation
or electrostatic discharge, the isolating junction can become forward biased. In SOI
technology, devices sit on an insulating layer. Thus, neighboring devices can easily
be isolated from one another.








1.1 Methods of Forming the SOI Materials


Because of the above advantages, researchers have been investigating silicon-
on-insulator (SOI) materials since the mid-1960's. Many different materials were
investigated for use as the insulating layer, but problems in achieving high quality
silicon films were encountered. Eventually, the silicon-on-sapphire (SOS) approach
emerged as the technology of choice. The SOS structure consists of a thin Si film
grown on a sapphire substrate. However, SOS still has problems with a high defect

density in the film and a poor film/sapphire interface. The development of solid phase
epitaxy techniques has dramatically improved the quality of the silicon film [1], but
material problems remain. In addition, the sapphire substrate is transparent and
brittle. These properties make it difficult to use SOS wafers in standard production
lines. Because of these problems, SOS circuits have been limited to applications in
which radiation hardness is the prime concern.

With the problems of SOS devices, much effort has been spent developing an
SOI approach with Si02 as the insulating layer. A number of promising approaches
have been developed. They include the recrystallization of polysilicon, BESOI (bond
and etchback SOI), and SIMOX (Separation by IMplantation of OXygen). These
techniques are described below.

In the recrystallization procedures, the first step is the growth of a thermal oxide
on the silicon wafer. If the recrystallization is to be seeded, vias are etched in the

oxide to the Si substrate. Next, polysilicon is deposited on the oxide. The substrate
is then heated, and a heat source is passed over/on the polysilicon. A variety of
heat sources have been used, such as lasers [2],[3], electron beams [4], lamps [5], and
graphite heaters [6]. The sweep rate and substrate temperature depend on the type
of heat source. After recrystallization, grain boundaries or subboundries remain.
Between boundaries, the Si film quality is excellent. The primary application for the
recrystallization techniques appears to be three dimensional circuits.








The BESOI technique proceeds as follows. First, a thermal oxide is grown on a
handle wafer. Next, a second Si wafer is brought close to the handle wafer, and the
wafers oxidized together. The second wafer is then polished and etched down to the
desired film thickness. Due to a lack of control over the etching rates, it is difficult
to achieve uniform film thicknesses in the submicron range. An additional problem
is the presence of voids between the two wafers. A recent development is the use of

backside implants to create n+ or p+ etch stops. With the addition of a second front
side etch stop implant, bonded wafers with very uniform (+/- 10 nm) Si films have
been fabricated with down to thicknesses of 580 nm [7]. However, at this time, the
bonded wafer approach appears to best suited for bipolar applications, which require
relatively thick, high quality films.

The technique regarded as the most promising is the SIMOX technique [8]. The
SIMOX process consists of implanting a very high dose of oxygen (typically 1.5 -
2.2 x 1018 cm-2) into a silicon wafer, followed by a high temperature anneal (at least
1285C for 6 hours). The lower end of the dose range corresponds to the minimum
dose required to form a continuous buried oxide layer [9]. The upper end is deter-
mined by the fact that some Si overlayer must remain intact after the implant [10].

Alternately, one can implant a lower dose and perform several sequential implant and
anneals. Evidence indicates that the multiple implant approach may be superior to
single implants [11]. The usual implant energy is 150-200 keV, and the wafers are typ-
ically heated to 500-700 C during the implant from beam heating. The lower bounds
of the energy is limited by the need to prevent all of the Si overlayer from being
sputtered away or consumed by the oxide. The upper bounds is determined by the
practical limitations of ion implanters. The lower bounds of the implant temperature
is an important quantity. At lower temperatures, the film/buried oxide interface be-
comes polycrystalline or amorphous. This damage cannot be annealed out [12,13,14].
Following the implant and anneal, about 0.2 ym of silicon film is left. One can then








grow an epilayer, or proceed with device fabrication. The advantage of the SIMOX
technique over the previously discussed techniques is that following the post-implant
anneal, the Si is very uniform, and reasonably defect free. At this time, none of the
other techniques can match the ultra-thin film uniformity of the SIMOX process.

At this time, a variety of CMOS circuits have been fabricated using the SIMOX
process. Examples include 64k SRAMs [15,16,17] and CMOS prescalar circuits oper-
ating at 6.2 GHz [18]. Under development are 256k SRAMS.

1.2 Characterization of Defects in SIMOX Materials and Devices

The process of implanting such a high dose of ions creates a highly damaged
structure. The primary defects are dislocations and oxide precipitates in the Si film,
a rough film/buried oxide (F/O) interface, and Si precipitates in the oxide [19]. In ad-
dition, the insides of the implanter are scoured by the implanting beam, leading to the
implantation of metal contaminants [20]. The high temperature anneal significantly
reduces the density of these defects, but it does not eliminate them [21]. Further-
more, as discussed below, it may be beneficial to have a certain level of damage. The
importance of the various defects depends on the device geometry, which depends
in large part on the intended application. There are basically two applications for
SIMOX/CMOS circuits: radiation-hardened and advanced VLSI. The geometry for
these two applications can in turn be divided into partially depleted (PD) and fully
depleted (FD) film. A PD film is partially depleted during device operation, while
a FD film is fully depleted during device operation. Although the depletion state of
the film depends on the doping and thickness of the film, films thinner than 0.2 Pm
are generally FD. For VLSI applications, FD films are used. This is due to several
advantages unique to FD films, such as increased carrier mobility [22], higher drive
currents [23], and a subthreshold slope near the theoretical maximum [24]. However,
in FD devices, the threshold voltage of the front gate is coupled to the substrate bias.
Thus voltage shifts at the film/buried oxide (F/O) interface are coupled to the front








gate. Thus, it is very important to have a good quality F/O interface. The coupling

effect also makes it very challenging to harden FD devices to total dose irradiation.

Another difficulty with FD devices is the parasitic bipolar effect. In samples with a
high carrier lifetime in the film, majority carriers collect in the body (since there is no
body contact). The presence of majority carriers increases the potential in the body,
eventually turning on the parasitic bipolar transistor [25]. This can cause breakdown.
Thus, the excess carrier lifetime is an important parameter.

The main application of PD devices is radiation hardened circuits. It is difficult
to use FD devices in rad hard applications because of the coupling between the front
and back gate voltages. Since there is no coupling in PD films, degradation of the
back channel only increases the device leakage. Even more than in FD devices, the
recombination lifetime is very important in rad-hard PD devices. If the excess carriers
generated by radiation are not removed quickly, the parasitic bipolar transistor will

turn on.

Finally, for all applications, the minority carrier generation lifetime is an impor-
tant parameter. This parameter is closely related to the reverse bias leakage of p/n
junctions, and so is a good indicator of material quality.

Approaches to characterizing SIMOX material can be divided into analytical
methods (TEMs, SIMS, Auger) and electrical methods (transistor parameter extrac-
tion, diode measurements). Much analytical work has been published on effect of

SIMOX processing on the defects of the film and buried oxide [8-14]. Although these
techniques are satisfactory for evaluating the quality of the microstructure and de-
termining the impurity content, they do not indicate the density of electrically active
defects. Electrical characterizations of SIMOX material have focused on diode and
MOSFET measurements, such as junction leakage [29] and DLTS (deep level tran-
sient spectroscopy) [30]. Although these electrical techniques are useful for evaluating
defects in the Si film, one can only get a rough idea of the density of interface states








and fixed oxide charge at the F/O interface. No information on the density of defects
at the S/O (substrate/buried oxide) interface can be obtained using these techniques.

Although the S/0 interface is not of great technological importance, comparison of
the S/O and F/O interfaces improves the overall understanding of the buried oxide.
Thus there is a need to develop a technique that can measure the defect density
of the buried oxide. Furthermore, the electrical techniques described above require
careful fabrication of test structures, and so are not suitable for quick evaluation of
SIMOX material. Several techniques have been applied to SIMOX material for quick
evaluation, such as SPV (surface photovoltage) [31] and spectroscopic ellipsometry
[32]. However, these techniques give only rough information on the defect density,
information only on the microstructure (spectroscopic ellipsometry), or the diffusion
length for only the substrate (SPV). Finally, despite the importance of the buried
oxide to the radiation hardness of SIMOX devices, very little characterization of the
effects of ionizing radiation on the buried oxide layer has been done. The few studies
that have been done have primarily centered on analysis of the back-channel transis-
tors. It is difficult to separate the contributions of interface states and fixed oxide
charge with MOSFET measurements.

A final point to consider is that the SIMOX process is very different from the
thermal or CVD oxide growth process. Thus, SIMOX oxides are essentially a new
material, and so need to be studied from the standpoint of scientific interest.

1.3 Objective and Approach

In this study, there are five basic objectives. They are:

1. Develop a technique to measure the interface state and fixed oxide charge den-
sities at both buried oxide interfaces.

2. Use this technique to characterize the effect of SIMOX processing on the defects

of the buried oxide.








3. Develop a method for quick-turn evaluation of SIMOX buried oxides.

4. Use the buried oxide characterization technique to study the effects of total dose

irradiation on the buried oxide.

5. Develop additional quick-turn/nondestructive techniques for evaluation of SIMOX

wafers.


The format of the disseration is as follows.

In Chapter 2, the high frequency C-V theory for the buried oxide capacitor is
derived. The chapter begins with the general expression for the capacitance of the

Si/SiO2 interface, then the high frequency approximation is discussed. Finally, the
details of the curve fitting are discussed, followed by an example.

Chapter 3 discusses the effects of SIMOX processing on the buried oxide defects,
prior to any radiation or high field stressing. First, C-V and C-t measurements are

used to characterize samples annealed at low temperatures. The generation lifetime

of the film and substrate, as calculated from the C-t measurements are correlated
to the C-V measurements. Next, samples annealed at 1285C are discussed. Again,

C-t measurements are correlated to the C-V analysis. Finally, the quick-turnaround
fabrication technique is developed, and the approach used to study a batch of wafers
implanted together, but given various anneals, and implanted with or without a screen

oxide.

In Chapter 4, the effects of radiation on SIMOX buried oxides are discussed.
The chapter begins with a review of the basic effects of ionizing radiation on SiO2.

Next, the basic radiation effects of SIMOX oxides are discussed. Finally, the effects
of SIMOX processing on the charge trapping are discussed.

Next, high voltage stressing is studied. Both ramped I-V and constant bias

stressing are examined. The results are correlated to the radiation effects discussed

in Chapter 4. The study focuses on samples annealed at 1285C for 6 hours.






8

Following the discussion of bias stress effects, Chapter 6 concerns the develop-

ment of a nondestructive technique for evaluating thin film SOI wafers. The method,

known as the dual beam optical modulation technique, consists of using one light

source for pumping up the carrier density, while monitoring the attenuation of the

second light by free carrier absorption as it passes through the wafer.

Finally, in Chapter 7, the dissertation is summed up, and the major conclusions

given.













CHAPTER 2
CAPACITANCE-VOLTAGE THEORY FOR
SILICON/INSULATOR/INSULATOR CAPACITORS

This chapter presents the theoretical background for C-V analysis of SIMOX
buried oxide layers. The chapter begins with a description of the various charges
found in an oxide layer and its interface. General C-V theory is derived, followed by
the high frequency approximation. The generation of the theoretical C-V curve and
the curve fitting approach are then discussed.


2.1 The Si/Si02 Interface

The Si02 layer in semiconductor devices is an amorphous structure, consisting
of a random network of four oxygen atoms bonded to one silicon atom. For a high
quality Si/SiO2 interface, the transition from crystalline silicon to stoichometric Si02
is atomically sharp. The transition region consists of SiOx, where x is less than 2.
X-ray photospectroscopy (XPS) measurements have found this region to be approx-
imately 10 A thick [33],[34]. A tail of silicon bonding to only three oxygen atoms
extends about 30 A into the oxide. There are four major types of charges in Si02
and at its interface with silicon. These are mobile ionic charge (Qm), oxide trapped
charge (Qot), fixed oxide charge (Qf), and interface trapped charge (Qit).

The source of mobile ionic charge is usually sodium or potassium ions, which be-
come mobile at higher temperatures under an electric field. These positively charged
ions migrate from the bulk of the oxide to the Si/Si02 interface over a period of
time, slowly increasing the oxide charge there [35]. Ionic charge is not a factor in
semiconductor processing today.







Oxide trapped charges arise from defects in the oxide. These defects can be
structural or chemical. The defects, initially neutral, capture electrons or holes to
become charged. An example of this is the E' center. The E' center is a silicon
atom in the bulk of the oxide that is missing an oxygen bond (.Si=O). It has been
shown to correlate with positive oxide charge following irradiation [36]. Since very
little current flows through the oxide layer during normal device operation, the traps
usually remain neutral. However, if carriers are injected into the oxide these traps
can become charged [37]. The distribution of Qm and Qot depends very strongly on
the history of the oxide.

Fixed oxide charge may be caused by more than one type of defect. Although
90% of the charge distribution is located within 34 A of the Si/SiO2 interface [38],
fixed charge is not mobile and is independent of the applied voltage. However, the
chemical identity of Qf has not been established. The value of Qf is highly dependent
on the process used to the create the oxide layer, and on the orientation of the silicon.

Finally, the most common source of interface traps is the Pb center. Pb centers
are silicon atoms on the silicon side of the Si/SiO2 interface bonding to three Si
atoms rather than four (.Si=Si). The dangling bond is an amphoteric trap [39],[40].
As the Fermi level rises from the valence band toward mid gap, the traps capture
electrons, becoming neutral. As the Fermi level rises towards the conduction band, the
traps accept additional electrons, becoming negatively charged. It is also possible for
positive charges near the interface to induce interface traps [38]. The energies of the
traps vary continuously throughout the silicon bandgap. Therefore, their probability
of trapping an electron is dependent on the applied voltage.

The positions of Qm, Qox, Qf, and Qit in the SIMOX structure are shown in
Figure 2.1. The spatial distribution of charge in the oxide cannot be determined
from C-V measurements (aside from destructive etch back experiments). One can
only measure the centroid of the charge. Thus, in the following derivation, the oxide








charge will be modelled as a sheet of charge at the oxide interfaces. For good quality
thermal oxides, this is a good assumption, as Qf and Qox are located very near the

oxide interfaces.


2.2 Derivation of SIS C-V Theory


The energy band diagram for the buried oxide capacitor (BOXCAP) and the
equivalent capacitance are shown in Figs. 2.2 and 2.3, respectively. In this example,
both the film and substrate are assumed to be n-type. The derivation of the high
frequency C-V characteristics is based on the following assumptions:


1. Minority carriers do not respond to the ac signal.

2. Doping near the oxide interfaces is uniform.

3. Qf can be represented as a sheet of charge.

4. Qit does not respond to the ac signal.

5. The distribution of interface traps across the bandgap can be modelled as ap-
proximately U-shaped.

6. Interface traps in the upper half of the bandgap are acceptor-like (negative when
filled), and traps in the lower half of the bandgap are donor like (neutral when
filled).

7. The film is never fully depleted.

8. There is no dielectric constant grading between the buried oxide and the silicon

layers.


If the substrate is grounded, and a voltage applied to the film, part of the voltage
drop will be across the film (Si), part across the oxide, and part across the substrate







(S2). There is also a built-in potential caused by the work function difference between
the film and substrate, denoted by W12. The applied voltage can then be expressed
as

Va =Vsl +Vox +Vs2 +W2 (1)

Assuming the voltage drop across the bulks of the film and substrate to be negligible,
Vsi and Vs2 are equal to the silicon band bending at the interfaces, and denoted by
0s1 and O's2, respectively. The work function difference between two semiconductors,
where S2 is grounded, is [41]
Egi Eg2 2 2
W12 = X1 + qq bl (X2 + 2 W) (2)
2q 2q
In the above equation, X is electron affinity, Eg is energy gap, and q is elementary
charge. Since both semiconductors are silicon, Xi = X2 and Egi = Eg2. The expression
for work function simplifies to

W12 = W2 bI (3)

In analogy to a parallel-plate capacitor, the voltage across the oxide is equal to

Qox/Cox-. The oxide capacitance is given by Cox, while Qox is the charge stored
by the capacitor. Since the charge at the S1 interface must be equal and opposite to
the charge at the S2 interface, Qox can be written in terms of the charges at either
interface. If the S1 interface is taken as x = 0, then

Qox = Qsl + Qtl + (1 R/dox)Qf = -Qs2 Qt2 RQf/dox (4)

In the above equation, Q% is the charge at the surface of silicon, Qt is the interface
trap charge, R is the average position of oxide charge distribution, and dox is the oxide
thickness. A 1 or 2 in the subscript refers to S1 or S2 respectively. If Qf is represented
as a sheet of charge at x = 0 and at x = 1, then


Qf = (1 /dox)Qf







and

Qf2 = xQf/dox (6)
Eq. (1) can then be written in terms of the charge at the S2 interface as

\T I ~Qs2 + Qt2 +^ Qf2 /iXXT/7
Va= sl Q.2+Qt2Qf2 + 2 + W12 (7)
Cox
Alternatively, Eq. (1) can be written in terms of charge at the S1 interface:
\T I i Qsl -+- Qtl r Q^ l\T
Va = -Osl -+ -QS1+-Qt+ + Os2 + W12 (8)
Cox
The equivalent circuit for the BOXCAP can be derived in the following manner.
When a small amplitude, time varying voltage is applied, the amount of charge at
the silicon surfaces and the charge trapped at the oxide interfaces will change. The
silicon surface and the interface traps can be viewed as storing charge, and so having
a capacitance. An expression for surface capacitance is derived below.

2.2.1 General Result [38]

The differential capacitance C, is defined as
C,() -dQ5
d.)= d (9)

The relationship between Q. and Os is

Q, = Sgn(-v) VT F(v5) (10)
Li

In the above equation, Sgn(-v,) is the negative of the sign of v,, 6. is the dielectric
constant for silicon, VT is the thermal voltage, F(vs) is the normalized electric field,
and Li is the intrinsic Debye length for silicon. The normalized band bending, v., is
equal to Os/VT. The electric field is equal to

F(v,) = ([-kvs 1 + exp(kv.) + (-) exp(-kv,)]) (11)

In Eq. (11), ni is the intrinsic carrier concentration, N is doping density, and k is
equal to 1 for n-type silicon and -1 for p-type silicon. The expression for C. then







becomes
C Cfbs[kexp(kv,) k(ni/N)2exp(-kv,) 1] (12)
s (2[-kv, 1 + exp(kv,) + (ni/N)2exp(-kv,)])1/2 (
Cfb., is the surface capacitance for vs = 0. It is equal to


Cfb (13)
s Ld
where Ld is the extrinsic Debye length. Similarly, the differential capacitance of
interface traps is defined as

-dQt/ (14)
~dO

The amount of trapped charge is related to the band bending by

Qt = q JEC[DtD(E)fD(E) DtA(E)fA(E)]dE (15)
vE
The quantities fD(E) and fA(E) are the Fermi distribution functions for donor traps
and acceptor traps, respectively, given by

f(E) = [1 + gexp(k[Ob + V Ot]/VT)]-1 (16)

where 1b is the bulk potential and Ot is the trap energy of interest. The quantity k is
equal to 1 for donor traps and -1 for acceptor traps. The variable g is the degeneracy
factor, equal to 1/2 for donor traps and 1/4 for acceptor traps. The quantities DtD(E)
and DtA (E) represent the distribution of donor and acceptor traps respectively, in the
silicon bandgap. To a first order approximation, only traps within a few VT of the
Fermi level contribute capacitance. Therefore

Cit() = qDtA(E) + qDtD(E) (17)

The total capacitance of the BOXCAP is

1 1 1 1
CT Csl + Ctl Cox Cs2 + C Ct2 (18)


2.2.2 High frequency approximation








If the ac signal is of high enough frequency, minority carriers and interface traps
will not respond. This frequency is approximately 1 KHz for minority carriers, and
100 MHz for interface traps near the band edges. However, 1 MHz is usually high
enough for traps over most of the bandgap. As a result, minority carriers and interface
traps contribute no capacitance. They do follow the dc bias, and so affect neutrality
requirements. Equation (12) for Cs must be changed to account for the lack of
minority carrier response. It becomes

s Cfbs[kexp(kv) 1]
C 1 [2(-kv,- 1 + exp(kv,))]1/2 (19)

A second-order effect must be taken into account at this point. This is the capacitance
caused by the spacial rearrangement of minority carriers at the surface. Although the
area density of minority carriers does not change in response to the ac signal, there
is a volume change. This volume change affects the width of the depletion layer.
Neglecting this effect can cause a 7% error in estimating the depletion capacitance,
which in turn causes an error in estimating doping concentration. This error can
be made less than 1% by choosing a certain surface potential to minimize the error.
From Nicollian and Brews [38], this surface potential is


Om= OL 0.75VT (20)

where OL is the Lindner potential, described later. The band bending is restricted to
being less than OL. The expression for total capacitance simplifies to

1 1 1 1
= I- + 1 + 1 (21)
CT C.1 Cox C.2

2.3 Application of SIS C-V Theory to Fitting Experimental Curves


The theoretical C-V curve is generated from data obtained experimentally. The
critical information is doping density at both interfaces, oxide capacitance, and oxide








area. From this information, an ideal C-V can be generated. To better fit the exper-

imental curve, Qf and Qit can be added to the model. The process of curve fitting is

shown in Figure 2.4. The details for generating the C-V curve are described below.

The oxide capacitance is determined by measuring a capacitor with a film and
substrate of different dopant type. For example, if the film is n-type and the substrate

is p-type and grounded, a sufficiently negative voltage applied to the film will cause

both interfaces to be in accumulation. This means that CG. and Cs2 are much greater

than Cox. Thus

CT = Cox (22)
Alternately, the inversion capacitance can be measured at very low frequencies or with
a bright light shining on the samples. The thickness of the oxide is then calculated

from


Cox
where A is the area of the capacitor. The doping concentrations can be obtained

from the strong inversion capacitance of each interface. For a BOXCAP with both
semiconductor layers of the same dopant type, when one interface is far into depletion,

the other interface is in accumulation, and its capacitance can be neglected. The total

capacitance is then

1 1 1 (24)
CT Cdep + 0o
where
CsA
Cd-ep W (25)
In Eq. (25), W is the width of the depletion layer. As the magnitude of the applied

voltage is increased, the depletion width increases (to maintain neutrality), lower-

ing the total capacitance. However, the minority carrier density also increases, and

eventually the silicon surface responds to an increase in voltage by increasing the

minority carrier density rather than increasing the depletion width. Thus, there is

a capacitance minimum when the minority carrier density approximately equals the








doping density. The surface potential at this point is given by the Lindner potential
[38], and is equal to

OL = VT[2.lln(-) + 2.08] (26)
ni
The maximum depletion width is then

Wmax -/ (27)
^ -V qN (7

From the measured curve

1 1
Wmx = ( oxA)( Cox) (28)

where Cmin is the minimum capacitance. From the last two equations:
N 2ESCbL[xA 1 1
q C= E[A( )]-2 (29)
q -6Zi C^ox
Using the above equation, the doping density can be calculated for both interfaces.
Now, the capacitance as function of voltage can be found.

Since neutrality is required, from Eq. (4)

Qsl + Qtln + Q + Qs2 + Qt2 + Qf2 = 0 (30)

If v.2 is assumed to be known, then V., can be found using a zero finding algorithm,
with vg1 as the unknown. Values for Qf and Dit are picked by the user. Once the
function has been zeroed, the gate voltage Va is calculated from Eq. (7) or Eq. (8).
With the band bending at each interface known, the surface capacitances can be
calculated from Eq. (19). The total capacitance for the given surface potentials is
then
1 1 1 -1
CT(VSl, V.2) Csl(vi) Cox- Cs2(Vs2) (31)
In Figure 2.4, the procedure of fitting theoretical C-V curves to experimental
C-V curves is shown. First, the ideal C-V curve is compared to the measured C-V
curve. Then, as discussed above, oxide thickness and epilayer and substrate doping are






18

calculated from the measured curve. When fixed oxide charge is taken into account,
the fit improves, but the measured curve is stretched out relative to the theoretical

curve. Finally, when interface trapped charge is accounted for, the theoretical curve
fits the measured curve well. It is noted that other groups have generated theoretical

C-V curves for the silicon-oxide-silicon structure [42,43]; however, this is the first

work to actually extract parameters from the measured C-V curve.















Film

+ V-*M+ + +M
M M
M- -
M
M M Buried
Oxide
M
M M
+v + + -X+S r Xe
Subst Ate
Substrate


Figure 2.1. A sketch of the SOI structure, showing the possible positions of the
various oxide charges. The meaning of the various symbols is as follows: X's represent
interface states, +'s represent fixed oxide charge, -'s are oxide trapped charge, and
the M's are mobile ion charge.


















cit 1


C it2


-- II ox I -
(a) c c2
sl Ss2


Cs1


cox


Cs2


(b)


Figure 2.2. The equivalent capacitances of the buried oxide capacitor for (a) low
frequency measurements and (b) the high frequency approximation.






















0
0- -----------













Film C


)xide


Substrate


Figure 2.3. The energy band diagram for the buried oxide capacitor, for the case
of the substrate grounded and a negative bias applied to the film.


V(
A


EC
Ef -IL

Ei


























20
A
--B
C I
..-----.... D \


15 ,

LL_






5 -----------------------------------------
10






5
-15 -10 -5 0 5 10 15

Bias (V)
Figure 2.4. An example of the curve fitting approach. The curves are as follows:
'A' is the measured curve: 'B' is the ideal fit: 'C' is the fit with fixed oxide charge but
no interface traps; and 'D' is the final fit. with both fixed oxide charge and interface
traps taken into account.














CHAPTER 3
THE EFFECTS OF PROCESSING ON THE
PRE-IRRADIATION DEFECT DENSITIES


In this chapter, the effects of SIMOX processing on the defects of the buried
oxide layer are investigated. The study is divided into three sections. The first is for

samples annealed at 1250C or below. The second is for samples annealed at 1285C.

Finally, a batch of wafers are studied using the quick-turnaround approach.


3.1 Low-Temperature Annealed Samples

3.1.1 Experimental

The starting silicon bulk wafers were 3-5 f-cm Czochralski-grown wafers. An
Eaton NV-200 oxygen implanter was used to implant the wafers at a substrate tem-
perature of 500 C, using an implantation energy of 150 keV, and implant oxygen

doses of 1.8 or 2.0 x 1018 cm-2. Following implantation, the SIMOX wafers were
annealed in an N2/02 ambient at 1150C for 3 hours or 1250C for 2 or 16 hours.

Oxygen is required in the annealing ambient in order to grow a thin oxide, to protect
the Si surface from pitting. After the anneal, n-type epilayers (doped 2 x 1015 cm-2)

were grown to thicknesses of 1.3 to 2.0 /m. Devices were then fabricated, including

laterally isolated BOXCAPs.

C-V measurements were taken at 1 MHz using an HP 4280A C-Meter. C-t
measurements were obtained with the HP 4280A using an external pulse source. The

C-t measurements for each interface were made by pulsing from inversion, so that the
effect of the other interface could be neglected. Pulsing from inversion also minimizes
the effects of interface traps on the C-t transient. Standard Zerbst analysis was used








to calculate the generation lifetime [44]. It should be noted that the films are all thick
enough to avoid full depletion, and that the steady-state width of the depletion layer
is always greater than the width of the original silicon seed layer. Thus, this heavily
damaged region cannot be profiled, although it still contributes to the generation of

minority carriers.

3.1.2. Results and Discussion

Typical C-V curves for BOXCAPs with various SIMOX process parameters are
shown in Fig. 3.1. Noting that a positive bias depletes the F/O interface and a
negative bias depletes the S/0 interface, it is seen that the C-V curves vary with
processing significantly more when the F/O interface is depleted than when the S/0
interface is depleted. Thus, the F/O interface is sensitive to changes in processing.

Since the minimum capacitance in inversion increases with donor density, as the
oxygen dose or anneal time is increased, the film donor density increases. Lowering
the anneal temperature also increases the film donor density. Fixed oxide charge
rigidly shifts the C-V curves in depletion. Therefore, one can see that increasing the

oxygen dose or anneal time, or lowering the anneal temperature increases Qnf. Finally,
since interface traps cause a stretch-out of C-V curves, it is seen that increasing the
oxygen dose or lowering the anneal temperature increases Ditl. Therefore, the C-V
measurements show that increasing the oxygen dose, the anneal time, or lowering the
anneal temperature all increase the charge density at the F/O interface and increase
the donor density in the film, but have little effect on the quality of the S/0 interface.

In Fig. 3.2, typical C-t curves are shown for the film. The transients are very
fast (< 0.3 s). A comparison of curves A and B to curves C, D, and E shows that
increasing the oxygen dose or lowering the anneal temperature sharply decreases the
time for the C-t transient, implying that the quality of the film near the buried oxide
is degraded. This result correlates well with the results of C-V measurements, which
also show that the density of defects increases with increasing dose and decreasing








anneal temperature. Furthermore, a comparison of curve A to curve B and curve
C to curve D shows that longer anneals produce devices with longer C-t transients,

indicating a lower defect density. This contrasts with the result of C-V analysis,
which showed higher fixed oxide charge density and increased donor concentration
with longer anneals. In Figure 3.3, typical C-t transients are shown for the substrate.

The major trend observed in this figure is that the substrate C-t transients tend to be

longer for devices with poorer quality films and buried oxides. A comparison of Figs.

3.2 and 3.3 shows that the C-t transients of the substrate are one to two orders of

magnitude longer than the transients for the film, reflecting the better quality of the
substrate. The higher quality of the substrate relative to the film correlates well with
the results of C-V analysis, which showed the density of defects at the S/O interface

to be an order of magnitude lower than at the F/O interface. Comparison of Figs.

3.2 and 3.3 also shows that the quality of the substrate changes less with processing
than does the film. The relative insensitivity of the substrate to changes in processing
was also found from C-V analysis when comparing the S/O and F/O interfaces. The

above results plus the effects of changing the various parameters on the thickness of

the buried oxide layer are tabulated in Table 3.1.

3.1.3 Discussion

Changing the dose of the implanted oxygen, the anneal temperature, and the
anneal time each has certain effects on the defects of SIMOX wafers. The physical
explanation of these effects are discussed as follows.

As shown above, increasing the oxygen dose results in a sharp increase in the
number of electrically active defects for both the silicon film and the F/O interface.
This is because increasing the oxygen dose causes more lattice damage, and produces

a higher concentration of oxygen-related defects in the film. This conclusion can
be seen as follows. The minority carrier generation lifetime in the film, Tgl reflects
the concentration of generation/recombination centers, which are dominated by bulk








midgap levels. Thus, in SIMOX material, Tgl is shortened by dislocations decorated
by metals and by oxygen complexes and precipitates. The film donor density, Ndl is
increased over the nominal doping density by thermal donors (TDs) [45], which are
small oxygen-containing clusters, and by "new donors" (NDs) [46], which are SiOx,
precipitates. Thus, increases in donor concentration over the nominal one can be
linked to increases in oxygen concentration. Since 'Tg is shortened and Ndi is increased
by increasing the oxygen dose, there is a strong indication that higher doses increase
the oxygen content of the top layer. Anomalous increases in donor concentration in
SIMOX material have also been found by other researchers, who linked the increase
to oxygen-related donors [47]. Additionally, Qnf and Dit, increase with dose. Others
have correlated increases in fixed oxide charge and interface traps to increases in the
roughness of the Si/SiO2 interface [48] (for thermally grown oxides). The increase
of Qfl and Dit, indicate that higher doses degrade the microstructure. It therefore
appears that increasing the dose causes more damage and introduces more defects.

Increasing the anneal time has a mixed result. Both Qfi and Ndl increase, indi-
cating a degradation of the buried oxide and more oxygen activity in the film. On
the other hand Tgi increases, indicating a better quality film. The generation lifetime

may be increased by either diffusion of metal contaminants out of the surface layer or
from dissolution of the oxide precipitates. Since Dit, remains the same or decreases,
the correct interpretation appears to be that increasing the anneal time improves

the microstructure, but causes the redistribution of deep-level impurities from the
film to the buried oxide. The increase in Ndl with anneal time may be caused by
nitrogen-related complexes formed during the long anneal [47].

Increasing the anneal temperature from 1150 to 1250C sharply improves the
quality of the film and its interface with the buried oxide. Published TEM data
on SIMOX wafers annealed at these two temperatures show that an 1150C anneal
leaves very high densities of dislocations and oxide precipitates, and produces a poor








F/O interface [21],[49]. Thus, it is expected that Tgl, Qfi, and DitI reflect the poor
microstructure, and with the high concentration of oxygen in the top layer, Nd1 reflects

the presence of oxygen donors.

As discussed above, changing the oxygen dose, the anneal temperature, or the
anneal time has a significant effect on the quality of the film and the F/O interface.
The S/O interface, however, is fairly insensitive to these process variations. Also, it
is interesting that the S/0 interface is much better than the F/0 interface. For a

dose of 1.8 or 2.0 x 1018 cm-2, silicon islands exist in the buried oxide layer near the
substrate, but not near the film. Thus, the islands have little effect on fixed oxide
charge or interface trap densities. Although Qf2 and DUt2 are comparable to thermal
oxides, Tg2 is very low in SIMOX, as values well over 100 pjs are obtained in bulk
silicon. This short lifetime is most likely caused by metallic contaminants introduced
during the oxygen implantation, which subsequently diffuse into the substrate during

the high temperature anneal [50],[51].

For higher temperature anneals, the thickness of the buried oxide layer increases
with dose, but not anneal time. The increase of thickness with dose is expected, since
more oxygen is being implanted. There is no noticeable increase of oxide thickness
with anneal time since the amount of oxygen precipitated out in the film and substrate

is a small fraction of the amount of oxygen implanted. For a given dose, the buried
oxide layer obtained after an 1150C anneal is less than for a 1250C anneal, showing
that a significant percentage of the implanted oxygen is in the form of precipitates

for the lower temperature anneal.


3.2 Samples Annealed at 1285C


3.2.1 Experimental

N-type, 3-5 Q-cm Si wafers were implanted with oxygen at energies and temper-
atures of 150 keV and 550C, respectively. The implant doses were 1.5 or 1.8 x 1018








cm-2. Multiple implant samples with three doses of 5 x 1017 cm-2 were also ex-

amined. Following implantation, the wafers were annealed in an N2/02 ambient at
1285C for 2 or 6 hours. The multiple implant sample was annealed for 2 hours after
each implant, to give a total anneal time of 6 hours. Three-five Q-cm epilayers were
then grown in dichlorosilane at 1050C. Fabrication of test chips then followed. C-V
and C-t measurements were then taken as described in Section 3.1.1.

3.2.2 Results and Discussion

In Table 3.2, the results of analysis of samples annealed at 1285C are shown.
Several interesting results can be seen.

First, for the low implant dose samples, an excess donor density was found. The
donor density is particularly large for the single implant sample, for which ANdl
is 2 x 1016 cm-3. For the multiple implant sample the excess donor concentration
is smaller, but it is still 3 x 1015 cm-3, which is significant when compared to the

nominal doping density of 2 x 1015 cm-3. The cause is the same as discussed above
for samples annealed at 1150C oxygen-related donors. For lower oxygen doses,
a smaller percentage of the implanted oxygen is incorporated into the buried oxide
[10]. Thus, higher anneal temperatures are required to eliminate oxide precipitates

in the film for lower implant doses. A 1285C, 6 hour anneal is not sufficient for a
1.5 x 1018 cm-2 oxygen dose. This explanation is borne out in TEM photographs of
the samples, which shows a high density of oxide precipitates in the Si film for both

low implant dose samples (see Chap. 5).

The sample with the lowest fixed oxide charge and interface state density for
the F/O interface was the standard dose (1.8 x 1018 cm-2) single implant sample
with the short 2 hour anneal. Relative to the LTA samples, the low dose samples
have a lower Qn but a higher Dijt. The high interface state density is due to the
interface roughness, which smears out the C-V curve. For the standard dose samples
annealed for 6 hours, a surprisingly large fixed oxide charge density was seen for the








F/O interface. Since Ditl is reasonably low for this sample (5 x 1010 cm-2eV-1), the
cause is not interface roughness. Similar results are seen for Qf2 and D2. A point
of particular interest is the high value of Dit2 for the low-dose single implant sample.
As will be seen in Chaps. 4 and 5, upon irradiation or electric field stressing, a very
large number of traps are generated at the S/O interface for this sample.

Overall, the data in Sections 3.1 and 3.2 indicates that increasing the anneal
temperature reduces the defect density, increasing the anneal time increases pre-stress
buried oxide defect density, and buried oxide layers formed by multiple implants have

reduced defect densities.


3.3 Quick-Turnaround Studies

3.3.1 Experimental

The test structures were fabricated as follows. N-type silicon wafers of 3-5 Q-cm
were split into two lots, one of which had a 500 A oxide grown on the front surface. The
lots were implanted together with oxygen using the Eaton NV-200 oxygen implanter at

IBIS Technology. The implant dose, energy and temperature were 1.8 x 1018 cm-2, 150
keV and 550C, respectively. The screen oxide was removed by sputtering during the
course of implanting. Following implantation, the wafers were annealed in an N2/02
ambient, at temperatures ranging from 1150 to 1285C and for times ranging from 2
to 16 hours. Epilayers were then grown to a thickness of 1.5 ym, using dichlorosilane

at 1050C. Ohmic contacts to the front and back surfaces were formed by spinning
phosphorous-doped glass on both sides of the wafers, followed by a 950C, 15 minute
drive-in. Trenches were then etched in the Si film, down to the buried oxide, forming
isolated silicon islands on the buried oxide. The area of the resulting capacitors was
450x450 ym2. Although the plasma etch used to isolate the islands may cause some
sidewall damage, the sidewall area is only about 1% of the capacitor area, making
its contribution to the capacitance measurements negligible. The difference between








these QT capacitors and the BOXCAPs discussed in the previous section is that the
other capacitors were on a CMOS test chip, and thus experienced a large amount
of post-SIMOX processing. C-V and C-t measurements were made following device
fabrication.

3.3.2 Results and Discussion

Typical BOXCAP C-V curves are shown in Fig. 3.4. Although the curves shown
in this figure refer to 1285C wafers implanted with a screen oxide (SO wafers), similar
trends were observed for wafers implanted without a screen oxide (NOSO wafers).
Since both silicon layers are n-type, a positive bias depletes the film while a negative
bias depletes the substrate. The presence of fixed oxide charge rigidly shifts the C-V
curve, while interface traps cause a stretch-out, and an increase in the donor density
increases the minimum capacitance. Thus, it is seen in Fig. 3.4 that the film/oxide
(F/O) interface is much more sensitive to changes in the anneal parameters than is
the substrate/oxide (S/O) interface. For the F/O interface, it is seen that the lower
temperature anneals cause an increase in the donor density, while the longer anneals
cause an increase in the fixed oxide charge density.

The analysis of the C-V and C-t data is summarized in Figs. 3.5 through 3.8.
As shown in these figures, all of the parameters show improvement with anneal tem-
perature. This effect is due to annealing out of precipitates and dislocations, as well
as a sharpening of the buried oxide interfaces [19,21,47]. The increase of the film
donor concentration (Ndl) at lower anneal temperatures has also been reported [47],
and is caused by oxygen-related donors. When the anneal time is increased, Tg, tends
to improve, but Qf becomes higher. Surprisingly, the density of traps at the F/O
interface (Ditl) does not increase with Qfj. For thermal oxides, it has been shown
that the density of both fixed oxide charge and interface traps correlates well with
the roughness of the Si/Si02 interface [48]. This may indicate that longer anneals
affect the chemistry of the oxide without making the F/O interface smoother. It is








also interesting to note that although Tgl improves with anneal time, Tg2 is degraded
by it. The increase of the film lifetime with longer anneals is probably due to a slight

annealing out of the dislocations. The cause of the increase of Qfn with anneal time
is under further investigation. Another interesting result is that while SO wafers
have longer lifetimes, NOSO wafers have a lower Qfi. The interface trap densities are

about the same for both wafers. It is expected that the effect of the screen oxide is
to randomize the implant beam, thus reducing channeling. A reduction of channel-
ing should make the depth profile of the as-implanted wafer tighter. However, it is

difficult to extrapolate the reduced channeling to electrical effects.

The results described above correlate well with analysis of fully-processed devices
[52]. In analysis of those devices, it was also found that Tgl improves with anneal time
while Qfi increases and Dit, remains unchanged. Similar trends were found for changes
in the anneal temperature. Although the trends are the same for the fully processed

and QT material, there are differences in the actual values of the parameters. The
QT material has a higher Qfn and lower -Tgl than the fully processed devices. On
the other hand, Tg2 is higher for the QT material. Some of the differences between
the two materials may be due to the extra thermal processing of the FP devices,
since this material experiences the full thermal cycling of a CMOS test chip. The
only processing experienced by the QT material is the 950C, 15 minute drive-in and
the plasma trench etch. The ratio of the capacitor to sidewall area for these devices
is 75 to 1. Therefore, it is unlikely that the capacitor measurements are affected
by sidewall damage. To further investigate the differences between the QT and FP
devices, the effect of CMOS processing was studied by giving several wafers short,
low temperature anneals. This second batch of wafers was implanted in a manner
similar to the first batch, without a screen oxide, and annealed at 1285 C for 6 hours.
After epi growth, the wafers were annealed at 1180C for 60 seconds, 875C for 8
hours, 1050C for 1 hour, or not annealed. The results of C-V measurements on these








devices are shown in Figs. 3.9 and 3.10. The x-axis is roughly in Dt diffusivityy x

time) order. As can be seen, longer, higher temperature anneals reduce the defect

density. Although it is known that a 1285C, 6 hour anneal does not fully anneal

out the defects in SIMOX material, it is surprising that these relatively insignificant

anneals have a major impact. The 1050C, 1 hour anneal reduces Qn by 2 x 1011

cm-2. This result shows that device processing can affect the defects of the buried

oxide layer.


3.4 Summary

C-V and C-t measurements have been used to analyze buried oxide layers formed
by the SIMOX process. The combination of C-V and C-t measurements allows defect
characterization of not only the buried oxide layer, but of its interfaces and of the

silicon near the buried oxide layer. The results show that the quality of SIMOX

material is enhanced by lowering the oxygen implant dose and increasing the anneal
temperature, whereas increasing the anneal time improves the quality of the upper
silicon layer, but lowers the quality of the film/buried oxide interface. It has also been

found that the substrate/buried interface has fewer defects than the film/buried oxide
interface, and that the substrate/buried oxide interface is less sensitive to changes in

processing.

The QT method for fabrication of buried oxide capacitors has been shown to
be a useful approach for the rapid evaluation of electrically-active defects in SIMOX

wafers, particularly for process optimization. Based on analysis of wafers implanted

with and without screen oxides, and annealed at various temperatures and times, it
has been shown that high temperature anneals produce the best quality wafers, and

that the choice of implanting with screen oxides and length of anneal time involves a

trade off. The use of screen oxides and long anneals increased the generation lifetime

of the Si film, but also increased the density of fixed oxide charge at the film/buried

oxide interface. Finally, post-epi anneals were seen to reduce the density of fixed oxide





33

charge and interface traps at the film/oxide interface, showing that device processing

can actually reduce the defects of the buried oxide layer.













Table 3.1. Summary of C-V and C-t Analysis on BOXCAPs. The Parameters are
Defined as Follows. Nd: Donor Concentration, Qf : Fixed Oxide Charge Density,
Dit: Midgap Interface Trap Density, rg: Minority Carrier Generation Lifetime, and
d: Thickness of the Buried Oxide Layer. The Numbers 1 and 2 Refer to the
Film/Buried Oxide and Substrate/Buried Oxide Interfaces, Respectively.


Dose (xl018 cm-2), Anneal Time (hr.)
Parameter 1.8,3 1.8,2 1.8,16 2.0,2 2.0,16
Ndl (xl015 cm-3) 19 3.2 3.5 4.5 5.1
Nd2 (xlo015 cm-3) 2.8 2.3 2.1 2.2 1.9
Qnf (xl011 cm-2) 3.7 2.1 2.6 2.7 3.1
Qf2 (xl011 cm-2) 0.3 0.1 0.15 0.15 0.2
Ditl (xlo011 cm-2eV-1) 2.0 0.5 0.6 2.0 1.0
Dit2 (xl011 cm-2eV-I) <0.5 <0.5 <0.5 <0.5 <0.5

Tgl (Ps) 0.001 0.120 0.220 0.062 0.075
Tg2 (Ys) 14 9 8 9 11
d (jim) 0.30 0.35 0.35 0.37 0.37













Table 3.2. Summary of C-V and C-t Analysis for samples annealed at 1285C. The
Parameters Below are Defined as Follows. Nd: Donor Concentration, Qf : Fixed
Oxide Charge Density, Dit: Midgap Interface Trap Density, and d: Thickness of the
Buried Oxide Layer. The Numbers 1 and 2 Refer to the Film/Buried Oxide and
Substrate/Buried Oxide Interfaces, Respectively.


Dose (xl018 cm-2), Anneal Time (hr.)
Parameter 0.5x3,6 1.5,6 1.8, 2 1.8,6
A Ndl (x 1015 cm-3) 20 3 0 0

Qfl (xl011 cm-2) 1.65 2.0 0.75 4.8
Qf2 (x101 cm-2) 0.2 0.6 0.3 0.9
Ditl (xl011 cm-2eV-1) 1.2 3.6 <0.2 0.5
Dit2 (X 1011 cm-2eV-1) <0.2 0.8 0.3 <0.2
d (/im) 0.32 0.29 0.35 0.35






















1.0
D, t
A- 1.8, 2




0
0.9 B- -1.8, 16 ^ \ \





UD
C -2.0, 2 / \\
D -2.0, 16 \\ V
X 0.8 E- E1.8, 3(1150C) \ \ ^ -



0.7 -
A B

0.6 -


0.5
-15 -10 -5 0 5 10 15
Applied Voltage (V)

Figure 3.1. Typical high-frequency C-V curves for various oxygen implant closes.
anneal temperatures., and anneal times, as indicated in the figure. The symbol "D"
represents the implant dose in units of 1018 cm-2, and "t" represents the anneal time
in hours.







37














1.0 .. .
C D A B

E

D, t
A 1.8, 2
B- 1.8, 16
0 C 2.0, 2
0.9 D 2.0,16
)E 1.8,3 (1150C)







0.8 --I
0.0 0.1 0.2 0.3 0.4

Time (s)

Figure 3.2. Typical C-t transients (normalized with respect to the final capaci-
tance) for various oxygen implant doses, anneal temperatures, and anneal times, as
indicated in the figure, when epilayer is pulsed into strong inversion. The symbol "D"
represents the implant dose in units of 10" cm-2, and "t" represents the anneal time
in hours. Results are shown for the film.





















1.0


C D E

0.9 A



0.8 D, t
0 A- 1.8, 2
B- 1.8, 16
C 2.0, 2
0.7 D- 2.0, 16
E 1.8, 3 (1150C)


0.6 1
0.0 2.5 5.0 7.5 10.0
Time (s)



Figure 3.3. Typical C-t transients (normalized with respect to the final capaci-
tance) for various oxygen implant doses, anneal temperatures, and anneal times, as
indicated in the figure, when epilayer is pulsed into strong inversion. The symbol 'D"
represents the implant dose in units of 1018 cm-2, and "t" represents the anneal time
in hours. Results are shown for the substrate.



















1.00 -
VA.^
',' r ^ -~-- A
Si Film ,,
Buried_0;////7 // \\B
Oxide \
Substrate .i. '-- ---.-.=
0X ................. ........................
0 0.75
D E
^ O .- --- - - - - - - - --



0.50 ----------------------------------
0.50 1 .
-20 -10 0 10 20
Bias (V)


Figure 3.4. Typical C-V curves for SIMOX buried oxide capacitors with various
anneals. The curves are for wafers implanted with a screen oxide. Curve A represents
material annealed at 1250C for 2 hours, curve E is an ideal curve, and curves B, C.
and D represent material annealed at 1285C for 16, 8 and 2 hours, respectively.




















2.5




2.0 -


'E
(~J




X
C1
d7
L-
0



0
1d


1.5 -




1.0-




0.5 -


Qf1


---- --


f2
13 - - - Q

-0- -NOSO WAFER
U- SO WAFER


~1 I


Anneal Time (hrs.)


Figure 3.5. The change in fixed oxide charge density at both the film/oxide
interface and the substrate/oxide interface. A comparison between wafers implanted
with and without screen oxides is also shown.























2


10 -j----Ea- -------

10- /





C 10-
10
03 / ih
10 --





i -4
(3 10-


10 1 1/ -I -
1150 1200 1250 1285 1285 1285 1285
2 2 2 2 4 8 16

Anneal eC, hrs.)

Figure 3.6. The effect of changing both the anneal temperature and anneal time
on the film and substrate minority carrier generation lifetimes, for wafers implanted
with and without screen oxides. On the x-axis labels, the top numbers are the anneal
temperatures while the bottom numbers are the anneal times.







42















2



S10-

1



10 Nd,


0 10


-Dti
-310


10- -I-i
0 5 10 15 20

Anneal Time (hrs.)


Figure 3.7. Summary of the effect of changing the anneal time on the various
parameters of the film and the film/oxide interface. Results are shown for wafers
implanted with a screen oxide and annealed at 1285C. The unit of Tgl is pis, Ndl is
1015 cm-3, Qfl is 1011 cm-2, and Dit, is in 10l eV- cm-2.







43














3
10-



2
10-


II

(D) 10



10- Nd2



-10-
10-------------- ------ ^ ------
1150 1200 1250 1285 1285 1285 1285
2 2 2 2 4 8 16

Anneal (C, hrs.)


Figure 3.8. Summary of the effect of changing the anneal time on the various
parameters of the substrate and the substrate/oxide interface. Results are shown for
wafers implanted with a screen oxide and annealed at 1285C. The unit of Tgl is /is.
Ndi is 1015 cm-3, Qfl is 1011 cm2, and Dit, is in 1011 eV-Vcm-2.
























6


5 -------. X,
N


s-X
N




f1
CM 3



X
o" 2-
%0


-I-f

% 2


0 OfI I2

A B C D

Anneal Temperature and Time



Figure 3.9. The effect of various low temperature anneals on the fixed oxide
charge density. On the x-axis, 'A' represents samples with no anneal, "B' represents
samples annealed at 1180C for 60 s, 'C' represents samples annealed at 875C for 8
hours, and 'D' represents samples annealed at 1050C for 1 hour.





















/ \


5 -


CM 4

3
x"
'2



I \ \
X\
I 2 \ \
-/ 3x Dt 1\

/ 3,

1 Dit2


0 i i I,-
A B C D

Anneal Temperature and Time




Figure 3.10. The effect of various low temperature anneals on the interface state
density. On the x-axis, 'A' represents samples with no anneal, 'B' represents samples
annealed at 1180C for 60 s. 'C' represents samples annealed at 875C for 8 hours.
and 'D' represents samples annealed at 1050C for 1 hour.













CHAPTER 4
THE EFFECTS OF TOTAL DOSE IRRADIATION ON THE CHARGE
TRAPPING OF THE BURIED OXIDE LAYER

Much of the interest in SOI technology is based on the enhanced immunity of
SOI circuits to transient radiation and single event upset [53]-[62]. However, the
buried oxide layer presents an additional oxide whose response to total dose irradi-
ation must be characterized. This is especially true for buried oxide layers formed
by the SIMOX technique. Clearly, the SIMOX process is much different from the
conventional thermal and CVD oxides. Depending on the post-implant anneal, one
can have a highly defective structure (such as oxide precipitates in the Si film, silicon
precipitates in the oxide, and oxide protrusions into the Si film) or a high quality
structure with very sharp oxide interfaces and few defects in the Si film. The effect
of processing on SIMOX material, devices, and circuits has been well documented
[8]-[32]. However, few studies have been published on the effects of total-dose irradi-
ation on SIMOX buried oxides, particularly in relation with SIMOX processing. In
addition, most groups investigating total dose effects have studied the buried oxide
charge trapping by measuring the leakage or threshold voltage shifts of the backchan-
nel transistor. Therefore, one of the objectives of this work has been to investigate
the effects of changing the various SIMOX process parameters on the charge trapping
of the buried oxide layer. The buried oxide characteristics are studied directly by
high-frequency C-V measurements. The effects of varying the implant oxygen dose,
and the post-implant anneal temperature and time are studied. In addition, the
post-irradiation charge trapping is correlated to the pre-radiation charge densities. A
major result is that a large increase in the film donor density with X-ray dose is seen
for low oxygen dose samples.








4.1 The Interaction Between Ionizing Radiation and the Si/Si02 System

4.1.1 Radiation Generated Damage

Ionizing radiation (e.g. X-rays, gamma rays, high energy electrons) can interact
with a semiconductor in either of two ways. If the energy of the radiation is sufficient,

it can knock an atom out of its place in the lattice. Radiation also breaks the bonds
between neighboring atoms, generating electron-hole (e-h) pairs. The effects of lattice
damage and bond-breaking on the performance of devices can be divided into two
categories: transient effects and total dose effects. Transient effects concern the effects
of the generated excess electron-hole pairs. The sudden surge of excess carriers can
turn on parasitic bipolar transistors and thyristors. This action can upset logic states
or even burn out the device. Total dose effects include the gradual build up of

lattice damage and trapped electron and holes as the device is irradiated. In bipolar
transistors, the lattice damage lowers the minority carrier lifetime, thus decreasing
the transistor gain. In addition, the generated carriers can be trapped at the surface

of the transistor, turning on p-n junctions in a manner similar to gated diodes. MOS
devices, being majority carrier devices, are relatively insensitive to lattice damage.
However, they are sensitive to transient effects and to broken bonds in the oxide and
at the oxide/silicon interface. Since the topic of this chapter is total dose effects, the
remainder of this section will concern charge trapping in the oxide.

4.1.2 Radiation Generated Defects in MOS Structures

The details of the dynamics of the formation and annealing of radiation defects
in Si02 are very complicated. The exact sequence of the device processing is very
important. However, the basic mechanisms are as follows.

When ionizing radiation passes into an oxide, the incident energy creates electron-
hole pairs along its track. It has been shown that one e-h pair is created per 18 eV

[63]. Immediately after generation, some of the e-h pairs recombine. The percentage
of e-h pairs recombining depends the applied field and the energy of the particle. The








recombination rate is higher for lower electric fields and particles that create dense
tracks. At room temperature, electrons have a fairly high mobility in SiO2 (about 20
cm2V-ls-'1) [64]. Most oxides have few electron traps, so that the excess electrons

are swept out of the oxide on a time on the order of the dielectric relaxation time
(picoseconds). The transport of holes, rather than being characterized by a single
mobility, is characterized by a very slow, dispersive hopping transport. The averaged
mobility of the holes is below 104 cm2V-s-1 [65]. In addition to the dispersive
transport, a high density of hole traps are found near and at the oxide interfaces.
The trap density is a very sensitive function of processing. The mechanism for the
formation of interface states is still somewhat controversial, but the existence of a
two step process is essentially agreed upon. In the first step, holes drifting through
the oxide react with hydrogen to generate H+. In the second step, the hydrogen ion
drifts to the interface, where it reacts with hydrogen already present to produce H2
plus a dangling silicon bond. The dangling silicon bond is the amphoteric Pb center.
The main controversy is whether the protons are generated near the interface [66] or
in the bulk of the oxide [67]. The interaction of radiation and SIMOX buried oxides
is sketched in an energy band diagram in Fig. 4.1.


4.2 Experimental Details

N-type, 3 5 f-cm silicon wafers were implanted with oxygen, with implant
doses ranging from 1.5 to 2.0 x 1018 cm-2. Following the oxygen implant, the wafers
were annealed at either 1250 or 1285C in an N2/02 ambient, for 2, 6, or 16 hours.
Some multiple implant wafers were also examined. The multiple implant was carried
out by performing three implants of 5 x 1017 cm-2. Each implant was followed by a
2 hour anneal at 1285C for 2 hours, giving a total anneal time of 6 hours. Follow-
ing the SIMOX processing, 3 5 Q-cm n-type epilayers were grown in dichlorosilane
at 1050C. The net Si film thickness was around 1.5 /m. Devices were then fabri-
cated, including buried oxide capacitors (the capacitor formed between the film and








substrate with the buried oxide as the capacitor dielectric) and backgate transistors.
The unlidded devices were irradiated with 10 keV X-rays using an Aracor 4100 Semi-
conductor Irradiation System. Irradiation was performed with all contacts to the
film grounded, and a 0 or -5 V bias applied to the substrate. Threshold voltage
and subthreshold slope measurements were taken immediately following irradiation,
followed by high-frequency (1 MHz) C-V measurements on the BOXCAPs (Buried
OXide CAPacitors).

4.3 Basic Radiation Response

4.3.1 Results

In the following discussion, all voltage shifts referred to are given by their absolute
values. In Fig. 4.2, the effect of increasing the X-ray dose on the back-channel
transistors and on the buried oxide capacitor is shown, for the case of a grounded
substrate. The midgap voltage, Vnd, is defined as the voltage for which the Fermi
level at the Si/Si02 interface is in the middle of the bandgap. Although both donor
and acceptor type traps are found in both halves of the bandgap [68,69], the neutral
point is only a few kT/q from midgap [69] (for ionizing radiation). Thus, AV.id is
a good approximation of the voltage shift due solely to oxide charge. This quantity
is calculated from the shifts in the BOXCAP C-V curves. The threshold voltage
for MOSFETs (Vt), on the other hand, is related to the sum of oxide charge and
interface traps at the energy level corresponding to the onset of inversion. Since
a good correlation is seen between AVnid and AVt, few interface traps are being
created. The effect of a negative substrate bias during irradiation can be seen in
Fig. 4.3. As can be seen, a negative bias reduces the trapping of holes at the F/O
interface especially at doses above 100 kRad. The curves for AVmid and AVtnp are
essentially parallel, showing that very few interface states are generated, even at 1
Mrad. This result can be seen more specifically in Fig. 4.4, in which the subthreshold
slope and interface face trap density are both plotted versus dose. Even at a dose








of 1 Mrad, the subthreshold slopes are close to their pre-irradiation values and the
density of midgap interface traps that has been generated is only 1 x 1011 eV-'cm-2.
The effects of total X-ray dose and substrate bias are shown in detail in Figs. 4.5
and 4.6. In these figures, The degradation of the subthreshold slope is shown for
both n- and p-channel devices. BOXCAP data is not shown, because the C-V curves
were shifted beyond the voltage range of the C-V meter for the biases at which the
generated interface trap density became important. It is seen that ADit, is negligible

except for positive biases and for X-ray doses greater than 100 krad. The average
interface state density can be estimated from the subthreshold slope measurements

by [70]


CADit = oxAS
/ADit- kTln(10) (32)

where AS is the change in the subthreshold slope, and the other variables have their
usual meanings. Using the above equation, it is estimated that 2.4 x 1011 eV-cm-2
traps are generated at 500 krad with a substrate bias of 5 V. The number of generated
traps is below 1 x 1011 except for a total dose above 50 krad and a 5 V substrate bias.

Next, the effect of bias on the charge trapping at the two BOX interfaces is
examined. In Fig. 4.7, the density of trapped charge at both interfaces is shown as a
function of dose for substrate biases of 0 and -5 V. For a 0 V bias, the roughly equal
densities of charge are trapped at both oxide interfaces. For a -5 V bias, however,
the trapping of holes at the S/O (substrate/oxide) interface is greatly enhanced, even
at a dose of 10 kRad. At the F/O (film/oxide) interface, the -5 V bias keeps the
increase of trapped charge with dose relatively flat. Previous work on the total dose
response of buried oxide layers has indicated that there is a bias region for which the
trapping of charge is minimized. In order to investigate this effect, Qoti as well as
AVtn,p are plotted as a function of substrate bias and X-ray dose in Figs 4.8 4.10.
In each of these graphs, it is seen that the substrate bias required to minimize the








charge trapping becomes more negative with total dose. The minimum exists from
competition between three effects. The first is that as the field in the oxide increases,
a higher percentage of electron-holes pairs escape geminate recombination. Thus,
more holes survive to be trapped at the interface. The second effect is that as an
increasingly negative bias is applied to the substrate, holes are repelled from the F/O
interface. The third effect is that the capture cross section decreases as the electric
field in the oxide increases.

4.3.2 Discussion

The pre-radiation density of electrically-active defects is much higher in the film
and at the F/O interface than in the substrate and at the S/0 interface [52],[71].
To see how this affects the post-radiation charge trapping characteristics, we plot
both Qoti and Qot2 versus the substrate bias in Fig. 4.11. For a bias of 0 V or one
that attracts holes to the interface, the F/0 interface traps slightly fewer holes than
the S/O interface. It is interesting that although Qn > Qf2, Qoti < Qot2- For an
attractive bias, the rate of charge build is 3.80 x 1011 cm-2/V at the F/0 interface
and 3.86 x 1011 cm-2/V for the S/0 interface. This implies that despite the higher
density of fixed oxide charge and interface traps at the F/0 interface, the number
of hole traps is nearly the same at both interfaces. However, when holes are being

repelled from the interface under consideration, the S/0 interface traps less holes,
as seen by the fact that the minimum Qot is lower for the S/0 interface than for
the F/0 interface. Since silicon islands are found in the buried oxide layer near the
S/0 interface, but not near the F/0 interface, it is expected that the S/0 interface
would have more traps than the F/0 interface. An alternative explanation may be
that holes are trapped throughout the bulk of the oxide, rather than at the interfaces.
Using photoyield experiments, workers at Harry Diamond Labs found that holes were
trapped in place almost immediately following generation [72,73]. This could account
for the similarity in the charge trapping as determined by the voltage shifts at the








oxide interfaces. The low density of generated interface traps can also be explained
by the lack of hole movement. As discussed above, the generally accepted models of

interface trap generation all require that H+ be generated by hole transport.

An additional comment should be made on the use of negative substrate biases
during irradiation. Clearly, the total dose hardness of the buried oxide is greatly
improved by the use of a negative bias. Since the voltage shifts for a zero volt
substrate bias are significant, a negative bias is needed to reduce the backchannel
voltage shift to keep the circuits functional. Thus, technically, the negative bias is

clearly beneficial. However, from the perspective of a systems designer, the need
for an additional supply and/or pin compatibility can be major issues, and a circuit

requiring a negative bias may not be acceptable.


4.4 The Effects of Processing


The SIMOX process parameters investigated in this study were the dose of the
oxygen implant, the temperature of the post-implant anneal, and the time of the post-
implant anneal. Of these parameters, charge trapping at the F/O interface appeared
to be most sensitive to the post-implant anneal parameters. Although the dose of the
oxygen implant has little effect on the F/O interface charge trapping, low oxygen dose
material exhibits an increase in the film donor density with X-ray dose. A similar,
but weaker, process dependence was seen for charge trapping at the S/0 interface.
An exception to this is the low dose single implant material, for which large increases
in ADit2 and Qot2 were found. For both interfaces, a trend is seen towards reduced
charge trapping for samples with lower initial charge densities. Since similar results
were obtained for AVtp and AVtn, the following discussion will focus on AVtp only.

4.4.1 The Film/Buried Oxide Interface

The effects of varying the implant dose and anneal time are shown in Figs. 4.12
and 4.13, for samples annealed at 1250C and irradiated with Vub = 0 V. Since the








thickness of the buried oxide, hence the number of electron-hole pairs generated in
the oxide, increases with the oxygen dose, so should the charge trapping (ideally).
However, it is seen that the implant dose has little effect on the density of trapped
charge at the film/buried oxide interface (Qoti). Note that the voltage shifts corre-
sponding to these charge densities are greater for the higher dose samples, since Vot

= Qotdox/kox. This seen in Fig. 4.13, where AVtp is shown as a function of X-ray
dose. Increasing the anneal time from 2 to 16 hours, however, strongly reduces Qoti.
The reduction is by around 5.5 x 1011 cm-2. As discussed above, irradiating with a
negative bias reduces the charge trapping. From Figs. 4.14 and 4.15, it can be seen
that the relative reduction is essentially the same for the various samples, showing
that the negative bias does not change the effect of processing on the charge trapping
of the BOX.

The trapped charge density is also greatly reduced when the anneal temperature
is increased. A comparison of Figs. 4.12 and 4.16 shows that for samples with an
implant dose of 1.8 x 1018 cm-2 and annealed for 2 hours, Qoti is reduced by 6.5 x 1011
cm-2. As with samples annealed at 1250C, changing the oxygen dose has little effect
on the charge trapping for samples annealed at 1285C. However, for this anneal
temperature, increasing the anneal time has little effect over most of the X-ray dose
range. The anneal time range is smaller for the samples in the 1285C group than in
the 1250C, but the trend is still clear. In thermal oxides, ion implantation typically
causes electron traps, which can enhance the radiation hardness by compensating the
hole traps [74]. However, in SIMOX materials, our data indicates that the oxygen
implant damage creates more hole traps than electron traps, since annealing reduces
the net positive charge.

It was previously reported that total dose irradiation generates few interface
trap in SIMOX buried oxides [75]. However, in this study, significant interface trap
generation at both buried oxide interfaces was found for samples implanted with an








oxygen dose of 1.5 or 1.8 x 101 cm-2 and annealed at 1285C for 6 hours. The density
of traps at the F/IO interface is graphed in Fig. 4.17. It is interesting that both of

these samples show large increases in ADit and Qot at higher X-ray doses.

In addition to increasing the charge densities of the buried oxide layer, for certain
samples, total dose irradiation was found to increase the effective donor density in
the film. For the low (1.5 x 1018 cm-2) implant dose samples, a large (4 to 8 x

1016 cm-3 at 1 Mrad) increase in the donor density was seen following irradiation.
This can be seen in the C-V curves, shown in Figs. 4.18 4.20. Both the film

and substrate in these samples are n-type, and the C-V curves were taken with the
substrate grounded. Thus, the positive bias portion of the curves corresponds to

depletion of the F/O interface while the negative bias portion corresponds to depletion
of the S/O interface. For the low implant dose samples, the minimum capacitance
of the F/O interface increases with X-ray dose. There are several effects that can
change this capacitance, including non-negligible capacitances of interface traps or
minority carriers, a leaky oxide, an oxide whose effective capacitance changes, or
an increase in the film donor density. Capacitance measurements as a function of
frequency showed that the minimum capacitance was frequency-independent above
100 kHz, proving that minority carriers and interface traps do not contribute to the
measured capacitance. The fact that "good" C-V curves were obtained shows that
the capacitor was not leaky. Finally, Since the minimum capacitance of the S/0

interface does not change (excluding the sample with a high ADi2), one can be sure
that the oxide capacitance is constant throughout the irradiation. This leaves an
increase in the donor density as the cause for the capacitance increase. In Fig. 4.21,
the increase in the film density (ANdl) is shown as a function of irradiation dose. The
donor enhancement (DE) effect was also seen for material with an implant dose of
2.0 x 1018 and annealed at 1250C for 2 hours, but it was fairly small. Note that the

multiple implant samples exhibit a much stronger DE effect than the single implant








samples. Furthermore, the magnitude of the DE effect was found to be independent
of the substrate bias during irradiation. We next discuss the source of the DE effect.

It is widely known that in bulk silicon oxygen complexes and SiOx precipitates
can act as donor centers [45],[46] (known as thermal donors and new donors, respec-
tively). Furthermore, it has been shown that thermal donors (TDs) and new donors
(NDs) can be active in SIMOX material annealed at temperatures below 1300C [47].
It is also known that as one lowers the implant dose, for a given anneal, more oxygen
remains in the Si film. In the low implant dose samples in this study, a high pre-
irradiation film donor density was found (see Section 3.2). We therefore believe that
either TDs or NDs are responsible for the DE effect. To support this thesis, TEMs
were performed on the low dose samples and on a higher dose samples which did not
exhibit the DE effect (see Chap. 5). The multiple implant material was found to
have a very high density of precipitates near the buried oxide. The low dose single
implant material was seen to have a high density of precipitates, but not as high as
the multiple implant sample. Very few precipitates were seen for the material with the
1.8 x 1018 cm-2 implant dose. Thus, the amount of precipitates correlates well with
the DE effect. Also, note that the DE effect has not been observed for the substrate,
and precipitates were not observed in the substrate for any of the samples. Thus, we
believe that the DE effect is related to radiation-induced states at the precipitate/film
interfaces. Note, however, that the precipitate density does not correlate well with
the pre-rad donor effect. The pre-rad effect may be due to TDs.

It is important to consider how the DE effect may affect the performance of
irradiated devices. For example, the addition of donors will compensate the body of
the n-channel devices, thus reducing the backchannel threshold voltage and increasing
the backchannel leakage. In p-channel devices, the well doping near the buried oxide
will increase, thus increasing the drain junction leakage.

A discussion of the effect of processing on the radiation response is incomplete








without correlating it to the pre-rad defect densities. In previous publications, we
showed that Qfn increases with oxygen dose and anneal time, and decreases with
higher anneal temperatures [71],[76]. The trap density at the F/O interface was found
to increase with oxygen dose, decrease with higher anneal temperatures, and to be
insensitive to the anneal time. The general trends seen for the sensitivity of the F/O
interface to SIMOX processing are summarized in Table 4.1. The lowest overall charge
density is obtained for SIMOX material with a low oxygen dose and a higher post-
implant anneal temperature. Increasing the anneal time improves Qotl but increases
Qf-i. The reduction of the net positive charge with anneal time may be related to
the anneal procedure. It has been reported that long anneals in an N2 ambient can
cause a nitrogenization of the F/O interface [77]. Oxynitrides have electron traps
that partially compensate the hole traps. This could explain the reduction of Qotj
with anneal time. The data in Table 4.1 indicates a rough correlation of the pre-
and post-rad charge densities. To investigate this, Qotl is plotted versus Qfi for a
total dose of 1 Mrad in Fig. 4.23. Although the plot is somewhat scattered, a rough
trend is seen towards reduced charge trapping in samples with a low initial fixed
oxide charge density. For samples irradiated with a -5 V substrate bias, the trend is
weaker, showing that a substrate bias reduces the effects of processing, and that some
minimum intrinsic trapping limit is reached. It is also seen that irradiating with a
-5 bias typically reduces Qoti by 5 x 1011 cm-2. Extrapolating the Vsub =0 V data
to Qfi = 0 indicates that the minimum charge trapping that can be expected is still
above 5 x 1011 cm-2. To achieve greater hardness, one must either apply a negative
bias or greatly reduce the buried oxide thickness.

4.4.2 The Substrate/Buried Oxide Interface

The effects of varying the SIMOX processing variables on charge trapping at
the substrate/buried oxide (S/O) interface can be seen in Figs. 4.24 and 4.25. For
material annealed at 1250C, Qot2 is nearly independent of processing. This contrasts








with Qoti, which was found to be sensitive to the anneal time. Samples annealed at
1285C were also found to have a Qot2 relatively independent of processing. An
exception to this is the single-implant low oxygen dose sample, which exhibited high
trapped charge and interface trap densities. The reason for the relative insensitivity of

Qot2 to processing is that the S/O interface itself changes very little with processing.
As discussed below, this correlates well with our pre-rad studies, which show that Qf2
is also relatively insensitive to processing changes. The reason for the high Qot2 for
the low dose single implant is can be found by examining TEM photos. TEMs show

a that the S/0 interface is rough, and a very high density of islands is seen in the
buried oxide. This most likely leads to a high density of dangling or easily broken
bonds, which then act as traps.

A comparison of Figs. 4.12 and 4.24 and 4.13 and 4.25 shows that Qotu and Qot2
tend to have nearly identical functional dependencies on the total X-ray dose (for
irradiation with the substrate grounded). At higher total doses, Qot2 always increases
a little faster. This result is very consistent for a large number of wafers. This result
has practical applications for ultra thin SIMOX wafers, in which the Si film is too thin
for buried oxide capacitor analysis of the film. In this material, one could extrapolate
charge trapping at the F/O interface from the Qot2 measured by C-V analysis of the
S/0 interface.

For the S/0 interface, few interface traps were found to be generated. However,
as seen for the F/O interface, the single implant samples annealed for six hours
were found to have high densities of interface traps generated. For the standard

dose material, ADit, is less than ADAt2, by around 2 x 1011 eV-'cm-2. For the
low dose sample, ADUt2 is very high, as seen in Fig. 4.20. At low X-ray doses, a
stretchout of the C-V curve is seen when the S/0 interface is near inversion. As the

total dose increases, the magnitude of the stretchout increases, and begins around
midgap. Finally, at high X-ray doses, the stretchout begins when the interface is in








weak accumulation, and the trap density is so high that the Fermi level is essentially
pinned.

To compare the pre- and post-irradiation charges of the S/O interface, Qot2 is
plotted versus Qf2 in Fig. 4.26. Although some scatter is seen in the data, Qot2 is seen
to increase with Qf2. This correlates well with a similar plot for the F/O interface
in Fig. 4.23. An interesting difference between the two interfaces is that while Qf2

<< Qfl, Qotli < Qot2. This may be related to the presence of Si islands in the buried
oxide. The islands are predominantly found near the S/0 interface. Hole traps may
be associated with the interface between these islands and the oxide.


4.5. Summary

High-frequency C-V analysis and backchannel transistor measurements have been
used to study the effects of total dose X-ray irradiation on the oxide charge and
interface state densities at the silicon/buried oxide interfaces. The buried oxide layers
were found to have a very low rate of interface trap generation. A negative bias was
found to reduce the buildup of charge at the film/oxide interface, and a bias region

was found for which charge trapping was minimized. A comparison of the radiation
response of the two buried oxide interfaces revealed that for a 0 V substrate bias, or

one that attracts holes to the interface, the film/oxide interface has less charge build

up, while a for a substrate bias that repels holes from the interface, the substrate/oxide
interface has less charge build up.

SIMOX buried oxides with various oxygen doses and post-implant anneal tem-
peratures and times were irradiated with X-rays to investigate the effect of SIMOX
processing on the total dose hardness on the buried oxide layer. Charge trapping
at the substrate/buried oxide interface was found be fairly independent of process-

ing. For the film/buried oxide interface, the charge trapping of samples annealed at
1250C was reduced by long anneals. Samples annealed at 1285C, however, were








found to be insensitive to the anneal time. At both anneal temperatures, the dose of

the oxygen implant did not have a major impact on the charge trapping in the buried

oxide. The results indicate a trend towards reduced charge trapping for samples with

lower pre-rad fixed oxide charge. However, the it appears that the post-rad charge

density (for irradiation with the substrate grounded) saturates above 5 x 1011 cm-2.

Thus, additional measures are needed to reduce the voltage shift at the film/oxide

interface.

Although the implant dose had only a small effect on the buried oxide charge

trapping, samples implanted with an oxygen dose of 1.5 x 10"s cm-2 exhibited a large
increase in the film donor density with X-ray dose. This donor enhancement effect

correlates well with the presence of oxygen precipitates in the film. The DE effect

is important since the donors can compensate the back channel doping in n-channel
devices, increasing the leakage.












Table 4.1. Changes in the pre- and post-irradiation charge densities of the F/O
interface as the implant dose (02 Dose), anneal temperature (TA), and anneal time
(tA) are increased. A dash indicates no change in the parameter.


Parameter 02 Dose TA tA

Q4 T T
Qoti -


Dit -
ADjt -


































VA 0--__---






Incident
Radiation


Film


SOxide
Oxide


Figure 4.1. Energy band diagram, showing the generation of electon-hole pairs
by ionizing radiation.


+
+ +



i ^ ------- E71*


Substrate




















30
Vsub= 0 V

A Vmid2 .

> 20-


g ixVtn ,<
M \1 001.I
0 10- 44, Ar VtP .
> ,- nVid i1 "
10" -0
...... **r! ..1i.l



I -----I I---I--1 1 1 1 1 --i-- i- I i I I I

101 102 103
Dose (krad[Siq02])

Figure 4.2. Magnitude of voltage shift versus x-ray dose for the buried oxide
capacitor and for n- and p-backchannel transistors, for the case of the substrate
grounded during irradiation. AVtntp represents the threshold voltage of the n and
p-channel transistors, while A/Vmid,mid2 represents the midgap voltage shift at the
film/oxide and substrate/oxide interfaces, respectively.





63














8
ub-5 V


6- AVtn
A\4P
6- Ap .2'-> > :

I A~nldl |L-n.'I d I
()4- -' ^


> 2(



01 102 103
Dose (krad[Si02)

Figure 4.3. Magnitude of voltage shift versus x-ray dose for the buried oxide
capacitor and for n- and p-backchannel transistors, for the case of a -5 V substrate bias
during irradiation. AVtntp represents the threshold voltage of the n and p-channel
transistors, while AVmidl represents the midgap voltage shift at the film/oxide and
substrate/oxide interfaces, respectively.





















1 .5 .. .. ..... 1 .5
v =-5 v
sub S
n


C%4
1.0 ~- 1.0 I
E

C,, I>


s / o0
0.5 P 0.5 '-
X
.4-


.00
/ ^~it1
0.0 I.. I I I 0.0

101 102 103

Dose (krad[Si021)



Figure 4.4. Degradation of the subthreshold slope for the n- and p-channel
backgate transistors and generation of midgap interface traps as a function of dose.
The quantities Sn and Sp represent changes in the subthreshold slopes of the n- and p-
backchannel transistors, while Dit, represents the density of interface traps generated
at the film/oxide interface. A bias of -5 V was applied during irradiation.























1.6
1,6 .-------------------------

500 krad

1.5



0 1.4



U/)


1.1100 krad

1.1 10 krad


1.0 I ..IIII
-6 -4 -2 0 2 4 6

Substrate Bias (V)


Figure 4.5. Degradation of the backchannel subthreshold slope for p-charmel
devices, as a function of X-ray dose and substrate bias.






66













1.5
500 krad

1.4 -


0 1.3 -

u/) 100 krad
C 1.2
C/)

1.1


1.0 --10 krad


0 .9 ..I----...
-6 -4 -2 0 2 4 6

Substrate Bias (V)


Figure 4.6. Degradation of the backchannel subthreshold slope for n-channel
devices, as a function of X-ray dose and substrate bias.







67
















25-

SQot2(-5 V)

E 20
(P.)
1-( V)
ot2

".. 15
0
L,


"0 Q ot 1(0 V)
CL






101 102 103


Dose (krad[SiO2])

Figure 4.7. Comparison of trapped charge at both buried oxide interfaces for the
cases of 0 and -5 V substrate bias during irradiation. The subscripts "1" and "T'
refer to the film/oxide and substrate/oxide interfaces, respectively.










































-4 -3 -2 -1 0

Substrate Bias (V)


Figure 4.8.
X-ray dose and


Charge trapping at the film buried oxide interface, as a function of
substrate bias.







69

















102.. .
P-Channel
; ^a ~1 Mrad ^f

>^ ^--"100 krad
101
""S. ~~~~~ ~1 ; e ^ ^ ^ ^ ^ 'l krad



100

10o

10-' --- I --,- --- i --- l --- ---
-6 -4 -2 0 2 4 6

Substrate Bias (V)



Figure 4.9. The magnitude of the p-backchannel threshold voltage shifts as a
function of X-ray dose and substrate bias.





















102



:1 Mrad


100 krad

4.4
> 101

10 krad





100 -,,- i -, ,
-6 -4 -2 0 2 4 6

Substrate Bias (V)

Figure 4.10. The magnitude of the n-backchannel threshold voltage shifts as a
function of X-ray dose and substrate bias.
























2O
Dose = 100 krad[SiOl
'E

C.)
15- o2 otl


4)
10-

0

05 5
Q.5 .'


0.
!._- I i........ ......... ........I!....... ....... _ ^^

0 a a
-5 -4 -3 -2 -1 0 1 2 3 4 5

Substrate Bias (V)


Figure -14.11. Effect of substrate bias on trapping of charge at the film/oxide and
substrate/oxide interfaces, for a dose of 100 kRad(Si02). The quantities Qo0t and
Qo.. refer to the film/oxide and substrate/oxide interfaces, respectively.

























*-1.8, 2 /
E 10 1.8, 16
o 2.0,2 / 2
Sx 2.0, 16 /Ix


0
0 ./.. ,."






0 I 1 I I I ii I jI I I l l

101 102 103
X-Ray Dose (krad[SiO ])


Figure 4.12. The total dose charge trapping for samples annealed at 1250C, for
irradiation with the substrate grounded. The oxygen dose (1018 cm -2) and anneal
time (Hr.) are given for each material in the legend.






73













30
Vsub = 0 V
25 DO 2 tA /

1.8,2 /
20 +1.8, 16 /
r 2.0, 2 "4
S5 x 2.0, 16 /


10 .-
// .D;->

5 I I ,


0
101 102 103
X-Ray Dose (krad[SiO2 ])


Figure 4.13. The p-channel threshold voltage shift for samples annealed at
1250C. for irradiation with the substrate grounded. The oxygen dose (1018 cm-2)
and anneal time (Hir.) are given for each material in the legend.






74













8
Vsub = -5V

D02 tA
._ 6 1.8, 2 /
+ 1.8,16 /
E c32.0, 2
x 2.0, 16 -
"0o 4 .



.00
./ ....'"
r -r ....@; --^-'





0 I I I I i

101 102 103
X-Ray Dose (krad[SiO2])

Figure 4.14. The total dose charge trapping for samples annealed at 1250C, and
irradiated with a -5 V substrate bias. The oxygen dose (1018 cm-2) and anneal time
(Hr.) are given for each material in the legend.






















V =-5V


V =-5 V
sub
D02 tA /
S1.8, 2
10 + 1.8, 16

/
o2.0, 2
x 2.0, 16
>/

,--" ... *B .'" '" -"
5 or
m -l ..1 .....-- - >< .




0 1 I I------- --------I- i ii

101 102 103
X-Ray Dose (kradESiO2])


Figure 4.15. The p-channel threshold voltage shift for samples annealed at,
1250C, and irradiated with a -5 V substrate bias. The oxygen dose (1018 cm-')
and anneal time (Hr.) are given for each material in the legend.



















10 -. A
1.8 2 .
0 1.8 6 /
S+ 0.5 x 3 2 / A
II
E <>1.5 6 / -
*1- / /.
"0 I/ ./'"/
5- /

o .., ,,
X






0

101 102 103
X-Ray Dose (krad[SiO2])

Figure 4.16. Charge trapping at the film/buried oxide interface for samples
annealed at 1285C.

















6


5 -
CM /
4

I>
S 3 Dose= 1.5E18

x 2 Dose=1.8E18






0
101 102 103
X-Ray Dose (krad[SiO2])


Figure 4.17. Generation of interface traps at the film/buried oxide interface for
samples annealed at 1285C for 6 hours.




































0.6



0.5
-30


-20 -10 0 10 20


Bias (V)



Figure 4.18. Typical pre- and post-irradiation C-V curves for SIMOX samples
with an oxygen dose of 1.8 x 1018 cm-2.



















1.0




0.9 -



0.8 -



0.7 -



0.6 -



0.5 -L 0 -
-40 -30 -20


-10 0 10 20 30 40


Bias (V)


Figure 4.19. Typical pre- and post-irradiation C-V curves for SIMOX samples
with thrce implants of 0.5 x 1018 cm-2.





















1.0


0.9


0.8 -

x 1 Mrad
0
L) 0.7 -


0.6 -

200 krad
0.5 Pre-rad


0.4 '-- I 1 I1 1--
-40 -30 -20 -10 0 10 20 30 40

Bias (V)


Figure 4.20. Typical pre- and post-irradiation C-V curves for a single implant of
1.5 x 1018 cm-2.



















8

Dose 0.5E17 x 3

6 -
I
E
o
- 4 Dose= 1.5E1E

x

z
< 2 -
Dose = 2.0E18
^ 2 hr. Anneal

0 1- 1 i m ri- ^ 1 I iL __ L
101 102 103
X-Ray Dose (krad[Si02])

Figure 4.21. The donor enhancement effect, as a function of X-ray dose.






82














6 ...... 2 .0


5
5 1.8

-% 4
C /1.6 o
E C.
LO 3.

ANN- -1.4w
'2
z
<] 1.2
1


0 1.0

101 102 103 104

X-Ray Dose (krads[SiO2])

Figure 4.22. The correlation between the donor enhancement effect and the
degradation in the subthreshold slope. The sample had an implant dose of 2.0 x 1018
cm2, and was annealed at 1250C for 2 hours.







83













15
Excluding 12500C, 2 hr. Anneals
Vsub:

LI [] OV
a 0 V
10







0
X U

5 ~ -5V

U


0
0 2 4 6

Qf 1(x 1011cm-2)

Figure 4.23. The correlation between the densities of the post-irradiation trapped
charge and pre-irradiation fixed oxide charge, for the film/buried oxide interface.



















20 T A= 1250 C

D02 tA
c" 15 1.8,2
E +1.8,16
,.- 2.0, 2
o 10 x2.0, 16
I-.
x

d' 5




101 102 103

X-Ray Dose (krad[SiO2])


Figure 4.24. Post-irradiation charge trapping at the substrate/buried oxide in-
terface for samples annealed at 1250C.


















1 5 ...
T A= 1285 t
Dose tA /
E*1.8 2
c 10 0- 1.8 6 / /
C_ /+ 0.5x3 2 / /




0
T_ < 1.5 6 /7

X
0 5


0

0 --i-- i i i 1i i -- a* il*i i
101 102 103
X-Ray Dose (krad[Si02])

Figure 4.25. Post-irradiation charge trapping at the substrate/buried oxide in-
terface for samples annealed at 1285C.























Excluding 1250 C, 2 hr. Anneals


04 12.5 -



0
X
C"M
.100 -






7.5 -
0.0


.............
"-"- ^^U


I*


0.4 0.6
11 -2
Qf2(x1O cm )


Figure 4.26. The correlation between the densities of the post-irradiation trapped
charge and pre-irradiation fixed oxide charge, for the substrate/buried oxide interface.


15.0














CHAPTER 5
HIGH ELECTRIC FIELD STRESSING OF THE BURIED OXIDE LAYER


In Chapter 4, ionizing radiation was used to inject carriers into the buried oxide.
In the present chapter, the effects of high electric fields are investigated. In particular,
samples annealed at 1285 C are studied. This investigation is relevant to the relia-

bility of the buried oxide in high voltage devices as well as in electrostatic discharge
events. In addition, further understanding of the buried oxide defects is gained.


5.1 Fowler-Nordheim Tunneling

There are two methods of electrically introducing carriers into the oxide. The
first is by hot carrier injection. In this approach, a large electric field is created at
the silicon surface, so that electrons or holes are accelerated at the surface to attain
sufficient energy the surmount the energy barrier at the Si/SiO2 interface. This
can be accomplished with a reverse biased p-n junction or by pulsing the interface
into deep depletion. The second method is Fowler-Nordheim (F-N) tunneling. In F-N
tunneling, the electric field across the oxide is high enough that the carriers can tunnel
from the Si conduction band into the oxide conduction band. This is illustrated in
Fig. 5.1. The barrier height for F-N injection is 3.3 eV for electrons, but 4.5 eV
for holes, so that only electrons can be injected by this means. In this study, F-N
tunneling is employed. Next, the expression for F-N tunneling is derived.

The tunneling current is equal to the product of the number of carriers available
for tunneling and the transmission probability per electron, and can be written as

[78]










J = qfNQ (33)

where J is the current density, q is unit charge, f is the fraction of carriers in the
lowest subband (equal to 0.626 at 300 K for < 100 > silicon), N is the number of
electrons in the accumulation layer, and Q is the transmission probability per unit
electron. The number of electrons in the accumulation layer can be obtained from
electrostatic evaluation of the capacitor, and is equal to (assuming negligable charge
in the oxide)


N OEOX (34)
q
where cox,, is the dielectric constant of the oxide and Eox is the electric field across the
oxide. The transmission probability is given by

q2 m
Q = m2 n EmoxT (35)
87rheoxOB mox
In the above equation, h is Planck's constant, OB is the barrier height, mox/m is the
effective electron mass in the SiO2 bandgap, equal to 0.5, and T is the transmission
coefficient. The expression for T can be found using the WKB approximation, and is

[79]


T = exp( -8r(2moxq)1/2 (B )32) (36)
3hEox

In the above equation, it is assumed that the electrons are all in the bottom of
the conduction band. Combining the above equations, one can write an emipirical
expression for the tunneling current


2 CepC2
J = EoCexp(- 2-) (37)
lox








where



C = m/moxq2N (38)
87rheoxOB
and


C- 87r(2mq)1/2 3/2 (39)
= 3h (

For tunneling into an ideal thermal oxide, C2 is equal to 283 MV/cm. The magnitude

of the electric field required for F-N tunneling is very sensitive to the quality of the

emitter/oxide interface. For high quality oxides, the minimum field is well over 7

MV/cm. For oxides grown on rough Si surfaces, such as polysilicon, F-N tunneling

has been seen for fields as low as 2 MV/cm. Electron injection by F-N tunneling can

alter the oxide charge in two ways. The first is the trapping of electrons by initially

neutral traps. The second way is by bond breaking, as the electrons are very energetic.
Interface traps and positive charge can be generated in this way. Using structures in

which the oxide electric field and electron current could be varied separately, DiMaria

[80] and Hsu et al [81] both found that the minimum electric field required for the
generation oxide damage (for thermal oxides) is 1.5 MV/cm.


5.2 Experimental Details


Buried oxide capacitors were formed using the quick-turnaround technique (see

Section 3.3). The samples investigated included the previously-discussed samples
annealed at 1285C for 6 hours. Two approaches to stressing were taken. The first
was ramp I-V measurements, where the voltage was ramped at a rate of 0.5 V/s. The

second approach was to apply a constant dc bias for 1 hour. The bias stresses were

done at voltages ranging from 50 to 150 V. In both cases C-V measurements were

taken immediately before and after stressing.








5.3 Results

5.3.1 Sample S5109

We begin a look at the results by examining the effects of high-field stress on
sample S5109. This sample had an implant dose of 1.8 x 1018 cm-2, and was annealed
at 1285C for 6 hours. In Fig. 5.2, typical ramp I-V measurements are shown for
S5109. Several aspects of the curves should be pointed out. First, for lower biases, a
shallow-slope region is seen. This corresponds to an ohmic region. Typical resistivities
are 1012 1013 Qf-cm. At higher biases, the current is seen to jump up. As will be
discussed below, this corresponds to the onset of F-N tunneling. Next, a big drop in
the current is seen when the voltage is ramped down. This is due to the trapping of
electrons in the bulk of the oxide. The trapped electrons generated an internal electric
field that opposes the applied field, increasing the voltage necessary to maintain a
given injection current. Finally, it is seen that the injected current density is much
higher for positive biases (which corresponds to injection from the S/O interface)
than for negative biases (injection from the F/O interface). We now discuss these
phenomena more fully.

A closer examination of the I-V curves in the low field (< 2 MV/cm) region shows
that curves exhibit ohmic behavior. The oxide resistivity can be calculated from the
slope of the I-V curve, and the result is that for the better oxides, p is around 1012
1013 P-cm. This is slightly lower than the value of 1014 1016 Q-cm expected for

thermal oxides. It is also seen in Fig. 5.2 that the oxide resistivity tends to increase
slightly after being stressed. This is due to the presence of trapped electrons in the
oxide, which oppose the applied field.

In Fig. 5.2, it is seen that after a certain voltage threshold, the current sharply
increases. The cause of this increase is the onset of F-N tunneling. To show that the
electron injection mechanism is F-N tunneling, we plot ln(J/E2) versus 1/E in Fig.
5.3. At higher biases, a straight line is seen, showing that F-N tunneling is indeed








the mechanism. From Fig. 5.3, one can estimate the threshold field for the onset
of F-N tunneling. The resulting threshold fields (E+N and E-N) are 2.6 MV/cm for
injection from the substrate and 2.9 MV/cm for the film. An additional difference is
that a much steeper slope is seen for injection from the S/O interface. These values
are much lower than those obtained with good quality thermal oxides. This is the
opposite of what one would expect, since from Eq. (37), the slope is proportional
to the effective barrier height. A greater slope would be expected for interfaces with
higher EFN. For example, good quality thermal oxides require fields of well over 7
MV/cm for F-N tunneling, and have a slope of 283 MV/cm. In Fig. 5.3, the slopes
are 36 and 19.5 MV/cm for positive and negative bias injection, respectively.

The next aspect of the ramp I-V curves to be discussed is the sharp drop of the
current during the ramp down portion of the curve. This effect is well known, and
is due to the trapping of electrons in the oxide. The energy barrier between the Si
and SiO2 conduction bands is insensitive to trapping at the Si/SiO2 interface, but
sensitive to trapping in the bulk. The presence of electrons trapped in the bulk of the
oxide creates an internal field opposing the applied field. Thus a higher applied field
is required to maintain a given current. Thus, using Fig. 5.2, one can calculate the
density of trapped electrons for both ramp stresses. The result is 1.7 x 1012 e-/cm2
for injection from the F/O interface and 1.6 x 1012 e-/cm-2 for injection from the
S/O interface. Note that while the injected current is sensitive primarily to bulk
electronic charge, C-V measurements are sensitive to the net oxide charge. Thus,
to analyze the total degradation of the buried oxide, C-V curves were taken before
and after the ramp I-V stresses. The results can be seen in Fig. 5.4. In the inset,
the corresponding values for net oxide charge and interface trap densities are shown,
as well as the bulk electron trapping. Several trends can be seen. The first is that
the degradation at an interface increases when the injection is from that interface.
However, irrespective of the polarity of the injecting bias, there is always significantly








greater degradation at the S/O interface than at the F/O interface. Since both Qot2
and ADit2 are very high, the bonding at the S/O interface must be weaker than at
the F/O interface. Another interesting aspect of the C-V curves is that despite the
high density of trapped electrons, the net oxide charge is still positive.

To examine the effects of high-field stress more closely, constant voltage stresses
were applied to the BOXCAPs for 1 hour. Several different voltages were studied,
for both positive and negative polarities. The results are summarized in Fig. 5.5. In
this figure, it is again seen that more damage is created at the S/O interface than at
the F/O interface for both bias polarities. For injection from the F/O interface, the
threshold voltage for generating damage at the F/O interface (Edr) is 2.8 MV/cm,
while the threshold for generating damage at the S/O interface (Eds) is 2.0 MV/cm.
Similarly, for positive stressing biases, the thresholds for generating damage at the
F/O and S/O interfaces are Ear = 2.8 MV/cm and Eds = 2.0 MV/cm. This difference
is significant, and strongly indicates that the bonding is different at the two buried
oxide interfaces. The bonding difference may be due in part to the large density of Si
precipitates in the buried oxide layer near the S/O interface. It is particularly inter-
esting that Ed& is below the threshold voltage for F-N tunneling from the film. This
indicates that a high percentage of the tunneling electrons are generating the defects,
implying a large cross section for defect generation. For both stressing polarities, a
rough correlation is seen between Qot and ADit for a given interface, although Qot
increases more rapidly than does LDit. For positive biases, the correlation between

Qot and ADit is seen at lower fields. At higher fields, however, ADit2 actually begins
to decrease. The maximum occurs around 2.5 MV/cm. For the F/O interface, at
higher fields, the net charge trapping becomes negative.

An interesting question is the correlation of the bias stress and irradiation stress
results. For this sample, significant densities of interface traps were generated under
both types of stress. However, a major difference is seen in the charge trapping








behavior. For irradiation under a 0 V bias, the trapping of positive charge was nearly
identical for both interfaces, with only a 10% difference. For bias stress, the S/O
interface has much higher positive charge densities than does the F/O interface. The
difference in the positive charge generation shows that the physical origin of the
defects are different.

5.3.2 Sample M10

A similar analysis was performed on sample M10. In Fig. 5.6, the ramped
J-V curves are shown. The curves are very symmetrical with respect to the stressing
polarity. This is surprising, since a row of oxide precipitates is seen adjacent to the
F/O interface, while the S/O interface is relatively smooth. In addition, the slope of
the curve after the onset of F-N tunneling is so shallow, that it is difficult to separate
it out from the ohmic portion of the curve. However, a drop in the current is seen
on the ramp down, indicating electron trapping. Furthermore, as seen in Fig. 5.7, a
linear J/E2 versus 1/E plot is obtained on the semi-log graph. From Fig. 5.7, it can
be seen that E+N = 2.6 MV/cm while E-N = 2.8 MV/cm. As might be expected from

the lower threshold voltage, a greater number of electrons are trapped for injection
from the substrate. As seen in the C-V curves in Fig. 5.8, this results in enhanced
degradation for positive bias injection. Surprisingly, more defects are generated at
the F/O interface for injection from the substrate than for injection from the film.
This is true for the S/0 interface also. A comparison of MI1O and S5109 shows that
although Qtl and ADit are of similar values for injection from the substrate, S5109
otherwise has greatly enhanced degradation, especially for the S/0 interface. This is
partly due to the previously discussed low damage threshold for the S/0 interface for
S5109. However, even for injection from the film, for which the electron fluence and
peak electric fields are similar for the two samples, S5109 has an order of magnitude
greater degradation. This shows that the multiple implant process greatly enhances
the hardness of the buried oxide.








Hour-long constant bias stresses were also performed on MI10, the multiple im-
plant sample. The resulting analysis of oxide charge and interface traps can be seen in

Fig. 5.9. The degradation is seen to be very symmetrical with respect to the stressing
polarity. The threshold for generating damage appears to be equal for both buried

oxide interfaces, and equal to around 2.8 MV/cm. However, after the onset defect

generation, the degradation of the S/O interface increases very fast with electric field,
for both bias polarities. For positive stresses, there appears to be an annealing out of
defects at the S/O interface for fields greater than 3.7 MV/cm. A major difference

between the ramp stress and the constant bias stress is the behavior of the inter-
face traps. For ramp stresses, roughly equal trap densities were generated at each
interface. With constant bias stress, however, ADit2 >> ADitI. It is also seen that
the generation of interface traps and net oxide charge tend to track each other well.
Again, comparing Fig. 5.9 to Fig. 5.5 shows that S5109 is much more degraded by
high electric field stress than MI10. In Section 4.4 it was seen that at 1 Mrad, MI1O
had much less positive charge trapping than S5109. Thus the degradation trends (as
a function of processing) are similar for both types of stress.

5.3.3 Sample S4419

Next, the analysis of the low-dose, single-implant sample, S4419, is discussed.
In Fig. 5.10, a typical J-E curve is shown for this wafer. Contrary to results for
the other samples, enhanced injection is seen for negative biases, corresponding to

injection from the film. Not only is the current significantly higher than for the other
SIMOX samples, but the F-N tunneling threshold voltage is clearly lower. This is

expected, as TEMs show this sample to have a very rough F/O interface. The large
voltage shift for negative biases also indicates a large number of trapped electrons. In
Fig. 5.11, the F-N graph is shown, again showing that the injection mechanism is F-N
tunneling. From this graph, EN and E-N are determined to be 2.6 and 1.8 MV/cm,
respectively. The corresponding pre- and post-stress C-V curves are shown in Fig.