Wireless embedded test for RF/Microwave IC

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Wireless embedded test for RF/Microwave IC
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Table of Contents
    Title Page
        Page i
        Page i-a
        Page ii
    Table of Contents
        Page iii
        Page iv
        Page v
    List of Tables
        Page vi
    List of Figures
        Page vii
        Page viii
        Page ix
        Page x
        Page xi
    Abstract
        Page xii
        Page xiii
    Chapter 1. Introduction
        Page 1
        Page 2
        Page 3
        Page 4
        Page 5
        Page 6
        Page 7
        Page 8
        Page 9
        Page 10
        Page 11
        Page 12
        Page 13
    Chapter 2. Embedded test for RF/microwave IC
        Page 14
        Page 15
        Page 16
        Page 17
        Page 18
        Page 19
        Page 20
        Page 21
        Page 22
        Page 23
        Page 24
        Page 25
        Page 26
    Chapter 3. RF RMS detector for embedded test
        Page 27
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        Page 29
        Page 30
        Page 31
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    Chapter 4. On-chip components of RF/microwave signal generation
        Page 53
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    Chapter 5. An integrated RF/microwave source and its applications for embedded test
        Page 99
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        Page 101
        Page 102
        Page 103
        Page 104
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    Chapter 6. Summary and future work
        Page 128
        Page 129
        Page 130
        Page 131
        Page 132
        Page 133
    List of references
        Page 134
        Page 135
        Page 136
        Page 137
        Page 138
    Biographical sketch
        Page 139
        Page 140
        Page 141
Full Text











WIRELESS EMBEDDED TEST FOR RF/MICROWAVE IC


By

QIZHANG YIN













A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


2005










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Copyright 2005

by

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TABLE OF CONTENTS
Page

L IST O F T A B L E S ......................................................... ... ................................................... vi

LIST OF FIGURES ...................................................................................................... vii

ABSTRACT.................................................................................. ............................. xii

CHAPTERS

1 IN T R O D U C T IO N ................................................................ ........... ............................. 1

1.1 Background ofRF/Microwave IC Test .............................................. ... ............. 1
1.2 Challenges to RF/Microwave IC Test................................................................ 3
1.3 Potential Solutions.......................................................................................... 6
1.4 Overview of Dissertation .................................................................................... 9


2 EMBEDDED TEST FOR RF/MICROWAVE IC................................ .......................... 14

2 .1 Introdu action ........................................................................................................... 14
2.2 RF Embedded Test Overview ............................................................. .......... 16
2.2.1 ADC/DSP-based Approach for RF Embedded Test.................................. 16
2.2.2 Loop-back Approach for RF Embedded Test............................................ 18
2.2.3 Alternate Test Approach for RF Embedded Test....................................... 20
2.3 Proposed Wireless RF/Microwave Embedded Test............................................. 22
2.3.1 Potential B enefits........................................................................................ 22
2.3.2 D esign Issues...................................................... ......................................... 25


3 RF RMS DETECTOR FOR EMBEDDED TEST............................ .............................. 27

3 .1 Introdu action ........................................................................................................... 2 8
3.2 Design Principle for RF RMS Detector................................ ................................ 29
3.3 Design of RF RMS Detector Circuit..................................................................... 31
3.3.1. The Input Interface Circuit........................... ............................................. 31
3.3.2. Squarer-divider and Low-pass Filter......................................................... 33
3.3.3. The Output Interface Circuit.................................................. .................... 35
3.3.4. E rror A analysis .......................................................................................... .. 36
3.4 Verifications of the RMS Circuit Design............................................................. 39
3.4.1. Analog Behavior Model of the RMS Circuit......................................... 39








3.4.2. Monte Carlo Analysis of the RMS Circuit Design................................... 40
3.4.3. Simulation Results of the Proposed RMS Detector.................................. 43
3.5 Test Setup & Measurement Results...................................................................... 45
3.5.1. Test Setup and RF Calibration................................................................... 46
3.5.2. M easurem ent R results ................................................................................. 50


4 ON-CHIP COMPONENTS OF RF/MICROWAVE SIGNAL GENERATION........... 53

4 .1 Introduction ........................................................................................................... 53
4.2 O n-chip A ntennas.................................................................................................. 53
4.2.1 Performance Issues of Various Antennas................................................... 54
4.2.2 Design Issues on On-chip Zigzag Dipole Antenna.................................... 58
4.2.3 Simulation Results of On-chip Zigzag Dipole Antenna............................ 60
4.2.4 Measurement Results of On-chip Zigzag Dipole Antenna........................ 64
4.3 High-speed CMOS Frequency Divider................................................................. 65
4.3.1 Injection Locking and Pulling of Oscillators ............................................. 68
4.3.2 An 11.2 GHz Injection-locked frequency divider...................................... 75
4.3.3 A 24 GHz Pseudo-differential Injection-locked Frequency Dividers....... 80
4.3.4 A 22.4 GHz Fully Differential Injection-locked Frequency Divider........ 81
4.3.5 A 24 GHz Direct Injection-locked Frequency Divider.............................. 84
4.3.6 A 10 GHz Flip-flop-based Frequency Divider........................................... 86
4.4 Investigation of Multi-tone Performance in Injection-locked Frequency Divider89
4.4.1. Theoretical Analysis of Multi-tone Performance in Injection-locked
Frequency D ivider............................................................................................ 90
4.4.2. Measurement Results of Multi-tone Performance in Injection-locked
Frequency D ivider............................................................................................ 94
4.4.3. Summary of Multi-tone Performance in Injection-locked Frequency
D iv ider .............................................................................................................. 9 8


5 AN INTEGRATED RF/MICROWAVE SOURCE AND ITS APPLICATION FOR
EM B ED D ED TEST .................................................................................................... 99

5.1 Introduction ........................................................................................................... 99
5.2 Design Approaches for On-chip Signal Generation........................................... 100
5.3 The Proposed 5 GHz Cascade RF/Microwave On-chip Source........................ 101
5.3.1 D esign Issues............................................................................................ 10 1
5.3.2 Sim ulation R results .................................................................................... 104
5.3.3 M easurem ent R results ................................................................................ 106
5.4 A 9 GHz single-stage RF/Microwave On-chip Source...................................... 112
5.5 Wireless Embedded Test for a 5 GHz Low Noise Amplifier............................ 112
5.5.1 Test Scheme for a 5 GHz Low Noise Amplifier...................................... 113
5.5.2 Low Noise Amplifier under Test.............................................................. 114
5.5.3 Theoretical Analysis of the Proposed Test Scheme................................. 117
5.5.4 Measurement Results of the Proposed Test Scheme................................ 120
5.5.5 Summary of the Proposed Test Scheme................................................... 126








6 SU M M A RY AN D FU TU RE W ORK ........................................................................... 128

6.1 Sum m ary ................................................................. ............................................. 128
6.2 Future W ork......................................................................................................... 130


LIST OF REFEREN CES ......................................................................... ......................... 134

BIO GRA PH ICA L SKETCH ................................................................... ........................ 139














LIST OF TABLES


Table page

3-1 Information for simulations with different crest factors ............................................ 45

4-1 Signal frequency versus wavelength in millimeters for different materials ............... 54

4-2 Parameters characterizing the performance of an antenna [Set97]............................. 55

4-3 Types of on-chip antenna m anufactured...................................................................... 61

4-4 Frequency dividers studied in this chapter................................................................. 68

4-5 Input locking range of the cascade frequency divider .vs. injection power ............... 88

5-1 Bias setup & input signals of simulations for the schematic in figure 5-2.............. 105

5-2 Input locking range of the cascade frequency divider .vs. injection power............. 109

5-3 Summary of measured results for LNA at 5 GHz.................................................... 116














LIST OF FIGURES


Figure Ease

1-1 C conventional R F IC testing............................................................................................. 1

1-2 Moore's law for test: fab .vs. test capital........................................................................ 3

1-3 Cost contributors to testing a part for various test times................................................ 5

1-4 Flow chart of dissertation............................................................................................. 13

2-1 Evolution of em bedded test.......................................................................................... 15

2-2 ADC/DSP-based embedded test structure................................................................... 16

2-3 Block diagram of loop-back approach for RF embedded test..................................... 19

2-4 Relationship between manufacturing process, DUT specification and test................ 20

2-5 Basic alternate test configurations for RF IC .............................................................. 21

2-6 Wireless embedded test setup ................................................................................. 24

3-1 Basic translinear loop used in RMS detector............................................................... 30

3-2 Input interface circuit and its matching performance.................................................. 31

3-3 Simulation results of input S-parameter ...................................................................... 33

3-4 Translinear loop with base-current compensation shown in the dashed region (CM:
current mirror) ........................................................................................................... 34

3-5 Frequency response at the input of the translinear loop.............................................. 35

3-6 The output interface circuit.......................................................................................... 35

3-7 The simulation results of RMS circuit with and without compensation subcircuit for 1
G H z sinusoid input signal................................................. ....................................... 38

3-8 Complete circuit diagram of the proposed RMS detector ........................................ 38








3-9 Analog behavior model of the RMS circuit: (a) test fixture of analog behavior model;
(b) comparison of simulation results between two models...................................... 39

3-10 Output distribution with process and mismatch variation: (a) with bias circuit; (b)
with ideal bias (sample size 100, room temperature)............................................... 41

3-11 Variation of output .vs. temperature.......................................................................... 42

3-12 Simulated relative errors for different waveforms .................................................... 43

3-13 Relative error versus crest factor ............................................................................... 44

3-14 The microphotograph of the RMS circuit.................................................................. 46

3-15 B asic R F test setup ..................................................................................................... 47

3-16 Measured one-port s-parameters at different frequencies......................................... 49

3-17 The de-embedded input impedance........................................................................... 50

3-18 Measured linearity error .vs. different input signals.................................................. 51

3-19 The upper measurement limit of the detector (measured at 1G Hz)......................... 51

3-20 Frequency response of the proposed detector............................................................ 52

4-1 Four common types of antenna: (a) slot antenna; (b) patch antenna; (c) dipole
antenna; (d) loop antenna.......................................................................................... 56

4-2 An on-chip zigzag dipole antenna................................................................................ 58

4-3 HFSS model of on-chip antenna.................................................................................. 60

4-4 Layout of a 2-mm on-chip zigzag dipole antenna....................................................... 60

4-5 Simulation results of input impedances of different on-chip antennas....................... 62

4-6 Simulation results of antenna gain of different on-chip antennas............................... 62

4-7 Antenna patterns: (a) antenna patterns in XY plane where the antenna locates; (b) 3-D
antenna pattern .......................................................................................................... 63

4-8 Fabricated 2-mm on-chip zigzag dipole antenna......................................................... 64

4-9 Test setup for on-chip antenna ..................................................................................... 64

4-10 Measured input impedance of on-chip zigzag dipole antenna.................................. 65

4-11 Measured antenna gain as a function of frequency................................................... 65








4-12 Frequency dividers: (a) injection-locked divider; (b) flip-flop-based divider; (c)
regenerative divider................................................................................................... 66

4-13 Injection pulling in an RF transmitter........................................................................ 69

4-14 Injection-locked oscillator m odel............................................................................... 70

4-15 Phasor representation of injection-locked oscillator model...................................... 72

4-16 An 11.2 GHz injection-locked frequency divider based on L-C oscillator.............. 76

4-17 The measurement results of variations of free-running frequency and output power
as a function of the bias voltage ............................................................................... 77

4-18 Oscillation frequency and output power as a function of varactor tuning voltage... 77

4-19 (a) Measured S1 parameters; (b)Locking range as a function of incident signal
power; (c) Relationship between minimum injection power and input frequency. 78

4-20 Measurement results of frequency sweep of oscillator as a VCO and a frequency
d iv id er ....................................................................................................................... 8 0

4-21 Pseudo differential injection-locked frequency divider............................................ 80

4-22 Measurement results of pseudo-differential injection-locked frequency divider: (a)
variation of free running frequency; (b) input sensitivity of frequency divider...... 81

4-23 A stacked fully differential injection-locked frequency divider (new topology)..... 82

4-24 Photomicrograph of the proposed stacked fully differential injection-locked
frequency divider ...................................................................................................... 82

4-25 Measurement Results of stacked fully differential injection frequency divider: (a)
variation of free running frequency; (b) input sensitivity of frequency divider...... 83

4-26 Simulated phase noise performance under the effect of the injected phase distortion
caused by different speed of PMOS and NMOS tail transistors.............................. 84

4-27 A 24 GHz directive injection-locked frequency divider........................................... 85

4-28 Fabricated direct injection frequency divider............................................................ 86

4-29 Measurement results of direct injection frequency divider: (a) variation of free
running frequency; (b) input sensitivity of frequency divider ................................. 86

4-30 A 10 GHz flip-flop-based frequency divider............................................................. 87

4-31 Photo micrograph of the fabricated flip-flop-based frequency divider..................... 88








4-32 Measurement results of self-oscillating frequencies of the flip-flop-based frequency
divider with different power supply......................................................................... 89

4-33 Measurement setup for multi-tone performance of injection-locked frequency
d iv id er........................................................................................................................ 9 4

4-34 The injected two-tone signal to the frequency divider.............................................. 95

4-35 The resulted output spectrum of the frequency divider due to the injected two-tone
sig n al ......................................................................................................................... 9 5

4-36 The output spectrum of the divider when two-tone input has the same amplitude.. 96

4-37 The spectrum of the injected AM signal to the divider............................................. 97

4-38 The output spectrum of the divider due to the injected AM signal in figure 4-37 ... 97

5-1 Block diagram of on-chip signal generator................................................................ 101

5-2 The schematic of two cascaded frequency dividers with output buffers (LCFD: LC-
based VCO frequency divider; SCLFD: source-coupled logic frequency divider)103

5-3 Simulation results of the schematic in figure 5-2; (a) input and output transient
waveforms; (b) frequency harmonics of output signal; (c) phase noise performance
of output signal.................................................................... .................................... 10 5

5-4 The photomicrograph of the circuit shown in figure 5-2 connected with an on-chip
anten n a.............................................................................................. ................... .... 106

5-5 The output signal of the cascade frequency divider in frequency domain when the
second stage is unable to divide the first stage output signal................................ 107

5-6 Harmonics of two-stage frequency dividers with the signal generated by the first
stage div ider ............................................................................................................ 108

5-7 (a) Output signal of 5 GHz on-chip signal source; (b) 5 GHz output signal of external
test signal generator ................................................................................................ 110

5-8 Measured phase noise using spectral analyzer: (a) signal generated by on-chip source;
(b) signal generated by external source .................................................................. I11

5-9 (a) Output signal of 9 GHz on-chip signal source; (b) 9 GHz output signal of external
test signal generator ................................................................................................ 112

5-10 A new embedded test scheme for LNA measurement............................................ 113

5-11 (a) The schematic of LNA under test. (b) The photomicrograph of the fabricated
LN A under test ........................................................................................................ 114








5-12 The measured S-parameters of a 5 GHz LNA......................................................... 115

5-13 1-dB compression point of 5 GHz LNA.................................................................. 115

5-14 Noise figure and available power gain versus frequency........................................ 116

5-15 R F peak detector....................................................................................................... 117

5-16 The equivalent network representation of the LNA test scheme............................ 118

5-17 Microphotograph of the on-chip LNA test structure............................................... 120

5-18 Measured output signals of three on-chip detectors................................................ 121

5-19 Derived s-parameters of the LNA from measured output voltage of detectors...... 121

5-20 Thevenin equivalent circuit for LNA input............................................................. 123

5-21 V oltage gain of LN A under test............................................................................... 123

5-22 The adjustable power range of LNA's input and output......................................... 125

5-23 LN A linearity from embedded test.......................................................................... 126

6-1 One possible implementation of wireless embedded test scheme for LNA ............. 132














Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

WIRELESS EMBEDDED TEST FOR RF/MICROWAVE IC

By

Qizhang Yin

December, 2005

Chair: William R. Eisenstadt
Major Department: Electrical and Computer Engineering

The explosive growth of RF/Microwave IC industry has made the testing of

RF/Microwave applications very challenging, particularly under the constraints of high

quality and low price. Embedded test is a potential solution to face the challenges posed

to RF/Microwave IC test, in which low-cost testers, already on the factory floor, can be

applied to perform RF/Microwave ICs testing with additional design for test (DFT)

circuitry integrated with the IC under test, instead of costly advanced ATE system with

RF functions.

The fundamental idea is to move very high-speed test functions on-chip, thus

reducing the requirement and the cost of the external ATE. This move, however, is not

that simple, and still in the development stage.

The basis of the proposed wireless embedded test is an off-wafer (chip) tester plus

some test circuitry integrated with the device-under-test (DUT). The on-wafer (chip) test

circuit receives a signal from the external signal source, modifies it into a suitable test

stimulus for the DUT, and then extracts the useful information from the response of the








DUT into baseband signals, which are finally transmitted back to the external tester. The

external tester and antenna are needed for sending the initial RF signals without any

physical interconnection to the DUT and receiving the low-speed test response from the

DUT by low-frequency wire connections. Thereby, the necessary on-chip components of

the proposed embedded test are an antenna, power and high frequency rectification and

sensing circuitry.

First, the design and implementation of an RF RMS detector for embedded test is

presented, which is based on a bipolar translinear design methodology. Then single-layer

and multi-layer on-chip antennas with different lengths are developed, the performance of

which will be compared with the measurement results. Next, CMOS frequency dividers

are reviewed, including theoretical analysis of injection locking performance and designs

of injection-locking frequency dividers and flip-flop-based frequency divider at 12 GHz

and 24 GHz. With the designed on-chip antenna and frequency dividers, a simple

microwave test source is built. Finally, the application of the test source is studied and a

wireless embedded test scheme for LNA is proposed.













CHAPTER 1
INTRODUCTION

1.1 Background of RF/Microwave IC Test

Usually RF/Microwave measurements can be categorized into two classes, scalar

tests and vector tests. Scalar tests are concerned with measurement of signal amplitudes,

but not phase. Examples of scalar tests are gain, spurious and harmonic tests, linearity,

and noise figure. In contrast, vector tests involve measurement of both magnitude and

phase. Examples include scattering or S-parameters, voltage standing wave ratio (VSWR)

and group delay. Some examples are shown in figure 1-1.







DUT


Figure 1-1. Conventional RF IC testing

Before 1983, high-speed, integrated circuit (IC) designers could only speculate as

to why a particular design worked. The true electrical performance of these tiny

microwave circuits was impossible to measure at the wafer level. With the development

of high-performance and high-frequency on-wafer probes and probe stations, design

engineers could test and characterize their circuits on-wafer, before the ICs were diced

and packaged. Since then, RF measurement systems evolved from rack-and-stack

systems to extremely complex, million dollar Automatic Test Equipment (ATE). RF ATE








is actually several RF instruments rolled into one--signal generators, power meters,

spectrum and network analyzers and noise figure meters, that can provide a much higher

throughput capability than traditional rack-and-stack systems. But on-wafer testing in this

way is not only expensive but also time-consuming.

Since the early days of silicon, wafer-level testing has been used to prune away

catastrophically defective dies before packaging. Since all dies that pass the wafer-level

testing are again tested thoroughly after packaging, the cost of wafer-level testing needs

to be extremely low. The high cost of RF testers coupled with the difficulty of measuring

RF signals has limited wafer-level testing to digital circuits only. Thus, during wafer-

level testing, the RF path is completely bypassed.

With improvements in manufacturing technology, and relaxed performance

requirements of some application domains, leading to easier design processes, the cost of

manufacturing RF dies has appreciably reduced. However, each manufactured die which

passes the wafer-level digital testing, and whether or not there is any defect in its RF

path, still needs to be packaged and fully tested, the cost of which has not reduced at the

same rate as design and manufacturing. As the packaging cost becomes an appreciable

component of the overall cost and the yields are lower as a result of increased IC

complexities, bypassing the RF path during wafer-level testing proves to be an inefficient

method in terms of the overall cost. Plus, there are new configurations of RF/mixed-

signal IC system in a package which need to be tested prior to assembly. However,

utilization of existed RF testing methods on wafer-level testing faces many challenges as

well.









1.2 Challenges to RF/Microwave IC Test

Over the past decade, it has been observed that the radio frequency (RF) wireless

market expanded to unimaginable size. Devices such as pagers, cellular and cordless

phones, cable modems, and RF ID tags are rapidly penetrating all aspects of our lives,

evolving from luxury items to indispensable tools. Meanwhile, due to the increasing

demands for broadband wireless communication, higher frequency bands such as

microwave and millimeter-wave where there is sufficient spectrum are of growing

interest. The recent rapid development of Si-based CMOS devices makes it possible to

implement low cost and high integration circuits at such high frequencies [YU04,

Gua04]. Simultaneously, the integration density and complexity of these devices increase

with customers' demands in functionality.

This explosive growth of wireless communication industry has made the testing of

RF/Microwave applications very challenging, particularly under the constraints of high

quality and low price.

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Figure 1-2. Moore's law for test: fab .vs. test capital








The dominant challenge is testing cost. In the past, RF/Microwave applications

have imposed stringent performance requirements on the design, manufacturing and

testing, which led to high overall costs. And despite the high production cost, high market

prices could still provide adequate profitability for them. However, with increasing

competitions in traditional applications, such as cellular phones, and emerging

application domains, such as sensor networks, profit margins are decreasing and the cost

pressure becomes prohibitive. And the cost dynamics for ICs are also changing. Before,

RF design and silicon manufacturing have contributed the highest components to the total

cost, thus drawing little attention to testing. With recent improvements in manufacturing

technology, and relaxed performance requirements of some application domains, leading

to an easier design process, the cost of manufacturing RF dies has appreciably reduced. It

can be seen that the manufacturing cost per transistor indeed follows Moore's Law,

which reduces the cost per IC even as functionality and performance increases, while test

costs don't scale with Moore's Law, therefore becoming a bigger factor in the total

manufacturing cost of a chip. Figure 1-2 shows a plot extrapolated from the 2001

International Technology Roadmap for Semiconductors (ITRS) [ITR01]. It depicts the

capital costs for chip fabrication versus the capital costs for manufacturing test,

normalized per transistor. The top curve shows the consistent reduction in chip

fabrication cost per transistor that in turn drives the continued expansion and evolution of

the semiconductor business. The bottom curve indicates capital expenses for IC test have

been essentially flat per transistor. But this does not mean IC test really has been standing

still for the last 20 years, rather the historical test trend exhibits the tremendous amount of

effort and technology in test to keep up with the continued increases in IC device








performance and complexity. Even so, the test capital per transistor still trends to rise as

in the plot. If not addressed, the data in Figure 1-1 would project the industry would reach

a point in several years where the general cost of testing ICs exceeds the cost of

fabricating them.

Associated with testing cost is testing time. Nowadays the commercial wireless

industry demands extremely low cost RF components, and a key contributor to the cost of

RF ICs has been the test time per part. For an ATE system, total test time includes Tester

Capability/Speed (Electrical Test Time), Handler/Tester/Controller Communications

Time, Handler Capability and Index Time of Handler. As an example, figure 1-3 shows

the relationships between test cost and test time; the information source is from IBM test

development group [IBM02]. The left plot illustrates the test cost for a $2M tester and the

right plot illustrates the test cost for a $100K tester. Both plots show test cost/part is

almost entirely a function of test time.

Test Cost vs Test Time $2M Tester Test Cost vs Test Time $100K Tester

S20 10
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Figure 1-3. Cost contributors to testing a part for various test times

Another challenge is visibility and accessibility in the testing of ICs. Increasing

wafer size with decreasing feature size, coupled with more complex fabrication

processes, causes the characteristics of the devices-under-test (DUTs) immeasurable or








even inaccessible using existing testing methods, which is especially significant for

RF/Microwave ICs. For instance, at frequencies above 5 GHz, it is hard to tell the value

of the signal injected into the DUT from external ATE. At the same time, as density and

complexity of circuits increases, the number of input/output pins remains relatively

constant, thus the need for added testing pads and increased placement precision of

testing probes is more and more demanding and expensive.

In addition, the fault model paradigm, extremely successful in digital tests, has not

been standardized for analog RF tests and the fall-back position is still specification-

based tests, which were developed for stand-alone components and do not really fit the

system test protocols. New paradigms are being investigated but encounter strong

resistance in applications since these new techniques have not been correlated to existing

techniques to convince the industry of the test robustness and quality.

Clearly, it is important to look for innovative ways to circumvent these challenges

and make test techniques catch up the pace of RF/Microwave ICs' performance.



1.3 Potential Solutions

While the testing requirements and procedures for various RF/Microwave ICs

differ widely, all are tested at very high frequencies, typically at 900 MHz or higher.

Potential solutions to response the challenges to RF/Microwave ICs' testing can be

categorized as follows:

Test cost and time reduction for RF/Microwave ICs can fall into three techniques:

test less, test earlier and test faster [Eri98]. Test less exploits redundancy among the tests,

like between the wafer level tests and final tests. With test earlier, package scrap is

reduced by performing as many tests on-wafer as possible. Final test is still necessary, but








often limited to continuity tests for high yield production lines. Test faster involves the

use of test parallelism or high-throughput testers.

To address the limitation of visibility and accessibility in the testing of ICs, the

simplest approach is to use a multiplexer to add test points at the I/O of the analog

subsystem to be tested. This methodology is originally proposed by Wagner [Wag88],

and is still commonly used in industry. This technique permits the monitoring of one

signal at a time but degrades the test accuracy as the number of test points is increased

and at higher speed operation of the DUT because of the capacitive load of the

multiplexers

IEEE1149.1 (JTAG) boundary-scan standard provides an effective means for test-

access to internal modules of the DUT for testing static faults in digital ICs. Its JTAG

counter part in mixed-signal testing, the IEEE P1 149.4 standard [IEEE99], extended to

cover RF/Microwave devices has been discussed in many different publications [Heu99,

Alt03]. In these papers, the boundary-scan standard provides only an indirect testability

to the RF devices, which limits the resolution of RF diagnostics. To provide a structural

test solution for RF circuits and increase the resolution of RF diagnostics, the boundary

scan standard should be directly implemented on RF input and output ports. However,

there are many difficulties to perform boundary-scan tests on RF pins. The main reason is

that adding additional test circuitry to the parasitic sensitive RF lines is not trivial and can

easily degrade the RF performance of the RFICs. Though some improvements have been

made [Hua04], more study is needed for the on-chip extension of the boundary-scan

standard.








Fault-based test development approaches have flourished for years, mostly from

academic publications. The extension of digital fault models to analog fault models has

created several new fault classes [Som97], most notably the catastrophic fault models and

the parametric fault models. Test techniques based on these models have been developed

and are strongly biased toward the re-use of existing tests and seek to validate them based

on a fault coverage measure defined and computed based on a selected fault model.

These developments to date have not been in frequent use by industry since there is no

agreement on an adequacy and usefulness of fault models. The correlation with

specification-based tests, critical to industry acceptance of new techniques, has not been

demonstrated and viable analog fault models have yet to be discovered.

Another potential solution is the use of embedded test, in which low-cost testers

can be applied to perform RF/Microwave ICs testing instead of costly advanced ATE

system with RF functions. Actually, embedded test is comprised of two distinct test

approaches: external ATE and conventional DFT. This test integration facilitates the

chip, board and system level test, diagnosis, debug and repair. Typically, embedded test

is implemented in two components [Zor02]: user configurable test IP (intellectual

property) in the form of design objects delivered as Register Transfer Level (RTL) soft

cores; and a suite of test automation tools to automate generating, integrating, analyzing,

and verifying test and diagnostic patterns. The fundamental approach is to move very

high-speed test functions on-chip, thus reducing the requirement on and the cost of the

external test. This move, however, is not that simple, and still in the development stage.

The use of embedded test can improve circuit controllability and enhance circuit

observability. Given reliable embedded test, the time spent in ATE can be reduced,








thereby lowering the cost per chip. With embedded test, comprehensive fault coverage

with minimal external intervention is enabled a benefit that extends not only to

production test but also to ongoing field maintenance. During production, an ATE can

activate the test sequence and read the pass or fail result. For device debug, design tools

interact with the DUT to diagnose the failure quickly. The bigger advantage is that circuit

functionality can be tested and validated throughout the lifetime of the device. This

includes debugging remote systems that are in the field.



1.4 Overview of Dissertation

This dissertation concentrates on the design issues of various components in a

proposed wireless RF/Microwave IC embedded test vehicle, as well as the evaluation of

the system feasibility, which serves as the first step for implementing future low-cost

RF/Microwave test wirelessly. The graphic overview of the whole work is shown in

figure 1-4.

In chapter 2, some features and trends of current embedded test are first introduced,

followed by several example RF/Microwave IC test architectures. A new wireless

RF/Microwave IC embedded test vehicle is then proposed, which include an on-chip

microwave antenna, analog/digital dividers and RF detectors. As an application, the

proposed test structure is used to test a low-noise-amplifier (LNA), all of which are

integrated on the same chip.

A new RF RMS detector with very wide bandwidth is presented in chapter 3, which

is based on the dynamic translinear principle and integrated in a BiCMOS process. The

main computation is carried out in the current domain and errors due to finite transistor

gain are compensated in a novel circuit structure. Monte Carlo analysis is used to check








the design for the process and mismatch variations. To make the circuit suitable for

voltage processing, both input and output interface circuits are included. Test setup and

measurements on a prototype chip demonstrate the practicality of the circuit for on-chip

embedded tests.

A critical component of a wireless test system is the antenna, which acts as a

receiver of external test signals. The implementations of various-length on-chip zigzag

dipole antennas are discussed in the first part of chapter 4. The designed antennas can be

considered as transducers between the incoming electromagnetic (EM) wave and the

current and voltage within the subsequent circuitry. Since they are integrated with other

circuits on the same chip and for the purpose of embedded test, these antennas should be

area-efficient, and meanwhile keep the antenna gain maximized. Both simulation results

with EM simulation tool HFSS and measured results of on-chip antennas are evaluated

and demonstrate the plausibility of small on-chip antennas as a receiver for external test

signals.

The second part of Chapter 4 demonstrates the designs and measurements for

different types of frequency dividers. The analog dividers are designed using the

phenomena of injection pulling and locking in an LC-based oscillator, so-called ILFD.

Three ILFDs were implemented with 0.1 8um technology. Two of them utilize all NMOS

differential LC VCO with indirect injection topology and resonate at 12 GHz and 6GHz

respectively. The third one employs CMOS differential LC VCO with direct injection

topology, the free running frequency of which is 12 GHz. A CMOS source-coupled logic

(SCL) frequency divider is implemented with the same technology, which can operate








within a wider bandwidth than the analog ones. The performance difference on different

types of dividers is shown through the simulations of each divider.

The generation of an on-chip RF/Microwave test signal source is developed in

chapter 5, which utilizes the on-chip antenna and frequency divider described in the last

two chapters. The on-chip passive antenna receives the incoming microwave signal with

little distortion and passes the signal into the input of the frequency divider. The

frequency divider then divides the frequency of the signal into the desired band. Since the

frequency divider is implemented based on the principle of injection locking. The phase

noise performance of the generated on-chip signal is comparable to that generated by the

external tester. This solves the problem existing in the wired test system that test signals

at or above 5 GHz are severely degraded when they are passed onto the DUT from the

tester. The future measurement results will prove the realizability of such an on-chip

RF/Microwave signal source.

The goal of this work is to demonstrate the operation of RF/Microwave wireless

embedded test and evaluate its feasibility. Apart from the generation of on-chip

RF/Microwave test signal source, Chapter 5 displays an application of the proposed

wireless RF/Microwave embedded test. In this demonstration, an LNA, which is the most

common and key component in RF front-end, serves as DUT and is integrated with the

embedded test function circuits discussed in the previous chapters. A test signal is

injected from the on-chip signal source, and the RF detectors sense the signals from the

DUT and output the dc signals to the external low-cost ATE. With this method, the

figures of merit characterizing the LNA can be accurately obtained, which include

voltage gain, transducer gain, input impedance and noise figure. Compared to





12


conventional LNA tests, this prototype scheme of LNA embedded self-test is simple and

cost-effective. It is worth exploiting further in the future.

Finally, chapter 6 summarizes the overall work in this dissertation and concludes

the feasibility of the wireless RF/Microwave embedded test and future work is suggested.















































Figure 1-4. Flow chart of dissertation


Chapter 2 Embedded Tests for RF/Microwave IC

Existed embedded test architectures

Proposed embedded test architectures


Chapter 5 On-chip Test Signal Generation &

Application of Wireless RF/Microwave Embedded Test


Chapter 3 RF RMS Detector

OUT= n2) ( DUT
<> is average operator




Chapter 4 On-chip Components of Microwave Signal Source


On-chip Antenna Frequency Dividers


w __.tI~-2


I


I I


a












CHAPTER 2
EMBEDDED TEST FOR RF/MICROWAVE IC

2.1 Introduction

Embedded test as a potential solution to face the challenges posed to

RF/Microwave IC test is introduced in chapter 1. Embedded test proposes a flexible

paradigm for RF/Microwave test while providing scalability with advances in design.

Usually embedded test includes designing test hardware on-chip, supporting the test

hardware with design for testability (DFT) features and designing in standard

communication protocols that allow an external tester to control the test procedure with

low-bandwidth access and hence, lower cost external testers. Recent studies [Dab03,

Haf03, Cha04, Eis04 and Sel04] have demonstrated the ability to measure RF/Microwave

circuits via compact on-chip test structures and a low-cost external tester.

With a typical RF ATE, which may include functions of DC bias, DC

measurement, RF power meter, network analyzer and etc., RF/Microwave test signals are

being transported across the package to IC boundary for excitation or measurement.

Unfortunately, at frequencies above 5 GHz, signals that pass between the ATE system

and the DUT can be significantly degraded. Variability of mechanical pogo-pin

placement in the connections to IC packages, load-board signal loss, and package and

load-board crosstalk can create large uncertainties in the amount of power delivered from

the IC tester into the IC. In the future, required guard-banding for the IC tester signal

connection uncertainty may create significant rejection of good ICs during manufacturing

test. Finally, the signaling specifications will be increasingly complex and transmitter








output spectral requirements more stringent, which will stretch the manufacturing test

development time [Eis04]. An alternative to this approach is to integrate some additional

circuitry functioning as RF exciting or measuring with the DUT or reuse some

components already available in the DUT. In this way, high frequency communication is

constrained on-chip and eliminated between the DUT and the external tester. And instead

of a costly RF tester, a low-cost external tester can be employed to monitor low-speed

communication taking place between it and the built-in circuitry inside the DUT, as

shown in figure 2-1. If the effects of the additional circuitry on the DUT, such as device

mismatching, parasitic loading and more area requirement, can be negligible, low-cost

RF/Microwave test is plausible.



Cosrly Lo\o -cost
RF ATE | -- \ATE


Embedded test circuitry
DUrT




High-speed connection Low-speed connection

Figure 2-1. Evolution of embedded test

The rest of this chapter is organized as follows: in section 2.2, some recent work on

RF embedded test are reviewed, including the trade-offs and design issues of these

approaches; section 2.3 describes the proposed wireless RF/Microwave embedded test.








2.2 RF Embedded Test Overview

2.2.1 ADC/DSP-based Approach for RF Embedded Test

Motivated by analog integration trends and the increasing difficulty in transferring

test information using a conventional setup, an ADC/DSP-based embedded test is

adopted by Hafed and Roberts [Haf03], in which both a waveform generator and a

waveform digitizer are integrated in the form of a D/A converter and an A/D converter,

respectively. Thereby, test information can be available in the digital domain for further

processing on or off the IC.

Figure 2-2 illustrates a block diagram of the components comprising the

ADC/DSP-based embedded test. It consists of two one-bit memories (or sequential-

registers), some analog structures, and a multi-bit memory for output data storage. The

memory on the left part of the figure consists of two bit stream generators, one for ac

stimulus generation, and one for dc signal generation. The latter is combined with the

analog comparator to perform multi-bit resolution digitization.



/> : ... CUT ,



-- - ---



/ -.-.-.-- ---- -
DAWG i-^ j^^^ : L1


Figure 2-2. ADC/DSP-based embedded test structure








The ac waveform generator synthesizes test frequencies using a short repetitious

sequence of digital bits. This sequence is chosen to approximate the output of a 1-bit

sigma-delta modulator. Specifically, a finite duration of the output of a software sigma-

delta modulator that is driven by a periodic input is captured and periodically repeated

on-chip to approximate the infinite-duration sigma-delta modulator output.

On-chip waveform digitization is achieved using the second bit stream generator

(the dc generator), a passive on-chip RC filter, and a voltage comparator. Multi-bit

digitization using such limited hardware is achieved by making use of the periodicity of

the input signal. In this approach, the way the signal is digitized is as follows. All

samples of a unit test period are compared to a single quantization level, say 0 V, set by

the dc voltage generator. Once all incoming samples are compared to this level, the dc bit

stream generator is commanded to increment its output to the next quantization level, and

the process repeats. The encoding method used in the dc bit stream generator is also

based on approximating sigma-delta modulated streams. Specifically, the one-bit nature

of the sigma-delta streams significantly reduces sensitivity to process mismatches and

preserves linearity. Similarly, drifts in RC component values do not alter the average

output of the filter. It is recognized that temperature as well as aging will affect the

proposed circuits in much the same way that they would affect external measurement

instruments. Such effects are generally minimized using a controlled test environment

and/or calibration.

The capture algorithm relies primarily on the proper synchronization with the

excitation system. Such synchronization is achieved in this system, which fixes the

stimulus and capture sample rates in order to achieve a coherent measurement setup.








Processing of the comparator output is done using a multi-bit memory (Figure 2-2)

that is the same length as the length of the unit test period and that is initialized to zero at

the beginning of a measurement run. This memory can be integrated on-chip or in

software, depending on the application. For each comparison pass, the bit stream

generators continuously circulate their contents to output the analog stimulus and the

reference level, respectively. For each circuit response sample, the corresponding

memory location is incremented or left unchanged, depending on whether the comparator

output (for the current dc level) was 1 or 0. At the end of the digitization process, each

memory location will contain an integer count representing the quantization level for the

corresponding sample (i.e. a thermometer code).

The benefits from this approach include the elimination of long interconnect

problems, less capital cost and high fidelity measurement because of digitalization of test

signals. In addition, a memory-based approach allows for faster design times, robustness

to process variation, and scalability. But to a large extent, the bandwidth of this test

structure is limited by the capability of its A/D and D/A converters.

2.2.2 Loop-back Approach for RF Embedded Test

For wireless communications and portable devices, current test techniques are often

based on some kind of loop-back approach, in order to reuse the transmitter or receiver

section.

A typical loop-back test block diagram of a present RF transceiver is shown in

figure 2-3 [Dab03]. All the functional blocks except of the power amplifier (PA), RF

filter and diplexer with antenna are integrated on one chip. To enable the embedded test,

the test amplifier (TA) has been added to the chip. With this approach, the on-chip RF








front-end is targeted rather than the complete transceiver, for which a set of detailed tests

is prescribed by standards that a vendor must comply with.



RFFilter Down- LP |



A A Ctrl-2 I LO r- D ,,
AX Z r .....
.T~est Tes \

_____ ___ LUp- Lp h DA
---- -- --- Conv~erter I Filter EB_____



Figure 2-3. Block diagram of loop-back approach for RF embedded test
In the figure, the base-band processor serves both as a stimulus generator and

response analyzer. The test loop comprising the transmitter (Tx) and receiver (Rx) path is

closed by TA. A possible local test loop aimed at DA/AD converters is marked with the

dashed arrow (filters can be included too). This structure requires additional multiplexers,

not shown in the figure. It is assumed that testing the DA/AD converters precedes the RF

front-end test. The TA is a low power variable gain amplifier, which is powered down in

normal operation mode, and should not affect the transceiver performance. The frequency

synthesizer (LO) is involved as well, and in test mode it must support Tx to operate at the

carrier frequency of the receiver (that might be different from the normal mode).

When the loop-back test targets the receiver blocks, the control path traces through

Tx and TA. The frequency synthesizer (LO) is involved as well. The stimulus for testing

Rx blocks has three attributes: Base band digital content (pattern), frequency of RF

carrier, and RF carrier level. Different functional blocks are involved with those






20


attributes. When the loop-back test aims at the transmitter blocks, the control path is very

short, but the observation path traces through TA and Rx. Also LO is involved. In this

case, the carrier level is not the stimulus attribute, but is important to retrieve the

response. The distinction between control path and observation path is important during

verification of the test stimuli in order to target a faulty block in the loop (fault

simulation).

The above loop-back technique makes use of the "duality" present in the

transceiver system. The output of a receiver is analyzed by its dual transmitter and vice

versa. However, test interconnections require additional components to balance power

levels and to overlap the frequency bands of two subsystems. Furthermore, consecutive

stages mask fault effects, and during testing, the loop can only be addressed as a whole,

hence the fault diagnosis is a hard problem.

2.2.3 Alternate Test Approach for RF Embedded Test

4
aA *t d '@ ",' >' ... *' ,, .1 '. iam s

I

Re io f" I, '.,-; -. ,"* *' 0 *,rr; ;*. .- /j, ,.r. ~ i+ :" : I
,a ,rw d t ic' i a,.l', U ,i L' ,, r. |. ,,..iv
*, .-S ". ,









Figure 2-4. Relationship between manufacturing process, DUT specification and test
-- Iwfit




p >4



4 Ecrjbiu-aftro apac 1 4; dfeiau hirnrt E~c '





Figure 2-4. Relationship between manufacturing process, DUT specification and test








The basic idea behind alternate test is that the DUT performance is related to (and,

in turn, is affected by) process variations, and that it is possible to predict the DUT

performance using additional tests that are much "cheaper" to perform than tests that

explicitly measure the performance specifications.

As shown in figure 2-4 [Cha04], a mapping function f: M->S can be constructed for

the circuit specifications S from all the measurements in the measurement space M using

nonlinear statistical multivariate regression. Given the existence of the regression model

for S, an unknown specification of a DUT can be predicted from the measured data

The objective of the alternate test methodology is to find a suitable transient test

stimulus and to predict circuit specifications accurately from alternate test response. The

methods are targeted at low-cost testing of RF front-ends and front-end chips, such as

LNAs, power amplifiers, attenuators and mixers. Different type of test stimuli can be

used in different cases.



\I .',l K ILX'et2 I Ili- DU
Test DDI
S ign-alt ~riu~



Figure 2-5. Basic alternate test configurations for RF IC



The basic alternate test configuration for testing RF IC is illustrated in figure 2-5.

The concepts of modulation and demodulation are applied to translate a transient base

band test stimulus to the RF spectrum for applying to the DUT, and the DUT response

back to base band signature. The low-cost tester supplies a carefully designed base band

test stimulus and the stimulus is then modulated onto a carrier via mixer 1. This








modulated carrier is the test input signal to the DUT. The response of the DUT is

demodulated to base band and sent back to the external test. The design of the test

stimulus (base band + carrier) is done in such a way that the performance variations in

DUT cause significant changes in the response see by the tester.

The main feature of this test approach is that multiple DUT specifications can be

measured using a single acquisition and a single test configuration. As testing is

performed on a low-cost ATE using an extremely short duration test stimulus,

improvement in test throughput and test costs of RF circuits is made possible. But with

the need of additional resources, like mixers or A/D converters, area overhead is

increased. The quality of RF test stimulus may be degraded because of the modulation

and demodulation involved with mixers.



2.3 Proposed Wireless RF/Microwave Embedded Test

2.3.1 Potential Benefits

Given the distances that signals have to travel in a conventional measurement

setup, usually in the range of 10 cm ~ 100cm, and at high frequencies, for instance, at 1

GHz, the wavelength of a signal is only 3 mm in air, transmission line theory becomes

more effective than lumped-circuit theory in describing the effect of the interconnect

between the device under test and the measurement instruments. The issue in high-speed

measurement becomes that of interconnect uniformity (matched impedances throughout

signal paths). Ensuring that the measurement results exclude the transmission properties

of the interconnection is generally rather costly and requires a significant level of effort

and expertise. For example, a common approach is to measure the scattering parameters

of the interconnection and to formulate mathematical models to decouple the response of








the interconnection from the actual response of the device being measured.

Unfortunately, this is becoming extremely cumbersome as test path calibration accuracy

is no longer simply determined by the instrument alone but rather by the whole

combination of device under test, instrument, and the connection media in between.

Embedded test is one way to circumvent this bottleneck of RF/Microwave IC test, in

which the external tester controls the generation of on-chip test stimulus by baseband

communication and the high frequency response from DUT is converted to baseband

signals on-chip and then sent to the external tester. Hence, to handle RF/Microwave test,

embedded test still presents the following major challenges:

1) on-chip generation of high-quality and high speed test signals using low-cost
hardware;

2) high-speed on-chip response acquisition followed by analysis or response
compaction.

Through the discussion of different embedded test structures in section 2.2, it can

be seen that to satisfy the above two challenges is still a tough job. With ADC/DSP-based

approach, the speed of test stimulus is limited by the capability of mixed-signal circuitry.

It is nearly impossible to generate a high-quality and a high speed test signal with a

simple area-effective on-chip ADC. Similarly, the compact on-chip modulation and

demodulation process in alternate test can not guarantee the quality of signals as well.

The loop-back approach is constrained by the type of DUT and can not do fault diagnosis

locally. Therefore, the opportunity for a wireless embedded test methodology becomes

evident.

As shown in figure 2-6, the basis of the wireless embedded test is an off-wafer

(chip) tester plus some test circuitry integrated with the DUT. The on-wafer (chip) test

circuit receives a signal from the external signal source, modifies it into a suitable test








stimulus to DUT, and then extracts the useful information from the response of the DUT

into baseband signals, which are finally transmitted back to the external tester. The

externmi tester Pd nrtera a'g erlr fnr fn eT the jnitiq! P1P piti, .;+^r,,+

interconnection to the DUT and receiving the low-speed test response from the DUT by

general wired connections. Thereby, the necessary on-chip components of the proposed

embedded test are an antenna, power and high frequency rectification and sensing

circuitry.





Test Unit -
&
Off-vvafer
antenna On-chip Antenna
& Test circuitry



Figure 2-6. Wireless embedded test setup

Compared to other existed RF/Microwave test methods, the potential benefits

offered by the proposed wireless embedded test methods are listed as follows:

First, wireless communication provides a short direct connection between a tester

and DUTs. This ensures that the measurement results exclude the transmission properties

of the interconnection. No matched impedances throughout signal paths need to be

considered, hence, no scattering parameters between the tester and the DUT are

measured. In addition, usually, as the increasing of the operation frequency, it is harder to

make tests with traditional test setups because of signal degradation. But with wireless








technology, somehow, it is easier to transmit the test signal with high-quality from the

tester to the DUT according to the design principle of antenna.

Second, wireless test provides the possibility of testing multiple DUTs

simultaneously with one single test source so that test time is reduced and the utilization

of tester's valuable resources is enhanced. The communications between the DUT and

the tester are through antennas. Though the efficiency of on-chip antenna is low because

of the limited area and lossy substrate, no constraints are put on the design of a high

efficiency and high-power off-chip antenna. With such an off-chip antenna, the tester can

transmit the signals to the DUTs in a quite large area, compared to the size of the chip.

Third, wireless embedded test is more reliable. Conventional tests often involve

probing the wafer (chip) which can not only contaminate and damage the wafer (chip) but

need additional RF bondpads, which result in more parasitics.

Finally, wireless test has the potential to reduce test system cost since it does not

require a physical interconnection based on wires, connectors and RF probe cards.

2.3.2 Design Issues

The main limit of this wireless embedded test is that of the embedded test circuits

themselves and it does not matter which off-wafer (chip) tester is used.

The embedded test circuit, however, is limited in size because of economic

considerations. The test circuit is also limited by technology in its ability to operate at

reduced power and voltage. The implementation of the proposed embedded test design

must include some type of interface circuitry for input and output. It must also include the

processing circuitry, which is capable of converting the input signal into the desired test

stimulus without degrading the quality of converting the high frequency response into

baseband signals.








This setup must be done with minimal power, voltage, and size so that it does not

impact the circuit design. The power of the generated test stimulus must be kept low

without compromising the signal quality, as this is the requirement of most

RF/microwave tests. The size of the test circuits must be minimized to reduce the

overhead costs associated with these test sites on wafers (chips).

Calibration of these on-chip test circuits is also an important issue. Calibration is a

one-time effort which ensures testing circuits themselves work well before being applied

to make normal measurements. Otherwise, when an error occurs, it is hard to say whether

the DUT fails or not since it is possible to be a fault of testing circuits.

The introduction of on-chip test circuits should have as few effects on other circuits

as possible. For example, without careful design and layout, the pararsitics accompanying

the testing circuits will severely degrade the performance of the DUT during its normal

operation.

All the design issues described above will be further discussed in the next several

chapters when the detail designs of components in this proposed wireless embedded test

are presented.













CHAPTER 3
RF RMS DETECTOR FOR EMBEDDED TEST

In an embedded test system, one goal is to accurately estimate the signal strengths.

This is useful in (I) calibrating other test circuits, which ensures they work correctly, (II)

measuring signals entering the circuit under test (CUT), which makes sure the magnitude

of the input signal is within the desired specification of CUT and keep this value as a part

of test results and (III) measuring signals out of the CUT. To a large extent, the accuracy

of the test results is determined by the accuracy and calibration of the detector. Hence, for

detectors employed in embedded test, besides the requirements on bandwidth, dynamic

range and accuracy, calibratability and reliability should be considered as well.

Typically, two kinds of detectors are widely being used: peak detectors and rms

detectors. Although an average value can be estimated in both cases, for the first one, the

value is only accurate at the one chosen waveform type for which it is calibrated, usually

sinusoid waves. And the latter can be applied to measure the power of different types of

signals depending on the performance of the detector.

In this chapter, a new wide bandwidth RF RMS detector is presented as follows:

first, the principle of operation is discussed; next, a detailed circuit design is described

and a behavior model of the circuit is built with Verilog-A, followed by a comparison of

simulation results between the proposed analog behavior model and transistor-level

model (using parameters from the IBM 6HP process); then, the circuit error analysis and

analog statistical analysis for the detector are reported; finally, a test setup and

measurement results are shown to support the design.








3.1 Introduction

The RMS amplitude is a consistent, useful and standard way to measure and

compare dynamic signals of all shapes and sizes. When incorporated into embedded RF

test structures, compact RMS detectors can directly convert on-chip high frequency

signals to baseband signals, which can then be measured by low bandwidth test systems.

Thus, low-cost test implementations for RF systems can be developed.

RMS detectors of various designs can be found in many applications in the fields of

communication and of measurement systems. RMS detectors based on Joule heating

provide good accuracy and wide bandwidth. However, the rather complex packaging

requirements do not lead to a low-cost test solution. Diode detectors based on the square-

law are traditionally employed in communication systems as a form of power

measurement because of their favorable high-frequency performance and low-cost.

However, elaborate compensation techniques are required to make them meet the

demands of most applications. Dynamic range and temperature stability also limit their

application.

Another choice for RMS detector designs is based upon the translinear principle.

Compact integrated versions of such circuits are described in references [See84, Was88,

Mul97, Kum98 and CarOl], which include both implementations using bipolar transistors

[See84, Was88, Mul97 and Kum98] and MOS extensions [CarOl]. A well-known

example of the bipolar approach is presented by Mulder [Mul97], in which the authors

merged both squarer-divider and low-pass filter blocks into one dynamic translinear loop,

achieving a high-functional density. Since a full-wave rectifier is still required to precede

the whole translinear loop, high-speed performance is severely degraded. A bipolar dual

translinear-based RMS detector was described by Kumwachara and Surakampontomrn








[Kum98]. The bandwidth was improved to 100 MHz without the requirement of the

rectifier circuit. Carlosena [CarOl] applied the MOS translinear principle to the design of

a RMS detector. Although it has the advantages of implementation in a standard CMOS

technology and very low supply voltage, the circuit can not match the corresponding

bipolar circuits in performance.

For modem system applications, detectors with better performance are needed. It

has been demonstrated [Mul97] that translinear circuits allow designs with high

frequency and high-thermal stability, but this has not been realized in RMS detectors. In

this chapter a monolithic integrated RF RMS detector is presented with wide bandwidth

(up to Gigahertz) and that is stable with temperature [Yin04]. For a 40 dB input dynamic

range, the relative errors of the output are within 2%. With the addition of a base-current-

compensation circuit, the errors can be further reduced.

The chapter is organized as follows. First, the principle of operation is discussed.

Next, detailed circuit design is described and behavior model of the circuit is built with

Verilog-A, followed by a comparison of simulation results between the proposed analog

behavior model and transistor-level model (using parameters from the IBM 6HP process).

Then, the circuit error analysis and analog statistical analysis for the detector are

reported. Finally, Test setup and measurement results are shown to support the design.



3.2 Design Principle for RF RMS Detector

The translinear principle is a practical way of implementing nonlinear analog

circuits. Systematic analysis and useful applications of translinear circuits can be found

[Mul97, See91]. Two key building blocks in an RMS detector are a squarer-divider and a

low-pass filter. By use of the translinear principle, the two functions can be merged into








one translinear loop. In figure 3-1, if the nonideal properties of the transistors are

negligible, the relationship between lin and lout can be represented by a nonlinear

differential equation:

1in =oIouI +CVTIo., (3-1)

where lo is the bias current. Solving for lout,

lout _/_\ -
11 + sCV 10 \10 (3-2)


where the operator < > represents a time average. Thus, the output current becomes

the mean-square of the input signal. The rms signal is obtained by performing a square-

root operation on Iout. Since this is just a baseband operation, the operation can be put off-

chip without affecting the performance.



lin


5--<--L lout
Q1 Q3Q4


Io C Q4
Q2


Figure 3-1. Basic translinear loop used in RMS detector.


In figure 3-1, i,, flowing into the collector of Ql, has to be positive. To avoid using

a rectifier and improve the high-frequency performance of the circuit, a DC bias current

lo can be added to lin, which eliminates the need for the rectifier (|Im| < lo). In addition,








since it is more desirable to have voltage I/O signals than current I/O signals, a V/I input

converter and an I/V output converter are integrated into the circuit. By avoiding any

feedback loops in the circuit and separately optimizing the V/I conversion, a very wide-

band operation is possible.


3.3 Design of RF RMS Detector Circuit

3.3.1. The Input Interface Circuit


Figure 3-2. Input interface circuit and its matching performance.








To make sure the V/I converter does not affect the performance of the rest of the

circuit, a wide-bandwidth converter has to be implemented. The circuit which the authors

employed is shown in figure 3-2, the performance of which has been demonstrated by

Caprio and El-Gamal [Cap73, Elg98]. I, is given by

__ V -V
i- = V VBE -VBE2 (3-3)
Rin Rin

The second term on the right side of the above equation represents the distortion of

I, due to the difference of VBEI and VsBE2. The Caprio quad composed of Q3-Q6

provides feedback to reduce this effect, where

V -v v -V
IcorV5 VB6 VEl BE2 (3-4)
Rin -Ri(

By adding I- and Ico,. together, the current I, is obtained, which is a theoretically


linear function of Vin.

The input referred noise is affected by the devices in the circuit. There exists a

tradeoff between the linearity and the noise performance. The authors emphasize the

former while keeping the noise low enough compared with the measurable input signal

levels.

This input V/I converter can be operated in two modes: differential-mode and

single-ended mode. For the differential-mode, the differential input voltage can be

applied on the two sides and Vin becomes V,., = V,, V,._. For the single-ended mode, an

input voltage can be applied on one side and the other side is DC biased at a constant DC

level.









o\ _,_____________________ 1
S-.- S-Parameter Response
-10
-20
-30
,-40
-50
-60
-70 ' ' i ii"
0.1 1 10
freq (GHz)

Figure 3-3. Simulation results of input S-parameter



For Gigahertz operations, input matching has to be emphasized. In practice, 50-

ohm resistors shunted to ground on both sides will provide the best overall match (see

Figure 3-2) for wide bandwidth applications. The simulated input s-parameters are

shown in figure 3-3, which is good enough for the interested bandwidth. In addition, for

improved testability of the circuit, a bypass capacitor should be added at Vbiasl for the

differential-mode since it's not completely differential inside the circuit. In the single-

ended mode, both Vbiasl and Vbias2 should be shunted with a bypass capacitor.

3.3.2. Squarer-divider and Low-pass Filter

Section 3.2 demonstrates the basic principles used to build a squarer-divider and a

low-pass filter in one translinear loop. And a pair of differential currents was obtained

from the input circuit discussed in Section 3.1, which is a linear function of the input

voltage. Without using a rectifier, the sums of IolIin (|Iin|< lo) are applied into two equal

translinear loops as one is shown in figure 3-4. Therefore, according to the result of

Section 3.2, the output currents of the loops can be obtained:









'ootl,2 ~ jr )2)


(3-4)


lout


Figure 3-4. Translinear loop with base-current compensation shown in the dashed region
(CM: current mirror)



The sum of the two output currents is:



\01t + 1( + i I + (I i )



0

2(I:)
t+ 21
o (3-5)

The average operation is linear and lo is a DC bias current. Therefore, if the DC current

2Io can be subtracted, the remaining part of the right side of (3-5) becomes the mean-

square value of the input current multiplied by a scalar of 2/Io.








100 . . . . 20% of lo
80 -50% of to
5*90% of o10

60

40


20

0
0.01 0.1 1 10
Freq (GHz)

Figure 3-5. Frequency response at the input of the translinear loop

In figure 3-4, one translinear loop used is shown. The diode connection at the input

of the loop is replaced by a NMOS helper transistor. This NMOS helper has two

advantages over the bipolar helper transistor. First, it further reduces the base current

error. Second, it brings better high-frequency performance than the bipolar helper if the

size of the NMOS transistor and the bias current through it are carefully chosen. Only the

left half of the translinear loop works in the high-frequency region. The simulated

frequency response (using parameters from the IBM 6HP process) for the input is shown

in figure 3-5.

3.3.3. The Output Interface Circuit

Rxout

21o



Ioutl+Iout2



DFigure 3-6. The output interface circuit


Figure 3-6. The output interface circuit








An output I/V converter is used to convert the current signal back to a voltage

signal. Since at this step, the signal is low-frequency, the design of this converter

becomes quite simple. It can be realized by a CMOS op-amp with a feedback resistor (see

figure 3-6). The negative input terminal of the op-amp is connected to the output of two

translinear loops and the other terminal is connected to a voltage bias, which is set to the

collector voltages of the NPN bipolar transistors at the last stage of the translinear circuit.

After offsetting the DC current 2Io at the output of the two translinear loops, the

remaining current is converted into an output voltage. By suitably choosing the value of

the resistor, Vout is the product of the mean-square value of the input voltage and a gain

k.


"- 2R0 (2) -(3-6)
Io

3.3.4. Error Analysis

The major sources of error in the circuit are in the translinear loop. Because of the

finite current gain of bipolar transistors, the collector current of transistor Q3 will not be

exactly (Io+Ic). This current error results from the base current of Q4 and Q3. Here, a

new base-current compensation technique is introduced as shown inside the dashed part

of figure 3-4. Without the base-current compensation circuit in the dashed block, the

following can be derived:


lCQ3 = l~ (10 + lcap + lCQ4 i 1)

-l ( + I P) + ZCQ4 (3-7)
e+ro el+/3
error term








where 3 is the current gain of the bipolar transistors. With 3 around 100, which is a

reasonable value for modem bipolar transistors, the first term on the right side of the

above equation can be treated as the ideal value of ICQ3 while the second term is the error

term. Furthermore, this error term is a function of ICQ4. With the increase of IcQ4, it is

easy to see from the equation of 3-7 that the error of ICQ3 becomes worse. Considering the

base-current-compensation circuit in the block with the assumption that all transistors are

matched, a more accurate collector current of Q3 can be obtained from the following

derivations:

IbQ6 CQ5 ICQ4 (3-8)
1 +- \+ 1+f8


ICQ3 = f (I0 + Icap + 21CQ4 /1 2bQ6
+CQo2IC 16+)+8

(Io i +Zcap )+" 18(21C44/18-2IcQ4/(1+ 18))


=8 (i + + 2ICQ4 (3-9)
1+ 8 (1+8)2
error term

Comparing equation 3-9 with 3-7, the first terms on the right side of both

equations are same while the error terms are different. It is obvious from equation 3-9

that the error of ICQ3 can be reduced by a factor of 2/(1+P3). Figure 3-7 shows the

simulation results of RMS circuit with and without compensation subcircuit. From the

figure, it can be seen that there is not much difference for the relative errors of two cases

when the input signal is small. The relative errors become bigger for the rms circuit

without the compensation subcircuit than that with the compensation circuit as the

amplitude of the input signal increases. Hence, the compensation method is very effective





38


for reducing the base-current error resulting from Q4. Simulations demonstrate that the

total relative errors of the output can be reduced to 1%. The complete RMS detector

circuit is depicted in figure 3-8.

0.010 -&-with compensation
0.00 circuit
0,005 -0,-without compensation
^ ^^ j circuit


U.UUU
-0.005
-0.010
-0.015
-0.020
-0.025
_n ndin


0.00 0.02 0.04 0.06 0.08 0.10 0.12
Vin (V)

Figure 3-7. The simulation results of RMS circuit with and without compensation
subcircuit for 1 GHz sinusoid input signal.



T- r nnlinernrPr i ^
r -- ----------- ---------- V------------
I vddi




II- [11 II Ii- UI^-
It






VI.- Vin-

oco r .R -
I DC ,
FIgre-. -olee -u -d-i o r- Gnd Teet
e 'B z 7 1uuIn t interface
Figure 3-8. Complete circuit diagram of the proposed RMS detector.








3.4 Verifications of the RMS Circuit Design

3.4.1. Analog Behavior Model of the RMS Circuit

12
--.-------W--] vin) I
1 ---Y-- ----vout-- ----
|. I __- 3 ___

4 -.-- 1Behavi )r modee-
2
S VI / Transistor model
---- -- Ij -- .. ---------
T j i-- 0 50 100 150 200
time (ns)

(a) (b)

Figure 3-9. Analog behavior model of the RMS circuit: (a) test fixture of analog behavior
model; (b) comparison of simulation results between two models.

A behavior model is a way of defining the functionality of a design in terms of

algorithms without describing its hardware implementation; behavioral models are based

on sets of mathematical equations describing the behavior of a circuit element. A

behavioral model is similar to a subcircuit object in that it constitutes a box which is

connected to a circuit through electrical ports. Compared with transistor-level models, the

difference is that the interior of a behavioral model box is implemented in terms of

symbolic equations rather than a netlist, which greatly increases the simulation speed.

To verify the proposed RMS detector circuit design and to use the detector in

"alternative test" methodologies [VarOO], an analog behavior model is built based on the

above analysis, which is shown in figure 3-9(a). With this model, the performance of the

design can be accurately estimated without resorting to time-consuming transient analysis

with transistor-level models. Simulation results of this proposed analog behavioral model

are compared with simulations of the transistor-level model (using parameters from








IBM6HP process) in figure 3-9(b). The results of analog behavior model show small

deviations from those of the transistor-level model only in the transient case, but have a

good agreement in steady-state.

3.4.2. Monte Carlo Analysis of the RMS Circuit Design

To account for process and mismatch variations, which play a more vital role on

manufacturing yields as processes move to smaller geometries, comer simulations or

Monte Carlo analysis can be applied on the proposed RMS circuit design.

Comers simulation tests for process, temperature, and mismatch variations. With

this method, a designer determines the worst case comers, or conditions, under which the

design will be expected to function. Next, each comer is simulated, and the output of

each corner is examined to determine whether or not the design performs as required

under each of the specified conditions.

The advantage of comer simulation is its relative simplicity. However, there are a

number of issues with comer simulation. Perhaps the most troublesome of these is if the

comers are not provided, then the designer may not know what the comers actually are,

leading him to frequently make a best guess. Guessing worst case comers that will never

occur in reality not only wastes design time, but also can result in a design that takes

more area or consumes more power than needed, or even becomes impossible to design.

Not guessing comers that will occur in reality may result in lower yield.

With Monte Carlo analysis, hundreds of simulations are typically run with a variety

of variations introduced randomly, though; the guess work in determining the worst case

comers is removed. Whereas comers analysis produces a binary outcome (either the

comer passes or fails), Monte Carlo analysis produces samples of a continuous function

that can be used to estimate yield. In addition, Monte Carlo deals with the distributions of






41


the process parameters among lots, wafers, and dies, and allows the designer to study the

effect of parameter variations among devices on the same chip.


s14 6 14


w w,
12 .............. .. ............... ......... ....................... 12 --- -- --........... I...... ---- - --........ ............ ... . ..


ii

2 2
10 ............ .... 7-7- .................. .0 ......... ----- ....... ------

.. - - - - - - - ....... .... .... .. . .......... ---- ----

4 ----- ----- ----- ---- - - --- .. . .I. . .


6 bG 75 6 85 6, 6 8 7 72 74 760 78 8
Voult (mV) Vout (mV)

(a) (b)

Figure 3-10. Output distribution with process and mismatch variation: (a) with bias
circuit; (b) with ideal bias (sample size 100, room temperature).

In the case of the proposed circuit design, since no worst case corners are available

and the technology provided the statistical models, Monte Carlo analysis is preferred

here. In the following analysis, the size of samples is 100 and a 1 GHz sinusoid input is

assumed with 10 mV amplitude. Figure 3-10 (a) shows the RMS output values using

Monte Carlo analysis with process and mismatch variation under the room temperature. It

can be seen the variation of the output is around 15%. However, with all the bias circuits

replaced by the ideal ones (Figure 3-10 (b)), it is found that the output variation decreases

to 7%. This means the bias circuit is most vulnerable to process variation and mismatch.

Therefore, to improve the yield of the proposed circuit, larger area bias current transistors

need to be used. In addition, careful layout and employment of symmetric layout

techniques can increase the yield further.









1.5 ..-....---

1 _<

0.5

0
S-0.5 -



-1.5 I--------------------
-40 -20 0 20 40 60 80 100
temperature (c)

Figure 3-11. Variation of output .vs. temperature

The performance of the circuit under different temperatures is not examined with

Monte Carlo analysis. Instead, output changes are obtained by transient simulations.

From figure 3-11, it is found that the variation of the output is around ldB for

temperature variation from -40 C to 100 C, which is acceptable for RF measurements.

By examining the relation between the input voltage and output voltage in (3-6), it can be

found this variation mainly results from the temperature variation of bias current Io.

Hence, if the circuit supplying lo is improved to be independent of the temperature

variation, it is expected that the variation of the output with temperature could be reduced

further.

Since there exist process mismatch and variation for the design, from the above

analysis, it can be seen the RMS detector needs to be calibrated first before it is applied

for embedded test. Here one question arises: how to calibrate the detector which is

integrated with the circuit under test?

The goal of the embedded test is to reduce the cost of on-chip RF test. Hence, the

detector can not be calibrated via applying a very high frequency input signal to the chip

with expensive RF probes. One simple approach is to use the wide band characteristics of








the detector. That is, the detector can be calibrated at low frequencies and then applied to

measurements at higher frequency signals.

3.4.3. Simulation Results of the Proposed RMS Detector




Vi rectane 0.05 rectangle OOM
0 0.04 -A-trianglelOOM
-Vin.--- 0.03 -- two tones
0.02
Vin- triangle 0i .01.-- ---
d) 0.00
.0.01 ---" ---- --
-0.02
2-tone -0.03
V in--.w -n. -0.04 ----------- ^ ''i

-Vin 0.00 0.02 0.04 0.06 0.08 0.10
Vin (V)

Figure 3-12. Simulated relative errors for different waveforms



To further verify the performance of the proposed RMS detector, simulations of

transistor-level models (using parameters from IBM6HP process) are run with the

SpectreS simulator.

Figure 3-12 shows the simulated relative errors for three waveforms other than

sinusoid waveforms at 100 MHz. It can be seen that it's more inaccurate to detect the rms

value of rectangular wave than that of triangular wave, especially at higher amplitude

levels. The reason is that there is more peak energy in rectangular waves than in

triangular waves. The two-tone simulation is performed with two sinusoid waveforms of

same amplitude at 850 MHz and 900 MHz.










0.02
-02--single-end mode
0.00 -U-differential mode
-0.02
iuj -0.04 -- Veak
-0.06 -- ---

-0.08
-0.10
01, t: pulse width;
-0.12 T: period;
-0.14 Duty Cycle=t/T;
0 2 4 6 8 10 CF=1/(Duty Cycle)1/2.
Crest Factor

Figure 3-13. Relative error versus crest factor



As stated by Mulder [Mu197], the worst-case waveform for an rms measurement is

a rectangular pulse train, where all energy is contained in the peaks. To perform

simulations of the relative errors as a function of the crest factor, the duty cycle and the

peak voltage of the applied input rectangular pulse train are varied to obtain different

crest factors at some constant rms value and pulse width. The information required by

simulations is displayed in table 3-1. In all simulations, a constant rms value of 10 mV is

assumed and the pulse width of the peak is given as 500 ps. Figure 3-13 shows the results

of relative errors with different crest factors.

The blue curve is obtained when the circuit is driven in a single-sided manner, e.g.,

the full input signal is applied to one input terminal and the other terminal is AC

grounded. If driven with a balanced differential signal, the red curve is obtained, which

obviously has smaller errors than with the single-end signal. Actually, regardless which

kind of input waveform is, the highest accuracy is always obtained when a balanced drive








is used, which can be available by using a balun (balanced-to-unbalanced converter) or

some other high frequency transformer external to the integrated circuit. This is partly

because the resistor between two input transistors results in an unbalanced current

distribution on the two sides, especially for higher operating frequency or bigger input

resistor.

Table 3-1. Information for simulations with different crest factors
CF Vpk (mV) Duty Cycle (%) Period (ns)
1 10 100 ---
1.4 14 50.0 1
2 20 25.0 2
3 30 11.1 4.5
4 40 6.25 8
5 50 4.00 12.5
6 60 2.78 18
7 70 2.04 24.5
8 80 1.56 32
9 90 1.23 40.5
10 100 1.00 50


3.5 Test Setup & Measurement Results

The circuit was fabricated in the IBM 6HP BiCMOS process. The power supply is

3.4V and the DC bias current used in translinear loops is 100 uA. The capacitors of two

low-pass filters are 48 pF each, which combine with the bias current to yield a cut-off

frequency of 12.8 MHz. All components are integrated on chip, including input matching

and bypass capacitors for RF testability of the chip. The total size of the chip is 0.912

mm2 (1102 umx828 um) and the core circuit area is only about 0.07 mm2 (290 umx250

um. And a photomicrograph of this design is shown in figure 3-14.



























Figure 3-14. The microphotograph of the RMS circuit

There are totally 16 bondpads on the three sides of the chip. The bondpads of the

top side (figure 3-14) are used for dc bias, each of which (except the ground pad) is

shunted by an on-chip bypass capacitor of some suitable values. The goal of bypass

capacitors here is to ensure the shunted terminals have good ac grounds since the

parasitic inductance of the connection between the on-chip terminal and the external dc

supply has to be considered in the very high frequency domain. The bondpads of the left

side consist of output pads and pads for test. The input bondpads are at the bottom of the

chip. (From left to right: G-S-G-G-S-G; G: ground, S: signal)

3.5.1. Test Setup and RF Calibration

It is quite easy to make DC measurements with semiconductor parameter analyzer.

Besides setting the correct DC biases, the value of bias current lo is allowed to be

observed by test pad and therefore it can be adjusted as required, which is important to

the performance of the detector. A star grounding scheme is preferred to connect the

grounds of all the instruments to a single point.











.... "" " DC power I .. . ." I
supply
..ias Power Microwave Power Meter


Power r.or
seso A.[I "k onojl
? Analyzer


SPChip under test
Probe Probe Meter
t --- Multimeter

Figure 3-15. Basic RF test setup



Although it is simple to make DC measurements, to perform accurate RF

measurements on the proposed detector is quite complicated. As seen in the left part of

figure 3-15, a basic setup for RF measurements consists of a network analyzer, an ac or

RF signal source (if not included in the network analyzer), an RF power meter and

associated power sensor, a microwave probe station and probe heads, a bias Tee, DC

supplies and multi-meters. A more visualable version of this test setup is shown in the

right part of figure 3-15. The power meter and power sensor in the dashed block are only

used for the power calibration of the network analyzer itself, not for the circuit

measurements.

In the RF domain, the actual input signal power of the DUT (device under test) will

be not equal to the one at the output of the signal source because of signal loss and

reflection, both of which can be reasonably ignored in the lower frequency-domain.

Therefore, the correct calibration and de-embedding processes have to be employed to

obtain accurate experiment data. To a large extent, the correction procedure determines

the final accuracy of the measurements.








The calibration procedure is to determine error-terms of the measurement system

and sets a reference plane at the interface of the measurement system and DUT. With the

help of network analyzer (Agilent PNA), the calibration process can be characterized into

two steps: the source power calibration and the connection path calibration. Traditionally,

people do not calibrate the power of the signal source; one reason is that all but s-

parameters are energy ratios of incident and reflected power waves, and the other reason

is that it is inconvenient to calibrate the source power with the traditional network

analyzer, like HP8510, etc. Fortunately, the job becomes quite reasonable using the

Agilent PNA with the details described in PNA manual [PNA02]. The calibration of the

connection path as a whole can be done with the one-port calibration method introduced

by Wijnen [Wij95]. At this stage, the reference plan is set to the end of the cable which

connects to the probe head.

As for the measurements of s-parameters of this detector circuit, only the input port

needs to be calibrated since the output always falls into the baseband. As a consequence,

one-port calibration (open-short-load) is adequate for the measurements of the detector

circuit. With the measured input s-parameters, the exact signal power entering the

detector can be calculated assuming the correct calibrations, i.e. the reference plane is

pushed to the tip of the probe head. The values of one-port s-parameter at 50 MHz and 1

GHz from -30dBm to OdBm are shown in figure 3-16.

In the figure, it is reasonable to observe that the values of input return loss at 1 GHz

are larger than those at 50 MHz since less of the signal is transmitted into the DUT at

higher frequency for the same incident signal. All the one-port s-parameters are








approximately equal at the same frequency, which is found to be useful when measuring

the frequency response.

0.3 -- __ ___________________________
0.30

0.25 -4-n-50MHz

0.20 -*- 1GHz(deembedded)
01- -.4-- 50MHz(deembedded)
"" 0.15 ,l- ..

0.10 j- --a-

0.05

0.00
-30 -25 -20 -15 -10 -5 0
Pin (dBm)

Figure 3-16. Measured one-port s-parameters at different frequencies

Further, the parasitics of the bondpads are included in the direct measurement of

one-port s-parameter. If the circuit is applied for embedded test, then the input matching

will become a little bit different since the input of the detector is connected to other

circuit without the bondpads. To get rid of the effect of the bondpads, the s-parameters of

a test structure of the bondpads is measured. The whole procedure is usually called de-

embedding. Then, according to the theory of one-port network parameters, the de-

embedded S1 parameter of the circuit can be extracted. The formulas used in this de-

embedding procedure are listed below:

S-parameter -) Y-parameter:

1 1- S11 1 1 S llbondpad
Yl 1llbondpad (3-10)
Zo 1+$11 z0 I + S llbondpad

Operation in Y-parameter domain:

Y = Y1 Y bondpad (3-11)
lI Ide-embedded 11l ^llbondpad (3-11









Y-parameter -> S-parameter:

I Zo m'Id de-embedded (3-12)
S1 I-embedded i 1 de-embedded



1 + r Zo* de-embedded d&

56 L2 " "":i]i "',';i ';, ,',i!h... .4 ...O:;,.--4.. .. .i originall
.g0 1-- --resistance
56 d e-embedded
resistance
.0 0.08 t -k-orignal
S54 -- capacitance
0.04 de-embedded
52 0.0 capacitance
0.02
50 --- 0
-30 -25 -20 -15 -10 -5 0
Pin (dBm)

Figure 3-17. The de-embedded input impedance

The resulting one-port s-parameters at different frequencies are shown in red

curves in figure 3-16 to compare with the un-deembedded ones. It is reasonable to note

that the parasitics of the bondpads effect s-parameters more at 1 GHz than at 50 MHz. In

the latter case (50 MHz), both the de-embedded curve and the un-deembedded curve are

almost overlapped together. With some calculations, the input impedance can be obtained

from the measured one-port s-parameters as shown in figure 3-17.

3.5.2. Measurement Results

Once all the errors are calibrated, accurate measurements are taken. The measured

relative errors of the RMS detector output for DC signals, 50 MHz and 1 GHz sinusoid

signals as a function of the input amplitude are shown in figure 3-18. The lower

measurement level is limited by the accuracy of the measurement instrument, which is -








30 dBm provided by the ac signal source inside the network analyzer for the power

sweep at a given frequency, and the upper measuring level is determined by the product

of the bias current and the input resistor (IoxRin), which can be seen in figure 3-19. The

lower measurement level can be extended uses external attenuators.


0.05
0.04
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
-0.04
-0.05
0.(


I


0.02


~~1


[ ____________ ______


11o"^^ >^^..,^^




- ,1GHz
_____- -,50MHz
-DC


0.04 0.06 0.08 0.10


Vin (V)

Figure 3-18. Measured linearity error .vs. different input signals


0.12
0.10
0.08
0.06
0.04
0.02
0.00


0 0.04 0.08 0.12 0.16
Vinrms (V)

Figure 3-19. The upper measurement limit of the detector (measured at 1G Hz)


)0









To investigate the bandwidth of the proposed detector, the calibrated frequency

response of the circuit has to be measured. It was assumed that the input match

parameters of the DUT are the same at each frequency independent of the power level of

the input signal. The assumption can be justified from figure 3-16. With this assumption,

the frequency response is obtained in figure 3-20. The measured -3 dB bandwidth is 1.3

GHz. The DC blocking capacitor causes a bit of rise of the curve.

2 .-----........
0
6 -2



0

L1-12
-14
-" 16


0.1 1 10
Frequency (GHz)


Figure 3-20. Frequency response of the proposed detector












CHAPTER 4
ON-CHIP COMPONENTS OF RF/MICROWAVE SIGNAL GENERATION

4.1 Introduction

From Chapter 2, it has been shown that one main challenge posed for today's

RF/Microwave IC test is the need for on-chip generation of high-quality and high speed

test signals using low-cost hardware. For this reason, this chapter demonstrates IC

components which will be employed in a new scheme for on-chip RF/Microwave signal

generation. Two components are presented in this chapter: an on-chip antenna and a

frequency divider. The common features of these two components are simple and the

capability of working at very high frequencies. The detail implementation of on-chip

RF/Microwave signal generation will be left for the next chapter.



4.2 On-chip Antennas

As a critical component in the proposed wireless embedded test, the on-chip

antenna is the subject of this section.

Traditionally, antennas are applied in such applications as long distance radio links

and radars, in which large-sized and high-gain antennas are needed. While in the targeted

application, the RF/Microwave signal source of the external tester can be very close to

the wafer (chip) under test and the transmitted signal power can be enough strong, so that

the size requirements of antennas are lowered. This gives an opportunity to mini-sized

and low-gain antennas. As will be shown later, for an incident signal with a frequency

above 20 GHz, an on-chip antenna with the length less than one tenth of the wavelength








still can be useful for short-range communication between the DUT and the external

tester. From table 4-1, which gives the frequency versus wavelength in the following

materials: air, dioxide, nitride and silicon, it can be seen that compared to the DUT, the

size of such an antenna is small enough to be integrated.



Table 4-1. Signal frequency versus wavelength in millimeters for different materials
Frequency (GHz) 1.0 10 20 40 60 80 100
Wavelength (air) 300 30.0 15.0 7.49 5.00 3.75 3.00
Wavelength (dioxide) 150 15.0 7.50 3.75 2.50 1.87 1.50
Wavelength (nitride) 113 11.3 5.67 2.83 1.89 1.42 1.13
Wavelength (silicon) 86.9 8.69 4.35 2.17 1.45 1.09 0.87


Currently, the study of on-chip antennas is mainly researched in laboratories while

it is gaining interest from industry. The on-chip antennas described in this work act as a

receiver of external test signals. Next, the performance issues of on-chip antennas are

discussed. Then the designs of various on-chip antennas are presented. These antennas

are simulated with the aid of the EM simulation tool HFSS. The obtained simulation

results of the antenna designs can be better explained how they will work in the real

world before being manufactured. Finally, the test setup and the measurement results of

the fabricated antenna test structures are demonstrated.

4.2.1 Performance Issues of Various Antennas

Conventionally, the performance of an antenna is characterized by its antenna

impedance, radiation resistance, directivity, antenna gain and efficiency, all of which are

summarized in table 4-2. Since all passive antennas are reciprocal, the same set of

radiation properties can be applied to either transmitting or receiving capabilities of an

antenna. Besides these properties of on-chip antennas, one key issue is large transmission








loss through silicon substrate. For most modem CMOS technologies, the resistivity of

silicon substrate is in the range of 10 ohm-cm to 25 ohm-cm, which means the substrate

is conductive at the usual working frequencies of on-chip microwave antennas.



Table 4-2. Parameters characterizing the performance of an antenna [Set97]
Antenna The impedance measured at the input port of the antenna and is also called
Impedance input impedance
Radiation The ratio of radiated power to input current squared.
Resistance
The ratio of the maximum power density radiated by the antenna under
Directivity consideration to the power density radiated by an isotropic antenna, both
measured at the same range and excited by the same amount of input power
Antenna The ratio of total radiated power to the input power supplied to the antenna
efficiency and also called radiation efficiency
Antenna The ratio of EIPR to the input power, where EIPR is effective isotropic
Gain radiated power


To improve the performance of on-chip antennas, different types of antennas have

been studied [KimOO, Oje04]. Some results obtained are summarized here:

The slot antenna consists of an aperture in a ground plan, where an electric field is

excited across the slot. The straight slot antenna can be considered to be the

complementary antenna to the dipole antenna, as shown in figure 4-1 (A) and (C), and

many of its properties, such as input impedance, can be directly calculated from its

equivalents. Typically, the slot antenna is an efficient radiator. But for on-chip

implementation, it is of interest to keep the antenna ground-plane dimensions as small as

possible, which inevitably compromises the performance. Another limitation is that the

slot antenna is usually single-ended and thus not suited for connection to differential

active circuits without the use of an on-chip balun.





56

Patch antennas, also called microstrip antennas, are metallic patches that sit on top
of a dielectric substrate, as shown in figure 4-1 (B). Typically, they consist of a ground
plane, a dielectric substrate and a patch. Usually, patch antennas are constructed from
printed circuit materials so that they are thin with a low profile. Other advantages of these
patch antennas are inexpensive, durable, conformable to various surfaces and versatile for
resonant frequency, polarization, pattern and impedance. But a patch antenna
manufactured on silicon will exhibit a small bandwidth and poor performance due to the
high dielectric constant of the substrate. Conductive losses in the silicon will lead to poor
efficiency, thus requiring the use of high resistivity silicon which is generally not
compatible with standard SiGe bipolar and CMOS processes.








C D







Figure 4-1. Four common types of antenna: (a) slot antenna; (b) patch antenna; (c) dipole
antenna; (d) Loop Antenna


The dipole antenna is an alternative for on-chip antenna. It includes a variety of
antennas, like folded dipole, linear dipole, meander dipole and zigzag dipole, most of








which are excited in the center. The dipole antenna has the same advantages for on-chip

integration as the loop antenna. Usually the length of on-chip dipole antenna is less than

half wavelength though 2-wave dipole is the most popular dipole. To further minimize

the size of dipole antennas while minimizing the degradation on performance, the

modified dipole antennas, such as zigzag and meander, were proposed by Nakano,

Rashed and Ali [Nak84, Ras91 and Ali96]. Compared with the same-length linear dipole

antennas, these modified dipole antennas have the higher gain and higher resonant

frequency.

Loop antennas are usually circular turns of wire that radiate bidirectionally along

the axis of the loop or normal to its axis, as shown in figure 4-1 (D). They are suitable for

on-chip integration because of two reasons: 1) The space that a loop antenna needs is

limited, which can be easily understood, that if an antenna of given length is wound

circularly it will be reduced in length; 2) A loop antenna is inherently balanced fed,

which makes the antenna suitable for integration with differential circuit topologies

without the use of on-chip baluns. In general, loop antennas have very low radiation

efficiency because the radiation resistance is much smaller than the loss resistance, but

which can be improved by using more turns of the loop.

Based on the above discussions, the loop antenna and the dipole antenna are more

suitable to be integrated on-chip than other types of antennas. Lots of on-wafer

measurements have been done to compare the performance of different types of on-chip

antennas by SiMICS research group at University of Florida. From their measurement

results, it has been seen that the best optimized performance results come from on-chip








zigzag dipole antennas [Li03]. Hence, the next subsections will focus on the

implementation of on-chip zigzag dipole antennas.

4.2.2 Design Issues on On-chip Zigzag Dipole Antenna



Feed gap







/A\\80 um
0 um bondpads


Figure 4-2. An on-chip zigzag dipole antenna



On-chip zigzag dipole antennas (shown in figure 4-2) with various length and metal

levels are designed to compare their performance. The bend angle of these antennas,

which is the angle between two neighboring arm elements of the antenna, is 30 degrees

which is based on the optimized results from on-chip antenna measurements [KimOO].

The employed technology for design is SiGe 0.18 BiCMOS with the option of 7 metal

levels. The lengths of designed antennas are 1mm and 2mm, respectively. For each

length, a six-metal-level antenna and a top-metal-only antenna are implemented.

The resistivity of silicon substrate on which antennas are fabricated is in the range

of 11 ohm-cm -16 ohm-cm. There are seven metal layers in this technology, in which

two metal layers are made of copper and the rest are made of aluminum. The top-metal-

level antenna is made of the top layer of the metal, which is also the thickest metal (4.0

um) in this technology. By use of this thickest metal layer, it is expected that the loss








resistance through the antenna arms can be reduced so that the antenna efficiency can be

increased. Based on the same target, multiple metal layers can be used in parallel in

antenna design.

To make on-chip antennas more area-effective, the length of these antennas is

usually designed to be less than half of the wavelength of incident signal, which means

these on-chip antennas are not operating at resonance and hence the impedance of the

antenna is not real when being matched to the following circuits.

One more point needs to be mentioned here is the feed gap, which is defined as the

distance between two feed points as seen in figure 4-2. To improve both area efficiency

and antenna efficiency, the gap should be as small as possible. However, if the gap

becomes too small, two feed arms of the dipole antenna could couple with each other at

very high frequency operation because of the parasitic capacitance between them. In our

case, the antenna is operating around 24 GHz, and a reasonable feed gap can be chosen

between 5 um~ 30 um.

Apart from the above considerations, it is worth examining the effect of an on-chip

antenna on the nearby circuits on the same chip. According to experiments and

simulations [004], this effect can be identified as noise coupling between the on-chip

antenna and the integrated circuit elements through the common silicon substrate.

Generally, the nature of this noise coupling is common-mode. Thereafter, to reduce this

noise coupling, a symmetric IC layout relative to on-chip antenna is preferred and,

meanwhile, the on-chip antenna itself is required to have a balanced structure and

balanced feed.





60


4.2.3 Simulation Results of On-chip Zigzag Dipole Antenna


air


Figure 4-3. HFSS model of on-chip antenna


Figure 4-4. Layout of a 2-mm on-chip zigzag dipole antenna

Three different on-chip antennas are simulated with an EM (Electromagnetic) tool

- HFSS (High Frequency Structure Simulator) as listed in table 4-3. The whole 3-D

simulation model used in simulations is shown in figure 4-3. The radiation sphere is

defined to allow waves to radiate infinitely into far space. At the bottom is an ideal

ground plane. At the top right comer is the antenna chip model, which consists of four








layers (from bottom to top): silicon, silicon-dioxide, silicon-nitrite and final passivation.

The metals of which the antennas are made of are located inside the silicon-dioxide. The

thickness of each level is given as physical dimensions which are obtained from MOSIS

[IBM05]. Beneath the chip is a 2-mm metal layer, which touches the ground plane. More

details about the building of antenna model can be found in related HFSS manuals

[Ans05].

Table 4-3. Types of on-chip antenna manufactured
Type Length (mm) Metal levels used
1 1 Top Metal (MA)
2 2 Top Metal (MA)
3 1 16 Metal Levels (Ml, M2, M3, M4, MT, MA)

All HFSS simulations are performed with frequency sweep from 16 GHz to 32

GHz. The input impedances of different antenna designs are shown in figure 4-5 (a) and

(b). From figure 4-5 (a), it can be observed that all the real parts of the antenna input

impedance decrease with the increase of the signal frequency but the rate of decreasing

becomes slower, for the case of type 2 antenna, the values even tend to increase from 28

GHz. The resistance of on-chip antenna is composed of radiation resistance and loss

resistance. At the lower frequency end, the resistance of on-chip antenna is dominated by

loss resistance, which explains that the 2 mm antenna made of the top metal has the

lowest resistance and the resistance of type 3 is the highest among three antennas. This is

also consistent with the results of figure 4-6, which shows the antenna gain varies with

the frequency. In addition, the lower reactance of antennas made of the top metal due to

lower metal-to-substrate parasitic capacitance contributes to their lower loss resistance as

well. As the frequency increases, the radiation resistance becomes more important, which

is proven by observing the real impedances of type 2 and type 3 become close and higher








than that of type 1 at the higher frequency end since the 2 mm antenna made of the top

metal has the highest radiation resistance. In figure 4-5 (b), it can be observed that all the

reactance parts of the antenna input impedance increase with the increasing of the

simulated frequencies and are less than zero for the simulated frequencies, which means

none of these on-chip antennas are half-wave antennas and they resonate at higher

frequencies.
70 ........... .... 1. ........ 40 ....... m m e top 0 . ..... ... ........... 0
E 60 E .5-
6 -m-2mm top-metal =0 a50
0
20M -100
Vm 40


10 J -250
16 20 24 28 32 16 20 24 28 32
frequency (GHz) frequency (GHz)

(a) (b)
Figure 4-5. Simulation results of input impedances of different on-chip antennas

(Theta --90 deg, Ph1=0 deg) (Theta=90 deg, Freq.=24 GHz)
E 0 ---- ^^-- -. ----- 0





0 4 [ .e rm m to p rn e ta l ... .... . ....... - -- !0 ...... ........ 1 1.. . . I e r M to p m e ta ll
B 2m top metlI" .5 --2mm top metal
-9- 2mm toprea/ -6 met.I ,, alsJ



20 ---- ----...__--', -2....

03 .15

-25 I -35
16 20 24 28 32 0 100 200 300 400
frequency (GHz) Phi (deg)

(a) (b)

Figure 4-6. Simulation results of antenna gain of different on-chip antennas






63


The simulated antenna gain for these on-chip antennas are displayed in figure 4-6

(a) and (b), where gain is defined as the ratio of antenna's radiation intensity in a given

direction to the average power incident upon the antenna port. From figure 4-6 (a), it can

be observed that the gain increases as frequency increases. The gain of 2-mm antenna is

larger than that of 1-mm antennas at the same frequency. From figure 4-6 (b), it can be

observed that the maximal gain occurs along the broadside directions. Furthermore,

figure 4-7 (a) and (b) investigate the gain in the plane where the antenna locates and in

the 3-D space, the shapes of which are similar to those obtained from usual half-wave

dipole antennas.

90 -- 2mm top metal
120 60 1- Imm top metal
//'<" ',1rmM 6 metals

dB(Ga nTot 1)



150 7 a. a -: 302
IdN.

180 .. ..... ........ ....... ... --- --- '



270

(a) (b)

Figure 4-7. Antenna patterns: (a) antenna patterns in XY plane where the antenna locates;
(b) 3-D antenna pattern.

It can be observed that the radiation patterns of all the treated antennas are

bidirectional with maximums in the broadside direction and with back lobes of similar

strength as the front lobes. The directivity of such antennas is generally less than 3 dB.

The antenna gain is always lower than the directivity due to conductor and substrate

losses in the antenna.








4.2.4 Measurement Results of On-chip Zigzag Dipole Antenna


Figure 4-8. Fabricated 2-mm on-chip zigzag dipole antenna


The test structures of on-chip antenna are made with an IBM process through

MOSIS. Figure 4-8 shows the fabricated 2-mm on-chip zigzag dipole antenna. In

practice, the test structures of both 2-mm and 1-mm antennas are fabricated. Two

parameters are obtained in the test, which are antenna gain and input impedance. The test

setup is shown in figure 4-9.


Off-chip antenna


Antenna chip


interconnection


Probe head


Figure 4-9. Test setup for on-chip antenna.



For input impedance measurements, on-wafer one-port calibration is performed

first to a microwave probe through the network analyzer. Then, measured S-parameters

are obtained and converted to the input impedances of the antennas, which are shown in

figure 4-10.






65


The transmission gains of the on-chip zigzag dipole antennas are also measured

using the test structure shown in figure 4-9. For the results plotted in figure 4-11, the

separation between on-chip antenna and off-chip antenna is 6 cm.

34 0
,0,_~~~~~........ ......................... 2
342 --r.....--- --.......-i------ ------ 0. i ............... .. .


-- -- ---- --.-- .4... -20 ... ..- .... .. ..------ i ...............
.8-.... ...... ....... ........ I ........... . .. ... ............................
S ?6 --**--1-4.-1 ...... 4.... ------- ...... ------,^ i -! - - -&: /
o 20 - ---j--



j-- --- --------- i-- ----- ---i-ii ---------------.......
24~~~ ~ ~ ~ .... ........ ........ \ .................. ..... -------


8 '1S0I 12 14 16 18 20 2i2 24 26 6 8 10 'M 14 16 18 20) 22 2 26
FB .enc,, iGHW Frequeancy, (GHz)
Figure 4-10. Measured input impedance of on-chip zigzag dipole antenna..
2 ..-15---- ----- -




,-,*-- 1 mm
-20 -----------------------2 mm




I-35 ,o -^ -


*i-45 4^ p y --
16~ 1 00










10-50 .. .9
-50 L ---- -----L- L-L-L-L _ _____









10 12 1 16 1 8 2 0 22 24 1 14 1 1 264 2
ency Gz)Freq. (GHz)Fun GH

Figure 4-11. Measured input impedance of on-chip zigzag dipole antennaof frequency
-15






















4.3 High-speed CMOS Frequency Divider

High-speed frequency dividers play a critical role in various wireless applications.

For the implementations of frequency dividers, as shown in figure 4-12, there are
-205


-30 _

.~-354

-40

-45

-50
16 18 20 22 24 26
Freq. (GHz)

Figure 4-11. Measured antenna gain as a function of frequency



4.3 High-speed CMOS Frequency Divider

High-speed frequency dividers play a critical role in various wireless applications.

For the implementations of frequency dividers, as shown in figure 4-12, there are








basically three configurations: 1) injection-locked dividers, 2) flip-flop-based dividers, 3)

regenerative dividers.


%f -f =f/2 D A 1 Q1 D Q2--
SOscillator 'tf' /2 LATCH 1 LATCH2 f =f Q/2
9- / T LAT9l I =,2 /
fI fn _


(a) (b)


I I 4 fo f,,/2

LPF


(c)

Figure 4-12. Frequency dividers: (a) injection-locked divider; (b) flip-flop-based divider;
(c) regenerative divider.

Although all of these three frequency dividers have shown the capability of

working at very high frequency in recently published papers [Tie04, Who02, Lee04],

regenerative frequency dividers require many functional blocks to guarantee frequency

division. As a result, they are not the best choice for embedded test circuits which

emphasize on simplicity and area efficiency.

An injection-locked frequency divider is a free running oscillator which locks at the

sub-harmonic of the injected input signal. The input signal can be injected through

different nodes of an oscillator, and depending on the injection node, different injection-

locked performances can be observed. Usually L-C oscillators are being studied as

injection-locked frequency dividers since they are fast, simple, low power and low phase

noise, though other kinds of oscillators can be injection-locked as well. Hence, most

injection-locked frequency dividers in this chapter are based on L-C oscillators. One








more feature of injection-locked frequency divider is that the power level of input signal

can be much less than that of the output signal. However, with the use of passive

components, the area requirements need consideration for L-C oscillators at not very high

frequencies.

Compared with regenerative dividers and injection-locked dividers, flip-flop-based

dividers are static frequency diviers. They are comprised of two D-latches in cascade and

in a negative feedback configuration as seen in figure 4-12(b). High-speed flip-flop-based

frequency dividers are typically implemented using the current-mode-logic (CML)

latches. Without using passive components, flip-flop-based frequency dividers achieve a

wider bandwidth than other types of frequency dividers with smaller design areas. A

major disadvantage associated with flip-flop-based frequency dividers is the high power

dissipation especially at higher frequencies due to the proportional relationship between

the power and operating frequency.

In this dissertation, frequency dividers are specifically used in wireless

RF/Microwave test signal generation, which is required to generate a quite "clean" test

signal from a "clean" while small amplitude input signal. Therefore, besides functioning

as frequency-division, frequency dividers are also required not to degrade the qualities of

the signal and have a good driving capability.

Based on the above concern and the discussion of different frequency dividers,

when implementing the test signal generation, a frequency divider based on L-C

oscillator can be used together with flip-flop-based frequency divider as well in the need

of multi-stage frequency dividers.








To investigate the performance of frequency dividers, several designs of frequency

dividers are manufactured with 0.18 um IBM technology, all of which are listed in table

4-4. The theoretical work of injection locking and pulling of oscillators is summarized in

the next section. The design, simulation and measurement results of frequency dividers

based on L-C oscillator are given in subsection 4.3.2. And in the subsection 4.3.3, the

design, simulation and measurement results of flip-flop-based frequency dividers are

discussed.

Table 4-4. Frequency dividers studied in this chapter
Index Frequency Divider Free Running Frequency Comments
I Ie ion-l 5 NMOS-only L-C oscillator, single-
1 Injection-locked 5.6 GHz ended injecting input
____-__________________ended inj eating input____
2 Injection-locked 12 GHz NMOS-only L-C oscillator, Pseudo-
2 differential-ended injecting input
3 Injection-locked 12 GHz Fully differential stacked CMOS
4, Injcton-oced2TTCMOS L-C oscillator with single-
4 Injection-locked 12 GHz e d ien input
ended direct injecting input
5 Flip-flop 5 GHz Fully differential CMOS without
________ ___________________passive components


4.3.1 Injection Locking and Pulling of Oscillators

Many studies of injection locking have been published since the 70s in the last

century [Adl73, Rat99, and Raz03]. But the date that the phenomenon of injection

locking was observed can be traced back to as early as the 17th century, when Christian

Huygens1, confined to bed by illness, noticed that the pendulums of two clocks on the

wall moved in unison if the clocks were hung close to each other [Raz03]. As a matter of

fact, injection pulling and locking can occur in any oscillatory system, such as lasers,

mechanical machines and electrical oscillators.


1 Huygens is known for inventing the pendulum clock, discovering the nature of the rings around Saturn
and numerous other accomplishments.








Here, only the injection locking of L-C oscillators are concerned. Sometimes, this

phenomenon, also called injection pulling in communication system, is undesirable. For

instance, as shown in figure 4-13, in an RF transmitter, when VCO and power amplifier

(PA) are integrated on the same chip and the large output signal of the PA has the

frequency close to that of a VCO, a portion of this signal can couple into the VCO

through substrate and pull the VCO output, resulting in an unstable and noisy VCO

output. Hence, the system and circuit approaches to reduce the interaction between VCO

and incident signals are required, some of which can be found in the reference [Li04].

However, for the design of high speed frequency divider, injection locking can be proved

to be a useful technique.

MIXER

BPF PA




0
MIXER

Figure 4-13. Injection pulling in an RF transmitter

A general model which is used to analyze the injection-locked oscillator is depicted

in figure 4-14. Without the injection signal Vi, the model is just an autonomous system

representing a free running oscillator. The nonlinear effects in the oscillator can be

modeled as a function F(e) followed by a band-pass filter H(co) with the center frequency

Wo at the free running frequency of the oscillator. Considering Vi injected into the model,

with the well-known Nyquist criterion for oscillation (loop gain equal to 1 and phase shift

equal to multiple of 27t), the Adler equation [Adl73], which is given by


'9








dO Co 0V.
o = o ... sin8 (4-1)
dt 2Q V,

can be derived, where coi is the angular frequency of the incident signal, co is the angular

frequency of the output signal, Q is the quality factor of the L-C tank and 6 is the phase

shift between the output signal and the injection signal.



Vi e u V

A BPF



Figure 4-14. Injection-locked oscillator model



For the oscillator to be locked by the injection signal, the phase shift 0 must remain

constant with time. Therefore, from equation 4-1, the maximal locking range AcO can be

obtained as

A.-=2(o),- w)= sin 0- -<0 (4-2)
QVo Q V

and with this expression of Aco, several design insights of injection-locked oscillator can

be observed:

1) Operating frequency of the injection-locked frequency divider has little effect on

the locking range since the quality factor of the oscillator will increase with the

increasing of the operating frequency.








2) At the same operating frequency, the quality factor of the oscillator should be

minimized to widen the locking range. The quality factor of an L-C oscillator can

be approximately given by
1 1 1
1 = I+(4-3)
Q QL QC

where Q, QL and Qc are the quality factors of the oscillator, inductor and

capacitor, respectively. For the oscillator working at below several gigahertzes, Q

is dominated by QL so that using high-Q inductor directly leads a smaller locking

range. For higher frequency regime, since QL is not much less than and even more

than Qc, more considerations need to be taken to adjust the quality factor of the

oscillator.

3) The increasing of the injection signal can help the widening of the locking range.

It can be easily understood that stronger the injection signal is, more efficiently it

affect the oscillator. Intuitively, the performance of phase noise can be improved

by the increasing of the injection signal as well, which will be discussed later.

4) The amplitude of the oscillator output signal should be limited to improve the

locking range, which means that, without the injection signal, the oscillator should

work at current-limited domain not voltage-limited domain. In this domain, the

oscillator amplitude is solely determined by the tail current source and the tank

equivalent resistance [Haj99].

5) The locking range is symmetric to the free running frequency of the oscillator.

That is, the output center frequency of the injection-locked frequency divider is

the free running frequency of the oscillator.






6) For the operation of a divide-by-n divider, w, in equations (4-1) and (4-2) should
be replaced by cow/n and 0 in equations (4-1) and (4-2) represents the relative
phase shift between ci/n and co,.
The graphic solution based on the model in figure 4-14 can generate the same
locking range as well. In this way, the input signal and output signal can be represented
by phasors:
v.i = Vie (4-4)

V = Vo e1 (4-5)
when locking happens, ci=coo and 0, is the phase shift between the input signal and the
output signal. Further, if the phase shift between e and Vo is defined as (o and the phase
shift contributed by bandpass filter is if, V should be equal to -(p to satisfy Barkhausen's
criteria.

vi e



-----------------e



Figure 4-15 Phasor representation of injection-locked oscillator model

As shown in figure 4-15, (p can be represented by 60o and the amplitudes of vi and V0,
which is given by:








(o = arctan(Vi sin 0, /(V, cos 0, + V,)) (4-6)

The transfer function of bandpass filter can be represented by H(co).

H(o) = A (4-7)
1 + j2Q(o co) / co,

Hence, the phase shift of H(w)is:

= -arctan(2Q(oj &,) / o,) (4-8)

From (4-6) and (4-8) and using the relationship between V and qp, it can be

obtained:

Vi sin0 2Q(& o,0)
V, cos0+, Co (49)
Ao= 2(o -o,)= V) sinO= co V
QVcos9o+Vo Q V

which is the same as the locking range derived from Adler's equation.

Furthermore, if the frequency of the injection signal falls out of, but not very far

from the lock range, then the oscillator is said to be "pulled" [Raz03], as seen in the right

part of figure 4-13.

Excellent phase noise performance is one of the major features to apply injection-

locked oscillator as frequency divider. If there exists phase noise in an injection-locked

frequency divider, then the input-output phase shift is no longer constant and can be

written as

0=0o +0n (4-10)

where 60 is the constant input-output phase shift in the absence of noise and On is the

time-variant portion of 0, accounting for the additional noise. Substituting equation (4-10)

into (4-1), it can be obtained that








dO, o- Vsin(+ )
0-coo oj; ..... 0 +0,
dt 2Q V,

=c Co - [sin 0 cos O + cos sin O] (4-11)
S2Q V.
=0 ) co.- -0 *-.W-L-cosO.
-2Q VinO Q ,

where V,' represents the sum of the injection signal V, and injected noise V,, and

reasonable assumptions that both 6o<<1 and Vn<
equation into the form of a transfer function of filter, with the help of equation (4-2) it

becomes

0)0 Vi'
o l 2Q .. . *sin 0 A

co + *-. -- Cos 00 + j
2Q Vo WC

where

A tan 0o
V.i (4-13)
co o -.L .cosO
= 2Q V,

Hence, the injected noise is shaped by a low-pass filter before it becomes the phase noise

of the output signal, which is consistent with the results obtained by Rategh [Rat99]. The

injection-locked frequency divider has the same noise transfer function as a first-order

PLL. From equations (4-12) and (4-13), it is clear that the phase noise will decrease as

the increasing of the injection signal, which intensifies the conclusion resulting from the

analysis of the locking range.








Razavi [Raz03] explained from a time-domain perspective that the "synchronizing"

effect of injection manifests itself as correction of the oscillator zero crossings in every

period, thereby lowering the accumulation of jitter. He concluded that (1) the reduction of

phase noise depends on the injection level, and (2) the reduction reaches a maximum for

coi=co. These two conclusions can be verified by our derivation as well. For example,

when cwi=co, which means no phase shift between input and output, A in (4-13)

approaches zero, which minimizes the gain of the phase noise transfer function and the

phase noise is minimized.

In the following sections, the simulations and measurements of injection-locked

frequency divider designs will be used to verify the above theoretical analysis.

4.3.2 An 11.2 GHz Injection-locked frequency divider

An 11.2 GHz injection-locked frequency divider was designed first, which uses a

simple NMOS-only VCO structure, as illustrated in figure 4-16. The free running

frequency of the VCO (j0 = l/(2-,zL-C)) is 5.6GHz. A 1.2 V Vdd and 4.6 mA bias

current give a power consumption of 5.5 mW. The varactors in figure 4-16 are

accumulation-mode nMOS capacitors. The quality factor of these varactors at 5 GHz is

estimated to exceed 60. The quality factor of the LC tank is thus dominated by the

inductors, as expected.

Before treating the circuit in figure 4-16 as a frequency divider, it is interesting to

investigate the basic characteristics of it as a VCO. First, the relationship among Vbias,

free-running frequency and output power is studied. Under the condition that the tuning

voltage of the varactors is fixed and no injected signal is applied, figure 4-17 shows the

measurement results of variations of free-running frequency and output power as a








function of the bias voltage. The bottom limit of Vbias is determined by Nyquist criterion

for oscillation, the oscillation power at which is just above the noise floor. The maximum

Vbias is limited by the maximum voltage which can be applied on the gate of MOS

transistor Ml, which is 1.8 V for 0.1 Sumrn IBM technology. It can be observed that the

free-running frequency of the VCO is almost independent of the bias voltage, especially

at higher level of Vbias, which means the oscillation becomes more stable as Vbias

increases. As for the output power, it increases as Vbias increases until Vbias reaches 1.0 V

and then become saturated. This is reasonable since the output of VCO moves from

current-limited regime to voltage-limited regime as Vbias increases [Haj99].




Vddl npu

Li L2
3.2nH 3.2
vutp
-3.
M4 M5
M23 M3
6.3/0.18 6.3/0 18

18/0.18H
Vbia

Figure 4-16. An 11.2 GHz injection-locked frequency divider based on L-C oscillator

The function of nMOS varactors is to tune the free running frequency of the

oscillator by adjusting their control voltage. The voltage of nMOS varactor can be

adjusted within a range of-0.5 V ~ 1.0 V. Figure 4-18 shows the measured tuning range

and output power of the VCO. It can be observed that the VCO can achieve a 14% tuning

range and contribute little to the variation of the output amplitude, which is less than 1








dBm within the whole tuning voltage range. Hence, with the help of the varactors, the

bandwidth of the frequency divider can be extended.


5.80

1 5.75

S5.70

S5.65

"5.60
LL
u.
) 5.55

5.50

0 5.45


5.40


-4-frequency
--M power


E
"o
-20 "
o
0
IL
-30 S
0.
0
-40


-50


Vbias (V)

Figure 4-17. The measurement results of variations of free-running frequency and output
power as a function of the bias voltage.

6.6 -------20.0
6.5 -20.2
6.4 -20.4
I 6.3 --20.6
-20.8
6.1 -21.0
S6.0 -
-21.2 0
CR 5.9 -21.4
(u -5.8
5.7 --Frequen -21.6
5.6 -Power -21.8
5.5 -22.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Vtune (V)

Figure 4-18. Oscillation frequency and output power as a function ofvaractor tuning
voltage.









When the VCO in figure 4-16 is employed as a frequency divider, it becomes a

non-autonomous system with an input serving as an injection point. Here, the injection

point is chosen at the gate of transistor M1 since (1) the required incident power can be

reduced efficiently by injecting the signal to a high impedance node and (2) the common

source connection of M2 and M3 oscillates at twice the frequency of the output signal

even in the absence of the incident signal [Rat99].

-150





.170 ---- ---
-' 5 ....... ...... ............... ....... ....... ..................... -.....




-. . ......... . . -. . ....-- .- -.. .... .
100
S0 10,2 104 106 100 110 112 11.4 116 11 6 12.0
Frequency !GHzz

(a)

1110

114 .... -:. .... .i ......... "......... .-..... .. ...... .. ..--



1135 ---------1------- I -------------------.D--- ------ ------ -----
1! 0 .. ..... ... : .... .... ... ..... ; .. ..... -. J ............ . . . . .
-= 1 9 ... . ........... J .................... 1 ..........- II _- "_ I_ __ ---- -- i - --,- - -

*25 iE --- -15 ...... .5.. 0 5.1 8..............
: i i .2....... ......... .......... .........
,0,~~~~~~~~~ ... . . . . . . . .--------- -il~iiiiiiiii i
.20 .......... ......... .. ........ I.... .. . .
10 6 - ', ....,....',
J J I',
r ,100


1 .25 -20 .1 .10 -5 0 0 0 50 4 0.9 11'a ill 11_2 113 114 11 5
Injection Power (dBmn) Input Frequency (GHz)

(b) (c)

Figure 4-19. (a) Measured S11 parameters; (b)Locking range as a function of incident
signal power; (c) Relationship between minimum injection power and input
frequency.








In addition, a wide-band input matching is formed by shunting a 50 ohm resistor

with the gate of Ml as shown in figure 4-16. The stability of this input matching has been

verified by measured SII parameters at interesting input frequency band. The results are

shown in figure 4-19 (a).

From measured S11 parameters, it can be observed that there is a glitch at 11.26

GHz, which is just at twice the oscillating frequency. This phenomenon further proves

the selected input point is a natural injection point for divide-by-two frequency divider.

Figure 4-19 (b) shows the locking range of this frequency divider as a function of

injection power. As expected in theoretical analysis, the locking range increases as the

injection power increases.

Figure 4-19 (c) is just another expressing form of figure 4-19 (b), which shows the

relationship between minimum injection power and input frequency. Both of figure 4-19

(b) & (c) show the locking range is exactly symmetric with the free-running frequency of

the VCO. And the injection power can be correctly estimated by use of

Pj. = P measuree -(1-$S1112) (4-14)

where Pmeasure is the signal power at the output of the signal source, and Pij. is the actual

signal power injected into the VCO.

A comparison of the circuit in figure 4-16 working as a VCO and a divide-by-2

frequency divider is shown in figure 4-20, next to which is the test setup. To obtain a

good phase noise performance, it is desirable to use battery to supply DC biases.









0

-20 -

-40

-60

-80 -

-100

-120


5.584 5.585 5.585 5.586 5.586 5.587 I ProbeI I Anaiyzel
Frequency (GHz)

Figure 4-20. Measurement results of frequency sweep of oscillator as a VCO and a
frequency divider.

4.3.3 A 24 GHz Pseudo-differential Injection-locked Frequency Dividers


]


OUT+


I IN- IN+ I

Figure 4-21. Pseudo differential injection-locked frequency divider

Considering connecting with other circuits, it is desirable to use differential-input

frequency dividers. Here, a pseudo differential-input structure is used as displayed in

figure 4-21. The measurement results of the fabricated circuit are shown in figure 4-22.


I-----------------
Signal
Generator

SG-S-G
PPrrobe

FrequenAcy7
Divider
([wco)

f&TS Gl J Spectrum


OUT-











0 12 15
F
[*11 _____ _
I ~-15
10
. iE -20
0 9 :E ,
0 9 N-25
0 0.5 1 1.5 2 2.5 22.8 23 23.2 23.4 23.6 23.8 24
Control (V) Input Frequency (GHz)

(a) (b)

Figure 4-22. Measurement results of pseudo-differential injection-locked frequency
divider: (a) variation of free running frequency; (b) input sensitivity of
frequency divider.


4.3.4 A 22.4 GHz Fully Differential Injection-locked Frequency Divider

Two topologies of differential injection-locked frequency dividers have been

examined. Pseudo-differential divider can follow a differential circuit with the need of

balun but the actual injected power is still the same as single-ended divider. Direct

injection-locked frequency dividers can have a wide input locking range only for a large

injection signal. So, is it possible to implement a real differential injection locked

frequency divider with high input sensitivity?

From basic NMOS-only and PMOS-only injection-locked frequency dividers as

shown in figure 4-23, it can be observed that, if the signals injected to both dividers are

exactly the same except for a phase difference of 180 degrees, the outputs of both

dividers can be connected together to form an output signal with larger swing. In this

way, the topology in the right of figure 4-23 is proposed to form a stacked fully

differential injection-locked frequency divider. The fabricated circuit is shown in figure

4-24.





; 82


Vbiasp Vdd
'V!dd Vd







Vo tV oumout o
Vinj-+
b iasI -
V d d V O ~ t P t u n e .


L V 'P 3


I --- _. ---- 1 Vbiasn^- ^
V !


V V bias

Figure 4-23. A stacked fully differential injection-locked frequency divider (new
topology)


differential outut

DC }D




differential input
Figure 4-24. Photomrnicrograph of the proposed stacked fully differential injection-locked
frequency divider









Furthermore, it can be proven that combining two basic frequency dividers of same

type (NMOS-only or PMOS-only) does not work out because, in this case, the

waveforms at the output nodes of both dividers can not have the same phase. This can be

explained from the point of phase change as well. If the combined dividers are the same

type, then the phase difference at outputs of two dividers is 90 degree for an input phase

difference of 180 degree. Here the dividers are assumed to be divide-by-2. On the other

hand, if two combined dividers are NMOS-only and PMOS-only, the phase difference at

outputs of two dividers is 180 degree for an input phase difference of 180 degree since

another 180 degree phase difference is added at the inputs of two dividers by the nature

of using different types of injection transistor.




0 00
>, 15 . ... -.... ..
0~ o
S -15 .......

-20
-25

~0
12 ........ . .... . -35. .... .
0 0.5 1 1.5 2 2.5 3 23.5 24 24.5 25 25.E
Control (V) Input Frequency (GHz)

(a) (b)

Figure 4-25. Measurement Results of stacked fully differential injection frequency
divider: (a) variation of free running frequency; (b) input sensitivity of
frequency divider.

Figure 4-25 shows the measurement results of the proposed stacked fully

differential injection-locked frequency divider. It can be seen that, compared to those of

pseudo-differential divider, both input sensitivity and input locking range have been









improved since the actual power injected into the core has been increased about 3 dB for

the same injection signal.

-104.6 180 deg-
.- -104.8 --.- 181 deg
S-105.0 182 aeg
-105.2 1 0
tde
105.
-105.4
0
-105.6
c -105.8 -si
-106.0 I,,
1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07
relative frequency (Hz)

Figure 4-26. Simulated phase noise performance under the effect of the injected phase
distortion

To investigate the effect of the injected phase distortion resulting from the different

speed between input PMOS and NMOS transistors, simulations under various phase

difference between two signals injected to the PMOS and NMOS tail transistors,

respectively, as shown in figure 4-23, are run with spectre simulator. The resulted

simulation phase noise performance is shown in figure 4-26. It can be seen that, for small

phase distortions, which is the usual case for the phase distortion caused by different

speed between input PMOS and NMOS transistors, the output still can be still locked to

the input differential signal though the phase noise performance become a little worse.

4.3.5 A 24 GHz Direct Injection-locked Frequency Divider

Recently a new scheme to implement injection-locked frequency divider based on

L-C oscillator is proposed [Tie04, Yam03], in which the incident signal is directly

injected to the L-C tank through an extra transistor M4 instead of the tail transistor Ml as

shown in figure 4-27. This injection scheme is believed to be more efficient at very high









frequencies because usually Ml has to be laid out with a large width to provide tail dc

current and results in a large parasitic capacitance at the tail node, which includes Cgd and

Cdb of Ml as well as Csb of M2 and M3. The effect of this parasitic capacitance becomes

evident with the increase of oscillating frequency and lowers the effective injected power

if the incident signal is injected through Ml.

Vdd
7-T
24/0.18 24/0.18
M6 M5

Vbias2
M4 18/0.18
LI 0.8nH
voutnl
V C, v ) V

M8- -1- -2I--] M7
M2 M3
12/0.18 12/0.18 "
Tail node 24/0.18 Vbi1



Figure 4-27. A 24 GHz directive injection-locked frequency divider

However, from simulations, it has been observed that the VCO can not be locked

until the incident signal reaches a large power level, which can be explained examing the

switching function of injection transistor M4.

The fabricated circuit is shown in figure 4-28. The measurement results are shown

in figure 4-29. Compared with other types of L-C based injection-locked frequency

dividers, direct injection-locked frequency divider requires a higher injection power to

lock the frequency of input signal and the input locking range will not be enough wide

until the injection signal reaches a high power level.






86


input bondpads (gnd, signal, gnd)
',i' l m.. u.


DC bias bondpads
DC bias bondpads


Figure 4-28. Fabricated direct injection frequency divider


15
N
a14
U
I 13
U-
12
--11
10
010


0 0.5 1 1.5
Control (V)


S--2 -

0~
? 2 --- /y^-
S-6
-8
-910
E
E -12 --- -_--
-14
5 22 23 24 25
Input Frequency (GHz)


Figure 4-29. Measurement results of direct injection frequency divider: (a) variation of
free running frequency; (b) input sensitivity of frequency divider.



4.3.6 A 10 GHz Flip-flop-based Frequency Divider

A flip-flop-based frequency divider is a wide-bandwidth frequency divider.

Without using any on-chip inductors and capacitors, it consumes the smallest area among

all kinds of frequency dividers. But it suffers from higher power dissipation with the


__i


10