Production scheduling algorithms for semiconductor test operations

MISSING IMAGE

Material Information

Title:
Production scheduling algorithms for semiconductor test operations
Physical Description:
x, 164 leaves : ill. ; 29 cm.
Language:
English
Creator:
Uzsoy, Reha, 1963-
Publication Date:

Subjects

Subjects / Keywords:
Production scheduling   ( lcsh )
Production management   ( lcsh )
Semiconductors -- Testing   ( lcsh )
Semiconductors -- Quality control   ( lcsh )
Industrial and Systems Engineering thesis Ph. D
Dissertations, Academic -- Industrial and Systems Engineering -- UF
Genre:
bibliography   ( marcgt )
non-fiction   ( marcgt )

Notes

Thesis:
Thesis (Ph. D.)--University of Florida, 1990.
Bibliography:
Includes bibliographical references (leaves 155-163).
General Note:
Typescript.
General Note:
Vita.
Statement of Responsibility:
by Reha Uzsoy.

Record Information

Source Institution:
University of Florida
Rights Management:
All applicable rights reserved by the source institution and holding location.
Resource Identifier:
aleph - 024458560
oclc - 23725694
System ID:
AA00022518:00001

Table of Contents
    Title Page
        Page i
        Page ii
    Acknowledgement
        Page iii
        Page iv
    Table of Contents
        Page v
        Page vi
        Page vii
        Page viii
    Abstract
        Page ix
        Page x
    Chapter 1. Introduction
        Page 1
        Page 2
        Page 3
        Page 4
        Page 5
        Page 6
    Chapter 2. Physical situation
        Page 7
        Page 8
        Page 9
        Page 10
        Page 11
        Page 12
        Page 13
        Page 14
        Page 15
        Page 16
        Page 17
    Chapter 3. Literature review
        Page 18
        Page 19
        Page 20
        Page 21
        Page 22
        Page 23
        Page 24
        Page 25
        Page 26
        Page 27
        Page 28
        Page 29
        Page 30
        Page 31
        Page 32
        Page 33
        Page 34
        Page 35
        Page 36
        Page 37
        Page 38
        Page 39
        Page 40
        Page 41
        Page 42
        Page 43
        Page 44
        Page 45
        Page 46
        Page 47
        Page 48
        Page 49
        Page 50
        Page 51
        Page 52
        Page 53
    Chapter 4. Modelling approach
        Page 54
        Page 55
        Page 56
        Page 57
        Page 58
        Page 59
        Page 60
        Page 61
        Page 62
        Page 63
        Page 64
        Page 65
        Page 66
        Page 67
        Page 68
        Page 69
    Chapter 5. Single-machine workcenters
        Page 70
        Page 71
        Page 72
        Page 73
        Page 74
        Page 75
        Page 76
        Page 77
        Page 78
        Page 79
        Page 80
        Page 81
        Page 82
        Page 83
        Page 84
        Page 85
        Page 86
        Page 87
        Page 88
        Page 89
        Page 90
        Page 91
        Page 92
        Page 93
        Page 94
        Page 95
        Page 96
        Page 97
        Page 98
        Page 99
        Page 100
        Page 101
        Page 102
        Page 103
        Page 104
        Page 105
        Page 106
        Page 107
    Chapter 6. Batch processing machines
        Page 108
        Page 109
        Page 110
        Page 111
        Page 112
        Page 113
        Page 114
        Page 115
        Page 116
        Page 117
        Page 118
        Page 119
        Page 120
        Page 121
        Page 122
        Page 123
        Page 124
        Page 125
        Page 126
        Page 127
        Page 128
        Page 129
        Page 130
    Chapter 7. Prototype implementation of approximation methodology
        Page 131
        Page 132
        Page 133
        Page 134
        Page 135
        Page 136
        Page 137
        Page 138
        Page 139
        Page 140
        Page 141
        Page 142
        Page 143
        Page 144
    Chapter 8. Summary and future directions
        Page 145
        Page 146
        Page 147
        Page 148
        Page 149
        Page 150
        Page 151
        Page 152
        Page 153
        Page 154
    References
        Page 155
        Page 156
        Page 157
        Page 158
        Page 159
        Page 160
        Page 161
        Page 162
        Page 163
    Biographical sketch
        Page 164
        Page 165
        Page 166
        Page 167
Full Text















PRODUCTION SCHEDULING ALGORITHMS FOR SEMICONDUCTOR TEST OPERATIONS














By

REHA UZSOY



















A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY


UNIVERSITY OF FLORIDA UtIVERNlTY OF FLORIDA LIBRARIES 1990





















As you set out for Ithaka hope your road is a long one, full of adventure, full of discovery. Laistrygonians, Cyclops, angry Poseidon -- don't be afraid of them: you'll never find things like that on your way as long as you keep your thoughts raised high, as long as a rare excitement stirs your spirit and your body. Laistrygonians, Cyclops, wild Poseidon you won't encounter them unless you bring them along inside your soul, unless your soul sets them up in front of you.


Keep Ithaka always in your mind. Arriving there is what you're destined for. But don't hurry the journey at all. Better if it lasts for years, so you're old by the time you reach the island, wealthy with all you've gained on the way, not expecting Ithaka to make you rich. Ithaka gave you the marvelous journey. Without her you wouldn't have set out. She has nothing left to give you now.

And if you find her poor, Ithaka won't have fooled you. Wise as you will have become, so full of experience, you'll have understood by then what these Ithakas mean.



C.P. Cavafy

















ACKNOWLEDGEMENTS



I would like to extend my sincere appreciation to Dr. Louis A. Martin-Vega, chairman, and Dr. Chung-Yee Lee,

cochairman of my supervisory committee, for their guidance and assistance without which this work could not have been completed. Their excellent teamwork, their excellent advice on matters academic and otherwise and their willingness to sit down and reason with a stubborn Turco-Scot have set me an excellent example to follow throughout my career.

Thanks are also due to Dr. D.J. Elzinga, Dr. Sencer Yeralan and Dr. Selcuk Erenguc for serving on my supervisory committee and providing me with valuable assistance and feedback as the work progressed. I should also like to thank Dr. Elzinga for helping me start my teaching career. special thanks are due to Dr. B.D. Sivazlian for serving on my

committee for a time and for his support and encouragement throughout.

I would also like to acknowledge the support of Harris

Semiconductor, which made it possible for me to work in a real-world environment which motivated the research in this dissertation. I would especially like to thank Mr. T. Haycock, iii








Mr. P. Leonard, Mr. J. Rice and Mr. J. Hinchman for their assistance and cooperation over the last two years. It has been a pleasure to work with them.

Without the support of my family and friends this work would never have been completed. To my parents, Nancy and Safak Uzsoy, goes my appreciation for their unfailing

confidence, support, the excellent opportunities they have given me and the excellent example they have set me. Special thanks are due to my roommates over the last four years, who have lived a good deal of the Ph.D experience with me: David and Farah Ramcharan, Irfan Ovacik and Haldun Aytug. Among my friends, Elias Stassinos, Serpil Unver, Clara Azcunes and Roberto Cavalieros deserve special mention. Finally, to Gerry Chestnut goes my heartfelt thanks for her support and confidence over the last difficult months, and for showing me how much growing up I still have left to do.






















iv















TABLE OF CONTENTS


ACKNOWLEDGEMENTS .....................................

ABSTRACT ............................................. ix

CHAPTERS

I INTRODUCTION ................................... 1

Objectives of Dissertation ...................... 4

Outline of Remaining Sections ................... 5

II PHYSICAL SITUATION .............................. 7

The Semiconductor Manufacturing Process ........ 7 The Semiconductor Testing Process ............... 10

Management objectives in Semiconductor Testing .. 15 III LITERATURE REVIEW ............................... 18

Introduction .................................... 18

Scheduling Theory ............................... 18

Job Shop Scheduling ........................... 19

Branch and Bound Algorithms ................. 24

Improvement-based branch and bound
algorithms .............................. 24

Conflict-based branch and bound
algorithms .............................. 26

Flowshop Scheduling ......................... 28

Heuristic Approaches ........................ 29

Shifting Bottleneck Approach ................ 31

Summary ..................................... 35

v









Single and Parallel Machine Scheduling............35

Single-Machine Scheduling..................... 36

Parallel Machine Scheduling................... 42

Batch Processing Machines..................... 43

Research on Semiconductor Manufacturing..........45 Sum~mary.......................................... 52

IV MODELLING APPROACH................................. 54

Introduction....................................... 54

Modelling of Job Shop.............................. 54

Disjunctive Graph Representation.................. 57

Approximation Methodology.......................... 61

Step 3: Determination of Critical Workcenter 63

Step 4: Sequencing of the Critical Workcenter 65

step 5: use of Disjunctive Graph to Capture
Interactions................................... 66

Step 6: Resequencing in the light of new
Information.................................... 68

Experimentation with Overall Methodology............68

V SINGLE-MACHINE WORKCENTERS.......................... 70

Introduction....................................... 70

Description of a Single-Machine Workcenter.........70 Minimizing Maximum Lateness....................... 73

Algorithms for 1/prec,SDST/Lmax................. 74

A branch and bound algorithm for
1/prec, q,,SDST/Cmax......................... 74

Dynamic programming algorithms for
1/prec,SDST/Lmax............................. 82

Heuristic Procedures for
1/r,prec,q,SDST/Cmax........................ 85

vi









A Neighborhood Search Algorithm .............. 91

Minimizing the Number of Tardy Lots ............. 95

A Heuristic Procedure for 1/precSDST/ZUi "1 96 Worst-Case Analysis for 1/SDST/ZUi ........... 100

Dynamic Programming Procedures for
1/precSDST/ZUi ............................ 103

Summary ......................................... 105

VI BATCH PROCESSING MACHINES ....................... 108

Introduction .................................... 108

Assumptions and Notation ........................ 109

Minimizing Total Flowtime ....................... 111

Minimizing Maximum Tardiness .................... 113

Minimizing Number of Tardy Jobs ................. 121

Parallel Batch Machines ......................... 125

Summary ......................................... 129

VII PROTOTYPE IMPLEMENTATION OF APPROXIMATION METHODOLOGY .................................... 131

Introduction .................................... 131

Implementation Environment ...................... 132

Implementation of Approximation Methodology ..... 133 Computational Testing ........................... 138

Experimental Results ............................ 139

Summary and Conclusions ......................... 143

VIII SUMMARY AND FUTURE DIRECTIONS ................... 145

Summary of Accomplishments ....................... 145

Single and Parallel Machines ..................... 147

Batch Processing Machines ........................ 149


vii








Overall Approximation Scheme ..................... 151

REFERENCES ........................................... 155

BIOGRAPHICAL SKETCH .................................. 164

















































viii
















Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy


PRODUCTION SCHEDULING ALGORITHMS FOR SEMICONDUCTOR TEST OPERATIONS


by

Reha Uzsoy

August 1990



Chairman: Dr. Louis A. Martin-Vega Cochairman: Dr. Chung-Yee Lee Major Department: Industrial and Systems Engineering

We consider a class of job shop scheduling problems motivated by semiconductor test operations but having broad applicability in other industries. Since the problem is NPhard, we present an approximation methodology which proceeds

by dividing the job shop into a number of workcenters and scheduling these sequentially. A disjunctive graph is used to capture interactions between workcenters. The performance measures to be minimized are maximum lateness and number of tardy jobs.

The development of such an approximation methodology requires efficient means of scheduling the individual workcenters. In this dissertation we first consider ix








workcenters consisting of a single machine. The problems of scheduling these machines are characterized by latenessrelated performance measures, sequence-dependent setup times and precedence constraints, and are thus NP-hard. We provide optimal implicit enumeration algorithms and heuristics with tight error bounds for a number of these problems.

Another type of workcenter considered consists of batch processing machines. A batch processing machine is one where a number of jobs are processed simultaneously as a batch. We

present polynomial-time solution procedures for a number of problems of scheduling workcenters consisting of single or parallel identical batch processing machines.

Finally, we demonstrate how some of the algorithms

developed can be integrated into the overall approximation methodology and discuss future research.
























x















CHAPTER I

INTRODUCTION





The area of scheduling deals with the problem of

allocating a collection of scarce resources over time to perform a number of tasks. While first conceived in a production context, the areas of application of scheduling theory have broadened over the years to include service industries, computer system design, vehicle routing and many others. Attempts to model and quantify the scheduling process, starting around the turn of the century, have led to the development of a broad body of knowledge in this field.

The deterministic scheduling problem can be defined as follows:

"Given a set of n 'jobs' (tasks, events, products), that have to pass through m machines (processors) under certain restrictive assumptions, determine the schedule that optimizes some measure of performance."

The development of complexity theory over the last

fifteen years has provided profound insights into the nature of scheduling problems. Due to the work of researchers like


1








2

Lageweg, Lawler,Lenstra and Rinnooy Kan[59,60], a complete classification of deterministic scheduling problems is available. This work has shown that while many scheduling problems can be solved efficiently in polynomial time, there are a great many others for which it is unlikely that such good methods exist[42,71]. For problems in the latter class, the researcher is forced to resort to heuristics for good solutions, or implicit enumeration methods to obtain optimal solutions. There have also, in recent years, been a number of attempts to apply techniques from other engineering fields such as artificial intelligence and control theory to solve scheduling problems. Interesting reviews of some of these research efforts may be found in Buxey[19] and Rodammer and White[88].

While the benefits yielded by effective scheduling vary depending on the area of application, it is clear from both theory and practice that significant differences may result from the use of different schedules. This is especially the case in industries using extremely capital-intensive technologies and operating in highly competitive markets. High competition for capacity at key resources and the importance of customer satisfaction render scheduling decisions particularly critical in such enterprises. The epitome of such industries today is the semiconductor industry.








3

The miniaturization of electronic components by means

of Very Large Scale Integration (VLSI) technologies has been one of the most significant technological developments of the last fifty years. Steadily improving technologies and decreasing prices have led to integrated circuits appearing in all walks of life. The computer revolution of the past two decades is a direct result of the ability to develop and fabricate these components economically. Integrated circuits can be found in almost every piece of military hardware in use today, rendering this industry extremely important from the point of view of national security. The development of complex Computer-Integrated Manufacturing (CIM) systems, essential to the maintenance of a competitive edge in today's volatile, global markets, is directly linked to the availability of the integrated components of the controllers, computers and communications equipment necessary for their implementation. Integrated circuits are also used in a wide range of industries, such as domestic appliances, cars and avionics. Thus it is safe to state that the importance of the semiconductor industry today is comparable to, if not greater than, that of the steel industry around the turn of the century.

Despite the widely recognized importance of this industry, it is only in the last few years that the operational aspects of semiconductor manufacturing companies are being addressed and attempts being made to bring








4

industrial engineering and operations research techniques to bear on problems in these areas. The majority of these efforts to date, however, have focused on the extremely capital-intensive and technologically complex wafer fabrication process. The so-called 'back end' operations where the chips are packaged, tested and shipped to the customer, have remained relatively unexamined.



Objectives of Dissertation

The objective of the research described in this

dissertation is to develop and apply production scheduling methodologies to certain job shop scheduling problems whose structure is derived from industrial settings. The primary motivation for the problems addressed in this proposal is found in testing operations within a semiconductor manufacturing facility although the classification of the problem is generic in nature. The purpose of these operations is the testing of the finished product to ensure that it meets the customer specifications. Since these operations do not add any value to the product, improvements in productivity resulting from more effective scheduling will reduce overhead, helping thus to reduce costs.

An important consideration throughout this research

will be the relevance of the resulting algorithms in actual real-time testing environments.








5

Outline of Remaining Sections

The purpose of Chapter II is to provide the motivation for the following sections. A broad overview of the semiconductor manufacturing process is given. Test operations are placed in this perspective and described in detail. Insights into the physical situation will enable us to derive the structure of the scheduling problems addressed in this research.

The purpose of Chapter III is to place the

research proposed here in perspective to the existing body of knowledge in the areas of both scheduling theory and semiconductor manufacturing. The first section reviews relevant results from scheduling theory which form a basis for this work. The second section reviews applications of operations research techniques to problems in semiconductor manufacturing. Finally, the contribution of this research to the above areas is discussed in the light of these reviews.

Chapter IV describes the modelling of the test facility as a job shop and the methodology with which the problem will be approached. This methodology entails decomposing the job shop into a number of workcenters and sequencing these individually, while capturing their interactions using a disjunctive graph representation of the entire facility.

Chapter V presents formulations and solution approaches to the problems of sequencing workcenters consisting of a single machine under different performance measures. Chapter








6
VI examines problems related to scheduling batch processing machines. Chapter VII gives results and insights obtained from preliminary computational experience with some of the solution procedures developed in Chapter V. In Chapter VIII we present a summary of the accomplishments of this research and directions for future investigation.














CHAPTER II

PHYSICAL SITUATION



The Semiconductor Manufacturing Process

The process by which Very Large Scale Integrated (VLSI) circuits are manufactured can be divided into four basic steps: wafer fabrication wafer probe, assembly or packaging and final testing. While the research in this dissertation is motivated by the final testing stage, we will give a brief overview of the entire process to put the testing operations in perspective and to provide the background information for some of the literature reviewed in chapter III.

Wafer fabrication is the most technologically complex and capital intensive of all four phases. It involves the processing of wafers of silicon or gallium arsenide in order to build up the layers and patterns of metal and wafer material to produce the required circuitry. The number of operations here can be well into the hundreds for a complex component such as a microprocessor. while the specific operations may vary widely depending on the product and the technology in use, the processes in wafer fabrication can be roughly grouped as follows [18]:


7








8

Clean ingr

The object of this operation is the removal of

particulate matter before a layer of circuitry is produced. Oxidation, deposition. metallization

In this stage a layer of material is grown or deposited on the surface of the cleaned wafer. Extensive setup times are involved, resulting in machines being dedicated to a limited number of operations. Lithogiraphy

This is the most complex operation, as well as the one requiring greatest precision. A photoresistant liquid is deposited onto the wafer and the circuitry defined using photography. The photoresist is first deposited and baked. It is then exposed to ultraviolet light through a mask which contains the pattern of the circuit. Finally the exposed wafer is developed and baked. Etch inca

In order to define the circuits, in this step the exposed part of the material is etched away. Ion Implantation

At this stage selected impurities are introduced in a controlled fashion to change the electrical properties of the exposed portion of the layer. Setups may range from minutes to hours.








9
Photoresist Strip

The photoresist remaining on the wafer is removed by a process similar to etching.

Inspection and Measurement

The layer is inspected and measured to identify defects and guide future operations.

This sequence of operations is repeated for each layer of circuitry on the wafer, in some cases up to 8 or 9 times. A detailed description of the technologies used in VLSI wafer fabrication can be found in specialized texts on this subject[90].

In the next stage, wafer probe, the individual

circuits, of which there may be hundreds on one wafer, are tested electrically by means of thin probes. circuits that fail to meet specifications are marked with an ink dot. The wafers are then cut up into the individual circuits or chips, known as dice, and the defective circuits discarded.

The assembly stage is where the dice are placed in plastic or ceramic packages that protect them from the environment. This entails the placing of the chip in an appropriate package and the attachment of leads. There are many different types of packages, such as plastic or ceramic dual in-line packages, headless chip carriers, and pin-grid arrays. Since it is possible for a given circuit to be packaged in many different ways, there is a great proliferation of product types at this stage. Once the leads








10

have been attached, the package sealed and tested for leaks, cracks and other defects, the product is sent to final test.



The Semiconductor Testing Process

The goal of the testing process is to ensure that

customers receive a defect-free product by using automated testing equipment to interrogate each integrated circuit and determine whether or not it is operating at the required specifications. Product flows through the test area in lots. Lots vary in size from several individual chips to several thousand and are processed as a batch. Once a certain operation has been started on a lot, every chip in the lot must be processed. The actual sequence of operations a lot will go through depends on the product and on customer specification. While there is considerable variety in process flows, a general idea of product flow can be formed from Figure 2.1. Products are also classified by primary product line, as digital, analog or data acquisition. The test area is organized into cells based on this classification.

The specific test system that a product can be tested on depends on the type of product only. Thus, each product can be tested only on a certain specific test system and there is no flow of work between different testing workcenters. Thus the sequence of one test workcenter will affect the sequence of another only due to the interaction

























0
0
0
.CO > U











c c
4-w C
(D
E c
co .0.
C
4- .0

0 cz co co

> C:
(D -C =3
cz co
co
co co
c co
> Cl)

LLJ I






















c
(D 0
4- 0 0
4

ct) 4- co 4- V) 4'2 CD
a > F W








12

at non-test operations, such as brand and burn-in.

The major operations taking place in the testing process are the following:

Brand

This operation consists of the printing of the name of the manufacturer and other information required by the customer, such as serial number, on the product package. Burn-in

In this operation the circuits are subjected to a

thermal stress of 125 degrees centigrade for a period of time generally not less than 96 hours in order to precipitate latent defects that would otherwise surface in the operating environment. This is done by loading the circuits onto boards. Each board can hold a certain number of circuits, and each circuit requires a certain specific board type. once the circuits have been loaded onto the boards, the boards are loaded into ovens. Each oven can accommodate a limited number of boards, and certain types of circuit may require a specific oven. It is possible to load a number of different lots into the same oven. However, once the burn-in process has begun, it is undesirable to open the oven to remove or insert lots. The reason for this is that the temperature drop resulting from the opening of the door biases the test, requiring extra burn-in time for all circuits in the oven at the time the drop occurred. Thus once processing has begun, no lot in the oven, i.e., in the








13

batch being processed, can be removed until the entire process is complete. Modelling of these systems as batch processing machines will be described in Chapter VI. Quality Assurance

At this step the circuits are checked visually for defects like bent leads or chipped packages, and the paperwork associated with the testing is examined to ensure that all customer specifications have been met. Testing

This is the central operation of the testing process,

and consists of the subjection of the components to a series of tests by computer-controlled testing equipment at various temperatures. Since this operation provides the motivation for the study of several of the scheduling problems examined in this research, we will describe this in some detail.

In order for a testing operation to be able to take place, the following conditions must be met:

1) The Tester, the computer-controlled device that does the actual testing, must be available. A number of testers have separate high- and low-voltage heads, which for all practical purposes function as independent testers.

2) The Handler, a device that transfers the individual chips from the load chutes to the single set of contacts connected to the tester and then to the output bin according to the result of the test, must be available. The handlers also bring the chips to the required temperature, if high-








14

temperature (1250C) or low temperature (-550C) testing is required in addition to room-temperature testing. The handler is restricted in the types of packages it can handle, and in some cases by temperature capabilities.

3) The Load Boards and Contacts, the electrical devices that form the interface between the tester and the handler must be available. These are also package, and sometimes even product, specific.

4) The Test Software, to control the tester, must be

downloaded from a host computer to the tester and activated.

Thus, we see that the operation of setting up a tester to test a certain type of product consists of

1) Obtaining the appropriate handler, load board, contacts and bringing them to the tester or test head concerned,

2) Connecting handler, contacts and load boards to the tester,

3) Bringing the handler to the required temperature,

4) Downloading the required software.

The amount of time required for these operations may be of the order of 45 minutes, which is significant compared to the processing times of the individual chips. It is also clear that the scheduling decisions can have a considerable effect on the time spent in setup. By scheduling together lots requiring the same temperature, for example, one can reduce the time spent bringing the handler to the required








15

temperature. This nature of the setup operations results in sequence-dependent setup times. It is important to note, however, that the number of distinct setup times is very limited. The time required to change a handler, or to change temperature from room to high temperature, for example, is well known. Thus it is possible to characterize all possible setup changes with less than 10 different times. This factor will be exploited in the dynamic programming algorithms developed in Chapter V.



Management Objectives in Semiconductor Testing

An example of the decision logic commonly used in

practice for scheduling test equipment is illustrated by Figure 2.2. Lots that are late have priority over all others. A lot is considered to be late if its due date has passed without its being delivered to the customer. Once the late lots have been determined, the major considerations, in order of importance, are the handler and the test temperature. once a tester is in a certain setup configuration, all lots requiring that configuration will be processed before a change is made. If a change becomes necessary, a change at the lowest possible level of the tree is preferred. In the event of a number of different requirements at a given level in the tree, the configuration that will service the largest number of lots awaiting processing is adopted.










16












Cco










C:j z



7D c:
CIO (10






-z 0.- CZ-.

o 0o



-;D M
0

CID) 0U





)



co







<00








17

The decision process described above provides the

motivation for examining the performance measures of maximum lateness and number of tardy lots. These performance measures reflect management concerns for better customer service through on-time delivery. Explicit consideration of the setup times in the scheduling models developed addresses the concerns of shop-floor personnel for reducing time spent in setup changes.
















CHAPTER III

LITERATURE REVIEW



Introduction

As indicated in Chapter I, the motivation for the problems addressed in this dissertation stems from particular job shop characteristics and parameters found in semiconductor test operations. This has led to the identification of a set of problems that are not only meaningful and original from an application perspective but also within the general context of the theory of job shop scheduling. The first part of this review will focus on the body of scheduling theory that is relevant to this research. The second section will cover research that has been carried out in industrial engineering and operations research related to modelling and analyzing semiconductor manufacturing operations in general.



Scheduling Theory

In this section we will present a review of the body of scheduling theory that serves as a basis for this research. We shall begin with the general job shop scheduling problem,


is








19

which is the central theme of this research. Approximate methods of solving this problem which proceed by decomposing the job shop into a number of workcenters and scheduling these iteratively are examined. The subproblems occurring in these methods lead to consideration of single and parallel machine scheduling problems. Relevant literature for these classes of problems is reviewed in the following two sections.



Job Shop Schedulincr

For the purposes of this research we can define the job shop scheduling problem as follows. We are given a set of m non-identical workcenters, which may consist of a single machine or parallel identical machines, and n jobs to be processed. The sequence of workcenters which each job must visit is known a priori. The problem is to schedule the jobs on the workcenters so as to optimize some measure of performance.

The classical job shop scheduling problem referred to by that name in the literature is a special case of the above, where each workcenter consists of a single machine that is capable of processing only one job at a time. The performance measure most commonly considered is the makespan, or time elapsed from the start to the completion of the last job. This problem is represented as J//Cmax in the notation of Lageweg et al.[59,60J, and has been shown to








20
be NP-hard in the strong sense[42]. Even among NP-hard problems, it is one of the more difficult. While it is possible to solve travelling salesman problems with several hundred cities to optimality in a reasonable period of time, a 10-job 10-machine job shop scheduling problem posed by Muth and Thompson defied solution for 20 years before finally being solved by Carlier and Pinson[21] in five hours of computer time. Thus, the two main avenues of attack on this problem have been implicit enumeration methods and heuristics. Before discussing these approaches, however, let us describe the representation of the J//Cmax problem as a disjunctive graph. This representation provides useful insights into the structure of the problem and has formed the basis for some of the most successful solution approaches.



Disi~unctive giraph representation

A disjunctive graph is a graph consisting of a set of nodes N, a set of conjunctive arcs A and a disjunctive arc set E. Two arcs are said to form a disjunctive pair if any path through the graph can contain at most one of them. A conjunctive arc is simply an arc that is not disjunctive. In order to represent the job shop scheduling problem as a disjunctive graph, let us introduce the concept of operations. An operation consists of the processing of a certain job at a certain machine. The problem of scheduling








21
the n jobs on the in machines can now be viewed as that of scheduling of the operations associated with the jobs on the machines. The sequence in which the jobs have to visit the machines induces precedence constraints between operations on the same job. Let N be the set of all operations, plus two dummy operations representing a source (operation 0) and a sink (operation *) respectively. Define a node i for every operation ieN. Add a conjunctive arc (i,j) if operation i has to be performed before operation j. Disjunctive pairs of arcs link operations that can be carried out at the same machine. If we let N be the set of nodes, A the set of conjunctive arcs and E the set of disjunctive arcs, we have now obtained the disjunctive graph G = (N,A,E). Note that the set of operations N and the set of disjunctive arcs E

decompose into subsets Nk and Ek each associated with a particular machine k. With each arc (i,j), associate a cost c which corresponds to the time it takes to complete operation i. To illustrate this mode of representation, consider the following example with five jobs and four machines[l].

Job operation Machine Predecessor

1 1 1

1 2 4 1

2 3 1

2 4 2 3

2 5 4 4









22

Job operation Machine Predecessor

3 6 1

3 7 4 6

3 8 3 7

4 9 1

4 10 3 9

4 11 2 10

5 12 3

5 13 2 12



This can be represented as the disjunctive graph in Figure 3.1.

We denote by D = (NA) the directed graph obtained by deleting all disjunctive arcs from G. For each Ek, a

selection Sk contains exactly one member of each disjunctive arc pair. A selection is acyclic if it contains no directed

cycles. Each selection Sk completely defines the precedence relations of each operation to every other operation carried

out on machine k. Thus an acyclic selection S, corresponds to a unique feasible sequence of the operations to be carried out on machine k. A complete selection S is the

union of all selections Sk over the individual machines k. When we construct a complete selection, we are able to replace the disjunctive graph G = (NAE) by the conjunctive

graph D. = (N, A U S) A complete selection is acyclic if Dr is acyclic. Each acyclic complete selection S defines a








23









C\j C\j


co Ci C\j
Oj
dm







P4 cz







C\j


rz
co







rX4








24

family of schedules, and every schedule belongs to exactly one such family. The makespan of a schedule that is optimal

for S is equal to the length of a longest path in D.. Thus, the scheduling problem becomes that of determining an acyclic complete selection S that minimizes the length of a longest path in the directed graph DS.



Branch and Bound Algorithms

The disjunctive graph representation of the job shop scheduling problem has formed the basis for a number of branch and bound algorithms. These algorithms can be classified into two broad groups. The algorithms in the first class proceed by constructing an initial feasible solution and then improving it by selectively reversing disjunctive arcs. The second class of algorithms constructs a schedule until a conflict of some kind, usually violation of a capacity constraint at a machine, occurs. They then branch on each of the possible outcomes of the conflict. A similar classification of enumerative methods of solving the job shop scheduling problem is given by Lageweg et al.[61].



Improvement-based branch and bound algorithms

One of the earliest algorithms in the first class was developed by Balas[81. Let S denote the set of all complete selections and G h the conjunctive graph associated with a selection Sh' Let GI be the set of all Gh such that Gh is









25

circuit-free. We know from the discussion above that the solution of the minimum makespan problem is equivalent to that of finding an optimal selection and minimaximal path in this disjunctive graph.

The algorithm generates a sequence of circuit-free

graphs Gh e G' and solves a slightly modified critical path problem f or each Gh in the sequence. Each graph Gh is obtained from a previous member of the sequence by reversing the direction of one disjunctive arc. At each stage some disjunctive arcs are fixed while some are free to be reversed, but only the candidates for reversing that lie on

a critical path of the current Gh need to be considered. This, however, is only true when the arc between two nodes is the shortest path between the two nodes. At each stage the shortest critical path found so far provides an upper bound, while the critical path in the partial graph containing only the fixed arcs yields a lower bound. In another paper[lO], Balas provides another approach to the solution of this problem where he relates it to the concept of degree-constrained subgraph. In [9] he extends the disjunctive graph representation to handle parallel machines. In [11] he characterizes the facial structure of the polyhedra related to this problem.

Carlier and Pinson[21] present a branch and bound algorithm that makes use of single-machine problems to obtain bounds and various propositions which enable the size








26

of the search tree to be limited. These authors again branch by selecting a disjunctive arc and examining each of its two possible orientations. This algorithm has the distinction of having been the first to optimally solve the notorious 10job 10-machine job shop problem posed by Muth and Thompson[21].



Conflict-based branch and bound algorithms

Charlton and Death[22,23] propose an algorithm that

uses the second approach. These authors start by considering only the conjunctive arcs and determining the start times for jobs on machines based on this information. They then select a machine k on which two operations i and j are processed simultaneously and branch by considering fixing the disjunctive arc (i,j) in each of its possible two directions. The lower bound at a node of the search tree is given by the critical path in the graph containing only the fixed arcs. The authors claim computational performance superior to that of Balas' approach[8].

Barker and McMahon[13] also propose a method that is based on branching using conflict resolution. In this approach the conflict resolution on which the branching takes place is based not on the conflict between two operations but on the conflict between an operation and several others that appear in a critical block in a tentative schedule. The method generates a tree each node of








27
which is associated with a complete schedule and a critical block of operations. At each node, a critical operation j is determined. The critical block consists of a continuous sequence of operations ending in the critical operation j. The subproblems at each of the successor nodes are obtained by fixing part of the schedule in the critical block. Lower bounds are obtained by solving single-machine subproblems using the algorithm of McMahon and Florian[76], which is itself a branch and bound method.

Florian et al.[40] also propose a branch and bound

algorithm for job-shop scheduling based on the disjunctive graph representation. This approach proceeds by determining sets called cuts consisting of the first unscheduled operation of all jobs. operations are scheduled by having all disjunctive arcs incident into the corresponding node have been fixed. The branching mechanism of the algorithm proceeds by selecting one operation from the cut to be scheduled next and fixing the disjunctive arcs accordingly. The authors prove that a graph constructed by fixing disjunctive arcs in this manner will never contain cycles and that the set of schedules enumerated in this way contains the optimal solution. The lower bound is based on the fact that each machine must perform at least one terminal operation. Hence, a lower bound for the job shop problem is obtained by sequencing the remaining jobs on each machine in order of increasing earliest start time.








28

Flowshop Scheduling

The flowshop scheduling problem (F//Cmax) is a special case of the job shop problem where work flow is unidirectional. Since it has also been shown to be NPhard[59,60], it has also been approached using branch and bound algorithms. A number of algorithms for minimizing makespan have been developed [5,6,53,54,55,62,91]. Gupta[49], Corwin and Esogbue[29] and Uskup and Smith[92] have examined the problem of minimizing makespan in the presence of sequence-dependent setup times. However, performance measures other than makespan have not received so much attention. In [54] and [55] Heck and Roberts develop algorithms along the lines of that of Balas[8] for the measures of performance of maximum tardiness, average flow time and average tardiness. In order to minimize maximum tardiness, they introduce the concept of a critical path for maximum tardiness. This concept is then used in a manner analogous to that of Balas[8] to decide which disjunctive arcs are to be reversed. The average performance measures are handled by the same type of enumeration and branching mechanism. The difference in this case is that a sink node is associated with each job to enable the performance measures to be calculated easily. Hariri and Potts[52] have developed a branch and bound algorithm to minimize number of tardy jobs in a flowshop. However, this algorithm becomes computationally very demanding as problem size increases.









29

Heuristic Approaches

The branch and bound methods described above all suffer from the common fault of implicit enumeration approachesthe exponential growth in computational effort as problem size increases. Hence a good deal of research has been devoted to developing heuristic procedures that obtain good solutions with less computational burden. We shall distinguish between two classes of heuristics: d ispatching rules, that take into account only local information at the individual machines, and approximation methods, which take into account the entire job shop.

There are a great many dispatching rules that have been examined in the literature. Surveys of such rules for job shop scheduling can be found in Baker[3], Conway et al.[28] and Panwalkar and Iskander[81]. Dispatching rules have the advantages of being easy to implement and explain, and will often give good results. While this approach may be sufficient for some cases, in job shops where there is high competition for capacity at key resources the extra computational effort involved in obtaining better schedules would appear to be justified. This is the motivation for the development of approximation methods, like the Shifting Bottleneck Method developed by Adams et al.[l] described in the next section.









30
An interesting application of new ideas to this problem can be found in van Laarhoven et al.[93], who apply the technique of simulated annealing to the job shop problem. These authors prove that the algorithm they present asymptotically converges to a global minimum, and finds better schedules than heuristics at the expense of higher computation times. Comparing their method with the Shifting Bottleneck procedure [1], these authors found that overall the shifting bottleneck outperforms simulated annealing on the basis of a time versus quality of solution tradeoff. Matsuo et al.[75] also provide a simulated annealing procedure for the J//Cmax problem. The neighborhood structure they employ is rather more sophisticated than that of van Laarhoven et al.[93]. Their algorithm obtains solutions as good as those obtained by the partial enumeration version of the Shifting Bottleneck Procedure in comparable computation times.

Another interesting class of heuristics for job shop scheduling has been developed recently based on the concept of resource pricing. An example of such an approach is given by Morton et al.[79] in the SCHED-STAR system. This system assigns a price to each machine based on the jobs waiting for it, their tardiness and inventory holding costs and the material and labor costs involved. Based on these costs a rate of return is calculated for each job and the job with the highest rate of return is scheduled next. The authors








31

report that this procedure performs better than dispatching rules over a wide range of problem instances.

A number of heuristics based on approaches like

neighborhood search and repeated application of Johnson's Algorithm for the two-machine case[3] have been developed for the flowshop problem. Surveys and evaluations can be found in Dannenbring[31] and Park et a14[821.



Shiftingi Bottleneck Approach

The basic idea of the Shifting Bottleneck (SB) approach[l] is to give priority to the most critical machine. At each machine a single-machine scheduling problem is solved to optimality. The results are then used to rank the machines in order of criticality, the one with the worst objective function value being the most critical. The solution associated with the most critical machine is fixed as the sequence for that machine, and the procedure is repeated in the light of this information for the machines not yet scheduled. Each time a new machine is sequenced, previously scheduled machines that are amenable to improvement are reoptimized. The procedure continues in this fashion until no further improvements are possible.

Having presented the broad framework, let us now

present the methodology in a more formal manner. There are two important points to consider:

The nature and solution procedure for the single-








32

machine problems that are used to determine the degree of criticality of a machine as well as the sequence of the most critical

How the interactions between the individual machines are captured using the disjunctive graph representation

There are a number of different ways that a machine can be classified as critical for the makespan problem. Let MO be the set of machines sequenced to date, and M the entire set of machines. Denoting a selection associated with machine k as S k' we obtain a partial selection S = U keMO S k' Let DS be the directed graph obtained by deleting all disjunctive arcs associated with machines j, je M \ MO and fixing the arcs in the selection S. A longest path in DS will correspond to a lower bound on the makespan. Thus, it would be mathematically justifiable to define a machine as

critical with respect to a partial selection S if Sk has an arc on a longest path in D S. This, however, does not allow us to rank the machines in order of criticality, but merely partitions the set of machines into two subsets, critical and non-critical.

Instead, the solution to a single-machine sequencing problem is used to determine the criticality of a machine. Let us assume that we are interested in determining the degree of criticality of machine k, given that the machines

j 6 MO have already been sequenced. Create the problem P(kMO) as follows:









33

Replace each disjunctive arc set EP, p e Mo, by the corresponding selection S .

Delete all disjunctive arcs in E,, J E M \ Mo.

The release times and due dates for operations on

machine k are then determined using the disjunctive graph as will be discussed shortly. The problem that results is that of sequencing a single machine to minimize maximum lateness with due dates and release times. This problem in turn is equivalent to that of sequencing a single machine so as to minimize makespan, when each job has a release time and a certain "tail" that represents the time it must spend in the system after processing. These subproblems are solved using the algorithm of Carlier[22], which is a branch and bound procedure with good computational performance.

The release times ri and due dates f1 associated with

operation i on machine k are determined from the disjunctive

graph obtained from P(k,M0) above by solving a number of longest path problems. Let L(i,j) denote the longest path from node i to node j in DT, T = U kem Sk.- Then r, L(O, i)

where node 0 is the source node and

d= L(0,n) L(i,n) + d

where node n is the sink node and di is the processing time for operation i. The "tail" associated with operation i can then be calculated to be

q= L (0,N) -f








34

The authors exploit the structure of the disjunctive graph to develop a longest path algorithm with a computational effort of O(n), as opposed to the conventional algorithms that require O(n 2 ) effort, where n denotes the number of nodes.

The Shifting Bottleneck methodology for minimizing makespan can now be summarized as follows:

1) Identify a bottleneck machine k among the as yet unscheduled machines and sequence it optimally.

2) Reoptimize each machine h whose selection Sh has an arc on a longest path in DT, keeping the other sequences fixed. If all machines are sequenced, stop. Else, go to Step



Computational experience with this methodology has been extremely encouraging. The authors carried out experiments on problems ranging from small ones whose optimal solution was known to larger problems with 500 operations. The approach took on the order of one or two minutes to solve the larger problems, even though a great many single-machine problems had to be solved. The authors observe that the difficulty of solving a problem increases sharply with the number of machines. However, increasing the number of operations does not seem to affect the computational effort significantly and seems to improve the quality of the solutions. A significant fact is that the classic 10 jobs/10 machines problem that resisted solution for 20 years was








35

solved optimally by the Shifting Bottleneck procedure in just over 5 minutes. When compared with priority dispatching rules, the Shifting Bottleneck Procedure outperformed them 38 out of 40 times.

Adams et al.[1] have also applied the Shifting

Bottleneck methodology to the nodes of a partial enumeration tree. This method most of the time yields better solutions than those obtained by applying the basic approach.



Summary

In the light of this review, we feel that we are able to state the following conclusions:

Approximation methods like the Shifting Bottleneck approach are the most effective solution techniques available at present for job shop scheduling problems.

Performance measures other than makespan have not been extensively examined to date.

Scheduling job shops in the presence of sequencedependent setup times and workcenters with parallel identical machines and batch machines has not been examined extensively.



Single and Parallel Machine Scheduling

The effectiveness of approximation methods like the SB approach described in the previous subsection hinges on the ability to efficiently schedule the individual workcenters.








36
These workcenters may consist of a single machine, or a number of parallel identical machines. In this subsection we will review results on single and parallel machine scheduling that will assist us in developing solution procedures for the workcenter subproblems.



Single-Machine Scheduling

Research on the sequencing of a number of jobs through a single processor dates back to the 1950s. In this section we shall only review results relevant to this research. Reviews of the basic results in this area can be found in Baker[3], Conway et al.[28] and French[41]. Detailed complexity classifications of these problems are given by Lageweg et al.[59,60].

The nature of the facility motivating this study and the management objectives involved lead us to examine single-machine scheduling problems with performance measures of maximum lateness and number of tardy jobs. The problems are characterized by the presence of release times, due dates, precedence constraints and sequence-dependent setup times. In order to represent these problems in a concise manner we shall extend the notation of Lageweg et al.[59,60] to include sequence-dependent setup times (SDST). Thus, for example, the problem of minimizing Lmax on a single machine with precedence constraints and sequence-dependent setup times will be represented as i/prec,SDST/Lmax.








37

The problem of minimizing Lmax on a single processor

without setup times has been extensively examined. The cases with simultaneous release times (l//Lmax and i/prec/Lmax) are easy to solve using the Earliest Due Date rule and Lawler's Algorithm respectively[3,64]. However, the presence of non-simultaneous release times renders the problem i/r,/Lmax NP-hard in the strong sense[60]. Thus we see that our problem, I/r,prec,SDST/Lmax, is NP-hard in the strong sense even without the sequence-dependent setup times. Furthermore, we note that the special case of l/SDST/Lmax with common due dates is equivalent to l/SDST/Cmax, which is well known to be equivalent in turn to the Travelling Salesman Problem (TSP) [3].

The 1/r1/Lmax problem has been examined by a number of researchers. It has been shown that this problem is equivalent to the problem of minimizing makespan (Cmax) on a single machine in the presence of delivery times qi = K di, where K > maxi(di) [71]. The optimal sequences for these two problems are identical, and their optimal values differ by the constant K. We shall denote this problem by i/r1,q1/Cmax. Branch and bound algorithms for this problem have been developed by Baker and Su[7], McMahon and Florian[76] and Carlier[20]. The latter two approaches are closely related and both have been integrated into larger branch and bound schemes for solving the general job shop problem[13,21].








38

Baker and Su[7] develop an enumeration scheme that

enumerates all active schedules. Active schedules are those schedules in which no job can be started earlier without delaying the start of another. Let S be the set of all jobs. Then at time t the set Q of jobs eligible for scheduling next is

Q = {jeSir, :: min~max~t,rk)+pklikeS}

This ensures that only active schedules are generated, since if r i > max~t,rk) + Pk for some job k, then k can precede j without delaying the completion of j. The bounding rule employed is based on the fact that the value of an optimal schedule will not increase if job splitting is allowed. A lower bound for all completions of a partial schedule is obtained by sequencing the remaining jobs in EDD order allowing job splitting.

This algorithm can easily be extended to the problem

with precedence constraints by defining the set Q to be the set of jobs whose predecessors have been scheduled that satisfy the condition specified above.

A more sophisticated algorithm is given by McMahon and Florian[76]. This approach uses a heuristic to construct a good initial solution and then generates an enumeration tree of improved solutions. The heuristic selects the job available at time t that has the earliest due date, breaking ties by choosing the job with longest processing time. The resulting schedule consists of a number of blocks, which are








39

periods of continuous utilization of the machine. The authors define the critical job to be the job that realizes the value of Lmax in a given schedule. Branching rules and lower bounds are obtained by scheduling other jobs last in the block instead of the critical job.

The algorithm of Carlier[20] is closely related to that of McMahon and Florian[76] and also makes use of the same heuristic. This author proves that if L is the makespan of the schedule obtained using this heuristic, then there exists a critical job c and a critical set J such that

min {r,) + Z pi + min {qi) > L pc
iEJ iEJ iEJ
and that in an optimal schedule job c will be processed either before or after all the jobs in J. This latter observation forms the basis of the branching rule employed. Lower bounds are obtained by applying the heuristic but also allowing preemption. This algorithm has excellent computational performance, and has been integrated into algorithms for the job shop problem developed by Carlier and Pinson[21] and Adams et al.[l].

Potts[85], Carlier[20] and Hall and Shmoys[51] present heuristics for the 1/r,q1/Cmax problem and analyze their worst-case behavior. Most of these heuristics are based on the Extended Jackson's Rule, which can be stated as follows: Whenever the machine is free and there are one or more available operations, sequence next the operation with largest value of qi. The best heuristic developed so far








40

appears to be that of Potts quoted by Hall and Shmoys[51], which has a worst-case error of one-third.

The performance measure of number of tardy jobs (ZU) is considerably more difficult to optimize than Lmax. The problem 1//ZUi can be solved in polynomial time using Moore's Algorithm[3]. Lawler[65] extends this approach to the 1//EwiUi problem where wi < wj implies pi : p3, where w3 is a nonnegative penalty for the job j being tardy. However, the general 1//EwiUi problem and the 1/prec/ZUi problem are both NP-hard[59,60,72]. Lawler and Moore[66] give a pseudopolynomial dynamic programming algorithm for the former problem, and Villarreal and Bulfin[96] and Potts and Van Wassenhove[86] provide branch and bound algorithms. The algorithm of Potts and Van Wassenhove uses problem reductions derived from the knapsack problem and dominance relations to reduce the size of the search tree. Lower bounds are derived from the dynamic programming algorithm of Lawler and Moore[66] and a linear programming relaxation of the integer programming formulation of the problem.

The problem with arbitrary release times and due dates, 1/r/EUi, is also NP-hard in the strong sense[59,60]. Kise et al.[58] give a polynomial time algorithm to solve the case with agreeable release times and due dates, i.e., r 2 r3 implies di > d .

It is well known that the problem of minimizing

makespan on a single machine with sequence-dependent setup








41

times (l/SDST/Cmax) is equivalent to the travelling salesman problem (TSP), which is NP-complete[3]. Picard and Queyranne[84] relate the problems of minimizing weighted lateness, number of late jobs and the sum of weighted tardiness and flow-time costs to the time-dependent TSP. In this generalization of the TSP the cost of each transition depends not only on the locations between which it takes place but also on the position of the transition in the sequence defining the tour. These authors use relaxations of integer programming formulations to obtain bounds which they use in a branch and bound algorithm. Barnes and Vanston[14] address the problem of minimizing the sum of linear delay costs and sequence-dependent setup costs, where the delay is defined as the time elapsing until the job starts being processed. They examine a number of branch and bound algorithms and develop a hybrid dynamic programming/branch and bound approach. Driscoll and Emmons[39] present a dynamic programming formulation of the problem and demonstrate some monotonicity properties of the functions employed. A number of authors, such as Lockett and Muhlemann[73], White and Wilson[98] and Irani et al.[57] have also developed heuristics. These heuristics generally entail some analysis of the setup operations and the approximate solution of the resulting TSP.








42

The problems of minimizing Lmax or ZUi with

sequence-dependent setup times (l/SDST/Lmax, l/SDST/ZU) do not seem to have been extensively examined. Monma and Potts[78] present a dynamic programming algorithm and optimality properties for the case of batch setups, where setups between jobs from the same batch are zero.



Parallel Machine Schedulin'

Lageweg et al.[59,60] give a detailed complexity

classification of results in parallel machine scheduling without preemption. From this classification it appears that only problems with unit processing times can be solved in polynomial time. The problems P2/r, dj, Pjl/Lmax, P/rI, d1, p!=I/Zw1T and P/r, d1, pj=l/Zwj U are among these[63]. The other problems in this area are either open or NP-hard. Considerable effort has been devoted to the development and analysis of heuristics for these problems[26,37].

The problem of scheduling parallel machines in the presence of sequence-dependent setup times has also been addressed by a number of researchers. Geoffrion and Graves[43] examine the problem of scheduling parallel production lines in the presence of changeover costs and formulate it as a quadratic assignment problem. Wittrock[99] presents a heuristic for minimizing total completion time on a set of parallel identical machines where there are two types of setups: "family" setups, which are more time-








43

consuming and are incurred when the product being run changes drastically, and product setups due to changes from one product to another in the same family. Computational experience is reported and a lower bound for the optimal solution derived. Dietrich[38] examines the problem of determining schedules that are efficient with respect to both makespan and flow time for the case of parallel unrelated machines with sequence-dependent setups. An integer programming formulation is presented and a heuristic algorithm developed. Parker et al.[83] use a vehicle-routing algorithm to solve the problem of minimizing total setup costs on parallel processors.



Batch Processing Machines

A batch processor is defined to be a machine where a number of jobs can be processed simultaneously as a batch. The processing time of a batch is equal to the longest processing time among all jobs in the batch. once processing is begun on a batch, no job can be removed from the machine until the processing of the batch is complete. These problems are motivated by burn-in operations in the semiconductor industry, where lots of chips are placed in ovens and subjected to thermal stresses for an expended period of time in order to bring out latent defects leading to infant mortality before the product goes to the customer. The scheduling of batch processors does not seem to have








44

been extensively examined in the deterministic scheduling literature to date. Ikura and Gimple[56] provide an 0(n 2) algorithm to determine whether a feasible schedule (i.e., one where all jobs are completed by their due date) exists for the case where release times and due dates are agreeable and all jobs have the same processing time. In the event of a feasible schedule existing, their algorithm finds the one with minimum finishing time. Bartholdi[15] examines the problem of minimizing makespan on a single batch processor. He shows that successively grouping the B longest jobs into a batch will minimize makespan for the case where all jobs are available simultaneously. Ahmadi et al.[2] examine the problems of minimizing mean flow time and makespan in flowshops consisting of batch and unit-capacity machines, assuming that all jobs require the same processing time on the batch machine. They provide polynomial-time algorithms for a number of cases and provide NP-completeness proofs and heuristics for others.

Related problems seem to have been more extensively

examined from a stochastic perspective. Neuts[80] considers a case where customers are served in groups. Service can only start if a certain number of customers are waiting, and the number of customers which can be served together is limited. He examines system characteristics such as the output process, queue length and number of customers served over a long period of time. Medhi[77] examines the








45

distribution of waiting times in this system when service times are exponential. Deb and Serfozo[36] use dynamic programming to minimize expected total or average costs.

Concluding this subsection, it emerges that the

problems in the areas of single, parallel and batch machine scheduling of the types examined in this research have not been examined extensively in the literature and a great many of them are NP-hard.



Research on Semiconductor Manufacturin

Despite the ever-increasing role played by the semiconductor industry in worldwide technological development it is only recently that semiconductor manufacturing systems have attracted the attention of industrial engineering and management science researchers.

One of the earliest articles available in the published literature is that of Burman et al.[18] which discusses methods of using various operations research tools to enhance productivity in wafer fabs. They compare the usefulness of simulation, deterministic capacity models and queueing models. Simulation models can be developed to model an entire production operation with a view to answering many potential questions, or as smaller models to address specific issues. However they point out that considerable effort is needed to develop the model and to analyze the output. Deterministic capacity models are used








46

for capacity estimation purposes, are easy to develop and quick to run but limited in the range of questions they can address. Queueing models can be developed that can be used to examine a broader set of issues than the deterministic capacity models, but the mathematical assumptions they make tend to render them inaccurate representations of the physical system. The authors then proceed to give an example for the application of each technique in a wafer fab environment.

Considerable effort has gone into the development of simulation models for wafer fabs and their use to analyze the effects of different control strategies. Dayhoff and Atherton [32,33,34,35] have developed such a model and used it to analyze the performance of wafer fabs under different conditions. Their approach is based on modelling a fab as a special type of queueing network. Similar approaches, namely the modelling of the wafer fab as a network of queues and the subsequent use of a simulation model, are followed by Wein[97], Glassey and Resende[44,45] and Lozinski and Glassey[74]. Wein[97] evaluates the effect of scheduling on the performance of wafer fabs, taking cycle time as the measure of interest. He examines two different types of control strategy: regulation of input, where the number of lots started into the fab is controlled, and sequencing of lots at the individual stations. He observes that input regulation yields larger improvements than sequencing at the








47

individual stations, and that the effects of sequencing rules depend heavily on the number and location of the bottleneck stations and the specific input regulation mechanism involved.

Glassey and Resende[44,45] point out that due to the extensive use of Computer-Integrated Manufacturing (CIM) systems such as the COMETS system[27] dispatching decisions at the individual stations and lot release decisions governing the release of work to the fab can be made based on more global information. similarly to Wein[97], they examine the effects of input regulation mechanisms, assuming they have a single bottleneck workstation in a fab with a single product and constant demand rates. They develop a rule for input regulation which attempts to release work into the fab so that it will arrive at the bottleneck station just in time to stop it from starving. The authors compare this strategy with a number of others and report favorably on its performance, which is measured based on a tradeoff between cycle time and throughput. Lozinski and Glassey[74] discuss implementation issues. Leachman et al.[68] further develop this approach by removing the need for a priori bottleneck determination. Spence and Welter[89] use a simulation model to examine the performance of a photolithography workcell based on a throughput-cycle time tradeoff.








48
Chen et al.[24] develop a queueing network model of a research and development wafer fab operation. A network in which a number of different types of customer, corresponding to different lot types, are present is presented. The model is of a mixed nature, that is, open for certain classes of customers and closed for others. After defining parameters such as expected number of visits to each station and station service rates, an iterative procedure is employed to arrive at throughput rates for the entire network and other quantities of interest such as average throughput time per customer at each station. The results obtained from the model are compared with actual observed data and found to be in close agreement.

Bitran and Tirupati[16,17] describe a scheduling system for a facility manufacturing epitaxial wafers. They model this facility as a single-stage parallel-machine system, and propose a number of heuristics with a view to optimizing two criteria, makespan and total tardiness. They also examine product mix and the associated problem of assigning product families to reactors so as to achieve a more homogeneous product mix. This is formulated as a convex program. They recommend various different heuristics for different cases, and observe that when the jobs are preprocessed by assigning product families to reactors a priori, simpler heuristics give results comparable to the more complex procedures they develop.









49

As can be seen from the above review, the majority of the approaches to scheduling of semiconductor manufacturing facilities are of the nature of input regulation mechanisms and dispatching rules at the individual stations. A significant exception is the work of Bartholdi et al.[15] which is related to the work in this dissertation. The most important part of these authors' work is their application and extension of the Shifting Bottleneck (SB) approach of Adams et al.[l] to wafer fabrication operations. These authors model the wafer fab using the SB approach and extend the basic model in various ways to include parallel identical machines and batch processing machines. To model parallel identical machines, they start from the observation that a sequence for a single machine k corresponds to a path connecting all nodes in the associated selection Sk* A schedule for a workcenter with m parallel identical machines will then correspond to m disjoint paths, each one corresponding to the sequence for one of the m machines. Each node corresponding to an operation has to be visited by one and only one path. Batch processing machines are represented using stars. An n-star is a graph with n-1 arcs containing a node c, called the center, which is adjacent to all other nodes, called satellites. If a batch can be processed at a workcenter, this can be represented by a star with a center corresponding to the operation with the longest processing time. The costs of the arcs leaving the









50
satellites are set to 0, and the costs of the arcs leaving the center are set to the longest processing time in the batch. In the case of several batches being available, there will be as many stars as batches. This assumes, however, that the assignment of operations to batches is already known.

Leachman[67] gives a corporate-level production

planning model for the semiconductor industry. He divides the manufacturing process into the stages of fab, probe, assembly and test, linked by inventories. The model may include multiple facilities, and treats entire production processes in each plant as integral entities. Products undergoing the same process at each stage are aggregated into families. Computerized routines create the input files of an aggregate planning model and then generate the linear programming formulation. The solution to this linear program yields a production plan at the process level of detail, which is then validated by management. If it is invalid, due to some resource being overutilized for instance, the input data are revised and the process repeated until an acceptable plan is generated. once an aggregate plan has thus been obtained, it is disaggregated by solving a number of linear programs to divide the volume of production planned for each product family over the individual products. This model has been used by a number of manufacturers in the industry.








51

A number of commercial software systems for the planning and control of semiconductor manufacturing operations have been developed. one such system widely used in industry is COMETS[27], marketed by Consilium,Inc. and used by a number of leading companies. This system is composed of a number of different modules, and is designed as an integrated plant management system, with all the different groups involved in the manufacturing process being supported by the same database. The main modules of interest to this study are the Work-in-Process (WIP) tracking module, the Activity Planner/Dispatch (AP/D) module and the ShortInterval Scheduling (SIS) module. other modules such as engineering data collection, factory communications and online specifications are also available.

The Short-Interval Scheduling (SIS) module of COMETS gives the user real-time scheduling capabilities. The process is modelled using the concept of dispatch stations, which are essentially points in the process where inventory accumulates and a scheduling decision is required. SIS enables the user to develop his own dispatching rules. This is done by defining a set of priority classes, with a strict hierarchy, and then using rules to define the conditions under which a lot may be a member of a class. Lots at the dispatch station are prioritized according to the status of the system at the moment the request for the dispatch list was made, and the operator selects the lot with the highest








52

priority for processing. The module makes information like machine status (up/down, setup) at the dispatch station itself or a subsequent station, time spent by a lot at the station and setups required by lots awaiting processing available to the user. Detailed information on this software module can be found in Consilium[27].

Thus, the scheduling technology present in this system is the classical dispatching rule, using mostly local information in the immediate environs of the dispatch station and not using global information at all.



Summary

In this chapter we have reviewed the current body of knowledge in the areas of scheduling theory and its applications in semiconductor manufacturing. We shall now examine the contributions of the research in this dissertation to these areas.

The problems of scheduling the job shop to minimize maximum lateness and number of late jobs are NP-hard and have not been extensively studied. The excellent computational performance of the SB methodology for minimizing makespan would suggest that similar approximation methods will rapidly yield good solutions for these problems. The development of such methods contributes significantly to the area of job shop scheduling. The extension of the job shop model to include multiple-machine








53

workcenters and batch processing machines also extends modelling capabilities in this area.

The single, parallel and batch processing machine

problems that constitute the subproblems in an approximation approach are also of considerable interest and have not been examined extensively in the literature. In Chapter V exact and heuristic solution procedures for the problems of minimizing maximum lateness and number of tardy jobs are developed. The worst-case analysis of the heuristics developed is the first such analysis known to the author for problems of this type. In Chapter VI the problem of scheduling batch processing machines for a number of different performance measures is examined. optimal solution procedures and heuristics are presented, together with a complexity classification of these problems.

The problem of scheduling in the semiconductor industry seems to have been addressed mainly through dispatching rules. The ultimate goal of this research is the development of algorithms capable of being incorporated into a decision support tool to assist shop-floor personnel in real-time decision-making. This would constitute a significant improvement over available commercial scheduling systems, which are based solely on dispatching rules. The consideration of the status of the entire job shop should yield considerably better schedules, especially for bottleneck resources.














CHAPTER IV

MODELLING APPROACH



Introduction

In this chapter we shall formulate the problem of scheduling a semiconductor test facility as a job shop scheduling problem. We shall then present an approximate

solution methodology for this problem similar to the Shifting Bottleneck (SB) methodology of Adams et al. [1] for the J//Cmax problem described in the previous chapter. The basic SB

methodology is extended in a number of ways to be able to address the type of job shop under study. Chapters V and VI develop algorithms necessary to solve the local problems in

the approximation approach, and a prototype implementation of the approximation scheme is described in Chapter VII.



Modelling of Job Shop

In a semiconductor testing facility, product moves

through the area in lots, which vary in size from a few individual chips to several thousand. Once processing of a lot has begun, it cannot be interrupted until the whole lot

has been completed. Processing takes place at a number of workcenters, generally consisting of one or more identical 54








55

machines. The machines may be testers, branders or burn-in ovens, to name a few. These machines differ considerably in scheduling characteristics. For example, testers have

sequence-dependent setup times, while branders do not. Test systems and branders can process only one lot at a time, while burn-in ovens can process a number of lots together as a batch.

Hence a natural way to model a semiconductor test

facility as a job shop scheduling problem is to model each lot of chips as a job, and each group of similar machines scheduled as a unit as a workcenter. Note that this is a somewhat more general problem than the classical job shop scheduling problem discussed in Chapter III. The common assumptions in this problem are that each machine is visited by each job only once, that each machine can process only one

job at a time and that setup times are not sequence-dependent. In the semiconductor test facility that provided the motivation for this study, however, there are several differences from this model:

The presence of different types of workcenters, some

consisting of multiple identical machines, some of a single machine and some of one or more batch processing machines, where a number of jobs are processed together as a batch.

The presence of sequence-dependent setup times at some workcenters.

The performance measures being related to lateness








56

instead of makespan.

The possibility that a given job may return to a certain workcenter more than once (reentrant work flows) For example, if a lot of chips has to be tested at three different temperatures, all three operations are carried out at the same test workcenter. This also results in the presence of precedence constraints between operations at a given workcenter, a complication not present in the classical J//Cmax problem.

Recall from Chapter III that the disjunctive graph representation of the job shop scheduling problem has formed

the basis for many solution approaches. From the point of view of this research, the most important application is the use

made of it in the SB methodology to capture interactions between different workcenters as the methodology proceeds and a complete job shop schedule is built up. We shall now give the disjunctive graph representation of the job shop defined by a semiconductor test facility and describe how it is used to capture interactions between individual workcenters. Throughout the rest of this chapter, we will make the following assumptions:

All handlers, load boards contacts and operators are freely available at all times

-Operations on the same lot have a strict precedence relation which is known a priori. once processing on a lot has started, the entire lot has to be completed.








57

All the process times and sequence-dependent setup times are available and deterministic.



Disiunctive Graph Representation

In order to construct the disjunctive graph representation of the job shop, let us first consider the case of a workcenter consisting of a single machine. The following notation will be used:

ij = operation i of lot j

Pij= processing time for operation i of lot j

sij,kL = setup time required for change from operation i of lot j to operation k of lot 1 on the workcenter

Let us now construct the disjunctive graph representation of the workcenter as follows. Assume there are N operations to be processed at the workcenter. Add a source node 0, and associate a node ij with each operation j to be carried out on lot i at the workcenter. With each lot i to be processed at the workcenter, associate a sink node i* that represents the completion of that lot. This is similar to the approach used by Heck and Roberts[55] for average tardiness minimization in flowshops. Define the arc set as follows:

-Associate a conjunctive arc (ij,kl) between pairs of operations ij and kl where ij must precede kl at the workcenter. Each of these arcs represents a precedence constraint between the two operations corresponding to the nodes at each end. Add a conjunctive arc (0,ij) from the








58

source node to all nodes representing operations ij having no fixed predecessor, and another conjunctive arc (ij,j*) from



all nodes ij representing the final operation ij on lot j to the sink node.

-Associate a pair of disjunctive arcs between all pairs of nodes (ij,kl) that correspond to operations that can be carried out at the workcenter and have no precedence relation.

-With each arc, conjunctive or disjunctive, associate a cost c,,kt defined as

Cij,kt = Pij + Sij,kt

Assume p0j = 0 for all j. The sequence-dependent setup times are thus taken into account. All process and setup times associated with the sink nodes i* are assumed to be zero. An example of a workcenter with three lots is shown in Fig.4.1. Arc costs are omitted for the sake of clarity. The first lot has two operations, represented by nodes 11 and 21, while two other lots have one operation each. Notice that each path from source to sink consisting of only conjunctive arcs corresponds to a lot. Operation 11 has to be carried out before operation 21, hence the conjunctive arc between nodes 11 and 21. The possible sequences of operations for this workcenter are described by the pairs of disjunctive arcs. Each sequence for the workcenter corresponds to a selection of exactly one of each disjunctive pair. The sequence of operations 11-21-1213, for example,is represented by the graph in Fig.4.2.











59























4

CY)

u
114
4
0

4
0
4



4
0 cu Oj






cu














PL4












60



















4 a) 4.J



4
0

co
0
44 aj


7j cu
a
u
M

44
0




co
41



4







ro
x C\j co w


L


cu


to
-H








61

In order to represent the entire job shop as a disjunctive graph, we represent each workcenter in the manner described above. However we no longer define a source and sink node for each workcenter. Instead the nodes that would be linked to the source at each workcenter are now linked to nodes corresponding to operations on that lot at preceding workcenters. We create a source node for the entire facility, to which all nodes corresponding to operations with no predecessors are linked, and again associate a sink node i* with the completion of the final operation on each lot i.

An example for a job shop with two workcenters is shown in Fig.4.3. Operations 11,21,12 and 13 take place at the first workcenter, while 31, 22 and 23 take place at the second. Lots must be processed at the first workcenter before they can be processed at the second. Nodes 1*, 2* and 3* denote the completion of the lots.



Approximation Methodology

Now that we have formulated the problem of scheduling a semiconductor test facility as a job shop scheduling problem and have shown how it can be represented using a disjunctive graph, we are ready to present an approximation methodology for its solution similar to the SB methodology of Adams et al.[l]. The approach may be outlined as follows:

1) Divide the job shop into a number of workcenters numbered 1,...,m that have to be scheduled. Let M be the set









62















cm co








0


co 0
co
4
0



C,4








C\j






N CY)




rZ4








63

of workcenters, and M0 the set of all workcenters that have been sequenced. Initially, M0 =(P.

2) Represent the job shop using a disjunctive graph.

3) From among the non-sequenced workcenters k E M \MO, determine the most critical workcenter j.

4) Sequence the critical workcenter j. Fix the selection of disjunctive arcs S corresponding to this sequence. Set M0 M 0 U {j}.

5) Use the disjunctive graph representation to capture the interactions between the workcenters already scheduled and those not yet scheduled.

6) Resequence those workcenters that have already been sequenced using the new information obtained in Step 5. If M0 M, stop. Else, go to Step 3.

The main body of the methodology is contained in Steps 3 through 6. We shall now discuss each of these steps individually.



Step 3: Determination of Critical Workcenter

The objective of this phase is to determine which workcenter is most critical, in the sense that a poor schedule on that workcenter will result with high probability in a poor overall schedule for the job shop. For this stage, Adams et al.[l] use the optimal solution to a relaxed problem which ignores machine interference between machines not yet sequenced. Since all of their subproblems are of the same type









64

and are solved to optimality, this is a good indicator since all machines are compared equally.

In the case of the job shops under study here, this issue becomes more complicated. While extremely fast branch and bound algorithms are available to solve subproblems for

workcenters without setup times, such methods are not yet available for the case where sequence-dependent setups are present. This would seem to force us to use heuristics to obtain solutions to the relaxed problems for this type of workcenter, thus losing the common denominator of optimality present in the case of Adams et al.[l].

One possibility is to try and ensure equitable comparisons between the different types of problems by using heuristics with comparable performance to evaluate each different type of workcenter problem. In this case we would define performance in terms of average or worst-case

performance. The prototype implementation described in Chapter VII uses this approach.

An interesting point is that although in their methodology Adams et al.[l] use the algorithm of Carlier[20] both to make criticality decisions and to sequence the

critical workcenter, there is no apparent need to do so in the case of the more general shops under consideration in this research. In the case of Adams et al.[l] the use of the same algorithm for both purposes is extremely logical, since all subproblems are of the same type and the optimal sequence of








65

the critical machine is available at the end of the f irst stage anyway. However, in view of the intrinsically more difficult subproblems considered in this study, it might make sense to use a fast heuristic to make criticality decisions

and a more computationally intensive algorithm to sequence the critical workcenter as well as possible. This makes even more sense when we note that the problems relating to criticality

decisions have to be solved for each unscheduled machine, while the problem of sequencing the critical machine need only be solved for that one machine at each iteration of the general methodology.



Step 4: Sequencing of the critical workcenter

This phase consists of finding a good, preferably optimal sequence for the critical workcenter, fixing it and modifying

the constraints such as finish times and release times on other machines according to the results obtained. An

algorithm used at this stage should ideally be fast from a computational point of view and generate solutions whose deviation from the optimal could be bounded within a

reasonable interval. Extremely efficient branch and bound algorithms are available in the literature for the cases without sequence-dependent setup times. In the next chapter

we present optimal and heuristic algorithms for single-machine workcenters with sequence-dependent setup times. How some of

these algorithms can be incorporated into the approximation








66
methodology is illustrated in the prototype implementation in Chapter VII.



Step 5: Use of Disjunctive Graph to Capture Interactions

Note that when a certain subset of the workcenters have been sequenced, certain constraints are imposed on the sequencing problems for the remaining workcenters. Jobs will become available for processing at certain times (release times) depending on how the previous workcenter is scheduled. It is also important to have estimates of the time by which an operation must be completed on a particular workcenter (operation due dates) in order to allow the lot it is performed upon to complete on time. These operation due dates, in turn, form the input to the algorithms used to determine and schedule the critical workcenter.

If we fix the disjunctive arcs associated with the sequences of workcenters already sequenced, we can estimate the release times and operation due dates for operations by performing a number of longest path calculations in the resulting directed graph, in a manner analogous to calculating early start and latest finish times in a CPM problem[3]. If we denote by L(ij,kl) the length of a longest path from ij to kl in the directed graph described above, the release time, i.e., the earliest start time, of operation ij is given by ri, = L(0,ij) SkLij
where kl is the operation preceding ij on the longest path








67

and the operation due date di, by dcj = di L(ij,i*) + Pij

Both these expressions use the longest path operator L(ij,ik) to estimate the time that will elapse between the start of operation ij and the completion of operation ik. Note that in most cases this will underestimate the actual time needed, since it will ignore machine interference effects at the machines not yet scheduled. A similar approach for the estimation of operation due dates from job due dates has been used by Vepsalainen and Morton[94,95] and Baker[4]. An extensive survey of the literature on due date estimation can be found in Cheng and Gupta[25].

Thus the graph representation is used to capture interactions between the different workcenters. Each time a workcenter is sequenced, the due dates and release times of operations on other workcenters are updated in order to include the constraints imposed on the entire system by the sequencing of that machine.

It is clear from the above discussion that the solution of the longest path problems required to set up the local problems at each iteration will form a major part of the computational burden of the approximation methodology. Adams et al.[1] have developed a longest path algorithm that exploits problem structure and has O(n) complexity as opposed to the O(n2) complexity of conventional longest path algorithms. This algorithm must be extended to the case where









68
parallel identical machines and batch processing machines are present. However, when each workcenter consists of a single machine it results in substantial savings in computation time.



Step 6: Reseqruencing in the light of new information.

This step consists of resequencing the workcenters that have already been sequenced in the light of the constraints

imposed on them by fixing the schedule of the latest scheduled machine. The main point here is that it may not be necessary

to resequence all machines already sequenced. Some machines may not interact at all with the newly scheduled machine, and

thus the sequence on this machine will not affect them at all, while others may be affected only insignificantly. What is needed here is some way of determining what machines are the most important to resequence, taking into account the

structure of the job shop and other relevant information. Heck's extension of the concept of a critical path to lateness[54] may form the basis of an approach to this.



Experimentation with Overall Methodology

The development of an efficient methodology based on the

Shifting Bottleneck concept for the types of job shops studied here clearly requires a good deal of empirical work. The methodology itself will consist of a combination of heuristics and optimization algorithms to make the criticality decisions

and sequence the critical workcenters. Other heuristics may








69

be used to determine which workcenters should be resequenced at the end of each iteration. The sensitivity of the overall

procedure to the various procedures used f or each of these purposes needs to be extensively investigated.

The empirical analysis of such a complex approximation procedure for a large combinatorial optimization problem poses interesting difficulties. First of all, one issue is the determination of how good are the results of the approximation scheme. Comparison of the results of the approximation

procedure and dispatching rules, which currently constitute the state of the art in most industry environments, is one approach. This would allow a statistical comparison of the procedures to be made[47]. Estimation of how close to the optimum results are, however, is more difficult due to the fact that obtaining optimal solutions to realistic problems is prohibitively time-consuming. For this purpose, use of statistical techniques to estimate optimal values offers one avenue of approach. Such techniques have been developed and

documented by Dannenbring[30] and Golden and Alt[46]. The overall goal is configure a specific methodology for the type of job shop under consideration, specifying what algorithms to use at each step for each type of subproblem, in order to arrive at a robust way of obtaining good solutions.














CHAPTER V

SINGLE -MACHINE WORKCENTERS



Introduction

In the previous chapter the main methodology with which the problem of sequencing the job shop under study would be attacked was outlined. This methodology requires repeated solution of subproblems related to the sequencing of individual workcenters.

In this chapter, problems motivated by the modelling of workcenters consisting of a single machine will be formulated as scheduling problems and methods for solution presented.



Description of a sing~le-Machine Workcenter

These problems were motivated by the need to schedule

workcenters consisting of a single tester. A number of lots, some of which may require more than one operation with different setups, need to be processed at the workcenter. If a lot requires more than one operation, there are strict precedence constraints between them defining the order in which they have to be performed. Note that a special precedence structure results since there are no precedence


70









71

relations between operations on different lots. Thus, the problem becomes that of sequencing a number of "strings" of operations which must be processed in the order suggested by the precedence constraints but not necessarily in immediate succession. An example of the precedence graph for a singleworkcenter problem with three different lots is shown in Figure 5.1.

All operations on the same lot have the same due date. The measures of performance we wish to optimize are functions of the completion times and due dates of the lots, not of the individual operations. The performance measures of maximum lateness of a lot and number of tardy lots will be examined in this research.

Due to the nature of the production technology, the sequence-dependent nature of the setups is explicitly considered.

Let us define the following notation for the singleworkcenter problem:

n = number of operations to be scheduled

m =number of lots to be scheduled

N = set of operations to be performed at the workcenter

ij operation i on lot j

pi processing time of operation i of lot j on the workcenter

d = due date of operation i of lotj












72

























L











CY)




tv
4


u LO z
4



cu


W
"Cl (V
u Q)
w CD A4

w








73

5ij,kt = setup time necessary to change from operation i of lot j to operation k of lot 1 on the workcenter

rj=the time the lot j becomes available at the workcenter, i.e., the release time of lot j

In order to integrate the subproblems into the main

approach, it is necessary to include release times r.. These times represent the time the lot arrives at the workcenter from previous processing steps. However, in order to gain insight, we shall first relax the release times. In a later section we shall examine heuristics for the case with nonsimultaneous release times.



Minimizing Maximum Lateness

The first problem we shall examine is that of

minimizing maximum lateness (Lmax) of a lot. This can be stated as follows:

"Minimize the maximum lateness of a lot in the presence of precedence constraints and sequence-dependent setup times."

Extending the classification of Lageweg et al.[59,60], this problem will be written as l/prec,SDST/Lmax, where SDST denotes the presence of sequence-dependent setup times. Recall from Chapter III that this problem is NP-hard. Thus the approaches left open to us are the development of implicit enumeration methods, or the design of heuristics.








74

Algorithms for 1/precSDST/Lmax

In this section we shall present two algorithms

developed to obtain solutions to 1/prec,SDST/Lmax. The first is a branch and bound approach that makes use of the fact that 1/prec,SDST/Lmax is equivalent to the problem of minimizing makespan in the presence of delivery times, 1/prec,q1,SDST/Cmax. The second is a dynamic programming algorithm which exploits the special structure of both the precedence constraints and the setup time matrix.



A branch and bound algorithm for l/prec,q ,SDST/Cmax

Recall from Chapter III that the 1/prec,SDST/Lmax

problem can be transformed into an equivalent problem of minimizing Cmax in the presence of delivery times, 1/prec,q1,SDST/Cmax. In this section we describe a branch and bound algorithm to find optimal solutions to 1/prec,qj,SDST/Cmax.

Following the approach of Carlier[20], with each feasible sequence for this problem we can associate a directed graph G = (X,U). The node set X consists of a node for each operation ij carried out on the workcenter, plus a source node 0 and a sink node *. The arc set consists of three types of arcs, U1, U2, and U3 defined as follows:

UI = the set of arcs (0,ij) whose cost is equal to 0

except for the first operation ij in the sequence, for which it is so.ij,









75
U2 = the set of arcs (ij,*) with costs pi + qi1,

U3 = the set of arcs (ij,kl) where ij immediately

precedes ki in the sequence. These arcs have costs equal to j + s 1j,kI

The maximum lateness of a feas ible sequence is equal to the length of a longest path in the associated graph G(X,U). An example of such a graph is shown in Figure 5.2. The nodes have been numbered according to their occurrence in the sequence, with [i] representing the i'th operation in the sequence corresponding to this graph. Another important property of this graph is that the node corresponding to the operation with completion time equal to Cmax will be the node immediately preceding on a longest path.

Hence the problem of minimizing Cmax can be viewed as the problem of finding a sequence such that the length of the longest path in the corresponding graph G is minimized over the set of graphs corresponding to all feasible sequences. We can state the algorithm as follows:



Algorithm BB:

Step 1: Let K = max { d~ }j. Calculate q, = K d.. for ijeN i
each operation ij.



Step 2: Obtain an initial feasible solution by applying some heuristic to the problem. Set the upper bound UB to the value of Cmax for this solution. Let S denote the set of










76




























E-4
cli co
cr Cr
+ + + +
Cj co
cl
4



4
0
(4



CM CY)
C\j co
T-r C\F C6



CM cz
CY)
Cl.




(U
4
z b-0
.rq




U)









77

operations available for sequencing, i.e., those whose predecessors have been sequenced. Let P be the partial sequence of operations already sequenced. Set S to be the set of operations without fixed predecessors, P This corresponds to the root node of

the search tree.



Step 3: Branch by appending each member of S in turn to the right of the partial sequence P associated with the current node.



Step 4: For each new node generated at Step 2, perform the following:

i) Calculate a lower bound LB as described below.

ii) If LB > UB, fathom this node and go to step 5.

Else, check if LB corresponds to a feasible solution. If so, set UB = LB. Update S by adding to it the successors of the last sequenced operation. Go to Step 5.



Step 5: Select for further expansion the open ( i.e., not fathomed or already expanded) node with the lowest associated LB value. If no such node can be found, an optimal solution has been obtained. Else, go to Step 3.



The lower bounds used for fathoming form one of the

most critical components of any branch and bound method. We









78

will present two lower bounds that have been developed for 1/prec, q,, SDST/Cmax.

Let us first consider viewing the qij as a "teardown" time necessary to bring the machine to a final state after the completion of the last operation. Let us refer to this modified problem as (API). The makespan of this problem will be given by


n-l
.pU +Z s[iJ[i+1] + q[nJ
ji~c 1=1

We have then the following propositions:



Proposition 5.1

The optimal makespan for (APl) is a lower bound on the makespan for i/prec,q ,SDST/Cmax.



Proof:

Consider the graph G* corresponding to an optimal

sequence S to l/prec,q1,SDST/Cmax. There are two cases to consider:

i) The operation with maximum lateness in S* is the last in the sequence. Then the longest path in G* is the path 0 [1] [2] ... -[n-li [n] *. Note that by its

definition, an optimal solution to (APl) will be the shortest path from 0 to containing all n nodes corresponding to operations. Hence, the path 0 [1] [2] ... -[n-l] [n] in G must be the same as that








79
generated by the solution to (API), otherwise it would not be optimal. Thus the objective function values of i/prec,q,SDST/Cmax and (API) are equal.

ii) The operation with maximum lateness in S* is not

the last operation. Then, since the objective function value corresponds to the length of a longest path in G*, the path

0 [1] [2] ... -[n-1] [n] cannot be a longest path in G*. Since the optimal value of (API) corresponds to the length of the shortest path of this form, it must be less than the length of the longest path in G*, and hence the optimal value of i/prec,q,SDST/Cmax. Q.E.D.



Proposition 5.2

If the operation having maximum lateness in the

sequence obtained from (AP1) is the last operation in the sequence, then the sequence is optimal to 1/prec, q,, SDST/Cmax.



Proof:

Construct the graph G corresponding to the sequence obtained by solving (APi), numbering nodes according to their position in the sequence. Since operation [n] has maximum lateness, the longest path in G is the path 0 [1]

- [2] ... [n] *, and the length of this path, ZPi + Z sEi 3i+1J + q[n], is equal to the optimal value of (APi). Since we know from Proposition 5.1 that the optimal value of (APi)









80

is a lower bound on the optimal value of

l/prec, q,,SDST/Cmax, this sequence is optimal to 1/prec, %, SDST/Cmax. Q.E.D.



Problem (APl) can be formulated as a Travelling

Salesman Problem (TSP) as follows. Let the cities correspond to the node set of G. Let the arc costs represent the setup times slik for nodes corresponding to operations, and qi1 for arcs incident into node *. There are no arcs incident into node 0 except one from node that has cost 0, which is also the only arc incident out of that node. Thus we have ensured that the tour starts and ends in city 0, with city* the next to last city in the tour. The problem is to find the minimum cost tour starting and ending at node 0 that visits all intermediate nodes exactly once.

Since the TSP is known to be NP-hard, it is not

computationally feasible to use it to develop bounds at each node of an implicit enumeration tree. Therefore it becomes necessary to find a tight lower bound on the optimal value of (APi) which we could obtain with less computational effort. Such a lower bound is provided by the assignment relaxation to the TSP. This problem is solvable in polynomial time, and Balas and Toth[12] have found in an extensive study that this bound is a tight one for the TSP, on average yielding an optimal value equal to 99.2% of the optimal TSP value. It is important to note that the solution









81
generated by the assignment problem need not be feasible for (API), since it may contain subtours and violate precedence constraints.

Since the optimal value of the assignment problem is a lower bound on that of the TSP, then substituting the optimal value of the assignment problem for that of the TSP will still yield a lower bound on i/prec,q1,SDST/Cmax. Thus, if we denote the optimal value of the assignment relaxation of the TSP described above by A, then we have a lower bound LBI given by

LBI = Z p11 + A
ijEN


The lower bound LBI(P) for the partial sequence P at a given node of the enumeration tree corresponding to a partial sequence P is given by

LBI(P) = M(P) + T + A(N\P)

where M(P) denotes the makespan of the jobs in the partial sequence, T the total processing time of jobs in N \ P, and A(N\P) the assignment problem solved for the unsequenced jobs.

A second lower bound, which will be referred to as LB2, is obtained by relaxing the sequence-dependent setup times and sequencing operations in Earliest Due Date (EDD) order. The bound LB2 is set equal to the maximum lateness obtained from this sequence.








82
Dynamic programming algorithms for l/precSDST/Lmax

In this subsection we shall examine dynamic programming procedures for the l/SDST/Lmax problem. We assume that there are m lots of chips to be processed, and that lot i requires N(i) operations. Operations on the same lot are numbered in order of their precedence order. The total number of operations to be scheduled is n. Recall that we have a chain-like precedence graph since operations on separate lots are not linked by precedence constraints. This imposes a fixed ordering on the operations on the same lot. Given this ordering, we now give a dynamic programming procedure similar to that of Monma and Potts[78] to merge the operations on different lots together into an optimal schedule. Define f[n(1),n(2),...,n(m),t,i] to be the minimum Lmax value for a partial schedule completed at time t containing the first n(k) operations of lot k, k=l,...,m where the last operation in the partial sequence comes from lot i. Initially, set f[0,0,0,...,O]=o and all other values to infinity. The optimal Lmax value will be the smallest value of the form

min { f[N(1),N(2),...,N(m),T,i] } where l
m N(i) m
T < Z Epj i + Z N (i) Smax
i=l j=1 i=l

and smax denotes the maximum setup time value.

The function values can be computed using the following recursive relation:








83
f[n(1),n(2),...,n(m),t,i] =

min( max (t-dn(j) f[n' (1) ,n' (2) .,n' (m),t' ,k] I I
1
where n'(j) = n(j) for j;i, n'(i) = n(i)-i and

t'=t-Pn(),i S(n'(k),k),(n(i),i)

The number of possible states in this dynamic program is m(N+l)mT, where N = maxi{N(i)), and the value of each state is calculated in O(m) steps. Hence the computational complexity of this procedure is O(m2(N+l)mT).

When setup and process times are large, the large

values of T will result in rapid growth of the state space and thus of storage requirements. However, we observe that the completion time t of any partial schedule will consist of two components, the processing times of the operations in the partial sequence and the setup times taking place between operations. This enables us to take advantage of the special structure of the semiconductor testing environment. An important characteristic of the production equipment in use is that there are a limited number, generally less than ten, of distinct entries in the setup time matrix. This is much less than n 2, the number of possible entries in the setup matrix. Let the total number of distinct setup time values s(k) be S.

Define f[n(l),n(2),...,n(m),o1al,...,as5i] to be the minimum Lmax value for a partial schedule containing the first n(k) operations of lot k, k=l,...,m and a. occurrences








84
of the j'th distinct setup time value s(j) j=l,...,S where the last operation to be processed belongs to lot i. We can now calculate the completion time t of the partial sequence from the relation

m n(i) S
t = E E pji + aks(k)
i=l j=l k=l


Initially set f[0,0,...,0,0] = 0 and all other values

to infinity. The optimal value will be the smallest value of the form

min { f[N(1),...,N(m),a ,,21...,a S,i] } where Ziai=n. The l
recursive relation can now be written as

f[n(1),n(2) . .,n(m) ,1,02,...,as,i] =

min{ max {t-dn(i),i f[n' (1) ...,n' (m),a', ...,a's,k] } } l
where t is as calculated above, ao = if s s(j) and o'. = a 1 if s = s(j).
1 J(n'(k),k), {n(i),i) i
The number of states in this dynamic program is at most m(N+l)mns, where N = maxi{N(i) }), and the value of each state is computed in O(m) steps. Hence the complexity of this procedure is O(m2(N+ l)mnS)

It is interesting to note that the complexity of these procedures is polynomial in the number of operations but exponential in the number of lots. Thus, when the number of lots is fixed, 1/prec,SDST/Lmax can be solved in polynomial time. When the number of lots is small and the number of









85
operations on each lot is large, this procedure may provide a practical alternative to branch and bound. However, as the number of lots increases, the computational burden increases rapidly.



Heuristic Procedures for 1/r1. Drecc, SDST/Cmax

In this subsection we will first examine the worst-case performance of a certain class of one-pass heuristics, listscheduling procedures, for l/r1,prec,q1,SDST/Cmax. For the sake of simplicity in this section we shall use only a single subscript to represent operations, taking the lot structure into account explicitly as precedence constraints. We shall then examine the behavior of a member of this class that has been extensively studied in the context of the problem without setup times, the Extended Jackson's Rule[20.85], for the special case of the problem where release times and due dates are agreeable, i.e., ri < implies di < d 1.

We can define the family of list-scheduling algorithms as follows:



Algorithm LS:

Whenever the machine is free and there are one or more available operations, select one of the available operations and sequence it next.








86
An operation i is said to be available at time t if ri < t and all predecessors of operation i have already been sequenced at time t.

Note that which of the available operations is to be selected can be specified in different ways. Examples of selection criteria resulting in different list-scheduling heuristics might be to select the operation with earliest due date or shortest processing time.

Due to the presence of release times the schedule

obtained by Algorithm LS will consist of one or more blocks, periods of time in which the machine is continually busy, either in processing or in setup. Let C(LS) denote the maximum completion time of the sequence obtained by Algorithm LS. Let [k] denote the k'th operation in the sequence, and [j] be the operation such that its completion time is equal to C(LS). Then



j-i j
C(LS) = r(i] + Z SNh]h+1 + 7 P[h] + q[j] h=i-i h=i

for some operation [i], before whose arrival the machine is idle.


Proposition 5.3: Let C(LS) be the value of the schedule

obtained from LS for the i/r,prec,q,SDST/Cmax problem, and C the optimal value of 1/r,q1/Cmax, the problem without setup times. Then C(LS) 3C*, and this bound is tight.








87
Proof: As discussed above, j-1 j
C(LS) = r[i] + Z S[h][h+1] + P[h] + q[j] h=i-i h=i

By construction of the sequence, operation [i] is available no later than operation [j], which means that either r[e] I rt],, or ri3 > r,,] and i precedes j. However, the latter case is impossible since if i precedes j then they must be operations performed on the same lot, which means that r[iJ = r j. This contradicts the assumption that r[il > rly. Thus, we conclude that r[] rl,].



j-1 j
C(LS) rj + E SEh]Eh+1 + Z P[h] + q[j] h=i-1 h=i


j-1 j-1
= r, + p + q[j + s [h]h+11 + E P[h] h=i-1 h=i

The first three terms clearly constitute a lower bound on C Each of the latter two terms is less than or equal to the sum of the processing times, which in turn is a lower bound on C Thus, C(LS) < 3C .

We now provide an example to show that this bound is tight. Consider an instance without precedence constraints and with the following parameters:

i ri pi qi 1 0 n 0 2 1 1 n









88
where s12 = n, s2l = 1. Let all other si. values be equal to 0. Algorithm LS will yield a sequence {i,2} with completion time 3n+l. However, the optimal sequence for the problem without setup times is {2,1) with completion time n+2. Thus, C(LS)/C* approaches 3 as n becomes large. Q.E.D.



Remark: Proposition 5.3 is also true for the problem without precedence constraints.

A particular member of the class of list-scheduling algorithms is the Extended Jackson's Rule studied by Potts[85] and Carlier[20]. This algorithm can be stated as follows:



Algorithm EJ:

Whenever the machine is free and there are one or more available operations, sequence next the operation with largest value of qj.



Let [k] denote the k'th operation in the sequence, and [j] be the operation such that its completion time is equal to C(EJ). Then

j-i j
C(EJ) = rci + Z S[hJ[h+1J + Z P[h] + qcj] h=i-i h=i


for some operation [i], before whose arrival the machine is idle.








89
It is clear from Proposition 5.3 that for the general

1/rj,prec,q1,SDST/Cmax problem, C(EJ) < 3C*, where C* is the optimal value of 1/r ,q,/Cmax. However, for a special case of the problem we have the following result:



Proposition 5.4: Suppose rs > rt implies ds dt and thus qs <

qt and s, < p, for all jobs i,j. Let C(EJ) be the value of the sequence obtained by Algorithm EJ, and C* the optimal

value of 1/r ,q/Cmax. Then C(EJ) < 2C and this bound is tight.



Proof: By construction of the sequence, r[1] = mink{rk}, ke{[i],...,[j]}, by the argument in the proof of Proposition

5.3. For any kE{[i],...,[j]), suppose q,, > qk]. It is impossible for [j] and [k] to be operations on the same lot since in that case we would have qj = q[k]. Hence [k] and [j] are not operations on the same lot, i.e., they are not linked by any precedence constraints. Since [k] is processed
earlier than [j], this means either qk > q[J, or r[k] < r[J, which by the assumption of agreeable arrival times and due dates implies q[k > q[J. Both these cases contradict the assumption that q~j, > q[k]. Hence, we conclude that qJ = mink (qk *



It has been shown by Carlier[20] that for any subset I of the operations to be sequenced,








90

H(I) = min{ri i + Z + min{qi)
iEl iEI iEI
is a lower bound on the optimal value of 1/r ,q/Cmax, the problem without setups. Setting I= {[i],...,[j]}, we see


j-1 j
C(EJ) = r[i + Z S[h][h+1 + Z P[h] + q[j] h=i-1 h=i

j j-1
S ri + ZP[h3 + qj3 + Z slh][h+13 hh=1 q h=i-1

j j
rN + 2 P[h] + q[j] + Z pi h=i h=i


< 2C
To see that the bound is tight, consider the following example:

i ri Pi qi 1 0 n 1

2 0 1 n

where s12 = n and s21 = 0. Algorithm EJ returns a sequence of {2,1) with C(EJ) = 2n+2. The optimal solution without setups

is also (2,1} with C = n+2. Thus we see that C(EJ)/C tends to 2 as n becomes large. Q.E.D.



Corollary 5.1: Let L(EJ) denote the value of Lmax of the sequence obtained by applying Algorithm EJ to the corresponding 1/r ,q,SDST/Cmax problem, and L* the optimal

value of 1/r3/Lmax. Then L(EJ) < 2L* + dmax, where dmax = maxi { di 1.