Theory and experiments of electron-hole recombination at Si/SiO2 interface traps and tunneling in thin oxide MOS transistors


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Theory and experiments of electron-hole recombination at Si/SiO2 interface traps and tunneling in thin oxide MOS transistors
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vi, 200 leaves : ill. ; 29 cm.
Cai, Jin
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Metal oxide semiconductors   ( lcsh )
Electrical and Computer Engineering thesis, Ph. D   ( lcsh )
Dissertations, Academic -- Electrical and Computer Engineering -- UF   ( lcsh )
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theses   ( marcgt )
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Thesis (Ph. D.)--University of Florida, 2000.
Includes bibliographical references (leaves 190-199).
Statement of Responsibility:
by Jin Cai.
General Note:
General Note:
General Note:
"2" in title is subscript.

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University of Florida
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I am deeply indebted to Professor Chih-Tang Sah for his education,

encouragement and patience throughout my graduate study at the University of Florida.

I would like to thank Professors Arnost Neugroschel, Ewen Thomson and Sergei

Obukhov for serving on my supervisory committee. I would also like to thank

Professors Hunhui Sun and Xun Wang who led me into the field of solid-state physics

during my senior year at Fudan University.

I am grateful to our industrial mentors from AMD, Harris, Intel, Motorola and

Texas Instrument who provided the samples used in this dissertation research. I am also

indebted to Dr. Tak Ning and Dr. Philip Wong for hiring me as a summer intern at IBM

Research and Dr. Yuan Taur for his mentorship during my internship which exposed to

me the latest state-of-the-art silicon technology. Additional thanks go to my previous

and present colleagues, Dr. Michael Han, Dr. Guoxin Li and Yih Wang, for their

professional helps and personal friendship. Financial support from Semiconductor

Research Corporation and a Robert C. Pittman Doctoral Research Fellowship is

gratefully acknowledged.

Finally I would like to thank my wife, Yijun Chen, and our parents, Fumin and

Yumei Cai, Xuehong and Gendi Chen, for their continuous support throughout my five-

year graduate education.


ACKNOWLEDGEMENT...................................................................................... ii

A B STR A C TS .......................................................................................................... v


1 INTRODUCTION............................................................................. ...... 1

TR A N SISTO R S.......................................................................................... 6

2.1 Introduction................................................................... ........ 6
2.2 Carrier Recombination in MOS Transistor Channel Region..... 9
2.3 Carrier Recombination in MOS Transistor Junction Space
Charge Region........................................... ........................ 18
2.4 Diffusion Limitation and Other Non-Ideal Factors.................. 27
2.5 Application Examples........................................................ 31
2.6 Sum m ary.............................. ............................................... 39

MEASUREMENTS.... .............. ..................... ................ 40

3.1 Introduction............................................. ........................... 40
3.2 Theoretical Analysis.......................................................... 41
3.3 Extraction of MOST Device Parameters............................ 59
3.4 Profiling Interface Traps in Junction Space-Charge Regions.... 66
3.5 Interface Trap Profile in the Channel Region.......................... 70
3.6 Sum m ary............................................ ..................................... 80

TR A N SISTO R S......................................................................................... 81

4.1 Historical Survey.................................................................. 81
4.2 Recent Technology Motivations............................................ 86
4.3 Theory of Tunneling in MOS Structures.............................. 88
4.4 Theoretical Tunneling-Current Voltage Characteristics........... 97
4.5 Experimental Correlations.................................................... 111

4.6 Sum m ary.................................................................................... 129

JUNCTION PERIMETERS IN MOS TRANSISTORS.............................. 131

5.1 Introduction................................................................................ 131
5.2 Theory of Drain Junction Perimeter Tunneling........................ 132
5.3 Tunneling into Quantized Surface Accumulation Layer.......... 139
5.4 Base-Terminal Current under Accumulation Gate Bias............ 148
5.5 Interface Trap Assisted Tunneling............................................. 158
5.6 Sum m ary.................................................................................... 170

6 SUMMARIES AND CONCLUSIONS...................................................... 171

A PPEN D IX .......................................................................................................... .. 175

RE FE REN CE S..................................................................... ..................................... 190

BIOGRAPHICAL SKETCH .................................................................................... 200

Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fullfilment of the
Requirement for the Degree of Doctor of Philosophy



Jin Cai

August 2000

Chairman: Chih-Tang Sah
Major Department: Electrical and Computer Engineering

Surface recombination and channel have dominated the electrical characteristics,

performance and reliability of p/n junction diodes and transistors. This dissertation uses

a sensitive direct-current current voltage (DCIV) method to measure base terminal

currents (IB) modulated by the gate bias (VGB) and forward p/n junction bias (VpN) in a

MOS transistor (MOST). Base terminal currents originate from electron-hole

recombination at Si/SiO2 interface traps. Fundamental theories which relate DCIV

characteristics to device and material parameters are presented. Three theory-based

applications are demonstrated on both the unstressed as well as hot-carrier-stressed

MOSTs: (1) determination of interface trap density and energy levels, (2) spatial profile

of interface traps in the drain/base junction-space-charge region and in the channel

region, and (3) determination of gate oxide thickness and impurity doping

concentrations. The results show that interface trap energy levels are discrete, which is

consistent with those from silicon dangling bonds; in unstressed MOS transistors

interface trap density in the channel region rises sharply towards source and drain, and

after channel-hot-carrier stress, interface trap density increases mostly in the junction

space-charge region.

As the gate oxide thins below 3nm, the gate oxide leakage current via quantum

mechanical tunneling becomes significant. A gate oxide tunneling theory which refined

the traditional WKB tunneling probability is developed for modeling tunneling currents

at low electric fields through a trapezoidal SiO2 barrier. Correlation with experimental

data on thin oxide MOSTs reveals two new results: (1) hole tunneling dominates over

electron tunneling in p+gate p-channel MOSTs, and (2) the small gate/drain overlap

region passes higher tunneling currents than the channel region under depletion to

flatband gate voltages. The good theory-experimental correlation enables the extraction

of impurity doping concentrations, which complements the DCIV method.

Two fundamental theories of interband tunneling are developed to correlate with

the VGB dependence of drain/base p/n junction currents: (1) direct tunneling at the

drain/base junction perimeter with and without the quantization effects in the base

surface accumulation layer, and (2) interface trap assisted tunneling in the gate/drain

overlap region. The second theory gives better correlation, which is further supported

by the DCIV peaks originated from interface traps in the gate/drain overlap region.


One of the most significant advancements in silicon transistor technology

development was the passivation of silicon surface by a thermally-grown oxide layer

some forty years ago [1,2]. Today, the metal-oxide-semiconductor (MOS) transistor has

become the most important building block of ultra-large-scale-integrated (ULSI)

circuits. In MOS transistors, electrical currents conduct in silicon surface channels

directly underneath the silicon/silicon dioxide interface. The mismatch of amorphous

thermal SiO2 and crystalline Si at the interface gives rise to point defects such as the

unpaired silicon dangling bond which acts as an electronic trap. The intrinsic interface

trap density after the thermal oxidation step can be as high as 5x012cm-2,

corresponding to a fractional occupancy of 0.6% of a (100) silicon plane, most of which

are passivated by hydrogenation in a forming gas annealing step, to give a residual

active interface trap density on the order of 1010cm-2 in as-manufactured MOS

transistors. However, during transistor operation, passivated interface traps can be

reactivated and new interface traps can be generated which degrade MOS transistor

performance by lowering its subthreshold slope and increasing its leakage current.

Traditional small-signal measurement techniques such as the MOS capacitance-

voltage method can only resolve interface trap density higher than about 101cm2 and

can not detect manufacturing residual interface traps on state-of-the-art MOS transistors.

The seminal work on surface recombination and channel by Sah [3,4] was recently

extended by Neugroschel and Sah [5] in 1995 to develop a sensitive technique known as

the DCIV methodology that measures the DC recombination current of injected

minority carriers at interface traps. The sensitivity is achieved by forward-biasing a p/n

junction in a MOS transistor structure to exponentially raise the injected minority carrier

concentration. In the past five years, many DCIV application papers and reports have

been published which include delineation of interface trap generation/annealing kinetics

on electrically-stressed transistors [6,7] and diagnosis of transistor design and

manufacturing processes on pre-stress transistors [8-10]. This dissertation analyzes the

theoretical basis of the DCIV method and develops theory-based new applications for

characterization of scaled MOS transistors with very thin gate oxide.

In chapter 2, the gate-voltage controlled interface trap recombination current

from the base-terminal is analyzed using the Shockley-Read-Hall steady-state

recombination kinetics to provide analytical expressions for DCIV lineshape, linewidth,

peak voltage and peak amplitude. It is predicted by the theory that DCIV peaks in the

intrinsic to flat band gate voltage range originate from interface traps located in the

channel area, while additional peaks in the surface accumulation range originate from

interface traps covering the gated p/n junction space-charge region. A new application

to determine interface trap density and energy level from the forward p/n junction bias

dependence of the DCIV peak current is proposed and demonstrated on both unstressed

and channel-hot-carrier stressed MOS transistors. The distortion of DCIV lineshape

from minority carrier injection level and diffusion is also analyzed.

In chapter 3, spatial distribution of interface traps in the gated p/n junction space

charge region (JSCR) is shown by theory to affect the DCIV lineshape in the gate

voltage range between the weak inversion of the channel area and the weak inversion of

the gate-overlapped drain area. In this gate voltage range, the recombination rate per

unit interface trap is sharply peaked in the JSCR due to rapid lateral variation of

minority carrier concentrations. Based on this discovery, an algorithm is developed to

determine spatial density profile of interface traps which has a resolution of -3nm. For

interface traps located outside the JSCR in either the channel area or the drain area, the

gate voltage that gives the peak recombination current depends only on transistor

parameters such as the channel and drain doping concentrations. Thus these peak

voltages provide a means to probe the MOS transistor design parameters. An analytical

three-parameter formula is given to fit the forward junction bias dependence of DCIV

peak voltage for the extraction of gate oxide thickness, impurity doping concentration

and flatband voltage.

MOS transistor has been aggressively downscaled in the past 25 years to

increase its speed while reducing its manufacturing cost at the same time. This trend

will continue in the near future [11-12]. In each technology generation, gate oxide

thickness is scaled almost in proportion to the channel length, while the Si/SiO2

interfacial layer can not be scaled and becomes a more significant part of the total SiO2

thickness in thin oxide MOS transistors. The DCIV method will continue to be a

powerful tool for evaluating interface reliability as well as for characterizing transistor

design. On thin oxide MOS transistors, DCIV measurements show base-terminal

current that rises with gate voltage, due to (1) increased gate oxide tunneling current at

both inversion and accumulation gate voltages, and (2) increased current flow through

forward-biased drain/base p/n junction at accumulation gate voltages. Quantitative

understanding of these two phenomena will not only provide accurate baselines for

DCIV peak analysis, but also enable new techniques for the characterization of scaled

MOS transistors.

Recent experimental data on ultrathin oxide (1.0nm-3.0nm) MOS transistors [13]

prompted us to develop a gate oxide tunneling theory that takes into account all three

tunneling particle species (electrons, holes and valence electrons), which is presented in

chapter 4. Theory-experimental correlation will prove two results: (1) hole is the

dominant tunneling carrier in p+ gate p-channel MOS transistors, which was not

recognized previously, and (2) the much smaller gate/drain overlap area passes higher

current than the channel area in the gate voltage range between flatband and strong

inversion [10,13]. Experimental tunneling currents from gate, source/drain, well and

substrate terminals will be matched with the tunneling theory from which transistor

design parameters such as oxide thickness, impurity doping concentrations in the

channel and drain areas are determined.

In chapter 5, physical origins for the increased DCIV base-terminal current at

accumulation gate voltages are investigated. Two theories of interband tunneling are

considered: (1) direct tunneling at the drain/substrate junction perimeter including the

effects of quantized surface accumulation layer, and (2) interface trap assisted tunneling

in the gate-overlapped drain area. The second theory has a lower threshold gate voltage


and predicts a Shockley-Read-Hall recombination current peak from interface traps

located in the overlap area, both of which are supported by experimental data.

We will summarize and conclude the dissertation in chapter 6.


2.1 Introduction

Surface recombination and channel have dominated the electrical characteristics,

performance, and reliability of p/n junction diodes and transistors. Due to the

technological importance, extensive research efforts have been undertaken to study

interfacial electronic traps at the Si/Si02 interface and to delineate their microscopic

(atomic) origins [14]. Two kinds of density-of-states (DOS) spectra were repeatedly

observed in the energy gap of silicon: two DOS peaks near the midgap and a U-shaped

distribution that rises towards the two band edges. The discrete energy levels are

characteristic of point defects at the Si/SiO2 interface, while the U-shaped band-tail

states are from random variations of Si-O bond length and bond angles [15]. These

conclusions were supported by early works of molecular-orbital calculations of Si/SiO2

interfacial electronic structures [16,17].

The peaked DOS were correlated to the trivalent silicon dangling bond (Pb

center) on oxidized (111) silicon [18-20] and its two variations (Pbo and Pbl centers) on

oxidized (100) silicon by the electron spin resonance (ESR) experiments [19,21].

Recent studies using ESR on oxidized silicon and spin-dependent recombination (SDR)

on MOS transistors reveal that the two Pb centers on (100) Si have different generation

and annealing kinetics. Electric field stress including the non-uniform channel hot

carrier stress [22] and the uniform Fowler-Nordheim stress [23] creates mostly PbO

centers, while both centers can be either passivated or generated by atomic hydrogen

[24,25]. The structural difference among the three Pb centers can be grossly described

by the direction of the single unpaired Si sp3 hybrid orbital. It points to a normal <111>

direction for both the Pb center on (111) Si and the Pb center on (100) Si, while it points

nearly along <211> for the Pbl on (100) Si [26]. Multiple DOS peaks of yet another

origin were observed by 10.2eV light-induced hole injection in MOS capacitors

annealed in oxygen ambient which could be from oxygen dangling bonds at the Si/Si02

interface [27].

While electron spin resonance has been used to identify the atomic structures of

interface traps on large area (~lcm2) oxidized silicon wafers, other techniques are more

traditionally used to monitor interface traps in MOS transistors and MOS capacitors in

manufacturing facilities. This includes MOS capacitance [28,29] and conductance [30]

methods and more recently the charge-pump method [31] and DCIV method [5].

Routine manufacturing processes have reduced interface trap areal density to below

1010cm-2 by slow cooling after high-temperature oxidation steps and by post-oxidation

annealing in hydrogen. At this low density, the DCIV technique has its unique

advantage in sensitivity over the other small-signal and transient techniques.

The principle of DCIV is the use of a surface potential controlling gate terminal

voltage, VGB, to modulate the base-terminal DC current, Ig, from electron-hole

recombination at the SiO2/Si interface traps [3,4]. The DCIV methodology, which gives

a family of IB-VGB curves from MOSTs and gated p/n junctions, was recently developed

by Neugroschel and Sah [5] to monitor the density of oxide and interface traps generated

by hot carriers (HC) in bipolar-junction and metal-oxide-field-effect transistors (BJTs

and MOSTs) in order to determine the transistor failure rate and 10-year operation time-

to-failure (TTFop) voltage [32]. Its application was extended to monitor the degradation

rate of transistors stressed at high current-densities and low voltages (HJ), and to

delineate the origin of hydrogen-related interconnect degradations [6,7]. Recent

demonstrations showed that the DCIV method could serve as a highly sensitive

diagnostic monitor for transistor designs [8] and manufacturing processes [8,33]. The

DCIV lineshape (i.e. Ig vs VGB around the IB-peak) was also used to obtain the electronic

and quantum-mechanical properties of the residual SiO2/Si interface traps on state-of-

the-art thermally grown thin gate oxides [34].

This chapter reports the elementary theory of the IB-VGB characteristics to help

quantify the applications of the DCIV methodology for the extraction of fundamental

and application-specific properties of transistors and interconnects and their materials,

such as the physical (spatial location and density) and electronic (quantum density of

states) properties of the residual and stress-generated interface and oxide traps, the

dopant impurity concentration profiles, and the hydrogen sources. Analytical solutions

and their physical models are presented first to illustrate the effects of material and

interface trap parameters on the IB-VGB lineshape and on the VGB-peak value at the

IB-peak. Application examples are then given for the process-residue and hot-carrier-

generated interface traps on thin thermally oxidized gate-oxide of production MOS


2.1 Carrier Recombination in MOS Transistor Channel Region

In DCIV measurements, excess minority carriers are injected by a forward-

biased p/n junction into the MOS-gated SiO2/Si interface which covers MOST's channel

region (denoted by MCR for mid-channel region) and drain-source junction space-

charge region (JSCR). The p/n junction can be located either away from the gated

interface, such as the well/substrate junction (bottom-emitter, BE) and a remote p/n

junction (remote-emitter, RE) or under the gated interface, such as the source or drain

p/n junction (source-emitter, SE, and drain-emitter, DE, or top-emitter with source-drain

tied to the same forward bias voltage). The IB-VGB theory is presented for these

injection bias configurations. The IB-JSCR current is especially important for factory

applications to monitor channel-hot-carrier-generated interface traps, while the IB-MCR

current is also useful for determining the electronic properties of the process-residual

and stress-generated interface traps. Modifications of the theory by DCIV bias

configurations, diffusion, dopant-impurity profiles and 2-dimensional geometries are

then discussed.

Figure 2.1 is the energy band diagram of the metal-oxide-silicon structure with a

forward-biased p/n+Si bottom emitter (BE) junction. It is labeled in detail to help

describe the approximations of the analyses as follows. All voltages are normalized by

kT/q. The BE is forward-biased at UBE while the DC voltage applied to the gate



UGB > 0






E, E

Up Bg

---XB -



Fig. 2.1 Energy band diagram and cross-sectional view of a gated SiO2/p-Si/n+Si
structure with the p/n' junction forward biased. UN and Up are respectively
the electron and hole quasi-Fermi potentials normalized to thermal voltage
(kT/q). Labeled on the figures are the terminologies (gate, base, and
emitter), dimensions [XBO and XB(VGB,VEB)], and the normalized (to kT/q)
voltages and quasi-Fermi-potentials (UGB, UFB=Flat-Band, and Up, UN).

relative to the p-Si base is UGB. UN and Up are electron and hole quasi-Fermi potentials

in p-Si and their difference, known as the quasi-Fermi-potential split, is UPN=Up-UN

which is slightly smaller than the applied BE voltage, UBE. A formula for AUpN will be

derived later. In the quasi-neutral region of p-Si base (BQNR), the quasi-Fermi-

potentials are:

Up= + log{ (N+4niexpUpN) 1/2+N] /2ni} (2.1)

UN log{ [ (N +4nexpUpN) 12- ] /2ni} (2.2)

The electron and hole concentrations at the SiO2/Si interface (Ns and Ps) are modulated

by the gate voltage via bending the Si energy band. The total energy band bending is

denoted by the surface potential Us=U(x=0,y).

There are four fundamental transition processes between the continuous band

states of silicon crystal and the localized trap states with an energy level ET in the Si

energy gap, as shown in the transition energy band diagram of figure 2.2. The rate

(event/second) of the four processes can be conveniently described by: (a) electron

capture from the conduction band at Cnn(NTT-nT), (b) electron emission to the

conduction band at ennT, (c) hole capture from the valence band at cppnT, and (d) hole

emission to the valence band at ep(NTT-nT). Here n and p are electron and hole

concentrations in the conduction band and valence band respectively, NTT is the total

density and nT is the electron-occupied density of trap states, and e's and c's are

emission and capture rate coefficients of the four processes which depend on the energy

levels of both the trap state and the band state. These transition processes are mostly

thermal involving emission and capture of phonons (ho). Since the indirect energy gap



en T

^ G

nl hi



ep (NTT-nT)

Fig. 2.2 A transition energy band diagram showing four fundamental transition
processes between a band state and a gap state in silicon: capture of a
condition band electron by the trap (a), emission of an electron to the
conduction band from the trap (b), capture of a valence band hole by the
trap (c) and emission of a hole to the valence band from the trap (d). The
volume density of band electrons, band holes, electron-occupied traps and
total traps are n, p, nT and NT respectively. The rates of the four process
are shown in terms of e's and c's. Purely thermal emission and capture
processes involve multiple phonons.

4 I

nT i

Cp pnT

Cn n(NTT-nT)



of Si is 1.12eV and the maximum optical phonon energy in Si is only about 60meV, the

thermal capture and emission processes could involve about ten phonons for mid-gap

trap levels.

Theoretical calculation of a multi-phonon process was first done by Huang and

Rhys [35] and later refined by Huang [36]. In contrast to the lattice scattering process

which can be treated by taking the linear coupling of electron Coulomb potential and

lattice vibration as the perturbation to calculate the scattering rate, the multi-phoono

process can not be treated in such a way since the linear coupling term could only result

in the emission and capture of a single phonon. Instead, the breakdown of the adiabatic

approximation [37] was used as a perturbation to compute the transition rate between

the band state and the trap state while the linear coupling term was used in the time-

independent perturbation theory to compute the lattice distortion/relaxation [38] in the

initial and final states. The first-principles calculation of the capture cross-sections in a

multi-phonon process is rather laborious. For the purpose of developing a theory for the

DCIV methodology, it would suffice to use the phenomelogical kinetic theory

developed by Shockley and Read, and by Hall [39] which treats the fundamental capture

and emission rates as constants independent of kinetic energies of band electrons and


The steady-state areal rate, Rss, of electron-hole recombination at a discrete-

energy-level interface trap (the equilateral triangle in Fig. 2.1), located at UTI from the

intrinsic Fermi potential, with a density of NIT (#/cm2), is given by the Shockley-Read-

Hall formula:

(CnsCpsNsPS enseps)
Rgg = NyI = RSSN *IT (2.3)
CnsNS + ens + CpsPS + eps

Cns, Cps, ens and eps are the electron-hole capture-emission rate coefficients at the

interface traps. From detailed balance near thermal equilibrium, c's and e's are related

by ens = Cnsniexp(UTI) and eps = Cpsniexp(-UTi). Using Boltzmann representation,

Ns=niexp(Us-UN) and Ps=niexp(Up-Us), then (1) becomes

(1/2) (cnscps )1/2n exp(UPN) -1]
exp (UpN/2) cosh (Us) + cosh(UTI,)

where Us.(x=O) = Us+loge(cns/cps)/2-(Up+UN)/2, and UTI* = UTI loge(Cns/Cps)1/2. The

expression (2.4) is exact with no approximations other than the thermal Boltzmann

distribution with lattice temperature T. It immediately shows the presence of a peak at

Ugs=0. The peak magnitude and the surface potential at the peak are

(1/2) (cnscps) 1/2ni[exp(UPN)-1]
RsS-peak = NIT
exp(UPN/2) + cosh(UTI*)

SRSS1-peak NIT (2.5)

US-peak = (U+UN) /2 loge(Cns/Cps)1/2 (2.6)

The peak formula (2.6), was derived by Sah et al. in 1957 [40]. The half width at half

maximum (HWHM) of the Rss-Us line is:

AUs = cosh-1[2+exp(-UpN/2) cosh(UTI, )] (2.7)

= cosh-1(2), for UpN > 2(IUTII + 4)

= UTI, (UpN/2) for UPN < 2(IUTI*I 4)

The HWHM drops to the narrowest, (cosh-'2)*(kT/q)=1.32kT/q=34mV, at high VPN

and widens to UTI* at low VpN. Results (2.4)-(2.9) are valid at all injection levels in

both p- and n-Si. For single-discrete level interface trap, they predict a peak body-

terminal recombination current, given by IB-peak = qRssl-peak NiTdydz that is

proportional to exp(UpN/n) with a transition of n from 1 to 2 over a small range of

forward bias, about AUPN=4 or AVpN=100mV. This result gives two important

consequences. First, for a single species of interface traps with a spatially varying

concentration, the DCIV lineshape will not change due to the y-distribution of NIT.

Second, if there are many interface trap species, each with a different energy level EI*,

IB is then just the superposition of the bell-shaped Rss curves one from each of the

energy levels or species with different peak locations in VGB, resulting in a broadening

and generally bell-shaped multi-peak DCIV curve [34] and an n-slope between 1 and 2

over a larger range of VPN.

For low injection levels, traditionally defined as N < NAA/10 in p-Si, we have

Up=UF>O for p-Si (UN=UF<0 for n-Si), where UF is the majority carrier Fermi potential.

This is the common application range of the DCIV methodology. At low levels,

equation (4) becomes:

US-peak = UF UPN/2 loge(cns/Cps)1/2 (p-Si) (2.8)

= UF + UpN/2 loge(cns/cps)1/2 (n-Si). (2.9)

Thus, the peak is in the flat-band to intrinsic gate-voltage range (0
this gate-voltage range, Sah [41] had given a formula for Vs(VGB) listed in (2.10) below

which we shall use to obtain the analytical solutions for the IB-VGB linewidth.

Vs = VGB VFB -

2.sign(Vs) *VA{ [1+(VGB-VFB-kTAD/q) /VA]1/2 1} (2.10)

VFB is the flatband voltage, VAA=sqNAA/2C2x where Cox=Eox/Xox is the oxide

capacitance per unit area, and AD=l in this range [41]. The last term in (2.10) is the

voltage drop across the oxide layer, whose error is negligible when using AD= 1 until Vs

is about kT/q from the flatband condition. The VGB at the peak can be solved from

(2.10) in terms of VSpeak given by (2.8) and (2.9):

VGB-peak VFB = VS-peak +

2 sign (Vs-peak) (VAA I VSpeak )1/2 (2.11)

Thus, the DCIV peak location is determined, via VS-peak, by the substrate impurity

concentration, trap parameters in terms of loge(cns/cps) and oxide thickness (from VAA).

The half-width at half maximum (HWHM) of the DCIV peak is:

AVGB = AVs + 2fv [ Vs-peak VS-peak I -AVs
(flat-band side) (2.12)

= AVs + 2 fv [ VS-peakl+AV Vs-peak ]
(intrinsic side) (2.13)

Since Rsg is symmetric around the peak in Vs, (2.12) and (2.13) show that the DCIV Ig-

VGB lineshape is asymmetric and slightly wider on the flat-band side of the peak than

on the intrinsic side. The difference is on the order of 0.5(VAAVSpeak)/2(AVs/Vspeak)2

which is more pronounced in transistors with thick oxide and high surface impurity


At high injection levels with N > 10NAA, we have Up=-UN or the electron and

hole concentrations are nearly equal in the BQNR, and the maximum surface

recombination rate is near the flat-band. The exact result is US-peak = loge(cps/cns)1/2

derived from (2.6). So the peak could not move deeply into accumulation range even at

extremely high forward bias since cps/cns is not likely to be outside of the range of 0.01

to 100 for any physically realistic bound state. The linewidth at the high injection level

limit is obtained from the general MOS voltage equation in p-Si, VGB(Vs):

VGB-VFB-VS = sign(Vs) (kT/q) .

{2UAA[ (eus-l-Us) (a-1) + (e-US-1+Us) (a+1) ]}12 (2.14)

where a = [1 + 4n2exp (UpN) /NAA]1/2. At high injection levels, a =

2exp[(UpN/2)-UF] >> 1. Only one term in the { } of (2.14) will dominate, depending

on the sign of Us:

VGB-VFB-VS = 2 (kT/q) (UA) 1/2sign (U)

exp [ ( I Us I +UN/2-UF) /2] (2.15)

The half-width of the DCIV line is then


2 (kT/q) (e+AUS/2-1) [U Cps/Cnsexp (UN/2-UF) ] 1/2
(cps>cns,Vs>0) (2.16)

2 (kT/q) (1-e-Us/2) [U, Cns/Csexp (UPN/2-UF) ]1/2
These results show that the Full Width Half Maximum (FWHM) has the exp(UpN/4)

dependence on forward bias at high injection levels. Thus, at low injection levels, the

IB-VGB linewidth can be large which is determined by the trap level, ETI-. The

linewidth then decreases with increasing VpN (to about FWHM=70mV for very thin

oxide) until the onset of high injection level condition, beyond which it increases

exponentially with VpN.

Figure 2.3 shows the theoretical and normalized DCIV lineshapes or the unit

steady-state recombination rate, Rssi vs VGB. The shape changes with increasing

forward biases, VpN, applied to a n+/p junction in p-Si with an acceptor impurity

concentration of NAA=1017cm-3, an oxide thickness of 5.0nm, and a discrete interface

trap level at ETI.=200meV. For VpN
maximum Rss1. The linewidth gradually decreases with increasing VpN and reaches the

high injection level asymptote as indicated by the dashed line at VpN=900mV.

2.3 Carrier Recombination in MOS Transistor Junction Space-Charge Region

The preceding IB-VGB theory applies to interface traps over MOST's mid-

channel region. This IB component will be denoted as the IB-MCR. The MCR formulas

assumed that there is no lateral variation of the carrier concentrations, thus, the surface

energy band bending Us is constant, independent of y, at a given gate voltage. For

interface traps over MOST's source and drain JSCR, the foregoing analysis needs to be

extended to take into account of Us(y) in the JSCR. These interface traps contribute a

second component to Ig, denoted as IB-JSCR, when source, drain or both of them are

forward biased. Figure 2.4 illustrates the cross-sectional view and the energy band

diagram at the SiO2/Si interface, x=0, of a forward-biased abrupt p/n+ junction. In Fig.

2.4, the build-in potential of the p/n+ junction is given by

a, I "I-
CZ 900mV -+i I =0

-0.5 0 0.5 1.0

VGB-VFB /(1 V)

Fig. 2.3 Theoretical normalized DCIV lineshapes as a function of minority carrier
injection levels, VPN. Parameters used are as follows. VpN=0-900mV at
100mV intervals with OmV and 900mV the asymptotes. p-Si with NAA =
1017cm3. ni=101cm-3. Oxide thickness Xox=5.0nm. Discrete interface
trap at ETI = 200meV from the intrinsic Fermi level (-mid-gap) with
Cns=Cp = 10-cm3/s, and NIT=low--0 but arbitrary since normalized.


Fig. 2.4 The x-cross section view of the two-dimensional energy band diagram of a
p/n' junction on the SiO2/Si interfacial plane, x=0. The one-sided junction
space charge region extends from y=0 to Y=YEB in the p-Si. VBI = built-in
potential of the p/n' junction, VB = p/n+ barrier height = VBI Vs VpN,
Vs = surface band bending outside the JSCR, and VpN = Vp VN = forward
bias voltage applied to the p/n+ junction disregarding voltage or potential
drops. All labeled potentials are normalized to (kT/q) with subscripted (#)
symbol U#=qV#/kT.

VBI=(kT/q)loge(NAANDD+/n2). The total normalized barrier height at the surface of the

p/n+ junction is:

UB=UBI-UPN-Usx+USE (2.18)

where Usx and USE are the surface band bendings outside of the JSCR in the MCR and

in the emitter (n+drain) region respectively. We use U(y) to represent the normalized

surface potential in the JSCR along the interface from y=0 at the junction boundary to

Y=YEB at the p-edge of the JSCR, with U(YEB)=Usx given by boundary condition.

For the one-sided p/n+ junction, the n+ side JSCR is much smaller than the p-

side JSCR and the lateral (y-direction) voltage drop across the n+ side JSCR can be

neglected. However, the vertical (x-direction) surface band bending in the n+drain is

significant at large negative gate biases even for highly degenerate doping

concentrations. Figure 2.5 shows surface band bendings Vsx in part (a) and VSE in part

(b) for the gated p/n+ junction as a function of gate to p-substrate voltage VGB with the

drain to p-substrate forward bias VDB=-VPN as a parameter. The results were obtained

by solving one-dimensional MOS capacitor equations taking into account of non-

equilibrium minority carrier concentrations. At VGB<-IV when the p-substrate surface

is strongly accumulated, surface band bending in n+ drain with NDD=1019cm-3 becomes

more significant than that in the p-substrate with NAA=1017cm-3. VSE reaches -1.0V at

VGB=-3V under a 100mV forward bias, while Vsx is at -0.25V at the same gate voltage

and is independent of forward bias. It shows that under the surface accumulation VGB

range, Vsx is the dominant term in eqn. (2.18) for UB and therefore indispensable in

evaluating the surface potential U(y) in the JSCR.

I I1t-yrCt. UA IV U 11
> 0.6 ox: 3.0nm

CX 0.3

-0.3 I I II i
0.3 I I I

n+Drain: 1019cm-3
S 800mV
> -0.3-



-3 -2 -1 0 1

VGB /(1V)

Fig. 2.5 Surface band bending in (a) p-substrate, Vsx and (b) n+ drain, VSE as a
function of gate voltage, with the forward bias on the drain/substrate
junction as a parameter that varies from OV to 800mV with a step size of
100mV. Transistor parameters include doping concentrations:
NAA=107cm-3 in p-substrate, NDD=1019cm-3 in n+ drain and 5x109cm-3
in n+ polysilicon gate, and gate oxide thickness of 3.0nm.

The carrier concentration at 0
N (y) = niexp[U(y) -UN] = niexp[Usx+U(y) -U (YEB) -UN]

Pg (y) = niexp [Up-U(y)] = niexp[Up-Usx-U(y) +U (YEB) ]

IB-JSCR is then obtained by integrating Rss, given by (2.3) over the JSCR, which




IB-JSCR = IBJO (2.21)
0 exp(UpN/2)cosh(UsJ) + cosh(UTI,)

where for the p/n+ junction

IBJO = q(CnsCps) 1/2(ni/2) [exp(UpN)-l] (Ampere) (2.22)
US* = Usx + U(y) U(YEB) (Up+UN)/2 + 1oge(cns/cps)1/2

Two NIT spatial distributions will be considered: (1) Localized NIT(y)=NIT6(y-

YT) and (2) uniform NIT(y)= NIT = constant. The localized interface trap distribution is

expected for channel-hot-carrier generated traps in MOSTs from Sah's Si:H bond

breaking model [42] in which the generated silicon dangling bonds are concentrated at

the location near the drain junction towards the source where the secondary hot carrier

kinetic energy reaches the Si:H bond energy (3.1eV).

For the localized spatial distribution, IB-JSCR has a peak when Us,*=0 in (2.23),

which gives:

USX-JSCR-pk = (Up+UN)/2 loge(Cns/Cps)1/2 [U(YT) U(YEB)

= USX-MCR-pk (YT) U(YEB)]

This shows a general result: the IB-JSCR peak is always at the accumulation gate-voltage

side of the IB-MCR peak. For interface traps located closer to the p/n+drain junction

boundary, y=0, [U(YT->O)-U(YEB)] in (2.24) is larger and the peak is further into the

accumulation VGB range. Quantitative results can be obtained from analytical solutions

when aEx,/axl<
does not modulate the potential variation inside JSCR, only outside in the MCR. Then,

using the depletion approximation, U(y) assumes the quadratic form illustrated in Fig.3

given by

U(y) U(YEB) = (q/kT) (qNA/2cs) (YEB- y)2

= (YEB-y) 2/2L2 0
where LD = [(kT/q)(Es/qNAA) 1/2 is the Debye screen length in p-substrate, U(YEB)=USX

and the JSCR barrier height is given by Ug = U(0) U(YEB) YB/2La. The thickness

of the JSCR, YEB, is determined from the barrier height UB. Using (2.18) and (2.25),

we derive the following expression for the surface potential at the trap location y=YT

inside the JSCR in terms of surface band bendings outside of the JSCR, Usx and USE:

U(YT) = UBI UpN + USE -

2 [UYT(UBI-Usx-UpN+USE) 1/2 + UYT (2.26)

where UyT Y 2LD. At IB-JSCR peak, U(YT) satisfies equation (2.6), which together

with (2.26) provide the following equation to relate the two surface band bendings at the



[UBI-UN/2 -UF+USE-JSCR-pk+UYT+ 1ge(Cns/Cps)1/2]2 (2.27)

The surface band bendings outside the JSCR in p-substrate and n+ drain are both

determined by the gate voltage through the one-dimensional MOS capacitor equation.

Thus eqn. (2.27) provides a means to numerically solve the two surface band bendings

at IB-JSCR peak.

The result of IB-Vs HWHM (denoted by AVs) in equation (2.7) applies to all NIT

locations, while the result of IB-VGB HWHM in (2.10) and (2.11) applies to NIT in JSCR

only if U(YT)-U(YEB) < USX-MCR-pk so that USX-JSCR-pk in (2.24) will not change sign,

which corresponds to NIT located near the p-edge of the JSCR. If the condition is not

satisfied, then AVs translates differently to AVGB because the peak is now in the

accumulation range while (2.10) of VGB(Vs) is valid only for the depletion range. To

give an analytical solution in the accumulation range, we use the asymptotic Vs(VGB)

equation given by [41]:

Us = -loge (UGB-UFB-Us)2/4U + AA] (p-Si) (2.28)

with AA= 1, then the HWHM of IB-VGB is given by

AVGB = AVs + 2 (kT/q) 4U exp( UIsx-JscR-pk /2) [exp (AUs/2) -1]
(accum. side) (2.29)

AVGB = AVs + 2 (kT/q) JUAexp( IUsx-JSCR-pk /2) [1-exp(-AUs/2) ]
(FB side) (2.30)

To compare the linewidth of JSCR peak to that of the MCR peak, we examine

the change of surface potential U(YT) with respect to an infinitesimal change of VGB by

taking the derivative of eqn. (2.26), which gives:

AU(YT) = [1-(UyT/UB) /2AU]sE + (UYT/UB)1/2AUsx

= [1-(YT/YEB)1/2]AUSE + (YT/YEB)1/2AUS (2.31)

In the limit that the interface traps are located near the MCR (YT--YEB), the JSCR peak

is close to the MCR peak with gate voltage corresponding to the weak inversion of p-

substrate surface where IAUsE<
near the drain region (YT->O), the JSCR peak is close to the drain peak where

IAUsEI>>AUsxl, refer to Fig. 2.3. Therefore the two asymptotic limits of (2.31) are:

AU(YT) = (YT/YEB)1/2 AUSX YT-YEB, near MCR (2.32)

AU(YT) = [1-(Y,/YEB)1/2] AUSE YT-O, near drain (2.33)

The above equations clearly show the DCIV linewidth dependence on the spatial

location of the interface trap YT. If the interface traps are near the two edges of JSCR,

the DCIV linewidths approach those of the MCR peak and the drain peak respectively,

as AU(YT)=AUsx at Y,=YEB and AU(YT)=AUsE at YT=O. The DCIV linewidth

increases as a function of (YEB/YT)1/2 as the location of NIT moves away from the MCR

edge into the JSCR, it increases as a function of 1/[1-(YT/YEB)1/2] as the NIT location

moves away from the drain edge.

In case of a spatially constant NIT, we shall evaluate the IB-JSCR integral, (2.21),

analytically to describe the dependence of this current component as a function of VpN.

Since the integrand is expected to be a bell-shaped function with a maximum surface

recombination rate at y=YM that satisfies UsJ =0 in (2.23) we can use the Taylor series

to expand the integrand about y=YM and keep terms up to the second order. The result

is then

22qc cnsCpsniNITZ
3(q EM /kT)

[exp(UpN) 1]
exp (UpN/4) [exp (UpN/2) +cosh (UTI.) ]1/2

EM is the electric field at the position YM(VGB). EM varies with a low-power-exponent

of VpN so that the Ig dependence on VpN is dominated by the exponential dependence of

VpN shown in numerator and denominator of (20), which predicts a n=1.33 to n=2

transition from low forward biases to high forward biases with a transition range of

about UpN-8 =200mV.

2.4 Diffusion Limitation and Other Non-Ideal Factors

DCIV measurement on MOS transistors can use four different bias

configurations to inject minority carriers to the SiO2/Si interface [8], as illustrated in

figure 2.6. They are the drain-emitter (DE), source-emitter (SE), top-emitter (TE) with

both source and drain junctions tied and forward-biased together, and the bottom-emitter

(BE) in transistor structures having a well/substrate p/n junction which can be forward

biased. In each of the bias configurations, the p/n junctions not forward biased are zero-

biased (they can also be reverse-biased or even forward-biased at a lower voltage). In

the first three gated-emitter configurations (DE, SE, TE), the body-terminal current Ig

has two surface recombination components: from the MCR, IB-MCR, and from the one or

two emitter-base JSCRs, IB-JCR, while in the ungated BE configuration, IB contains only

IB-MCR because the drain and source p/n junction collectors are grounded so their

IB-JSCR=0. However, the zero-biased source and/or drain p/n JSCR's also reduce the

interface minority carrier concentrations in the MCR. This lowers IB-MCR and changes

the IB-VGB lineshape which becomes appreciable in short channels. A more prominent




Fig. 2.6 Four DCIV bias configurations: (a) Drain-emitter, (b) Source-emitter, (c)
Top-emitter, and (d) Bottom-emitter.



lowering and shape-change of IB-MCR arises from the 2-dimensional geometrical edge

effect due to the proximity of the grounded collector and forward-biased emitters in the

thin-base whose base thickness under the drain and source junction, is comparable with

the metallurgical channel length. Another source of deviation from the simple ideal

theory comes from the 2D impurity doping profiles as a result of channel and junction

engineering. Minority carriers injected from the body/well junction in BE-DCIV will

have a drift component due to the built-in field Ex(x) = (kT/q)d(logeNAA)/dx from the

vertical impurity profile. The vertical profile also gives a variation of the injected

minority carrier concentration near the source and drain junction perimeters. These

would give a difference between the TE and BE lineshapes. The channel regions that

have different NAA(x=0,y) and different oxide charge density, QoT(y), will shift VGB Of

the DCIV peaks which are combined into a broader peak.

Diffusion of the injected carriers in the BQNR (Base Quasi Neutral Region) can

affect and even limit the terminal Ig, especially the IB-VGB lineshape. For example, the

interface recombination rate could be so high that the minority carrier concentration at

the SiO2/Si interface is decreased below the injected value at the injecting p/n junction

boundary, Ns < No = (n/NAA)exp(UBE). In the limit of NIT--o, Ns=(nf/NAA) or

UpN(x--)=0. The interface recombination and base diffusion mechanisms are in series.

In contrast, bulk-JSCR recombination (the Sah-Noyce-Shockley or SNS current

component) and base diffusion mechanisms are in parallel [40]. Thus, the gate-

controlled terminal IB in the DCIV methodology is limited by the smaller of the two

series current mechanisms, base diffusion current at low VpN and interface

recombination current at higher VpN. A simple analytical solution to include diffusion

limitation is obtained using VBE = VpN+AVpN and assuming that AVPN is mainly in the

BQNR since the surface-space-charge layer is much thinner than the BQNR. Then,

AVPN(VBE) at the IB-peak can be obtained as follows by equating the interface

recombination current to the diffusion current:

JB-peak = [qni(CnsCp) 1/2NIT/2] .

[exp(UN)-l] / [exp (UpN/2) +cosh(UTI) ] (2.35)

= JD = (qDB/Xg) (n /NA) exp(UpN) [exp(AUpN)-I] (2.36)

which gives

exp (AUp) -1

= (NXB/niDB) [ (CnsCps) 1/2NIT/2]

[l-exp(-UpN) ] / [exp(UPN/2) +cosh(UTI) ] (2.37)

= 1000 [l-exp(-UN)] / [exp(UpN/2)+cosh(UTI,) ] (2.38)

= 1000./cosh(UT*),

for 0
= 1000.exp(-UpN/2),

for UpN>2[logecosh(UI) +2.3]=2(U( U, +1.6) (2.40)

Dg is the minority carrier diffusivity in the base well of XB thick. The value of 1000 is

obtained from using the following estimated typical values: cns=Cps=10-8cm3/s for a

0.3nm diameter neutral potential well of the interface traps and NIT=2 109cm-2 (which

give a surface recombination velocity of S=(cnsCps)/)2NIT=20cm/s); NAA=107cm3 at

x=Xg, ni=10l1cm-3, Dg=10cm2/s, and XB=10-4cm which gives


It is evident from the approximate results given in (2.39) and (2.40) that there

could be a significant AUPN only at low UpN's and only if the interface trap energy level

is near the mid-gap. The DCIV lineshape in this case will be distorted and have a

diffusion-limited flat top. An interface-recombination-limited threshold VpN can be

defined by equating the asymptotic current equations limited by recombination (2.36)

and diffusion (2.37). Using the numerical values just listed, this gives

UpN-th = 2[6.908 cosh(UT*)] (2.41)

The diffusion current JD given by (2.36) for constant NAA can be generalized to

graded and retrograded profiles, NAA(x), by replacing the pre-exponential factor with

the exact integral given by f [NAA(x)/DB(x)n?(x)]dx which is integrated over the quasi-

neutral base, x=0 to x=XB. This is the well-known Gummel Number.

2.5 Application Examples

DCIV measurements have been performed extensively since its revival in 1995

[5] on silicon micron and submicron MOSTs manufactured by 1988-1998 technologies

with channel aspect ratios of W/L=100lm/100pjm to 10m/0.lgm and gate oxide

thicknesses from 30nm to Inm. This section will present the DCIV curves obtained on

both unstressed and hot-carrier-stressed MOSTs to illustrate the theoretical analyses of

the experiments. The data were from the large pMOSTs to minimize the 2-D effects.

The pMOSTs have W/L=50gm/50pm, 10.5nm gate oxide, NDD(interface) = 2x1017cm-3

and a graded n-well with p+buried bottom emitter.

The first examples are from unstressed pMOSTs where the IB-VGB peak

originates from the residue interface traps of the manufacturing processing steps. Figure

2.7(a) shows a family of normalized experimental BE-DCIV curves in solid lines and

theoretical curves in dashed lines based on EIr.=228meV and Nrr=7.8xl09cm-2. These

numerical values were obtained from a 2-parameter least-squares-fit [33] of the IB-peak

vs VpN shown in Fig. 2.7(b) which shall be coined as the DCIV Peak-Plot (P-Plot). The

P-plot fits very well only the discrete-trap-level theory while the data deviate

substantially from the theory computed from constant or U-shaped interface trap energy

level distributions. Diffusion current was not included in this fit. Fig.7(a) indicates a

good theoretical account of the lineshape at the strong inversion side while the

experimental halfwidth is wider on the flatband side. Several sources contribute to the

difference including: diffusion limitation at these low VpN values which would broaden

the linewidth, larger surface impurity concentration than assumed from C-V

measurements and graded vertical doping profiles.

Figure 2.8 shows the differences among the DE-, SE-, TE- and BE-DCIV curves

measured at VpN=400mV on the same unstressed pMOST. The three gated-emitter

configurations (DE, SE and TE) all show one narrow peak indicating low NIT

concentrations inside the gated JSCR. Overlap of SE and DE curves shows good

source/drain symmetry. The different VGB-pak locations between TE and DE or TE and

SE come from the lateral variation of the minority carrier (holes) concentration at the





1 r




0.1 0.2 0.3 0.4 0.5 0.6 0.7
Forward bias /(1V)

Gate Voltage




Fig. 2.7 Experimental BE-DCIV's and Peak-Plots on unstressed 50/50 pMOST
compared with theories. Parameter values are: ETI*=228meV and
NIT=7.8x109cm-2 from least-squares-fit to the discrete-level theory using
cns=cps=10-8cm3/s (assumed), ni=10locm-3, and from Cg-VGB data,
NAA(x=0)=2xl017cm-3, and Xox=10.5nm. (a) Peak Plots (B-peak vs VPN) of
experimental data (points) and theory from three assumed DOS's of
interface traps: a: Discrete-level given above, b: constant DOS over EG-Si
with DIT = 7.1x109/cm2-eV, and c: U-shaped DIT =
2.5x109cosh(ETl/200meV)/cm2-eV. (b) Lineshape comparison with one-
discrete-level theory.

I I 1 I I I a '

- a) BbV -

1- -

,, Theory with NIT DOS
/ a Discrete (fitted)
b,"" / b- Constant
a c --..- U-shape
1 1 1 I I i I i



a- DE i
) b ---- SE
S-c-- TE
E d BE

-- \i \

-0.5 0 0.5 1.0
Gate Voltage /(1V)

Fig. 2.8 Experimental lineshape comparison of DCIV at VpN=400mV from four
different measurement configurations (DE, SE, TE, and BE) on the 50/50

interface, Ps(y), from Ps(0)=0 at the shorted source junction to Ps(L)=Pss[exp(UPN)-l]

at the forward-biased drain junction in the DE-DCIV bias configurations or vise versa in

the SE-DCIV bias configuration. Ps(y) is further reduced due to the finite diffusion

length towards the MCR from the injection edge of the drain or/and source junction.

These give a smaller effective channel interface recombination area and also a smaller

effective VPN which would shift the peak location towards the -VGB side as indicated by

(2.9). Figure 2.8 shows that the IB-VGB linewidth of the ungated emitter (BE) is almost

doubled in comparison with those of the gated emitter (SE, DE and TE), which is due to

carrier injection against a diffusion barrier from graded BQNR. These effects on the

lineshape from junction and geometrical edge effects and impurity concentration profile,

indeed, provide flexible variables that can be leveraged in the monitor application of the

DCIV methodology for optimization of transistor designs and fabrication processes.

For the second sets of application examples, the DCIV theory is used to evaluate

the interface traps generated during the substrate-hot-carrier (SHC) and channel-hot-

carrier (CHC) stresses of the same 50/50 pMOSTs used in the preceding unstressed

examples. During the SHC stress, the p+buried/n-well junction is forward biased to

inject a high concentration of holes into the strongly inverted hole surface channel

which is reverse biased by a high reverse voltage applied simultaneously to the drain

and source p+/n-well junctions. This high reverse voltage accelerates the injected holes

to a kinetic energy greater than the Si:H interfacial bond energy (3.1eV) in order to

release the hydrogen and generate the silicon dangle bonds, Si., which are the interface

traps. Reasonably good lateral uniformity of interface trap generation was expected

from using low-enough VBE and strong-enough inversion VGB to minimize the lateral

drop of the vertical acceleration potential due to channel ohmic resistance. Figure 2.9(a)

shows the IB-VGB DCIV lineshapes which indicates a larger experimental linewidth

suggesting diffusion limitation. Figure 2.9(b) shows the DCIV Peak-Plot, IB-peak-VPN,

which includes also the unstressed data that coincide the stressed data for VpN<400mV

further indicating diffusion limitation. The stress-generated interface traps are still quite

discrete as indicated by the good fit to the discrete-energy-level model at high VpN's.

The least-squares-fit (LSF) stressed-generated trap energy level, ETI- = 280meV, should

shift towards midgap when diffusion is taken into account.

A second example of stress-generated interface traps was obtained using the

channel-hot-carrier stress on the same 50/50 pMOST whose DCIV at VpN=350mV and

P-Plot are shown in Fig. 2.10. The unstressed peak near the intrinsic gate voltage

(VBG=+0.IV) does not grow at all which is consistent with its MCR location where

there are few if any hot carriers. The growing post-stress peak is broad (FWHM 2V)

and in the accumulation range (VGB=+1.8V). It has an n--2 over many decades in the

P-Plot (inset of Fig.8) which suggests that the interface traps are mainly generated in the

drain JSCR, as anticipated by the JSCR-DCIV theory just described, and the CHC stress

theory [42] where the channel hot holes and the secondary hot electrons are generated in

the drain junction space charge region in the pMOST during stress.





z _


0.4 0.5 0.6 0.7 0.8
Bias /(1V)


Fig. 2.9 Experimental and theoretical LSFitted BE-DCIV's from substrate-hot-
carrier (hole) stressed 50/50 pMOST. (a) The Peak-Plots IB-peak vs VpN
showing a discrete-energy-level interface trap at ETI.=280mV and
NIT=5x10l'cm-2. (b) Lineshape comparison with the discrete-level theory.
Other parameter values are the same as those of Fig. 2.7.

0.1 0.2 0.3


0 0.5

Gate Voltage /(1V)

250 _"'l""'" ""111 11 "'1111 1 -' '
200 -
C A n=2
150 n
-A _
1 10-141
0 0.2 0.4
m 100- Forward Bias

50 CHH stress
i \ ~
-I -- ..... _

0 0.LL L Hl I -1 --i- i ri 1 I IIII 1
-1 0 1 2 3

Gate Voltage /(1V)

Experimental DE-DCIV's taken on a channel-hot-carrier (hole) stressed
pMOST, with the Peak-Plot of the stressed-generated AIB.peak in the inset.
CHC (CHH) stress condition: VSB=OV, VDB=-7.0V, VGB=-l.OV and
t=1000 sec.

Fig. 2.10

2.6 Summary

Theory and experiments on gate-voltage modulation of the recombination rate at

the interfacial electronic traps are quantitatively correlated in prestress and two

poststress (channel and substrate hot carrier stresses) DCIV applications. The wider

experimental linewidths could be an indication of diffusion limitation in the low forward

bias range, and from 2-dimensional effects at high forward bias range due to lateral

variations of the interface minority carrier concentration along the gated conduction

channel. The examples illustrate the identification of discrete interface trap energy

levels and the near midgap energy level positions.


3.1 Introduction

The DC basewell terminal (or pad) current, Ig, modulated by the applied

gate/base DC voltage, VGB, in MOS transistors was a method recently reactivated to

monitor electric-field-stress generated interface traps as a transistor reliability monitor

[5] and to serve as a pre-stress diagnostic monitor for transistor design and processing

[8]. The VGB-modulated Ig arises from recombination of the injected minority carriers

by a forward-biased p/n junction (Drain/Base, Source/Base, or Substrate/Basewell) with

the majority carriers in the basewell, at the SiO2/Si interface traps under the gate oxide.

Electron-hole recombination can occur at interface traps under the gate oxide in three

regions [3,4]: (1) the mid-channel region MCR (2) the drain and source junction space-

charge regions D-JSCR and S-JSCR, and (3) drain and source lowly-doped extension

regions D-LDER and S-LDER. A detailed theoretical analysis was presented in chapter

2 for the MCR and JSCRs. Some of our recent application demonstrations [8,33,34]

focused on interface traps NIT in the MCR. However, recombination at interface traps

in the other two regions, JSCR and LDERs, becomes increasingly important in

unstressed transistors as the channel length is scaled down and it is well-known that

recombination in JSCR dominates in stressed transistors [8,43,44]

regardless of the channel length [8,33]. It was anticipated [8] and analytically

demonstrated in the previous chapter that the IB-VGB lineshape and its VpN

dependencies are affected by two lateral variations: the interface traps, NIT(y), [8] and

the interface concentration of the injected minority carriers N(x=0,y) [8] in n-channel

MOSTs or P(x=0,y) in p-channel MOSTs. This spatial dependency was analytically

shown in chapter 3 to be substantial in the JSCR due to the rapid spatial variation of the

carrier concentrations in the JSCR. We will now describe the procedures for obtaining

the NIT(y) distribution and some transistor design parameters (gate oxide thicknesses

and dopant surface concentration). The theoretical analyses and computed illustrations

are given in section 3.2. Analyses of the experimental data to give transistor design

parameters in the MCR and NIT(y) profiles in both the JSCR and MCR are presented in

sections 3.3, 3.4 and 3.5 respectively. A summary is given in section 3.6.

3.2 Theoretical Analysis

The analytical formulas were derived and described in chapter 3 for the

Shockley-Read-Hall (SRH) steady-state recombination rate Rss at interface traps in the

MCR and JSCRs. There is an additional VGB-dependence of Rss from NIT in the

LDERs, which will be included in this chapter. The present analyses for the LDER

follow the steps for the MCR with two noticeable differences: (i) the nearly zero

flatband voltage in the LDERs due to the same dopant type and nearly the same high

dopant impurity concentrations in the Si-gate and drain and source LDERs according to

the traditional designs of digital CMOS transistors and (ii) the gate-to-drain voltage is

now VGD = VGB-VDB = VGBIVPN (+ for nMOST and for pMOST) which gives Ig the

additional VPN dependency, both are leverageable for NIT characterization described as


As illustrated by the computed potential variation curves in Fig.l, the (VpN)

forward-bias-injected minority carriers reduce the interfacial potential barrier height on

both the MCR-side (lower curves) and the LDER-side (upper curves) of the JSCR

shown in Fig. 3.1(a), and the total potential barrier height through the JSCR shown in

Fig. 3.1(b). This VpN dependency significantly affects the DCIV or IB-VGB lineshape

from NIT's located in the JSCR. [The interfacial electric potential, V(x,y) at the SiO2/Si

interface x=0, has been denoted by the two traditional and two recent engineering

notations: J(x=0,y) = Vs(y) V,(x=0,y) = VIs(y). The subscript I for intrinsic Fermi

potential will be dropped for arbitrariness of the reference electric potential and for

notation compactness using kT/q normalization: Us(y) = (q/kT)Vis(y).] The curves in

Figs. 3.1(a) and (b) were computed using the carrier depletion as the zeroth

approximation in the JSCR [45] but they do include, in the MCR and the LDERs, the

injected carrier concentration from the forward bias (VpN) just described, and also the

Fermi-Dirac carrier distribution and impurity deionization for high impurity surface or

interface concentrations [46]. The upper part of Fig. 3.1(a) gives the total lateral drop of

the interfacial potential in the LDER with 10-19cm 3. The potential-drop is about 100

times smaller than that in the MCR with 1017cm-3 shown in the lower part of Fig. 3.1(a)

as expected from the concentration ratio. Figure 3.1(b) shows that at VGB=-IV (about

flatband in the MCR), the p/n junction barrier height, VB, at the interface is reduced



> -

~ -0.5 -

> -1.0 1 I __I_,_I
-3 -2 -1 0 1
VGB /(1 V) (a)
0.05 -' 1 1 1
-{ p- Base ) -( JSCR )----- n+Drain }-
> 1-
S ~- VN=OmV
0 --- "
VPN=800mV .80mV
I------------ -

>----- B-JSCR --------

-0.5 D-JSCR -

> -VpN=OmV
-1.0 I 1 I 1
120 80 40 0 -40
y/(1 nm) (b)

Fig. 3.1 Gate-Basewell voltage (VGB) dependence of the potential variation through
the space-charge layer at the SiO2/Si interface of the drain or source n+/p-
Base junction covered with a n+Si gate in the carrier-depletion and thick-
oxide limits with spatially constant dopant impurity concentrations of
NGG=5x1019cm-3, NDD= 1019cm-3, and PBB=11017cm-3, and oxide
thickness of Xox=3.0nm. (a) The potential drop in the drain and basewell
sides of the junction space-charge region, VD-JSCR and VBJSCR for forward
applied dc biases of VpN=OmV to 800mV. (b) The potential variation along
the SiO2/Si interface for VpN=OmV and 800mV.

n+Drain: 1x1019cm-3
VpN=OmV p-Base: 1x1017cm-3
80 Xox:3.0nm -

C 60-


20 800mV

-3 -2 -1 0 1
VGB/(1V) (a)
100 1.0
80- 0.8 E
E c

S60- -/ 0.6
m 40 -0.4

>_ 20 0V -0.2 >

0------------- 0
-3 -2 -1 0 1
VGB/(1V) (b)

Fig. 3.2 The length of junction space-charge region as a function of the applied dc
gate voltage, VGB, for applied junction dc biases VpN=OmV to 800mV. (a)
Total length, YJSCR. (b) Length on the basewell and drain (or source) sides,
YJSCR-Base and YJSRC-Drain. Transistor parameters are the same as those
used in Fig. 3.1.

nearly 600mV by the injected carriers, from VB=720mV at VpN=OmV to VB=120mV at

VpN=800mV. The geometrical effect, shortening of the length of the JSCR by VpN in

Fig. 3.1(b), should also be noted which is leveraged in NIT profiling. This is further

illustrated in Fig. 3.2(a) for the total length, YJSCR, and in Fig. 3.2(b) respectively for

YJSCR's component on the Channel-side (left Y-axis) and the LDER- (or Drain- and

Source-) sides (right Y-axis) whose curves are nearly the same with ratio 100 from the

dopant impurity concentration ratio at the interface, 1019/1017=100.

The effects of this lateral interfacial potential variation with forward bias are

shown in Figs. 3.3(a) and 3.3(b) in which the normalized SRH recombination rate,

Rss/Rsspk, or normalized basewell-pad current, IB/IBpk, at a midgap interface trap in the

JSCR are computed as a function of VGB. As described in the following two

paragraphs, the IB-VGB lineshape provides the basis for calculating the spatial

dependence of the interface trap density, NIT(y) from experimental DCIV IB-VGB


In Fig. 3.3(a), the effects of spatial variation of NIT(y) in the JSCR on the IB-VGB

characteristics (at VpN=200mV) are illustrated for the seven NIT(y) distributions:

NIT(y)=NITo=constant in the (i) MCR, (ii) Drain (or Source) LDER, and (iii) Drain (or

Source) JSCR; and the four discrete NIT(y)=NIT18(y-YT) distributions located at (iv)-

(vii) y=YT=10, 20, 30 and 40nm from the metallurgical p/n junction boundary. There

are several obvious features in Fig. 3.3(a) useful for NIT(y) characterization from

experimental data. First consider the six distributions except the constant-NIT in the

Drain- or Source-JSCR, (iii). (1) The VGBpk moves from inversion to depletion-

1.2 1 1 1 I I I I
JSCR:YT(nm) =
10 20 30 4''
1.0 LDER= 2 4 5 6 31=MCR
._ S-LDER -

0.8 i

E 0.6 / _
.4- cons
a) 0.4 IT-
0.2 ETeV ,
VpN=200mV /
0 / f I
-2.5 -2.0 -1.5 -1.0 -0.5 0
VGB /(1V) (a)
1.2 I ( ooI I

( NIT=cnst. VpN(mV)= o< ~
1.0 3


E_ 0.6
uc 0.4


-2.5 -2.0 -1.5 -1.0 -0.5 0

VGB/(1 V) (b)

Fig.3 Effects of spatial variation of interface trap concentration (NIT) and forward
bias voltage (VpN) on the normalized DCIV lineshape (IB-Normalize or
Rss-Normalize vs VGB) from an Si-midgap (ETI,=OmV) interface trap located
in the drain and source lowly-doped-extension regions (D-LDER and S-
LDER), the junction space-charge-region (JSCR), and the mid-channel-
region (MCR). (a) Three spatially constant NIT's: curvel=MCR,
curve2=D-LDER and S-LDER, and curve3=JSCR, and four discrete (delta-
function) NIT'S located at YT=10, 20, 30, and 40nm (curve4,5,6,7) from the
p/n impurity concentration boundary, at a forward-bias of VpN=200mV. (b)
Forward-bias dependence (VpN=OmV to 800mV) for the constant NIT in the

flatband-accumulation as the discrete NIT(y=YT) moves from the MCR edge towards the

p/n boundary y=0. (2) The IB-VGB lineshape from the constant-NIT in the MCR and D-

LDER (or S-LDER) and from the four spatially discrete NIT(y) all are sharply peaked

Gaussian-like with increasing width as YT moves from the MCR towards the Drain (or

Source) LDER. These two lineshape properties provide the basis for its utility as a

delta-function probe for the lateral variation of NIT(y).

For the spatially constant Njr(y)=NITo in the JSCR, (iii), the following effects on

the lineshape and position are noted. From the VpN=200mV curve in Fig. 3.3(a): (31)

the VGBpk is near that of the NIT located in the MCR (i), and (32) the upper part of the

lineshape is similar to that of MCR-NIT (i) also. The curves in Fig. 3.3(b) shows the

effect of increasing VpN or injected minority carrier concentration: (33) VGBpk shifts

toward flatband-accumulation (negative VGB in mostT, (34) the lineshape broadens,

(35) a substantial plateau, about 25% for VpN-O0, diminishes, (36) the upper 20% of the

IB-VGB lineshape is nearly Gaussian with a slightly skew on the accumulation side, and

(37) the entire half of the IB-VGB lineshape on the inversion-side (positive VGB in

nMOST) is nearly Gaussian-like.

Figures 3.4 and 3.5 provide theoretical estimates of the confidence level or the

accuracy of using the delta-function approach to analyze the DCIV IB-VGB data for

extracting slowly and rapidly varying NIT(y) profiles respectively. The assumed

(continuous lines) and the extracted (crosses) profiles are shown in Figs. 3.4(a) and

3.5(a), respectively for the exponential profile, exp(-y/3nm), and the Gaussian profiles,

exp[-(y-YT)2/I_] located at four distances YT=10,20,30,40nm from the p/n boundary.


E 0.6


20 40
y /(1 nm)



lU (

(a) 60

0 20 40 60
y /(nm) (b)



I- ( "c-J/

IB-I (1011cm-2) -,
I-- -----------


-1.5 -1.0
VGB/(1 V)


Fig. 3.4 Illustration of the use of the DCIV line-shape for profile extrapolation of the
mid-gap interface trap concentration, NIT(y), for an exponential profile
located inside the JSCR, at VPN=200mV. Transistor parameters are the
same as those of Fig. 3.1. (a) Assumed and extrapolated profiles. (b)
Fractional error. (c) Current integrals of the profile-extrapolation






+ Extracted
C'J 10
I E 20
E 0.6 -o
c + 40 =YT(nm)

c. 0.4- + + +
+ ++ +

0.2 +

0 +
0 20 40 60
0 20y /(1 nm)40 (a) 60
n+Drain -- --- -'- -- 1 p-Base
Slo- .nm)=
263 -----Ynm)=
30 20 46
0 0 20 y/(lnm)40 (b) 60

30 1 1 1 1 1 1 1 1 1
-VpN=200mV YT= -
-ET=O 40nm-
-20 Onm 20nm
E 20 10nm
BL -

c 10-

SB-1 __ -
-2.0 -1.5 -1.0 -0.5
VGB /(1V) (c)

Fig. 3.5 Illustration of the use of the DCIV line-shape for profile extrapolation of the
mid-gap interface trap concentration, NIT(y), for four Gaussian profiles
located at YT=10, 20, 30 and 40nm from the n+D/p-B boundary inside of
the JSCR at VpN=200mV. Transistor parameters are the same as those of
Fig. 3.1. (a) Assumed and extrapolated profiles. (b) Fractional errors. (c)
Current integrals of the profile-extrapolation algorithm.

The difference or fractional error of the extracted profiles are shown in Figs. 3.4(b) and

3.5(b), indicating excellent accuracy (<0.07 or 7%) for the slowly varying exponential

NIT in Fig. 3.4(b), but rather large differences for the rapidly varying Gaussian NIT in

Fig. 3.5(b), the latter as expected since RSSI(Y,VGB) is far from a delta-function,

nevertheless, Fig. 3.5(a) shows that extrapolated profile are peaked and Gaussian-like

with a peak location near the true physical location and with a linewidth about 1.5-times

wider which increases -2-times wider as the peak moves towards the base-side or

channel-side of the JSCR. Thus, theoretical corrections could be made to correct part of

such a systematic difference.

The Nrr(y) profile extraction procedure, used to give Figs. 3.4(a), 3.4(b), 3.5(a)

and 3.5(b), starts with the delta-approximation for evaluating the general formula (2.21)

IB-JSCR (VGB) = NIT (y) RSS1(y, VGB) dy (3.1)

where W is the channel width. The integrand RSSI(Y,VGB) is the SRH recombination

rate per unit interface trap. Its lineshape in y and VGB are both bell-shaped and rather

sharp, resulting in a simple but accurate mapping of the experimental IB-VGB to the

Nrr(y)-y profile. The bellshape characteristics are illustrated by the following examples.

The maximum of Rssi(y)-y at a given VGB [See Fig. 3.6(a).] occurs at the position

y=YM(VGB) which was given by Eq. (2.4):

Us*j = U(YM)-(Up+UN)/2 + loge(cns/cps)1/2 = 0 (3.2)

Up and UN are the hole and electron quasi-Fermi potentials, respectively. Using the

U(y) from the depletion approximation and the abrupt dopant impurity concentration



0 10 20

30 40
y/(1 nm)

50 60

-0.5 I



-2.0 I I i
0 10 20

30 40 50

Fig. 3.6 Gate-voltage dependence of the spatial variation of the steady-state
recombination rate at VpN=200mV. Other parameters are the same as those
of Fig. 3.1. (a) Gate voltage dependence of Rssi vs y. (b) Location, YM, of
the peak Rss1 vs gate voltage.


model, YM has the following dependence on VGB where Usx and USE are total surface

potential changes in the x-direction normal to the SiO2/Si interface in the MCR

(Basewell) and the D-LDER or S-LDER (Emitters) respectively.

YM(VGB) = rLD [UBI-USX-UPN+USE 'U-UpN/2-UsX-loge (Cn/Cps)1/2]

LD is the Debye length, UBI the built-in potential of the n+D/p-B junction. This

equation maps a gate voltage to a spatial location in the JSCR in order to extract the

Nrr(y) profile from the experimental IB-VGB. Shown in Fig. 3.6(a) for the nMOST with

midgap trap at VpN=200mV, as VGB is swept from subthreshold-inversion (VGB=-0.6V)

to flatband-accumulation (VGB=-1.4V), the position of the RssI maximum, YM, moves

from the MCR-edge of the JSCR (YM=46nm) towards the metallurgical p/n boundary or

the LDER-edge of the JSCR (YM=9nm -+ 0). This shift is computed from (3.3) and

shown in Fig. 3.6(b) indicating almost a linear dependence of 30nm/V in the flatband-

accumulation range (VGB<-0.94V). Another feature is the narrowing of the RIls(y)

linewidth towards flatband-accumulation shown in Fig. 3.6(b) which sharpens the probe

for the NIT(y) profile. The sharp bellshaped Rssl(y) can be approximated by a delta-

function to evaluate the Ig integral, (3.1):

IB-JSCR(VGB) = WNIT(M) RSS (yVGB)dy = NIT(YM)*IB-_(VGB) (3.4)

where IB-JSCR is the experimental base-terminal current or theoretically generated

current using (3.1). The interface trap profiling formula in the JSCR is then given by

NIT(YM) = IB-JSCR(VGB)/IB-1 (VGB) (3.5)

where IB-I(VGB) defined by (3.4) is the recombination current from a spatially constant

interface trap concentration inside the JSCR normalized to NI(0
To estimate the error in the extracted NIT profile using the delta-function

approximation in (3.4), an assumed profile of NIT in the JSCR is used to compute

IBg-(VGB) from (3.1) and IB-I(VGB) from (3.4). These were given in Fig. 3.4(c) for the

exponential profile and Fig. 3.5(c) for the four Gaussian profiles. The ratio of these two

curves then give the extracted NIT profiles in Figs. 3.4(a) and 3.5(a) and the

corresponding difference errors in Figs. 3.4(b) and 3.5(b). Practical applications using

this procedure to extract pre-stress and post-stress NIT profiles are given in section 3.4.

Figures 3.7-3.9 give additional illustrations of the dependencies of the DCIV Ig-

VGB characteristics on the forward-bias VpN or injected minority carrier concentration.

These VpN dependencies can be used to determine additional properties of the interface

traps. The trap-spatial-location effects on the VGBpk-VpN is shown in Fig. 3.7 for the

NIT distributions given in Fig. 3.3(a) which indicate that increasing forward bias, VpN,

or minority carrier concentration would decrease VGBpk towards flatband-accumulation

if NIT(y) is constant in the JSCR and MCR, or localized near MCR (YT>30nm) while

increase VGBpk towards subthreshold and inversion if Nrr(y) is localized (delta-function)

in the JSCR (YT<30nm) or in the LDER.

The trap-energy-location effects on the shape of the Rss or IB vs VGB curve is

shown in Fig. 3.8(a) for a spatially constant NIT in the JSCR and four trap energy levels,

ETI=O.OV (midgap), 0.1V, 0.2V and 0.3V. The shallower traps (ETI=0.2V, 0.3V) have a

broader RSS-VGB or IB-VGB and steeper and higher plateau in the flatband-accumulation


S NIT(y)
-0.5 constant- MCR
^ y=YT(nm)= 40---- S -
T_ ~-~-- -- -- -- -- -

-1 .0 20----3 jSC

>_ 10 ....s A----
constant Source
constant or Drain LDER

-2.0 I I 1 1 1 1
-0.2 0 0.2 0.4 0.6 0.8

VPN /(1V)

Fig. 3.7 Forward-bias (VpN) dependence of the VGB at IBpk for the seven NIT(y)
distributions shown in Fig.3.

1.2 1
NIT = constant in JSCR
1.0 VpN=200mV

S0.8 / _
N / 1
E ETI=0.3eyV-'
o 0.6- -
Ch ."-"0.2ey.V / i -
S00.4 -.1eI
0.2- /~ \ \ -
0 i
-2.0 -1.5 -1.0 -0.5 0
VGB /(1 V) (a)
1.2 1 1 1 1 ,1 ,1
Discrete JSCR-NIT
1.0 -Y=20nm -..

0 ETI=0.3eV' /
S0.8 / I \ -
S/' 0.2/ ,
0.6- / ,
z i
C 0.
(P 0.4 -
II \

/ // E= \
0.2 ,/ E//

0-- -'r L I I I I Ik I L I
-2.0 -1.5 -1.0 -0.5 0
VGB/(1 V) (b)

Fig. 3.8 Effects of energy level of the interface trap in the JSCR on the DCIV
lineshape at VpN=200mV. Other transistor parameters are the same as those
in Fig. 3.1. (a) Constant NIT in the JSCR. (b) Discrete NIT at YT=20nm
from the n+D/p-B boundary.

range (VGB<-lV in this nMOST example). Figure 3.8(b) is for localized NIT in the

JSCR which shows broadened IB-VGB when the energy level of the interface trap moves

from the midgap EIT = 0 towards one of the band edge, EIT = 0.3eV.

The trap-energy-location effects on the shape and the normalized reciprocal

slope of the log(IBpk) vs VpN characteristics are shown in Figs. 3.9(a) and 3.9(b). (We

called this the Peak Plot or PP in contrast to the Gummel Plot and the Shockley Plots.)

This PP is probably the most powerful result of the DCIV methodology for rapid

interface trap energy level determination because the VpN-dependence of the peak Ig

current is a function of only the effective interface trap energy level, ETI- = ETI +

(kT)loge(ns/cps)1/2. It is completely independent of the surface energy band bending

and other material properties, such as surface impurity concentrations, oxide thickness,

and carrier capture rates. Although ETI* contains the carrier capture rate ratio it would

only give an uncertainty in the extracted ETI of (kT/q)loge(cns/Cps )12 ~ 1.l(kT/q) ~

30mV since the carrier capture ratio is usually in the range of 0.1 to 10 for neutral trap

potential wells of the intrinsic and silicon-dangling-bond interface traps observed

experimentally thus far. Figure 3.9(a) gives the IBpk-VPN plots for four ETI(eV) (0, 0.1,

0.2, 0.3) with the seven spatial NIT distributions of Fig. 3.3(a). Figure 3.9(b) gives the

reciprocal slope defined by

exp(UpN/n) = [exp(UpN) -]/[exp(UpN/2)+cosh(UTI.) ] (3.6)

Six of the NIT distributions have identical PP's (unbroken lines) in Fig. 3.9(a) which are

the two constant-NIT's in the MCR and LDERs (Drain and Source), and the four delta-

function-NIT's in the JSCR. Their n-factor, shown Fig. 3.9(b), approach the ideal

CM 1U--


E O / 1

S '- N-T(cm-'2)
---- KBpk-SCR 1.0x1011
S- JBpk-MCR 2.5x10
10-20 I _,_I ___,I_,
0 0.2 0.4 0.6 0.8 1.0
VpN /(1V) (a)


C 1.5 0-1 0.2,' 0.3,-

1.0 ---....- -------

0.5 F ---
0 0.2 0.4 0.6 0.8 1.0
VPN /(1V) (b)

Fig. 3.9 Effects of energy level of the interface trap in the JSCR and MCR on the
peak recombination current vs forward bias. Other transistor parameters are
the same as those in Fig. 3.1. (a)IBpk and KBpk vs VpN. (b) Reciprocal
slope or voltage-swing vs VPN.

Shockley value of n=l at low VpN for the three non-midgap traps (ETI* = 0.1eV, 0.2eV,

0.3eV), increasing to n=2 at high VpN or Ps=Ns >> ni in a small range of VPN about

200mV (10% to 90% rise). It degenerates to n=2.0 at all VpN for the midgap trap

ET*.=0. The seventh, constant-NIT in the JSCR, has a slightly higher PP (broken line) in

the lower VpN range and a higher n than the other six distributions. For this case, Fig.

3.9(b) also illustrates the contribution to IBpk from the NIT at the channel or MCR-edge

of the JSCR. This geometric effect from YJSCR(VpN) increases n above 2 at low VpN for

the midgap trap as indicated by the dotted line in Fig. 3.9(b). To remove this geometric

effect, the YJSCR(VPN) dependence can be taken out approximately by normalizing the

numerically integrated IBpk integral to YJScR(VPN) before using (3.6) to compute n.

Such a procedure is desired in this theoretical illustration since the reciprocal slope is

defined for the purpose of quickly assess the properties of the interface traps from the

experimental VpN dependence of IBpk used in the initial analyses of the gate-controlled

base-terminal current [5,8] and the 1957 SNS theory for the recombination at traps in

the bulk JSCR [40].

The insensitivity on the spatial distribution of NIT of the six distributions first

considered above allows an accurate determination of the effective energy level of the

interface traps, ETr., and the thermal activation energy of the Ig which is an important

component of the standby current in CMOS operations. In practice, the interface traps

have always been observed near the midgap (ErTI=OeV). Some extracted shallow-trap

energy levels in previous analyses of data [8,33,34] originated from emitter-injection-

limited and diffusion-limited Ig current through a thick basewell layer or long channels

rather than from shallow interface traps.

3.3 Extraction of MOST Device Parameters

One of the applications of the DCIV base-recombination-current methodology

was its use as the diagnosis monitor for transistor design and fabrication processes [8].

In this section, a demonstration is given on the extraction of the surface concentration of

the base dopant impurities, Nxx, and the oxide thickness, Xox, and their comparisons

with the design values. A sample of the experimental Top-Emitter DCIV (TE-DCIV)

data matrix used in this demonstration is shown in Figs. 3.10(a) and (b) for two drawn

channel lengths, W/L=10gm/10pm and 10m/0.25pm, of pre-stressed pMOSTs on 8-

inch wafers fabricated by a 0.25pm technology. The other 4-sets in the 6-set matrix

were obtained for L = 5, 2, 0.8 and 0.4im drawn channel lengths. Similar application

results have been obtained for earlier (0.5p1m and 0.35im) and later (<0.18jim)

technologies [8].

The broke lines in Figs. 3.10(a) and (b) show the location of the (IBpk,VGBpk)

whose shift towards flatband-accumulation (positive VGB for pMOSTs) with increasing

drain and source forward-bias, VpN=0-700mV, is characteristic of an interface traps in

the MCR. The IB-VGB curve around the IBpk is least-squares-fitted (LSF) to a Gaussian

with a baseline,

IB = A1+ A2.exp-[(VGB-A3) /A4]2) (3.7)

0 0.5 1.0 1.5
VGB/(1 V) (a)

10-16 t- i i i i I i i i i I i i i i I i i i i I
-1.0 -0.5 0 0.5 1.0
VGB /(1 V)


Experimental TE-DCIV of pMOSTs from quarter-micron CMOS
technology for VpN=50mV to 700mV. Channel Width to Length aspect
ratio W/L of (a) 10pm/10gm. (b) 10pm/0.25pm.

Fig. 3.10

The four fitting parameters are the baseline AI=I0o, the peak current A2=IBpk, the peak

gate voltage A3=VGBpk and the linewidth A4. These four LSF parameters were obtained

for the 84 DCIV curves from pMOSTs with the six L at the fourteen VPN values (50,

100, ..., 650, 700mV). Figure 3.11 shows a typical LSF result for the L=10OIm and

0.25pm pMOST at VpN=400mV. The simple Gaussian cannot be used to fit the entire

gate voltage range because (i) the DCIV lineshape from NIT in MCR is skewed toward

the flatband-accumulation side of the peak (towards positive VGB in pMOSTs), with a

slightly wider half-width-half-maximum (HWHM) as previously shown chapter 3 and

the skew was also observed in the analytical solution shown in Fig. 3.3(b) for a constant

NIT in the JSCR and (ii) constant or peaked NIT in the JSCR contributes to additional IB

to that from NIT in the MCR thereby lineshape widening on the flatband-accumulation

side of the MCR peak. To circumvent these two asymmetry possibilities, only data

points from the inversion range and a small range on the accumulation side of the IBpk

are LS Fitted to (3.6). These are the open circles (L=10glm) and squares (

shown Fig. 3.11. The difference, IB-DATA 'B-FIT, are shown by the two lower-height

humps labeled JSCR in Fig. 3.11 which are from the NIT distributions in the drain and

source JSCRs or LDERs. The VGBpk (or A3) from the LSFs are plotted as a function of

VpN in Figs. 3.12(a) and 3.12(b) for the main IBpkl. The increasing VGBpk1 towards

flatband-accumulation with increasing VpN (pMOST) suggest that the IBpkl arises from

NIT located in the MCR. Thus, we proceeded to fit the (VGBpkl,VPN) datapoints to the

analytical formulas developed in chapter 3:

VGBpk = VFB + VSpk + 2.sign(VSpk) [V( |VSpk I -kT/q) ]1/2 (3.8)

1.2 1 1 I I -
/_ 1.0 pMOST -
ao A L=10m
N 0.8 p--
8 L=0.25pm ,
0. VpN=400mV JSCR NIT
E 0.6 ;. -

Z 0.4- -

0.2 -'0.2


-0.2 I1 ,I,
0 0.2 0.4 0.6 0.8
VGB /(1V)

Fig. 3.11 Least-squares-fits of the TE-DCIV curve of L=10 m and 0.25tgm pMOST at
VpN=400mV shown in Fig. 3.10. Decomposition into two components: one from
Nrr in the MCR and one from Nr in the JSCR.


0.8 1 1
0.7 o 0.25
o 0.40
o 0.80
S0.6 2.0
-- 2.0 3-para LSF
0 5 5.0 L=2gm
.0 +10 3-para. LSF
m VFB=0.960.06V -
S04 VF'=-0.470.03V
> 0.4 Vxx=486mV
2-para. LSF
0.3 VFB=0.964V(fixed)-
0 0.2 0.4 0.6 ) 0.8
VpN/(1V) (a)
0.8 1 1 ,
0.7 700 -- pN(mV) pMOST
.6- 00
0 500 -500
0.5- 400
o 400 400
S0.4 -300- 300
0.3 -150
0.2 1 1 i, l i 1 1 M,
10-1 1 10 102
LDRAWN /(1 m) (b)

Fig. 3.12 Experimental channel length dependence of VGBpk at IBpk at six L(ptm) from 0.25
to 10 for extrapolation of dopant impurity concentration at the oxide/silicon
interface. (a) VGBpk vs VPN with 3-parameter and 2-parameter least-squares-fit for
L=2.0m. (b) VGBpk vs L for VpN=50mV to 700mV.


VSpk = VF VPN/2 loge(cn/Cps)1/2 (3.9)

where VSpk is the Si substrate surface energy band bending at the peak, Vxx =

EsqNxx/2C02 where Cox = Eox/Xox, and VF = (kT/q)ologe(Nxx/ni) is the majority

carrier quasi-Fermi potential. The term (-kT/q) in (8) was dropped in (2.11) and is

retained here to provide better accuracy at high VpN's where VS-pk approaches zero or

the flatband condition as indicated by the decreased drain/base p/n junction barrier

height at the interface shown in Fig. 3.1. Combining (3.8) and (3.9) gives the 3-

parameter formula to fit the experimental VGBpk-VPN data:

VGBpk = AI+A2+(VPN/2)-2 (A3. [-A2-(VN/2)- (kT/q)] }1/2
(pMOST) (3.10)

The three LSF parameters are: A1 = VFB, A2 VF'= VF (kT/q)loge(cns/ps)1/2 and A3

= Vxx.

As an example of the LSF procedure we discuss the steps to fit the L=2grm data

to (10) which gives the solid line in Fig. 3.12(a). Only 9 (VpN=150mV-550mV) of the

14 datapoints (50-700mV) were used which are the unfilled triangles of the L=2gpm data

in Fig. 3.12(a), in order to limit the experimental VGBpk uncertainty to <0.5mV. For

VpN<100mV, VGBpk errors are larger than 0.5mV due to the -3fA noise in Ig. In the

VpN>600mV range, a more tedious fit to parametric equations instead of (3.10) is

needed due to the high injection level. The 9-point VGBpk data fits the 3-parameter

equation (3.10) very well, as shown visually in Fig. 3.12(a), with a Chi-Square of only

0.16%. The LSF value of VFB, VF' and Vxx are also listed in Fig. 3.12(a). The

VFB=0.96V is consistent with the designed polysilicon p+Gate for pMOST. The

electron/hole capture rate ratio cns/Cps is on the order of unity for near mid-gap traps,

therefore A2 = VF' = VF, which gives a surface concentration for the n-Basewell donor

(implanted As or P) impurity of Nxx=NDD=1.lxl018cm'3 which is consistent with the

nominal design value of ~10'8cm-3. The gate oxide thickness can then be determined

from A3=Vxx which gives Xox=2.4nm compared with the nominal design value of

2.5nm. The exponential dependence of Nxx on the Fermi potential VF gives a much

larger uncertainty in Xox and Nxx from the 6% uncertainty in VF. The error propagates

as follows:

NDD/NDD = AVF/(kT/q) (3.11)

AXox/Xox = (AVxx/Vxx + ANDD/NDD) /2 (3.12)

The data was taken at room temperature giving kT/q-25mV and using AVF=0.03V, the

percentage error in Nxx is 116% and Xox, 64% in this global 3-parameter fit. However,

if one of the three parameters (VFB, Nxx and Xox) is known from another independent

measurement or is fixed in a regional 2-parameter fit, then the two LSF parameters may

be determined more precisely. For example, we fixed the value of VFB at 0.964V which

was obtained by the 3-parameter fit, and then we made a 2-parameter LSF to (3.10).

The results are listed in Fig. 3.12(a) showing a large reduction of uncertainties in VF'

and Vxx. The percentage errors translated to Nxx and Xox are only 4% and 2%


To test the sensitivity of this 2-parameter extraction to the fixed value of VFB,

we vary VFB by 2% (-20mV). An alternative test would be to fix Xox from an

independent measurement, such as the C-V. The value of the device parameters (Nxx

and Xox) and their uncertainties, computed from the A's from the 2-parameter LSF with

VFB fixed, are summarized in the following table:

VFB(V) Nxx (1018cm-3) Xox(nm) X2 ()
0.945 0.760.02 2.870.06 0.15
0.964 1.130.04 2.400.05 0.15
0.984 1.680.06 2.000.05 0.15

The above table shows that the DCIV method can extract Nxx and Xox to an accuracy

of <10% provided that the flatband voltage is known to better than about (kT/q)/5 -

5mV. In the preceding analysis, assumption is made that cns=Cps so VF'=VF. In factory

application, a calibration transistor with known substrate doping concentration and

oxide thickness may be used to determine the cns/cps ratio, from which VF can be

extracted and the gate dopant impurity concentration can be computed from

VFG=VFB+VF where VFG denotes the Fermi-potential in the p+Gate. For IVFGI 2 0.50V,

accurate gate doping concentration can be obtained only by including impurity

deionization and Fermi-Dirac statistics. A similar fit to the IBpk2 can be made to give

the Pxx and Xox in the LDERs.

3.4 Profiling Interface Traps in Junction Space-Charge Regions

Examples are now given on profiling the interface traps in the drain and source

junction space-charge regions before and after channel-hot-carrier (CHC) stress. An

earlier profiling technique employed the transient charge-pump current using its

dependence on the drain reverse biased [47] which was shown to correlate with the

DCIV method [48]. A recent demonstration of the DCIV technique for profiling

interface traps near the drain junction measured the differential basewell-terminal

conductance by varying the drain reverse bias [43]. The differential DCIV method had a

higher sensitivity and resolution and could profile a large portion of the channel.

However, these methods are all limited to the region outside of the reverse-biased

JSCRs. The new approach, as described in section 3.2, gives the spatial NIT variation

inside the forward-biased drain or source JSCR directly from the ratio of the

experimental DCIV curve and the reference theoretical DCIV curve corresponding to a

constant NIT distribution. The rather good spatial resolution and accuracy of this new

approach were already illustrated by using analytical NIT(y) models in Figs. 3.4-3.5 and

described in section 3.2. Oxide charge built-up, which is usually associated with

interface trap generation during CHC stress under large drain reverse-bias [32,49],

changes the local flatband voltage which complicates data analysis. In this

demonstration, the CHE stress is kept at low drain voltages to prevent injection of

secondary hot holes over the SiO2/Si barrier (4.25eV for hot holes and 3.12eV for hot

electrons) [32].

The example to be given is the extraction of NIT(y) in a 0.35gm-nMOST testbed

for reliability assessment of low-K interconnect materials [6]. The specific nMOST in

this demonstration has a drawn aspect ratio of W/L = 50prm/0.4gm. The pre-stress and

post-stress DCIV data are plotted in Fig. 3.13(a) with the VGB-independent IB-baseline

subtracted. The sharp pre-stress peak, IBpk=0.6pA, at VGBpk=-0.5V is in the

subthreshold range and comes from recombination at the interface traps in the MCR.

This peak gate voltage is consistent with the nominal Xox=7.0nm and



< 60

t 40





4 -3 -2 -1 0 1
VGB 1(1 V) (a)
I I I .



Fig. 3.13 Demonstration for the extrapolation algorithm applied to channel-hot-
electron stress-generated interface-trap concentration profile of an nMOST
from a 0.35ntm low-k-interconnect CMOS technology. (a) Prestress TE-
DCIV and poststress DE-DCIV curves. (b) Prestress and poststress NIT(y)
profile extrapolations.


+ Stress: 3000sec
SVGS=1.5V, VDS=5
+ CHC stress(1 x) NIT(y) extracted from
x p-Base=1 x10'7cm-3
S Prestress n+Drain=2x1019cm-3
- .,^ (200x) Xox=7.0nm

S I ++I+ + + I+


Pxx(boron)= 107cm-3. The broad pre-stress structure (~0.45pA) shown in Fig. 3.13(a)

in the range VGB<-2.5V (flatband-accumulation range for this nMOST) is from

recombination at NIT in the JSCR close to the metallurgical n+Drain/p-Basewell

boundary y=0 at the SiO2/Si interface x=0. This nMOST was then CHE stressed for

3000 seconds at VGB=+1.5V, VDB=+5.0V and VSB=OV. No positive oxide charging

was observed under this stress condition since the kinetic energy of the hot carriers is

only qVGB-q(VDB-VTH) = 5.0eV-(1.5eV-0.5eV) = 4.0eV, which is insufficient for the

secondary hot holes to surmount the 4.25eV hole barrier at Si/SiO2 interface [49].

Figure 3.13(a) shows that after the CHE stress, the broad pre-stress structure

(VGB<-2.5V) grew almost 200 times in amplitude (to 85pA) and became even broader

(VGB<-IV). This indicates a substantial increase of interface trap density in the JSCR.

A small post-stress hump can be observed around VGB=-0.5V which was the peak gate

voltage due to the pre-stress NIT in the MCR, indicating that some interface traps were

also generated in the MCR by the secondary hot holes generated by the hot electrons in

the JSCR, but at much smaller magnitude than that in the JSCR due to attenuation of the

hot hole density [32].

The pre- and post-stress IB-VGB data in Fig.3.13(a) can be analyzed using (3.5)

to give the lateral distribution of the interface trap density. The results are shown in Fig.

3.13(b). The pre-stress NIT was about 2x1010cm-2 from the p/n boundary, y=0, to

y=10nm into the JSCR on the basewell or channel side, and it dropped to a nearly

constant value of 5x109cm-2 beyond y=16nm. The post-stress NIT increased to

8x1012cm-2 within 18nm of the p/n boundary y=0 and dropped continuously towards

the MCR, and is below 1012cm-2 at y=40nm. The sharp rise near y=0 or the D-LDER in

approximation and the resolution limitation of steeply varying NIT(y), as indicated by

the theoretical models shown in Figs. 3.4 and 3.5. Thus, this example shows a 3nm

spatial resolution.

3.5 Interface Trap Profile in the Channel Region

A single DCIV curve would not provide sufficient information to profile the

interface traps in the MCR. Because the surface potential is essentially constant along

the entire length of the MCR, every interface trap along the MCR gives the same IB-VGB

dependency in the TE-DCIV measurement regardless of the NIT location. This is

readily seen by the general proof using (3.1) for the interface traps in the MCR which

reduces to the simple formula:

IB = B NIT(y)Wdy = B NITA(LEL) (3.13)

IBI=qRssi is the basewell recombination current from a single interface trap and NITA is

the number of interface traps in the MCR with the electrical channel length of LEL

between the edge of source and drain JSCRs. Thus, the spatial variation of NIT(y) is

given by

NIT(LEL)*W = (d/dLEL)NITA(LEL) = (d/dLEL) (IB/ IB) (3.14)

Since LEL is modulated by VPN, the forward bias applied to the Source/Basewell and

Drain/Basewell junctions, the VpN-dependent IBpk measured in MOSTs covering a range

of drawn channel length, L, can give the NIT(y) profile near the basewell edge of the two

JSCR's. In addition to TE-DCIV measurement, the SE-DCIV and DE-DCIV

measurements would provide further information regarding to the symmetry of the NIT

distribution by utilizing the additional variable, i.e., the nearly linear variation of the

injected minority carrier interfacial concentration from the emitter, such as the DE, to

the collector, such as the zero-biased Source Collector or SC in the DE-DCIV bias

configuration. In DE-DCIV, interface traps near the drain-emitter (DE) dominate the IB

while in SE-DCIV, those near the SE dominate. Thus, large asymmetry or differences

between DE-DCIV and SE-DCIV would be expected in the stressed transistors and in

pre-stressed transistors with designed drain-source asymmetries such as the FLASH

memory transistor.

The above differential method will be applied to the 0.25gm family of pMOSTs

with 6 drawn channel lengths whose typical TE-DCIV data at 15-VpN's (OmV to 700mV

with 50mV steps) were shown in Fig. 3.10(a) for L=10gtm and Fig.10(b) for L=0.25gm.

The IBpk's were obtained from the LSF to the Gaussian as described by eq. (3.7) with

uncertainties of 4-8%. The ratio IBpk(L)/IBpk(L=10gm) versus VPN for the five drawn

L's are plotted in Fig. 3.14(a) and the 4%-8% uncertainties of the datapoints are not

perceptible. The nearly VpN-independent value of this ratio is plotted as a function of L

in Fig. 3.14(b) for three VPN's (300, 400 and 500mV) showing two features: (i) a rise

proportional to L, suggesting an increasing dominance of the NIT in MCR due to

increasing length or recombination area, and (ii) an asymptotic constant value of 0.25

with decreasing L, suggesting a large contribution to Ig from NIT inside or near the edge

of the drain and source JSCRs due to its L-independence. The data points can be fitted


E 0.8

.. 0.6


-- 0.2


VpN /(1 V)

E _

01 -

J 10-1



I 1 1111111 I 1 1111111 I I I I 1II~


1 /

o 300
o 400
0 500


o0 /

-0- 0-

I I 11111

II I 1 11111

LDRAWN/(l jIm)


NIT profile extrapolation from channel length dependence of DCIV peak
current. (a) Normalized IBpk vs VPN for L(gm)=0.25 to 10. (b) Normalized
IBpk vs L at VpN=300, 400, and 500mV. Two components are evident, one
each from the MCR and JSCR.

5 o_-eo--- e- c e---

0.4 --
- 0.25




Fig. 3.14

I I I 1111 1 I I I I II

to the following geometric equation where L is Lithographic or drawn channel length

which will be taken as the distance between the metallurgical drain and source p/n

junction, LMCR is the length of the mid-channel region, YD(=YDJscR) and Ys(-YSJSCR)

are respectively the length of the drain and source junction-space-charge region at the

SiO2/Si interface which are equal, YD+Ys=2YD=YJ for conventional symmetrical

cMOS transistor design, and YMCR = L Yj, and where the J's are the areal density of

the recombination current in the MCR and the drain and source JSCR as indicated by

the subscripts which are to be shortened to two characters, MC, DJ, SJ.


Bpk (10) JMCR(10- Yj) + JDJSCR*YD + JSJSCR*YS

= y = (x + AI)/(10 + Ai) (3.15)

where x=L, Al = (JDJ*YD + JSJ*YS)/JMC YJ which reduces to Al = [(JDJ/JMC) 1]*

for identical drain and source. The data in Fig. 3.14(b) gives A1 = 3.250.13gm. For an

abrupt source and drain n+/p-B junction of -1018cm-3, YD=Ys=YJ/2=0.04gm giving

(JJSCR/JMCR)=NIT(SCR)/NIT(MCR) 40. This suggests that the NIT(y) profile rises

sharply in a short-distance (<0.04gm or <40nm) in the MCR near or inside the JSCR,

which was depicted by the theoretical example of a sharper exponential profile,

NIT(y)/NiT(0) = exp(-y/3nm) given in Fig. 3.4(a).

The geometric modeling from the L-dependence just presented that showed a

MCR trap and a high-NIT JSCR trap can be analyzed more thoroughly using the IB

integral given by (3.1) to cover the entire channel. In view of the good accuracy and

resolution demonstrated by the analytical model of an exponential NIT profile in the

JSCR shown in Fig.4(a)-(c), we shall assume the exponential NIT profile again to model

the L-dependence that showed a high-NIT near the edge or inside of the JSCR over the

entire VpN range (50mV to 700mV) which sweeps this edge over a region about 20nm

to 40nm on the MCR side of the p+D/n-B boundary. Thus, the NIT profile can be

modeled by

NIT(y) = A1 + A2 {exp(-y/A3) + exp[ (y-YMR) /A3] (3.16)

A1 is the constant concentration in the middle of the channel in asymptotic long channel,

A2 is the peak concentration near the edges of the two JSCR's and A3 = LIT is the decay

length of the NIT distribution.

With the TE-DCIV (both Drain and Source are forward-biased at the same VpN)

the minority carrier interfacial concentration, P(x=0,y), in the n-Basewell of a pMOST is

spatially constant in the MCR from y=0 to y=YMCR (y-axis shifted). In the DE-DCIV or

SE-DCIV bias configuration, it is linearly decreasing from the forward-biased drain (or

source) emitter to the zero-biased source (or drain) collector. These are given below

with the origin of the y-axis shifted to the collector-edge of the MCR.

P(x=0,y) = P (Y) = P (YMCR) TE-DCIV

These three minority carrier concentration profiles can be used with the symmetrical

exponential NIT profile of (3.16) to evaluate the IB integral such as (3.1) with the

integration limit extended over the entire channel. To provide the analytical solutions

for IBpk, we shall use the peak value of Rssi in (3.1), which occurs at CpsPs = cnsNs. For

ETI ~ 0 or cpsPs=cnsNs >> eps and ens, it is given by

Rss1-pk = (1/2) (cpsPCnsNs) 1/2 (3.18)

= (1/2) (psns) 1/2 [niexp (qVpN/2) ] TE-DCIV

= (1/2) (cpsns)1/2[niexp (qVpN/2)] (Y/YMCR)1/2 DE/SE-DCIV

Then, from (3.1) using (3.16) and (3.18), and L instead YMCR for the integration limit,

and noting that YMCR = L 2YJscR(VpN), we have

IBpk = { AlL+2A2A3 [1-exp(-L/A3) ] }IBW TE-DCIV (3.19)

= { (2/3)AiL+aA2A3. [l-exp(-L/A3) ] }IBIW DE/SE-DCIV (3.20)

Where c= 1 if A3 << L, or the exponential Nrr(y) is localized near the Source and Drain.

In the other limit that NIT(y) varies slowly across the channel, A3 > L, ca=4/3. These

show that IBpk of TE-DCIV is 1.5 or 2.0 times larger than that of DE-DCIV and SE-

DCIV for very long and short channels respectively.

The TE-DCIV, DE-DCIV and SE-DCIV data at VpN=400mV are fitted to (3.19)

giving the following results which are used for the LSF lines in Fig. 3.15.

A1IBW (pA/pn) A2IB1W (pA/Pm) A3 (nm)
TE 4.30.2 9040 8040
DE 4.10.2 9050 8050
SE 4.80.2 -

These show consistency among the three bias configurations and a NIT(Y) that rises from

the MCR by a factor of 20 to the edge MCR or JSCR (90/4.2=21). The two LSF

parameters, A1 and A2, can be converted to NIT. Using W=10pm, ni=1010cm-3, and

assuming cns=cps=10- cm3/sec, we obtained A =2.2x109cm-2 and A2=4.68x101cm-2

for the interface trap densities in the middle of the channel and near the drain and source





- C

CIV Data LSF Eq (17)



I I I 111111

I I I 11111

I I l I I I4
W=1Om -
VpN=400mV -

I I 1 iI I lI


LEL (1m)


Forward bias configuration dependence of the IBpk-L data from TE-DCIV,
DE-DCIV and SE-DCIV measurements at VpN=400mV, showing the 0.5
ratio at short L from contributions of NIT located inside and near the edge of
the -30nm JSCR and the 0.66 ratio at long L from NIT located in the MCR
which are illustrated more explicitly in Fig. 3.16.

Fig. 3.15

_ ____ __ rl

I I (1111 1 111 II(

The experimental data for the DE/TE and SE/TE ratios of the IBpk are shown in

Fig. 3.16(a) and (b) as a function of forward bias, VpN, showing the predicted variation

with channel L by (3.19) from 0.5 to 0.667. Finally, the LSF profile are plotted in Fig.

3.17 at VpN=400mV with an estimated YJscR=40nm for the shorter channels,

L=0.25gm, 0.4gm, 0.8gm and 2.0pm.

Outside of the MCR or in the JSCRs, NIT seemed to drop as shown by the two

broken lines in Fig. 3.17, as suggested by three experimental evidences: (1) The VpN-

independence of the IBpk in Figs. 3.14(a), 3.16(a) and 3.16(b); and channel-length

dependence of the (2) lineshape, and (3) VGB-pk as indicated in Fig. 3.11. The 0.25gm

pMOST has a higher shoulder and a larger HWHM at the base-accumulation side of the

peak which is consistent with contributions from NIT in the JSCR anticipated by the

analytical theory discussed in section 3.3. There is also a 20mV shift of peak gate

voltages between the L=10gm and 0.25gm curves which could be from two

possibilities: (1) NIT in the JSCR near MCR edge would shift VGBpk(0.25gm) pMOST

towards flatband-accumulation (positive VGB) with respect to VGBpk(lOgm) and (2)

injection-diffusion-limited minority carrier reduction in the 10m pMOST would shift

VGBpk(10pm) towards subthreshold-inversion (negative VGB direction) with respect to

VGBpk(0.25gm). The first explanation is favored because NIT inside the JSCR and near

the MCR/JSCR boundary can account for the lineshape change as well as peak gate

voltage shift as indicated in Fig. 3.11. Furthermore, injection-diffusion-limitation,

proportional to L, is expected to dominate at low VPN due to its lower value from the


L(pm) -

2 -
0 0.8


S 2/3 [constant NIT(y)]

&-- [NIT localized near S/D]

1/2 [N|T localized near S/D]


VpN /(1 V)





- --





L(gm) -

2 -
0 0.8




VpN /(1 V)




Channel length dependence of the IBpk-VPN and its theoretical limits for
short and long channels. (a) DE-IBpk/TE-IBpk and (b) SE-IBpk/TE-IBpk,
showing the theoretically anticipated 0.5 ratio at short L from NIT located
inside and near the edge of ~30nm thick JSCR and the 0.66 ratio at long L
from NIT located in the MCR.








0.4 L








Fig. 3.16




P+ +
su -

I -"








- I
1 2

I 0

0.2 0.4 0.6 0.8


Fig. 3.17 NIT(y) distribution for L(gm)=0.25 to 2.0 of pMOSTs extrapolated from
experimental data using the profiling algorithm described in the text.



exp(qVpN/kT), which is inconsistent with the nearly L-independence of the experimental

VGBpk at all VpN'S shown in Fig. 3.12(b).

The presence of the interface traps inside JSCR should not affect the validity of

MOST parameter extraction using the VPN dependence of VGB-pk as described in section

3.4. The parallel shift in Fig. 3.12(b) indicates that the accuracy of oxide thickness and

substrate doping concentration extraction would not be affected by the channel length of

the MOST. However, there could be a small offset (<20mV) in the extracted flatband


3.6 Summary

A self-consistent picture on the effects of spatial distributions of interface traps

on DCIV characteristics has been obtained and presented. Three applications of the

DCIV method have been demonstrated with experimental data: (1) Extraction of

transistor design parameters using the weak inversion gate voltage at the peak base

terminal current from carrier recombination at interface traps in the channel region; (2)

Profiling the concentration of process-residual and channel hot carrier stress generated

interface traps in the forward-biased drain junction space charge region using a portion

of DCIV curve between the weak inversion gate voltage and strong accumulation gate

voltage; and (3) Profiling the concentration of process residual interface traps in the

channel region using the channel length dependence of base-current peak. These

demonstrations provide further application capabilities for industrial applications of the

DCIV method [50,51].


4.1 Historical Survey

Electron tunneling through a classically-forbidden energy barrier was first

employed by Fowler and Nordheim [52] (F-N) in 1928 to successfully explain the

emission of electrons from the surface of a tungsten electrode into vacuum under the

influence of an external electric field of some 106 V/cm. Schottky attempted to explain

the phenomena by thermionic emission through an image force lowered surface

potential barrier [53], but a complete reduction of the 4.5eV barrier in tungsten requires

a field of at least 108V/cm. In the F-N theory of field emission [54], the electrons inside

the tungsten with kinetic energy lower than 4.5eV have an energy dependent probability

of tunneling through the field-induced triangular potential barrier as determined by

Schrodinger's wave mechanics, while the energy distribution of electrons was obtained

following Sommerfeld's electron theory of metal.

With the advancement of quantum theory and materials technology,

investigation of tunneling phenomena was extended to (1) extrinsic semiconductors first

by Zener [55] which eventually led to the invention of p-n tunnel diode by Esaki [56] in

1957, and (2) metal-oxide-metal (MOM) and metal-oxide-semiconductor (MOS)

structures which were made possible by the thermal oxidation technology to grow

surface oxide. In terms of band theories of semiconductors, Kane [57] interpreted the

interband tunneling in p-n diode as 'electron penetrating the forbidden gap along the

imaginary k axis' and under the constant-field approximation derived an electron

tunneling theory that took into account of perpendicular momentum conservation. The

p-n tunnel diode showed negative resistance under small forward biases due to the

narrowing of energy range for direct interband tunneling with increasing forward-bias

but its current never went to zero even when the constant energy tunneling path ceased

to exist. This 'excess' current was from many trap-assisted inelastic tunneling

pathways, such as those studied by Sah in gold-doped narrow p-n diode [58]. Bardeen

considered tunneling in MOM structure as transferring of a quasi-particle across the

oxide in a many-particle system [59]. He calculated the transition probability using the

time-dependent perturbation approach and showed that the matrix element for the

transition is that of the current density operator in the barrier region. This was followed

by Harrison [60] to treat tunneling through a forbidden region with spatially varying

band structures from an independent-particle point of view. Harrison showed that the

traditional Wentzel-Kramers-Brillouin (WKB) approximation can be readily applied to

band structures which vary slowly over a wavelength of the particle, but at the sharp

boundaries the wavefunctions must be matched to assure the conservation of electron

flux. The latter resulted in an energy-dependent pre-exponential factor in the expression

of the transition probability which was used by Shewchun and Temple [61] in their

computations of tunneling current through semiconductor-insulator-semiconductor

strictures. Simmons [62] introduced the average-barrier approximation to evaluate the

WKB tunneling probability for barriers of arbitrary shape and derived an analytical

tunneling current formula for MOM structures at zero temperature. Simmon's formula

was used by Chang, Stiles and Esaki [63] to correlate their data on electron tunneling

through a trapezoidal barrier in a Al/A1203/SnTe MOS structure while neglecting band

bendings in the highly-degenerate p-type SnTe. By making the WKB approximation,

detailed tunneling current structures due to the sharp potential boundaries are obscured.

Gundlach [64] showed by solving the Schrodinger equation exactly that tunneling

current through a triangular barrier can be an oscillatory function of applied voltage due

to partial reflections and interference of electron waves in the conduction band of the

insulator at the sharp potential boundary.

Since the advent of silicon transistor technologies in the late 1950's [1],

tunneling through metal/SiO2/Si structures has received much attention. Lenzlinger and

Snow [65] performed the original experiment of electron tunneling from silicon into

thermally grown SiO2 and found that the tunneling current density as a function of

electric field J(E) followed the classical F-N theory. They derived a constant effective

mass of 0.42mo in the forbidden energy gap of SiO2 and showed that the simple

parabolic dispersion relationship is equivalent to that of the empirical Franz-type which

reduces to k=0 at both conduction band edge E=Ec and valence band edge E=Ev. We

note that this equivalence is only valid in the triangular barrier range (or F-N range)

while some recent authors applied it to trapezoidal barriers. The band bandings and

carrier quantization effects in silicon inversion layer were considered by Weinberg

[66,67] and those of silicon accumulation layer considered by Krieger and Swanson [68]

who also included transverse momentum conservation and image force correction in

their theory. In view of the accuracy of Weinberg's tunneling J(E) data [66] on thick

~100nm SiO2 films, we will use them as a reference to calibrate our analytical tunneling

theory in the F-N range. On thin -5.0nm oxide MOS structures, Lewicki and Maserjian

[69] observed oscillatory tunneling J(V) characteristics in the F-N range as predicted by

the Gundlach theory. From the decay of the oscillation amplitude with the tunneling

path length in SiO2 conduction band, they obtained a value of scattering mean-free-path

(MFP) in SiO2 conduction band, which was later re-interpreted to be 0.65nm by

Fischetti et al. [70] who correlated this MFP to the electron-LO phonon scattering.

Recently, the oxide fields at which oscillatory extrema occur were used by Zafar et al.

[71] to extract oxide thickness in the range of 4.0nm to 6.0nm.

In MOS structures, tunneling carrier species includes electrons and holes, which

were first separated by Weinberg et al. who diffused a shallow p-n junction in the silicon

substrate under the insulator [72,73]. In a MOS transistor or a MOS capacitor

surrounded by a source region (sourced MOS capacitor, or SMOSC), the inversion

channel and the well/substrate p-n junction (if available) provide a means for charge-

carrier separation. However, this separation is not unambiguous because the carrier type

detected are those in the terminals of the p-n junction or the MOST rather than those in

the oxide. The following three processes lead to the detection of hole currents as a

result of electron tunneling: (1) valence electron tunneling from Si leaves a hole behind

(2) electron tunneling from the gate electrode can impact generate a hole or (3)

recombine with a hole in the silicon substrate. Careful analysis of charge-separation

data were demonstrated by Yau [74] in his identification of electron as the major

conduction carrier in Si3N4. Eitan and Kolodny [75] observed a hole current in the p-

substrate terminal of a 7.8nm oxide n+sourced MOS capacitor under positive gate bias

and attributed it to valence electron tunneling from the p-substrate. This was argued

against by Weinberg and Fischetti [76] because their theoretical estimates for valence

electron tunneling was about 103 times lower than the experimental data. Recently,

Rasras et al. [77] used a remote collector to show that this hole current under large

positive gate voltage was due to electron-hole pair generation in the p-substrate by

photons travelled from the gate electrode. For thin oxide (<3.0nm) under low (<3V)

gate voltages, Shanware et al. [78] showed that their valence band tunneling theory with

a tunneling effective mass of 0.33mo correlated with the hole substrate currents from

which oxide thickness can be extracted.

At the Si/SiO2 interface, the valence band offset is 4.25eV while the conduction

band offset is 3.13eV [79]. The 1.12eV difference in tunneling barrier height makes the

hole tunneling much smaller in magnitude and elusive for experimental detection.

However, secondary hot hole generation [80] and injection [81] from the anode initiated

by F-N tunneling of primary electrons from the cathode was identified to cause positive

oxide charge and dielectric breakdown. The threshold SiO2 voltage to give secondary

hole over-the-barrier injection was found by Lu and Sah [81] to be (1) 4.25V by Auger

generation and (2) 5V by impact generation of energetic holes. Primary hole tunneling

was not reported until very recently in p+gate pMOST [82-84] at the low inversion gate

voltage range, but no quantitative correlation with hole tunneling theory was given.

4.2 Recent Technology Motivations

Literatures on fundamental theories and experiments of tunneling are abundant

as reviewed in the first section. Most of them focused on tunneling through a triangular

barrier. Over the past three decades, semiconductor industry has sustained a growth rate

of 15% per year which is fueled by relentless down scaling of silicon transistors. The

channel length of a MOST is scaled from 25gm in 1962 [1] to about 0.13gm in the

current production technology. Following Dennard's constant-field scaling law [85],

gate oxide thickness and power supply voltage need to be scaled accordingly. Oxide

thickness is scaled down to about 3.0nm in production technologies while more

aggressive scaling to below 1.5nm has been pursued in research and development

establishments [86-87] which is limited by oxide tunneling currents. Power supply

voltage is limited by the MOST threshold voltage to about 1.0V. At such values of

oxide thickness and power supply voltage, the shape of the potential barrier for

tunneling is trapezoidal rather than triangle, and gate oxide tunneling could become a

limiting factor in MOST off-state power dissipation. Also, tunneling current hinders

transistor parameter extraction by traditional measurement techniques such as

capacitance-voltage method [10,13,88]. Accurate modeling of trapezoidal tunneling

through ultrathin (<3.0nm) oxide is needed in new transistor technology development.

Tunneling through a trapezoidal SiO2 barrier has been modeled for conduction

band electron tunneling from nMOST inversion layers [89-92] and from pMOST

accumulation layers [93,94]. When the silicon surface is strongly inverted or strongly

accumulated, electrons at the Si/SiO2 interface are confined by the surface electric field

on the silicon side and the 3.13eV potential barrier on the SiO2 side. Due to the finite

probability of tunneling through the SiO2 barrier, electrons are in quasi-bound states.

Full quantum mechanical models compute the tunneling current by solving the lifetime

of the quasi-bound state [89,91,93], which is computationally demanding and not

suitable for compact modeling. A comparative study of quantum mechanical and

classical modeling, however, reveals similar results in tunneling current-voltage

characteristics [93]. This maybe due to the two quantum mechanical effects that act

against each other as far as tunneling current is concerned: (1) energy quantization gives

a ground state energy above the silicon conduction band minimum which reduces the

effective barrier height, and (2) the centroid of electron distribution in the surface layer

moves away from the Si/SiO2 interface which increases 'tunneling distance'.

Analytical approximations to evaluate lifetimes [92,94], however, render the tunneling

current as a function of oxide electric field and oxide thickness only. Those results give

zero tunneling current at zero oxide electric field rather than at the zero gate voltage,

which is inaccurate for any MOST structures that has work function difference between

gate and substrate materials.

We will develop a compact tunneling current model, which is applicable to the

full gate voltage range for both nMOSTs and pMOSTs. The model will treat conduction

band electrons, valence band electrons and valence band holes on equal basis. The latter

is indispensable to describe the tunneling currents in the inversion range of a p+gate

pMOST. Carrier concentrations in silicon layers will be taken into account both

explicitly and implicitly, the latter through the gate-voltage vs. oxide field relationship,

and tunneling in both directions will be included. This will allow an accurate

comparison of relative importance of various energetic tunneling pathways and

geometric tunneling pathways in MOSTs at low gate voltages. We will correlate the

model to experimental data and explore its utility for transistor parameter extraction.

4.3 Theory of Tunneling in MOS Structures

In deriving our tunneling current formula, we follow Bardeen's transition

probability approach [59] and Harrison's independent-particle tunneling model [60].

The probability per unit time of transition for an electron in state a on one side of the

tunneling barrier to state 3 on the other side is described by Fermi's golden rule:

Pa = (27/h) |Map 2 Ppfa(l-f) (4.1)

Ma0 is the matrix element to be evaluated between the two states a and 1 in the

tunneling region where M is proportional to the current density operator as shown by

Bardeen [59]. pp is the density of states at 1, and fa and f1 are occupation probabilities

of the two states respectively.

The net tunneling current density is derived by summing over all allowed states

a and subtracting the reverse tunneling current under the constraint of transverse

momentum (kt) conservation [60]:

J IM a12 PaP(fa-f) dE (4.2)
h kt 0

The additional factor 2 accounts for spin degeneracy, q is the charge of an electron and

zero to Em represents allowed energy range for tunneling. The summation over

transverse momentum can be converted to integrals if the electrons are free to move in

the transverse directions: I -- 1/(2nt)2dkyfdkz. The double integration over transverse

momentum can be carried out explicitly for the Fermi functions (fa-f.). The matrix

element can be evaluated if the wavefunctions inside the tunneling barrier for state a

and 0 are written in terms of WKB approximations. The result is the familiar

exponential WKB tunneling probability. Figure 4.1 shows an energy band diagram of a

Si/SiO2/Si trapezoidal barrier. The Si/SiO2 conduction band and valence band offsets

are denoted by OBn and OBp respectively. The initial state on the right side of the barrier

with kinetic energy El and wavefunction Ygs tunnels to the final state on the left side

with kinetic energy E2 and wavefunction TS2. At the two abrupt boundaries, x=0 and

x=Xox, both Y and (1/ms)aY/aX must be continuous to conserve electron flux.

Wavefunction matching of Ysl at x=0, and Ys2 at x=Xox results in an electron kinetic

energy dependent pre-exponential factor.

Applying the above for electron tunneling through Si/SiO2/Si structure (see

Appendix for detailed analysis), we derive the following tunneling current formula for a

single ellipsoid conduction band sub-valley in the silicon:

4tnqmdkT 0Bn
JN = 3 J0 To(E) exp[-2 (Ex)]

X le 1+exp[ (EF-Ec-Ex) /kT] dE 3)
x loge dEx ( 4.3 )
l+exp [ (EF-Ec-Ex-qVGB) /kT]

md is the density-of-states effective mass of the sub-valley, Ex=(E-Ec)-Et is the

electron kinetic energy in the tunneling direction x, EF is the Fermi energy, EC is the


Ev OBp

Si Si02 Si

Xox 0

Fig. 4.1 Trapezoidal barrier for electron tunneling in a Si/SiO2/Si structure.
Electron wavefunctions of the initial and final states are denoted by 'Ps and
'S2 respectively. Boundary conditions at x=0 and x=Xox must be satisfied
to conserve electron flux across the two abrupt boundaries.

conduction band minimum in the semiconductor near the tunneling boundary. To(Ex)

and u(Ex) are the pre-exponential factor and the exponent of the WKB tunneling

probability respectively to be described as follows in conjunction with figure 4.1.

To(Ex) =
mxklx(0) mslKox (0) xk2(OX ms2Kox(Xox)
+ + I-
slKox() moxkl (0) 2Kx(Xox) moxk2x(Xox) (4.4)

v(Ex) = K (x)dx
.0 (4.5)

msi (i=l, 2) are the normal effective mass in the two silicon regions, and mox is the

tunneling effective mass in the SiO2 layer with two boundaries at x=0 and x=Xox

respectively. klx(0) and k2x(Xox) are real wave numbers at the silicon side of the

boundaries, while K(O) and K(Xox) are imaginary wave numbers at the SiO2 side of the

boundaries. Assuming parabolic conduction band of SiO2 and extending the dispersion

relationship analytically into the energy gap, we have the traditional expression for K,

which is:

K(x) = [2mox(~ n-qEox-Ex)] 1/2/) (4.6)

Eox is the electric field inside SiO2 and is constant for a trapezoidal barrier. We will

include some discussions to the above formulas (4.3) to (4.6) in the following


The WKB approximation is valid when the de Broglie wavelength (X) of the

electron (or its imaginary analogue inside the barrier) is much smaller than the

characteristic length over which the potential varies appreciably [95]. For the Si/SiO2

electron barrier, X can be estimated as follows:

1 h
S= = = 1.5A
K (2mox B)1/2 (4.7)

This result shows that the WKB approximation should be valid for oxide thickness as

thin as 10-15A which is already 6-10 times larger than the (imaginary) electron


The pre-exponential factor To(Ex) of (4.4) is valid for trapezoidal barrier only in

which both boundaries are abrupt. This kinetic-energy dependent factor plays an

important role in explaining the gate voltage dependence of thin oxide tunnel data as

will be shown later. It gives the largest correction near the flatband voltage as compared

to the traditional unity pre-exponent. Equation (4.4) is symmetric to the two silicon

layers, which is consistent with the notion that the tunneling probability of a trapezoidal

barrier is independent of the tunneling direction. In the triangular barrier range, only an

approximate form of pre-exponential factor can be derived (see Appendix). A similar

factor was used by Krieger and Swanson [68]. As it does not affect the gate voltage

dependence of tunneling current, we simply use To=1 in the triangular barrier range.

The band structures of SiO2 was studied by Li and Ching [96]. However, the

exact dispersion relationship in the wide energy gap of SiO2 is not known. We use the

simplest parabolic band approximation in (6). The empirical Franz-type dispersion

relationship has been used by several authors [92,94], which treated the conduction band

barrier and valence band barrier on the same footing. However, it assumed equal

effective masses near the valence band edge and near the conduction band edge, i.e.,

mcb=mvb. This is not supported by theoretical band structure calculations [96] that

showed a much smaller curvature near the valence band edge (mvb>mcb). Using the

form suggested by Freeman and Dahlke [97], a more appropriate empirical E(k)

relationship in the energy gap is:

K-2(Ex) = Kb2 (E)+Kvb2 (E)

= h2/[2mcb (B-qEoxX-Ex) ] +2/{2mvb[Eg- (0B-qEoxX-Ex) ] (4.8)

where Eg=8.5eV is the energy gap of SiO2. Equation (4.8), however, does not yield an

analytical solution for the tunneling probability. Since mvb is much larger than mcb, it

would be a better approximation by simply dropping the second term on the R.H.S. of

(4.8) (the parabolic band approximation) than retaining both terms and making mvb=mcb

(Frantz-type dispersion relationship).

It would be straightforward to prove that the equation (3.3) reduces to the

classical Fowler-Nordheim formula under these conditions: (1) low temperature: T--0,

(2) highly degenerate n-type surface layer: E-Ec>kT (3) triangular barrier and (4) unity

pre-exponential factor: To(Ex)=I. The classical F-N formula predicts that a semilog plot

of JFN/Eox vs. 1/Eox is a straight line:

JFN = aEox exp(-P/Eox) (4.9)
a = q3md/ (16;r2 moxB)

P = 4(2moxOB3)1/2/(3qh)

The total conduction band electron tunneling current is obtained by summing

over contributions from all six conduction band subvalleys of silicon. The result

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