Analysis, modeling, and control of floating-body effects in nanometer-gate-length partially depleted silicon-on-insulato...

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Analysis, modeling, and control of floating-body effects in nanometer-gate-length partially depleted silicon-on-insulator CMOS devices and circuits
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Metal oxide semiconductor field-effect transistors -- Design and construction   ( lcsh )
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Thesis (Ph.D.)--University of Florida, 2000.
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ANALYSIS, MODELING, AND CONTROL OF FLOATING-BODY EFFECTS IN
NANOMETER-GATE-LENGTH PARTIALLY DEPLETED SILICON-ON-
INSULATOR CMOS DEVICES AND CIRCUITS















By

MARIO MICHAEL ALBERT PELELLA


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY


UNIVERSITY OF FLORIDA


2000













ACKNOWLEDGMENTS


I would like to express my deepest appreciation to my advisor and

chairman of my supervisory committee, Professor Jerry G. Fossum, for his guidance,

stimulating discussions, and encouragement which enabled a mature student to

successfully complete this significant milestone. His exemplary pursuit of academic

excellence, integrity, and standards will be a constant source of inspiration

throughout the rest of my life. I also would like to thank the members of my

supervisory committee, Professors Gijs Bosman, Sheng Li, Kenneth 0, and Timothy

Anderson for their support and interest in this work.

I am grateful for the financial support of the Semiconductor Research

Corporation, the University of Florida, and IBM which awarded the author a

prestigious IBM Cooperative Fellowship.

I would also like to thank former students Drs. Dongwook Suh, Srinath

Krishnan, Doug Weiser, Duckhyun Chang, Wenyi Zhou, and Glenn (Chip) Workman

whom I had the opportunity to mentor while I was in industry and who helped inspire

my return to academe, along with Ms. Yan Chong and Mr. Bin Liu; and also current

students Meng-Hsueh Chiang, Keunwoo Kim, Lixin Ge, Ji-Woon Yang, and Kehuey

Wu for their friendship and profound technical discussions.

Finally, I am deeply thankful to my immediate family: my cherished wife,

Anne Marie, who is truly a saint for putting up with this endeavor while nurturing







our three adorable children: Mary, Mario Michael, and Grace; my father, Mario M.

Pelella, Sr.; mother, Raphaela (Lena) Pelella; father-in-law, Dr. Victor Moruzzi;

mother-in-law, Joan Moruzzi for their unending love, support, and encouragement

throughout my years; and my brothers, John and Anthony, and sister, Giovanna for

their warm and frequent contacts via email and phone calls which helped to lift my

spirits through much of this work.



Pax et Bonum.













TABLE OF CONTENTS


page

ACKNOWLEDGMENTS .................................................ii

LIST OF TABLES ......................................................vii

LIST OFFIGURES ................................................. viii

KEY TO ABBREVIATIONS.............................................. xi

ABSTRACT ...................................................... xii

CHAPTERS

1 INTRODUCTION ............................................... 1

2 ANALYSIS AND CONTROL OF OFF-STATE CURRENT IN SCALED PD/SOI
WITH FLOATING BODIES ................................... 7

2.1 Introduction .................................................. 7
2.2 Analysis of the Floating-Body Effect on Off-State Current .............. 8
2.3 Temperature Dependence of the Body Voltage at Off State ............ 12
2.4 Controlling Floating-Body Effects at the Off-State Condition .......... 16
2.5 Effects on Performance ........................................ 18
2.6 Conclusions ......................................... .... .... 22

3 ANALYSIS AND CONTROL OF HYSTERESIS IN PD/SOI CMOS........ 25

3.1 Introduction ................................................ 25
3.2 Fundamental Delays and Methodology ............................ 27
3.3 Dynamic Loading Effect ....................................... 31
3.4 Dynamic-Gate and Heavy-Loading Effects......................... 32
3.5 Integrity of the Dynamic Steady-State Results ...................... 35
3.6 Does Controlled Off-State Current Imply Hysteresis Control?.......... 35
3.7 Correlation to Measurements................................. ... 36
3.8 Scaling ..................................................38
3.9 Control of Hysteresis: Asymmetric SOI CMOS ..................... 42
3.10 Circuit Application.................. ......................... 44







3.11 Sum m ary .................................................... 48

4 PERFORMANCE ADVANTAGE OF PD/SOI WITH FLOATING BODIES.. 49

4.1 Introduction .................................................49
4.2 Unified Model for PD/SOI and Bulk-Si MOSFETs................... 51
4.3 Performance Benefits of Contemporary SOI........................ 54
4.3.1 Modeling and DC Characteristics .......................... 54
4.3.2 Performance Comparison................................. 56
4.3.3 Hysteresis Effect ........................................ 58
4.4 Performance Insights ....................... ................. 60
4.4.1 Delay Benefit from Junction Capacitance .................... 60
4.4.2 Delay Benefit from the Kink Effect......................... 60
4.4.3 Delay Benefit from the Capacitive-Coupling Effect ............ 62
4.4.4 Body-Voltage Dynamics and Increased Threshold Voltage ...... 63
4.5 Scaling SOI: Diminishing Returns?............................... 65
4.5.1 Scaled SOI CMOS Devices ............................... 65
4.5.2 Performance Comparison................................. 66
4.5.3 Loss of SOI Advantage ................................ 68
4.5.4 Temperature Effects................................... 70
4.6 Increased SOI Advantage: Stacked Logic Gates ..................... 72
4.6.1 Top-Switching Case............... ................... 74
4.6.2 Bottom-Switching Case .................................. 76
4.6.3 Simultaneously Switching Case....................... ...... 77
4.6.4 Device Width Ratio and Temperature Sensitivity .............. 79
4.7 Discussion: Optimization and Future Opportunities .................. 80
4.7.1 Optimization: Recombination Current and Device Structure ..... 80
4.7.2 Present Benefits ...................................... 81
4.7.3 Near-Term Future................................... 82
4.7.4 Future .............................................. 83
4.8 Conclusions ................................................ 83

5 PD/SOI MOSFETs AT LOW TEMPERATURE......................... 86

5.1 Introduction ............................................... .. 86
5.2 Anomalous Drain Current at Low T: New BJT Effect ................. 88
5.3 Revised Gate Control of the BJT Model ........................... 91
5.3.1 BJT Current Insight at Low T ............................. 95
5.3.2 Revised Subthreshold Characteristics as a Function of T ........ 97
5.4 Impact of Low-T BJT Effect on Off-State Current and IDDQ .......... 97
5.5 Same-Off-Current T-Scaling Scenario............................ 101
5.5.1 Threshold and Performance Impact ........................ 101
5.6 Same-Device T-Scaling Scenario............................... 103
5.6.1 Threshold Voltage and Performance Impact ................. 103
5.7 SOI Benefit at Low T................................... 106
5.8 Conclusions .............................................. 108







6 SUMMARY AND RECOMMENDATIONS FOR FUTURE WORK ....... 110

6.1 Summary ..................................................110
6.2 Recommendations for Future Work ........................... 113

APPENDIX .......................................................... 115

CONTROL OF FLOATING-BODY EFFECTS BY SOURCE/DRAIN
JUNCTION ENGINEERING .................................. 115

REFERENCES ..................................................... 121

BIOGRAPHICAL SKETCH ............................................ 126












LIST OF TABLES


Table page

4.1 Comparison of Ion and Ioff for the nominal Leff=145nm MOSFET devices at the
minimum Leff condition ........................................... 56

4.2 Predicted steady-state delay and hysteresis results for the four Leff=145nm
technologies ................................................... 58

4.3 Comparison of Ion and Ioff of the nominal Leff=70nm devices at the minimum Leff
condition for the scaled MOSFET technologies ........................ 66

4.4 Predicted steady-state delay and hysteresis results for the five scaled Leff=70nm
technologies ..................................................69

4.5 Predicted steady-state delay and hysteresis results for the five scaled Leff=70nm
technologies at elevated ambient temperatures.......................... 72

4.6 2WNAND top switching configuration truth table of Fig. 4.8 .............. 74

4.7 2WNAND bot switching configuration truth table of Fig. 4.8.............. 76

4.8 2WNAND simultaneously switching configuration truth table of Fig. 4.8. ... 77

4.9 Predicted propagation delay and hysteresis results for the three switching
configurations of a 2WNAND circuit. ............................. 79













LIST OF FIGURES


Figure page

1.1 The network representation of the UFSOI physical charged-based compact device
model.................... ................................. 3

2.1 Model calibration for 145nm technology .............................. 9

2.2 Predicted IDs-VGS for minimum L with nominal threshold. .............. 11

2.3 Measured IDS-VGS for 100nm technology as a function of T .............. 13

2.4 Predicted IDS-VGS as a function of recombination current. ............... 17

2.5 Measured IDS-VGS with and without Ar I........................... 19

2.6 Floating-body voltage versus T with m and IR varying .................. 20

2.7 Predicted IDS-VDS for T and IR variations ............................21

2.8 Predicted RO delay vs. VDD with T and IR variations ................... 23

3.1 Schematic depicting IR and IG charging..............................26

3.2 Definitions of fundamental and average delays ......................... 28

3.3 Hysteretic delay and body voltage results of an CMOS inverter. ........... 30

3.4 Dynamic loading effect on hysteretic delays ................... ...... 33

3.5 Heavy loading effect on hysteretic delays......................................34

3.6 Increased T and IR effects on hysteretic delays........................ 37

3.7 Sensitivity of film thickness on hysteretic delay......................... 39

3.8 Effect of lower VDD on hysteretic delays............................ .40

3.9 Scaled technology effects on the hysteretic delays....................... 41


viii








3.10

3.11

3.12

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10


Techniques to control hysteresis ............................

FB PD/SOI CMOS microprocessor simulation..................

Suppressing hysteresis to prevent microprocessor fails...........

PD/SOI and bulk-Si IDS-VDS, IDS-VGS predicted by UFSOI/PD-B..

Predicted IDS-VGS for SOI and bulk-Si 145nm technologies. .....

Predicted delay for SOI and bulk-Si 145nm technologies. ........

VBS vs. time for nominal and increased Vt FB/SOI technologies....

Predicted IDS-VGS for SOI and bulk-Si 70nm technologies. ......

Predicted delay for SOI and bulk-Si 70nm technologies. .........

Predicted delay for SOI and bulk-Si 70nm technologies at T=850C.

Schematic of a two-input NAND circuit.......................

Predicted 2WNAND delay for SOI and bulk-Si 70nm technologies.

Predicted 2WNAND delay for various switching configurations....

Predicted IDS-VGs for bulk-Si as a function of T ...............

Predicted IDS-VGS for PD/SOI as a function of T ...............

Measured IDS-VGS for Lgaie=100nm PD/SOI as a function of T....

Measured IDS-VGS for Lgate=250nm PD/SOI as a function of T....

Revised BJT(lsf(VGs)) model ..............................

Revised Vysf Smoothing Function, T=-100C, Leff=70nm .........

Revised IDS-VGS for PD/SOI as a function of T with new BJT mod

Predicted loff as a function of T..............................

Measured IDDQ versus T .................................

Predicted saturated threshold voltage versus T for same-lof. ......


........ 43

........ 45

........ 47

........ 53

........ 55

........ 57

....... 59

. ..... 67

... ... 68

........ 7 1

........73

. ... 75

........ 78

........ 87

........ 89

........ 90

........ 92

....... 93

...... .. 96

el ....... 98

........99

.......100

. ..... 102







5.11

5.12

5.13

A.1

A.2

A.3

A.4


RO delays for same-ffT-scaling vs. T.............................. 104

Predicted saturated threshold voltage versus T for same-device............ 105

RO delays for same-device T-scaling vs. T .......................... 107

Schematic cross-section of the PD-tgap/SOI nMOSFET................. 116

Medici current flow of an abutted source junction to the buried oxide. ..... 117

Medici current flow of the PD-tgap/SOI device structure ............... 118

Medici current-voltage for abutted and xj defined source junction. ........ 120












KEY TO ABBREVIATIONS


BOX

BTS

CMOS

DIBL

FB

FD

GIDL

IC

MOSFET

NFD

SOI

UFSOI


back oxide

body-tied-to-source

complementary metal-oxide-semiconductor

drain-induced barrier lowering

floating body

fully depleted

gate-induced drain leakage

integrated circuit

metal-oxide-semiconductor field-effect transistor

non-fully depleted (partially depleted)

silicon-on-insulator

University of Florida silicon-on-insulator












Abstract of Dissertation Presented to the Graduate School of the
University of Florida in Partial Fulfillment of the Requirements
for the Degree of Doctor of Philosophy


ANALYSIS, MODELING, AND CONTROL OF FLOATING-BODY EFFECTS IN
NANOMETER-GATE-LENGTH PARTIALLY DEPLETED SILICON-ON-
INSULATOR CMOS DEVICES AND CIRCUITS

By

Mario Michael Albert Pelella

December 2000

Chairman: Jerry G. Fossum
Major Department: Electrical and Computer Engineering

This dissertation focuses on the analysis, modeling, and control of

floating-body (FB) effects in scaled (nanometer-gate-length regime) silicon-on-

insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect

transistors (FETs). Refinements to the University of Florida SOI (UFSOI) partially

depleted (PD) (or non-fully depleted, NFD) SOI MOSFET model are developed and

applied to gain insight into the behavior of SOI MOSFETs in integrated circuits.

The scalability of PD/SOI CMOS is assessed while giving a physically

insightful analysis of the FB effect on off-state current (Ioff), which tends to be high

compared to that of bulk-Si technologies. The analysis shows that the FB effect on

Ioff can be naturally ameliorated by typical high operating temperatures (T) and

increased junction recombination currents. Physical insight into such control of FB

effects is provided.







An efficient new methodology to properly analyze hysteresis is developed

utilizing the four fundamental delays of an FB PD/SOI CMOS inverter, which are

defined. The hysteretic-delay analysis reveals the possibility of non-monotonic

delays caused by a newly recognized dynamic-loading effect. Hysteresis trends are

shown to increase or decrease when the device structure is modified; an asymmetric

design concept is thereby conceived. Moreover, hysteresis is shown to worsen as the

technology is scaled.

A new unified UFSOI modeling capability is implemented to enable

performance of bulk-Si CMOS to be assessed as a counterpart technology to PD/SOI

CMOS. This models allows a bulk-Si counterpart structure to be simulated with

exactly the same device design assumptions as the PD/SOI technology. With this

capability, the performance benefits for contemporary and scaled FB PD/SOI versus

bulk-Si technologies are assessed. Insights underlying the benefits are given; the

advantages are shown to diminish for scaled inverter circuits, while stacked gate

logic circuits are shown to restore the performance advantage for the FB PD/SOI

technologies.

The behavior of FB PD/SOI is investigated at low operating temperatures

(T), revealing an anomalous drain current near and below the Ioff condition. This

anomalous current is shown to be caused by the parasitic lateral BJT and is

corroborated by I-V and IDDQ measurements. The gate dependence of the BJT

model in UFSOI is revised to improve its physical accounting of the behavior near

and below the Ioff condition. The impacts of two T-scaling scenarios are assessed,

revealing a significant performance gain as T is decreased to -500C to -1000C.


xiii













CHAPTER 1
INTRODUCTION


Silicon-on-insulator (SOI) MOSFETs have generated enormous interest

due to the promise of improved isolation and integration density, reduced parasitic

capacitances, and improved radiation-hardened features as compared to their bulk-Si

counterparts. Along with providing superior power/performance, SOI CMOS is

progressing towards becoming the ULSI technology of choice for low-power, high-

performance electronic system applications.

Although both fully depleted (FD) and partially depleted (PD) SOI device

structures are being developed in the semiconductor industry, PD/SOI CMOS has

emerged as the leading candidate to become the mainstream device technology. This

is due to the improved scalability and better threshold control (manufacturability) of

PD/SOI leading to greater flexibility in optimizing the device design over FD/SOI.

However, the floating body (FB) of the PD/SOI device, due to its isolated neutral

body region, can lead to device and circuit instabilities causing unwanted glitches or

failures in circuits, especially in dynamic logic and memory circuits. With SOI-

material concerns rapidly diminishing, the problematic FB effects in PD/SOI

technologies are the most significant design issue preventing its ubiquitous use in

product designs.

The FB effects of PD/SOI are manifested in both the static (e.g., kink

effect, single transistor latch, premature drain-source breakdown) and dynamic (e.g.,

transient threshold voltages, capacitive coupling to the body, drain current

overshoot, hysteretic memory effects, transient parasitic bipolar leakage effects)

operations of the device. To deal with the implied design issues, the unique behavior







of these FB effects must be fully understood (via physical mechanisms) and

implemented into mature device models so that product designers can reliably

evaluate their circuits for possible instabilities. The aim of this work is to assess the

scalability of the PD/SOI device structure at both room temperature and moderately

low temperature, while evaluating the FB effects and amenable approaches to control

them. Extending and refining deficiencies of the UFSOI PD (or non-fully-depleted

(NFD)) device model [Suh95], [Kri96], [Cha97b], [Wor99], [Fos99] are pursued

when necessary to enhance its predictive capability. To truly capture the complex FB

dynamics in PD/SOI technologies it is essential that the analyses use a physical

(based on device structure and profile information) charged-based compact device

model, such as the UFSOI model shown in Fig. 1.1. Empirical (especially

capacitance-based) models are vulnerable to numerical instability, charge-

nonconservation, and integrity issues, and hence are unreliable for accurately

predicting the behavior of the FB PD/SOI technologies as described in this work.

The scalability and viability of PD/SOI CMOS are addressed in Chapter 2

while giving a physically insightful analysis of the FB effect on loff, which tends to

be high compared to that of bulk-Si technologies and significantly impacts the

nominal design point and performance of a given SOI technology. The analysis

indicates that the FB effect on loff can be naturally ameliorated by typical high

operating temperatures (T) and increased junction recombination currents. The

temperature dependence of the induced body-source bias, VBs(T), is developed to

gain insight into possible ways to control FB effects; it is shown to have a significant

negative temperature coefficient. The impacts of using increased T and IR as

controlling techniques for the FB effect are evaluated in RO inverter circuits and














ICH


RS+RLDS

S S
-- -*


dQGb
dt


dQGf
dt


RD+ RLDD


-'RGt(VB'D')


Gb


Figure 1.1


The network representation of the UFSOI physical
charged-based compact device model.


IRGt(VB'S')







device characteristics, the results of which contradict a negative assessment recently

put forth in the literature [Cha97].

An efficient new methodology to properly analyze history-dependent

propagation delay (hysteresis) [Suh94] is developed, including its true worst case,

utilizing the four fundamental delays of a FB PD/SOI CMOS inverter that are defined

in Chapter 3. This methodology enables a fundamental understanding of the complex

FB dynamics that govern the hysteretic delays and provides the flexibility of

analyzing variations in duty cycle and slew rate in any particular circuit. The analysis

reveals the possibility of non-monotonic delays caused by a newly recognized

dynamic-loading effect. Hysteresis trends are shown to increase or decrease by

adjusting the device structure or by using a proposed asymmetric design concept.

Moreover, hysteresis is shown to worsen as the technology is scaled, and the impacts

of dynamic (i.e., changing gate load of an inverter chain) and heavy (e.g., long metal

lines) loading effects are investigated. Additional analyses are included to provide

insight into a discrepancy in the literature between simulations and measurements of

the hysteretic delay.

A new unified modeling capability is implemented in UFSOI to enable

performance assessments of bulk-Si CMOS in a stand-alone technology or as a

counterpart technology to PD/SOI CMOS. This model allows a bulk-Si counterpart

structure to be simulated with exactly the same device design assumptions as the PD/

SOI technology, eliminating any ambiguities in device design and structure. With

this capability, the performance benefits for contemporary and scaled FB PD/SOI

versus bulk-Si technologies are assessed in Chapter 4. Insights underlying these







benefits are given; the advantages FB PD/SOI are shown to diminish for scaled

inverter circuits, while stacked gate logic circuits are shown to restore the

performance advantage for the FB PD/SOI technologies.

As the CMOS scaling trend begins to slow due to fundamental factors such

as oxide tunneling, excessive off-state current, and voltage nonscaling [Tau97],

[SIA99], one option to improve performance is to reduce the ambient operating

temperature (T) of the semiconductor chip. In Chapter 5, the behavior of FB PD/SOI

is investigated at low operating temperatures, revealing an anomalous drain current

near and below the Ioff condition. This anomalous drain current is shown to be caused

by the parasitic lateral BJT and is corroborated by I-V and IDDQ measurements. The

gate dependence of the BJT model in UFSOI, which predicted the anomaly, is revised

to improve its physical accounting of the behavior near and below the loff condition.

As T decreases, loff is shown to switch from being controlled by the MOSFET

channel current to being controlled by the parasitic BJT current, which increases with

decreasing T, giving rise to a non-monotonic trend for loff and suggesting a possible

limit to the low-T operating range. The impacts on threshold voltage and propagation

delay for two T-scaling scenarios (same-device and same-lff) are assessed revealing

a significant performance gain as T is decreased to -500C to -1000C, a practical range

of operating T.

Chapter 6 summarizes the significant contributions of this work, and then

concludes with recommendations to preserve the predictive capabilities of the

UFSOI compact models as device technologies are scaled to dimensions (-10nm)

near the end of the SIA roadmap [SIA99].

The Appendix describes an alternative device structure to suppress the FB

effects in PD SOI CMOS, which naturally increases the recombination current of the




6


junctions. The modified device structure intentionally employs a gap between the

source/drain regions and the buried oxide (e.g., as in [Hor96]). The gap provides

additional junction area for recombination current at the source to prevent the build-

up of excess charge in the neutral region of the body. A preliminary analysis of this

device structure via Medici is included, showing the potential benefits of using such

a design.













CHAPTER 2
ANALYSIS AND CONTROL OF OFF-STATE CURRENT IN SCALED PD/SOI
WITH FLOATING BODIES


2.1 Introduction

A recent study [Cha97] of the scalability of partially depleted (PD) SOI

CMOS technology led to the conclusion that it was no better than bulk-Si CMOS for

sub-0.25gm logic applications, irrespective of its inherent advantages. The

investigators argued that the PD/SOI nMOSFET would need a higher threshold

voltage (Vt) to limit off-state current (loff) because of the Vt reduction resulting from

the drain (VDs)-induced floating-body (FB) effect, in addition to the barrier lowering

(DIBL). Results obtained from circuits made by using the same process flow for SOI

and bulk-Si wafers, except for a modification to give higher Vt for the SOI

nMOSFETs, were presented to project inferior SOI speed performance for Leff <

0.15pm, as well as undermined SOI (dynamic) power performance. Of course, the

performance losses were due to the higher Vt.

In this chapter a physically insightful analysis of the FB effect on Ioff is

given, based on the scaled PD/SOI CMOS technology described in [Cha97], which

contradicts the negative assessment of the scalability of SOI digital ICs. Operation

at high chip temperatures (T=55-850C) that are typical for high-performance circuits

is shown to naturally ameliorate the FB effect, and previously proven techniques for

controlling FB effects are shown to be effective in limiting loff as well. Further, it is







shown that the amelioration at high T is significantly enhanced when the mentioned

techniques are employed. The performance (Ion, TRO) impact of elevated temperature

and increased IR operation is shown to be minimal, and the analysis indicates that

PD/SOI can achieve at least a 15% relative speed advantage over its body-tied PD/

SOI (or bulk-Si) counterpart.



2.2 Analysis of the Floating-Body Effect on Off-State Current

The measured subthreshold IDS-VGS data plotted in Fig. 2.1 were given in

[Cha97] for a floating-body PD/SOI nMOSFET with Leff = 0.1451.m and Vt = 0.61V

(at low VDS). These data and device structural information (4.5nm gate oxide, etc.)

also given in [Cha97] were used to calibrate the non-fully depleted (or PD) model in

UFSOI/SPICE [Fos97]. The UFSOI model is physical and process-based, and hence

amenable to reliable calibration based on the device structure and minimal I-V data.

Unlike typical empirical compact models, it has only a few parameters that need to

be tuned to measured data, and hence it can be predictive, as exemplified in [Suh94].

The process-based calibration procedure used here is similar to that described in

[Chi98]. The UFSOI model-predicted IDS-VGS characteristics, as shown

superimposed in Fig. 2.1, match the data quite well and the results give good insight

about the device and the technology. For example, the FB effect, reflected by the

large VDS-induced shift in IDS(VGs), is influenced significantly by GIDL [Che87];

with the GIDL current in the UFSOI model turned off, the predicted shift, shown in

the figure, is much smaller at currents where impact ionization is not predominant in

charging the floating body.











10-3 T=270C .

10-4

10-5 0.05V

10"6 -

10-7

10-8

109 Measured Data
10-10 UFSOI Model w/ GIDL

10-11 -- UFSOI Model w/o GIDL
10"2 i//


10"13 *

10-14
-0.5 0.0 0.5 1.0 1.5 2.0
VGS (V)




Figure 2.1 Model calibration for 145nm technology.
Measured subthreshold current-voltage characteristics of a PD/SOI
nMOSFET (Leff=145nm, tox,=4.5nm, Vt=0.61V) [Cha97], and
UFSOI-predicted characteristics with and without GIDL.







The high Vt was chosen in [Cha97] to limit Ioff to about lnA/.Lm (at T =

270C) at VDD = 1.8V for the minimum Leff of 0.1 llm in the 0.15pm PD/SOI CMOS

technology described. In fact, the nominal Vt = 0.4V design (with lower channel

doping) would yield an excessive loff (drain current at VGS = 0 with VDS = 1.8V) for

the Leff = 0.1 lpm device as shown by the UFSOI-predicted characteristics in Fig.

2.2. By comparing the characteristics with those of the same device with its body tied

to the source (BTS), also shown in Fig. 2.2, it can be seen that the large drain-induced

shift of IDs(VGs) is due predominantly to the FB effect; at IDS = Ioff, the FB effect

adds 219mV (AVFB as labeled in Fig. 2.2) to that due to the DIBL effect. The latter,

only about 80mV as reflected by the BTS device, is comparable to that of a 0. lpm

bulk-Si device.

The FB effect increases Ioff by more than two orders of magnitude in Fig.

2.2, and does indeed portend the need for higher Vt. (Note that the increase in Vt

(143mV) needed to make Ioff = Ioff(BTS), which is tantamount to AVFB = 0, is

substantially smaller than AVFB.) However, as the ambient, or chip temperature is

raised, the FB effect becomes less severe as predicted by additional UFSOI/SPICE

simulations. The temperature dependence of the UFSOI model [Wor98] is physical

too, being defined directly by well known dependence of the pertinent physics-

based model parameters without any new parameters. The inset in Fig. 2.2 gives

UFSOI-predicted AVFB versus T, and the corresponding relative increase in loff due

to the FB effect. For T=850C, AVFB is reduced to only about 100mV and the increase

in Ioff is reduced to less than one order of magnitude. Measured subthreshold current-

voltage characteristics [Kri98b] of a Leff=100nm nMOSFET as a function of T, shown in









10-2
VDS= .8V
10-3 FB
.BTS
0.05V
10-5 AVFB
10-6 T=27C
10-6


I T (OC) AVF (mV) lofioff(BTS)
108 143mV
27 219 232
10-9

10-10 / 55 168 43

10-11 1 85 105 9

1021
1100 80 5
10-13

10-14
-0.5 0.0 0.5 1.0 1.5 2.0
VGS (V)






Figure 2.2 Predicted IDS-VGS for minimum L with nominal threshold.
UFSOI-predicted subthreshold current-voltage characteristics of the
Leff = 0.11 gm nMOSFET in the Vt = 0.4V (for Lef= 0.145gm) design.
The table inset gives the predicted AVF (as labeled) and loff /off(BTS)
ratio for increasing temperature.







Fig. 2.3, corroborate the negative temperature-coefficient trend of the Ioff fIoff(Bulk-Si) ratio

as predicted by the UFSOI models. These results imply the viability of scaled PD/SOI

CMOS in high-performance applications where 55-850C operation is typical.

Explanation of this improvement at high T follows from a physics-based

interpretation of the simulation results in Fig. 2.2.



2.3 Temperature Dependence of the Body Voltage at Off State

The FB effect underlying the increase in loff is a reduction in V, caused by

a forward bias VBS (i.e., a separation of the electron and hole quasi-Fermi potentials)

developed on the body-source junction at high VDS. Holes generated near the drain

are injected into the floating body, and henceforth raise VBS in support of carrier

recombination to balance the generation in the DC steady state. The simulations of

Fig. 2.2 (as well as measurements of typical scaled, low-Vt PD/SOI MOSFETs) show

that the predominant generation mechanism in the subthreshold region is weak

impact ionization driven by the channel current. Thermal generation (IGt) and

tunneling current (Itun) are negligible; GIDL, as depicted in Fig. 2.1, could be

important for higher Vt. Thus, the generation current at the off condition is


IG Gt +Itun +GIDL ff M )off (2.1)


where (M-l) << 1 is the multiplication factor for impact ionization, which is

characterized by a non-local model [Kri96] in UFSOI. (Note that lowering VDS, or

scaling VDD, would reduce the FB effect since (M-l) would decrease sharply.) The












10-2
10-3
10-4
10-5
10-6


10-8
10-9


1010 25 0.96 32
10 -1150 2.20 20
2102 85 5.83 12
10-13 /
10I
10-14 .v------,. ..--. .,-. .
-0.5 0.0 0.5 1.0 1.5
VGS (V)






Figure 2.3 Measured IDS-VGS for 100nm technology as a function ofT.
Measured subthreshold current-voltage characteristics [Kri98b] of an
Leff=0.lJIm nMOSFET that corroborate the UFSOI model predictions.
The table inset gives the measured Ioff and loff /off(Bulk-Si) ratio for
increasing temperature that corroborates the decreasing Ioffl/off(bulk-Si)-
ratio trend of the UFSOI model predictions in Fig. 2.2.







off-state channel current in the FB device can be expressed in terms of that in the

BTS device [Suh95]:



Ioff= I TSf(BTS)exP qBk (2.2)
( I kT


where a = Cb/C0 (= 0.42 for the technology in [Cha97]) is the ratio of the depletion

and oxide capacitances of the MOS structure.

The DC value of VBS, which governs Ioff, is thus defined by


IG =R =Roexp( T) (2.3)


where the recombination current IR (for VBS > 0) is represented by the general

forward-bias diode equation [Sze81] with 1 < m < 2 (= 1.3 for the technology in

[Cha97]). For increasing T, both IG and IR in (2.3) increase, but at different rates

depending on the device design. Insight on optimal design as well as on the predicted

temperature dependence of Ioff and AVFB in Fig. 2.2 is obtained by combining (2.3)

with (2.1) and (2.2). Using the basic weak-inversion current relation

Ioff(BTS) oc ni2exp(qW/kT) [Suh95], where Vs (= -0MS/(l+a)= 0.75V) is the surface
potential when VGS = 0, we get


m(1 ++a) kT kT ni(T)
VBs(T) = m +a) vs + ln CI, (M- 1) )ni ) (2.4)
Sl+a-ma I q \q IRO(T)







where C is assumed constant (=qW/(LeffNBExf)). The coefficient in (2.4) is positive

and has only weak dependence on T. The predominant T dependence of VBS is

defined by the In term, the argument of which dictates whether VBS will decrease or

increase with T. Since (M-l) has relatively weak T dependence [Wor98], [Kri96] and

IRO oc ni(3-m)/r is representative [Wor98], [Sze81], we can write:


m(1 + a)
VBS(T, m, IRO) = + )[FT IRO)
l+a-ma
with


rkT ( kT\2 nim- (Ti 3-Tref)r
F(T, m, IRO) = ws(T) + ln C (T (M (n (Tef) (2.5)
q q IRO(Tref) r(Tref)


where Tr is the carrier recombination lifetime and Tref is a reference temperature.

Note that the In argument varies as -trni(m-l). Hence for m low (-1), the ni(T)

dependence is negated and the In argument tends to be less that unity, giving VBS(T)

a negative temperature coefficient. This is the case for the technology in [Cha97] as

implied by the simulations of Fig. 2.2; at IDS = loff, VBS = 0.47V at 270C and it drops

to 0.12V at 1000C. However for m high (-2), the ni(T) dependence undermines the

negative temperature coefficient of VBs(T) and possibly makes it positive. Note

though that decreasing the lifetime Tr, or increasing IRO, makes the In argument

smaller, and hence tends to give a negative temperature coefficient as well as

lowering VBS at a specific T.







2.4 Controlling Floating-Body Effects at the Off-State Condition

This insight afforded in Sec. 2.4 suggests how the FB effect on loff can be

controlled by design. Killing carrier lifetime via defects created by ion implantation

of inert ions has been shown to effectively enhance recombination current in SOI

MOSFETs. Implantation of Ar in the source/drain junction regions [Ohn98], or

implantation of Ge in the channel region [Wei93] and/or in the source/drain regions

[Yos97], which are simple processes that are not incompatible with scaled CMOS

technology, can increase IRO by orders of magnitude. Implantation-induced defects

result in bandgap traps, which lower Tr. The generation lifetime is lowered too, but,

as indicated in (2.1), the increase in IGt is inconsequential. (Junction tunneling, e.g.,

that resulting from halo regions [Che97], can supplement IR at the source, but can

also augment IG at the drain. Its benefit, if any, would depend on the nature of the

forward- and reverse-bias tunneling current components.)

UFSOI-predicted subthreshold characteristics of the device of Fig. 2.2 at

270C for increasing IRO (and IGt accordingly), via lowering tr (and Tg), are shown in

Fig. 2.4; the inset tabulates the decreasing AVFB. For IRO increased by a factor of 100

over its calibrated value (Fig. 2.2), AVFB is reduced to only 91mV; for another order

of magnitude or so of lifetime killing, the FB effect on loff is virtually eliminated.

The increasing IGt, evident in the low-VDS characteristics in Fig. 2.4 at negative VGS,

is innocuous. Furthermore, as indicated by (2.4) and (2.5), the benefit of operation at

higher T is substantively enhanced by the lifetime killing. Predicted AVFB at 850C is

included in the inset of Fig. 2.4. At 850C, with IRO increased by a factor of 100, AVFB










10-3 VDS=1.8V
T=27C


10-5 ROX104 0.05V

10-6 ROx10


10-8 'R AVF (mV) AVF (mV) -
S IROx0 coefficient at 27C at 85C
. 10-9 R

10O 219 105
10-10 IROX10 157 48
1 IsROxl02 91 19
10"11
SIoxl03 35 9
10-12
l-"12 IRoxl04 11 7
10-13 I 1

10-14
-0.5 0.0 0.5 1.0
VGS (V)





Figure 2.4 Predicted IDS-VGS as a function of recombination current.
UFSOI-predicted subthreshold current-voltage characteristics for
increasing thermal recombination (and generation) current in the
nMOSFET of Fig. 2.2. The table inset gives the corresponding AV.
at two temperatures.







(= 19mV) is smaller than the thermal voltage (kT/q = 31mV) and off (= 1.5Ioff(BTS))

is nearly equal to that of the BTS device. (Note that even though the lifetime killing

typically increases m and IRO, the latter increase is predominant in (2.4), ensuring a

negative temperature coefficient for VBs(T), as will be illustrated in Fig. 2.6.)

Recently published data from [Cha98], which employed a high-energy Ar

implantation into the source/drain regions of the MOSFET to intentionally induce

recombination centers in the silicon, corroborate this prediction and our simulation

results, as shown in Fig. 2.5. These data demonstrate a decreasing AVt trend at 270C and

a shift in the temperature coefficient of AVt from positive to negative when Ar (lifetime

killing) is employed.

The predicted sensitivity of VBs(T) to m and IRO is shown in Fig. 2.6(a).

For low m (-1), VBs(T) has a strong negative coefficient, which is reflected by the

simulations of Fig. 2.2, where m=1.3 for the technology in [Cha97]. However, the

negative coefficient of VBs(T) is undermined as m is increased, leading to a

temperature insensitive VBs(T). However, as shown in Fig. 2.6(b) for high m (=2),

increasing IRO tends to restore and enhance the negative coefficient of VBS(T).



2.5 Effects on Performance

The corresponding predicted variations of on-state current (Ion) for the

devices of Fig. 2.2 are depicted in Fig. 2.7. For the FB device at 270C, Ion is only

reduced by 5% when IRO is increased by 100X, as indicated in the table inset. When

T increases to 850C, Ion decreases substantially more for the FB device than the BTS

device; however, the additional loss in drive current is not manifested into a slower












10-2 III I- *-

10.2
10-3 Leff=0.36gm
T=27C VDS=1.V
10"
VT=0.5V
10-5 tox=5.0nm
0.1V
10-6
=L 10-7

10"-8
.- *---* w/o Ar
10-9 0--0 w/ Ar

10-10

10."1 r Ar AVT (mV) AVT (mV)
at 27C at 85C
10-12a No 236 248
10-13 P I Yes 143 122

10-14
-0.5 0.0 0.5 1.0
VGS (V)




Figure 2.5 Measured IDs-VGS with and without Ar I/I.
Measured [Cha98] subthreshold current-voltage characteristics of the
Lef=0.36p.m nMOSFET. The table inset gives the measured AVt at two
temperatures (270C and 850C). The decreasing AVt trend at 27oC and the shift
in the temperature coefficient of AV1 when Ar (lifetime killing) is employed
corroborates the UFSOI model predictions of Fig. 2.4.







1.0

2.0
o- 0.8


S0.6 1
3-a1.3

0 0.4
IRO m=l.0
0.2
(a)

1.0 "
IROx10-2
-0.8 -
IRO

O 0.6 -
\ IROx10


e 0.4
m=2
IROX103
0.2
20 40 60 80 100
Temperature (oC)
(b)

Figure 2.6 Floating-body voltage versus T with m and IR varying.
Predicted sensitivity of the body-source voltage (VBs) to temperature for
variations in (a) ideality factor (m) and (b) recombination current (IRo)
lifetime.











0.8





0.6





0.4





0.2




0
0.0


0.5 1.0 1.5 2.0


VDS (V)


Figure 2.7 Predicted IDs-VDS for T and IR variations.
UFSOI-predicted output current-voltage characteristics for nominal and
100X thermal recombination currents in the nMOSFET of Fig. 2.2 at 270C
and 850C. The table inset gives the corresponding on (VDs=VGS=1.8V).







performance. In fact, the FB circuit performance at 850C (see Fig. 2.8) is faster than

that of the BTS circuit at 270C, which is a consequence of the dynamic threshold in

the FB device. These results undermine the utility of Ion as a figure-of-merit for FB/

SOI technologies. The circuit performances are reflected by the UFSOI/SPICE-

simulated gate propagation delay (TD), plotted in Fig. 2.8 as a function of supply

voltage, of a CMOS inverter ring oscillator with the FB and BTS devices of Fig. 2.7.

For T=270C and VDD=1.8V, TD for the FB circuit is only increased by 4% when IRO

is increased by 100X, and by <2% at VDD=l.0V. Then, raising T to 850C increases

tD of the FB circuit by only 15%, compared to 12% for the BTS circuit. At 850C and

VDD=1.8V, the BTS circuit is 17% slower than the FB circuit with the 100X IRO, and

is 27% slower at VDD=I.OV. These results indicate that the FB device reflected in

Fig. 2.2, with a 100X increase in IRO and operating at 85C, will have an equivalent

Ioff and at least a 15% advantage in circuit speed relative to its BTS, or bulk-Si

counterpart.



2.6 Conclusions

UFSOI/SPICE simulations, calibrated to the scaled PD/SOI CMOS

technology in [Cha97], have been used to gain physical insight concerning the FB

effect on loff, and to note the efficacy of proven lifetime-killing processes, in

conjunction with normal high chip temperature operation, in suppressing the FB

effect. The insight explains why the effect can be naturally ameliorated by operation

at high temperatures that are typical for high-performance circuits. The results

contradict the negative outlook for SOI digital circuits put forth in [Cha97], and

















40



850C

S \30





20

270C


10

1.0 1.2 1.4 1.6 1.8

VDD (V)


Figure 2.8 Predicted RO delay vs. VDD with T and IR variations
Simulated gate-propagation delay of a nine-stage CMOS inverter
ring oscillator comprising the FB and BTS devices in Fig. 2.5 versus
supply voltage; Leffn,p= O.145gm, Wp/WN=32/16, CLOAD=lOfF.







imply that PD/SOI CMOS technology can be optimally designed to be scalable with

low Vt such that its inherent advantages can be exploited in low-power as well as

high-performance digital IC applications. The advantages include not only negligible

source/drain junction capacitance, which as noted in [Cha97] tends to be undermined

in predominantly interconnect-loaded circuits, but others such as the elimination of

the normal body effect (VBS < 0 in nMOSFETs), which is significant in interconnect-

as well as gate-loaded circuits having stacked devices or pass transistors. UFSOI/

SPICE circuit simulations based on the model calibration done herein reveal that on-

state currents are not significantly reduced when loff is controlled as discussed, and

that FB SOI/CMOS IC performance (speed versus power) can indeed be superior to

that of bulk-Si CMOS when the devices are properly designed.












CHAPTER 3
ANALYSIS AND CONTROL OF HYSTERESIS IN PD/SOI CMOS


3.1 Introduction

As ULSI SOI CMOS technologies mature and become more pervasive in

industry, controlling floating-body (FB) effects in partially depleted (PD) SOI

MOSFETs, such as increased off-state current as studied in Chapter 2, is essential for

defining a nominal design center for a technology. Perhaps the most worrisome FB

effect is hysteresis [Suh94], e.g., history-dependent propagation delay, which is due

to the relatively slow carrier recombination/generation processes, indicated in the

device structure in Fig. 3.1, superimposed on the fast body charge dynamics driven

by the intrinsic capacitive coupling. In this chapter, we define a new methodology to

characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits,

including its true worst case, and we provide new insight into the underlying physics.

We use this methodology to explore novel device/circuit designs for controlling

hysteresis. We show that scaling will tend to worsen the hysteretic effects,

necessitating the implementation of specific hysteresis-controlling techniques at

both the device and circuit levels.

The hysteretic delay trends described above are evaluated in a

microprocessor latch-based pipelined circuit to assess timing fail mechanisms and

amenable techniques to control them. By employing a newly described asymmetric












n+-Poly


G
7


tox
j


tOI
tsol


Figure 3.1 Schematic depicting IR and IG charging.
Schematic cross-section of the floating-body PD/SOI nMOSFET indicating the
recombination/generation-defined body charging.


P







SOI CMOS design concept, the hysteresis associated with a given fundamental delay

is shown to be adjusted sufficiently to eliminate the fail mechanism and allow normal

operation of the circuit.


3.2 Fundamental Delays and Methodology

A new methodology is developed to characterize the hysteretic

propagation delay versus time from DC to dynamic steady state. The simulation-

based method utilizes the four fundamental delays obtained from a single-stage

CMOS inverter, a basic building block for higher-order digital circuits, thus

providing the flexibility of analyzing variations in duty cycle and slew rate in any

particular circuit. The four delays, illustrated in Fig. 3.2, are obtained from two

separate initial conditions for the input voltage: 1) DC low-to-high (LH) transition,

and 2) DC high-to-low (HL) transition. The corresponding initial output voltages

define the nMOSFET and pMOSFET initial body charges, which affect the delays.

When VDS is high for a long time, the body is charged, implying fast delays, whereas

VDs=OV implies no body charge and slow delays. The pull-down-fast (a.k.a. as

"first-switch") (tpd-f) and pull-up-slow (a.k.a. as "second-switch") (tpu-s) delays are

obtained from the first and second transitions of the LH input condition, respectively;

and the pull-up-fast (tpu-f) and pull-down-slow (tpd-s) delays are obtained from the

first and second transitions of the HL input condition, respectively. Application-

specific averages of these four fundamental delays define pertinent circuit delays; for

example, as illustrated in Fig. 3.2, the "fast" open-chain average delay (tOC-f = (Tpd-

f + Tpu-f)/2), the "slow" open-chain average delay (TOC-s = (Tpd-s + 'pu-s)/2), and the











VDD


In


In *-

Out --.
Tpu-f Tpd-s


CL


P-- p-


tpd-f tpu-s


Open-Chain Fast Delay:


I-.'


Open-Chain Slow Delay:


JI
I


Ring-Oscillator Delay:


IRO = (TOC-f + TOC-s)/21


Figure 3.2 Definitions of fundamental and average delays.
Schematic representation of the four fundamental and average delays of
floating-body PD/SOI CMOS inverter-based circuits. The arrows depict the
active devices as the waveform propagates down the chain for the first (tOC-f)
and second (ToC-s) transition of the input waveform.


S* OC-f = (rpd-f + pu-f)/2


e ** eOC-s = (tpd-s + pu-s)







(pre-biased) ring-oscillator average delay (RO = (TOC-f + TOC-s)/2), which are the

delays obtained by common measurements.

Possible hysteresis associated with the four fundamental delays and the

three noted average delays, simulated with our physical charge-based device model

(UFSOI/Spice3 [Fos99]) for repetitive input pulsing, is indicated in Fig. 3.3(a) for

the Leff=145nm technology (tox=4.5nm, tsol =150nm, Vt=0.4V @ IDs=100nA*W/L)

in Chapter 2. The corresponding body-to-source voltages for the nMOS (VBsn) and

pMOS (VBsp) devices are shown in Fig. 3.3(b). The body voltages were recorded at

time-points just prior to the input rise and fall transitions, as indicated by the dots

superimposed on the input waveforms in Fig. 3.2. (Note that VBs(t) is virtually

periodic over one period of the input waveform as defined by the capacitance

coupling, but with the average value slowly changing in accord with the net

recombination/generation [Kri98].) The predicted average delays all decrease in time

by 4-7%, with toC-s showing the largest variation. The four fundamental delays show

significantly larger, non-monotonic variations, with a worst case of 9% for tpd-s

occurring prior to the dynamic steady state.

The dynamic threshold voltage (Vt(t)) and the hysteretic propagation

delay in PD/SOI circuits are governed by the transient body voltages in both the

nMOS and pMOS devices, dependent on the input pulse waveform as well as the

electrical properties of the device (e.g., recombination, generation, and capacitive

coupling). The initial DC values of the body voltages are defined by the condition of

equal recombination and generation currents (IR=IG in Fig. 3.1) in the devices. The








29

28

27

26


25

(a) 24
0.5
0.4
s 0.3
S0.2
S0.1
0.0
0.2
0.0
^ -0.2
. -0.4


-0.6
1


(b)


pd-s
pd-f
pu-f
** j> ._ -
^ pV~RU


10-7
Time (s)


10-6


10-5


Figure 3.3 Hysteretic delay and body voltage results of an CMOS inverter.
Simulated floating-body PD/SOI CMOS inverter-based delays showing non-
monotonic hysteresis: a) delay versus time, and b) corresponding nMOSFET
and pMOSFET VBS(t) prior to each input transition. (Leff=145nm, Vt=0.4V,
T=270C, VDD=1.8V, trise-fall=100ps, W/Wn=32/16, CL=85fF, Per=lns, 50%
duty cycle)


)-9







dynamic steady-state body voltages are defined by the condition of equal integrated

IR and IG over one period:


J IG(t)dt = IR(t)dt (3.1)
Per Per


The dynamic steady-state condition (3.1), which typically takes several

microseconds to obtain, implies different (corresponding) body voltages than the DC

condition, and hence reflects hysteresis; but the intermediate transient body voltages

show the complete (and worst-case) hysteresis as evident in Fig. 3.3.



3.3 Dynamic Loading Effect

The non-monotonic hysteretic behavior is manifested by the asymmetry of

the FB charging currents in both devices of the CMOS inverter, due mainly to the

difference of the impact-ionization coefficients for electrons and holes. A newly

recognized dynamic-loading effect is revealed when the pMOSFET body continues

to charge ("strengthen" as IVBsp(t)l increases) subsequent to a dynamic steady-state

condition for the nMOSFET as evident in Fig.3.3(b). It is clear from Fig. 3.3 that,

because of the dynamic loading, the common practice of setting the body voltage to

high and low values to estimate the range of hysteresis will not capture the true

worst-case delay variation in a given technology.

The dynamic-loading effect is a manifestation of the dynamic V, of the

load device on the switching delay of the inverter. For example, in the pull-down

transient, when the nMOSFET current is discharging the output node, it also has to

support the pMOSFET channel current along with the capacitive charging current of







the drain (dQD/dt). As the pMOSFET's Vt(t) is lowered during the pull-down

transient (via gate-body coupling) and previous switching cycles (via body

charging), its channel current becomes larger, which lengthens the pull-down delay

by effectively reducing the nMOSFET drive current that is discharging the node

capacitance. This newly recognized effect can be important for heavy as well as light

loads.



3.4 Dynamic-Gate and Heavy-Loading Effects

To assess if the proposed hysteresis characterization methodology is

generally applicable, two additional loading conditions were evaluated. The first

utilizes a second inverter stage as a representative dynamic load, as shown in Fig

3.4(a) with the hysteretic propagation delay results shown in Fig. 3.4(b). Although

all of the delays are shortened compared to the results of Fig. 3.3 with a static gate

capacitance load, the non-monotonic hysteretic behavior is still present and has

nearly the same delay variation, thus demonstrating the utility of the characterization

methodology.

The second condition is a large load, (e.g., long metal line), as exemplified

in Fig. 3.5(a). The delay results of Fig. 3.5(b) show monotonically decreasing delays,

which demonstrates how the charge dynamics of a large load at the output node can

inhibit the dynamic-loading effect of the load transistor of the CMOS inverter. In this

case, The nodal equation during a pull-down transient is given by






















27 ..el- .....i ...
Tpu-s T=270C

COC-s Z RO
25


1;pd-s
23
Tpd-f

21
10-9 08 01-7 10-6 10-5
Time (s)

(b)

Figure 3.4 Dynamic loading effect on hysteretic delays.
Hysteretic delays for dynamic output node load (replaced static load of Fig. 3.3
with actual gate load of subsequent inverter stage). (Leff=145nm, Vt=0.4V,
T=270C, IR*100, VDD=1.8V, rise=Tfal=100ps, WpWIn=32/16, Per=Ins, 50%
duty cycle)














CL*10


(a)


104 -

102

100

98

96

94

10-9


10-8 10-7 10-6


Time (s)

(b)


Figure 3.5 Heavy loading effect on hysteretic delays.
Hysteretic delays for large output node load (replaced static load of Fig. 3.3
with a large load (e.g., long metal line). (Leff=145nm, Vt=0.4V, T=270C,
IR*100, VDD=1.8V, 'risei-fal=100ps, WpWn=32/16, Per=lns, 50% duty
cycle)




35


In(t) = DQDp + CLd (3.2)


where In(t) is the drive current of the nMOSFET. Since the capacitive load is very

large, the transient voltage across the load decreases slowly making the output node

voltage (Vout(t)) maintain its pre-switch value for a longer time prior to its decrease.

This constrains the build-up of VDS across the load device during the tranient and

thus suppresses the influence of the increased load current (e.g., for the pMOSFET:

Ip(t)+dQDp/dt) due to the dynamic-loading effect, sufficiently such that the non-

monotonic behavior of Figs. 3.2 and 3.3 is not present.



3.5 Integrity of the Dynamic Steady-State Results

At the dynamic steady-state (DSS) condition of (3.1) for a CMOS inverter,

the pull-up (Tpu-f. rpu-s) and pull-down (tpd-f. rpd-s) fundamental delays must be equal

(to within a given tolerance), as in Figs. 3.3-3.5. If the delays do not merge at the

DSS condition, the predicted results may be unreliable, due to numerical instabilities

such as truncation error or charge non-conservation [Kun95]. Empirical (especially

capacitance-based) compact models are more vulnerable to these instabilities, and

the inherent complex dynamics of PD/SOI technologies necessitate the use a physical

charge-based model such as the UFSOI compact device model [Fos99].



3.6 Does Controlled Off-State Current Imply Hysteresis Control?

When the Ioffcontrolling techniques of Chapter 2, i.e., increasing the

recombination (and thermal generation) rate by 100x and temperature from 250C to







850C, are checked for hysteresis control, the non-monotonic behavior is eliminated,

but o0C-s, tpd-s, and tpu-s all show, in Fig. 3.6, worsened hysteresis. These delays,

along with TRO, show a shift from decreasing delays to increasing delays, due to the

discharging or dynamic weakening of the active device. The hysteresis of the "fast"

delays (Too-f, rpd-f,' pu-f) remains about the same. All of the delays are longer

because of the higher temperature (reduced mobility), but the initial "fast" delays

have been lengthened the most because of the suppression of VBS in both devices at

the DC condition (t=0) due to the higher recombination rates. In time, the "fast"

delays shorten due mainly to the discharging of the load device. This dynamic

weakening of the load device is due to the net recombination that occurs each cycle,

in contrast to the net generation (via impact ionization) each cycle reflected by Fig.

3.3. For rpu-f, VBS of the nMOSFET load becomes increasingly negative in time. For

tpd-f, VBS of the pMOSFET load becomes increasingly positive in time. These results

suggest that an "intermediate" design point could be achieved which is void of

hysteresis for tRO and the "slow" delays.



3.7 Correlation to Measurements

Recent measured data [Ass96], [Hou98], though limited to only the

average delays, show dynamic steady-state delays that increase, relative to the initial

delay, as the input pulse period decreases (increasing frequency). Contrarily,

simulations [Gau95], [Wei98] of such hysteresis typically predict that the steady-

state delays decrease as indicated in Fig. 3.3. This discrepancy in hysteretic trends

can be explained via measurement uncertainties (voltage supply collapse, self-













34



32



S30



28



26
11


10-5


10-'
Time (s)


Figure 3.6 Increased T and IR effects on hysteretic delays.
Hysteretic delays for higher recombination rates and elevated temperature,
relative to those in Fig. 3.3. (Leff=145nm, Vt=0.4V, T=85C, IR*100,
VDD=1.8V, nrise=Tfall=100ps, W/Wn=32/16, CL=85fF, Per=Ins, 50% duty
cycle)







heating) and device technology differences, as suggested and Fig. 3.6 and by Fig.

3.7. The FB dynamics which underlie the hysteresis in circuits can be influenced by

the ratio of the gate-to-body capacitance (CGB) to the drain-to-body capacitance

(CDB) [Pel97], [Kri98] and by the unbalanced body charging rates of the nMOS and

pMOS devices, as exemplified in Fig. 3.7 where predicted Toc-f for thinner tsoI is

contrasted to that for tsoi=150nm as in Fig. 3.3. The results show that early in time

the smaller CDB (.tsoI) enables more gate-to-body capacitive coupling, enhancing

the current-overshoot effect, which significantly shortens TOC-f. Later in time the

dynamic strengthening of the load device lengthens TOC-f. These results demonstrate

that the hysteretic delay can be made to either increase or decrease in time by altering

the SOI film thickness (changing CDB), and by changing CGB (e.g., varying L) too.



3.8 Scaling

As the voltage supply is scaled from 1.8V to 1.2V, the worst-case

hysteretic delay variation increases significantly from 9 to 17%, as shown in Fig. 3.8.

When the device technology (tox, tsoI, etc.) is also scaled to Leff=70nm at 1.2V in

accord with the SIA ITRS [SIA99], as detailed in Chapter 4, a delay hysteresis of

12% is predicted, as shown in Fig. 3.9. The increased CGB/CDB ratio of the scaled

technology helps to suppress the hysteresis somewhat. These results suggest that as

PD/SOI technologies are scaled, hysteresis will tend to worsen, mainly because AVt

(the dynamic threshold due to hysteresis) cannot be scaled while VDD is reduced, and

hence will become more significant in the delay equation: t = 1/[(VDD/2)- IVTI 2

Also, a slower slew rate (rise/fall time) enhances the associated hysteresis, due to














27.0
tsol = 150nm
S 26.5

CO
S26.0


25.5

4-o 100nm
25.0 OOnm

2 4 .5 .. .. ..... ..... ,
10-9 10"8 10-7 10"-6
Time (s)





Figure 3.7 Sensitivity of film thickness on hysteretic delay.
Modified fast open-chain delay for a thinner SOI film thickness, relative to that
in Fig. 3.3. (Leff=145nm, Vt=0.4V, T=27C, VDD=1.8V, *rise=tfall= 00ps, Wp/
Wn=32/16, CL=85fF, Per=lns, 50% duty cycle)











40 .

OC-f pu-------f
38 Ipu-s -
OC-s .

TRO Zpd-
' 36
pd-

I 34


32


30 .-
10-9 10'8 10-7 10-6 10-5
Time (s)






Figure 3.8 Effect of lower VDD on hysteretic delays.
Hysteretic delays for reduced supply voltage, relative to those in Fig. 3.3.
(Leff=145nm, Vt=0.4V, T=270C, VDD=1.2V, rise-fall= 100pS, Wp/Wn=32/16,
CL=85fF, Per=Ins, 50% duty cycle)












328 .
TpU-f
------------^pu-
TOC-s pu-
30
T Cb-f
1 RO pd-s

o28.
p pd-f


26
S248 ----------------* -^ \\* -




10-9 10"8 10-7 10-6 10-5
Time (s)






Figure 3.9 Scaled technology effects on the hysteretic delays.
Hysteretic delays for scaled technology, relative to those in Fig. 3.3.
(Leff=70nm, tox=2.5nm, tsoi=100nm, Vt=0.4V, T=270C, VDD=1.2V,
Trise=fall=100ps, WpAWn=32/16, CL=85fF, Per=lns, 50% duty cycle)







increased impact-ionization charging of the body during the lenghtened transition

period when both nMOS and pMOS devices conduct current [Pel99a].



3.9 Control of Hysteresis: Asymmetric SOI CMOS

Results of applying hysteresis-controlling techniques to the technology of

Fig. 3.3 are shown in Fig. 3.10. By thinning tsoI from 150nm to 100nm (case "A")

as demonstrated in Fig. 3.7, in both nMOS and pMOS device structures, the

hysteresis of the average delay Toc-f is made to increase in time, suggesting that a

null-hysteresis design can be achieved for Toc-f. Because the adjustments in tsoI are

typically limited (PD neutral region design, S/D resistance, and thickness control),

to suppress the hysteresis associated with TOC-f, we propose an asymmetric SOI

CMOS design concept that adjusts key device/structure parameters of the pMOSFET

while maintaining the original nMOSFET design (or vice versa). This allows a

decoupling of the device structures so that the nMOSFET can be designed to fully

exploit the benefits of SOI, while the pMOSFET can be utilized to control hysteresis.

This is demonstrated by cases "B" and "C" in Fig. 3.10. By additionally increasing

the junction recombination current (100x) of the pMOSFET, a virtual null-hysteresis

for Toc-f is achieved, as shown by case "B." By additionally increasing the halo and/

or retrograde (NBH) doping density (5x) of the pMOSFET, which decreases the CGB/

CDB ratio and reduces the current overshoot caused by the gate-body coupling, the

toc-f delay is now shown to decrease in time, as shown by case "C." These

asymmetric device adjustments demonstrate that the rOC-f delay can be designed to

either increase, decrease, or remain the same in time. However, the TOC-s delays for












30

29

28

a 27




25


241
10-9


10-5


10-8 10-7 10-6
Time (s)


Figure 3.10 Techniques to control hysteresis.
Controlled hysteretic delays, relative to those in Fig. 3.3; SOI film thickness
("A", "B", and "C"), recombination rates ("B" and "C"), and halo doping
density ("C") have been modified. (Leff=145nm, tox=4.5nm, tsol=100nm,
Vt=0.4V, T=270C, VDD=1.8V, rise--fall=100ps, WpWn=32/16, CL=85fF,
Per=lns, 50% duty cycle)







cases "A" and "B" show a marked increase in hysteresis, which may be problematic

in some circuit designs. By utilizing case "C," a closer balance of hysteresis is

achieved for the TOC-f and roc-s delays. The hysteresis for both delays of case "C" is

less than 5%.



3.10 Circuit Application

The problematic nature of hysteresis is exemplified via simulation of a

microprocessor circuit in Fig. 3.11 which depicts an early-mode (or race)

feedthrough timing fail mechanism. The circuit is a latch-based pipelined clocked

system, which has input and output latches (captures the data at each stage at the end

of each clock cycle) separated by a logic block. When data DO of Fig. 3.11(a) goes

to a high ("1") level, with the clock at a high level, the data will propagate through

the first latch (which includes a complementary pass gate) and subsequently through

the logic gates within one clock cycle. A timing issue arises if the setup time,

minimized for chip-performance reasons, is too short and allows the data from the

first cycle to propagate through to the second latch within one clock cycle. If the

delay of the first latch and logic gates decreases in time (hysteresis), it will

compromise the setup timing design and lead to a feedthrough fail, as shown in the

UFSOI/SPICE simulation results of Fig. 3.11(b). During the first cycle (with no

hysteresis), the inverted signal of data Dl (D2) does not propagate through to the

second latch, as indicated by the high logic level of D3 at time equal to -Ins, and

thus passes the timing condition. However, subsequent to many cycles at time equal

to -l1is, data D3 is shown to change (flip) its logic state to a low level, since the













DO I ID1l ID21 D3

SClock t Clock

Clk Clk

1--
CIk Cik
LClk Clk

DO D1 D2 D3
TClk TClk

(a)

2.0 ..


rw Ij O3I
DO Fail

o Pass
0.5
D : 1o Clock D3
0.0 i .LL I`9* K
0 0.5e-9 1.0e-9 .e- 9.995e-07 1.0e-06
Time (s)
(b)
Figure 3.11 FB PD/SOI CMOS microprocessor simulation.
(a) Latch-based pipeline clocked system. (b) Dependent on the hysteresis, the
second (invalid-data) transition of the data signal DO could be propagated
(fail) or not (pass) through the second latch before the clock closes; an early-
mode (or race) feedthrough fail is predicted. (Leff=145nm, T=270C,
VDD=1.8V; Logic: Wp/Wn= 4/2.4; Pass Gate: WpWn= 0.4/0.4)







second latch did not close before the next data signal approached. This timing failure

is due to the delay speedup from the associated hysteresis of the prior latch and logic

block.

To eliminate this fail mechanism, the setup time should include the worst-

case hysteresis expected, or a technology adjustment could be employed utilizing the

insight gained from the proposed fundamental delay-based methodology and the

asymmetric SOI CMOS design concept. The pertinent hysteretic delay for the given

application is tpd-s of Fig. 3.3, which decreases by 7% at lips because of nMOSFET

charging.

By employing an increased IR for only the nMOSFET, simulations of Fig.

3.12 show that the hysteresis is effectively suppressed and the noted feedthrough fail

is eliminated without significant loss of performance. Alternatively, a decreased IR

for the pMOSFET would control this hysteresis effect as well. Fig. 3.12 exemplifies

the effects of increasing IR only in the nMOSFET and decreasing IR only in the

pMOSFET on the 'pd-s of Fig. 3.3. The results show a successful suppression of

At(tnom tmin) by either asymmetrical design technique. The weakened nMOSFET

(increased IRn by lOx) design reduced the worst-case AS from 9% for the nominal

design to 5%. If IRn is increased by 100x, AT decreased further to only 2%.

Alternatively, if the pMOSFET is strengthened by reducing IRp, the worst-case At is

also reduced to only 5%. Thus, both of these asymmetric design techniques will

suppress the hysteresis of the Tpd-s delay and restore the pass condition for the

microprocessor latch circuit application. Other asymmetric designs, e.g., those

suggested by Fig. 3.10, could also be considered in this application. If the transition











29 ...... .. .
Lefn=145nm T=270C
VDD=1.8V
28


E427
.......................... IRp*0.01 Rn*100





S26 Rn*10


25 ~"Nominal"



10-9 10-8 10-7 106 10-5
Time (s)





Figure 3.12 Suppressing hysteresis to prevent microprocessor fails.
Modified floating-body PD/SOI CMOS fundamental Tpd-s delay for
increased nMOSFET recombination currents (IRn) and decreased pMOSFET
IRp current, relative to the nominal Tpd-s of Fig. 3.3 depicting the suppression
of At by employing the asymmetric SOI CMOS design concept. (Leff= 145nm,
Vt=0.4V, T=270C, VDD=1.8V, ise-Tfal=100ps, Wp/Wn=32/16, CL=85fF,
Per=Ins, 50% duty cycle)







of data DO is flipped, the pertinent hysteretic delay would be tpu-s, and its associated

feedthrough fail could also be resolved by these asymmetric designs.



3.11 Summary

The fundamental delays of a PD/SOI CMOS inverter have been defined

along with a new methodology to properly analyze hysteresis. Our analysis revealed

the possibility of a non-monotonic hysteretic delay caused by a dynamic loading

effect that is due to the imbalance of the impact-ionization rates of the electrons and

holes in the nMOS and pMOS devices. Hysteresis can be suppressed via the same

controlling techniques for Ioff, but not generally. An increasing or decreasing

hysteretic delay was demonstrated by physically adjusting the CGB/CDB ratio

(resolving an open discrepancy between simulations and measurements). Hysteresis

will tend to worsen as the technology is scaled, due mainly to the non-scaling of Vt.

However, a new asymmetric SOI CMOS design concept was proposed to generally

suppress and control hysteresis per specific applications within a given technology,

while retaining the benefits of SOI.












CHAPTER 4
PERFORMANCE ADVANTAGE OF PD/SOI WITH FLOATING BODIES


4.1 Introduction

The floating-body (FB) partially depleted (PD) silicon-on-insulator (SOI)

CMOS technology potentially offers superior performance/power relative to its bulk-

Si counterpart. The PD/SOI advantage is due in part to FB effects [Kri98], which,

however, can lead to device and circuit instabilities, especially in dynamic logic and

memory circuits as described in Chapter 3. These problematic FB effects are

manifested in both the static (e.g., kink effect, single-transistor latch, premature

drain-source breakdown) [Col97], [Cri95] and dynamic (e.g., transient threshold

voltages, capacitive coupling, drain current overshoot/undershoot, hysteretic

memory effects, transient parasitic bipolar leakage effects) [Suh94], [Gau95],

[PeI96], [Pe197], [Gau97], [Wei98] operation of the devices and circuits. (Fully

depleted SOI CMOS devices tend to suppress the FB effects, but their scalability is

limited by pragmatic, finite Si-film and buried-oxide thicknesses [Yeh95].)

Recent demonstrations of SOI microprocessors [Buc20]] reveal that the

detrimental FB effects of a PD/SOI technology can be suppressed enough via device

and circuit modifications [Can99], [A1199] to achieve a viable ULSI high-

performance processor technology. However, it has recently been suggested that the

10-30% improvement in performance over the bulk-Si counterpart will diminish as







the technologies are scaled to 150nm (effective channel length) [Cha97] and below

[Mis20].

The aim of this chapter, based on physical device/circuit simulations, is to

quantify the performance benefits of the FB PD/SOI CMOS technology over its bulk-

Si counterpart using a newly developed unified UFSOI model capability, provide

insight into the physical mechanisms underlying the benefits, and to assess these

benefits as the technology is scaled, noting the need for device/circuit design

optimization to control and exploit the FB effects. The study begins with simulations

of a static CMOS-inverter ring oscillator from the contemporary 145nm (effective

channel length), 1.8V FB PD/SOI technology of Chapter 2, the speed of which is

predicted to be more than 25% faster than that of its bulk-Si counterpart. This

advantage is shown to be due mainly to the dynamic capacitive coupling of the

floating body to the gate and drain, which often has been ignored (relative to the kink

effect) in previous explanations of the SOI advantage. However, in accord with the

suggestion in [Cha97], this coupling is shown to diminish as the technology is scaled

(Leff--70nm, VDD--+1.2V), mainly because of the reduced power-supply voltage.

Additional simulations reveal though that this potential loss of the SOI advantage can

be mitigated via design optimization (increased recombination current) as well as

operation at typically elevated ambient temperatures. Moreover, the suppression of

the body-bias effects in stacked-transistor (e.g., NAND) circuits is shown, in accord

with [A1199], to provide a significant advantage for SOI technologies over equivalent

bulk-Si technologies, even as the technology is scaled, providing an additional 5-

25% performance benefit.







4.2 Unified Model for PD/SOI and Bulk-Si MOSFETs

In order to properly evaluate and benchmark both FB SOI and bulk-Si

technologies at the same technology node, the UFSOI model formalism for PD/SOI

[Fos99] was extended creating a new unified capability (UFSOI/PD-B) to enable a

bulk-Si counterpart structure to be simulated with exactly the same device design

assumptions as the PD/SOI technology. This new unified capability allows direct

performance comparisons of the two technologies without ambiguities in device

design and structure, and enables reliable benchmarking of scaled technologies

projected in the SIA International Technology Roadmap for Semiconductors (ITRS)

[SIA99]. This unique feature is facilitated in UFSOI by its process-based physical

model formalism, e.g., a MOS theory-based source/drain-substrate capacitance that

simplifies to source/drain-body depletion capacitance when the buried oxide is

theoretically thinned to -0 and the back-gate/substrate and body terminals are

merged.

The new bulk-Si feature is activated by changing a UFSOI/PD-B model

flag (NFDMOD=2) and updating the substrate doping density (NSUB) to reflect an

equivalent well doping. To obtain the correct junction recombination current for the

bulk-Si counterpart technology, which must include the areal as well as the sidewall

components, the following adjustment to the model parameter JRO [Fos99] can be

made:


JROi= J (41)
JRObulk Si= JROsoIl 1 + (4.1)
tsoI X W)







where Aj is the source/drain areal junction area, tsoI is the SOI film thickness, and

W is the width of the MOSFET.

The results of this new unified model capability are exemplified in Fig. 4.1

where the predicted IDS-VGS and IDS-VDs characteristics of an Leff=70nm FB PD/

SOI nMOSFET and its bulk-Si counterpart (with NFDMOD=2, NSUB=NWELL) are

shown. The discernible FB effects, e.g., the strong-inversion and subthreshold kink

effects, the enhanced Ion, the increased Ioff, the lower Vt(sat), and the degraded drain/

output conductance are all evident.

In UFSOI/PD-B, the source/drain-substrate capacitance is characterized

by modeling the MOS substrate depletion charge under the source/drain region

[Yeh95]. In essence, the capacitance (per source/drain area) is a series combination

of the buried oxide capacitance (CBox) and the depletion-layer capacitance of the

substrate (Csub):


1 1 1 1
+ (4.2)
CS/D Csub BOX


where CBOX=EOX /tBOX and Csub=Es /Wdepl. The depletion width (Wdepl) in the

substrate is a function of the surface potential (Vs-sub) below the BOX, under the

source/drain regions, and is modeled by the depletion approximation dependent on

the source/drain-to-substrate voltage (Vs/D-sub). For tBOX ~-0, CBOX >> Csub,and


1 1 1
c 1 (4.3)
S/D Csub j -areal







1.0
0.9 PD/SOI
------ bulk-Si
0.8

0.7 VGS=0.3 1.5V
5 0.6


0.4
0.3
0.2
0.1
0.0
0.0 0.5 1.0 1.5
VDs (V)

(a)
10-2 .
10 PD/SOI ------------
10-4 ...... bulk-Si ...
10-5
10-6 VDS=0.05 1.5V
10 -7
10-8
-10 -97
10.io i0. ... ,
10-11
10-11

10"1 -.... ,

-1. -0.5 0.0 0.5 1.0 1.5
VGS (V)
(b)
Figure 4.1 PD/SOI and bulk-Si IDS-VDS, IDS-VGS predicted by UFSOI/PD-B.
The predicted I-V characteristics for a Leff70nm nMOSFET at 270C
exemplifying the utility of the new unified UFSOI/PD-B model.







where Cj-areal is the areal component of the source/drain junction capacitance (per

source/drain area), now modeled physically when the substrate doping density is set

to the well doping density.



4.3 Performance Benefits of Contemporary SOI

4.3.1 Modeling and DC Characteristics

Device and circuit simulations are done using the unified process-based

UFSOI/PD-B MOSFET model. Because the model parameters relate directly to

device structure and physics, the simulation results are representative and predictive

of important trends. UFSOI-predicted subthreshold IDS-VGS device characteristics,

at room temperature (T=270C), of the minimum-Leff (11Onm) condition for the

contemporary VDD=1.8V, Leff=145nm PD/SOI technology of Chapters 2 and 3 are

shown in Fig. 4.2. The gate oxide thickness (tox) is 4.5nm; Vt(linear)=0.4V@

IDS=100nA*W/L; the buried oxide thickness (tBox) is 400nm; and the Si-film

thickness (tsol) is 150nm. The bulk-Si counterpart technology, also portrayed in Fig.

4.2, is defined by identical processing as the SOI technology with its well doping at

1017cm"3. Superimposed in Fig. 4.2 too are the body-tied-to-source (BTS) results for

the FB PD/SOI devices, which indicate the minimum off-state (VGS=OV) leakage

current (Ioff) that can be achieved if there is no enhancement of IDS due to the DC

floating-body (subthreshold-kink) effect. Also in Fig. 4.2 are the characteristics of

the FB PD/SOI devices with threshold voltages (Vt) increased via channel-doping

adjustments to achieve an Ioff equal to that of the BTS/SOI and bulk-Si devices

[Cha97]. The Vt for the nMOSFET and Vtp for the pMOSFET were increased by





















10-5




10-6




10-7 Leff (min)=110nm FB/SOI
tox = 4.5nm ---. FB-VV/SOI
VDS=1.8V BTS/SOI, bulk-Si
T= 270C
10-8

pMOSFET nMOSFET

10j-9 ..1
-1.8 -0.9 0.0 0.9 1.8
VGS V)


Figure 4.2 Predicted IDS-VGS for SOI and bulk-Si 145nm technologies.
UFSOI-predicted subthreshold current-voltage characteristics of the minimum
devices (Leff=110nm) for 145nm Leff SOI nMOSFET and pMOSFET
technologies including: FB/SOI, FB-V/SOI, BTS/SOI(bulk-si equivalent DC
characteristics); tox=4.5nm, tsoi=150nm, Vt(linear)=0.4V@TIDS=10nA*W/L,
T=270C.







143mV and 141mV, respectively. The drive currents (Ion) at VDD = 1.8V (without

self-heating) for the nMOSFETs/pMOSFETs are 0.74/0.35 mA/pm for FB-SOI,

0.69/0.325 mA/p.m for FB-Vt/SOI, and 0.59/0.3 mA/p.m for BTS-SOI/bulk-Si. Table

4.1 summarizes Ioff and Ion for the minimum-Leff devices of each technology.



Table 4.1 Comparison of Ion and loff for the nominal Leff=145nm MOSFET devices
at the minimum Leff condition

Leff=110nm (min) FB/SOI FB-Vt/SOI BTS/SOI bulk-Si
VDD=1.8V,
T=270C nMOS pMOS nMOS pMOS nMOS pMOS nMOS pMOS
Ion (mA/.m) 0.74 0.35 0.69 0.325 0.59 0.3 0.59 0.3
Iff (nA/Lm) 690 36 3 1 3 1 3 1


4.3.2 Performance Comparison

With reference to the hysteretic delay-analysis methodology described in

Chapter 3, the predicted ring-oscillator (fanout=1) propagation delay (tRO) at

T=270C for the four technologies described above are shown, varying in time, in Fig.

4.2. The device layouts assume a 6X-based ground rule for the source/drain contact

lengths, with X equal to Lgate/2.0 (Lgate=195nm). UFSOI simulations predict the

performance benefit to the dynamic steady-state TRO (SSRo) to be 29% for the FB/

SOI technology over bulk-Si counterpart. However, the FB/SOI technology has an

excessive Ioff, as indicated in Table 4.1, and requires loff-controlling techniques as

suggested in Chapter 2 and [Fos98], [Ohn98], [Wei93], [Yos97], [Che97], [Hor96],

[Che96] to maintain reasonable chip power and SRAM functionality. Alternatively,

increasing Vt of the FB/SOI technology (which yields FB-Vt/SOI) to get loff equal to
















35
Junction Capacitance
Benefit
BTS/SOI
33

Kink effect
.Benefit

as 31
SVDD=1.8V
Lefr (nom)=145nm
T=27C

29 Coupling effect
Benefit

FB-Vt/SOI

27
^27 ^ FB/SOI



10-9 10-8 10-7 10-6 10-5
Time (s)



Figure 4.3 Predicted delay for SOI and bulk-Si 145nm technologies.
UFSOI-predicted TRO propagation delay for the 145nm Leff technologies
(Lgate=195nm, tox=4.5nm, Vt(linear)=0.4V@IDS=100nA*W/L, T=270C, VDD=
1.8V, Trisetfall=O00ps, Wp/Wn=32/16, LS/D=6k G/R.)







that of bulk-Si still yields a 23% TSSRO performance benefit over the bulk-Si

technology. The predicted TsSRO delays and accompanying history-dependent

propagation-delay (hysteresis) results are summarized for the above technologies in

Table 4.2.



Table 4.2 Predicted steady-state delay and hysteresis results for the four Leff= 145nm
technologies.

Leff= 145nm (nom)
VDD=1.8V, T=270C FB/SOI FB-Vt/SOI BTS/SOI bulk-Si
tSSRO (ps) 25.5 27.5 33 35.7
SOI Benefit over bulk-Si 28.6% 23% 7.6% --%
TRO Hysteresis (ATRo/'RO) 4.5% 7.1% -% --%


4.3.3 Hysteresis Effect

Hysteresis is reflected by the relative change of a specific delay as a

function of time from its initial delay (riD) to its steady-state delay (rSSD), computed

by ('D-T SSD)/ iD. The hysteresis of tRO for the FB-Vt/SOI technology increases to

7.1% from 4.5% for the nominal FB/SOI technology as noted in Table 4.2 and as can

be seen in Fig. 4.3. This increase reflects the wider variation of body voltage over

time, AVBS {initial VBS (ViBs) relative to the steady-state VBS (VSSBS)}.

To gain additional insight regarding the impact of the increased Vt of the

FB-Vt/SOI technology, Fig. 4.4 shows the VBs(t) during the first switching cycle for

the nMOSFET and pMOSFET devices of an inverter circuit. Figs. 4.4(a) and (b)

reveal the VBs(t) behavior for the low-to-high (LH) input signal case, while Figs.

4.4(c) and (d) depict the VBs(t) behavior for the high-to-low (HL) input signal case.














0.4

0.3

0.2

0.1

0.0


-0.1 t I I I ,
-0.5 0 0.5 1 1.5


0.4 v

0.3

0.2

0.1

0.0

-0.1 -
-0.5


0 0.5 1 1.5


(a)


0 0.5
Time (ns)


0.0

-0.1

-0.2

-0.3

-0.4


I 1a. -0.5 0-
1 1.5 -0.5


0 0.5
Time (ns)


Figure 4.4 VBS vs. time for nominal and increased Vt FB/SOI technologies.
UFSOI-predicted VBS(t) for the nominal FB/SOI and FB-Vt/SOI 145nm Leff
technologies. Lgate=195nm, tox=4.5nm, V(linear)=0.4V@ IDS=100nA*W/L,
T=270C, VDD= 1.8V, Trise/fail=100ps, Wp/Wn=32/16, LS/D =6A G/R.


0.0

-0.1

c0.2

-0.3

-0.4


-0.5 1
-0.5


1 1.5







Also, superimposed on Fig. 4.4 are the corresponding fundamental delays and an

indication of what mode (active or load) the device is operating in during each input

switching event.

As shown in Fig. 4.4(a), increasing Vt (FB-Vt/SOI) results in V'BS

dropping from 0.36V to 0.24V, while the VssBS remains about the same. The decrease

in V'BS is due to the reduced impact-ionization current (IGi), driven by the channel

current, in the off-state condition where IR(VBS) = IGi, as described in Chapter 2. The

VSSBS, defined by the dynamic steady-state condition in (3.1), remains unchanged

since the (dynamic) Ion for both technologies is nearly the same.



4.4 Performance Insights

4.4.1 Delay Benefit from Junction Capacitance

With reference to Fig. 4.3 and Table 4.2, if the bodies of the FB/SOI

devices are tied to the sources (BTS/SOI), yielding loff equal to that of the bulk-Si

devices, the TsSRO performance benefit is reduced to 7.6%. This result reflects the

benefit of the reduced SOI source/drain junction capacitance afforded by the thick

tBOX. The rest of the previously noted tRO performance benefit is due to the FB

effects described as follows.


4.4.2 Delay Benefit from the Kink Effect

To distinguish the FB delay benefit of the subthresholdd) kink effect (i.e.,

a Vt lowering due to impact-ionization charging of the body) versus that of the

capacitive-coupling effects, the two input conditions defined in Chapter 3 were

simulated with the body voltages (VBs) of their devices fixed to the initial DC levels.







For the low-to-high (LH) input condition, the pull-down "fast" or "first-switch" ('pd-

f) and pull-up "slow" or "second-swicth" (rpu-s) fundamental inverter delays of Fig.

3.2 are derived with the body voltages of the devices tied to their initial DC values

(VBSn=0.36V and VBSp=OV) defined by the input-low simulation. Similarly, for the

high-to-low (HL) input condition, the pull-up "fast" or "first-switch" (tpu-f) and

pull-down "slow" or "second-swicth" (Tpd-s) fundamental inverter delays are

obtained with the body voltages of the devices tied to their initial DC values

(VBSn=0V and VBSp= -0.23V) defined by the input-high simulation. Then, the initial

TRO ('iRO) without the capacitive-coupling effect can be computed from these

fundamental delays: 'iRO = ('ipd-f+ ipu-s + ipuf + ipd-s)/4. The results, as depicted

in Fig. 4.3, indicate that the FB/SOI performance benefit from the kink effect is only

5.0% of the total 25% T'RO benefit.

This result contradicts the Ion improvement (20%) from the DC kink effect

for the nMOSFET and is due to the relatively long time ( -1 As) required to

fully charge the body via impact ionization as compared to the fast VGS(t) input

switching signal [Jen96], [Wei95]. For fast input rise times, the total generation

current (IG= IGi+IGt+IGtun) first supports the transient body-charging current (dQB/

dt) prior to it significantly influencing IR (or VBs(t)), which can be expressed as

dQe
I dt (1)

where

(qVs)
IR cc exp M ) (2)


and







dQB d d d d
-= C BSt DVBS) + CCBDBG V(V) + CCBGb VBGb) (3)
dt dt

Thus, for fast slew rates, the full performance benefit of the DC kink-effect

enhancement of Ion is not realized. For slow slew rates, IG can more directly affect

IR since dQB/dt is small, and the benefit can be realized. Changes to the slew rate will

thus significantly affect the propagation delay and their hysteretic behavior [Pel99a];

an increase in the slew rate will increase both the propagation delay and the

accompanying hysteresis. Note that if VBs(t=O)=OV, the device will not acquire any

significant performance benefit from the kink effect until IG becomes significantly

greater than dQB/dt during subsequent switching events.


4.4.3 Delay Benefit from the Capacitive-Coupling Effect

The remaining 12% of the T'RO performance improvement as indicated in

Fig. 4.3 can be attributed to the capacitive-coupling effects, which strongly influence

VBS(t) and the dynamic Vt in two ways. The first is the classical current-overshoot

effect [Lim84], which improves the fast delays (tpd-f. tpu-f) by increasing IVBS(t)I

(lowering the dynamic Vt) via gate-to-body coupling during the first and subsequent

odd transitions of the input signal. The second is the dynamic loading effect as

described in Chapter 3, which improves the slow delays (tpd-s, 'pu-s) by decreasing

IVBs(t)l (raising the dynamic Vt) of the load device via drain-to-hody coupling

during the second and subsequent even transitions of the input signal. As shown in

Fig. 4.4(a), the capacitive coupling of the drain to body, subsequent to the pull-down

of the output voltage, pulls VBSn lower prior to the pull-up transition of the output

voltage. This beneficial coupling weakens the drive current of the nMOSFET and







thus provides a smaller load for the active pMOSFET when it pulls up the output

voltage. At the same time, as shown in Fig. 4.4(b), the gate-to-body capacitive

coupling induces a VBSp overshoot in the pMOSFET that helps strengthen its drive

current prior to the output pull-up transition, also enhancing this performance

benefit.


4.4.4 Body-Voltage Dynamics and Increased Threshold Voltage

The TRO delay, defined by the fundamental delays (Tpd-f, Cpu-s, rpu-f, tpd-s)

as discussed in Chapter 3, strongly depends on the behavior of the VBS as a function

of time, shown in Fig. 4.4. The initial VBSn for this fundamental delay is established

at the DC condition of equal recombination and generation currents (IR=IG) and

subsequently pulled higher by the gate-to-body coupling (overshoot) prior to the

formation of the inversion region (VGS < Vtn). When VGS > Vtn, the inversion layer

forms and inhibits the gate-to-body coupling; VBSn then follows the drain (output)

voltage lower via the drain-to-body capacitive coupling. Concurrently, the VBSp of

the pMOSFET load is first coupled higher from the gate-to-drain Miller capacitance,

since the inversion layer screens the direct gate-to-body coupling, and then follows

the drain voltage lower (increasingly negative) until IVGSI < IVipl. The dynamic-

capacitive coupling mechanisms described above all contribute positively to improve

the fundamental delays, which translates into an improved TRO speed performance

for the FB/SOI technology.

If we now consider the 'pu.s delay for the second switching transition of

the LH case when VGS returns to its low voltage level, the VBSp of the active

pMOSFET is first coupled to increasing negative voltages via the gate-to-body







coupling (overshoot), since IVGsI < IVtpl and the inversion layer is not formed. Then,

when IVGsl > IV,pl the inversion layer forms and VBSp follows the drain higher

(decreasing negative voltages) via the drain-to-body coupling, which "weakens" the

pMOSFET for the next input transition when it becomes the load device for the pull-

down condition. Concurrently, for the tpu.s delay, the VBSn of the nMOSFET is first

coupled lower via the gate-to-drain Miller capacitance and the drain-to-body

coupling, since the channel inversion layer is present, and then follows the drain to

a higher voltage level, until VGS < Vtn. The VBS(t) behavior of the tpu-f and tpd.s

delays can be similarly described for the HL input transitions, as depicted in Figs.

4.4(c) and 4.4(d).

As described previously, the VBs(t) results for the increased-Vt FB/SOI

(FB-Vt/SOI) technology are shown in Fig. 4.4 superimposed on the nominal FB/SOI

results. The initial VBSn is lower, due to the reduction in the channel current at the

Ioff condition, which lowers IGi and thus ViBSn is reduced (0.36V to 0.24V). The

overshoot condition is enhanced since the gate-to-body coupling can affect the body

voltage for a longer duration given the higher Vt. The drain-to-body coupling

remains the same, except that the coupling of the VBS for the load device terminates

earlier than the nominal technology, since VGS reaches Vt sooner during the input

transitions and removes the inversion layer. The reduction of VBS and the reduced

drive current from the higher Vt combine to degrade the TRO performance of the FB-

Vt/SOI technology, as reflected in Fig. 4.3.







4.5 Scaling SOI: Diminishing Returns?

4.5.1 Scaled SOI CMOS Devices

Via UFSOI simulation, the SOI CMOS technology is scaled to Leff=70nm

consistent with the ITRS [SIA99] technology requirements for the 100nm MPU gate

length node, with the idea of reducing the device dimensions (to reduce the cost per

function) and the power supply (to minimize power increase and high field effects)

while still maintaining the current drive (per unit width) of the prior technology for

improved performance. The Leff=145nm, 1.8V nMOSFET technology was scaled to

the Leff=70nm, 1.2V technology by first thinning the tox (TOXF) from 4.5nm to

2. nm to control short channel effects; the channel doping concentration (NBL) was

then adjusted to maintain a Vt-lin (at IDS=10OnA*WIL) of 0.4V in order to control

Ioff; and the depth (TB) of the retrograded channel was reduced sufficiently less than

the MOSFET's maximum depletion width to maintain the model's validity, but

keeping in mind the trade-off with the subthreshold slope (which degrades as TB is

reduced). The BOX thickness was also reduced to 200nm (consistent with lower cost

wafer trends) and the mobility and source/drain resistances were adjusted to achieve

an appropriate Ion level that was consistent with recently published PD/SOI

technologies [Mis00], [Leo99] at 1.5V. The pMOSFET was scaled in a similar way

as the nMOSFET, with the hole mobility reduced by -0.5x (relative to the electron

mobility) and the source/drain resistance doubled, while maintaining its on-pat

-0.5x of the nMOSFET's Ion-n.







The room-temperature subthreshold IDS-VGS FB device characteristics for

the minimum-Leff (50nm) condition in the scaled technology are shown in Fig. 4.5;

VDD=1.2V, Vt(linear)=0.4V @ IDS=100nA*W/L, tox=2.1nm, tBox=200nm,

tsoi=100nm. Analogous to Fig. 4.2, the predicted bulk-Si (well doping at 1017cm 3),

BTS-SOI, and FB-Vt/SOI (AVtn=ll8mV, AVtp=102mV) characteristics are also

shown in Fig. 4.5. The drive currents at VDD=1.2V (without self-heating) for the

minimum channel length (Leff=50nm) nMOSFETs/pMOSFETs of each technology

are 0.79/0.40 mA/I.m for FB-SOI, 0.71/0.37 mA/gm for FB-Vt/SOI, and 0.65/0.33

mA/gm for BTS-SOI/bulk-Si. Table 4.3 summarizes Ion and Ioff for the minimum-

Leff nMOSFET and pMOSFET for each scaled technology.



Table 4.3 Comparison of Ion and loff of the nominal Leff=70nm devices at the
minimum Leff condition for the scaled MOSFET technologies

Le. ( ) FB/SOI FB-Vt/SOI BTS/SOI, bulk-Si
Leff=50nm (nmin)
1.2V, 270C nMOS pMOS nMOS pMOS nMOS pMOS
Ion (mA/gm) 0.79 0.40 0.71 0.37 0.65 0.33
off (nA/pm) 118 157 4 9 4 9


4.5.2 Performance Comparison

The predicted tsRO performance benefit for the scaled FB/SOI technology

over the scaled bulk-Si counterpart is reduced slightly to 28%, as shown in Fig. 4.6.

The device layouts again assume a 6X based ground rule for the source/drain contact

lengths, with X equal to Lgate/2.0 (Lgate=100nm). However, when Vt is increased

(FB-Vt/SOI) to achieve an equivalent loff as in the bulk-Si technology, the











10-3 .

















Leff (min)=50nm \ *--*FB/SOI
tx = 2.1nm 0 *-- FB-V/SOI
VDS=1.2V *--- FB-IRVt/SOI
108 --A BTS/SOIJbulk-Si


pMOSFET nMOSFET

10-9 I .
-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2
VGS (V)




Figure 4.5 Predicted IDS-VGS for SOI and bulk-Si 70nm technologies.
UFSOI-predicted subthreshold current-voltage characteristics of the minimum
devices (Leff=50nm) for 70nm Lff SOI nMOSFET and pMOSFET
technologies including: FB/SOI, FB-Vt/SOI, FB-IRVt/SOI, BTS/SOI(bulk-si
equivalent DC characteristics); tox=2.lnm, tsoi=100nm, V(inea)=0.4V@IDS
=100nA*W/L, T=270C.









32

bulk-Si

Junction Cap. Benefit
30 BTS/SOI



FB-Vt/SOI
28 Kink Benefit



S -- VDD=1.2V
0 Leff (nom)=70nm
26 Coupling Benefit T=27o0




24 -


FB/SOI

2 2 -I.
10-9 10-8 10-7 10 1-5
Time (s)






Figure 4.6 Predicted delay for SOI and bulk-Si 70nm technologies.
UFSOI-predicted TRO propagation delay for the 70nm Leff technologies.
Lgate=100nm, tox=2.1nm, Vt(inear)=0.4V@ID=100 nA*WIL, T=270C, VDD=
1.2V, Trise/Tfall=100ps, Wp/Wn=32/16, Ls/=6, G/R.







performance benefit of the FB-Vt/SOI technology is significantly reduced to only

6.5%, as summarized in Table 4.4 for the four scaled technologies. The hysteresis is

also predicted to worsen (to 10% from 4.5%) as the technology is scaled, due mainly

to the reduction in the power supply as described in Chapter 3 and [Pel99a].



Table 4.4 Predicted steady-state delay and hysteresis results for the five scaled
Leff=70nm technologies.

Leff=70nm (nom)
VDD=1.2V, T=270C FB/SOI FB-Vt/SOI BTS/SOI bulk-Si
TsRO (ps) 22.4 28.9 29.7 30.9
SOI Benefit over bulk-Si 27.5% 6.5% 3.9%
TRO Hysteresis(ATRo/T'RO) 10% 10.6% --% --%


4.5.3 Loss of SOI Advantage

As the technology is scaled, the performance benefit, as quantified in Fig.

4.6, is predicted to diminish, especially for the Ioff controlled (FB-Vt/SOI)

technology. This is due in part to a lesser gain from the decreased junction

capacitance since the layout ground rules of the source/drain regions are

correspondingly reduced. Moreover, as the areal component of junction capacitance

is reduced, the perimeter component (adjacent to the body region) is increasing due

to the higher doping concentrations in the body and halo implants. This indicates that

the difference between the bulk-Si and the SOI junction capacitances will shrink, and

portends a diminishing performance benefit from the reduction of the junction

capacitance in scaled SOI technologies.







Furthermore, the delay contribution of the capacitive-coupling effect is

reduced to only 5.0% compared to 12% for the contemporary Leff =145nm

technology. The beneficial dynamic loading effect is the predominate component

reduced; this is a result of the reduced output voltage swing, due to the lower supply

voltage, VDD, as can be inferred from the discussions of Fig. 4.4. (These results, in

conjunction with those in Fig. 4.3, clearly show that the main capacitive-coupling

effect is due to the body-drain junction capacitance.) Consequently, the kink-effect

contribution increased to 10% for the scaled FB/SOI technology compared to 5% for

the contemporary technology. This is not a beneficial trade-off since the DC kink

effect typically controls Ioff and is usually suppressed.


4.5.4 Temperature Effects

At elevated ambient temperatures (T=850C), the performance benefit of

the TSSRO delay for the scaled FB/SOI technology is predicted to reduce from 28% to

20% relative to the bulk-Si counterpart technology, as shown in Fig. 4.7. This is due

to the natural amelioration of the FB effect by the increased IR(T) at elevated

temperatures discussed in Chapter 2, which while diminishing the tRO performance

benefit some, helps to suppress the excessive Ioff and hysteresis of the FB/SOI

technology, making it more palatable.

For the scaled FB-Vt/SOI technology at T=850C, with a controlled loff, the

performance benefit increased from 6.5% to 9.9% over an equivalent bulk-Si

technology, with its associated hysteresis reduced by half of the room-temperature

value. This improvement is due to a smaller Vt shift (AVtn=62mV, AVp=46mV









32 1 1 1 l I I I I f o i

bulk-Si




30 BTS/SOI




FB-IRV/SOI \*...

S 28-
28 FB-V/SOI






26

VDD=1.2V
Leff (nom)=70nm
T=850C FBISOI


24 A I I 5 tl l a 1 1,al I J # # fil I I I ... I s
10-9 10- 10-7 10-6 10-5
Time (s)





Figure 4.7 Predicted delay for SOI and bulk-Si 70nm technologies at T=850C.
UFSOI-predicted TRO propagation delay for the scaled Leff=70nm technologies
with the optimized FB-IR/SOI superimposed at elevated ambient temperatures.
Lgate=100nm, tox=2.1nm, Vt(linear)=0.4V@IDs=100nA*W/L, T=850C, VDD=
1.2V, Trise/tfall=100ps, Wp/Wn=32/16, LS/D=6 G/R.







compared to AVtn=118mV, AVtp=102mV at T=270C) that is needed to achieve a

controlled Ioff at elevated temperatures.

If IR is intentionally increased further by 10x (beyond the increase from

the temperature effect), yielding FB-IRVt/SOI (AVtn=36mV, AVtp=24mV), the

performance benefit is maintained at 9.3% while its associated hysteresis is reduced

to a negligible value (only 1.7%), as depicted in Fig. 4.7. The performance results for

the all technologies discussed above at elevated ambient temperatures are

summarized in Table 4.5.



Table 4.5 Predicted steady-state delay and hysteresis results for the five scaled
Leff=70nm technologies at elevated ambient temperatures.

Leff=70nm (nom)
VDD= .2V, T=850C FB/SOI FB-V/SOI FB-IRV/SOI BTS/SOI bulk-Si
TsSRo (ps) 25.1 28.1 28.3 30.0 31.2
SOI Benefit over bulk-Si 19.6% 9.9% 9.3% 3.9% -%
TRO Hysteresis (ARo//1'RO) 6.3% 4.8% 1.7% -% -%


4.6 Increased SOI Advantage: Stacked Logic Gates

The CMOS inverter, which has been studied so far, provides the basic

building block for higher level static logic circuits, e.g., two-input or two-way

NAND (2WNAND), as shown in Fig. 4.8. The stacked (or series-connected

nMOSFETs) nature of 2WNANDs gives rise to an added benefit in SOI technologies

by eliminating the detrimental body-bias (reverse VBS) effects associated with the

top nMOSFET (N2) in bulk-Si technologies. The performance benefit of the scaled

1.2V, Leff=70nm FB SOI CMOS technology with loff controlled (FB-Vt/SOI) is













VDD


P1 P P2
iP A*B


A~~~1 --------^ N
B N2 CL

x T

A N1












Figure 4.8 Schematic of a two-input NAND circuit.
The transistors are labeled P1,P2, N1, and N2; The connecting node of NI and
N2 is labeled as X. The capacitive load is labeled as CL.







investigated, using UFSOI/SPICE, for the three possible switching configurations of

a 2WNAND logic circuit with Wn=Wp (device width ratio is equal to 1): top, bottom,

and simultaneously switching, where the designation refers to the active switching

device of the nMOSFET stack.


4.6.1 Top-Switching Case

The tRO (as obtained from the hysteretic inverter delay methodology

described in Chapter 3 for the 2WNAND circuit) results for the top-switching case

of the 2WNAND circuit (the top nMOSFET (N2) in the stack continuously switches

its logic level while the bottom nMOSFET (N1) maintains a high or "on" level, as

depicted in Table 4.6) are shown in Fig. 4.9. An 11% TSSRO performance benefit for

the FB-Vt/SOI technology over its bulk-Si counterpart is predicted as shown in Fig.

4.9(a); an associated hysteresis of 11% is also predicted. The riRO results indicates



Table 4.6 2WNAND top-switching configuration truth table of Fig. 4.8.
Input: A Input: B Output: KA
1 0 1
1 1 0


that there is no performance benefit during the initial switching cycles of the

2WNAND circuit. This is mainly due to the increased threshold voltage of the FB-

Vt/SOI technology compared to the bulk-si counterpart, suggesting that an

alternative technology or operation at an elevated ambient T should be used if this

part of the delay is vital. The increased performance benefit of the 2WNAND as

compared to the 6.5% inverter benefit is mainly due to the elimination of the reverse

body-bias effect. The floating-body effect also contributes to this performance gain







.1 F. I ..I I I I I I I"F F I F I. I I

37 bulk-Si

36 -

35 -

34 -
FB-V/SOI

10-9 10-8 10-7 10- 10-5
(a)

0.5 -
S0.4 pd-f
S0.3 pd-s
S0.2
Spu -s .........
0.1 p
pu-f

10-9 10-8 10-7 10-6 10-5
(b)
0.5 I

0.4 -

t 0.3 pd-f
0 pd-s
0.2 -
pu-s
S0.1 pu-f

0.0
10-9 10-8 10-7 10-6 10-5
Time (s)

(c)
Figure 4.9 Predicted 2WNAND delay for SOI and bulk-Si 70nm technologies.
UFSOI-predicted top-switching 2WNAND TRO propagation delay analysis for
the scaled Leff=70nm loff controlled (FB-Vt/SOI) technology with its bulk-Si
counterpart superimposed, a) delay versus time, b) corresponding FB-Vt/SOI
top nMOSFET VBs(t) prior to each input transition for each fundamental delay,
and c) corresponding FB-Vt/SOI bottom nMOSFET VBS(t). Lgate=100nm,
tox=2.1nm, Vt(inear)=0.4V @ IDS=100nA*W/L, T=270C, VDD=1.2V, rise/
tfall=100ps, Wp/Wn=32/32, LS/D==6X G/R.




76

but to a lesser extent (mainly through the dynamic-loading effect identified in

Chapter 3), since the charging effects of the floating body are nearly the same.

Although node X (the node connecting the two stacked nMOSFETs (N1 and N2) in

Fig. 4.8) still rises to support the discharge current as in the bulk-Si technology, its

affect on the threshold voltage is overwhelmed by the increased body potential of FB

SOI technology. For each of the fundamental delays described in Chapter 3, the

body-to-source voltages as a function of time for N1 and N2 of the stack are shown

in Figs. 4.9(b) and (c), respectively, which were recorded at time-points just prior to

the input rise and fall transitions. The charging of the floating body in N2 is in accord

with the charging dynamics of the inverter. However, Nlcharges much more slowly

since it is constantly on and hence only charges its body during the output pull-down

transients when node X increases slightly to support the discharge current (or

channel current) that drives impact ionization near the drain.


4.6.2 Bottom-Switching Case

For the bottom-switching case of the 2WNAND circuit (the bottom

nMOSFET in the stack continuously switches its logic level while the top nMOSFET

maintains a high or "on" level, as depicted in Table 4.7), the predicted TsRO

performance benefit of the FB-Vt/SOI technology over its bulk-Si counterpart is

6.9%, as summarized later in Table 4.9, with an associated hysteresis of 5.0%. The



Table 4.7 2WNAND bot-switching configuration truth table of Fig. 4.8.
Input: A Input: B Output: AB
1 1 0
0 1 1







delay-versus-time results are shown in Fig. 4.10(a) superimposed on the top-

switching case results, indicating degraded delay. The reduction in the performance

benefit, compared to the bulk-Si counterpart and the top-switching case, is due in part

to a reduced FB effect in N2 since node X is much higher than in the top-switching

case during the switching transients, as shown in Fig. 4.10(b), and to a lower drain

voltage (VDS-Bot) for N1; the output voltage is divided across both nMOSFETs,

contingent upon their operating region, in the stack, which lowers the drive current.

This causes the body voltage of N2 to drop (or the body discharge) in time, also

weakening its drive current. As a result, the dynamic-loading effect described in

Chapter 3 is much more significant under this switching configuration, which

counters the 'sSRO speedup and reduces the performance gain and its affiliated

hysteresis.


4.6.3 Simultaneously Switching Case

For the simultaneously switching case of the 2WNAND circuit (the top

and bottom nMOSFETs in the stack continuously switch their logic levels at the same

time, as depicted in Table 4.8), the predicted rSSRO performance benefit of the FB-

Vt/SOI technology over its bulk-Si counterpart is 3.2% with an associated hysteresis



Table 4.8 2WNAND simultaneously switching configuration truth table of Fig. 4.8.
Input: A Input: B Output: AB
1 1 0
0 0 1







42


40 Bottom


1 38

( 36 -
0
a Simultaneous
34


32 105
10-9 10- 10-7 106 10
Time (s)
(a)
1.5 -

Input

1.0 Bottom



0.5 l
05 r Simultaneous


0.0



-0.5
Oe+00 5e-10 le-09
Time (s)
(b)
Figure 4.10 Predicted 2WNAND delay for various switching configurations.
UFSOI-predicted 2WNAND TRO propagation delay analysis with Wp/Wn=1 in
the scaled Leff=70nm loff controlled (FB-V/SOI) technology, a) delay versus
time for the top, bottom, and simultaneously switching configurations, b) Vx
node (the node connecting the two stacked nMOSFETs) versus time during the
first input cycle for the three switching configurations. Lgate=100nm, tox=2.1nm,
Vt(linear)=0.4V@IDS= lOOnA*W/L, T=270C, VDD=1.2V, Trise/rfall=1Os, Wp/
Wn=32/32, Ls/D=6X G/R.







of 5.9%. The TRO results, as shown superimposed on Fig. 4.10(a), indicate a

significant speedup in the t'RO delay (compared to the top- and bottom-switching

configurations) which is due to: i) the doubling of the pull-up drive current since both

pMOSFETs are switched on, ii) the moderately charged bodies of the nMOSFETs,

which reduce the body-bias effects as in the other switching cases, and iii) the gate

coupling of node X to a negative voltage (see Fig. 4.10(b)) during the high-to-low

input transitions, which helps to eliminate the transient drain current in the

nMOSFETs (which act as the load during this transition) while the pMOSFETs pull

the output node high. However, as with the bottom-switching case, the lack of

significant charging in the nMOSFETs relative to the pMOSFETs enhances the

dynamic-loading effect and contributes to a reduced rsSRO speedup and hysteresis.

Table 4.9 summarizes the 2WNAND circuit results for all three switching cases.



Table 4.9 Predicted propagation delay and hysteresis results for the three switching
configurations of a 2WNAND circuit.
2WNAND, Wp/Wn=l SOI Benefit SOI
Leff=70nm (nom), bulk-Si FB-Vt/SOI FB-Vt/SOI (TRO-bulk- "RO)/ Hysteresis
VDD=1.2V, T=270C TRO (ps) TRO (ps) TSSRO (ps) TRO-bulk (ATRO/'RO)
Top 37.4 37.4 33.3 11% 11%
Bottom 40.9 40.1 38.1 6.9% 5.0%
Simultaneously 34.8 35.8 33.7 3.2% 5.9%


4.6.4 Device Width Ratio and Temperature Sensitivity

When the device width ratio (Wp/Wn) is altered from 1 (Wn=Wp) to 2

(Wn=Wp/2) or 0.5 (Wn=2Wp), the 2WNAND performance benefit of the FB-Vt/SOI

technology over its bulk-Si counterpart remains about the same (-11%) for all three







cases in the top-switching configuration. The absolute delays (initial and dynamic

steady-state) were the shortest for the Wn=Wp case. Even though the performance

benefit results are nearly the same, the shift in the ratio affects the voltage level of

node X, which influences the dynamic-loading effect and hence the level and time

that each device in the circuit achieves its dynamic steady state. Although there are

noise-margin implications associated with changing the device width ratio, the

nearly constant performance benefit suggests that the circuit layout density may be

improved by using smaller device width ratio, i.e., (Wp = Wn/2).

When the ambient temperature is increased to 850C, increasing IR, the

predicted TSSRO delay for the top-switching case of the 2WNAND circuit with

Wn=Wp is 33.7ps, which is nearly the same as the T=270C case (33.3ps), and the

performance benefit over its bulk-Si counterpart is also the same at 11%. However,

the T'RO delay at T=850C improves by 6.7% to 34.9ps, reducing the hysteresis to only

3.4%. If IR is intentionally increased further (by 10x) along with T=850C, the

predicted tSSRO delay improves to 32.7ps and the 'iRO delay improves to 34.1ps,

while improving the performance benefit over its bulk-Si counterpart to 14%.



4.7 Discussion: Optimization and Future Opportunities

To further enhance the SOI performance benefit of the CMOS inverter

circuit over its bulk-Si counterpart, additional and more aggressive approaches are

considered based on the insight provided in the analyses of the previous sections.







4.7.1 Optimization: Recombination Current and Device Structure

If IR is moderately increased (100x) in conjunction with an increased Vt

(Vin and Vp shifted by 60 and 50mV, respectively) at T=270C, yielding FB-IR100Vt/

SOI with an equivalent Ioff as its bulk-Si counterpart, the CMOS inverter 'SSRO

performance benefit for the scaled technology improves to 9.7%, with its

accompanying hysteresis decreasing from 10.6% to 6.4%. Further, to enhance the

capacitive-coupling effect (single-cycle dynamic loading), which is undermined by

the VDD reduction, tsoI can be adjusted (100nm to 200nm) to increase CDB. The

TFAST (Tpd-f,' pu-f) delays lenghtened or degraded from the reduction of the overshoot

effect due to the stronger drain coupling while the TSLOW (Cpd-s, pu-s) delays

improved from the enhancement of the dynamic-loading effect. Thus, the delay

results show that there is a trade-off between the TFAST and tSLOW delays, which

leads to nearly an unchanged T'R/dSSRo delay and hysteresis.

Alternatively, the asymmetric SOI CMOS design concept described in

Chapter 3 can be employed via modifying the halo or retrograde doping

asymmetrically in either CMOS device to uniquely adjust the dynamic-loading

effect. For example, when the halo/retrograde doping is increased in only the

pMOSFET, the tFAST delays increase while the TSLOW delays decrease, as in the case

for increased tsoI in Chapter 3, while hysteresis tends to be negligible. This also

suggests an added degree of freedom in the device design, which allows a decoupling

of the device structures so that the technology can be designed to fully exploit the

performance benefits of SOI, while simultaneously controlling hysteresis.







4.7.2 Present Benefits

In today's 200nm gate length (Leff=145nm), 1.8V PD/SOI technology, the

expected TssRO performance benefit from the propagation delay of a basic static

CMOS ring-oscillator inverter or a 2WNAND circuit, with controlled Ioff, as

predicted in this study and measured in the literature [Buc20], is about 15-25%. The

main performance contribution is the dynamic-loading effect of the capacitive

coupling, which significantly enhances the TSLOW or second-transition delays of the

tRO delay for the CMOS circuit. The kink and junction capacitance effects contribute

to the overall performance benefit, but to a lesser extent.


4.7.3 Near-Term Future

As the PD/SOI device technology is scaled to 100nm gate lengths

(Leff=70nm) and a VDD=1.2V voltage supply, to improve density and performance

and contain switching power, the performance benefit of a static PD/SOI CMOS

inverter, with controlled Ioff, over the bulk-Si technology is predicted to diminish to

about 6% at T=270C. The reduced power supply of the scaled technology

significantly undermines the dynamic-loading effect, letting the kink effect dominate

the performance benefit. However, the fast signal transitions of high-performance

CMOS gates do not allow the circuits to fully benefit from the kink-effect

enhancement of Ion.

At higher operating temperatures (55-850C), which are typical for high-

performance circuits, the FB effects are naturally suppressed from the increased

IR(T). This relinquishes the amount of FB controlling technique needed for a well

controlled loff, and thus enables the SOI technology to recover some of its







performance advantage over an equivalent bulk-Si technology while significantly

reducing hysteresis as well.

Further, the suppression of the body-bias effects in stacked-transistor

circuits (e.g., NAND, Domino, or CPL) also provides a significant advantage for SOI

technologies over equivalent bulk-Si technologies, even as the technology is scaled,

providing an additional 5-25% [Buc20] performance benefit beyond the intrinsic

CMOS inverter benefit. Additionally, the advantage of an attenuated short-channel

effect (SCE) in PD/SOI technologies [Cro95] will likely enable the device to be

scaled beyond that of conventional bulk-Si technologies, thus providing continued

performance and density benefits.


4.7.4 Future

In light of the diminishing performance benefits for conventional scaled

PD/SOI CMOS, variations of the SOI device structure should be considered to

continue its performance advantage over an equivalent bulk-Si technology,

especially when scaled below Leff=50nm and VDD=1.OV. These alternative device

designs include: body-contacted schemes, (such as, body-tied-to-gate (BTG) SOI),

ultra-thin-film (UTF) fully depleted (FD) SOI, and double-gate (DG) SOI. Another

possible approach to enhance the SOT performance advantage is to lower the ambient

operating temperature of the chip [Tau97], which may allow the exploitation of the

FB effects as the temperature is decreased. Operating PD/SOI MOSFETs at low

ambient temperatures will be investigated in Chapter 5.







4.8 Conclusions

The performance benefit of FB PD/SOI technologies over equivalent bulk-

Si technologies have been evaluated, suggesting a 23% CMOS inverter-based tsRO

advantage with loff controlled (FB-Vt/SOI) for a Leff=145nm, 1.8V technology. The

dynamic-loading effect was shown to predominate the performance advantage of the

1.8V PD/SOI technology. As PD/SOI CMOS technologies are scaled to 70nm

effective channel lengths and a 1.2V power supply, the performance benefit over the

bulk-Si counterpart technology was projected to diminish, mainly due to the lower

power supply reducing the dynamic-loading effect, providing only a 6.5% tSSRO

performance advantage. The kink effect was shown to dominate the performance

advantage for this scaled technology, which is not as effective as the capacitive-

coupling effect since the input signal transition rates are too fast for the device to

fully realize the enhanced DC drive current levels.

However, operation at elevated ambient temperatures is shown to increase

the SOI TSSRO performance advantage to 9.9%. Moreover, by the utilizing unique

optimization techniques (e.g., increased IR) for the scaled PD/SOI device structure,

mitigation of the diminishing performance benefit is shown to be possible, increasing

the SOI performance advantage to near 10% with a suppressed hysteresis effect.

Furthermore, by employing the asymmetric SOI CMOS design concept, the

fundamental delays and their associated hysteresis can be improved per specific

applications within a given technology. In addition, by exploiting stacked-transistor

logic circuits an additional 5-25% performance benefit can be expected. For the three

switching configurations of the 2WNAND inverter investigated, the top-switching







case offers the

simultaneously

simultaneously

hysteresis.


greatest performance benefit over its bulk-Si counterpart, with the

switching case providing the least benefit. However, the

switching case provides the shortest T'RO with the smallest associated


Alternative or more aggressive optimization approaches can increase the

performance benefit of PD/SOI technologies, but not generally since there are trade-

offs for a given fundamental delay. Exploring aggressive techniques to increase IR,

implementing the asymmetric SOI CMOS design concept, and exploiting the

capacitive-coupling (or single-cycle dynamic-loading) effect will provide design

flexibility while optimizing the delay performance for a given application.












CHAPTER 5
PD/SOI MOSFETS AT LOW TEMPERATURE


5.1 Introduction

One option to counter the slowing CMOS scaling trend [SIA99] is to

reduce the ambient temperature (T) of the semiconductor chip. At low operating T,

increased carrier mobility, subthreshold slope, and threshold voltage (Vt) have been

demonstrated for bulk-Si MOSFETs [Sun87], as exemplified in Fig. 5.1, thus

lowering off-state current, enhancing drive current, allowing lower-Vt design, and

providing significant improvement in the speed-power performance of the

technology, especially for the same-off-current T-scaling scenario [Tau97]. In this

chapter, the behavior of floating-body (FB) partially depleted (PD) SOI CMOS is

evaluated at low T down to -1000C, which reflects a practical range of operating

temperature subject to the cost of the required cooling system. The results show that

the negative T-coefficient of the FB voltage VBs(T), described in Chapter 2, can lead

to activation of the parasitic bipolar transistor (BJT), inducing an anomalous

subthreshold current characteristic as T is reduced. They further reveal an increasing

off-state current (loff), below a critical T, which implies a possible limit to the low-

T operating range of FB PD/SOI CMOS. However, device design optimization is

shown to ameliorate this low-T bipolar effect, enabling a lower-T operating range

and a significantly enhanced circuit performance. The results also reveal that, as T is


















10"3
10-4 VDS=1.5V '"
10 abulk-Si
10 Len=70nm 0.05V
10"6


ST=85C T=-1000C

^ i10o-
10-10

10-14

10 "3


10-15 .
-1.0 -0.5 0.0 0.5 1.0 1.5
VGS (V)






Figure 5.1 Predicted IDS-VGS for bulk-Si as a function of T
UFSOI-predicted saturated subthreshold IDS-VGS as a function of T, exemplifying
increased carrier mobility, subthreshold slope, and threshold voltage at low
temperatures, for a bulk-Si technology. (Lgate=100nm, Leff=70nm, tox=2.1nm,
Vt(lin)= O.4V @ IDS= 00nA*W/L @ T=270C)




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